STM32F373xC HAL User Manual: STM32F3xx HAL Drivers

STM32F373xC HAL User Manual
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STM32F3xx HAL Drivers

HAL Drivers User Manual

This document contains the User Manual (UM) of the STM32F373xC HAL (Hardware Abstraction Layer) drivers.

Document tabsheets description:

  • "Modules" : List the different modules.
  • "Files" : List all the files and globals.
  • "Directories" : Firmware Directory hierarchy.
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC

  • Data Structures
  • Files
  • Directories
Modules
ADC
STM32F3xx_LL_Driver

Modules

ADC Private Constants
ADC Private Macros
ADC Exported Init structure
ADC Exported Constants
ADC Exported Macros
ADC Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for ADC registers.

Register | Bit | Function
CR1 | AWD1CH | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
 | AWD1EN | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
 | AWD1SGL | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
 | AWDIE | LL_ADC_EnableIT_AWD1
 | DISCEN | LL_ADC_INJ_SetSequencerDiscont
 |  | LL_ADC_REG_GetSequencerDiscont
 |  | LL_ADC_REG_SetSequencerDiscont
 | DISCNUM | LL_ADC_REG_GetSequencerDiscont
 |  | LL_ADC_REG_SetSequencerDiscont
 | EOCIE | LL_ADC_DisableIT_EOS
 |  | LL_ADC_EnableIT_EOS
 |  | LL_ADC_IsEnabledIT_EOS
 | JAUTO | LL_ADC_INJ_GetTrigAuto
 |  | LL_ADC_INJ_SetTrigAuto
 | JEOCIE | LL_ADC_EnableIT_JEOS
 | SCAN | LL_ADC_GetSequencersScanMode
 |  | LL_ADC_SetSequencersScanMode
CR2 | ADON | LL_ADC_Disable
 |  | LL_ADC_Enable
 |  | LL_ADC_IsEnabled
 | ALIGN | LL_ADC_SetDataAlignment
 | CAL | LL_ADC_IsCalibrationOnGoing
 |  | LL_ADC_StartCalibration
 | CONT | LL_ADC_REG_GetContinuousMode
 |  | LL_ADC_REG_SetContinuousMode
 | DMA | LL_ADC_REG_GetDMATransfer
 |  | LL_ADC_REG_SetDMATransfer
 | EXTSEL | LL_ADC_REG_GetTriggerSource
 |  | LL_ADC_REG_IsTriggerSourceSWStart
 |  | LL_ADC_REG_SetTriggerSource
 |  | LL_ADC_REG_StopConversionExtTrig
 | EXTTRIG | LL_ADC_REG_StartConversion
 | JEXTSEL | LL_ADC_INJ_GetTriggerSource
 |  | LL_ADC_INJ_IsTriggerSourceSWStart
 |  | LL_ADC_INJ_SetTriggerSource
 |  | LL_ADC_INJ_StopConversionExtTrig
 | JEXTTRIG | LL_ADC_REG_StartConversion
 | TSVREFE | LL_ADC_GetCommonPathInternalCh
 |  | LL_ADC_SetCommonPathInternalCh
DR | DATA | LL_ADC_DMA_GetRegAddr
 | RDATA | LL_ADC_REG_ReadConversionData12
 |  | LL_ADC_REG_ReadConversionData32
HTR | HT | LL_ADC_GetAnalogWDThresholds
 |  | LL_ADC_SetAnalogWDThresholds
JDR1 | JDATA | LL_ADC_INJ_ReadConversionData12
 |  | LL_ADC_INJ_ReadConversionData32
JDR2 | JDATA | LL_ADC_INJ_ReadConversionData12
 |  | LL_ADC_INJ_ReadConversionData32
JDR3 | JDATA | LL_ADC_INJ_ReadConversionData12
 |  | LL_ADC_INJ_ReadConversionData32
JDR4 | JDATA | LL_ADC_INJ_ReadConversionData12
 |  | LL_ADC_INJ_ReadConversionData32
JOFR1 | JOFFSET1 | LL_ADC_INJ_GetOffset
 |  | LL_ADC_INJ_SetOffset
JOFR2 | JOFFSET2 | LL_ADC_INJ_GetOffset
 |  | LL_ADC_INJ_SetOffset
JOFR3 | JOFFSET3 | LL_ADC_INJ_GetOffset
 |  | LL_ADC_INJ_SetOffset
JOFR4 | JOFFSET4 | LL_ADC_INJ_GetOffset
 |  | LL_ADC_INJ_SetOffset
JSQR | JL | LL_ADC_INJ_GetSequencerLength
 |  | LL_ADC_INJ_SetSequencerLength
 | JSQ1 | LL_ADC_INJ_SetSequencerRanks
 | JSQ2 | LL_ADC_INJ_SetSequencerRanks
 | JSQ3 | LL_ADC_INJ_SetSequencerRanks
 | JSQ4 | LL_ADC_INJ_SetSequencerRanks
LTR | LT | LL_ADC_GetAnalogWDThresholds
 |  | LL_ADC_SetAnalogWDThresholds
SMPR1 | SMP10 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP11 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP12 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP13 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP14 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP15 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP16 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP17 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
SMPR2 | SMP0 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP1 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP2 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP3 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP4 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP5 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP6 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP7 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP8 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP9 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
SQR1 | L | LL_ADC_REG_SetSequencerLength
 | SQ13 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ14 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ15 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ16 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
SQR2 | SQ10 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ11 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ12 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ7 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ8 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ9 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
SQR3 | SQ1 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ2 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ3 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ4 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ5 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ6 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
SR | AWD | LL_ADC_ClearFlag_AWD1
 |  | LL_ADC_IsActiveFlag_AWD1
 | EOC | LL_ADC_ClearFlag_EOS
 |  | LL_ADC_IsActiveFlag_EOS
 | JEOC | LL_ADC_ClearFlag_JEOS
 |  | LL_ADC_IsActiveFlag_JEOS
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Private Constants

Defines
ADC Private Constants
ADC

Defines

#define | ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)
#define | ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)
#define | ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)
#define | ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
#define | ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
#define | ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
#define | ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
#define | ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
#define | ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
#define | ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
#define | ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
#define | ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
#define | ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
#define | ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
#define | ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
#define | ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
#define | ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
#define | ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
#define | ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
#define | ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
#define | ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)
#define | ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)
#define | ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)
#define | ADC_JOFR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_JOFR2_REGOFFSET ((uint32_t)0x00001000U)
#define | ADC_JOFR3_REGOFFSET ((uint32_t)0x00002000U)
#define | ADC_JOFR4_REGOFFSET ((uint32_t)0x00003000U)
#define | ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
#define | ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
#define | ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
#define | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
#define | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
#define | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
#define | ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
#define | ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t) 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
#define | ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
#define | ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
#define | ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */
#define | ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x40000000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define | ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
#define | ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)
#define | ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
#define | ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)
#define | ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
#define | ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
#define | ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
#define | ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
#define | ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
#define | ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
#define | ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
#define | ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
#define | ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
#define | ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
#define | ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
#define | ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
#define | ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
#define | ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
#define | ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
#define | ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
#define | ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
#define | ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
#define | ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
#define | ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
#define | ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
#define | ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
#define | ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
#define | ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
#define | ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
#define | ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
#define | ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
#define | ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
#define | ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
#define | ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
#define | ADC_AWD_TR1_HIGH_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_AWD_TR1_LOW_REGOFFSET ((uint32_t)0x00000001U)
#define | ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
#define | ADC_CR1_DUALMOD_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */
#define | VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define | VREFINT_CAL_VREF ((uint32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
#define | TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F37x, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F37x, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */

Define Documentation

#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

Definition at line 7455 of file stm32f3xx_ll_adc.h.

#define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)

Definition at line 7451 of file stm32f3xx_ll_adc.h.

#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)

Definition at line 7456 of file stm32f3xx_ll_adc.h.

#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)

Definition at line 7453 of file stm32f3xx_ll_adc.h.

#define ADC_AWD_TR1_HIGH_REGOFFSET ((uint32_t)0x00000000U)

Definition at line 7459 of file stm32f3xx_ll_adc.h.

#define ADC_AWD_TR1_LOW_REGOFFSET ((uint32_t)0x00000001U)

Definition at line 7460 of file stm32f3xx_ll_adc.h.

#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)

Definition at line 7461 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)

Definition at line 7402 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */

Definition at line 7423 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )

Definition at line 7412 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */

Definition at line 7433 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

Definition at line 7413 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */

Definition at line 7434 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )

Definition at line 7414 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */

Definition at line 7435 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)

Definition at line 7415 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */

Definition at line 7436 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )

Definition at line 7416 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */

Definition at line 7437 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

Definition at line 7417 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */

Definition at line 7438 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )

Definition at line 7418 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */

Definition at line 7439 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)

Definition at line 7419 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */

Definition at line 7440 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)

Definition at line 7403 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */

Definition at line 7424 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )

Definition at line 7404 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */

Definition at line 7425 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

Definition at line 7405 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */

Definition at line 7426 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )

Definition at line 7406 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */

Definition at line 7427 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)

Definition at line 7407 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */

Definition at line 7428 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )

Definition at line 7408 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */

Definition at line 7429 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

Definition at line 7409 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */

Definition at line 7430 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )

Definition at line 7410 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */

Definition at line 7431 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)

Definition at line 7411 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */

Definition at line 7432 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */

Definition at line 7387 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x40000000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */

Definition at line 7388 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)

Definition at line 7389 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)

Definition at line 7382 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t) 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */

Definition at line 7381 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)

Definition at line 7380 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */

Definition at line 7384 of file stm32f3xx_ll_adc.h.

#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)

Definition at line 7395 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)

Definition at line 7397 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */

Definition at line 7398 of file stm32f3xx_ll_adc.h.

#define ADC_CR1_DUALMOD_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */

Definition at line 7465 of file stm32f3xx_ll_adc.h.

#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)

Definition at line 7360 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_INJ_ReadConversionData12(), and LL_ADC_INJ_ReadConversionData32().

#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)

Definition at line 7361 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_INJ_GetOffset(), and LL_ADC_INJ_SetOffset().

#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */

Definition at line 7366 of file stm32f3xx_ll_adc.h.

#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */

Definition at line 7367 of file stm32f3xx_ll_adc.h.

#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */

Definition at line 7368 of file stm32f3xx_ll_adc.h.

#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */

Definition at line 7369 of file stm32f3xx_ll_adc.h.

#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

Definition at line 7362 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_INJ_GetSequencerRanks(), and LL_ADC_INJ_SetSequencerRanks().

#define ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)

Definition at line 7348 of file stm32f3xx_ll_adc.h.

#define ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)

Definition at line 7349 of file stm32f3xx_ll_adc.h.

#define ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)

Definition at line 7350 of file stm32f3xx_ll_adc.h.

#define ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)

Definition at line 7351 of file stm32f3xx_ll_adc.h.

#define ADC_JOFR1_REGOFFSET ((uint32_t)0x00000000U)

Definition at line 7355 of file stm32f3xx_ll_adc.h.

#define ADC_JOFR2_REGOFFSET ((uint32_t)0x00001000U)

Definition at line 7356 of file stm32f3xx_ll_adc.h.

#define ADC_JOFR3_REGOFFSET ((uint32_t)0x00002000U)

Definition at line 7357 of file stm32f3xx_ll_adc.h.

#define ADC_JOFR4_REGOFFSET ((uint32_t)0x00003000U)

Definition at line 7358 of file stm32f3xx_ll_adc.h.

#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */

Definition at line 7330 of file stm32f3xx_ll_adc.h.

#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */

Definition at line 7331 of file stm32f3xx_ll_adc.h.

#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */

Definition at line 7332 of file stm32f3xx_ll_adc.h.

#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */

Definition at line 7333 of file stm32f3xx_ll_adc.h.

#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */

Definition at line 7334 of file stm32f3xx_ll_adc.h.

#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */

Definition at line 7335 of file stm32f3xx_ll_adc.h.

#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */

Definition at line 7336 of file stm32f3xx_ll_adc.h.

#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */

Definition at line 7321 of file stm32f3xx_ll_adc.h.

#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */

Definition at line 7322 of file stm32f3xx_ll_adc.h.

#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */

Definition at line 7323 of file stm32f3xx_ll_adc.h.

#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */

Definition at line 7324 of file stm32f3xx_ll_adc.h.

#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */

Definition at line 7325 of file stm32f3xx_ll_adc.h.

#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */

Definition at line 7326 of file stm32f3xx_ll_adc.h.

#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */

Definition at line 7327 of file stm32f3xx_ll_adc.h.

#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */

Definition at line 7328 of file stm32f3xx_ll_adc.h.

#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */

Definition at line 7329 of file stm32f3xx_ll_adc.h.

#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

Definition at line 7317 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks().

#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)

Definition at line 7316 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)

Definition at line 7393 of file stm32f3xx_ll_adc.h.

#define ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)

Definition at line 7394 of file stm32f3xx_ll_adc.h.

#define ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)

Definition at line 7311 of file stm32f3xx_ll_adc.h.

#define ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)

Definition at line 7312 of file stm32f3xx_ll_adc.h.

#define ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)

Definition at line 7313 of file stm32f3xx_ll_adc.h.

#define ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)

Definition at line 7314 of file stm32f3xx_ll_adc.h.

#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F37x, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

Definition at line 7473 of file stm32f3xx_ll_adc.h.

#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */

Definition at line 7475 of file stm32f3xx_ll_adc.h.

#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F37x, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

Definition at line 7474 of file stm32f3xx_ll_adc.h.

#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */

Definition at line 7476 of file stm32f3xx_ll_adc.h.

#define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */

Definition at line 7477 of file stm32f3xx_ll_adc.h.

#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

Definition at line 7470 of file stm32f3xx_ll_adc.h.

#define VREFINT_CAL_VREF ((uint32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */

Definition at line 7471 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Private Macros

Defines
ADC Private Macros
ADC

Defines

#define | IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)
#define | IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__)
#define | IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__)
#define | IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)
#define | IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)
#define | IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)
#define | IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)
#define | IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)
#define | __ADC_MASK_SHIFT(__BITS__, __MASK__) (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).
#define | __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Define Documentation

#define __ADC_MASK_SHIFT | ( | __BITS__,
 |  | __MASK__
 | ) | (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))

Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).

Parameters:
__BITS__ | Bits in register 32 bits
__MASK__ | Mask in register 32 bits
Return values:
Bits in register 32 bits

Definition at line 7498 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), LL_ADC_INJ_GetOffset(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData32(), LL_ADC_INJ_SetOffset(), LL_ADC_REG_GetSequencerRanks(), LL_ADC_REG_SetSequencerRanks(), and LL_ADC_SetChannelSamplingTime().

#define __ADC_PTR_REG_OFFSET | ( | __REG__,
 |  | __REG_OFFFSET__
 | ) | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))

Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Parameters:
__REG__ | Register basis from which the offset is applied.
__REG_OFFFSET__ | Offset to be applied (unit: number of registers).
Return values:
Pointer to register address

Definition at line 7509 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDThresholds(), LL_ADC_GetChannelSamplingTime(), LL_ADC_INJ_GetOffset(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData32(), LL_ADC_INJ_SetOffset(), LL_ADC_REG_GetSequencerRanks(), LL_ADC_REG_SetSequencerRanks(), LL_ADC_SetAnalogWDThresholds(), and LL_ADC_SetChannelSamplingTime().

#define IS_LL_ADC_DATA_ALIGN ( __DATA_ALIGN__ )
Value:
(   ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                            \
   || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) )

Definition at line 1392 of file stm32f3xx_ll_adc.c.

Referenced by LL_ADC_Init().

#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE ( __INJ_SEQ_DISCONT_MODE__ )
Value:
(   ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)           \
   || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)  )

Definition at line 1475 of file stm32f3xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH ( __INJ_SEQ_SCAN_LENGTH__ )
Value:
(   ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)               \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS))

Definition at line 1469 of file stm32f3xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_TRIG_AUTO ( __INJ_TRIG_AUTO__ )
Value:
(   ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                     \
   || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR))

Definition at line 1465 of file stm32f3xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_TRIG_SOURCE ( __INJ_TRIG_SOURCE__ )
Value:
(   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM19_CH1)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM19_CH2)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15))

Definition at line 1455 of file stm32f3xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_REG_CONTINUOUS_MODE ( __REG_CONTINUOUS_MODE__ )
Value:
(   ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                    \
   || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS))

Definition at line 1416 of file stm32f3xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_DMA_TRANSFER ( __REG_DMA_TRANSFER__ )
Value:
(   ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                 \
   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED))

Definition at line 1420 of file stm32f3xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE ( __REG_SEQ_DISCONT_MODE__ )
Value:
(   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) )

Definition at line 1442 of file stm32f3xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH ( __REG_SEQ_SCAN_LENGTH__ )
Value:
(   ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)               \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS))

Definition at line 1424 of file stm32f3xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_TRIG_SOURCE ( __REG_TRIG_SOURCE__ )
Value:
(   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH2)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_TRGO)                \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_CH3)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_CH4)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11))

Definition at line 1406 of file stm32f3xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_SCAN_SELECTION ( __SCAN_SELECTION__ )
Value:
(   ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE)                        \
   || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) )

Definition at line 1396 of file stm32f3xx_ll_adc.c.

Referenced by LL_ADC_Init().

#define IS_LL_ADC_SEQ_SCAN_MODE ( __SEQ_SCAN_MODE__ )
Value:
(   ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE)                             \
   || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) )

Definition at line 1400 of file stm32f3xx_ll_adc.c.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_ADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC instance. More...

#include <stm32f3xx_ll_adc.h>

Data Fields

uint32_t | DataAlignment
uint32_t | SequencersScanMode

Detailed Description

Structure definition of some features of ADC instance.

Note:
These parameters have an impact on ADC scope: ADC instance. Affects both group regular and group injected (availability of ADC group injected depends on STM32 families). Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: ADC instance .
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 7543 of file stm32f3xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_InitTypeDef::DataAlignment

Set ADC conversion data alignment. This parameter can be a value of ADC instance - Data alignment

This feature can be modified afterwards using unitary function LL_ADC_SetDataAlignment().

Definition at line 7545 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

uint32_t LL_ADC_InitTypeDef::SequencersScanMode

Set ADC scan selection. This parameter can be a value of ADC instance - Scan selection

This feature can be modified afterwards using unitary function LL_ADC_SetSequencersScanMode().

Definition at line 7550 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_adc.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_ADC_REG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_REG_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC group regular. More...

#include <stm32f3xx_ll_adc.h>

Data Fields

uint32_t | TriggerSource
uint32_t | SequencerLength
uint32_t | SequencerDiscont
uint32_t | ContinuousMode
uint32_t | DMATransfer

Detailed Description

Structure definition of some features of ADC group regular.

Note:
These parameters have an impact on ADC scope: ADC group regular. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "REG").
The setting of these parameters by function LL_ADC_REG_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 7576 of file stm32f3xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_REG_InitTypeDef::ContinuousMode

Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). This parameter can be a value of ADC group regular - Continuous mode Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.

This feature can be modified afterwards using unitary function LL_ADC_REG_SetContinuousMode().

Definition at line 7598 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::DMATransfer

Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. This parameter can be a value of ADC group regular - DMA transfer

This feature can be modified afterwards using unitary function LL_ADC_REG_SetDMATransfer().

Definition at line 7604 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::SequencerDiscont

Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of ADC group regular - Sequencer discontinuous mode

Note:
This parameter has an effect only if group regular sequencer is enabled (scan length of 2 ranks or more).

This feature can be modified afterwards using unitary function LL_ADC_REG_SetSequencerDiscont().

Definition at line 7591 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::SequencerLength

Set ADC group regular sequencer length. This parameter can be a value of ADC group regular - Sequencer scan length

Note:
This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').

This feature can be modified afterwards using unitary function LL_ADC_REG_SetSequencerLength().

Definition at line 7585 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::TriggerSource

Set ADC group regular conversion trigger source: internal (SW start) or external from timer or external interrupt. This parameter can be a value of ADC group regular - Trigger source

Note:
On this STM32 serie, external trigger is set with trigger polarity: rising edge (only trigger polarity available on this STM32 serie).

This feature can be modified afterwards using unitary function LL_ADC_REG_SetTriggerSource().

Definition at line 7578 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_adc.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_ADC_INJ_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_INJ_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC group injected. More...

#include <stm32f3xx_ll_adc.h>

Data Fields

uint32_t | TriggerSource
uint32_t | SequencerLength
uint32_t | SequencerDiscont
uint32_t | TrigAuto

Detailed Description

Structure definition of some features of ADC group injected.

Note:
These parameters have an impact on ADC scope: ADC group injected. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "INJ").
The setting of these parameters by function LL_ADC_INJ_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 7630 of file stm32f3xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_INJ_InitTypeDef::SequencerDiscont

Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of ADC group injected - Sequencer discontinuous mode

Note:
This parameter has an effect only if group injected sequencer is enabled (scan length of 2 ranks or more).

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetSequencerDiscont().

Definition at line 7645 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::SequencerLength

Set ADC group injected sequencer length. This parameter can be a value of ADC group injected - Sequencer scan length

Note:
This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetSequencerLength().

Definition at line 7639 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::TrigAuto

Set ADC group injected conversion trigger: independent or from ADC group regular. This parameter can be a value of ADC group injected - Automatic trigger mode Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetTrigAuto().

Definition at line 7652 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::TriggerSource

Set ADC group injected conversion trigger source: internal (SW start) or external from timer or external interrupt. This parameter can be a value of ADC group injected - Trigger source

Note:
On this STM32 serie, external trigger is set with trigger polarity: rising edge (only trigger polarity available on this STM32 serie).

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetTriggerSource().

Definition at line 7632 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_adc.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC flags

Defines
ADC flags
ADC Exported Constants

Flags defines which can be used with LL_ADC_ReadReg function. More...

Defines

#define | LL_ADC_FLAG_STRT ADC_SR_STRT
#define | LL_ADC_FLAG_EOS ADC_SR_EOC
#define | LL_ADC_FLAG_JSTRT ADC_SR_JSTRT
#define | LL_ADC_FLAG_JEOS ADC_SR_JEOC
#define | LL_ADC_FLAG_AWD1 ADC_SR_AWD

Detailed Description

Flags defines which can be used with LL_ADC_ReadReg function.

Define Documentation

#define LL_ADC_FLAG_AWD1 ADC_SR_AWD

ADC flag ADC analog watchdog 1

Definition at line 7678 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_AWD1(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_AWD1().

#define LL_ADC_FLAG_EOS ADC_SR_EOC

ADC flag ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families)

Definition at line 7675 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOS(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_EOS().

#define LL_ADC_FLAG_JEOS ADC_SR_JEOC

ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families)

Definition at line 7677 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_JEOS(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_JEOS().

#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT

ADC flag ADC group injected conversion start

Definition at line 7676 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

#define LL_ADC_FLAG_STRT ADC_SR_STRT

ADC flag ADC group regular conversion start

Definition at line 7674 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC interruptions for configuration (interruption enable or disable)

Defines
ADC interruptions for configuration (interruption enable or disable)
ADC Exported Constants

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions. More...

Defines

#define | LL_ADC_IT_EOS ADC_CR1_EOCIE
#define | LL_ADC_IT_JEOS ADC_CR1_JEOCIE
#define | LL_ADC_IT_AWD1 ADC_CR1_AWDIE

Detailed Description

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions.

Define Documentation

#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE

ADC interruption ADC analog watchdog 1

Definition at line 7689 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_DisableIT_AWD1(), LL_ADC_EnableIT_AWD1(), and LL_ADC_IsEnabledIT_AWD1().

#define LL_ADC_IT_EOS ADC_CR1_EOCIE

ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families)

Definition at line 7687 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_IsEnabledIT_EOS().

#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE

ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families)

Definition at line 7688 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_DisableIT_JEOS(), LL_ADC_EnableIT_JEOS(), and LL_ADC_IsEnabledIT_JEOS().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC registers compliant with specific purpose

Defines
ADC registers compliant with specific purpose
ADC Exported Constants

Defines

#define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */

Define Documentation

#define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */

Definition at line 7700 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC common - Measurement path to internal channels

Defines
ADC common - Measurement path to internal channels
ADC Exported Constants

Defines

#define | LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)
#define | LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE)
#define | LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE)

Define Documentation

#define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)

ADC measurement pathes all disabled

Definition at line 7713 of file stm32f3xx_ll_adc.h.

#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE)

ADC measurement path to internal channel temperature sensor

Definition at line 7715 of file stm32f3xx_ll_adc.h.

#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE)

ADC measurement path to internal channel VrefInt

Definition at line 7714 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC instance - Resolution

Defines
ADC instance - Resolution
ADC Exported Constants

Defines

#define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U)

Define Documentation

#define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U)

ADC resolution 12 bits

Definition at line 7723 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC instance - Data alignment

Defines
ADC instance - Data alignment
ADC Exported Constants

Defines

#define | LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)
#define | LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN)

Define Documentation

#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN)

ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)

Definition at line 7732 of file stm32f3xx_ll_adc.h.

#define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)

ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)

Definition at line 7731 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_StructInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC instance - Scan selection

Defines
ADC instance - Scan selection
ADC Exported Constants

Defines

#define | LL_ADC_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_SEQ_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)

Define Documentation

#define LL_ADC_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U)

ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.

Definition at line 7740 of file stm32f3xx_ll_adc.h.

#define LL_ADC_SEQ_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)

ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...).

Definition at line 7741 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_StructInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC instance - Groups

Defines
ADC instance - Groups
ADC Exported Constants

Defines

#define | LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U)
#define | LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U)
#define | LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U)

Define Documentation

#define LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U)

ADC group injected (not available on all STM32 devices)

Definition at line 7750 of file stm32f3xx_ll_adc.h.

#define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U)

ADC group regular (available on all STM32 devices)

Definition at line 7749 of file stm32f3xx_ll_adc.h.

#define LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U)

ADC both groups regular and injected

Definition at line 7751 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC instance - Channel number

Defines
ADC instance - Channel number
ADC Exported Constants

Defines

#define | LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP)
#define | LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP)
#define | LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP)
#define | LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP)
#define | LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP)
#define | LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP)
#define | LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP)
#define | LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP)
#define | LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP)
#define | LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP)
#define | LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP)
#define | LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP)
#define | LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP)
#define | LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP)
#define | LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP)
#define | LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP)
#define | LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP)
#define | LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP)
#define | LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)

Define Documentation

#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN0

Definition at line 7759 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN1

Definition at line 7760 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN10

Definition at line 7769 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN11

Definition at line 7770 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN12

Definition at line 7771 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN13

Definition at line 7772 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN14

Definition at line 7773 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN15

Definition at line 7774 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN16

Definition at line 7775 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN17

Definition at line 7776 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN2

Definition at line 7761 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN3

Definition at line 7762 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN4

Definition at line 7763 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN5

Definition at line 7764 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN6

Definition at line 7765 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN7

Definition at line 7766 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN8

Definition at line 7767 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN9

Definition at line 7768 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to Temperature sensor.

Definition at line 7778 of file stm32f3xx_ll_adc.h.

#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F37x, ADC channel available only on ADC instance: ADC1.

Definition at line 7777 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC group regular - Trigger source

Defines
ADC group regular - Trigger source
ADC Exported Constants

Defines

#define | LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)
#define | LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)
#define | LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2)
#define | LL_ADC_REG_TRIG_EXT_TIM4_CH2 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)
#define | LL_ADC_REG_TRIG_EXT_TIM19_TRGO ((uint32_t)0x00000000U)
#define | LL_ADC_REG_TRIG_EXT_TIM19_CH3 (ADC_CR2_EXTSEL_0)
#define | LL_ADC_REG_TRIG_EXT_TIM19_CH4 (ADC_CR2_EXTSEL_1)
#define | LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)

Define Documentation

#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)

ADC group regular conversion trigger external interrupt line 11. Trigger edge set to rising edge (default setting).

Definition at line 7793 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM19_CH3 (ADC_CR2_EXTSEL_0)

ADC group regular conversion trigger external from TIM19 CC3. Trigger edge set to rising edge (default setting).

Definition at line 7791 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM19_CH4 (ADC_CR2_EXTSEL_1)

ADC group regular conversion trigger external from TIM19 CC4. Trigger edge set to rising edge (default setting).

Definition at line 7792 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM19_TRGO ((uint32_t)0x00000000U)

ADC group regular conversion trigger external from TIM19 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 7790 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)

ADC group regular conversion trigger external from TIM2 CC2. Trigger edge set to rising edge (default setting).

Definition at line 7787 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2)

ADC group regular conversion trigger external from TIM3 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 7788 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM4_CH2 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)

ADC group regular conversion trigger external from TIM4 CC4. Trigger edge set to rising edge (default setting).

Definition at line 7789 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)

ADC group regular conversion trigger internal (SW start)

Definition at line 7786 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_REG_IsTriggerSourceSWStart(), and LL_ADC_REG_StructInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC group regular - Trigger edge

Defines
ADC group regular - Trigger edge
ADC Exported Constants

Defines

#define LL_ADC_REG_TRIG_EXT_RISING ((uint32_t)0x00000000U)

Define Documentation

#define LL_ADC_REG_TRIG_EXT_RISING ((uint32_t)0x00000000U)

ADC group regular conversion trigger polarity set to rising edge

Definition at line 7801 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC group regular - Continuous mode

Defines
ADC group regular - Continuous mode
ADC Exported Constants

Defines

#define | LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT)

Define Documentation

#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT)

ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically

Definition at line 7810 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U)

ADC conversions are performed in single mode: one conversion per trigger

Definition at line 7809 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_REG_StructInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC group regular - DMA transfer

Defines
ADC group regular - DMA transfer
ADC Exported Constants

Defines

#define | LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA)

Define Documentation

#define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U)

ADC conversions are not transferred by DMA

Definition at line 7818 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_REG_StructInit().

#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA)

ADC conversions are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.

Definition at line 7819 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC group regular - Sequencer scan length

Defines
ADC group regular - Sequencer scan length
ADC Exported Constants

Defines

#define | LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

Define Documentation

#define LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U)

ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel)

Definition at line 7827 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 10 ranks in the sequence

Definition at line 7836 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )

ADC group regular sequencer enable with 11 ranks in the sequence

Definition at line 7837 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 12 ranks in the sequence

Definition at line 7838 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )

ADC group regular sequencer enable with 13 ranks in the sequence

Definition at line 7839 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 14 ranks in the sequence

Definition at line 7840 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )

ADC group regular sequencer enable with 15 ranks in the sequence

Definition at line 7841 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 16 ranks in the sequence

Definition at line 7842 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)

ADC group regular sequencer enable with 2 ranks in the sequence

Definition at line 7828 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )

ADC group regular sequencer enable with 3 ranks in the sequence

Definition at line 7829 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 4 ranks in the sequence

Definition at line 7830 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )

ADC group regular sequencer enable with 5 ranks in the sequence

Definition at line 7831 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 6 ranks in the sequence

Definition at line 7832 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )

ADC group regular sequencer enable with 7 ranks in the sequence

Definition at line 7833 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 8 ranks in the sequence

Definition at line 7834 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )

ADC group regular sequencer enable with 9 ranks in the sequence

Definition at line 7835 of file stm32f3xx_ll_adc.h.

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STM32F373xC HAL User Manual: ADC group regular - Sequencer discontinuous mode

Defines
ADC group regular - Sequencer discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)

Define Documentation

#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every rank

Definition at line 7851 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks

Definition at line 7852 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks

Definition at line 7853 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks

Definition at line 7854 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks

Definition at line 7855 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks

Definition at line 7856 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks

Definition at line 7857 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks

Definition at line 7858 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)

ADC group regular sequencer discontinuous mode disable

Definition at line 7850 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC group regular - Sequencer ranks

Defines
ADC group regular - Sequencer ranks
ADC Exported Constants

Defines

#define | LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)

Define Documentation

#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 1

Definition at line 7866 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 10

Definition at line 7875 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 11

Definition at line 7876 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 12

Definition at line 7877 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 13

Definition at line 7878 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 14

Definition at line 7879 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 15

Definition at line 7880 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 16

Definition at line 7881 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 2

Definition at line 7867 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 3

Definition at line 7868 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 4

Definition at line 7869 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 5

Definition at line 7870 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 6

Definition at line 7871 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 7

Definition at line 7872 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 8

Definition at line 7873 of file stm32f3xx_ll_adc.h.

#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 9

Definition at line 7874 of file stm32f3xx_ll_adc.h.

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STM32F373xC HAL User Manual: ADC group injected - Trigger source

Defines
ADC group injected - Trigger source
ADC Exported Constants

Defines

#define | LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2)
#define | LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)
#define | LL_ADC_INJ_TRIG_EXT_TIM19_CH1 ((uint32_t)0x00000000U)
#define | LL_ADC_INJ_TRIG_EXT_TIM19_CH2 (ADC_CR2_JEXTSEL_0)
#define | LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)

Define Documentation

#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)

ADC group injected conversion trigger external interrupt line 15. Trigger edge set to rising edge (default setting).

Definition at line 7896 of file stm32f3xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM19_CH1 ((uint32_t)0x00000000U)

ADC group injected conversion trigger external from TIM19 CC1. Trigger edge set to rising edge (default setting).

Definition at line 7894 of file stm32f3xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM19_CH2 (ADC_CR2_JEXTSEL_0)

ADC group injected conversion trigger external from TIM19 CC2. Trigger edge set to rising edge (default setting).

Definition at line 7895 of file stm32f3xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)

ADC group injected conversion trigger external from TIM2 CC1. Trigger edge set to rising edge (default setting).

Definition at line 7891 of file stm32f3xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1)

ADC group injected conversion trigger external from TIM2 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 7890 of file stm32f3xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2)

ADC group injected conversion trigger external from TIM3 CC4. Trigger edge set to rising edge (default setting).

Definition at line 7892 of file stm32f3xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)

ADC group injected conversion trigger external from TIM4 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 7893 of file stm32f3xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)

ADC group injected conversion trigger internal (SW start)

Definition at line 7889 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_INJ_IsTriggerSourceSWStart(), and LL_ADC_INJ_StructInit().

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STM32F373xC HAL User Manual: ADC group injected - Trigger edge

Defines
ADC group injected - Trigger edge
ADC Exported Constants

Defines

#define LL_ADC_INJ_TRIG_EXT_RISING ((uint32_t)0x00000000U)

Define Documentation

#define LL_ADC_INJ_TRIG_EXT_RISING ((uint32_t)0x00000000U)

ADC group injected conversion trigger polarity set to rising edge

Definition at line 7904 of file stm32f3xx_ll_adc.h.

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STM32F373xC HAL User Manual: ADC group injected - Automatic trigger mode

Defines
ADC group injected - Automatic trigger mode
ADC Exported Constants

Defines

#define | LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)
#define | LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO)

Define Documentation

#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO)

ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular.

Definition at line 7913 of file stm32f3xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)

ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger.

Definition at line 7912 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_INJ_StructInit().

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STM32F373xC HAL User Manual: ADC group injected - Sequencer scan length

Defines
ADC group injected - Sequencer scan length
ADC Exported Constants

Defines

#define | LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)

Define Documentation

#define LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U)

ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel)

Definition at line 7922 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)

ADC group injected sequencer enable with 2 ranks in the sequence

Definition at line 7923 of file stm32f3xx_ll_adc.h.

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )

ADC group injected sequencer enable with 3 ranks in the sequence

Definition at line 7924 of file stm32f3xx_ll_adc.h.

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)

ADC group injected sequencer enable with 4 ranks in the sequence

Definition at line 7925 of file stm32f3xx_ll_adc.h.

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STM32F373xC HAL User Manual: ADC group injected - Sequencer discontinuous mode

Defines
ADC group injected - Sequencer discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN)

Define Documentation

#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN)

ADC group injected sequencer discontinuous mode enable with sequence interruption every rank

Definition at line 7934 of file stm32f3xx_ll_adc.h.

#define LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)

ADC group injected sequencer discontinuous mode disable

Definition at line 7933 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_INJ_StructInit().

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STM32F373xC HAL User Manual: ADC group injected - Sequencer ranks

Defines
ADC group injected - Sequencer ranks
ADC Exported Constants

Defines

#define | LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)

Define Documentation

#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)

ADC group injected sequencer rank 1

Definition at line 7942 of file stm32f3xx_ll_adc.h.

#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)

ADC group injected sequencer rank 2

Definition at line 7943 of file stm32f3xx_ll_adc.h.

#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)

ADC group injected sequencer rank 3

Definition at line 7944 of file stm32f3xx_ll_adc.h.

#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)

ADC group injected sequencer rank 4

Definition at line 7945 of file stm32f3xx_ll_adc.h.

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STM32F373xC HAL User Manual: Channel - Sampling time

Defines
Channel - Sampling time
ADC Exported Constants

Defines

#define | LL_ADC_SAMPLINGTIME_1CYCLE_5 ((uint32_t)0x00000000U)
#define | LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0)
#define | LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1)
#define | LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)
#define | LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2)
#define | LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)
#define | LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)
#define | LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)

Define Documentation

#define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1)

Sampling time 13.5 ADC clock cycles

Definition at line 7955 of file stm32f3xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_1CYCLE_5 ((uint32_t)0x00000000U)

Sampling time 1.5 ADC clock cycle

Definition at line 7953 of file stm32f3xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)

Sampling time 239.5 ADC clock cycles

Definition at line 7960 of file stm32f3xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)

Sampling time 28.5 ADC clock cycles

Definition at line 7956 of file stm32f3xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2)

Sampling time 41.5 ADC clock cycles

Definition at line 7957 of file stm32f3xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)

Sampling time 55.5 ADC clock cycles

Definition at line 7958 of file stm32f3xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)

Sampling time 71.5 ADC clock cycles

Definition at line 7959 of file stm32f3xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0)

Sampling time 7.5 ADC clock cycles

Definition at line 7954 of file stm32f3xx_ll_adc.h.

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STM32F373xC HAL User Manual: Analog watchdog - Analog watchdog number

Defines
Analog watchdog - Analog watchdog number
ADC Exported Constants

Defines

#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)

Define Documentation

#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)

ADC analog watchdog number 1

Definition at line 7968 of file stm32f3xx_ll_adc.h.

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STM32F373xC HAL User Manual: Analog watchdog - Monitored channels

Defines
Analog watchdog - Monitored channels
ADC Exported Constants

Defines

#define | LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN )
#define | LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN )
#define | LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN )
#define | LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

Define Documentation

#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN )

ADC analog watchdog monitoring of all channels, converted by group injected only

Definition at line 7978 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN )

ADC analog watchdog monitoring of all channels, converted by group regular only

Definition at line 7977 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN )

ADC analog watchdog monitoring of all channels, converted by either group regular or injected

Definition at line 7979 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only

Definition at line 8038 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only

Definition at line 8037 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected

Definition at line 8039 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only

Definition at line 8035 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only

Definition at line 8034 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected

Definition at line 8036 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only

Definition at line 7981 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only

Definition at line 7980 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected

Definition at line 7982 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only

Definition at line 8011 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only

Definition at line 8010 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected

Definition at line 8012 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only

Definition at line 8014 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only

Definition at line 8013 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected

Definition at line 8015 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only

Definition at line 8017 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only

Definition at line 8016 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected

Definition at line 8018 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only

Definition at line 8020 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only

Definition at line 8019 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected

Definition at line 8021 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only

Definition at line 8023 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only

Definition at line 8022 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected

Definition at line 8024 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only

Definition at line 8026 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only

Definition at line 8025 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected

Definition at line 8027 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only

Definition at line 8029 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only

Definition at line 8028 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected

Definition at line 8030 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only

Definition at line 8032 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only

Definition at line 8031 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected

Definition at line 8033 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only

Definition at line 7984 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only

Definition at line 7983 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected

Definition at line 7985 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only

Definition at line 7987 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only

Definition at line 7986 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected

Definition at line 7988 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only

Definition at line 7990 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only

Definition at line 7989 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected

Definition at line 7991 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only

Definition at line 7993 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only

Definition at line 7992 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected

Definition at line 7994 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only

Definition at line 7996 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only

Definition at line 7995 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected

Definition at line 7997 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only

Definition at line 7999 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only

Definition at line 7998 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected

Definition at line 8000 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only

Definition at line 8002 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only

Definition at line 8001 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected

Definition at line 8003 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only

Definition at line 8005 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only

Definition at line 8004 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected

Definition at line 8006 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only

Definition at line 8008 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only

Definition at line 8007 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected

Definition at line 8009 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U)

ADC analog watchdog monitoring disabled

Definition at line 7976 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Analog watchdog - Thresholds

Defines
Analog watchdog - Thresholds
ADC Exported Constants

Defines

#define | LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET)
#define | LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET)

Define Documentation

#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET)

ADC analog watchdog threshold high

Definition at line 8047 of file stm32f3xx_ll_adc.h.

#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET)

ADC analog watchdog threshold low

Definition at line 8048 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Definitions of ADC hardware constraints delays

Defines
Definitions of ADC hardware constraints delays
ADC Exported Constants

Defines

#define | LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 10U)
#define | LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES ((uint32_t) 2U)

Detailed Description

Note:
Only ADC IP HW delays are defined in ADC LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES ((uint32_t) 2U)

Delay required between ADC disable and ADC calibration start

Definition at line 8091 of file stm32f3xx_ll_adc.h.

#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 10U)

Delay for internal voltage reference stabilization time

Definition at line 8079 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Common write and read registers Macros

Defines
Common write and read registers Macros
ADC Exported Macros

Defines

#define | LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in ADC register.
#define | LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in ADC register.

Define Documentation

#define LL_ADC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in ADC register.

Parameters:
__INSTANCE__ | ADC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 8126 of file stm32f3xx_ll_adc.h.

#define LL_ADC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in ADC register.

Parameters:
__INSTANCE__ | ADC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 8118 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC helper macro

Defines
ADC helper macro
ADC Exported Macros

Defines

#define | __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.
#define | __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.
#define | __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
#define | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)
Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.
#define | __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) ((__AWD_THRESHOLD__) << (0U))
Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) (__AWD_THRESHOLD_12_BITS__)
Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC1_COMMON)
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) LL_ADC_IsEnabled(ADC1)
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) ((uint32_t)0xFFFU)
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Define Documentation

#define __LL_ADC_ANALOGWD_CHANNEL_GROUP | ( | __CHANNEL__,
 |  | __GROUP__
 | ) |
Value:
(((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)                            \
      :                                                                                                   \
      ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                              \
       ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)                        \
         :                                                                                                \
         (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)        \
  )

Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.

Note:
To be used with function LL_ADC_SetAnalogWDMonitChannels(). Example: LL_ADC_SetAnalogWDMonitChannels( ADC1, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F37x, parameter available only on ADC instance: ADC1.
(1) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
__GROUP__ This parameter can be one of the following values:
  • LL_ADC_GROUP_REGULAR
  • LL_ADC_GROUP_INJECTED
  • LL_ADC_GROUP_REGULAR_INJECTED
Return values:
Returned value can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG
  • LL_ADC_AWD_ALL_CHANNELS_INJ
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG
  • LL_ADC_AWD_CHANNEL_0_INJ
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG
  • LL_ADC_AWD_CHANNEL_1_INJ
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG
  • LL_ADC_AWD_CHANNEL_2_INJ
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG
  • LL_ADC_AWD_CHANNEL_3_INJ
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG
  • LL_ADC_AWD_CHANNEL_4_INJ
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG
  • LL_ADC_AWD_CHANNEL_5_INJ
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG
  • LL_ADC_AWD_CHANNEL_6_INJ
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG
  • LL_ADC_AWD_CHANNEL_7_INJ
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG
  • LL_ADC_AWD_CHANNEL_8_INJ
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG
  • LL_ADC_AWD_CHANNEL_9_INJ
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG
  • LL_ADC_AWD_CHANNEL_10_INJ
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG
  • LL_ADC_AWD_CHANNEL_11_INJ
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG
  • LL_ADC_AWD_CHANNEL_12_INJ
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG
  • LL_ADC_AWD_CHANNEL_13_INJ
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG
  • LL_ADC_AWD_CHANNEL_14_INJ
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG
  • LL_ADC_AWD_CHANNEL_15_INJ
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG
  • LL_ADC_AWD_CHANNEL_16_INJ
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG
  • LL_ADC_AWD_CHANNEL_17_INJ
  • LL_ADC_AWD_CHANNEL_17_REG_INJ
  • LL_ADC_AWD_CH_VREFINT_REG (1)
  • LL_ADC_AWD_CH_VREFINT_INJ (1)
  • LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
(1) On STM32F37x, parameter available only on ADC instance: ADC1.

Definition at line 8463 of file stm32f3xx_ll_adc.h.

#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION | ( | __ADC_RESOLUTION__,
 |  | __AWD_THRESHOLD_12_BITS__
 | ) | (__AWD_THRESHOLD_12_BITS__)

Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.

Note:
To be used with function LL_ADC_GetAnalogWDThresholds(). Example, with a ADC resolution of 8 bits, to get the value of analog watchdog threshold high (on 8 bits): < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION (LL_ADC_RESOLUTION_8B, LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH) );
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
__AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 8514 of file stm32f3xx_ll_adc.h.

#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION | ( | __ADC_RESOLUTION__,
 |  | __AWD_THRESHOLD__
 | ) | ((__AWD_THRESHOLD__) << (0U))

Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.

Note:
To be used with function LL_ADC_SetAnalogWDThresholds(). Example, with a ADC resolution of 8 bits, to set the value of analog watchdog threshold high (on 8 bits): LL_ADC_SetAnalogWDThresholds (< ADCx param >, __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>) );
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
__AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 8492 of file stm32f3xx_ll_adc.h.

#define __LL_ADC_CALC_DATA_TO_VOLTAGE | ( | __VREFANALOG_VOLTAGE__,
 |  | __ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
  )

Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).

Note:
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__ADC_DATA__ | ADC conversion data (resolution 12 bits) (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 8607 of file stm32f3xx_ll_adc.h.

#define __LL_ADC_CALC_TEMPERATURE | ( | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
                                                    (__ADC_RESOLUTION__),          \
                                                    LL_ADC_RESOLUTION_12B)         \
                   * (__VREFANALOG_VOLTAGE__))                                     \
                  / TEMPSENSOR_CAL_VREFANALOG)                                     \
        - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
     ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
    ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
   ) + TEMPSENSOR_CAL1_TEMP                                                        \
  )

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor calibration values stored in system memory for each device during production.
Calculation formula: Temperature = ((TS_ADC_DATA - TS_CAL1) * (TS_CAL2_TEMP - TS_CAL1_TEMP)) / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC Avg_Slope = (TS_CAL2 - TS_CAL1) / (TS_CAL2_TEMP - TS_CAL1_TEMP) TS_CAL1 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL1 (calibrated in factory) TS_CAL2 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL2 (calibrated in factory) Caution: Calculation relevancy under reserve that calibration parameters are correct (address and data). To calculate temperature using temperature sensor datasheet typical values (generic values less, therefore less accurate than calibrated values), use helper macro __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
On this STM32 serie, calibration data of temperature sensor corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of temperature sensor. On STM32F37x, the only ADC resolution available is 12 bits. The parameter of ADC resolution is kept for compatibility purpose over other STM32 families.
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
Return values:
Temperature (unit: degree Celsius)

Definition at line 8689 of file stm32f3xx_ll_adc.h.

#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS | ( | __TEMPSENSOR_TYP_AVGSLOPE__,
 |  | __TEMPSENSOR_TYP_CALX_V__,
 |  | __TEMPSENSOR_CALX_TEMP__,
 |  | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
((( (                                                                        \
       (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
                 * 1000)                                                       \
       -                                                                       \
       (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
                  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
                 * 1000)                                                       \
      )                                                                        \
    ) / (__TEMPSENSOR_TYP_AVGSLOPE__)                                          \
   ) + (__TEMPSENSOR_CALX_TEMP__)                                              \
  )

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor typical values (refer to device datasheet).
Calculation formula: Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) / Avg_Slope + CALx_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC (unit: digital value) Avg_Slope = temperature sensor slope (unit: uV/Degree Celsius) TS_TYP_CALx_VOLT = temperature sensor digital value at temperature CALx_TEMP (unit: mV) Caution: Calculation relevancy under reserve the temperature sensor of the current device has characteristics in line with datasheet typical values. If temperature sensor calibration values are available on on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), temperature calculation will be more accurate using helper macro __LL_ADC_CALC_TEMPERATURE().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
ADC measurement data must correspond to a resolution of 12bits (full scale digital value 4095). If not the case, the data must be preliminarily rescaled to an equivalent resolution of 12 bits.
Parameters:
__TEMPSENSOR_TYP_AVGSLOPE__ | Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). On STM32F37x, refer to device datasheet parameter "Avg_Slope".
__TEMPSENSOR_TYP_CALX_V__ | Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). On STM32F37x, refer to device datasheet parameter "V25".
__TEMPSENSOR_CALX_TEMP__ | Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
__VREFANALOG_VOLTAGE__ | Analog voltage reference (Vref+) voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
Return values:
Temperature (unit: degree Celsius)

Definition at line 8744 of file stm32f3xx_ll_adc.h.

#define __LL_ADC_CALC_VREFANALOG_VOLTAGE | ( | __VREFINT_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
    / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                 \
                                       (__ADC_RESOLUTION__),                   \
                                       LL_ADC_RESOLUTION_12B)                  \
  )

Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.

Note:
Computation is using VrefInt calibration value stored in system memory for each device during production.
This voltage depends on user board environment: voltage level connected to pin Vref+. On devices with small package, the pin Vref+ is not present and internally bonded to pin Vdda.
On this STM32 serie, calibration data of internal voltage reference VrefInt corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of internal voltage reference VrefInt. On STM32F37x, the only ADC resolution available is 12 bits. The parameter of ADC resolution is kept for compatibility purpose over other STM32 families.
Parameters:
__VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) of internal voltage reference VrefInt (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
Return values:
Analog reference voltage (unit: mV)

Definition at line 8638 of file stm32f3xx_ll_adc.h.

#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL ( __CHANNEL__ ) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)

Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).

Note:
The channel parameter can be, additionally to a value defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), a value defined from parameter definition of ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F37x, parameter available only on ADC instance: ADC1.
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17

Definition at line 8321 of file stm32f3xx_ll_adc.h.

#define __LL_ADC_CHANNEL_TO_DECIMAL_NB ( __CHANNEL__ ) (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)

Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.

Note:
Example: __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) will return decimal number "4".
The input can be a value from functions where a channel number is returned, either defined with number or with bitfield (only one bit must be set).
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F37x, parameter available only on ADC instance: ADC1.
Return values:
Value between Min_Data=0 and Max_Data=18

Definition at line 8169 of file stm32f3xx_ll_adc.h.

#define __LL_ADC_COMMON_INSTANCE ( __ADCx__ ) (ADC1_COMMON)

Helper macro to select the ADC common instance to which is belonging the selected ADC instance.

Note:
ADC common register instance can be used for:
  • Set parameters common to several ADC instances
  • Multimode (for devices with several ADC instances) Refer to functions having argument "ADCxy_COMMON" as parameter.
On STM32F37x, there is no common ADC instance. However, ADC instance ADC1 has a role of common ADC instance (equivalence with other STM32 families featuring several ADC instances).
Parameters:
__ADCx__ ADC instance
Return values:
ADC common register instance

Definition at line 8531 of file stm32f3xx_ll_adc.h.

#define __LL_ADC_CONVERT_DATA_RESOLUTION | ( | __DATA__,
 |  | __ADC_RESOLUTION_CURRENT__,
 |  | __ADC_RESOLUTION_TARGET__
 | ) |
Value:
(((__DATA__)                                                                 \
    << ((__ADC_RESOLUTION_CURRENT__) >> (0U)))                                 \
   >> ((__ADC_RESOLUTION_TARGET__) >> (0U))                                    \
  )

Helper macro to convert the ADC conversion data from a resolution to another resolution.

Note:
On STM32F37x, the only ADC resolution available is 12 bits. This macro has been kept for compatibility purpose over other STM32 families.
Parameters:
__DATA__ ADC conversion data to be converted
__ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
__ADC_RESOLUTION_TARGET__ Resolution of the data after conversion This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
Return values:
ADC conversion data to the requested resolution

Definition at line 8586 of file stm32f3xx_ll_adc.h.

#define __LL_ADC_DECIMAL_NB_TO_CHANNEL ( __DECIMAL_NB__ )
Value:
(((__DECIMAL_NB__) <= 9U)                                                                                     \
    ? (                                                                                                         \
       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |        \
       (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))         \
      )                                                                                                         \
      :                                                                                                         \
      (                                                                                                         \
       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                              | \
       (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
      )                                                                                                         \
  )

Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.

Note:
Example: __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) will return a data equivalent to "LL_ADC_CHANNEL_4".
Parameters:
__DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F37x, parameter available only on ADC instance: ADC1.
(1) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 8206 of file stm32f3xx_ll_adc.h.

#define __LL_ADC_DIGITAL_SCALE ( __ADC_RESOLUTION__ ) ((uint32_t)0xFFFU)

Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.

Note:
ADC conversion data full-scale corresponds to voltage range determined by analog voltage references Vref+ and Vref- (refer to reference manual).
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 8568 of file stm32f3xx_ll_adc.h.

#define __LL_ADC_IS_CHANNEL_INTERNAL ( __CHANNEL__ ) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)

Helper macro to determine whether the selected channel corresponds to literal definitions of driver.

Note:
The different literal definitions of ADC channels are:
  • ADC internal channel: LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
  • ADC external channel (channel connected to a GPIO pin): LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
The channel parameter must be a value defined from literal definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), must not be a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F37x, parameter available only on ADC instance: ADC1.
Return values:
Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin) Value "1" if the channel corresponds to a parameter definition of a ADC internal channel

Definition at line 8262 of file stm32f3xx_ll_adc.h.

#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE | ( | __ADC_INSTANCE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__ADC_INSTANCE__) == ADC1)                                                \
    ? (                                                                        \
       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                         \
       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)                            \
      )                                                                        \
      :                                                                        \
      (0U)                                                                     \
  )

Helper macro to determine whether the internal channel selected is available on the ADC instance selected.

Note:
The channel parameter must be a value defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), must not be a value defined from parameter definition of ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__ADC_INSTANCE__ ADC instance
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F37x, parameter available only on ADC instance: ADC1.
Return values:
Value "0" if the internal channel selected is not available on the ADC instance selected. Value "1" if the internal channel selected is available on the ADC instance selected.

Definition at line 8346 of file stm32f3xx_ll_adc.h.

#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE ( __ADCXY_COMMON__ ) LL_ADC_IsEnabled(ADC1)

Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.

Note:
This check is required by functions with setting conditioned to ADC state: All ADC instances of the ADC common group must be disabled. Refer to functions having argument "ADCxy_COMMON" as parameter.
On devices with only 1 ADC common instance, parameter of this macro is useless and can be ignored (parameter kept for compatibility with devices featuring several ADC common instances).
On STM32F37x, there is no common ADC instance. However, ADC instance ADC1 has a role of common ADC instance (equivalence with other STM32 families featuring several ADC instances).
Parameters:
__ADCXY_COMMON__ ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Value "0" All ADC instances sharing the same ADC common instance are disabled. Value "1" At least one ADC instance sharing the same ADC common instance is enabled

Definition at line 8555 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC DMA management

Functions
ADC DMA management
ADC Exported Functions

Functions

__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr (ADC_TypeDef *ADCx, uint32_t Register)
Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Register
 | ) |  |

Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.

Note:
These ADC registers are data registers: when ADC conversion data is available in ADC data registers, ADC generates a DMA transfer request.
This macro is intended to be used with LL DMA driver, refer to function "LL_DMA_ConfigAddresses()". Example: LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_1, LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), (uint32_t)&< array or variable >, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
For devices with several ADC: in multimode, some devices use a different data register outside of ADC instance scope (common data register). This macro manages this register difference, only ADC instance has to be set as parameter.
Reference Manual to LL API cross reference:
DR DATA LL_ADC_DMA_GetRegAddr
Parameters:
ADCx ADC instance
Register This parameter can be one of the following values:
  • LL_ADC_DMA_REG_REGULAR_DATA
Return values:
ADC register address

Definition at line 8808 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration of ADC hierarchical scope: common to several ADC instances

Functions
Configuration of ADC hierarchical scope: common to several ADC instances
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE uint32_t | LL_ADC_GetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh ( ADC_Common_TypeDef * ADCxy_COMMON )

Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR)
Reference Manual to LL API cross reference:
CR2 TSVREFE LL_ADC_GetCommonPathInternalCh
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR

Definition at line 8866 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | PathInternal
 | ) |  |

Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR)
Stabilization time of measurement path to internal channel: After enabling internal paths, before starting ADC conversion, a delay is required for internal voltage reference and temperature sensor stabilization time. Refer to device datasheet. Refer to literal LL_ADC_DELAY_TEMPSENSOR_STAB_US.
ADC internal channel sampling time constraint: For ADC conversion of internal channels, a sampling time minimum value is required. Refer to device datasheet.
Reference Manual to LL API cross reference:
CR2 TSVREFE LL_ADC_SetCommonPathInternalCh
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
PathInternal This parameter can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR
Return values:
None

Definition at line 8847 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration of ADC hierarchical scope: ADC instance

Functions
Configuration of ADC hierarchical scope: ADC instance
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetDataAlignment (ADC_TypeDef *ADCx, uint32_t DataAlignment)
Set ADC conversion data alignment.
__STATIC_INLINE uint32_t | LL_ADC_GetDataAlignment (ADC_TypeDef *ADCx)
Get ADC conversion data alignment.
__STATIC_INLINE void | LL_ADC_SetSequencersScanMode (ADC_TypeDef *ADCx, uint32_t ScanMode)
Set ADC sequencers scan mode, for all ADC groups (group regular, group injected).
__STATIC_INLINE uint32_t | LL_ADC_GetSequencersScanMode (ADC_TypeDef *ADCx)
Get ADC sequencers scan mode, for all ADC groups (group regular, group injected).

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment ( ADC_TypeDef * ADCx )

Get ADC conversion data alignment.

Note:
Refer to reference manual for alignments formats dependencies to ADC resolutions.
Reference Manual to LL API cross reference:
CR2 ALIGN LL_ADC_SetDataAlignment
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_DATA_ALIGN_RIGHT
  • LL_ADC_DATA_ALIGN_LEFT

Definition at line 8905 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode ( ADC_TypeDef * ADCx )

Get ADC sequencers scan mode, for all ADC groups (group regular, group injected).

Note:
According to sequencers scan mode :
  • If disabled: ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of sequencers of all ADC groups (sequencer scan length, ...) is discarded: equivalent to scan length of 1 rank.
  • If enabled: ADC conversions are performed in sequence conversions mode, according to configuration of sequencers of each ADC group (sequencer scan length, ...). Refer to function LL_ADC_REG_SetSequencerLength() and to function LL_ADC_INJ_SetSequencerLength().
Reference Manual to LL API cross reference:
CR1 SCAN LL_ADC_GetSequencersScanMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_SEQ_SCAN_DISABLE
  • LL_ADC_SEQ_SCAN_ENABLE

Definition at line 8956 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetDataAlignment | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | DataAlignment
 | ) |  |

Set ADC conversion data alignment.

Note:
Refer to reference manual for alignments formats dependencies to ADC resolutions.
Reference Manual to LL API cross reference:
CR2 ALIGN LL_ADC_SetDataAlignment
Parameters:
ADCx ADC instance
DataAlignment This parameter can be one of the following values:
  • LL_ADC_DATA_ALIGN_RIGHT
  • LL_ADC_DATA_ALIGN_LEFT
Return values:
None

Definition at line 8890 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetSequencersScanMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ScanMode
 | ) |  |

Set ADC sequencers scan mode, for all ADC groups (group regular, group injected).

Note:
According to sequencers scan mode :
  • If disabled: ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of sequencers of all ADC groups (sequencer scan length, ...) is discarded: equivalent to scan length of 1 rank.
  • If enabled: ADC conversions are performed in sequence conversions mode, according to configuration of sequencers of each ADC group (sequencer scan length, ...). Refer to function LL_ADC_REG_SetSequencerLength() and to function LL_ADC_INJ_SetSequencerLength().
Reference Manual to LL API cross reference:
CR1 SCAN LL_ADC_SetSequencersScanMode
Parameters:
ADCx ADC instance
ScanMode This parameter can be one of the following values:
  • LL_ADC_SEQ_SCAN_DISABLE
  • LL_ADC_SEQ_SCAN_ENABLE
Return values:
None

Definition at line 8931 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration of ADC hierarchical scope: group regular

Functions
Configuration of ADC hierarchical scope: group regular
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_REG_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group regular conversion trigger source: internal (SW start) or external from timer or external interrupt.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source: internal (SW start) or external from timer or external interrupt.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE void | LL_ADC_REG_SetContinuousMode (ADC_TypeDef *ADCx, uint32_t Continuous)
Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetContinuousMode (ADC_TypeDef *ADCx)
Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void | LL_ADC_REG_SetDMATransfer (ADC_TypeDef *ADCx, uint32_t DMATransfer)
Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetDMATransfer (ADC_TypeDef *ADCx)
Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode ( ADC_TypeDef * ADCx )

Get ADC continuous conversion mode on ADC group regular.

Note:
Description of ADC continuous conversion mode:
  • single mode: one conversion per trigger
  • continuous mode: after the first trigger, following conversions launched successively automatically.
Reference Manual to LL API cross reference:
CR2 CONT LL_ADC_REG_GetContinuousMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_CONV_SINGLE
  • LL_ADC_REG_CONV_CONTINUOUS

Definition at line 9427 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

Note:
If transfer by DMA selected, specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
To configure DMA source address (peripheral address), use function LL_ADC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CR2 DMA LL_ADC_REG_GetDMATransfer
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_DMA_TRANSFER_NONE
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED

Definition at line 9490 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont ( ADC_TypeDef * ADCx )

Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Reference Manual to LL API cross reference:
CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_SEQ_DISCONT_DISABLE
  • LL_ADC_REG_SEQ_DISCONT_1RANK
  • LL_ADC_REG_SEQ_DISCONT_2RANKS
  • LL_ADC_REG_SEQ_DISCONT_3RANKS
  • LL_ADC_REG_SEQ_DISCONT_4RANKS
  • LL_ADC_REG_SEQ_DISCONT_5RANKS
  • LL_ADC_REG_SEQ_DISCONT_6RANKS
  • LL_ADC_REG_SEQ_DISCONT_7RANKS
  • LL_ADC_REG_SEQ_DISCONT_8RANKS

Definition at line 9211 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength ( ADC_TypeDef * ADCx )

Get ADC group regular sequencer length and scan direction.

Note:
Description of ADC group regular sequencer features:
  • For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function retrieves:
    • Sequence length: Number of ranks in the scan sequence.
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()".
  • For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function retrieves:
    • Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()".
On this STM32 serie, group regular sequencer configuration is conditioned to ADC instance sequencer mode. If ADC instance sequencer mode is disabled, sequencers of all groups (group regular, group injected) can be configured but their execution is disabled (limited to rank 1). Refer to function LL_ADC_SetSequencersScanMode().
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
Reference Manual to LL API cross reference:
SQR1 L LL_ADC_REG_SetSequencerLength
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_SEQ_SCAN_DISABLE
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

Definition at line 9160 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group regular sequence: channel on the selected scan sequence rank.

Note:
On this STM32 serie, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().
Reference Manual to LL API cross reference:
SQR3 SQ1 LL_ADC_REG_GetSequencerRanks
SQR3 SQ2 LL_ADC_REG_GetSequencerRanks
SQR3 SQ3 LL_ADC_REG_GetSequencerRanks
SQR3 SQ4 LL_ADC_REG_GetSequencerRanks
SQR3 SQ5 LL_ADC_REG_GetSequencerRanks
SQR3 SQ6 LL_ADC_REG_GetSequencerRanks
SQR2 SQ7 LL_ADC_REG_GetSequencerRanks
SQR2 SQ8 LL_ADC_REG_GetSequencerRanks
SQR2 SQ9 LL_ADC_REG_GetSequencerRanks
SQR2 SQ10 LL_ADC_REG_GetSequencerRanks
SQR2 SQ11 LL_ADC_REG_GetSequencerRanks
SQR2 SQ12 LL_ADC_REG_GetSequencerRanks
SQR1 SQ13 LL_ADC_REG_GetSequencerRanks
SQR1 SQ14 LL_ADC_REG_GetSequencerRanks
SQR1 SQ15 LL_ADC_REG_GetSequencerRanks
SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_REG_RANK_1
  • LL_ADC_REG_RANK_2
  • LL_ADC_REG_RANK_3
  • LL_ADC_REG_RANK_4
  • LL_ADC_REG_RANK_5
  • LL_ADC_REG_RANK_6
  • LL_ADC_REG_RANK_7
  • LL_ADC_REG_RANK_8
  • LL_ADC_REG_RANK_9
  • LL_ADC_REG_RANK_10
  • LL_ADC_REG_RANK_11
  • LL_ADC_REG_RANK_12
  • LL_ADC_REG_RANK_13
  • LL_ADC_REG_RANK_14
  • LL_ADC_REG_RANK_15
  • LL_ADC_REG_RANK_16
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F37x, parameter available only on ADC instance: ADC1.
(1) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 9385 of file stm32f3xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, ADC_REG_RANK_ID_SQRX_MASK, and ADC_REG_SQRX_REGOFFSET_MASK.

__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource ( ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger source: internal (SW start) or external from timer or external interrupt.

Note:
To determine whether group regular trigger source is internal (SW start) or external, without detail of which peripheral is selected as external trigger, (equivalent to "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") use function LL_ADC_REG_IsTriggerSourceSWStart.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR2 EXTSEL LL_ADC_REG_GetTriggerSource
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_TRIG_SOFTWARE
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM4_CH2
  • LL_ADC_REG_TRIG_EXT_TIM19_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM19_CH3
  • LL_ADC_REG_TRIG_EXT_TIM19_CH4
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11

Definition at line 9022 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart ( ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger source internal (SW start) or external.

Note:
In case of group regular trigger source set to external trigger, to determine which peripheral is selected as external trigger, use function LL_ADC_REG_GetTriggerSource().
Reference Manual to LL API cross reference:
CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart
Parameters:
ADCx ADC instance
Return values:
Value "0" trigger source external trigger Value "1" trigger source SW start.

Definition at line 9038 of file stm32f3xx_ll_adc.h.

References LL_ADC_REG_TRIG_SOFTWARE.

__STATIC_INLINE void LL_ADC_REG_SetContinuousMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Continuous
 | ) |  |

Set ADC continuous conversion mode on ADC group regular.

Note:
Description of ADC continuous conversion mode:
  • single mode: one conversion per trigger
  • continuous mode: after the first trigger, following conversions launched successively automatically.
It is not possible to enable both ADC group regular continuous mode and sequencer discontinuous mode.
Reference Manual to LL API cross reference:
CR2 CONT LL_ADC_REG_SetContinuousMode
Parameters:
ADCx ADC instance
Continuous This parameter can be one of the following values:
  • LL_ADC_REG_CONV_SINGLE
  • LL_ADC_REG_CONV_CONTINUOUS
Return values:
None

Definition at line 9410 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetDMATransfer | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | DMATransfer
 | ) |  |

Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

Note:
If transfer by DMA selected, specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
To configure DMA source address (peripheral address), use function LL_ADC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CR2 DMA LL_ADC_REG_SetDMATransfer
Parameters:
ADCx ADC instance
DMATransfer This parameter can be one of the following values:
  • LL_ADC_REG_DMA_TRANSFER_NONE
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED
Return values:
None

Definition at line 9459 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SeqDiscont
 | ) |  |

Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Note:
It is not possible to enable both ADC group regular continuous mode and sequencer discontinuous mode.
It is not possible to enable both ADC auto-injected mode and ADC group regular sequencer discontinuous mode.
Reference Manual to LL API cross reference:
CR1 DISCEN LL_ADC_REG_SetSequencerDiscont
CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
Parameters:
ADCx ADC instance
SeqDiscont This parameter can be one of the following values:
  • LL_ADC_REG_SEQ_DISCONT_DISABLE
  • LL_ADC_REG_SEQ_DISCONT_1RANK
  • LL_ADC_REG_SEQ_DISCONT_2RANKS
  • LL_ADC_REG_SEQ_DISCONT_3RANKS
  • LL_ADC_REG_SEQ_DISCONT_4RANKS
  • LL_ADC_REG_SEQ_DISCONT_5RANKS
  • LL_ADC_REG_SEQ_DISCONT_6RANKS
  • LL_ADC_REG_SEQ_DISCONT_7RANKS
  • LL_ADC_REG_SEQ_DISCONT_8RANKS
Return values:
None

Definition at line 9188 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSequencerLength | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SequencerNbRanks
 | ) |  |

Set ADC group regular sequencer length and scan direction.

Note:
Description of ADC group regular sequencer features:
  • For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function performs configuration of:
    • Sequence length: Number of ranks in the scan sequence.
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()".
  • For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function performs configuration of:
    • Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()".
On this STM32 serie, group regular sequencer configuration is conditioned to ADC instance sequencer mode. If ADC instance sequencer mode is disabled, sequencers of all groups (group regular, group injected) can be configured but their execution is disabled (limited to rank 1). Refer to function LL_ADC_SetSequencersScanMode().
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
Reference Manual to LL API cross reference:
SQR1 L LL_ADC_REG_SetSequencerLength
Parameters:
ADCx ADC instance
SequencerNbRanks This parameter can be one of the following values:
  • LL_ADC_REG_SEQ_SCAN_DISABLE
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
Return values:
None

Definition at line 9100 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_REG_Init().

__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank,
 |  | uint32_t | Channel
 | ) |  |

Set ADC group regular sequence: channel on the selected scan sequence rank.

Note:
This function performs configuration of:
  • Channels ordering into each rank of scan sequence: whatever channel can be placed into whatever rank.
On this STM32 serie, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
On this STM32 serie, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
Reference Manual to LL API cross reference:
SQR3 SQ1 LL_ADC_REG_SetSequencerRanks
SQR3 SQ2 LL_ADC_REG_SetSequencerRanks
SQR3 SQ3 LL_ADC_REG_SetSequencerRanks
SQR3 SQ4 LL_ADC_REG_SetSequencerRanks
SQR3 SQ5 LL_ADC_REG_SetSequencerRanks
SQR3 SQ6 LL_ADC_REG_SetSequencerRanks
SQR2 SQ7 LL_ADC_REG_SetSequencerRanks
SQR2 SQ8 LL_ADC_REG_SetSequencerRanks
SQR2 SQ9 LL_ADC_REG_SetSequencerRanks
SQR2 SQ10 LL_ADC_REG_SetSequencerRanks
SQR2 SQ11 LL_ADC_REG_SetSequencerRanks
SQR2 SQ12 LL_ADC_REG_SetSequencerRanks
SQR1 SQ13 LL_ADC_REG_SetSequencerRanks
SQR1 SQ14 LL_ADC_REG_SetSequencerRanks
SQR1 SQ15 LL_ADC_REG_SetSequencerRanks
SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_REG_RANK_1
  • LL_ADC_REG_RANK_2
  • LL_ADC_REG_RANK_3
  • LL_ADC_REG_RANK_4
  • LL_ADC_REG_RANK_5
  • LL_ADC_REG_RANK_6
  • LL_ADC_REG_RANK_7
  • LL_ADC_REG_RANK_8
  • LL_ADC_REG_RANK_9
  • LL_ADC_REG_RANK_10
  • LL_ADC_REG_RANK_11
  • LL_ADC_REG_RANK_12
  • LL_ADC_REG_RANK_13
  • LL_ADC_REG_RANK_14
  • LL_ADC_REG_RANK_15
  • LL_ADC_REG_RANK_16
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F37x, parameter available only on ADC instance: ADC1.
Return values:
None

Definition at line 9291 of file stm32f3xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, and ADC_REG_SQRX_REGOFFSET_MASK.

__STATIC_INLINE void LL_ADC_REG_SetTriggerSource | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource
 | ) |  |

Set ADC group regular conversion trigger source: internal (SW start) or external from timer or external interrupt.

Note:
On this STM32 serie, external trigger is set with trigger polarity: rising edge (only trigger polarity available on this STM32 serie).
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR2 EXTSEL LL_ADC_REG_SetTriggerSource
Parameters:
ADCx ADC instance
TriggerSource This parameter can be one of the following values:
  • LL_ADC_REG_TRIG_SOFTWARE
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM4_CH2
  • LL_ADC_REG_TRIG_EXT_TIM19_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM19_CH3
  • LL_ADC_REG_TRIG_EXT_TIM19_CH4
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11
Return values:
None

Definition at line 8989 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration of ADC hierarchical scope: group injected

Functions
Configuration of ADC hierarchical scope: group injected
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_INJ_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group injected conversion trigger source: internal (SW start) or external from timer or external interrupt.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source: internal (SW start) or external from timer or external interrupt.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group injected sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group injected sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE void | LL_ADC_INJ_SetTrigAuto (ADC_TypeDef *ADCx, uint32_t TrigAuto)
Set ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTrigAuto (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE void | LL_ADC_INJ_SetOffset (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
Set ADC group injected offset.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetOffset (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected offset.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected offset.

Note:
It gives offset level (offset to be subtracted from the raw converted data). Caution: Offset format is dependent to ADC resolution: offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
Reference Manual to LL API cross reference:
JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset
JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset
JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset
JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 9878 of file stm32f3xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, and ADC_INJ_JOFRX_REGOFFSET_MASK.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont ( ADC_TypeDef * ADCx )

Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Reference Manual to LL API cross reference:
CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE
  • LL_ADC_INJ_SEQ_DISCONT_1RANK

Definition at line 9660 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength ( ADC_TypeDef * ADCx )

Get ADC group injected sequencer length and scan direction.

Note:
This function retrieves:
  • Sequence length: Number of ranks in the scan sequence.
  • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n).
On this STM32 serie, group injected sequencer configuration is conditioned to ADC instance sequencer mode. If ADC instance sequencer mode is disabled, sequencers of all groups (group regular, group injected) can be configured but their execution is disabled (limited to rank 1). Refer to function LL_ADC_SetSequencersScanMode().
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
Reference Manual to LL API cross reference:
JSQR JL LL_ADC_INJ_GetSequencerLength
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_SEQ_SCAN_DISABLE
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

Definition at line 9627 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected sequence: channel on the selected sequence rank.

Note:
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().
Reference Manual to LL API cross reference:
JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F37x, parameter available only on ADC instance: ADC1.
(1) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 9773 of file stm32f3xx_ll_adc.h.

References ADC_INJ_RANK_ID_JSQR_MASK.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger: independent or from ADC group regular.

Reference Manual to LL API cross reference:
CR1 JAUTO LL_ADC_INJ_GetTrigAuto
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_TRIG_INDEPENDENT
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

Definition at line 9821 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger source: internal (SW start) or external from timer or external interrupt.

Note:
To determine whether group injected trigger source is internal (SW start) or external, without detail of which peripheral is selected as external trigger, (equivalent to "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") use function LL_ADC_INJ_IsTriggerSourceSWStart.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_TRIG_SOFTWARE
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM19_CH1
  • LL_ADC_INJ_TRIG_EXT_TIM19_CH2
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

Definition at line 9556 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger source internal (SW start) or external.

Note:
In case of group injected trigger source set to external trigger, to determine which peripheral is selected as external trigger, use function LL_ADC_INJ_GetTriggerSource.
Reference Manual to LL API cross reference:
CR2 JEXTSEL LL_ADC_INJ_IsTriggerSourceSWStart
Parameters:
ADCx ADC instance
Return values:
Value "0" trigger source external trigger Value "1" trigger source SW start.

Definition at line 9572 of file stm32f3xx_ll_adc.h.

References LL_ADC_INJ_TRIG_SOFTWARE.

__STATIC_INLINE void LL_ADC_INJ_SetOffset | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank,
 |  | uint32_t | OffsetLevel
 | ) |  |

Set ADC group injected offset.

Note:
It sets:
  • ADC group injected rank to which the offset programmed will be applied
  • Offset level (offset to be subtracted from the raw converted data). Caution: Offset format is dependent to ADC resolution: offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
Offset cannot be enabled or disabled. To emulate offset disabled, set an offset value equal to 0.
Reference Manual to LL API cross reference:
JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset
JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset
JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset
JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
Parameters:
ADCx | ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
OffsetLevel | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 9851 of file stm32f3xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, and ADC_INJ_JOFRX_REGOFFSET_MASK.

__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SeqDiscont
 | ) |  |

Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Note:
It is not possible to enable both ADC group injected auto-injected mode and sequencer discontinuous mode.
Reference Manual to LL API cross reference:
CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
Parameters:
ADCx ADC instance
SeqDiscont This parameter can be one of the following values:
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE
  • LL_ADC_INJ_SEQ_DISCONT_1RANK
Return values:
None

Definition at line 9645 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SequencerNbRanks
 | ) |  |

Set ADC group injected sequencer length and scan direction.

Note:
This function performs configuration of:
  • Sequence length: Number of ranks in the scan sequence.
  • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n).
On this STM32 serie, group injected sequencer configuration is conditioned to ADC instance sequencer mode. If ADC instance sequencer mode is disabled, sequencers of all groups (group regular, group injected) can be configured but their execution is disabled (limited to rank 1). Refer to function LL_ADC_SetSequencersScanMode().
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
Reference Manual to LL API cross reference:
JSQR JL LL_ADC_INJ_SetSequencerLength
Parameters:
ADCx ADC instance
SequencerNbRanks This parameter can be one of the following values:
  • LL_ADC_INJ_SEQ_SCAN_DISABLE
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
Return values:
None

Definition at line 9600 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init().

__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank,
 |  | uint32_t | Channel
 | ) |  |

Set ADC group injected sequence: channel on the selected sequence rank.

Note:
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
On this STM32 serie, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
Reference Manual to LL API cross reference:
JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F37x, parameter available only on ADC instance: ADC1.
Return values:
None

Definition at line 9709 of file stm32f3xx_ll_adc.h.

References ADC_INJ_RANK_ID_JSQR_MASK.

__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TrigAuto
 | ) |  |

Set ADC group injected conversion trigger: independent or from ADC group regular.

Note:
This mode can be used to extend number of data registers updated after one ADC conversion trigger and with data permanently kept (not erased by successive conversions of scan of ADC sequencer ranks), up to 5 data registers: 1 data register on ADC group regular, 4 data registers on ADC group injected.
If ADC group injected injected trigger source is set to an external trigger, this feature must be must be set to independent trigger. ADC group injected automatic trigger is compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular.
It is not possible to enable both ADC group injected auto-injected mode and sequencer discontinuous mode.
Reference Manual to LL API cross reference:
CR1 JAUTO LL_ADC_INJ_SetTrigAuto
Parameters:
ADCx ADC instance
TrigAuto This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_INDEPENDENT
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
Return values:
None

Definition at line 9807 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource
 | ) |  |

Set ADC group injected conversion trigger source: internal (SW start) or external from timer or external interrupt.

Note:
On this STM32 serie, external trigger is set with trigger polarity: rising edge (only trigger polarity available on this STM32 serie).
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource
Parameters:
ADCx ADC instance
TriggerSource This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_SOFTWARE
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM19_CH1
  • LL_ADC_INJ_TRIG_EXT_TIM19_CH2
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
Return values:
None

Definition at line 9523 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration of ADC hierarchical scope: channels

Functions
Configuration of ADC hierarchical scope: channels
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel)
Get sampling time of the selected ADC channel Unit: ADC clock cycles.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel
 | ) |  |

Get sampling time of the selected ADC channel Unit: ADC clock cycles.

Note:
On this device, sampling time is on channel scope: independently of channel mapped on ADC group regular or injected.
Conversion time is the addition of sampling time and processing time. Refer to reference manual for ADC processing time of this STM32 serie.
Reference Manual to LL API cross reference:
SMPR1 SMP17 LL_ADC_GetChannelSamplingTime
SMPR1 SMP16 LL_ADC_GetChannelSamplingTime
SMPR1 SMP15 LL_ADC_GetChannelSamplingTime
SMPR1 SMP14 LL_ADC_GetChannelSamplingTime
SMPR1 SMP13 LL_ADC_GetChannelSamplingTime
SMPR1 SMP12 LL_ADC_GetChannelSamplingTime
SMPR1 SMP11 LL_ADC_GetChannelSamplingTime
SMPR1 SMP10 LL_ADC_GetChannelSamplingTime
SMPR2 SMP9 LL_ADC_GetChannelSamplingTime
SMPR2 SMP8 LL_ADC_GetChannelSamplingTime
SMPR2 SMP7 LL_ADC_GetChannelSamplingTime
SMPR2 SMP6 LL_ADC_GetChannelSamplingTime
SMPR2 SMP5 LL_ADC_GetChannelSamplingTime
SMPR2 SMP4 LL_ADC_GetChannelSamplingTime
SMPR2 SMP3 LL_ADC_GetChannelSamplingTime
SMPR2 SMP2 LL_ADC_GetChannelSamplingTime
SMPR2 SMP1 LL_ADC_GetChannelSamplingTime
SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
Parameters:
ADCx ADC instance
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F37x, parameter available only on ADC instance: ADC1.
Return values:
Returned value can be one of the following values:
  • LL_ADC_SAMPLINGTIME_1CYCLE_5
  • LL_ADC_SAMPLINGTIME_7CYCLES_5
  • LL_ADC_SAMPLINGTIME_13CYCLES_5
  • LL_ADC_SAMPLINGTIME_28CYCLES_5
  • LL_ADC_SAMPLINGTIME_41CYCLES_5
  • LL_ADC_SAMPLINGTIME_55CYCLES_5
  • LL_ADC_SAMPLINGTIME_71CYCLES_5
  • LL_ADC_SAMPLINGTIME_239CYCLES_5

Definition at line 10040 of file stm32f3xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, ADC_CHANNEL_SMPRX_REGOFFSET_MASK, and ADC_CHANNEL_SMPx_BITOFFSET_MASK.

__STATIC_INLINE void LL_ADC_SetChannelSamplingTime | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel,
 |  | uint32_t | SamplingTime
 | ) |  |

Set sampling time of the selected ADC channel Unit: ADC clock cycles.

Note:
On this device, sampling time is on channel scope: independently of channel mapped on ADC group regular or injected.
In case of internal channel (VrefInt, TempSensor, ...) to be converted: sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting). Refer to device datasheet for timings values (parameters TS_vrefint, TS_temp, ...).
Conversion time is the addition of sampling time and processing time. Refer to reference manual for ADC processing time of this STM32 serie.
In case of ADC conversion of internal channel (VrefInt, temperature sensor, ...), a sampling time minimum value is required. Refer to device datasheet.
Reference Manual to LL API cross reference:
SMPR1 SMP17 LL_ADC_SetChannelSamplingTime
SMPR1 SMP16 LL_ADC_SetChannelSamplingTime
SMPR1 SMP15 LL_ADC_SetChannelSamplingTime
SMPR1 SMP14 LL_ADC_SetChannelSamplingTime
SMPR1 SMP13 LL_ADC_SetChannelSamplingTime
SMPR1 SMP12 LL_ADC_SetChannelSamplingTime
SMPR1 SMP11 LL_ADC_SetChannelSamplingTime
SMPR1 SMP10 LL_ADC_SetChannelSamplingTime
SMPR2 SMP9 LL_ADC_SetChannelSamplingTime
SMPR2 SMP8 LL_ADC_SetChannelSamplingTime
SMPR2 SMP7 LL_ADC_SetChannelSamplingTime
SMPR2 SMP6 LL_ADC_SetChannelSamplingTime
SMPR2 SMP5 LL_ADC_SetChannelSamplingTime
SMPR2 SMP4 LL_ADC_SetChannelSamplingTime
SMPR2 SMP3 LL_ADC_SetChannelSamplingTime
SMPR2 SMP2 LL_ADC_SetChannelSamplingTime
SMPR2 SMP1 LL_ADC_SetChannelSamplingTime
SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
Parameters:
ADCx ADC instance
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F37x, parameter available only on ADC instance: ADC1.
SamplingTime This parameter can be one of the following values:
  • LL_ADC_SAMPLINGTIME_1CYCLE_5
  • LL_ADC_SAMPLINGTIME_7CYCLES_5
  • LL_ADC_SAMPLINGTIME_13CYCLES_5
  • LL_ADC_SAMPLINGTIME_28CYCLES_5
  • LL_ADC_SAMPLINGTIME_41CYCLES_5
  • LL_ADC_SAMPLINGTIME_55CYCLES_5
  • LL_ADC_SAMPLINGTIME_71CYCLES_5
  • LL_ADC_SAMPLINGTIME_239CYCLES_5
Return values:
None

Definition at line 9967 of file stm32f3xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, ADC_CHANNEL_SMPRX_REGOFFSET_MASK, and ADC_CHANNEL_SMPx_BITOFFSET_MASK.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration of ADC transversal scope: analog watchdog

Functions
Configuration of ADC transversal scope: analog watchdog
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
Set ADC analog watchdog monitored channels: a single channel or all channels, on ADC groups regular and-or injected.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDMonitChannels (ADC_TypeDef *ADCx)
Get ADC analog watchdog monitored channel.
__STATIC_INLINE void | LL_ADC_SetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
Get ADC analog watchdog threshold value of threshold high or threshold low.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels ( ADC_TypeDef * ADCx )

Get ADC analog watchdog monitored channel.

Note:
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Applicable only when the analog watchdog is set to monitor one channel.
On this STM32 serie, there is only 1 kind of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
Reference Manual to LL API cross reference:
CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels
CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels
CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG
  • LL_ADC_AWD_ALL_CHANNELS_INJ
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG
  • LL_ADC_AWD_CHANNEL_0_INJ
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG
  • LL_ADC_AWD_CHANNEL_1_INJ
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG
  • LL_ADC_AWD_CHANNEL_2_INJ
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG
  • LL_ADC_AWD_CHANNEL_3_INJ
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG
  • LL_ADC_AWD_CHANNEL_4_INJ
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG
  • LL_ADC_AWD_CHANNEL_5_INJ
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG
  • LL_ADC_AWD_CHANNEL_6_INJ
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG
  • LL_ADC_AWD_CHANNEL_7_INJ
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG
  • LL_ADC_AWD_CHANNEL_8_INJ
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG
  • LL_ADC_AWD_CHANNEL_9_INJ
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG
  • LL_ADC_AWD_CHANNEL_10_INJ
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG
  • LL_ADC_AWD_CHANNEL_11_INJ
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG
  • LL_ADC_AWD_CHANNEL_12_INJ
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG
  • LL_ADC_AWD_CHANNEL_13_INJ
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG
  • LL_ADC_AWD_CHANNEL_14_INJ
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG
  • LL_ADC_AWD_CHANNEL_15_INJ
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG
  • LL_ADC_AWD_CHANNEL_16_INJ
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG
  • LL_ADC_AWD_CHANNEL_17_INJ
  • LL_ADC_AWD_CHANNEL_17_REG_INJ

Definition at line 10240 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDThresholdsHighLow
 | ) |  |

Get ADC analog watchdog threshold value of threshold high or threshold low.

Note:
In case of ADC resolution different of 12 bits, analog watchdog thresholds data require a specific shift. Use helper macro __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
Reference Manual to LL API cross reference:
HTR HT LL_ADC_GetAnalogWDThresholds
LTR LT LL_ADC_GetAnalogWDThresholds
Parameters:
ADCx ADC instance
AWDThresholdsHighLow This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 10287 of file stm32f3xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDChannelGroup
 | ) |  |

Set ADC analog watchdog monitored channels: a single channel or all channels, on ADC groups regular and-or injected.

Note:
Once monitored channels are selected, analog watchdog is enabled.
In case of need to define a single channel to monitor with analog watchdog from sequencer channel definition, use helper macro __LL_ADC_ANALOGWD_CHANNEL_GROUP().
On this STM32 serie, there is only 1 kind of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
Reference Manual to LL API cross reference:
CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels
CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels
CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
Parameters:
ADCx ADC instance
AWDChannelGroup This parameter can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG
  • LL_ADC_AWD_ALL_CHANNELS_INJ
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG
  • LL_ADC_AWD_CHANNEL_0_INJ
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG
  • LL_ADC_AWD_CHANNEL_1_INJ
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG
  • LL_ADC_AWD_CHANNEL_2_INJ
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG
  • LL_ADC_AWD_CHANNEL_3_INJ
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG
  • LL_ADC_AWD_CHANNEL_4_INJ
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG
  • LL_ADC_AWD_CHANNEL_5_INJ
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG
  • LL_ADC_AWD_CHANNEL_6_INJ
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG
  • LL_ADC_AWD_CHANNEL_7_INJ
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG
  • LL_ADC_AWD_CHANNEL_8_INJ
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG
  • LL_ADC_AWD_CHANNEL_9_INJ
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG
  • LL_ADC_AWD_CHANNEL_10_INJ
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG
  • LL_ADC_AWD_CHANNEL_11_INJ
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG
  • LL_ADC_AWD_CHANNEL_12_INJ
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG
  • LL_ADC_AWD_CHANNEL_13_INJ
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG
  • LL_ADC_AWD_CHANNEL_14_INJ
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG
  • LL_ADC_AWD_CHANNEL_15_INJ
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG
  • LL_ADC_AWD_CHANNEL_16_INJ
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG
  • LL_ADC_AWD_CHANNEL_17_INJ
  • LL_ADC_AWD_CHANNEL_17_REG_INJ
  • LL_ADC_AWD_CH_VREFINT_REG (1)
  • LL_ADC_AWD_CH_VREFINT_INJ (1)
  • LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
(1) On STM32F37x, parameter available only on ADC instance: ADC1.
Return values:
None

Definition at line 10147 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDThresholdsHighLow,
 |  | uint32_t | AWDThresholdValue
 | ) |  |

Set ADC analog watchdog threshold value of threshold high or low.

Note:
On this STM32 serie, there is only 1 kind of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
Reference Manual to LL API cross reference:
HTR HT LL_ADC_SetAnalogWDThresholds
LTR LT LL_ADC_SetAnalogWDThresholds
Parameters:
ADCx | ADC instance
AWDThresholdsHighLow This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
AWDThresholdValue | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 10264 of file stm32f3xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Operation on ADC hierarchical scope: ADC instance

Functions
Operation on ADC hierarchical scope: ADC instance
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_Enable (ADC_TypeDef *ADCx)
Enable the selected ADC instance.
__STATIC_INLINE void | LL_ADC_Disable (ADC_TypeDef *ADCx)
Disable the selected ADC instance.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance enable state.
__STATIC_INLINE void | LL_ADC_StartCalibration (ADC_TypeDef *ADCx)
Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_IsCalibrationOnGoing (ADC_TypeDef *ADCx)
Get ADC calibration state.

Function Documentation

__STATIC_INLINE void LL_ADC_Disable ( ADC_TypeDef * ADCx )

Disable the selected ADC instance.

Reference Manual to LL API cross reference:
CR2 ADON LL_ADC_Disable
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 10323 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE void LL_ADC_Enable ( ADC_TypeDef * ADCx )

Enable the selected ADC instance.

Note:
On this STM32 serie, after ADC enable, a delay for ADC internal analog stabilization is required before performing a ADC conversion start. Refer to device datasheet, parameter tSTAB.
Reference Manual to LL API cross reference:
CR2 ADON LL_ADC_Enable
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 10312 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing ( ADC_TypeDef * ADCx )

Get ADC calibration state.

Reference Manual to LL API cross reference:
CR2 CAL LL_ADC_IsCalibrationOnGoing
Parameters:
ADCx ADC instance
Return values:
0,: calibration complete, 1: calibration in progress.

Definition at line 10365 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsEnabled ( ADC_TypeDef * ADCx )

Get the selected ADC instance enable state.

Reference Manual to LL API cross reference:
CR2 ADON LL_ADC_IsEnabled
Parameters:
ADCx ADC instance
Return values:
0,: ADC is disabled, 1: ADC is enabled.

Definition at line 10334 of file stm32f3xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_Init(), LL_ADC_INJ_Init(), and LL_ADC_REG_Init().

__STATIC_INLINE void LL_ADC_StartCalibration ( ADC_TypeDef * ADCx )

Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).

Note:
On this STM32 serie, before starting a calibration, ADC must be disabled. A minimum number of ADC clock cycles are required between ADC disable state and calibration start. Refer to literal LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES.
On this STM32 serie, hardware prerequisite before starting a calibration: the ADC must have been in power-on state for at least two ADC clock cycles.
Reference Manual to LL API cross reference:
CR2 CAL LL_ADC_StartCalibration
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 10354 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Operation on ADC hierarchical scope: group regular

Functions
Operation on ADC hierarchical scope: group regular
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_REG_StartConversion (ADC_TypeDef *ADCx)
Start ADC group regular conversion.
__STATIC_INLINE void | LL_ADC_REG_StopConversionExtTrig (ADC_TypeDef *ADCx)
Stop ADC group regular conversion from external trigger.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadConversionData32 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData12 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 12 bits.

Function Documentation

__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 12 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData12
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 10441 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).

Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData32
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 10426 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_StartConversion ( ADC_TypeDef * ADCx )

Start ADC group regular conversion.

Note:
On this STM32 serie, this function is relevant for both internal trigger (SW start) and external trigger:
  • If ADC trigger has been set to software start, ADC conversion starts immediately.
  • If ADC trigger has been set to external trigger, ADC conversion will start at next trigger event (on the selected trigger edge) following the ADC start conversion command.
Reference Manual to LL API cross reference:
CR2 EXTTRIG LL_ADC_REG_StartConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 10391 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig ( ADC_TypeDef * ADCx )

Stop ADC group regular conversion from external trigger.

Note:
No more ADC conversion will start at next trigger event following the ADC stop conversion command. If a conversion is on-going, it will be completed.
On this STM32 serie, there is no specific command to stop a conversion on-going or to stop ADC converting in continuous mode. These actions can be performed using function LL_ADC_Disable().
Reference Manual to LL API cross reference:
CR2 EXTSEL LL_ADC_REG_StopConversionExtTrig
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 10412 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Operation on ADC hierarchical scope: group injected

Functions
Operation on ADC hierarchical scope: group injected
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_INJ_StartConversion (ADC_TypeDef *ADCx)
Start ADC group injected conversion.
__STATIC_INLINE void | LL_ADC_INJ_StopConversionExtTrig (ADC_TypeDef *ADCx)
Stop ADC group injected conversion from external trigger.
__STATIC_INLINE uint32_t | LL_ADC_INJ_ReadConversionData32 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData12 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 12 bits.

Function Documentation

__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 12 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData12
JDR2 JDATA LL_ADC_INJ_ReadConversionData12
JDR3 JDATA LL_ADC_INJ_ReadConversionData12
JDR4 JDATA LL_ADC_INJ_ReadConversionData12
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 10537 of file stm32f3xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, and ADC_INJ_JDRX_REGOFFSET_MASK.

__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).

Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData32
JDR2 JDATA LL_ADC_INJ_ReadConversionData32
JDR3 JDATA LL_ADC_INJ_ReadConversionData32
JDR4 JDATA LL_ADC_INJ_ReadConversionData32
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 10510 of file stm32f3xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, and ADC_INJ_JDRX_REGOFFSET_MASK.

__STATIC_INLINE void LL_ADC_INJ_StartConversion ( ADC_TypeDef * ADCx )

Start ADC group injected conversion.

Note:
On this STM32 serie, this function is relevant for both internal trigger (SW start) and external trigger:
  • If ADC trigger has been set to software start, ADC conversion starts immediately.
  • If ADC trigger has been set to external trigger, ADC conversion will start at next trigger event (on the selected trigger edge) following the ADC start conversion command.
Reference Manual to LL API cross reference:
CR2 JEXTTRIG LL_ADC_REG_StartConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 10467 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig ( ADC_TypeDef * ADCx )

Stop ADC group injected conversion from external trigger.

Note:
No more ADC conversion will start at next trigger event following the ADC stop conversion command. If a conversion is on-going, it will be completed.
On this STM32 serie, there is no specific command to stop a conversion on-going or to stop ADC converting in continuous mode. These actions can be performed using function LL_ADC_Disable().
Reference Manual to LL API cross reference:
CR2 JEXTSEL LL_ADC_INJ_StopConversionExtTrig
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 10488 of file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC flag management

Functions
ADC flag management
ADC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOS (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOS (ADC_TypeDef *ADCx)
Get flag ADC group injected end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD1 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOS (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOS (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD1 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 1.

Function Documentation

__STATIC_INLINE void LL_ADC_ClearFlag_AWD1 ( ADC_TypeDef * ADCx )

Clear flag ADC analog watchdog 1.

Reference Manual to LL API cross reference:
SR AWD LL_ADC_ClearFlag_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 10633 of file stm32f3xx_ll_adc.h.

References LL_ADC_FLAG_AWD1.

__STATIC_INLINE void LL_ADC_ClearFlag_EOS ( ADC_TypeDef * ADCx )

Clear flag ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
SR EOC LL_ADC_ClearFlag_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 10602 of file stm32f3xx_ll_adc.h.

References LL_ADC_FLAG_EOS.

__STATIC_INLINE void LL_ADC_ClearFlag_JEOS ( ADC_TypeDef * ADCx )

Clear flag ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
SR JEOC LL_ADC_ClearFlag_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 10618 of file stm32f3xx_ll_adc.h.

References LL_ADC_FLAG_JEOS.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1 ( ADC_TypeDef * ADCx )

Get flag ADC analog watchdog 1 flag.

Reference Manual to LL API cross reference:
SR AWD LL_ADC_IsActiveFlag_AWD1
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 10591 of file stm32f3xx_ll_adc.h.

References LL_ADC_FLAG_AWD1.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS ( ADC_TypeDef * ADCx )

Get flag ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
SR EOC LL_ADC_IsActiveFlag_EOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 10560 of file stm32f3xx_ll_adc.h.

References LL_ADC_FLAG_EOS.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS ( ADC_TypeDef * ADCx )

Get flag ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
SR JEOC LL_ADC_IsActiveFlag_JEOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 10576 of file stm32f3xx_ll_adc.h.

References LL_ADC_FLAG_JEOS.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC IT management

Functions
ADC IT management
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_EnableIT_EOS (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOS (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD1 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_DisableIT_EOS (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOS (ADC_TypeDef *ADCx)
Disable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD1 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 1.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD1 (ADC_TypeDef *ADCx)
Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).

Function Documentation

__STATIC_INLINE void LL_ADC_DisableIT_AWD1 ( ADC_TypeDef * ADCx )

Disable interruption ADC analog watchdog 1.

Reference Manual to LL API cross reference:
CR1 AWDIE LL_ADC_EnableIT_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 10725 of file stm32f3xx_ll_adc.h.

References LL_ADC_IT_AWD1.

__STATIC_INLINE void LL_ADC_DisableIT_EOS ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
CR1 EOCIE LL_ADC_DisableIT_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 10694 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_DisableIT_JEOS ( ADC_TypeDef * ADCx )

Disable interruption ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
CR1 JEOCIE LL_ADC_EnableIT_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 10710 of file stm32f3xx_ll_adc.h.

References LL_ADC_IT_JEOS.

__STATIC_INLINE void LL_ADC_EnableIT_AWD1 ( ADC_TypeDef * ADCx )

Enable interruption ADC analog watchdog 1.

Reference Manual to LL API cross reference:
CR1 AWDIE LL_ADC_EnableIT_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 10683 of file stm32f3xx_ll_adc.h.

References LL_ADC_IT_AWD1.

__STATIC_INLINE void LL_ADC_EnableIT_EOS ( ADC_TypeDef * ADCx )

Enable interruption ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
CR1 EOCIE LL_ADC_EnableIT_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 10652 of file stm32f3xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_EnableIT_JEOS ( ADC_TypeDef * ADCx )

Enable interruption ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
CR1 JEOCIE LL_ADC_EnableIT_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 10668 of file stm32f3xx_ll_adc.h.

References LL_ADC_IT_JEOS.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1 ( ADC_TypeDef * ADCx )

Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
CR1 AWDIE LL_ADC_EnableIT_AWD1
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 10770 of file stm32f3xx_ll_adc.h.

References LL_ADC_IT_AWD1.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
CR1 EOCIE LL_ADC_IsEnabledIT_EOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 10737 of file stm32f3xx_ll_adc.h.

References LL_ADC_IT_EOS.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS ( ADC_TypeDef * ADCx )

Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
CR1 JEOCIE LL_ADC_EnableIT_JEOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 10754 of file stm32f3xx_ll_adc.h.

References LL_ADC_IT_JEOS.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
ADC Exported Functions

Functions

ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *ADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_ADC_CommonDeInit ( ADC_Common_TypeDef * ADCxy_COMMON )

De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.

Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC common registers are de-initialized
  • ERROR: not applicable

Definition at line 1504 of file stm32f3xx_ll_adc.c.

References assert_param, LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_ADC1, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_ADC_DeInit ( ADC_TypeDef * ADCx )

De-initialize registers of the selected ADC instance to their default reset values.

Note:
To reset all ADC instances quickly (perform a hard reset), use function LL_ADC_CommonDeInit().
Parameters:
ADCx ADC instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are de-initialized
  • ERROR: ADC registers are not de-initialized

Definition at line 1528 of file stm32f3xx_ll_adc.c.

References assert_param, LL_ADC_Disable(), LL_ADC_FLAG_AWD1, LL_ADC_FLAG_EOS, LL_ADC_FLAG_JEOS, LL_ADC_FLAG_JSTRT, LL_ADC_FLAG_STRT, LL_ADC_INJ_SetTriggerSource(), LL_ADC_INJ_TRIG_SOFTWARE, LL_ADC_IsEnabled(), LL_ADC_REG_SetTriggerSource(), and LL_ADC_REG_TRIG_SOFTWARE.

ErrorStatus LL_ADC_Init | ( | ADC_TypeDef * | ADCx,
 |  | LL_ADC_InitTypeDef * | ADC_InitStruct
 | ) |  |

Initialize some features of ADC instance.

Note:
These parameters have an impact on ADC scope: ADC instance. Affects both group regular and group injected (availability of ADC group injected depends on STM32 families). Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: ADC instance .
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, some other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group regular or group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_REG_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
ADC_InitStruct | Pointer to a LL_ADC_REG_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 1679 of file stm32f3xx_ll_adc.c.

References assert_param, LL_ADC_InitTypeDef::DataAlignment, IS_LL_ADC_DATA_ALIGN, IS_LL_ADC_SCAN_SELECTION, LL_ADC_IsEnabled(), and LL_ADC_InitTypeDef::SequencersScanMode.

ErrorStatus LL_ADC_INJ_Init | ( | ADC_TypeDef * | ADCx,
 |  | LL_ADC_INJ_InitTypeDef * | ADC_INJ_InitStruct
 | ) |  |

Initialize some features of ADC group injected.

Note:
These parameters have an impact on ADC scope: ADC group injected. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "INJ").
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_INJ_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
ADC_INJ_InitStruct | Pointer to a LL_ADC_INJ_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 1899 of file stm32f3xx_ll_adc.c.

References assert_param, IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE, IS_LL_ADC_INJ_SEQ_SCAN_LENGTH, IS_LL_ADC_INJ_TRIG_AUTO, IS_LL_ADC_INJ_TRIG_SOURCE, LL_ADC_INJ_SEQ_SCAN_DISABLE, LL_ADC_INJ_SetSequencerLength(), LL_ADC_IsEnabled(), LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_INJ_InitTypeDef::SequencerDiscont, LL_ADC_INJ_InitTypeDef::SequencerLength, LL_ADC_INJ_InitTypeDef::TrigAuto, and LL_ADC_INJ_InitTypeDef::TriggerSource.

void LL_ADC_INJ_StructInit ( LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct )

Set each LL_ADC_INJ_InitTypeDef field to default value.

Parameters:
ADC_INJ_InitStruct Pointer to a LL_ADC_INJ_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 1976 of file stm32f3xx_ll_adc.c.

References LL_ADC_INJ_SEQ_DISCONT_DISABLE, LL_ADC_INJ_SEQ_SCAN_DISABLE, LL_ADC_INJ_TRIG_INDEPENDENT, LL_ADC_INJ_TRIG_SOFTWARE, LL_ADC_INJ_InitTypeDef::SequencerDiscont, LL_ADC_INJ_InitTypeDef::SequencerLength, LL_ADC_INJ_InitTypeDef::TrigAuto, and LL_ADC_INJ_InitTypeDef::TriggerSource.

ErrorStatus LL_ADC_REG_Init | ( | ADC_TypeDef * | ADCx,
 |  | LL_ADC_REG_InitTypeDef * | ADC_REG_InitStruct
 | ) |  |

Initialize some features of ADC group regular.

Note:
These parameters have an impact on ADC scope: ADC group regular. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "REG").
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group regular or group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_REG_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
ADC_REG_InitStruct | Pointer to a LL_ADC_REG_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 1769 of file stm32f3xx_ll_adc.c.

References assert_param, LL_ADC_REG_InitTypeDef::ContinuousMode, LL_ADC_REG_InitTypeDef::DMATransfer, IS_LL_ADC_REG_CONTINUOUS_MODE, IS_LL_ADC_REG_DMA_TRANSFER, IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE, IS_LL_ADC_REG_SEQ_SCAN_LENGTH, IS_LL_ADC_REG_TRIG_SOURCE, LL_ADC_IsEnabled(), LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_REG_SetSequencerLength(), LL_ADC_REG_InitTypeDef::SequencerDiscont, LL_ADC_REG_InitTypeDef::SequencerLength, and LL_ADC_REG_InitTypeDef::TriggerSource.

void LL_ADC_REG_StructInit ( LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct )

Set each LL_ADC_REG_InitTypeDef field to default value.

Parameters:
ADC_REG_InitStruct Pointer to a LL_ADC_REG_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 1853 of file stm32f3xx_ll_adc.c.

References LL_ADC_REG_InitTypeDef::ContinuousMode, LL_ADC_REG_InitTypeDef::DMATransfer, LL_ADC_REG_CONV_SINGLE, LL_ADC_REG_DMA_TRANSFER_NONE, LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_REG_TRIG_SOFTWARE, LL_ADC_REG_InitTypeDef::SequencerDiscont, LL_ADC_REG_InitTypeDef::SequencerLength, and LL_ADC_REG_InitTypeDef::TriggerSource.

void LL_ADC_StructInit ( LL_ADC_InitTypeDef * ADC_InitStruct )

Set each LL_ADC_InitTypeDef field to default value.

Parameters:
ADC_InitStruct Pointer to a LL_ADC_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 1723 of file stm32f3xx_ll_adc.c.

References LL_ADC_InitTypeDef::DataAlignment, LL_ADC_DATA_ALIGN_RIGHT, LL_ADC_SEQ_SCAN_ENABLE, and LL_ADC_InitTypeDef::SequencersScanMode.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: BUS

Modules
BUS
STM32F3xx_LL_Driver

Modules

BUS Exported Constants
BUS Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for BUS registers.

Register | Bit | Function
AHBENR | ADC12EN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | ADC1EN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | ADC34EN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | CRCEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | DMA1EN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | DMA2EN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | FLITFEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | FMCEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | GPIOAEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | GPIOBEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | GPIOCEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | GPIODEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | GPIOEEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | GPIOFEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | GPIOGEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | GPIOHEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | SRAMEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | TSCEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
AHBRSTR | ADC12RST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | ADC1RST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | ADC34RST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | FMCRST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | GPIOARST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | GPIOBRST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | GPIOCRST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | GPIODRST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | GPIOERST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | GPIOFRST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | GPIOGRST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | GPIOHRST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | TSCRST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
APB1ENR | CANEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | CECEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | DAC1EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | DAC2EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | I2C1EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | I2C2EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | I2C3EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | PWREN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | SPI2EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | SPI3EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM12EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM13EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM14EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM18EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM2EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM3EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM4EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM5EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM6EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM7EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | UART4EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | UART5EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | USART2EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | USART3EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | USBEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | WWDGEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
APB1RSTR | CANRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | CECRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | DAC1RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | DAC2RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | I2C1RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | I2C2RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | I2C3RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | PWRRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | SPI2RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | SPI3RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM12RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM13RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM14RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM18RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM2RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM3RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM4RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM5RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM6RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM7RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | UART4RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | UART5RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | USART2RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | USART3RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | USBRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | WWDGRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
APB2ENR | ADC1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | HRTIM1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | SDADC1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | SDADC2EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | SDADC3EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | SPI1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | SPI4EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | SYSCFGEN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM15EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM16EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM17EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM19EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM20EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM8EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | USART1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
APB2RSTR | ADC1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | HRTIM1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | SDADC1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | SDADC2RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | SDADC3RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | SPI1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | SPI4RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | SYSCFGRST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM15RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM16RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM17RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM19RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM20RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM8RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | USART1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: AHB1 GRP1 PERIPH

Defines
AHB1 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
#define | LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
#define | LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
#define | LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
#define | LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
#define | LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
#define | LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
#define | LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
#define | LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
#define | LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
#define | LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
#define | LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN

Define Documentation

#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU

Definition at line 90 of file stm32f3xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN

Definition at line 100 of file stm32f3xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN

Definition at line 91 of file stm32f3xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN

Definition at line 93 of file stm32f3xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN

Definition at line 96 of file stm32f3xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN

Definition at line 104 of file stm32f3xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN

Definition at line 105 of file stm32f3xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN

Definition at line 106 of file stm32f3xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN

Definition at line 107 of file stm32f3xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN

Definition at line 109 of file stm32f3xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN

Definition at line 111 of file stm32f3xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN

Definition at line 95 of file stm32f3xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN

Definition at line 115 of file stm32f3xx_ll_bus.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: APB1 GRP1 PERIPH

Defines
APB1 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
#define | LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
#define | LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
#define | LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
#define | LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
#define | LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
#define | LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
#define | LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
#define | LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
#define | LL_APB1_GRP1_PERIPH_TIM18 RCC_APB1ENR_TIM18EN
#define | LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
#define | LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
#define | LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
#define | LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
#define | LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
#define | LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
#define | LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
#define | LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
#define | LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN
#define | LL_APB1_GRP1_PERIPH_DAC2 RCC_APB1ENR_DAC2EN
#define | LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
#define | LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DAC1EN
#define | LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN

Define Documentation

#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU

Definition at line 132 of file stm32f3xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN

Definition at line 182 of file stm32f3xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN

Definition at line 190 of file stm32f3xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DAC1EN

Definition at line 188 of file stm32f3xx_ll_bus.h.

Referenced by LL_DAC_DeInit().

#define LL_APB1_GRP1_PERIPH_DAC2 RCC_APB1ENR_DAC2EN

Definition at line 185 of file stm32f3xx_ll_bus.h.

Referenced by LL_DAC_DeInit().

#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN

Definition at line 174 of file stm32f3xx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN

Definition at line 176 of file stm32f3xx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN

Definition at line 187 of file stm32f3xx_ll_bus.h.

Referenced by LL_PWR_DeInit().

#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN

Definition at line 161 of file stm32f3xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN

Definition at line 164 of file stm32f3xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN

Definition at line 148 of file stm32f3xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN

Definition at line 151 of file stm32f3xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN

Definition at line 154 of file stm32f3xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM18 RCC_APB1ENR_TIM18EN

Definition at line 157 of file stm32f3xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN

Definition at line 133 of file stm32f3xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN

Definition at line 135 of file stm32f3xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN

Definition at line 138 of file stm32f3xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN

Definition at line 141 of file stm32f3xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN

Definition at line 143 of file stm32f3xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN

Definition at line 145 of file stm32f3xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN

Definition at line 166 of file stm32f3xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN

Definition at line 167 of file stm32f3xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN

Definition at line 179 of file stm32f3xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN

Definition at line 159 of file stm32f3xx_ll_bus.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: APB2 GRP1 PERIPH

Defines
APB2 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
#define | LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
#define | LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
#define | LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
#define | LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
#define | LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
#define | LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
#define | LL_APB2_GRP1_PERIPH_TIM19 RCC_APB2ENR_TIM19EN
#define | LL_APB2_GRP1_PERIPH_SDADC1 RCC_APB2ENR_SDADC1EN
#define | LL_APB2_GRP1_PERIPH_SDADC2 RCC_APB2ENR_SDADC2EN
#define | LL_APB2_GRP1_PERIPH_SDADC3 RCC_APB2ENR_SDADC3EN

Define Documentation

#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN

Definition at line 205 of file stm32f3xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit().

#define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU

Definition at line 202 of file stm32f3xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_SDADC1 RCC_APB2ENR_SDADC1EN

Definition at line 233 of file stm32f3xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_SDADC2 RCC_APB2ENR_SDADC2EN

Definition at line 236 of file stm32f3xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_SDADC3 RCC_APB2ENR_SDADC3EN

Definition at line 239 of file stm32f3xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN

Definition at line 211 of file stm32f3xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN

Definition at line 203 of file stm32f3xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN

Definition at line 220 of file stm32f3xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN

Definition at line 221 of file stm32f3xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN

Definition at line 222 of file stm32f3xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM19 RCC_APB2ENR_TIM19EN

Definition at line 224 of file stm32f3xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN

Definition at line 216 of file stm32f3xx_ll_bus.h.

Referenced by LL_USART_DeInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: AHB1

Functions
AHB1
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
Enable AHB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
Disable AHB1 peripherals clock.
__STATIC_INLINE void | LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
Force AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB1 peripherals reset.

Function Documentation

__STATIC_INLINE void LL_AHB1_GRP1_DisableClock ( uint32_t Periphs )

Disable AHB1 peripherals clock.

Reference Manual to LL API cross reference:
AHBENR DMA1EN LL_AHB1_GRP1_DisableClock
AHBENR DMA2EN LL_AHB1_GRP1_DisableClock
AHBENR SRAMEN LL_AHB1_GRP1_DisableClock
AHBENR FLITFEN LL_AHB1_GRP1_DisableClock
AHBENR FMCEN LL_AHB1_GRP1_DisableClock
AHBENR CRCEN LL_AHB1_GRP1_DisableClock
AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock
AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock
AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock
AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock
AHBENR GPIODEN LL_AHB1_GRP1_DisableClock
AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock
AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock
AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock
AHBENR TSCEN LL_AHB1_GRP1_DisableClock
AHBENR ADC1EN LL_AHB1_GRP1_DisableClock
AHBENR ADC12EN LL_AHB1_GRP1_DisableClock
AHBENR ADC34EN LL_AHB1_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2 (*)
  • LL_AHB1_GRP1_PERIPH_SRAM
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_FMC (*)
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_GPIOH (*)
  • LL_AHB1_GRP1_PERIPH_GPIOA
  • LL_AHB1_GRP1_PERIPH_GPIOB
  • LL_AHB1_GRP1_PERIPH_GPIOC
  • LL_AHB1_GRP1_PERIPH_GPIOD
  • LL_AHB1_GRP1_PERIPH_GPIOE (*)
  • LL_AHB1_GRP1_PERIPH_GPIOF
  • LL_AHB1_GRP1_PERIPH_GPIOG (*)
  • LL_AHB1_GRP1_PERIPH_TSC
  • LL_AHB1_GRP1_PERIPH_ADC1 (*)
  • LL_AHB1_GRP1_PERIPH_ADC12 (*)
  • LL_AHB1_GRP1_PERIPH_ADC34 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 403 of file stm32f3xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_EnableClock ( uint32_t Periphs )

Enable AHB1 peripherals clock.

Reference Manual to LL API cross reference:
AHBENR DMA1EN LL_AHB1_GRP1_EnableClock
AHBENR DMA2EN LL_AHB1_GRP1_EnableClock
AHBENR SRAMEN LL_AHB1_GRP1_EnableClock
AHBENR FLITFEN LL_AHB1_GRP1_EnableClock
AHBENR FMCEN LL_AHB1_GRP1_EnableClock
AHBENR CRCEN LL_AHB1_GRP1_EnableClock
AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock
AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock
AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock
AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock
AHBENR GPIODEN LL_AHB1_GRP1_EnableClock
AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock
AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock
AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock
AHBENR TSCEN LL_AHB1_GRP1_EnableClock
AHBENR ADC1EN LL_AHB1_GRP1_EnableClock
AHBENR ADC12EN LL_AHB1_GRP1_EnableClock
AHBENR ADC34EN LL_AHB1_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2 (*)
  • LL_AHB1_GRP1_PERIPH_SRAM
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_FMC (*)
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_GPIOH (*)
  • LL_AHB1_GRP1_PERIPH_GPIOA
  • LL_AHB1_GRP1_PERIPH_GPIOB
  • LL_AHB1_GRP1_PERIPH_GPIOC
  • LL_AHB1_GRP1_PERIPH_GPIOD
  • LL_AHB1_GRP1_PERIPH_GPIOE (*)
  • LL_AHB1_GRP1_PERIPH_GPIOF
  • LL_AHB1_GRP1_PERIPH_GPIOG (*)
  • LL_AHB1_GRP1_PERIPH_TSC
  • LL_AHB1_GRP1_PERIPH_ADC1 (*)
  • LL_AHB1_GRP1_PERIPH_ADC12 (*)
  • LL_AHB1_GRP1_PERIPH_ADC34 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 303 of file stm32f3xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_ForceReset ( uint32_t Periphs )

Force AHB1 peripherals reset.

Reference Manual to LL API cross reference:
AHBRSTR FMCRST LL_AHB1_GRP1_ForceReset
AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset
AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset
AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset
AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset
AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset
AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset
AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset
AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset
AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset
AHBRSTR ADC1RST LL_AHB1_GRP1_ForceReset
AHBRSTR ADC12RST LL_AHB1_GRP1_ForceReset
AHBRSTR ADC34RST LL_AHB1_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_ALL
  • LL_AHB1_GRP1_PERIPH_FMC (*)
  • LL_AHB1_GRP1_PERIPH_GPIOH (*)
  • LL_AHB1_GRP1_PERIPH_GPIOA
  • LL_AHB1_GRP1_PERIPH_GPIOB
  • LL_AHB1_GRP1_PERIPH_GPIOC
  • LL_AHB1_GRP1_PERIPH_GPIOD
  • LL_AHB1_GRP1_PERIPH_GPIOE (*)
  • LL_AHB1_GRP1_PERIPH_GPIOF
  • LL_AHB1_GRP1_PERIPH_GPIOG (*)
  • LL_AHB1_GRP1_PERIPH_TSC
  • LL_AHB1_GRP1_PERIPH_ADC1 (*)
  • LL_AHB1_GRP1_PERIPH_ADC12 (*)
  • LL_AHB1_GRP1_PERIPH_ADC34 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 442 of file stm32f3xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if AHB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock
AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock
AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock
AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock
AHBENR FMCEN LL_AHB1_GRP1_IsEnabledClock
AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock
AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock
AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock
AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock
AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock
AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock
AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock
AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock
AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock
AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock
AHBENR ADC1EN LL_AHB1_GRP1_IsEnabledClock
AHBENR ADC12EN LL_AHB1_GRP1_IsEnabledClock
AHBENR ADC34EN LL_AHB1_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2 (*)
  • LL_AHB1_GRP1_PERIPH_SRAM
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_FMC (*)
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_GPIOH (*)
  • LL_AHB1_GRP1_PERIPH_GPIOA
  • LL_AHB1_GRP1_PERIPH_GPIOB
  • LL_AHB1_GRP1_PERIPH_GPIOC
  • LL_AHB1_GRP1_PERIPH_GPIOD
  • LL_AHB1_GRP1_PERIPH_GPIOE (*)
  • LL_AHB1_GRP1_PERIPH_GPIOF
  • LL_AHB1_GRP1_PERIPH_GPIOG (*)
  • LL_AHB1_GRP1_PERIPH_TSC
  • LL_AHB1_GRP1_PERIPH_ADC1 (*)
  • LL_AHB1_GRP1_PERIPH_ADC12 (*)
  • LL_AHB1_GRP1_PERIPH_ADC34 (*)
(*) value not defined in all devices.
Return values:
State of Periphs (1 or 0).

Definition at line 355 of file stm32f3xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset ( uint32_t Periphs )

Release AHB1 peripherals reset.

Reference Manual to LL API cross reference:
AHBRSTR FMCRST LL_AHB1_GRP1_ReleaseReset
AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset
AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset
AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset
AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset
AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset
AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset
AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset
AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset
AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset
AHBRSTR ADC1RST LL_AHB1_GRP1_ReleaseReset
AHBRSTR ADC12RST LL_AHB1_GRP1_ReleaseReset
AHBRSTR ADC34RST LL_AHB1_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_ALL
  • LL_AHB1_GRP1_PERIPH_FMC (*)
  • LL_AHB1_GRP1_PERIPH_GPIOH (*)
  • LL_AHB1_GRP1_PERIPH_GPIOA
  • LL_AHB1_GRP1_PERIPH_GPIOB
  • LL_AHB1_GRP1_PERIPH_GPIOC
  • LL_AHB1_GRP1_PERIPH_GPIOD
  • LL_AHB1_GRP1_PERIPH_GPIOE (*)
  • LL_AHB1_GRP1_PERIPH_GPIOF
  • LL_AHB1_GRP1_PERIPH_GPIOG (*)
  • LL_AHB1_GRP1_PERIPH_TSC
  • LL_AHB1_GRP1_PERIPH_ADC1 (*)
  • LL_AHB1_GRP1_PERIPH_ADC12 (*)
  • LL_AHB1_GRP1_PERIPH_ADC34 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 481 of file stm32f3xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: APB1

Functions
APB1
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_APB1_GRP1_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP1_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.

Function Documentation

__STATIC_INLINE void LL_APB1_GRP1_DisableClock ( uint32_t Periphs )

Disable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1ENR TIM2EN LL_APB1_GRP1_DisableClock
APB1ENR TIM3EN LL_APB1_GRP1_DisableClock
APB1ENR TIM4EN LL_APB1_GRP1_DisableClock
APB1ENR TIM5EN LL_APB1_GRP1_DisableClock
APB1ENR TIM6EN LL_APB1_GRP1_DisableClock
APB1ENR TIM7EN LL_APB1_GRP1_DisableClock
APB1ENR TIM12EN LL_APB1_GRP1_DisableClock
APB1ENR TIM13EN LL_APB1_GRP1_DisableClock
APB1ENR TIM14EN LL_APB1_GRP1_DisableClock
APB1ENR TIM18EN LL_APB1_GRP1_DisableClock
APB1ENR WWDGEN LL_APB1_GRP1_DisableClock
APB1ENR SPI2EN LL_APB1_GRP1_DisableClock
APB1ENR SPI3EN LL_APB1_GRP1_DisableClock
APB1ENR USART2EN LL_APB1_GRP1_DisableClock
APB1ENR USART3EN LL_APB1_GRP1_DisableClock
APB1ENR UART4EN LL_APB1_GRP1_DisableClock
APB1ENR UART5EN LL_APB1_GRP1_DisableClock
APB1ENR I2C1EN LL_APB1_GRP1_DisableClock
APB1ENR I2C2EN LL_APB1_GRP1_DisableClock
APB1ENR USBEN LL_APB1_GRP1_DisableClock
APB1ENR CANEN LL_APB1_GRP1_DisableClock
APB1ENR DAC2EN LL_APB1_GRP1_DisableClock
APB1ENR PWREN LL_APB1_GRP1_DisableClock
APB1ENR DAC1EN LL_APB1_GRP1_DisableClock
APB1ENR CECEN LL_APB1_GRP1_DisableClock
APB1ENR I2C3EN LL_APB1_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3 (*)
  • LL_APB1_GRP1_PERIPH_TIM4 (*)
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7 (*)
  • LL_APB1_GRP1_PERIPH_TIM12 (*)
  • LL_APB1_GRP1_PERIPH_TIM13 (*)
  • LL_APB1_GRP1_PERIPH_TIM14 (*)
  • LL_APB1_GRP1_PERIPH_TIM18 (*)
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2 (*)
  • LL_APB1_GRP1_PERIPH_SPI3 (*)
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2 (*)
  • LL_APB1_GRP1_PERIPH_USB (*)
  • LL_APB1_GRP1_PERIPH_CAN (*)
  • LL_APB1_GRP1_PERIPH_DAC2 (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1
  • LL_APB1_GRP1_PERIPH_CEC (*)
  • LL_APB1_GRP1_PERIPH_I2C3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 685 of file stm32f3xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_EnableClock ( uint32_t Periphs )

Enable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1ENR TIM2EN LL_APB1_GRP1_EnableClock
APB1ENR TIM3EN LL_APB1_GRP1_EnableClock
APB1ENR TIM4EN LL_APB1_GRP1_EnableClock
APB1ENR TIM5EN LL_APB1_GRP1_EnableClock
APB1ENR TIM6EN LL_APB1_GRP1_EnableClock
APB1ENR TIM7EN LL_APB1_GRP1_EnableClock
APB1ENR TIM12EN LL_APB1_GRP1_EnableClock
APB1ENR TIM13EN LL_APB1_GRP1_EnableClock
APB1ENR TIM14EN LL_APB1_GRP1_EnableClock
APB1ENR TIM18EN LL_APB1_GRP1_EnableClock
APB1ENR WWDGEN LL_APB1_GRP1_EnableClock
APB1ENR SPI2EN LL_APB1_GRP1_EnableClock
APB1ENR SPI3EN LL_APB1_GRP1_EnableClock
APB1ENR USART2EN LL_APB1_GRP1_EnableClock
APB1ENR USART3EN LL_APB1_GRP1_EnableClock
APB1ENR UART4EN LL_APB1_GRP1_EnableClock
APB1ENR UART5EN LL_APB1_GRP1_EnableClock
APB1ENR I2C1EN LL_APB1_GRP1_EnableClock
APB1ENR I2C2EN LL_APB1_GRP1_EnableClock
APB1ENR USBEN LL_APB1_GRP1_EnableClock
APB1ENR CANEN LL_APB1_GRP1_EnableClock
APB1ENR DAC2EN LL_APB1_GRP1_EnableClock
APB1ENR PWREN LL_APB1_GRP1_EnableClock
APB1ENR DAC1EN LL_APB1_GRP1_EnableClock
APB1ENR CECEN LL_APB1_GRP1_EnableClock
APB1ENR I2C3EN LL_APB1_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3 (*)
  • LL_APB1_GRP1_PERIPH_TIM4 (*)
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7 (*)
  • LL_APB1_GRP1_PERIPH_TIM12 (*)
  • LL_APB1_GRP1_PERIPH_TIM13 (*)
  • LL_APB1_GRP1_PERIPH_TIM14 (*)
  • LL_APB1_GRP1_PERIPH_TIM18 (*)
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2 (*)
  • LL_APB1_GRP1_PERIPH_SPI3 (*)
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2 (*)
  • LL_APB1_GRP1_PERIPH_USB (*)
  • LL_APB1_GRP1_PERIPH_CAN (*)
  • LL_APB1_GRP1_PERIPH_DAC2 (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1
  • LL_APB1_GRP1_PERIPH_CEC (*)
  • LL_APB1_GRP1_PERIPH_I2C3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 553 of file stm32f3xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_ForceReset ( uint32_t Periphs )

Force APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM18RST LL_APB1_GRP1_ForceReset
APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset
APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset
APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset
APB1RSTR USART2RST LL_APB1_GRP1_ForceReset
APB1RSTR USART3RST LL_APB1_GRP1_ForceReset
APB1RSTR UART4RST LL_APB1_GRP1_ForceReset
APB1RSTR UART5RST LL_APB1_GRP1_ForceReset
APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset
APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset
APB1RSTR USBRST LL_APB1_GRP1_ForceReset
APB1RSTR CANRST LL_APB1_GRP1_ForceReset
APB1RSTR DAC2RST LL_APB1_GRP1_ForceReset
APB1RSTR PWRRST LL_APB1_GRP1_ForceReset
APB1RSTR DAC1RST LL_APB1_GRP1_ForceReset
APB1RSTR CECRST LL_APB1_GRP1_ForceReset
APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_ALL
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3 (*)
  • LL_APB1_GRP1_PERIPH_TIM4 (*)
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7 (*)
  • LL_APB1_GRP1_PERIPH_TIM12 (*)
  • LL_APB1_GRP1_PERIPH_TIM13 (*)
  • LL_APB1_GRP1_PERIPH_TIM14 (*)
  • LL_APB1_GRP1_PERIPH_TIM18 (*)
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2 (*)
  • LL_APB1_GRP1_PERIPH_SPI3 (*)
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2 (*)
  • LL_APB1_GRP1_PERIPH_USB (*)
  • LL_APB1_GRP1_PERIPH_CAN (*)
  • LL_APB1_GRP1_PERIPH_DAC2 (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1
  • LL_APB1_GRP1_PERIPH_CEC (*)
  • LL_APB1_GRP1_PERIPH_I2C3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 750 of file stm32f3xx_ll_bus.h.

Referenced by LL_DAC_DeInit(), LL_I2C_DeInit(), LL_PWR_DeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if APB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM18EN LL_APB1_GRP1_IsEnabledClock
APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock
APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock
APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock
APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock
APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock
APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock
APB1ENR DAC2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock
APB1ENR DAC1EN LL_APB1_GRP1_IsEnabledClock
APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock
APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3 (*)
  • LL_APB1_GRP1_PERIPH_TIM4 (*)
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7 (*)
  • LL_APB1_GRP1_PERIPH_TIM12 (*)
  • LL_APB1_GRP1_PERIPH_TIM13 (*)
  • LL_APB1_GRP1_PERIPH_TIM14 (*)
  • LL_APB1_GRP1_PERIPH_TIM18 (*)
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2 (*)
  • LL_APB1_GRP1_PERIPH_SPI3 (*)
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2 (*)
  • LL_APB1_GRP1_PERIPH_USB (*)
  • LL_APB1_GRP1_PERIPH_CAN (*)
  • LL_APB1_GRP1_PERIPH_DAC2 (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1
  • LL_APB1_GRP1_PERIPH_CEC (*)
  • LL_APB1_GRP1_PERIPH_I2C3 (*)
(*) value not defined in all devices.
Return values:
State of Periphs (1 or 0).

Definition at line 621 of file stm32f3xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset ( uint32_t Periphs )

Release APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM18RST LL_APB1_GRP1_ReleaseReset
APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset
APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset
APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset
APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset
APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset
APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset
APB1RSTR DAC2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset
APB1RSTR DAC1RST LL_APB1_GRP1_ReleaseReset
APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset
APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_ALL
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3 (*)
  • LL_APB1_GRP1_PERIPH_TIM4 (*)
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7 (*)
  • LL_APB1_GRP1_PERIPH_TIM12 (*)
  • LL_APB1_GRP1_PERIPH_TIM13 (*)
  • LL_APB1_GRP1_PERIPH_TIM14 (*)
  • LL_APB1_GRP1_PERIPH_TIM18 (*)
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2 (*)
  • LL_APB1_GRP1_PERIPH_SPI3 (*)
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2 (*)
  • LL_APB1_GRP1_PERIPH_USB (*)
  • LL_APB1_GRP1_PERIPH_CAN (*)
  • LL_APB1_GRP1_PERIPH_DAC2 (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1
  • LL_APB1_GRP1_PERIPH_CEC (*)
  • LL_APB1_GRP1_PERIPH_I2C3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 815 of file stm32f3xx_ll_bus.h.

Referenced by LL_DAC_DeInit(), LL_I2C_DeInit(), LL_PWR_DeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: APB2

Functions
APB2
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_APB2_GRP1_EnableClock (uint32_t Periphs)
Enable APB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClock (uint32_t Periphs)
Disable APB2 peripherals clock.
__STATIC_INLINE void | LL_APB2_GRP1_ForceReset (uint32_t Periphs)
Force APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
Release APB2 peripherals reset.

Function Documentation

__STATIC_INLINE void LL_APB2_GRP1_DisableClock ( uint32_t Periphs )

Disable APB2 peripherals clock.

Reference Manual to LL API cross reference:
APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock
APB2ENR ADC1EN LL_APB2_GRP1_DisableClock
APB2ENR TIM1EN LL_APB2_GRP1_DisableClock
APB2ENR SPI1EN LL_APB2_GRP1_DisableClock
APB2ENR TIM8EN LL_APB2_GRP1_DisableClock
APB2ENR USART1EN LL_APB2_GRP1_DisableClock
APB2ENR SPI4EN LL_APB2_GRP1_DisableClock
APB2ENR TIM15EN LL_APB2_GRP1_DisableClock
APB2ENR TIM16EN LL_APB2_GRP1_DisableClock
APB2ENR TIM17EN LL_APB2_GRP1_DisableClock
APB2ENR TIM19EN LL_APB2_GRP1_DisableClock
APB2ENR TIM20EN LL_APB2_GRP1_DisableClock
APB2ENR HRTIM1EN LL_APB2_GRP1_DisableClock
APB2ENR SDADC1EN LL_APB2_GRP1_DisableClock
APB2ENR SDADC2EN LL_APB2_GRP1_DisableClock
APB2ENR SDADC3EN LL_APB2_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_ADC1 (*)
  • LL_APB2_GRP1_PERIPH_TIM1 (*)
  • LL_APB2_GRP1_PERIPH_SPI1 (*)
  • LL_APB2_GRP1_PERIPH_TIM8 (*)
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_SPI4 (*)
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_TIM19 (*)
  • LL_APB2_GRP1_PERIPH_TIM20 (*)
  • LL_APB2_GRP1_PERIPH_HRTIM1 (*)
  • LL_APB2_GRP1_PERIPH_SDADC1 (*)
  • LL_APB2_GRP1_PERIPH_SDADC2 (*)
  • LL_APB2_GRP1_PERIPH_SDADC3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 959 of file stm32f3xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_EnableClock ( uint32_t Periphs )

Enable APB2 peripherals clock.

Reference Manual to LL API cross reference:
APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock
APB2ENR ADC1EN LL_APB2_GRP1_EnableClock
APB2ENR TIM1EN LL_APB2_GRP1_EnableClock
APB2ENR SPI1EN LL_APB2_GRP1_EnableClock
APB2ENR TIM8EN LL_APB2_GRP1_EnableClock
APB2ENR USART1EN LL_APB2_GRP1_EnableClock
APB2ENR SPI4EN LL_APB2_GRP1_EnableClock
APB2ENR TIM15EN LL_APB2_GRP1_EnableClock
APB2ENR TIM16EN LL_APB2_GRP1_EnableClock
APB2ENR TIM17EN LL_APB2_GRP1_EnableClock
APB2ENR TIM19EN LL_APB2_GRP1_EnableClock
APB2ENR TIM20EN LL_APB2_GRP1_EnableClock
APB2ENR HRTIM1EN LL_APB2_GRP1_EnableClock
APB2ENR SDADC1EN LL_APB2_GRP1_EnableClock
APB2ENR SDADC2EN LL_APB2_GRP1_EnableClock
APB2ENR SDADC3EN LL_APB2_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_ADC1 (*)
  • LL_APB2_GRP1_PERIPH_TIM1 (*)
  • LL_APB2_GRP1_PERIPH_SPI1 (*)
  • LL_APB2_GRP1_PERIPH_TIM8 (*)
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_SPI4 (*)
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_TIM19 (*)
  • LL_APB2_GRP1_PERIPH_TIM20 (*)
  • LL_APB2_GRP1_PERIPH_HRTIM1 (*)
  • LL_APB2_GRP1_PERIPH_SDADC1 (*)
  • LL_APB2_GRP1_PERIPH_SDADC2 (*)
  • LL_APB2_GRP1_PERIPH_SDADC3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 867 of file stm32f3xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_ForceReset ( uint32_t Periphs )

Force APB2 peripherals reset.

Reference Manual to LL API cross reference:
APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset
APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset
APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset
APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM19RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset
APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset
APB2RSTR SDADC1RST LL_APB2_GRP1_ForceReset
APB2RSTR SDADC2RST LL_APB2_GRP1_ForceReset
APB2RSTR SDADC3RST LL_APB2_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_ALL
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_ADC1 (*)
  • LL_APB2_GRP1_PERIPH_TIM1 (*)
  • LL_APB2_GRP1_PERIPH_SPI1 (*)
  • LL_APB2_GRP1_PERIPH_TIM8 (*)
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_SPI4 (*)
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_TIM19 (*)
  • LL_APB2_GRP1_PERIPH_TIM20 (*)
  • LL_APB2_GRP1_PERIPH_HRTIM1 (*)
  • LL_APB2_GRP1_PERIPH_SDADC1 (*)
  • LL_APB2_GRP1_PERIPH_SDADC2 (*)
  • LL_APB2_GRP1_PERIPH_SDADC3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1004 of file stm32f3xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if APB2 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock
APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock
APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM19EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM20EN LL_APB2_GRP1_IsEnabledClock
APB2ENR HRTIM1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SDADC1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SDADC2EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SDADC3EN LL_APB2_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_ADC1 (*)
  • LL_APB2_GRP1_PERIPH_TIM1 (*)
  • LL_APB2_GRP1_PERIPH_SPI1 (*)
  • LL_APB2_GRP1_PERIPH_TIM8 (*)
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_SPI4 (*)
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_TIM19 (*)
  • LL_APB2_GRP1_PERIPH_TIM20 (*)
  • LL_APB2_GRP1_PERIPH_HRTIM1 (*)
  • LL_APB2_GRP1_PERIPH_SDADC1 (*)
  • LL_APB2_GRP1_PERIPH_SDADC2 (*)
  • LL_APB2_GRP1_PERIPH_SDADC3 (*)
(*) value not defined in all devices.
Return values:
State of Periphs (1 or 0).

Definition at line 915 of file stm32f3xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset ( uint32_t Periphs )

Release APB2 peripherals reset.

Reference Manual to LL API cross reference:
APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset
APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset
APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM19RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM20RST LL_APB2_GRP1_ReleaseReset
APB2RSTR HRTIM1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR SDADC1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR SDADC2RST LL_APB2_GRP1_ReleaseReset
APB2RSTR SDADC3RST LL_APB2_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_ALL
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_ADC1 (*)
  • LL_APB2_GRP1_PERIPH_TIM1 (*)
  • LL_APB2_GRP1_PERIPH_SPI1 (*)
  • LL_APB2_GRP1_PERIPH_TIM8 (*)
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_SPI4 (*)
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_TIM19 (*)
  • LL_APB2_GRP1_PERIPH_TIM20 (*)
  • LL_APB2_GRP1_PERIPH_HRTIM1 (*)
  • LL_APB2_GRP1_PERIPH_SDADC1 (*)
  • LL_APB2_GRP1_PERIPH_SDADC2 (*)
  • LL_APB2_GRP1_PERIPH_SDADC3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1049 of file stm32f3xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP

Modules
COMP
STM32F3xx_LL_Driver

Modules

COMP Private Constants
COMP Private Macros
COMP Exported Init structure
COMP Exported Constants
COMP Exported Macros
COMP Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for COMP registers.

Register | Bit | Function
CSR | COMP1EN | LL_COMP_Disable
 |  | LL_COMP_Enable
 |  | LL_COMP_IsEnabled
 | COMP1HYST | LL_COMP_GetInputHysteresis
 |  | LL_COMP_SetInputHysteresis
 | COMP1INSEL | LL_COMP_ConfigInputs
 |  | LL_COMP_GetInputPlus
 |  | LL_COMP_SetInputPlus
 | COMP1LOCK | LL_COMP_IsLocked
 |  | LL_COMP_Lock
 | COMP1MODE | LL_COMP_GetPowerMode
 |  | LL_COMP_SetPowerMode
 | COMP1OUT | LL_COMP_ReadOutputLevel
 | COMP1OUTSEL | LL_COMP_GetOutputSelection
 |  | LL_COMP_SetOutputSelection
 | COMP1POL | LL_COMP_GetOutputPolarity
 |  | LL_COMP_SetOutputPolarity
 | COMP1SW1 | LL_COMP_ConfigInputs
 |  | LL_COMP_GetInputMinus
 |  | LL_COMP_SetInputMinus
 | COMP2INSEL | LL_COMP_ConfigInputs
 |  | LL_COMP_GetInputPlus
 |  | LL_COMP_SetInputPlus
 | WNDWEN | LL_COMP_GetCommonWindowMode
 |  | LL_COMP_SetCommonWindowMode
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STM32F373xC HAL User Manual: COMP Private Constants

Defines
COMP Private Constants
COMP

Defines

#define | COMPX_BASE COMP_BASE
#define | COMPX (COMP1 - COMP2)
#define | LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(COMP_CSR_COMP1OUT) */

Define Documentation

#define COMPX (COMP1 - COMP2)

Definition at line 1454 of file stm32f3xx_ll_comp.h.

#define COMPX_BASE COMP_BASE

Definition at line 1453 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(COMP_CSR_COMP1OUT) */

Definition at line 1457 of file stm32f3xx_ll_comp.h.

Referenced by LL_COMP_ReadOutputLevel().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Private Macros

Defines
COMP Private Macros
COMP

Defines

#define | IS_LL_COMP_POWER_MODE(__POWER_MODE__)
#define | IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)
#define | IS_LL_COMP_OUTPUT_SELECTION(__OUTPUT_SELECTION__)
#define | IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)
#define | __COMP_IS_INSTANCE_ODD(__COMP_INSTANCE__) ((~(((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) >> 1U)) & 0x00000001)
Driver macro reserved for internal use: if COMP instance selected is odd (COMP1, COMP3, ...), return value '1', else return '0'.
#define | __COMP_IS_INSTANCE_EVEN(__COMP_INSTANCE__) (((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) >> 1U)
Driver macro reserved for internal use: if COMP instance selected is even (COMP2, COMP4, ...), return value '1', else return '0'.
#define | __COMP_BITOFFSET_INSTANCE(__COMP_INSTANCE__) (((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) << 3U)
Driver macro reserved for internal use: from COMP instance selected, set offset of bits into COMP register.

Define Documentation

#define __COMP_BITOFFSET_INSTANCE ( __COMP_INSTANCE__ ) (((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) << 3U)

Driver macro reserved for internal use: from COMP instance selected, set offset of bits into COMP register.

Note:
Since both COMP instances are sharing the same register with 2 area of bits with an offset of 16 bits, this function returns value "0" if COMP1 is selected and "16" if COMP2 is selected.
Parameters:
__COMP_INSTANCE__ COMP instance
Return values:
Bits offset in register 32 bits

Definition at line 1496 of file stm32f3xx_ll_comp.h.

Referenced by LL_COMP_ConfigInputs(), LL_COMP_DeInit(), LL_COMP_Disable(), LL_COMP_Enable(), LL_COMP_GetInputHysteresis(), LL_COMP_GetInputMinus(), LL_COMP_GetInputPlus(), LL_COMP_GetOutputPolarity(), LL_COMP_GetOutputSelection(), LL_COMP_GetPowerMode(), LL_COMP_Init(), LL_COMP_IsEnabled(), LL_COMP_IsLocked(), LL_COMP_Lock(), LL_COMP_ReadOutputLevel(), LL_COMP_SetInputHysteresis(), LL_COMP_SetInputMinus(), LL_COMP_SetInputPlus(), LL_COMP_SetOutputPolarity(), LL_COMP_SetOutputSelection(), and LL_COMP_SetPowerMode().

#define __COMP_IS_INSTANCE_EVEN ( __COMP_INSTANCE__ ) (((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) >> 1U)

Driver macro reserved for internal use: if COMP instance selected is even (COMP2, COMP4, ...), return value '1', else return '0'.

Parameters:
__COMP_INSTANCE__ COMP instance
Return values:
If COMP instance is even, value '1'. Else, value '0'.

Definition at line 1483 of file stm32f3xx_ll_comp.h.

#define __COMP_IS_INSTANCE_ODD ( __COMP_INSTANCE__ ) ((~(((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) >> 1U)) & 0x00000001)

Driver macro reserved for internal use: if COMP instance selected is odd (COMP1, COMP3, ...), return value '1', else return '0'.

Parameters:
__COMP_INSTANCE__ COMP instance
Return values:
If COMP instance is odd, value '1'. Else, value '0'.

Definition at line 1474 of file stm32f3xx_ll_comp.h.

Referenced by LL_COMP_ConfigInputs(), and LL_COMP_SetInputPlus().

#define IS_LL_COMP_INPUT_HYSTERESIS ( __INPUT_HYSTERESIS__ )
Value:
(   ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)                      \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW)                       \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM)                    \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH)                      \
  )

Definition at line 817 of file stm32f3xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_INPUT_MINUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_MINUS__
 | ) |
Value:
(   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                      \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3)                           \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4)                           \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1)                      \
  )

Definition at line 803 of file stm32f3xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_INPUT_PLUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_PLUS__
 | ) |
Value:
(((__COMP_INSTANCE__) == COMP1)                                              \
    ? (                                                                        \
          ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                         \
       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1)                    \
      )                                                                        \
      :                                                                        \
      (                                                                        \
          ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                         \
      )                                                                        \
  )

Definition at line 787 of file stm32f3xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_OUTPUT_POLARITY ( __POLARITY__ )
Value:
(   ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED)                        \
   || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED)                           \
  )

Definition at line 838 of file stm32f3xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_OUTPUT_SELECTION ( __OUTPUT_SELECTION__ )
Value:
(   ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE)                          \
   || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_BKIN)                    \
   || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC1)                      \
   || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_OCCLR)                    \
   || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4)                      \
   || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR)                    \
   || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP2)                \
   || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP2)              \
  )

Definition at line 827 of file stm32f3xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_POWER_MODE ( __POWER_MODE__ )
Value:
(   ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)                        \
   || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED)                      \
   || ((__POWER_MODE__) == LL_COMP_POWERMODE_LOWPOWER)                         \
   || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER)                    \
  )

Definition at line 778 of file stm32f3xx_ll_comp.c.

Referenced by LL_COMP_Init().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_COMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_COMP_InitTypeDef Struct Reference
COMP Exported Init structure

Structure definition of some features of COMP instance. More...

#include <stm32f3xx_ll_comp.h>

Data Fields

uint32_t | PowerMode
uint32_t | InputPlus
uint32_t | InputMinus
uint32_t | InputHysteresis
uint32_t | OutputSelection
uint32_t | OutputPolarity

Detailed Description

Structure definition of some features of COMP instance.

Definition at line 1512 of file stm32f3xx_ll_comp.h.

Field Documentation

uint32_t LL_COMP_InitTypeDef::InputHysteresis

Set comparator hysteresis mode of the input minus. This parameter can be a value of Comparator input - Hysteresis

This feature can be modified afterwards using unitary function LL_COMP_SetInputHysteresis().

Definition at line 1529 of file stm32f3xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::InputMinus

Set comparator input minus (inverting input). This parameter can be a value of Comparator inputs - Input minus (input inverting) selection

This feature can be modified afterwards using unitary function LL_COMP_SetInputMinus().

Definition at line 1524 of file stm32f3xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::InputPlus

Set comparator input plus (non-inverting input). This parameter can be a value of Comparator inputs - Input plus (input non-inverting) selection

This feature can be modified afterwards using unitary function LL_COMP_SetInputPlus().

Definition at line 1519 of file stm32f3xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::OutputPolarity

Set comparator output polarity. This parameter can be a value of Comparator output - Output polarity

This feature can be modified afterwards using unitary function LL_COMP_SetOutputPolarity().

Definition at line 1539 of file stm32f3xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::OutputSelection

Set comparator output selection. This parameter can be a value of Comparator output - Output selection

This feature can be modified afterwards using unitary function LL_COMP_SetOutputSelection().

Definition at line 1534 of file stm32f3xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::PowerMode

Set comparator operating mode to adjust power and speed. This parameter can be a value of Comparator modes - Power mode

This feature can be modified afterwards using unitary function LL_COMP_SetPowerMode().

Definition at line 1514 of file stm32f3xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_comp.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Comparator common modes - Window mode

Defines
Comparator common modes - Window mode
COMP Exported Constants

Defines

#define | LL_COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000U)
#define | LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WNDWEN)

Define Documentation

#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WNDWEN)

Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible).

Definition at line 1560 of file stm32f3xx_ll_comp.h.

#define LL_COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000U)

Window mode disable: Comparators 1 and 2 are independent

Definition at line 1559 of file stm32f3xx_ll_comp.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Comparator modes - Power mode

Defines
Comparator modes - Power mode
COMP Exported Constants

Defines

#define | LL_COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000U)
#define | LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_COMP1MODE_0)
#define | LL_COMP_POWERMODE_LOWPOWER (COMP_CSR_COMP1MODE_1)
#define | LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_COMP1MODE_1 | COMP_CSR_COMP1MODE_0)

Define Documentation

#define LL_COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000U)

COMP power mode to high speed

Definition at line 1568 of file stm32f3xx_ll_comp.h.

#define LL_COMP_POWERMODE_LOWPOWER (COMP_CSR_COMP1MODE_1)

COMP power mode to low power

Definition at line 1570 of file stm32f3xx_ll_comp.h.

#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_COMP1MODE_0)

COMP power mode to medium speed

Definition at line 1569 of file stm32f3xx_ll_comp.h.

#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_COMP1MODE_1 | COMP_CSR_COMP1MODE_0)

COMP power mode to ultra-low power

Definition at line 1571 of file stm32f3xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Comparator inputs - Input plus (input non-inverting) selection

Defines
Comparator inputs - Input plus (input non-inverting) selection
COMP Exported Constants

Defines

#define | LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U)
#define | LL_COMP_INPUT_PLUS_DAC1_CH1 (COMP_CSR_COMP1SW1)

Define Documentation

#define LL_COMP_INPUT_PLUS_DAC1_CH1 (COMP_CSR_COMP1SW1)

Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch (Note: this switch is solely intended to redirect signals onto high impedance input, such as COMP1 input plus (highly resistive switch)) (specific to COMP instance: COMP1)

Definition at line 1580 of file stm32f3xx_ll_comp.h.

#define LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U)

Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA3 for COMP2)

Definition at line 1579 of file stm32f3xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Comparator inputs - Input minus (input inverting) selection

Defines
Comparator inputs - Input minus (input inverting) selection
COMP Exported Constants

Defines

#define | LL_COMP_INPUT_MINUS_1_4VREFINT ((uint32_t)0x00000000U)
#define | LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_COMP1INSEL_0)
#define | LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_COMP1INSEL_1 )
#define | LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0)
#define | LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_COMP1INSEL_2 )
#define | LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_0)
#define | LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 )
#define | LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0)
#define | LL_COMP_INPUT_MINUS_IO3 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_0)
#define | LL_COMP_INPUT_MINUS_IO4 (COMP_CSR_COMP1INSEL_2 )
#define | LL_COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0)

Define Documentation

#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_COMP1INSEL_0)

Comparator input minus connected to 1/2 VrefInt

Definition at line 1589 of file stm32f3xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_1_4VREFINT ((uint32_t)0x00000000U)

Comparator input minus connected to 1/4 VrefInt

Definition at line 1588 of file stm32f3xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_COMP1INSEL_1 )

Comparator input minus connected to 3/4 VrefInt

Definition at line 1590 of file stm32f3xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_COMP1INSEL_2 )

Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)

Definition at line 1592 of file stm32f3xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_0)

Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)

Definition at line 1593 of file stm32f3xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0)

Comparator input minus connected to DAC2 channel 1 (DAC2_OUT1)

Definition at line 1598 of file stm32f3xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 )

Comparator input minus connected to IO1 (pin PA0 for COMP1, pin PA2 for COMP2)

Definition at line 1594 of file stm32f3xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0)

Comparator input minus connected to IO2 (pin PA6 for COMP1 & COMP2)

Definition at line 1595 of file stm32f3xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO3 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_0)

Comparator input minus connected to IO3 (pin PA5 for COMP1 & COMP2)

Definition at line 1596 of file stm32f3xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO4 (COMP_CSR_COMP1INSEL_2 )

Comparator input minus connected to IO4 (pin PA4 for COMP1 & COMP2)

Definition at line 1597 of file stm32f3xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0)

Comparator input minus connected to VrefInt

Definition at line 1591 of file stm32f3xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Comparator input - Hysteresis

Defines
Comparator input - Hysteresis
COMP Exported Constants

Defines

#define | LL_COMP_HYSTERESIS_NONE ((uint32_t)0x00000000U)
#define | LL_COMP_HYSTERESIS_LOW ( COMP_CSR_COMP1HYST_0)
#define | LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_COMP1HYST_1 )
#define | LL_COMP_HYSTERESIS_HIGH (COMP_CSR_COMP1HYST_1 | COMP_CSR_COMP1HYST_0)

Define Documentation

#define LL_COMP_HYSTERESIS_HIGH (COMP_CSR_COMP1HYST_1 | COMP_CSR_COMP1HYST_0)

Hysteresis level high

Definition at line 1609 of file stm32f3xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_LOW ( COMP_CSR_COMP1HYST_0)

Hysteresis level low

Definition at line 1607 of file stm32f3xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_COMP1HYST_1 )

Hysteresis level medium

Definition at line 1608 of file stm32f3xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_NONE ((uint32_t)0x00000000U)

No hysteresis

Definition at line 1606 of file stm32f3xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Comparator output - Output selection

Defines
Comparator output - Output selection
COMP Exported Constants

Defines

#define | LL_COMP_OUTPUT_NONE ((uint32_t)0x00000000U)
#define | LL_COMP_OUTPUT_TIM2_IC4 (COMP_CSR_COMP1OUTSEL_2)
#define | LL_COMP_OUTPUT_TIM2_OCCLR (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_0)
#define | LL_COMP_OUTPUT_TIM15_BKIN_COMP1 (COMP_CSR_COMP1OUTSEL_0)
#define | LL_COMP_OUTPUT_TIM3_IC1_COMP1 (COMP_CSR_COMP1OUTSEL_1)
#define | LL_COMP_OUTPUT_TIM3_OCCLR_COMP1 (COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0)
#define | LL_COMP_OUTPUT_TIM5_IC4_COMP1 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1)
#define | LL_COMP_OUTPUT_TIM5_OCCLR_COMP1 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0)
#define | LL_COMP_OUTPUT_TIM16_BKIN_COMP2 (COMP_CSR_COMP1OUTSEL_0)
#define | LL_COMP_OUTPUT_TIM4_IC1_COMP2 (COMP_CSR_COMP1OUTSEL_1)
#define | LL_COMP_OUTPUT_TIM4_OCCLR_COMP2 (COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0)
#define | LL_COMP_OUTPUT_TIM3_IC1_COMP2 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1)
#define | LL_COMP_OUTPUT_TIM3_OCCLR_COMP2 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0)
#define | LL_COMP_OUTPUT_TIM15_BKIN LL_COMP_OUTPUT_TIM15_BKIN_COMP1
#define | LL_COMP_OUTPUT_TIM16_BKIN LL_COMP_OUTPUT_TIM16_BKIN_COMP2
#define | LL_COMP_OUTPUT_TIM4_IC1 LL_COMP_OUTPUT_TIM4_IC1_COMP2
#define | LL_COMP_OUTPUT_TIM4_OCCLR LL_COMP_OUTPUT_TIM4_OCCLR_COMP2
#define | LL_COMP_OUTPUT_TIM5_IC4 LL_COMP_OUTPUT_TIM5_IC1_COMP1
#define | LL_COMP_OUTPUT_TIM5_OCCLR LL_COMP_OUTPUT_TIM5_OCCLR_COMP1

Define Documentation

#define LL_COMP_OUTPUT_NONE ((uint32_t)0x00000000U)

COMP output is not connected to other peripherals (except GPIO and EXTI that are always connected to COMP output)

Definition at line 1618 of file stm32f3xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

#define LL_COMP_OUTPUT_TIM15_BKIN LL_COMP_OUTPUT_TIM15_BKIN_COMP1

COMP output connected to TIM15 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints.

Definition at line 1643 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_TIM15_BKIN_COMP1 (COMP_CSR_COMP1OUTSEL_0)

COMP output connected to TIM15 break input (BKIN) (specific to COMP instance: COMP1)

Definition at line 1623 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_TIM16_BKIN LL_COMP_OUTPUT_TIM16_BKIN_COMP2

COMP output connected to TIM16 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints.

Definition at line 1644 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_TIM16_BKIN_COMP2 (COMP_CSR_COMP1OUTSEL_0)

COMP output connected to TIM16 break input (BKIN) (specific to COMP instance: COMP2)

Definition at line 1630 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_TIM2_IC4 (COMP_CSR_COMP1OUTSEL_2)

COMP output connected to TIM2 input capture 4

Definition at line 1619 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_TIM2_OCCLR (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_0)

COMP output connected to TIM2 OCREF clear

Definition at line 1620 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_TIM3_IC1_COMP1 (COMP_CSR_COMP1OUTSEL_1)

COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP1)

Definition at line 1624 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_TIM3_IC1_COMP2 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1)

COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2)

Definition at line 1633 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_TIM3_OCCLR_COMP1 (COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0)

COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP1)

Definition at line 1625 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_TIM3_OCCLR_COMP2 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0)

COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP2)

Definition at line 1634 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_TIM4_IC1 LL_COMP_OUTPUT_TIM4_IC1_COMP2

COMP output connected to TIM4 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints.

Definition at line 1645 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_TIM4_IC1_COMP2 (COMP_CSR_COMP1OUTSEL_1)

COMP output connected to TIM4 input capture 1 (specific to COMP instance: COMP2)

Definition at line 1631 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_TIM4_OCCLR LL_COMP_OUTPUT_TIM4_OCCLR_COMP2

COMP output connected to TIM4 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints.

Definition at line 1646 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_TIM4_OCCLR_COMP2 (COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0)

COMP output connected to TIM4 OCREF clear (specific to COMP instance: COMP2)

Definition at line 1632 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_TIM5_IC4 LL_COMP_OUTPUT_TIM5_IC1_COMP1

COMP output connected to TIM5 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints.

Definition at line 1647 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_TIM5_IC4_COMP1 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1)

COMP output connected to TIM5 input capture 4 (specific to COMP instance: COMP1)

Definition at line 1626 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_TIM5_OCCLR LL_COMP_OUTPUT_TIM5_OCCLR_COMP1

COMP output connected to TIM5 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints.

Definition at line 1648 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_TIM5_OCCLR_COMP1 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0)

COMP output connected to TIM5 OCREF clear (specific to COMP instance: COMP1)

Definition at line 1627 of file stm32f3xx_ll_comp.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Comparator output - Output polarity

Defines
Comparator output - Output polarity
COMP Exported Constants

Defines

#define | LL_COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000U)
#define | LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_COMP1POL)

Define Documentation

#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_COMP1POL)

COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input

Definition at line 1657 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000U)

COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input

Definition at line 1656 of file stm32f3xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Comparator output - Output level

Defines
Comparator output - Output level
COMP Exported Constants

Defines

#define | LL_COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000U)
#define | LL_COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001U)

Define Documentation

#define LL_COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001U)

Comparator output level high (if the polarity is not inverted, otherwise to be complemented)

Definition at line 1666 of file stm32f3xx_ll_comp.h.

#define LL_COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000U)

Comparator output level low (if the polarity is not inverted, otherwise to be complemented)

Definition at line 1665 of file stm32f3xx_ll_comp.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Definitions of COMP hardware constraints delays

Defines
Definitions of COMP hardware constraints delays
COMP Exported Constants

Defines

#define | LL_COMP_DELAY_STARTUP_US ((uint32_t) 60U)
#define | LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)

Detailed Description

Note:
Only COMP IP HW delays are defined in COMP LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_COMP_DELAY_STARTUP_US ((uint32_t) 60U)

Delay for COMP startup time

Definition at line 1684 of file stm32f3xx_ll_comp.h.

#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)

Delay for COMP voltage scaler stabilization time

Definition at line 1691 of file stm32f3xx_ll_comp.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Common write and read registers macro

Defines
Common write and read registers macro
COMP Exported Macros

Defines

#define | LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in COMP register.
#define | LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in COMP register.

Define Documentation

#define LL_COMP_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in COMP register.

Parameters:
__INSTANCE__ | comparator instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 1725 of file stm32f3xx_ll_comp.h.

#define LL_COMP_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in COMP register.

Parameters:
__INSTANCE__ | comparator instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 1717 of file stm32f3xx_ll_comp.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP helper macro

Defines
COMP helper macro
COMP Exported Macros

Defines

#define __LL_COMP_COMMON_INSTANCE(__COMPx__) (COMP12_COMMON)
Helper macro to select the COMP common instance to which is belonging the selected COMP instance.

Define Documentation

#define __LL_COMP_COMMON_INSTANCE ( __COMPx__ ) (COMP12_COMMON)

Helper macro to select the COMP common instance to which is belonging the selected COMP instance.

Note:
COMP common register instance can be used to set parameters common to several COMP instances. Refer to functions having argument "COMPxy_COMMON" as parameter.
Parameters:
__COMPx__ COMP instance
Return values:
COMP common instance or value "0" if there is no COMP common instance.

Definition at line 1743 of file stm32f3xx_ll_comp.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration of COMP hierarchical scope: common to several COMP instances

Functions
Configuration of COMP hierarchical scope: common to several COMP instances
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_SetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
Set window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
__STATIC_INLINE uint32_t | LL_COMP_GetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON)
Get window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).

Function Documentation

__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode ( COMP_Common_TypeDef * COMPxy_COMMON )

Get window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).

Reference Manual to LL API cross reference:
CSR WNDWEN LL_COMP_GetCommonWindowMode
Parameters:
COMPxy_COMMON Comparator common instance (can be set directly from CMSIS definition or by using helper macro __LL_COMP_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_COMP_WINDOWMODE_DISABLE
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON

Definition at line 1789 of file stm32f3xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetCommonWindowMode | ( | COMP_Common_TypeDef * | COMPxy_COMMON,
 |  | uint32_t | WindowMode
 | ) |  |

Set window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).

Reference Manual to LL API cross reference:
CSR WNDWEN LL_COMP_SetCommonWindowMode
Parameters:
COMPxy_COMMON Comparator common instance (can be set directly from CMSIS definition or by using helper macro __LL_COMP_COMMON_INSTANCE() )
WindowMode This parameter can be one of the following values:
  • LL_COMP_WINDOWMODE_DISABLE
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
Return values:
None

Definition at line 1774 of file stm32f3xx_ll_comp.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration of comparator modes

Functions
Configuration of comparator modes
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_SetPowerMode (COMP_TypeDef *COMPx, uint32_t PowerMode)
Set comparator instance operating mode to adjust power and speed.
__STATIC_INLINE uint32_t | LL_COMP_GetPowerMode (COMP_TypeDef *COMPx)
Get comparator instance operating mode to adjust power and speed.

Function Documentation

__STATIC_INLINE uint32_t LL_COMP_GetPowerMode ( COMP_TypeDef * COMPx )

Get comparator instance operating mode to adjust power and speed.

Reference Manual to LL API cross reference:
CSR COMP1MODE LL_COMP_GetPowerMode
COMP2MODE LL_COMP_GetPowerMode
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_POWERMODE_HIGHSPEED
  • LL_COMP_POWERMODE_MEDIUMSPEED
  • LL_COMP_POWERMODE_LOWPOWER
  • LL_COMP_POWERMODE_ULTRALOWPOWER

Definition at line 1832 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE.

__STATIC_INLINE void LL_COMP_SetPowerMode | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | PowerMode
 | ) |  |

Set comparator instance operating mode to adjust power and speed.

Reference Manual to LL API cross reference:
CSR COMP1MODE LL_COMP_SetPowerMode
COMP2MODE LL_COMP_SetPowerMode
Parameters:
COMPx Comparator instance
PowerMode This parameter can be one of the following values:
  • LL_COMP_POWERMODE_HIGHSPEED
  • LL_COMP_POWERMODE_MEDIUMSPEED
  • LL_COMP_POWERMODE_LOWPOWER
  • LL_COMP_POWERMODE_ULTRALOWPOWER
Return values:
None

Definition at line 1814 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration of comparator inputs

Functions
Configuration of comparator inputs
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_ConfigInputs (COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
Set comparator inputs minus (inverting) and plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputPlus (COMP_TypeDef *COMPx, uint32_t InputPlus)
Set comparator input plus (non-inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputPlus (COMP_TypeDef *COMPx)
Get comparator input plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputMinus (COMP_TypeDef *COMPx, uint32_t InputMinus)
Set comparator input minus (inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputMinus (COMP_TypeDef *COMPx)
Get comparator input minus (inverting).
__STATIC_INLINE void | LL_COMP_SetInputHysteresis (COMP_TypeDef *COMPx, uint32_t InputHysteresis)
Set comparator instance hysteresis mode of the input minus (inverting input).
__STATIC_INLINE uint32_t | LL_COMP_GetInputHysteresis (COMP_TypeDef *COMPx)
Get comparator instance hysteresis mode of the minus (inverting) input.

Function Documentation

__STATIC_INLINE void LL_COMP_ConfigInputs | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputMinus,
 |  | uint32_t | InputPlus
 | ) |  |

Set comparator inputs minus (inverting) and plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR COMP1INSEL LL_COMP_ConfigInputs
CSR COMP2INSEL LL_COMP_ConfigInputs
CSR COMP1SW1 LL_COMP_ConfigInputs
Parameters:
COMPx Comparator instance
InputMinus This parameter can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_DAC1_CH1
  • LL_COMP_INPUT_MINUS_DAC1_CH2
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2
  • LL_COMP_INPUT_MINUS_IO3
  • LL_COMP_INPUT_MINUS_IO4
  • LL_COMP_INPUT_MINUS_DAC2_CH1
InputPlus This parameter can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_DAC1_CH1 (1)
(1) Parameter available only on COMP instance: COMP1.
Return values:
None

Definition at line 1876 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE, and __COMP_IS_INSTANCE_ODD.

__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis ( COMP_TypeDef * COMPx )

Get comparator instance hysteresis mode of the minus (inverting) input.

Reference Manual to LL API cross reference:
CSR COMP1HYST LL_COMP_GetInputHysteresis
COMP2HYST LL_COMP_GetInputHysteresis
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_HYSTERESIS_NONE
  • LL_COMP_HYSTERESIS_LOW
  • LL_COMP_HYSTERESIS_MEDIUM
  • LL_COMP_HYSTERESIS_HIGH

Definition at line 2021 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE.

__STATIC_INLINE uint32_t LL_COMP_GetInputMinus ( COMP_TypeDef * COMPx )

Get comparator input minus (inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR COMP1SW1 LL_COMP_GetInputMinus
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_DAC1_CH1
  • LL_COMP_INPUT_MINUS_DAC1_CH2
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2
  • LL_COMP_INPUT_MINUS_IO3
  • LL_COMP_INPUT_MINUS_IO4
  • LL_COMP_INPUT_MINUS_DAC2_CH1

Definition at line 1983 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE.

__STATIC_INLINE uint32_t LL_COMP_GetInputPlus ( COMP_TypeDef * COMPx )

Get comparator input plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR COMP1INSEL LL_COMP_GetInputPlus
CSR COMP2INSEL LL_COMP_GetInputPlus
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_DAC1_CH1 (1)
(1) Parameter available only on COMP instance: COMP1.

Definition at line 1925 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE.

__STATIC_INLINE void LL_COMP_SetInputHysteresis | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputHysteresis
 | ) |  |

Set comparator instance hysteresis mode of the input minus (inverting input).

Reference Manual to LL API cross reference:
CSR COMP1HYST LL_COMP_SetInputHysteresis
COMP2HYST LL_COMP_SetInputHysteresis
Parameters:
COMPx Comparator instance
InputHysteresis This parameter can be one of the following values:
  • LL_COMP_HYSTERESIS_NONE
  • LL_COMP_HYSTERESIS_LOW
  • LL_COMP_HYSTERESIS_MEDIUM
  • LL_COMP_HYSTERESIS_HIGH
Return values:
None

Definition at line 2003 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE.

__STATIC_INLINE void LL_COMP_SetInputMinus | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputMinus
 | ) |  |

Set comparator input minus (inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR COMP1SW1 LL_COMP_SetInputMinus
Parameters:
COMPx Comparator instance
InputMinus This parameter can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_DAC1_CH1
  • LL_COMP_INPUT_MINUS_DAC1_CH2
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2
  • LL_COMP_INPUT_MINUS_IO3
  • LL_COMP_INPUT_MINUS_IO4
  • LL_COMP_INPUT_MINUS_DAC2_CH1
Return values:
None

Definition at line 1956 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE.

__STATIC_INLINE void LL_COMP_SetInputPlus | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputPlus
 | ) |  |

Set comparator input plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR COMP1INSEL LL_COMP_SetInputPlus
CSR COMP2INSEL LL_COMP_SetInputPlus
Parameters:
COMPx Comparator instance
InputPlus This parameter can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_DAC1_CH1 (1)
(1) Parameter available only on COMP instance: COMP1.
Return values:
None

Definition at line 1901 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE, and __COMP_IS_INSTANCE_ODD.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration of comparator output

Functions
Configuration of comparator output
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_SetOutputSelection (COMP_TypeDef *COMPx, uint32_t OutputSelection)
Set comparator output selection.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputSelection (COMP_TypeDef *COMPx)
Get comparator output selection.
__STATIC_INLINE void | LL_COMP_SetOutputPolarity (COMP_TypeDef *COMPx, uint32_t OutputPolarity)
Set comparator instance output polarity.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputPolarity (COMP_TypeDef *COMPx)
Get comparator instance output polarity.

Function Documentation

__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity ( COMP_TypeDef * COMPx )

Get comparator instance output polarity.

Reference Manual to LL API cross reference:
CSR COMP1POL LL_COMP_GetOutputPolarity
COMP2POL LL_COMP_GetOutputPolarity
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_OUTPUTPOL_NONINVERTED
  • LL_COMP_OUTPUTPOL_INVERTED

Definition at line 2120 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE.

__STATIC_INLINE uint32_t LL_COMP_GetOutputSelection ( COMP_TypeDef * COMPx )

Get comparator output selection.

Note:
Availability of parameters of output selection to timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CSR COMP1OUTSEL LL_COMP_GetOutputSelection
COMP2OUTSEL LL_COMP_GetOutputSelection
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_OUTPUT_NONE
  • LL_COMP_OUTPUT_TIM16_BKIN (1)
  • LL_COMP_OUTPUT_TIM4_IC1 (1)
  • LL_COMP_OUTPUT_TIM4_OCCLR (1)
  • LL_COMP_OUTPUT_TIM2_IC4 (1)
  • LL_COMP_OUTPUT_TIM2_OCCLR (1)
  • LL_COMP_OUTPUT_TIM3_IC1 (1)
  • LL_COMP_OUTPUT_TIM3_OCCLR (1)
(1) Parameter availability depending on timer availability on the selected device.

Definition at line 2086 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE.

__STATIC_INLINE void LL_COMP_SetOutputPolarity | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | OutputPolarity
 | ) |  |

Set comparator instance output polarity.

Reference Manual to LL API cross reference:
CSR COMP1POL LL_COMP_SetOutputPolarity
COMP2POL LL_COMP_SetOutputPolarity
Parameters:
COMPx Comparator instance
OutputPolarity This parameter can be one of the following values:
  • LL_COMP_OUTPUTPOL_NONINVERTED
  • LL_COMP_OUTPUTPOL_INVERTED
Return values:
None

Definition at line 2104 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE.

__STATIC_INLINE void LL_COMP_SetOutputSelection | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | OutputSelection
 | ) |  |

Set comparator output selection.

Note:
Availability of parameters of output selection to timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CSR COMP1OUTSEL LL_COMP_SetOutputSelection
COMP2OUTSEL LL_COMP_SetOutputSelection
Parameters:
COMPx Comparator instance
OutputSelection This parameter can be one of the following values:
  • LL_COMP_OUTPUT_NONE
  • LL_COMP_OUTPUT_TIM16_BKIN (1)
  • LL_COMP_OUTPUT_TIM4_IC1 (1)
  • LL_COMP_OUTPUT_TIM4_OCCLR (1)
  • LL_COMP_OUTPUT_TIM2_IC4 (1)
  • LL_COMP_OUTPUT_TIM2_OCCLR (1)
  • LL_COMP_OUTPUT_TIM3_IC1 (1)
  • LL_COMP_OUTPUT_TIM3_OCCLR (1)
(1) Parameter availability depending on timer availability on the selected device.
Return values:
None

Definition at line 2059 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Operation on comparator instance

Functions
Operation on comparator instance
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_Enable (COMP_TypeDef *COMPx)
Enable comparator instance.
__STATIC_INLINE void | LL_COMP_Disable (COMP_TypeDef *COMPx)
Disable comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsEnabled (COMP_TypeDef *COMPx)
Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)
__STATIC_INLINE void | LL_COMP_Lock (COMP_TypeDef *COMPx)
Lock comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsLocked (COMP_TypeDef *COMPx)
Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).
__STATIC_INLINE uint32_t | LL_COMP_ReadOutputLevel (COMP_TypeDef *COMPx)
Read comparator instance output level.

Function Documentation

__STATIC_INLINE void LL_COMP_Disable ( COMP_TypeDef * COMPx )

Disable comparator instance.

Reference Manual to LL API cross reference:
CSR COMP1EN LL_COMP_Disable
COMP2EN LL_COMP_Disable
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 2158 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE.

__STATIC_INLINE void LL_COMP_Enable ( COMP_TypeDef * COMPx )

Enable comparator instance.

Note:
After enable from off state, comparator requires a delay to reach reach propagation delay specification. Refer to device datasheet, parameter "tSTART".
Reference Manual to LL API cross reference:
CSR COMP1EN LL_COMP_Enable
COMP2EN LL_COMP_Enable
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 2146 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE.

__STATIC_INLINE uint32_t LL_COMP_IsEnabled ( COMP_TypeDef * COMPx )

Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)

Reference Manual to LL API cross reference:
CSR COMP1EN LL_COMP_IsEnabled
COMP2EN LL_COMP_IsEnabled
Parameters:
COMPx Comparator instance
Return values:
State of bit (1 or 0).

Definition at line 2171 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE.

__STATIC_INLINE uint32_t LL_COMP_IsLocked ( COMP_TypeDef * COMPx )

Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).

Note:
Once locked, comparator configuration can be accessed in read-only.
The only way to unlock the comparator is a device hardware reset.
Reference Manual to LL API cross reference:
CSR COMP1LOCK LL_COMP_IsLocked
COMP2LOCK LL_COMP_IsLocked
Parameters:
COMPx Comparator instance
Return values:
State of bit (1 or 0).

Definition at line 2200 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE.

Referenced by LL_COMP_DeInit(), and LL_COMP_Init().

__STATIC_INLINE void LL_COMP_Lock ( COMP_TypeDef * COMPx )

Lock comparator instance.

Note:
Once locked, comparator configuration can be accessed in read-only.
The only way to unlock the comparator is a device hardware reset.
Reference Manual to LL API cross reference:
CSR COMP1LOCK LL_COMP_Lock
COMP2LOCK LL_COMP_Lock
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 2185 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE.

__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel ( COMP_TypeDef * COMPx )

Read comparator instance output level.

Note:
The comparator output level depends on the selected polarity (Refer to function LL_COMP_SetOutputPolarity()). If the comparator polarity is not inverted:
  • Comparator output is low when the input plus is at a lower voltage than the input minus
  • Comparator output is high when the input plus is at a higher voltage than the input minus If the comparator polarity is inverted:
  • Comparator output is high when the input plus is at a lower voltage than the input minus
  • Comparator output is low when the input plus is at a higher voltage than the input minus
Reference Manual to LL API cross reference:
CSR COMP1OUT LL_COMP_ReadOutputLevel
COMP2OUT LL_COMP_ReadOutputLevel
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_OUTPUT_LEVEL_LOW
  • LL_COMP_OUTPUT_LEVEL_HIGH

Definition at line 2226 of file stm32f3xx_ll_comp.h.

References __COMP_BITOFFSET_INSTANCE, and LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
COMP Exported Functions

Functions

ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_COMP_DeInit ( COMP_TypeDef * COMPx )

De-initialize registers of the selected COMP instance to their default reset values.

Note:
If comparator is locked, de-initialization by software is not possible. The only way to unlock the comparator is a device hardware reset.
Parameters:
COMPx COMP instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: COMP registers are de-initialized
  • ERROR: COMP registers are not de-initialized

Definition at line 870 of file stm32f3xx_ll_comp.c.

References __COMP_BITOFFSET_INSTANCE, assert_param, and LL_COMP_IsLocked().

ErrorStatus LL_COMP_Init | ( | COMP_TypeDef * | COMPx,
 |  | LL_COMP_InitTypeDef * | COMP_InitStruct
 | ) |  |

Initialize some features of COMP instance.

Note:
This function configures features of the selected COMP instance. Some features are also available at scope COMP common instance (common to several COMP instances). Refer to functions having argument "COMPxy_COMMON" as parameter.
Parameters:
COMPx | COMP instance
COMP_InitStruct | Pointer to a LL_COMP_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: COMP registers are initialized
  • ERROR: COMP registers are not initialized

Definition at line 934 of file stm32f3xx_ll_comp.c.

References __COMP_BITOFFSET_INSTANCE, assert_param, LL_COMP_InitTypeDef::InputHysteresis, LL_COMP_InitTypeDef::InputMinus, LL_COMP_InitTypeDef::InputPlus, IS_LL_COMP_INPUT_HYSTERESIS, IS_LL_COMP_INPUT_MINUS, IS_LL_COMP_INPUT_PLUS, IS_LL_COMP_OUTPUT_POLARITY, IS_LL_COMP_OUTPUT_SELECTION, IS_LL_COMP_POWER_MODE, LL_COMP_IsLocked(), LL_COMP_InitTypeDef::OutputPolarity, LL_COMP_InitTypeDef::OutputSelection, and LL_COMP_InitTypeDef::PowerMode.

void LL_COMP_StructInit ( LL_COMP_InitTypeDef * COMP_InitStruct )

Set each LL_COMP_InitTypeDef field to default value.

Parameters:
COMP_InitStruct pointer to a LL_COMP_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 1017 of file stm32f3xx_ll_comp.c.

References LL_COMP_InitTypeDef::InputHysteresis, LL_COMP_InitTypeDef::InputMinus, LL_COMP_InitTypeDef::InputPlus, LL_COMP_HYSTERESIS_NONE, LL_COMP_INPUT_MINUS_VREFINT, LL_COMP_INPUT_PLUS_IO1, LL_COMP_OUTPUT_NONE, LL_COMP_OUTPUTPOL_NONINVERTED, LL_COMP_POWERMODE_ULTRALOWPOWER, LL_COMP_InitTypeDef::OutputPolarity, LL_COMP_InitTypeDef::OutputSelection, and LL_COMP_InitTypeDef::PowerMode.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CORTEX

Modules
CORTEX
STM32F3xx_LL_Driver

Modules

CORTEX Exported Constants
CORTEX Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for CORTEX registers.

Register | Bit | Function
MPU_CTRL | ENABLE | LL_MPU_Disable
 |  | LL_MPU_Enable
 |  | LL_MPU_IsEnabled
MPU_RASR | AP | LL_MPU_ConfigRegion
 | B | LL_MPU_ConfigRegion
 | C | LL_MPU_ConfigRegion
 | ENABLE | LL_MPU_DisableRegion
 |  | LL_MPU_EnableRegion
 | S | LL_MPU_ConfigRegion
 | SIZE | LL_MPU_ConfigRegion
 | XN | LL_MPU_ConfigRegion
MPU_RBAR | ADDR | LL_MPU_ConfigRegion
 | REGION | LL_MPU_ConfigRegion
MPU_RNR | REGION | LL_MPU_ConfigRegion
 |  | LL_MPU_DisableRegion
SCB_CPUID | ARCHITECTURE | LL_CPUID_GetConstant
 | IMPLEMENTER | LL_CPUID_GetImplementer
 | PARTNO | LL_CPUID_GetParNo
 | REVISION | LL_CPUID_GetRevision
 | VARIANT | LL_CPUID_GetVariant
SCB_SCR | SEVEONPEND | LL_LPM_DisableEventOnPend
 |  | LL_LPM_EnableEventOnPend
 | SLEEPDEEP | LL_LPM_EnableDeepSleep
 |  | LL_LPM_EnableSleep
 | SLEEPONEXIT | LL_LPM_DisableSleepOnExit
 |  | LL_LPM_EnableSleepOnExit
SCB_SHCSR | MEMFAULTENA | LL_HANDLER_DisableFault
 |  | LL_HANDLER_EnableFault
STK_CTRL | CLKSOURCE | LL_SYSTICK_GetClkSource
 |  | LL_SYSTICK_SetClkSource
 | COUNTFLAG | LL_SYSTICK_IsActiveCounterFlag
 | TICKINT | LL_SYSTICK_DisableIT
 |  | LL_SYSTICK_EnableIT
 |  | LL_SYSTICK_IsEnabledIT
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STM32F373xC HAL User Manual: SYSTICK Clock Source

Defines
SYSTICK Clock Source
CORTEX Exported Constants

Defines

#define | LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk

Define Documentation

#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk

AHB clock selected as SysTick clock source.

Definition at line 88 of file stm32f3xx_ll_cortex.h.

Referenced by LL_SYSTICK_GetClkSource(), and LL_SYSTICK_SetClkSource().

#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U

AHB clock divided by 8 selected as SysTick clock source.

Definition at line 87 of file stm32f3xx_ll_cortex.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Handler Fault type

Defines
Handler Fault type
CORTEX Exported Constants

Defines

#define | LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk
#define | LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk
#define | LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk

Define Documentation

#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk

Bus fault

Definition at line 97 of file stm32f3xx_ll_cortex.h.

#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk

Memory management fault

Definition at line 98 of file stm32f3xx_ll_cortex.h.

#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk

Usage fault

Definition at line 96 of file stm32f3xx_ll_cortex.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: MPU Control

Defines
MPU Control
CORTEX Exported Constants

Defines

#define | LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U
#define | LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define | LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Define Documentation

#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk

Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers

Definition at line 109 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Enable NMI and privileged SW access

Definition at line 111 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U

Disable NMI and privileged SW access

Definition at line 108 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk

Enable privileged software access to default memory map

Definition at line 110 of file stm32f3xx_ll_cortex.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: MPU Region Number

Defines
MPU Region Number
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_NUMBER0 0x00U
#define | LL_MPU_REGION_NUMBER1 0x01U
#define | LL_MPU_REGION_NUMBER2 0x02U
#define | LL_MPU_REGION_NUMBER3 0x03U
#define | LL_MPU_REGION_NUMBER4 0x04U
#define | LL_MPU_REGION_NUMBER5 0x05U
#define | LL_MPU_REGION_NUMBER6 0x06U
#define | LL_MPU_REGION_NUMBER7 0x07U

Define Documentation

#define LL_MPU_REGION_NUMBER0 0x00U

REGION Number 0

Definition at line 119 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER1 0x01U

REGION Number 1

Definition at line 120 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER2 0x02U

REGION Number 2

Definition at line 121 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER3 0x03U

REGION Number 3

Definition at line 122 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER4 0x04U

REGION Number 4

Definition at line 123 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER5 0x05U

REGION Number 5

Definition at line 124 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER6 0x06U

REGION Number 6

Definition at line 125 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER7 0x07U

REGION Number 7

Definition at line 126 of file stm32f3xx_ll_cortex.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: MPU Region Size

Defines
MPU Region Size
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos)

Define Documentation

#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos)

128B Size of the MPU protection region

Definition at line 136 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos)

128KB Size of the MPU protection region

Definition at line 146 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos)

128MB Size of the MPU protection region

Definition at line 156 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos)

16KB Size of the MPU protection region

Definition at line 143 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos)

16MB Size of the MPU protection region

Definition at line 153 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos)

1GB Size of the MPU protection region

Definition at line 159 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos)

1KB Size of the MPU protection region

Definition at line 139 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos)

1MB Size of the MPU protection region

Definition at line 149 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos)

256B Size of the MPU protection region

Definition at line 137 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos)

256KB Size of the MPU protection region

Definition at line 147 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos)

256MB Size of the MPU protection region

Definition at line 157 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos)

2GB Size of the MPU protection region

Definition at line 160 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos)

2KB Size of the MPU protection region

Definition at line 140 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos)

2MB Size of the MPU protection region

Definition at line 150 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos)

32B Size of the MPU protection region

Definition at line 134 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos)

32KB Size of the MPU protection region

Definition at line 144 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos)

32MB Size of the MPU protection region

Definition at line 154 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos)

4GB Size of the MPU protection region

Definition at line 161 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos)

4KB Size of the MPU protection region

Definition at line 141 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos)

4MB Size of the MPU protection region

Definition at line 151 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos)

512B Size of the MPU protection region

Definition at line 138 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos)

512KB Size of the MPU protection region

Definition at line 148 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos)

512MB Size of the MPU protection region

Definition at line 158 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos)

64B Size of the MPU protection region

Definition at line 135 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos)

64KB Size of the MPU protection region

Definition at line 145 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos)

64MB Size of the MPU protection region

Definition at line 155 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos)

8KB Size of the MPU protection region

Definition at line 142 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos)

8MB Size of the MPU protection region

Definition at line 152 of file stm32f3xx_ll_cortex.h.

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STM32F373xC HAL User Manual: MPU Region Privileges

Defines
MPU Region Privileges
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos)

Define Documentation

#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos)

RW privileged & user (Full access)

Definition at line 172 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos)

No access

Definition at line 169 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos)

RO privileged (privileged read only)

Definition at line 173 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos)

RO privileged & user (read only)

Definition at line 174 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos)

RW privileged (privileged access only)

Definition at line 170 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos)

RW privileged - RO user (Write in a user program generates a fault)

Definition at line 171 of file stm32f3xx_ll_cortex.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: MPU TEX Level

Defines
MPU TEX Level
CORTEX Exported Constants

Defines

#define | LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos)

Define Documentation

#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos)

b000 for TEX bits

Definition at line 182 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos)

b001 for TEX bits

Definition at line 183 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos)

b010 for TEX bits

Definition at line 184 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos)

b100 for TEX bits

Definition at line 185 of file stm32f3xx_ll_cortex.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: MPU Instruction Access

Defines
MPU Instruction Access
CORTEX Exported Constants

Defines

#define | LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U
#define | LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk

Define Documentation

#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk

Instruction fetches disabled

Definition at line 194 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U

Instruction fetches enabled

Definition at line 193 of file stm32f3xx_ll_cortex.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: MPU Shareable Access

Defines
MPU Shareable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk
#define | LL_MPU_ACCESS_NOT_SHAREABLE 0x00U

Define Documentation

#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U

Not Shareable memory attribute

Definition at line 203 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk

Shareable memory attribute

Definition at line 202 of file stm32f3xx_ll_cortex.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: MPU Cacheable Access

Defines
MPU Cacheable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk
#define | LL_MPU_ACCESS_NOT_CACHEABLE 0x00U

Define Documentation

#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk

Cacheable memory attribute

Definition at line 211 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U

Not Cacheable memory attribute

Definition at line 212 of file stm32f3xx_ll_cortex.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: MPU Bufferable Access

Defines
MPU Bufferable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk
#define | LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U

Define Documentation

#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk

Bufferable memory attribute

Definition at line 220 of file stm32f3xx_ll_cortex.h.

#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U

Not Bufferable memory attribute

Definition at line 221 of file stm32f3xx_ll_cortex.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SYSTICK

Functions
SYSTICK
CORTEX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SYSTICK_IsActiveCounterFlag (void)
This function checks if the Systick counter flag is active or not.
__STATIC_INLINE void | LL_SYSTICK_SetClkSource (uint32_t Source)
Configures the SysTick clock source.
__STATIC_INLINE uint32_t | LL_SYSTICK_GetClkSource (void)
Get the SysTick clock source.
__STATIC_INLINE void | LL_SYSTICK_EnableIT (void)
Enable SysTick exception request.
__STATIC_INLINE void | LL_SYSTICK_DisableIT (void)
Disable SysTick exception request.
__STATIC_INLINE uint32_t | LL_SYSTICK_IsEnabledIT (void)
Checks if the SYSTICK interrupt is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_SYSTICK_DisableIT ( void )

Disable SysTick exception request.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_DisableIT
Return values:
None

Definition at line 299 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE void LL_SYSTICK_EnableIT ( void )

Enable SysTick exception request.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_EnableIT
Return values:
None

Definition at line 289 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource ( void )

Get the SysTick clock source.

Reference Manual to LL API cross reference:
STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
Return values:
Returned value can be one of the following values:
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8
  • LL_SYSTICK_CLKSOURCE_HCLK

Definition at line 279 of file stm32f3xx_ll_cortex.h.

References LL_SYSTICK_CLKSOURCE_HCLK.

__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag ( void )

This function checks if the Systick counter flag is active or not.

Note:
It can be used in timeout function on application side.
Reference Manual to LL API cross reference:
STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
Return values:
State of bit (1 or 0).

Definition at line 247 of file stm32f3xx_ll_cortex.h.

Referenced by LL_RTC_EnterInitMode(), and LL_RTC_WaitForSynchro().

__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT ( void )

Checks if the SYSTICK interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
Return values:
State of bit (1 or 0).

Definition at line 309 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE void LL_SYSTICK_SetClkSource ( uint32_t Source )

Configures the SysTick clock source.

Reference Manual to LL API cross reference:
STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
Parameters:
Source This parameter can be one of the following values:
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8
  • LL_SYSTICK_CLKSOURCE_HCLK
Return values:
None

Definition at line 260 of file stm32f3xx_ll_cortex.h.

References LL_SYSTICK_CLKSOURCE_HCLK.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LOW POWER MODE

Functions
LOW POWER MODE
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_LPM_EnableSleep (void)
Processor uses sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableDeepSleep (void)
Processor uses deep sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableSleepOnExit (void)
Configures sleep-on-exit when returning from Handler mode to Thread mode.
__STATIC_INLINE void | LL_LPM_DisableSleepOnExit (void)
Do not sleep when returning to Thread mode.
__STATIC_INLINE void | LL_LPM_EnableEventOnPend (void)
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
__STATIC_INLINE void | LL_LPM_DisableEventOnPend (void)
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

Function Documentation

__STATIC_INLINE void LL_LPM_DisableEventOnPend ( void )

Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

Reference Manual to LL API cross reference:
SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
Return values:
None

Definition at line 386 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_DisableSleepOnExit ( void )

Do not sleep when returning to Thread mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
Return values:
None

Definition at line 362 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableDeepSleep ( void )

Processor uses deep sleep as its low power mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
Return values:
None

Definition at line 338 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableEventOnPend ( void )

Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.

Reference Manual to LL API cross reference:
SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
Return values:
None

Definition at line 374 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableSleep ( void )

Processor uses sleep as its low power mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
Return values:
None

Definition at line 327 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableSleepOnExit ( void )

Configures sleep-on-exit when returning from Handler mode to Thread mode.

Note:
Setting this bit to 1 enables an interrupt-driven application to avoid returning to an empty main application.
Reference Manual to LL API cross reference:
SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
Return values:
None

Definition at line 351 of file stm32f3xx_ll_cortex.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HANDLER

Functions
HANDLER
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_HANDLER_EnableFault (uint32_t Fault)
Enable a fault in System handler control register (SHCSR)
__STATIC_INLINE void | LL_HANDLER_DisableFault (uint32_t Fault)
Disable a fault in System handler control register (SHCSR)

Function Documentation

__STATIC_INLINE void LL_HANDLER_DisableFault ( uint32_t Fault )

Disable a fault in System handler control register (SHCSR)

Reference Manual to LL API cross reference:
SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
Parameters:
Fault This parameter can be a combination of the following values:
  • LL_HANDLER_FAULT_USG
  • LL_HANDLER_FAULT_BUS
  • LL_HANDLER_FAULT_MEM
Return values:
None

Definition at line 424 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE void LL_HANDLER_EnableFault ( uint32_t Fault )

Enable a fault in System handler control register (SHCSR)

Reference Manual to LL API cross reference:
SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
Parameters:
Fault This parameter can be a combination of the following values:
  • LL_HANDLER_FAULT_USG
  • LL_HANDLER_FAULT_BUS
  • LL_HANDLER_FAULT_MEM
Return values:
None

Definition at line 409 of file stm32f3xx_ll_cortex.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: MCU INFO

Functions
MCU INFO
CORTEX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_CPUID_GetImplementer (void)
Get Implementer code.
__STATIC_INLINE uint32_t | LL_CPUID_GetVariant (void)
Get Variant number (The r value in the rnpn product revision identifier)
__STATIC_INLINE uint32_t | LL_CPUID_GetConstant (void)
Get Constant number.
__STATIC_INLINE uint32_t | LL_CPUID_GetParNo (void)
Get Part number.
__STATIC_INLINE uint32_t | LL_CPUID_GetRevision (void)
Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)

Function Documentation

__STATIC_INLINE uint32_t LL_CPUID_GetConstant ( void )

Get Constant number.

Reference Manual to LL API cross reference:
SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
Return values:
Value should be equal to 0xF for Cortex-M4 devices

Definition at line 463 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetImplementer ( void )

Get Implementer code.

Reference Manual to LL API cross reference:
SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
Return values:
Value should be equal to 0x41 for ARM

Definition at line 443 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetParNo ( void )

Get Part number.

Reference Manual to LL API cross reference:
SCB_CPUID PARTNO LL_CPUID_GetParNo
Return values:
Value should be equal to 0xC24 for Cortex-M4

Definition at line 473 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetRevision ( void )

Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)

Reference Manual to LL API cross reference:
SCB_CPUID REVISION LL_CPUID_GetRevision
Return values:
Value between 0 and 255 (0x1: patch 1)

Definition at line 483 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetVariant ( void )

Get Variant number (The r value in the rnpn product revision identifier)

Reference Manual to LL API cross reference:
SCB_CPUID VARIANT LL_CPUID_GetVariant
Return values:
Value between 0 and 255 (0x0: revision 0)

Definition at line 453 of file stm32f3xx_ll_cortex.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: MPU

Functions
MPU
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_MPU_Enable (uint32_t Options)
Enable MPU with input options.
__STATIC_INLINE void | LL_MPU_Disable (void)
Disable MPU.
__STATIC_INLINE uint32_t | LL_MPU_IsEnabled (void)
Check if MPU is enabled or not.
__STATIC_INLINE void | LL_MPU_EnableRegion (uint32_t Region)
Enable a MPU region.
__STATIC_INLINE void | LL_MPU_ConfigRegion (uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
Configure and enable a region.
__STATIC_INLINE void | LL_MPU_DisableRegion (uint32_t Region)
Disable a region.

Function Documentation

__STATIC_INLINE void LL_MPU_ConfigRegion | ( | uint32_t | Region,
 |  | uint32_t | SubRegionDisable,
 |  | uint32_t | Address,
 |  | uint32_t | Attributes
 | ) |  |

Configure and enable a region.

Reference Manual to LL API cross reference:
MPU_RNR REGION LL_MPU_ConfigRegion
MPU_RBAR REGION LL_MPU_ConfigRegion
MPU_RBAR ADDR LL_MPU_ConfigRegion
MPU_RASR XN LL_MPU_ConfigRegion
MPU_RASR AP LL_MPU_ConfigRegion
MPU_RASR S LL_MPU_ConfigRegion
MPU_RASR C LL_MPU_ConfigRegion
MPU_RASR B LL_MPU_ConfigRegion
MPU_RASR SIZE LL_MPU_ConfigRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
Address | Value of region base address
SubRegionDisable | Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
Attributes This parameter can be a combination of the following values:
  • LL_MPU_REGION_SIZE_32B or LL_MPU_REGION_SIZE_64B or LL_MPU_REGION_SIZE_128B or LL_MPU_REGION_SIZE_256B or LL_MPU_REGION_SIZE_512B or LL_MPU_REGION_SIZE_1KB or LL_MPU_REGION_SIZE_2KB or LL_MPU_REGION_SIZE_4KB or LL_MPU_REGION_SIZE_8KB or LL_MPU_REGION_SIZE_16KB or LL_MPU_REGION_SIZE_32KB or LL_MPU_REGION_SIZE_64KB or LL_MPU_REGION_SIZE_128KB or LL_MPU_REGION_SIZE_256KB or LL_MPU_REGION_SIZE_512KB or LL_MPU_REGION_SIZE_1MB or LL_MPU_REGION_SIZE_2MB or LL_MPU_REGION_SIZE_4MB or LL_MPU_REGION_SIZE_8MB or LL_MPU_REGION_SIZE_16MB or LL_MPU_REGION_SIZE_32MB or LL_MPU_REGION_SIZE_64MB or LL_MPU_REGION_SIZE_128MB or LL_MPU_REGION_SIZE_256MB or LL_MPU_REGION_SIZE_512MB or LL_MPU_REGION_SIZE_1GB or LL_MPU_REGION_SIZE_2GB or LL_MPU_REGION_SIZE_4GB
  • LL_MPU_REGION_NO_ACCESS or LL_MPU_REGION_PRIV_RW or LL_MPU_REGION_PRIV_RW_URO or LL_MPU_REGION_FULL_ACCESS or LL_MPU_REGION_PRIV_RO or LL_MPU_REGION_PRIV_RO_URO
  • LL_MPU_TEX_LEVEL0 or LL_MPU_TEX_LEVEL1 or LL_MPU_TEX_LEVEL2 or LL_MPU_TEX_LEVEL4
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE or LL_MPU_INSTRUCTION_ACCESS_DISABLE
  • LL_MPU_ACCESS_SHAREABLE or LL_MPU_ACCESS_NOT_SHAREABLE
  • LL_MPU_ACCESS_CACHEABLE or LL_MPU_ACCESS_NOT_CACHEABLE
  • LL_MPU_ACCESS_BUFFERABLE or LL_MPU_ACCESS_NOT_BUFFERABLE
Return values:
None

Definition at line 600 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_Disable ( void )

Disable MPU.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_Disable
Return values:
None

Definition at line 522 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_DisableRegion ( uint32_t Region )

Disable a region.

Reference Manual to LL API cross reference:
MPU_RNR REGION LL_MPU_DisableRegion
MPU_RASR ENABLE LL_MPU_DisableRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
Return values:
None

Definition at line 625 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_Enable ( uint32_t Options )

Enable MPU with input options.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_Enable
Parameters:
Options This parameter can be one of the following values:
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
  • LL_MPU_CTRL_HARDFAULT_NMI
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT
  • LL_MPU_CTRL_HFNMI_PRIVDEF
Return values:
None

Definition at line 507 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_EnableRegion ( uint32_t Region )

Enable a MPU region.

Reference Manual to LL API cross reference:
MPU_RASR ENABLE LL_MPU_EnableRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
Return values:
None

Definition at line 554 of file stm32f3xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_MPU_IsEnabled ( void )

Check if MPU is enabled or not.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 535 of file stm32f3xx_ll_cortex.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRC

Modules
CRC
STM32F3xx_LL_Driver

Modules

CRC Exported Constants
CRC Exported Macros
CRC Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for CRC registers.

Register | Bit | Function
CR | POLYSIZE | LL_CRC_GetPolynomialSize
 |  | LL_CRC_SetPolynomialSize
 | RESET | LL_CRC_ResetCRCCalculationUnit
 | REV_IN | LL_CRC_GetInputDataReverseMode
 |  | LL_CRC_SetInputDataReverseMode
 | REV_OUT | LL_CRC_GetOutputDataReverseMode
 |  | LL_CRC_SetOutputDataReverseMode
DR | DR | LL_CRC_FeedData16
 |  | LL_CRC_FeedData32
 |  | LL_CRC_FeedData8
 |  | LL_CRC_ReadData16
 |  | LL_CRC_ReadData32
 |  | LL_CRC_ReadData7
 |  | LL_CRC_ReadData8
IDR | IDR | LL_CRC_Read_IDR
 |  | LL_CRC_Write_IDR
INIT | INIT | LL_CRC_GetInitialData
 |  | LL_CRC_SetInitialData
POL | POL | LL_CRC_GetPolynomialCoef
 |  | LL_CRC_SetPolynomialCoef
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Polynomial length

Defines
Polynomial length
CRC Exported Constants

Defines

#define | LL_CRC_POLYLENGTH_32B 0x00000000U
#define | LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)

Define Documentation

#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0

16 bits Polynomial size

Definition at line 72 of file stm32f3xx_ll_crc.h.

#define LL_CRC_POLYLENGTH_32B 0x00000000U

32 bits Polynomial size

Definition at line 71 of file stm32f3xx_ll_crc.h.

Referenced by LL_CRC_DeInit().

#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)

7 bits Polynomial size

Definition at line 74 of file stm32f3xx_ll_crc.h.

#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1

8 bits Polynomial size

Definition at line 73 of file stm32f3xx_ll_crc.h.

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STM32F373xC HAL User Manual: Input Data Reverse

Defines
Input Data Reverse
CRC Exported Constants

Defines

#define | LL_CRC_INDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0
#define | LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1
#define | LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)

Define Documentation

#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0

Input Data bit reversal done by byte

Definition at line 83 of file stm32f3xx_ll_crc.h.

#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1

Input Data bit reversal done by half-word

Definition at line 84 of file stm32f3xx_ll_crc.h.

#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U

Input Data bit order not affected

Definition at line 82 of file stm32f3xx_ll_crc.h.

Referenced by LL_CRC_DeInit().

#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)

Input Data bit reversal done by word

Definition at line 85 of file stm32f3xx_ll_crc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Output Data Reverse

Defines
Output Data Reverse
CRC Exported Constants

Defines

#define | LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT

Define Documentation

#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT

Output Data bit reversal done by bit

Definition at line 94 of file stm32f3xx_ll_crc.h.

#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U

Output Data bit order not affected

Definition at line 93 of file stm32f3xx_ll_crc.h.

Referenced by LL_CRC_DeInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Default CRC generating polynomial value

Defines
Default CRC generating polynomial value
CRC Exported Constants

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 . More...

Defines

#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U

Detailed Description

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .

Define Documentation

#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U

Default CRC generating polynomial value

Definition at line 104 of file stm32f3xx_ll_crc.h.

Referenced by LL_CRC_DeInit().

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STM32F373xC HAL User Manual: Default CRC computation initialization value

Defines
Default CRC computation initialization value
CRC Exported Constants

Defines

#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Define Documentation

#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Default CRC computation initialization value

Definition at line 112 of file stm32f3xx_ll_crc.h.

Referenced by LL_CRC_DeInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
CRC Exported Macros

Defines

#define | LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in CRC register.
#define | LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRC register.

Define Documentation

#define LL_CRC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in CRC register.

Parameters:
__INSTANCE__ | CRC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 145 of file stm32f3xx_ll_crc.h.

#define LL_CRC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in CRC register.

Parameters:
__INSTANCE__ | CRC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 137 of file stm32f3xx_ll_crc.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRC Configuration functions

Functions
CRC Configuration functions
CRC Exported Functions

Functions

__STATIC_INLINE void | LL_CRC_ResetCRCCalculationUnit (CRC_TypeDef *CRCx)
Reset the CRC calculation unit.
__STATIC_INLINE void | LL_CRC_SetPolynomialSize (CRC_TypeDef *CRCx, uint32_t PolySize)
Configure size of the polynomial.
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialSize (CRC_TypeDef *CRCx)
Return size of the polynomial.
__STATIC_INLINE void | LL_CRC_SetInputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the input data.
__STATIC_INLINE uint32_t | LL_CRC_GetInputDataReverseMode (CRC_TypeDef *CRCx)
Return type of reversal for input data bit order.
__STATIC_INLINE void | LL_CRC_SetOutputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE uint32_t | LL_CRC_GetOutputDataReverseMode (CRC_TypeDef *CRCx)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE void | LL_CRC_SetInitialData (CRC_TypeDef *CRCx, uint32_t InitCrc)
Initialize the Programmable initial CRC value.
__STATIC_INLINE uint32_t | LL_CRC_GetInitialData (CRC_TypeDef *CRCx)
Return current Initial CRC value.
__STATIC_INLINE void | LL_CRC_SetPolynomialCoef (CRC_TypeDef *CRCx, uint32_t PolynomCoef)
Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialCoef (CRC_TypeDef *CRCx)
Return current Programmable polynomial value.

Function Documentation

__STATIC_INLINE uint32_t LL_CRC_GetInitialData ( CRC_TypeDef * CRCx )

Return current Initial CRC value.

Note:
If the CRC size is less than 32 bits, the least significant bits are used to read the correct value
Reference Manual to LL API cross reference:
INIT INIT LL_CRC_GetInitialData
Parameters:
CRCx CRC Instance
Return values:
Value programmed in Programmable initial CRC value register

Definition at line 290 of file stm32f3xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode ( CRC_TypeDef * CRCx )

Return type of reversal for input data bit order.

Reference Manual to LL API cross reference:
CR REV_IN LL_CRC_GetInputDataReverseMode
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_INDATA_REVERSE_NONE
  • LL_CRC_INDATA_REVERSE_BYTE
  • LL_CRC_INDATA_REVERSE_HALFWORD
  • LL_CRC_INDATA_REVERSE_WORD

Definition at line 235 of file stm32f3xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode ( CRC_TypeDef * CRCx )

Configure the reversal of the bit order of the Output data.

Reference Manual to LL API cross reference:
CR REV_OUT LL_CRC_GetOutputDataReverseMode
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_OUTDATA_REVERSE_NONE
  • LL_CRC_OUTDATA_REVERSE_BIT

Definition at line 262 of file stm32f3xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef ( CRC_TypeDef * CRCx )

Return current Programmable polynomial value.

Note:
Please check Reference Manual and existing Errata Sheets, regarding possible limitations for Polynomial values usage. For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
Reference Manual to LL API cross reference:
POL POL LL_CRC_GetPolynomialCoef
Parameters:
CRCx CRC Instance
Return values:
Value programmed in Programmable Polynomial value register

Definition at line 321 of file stm32f3xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize ( CRC_TypeDef * CRCx )

Return size of the polynomial.

Reference Manual to LL API cross reference:
CR POLYSIZE LL_CRC_GetPolynomialSize
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_POLYLENGTH_32B
  • LL_CRC_POLYLENGTH_16B
  • LL_CRC_POLYLENGTH_8B
  • LL_CRC_POLYLENGTH_7B

Definition at line 204 of file stm32f3xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit ( CRC_TypeDef * CRCx )

Reset the CRC calculation unit.

Note:
If Programmable Initial CRC value feature is available, also set the Data Register to the value stored in the CRC_INIT register, otherwise, reset Data Register to its default value.
Reference Manual to LL API cross reference:
CR RESET LL_CRC_ResetCRCCalculationUnit
Parameters:
CRCx CRC Instance
Return values:
None

Definition at line 173 of file stm32f3xx_ll_crc.h.

Referenced by LL_CRC_DeInit().

__STATIC_INLINE void LL_CRC_SetInitialData | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InitCrc
 | ) |  |

Initialize the Programmable initial CRC value.

Note:
If the CRC size is less than 32 bits, the least significant bits are used to write the correct value
LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
Reference Manual to LL API cross reference:
INIT INIT LL_CRC_SetInitialData
Parameters:
CRCx | CRC Instance
InitCrc | Value to be programmed in Programmable initial CRC value register
Return values:
None

Definition at line 277 of file stm32f3xx_ll_crc.h.

Referenced by LL_CRC_DeInit().

__STATIC_INLINE void LL_CRC_SetInputDataReverseMode | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | ReverseMode
 | ) |  |

Configure the reversal of the bit order of the input data.

Reference Manual to LL API cross reference:
CR REV_IN LL_CRC_SetInputDataReverseMode
Parameters:
CRCx CRC Instance
ReverseMode This parameter can be one of the following values:
  • LL_CRC_INDATA_REVERSE_NONE
  • LL_CRC_INDATA_REVERSE_BYTE
  • LL_CRC_INDATA_REVERSE_HALFWORD
  • LL_CRC_INDATA_REVERSE_WORD
Return values:
None

Definition at line 220 of file stm32f3xx_ll_crc.h.

Referenced by LL_CRC_DeInit().

__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | ReverseMode
 | ) |  |

Configure the reversal of the bit order of the Output data.

Reference Manual to LL API cross reference:
CR REV_OUT LL_CRC_SetOutputDataReverseMode
Parameters:
CRCx CRC Instance
ReverseMode This parameter can be one of the following values:
  • LL_CRC_OUTDATA_REVERSE_NONE
  • LL_CRC_OUTDATA_REVERSE_BIT
Return values:
None

Definition at line 249 of file stm32f3xx_ll_crc.h.

Referenced by LL_CRC_DeInit().

__STATIC_INLINE void LL_CRC_SetPolynomialCoef | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | PolynomCoef
 | ) |  |

Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).

Note:
LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
Please check Reference Manual and existing Errata Sheets, regarding possible limitations for Polynomial values usage. For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
Reference Manual to LL API cross reference:
POL POL LL_CRC_SetPolynomialCoef
Parameters:
CRCx | CRC Instance
PolynomCoef | Value to be programmed in Programmable Polynomial value register
Return values:
None

Definition at line 307 of file stm32f3xx_ll_crc.h.

Referenced by LL_CRC_DeInit().

__STATIC_INLINE void LL_CRC_SetPolynomialSize | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | PolySize
 | ) |  |

Configure size of the polynomial.

Reference Manual to LL API cross reference:
CR POLYSIZE LL_CRC_SetPolynomialSize
Parameters:
CRCx CRC Instance
PolySize This parameter can be one of the following values:
  • LL_CRC_POLYLENGTH_32B
  • LL_CRC_POLYLENGTH_16B
  • LL_CRC_POLYLENGTH_8B
  • LL_CRC_POLYLENGTH_7B
Return values:
None

Definition at line 189 of file stm32f3xx_ll_crc.h.

Referenced by LL_CRC_DeInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data_Management

Functions
Data_Management
CRC Exported Functions

Functions

__STATIC_INLINE void | LL_CRC_FeedData32 (CRC_TypeDef *CRCx, uint32_t InData)
Write given 32-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData16 (CRC_TypeDef *CRCx, uint16_t InData)
Write given 16-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData8 (CRC_TypeDef *CRCx, uint8_t InData)
Write given 8-bit data to the CRC calculator.
__STATIC_INLINE uint32_t | LL_CRC_ReadData32 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint16_t | LL_CRC_ReadData16 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData8 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData7 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint32_t | LL_CRC_Read_IDR (CRC_TypeDef *CRCx)
Return data stored in the Independent Data(IDR) register.
__STATIC_INLINE void | LL_CRC_Write_IDR (CRC_TypeDef *CRCx, uint32_t InData)
Store data in the Independent Data(IDR) register.

Function Documentation

__STATIC_INLINE void LL_CRC_FeedData16 | ( | CRC_TypeDef * | CRCx,
 |  | uint16_t | InData
 | ) |  |

Write given 16-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData16
Parameters:
CRCx | CRC Instance
InData | 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
Return values:
None

Definition at line 353 of file stm32f3xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_FeedData32 | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InData
 | ) |  |

Write given 32-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData32
Parameters:
CRCx | CRC Instance
InData | value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 341 of file stm32f3xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_FeedData8 | ( | CRC_TypeDef * | CRCx,
 |  | uint8_t | InData
 | ) |  |

Write given 8-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData8
Parameters:
CRCx | CRC Instance
InData | 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 365 of file stm32f3xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_Read_IDR ( CRC_TypeDef * CRCx )

Return data stored in the Independent Data(IDR) register.

Note:
This register can be used as a temporary storage location for one byte.
Reference Manual to LL API cross reference:
IDR IDR LL_CRC_Read_IDR
Parameters:
CRCx CRC Instance
Return values:
Value stored in CRC_IDR register (General-purpose 8-bit data register).

Definition at line 424 of file stm32f3xx_ll_crc.h.

__STATIC_INLINE uint16_t LL_CRC_ReadData16 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

16 bits value is returned.

Note:
This function is expected to be used in a 16 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData16
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (16 bits).

Definition at line 388 of file stm32f3xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_ReadData32 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

32 bits value is returned.

Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData32
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (32 bits).

Definition at line 376 of file stm32f3xx_ll_crc.h.

__STATIC_INLINE uint8_t LL_CRC_ReadData7 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

7 bits value is returned.

Note:
This function is expected to be used in a 7 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData7
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (7 bits).

Definition at line 412 of file stm32f3xx_ll_crc.h.

__STATIC_INLINE uint8_t LL_CRC_ReadData8 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

8 bits value is returned.

Note:
This function is expected to be used in a 8 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData8
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (8 bits).

Definition at line 400 of file stm32f3xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_Write_IDR | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InData
 | ) |  |

Store data in the Independent Data(IDR) register.

Note:
This register can be used as a temporary storage location for one byte.
Reference Manual to LL API cross reference:
IDR IDR LL_CRC_Write_IDR
Parameters:
CRCx | CRC Instance
InData | value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 437 of file stm32f3xx_ll_crc.h.

Referenced by LL_CRC_DeInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRC Exported Functions

Functions

ErrorStatus LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Function Documentation

ErrorStatus LL_CRC_DeInit ( CRC_TypeDef * CRCx )

De-initialize CRC registers (Registers restored to their default values).

Parameters:
CRCx CRC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: CRC registers are de-initialized
  • ERROR: CRC registers are not de-initialized

Definition at line 78 of file stm32f3xx_ll_crc.c.

References assert_param, LL_CRC_DEFAULT_CRC32_POLY, LL_CRC_DEFAULT_CRC_INITVALUE, LL_CRC_INDATA_REVERSE_NONE, LL_CRC_OUTDATA_REVERSE_NONE, LL_CRC_POLYLENGTH_32B, LL_CRC_ResetCRCCalculationUnit(), LL_CRC_SetInitialData(), LL_CRC_SetInputDataReverseMode(), LL_CRC_SetOutputDataReverseMode(), LL_CRC_SetPolynomialCoef(), LL_CRC_SetPolynomialSize(), and LL_CRC_Write_IDR().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC

Modules
DAC
STM32F3xx_LL_Driver

Modules

DAC Private Constants
DAC Private Macros
DAC Exported Init structure
DAC Exported Constants
DAC Exported Macros
DAC Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for DAC registers.

Register | Bit | Function
CR | BOFF1 | LL_DAC_GetOutputBuffer
 |  | LL_DAC_SetOutputBuffer
 | BOFF2 | LL_DAC_GetOutputBuffer
 |  | LL_DAC_SetOutputBuffer
 | DMAEN1 | LL_DAC_DisableDMAReq
 |  | LL_DAC_EnableDMAReq
 |  | LL_DAC_IsDMAReqEnabled
 | DMAEN2 | LL_DAC_DisableDMAReq
 |  | LL_DAC_EnableDMAReq
 |  | LL_DAC_IsDMAReqEnabled
 | DMAUDRIE1 | LL_DAC_DisableIT_DMAUDR1
 |  | LL_DAC_EnableIT_DMAUDR1
 |  | LL_DAC_IsEnabledIT_DMAUDR1
 | DMAUDRIE2 | LL_DAC_DisableIT_DMAUDR2
 |  | LL_DAC_EnableIT_DMAUDR2
 |  | LL_DAC_IsEnabledIT_DMAUDR2
 | EN1 | LL_DAC_Disable
 |  | LL_DAC_Enable
 |  | LL_DAC_IsEnabled
 | EN2 | LL_DAC_Disable
 |  | LL_DAC_Enable
 |  | LL_DAC_IsEnabled
 | MAMP1 | LL_DAC_GetWaveNoiseLFSR
 |  | LL_DAC_GetWaveTriangleAmplitude
 |  | LL_DAC_SetWaveNoiseLFSR
 |  | LL_DAC_SetWaveTriangleAmplitude
 | MAMP2 | LL_DAC_GetWaveNoiseLFSR
 |  | LL_DAC_GetWaveTriangleAmplitude
 |  | LL_DAC_SetWaveNoiseLFSR
 |  | LL_DAC_SetWaveTriangleAmplitude
 | TEN1 | LL_DAC_DisableTrigger
 |  | LL_DAC_EnableTrigger
 |  | LL_DAC_IsTriggerEnabled
 | TEN2 | LL_DAC_DisableTrigger
 |  | LL_DAC_EnableTrigger
 |  | LL_DAC_IsTriggerEnabled
 | TSEL1 | LL_DAC_GetTriggerSource
 |  | LL_DAC_SetTriggerSource
 | TSEL2 | LL_DAC_GetTriggerSource
 |  | LL_DAC_SetTriggerSource
 | WAVE1 | LL_DAC_GetWaveAutoGeneration
 |  | LL_DAC_SetWaveAutoGeneration
 | WAVE2 | LL_DAC_GetWaveAutoGeneration
 |  | LL_DAC_SetWaveAutoGeneration
DHR12L1 | DACC1DHR | LL_DAC_ConvertData12LeftAligned
 |  | LL_DAC_DMA_GetRegAddr
DHR12L2 | DACC2DHR | LL_DAC_ConvertData12LeftAligned
 |  | LL_DAC_DMA_GetRegAddr
DHR12LD | DACC1DHR | LL_DAC_ConvertDualData12LeftAligned
 | DACC2DHR | LL_DAC_ConvertDualData12LeftAligned
DHR12R1 | DACC1DHR | LL_DAC_ConvertData12RightAligned
 |  | LL_DAC_DMA_GetRegAddr
DHR12R2 | DACC2DHR | LL_DAC_ConvertData12RightAligned
 |  | LL_DAC_DMA_GetRegAddr
DHR12RD | DACC1DHR | LL_DAC_ConvertDualData12RightAligned
 | DACC2DHR | LL_DAC_ConvertDualData12RightAligned
DHR8R1 | DACC1DHR | LL_DAC_ConvertData8RightAligned
 |  | LL_DAC_DMA_GetRegAddr
DHR8R2 | DACC2DHR | LL_DAC_ConvertData8RightAligned
 |  | LL_DAC_DMA_GetRegAddr
DHR8RD | DACC1DHR | LL_DAC_ConvertDualData8RightAligned
 | DACC2DHR | LL_DAC_ConvertDualData8RightAligned
DOR1 | DACC1DOR | LL_DAC_RetrieveOutputData
DOR2 | DACC2DOR | LL_DAC_RetrieveOutputData
SR | DMAUDR1 | LL_DAC_ClearFlag_DMAUDR1
 |  | LL_DAC_IsActiveFlag_DMAUDR1
 | DMAUDR2 | LL_DAC_ClearFlag_DMAUDR2
 |  | LL_DAC_IsActiveFlag_DMAUDR2
SWTRIGR | SWTRIG1 | LL_DAC_TrigSWConversion
 | SWTRIG2 | LL_DAC_TrigSWConversion
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STM32F373xC HAL User Manual: DAC Private Constants

Defines
DAC Private Constants
DAC

Defines

#define | DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
#define | DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
#define | DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
#define | DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
#define | DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
#define | DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
#define | DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
#define | DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
#define | DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
#define | DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
#define | DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
#define | DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
#define | DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
#define | DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
#define | DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
#define | DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
#define | DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
#define | DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
#define | DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
#define | DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
#define | DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
#define | DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
#define | DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */

Define Documentation

#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */

Definition at line 71 of file stm32f3xx_ll_dac.h.

#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */

Definition at line 72 of file stm32f3xx_ll_dac.h.

#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)

Definition at line 73 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_Disable(), LL_DAC_DisableDMAReq(), LL_DAC_DisableTrigger(), LL_DAC_Enable(), LL_DAC_EnableDMAReq(), LL_DAC_EnableTrigger(), LL_DAC_GetOutputBuffer(), LL_DAC_GetTriggerSource(), LL_DAC_GetWaveAutoGeneration(), LL_DAC_GetWaveNoiseLFSR(), LL_DAC_GetWaveTriangleAmplitude(), LL_DAC_Init(), LL_DAC_IsDMAReqEnabled(), LL_DAC_IsEnabled(), LL_DAC_IsTriggerEnabled(), LL_DAC_SetOutputBuffer(), LL_DAC_SetTriggerSource(), LL_DAC_SetWaveAutoGeneration(), LL_DAC_SetWaveNoiseLFSR(), and LL_DAC_SetWaveTriangleAmplitude().

#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */

Definition at line 107 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_ConvertDualData12LeftAligned().

#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */

Definition at line 106 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_ConvertDualData12RightAligned().

#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */

Definition at line 108 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_ConvertDualData8RightAligned().

#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */

Definition at line 112 of file stm32f3xx_ll_dac.h.

#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */

Definition at line 84 of file stm32f3xx_ll_dac.h.

#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */

Definition at line 88 of file stm32f3xx_ll_dac.h.

#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U

Definition at line 92 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12LeftAligned().

#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */

Definition at line 83 of file stm32f3xx_ll_dac.h.

#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */

Definition at line 87 of file stm32f3xx_ll_dac.h.

#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U

Definition at line 91 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12RightAligned().

#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */

Definition at line 85 of file stm32f3xx_ll_dac.h.

#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */

Definition at line 89 of file stm32f3xx_ll_dac.h.

#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U

Definition at line 93 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_ConvertData8RightAligned().

#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)

Definition at line 94 of file stm32f3xx_ll_dac.h.

#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */

Definition at line 96 of file stm32f3xx_ll_dac.h.

#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */

Definition at line 98 of file stm32f3xx_ll_dac.h.

#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)

Definition at line 99 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_RetrieveOutputData().

#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */

Definition at line 75 of file stm32f3xx_ll_dac.h.

#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */

Definition at line 77 of file stm32f3xx_ll_dac.h.

#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)

Definition at line 78 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_TrigSWConversion().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC Private Macros

Defines
DAC Private Macros
DAC

Defines

#define | IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)
#define | IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__)
#define | IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)
#define | __DAC_MASK_SHIFT(__BITS__, __MASK__) (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).
#define | __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Define Documentation

#define __DAC_MASK_SHIFT | ( | __BITS__,
 |  | __MASK__
 | ) | (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))

Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).

Parameters:
__BITS__ | Bits in register 32 bits
__MASK__ | Mask in register 32 bits
Return values:
Bits in register 32 bits

Definition at line 132 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12LeftAligned(), LL_DAC_ConvertData12RightAligned(), LL_DAC_ConvertData8RightAligned(), LL_DAC_DMA_GetRegAddr(), and LL_DAC_RetrieveOutputData().

#define __DAC_PTR_REG_OFFSET | ( | __REG__,
 |  | __REG_OFFFSET__
 | ) | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))

Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Parameters:
__REG__ | Register basis from which the offset is applied.
__REG_OFFFSET__ | Offset to be applied (unit: number of registers).
Return values:
Pointer to register address

Definition at line 143 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12LeftAligned(), LL_DAC_ConvertData12RightAligned(), LL_DAC_ConvertData8RightAligned(), LL_DAC_DMA_GetRegAddr(), and LL_DAC_RetrieveOutputData().

#define IS_LL_DAC_CHANNEL | ( | __DACX__,
 |  | __DAC_CHANNEL__
 | ) |
Value:
(                                                                            \
      ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                  \
   || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)                                  \
  )

Definition at line 67 of file stm32f3xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_OUTPUT_BUFFER ( __OUTPUT_BUFFER__ )
Value:
(   ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                     \
   || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                    \
  )

Definition at line 181 of file stm32f3xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_TRIGGER_SOURCE ( __TRIGGER_SOURCE__ )
Value:
(   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
  )

Definition at line 123 of file stm32f3xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG ( __WAVE_AUTO_GENERATION_CONFIG__ )
Value:
(   ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0)     \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1)       \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3)       \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7)       \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15)      \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31)      \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63)      \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127)     \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255)     \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511)     \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023)    \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047)    \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)    \
  )

Definition at line 154 of file stm32f3xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_WAVE_AUTO_GENER_MODE ( __WAVE_AUTO_GENERATION_MODE__ )
Value:
(   ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)     \
   || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)    \
   || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
  )

Definition at line 148 of file stm32f3xx_ll_dac.c.

Referenced by LL_DAC_Init().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_DAC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_DAC_InitTypeDef Struct Reference
DAC Exported Init structure

Structure definition of some features of DAC instance. More...

#include <stm32f3xx_ll_dac.h>

Data Fields

uint32_t | TriggerSource
uint32_t | WaveAutoGeneration
uint32_t | WaveAutoGenerationConfig
uint32_t | OutputBuffer

Detailed Description

Structure definition of some features of DAC instance.

Definition at line 160 of file stm32f3xx_ll_dac.h.

Field Documentation

uint32_t LL_DAC_InitTypeDef::OutputBuffer

Set the output buffer for the selected DAC channel. This parameter can be a value of DAC channel output buffer

This feature can be modified afterwards using unitary function LL_DAC_SetOutputBuffer().

Definition at line 179 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::TriggerSource

Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line). This parameter can be a value of DAC trigger source

This feature can be modified afterwards using unitary function LL_DAC_SetTriggerSource().

Definition at line 162 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::WaveAutoGeneration

Set the waveform automatic generation mode for the selected DAC channel. This parameter can be a value of DAC waveform automatic generation mode

This feature can be modified afterwards using unitary function LL_DAC_SetWaveAutoGeneration().

Definition at line 167 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::WaveAutoGenerationConfig

Set the waveform automatic generation mode for the selected DAC channel. If waveform automatic generation mode is set to noise, this parameter can be a value of DAC wave generation - Noise LFSR unmask bits If waveform automatic generation mode is set to triangle, this parameter can be a value of DAC wave generation - Triangle amplitude

Note:
If waveform automatic generation mode is disabled, this parameter is discarded.

This feature can be modified afterwards using unitary function LL_DAC_SetWaveNoiseLFSR() or LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected.

Definition at line 172 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_dac.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC flags

Defines
DAC flags
DAC Exported Constants

Flags defines which can be used with LL_DAC_ReadReg function. More...

Defines

#define | LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define | LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)

Detailed Description

Flags defines which can be used with LL_DAC_ReadReg function.

Define Documentation

#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)

DAC channel 1 flag DMA underrun

Definition at line 201 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_ClearFlag_DMAUDR1(), and LL_DAC_IsActiveFlag_DMAUDR1().

#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)

DAC channel 2 flag DMA underrun

Definition at line 205 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_ClearFlag_DMAUDR2(), and LL_DAC_IsActiveFlag_DMAUDR2().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC interruptions

Defines
DAC interruptions
DAC Exported Constants

IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions. More...

Defines

#define | LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)
#define | LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)

Detailed Description

IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions.

Define Documentation

#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)

DAC channel 1 interruption DMA underrun

Definition at line 215 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_DisableIT_DMAUDR1(), LL_DAC_EnableIT_DMAUDR1(), and LL_DAC_IsEnabledIT_DMAUDR1().

#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)

DAC channel 2 interruption DMA underrun

Definition at line 217 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_DisableIT_DMAUDR2(), LL_DAC_EnableIT_DMAUDR2(), and LL_DAC_IsEnabledIT_DMAUDR2().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC channels

Defines
DAC channels
DAC Exported Constants

Defines

#define | LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1)
#define | LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2)

Define Documentation

#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1)

DAC channel 1

Definition at line 226 of file stm32f3xx_ll_dac.h.

#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2)

DAC channel 2

Definition at line 228 of file stm32f3xx_ll_dac.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC trigger source

Defines
DAC trigger source
DAC Exported Constants

Defines

#define | LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U
#define | LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 )
#define | LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM18_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO)
#define | LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )

Define Documentation

#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )

DAC channel conversion trigger from external IP: external interrupt line 9.

Definition at line 278 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM18_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO)

DAC channel conversion trigger from external IP: TIM18 TRGO.

Definition at line 277 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 )

DAC channel conversion trigger from external IP: TIM2 TRGO.

Definition at line 275 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0)

DAC channel conversion trigger from external IP: TIM3 TRGO.

Definition at line 272 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)

DAC channel conversion trigger from external IP: TIM4 TRGO.

Definition at line 276 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)

DAC channel conversion trigger from external IP: TIM5 TRGO.

Definition at line 274 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U

DAC channel conversion trigger from external IP: TIM6 TRGO.

Definition at line 271 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 )

DAC channel conversion trigger from external IP: TIM7 TRGO.

Definition at line 273 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)

DAC channel conversion trigger internal (SW start)

Definition at line 237 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC waveform automatic generation mode

Defines
DAC waveform automatic generation mode
DAC Exported Constants

Defines

#define | LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U
#define | LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0)
#define | LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1)

Define Documentation

#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0)

DAC channel wave auto generation mode enabled, set generated noise waveform.

Definition at line 300 of file stm32f3xx_ll_dac.h.

#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U

DAC channel wave auto generation mode disabled.

Definition at line 299 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1)

DAC channel wave auto generation mode enabled, set generated triangle waveform.

Definition at line 301 of file stm32f3xx_ll_dac.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC wave generation - Noise LFSR unmask bits

Defines
DAC wave generation - Noise LFSR unmask bits
DAC Exported Constants

Defines

#define | LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U

Noise wave generation, unmask LFSR bit0, for the selected DAC channel

Definition at line 309 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )

Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel

Definition at line 319 of file stm32f3xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel

Definition at line 320 of file stm32f3xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel

Definition at line 310 of file stm32f3xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )

Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel

Definition at line 311 of file stm32f3xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel

Definition at line 312 of file stm32f3xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )

Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel

Definition at line 313 of file stm32f3xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel

Definition at line 314 of file stm32f3xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )

Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel

Definition at line 315 of file stm32f3xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel

Definition at line 316 of file stm32f3xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )

Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel

Definition at line 317 of file stm32f3xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel

Definition at line 318 of file stm32f3xx_ll_dac.h.

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STM32F373xC HAL User Manual: DAC wave generation - Triangle amplitude

Defines
DAC wave generation - Triangle amplitude
DAC Exported Constants

Defines

#define | LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U
#define | LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U

Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel

Definition at line 328 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel

Definition at line 337 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )

Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel

Definition at line 334 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel

Definition at line 331 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )

Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel

Definition at line 338 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel

Definition at line 335 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel

Definition at line 329 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )

Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel

Definition at line 332 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel

Definition at line 339 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )

Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel

Definition at line 336 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel

Definition at line 333 of file stm32f3xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )

Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel

Definition at line 330 of file stm32f3xx_ll_dac.h.

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STM32F373xC HAL User Manual: DAC channel output buffer

Defines
DAC channel output buffer
DAC Exported Constants

Defines

#define | LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U
#define | LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1)

Define Documentation

#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1)

The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption

Definition at line 348 of file stm32f3xx_ll_dac.h.

#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U

The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption

Definition at line 347 of file stm32f3xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

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STM32F373xC HAL User Manual: DAC channel output resolution

Defines
DAC channel output resolution
DAC Exported Constants

Defines

#define | LL_DAC_RESOLUTION_12B 0x00000000U
#define | LL_DAC_RESOLUTION_8B 0x00000002U

Define Documentation

#define LL_DAC_RESOLUTION_12B 0x00000000U

DAC channel resolution 12 bits

Definition at line 362 of file stm32f3xx_ll_dac.h.

#define LL_DAC_RESOLUTION_8B 0x00000002U

DAC channel resolution 8 bits

Definition at line 363 of file stm32f3xx_ll_dac.h.

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STM32F373xC HAL User Manual: DAC registers compliant with specific purpose

Defines
DAC registers compliant with specific purpose
DAC Exported Constants

Defines

#define | LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK
#define | LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK
#define | LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK

Define Documentation

#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK

DAC channel data holding register 12 bits left aligned

Definition at line 375 of file stm32f3xx_ll_dac.h.

#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK

DAC channel data holding register 12 bits right aligned

Definition at line 374 of file stm32f3xx_ll_dac.h.

#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK

DAC channel data holding register 8 bits right aligned

Definition at line 376 of file stm32f3xx_ll_dac.h.

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STM32F373xC HAL User Manual: Definitions of DAC hardware constraints delays

Defines
Definitions of DAC hardware constraints delays
DAC Exported Constants

Defines

#define | LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U
#define | LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U

Detailed Description

Note:
Only DAC IP HW delays are defined in DAC LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U

Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable)

Definition at line 401 of file stm32f3xx_ll_dac.h.

#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U

Delay for DAC channel voltage settling time

Definition at line 414 of file stm32f3xx_ll_dac.h.

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STM32F373xC HAL User Manual: Common write and read registers macros

Defines
Common write and read registers macros
DAC Exported Macros

Defines

#define | LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DAC register.
#define | LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DAC register.

Define Documentation

#define LL_DAC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in DAC register.

Parameters:
__INSTANCE__ | DAC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 447 of file stm32f3xx_ll_dac.h.

#define LL_DAC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in DAC register.

Parameters:
__INSTANCE__ | DAC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 439 of file stm32f3xx_ll_dac.h.

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STM32F373xC HAL User Manual: DAC helper macro

Defines
DAC helper macro
DAC Exported Macros

Defines

#define | __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
Helper macro to get DAC channel number in decimal format from literals LL_DAC_CHANNEL_x.
#define | __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x from number in decimal format.
#define | __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
Helper macro to define the DAC conversion data full-scale digital value corresponding to the selected DAC resolution.
#define | __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__)
Helper macro to calculate the DAC conversion data (unit: digital value) corresponding to a voltage (unit: mVolt).

Define Documentation

#define __LL_DAC_CALC_VOLTAGE_TO_DATA | ( | __VREFANALOG_VOLTAGE__,
 |  | __DAC_VOLTAGE__,
 |  | __DAC_RESOLUTION__
 | ) |
Value:
((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)              \
   / (__VREFANALOG_VOLTAGE__)                                                  \
  )

Helper macro to calculate the DAC conversion data (unit: digital value) corresponding to a voltage (unit: mVolt).

Note:
This helper macro is intended to provide input data in voltage rather than digital value, to be used with LL DAC functions such as LL_DAC_ConvertData12RightAligned().
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__DAC_VOLTAGE__ | Voltage to be generated by DAC channel (unit: mVolt).
__DAC_RESOLUTION__ This parameter can be one of the following values:
  • LL_DAC_RESOLUTION_12B
  • LL_DAC_RESOLUTION_8B
Return values:
DAC conversion data (unit: digital value)

Definition at line 554 of file stm32f3xx_ll_dac.h.

#define __LL_DAC_CHANNEL_TO_DECIMAL_NB ( __CHANNEL__ ) ((__CHANNEL__) & DAC_SWTR_CHX_MASK)

Helper macro to get DAC channel number in decimal format from literals LL_DAC_CHANNEL_x.

Example: __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) will return decimal number "1".

Note:
The input can be a value from functions where a channel number is returned.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Return values:
1...2 (value "2" depending on DAC channel 2 availability)

Definition at line 473 of file stm32f3xx_ll_dac.h.

#define __LL_DAC_DECIMAL_NB_TO_CHANNEL ( __DECIMAL_NB__ )
Value:
(((__DECIMAL_NB__) == 1U)                                                     \
    ? (                                                                        \
       LL_DAC_CHANNEL_1                                                        \
      )                                                                        \
      :                                                                        \
      (((__DECIMAL_NB__) == 2U)                                                 \
        ? (                                                                    \
           LL_DAC_CHANNEL_2                                                    \
          )                                                                    \
          :                                                                    \
          (                                                                    \
           0                                                                   \
          )                                                                    \
      )                                                                        \
  )

Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x from number in decimal format.

Example: __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) will return a data equivalent to "LL_DAC_CHANNEL_1".

Note:
If the input parameter does not correspond to a DAC channel, this macro returns value '0'.
Parameters:
__DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
Return values:
Returned value can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.

Definition at line 493 of file stm32f3xx_ll_dac.h.

#define __LL_DAC_DIGITAL_SCALE ( __DAC_RESOLUTION__ ) ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))

Helper macro to define the DAC conversion data full-scale digital value corresponding to the selected DAC resolution.

Note:
DAC conversion data full-scale corresponds to voltage range determined by analog voltage references Vref+ and Vref- (refer to reference manual).
Parameters:
__DAC_RESOLUTION__ This parameter can be one of the following values:
  • LL_DAC_RESOLUTION_12B
  • LL_DAC_RESOLUTION_8B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 533 of file stm32f3xx_ll_dac.h.

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STM32F373xC HAL User Manual: Configuration of DAC channels

Functions
Configuration of DAC channels
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_SetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
Set the conversion trigger source for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the conversion trigger source for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
Set the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE uint32_t | LL_DAC_GetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE void | LL_DAC_SetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE void | LL_DAC_SetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
Set the output buffer for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output buffer state for the selected DAC channel.

Function Documentation

__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the output buffer state for the selected DAC channel.

Reference Manual to LL API cross reference:
CR BOFF1 LL_DAC_GetOutputBuffer
CR BOFF2 LL_DAC_GetOutputBuffer
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Return values:
Returned value can be one of the following values:
  • LL_DAC_OUTPUT_BUFFER_ENABLE
  • LL_DAC_OUTPUT_BUFFER_DISABLE
  • LL_DAC_OUTPUT_SWITCH_DISABLE (1)
  • LL_DAC_OUTPUT_SWITCH_ENABLE (1)
(1) Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6.

Definition at line 912 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the conversion trigger source for the selected DAC channel.

Note:
For conversion trigger source to be effective, DAC trigger must be enabled using function LL_DAC_EnableTrigger().
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR TSEL1 LL_DAC_GetTriggerSource
CR TSEL2 LL_DAC_GetTriggerSource
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Return values:
Returned value can be one of the following values:
  • LL_DAC_TRIG_SOFTWARE
  • LL_DAC_TRIG_EXT_TIM2_TRGO
  • LL_DAC_TRIG_EXT_TIM3_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM4_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM5_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM6_TRGO
  • LL_DAC_TRIG_EXT_TIM7_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM8_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM15_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM18_TRGO (1)
  • LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1)
  • LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2)
  • LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3)
  • LL_DAC_TRIG_EXT_EXTI_LINE9
(1) On STM32F3, parameter not available on all devices (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).
(3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).

Definition at line 658 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the waveform automatic generation mode for the selected DAC channel.

Reference Manual to LL API cross reference:
CR WAVE1 LL_DAC_GetWaveAutoGeneration
CR WAVE2 LL_DAC_GetWaveAutoGeneration
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Return values:
Returned value can be one of the following values:
  • LL_DAC_WAVE_AUTO_GENERATION_NONE
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE

Definition at line 707 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).

Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_GetWaveNoiseLFSR
CR MAMP2 LL_DAC_GetWaveNoiseLFSR
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Return values:
Returned value can be one of the following values:
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0

Definition at line 779 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.

Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_GetWaveTriangleAmplitude
CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Return values:
Returned value can be one of the following values:
  • LL_DAC_TRIANGLE_AMPLITUDE_1
  • LL_DAC_TRIANGLE_AMPLITUDE_3
  • LL_DAC_TRIANGLE_AMPLITUDE_7
  • LL_DAC_TRIANGLE_AMPLITUDE_15
  • LL_DAC_TRIANGLE_AMPLITUDE_31
  • LL_DAC_TRIANGLE_AMPLITUDE_63
  • LL_DAC_TRIANGLE_AMPLITUDE_127
  • LL_DAC_TRIANGLE_AMPLITUDE_255
  • LL_DAC_TRIANGLE_AMPLITUDE_511
  • LL_DAC_TRIANGLE_AMPLITUDE_1023
  • LL_DAC_TRIANGLE_AMPLITUDE_2047
  • LL_DAC_TRIANGLE_AMPLITUDE_4095

Definition at line 851 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetOutputBuffer | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | OutputBuffer
 | ) |  |

Set the output buffer for the selected DAC channel.

Reference Manual to LL API cross reference:
CR BOFF1 LL_DAC_SetOutputBuffer
CR BOFF2 LL_DAC_SetOutputBuffer
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
OutputBuffer This parameter can be one of the following values:
  • LL_DAC_OUTPUT_BUFFER_ENABLE
  • LL_DAC_OUTPUT_BUFFER_DISABLE
  • LL_DAC_OUTPUT_SWITCH_DISABLE (1)
  • LL_DAC_OUTPUT_SWITCH_ENABLE (1)
(1) Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6.
Return values:
None

Definition at line 882 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetTriggerSource | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | TriggerSource
 | ) |  |

Set the conversion trigger source for the selected DAC channel.

Note:
For conversion trigger source to be effective, DAC trigger must be enabled using function LL_DAC_EnableTrigger().
To set conversion trigger source, DAC channel must be disabled. Otherwise, the setting is discarded.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR TSEL1 LL_DAC_SetTriggerSource
CR TSEL2 LL_DAC_SetTriggerSource
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
TriggerSource This parameter can be one of the following values:
  • LL_DAC_TRIG_SOFTWARE
  • LL_DAC_TRIG_EXT_TIM2_TRGO
  • LL_DAC_TRIG_EXT_TIM3_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM4_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM5_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM6_TRGO
  • LL_DAC_TRIG_EXT_TIM7_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM8_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM15_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM18_TRGO (1)
  • LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1)
  • LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2)
  • LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3)
  • LL_DAC_TRIG_EXT_EXTI_LINE9
(1) On STM32F3, parameter not available on all devices (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).
(3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).
Return values:
None

Definition at line 616 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | WaveAutoGeneration
 | ) |  |

Set the waveform automatic generation mode for the selected DAC channel.

Reference Manual to LL API cross reference:
CR WAVE1 LL_DAC_SetWaveAutoGeneration
CR WAVE2 LL_DAC_SetWaveAutoGeneration
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
WaveAutoGeneration This parameter can be one of the following values:
  • LL_DAC_WAVE_AUTO_GENERATION_NONE
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
Return values:
None

Definition at line 683 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | NoiseLFSRMask
 | ) |  |

Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).

Note:
For wave generation to be effective, DAC channel wave generation mode must be enabled using function LL_DAC_SetWaveAutoGeneration().
This setting can be set when the selected DAC channel is disabled (otherwise, the setting operation is ignored).
Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_SetWaveNoiseLFSR
CR MAMP2 LL_DAC_SetWaveNoiseLFSR
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
NoiseLFSRMask This parameter can be one of the following values:
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
Return values:
None

Definition at line 746 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | TriangleAmplitude
 | ) |  |

Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.

Note:
For wave generation to be effective, DAC channel wave generation mode must be enabled using function LL_DAC_SetWaveAutoGeneration().
This setting can be set when the selected DAC channel is disabled (otherwise, the setting operation is ignored).
Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_SetWaveTriangleAmplitude
CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
TriangleAmplitude This parameter can be one of the following values:
  • LL_DAC_TRIANGLE_AMPLITUDE_1
  • LL_DAC_TRIANGLE_AMPLITUDE_3
  • LL_DAC_TRIANGLE_AMPLITUDE_7
  • LL_DAC_TRIANGLE_AMPLITUDE_15
  • LL_DAC_TRIANGLE_AMPLITUDE_31
  • LL_DAC_TRIANGLE_AMPLITUDE_63
  • LL_DAC_TRIANGLE_AMPLITUDE_127
  • LL_DAC_TRIANGLE_AMPLITUDE_255
  • LL_DAC_TRIANGLE_AMPLITUDE_511
  • LL_DAC_TRIANGLE_AMPLITUDE_1023
  • LL_DAC_TRIANGLE_AMPLITUDE_2047
  • LL_DAC_TRIANGLE_AMPLITUDE_4095
Return values:
None

Definition at line 818 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Management

Functions
DMA Management
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_EnableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC DMA transfer request of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC DMA transfer request of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsDMAReqEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC DMA transfer request state of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_DMA_GetRegAddr (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
Function to help to configure DMA transfer to DAC: retrieve the DAC register address from DAC instance and a list of DAC registers intended to be used (most commonly) with DMA transfer.

Function Documentation

__STATIC_INLINE void LL_DAC_DisableDMAReq | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Disable DAC DMA transfer request of the selected channel.

Note:
To configure DMA source address (peripheral address), use function LL_DAC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CR DMAEN1 LL_DAC_DisableDMAReq
CR DMAEN2 LL_DAC_DisableDMAReq
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 963 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Register
 | ) |  |

Function to help to configure DMA transfer to DAC: retrieve the DAC register address from DAC instance and a list of DAC registers intended to be used (most commonly) with DMA transfer.

Note:
These DAC registers are data holding registers: when DAC conversion is requested, DAC generates a DMA transfer request to have data available in DAC data holding registers.
This macro is intended to be used with LL DMA driver, refer to function "LL_DMA_ConfigAddresses()". Example: LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_1, (uint32_t)&< array or variable >, LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
Reference Manual to LL API cross reference:
DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr
DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr
DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr
DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr
DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr
DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Register This parameter can be one of the following values:
  • LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
  • LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
  • LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
Return values:
DAC register address

Definition at line 1024 of file stm32f3xx_ll_dac.h.

References __DAC_MASK_SHIFT, and __DAC_PTR_REG_OFFSET.

__STATIC_INLINE void LL_DAC_EnableDMAReq | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Enable DAC DMA transfer request of the selected channel.

Note:
To configure DMA source address (peripheral address), use function LL_DAC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CR DMAEN1 LL_DAC_EnableDMAReq
CR DMAEN2 LL_DAC_EnableDMAReq
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 942 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get DAC DMA transfer request state of the selected channel.

(0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)

Reference Manual to LL API cross reference:
CR DMAEN1 LL_DAC_IsDMAReqEnabled
CR DMAEN2 LL_DAC_IsDMAReqEnabled
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Return values:
State of bit (1 or 0).

Definition at line 983 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Operation on DAC channels

Functions
Operation on DAC channels
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_Enable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC selected channel.
__STATIC_INLINE void | LL_DAC_Disable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC enable state of the selected channel.
__STATIC_INLINE void | LL_DAC_EnableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC trigger of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC trigger of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsTriggerEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC trigger state of the selected channel.
__STATIC_INLINE void | LL_DAC_TrigSWConversion (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Trig DAC conversion by software for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12LeftAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData8RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertDualData12RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData12LeftAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData8RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE uint32_t | LL_DAC_RetrieveOutputData (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Retrieve output data currently generated for the selected DAC channel.

Function Documentation

__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Data
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for the selected DAC channel.

Reference Manual to LL API cross reference:
DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned
DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Data | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 1236 of file stm32f3xx_ll_dac.h.

References __DAC_MASK_SHIFT, __DAC_PTR_REG_OFFSET, and DAC_REG_DHR12LX_REGOFFSET_MASK.

__STATIC_INLINE void LL_DAC_ConvertData12RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Data
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.

Reference Manual to LL API cross reference:
DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned
DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Data | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 1211 of file stm32f3xx_ll_dac.h.

References __DAC_MASK_SHIFT, __DAC_PTR_REG_OFFSET, and DAC_REG_DHR12RX_REGOFFSET_MASK.

__STATIC_INLINE void LL_DAC_ConvertData8RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Data
 | ) |  |

Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.

Reference Manual to LL API cross reference:
DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned
DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Data | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1261 of file stm32f3xx_ll_dac.h.

References __DAC_MASK_SHIFT, __DAC_PTR_REG_OFFSET, and DAC_REG_DHR8RX_REGOFFSET_MASK.

__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DataChannel1,
 |  | uint32_t | DataChannel2
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for both DAC channels.

Reference Manual to LL API cross reference:
DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned
DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
Parameters:
DACx | DAC instance
DataChannel1 | Value between Min_Data=0x000 and Max_Data=0xFFF
DataChannel2 | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 1300 of file stm32f3xx_ll_dac.h.

References DAC_DHR12LD_DACC2DHR_BITOFFSET_POS.

__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DataChannel1,
 |  | uint32_t | DataChannel2
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for both DAC channels.

Reference Manual to LL API cross reference:
DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned
DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
Parameters:
DACx | DAC instance
DataChannel1 | Value between Min_Data=0x000 and Max_Data=0xFFF
DataChannel2 | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 1282 of file stm32f3xx_ll_dac.h.

References DAC_DHR12RD_DACC2DHR_BITOFFSET_POS.

__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DataChannel1,
 |  | uint32_t | DataChannel2
 | ) |  |

Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for both DAC channels.

Reference Manual to LL API cross reference:
DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned
DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
Parameters:
DACx | DAC instance
DataChannel1 | Value between Min_Data=0x00 and Max_Data=0xFF
DataChannel2 | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1321 of file stm32f3xx_ll_dac.h.

References DAC_DHR8RD_DACC2DHR_BITOFFSET_POS.

__STATIC_INLINE void LL_DAC_Disable | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Disable DAC selected channel.

Reference Manual to LL API cross reference:
CR EN1 LL_DAC_Disable
CR EN2 LL_DAC_Disable
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 1073 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_DisableTrigger | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Disable DAC trigger of the selected channel.

Reference Manual to LL API cross reference:
CR TEN1 LL_DAC_DisableTrigger
CR TEN2 LL_DAC_DisableTrigger
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 1140 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_Enable | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Enable DAC selected channel.

Reference Manual to LL API cross reference:
CR EN1 LL_DAC_Enable
CR EN2 LL_DAC_Enable
Note:
After enable from off state, DAC channel requires a delay for output voltage to reach accuracy +/- 1 LSB. Refer to device datasheet, parameter "tWAKEUP".
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 1054 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_EnableTrigger | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Enable DAC trigger of the selected channel.

Note:
- If DAC trigger is disabled, DAC conversion is performed automatically once the data holding register is updated, using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": LL_DAC_ConvertData12RightAligned(), ...
  • If DAC trigger is enabled, DAC conversion is performed only when a hardware of software trigger event is occurring. Select trigger source using function LL_DAC_SetTriggerSource().
Reference Manual to LL API cross reference:
CR TEN1 LL_DAC_EnableTrigger
CR TEN2 LL_DAC_EnableTrigger
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 1121 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_IsEnabled | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get DAC enable state of the selected channel.

(0: DAC channel is disabled, 1: DAC channel is enabled)

Reference Manual to LL API cross reference:
CR EN1 LL_DAC_IsEnabled
CR EN2 LL_DAC_IsEnabled
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Return values:
State of bit (1 or 0).

Definition at line 1093 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

Referenced by LL_DAC_Init().

__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get DAC trigger state of the selected channel.

(0: DAC trigger is disabled, 1: DAC trigger is enabled)

Reference Manual to LL API cross reference:
CR TEN1 LL_DAC_IsTriggerEnabled
CR TEN2 LL_DAC_IsTriggerEnabled
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Return values:
State of bit (1 or 0).

Definition at line 1160 of file stm32f3xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Retrieve output data currently generated for the selected DAC channel.

Note:
Whatever alignment and resolution settings (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": LL_DAC_ConvertData12RightAligned(), ...), output data format is 12 bits right aligned (LSB aligned on bit 0).
Reference Manual to LL API cross reference:
DOR1 DACC1DOR LL_DAC_RetrieveOutputData
DOR2 DACC2DOR LL_DAC_RetrieveOutputData
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1346 of file stm32f3xx_ll_dac.h.

References __DAC_MASK_SHIFT, __DAC_PTR_REG_OFFSET, and DAC_REG_DORX_REGOFFSET_MASK.

__STATIC_INLINE void LL_DAC_TrigSWConversion | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Trig DAC conversion by software for the selected DAC channel.

Note:
Preliminarily, DAC trigger must be set to software trigger using function LL_DAC_SetTriggerSource() with parameter "LL_DAC_TRIGGER_SOFTWARE". and DAC trigger must be enabled using function LL_DAC_EnableTrigger().
For devices featuring DAC with 2 channels: this function can perform a SW start of both DAC channels simultaneously. Two channels can be selected as parameter. Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
Reference Manual to LL API cross reference:
SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion
SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
Parameters:
DACx DAC instance
DAC_Channel This parameter can a combination of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 1189 of file stm32f3xx_ll_dac.h.

References DAC_SWTR_CHX_MASK.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLAG Management

Functions
FLAG Management
DAC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR1 (DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR2 (DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 2.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR1 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 1.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR2 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 2.

Function Documentation

__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1 ( DAC_TypeDef * DACx )

Clear DAC underrun flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1390 of file stm32f3xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR1.

__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2 ( DAC_TypeDef * DACx )

Clear DAC underrun flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1402 of file stm32f3xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR2.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1 ( DAC_TypeDef * DACx )

Get DAC underrun flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1366 of file stm32f3xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR1.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2 ( DAC_TypeDef * DACx )

Get DAC underrun flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1378 of file stm32f3xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR2.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IT management

Functions
IT management
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR1 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR2 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR1 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR2 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR1 (DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR2 (DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 2.

Function Documentation

__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1 ( DAC_TypeDef * DACx )

Disable DMA underrun interrupt for DAC channel 1.

Reference Manual to LL API cross reference:
CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1446 of file stm32f3xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE1.

__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2 ( DAC_TypeDef * DACx )

Disable DMA underrun interrupt for DAC channel 2.

Reference Manual to LL API cross reference:
CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1458 of file stm32f3xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE2.

__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1 ( DAC_TypeDef * DACx )

Enable DMA underrun interrupt for DAC channel 1.

Reference Manual to LL API cross reference:
CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1422 of file stm32f3xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE1.

__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2 ( DAC_TypeDef * DACx )

Enable DMA underrun interrupt for DAC channel 2.

Reference Manual to LL API cross reference:
CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1434 of file stm32f3xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE2.

__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1 ( DAC_TypeDef * DACx )

Get DMA underrun interrupt for DAC channel 1.

Reference Manual to LL API cross reference:
CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1470 of file stm32f3xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE1.

__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2 ( DAC_TypeDef * DACx )

Get DMA underrun interrupt for DAC channel 2.

Reference Manual to LL API cross reference:
CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1482 of file stm32f3xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE2.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DAC Exported Functions

Functions

ErrorStatus | LL_DAC_DeInit (DAC_TypeDef *DACx)
De-initialize registers of the selected DAC instance to their default reset values.
ErrorStatus | LL_DAC_Init (DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
Initialize some features of DAC instance.
void | LL_DAC_StructInit (LL_DAC_InitTypeDef *DAC_InitStruct)
Set each LL_DAC_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_DAC_DeInit ( DAC_TypeDef * DACx )

De-initialize registers of the selected DAC instance to their default reset values.

Parameters:
DACx DAC instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DAC registers are de-initialized
  • ERROR: not applicable

Definition at line 210 of file stm32f3xx_ll_dac.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_DAC1, LL_APB1_GRP1_PERIPH_DAC2, and LL_APB1_GRP1_ReleaseReset().

ErrorStatus LL_DAC_Init | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | LL_DAC_InitTypeDef * | DAC_InitStruct
 | ) |  |

Initialize some features of DAC instance.

Note:
The setting of these parameters by function LL_DAC_Init() is conditioned to DAC state: DAC instance must be disabled.
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 serie, parameter not available on all devices. Refer to device datasheet for channels availability.
DAC_InitStruct | Pointer to a LL_DAC_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DAC registers are initialized
  • ERROR: DAC registers are not initialized

Definition at line 253 of file stm32f3xx_ll_dac.c.

References assert_param, DAC_CR_CHX_BITOFFSET_MASK, IS_LL_DAC_CHANNEL, IS_LL_DAC_OUTPUT_BUFFER, IS_LL_DAC_TRIGGER_SOURCE, IS_LL_DAC_WAVE_AUTO_GENER_CONFIG, IS_LL_DAC_WAVE_AUTO_GENER_MODE, LL_DAC_IsEnabled(), LL_DAC_WAVE_AUTO_GENERATION_NONE, LL_DAC_InitTypeDef::OutputBuffer, LL_DAC_InitTypeDef::TriggerSource, LL_DAC_InitTypeDef::WaveAutoGeneration, and LL_DAC_InitTypeDef::WaveAutoGenerationConfig.

void LL_DAC_StructInit ( LL_DAC_InitTypeDef * DAC_InitStruct )

Set each LL_DAC_InitTypeDef field to default value.

Parameters:
DAC_InitStruct pointer to a LL_DAC_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 321 of file stm32f3xx_ll_dac.c.

References LL_DAC_NOISE_LFSR_UNMASK_BIT0, LL_DAC_OUTPUT_BUFFER_ENABLE, LL_DAC_TRIG_SOFTWARE, LL_DAC_WAVE_AUTO_GENERATION_NONE, LL_DAC_InitTypeDef::OutputBuffer, LL_DAC_InitTypeDef::TriggerSource, LL_DAC_InitTypeDef::WaveAutoGeneration, and LL_DAC_InitTypeDef::WaveAutoGenerationConfig.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA

Modules
DMA
STM32F3xx_LL_Driver

Modules

DMA Private Variables
DMA Private Macros
DMA Exported Init structure
DMA Exported Constants
DMA Exported Macros
DMA Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for DMA registers.

Register | Bit | Function
CCR | CIRC | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetMode
 |  | LL_DMA_SetMode
 | DIR | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetDataTransferDirection
 |  | LL_DMA_SetDataTransferDirection
 | EN | LL_DMA_DisableChannel
 |  | LL_DMA_EnableChannel
 |  | LL_DMA_IsEnabledChannel
 | HTIE | LL_DMA_DisableIT_HT
 |  | LL_DMA_EnableIT_HT
 |  | LL_DMA_IsEnabledIT_HT
 | MEM2MEM | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetDataTransferDirection
 |  | LL_DMA_SetDataTransferDirection
 | MINC | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetMemoryIncMode
 |  | LL_DMA_SetMemoryIncMode
 | MSIZE | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetMemorySize
 |  | LL_DMA_SetMemorySize
 | PINC | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetPeriphIncMode
 |  | LL_DMA_SetPeriphIncMode
 | PL | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetChannelPriorityLevel
 |  | LL_DMA_SetChannelPriorityLevel
 | PSIZE | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetPeriphSize
 |  | LL_DMA_SetPeriphSize
 | TCIE | LL_DMA_DisableIT_TC
 |  | LL_DMA_EnableIT_TC
 |  | LL_DMA_IsEnabledIT_TC
 | TEIE | LL_DMA_DisableIT_TE
 |  | LL_DMA_EnableIT_TE
 |  | LL_DMA_IsEnabledIT_TE
CMAR | MA | LL_DMA_ConfigAddresses
 |  | LL_DMA_GetM2MDstAddress
 |  | LL_DMA_GetMemoryAddress
 |  | LL_DMA_SetM2MDstAddress
 |  | LL_DMA_SetMemoryAddress
CNDTR | NDT | LL_DMA_GetDataLength
 |  | LL_DMA_SetDataLength
CPAR | PA | LL_DMA_ConfigAddresses
 |  | LL_DMA_GetM2MSrcAddress
 |  | LL_DMA_GetPeriphAddress
 |  | LL_DMA_SetM2MSrcAddress
 |  | LL_DMA_SetPeriphAddress
IFCR | CGIF1 | LL_DMA_ClearFlag_GI1
 | CGIF2 | LL_DMA_ClearFlag_GI2
 | CGIF3 | LL_DMA_ClearFlag_GI3
 | CGIF4 | LL_DMA_ClearFlag_GI4
 | CGIF5 | LL_DMA_ClearFlag_GI5
 | CGIF6 | LL_DMA_ClearFlag_GI6
 | CGIF7 | LL_DMA_ClearFlag_GI7
 | CHTIF1 | LL_DMA_ClearFlag_HT1
 | CHTIF2 | LL_DMA_ClearFlag_HT2
 | CHTIF3 | LL_DMA_ClearFlag_HT3
 | CHTIF4 | LL_DMA_ClearFlag_HT4
 | CHTIF5 | LL_DMA_ClearFlag_HT5
 | CHTIF6 | LL_DMA_ClearFlag_HT6
 | CHTIF7 | LL_DMA_ClearFlag_HT7
 | CTCIF1 | LL_DMA_ClearFlag_TC1
 | CTCIF2 | LL_DMA_ClearFlag_TC2
 | CTCIF3 | LL_DMA_ClearFlag_TC3
 | CTCIF4 | LL_DMA_ClearFlag_TC4
 | CTCIF5 | LL_DMA_ClearFlag_TC5
 | CTCIF6 | LL_DMA_ClearFlag_TC6
 | CTCIF7 | LL_DMA_ClearFlag_TC7
 | CTEIF1 | LL_DMA_ClearFlag_TE1
 | CTEIF2 | LL_DMA_ClearFlag_TE2
 | CTEIF3 | LL_DMA_ClearFlag_TE3
 | CTEIF4 | LL_DMA_ClearFlag_TE4
 | CTEIF5 | LL_DMA_ClearFlag_TE5
 | CTEIF6 | LL_DMA_ClearFlag_TE6
 | CTEIF7 | LL_DMA_ClearFlag_TE7
ISR | GIF1 | LL_DMA_IsActiveFlag_GI1
 | GIF2 | LL_DMA_IsActiveFlag_GI2
 | GIF3 | LL_DMA_IsActiveFlag_GI3
 | GIF4 | LL_DMA_IsActiveFlag_GI4
 | GIF5 | LL_DMA_IsActiveFlag_GI5
 | GIF6 | LL_DMA_IsActiveFlag_GI6
 | GIF7 | LL_DMA_IsActiveFlag_GI7
 | HTIF1 | LL_DMA_IsActiveFlag_HT1
 | HTIF2 | LL_DMA_IsActiveFlag_HT2
 | HTIF3 | LL_DMA_IsActiveFlag_HT3
 | HTIF4 | LL_DMA_IsActiveFlag_HT4
 | HTIF5 | LL_DMA_IsActiveFlag_HT5
 | HTIF6 | LL_DMA_IsActiveFlag_HT6
 | HTIF7 | LL_DMA_IsActiveFlag_HT7
 | TCIF1 | LL_DMA_IsActiveFlag_TC1
 | TCIF2 | LL_DMA_IsActiveFlag_TC2
 | TCIF3 | LL_DMA_IsActiveFlag_TC3
 | TCIF4 | LL_DMA_IsActiveFlag_TC4
 | TCIF5 | LL_DMA_IsActiveFlag_TC5
 | TCIF6 | LL_DMA_IsActiveFlag_TC6
 | TCIF7 | LL_DMA_IsActiveFlag_TC7
 | TEIF1 | LL_DMA_IsActiveFlag_TE1
 | TEIF2 | LL_DMA_IsActiveFlag_TE2
 | TEIF3 | LL_DMA_IsActiveFlag_TE3
 | TEIF4 | LL_DMA_IsActiveFlag_TE4
 | TEIF5 | LL_DMA_IsActiveFlag_TE5
 | TEIF6 | LL_DMA_IsActiveFlag_TE6
 | TEIF7 | LL_DMA_IsActiveFlag_TE7
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Private Variables

Variables
DMA Private Variables
DMA

Variables

static const uint8_t CHANNEL_OFFSET_TAB []

Variable Documentation

const uint8_t CHANNEL_OFFSET_TAB[] [static]
Initial value:
{
  (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
}

Definition at line 63 of file stm32f3xx_ll_dma.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMA

Defines

#define | IS_LL_DMA_DIRECTION(__VALUE__)
#define | IS_LL_DMA_MODE(__VALUE__)
#define | IS_LL_DMA_PERIPHINCMODE(__VALUE__)
#define | IS_LL_DMA_MEMORYINCMODE(__VALUE__)
#define | IS_LL_DMA_PERIPHDATASIZE(__VALUE__)
#define | IS_LL_DMA_MEMORYDATASIZE(__VALUE__)
#define | IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_DMA_PRIORITY(__VALUE__)
#define | IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)

Define Documentation

#define IS_LL_DMA_ALL_CHANNEL_INSTANCE | ( | INSTANCE,
 |  | CHANNEL
 | ) |
Value:
((((INSTANCE) == DMA1) && \
                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_5) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_6) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
                                                         (((INSTANCE) == DMA2) && \
                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_5))))

Definition at line 111 of file stm32f3xx_ll_dma.c.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

#define IS_LL_DMA_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))

Definition at line 63 of file stm32f3xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MEMORYDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))

Definition at line 80 of file stm32f3xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MEMORYINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))

Definition at line 73 of file stm32f3xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MODE_NORMAL) || \
                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))

Definition at line 67 of file stm32f3xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_NBDATA ( __VALUE__ ) ((__VALUE__) <= 0x0000FFFFU)

Definition at line 84 of file stm32f3xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))

Definition at line 76 of file stm32f3xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))

Definition at line 70 of file stm32f3xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PRIORITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))

Definition at line 87 of file stm32f3xx_ll_dma.c.

Referenced by LL_DMA_Init().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_DMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_DMA_InitTypeDef Struct Reference
DMA Exported Init structure

#include <stm32f3xx_ll_dma.h>

Data Fields

uint32_t | PeriphOrM2MSrcAddress
uint32_t | MemoryOrM2MDstAddress
uint32_t | Direction
uint32_t | Mode
uint32_t | PeriphOrM2MSrcIncMode
uint32_t | MemoryOrM2MDstIncMode
uint32_t | PeriphOrM2MSrcDataSize
uint32_t | MemoryOrM2MDstDataSize
uint32_t | NbData
uint32_t | Priority

Detailed Description

Definition at line 93 of file stm32f3xx_ll_dma.h.

Field Documentation

uint32_t LL_DMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of Transfer Direction

This feature can be modified afterwards using unitary function LL_DMA_SetDataTransferDirection().

Definition at line 105 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstAddress

Specifies the memory base address for DMA transfer or as Destination base address in case of memory to memory transfer direction.

This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

Definition at line 100 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize

Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of Memory data alignment

This feature can be modified afterwards using unitary function LL_DMA_SetMemorySize().

Definition at line 136 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode

Specifies whether the Memory address or Destination address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of Memory increment mode

This feature can be modified afterwards using unitary function LL_DMA_SetMemoryIncMode().

Definition at line 124 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::Mode

Specifies the normal or circular operation mode. This parameter can be a value of Transfer mode

Note:
: The circular buffer mode cannot be used if the memory to memory data transfer direction is configured on the selected Channel

This feature can be modified afterwards using unitary function LL_DMA_SetMode().

Definition at line 111 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::NbData

Specifies the number of data to transfer, in data unit. The data unit is equal to the source buffer configuration set in PeripheralSize or MemorySize parameters depending in the transfer direction. This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF

This feature can be modified afterwards using unitary function LL_DMA_SetDataLength().

Definition at line 142 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress

Specifies the peripheral base address for DMA transfer or as Source base address in case of memory to memory transfer direction.

This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

Definition at line 95 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize

Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of Peripheral data alignment

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphSize().

Definition at line 130 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode

Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of Peripheral increment mode

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphIncMode().

Definition at line 118 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::Priority

Specifies the channel priority level. This parameter can be a value of Transfer Priority level

This feature can be modified afterwards using unitary function LL_DMA_SetChannelPriorityLevel().

Definition at line 149 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_dma.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
DMA Exported Constants

Flags defines which can be used with LL_DMA_WriteReg function. More...

Defines

#define | LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1
#define | LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1
#define | LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1
#define | LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1
#define | LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2
#define | LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2
#define | LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2
#define | LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2
#define | LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3
#define | LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3
#define | LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3
#define | LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3
#define | LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4
#define | LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4
#define | LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4
#define | LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4
#define | LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5
#define | LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5
#define | LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5
#define | LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5
#define | LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6
#define | LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6
#define | LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6
#define | LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6
#define | LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7
#define | LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7
#define | LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7
#define | LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7

Detailed Description

Flags defines which can be used with LL_DMA_WriteReg function.

Define Documentation

#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1

Channel 1 global flag

Definition at line 168 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2

Channel 2 global flag

Definition at line 172 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3

Channel 3 global flag

Definition at line 176 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4

Channel 4 global flag

Definition at line 180 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5

Channel 5 global flag

Definition at line 184 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6

Channel 6 global flag

Definition at line 188 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7

Channel 7 global flag

Definition at line 192 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1

Channel 1 half transfer flag

Definition at line 170 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2

Channel 2 half transfer flag

Definition at line 174 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3

Channel 3 half transfer flag

Definition at line 178 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4

Channel 4 half transfer flag

Definition at line 182 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5

Channel 5 half transfer flag

Definition at line 186 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6

Channel 6 half transfer flag

Definition at line 190 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7

Channel 7 half transfer flag

Definition at line 194 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1

Channel 1 transfer complete flag

Definition at line 169 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2

Channel 2 transfer complete flag

Definition at line 173 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3

Channel 3 transfer complete flag

Definition at line 177 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4

Channel 4 transfer complete flag

Definition at line 181 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5

Channel 5 transfer complete flag

Definition at line 185 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6

Channel 6 transfer complete flag

Definition at line 189 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7

Channel 7 transfer complete flag

Definition at line 193 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1

Channel 1 transfer error flag

Definition at line 171 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2

Channel 2 transfer error flag

Definition at line 175 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3

Channel 3 transfer error flag

Definition at line 179 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4

Channel 4 transfer error flag

Definition at line 183 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5

Channel 5 transfer error flag

Definition at line 187 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6

Channel 6 transfer error flag

Definition at line 191 of file stm32f3xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7

Channel 7 transfer error flag

Definition at line 195 of file stm32f3xx_ll_dma.h.

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STM32F373xC HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
DMA Exported Constants

Flags defines which can be used with LL_DMA_ReadReg function. More...

Defines

#define | LL_DMA_ISR_GIF1 DMA_ISR_GIF1
#define | LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1
#define | LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1
#define | LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1
#define | LL_DMA_ISR_GIF2 DMA_ISR_GIF2
#define | LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2
#define | LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2
#define | LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2
#define | LL_DMA_ISR_GIF3 DMA_ISR_GIF3
#define | LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3
#define | LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3
#define | LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3
#define | LL_DMA_ISR_GIF4 DMA_ISR_GIF4
#define | LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4
#define | LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4
#define | LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4
#define | LL_DMA_ISR_GIF5 DMA_ISR_GIF5
#define | LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5
#define | LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5
#define | LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5
#define | LL_DMA_ISR_GIF6 DMA_ISR_GIF6
#define | LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6
#define | LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6
#define | LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6
#define | LL_DMA_ISR_GIF7 DMA_ISR_GIF7
#define | LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7
#define | LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7
#define | LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7

Detailed Description

Flags defines which can be used with LL_DMA_ReadReg function.

Define Documentation

#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1

Channel 1 global flag

Definition at line 204 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2

Channel 2 global flag

Definition at line 208 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3

Channel 3 global flag

Definition at line 212 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4

Channel 4 global flag

Definition at line 216 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5

Channel 5 global flag

Definition at line 220 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6

Channel 6 global flag

Definition at line 224 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7

Channel 7 global flag

Definition at line 228 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1

Channel 1 half transfer flag

Definition at line 206 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2

Channel 2 half transfer flag

Definition at line 210 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3

Channel 3 half transfer flag

Definition at line 214 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4

Channel 4 half transfer flag

Definition at line 218 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5

Channel 5 half transfer flag

Definition at line 222 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6

Channel 6 half transfer flag

Definition at line 226 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7

Channel 7 half transfer flag

Definition at line 230 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1

Channel 1 transfer complete flag

Definition at line 205 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2

Channel 2 transfer complete flag

Definition at line 209 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3

Channel 3 transfer complete flag

Definition at line 213 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4

Channel 4 transfer complete flag

Definition at line 217 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5

Channel 5 transfer complete flag

Definition at line 221 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6

Channel 6 transfer complete flag

Definition at line 225 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7

Channel 7 transfer complete flag

Definition at line 229 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1

Channel 1 transfer error flag

Definition at line 207 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2

Channel 2 transfer error flag

Definition at line 211 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3

Channel 3 transfer error flag

Definition at line 215 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4

Channel 4 transfer error flag

Definition at line 219 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5

Channel 5 transfer error flag

Definition at line 223 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6

Channel 6 transfer error flag

Definition at line 227 of file stm32f3xx_ll_dma.h.

#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7

Channel 7 transfer error flag

Definition at line 231 of file stm32f3xx_ll_dma.h.

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STM32F373xC HAL User Manual: IT Defines

Defines
IT Defines
DMA Exported Constants

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions. More...

Defines

#define | LL_DMA_CCR_TCIE DMA_CCR_TCIE
#define | LL_DMA_CCR_HTIE DMA_CCR_HTIE
#define | LL_DMA_CCR_TEIE DMA_CCR_TEIE

Detailed Description

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions.

Define Documentation

#define LL_DMA_CCR_HTIE DMA_CCR_HTIE

Half Transfer interrupt

Definition at line 241 of file stm32f3xx_ll_dma.h.

#define LL_DMA_CCR_TCIE DMA_CCR_TCIE

Transfer complete interrupt

Definition at line 240 of file stm32f3xx_ll_dma.h.

#define LL_DMA_CCR_TEIE DMA_CCR_TEIE

Transfer error interrupt

Definition at line 242 of file stm32f3xx_ll_dma.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CHANNEL

Defines
CHANNEL
DMA Exported Constants

Defines

#define | LL_DMA_CHANNEL_1 0x00000001U
#define | LL_DMA_CHANNEL_2 0x00000002U
#define | LL_DMA_CHANNEL_3 0x00000003U
#define | LL_DMA_CHANNEL_4 0x00000004U
#define | LL_DMA_CHANNEL_5 0x00000005U
#define | LL_DMA_CHANNEL_6 0x00000006U
#define | LL_DMA_CHANNEL_7 0x00000007U
#define | LL_DMA_CHANNEL_ALL 0xFFFF0000U

Define Documentation

#define LL_DMA_CHANNEL_1 0x00000001U

DMA Channel 1

Definition at line 250 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_2 0x00000002U

DMA Channel 2

Definition at line 251 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_3 0x00000003U

DMA Channel 3

Definition at line 252 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_4 0x00000004U

DMA Channel 4

Definition at line 253 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_5 0x00000005U

DMA Channel 5

Definition at line 254 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_6 0x00000006U

DMA Channel 6

Definition at line 255 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_7 0x00000007U

DMA Channel 7

Definition at line 256 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_ALL 0xFFFF0000U

DMA Channel all (used only for function LL_DMA_DeInit().

Definition at line 258 of file stm32f3xx_ll_dma.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Transfer Direction

Defines
Transfer Direction
DMA Exported Constants

Defines

#define | LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
#define | LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR
#define | LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM

Define Documentation

#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM

Memory to memory direction

Definition at line 269 of file stm32f3xx_ll_dma.h.

#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR

Memory to peripheral direction

Definition at line 268 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_ConfigAddresses().

#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U

Peripheral to memory direction

Definition at line 267 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Transfer mode

Defines
Transfer mode
DMA Exported Constants

Defines

#define | LL_DMA_MODE_NORMAL 0x00000000U
#define | LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC

Define Documentation

#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC

Circular Mode

Definition at line 278 of file stm32f3xx_ll_dma.h.

#define LL_DMA_MODE_NORMAL 0x00000000U

Normal Mode

Definition at line 277 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral increment mode

Defines
Peripheral increment mode
DMA Exported Constants

Defines

#define | LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC
#define | LL_DMA_PERIPH_NOINCREMENT 0x00000000U

Define Documentation

#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC

Peripheral increment mode Enable

Definition at line 286 of file stm32f3xx_ll_dma.h.

#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U

Peripheral increment mode Disable

Definition at line 287 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Memory increment mode

Defines
Memory increment mode
DMA Exported Constants

Defines

#define | LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC
#define | LL_DMA_MEMORY_NOINCREMENT 0x00000000U

Define Documentation

#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC

Memory increment mode Enable

Definition at line 295 of file stm32f3xx_ll_dma.h.

#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U

Memory increment mode Disable

Definition at line 296 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral data alignment

Defines
Peripheral data alignment
DMA Exported Constants

Defines

#define | LL_DMA_PDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
#define | LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1

Define Documentation

#define LL_DMA_PDATAALIGN_BYTE 0x00000000U

Peripheral data alignment : Byte

Definition at line 304 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0

Peripheral data alignment : HalfWord

Definition at line 305 of file stm32f3xx_ll_dma.h.

#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1

Peripheral data alignment : Word

Definition at line 306 of file stm32f3xx_ll_dma.h.

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STM32F373xC HAL User Manual: Memory data alignment

Defines
Memory data alignment
DMA Exported Constants

Defines

#define | LL_DMA_MDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
#define | LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1

Define Documentation

#define LL_DMA_MDATAALIGN_BYTE 0x00000000U

Memory data alignment : Byte

Definition at line 314 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0

Memory data alignment : HalfWord

Definition at line 315 of file stm32f3xx_ll_dma.h.

#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1

Memory data alignment : Word

Definition at line 316 of file stm32f3xx_ll_dma.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Transfer Priority level

Defines
Transfer Priority level
DMA Exported Constants

Defines

#define | LL_DMA_PRIORITY_LOW 0x00000000U
#define | LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0
#define | LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1
#define | LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL

Define Documentation

#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1

Priority level : High

Definition at line 326 of file stm32f3xx_ll_dma.h.

#define LL_DMA_PRIORITY_LOW 0x00000000U

Priority level : Low

Definition at line 324 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0

Priority level : Medium

Definition at line 325 of file stm32f3xx_ll_dma.h.

#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL

Priority level : Very_High

Definition at line 327 of file stm32f3xx_ll_dma.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
DMA Exported Macros

Defines

#define | LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMA register.
#define | LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMA register.

Define Documentation

#define LL_DMA_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in DMA register.

Parameters:
__INSTANCE__ | DMA Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 360 of file stm32f3xx_ll_dma.h.

#define LL_DMA_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in DMA register.

Parameters:
__INSTANCE__ | DMA Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 352 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Convert DMAxChannely

Defines
Convert DMAxChannely
DMA Exported Macros

Defines

#define | __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
Convert DMAx_Channely into DMAx.
#define | __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)
Convert DMAx_Channely into LL_DMA_CHANNEL_y.
#define | __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)
Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Define Documentation

#define __LL_DMA_GET_CHANNEL ( __CHANNEL_INSTANCE__ )
Value:
(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
 LL_DMA_CHANNEL_7)

Convert DMAx_Channely into LL_DMA_CHANNEL_y.

Parameters:
__CHANNEL_INSTANCE__ DMAx_Channely
Return values:
LL_DMA_CHANNEL_y

Definition at line 402 of file stm32f3xx_ll_dma.h.

#define __LL_DMA_GET_CHANNEL_INSTANCE | ( | __DMA_INSTANCE__,
 |  | __CHANNEL__
 | ) |
Value:
((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
 DMA1_Channel7)

Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Parameters:
__DMA_INSTANCE__ | DMAx
__CHANNEL__ | LL_DMA_CHANNEL_y
Return values:
DMAx_Channely

Definition at line 451 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define __LL_DMA_GET_INSTANCE ( __CHANNEL_INSTANCE__ ) (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)

Convert DMAx_Channely into DMAx.

Parameters:
__CHANNEL_INSTANCE__ DMAx_Channely
Return values:
DMAx

Definition at line 374 of file stm32f3xx_ll_dma.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration

Functions
Configuration
DMA Exported Functions

Functions

__STATIC_INLINE void | LL_DMA_EnableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Enable DMA channel.
__STATIC_INLINE void | LL_DMA_DisableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Disable DMA channel.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Check if DMA channel is enabled or disabled.
__STATIC_INLINE void | LL_DMA_ConfigTransfer (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
Configure all parameters link to DMA transfer.
__STATIC_INLINE void | LL_DMA_SetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
Set Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE uint32_t | LL_DMA_GetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel)
Get Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE void | LL_DMA_SetMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
Set DMA mode circular or normal.
__STATIC_INLINE uint32_t | LL_DMA_GetMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA mode circular or normal.
__STATIC_INLINE void | LL_DMA_SetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
Set Peripheral increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral increment mode.
__STATIC_INLINE void | LL_DMA_SetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
Set Memory increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory increment mode.
__STATIC_INLINE void | LL_DMA_SetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
Set Peripheral size.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral size.
__STATIC_INLINE void | LL_DMA_SetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
Set Memory size.
__STATIC_INLINE uint32_t | LL_DMA_GetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory size.
__STATIC_INLINE void | LL_DMA_SetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
Set Channel priority level.
__STATIC_INLINE uint32_t | LL_DMA_GetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel)
Get Channel priority level.
__STATIC_INLINE void | LL_DMA_SetDataLength (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
Set Number of data to transfer.
__STATIC_INLINE uint32_t | LL_DMA_GetDataLength (DMA_TypeDef *DMAx, uint32_t Channel)
Get Number of data to transfer.
__STATIC_INLINE void | LL_DMA_ConfigAddresses (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_DMA_SetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory address.
__STATIC_INLINE void | LL_DMA_SetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
Set the Peripheral address.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory address.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral address.
__STATIC_INLINE void | LL_DMA_SetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Source address.
__STATIC_INLINE void | LL_DMA_SetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Source address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Destination address.

Function Documentation

__STATIC_INLINE void LL_DMA_ConfigAddresses | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Direction
 | ) |  |

Configure the Source and Destination addresses.

Note:
This API must not be called when the DMA channel is enabled.
Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_ConfigAddresses
CMAR MA LL_DMA_ConfigAddresses
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
SrcAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
DstAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Direction This parameter can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Return values:
None

Definition at line 983 of file stm32f3xx_ll_dma.h.

References LL_DMA_DIRECTION_MEMORY_TO_PERIPH.

__STATIC_INLINE void LL_DMA_ConfigTransfer | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure all parameters link to DMA transfer.

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_ConfigTransfer
CCR MEM2MEM LL_DMA_ConfigTransfer
CCR CIRC LL_DMA_ConfigTransfer
CCR PINC LL_DMA_ConfigTransfer
CCR MINC LL_DMA_ConfigTransfer
CCR PSIZE LL_DMA_ConfigTransfer
CCR MSIZE LL_DMA_ConfigTransfer
CCR PL LL_DMA_ConfigTransfer
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Configuration This parameter must be a combination of all the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH or LL_DMA_DIRECTION_MEMORY_TO_MEMORY
  • LL_DMA_MODE_NORMAL or LL_DMA_MODE_CIRCULAR
  • LL_DMA_PERIPH_INCREMENT or LL_DMA_PERIPH_NOINCREMENT
  • LL_DMA_MEMORY_INCREMENT or LL_DMA_MEMORY_NOINCREMENT
  • LL_DMA_PDATAALIGN_BYTE or LL_DMA_PDATAALIGN_HALFWORD or LL_DMA_PDATAALIGN_WORD
  • LL_DMA_MDATAALIGN_BYTE or LL_DMA_MDATAALIGN_HALFWORD or LL_DMA_MDATAALIGN_WORD
  • LL_DMA_PRIORITY_LOW or LL_DMA_PRIORITY_MEDIUM or LL_DMA_PRIORITY_HIGH or LL_DMA_PRIORITY_VERYHIGH
Return values:
None

Definition at line 579 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_DisableChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable DMA channel.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_DisableChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 525 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable DMA channel.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_EnableChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 506 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Channel priority level.

Reference Manual to LL API cross reference:
CCR PL LL_DMA_GetChannelPriorityLevel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PRIORITY_LOW
  • LL_DMA_PRIORITY_MEDIUM
  • LL_DMA_PRIORITY_HIGH
  • LL_DMA_PRIORITY_VERYHIGH

Definition at line 909 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetDataLength | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Number of data to transfer.

Note:
Once the channel is enabled, the return value indicate the remaining bytes to be transmitted.
Reference Manual to LL API cross reference:
CNDTR NDT LL_DMA_GetDataLength
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 954 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Data transfer direction (read from peripheral or from memory).

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_GetDataTransferDirection
CCR MEM2MEM LL_DMA_GetDataTransferDirection
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY

Definition at line 629 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get the Memory to Memory Destination address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_GetM2MDstAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1163 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get the Memory to Memory Source address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_GetM2MSrcAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1143 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_GetMemoryAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1059 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory increment mode.

Reference Manual to LL API cross reference:
CCR MINC LL_DMA_GetMemoryIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MEMORY_INCREMENT
  • LL_DMA_MEMORY_NOINCREMENT

Definition at line 766 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemorySize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory size.

Reference Manual to LL API cross reference:
CCR MSIZE LL_DMA_GetMemorySize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MDATAALIGN_BYTE
  • LL_DMA_MDATAALIGN_HALFWORD
  • LL_DMA_MDATAALIGN_WORD

Definition at line 860 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get DMA mode circular or normal.

Reference Manual to LL API cross reference:
CCR CIRC LL_DMA_GetMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MODE_NORMAL
  • LL_DMA_MODE_CIRCULAR

Definition at line 676 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_GetPeriphAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1079 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral increment mode.

Reference Manual to LL API cross reference:
CCR PINC LL_DMA_GetPeriphIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PERIPH_INCREMENT
  • LL_DMA_PERIPH_NOINCREMENT

Definition at line 721 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral size.

Reference Manual to LL API cross reference:
CCR PSIZE LL_DMA_GetPeriphSize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PDATAALIGN_BYTE
  • LL_DMA_PDATAALIGN_HALFWORD
  • LL_DMA_PDATAALIGN_WORD

Definition at line 813 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if DMA channel is enabled or disabled.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_IsEnabledChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 544 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Priority
 | ) |  |

Set Channel priority level.

Reference Manual to LL API cross reference:
CCR PL LL_DMA_SetChannelPriorityLevel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Priority This parameter can be one of the following values:
  • LL_DMA_PRIORITY_LOW
  • LL_DMA_PRIORITY_MEDIUM
  • LL_DMA_PRIORITY_HIGH
  • LL_DMA_PRIORITY_VERYHIGH
Return values:
None

Definition at line 885 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetDataLength | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | NbData
 | ) |  |

Set Number of data to transfer.

Note:
This action has no effect if channel is enabled.
Reference Manual to LL API cross reference:
CNDTR NDT LL_DMA_SetDataLength
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
NbData | Between Min_Data = 0 and Max_Data = 0x0000FFFF
Return values:
None

Definition at line 932 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetDataTransferDirection | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Direction
 | ) |  |

Set Data transfer direction (read from peripheral or from memory).

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_SetDataTransferDirection
CCR MEM2MEM LL_DMA_SetDataTransferDirection
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Direction This parameter can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Return values:
None

Definition at line 605 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetM2MDstAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory to Memory Destination address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_SetM2MDstAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1123 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetM2MSrcAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory to Memory Source address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_SetM2MSrcAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1101 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMemoryAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_SetMemoryAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1017 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetMemoryIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryOrM2MDstIncMode
 | ) |  |

Set Memory increment mode.

Reference Manual to LL API cross reference:
CCR MINC LL_DMA_SetMemoryIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryOrM2MDstIncMode This parameter can be one of the following values:
  • LL_DMA_MEMORY_INCREMENT
  • LL_DMA_MEMORY_NOINCREMENT
Return values:
None

Definition at line 744 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMemorySize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryOrM2MDstDataSize
 | ) |  |

Set Memory size.

Reference Manual to LL API cross reference:
CCR MSIZE LL_DMA_SetMemorySize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryOrM2MDstDataSize This parameter can be one of the following values:
  • LL_DMA_MDATAALIGN_BYTE
  • LL_DMA_MDATAALIGN_HALFWORD
  • LL_DMA_MDATAALIGN_WORD
Return values:
None

Definition at line 837 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Mode
 | ) |  |

Set DMA mode circular or normal.

Note:
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel.
Reference Manual to LL API cross reference:
CCR CIRC LL_DMA_SetMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Mode This parameter can be one of the following values:
  • LL_DMA_MODE_NORMAL
  • LL_DMA_MODE_CIRCULAR
Return values:
None

Definition at line 654 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetPeriphAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphAddress
 | ) |  |

Set the Peripheral address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_SetPeriphAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
PeriphAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1039 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetPeriphIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphOrM2MSrcIncMode
 | ) |  |

Set Peripheral increment mode.

Reference Manual to LL API cross reference:
CCR PINC LL_DMA_SetPeriphIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
PeriphOrM2MSrcIncMode This parameter can be one of the following values:
  • LL_DMA_PERIPH_INCREMENT
  • LL_DMA_PERIPH_NOINCREMENT
Return values:
None

Definition at line 699 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetPeriphSize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphOrM2MSrcDataSize
 | ) |  |

Set Peripheral size.

Reference Manual to LL API cross reference:
CCR PSIZE LL_DMA_SetPeriphSize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
PeriphOrM2MSrcDataSize This parameter can be one of the following values:
  • LL_DMA_PDATAALIGN_BYTE
  • LL_DMA_PDATAALIGN_HALFWORD
  • LL_DMA_PDATAALIGN_WORD
Return values:
None

Definition at line 790 of file stm32f3xx_ll_dma.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLAG_Management

Functions
FLAG_Management
DMA Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI1 (DMA_TypeDef *DMAx)
Get Channel 1 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI2 (DMA_TypeDef *DMAx)
Get Channel 2 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI3 (DMA_TypeDef *DMAx)
Get Channel 3 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI4 (DMA_TypeDef *DMAx)
Get Channel 4 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI5 (DMA_TypeDef *DMAx)
Get Channel 5 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI6 (DMA_TypeDef *DMAx)
Get Channel 6 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI7 (DMA_TypeDef *DMAx)
Get Channel 7 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT1 (DMA_TypeDef *DMAx)
Get Channel 1 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT2 (DMA_TypeDef *DMAx)
Get Channel 2 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT3 (DMA_TypeDef *DMAx)
Get Channel 3 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT4 (DMA_TypeDef *DMAx)
Get Channel 4 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT5 (DMA_TypeDef *DMAx)
Get Channel 5 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT6 (DMA_TypeDef *DMAx)
Get Channel 6 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT7 (DMA_TypeDef *DMAx)
Get Channel 7 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI1 (DMA_TypeDef *DMAx)
Clear Channel 1 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI2 (DMA_TypeDef *DMAx)
Clear Channel 2 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI3 (DMA_TypeDef *DMAx)
Clear Channel 3 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI4 (DMA_TypeDef *DMAx)
Clear Channel 4 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI5 (DMA_TypeDef *DMAx)
Clear Channel 5 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI6 (DMA_TypeDef *DMAx)
Clear Channel 6 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI7 (DMA_TypeDef *DMAx)
Clear Channel 7 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT1 (DMA_TypeDef *DMAx)
Clear Channel 1 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT2 (DMA_TypeDef *DMAx)
Clear Channel 2 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT3 (DMA_TypeDef *DMAx)
Clear Channel 3 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT4 (DMA_TypeDef *DMAx)
Clear Channel 4 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT5 (DMA_TypeDef *DMAx)
Clear Channel 5 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT6 (DMA_TypeDef *DMAx)
Clear Channel 6 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT7 (DMA_TypeDef *DMAx)
Clear Channel 7 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer error flag.

Function Documentation

__STATIC_INLINE void LL_DMA_ClearFlag_GI1 ( DMA_TypeDef * DMAx )

Clear Channel 1 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF1 LL_DMA_ClearFlag_GI1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1491 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI2 ( DMA_TypeDef * DMAx )

Clear Channel 2 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF2 LL_DMA_ClearFlag_GI2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1502 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI3 ( DMA_TypeDef * DMAx )

Clear Channel 3 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF3 LL_DMA_ClearFlag_GI3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1513 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI4 ( DMA_TypeDef * DMAx )

Clear Channel 4 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF4 LL_DMA_ClearFlag_GI4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1524 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI5 ( DMA_TypeDef * DMAx )

Clear Channel 5 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF5 LL_DMA_ClearFlag_GI5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1535 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI6 ( DMA_TypeDef * DMAx )

Clear Channel 6 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF6 LL_DMA_ClearFlag_GI6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1546 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI7 ( DMA_TypeDef * DMAx )

Clear Channel 7 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF7 LL_DMA_ClearFlag_GI7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1557 of file stm32f3xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_HT1 ( DMA_TypeDef * DMAx )

Clear Channel 1 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF1 LL_DMA_ClearFlag_HT1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1645 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT2 ( DMA_TypeDef * DMAx )

Clear Channel 2 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF2 LL_DMA_ClearFlag_HT2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1656 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT3 ( DMA_TypeDef * DMAx )

Clear Channel 3 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF3 LL_DMA_ClearFlag_HT3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1667 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT4 ( DMA_TypeDef * DMAx )

Clear Channel 4 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF4 LL_DMA_ClearFlag_HT4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1678 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT5 ( DMA_TypeDef * DMAx )

Clear Channel 5 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF5 LL_DMA_ClearFlag_HT5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1689 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT6 ( DMA_TypeDef * DMAx )

Clear Channel 6 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF6 LL_DMA_ClearFlag_HT6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1700 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT7 ( DMA_TypeDef * DMAx )

Clear Channel 7 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF7 LL_DMA_ClearFlag_HT7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1711 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC1 ( DMA_TypeDef * DMAx )

Clear Channel 1 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF1 LL_DMA_ClearFlag_TC1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1568 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC2 ( DMA_TypeDef * DMAx )

Clear Channel 2 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF2 LL_DMA_ClearFlag_TC2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1579 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC3 ( DMA_TypeDef * DMAx )

Clear Channel 3 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF3 LL_DMA_ClearFlag_TC3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1590 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC4 ( DMA_TypeDef * DMAx )

Clear Channel 4 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF4 LL_DMA_ClearFlag_TC4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1601 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC5 ( DMA_TypeDef * DMAx )

Clear Channel 5 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF5 LL_DMA_ClearFlag_TC5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1612 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC6 ( DMA_TypeDef * DMAx )

Clear Channel 6 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF6 LL_DMA_ClearFlag_TC6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1623 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC7 ( DMA_TypeDef * DMAx )

Clear Channel 7 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF7 LL_DMA_ClearFlag_TC7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1634 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE1 ( DMA_TypeDef * DMAx )

Clear Channel 1 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF1 LL_DMA_ClearFlag_TE1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1722 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE2 ( DMA_TypeDef * DMAx )

Clear Channel 2 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF2 LL_DMA_ClearFlag_TE2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1733 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE3 ( DMA_TypeDef * DMAx )

Clear Channel 3 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF3 LL_DMA_ClearFlag_TE3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1744 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE4 ( DMA_TypeDef * DMAx )

Clear Channel 4 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF4 LL_DMA_ClearFlag_TE4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1755 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE5 ( DMA_TypeDef * DMAx )

Clear Channel 5 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF5 LL_DMA_ClearFlag_TE5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1766 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE6 ( DMA_TypeDef * DMAx )

Clear Channel 6 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF6 LL_DMA_ClearFlag_TE6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1777 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE7 ( DMA_TypeDef * DMAx )

Clear Channel 7 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF7 LL_DMA_ClearFlag_TE7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1788 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1 ( DMA_TypeDef * DMAx )

Get Channel 1 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF1 LL_DMA_IsActiveFlag_GI1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1183 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2 ( DMA_TypeDef * DMAx )

Get Channel 2 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF2 LL_DMA_IsActiveFlag_GI2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1194 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3 ( DMA_TypeDef * DMAx )

Get Channel 3 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF3 LL_DMA_IsActiveFlag_GI3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1205 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4 ( DMA_TypeDef * DMAx )

Get Channel 4 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF4 LL_DMA_IsActiveFlag_GI4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1216 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5 ( DMA_TypeDef * DMAx )

Get Channel 5 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF5 LL_DMA_IsActiveFlag_GI5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1227 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6 ( DMA_TypeDef * DMAx )

Get Channel 6 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF6 LL_DMA_IsActiveFlag_GI6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1238 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7 ( DMA_TypeDef * DMAx )

Get Channel 7 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF7 LL_DMA_IsActiveFlag_GI7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1249 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1 ( DMA_TypeDef * DMAx )

Get Channel 1 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF1 LL_DMA_IsActiveFlag_HT1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1337 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2 ( DMA_TypeDef * DMAx )

Get Channel 2 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF2 LL_DMA_IsActiveFlag_HT2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1348 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3 ( DMA_TypeDef * DMAx )

Get Channel 3 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF3 LL_DMA_IsActiveFlag_HT3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1359 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4 ( DMA_TypeDef * DMAx )

Get Channel 4 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF4 LL_DMA_IsActiveFlag_HT4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1370 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5 ( DMA_TypeDef * DMAx )

Get Channel 5 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF5 LL_DMA_IsActiveFlag_HT5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1381 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6 ( DMA_TypeDef * DMAx )

Get Channel 6 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF6 LL_DMA_IsActiveFlag_HT6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1392 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7 ( DMA_TypeDef * DMAx )

Get Channel 7 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF7 LL_DMA_IsActiveFlag_HT7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1403 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1 ( DMA_TypeDef * DMAx )

Get Channel 1 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF1 LL_DMA_IsActiveFlag_TC1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1260 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2 ( DMA_TypeDef * DMAx )

Get Channel 2 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF2 LL_DMA_IsActiveFlag_TC2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1271 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3 ( DMA_TypeDef * DMAx )

Get Channel 3 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF3 LL_DMA_IsActiveFlag_TC3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1282 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4 ( DMA_TypeDef * DMAx )

Get Channel 4 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF4 LL_DMA_IsActiveFlag_TC4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1293 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5 ( DMA_TypeDef * DMAx )

Get Channel 5 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF5 LL_DMA_IsActiveFlag_TC5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1304 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6 ( DMA_TypeDef * DMAx )

Get Channel 6 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF6 LL_DMA_IsActiveFlag_TC6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1315 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7 ( DMA_TypeDef * DMAx )

Get Channel 7 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF7 LL_DMA_IsActiveFlag_TC7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1326 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1 ( DMA_TypeDef * DMAx )

Get Channel 1 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF1 LL_DMA_IsActiveFlag_TE1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1414 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2 ( DMA_TypeDef * DMAx )

Get Channel 2 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF2 LL_DMA_IsActiveFlag_TE2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1425 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3 ( DMA_TypeDef * DMAx )

Get Channel 3 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF3 LL_DMA_IsActiveFlag_TE3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1436 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4 ( DMA_TypeDef * DMAx )

Get Channel 4 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF4 LL_DMA_IsActiveFlag_TE4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1447 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5 ( DMA_TypeDef * DMAx )

Get Channel 5 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF5 LL_DMA_IsActiveFlag_TE5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1458 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6 ( DMA_TypeDef * DMAx )

Get Channel 6 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF6 LL_DMA_IsActiveFlag_TE6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1469 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7 ( DMA_TypeDef * DMAx )

Get Channel 7 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF7 LL_DMA_IsActiveFlag_TE7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1480 of file stm32f3xx_ll_dma.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IT_Management

Functions
IT_Management
DMA Exported Functions

Functions

__STATIC_INLINE void | LL_DMA_EnableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer error interrupt.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer complete Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Half transfer Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer error Interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_DMA_DisableIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Half transfer interrupt.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_DisableIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1890 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_DisableIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Transfer complete interrupt.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_DisableIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1871 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_DisableIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Transfer error interrupt.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_DisableIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1909 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Half transfer interrupt.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_EnableIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1833 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Transfer complete interrupt.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_EnableIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1814 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Transfer error interrupt.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_EnableIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1852 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Half transfer Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_IsEnabledIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 1948 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Transfer complete Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_IsEnabledIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 1928 of file stm32f3xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Transfer error Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_IsEnabledIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 1968 of file stm32f3xx_ll_dma.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA Exported Functions

Functions

uint32_t | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
uint32_t | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Function Documentation

uint32_t LL_DMA_DeInit | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

De-initialize the DMA registers to their default reset values.

Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA registers are de-initialized
  • ERROR: DMA registers are not de-initialized

Definition at line 166 of file stm32f3xx_ll_dma.c.

References __LL_DMA_GET_CHANNEL_INSTANCE, assert_param, IS_LL_DMA_ALL_CHANNEL_INSTANCE, LL_DMA_CHANNEL_1, LL_DMA_CHANNEL_2, LL_DMA_CHANNEL_3, LL_DMA_CHANNEL_4, LL_DMA_CHANNEL_5, LL_DMA_CHANNEL_6, LL_DMA_CHANNEL_7, LL_DMA_ClearFlag_GI1(), LL_DMA_ClearFlag_GI2(), LL_DMA_ClearFlag_GI3(), LL_DMA_ClearFlag_GI4(), LL_DMA_ClearFlag_GI5(), LL_DMA_ClearFlag_GI6(), LL_DMA_ClearFlag_GI7(), and LL_DMA_WriteReg.

uint32_t LL_DMA_Init | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | LL_DMA_InitTypeDef * | DMA_InitStruct
 | ) |  |

Initialize the DMA registers according to the specified parameters in DMA_InitStruct.

Note:
To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
  • __LL_DMA_GET_INSTANCE
  • __LL_DMA_GET_CHANNEL
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
DMA_InitStruct | pointer to a LL_DMA_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA registers are initialized
  • ERROR: Not applicable

Definition at line 255 of file stm32f3xx_ll_dma.c.

References assert_param, LL_DMA_InitTypeDef::Direction, IS_LL_DMA_ALL_CHANNEL_INSTANCE, IS_LL_DMA_DIRECTION, IS_LL_DMA_MEMORYDATASIZE, IS_LL_DMA_MEMORYINCMODE, IS_LL_DMA_MODE, IS_LL_DMA_NBDATA, IS_LL_DMA_PERIPHDATASIZE, IS_LL_DMA_PERIPHINCMODE, IS_LL_DMA_PRIORITY, LL_DMA_ConfigTransfer(), LL_DMA_SetDataLength(), LL_DMA_SetMemoryAddress(), LL_DMA_SetPeriphAddress(), LL_DMA_InitTypeDef::MemoryOrM2MDstAddress, LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize, LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode, LL_DMA_InitTypeDef::Mode, LL_DMA_InitTypeDef::NbData, LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress, LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize, LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode, and LL_DMA_InitTypeDef::Priority.

void LL_DMA_StructInit ( LL_DMA_InitTypeDef * DMA_InitStruct )

Set each LL_DMA_InitTypeDef field to default value.

Parameters:
DMA_InitStruct Pointer to a LL_DMA_InitTypeDef structure.
Return values:
None

Definition at line 317 of file stm32f3xx_ll_dma.c.

References LL_DMA_InitTypeDef::Direction, LL_DMA_DIRECTION_PERIPH_TO_MEMORY, LL_DMA_MDATAALIGN_BYTE, LL_DMA_MEMORY_NOINCREMENT, LL_DMA_MODE_NORMAL, LL_DMA_PDATAALIGN_BYTE, LL_DMA_PERIPH_NOINCREMENT, LL_DMA_PRIORITY_LOW, LL_DMA_InitTypeDef::MemoryOrM2MDstAddress, LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize, LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode, LL_DMA_InitTypeDef::Mode, LL_DMA_InitTypeDef::NbData, LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress, LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize, LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode, and LL_DMA_InitTypeDef::Priority.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: EXTI

Modules
EXTI
STM32F3xx_LL_Driver

Modules

EXTI Private Macros
EXTI Exported Init structure
EXTI Exported Constants
EXTI Exported Macros
EXTI Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for EXTI registers.

Register | Bit | Function
EMR | EMx | LL_EXTI_DisableEvent_0_31
 |  | LL_EXTI_EnableEvent_0_31
 |  | LL_EXTI_IsEnabledEvent_0_31
FTSR | FTx | LL_EXTI_DisableFallingTrig_0_31
 |  | LL_EXTI_EnableFallingTrig_0_31
 |  | LL_EXTI_IsEnabledFallingTrig_0_31
IMR | IMx | LL_EXTI_DisableIT_0_31
 |  | LL_EXTI_EnableIT_0_31
 |  | LL_EXTI_IsEnabledIT_0_31
PR | PIFx | LL_EXTI_ClearFlag_0_31
 |  | LL_EXTI_IsActiveFlag_0_31
 |  | LL_EXTI_ReadFlag_0_31
RTSR | RTx | LL_EXTI_DisableRisingTrig_0_31
 |  | LL_EXTI_EnableRisingTrig_0_31
 |  | LL_EXTI_IsEnabledRisingTrig_0_31
SWIER | SWIx | LL_EXTI_GenerateSWI_0_31
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: EXTI Private Macros

Defines
EXTI Private Macros
EXTI

Defines

#define | IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define | IS_LL_EXTI_MODE(__VALUE__)
#define | IS_LL_EXTI_TRIGGER(__VALUE__)

Define Documentation

#define IS_LL_EXTI_LINE_0_31 ( __VALUE__ ) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)

Definition at line 63 of file stm32f3xx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_EXTI_MODE_IT)            \
                                                   || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
                                                   || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))

Definition at line 68 of file stm32f3xx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_TRIGGER ( __VALUE__ )
Value:
(((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))

Definition at line 73 of file stm32f3xx_ll_exti.c.

Referenced by LL_EXTI_Init().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_EXTI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_EXTI_InitTypeDef Struct Reference
EXTI Exported Init structure

#include <stm32f3xx_ll_exti.h>

Data Fields

uint32_t | Line_0_31
FunctionalState | LineCommand
uint8_t | Mode
uint8_t | Trigger

Detailed Description

Definition at line 74 of file stm32f3xx_ll_exti.h.

Field Documentation

uint32_t LL_EXTI_InitTypeDef::Line_0_31

Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 This parameter can be any combination of LINE

Definition at line 77 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

FunctionalState LL_EXTI_InitTypeDef::LineCommand

Specifies the new state of the selected EXTI lines. This parameter can be set either to ENABLE or DISABLE

Definition at line 85 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint8_t LL_EXTI_InitTypeDef::Mode

Specifies the mode for the EXTI lines. This parameter can be a value of Mode.

Definition at line 88 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint8_t LL_EXTI_InitTypeDef::Trigger

Specifies the trigger signal active edge for the EXTI lines. This parameter can be a value of Edge Trigger.

Definition at line 91 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_exti.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LINE

Defines
LINE
EXTI Exported Constants

Defines

#define | LL_EXTI_LINE_0 EXTI_IMR_IM0
#define | LL_EXTI_LINE_1 EXTI_IMR_IM1
#define | LL_EXTI_LINE_2 EXTI_IMR_IM2
#define | LL_EXTI_LINE_3 EXTI_IMR_IM3
#define | LL_EXTI_LINE_4 EXTI_IMR_IM4
#define | LL_EXTI_LINE_5 EXTI_IMR_IM5
#define | LL_EXTI_LINE_6 EXTI_IMR_IM6
#define | LL_EXTI_LINE_7 EXTI_IMR_IM7
#define | LL_EXTI_LINE_8 EXTI_IMR_IM8
#define | LL_EXTI_LINE_9 EXTI_IMR_IM9
#define | LL_EXTI_LINE_10 EXTI_IMR_IM10
#define | LL_EXTI_LINE_11 EXTI_IMR_IM11
#define | LL_EXTI_LINE_12 EXTI_IMR_IM12
#define | LL_EXTI_LINE_13 EXTI_IMR_IM13
#define | LL_EXTI_LINE_14 EXTI_IMR_IM14
#define | LL_EXTI_LINE_15 EXTI_IMR_IM15
#define | LL_EXTI_LINE_16 EXTI_IMR_IM16
#define | LL_EXTI_LINE_17 EXTI_IMR_IM17
#define | LL_EXTI_LINE_18 EXTI_IMR_IM18
#define | LL_EXTI_LINE_19 EXTI_IMR_IM19
#define | LL_EXTI_LINE_20 EXTI_IMR_IM20
#define | LL_EXTI_LINE_21 EXTI_IMR_IM21
#define | LL_EXTI_LINE_22 EXTI_IMR_IM22
#define | LL_EXTI_LINE_23 EXTI_IMR_IM23
#define | LL_EXTI_LINE_24 EXTI_IMR_IM24
#define | LL_EXTI_LINE_25 EXTI_IMR_IM25
#define | LL_EXTI_LINE_26 EXTI_IMR_IM26
#define | LL_EXTI_LINE_27 EXTI_IMR_IM27
#define | LL_EXTI_LINE_28 EXTI_IMR_IM28
#define | LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM
#define | LL_EXTI_LINE_ALL (0xFFFFFFFFU)
#define | LL_EXTI_LINE_NONE (0x00000000U)

Define Documentation

#define LL_EXTI_LINE_0 EXTI_IMR_IM0

Extended line 0

Definition at line 108 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_1 EXTI_IMR_IM1

Extended line 1

Definition at line 109 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_10 EXTI_IMR_IM10

Extended line 10

Definition at line 118 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_11 EXTI_IMR_IM11

Extended line 11

Definition at line 119 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_12 EXTI_IMR_IM12

Extended line 12

Definition at line 120 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_13 EXTI_IMR_IM13

Extended line 13

Definition at line 121 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_14 EXTI_IMR_IM14

Extended line 14

Definition at line 122 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_15 EXTI_IMR_IM15

Extended line 15

Definition at line 123 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_16 EXTI_IMR_IM16

Extended line 16

Definition at line 125 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_17 EXTI_IMR_IM17

Extended line 17

Definition at line 127 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_18 EXTI_IMR_IM18

Extended line 18

Definition at line 129 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_19 EXTI_IMR_IM19

Extended line 19

Definition at line 131 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_2 EXTI_IMR_IM2

Extended line 2

Definition at line 110 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_20 EXTI_IMR_IM20

Extended line 20

Definition at line 133 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_21 EXTI_IMR_IM21

Extended line 21

Definition at line 136 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_22 EXTI_IMR_IM22

Extended line 22

Definition at line 139 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_23 EXTI_IMR_IM23

Extended line 23

Definition at line 141 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_24 EXTI_IMR_IM24

Extended line 24

Definition at line 143 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_25 EXTI_IMR_IM25

Extended line 25

Definition at line 146 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_26 EXTI_IMR_IM26

Extended line 26

Definition at line 149 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_27 EXTI_IMR_IM27

Extended line 27

Definition at line 152 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_28 EXTI_IMR_IM28

Extended line 28

Definition at line 155 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_3 EXTI_IMR_IM3

Extended line 3

Definition at line 111 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_4 EXTI_IMR_IM4

Extended line 4

Definition at line 112 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_5 EXTI_IMR_IM5

Extended line 5

Definition at line 113 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_6 EXTI_IMR_IM6

Extended line 6

Definition at line 114 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_7 EXTI_IMR_IM7

Extended line 7

Definition at line 115 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_8 EXTI_IMR_IM8

Extended line 8

Definition at line 116 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_9 EXTI_IMR_IM9

Extended line 9

Definition at line 117 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_ALL (0xFFFFFFFFU)

All Extended line

Definition at line 198 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM

All Extended line not reserved

Definition at line 166 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_LINE_NONE (0x00000000U)

None Extended line

Definition at line 201 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Mode

Defines
Mode
EXTI Exported Constants

Defines

#define | LL_EXTI_MODE_IT ((uint8_t)0x00U)
#define | LL_EXTI_MODE_EVENT ((uint8_t)0x01U)
#define | LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)

Define Documentation

#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U)

Event Mode

Definition at line 213 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_MODE_IT ((uint8_t)0x00U)

Interrupt Mode

Definition at line 212 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)

Interrupt & Event Mode

Definition at line 214 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Edge Trigger

Defines
Edge Trigger
EXTI Exported Constants

Defines

#define | LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)
#define | LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)
#define | LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)

Define Documentation

#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)

Trigger Falling Mode

Definition at line 224 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)

No Trigger Mode

Definition at line 222 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)

Trigger Rising Mode

Definition at line 223 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)

Trigger Rising & Falling Mode

Definition at line 225 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
EXTI Exported Macros

Defines

#define | LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
Write a value in EXTI register.
#define | LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
Read a value in EXTI register.

Define Documentation

#define LL_EXTI_ReadReg ( __REG__ ) READ_REG(EXTI->__REG__)

Read a value in EXTI register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 261 of file stm32f3xx_ll_exti.h.

#define LL_EXTI_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(EXTI->__REG__, (__VALUE__))

Write a value in EXTI register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 254 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_DeInit().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IT_Management

Functions
IT_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableIT_0_31 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableIT_0_31 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableIT_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Interrupt request for Lines in range 0 to 31.

Note:
The reset value for the direct or internal lines (see RM) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR IMx LL_EXTI_DisableIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 396 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableIT_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Interrupt request for Lines in range 0 to 31.

Note:
The reset value for the direct or internal lines (see RM) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR IMx LL_EXTI_EnableIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 324 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31 ( uint32_t ExtiLine )

Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.

Note:
The reset value for the direct or internal lines (see RM) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR IMx LL_EXTI_IsEnabledIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 469 of file stm32f3xx_ll_exti.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Event_Management

Functions
Event_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableEvent_0_31 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableEvent_0_31 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableEvent_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Event request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR EMx LL_EXTI_DisableEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 615 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableEvent_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Event request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR EMx LL_EXTI_EnableEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 547 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31 ( uint32_t ExtiLine )

Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR EMx LL_EXTI_IsEnabledEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 682 of file stm32f3xx_ll_exti.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Rising_Trigger_Management

Functions
Rising_Trigger_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_0_31 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 0 to 31.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR RTx LL_EXTI_DisableRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 825 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR RTx LL_EXTI_EnableRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 757 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31 ( uint32_t ExtiLine )

Check if rising edge trigger is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 887 of file stm32f3xx_ll_exti.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Falling_Trigger_Management

Functions
Falling_Trigger_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_0_31 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 0 to 31.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR FTx LL_EXTI_DisableFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 1023 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR FTx LL_EXTI_EnableFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 956 of file stm32f3xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31 ( uint32_t ExtiLine )

Check if falling edge trigger is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 1083 of file stm32f3xx_ll_exti.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Software_Interrupt_Management

Functions
Software_Interrupt_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 0 to 31.

Function Documentation

__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31 ( uint32_t ExtiLine )

Generate a software Interrupt Event for Lines in range 0 to 31.

Note:
If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit in the EXTI_PR register (by writing a 1 into the bit)
Reference Manual to LL API cross reference:
SWIER SWIx LL_EXTI_GenerateSWI_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 1150 of file stm32f3xx_ll_exti.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Flag_Management

Functions
Flag_Management
EXTI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_0_31 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_0_31 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_ClearFlag_0_31 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 0 to 31.

Function Documentation

__STATIC_INLINE void LL_EXTI_ClearFlag_0_31 ( uint32_t ExtiLine )

Clear ExtLine Flags for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR PIFx LL_EXTI_ClearFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 1336 of file stm32f3xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31 ( uint32_t ExtiLine )

Check if the ExtLine Flag is set or not for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR PIFx LL_EXTI_IsActiveFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 1219 of file stm32f3xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31 ( uint32_t ExtiLine )

Read ExtLine Combination Flag for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR PIFx LL_EXTI_ReadFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
@note This bit is set when the selected edge event arrives on the interrupt

Definition at line 1277 of file stm32f3xx_ll_exti.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
EXTI Exported Functions

Functions

uint32_t | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
uint32_t | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Function Documentation

uint32_t LL_EXTI_DeInit ( void )

De-initialize the EXTI registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: EXTI registers are de-initialized
  • ERROR: not applicable

Definition at line 99 of file stm32f3xx_ll_exti.c.

References LL_EXTI_WriteReg.

uint32_t LL_EXTI_Init ( LL_EXTI_InitTypeDef * EXTI_InitStruct )

Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.

Parameters:
EXTI_InitStruct pointer to a LL_EXTI_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: EXTI registers are initialized
  • ERROR: not applicable

Definition at line 143 of file stm32f3xx_ll_exti.c.

References assert_param, IS_LL_EXTI_LINE_0_31, IS_LL_EXTI_MODE, IS_LL_EXTI_TRIGGER, LL_EXTI_InitTypeDef::Line_0_31, LL_EXTI_InitTypeDef::LineCommand, LL_EXTI_DisableEvent_0_31(), LL_EXTI_DisableFallingTrig_0_31(), LL_EXTI_DisableIT_0_31(), LL_EXTI_DisableRisingTrig_0_31(), LL_EXTI_EnableEvent_0_31(), LL_EXTI_EnableFallingTrig_0_31(), LL_EXTI_EnableIT_0_31(), LL_EXTI_EnableRisingTrig_0_31(), LL_EXTI_LINE_NONE, LL_EXTI_MODE_EVENT, LL_EXTI_MODE_IT, LL_EXTI_MODE_IT_EVENT, LL_EXTI_TRIGGER_FALLING, LL_EXTI_TRIGGER_NONE, LL_EXTI_TRIGGER_RISING, LL_EXTI_TRIGGER_RISING_FALLING, LL_EXTI_InitTypeDef::Mode, and LL_EXTI_InitTypeDef::Trigger.

void LL_EXTI_StructInit ( LL_EXTI_InitTypeDef * EXTI_InitStruct )

Set each LL_EXTI_InitTypeDef field to default value.

Parameters:
EXTI_InitStruct Pointer to a LL_EXTI_InitTypeDef structure.
Return values:
None

Definition at line 286 of file stm32f3xx_ll_exti.c.

References LL_EXTI_InitTypeDef::Line_0_31, LL_EXTI_InitTypeDef::LineCommand, LL_EXTI_LINE_NONE, LL_EXTI_MODE_IT, LL_EXTI_TRIGGER_FALLING, LL_EXTI_InitTypeDef::Mode, and LL_EXTI_InitTypeDef::Trigger.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: GPIO

Modules
GPIO
STM32F3xx_LL_Driver

Modules

GPIO Private Macros
GPIO Exported Init structures
GPIO Exported Constants
GPIO Exported Macros
GPIO Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for GPIO registers.

Register | Bit | Function
AFRH | AFSELy | LL_GPIO_GetAFPin_8_15
 |  | LL_GPIO_SetAFPin_8_15
AFRL | AFSELy | LL_GPIO_GetAFPin_0_7
 |  | LL_GPIO_SetAFPin_0_7
BRR | BRy | LL_GPIO_ResetOutputPin
BSRR | BSy | LL_GPIO_SetOutputPin
IDR | IDy | LL_GPIO_IsInputPinSet
 |  | LL_GPIO_ReadInputPort
LCKR | LCKK | LL_GPIO_IsAnyPinLocked
 |  | LL_GPIO_LockPin
 | LCKy | LL_GPIO_IsPinLocked
MODER | MODEy | LL_GPIO_GetPinMode
 |  | LL_GPIO_SetPinMode
ODR | ODy | LL_GPIO_IsOutputPinSet
 |  | LL_GPIO_ReadOutputPort
 |  | LL_GPIO_TogglePin
 |  | LL_GPIO_WriteOutputPort
OSPEEDR | OSPEEDy | LL_GPIO_GetPinSpeed
 |  | LL_GPIO_SetPinSpeed
OTYPER | OTy | LL_GPIO_GetPinOutputType
 |  | LL_GPIO_SetPinOutputType
PUPDR | PUPDy | LL_GPIO_GetPinPull
 |  | LL_GPIO_SetPinPull
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: GPIO Private Macros

Defines
GPIO Private Macros
GPIO

Defines

#define | IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define | IS_LL_GPIO_MODE(__VALUE__)
#define | IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)
#define | IS_LL_GPIO_SPEED(__VALUE__)
#define | IS_LL_GPIO_PULL(__VALUE__)
#define | IS_LL_GPIO_ALTERNATE(__VALUE__)

Define Documentation

#define IS_LL_GPIO_ALTERNATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_AF_0  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_7  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_8  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_9  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_10 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_11 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_12 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_13 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_14 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_15 ))

Definition at line 81 of file stm32f3xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))

Definition at line 65 of file stm32f3xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_OUTPUT_TYPE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))

Definition at line 70 of file stm32f3xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_PIN ( __VALUE__ ) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))

Definition at line 63 of file stm32f3xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_PULL ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_PULL_NO)   ||\
                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))

Definition at line 77 of file stm32f3xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_SPEED ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH))

Definition at line 73 of file stm32f3xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_GPIO_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_GPIO_InitTypeDef Struct Reference
GPIO Exported Init structures

LL GPIO Init Structure definition. More...

#include <stm32f3xx_ll_gpio.h>

Data Fields

uint32_t | Pin
uint32_t | Mode
uint32_t | Speed
uint32_t | OutputType
uint32_t | Pull
uint32_t | Alternate

Detailed Description

LL GPIO Init Structure definition.

Definition at line 80 of file stm32f3xx_ll_gpio.h.

Field Documentation

uint32_t LL_GPIO_InitTypeDef::Alternate

Specifies the Peripheral to be connected to the selected pins. This parameter can be a value of Alternate Function.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().

Definition at line 105 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Mode

Specifies the operating mode for the selected pins. This parameter can be a value of Mode.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinMode().

Definition at line 85 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::OutputType

Specifies the operating output type for the selected pins. This parameter can be a value of Output Type.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinOutputType().

Definition at line 95 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Pin

Specifies the GPIO pins to be configured. This parameter can be any value of PIN

Definition at line 82 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Pull

Specifies the operating Pull-up/Pull down for the selected pins. This parameter can be a value of Pull Up Pull Down.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinPull().

Definition at line 100 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Speed

Specifies the speed for the selected pins. This parameter can be a value of Output Speed.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinSpeed().

Definition at line 90 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_gpio.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PIN

Defines
PIN
GPIO Exported Constants

Defines

#define | LL_GPIO_PIN_0 GPIO_BSRR_BS_0
#define | LL_GPIO_PIN_1 GPIO_BSRR_BS_1
#define | LL_GPIO_PIN_2 GPIO_BSRR_BS_2
#define | LL_GPIO_PIN_3 GPIO_BSRR_BS_3
#define | LL_GPIO_PIN_4 GPIO_BSRR_BS_4
#define | LL_GPIO_PIN_5 GPIO_BSRR_BS_5
#define | LL_GPIO_PIN_6 GPIO_BSRR_BS_6
#define | LL_GPIO_PIN_7 GPIO_BSRR_BS_7
#define | LL_GPIO_PIN_8 GPIO_BSRR_BS_8
#define | LL_GPIO_PIN_9 GPIO_BSRR_BS_9
#define | LL_GPIO_PIN_10 GPIO_BSRR_BS_10
#define | LL_GPIO_PIN_11 GPIO_BSRR_BS_11
#define | LL_GPIO_PIN_12 GPIO_BSRR_BS_12
#define | LL_GPIO_PIN_13 GPIO_BSRR_BS_13
#define | LL_GPIO_PIN_14 GPIO_BSRR_BS_14
#define | LL_GPIO_PIN_15 GPIO_BSRR_BS_15
#define | LL_GPIO_PIN_ALL

Define Documentation

#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0

Select pin 0

Definition at line 124 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1

Select pin 1

Definition at line 125 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10

Select pin 10

Definition at line 134 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11

Select pin 11

Definition at line 135 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12

Select pin 12

Definition at line 136 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13

Select pin 13

Definition at line 137 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14

Select pin 14

Definition at line 138 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15

Select pin 15

Definition at line 139 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2

Select pin 2

Definition at line 126 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3

Select pin 3

Definition at line 127 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4

Select pin 4

Definition at line 128 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5

Select pin 5

Definition at line 129 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6

Select pin 6

Definition at line 130 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7

Select pin 7

Definition at line 131 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8

Select pin 8

Definition at line 132 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9

Select pin 9

Definition at line 133 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_PIN_ALL
Value:
(GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1  | GPIO_BSRR_BS_2  | \
                                           GPIO_BSRR_BS_3  | GPIO_BSRR_BS_4  | GPIO_BSRR_BS_5  | \
                                           GPIO_BSRR_BS_6  | GPIO_BSRR_BS_7  | GPIO_BSRR_BS_8  | \
                                           GPIO_BSRR_BS_9  | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
                                           GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
                                           GPIO_BSRR_BS_15)

Select all pins

Definition at line 140 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Mode

Defines
Mode
GPIO Exported Constants

Defines

#define | LL_GPIO_MODE_INPUT (0x00000000U)
#define | LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0
#define | LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1
#define | LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0

Define Documentation

#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1

Select alternate function mode

Definition at line 155 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0

Select analog mode

Definition at line 156 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_MODE_INPUT (0x00000000U)

Select input mode

Definition at line 153 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0

Select output mode

Definition at line 154 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Output Type

Defines
Output Type
GPIO Exported Constants

Defines

#define | LL_GPIO_OUTPUT_PUSHPULL (0x00000000U)
#define | LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0

Define Documentation

#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0

Select open-drain as output type

Definition at line 165 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U)

Select push-pull as output type

Definition at line 164 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Output Speed

Defines
Output Speed
GPIO Exported Constants

Defines

#define | LL_GPIO_SPEED_FREQ_LOW (0x00000000U)
#define | LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0
#define | LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0

Define Documentation

#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0

Select I/O high output speed

Definition at line 175 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U)

Select I/O low output speed

Definition at line 173 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0

Select I/O medium output speed

Definition at line 174 of file stm32f3xx_ll_gpio.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Pull Up Pull Down

Defines
Pull Up Pull Down
GPIO Exported Constants

Defines

#define | LL_GPIO_PULL_NO (0x00000000U)
#define | LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0
#define | LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1

Define Documentation

#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1

Select I/O pull down

Definition at line 185 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_PULL_NO (0x00000000U)

Select I/O no pull

Definition at line 183 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0

Select I/O pull up

Definition at line 184 of file stm32f3xx_ll_gpio.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Alternate Function

Defines
Alternate Function
GPIO Exported Constants

Defines

#define | LL_GPIO_AF_0 (0x0000000U)
#define | LL_GPIO_AF_1 (0x0000001U)
#define | LL_GPIO_AF_2 (0x0000002U)
#define | LL_GPIO_AF_3 (0x0000003U)
#define | LL_GPIO_AF_4 (0x0000004U)
#define | LL_GPIO_AF_5 (0x0000005U)
#define | LL_GPIO_AF_6 (0x0000006U)
#define | LL_GPIO_AF_7 (0x0000007U)
#define | LL_GPIO_AF_8 (0x0000008U)
#define | LL_GPIO_AF_9 (0x0000009U)
#define | LL_GPIO_AF_10 (0x000000AU)
#define | LL_GPIO_AF_11 (0x000000BU)
#define | LL_GPIO_AF_12 (0x000000CU)
#define | LL_GPIO_AF_13 (0x000000DU)
#define | LL_GPIO_AF_14 (0x000000EU)
#define | LL_GPIO_AF_15 (0x000000FU)

Define Documentation

#define LL_GPIO_AF_0 (0x0000000U)

Select alternate function 0

Definition at line 193 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_AF_1 (0x0000001U)

Select alternate function 1

Definition at line 194 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_AF_10 (0x000000AU)

Select alternate function 10

Definition at line 203 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_AF_11 (0x000000BU)

Select alternate function 11

Definition at line 204 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_AF_12 (0x000000CU)

Select alternate function 12

Definition at line 205 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_AF_13 (0x000000DU)

Select alternate function 13

Definition at line 206 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_AF_14 (0x000000EU)

Select alternate function 14

Definition at line 207 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_AF_15 (0x000000FU)

Select alternate function 15

Definition at line 208 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_AF_2 (0x0000002U)

Select alternate function 2

Definition at line 195 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_AF_3 (0x0000003U)

Select alternate function 3

Definition at line 196 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_AF_4 (0x0000004U)

Select alternate function 4

Definition at line 197 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_AF_5 (0x0000005U)

Select alternate function 5

Definition at line 198 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_AF_6 (0x0000006U)

Select alternate function 6

Definition at line 199 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_AF_7 (0x0000007U)

Select alternate function 7

Definition at line 200 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_AF_8 (0x0000008U)

Select alternate function 8

Definition at line 201 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_AF_9 (0x0000009U)

Select alternate function 9

Definition at line 202 of file stm32f3xx_ll_gpio.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
GPIO Exported Macros

Defines

#define | LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in GPIO register.
#define | LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in GPIO register.

Define Documentation

#define LL_GPIO_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in GPIO register.

Parameters:
__INSTANCE__ | GPIO Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 241 of file stm32f3xx_ll_gpio.h.

#define LL_GPIO_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in GPIO register.

Parameters:
__INSTANCE__ | GPIO Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 233 of file stm32f3xx_ll_gpio.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Port Configuration

Functions
Port Configuration
GPIO Exported Functions

Functions

__STATIC_INLINE void | LL_GPIO_SetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
Configure gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
Configure gpio output type for several pins on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio output type for several pins on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
Configure gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Lock configuration of several pins for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsPinLocked (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return 1 if all pins passed as parameter, of a dedicated port, are locked.
__STATIC_INLINE uint32_t | LL_GPIO_IsAnyPinLocked (GPIO_TypeDef *GPIOx)
Return 1 if one of the pin of a dedicated port is locked.

Function Documentation

__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.

Reference Manual to LL API cross reference:
AFRL AFSELy LL_GPIO_GetAFPin_0_7
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
Return values:
Returned value can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15

Definition at line 607 of file stm32f3xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.

Note:
Possible values are from AF0 to AF15 depending on target.
Reference Manual to LL API cross reference:
AFRH AFSELy LL_GPIO_GetAFPin_8_15
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15

Definition at line 685 of file stm32f3xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinMode | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio mode for a dedicated pin on dedicated port.

Note:
I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
MODER MODEy LL_GPIO_GetPinMode
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_MODE_INPUT
  • LL_GPIO_MODE_OUTPUT
  • LL_GPIO_MODE_ALTERNATE
  • LL_GPIO_MODE_ANALOG

Definition at line 323 of file stm32f3xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio output type for several pins on dedicated port.

Note:
Output type as to be set when gpio pin is in output or alternate modes. Possible type are Push-pull or Open-drain.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
OTYPER OTy LL_GPIO_GetPinOutputType
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
Returned value can be one of the following values:
  • LL_GPIO_OUTPUT_PUSHPULL
  • LL_GPIO_OUTPUT_OPENDRAIN

Definition at line 392 of file stm32f3xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinPull | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.

Note:
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
PUPDR PUPDy LL_GPIO_GetPinPull
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_PULL_NO
  • LL_GPIO_PULL_UP
  • LL_GPIO_PULL_DOWN

Definition at line 530 of file stm32f3xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio speed for a dedicated pin on dedicated port.

Note:
I/O speed can be Low, Medium, Fast or High speed.
Warning: only one pin can be passed as parameter.
Refer to datasheet for frequency specifications and the power supply and load conditions for each speed.
Reference Manual to LL API cross reference:
OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_SPEED_FREQ_LOW
  • LL_GPIO_SPEED_FREQ_MEDIUM
  • LL_GPIO_SPEED_FREQ_HIGH

Definition at line 464 of file stm32f3xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked ( GPIO_TypeDef * GPIOx )

Return 1 if one of the pin of a dedicated port is locked.

else return 0.

Reference Manual to LL API cross reference:
LCKR LCKK LL_GPIO_IsAnyPinLocked
Parameters:
GPIOx GPIO Port
Return values:
State of bit (1 or 0).

Definition at line 766 of file stm32f3xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return 1 if all pins passed as parameter, of a dedicated port, are locked.

else Return 0.

Reference Manual to LL API cross reference:
LCKR LCKy LL_GPIO_IsPinLocked
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 755 of file stm32f3xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_LockPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Lock configuration of several pins for a dedicated port.

Note:
When the lock sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next reset.
Each lock bit freezes a specific configuration register (control and alternate function registers).
Reference Manual to LL API cross reference:
LCKR LCKK LL_GPIO_LockPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 721 of file stm32f3xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_SetAFPin_0_7 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Alternate
 | ) |  |

Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.

Note:
Possible values are from AF0 to AF15 depending on target.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
AFRL AFSELy LL_GPIO_SetAFPin_0_7
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
Alternate This parameter can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15
Return values:
None

Definition at line 570 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetAFPin_8_15 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Alternate
 | ) |  |

Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.

Note:
Possible values are from AF0 to AF15 depending on target.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
AFRH AFSELy LL_GPIO_SetAFPin_8_15
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Alternate This parameter can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15
Return values:
None

Definition at line 647 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinMode | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Mode
 | ) |  |

Configure gpio mode for a dedicated pin on dedicated port.

Note:
I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
MODER MODEy LL_GPIO_SetPinMode
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Mode This parameter can be one of the following values:
  • LL_GPIO_MODE_INPUT
  • LL_GPIO_MODE_OUTPUT
  • LL_GPIO_MODE_ALTERNATE
  • LL_GPIO_MODE_ANALOG
Return values:
None

Definition at line 289 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinOutputType | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask,
 |  | uint32_t | OutputType
 | ) |  |

Configure gpio output type for several pins on dedicated port.

Note:
Output type as to be set when gpio pin is in output or alternate modes. Possible type are Push-pull or Open-drain.
Reference Manual to LL API cross reference:
OTYPER OTy LL_GPIO_SetPinOutputType
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
OutputType This parameter can be one of the following values:
  • LL_GPIO_OUTPUT_PUSHPULL
  • LL_GPIO_OUTPUT_OPENDRAIN
Return values:
None

Definition at line 358 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinPull | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Pull
 | ) |  |

Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.

Note:
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
PUPDR PUPDy LL_GPIO_SetPinPull
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Pull This parameter can be one of the following values:
  • LL_GPIO_PULL_NO
  • LL_GPIO_PULL_UP
  • LL_GPIO_PULL_DOWN
Return values:
None

Definition at line 498 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinSpeed | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Speed
 | ) |  |

Configure gpio speed for a dedicated pin on dedicated port.

Note:
I/O speed can be Low, Medium, Fast or High speed.
Warning: only one pin can be passed as parameter.
Refer to datasheet for frequency specifications and the power supply and load conditions for each speed.
Reference Manual to LL API cross reference:
OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Speed This parameter can be one of the following values:
  • LL_GPIO_SPEED_FREQ_LOW
  • LL_GPIO_SPEED_FREQ_MEDIUM
  • LL_GPIO_SPEED_FREQ_HIGH
Return values:
None

Definition at line 428 of file stm32f3xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Access

Functions
Data Access
GPIO Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_GPIO_ReadInputPort (GPIO_TypeDef *GPIOx)
Return full input data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsInputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_WriteOutputPort (GPIO_TypeDef *GPIOx, uint32_t PortValue)
Write output data register for the port.
__STATIC_INLINE uint32_t | LL_GPIO_ReadOutputPort (GPIO_TypeDef *GPIOx)
Return full output data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsOutputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_SetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to high level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_ResetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to low level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Toggle data value for several pin of dedicated port.

Function Documentation

__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return if input data level for several pins of dedicated port is high or low.

Reference Manual to LL API cross reference:
IDR IDy LL_GPIO_IsInputPinSet
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 814 of file stm32f3xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return if input data level for several pins of dedicated port is high or low.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_IsOutputPinSet
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 866 of file stm32f3xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort ( GPIO_TypeDef * GPIOx )

Return full input data register value for a dedicated port.

Reference Manual to LL API cross reference:
IDR IDy LL_GPIO_ReadInputPort
Parameters:
GPIOx GPIO Port
Return values:
Input data register value of port

Definition at line 785 of file stm32f3xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort ( GPIO_TypeDef * GPIOx )

Return full output data register value for a dedicated port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_ReadOutputPort
Parameters:
GPIOx GPIO Port
Return values:
Output data register value of port

Definition at line 837 of file stm32f3xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_ResetOutputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Set several pins to low level on dedicated gpio port.

Reference Manual to LL API cross reference:
BRR BRy LL_GPIO_ResetOutputPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 924 of file stm32f3xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_SetOutputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Set several pins to high level on dedicated gpio port.

Reference Manual to LL API cross reference:
BSRR BSy LL_GPIO_SetOutputPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 895 of file stm32f3xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_TogglePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Toggle data value for several pin of dedicated port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_TogglePin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 953 of file stm32f3xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_WriteOutputPort | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PortValue
 | ) |  |

Write output data register for the port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_WriteOutputPort
Parameters:
GPIOx | GPIO Port
PortValue | Level value for each pin of the port
Return values:
None

Definition at line 826 of file stm32f3xx_ll_gpio.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
GPIO Exported Functions

Functions

ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_GPIO_DeInit ( GPIO_TypeDef * GPIOx )

De-initialize GPIO registers (Registers restored to their default values).

Parameters:
GPIOx GPIO Port
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: GPIO registers are de-initialized
  • ERROR: Wrong GPIO Port

Definition at line 119 of file stm32f3xx_ll_gpio.c.

References assert_param, LL_AHB1_GRP1_ForceReset(), LL_AHB1_GRP1_PERIPH_GPIOA, LL_AHB1_GRP1_PERIPH_GPIOB, LL_AHB1_GRP1_PERIPH_GPIOC, LL_AHB1_GRP1_PERIPH_GPIOD, LL_AHB1_GRP1_PERIPH_GPIOE, LL_AHB1_GRP1_PERIPH_GPIOF, and LL_AHB1_GRP1_ReleaseReset().

ErrorStatus LL_GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | LL_GPIO_InitTypeDef * | GPIO_InitStruct
 | ) |  |

Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.

Parameters:
GPIOx | GPIO Port
GPIO_InitStruct | pointer to a LL_GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
  • ERROR: Not applicable

Definition at line 194 of file stm32f3xx_ll_gpio.c.

References LL_GPIO_InitTypeDef::Alternate, assert_param, IS_LL_GPIO_ALTERNATE, IS_LL_GPIO_MODE, IS_LL_GPIO_OUTPUT_TYPE, IS_LL_GPIO_PIN, IS_LL_GPIO_PULL, IS_LL_GPIO_SPEED, LL_GPIO_MODE_ALTERNATE, LL_GPIO_MODE_OUTPUT, LL_GPIO_SetAFPin_0_7(), LL_GPIO_SetAFPin_8_15(), LL_GPIO_SetPinMode(), LL_GPIO_SetPinOutputType(), LL_GPIO_SetPinPull(), LL_GPIO_SetPinSpeed(), LL_GPIO_InitTypeDef::Mode, LL_GPIO_InitTypeDef::OutputType, LL_GPIO_InitTypeDef::Pin, LL_GPIO_InitTypeDef::Pull, and LL_GPIO_InitTypeDef::Speed.

void LL_GPIO_StructInit ( LL_GPIO_InitTypeDef * GPIO_InitStruct )

Set each LL_GPIO_InitTypeDef field to default value.

Parameters:
GPIO_InitStruct pointer to a LL_GPIO_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 270 of file stm32f3xx_ll_gpio.c.

References LL_GPIO_InitTypeDef::Alternate, LL_GPIO_AF_0, LL_GPIO_MODE_ANALOG, LL_GPIO_OUTPUT_PUSHPULL, LL_GPIO_PIN_ALL, LL_GPIO_PULL_NO, LL_GPIO_SPEED_FREQ_LOW, LL_GPIO_InitTypeDef::Mode, LL_GPIO_InitTypeDef::OutputType, LL_GPIO_InitTypeDef::Pin, LL_GPIO_InitTypeDef::Pull, and LL_GPIO_InitTypeDef::Speed.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C

Modules
I2C
STM32F3xx_LL_Driver

Modules

I2C Private Constants
I2C Private Macros
I2C Exported Init structure
I2C Exported Constants
I2C Exported Macros
I2C Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for I2C registers.

Register | Bit | Function
CR1 | ADDRIE | LL_I2C_DisableIT_ADDR
 |  | LL_I2C_EnableIT_ADDR
 |  | LL_I2C_IsEnabledIT_ADDR
 | ALERTEN | LL_I2C_DisableSMBusAlert
 |  | LL_I2C_EnableSMBusAlert
 |  | LL_I2C_IsEnabledSMBusAlert
 | ANFOFF | LL_I2C_ConfigFilters
 |  | LL_I2C_DisableAnalogFilter
 |  | LL_I2C_EnableAnalogFilter
 |  | LL_I2C_IsEnabledAnalogFilter
 | DNF | LL_I2C_ConfigFilters
 |  | LL_I2C_GetDigitalFilter
 |  | LL_I2C_SetDigitalFilter
 | ERRIE | LL_I2C_DisableIT_ERR
 |  | LL_I2C_EnableIT_ERR
 |  | LL_I2C_IsEnabledIT_ERR
 | GCEN | LL_I2C_DisableGeneralCall
 |  | LL_I2C_EnableGeneralCall
 |  | LL_I2C_IsEnabledGeneralCall
 | NACKIE | LL_I2C_DisableIT_NACK
 |  | LL_I2C_EnableIT_NACK
 |  | LL_I2C_IsEnabledIT_NACK
 | NOSTRETCH | LL_I2C_DisableClockStretching
 |  | LL_I2C_EnableClockStretching
 |  | LL_I2C_IsEnabledClockStretching
 | PE | LL_I2C_Disable
 |  | LL_I2C_Enable
 |  | LL_I2C_IsEnabled
 | PECEN | LL_I2C_DisableSMBusPEC
 |  | LL_I2C_EnableSMBusPEC
 |  | LL_I2C_IsEnabledSMBusPEC
 | RXDMAEN | LL_I2C_DisableDMAReq_RX
 |  | LL_I2C_EnableDMAReq_RX
 |  | LL_I2C_IsEnabledDMAReq_RX
 | RXIE | LL_I2C_DisableIT_RX
 |  | LL_I2C_EnableIT_RX
 |  | LL_I2C_IsEnabledIT_RX
 | SBC | LL_I2C_DisableSlaveByteControl
 |  | LL_I2C_EnableSlaveByteControl
 |  | LL_I2C_IsEnabledSlaveByteControl
 | SMBDEN | LL_I2C_GetMode
 |  | LL_I2C_SetMode
 | SMBHEN | LL_I2C_GetMode
 |  | LL_I2C_SetMode
 | STOPIE | LL_I2C_DisableIT_STOP
 |  | LL_I2C_EnableIT_STOP
 |  | LL_I2C_IsEnabledIT_STOP
 | TCIE | LL_I2C_DisableIT_TC
 |  | LL_I2C_EnableIT_TC
 |  | LL_I2C_IsEnabledIT_TC
 | TXDMAEN | LL_I2C_DisableDMAReq_TX
 |  | LL_I2C_EnableDMAReq_TX
 |  | LL_I2C_IsEnabledDMAReq_TX
 | TXIE | LL_I2C_DisableIT_TX
 |  | LL_I2C_EnableIT_TX
 |  | LL_I2C_IsEnabledIT_TX
 | WUPEN | LL_I2C_DisableWakeUpFromStop
 |  | LL_I2C_EnableWakeUpFromStop
 |  | LL_I2C_IsEnabledWakeUpFromStop
CR2 | ADD10 | LL_I2C_GetMasterAddressingMode
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_SetMasterAddressingMode
 | AUTOEND | LL_I2C_DisableAutoEndMode
 |  | LL_I2C_EnableAutoEndMode
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_IsEnabledAutoEndMode
 | HEAD10R | LL_I2C_DisableAuto10BitRead
 |  | LL_I2C_EnableAuto10BitRead
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_IsEnabledAuto10BitRead
 | NACK | LL_I2C_AcknowledgeNextData
 | NBYTES | LL_I2C_GetTransferSize
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_SetTransferSize
 | PECBYTE | LL_I2C_EnableSMBusPECCompare
 |  | LL_I2C_IsEnabledSMBusPECCompare
 | RD_WRN | LL_I2C_GetTransferRequest
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_SetTransferRequest
 | RELOAD | LL_I2C_DisableReloadMode
 |  | LL_I2C_EnableReloadMode
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_IsEnabledReloadMode
 | SADD | LL_I2C_GetSlaveAddr
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_SetSlaveAddr
 | START | LL_I2C_GenerateStartCondition
 |  | LL_I2C_HandleTransfer
 | STOP | LL_I2C_GenerateStopCondition
 |  | LL_I2C_HandleTransfer
ICR | ADDRCF | LL_I2C_ClearFlag_ADDR
 | ALERTCF | LL_I2C_ClearSMBusFlag_ALERT
 | ARLOCF | LL_I2C_ClearFlag_ARLO
 | BERRCF | LL_I2C_ClearFlag_BERR
 | NACKCF | LL_I2C_ClearFlag_NACK
 | OVRCF | LL_I2C_ClearFlag_OVR
 | PECCF | LL_I2C_ClearSMBusFlag_PECERR
 | STOPCF | LL_I2C_ClearFlag_STOP
 | TIMOUTCF | LL_I2C_ClearSMBusFlag_TIMEOUT
ISR | ADDCODE | LL_I2C_GetAddressMatchCode
 | ADDR | LL_I2C_IsActiveFlag_ADDR
 | ALERT | LL_I2C_IsActiveSMBusFlag_ALERT
 | ARLO | LL_I2C_IsActiveFlag_ARLO
 | BERR | LL_I2C_IsActiveFlag_BERR
 | BUSY | LL_I2C_IsActiveFlag_BUSY
 | DIR | LL_I2C_GetTransferDirection
 | NACKF | LL_I2C_IsActiveFlag_NACK
 | OVR | LL_I2C_IsActiveFlag_OVR
 | PECERR | LL_I2C_IsActiveSMBusFlag_PECERR
 | RXNE | LL_I2C_IsActiveFlag_RXNE
 | STOPF | LL_I2C_IsActiveFlag_STOP
 | TC | LL_I2C_IsActiveFlag_TC
 | TCR | LL_I2C_IsActiveFlag_TCR
 | TIMEOUT | LL_I2C_IsActiveSMBusFlag_TIMEOUT
 | TXE | LL_I2C_ClearFlag_TXE
 |  | LL_I2C_IsActiveFlag_TXE
 | TXIS | LL_I2C_IsActiveFlag_TXIS
OAR1 | OA1 | LL_I2C_SetOwnAddress1
 | OA1EN | LL_I2C_DisableOwnAddress1
 |  | LL_I2C_EnableOwnAddress1
 |  | LL_I2C_IsEnabledOwnAddress1
 | OA1MODE | LL_I2C_SetOwnAddress1
OAR2 | OA2 | LL_I2C_SetOwnAddress2
 | OA2EN | LL_I2C_DisableOwnAddress2
 |  | LL_I2C_EnableOwnAddress2
 |  | LL_I2C_IsEnabledOwnAddress2
 | OA2MSK | LL_I2C_SetOwnAddress2
PECR | PEC | LL_I2C_GetSMBusPEC
RXDR | RXDATA | LL_I2C_DMA_GetRegAddr
 |  | LL_I2C_ReceiveData8
TIMEOUTR | TEXTEN | LL_I2C_DisableSMBusTimeout
 |  | LL_I2C_EnableSMBusTimeout
 |  | LL_I2C_IsEnabledSMBusTimeout
 | TIDLE | LL_I2C_ConfigSMBusTimeout
 |  | LL_I2C_GetSMBusTimeoutAMode
 |  | LL_I2C_SetSMBusTimeoutAMode
 | TIMEOUTA | LL_I2C_ConfigSMBusTimeout
 |  | LL_I2C_GetSMBusTimeoutA
 |  | LL_I2C_SetSMBusTimeoutA
 | TIMEOUTB | LL_I2C_ConfigSMBusTimeout
 |  | LL_I2C_GetSMBusTimeoutB
 |  | LL_I2C_SetSMBusTimeoutB
 | TIMOUTEN | LL_I2C_DisableSMBusTimeout
 |  | LL_I2C_EnableSMBusTimeout
 |  | LL_I2C_IsEnabledSMBusTimeout
TIMINGR | PRESC | LL_I2C_GetTimingPrescaler
 | SCLDEL | LL_I2C_GetDataSetupTime
 | SCLH | LL_I2C_GetClockHighPeriod
 | SCLL | LL_I2C_GetClockLowPeriod
 | SDADEL | LL_I2C_GetDataHoldTime
 | TIMINGR | LL_I2C_SetTiming
TXDR | TXDATA | LL_I2C_DMA_GetRegAddr
 |  | LL_I2C_TransmitData8
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Private Constants

I2C Private Constants
I2C
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Private Macros

Defines
I2C Private Macros
I2C

Defines

#define | IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)
#define | IS_LL_I2C_ANALOG_FILTER(__VALUE__)
#define | IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
#define | IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
#define | IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)
#define | IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)

Define Documentation

#define IS_LL_I2C_ANALOG_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
                                                 ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))

Definition at line 69 of file stm32f3xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_DIGITAL_FILTER ( __VALUE__ ) ((__VALUE__) <= 0x0000000FU)

Definition at line 72 of file stm32f3xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_OWN_ADDRESS1 ( __VALUE__ ) ((__VALUE__) <= 0x000003FFU)

Definition at line 74 of file stm32f3xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_OWN_ADDRSIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
                                                 ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))

Definition at line 79 of file stm32f3xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_PERIPHERAL_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_MODE_I2C)          || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))

Definition at line 64 of file stm32f3xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_TYPE_ACKNOWLEDGE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_ACK) || \
                                                 ((__VALUE__) == LL_I2C_NACK))

Definition at line 76 of file stm32f3xx_ll_i2c.c.

Referenced by LL_I2C_Init().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_I2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_I2C_InitTypeDef Struct Reference
I2C Exported Init structure

#include <stm32f3xx_ll_i2c.h>

Data Fields

uint32_t | PeripheralMode
uint32_t | Timing
uint32_t | AnalogFilter
uint32_t | DigitalFilter
uint32_t | OwnAddress1
uint32_t | TypeAcknowledge
uint32_t | OwnAddrSize

Detailed Description

Definition at line 83 of file stm32f3xx_ll_i2c.h.

Field Documentation

uint32_t LL_I2C_InitTypeDef::AnalogFilter

Enables or disables analog noise filter. This parameter can be a value of Analog Filter Selection

This feature can be modified afterwards using unitary functions LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter().

Definition at line 96 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::DigitalFilter

Configures the digital noise filter. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F

This feature can be modified afterwards using unitary function LL_I2C_SetDigitalFilter().

Definition at line 101 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::OwnAddress1

Specifies the device own address 1. This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF

This feature can be modified afterwards using unitary function LL_I2C_SetOwnAddress1().

Definition at line 106 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::OwnAddrSize

Specifies the device own address 1 size (7-bit or 10-bit). This parameter can be a value of Own Address 1 Length

This feature can be modified afterwards using unitary function LL_I2C_SetOwnAddress1().

Definition at line 116 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::PeripheralMode

Specifies the peripheral mode. This parameter can be a value of Peripheral Mode

This feature can be modified afterwards using unitary function LL_I2C_SetMode().

Definition at line 85 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::Timing

Specifies the SDA setup, hold time and the SCL high, low period values. This parameter must be set by referring to the STM32CubeMX Tool and the helper macro __LL_I2C_CONVERT_TIMINGS()

This feature can be modified afterwards using unitary function LL_I2C_SetTiming().

Definition at line 90 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::TypeAcknowledge

Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. This parameter can be a value of Acknowledge Generation

This feature can be modified afterwards using unitary function LL_I2C_AcknowledgeNextData().

Definition at line 111 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_i2c.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
I2C Exported Constants

Flags defines which can be used with LL_I2C_WriteReg function. More...

Defines

#define | LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF
#define | LL_I2C_ICR_NACKCF I2C_ICR_NACKCF
#define | LL_I2C_ICR_STOPCF I2C_ICR_STOPCF
#define | LL_I2C_ICR_BERRCF I2C_ICR_BERRCF
#define | LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF
#define | LL_I2C_ICR_OVRCF I2C_ICR_OVRCF
#define | LL_I2C_ICR_PECCF I2C_ICR_PECCF
#define | LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF
#define | LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF

Detailed Description

Flags defines which can be used with LL_I2C_WriteReg function.

Define Documentation

#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF

Address Matched flag

Definition at line 135 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF

Alert flag

Definition at line 143 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF

Arbitration Lost flag

Definition at line 139 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF

Bus error flag

Definition at line 138 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF

Not Acknowledge flag

Definition at line 136 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF

Overrun/Underrun flag

Definition at line 140 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ICR_PECCF I2C_ICR_PECCF

PEC error flag

Definition at line 141 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF

Stop detection flag

Definition at line 137 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF

Timeout detection flag

Definition at line 142 of file stm32f3xx_ll_i2c.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
I2C Exported Constants

Flags defines which can be used with LL_I2C_ReadReg function. More...

Defines

#define | LL_I2C_ISR_TXE I2C_ISR_TXE
#define | LL_I2C_ISR_TXIS I2C_ISR_TXIS
#define | LL_I2C_ISR_RXNE I2C_ISR_RXNE
#define | LL_I2C_ISR_ADDR I2C_ISR_ADDR
#define | LL_I2C_ISR_NACKF I2C_ISR_NACKF
#define | LL_I2C_ISR_STOPF I2C_ISR_STOPF
#define | LL_I2C_ISR_TC I2C_ISR_TC
#define | LL_I2C_ISR_TCR I2C_ISR_TCR
#define | LL_I2C_ISR_BERR I2C_ISR_BERR
#define | LL_I2C_ISR_ARLO I2C_ISR_ARLO
#define | LL_I2C_ISR_OVR I2C_ISR_OVR
#define | LL_I2C_ISR_PECERR I2C_ISR_PECERR
#define | LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT
#define | LL_I2C_ISR_ALERT I2C_ISR_ALERT
#define | LL_I2C_ISR_BUSY I2C_ISR_BUSY

Detailed Description

Flags defines which can be used with LL_I2C_ReadReg function.

Define Documentation

#define LL_I2C_ISR_ADDR I2C_ISR_ADDR

Address matched (slave mode)

Definition at line 155 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ISR_ALERT I2C_ISR_ALERT

SMBus alert (SMBus mode)

Definition at line 165 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ISR_ARLO I2C_ISR_ARLO

Arbitration lost

Definition at line 161 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ISR_BERR I2C_ISR_BERR

Bus error

Definition at line 160 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ISR_BUSY I2C_ISR_BUSY

Bus busy

Definition at line 166 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ISR_NACKF I2C_ISR_NACKF

Not Acknowledge received flag

Definition at line 156 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ISR_OVR I2C_ISR_OVR

Overrun/Underrun (slave mode)

Definition at line 162 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ISR_PECERR I2C_ISR_PECERR

PEC Error in reception (SMBus mode)

Definition at line 163 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ISR_RXNE I2C_ISR_RXNE

Receive data register not empty

Definition at line 154 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ISR_STOPF I2C_ISR_STOPF

Stop detection flag

Definition at line 157 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ISR_TC I2C_ISR_TC

Transfer Complete (master mode)

Definition at line 158 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ISR_TCR I2C_ISR_TCR

Transfer Complete Reload

Definition at line 159 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT

Timeout detection flag (SMBus mode)

Definition at line 164 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ISR_TXE I2C_ISR_TXE

Transmit data register empty

Definition at line 152 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ISR_TXIS I2C_ISR_TXIS

Transmit interrupt status

Definition at line 153 of file stm32f3xx_ll_i2c.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IT Defines

Defines
IT Defines
I2C Exported Constants

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions. More...

Defines

#define | LL_I2C_CR1_TXIE I2C_CR1_TXIE
#define | LL_I2C_CR1_RXIE I2C_CR1_RXIE
#define | LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE
#define | LL_I2C_CR1_NACKIE I2C_CR1_NACKIE
#define | LL_I2C_CR1_STOPIE I2C_CR1_STOPIE
#define | LL_I2C_CR1_TCIE I2C_CR1_TCIE
#define | LL_I2C_CR1_ERRIE I2C_CR1_ERRIE

Detailed Description

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions.

Define Documentation

#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE

Address match Interrupt enable (slave only)

Definition at line 177 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE

Error interrupts enable

Definition at line 181 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE

Not acknowledge received Interrupt enable

Definition at line 178 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_CR1_RXIE I2C_CR1_RXIE

RX Interrupt enable

Definition at line 176 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE

STOP detection Interrupt enable

Definition at line 179 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_CR1_TCIE I2C_CR1_TCIE

Transfer Complete interrupt enable

Definition at line 180 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_CR1_TXIE I2C_CR1_TXIE

TX Interrupt enable

Definition at line 175 of file stm32f3xx_ll_i2c.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral Mode

Defines
Peripheral Mode
I2C Exported Constants

Defines

#define | LL_I2C_MODE_I2C 0x00000000U
#define | LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | LL_I2C_MODE_SMBUS_DEVICE 0x00000000U
#define | LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN

Define Documentation

#define LL_I2C_MODE_I2C 0x00000000U

I2C Master or Slave mode

Definition at line 189 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U

SMBus Device default mode (Default address not acknowledge)

Definition at line 191 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN

SMBus Device Default address acknowledge

Definition at line 192 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN

SMBus Host address acknowledge

Definition at line 190 of file stm32f3xx_ll_i2c.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Analog Filter Selection

Defines
Analog Filter Selection
I2C Exported Constants

Defines

#define | LL_I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Analog filter is disabled.

Definition at line 201 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U

Analog filter is enabled.

Definition at line 200 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Master Addressing Mode

Defines
Master Addressing Mode
I2C Exported Constants

Defines

#define | LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U
#define | LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10

Define Documentation

#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10

Master operates in 10-bit addressing mode.

Definition at line 210 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U

Master operates in 7-bit addressing mode.

Definition at line 209 of file stm32f3xx_ll_i2c.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Own Address 1 Length

Defines
Own Address 1 Length
I2C Exported Constants

Defines

#define | LL_I2C_OWNADDRESS1_7BIT 0x00000000U
#define | LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE

Define Documentation

#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE

Own address 1 is a 10-bit address.

Definition at line 219 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U

Own address 1 is a 7-bit address.

Definition at line 218 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Own Address 2 Masks

Defines
Own Address 2 Masks
I2C Exported Constants

Defines

#define | LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK
#define | LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01
#define | LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02
#define | LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03
#define | LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04
#define | LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05
#define | LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06
#define | LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07

Define Documentation

#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01

Only Address2 bits[7:2] are compared.

Definition at line 228 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02

Only Address2 bits[7:3] are compared.

Definition at line 229 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03

Only Address2 bits[7:4] are compared.

Definition at line 230 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04

Only Address2 bits[7:5] are compared.

Definition at line 231 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05

Only Address2 bits[7:6] are compared.

Definition at line 232 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06

Only Address2 bits[7] are compared.

Definition at line 233 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07

No comparison is done. All Address2 are acknowledged.

Definition at line 234 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK

Own Address2 No mask.

Definition at line 227 of file stm32f3xx_ll_i2c.h.

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STM32F373xC HAL User Manual: Acknowledge Generation

Defines
Acknowledge Generation
I2C Exported Constants

Defines

#define | LL_I2C_ACK 0x00000000U
#define | LL_I2C_NACK I2C_CR2_NACK

Define Documentation

#define LL_I2C_ACK 0x00000000U

ACK is sent after current received byte.

Definition at line 242 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_NACK I2C_CR2_NACK

NACK is sent after current received byte.

Definition at line 243 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Slave Address Length

Defines
Slave Address Length
I2C Exported Constants

Defines

#define | LL_I2C_ADDRSLAVE_7BIT 0x00000000U
#define | LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10

Define Documentation

#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10

Slave Address in 10-bit.

Definition at line 252 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U

Slave Address in 7-bit.

Definition at line 251 of file stm32f3xx_ll_i2c.h.

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STM32F373xC HAL User Manual: Transfer Request Direction

Defines
Transfer Request Direction
I2C Exported Constants

Defines

#define | LL_I2C_REQUEST_WRITE 0x00000000U
#define | LL_I2C_REQUEST_READ I2C_CR2_RD_WRN

Define Documentation

#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN

Master request a read transfer.

Definition at line 261 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_REQUEST_WRITE 0x00000000U

Master request a write transfer.

Definition at line 260 of file stm32f3xx_ll_i2c.h.

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STM32F373xC HAL User Manual: Transfer End Mode

Defines
Transfer End Mode
I2C Exported Constants

Defines

#define | LL_I2C_MODE_RELOAD I2C_CR2_RELOAD
#define | LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND
#define | LL_I2C_MODE_SOFTEND 0x00000000U
#define | LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD
#define | LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND
#define | LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND
#define | LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
#define | LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)

Define Documentation

#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND

Enable I2C Automatic end mode with no HW PEC comparison.

Definition at line 270 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD

Enable I2C Reload mode.

Definition at line 269 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 273 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 275 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 272 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND

Enable SMBUS Software end mode with HW PEC comparison.

Definition at line 274 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)

Enable SMBUS Software end mode with HW PEC comparison.

Definition at line 276 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_MODE_SOFTEND 0x00000000U

Enable I2C Software end mode with no HW PEC comparison.

Definition at line 271 of file stm32f3xx_ll_i2c.h.

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STM32F373xC HAL User Manual: Start And Stop Generation

Defines
Start And Stop Generation
I2C Exported Constants

Defines

#define | LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
#define | LL_I2C_GENERATE_STOP I2C_CR2_STOP
#define | LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_START_WRITE I2C_CR2_START
#define | LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START
#define | LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
#define | LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START

Define Documentation

#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U

Don't Generate Stop and Start condition.

Definition at line 284 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)

Generate Restart for read request, slave 10Bit address.

Definition at line 290 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START

Generate Restart for write request, slave 10Bit address.

Definition at line 291 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)

Generate Restart for read request, slave 7Bit address.

Definition at line 288 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START

Generate Restart for write request, slave 7Bit address.

Definition at line 289 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)

Generate Start for read request.

Definition at line 286 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START

Generate Start for write request.

Definition at line 287 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_GENERATE_STOP I2C_CR2_STOP

Generate Stop condition (Size should be set to 0).

Definition at line 285 of file stm32f3xx_ll_i2c.h.

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STM32F373xC HAL User Manual: Read Write Direction

Defines
Read Write Direction
I2C Exported Constants

Defines

#define | LL_I2C_DIRECTION_WRITE 0x00000000U
#define | LL_I2C_DIRECTION_READ I2C_ISR_DIR

Define Documentation

#define LL_I2C_DIRECTION_READ I2C_ISR_DIR

Read transfer request by master, slave enters transmitter mode.

Definition at line 300 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_DIRECTION_WRITE 0x00000000U

Write transfer request by master, slave enters receiver mode.

Definition at line 299 of file stm32f3xx_ll_i2c.h.

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STM32F373xC HAL User Manual: DMA Register Data

Defines
DMA Register Data
I2C Exported Constants

Defines

#define | LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U

Define Documentation

#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U

Get address of data register used for reception

Definition at line 309 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U

Get address of data register used for transmission

Definition at line 308 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_DMA_GetRegAddr().

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STM32F373xC HAL User Manual: SMBus TimeoutA Mode SCL SDA Timeout

Defines
SMBus TimeoutA Mode SCL SDA Timeout
I2C Exported Constants

Defines

#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE

Define Documentation

#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U

TimeoutA is used to detect SCL low level timeout.

Definition at line 317 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE

TimeoutA is used to detect both SCL and SDA high level timeout.

Definition at line 318 of file stm32f3xx_ll_i2c.h.

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STM32F373xC HAL User Manual: SMBus Timeout Selection

Defines
SMBus Timeout Selection
I2C Exported Constants

Defines

#define | LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN
#define | LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN
#define | LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)

Define Documentation

#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)

TimeoutA and TimeoutB (extended clock) enable bits

Definition at line 328 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN

TimeoutA enable bit

Definition at line 326 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN

TimeoutB (extended clock) enable bit

Definition at line 327 of file stm32f3xx_ll_i2c.h.

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STM32F373xC HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
I2C Exported Macros

Defines

#define | LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2C register.
#define | LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2C register.

Define Documentation

#define LL_I2C_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in I2C register.

Parameters:
__INSTANCE__ | I2C Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 361 of file stm32f3xx_ll_i2c.h.

#define LL_I2C_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in I2C register.

Parameters:
__INSTANCE__ | I2C Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 353 of file stm32f3xx_ll_i2c.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Convert SDA SCL timings

Defines
Convert SDA SCL timings
I2C Exported Macros

Defines

#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)
Configure the SDA setup, hold time and the SCL high, low period.

Define Documentation

#define __LL_I2C_CONVERT_TIMINGS | ( | __PRESCALER__,
 |  | __DATA_SETUP_TIME__,
 |  | __DATA_HOLD_TIME__,
 |  | __CLOCK_HIGH_PERIOD__,
 |  | __CLOCK_LOW_PERIOD__
 | ) |
Value:
((((uint32_t)(__PRESCALER__)         << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
         (((uint32_t)(__DATA_SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
         (((uint32_t)(__DATA_HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
         (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
         (((uint32_t)(__CLOCK_LOW_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))

Configure the SDA setup, hold time and the SCL high, low period.

Parameters:
__PRESCALER__ | This parameter must be a value between Min_Data=0 and Max_Data=0xF.
__DATA_SETUP_TIME__ | This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
__DATA_HOLD_TIME__ | This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
__CLOCK_HIGH_PERIOD__ | This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
__CLOCK_LOW_PERIOD__ | This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
Return values:
Value between Min_Data=0 and Max_Data=0xFFFFFFFF

Definition at line 378 of file stm32f3xx_ll_i2c.h.

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STM32F373xC HAL User Manual: Configuration

Functions
Configuration
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_Enable (I2C_TypeDef *I2Cx)
Enable I2C peripheral (PE = 1).
__STATIC_INLINE void | LL_I2C_Disable (I2C_TypeDef *I2Cx)
Disable I2C peripheral (PE = 0).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabled (I2C_TypeDef *I2Cx)
Check if the I2C peripheral is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigFilters (I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
Configure Noise Filters (Analog and Digital).
__STATIC_INLINE void | LL_I2C_SetDigitalFilter (I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
Configure Digital Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_GetDigitalFilter (I2C_TypeDef *I2Cx)
Get the current Digital Noise Filter configuration.
__STATIC_INLINE void | LL_I2C_EnableAnalogFilter (I2C_TypeDef *I2Cx)
Enable Analog Noise Filter.
__STATIC_INLINE void | LL_I2C_DisableAnalogFilter (I2C_TypeDef *I2Cx)
Disable Analog Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAnalogFilter (I2C_TypeDef *I2Cx)
Check if Analog Noise Filter is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_TX (I2C_TypeDef *I2Cx)
Enable DMA transmission requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_TX (I2C_TypeDef *I2Cx)
Disable DMA transmission requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_TX (I2C_TypeDef *I2Cx)
Check if DMA transmission requests are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_RX (I2C_TypeDef *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_RX (I2C_TypeDef *I2Cx)
Disable DMA reception requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_RX (I2C_TypeDef *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_DMA_GetRegAddr (I2C_TypeDef *I2Cx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE void | LL_I2C_EnableClockStretching (I2C_TypeDef *I2Cx)
Enable Clock stretching.
__STATIC_INLINE void | LL_I2C_DisableClockStretching (I2C_TypeDef *I2Cx)
Disable Clock stretching.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledClockStretching (I2C_TypeDef *I2Cx)
Check if Clock stretching is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSlaveByteControl (I2C_TypeDef *I2Cx)
Enable hardware byte control in slave mode.
__STATIC_INLINE void | LL_I2C_DisableSlaveByteControl (I2C_TypeDef *I2Cx)
Disable hardware byte control in slave mode.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSlaveByteControl (I2C_TypeDef *I2Cx)
Check if hardware byte control in slave mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableWakeUpFromStop (I2C_TypeDef *I2Cx)
Enable Wakeup from STOP.
__STATIC_INLINE void | LL_I2C_DisableWakeUpFromStop (I2C_TypeDef *I2Cx)
Disable Wakeup from STOP.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledWakeUpFromStop (I2C_TypeDef *I2Cx)
Check if Wakeup from STOP is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableGeneralCall (I2C_TypeDef *I2Cx)
Enable General Call.
__STATIC_INLINE void | LL_I2C_DisableGeneralCall (I2C_TypeDef *I2Cx)
Disable General Call.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledGeneralCall (I2C_TypeDef *I2Cx)
Check if General Call is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetMasterAddressingMode (I2C_TypeDef *I2Cx, uint32_t AddressingMode)
Configure the Master to operate in 7-bit or 10-bit addressing mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMasterAddressingMode (I2C_TypeDef *I2Cx)
Get the Master addressing mode.
__STATIC_INLINE void | LL_I2C_SetOwnAddress1 (I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
Set the Own Address1.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress1 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address1 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress1 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address1 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress1 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetOwnAddress2 (I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
Set the 7bits Own Address2.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress2 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address2 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress2 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address2 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress2 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTiming (I2C_TypeDef *I2Cx, uint32_t Timing)
Configure the SDA setup, hold time and the SCL high, low period.
__STATIC_INLINE uint32_t | LL_I2C_GetTimingPrescaler (I2C_TypeDef *I2Cx)
Get the Timing Prescaler setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockLowPeriod (I2C_TypeDef *I2Cx)
Get the SCL low period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockHighPeriod (I2C_TypeDef *I2Cx)
Get the SCL high period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetDataHoldTime (I2C_TypeDef *I2Cx)
Get the SDA hold time.
__STATIC_INLINE uint32_t | LL_I2C_GetDataSetupTime (I2C_TypeDef *I2Cx)
Get the SDA setup time.
__STATIC_INLINE void | LL_I2C_SetMode (I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
Configure peripheral mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMode (I2C_TypeDef *I2Cx)
Get peripheral mode.
__STATIC_INLINE void | LL_I2C_EnableSMBusAlert (I2C_TypeDef *I2Cx)
Enable SMBus alert (Host or Device mode)
__STATIC_INLINE void | LL_I2C_DisableSMBusAlert (I2C_TypeDef *I2Cx)
Disable SMBus alert (Host or Device mode)
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusAlert (I2C_TypeDef *I2Cx)
Check if SMBus alert (Host or Device mode) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSMBusPEC (I2C_TypeDef *I2Cx)
Enable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE void | LL_I2C_DisableSMBusPEC (I2C_TypeDef *I2Cx)
Disable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPEC (I2C_TypeDef *I2Cx)
Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, uint32_t TimeoutB)
Configure the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutA (I2C_TypeDef *I2Cx, uint32_t TimeoutA)
Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutA (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA setting.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutAMode (I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
Set the SMBus Clock TimeoutA mode.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutAMode (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA mode.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutB (I2C_TypeDef *I2Cx, uint32_t TimeoutB)
Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutB (I2C_TypeDef *I2Cx)
Get the SMBus Extented Cumulative Clock TimeoutB setting.
__STATIC_INLINE void | LL_I2C_EnableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Enable the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_DisableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Disable the SMBus Clock Timeout.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Check if the SMBus Clock Timeout is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_I2C_ConfigFilters | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | AnalogFilter,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure Noise Filters (Analog and Digital).

Note:
If the analog filter is also enabled, the digital filter is added to analog filter. The filters can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_ConfigFilters
CR1 DNF LL_I2C_ConfigFilters
Parameters:
I2Cx | I2C Instance.
AnalogFilter This parameter can be one of the following values:
  • LL_I2C_ANALOGFILTER_ENABLE
  • LL_I2C_ANALOGFILTER_DISABLE
DigitalFilter | This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
Return values:
None

Definition at line 452 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutA,
 |  | uint32_t | TimeoutAMode,
 |  | uint32_t | TimeoutB
 | ) |  |

Configure the SMBus Clock Timeout.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout
TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout
TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
Parameters:
I2Cx | I2C Instance.
TimeoutA | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
TimeoutAMode This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
TimeoutB
Return values:
None

Definition at line 1099 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_Disable ( I2C_TypeDef * I2Cx )

Disable I2C peripheral (PE = 0).

Note:
When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
Reference Manual to LL API cross reference:
CR1 PE LL_I2C_Disable
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 421 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableAnalogFilter ( I2C_TypeDef * I2Cx )

Disable Analog Noise Filter.

Note:
This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_DisableAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 503 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableClockStretching ( I2C_TypeDef * I2Cx )

Disable Clock stretching.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_DisableClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 632 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableDMAReq_RX ( I2C_TypeDef * I2Cx )

Disable DMA reception requests.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 569 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableDMAReq_TX ( I2C_TypeDef * I2Cx )

Disable DMA transmission requests.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 536 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableGeneralCall ( I2C_TypeDef * I2Cx )

Disable General Call.

Note:
When disabled the Address 0x00 is NACKed.
Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_DisableGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 740 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableOwnAddress1 ( I2C_TypeDef * I2Cx )

Disable acknowledge on Own Address1 match address.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_DisableOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 817 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableOwnAddress2 ( I2C_TypeDef * I2Cx )

Disable acknowledge on Own Address2 match address.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_DisableOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 873 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSlaveByteControl ( I2C_TypeDef * I2Cx )

Disable hardware byte control in slave mode.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_DisableSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 665 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusAlert ( I2C_TypeDef * I2Cx )

Disable SMBus alert (Host or Device mode)

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
SMBus Device mode:
  • SMBus Alert pin is not drived (can be used as a standard GPIO) and Alert Response Address Header acknowledge is disabled. SMBus Host mode:
  • SMBus Alert pin management is not supported.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_DisableSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1026 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusPEC ( I2C_TypeDef * I2Cx )

Disable SMBus Packet Error Calculation (PEC).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_DisableSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1065 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Disable the SMBus Clock Timeout.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
None

Definition at line 1225 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop ( I2C_TypeDef * I2Cx )

Disable Wakeup from STOP.

Note:
Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_DisableWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 703 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | Direction
 | ) |  |

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
TXDR TXDATA LL_I2C_DMA_GetRegAddr
RXDR RXDATA LL_I2C_DMA_GetRegAddr
Parameters:
I2Cx I2C Instance
Direction This parameter can be one of the following values:
  • LL_I2C_DMA_REG_DATA_TRANSMIT
  • LL_I2C_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 595 of file stm32f3xx_ll_i2c.h.

References LL_I2C_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_I2C_Enable ( I2C_TypeDef * I2Cx )

Enable I2C peripheral (PE = 1).

Reference Manual to LL API cross reference:
CR1 PE LL_I2C_Enable
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 407 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_EnableAnalogFilter ( I2C_TypeDef * I2Cx )

Enable Analog Noise Filter.

Note:
This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_EnableAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 491 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableClockStretching ( I2C_TypeDef * I2Cx )

Enable Clock stretching.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_EnableClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 620 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableDMAReq_RX ( I2C_TypeDef * I2Cx )

Enable DMA reception requests.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 558 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableDMAReq_TX ( I2C_TypeDef * I2Cx )

Enable DMA transmission requests.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 525 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableGeneralCall ( I2C_TypeDef * I2Cx )

Enable General Call.

Note:
When enabled the Address 0x00 is ACKed.
Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_EnableGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 728 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableOwnAddress1 ( I2C_TypeDef * I2Cx )

Enable acknowledge on Own Address1 match address.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_EnableOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 806 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_EnableOwnAddress2 ( I2C_TypeDef * I2Cx )

Enable acknowledge on Own Address2 match address.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_EnableOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 862 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSlaveByteControl ( I2C_TypeDef * I2Cx )

Enable hardware byte control in slave mode.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_EnableSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 654 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusAlert ( I2C_TypeDef * I2Cx )

Enable SMBus alert (Host or Device mode)

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
SMBus Device mode:
  • SMBus Alert pin is drived low and Alert Response Address Header acknowledge is enabled. SMBus Host mode:
  • SMBus Alert pin management is supported.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_EnableSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1008 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusPEC ( I2C_TypeDef * I2Cx )

Enable SMBus Packet Error Calculation (PEC).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_EnableSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1052 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Enable the SMBus Clock Timeout.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
None

Definition at line 1207 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop ( I2C_TypeDef * I2Cx )

Enable Wakeup from STOP.

Note:
Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
This bit can only be programmed when Digital Filter is disabled.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_EnableWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 690 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod ( I2C_TypeDef * I2Cx )

Get the SCL high period setting.

Reference Manual to LL API cross reference:
TIMINGR SCLH LL_I2C_GetClockHighPeriod
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 931 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod ( I2C_TypeDef * I2Cx )

Get the SCL low period setting.

Reference Manual to LL API cross reference:
TIMINGR SCLL LL_I2C_GetClockLowPeriod
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 920 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime ( I2C_TypeDef * I2Cx )

Get the SDA hold time.

Reference Manual to LL API cross reference:
TIMINGR SDADEL LL_I2C_GetDataHoldTime
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 942 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime ( I2C_TypeDef * I2Cx )

Get the SDA setup time.

Reference Manual to LL API cross reference:
TIMINGR SCLDEL LL_I2C_GetDataSetupTime
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 953 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter ( I2C_TypeDef * I2Cx )

Get the current Digital Noise Filter configuration.

Reference Manual to LL API cross reference:
CR1 DNF LL_I2C_GetDigitalFilter
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 479 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode ( I2C_TypeDef * I2Cx )

Get the Master addressing mode.

Reference Manual to LL API cross reference:
CR2 ADD10 LL_I2C_GetMasterAddressingMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_ADDRESSING_MODE_7BIT
  • LL_I2C_ADDRESSING_MODE_10BIT

Definition at line 779 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetMode ( I2C_TypeDef * I2Cx )

Get peripheral mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 SMBHEN LL_I2C_GetMode
CR1 SMBDEN LL_I2C_GetMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_MODE_I2C
  • LL_I2C_MODE_SMBUS_HOST
  • LL_I2C_MODE_SMBUS_DEVICE
  • LL_I2C_MODE_SMBUS_DEVICE_ARP

Definition at line 990 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA ( I2C_TypeDef * I2Cx )

Get the SMBus Clock TimeoutA setting.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0 and Max_Data=0xFFF

Definition at line 1129 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode ( I2C_TypeDef * I2Cx )

Get the SMBus Clock TimeoutA mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH

Definition at line 1161 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB ( I2C_TypeDef * I2Cx )

Get the SMBus Extented Cumulative Clock TimeoutB setting.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0 and Max_Data=0xFFF

Definition at line 1189 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler ( I2C_TypeDef * I2Cx )

Get the Timing Prescaler setting.

Reference Manual to LL API cross reference:
TIMINGR PRESC LL_I2C_GetTimingPrescaler
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 909 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabled ( I2C_TypeDef * I2Cx )

Check if the I2C peripheral is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PE LL_I2C_IsEnabled
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 432 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter ( I2C_TypeDef * I2Cx )

Check if Analog Noise Filter is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 514 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching ( I2C_TypeDef * I2Cx )

Check if Clock stretching is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 643 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX ( I2C_TypeDef * I2Cx )

Check if DMA reception requests are enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 580 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX ( I2C_TypeDef * I2Cx )

Check if DMA transmission requests are enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 547 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall ( I2C_TypeDef * I2Cx )

Check if General Call is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_IsEnabledGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 751 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1 ( I2C_TypeDef * I2Cx )

Check if Own Address1 acknowledge is enabled or disabled.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 828 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2 ( I2C_TypeDef * I2Cx )

Check if Own Address1 acknowledge is enabled or disabled.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 884 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl ( I2C_TypeDef * I2Cx )

Check if hardware byte control in slave mode is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_IsEnabledSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 676 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert ( I2C_TypeDef * I2Cx )

Check if SMBus alert (Host or Device mode) is enabled or disabled.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1039 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC ( I2C_TypeDef * I2Cx )

Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_IsEnabledSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1078 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Check if the SMBus Clock Timeout is enabled or disabled.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
State of bit (1 or 0).

Definition at line 1243 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop ( I2C_TypeDef * I2Cx )

Check if Wakeup from STOP is enabled or disabled.

Note:
Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 716 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetDigitalFilter | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure Digital Noise Filter.

Note:
If the analog filter is also enabled, the digital filter is added to analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 DNF LL_I2C_SetDigitalFilter
Parameters:
I2Cx | I2C Instance.
DigitalFilter | This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
Return values:
None

Definition at line 468 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetMasterAddressingMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | AddressingMode
 | ) |  |

Configure the Master to operate in 7-bit or 10-bit addressing mode.

Note:
Changing this bit is not allowed, when the START bit is set.
Reference Manual to LL API cross reference:
CR2 ADD10 LL_I2C_SetMasterAddressingMode
Parameters:
I2Cx I2C Instance.
AddressingMode This parameter can be one of the following values:
  • LL_I2C_ADDRESSING_MODE_7BIT
  • LL_I2C_ADDRESSING_MODE_10BIT
Return values:
None

Definition at line 766 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | PeripheralMode
 | ) |  |

Configure peripheral mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 SMBHEN LL_I2C_SetMode
CR1 SMBDEN LL_I2C_SetMode
Parameters:
I2Cx I2C Instance.
PeripheralMode This parameter can be one of the following values:
  • LL_I2C_MODE_I2C
  • LL_I2C_MODE_SMBUS_HOST
  • LL_I2C_MODE_SMBUS_DEVICE
  • LL_I2C_MODE_SMBUS_DEVICE_ARP
Return values:
None

Definition at line 972 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_SetOwnAddress1 | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | OwnAddress1,
 |  | uint32_t | OwnAddrSize
 | ) |  |

Set the Own Address1.

Reference Manual to LL API cross reference:
OAR1 OA1 LL_I2C_SetOwnAddress1
OAR1 OA1MODE LL_I2C_SetOwnAddress1
Parameters:
I2Cx | I2C Instance.
OwnAddress1 | This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
OwnAddrSize This parameter can be one of the following values:
  • LL_I2C_OWNADDRESS1_7BIT
  • LL_I2C_OWNADDRESS1_10BIT
Return values:
None

Definition at line 795 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_SetOwnAddress2 | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | OwnAddress2,
 |  | uint32_t | OwnAddrMask
 | ) |  |

Set the 7bits Own Address2.

Note:
This action has no effect if own address2 is enabled.
Reference Manual to LL API cross reference:
OAR2 OA2 LL_I2C_SetOwnAddress2
OAR2 OA2MSK LL_I2C_SetOwnAddress2
Parameters:
I2Cx | I2C Instance.
OwnAddress2 | Value between Min_Data=0 and Max_Data=0x7F.
OwnAddrMask This parameter can be one of the following values:
  • LL_I2C_OWNADDRESS2_NOMASK
  • LL_I2C_OWNADDRESS2_MASK01
  • LL_I2C_OWNADDRESS2_MASK02
  • LL_I2C_OWNADDRESS2_MASK03
  • LL_I2C_OWNADDRESS2_MASK04
  • LL_I2C_OWNADDRESS2_MASK05
  • LL_I2C_OWNADDRESS2_MASK06
  • LL_I2C_OWNADDRESS2_MASK07
Return values:
None

Definition at line 851 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutA
 | ) |  |

Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
These bits can only be programmed when TimeoutA is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
Parameters:
I2Cx | I2C Instance.
TimeoutA | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
Return values:
None

Definition at line 1116 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutAMode
 | ) |  |

Set the SMBus Clock TimeoutA mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This bit can only be programmed when TimeoutA is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
Parameters:
I2Cx I2C Instance.
TimeoutAMode This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
Return values:
None

Definition at line 1146 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutB
 | ) |  |

Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
These bits can only be programmed when TimeoutB is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
Parameters:
I2Cx | I2C Instance.
TimeoutB | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
Return values:
None

Definition at line 1176 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetTiming | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | Timing
 | ) |  |

Configure the SDA setup, hold time and the SCL high, low period.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
TIMINGR TIMINGR LL_I2C_SetTiming
Parameters:
I2Cx | I2C Instance.
Timing | This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
Note:
This parameter is computed with the STM32CubeMX Tool.
Return values:
None

Definition at line 898 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_Init().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IT_Management

Functions
IT_Management
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_EnableIT_TX (I2C_TypeDef *I2Cx)
Enable TXIS interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TX (I2C_TypeDef *I2Cx)
Disable TXIS interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TX (I2C_TypeDef *I2Cx)
Check if the TXIS Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_RX (I2C_TypeDef *I2Cx)
Enable RXNE interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_RX (I2C_TypeDef *I2Cx)
Disable RXNE interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_RX (I2C_TypeDef *I2Cx)
Check if the RXNE Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ADDR (I2C_TypeDef *I2Cx)
Enable Address match interrupt (slave mode only).
__STATIC_INLINE void | LL_I2C_DisableIT_ADDR (I2C_TypeDef *I2Cx)
Disable Address match interrupt (slave mode only).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ADDR (I2C_TypeDef *I2Cx)
Check if Address match interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_NACK (I2C_TypeDef *I2Cx)
Enable Not acknowledge received interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_NACK (I2C_TypeDef *I2Cx)
Disable Not acknowledge received interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_NACK (I2C_TypeDef *I2Cx)
Check if Not acknowledge received interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_STOP (I2C_TypeDef *I2Cx)
Enable STOP detection interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_STOP (I2C_TypeDef *I2Cx)
Disable STOP detection interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_STOP (I2C_TypeDef *I2Cx)
Check if STOP detection interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TC (I2C_TypeDef *I2Cx)
Enable Transfer Complete interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TC (I2C_TypeDef *I2Cx)
Disable Transfer Complete interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TC (I2C_TypeDef *I2Cx)
Check if Transfer Complete interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ERR (I2C_TypeDef *I2Cx)
Enable Error interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_ERR (I2C_TypeDef *I2Cx)
Disable Error interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ERR (I2C_TypeDef *I2Cx)
Check if Error interrupts are enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_I2C_DisableIT_ADDR ( I2C_TypeDef * I2Cx )

Disable Address match interrupt (slave mode only).

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_DisableIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1339 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_ERR ( I2C_TypeDef * I2Cx )

Disable Error interrupts.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Any of these errors will generate interrupt : Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) SMBus Timeout detection (TIMEOUT) SMBus PEC error detection (PECERR) SMBus Alert pin event detection (ALERT)
Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_DisableIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1495 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_NACK ( I2C_TypeDef * I2Cx )

Disable Not acknowledge received interrupt.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_DisableIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1372 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_RX ( I2C_TypeDef * I2Cx )

Disable RXNE interrupt.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_DisableIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1306 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_STOP ( I2C_TypeDef * I2Cx )

Disable STOP detection interrupt.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_DisableIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1405 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_TC ( I2C_TypeDef * I2Cx )

Disable Transfer Complete interrupt.

Note:
Any of these events will generate interrupt : Transfer Complete (TC) Transfer Complete Reload (TCR)
Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_DisableIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1444 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_TX ( I2C_TypeDef * I2Cx )

Disable TXIS interrupt.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_DisableIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1273 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_ADDR ( I2C_TypeDef * I2Cx )

Enable Address match interrupt (slave mode only).

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_EnableIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1328 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_ERR ( I2C_TypeDef * I2Cx )

Enable Error interrupts.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Any of these errors will generate interrupt : Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) SMBus Timeout detection (TIMEOUT) SMBus PEC error detection (PECERR) SMBus Alert pin event detection (ALERT)
Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_EnableIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1475 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_NACK ( I2C_TypeDef * I2Cx )

Enable Not acknowledge received interrupt.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_EnableIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1361 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_RX ( I2C_TypeDef * I2Cx )

Enable RXNE interrupt.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_EnableIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1295 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_STOP ( I2C_TypeDef * I2Cx )

Enable STOP detection interrupt.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_EnableIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1394 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_TC ( I2C_TypeDef * I2Cx )

Enable Transfer Complete interrupt.

Note:
Any of these events will generate interrupt : Transfer Complete (TC) Transfer Complete Reload (TCR)
Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_EnableIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1430 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_TX ( I2C_TypeDef * I2Cx )

Enable TXIS interrupt.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_EnableIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1262 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR ( I2C_TypeDef * I2Cx )

Check if Address match interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1350 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR ( I2C_TypeDef * I2Cx )

Check if Error interrupts are enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_IsEnabledIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1506 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK ( I2C_TypeDef * I2Cx )

Check if Not acknowledge received interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_IsEnabledIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1383 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX ( I2C_TypeDef * I2Cx )

Check if the RXNE Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_IsEnabledIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1317 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP ( I2C_TypeDef * I2Cx )

Check if STOP detection interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_IsEnabledIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1416 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC ( I2C_TypeDef * I2Cx )

Check if Transfer Complete interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_IsEnabledIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1455 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX ( I2C_TypeDef * I2Cx )

Check if the TXIS Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_IsEnabledIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1284 of file stm32f3xx_ll_i2c.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLAG_management

Functions
FLAG_management
I2C Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXE (I2C_TypeDef *I2Cx)
Indicate the status of Transmit data register empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXIS (I2C_TypeDef *I2Cx)
Indicate the status of Transmit interrupt flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_RXNE (I2C_TypeDef *I2Cx)
Indicate the status of Receive data register not empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ADDR (I2C_TypeDef *I2Cx)
Indicate the status of Address matched flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_NACK (I2C_TypeDef *I2Cx)
Indicate the status of Not Acknowledge received flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_STOP (I2C_TypeDef *I2Cx)
Indicate the status of Stop detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TC (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TCR (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BERR (I2C_TypeDef *I2Cx)
Indicate the status of Bus error flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ARLO (I2C_TypeDef *I2Cx)
Indicate the status of Arbitration lost flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_OVR (I2C_TypeDef *I2Cx)
Indicate the status of Overrun/Underrun flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Indicate the status of SMBus PEC error flag in reception.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus Timeout detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus alert flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BUSY (I2C_TypeDef *I2Cx)
Indicate the status of Bus Busy flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ADDR (I2C_TypeDef *I2Cx)
Clear Address Matched flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_NACK (I2C_TypeDef *I2Cx)
Clear Not Acknowledge flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_STOP (I2C_TypeDef *I2Cx)
Clear Stop detection flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_TXE (I2C_TypeDef *I2Cx)
Clear Transmit data register empty flag (TXE).
__STATIC_INLINE void | LL_I2C_ClearFlag_BERR (I2C_TypeDef *I2Cx)
Clear Bus error flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ARLO (I2C_TypeDef *I2Cx)
Clear Arbitration lost flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_OVR (I2C_TypeDef *I2Cx)
Clear Overrun/Underrun flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Clear SMBus PEC error flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Clear SMBus Timeout detection flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Clear SMBus Alert flag.

Function Documentation

__STATIC_INLINE void LL_I2C_ClearFlag_ADDR ( I2C_TypeDef * I2Cx )

Clear Address Matched flag.

Reference Manual to LL API cross reference:
ICR ADDRCF LL_I2C_ClearFlag_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1727 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_ARLO ( I2C_TypeDef * I2Cx )

Clear Arbitration lost flag.

Reference Manual to LL API cross reference:
ICR ARLOCF LL_I2C_ClearFlag_ARLO
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1783 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_BERR ( I2C_TypeDef * I2Cx )

Clear Bus error flag.

Reference Manual to LL API cross reference:
ICR BERRCF LL_I2C_ClearFlag_BERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1772 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_NACK ( I2C_TypeDef * I2Cx )

Clear Not Acknowledge flag.

Reference Manual to LL API cross reference:
ICR NACKCF LL_I2C_ClearFlag_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1738 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_OVR ( I2C_TypeDef * I2Cx )

Clear Overrun/Underrun flag.

Reference Manual to LL API cross reference:
ICR OVRCF LL_I2C_ClearFlag_OVR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1794 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_STOP ( I2C_TypeDef * I2Cx )

Clear Stop detection flag.

Reference Manual to LL API cross reference:
ICR STOPCF LL_I2C_ClearFlag_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1749 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_TXE ( I2C_TypeDef * I2Cx )

Clear Transmit data register empty flag (TXE).

Note:
This bit can be clear by software in order to flush the transmit data register (TXDR).
Reference Manual to LL API cross reference:
ISR TXE LL_I2C_ClearFlag_TXE
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1761 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT ( I2C_TypeDef * I2Cx )

Clear SMBus Alert flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1833 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR ( I2C_TypeDef * I2Cx )

Clear SMBus PEC error flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1807 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT ( I2C_TypeDef * I2Cx )

Clear SMBus Timeout detection flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1820 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR ( I2C_TypeDef * I2Cx )

Indicate the status of Address matched flag (slave mode).

Note:
RESET: Clear default value. SET: When the received slave address matched with one of the enabled slave address.
Reference Manual to LL API cross reference:
ISR ADDR LL_I2C_IsActiveFlag_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1566 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO ( I2C_TypeDef * I2Cx )

Indicate the status of Arbitration lost flag.

Note:
RESET: Clear default value. SET: When arbitration lost.
Reference Manual to LL API cross reference:
ISR ARLO LL_I2C_IsActiveFlag_ARLO
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1644 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR ( I2C_TypeDef * I2Cx )

Indicate the status of Bus error flag.

Note:
RESET: Clear default value. SET: When a misplaced Start or Stop condition is detected.
Reference Manual to LL API cross reference:
ISR BERR LL_I2C_IsActiveFlag_BERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1631 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY ( I2C_TypeDef * I2Cx )

Indicate the status of Bus Busy flag.

Note:
RESET: Clear default value. SET: When a Start condition is detected.
Reference Manual to LL API cross reference:
ISR BUSY LL_I2C_IsActiveFlag_BUSY
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1716 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK ( I2C_TypeDef * I2Cx )

Indicate the status of Not Acknowledge received flag.

Note:
RESET: Clear default value. SET: When a NACK is received after a byte transmission.
Reference Manual to LL API cross reference:
ISR NACKF LL_I2C_IsActiveFlag_NACK
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1579 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR ( I2C_TypeDef * I2Cx )

Indicate the status of Overrun/Underrun flag (slave mode).

Note:
RESET: Clear default value. SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
Reference Manual to LL API cross reference:
ISR OVR LL_I2C_IsActiveFlag_OVR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1657 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE ( I2C_TypeDef * I2Cx )

Indicate the status of Receive data register not empty flag.

Note:
RESET: When Receive data register is read. SET: When the received data is copied in Receive data register.
Reference Manual to LL API cross reference:
ISR RXNE LL_I2C_IsActiveFlag_RXNE
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1553 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP ( I2C_TypeDef * I2Cx )

Indicate the status of Stop detection flag.

Note:
RESET: Clear default value. SET: When a Stop condition is detected.
Reference Manual to LL API cross reference:
ISR STOPF LL_I2C_IsActiveFlag_STOP
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1592 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC ( I2C_TypeDef * I2Cx )

Indicate the status of Transfer complete flag (master mode).

Note:
RESET: Clear default value. SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
Reference Manual to LL API cross reference:
ISR TC LL_I2C_IsActiveFlag_TC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1605 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR ( I2C_TypeDef * I2Cx )

Indicate the status of Transfer complete flag (master mode).

Note:
RESET: Clear default value. SET: When RELOAD=1 and NBYTES date have been transferred.
Reference Manual to LL API cross reference:
ISR TCR LL_I2C_IsActiveFlag_TCR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1618 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE ( I2C_TypeDef * I2Cx )

Indicate the status of Transmit data register empty flag.

Note:
RESET: When next data is written in Transmit data register. SET: When Transmit data register is empty.
Reference Manual to LL API cross reference:
ISR TXE LL_I2C_IsActiveFlag_TXE
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1527 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS ( I2C_TypeDef * I2Cx )

Indicate the status of Transmit interrupt flag.

Note:
RESET: When next data is written in Transmit data register. SET: When Transmit data register is empty.
Reference Manual to LL API cross reference:
ISR TXIS LL_I2C_IsActiveFlag_TXIS
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1540 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus alert flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When SMBus host configuration, SMBus alert enabled and a falling edge event occurs on SMBA pin.
Reference Manual to LL API cross reference:
ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1703 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus PEC error flag in reception.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When the received PEC does not match with the PEC register content.
Reference Manual to LL API cross reference:
ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1672 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus Timeout detection flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When a timeout or extended clock timeout occurs.
Reference Manual to LL API cross reference:
ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1687 of file stm32f3xx_ll_i2c.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data_Management

Functions
Data_Management
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_EnableAutoEndMode (I2C_TypeDef *I2Cx)
Enable automatic STOP condition generation (master mode).
__STATIC_INLINE void | LL_I2C_DisableAutoEndMode (I2C_TypeDef *I2Cx)
Disable automatic STOP condition generation (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAutoEndMode (I2C_TypeDef *I2Cx)
Check if automatic STOP condition is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableReloadMode (I2C_TypeDef *I2Cx)
Enable reload mode (master mode).
__STATIC_INLINE void | LL_I2C_DisableReloadMode (I2C_TypeDef *I2Cx)
Disable reload mode (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledReloadMode (I2C_TypeDef *I2Cx)
Check if reload mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferSize (I2C_TypeDef *I2Cx, uint32_t TransferSize)
Configure the number of bytes for transfer.
__STATIC_INLINE uint32_t | LL_I2C_GetTransferSize (I2C_TypeDef *I2Cx)
Get the number of bytes configured for transfer.
__STATIC_INLINE void | LL_I2C_AcknowledgeNextData (I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
__STATIC_INLINE void | LL_I2C_GenerateStartCondition (I2C_TypeDef *I2Cx)
Generate a START or RESTART condition.
__STATIC_INLINE void | LL_I2C_GenerateStopCondition (I2C_TypeDef *I2Cx)
Generate a STOP condition after the current byte transfer (master mode).
__STATIC_INLINE void | LL_I2C_EnableAuto10BitRead (I2C_TypeDef *I2Cx)
Enable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE void | LL_I2C_DisableAuto10BitRead (I2C_TypeDef *I2Cx)
Disable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAuto10BitRead (I2C_TypeDef *I2Cx)
Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferRequest (I2C_TypeDef *I2Cx, uint32_t TransferRequest)
Configure the transfer direction (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferRequest (I2C_TypeDef *I2Cx)
Get the transfer direction requested (master mode).
__STATIC_INLINE void | LL_I2C_SetSlaveAddr (I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
Configure the slave address for transfer (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSlaveAddr (I2C_TypeDef *I2Cx)
Get the slave address programmed for transfer.
__STATIC_INLINE void | LL_I2C_HandleTransfer (I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferDirection (I2C_TypeDef *I2Cx)
Indicate the value of transfer direction (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetAddressMatchCode (I2C_TypeDef *I2Cx)
Return the slave matched address.
__STATIC_INLINE void | LL_I2C_EnableSMBusPECCompare (I2C_TypeDef *I2Cx)
Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPECCompare (I2C_TypeDef *I2Cx)
Check if the SMBus Packet Error byte internal comparison is requested or not.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusPEC (I2C_TypeDef *I2Cx)
Get the SMBus Packet Error byte calculated.
__STATIC_INLINE uint8_t | LL_I2C_ReceiveData8 (I2C_TypeDef *I2Cx)
Read Receive Data register.
__STATIC_INLINE void | LL_I2C_TransmitData8 (I2C_TypeDef *I2Cx, uint8_t Data)
Write in Transmit Data Register .

Function Documentation

__STATIC_INLINE void LL_I2C_AcknowledgeNextData | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TypeAcknowledge
 | ) |  |

Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.

Note:
Usage in Slave mode only.
Reference Manual to LL API cross reference:
CR2 NACK LL_I2C_AcknowledgeNextData
Parameters:
I2Cx I2C Instance.
TypeAcknowledge This parameter can be one of the following values:
  • LL_I2C_ACK
  • LL_I2C_NACK
Return values:
None

Definition at line 1951 of file stm32f3xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableAuto10BitRead ( I2C_TypeDef * I2Cx )

Disable automatic RESTART Read request condition for 10bit address header (master mode).

Note:
The master only sends the first 7 bits of 10bit address in Read direction.
Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_DisableAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 2000 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableAutoEndMode ( I2C_TypeDef * I2Cx )

Disable automatic STOP condition generation (master mode).

Note:
Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_DisableAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1866 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableReloadMode ( I2C_TypeDef * I2Cx )

Disable reload mode (master mode).

Note:
The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_DisableReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1901 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableAuto10BitRead ( I2C_TypeDef * I2Cx )

Enable automatic RESTART Read request condition for 10bit address header (master mode).

Note:
The master sends the complete 10bit slave address read sequence : Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_EnableAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1988 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableAutoEndMode ( I2C_TypeDef * I2Cx )

Enable automatic STOP condition generation (master mode).

Note:
Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. This bit has no effect in slave mode or when RELOAD bit is set.
Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_EnableAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1854 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableReloadMode ( I2C_TypeDef * I2Cx )

Enable reload mode (master mode).

Note:
The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_EnableReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1889 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare ( I2C_TypeDef * I2Cx )

Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. This bit has no effect when RELOAD bit is set. This bit has no effect in device mode when SBC bit is not set.
Reference Manual to LL API cross reference:
CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 2151 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_GenerateStartCondition ( I2C_TypeDef * I2Cx )

Generate a START or RESTART condition.

Note:
The START bit can be set even if bus is BUSY or I2C is in slave mode. This action has no effect when RELOAD is set.
Reference Manual to LL API cross reference:
CR2 START LL_I2C_GenerateStartCondition
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1964 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_GenerateStopCondition ( I2C_TypeDef * I2Cx )

Generate a STOP condition after the current byte transfer (master mode).

Reference Manual to LL API cross reference:
CR2 STOP LL_I2C_GenerateStopCondition
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1975 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode ( I2C_TypeDef * I2Cx )

Return the slave matched address.

Reference Manual to LL API cross reference:
ISR ADDCODE LL_I2C_GetAddressMatchCode
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0x3F

Definition at line 2135 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr ( I2C_TypeDef * I2Cx )

Get the slave address programmed for transfer.

Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_GetSlaveAddr
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0x3F

Definition at line 2063 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC ( I2C_TypeDef * I2Cx )

Get the SMBus Packet Error byte calculated.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
PECR PEC LL_I2C_GetSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2177 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection ( I2C_TypeDef * I2Cx )

Indicate the value of transfer direction (slave mode).

Note:
RESET: Write transfer, Slave enters in receiver mode. SET: Read transfer, Slave enters in transmitter mode.
Reference Manual to LL API cross reference:
ISR DIR LL_I2C_GetTransferDirection
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_DIRECTION_WRITE
  • LL_I2C_DIRECTION_READ

Definition at line 2124 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest ( I2C_TypeDef * I2Cx )

Get the transfer direction requested (master mode).

Reference Manual to LL API cross reference:
CR2 RD_WRN LL_I2C_GetTransferRequest
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_REQUEST_WRITE
  • LL_I2C_REQUEST_READ

Definition at line 2039 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferSize ( I2C_TypeDef * I2Cx )

Get the number of bytes configured for transfer.

Reference Manual to LL API cross reference:
CR2 NBYTES LL_I2C_GetTransferSize
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xFF

Definition at line 1936 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_HandleTransfer | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | SlaveAddr,
 |  | uint32_t | SlaveAddrSize,
 |  | uint32_t | TransferSize,
 |  | uint32_t | EndMode,
 |  | uint32_t | Request
 | ) |  |

Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_HandleTransfer
CR2 ADD10 LL_I2C_HandleTransfer
CR2 RD_WRN LL_I2C_HandleTransfer
CR2 START LL_I2C_HandleTransfer
CR2 STOP LL_I2C_HandleTransfer
CR2 RELOAD LL_I2C_HandleTransfer
CR2 NBYTES LL_I2C_HandleTransfer
CR2 AUTOEND LL_I2C_HandleTransfer
CR2 HEAD10R LL_I2C_HandleTransfer
Parameters:
I2Cx | I2C Instance.
SlaveAddr | Specifies the slave address to be programmed.
SlaveAddrSize This parameter can be one of the following values:
  • LL_I2C_ADDRSLAVE_7BIT
  • LL_I2C_ADDRSLAVE_10BIT
TransferSize | Specifies the number of bytes to be programmed. This parameter must be a value between Min_Data=0 and Max_Data=255.
EndMode This parameter can be one of the following values:
  • LL_I2C_MODE_RELOAD
  • LL_I2C_MODE_AUTOEND
  • LL_I2C_MODE_SOFTEND
  • LL_I2C_MODE_SMBUS_RELOAD
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
Request This parameter can be one of the following values:
  • LL_I2C_GENERATE_NOSTARTSTOP
  • LL_I2C_GENERATE_STOP
  • LL_I2C_GENERATE_START_READ
  • LL_I2C_GENERATE_START_WRITE
  • LL_I2C_GENERATE_RESTART_7BIT_READ
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE
  • LL_I2C_GENERATE_RESTART_10BIT_READ
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE
Return values:
None

Definition at line 2106 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead ( I2C_TypeDef * I2Cx )

Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 2011 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode ( I2C_TypeDef * I2Cx )

Check if automatic STOP condition is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1877 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode ( I2C_TypeDef * I2Cx )

Check if reload mode is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_IsEnabledReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1912 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare ( I2C_TypeDef * I2Cx )

Check if the SMBus Packet Error byte internal comparison is requested or not.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 2164 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE uint8_t LL_I2C_ReceiveData8 ( I2C_TypeDef * I2Cx )

Read Receive Data register.

Reference Manual to LL API cross reference:
RXDR RXDATA LL_I2C_ReceiveData8
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2188 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSlaveAddr | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | SlaveAddr
 | ) |  |

Configure the slave address for transfer (master mode).

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_SetSlaveAddr
Parameters:
I2Cx | I2C Instance.
SlaveAddr | This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
Return values:
None

Definition at line 2052 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetTransferRequest | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TransferRequest
 | ) |  |

Configure the transfer direction (master mode).

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 RD_WRN LL_I2C_SetTransferRequest
Parameters:
I2Cx I2C Instance.
TransferRequest This parameter can be one of the following values:
  • LL_I2C_REQUEST_WRITE
  • LL_I2C_REQUEST_READ
Return values:
None

Definition at line 2026 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetTransferSize | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TransferSize
 | ) |  |

Configure the number of bytes for transfer.

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 NBYTES LL_I2C_SetTransferSize
Parameters:
I2Cx | I2C Instance.
TransferSize | This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
Return values:
None

Definition at line 1925 of file stm32f3xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_TransmitData8 | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Data
 | ) |  |

Write in Transmit Data Register .

Reference Manual to LL API cross reference:
TXDR TXDATA LL_I2C_TransmitData8
Parameters:
I2Cx | I2C Instance.
Data | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2200 of file stm32f3xx_ll_i2c.h.

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STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2C Exported Functions

Functions

uint32_t | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
uint32_t | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Function Documentation

uint32_t LL_I2C_DeInit ( I2C_TypeDef * I2Cx )

De-initialize the I2C registers to their default reset values.

Parameters:
I2Cx I2C Instance.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: I2C registers are de-initialized
  • ERROR: I2C registers are not de-initialized

Definition at line 103 of file stm32f3xx_ll_i2c.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_I2C1, LL_APB1_GRP1_PERIPH_I2C2, and LL_APB1_GRP1_ReleaseReset().

uint32_t LL_I2C_Init | ( | I2C_TypeDef * | I2Cx,
 |  | LL_I2C_InitTypeDef * | I2C_InitStruct
 | ) |  |

Initialize the I2C registers according to the specified parameters in I2C_InitStruct.

Parameters:
I2Cx | I2C Instance.
I2C_InitStruct | pointer to a LL_I2C_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: I2C registers are initialized
  • ERROR: Not applicable

Definition at line 155 of file stm32f3xx_ll_i2c.c.

References LL_I2C_InitTypeDef::AnalogFilter, assert_param, LL_I2C_InitTypeDef::DigitalFilter, IS_LL_I2C_ANALOG_FILTER, IS_LL_I2C_DIGITAL_FILTER, IS_LL_I2C_OWN_ADDRESS1, IS_LL_I2C_OWN_ADDRSIZE, IS_LL_I2C_PERIPHERAL_MODE, IS_LL_I2C_TYPE_ACKNOWLEDGE, LL_I2C_AcknowledgeNextData(), LL_I2C_ConfigFilters(), LL_I2C_Disable(), LL_I2C_DisableOwnAddress1(), LL_I2C_Enable(), LL_I2C_EnableOwnAddress1(), LL_I2C_SetMode(), LL_I2C_SetOwnAddress1(), LL_I2C_SetTiming(), LL_I2C_InitTypeDef::OwnAddress1, LL_I2C_InitTypeDef::OwnAddrSize, LL_I2C_InitTypeDef::PeripheralMode, LL_I2C_InitTypeDef::Timing, and LL_I2C_InitTypeDef::TypeAcknowledge.

void LL_I2C_StructInit ( LL_I2C_InitTypeDef * I2C_InitStruct )

Set each LL_I2C_InitTypeDef field to default value.

Parameters:
I2C_InitStruct Pointer to a LL_I2C_InitTypeDef structure.
Return values:
None

Definition at line 223 of file stm32f3xx_ll_i2c.c.

References LL_I2C_InitTypeDef::AnalogFilter, LL_I2C_InitTypeDef::DigitalFilter, LL_I2C_ANALOGFILTER_ENABLE, LL_I2C_MODE_I2C, LL_I2C_NACK, LL_I2C_OWNADDRESS1_7BIT, LL_I2C_InitTypeDef::OwnAddress1, LL_I2C_InitTypeDef::OwnAddrSize, LL_I2C_InitTypeDef::PeripheralMode, LL_I2C_InitTypeDef::Timing, and LL_I2C_InitTypeDef::TypeAcknowledge.

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STM32F373xC HAL User Manual: IWDG

Modules
IWDG
STM32F3xx_LL_Driver

Modules

IWDG Private Constants
IWDG Exported Constants
IWDG Exported Macros
IWDG Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for IWDG registers.

Register | Bit | Function
KR | KEY | LL_IWDG_DisableWriteAccess
 |  | LL_IWDG_Enable
 |  | LL_IWDG_EnableWriteAccess
 |  | LL_IWDG_ReloadCounter
PR | PR | LL_IWDG_GetPrescaler
 |  | LL_IWDG_SetPrescaler
RLR | RL | LL_IWDG_GetReloadCounter
 |  | LL_IWDG_SetReloadCounter
SR | PVU | LL_IWDG_IsActiveFlag_PVU
 |  | LL_IWDG_IsReady
 | RVU | LL_IWDG_IsActiveFlag_RVU
 |  | LL_IWDG_IsReady
 | WVU | LL_IWDG_IsActiveFlag_WVU
 |  | LL_IWDG_IsReady
WINR | WIN | LL_IWDG_GetWindow
 |  | LL_IWDG_SetWindow
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IWDG Private Constants

Defines
IWDG Private Constants
IWDG

Defines

#define | LL_IWDG_KEY_RELOAD 0x0000AAAAU
#define | LL_IWDG_KEY_ENABLE 0x0000CCCCU
#define | LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U
#define | LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U

Define Documentation

#define LL_IWDG_KEY_ENABLE 0x0000CCCCU

IWDG Peripheral Enable

Definition at line 66 of file stm32f3xx_ll_iwdg.h.

Referenced by LL_IWDG_Enable().

#define LL_IWDG_KEY_RELOAD 0x0000AAAAU

IWDG Reload Counter Enable

Definition at line 65 of file stm32f3xx_ll_iwdg.h.

Referenced by LL_IWDG_ReloadCounter().

#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U

IWDG KR Write Access Disable

Definition at line 68 of file stm32f3xx_ll_iwdg.h.

Referenced by LL_IWDG_DisableWriteAccess().

#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U

IWDG KR Write Access Enable

Definition at line 67 of file stm32f3xx_ll_iwdg.h.

Referenced by LL_IWDG_EnableWriteAccess().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
IWDG Exported Constants

Flags defines which can be used with LL_IWDG_ReadReg function. More...

Defines

#define | LL_IWDG_SR_PVU IWDG_SR_PVU
#define | LL_IWDG_SR_RVU IWDG_SR_RVU
#define | LL_IWDG_SR_WVU IWDG_SR_WVU

Detailed Description

Flags defines which can be used with LL_IWDG_ReadReg function.

Define Documentation

#define LL_IWDG_SR_PVU IWDG_SR_PVU

Watchdog prescaler value update

Definition at line 86 of file stm32f3xx_ll_iwdg.h.

#define LL_IWDG_SR_RVU IWDG_SR_RVU

Watchdog counter reload value update

Definition at line 87 of file stm32f3xx_ll_iwdg.h.

#define LL_IWDG_SR_WVU IWDG_SR_WVU

Watchdog counter window value update

Definition at line 88 of file stm32f3xx_ll_iwdg.h.

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STM32F373xC HAL User Manual: Prescaler Divider

Defines
Prescaler Divider
IWDG Exported Constants

Defines

#define | LL_IWDG_PRESCALER_4 0x00000000U
#define | LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)
#define | LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)
#define | LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Define Documentation

#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)

Divider by 128

Definition at line 102 of file stm32f3xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)

Divider by 16

Definition at line 99 of file stm32f3xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Divider by 256

Definition at line 103 of file stm32f3xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)

Divider by 32

Definition at line 100 of file stm32f3xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_4 0x00000000U

Divider by 4

Definition at line 97 of file stm32f3xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)

Divider by 64

Definition at line 101 of file stm32f3xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)

Divider by 8

Definition at line 98 of file stm32f3xx_ll_iwdg.h.

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STM32F373xC HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
IWDG Exported Macros

Defines

#define | LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in IWDG register.
#define | LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in IWDG register.

Define Documentation

#define LL_IWDG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in IWDG register.

Parameters:
__INSTANCE__ | IWDG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 136 of file stm32f3xx_ll_iwdg.h.

#define LL_IWDG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in IWDG register.

Parameters:
__INSTANCE__ | IWDG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 128 of file stm32f3xx_ll_iwdg.h.

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STM32F373xC HAL User Manual: Configuration

Functions
Configuration
IWDG Exported Functions

Functions

__STATIC_INLINE void | LL_IWDG_Enable (IWDG_TypeDef *IWDGx)
Start the Independent Watchdog.
__STATIC_INLINE void | LL_IWDG_ReloadCounter (IWDG_TypeDef *IWDGx)
Reloads IWDG counter with value defined in the reload register.
__STATIC_INLINE void | LL_IWDG_EnableWriteAccess (IWDG_TypeDef *IWDGx)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_DisableWriteAccess (IWDG_TypeDef *IWDGx)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_SetPrescaler (IWDG_TypeDef *IWDGx, uint32_t Prescaler)
Select the prescaler of the IWDG.
__STATIC_INLINE uint32_t | LL_IWDG_GetPrescaler (IWDG_TypeDef *IWDGx)
Get the selected prescaler of the IWDG.
__STATIC_INLINE void | LL_IWDG_SetReloadCounter (IWDG_TypeDef *IWDGx, uint32_t Counter)
Specify the IWDG down-counter reload value.
__STATIC_INLINE uint32_t | LL_IWDG_GetReloadCounter (IWDG_TypeDef *IWDGx)
Get the specified IWDG down-counter reload value.
__STATIC_INLINE void | LL_IWDG_SetWindow (IWDG_TypeDef *IWDGx, uint32_t Window)
Specify high limit of the window value to be compared to the down-counter.
__STATIC_INLINE uint32_t | LL_IWDG_GetWindow (IWDG_TypeDef *IWDGx)
Get the high limit of the window value specified.

Function Documentation

__STATIC_INLINE void LL_IWDG_DisableWriteAccess ( IWDG_TypeDef * IWDGx )

Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_DisableWriteAccess
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 194 of file stm32f3xx_ll_iwdg.h.

References LL_IWDG_KEY_WR_ACCESS_DISABLE.

__STATIC_INLINE void LL_IWDG_Enable ( IWDG_TypeDef * IWDGx )

Start the Independent Watchdog.

Note:
Except if the hardware watchdog option is selected
Reference Manual to LL API cross reference:
KR KEY LL_IWDG_Enable
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 161 of file stm32f3xx_ll_iwdg.h.

References LL_IWDG_KEY_ENABLE.

__STATIC_INLINE void LL_IWDG_EnableWriteAccess ( IWDG_TypeDef * IWDGx )

Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_EnableWriteAccess
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 183 of file stm32f3xx_ll_iwdg.h.

References LL_IWDG_KEY_WR_ACCESS_ENABLE.

__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler ( IWDG_TypeDef * IWDGx )

Get the selected prescaler of the IWDG.

Reference Manual to LL API cross reference:
PR PR LL_IWDG_GetPrescaler
Parameters:
IWDGx IWDG Instance
Return values:
Returned value can be one of the following values:
  • LL_IWDG_PRESCALER_4
  • LL_IWDG_PRESCALER_8
  • LL_IWDG_PRESCALER_16
  • LL_IWDG_PRESCALER_32
  • LL_IWDG_PRESCALER_64
  • LL_IWDG_PRESCALER_128
  • LL_IWDG_PRESCALER_256

Definition at line 231 of file stm32f3xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter ( IWDG_TypeDef * IWDGx )

Get the specified IWDG down-counter reload value.

Reference Manual to LL API cross reference:
RLR RL LL_IWDG_GetReloadCounter
Parameters:
IWDGx IWDG Instance
Return values:
Value between Min_Data=0 and Max_Data=0x0FFF

Definition at line 254 of file stm32f3xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_GetWindow ( IWDG_TypeDef * IWDGx )

Get the high limit of the window value specified.

Reference Manual to LL API cross reference:
WINR WIN LL_IWDG_GetWindow
Parameters:
IWDGx IWDG Instance
Return values:
Value between Min_Data=0 and Max_Data=0x0FFF

Definition at line 277 of file stm32f3xx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_ReloadCounter ( IWDG_TypeDef * IWDGx )

Reloads IWDG counter with value defined in the reload register.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_ReloadCounter
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 172 of file stm32f3xx_ll_iwdg.h.

References LL_IWDG_KEY_RELOAD.

__STATIC_INLINE void LL_IWDG_SetPrescaler | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Prescaler
 | ) |  |

Select the prescaler of the IWDG.

Reference Manual to LL API cross reference:
PR PR LL_IWDG_SetPrescaler
Parameters:
IWDGx IWDG Instance
Prescaler This parameter can be one of the following values:
  • LL_IWDG_PRESCALER_4
  • LL_IWDG_PRESCALER_8
  • LL_IWDG_PRESCALER_16
  • LL_IWDG_PRESCALER_32
  • LL_IWDG_PRESCALER_64
  • LL_IWDG_PRESCALER_128
  • LL_IWDG_PRESCALER_256
Return values:
None

Definition at line 213 of file stm32f3xx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_SetReloadCounter | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Counter
 | ) |  |

Specify the IWDG down-counter reload value.

Reference Manual to LL API cross reference:
RLR RL LL_IWDG_SetReloadCounter
Parameters:
IWDGx | IWDG Instance
Counter | Value between Min_Data=0 and Max_Data=0x0FFF
Return values:
None

Definition at line 243 of file stm32f3xx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_SetWindow | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Window
 | ) |  |

Specify high limit of the window value to be compared to the down-counter.

Reference Manual to LL API cross reference:
WINR WIN LL_IWDG_SetWindow
Parameters:
IWDGx | IWDG Instance
Window | Value between Min_Data=0 and Max_Data=0x0FFF
Return values:
None

Definition at line 266 of file stm32f3xx_ll_iwdg.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLAG_Management

Functions
FLAG_Management
IWDG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_PVU (IWDG_TypeDef *IWDGx)
Check if flag Prescaler Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_RVU (IWDG_TypeDef *IWDGx)
Check if flag Reload Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_WVU (IWDG_TypeDef *IWDGx)
Check if flag Window Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsReady (IWDG_TypeDef *IWDGx)
Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Function Documentation

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU ( IWDG_TypeDef * IWDGx )

Check if flag Prescaler Value Update is set or not.

Reference Manual to LL API cross reference:
SR PVU LL_IWDG_IsActiveFlag_PVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 296 of file stm32f3xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU ( IWDG_TypeDef * IWDGx )

Check if flag Reload Value Update is set or not.

Reference Manual to LL API cross reference:
SR RVU LL_IWDG_IsActiveFlag_RVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 307 of file stm32f3xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU ( IWDG_TypeDef * IWDGx )

Check if flag Window Value Update is set or not.

Reference Manual to LL API cross reference:
SR WVU LL_IWDG_IsActiveFlag_WVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 318 of file stm32f3xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsReady ( IWDG_TypeDef * IWDGx )

Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Reference Manual to LL API cross reference:
SR PVU LL_IWDG_IsReady
SR WVU LL_IWDG_IsReady
SR RVU LL_IWDG_IsReady
Parameters:
IWDGx IWDG Instance
Return values:
State of bits (1 or 0).

Definition at line 331 of file stm32f3xx_ll_iwdg.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR

Modules
PWR
STM32F3xx_LL_Driver

Modules

PWR Exported Constants
PWR Exported Macros
PWR Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for PWR registers.

Register | Bit | Function
CR | CSBF | LL_PWR_ClearFlag_SB
 | CWUF | LL_PWR_ClearFlag_WU
 | DBP | LL_PWR_DisableBkUpAccess
 |  | LL_PWR_EnableBkUpAccess
 |  | LL_PWR_IsEnabledBkUpAccess
 | ENSD1 | LL_PWR_EnableSDADC
 |  | LL_PWR_IsEnabledSDADC
 | ENSD2 | LL_PWR_EnableSDADC
 |  | LL_PWR_IsEnabledSDADC
 | ENSD3 | LL_PWR_EnableSDADC
 |  | LL_PWR_IsEnabledSDADC
 | LPDS | LL_PWR_GetPowerMode
 |  | LL_PWR_GetRegulModeDS
 |  | LL_PWR_SetPowerMode
 |  | LL_PWR_SetRegulModeDS
 | PDDS | LL_PWR_GetPowerMode
 |  | LL_PWR_SetPowerMode
 | PLS | LL_PWR_GetPVDLevel
 |  | LL_PWR_SetPVDLevel
 | PVDE | LL_PWR_DisablePVD
 |  | LL_PWR_EnablePVD
 |  | LL_PWR_IsEnabledPVD
CSR | EWUP1 | LL_PWR_DisableWakeUpPin
 |  | LL_PWR_EnableWakeUpPin
 |  | LL_PWR_IsEnabledWakeUpPin
 | EWUP2 | LL_PWR_DisableWakeUpPin
 |  | LL_PWR_EnableWakeUpPin
 |  | LL_PWR_IsEnabledWakeUpPin
 | EWUP3 | LL_PWR_DisableWakeUpPin
 |  | LL_PWR_EnableWakeUpPin
 |  | LL_PWR_IsEnabledWakeUpPin
 | PVDO | LL_PWR_IsActiveFlag_PVDO
 | SBF | LL_PWR_IsActiveFlag_SB
 | VREFINTRDYF | LL_PWR_IsActiveFlag_VREFINTRDY
 | WUF | LL_PWR_IsActiveFlag_WU
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STM32F373xC HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
PWR Exported Constants

Flags defines which can be used with LL_PWR_WriteReg function. More...

Defines

#define | LL_PWR_CR_CSBF PWR_CR_CSBF
#define | LL_PWR_CR_CWUF PWR_CR_CWUF

Detailed Description

Flags defines which can be used with LL_PWR_WriteReg function.

Define Documentation

#define LL_PWR_CR_CSBF PWR_CR_CSBF

Clear standby flag

Definition at line 71 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_CR_CWUF PWR_CR_CWUF

Clear wakeup flag

Definition at line 72 of file stm32f3xx_ll_pwr.h.

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STM32F373xC HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
PWR Exported Constants

Flags defines which can be used with LL_PWR_ReadReg function. More...

Defines

#define | LL_PWR_CSR_WUF PWR_CSR_WUF
#define | LL_PWR_CSR_SBF PWR_CSR_SBF
#define | LL_PWR_CSR_PVDO PWR_CSR_PVDO
#define | LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF
#define | LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1
#define | LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2
#define | LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3

Detailed Description

Flags defines which can be used with LL_PWR_ReadReg function.

Define Documentation

#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1

Enable WKUP pin 1

Definition at line 89 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2

Enable WKUP pin 2

Definition at line 90 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3

Enable WKUP pin 3

Definition at line 92 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_CSR_PVDO PWR_CSR_PVDO

Power voltage detector output flag

Definition at line 84 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_CSR_SBF PWR_CSR_SBF

Standby flag

Definition at line 82 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF

VREFINT ready flag

Definition at line 87 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_CSR_WUF PWR_CSR_WUF

Wakeup flag

Definition at line 81 of file stm32f3xx_ll_pwr.h.

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STM32F373xC HAL User Manual: Mode Power

Defines
Mode Power
PWR Exported Constants

Defines

#define | LL_PWR_MODE_STOP_MAINREGU 0x00000000U
#define | LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS)
#define | LL_PWR_MODE_STANDBY (PWR_CR_PDDS)

Define Documentation

#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS)

Enter Standby mode when the CPU enters deepsleep

Definition at line 104 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS)

Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep

Definition at line 103 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U

Enter Stop mode when the CPU enters deepsleep

Definition at line 102 of file stm32f3xx_ll_pwr.h.

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STM32F373xC HAL User Manual: Regulator Mode In Deep Sleep Mode

Defines
Regulator Mode In Deep Sleep Mode
PWR Exported Constants

Defines

#define | LL_PWR_REGU_DSMODE_MAIN 0x00000000U
#define | LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS)

Define Documentation

#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS)

Voltage Regulator in low-power mode during deepsleep mode

Definition at line 114 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U

Voltage Regulator in main mode during deepsleep mode

Definition at line 113 of file stm32f3xx_ll_pwr.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Power Voltage Detector Level

Defines
Power Voltage Detector Level
PWR Exported Constants

Defines

#define | LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0)
#define | LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1)
#define | LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2)
#define | LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3)
#define | LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4)
#define | LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5)
#define | LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6)
#define | LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7)

Define Documentation

#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0)

Voltage threshold detected by PVD 2.2 V

Definition at line 124 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1)

Voltage threshold detected by PVD 2.3 V

Definition at line 125 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2)

Voltage threshold detected by PVD 2.4 V

Definition at line 126 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3)

Voltage threshold detected by PVD 2.5 V

Definition at line 127 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4)

Voltage threshold detected by PVD 2.6 V

Definition at line 128 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5)

Voltage threshold detected by PVD 2.7 V

Definition at line 129 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6)

Voltage threshold detected by PVD 2.8 V

Definition at line 130 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7)

Voltage threshold detected by PVD 2.9 V

Definition at line 131 of file stm32f3xx_ll_pwr.h.

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STM32F373xC HAL User Manual: Wakeup Pins

Defines
Wakeup Pins
PWR Exported Constants

Defines

#define | LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1)
#define | LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2)
#define | LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3)

Define Documentation

#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1)

WKUP pin 1 : PA0

Definition at line 139 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2)

WKUP pin 2 : PC13

Definition at line 140 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3)

WKUP pin 3 : PE6 or PA2 according to device

Definition at line 142 of file stm32f3xx_ll_pwr.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC Analogx

Defines
SDADC Analogx
PWR Exported Constants

Defines

#define | LL_PWR_SDADC_ANALOG1 (PWR_CR_ENSD1)
#define | LL_PWR_SDADC_ANALOG2 (PWR_CR_ENSD2)
#define | LL_PWR_SDADC_ANALOG3 (PWR_CR_ENSD3)

Define Documentation

#define LL_PWR_SDADC_ANALOG1 (PWR_CR_ENSD1)

Enable SDADC1

Definition at line 152 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_SDADC_ANALOG2 (PWR_CR_ENSD2)

Enable SDADC2

Definition at line 155 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_SDADC_ANALOG3 (PWR_CR_ENSD3)

Enable SDADC3

Definition at line 158 of file stm32f3xx_ll_pwr.h.

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STM32F373xC HAL User Manual: Common write and read registers Macros

Defines
Common write and read registers Macros
PWR Exported Macros

Defines

#define | LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
Write a value in PWR register.
#define | LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
Read a value in PWR register.

Define Documentation

#define LL_PWR_ReadReg ( __REG__ ) READ_REG(PWR->__REG__)

Read a value in PWR register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 190 of file stm32f3xx_ll_pwr.h.

#define LL_PWR_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(PWR->__REG__, (__VALUE__))

Write a value in PWR register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 183 of file stm32f3xx_ll_pwr.h.

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STM32F373xC HAL User Manual: Configuration

Functions
Configuration
PWR Exported Functions

Functions

__STATIC_INLINE void | LL_PWR_EnableSDADC (uint32_t Analogx)
Enables the SDADC peripheral functionality.
__STATIC_INLINE void | LL_PWR_DisableSDADC (uint32_t Analogx)
Disables the SDADC peripheral functionality.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledSDADC (uint32_t Analogx)
Check if SDADCx has been enabled or not.
__STATIC_INLINE void | LL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain.
__STATIC_INLINE void | LL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBkUpAccess (void)
Check if the backup domain is enabled.
__STATIC_INLINE void | LL_PWR_SetRegulModeDS (uint32_t RegulMode)
Set voltage Regulator mode during deep sleep mode.
__STATIC_INLINE uint32_t | LL_PWR_GetRegulModeDS (void)
Get voltage Regulator mode during deep sleep mode.
__STATIC_INLINE void | LL_PWR_SetPowerMode (uint32_t PDMode)
Set Power Down mode when CPU enters deepsleep.
__STATIC_INLINE uint32_t | LL_PWR_GetPowerMode (void)
Get Power Down mode when CPU enters deepsleep.
__STATIC_INLINE void | LL_PWR_SetPVDLevel (uint32_t PVDLevel)
Configure the voltage threshold detected by the Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetPVDLevel (void)
Get the voltage threshold detection.
__STATIC_INLINE void | LL_PWR_EnablePVD (void)
Enable Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_DisablePVD (void)
Disable Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVD (void)
Check if Power Voltage Detector is enabled.
__STATIC_INLINE void | LL_PWR_EnableWakeUpPin (uint32_t WakeUpPin)
Enable the WakeUp PINx functionality.
__STATIC_INLINE void | LL_PWR_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the WakeUp PINx functionality.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledWakeUpPin (uint32_t WakeUpPin)
Check if the WakeUp PINx functionality is enabled.

Function Documentation

__STATIC_INLINE void LL_PWR_DisableBkUpAccess ( void )

Disable access to the backup domain.

Reference Manual to LL API cross reference:
CR DBP LL_PWR_DisableBkUpAccess
Return values:
None

Definition at line 270 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisablePVD ( void )

Disable Power Voltage Detector.

Reference Manual to LL API cross reference:
CR PVDE LL_PWR_DisablePVD
Return values:
None

Definition at line 394 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableSDADC ( uint32_t Analogx )

Disables the SDADC peripheral functionality.

Reference Manual to LL API cross reference:
CR ENSD1 LL_PWR_EnableSDADC
CR ENSD2 LL_PWR_EnableSDADC
CR ENSD3 LL_PWR_EnableSDADC
Parameters:
Analogx This parameter can be a combination of the following values:
  • LL_PWR_SDADC_ANALOG1
  • LL_PWR_SDADC_ANALOG2
  • LL_PWR_SDADC_ANALOG3
Return values:
None

Definition at line 234 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableWakeUpPin ( uint32_t WakeUpPin )

Disable the WakeUp PINx functionality.

Reference Manual to LL API cross reference:
CSR EWUP1 LL_PWR_DisableWakeUpPin
Reference Manual to LL API cross reference:
CSR EWUP2 LL_PWR_DisableWakeUpPin
Reference Manual to LL API cross reference:
CSR EWUP3 LL_PWR_DisableWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3 (*)
(*) not available on all devices
Return values:
None

Definition at line 441 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableBkUpAccess ( void )

Enable access to the backup domain.

Reference Manual to LL API cross reference:
CR DBP LL_PWR_EnableBkUpAccess
Return values:
None

Definition at line 260 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnablePVD ( void )

Enable Power Voltage Detector.

Reference Manual to LL API cross reference:
CR PVDE LL_PWR_EnablePVD
Return values:
None

Definition at line 384 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableSDADC ( uint32_t Analogx )

Enables the SDADC peripheral functionality.

Reference Manual to LL API cross reference:
CR ENSD1 LL_PWR_EnableSDADC
CR ENSD2 LL_PWR_EnableSDADC
CR ENSD3 LL_PWR_EnableSDADC
Parameters:
Analogx This parameter can be a combination of the following values:
  • LL_PWR_SDADC_ANALOG1
  • LL_PWR_SDADC_ANALOG2
  • LL_PWR_SDADC_ANALOG3
Return values:
None

Definition at line 218 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableWakeUpPin ( uint32_t WakeUpPin )

Enable the WakeUp PINx functionality.

Reference Manual to LL API cross reference:
CSR EWUP1 LL_PWR_EnableWakeUpPin
Reference Manual to LL API cross reference:
CSR EWUP2 LL_PWR_EnableWakeUpPin
Reference Manual to LL API cross reference:
CSR EWUP3 LL_PWR_EnableWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3 (*)
(*) not available on all devices
Return values:
None

Definition at line 423 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetPowerMode ( void )

Get Power Down mode when CPU enters deepsleep.

Reference Manual to LL API cross reference:
CR PDDS LL_PWR_GetPowerMode
Reference Manual to LL API cross reference:
CR LPDS LL_PWR_GetPowerMode
Return values:
Returned value can be one of the following values:
  • LL_PWR_MODE_STOP_MAINREGU
  • LL_PWR_MODE_STOP_LPREGU
  • LL_PWR_MODE_STANDBY

Definition at line 336 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel ( void )

Get the voltage threshold detection.

Reference Manual to LL API cross reference:
CR PLS LL_PWR_GetPVDLevel
Return values:
Returned value can be one of the following values:
  • LL_PWR_PVDLEVEL_0
  • LL_PWR_PVDLEVEL_1
  • LL_PWR_PVDLEVEL_2
  • LL_PWR_PVDLEVEL_3
  • LL_PWR_PVDLEVEL_4
  • LL_PWR_PVDLEVEL_5
  • LL_PWR_PVDLEVEL_6
  • LL_PWR_PVDLEVEL_7

Definition at line 374 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS ( void )

Get voltage Regulator mode during deep sleep mode.

Reference Manual to LL API cross reference:
CR LPDS LL_PWR_GetRegulModeDS
Return values:
Returned value can be one of the following values:
  • LL_PWR_REGU_DSMODE_MAIN
  • LL_PWR_REGU_DSMODE_LOW_POWER

Definition at line 306 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess ( void )

Check if the backup domain is enabled.

Reference Manual to LL API cross reference:
CR DBP LL_PWR_IsEnabledBkUpAccess
Return values:
State of bit (1 or 0).

Definition at line 280 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD ( void )

Check if Power Voltage Detector is enabled.

Reference Manual to LL API cross reference:
CR PVDE LL_PWR_IsEnabledPVD
Return values:
State of bit (1 or 0).

Definition at line 404 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledSDADC ( uint32_t Analogx )

Check if SDADCx has been enabled or not.

Reference Manual to LL API cross reference:
CR ENSD1 LL_PWR_IsEnabledSDADC
CR ENSD2 LL_PWR_IsEnabledSDADC
CR ENSD3 LL_PWR_IsEnabledSDADC
Parameters:
Analogx This parameter can be a combination of the following values:
  • LL_PWR_SDADC_ANALOG1
  • LL_PWR_SDADC_ANALOG2
  • LL_PWR_SDADC_ANALOG3
Return values:
None

Definition at line 250 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin ( uint32_t WakeUpPin )

Check if the WakeUp PINx functionality is enabled.

Reference Manual to LL API cross reference:
CSR EWUP1 LL_PWR_IsEnabledWakeUpPin
Reference Manual to LL API cross reference:
CSR EWUP2 LL_PWR_IsEnabledWakeUpPin
Reference Manual to LL API cross reference:
CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3 (*)
(*) not available on all devices
Return values:
State of bit (1 or 0).

Definition at line 459 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetPowerMode ( uint32_t PDMode )

Set Power Down mode when CPU enters deepsleep.

Reference Manual to LL API cross reference:
CR PDDS LL_PWR_SetPowerMode
Reference Manual to LL API cross reference:
CR LPDS LL_PWR_SetPowerMode
Parameters:
PDMode This parameter can be one of the following values:
  • LL_PWR_MODE_STOP_MAINREGU
  • LL_PWR_MODE_STOP_LPREGU
  • LL_PWR_MODE_STANDBY
Return values:
None

Definition at line 322 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetPVDLevel ( uint32_t PVDLevel )

Configure the voltage threshold detected by the Power Voltage Detector.

Reference Manual to LL API cross reference:
CR PLS LL_PWR_SetPVDLevel
Parameters:
PVDLevel This parameter can be one of the following values:
  • LL_PWR_PVDLEVEL_0
  • LL_PWR_PVDLEVEL_1
  • LL_PWR_PVDLEVEL_2
  • LL_PWR_PVDLEVEL_3
  • LL_PWR_PVDLEVEL_4
  • LL_PWR_PVDLEVEL_5
  • LL_PWR_PVDLEVEL_6
  • LL_PWR_PVDLEVEL_7
Return values:
None

Definition at line 356 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetRegulModeDS ( uint32_t RegulMode )

Set voltage Regulator mode during deep sleep mode.

Reference Manual to LL API cross reference:
CR LPDS LL_PWR_SetRegulModeDS
Parameters:
RegulMode This parameter can be one of the following values:
  • LL_PWR_REGU_DSMODE_MAIN
  • LL_PWR_REGU_DSMODE_LOW_POWER
Return values:
None

Definition at line 294 of file stm32f3xx_ll_pwr.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLAG_Management

Functions
FLAG_Management
PWR Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU (void)
Get Wake-up Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_SB (void)
Get Standby Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVDO (void)
Indicate whether VDD voltage is below the selected PVD threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_VREFINTRDY (void)
Get Internal Reference VrefInt Flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_SB (void)
Clear Standby Flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU (void)
Clear Wake-up Flags.

Function Documentation

__STATIC_INLINE void LL_PWR_ClearFlag_SB ( void )

Clear Standby Flag.

Reference Manual to LL API cross reference:
CR CSBF LL_PWR_ClearFlag_SB
Return values:
None

Definition at line 521 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU ( void )

Clear Wake-up Flags.

Reference Manual to LL API cross reference:
CR CWUF LL_PWR_ClearFlag_WU
Return values:
None

Definition at line 531 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO ( void )

Indicate whether VDD voltage is below the selected PVD threshold.

Reference Manual to LL API cross reference:
CSR PVDO LL_PWR_IsActiveFlag_PVDO
Return values:
State of bit (1 or 0).

Definition at line 499 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB ( void )

Get Standby Flag.

Reference Manual to LL API cross reference:
CSR SBF LL_PWR_IsActiveFlag_SB
Return values:
State of bit (1 or 0).

Definition at line 488 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY ( void )

Get Internal Reference VrefInt Flag.

Reference Manual to LL API cross reference:
CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY
Return values:
State of bit (1 or 0).

Definition at line 511 of file stm32f3xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU ( void )

Get Wake-up Flag.

Reference Manual to LL API cross reference:
CSR WUF LL_PWR_IsActiveFlag_WU
Return values:
State of bit (1 or 0).

Definition at line 478 of file stm32f3xx_ll_pwr.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: De-initialization function

Functions
De-initialization function
PWR Exported Functions

Functions

ErrorStatus LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Function Documentation

ErrorStatus LL_PWR_DeInit ( void )

De-initialize the PWR registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: PWR registers are de-initialized
  • ERROR: not applicable

Definition at line 72 of file stm32f3xx_ll_pwr.c.

References LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_PWR, and LL_APB1_GRP1_ReleaseReset().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC

Modules
RCC
STM32F3xx_LL_Driver

Modules

RCC Private functions
RCC Private Constants
RCC Private Macros
RCC Exported Types
RCC Exported Constants
RCC Exported Macros
RCC Exported Functions
RCC_LL_Private_Variables

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for RCC registers.

Register | Bit | Function
BDCR | BDRST | LL_RCC_ForceBackupDomainReset
 |  | LL_RCC_ReleaseBackupDomainReset
 | LSEBYP | LL_RCC_LSE_DisableBypass
 |  | LL_RCC_LSE_EnableBypass
 | LSEDRV | LL_RCC_LSE_GetDriveCapability
 |  | LL_RCC_LSE_SetDriveCapability
 | LSEON | LL_RCC_LSE_Disable
 |  | LL_RCC_LSE_Enable
 | LSERDY | LL_RCC_LSE_IsReady
 | RTCEN | LL_RCC_DisableRTC
 |  | LL_RCC_EnableRTC
 |  | LL_RCC_IsEnabledRTC
 | RTCSEL | LL_RCC_GetRTCClockSource
 |  | LL_RCC_SetRTCClockSource
CFGR | ADCPRE | LL_RCC_GetADCClockSource
 |  | LL_RCC_SetADCClockSource
 | HPRE | LL_RCC_GetAHBPrescaler
 |  | LL_RCC_SetAHBPrescaler
 | MCO | LL_RCC_ConfigMCO
 | MCOPRE | LL_RCC_ConfigMCO
 | PLLMUL | LL_RCC_PLL_ConfigDomain_SYS
 |  | LL_RCC_PLL_GetMultiplicator
 | PLLNODIV | LL_RCC_ConfigMCO
 | PLLSRC | LL_RCC_PLL_ConfigDomain_SYS
 |  | LL_RCC_PLL_GetMainSource
 | PPRE1 | LL_RCC_GetAPB1Prescaler
 |  | LL_RCC_SetAPB1Prescaler
 | PPRE2 | LL_RCC_GetAPB2Prescaler
 |  | LL_RCC_SetAPB2Prescaler
 | SDPRE | LL_RCC_GetSDADCClockSource
 |  | LL_RCC_SetSDADCClockSource
 | SW | LL_RCC_SetSysClkSource
 | SWS | LL_RCC_GetSysClkSource
 | USBPRE | LL_RCC_GetUSBClockSource
 |  | LL_RCC_SetUSBClockSource
CFGR2 | PREDIV | LL_RCC_PLL_ConfigDomain_SYS
 |  | LL_RCC_PLL_GetPrediv
CFGR3 | CECSW | LL_RCC_GetCECClockSource
 |  | LL_RCC_SetCECClockSource
 | I2C1SW | LL_RCC_GetI2CClockSource
 |  | LL_RCC_SetI2CClockSource
 | I2C2SW | LL_RCC_GetI2CClockSource
 |  | LL_RCC_SetI2CClockSource
 | I2C3SW | LL_RCC_GetI2CClockSource
 |  | LL_RCC_SetI2CClockSource
 | USART1SW | LL_RCC_GetUSARTClockSource
 |  | LL_RCC_SetUSARTClockSource
 | USART2SW | LL_RCC_GetUSARTClockSource
 |  | LL_RCC_SetUSARTClockSource
 | USART3SW | LL_RCC_GetUSARTClockSource
 |  | LL_RCC_SetUSARTClockSource
CIR | CSSC | LL_RCC_ClearFlag_HSECSS
 | CSSF | LL_RCC_IsActiveFlag_HSECSS
 | HSERDYC | LL_RCC_ClearFlag_HSERDY
 | HSERDYF | LL_RCC_IsActiveFlag_HSERDY
 | HSERDYIE | LL_RCC_DisableIT_HSERDY
 |  | LL_RCC_EnableIT_HSERDY
 |  | LL_RCC_IsEnabledIT_HSERDY
 | HSIRDYC | LL_RCC_ClearFlag_HSIRDY
 | HSIRDYF | LL_RCC_IsActiveFlag_HSIRDY
 | HSIRDYIE | LL_RCC_DisableIT_HSIRDY
 |  | LL_RCC_EnableIT_HSIRDY
 |  | LL_RCC_IsEnabledIT_HSIRDY
 | LSERDYC | LL_RCC_ClearFlag_LSERDY
 | LSERDYF | LL_RCC_IsActiveFlag_LSERDY
 | LSERDYIE | LL_RCC_DisableIT_LSERDY
 |  | LL_RCC_EnableIT_LSERDY
 |  | LL_RCC_IsEnabledIT_LSERDY
 | LSIRDYC | LL_RCC_ClearFlag_LSIRDY
 | LSIRDYF | LL_RCC_IsActiveFlag_LSIRDY
 | LSIRDYIE | LL_RCC_DisableIT_LSIRDY
 |  | LL_RCC_EnableIT_LSIRDY
 |  | LL_RCC_IsEnabledIT_LSIRDY
 | PLLRDYC | LL_RCC_ClearFlag_PLLRDY
 | PLLRDYF | LL_RCC_IsActiveFlag_PLLRDY
 | PLLRDYIE | LL_RCC_DisableIT_PLLRDY
 |  | LL_RCC_EnableIT_PLLRDY
 |  | LL_RCC_IsEnabledIT_PLLRDY
CR | CSSON | LL_RCC_HSE_DisableCSS
 |  | LL_RCC_HSE_EnableCSS
 | HSEBYP | LL_RCC_HSE_DisableBypass
 |  | LL_RCC_HSE_EnableBypass
 | HSEON | LL_RCC_HSE_Disable
 |  | LL_RCC_HSE_Enable
 | HSERDY | LL_RCC_HSE_IsReady
 | HSICAL | LL_RCC_HSI_GetCalibration
 | HSION | LL_RCC_HSI_Disable
 |  | LL_RCC_HSI_Enable
 | HSIRDY | LL_RCC_HSI_IsReady
 | HSITRIM | LL_RCC_HSI_GetCalibTrimming
 |  | LL_RCC_HSI_SetCalibTrimming
 | PLLON | LL_RCC_PLL_Disable
 |  | LL_RCC_PLL_Enable
 | PLLRDY | LL_RCC_PLL_IsReady
CSR | IWDGRSTF | LL_RCC_IsActiveFlag_IWDGRST
 | LPWRRSTF | LL_RCC_IsActiveFlag_LPWRRST
 | LSION | LL_RCC_LSI_Disable
 |  | LL_RCC_LSI_Enable
 | LSIRDY | LL_RCC_LSI_IsReady
 | OBLRSTF | LL_RCC_IsActiveFlag_OBLRST
 | PINRSTF | LL_RCC_IsActiveFlag_PINRST
 | PORRSTF | LL_RCC_IsActiveFlag_PORRST
 | RMVF | LL_RCC_ClearResetFlags
 | SFTRSTF | LL_RCC_IsActiveFlag_SFTRST
 | V18PWRRSTF | LL_RCC_IsActiveFlag_V18PWRRST
 | WWDGRSTF | LL_RCC_IsActiveFlag_WWDGRST
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Private functions

Functions
RCC Private functions
RCC

Functions

uint32_t | RCC_GetSystemClockFreq (void)
Return SYSTEM clock frequency.
uint32_t | RCC_GetHCLKClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK clock frequency.
uint32_t | RCC_GetPCLK1ClockFreq (uint32_t HCLK_Frequency)
Return PCLK1 clock frequency.
uint32_t | RCC_GetPCLK2ClockFreq (uint32_t HCLK_Frequency)
Return PCLK2 clock frequency.
uint32_t | RCC_PLL_GetFreqDomain_SYS (void)
Return PLL clock frequency used for system domain.

Function Documentation

uint32_t RCC_GetHCLKClockFreq ( uint32_t SYSCLK_Frequency )

Return HCLK clock frequency.

Parameters:
SYSCLK_Frequency SYSCLK clock frequency
Return values:
HCLK clock frequency (in Hz)

Definition at line 1033 of file stm32f3xx_ll_rcc.c.

References __LL_RCC_CALC_HCLK_FREQ, and LL_RCC_GetAHBPrescaler().

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetSystemClocksFreq(), and LL_RCC_GetUSARTClockFreq().

uint32_t RCC_GetPCLK1ClockFreq ( uint32_t HCLK_Frequency )

Return PCLK1 clock frequency.

Parameters:
HCLK_Frequency HCLK clock frequency
Return values:
PCLK1 clock frequency (in Hz)

Definition at line 1044 of file stm32f3xx_ll_rcc.c.

References __LL_RCC_CALC_PCLK1_FREQ, and LL_RCC_GetAPB1Prescaler().

Referenced by LL_RCC_GetSystemClocksFreq(), and LL_RCC_GetUSARTClockFreq().

uint32_t RCC_GetPCLK2ClockFreq ( uint32_t HCLK_Frequency )

Return PCLK2 clock frequency.

Parameters:
HCLK_Frequency HCLK clock frequency
Return values:
PCLK2 clock frequency (in Hz)

Definition at line 1055 of file stm32f3xx_ll_rcc.c.

References __LL_RCC_CALC_PCLK2_FREQ, and LL_RCC_GetAPB2Prescaler().

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetSystemClocksFreq(), and LL_RCC_GetUSARTClockFreq().

uint32_t RCC_GetSystemClockFreq ( void )

Return SYSTEM clock frequency.

Return values:
SYSTEM clock frequency (in Hz)

Definition at line 1001 of file stm32f3xx_ll_rcc.c.

References HSE_VALUE, HSI_VALUE, LL_RCC_GetSysClkSource(), LL_RCC_SYS_CLKSOURCE_STATUS_HSE, LL_RCC_SYS_CLKSOURCE_STATUS_HSI, LL_RCC_SYS_CLKSOURCE_STATUS_PLL, and RCC_PLL_GetFreqDomain_SYS().

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetSDADCClockFreq(), LL_RCC_GetSystemClocksFreq(), and LL_RCC_GetUSARTClockFreq().

uint32_t RCC_PLL_GetFreqDomain_SYS ( void )

Return PLL clock frequency used for system domain.

Return values:
PLL clock frequency (in Hz)

Definition at line 1065 of file stm32f3xx_ll_rcc.c.

References __LL_RCC_CALC_PLLCLK_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv(), LL_RCC_PLLSOURCE_HSE, and LL_RCC_PLLSOURCE_HSI_DIV_2.

Referenced by LL_RCC_GetUSBClockFreq(), and RCC_GetSystemClockFreq().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Private Constants

Defines
RCC Private Constants
RCC

Defines

#define | RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE)
#define | RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1)
#define | RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2)
#define | RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_CR_HSICAL)
#define | RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_CR_HSITRIM)
#define | RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL)
#define | RCC_POSITION_USART1SW (uint32_t)0U
#define | RCC_POSITION_USART2SW (uint32_t)16U
#define | RCC_POSITION_USART3SW (uint32_t)18U
#define | RCC_POSITION_TIM1SW (uint32_t)8U
#define | RCC_POSITION_TIM8SW (uint32_t)9U
#define | RCC_POSITION_TIM15SW (uint32_t)10U
#define | RCC_POSITION_TIM16SW (uint32_t)11U
#define | RCC_POSITION_TIM17SW (uint32_t)13U
#define | RCC_POSITION_TIM20SW (uint32_t)15U
#define | RCC_POSITION_TIM2SW (uint32_t)24U
#define | RCC_POSITION_TIM34SW (uint32_t)25U

Define Documentation

#define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE)

field position in register RCC_CFGR

Definition at line 64 of file stm32f3xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_CR_HSICAL)

field position in register RCC_CR

Definition at line 67 of file stm32f3xx_ll_rcc.h.

#define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_CR_HSITRIM)

field position in register RCC_CR

Definition at line 68 of file stm32f3xx_ll_rcc.h.

#define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL)

field position in register RCC_CFGR

Definition at line 69 of file stm32f3xx_ll_rcc.h.

#define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1)

field position in register RCC_CFGR

Definition at line 65 of file stm32f3xx_ll_rcc.h.

#define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2)

field position in register RCC_CFGR

Definition at line 66 of file stm32f3xx_ll_rcc.h.

#define RCC_POSITION_TIM15SW (uint32_t)10U

field position in register RCC_CFGR3

Definition at line 75 of file stm32f3xx_ll_rcc.h.

#define RCC_POSITION_TIM16SW (uint32_t)11U

field position in register RCC_CFGR3

Definition at line 76 of file stm32f3xx_ll_rcc.h.

#define RCC_POSITION_TIM17SW (uint32_t)13U

field position in register RCC_CFGR3

Definition at line 77 of file stm32f3xx_ll_rcc.h.

#define RCC_POSITION_TIM1SW (uint32_t)8U

field position in register RCC_CFGR3

Definition at line 73 of file stm32f3xx_ll_rcc.h.

#define RCC_POSITION_TIM20SW (uint32_t)15U

field position in register RCC_CFGR3

Definition at line 78 of file stm32f3xx_ll_rcc.h.

#define RCC_POSITION_TIM2SW (uint32_t)24U

field position in register RCC_CFGR3

Definition at line 79 of file stm32f3xx_ll_rcc.h.

#define RCC_POSITION_TIM34SW (uint32_t)25U

field position in register RCC_CFGR3

Definition at line 80 of file stm32f3xx_ll_rcc.h.

#define RCC_POSITION_TIM8SW (uint32_t)9U

field position in register RCC_CFGR3

Definition at line 74 of file stm32f3xx_ll_rcc.h.

#define RCC_POSITION_USART1SW (uint32_t)0U

field position in register RCC_CFGR3

Definition at line 70 of file stm32f3xx_ll_rcc.h.

#define RCC_POSITION_USART2SW (uint32_t)16U

field position in register RCC_CFGR3

Definition at line 71 of file stm32f3xx_ll_rcc.h.

#define RCC_POSITION_USART3SW (uint32_t)18U

field position in register RCC_CFGR3

Definition at line 72 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Private Macros

Defines
RCC Private Macros
RCC

Defines

#define | IS_LL_RCC_USART_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
#define | IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
#define | IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
#define | IS_LL_RCC_SDADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDADC_CLKSOURCE))
#define | IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))

Define Documentation

#define IS_LL_RCC_ADC_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))

Definition at line 122 of file stm32f3xx_ll_rcc.c.

Referenced by LL_RCC_GetADCClockFreq().

#define IS_LL_RCC_CEC_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))

Definition at line 139 of file stm32f3xx_ll_rcc.c.

Referenced by LL_RCC_GetCECClockFreq().

#define IS_LL_RCC_I2C_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE))

Definition at line 104 of file stm32f3xx_ll_rcc.c.

Referenced by LL_RCC_GetI2CClockFreq().

#define IS_LL_RCC_I2S_CLKSOURCE ( __VALUE__ ) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)

Definition at line 115 of file stm32f3xx_ll_rcc.c.

#define IS_LL_RCC_SDADC_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_SDADC_CLKSOURCE))

Definition at line 135 of file stm32f3xx_ll_rcc.c.

Referenced by LL_RCC_GetSDADCClockFreq().

#define IS_LL_RCC_USART_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))

Definition at line 76 of file stm32f3xx_ll_rcc.c.

Referenced by LL_RCC_GetUSARTClockFreq().

#define IS_LL_RCC_USB_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))

Definition at line 118 of file stm32f3xx_ll_rcc.c.

Referenced by LL_RCC_GetUSBClockFreq().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_RCC_ClocksTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RCC_ClocksTypeDef Struct Reference
Clocks Frequency Structure

RCC Clocks Frequency Structure. More...

#include <stm32f3xx_ll_rcc.h>

Data Fields

uint32_t | SYSCLK_Frequency
uint32_t | HCLK_Frequency
uint32_t | PCLK1_Frequency
uint32_t | PCLK2_Frequency

Detailed Description

RCC Clocks Frequency Structure.

Definition at line 108 of file stm32f3xx_ll_rcc.h.

Field Documentation

uint32_t LL_RCC_ClocksTypeDef::HCLK_Frequency

HCLK clock frequency

Definition at line 111 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::PCLK1_Frequency

PCLK1 clock frequency

Definition at line 112 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq(), and LL_USART_Init().

uint32_t LL_RCC_ClocksTypeDef::PCLK2_Frequency

PCLK2 clock frequency

Definition at line 113 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::SYSCLK_Frequency

SYSCLK clock frequency

Definition at line 110 of file stm32f3xx_ll_rcc.h.

Referenced by LL_I2S_Init(), and LL_RCC_GetSystemClocksFreq().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_rcc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Oscillator Values adaptation

Defines
Oscillator Values adaptation
RCC Exported Constants

Defines used to adapt values of different oscillators. More...

Defines

#define | HSE_VALUE 8000000U
#define | HSI_VALUE 8000000U
#define | LSE_VALUE 32768U
#define | LSI_VALUE 32000U

Detailed Description

Defines used to adapt values of different oscillators.

Note:
These values could be modified in the user environment according to HW set-up.

Define Documentation

#define HSE_VALUE 8000000U

Value of the HSE oscillator in Hz

Definition at line 137 of file stm32f3xx_ll_rcc.h.

#define HSI_VALUE 8000000U

Value of the HSI oscillator in Hz

Definition at line 141 of file stm32f3xx_ll_rcc.h.

#define LSE_VALUE 32768U

Value of the LSE oscillator in Hz

Definition at line 145 of file stm32f3xx_ll_rcc.h.

#define LSI_VALUE 32000U

Value of the LSI oscillator in Hz

Definition at line 149 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
RCC Exported Constants

Flags defines which can be used with LL_RCC_WriteReg function. More...

Defines

#define | LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC
#define | LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC
#define | LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC
#define | LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC
#define | LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC
#define | LL_RCC_CIR_CSSC RCC_CIR_CSSC

Detailed Description

Flags defines which can be used with LL_RCC_WriteReg function.

Define Documentation

#define LL_RCC_CIR_CSSC RCC_CIR_CSSC

Clock Security System Interrupt Clear

Definition at line 164 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC

HSE Ready Interrupt Clear

Definition at line 162 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC

HSI Ready Interrupt Clear

Definition at line 161 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC

LSE Ready Interrupt Clear

Definition at line 160 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC

LSI Ready Interrupt Clear

Definition at line 159 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC

PLL Ready Interrupt Clear

Definition at line 163 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
RCC Exported Constants

Flags defines which can be used with LL_RCC_ReadReg function. More...

Defines

#define | LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF
#define | LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF
#define | LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF
#define | LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF
#define | LL_RCC_CFGR_MCOF RCC_CFGR_MCOF
#define | LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF
#define | LL_RCC_CIR_CSSF RCC_CIR_CSSF
#define | LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF
#define | LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF
#define | LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF
#define | LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF
#define | LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF
#define | LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF
#define | LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF
#define | LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF

Detailed Description

Flags defines which can be used with LL_RCC_ReadReg function.

Define Documentation

#define LL_RCC_CFGR_MCOF RCC_CFGR_MCOF

MCO flag

Definition at line 177 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CIR_CSSF RCC_CIR_CSSF

Clock Security System Interrupt flag

Definition at line 179 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF

HSE Ready Interrupt flag

Definition at line 176 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF

HSI Ready Interrupt flag

Definition at line 175 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF

LSE Ready Interrupt flag

Definition at line 174 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF

LSI Ready Interrupt flag

Definition at line 173 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF

PLL Ready Interrupt flag

Definition at line 178 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF

Independent Watchdog reset flag

Definition at line 184 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF

Low-Power reset flag

Definition at line 186 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF

OBL reset flag

Definition at line 180 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF

PIN reset flag

Definition at line 181 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF

POR/PDR reset flag

Definition at line 182 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF

Software Reset flag

Definition at line 183 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF

Reset flag of the 1.8 V domain.

Definition at line 188 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF

Window watchdog reset flag

Definition at line 185 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IT Defines

Defines
IT Defines
RCC Exported Constants

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions. More...

Defines

#define | LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE
#define | LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE
#define | LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE
#define | LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE
#define | LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE

Detailed Description

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions.

Define Documentation

#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE

HSE Ready Interrupt Enable

Definition at line 201 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE

HSI Ready Interrupt Enable

Definition at line 200 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE

LSE Ready Interrupt Enable

Definition at line 199 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE

LSI Ready Interrupt Enable

Definition at line 198 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE

PLL Ready Interrupt Enable

Definition at line 202 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LSE oscillator drive capability

Defines
LSE oscillator drive capability
RCC Exported Constants

Defines

#define | LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)
#define | LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
#define | LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
#define | LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Define Documentation

#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Xtal mode higher driving capability

Definition at line 213 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)

Xtal mode lower driving capability

Definition at line 210 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0

Xtal mode medium high driving capability

Definition at line 212 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1

Xtal mode medium low driving capability

Definition at line 211 of file stm32f3xx_ll_rcc.h.

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STM32F373xC HAL User Manual: System clock switch

Defines
System clock switch
RCC Exported Constants

Defines

#define | LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL

Define Documentation

#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE

HSE selection as system clock

Definition at line 222 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI

HSI selection as system clock

Definition at line 221 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL

PLL selection as system clock

Definition at line 223 of file stm32f3xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

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STM32F373xC HAL User Manual: System clock switch status

Defines
System clock switch status
RCC Exported Constants

Defines

#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL

Define Documentation

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE

HSE used as system clock

Definition at line 232 of file stm32f3xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq().

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI

HSI used as system clock

Definition at line 231 of file stm32f3xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq().

#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL

PLL used as system clock

Definition at line 233 of file stm32f3xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

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STM32F373xC HAL User Manual: AHB prescaler

Defines
AHB prescaler
RCC Exported Constants

Defines

#define | LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1
#define | LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2
#define | LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4
#define | LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8
#define | LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16
#define | LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64
#define | LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128
#define | LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256
#define | LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512

Define Documentation

#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1

SYSCLK not divided

Definition at line 241 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128

SYSCLK divided by 128

Definition at line 247 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16

SYSCLK divided by 16

Definition at line 245 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2

SYSCLK divided by 2

Definition at line 242 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256

SYSCLK divided by 256

Definition at line 248 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4

SYSCLK divided by 4

Definition at line 243 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512

SYSCLK divided by 512

Definition at line 249 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64

SYSCLK divided by 64

Definition at line 246 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8

SYSCLK divided by 8

Definition at line 244 of file stm32f3xx_ll_rcc.h.

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STM32F373xC HAL User Manual: APB low-speed prescaler (APB1)

Defines
APB low-speed prescaler (APB1)
RCC Exported Constants

Defines

#define | LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1
#define | LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2
#define | LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4
#define | LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8
#define | LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16

Define Documentation

#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1

HCLK not divided

Definition at line 257 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16

HCLK divided by 16

Definition at line 261 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2

HCLK divided by 2

Definition at line 258 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4

HCLK divided by 4

Definition at line 259 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8

HCLK divided by 8

Definition at line 260 of file stm32f3xx_ll_rcc.h.

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STM32F373xC HAL User Manual: APB high-speed prescaler (APB2)

Defines
APB high-speed prescaler (APB2)
RCC Exported Constants

Defines

#define | LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1
#define | LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2
#define | LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4
#define | LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8
#define | LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16

Define Documentation

#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1

HCLK not divided

Definition at line 269 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16

HCLK divided by 16

Definition at line 273 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2

HCLK divided by 2

Definition at line 270 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4

HCLK divided by 4

Definition at line 271 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8

HCLK divided by 8

Definition at line 272 of file stm32f3xx_ll_rcc.h.

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STM32F373xC HAL User Manual: MCO1 SOURCE selection

Defines
MCO1 SOURCE selection
RCC Exported Constants

Defines

#define | LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
#define | LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
#define | LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI
#define | LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE
#define | LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI
#define | LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE
#define | LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2

Define Documentation

#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE

HSE selection as MCO source

Definition at line 284 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI

HSI selection as MCO source

Definition at line 283 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE

LSE selection as MCO source

Definition at line 286 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI

LSI selection as MCO source

Definition at line 285 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK

MCO output disabled, no clock on MCO

Definition at line 281 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2

PLL clock divided by 2

Definition at line 287 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK

SYSCLK selection as MCO source

Definition at line 282 of file stm32f3xx_ll_rcc.h.

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STM32F373xC HAL User Manual: MCO1 prescaler

Defines
MCO1 prescaler
RCC Exported Constants

Defines

#define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)

Define Documentation

#define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)

MCO Clock divided by 1

Definition at line 298 of file stm32f3xx_ll_rcc.h.

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STM32F373xC HAL User Manual: Peripheral clock frequency

Defines
Peripheral clock frequency
RCC Exported Constants

Defines

#define | LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U
#define | LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU

Define Documentation

#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU

Frequency cannot be provided as external clock

Definition at line 317 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U

No clock enabled for the peripheral

Definition at line 316 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetCECClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetSDADCClockFreq(), LL_RCC_GetUSARTClockFreq(), LL_RCC_GetUSBClockFreq(), and LL_USART_Init().

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STM32F373xC HAL User Manual: Peripheral USART clock source selection

Defines
Peripheral USART clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK2)
#define | LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_SYSCLK)
#define | LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_LSE)
#define | LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_HSI)
#define | LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_PCLK)
#define | LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_SYSCLK)
#define | LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_LSE)
#define | LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_HSI)
#define | LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_PCLK)
#define | LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_SYSCLK)
#define | LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_LSE)
#define | LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_HSI)

Define Documentation

#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_HSI)

HSI oscillator clock used as USART1 clock source

Definition at line 333 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_LSE)

LSE oscillator clock used as USART1 clock source

Definition at line 332 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK2)

PCLK2 clock used as USART1 clock source

Definition at line 329 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_SYSCLK)

System clock selected as USART1 clock source

Definition at line 331 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_HSI)

HSI oscillator clock used as USART2 clock source

Definition at line 338 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_LSE)

LSE oscillator clock used as USART2 clock source

Definition at line 337 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_PCLK)

PCLK1 clock used as USART2 clock source

Definition at line 335 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_SYSCLK)

System clock selected as USART2 clock source

Definition at line 336 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_HSI)

HSI oscillator clock used as USART3 clock source

Definition at line 344 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_LSE)

LSE oscillator clock used as USART3 clock source

Definition at line 343 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_PCLK)

PCLK1 clock used as USART3 clock source

Definition at line 341 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_SYSCLK)

System clock selected as USART3 clock source

Definition at line 342 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

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STM32F373xC HAL User Manual: Peripheral I2C clock source selection

Defines
Peripheral I2C clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_HSI)
#define | LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_SYSCLK)
#define | LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_HSI)
#define | LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_SYSCLK)

Define Documentation

#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_HSI)

HSI oscillator clock used as I2C1 clock source

Definition at line 371 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_SYSCLK)

System clock selected as I2C1 clock source

Definition at line 372 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_HSI)

HSI oscillator clock used as I2C2 clock source

Definition at line 374 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_SYSCLK)

System clock selected as I2C2 clock source

Definition at line 375 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

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STM32F373xC HAL User Manual: Peripheral CEC clock source selection

Defines
Peripheral CEC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244
#define | LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE

Define Documentation

#define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244

HSI clock divided by 244 selected as HDMI CEC entry clock source

Definition at line 453 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetCECClockFreq().

#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE

LSE clock selected as HDMI CEC entry clock source

Definition at line 454 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetCECClockFreq().

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STM32F373xC HAL User Manual: Peripheral USB clock source selection

Defines
Peripheral USB clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1
#define | LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 RCC_CFGR_USBPRE_DIV1_5

Define Documentation

#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1

USB prescaler is PLL clock divided by 1

Definition at line 465 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 RCC_CFGR_USBPRE_DIV1_5

USB prescaler is PLL clock divided by 1.5

Definition at line 466 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

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STM32F373xC HAL User Manual: Peripheral ADC clock source selection

Defines
Peripheral ADC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2
#define | LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4
#define | LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6
#define | LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8

Define Documentation

#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2

ADC prescaler PCLK divided by 2

Definition at line 477 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4

ADC prescaler PCLK divided by 4

Definition at line 478 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6

ADC prescaler PCLK divided by 6

Definition at line 479 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8

ADC prescaler PCLK divided by 8

Definition at line 480 of file stm32f3xx_ll_rcc.h.

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STM32F373xC HAL User Manual: Peripheral SDADC clock source selection

Defines
Peripheral SDADC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_1 RCC_CFGR_SDPRE_DIV1
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_2 RCC_CFGR_SDPRE_DIV2
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_4 RCC_CFGR_SDPRE_DIV4
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_6 RCC_CFGR_SDPRE_DIV6
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_8 RCC_CFGR_SDPRE_DIV8
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_10 RCC_CFGR_SDPRE_DIV10
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_12 RCC_CFGR_SDPRE_DIV12
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_14 RCC_CFGR_SDPRE_DIV14
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_16 RCC_CFGR_SDPRE_DIV16
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_20 RCC_CFGR_SDPRE_DIV20
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_24 RCC_CFGR_SDPRE_DIV24
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_28 RCC_CFGR_SDPRE_DIV28
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_32 RCC_CFGR_SDPRE_DIV32
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_36 RCC_CFGR_SDPRE_DIV36
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_40 RCC_CFGR_SDPRE_DIV40
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_44 RCC_CFGR_SDPRE_DIV44
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_48 RCC_CFGR_SDPRE_DIV48

Define Documentation

#define LL_RCC_SDADC_CLKSRC_SYS_DIV_1 RCC_CFGR_SDPRE_DIV1

SDADC CLK not divided

Definition at line 577 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SDADC_CLKSRC_SYS_DIV_10 RCC_CFGR_SDPRE_DIV10

SDADC CLK divided by 10

Definition at line 582 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SDADC_CLKSRC_SYS_DIV_12 RCC_CFGR_SDPRE_DIV12

SDADC CLK divided by 12

Definition at line 583 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SDADC_CLKSRC_SYS_DIV_14 RCC_CFGR_SDPRE_DIV14

SDADC CLK divided by 14

Definition at line 584 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SDADC_CLKSRC_SYS_DIV_16 RCC_CFGR_SDPRE_DIV16

SDADC CLK divided by 16

Definition at line 585 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SDADC_CLKSRC_SYS_DIV_2 RCC_CFGR_SDPRE_DIV2

SDADC CLK divided by 2

Definition at line 578 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SDADC_CLKSRC_SYS_DIV_20 RCC_CFGR_SDPRE_DIV20

SDADC CLK divided by 20

Definition at line 586 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SDADC_CLKSRC_SYS_DIV_24 RCC_CFGR_SDPRE_DIV24

SDADC CLK divided by 24

Definition at line 587 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SDADC_CLKSRC_SYS_DIV_28 RCC_CFGR_SDPRE_DIV28

SDADC CLK divided by 28

Definition at line 588 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SDADC_CLKSRC_SYS_DIV_32 RCC_CFGR_SDPRE_DIV32

SDADC CLK divided by 32

Definition at line 589 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SDADC_CLKSRC_SYS_DIV_36 RCC_CFGR_SDPRE_DIV36

SDADC CLK divided by 36

Definition at line 590 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SDADC_CLKSRC_SYS_DIV_4 RCC_CFGR_SDPRE_DIV4

SDADC CLK divided by 4

Definition at line 579 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SDADC_CLKSRC_SYS_DIV_40 RCC_CFGR_SDPRE_DIV40

SDADC CLK divided by 40

Definition at line 591 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SDADC_CLKSRC_SYS_DIV_44 RCC_CFGR_SDPRE_DIV44

SDADC CLK divided by 44

Definition at line 592 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SDADC_CLKSRC_SYS_DIV_48 RCC_CFGR_SDPRE_DIV48

SDADC CLK divided by 48

Definition at line 593 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SDADC_CLKSRC_SYS_DIV_6 RCC_CFGR_SDPRE_DIV6

SDADC CLK divided by 6

Definition at line 580 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_SDADC_CLKSRC_SYS_DIV_8 RCC_CFGR_SDPRE_DIV8

SDADC CLK divided by 8

Definition at line 581 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral USART get clock source

Defines
Peripheral USART get clock source
RCC Exported Constants

Defines

#define | LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW
#define | LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW
#define | LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW

Define Documentation

#define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW

USART1 Clock source selection

Definition at line 603 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq(), and LL_USART_Init().

#define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW

USART2 Clock source selection

Definition at line 605 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq(), and LL_USART_Init().

#define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW

USART3 Clock source selection

Definition at line 608 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq(), and LL_USART_Init().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral I2C get clock source

Defines
Peripheral I2C get clock source
RCC Exported Constants

Defines

#define | LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW
#define | LL_RCC_I2C2_CLKSOURCE RCC_CFGR3_I2C2SW

Define Documentation

#define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW

I2C1 Clock source selection

Definition at line 629 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C2_CLKSOURCE RCC_CFGR3_I2C2SW

I2C2 Clock source selection

Definition at line 631 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral CEC get clock source

Defines
Peripheral CEC get clock source
RCC Exported Constants

Defines

#define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW

Define Documentation

#define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW

CEC Clock source selection

Definition at line 698 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral USB get clock source

Defines
Peripheral USB get clock source
RCC Exported Constants

Defines

#define LL_RCC_USB_CLKSOURCE RCC_CFGR_USBPRE

Define Documentation

#define LL_RCC_USB_CLKSOURCE RCC_CFGR_USBPRE

USB Clock source selection

Definition at line 709 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral ADC get clock source

Defines
Peripheral ADC get clock source
RCC Exported Constants

Defines

#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE

Define Documentation

#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE

ADC Clock source selection

Definition at line 720 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral SDADC get clock source

Defines
Peripheral SDADC get clock source
RCC Exported Constants

Defines

#define LL_RCC_SDADC_CLKSOURCE RCC_CFGR_SDPRE

Define Documentation

#define LL_RCC_SDADC_CLKSOURCE RCC_CFGR_SDPRE

SDADC Clock source selection

Definition at line 749 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC clock source selection

Defines
RTC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U
#define | LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL

Define Documentation

#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL

HSE oscillator clock divided by 32 used as RTC clock

Definition at line 763 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0

LSE oscillator clock used as RTC clock

Definition at line 761 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1

LSI oscillator clock used as RTC clock

Definition at line 762 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U

No clock used as RTC clock

Definition at line 760 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PLL Multiplicator factor

Defines
PLL Multiplicator factor
RCC Exported Constants

Defines

#define | LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2
#define | LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3
#define | LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4
#define | LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5
#define | LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6
#define | LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7
#define | LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8
#define | LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9
#define | LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10
#define | LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11
#define | LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12
#define | LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13
#define | LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14
#define | LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15
#define | LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16

Define Documentation

#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10

PLL input clock*10

Definition at line 779 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11

PLL input clock*11

Definition at line 780 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12

PLL input clock*12

Definition at line 781 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13

PLL input clock*13

Definition at line 782 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14

PLL input clock*14

Definition at line 783 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15

PLL input clock*15

Definition at line 784 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16

PLL input clock*16

Definition at line 785 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2

PLL input clock*2

Definition at line 771 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3

PLL input clock*3

Definition at line 772 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4

PLL input clock*4

Definition at line 773 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5

PLL input clock*5

Definition at line 774 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6

PLL input clock*6

Definition at line 775 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7

PLL input clock*7

Definition at line 776 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8

PLL input clock*8

Definition at line 777 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9

PLL input clock*9

Definition at line 778 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PLL SOURCE

Defines
PLL SOURCE
RCC Exported Constants

Defines

#define | LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
#define | LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2
#define | LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1)
#define | LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2)
#define | LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3)
#define | LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4)
#define | LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5)
#define | LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6)
#define | LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7)
#define | LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8)
#define | LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9)
#define | LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10)
#define | LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11)
#define | LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12)
#define | LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13)
#define | LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14)
#define | LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15)
#define | LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16)

Define Documentation

#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV

HSE/PREDIV clock selected as PLL entry clock source

Definition at line 793 of file stm32f3xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and RCC_PLL_GetFreqDomain_SYS().

#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1)

HSE clock selected as PLL entry clock source

Definition at line 798 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10)

HSE/10 clock selected as PLL entry clock source

Definition at line 807 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11)

HSE/11 clock selected as PLL entry clock source

Definition at line 808 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12)

HSE/12 clock selected as PLL entry clock source

Definition at line 809 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13)

HSE/13 clock selected as PLL entry clock source

Definition at line 810 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14)

HSE/14 clock selected as PLL entry clock source

Definition at line 811 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15)

HSE/15 clock selected as PLL entry clock source

Definition at line 812 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16)

HSE/16 clock selected as PLL entry clock source

Definition at line 813 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2)

HSE/2 clock selected as PLL entry clock source

Definition at line 799 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3)

HSE/3 clock selected as PLL entry clock source

Definition at line 800 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4)

HSE/4 clock selected as PLL entry clock source

Definition at line 801 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5)

HSE/5 clock selected as PLL entry clock source

Definition at line 802 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6)

HSE/6 clock selected as PLL entry clock source

Definition at line 803 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7)

HSE/7 clock selected as PLL entry clock source

Definition at line 804 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8)

HSE/8 clock selected as PLL entry clock source

Definition at line 805 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9)

HSE/9 clock selected as PLL entry clock source

Definition at line 806 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2

HSI clock divided by 2 selected as PLL entry clock source

Definition at line 797 of file stm32f3xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI(), and RCC_PLL_GetFreqDomain_SYS().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PREDIV Division factor

Defines
PREDIV Division factor
RCC Exported Constants

Defines

#define | LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1
#define | LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2
#define | LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3
#define | LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4
#define | LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5
#define | LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6
#define | LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7
#define | LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8
#define | LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9
#define | LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10
#define | LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11
#define | LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12
#define | LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13
#define | LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14
#define | LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15
#define | LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16

Define Documentation

#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1

PREDIV input clock not divided

Definition at line 822 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10

PREDIV input clock divided by 10

Definition at line 831 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11

PREDIV input clock divided by 11

Definition at line 832 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12

PREDIV input clock divided by 12

Definition at line 833 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13

PREDIV input clock divided by 13

Definition at line 834 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14

PREDIV input clock divided by 14

Definition at line 835 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15

PREDIV input clock divided by 15

Definition at line 836 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16

PREDIV input clock divided by 16

Definition at line 837 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2

PREDIV input clock divided by 2

Definition at line 823 of file stm32f3xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI().

#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3

PREDIV input clock divided by 3

Definition at line 824 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4

PREDIV input clock divided by 4

Definition at line 825 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5

PREDIV input clock divided by 5

Definition at line 826 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6

PREDIV input clock divided by 6

Definition at line 827 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7

PREDIV input clock divided by 7

Definition at line 828 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8

PREDIV input clock divided by 8

Definition at line 829 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9

PREDIV input clock divided by 9

Definition at line 830 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
RCC Exported Macros

Defines

#define | LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
Write a value in RCC register.
#define | LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
Read a value in RCC register.

Define Documentation

#define LL_RCC_ReadReg ( __REG__ ) READ_REG(RCC->__REG__)

Read a value in RCC register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 868 of file stm32f3xx_ll_rcc.h.

#define LL_RCC_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(RCC->__REG__, (__VALUE__))

Write a value in RCC register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 861 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Calculate frequencies

Defines
Calculate frequencies
RCC Exported Macros

Defines

#define | __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
Helper macro to calculate the PLLCLK frequency.
#define | __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
Helper macro to calculate the HCLK frequency.
#define | __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
Helper macro to calculate the PCLK1 frequency (ABP1)
#define | __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
Helper macro to calculate the PCLK2 frequency (ABP2)

Define Documentation

#define __LL_RCC_CALC_HCLK_FREQ | ( | __SYSCLKFREQ__,
 |  | __AHBPRESCALER__
 | ) | ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])

Helper macro to calculate the HCLK frequency.

Note:
: __AHBPRESCALER__ be retrieved by LL_RCC_GetAHBPrescaler ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
Parameters:
__SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
__AHBPRESCALER__ This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
HCLK clock frequency (in Hz)

Definition at line 964 of file stm32f3xx_ll_rcc.h.

Referenced by RCC_GetHCLKClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

#define __LL_RCC_CALC_PCLK1_FREQ | ( | __HCLKFREQ__,
 |  | __APB1PRESCALER__
 | ) | ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])

Helper macro to calculate the PCLK1 frequency (ABP1)

Note:
: __APB1PRESCALER__ be retrieved by LL_RCC_GetAPB1Prescaler ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
Parameters:
__HCLKFREQ__ HCLK frequency
__APB1PRESCALER__,: This parameter can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16
Return values:
PCLK1 clock frequency (in Hz)

Definition at line 979 of file stm32f3xx_ll_rcc.h.

Referenced by RCC_GetPCLK1ClockFreq().

#define __LL_RCC_CALC_PCLK2_FREQ | ( | __HCLKFREQ__,
 |  | __APB2PRESCALER__
 | ) | ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])

Helper macro to calculate the PCLK2 frequency (ABP2)

Note:
: __APB2PRESCALER__ be retrieved by LL_RCC_GetAPB2Prescaler ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
Parameters:
__HCLKFREQ__ HCLK frequency
__APB2PRESCALER__,: This parameter can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16
Return values:
PCLK2 clock frequency (in Hz)

Definition at line 994 of file stm32f3xx_ll_rcc.h.

Referenced by RCC_GetPCLK2ClockFreq().

#define __LL_RCC_CALC_PLLCLK_FREQ | ( | __INPUTFREQ__,
 |  | __PLLMUL__
 | ) | ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))

Helper macro to calculate the PLLCLK frequency.

Note:
ex: __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (LL_RCC_PLL_GetPrediv () + 1), LL_RCC_PLL_GetMultiplicator());
Parameters:
__INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2)
__PLLMUL__ This parameter can be one of the following values:
  • LL_RCC_PLL_MUL_2
  • LL_RCC_PLL_MUL_3
  • LL_RCC_PLL_MUL_4
  • LL_RCC_PLL_MUL_5
  • LL_RCC_PLL_MUL_6
  • LL_RCC_PLL_MUL_7
  • LL_RCC_PLL_MUL_8
  • LL_RCC_PLL_MUL_9
  • LL_RCC_PLL_MUL_10
  • LL_RCC_PLL_MUL_11
  • LL_RCC_PLL_MUL_12
  • LL_RCC_PLL_MUL_13
  • LL_RCC_PLL_MUL_14
  • LL_RCC_PLL_MUL_15
  • LL_RCC_PLL_MUL_16
Return values:
PLL clock frequency (in Hz)

Definition at line 944 of file stm32f3xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SYS(), and UTILS_GetPLLOutputFrequency().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HSE

Functions
HSE
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSE_EnableCSS (void)
Enable the Clock Security System.
__STATIC_INLINE void | LL_RCC_HSE_DisableCSS (void)
Disable the Clock Security System.
__STATIC_INLINE void | LL_RCC_HSE_EnableBypass (void)
Enable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_DisableBypass (void)
Disable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_Enable (void)
Enable HSE crystal oscillator (HSE ON)
__STATIC_INLINE void | LL_RCC_HSE_Disable (void)
Disable HSE crystal oscillator (HSE ON)
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsReady (void)
Check if HSE oscillator Ready.

Function Documentation

__STATIC_INLINE void LL_RCC_HSE_Disable ( void )

Disable HSE crystal oscillator (HSE ON)

Reference Manual to LL API cross reference:
CR HSEON LL_RCC_HSE_Disable
Return values:
None

Definition at line 1069 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSE_DisableBypass ( void )

Disable HSE external oscillator (HSE Bypass)

Reference Manual to LL API cross reference:
CR HSEBYP LL_RCC_HSE_DisableBypass
Return values:
None

Definition at line 1049 of file stm32f3xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_RCC_DeInit().

__STATIC_INLINE void LL_RCC_HSE_DisableCSS ( void )

Disable the Clock Security System.

Note:
Cannot be disabled in HSE is ready (only by hardware)
Reference Manual to LL API cross reference:
CR CSSON LL_RCC_HSE_DisableCSS
Return values:
None

Definition at line 1029 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSE_Enable ( void )

Enable HSE crystal oscillator (HSE ON)

Reference Manual to LL API cross reference:
CR HSEON LL_RCC_HSE_Enable
Return values:
None

Definition at line 1059 of file stm32f3xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_EnableBypass ( void )

Enable HSE external oscillator (HSE Bypass)

Reference Manual to LL API cross reference:
CR HSEBYP LL_RCC_HSE_EnableBypass
Return values:
None

Definition at line 1039 of file stm32f3xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_EnableCSS ( void )

Enable the Clock Security System.

Reference Manual to LL API cross reference:
CR CSSON LL_RCC_HSE_EnableCSS
Return values:
None

Definition at line 1018 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady ( void )

Check if HSE oscillator Ready.

Reference Manual to LL API cross reference:
CR HSERDY LL_RCC_HSE_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1079 of file stm32f3xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HSI

Functions
HSI
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSI_Enable (void)
Enable HSI oscillator.
__STATIC_INLINE void | LL_RCC_HSI_Disable (void)
Disable HSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsReady (void)
Check if HSI clock is ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibration (void)
Get HSI Calibration value.
__STATIC_INLINE void | LL_RCC_HSI_SetCalibTrimming (uint32_t Value)
Set HSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibTrimming (void)
Get HSI Calibration trimming.

Function Documentation

__STATIC_INLINE void LL_RCC_HSI_Disable ( void )

Disable HSI oscillator.

Reference Manual to LL API cross reference:
CR HSION LL_RCC_HSI_Disable
Return values:
None

Definition at line 1107 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI_Enable ( void )

Enable HSI oscillator.

Reference Manual to LL API cross reference:
CR HSION LL_RCC_HSI_Enable
Return values:
None

Definition at line 1097 of file stm32f3xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI(), and LL_RCC_DeInit().

__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration ( void )

Get HSI Calibration value.

Note:
When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value
Reference Manual to LL API cross reference:
CR HSICAL LL_RCC_HSI_GetCalibration
Return values:
Between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 1129 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming ( void )

Get HSI Calibration trimming.

Reference Manual to LL API cross reference:
CR HSITRIM LL_RCC_HSI_GetCalibTrimming
Return values:
Between Min_Data = 0x00 and Max_Data = 0x1F

Definition at line 1153 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady ( void )

Check if HSI clock is ready.

Reference Manual to LL API cross reference:
CR HSIRDY LL_RCC_HSI_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1117 of file stm32f3xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI(), LL_RCC_GetCECClockFreq(), LL_RCC_GetI2CClockFreq(), and LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming ( uint32_t Value )

Set HSI Calibration trimming.

Note:
user-programmable trimming value that is added to the HSICAL
Default value is 16, which, when added to the HSICAL value, should trim the HSI to 16 MHz +/- 1 %
Reference Manual to LL API cross reference:
CR HSITRIM LL_RCC_HSI_SetCalibTrimming
Parameters:
Value between Min_Data = 0x00 and Max_Data = 0x1F
Return values:
None

Definition at line 1143 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LSE

Functions
LSE
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSE_Enable (void)
Enable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_Disable (void)
Disable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_EnableBypass (void)
Enable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_DisableBypass (void)
Disable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_SetDriveCapability (uint32_t LSEDrive)
Set LSE oscillator drive capability.
__STATIC_INLINE uint32_t | LL_RCC_LSE_GetDriveCapability (void)
Get LSE oscillator drive capability.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsReady (void)
Check if LSE oscillator Ready.

Function Documentation

__STATIC_INLINE void LL_RCC_LSE_Disable ( void )

Disable Low Speed External (LSE) crystal.

Reference Manual to LL API cross reference:
BDCR LSEON LL_RCC_LSE_Disable
Return values:
None

Definition at line 1181 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_DisableBypass ( void )

Disable external clock source (LSE bypass).

Reference Manual to LL API cross reference:
BDCR LSEBYP LL_RCC_LSE_DisableBypass
Return values:
None

Definition at line 1201 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_Enable ( void )

Enable Low Speed External (LSE) crystal.

Reference Manual to LL API cross reference:
BDCR LSEON LL_RCC_LSE_Enable
Return values:
None

Definition at line 1171 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_EnableBypass ( void )

Enable external clock source (LSE bypass).

Reference Manual to LL API cross reference:
BDCR LSEBYP LL_RCC_LSE_EnableBypass
Return values:
None

Definition at line 1191 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability ( void )

Get LSE oscillator drive capability.

Reference Manual to LL API cross reference:
BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
Return values:
Returned value can be one of the following values:
  • LL_RCC_LSEDRIVE_LOW
  • LL_RCC_LSEDRIVE_MEDIUMLOW
  • LL_RCC_LSEDRIVE_MEDIUMHIGH
  • LL_RCC_LSEDRIVE_HIGH

Definition at line 1231 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady ( void )

Check if LSE oscillator Ready.

Reference Manual to LL API cross reference:
BDCR LSERDY LL_RCC_LSE_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1241 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetCECClockFreq(), and LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability ( uint32_t LSEDrive )

Set LSE oscillator drive capability.

Note:
The oscillator is in Xtal mode when it is not in bypass mode.
Reference Manual to LL API cross reference:
BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
Parameters:
LSEDrive This parameter can be one of the following values:
  • LL_RCC_LSEDRIVE_LOW
  • LL_RCC_LSEDRIVE_MEDIUMLOW
  • LL_RCC_LSEDRIVE_MEDIUMHIGH
  • LL_RCC_LSEDRIVE_HIGH
Return values:
None

Definition at line 1217 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LSI

Functions
LSI
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSI_Enable (void)
Enable LSI Oscillator.
__STATIC_INLINE void | LL_RCC_LSI_Disable (void)
Disable LSI Oscillator.
__STATIC_INLINE uint32_t | LL_RCC_LSI_IsReady (void)
Check if LSI is Ready.

Function Documentation

__STATIC_INLINE void LL_RCC_LSI_Disable ( void )

Disable LSI Oscillator.

Reference Manual to LL API cross reference:
CSR LSION LL_RCC_LSI_Disable
Return values:
None

Definition at line 1269 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSI_Enable ( void )

Enable LSI Oscillator.

Reference Manual to LL API cross reference:
CSR LSION LL_RCC_LSI_Enable
Return values:
None

Definition at line 1259 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady ( void )

Check if LSI is Ready.

Reference Manual to LL API cross reference:
CSR LSIRDY LL_RCC_LSI_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1279 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: System

Functions
System
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetSysClkSource (uint32_t Source)
Configure the system clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSysClkSource (void)
Get the system clock source.
__STATIC_INLINE void | LL_RCC_SetAHBPrescaler (uint32_t Prescaler)
Set AHB prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB1Prescaler (uint32_t Prescaler)
Set APB1 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB2Prescaler (uint32_t Prescaler)
Set APB2 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAHBPrescaler (void)
Get AHB prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB1Prescaler (void)
Get APB1 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB2Prescaler (void)
Get APB2 prescaler.

Function Documentation

__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler ( void )

Get AHB prescaler.

Reference Manual to LL API cross reference:
CFGR HPRE LL_RCC_GetAHBPrescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512

Definition at line 1385 of file stm32f3xx_ll_rcc.h.

Referenced by RCC_GetHCLKClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler ( void )

Get APB1 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE1 LL_RCC_GetAPB1Prescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16

Definition at line 1400 of file stm32f3xx_ll_rcc.h.

Referenced by RCC_GetPCLK1ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler ( void )

Get APB2 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE2 LL_RCC_GetAPB2Prescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16

Definition at line 1415 of file stm32f3xx_ll_rcc.h.

Referenced by RCC_GetPCLK2ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource ( void )

Get the system clock source.

Reference Manual to LL API cross reference:
CFGR SWS LL_RCC_GetSysClkSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL

Definition at line 1314 of file stm32f3xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAHBPrescaler ( uint32_t Prescaler )

Set AHB prescaler.

Reference Manual to LL API cross reference:
CFGR HPRE LL_RCC_SetAHBPrescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
None

Definition at line 1334 of file stm32f3xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAPB1Prescaler ( uint32_t Prescaler )

Set APB1 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE1 LL_RCC_SetAPB1Prescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16
Return values:
None

Definition at line 1350 of file stm32f3xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAPB2Prescaler ( uint32_t Prescaler )

Set APB2 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE2 LL_RCC_SetAPB2Prescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16
Return values:
None

Definition at line 1366 of file stm32f3xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetSysClkSource ( uint32_t Source )

Configure the system clock source.

Reference Manual to LL API cross reference:
CFGR SW LL_RCC_SetSysClkSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_SYS_CLKSOURCE_HSI
  • LL_RCC_SYS_CLKSOURCE_HSE
  • LL_RCC_SYS_CLKSOURCE_PLL
Return values:
None

Definition at line 1301 of file stm32f3xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: MCO

Functions
MCO
RCC Exported Functions

Functions

__STATIC_INLINE void LL_RCC_ConfigMCO (uint32_t MCOxSource, uint32_t MCOxPrescaler)
Configure MCOx.

Function Documentation

__STATIC_INLINE void LL_RCC_ConfigMCO | ( | uint32_t | MCOxSource,
 |  | uint32_t | MCOxPrescaler
 | ) |  |

Configure MCOx.

Reference Manual to LL API cross reference:
CFGR MCO LL_RCC_ConfigMCO
CFGR MCOPRE LL_RCC_ConfigMCO
CFGR PLLNODIV LL_RCC_ConfigMCO
Parameters:
MCOxSource This parameter can be one of the following values:
  • LL_RCC_MCO1SOURCE_NOCLOCK
  • LL_RCC_MCO1SOURCE_SYSCLK
  • LL_RCC_MCO1SOURCE_HSI
  • LL_RCC_MCO1SOURCE_HSE
  • LL_RCC_MCO1SOURCE_LSI
  • LL_RCC_MCO1SOURCE_LSE
  • LL_RCC_MCO1SOURCE_PLLCLK (*)
  • LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
(*) value not defined in all devices
MCOxPrescaler This parameter can be one of the following values:
  • LL_RCC_MCO1_DIV_1
  • LL_RCC_MCO1_DIV_2 (*)
  • LL_RCC_MCO1_DIV_4 (*)
  • LL_RCC_MCO1_DIV_8 (*)
  • LL_RCC_MCO1_DIV_16 (*)
  • LL_RCC_MCO1_DIV_32 (*)
  • LL_RCC_MCO1_DIV_64 (*)
  • LL_RCC_MCO1_DIV_128 (*)
(*) value not defined in all devices
Return values:
None

Definition at line 1457 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral Clock Source

Functions
Peripheral Clock Source
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetUSARTClockSource (uint32_t USARTxSource)
Configure USARTx clock source.
__STATIC_INLINE void | LL_RCC_SetI2CClockSource (uint32_t I2CxSource)
Configure I2Cx clock source.
__STATIC_INLINE void | LL_RCC_SetCECClockSource (uint32_t CECxSource)
Configure CEC clock source.
__STATIC_INLINE void | LL_RCC_SetUSBClockSource (uint32_t USBxSource)
Configure USB clock source.
__STATIC_INLINE void | LL_RCC_SetADCClockSource (uint32_t ADCxSource)
Configure ADC clock source.
__STATIC_INLINE void | LL_RCC_SetSDADCClockSource (uint32_t SDADCxSource)
Configure SDADCx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSARTClockSource (uint32_t USARTx)
Get USARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetI2CClockSource (uint32_t I2Cx)
Get I2Cx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetCECClockSource (uint32_t CECx)
Get CEC clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSBClockSource (uint32_t USBx)
Get USBx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetADCClockSource (uint32_t ADCx)
Get ADCx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSDADCClockSource (uint32_t SDADCx)
Get SDADCx clock source.

Function Documentation

__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource ( uint32_t ADCx )

Get ADCx clock source.

Reference Manual to LL API cross reference:
CFGR ADCPRE LL_RCC_GetADCClockSource
Parameters:
ADCx This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_8

Definition at line 1971 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource ( uint32_t CECx )

Get CEC clock source.

Reference Manual to LL API cross reference:
CFGR3 CECSW LL_RCC_GetCECClockSource
Parameters:
CECx This parameter can be one of the following values:
  • LL_RCC_CEC_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_CEC_CLKSOURCE_HSI_DIV244
  • LL_RCC_CEC_CLKSOURCE_LSE

Definition at line 1937 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetCECClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource ( uint32_t I2Cx )

Get I2Cx clock source.

Reference Manual to LL API cross reference:
CFGR3 I2C1SW LL_RCC_GetI2CClockSource
CFGR3 I2C2SW LL_RCC_GetI2CClockSource
CFGR3 I2C3SW LL_RCC_GetI2CClockSource
Parameters:
I2Cx This parameter can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE
  • LL_RCC_I2C2_CLKSOURCE (*)
  • LL_RCC_I2C3_CLKSOURCE (*)
(*) value not defined in all devices.
Return values:
Returned value can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE_HSI
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK
  • LL_RCC_I2C2_CLKSOURCE_HSI (*)
  • LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
  • LL_RCC_I2C3_CLKSOURCE_HSI (*)
  • LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
(*) value not defined in all devices.

Definition at line 1842 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetSDADCClockSource ( uint32_t SDADCx )

Get SDADCx clock source.

Reference Manual to LL API cross reference:
CFGR SDPRE LL_RCC_GetSDADCClockSource
Parameters:
SDADCx This parameter can be one of the following values:
  • LL_RCC_SDADC_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_1
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_2
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_4
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_6
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_8
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_10
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_12
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_14
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_16
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_20
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_24
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_28
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_32
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_36
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_40
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_44
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_48

Definition at line 2077 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetSDADCClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource ( uint32_t USARTx )

Get USARTx clock source.

Reference Manual to LL API cross reference:
CFGR3 USART1SW LL_RCC_GetUSARTClockSource
CFGR3 USART2SW LL_RCC_GetUSARTClockSource
CFGR3 USART3SW LL_RCC_GetUSARTClockSource
Parameters:
USARTx This parameter can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE
  • LL_RCC_USART2_CLKSOURCE (*)
  • LL_RCC_USART3_CLKSOURCE (*)
(*) value not defined in all devices.
Return values:
Returned value can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE_PCLK1 (*)
  • LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
  • LL_RCC_USART1_CLKSOURCE_SYSCLK
  • LL_RCC_USART1_CLKSOURCE_LSE
  • LL_RCC_USART1_CLKSOURCE_HSI
  • LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
  • LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
  • LL_RCC_USART2_CLKSOURCE_LSE (*)
  • LL_RCC_USART2_CLKSOURCE_HSI (*)
  • LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
  • LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
  • LL_RCC_USART3_CLKSOURCE_LSE (*)
  • LL_RCC_USART3_CLKSOURCE_HSI (*)
(*) value not defined in all devices.

Definition at line 1792 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource ( uint32_t USBx )

Get USBx clock source.

Reference Manual to LL API cross reference:
CFGR USBPRE LL_RCC_GetUSBClockSource
Parameters:
USBx This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_USB_CLKSOURCE_PLL
  • LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5

Definition at line 1953 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

__STATIC_INLINE void LL_RCC_SetADCClockSource ( uint32_t ADCxSource )

Configure ADC clock source.

Reference Manual to LL API cross reference:
CFGR ADCPRE LL_RCC_SetADCClockSource
Parameters:
ADCxSource This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
Return values:
None

Definition at line 1658 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetCECClockSource ( uint32_t CECxSource )

Configure CEC clock source.

Reference Manual to LL API cross reference:
CFGR3 CECSW LL_RCC_SetCECClockSource
Parameters:
CECxSource This parameter can be one of the following values:
  • LL_RCC_CEC_CLKSOURCE_HSI_DIV244
  • LL_RCC_CEC_CLKSOURCE_LSE
Return values:
None

Definition at line 1626 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetI2CClockSource ( uint32_t I2CxSource )

Configure I2Cx clock source.

Reference Manual to LL API cross reference:
CFGR3 I2C1SW LL_RCC_SetI2CClockSource
CFGR3 I2C2SW LL_RCC_SetI2CClockSource
CFGR3 I2C3SW LL_RCC_SetI2CClockSource
Parameters:
I2CxSource This parameter can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE_HSI
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK
  • LL_RCC_I2C2_CLKSOURCE_HSI (*)
  • LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
  • LL_RCC_I2C3_CLKSOURCE_HSI (*)
  • LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1544 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetSDADCClockSource ( uint32_t SDADCxSource )

Configure SDADCx clock source.

Reference Manual to LL API cross reference:
CFGR SDPRE LL_RCC_SetSDADCClockSource
Parameters:
SDADCxSource This parameter can be one of the following values:
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_1
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_2
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_4
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_6
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_8
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_10
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_12
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_14
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_16
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_20
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_24
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_28
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_32
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_36
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_40
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_44
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_48
Return values:
None

Definition at line 1758 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetUSARTClockSource ( uint32_t USARTxSource )

Configure USARTx clock source.

Reference Manual to LL API cross reference:
CFGR3 USART1SW LL_RCC_SetUSARTClockSource
CFGR3 USART2SW LL_RCC_SetUSARTClockSource
CFGR3 USART3SW LL_RCC_SetUSARTClockSource
Parameters:
USARTxSource This parameter can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE_PCLK1 (*)
  • LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
  • LL_RCC_USART1_CLKSOURCE_SYSCLK
  • LL_RCC_USART1_CLKSOURCE_LSE
  • LL_RCC_USART1_CLKSOURCE_HSI
  • LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
  • LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
  • LL_RCC_USART2_CLKSOURCE_LSE (*)
  • LL_RCC_USART2_CLKSOURCE_HSI (*)
  • LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
  • LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
  • LL_RCC_USART3_CLKSOURCE_LSE (*)
  • LL_RCC_USART3_CLKSOURCE_HSI (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1501 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetUSBClockSource ( uint32_t USBxSource )

Configure USB clock source.

Reference Manual to LL API cross reference:
CFGR USBPRE LL_RCC_SetUSBClockSource
Parameters:
USBxSource This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE_PLL
  • LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5
Return values:
None

Definition at line 1641 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC

Functions
RTC
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetRTCClockSource (uint32_t Source)
Set RTC Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_GetRTCClockSource (void)
Get RTC Clock Source.
__STATIC_INLINE void | LL_RCC_EnableRTC (void)
Enable RTC.
__STATIC_INLINE void | LL_RCC_DisableRTC (void)
Disable RTC.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledRTC (void)
Check if RTC has been enabled or not.
__STATIC_INLINE void | LL_RCC_ForceBackupDomainReset (void)
Force the Backup domain reset.
__STATIC_INLINE void | LL_RCC_ReleaseBackupDomainReset (void)
Release the Backup domain reset.

Function Documentation

__STATIC_INLINE void LL_RCC_DisableRTC ( void )

Disable RTC.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_DisableRTC
Return values:
None

Definition at line 2137 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableRTC ( void )

Enable RTC.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_EnableRTC
Return values:
None

Definition at line 2127 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ForceBackupDomainReset ( void )

Force the Backup domain reset.

Reference Manual to LL API cross reference:
BDCR BDRST LL_RCC_ForceBackupDomainReset
Return values:
None

Definition at line 2157 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource ( void )

Get RTC Clock Source.

Reference Manual to LL API cross reference:
BDCR RTCSEL LL_RCC_GetRTCClockSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_RTC_CLKSOURCE_NONE
  • LL_RCC_RTC_CLKSOURCE_LSE
  • LL_RCC_RTC_CLKSOURCE_LSI
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32

Definition at line 2117 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC ( void )

Check if RTC has been enabled or not.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_IsEnabledRTC
Return values:
State of bit (1 or 0).

Definition at line 2147 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset ( void )

Release the Backup domain reset.

Reference Manual to LL API cross reference:
BDCR BDRST LL_RCC_ReleaseBackupDomainReset
Return values:
None

Definition at line 2167 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetRTCClockSource ( uint32_t Source )

Set RTC Clock Source.

Note:
Once the RTC clock source has been selected, it cannot be changed any more unless the Backup domain is reset. The BDRST bit can be used to reset them.
Reference Manual to LL API cross reference:
BDCR RTCSEL LL_RCC_SetRTCClockSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_RTC_CLKSOURCE_NONE
  • LL_RCC_RTC_CLKSOURCE_LSE
  • LL_RCC_RTC_CLKSOURCE_LSI
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32
Return values:
None

Definition at line 2103 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PLL

Functions
PLL
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_PLL_Enable (void)
Enable PLL.
__STATIC_INLINE void | LL_RCC_PLL_Disable (void)
Disable PLL.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsReady (void)
Check if PLL Ready.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SYS (uint32_t Source, uint32_t PLLMul)
Configure PLL used for SYSCLK Domain.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMainSource (void)
Get the oscillator used as PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMultiplicator (void)
Get PLL multiplication Factor.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetPrediv (void)
Get PREDIV division factor for the main PLL.

Function Documentation

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS | ( | uint32_t | Source,
 |  | uint32_t | PLLMul
 | ) |  |

Configure PLL used for SYSCLK Domain.

Reference Manual to LL API cross reference:
CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS
CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS
CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_HSI_DIV_2
  • LL_RCC_PLLSOURCE_HSE_DIV_1
  • LL_RCC_PLLSOURCE_HSE_DIV_2
  • LL_RCC_PLLSOURCE_HSE_DIV_3
  • LL_RCC_PLLSOURCE_HSE_DIV_4
  • LL_RCC_PLLSOURCE_HSE_DIV_5
  • LL_RCC_PLLSOURCE_HSE_DIV_6
  • LL_RCC_PLLSOURCE_HSE_DIV_7
  • LL_RCC_PLLSOURCE_HSE_DIV_8
  • LL_RCC_PLLSOURCE_HSE_DIV_9
  • LL_RCC_PLLSOURCE_HSE_DIV_10
  • LL_RCC_PLLSOURCE_HSE_DIV_11
  • LL_RCC_PLLSOURCE_HSE_DIV_12
  • LL_RCC_PLLSOURCE_HSE_DIV_13
  • LL_RCC_PLLSOURCE_HSE_DIV_14
  • LL_RCC_PLLSOURCE_HSE_DIV_15
  • LL_RCC_PLLSOURCE_HSE_DIV_16
PLLMul This parameter can be one of the following values:
  • LL_RCC_PLL_MUL_2
  • LL_RCC_PLL_MUL_3
  • LL_RCC_PLL_MUL_4
  • LL_RCC_PLL_MUL_5
  • LL_RCC_PLL_MUL_6
  • LL_RCC_PLL_MUL_7
  • LL_RCC_PLL_MUL_8
  • LL_RCC_PLL_MUL_9
  • LL_RCC_PLL_MUL_10
  • LL_RCC_PLL_MUL_11
  • LL_RCC_PLL_MUL_12
  • LL_RCC_PLL_MUL_13
  • LL_RCC_PLL_MUL_14
  • LL_RCC_PLL_MUL_15
  • LL_RCC_PLL_MUL_16
Return values:
None

Definition at line 2304 of file stm32f3xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

__STATIC_INLINE void LL_RCC_PLL_Disable ( void )

Disable PLL.

Note:
Cannot be disabled if the PLL clock is used as the system clock
Reference Manual to LL API cross reference:
CR PLLON LL_RCC_PLL_Disable
Return values:
None

Definition at line 2196 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_Enable ( void )

Enable PLL.

Reference Manual to LL API cross reference:
CR PLLON LL_RCC_PLL_Enable
Return values:
None

Definition at line 2185 of file stm32f3xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource ( void )

Get the oscillator used as PLL clock source.

Reference Manual to LL API cross reference:
CFGR PLLSRC LL_RCC_PLL_GetMainSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLSOURCE_HSI (*)
  • LL_RCC_PLLSOURCE_HSI_DIV_2 (*)
  • LL_RCC_PLLSOURCE_HSE
(*) value not defined in all devices

Definition at line 2321 of file stm32f3xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SYS().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator ( void )

Get PLL multiplication Factor.

Reference Manual to LL API cross reference:
CFGR PLLMUL LL_RCC_PLL_GetMultiplicator
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLL_MUL_2
  • LL_RCC_PLL_MUL_3
  • LL_RCC_PLL_MUL_4
  • LL_RCC_PLL_MUL_5
  • LL_RCC_PLL_MUL_6
  • LL_RCC_PLL_MUL_7
  • LL_RCC_PLL_MUL_8
  • LL_RCC_PLL_MUL_9
  • LL_RCC_PLL_MUL_10
  • LL_RCC_PLL_MUL_11
  • LL_RCC_PLL_MUL_12
  • LL_RCC_PLL_MUL_13
  • LL_RCC_PLL_MUL_14
  • LL_RCC_PLL_MUL_15
  • LL_RCC_PLL_MUL_16

Definition at line 2346 of file stm32f3xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SYS().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv ( void )

Get PREDIV division factor for the main PLL.

Note:
They can be written only when the PLL is disabled
Reference Manual to LL API cross reference:
CFGR2 PREDIV LL_RCC_PLL_GetPrediv
Return values:
Returned value can be one of the following values:
  • LL_RCC_PREDIV_DIV_1
  • LL_RCC_PREDIV_DIV_2
  • LL_RCC_PREDIV_DIV_3
  • LL_RCC_PREDIV_DIV_4
  • LL_RCC_PREDIV_DIV_5
  • LL_RCC_PREDIV_DIV_6
  • LL_RCC_PREDIV_DIV_7
  • LL_RCC_PREDIV_DIV_8
  • LL_RCC_PREDIV_DIV_9
  • LL_RCC_PREDIV_DIV_10
  • LL_RCC_PREDIV_DIV_11
  • LL_RCC_PREDIV_DIV_12
  • LL_RCC_PREDIV_DIV_13
  • LL_RCC_PREDIV_DIV_14
  • LL_RCC_PREDIV_DIV_15
  • LL_RCC_PREDIV_DIV_16

Definition at line 2373 of file stm32f3xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SYS().

__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady ( void )

Check if PLL Ready.

Reference Manual to LL API cross reference:
CR PLLRDY LL_RCC_PLL_IsReady
Return values:
State of bit (1 or 0).

Definition at line 2206 of file stm32f3xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq(), UTILS_EnablePLLAndSwitchSystem(), and UTILS_PLL_IsBusy().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLAG Management

Functions
FLAG Management
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_ClearFlag_LSIRDY (void)
Clear LSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSERDY (void)
Clear LSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSIRDY (void)
Clear HSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSERDY (void)
Clear HSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLRDY (void)
Clear PLL ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSECSS (void)
Clear Clock security system interrupt flag.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSIRDY (void)
Check if LSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSERDY (void)
Check if LSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSIRDY (void)
Check if HSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSERDY (void)
Check if HSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLRDY (void)
Check if PLL ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSECSS (void)
Check if Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_IWDGRST (void)
Check if RCC flag Independent Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LPWRRST (void)
Check if RCC flag Low Power reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_OBLRST (void)
Check if RCC flag is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PINRST (void)
Check if RCC flag Pin reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PORRST (void)
Check if RCC flag POR/PDR reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SFTRST (void)
Check if RCC flag Software reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_WWDGRST (void)
Check if RCC flag Window Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_V18PWRRST (void)
Check if RCC Reset flag of the 1.8 V domain is set or not.
__STATIC_INLINE void | LL_RCC_ClearResetFlags (void)
Set RMVF bit to clear the reset flags.

Function Documentation

__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS ( void )

Clear Clock security system interrupt flag.

Reference Manual to LL API cross reference:
CIR CSSC LL_RCC_ClearFlag_HSECSS
Return values:
None

Definition at line 2441 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY ( void )

Clear HSE ready interrupt flag.

Reference Manual to LL API cross reference:
CIR HSERDYC LL_RCC_ClearFlag_HSERDY
Return values:
None

Definition at line 2421 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY ( void )

Clear HSI ready interrupt flag.

Reference Manual to LL API cross reference:
CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
Return values:
None

Definition at line 2411 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY ( void )

Clear LSE ready interrupt flag.

Reference Manual to LL API cross reference:
CIR LSERDYC LL_RCC_ClearFlag_LSERDY
Return values:
None

Definition at line 2401 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY ( void )

Clear LSI ready interrupt flag.

Reference Manual to LL API cross reference:
CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
Return values:
None

Definition at line 2391 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY ( void )

Clear PLL ready interrupt flag.

Reference Manual to LL API cross reference:
CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
Return values:
None

Definition at line 2431 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearResetFlags ( void )

Set RMVF bit to clear the reset flags.

Reference Manual to LL API cross reference:
CSR RMVF LL_RCC_ClearResetFlags
Return values:
None

Definition at line 2605 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS ( void )

Check if Clock security system interrupt occurred or not.

Reference Manual to LL API cross reference:
CIR CSSF LL_RCC_IsActiveFlag_HSECSS
Return values:
State of bit (1 or 0).

Definition at line 2513 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY ( void )

Check if HSE ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
Return values:
State of bit (1 or 0).

Definition at line 2481 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY ( void )

Check if HSI ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
Return values:
State of bit (1 or 0).

Definition at line 2471 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST ( void )

Check if RCC flag Independent Watchdog reset is set or not.

Reference Manual to LL API cross reference:
CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
Return values:
State of bit (1 or 0).

Definition at line 2523 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST ( void )

Check if RCC flag Low Power reset is set or not.

Reference Manual to LL API cross reference:
CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
Return values:
State of bit (1 or 0).

Definition at line 2533 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY ( void )

Check if LSE ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
Return values:
State of bit (1 or 0).

Definition at line 2461 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY ( void )

Check if LSI ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
Return values:
State of bit (1 or 0).

Definition at line 2451 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST ( void )

Check if RCC flag is set or not.

Reference Manual to LL API cross reference:
CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
Return values:
State of bit (1 or 0).

Definition at line 2543 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST ( void )

Check if RCC flag Pin reset is set or not.

Reference Manual to LL API cross reference:
CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
Return values:
State of bit (1 or 0).

Definition at line 2553 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY ( void )

Check if PLL ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
Return values:
State of bit (1 or 0).

Definition at line 2503 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST ( void )

Check if RCC flag POR/PDR reset is set or not.

Reference Manual to LL API cross reference:
CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
Return values:
State of bit (1 or 0).

Definition at line 2563 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST ( void )

Check if RCC flag Software reset is set or not.

Reference Manual to LL API cross reference:
CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
Return values:
State of bit (1 or 0).

Definition at line 2573 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST ( void )

Check if RCC Reset flag of the 1.8 V domain is set or not.

Reference Manual to LL API cross reference:
CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST
Return values:
State of bit (1 or 0).

Definition at line 2594 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST ( void )

Check if RCC flag Window Watchdog reset is set or not.

Reference Manual to LL API cross reference:
CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
Return values:
State of bit (1 or 0).

Definition at line 2583 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IT Management

Functions
IT Management
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_EnableIT_LSIRDY (void)
Enable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSERDY (void)
Enable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSIRDY (void)
Enable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSERDY (void)
Enable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLRDY (void)
Enable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSIRDY (void)
Disable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSERDY (void)
Disable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSIRDY (void)
Disable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSERDY (void)
Disable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLRDY (void)
Disable PLL ready interrupt.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSIRDY (void)
Checks if LSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSERDY (void)
Checks if LSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSIRDY (void)
Checks if HSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSERDY (void)
Checks if HSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLRDY (void)
Checks if PLL ready interrupt source is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_RCC_DisableIT_HSERDY ( void )

Disable HSE ready interrupt.

Reference Manual to LL API cross reference:
CIR HSERDYIE LL_RCC_DisableIT_HSERDY
Return values:
None

Definition at line 2703 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY ( void )

Disable HSI ready interrupt.

Reference Manual to LL API cross reference:
CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
Return values:
None

Definition at line 2693 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSERDY ( void )

Disable LSE ready interrupt.

Reference Manual to LL API cross reference:
CIR LSERDYIE LL_RCC_DisableIT_LSERDY
Return values:
None

Definition at line 2683 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY ( void )

Disable LSI ready interrupt.

Reference Manual to LL API cross reference:
CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
Return values:
None

Definition at line 2673 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY ( void )

Disable PLL ready interrupt.

Reference Manual to LL API cross reference:
CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
Return values:
None

Definition at line 2713 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSERDY ( void )

Enable HSE ready interrupt.

Reference Manual to LL API cross reference:
CIR HSERDYIE LL_RCC_EnableIT_HSERDY
Return values:
None

Definition at line 2653 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY ( void )

Enable HSI ready interrupt.

Reference Manual to LL API cross reference:
CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
Return values:
None

Definition at line 2643 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSERDY ( void )

Enable LSE ready interrupt.

Reference Manual to LL API cross reference:
CIR LSERDYIE LL_RCC_EnableIT_LSERDY
Return values:
None

Definition at line 2633 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY ( void )

Enable LSI ready interrupt.

Reference Manual to LL API cross reference:
CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
Return values:
None

Definition at line 2623 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY ( void )

Enable PLL ready interrupt.

Reference Manual to LL API cross reference:
CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
Return values:
None

Definition at line 2663 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY ( void )

Checks if HSE ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
Return values:
State of bit (1 or 0).

Definition at line 2753 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY ( void )

Checks if HSI ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
Return values:
State of bit (1 or 0).

Definition at line 2743 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY ( void )

Checks if LSE ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
Return values:
State of bit (1 or 0).

Definition at line 2733 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY ( void )

Checks if LSI ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
Return values:
State of bit (1 or 0).

Definition at line 2723 of file stm32f3xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY ( void )

Checks if PLL ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
Return values:
State of bit (1 or 0).

Definition at line 2763 of file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: De-initialization function

Functions
De-initialization function
RCC Exported Functions

Functions

ErrorStatus LL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.

Function Documentation

ErrorStatus LL_RCC_DeInit ( void )

Reset the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • HSI ON and used as system clock source
  • HSE and PLL OFF
  • AHB, APB1 and APB2 prescaler set to 1.
  • CSS, MCO OFF
  • All interrupts disabled
This function doesn't modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RCC registers are de-initialized
  • ERROR: not applicable

Definition at line 240 of file stm32f3xx_ll_rcc.c.

References LL_RCC_CIR_CSSC, LL_RCC_CIR_HSERDYC, LL_RCC_CIR_HSIRDYC, LL_RCC_CIR_LSERDYC, LL_RCC_CIR_LSIRDYC, LL_RCC_CIR_PLLRDYC, LL_RCC_HSE_DisableBypass(), LL_RCC_HSI_Enable(), LL_RCC_HSI_SetCalibTrimming(), and LL_RCC_WriteReg.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Get system and peripherals clocks frequency functions

Functions
Get system and peripherals clocks frequency functions
RCC Exported Functions

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks and different peripheral clocks available on the device. More...

Functions

void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.
uint32_t | LL_RCC_GetSDADCClockFreq (uint32_t SDADCxSource)
Return SDADCx clock frequency.
uint32_t | LL_RCC_GetCECClockFreq (uint32_t CECxSource)
Return CECx clock frequency.
uint32_t | LL_RCC_GetHRTIMClockFreq (uint32_t HRTIMxSource)

Detailed Description

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks and different peripheral clocks available on the device.

Note:
If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
If SYSCLK source is PLL, function returns values based on HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
(**) HSI_VALUE is a defined constant but the real value may vary depending on the variations in voltage and temperature.
(***) HSE_VALUE is a defined constant, user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be incorrect when using fractional value for HSE crystal.
This function can be used by the user application to compute the baud-rate for the communication peripherals or configure other parameters.

Function Documentation

uint32_t LL_RCC_GetADCClockFreq ( uint32_t ADCxSource )

Return ADCx clock frequency.

Parameters:
ADCxSource This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE (*)
  • LL_RCC_ADC1_CLKSOURCE (*)
  • LL_RCC_ADC12_CLKSOURCE (*)
  • LL_RCC_ADC34_CLKSOURCE (*)
(*) value not defined in all devices
Return values:
ADC clock frequency (in Hz)

Definition at line 697 of file stm32f3xx_ll_rcc.c.

References assert_param, IS_LL_RCC_ADC_CLKSOURCE, LL_RCC_GetADCClockSource(), LL_RCC_PERIPH_FREQUENCY_NO, RCC_GetHCLKClockFreq(), RCC_GetPCLK2ClockFreq(), and RCC_GetSystemClockFreq().

uint32_t LL_RCC_GetCECClockFreq ( uint32_t CECxSource )

Return CECx clock frequency.

Parameters:
CECxSource This parameter can be one of the following values:
  • LL_RCC_CEC_CLKSOURCE
Return values:
CEC clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready

Definition at line 764 of file stm32f3xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_CEC_CLKSOURCE, LL_RCC_CEC_CLKSOURCE_HSI_DIV244, LL_RCC_CEC_CLKSOURCE_LSE, LL_RCC_GetCECClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_LSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, and LSE_VALUE.

uint32_t LL_RCC_GetHRTIMClockFreq ( uint32_t HRTIMxSource )
uint32_t LL_RCC_GetI2CClockFreq ( uint32_t I2CxSource )

Return I2Cx clock frequency.

Parameters:
I2CxSource This parameter can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE
  • LL_RCC_I2C2_CLKSOURCE (*)
  • LL_RCC_I2C3_CLKSOURCE (*)
(*) value not defined in all devices
Return values:
I2C clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready

Definition at line 545 of file stm32f3xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_I2C_CLKSOURCE, LL_RCC_GetI2CClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_I2C1_CLKSOURCE, LL_RCC_I2C1_CLKSOURCE_HSI, LL_RCC_I2C1_CLKSOURCE_SYSCLK, LL_RCC_I2C2_CLKSOURCE, LL_RCC_I2C2_CLKSOURCE_HSI, LL_RCC_I2C2_CLKSOURCE_SYSCLK, LL_RCC_PERIPH_FREQUENCY_NO, and RCC_GetSystemClockFreq().

uint32_t LL_RCC_GetSDADCClockFreq ( uint32_t SDADCxSource )

Return SDADCx clock frequency.

Parameters:
SDADCxSource This parameter can be one of the following values:
  • LL_RCC_SDADC_CLKSOURCE
Return values:
SDADC clock frequency (in Hz)

Definition at line 737 of file stm32f3xx_ll_rcc.c.

References aSDADCPrescTable, assert_param, IS_LL_RCC_SDADC_CLKSOURCE, LL_RCC_GetSDADCClockSource(), LL_RCC_PERIPH_FREQUENCY_NO, and RCC_GetSystemClockFreq().

void LL_RCC_GetSystemClocksFreq ( LL_RCC_ClocksTypeDef * RCC_Clocks )

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.

Note:
Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update structure fields. Otherwise, any configuration based on this function will be incorrect.
Parameters:
RCC_Clocks pointer to a LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
Return values:
None

Definition at line 313 of file stm32f3xx_ll_rcc.c.

References LL_RCC_ClocksTypeDef::HCLK_Frequency, LL_RCC_ClocksTypeDef::PCLK1_Frequency, LL_RCC_ClocksTypeDef::PCLK2_Frequency, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), RCC_GetPCLK2ClockFreq(), RCC_GetSystemClockFreq(), and LL_RCC_ClocksTypeDef::SYSCLK_Frequency.

Referenced by LL_I2S_Init(), and LL_USART_Init().

uint32_t LL_RCC_GetUSARTClockFreq ( uint32_t USARTxSource )

Return USARTx clock frequency.

Parameters:
USARTxSource This parameter can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE
  • LL_RCC_USART2_CLKSOURCE (*)
  • LL_RCC_USART3_CLKSOURCE (*)
(*) value not defined in all devices.
Return values:
USART clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready

Definition at line 339 of file stm32f3xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_USART_CLKSOURCE, LL_RCC_GetUSARTClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_LSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_USART1_CLKSOURCE, LL_RCC_USART1_CLKSOURCE_HSI, LL_RCC_USART1_CLKSOURCE_LSE, LL_RCC_USART1_CLKSOURCE_PCLK2, LL_RCC_USART1_CLKSOURCE_SYSCLK, LL_RCC_USART2_CLKSOURCE, LL_RCC_USART2_CLKSOURCE_HSI, LL_RCC_USART2_CLKSOURCE_LSE, LL_RCC_USART2_CLKSOURCE_PCLK1, LL_RCC_USART2_CLKSOURCE_SYSCLK, LL_RCC_USART3_CLKSOURCE, LL_RCC_USART3_CLKSOURCE_HSI, LL_RCC_USART3_CLKSOURCE_LSE, LL_RCC_USART3_CLKSOURCE_PCLK1, LL_RCC_USART3_CLKSOURCE_SYSCLK, LSE_VALUE, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), RCC_GetPCLK2ClockFreq(), and RCC_GetSystemClockFreq().

Referenced by LL_USART_Init().

uint32_t LL_RCC_GetUSBClockFreq ( uint32_t USBxSource )

Return USBx clock frequency.

Parameters:
USBxSource This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE
Return values:
USB clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected

Definition at line 655 of file stm32f3xx_ll_rcc.c.

References assert_param, IS_LL_RCC_USB_CLKSOURCE, LL_RCC_GetUSBClockSource(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsReady(), LL_RCC_USB_CLKSOURCE_PLL, LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5, and RCC_PLL_GetFreqDomain_SYS().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC_LL_Private_Variables

Variables
RCC_LL_Private_Variables
RCC

Variables

const uint8_t aSDADCPrescTable [16] = {2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U}

Variable Documentation

const uint8_t aSDADCPrescTable[16] = {2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U}

Definition at line 63 of file stm32f3xx_ll_rcc.c.

Referenced by LL_RCC_GetSDADCClockFreq().

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC

Modules
RTC
STM32F3xx_LL_Driver

Modules

RTC Private Constants
RTC Private Macros
RTC Exported Init structure
RTC Exported Constants
RTC Exported Macros
RTC Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for RTC registers.

Register | Bit | Function
ALRMAR | DT | LL_RTC_ALMA_GetDay
 |  | LL_RTC_ALMA_SetDay
 | DU | LL_RTC_ALMA_GetDay
 |  | LL_RTC_ALMA_GetWeekDay
 |  | LL_RTC_ALMA_SetDay
 |  | LL_RTC_ALMA_SetWeekDay
 | HT | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetHour
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetHour
 | HU | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetHour
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetHour
 | MNT | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetMinute
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetMinute
 | MNU | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetMinute
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetMinute
 | MSK1 | LL_RTC_ALMA_GetMask
 |  | LL_RTC_ALMA_SetMask
 | MSK2 | LL_RTC_ALMA_GetMask
 |  | LL_RTC_ALMA_SetMask
 | MSK3 | LL_RTC_ALMA_GetMask
 |  | LL_RTC_ALMA_SetMask
 | MSK4 | LL_RTC_ALMA_GetMask
 |  | LL_RTC_ALMA_SetMask
 | PM | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetTimeFormat
 |  | LL_RTC_ALMA_SetTimeFormat
 | ST | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetSecond
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetSecond
 | SU | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetSecond
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetSecond
 | WDSEL | LL_RTC_ALMA_DisableWeekday
 |  | LL_RTC_ALMA_EnableWeekday
ALRMASSR | MASKSS | LL_RTC_ALMA_GetSubSecondMask
 |  | LL_RTC_ALMA_SetSubSecondMask
 | SS | LL_RTC_ALMA_GetSubSecond
 |  | LL_RTC_ALMA_SetSubSecond
ALRMBR | DT | LL_RTC_ALMB_GetDay
 |  | LL_RTC_ALMB_SetDay
 | DU | LL_RTC_ALMB_GetDay
 |  | LL_RTC_ALMB_GetWeekDay
 |  | LL_RTC_ALMB_SetDay
 |  | LL_RTC_ALMB_SetWeekDay
 | HT | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetHour
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetHour
 | HU | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetHour
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetHour
 | MNT | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetMinute
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetMinute
 | MNU | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetMinute
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetMinute
 | MSK1 | LL_RTC_ALMB_GetMask
 |  | LL_RTC_ALMB_SetMask
 | MSK2 | LL_RTC_ALMB_GetMask
 |  | LL_RTC_ALMB_SetMask
 | MSK3 | LL_RTC_ALMB_GetMask
 |  | LL_RTC_ALMB_SetMask
 | MSK4 | LL_RTC_ALMB_GetMask
 |  | LL_RTC_ALMB_SetMask
 | PM | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetTimeFormat
 |  | LL_RTC_ALMB_SetTimeFormat
 | ST | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetSecond
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetSecond
 | SU | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetSecond
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetSecond
 | WDSEL | LL_RTC_ALMB_DisableWeekday
 |  | LL_RTC_ALMB_EnableWeekday
ALRMBSSR | MASKSS | LL_RTC_ALMB_GetSubSecondMask
 |  | LL_RTC_ALMB_SetSubSecondMask
 | SS | LL_RTC_ALMB_GetSubSecond
 |  | LL_RTC_ALMB_SetSubSecond
BKPxR | BKP | LL_RTC_BAK_GetRegister
 |  | LL_RTC_BAK_SetRegister
CALR | CALM | LL_RTC_CAL_GetMinus
 |  | LL_RTC_CAL_SetMinus
 | CALP | LL_RTC_CAL_IsPulseInserted
 |  | LL_RTC_CAL_SetPulse
 | CALW16 | LL_RTC_CAL_GetPeriod
 |  | LL_RTC_CAL_SetPeriod
 | CALW8 | LL_RTC_CAL_GetPeriod
 |  | LL_RTC_CAL_SetPeriod
CR | ADD1H | LL_RTC_TIME_IncHour
 | ALRAE | LL_RTC_ALMA_Disable
 |  | LL_RTC_ALMA_Enable
 | ALRAIE | LL_RTC_DisableIT_ALRA
 |  | LL_RTC_EnableIT_ALRA
 |  | LL_RTC_IsEnabledIT_ALRA
 | ALRBE | LL_RTC_ALMB_Disable
 |  | LL_RTC_ALMB_Enable
 | ALRBIE | LL_RTC_DisableIT_ALRB
 |  | LL_RTC_EnableIT_ALRB
 |  | LL_RTC_IsEnabledIT_ALRB
 | BKP | LL_RTC_TIME_DisableDayLightStore
 |  | LL_RTC_TIME_EnableDayLightStore
 |  | LL_RTC_TIME_IsDayLightStoreEnabled
 | BYPSHAD | LL_RTC_DisableShadowRegBypass
 |  | LL_RTC_EnableShadowRegBypass
 |  | LL_RTC_IsShadowRegBypassEnabled
 | COE | LL_RTC_CAL_GetOutputFreq
 |  | LL_RTC_CAL_SetOutputFreq
 | COSEL | LL_RTC_CAL_GetOutputFreq
 |  | LL_RTC_CAL_SetOutputFreq
 | FMT | LL_RTC_GetHourFormat
 |  | LL_RTC_SetHourFormat
 | OSEL | LL_RTC_GetAlarmOutEvent
 |  | LL_RTC_SetAlarmOutEvent
 | POL | LL_RTC_GetOutputPolarity
 |  | LL_RTC_SetOutputPolarity
 | REFCKON | LL_RTC_DisableRefClock
 |  | LL_RTC_EnableRefClock
 | SUB1H | LL_RTC_TIME_DecHour
 | TSE | LL_RTC_TS_Disable
 |  | LL_RTC_TS_Enable
 | TSEDGE | LL_RTC_TS_GetActiveEdge
 |  | LL_RTC_TS_SetActiveEdge
 | TSIE | LL_RTC_DisableIT_TS
 |  | LL_RTC_EnableIT_TS
 |  | LL_RTC_IsEnabledIT_TS
 | WUCKSEL | LL_RTC_WAKEUP_GetClock
 |  | LL_RTC_WAKEUP_SetClock
 | WUTE | LL_RTC_WAKEUP_Disable
 |  | LL_RTC_WAKEUP_Enable
 |  | LL_RTC_WAKEUP_IsEnabled
 | WUTIE | LL_RTC_DisableIT_WUT
 |  | LL_RTC_EnableIT_WUT
 |  | LL_RTC_IsEnabledIT_WUT
DR | DT | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetDay
 |  | LL_RTC_DATE_SetDay
 | DU | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetDay
 |  | LL_RTC_DATE_SetDay
 | MT | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetMonth
 |  | LL_RTC_DATE_SetMonth
 | MU | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetMonth
 |  | LL_RTC_DATE_SetMonth
 | WDU | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetWeekDay
 |  | LL_RTC_DATE_SetWeekDay
 | YT | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetYear
 |  | LL_RTC_DATE_SetYear
 | YU | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetYear
 |  | LL_RTC_DATE_SetYear
ISR | ALRAF | LL_RTC_ClearFlag_ALRA
 |  | LL_RTC_IsActiveFlag_ALRA
 | ALRAWF | LL_RTC_IsActiveFlag_ALRAW
 | ALRBF | LL_RTC_ClearFlag_ALRB
 |  | LL_RTC_IsActiveFlag_ALRB
 | ALRBWF | LL_RTC_IsActiveFlag_ALRBW
 | INIT | LL_RTC_DisableInitMode
 |  | LL_RTC_EnableInitMode
 | INITF | LL_RTC_IsActiveFlag_INIT
 | INITS | LL_RTC_IsActiveFlag_INITS
 | RECALPF | LL_RTC_IsActiveFlag_RECALP
 | RSF | LL_RTC_ClearFlag_RS
 |  | LL_RTC_IsActiveFlag_RS
 | SHPF | LL_RTC_IsActiveFlag_SHP
 | TAMP1F | LL_RTC_ClearFlag_TAMP1
 |  | LL_RTC_IsActiveFlag_TAMP1
 | TAMP2F | LL_RTC_ClearFlag_TAMP2
 |  | LL_RTC_IsActiveFlag_TAMP2
 | TAMP3F | LL_RTC_ClearFlag_TAMP3
 |  | LL_RTC_IsActiveFlag_TAMP3
 | TSF | LL_RTC_ClearFlag_TS
 |  | LL_RTC_IsActiveFlag_TS
 | TSOVF | LL_RTC_ClearFlag_TSOV
 |  | LL_RTC_IsActiveFlag_TSOV
 | WUTF | LL_RTC_ClearFlag_WUT
 |  | LL_RTC_IsActiveFlag_WUT
 | WUTWF | LL_RTC_IsActiveFlag_WUTW
PRER | PREDIV_A | LL_RTC_GetAsynchPrescaler
 |  | LL_RTC_SetAsynchPrescaler
 | PREDIV_S | LL_RTC_GetSynchPrescaler
 |  | LL_RTC_SetSynchPrescaler
SHIFTR | ADD1S | LL_RTC_TIME_Synchronize
 | SUBFS | LL_RTC_TIME_Synchronize
SSR | SS | LL_RTC_TIME_GetSubSecond
TAFCR | ALARMOUTTYPE | LL_RTC_GetAlarmOutputType
 |  | LL_RTC_SetAlarmOutputType
 | PC13MODE | LL_RTC_DisablePushPullMode
 |  | LL_RTC_EnablePushPullMode
 | PC14MODE | LL_RTC_DisablePushPullMode
 |  | LL_RTC_EnablePushPullMode
 | PC14VALUE | LL_RTC_ResetOutputPin
 |  | LL_RTC_SetOutputPin
 | PC15MODE | LL_RTC_DisablePushPullMode
 |  | LL_RTC_EnablePushPullMode
 | PC15VALUE | LL_RTC_ResetOutputPin
 |  | LL_RTC_SetOutputPin
 | TAMP1E | LL_RTC_TAMPER_Disable
 |  | LL_RTC_TAMPER_Enable
 | TAMP1TRG | LL_RTC_TAMPER_DisableActiveLevel
 |  | LL_RTC_TAMPER_EnableActiveLevel
 | TAMP2E | LL_RTC_TAMPER_Disable
 |  | LL_RTC_TAMPER_Enable
 | TAMP2TRG | LL_RTC_TAMPER_DisableActiveLevel
 |  | LL_RTC_TAMPER_EnableActiveLevel
 | TAMP3E | LL_RTC_TAMPER_Disable
 |  | LL_RTC_TAMPER_Enable
 | TAMP3TRG | LL_RTC_TAMPER_DisableActiveLevel
 |  | LL_RTC_TAMPER_EnableActiveLevel
 | TAMPFLT | LL_RTC_TAMPER_GetFilterCount
 |  | LL_RTC_TAMPER_SetFilterCount
 | TAMPFREQ | LL_RTC_TAMPER_GetSamplingFreq
 |  | LL_RTC_TAMPER_SetSamplingFreq
 | TAMPIE | LL_RTC_DisableIT_TAMP
 |  | LL_RTC_EnableIT_TAMP
 |  | LL_RTC_IsEnabledIT_TAMP
 | TAMPPRCH | LL_RTC_TAMPER_GetPrecharge
 |  | LL_RTC_TAMPER_SetPrecharge
 | TAMPPUDIS | LL_RTC_TAMPER_DisablePullUp
 |  | LL_RTC_TAMPER_EnablePullUp
 | TAMPTS | LL_RTC_TS_DisableOnTamper
 |  | LL_RTC_TS_EnableOnTamper
TR | HT | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetHour
 |  | LL_RTC_TIME_SetHour
 | HU | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetHour
 |  | LL_RTC_TIME_SetHour
 | MNT | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetMinute
 |  | LL_RTC_TIME_SetMinute
 | MNU | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetMinute
 |  | LL_RTC_TIME_SetMinute
 | PM | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_GetFormat
 |  | LL_RTC_TIME_SetFormat
 | ST | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetSecond
 |  | LL_RTC_TIME_SetSecond
 | SU | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetSecond
 |  | LL_RTC_TIME_SetSecond
TSDR | DT | LL_RTC_TS_GetDate
 |  | LL_RTC_TS_GetDay
 | DU | LL_RTC_TS_GetDate
 |  | LL_RTC_TS_GetDay
 | MT | LL_RTC_TS_GetDate
 |  | LL_RTC_TS_GetMonth
 | MU | LL_RTC_TS_GetDate
 |  | LL_RTC_TS_GetMonth
 | WDU | LL_RTC_TS_GetDate
 |  | LL_RTC_TS_GetWeekDay
TSSSR | SS | LL_RTC_TS_GetSubSecond
TSTR | HT | LL_RTC_TS_GetHour
 |  | LL_RTC_TS_GetTime
 | HU | LL_RTC_TS_GetHour
 |  | LL_RTC_TS_GetTime
 | MNT | LL_RTC_TS_GetMinute
 |  | LL_RTC_TS_GetTime
 | MNU | LL_RTC_TS_GetMinute
 |  | LL_RTC_TS_GetTime
 | PM | LL_RTC_TS_GetTimeFormat
 | ST | LL_RTC_TS_GetSecond
 |  | LL_RTC_TS_GetTime
 | SU | LL_RTC_TS_GetSecond
 |  | LL_RTC_TS_GetTime
WPR | KEY | LL_RTC_DisableWriteProtection
 |  | LL_RTC_EnableWriteProtection
WUTR | WUT | LL_RTC_WAKEUP_GetAutoReload
 |  | LL_RTC_WAKEUP_SetAutoReload
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Private Constants

Defines
RTC Private Constants
RTC

Defines

#define | RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU
#define | RTC_SYNCH_PRESC_DEFAULT 0x000000FFU
#define | RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define | RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define | RTC_INIT_MASK 0xFFFFFFFFU
#define | RTC_RSF_MASK 0xFFFFFF5FU
#define | RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)
#define | RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
#define | RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
#define | RTC_OFFSET_WEEKDAY 24U
#define | RTC_OFFSET_DAY 16U
#define | RTC_OFFSET_MONTH 8U
#define | RTC_OFFSET_HOUR 16U
#define | RTC_OFFSET_MINUTE 8U

Define Documentation

#define RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU

Definition at line 63 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_StructInit().

#define RTC_INIT_MASK 0xFFFFFFFFU

Definition at line 64 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_EnableInitMode().

#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */

Definition at line 67 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_EnterInitMode().

#define RTC_OFFSET_DAY 16U

Definition at line 74 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_OFFSET_HOUR 16U

Definition at line 76 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime(), LL_RTC_ALMB_GetTime(), and LL_RTC_TIME_Get().

#define RTC_OFFSET_MINUTE 8U

Definition at line 77 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime(), LL_RTC_ALMB_GetTime(), and LL_RTC_TIME_Get().

#define RTC_OFFSET_MONTH 8U

Definition at line 75 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_OFFSET_WEEKDAY 24U

Definition at line 73 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_RSF_MASK 0xFFFFFF5FU

Definition at line 65 of file stm32f3xx_ll_rtc.h.

#define RTC_SYNCH_PRESC_DEFAULT 0x000000FFU

Definition at line 64 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_DeInit(), and LL_RTC_StructInit().

#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */

Definition at line 68 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_WaitForSynchro().

#define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)

Definition at line 68 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_EnableWriteProtection().

#define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)

Definition at line 69 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_DisableWriteProtection().

#define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)

Definition at line 70 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_DisableWriteProtection().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Private Macros

Defines
RTC Private Macros
RTC

Defines

#define | IS_LL_RTC_HOURFORMAT(__VALUE__)
#define | IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
#define | IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
#define | IS_LL_RTC_FORMAT(__VALUE__)
#define | IS_LL_RTC_TIME_FORMAT(__VALUE__)
#define | IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
#define | IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
#define | IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
#define | IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
#define | IS_LL_RTC_WEEKDAY(__VALUE__)
#define | IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
#define | IS_LL_RTC_MONTH(__VALUE__)
#define | IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
#define | IS_LL_RTC_ALMA_MASK(__VALUE__)
#define | IS_LL_RTC_ALMB_MASK(__VALUE__)
#define | IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__)
#define | IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__)

Define Documentation

#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL ( __SEL__ )
Value:
(((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
                                                  ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))

Definition at line 136 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init().

#define IS_LL_RTC_ALMA_MASK ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))

Definition at line 121 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init().

#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL ( __SEL__ )
Value:
(((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
                                                  ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))

Definition at line 139 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_ALMB_Init().

#define IS_LL_RTC_ALMB_MASK ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))

Definition at line 128 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_ALMB_Init().

#define IS_LL_RTC_ASYNCH_PREDIV ( __VALUE__ ) ((__VALUE__) <= 0x7FU)

Definition at line 81 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_DAY ( __DAY__ ) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))

Definition at line 104 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_DATE_Init().

#define IS_LL_RTC_FORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_FORMAT_BIN) \
                                  || ((__VALUE__) == LL_RTC_FORMAT_BCD))

Definition at line 85 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOUR12 ( __HOUR__ ) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))

Definition at line 91 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOUR24 ( __HOUR__ ) ((__HOUR__) <= 23U)

Definition at line 92 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOURFORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
                                      || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))

Definition at line 78 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_MINUTES ( __MINUTES__ ) ((__MINUTES__) <= 59U)

Definition at line 93 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_MONTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_MONTH_JANUARY) \
                                 || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
                                 || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
                                 || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
                                 || ((__VALUE__) == LL_RTC_MONTH_MAY) \
                                 || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
                                 || ((__VALUE__) == LL_RTC_MONTH_JULY) \
                                 || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
                                 || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
                                 || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
                                 || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
                                 || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))

Definition at line 106 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_DATE_Init().

#define IS_LL_RTC_SECONDS ( __SECONDS__ ) ((__SECONDS__) <= 59U)

Definition at line 94 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_SYNCH_PREDIV ( __VALUE__ ) ((__VALUE__) <= 0x7FFFU)

Definition at line 83 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_TIME_FORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
                                       || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))

Definition at line 88 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_WEEKDAY ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))

Definition at line 96 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_DATE_Init().

#define IS_LL_RTC_YEAR ( __YEAR__ ) ((__YEAR__) <= 99U)

Definition at line 119 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_DATE_Init().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_RTC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_InitTypeDef Struct Reference
RTC Exported Init structure

RTC Init structures definition. More...

#include <stm32f3xx_ll_rtc.h>

Data Fields

uint32_t | HourFormat
uint32_t | AsynchPrescaler
uint32_t | SynchPrescaler

Detailed Description

RTC Init structures definition.

Definition at line 102 of file stm32f3xx_ll_rtc.h.

Field Documentation

uint32_t LL_RTC_InitTypeDef::AsynchPrescaler

Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

This feature can be modified afterwards using unitary function LL_RTC_SetAsynchPrescaler().

Definition at line 110 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

uint32_t LL_RTC_InitTypeDef::HourFormat

Specifies the RTC Hours Format. This parameter can be a value of HOUR FORMAT

This feature can be modified afterwards using unitary function LL_RTC_SetHourFormat().

Definition at line 104 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

uint32_t LL_RTC_InitTypeDef::SynchPrescaler

Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF

This feature can be modified afterwards using unitary function LL_RTC_SetSynchPrescaler().

Definition at line 116 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_rtc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_RTC_TimeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_TimeTypeDef Struct Reference
RTC Exported Init structure

RTC Time structure definition. More...

#include <stm32f3xx_ll_rtc.h>

Data Fields

uint32_t | TimeFormat
uint8_t | Hours
uint8_t | Minutes
uint8_t | Seconds

Detailed Description

RTC Time structure definition.

Definition at line 126 of file stm32f3xx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_TimeTypeDef::Hours

Specifies the RTC Time Hours. This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the LL_RTC_TIME_FORMAT_PM is selected. This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the LL_RTC_TIME_FORMAT_AM_OR_24 is selected.

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetHour().

Definition at line 133 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint8_t LL_RTC_TimeTypeDef::Minutes

Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetMinute().

Definition at line 139 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint8_t LL_RTC_TimeTypeDef::Seconds

Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetSecond().

Definition at line 144 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint32_t LL_RTC_TimeTypeDef::TimeFormat

Specifies the RTC AM/PM Time. This parameter can be a value of TIME FORMAT

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetFormat().

Definition at line 128 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_rtc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_RTC_DateTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_DateTypeDef Struct Reference
RTC Exported Init structure

RTC Date structure definition. More...

#include <stm32f3xx_ll_rtc.h>

Data Fields

uint8_t | WeekDay
uint8_t | Month
uint8_t | Day
uint8_t | Year

Detailed Description

RTC Date structure definition.

Definition at line 153 of file stm32f3xx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_DateTypeDef::Day

Specifies the RTC Date Day. This parameter must be a number between Min_Data = 1 and Max_Data = 31

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetDay().

Definition at line 165 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::Month

Specifies the RTC Date Month. This parameter can be a value of MONTH

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetMonth().

Definition at line 160 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::WeekDay

Specifies the RTC Date WeekDay. This parameter can be a value of WEEK DAY

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetWeekDay().

Definition at line 155 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::Year

Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetYear().

Definition at line 170 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_rtc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_RTC_AlarmTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_AlarmTypeDef Struct Reference
RTC Exported Init structure

RTC Alarm structure definition. More...

#include <stm32f3xx_ll_rtc.h>

Data Fields

LL_RTC_TimeTypeDef AlarmTime
uint32_t | AlarmMask
uint32_t | AlarmDateWeekDaySel
uint8_t | AlarmDateWeekDay

Detailed Description

RTC Alarm structure definition.

Definition at line 179 of file stm32f3xx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_AlarmTypeDef::AlarmDateWeekDay

Specifies the RTC Alarm Day/WeekDay. If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetDay() for ALARM A or LL_RTC_ALMB_SetDay() for ALARM B.

If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of WEEK DAY.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetWeekDay() for ALARM A or LL_RTC_ALMB_SetWeekDay() for ALARM B.

Definition at line 197 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

uint32_t LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel

Specifies the RTC Alarm is on day or WeekDay. This parameter can be a value of RTC Alarm A Date WeekDay for ALARM A or RTC Alarm B Date WeekDay for ALARM B

This feature can be modified afterwards using unitary function LL_RTC_ALMA_EnableWeekday() or LL_RTC_ALMA_DisableWeekday() for ALARM A or LL_RTC_ALMB_EnableWeekday() or LL_RTC_ALMB_DisableWeekday() for ALARM B

Definition at line 190 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

uint32_t LL_RTC_AlarmTypeDef::AlarmMask

Specifies the RTC Alarm Masks. This parameter can be a value of ALARMA MASK for ALARM A or ALARMB MASK for ALARM B.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetMask() for ALARM A or LL_RTC_ALMB_SetMask() for ALARM B

Definition at line 183 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

LL_RTC_TimeTypeDef LL_RTC_AlarmTypeDef::AlarmTime

Specifies the RTC Alarm Time members.

Definition at line 181 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_rtc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FORMAT

Defines
FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_FORMAT_BIN 0x000000000U
#define | LL_RTC_FORMAT_BCD 0x000000001U

Define Documentation

#define LL_RTC_FORMAT_BCD 0x000000001U

BCD data format

Definition at line 225 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_FORMAT_BIN 0x000000000U

Binary data format

Definition at line 224 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Alarm A Date WeekDay

Defines
RTC Alarm A Date WeekDay
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Define Documentation

#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U

Alarm A Date is selected

Definition at line 233 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), and LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Alarm A WeekDay is selected

Definition at line 234 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Alarm B Date WeekDay

Defines
RTC Alarm B Date WeekDay
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL

Define Documentation

#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U

Alarm B Date is selected

Definition at line 242 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL

Alarm B WeekDay is selected

Definition at line 243 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
RTC Exported Constants

Flags defines which can be used with LL_RTC_ReadReg function. More...

Defines

#define | LL_RTC_ISR_RECALPF RTC_ISR_RECALPF
#define | LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F
#define | LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F
#define | LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F
#define | LL_RTC_ISR_TSOVF RTC_ISR_TSOVF
#define | LL_RTC_ISR_TSF RTC_ISR_TSF
#define | LL_RTC_ISR_WUTF RTC_ISR_WUTF
#define | LL_RTC_ISR_ALRBF RTC_ISR_ALRBF
#define | LL_RTC_ISR_ALRAF RTC_ISR_ALRAF
#define | LL_RTC_ISR_INITF RTC_ISR_INITF
#define | LL_RTC_ISR_RSF RTC_ISR_RSF
#define | LL_RTC_ISR_INITS RTC_ISR_INITS
#define | LL_RTC_ISR_SHPF RTC_ISR_SHPF
#define | LL_RTC_ISR_WUTWF RTC_ISR_WUTWF
#define | LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF
#define | LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF

Detailed Description

Flags defines which can be used with LL_RTC_ReadReg function.

Define Documentation

#define LL_RTC_ISR_ALRAF RTC_ISR_ALRAF

Definition at line 262 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF

Definition at line 269 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ISR_ALRBF RTC_ISR_ALRBF

Definition at line 261 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF

Definition at line 268 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ISR_INITF RTC_ISR_INITF

Definition at line 263 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ISR_INITS RTC_ISR_INITS

Definition at line 265 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF

Definition at line 254 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ISR_RSF RTC_ISR_RSF

Definition at line 264 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ISR_SHPF RTC_ISR_SHPF

Definition at line 266 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F

Definition at line 257 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F

Definition at line 256 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F

Definition at line 255 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ISR_TSF RTC_ISR_TSF

Definition at line 259 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF

Definition at line 258 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ISR_WUTF RTC_ISR_WUTF

Definition at line 260 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF

Definition at line 267 of file stm32f3xx_ll_rtc.h.

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STM32F373xC HAL User Manual: IT Defines

Defines
IT Defines
RTC Exported Constants

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions. More...

Defines

#define | LL_RTC_CR_TSIE RTC_CR_TSIE
#define | LL_RTC_CR_WUTIE RTC_CR_WUTIE
#define | LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
#define | LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
#define | LL_RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE

Detailed Description

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions.

Define Documentation

#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE

Definition at line 281 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE

Definition at line 280 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_CR_TSIE RTC_CR_TSIE

Definition at line 278 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_CR_WUTIE RTC_CR_WUTIE

Definition at line 279 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE

Definition at line 282 of file stm32f3xx_ll_rtc.h.

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STM32F373xC HAL User Manual: WEEK DAY

Defines
WEEK DAY
RTC Exported Constants

Defines

#define | LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define | LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define | LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define | LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define | LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define | LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define | LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)

Define Documentation

#define LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)

Friday

Definition at line 294 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)

Monday

Definition at line 290 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_DATE_StructInit().

#define LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)

Saturday

Definition at line 295 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)

Sunday

Definition at line 296 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)

Thrusday

Definition at line 293 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)

Tuesday

Definition at line 291 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)

Wednesday

Definition at line 292 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: MONTH

Defines
MONTH
RTC Exported Constants

Defines

#define | LL_RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define | LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define | LL_RTC_MONTH_MARCH ((uint8_t)0x03U)
#define | LL_RTC_MONTH_APRIL ((uint8_t)0x04U)
#define | LL_RTC_MONTH_MAY ((uint8_t)0x05U)
#define | LL_RTC_MONTH_JUNE ((uint8_t)0x06U)
#define | LL_RTC_MONTH_JULY ((uint8_t)0x07U)
#define | LL_RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define | LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define | LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define | LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define | LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U)

Define Documentation

#define LL_RTC_MONTH_APRIL ((uint8_t)0x04U)

April

Definition at line 307 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_MONTH_AUGUST ((uint8_t)0x08U)

August

Definition at line 311 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U)

December

Definition at line 315 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U)

February

Definition at line 305 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_MONTH_JANUARY ((uint8_t)0x01U)

January

Definition at line 304 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_DATE_StructInit().

#define LL_RTC_MONTH_JULY ((uint8_t)0x07U)

July

Definition at line 310 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_MONTH_JUNE ((uint8_t)0x06U)

June

Definition at line 309 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_MONTH_MARCH ((uint8_t)0x03U)

March

Definition at line 306 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_MONTH_MAY ((uint8_t)0x05U)

May

Definition at line 308 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U)

November

Definition at line 314 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U)

October

Definition at line 313 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)

September

Definition at line 312 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HOUR FORMAT

Defines
HOUR FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_HOURFORMAT_24HOUR 0x00000000U
#define | LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT

Define Documentation

#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U

24 hour/day format

Definition at line 323 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_StructInit(), and LL_RTC_TIME_Init().

#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT

AM/PM hour format

Definition at line 324 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ALARM OUTPUT

Defines
ALARM OUTPUT
RTC Exported Constants

Defines

#define | LL_RTC_ALARMOUT_DISABLE 0x00000000U
#define | LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0
#define | LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1
#define | LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL

Define Documentation

#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0

Alarm A output enabled

Definition at line 333 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1

Alarm B output enabled

Definition at line 334 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ALARMOUT_DISABLE 0x00000000U

Output disabled

Definition at line 332 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL

Wakeup output enabled

Definition at line 335 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ALARM OUTPUT TYPE

Defines
ALARM OUTPUT TYPE
RTC Exported Constants

Defines

#define | LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U
#define | LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE

Define Documentation

#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U

RTC_ALARM, when mapped on PC13, is open-drain output

Definition at line 343 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE

RTC_ALARM, when mapped on PC13, is push-pull output

Definition at line 344 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PIN

Defines
PIN
RTC Exported Constants

Defines

#define | LL_RTC_PIN_PC13 RTC_TAFCR_PC13MODE
#define | LL_RTC_PIN_PC14 RTC_TAFCR_PC14MODE
#define | LL_RTC_PIN_PC15 RTC_TAFCR_PC15MODE

Define Documentation

#define LL_RTC_PIN_PC13 RTC_TAFCR_PC13MODE

PC13 is forced to push-pull output if all RTC alternate functions are disabled

Definition at line 352 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_PIN_PC14 RTC_TAFCR_PC14MODE

PC14 is forced to push-pull output if LSE is disabled

Definition at line 353 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_PIN_PC15 RTC_TAFCR_PC15MODE

PC15 is forced to push-pull output if LSE is disabled

Definition at line 354 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: OUTPUT POLARITY PIN

Defines
OUTPUT POLARITY PIN
RTC Exported Constants

Defines

#define | LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U
#define | LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL

Define Documentation

#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U

Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)

Definition at line 362 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL

Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)

Definition at line 363 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIME FORMAT

Defines
TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U
#define | LL_RTC_TIME_FORMAT_PM RTC_TR_PM

Define Documentation

#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U

AM or 24-hour format

Definition at line 371 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_TIME_StructInit().

#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM

PM

Definition at line 372 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SHIFT SECOND

Defines
SHIFT SECOND
RTC Exported Constants

Defines

#define | LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
#define | LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */

Define Documentation

#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */

Definition at line 381 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */

Definition at line 380 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ALARMA MASK

Defines
ALARMA MASK
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_MASK_NONE 0x00000000U
#define | LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3
#define | LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2
#define | LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1
#define | LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)

Define Documentation

#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)

Masks all

Definition at line 394 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4

Date/day do not care in Alarm A comparison

Definition at line 390 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3

Hours do not care in Alarm A comparison

Definition at line 391 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2

Minutes do not care in Alarm A comparison

Definition at line 392 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_NONE 0x00000000U

No masks applied on Alarm A

Definition at line 389 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1

Seconds do not care in Alarm A comparison

Definition at line 393 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ALARMA TIME FORMAT

Defines
ALARMA TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM

Define Documentation

#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U

AM or 24-hour format

Definition at line 402 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM

PM

Definition at line 403 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ALARMB MASK

Defines
ALARMB MASK
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_MASK_NONE 0x00000000U
#define | LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4
#define | LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3
#define | LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2
#define | LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1
#define | LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)

Define Documentation

#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)

Masks all

Definition at line 416 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4

Date/day do not care in Alarm B comparison

Definition at line 412 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3

Hours do not care in Alarm B comparison

Definition at line 413 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2

Minutes do not care in Alarm B comparison

Definition at line 414 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_NONE 0x00000000U

No masks applied on Alarm B

Definition at line 411 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1

Seconds do not care in Alarm B comparison

Definition at line 415 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ALARMB TIME FORMAT

Defines
ALARMB TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM

Define Documentation

#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U

AM or 24-hour format

Definition at line 424 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM

PM

Definition at line 425 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIMESTAMP EDGE

Defines
TIMESTAMP EDGE
RTC Exported Constants

Defines

#define | LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U
#define | LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE

Define Documentation

#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE

RTC_TS input falling edge generates a time-stamp even

Definition at line 434 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U

RTC_TS input rising edge generates a time-stamp event

Definition at line 433 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIMESTAMP TIME FORMAT

Defines
TIMESTAMP TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_TS_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM

Define Documentation

#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U

AM or 24-hour format

Definition at line 442 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM

PM

Definition at line 443 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TAMPER

Defines
TAMPER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_1 RTC_TAFCR_TAMP1E
#define | LL_RTC_TAMPER_2 RTC_TAFCR_TAMP2E
#define | LL_RTC_TAMPER_3 RTC_TAFCR_TAMP3E

Define Documentation

#define LL_RTC_TAMPER_1 RTC_TAFCR_TAMP1E

RTC_TAMP1 input detection

Definition at line 452 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_2 RTC_TAFCR_TAMP2E

RTC_TAMP2 input detection

Definition at line 455 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_3 RTC_TAFCR_TAMP3E

RTC_TAMP3 input detection

Definition at line 458 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TAMPER MASK

Defines
TAMPER MASK
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAFCR_TAMP1MF
#define | LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAFCR_TAMP2MF
#define | LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAFCR_TAMP3MF

Define Documentation

#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAFCR_TAMP1MF

Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased

Definition at line 468 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAFCR_TAMP2MF

Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased.

Definition at line 471 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAFCR_TAMP3MF

Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased

Definition at line 474 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TAMPER NO ERASE

Defines
TAMPER NO ERASE
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAFCR_TAMP1NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAFCR_TAMP2NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAFCR_TAMP3NOERASE

Define Documentation

#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAFCR_TAMP1NOERASE

Tamper 1 event does not erase the backup registers.

Definition at line 484 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAFCR_TAMP2NOERASE

Tamper 2 event does not erase the backup registers.

Definition at line 487 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAFCR_TAMP3NOERASE

Tamper 3 event does not erase the backup registers.

Definition at line 490 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TAMPER DURATION

Defines
TAMPER DURATION
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U
#define | LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0
#define | LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1
#define | LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAFCR_TAMPPRCH

Define Documentation

#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U

Tamper pins are pre-charged before sampling during 1 RTCCLK cycle

Definition at line 500 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0

Tamper pins are pre-charged before sampling during 2 RTCCLK cycles

Definition at line 501 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1

Tamper pins are pre-charged before sampling during 4 RTCCLK cycles

Definition at line 502 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAFCR_TAMPPRCH

Tamper pins are pre-charged before sampling during 8 RTCCLK cycles

Definition at line 503 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TAMPER FILTER

Defines
TAMPER FILTER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U
#define | LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0
#define | LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1
#define | LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAFCR_TAMPFLT

Define Documentation

#define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0

Tamper is activated after 2 consecutive samples at the active level

Definition at line 514 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1

Tamper is activated after 4 consecutive samples at the active level

Definition at line 515 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAFCR_TAMPFLT

Tamper is activated after 8 consecutive samples at the active level.

Definition at line 516 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U

Tamper filter is disabled

Definition at line 513 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TAMPER SAMPLING FREQUENCY DIVIDER

Defines
TAMPER SAMPLING FREQUENCY DIVIDER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U
#define | LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAFCR_TAMPFREQ_0
#define | LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAFCR_TAMPFREQ_1
#define | LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAFCR_TAMPFREQ_2
#define | LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_1)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAFCR_TAMPFREQ

Define Documentation

#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_0)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024

Definition at line 531 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAFCR_TAMPFREQ_0

Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384

Definition at line 527 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAFCR_TAMPFREQ_2

Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048

Definition at line 530 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAFCR_TAMPFREQ

Each of the tamper inputs are sampled with a frequency = RTCCLK / 256

Definition at line 533 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U

Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768

Definition at line 526 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_0)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096

Definition at line 529 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_1)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 512

Definition at line 532 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAFCR_TAMPFREQ_1

Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192

Definition at line 528 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TAMPER ACTIVE LEVEL

Defines
TAMPER ACTIVE LEVEL
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAFCR_TAMP1TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAFCR_TAMP2TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAFCR_TAMP3TRG

Define Documentation

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAFCR_TAMP1TRG

RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 543 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAFCR_TAMP2TRG

RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 546 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAFCR_TAMP3TRG

RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 549 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: WAKEUP CLOCK DIV

Defines
WAKEUP CLOCK DIV
RTC Exported Constants

Defines

#define | LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U
#define | LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1)
#define | LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)

Define Documentation

#define LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2)

ck_spre (usually 1 Hz) clock is selected

Definition at line 562 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)

ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value

Definition at line 563 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U

RTC/16 clock is selected

Definition at line 558 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)

RTC/2 clock is selected

Definition at line 561 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1)

RTC/4 clock is selected

Definition at line 560 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0)

RTC/8 clock is selected

Definition at line 559 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: BACKUP

Defines
BACKUP
RTC Exported Constants

Defines

#define | LL_RTC_BKP_DR0 0x00000000U
#define | LL_RTC_BKP_DR1 0x00000001U
#define | LL_RTC_BKP_DR2 0x00000002U
#define | LL_RTC_BKP_DR3 0x00000003U
#define | LL_RTC_BKP_DR4 0x00000004U
#define | LL_RTC_BKP_DR5 0x00000005U
#define | LL_RTC_BKP_DR6 0x00000006U
#define | LL_RTC_BKP_DR7 0x00000007U
#define | LL_RTC_BKP_DR8 0x00000008U
#define | LL_RTC_BKP_DR9 0x00000009U
#define | LL_RTC_BKP_DR10 0x0000000AU
#define | LL_RTC_BKP_DR11 0x0000000BU
#define | LL_RTC_BKP_DR12 0x0000000CU
#define | LL_RTC_BKP_DR13 0x0000000DU
#define | LL_RTC_BKP_DR14 0x0000000EU
#define | LL_RTC_BKP_DR15 0x0000000FU
#define | LL_RTC_BKP_DR16 0x00000010U
#define | LL_RTC_BKP_DR17 0x00000011U
#define | LL_RTC_BKP_DR18 0x00000012U
#define | LL_RTC_BKP_DR19 0x00000013U
#define | LL_RTC_BKP_DR20 0x00000014U
#define | LL_RTC_BKP_DR21 0x00000015U
#define | LL_RTC_BKP_DR22 0x00000016U
#define | LL_RTC_BKP_DR23 0x00000017U
#define | LL_RTC_BKP_DR24 0x00000018U
#define | LL_RTC_BKP_DR25 0x00000019U
#define | LL_RTC_BKP_DR26 0x0000001AU
#define | LL_RTC_BKP_DR27 0x0000001BU
#define | LL_RTC_BKP_DR28 0x0000001CU
#define | LL_RTC_BKP_DR29 0x0000001DU
#define | LL_RTC_BKP_DR30 0x0000001EU
#define | LL_RTC_BKP_DR31 0x0000001FU

Define Documentation

#define LL_RTC_BKP_DR0 0x00000000U

Definition at line 572 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR1 0x00000001U

Definition at line 573 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR10 0x0000000AU

Definition at line 583 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR11 0x0000000BU

Definition at line 584 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR12 0x0000000CU

Definition at line 585 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR13 0x0000000DU

Definition at line 586 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR14 0x0000000EU

Definition at line 587 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR15 0x0000000FU

Definition at line 588 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR16 0x00000010U

Definition at line 592 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR17 0x00000011U

Definition at line 593 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR18 0x00000012U

Definition at line 594 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR19 0x00000013U

Definition at line 595 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR2 0x00000002U

Definition at line 574 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR20 0x00000014U

Definition at line 599 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR21 0x00000015U

Definition at line 600 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR22 0x00000016U

Definition at line 601 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR23 0x00000017U

Definition at line 602 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR24 0x00000018U

Definition at line 603 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR25 0x00000019U

Definition at line 604 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR26 0x0000001AU

Definition at line 605 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR27 0x0000001BU

Definition at line 606 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR28 0x0000001CU

Definition at line 607 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR29 0x0000001DU

Definition at line 608 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR3 0x00000003U

Definition at line 575 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR30 0x0000001EU

Definition at line 609 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR31 0x0000001FU

Definition at line 610 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR4 0x00000004U

Definition at line 576 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR5 0x00000005U

Definition at line 578 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR6 0x00000006U

Definition at line 579 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR7 0x00000007U

Definition at line 580 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR8 0x00000008U

Definition at line 581 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_BKP_DR9 0x00000009U

Definition at line 582 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Calibration output

Defines
Calibration output
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_OUTPUT_NONE 0x00000000U
#define | LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)
#define | LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE)

Define Documentation

#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)

Calibration output is 1 Hz

Definition at line 621 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE)

Calibration output is 512 Hz

Definition at line 622 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U

Calibration output disabled

Definition at line 620 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Calibration pulse insertion

Defines
Calibration pulse insertion
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U
#define | LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP

Define Documentation

#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U

No RTCCLK pulses are added

Definition at line 630 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP

One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm)

Definition at line 631 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Calibration period

Defines
Calibration period
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_PERIOD_32SEC 0x00000000U
#define | LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8

Define Documentation

#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16

Use a 16-second calibration cycle period

Definition at line 640 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U

Use a 32-second calibration cycle period

Definition at line 639 of file stm32f3xx_ll_rtc.h.

#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8

Use a 8-second calibration cycle period

Definition at line 641 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
RTC Exported Macros

Defines

#define | LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RTC register.
#define | LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RTC register.

Define Documentation

#define LL_RTC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in RTC register.

Parameters:
__INSTANCE__ | RTC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 674 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_DeInit().

#define LL_RTC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in RTC register.

Parameters:
__INSTANCE__ | RTC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 666 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_DeInit().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Convert helper Macros

Defines
Convert helper Macros
RTC Exported Macros

Defines

#define | __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
Helper macro to convert a value from 2 digit decimal format to BCD format.
#define | __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))
Helper macro to convert a value from BCD format to 2 digit decimal format.

Define Documentation

#define __LL_RTC_CONVERT_BCD2BIN ( __VALUE__ ) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))

Helper macro to convert a value from BCD format to 2 digit decimal format.

Parameters:
__VALUE__ BCD value to be converted
Return values:
Converted byte

Definition at line 695 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

#define __LL_RTC_CONVERT_BIN2BCD ( __VALUE__ ) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))

Helper macro to convert a value from 2 digit decimal format to BCD format.

Parameters:
__VALUE__ Byte to be converted
Return values:
Converted byte

Definition at line 688 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Date helper Macros

Defines
Date helper Macros
RTC Exported Macros

Defines

#define | __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
Helper macro to retrieve weekday.
#define | __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
Helper macro to retrieve Year in BCD format.
#define | __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
Helper macro to retrieve Month in BCD format.
#define | __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
Helper macro to retrieve Day in BCD format.

Define Documentation

#define __LL_RTC_GET_DAY ( __RTC_DATE__ ) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)

Helper macro to retrieve Day in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Day in BCD format (0x01 . . . 0x31)

Definition at line 750 of file stm32f3xx_ll_rtc.h.

#define __LL_RTC_GET_MONTH ( __RTC_DATE__ ) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)

Helper macro to retrieve Month in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 743 of file stm32f3xx_ll_rtc.h.

#define __LL_RTC_GET_WEEKDAY ( __RTC_DATE__ ) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)

Helper macro to retrieve weekday.

Parameters:
__RTC_DATE__ Date returned by LL_RTC_DATE_Get function.
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 717 of file stm32f3xx_ll_rtc.h.

#define __LL_RTC_GET_YEAR ( __RTC_DATE__ ) ((__RTC_DATE__) & 0x000000FFU)

Helper macro to retrieve Year in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Year in BCD format (0x00 . . . 0x99)

Definition at line 724 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Time helper Macros

Defines
Time helper Macros
RTC Exported Macros

Defines

#define | __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
Helper macro to retrieve hour in BCD format.
#define | __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
Helper macro to retrieve minute in BCD format.
#define | __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
Helper macro to retrieve second in BCD format.

Define Documentation

#define __LL_RTC_GET_HOUR ( __RTC_TIME__ ) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)

Helper macro to retrieve hour in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)

Definition at line 765 of file stm32f3xx_ll_rtc.h.

#define __LL_RTC_GET_MINUTE ( __RTC_TIME__ ) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)

Helper macro to retrieve minute in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Minutes in BCD format (0x00. . .0x59)

Definition at line 772 of file stm32f3xx_ll_rtc.h.

#define __LL_RTC_GET_SECOND ( __RTC_TIME__ ) ((__RTC_TIME__) & 0x000000FFU)

Helper macro to retrieve second in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Seconds in format (0x00. . .0x59)

Definition at line 779 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration

Functions
Configuration
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_SetHourFormat (RTC_TypeDef *RTCx, uint32_t HourFormat)
Set Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE uint32_t | LL_RTC_GetHourFormat (RTC_TypeDef *RTCx)
Get Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE void | LL_RTC_SetAlarmOutEvent (RTC_TypeDef *RTCx, uint32_t AlarmOutput)
Select the flag to be routed to RTC_ALARM output.
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutEvent (RTC_TypeDef *RTCx)
Get the flag to be routed to RTC_ALARM output.
__STATIC_INLINE void | LL_RTC_SetAlarmOutputType (RTC_TypeDef *RTCx, uint32_t Output)
Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutputType (RTC_TypeDef *RTCx)
Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE void | LL_RTC_EnablePushPullMode (RTC_TypeDef *RTCx, uint32_t PinMask)
Enable push-pull output on PC13, PC14 and/or PC15.
__STATIC_INLINE void | LL_RTC_DisablePushPullMode (RTC_TypeDef *RTCx, uint32_t PinMask)
Disable push-pull output on PC13, PC14 and/or PC15.
__STATIC_INLINE void | LL_RTC_SetOutputPin (RTC_TypeDef *RTCx, uint32_t PinMask)
Set PC14 and/or PC15 to high level.
__STATIC_INLINE void | LL_RTC_ResetOutputPin (RTC_TypeDef *RTCx, uint32_t PinMask)
Set PC14 and/or PC15 to low level.
__STATIC_INLINE void | LL_RTC_EnableInitMode (RTC_TypeDef *RTCx)
Enable initialization mode.
__STATIC_INLINE void | LL_RTC_DisableInitMode (RTC_TypeDef *RTCx)
Disable initialization mode (Free running mode)
__STATIC_INLINE void | LL_RTC_SetOutputPolarity (RTC_TypeDef *RTCx, uint32_t Polarity)
Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
__STATIC_INLINE uint32_t | LL_RTC_GetOutputPolarity (RTC_TypeDef *RTCx)
Get Output polarity.
__STATIC_INLINE void | LL_RTC_EnableShadowRegBypass (RTC_TypeDef *RTCx)
Enable Bypass the shadow registers.
__STATIC_INLINE void | LL_RTC_DisableShadowRegBypass (RTC_TypeDef *RTCx)
Disable Bypass the shadow registers.
__STATIC_INLINE uint32_t | LL_RTC_IsShadowRegBypassEnabled (RTC_TypeDef *RTCx)
Check if Shadow registers bypass is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableRefClock (RTC_TypeDef *RTCx)
Enable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_DisableRefClock (RTC_TypeDef *RTCx)
Disable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_SetAsynchPrescaler (RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
Set Asynchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_SetSynchPrescaler (RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
Set Synchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetAsynchPrescaler (RTC_TypeDef *RTCx)
Get Asynchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetSynchPrescaler (RTC_TypeDef *RTCx)
Get Synchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_EnableWriteProtection (RTC_TypeDef *RTCx)
Enable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_DisableWriteProtection (RTC_TypeDef *RTCx)
Disable the write protection for RTC registers.

Function Documentation

__STATIC_INLINE void LL_RTC_DisableInitMode ( RTC_TypeDef * RTCx )

Disable initialization mode (Free running mode)

Reference Manual to LL API cross reference:
ISR INIT LL_RTC_DisableInitMode
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 983 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), LL_RTC_ExitInitMode(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_DisablePushPullMode | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | PinMask
 | ) |  |

Disable push-pull output on PC13, PC14 and/or PC15.

Note:
PC13, PC14 and/or PC15 are controlled by the GPIO configuration registers. Consequently PC13, PC14 and/or PC15 are floating in Standby mode.
Reference Manual to LL API cross reference:
TAFCR PC13MODE LL_RTC_DisablePushPullMode
TAFCR PC14MODE LL_RTC_DisablePushPullMode
TAFCR PC15MODE LL_RTC_DisablePushPullMode
Parameters:
RTCx RTC Instance
PinMask This parameter can be a combination of the following values:
  • LL_RTC_PIN_PC13
  • LL_RTC_PIN_PC14
  • LL_RTC_PIN_PC15
Return values:
None

Definition at line 925 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableRefClock ( RTC_TypeDef * RTCx )

Disable RTC_REFIN reference clock detection (50 or 60 Hz)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
CR REFCKON LL_RTC_DisableRefClock
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1072 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableShadowRegBypass ( RTC_TypeDef * RTCx )

Disable Bypass the shadow registers.

Reference Manual to LL API cross reference:
CR BYPSHAD LL_RTC_DisableShadowRegBypass
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1035 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableWriteProtection ( RTC_TypeDef * RTCx )

Disable the write protection for RTC registers.

Reference Manual to LL API cross reference:
WPR KEY LL_RTC_DisableWriteProtection
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1140 of file stm32f3xx_ll_rtc.h.

References RTC_WRITE_PROTECTION_ENABLE_1, and RTC_WRITE_PROTECTION_ENABLE_2.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_EnableInitMode ( RTC_TypeDef * RTCx )

Enable initialization mode.

Note:
Initialization mode is used to program time and date register (RTC_TR and RTC_DR) and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
Reference Manual to LL API cross reference:
ISR INIT LL_RTC_EnableInitMode
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 971 of file stm32f3xx_ll_rtc.h.

References RTC_INIT_MASK.

Referenced by LL_RTC_EnterInitMode().

__STATIC_INLINE void LL_RTC_EnablePushPullMode | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | PinMask
 | ) |  |

Enable push-pull output on PC13, PC14 and/or PC15.

Note:
PC13 forced to push-pull output if all RTC alternate functions are disabled
PC14 and PC15 forced to push-pull output if LSE is disabled
Reference Manual to LL API cross reference:
TAFCR PC13MODE LL_RTC_EnablePushPullMode
Reference Manual to LL API cross reference:
TAFCR PC14MODE LL_RTC_EnablePushPullMode
Reference Manual to LL API cross reference:
TAFCR PC15MODE LL_RTC_EnablePushPullMode
Parameters:
RTCx RTC Instance
PinMask This parameter can be a combination of the following values:
  • LL_RTC_PIN_PC13
  • LL_RTC_PIN_PC14
  • LL_RTC_PIN_PC15
Return values:
None

Definition at line 906 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableRefClock ( RTC_TypeDef * RTCx )

Enable RTC_REFIN reference clock detection (50 or 60 Hz)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
CR REFCKON LL_RTC_EnableRefClock
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1059 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableShadowRegBypass ( RTC_TypeDef * RTCx )

Enable Bypass the shadow registers.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR BYPSHAD LL_RTC_EnableShadowRegBypass
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1024 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableWriteProtection ( RTC_TypeDef * RTCx )

Enable the write protection for RTC registers.

Reference Manual to LL API cross reference:
WPR KEY LL_RTC_EnableWriteProtection
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1129 of file stm32f3xx_ll_rtc.h.

References RTC_WRITE_PROTECTION_DISABLE.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent ( RTC_TypeDef * RTCx )

Get the flag to be routed to RTC_ALARM output.

Reference Manual to LL API cross reference:
CR OSEL LL_RTC_GetAlarmOutEvent
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALARMOUT_DISABLE
  • LL_RTC_ALARMOUT_ALMA
  • LL_RTC_ALARMOUT_ALMB
  • LL_RTC_ALARMOUT_WAKEUP

Definition at line 854 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType ( RTC_TypeDef * RTCx )

Get RTC_ALARM output type (ALARM in push-pull or open-drain output)

Note:
used only when RTC_ALARM is mapped on PC13
If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the PC13 output data
Reference Manual to LL API cross reference:
TAFCR ALARMOUTTYPE LL_RTC_GetAlarmOutputType
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL

Definition at line 887 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler ( RTC_TypeDef * RTCx )

Get Asynchronous prescaler factor.

Reference Manual to LL API cross reference:
PRER PREDIV_A LL_RTC_GetAsynchPrescaler
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data = 0 and Max_Data = 0x7F

Definition at line 1107 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetHourFormat ( RTC_TypeDef * RTCx )

Get Hours format (24 hour/day or AM/PM hour format)

Reference Manual to LL API cross reference:
CR FMT LL_RTC_GetHourFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_HOURFORMAT_24HOUR
  • LL_RTC_HOURFORMAT_AMPM

Definition at line 822 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity ( RTC_TypeDef * RTCx )

Get Output polarity.

Reference Manual to LL API cross reference:
CR POL LL_RTC_GetOutputPolarity
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW

Definition at line 1012 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler ( RTC_TypeDef * RTCx )

Get Synchronous prescaler factor.

Reference Manual to LL API cross reference:
PRER PREDIV_S LL_RTC_GetSynchPrescaler
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data = 0 and Max_Data = 0x7FFF

Definition at line 1118 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled ( RTC_TypeDef * RTCx )

Check if Shadow registers bypass is enabled or not.

Reference Manual to LL API cross reference:
CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1046 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_ResetOutputPin | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | PinMask
 | ) |  |

Set PC14 and/or PC15 to low level.

Note:
Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through LL_RTC_EnablePushPullMode)
Reference Manual to LL API cross reference:
TAFCR PC14VALUE LL_RTC_ResetOutputPin
TAFCR PC15VALUE LL_RTC_ResetOutputPin
Parameters:
RTCx RTC Instance
PinMask This parameter can be a combination of the following values:
  • LL_RTC_PIN_PC14
  • LL_RTC_PIN_PC15
Return values:
None

Definition at line 957 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetAlarmOutEvent | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | AlarmOutput
 | ) |  |

Select the flag to be routed to RTC_ALARM output.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR OSEL LL_RTC_SetAlarmOutEvent
Parameters:
RTCx RTC Instance
AlarmOutput This parameter can be one of the following values:
  • LL_RTC_ALARMOUT_DISABLE
  • LL_RTC_ALARMOUT_ALMA
  • LL_RTC_ALARMOUT_ALMB
  • LL_RTC_ALARMOUT_WAKEUP
Return values:
None

Definition at line 839 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetAlarmOutputType | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Output
 | ) |  |

Set RTC_ALARM output type (ALARM in push-pull or open-drain output)

Note:
Used only when RTC_ALARM is mapped on PC13
If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the PC13 output data
Reference Manual to LL API cross reference:
TAFCR ALARMOUTTYPE LL_RTC_SetAlarmOutputType
Parameters:
RTCx RTC Instance
Output This parameter can be one of the following values:
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
Return values:
None

Definition at line 871 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetAsynchPrescaler | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | AsynchPrescaler
 | ) |  |

Set Asynchronous prescaler factor.

Reference Manual to LL API cross reference:
PRER PREDIV_A LL_RTC_SetAsynchPrescaler
Parameters:
RTCx | RTC Instance
AsynchPrescaler | Value between Min_Data = 0 and Max_Data = 0x7F
Return values:
None

Definition at line 1084 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_Init().

__STATIC_INLINE void LL_RTC_SetHourFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | HourFormat
 | ) |  |

Set Hours format (24 hour/day or AM/PM hour format)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
CR FMT LL_RTC_SetHourFormat
Parameters:
RTCx RTC Instance
HourFormat This parameter can be one of the following values:
  • LL_RTC_HOURFORMAT_24HOUR
  • LL_RTC_HOURFORMAT_AMPM
Return values:
None

Definition at line 809 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_Init().

__STATIC_INLINE void LL_RTC_SetOutputPin | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | PinMask
 | ) |  |

Set PC14 and/or PC15 to high level.

Note:
Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through LL_RTC_EnablePushPullMode)
Reference Manual to LL API cross reference:
TAFCR PC14VALUE LL_RTC_SetOutputPin
TAFCR PC15VALUE LL_RTC_SetOutputPin
Parameters:
RTCx RTC Instance
PinMask This parameter can be a combination of the following values:
  • LL_RTC_PIN_PC14
  • LL_RTC_PIN_PC15
Return values:
None

Definition at line 941 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetOutputPolarity | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Polarity
 | ) |  |

Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR POL LL_RTC_SetOutputPolarity
Parameters:
RTCx RTC Instance
Polarity This parameter can be one of the following values:
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW
Return values:
None

Definition at line 999 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetSynchPrescaler | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | SynchPrescaler
 | ) |  |

Set Synchronous prescaler factor.

Reference Manual to LL API cross reference:
PRER PREDIV_S LL_RTC_SetSynchPrescaler
Parameters:
RTCx | RTC Instance
SynchPrescaler | Value between Min_Data = 0 and Max_Data = 0x7FFF
Return values:
None

Definition at line 1096 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_Init().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Time

Functions
Time
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TIME_SetFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetFormat (RTC_TypeDef *RTCx)
Get time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_TIME_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetHour (RTC_TypeDef *RTCx)
Get Hours in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetMinute (RTC_TypeDef *RTCx)
Get Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSecond (RTC_TypeDef *RTCx)
Get Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_Config (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_Get (RTC_TypeDef *RTCx)
Get time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_EnableDayLightStore (RTC_TypeDef *RTCx)
Memorize whether the daylight saving time change has been performed.
__STATIC_INLINE void | LL_RTC_TIME_DisableDayLightStore (RTC_TypeDef *RTCx)
Disable memorization whether the daylight saving time change has been performed.
__STATIC_INLINE uint32_t | LL_RTC_TIME_IsDayLightStoreEnabled (RTC_TypeDef *RTCx)
Check if RTC Day Light Saving stored operation has been enabled or not.
__STATIC_INLINE void | LL_RTC_TIME_DecHour (RTC_TypeDef *RTCx)
Subtract 1 hour (winter time change)
__STATIC_INLINE void | LL_RTC_TIME_IncHour (RTC_TypeDef *RTCx)
Add 1 hour (summer time change)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSubSecond (RTC_TypeDef *RTCx)
Get Sub second value in the synchronous prescaler counter.
__STATIC_INLINE void | LL_RTC_TIME_Synchronize (RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
Synchronize to a remote clock with a high degree of precision.

Function Documentation

__STATIC_INLINE void LL_RTC_TIME_Config | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set time (hour, minute and second) in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
TimeFormat and Hours should follow the same format
Reference Manual to LL API cross reference:
TR PM LL_RTC_TIME_Config
TR HT LL_RTC_TIME_Config
TR HU LL_RTC_TIME_Config
TR MNT LL_RTC_TIME_Config
TR MNU LL_RTC_TIME_Config
TR ST LL_RTC_TIME_Config
TR SU LL_RTC_TIME_Config
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1322 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_TIME_DecHour ( RTC_TypeDef * RTCx )

Subtract 1 hour (winter time change)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR SUB1H LL_RTC_TIME_DecHour
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1402 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore ( RTC_TypeDef * RTCx )

Disable memorization whether the daylight saving time change has been performed.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR BKP LL_RTC_TIME_DisableDayLightStore
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1379 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore ( RTC_TypeDef * RTCx )

Memorize whether the daylight saving time change has been performed.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR BKP LL_RTC_TIME_EnableDayLightStore
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1367 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_Get ( RTC_TypeDef * RTCx )

Get time (hour, minute and second) in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
TR HT LL_RTC_TIME_Get
TR HU LL_RTC_TIME_Get
TR MNT LL_RTC_TIME_Get
TR MNU LL_RTC_TIME_Get
TR ST LL_RTC_TIME_Get
TR SU LL_RTC_TIME_Get
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds (Format: 0x00HHMMSS).

Definition at line 1350 of file stm32f3xx_ll_rtc.h.

References RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat ( RTC_TypeDef * RTCx )

Get time format (AM or PM notation)

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
Reference Manual to LL API cross reference:
TR PM LL_RTC_TIME_GetFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM

Definition at line 1182 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour ( RTC_TypeDef * RTCx )

Get Hours in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to Binary format
Reference Manual to LL API cross reference:
TR HT LL_RTC_TIME_GetHour
TR HU LL_RTC_TIME_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 1217 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute ( RTC_TypeDef * RTCx )

Get Minutes in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD to Binary format
Reference Manual to LL API cross reference:
TR MNT LL_RTC_TIME_GetMinute
TR MNU LL_RTC_TIME_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1255 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond ( RTC_TypeDef * RTCx )

Get Seconds in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
TR ST LL_RTC_TIME_GetSecond
TR SU LL_RTC_TIME_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1293 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond ( RTC_TypeDef * RTCx )

Get Sub second value in the synchronous prescaler counter.

Note:
You can use both SubSeconds value and SecondFraction (PREDIV_S through LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar SubSeconds value in second fraction ratio with time unit following generic formula: ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS.
Reference Manual to LL API cross reference:
SSR SS LL_RTC_TIME_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Sub second value (number between 0 and 65535)

Definition at line 1432 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_IncHour ( RTC_TypeDef * RTCx )

Add 1 hour (summer time change)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ADD1H LL_RTC_TIME_IncHour
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1414 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled ( RTC_TypeDef * RTCx )

Check if RTC Day Light Saving stored operation has been enabled or not.

Reference Manual to LL API cross reference:
CR BKP LL_RTC_TIME_IsDayLightStoreEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1390 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set time format (AM/24-hour or PM notation)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
TR PM LL_RTC_TIME_SetFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM
Return values:
None

Definition at line 1165 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set Hours in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
Reference Manual to LL API cross reference:
TR HT LL_RTC_TIME_SetHour
TR HU LL_RTC_TIME_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 1198 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set Minutes in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
TR MNT LL_RTC_TIME_SetMinute
TR MNU LL_RTC_TIME_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1236 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set Seconds in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
TR ST LL_RTC_TIME_SetSecond
TR SU LL_RTC_TIME_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1274 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_Synchronize | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | ShiftSecond,
 |  | uint32_t | Fraction
 | ) |  |

Synchronize to a remote clock with a high degree of precision.

Note:
This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
When REFCKON is set, firmware must not write to Shift control register.
Reference Manual to LL API cross reference:
SHIFTR ADD1S LL_RTC_TIME_Synchronize
SHIFTR SUBFS LL_RTC_TIME_Synchronize
Parameters:
RTCx | RTC Instance
ShiftSecond This parameter can be one of the following values:
  • LL_RTC_SHIFT_SECOND_DELAY
  • LL_RTC_SHIFT_SECOND_ADVANCE
Fraction | Number of Seconds Fractions (any value from 0 to 0x7FFF)
Return values:
None

Definition at line 1451 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Date

Functions
Date
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_DATE_SetYear (RTC_TypeDef *RTCx, uint32_t Year)
Set Year in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetYear (RTC_TypeDef *RTCx)
Get Year in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set Week day.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetWeekDay (RTC_TypeDef *RTCx)
Get Week day.
__STATIC_INLINE void | LL_RTC_DATE_SetMonth (RTC_TypeDef *RTCx, uint32_t Month)
Set Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetMonth (RTC_TypeDef *RTCx)
Get Month in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetDay (RTC_TypeDef *RTCx)
Get Day in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_Config (RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
Set date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_Get (RTC_TypeDef *RTCx)
Get date (WeekDay, Day, Month and Year) in BCD format.

Function Documentation

__STATIC_INLINE void LL_RTC_DATE_Config | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay,
 |  | uint32_t | Day,
 |  | uint32_t | Month,
 |  | uint32_t | Year
 | ) |  |

Set date (WeekDay, Day, Month and Year) in BCD format.

Reference Manual to LL API cross reference:
DR WDU LL_RTC_DATE_Config
DR MT LL_RTC_DATE_Config
DR MU LL_RTC_DATE_Config
DR DT LL_RTC_DATE_Config
DR DU LL_RTC_DATE_Config
DR YT LL_RTC_DATE_Config
DR YU LL_RTC_DATE_Config
Parameters:
RTCx | RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Day | Value between Min_Data=0x01 and Max_Data=0x31
Month This parameter can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER
Year | Value between Min_Data=0x00 and Max_Data=0x99
Return values:
None

Definition at line 1661 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init().

__STATIC_INLINE uint32_t LL_RTC_DATE_Get ( RTC_TypeDef * RTCx )

Get date (WeekDay, Day, Month and Year) in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, and __LL_RTC_GET_DAY are available to get independently each parameter.
Reference Manual to LL API cross reference:
DR WDU LL_RTC_DATE_Get
DR MT LL_RTC_DATE_Get
DR MU LL_RTC_DATE_Get
DR DT LL_RTC_DATE_Get
DR DU LL_RTC_DATE_Get
DR YT LL_RTC_DATE_Get
DR YU LL_RTC_DATE_Get
Parameters:
RTCx RTC Instance
Return values:
Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).

Definition at line 1689 of file stm32f3xx_ll_rtc.h.

References RTC_OFFSET_DAY, RTC_OFFSET_MONTH, and RTC_OFFSET_WEEKDAY.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay ( RTC_TypeDef * RTCx )

Get Day in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
DR DT LL_RTC_DATE_GetDay
DR DU LL_RTC_DATE_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 1618 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth ( RTC_TypeDef * RTCx )

Get Month in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
Reference Manual to LL API cross reference:
DR MT LL_RTC_DATE_GetMonth
DR MU LL_RTC_DATE_GetMonth
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 1585 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay ( RTC_TypeDef * RTCx )

Get Week day.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Reference Manual to LL API cross reference:
DR WDU LL_RTC_DATE_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 1531 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear ( RTC_TypeDef * RTCx )

Get Year in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
Reference Manual to LL API cross reference:
DR YT LL_RTC_DATE_GetYear
DR YU LL_RTC_DATE_GetYear
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x99

Definition at line 1489 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
DR DT LL_RTC_DATE_SetDay
DR DU LL_RTC_DATE_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 1602 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetMonth | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Month
 | ) |  |

Set Month in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
Reference Manual to LL API cross reference:
DR MT LL_RTC_DATE_SetMonth
DR MU LL_RTC_DATE_SetMonth
Parameters:
RTCx RTC Instance
Month This parameter can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER
Return values:
None

Definition at line 1557 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set Week day.

Reference Manual to LL API cross reference:
DR WDU LL_RTC_DATE_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 1511 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetYear | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Year
 | ) |  |

Set Year in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
Reference Manual to LL API cross reference:
DR YT LL_RTC_DATE_SetYear
DR YU LL_RTC_DATE_SetYear
Parameters:
RTCx | RTC Instance
Year | Value between Min_Data=0x00 and Max_Data=0x99
Return values:
None

Definition at line 1473 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ALARMA

Functions
ALARMA
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_ALMA_Enable (RTC_TypeDef *RTCx)
Enable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_Disable (RTC_TypeDef *RTCx)
Disable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm A masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMask (RTC_TypeDef *RTCx)
Get the Alarm A masks.
__STATIC_INLINE void | LL_RTC_ALMA_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmA Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMA_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmA Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMA_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM A Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetDay (RTC_TypeDef *RTCx)
Get ALARM A Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM A Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM A Weekday.
__STATIC_INLINE void | LL_RTC_ALMA_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set Alarm A time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTimeFormat (RTC_TypeDef *RTCx)
Get Alarm A time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMA_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM A Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetHour (RTC_TypeDef *RTCx)
Get ALARM A Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM A Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMinute (RTC_TypeDef *RTCx)
Get ALARM A Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM A Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSecond (RTC_TypeDef *RTCx)
Get ALARM A Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm A Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm A Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm A Sub seconds value.

Function Documentation

__STATIC_INLINE void LL_RTC_ALMA_ConfigTime | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set Alarm A Time (hour, minute and second) in BCD format.

Reference Manual to LL API cross reference:
ALRMAR PM LL_RTC_ALMA_ConfigTime
ALRMAR HT LL_RTC_ALMA_ConfigTime
ALRMAR HU LL_RTC_ALMA_ConfigTime
ALRMAR MNT LL_RTC_ALMA_ConfigTime
ALRMAR MNU LL_RTC_ALMA_ConfigTime
ALRMAR ST LL_RTC_ALMA_ConfigTime
ALRMAR SU LL_RTC_ALMA_ConfigTime
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2001 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_Disable ( RTC_TypeDef * RTCx )

Disable Alarm A.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRAE LL_RTC_ALMA_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1727 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday ( RTC_TypeDef * RTCx )

Disable AlarmA Week day selection (DU[3:0] represents the date )

Reference Manual to LL API cross reference:
ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1790 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_Enable ( RTC_TypeDef * RTCx )

Enable Alarm A.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRAE LL_RTC_ALMA_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1715 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday ( RTC_TypeDef * RTCx )

Enable AlarmA Week day selection (DU[3:0] represents the week day.

DT[1:0] is do not care)

Reference Manual to LL API cross reference:
ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1779 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay ( RTC_TypeDef * RTCx )

Get ALARM A Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMAR DT LL_RTC_ALMA_GetDay
ALRMAR DU LL_RTC_ALMA_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 1818 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour ( RTC_TypeDef * RTCx )

Get ALARM A Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMAR HT LL_RTC_ALMA_GetHour
ALRMAR HU LL_RTC_ALMA_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 1913 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask ( RTC_TypeDef * RTCx )

Get the Alarm A masks.

Reference Manual to LL API cross reference:
ALRMAR MSK4 LL_RTC_ALMA_GetMask
ALRMAR MSK3 LL_RTC_ALMA_GetMask
ALRMAR MSK2 LL_RTC_ALMA_GetMask
ALRMAR MSK1 LL_RTC_ALMA_GetMask
Parameters:
RTCx RTC Instance
Return values:
Returned value can be can be a combination of the following values:
  • LL_RTC_ALMA_MASK_NONE
  • LL_RTC_ALMA_MASK_DATEWEEKDAY
  • LL_RTC_ALMA_MASK_HOURS
  • LL_RTC_ALMA_MASK_MINUTES
  • LL_RTC_ALMA_MASK_SECONDS
  • LL_RTC_ALMA_MASK_ALL

Definition at line 1768 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute ( RTC_TypeDef * RTCx )

Get ALARM A Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMAR MNT LL_RTC_ALMA_GetMinute
ALRMAR MNU LL_RTC_ALMA_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1944 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond ( RTC_TypeDef * RTCx )

Get ALARM A Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMAR ST LL_RTC_ALMA_GetSecond
ALRMAR SU LL_RTC_ALMA_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1975 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond ( RTC_TypeDef * RTCx )

Get Alarm A Sub seconds value.

Reference Manual to LL API cross reference:
ALRMASSR SS LL_RTC_ALMA_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x7FFF

Definition at line 2073 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask ( RTC_TypeDef * RTCx )

Get Alarm A Mask the most-significant bits starting at this bit.

Reference Manual to LL API cross reference:
ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xF

Definition at line 2050 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime ( RTC_TypeDef * RTCx )

Get Alarm B Time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
ALRMAR HT LL_RTC_ALMA_GetTime
ALRMAR HU LL_RTC_ALMA_GetTime
ALRMAR MNT LL_RTC_ALMA_GetTime
ALRMAR MNU LL_RTC_ALMA_GetTime
ALRMAR ST LL_RTC_ALMA_GetTime
ALRMAR SU LL_RTC_ALMA_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 2025 of file stm32f3xx_ll_rtc.h.

References LL_RTC_ALMA_GetHour(), LL_RTC_ALMA_GetMinute(), LL_RTC_ALMA_GetSecond(), RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat ( RTC_TypeDef * RTCx )

Get Alarm A time format (AM or PM notation)

Reference Manual to LL API cross reference:
ALRMAR PM LL_RTC_ALMA_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM

Definition at line 1885 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay ( RTC_TypeDef * RTCx )

Get ALARM A Weekday.

Reference Manual to LL API cross reference:
ALRMAR DU LL_RTC_ALMA_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 1858 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set ALARM A Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
ALRMAR DT LL_RTC_ALMA_SetDay
ALRMAR DU LL_RTC_ALMA_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 1804 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set ALARM A Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
Reference Manual to LL API cross reference:
ALRMAR HT LL_RTC_ALMA_SetHour
ALRMAR HU LL_RTC_ALMA_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 1899 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Specify the Alarm A masks.

Reference Manual to LL API cross reference:
ALRMAR MSK4 LL_RTC_ALMA_SetMask
ALRMAR MSK3 LL_RTC_ALMA_SetMask
ALRMAR MSK2 LL_RTC_ALMA_SetMask
ALRMAR MSK1 LL_RTC_ALMA_SetMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_ALMA_MASK_NONE
  • LL_RTC_ALMA_MASK_DATEWEEKDAY
  • LL_RTC_ALMA_MASK_HOURS
  • LL_RTC_ALMA_MASK_MINUTES
  • LL_RTC_ALMA_MASK_SECONDS
  • LL_RTC_ALMA_MASK_ALL
Return values:
None

Definition at line 1748 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set ALARM A Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
ALRMAR MNT LL_RTC_ALMA_SetMinute
ALRMAR MNU LL_RTC_ALMA_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1930 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set ALARM A Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
ALRMAR ST LL_RTC_ALMA_SetSecond
ALRMAR SU LL_RTC_ALMA_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1961 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Subsecond
 | ) |  |

Set Alarm A Sub seconds value.

Reference Manual to LL API cross reference:
ALRMASSR SS LL_RTC_ALMA_SetSubSecond
Parameters:
RTCx | RTC Instance
Subsecond | Value between Min_Data=0x00 and Max_Data=0x7FFF
Return values:
None

Definition at line 2062 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Set Alarm A Mask the most-significant bits starting at this bit.

Note:
This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.
Reference Manual to LL API cross reference:
ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask
Parameters:
RTCx | RTC Instance
Mask | Value between Min_Data=0x00 and Max_Data=0xF
Return values:
None

Definition at line 2039 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set Alarm A time format (AM/24-hour or PM notation)

Reference Manual to LL API cross reference:
ALRMAR PM LL_RTC_ALMA_SetTimeFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM
Return values:
None

Definition at line 1872 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set ALARM A Weekday.

Reference Manual to LL API cross reference:
ALRMAR DU LL_RTC_ALMA_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 1840 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ALARMB

Functions
ALARMB
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_ALMB_Enable (RTC_TypeDef *RTCx)
Enable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_Disable (RTC_TypeDef *RTCx)
Disable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm B masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMask (RTC_TypeDef *RTCx)
Get the Alarm B masks.
__STATIC_INLINE void | LL_RTC_ALMB_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmB Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMB_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmB Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMB_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM B Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetDay (RTC_TypeDef *RTCx)
Get ALARM B Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM B Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM B Weekday.
__STATIC_INLINE void | LL_RTC_ALMB_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set ALARM B time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTimeFormat (RTC_TypeDef *RTCx)
Get ALARM B time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMB_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM B Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetHour (RTC_TypeDef *RTCx)
Get ALARM B Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM B Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMinute (RTC_TypeDef *RTCx)
Get ALARM B Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM B Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSecond (RTC_TypeDef *RTCx)
Get ALARM B Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm B Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm B Sub seconds value.

Function Documentation

__STATIC_INLINE void LL_RTC_ALMB_ConfigTime | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set Alarm B Time (hour, minute and second) in BCD format.

Reference Manual to LL API cross reference:
ALRMBR PM LL_RTC_ALMB_ConfigTime
ALRMBR HT LL_RTC_ALMB_ConfigTime
ALRMBR HU LL_RTC_ALMB_ConfigTime
ALRMBR MNT LL_RTC_ALMB_ConfigTime
ALRMBR MNU LL_RTC_ALMB_ConfigTime
ALRMBR ST LL_RTC_ALMB_ConfigTime
ALRMBR SU LL_RTC_ALMB_ConfigTime
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2379 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_Disable ( RTC_TypeDef * RTCx )

Disable Alarm B.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRBE LL_RTC_ALMB_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2105 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday ( RTC_TypeDef * RTCx )

Disable AlarmB Week day selection (DU[3:0] represents the date )

Reference Manual to LL API cross reference:
ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2168 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_Enable ( RTC_TypeDef * RTCx )

Enable Alarm B.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRBE LL_RTC_ALMB_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2093 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday ( RTC_TypeDef * RTCx )

Enable AlarmB Week day selection (DU[3:0] represents the week day.

DT[1:0] is do not care)

Reference Manual to LL API cross reference:
ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2157 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay ( RTC_TypeDef * RTCx )

Get ALARM B Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMBR DT LL_RTC_ALMB_GetDay
ALRMBR DU LL_RTC_ALMB_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 2196 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour ( RTC_TypeDef * RTCx )

Get ALARM B Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMBR HT LL_RTC_ALMB_GetHour
ALRMBR HU LL_RTC_ALMB_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 2291 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask ( RTC_TypeDef * RTCx )

Get the Alarm B masks.

Reference Manual to LL API cross reference:
ALRMBR MSK4 LL_RTC_ALMB_GetMask
ALRMBR MSK3 LL_RTC_ALMB_GetMask
ALRMBR MSK2 LL_RTC_ALMB_GetMask
ALRMBR MSK1 LL_RTC_ALMB_GetMask
Parameters:
RTCx RTC Instance
Return values:
Returned value can be can be a combination of the following values:
  • LL_RTC_ALMB_MASK_NONE
  • LL_RTC_ALMB_MASK_DATEWEEKDAY
  • LL_RTC_ALMB_MASK_HOURS
  • LL_RTC_ALMB_MASK_MINUTES
  • LL_RTC_ALMB_MASK_SECONDS
  • LL_RTC_ALMB_MASK_ALL

Definition at line 2146 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute ( RTC_TypeDef * RTCx )

Get ALARM B Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMBR MNT LL_RTC_ALMB_GetMinute
ALRMBR MNU LL_RTC_ALMB_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2322 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond ( RTC_TypeDef * RTCx )

Get ALARM B Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMBR ST LL_RTC_ALMB_GetSecond
ALRMBR SU LL_RTC_ALMB_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2353 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond ( RTC_TypeDef * RTCx )

Get Alarm B Sub seconds value.

Reference Manual to LL API cross reference:
ALRMBSSR SS LL_RTC_ALMB_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x7FFF

Definition at line 2451 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask ( RTC_TypeDef * RTCx )

Get Alarm B Mask the most-significant bits starting at this bit.

Reference Manual to LL API cross reference:
ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xF

Definition at line 2428 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime ( RTC_TypeDef * RTCx )

Get Alarm B Time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
ALRMBR HT LL_RTC_ALMB_GetTime
ALRMBR HU LL_RTC_ALMB_GetTime
ALRMBR MNT LL_RTC_ALMB_GetTime
ALRMBR MNU LL_RTC_ALMB_GetTime
ALRMBR ST LL_RTC_ALMB_GetTime
ALRMBR SU LL_RTC_ALMB_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 2403 of file stm32f3xx_ll_rtc.h.

References LL_RTC_ALMB_GetHour(), LL_RTC_ALMB_GetMinute(), LL_RTC_ALMB_GetSecond(), RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat ( RTC_TypeDef * RTCx )

Get ALARM B time format (AM or PM notation)

Reference Manual to LL API cross reference:
ALRMBR PM LL_RTC_ALMB_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM

Definition at line 2263 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay ( RTC_TypeDef * RTCx )

Get ALARM B Weekday.

Reference Manual to LL API cross reference:
ALRMBR DU LL_RTC_ALMB_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 2236 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set ALARM B Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
ALRMBR DT LL_RTC_ALMB_SetDay
ALRMBR DU LL_RTC_ALMB_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 2182 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set ALARM B Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
Reference Manual to LL API cross reference:
ALRMBR HT LL_RTC_ALMB_SetHour
ALRMBR HU LL_RTC_ALMB_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 2277 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Specify the Alarm B masks.

Reference Manual to LL API cross reference:
ALRMBR MSK4 LL_RTC_ALMB_SetMask
ALRMBR MSK3 LL_RTC_ALMB_SetMask
ALRMBR MSK2 LL_RTC_ALMB_SetMask
ALRMBR MSK1 LL_RTC_ALMB_SetMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_ALMB_MASK_NONE
  • LL_RTC_ALMB_MASK_DATEWEEKDAY
  • LL_RTC_ALMB_MASK_HOURS
  • LL_RTC_ALMB_MASK_MINUTES
  • LL_RTC_ALMB_MASK_SECONDS
  • LL_RTC_ALMB_MASK_ALL
Return values:
None

Definition at line 2126 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set ALARM B Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
ALRMBR MNT LL_RTC_ALMB_SetMinute
ALRMBR MNU LL_RTC_ALMB_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2308 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set ALARM B Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
ALRMBR ST LL_RTC_ALMB_SetSecond
ALRMBR SU LL_RTC_ALMB_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2339 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Subsecond
 | ) |  |

Set Alarm B Sub seconds value.

Reference Manual to LL API cross reference:
ALRMBSSR SS LL_RTC_ALMB_SetSubSecond
Parameters:
RTCx | RTC Instance
Subsecond | Value between Min_Data=0x00 and Max_Data=0x7FFF
Return values:
None

Definition at line 2440 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Set Alarm B Mask the most-significant bits starting at this bit.

Note:
This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.
Reference Manual to LL API cross reference:
ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask
Parameters:
RTCx | RTC Instance
Mask | Value between Min_Data=0x00 and Max_Data=0xF
Return values:
None

Definition at line 2417 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set ALARM B time format (AM/24-hour or PM notation)

Reference Manual to LL API cross reference:
ALRMBR PM LL_RTC_ALMB_SetTimeFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM
Return values:
None

Definition at line 2250 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set ALARM B Weekday.

Reference Manual to LL API cross reference:
ALRMBR DU LL_RTC_ALMB_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 2218 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Timestamp

Functions
Timestamp
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TS_Enable (RTC_TypeDef *RTCx)
Enable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_Disable (RTC_TypeDef *RTCx)
Disable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_SetActiveEdge (RTC_TypeDef *RTCx, uint32_t Edge)
Set Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetActiveEdge (RTC_TypeDef *RTCx)
Get Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTimeFormat (RTC_TypeDef *RTCx)
Get Timestamp AM/PM notation (AM or 24-hour format)
__STATIC_INLINE uint32_t | LL_RTC_TS_GetHour (RTC_TypeDef *RTCx)
Get Timestamp Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMinute (RTC_TypeDef *RTCx)
Get Timestamp Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSecond (RTC_TypeDef *RTCx)
Get Timestamp Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTime (RTC_TypeDef *RTCx)
Get Timestamp time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetWeekDay (RTC_TypeDef *RTCx)
Get Timestamp Week day.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMonth (RTC_TypeDef *RTCx)
Get Timestamp Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDay (RTC_TypeDef *RTCx)
Get Timestamp Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDate (RTC_TypeDef *RTCx)
Get Timestamp date (WeekDay, Day and Month) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSubSecond (RTC_TypeDef *RTCx)
Get time-stamp sub second value.
__STATIC_INLINE void | LL_RTC_TS_EnableOnTamper (RTC_TypeDef *RTCx)
Activate timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TS_DisableOnTamper (RTC_TypeDef *RTCx)
Disable timestamp on tamper detection event.

Function Documentation

__STATIC_INLINE void LL_RTC_TS_Disable ( RTC_TypeDef * RTCx )

Disable Timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR TSE LL_RTC_TS_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2483 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_DisableOnTamper ( RTC_TypeDef * RTCx )

Disable timestamp on tamper detection event.

Reference Manual to LL API cross reference:
TAFCR TAMPTS LL_RTC_TS_DisableOnTamper
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2691 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_Enable ( RTC_TypeDef * RTCx )

Enable Timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR TSE LL_RTC_TS_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2471 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_EnableOnTamper ( RTC_TypeDef * RTCx )

Activate timestamp on tamper detection event.

Reference Manual to LL API cross reference:
TAFCR TAMPTS LL_RTC_TS_EnableOnTamper
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2680 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge ( RTC_TypeDef * RTCx )

Get Time-stamp event active edge.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR TSEDGE LL_RTC_TS_GetActiveEdge
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TIMESTAMP_EDGE_RISING
  • LL_RTC_TIMESTAMP_EDGE_FALLING

Definition at line 2513 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetDate ( RTC_TypeDef * RTCx )

Get Timestamp date (WeekDay, Day and Month) in BCD format.

Note:
helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH, and __LL_RTC_GET_DAY are available to get independently each parameter.
Reference Manual to LL API cross reference:
TSDR WDU LL_RTC_TS_GetDate
TSDR MT LL_RTC_TS_GetDate
TSDR MU LL_RTC_TS_GetDate
TSDR DT LL_RTC_TS_GetDate
TSDR DU LL_RTC_TS_GetDate
Parameters:
RTCx RTC Instance
Return values:
Combination of Weekday, Day and Month

Definition at line 2657 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetDay ( RTC_TypeDef * RTCx )

Get Timestamp Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
TSDR DT LL_RTC_TS_GetDay
TSDR DU LL_RTC_TS_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 2640 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetHour ( RTC_TypeDef * RTCx )

Get Timestamp Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
TSTR HT LL_RTC_TS_GetHour
TSTR HU LL_RTC_TS_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 2539 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute ( RTC_TypeDef * RTCx )

Get Timestamp Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
TSTR MNT LL_RTC_TS_GetMinute
TSTR MNU LL_RTC_TS_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2552 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth ( RTC_TypeDef * RTCx )

Get Timestamp Month in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
Reference Manual to LL API cross reference:
TSDR MT LL_RTC_TS_GetMonth
TSDR MU LL_RTC_TS_GetMonth
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 2627 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond ( RTC_TypeDef * RTCx )

Get Timestamp Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
TSTR ST LL_RTC_TS_GetSecond
TSTR SU LL_RTC_TS_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2565 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond ( RTC_TypeDef * RTCx )

Get time-stamp sub second value.

Reference Manual to LL API cross reference:
TSSSR SS LL_RTC_TS_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 2668 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetTime ( RTC_TypeDef * RTCx )

Get Timestamp time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
TSTR HT LL_RTC_TS_GetTime
TSTR HU LL_RTC_TS_GetTime
TSTR MNT LL_RTC_TS_GetTime
TSTR MNU LL_RTC_TS_GetTime
TSTR ST LL_RTC_TS_GetTime
TSTR SU LL_RTC_TS_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 2583 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat ( RTC_TypeDef * RTCx )

Get Timestamp AM/PM notation (AM or 24-hour format)

Reference Manual to LL API cross reference:
TSTR PM LL_RTC_TS_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TS_TIME_FORMAT_AM
  • LL_RTC_TS_TIME_FORMAT_PM

Definition at line 2526 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay ( RTC_TypeDef * RTCx )

Get Timestamp Week day.

Reference Manual to LL API cross reference:
TSDR WDU LL_RTC_TS_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 2602 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_SetActiveEdge | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Edge
 | ) |  |

Set Time-stamp event active edge.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
Reference Manual to LL API cross reference:
CR TSEDGE LL_RTC_TS_SetActiveEdge
Parameters:
RTCx RTC Instance
Edge This parameter can be one of the following values:
  • LL_RTC_TIMESTAMP_EDGE_RISING
  • LL_RTC_TIMESTAMP_EDGE_FALLING
Return values:
None

Definition at line 2499 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Tamper

Functions
Tamper
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TAMPER_Enable (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable RTC_TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_Disable (RTC_TypeDef *RTCx, uint32_t Tamper)
Clear RTC_TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisablePullUp (RTC_TypeDef *RTCx)
Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
__STATIC_INLINE void | LL_RTC_TAMPER_EnablePullUp (RTC_TypeDef *RTCx)
Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
__STATIC_INLINE void | LL_RTC_TAMPER_SetPrecharge (RTC_TypeDef *RTCx, uint32_t Duration)
Set RTC_TAMPx precharge duration.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetPrecharge (RTC_TypeDef *RTCx)
Get RTC_TAMPx precharge duration.
__STATIC_INLINE void | LL_RTC_TAMPER_SetFilterCount (RTC_TypeDef *RTCx, uint32_t FilterCount)
Set RTC_TAMPx filter count.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetFilterCount (RTC_TypeDef *RTCx)
Get RTC_TAMPx filter count.
__STATIC_INLINE void | LL_RTC_TAMPER_SetSamplingFreq (RTC_TypeDef *RTCx, uint32_t SamplingFreq)
Set Tamper sampling frequency.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetSamplingFreq (RTC_TypeDef *RTCx)
Get Tamper sampling frequency.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableActiveLevel (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableActiveLevel (RTC_TypeDef *RTCx, uint32_t Tamper)
Disable Active level for Tamper input.

Function Documentation

__STATIC_INLINE void LL_RTC_TAMPER_Disable | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Clear RTC_TAMPx input detection.

Reference Manual to LL API cross reference:
TAFCR TAMP1E LL_RTC_TAMPER_Disable
TAFCR TAMP2E LL_RTC_TAMPER_Disable
TAFCR TAMP3E LL_RTC_TAMPER_Disable
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_1
  • LL_RTC_TAMPER_2
  • LL_RTC_TAMPER_3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2738 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Disable Active level for Tamper input.

Reference Manual to LL API cross reference:
TAFCR TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel
TAFCR TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel
TAFCR TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2907 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp ( RTC_TypeDef * RTCx )

Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)

Reference Manual to LL API cross reference:
TAFCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2750 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_Enable | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Enable RTC_TAMPx input detection.

Reference Manual to LL API cross reference:
TAFCR TAMP1E LL_RTC_TAMPER_Enable
TAFCR TAMP2E LL_RTC_TAMPER_Enable
TAFCR TAMP3E LL_RTC_TAMPER_Enable
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_1
  • LL_RTC_TAMPER_2
  • LL_RTC_TAMPER_3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2719 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Enable Active level for Tamper input.

Reference Manual to LL API cross reference:
TAFCR TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel
TAFCR TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel
TAFCR TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2888 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp ( RTC_TypeDef * RTCx )

Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)

Reference Manual to LL API cross reference:
TAFCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2761 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount ( RTC_TypeDef * RTCx )

Get RTC_TAMPx filter count.

Reference Manual to LL API cross reference:
TAFCR TAMPFLT LL_RTC_TAMPER_GetFilterCount
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_FILTER_DISABLE
  • LL_RTC_TAMPER_FILTER_2SAMPLE
  • LL_RTC_TAMPER_FILTER_4SAMPLE
  • LL_RTC_TAMPER_FILTER_8SAMPLE

Definition at line 2827 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge ( RTC_TypeDef * RTCx )

Get RTC_TAMPx precharge duration.

Reference Manual to LL API cross reference:
TAFCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_DURATION_1RTCCLK
  • LL_RTC_TAMPER_DURATION_2RTCCLK
  • LL_RTC_TAMPER_DURATION_4RTCCLK
  • LL_RTC_TAMPER_DURATION_8RTCCLK

Definition at line 2794 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq ( RTC_TypeDef * RTCx )

Get Tamper sampling frequency.

Reference Manual to LL API cross reference:
TAFCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024
  • LL_RTC_TAMPER_SAMPLFREQDIV_512
  • LL_RTC_TAMPER_SAMPLFREQDIV_256

Definition at line 2868 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | FilterCount
 | ) |  |

Set RTC_TAMPx filter count.

Reference Manual to LL API cross reference:
TAFCR TAMPFLT LL_RTC_TAMPER_SetFilterCount
Parameters:
RTCx RTC Instance
FilterCount This parameter can be one of the following values:
  • LL_RTC_TAMPER_FILTER_DISABLE
  • LL_RTC_TAMPER_FILTER_2SAMPLE
  • LL_RTC_TAMPER_FILTER_4SAMPLE
  • LL_RTC_TAMPER_FILTER_8SAMPLE
Return values:
None

Definition at line 2812 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Duration
 | ) |  |

Set RTC_TAMPx precharge duration.

Reference Manual to LL API cross reference:
TAFCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge
Parameters:
RTCx RTC Instance
Duration This parameter can be one of the following values:
  • LL_RTC_TAMPER_DURATION_1RTCCLK
  • LL_RTC_TAMPER_DURATION_2RTCCLK
  • LL_RTC_TAMPER_DURATION_4RTCCLK
  • LL_RTC_TAMPER_DURATION_8RTCCLK
Return values:
None

Definition at line 2779 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | SamplingFreq
 | ) |  |

Set Tamper sampling frequency.

Reference Manual to LL API cross reference:
TAFCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq
Parameters:
RTCx RTC Instance
SamplingFreq This parameter can be one of the following values:
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024
  • LL_RTC_TAMPER_SAMPLFREQDIV_512
  • LL_RTC_TAMPER_SAMPLFREQDIV_256
Return values:
None

Definition at line 2849 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Wakeup

Functions
Wakeup
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_WAKEUP_Enable (RTC_TypeDef *RTCx)
Enable Wakeup timer.
__STATIC_INLINE void | LL_RTC_WAKEUP_Disable (RTC_TypeDef *RTCx)
Disable Wakeup timer.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_IsEnabled (RTC_TypeDef *RTCx)
Check if Wakeup timer is enabled or not.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetClock (RTC_TypeDef *RTCx, uint32_t WakeupClock)
Select Wakeup clock.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetClock (RTC_TypeDef *RTCx)
Get Wakeup clock.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetAutoReload (RTC_TypeDef *RTCx, uint32_t Value)
Set Wakeup auto-reload value.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetAutoReload (RTC_TypeDef *RTCx)
Get Wakeup auto-reload value.

Function Documentation

__STATIC_INLINE void LL_RTC_WAKEUP_Disable ( RTC_TypeDef * RTCx )

Disable Wakeup timer.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR WUTE LL_RTC_WAKEUP_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2940 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_Enable ( RTC_TypeDef * RTCx )

Enable Wakeup timer.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR WUTE LL_RTC_WAKEUP_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2928 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload ( RTC_TypeDef * RTCx )

Get Wakeup auto-reload value.

Reference Manual to LL API cross reference:
WUTR WUT LL_RTC_WAKEUP_GetAutoReload
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 3012 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock ( RTC_TypeDef * RTCx )

Get Wakeup clock.

Reference Manual to LL API cross reference:
CR WUCKSEL LL_RTC_WAKEUP_GetClock
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WAKEUPCLOCK_DIV_16
  • LL_RTC_WAKEUPCLOCK_DIV_8
  • LL_RTC_WAKEUPCLOCK_DIV_4
  • LL_RTC_WAKEUPCLOCK_DIV_2
  • LL_RTC_WAKEUPCLOCK_CKSPRE
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT

Definition at line 2988 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled ( RTC_TypeDef * RTCx )

Check if Wakeup timer is enabled or not.

Reference Manual to LL API cross reference:
CR WUTE LL_RTC_WAKEUP_IsEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 2951 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Value
 | ) |  |

Set Wakeup auto-reload value.

Note:
Bit can be written only when WUTWF is set to 1 in RTC_ISR
Reference Manual to LL API cross reference:
WUTR WUT LL_RTC_WAKEUP_SetAutoReload
Parameters:
RTCx | RTC Instance
Value | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 3001 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_SetClock | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WakeupClock
 | ) |  |

Select Wakeup clock.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
Reference Manual to LL API cross reference:
CR WUCKSEL LL_RTC_WAKEUP_SetClock
Parameters:
RTCx RTC Instance
WakeupClock This parameter can be one of the following values:
  • LL_RTC_WAKEUPCLOCK_DIV_16
  • LL_RTC_WAKEUPCLOCK_DIV_8
  • LL_RTC_WAKEUPCLOCK_DIV_4
  • LL_RTC_WAKEUPCLOCK_DIV_2
  • LL_RTC_WAKEUPCLOCK_CKSPRE
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
Return values:
None

Definition at line 2971 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Backup_Registers

Functions
Backup_Registers
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_BAK_SetRegister (RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified RTC Backup data register.
__STATIC_INLINE uint32_t | LL_RTC_BAK_GetRegister (RTC_TypeDef *RTCx, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.

Function Documentation

__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | BackupRegister
 | ) |  |

Reads data from the specified RTC Backup data Register.

Reference Manual to LL API cross reference:
BKPxR BKP LL_RTC_BAK_GetRegister
Parameters:
RTCx RTC Instance
BackupRegister This parameter can be one of the following values:
  • LL_RTC_BKP_DR0
  • LL_RTC_BKP_DR1
  • LL_RTC_BKP_DR2
  • LL_RTC_BKP_DR3
  • LL_RTC_BKP_DR4
  • LL_RTC_BKP_DR5 (*)
  • LL_RTC_BKP_DR6 (*)
  • LL_RTC_BKP_DR7 (*)
  • LL_RTC_BKP_DR8 (*)
  • LL_RTC_BKP_DR9 (*)
  • LL_RTC_BKP_DR10 (*)
  • LL_RTC_BKP_DR11 (*)
  • LL_RTC_BKP_DR12 (*)
  • LL_RTC_BKP_DR13 (*)
  • LL_RTC_BKP_DR14 (*)
  • LL_RTC_BKP_DR15 (*)
  • LL_RTC_BKP_DR16 (*)
  • LL_RTC_BKP_DR17 (*)
  • LL_RTC_BKP_DR18 (*)
  • LL_RTC_BKP_DR19 (*)
  • LL_RTC_BKP_DR20 (*)
  • LL_RTC_BKP_DR21 (*)
  • LL_RTC_BKP_DR22 (*)
  • LL_RTC_BKP_DR23 (*)
  • LL_RTC_BKP_DR24 (*)
  • LL_RTC_BKP_DR25 (*)
  • LL_RTC_BKP_DR26 (*)
  • LL_RTC_BKP_DR27 (*)
  • LL_RTC_BKP_DR28 (*)
  • LL_RTC_BKP_DR29 (*)
  • LL_RTC_BKP_DR30 (*)
  • LL_RTC_BKP_DR31 (*)
(*) value not defined in all devices.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF

Definition at line 3121 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_BAK_SetRegister | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | BackupRegister,
 |  | uint32_t | Data
 | ) |  |

Writes a data in a specified RTC Backup data register.

Reference Manual to LL API cross reference:
BKPxR BKP LL_RTC_BAK_SetRegister
Parameters:
RTCx | RTC Instance
BackupRegister This parameter can be one of the following values:
  • LL_RTC_BKP_DR0
  • LL_RTC_BKP_DR1
  • LL_RTC_BKP_DR2
  • LL_RTC_BKP_DR3
  • LL_RTC_BKP_DR4
  • LL_RTC_BKP_DR5 (*)
  • LL_RTC_BKP_DR6 (*)
  • LL_RTC_BKP_DR7 (*)
  • LL_RTC_BKP_DR8 (*)
  • LL_RTC_BKP_DR9 (*)
  • LL_RTC_BKP_DR10 (*)
  • LL_RTC_BKP_DR11 (*)
  • LL_RTC_BKP_DR12 (*)
  • LL_RTC_BKP_DR13 (*)
  • LL_RTC_BKP_DR14 (*)
  • LL_RTC_BKP_DR15 (*)
  • LL_RTC_BKP_DR16 (*)
  • LL_RTC_BKP_DR17 (*)
  • LL_RTC_BKP_DR18 (*)
  • LL_RTC_BKP_DR19 (*)
  • LL_RTC_BKP_DR20 (*)
  • LL_RTC_BKP_DR21 (*)
  • LL_RTC_BKP_DR22 (*)
  • LL_RTC_BKP_DR23 (*)
  • LL_RTC_BKP_DR24 (*)
  • LL_RTC_BKP_DR25 (*)
  • LL_RTC_BKP_DR26 (*)
  • LL_RTC_BKP_DR27 (*)
  • LL_RTC_BKP_DR28 (*)
  • LL_RTC_BKP_DR29 (*)
  • LL_RTC_BKP_DR30 (*)
  • LL_RTC_BKP_DR31 (*)
(*) value not defined in all devices.
Data | Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 3069 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Calibration

Functions
Calibration
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_CAL_SetOutputFreq (RTC_TypeDef *RTCx, uint32_t Frequency)
Set Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetOutputFreq (RTC_TypeDef *RTCx)
Get Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE void | LL_RTC_CAL_SetPulse (RTC_TypeDef *RTCx, uint32_t Pulse)
Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE uint32_t | LL_RTC_CAL_IsPulseInserted (RTC_TypeDef *RTCx)
Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE void | LL_RTC_CAL_SetPeriod (RTC_TypeDef *RTCx, uint32_t Period)
Set the calibration cycle period.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetPeriod (RTC_TypeDef *RTCx)
Get the calibration cycle period.
__STATIC_INLINE void | LL_RTC_CAL_SetMinus (RTC_TypeDef *RTCx, uint32_t CalibMinus)
Set Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetMinus (RTC_TypeDef *RTCx)
Get Calibration minus.

Function Documentation

__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus ( RTC_TypeDef * RTCx )

Get Calibration minus.

Reference Manual to LL API cross reference:
CALR CALM LL_RTC_CAL_GetMinus
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data= 0x1FF

Definition at line 3253 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq ( RTC_TypeDef * RTCx )

Get Calibration output frequency (1 Hz or 512 Hz)

Reference Manual to LL API cross reference:
CR COE LL_RTC_CAL_GetOutputFreq
CR COSEL LL_RTC_CAL_GetOutputFreq
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_CALIB_OUTPUT_NONE
  • LL_RTC_CALIB_OUTPUT_1HZ
  • LL_RTC_CALIB_OUTPUT_512HZ

Definition at line 3168 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod ( RTC_TypeDef * RTCx )

Get the calibration cycle period.

Reference Manual to LL API cross reference:
CALR CALW8 LL_RTC_CAL_GetPeriod
CALR CALW16 LL_RTC_CAL_GetPeriod
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_CALIB_PERIOD_32SEC
  • LL_RTC_CALIB_PERIOD_16SEC
  • LL_RTC_CALIB_PERIOD_8SEC

Definition at line 3228 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted ( RTC_TypeDef * RTCx )

Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)

Reference Manual to LL API cross reference:
CALR CALP LL_RTC_CAL_IsPulseInserted
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3195 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetMinus | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | CalibMinus
 | ) |  |

Set Calibration minus.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0 in RTC_ISR
Reference Manual to LL API cross reference:
CALR CALM LL_RTC_CAL_SetMinus
Parameters:
RTCx | RTC Instance
CalibMinus | Value between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 3242 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Frequency
 | ) |  |

Set Calibration output frequency (1 Hz or 512 Hz)

Note:
Bits are write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR COE LL_RTC_CAL_SetOutputFreq
CR COSEL LL_RTC_CAL_SetOutputFreq
Parameters:
RTCx RTC Instance
Frequency This parameter can be one of the following values:
  • LL_RTC_CALIB_OUTPUT_NONE
  • LL_RTC_CALIB_OUTPUT_1HZ
  • LL_RTC_CALIB_OUTPUT_512HZ
Return values:
None

Definition at line 3153 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetPeriod | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Period
 | ) |  |

Set the calibration cycle period.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0 in RTC_ISR
Reference Manual to LL API cross reference:
CALR CALW8 LL_RTC_CAL_SetPeriod
CALR CALW16 LL_RTC_CAL_SetPeriod
Parameters:
RTCx RTC Instance
Period This parameter can be one of the following values:
  • LL_RTC_CALIB_PERIOD_32SEC
  • LL_RTC_CALIB_PERIOD_16SEC
  • LL_RTC_CALIB_PERIOD_8SEC
Return values:
None

Definition at line 3213 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetPulse | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Pulse
 | ) |  |

Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0 in RTC_ISR
Reference Manual to LL API cross reference:
CALR CALP LL_RTC_CAL_SetPulse
Parameters:
RTCx RTC Instance
Pulse This parameter can be one of the following values:
  • LL_RTC_CALIB_INSERTPULSE_NONE
  • LL_RTC_CALIB_INSERTPULSE_SET
Return values:
None

Definition at line 3184 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLAG_Management

Functions
FLAG_Management
RTC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RECALP (RTC_TypeDef *RTCx)
Get Recalibration pending Flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3 (RTC_TypeDef *RTCx)
Get RTC_TAMP3 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2 (RTC_TypeDef *RTCx)
Get RTC_TAMP2 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1 (RTC_TypeDef *RTCx)
Get RTC_TAMP1 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOV (RTC_TypeDef *RTCx)
Get Time-stamp overflow flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TS (RTC_TypeDef *RTCx)
Get Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUT (RTC_TypeDef *RTCx)
Get Wakeup timer flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRB (RTC_TypeDef *RTCx)
Get Alarm B flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRA (RTC_TypeDef *RTCx)
Get Alarm A flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP3 (RTC_TypeDef *RTCx)
Clear RTC_TAMP3 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP2 (RTC_TypeDef *RTCx)
Clear RTC_TAMP2 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP1 (RTC_TypeDef *RTCx)
Clear RTC_TAMP1 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TSOV (RTC_TypeDef *RTCx)
Clear Time-stamp overflow flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TS (RTC_TypeDef *RTCx)
Clear Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_WUT (RTC_TypeDef *RTCx)
Clear Wakeup timer flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRB (RTC_TypeDef *RTCx)
Clear Alarm B flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRA (RTC_TypeDef *RTCx)
Clear Alarm A flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INIT (RTC_TypeDef *RTCx)
Get Initialization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RS (RTC_TypeDef *RTCx)
Get Registers synchronization flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_RS (RTC_TypeDef *RTCx)
Clear Registers synchronization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INITS (RTC_TypeDef *RTCx)
Get Initialization status flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_SHP (RTC_TypeDef *RTCx)
Get Shift operation pending flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTW (RTC_TypeDef *RTCx)
Get Wakeup timer write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBW (RTC_TypeDef *RTCx)
Get Alarm B write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAW (RTC_TypeDef *RTCx)
Get Alarm A write flag.

Function Documentation

__STATIC_INLINE void LL_RTC_ClearFlag_ALRA ( RTC_TypeDef * RTCx )

Clear Alarm A flag.

Reference Manual to LL API cross reference:
ISR ALRAF LL_RTC_ClearFlag_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3464 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_ALRB ( RTC_TypeDef * RTCx )

Clear Alarm B flag.

Reference Manual to LL API cross reference:
ISR ALRBF LL_RTC_ClearFlag_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3453 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_RS ( RTC_TypeDef * RTCx )

Clear Registers synchronization flag.

Reference Manual to LL API cross reference:
ISR RSF LL_RTC_ClearFlag_RS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3497 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_WaitForSynchro().

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1 ( RTC_TypeDef * RTCx )

Clear RTC_TAMP1 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP1F LL_RTC_ClearFlag_TAMP1
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3406 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2 ( RTC_TypeDef * RTCx )

Clear RTC_TAMP2 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP2F LL_RTC_ClearFlag_TAMP2
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3393 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3 ( RTC_TypeDef * RTCx )

Clear RTC_TAMP3 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP3F LL_RTC_ClearFlag_TAMP3
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3380 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TS ( RTC_TypeDef * RTCx )

Clear Time-stamp flag.

Reference Manual to LL API cross reference:
ISR TSF LL_RTC_ClearFlag_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3429 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TSOV ( RTC_TypeDef * RTCx )

Clear Time-stamp overflow flag.

Reference Manual to LL API cross reference:
ISR TSOVF LL_RTC_ClearFlag_TSOV
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3418 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_WUT ( RTC_TypeDef * RTCx )

Clear Wakeup timer flag.

Reference Manual to LL API cross reference:
ISR WUTF LL_RTC_ClearFlag_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3441 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA ( RTC_TypeDef * RTCx )

Get Alarm A flag.

Reference Manual to LL API cross reference:
ISR ALRAF LL_RTC_IsActiveFlag_ALRA
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3368 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW ( RTC_TypeDef * RTCx )

Get Alarm A write flag.

Reference Manual to LL API cross reference:
ISR ALRAWF LL_RTC_IsActiveFlag_ALRAW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3554 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB ( RTC_TypeDef * RTCx )

Get Alarm B flag.

Reference Manual to LL API cross reference:
ISR ALRBF LL_RTC_IsActiveFlag_ALRB
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3357 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW ( RTC_TypeDef * RTCx )

Get Alarm B write flag.

Reference Manual to LL API cross reference:
ISR ALRBWF LL_RTC_IsActiveFlag_ALRBW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3543 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT ( RTC_TypeDef * RTCx )

Get Initialization flag.

Reference Manual to LL API cross reference:
ISR INITF LL_RTC_IsActiveFlag_INIT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3475 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_EnterInitMode().

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS ( RTC_TypeDef * RTCx )

Get Initialization status flag.

Reference Manual to LL API cross reference:
ISR INITS LL_RTC_IsActiveFlag_INITS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3508 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP ( RTC_TypeDef * RTCx )

Get Recalibration pending Flag.

Reference Manual to LL API cross reference:
ISR RECALPF LL_RTC_IsActiveFlag_RECALP
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3272 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS ( RTC_TypeDef * RTCx )

Get Registers synchronization flag.

Reference Manual to LL API cross reference:
ISR RSF LL_RTC_IsActiveFlag_RS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3486 of file stm32f3xx_ll_rtc.h.

Referenced by LL_RTC_WaitForSynchro().

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP ( RTC_TypeDef * RTCx )

Get Shift operation pending flag.

Reference Manual to LL API cross reference:
ISR SHPF LL_RTC_IsActiveFlag_SHP
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3519 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1 ( RTC_TypeDef * RTCx )

Get RTC_TAMP1 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP1F LL_RTC_IsActiveFlag_TAMP1
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3310 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2 ( RTC_TypeDef * RTCx )

Get RTC_TAMP2 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP2F LL_RTC_IsActiveFlag_TAMP2
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3297 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3 ( RTC_TypeDef * RTCx )

Get RTC_TAMP3 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP3F LL_RTC_IsActiveFlag_TAMP3
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3284 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS ( RTC_TypeDef * RTCx )

Get Time-stamp flag.

Reference Manual to LL API cross reference:
ISR TSF LL_RTC_IsActiveFlag_TS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3333 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV ( RTC_TypeDef * RTCx )

Get Time-stamp overflow flag.

Reference Manual to LL API cross reference:
ISR TSOVF LL_RTC_IsActiveFlag_TSOV
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3322 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT ( RTC_TypeDef * RTCx )

Get Wakeup timer flag.

Reference Manual to LL API cross reference:
ISR WUTF LL_RTC_IsActiveFlag_WUT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3345 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW ( RTC_TypeDef * RTCx )

Get Wakeup timer write flag.

Reference Manual to LL API cross reference:
ISR WUTWF LL_RTC_IsActiveFlag_WUTW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3531 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IT_Management

Functions
IT_Management
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_EnableIT_TS (RTC_TypeDef *RTCx)
Enable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TS (RTC_TypeDef *RTCx)
Disable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_WUT (RTC_TypeDef *RTCx)
Enable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_WUT (RTC_TypeDef *RTCx)
Disable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRB (RTC_TypeDef *RTCx)
Enable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRB (RTC_TypeDef *RTCx)
Disable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRA (RTC_TypeDef *RTCx)
Enable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRA (RTC_TypeDef *RTCx)
Disable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP (RTC_TypeDef *RTCx)
Enable all Tamper Interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP (RTC_TypeDef *RTCx)
Disable all Tamper Interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TS (RTC_TypeDef *RTCx)
Check if Time-stamp interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_WUT (RTC_TypeDef *RTCx)
Check if Wakeup timer interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRB (RTC_TypeDef *RTCx)
Check if Alarm B interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRA (RTC_TypeDef *RTCx)
Check if Alarm A interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP (RTC_TypeDef *RTCx)
Check if all the TAMPER interrupts are enabled or not.

Function Documentation

__STATIC_INLINE void LL_RTC_DisableIT_ALRA ( RTC_TypeDef * RTCx )

Disable Alarm A interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRAIE LL_RTC_DisableIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3660 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_ALRB ( RTC_TypeDef * RTCx )

Disable Alarm B interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRBIE LL_RTC_DisableIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3636 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP ( RTC_TypeDef * RTCx )

Disable all Tamper Interrupt.

Reference Manual to LL API cross reference:
TAFCR TAMPIE LL_RTC_DisableIT_TAMP
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3682 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TS ( RTC_TypeDef * RTCx )

Disable Time-stamp interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR TSIE LL_RTC_DisableIT_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3586 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_WUT ( RTC_TypeDef * RTCx )

Disable Wakeup timer interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR WUTIE LL_RTC_DisableIT_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3611 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_ALRA ( RTC_TypeDef * RTCx )

Enable Alarm A interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRAIE LL_RTC_EnableIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3648 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_ALRB ( RTC_TypeDef * RTCx )

Enable Alarm B interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRBIE LL_RTC_EnableIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3624 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP ( RTC_TypeDef * RTCx )

Enable all Tamper Interrupt.

Reference Manual to LL API cross reference:
TAFCR TAMPIE LL_RTC_EnableIT_TAMP
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3671 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TS ( RTC_TypeDef * RTCx )

Enable Time-stamp interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR TSIE LL_RTC_EnableIT_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3574 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_WUT ( RTC_TypeDef * RTCx )

Enable Wakeup timer interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR WUTIE LL_RTC_EnableIT_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3599 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA ( RTC_TypeDef * RTCx )

Check if Alarm A interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR ALRAIE LL_RTC_IsEnabledIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3728 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB ( RTC_TypeDef * RTCx )

Check if Alarm B interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR ALRBIE LL_RTC_IsEnabledIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3717 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP ( RTC_TypeDef * RTCx )

Check if all the TAMPER interrupts are enabled or not.

Reference Manual to LL API cross reference:
TAFCR TAMPIE LL_RTC_IsEnabledIT_TAMP
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3739 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS ( RTC_TypeDef * RTCx )

Check if Time-stamp interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR TSIE LL_RTC_IsEnabledIT_TS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3693 of file stm32f3xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT ( RTC_TypeDef * RTCx )

Check if Wakeup timer interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR WUTIE LL_RTC_IsEnabledIT_WUT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3705 of file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RTC Exported Functions

Functions

ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Function Documentation

ErrorStatus LL_RTC_ALMA_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_AlarmTypeDef * | RTC_AlarmStruct
 | ) |  |

Set the RTC Alarm A.

Note:
The Alarm register can only be written when the corresponding Alarm is disabled (Use LL_RTC_ALMA_Disable function).
Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_AlarmStruct | pointer to a LL_RTC_AlarmTypeDef structure that contains the alarm configuration parameters.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ALARMA registers are configured
  • ERROR: ALARMA registers are not configured

Definition at line 478 of file stm32f3xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL, IS_LL_RTC_ALMA_MASK, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, IS_LL_RTC_WEEKDAY, LL_RTC_ALMA_ConfigTime(), LL_RTC_ALMA_DATEWEEKDAYSEL_DATE, LL_RTC_ALMA_DisableWeekday(), LL_RTC_ALMA_EnableWeekday(), LL_RTC_ALMA_SetDay(), LL_RTC_ALMA_SetMask(), LL_RTC_ALMA_SetWeekDay(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_ALMA_StructInit ( LL_RTC_AlarmTypeDef * RTC_AlarmStruct )

Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).

Parameters:
RTC_AlarmStruct pointer to a LL_RTC_AlarmTypeDef structure which will be initialized.
Return values:
None

Definition at line 706 of file stm32f3xx_ll_rtc.c.

References LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, LL_RTC_TimeTypeDef::Hours, LL_RTC_ALMA_DATEWEEKDAYSEL_DATE, LL_RTC_ALMA_MASK_NONE, LL_RTC_ALMA_TIME_FORMAT_AM, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_ALMB_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_AlarmTypeDef * | RTC_AlarmStruct
 | ) |  |

Set the RTC Alarm B.

Note:
The Alarm register can only be written when the corresponding Alarm is disabled (LL_RTC_ALMB_Disable function).
Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_AlarmStruct | pointer to a LL_RTC_AlarmTypeDef structure that contains the alarm configuration parameters.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ALARMB registers are configured
  • ERROR: ALARMB registers are not configured

Definition at line 596 of file stm32f3xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL, IS_LL_RTC_ALMB_MASK, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, IS_LL_RTC_WEEKDAY, LL_RTC_ALMB_ConfigTime(), LL_RTC_ALMB_DATEWEEKDAYSEL_DATE, LL_RTC_ALMB_DisableWeekday(), LL_RTC_ALMB_EnableWeekday(), LL_RTC_ALMB_SetDay(), LL_RTC_ALMB_SetMask(), LL_RTC_ALMB_SetWeekDay(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_ALMB_StructInit ( LL_RTC_AlarmTypeDef * RTC_AlarmStruct )

Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).

Parameters:
RTC_AlarmStruct pointer to a LL_RTC_AlarmTypeDef structure which will be initialized.
Return values:
None

Definition at line 728 of file stm32f3xx_ll_rtc.c.

References LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, LL_RTC_TimeTypeDef::Hours, LL_RTC_ALMB_DATEWEEKDAYSEL_DATE, LL_RTC_ALMB_MASK_NONE, LL_RTC_ALMB_TIME_FORMAT_AM, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_DATE_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_DateTypeDef * | RTC_DateStruct
 | ) |  |

Set the RTC current date.

Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_DateStruct | pointer to a RTC_DateTypeDef structure that contains the date configuration information for the RTC.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC Day register is configured
  • ERROR: RTC Day register is not configured

Definition at line 388 of file stm32f3xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, assert_param, LL_RTC_DateTypeDef::Day, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_MONTH, IS_LL_RTC_WEEKDAY, IS_LL_RTC_YEAR, LL_RTC_DATE_Config(), LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_FORMAT_BIN, LL_RTC_IsShadowRegBypassEnabled(), LL_RTC_WaitForSynchro(), LL_RTC_DateTypeDef::Month, LL_RTC_DateTypeDef::WeekDay, and LL_RTC_DateTypeDef::Year.

void LL_RTC_DATE_StructInit ( LL_RTC_DateTypeDef * RTC_DateStruct )

Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)

Parameters:
RTC_DateStruct pointer to a LL_RTC_DateTypeDef structure which will be initialized.
Return values:
None

Definition at line 455 of file stm32f3xx_ll_rtc.c.

References LL_RTC_DateTypeDef::Day, LL_RTC_MONTH_JANUARY, LL_RTC_WEEKDAY_MONDAY, LL_RTC_DateTypeDef::Month, LL_RTC_DateTypeDef::WeekDay, and LL_RTC_DateTypeDef::Year.

ErrorStatus LL_RTC_DeInit ( RTC_TypeDef * RTCx )

De-Initializes the RTC registers to their default reset values.

Note:
This function doesn't reset the RTC Clock source and RTC Backup Data registers.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are de-initialized
  • ERROR: RTC registers are not de-initialized

Definition at line 165 of file stm32f3xx_ll_rtc.c.

References assert_param, LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_ReadReg, LL_RTC_WaitForSynchro(), LL_RTC_WriteReg, and RTC_SYNCH_PRESC_DEFAULT.

ErrorStatus LL_RTC_EnterInitMode ( RTC_TypeDef * RTCx )

Enters the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC is in Init mode
  • ERROR: RTC is not in Init mode

Definition at line 753 of file stm32f3xx_ll_rtc.c.

References assert_param, LL_RTC_EnableInitMode(), LL_RTC_IsActiveFlag_INIT(), LL_SYSTICK_IsActiveCounterFlag(), and RTC_INITMODE_TIMEOUT.

Referenced by LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

ErrorStatus LL_RTC_ExitInitMode ( RTC_TypeDef * RTCx )

Exit the RTC Initialization mode.

Note:
When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles.
The RTC Initialization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC exited from in Init mode
  • ERROR: Not applicable

Definition at line 797 of file stm32f3xx_ll_rtc.c.

References assert_param, and LL_RTC_DisableInitMode().

ErrorStatus LL_RTC_Init | ( | RTC_TypeDef * | RTCx,
 |  | LL_RTC_InitTypeDef * | RTC_InitStruct
 | ) |  |

Initializes the RTC registers according to the specified parameters in RTC_InitStruct.

Parameters:
RTCx | RTC Instance
RTC_InitStruct | pointer to a LL_RTC_InitTypeDef structure that contains the configuration information for the RTC peripheral.
Note:
The RTC Prescaler register is write protected and can be written in initialization mode only.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are initialized
  • ERROR: RTC registers are not initialized

Definition at line 226 of file stm32f3xx_ll_rtc.c.

References assert_param, LL_RTC_InitTypeDef::AsynchPrescaler, LL_RTC_InitTypeDef::HourFormat, IS_LL_RTC_ASYNCH_PREDIV, IS_LL_RTC_HOURFORMAT, IS_LL_RTC_SYNCH_PREDIV, LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_SetAsynchPrescaler(), LL_RTC_SetHourFormat(), LL_RTC_SetSynchPrescaler(), and LL_RTC_InitTypeDef::SynchPrescaler.

void LL_RTC_StructInit ( LL_RTC_InitTypeDef * RTC_InitStruct )

Set each LL_RTC_InitTypeDef field to default value.

Parameters:
RTC_InitStruct pointer to a LL_RTC_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 265 of file stm32f3xx_ll_rtc.c.

References LL_RTC_InitTypeDef::AsynchPrescaler, LL_RTC_InitTypeDef::HourFormat, LL_RTC_HOURFORMAT_24HOUR, RTC_ASYNCH_PRESC_DEFAULT, RTC_SYNCH_PRESC_DEFAULT, and LL_RTC_InitTypeDef::SynchPrescaler.

ErrorStatus LL_RTC_TIME_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_TimeTypeDef * | RTC_TimeStruct
 | ) |  |

Set the RTC current time.

Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_TimeStruct | pointer to a RTC_TimeTypeDef structure that contains the time configuration information for the RTC.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC Time register is configured
  • ERROR: RTC Time register is not configured

Definition at line 285 of file stm32f3xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_IsShadowRegBypassEnabled(), LL_RTC_TIME_Config(), LL_RTC_WaitForSynchro(), LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_TIME_StructInit ( LL_RTC_TimeTypeDef * RTC_TimeStruct )

Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).

Parameters:
RTC_TimeStruct pointer to a LL_RTC_TimeTypeDef structure which will be initialized.
Return values:
None

Definition at line 367 of file stm32f3xx_ll_rtc.c.

References LL_RTC_TimeTypeDef::Hours, LL_RTC_TIME_FORMAT_AM_OR_24, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_WaitForSynchro ( RTC_TypeDef * RTCx )

Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are synchronised
  • ERROR: RTC registers are not synchronised

Definition at line 824 of file stm32f3xx_ll_rtc.c.

References assert_param, LL_RTC_ClearFlag_RS(), LL_RTC_IsActiveFlag_RS(), LL_SYSTICK_IsActiveCounterFlag(), and RTC_SYNCHRO_TIMEOUT.

Referenced by LL_RTC_DATE_Init(), LL_RTC_DeInit(), and LL_RTC_TIME_Init().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI

Modules
SPI
STM32F3xx_LL_Driver

Modules

SPI Private Constants
SPI Private Macros
SPI Exported Init structure
SPI Exported Constants
SPI Exported Macros
SPI Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for SPI registers.

Register | Bit | Function
CR1 | BIDIMODE | LL_SPI_GetTransferDirection
 |  | LL_SPI_SetTransferDirection
 | BIDIOE | LL_SPI_GetTransferDirection
 |  | LL_SPI_SetTransferDirection
 | BR | LL_SPI_GetBaudRatePrescaler
 |  | LL_SPI_SetBaudRatePrescaler
 | CPHA | LL_SPI_GetClockPhase
 |  | LL_SPI_SetClockPhase
 | CPOL | LL_SPI_GetClockPolarity
 |  | LL_SPI_SetClockPolarity
 | CRCEN | LL_SPI_DisableCRC
 |  | LL_SPI_EnableCRC
 |  | LL_SPI_IsEnabledCRC
 | CRCL | LL_SPI_GetCRCWidth
 |  | LL_SPI_SetCRCWidth
 | CRCNEXT | LL_SPI_SetCRCNext
 | LSBFIRST | LL_SPI_GetTransferBitOrder
 |  | LL_SPI_SetTransferBitOrder
 | MSTR | LL_SPI_GetMode
 |  | LL_SPI_SetMode
 | RXONLY | LL_SPI_GetTransferDirection
 |  | LL_SPI_SetTransferDirection
 | SPE | LL_SPI_Disable
 |  | LL_SPI_Enable
 |  | LL_SPI_IsEnabled
 | SSI | LL_SPI_GetMode
 |  | LL_SPI_SetMode
 | SSM | LL_SPI_GetNSSMode
 |  | LL_SPI_SetNSSMode
CR2 | DS | LL_SPI_GetDataWidth
 |  | LL_SPI_SetDataWidth
 | ERRIE | LL_SPI_DisableIT_ERR
 |  | LL_SPI_EnableIT_ERR
 |  | LL_SPI_IsEnabledIT_ERR
 | FRF | LL_SPI_GetStandard
 |  | LL_SPI_SetStandard
 | FRXTH | LL_SPI_GetRxFIFOThreshold
 |  | LL_SPI_SetRxFIFOThreshold
 | LDMARX | LL_SPI_GetDMAParity_RX
 |  | LL_SPI_SetDMAParity_RX
 | LDMATX | LL_SPI_GetDMAParity_TX
 |  | LL_SPI_SetDMAParity_TX
 | NSSP | LL_SPI_DisableNSSPulseMgt
 |  | LL_SPI_EnableNSSPulseMgt
 |  | LL_SPI_IsEnabledNSSPulse
 | RXDMAEN | LL_SPI_DisableDMAReq_RX
 |  | LL_SPI_EnableDMAReq_RX
 |  | LL_SPI_IsEnabledDMAReq_RX
 | RXNEIE | LL_SPI_DisableIT_RXNE
 |  | LL_SPI_EnableIT_RXNE
 |  | LL_SPI_IsEnabledIT_RXNE
 | SSOE | LL_SPI_GetNSSMode
 |  | LL_SPI_SetNSSMode
 | TXDMAEN | LL_SPI_DisableDMAReq_TX
 |  | LL_SPI_EnableDMAReq_TX
 |  | LL_SPI_IsEnabledDMAReq_TX
 | TXEIE | LL_SPI_DisableIT_TXE
 |  | LL_SPI_EnableIT_TXE
 |  | LL_SPI_IsEnabledIT_TXE
CRCPR | CRCPOLY | LL_SPI_GetCRCPolynomial
 |  | LL_SPI_SetCRCPolynomial
DR | DR | LL_SPI_DMA_GetRegAddr
 |  | LL_SPI_ReceiveData16
 |  | LL_SPI_ReceiveData8
 |  | LL_SPI_TransmitData16
 |  | LL_SPI_TransmitData8
RXCRCR | RXCRC | LL_SPI_GetRxCRC
SR | BSY | LL_SPI_IsActiveFlag_BSY
 | CRCERR | LL_SPI_ClearFlag_CRCERR
 |  | LL_SPI_IsActiveFlag_CRCERR
 | FRE | LL_SPI_ClearFlag_FRE
 |  | LL_SPI_IsActiveFlag_FRE
 | FRLVL | LL_SPI_GetRxFIFOLevel
 | FTLVL | LL_SPI_GetTxFIFOLevel
 | MODF | LL_SPI_ClearFlag_MODF
 |  | LL_SPI_IsActiveFlag_MODF
 | OVR | LL_SPI_ClearFlag_OVR
 |  | LL_SPI_IsActiveFlag_OVR
 | RXNE | LL_SPI_IsActiveFlag_RXNE
 | TXE | LL_SPI_IsActiveFlag_TXE
TXCRCR | TXCRC | LL_SPI_GetTxCRC
Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Private Constants

Defines
SPI Private Constants
SPI

Defines

#define SPI_CR1_CLEAR_MASK

Define Documentation

#define SPI_CR1_CLEAR_MASK
Value:
(SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
                                            SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
                                            SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
                                            SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
                                            SPI_CR1_BIDIMODE)

Definition at line 66 of file stm32f3xx_ll_spi.c.

Referenced by LL_SPI_Init().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Private Macros

Defines
SPI Private Macros
SPI

Defines

#define | IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)
#define | IS_LL_SPI_MODE(__VALUE__)
#define | IS_LL_SPI_DATAWIDTH(__VALUE__)
#define | IS_LL_SPI_POLARITY(__VALUE__)
#define | IS_LL_SPI_PHASE(__VALUE__)
#define | IS_LL_SPI_NSS(__VALUE__)
#define | IS_LL_SPI_BAUDRATE(__VALUE__)
#define | IS_LL_SPI_BITORDER(__VALUE__)
#define | IS_LL_SPI_CRCCALCULATION(__VALUE__)
#define | IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)

Define Documentation

#define IS_LL_SPI_BAUDRATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)   \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))

Definition at line 111 of file stm32f3xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_BITORDER ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_LSB_FIRST) \
                                    || ((__VALUE__) == LL_SPI_MSB_FIRST))

Definition at line 120 of file stm32f3xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_CRC_POLYNOMIAL ( __VALUE__ ) ((__VALUE__) >= 0x1U)

Definition at line 126 of file stm32f3xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_CRCCALCULATION ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
                                          || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))

Definition at line 123 of file stm32f3xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)  \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))

Definition at line 87 of file stm32f3xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_MODE_MASTER) \
                                || ((__VALUE__) == LL_SPI_MODE_SLAVE))

Definition at line 84 of file stm32f3xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_NSS ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_NSS_SOFT) \
                               || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
                               || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))

Definition at line 107 of file stm32f3xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_PHASE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_PHASE_1EDGE) \
                                 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))

Definition at line 104 of file stm32f3xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_POLARITY_LOW) \
                                    || ((__VALUE__) == LL_SPI_POLARITY_HIGH))

Definition at line 101 of file stm32f3xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_TRANSFER_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_FULL_DUPLEX)    \
                                              || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
                                              || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
                                              || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))

Definition at line 79 of file stm32f3xx_ll_spi.c.

Referenced by LL_SPI_Init().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_SPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_SPI_InitTypeDef Struct Reference
SPI Exported Init structure

SPI Init structures definition. More...

#include <stm32f3xx_ll_spi.h>

Data Fields

uint32_t | TransferDirection
uint32_t | Mode
uint32_t | DataWidth
uint32_t | ClockPolarity
uint32_t | ClockPhase
uint32_t | NSS
uint32_t | BaudRate
uint32_t | BitOrder
uint32_t | CRCCalculation
uint32_t | CRCPoly

Detailed Description

SPI Init structures definition.

Definition at line 70 of file stm32f3xx_ll_spi.h.

Field Documentation

uint32_t LL_SPI_InitTypeDef::BaudRate

Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of Baud Rate Prescaler.

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

This feature can be modified afterwards using unitary function LL_SPI_SetBaudRatePrescaler().

Definition at line 102 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::BitOrder

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of Transmission Bit Order.

This feature can be modified afterwards using unitary function LL_SPI_SetTransferBitOrder().

Definition at line 108 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::ClockPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of Clock Phase.

This feature can be modified afterwards using unitary function LL_SPI_SetClockPhase().

Definition at line 92 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::ClockPolarity

Specifies the serial clock steady state. This parameter can be a value of Clock Polarity.

This feature can be modified afterwards using unitary function LL_SPI_SetClockPolarity().

Definition at line 87 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of CRC Calculation.

This feature can be modified afterwards using unitary functions LL_SPI_EnableCRC() and LL_SPI_DisableCRC().

Definition at line 113 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::CRCPoly

Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.

This feature can be modified afterwards using unitary function LL_SPI_SetCRCPolynomial().

Definition at line 118 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::DataWidth

Specifies the SPI data width. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_SPI_SetDataWidth().

Definition at line 82 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::Mode

Specifies the SPI mode (Master/Slave). This parameter can be a value of Operation Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetMode().

Definition at line 77 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of Slave Select Pin Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetNSSMode().

Definition at line 97 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::TransferDirection

Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of Transfer Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetTransferDirection().

Definition at line 72 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_spi.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
SPI Exported Constants

Flags defines which can be used with LL_SPI_ReadReg function. More...

Defines

#define | LL_SPI_SR_RXNE SPI_SR_RXNE
#define | LL_SPI_SR_TXE SPI_SR_TXE
#define | LL_SPI_SR_BSY SPI_SR_BSY
#define | LL_SPI_SR_CRCERR SPI_SR_CRCERR
#define | LL_SPI_SR_MODF SPI_SR_MODF
#define | LL_SPI_SR_OVR SPI_SR_OVR
#define | LL_SPI_SR_FRE SPI_SR_FRE

Detailed Description

Flags defines which can be used with LL_SPI_ReadReg function.

Define Documentation

#define LL_SPI_SR_BSY SPI_SR_BSY

Busy flag

Definition at line 141 of file stm32f3xx_ll_spi.h.

#define LL_SPI_SR_CRCERR SPI_SR_CRCERR

CRC error flag

Definition at line 142 of file stm32f3xx_ll_spi.h.

#define LL_SPI_SR_FRE SPI_SR_FRE

TI mode frame format error flag

Definition at line 145 of file stm32f3xx_ll_spi.h.

#define LL_SPI_SR_MODF SPI_SR_MODF

Mode fault flag

Definition at line 143 of file stm32f3xx_ll_spi.h.

#define LL_SPI_SR_OVR SPI_SR_OVR

Overrun flag

Definition at line 144 of file stm32f3xx_ll_spi.h.

#define LL_SPI_SR_RXNE SPI_SR_RXNE

Rx buffer not empty flag

Definition at line 139 of file stm32f3xx_ll_spi.h.

#define LL_SPI_SR_TXE SPI_SR_TXE

Tx buffer empty flag

Definition at line 140 of file stm32f3xx_ll_spi.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IT Defines

Defines
IT Defines
SPI Exported Constants | I2S Exported Constants

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions. More...

Defines

#define | LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE
#define | LL_SPI_CR2_TXEIE SPI_CR2_TXEIE
#define | LL_SPI_CR2_ERRIE SPI_CR2_ERRIE
#define | LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE
#define | LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE
#define | LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE

Detailed Description

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Define Documentation

#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE

Error interrupt enable

Definition at line 1503 of file stm32f3xx_ll_spi.h.

#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE

Rx buffer not empty interrupt enable

Definition at line 1501 of file stm32f3xx_ll_spi.h.

#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE

Tx buffer empty interrupt enable

Definition at line 1502 of file stm32f3xx_ll_spi.h.

#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE

Error interrupt enable

Definition at line 156 of file stm32f3xx_ll_spi.h.

#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE

Rx buffer not empty interrupt enable

Definition at line 154 of file stm32f3xx_ll_spi.h.

#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE

Tx buffer empty interrupt enable

Definition at line 155 of file stm32f3xx_ll_spi.h.

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STM32F373xC HAL User Manual: Operation Mode

Defines
Operation Mode
SPI Exported Constants

Defines

#define | LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | LL_SPI_MODE_SLAVE 0x00000000U

Define Documentation

#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Master configuration

Definition at line 164 of file stm32f3xx_ll_spi.h.

#define LL_SPI_MODE_SLAVE 0x00000000U

Slave configuration

Definition at line 165 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Serial Protocol

Defines
Serial Protocol
SPI Exported Constants

Defines

#define | LL_SPI_PROTOCOL_MOTOROLA 0x00000000U
#define | LL_SPI_PROTOCOL_TI (SPI_CR2_FRF)

Define Documentation

#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U

Motorola mode. Used as default value

Definition at line 173 of file stm32f3xx_ll_spi.h.

#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF)

TI mode

Definition at line 174 of file stm32f3xx_ll_spi.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Clock Phase

Defines
Clock Phase
SPI Exported Constants

Defines

#define | LL_SPI_PHASE_1EDGE 0x00000000U
#define | LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)

Define Documentation

#define LL_SPI_PHASE_1EDGE 0x00000000U

First clock transition is the first data capture edge

Definition at line 182 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)

Second clock transition is the first data capture edge

Definition at line 183 of file stm32f3xx_ll_spi.h.

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STM32F373xC HAL User Manual: Clock Polarity

Defines
Clock Polarity
SPI Exported Constants

Defines

#define | LL_SPI_POLARITY_LOW 0x00000000U
#define | LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)

Define Documentation

#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)

Clock to 1 when idle

Definition at line 192 of file stm32f3xx_ll_spi.h.

#define LL_SPI_POLARITY_LOW 0x00000000U

Clock to 0 when idle

Definition at line 191 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Baud Rate Prescaler

Defines
Baud Rate Prescaler
SPI Exported Constants

Defines

#define | LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U
#define | LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)
#define | LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

Define Documentation

#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)

BaudRate control equal to fPCLK/128

Definition at line 206 of file stm32f3xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/16

Definition at line 203 of file stm32f3xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U

BaudRate control equal to fPCLK/2

Definition at line 200 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/256

Definition at line 207 of file stm32f3xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)

BaudRate control equal to fPCLK/32

Definition at line 204 of file stm32f3xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)

BaudRate control equal to fPCLK/4

Definition at line 201 of file stm32f3xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/64

Definition at line 205 of file stm32f3xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)

BaudRate control equal to fPCLK/8

Definition at line 202 of file stm32f3xx_ll_spi.h.

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STM32F373xC HAL User Manual: Transmission Bit Order

Defines
Transmission Bit Order
SPI Exported Constants

Defines

#define | LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)
#define | LL_SPI_MSB_FIRST 0x00000000U

Define Documentation

#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)

Data is transmitted/received with the LSB first

Definition at line 215 of file stm32f3xx_ll_spi.h.

#define LL_SPI_MSB_FIRST 0x00000000U

Data is transmitted/received with the MSB first

Definition at line 216 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

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STM32F373xC HAL User Manual: Transfer Mode

Defines
Transfer Mode
SPI Exported Constants

Defines

#define | LL_SPI_FULL_DUPLEX 0x00000000U
#define | LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)
#define | LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)
#define | LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)

Define Documentation

#define LL_SPI_FULL_DUPLEX 0x00000000U

Full-Duplex mode. Rx and Tx transfer on 2 lines

Definition at line 224 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)

Half-Duplex Rx mode. Rx transfer on 1 line

Definition at line 226 of file stm32f3xx_ll_spi.h.

#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)

Half-Duplex Tx mode. Tx transfer on 1 line

Definition at line 227 of file stm32f3xx_ll_spi.h.

#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)

Simplex Rx mode. Rx transfer only on 1 line

Definition at line 225 of file stm32f3xx_ll_spi.h.

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STM32F373xC HAL User Manual: Slave Select Pin Mode

Defines
Slave Select Pin Mode
SPI Exported Constants

Defines

#define | LL_SPI_NSS_SOFT (SPI_CR1_SSM)
#define | LL_SPI_NSS_HARD_INPUT 0x00000000U
#define | LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))

Define Documentation

#define LL_SPI_NSS_HARD_INPUT 0x00000000U

NSS pin used in Input. Only used in Master mode

Definition at line 236 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))

NSS pin used in Output. Only used in Slave mode as chip select

Definition at line 237 of file stm32f3xx_ll_spi.h.

#define LL_SPI_NSS_SOFT (SPI_CR1_SSM)

NSS managed internally. NSS pin not used and free

Definition at line 235 of file stm32f3xx_ll_spi.h.

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STM32F373xC HAL User Manual: Datawidth

Defines
Datawidth
SPI Exported Constants

Defines

#define | LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3)
#define | LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Define Documentation

#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0)

Data length for SPI transfer: 10 bits

Definition at line 251 of file stm32f3xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1)

Data length for SPI transfer: 11 bits

Definition at line 252 of file stm32f3xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Data length for SPI transfer: 12 bits

Definition at line 253 of file stm32f3xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2)

Data length for SPI transfer: 13 bits

Definition at line 254 of file stm32f3xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)

Data length for SPI transfer: 14 bits

Definition at line 255 of file stm32f3xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)

Data length for SPI transfer: 15 bits

Definition at line 256 of file stm32f3xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Data length for SPI transfer: 16 bits

Definition at line 257 of file stm32f3xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1)

Data length for SPI transfer: 4 bits

Definition at line 245 of file stm32f3xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2)

Data length for SPI transfer: 5 bits

Definition at line 246 of file stm32f3xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0)

Data length for SPI transfer: 6 bits

Definition at line 247 of file stm32f3xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1)

Data length for SPI transfer: 7 bits

Definition at line 248 of file stm32f3xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Data length for SPI transfer: 8 bits

Definition at line 249 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3)

Data length for SPI transfer: 9 bits

Definition at line 250 of file stm32f3xx_ll_spi.h.

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STM32F373xC HAL User Manual: CRC Calculation

Defines
CRC Calculation
SPI Exported Constants

Defines

#define | LL_SPI_CRCCALCULATION_DISABLE 0x00000000U
#define | LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)

Define Documentation

#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U

CRC calculation disabled

Definition at line 266 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)

CRC calculation enabled

Definition at line 267 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_Init().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRC Length

Defines
CRC Length
SPI Exported Constants

Defines

#define | LL_SPI_CRC_8BIT 0x00000000U
#define | LL_SPI_CRC_16BIT (SPI_CR1_CRCL)

Define Documentation

#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL)

16-bit CRC length

Definition at line 277 of file stm32f3xx_ll_spi.h.

#define LL_SPI_CRC_8BIT 0x00000000U

8-bit CRC length

Definition at line 276 of file stm32f3xx_ll_spi.h.

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STM32F373xC HAL User Manual: RX FIFO Threshold

Defines
RX FIFO Threshold
SPI Exported Constants

Defines

#define | LL_SPI_RX_FIFO_TH_HALF 0x00000000U
#define | LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH)

Define Documentation

#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U

RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit)

Definition at line 285 of file stm32f3xx_ll_spi.h.

#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH)

RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit)

Definition at line 286 of file stm32f3xx_ll_spi.h.

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STM32F373xC HAL User Manual: RX FIFO Level

Defines
RX FIFO Level
SPI Exported Constants

Defines

#define | LL_SPI_RX_FIFO_EMPTY 0x00000000U
#define | LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0)
#define | LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1)
#define | LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0)

Define Documentation

#define LL_SPI_RX_FIFO_EMPTY 0x00000000U

FIFO reception empty

Definition at line 294 of file stm32f3xx_ll_spi.h.

#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0)

FIFO reception full

Definition at line 297 of file stm32f3xx_ll_spi.h.

#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1)

FIFO reception 1/2

Definition at line 296 of file stm32f3xx_ll_spi.h.

#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0)

FIFO reception 1/4

Definition at line 295 of file stm32f3xx_ll_spi.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TX FIFO Level

Defines
TX FIFO Level
SPI Exported Constants

Defines

#define | LL_SPI_TX_FIFO_EMPTY 0x00000000U
#define | LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0)
#define | LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1)
#define | LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0)

Define Documentation

#define LL_SPI_TX_FIFO_EMPTY 0x00000000U

FIFO transmission empty

Definition at line 305 of file stm32f3xx_ll_spi.h.

#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0)

FIFO transmission full

Definition at line 308 of file stm32f3xx_ll_spi.h.

#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1)

FIFO transmission 1/2

Definition at line 307 of file stm32f3xx_ll_spi.h.

#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0)

FIFO transmission 1/4

Definition at line 306 of file stm32f3xx_ll_spi.h.

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STM32F373xC HAL User Manual: DMA Parity

Defines
DMA Parity
SPI Exported Constants

Defines

#define | LL_SPI_DMA_PARITY_EVEN 0x00000000U
#define | LL_SPI_DMA_PARITY_ODD 0x00000001U

Define Documentation

#define LL_SPI_DMA_PARITY_EVEN 0x00000000U

Select DMA parity Even

Definition at line 316 of file stm32f3xx_ll_spi.h.

#define LL_SPI_DMA_PARITY_ODD 0x00000001U

Select DMA parity Odd

Definition at line 317 of file stm32f3xx_ll_spi.h.

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STM32F373xC HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
SPI Exported Macros

Defines

#define | LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SPI register.
#define | LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SPI register.

Define Documentation

#define LL_SPI_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in SPI register.

Parameters:
__INSTANCE__ | SPI Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 351 of file stm32f3xx_ll_spi.h.

#define LL_SPI_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in SPI register.

Parameters:
__INSTANCE__ | SPI Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 343 of file stm32f3xx_ll_spi.h.

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STM32F373xC HAL User Manual: Configuration

Functions
Configuration
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_Enable (SPI_TypeDef *SPIx)
Enable SPI peripheral.
__STATIC_INLINE void | LL_SPI_Disable (SPI_TypeDef *SPIx)
Disable SPI peripheral.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabled (SPI_TypeDef *SPIx)
Check if SPI peripheral is enabled.
__STATIC_INLINE void | LL_SPI_SetMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set SPI operation mode to Master or Slave.
__STATIC_INLINE uint32_t | LL_SPI_GetMode (SPI_TypeDef *SPIx)
Get SPI operation mode (Master or Slave)
__STATIC_INLINE void | LL_SPI_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set serial protocol used.
__STATIC_INLINE uint32_t | LL_SPI_GetStandard (SPI_TypeDef *SPIx)
Get serial protocol used.
__STATIC_INLINE void | LL_SPI_SetClockPhase (SPI_TypeDef *SPIx, uint32_t ClockPhase)
Set clock phase.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPhase (SPI_TypeDef *SPIx)
Get clock phase.
__STATIC_INLINE void | LL_SPI_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set clock polarity.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPolarity (SPI_TypeDef *SPIx)
Get clock polarity.
__STATIC_INLINE void | LL_SPI_SetBaudRatePrescaler (SPI_TypeDef *SPIx, uint32_t BaudRate)
Set baud rate prescaler.
__STATIC_INLINE uint32_t | LL_SPI_GetBaudRatePrescaler (SPI_TypeDef *SPIx)
Get baud rate prescaler.
__STATIC_INLINE void | LL_SPI_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder)
Set transfer bit order.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferBitOrder (SPI_TypeDef *SPIx)
Get transfer bit order.
__STATIC_INLINE void | LL_SPI_SetTransferDirection (SPI_TypeDef *SPIx, uint32_t TransferDirection)
Set transfer direction mode.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferDirection (SPI_TypeDef *SPIx)
Get transfer direction mode.
__STATIC_INLINE void | LL_SPI_SetDataWidth (SPI_TypeDef *SPIx, uint32_t DataWidth)
Set frame data width.
__STATIC_INLINE uint32_t | LL_SPI_GetDataWidth (SPI_TypeDef *SPIx)
Get frame data width.
__STATIC_INLINE void | LL_SPI_SetRxFIFOThreshold (SPI_TypeDef *SPIx, uint32_t Threshold)
Set threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOThreshold (SPI_TypeDef *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.

Function Documentation

__STATIC_INLINE void LL_SPI_Disable ( SPI_TypeDef * SPIx )

Disable SPI peripheral.

Note:
When disabling the SPI, follow the procedure described in the Reference Manual.
Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_Disable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 387 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_Enable ( SPI_TypeDef * SPIx )

Enable SPI peripheral.

Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_Enable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 375 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler ( SPI_TypeDef * SPIx )

Get baud rate prescaler.

Reference Manual to LL API cross reference:
CR1 BR LL_SPI_GetBaudRatePrescaler
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_BAUDRATEPRESCALER_DIV2
  • LL_SPI_BAUDRATEPRESCALER_DIV4
  • LL_SPI_BAUDRATEPRESCALER_DIV8
  • LL_SPI_BAUDRATEPRESCALER_DIV16
  • LL_SPI_BAUDRATEPRESCALER_DIV32
  • LL_SPI_BAUDRATEPRESCALER_DIV64
  • LL_SPI_BAUDRATEPRESCALER_DIV128
  • LL_SPI_BAUDRATEPRESCALER_DIV256

Definition at line 554 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetClockPhase ( SPI_TypeDef * SPIx )

Get clock phase.

Reference Manual to LL API cross reference:
CR1 CPHA LL_SPI_GetClockPhase
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_PHASE_1EDGE
  • LL_SPI_PHASE_2EDGE

Definition at line 485 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity ( SPI_TypeDef * SPIx )

Get clock polarity.

Reference Manual to LL API cross reference:
CR1 CPOL LL_SPI_GetClockPolarity
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_POLARITY_LOW
  • LL_SPI_POLARITY_HIGH

Definition at line 514 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetDataWidth ( SPI_TypeDef * SPIx )

Get frame data width.

Reference Manual to LL API cross reference:
CR2 DS LL_SPI_GetDataWidth
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_DATAWIDTH_4BIT
  • LL_SPI_DATAWIDTH_5BIT
  • LL_SPI_DATAWIDTH_6BIT
  • LL_SPI_DATAWIDTH_7BIT
  • LL_SPI_DATAWIDTH_8BIT
  • LL_SPI_DATAWIDTH_9BIT
  • LL_SPI_DATAWIDTH_10BIT
  • LL_SPI_DATAWIDTH_11BIT
  • LL_SPI_DATAWIDTH_12BIT
  • LL_SPI_DATAWIDTH_13BIT
  • LL_SPI_DATAWIDTH_14BIT
  • LL_SPI_DATAWIDTH_15BIT
  • LL_SPI_DATAWIDTH_16BIT

Definition at line 668 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetMode ( SPI_TypeDef * SPIx )

Get SPI operation mode (Master or Slave)

Reference Manual to LL API cross reference:
CR1 MSTR LL_SPI_GetMode
CR1 SSI LL_SPI_GetMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_MODE_MASTER
  • LL_SPI_MODE_SLAVE

Definition at line 428 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold ( SPI_TypeDef * SPIx )

Get threshold of RXFIFO that triggers an RXNE event.

Reference Manual to LL API cross reference:
CR2 FRXTH LL_SPI_GetRxFIFOThreshold
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_RX_FIFO_TH_HALF
  • LL_SPI_RX_FIFO_TH_QUARTER

Definition at line 695 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetStandard ( SPI_TypeDef * SPIx )

Get serial protocol used.

Reference Manual to LL API cross reference:
CR2 FRF LL_SPI_GetStandard
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_PROTOCOL_MOTOROLA
  • LL_SPI_PROTOCOL_TI

Definition at line 456 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder ( SPI_TypeDef * SPIx )

Get transfer bit order.

Reference Manual to LL API cross reference:
CR1 LSBFIRST LL_SPI_GetTransferBitOrder
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_LSB_FIRST
  • LL_SPI_MSB_FIRST

Definition at line 582 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection ( SPI_TypeDef * SPIx )

Get transfer direction mode.

Reference Manual to LL API cross reference:
CR1 RXONLY LL_SPI_GetTransferDirection
CR1 BIDIMODE LL_SPI_GetTransferDirection
CR1 BIDIOE LL_SPI_GetTransferDirection
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_FULL_DUPLEX
  • LL_SPI_SIMPLEX_RX
  • LL_SPI_HALF_DUPLEX_RX
  • LL_SPI_HALF_DUPLEX_TX

Definition at line 619 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabled ( SPI_TypeDef * SPIx )

Check if SPI peripheral is enabled.

Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_IsEnabled
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 398 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_Init().

__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | BaudRate
 | ) |  |

Set baud rate prescaler.

Note:
These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
Reference Manual to LL API cross reference:
CR1 BR LL_SPI_SetBaudRatePrescaler
Parameters:
SPIx SPI Instance
BaudRate This parameter can be one of the following values:
  • LL_SPI_BAUDRATEPRESCALER_DIV2
  • LL_SPI_BAUDRATEPRESCALER_DIV4
  • LL_SPI_BAUDRATEPRESCALER_DIV8
  • LL_SPI_BAUDRATEPRESCALER_DIV16
  • LL_SPI_BAUDRATEPRESCALER_DIV32
  • LL_SPI_BAUDRATEPRESCALER_DIV64
  • LL_SPI_BAUDRATEPRESCALER_DIV128
  • LL_SPI_BAUDRATEPRESCALER_DIV256
Return values:
None

Definition at line 535 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetClockPhase | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPhase
 | ) |  |

Set clock phase.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 CPHA LL_SPI_SetClockPhase
Parameters:
SPIx SPI Instance
ClockPhase This parameter can be one of the following values:
  • LL_SPI_PHASE_1EDGE
  • LL_SPI_PHASE_2EDGE
Return values:
None

Definition at line 472 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetClockPolarity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Set clock polarity.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 CPOL LL_SPI_SetClockPolarity
Parameters:
SPIx SPI Instance
ClockPolarity This parameter can be one of the following values:
  • LL_SPI_POLARITY_LOW
  • LL_SPI_POLARITY_HIGH
Return values:
None

Definition at line 501 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetDataWidth | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | DataWidth
 | ) |  |

Set frame data width.

Reference Manual to LL API cross reference:
CR2 DS LL_SPI_SetDataWidth
Parameters:
SPIx SPI Instance
DataWidth This parameter can be one of the following values:
  • LL_SPI_DATAWIDTH_4BIT
  • LL_SPI_DATAWIDTH_5BIT
  • LL_SPI_DATAWIDTH_6BIT
  • LL_SPI_DATAWIDTH_7BIT
  • LL_SPI_DATAWIDTH_8BIT
  • LL_SPI_DATAWIDTH_9BIT
  • LL_SPI_DATAWIDTH_10BIT
  • LL_SPI_DATAWIDTH_11BIT
  • LL_SPI_DATAWIDTH_12BIT
  • LL_SPI_DATAWIDTH_13BIT
  • LL_SPI_DATAWIDTH_14BIT
  • LL_SPI_DATAWIDTH_15BIT
  • LL_SPI_DATAWIDTH_16BIT
Return values:
None

Definition at line 644 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Mode
 | ) |  |

Set SPI operation mode to Master or Slave.

Note:
This bit should not be changed when communication is ongoing.
Reference Manual to LL API cross reference:
CR1 MSTR LL_SPI_SetMode
CR1 SSI LL_SPI_SetMode
Parameters:
SPIx SPI Instance
Mode This parameter can be one of the following values:
  • LL_SPI_MODE_MASTER
  • LL_SPI_MODE_SLAVE
Return values:
None

Definition at line 414 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Threshold
 | ) |  |

Set threshold of RXFIFO that triggers an RXNE event.

Reference Manual to LL API cross reference:
CR2 FRXTH LL_SPI_SetRxFIFOThreshold
Parameters:
SPIx SPI Instance
Threshold This parameter can be one of the following values:
  • LL_SPI_RX_FIFO_TH_HALF
  • LL_SPI_RX_FIFO_TH_QUARTER
Return values:
None

Definition at line 682 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetStandard | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Standard
 | ) |  |

Set serial protocol used.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR2 FRF LL_SPI_SetStandard
Parameters:
SPIx SPI Instance
Standard This parameter can be one of the following values:
  • LL_SPI_PROTOCOL_MOTOROLA
  • LL_SPI_PROTOCOL_TI
Return values:
None

Definition at line 443 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetTransferBitOrder | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | BitOrder
 | ) |  |

Set transfer bit order.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 LSBFIRST LL_SPI_SetTransferBitOrder
Parameters:
SPIx SPI Instance
BitOrder This parameter can be one of the following values:
  • LL_SPI_LSB_FIRST
  • LL_SPI_MSB_FIRST
Return values:
None

Definition at line 569 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetTransferDirection | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | TransferDirection
 | ) |  |

Set transfer direction mode.

Note:
For Half-Duplex mode, Rx Direction is set by default. In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
Reference Manual to LL API cross reference:
CR1 RXONLY LL_SPI_SetTransferDirection
CR1 BIDIMODE LL_SPI_SetTransferDirection
CR1 BIDIOE LL_SPI_SetTransferDirection
Parameters:
SPIx SPI Instance
TransferDirection This parameter can be one of the following values:
  • LL_SPI_FULL_DUPLEX
  • LL_SPI_SIMPLEX_RX
  • LL_SPI_HALF_DUPLEX_RX
  • LL_SPI_HALF_DUPLEX_TX
Return values:
None

Definition at line 602 of file stm32f3xx_ll_spi.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRC Management

Functions
CRC Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableCRC (SPI_TypeDef *SPIx)
Enable CRC.
__STATIC_INLINE void | LL_SPI_DisableCRC (SPI_TypeDef *SPIx)
Disable CRC.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledCRC (SPI_TypeDef *SPIx)
Check if CRC is enabled.
__STATIC_INLINE void | LL_SPI_SetCRCWidth (SPI_TypeDef *SPIx, uint32_t CRCLength)
Set CRC Length.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCWidth (SPI_TypeDef *SPIx)
Get CRC Length.
__STATIC_INLINE void | LL_SPI_SetCRCNext (SPI_TypeDef *SPIx)
Set CRCNext to transfer CRC on the line.
__STATIC_INLINE void | LL_SPI_SetCRCPolynomial (SPI_TypeDef *SPIx, uint32_t CRCPoly)
Set polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Get polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetRxCRC (SPI_TypeDef *SPIx)
Get Rx CRC.
__STATIC_INLINE uint32_t | LL_SPI_GetTxCRC (SPI_TypeDef *SPIx)
Get Tx CRC.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableCRC ( SPI_TypeDef * SPIx )

Disable CRC.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_DisableCRC
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 727 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableCRC ( SPI_TypeDef * SPIx )

Enable CRC.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_EnableCRC
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 715 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial ( SPI_TypeDef * SPIx )

Get polynomial for CRC calculation.

Reference Manual to LL API cross reference:
CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 802 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth ( SPI_TypeDef * SPIx )

Get CRC Length.

Reference Manual to LL API cross reference:
CR1 CRCL LL_SPI_GetCRCWidth
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_CRC_8BIT
  • LL_SPI_CRC_16BIT

Definition at line 767 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetRxCRC ( SPI_TypeDef * SPIx )

Get Rx CRC.

Reference Manual to LL API cross reference:
RXCRCR RXCRC LL_SPI_GetRxCRC
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 813 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTxCRC ( SPI_TypeDef * SPIx )

Get Tx CRC.

Reference Manual to LL API cross reference:
TXCRCR TXCRC LL_SPI_GetTxCRC
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 824 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC ( SPI_TypeDef * SPIx )

Check if CRC is enabled.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_IsEnabledCRC
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 739 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetCRCNext ( SPI_TypeDef * SPIx )

Set CRCNext to transfer CRC on the line.

Note:
This bit has to be written as soon as the last data is written in the SPIx_DR register.
Reference Manual to LL API cross reference:
CR1 CRCNEXT LL_SPI_SetCRCNext
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 779 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetCRCPolynomial | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | CRCPoly
 | ) |  |

Set polynomial for CRC calculation.

Reference Manual to LL API cross reference:
CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
Parameters:
SPIx | SPI Instance
CRCPoly | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
Return values:
None

Definition at line 791 of file stm32f3xx_ll_spi.h.

Referenced by LL_SPI_Init().

__STATIC_INLINE void LL_SPI_SetCRCWidth | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | CRCLength
 | ) |  |

Set CRC Length.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCL LL_SPI_SetCRCWidth
Parameters:
SPIx SPI Instance
CRCLength This parameter can be one of the following values:
  • LL_SPI_CRC_8BIT
  • LL_SPI_CRC_16BIT
Return values:
None

Definition at line 754 of file stm32f3xx_ll_spi.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Slave Select Pin Management

Functions
Slave Select Pin Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_SetNSSMode (SPI_TypeDef *SPIx, uint32_t NSS)
Set NSS mode.
__STATIC_INLINE uint32_t | LL_SPI_GetNSSMode (SPI_TypeDef *SPIx)
Get NSS mode.
__STATIC_INLINE void | LL_SPI_EnableNSSPulseMgt (SPI_TypeDef *SPIx)
Enable NSS pulse management.
__STATIC_INLINE void | LL_SPI_DisableNSSPulseMgt (SPI_TypeDef *SPIx)
Disable NSS pulse management.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledNSSPulse (SPI_TypeDef *SPIx)
Check if NSS pulse is enabled.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt ( SPI_TypeDef * SPIx )

Disable NSS pulse management.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR2 NSSP LL_SPI_DisableNSSPulseMgt
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 891 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt ( SPI_TypeDef * SPIx )

Enable NSS pulse management.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR2 NSSP LL_SPI_EnableNSSPulseMgt
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 879 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetNSSMode ( SPI_TypeDef * SPIx )

Get NSS mode.

Reference Manual to LL API cross reference:
CR1 SSM LL_SPI_GetNSSMode
Reference Manual to LL API cross reference:
CR2 SSOE LL_SPI_GetNSSMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_NSS_SOFT
  • LL_SPI_NSS_HARD_INPUT
  • LL_SPI_NSS_HARD_OUTPUT

Definition at line 865 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse ( SPI_TypeDef * SPIx )

Check if NSS pulse is enabled.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR2 NSSP LL_SPI_IsEnabledNSSPulse
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 903 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetNSSMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | NSS
 | ) |  |

Set NSS mode.

Note:
LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 SSM LL_SPI_SetNSSMode
Reference Manual to LL API cross reference:
CR2 SSOE LL_SPI_SetNSSMode
Parameters:
SPIx SPI Instance
NSS This parameter can be one of the following values:
  • LL_SPI_NSS_SOFT
  • LL_SPI_NSS_HARD_INPUT
  • LL_SPI_NSS_HARD_OUTPUT
Return values:
None

Definition at line 849 of file stm32f3xx_ll_spi.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLAG Management

Functions
FLAG Management
SPI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_CRCERR (SPI_TypeDef *SPIx)
Get CRC error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_MODF (SPI_TypeDef *SPIx)
Get mode fault error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO reception Level.
__STATIC_INLINE uint32_t | LL_SPI_GetTxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO Transmission Level.
__STATIC_INLINE void | LL_SPI_ClearFlag_CRCERR (SPI_TypeDef *SPIx)
Clear CRC error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_MODF (SPI_TypeDef *SPIx)
Clear mode fault error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.

Function Documentation

__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR ( SPI_TypeDef * SPIx )

Clear CRC error flag.

Reference Manual to LL API cross reference:
SR CRCERR LL_SPI_ClearFlag_CRCERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1036 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_FRE ( SPI_TypeDef * SPIx )

Clear frame format error flag.

Note:
Clearing this flag is done by reading SPIx_SR register
Reference Manual to LL API cross reference:
SR FRE LL_SPI_ClearFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1082 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_ClearFlag_FRE().

__STATIC_INLINE void LL_SPI_ClearFlag_MODF ( SPI_TypeDef * SPIx )

Clear mode fault error flag.

Note:
Clearing this flag is done by a read access to the SPIx_SR register followed by a write access to the SPIx_CR1 register
Reference Manual to LL API cross reference:
SR MODF LL_SPI_ClearFlag_MODF
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1049 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_OVR ( SPI_TypeDef * SPIx )

Clear overrun error flag.

Note:
Clearing this flag is done by a read access to the SPIx_DR register followed by a read access to the SPIx_SR register
Reference Manual to LL API cross reference:
SR OVR LL_SPI_ClearFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1066 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_ClearFlag_OVR().

__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel ( SPI_TypeDef * SPIx )

Get FIFO reception Level.

Reference Manual to LL API cross reference:
SR FRLVL LL_SPI_GetRxFIFOLevel
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_RX_FIFO_EMPTY
  • LL_SPI_RX_FIFO_QUARTER_FULL
  • LL_SPI_RX_FIFO_HALF_FULL
  • LL_SPI_RX_FIFO_FULL

Definition at line 1010 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel ( SPI_TypeDef * SPIx )

Get FIFO Transmission Level.

Reference Manual to LL API cross reference:
SR FTLVL LL_SPI_GetTxFIFOLevel
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_TX_FIFO_EMPTY
  • LL_SPI_TX_FIFO_QUARTER_FULL
  • LL_SPI_TX_FIFO_HALF_FULL
  • LL_SPI_TX_FIFO_FULL

Definition at line 1025 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY ( SPI_TypeDef * SPIx )

Get busy flag.

Note:
The BSY flag is cleared under any one of the following conditions: -When the SPI is correctly disabled -When a fault is detected in Master mode (MODF bit set to 1) -In Master mode, when it finishes a data transmission and no new data is ready to be sent -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between each data transfer.
Reference Manual to LL API cross reference:
SR BSY LL_SPI_IsActiveFlag_BSY
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 984 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_BSY().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR ( SPI_TypeDef * SPIx )

Get CRC error flag.

Reference Manual to LL API cross reference:
SR CRCERR LL_SPI_IsActiveFlag_CRCERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 944 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE ( SPI_TypeDef * SPIx )

Get frame format error flag.

Reference Manual to LL API cross reference:
SR FRE LL_SPI_IsActiveFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 995 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_FRE().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF ( SPI_TypeDef * SPIx )

Get mode fault error flag.

Reference Manual to LL API cross reference:
SR MODF LL_SPI_IsActiveFlag_MODF
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 955 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR ( SPI_TypeDef * SPIx )

Get overrun error flag.

Reference Manual to LL API cross reference:
SR OVR LL_SPI_IsActiveFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 966 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_OVR().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE ( SPI_TypeDef * SPIx )

Check if Rx buffer is not empty.

Reference Manual to LL API cross reference:
SR RXNE LL_SPI_IsActiveFlag_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 922 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_RXNE().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE ( SPI_TypeDef * SPIx )

Check if Tx buffer is empty.

Reference Manual to LL API cross reference:
SR TXE LL_SPI_IsActiveFlag_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 933 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_TXE().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Interrupt Management

Functions
Interrupt Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty interrupt.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer not empty interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer empty interrupt.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableIT_ERR ( SPI_TypeDef * SPIx )

Disable error interrupt.

Note:
This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_DisableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1138 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_DisableIT_ERR().

__STATIC_INLINE void LL_SPI_DisableIT_RXNE ( SPI_TypeDef * SPIx )

Disable Rx buffer not empty interrupt.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_DisableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1149 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_DisableIT_RXNE().

__STATIC_INLINE void LL_SPI_DisableIT_TXE ( SPI_TypeDef * SPIx )

Disable Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_DisableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1160 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_DisableIT_TXE().

__STATIC_INLINE void LL_SPI_EnableIT_ERR ( SPI_TypeDef * SPIx )

Enable error interrupt.

Note:
This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_EnableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1104 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_EnableIT_ERR().

__STATIC_INLINE void LL_SPI_EnableIT_RXNE ( SPI_TypeDef * SPIx )

Enable Rx buffer not empty interrupt.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_EnableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1115 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_EnableIT_RXNE().

__STATIC_INLINE void LL_SPI_EnableIT_TXE ( SPI_TypeDef * SPIx )

Enable Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_EnableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1126 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_EnableIT_TXE().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR ( SPI_TypeDef * SPIx )

Check if error interrupt is enabled.

Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_IsEnabledIT_ERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1171 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIT_ERR().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE ( SPI_TypeDef * SPIx )

Check if Rx buffer not empty interrupt is enabled.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1182 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIT_RXNE().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE ( SPI_TypeDef * SPIx )

Check if Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_IsEnabledIT_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1193 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIT_TXE().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Management

Functions
DMA Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE void | LL_SPI_SetDMAParity_RX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA reception.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_RX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA reception.
__STATIC_INLINE void | LL_SPI_SetDMAParity_TX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_TX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_DMA_GetRegAddr (SPI_TypeDef *SPIx)
Get the data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableDMAReq_RX ( SPI_TypeDef * SPIx )

Disable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1223 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_DisableDMAReq_RX().

__STATIC_INLINE void LL_SPI_DisableDMAReq_TX ( SPI_TypeDef * SPIx )

Disable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1256 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_DisableDMAReq_TX().

__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr ( SPI_TypeDef * SPIx )

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
DR DR LL_SPI_DMA_GetRegAddr
Parameters:
SPIx SPI Instance
Return values:
Address of data register

Definition at line 1332 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableDMAReq_RX ( SPI_TypeDef * SPIx )

Enable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1212 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_EnableDMAReq_RX().

__STATIC_INLINE void LL_SPI_EnableDMAReq_TX ( SPI_TypeDef * SPIx )

Enable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1245 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_EnableDMAReq_TX().

__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX ( SPI_TypeDef * SPIx )

Get parity configuration for Last DMA reception.

Reference Manual to LL API cross reference:
CR2 LDMARX LL_SPI_GetDMAParity_RX
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN

Definition at line 1294 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX ( SPI_TypeDef * SPIx )

Get parity configuration for Last DMA transmission.

Reference Manual to LL API cross reference:
CR2 LDMATX LL_SPI_GetDMAParity_TX
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN

Definition at line 1321 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX ( SPI_TypeDef * SPIx )

Check if DMA Rx is enabled.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1234 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledDMAReq_RX().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX ( SPI_TypeDef * SPIx )

Check if DMA Tx is enabled.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1267 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledDMAReq_TX().

__STATIC_INLINE void LL_SPI_SetDMAParity_RX | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Parity
 | ) |  |

Set parity of Last DMA reception.

Reference Manual to LL API cross reference:
CR2 LDMARX LL_SPI_SetDMAParity_RX
Parameters:
SPIx SPI Instance
Parity This parameter can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN
Return values:
None

Definition at line 1281 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetDMAParity_TX | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Parity
 | ) |  |

Set parity of Last DMA transmission.

Reference Manual to LL API cross reference:
CR2 LDMATX LL_SPI_SetDMAParity_TX
Parameters:
SPIx SPI Instance
Parity This parameter can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN
Return values:
None

Definition at line 1308 of file stm32f3xx_ll_spi.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DATA Management

Functions
DATA Management
SPI Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_SPI_ReceiveData8 (SPI_TypeDef *SPIx)
Read 8-Bits in the data register.
__STATIC_INLINE uint16_t | LL_SPI_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData8 (SPI_TypeDef *SPIx, uint8_t TxData)
Write 8-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in the data register.

Function Documentation

__STATIC_INLINE uint16_t LL_SPI_ReceiveData16 ( SPI_TypeDef * SPIx )

Read 16-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_ReceiveData16
Parameters:
SPIx SPI Instance
Return values:
RxData Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 1362 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_ReceiveData16().

__STATIC_INLINE uint8_t LL_SPI_ReceiveData8 ( SPI_TypeDef * SPIx )

Read 8-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_ReceiveData8
Parameters:
SPIx SPI Instance
Return values:
RxData Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 1351 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_TransmitData16 | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | TxData
 | ) |  |

Write 16-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_TransmitData16
Parameters:
SPIx | SPI Instance
TxData | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 1386 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_TransmitData16().

__STATIC_INLINE void LL_SPI_TransmitData8 | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | TxData
 | ) |  |

Write 8-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_TransmitData8
Parameters:
SPIx | SPI Instance
TxData | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1374 of file stm32f3xx_ll_spi.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPI Exported Functions

Functions

ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_SPI_DeInit ( SPI_TypeDef * SPIx )

De-initialize the SPI registers to their default reset values.

Parameters:
SPIx SPI Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are de-initialized
  • ERROR: SPI registers are not de-initialized

Definition at line 150 of file stm32f3xx_ll_spi.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_SPI2, LL_APB1_GRP1_PERIPH_SPI3, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_SPI1, and LL_APB2_GRP1_ReleaseReset().

Referenced by LL_I2S_DeInit().

ErrorStatus LL_SPI_Init | ( | SPI_TypeDef * | SPIx,
 |  | LL_SPI_InitTypeDef * | SPI_InitStruct
 | ) |  |

Initialize the SPI registers according to the specified parameters in SPI_InitStruct.

Note:
As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
SPIx | SPI Instance
SPI_InitStruct | pointer to a LL_SPI_InitTypeDef structure
Return values:
An ErrorStatus enumeration value. (Return always SUCCESS)

Definition at line 217 of file stm32f3xx_ll_spi.c.

References assert_param, LL_SPI_InitTypeDef::BaudRate, LL_SPI_InitTypeDef::BitOrder, LL_SPI_InitTypeDef::ClockPhase, LL_SPI_InitTypeDef::ClockPolarity, LL_SPI_InitTypeDef::CRCCalculation, LL_SPI_InitTypeDef::CRCPoly, LL_SPI_InitTypeDef::DataWidth, IS_LL_SPI_BAUDRATE, IS_LL_SPI_BITORDER, IS_LL_SPI_CRC_POLYNOMIAL, IS_LL_SPI_CRCCALCULATION, IS_LL_SPI_DATAWIDTH, IS_LL_SPI_MODE, IS_LL_SPI_NSS, IS_LL_SPI_PHASE, IS_LL_SPI_POLARITY, IS_LL_SPI_TRANSFER_DIRECTION, LL_SPI_CRCCALCULATION_ENABLE, LL_SPI_IsEnabled(), LL_SPI_SetCRCPolynomial(), LL_SPI_InitTypeDef::Mode, LL_SPI_InitTypeDef::NSS, SPI_CR1_CLEAR_MASK, and LL_SPI_InitTypeDef::TransferDirection.

void LL_SPI_StructInit ( LL_SPI_InitTypeDef * SPI_InitStruct )

Set each LL_SPI_InitTypeDef field to default value.

Parameters:
SPI_InitStruct pointer to a LL_SPI_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 289 of file stm32f3xx_ll_spi.c.

References LL_SPI_InitTypeDef::BaudRate, LL_SPI_InitTypeDef::BitOrder, LL_SPI_InitTypeDef::ClockPhase, LL_SPI_InitTypeDef::ClockPolarity, LL_SPI_InitTypeDef::CRCCalculation, LL_SPI_InitTypeDef::CRCPoly, LL_SPI_InitTypeDef::DataWidth, LL_SPI_BAUDRATEPRESCALER_DIV2, LL_SPI_CRCCALCULATION_DISABLE, LL_SPI_DATAWIDTH_8BIT, LL_SPI_FULL_DUPLEX, LL_SPI_MODE_SLAVE, LL_SPI_MSB_FIRST, LL_SPI_NSS_HARD_INPUT, LL_SPI_PHASE_1EDGE, LL_SPI_POLARITY_LOW, LL_SPI_InitTypeDef::Mode, LL_SPI_InitTypeDef::NSS, and LL_SPI_InitTypeDef::TransferDirection.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S

Modules
I2S
STM32F3xx_LL_Driver

Modules

I2S Private Constants
I2S Private Macros
I2S Exported Init structure
I2S Exported Constants
I2S Exported Macros
I2S Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for I2S registers.

Register | Bit | Function
CR2 | ERRIE | LL_I2S_DisableIT_ERR
 |  | LL_I2S_EnableIT_ERR
 |  | LL_I2S_IsEnabledIT_ERR
 | RXDMAEN | LL_I2S_DisableDMAReq_RX
 |  | LL_I2S_EnableDMAReq_RX
 |  | LL_I2S_IsEnabledDMAReq_RX
 | RXNEIE | LL_I2S_DisableIT_RXNE
 |  | LL_I2S_EnableIT_RXNE
 |  | LL_I2S_IsEnabledIT_RXNE
 | TXDMAEN | LL_I2S_DisableDMAReq_TX
 |  | LL_I2S_EnableDMAReq_TX
 |  | LL_I2S_IsEnabledDMAReq_TX
 | TXEIE | LL_I2S_DisableIT_TXE
 |  | LL_I2S_EnableIT_TXE
 |  | LL_I2S_IsEnabledIT_TXE
DR | DR | LL_I2S_ReceiveData16
 |  | LL_I2S_TransmitData16
I2SCFGR | CHLEN | LL_I2S_GetDataFormat
 |  | LL_I2S_SetDataFormat
 | CKPOL | LL_I2S_GetClockPolarity
 |  | LL_I2S_SetClockPolarity
 | DATLEN | LL_I2S_GetDataFormat
 |  | LL_I2S_SetDataFormat
 | I2SCFG | LL_I2S_GetTransferMode
 |  | LL_I2S_SetTransferMode
 | I2SE | LL_I2S_Disable
 |  | LL_I2S_Enable
 |  | LL_I2S_IsEnabled
 | I2SMOD | LL_I2S_Enable
 | I2SSTD | LL_I2S_GetStandard
 |  | LL_I2S_SetStandard
 | PCMSYNC | LL_I2S_GetStandard
 |  | LL_I2S_SetStandard
I2SPR | I2SDIV | LL_I2S_GetPrescalerLinear
 |  | LL_I2S_SetPrescalerLinear
 | MCKOE | LL_I2S_DisableMasterClock
 |  | LL_I2S_EnableMasterClock
 |  | LL_I2S_IsEnabledMasterClock
 | ODD | LL_I2S_GetPrescalerParity
 |  | LL_I2S_SetPrescalerParity
SR | BSY | LL_I2S_IsActiveFlag_BSY
 | CHSIDE | LL_I2S_IsActiveFlag_CHSIDE
 | FRE | LL_I2S_ClearFlag_FRE
 |  | LL_I2S_IsActiveFlag_FRE
 | OVR | LL_I2S_ClearFlag_OVR
 |  | LL_I2S_IsActiveFlag_OVR
 | RXNE | LL_I2S_IsActiveFlag_RXNE
 | TXE | LL_I2S_IsActiveFlag_TXE
 | UDR | LL_I2S_ClearFlag_UDR
 |  | LL_I2S_IsActiveFlag_UDR
Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Private Constants

Defines
I2S Private Constants
I2S

Defines

#define | I2S_I2SCFGR_CLEAR_MASK
#define | I2S_I2SPR_CLEAR_MASK 0x0002U

Define Documentation

#define I2S_I2SCFGR_CLEAR_MASK
Value:
(SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
                                            SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
                                            SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )

Definition at line 328 of file stm32f3xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define I2S_I2SPR_CLEAR_MASK 0x0002U

Definition at line 332 of file stm32f3xx_ll_spi.c.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Private Macros

Defines
I2S Private Macros
I2S

Defines

#define | IS_LL_I2S_DATAFORMAT(__VALUE__)
#define | IS_LL_I2S_CPOL(__VALUE__)
#define | IS_LL_I2S_STANDARD(__VALUE__)
#define | IS_LL_I2S_MODE(__VALUE__)
#define | IS_LL_I2S_MCLK_OUTPUT(__VALUE__)
#define | IS_LL_I2S_AUDIO_FREQ(__VALUE__)
#define | IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
#define | IS_LL_I2S_PRESCALER_PARITY(__VALUE__)

Define Documentation

#define IS_LL_I2S_AUDIO_FREQ ( __VALUE__ )
Value:
((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)    \
                                       && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
                                       || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))

Definition at line 363 of file stm32f3xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_CPOL ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_POLARITY_LOW)  \
                                       || ((__VALUE__) == LL_I2S_POLARITY_HIGH))

Definition at line 346 of file stm32f3xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_DATAFORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_DATAFORMAT_16B)          \
                                       || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
                                       || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
                                       || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))

Definition at line 341 of file stm32f3xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_MCLK_OUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
                                       || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))

Definition at line 360 of file stm32f3xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_MODE_SLAVE_TX)  \
                                       || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
                                       || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
                                       || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))

Definition at line 355 of file stm32f3xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_PRESCALER_LINEAR ( __VALUE__ ) ((__VALUE__) >= 0x2U)

Definition at line 367 of file stm32f3xx_ll_spi.c.

Referenced by LL_I2S_ConfigPrescaler().

#define IS_LL_I2S_PRESCALER_PARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
                                           || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))

Definition at line 369 of file stm32f3xx_ll_spi.c.

Referenced by LL_I2S_ConfigPrescaler().

#define IS_LL_I2S_STANDARD ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_STANDARD_PHILIPS)   \
                                       || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
                                       || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
                                       || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
                                       || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))

Definition at line 349 of file stm32f3xx_ll_spi.c.

Referenced by LL_I2S_Init().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_I2S_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_I2S_InitTypeDef Struct Reference
I2S Exported Init structure

I2S Init structure definition. More...

#include <stm32f3xx_ll_spi.h>

Data Fields

uint32_t | Mode
uint32_t | Standard
uint32_t | DataFormat
uint32_t | MCLKOutput
uint32_t | AudioFreq
uint32_t | ClockPolarity

Detailed Description

I2S Init structure definition.

Definition at line 1434 of file stm32f3xx_ll_spi.h.

Field Documentation

uint32_t LL_I2S_InitTypeDef::AudioFreq

Specifies the frequency selected for the I2S communication. This parameter can be a value of Audio Frequency

Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity and unitary functions LL_I2S_SetPrescalerLinear() and LL_I2S_SetPrescalerParity() to set it.

Definition at line 1459 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::ClockPolarity

Specifies the idle state of the I2S clock. This parameter can be a value of Clock Polarity

This feature can be modified afterwards using unitary function LL_I2S_SetClockPolarity().

Definition at line 1466 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::DataFormat

Specifies the data format for the I2S communication. This parameter can be a value of Data format

This feature can be modified afterwards using unitary function LL_I2S_SetDataFormat().

Definition at line 1447 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::MCLKOutput

Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of MCLK Output

This feature can be modified afterwards using unitary functions LL_I2S_EnableMasterClock() or LL_I2S_DisableMasterClock.

Definition at line 1453 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::Mode

Specifies the I2S operating mode. This parameter can be a value of Operation Mode

This feature can be modified afterwards using unitary function LL_I2S_SetTransferMode().

Definition at line 1436 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::Standard

Specifies the standard used for the I2S communication. This parameter can be a value of I2s Standard

This feature can be modified afterwards using unitary function LL_I2S_SetStandard().

Definition at line 1441 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_spi.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
I2S Exported Constants

Flags defines which can be used with LL_I2S_ReadReg function. More...

Defines

#define | LL_I2S_SR_RXNE LL_SPI_SR_RXNE
#define | LL_I2S_SR_TXE LL_SPI_SR_TXE
#define | LL_I2S_SR_BSY LL_SPI_SR_BSY
#define | LL_I2S_SR_UDR SPI_SR_UDR
#define | LL_I2S_SR_OVR LL_SPI_SR_OVR
#define | LL_I2S_SR_FRE LL_SPI_SR_FRE

Detailed Description

Flags defines which can be used with LL_I2S_ReadReg function.

Define Documentation

#define LL_I2S_SR_BSY LL_SPI_SR_BSY

Busy flag

Definition at line 1489 of file stm32f3xx_ll_spi.h.

#define LL_I2S_SR_FRE LL_SPI_SR_FRE

TI mode frame format error flag

Definition at line 1492 of file stm32f3xx_ll_spi.h.

#define LL_I2S_SR_OVR LL_SPI_SR_OVR

Overrun flag

Definition at line 1491 of file stm32f3xx_ll_spi.h.

#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE

Rx buffer not empty flag

Definition at line 1487 of file stm32f3xx_ll_spi.h.

#define LL_I2S_SR_TXE LL_SPI_SR_TXE

Tx buffer empty flag

Definition at line 1488 of file stm32f3xx_ll_spi.h.

#define LL_I2S_SR_UDR SPI_SR_UDR

Underrun flag

Definition at line 1490 of file stm32f3xx_ll_spi.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data format

Defines
Data format
I2S Exported Constants

Defines

#define | LL_I2S_DATAFORMAT_16B 0x00000000U
#define | LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define | LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
#define | LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)

Define Documentation

#define LL_I2S_DATAFORMAT_16B 0x00000000U

Data length 16 bits, Channel lenght 16bit

Definition at line 1511 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)

Data length 16 bits, Channel lenght 32bit

Definition at line 1512 of file stm32f3xx_ll_spi.h.

#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)

Data length 24 bits, Channel lenght 32bit

Definition at line 1513 of file stm32f3xx_ll_spi.h.

#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)

Data length 16 bits, Channel lenght 32bit

Definition at line 1514 of file stm32f3xx_ll_spi.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Clock Polarity

Defines
Clock Polarity
I2S Exported Constants

Defines

#define | LL_I2S_POLARITY_LOW 0x00000000U
#define | LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)

Define Documentation

#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)

Clock steady state is high level

Definition at line 1523 of file stm32f3xx_ll_spi.h.

#define LL_I2S_POLARITY_LOW 0x00000000U

Clock steady state is low level

Definition at line 1522 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_StructInit().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2s Standard

Defines
I2s Standard
I2S Exported Constants

Defines

#define | LL_I2S_STANDARD_PHILIPS 0x00000000U
#define | LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define | LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)

Define Documentation

#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)

LSB justified standard (right justified)

Definition at line 1533 of file stm32f3xx_ll_spi.h.

#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)

MSB justified standard (left justified)

Definition at line 1532 of file stm32f3xx_ll_spi.h.

#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)

PCM standard, long frame synchronization

Definition at line 1535 of file stm32f3xx_ll_spi.h.

#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)

PCM standard, short frame synchronization

Definition at line 1534 of file stm32f3xx_ll_spi.h.

#define LL_I2S_STANDARD_PHILIPS 0x00000000U

I2S standard philips

Definition at line 1531 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_StructInit().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Operation Mode

Defines
Operation Mode
I2S Exported Constants

Defines

#define | LL_I2S_MODE_SLAVE_TX 0x00000000U
#define | LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define | LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define | LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)

Define Documentation

#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)

Master Rx configuration

Definition at line 1546 of file stm32f3xx_ll_spi.h.

#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)

Master Tx configuration

Definition at line 1545 of file stm32f3xx_ll_spi.h.

#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)

Slave Rx configuration

Definition at line 1544 of file stm32f3xx_ll_spi.h.

#define LL_I2S_MODE_SLAVE_TX 0x00000000U

Slave Tx configuration

Definition at line 1543 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_StructInit().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Prescaler Factor

Defines
Prescaler Factor
I2S Exported Constants

Defines

#define | LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U
#define | LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U)

Define Documentation

#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U

Odd factor: Real divider value is = I2SDIV * 2

Definition at line 1554 of file stm32f3xx_ll_spi.h.

#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U)

Odd factor: Real divider value is = (I2SDIV * 2)+1

Definition at line 1555 of file stm32f3xx_ll_spi.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: MCLK Output

Defines
MCLK Output
I2S Exported Constants

Defines

#define | LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U
#define | LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE)

Define Documentation

#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U

Master clock output is disabled

Definition at line 1565 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_StructInit().

#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE)

Master clock output is enabled

Definition at line 1566 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_Init().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Audio Frequency

Defines
Audio Frequency
I2S Exported Constants

Defines

#define | LL_I2S_AUDIOFREQ_192K 192000U
#define | LL_I2S_AUDIOFREQ_96K 96000U
#define | LL_I2S_AUDIOFREQ_48K 48000U
#define | LL_I2S_AUDIOFREQ_44K 44100U
#define | LL_I2S_AUDIOFREQ_32K 32000U
#define | LL_I2S_AUDIOFREQ_22K 22050U
#define | LL_I2S_AUDIOFREQ_16K 16000U
#define | LL_I2S_AUDIOFREQ_11K 11025U
#define | LL_I2S_AUDIOFREQ_8K 8000U
#define | LL_I2S_AUDIOFREQ_DEFAULT 2U

Define Documentation

#define LL_I2S_AUDIOFREQ_11K 11025U

Audio Frequency configuration 11025 Hz

Definition at line 1582 of file stm32f3xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_16K 16000U

Audio Frequency configuration 16000 Hz

Definition at line 1581 of file stm32f3xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_192K 192000U

Audio Frequency configuration 192000 Hz

Definition at line 1575 of file stm32f3xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_22K 22050U

Audio Frequency configuration 22050 Hz

Definition at line 1580 of file stm32f3xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_32K 32000U

Audio Frequency configuration 32000 Hz

Definition at line 1579 of file stm32f3xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_44K 44100U

Audio Frequency configuration 44100 Hz

Definition at line 1578 of file stm32f3xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_48K 48000U

Audio Frequency configuration 48000 Hz

Definition at line 1577 of file stm32f3xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_8K 8000U

Audio Frequency configuration 8000 Hz

Definition at line 1583 of file stm32f3xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_96K 96000U

Audio Frequency configuration 96000 Hz

Definition at line 1576 of file stm32f3xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_DEFAULT 2U

Audio Freq not specified. Register I2SDIV = 2

Definition at line 1584 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
I2S Exported Macros

Defines

#define | LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2S register.
#define | LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2S register.

Define Documentation

#define LL_I2S_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in I2S register.

Parameters:
__INSTANCE__ | I2S Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 1618 of file stm32f3xx_ll_spi.h.

#define LL_I2S_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in I2S register.

Parameters:
__INSTANCE__ | I2S Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 1610 of file stm32f3xx_ll_spi.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration

Functions
Configuration
I2S Exported Functions

Functions

__STATIC_INLINE void | LL_I2S_Enable (SPI_TypeDef *SPIx)
Select I2S mode and Enable I2S peripheral.
__STATIC_INLINE void | LL_I2S_Disable (SPI_TypeDef *SPIx)
Disable I2S peripheral.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabled (SPI_TypeDef *SPIx)
Check if I2S peripheral is enabled.
__STATIC_INLINE void | LL_I2S_SetDataFormat (SPI_TypeDef *SPIx, uint32_t DataFormat)
Set I2S data frame length.
__STATIC_INLINE uint32_t | LL_I2S_GetDataFormat (SPI_TypeDef *SPIx)
Get I2S data frame length.
__STATIC_INLINE void | LL_I2S_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set I2S clock polarity.
__STATIC_INLINE uint32_t | LL_I2S_GetClockPolarity (SPI_TypeDef *SPIx)
Get I2S clock polarity.
__STATIC_INLINE void | LL_I2S_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set I2S standard protocol.
__STATIC_INLINE uint32_t | LL_I2S_GetStandard (SPI_TypeDef *SPIx)
Get I2S standard protocol.
__STATIC_INLINE void | LL_I2S_SetTransferMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set I2S transfer mode.
__STATIC_INLINE uint32_t | LL_I2S_GetTransferMode (SPI_TypeDef *SPIx)
Get I2S transfer mode.
__STATIC_INLINE void | LL_I2S_SetPrescalerLinear (SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
Set I2S linear prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerLinear (SPI_TypeDef *SPIx)
Get I2S linear prescaler.
__STATIC_INLINE void | LL_I2S_SetPrescalerParity (SPI_TypeDef *SPIx, uint32_t PrescalerParity)
Set I2S parity prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerParity (SPI_TypeDef *SPIx)
Get I2S parity prescaler.
__STATIC_INLINE void | LL_I2S_EnableMasterClock (SPI_TypeDef *SPIx)
Enable the master clock ouput (Pin MCK)
__STATIC_INLINE void | LL_I2S_DisableMasterClock (SPI_TypeDef *SPIx)
Disable the master clock ouput (Pin MCK)
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledMasterClock (SPI_TypeDef *SPIx)
Check if the master clock ouput (Pin MCK) is enabled.

Function Documentation

__STATIC_INLINE void LL_I2S_Disable ( SPI_TypeDef * SPIx )

Disable I2S peripheral.

Reference Manual to LL API cross reference:
I2SCFGR I2SE LL_I2S_Disable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1656 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_DisableMasterClock ( SPI_TypeDef * SPIx )

Disable the master clock ouput (Pin MCK)

Reference Manual to LL API cross reference:
I2SPR MCKOE LL_I2S_DisableMasterClock
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1865 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_Enable ( SPI_TypeDef * SPIx )

Select I2S mode and Enable I2S peripheral.

Reference Manual to LL API cross reference:
I2SCFGR I2SMOD LL_I2S_Enable
I2SCFGR I2SE LL_I2S_Enable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1645 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_EnableMasterClock ( SPI_TypeDef * SPIx )

Enable the master clock ouput (Pin MCK)

Reference Manual to LL API cross reference:
I2SPR MCKOE LL_I2S_EnableMasterClock
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1854 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity ( SPI_TypeDef * SPIx )

Get I2S clock polarity.

Reference Manual to LL API cross reference:
I2SCFGR CKPOL LL_I2S_GetClockPolarity
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_POLARITY_LOW
  • LL_I2S_POLARITY_HIGH

Definition at line 1727 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetDataFormat ( SPI_TypeDef * SPIx )

Get I2S data frame length.

Reference Manual to LL API cross reference:
I2SCFGR DATLEN LL_I2S_GetDataFormat
I2SCFGR CHLEN LL_I2S_GetDataFormat
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_DATAFORMAT_16B
  • LL_I2S_DATAFORMAT_16B_EXTENDED
  • LL_I2S_DATAFORMAT_24B
  • LL_I2S_DATAFORMAT_32B

Definition at line 1700 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear ( SPI_TypeDef * SPIx )

Get I2S linear prescaler.

Reference Manual to LL API cross reference:
I2SPR I2SDIV LL_I2S_GetPrescalerLinear
Parameters:
SPIx SPI Instance
Return values:
PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF

Definition at line 1816 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity ( SPI_TypeDef * SPIx )

Get I2S parity prescaler.

Reference Manual to LL API cross reference:
I2SPR ODD LL_I2S_GetPrescalerParity
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_PRESCALER_PARITY_EVEN
  • LL_I2S_PRESCALER_PARITY_ODD

Definition at line 1843 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetStandard ( SPI_TypeDef * SPIx )

Get I2S standard protocol.

Reference Manual to LL API cross reference:
I2SCFGR I2SSTD LL_I2S_GetStandard
I2SCFGR PCMSYNC LL_I2S_GetStandard
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_STANDARD_PHILIPS
  • LL_I2S_STANDARD_MSB
  • LL_I2S_STANDARD_LSB
  • LL_I2S_STANDARD_PCM_SHORT
  • LL_I2S_STANDARD_PCM_LONG

Definition at line 1762 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetTransferMode ( SPI_TypeDef * SPIx )

Get I2S transfer mode.

Reference Manual to LL API cross reference:
I2SCFGR I2SCFG LL_I2S_GetTransferMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_MODE_SLAVE_TX
  • LL_I2S_MODE_SLAVE_RX
  • LL_I2S_MODE_MASTER_TX
  • LL_I2S_MODE_MASTER_RX

Definition at line 1793 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_IsEnabled ( SPI_TypeDef * SPIx )

Check if I2S peripheral is enabled.

Reference Manual to LL API cross reference:
I2SCFGR I2SE LL_I2S_IsEnabled
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1667 of file stm32f3xx_ll_spi.h.

Referenced by LL_I2S_Init().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock ( SPI_TypeDef * SPIx )

Check if the master clock ouput (Pin MCK) is enabled.

Reference Manual to LL API cross reference:
I2SPR MCKOE LL_I2S_IsEnabledMasterClock
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1876 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetClockPolarity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Set I2S clock polarity.

Reference Manual to LL API cross reference:
I2SCFGR CKPOL LL_I2S_SetClockPolarity
Parameters:
SPIx SPI Instance
ClockPolarity This parameter can be one of the following values:
  • LL_I2S_POLARITY_LOW
  • LL_I2S_POLARITY_HIGH
Return values:
None

Definition at line 1714 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetDataFormat | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | DataFormat
 | ) |  |

Set I2S data frame length.

Reference Manual to LL API cross reference:
I2SCFGR DATLEN LL_I2S_SetDataFormat
I2SCFGR CHLEN LL_I2S_SetDataFormat
Parameters:
SPIx SPI Instance
DataFormat This parameter can be one of the following values:
  • LL_I2S_DATAFORMAT_16B
  • LL_I2S_DATAFORMAT_16B_EXTENDED
  • LL_I2S_DATAFORMAT_24B
  • LL_I2S_DATAFORMAT_32B
Return values:
None

Definition at line 1684 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetPrescalerLinear | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | PrescalerLinear
 | ) |  |

Set I2S linear prescaler.

Reference Manual to LL API cross reference:
I2SPR I2SDIV LL_I2S_SetPrescalerLinear
Parameters:
SPIx | SPI Instance
PrescalerLinear | Value between Min_Data=0x02 and Max_Data=0xFF
Return values:
None

Definition at line 1805 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetPrescalerParity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | PrescalerParity
 | ) |  |

Set I2S parity prescaler.

Reference Manual to LL API cross reference:
I2SPR ODD LL_I2S_SetPrescalerParity
Parameters:
SPIx SPI Instance
PrescalerParity This parameter can be one of the following values:
  • LL_I2S_PRESCALER_PARITY_EVEN
  • LL_I2S_PRESCALER_PARITY_ODD
Return values:
None

Definition at line 1830 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetStandard | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Standard
 | ) |  |

Set I2S standard protocol.

Reference Manual to LL API cross reference:
I2SCFGR I2SSTD LL_I2S_SetStandard
I2SCFGR PCMSYNC LL_I2S_SetStandard
Parameters:
SPIx SPI Instance
Standard This parameter can be one of the following values:
  • LL_I2S_STANDARD_PHILIPS
  • LL_I2S_STANDARD_MSB
  • LL_I2S_STANDARD_LSB
  • LL_I2S_STANDARD_PCM_SHORT
  • LL_I2S_STANDARD_PCM_LONG
Return values:
None

Definition at line 1745 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetTransferMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Mode
 | ) |  |

Set I2S transfer mode.

Reference Manual to LL API cross reference:
I2SCFGR I2SCFG LL_I2S_SetTransferMode
Parameters:
SPIx SPI Instance
Mode This parameter can be one of the following values:
  • LL_I2S_MODE_SLAVE_TX
  • LL_I2S_MODE_SLAVE_RX
  • LL_I2S_MODE_MASTER_TX
  • LL_I2S_MODE_MASTER_RX
Return values:
None

Definition at line 1778 of file stm32f3xx_ll_spi.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLAG Management

Functions
FLAG Management
I2S Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_UDR (SPI_TypeDef *SPIx)
Get underrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_CHSIDE (SPI_TypeDef *SPIx)
Get channel side flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_UDR (SPI_TypeDef *SPIx)
Clear underrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.

Function Documentation

__STATIC_INLINE void LL_I2S_ClearFlag_FRE ( SPI_TypeDef * SPIx )

Clear frame format error flag.

Reference Manual to LL API cross reference:
SR FRE LL_I2S_ClearFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1999 of file stm32f3xx_ll_spi.h.

References LL_SPI_ClearFlag_FRE().

__STATIC_INLINE void LL_I2S_ClearFlag_OVR ( SPI_TypeDef * SPIx )

Clear overrun error flag.

Reference Manual to LL API cross reference:
SR OVR LL_I2S_ClearFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1975 of file stm32f3xx_ll_spi.h.

References LL_SPI_ClearFlag_OVR().

__STATIC_INLINE void LL_I2S_ClearFlag_UDR ( SPI_TypeDef * SPIx )

Clear underrun error flag.

Reference Manual to LL API cross reference:
SR UDR LL_I2S_ClearFlag_UDR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1986 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY ( SPI_TypeDef * SPIx )

Get busy flag.

Reference Manual to LL API cross reference:
SR BSY LL_I2S_IsActiveFlag_BSY
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1917 of file stm32f3xx_ll_spi.h.

References LL_SPI_IsActiveFlag_BSY().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE ( SPI_TypeDef * SPIx )

Get channel side flag.

Note:
0: Channel Left has to be transmitted or has been received
1: Channel Right has to be transmitted or has been received
It has no significance in PCM mode.
Reference Manual to LL API cross reference:
SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1964 of file stm32f3xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE ( SPI_TypeDef * SPIx )

Get frame format error flag.

Reference Manual to LL API cross reference:
SR FRE LL_I2S_IsActiveFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1950 of file stm32f3xx_ll_spi.h.

References LL_SPI_IsActiveFlag_FRE().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR ( SPI_TypeDef * SPIx )

Get overrun error flag.

Reference Manual to LL API cross reference:
SR OVR LL_I2S_IsActiveFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1928 of file stm32f3xx_ll_spi.h.

References LL_SPI_IsActiveFlag_OVR().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE ( SPI_TypeDef * SPIx )

Check if Rx buffer is not empty.

Reference Manual to LL API cross reference:
SR RXNE LL_I2S_IsActiveFlag_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1895 of file stm32f3xx_ll_spi.h.

References LL_SPI_IsActiveFlag_RXNE().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE ( SPI_TypeDef * SPIx )

Check if Tx buffer is empty.

Reference Manual to LL API cross reference:
SR TXE LL_I2S_IsActiveFlag_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1906 of file stm32f3xx_ll_spi.h.

References LL_SPI_IsActiveFlag_TXE().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR ( SPI_TypeDef * SPIx )

Get underrun error flag.

Reference Manual to LL API cross reference:
SR UDR LL_I2S_IsActiveFlag_UDR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1939 of file stm32f3xx_ll_spi.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Interrupt Management

Functions
Interrupt Management
I2S Exported Functions

Functions

__STATIC_INLINE void | LL_I2S_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error IT.
__STATIC_INLINE void | LL_I2S_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty IT.
__STATIC_INLINE void | LL_I2S_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty IT.
__STATIC_INLINE void | LL_I2S_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error IT.
__STATIC_INLINE void | LL_I2S_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty IT.
__STATIC_INLINE void | LL_I2S_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty IT.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if ERR IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if RXNE IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if TXE IT is enabled.

Function Documentation

__STATIC_INLINE void LL_I2S_DisableIT_ERR ( SPI_TypeDef * SPIx )

Disable error IT.

Note:
This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_I2S_DisableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2053 of file stm32f3xx_ll_spi.h.

References LL_SPI_DisableIT_ERR().

__STATIC_INLINE void LL_I2S_DisableIT_RXNE ( SPI_TypeDef * SPIx )

Disable Rx buffer not empty IT.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_I2S_DisableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2064 of file stm32f3xx_ll_spi.h.

References LL_SPI_DisableIT_RXNE().

__STATIC_INLINE void LL_I2S_DisableIT_TXE ( SPI_TypeDef * SPIx )

Disable Tx buffer empty IT.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_I2S_DisableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2075 of file stm32f3xx_ll_spi.h.

References LL_SPI_DisableIT_TXE().

__STATIC_INLINE void LL_I2S_EnableIT_ERR ( SPI_TypeDef * SPIx )

Enable error IT.

Note:
This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_I2S_EnableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2019 of file stm32f3xx_ll_spi.h.

References LL_SPI_EnableIT_ERR().

__STATIC_INLINE void LL_I2S_EnableIT_RXNE ( SPI_TypeDef * SPIx )

Enable Rx buffer not empty IT.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_I2S_EnableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2030 of file stm32f3xx_ll_spi.h.

References LL_SPI_EnableIT_RXNE().

__STATIC_INLINE void LL_I2S_EnableIT_TXE ( SPI_TypeDef * SPIx )

Enable Tx buffer empty IT.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_I2S_EnableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2041 of file stm32f3xx_ll_spi.h.

References LL_SPI_EnableIT_TXE().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR ( SPI_TypeDef * SPIx )

Check if ERR IT is enabled.

Reference Manual to LL API cross reference:
CR2 ERRIE LL_I2S_IsEnabledIT_ERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 2086 of file stm32f3xx_ll_spi.h.

References LL_SPI_IsEnabledIT_ERR().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE ( SPI_TypeDef * SPIx )

Check if RXNE IT is enabled.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 2097 of file stm32f3xx_ll_spi.h.

References LL_SPI_IsEnabledIT_RXNE().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE ( SPI_TypeDef * SPIx )

Check if TXE IT is enabled.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_I2S_IsEnabledIT_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 2108 of file stm32f3xx_ll_spi.h.

References LL_SPI_IsEnabledIT_TXE().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Management

Functions
DMA Management
I2S Exported Functions

Functions

__STATIC_INLINE void | LL_I2S_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_I2S_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.

Function Documentation

__STATIC_INLINE void LL_I2S_DisableDMAReq_RX ( SPI_TypeDef * SPIx )

Disable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2138 of file stm32f3xx_ll_spi.h.

References LL_SPI_DisableDMAReq_RX().

__STATIC_INLINE void LL_I2S_DisableDMAReq_TX ( SPI_TypeDef * SPIx )

Disable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2171 of file stm32f3xx_ll_spi.h.

References LL_SPI_DisableDMAReq_TX().

__STATIC_INLINE void LL_I2S_EnableDMAReq_RX ( SPI_TypeDef * SPIx )

Enable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2127 of file stm32f3xx_ll_spi.h.

References LL_SPI_EnableDMAReq_RX().

__STATIC_INLINE void LL_I2S_EnableDMAReq_TX ( SPI_TypeDef * SPIx )

Enable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2160 of file stm32f3xx_ll_spi.h.

References LL_SPI_EnableDMAReq_TX().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX ( SPI_TypeDef * SPIx )

Check if DMA Rx is enabled.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 2149 of file stm32f3xx_ll_spi.h.

References LL_SPI_IsEnabledDMAReq_RX().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX ( SPI_TypeDef * SPIx )

Check if DMA Tx is enabled.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 2182 of file stm32f3xx_ll_spi.h.

References LL_SPI_IsEnabledDMAReq_TX().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DATA Management

Functions
DATA Management
I2S Exported Functions

Functions

__STATIC_INLINE uint16_t | LL_I2S_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in data register.
__STATIC_INLINE void | LL_I2S_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in data register.

Function Documentation

__STATIC_INLINE uint16_t LL_I2S_ReceiveData16 ( SPI_TypeDef * SPIx )

Read 16-Bits in data register.

Reference Manual to LL API cross reference:
DR DR LL_I2S_ReceiveData16
Parameters:
SPIx SPI Instance
Return values:
RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF

Definition at line 2201 of file stm32f3xx_ll_spi.h.

References LL_SPI_ReceiveData16().

__STATIC_INLINE void LL_I2S_TransmitData16 | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | TxData
 | ) |  |

Write 16-Bits in data register.

Reference Manual to LL API cross reference:
DR DR LL_I2S_TransmitData16
Parameters:
SPIx | SPI Instance
TxData | Value between Min_Data=0x0000 and Max_Data=0xFFFF
Return values:
None

Definition at line 2213 of file stm32f3xx_ll_spi.h.

References LL_SPI_TransmitData16().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2S Exported Functions

Functions

ErrorStatus | LL_I2S_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI/I2S registers to their default reset values.
ErrorStatus | LL_I2S_Init (SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
void | LL_I2S_StructInit (LL_I2S_InitTypeDef *I2S_InitStruct)
Set each LL_I2S_InitTypeDef field to default value.
void | LL_I2S_ConfigPrescaler (SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
Set linear and parity prescaler.

Function Documentation

void LL_I2S_ConfigPrescaler | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | PrescalerLinear,
 |  | uint32_t | PrescalerParity
 | ) |  |

Set linear and parity prescaler.

Note:
To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)
Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
Parameters:
SPIx | SPI Instance
PrescalerLinear | value: Min_Data=0x02 and Max_Data=0xFF.
PrescalerParity This parameter can be one of the following values:
  • LL_I2S_PRESCALER_PARITY_EVEN
  • LL_I2S_PRESCALER_PARITY_ODD
Return values:
None

Definition at line 537 of file stm32f3xx_ll_spi.c.

References assert_param, IS_LL_I2S_PRESCALER_LINEAR, and IS_LL_I2S_PRESCALER_PARITY.

ErrorStatus LL_I2S_DeInit ( SPI_TypeDef * SPIx )

De-initialize the SPI/I2S registers to their default reset values.

Parameters:
SPIx SPI Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are de-initialized
  • ERROR: SPI registers are not de-initialized

Definition at line 393 of file stm32f3xx_ll_spi.c.

References LL_SPI_DeInit().

ErrorStatus LL_I2S_Init | ( | SPI_TypeDef * | SPIx,
 |  | LL_I2S_InitTypeDef * | I2S_InitStruct
 | ) |  |

Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.

Note:
As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
SPIx | SPI Instance
I2S_InitStruct | pointer to a LL_I2S_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are Initialized
  • ERROR: SPI registers are not Initialized

Definition at line 408 of file stm32f3xx_ll_spi.c.

References assert_param, LL_I2S_InitTypeDef::AudioFreq, LL_I2S_InitTypeDef::ClockPolarity, LL_I2S_InitTypeDef::DataFormat, I2S_I2SCFGR_CLEAR_MASK, IS_LL_I2S_AUDIO_FREQ, IS_LL_I2S_CPOL, IS_LL_I2S_DATAFORMAT, IS_LL_I2S_MCLK_OUTPUT, IS_LL_I2S_MODE, IS_LL_I2S_STANDARD, LL_I2S_AUDIOFREQ_DEFAULT, LL_I2S_DATAFORMAT_16B, LL_I2S_IsEnabled(), LL_I2S_MCLK_OUTPUT_ENABLE, LL_RCC_GetSystemClocksFreq(), LL_I2S_InitTypeDef::MCLKOutput, LL_I2S_InitTypeDef::Mode, LL_I2S_InitTypeDef::Standard, and LL_RCC_ClocksTypeDef::SYSCLK_Frequency.

void LL_I2S_StructInit ( LL_I2S_InitTypeDef * I2S_InitStruct )

Set each LL_I2S_InitTypeDef field to default value.

Parameters:
I2S_InitStruct pointer to a LL_I2S_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 515 of file stm32f3xx_ll_spi.c.

References LL_I2S_InitTypeDef::AudioFreq, LL_I2S_InitTypeDef::ClockPolarity, LL_I2S_InitTypeDef::DataFormat, LL_I2S_AUDIOFREQ_DEFAULT, LL_I2S_DATAFORMAT_16B, LL_I2S_MCLK_OUTPUT_DISABLE, LL_I2S_MODE_SLAVE_TX, LL_I2S_POLARITY_LOW, LL_I2S_STANDARD_PHILIPS, LL_I2S_InitTypeDef::MCLKOutput, LL_I2S_InitTypeDef::Mode, and LL_I2S_InitTypeDef::Standard.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SYSTEM

Modules
SYSTEM
STM32F3xx_LL_Driver

Modules

SYSTEM Private Constants
SYSTEM Exported Constants
SYSTEM Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for SYSTEM registers.

Register | Bit | Function
APB1_FZ | DBG_CAN_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_I2C1_SMBUS_TIMEOUT | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_I2C2_SMBUS_TIMEOUT | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_I2C3_SMBUS_TIMEOUT | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_IWDG_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_RTC_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM12_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM13_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM14_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM18_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM2_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM3_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM4_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM5_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM6_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM7_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_WWDG_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
APB2_FZ | DBG_HRTIM1_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB2_GRP1_UnFreezePeriph
 | DBG_TIM15_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB2_GRP1_UnFreezePeriph
 | DBG_TIM16_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB2_GRP1_UnFreezePeriph
 | DBG_TIM17_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB2_GRP1_UnFreezePeriph
 | DBG_TIM19_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB2_GRP1_UnFreezePeriph
 | DBG_TIM1_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB2_GRP1_UnFreezePeriph
 | DBG_TIM20_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB2_GRP1_UnFreezePeriph
 | DBG_TIM8_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB2_GRP1_UnFreezePeriph
DBGMCU_CR | DBG_SLEEP | LL_DBGMCU_DisableDBGSleepMode
 |  | LL_DBGMCU_EnableDBGSleepMode
 | DBG_STANDBY | LL_DBGMCU_DisableDBGStandbyMode
 |  | LL_DBGMCU_EnableDBGStandbyMode
 | DBG_STOP | LL_DBGMCU_DisableDBGStopMode
 |  | LL_DBGMCU_EnableDBGStopMode
 | TRACE_IOEN | LL_DBGMCU_GetTracePinAssignment
 |  | LL_DBGMCU_SetTracePinAssignment
 | TRACE_MODE | LL_DBGMCU_GetTracePinAssignment
 |  | LL_DBGMCU_SetTracePinAssignment
DBGMCU_IDCODE | DEV_ID | LL_DBGMCU_GetDeviceID
 | REV_ID | LL_DBGMCU_GetRevisionID
FLASH_ACR | LATENCY | LL_FLASH_GetLatency
 |  | LL_FLASH_SetLatency
 | PRFTBE | LL_FLASH_DisablePrefetch
 |  | LL_FLASH_EnablePrefetch
 | PRFTBS | LL_FLASH_IsPrefetchEnabled
SYSCFG_CFGR1 | DAC2Ch1_DMA_RMP | LL_SYSCFG_SetRemapDMA_DAC
 | FPU_IE_0 | LL_SYSCFG_DisableIT_FPU_IOC
 |  | LL_SYSCFG_EnableIT_FPU_IOC
 |  | LL_SYSCFG_IsEnabledIT_FPU_IOC
 | FPU_IE_1 | LL_SYSCFG_DisableIT_FPU_DZC
 |  | LL_SYSCFG_EnableIT_FPU_DZC
 |  | LL_SYSCFG_IsEnabledIT_FPU_DZC
 | FPU_IE_2 | LL_SYSCFG_DisableIT_FPU_UFC
 |  | LL_SYSCFG_EnableIT_FPU_UFC
 |  | LL_SYSCFG_IsEnabledIT_FPU_UFC
 | FPU_IE_3 | LL_SYSCFG_DisableIT_FPU_OFC
 |  | LL_SYSCFG_EnableIT_FPU_OFC
 |  | LL_SYSCFG_IsEnabledIT_FPU_OFC
 | FPU_IE_4 | LL_SYSCFG_DisableIT_FPU_IDC
 |  | LL_SYSCFG_EnableIT_FPU_IDC
 |  | LL_SYSCFG_IsEnabledIT_FPU_IDC
 | FPU_IE_5 | LL_SYSCFG_DisableIT_FPU_IXC
 |  | LL_SYSCFG_EnableIT_FPU_IXC
 |  | LL_SYSCFG_IsEnabledIT_FPU_IXC
 | I2C1_FMP | LL_SYSCFG_DisableFastModePlus
 |  | LL_SYSCFG_EnableFastModePlus
 | I2C2_FMP | LL_SYSCFG_DisableFastModePlus
 |  | LL_SYSCFG_EnableFastModePlus
 | I2C3_FMP | LL_SYSCFG_DisableFastModePlus
 |  | LL_SYSCFG_EnableFastModePlus
 | I2C_PB6_FMP | LL_SYSCFG_DisableFastModePlus
 |  | LL_SYSCFG_EnableFastModePlus
 | I2C_PB7_FMP | LL_SYSCFG_DisableFastModePlus
 |  | LL_SYSCFG_EnableFastModePlus
 | I2C_PB8_FMP | LL_SYSCFG_DisableFastModePlus
 |  | LL_SYSCFG_EnableFastModePlus
 | I2C_PB9_FMP | LL_SYSCFG_DisableFastModePlus
 |  | LL_SYSCFG_EnableFastModePlus
 | MEM_MODE | LL_SYSCFG_GetRemapMemory
 |  | LL_SYSCFG_SetRemapMemory
 | TIM16_DMA_RMP | LL_SYSCFG_SetRemapDMA_TIM
 | TIM17_DMA_RMP | LL_SYSCFG_SetRemapDMA_TIM
 | TIM18DAC2Ch1_DMA_RMP | LL_SYSCFG_SetRemapDMA_TIM
 | TIM6DAC1Ch1_DMA_RMP | LL_SYSCFG_SetRemapDMA_DAC
 |  | LL_SYSCFG_SetRemapDMA_TIM
 | TIM7DAC1Ch2_DMA_RMP | LL_SYSCFG_SetRemapDMA_TIM
 | VBAT | LL_SYSCFG_DisableVBATMonitoring
 |  | LL_SYSCFG_EnableVBATMonitoring
SYSCFG_CFGR2 | LOCKUP_LOCK | LL_SYSCFG_GetTIMBreakInputs
 |  | LL_SYSCFG_SetTIMBreakInputs
 | PVD_LOCK | LL_SYSCFG_GetTIMBreakInputs
 |  | LL_SYSCFG_SetTIMBreakInputs
 | SRAM_PARITY_LOCK | LL_SYSCFG_GetTIMBreakInputs
 |  | LL_SYSCFG_SetTIMBreakInputs
 | SRAM_PE | LL_SYSCFG_ClearFlag_SP
 |  | LL_SYSCFG_IsActiveFlag_SP
SYSCFG_EXTICR1 | EXTI0 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI1 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI10 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI11 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI12 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI13 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI14 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI15 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI2 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI3 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI4 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI5 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI6 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI7 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI8 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI9 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 | EXTI0 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI1 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI10 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI11 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI12 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI13 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI14 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI15 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI2 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI3 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI4 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI5 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI6 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI7 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI8 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI9 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 | EXTI0 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI1 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI10 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI11 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI12 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI13 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI14 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI15 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI2 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI3 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI4 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI5 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI6 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI7 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI8 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI9 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 | EXTI0 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI1 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI10 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI11 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI12 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI13 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI14 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI15 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI2 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI3 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI4 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI5 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI6 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI7 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI8 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
 | EXTI9 | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SYSTEM Private Constants

Defines
SYSTEM Private Constants
SYSTEM

Defines

#define | SYSCFG_OFFSET_CFGR1 0x00000000U
#define | SYSCFG_OFFSET_CFGR3 0x00000050U
#define | SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)

Define Documentation

#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)

Definition at line 83 of file stm32f3xx_ll_system.h.

Referenced by LL_SYSCFG_GetTIMBreakInputs(), and LL_SYSCFG_SetTIMBreakInputs().

#define SYSCFG_OFFSET_CFGR1 0x00000000U

Definition at line 78 of file stm32f3xx_ll_system.h.

#define SYSCFG_OFFSET_CFGR3 0x00000050U

Definition at line 79 of file stm32f3xx_ll_system.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SYSCFG REMAP

Defines
SYSCFG REMAP
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /* Main Flash memory mapped at 0x00000000 */
#define | LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /* System Flash memory mapped at 0x00000000 */
#define | LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /* Embedded SRAM mapped at 0x00000000 */

Define Documentation

#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /* Main Flash memory mapped at 0x00000000 */

Definition at line 107 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /* Embedded SRAM mapped at 0x00000000 */

Definition at line 109 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /* System Flash memory mapped at 0x00000000 */

Definition at line 108 of file stm32f3xx_ll_system.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SYSCFG DAC1/2 DMA1/2 request REMAP

Defines
SYSCFG DAC1/2 DMA1/2 request REMAP
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
#define | LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP)
#define | LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U)
#define | LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
#define | LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
#define | LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)

Define Documentation

#define LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP)

DAC_CH1 DMA requests mapped on DMA1 channel 3

Definition at line 172 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)

DAC_CH1 DMA requests mapped on DMA2 channel 3

Definition at line 171 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)

DAC1_OUT2 DMA requests mapped on DMA1 channel 4

Definition at line 175 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U)

DAC1_OUT2 DMA requests mapped on DMA2 channel 4

Definition at line 174 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)

DAC2_OUT1 DMA requests mapped on DMA1 channel 5

Definition at line 179 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)

DAC2_OUT1 DMA requests mapped on DMA2 channel 5

Definition at line 178 of file stm32f3xx_ll_system.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SYSCFG TIM DMA request REMAP

Defines
SYSCFG TIM DMA request REMAP
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | (uint32_t)0x00000000U)
#define | LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP)
#define | LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | (uint32_t)0x00000000U)
#define | LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP)
#define | LL_SYSCFG_TIM6_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
#define | LL_SYSCFG_TIM6_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP)
#define | LL_SYSCFG_TIM7_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U)
#define | LL_SYSCFG_TIM7_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
#define | LL_SYSCFG_TIM18_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
#define | LL_SYSCFG_TIM18_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)

Define Documentation

#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | (uint32_t)0x00000000U)

TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 3

Definition at line 192 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP)

TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6

Definition at line 193 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | (uint32_t)0x00000000U)

TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 1

Definition at line 194 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP)

TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7

Definition at line 195 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_TIM18_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)

TIM18 DMA requests mapped on DMA1 channel 5

Definition at line 204 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_TIM18_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)

TIM18 DMA requests mapped on DMA2 channel 5

Definition at line 203 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_TIM6_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP)

TIM6 DMA requests mapped on DMA1 channel 3

Definition at line 197 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_TIM6_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)

TIM6 DMA requests mapped on DMA2 channel 3

Definition at line 196 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_TIM7_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)

TIM7 DMA requests mapped on DMA1 channel 4

Definition at line 200 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_TIM7_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U)

TIM7 DMA requests mapped on DMA2 channel 4

Definition at line 199 of file stm32f3xx_ll_system.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SYSCFG I2C FASTMODEPLUS

Defines
SYSCFG I2C FASTMODEPLUS
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP

Define Documentation

#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP

I2C1 Fast mode plus

Definition at line 301 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP

I2C2 Fast mode plus

Definition at line 303 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP

I2C PB6 Fast mode plus

Definition at line 297 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP

I2C PB7 Fast mode plus

Definition at line 298 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP

I2C PB8 Fast mode plus

Definition at line 299 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

I2C PB9 Fast mode plus

Definition at line 300 of file stm32f3xx_ll_system.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SYSCFG EXTI PORT

Defines
SYSCFG EXTI PORT
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_EXTI_PORTA (uint32_t)0U
#define | LL_SYSCFG_EXTI_PORTB (uint32_t)1U
#define | LL_SYSCFG_EXTI_PORTC (uint32_t)2U
#define | LL_SYSCFG_EXTI_PORTD (uint32_t)3U
#define | LL_SYSCFG_EXTI_PORTE (uint32_t)4U
#define | LL_SYSCFG_EXTI_PORTF (uint32_t)5U

Define Documentation

#define LL_SYSCFG_EXTI_PORTA (uint32_t)0U

EXTI PORT A

Definition at line 315 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTB (uint32_t)1U

EXTI PORT B

Definition at line 316 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTC (uint32_t)2U

EXTI PORT C

Definition at line 317 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTD (uint32_t)3U

EXTI PORT D

Definition at line 318 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTE (uint32_t)4U

EXTI PORT E

Definition at line 320 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTF (uint32_t)5U

EXTI PORT F

Definition at line 322 of file stm32f3xx_ll_system.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SYSCFG EXTI LINE

Defines
SYSCFG EXTI LINE
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* EXTI_POSITION_0 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* EXTI_POSITION_4 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* EXTI_POSITION_8 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* EXTI_POSITION_12 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* EXTI_POSITION_0 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* EXTI_POSITION_4 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* EXTI_POSITION_8 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* EXTI_POSITION_12 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* EXTI_POSITION_0 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* EXTI_POSITION_4 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* EXTI_POSITION_8 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* EXTI_POSITION_12 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* EXTI_POSITION_0 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* EXTI_POSITION_4 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* EXTI_POSITION_8 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* EXTI_POSITION_12 | EXTICR[3] */

Define Documentation

#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* EXTI_POSITION_0 | EXTICR[0] */

Definition at line 336 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* EXTI_POSITION_4 | EXTICR[0] */

Definition at line 337 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* EXTI_POSITION_8 | EXTICR[2] */

Definition at line 346 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* EXTI_POSITION_12 | EXTICR[2] */

Definition at line 347 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* EXTI_POSITION_0 | EXTICR[3] */

Definition at line 348 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* EXTI_POSITION_4 | EXTICR[3] */

Definition at line 349 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* EXTI_POSITION_8 | EXTICR[3] */

Definition at line 350 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* EXTI_POSITION_12 | EXTICR[3] */

Definition at line 351 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* EXTI_POSITION_8 | EXTICR[0] */

Definition at line 338 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* EXTI_POSITION_12 | EXTICR[0] */

Definition at line 339 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* EXTI_POSITION_0 | EXTICR[1] */

Definition at line 340 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* EXTI_POSITION_4 | EXTICR[1] */

Definition at line 341 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* EXTI_POSITION_8 | EXTICR[1] */

Definition at line 342 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* EXTI_POSITION_12 | EXTICR[1] */

Definition at line 343 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* EXTI_POSITION_0 | EXTICR[2] */

Definition at line 344 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* EXTI_POSITION_4 | EXTICR[2] */

Definition at line 345 of file stm32f3xx_ll_system.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SYSCFG TIMER BREAK

Defines
SYSCFG TIMER BREAK
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK
#define | LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK
#define | LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK

Define Documentation

#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK

Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMx

Definition at line 365 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK

Enables and locks the PVD connection with TIMx Break Input and also the PVDE and PLS bits of the Power Control Interface

Definition at line 360 of file stm32f3xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK

Enables and locks the SRAM_PARITY error signal with Break Input of TIMx

Definition at line 363 of file stm32f3xx_ll_system.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DBGMCU TRACE Pin Assignment

Defines
DBGMCU TRACE Pin Assignment
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_TRACE_NONE 0x00000000U
#define | LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN
#define | LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)

Define Documentation

#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN

TRACE pin assignment for Asynchronous Mode

Definition at line 404 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_TRACE_NONE 0x00000000U

TRACE pins not assigned (default state)

Definition at line 403 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)

TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1

Definition at line 405 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)

TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2

Definition at line 406 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)

TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4

Definition at line 407 of file stm32f3xx_ll_system.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DBGMCU APB1 GRP1 STOP IP

Defines
DBGMCU APB1 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM18_STOP DBGMCU_APB1_FZ_DBG_TIM18_STOP
#define | LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP
#define | LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT
#define | LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT
#define | LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP

Define Documentation

#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP

CAN debug stopped when Core is halted

Definition at line 452 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT

I2C1 SMBUS timeout mode stopped when Core is halted

Definition at line 444 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT

I2C2 SMBUS timeout mode stopped when Core is halted

Definition at line 446 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP

Debug Independent Watchdog stopped when Core is halted

Definition at line 443 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP

RTC counter stopped when core is halted

Definition at line 441 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP

TIM12 counter stopped when core is halted

Definition at line 430 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP

TIM13 counter stopped when core is halted

Definition at line 433 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP

TIM14 counter stopped when core is halted

Definition at line 436 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM18_STOP DBGMCU_APB1_FZ_DBG_TIM18_STOP

TIM18 counter stopped when core is halted

Definition at line 439 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP

TIM2 counter stopped when core is halted

Definition at line 415 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP

TIM3 counter stopped when core is halted

Definition at line 417 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP

TIM4 counter stopped when core is halted

Definition at line 420 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP

TIM5 counter stopped when core is halted

Definition at line 423 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP

TIM6 counter stopped when core is halted

Definition at line 425 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP

TIM7 counter stopped when core is halted

Definition at line 427 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP

Debug Window Watchdog stopped when Core is halted

Definition at line 442 of file stm32f3xx_ll_system.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DBGMCU APB2 GRP1 STOP IP

Defines
DBGMCU APB2 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM19_STOP DBGMCU_APB2_FZ_DBG_TIM19_STOP

Define Documentation

#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP

TIM15 counter stopped when core is halted

Definition at line 467 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP

TIM16 counter stopped when core is halted

Definition at line 468 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP

TIM17 counter stopped when core is halted

Definition at line 469 of file stm32f3xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM19_STOP DBGMCU_APB2_FZ_DBG_TIM19_STOP

TIM19 counter stopped when core is halted

Definition at line 471 of file stm32f3xx_ll_system.h.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASH LATENCY

Defines
FLASH LATENCY
SYSTEM Exported Constants

Defines

#define | LL_FLASH_LATENCY_0 0x00000000U
#define | LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0
#define | LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1

Define Documentation

#define LL_FLASH_LATENCY_0 0x00000000U

FLASH Zero Latency cycle

Definition at line 486 of file stm32f3xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0

FLASH One Latency cycle

Definition at line 487 of file stm32f3xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1

FLASH Two Latency cycles

Definition at line 488 of file stm32f3xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SYSCFG

Functions
SYSCFG
SYSTEM Exported Functions

Functions

__STATIC_INLINE void | LL_SYSCFG_SetRemapMemory (uint32_t Memory)
Set memory mapping at address 0x00000000.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetRemapMemory (void)
Get memory mapping at address 0x00000000.
__STATIC_INLINE void | LL_SYSCFG_SetRemapDMA_DAC (uint32_t Remap)
Set DMA request remapping bits for DAC.
__STATIC_INLINE void | LL_SYSCFG_SetRemapDMA_TIM (uint32_t Remap)
Set DMA request remapping bits for TIM.
__STATIC_INLINE void | LL_SYSCFG_EnableVBATMonitoring (void)
Enable VBAT monitoring (to enable the power switch to deliver VBAT voltage on ADC channel 18 input)
__STATIC_INLINE void | LL_SYSCFG_DisableVBATMonitoring (void)
Disable VBAT monitoring.
__STATIC_INLINE void | LL_SYSCFG_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IOC (void)
Enable Floating Point Unit Invalid operation Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_DZC (void)
Enable Floating Point Unit Divide-by-zero Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_UFC (void)
Enable Floating Point Unit Underflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_OFC (void)
Enable Floating Point Unit Overflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IDC (void)
Enable Floating Point Unit Input denormal Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IXC (void)
Enable Floating Point Unit Inexact Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IOC (void)
Disable Floating Point Unit Invalid operation Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_DZC (void)
Disable Floating Point Unit Divide-by-zero Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_UFC (void)
Disable Floating Point Unit Underflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_OFC (void)
Disable Floating Point Unit Overflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IDC (void)
Disable Floating Point Unit Input denormal Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IXC (void)
Disable Floating Point Unit Inexact Interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IOC (void)
Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_DZC (void)
Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_UFC (void)
Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_OFC (void)
Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IDC (void)
Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IXC (void)
Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
__STATIC_INLINE void | LL_SYSCFG_SetEXTISource (uint32_t Port, uint32_t Line)
Configure source input for the EXTI external interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetEXTISource (uint32_t Line)
Get the configured defined for specific EXTI Line.
__STATIC_INLINE void | LL_SYSCFG_SetTIMBreakInputs (uint32_t Break)
Set connections to TIMx Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetTIMBreakInputs (void)
Get connections to TIMx Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_SP (void)
Check if SRAM parity error detected.
__STATIC_INLINE void | LL_SYSCFG_ClearFlag_SP (void)
Clear SRAM parity error flag.

Function Documentation

__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP ( void )

Clear SRAM parity error flag.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_ClearFlag_SP
Return values:
None

Definition at line 1289 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus ( uint32_t ConfigFastModePlus )

Disable the I2C fast mode plus driving capability.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_DisableFastModePlus
SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_DisableFastModePlus
SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_DisableFastModePlus
SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_DisableFastModePlus
SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_DisableFastModePlus
SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_DisableFastModePlus
SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_DisableFastModePlus
Parameters:
ConfigFastModePlus This parameter can be a combination of the following values:
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 840 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC ( void )

Disable Floating Point Unit Divide-by-zero Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
Return values:
None

Definition at line 920 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC ( void )

Disable Floating Point Unit Input denormal Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
Return values:
None

Definition at line 950 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC ( void )

Disable Floating Point Unit Invalid operation Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
Return values:
None

Definition at line 910 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC ( void )

Disable Floating Point Unit Inexact Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
Return values:
None

Definition at line 960 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC ( void )

Disable Floating Point Unit Overflow Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
Return values:
None

Definition at line 940 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC ( void )

Disable Floating Point Unit Underflow Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
Return values:
None

Definition at line 930 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableVBATMonitoring ( void )

Disable VBAT monitoring.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 VBAT LL_SYSCFG_DisableVBATMonitoring
Return values:
None

Definition at line 787 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus ( uint32_t ConfigFastModePlus )

Enable the I2C fast mode plus driving capability.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_EnableFastModePlus
Parameters:
ConfigFastModePlus This parameter can be a combination of the following values:
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 814 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC ( void )

Enable Floating Point Unit Divide-by-zero Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
Return values:
None

Definition at line 860 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC ( void )

Enable Floating Point Unit Input denormal Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
Return values:
None

Definition at line 890 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC ( void )

Enable Floating Point Unit Invalid operation Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
Return values:
None

Definition at line 850 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC ( void )

Enable Floating Point Unit Inexact Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
Return values:
None

Definition at line 900 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC ( void )

Enable Floating Point Unit Overflow Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
Return values:
None

Definition at line 880 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC ( void )

Enable Floating Point Unit Underflow Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
Return values:
None

Definition at line 870 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableVBATMonitoring ( void )

Enable VBAT monitoring (to enable the power switch to deliver VBAT voltage on ADC channel 18 input)

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 VBAT LL_SYSCFG_EnableVBATMonitoring
Return values:
None

Definition at line 777 of file stm32f3xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource ( uint32_t Line )

Get the configured defined for specific EXTI Line.

Reference Manual to LL API cross reference:
SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_GetEXTISource
Parameters:
Line This parameter can be one of the following values:
  • LL_SYSCFG_EXTI_LINE0
  • LL_SYSCFG_EXTI_LINE1
  • LL_SYSCFG_EXTI_LINE2
  • LL_SYSCFG_EXTI_LINE3
  • LL_SYSCFG_EXTI_LINE4
  • LL_SYSCFG_EXTI_LINE5
  • LL_SYSCFG_EXTI_LINE6
  • LL_SYSCFG_EXTI_LINE7
  • LL_SYSCFG_EXTI_LINE8
  • LL_SYSCFG_EXTI_LINE9
  • LL_SYSCFG_EXTI_LINE10
  • LL_SYSCFG_EXTI_LINE11
  • LL_SYSCFG_EXTI_LINE12
  • LL_SYSCFG_EXTI_LINE13
  • LL_SYSCFG_EXTI_LINE14
  • LL_SYSCFG_EXTI_LINE15
Return values:
Returned value can be one of the following values:
  • LL_SYSCFG_EXTI_PORTA
  • LL_SYSCFG_EXTI_PORTB
  • LL_SYSCFG_EXTI_PORTC
  • LL_SYSCFG_EXTI_PORTD
  • LL_SYSCFG_EXTI_PORTE (*)
  • LL_SYSCFG_EXTI_PORTF
  • LL_SYSCFG_EXTI_PORTG (*)
  • LL_SYSCFG_EXTI_PORTH (*)
(*) value not defined in all devices.

Definition at line 1221 of file stm32f3xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory ( void )

Get memory mapping at address 0x00000000.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
Return values:
Returned value can be one of the following values:
  • LL_SYSCFG_REMAP_FLASH
  • LL_SYSCFG_REMAP_SYSTEMFLASH
  • LL_SYSCFG_REMAP_SRAM
  • LL_SYSCFG_REMAP_FMC (*)
(*) value not defined in all devices.

Definition at line 536 of file stm32f3xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs ( void )

Get connections to TIMx Break inputs.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs
Return values:
Returned value can be can be a combination of the following values:
  • LL_SYSCFG_TIMBREAK_PVD (*)
  • LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
  • LL_SYSCFG_TIMBREAK_LOCKUP
(*) value not defined in all devices.

Definition at line 1256 of file stm32f3xx_ll_system.h.

References SYSCFG_MASK_TIM_BREAK.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP ( void )

Check if SRAM parity error detected.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_IsActiveFlag_SP
Return values:
State of bit (1 or 0).

Definition at line 1279 of file stm32f3xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC ( void )

Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
Return values:
State of bit (1 or 0).

Definition at line 980 of file stm32f3xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC ( void )

Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
Return values:
State of bit (1 or 0).

Definition at line 1010 of file stm32f3xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC ( void )

Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
Return values:
State of bit (1 or 0).

Definition at line 970 of file stm32f3xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC ( void )

Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
Return values:
State of bit (1 or 0).

Definition at line 1020 of file stm32f3xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC ( void )

Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
Return values:
State of bit (1 or 0).

Definition at line 1000 of file stm32f3xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC ( void )

Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
Return values:
State of bit (1 or 0).

Definition at line 990 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetEXTISource | ( | uint32_t | Port,
 |  | uint32_t | Line
 | ) |  |

Configure source input for the EXTI external interrupt.

Reference Manual to LL API cross reference:
SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
Parameters:
Port This parameter can be one of the following values:
  • LL_SYSCFG_EXTI_PORTA
  • LL_SYSCFG_EXTI_PORTB
  • LL_SYSCFG_EXTI_PORTC
  • LL_SYSCFG_EXTI_PORTD
  • LL_SYSCFG_EXTI_PORTE (*)
  • LL_SYSCFG_EXTI_PORTF
  • LL_SYSCFG_EXTI_PORTG (*)
  • LL_SYSCFG_EXTI_PORTH (*)
(*) value not defined in all devices.
Line This parameter can be one of the following values:
  • LL_SYSCFG_EXTI_LINE0
  • LL_SYSCFG_EXTI_LINE1
  • LL_SYSCFG_EXTI_LINE2
  • LL_SYSCFG_EXTI_LINE3
  • LL_SYSCFG_EXTI_LINE4
  • LL_SYSCFG_EXTI_LINE5
  • LL_SYSCFG_EXTI_LINE6
  • LL_SYSCFG_EXTI_LINE7
  • LL_SYSCFG_EXTI_LINE8
  • LL_SYSCFG_EXTI_LINE9
  • LL_SYSCFG_EXTI_LINE10
  • LL_SYSCFG_EXTI_LINE11
  • LL_SYSCFG_EXTI_LINE12
  • LL_SYSCFG_EXTI_LINE13
  • LL_SYSCFG_EXTI_LINE14
  • LL_SYSCFG_EXTI_LINE15
Return values:
None

Definition at line 1121 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_DAC ( uint32_t Remap )

Set DMA request remapping bits for DAC.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC
SYSCFG_CFGR1 DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC
Parameters:
Remap This parameter can be one of the following values:
  • LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3
  • LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3
  • LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 (*)
  • LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 (*)
  • LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 (*)
  • LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 (*)
  • LL_SYSCFG_DAC2_CH1_RMP_NO (*)
  • LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 621 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM ( uint32_t Remap )

Set DMA request remapping bits for TIM.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
SYSCFG_CFGR1 TIM7DAC1Ch2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
SYSCFG_CFGR1 TIM18DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
Parameters:
Remap This parameter can be a combination of the following values:
  • LL_SYSCFG_TIM16_RMP_DMA1_CH3 or LL_SYSCFG_TIM16_RMP_DMA1_CH6
  • LL_SYSCFG_TIM17_RMP_DMA1_CH1 or LL_SYSCFG_TIM17_RMP_DMA1_CH7
  • LL_SYSCFG_TIM6_RMP_DMA2_CH3 or LL_SYSCFG_TIM6_RMP_DMA1_CH3
  • LL_SYSCFG_TIM7_RMP_DMA2_CH4 or LL_SYSCFG_TIM7_RMP_DMA1_CH4 (*)
  • LL_SYSCFG_TIM18_RMP_DMA2_CH5 or LL_SYSCFG_TIM18_RMP_DMA1_CH5 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 643 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetRemapMemory ( uint32_t Memory )

Set memory mapping at address 0x00000000.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
Parameters:
Memory This parameter can be one of the following values:
  • LL_SYSCFG_REMAP_FLASH
  • LL_SYSCFG_REMAP_SYSTEMFLASH
  • LL_SYSCFG_REMAP_SRAM
  • LL_SYSCFG_REMAP_FMC (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 520 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs ( uint32_t Break )

Set connections to TIMx Break inputs.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs
Parameters:
Break This parameter can be a combination of the following values:
  • LL_SYSCFG_TIMBREAK_PVD (*)
  • LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
  • LL_SYSCFG_TIMBREAK_LOCKUP
(*) value not defined in all devices.
Return values:
None

Definition at line 1239 of file stm32f3xx_ll_system.h.

References SYSCFG_MASK_TIM_BREAK.

Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DBGMCU

Functions
DBGMCU
SYSTEM Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DBGMCU_GetDeviceID (void)
Return the device identifier.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetRevisionID (void)
Return the device revision identifier.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_SetTracePinAssignment (uint32_t PinAssignment)
Set Trace pin assignment control.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetTracePinAssignment (void)
Get Trace pin assignment control.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB2 peripherals.

Function Documentation

__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze APB1 peripherals (group1 peripherals)

Reference Manual to LL API cross reference:
APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph
APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph
APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph
APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
  • LL_DBGMCU_APB1_GRP1_RTC_STOP
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
  • LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1510 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze APB1 peripherals (group1 peripherals)

Reference Manual to LL API cross reference:
APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph
APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph
APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph
APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
  • LL_DBGMCU_APB1_GRP1_RTC_STOP
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
  • LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1556 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze APB2 peripherals.

Reference Manual to LL API cross reference:
APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP
  • LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
  • LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1584 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze APB2 peripherals.

Reference Manual to LL API cross reference:
APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP
  • LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
  • LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1612 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode ( void )

Disable the Debug Module during SLEEP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
Return values:
None

Definition at line 1391 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode ( void )

Disable the Debug Module during STANDBY mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
Return values:
None

Definition at line 1431 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode ( void )

Disable the Debug Module during STOP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
Return values:
None

Definition at line 1411 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode ( void )

Enable the Debug Module during SLEEP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
Return values:
None

Definition at line 1381 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode ( void )

Enable the Debug Module during STANDBY mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
Return values:
None

Definition at line 1421 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode ( void )

Enable the Debug Module during STOP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
Return values:
None

Definition at line 1401 of file stm32f3xx_ll_system.h.

__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID ( void )

Return the device identifier.

Note:
For STM32F303xC, STM32F358xx and STM32F302xC devices, the device ID is 0x422
For STM32F373xx and STM32F378xx devices, the device ID is 0x432
For STM32F303x8, STM32F334xx and STM32F328xx devices, the device ID is 0x438.
For STM32F302x8, STM32F301x8 and STM32F318xx devices, the device ID is 0x439
For STM32F303xE, STM32F398xx and STM32F302xE devices, the device ID is 0x446
Reference Manual to LL API cross reference:
DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
Return values:
Values between Min_Data=0x00 and Max_Data=0xFFF

Definition at line 1360 of file stm32f3xx_ll_system.h.

__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID ( void )

Return the device revision identifier.

Note:
This field indicates the revision of the device.
Reference Manual to LL API cross reference:
DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
Return values:
Values between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 1371 of file stm32f3xx_ll_system.h.

__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment ( void )

Get Trace pin assignment control.

Reference Manual to LL API cross reference:
DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment
DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
Return values:
Returned value can be one of the following values:
  • LL_DBGMCU_TRACE_NONE
  • LL_DBGMCU_TRACE_ASYNCH
  • LL_DBGMCU_TRACE_SYNCH_SIZE1
  • LL_DBGMCU_TRACE_SYNCH_SIZE2
  • LL_DBGMCU_TRACE_SYNCH_SIZE4

Definition at line 1464 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment ( uint32_t PinAssignment )

Set Trace pin assignment control.

Reference Manual to LL API cross reference:
DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment
DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
Parameters:
PinAssignment This parameter can be one of the following values:
  • LL_DBGMCU_TRACE_NONE
  • LL_DBGMCU_TRACE_ASYNCH
  • LL_DBGMCU_TRACE_SYNCH_SIZE1
  • LL_DBGMCU_TRACE_SYNCH_SIZE2
  • LL_DBGMCU_TRACE_SYNCH_SIZE4
Return values:
None

Definition at line 1448 of file stm32f3xx_ll_system.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASH

Functions
FLASH
SYSTEM Exported Functions

Functions

__STATIC_INLINE void | LL_FLASH_SetLatency (uint32_t Latency)
Set FLASH Latency.
__STATIC_INLINE uint32_t | LL_FLASH_GetLatency (void)
Get FLASH Latency.
__STATIC_INLINE void | LL_FLASH_EnablePrefetch (void)
Enable Prefetch.
__STATIC_INLINE void | LL_FLASH_DisablePrefetch (void)
Disable Prefetch.
__STATIC_INLINE uint32_t | LL_FLASH_IsPrefetchEnabled (void)
Check if Prefetch buffer is enabled.

Function Documentation

__STATIC_INLINE void LL_FLASH_DisablePrefetch ( void )

Disable Prefetch.

Reference Manual to LL API cross reference:
FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
Return values:
None

Definition at line 1667 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnablePrefetch ( void )

Enable Prefetch.

Reference Manual to LL API cross reference:
FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
Return values:
None

Definition at line 1657 of file stm32f3xx_ll_system.h.

__STATIC_INLINE uint32_t LL_FLASH_GetLatency ( void )

Get FLASH Latency.

Reference Manual to LL API cross reference:
FLASH_ACR LATENCY LL_FLASH_GetLatency
Return values:
Returned value can be one of the following values:
  • LL_FLASH_LATENCY_0
  • LL_FLASH_LATENCY_1
  • LL_FLASH_LATENCY_2

Definition at line 1647 of file stm32f3xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled ( void )

Check if Prefetch buffer is enabled.

Reference Manual to LL API cross reference:
FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
Return values:
State of bit (1 or 0).

Definition at line 1677 of file stm32f3xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_SetLatency ( uint32_t Latency )

Set FLASH Latency.

Reference Manual to LL API cross reference:
FLASH_ACR LATENCY LL_FLASH_SetLatency
Parameters:
Latency This parameter can be one of the following values:
  • LL_FLASH_LATENCY_0
  • LL_FLASH_LATENCY_1
  • LL_FLASH_LATENCY_2
Return values:
None

Definition at line 1634 of file stm32f3xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM

Modules
TIM
STM32F3xx_LL_Driver

Modules

TIM Private Functions

Private functions.

TIM Private Variables
TIM Private Constants
TIM Private Macros
TIM Exported Init structure
TIM Exported Constants
TIM Exported Macros
TIM Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for TIM registers.

Register | Bit | Function
ARR | ARR | LL_TIM_GetAutoReload
 |  | LL_TIM_SetAutoReload
BDTR | AOE | LL_TIM_DisableAutomaticOutput
 |  | LL_TIM_EnableAutomaticOutput
 |  | LL_TIM_IsEnabledAutomaticOutput
 | BKE | LL_TIM_DisableBRK
 |  | LL_TIM_EnableBRK
 | BKP | LL_TIM_ConfigBRK
 | DTG | LL_TIM_OC_SetDeadTime
 | LOCK | LL_TIM_CC_SetLockLevel
 | MOE | LL_TIM_DisableAllOutputs
 |  | LL_TIM_EnableAllOutputs
 |  | LL_TIM_IsEnabledAllOutputs
 | OSSI | LL_TIM_SetOffStates
 | OSSR | LL_TIM_SetOffStates
CCER | CC1E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC1NE | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC1NP | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC1P | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC2E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC2NE | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC2NP | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC2P | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC3E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC3NE | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC3NP | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC3P | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC4E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC4NP | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 | CC4P | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC5E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC5P | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC6E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC6P | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
CCMR1 | CC1S | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetActiveInput
 |  | LL_TIM_IC_SetActiveInput
 |  | LL_TIM_OC_ConfigOutput
 | CC2S | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetActiveInput
 |  | LL_TIM_IC_SetActiveInput
 |  | LL_TIM_OC_ConfigOutput
 | IC1F | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetFilter
 |  | LL_TIM_IC_SetFilter
 | IC1PSC | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPrescaler
 |  | LL_TIM_IC_SetPrescaler
 | IC2F | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetFilter
 |  | LL_TIM_IC_SetFilter
 | IC2PSC | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPrescaler
 |  | LL_TIM_IC_SetPrescaler
 | OC1CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC1FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC1M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC1PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
 | OC2CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC2FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC2M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC2PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
CCMR2 | CC3S | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetActiveInput
 |  | LL_TIM_IC_SetActiveInput
 |  | LL_TIM_OC_ConfigOutput
 | CC4S | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetActiveInput
 |  | LL_TIM_IC_SetActiveInput
 |  | LL_TIM_OC_ConfigOutput
 | IC3F | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetFilter
 |  | LL_TIM_IC_SetFilter
 | IC3PSC | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPrescaler
 |  | LL_TIM_IC_SetPrescaler
 | IC4F | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetFilter
 |  | LL_TIM_IC_SetFilter
 | IC4PSC | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPrescaler
 |  | LL_TIM_IC_SetPrescaler
 | OC3CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC3FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC3M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC3PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
 | OC4CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC4FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC4M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC4PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
CCR1 | CCR1 | LL_TIM_IC_GetCaptureCH1
 |  | LL_TIM_OC_GetCompareCH1
 |  | LL_TIM_OC_SetCompareCH1
CCR2 | CCR2 | LL_TIM_IC_GetCaptureCH2
 |  | LL_TIM_OC_GetCompareCH2
 |  | LL_TIM_OC_SetCompareCH2
CCR3 | CCR3 | LL_TIM_IC_GetCaptureCH3
 |  | LL_TIM_OC_GetCompareCH3
 |  | LL_TIM_OC_SetCompareCH3
CCR4 | CCR4 | LL_TIM_IC_GetCaptureCH4
 |  | LL_TIM_OC_GetCompareCH4
 |  | LL_TIM_OC_SetCompareCH4
CNT | CNT | LL_TIM_GetCounter
 |  | LL_TIM_SetCounter
CR1 | ARPE | LL_TIM_DisableARRPreload
 |  | LL_TIM_EnableARRPreload
 |  | LL_TIM_IsEnabledARRPreload
 | CEN | LL_TIM_DisableCounter
 |  | LL_TIM_EnableCounter
 |  | LL_TIM_IsEnabledCounter
 | CKD | LL_TIM_GetClockDivision
 |  | LL_TIM_SetClockDivision
 | CMS | LL_TIM_GetCounterMode
 |  | LL_TIM_SetCounterMode
 | DIR | LL_TIM_GetCounterMode
 |  | LL_TIM_GetDirection
 |  | LL_TIM_SetCounterMode
 | OPM | LL_TIM_GetOnePulseMode
 |  | LL_TIM_SetOnePulseMode
 | UDIS | LL_TIM_DisableUpdateEvent
 |  | LL_TIM_EnableUpdateEvent
 |  | LL_TIM_IsEnabledUpdateEvent
 | URS | LL_TIM_GetUpdateSource
 |  | LL_TIM_SetUpdateSource
CR2 | CCDS | LL_TIM_CC_GetDMAReqTrigger
 |  | LL_TIM_CC_SetDMAReqTrigger
 | CCPC | LL_TIM_CC_DisablePreload
 |  | LL_TIM_CC_EnablePreload
 | CCUS | LL_TIM_CC_SetUpdate
 | MMS | LL_TIM_SetTriggerOutput
 | OIS1 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS2 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS2N | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS3 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS3N | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS4 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS5 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS6 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | TI1S | LL_TIM_IC_DisableXORCombination
 |  | LL_TIM_IC_EnableXORCombination
 |  | LL_TIM_IC_IsEnabledXORCombination
DCR | DBA | LL_TIM_ConfigDMABurst
 | DBL | LL_TIM_ConfigDMABurst
DIER | BIE | LL_TIM_DisableIT_BRK
 |  | LL_TIM_EnableIT_BRK
 |  | LL_TIM_IsEnabledIT_BRK
 | CC1DE | LL_TIM_DisableDMAReq_CC1
 |  | LL_TIM_EnableDMAReq_CC1
 |  | LL_TIM_IsEnabledDMAReq_CC1
 | CC1IE | LL_TIM_DisableIT_CC1
 |  | LL_TIM_EnableIT_CC1
 |  | LL_TIM_IsEnabledIT_CC1
 | CC2DE | LL_TIM_DisableDMAReq_CC2
 |  | LL_TIM_EnableDMAReq_CC2
 |  | LL_TIM_IsEnabledDMAReq_CC2
 | CC2IE | LL_TIM_DisableIT_CC2
 |  | LL_TIM_EnableIT_CC2
 |  | LL_TIM_IsEnabledIT_CC2
 | CC3DE | LL_TIM_DisableDMAReq_CC3
 |  | LL_TIM_EnableDMAReq_CC3
 |  | LL_TIM_IsEnabledDMAReq_CC3
 | CC3IE | LL_TIM_DisableIT_CC3
 |  | LL_TIM_EnableIT_CC3
 |  | LL_TIM_IsEnabledIT_CC3
 | CC4DE | LL_TIM_DisableDMAReq_CC4
 |  | LL_TIM_EnableDMAReq_CC4
 |  | LL_TIM_IsEnabledDMAReq_CC4
 | CC4IE | LL_TIM_DisableIT_CC4
 |  | LL_TIM_EnableIT_CC4
 |  | LL_TIM_IsEnabledIT_CC4
 | COMDE | LL_TIM_DisableDMAReq_COM
 |  | LL_TIM_EnableDMAReq_COM
 |  | LL_TIM_IsEnabledDMAReq_COM
 | COMIE | LL_TIM_DisableIT_COM
 |  | LL_TIM_EnableIT_COM
 |  | LL_TIM_IsEnabledIT_COM
 | TDE | LL_TIM_DisableDMAReq_TRIG
 |  | LL_TIM_EnableDMAReq_TRIG
 |  | LL_TIM_IsEnabledDMAReq_TRIG
 | TIE | LL_TIM_DisableIT_TRIG
 |  | LL_TIM_EnableIT_TRIG
 |  | LL_TIM_IsEnabledIT_TRIG
 | UDE | LL_TIM_DisableDMAReq_UPDATE
 |  | LL_TIM_EnableDMAReq_UPDATE
 |  | LL_TIM_IsEnabledDMAReq_UPDATE
 | UIE | LL_TIM_DisableIT_UPDATE
 |  | LL_TIM_EnableIT_UPDATE
 |  | LL_TIM_IsEnabledIT_UPDATE
EGR | BG | LL_TIM_GenerateEvent_BRK
 | CC1G | LL_TIM_GenerateEvent_CC1
 | CC2G | LL_TIM_GenerateEvent_CC2
 | CC3G | LL_TIM_GenerateEvent_CC3
 | CC4G | LL_TIM_GenerateEvent_CC4
 | COMG | LL_TIM_GenerateEvent_COM
 | TG | LL_TIM_GenerateEvent_TRIG
 | UG | LL_TIM_GenerateEvent_UPDATE
PSC | PSC | LL_TIM_GetPrescaler
 |  | LL_TIM_SetPrescaler
RCR | REP | LL_TIM_GetRepetitionCounter
 |  | LL_TIM_SetRepetitionCounter
SMCR | ECE | LL_TIM_DisableExternalClock
 |  | LL_TIM_EnableExternalClock
 |  | LL_TIM_IsEnabledExternalClock
 |  | LL_TIM_SetClockSource
 | ETF | LL_TIM_ConfigETR
 | ETP | LL_TIM_ConfigETR
 | ETPS | LL_TIM_ConfigETR
 | MSM | LL_TIM_DisableMasterSlaveMode
 |  | LL_TIM_EnableMasterSlaveMode
 |  | LL_TIM_IsEnabledMasterSlaveMode
 | SMS | LL_TIM_SetClockSource
 |  | LL_TIM_SetEncoderMode
 |  | LL_TIM_SetSlaveMode
 | TS | LL_TIM_SetTriggerInput
SR | BIF | LL_TIM_ClearFlag_BRK
 |  | LL_TIM_IsActiveFlag_BRK
 | CC1IF | LL_TIM_ClearFlag_CC1
 |  | LL_TIM_IsActiveFlag_CC1
 | CC1OF | LL_TIM_ClearFlag_CC1OVR
 |  | LL_TIM_IsActiveFlag_CC1OVR
 | CC2IF | LL_TIM_ClearFlag_CC2
 |  | LL_TIM_IsActiveFlag_CC2
 | CC2OF | LL_TIM_ClearFlag_CC2OVR
 |  | LL_TIM_IsActiveFlag_CC2OVR
 | CC3IF | LL_TIM_ClearFlag_CC3
 |  | LL_TIM_IsActiveFlag_CC3
 | CC3OF | LL_TIM_ClearFlag_CC3OVR
 |  | LL_TIM_IsActiveFlag_CC3OVR
 | CC4IF | LL_TIM_ClearFlag_CC4
 |  | LL_TIM_IsActiveFlag_CC4
 | CC4OF | LL_TIM_ClearFlag_CC4OVR
 |  | LL_TIM_IsActiveFlag_CC4OVR
 | COMIF | LL_TIM_ClearFlag_COM
 |  | LL_TIM_IsActiveFlag_COM
 | TIF | LL_TIM_ClearFlag_TRIG
 |  | LL_TIM_IsActiveFlag_TRIG
 | UIF | LL_TIM_ClearFlag_UPDATE
 |  | LL_TIM_IsActiveFlag_UPDATE
TIM14_OR | TI1_RMP | LL_TIM_SetRemap
Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Private Functions

Functions
TIM Private Functions
TIM

Private functions. More...

Functions

static ErrorStatus | OC1Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 1.
static ErrorStatus | OC2Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 2.
static ErrorStatus | OC3Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 3.
static ErrorStatus | OC4Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 4.
static ErrorStatus | IC1Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 1.
static ErrorStatus | IC2Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 2.
static ErrorStatus | IC3Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 3.
static ErrorStatus | IC4Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 4.

Detailed Description

Private functions.

Function Documentation

static ErrorStatus IC1Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 1.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 1 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1324 of file stm32f3xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC2Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 2.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 2 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1357 of file stm32f3xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC3Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 3.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 3 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1390 of file stm32f3xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC4Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 4.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 4 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1423 of file stm32f3xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus OC1Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 1.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 1 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 883 of file stm32f3xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH1(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC2Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 2.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 2 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 962 of file stm32f3xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH2(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC3Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 3.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 3 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1044 of file stm32f3xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH3(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC4Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 4.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 4 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1126 of file stm32f3xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH4(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Private Variables

Variables
TIM Private Variables
TIM

Variables

static const uint8_t | OFFSET_TAB_CCMRx []
static const uint8_t | SHIFT_TAB_OCxx []
static const uint8_t | SHIFT_TAB_ICxx []
static const uint8_t | SHIFT_TAB_CCxP []
static const uint8_t | SHIFT_TAB_OISx []

Variable Documentation

const uint8_t OFFSET_TAB_CCMRx[] [static]
Initial value:
{
  0x00U,
  0x00U,
  0x00U,
  0x00U,
  0x04U,
  0x04U,
  0x04U,
  0x3CU,
  0x3CU
}

Definition at line 62 of file stm32f3xx_ll_tim.h.

const uint8_t SHIFT_TAB_CCxP[] [static]
Initial value:
{
  0U,
  2U,
  4U,
  6U,
  8U,
  10U,
  12U,
  16U,
  20U
}

Definition at line 101 of file stm32f3xx_ll_tim.h.

const uint8_t SHIFT_TAB_ICxx[] [static]
Initial value:
{
  0U,
  0U,
  8U,
  0U,
  0U,
  0U,
  8U,
  0U,
  0U
}

Definition at line 88 of file stm32f3xx_ll_tim.h.

const uint8_t SHIFT_TAB_OCxx[] [static]
Initial value:
{
  0U,
  0U,
  8U,
  0U,
  0U,
  0U,
  8U,
  0U,
  8U
}

Definition at line 75 of file stm32f3xx_ll_tim.h.

const uint8_t SHIFT_TAB_OISx[] [static]
Initial value:
{
  0U,
  1U,
  2U,
  3U,
  4U,
  5U,
  6U,
  8U,
  10U
}

Definition at line 114 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Private Constants

Defines
TIM Private Constants
TIM

Defines

#define | TIMx_OR_RMP_SHIFT 16U
#define | TIMx_OR_RMP_MASK 0x0000FFFFU
#define | TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
#define | TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
#define | DT_DELAY_1 ((uint8_t)0x7FU)
#define | DT_DELAY_2 ((uint8_t)0x3FU)
#define | DT_DELAY_3 ((uint8_t)0x1FU)
#define | DT_DELAY_4 ((uint8_t)0x1FU)
#define | DT_RANGE_1 ((uint8_t)0x00U)
#define | DT_RANGE_2 ((uint8_t)0x80U)
#define | DT_RANGE_3 ((uint8_t)0xC0U)
#define | DT_RANGE_4 ((uint8_t)0xE0U)

Define Documentation

#define DT_DELAY_1 ((uint8_t)0x7FU)

Definition at line 156 of file stm32f3xx_ll_tim.h.

#define DT_DELAY_2 ((uint8_t)0x3FU)

Definition at line 157 of file stm32f3xx_ll_tim.h.

#define DT_DELAY_3 ((uint8_t)0x1FU)

Definition at line 158 of file stm32f3xx_ll_tim.h.

#define DT_DELAY_4 ((uint8_t)0x1FU)

Definition at line 159 of file stm32f3xx_ll_tim.h.

#define DT_RANGE_1 ((uint8_t)0x00U)

Definition at line 162 of file stm32f3xx_ll_tim.h.

#define DT_RANGE_2 ((uint8_t)0x80U)

Definition at line 163 of file stm32f3xx_ll_tim.h.

#define DT_RANGE_3 ((uint8_t)0xC0U)

Definition at line 164 of file stm32f3xx_ll_tim.h.

#define DT_RANGE_4 ((uint8_t)0xE0U)

Definition at line 165 of file stm32f3xx_ll_tim.h.

#define TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)

Definition at line 146 of file stm32f3xx_ll_tim.h.

#define TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)

Definition at line 149 of file stm32f3xx_ll_tim.h.

#define TIMx_OR_RMP_MASK 0x0000FFFFU

Definition at line 138 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_SetRemap().

#define TIMx_OR_RMP_SHIFT 16U

Definition at line 137 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_SetRemap().

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Private Macros

Defines
TIM Private Macros
TIM

Defines

#define | IS_LL_TIM_COUNTERMODE(__VALUE__)
#define | IS_LL_TIM_CLOCKDIVISION(__VALUE__)
#define | IS_LL_TIM_OCMODE(__VALUE__)
#define | IS_LL_TIM_OCSTATE(__VALUE__)
#define | IS_LL_TIM_OCPOLARITY(__VALUE__)
#define | IS_LL_TIM_OCIDLESTATE(__VALUE__)
#define | IS_LL_TIM_ACTIVEINPUT(__VALUE__)
#define | IS_LL_TIM_ICPSC(__VALUE__)
#define | IS_LL_TIM_IC_FILTER(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY(__VALUE__)
#define | IS_LL_TIM_ENCODERMODE(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__)
#define | IS_LL_TIM_OSSR_STATE(__VALUE__)
#define | IS_LL_TIM_OSSI_STATE(__VALUE__)
#define | IS_LL_TIM_LOCK_LEVEL(__VALUE__)
#define | IS_LL_TIM_BREAK_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK_POLARITY(__VALUE__)
#define | IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__)
#define | TIM_GET_CHANNEL_INDEX(__CHANNEL__)
Convert channel id into channel index.
#define | TIM_CALC_DTS(__TIMCLK__, __CKD__)
Calculate the deadtime sampling period(in ps).

Define Documentation

#define IS_LL_TIM_ACTIVEINPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
                                       || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
                                       || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))

Definition at line 109 of file stm32f3xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_ENCODER_Init().

#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
                                                  || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))

Definition at line 207 of file stm32f3xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
                                          || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))

Definition at line 160 of file stm32f3xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_DISABLE) \
                                       || ((__VALUE__) == LL_TIM_BREAK_ENABLE))

Definition at line 157 of file stm32f3xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_CLOCKDIVISION ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
                                         || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
                                         || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))

Definition at line 70 of file stm32f3xx_ll_tim.c.

Referenced by LL_TIM_Init().

#define IS_LL_TIM_COUNTERMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))

Definition at line 64 of file stm32f3xx_ll_tim.c.

Referenced by LL_TIM_Init().

#define IS_LL_TIM_ENCODERMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
                                       || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
                                       || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))

Definition at line 139 of file stm32f3xx_ll_tim.c.

Referenced by LL_TIM_ENCODER_Init().

#define IS_LL_TIM_IC_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))

Definition at line 118 of file stm32f3xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_ENCODER_Init().

#define IS_LL_TIM_IC_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
                                       || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
                                       || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))

Definition at line 135 of file stm32f3xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), and IC4Config().

#define IS_LL_TIM_IC_POLARITY_ENCODER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
                                               || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))

Definition at line 143 of file stm32f3xx_ll_tim.c.

Referenced by LL_TIM_ENCODER_Init().

#define IS_LL_TIM_ICPSC ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ICPSC_DIV1) \
                                 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
                                 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
                                 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))

Definition at line 113 of file stm32f3xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_ENCODER_Init().

#define IS_LL_TIM_LOCK_LEVEL ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
                                      || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
                                      || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
                                      || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))

Definition at line 152 of file stm32f3xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_OCIDLESTATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
                                       || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))

Definition at line 106 of file stm32f3xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), and OC4Config().

#define IS_LL_TIM_OCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_PWM2))

Definition at line 90 of file stm32f3xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), and OC4Config().

#define IS_LL_TIM_OCPOLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
                                      || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))

Definition at line 103 of file stm32f3xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), and OC4Config().

#define IS_LL_TIM_OCSTATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
                                   || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))

Definition at line 100 of file stm32f3xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), and OC4Config().

#define IS_LL_TIM_OSSI_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OSSI_DISABLE) \
                                      || ((__VALUE__) == LL_TIM_OSSI_ENABLE))

Definition at line 149 of file stm32f3xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_OSSR_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OSSR_DISABLE) \
                                     || ((__VALUE__) == LL_TIM_OSSR_ENABLE))

Definition at line 146 of file stm32f3xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define TIM_CALC_DTS | ( | __TIMCLK__,
 |  | __CKD__
 | ) |
Value:
(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
     ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
     ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))

Calculate the deadtime sampling period(in ps).

Parameters:
__TIMCLK__ timer input clock frequency (in Hz).
__CKD__ This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
Return values:
none

Definition at line 218 of file stm32f3xx_ll_tim.h.

#define TIM_GET_CHANNEL_INDEX ( __CHANNEL__ )
Value:
(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)

Convert channel id into channel index.

Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Note:
CH5 and CH6 channels are not available for all F3 devices
Return values:
none

Definition at line 201 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_IC_Config(), LL_TIM_IC_GetActiveInput(), LL_TIM_IC_GetFilter(), LL_TIM_IC_GetPolarity(), LL_TIM_IC_GetPrescaler(), LL_TIM_IC_SetActiveInput(), LL_TIM_IC_SetFilter(), LL_TIM_IC_SetPolarity(), LL_TIM_IC_SetPrescaler(), LL_TIM_OC_ConfigOutput(), LL_TIM_OC_DisableClear(), LL_TIM_OC_DisableFast(), LL_TIM_OC_DisablePreload(), LL_TIM_OC_EnableClear(), LL_TIM_OC_EnableFast(), LL_TIM_OC_EnablePreload(), LL_TIM_OC_GetIdleState(), LL_TIM_OC_GetMode(), LL_TIM_OC_GetPolarity(), LL_TIM_OC_IsEnabledClear(), LL_TIM_OC_IsEnabledFast(), LL_TIM_OC_IsEnabledPreload(), LL_TIM_OC_SetIdleState(), LL_TIM_OC_SetMode(), and LL_TIM_OC_SetPolarity().

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_TIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Time Base configuration structure definition. More...

#include <stm32f3xx_ll_tim.h>

Data Fields

uint16_t | Prescaler
uint32_t | CounterMode
uint32_t | Autoreload
uint32_t | ClockDivision
uint8_t | RepetitionCounter

Detailed Description

TIM Time Base configuration structure definition.

Definition at line 236 of file stm32f3xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_InitTypeDef::Autoreload

Specifies the auto reload value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.

This feature can be modified afterwards using unitary function LL_TIM_SetAutoReload().

Definition at line 248 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint32_t LL_TIM_InitTypeDef::ClockDivision

Specifies the clock division. This parameter can be a value of Clock Division.

This feature can be modified afterwards using unitary function LL_TIM_SetClockDivision().

Definition at line 255 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint32_t LL_TIM_InitTypeDef::CounterMode

Specifies the counter mode. This parameter can be a value of Counter Mode.

This feature can be modified afterwards using unitary function LL_TIM_SetCounterMode().

Definition at line 243 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint16_t LL_TIM_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_SetPrescaler().

Definition at line 238 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint8_t LL_TIM_InitTypeDef::RepetitionCounter

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode This parameter must be a number between 0x00 and 0xFF.

This feature can be modified afterwards using unitary function LL_TIM_SetRepetitionCounter().

Definition at line 260 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_tim.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_TIM_OC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_OC_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Output Compare configuration structure definition. More...

#include <stm32f3xx_ll_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | OCState
uint32_t | OCNState
uint32_t | CompareValue
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCIdleState
uint32_t | OCNIdleState

Detailed Description

TIM Output Compare configuration structure definition.

Definition at line 274 of file stm32f3xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_OC_InitTypeDef::CompareValue

Specifies the Compare value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).

Definition at line 291 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

uint32_t LL_TIM_OC_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of Output Configuration Idle State.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetIdleState().

Definition at line 307 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

uint32_t LL_TIM_OC_InitTypeDef::OCMode

Specifies the output mode. This parameter can be a value of Output Configuration Mode.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetMode().

Definition at line 276 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of Output Configuration Idle State.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetIdleState().

Definition at line 312 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of Output Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetPolarity().

Definition at line 301 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNState

Specifies the TIM complementary Output Compare state. This parameter can be a value of Output Configuration State.

This feature can be modified afterwards using unitary functions LL_TIM_CC_EnableChannel() or LL_TIM_CC_DisableChannel().

Definition at line 286 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

uint32_t LL_TIM_OC_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of Output Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetPolarity().

Definition at line 296 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

uint32_t LL_TIM_OC_InitTypeDef::OCState

Specifies the TIM Output Compare state. This parameter can be a value of Output Configuration State.

This feature can be modified afterwards using unitary functions LL_TIM_CC_EnableChannel() or LL_TIM_CC_DisableChannel().

Definition at line 281 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_tim.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_TIM_IC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_IC_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Input Capture configuration structure definition. More...

#include <stm32f3xx_ll_tim.h>

Data Fields

uint32_t | ICPolarity
uint32_t | ICActiveInput
uint32_t | ICPrescaler
uint32_t | ICFilter

Detailed Description

TIM Input Capture configuration structure definition.

Definition at line 322 of file stm32f3xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_IC_InitTypeDef::ICActiveInput

Specifies the input. This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 330 of file stm32f3xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 340 of file stm32f3xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 325 of file stm32f3xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 335 of file stm32f3xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_tim.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_TIM_ENCODER_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_ENCODER_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Encoder interface configuration structure definition. More...

#include <stm32f3xx_ll_tim.h>

Data Fields

uint32_t | EncoderMode
uint32_t | IC1Polarity
uint32_t | IC1ActiveInput
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | IC2Polarity
uint32_t | IC2ActiveInput
uint32_t | IC2Prescaler
uint32_t | IC2Filter

Detailed Description

TIM Encoder interface configuration structure definition.

Definition at line 350 of file stm32f3xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_ENCODER_InitTypeDef::EncoderMode

Specifies the encoder resolution (x2 or x4). This parameter can be a value of Encoder Mode.

This feature can be modified afterwards using unitary function LL_TIM_SetEncoderMode().

Definition at line 352 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput

Specifies the TI1 input source This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 362 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Filter

Specifies the TI1 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 372 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Polarity

Specifies the active edge of TI1 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 357 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Prescaler

Specifies the TI1 input prescaler value. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 367 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput

Specifies the TI2 input source This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 382 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Filter

Specifies the TI2 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 392 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Polarity

Specifies the active edge of TI2 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 377 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Prescaler

Specifies the TI2 input prescaler value. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 387 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_tim.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_TIM_HALLSENSOR_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_HALLSENSOR_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Hall sensor interface configuration structure definition. More...

#include <stm32f3xx_ll_tim.h>

Data Fields

uint32_t | IC1Polarity
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | CommutationDelay

Detailed Description

TIM Hall sensor interface configuration structure definition.

Definition at line 402 of file stm32f3xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay

Specifies the compare value to be loaded into the Capture Compare Register. A positive pulse (TRGO event) is generated with a programmable delay every time a change occurs on the Hall inputs. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCH2().

Definition at line 422 of file stm32f3xx_ll_tim.h.

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter

Specifies the TI1 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 417 of file stm32f3xx_ll_tim.h.

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity

Specifies the active edge of TI1 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 405 of file stm32f3xx_ll_tim.h.

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler

Specifies the TI1 input prescaler value. Prescaler must be set to get a maximum counter period longer than the time interval between 2 consecutive changes on the Hall inputs. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 410 of file stm32f3xx_ll_tim.h.

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_tim.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_TIM_BDTR_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_BDTR_InitTypeDef Struct Reference
TIM Exported Init structure

BDTR (Break and Dead Time) structure definition. More...

#include <stm32f3xx_ll_tim.h>

Data Fields

uint32_t | OSSRState
uint32_t | OSSIState
uint32_t | LockLevel
uint8_t | DeadTime
uint16_t | BreakState
uint32_t | BreakPolarity
uint32_t | AutomaticOutput

Detailed Description

BDTR (Break and Dead Time) structure definition.

Definition at line 433 of file stm32f3xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_BDTR_InitTypeDef::AutomaticOutput

Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of Automatic output enable

This feature can be modified afterwards using unitary functions LL_TIM_EnableAutomaticOutput() or LL_TIM_DisableAutomaticOutput()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 509 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::BreakPolarity

Specifies the TIM Break Input pin polarity. This parameter can be a value of break polarity

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 470 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint16_t LL_TIM_BDTR_InitTypeDef::BreakState

Specifies whether the TIM Break input is enabled or not. This parameter can be a value of Break Enable

This feature can be modified afterwards using unitary functions LL_TIM_EnableBRK() or LL_TIM_DisableBRK()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 463 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint8_t LL_TIM_BDTR_InitTypeDef::DeadTime

Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetDeadTime()

Note:
This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed.

Definition at line 455 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::LockLevel

Specifies the LOCK level parameters. This parameter can be a value of Lock Level

Note:
The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.

Definition at line 449 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::OSSIState

Specifies the Off-State used in Idle state. This parameter can be a value of OSSI

This feature can be modified afterwards using unitary function LL_TIM_SetOffStates()

Note:
This bit-field cannot be modified as long as LOCK level 2 has been programmed.

Definition at line 442 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::OSSRState

Specifies the Off-State selection used in Run mode. This parameter can be a value of OSSR

This feature can be modified afterwards using unitary function LL_TIM_SetOffStates()

Note:
This bit-field cannot be modified as long as LOCK level 2 has been programmed.

Definition at line 435 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_tim.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
TIM Exported Constants

Flags defines which can be used with LL_TIM_ReadReg function. More...

Defines

#define | LL_TIM_SR_UIF TIM_SR_UIF
#define | LL_TIM_SR_CC1IF TIM_SR_CC1IF
#define | LL_TIM_SR_CC2IF TIM_SR_CC2IF
#define | LL_TIM_SR_CC3IF TIM_SR_CC3IF
#define | LL_TIM_SR_CC4IF TIM_SR_CC4IF
#define | LL_TIM_SR_COMIF TIM_SR_COMIF
#define | LL_TIM_SR_TIF TIM_SR_TIF
#define | LL_TIM_SR_BIF TIM_SR_BIF
#define | LL_TIM_SR_B2IF TIM_SR_B2IF
#define | LL_TIM_SR_CC1OF TIM_SR_CC1OF
#define | LL_TIM_SR_CC2OF TIM_SR_CC2OF
#define | LL_TIM_SR_CC3OF TIM_SR_CC3OF
#define | LL_TIM_SR_CC4OF TIM_SR_CC4OF

Detailed Description

Flags defines which can be used with LL_TIM_ReadReg function.

Define Documentation

#define LL_TIM_SR_B2IF TIM_SR_B2IF

Second break interrupt flag

Definition at line 543 of file stm32f3xx_ll_tim.h.

#define LL_TIM_SR_BIF TIM_SR_BIF

Break interrupt flag

Definition at line 542 of file stm32f3xx_ll_tim.h.

#define LL_TIM_SR_CC1IF TIM_SR_CC1IF

Capture/compare 1 interrupt flag

Definition at line 532 of file stm32f3xx_ll_tim.h.

#define LL_TIM_SR_CC1OF TIM_SR_CC1OF

Capture/Compare 1 overcapture flag

Definition at line 544 of file stm32f3xx_ll_tim.h.

#define LL_TIM_SR_CC2IF TIM_SR_CC2IF

Capture/compare 2 interrupt flag

Definition at line 533 of file stm32f3xx_ll_tim.h.

#define LL_TIM_SR_CC2OF TIM_SR_CC2OF

Capture/Compare 2 overcapture flag

Definition at line 545 of file stm32f3xx_ll_tim.h.

#define LL_TIM_SR_CC3IF TIM_SR_CC3IF

Capture/compare 3 interrupt flag

Definition at line 534 of file stm32f3xx_ll_tim.h.

#define LL_TIM_SR_CC3OF TIM_SR_CC3OF

Capture/Compare 3 overcapture flag

Definition at line 546 of file stm32f3xx_ll_tim.h.

#define LL_TIM_SR_CC4IF TIM_SR_CC4IF

Capture/compare 4 interrupt flag

Definition at line 535 of file stm32f3xx_ll_tim.h.

#define LL_TIM_SR_CC4OF TIM_SR_CC4OF

Capture/Compare 4 overcapture flag

Definition at line 547 of file stm32f3xx_ll_tim.h.

#define LL_TIM_SR_COMIF TIM_SR_COMIF

COM interrupt flag

Definition at line 540 of file stm32f3xx_ll_tim.h.

#define LL_TIM_SR_TIF TIM_SR_TIF

Trigger interrupt flag

Definition at line 541 of file stm32f3xx_ll_tim.h.

#define LL_TIM_SR_UIF TIM_SR_UIF

Update interrupt flag

Definition at line 531 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: Break Enable

Defines
Break Enable
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_DISABLE 0x00000000U
#define | LL_TIM_BREAK_ENABLE TIM_BDTR_BKE

Define Documentation

#define LL_TIM_BREAK_DISABLE 0x00000000U

Break function disabled

Definition at line 556 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE

Break function enabled

Definition at line 557 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Automatic output enable

Defines
Automatic output enable
TIM Exported Constants

Defines

#define | LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

Define Documentation

#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U

MOE can be set only by software

Definition at line 576 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

MOE can be set by software or automatically at the next update event

Definition at line 577 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IT Defines

Defines
IT Defines
TIM Exported Constants

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. More...

Defines

#define | LL_TIM_DIER_UIE TIM_DIER_UIE
#define | LL_TIM_DIER_CC1IE TIM_DIER_CC1IE
#define | LL_TIM_DIER_CC2IE TIM_DIER_CC2IE
#define | LL_TIM_DIER_CC3IE TIM_DIER_CC3IE
#define | LL_TIM_DIER_CC4IE TIM_DIER_CC4IE
#define | LL_TIM_DIER_COMIE TIM_DIER_COMIE
#define | LL_TIM_DIER_TIE TIM_DIER_TIE
#define | LL_TIM_DIER_BIE TIM_DIER_BIE

Detailed Description

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.

Define Documentation

#define LL_TIM_DIER_BIE TIM_DIER_BIE

Break interrupt enable

Definition at line 594 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE

Capture/compare 1 interrupt enable

Definition at line 588 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE

Capture/compare 2 interrupt enable

Definition at line 589 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE

Capture/compare 3 interrupt enable

Definition at line 590 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE

Capture/compare 4 interrupt enable

Definition at line 591 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DIER_COMIE TIM_DIER_COMIE

COM interrupt enable

Definition at line 592 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DIER_TIE TIM_DIER_TIE

Trigger interrupt enable

Definition at line 593 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DIER_UIE TIM_DIER_UIE

Update interrupt enable

Definition at line 587 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: Update Source

Defines
Update Source
TIM Exported Constants

Defines

#define | LL_TIM_UPDATESOURCE_REGULAR 0x00000000U
#define | LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS

Define Documentation

#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS

Only counter overflow/underflow generates an update request

Definition at line 603 of file stm32f3xx_ll_tim.h.

#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U

Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request

Definition at line 602 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: One Pulse Mode

Defines
One Pulse Mode
TIM Exported Constants

Defines

#define | LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM
#define | LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U

Define Documentation

#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U

Counter stops counting at the next update event

Definition at line 612 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM

Counter is not stopped at update event

Definition at line 611 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: Counter Mode

Defines
Counter Mode
TIM Exported Constants

Defines

#define | LL_TIM_COUNTERMODE_UP 0x00000000U
#define | LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0
#define | LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1
#define | LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS

Define Documentation

#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up

Definition at line 623 of file stm32f3xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down.

Definition at line 622 of file stm32f3xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down.

Definition at line 624 of file stm32f3xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR

Counter used as downcounter

Definition at line 621 of file stm32f3xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_UP 0x00000000U

Counter used as upcounter

Definition at line 620 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_StructInit().

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Clock Division

Defines
Clock Division
TIM Exported Constants

Defines

#define | LL_TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

Define Documentation

#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U

tDTS=tCK_INT

Definition at line 632 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_StructInit().

#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0

tDTS=2*tCK_INT

Definition at line 633 of file stm32f3xx_ll_tim.h.

#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

tDTS=4*tCK_INT

Definition at line 634 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: Counter Direction

Defines
Counter Direction
TIM Exported Constants

Defines

#define | LL_TIM_COUNTERDIRECTION_UP 0x00000000U
#define | LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR

Define Documentation

#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR

Timer counter counts down

Definition at line 643 of file stm32f3xx_ll_tim.h.

#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U

Timer counter counts up

Definition at line 642 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: Capture Compare Update Source

Defines
Capture Compare Update Source
TIM Exported Constants

Defines

#define | LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U
#define | LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS

Define Documentation

#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS

Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI)

Definition at line 652 of file stm32f3xx_ll_tim.h.

#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U

Capture/compare control bits are updated by setting the COMG bit only

Definition at line 651 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: Capture Compare DMA Request

Defines
Capture Compare DMA Request
TIM Exported Constants

Defines

#define | LL_TIM_CCDMAREQUEST_CC 0x00000000U
#define | LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

Define Documentation

#define LL_TIM_CCDMAREQUEST_CC 0x00000000U

CCx DMA request sent when CCx event occurs

Definition at line 660 of file stm32f3xx_ll_tim.h.

#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

CCx DMA requests sent when update event occurs

Definition at line 661 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: Lock Level

Defines
Lock Level
TIM Exported Constants

Defines

#define | LL_TIM_LOCKLEVEL_OFF 0x00000000U
#define | LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

Define Documentation

#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0

LOCK Level 1

Definition at line 670 of file stm32f3xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1

LOCK Level 2

Definition at line 671 of file stm32f3xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

LOCK Level 3

Definition at line 672 of file stm32f3xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_OFF 0x00000000U

LOCK OFF - No bit is write protected

Definition at line 669 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Channel

Defines
Channel
TIM Exported Constants

Defines

#define | LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E
#define | LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE
#define | LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E
#define | LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE
#define | LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E
#define | LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE
#define | LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E

Define Documentation

#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E

Timer input/output channel 1

Definition at line 691 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE

Timer complementary output channel 1

Definition at line 692 of file stm32f3xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E

Timer input/output channel 2

Definition at line 693 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE

Timer complementary output channel 2

Definition at line 694 of file stm32f3xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E

Timer input/output channel 3

Definition at line 695 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE

Timer complementary output channel 3

Definition at line 696 of file stm32f3xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E

Timer input/output channel 4

Definition at line 697 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

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STM32F373xC HAL User Manual: Output Configuration State

Defines
Output Configuration State
TIM Exported Constants

Defines

#define | LL_TIM_OCSTATE_DISABLE 0x00000000U
#define | LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E

Define Documentation

#define LL_TIM_OCSTATE_DISABLE 0x00000000U

OCx is not active

Definition at line 707 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E

OCx signal is output on the corresponding output pin

Definition at line 708 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: Output Configuration Mode

Defines
Output Configuration Mode
TIM Exported Constants

Defines

#define | LL_TIM_OCMODE_FROZEN 0x00000000U
#define | LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

Define Documentation

#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0

OCyREF is forced high on compare match

Definition at line 718 of file stm32f3xx_ll_tim.h.

#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)

OCyREF is forced high

Definition at line 722 of file stm32f3xx_ll_tim.h.

#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2

OCyREF is forced low

Definition at line 721 of file stm32f3xx_ll_tim.h.

#define LL_TIM_OCMODE_FROZEN 0x00000000U

The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level

Definition at line 717 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1

OCyREF is forced low on compare match

Definition at line 719 of file stm32f3xx_ll_tim.h.

#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)

In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.

Definition at line 723 of file stm32f3xx_ll_tim.h.

#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive

Definition at line 724 of file stm32f3xx_ll_tim.h.

#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

OCyREF toggles on compare match

Definition at line 720 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: Output Configuration Polarity

Defines
Output Configuration Polarity
TIM Exported Constants

Defines

#define | LL_TIM_OCPOLARITY_HIGH 0x00000000U
#define | LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P

Define Documentation

#define LL_TIM_OCPOLARITY_HIGH 0x00000000U

OCxactive high

Definition at line 744 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P

OCxactive low

Definition at line 745 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: Output Configuration Idle State

Defines
Output Configuration Idle State
TIM Exported Constants

Defines

#define | LL_TIM_OCIDLESTATE_LOW 0x00000000U
#define | LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1

Define Documentation

#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1

OCx=1 (after a dead-time if OC is implemented) when MOE=0

Definition at line 754 of file stm32f3xx_ll_tim.h.

#define LL_TIM_OCIDLESTATE_LOW 0x00000000U

OCx=0 (after a dead-time if OC is implemented) when MOE=0

Definition at line 753 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Active Input Selection

Defines
Active Input Selection
TIM Exported Constants

Defines

#define | LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)
#define | LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)
#define | LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)

Define Documentation

#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)

ICx is mapped on TIx

Definition at line 775 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)

ICx is mapped on TIy

Definition at line 776 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)

ICx is mapped on TRC

Definition at line 777 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: Input Configuration Prescaler

Defines
Input Configuration Prescaler
TIM Exported Constants

Defines

#define | LL_TIM_ICPSC_DIV1 0x00000000U
#define | LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)
#define | LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)
#define | LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)

Define Documentation

#define LL_TIM_ICPSC_DIV1 0x00000000U

No prescaler, capture is done each time an edge is detected on the capture input

Definition at line 785 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)

Capture is done once every 2 events

Definition at line 786 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)

Capture is done once every 4 events

Definition at line 787 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)

Capture is done once every 8 events

Definition at line 788 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: Input Configuration Filter

Defines
Input Configuration Filter
TIM Exported Constants

Defines

#define | LL_TIM_IC_FILTER_FDIV1 0x00000000U
#define | LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)

Define Documentation

#define LL_TIM_IC_FILTER_FDIV1 0x00000000U

No filter, sampling is done at fDTS

Definition at line 796 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/16, N=5

Definition at line 806 of file stm32f3xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/16, N=6

Definition at line 807 of file stm32f3xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)

fSAMPLING=fDTS/16, N=8

Definition at line 808 of file stm32f3xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)

fSAMPLING=fCK_INT, N=2

Definition at line 797 of file stm32f3xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)

fSAMPLING=fCK_INT, N=4

Definition at line 798 of file stm32f3xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fCK_INT, N=8

Definition at line 799 of file stm32f3xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)

fSAMPLING=fDTS/2, N=6

Definition at line 800 of file stm32f3xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/2, N=8

Definition at line 801 of file stm32f3xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/32, N=5

Definition at line 809 of file stm32f3xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/32, N=6

Definition at line 810 of file stm32f3xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)

fSAMPLING=fDTS/32, N=8

Definition at line 811 of file stm32f3xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/4, N=6

Definition at line 802 of file stm32f3xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/4, N=8

Definition at line 803 of file stm32f3xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)

fSAMPLING=fDTS/8, N=6

Definition at line 804 of file stm32f3xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/8, N=8

Definition at line 805 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: Input Configuration Polarity

Defines
Input Configuration Polarity
TIM Exported Constants

Defines

#define | LL_TIM_IC_POLARITY_RISING 0x00000000U
#define | LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P
#define | LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Define Documentation

#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted

Definition at line 821 of file stm32f3xx_ll_tim.h.

#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P

The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted

Definition at line 820 of file stm32f3xx_ll_tim.h.

#define LL_TIM_IC_POLARITY_RISING 0x00000000U

The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted

Definition at line 819 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), and LL_TIM_IC_StructInit().

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STM32F373xC HAL User Manual: Clock Source

Defines
Clock Source
TIM Exported Constants

Defines

#define | LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U
#define | LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE

Define Documentation

#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Counter counts at each rising or falling edge on a selected inpu t

Definition at line 830 of file stm32f3xx_ll_tim.h.

#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE

Counter counts at each rising or falling edge on the external trigger input ETR

Definition at line 831 of file stm32f3xx_ll_tim.h.

#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U

The timer is clocked by the internal clock provided from the RCC

Definition at line 829 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: Encoder Mode

Defines
Encoder Mode
TIM Exported Constants

Defines

#define | LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0
#define | LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1
#define | LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Define Documentation

#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0

Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level

Definition at line 839 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit().

#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1

Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level

Definition at line 840 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l

Definition at line 841 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: Trigger Output

Defines
Trigger Output
TIM Exported Constants

Defines

#define | LL_TIM_TRGO_RESET 0x00000000U
#define | LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

Define Documentation

#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

CC1 capture or a compare match is used as trigger output

Definition at line 852 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0

Counter Enable signal (CNT_EN) is used as trigger output

Definition at line 850 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2

OC1REF signal is used as trigger output

Definition at line 853 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)

OC2REF signal is used as trigger output

Definition at line 854 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)

OC3REF signal is used as trigger output

Definition at line 855 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

OC4REF signal is used as trigger output

Definition at line 856 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TRGO_RESET 0x00000000U

UG bit from the TIMx_EGR register is used as trigger output

Definition at line 849 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1

Update event is used as trigger output

Definition at line 851 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: Slave Mode

Defines
Slave Mode
TIM Exported Constants

Defines

#define | LL_TIM_SLAVEMODE_DISABLED 0x00000000U
#define | LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)

Define Documentation

#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U

Slave mode disabled

Definition at line 889 of file stm32f3xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)

Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high

Definition at line 891 of file stm32f3xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2

Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter

Definition at line 890 of file stm32f3xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)

Trigger Mode - The counter starts at a rising edge of the trigger TRGI

Definition at line 892 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Trigger Selection

Defines
Trigger Selection
TIM Exported Constants

Defines

#define | LL_TIM_TS_ITR0 0x00000000U
#define | LL_TIM_TS_ITR1 TIM_SMCR_TS_0
#define | LL_TIM_TS_ITR2 TIM_SMCR_TS_1
#define | LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)

Define Documentation

#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)

Filtered external Trigger (ETRF) is used as trigger input

Definition at line 910 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TS_ITR0 0x00000000U

Internal Trigger 0 (ITR0) is used as trigger input

Definition at line 903 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0

Internal Trigger 1 (ITR1) is used as trigger input

Definition at line 904 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1

Internal Trigger 2 (ITR2) is used as trigger input

Definition at line 905 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)

Internal Trigger 3 (ITR3) is used as trigger input

Definition at line 906 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2

TI1 Edge Detector (TI1F_ED) is used as trigger input

Definition at line 907 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)

Filtered Timer Input 1 (TI1FP1) is used as trigger input

Definition at line 908 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)

Filtered Timer Input 2 (TI12P2) is used as trigger input

Definition at line 909 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: External Trigger Polarity

Defines
External Trigger Polarity
TIM Exported Constants

Defines

#define | LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U
#define | LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP

Define Documentation

#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP

ETR is inverted, active at low level or falling edge

Definition at line 919 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U

ETR is non-inverted, active at high level or rising edge

Definition at line 918 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: External Trigger Prescaler

Defines
External Trigger Prescaler
TIM Exported Constants

Defines

#define | LL_TIM_ETR_PRESCALER_DIV1 0x00000000U
#define | LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS

Define Documentation

#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U

ETR prescaler OFF

Definition at line 927 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0

ETR frequency is divided by 2

Definition at line 928 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1

ETR frequency is divided by 4

Definition at line 929 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS

ETR frequency is divided by 8

Definition at line 930 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: External Trigger Filter

Defines
External Trigger Filter
TIM Exported Constants

Defines

#define | LL_TIM_ETR_FILTER_FDIV1 0x00000000U
#define | LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0
#define | LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1
#define | LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2
#define | LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3
#define | LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)
#define | LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF

Define Documentation

#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U

No filter, sampling is done at fDTS

Definition at line 938 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/16, N=6

Definition at line 948 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/16, N=8

Definition at line 949 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)

fSAMPLING=fDTS/16, N=5

Definition at line 950 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0

fSAMPLING=fCK_INT, N=2

Definition at line 939 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1

fSAMPLING=fCK_INT, N=4

Definition at line 940 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fCK_INT, N=8

Definition at line 941 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2

fSAMPLING=fDTS/2, N=6

Definition at line 942 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/2, N=8

Definition at line 943 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/32, N=5

Definition at line 951 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/32, N=6

Definition at line 952 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF

fSAMPLING=fDTS/32, N=8

Definition at line 953 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/4, N=6

Definition at line 944 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/4, N=8

Definition at line 945 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3

fSAMPLING=fDTS/8, N=8

Definition at line 946 of file stm32f3xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/16, N=5

Definition at line 947 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: break polarity

Defines
break polarity
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP

Define Documentation

#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP

Break input BRK is active high

Definition at line 963 of file stm32f3xx_ll_tim.h.

#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U

Break input BRK is active low

Definition at line 962 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: OSSI

Defines
OSSI
TIM Exported Constants

Defines

#define | LL_TIM_OSSI_DISABLE 0x00000000U
#define | LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI

Define Documentation

#define LL_TIM_OSSI_DISABLE 0x00000000U

When inactive, OCx/OCxN outputs are disabled

Definition at line 1032 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI

When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime

Definition at line 1033 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: OSSR

Defines
OSSR
TIM Exported Constants

Defines

#define | LL_TIM_OSSR_DISABLE 0x00000000U
#define | LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR

Define Documentation

#define LL_TIM_OSSR_DISABLE 0x00000000U

When inactive, OCx/OCxN outputs are disabled

Definition at line 1041 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR

When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1

Definition at line 1042 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Burst Base Address

Defines
DMA Burst Base Address
TIM Exported Constants

Defines

#define | LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U
#define | LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0
#define | LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1
#define | LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2
#define | LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3
#define | LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4
#define | LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

Define Documentation

#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_ARR register is the DMA base address for DMA burst

Definition at line 1062 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)

TIMx_BDTR register is the DMA base address for DMA burst

Definition at line 1068 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3

TIMx_CCER register is the DMA base address for DMA burst

Definition at line 1059 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_CCMR1 register is the DMA base address for DMA burst

Definition at line 1057 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCMR2 register is the DMA base address for DMA burst

Definition at line 1058 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)

TIMx_CCMR3 register is the DMA base address for DMA burst

Definition at line 1069 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_CCR1 register is the DMA base address for DMA burst

Definition at line 1064 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_CCR2 register is the DMA base address for DMA burst

Definition at line 1065 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCR3 register is the DMA base address for DMA burst

Definition at line 1066 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4

TIMx_CCR4 register is the DMA base address for DMA burst

Definition at line 1067 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)

TIMx_CNT register is the DMA base address for DMA burst

Definition at line 1060 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U

TIMx_CR1 register is the DMA base address for DMA burst

Definition at line 1051 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0

TIMx_CR2 register is the DMA base address for DMA burst

Definition at line 1052 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_DIER register is the DMA base address for DMA burst

Definition at line 1054 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_EGR register is the DMA base address for DMA burst

Definition at line 1056 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_OR register is the DMA base address for DMA burst

Definition at line 1074 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)

TIMx_PSC register is the DMA base address for DMA burst

Definition at line 1061 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)

TIMx_RCR register is the DMA base address for DMA burst

Definition at line 1063 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1

TIMx_SMCR register is the DMA base address for DMA burst

Definition at line 1053 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2

TIMx_SR register is the DMA base address for DMA burst

Definition at line 1055 of file stm32f3xx_ll_tim.h.

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STM32F373xC HAL User Manual: DMA Burst Length

Defines
DMA Burst Length
TIM Exported Constants

Defines

#define | LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U
#define | LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0
#define | LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1
#define | LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2
#define | LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3
#define | LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)
#define | LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4
#define | LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)

Define Documentation

#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)

Transfer is done to 10 registers starting from the DMA burst base address

Definition at line 1091 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)

Transfer is done to 11 registers starting from the DMA burst base address

Definition at line 1092 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 12 registers starting from the DMA burst base address

Definition at line 1093 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)

Transfer is done to 13 registers starting from the DMA burst base address

Definition at line 1094 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)

Transfer is done to 14 registers starting from the DMA burst base address

Definition at line 1095 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)

Transfer is done to 15 registers starting from the DMA burst base address

Definition at line 1096 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 16 registers starting from the DMA burst base address

Definition at line 1097 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4

Transfer is done to 17 registers starting from the DMA burst base address

Definition at line 1098 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)

Transfer is done to 18 registers starting from the DMA burst base address

Definition at line 1099 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U

Transfer is done to 1 register starting from the DMA burst base address

Definition at line 1082 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0

Transfer is done to 2 registers starting from the DMA burst base address

Definition at line 1083 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1

Transfer is done to 3 registers starting from the DMA burst base address

Definition at line 1084 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 4 registers starting from the DMA burst base address

Definition at line 1085 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2

Transfer is done to 5 registers starting from the DMA burst base address

Definition at line 1086 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)

Transfer is done to 6 registers starting from the DMA burst base address

Definition at line 1087 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)

Transfer is done to 7 registers starting from the DMA burst base address

Definition at line 1088 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 1 registers starting from the DMA burst base address

Definition at line 1089 of file stm32f3xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3

Transfer is done to 9 registers starting from the DMA burst base address

Definition at line 1090 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM16 External Input Ch1 Remap

Defines
TIM16 External Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK)
#define | LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR_TI1_RMP_1 | TIM16_OR_RMP_MASK)
#define | LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR_TI1_RMP_1 | TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK)

Define Documentation

#define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U

TIM16 input capture 1 is connected to GPIO

Definition at line 1166 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR_TI1_RMP_1 | TIM16_OR_RMP_MASK)

TIM16 input capture 1 is connected to HSE/32 clock

Definition at line 1168 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR_TI1_RMP_1 | TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK)

TIM16 input capture 1 is connected to MCO

Definition at line 1169 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK)

TIM16 input capture 1 is connected to RTC wakeup interrupt

Definition at line 1167 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM14 Timer Input1 Remap

Defines
TIM14 Timer Input1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM14_TI1_RMP_GPIO TIM14_OR_RMP_MASK
#define | LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 | TIM14_OR_RMP_MASK)
#define | LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK)
#define | LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 | TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK)

Define Documentation

#define LL_TIM_TIM14_TI1_RMP_GPIO TIM14_OR_RMP_MASK

TIM14_TI1 is connected to GPIO

Definition at line 1201 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK)

TIM14_TI1 is connected to HSE/32

Definition at line 1203 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 | TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK)

TIM14_TI1 is connected to MCO

Definition at line 1204 of file stm32f3xx_ll_tim.h.

#define LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 | TIM14_OR_RMP_MASK)

TIM14_TI1 is connected to RTC Clock

Definition at line 1202 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
TIM Exported Macros

Defines

#define | LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in TIM register.
#define | LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in TIM register.

Define Documentation

#define LL_TIM_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in TIM register.

Parameters:
__INSTANCE__ | TIM Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 1248 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

#define LL_TIM_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in TIM register.

Parameters:
__INSTANCE__ | TIM Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 1240 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), LL_TIM_ENCODER_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Exported_Macros

Defines
Exported_Macros
TIM Exported Macros

Defines

#define | __LL_TIM_GETFLAG_UIFCPY(__CNT__) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
HELPER macro retrieving the UIFCPY flag from the counter value.
#define | __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)
HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
#define | __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
#define | __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
#define | __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
#define | __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
HELPER macro retrieving the ratio of the input capture prescaler.

Define Documentation

#define __LL_TIM_CALC_ARR | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __FREQ__
 | ) | (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U

HELPER macro calculating the auto-reload value to achieve the required output signal frequency.

Note:
ex: __LL_TIM_CALC_ARR (1000000, LL_TIM_GetPrescaler (), 10000);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__FREQ__ | output signal frequency (in Hz)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 1303 of file stm32f3xx_ll_tim.h.

#define __LL_TIM_CALC_DEADTIME | ( | __TIMCLK__,
 |  | __CKD__,
 |  | __DT__
 | ) |
Value:
( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))           ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :                                               \
      (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
      (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
      (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
       0U)

HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.

Note:
ex: __LL_TIM_CALC_DEADTIME (80000000, LL_TIM_GetClockDivision (), 120);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__CKD__ This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
__DT__ | deadtime duration (in ns)
Return values:
DTG[0:7]

Definition at line 1278 of file stm32f3xx_ll_tim.h.

#define __LL_TIM_CALC_DELAY | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__
 | ) |
Value:
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
          / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))

HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.

Note:
ex: __LL_TIM_CALC_DELAY (1000000, LL_TIM_GetPrescaler (), 10);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
Return values:
Compare value (between Min_Data=0 and Max_Data=65535)

Definition at line 1314 of file stm32f3xx_ll_tim.h.

#define __LL_TIM_CALC_PSC | ( | __TIMCLK__,
 |  | __CNTCLK__
 | ) | ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U

HELPER macro calculating the prescaler value to achieve the required counter clock frequency.

Note:
ex: __LL_TIM_CALC_PSC (80000000, 1000000);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__CNTCLK__ | counter clock frequency (in Hz)
Return values:
Prescaler value (between Min_Data=0 and Max_Data=65535)

Definition at line 1292 of file stm32f3xx_ll_tim.h.

#define __LL_TIM_CALC_PULSE | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__,
 |  | __PULSE__
 | ) |
Value:
((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
           + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))

HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).

Note:
ex: __LL_TIM_CALC_PULSE (1000000, LL_TIM_GetPrescaler (), 10, 20);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
__PULSE__ | pulse duration (in us)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 1327 of file stm32f3xx_ll_tim.h.

#define __LL_TIM_GET_ICPSC_RATIO ( __ICPSC__ ) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))

HELPER macro retrieving the ratio of the input capture prescaler.

Note:
ex: __LL_TIM_GET_ICPSC_RATIO (LL_TIM_IC_GetPrescaler ());
Parameters:
__ICPSC__ This parameter can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8
Return values:
Input capture prescaler ratio (1, 2, 4 or 8)

Definition at line 1341 of file stm32f3xx_ll_tim.h.

#define __LL_TIM_GETFLAG_UIFCPY ( __CNT__ ) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)

HELPER macro retrieving the UIFCPY flag from the counter value.

Note:
ex: __LL_TIM_GETFLAG_UIFCPY (LL_TIM_GetCounter ());
Relevant only if UIF flag remapping has been enabled (UIF status bit is copied to TIMx_CNT register bit 31)
Parameters:
__CNT__ Counter value
Return values:
UIF status bit

Definition at line 1264 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Time Base configuration

Functions
Time Base configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableCounter (TIM_TypeDef *TIMx)
Enable timer counter.
__STATIC_INLINE void | LL_TIM_DisableCounter (TIM_TypeDef *TIMx)
Disable timer counter.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledCounter (TIM_TypeDef *TIMx)
Indicates whether the timer counter is enabled.
__STATIC_INLINE void | LL_TIM_EnableUpdateEvent (TIM_TypeDef *TIMx)
Enable update event generation.
__STATIC_INLINE void | LL_TIM_DisableUpdateEvent (TIM_TypeDef *TIMx)
Disable update event generation.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledUpdateEvent (TIM_TypeDef *TIMx)
Indicates whether update event generation is enabled.
__STATIC_INLINE void | LL_TIM_SetUpdateSource (TIM_TypeDef *TIMx, uint32_t UpdateSource)
Set update event source.
__STATIC_INLINE uint32_t | LL_TIM_GetUpdateSource (TIM_TypeDef *TIMx)
Get actual event update source.
__STATIC_INLINE void | LL_TIM_SetOnePulseMode (TIM_TypeDef *TIMx, uint32_t OnePulseMode)
Set one pulse mode (one shot v.s.
__STATIC_INLINE uint32_t | LL_TIM_GetOnePulseMode (TIM_TypeDef *TIMx)
Get actual one pulse mode.
__STATIC_INLINE void | LL_TIM_SetCounterMode (TIM_TypeDef *TIMx, uint32_t CounterMode)
Set the timer counter counting mode.
__STATIC_INLINE uint32_t | LL_TIM_GetCounterMode (TIM_TypeDef *TIMx)
Get actual counter mode.
__STATIC_INLINE void | LL_TIM_EnableARRPreload (TIM_TypeDef *TIMx)
Enable auto-reload (ARR) preload.
__STATIC_INLINE void | LL_TIM_DisableARRPreload (TIM_TypeDef *TIMx)
Disable auto-reload (ARR) preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledARRPreload (TIM_TypeDef *TIMx)
Indicates whether auto-reload (ARR) preload is enabled.
__STATIC_INLINE void | LL_TIM_SetClockDivision (TIM_TypeDef *TIMx, uint32_t ClockDivision)
Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE uint32_t | LL_TIM_GetClockDivision (TIM_TypeDef *TIMx)
Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE void | LL_TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Set the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetCounter (TIM_TypeDef *TIMx)
Get the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetDirection (TIM_TypeDef *TIMx)
Get the current direction of the counter.
__STATIC_INLINE void | LL_TIM_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Prescaler)
Set the prescaler value.
__STATIC_INLINE uint32_t | LL_TIM_GetPrescaler (TIM_TypeDef *TIMx)
Get the prescaler value.
__STATIC_INLINE void | LL_TIM_SetAutoReload (TIM_TypeDef *TIMx, uint32_t AutoReload)
Set the auto-reload value.
__STATIC_INLINE uint32_t | LL_TIM_GetAutoReload (TIM_TypeDef *TIMx)
Get the auto-reload value.
__STATIC_INLINE void | LL_TIM_SetRepetitionCounter (TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
Set the repetition counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetRepetitionCounter (TIM_TypeDef *TIMx)
Get the repetition counter value.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableARRPreload ( TIM_TypeDef * TIMx )

Disable auto-reload (ARR) preload.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_DisableARRPreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1547 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableCounter ( TIM_TypeDef * TIMx )

Disable timer counter.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_DisableCounter
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1379 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableUpdateEvent ( TIM_TypeDef * TIMx )

Disable update event generation.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_DisableUpdateEvent
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1412 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableARRPreload ( TIM_TypeDef * TIMx )

Enable auto-reload (ARR) preload.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_EnableARRPreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1536 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableCounter ( TIM_TypeDef * TIMx )

Enable timer counter.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_EnableCounter
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1368 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableUpdateEvent ( TIM_TypeDef * TIMx )

Enable update event generation.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_EnableUpdateEvent
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1401 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetAutoReload ( TIM_TypeDef * TIMx )

Get the auto-reload value.

Reference Manual to LL API cross reference:
ARR ARR LL_TIM_GetAutoReload
Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Parameters:
TIMx Timer instance
Return values:
Auto-reload value

Definition at line 1689 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetClockDivision ( TIM_TypeDef * TIMx )

Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.

Note:
Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check whether or not the clock division feature is supported by the timer instance.
Reference Manual to LL API cross reference:
CR1 CKD LL_TIM_GetClockDivision
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4

Definition at line 1593 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetCounter ( TIM_TypeDef * TIMx )

Get the counter value.

Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Reference Manual to LL API cross reference:
CNT CNT LL_TIM_GetCounter
Parameters:
TIMx Timer instance
Return values:
Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)

Definition at line 1620 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetCounterMode ( TIM_TypeDef * TIMx )

Get actual counter mode.

Note:
Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to check whether or not the counter mode selection feature is supported by a timer instance.
Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_GetCounterMode
CR1 CMS LL_TIM_GetCounterMode
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_COUNTERMODE_UP
  • LL_TIM_COUNTERMODE_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP
  • LL_TIM_COUNTERMODE_CENTER_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN

Definition at line 1525 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetDirection ( TIM_TypeDef * TIMx )

Get the current direction of the counter.

Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_GetDirection
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_COUNTERDIRECTION_UP
  • LL_TIM_COUNTERDIRECTION_DOWN

Definition at line 1633 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode ( TIM_TypeDef * TIMx )

Get actual one pulse mode.

Reference Manual to LL API cross reference:
CR1 OPM LL_TIM_GetOnePulseMode
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_ONEPULSEMODE_SINGLE
  • LL_TIM_ONEPULSEMODE_REPETITIVE

Definition at line 1484 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetPrescaler ( TIM_TypeDef * TIMx )

Get the prescaler value.

Reference Manual to LL API cross reference:
PSC PSC LL_TIM_GetPrescaler
Parameters:
TIMx Timer instance
Return values:
Prescaler value between Min_Data=0 and Max_Data=65535

Definition at line 1660 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter ( TIM_TypeDef * TIMx )

Get the repetition counter value.

Note:
Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a repetition counter.
Reference Manual to LL API cross reference:
RCR REP LL_TIM_GetRepetitionCounter
Parameters:
TIMx Timer instance
Return values:
Repetition counter value

Definition at line 1717 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource ( TIM_TypeDef * TIMx )

Get actual event update source.

Reference Manual to LL API cross reference:
CR1 URS LL_TIM_GetUpdateSource
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_UPDATESOURCE_REGULAR
  • LL_TIM_UPDATESOURCE_COUNTER

Definition at line 1457 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload ( TIM_TypeDef * TIMx )

Indicates whether auto-reload (ARR) preload is enabled.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_IsEnabledARRPreload
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1558 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter ( TIM_TypeDef * TIMx )

Indicates whether the timer counter is enabled.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_IsEnabledCounter
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1390 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent ( TIM_TypeDef * TIMx )

Indicates whether update event generation is enabled.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_IsEnabledUpdateEvent
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1423 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetAutoReload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | AutoReload
 | ) |  |

Set the auto-reload value.

Note:
The counter is blocked while the auto-reload value is null.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Helper macro __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
Reference Manual to LL API cross reference:
ARR ARR LL_TIM_SetAutoReload
Parameters:
TIMx | Timer instance
AutoReload | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 1676 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetClockDivision | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ClockDivision
 | ) |  |

Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.

Note:
Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check whether or not the clock division feature is supported by the timer instance.
Reference Manual to LL API cross reference:
CR1 CKD LL_TIM_SetClockDivision
Parameters:
TIMx Timer instance
ClockDivision This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
Return values:
None

Definition at line 1576 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Counter
 | ) |  |

Set the counter value.

Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Reference Manual to LL API cross reference:
CNT CNT LL_TIM_SetCounter
Parameters:
TIMx | Timer instance
Counter | Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
Return values:
None

Definition at line 1607 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetCounterMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CounterMode
 | ) |  |

Set the timer counter counting mode.

Note:
Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to check whether or not the counter mode selection feature is supported by a timer instance.
Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_SetCounterMode
CR1 CMS LL_TIM_SetCounterMode
Parameters:
TIMx Timer instance
CounterMode This parameter can be one of the following values:
  • LL_TIM_COUNTERMODE_UP
  • LL_TIM_COUNTERMODE_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP
  • LL_TIM_COUNTERMODE_CENTER_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN
Return values:
None

Definition at line 1505 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetOnePulseMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OnePulseMode
 | ) |  |

Set one pulse mode (one shot v.s.

repetitive).

Reference Manual to LL API cross reference:
CR1 OPM LL_TIM_SetOnePulseMode
Parameters:
TIMx Timer instance
OnePulseMode This parameter can be one of the following values:
  • LL_TIM_ONEPULSEMODE_SINGLE
  • LL_TIM_ONEPULSEMODE_REPETITIVE
Return values:
None

Definition at line 1471 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Prescaler
 | ) |  |

Set the prescaler value.

Note:
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
The prescaler can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.
Helper macro __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
Reference Manual to LL API cross reference:
PSC PSC LL_TIM_SetPrescaler
Parameters:
TIMx | Timer instance
Prescaler | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 1649 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetRepetitionCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | RepetitionCounter
 | ) |  |

Set the repetition counter value.

Note:
For advanced timer instances RepetitionCounter can be up to 65535 except for STM32F373xC and STM32F378xx devices.
Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a repetition counter.
Reference Manual to LL API cross reference:
RCR REP LL_TIM_SetRepetitionCounter
Parameters:
TIMx | Timer instance
RepetitionCounter | between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 1704 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetUpdateSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | UpdateSource
 | ) |  |

Set update event source.

Note:
Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events generate an update interrupt or DMA request if enabled:
  • Counter overflow/underflow
  • Setting the UG bit
  • Update generation through the slave mode controller
Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Reference Manual to LL API cross reference:
CR1 URS LL_TIM_SetUpdateSource
Parameters:
TIMx Timer instance
UpdateSource This parameter can be one of the following values:
  • LL_TIM_UPDATESOURCE_REGULAR
  • LL_TIM_UPDATESOURCE_COUNTER
Return values:
None

Definition at line 1444 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Capture Compare configuration

Functions
Capture Compare configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_CC_EnablePreload (TIM_TypeDef *TIMx)
Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_DisablePreload (TIM_TypeDef *TIMx)
Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_SetUpdate (TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
__STATIC_INLINE void | LL_TIM_CC_SetDMAReqTrigger (TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
Set the trigger of the capture/compare DMA request.
__STATIC_INLINE uint32_t | LL_TIM_CC_GetDMAReqTrigger (TIM_TypeDef *TIMx)
Get actual trigger of the capture/compare DMA request.
__STATIC_INLINE void | LL_TIM_CC_SetLockLevel (TIM_TypeDef *TIMx, uint32_t LockLevel)
Set the lock level to freeze the configuration of several capture/compare parameters.
__STATIC_INLINE void | LL_TIM_CC_EnableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Enable capture/compare channels.
__STATIC_INLINE void | LL_TIM_CC_DisableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Disable capture/compare channels.
__STATIC_INLINE uint32_t | LL_TIM_CC_IsEnabledChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Indicate whether channel(s) is(are) enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_CC_DisableChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Disable capture/compare channels.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_DisableChannel
CCER CC1NE LL_TIM_CC_DisableChannel
CCER CC2E LL_TIM_CC_DisableChannel
CCER CC2NE LL_TIM_CC_DisableChannel
CCER CC3E LL_TIM_CC_DisableChannel
CCER CC3NE LL_TIM_CC_DisableChannel
CCER CC4E LL_TIM_CC_DisableChannel
CCER CC5E LL_TIM_CC_DisableChannel
CCER CC6E LL_TIM_CC_DisableChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Note:
CH5 and CH6 channels are not available for all F3 devices
Return values:
None

Definition at line 1900 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_DisablePreload ( TIM_TypeDef * TIMx )

Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

Note:
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCPC LL_TIM_CC_DisablePreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1778 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_EnableChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Enable capture/compare channels.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_EnableChannel
CCER CC1NE LL_TIM_CC_EnableChannel
CCER CC2E LL_TIM_CC_EnableChannel
CCER CC2NE LL_TIM_CC_EnableChannel
CCER CC3E LL_TIM_CC_EnableChannel
CCER CC3NE LL_TIM_CC_EnableChannel
CCER CC4E LL_TIM_CC_EnableChannel
CCER CC5E LL_TIM_CC_EnableChannel
CCER CC6E LL_TIM_CC_EnableChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Note:
CH5 and CH6 channels are not available for all F3 devices
Return values:
None

Definition at line 1870 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_EnablePreload ( TIM_TypeDef * TIMx )

Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

Note:
CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs.
Only on channels that have a complementary output.
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCPC LL_TIM_CC_EnablePreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1765 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger ( TIM_TypeDef * TIMx )

Get actual trigger of the capture/compare DMA request.

Reference Manual to LL API cross reference:
CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_CCDMAREQUEST_CC
  • LL_TIM_CCDMAREQUEST_UPDATE

Definition at line 1821 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Indicate whether channel(s) is(are) enabled.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_IsEnabledChannel
CCER CC1NE LL_TIM_CC_IsEnabledChannel
CCER CC2E LL_TIM_CC_IsEnabledChannel
CCER CC2NE LL_TIM_CC_IsEnabledChannel
CCER CC3E LL_TIM_CC_IsEnabledChannel
CCER CC3NE LL_TIM_CC_IsEnabledChannel
CCER CC4E LL_TIM_CC_IsEnabledChannel
CCER CC5E LL_TIM_CC_IsEnabledChannel
CCER CC6E LL_TIM_CC_IsEnabledChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Note:
CH5 and CH6 channels are not available for all F3 devices
Return values:
State of bit (1 or 0).

Definition at line 1930 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DMAReqTrigger
 | ) |  |

Set the trigger of the capture/compare DMA request.

Reference Manual to LL API cross reference:
CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
Parameters:
TIMx Timer instance
DMAReqTrigger This parameter can be one of the following values:
  • LL_TIM_CCDMAREQUEST_CC
  • LL_TIM_CCDMAREQUEST_UPDATE
Return values:
None

Definition at line 1808 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetLockLevel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | LockLevel
 | ) |  |

Set the lock level to freeze the configuration of several capture/compare parameters.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not the lock mechanism is supported by a timer instance.
Reference Manual to LL API cross reference:
BDTR LOCK LL_TIM_CC_SetLockLevel
Parameters:
TIMx Timer instance
LockLevel This parameter can be one of the following values:
  • LL_TIM_LOCKLEVEL_OFF
  • LL_TIM_LOCKLEVEL_1
  • LL_TIM_LOCKLEVEL_2
  • LL_TIM_LOCKLEVEL_3
Return values:
None

Definition at line 1840 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetUpdate | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CCUpdateSource
 | ) |  |

Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).

Note:
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCUS LL_TIM_CC_SetUpdate
Parameters:
TIMx Timer instance
CCUpdateSource This parameter can be one of the following values:
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
Return values:
None

Definition at line 1794 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Output channel configuration

Functions
Output channel configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_OC_ConfigOutput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetMode (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetMode (TIM_TypeDef *TIMx, uint32_t Channel)
Get the output compare mode of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
Set the polarity of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the polarity of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetIdleState (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
Set the IDLE state of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetIdleState (TIM_TypeDef *TIMx, uint32_t Channel)
Get the IDLE state of an output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Enable fast mode for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Disable fast mode for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledFast (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether fast mode is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Enable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Disable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledPreload (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Enable clearing the output channel on an external event.
__STATIC_INLINE void | LL_TIM_OC_DisableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Disable clearing the output channel on an external event.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledClear (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates clearing the output channel on an external event is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_SetDeadTime (TIM_TypeDef *TIMx, uint32_t DeadTime)
Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH1 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 1 (TIMx_CCR1).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH2 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 2 (TIMx_CCR2).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH3 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 3 (TIMx_CCR3).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH4 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 4 (TIMx_CCR4).
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH1 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR1) set for output channel 1.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH2 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR2) set for output channel 2.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH3 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR3) set for output channel 3.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH4 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR4) set for output channel 4.

Function Documentation

__STATIC_INLINE void LL_TIM_OC_ConfigOutput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure an output channel.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_OC_ConfigOutput
CCMR1 CC2S LL_TIM_OC_ConfigOutput
CCMR2 CC3S LL_TIM_OC_ConfigOutput
CCMR2 CC4S LL_TIM_OC_ConfigOutput
CCER CC1P LL_TIM_OC_ConfigOutput
CCER CC2P LL_TIM_OC_ConfigOutput
CCER CC3P LL_TIM_OC_ConfigOutput
CCER CC4P LL_TIM_OC_ConfigOutput
CCER CC5P LL_TIM_OC_ConfigOutput
CCER CC6P LL_TIM_OC_ConfigOutput
CR2 OIS1 LL_TIM_OC_ConfigOutput
CR2 OIS2 LL_TIM_OC_ConfigOutput
CR2 OIS3 LL_TIM_OC_ConfigOutput
CR2 OIS4 LL_TIM_OC_ConfigOutput
CR2 OIS5 LL_TIM_OC_ConfigOutput
CR2 OIS6 LL_TIM_OC_ConfigOutput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Configuration This parameter must be a combination of all the following values:
  • LL_TIM_OCPOLARITY_HIGH or LL_TIM_OCPOLARITY_LOW
  • LL_TIM_OCIDLESTATE_LOW or LL_TIM_OCIDLESTATE_HIGH
Note:
CH3 CH4 CH5 and CH6 channels are not available for all F3 devices
Return values:
None

Definition at line 1984 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisableClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable clearing the output channel on an external event.

Note:
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_DisableClear
CCMR1 OC2CE LL_TIM_OC_DisableClear
CCMR2 OC3CE LL_TIM_OC_DisableClear
CCMR2 OC4CE LL_TIM_OC_DisableClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Note:
OC5CE and OC6CE are not available for all F3 devices
CH5 and CH6 channels are not available for all F3 devices
Return values:
None

Definition at line 2528 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisableFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable fast mode for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_DisableFast
CCMR1 OC2FE LL_TIM_OC_DisableFast
CCMR2 OC3FE LL_TIM_OC_DisableFast
CCMR2 OC4FE LL_TIM_OC_DisableFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Note:
OC5FE and OC6FE are not available for all F3 devices
CH5 and CH6 channels are not available for all F3 devices
Return values:
None

Definition at line 2310 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisablePreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable compare register (TIMx_CCRx) preload for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_DisablePreload
CCMR1 OC2PE LL_TIM_OC_DisablePreload
CCMR2 OC3PE LL_TIM_OC_DisablePreload
CCMR2 OC4PE LL_TIM_OC_DisablePreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Note:
OC5PE and OC6PE are not available for all F3 devices
CH5 and CH6 channels are not available for all F3 devices
Return values:
None

Definition at line 2417 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnableClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable clearing the output channel on an external event.

Note:
This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_EnableClear
CCMR1 OC2CE LL_TIM_OC_EnableClear
CCMR2 OC3CE LL_TIM_OC_EnableClear
CCMR2 OC4CE LL_TIM_OC_EnableClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Note:
OC5CE and OC6CE are not available for all F3 devices
CH5 and CH6 channels are not available for all F3 devices
Return values:
None

Definition at line 2491 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnableFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable fast mode for the output channel.

Note:
Acts only if the channel is configured in PWM1 or PWM2 mode.
Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_EnableFast
CCMR1 OC2FE LL_TIM_OC_EnableFast
CCMR2 OC3FE LL_TIM_OC_EnableFast
CCMR2 OC4FE LL_TIM_OC_EnableFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Note:
OC5FE and OC6FE are not available for all F3 devices
CH5 and CH6 channels are not available for all F3 devices
Return values:
None

Definition at line 2274 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnablePreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable compare register (TIMx_CCRx) preload for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_EnablePreload
CCMR1 OC2PE LL_TIM_OC_EnablePreload
CCMR2 OC3PE LL_TIM_OC_EnablePreload
CCMR2 OC4PE LL_TIM_OC_EnablePreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Note:
OC5PE and OC6PE are not available for all F3 devices
CH5 and CH6 channels are not available for all F3 devices
Return values:
None

Definition at line 2382 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR1) set for output channel 1.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not output channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_OC_GetCompareCH1
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2715 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR2) set for output channel 2.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not output channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_OC_GetCompareCH2
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2731 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR3) set for output channel 3.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not output channel 3 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_OC_GetCompareCH3
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2747 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR4) set for output channel 4.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not output channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_OC_GetCompareCH4
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2763 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the IDLE state of an output channel.

Reference Manual to LL API cross reference:
CR2 OIS1 LL_TIM_OC_GetIdleState
CR2 OIS2N LL_TIM_OC_GetIdleState
CR2 OIS2 LL_TIM_OC_GetIdleState
CR2 OIS2N LL_TIM_OC_GetIdleState
CR2 OIS3 LL_TIM_OC_GetIdleState
CR2 OIS3N LL_TIM_OC_GetIdleState
CR2 OIS4 LL_TIM_OC_GetIdleState
CR2 OIS5 LL_TIM_OC_GetIdleState
CR2 OIS6 LL_TIM_OC_GetIdleState
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Note:
CH5 and CH6 channels are not available for all F3 devices
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCIDLESTATE_LOW
  • LL_TIM_OCIDLESTATE_HIGH

Definition at line 2239 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the output compare mode of an output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1M LL_TIM_OC_GetMode
CCMR1 OC2M LL_TIM_OC_GetMode
CCMR2 OC3M LL_TIM_OC_GetMode
CCMR2 OC4M LL_TIM_OC_GetMode
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Note:
The following OC modes are not available on all F3 devices :
  • LL_TIM_OCMODE_RETRIG_OPM1
  • LL_TIM_OCMODE_RETRIG_OPM2
  • LL_TIM_OCMODE_COMBINED_PWM1
  • LL_TIM_OCMODE_COMBINED_PWM2
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2
CH5 and CH6 channels are not available for all F3 devices
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCMODE_FROZEN
  • LL_TIM_OCMODE_ACTIVE
  • LL_TIM_OCMODE_INACTIVE
  • LL_TIM_OCMODE_TOGGLE
  • LL_TIM_OCMODE_FORCED_INACTIVE
  • LL_TIM_OCMODE_FORCED_ACTIVE
  • LL_TIM_OCMODE_PWM1
  • LL_TIM_OCMODE_PWM2
  • LL_TIM_OCMODE_RETRIG_OPM1
  • LL_TIM_OCMODE_RETRIG_OPM2
  • LL_TIM_OCMODE_COMBINED_PWM1
  • LL_TIM_OCMODE_COMBINED_PWM2
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2

Definition at line 2100 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the polarity of an output channel.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_OC_GetPolarity
CCER CC1NP LL_TIM_OC_GetPolarity
CCER CC2P LL_TIM_OC_GetPolarity
CCER CC2NP LL_TIM_OC_GetPolarity
CCER CC3P LL_TIM_OC_GetPolarity
CCER CC3NP LL_TIM_OC_GetPolarity
CCER CC4P LL_TIM_OC_GetPolarity
CCER CC5P LL_TIM_OC_GetPolarity
CCER CC6P LL_TIM_OC_GetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Note:
CH5 and CH6 channels are not available for all F3 devices
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCPOLARITY_HIGH
  • LL_TIM_OCPOLARITY_LOW

Definition at line 2168 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates clearing the output channel on an external event is enabled for the output channel.

Note:
This function enables clearing the output channel on an external event.
This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_IsEnabledClear
CCMR1 OC2CE LL_TIM_OC_IsEnabledClear
CCMR2 OC3CE LL_TIM_OC_IsEnabledClear
CCMR2 OC4CE LL_TIM_OC_IsEnabledClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Note:
OC5CE and OC6CE are not available for all F3 devices
CH5 and CH6 channels are not available for all F3 devices
Return values:
State of bit (1 or 0).

Definition at line 2567 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates whether fast mode is enabled for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_IsEnabledFast
CCMR1 OC2FE LL_TIM_OC_IsEnabledFast
CCMR2 OC3FE LL_TIM_OC_IsEnabledFast
CCMR2 OC4FE LL_TIM_OC_IsEnabledFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Note:
OC5FE and OC6FE are not available for all F3 devices
CH5 and CH6 channels are not available for all F3 devices
Return values:
State of bit (1 or 0).

Definition at line 2346 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload
CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload
CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload
CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Note:
OC5PE and OC6PE are not available for all F3 devices
CH5 and CH6 channels are not available for all F3 devices
Return values:
State of bit (1 or 0).

Definition at line 2452 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetCompareCH1 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 1 (TIMx_CCR1).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not output channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_OC_SetCompareCH1
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2602 of file stm32f3xx_ll_tim.h.

Referenced by OC1Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 2 (TIMx_CCR2).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not output channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_OC_SetCompareCH2
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2619 of file stm32f3xx_ll_tim.h.

Referenced by OC2Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH3 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 3 (TIMx_CCR3).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not output channel is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_OC_SetCompareCH3
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2636 of file stm32f3xx_ll_tim.h.

Referenced by OC3Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH4 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 4 (TIMx_CCR4).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not output channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_OC_SetCompareCH4
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2653 of file stm32f3xx_ll_tim.h.

Referenced by OC4Config().

__STATIC_INLINE void LL_TIM_OC_SetDeadTime | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DeadTime
 | ) |  |

Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not dead-time insertion feature is supported by a timer instance.
Helper macro __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
Reference Manual to LL API cross reference:
BDTR DTG LL_TIM_OC_SetDeadTime
Parameters:
TIMx | Timer instance
DeadTime | between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 2585 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_OC_SetIdleState | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | IdleState
 | ) |  |

Set the IDLE state of an output channel.

Note:
This function is significant only for the timer instances supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
CR2 OIS1 LL_TIM_OC_SetIdleState
CR2 OIS2N LL_TIM_OC_SetIdleState
CR2 OIS2 LL_TIM_OC_SetIdleState
CR2 OIS2N LL_TIM_OC_SetIdleState
CR2 OIS3 LL_TIM_OC_SetIdleState
CR2 OIS3N LL_TIM_OC_SetIdleState
CR2 OIS4 LL_TIM_OC_SetIdleState
CR2 OIS5 LL_TIM_OC_SetIdleState
CR2 OIS6 LL_TIM_OC_SetIdleState
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
IdleState This parameter can be one of the following values:
  • LL_TIM_OCIDLESTATE_LOW
  • LL_TIM_OCIDLESTATE_HIGH
Note:
CH5 and CH6 channels are not available for all F3 devices
Return values:
None

Definition at line 2206 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Mode
 | ) |  |

Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.

Reference Manual to LL API cross reference:
CCMR1 OC1M LL_TIM_OC_SetMode
CCMR1 OC2M LL_TIM_OC_SetMode
CCMR2 OC3M LL_TIM_OC_SetMode
CCMR2 OC4M LL_TIM_OC_SetMode
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Mode This parameter can be one of the following values:
  • LL_TIM_OCMODE_FROZEN
  • LL_TIM_OCMODE_ACTIVE
  • LL_TIM_OCMODE_INACTIVE
  • LL_TIM_OCMODE_TOGGLE
  • LL_TIM_OCMODE_FORCED_INACTIVE
  • LL_TIM_OCMODE_FORCED_ACTIVE
  • LL_TIM_OCMODE_PWM1
  • LL_TIM_OCMODE_PWM2
  • LL_TIM_OCMODE_RETRIG_OPM1
  • LL_TIM_OCMODE_RETRIG_OPM2
  • LL_TIM_OCMODE_COMBINED_PWM1
  • LL_TIM_OCMODE_COMBINED_PWM2
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2
Note:
The following OC modes are not available on all F3 devices :
  • LL_TIM_OCMODE_RETRIG_OPM1
  • LL_TIM_OCMODE_RETRIG_OPM2
  • LL_TIM_OCMODE_COMBINED_PWM1
  • LL_TIM_OCMODE_COMBINED_PWM2
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2
CH5 and CH6 channels are not available for all F3 devices
Return values:
None

Definition at line 2045 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of an output channel.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_OC_SetPolarity
CCER CC1NP LL_TIM_OC_SetPolarity
CCER CC2P LL_TIM_OC_SetPolarity
CCER CC2NP LL_TIM_OC_SetPolarity
CCER CC3P LL_TIM_OC_SetPolarity
CCER CC3NP LL_TIM_OC_SetPolarity
CCER CC4P LL_TIM_OC_SetPolarity
CCER CC5P LL_TIM_OC_SetPolarity
CCER CC6P LL_TIM_OC_SetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Polarity This parameter can be one of the following values:
  • LL_TIM_OCPOLARITY_HIGH
  • LL_TIM_OCPOLARITY_LOW
Note:
CH5 and CH6 channels are not available for all F3 devices
Return values:
None

Definition at line 2135 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Input channel configuration

Functions
Input channel configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_IC_Config (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure input channel.
__STATIC_INLINE void | LL_TIM_IC_SetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
Set the active input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current active input.
__STATIC_INLINE void | LL_TIM_IC_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
Set the prescaler of input channel.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current prescaler value acting on an input channel.
__STATIC_INLINE void | LL_TIM_IC_SetFilter (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
Set the input filter duration.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetFilter (TIM_TypeDef *TIMx, uint32_t Channel)
Get the input filter duration.
__STATIC_INLINE void | LL_TIM_IC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
Set the input channel polarity.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current input channel polarity.
__STATIC_INLINE void | LL_TIM_IC_EnableXORCombination (TIM_TypeDef *TIMx)
Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
__STATIC_INLINE void | LL_TIM_IC_DisableXORCombination (TIM_TypeDef *TIMx)
Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_IsEnabledXORCombination (TIM_TypeDef *TIMx)
Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH1 (TIM_TypeDef *TIMx)
Get captured value for input channel 1.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH2 (TIM_TypeDef *TIMx)
Get captured value for input channel 2.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH3 (TIM_TypeDef *TIMx)
Get captured value for input channel 3.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH4 (TIM_TypeDef *TIMx)
Get captured value for input channel 4.

Function Documentation

__STATIC_INLINE void LL_TIM_IC_Config | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure input channel.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_Config
CCMR1 IC1PSC LL_TIM_IC_Config
CCMR1 IC1F LL_TIM_IC_Config
CCMR1 CC2S LL_TIM_IC_Config
CCMR1 IC2PSC LL_TIM_IC_Config
CCMR1 IC2F LL_TIM_IC_Config
CCMR2 CC3S LL_TIM_IC_Config
CCMR2 IC3PSC LL_TIM_IC_Config
CCMR2 IC3F LL_TIM_IC_Config
CCMR2 CC4S LL_TIM_IC_Config
CCMR2 IC4PSC LL_TIM_IC_Config
CCMR2 IC4F LL_TIM_IC_Config
CCER CC1P LL_TIM_IC_Config
CCER CC1NP LL_TIM_IC_Config
CCER CC2P LL_TIM_IC_Config
CCER CC2NP LL_TIM_IC_Config
CCER CC3P LL_TIM_IC_Config
CCER CC3NP LL_TIM_IC_Config
CCER CC4P LL_TIM_IC_Config
CCER CC4NP LL_TIM_IC_Config
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Configuration This parameter must be a combination of all the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI or LL_TIM_ACTIVEINPUT_INDIRECTTI or LL_TIM_ACTIVEINPUT_TRC
  • LL_TIM_ICPSC_DIV1 or ... or LL_TIM_ICPSC_DIV8
  • LL_TIM_IC_FILTER_FDIV1 or ... or LL_TIM_IC_FILTER_FDIV32_N8
  • LL_TIM_IC_POLARITY_RISING or LL_TIM_IC_POLARITY_FALLING or LL_TIM_IC_POLARITY_BOTHEDGE
Return values:
None

Definition at line 2887 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_DisableXORCombination ( TIM_TypeDef * TIMx )

Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_DisableXORCombination
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3150 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_IC_EnableXORCombination ( TIM_TypeDef * TIMx )

Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_EnableXORCombination
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3137 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current active input.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_GetActiveInput
CCMR1 CC2S LL_TIM_IC_GetActiveInput
CCMR2 CC3S LL_TIM_IC_GetActiveInput
CCMR2 CC4S LL_TIM_IC_GetActiveInput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI
  • LL_TIM_ACTIVEINPUT_INDIRECTTI
  • LL_TIM_ACTIVEINPUT_TRC

Definition at line 2939 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1 ( TIM_TypeDef * TIMx )

Get captured value for input channel 1.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not input channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3179 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2 ( TIM_TypeDef * TIMx )

Get captured value for input channel 2.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not input channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3195 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3 ( TIM_TypeDef * TIMx )

Get captured value for input channel 3.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not input channel 3 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3211 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4 ( TIM_TypeDef * TIMx )

Get captured value for input channel 4.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not input channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3227 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the input filter duration.

Reference Manual to LL API cross reference:
CCMR1 IC1F LL_TIM_IC_GetFilter
CCMR1 IC2F LL_TIM_IC_GetFilter
CCMR2 IC3F LL_TIM_IC_GetFilter
CCMR2 IC4F LL_TIM_IC_GetFilter
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_IC_FILTER_FDIV1
  • LL_TIM_IC_FILTER_FDIV1_N2
  • LL_TIM_IC_FILTER_FDIV1_N4
  • LL_TIM_IC_FILTER_FDIV1_N8
  • LL_TIM_IC_FILTER_FDIV2_N6
  • LL_TIM_IC_FILTER_FDIV2_N8
  • LL_TIM_IC_FILTER_FDIV4_N6
  • LL_TIM_IC_FILTER_FDIV4_N8
  • LL_TIM_IC_FILTER_FDIV8_N6
  • LL_TIM_IC_FILTER_FDIV8_N8
  • LL_TIM_IC_FILTER_FDIV16_N5
  • LL_TIM_IC_FILTER_FDIV16_N6
  • LL_TIM_IC_FILTER_FDIV16_N8
  • LL_TIM_IC_FILTER_FDIV32_N5
  • LL_TIM_IC_FILTER_FDIV32_N6
  • LL_TIM_IC_FILTER_FDIV32_N8

Definition at line 3065 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current input channel polarity.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_IC_GetPolarity
CCER CC1NP LL_TIM_IC_GetPolarity
CCER CC2P LL_TIM_IC_GetPolarity
CCER CC2NP LL_TIM_IC_GetPolarity
CCER CC3P LL_TIM_IC_GetPolarity
CCER CC3NP LL_TIM_IC_GetPolarity
CCER CC4P LL_TIM_IC_GetPolarity
CCER CC4NP LL_TIM_IC_GetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_IC_POLARITY_RISING
  • LL_TIM_IC_POLARITY_FALLING
  • LL_TIM_IC_POLARITY_BOTHEDGE

Definition at line 3122 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current prescaler value acting on an input channel.

Reference Manual to LL API cross reference:
CCMR1 IC1PSC LL_TIM_IC_GetPrescaler
CCMR1 IC2PSC LL_TIM_IC_GetPrescaler
CCMR2 IC3PSC LL_TIM_IC_GetPrescaler
CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8

Definition at line 2990 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination ( TIM_TypeDef * TIMx )

Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3163 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_IC_SetActiveInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICActiveInput
 | ) |  |

Set the active input.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_SetActiveInput
CCMR1 CC2S LL_TIM_IC_SetActiveInput
CCMR2 CC3S LL_TIM_IC_SetActiveInput
CCMR2 CC4S LL_TIM_IC_SetActiveInput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICActiveInput This parameter can be one of the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI
  • LL_TIM_ACTIVEINPUT_INDIRECTTI
  • LL_TIM_ACTIVEINPUT_TRC
Return values:
None

Definition at line 2915 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetFilter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICFilter
 | ) |  |

Set the input filter duration.

Reference Manual to LL API cross reference:
CCMR1 IC1F LL_TIM_IC_SetFilter
CCMR1 IC2F LL_TIM_IC_SetFilter
CCMR2 IC3F LL_TIM_IC_SetFilter
CCMR2 IC4F LL_TIM_IC_SetFilter
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICFilter This parameter can be one of the following values:
  • LL_TIM_IC_FILTER_FDIV1
  • LL_TIM_IC_FILTER_FDIV1_N2
  • LL_TIM_IC_FILTER_FDIV1_N4
  • LL_TIM_IC_FILTER_FDIV1_N8
  • LL_TIM_IC_FILTER_FDIV2_N6
  • LL_TIM_IC_FILTER_FDIV2_N8
  • LL_TIM_IC_FILTER_FDIV4_N6
  • LL_TIM_IC_FILTER_FDIV4_N8
  • LL_TIM_IC_FILTER_FDIV8_N6
  • LL_TIM_IC_FILTER_FDIV8_N8
  • LL_TIM_IC_FILTER_FDIV16_N5
  • LL_TIM_IC_FILTER_FDIV16_N6
  • LL_TIM_IC_FILTER_FDIV16_N8
  • LL_TIM_IC_FILTER_FDIV32_N5
  • LL_TIM_IC_FILTER_FDIV32_N6
  • LL_TIM_IC_FILTER_FDIV32_N8
Return values:
None

Definition at line 3028 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICPolarity
 | ) |  |

Set the input channel polarity.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_IC_SetPolarity
CCER CC1NP LL_TIM_IC_SetPolarity
CCER CC2P LL_TIM_IC_SetPolarity
CCER CC2NP LL_TIM_IC_SetPolarity
CCER CC3P LL_TIM_IC_SetPolarity
CCER CC3NP LL_TIM_IC_SetPolarity
CCER CC4P LL_TIM_IC_SetPolarity
CCER CC4NP LL_TIM_IC_SetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICPolarity This parameter can be one of the following values:
  • LL_TIM_IC_POLARITY_RISING
  • LL_TIM_IC_POLARITY_FALLING
  • LL_TIM_IC_POLARITY_BOTHEDGE
Return values:
None

Definition at line 3094 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICPrescaler
 | ) |  |

Set the prescaler of input channel.

Reference Manual to LL API cross reference:
CCMR1 IC1PSC LL_TIM_IC_SetPrescaler
CCMR1 IC2PSC LL_TIM_IC_SetPrescaler
CCMR2 IC3PSC LL_TIM_IC_SetPrescaler
CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICPrescaler This parameter can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8
Return values:
None

Definition at line 2965 of file stm32f3xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Counter clock selection

Functions
Counter clock selection
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableExternalClock (TIM_TypeDef *TIMx)
Enable external clock mode 2.
__STATIC_INLINE void | LL_TIM_DisableExternalClock (TIM_TypeDef *TIMx)
Disable external clock mode 2.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledExternalClock (TIM_TypeDef *TIMx)
Indicate whether external clock mode 2 is enabled.
__STATIC_INLINE void | LL_TIM_SetClockSource (TIM_TypeDef *TIMx, uint32_t ClockSource)
Set the clock source of the counter clock.
__STATIC_INLINE void | LL_TIM_SetEncoderMode (TIM_TypeDef *TIMx, uint32_t EncoderMode)
Set the encoder interface mode.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableExternalClock ( TIM_TypeDef * TIMx )

Disable external clock mode 2.

Note:
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_DisableExternalClock
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3261 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableExternalClock ( TIM_TypeDef * TIMx )

Enable external clock mode 2.

Note:
When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_EnableExternalClock
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3248 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock ( TIM_TypeDef * TIMx )

Indicate whether external clock mode 2 is enabled.

Note:
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_IsEnabledExternalClock
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3274 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetClockSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ClockSource
 | ) |  |

Set the clock source of the counter clock.

Note:
when selected clock source is external clock mode 1, the timer input the external clock is applied is selected by calling the LL_TIM_SetTriggerInput() function. This timer input must be configured by calling the LL_TIM_IC_Config() function.
Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode1.
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetClockSource
SMCR ECE LL_TIM_SetClockSource
Parameters:
TIMx Timer instance
ClockSource This parameter can be one of the following values:
  • LL_TIM_CLOCKSOURCE_INTERNAL
  • LL_TIM_CLOCKSOURCE_EXT_MODE1
  • LL_TIM_CLOCKSOURCE_EXT_MODE2
Return values:
None

Definition at line 3298 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetEncoderMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | EncoderMode
 | ) |  |

Set the encoder interface mode.

Note:
Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the encoder mode.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetEncoderMode
Parameters:
TIMx Timer instance
EncoderMode This parameter can be one of the following values:
  • LL_TIM_ENCODERMODE_X2_TI1
  • LL_TIM_ENCODERMODE_X2_TI2
  • LL_TIM_ENCODERMODE_X4_TI12
Return values:
None

Definition at line 3315 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init().

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Timer synchronisation configuration

Functions
Timer synchronisation configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_SetTriggerOutput (TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
Set the trigger output (TRGO) used for timer synchronization .
__STATIC_INLINE void | LL_TIM_SetSlaveMode (TIM_TypeDef *TIMx, uint32_t SlaveMode)
Set the synchronization mode of a slave timer.
__STATIC_INLINE void | LL_TIM_SetTriggerInput (TIM_TypeDef *TIMx, uint32_t TriggerInput)
Set the selects the trigger input to be used to synchronize the counter.
__STATIC_INLINE void | LL_TIM_EnableMasterSlaveMode (TIM_TypeDef *TIMx)
Enable the Master/Slave mode.
__STATIC_INLINE void | LL_TIM_DisableMasterSlaveMode (TIM_TypeDef *TIMx)
Disable the Master/Slave mode.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledMasterSlaveMode (TIM_TypeDef *TIMx)
Indicates whether the Master/Slave mode is enabled.
__STATIC_INLINE void | LL_TIM_ConfigETR (TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
Configure the external trigger (ETR) input.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigETR | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ETRPolarity,
 |  | uint32_t | ETRPrescaler,
 |  | uint32_t | ETRFilter
 | ) |  |

Configure the external trigger (ETR) input.

Note:
Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an external trigger input.
Reference Manual to LL API cross reference:
SMCR ETP LL_TIM_ConfigETR
SMCR ETPS LL_TIM_ConfigETR
SMCR ETF LL_TIM_ConfigETR
Parameters:
TIMx Timer instance
ETRPolarity This parameter can be one of the following values:
  • LL_TIM_ETR_POLARITY_NONINVERTED
  • LL_TIM_ETR_POLARITY_INVERTED
ETRPrescaler This parameter can be one of the following values:
  • LL_TIM_ETR_PRESCALER_DIV1
  • LL_TIM_ETR_PRESCALER_DIV2
  • LL_TIM_ETR_PRESCALER_DIV4
  • LL_TIM_ETR_PRESCALER_DIV8
ETRFilter This parameter can be one of the following values:
  • LL_TIM_ETR_FILTER_FDIV1
  • LL_TIM_ETR_FILTER_FDIV1_N2
  • LL_TIM_ETR_FILTER_FDIV1_N4
  • LL_TIM_ETR_FILTER_FDIV1_N8
  • LL_TIM_ETR_FILTER_FDIV2_N6
  • LL_TIM_ETR_FILTER_FDIV2_N8
  • LL_TIM_ETR_FILTER_FDIV4_N6
  • LL_TIM_ETR_FILTER_FDIV4_N8
  • LL_TIM_ETR_FILTER_FDIV8_N6
  • LL_TIM_ETR_FILTER_FDIV8_N8
  • LL_TIM_ETR_FILTER_FDIV16_N5
  • LL_TIM_ETR_FILTER_FDIV16_N6
  • LL_TIM_ETR_FILTER_FDIV16_N8
  • LL_TIM_ETR_FILTER_FDIV32_N5
  • LL_TIM_ETR_FILTER_FDIV32_N6
  • LL_TIM_ETR_FILTER_FDIV32_N8
Return values:
None

Definition at line 3497 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode ( TIM_TypeDef * TIMx )

Disable the Master/Slave mode.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_DisableMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3444 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode ( TIM_TypeDef * TIMx )

Enable the Master/Slave mode.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_EnableMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3431 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode ( TIM_TypeDef * TIMx )

Indicates whether the Master/Slave mode is enabled.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3457 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetSlaveMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | SlaveMode
 | ) |  |

Set the synchronization mode of a slave timer.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetSlaveMode
Parameters:
TIMx Timer instance
SlaveMode This parameter can be one of the following values:
  • LL_TIM_SLAVEMODE_DISABLED
  • LL_TIM_SLAVEMODE_RESET
  • LL_TIM_SLAVEMODE_GATED
  • LL_TIM_SLAVEMODE_TRIGGER
  • LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
Return values:
None

Definition at line 3396 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TriggerInput
 | ) |  |

Set the selects the trigger input to be used to synchronize the counter.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR TS LL_TIM_SetTriggerInput
Parameters:
TIMx Timer instance
TriggerInput This parameter can be one of the following values:
  • LL_TIM_TS_ITR0
  • LL_TIM_TS_ITR1
  • LL_TIM_TS_ITR2
  • LL_TIM_TS_ITR3
  • LL_TIM_TS_TI1F_ED
  • LL_TIM_TS_TI1FP1
  • LL_TIM_TS_TI2FP2
  • LL_TIM_TS_ETRF
Return values:
None

Definition at line 3418 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerOutput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TimerSynchronization
 | ) |  |

Set the trigger output (TRGO) used for timer synchronization .

Note:
Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a master timer.
Reference Manual to LL API cross reference:
CR2 MMS LL_TIM_SetTriggerOutput
Parameters:
TIMx Timer instance
TimerSynchronization This parameter can be one of the following values:
  • LL_TIM_TRGO_RESET
  • LL_TIM_TRGO_ENABLE
  • LL_TIM_TRGO_UPDATE
  • LL_TIM_TRGO_CC1IF
  • LL_TIM_TRGO_OC1REF
  • LL_TIM_TRGO_OC2REF
  • LL_TIM_TRGO_OC3REF
  • LL_TIM_TRGO_OC4REF
Return values:
None

Definition at line 3344 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Break function configuration

Functions
Break function configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableBRK (TIM_TypeDef *TIMx)
Enable the break function.
__STATIC_INLINE void | LL_TIM_DisableBRK (TIM_TypeDef *TIMx)
Disable the break function.
__STATIC_INLINE void | LL_TIM_ConfigBRK (TIM_TypeDef *TIMx, uint32_t BreakPolarity)
Configure the break input.
__STATIC_INLINE void | LL_TIM_SetOffStates (TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
Select the outputs off state (enabled v.s.
__STATIC_INLINE void | LL_TIM_EnableAutomaticOutput (TIM_TypeDef *TIMx)
Enable automatic output (MOE can be set by software or automatically when a break input is active).
__STATIC_INLINE void | LL_TIM_DisableAutomaticOutput (TIM_TypeDef *TIMx)
Disable automatic output (MOE can be set only by software).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAutomaticOutput (TIM_TypeDef *TIMx)
Indicate whether automatic output is enabled.
__STATIC_INLINE void | LL_TIM_EnableAllOutputs (TIM_TypeDef *TIMx)
Enable the outputs (set the MOE bit in TIMx_BDTR register).
__STATIC_INLINE void | LL_TIM_DisableAllOutputs (TIM_TypeDef *TIMx)
Disable the outputs (reset the MOE bit in TIMx_BDTR register).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAllOutputs (TIM_TypeDef *TIMx)
Indicates whether outputs are enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigBRK | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakPolarity
 | ) |  |

Configure the break input.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR BKP LL_TIM_ConfigBRK
Parameters:
TIMx Timer instance
BreakPolarity This parameter can be one of the following values:
  • LL_TIM_BREAK_POLARITY_LOW
  • LL_TIM_BREAK_POLARITY_HIGH
Return values:
None

Definition at line 3595 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableAllOutputs ( TIM_TypeDef * TIMx )

Disable the outputs (reset the MOE bit in TIMx_BDTR register).

Note:
The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event.
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_DisableAllOutputs
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3753 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableAutomaticOutput ( TIM_TypeDef * TIMx )

Disable automatic output (MOE can be set only by software).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_DisableAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3710 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableBRK ( TIM_TypeDef * TIMx )

Disable the break function.

Reference Manual to LL API cross reference:
BDTR BKE LL_TIM_DisableBRK
Parameters:
TIMx Timer instance
Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Return values:
None

Definition at line 3537 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableAllOutputs ( TIM_TypeDef * TIMx )

Enable the outputs (set the MOE bit in TIMx_BDTR register).

Note:
The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_EnableAllOutputs
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3738 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableAutomaticOutput ( TIM_TypeDef * TIMx )

Enable automatic output (MOE can be set by software or automatically when a break input is active).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_EnableAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3697 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableBRK ( TIM_TypeDef * TIMx )

Enable the break function.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR BKE LL_TIM_EnableBRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3518 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs ( TIM_TypeDef * TIMx )

Indicates whether outputs are enabled.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_IsEnabledAllOutputs
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3766 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput ( TIM_TypeDef * TIMx )

Indicate whether automatic output is enabled.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_IsEnabledAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3723 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetOffStates | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OffStateIdle,
 |  | uint32_t | OffStateRun
 | ) |  |

Select the outputs off state (enabled v.s.

disabled) in Idle and Run modes.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR OSSI LL_TIM_SetOffStates
BDTR OSSR LL_TIM_SetOffStates
Parameters:
TIMx Timer instance
OffStateIdle This parameter can be one of the following values:
  • LL_TIM_OSSI_DISABLE
  • LL_TIM_OSSI_ENABLE
OffStateRun This parameter can be one of the following values:
  • LL_TIM_OSSR_DISABLE
  • LL_TIM_OSSR_ENABLE
Return values:
None

Definition at line 3684 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA burst mode configuration

Functions
DMA burst mode configuration
TIM Exported Functions

Functions

__STATIC_INLINE void LL_TIM_ConfigDMABurst (TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
Configures the timer DMA burst feature.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigDMABurst | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DMABurstBaseAddress,
 |  | uint32_t | DMABurstLength
 | ) |  |

Configures the timer DMA burst feature.

Note:
Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the DMA burst mode.
Reference Manual to LL API cross reference:
DCR DBL LL_TIM_ConfigDMABurst
DCR DBA LL_TIM_ConfigDMABurst
Parameters:
TIMx Timer instance
DMABurstBaseAddress This parameter can be one of the following values:
  • LL_TIM_DMABURST_BASEADDR_CR1
  • LL_TIM_DMABURST_BASEADDR_CR2
  • LL_TIM_DMABURST_BASEADDR_SMCR
  • LL_TIM_DMABURST_BASEADDR_DIER
  • LL_TIM_DMABURST_BASEADDR_SR
  • LL_TIM_DMABURST_BASEADDR_EGR
  • LL_TIM_DMABURST_BASEADDR_CCMR1
  • LL_TIM_DMABURST_BASEADDR_CCMR2
  • LL_TIM_DMABURST_BASEADDR_CCER
  • LL_TIM_DMABURST_BASEADDR_CNT
  • LL_TIM_DMABURST_BASEADDR_PSC
  • LL_TIM_DMABURST_BASEADDR_ARR
  • LL_TIM_DMABURST_BASEADDR_RCR
  • LL_TIM_DMABURST_BASEADDR_CCR1
  • LL_TIM_DMABURST_BASEADDR_CCR2
  • LL_TIM_DMABURST_BASEADDR_CCR3
  • LL_TIM_DMABURST_BASEADDR_CCR4
  • LL_TIM_DMABURST_BASEADDR_BDTR
  • LL_TIM_DMABURST_BASEADDR_CCMR3 (*)
  • LL_TIM_DMABURST_BASEADDR_CCR5 (*)
  • LL_TIM_DMABURST_BASEADDR_CCR6 (*) (*) value not defined in all devices
  • LL_TIM_DMABURST_BASEADDR_OR
DMABurstLength This parameter can be one of the following values:
  • LL_TIM_DMABURST_LENGTH_1TRANSFER
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS
Return values:
None

Definition at line 3830 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Timer input remapping

Functions
Timer input remapping
TIM Exported Functions

Functions

__STATIC_INLINE void LL_TIM_SetRemap (TIM_TypeDef *TIMx, uint32_t Remap)
Remap TIM inputs (input channel, internal/external triggers).

Function Documentation

__STATIC_INLINE void LL_TIM_SetRemap | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Remap
 | ) |  |

Remap TIM inputs (input channel, internal/external triggers).

Note:
Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not a some timer inputs can be remapped.
Reference Manual to LL API cross reference:
TIM14_OR TI1_RMP LL_TIM_SetRemap
Parameters:
TIMx | Timer instance
Remap | Remap params depends on the TIMx. Description available only in CHM version of the User Manual (not in .pdf). Otherwise see Reference Manual description of OR registers.

Below description summarizes "Timer Instance" and "Remap" param combinations:

TIM1: any combination of ETR_RMP where (**)

. . ETR_RMP can be one of the following values

  • LL_TIM_TIM1_ETR_ADC1_RMP_NC
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (*)
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (*)
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (*)
  • LL_TIM_TIM1_ETR_ADC2_RMP_NC (*)
  • LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (*)
  • LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (*)
  • LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (*)
  • LL_TIM_TIM1_ETR_ADC3_RMP_NC (*)
  • LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (*)
  • LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (*)
  • LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (*)

TIM8: any combination of ETR_RMP where (**)

. . ETR_RMP can be one of the following values

  • LL_TIM_TIM8_ETR_ADC2_RMP_NC (*)
  • LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (*)
  • LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (*)
  • LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (*)
  • LL_TIM_TIM8_ETR_ADC3_RMP_NC (*)
  • LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (*)
  • LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (*)
  • LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (*)

TIM14: any combination of TI1_RMP where (**)

. . TI1_RMP can be one of the following values

  • LL_TIM_TIM14_TI1_RMP_GPIO (*)
  • LL_TIM_TIM14_TI1_RMP_RTC_CLK (*)
  • LL_TIM_TIM14_TI1_RMP_HSE (*)
  • LL_TIM_TIM14_TI1_RMP_MCO (*)

TIM16: any combination of TI1_RMP where (**)

. . TI1_RMP can be one of the following values

  • LL_TIM_TIM16_TI1_RMP_GPIO (*)
  • LL_TIM_TIM16_TI1_RMP_LSI (*)
  • LL_TIM_TIM16_TI1_RMP_LSE (*)
  • LL_TIM_TIM16_TI1_RMP_RTC (*)

TIM20: any combination of ETR_RMP where (**)

. . ETR_RMP can be one of the following values

  • LL_TIM_TIM20_ETR_ADC3_RMP_NC (*)
  • LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (*)
  • LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (*)
  • LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (*)
  • LL_TIM_TIM20_ETR_ADC4_RMP_NC (*)
  • LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (*)
  • LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (*)
  • LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (*)

(*) Value not defined in all devices.
(**) Register not available in all devices.

Return values:
None

Definition at line 3926 of file stm32f3xx_ll_tim.h.

References TIMx_OR_RMP_MASK, and TIMx_OR_RMP_SHIFT.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLAG-Management

Functions
FLAG-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_ClearFlag_UPDATE (TIM_TypeDef *TIMx)
Clear the update interrupt flag (UIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_UPDATE (TIM_TypeDef *TIMx)
Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 interrupt flag (CC1F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 interrupt flag (CC2F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 interrupt flag (CC3F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 interrupt flag (CC4F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_COM (TIM_TypeDef *TIMx)
Clear the commutation interrupt flag (COMIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_COM (TIM_TypeDef *TIMx)
Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_TRIG (TIM_TypeDef *TIMx)
Clear the trigger interrupt flag (TIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_TRIG (TIM_TypeDef *TIMx)
Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK (TIM_TypeDef *TIMx)
Clear the break interrupt flag (BIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK (TIM_TypeDef *TIMx)
Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).

Function Documentation

__STATIC_INLINE void LL_TIM_ClearFlag_BRK ( TIM_TypeDef * TIMx )

Clear the break interrupt flag (BIF).

Reference Manual to LL API cross reference:
SR BIF LL_TIM_ClearFlag_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4170 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC1 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 1 interrupt flag (CC1F).

Reference Manual to LL API cross reference:
SR CC1IF LL_TIM_ClearFlag_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3990 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).

Reference Manual to LL API cross reference:
SR CC1OF LL_TIM_ClearFlag_CC1OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4216 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC2 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 2 interrupt flag (CC2F).

Reference Manual to LL API cross reference:
SR CC2IF LL_TIM_ClearFlag_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4012 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).

Reference Manual to LL API cross reference:
SR CC2OF LL_TIM_ClearFlag_CC2OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4238 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC3 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 3 interrupt flag (CC3F).

Reference Manual to LL API cross reference:
SR CC3IF LL_TIM_ClearFlag_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4034 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).

Reference Manual to LL API cross reference:
SR CC3OF LL_TIM_ClearFlag_CC3OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4260 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC4 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 4 interrupt flag (CC4F).

Reference Manual to LL API cross reference:
SR CC4IF LL_TIM_ClearFlag_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4056 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).

Reference Manual to LL API cross reference:
SR CC4OF LL_TIM_ClearFlag_CC4OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4282 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_COM ( TIM_TypeDef * TIMx )

Clear the commutation interrupt flag (COMIF).

Reference Manual to LL API cross reference:
SR COMIF LL_TIM_ClearFlag_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4126 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_TRIG ( TIM_TypeDef * TIMx )

Clear the trigger interrupt flag (TIF).

Reference Manual to LL API cross reference:
SR TIF LL_TIM_ClearFlag_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4148 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE ( TIM_TypeDef * TIMx )

Clear the update interrupt flag (UIF).

Reference Manual to LL API cross reference:
SR UIF LL_TIM_ClearFlag_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3968 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK ( TIM_TypeDef * TIMx )

Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).

Reference Manual to LL API cross reference:
SR BIF LL_TIM_IsActiveFlag_BRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4181 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC1IF LL_TIM_IsActiveFlag_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4001 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4227 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC2IF LL_TIM_IsActiveFlag_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4023 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4249 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC3IF LL_TIM_IsActiveFlag_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4045 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4271 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC4IF LL_TIM_IsActiveFlag_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4067 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4293 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM ( TIM_TypeDef * TIMx )

Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).

Reference Manual to LL API cross reference:
SR COMIF LL_TIM_IsActiveFlag_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4137 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG ( TIM_TypeDef * TIMx )

Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).

Reference Manual to LL API cross reference:
SR TIF LL_TIM_IsActiveFlag_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4159 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE ( TIM_TypeDef * TIMx )

Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).

Reference Manual to LL API cross reference:
SR UIF LL_TIM_IsActiveFlag_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3979 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IT-Management

Functions
IT-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableIT_UPDATE (TIM_TypeDef *TIMx)
Enable update interrupt (UIE).
__STATIC_INLINE void | LL_TIM_DisableIT_UPDATE (TIM_TypeDef *TIMx)
Disable update interrupt (UIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update interrupt (UIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_COM (TIM_TypeDef *TIMx)
Enable commutation interrupt (COMIE).
__STATIC_INLINE void | LL_TIM_DisableIT_COM (TIM_TypeDef *TIMx)
Disable commutation interrupt (COMIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation interrupt (COMIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TIE).
__STATIC_INLINE void | LL_TIM_DisableIT_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_BRK (TIM_TypeDef *TIMx)
Enable break interrupt (BIE).
__STATIC_INLINE void | LL_TIM_DisableIT_BRK (TIM_TypeDef *TIMx)
Disable break interrupt (BIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_BRK (TIM_TypeDef *TIMx)
Indicates whether the break interrupt (BIE) is enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableIT_BRK ( TIM_TypeDef * TIMx )

Disable break interrupt (BIE).

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_DisableIT_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4553 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC1 ( TIM_TypeDef * TIMx )

Disable capture/compare 1 interrupt (CC1IE).

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_DisableIT_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4355 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC2 ( TIM_TypeDef * TIMx )

Disable capture/compare 2 interrupt (CC2IE).

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_DisableIT_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4388 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC3 ( TIM_TypeDef * TIMx )

Disable capture/compare 3 interrupt (CC3IE).

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_DisableIT_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4421 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC4 ( TIM_TypeDef * TIMx )

Disable capture/compare 4 interrupt (CC4IE).

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_DisableIT_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4454 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_COM ( TIM_TypeDef * TIMx )

Disable commutation interrupt (COMIE).

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_DisableIT_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4487 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_TRIG ( TIM_TypeDef * TIMx )

Disable trigger interrupt (TIE).

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_DisableIT_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4520 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_UPDATE ( TIM_TypeDef * TIMx )

Disable update interrupt (UIE).

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_DisableIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4322 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_BRK ( TIM_TypeDef * TIMx )

Enable break interrupt (BIE).

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_EnableIT_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4542 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC1 ( TIM_TypeDef * TIMx )

Enable capture/compare 1 interrupt (CC1IE).

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_EnableIT_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4344 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC2 ( TIM_TypeDef * TIMx )

Enable capture/compare 2 interrupt (CC2IE).

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_EnableIT_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4377 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC3 ( TIM_TypeDef * TIMx )

Enable capture/compare 3 interrupt (CC3IE).

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_EnableIT_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4410 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC4 ( TIM_TypeDef * TIMx )

Enable capture/compare 4 interrupt (CC4IE).

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_EnableIT_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4443 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_COM ( TIM_TypeDef * TIMx )

Enable commutation interrupt (COMIE).

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_EnableIT_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4476 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_TRIG ( TIM_TypeDef * TIMx )

Enable trigger interrupt (TIE).

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_EnableIT_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4509 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_UPDATE ( TIM_TypeDef * TIMx )

Enable update interrupt (UIE).

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_EnableIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4311 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK ( TIM_TypeDef * TIMx )

Indicates whether the break interrupt (BIE) is enabled.

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_IsEnabledIT_BRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4564 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_IsEnabledIT_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4366 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_IsEnabledIT_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4399 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_IsEnabledIT_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4432 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_IsEnabledIT_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4465 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM ( TIM_TypeDef * TIMx )

Indicates whether the commutation interrupt (COMIE) is enabled.

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_IsEnabledIT_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4498 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG ( TIM_TypeDef * TIMx )

Indicates whether the trigger interrupt (TIE) is enabled.

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_IsEnabledIT_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4531 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE ( TIM_TypeDef * TIMx )

Indicates whether the update interrupt (UIE) is enabled.

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_IsEnabledIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4333 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA-Management

Functions
DMA-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Enable update DMA request (UDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Disable update DMA request (UDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update DMA request (UDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_COM (TIM_TypeDef *TIMx)
Enable commutation DMA request (COMDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_COM (TIM_TypeDef *TIMx)
Disable commutation DMA request (COMDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation DMA request (COMDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TDE) is enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1 ( TIM_TypeDef * TIMx )

Disable capture/compare 1 DMA request (CC1DE).

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_DisableDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4626 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2 ( TIM_TypeDef * TIMx )

Disable capture/compare 2 DMA request (CC2DE).

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_DisableDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4659 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3 ( TIM_TypeDef * TIMx )

Disable capture/compare 3 DMA request (CC3DE).

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_DisableDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4692 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4 ( TIM_TypeDef * TIMx )

Disable capture/compare 4 DMA request (CC4DE).

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_DisableDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4725 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_COM ( TIM_TypeDef * TIMx )

Disable commutation DMA request (COMDE).

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_DisableDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4758 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG ( TIM_TypeDef * TIMx )

Disable trigger interrupt (TDE).

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_DisableDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4791 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Disable update DMA request (UDE).

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_DisableDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4593 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1 ( TIM_TypeDef * TIMx )

Enable capture/compare 1 DMA request (CC1DE).

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_EnableDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4615 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2 ( TIM_TypeDef * TIMx )

Enable capture/compare 2 DMA request (CC2DE).

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_EnableDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4648 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3 ( TIM_TypeDef * TIMx )

Enable capture/compare 3 DMA request (CC3DE).

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_EnableDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4681 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4 ( TIM_TypeDef * TIMx )

Enable capture/compare 4 DMA request (CC4DE).

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_EnableDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4714 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_COM ( TIM_TypeDef * TIMx )

Enable commutation DMA request (COMDE).

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_EnableDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4747 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG ( TIM_TypeDef * TIMx )

Enable trigger interrupt (TDE).

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_EnableDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4780 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Enable update DMA request (UDE).

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_EnableDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4582 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4637 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4670 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4703 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4736 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM ( TIM_TypeDef * TIMx )

Indicates whether the commutation DMA request (COMDE) is enabled.

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_IsEnabledDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4769 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG ( TIM_TypeDef * TIMx )

Indicates whether the trigger interrupt (TDE) is enabled.

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4802 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Indicates whether the update DMA request (UDE) is enabled.

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4604 of file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: EVENT-Management

Functions
EVENT-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_GenerateEvent_UPDATE (TIM_TypeDef *TIMx)
Generate an update event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC1 (TIM_TypeDef *TIMx)
Generate Capture/Compare 1 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC2 (TIM_TypeDef *TIMx)
Generate Capture/Compare 2 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC3 (TIM_TypeDef *TIMx)
Generate Capture/Compare 3 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC4 (TIM_TypeDef *TIMx)
Generate Capture/Compare 4 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_COM (TIM_TypeDef *TIMx)
Generate commutation event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_TRIG (TIM_TypeDef *TIMx)
Generate trigger event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK (TIM_TypeDef *TIMx)
Generate break event.

Function Documentation

__STATIC_INLINE void LL_TIM_GenerateEvent_BRK ( TIM_TypeDef * TIMx )

Generate break event.

Reference Manual to LL API cross reference:
EGR BG LL_TIM_GenerateEvent_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4897 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC1 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 1 event.

Reference Manual to LL API cross reference:
EGR CC1G LL_TIM_GenerateEvent_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4831 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC2 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 2 event.

Reference Manual to LL API cross reference:
EGR CC2G LL_TIM_GenerateEvent_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4842 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC3 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 3 event.

Reference Manual to LL API cross reference:
EGR CC3G LL_TIM_GenerateEvent_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4853 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC4 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 4 event.

Reference Manual to LL API cross reference:
EGR CC4G LL_TIM_GenerateEvent_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4864 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_COM ( TIM_TypeDef * TIMx )

Generate commutation event.

Reference Manual to LL API cross reference:
EGR COMG LL_TIM_GenerateEvent_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4875 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG ( TIM_TypeDef * TIMx )

Generate trigger event.

Reference Manual to LL API cross reference:
EGR TG LL_TIM_GenerateEvent_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4886 of file stm32f3xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE ( TIM_TypeDef * TIMx )

Generate an update event.

Reference Manual to LL API cross reference:
EGR UG LL_TIM_GenerateEvent_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4820 of file stm32f3xx_ll_tim.h.

Referenced by LL_TIM_Init().

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialisation and deinitialisation functions

Functions
Initialisation and deinitialisation functions
TIM Exported Functions

Functions

ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)

Function Documentation

ErrorStatus LL_TIM_BDTR_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_BDTR_InitTypeDef * | TIM_BDTRInitStruct
 | ) |  |

Configure the Break and Dead Time feature of the timer instance.

Note:
As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Parameters:
TIMx | Timer Instance
TIM_BDTRInitStruct | pointer to a LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Break and Dead Time is initialized
  • ERROR: not applicable

Definition at line 811 of file stm32f3xx_ll_tim.c.

References assert_param, LL_TIM_BDTR_InitTypeDef::AutomaticOutput, LL_TIM_BDTR_InitTypeDef::BreakPolarity, LL_TIM_BDTR_InitTypeDef::BreakState, LL_TIM_BDTR_InitTypeDef::DeadTime, IS_LL_TIM_AUTOMATIC_OUTPUT_STATE, IS_LL_TIM_BREAK_POLARITY, IS_LL_TIM_BREAK_STATE, IS_LL_TIM_LOCK_LEVEL, IS_LL_TIM_OSSI_STATE, IS_LL_TIM_OSSR_STATE, LL_TIM_WriteReg, LL_TIM_BDTR_InitTypeDef::LockLevel, LL_TIM_BDTR_InitTypeDef::OSSIState, and LL_TIM_BDTR_InitTypeDef::OSSRState.

void LL_TIM_BDTR_StructInit ( LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct )

Set the fields of the Break and Dead Time configuration data structure to their default values.

Parameters:
TIM_BDTRInitStruct pointer to a LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
Return values:
None

Definition at line 775 of file stm32f3xx_ll_tim.c.

References LL_TIM_BDTR_InitTypeDef::AutomaticOutput, LL_TIM_BDTR_InitTypeDef::BreakPolarity, LL_TIM_BDTR_InitTypeDef::BreakState, LL_TIM_BDTR_InitTypeDef::DeadTime, LL_TIM_AUTOMATICOUTPUT_DISABLE, LL_TIM_BREAK_DISABLE, LL_TIM_BREAK_POLARITY_LOW, LL_TIM_LOCKLEVEL_OFF, LL_TIM_OSSI_DISABLE, LL_TIM_OSSR_DISABLE, LL_TIM_BDTR_InitTypeDef::LockLevel, LL_TIM_BDTR_InitTypeDef::OSSIState, and LL_TIM_BDTR_InitTypeDef::OSSRState.

ErrorStatus LL_TIM_DeInit ( TIM_TypeDef * TIMx )

Set TIMx registers to their reset values.

Parameters:
TIMx Timer instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: invalid TIMx instance

Definition at line 252 of file stm32f3xx_ll_tim.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_TIM12, LL_APB1_GRP1_PERIPH_TIM13, LL_APB1_GRP1_PERIPH_TIM14, LL_APB1_GRP1_PERIPH_TIM18, LL_APB1_GRP1_PERIPH_TIM2, LL_APB1_GRP1_PERIPH_TIM3, LL_APB1_GRP1_PERIPH_TIM4, LL_APB1_GRP1_PERIPH_TIM5, LL_APB1_GRP1_PERIPH_TIM6, LL_APB1_GRP1_PERIPH_TIM7, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_TIM15, LL_APB2_GRP1_PERIPH_TIM16, LL_APB2_GRP1_PERIPH_TIM17, LL_APB2_GRP1_PERIPH_TIM19, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_TIM_ENCODER_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_ENCODER_InitTypeDef * | TIM_EncoderInitStruct
 | ) |  |

Configure the encoder interface of the timer instance.

Parameters:
TIMx | Timer Instance
TIM_EncoderInitStruct | pointer to a LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 604 of file stm32f3xx_ll_tim.c.

References assert_param, LL_TIM_ENCODER_InitTypeDef::EncoderMode, LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC1Filter, LL_TIM_ENCODER_InitTypeDef::IC1Polarity, LL_TIM_ENCODER_InitTypeDef::IC1Prescaler, LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC2Filter, LL_TIM_ENCODER_InitTypeDef::IC2Polarity, LL_TIM_ENCODER_InitTypeDef::IC2Prescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_ENCODERMODE, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY_ENCODER, IS_LL_TIM_ICPSC, LL_TIM_ReadReg, LL_TIM_SetEncoderMode(), and LL_TIM_WriteReg.

void LL_TIM_ENCODER_StructInit ( LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct )

Fills each TIM_EncoderInitStruct field with its default value.

Parameters:
TIM_EncoderInitStruct pointer to a LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
Return values:
None

Definition at line 582 of file stm32f3xx_ll_tim.c.

References LL_TIM_ENCODER_InitTypeDef::EncoderMode, LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC1Filter, LL_TIM_ENCODER_InitTypeDef::IC1Polarity, LL_TIM_ENCODER_InitTypeDef::IC1Prescaler, LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC2Filter, LL_TIM_ENCODER_InitTypeDef::IC2Polarity, LL_TIM_ENCODER_InitTypeDef::IC2Prescaler, LL_TIM_ACTIVEINPUT_DIRECTTI, LL_TIM_ENCODERMODE_X2_TI1, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_HALLSENSOR_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_HALLSENSOR_InitTypeDef * | TIM_HallSensorInitStruct
 | ) |  |
void LL_TIM_HALLSENSOR_StructInit ( LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct )
ErrorStatus LL_TIM_IC_Init | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | LL_TIM_IC_InitTypeDef * | TIM_IC_InitStruct
 | ) |  |

Configure the TIMx input channel.

Parameters:
TIMx | Timer Instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
TIM_IC_InitStruct | pointer to a LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx output channel is initialized
  • ERROR: TIMx output channel is not initialized

Definition at line 552 of file stm32f3xx_ll_tim.c.

References IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_CHANNEL_CH1, LL_TIM_CHANNEL_CH2, LL_TIM_CHANNEL_CH3, and LL_TIM_CHANNEL_CH4.

void LL_TIM_IC_StructInit ( LL_TIM_IC_InitTypeDef * TIM_ICInitStruct )

Set the fields of the TIMx input channel configuration data structure to their default values.

Parameters:
TIM_ICInitStruct pointer to a LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
Return values:
None

Definition at line 530 of file stm32f3xx_ll_tim.c.

References LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, LL_TIM_ACTIVEINPUT_DIRECTTI, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_InitTypeDef * | TIM_InitStruct
 | ) |  |

Configure the TIMx time base unit.

Parameters:
TIMx | Timer Instance
TIM_InitStruct | pointer to a LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 411 of file stm32f3xx_ll_tim.c.

References assert_param, LL_TIM_InitTypeDef::Autoreload, LL_TIM_InitTypeDef::ClockDivision, LL_TIM_InitTypeDef::CounterMode, IS_LL_TIM_CLOCKDIVISION, IS_LL_TIM_COUNTERMODE, LL_TIM_GenerateEvent_UPDATE(), LL_TIM_ReadReg, LL_TIM_SetAutoReload(), LL_TIM_SetPrescaler(), LL_TIM_SetRepetitionCounter(), LL_TIM_WriteReg, LL_TIM_InitTypeDef::Prescaler, and LL_TIM_InitTypeDef::RepetitionCounter.

ErrorStatus LL_TIM_OC_Init | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OC_InitStruct
 | ) |  |

Configure the TIMx output channel.

Parameters:
TIMx | Timer Instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
TIM_OC_InitStruct | pointer to a LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
Note:
OC5 and OC6 are not available for all F3 devices
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx output channel is initialized
  • ERROR: TIMx output channel is not initialized

Definition at line 491 of file stm32f3xx_ll_tim.c.

References LL_TIM_CHANNEL_CH1, LL_TIM_CHANNEL_CH2, LL_TIM_CHANNEL_CH3, LL_TIM_CHANNEL_CH4, OC1Config(), OC2Config(), OC3Config(), and OC4Config().

void LL_TIM_OC_StructInit ( LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct )

Set the fields of the TIMx output channel configuration data structure to their default values.

Parameters:
TIM_OC_InitStruct pointer to a LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
Return values:
None

Definition at line 462 of file stm32f3xx_ll_tim.c.

References LL_TIM_OC_InitTypeDef::CompareValue, LL_TIM_OCIDLESTATE_LOW, LL_TIM_OCMODE_FROZEN, LL_TIM_OCPOLARITY_HIGH, LL_TIM_OCSTATE_DISABLE, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

void LL_TIM_StructInit ( LL_TIM_InitTypeDef * TIM_InitStruct )

Set the fields of the time base unit configuration data structure to their default values.

Parameters:
TIM_InitStruct pointer to a LL_TIM_InitTypeDef structure (time base unit configuration data structure)
Return values:
None

Definition at line 393 of file stm32f3xx_ll_tim.c.

References LL_TIM_InitTypeDef::Autoreload, LL_TIM_InitTypeDef::ClockDivision, LL_TIM_InitTypeDef::CounterMode, LL_TIM_CLOCKDIVISION_DIV1, LL_TIM_COUNTERMODE_UP, LL_TIM_InitTypeDef::Prescaler, and LL_TIM_InitTypeDef::RepetitionCounter.

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART

Modules
USART
STM32F3xx_LL_Driver

Modules

USART Private Constants
USART Private Macros
USART Exported Init structures
USART Exported Constants
USART Exported Macros
USART Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for USART registers.

Register | Bit | Function
BRR | BRR | LL_USART_GetBaudRate
 |  | LL_USART_SetBaudRate
CR1 | CMIE | LL_USART_DisableIT_CM
 |  | LL_USART_EnableIT_CM
 |  | LL_USART_IsEnabledIT_CM
 | DEAT | LL_USART_GetDEAssertionTime
 |  | LL_USART_SetDEAssertionTime
 | DEDT | LL_USART_GetDEDeassertionTime
 |  | LL_USART_SetDEDeassertionTime
 | EOBIE | LL_USART_DisableIT_EOB
 |  | LL_USART_EnableIT_EOB
 |  | LL_USART_IsEnabledIT_EOB
 | IDLEIE | LL_USART_DisableIT_IDLE
 |  | LL_USART_EnableIT_IDLE
 |  | LL_USART_IsEnabledIT_IDLE
 | M0 | LL_USART_ConfigCharacter
 |  | LL_USART_GetDataWidth
 |  | LL_USART_SetDataWidth
 | M1 | LL_USART_ConfigCharacter
 |  | LL_USART_GetDataWidth
 |  | LL_USART_SetDataWidth
 | MME | LL_USART_DisableMuteMode
 |  | LL_USART_EnableMuteMode
 |  | LL_USART_IsEnabledMuteMode
 | OVER8 | LL_USART_GetOverSampling
 |  | LL_USART_SetOverSampling
 | PCE | LL_USART_ConfigCharacter
 |  | LL_USART_GetParity
 |  | LL_USART_SetParity
 | PEIE | LL_USART_DisableIT_PE
 |  | LL_USART_EnableIT_PE
 |  | LL_USART_IsEnabledIT_PE
 | PS | LL_USART_ConfigCharacter
 |  | LL_USART_GetParity
 |  | LL_USART_SetParity
 | RE | LL_USART_DisableDirectionRx
 |  | LL_USART_EnableDirectionRx
 |  | LL_USART_GetTransferDirection
 |  | LL_USART_SetTransferDirection
 | RTOIE | LL_USART_DisableIT_RTO
 |  | LL_USART_EnableIT_RTO
 |  | LL_USART_IsEnabledIT_RTO
 | RXNEIE | LL_USART_DisableIT_RXNE
 |  | LL_USART_EnableIT_RXNE
 |  | LL_USART_IsEnabledIT_RXNE
 | TCIE | LL_USART_DisableIT_TC
 |  | LL_USART_EnableIT_TC
 |  | LL_USART_IsEnabledIT_TC
 | TE | LL_USART_DisableDirectionTx
 |  | LL_USART_EnableDirectionTx
 |  | LL_USART_GetTransferDirection
 |  | LL_USART_SetTransferDirection
 | TXEIE | LL_USART_DisableIT_TXE
 |  | LL_USART_EnableIT_TXE
 |  | LL_USART_IsEnabledIT_TXE
 | UE | LL_USART_Disable
 |  | LL_USART_Enable
 |  | LL_USART_IsEnabled
 | UESM | LL_USART_DisableInStopMode
 |  | LL_USART_EnableInStopMode
 |  | LL_USART_IsEnabledInStopMode
 | WAKE | LL_USART_GetWakeUpMethod
 |  | LL_USART_SetWakeUpMethod
CR2 | ABREN | LL_USART_DisableAutoBaudRate
 |  | LL_USART_EnableAutoBaudRate
 |  | LL_USART_IsEnabledAutoBaud
 | ABRMODE | LL_USART_GetAutoBaudRateMode
 |  | LL_USART_SetAutoBaudRateMode
 | ADD | LL_USART_ConfigNodeAddress
 |  | LL_USART_GetNodeAddress
 | ADDM7 | LL_USART_ConfigNodeAddress
 |  | LL_USART_GetNodeAddressLen
 | CLKEN | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableSCLKOutput
 |  | LL_USART_EnableSCLKOutput
 |  | LL_USART_IsEnabledSCLKOutput
 | CPHA | LL_USART_ConfigClock
 |  | LL_USART_GetClockPhase
 |  | LL_USART_SetClockPhase
 | CPOL | LL_USART_ConfigClock
 |  | LL_USART_GetClockPolarity
 |  | LL_USART_SetClockPolarity
 | DATAINV | LL_USART_GetBinaryDataLogic
 |  | LL_USART_SetBinaryDataLogic
 | LBCL | LL_USART_ConfigClock
 |  | LL_USART_GetLastClkPulseOutput
 |  | LL_USART_SetLastClkPulseOutput
 | LBDIE | LL_USART_DisableIT_LBD
 |  | LL_USART_EnableIT_LBD
 |  | LL_USART_IsEnabledIT_LBD
 | LBDL | LL_USART_GetLINBrkDetectionLen
 |  | LL_USART_SetLINBrkDetectionLen
 | LINEN | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableLIN
 |  | LL_USART_EnableLIN
 |  | LL_USART_IsEnabledLIN
 | MSBFIRST | LL_USART_GetTransferBitOrder
 |  | LL_USART_SetTransferBitOrder
 | RTOEN | LL_USART_DisableRxTimeout
 |  | LL_USART_EnableRxTimeout
 |  | LL_USART_IsEnabledRxTimeout
 | RXINV | LL_USART_GetRXPinLevel
 |  | LL_USART_SetRXPinLevel
 | STOP | LL_USART_ConfigCharacter
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_GetStopBitsLength
 |  | LL_USART_SetStopBitsLength
 | SWAP | LL_USART_GetTXRXSwap
 |  | LL_USART_SetTXRXSwap
 | TXINV | LL_USART_GetTXPinLevel
 |  | LL_USART_SetTXPinLevel
CR3 | CTSE | LL_USART_DisableCTSHWFlowCtrl
 |  | LL_USART_EnableCTSHWFlowCtrl
 |  | LL_USART_GetHWFlowCtrl
 |  | LL_USART_SetHWFlowCtrl
 | CTSIE | LL_USART_DisableIT_CTS
 |  | LL_USART_EnableIT_CTS
 |  | LL_USART_IsEnabledIT_CTS
 | DDRE | LL_USART_DisableDMADeactOnRxErr
 |  | LL_USART_EnableDMADeactOnRxErr
 |  | LL_USART_IsEnabledDMADeactOnRxErr
 | DEM | LL_USART_DisableDEMode
 |  | LL_USART_EnableDEMode
 |  | LL_USART_IsEnabledDEMode
 | DEP | LL_USART_GetDESignalPolarity
 |  | LL_USART_SetDESignalPolarity
 | DMAR | LL_USART_DisableDMAReq_RX
 |  | LL_USART_EnableDMAReq_RX
 |  | LL_USART_IsEnabledDMAReq_RX
 | DMAT | LL_USART_DisableDMAReq_TX
 |  | LL_USART_EnableDMAReq_TX
 |  | LL_USART_IsEnabledDMAReq_TX
 | EIE | LL_USART_DisableIT_ERROR
 |  | LL_USART_EnableIT_ERROR
 |  | LL_USART_IsEnabledIT_ERROR
 | HDSEL | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableHalfDuplex
 |  | LL_USART_EnableHalfDuplex
 |  | LL_USART_IsEnabledHalfDuplex
 | IREN | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableIrda
 |  | LL_USART_EnableIrda
 |  | LL_USART_IsEnabledIrda
 | IRLP | LL_USART_GetIrdaPowerMode
 |  | LL_USART_SetIrdaPowerMode
 | NACK | LL_USART_DisableSmartcardNACK
 |  | LL_USART_EnableSmartcardNACK
 |  | LL_USART_IsEnabledSmartcardNACK
 | ONEBIT | LL_USART_DisableOneBitSamp
 |  | LL_USART_EnableOneBitSamp
 |  | LL_USART_IsEnabledOneBitSamp
 | OVRDIS | LL_USART_DisableOverrunDetect
 |  | LL_USART_EnableOverrunDetect
 |  | LL_USART_IsEnabledOverrunDetect
 | RTSE | LL_USART_DisableRTSHWFlowCtrl
 |  | LL_USART_EnableRTSHWFlowCtrl
 |  | LL_USART_GetHWFlowCtrl
 |  | LL_USART_SetHWFlowCtrl
 | SCARCNT | LL_USART_GetSmartcardAutoRetryCount
 |  | LL_USART_SetSmartcardAutoRetryCount
 | SCEN | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableSmartcard
 |  | LL_USART_EnableSmartcard
 |  | LL_USART_IsEnabledSmartcard
 | WUFIE | LL_USART_DisableIT_WKUP
 |  | LL_USART_EnableIT_WKUP
 |  | LL_USART_IsEnabledIT_WKUP
 | WUS | LL_USART_GetWKUPType
 |  | LL_USART_SetWKUPType
GTPR | GT | LL_USART_GetSmartcardGuardTime
 |  | LL_USART_SetSmartcardGuardTime
 | PSC | LL_USART_GetIrdaPrescaler
 |  | LL_USART_GetSmartcardPrescaler
 |  | LL_USART_SetIrdaPrescaler
 |  | LL_USART_SetSmartcardPrescaler
ICR | CMCF | LL_USART_ClearFlag_CM
 | CTSCF | LL_USART_ClearFlag_nCTS
 | EOBCF | LL_USART_ClearFlag_EOB
 | FECF | LL_USART_ClearFlag_FE
 | IDLECF | LL_USART_ClearFlag_IDLE
 | LBDCF | LL_USART_ClearFlag_LBD
 | NCF | LL_USART_ClearFlag_NE
 | ORECF | LL_USART_ClearFlag_ORE
 | PECF | LL_USART_ClearFlag_PE
 | RTOCF | LL_USART_ClearFlag_RTO
 | TCCF | LL_USART_ClearFlag_TC
 | WUCF | LL_USART_ClearFlag_WKUP
ISR | ABRE | LL_USART_IsActiveFlag_ABRE
 | ABRF | LL_USART_IsActiveFlag_ABR
 | BUSY | LL_USART_IsActiveFlag_BUSY
 | CMF | LL_USART_IsActiveFlag_CM
 | CTS | LL_USART_IsActiveFlag_CTS
 | CTSIF | LL_USART_IsActiveFlag_nCTS
 | EOBF | LL_USART_IsActiveFlag_EOB
 | FE | LL_USART_IsActiveFlag_FE
 | IDLE | LL_USART_IsActiveFlag_IDLE
 | LBDF | LL_USART_IsActiveFlag_LBD
 | NF | LL_USART_IsActiveFlag_NE
 | ORE | LL_USART_IsActiveFlag_ORE
 | PE | LL_USART_IsActiveFlag_PE
 | REACK | LL_USART_IsActiveFlag_REACK
 | RTOF | LL_USART_IsActiveFlag_RTO
 | RWU | LL_USART_IsActiveFlag_RWU
 | RXNE | LL_USART_IsActiveFlag_RXNE
 | SBKF | LL_USART_IsActiveFlag_SBK
 | TC | LL_USART_IsActiveFlag_TC
 | TEACK | LL_USART_IsActiveFlag_TEACK
 | TXE | LL_USART_IsActiveFlag_TXE
 | WUF | LL_USART_IsActiveFlag_WKUP
RDR | RDR | LL_USART_DMA_GetRegAddr
 |  | LL_USART_ReceiveData8
 |  | LL_USART_ReceiveData9
RQR | ABRRQ | LL_USART_RequestAutoBaudRate
 | MMRQ | LL_USART_RequestEnterMuteMode
 | RXFRQ | LL_USART_RequestRxDataFlush
 | SBKRQ | LL_USART_RequestBreakSending
 | TXFRQ | LL_USART_RequestTxDataFlush
RTOR | BLEN | LL_USART_GetBlockLength
 |  | LL_USART_SetBlockLength
 | RTO | LL_USART_GetRxTimeout
 |  | LL_USART_SetRxTimeout
TDR | TDR | LL_USART_DMA_GetRegAddr
 |  | LL_USART_TransmitData8
 |  | LL_USART_TransmitData9
Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Private Constants

USART Private Constants
USART
Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Private Macros

Defines
USART Private Macros
USART

Defines

#define | IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 9000000U)
#define | IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
#define | IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_USART_DIRECTION(__VALUE__)
#define | IS_LL_USART_PARITY(__VALUE__)
#define | IS_LL_USART_DATAWIDTH(__VALUE__)
#define | IS_LL_USART_OVERSAMPLING(__VALUE__)
#define | IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__)
#define | IS_LL_USART_CLOCKPHASE(__VALUE__)
#define | IS_LL_USART_CLOCKPOLARITY(__VALUE__)
#define | IS_LL_USART_CLOCKOUTPUT(__VALUE__)
#define | IS_LL_USART_STOPBITS(__VALUE__)
#define | IS_LL_USART_HWCONTROL(__VALUE__)

Define Documentation

#define IS_LL_USART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) <= 9000000U)

Definition at line 76 of file stm32f3xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_BRR_MAX ( __VALUE__ ) ((__VALUE__) <= 0x0000FFFFU)

Definition at line 82 of file stm32f3xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_BRR_MIN ( __VALUE__ ) ((__VALUE__) >= 16U)

Definition at line 79 of file stm32f3xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_CLOCKOUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_CLOCK_DISABLE) \
                                         || ((__VALUE__) == LL_USART_CLOCK_ENABLE))

Definition at line 114 of file stm32f3xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_CLOCKPHASE ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PHASE_1EDGE) \
                                        || ((__VALUE__) == LL_USART_PHASE_2EDGE))

Definition at line 108 of file stm32f3xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_CLOCKPOLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_POLARITY_LOW) \
                                           || ((__VALUE__) == LL_USART_POLARITY_HIGH))

Definition at line 111 of file stm32f3xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_DATAWIDTH_8B) \
                                       || ((__VALUE__) == LL_USART_DATAWIDTH_9B))

Definition at line 98 of file stm32f3xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_DIRECTION_NONE) \
                                       || ((__VALUE__) == LL_USART_DIRECTION_RX) \
                                       || ((__VALUE__) == LL_USART_DIRECTION_TX) \
                                       || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))

Definition at line 84 of file stm32f3xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_HWCONTROL ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_HWCONTROL_NONE) \
                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
                                       || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))

Definition at line 122 of file stm32f3xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_LASTBITCLKOUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
                                              || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))

Definition at line 105 of file stm32f3xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_OVERSAMPLING ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_OVERSAMPLING_16) \
                                          || ((__VALUE__) == LL_USART_OVERSAMPLING_8))

Definition at line 102 of file stm32f3xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_PARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PARITY_NONE) \
                                    || ((__VALUE__) == LL_USART_PARITY_EVEN) \
                                    || ((__VALUE__) == LL_USART_PARITY_ODD))

Definition at line 89 of file stm32f3xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_STOPBITS ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_STOPBITS_0_5) \
                                      || ((__VALUE__) == LL_USART_STOPBITS_1) \
                                      || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
                                      || ((__VALUE__) == LL_USART_STOPBITS_2))

Definition at line 117 of file stm32f3xx_ll_usart.c.

Referenced by LL_USART_Init().

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_USART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_USART_InitTypeDef Struct Reference
USART Exported Init structures

LL USART Init Structure definition. More...

#include <stm32f3xx_ll_usart.h>

Data Fields

uint32_t | BaudRate
uint32_t | DataWidth
uint32_t | StopBits
uint32_t | Parity
uint32_t | TransferDirection
uint32_t | HardwareFlowControl
uint32_t | OverSampling

Detailed Description

LL USART Init Structure definition.

Definition at line 87 of file stm32f3xx_ll_usart.h.

Field Documentation

uint32_t LL_USART_InitTypeDef::BaudRate

This field defines expected Usart communication baud rate.

This feature can be modified afterwards using unitary function LL_USART_SetBaudRate().

Definition at line 89 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::DataWidth

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_USART_SetDataWidth().

Definition at line 93 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::HardwareFlowControl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of Hardware Control.

This feature can be modified afterwards using unitary function LL_USART_SetHWFlowCtrl().

Definition at line 113 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::OverSampling

Specifies whether USART oversampling mode is 16 or 8. This parameter can be a value of Oversampling.

This feature can be modified afterwards using unitary function LL_USART_SetOverSampling().

Definition at line 118 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of Parity Control.

This feature can be modified afterwards using unitary function LL_USART_SetParity().

Definition at line 103 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of Stop Bits.

This feature can be modified afterwards using unitary function LL_USART_SetStopBitsLength().

Definition at line 98 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::TransferDirection

Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of Communication Direction.

This feature can be modified afterwards using unitary function LL_USART_SetTransferDirection().

Definition at line 108 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_usart.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_USART_ClockInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_USART_ClockInitTypeDef Struct Reference
USART Exported Init structures

LL USART Clock Init Structure definition. More...

#include <stm32f3xx_ll_usart.h>

Data Fields

uint32_t | ClockOutput
uint32_t | ClockPolarity
uint32_t | ClockPhase
uint32_t | LastBitClockPulse

Detailed Description

LL USART Clock Init Structure definition.

Definition at line 128 of file stm32f3xx_ll_usart.h.

Field Documentation

uint32_t LL_USART_ClockInitTypeDef::ClockOutput

Specifies whether the USART clock is enabled or disabled. This parameter can be a value of Clock Signal.

USART HW configuration can be modified afterwards using unitary functions LL_USART_EnableSCLKOutput() or LL_USART_DisableSCLKOutput(). For more details, refer to description of this function.

Definition at line 130 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::ClockPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of Clock Phase.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetClockPhase(). For more details, refer to description of this function.

Definition at line 143 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::ClockPolarity

Specifies the steady state of the serial clock. This parameter can be a value of Clock Polarity.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetClockPolarity(). For more details, refer to description of this function.

Definition at line 137 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::LastBitClockPulse

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of Last Clock Pulse.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetLastClkPulseOutput(). For more details, refer to description of this function.

Definition at line 149 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_usart.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
USART Exported Constants

Flags defines which can be used with LL_USART_WriteReg function. More...

Defines

#define | LL_USART_ICR_PECF USART_ICR_PECF
#define | LL_USART_ICR_FECF USART_ICR_FECF
#define | LL_USART_ICR_NCF USART_ICR_NCF
#define | LL_USART_ICR_ORECF USART_ICR_ORECF
#define | LL_USART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_USART_ICR_TCCF USART_ICR_TCCF
#define | LL_USART_ICR_LBDCF USART_ICR_LBDCF
#define | LL_USART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_USART_ICR_RTOCF USART_ICR_RTOCF
#define | LL_USART_ICR_EOBCF USART_ICR_EOBCF
#define | LL_USART_ICR_CMCF USART_ICR_CMCF
#define | LL_USART_ICR_WUCF USART_ICR_WUCF

Detailed Description

Flags defines which can be used with LL_USART_WriteReg function.

Define Documentation

#define LL_USART_ICR_CMCF USART_ICR_CMCF

Character match flag

Definition at line 182 of file stm32f3xx_ll_usart.h.

#define LL_USART_ICR_CTSCF USART_ICR_CTSCF

CTS flag

Definition at line 179 of file stm32f3xx_ll_usart.h.

#define LL_USART_ICR_EOBCF USART_ICR_EOBCF

End of block flag

Definition at line 181 of file stm32f3xx_ll_usart.h.

#define LL_USART_ICR_FECF USART_ICR_FECF

Framing error flag

Definition at line 173 of file stm32f3xx_ll_usart.h.

#define LL_USART_ICR_IDLECF USART_ICR_IDLECF

Idle line detected flag

Definition at line 176 of file stm32f3xx_ll_usart.h.

#define LL_USART_ICR_LBDCF USART_ICR_LBDCF

LIN break detection flag

Definition at line 178 of file stm32f3xx_ll_usart.h.

#define LL_USART_ICR_NCF USART_ICR_NCF

Noise detected flag

Definition at line 174 of file stm32f3xx_ll_usart.h.

#define LL_USART_ICR_ORECF USART_ICR_ORECF

Overrun error flag

Definition at line 175 of file stm32f3xx_ll_usart.h.

#define LL_USART_ICR_PECF USART_ICR_PECF

Parity error flag

Definition at line 172 of file stm32f3xx_ll_usart.h.

#define LL_USART_ICR_RTOCF USART_ICR_RTOCF

Receiver timeout flag

Definition at line 180 of file stm32f3xx_ll_usart.h.

#define LL_USART_ICR_TCCF USART_ICR_TCCF

Transmission complete flag

Definition at line 177 of file stm32f3xx_ll_usart.h.

#define LL_USART_ICR_WUCF USART_ICR_WUCF

Wakeup from Stop mode flag

Definition at line 183 of file stm32f3xx_ll_usart.h.

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STM32F373xC HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
USART Exported Constants

Flags defines which can be used with LL_USART_ReadReg function. More...

Defines

#define | LL_USART_ISR_PE USART_ISR_PE
#define | LL_USART_ISR_FE USART_ISR_FE
#define | LL_USART_ISR_NE USART_ISR_NE
#define | LL_USART_ISR_ORE USART_ISR_ORE
#define | LL_USART_ISR_IDLE USART_ISR_IDLE
#define | LL_USART_ISR_RXNE USART_ISR_RXNE
#define | LL_USART_ISR_TC USART_ISR_TC
#define | LL_USART_ISR_TXE USART_ISR_TXE
#define | LL_USART_ISR_LBDF USART_ISR_LBDF
#define | LL_USART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_USART_ISR_CTS USART_ISR_CTS
#define | LL_USART_ISR_RTOF USART_ISR_RTOF
#define | LL_USART_ISR_EOBF USART_ISR_EOBF
#define | LL_USART_ISR_ABRE USART_ISR_ABRE
#define | LL_USART_ISR_ABRF USART_ISR_ABRF
#define | LL_USART_ISR_BUSY USART_ISR_BUSY
#define | LL_USART_ISR_CMF USART_ISR_CMF
#define | LL_USART_ISR_SBKF USART_ISR_SBKF
#define | LL_USART_ISR_RWU USART_ISR_RWU
#define | LL_USART_ISR_WUF USART_ISR_WUF
#define | LL_USART_ISR_TEACK USART_ISR_TEACK
#define | LL_USART_ISR_REACK USART_ISR_REACK

Detailed Description

Flags defines which can be used with LL_USART_ReadReg function.

Define Documentation

#define LL_USART_ISR_ABRE USART_ISR_ABRE

Auto baud rate error flag

Definition at line 205 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_ABRF USART_ISR_ABRF

Auto baud rate flag

Definition at line 206 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_BUSY USART_ISR_BUSY

Busy flag

Definition at line 207 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_CMF USART_ISR_CMF

Character match flag

Definition at line 208 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_CTS USART_ISR_CTS

CTS flag

Definition at line 202 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_CTSIF USART_ISR_CTSIF

CTS interrupt flag

Definition at line 201 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_EOBF USART_ISR_EOBF

End of block flag

Definition at line 204 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_FE USART_ISR_FE

Framing error flag

Definition at line 193 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_IDLE USART_ISR_IDLE

Idle line detected flag

Definition at line 196 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_LBDF USART_ISR_LBDF

LIN break detection flag

Definition at line 200 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_NE USART_ISR_NE

Noise detected flag

Definition at line 194 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_ORE USART_ISR_ORE

Overrun error flag

Definition at line 195 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_PE USART_ISR_PE

Parity error flag

Definition at line 192 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_REACK USART_ISR_REACK

Receive enable acknowledge flag

Definition at line 213 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_RTOF USART_ISR_RTOF

Receiver timeout flag

Definition at line 203 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_RWU USART_ISR_RWU

Receiver wakeup from Mute mode flag

Definition at line 210 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_RXNE USART_ISR_RXNE

Read data register not empty flag

Definition at line 197 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_SBKF USART_ISR_SBKF

Send break flag

Definition at line 209 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_TC USART_ISR_TC

Transmission complete flag

Definition at line 198 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_TEACK USART_ISR_TEACK

Transmit enable acknowledge flag

Definition at line 212 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_TXE USART_ISR_TXE

Transmit data register empty flag

Definition at line 199 of file stm32f3xx_ll_usart.h.

#define LL_USART_ISR_WUF USART_ISR_WUF

Wakeup from Stop mode flag

Definition at line 211 of file stm32f3xx_ll_usart.h.

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STM32F373xC HAL User Manual: IT Defines

Defines
IT Defines
USART Exported Constants

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions. More...

Defines

#define | LL_USART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_USART_CR1_RXNEIE USART_CR1_RXNEIE
#define | LL_USART_CR1_TCIE USART_CR1_TCIE
#define | LL_USART_CR1_TXEIE USART_CR1_TXEIE
#define | LL_USART_CR1_PEIE USART_CR1_PEIE
#define | LL_USART_CR1_CMIE USART_CR1_CMIE
#define | LL_USART_CR1_RTOIE USART_CR1_RTOIE
#define | LL_USART_CR1_EOBIE USART_CR1_EOBIE
#define | LL_USART_CR2_LBDIE USART_CR2_LBDIE
#define | LL_USART_CR3_EIE USART_CR3_EIE
#define | LL_USART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_USART_CR3_WUFIE USART_CR3_WUFIE

Detailed Description

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions.

Define Documentation

#define LL_USART_CR1_CMIE USART_CR1_CMIE

Character match interrupt enable

Definition at line 227 of file stm32f3xx_ll_usart.h.

#define LL_USART_CR1_EOBIE USART_CR1_EOBIE

End of Block interrupt enable

Definition at line 229 of file stm32f3xx_ll_usart.h.

#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE

IDLE interrupt enable

Definition at line 222 of file stm32f3xx_ll_usart.h.

#define LL_USART_CR1_PEIE USART_CR1_PEIE

Parity error

Definition at line 226 of file stm32f3xx_ll_usart.h.

#define LL_USART_CR1_RTOIE USART_CR1_RTOIE

Receiver timeout interrupt enable

Definition at line 228 of file stm32f3xx_ll_usart.h.

#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE

Read data register not empty interrupt enable

Definition at line 223 of file stm32f3xx_ll_usart.h.

#define LL_USART_CR1_TCIE USART_CR1_TCIE

Transmission complete interrupt enable

Definition at line 224 of file stm32f3xx_ll_usart.h.

#define LL_USART_CR1_TXEIE USART_CR1_TXEIE

Transmit data register empty interrupt enable

Definition at line 225 of file stm32f3xx_ll_usart.h.

#define LL_USART_CR2_LBDIE USART_CR2_LBDIE

LIN break detection interrupt enable

Definition at line 230 of file stm32f3xx_ll_usart.h.

#define LL_USART_CR3_CTSIE USART_CR3_CTSIE

CTS interrupt enable

Definition at line 232 of file stm32f3xx_ll_usart.h.

#define LL_USART_CR3_EIE USART_CR3_EIE

Error interrupt enable

Definition at line 231 of file stm32f3xx_ll_usart.h.

#define LL_USART_CR3_WUFIE USART_CR3_WUFIE

Wakeup from Stop mode interrupt enable

Definition at line 233 of file stm32f3xx_ll_usart.h.

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STM32F373xC HAL User Manual: Communication Direction

Defines
Communication Direction
USART Exported Constants

Defines

#define | LL_USART_DIRECTION_NONE 0x00000000U
#define | LL_USART_DIRECTION_RX USART_CR1_RE
#define | LL_USART_DIRECTION_TX USART_CR1_TE
#define | LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define LL_USART_DIRECTION_NONE 0x00000000U

Transmitter and Receiver are disabled

Definition at line 241 of file stm32f3xx_ll_usart.h.

#define LL_USART_DIRECTION_RX USART_CR1_RE

Transmitter is disabled and Receiver is enabled

Definition at line 242 of file stm32f3xx_ll_usart.h.

#define LL_USART_DIRECTION_TX USART_CR1_TE

Transmitter is enabled and Receiver is disabled

Definition at line 243 of file stm32f3xx_ll_usart.h.

#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Transmitter and Receiver are enabled

Definition at line 244 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_StructInit().

Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Parity Control

Defines
Parity Control
USART Exported Constants

Defines

#define | LL_USART_PARITY_NONE 0x00000000U
#define | LL_USART_PARITY_EVEN USART_CR1_PCE
#define | LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define LL_USART_PARITY_EVEN USART_CR1_PCE

Parity control enabled and Even Parity is selected

Definition at line 253 of file stm32f3xx_ll_usart.h.

#define LL_USART_PARITY_NONE 0x00000000U

Parity control disabled

Definition at line 252 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Parity control enabled and Odd Parity is selected

Definition at line 254 of file stm32f3xx_ll_usart.h.

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STM32F373xC HAL User Manual: Wakeup

Defines
Wakeup
USART Exported Constants

Defines

#define | LL_USART_WAKEUP_IDLELINE 0x00000000U
#define | LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

Define Documentation

#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

USART wake up from Mute mode on Address Mark

Definition at line 263 of file stm32f3xx_ll_usart.h.

#define LL_USART_WAKEUP_IDLELINE 0x00000000U

USART wake up from Mute mode on Idle Line

Definition at line 262 of file stm32f3xx_ll_usart.h.

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STM32F373xC HAL User Manual: Datawidth

Defines
Datawidth
USART Exported Constants

Defines

#define | LL_USART_DATAWIDTH_8B 0x00000000U
#define | LL_USART_DATAWIDTH_9B USART_CR1_M

Define Documentation

#define LL_USART_DATAWIDTH_8B 0x00000000U

8 bits word length : Start bit, 8 data bits, n stop bits

Definition at line 276 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_DATAWIDTH_9B USART_CR1_M

9 bits word length : Start bit, 9 data bits, n stop bits

Definition at line 277 of file stm32f3xx_ll_usart.h.

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STM32F373xC HAL User Manual: Oversampling

Defines
Oversampling
USART Exported Constants

Defines

#define | LL_USART_OVERSAMPLING_16 0x00000000U
#define | LL_USART_OVERSAMPLING_8 USART_CR1_OVER8

Define Documentation

#define LL_USART_OVERSAMPLING_16 0x00000000U

Oversampling by 16

Definition at line 286 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8

Oversampling by 8

Definition at line 287 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_GetBaudRate(), and LL_USART_SetBaudRate().

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Clock Signal

Defines
Clock Signal
USART Exported Constants

Defines

#define | LL_USART_CLOCK_DISABLE 0x00000000U
#define | LL_USART_CLOCK_ENABLE USART_CR2_CLKEN

Define Documentation

#define LL_USART_CLOCK_DISABLE 0x00000000U

Clock signal not provided

Definition at line 297 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN

Clock signal provided

Definition at line 298 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Last Clock Pulse

Defines
Last Clock Pulse
USART Exported Constants

Defines

#define | LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U
#define | LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL

Define Documentation

#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U

The clock pulse of the last data bit is not output to the SCLK pin

Definition at line 307 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL

The clock pulse of the last data bit is output to the SCLK pin

Definition at line 308 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Clock Phase

Defines
Clock Phase
USART Exported Constants

Defines

#define | LL_USART_PHASE_1EDGE 0x00000000U
#define | LL_USART_PHASE_2EDGE USART_CR2_CPHA

Define Documentation

#define LL_USART_PHASE_1EDGE 0x00000000U

The first clock transition is the first data capture edge

Definition at line 316 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

#define LL_USART_PHASE_2EDGE USART_CR2_CPHA

The second clock transition is the first data capture edge

Definition at line 317 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Clock Polarity

Defines
Clock Polarity
USART Exported Constants

Defines

#define | LL_USART_POLARITY_LOW 0x00000000U
#define | LL_USART_POLARITY_HIGH USART_CR2_CPOL

Define Documentation

#define LL_USART_POLARITY_HIGH USART_CR2_CPOL

Steady high value on SCLK pin outside transmission window

Definition at line 326 of file stm32f3xx_ll_usart.h.

#define LL_USART_POLARITY_LOW 0x00000000U

Steady low value on SCLK pin outside transmission window

Definition at line 325 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Stop Bits

Defines
Stop Bits
USART Exported Constants

Defines

#define | LL_USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | LL_USART_STOPBITS_1 0x00000000U
#define | LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | LL_USART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0

0.5 stop bit

Definition at line 334 of file stm32f3xx_ll_usart.h.

#define LL_USART_STOPBITS_1 0x00000000U

1 stop bit

Definition at line 335 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

1.5 stop bits

Definition at line 336 of file stm32f3xx_ll_usart.h.

#define LL_USART_STOPBITS_2 USART_CR2_STOP_1

2 stop bits

Definition at line 337 of file stm32f3xx_ll_usart.h.

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STM32F373xC HAL User Manual: TX RX Pins Swap

Defines
TX RX Pins Swap
USART Exported Constants

Defines

#define | LL_USART_TXRX_STANDARD 0x00000000U
#define | LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)

Define Documentation

#define LL_USART_TXRX_STANDARD 0x00000000U

TX/RX pins are used as defined in standard pinout

Definition at line 345 of file stm32f3xx_ll_usart.h.

#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)

TX and RX pins functions are swapped.

Definition at line 346 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RX Pin Active Level Inversion

Defines
RX Pin Active Level Inversion
USART Exported Constants

Defines

#define | LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

Define Documentation

#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

RX pin signal values are inverted.

Definition at line 355 of file stm32f3xx_ll_usart.h.

#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U

RX pin signal works using the standard logic levels

Definition at line 354 of file stm32f3xx_ll_usart.h.

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STM32F373xC HAL User Manual: TX Pin Active Level Inversion

Defines
TX Pin Active Level Inversion
USART Exported Constants

Defines

#define | LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

Define Documentation

#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

TX pin signal values are inverted.

Definition at line 364 of file stm32f3xx_ll_usart.h.

#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U

TX pin signal works using the standard logic levels

Definition at line 363 of file stm32f3xx_ll_usart.h.

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STM32F373xC HAL User Manual: Binary Data Inversion

Defines
Binary Data Inversion
USART Exported Constants

Defines

#define | LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Define Documentation

#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted.

Definition at line 373 of file stm32f3xx_ll_usart.h.

#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U

Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)

Definition at line 372 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Bit Order

Defines
Bit Order
USART Exported Constants

Defines

#define | LL_USART_BITORDER_LSBFIRST 0x00000000U
#define | LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

Define Documentation

#define LL_USART_BITORDER_LSBFIRST 0x00000000U

data is transmitted/received with data bit 0 first, following the start bit

Definition at line 381 of file stm32f3xx_ll_usart.h.

#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

data is transmitted/received with the MSB first, following the start bit

Definition at line 382 of file stm32f3xx_ll_usart.h.

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STM32F373xC HAL User Manual: Autobaud Detection

Defines
Autobaud Detection
USART Exported Constants

Defines

#define | LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U
#define | LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0
#define | LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1
#define | LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)

Define Documentation

#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)

0x55 frame detection

Definition at line 393 of file stm32f3xx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1

0x7F frame detection

Definition at line 392 of file stm32f3xx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0

Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx

Definition at line 391 of file stm32f3xx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U

Measurement of the start bit is used to detect the baud rate

Definition at line 390 of file stm32f3xx_ll_usart.h.

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STM32F373xC HAL User Manual: Address Length Detection

Defines
Address Length Detection
USART Exported Constants

Defines

#define | LL_USART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7

Define Documentation

#define LL_USART_ADDRESS_DETECT_4B 0x00000000U

4-bit address detection method selected

Definition at line 401 of file stm32f3xx_ll_usart.h.

#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7

7-bit address detection (in 8-bit data mode) method selected

Definition at line 402 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Hardware Control

Defines
Hardware Control
USART Exported Constants

Defines

#define | LL_USART_HWCONTROL_NONE 0x00000000U
#define | LL_USART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_USART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Define Documentation

#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE

CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0)

Definition at line 412 of file stm32f3xx_ll_usart.h.

#define LL_USART_HWCONTROL_NONE 0x00000000U

CTS and RTS hardware flow control disabled

Definition at line 410 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE

RTS output enabled, data is only requested when there is space in the receive buffer

Definition at line 411 of file stm32f3xx_ll_usart.h.

#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

CTS and RTS hardware flow control enabled

Definition at line 413 of file stm32f3xx_ll_usart.h.

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STM32F373xC HAL User Manual: Wakeup Activation

Defines
Wakeup Activation
USART Exported Constants

Defines

#define | LL_USART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Define Documentation

#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U

Wake up active on address match

Definition at line 421 of file stm32f3xx_ll_usart.h.

#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Wake up active on RXNE

Definition at line 423 of file stm32f3xx_ll_usart.h.

#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1

Wake up active on Start bit detection

Definition at line 422 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IrDA Power

Defines
IrDA Power
USART Exported Constants

Defines

#define | LL_USART_IRDA_POWER_NORMAL 0x00000000U
#define | LL_USART_IRDA_POWER_LOW USART_CR3_IRLP

Define Documentation

#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP

IrDA low power mode

Definition at line 432 of file stm32f3xx_ll_usart.h.

#define LL_USART_IRDA_POWER_NORMAL 0x00000000U

IrDA normal power mode

Definition at line 431 of file stm32f3xx_ll_usart.h.

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STM32F373xC HAL User Manual: LIN Break Detection Length

Defines
LIN Break Detection Length
USART Exported Constants

Defines

#define | LL_USART_LINBREAK_DETECT_10B 0x00000000U
#define | LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL

Define Documentation

#define LL_USART_LINBREAK_DETECT_10B 0x00000000U

10-bit break detection method selected

Definition at line 440 of file stm32f3xx_ll_usart.h.

#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL

11-bit break detection method selected

Definition at line 441 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Driver Enable Polarity

Defines
Driver Enable Polarity
USART Exported Constants

Defines

#define | LL_USART_DE_POLARITY_HIGH 0x00000000U
#define | LL_USART_DE_POLARITY_LOW USART_CR3_DEP

Define Documentation

#define LL_USART_DE_POLARITY_HIGH 0x00000000U

DE signal is active high

Definition at line 449 of file stm32f3xx_ll_usart.h.

#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP

DE signal is active low

Definition at line 450 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Register Data

Defines
DMA Register Data
USART Exported Constants

Defines

#define | LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U

Define Documentation

#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U

Get address of data register used for reception

Definition at line 459 of file stm32f3xx_ll_usart.h.

#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U

Get address of data register used for transmission

Definition at line 458 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_DMA_GetRegAddr().

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STM32F373xC HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
USART Exported Macros

Defines

#define | LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in USART register.
#define | LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in USART register.

Define Documentation

#define LL_USART_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in USART register.

Parameters:
__INSTANCE__ | USART Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 492 of file stm32f3xx_ll_usart.h.

#define LL_USART_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in USART register.

Parameters:
__INSTANCE__ | USART Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 484 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Exported_Macros_Helper

Defines
Exported_Macros_Helper
USART Exported Macros

Defines

#define | __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
#define | __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)

Define Documentation

#define __LL_USART_DIV_SAMPLING16 | ( | __PERIPHCLK__,
 |  | __BAUDRATE__
 | ) | (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__))

Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for USART instance
__BAUDRATE__ | Baud rate value to achieve
Return values:
USARTDIV value to be used for BRR register filling in OverSampling_16 case

Definition at line 517 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_SetBaudRate().

#define __LL_USART_DIV_SAMPLING8 | ( | __PERIPHCLK__,
 |  | __BAUDRATE__
 | ) | ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__))

Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for USART instance
__BAUDRATE__ | Baud rate value to achieve
Return values:
USARTDIV value to be used for BRR register filling in OverSampling_8 case

Definition at line 508 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_SetBaudRate().

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration functions

Functions
Configuration functions
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_Enable (USART_TypeDef *USARTx)
USART Enable.
__STATIC_INLINE void | LL_USART_Disable (USART_TypeDef *USARTx)
USART Disable (all USART prescalers and outputs are disabled)
__STATIC_INLINE uint32_t | LL_USART_IsEnabled (USART_TypeDef *USARTx)
Indicate if USART is enabled.
__STATIC_INLINE void | LL_USART_EnableInStopMode (USART_TypeDef *USARTx)
USART enabled in STOP Mode.
__STATIC_INLINE void | LL_USART_DisableInStopMode (USART_TypeDef *USARTx)
USART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledInStopMode (USART_TypeDef *USARTx)
Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_USART_EnableDirectionRx (USART_TypeDef *USARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_USART_DisableDirectionRx (USART_TypeDef *USARTx)
Receiver Disable.
__STATIC_INLINE void | LL_USART_EnableDirectionTx (USART_TypeDef *USARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_USART_DisableDirectionTx (USART_TypeDef *USARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_USART_SetTransferDirection (USART_TypeDef *USARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_USART_GetTransferDirection (USART_TypeDef *USARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_USART_SetParity (USART_TypeDef *USARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled).
__STATIC_INLINE uint32_t | LL_USART_GetParity (USART_TypeDef *USARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_USART_SetWakeUpMethod (USART_TypeDef *USARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_USART_GetWakeUpMethod (USART_TypeDef *USARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_USART_SetDataWidth (USART_TypeDef *USARTx, uint32_t DataWidth)
Set Word length (i.e.
__STATIC_INLINE uint32_t | LL_USART_GetDataWidth (USART_TypeDef *USARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_USART_EnableMuteMode (USART_TypeDef *USARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_USART_DisableMuteMode (USART_TypeDef *USARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledMuteMode (USART_TypeDef *USARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_USART_SetOverSampling (USART_TypeDef *USARTx, uint32_t OverSampling)
Set Oversampling to 8-bit or 16-bit mode.
__STATIC_INLINE uint32_t | LL_USART_GetOverSampling (USART_TypeDef *USARTx)
Return Oversampling mode.
__STATIC_INLINE void | LL_USART_SetLastClkPulseOutput (USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
Configure if Clock pulse of the last data bit is output to the SCLK pin or not.
__STATIC_INLINE uint32_t | LL_USART_GetLastClkPulseOutput (USART_TypeDef *USARTx)
Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)
__STATIC_INLINE void | LL_USART_SetClockPhase (USART_TypeDef *USARTx, uint32_t ClockPhase)
Select the phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPhase (USART_TypeDef *USARTx)
Return phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_SetClockPolarity (USART_TypeDef *USARTx, uint32_t ClockPolarity)
Select the polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPolarity (USART_TypeDef *USARTx)
Return polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_ConfigClock (USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
__STATIC_INLINE void | LL_USART_EnableSCLKOutput (USART_TypeDef *USARTx)
Enable Clock output on SCLK pin.
__STATIC_INLINE void | LL_USART_DisableSCLKOutput (USART_TypeDef *USARTx)
Disable Clock output on SCLK pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSCLKOutput (USART_TypeDef *USARTx)
Indicate if Clock output on SCLK pin is enabled.
__STATIC_INLINE void | LL_USART_SetStopBitsLength (USART_TypeDef *USARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_USART_GetStopBitsLength (USART_TypeDef *USARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_USART_ConfigCharacter (USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_USART_SetTXRXSwap (USART_TypeDef *USARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_USART_GetTXRXSwap (USART_TypeDef *USARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_USART_SetRXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetRXPinLevel (USART_TypeDef *USARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetTXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetTXPinLevel (USART_TypeDef *USARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetBinaryDataLogic (USART_TypeDef *USARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_USART_GetBinaryDataLogic (USART_TypeDef *USARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_USART_SetTransferBitOrder (USART_TypeDef *USARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_USART_GetTransferBitOrder (USART_TypeDef *USARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_USART_EnableAutoBaudRate (USART_TypeDef *USARTx)
Enable Auto Baud-Rate Detection.
__STATIC_INLINE void | LL_USART_DisableAutoBaudRate (USART_TypeDef *USARTx)
Disable Auto Baud-Rate Detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledAutoBaud (USART_TypeDef *USARTx)
Indicate if Auto Baud-Rate Detection mechanism is enabled.
__STATIC_INLINE void | LL_USART_SetAutoBaudRateMode (USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
Set Auto Baud-Rate mode bits.
__STATIC_INLINE uint32_t | LL_USART_GetAutoBaudRateMode (USART_TypeDef *USARTx)
Return Auto Baud-Rate mode.
__STATIC_INLINE void | LL_USART_EnableRxTimeout (USART_TypeDef *USARTx)
Enable Receiver Timeout.
__STATIC_INLINE void | LL_USART_DisableRxTimeout (USART_TypeDef *USARTx)
Disable Receiver Timeout.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledRxTimeout (USART_TypeDef *USARTx)
Indicate if Receiver Timeout feature is enabled.
__STATIC_INLINE void | LL_USART_ConfigNodeAddress (USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the USART node.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddress (USART_TypeDef *USARTx)
Return 8 bit Address of the USART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddressLen (USART_TypeDef *USARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_USART_EnableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_EnableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_SetHWFlowCtrl (USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_USART_GetHWFlowCtrl (USART_TypeDef *USARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_USART_EnableOneBitSamp (USART_TypeDef *USARTx)
Enable One bit sampling method.
__STATIC_INLINE void | LL_USART_DisableOneBitSamp (USART_TypeDef *USARTx)
Disable One bit sampling method.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOneBitSamp (USART_TypeDef *USARTx)
Indicate if One bit sampling method is enabled.
__STATIC_INLINE void | LL_USART_EnableOverrunDetect (USART_TypeDef *USARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_USART_DisableOverrunDetect (USART_TypeDef *USARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOverrunDetect (USART_TypeDef *USARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_USART_SetWKUPType (USART_TypeDef *USARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetWKUPType (USART_TypeDef *USARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_USART_SetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, uint32_t BaudRate)
Configure USART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_USART_GetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.
__STATIC_INLINE void | LL_USART_SetRxTimeout (USART_TypeDef *USARTx, uint32_t Timeout)
Set Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE uint32_t | LL_USART_GetRxTimeout (USART_TypeDef *USARTx)
Get Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE void | LL_USART_SetBlockLength (USART_TypeDef *USARTx, uint32_t BlockLength)
Set Block Length value in reception.
__STATIC_INLINE uint32_t | LL_USART_GetBlockLength (USART_TypeDef *USARTx)
Get Block Length value in reception.

Function Documentation

__STATIC_INLINE void LL_USART_ConfigCharacter | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataWidth,
 |  | uint32_t | Parity,
 |  | uint32_t | StopBits
 | ) |  |

Configure Character frame format (Datawidth, Parity control, Stop Bits)

Note:
Call of this function is equivalent to following function call sequence :
  • Data Width configuration using LL_USART_SetDataWidth() function
  • Parity Control and mode configuration using LL_USART_SetParity() function
  • Stop bits configuration using LL_USART_SetStopBitsLength() function
Reference Manual to LL API cross reference:
CR1 PS LL_USART_ConfigCharacter
CR1 PCE LL_USART_ConfigCharacter
CR1 M0 LL_USART_ConfigCharacter
CR1 M1 LL_USART_ConfigCharacter
CR2 STOP LL_USART_ConfigCharacter
Parameters:
USARTx USART Instance
DataWidth This parameter can be one of the following values:
  • LL_USART_DATAWIDTH_7B (*)
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B
Parity This parameter can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD
StopBits This parameter can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2
(*) Values not available on all devices
Return values:
None

Definition at line 1070 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigClock | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Phase,
 |  | uint32_t | Polarity,
 |  | uint32_t | LBCPOutput
 | ) |  |

Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clock Phase configuration using LL_USART_SetClockPhase() function
  • Clock Polarity configuration using LL_USART_SetClockPolarity() function
  • Output of Last bit Clock pulse configuration using LL_USART_SetLastClkPulseOutput() function
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_ConfigClock
CR2 CPOL LL_USART_ConfigClock
CR2 LBCL LL_USART_ConfigClock
Parameters:
USARTx USART Instance
Phase This parameter can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE
Polarity This parameter can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH
LBCPOutput This parameter can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT
Return values:
None

Definition at line 966 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigNodeAddress | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AddressLen,
 |  | uint32_t | NodeAddress
 | ) |  |

Set Address of the USART node.

Note:
This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with address mark detection.
4bits address node is used when 4-bit Address Detection is selected in ADDM7. (b7-b4 should be set to 0) 8bits address node is used when 7-bit Address Detection is selected in ADDM7. (This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with 7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match)
Reference Manual to LL API cross reference:
CR2 ADD LL_USART_ConfigNodeAddress
CR2 ADDM7 LL_USART_ConfigNodeAddress
Parameters:
USARTx | USART Instance
AddressLen This parameter can be one of the following values:
  • LL_USART_ADDRESS_DETECT_4B
  • LL_USART_ADDRESS_DETECT_7B
NodeAddress | 4 or 7 bit Address of the USART node.
Return values:
None

Definition at line 1348 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_Disable ( USART_TypeDef * USARTx )

USART Disable (all USART prescalers and outputs are disabled)

Note:
When USART is disabled, USART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the USART is kept, but all the status flags, in the USARTx_ISR are set to their default values.
Reference Manual to LL API cross reference:
CR1 UE LL_USART_Disable
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 557 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableAutoBaudRate ( USART_TypeDef * USARTx )

Disable Auto Baud-Rate Detection.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_DisableAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1239 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl ( USART_TypeDef * USARTx )

Disable CTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1429 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDirectionRx ( USART_TypeDef * USARTx )

Receiver Disable.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_DisableDirectionRx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 632 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDirectionTx ( USART_TypeDef * USARTx )

Transmitter Disable.

Reference Manual to LL API cross reference:
CR1 TE LL_USART_DisableDirectionTx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 654 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableInStopMode ( USART_TypeDef * USARTx )

USART disabled in STOP Mode.

Note:
When this function is disabled, USART is not able to wake up the MCU from Stop mode
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_DisableInStopMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 597 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableMuteMode ( USART_TypeDef * USARTx )

Prevent Mute Mode use.

Set Receiver in active mode permanently.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_DisableMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 806 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableOneBitSamp ( USART_TypeDef * USARTx )

Disable One bit sampling method.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_DisableOneBitSamp
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1488 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableOverrunDetect ( USART_TypeDef * USARTx )

Disable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_DisableOverrunDetect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1521 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl ( USART_TypeDef * USARTx )

Disable RTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1403 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableRxTimeout ( USART_TypeDef * USARTx )

Disable Receiver Timeout.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_DisableRxTimeout
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1309 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSCLKOutput ( USART_TypeDef * USARTx )

Disable Clock output on SCLK pin.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_DisableSCLKOutput
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 992 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_ClockInit().

__STATIC_INLINE void LL_USART_Enable ( USART_TypeDef * USARTx )

USART Enable.

Reference Manual to LL API cross reference:
CR1 UE LL_USART_Enable
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 543 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableAutoBaudRate ( USART_TypeDef * USARTx )

Enable Auto Baud-Rate Detection.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_EnableAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1226 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl ( USART_TypeDef * USARTx )

Enable CTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1416 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDirectionRx ( USART_TypeDef * USARTx )

Receiver Enable (Receiver is enabled and begins searching for a start bit)

Reference Manual to LL API cross reference:
CR1 RE LL_USART_EnableDirectionRx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 621 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDirectionTx ( USART_TypeDef * USARTx )

Transmitter Enable.

Reference Manual to LL API cross reference:
CR1 TE LL_USART_EnableDirectionTx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 643 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableInStopMode ( USART_TypeDef * USARTx )

USART enabled in STOP Mode.

Note:
When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that USART clock selection is HSI or LSE in RCC.
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_EnableInStopMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 583 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableMuteMode ( USART_TypeDef * USARTx )

Allow switch between Mute Mode and Active mode.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_EnableMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 795 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableOneBitSamp ( USART_TypeDef * USARTx )

Enable One bit sampling method.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_EnableOneBitSamp
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1477 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableOverrunDetect ( USART_TypeDef * USARTx )

Enable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_EnableOverrunDetect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1510 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl ( USART_TypeDef * USARTx )

Enable RTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1390 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableRxTimeout ( USART_TypeDef * USARTx )

Enable Receiver Timeout.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_EnableRxTimeout
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1298 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSCLKOutput ( USART_TypeDef * USARTx )

Enable Clock output on SCLK pin.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_EnableSCLKOutput
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 979 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode ( USART_TypeDef * USARTx )

Return Auto Baud-Rate mode.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABRMODE LL_USART_GetAutoBaudRateMode
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME

Definition at line 1287 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetBaudRate | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | OverSampling
 | ) |  |

Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.

Note:
In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
Reference Manual to LL API cross reference:
BRR BRR LL_USART_GetBaudRate
Parameters:
USARTx | USART Instance
PeriphClk | Peripheral Clock
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
Return values:
Baud Rate

Definition at line 1618 of file stm32f3xx_ll_usart.h.

References LL_USART_OVERSAMPLING_8.

__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic ( USART_TypeDef * USARTx )

Retrieve Binary data configuration.

Reference Manual to LL API cross reference:
CR2 DATAINV LL_USART_GetBinaryDataLogic
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_BINARY_LOGIC_POSITIVE
  • LL_USART_BINARY_LOGIC_NEGATIVE

Definition at line 1182 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetBlockLength ( USART_TypeDef * USARTx )

Get Block Length value in reception.

Reference Manual to LL API cross reference:
RTOR BLEN LL_USART_GetBlockLength
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 1684 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetClockPhase ( USART_TypeDef * USARTx )

Return phase of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_GetClockPhase
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE

Definition at line 907 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetClockPolarity ( USART_TypeDef * USARTx )

Return polarity of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPOL LL_USART_GetClockPolarity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH

Definition at line 938 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDataWidth ( USART_TypeDef * USARTx )

Return Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M0 LL_USART_GetDataWidth
CR1 M1 LL_USART_GetDataWidth
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DATAWIDTH_7B (*)
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B
(*) Values not available on all devices

Definition at line 784 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl ( USART_TypeDef * USARTx )

Return HW Flow Control configuration (both CTS and RTS)

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_GetHWFlowCtrl
CR3 CTSE LL_USART_GetHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_HWCONTROL_NONE
  • LL_USART_HWCONTROL_RTS
  • LL_USART_HWCONTROL_CTS
  • LL_USART_HWCONTROL_RTS_CTS

Definition at line 1466 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput ( USART_TypeDef * USARTx )

Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBCL LL_USART_GetLastClkPulseOutput
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT

Definition at line 876 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetNodeAddress ( USART_TypeDef * USARTx )

Return 8 bit Address of the USART node as set in ADD field of CR2.

Note:
If 4-bit Address Detection is selected in ADDM7, only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) If 7-bit Address Detection is selected in ADDM7, only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
Reference Manual to LL API cross reference:
CR2 ADD LL_USART_GetNodeAddress
Parameters:
USARTx USART Instance
Return values:
Address of the USART node (Value between Min_Data=0 and Max_Data=255)

Definition at line 1364 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen ( USART_TypeDef * USARTx )

Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)

Reference Manual to LL API cross reference:
CR2 ADDM7 LL_USART_GetNodeAddressLen
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_ADDRESS_DETECT_4B
  • LL_USART_ADDRESS_DETECT_7B

Definition at line 1377 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetOverSampling ( USART_TypeDef * USARTx )

Return Oversampling mode.

Reference Manual to LL API cross reference:
CR1 OVER8 LL_USART_GetOverSampling
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8

Definition at line 844 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetParity ( USART_TypeDef * USARTx )

Return Parity configuration (enabled/disabled and parity mode if enabled)

Reference Manual to LL API cross reference:
CR1 PS LL_USART_GetParity
CR1 PCE LL_USART_GetParity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD

Definition at line 722 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel ( USART_TypeDef * USARTx )

Retrieve RX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 RXINV LL_USART_GetRXPinLevel
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_RXPIN_LEVEL_STANDARD
  • LL_USART_RXPIN_LEVEL_INVERTED

Definition at line 1126 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetRxTimeout ( USART_TypeDef * USARTx )

Get Receiver Time Out Value (expressed in nb of bits duration)

Reference Manual to LL API cross reference:
RTOR RTO LL_USART_GetRxTimeout
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x00FFFFFF

Definition at line 1661 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength ( USART_TypeDef * USARTx )

Retrieve the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_USART_GetStopBitsLength
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2

Definition at line 1036 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder ( USART_TypeDef * USARTx )

Return transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_USART_GetTransferBitOrder
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_BITORDER_LSBFIRST
  • LL_USART_BITORDER_MSBFIRST

Definition at line 1213 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTransferDirection ( USART_TypeDef * USARTx )

Return enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_GetTransferDirection
CR1 TE LL_USART_GetTransferDirection
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DIRECTION_NONE
  • LL_USART_DIRECTION_RX
  • LL_USART_DIRECTION_TX
  • LL_USART_DIRECTION_TX_RX

Definition at line 688 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel ( USART_TypeDef * USARTx )

Retrieve TX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 TXINV LL_USART_GetTXPinLevel
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_TXPIN_LEVEL_STANDARD
  • LL_USART_TXPIN_LEVEL_INVERTED

Definition at line 1153 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap ( USART_TypeDef * USARTx )

Retrieve TX/RX pins swapping configuration.

Reference Manual to LL API cross reference:
CR2 SWAP LL_USART_GetTXRXSwap
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_TXRX_STANDARD
  • LL_USART_TXRX_SWAPPED

Definition at line 1099 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod ( USART_TypeDef * USARTx )

Return Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_USART_GetWakeUpMethod
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_WAKEUP_IDLELINE
  • LL_USART_WAKEUP_ADDRESSMARK

Definition at line 749 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetWKUPType ( USART_TypeDef * USARTx )

Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUS LL_USART_GetWKUPType
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_WAKEUP_ON_ADDRESS
  • LL_USART_WAKEUP_ON_STARTBIT
  • LL_USART_WAKEUP_ON_RXNE

Definition at line 1565 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabled ( USART_TypeDef * USARTx )

Indicate if USART is enabled.

Reference Manual to LL API cross reference:
CR1 UE LL_USART_IsEnabled
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 568 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_Init().

__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud ( USART_TypeDef * USARTx )

Indicate if Auto Baud-Rate Detection mechanism is enabled.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_IsEnabledAutoBaud
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1252 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode ( USART_TypeDef * USARTx )

Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_IsEnabledInStopMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 610 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode ( USART_TypeDef * USARTx )

Indicate if switch between Mute Mode and Active mode is allowed.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_IsEnabledMuteMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 817 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp ( USART_TypeDef * USARTx )

Indicate if One bit sampling method is enabled.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1499 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect ( USART_TypeDef * USARTx )

Indicate if Overrun detection is enabled.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_IsEnabledOverrunDetect
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1532 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout ( USART_TypeDef * USARTx )

Indicate if Receiver Timeout feature is enabled.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_IsEnabledRxTimeout
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1320 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput ( USART_TypeDef * USARTx )

Indicate if Clock output on SCLK pin is enabled.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_IsEnabledSCLKOutput
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1005 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetAutoBaudRateMode | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AutoBaudRateMode
 | ) |  |

Set Auto Baud-Rate mode bits.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABRMODE LL_USART_SetAutoBaudRateMode
Parameters:
USARTx USART Instance
AutoBaudRateMode This parameter can be one of the following values:
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
Return values:
None

Definition at line 1270 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetBaudRate | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | OverSampling,
 |  | uint32_t | BaudRate
 | ) |  |

Configure USART BRR register for achieving expected Baud Rate value.

Note:
Compute and set USARTDIV value in BRR Register (full BRR content) according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
Peripheral clock and Baud rate values provided as function parameters should be valid (Baud rate value != 0)
In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
Reference Manual to LL API cross reference:
BRR BRR LL_USART_SetBaudRate
Parameters:
USARTx | USART Instance
PeriphClk | Peripheral Clock
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
BaudRate | Baud Rate
Return values:
None

Definition at line 1586 of file stm32f3xx_ll_usart.h.

References __LL_USART_DIV_SAMPLING16, __LL_USART_DIV_SAMPLING8, and LL_USART_OVERSAMPLING_8.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetBinaryDataLogic | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataLogic
 | ) |  |

Configure Binary data logic.

Note:
Allow to define how Logical data from the data register are send/received : either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
Reference Manual to LL API cross reference:
CR2 DATAINV LL_USART_SetBinaryDataLogic
Parameters:
USARTx USART Instance
DataLogic This parameter can be one of the following values:
  • LL_USART_BINARY_LOGIC_POSITIVE
  • LL_USART_BINARY_LOGIC_NEGATIVE
Return values:
None

Definition at line 1169 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetBlockLength | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | BlockLength
 | ) |  |

Set Block Length value in reception.

Reference Manual to LL API cross reference:
RTOR BLEN LL_USART_SetBlockLength
Parameters:
USARTx | USART Instance
BlockLength | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1673 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetClockPhase | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | ClockPhase
 | ) |  |

Select the phase of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_SetClockPhase
Parameters:
USARTx USART Instance
ClockPhase This parameter can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE
Return values:
None

Definition at line 892 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetClockPolarity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Select the polarity of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPOL LL_USART_SetClockPolarity
Parameters:
USARTx USART Instance
ClockPolarity This parameter can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH
Return values:
None

Definition at line 923 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDataWidth | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataWidth
 | ) |  |

Set Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M0 LL_USART_SetDataWidth
CR1 M1 LL_USART_SetDataWidth
Parameters:
USARTx USART Instance
DataWidth This parameter can be one of the following values:
  • LL_USART_DATAWIDTH_7B (*)
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B
(*) Values not available on all devices
Return values:
None

Definition at line 767 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetHWFlowCtrl | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | HardwareFlowControl
 | ) |  |

Configure HW Flow Control mode (both CTS and RTS)

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_SetHWFlowCtrl
CR3 CTSE LL_USART_SetHWFlowCtrl
Parameters:
USARTx USART Instance
HardwareFlowControl This parameter can be one of the following values:
  • LL_USART_HWCONTROL_NONE
  • LL_USART_HWCONTROL_RTS
  • LL_USART_HWCONTROL_CTS
  • LL_USART_HWCONTROL_RTS_CTS
Return values:
None

Definition at line 1448 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetLastClkPulseOutput | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | LastBitClockPulse
 | ) |  |

Configure if Clock pulse of the last data bit is output to the SCLK pin or not.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBCL LL_USART_SetLastClkPulseOutput
Parameters:
USARTx USART Instance
LastBitClockPulse This parameter can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT
Return values:
None

Definition at line 860 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetOverSampling | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | OverSampling
 | ) |  |

Set Oversampling to 8-bit or 16-bit mode.

Reference Manual to LL API cross reference:
CR1 OVER8 LL_USART_SetOverSampling
Parameters:
USARTx USART Instance
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
Return values:
None

Definition at line 831 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetParity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Parity
 | ) |  |

Configure Parity (enabled/disabled and parity mode if enabled).

Note:
This function selects if hardware parity control (generation and detection) is enabled or disabled. When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position (9th or 8th bit depending on data width) and parity is checked on the received data.
Reference Manual to LL API cross reference:
CR1 PS LL_USART_SetParity
CR1 PCE LL_USART_SetParity
Parameters:
USARTx USART Instance
Parity This parameter can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD
Return values:
None

Definition at line 707 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetRXPinLevel | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure RX pin active level logic.

Reference Manual to LL API cross reference:
CR2 RXINV LL_USART_SetRXPinLevel
Parameters:
USARTx USART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_USART_RXPIN_LEVEL_STANDARD
  • LL_USART_RXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1113 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetRxTimeout | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Timeout
 | ) |  |

Set Receiver Time Out Value (expressed in nb of bits duration)

Reference Manual to LL API cross reference:
RTOR RTO LL_USART_SetRxTimeout
Parameters:
USARTx | USART Instance
Timeout | Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
Return values:
None

Definition at line 1650 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetStopBitsLength | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | StopBits
 | ) |  |

Set the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_USART_SetStopBitsLength
Parameters:
USARTx USART Instance
StopBits This parameter can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2
Return values:
None

Definition at line 1021 of file stm32f3xx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetTransferBitOrder | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | BitOrder
 | ) |  |

Configure transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_USART_SetTransferBitOrder
Parameters:
USARTx USART Instance
BitOrder This parameter can be one of the following values:
  • LL_USART_BITORDER_LSBFIRST
  • LL_USART_BITORDER_MSBFIRST
Return values:
None

Definition at line 1198 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTransferDirection | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | TransferDirection
 | ) |  |

Configure simultaneously enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_SetTransferDirection
CR1 TE LL_USART_SetTransferDirection
Parameters:
USARTx USART Instance
TransferDirection This parameter can be one of the following values:
  • LL_USART_DIRECTION_NONE
  • LL_USART_DIRECTION_RX
  • LL_USART_DIRECTION_TX
  • LL_USART_DIRECTION_TX_RX
Return values:
None

Definition at line 672 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTXPinLevel | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure TX pin active level logic.

Reference Manual to LL API cross reference:
CR2 TXINV LL_USART_SetTXPinLevel
Parameters:
USARTx USART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_USART_TXPIN_LEVEL_STANDARD
  • LL_USART_TXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1140 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTXRXSwap | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | SwapConfig
 | ) |  |

Configure TX/RX pins swapping setting.

Reference Manual to LL API cross reference:
CR2 SWAP LL_USART_SetTXRXSwap
Parameters:
USARTx USART Instance
SwapConfig This parameter can be one of the following values:
  • LL_USART_TXRX_STANDARD
  • LL_USART_TXRX_SWAPPED
Return values:
None

Definition at line 1086 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetWakeUpMethod | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Method
 | ) |  |

Set Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_USART_SetWakeUpMethod
Parameters:
USARTx USART Instance
Method This parameter can be one of the following values:
  • LL_USART_WAKEUP_IDLELINE
  • LL_USART_WAKEUP_ADDRESSMARK
Return values:
None

Definition at line 736 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetWKUPType | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Type
 | ) |  |

Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUS LL_USART_SetWKUPType
Parameters:
USARTx USART Instance
Type This parameter can be one of the following values:
  • LL_USART_WAKEUP_ON_ADDRESS
  • LL_USART_WAKEUP_ON_STARTBIT
  • LL_USART_WAKEUP_ON_RXNE
Return values:
None

Definition at line 1549 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration functions related to Irda feature

Functions
Configuration functions related to Irda feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableIrda (USART_TypeDef *USARTx)
Enable IrDA mode.
__STATIC_INLINE void | LL_USART_DisableIrda (USART_TypeDef *USARTx)
Disable IrDA mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIrda (USART_TypeDef *USARTx)
Indicate if IrDA mode is enabled.
__STATIC_INLINE void | LL_USART_SetIrdaPowerMode (USART_TypeDef *USARTx, uint32_t PowerMode)
Configure IrDA Power Mode (Normal or Low Power)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPowerMode (USART_TypeDef *USARTx)
Retrieve IrDA Power Mode configuration (Normal or Low Power)
__STATIC_INLINE void | LL_USART_SetIrdaPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPrescaler (USART_TypeDef *USARTx)
Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Function Documentation

__STATIC_INLINE void LL_USART_DisableIrda ( USART_TypeDef * USARTx )

Disable IrDA mode.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_DisableIrda
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1718 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIrda ( USART_TypeDef * USARTx )

Enable IrDA mode.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_EnableIrda
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1705 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode ( USART_TypeDef * USARTx )

Retrieve IrDA Power Mode configuration (Normal or Low Power)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IRLP LL_USART_GetIrdaPowerMode
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_IRDA_POWER_NORMAL
  • LL_USART_PHASE_2EDGE

Definition at line 1762 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler ( USART_TypeDef * USARTx )

Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_GetIrdaPrescaler
Parameters:
USARTx USART Instance
Return values:
Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)

Definition at line 1791 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda ( USART_TypeDef * USARTx )

Indicate if IrDA mode is enabled.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_IsEnabledIrda
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1731 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetIrdaPowerMode | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PowerMode
 | ) |  |

Configure IrDA Power Mode (Normal or Low Power)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IRLP LL_USART_SetIrdaPowerMode
Parameters:
USARTx USART Instance
PowerMode This parameter can be one of the following values:
  • LL_USART_IRDA_POWER_NORMAL
  • LL_USART_IRDA_POWER_LOW
Return values:
None

Definition at line 1747 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetIrdaPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_SetIrdaPrescaler
Parameters:
USARTx | USART Instance
PrescalerValue | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1777 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration functions related to Smartcard feature

Functions
Configuration functions related to Smartcard feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableSmartcardNACK (USART_TypeDef *USARTx)
Enable Smartcard NACK transmission.
__STATIC_INLINE void | LL_USART_DisableSmartcardNACK (USART_TypeDef *USARTx)
Disable Smartcard NACK transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcardNACK (USART_TypeDef *USARTx)
Indicate if Smartcard NACK transmission is enabled.
__STATIC_INLINE void | LL_USART_EnableSmartcard (USART_TypeDef *USARTx)
Enable Smartcard mode.
__STATIC_INLINE void | LL_USART_DisableSmartcard (USART_TypeDef *USARTx)
Disable Smartcard mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcard (USART_TypeDef *USARTx)
Indicate if Smartcard mode is enabled.
__STATIC_INLINE void | LL_USART_SetSmartcardAutoRetryCount (USART_TypeDef *USARTx, uint32_t AutoRetryCount)
Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardAutoRetryCount (USART_TypeDef *USARTx)
Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE void | LL_USART_SetSmartcardPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardPrescaler (USART_TypeDef *USARTx)
Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE void | LL_USART_SetSmartcardGuardTime (USART_TypeDef *USARTx, uint32_t GuardTime)
Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardGuardTime (USART_TypeDef *USARTx)
Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Function Documentation

__STATIC_INLINE void LL_USART_DisableSmartcard ( USART_TypeDef * USARTx )

Disable Smartcard mode.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_DisableSmartcard
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1864 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSmartcardNACK ( USART_TypeDef * USARTx )

Disable Smartcard NACK transmission.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_DisableSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1825 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSmartcard ( USART_TypeDef * USARTx )

Enable Smartcard mode.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_EnableSmartcard
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1851 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSmartcardNACK ( USART_TypeDef * USARTx )

Enable Smartcard NACK transmission.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_EnableSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1812 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount ( USART_TypeDef * USARTx )

Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
Parameters:
USARTx USART Instance
Return values:
Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)

Definition at line 1909 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime ( USART_TypeDef * USARTx )

Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR GT LL_USART_GetSmartcardGuardTime
Parameters:
USARTx USART Instance
Return values:
Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)

Definition at line 1967 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler ( USART_TypeDef * USARTx )

Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_GetSmartcardPrescaler
Parameters:
USARTx USART Instance
Return values:
Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)

Definition at line 1938 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard ( USART_TypeDef * USARTx )

Indicate if Smartcard mode is enabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_IsEnabledSmartcard
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1877 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK ( USART_TypeDef * USARTx )

Indicate if Smartcard NACK transmission is enabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_IsEnabledSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1838 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AutoRetryCount
 | ) |  |

Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE and PE bits set)
Reference Manual to LL API cross reference:
CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount
Parameters:
USARTx | USART Instance
AutoRetryCount | Value between Min_Data=0 and Max_Data=7
Return values:
None

Definition at line 1896 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetSmartcardGuardTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | GuardTime
 | ) |  |

Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR GT LL_USART_SetSmartcardGuardTime
Parameters:
USARTx | USART Instance
GuardTime | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1953 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetSmartcardPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_SetSmartcardPrescaler
Parameters:
USARTx | USART Instance
PrescalerValue | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 1924 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration functions related to Half Duplex feature

Functions
Configuration functions related to Half Duplex feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableHalfDuplex (USART_TypeDef *USARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_USART_DisableHalfDuplex (USART_TypeDef *USARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledHalfDuplex (USART_TypeDef *USARTx)
Indicate if Single Wire Half-Duplex mode is enabled.

Function Documentation

__STATIC_INLINE void LL_USART_DisableHalfDuplex ( USART_TypeDef * USARTx )

Disable Single Wire Half-Duplex mode.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_DisableHalfDuplex
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2001 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableHalfDuplex ( USART_TypeDef * USARTx )

Enable Single Wire Half-Duplex mode.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_EnableHalfDuplex
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1988 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex ( USART_TypeDef * USARTx )

Indicate if Single Wire Half-Duplex mode is enabled.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_IsEnabledHalfDuplex
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2014 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration functions related to LIN feature

Functions
Configuration functions related to LIN feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_SetLINBrkDetectionLen (USART_TypeDef *USARTx, uint32_t LINBDLength)
Set LIN Break Detection Length.
__STATIC_INLINE uint32_t | LL_USART_GetLINBrkDetectionLen (USART_TypeDef *USARTx)
Return LIN Break Detection Length.
__STATIC_INLINE void | LL_USART_EnableLIN (USART_TypeDef *USARTx)
Enable LIN mode.
__STATIC_INLINE void | LL_USART_DisableLIN (USART_TypeDef *USARTx)
Disable LIN mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledLIN (USART_TypeDef *USARTx)
Indicate if LIN mode is enabled.

Function Documentation

__STATIC_INLINE void LL_USART_DisableLIN ( USART_TypeDef * USARTx )

Disable LIN mode.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_DisableLIN
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2079 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableLIN ( USART_TypeDef * USARTx )

Enable LIN mode.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_EnableLIN
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2066 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen ( USART_TypeDef * USARTx )

Return LIN Break Detection Length.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDL LL_USART_GetLINBrkDetectionLen
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_LINBREAK_DETECT_10B
  • LL_USART_LINBREAK_DETECT_11B

Definition at line 2053 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN ( USART_TypeDef * USARTx )

Indicate if LIN mode is enabled.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_IsEnabledLIN
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2092 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | LINBDLength
 | ) |  |

Set LIN Break Detection Length.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDL LL_USART_SetLINBrkDetectionLen
Parameters:
USARTx USART Instance
LINBDLength This parameter can be one of the following values:
  • LL_USART_LINBREAK_DETECT_10B
  • LL_USART_LINBREAK_DETECT_11B
Return values:
None

Definition at line 2038 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Configuration functions related to Driver Enable feature

Functions
Configuration functions related to Driver Enable feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_SetDEDeassertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEDeassertionTime (USART_TypeDef *USARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_USART_SetDEAssertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEAssertionTime (USART_TypeDef *USARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_USART_EnableDEMode (USART_TypeDef *USARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_USART_DisableDEMode (USART_TypeDef *USARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDEMode (USART_TypeDef *USARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_USART_SetDESignalPolarity (USART_TypeDef *USARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_USART_GetDESignalPolarity (USART_TypeDef *USARTx)
Return Driver Enable Polarity.

Function Documentation

__STATIC_INLINE void LL_USART_DisableDEMode ( USART_TypeDef * USARTx )

Disable Driver Enable (DE) Mode.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_DisableDEMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2180 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDEMode ( USART_TypeDef * USARTx )

Enable Driver Enable (DE) Mode.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_EnableDEMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2167 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime ( USART_TypeDef * USARTx )

Return DEAT (Driver Enable Assertion Time)

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEAT LL_USART_GetDEAssertionTime
Parameters:
USARTx USART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31

Definition at line 2154 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime ( USART_TypeDef * USARTx )

Return DEDT (Driver Enable De-Assertion Time)

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEDT LL_USART_GetDEDeassertionTime
Parameters:
USARTx USART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31

Definition at line 2127 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity ( USART_TypeDef * USARTx )

Return Driver Enable Polarity.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEP LL_USART_GetDESignalPolarity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DE_POLARITY_HIGH
  • LL_USART_DE_POLARITY_LOW

Definition at line 2224 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode ( USART_TypeDef * USARTx )

Indicate if Driver Enable (DE) Mode is enabled.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_IsEnabledDEMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2193 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDEAssertionTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEAT LL_USART_SetDEAssertionTime
Parameters:
USARTx | USART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 2141 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDEDeassertionTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEDT LL_USART_SetDEDeassertionTime
Parameters:
USARTx | USART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 2114 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDESignalPolarity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Polarity
 | ) |  |

Select Driver Enable Polarity.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEP LL_USART_SetDESignalPolarity
Parameters:
USARTx USART Instance
Polarity This parameter can be one of the following values:
  • LL_USART_DE_POLARITY_HIGH
  • LL_USART_DE_POLARITY_LOW
Return values:
None

Definition at line 2209 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Advanced Configurations services

Functions
Advanced Configurations services
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_ConfigAsyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
__STATIC_INLINE void | LL_USART_ConfigSyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Synchronous Mode.
__STATIC_INLINE void | LL_USART_ConfigLINMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in LIN Mode.
__STATIC_INLINE void | LL_USART_ConfigHalfDuplexMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Half Duplex Mode.
__STATIC_INLINE void | LL_USART_ConfigSmartcardMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Smartcard Mode.
__STATIC_INLINE void | LL_USART_ConfigIrdaMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Irda Mode.
__STATIC_INLINE void | LL_USART_ConfigMultiProcessMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).

Function Documentation

__STATIC_INLINE void LL_USART_ConfigAsyncMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)

Note:
In UART mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
Other remaining configurations items related to Asynchronous Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigAsyncMode
CR2 CLKEN LL_USART_ConfigAsyncMode
CR3 SCEN LL_USART_ConfigAsyncMode
CR3 IREN LL_USART_ConfigAsyncMode
CR3 HDSEL LL_USART_ConfigAsyncMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2262 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Half Duplex Mode.

Note:
In Half Duplex mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register, This function also sets the UART/USART in Half Duplex mode.
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Set HDSEL in CR3 using LL_USART_EnableHalfDuplex() function
Other remaining configurations items related to Half Duplex Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigHalfDuplexMode
CR2 CLKEN LL_USART_ConfigHalfDuplexMode
CR3 HDSEL LL_USART_ConfigHalfDuplexMode
CR3 SCEN LL_USART_ConfigHalfDuplexMode
CR3 IREN LL_USART_ConfigHalfDuplexMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2376 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigIrdaMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Irda Mode.

Note:
In IRDA mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • STOP and CLKEN bits in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also sets the UART/USART in IRDA mode (IREN bit).
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Configure STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Set IREN in CR3 using LL_USART_EnableIrda() function
Other remaining configurations items related to Irda Mode (as Baud Rate, Word length, Power mode, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigIrdaMode
CR2 CLKEN LL_USART_ConfigIrdaMode
CR2 STOP LL_USART_ConfigIrdaMode
CR3 SCEN LL_USART_ConfigIrdaMode
CR3 HDSEL LL_USART_ConfigIrdaMode
CR3 IREN LL_USART_ConfigIrdaMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2459 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigLINMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in LIN Mode.

Note:
In LIN mode, the following bits must be kept cleared:
  • STOP and CLKEN bits in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also set the UART/USART in LIN mode.
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Set LINEN in CR2 using LL_USART_EnableLIN() function
Other remaining configurations items related to LIN Mode (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_ConfigLINMode
CR2 STOP LL_USART_ConfigLINMode
CR2 LINEN LL_USART_ConfigLINMode
CR3 IREN LL_USART_ConfigLINMode
CR3 SCEN LL_USART_ConfigLINMode
CR3 HDSEL LL_USART_ConfigLINMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2338 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigMultiProcessMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).

Note:
In MultiProcessor mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
Other remaining configurations items related to Multi processor Mode (as Baud Rate, Wake Up Method, Node address, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigMultiProcessMode
CR2 CLKEN LL_USART_ConfigMultiProcessMode
CR3 SCEN LL_USART_ConfigMultiProcessMode
CR3 HDSEL LL_USART_ConfigMultiProcessMode
CR3 IREN LL_USART_ConfigMultiProcessMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2497 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigSmartcardMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Smartcard Mode.

Note:
In Smartcard mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also configures Stop bits to 1.5 bits and sets the USART in Smartcard mode (SCEN bit). Clock Output is also enabled (CLKEN).
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Configure STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Set CLKEN in CR2 using LL_USART_EnableSCLKOutput() function
  • Set SCEN in CR3 using LL_USART_EnableSmartcard() function
Other remaining configurations items related to Smartcard Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigSmartcardMode
CR2 STOP LL_USART_ConfigSmartcardMode
CR2 CLKEN LL_USART_ConfigSmartcardMode
CR3 HDSEL LL_USART_ConfigSmartcardMode
CR3 SCEN LL_USART_ConfigSmartcardMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2416 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigSyncMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Synchronous Mode.

Note:
In Synchronous mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also sets the USART in Synchronous mode.
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Set CLKEN in CR2 using LL_USART_EnableSCLKOutput() function
Other remaining configurations items related to Synchronous Mode (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigSyncMode
CR2 CLKEN LL_USART_ConfigSyncMode
CR3 SCEN LL_USART_ConfigSyncMode
CR3 IREN LL_USART_ConfigSyncMode
CR3 HDSEL LL_USART_ConfigSyncMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2298 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLAG_Management

Functions
FLAG_Management
USART Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_FE (USART_TypeDef *USARTx)
Check if the USART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_NE (USART_TypeDef *USARTx)
Check if the USART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ORE (USART_TypeDef *USARTx)
Check if the USART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXNE (USART_TypeDef *USARTx)
Check if the USART Read Data Register Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXE (USART_TypeDef *USARTx)
Check if the USART Transmit Data Register Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_nCTS (USART_TypeDef *USARTx)
Check if the USART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RTO (USART_TypeDef *USARTx)
Check if the USART Receiver Time Out Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_EOB (USART_TypeDef *USARTx)
Check if the USART End Of Block Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABRE (USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABR (USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_BUSY (USART_TypeDef *USARTx)
Check if the USART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CM (USART_TypeDef *USARTx)
Check if the USART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_SBK (USART_TypeDef *USARTx)
Check if the USART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RWU (USART_TypeDef *USARTx)
Check if the USART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_WKUP (USART_TypeDef *USARTx)
Check if the USART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TEACK (USART_TypeDef *USARTx)
Check if the USART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_REACK (USART_TypeDef *USARTx)
Check if the USART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE void | LL_USART_ClearFlag_PE (USART_TypeDef *USARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_FE (USART_TypeDef *USARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_NE (USART_TypeDef *USARTx)
Clear Noise detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_ORE (USART_TypeDef *USARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_IDLE (USART_TypeDef *USARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TC (USART_TypeDef *USARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_LBD (USART_TypeDef *USARTx)
Clear LIN Break Detection Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_nCTS (USART_TypeDef *USARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_RTO (USART_TypeDef *USARTx)
Clear Receiver Time Out Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_EOB (USART_TypeDef *USARTx)
Clear End Of Block Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_CM (USART_TypeDef *USARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_WKUP (USART_TypeDef *USARTx)
Clear Wake Up from stop mode Flag.

Function Documentation

__STATIC_INLINE void LL_USART_ClearFlag_CM ( USART_TypeDef * USARTx )

Clear Character Match Flag.

Reference Manual to LL API cross reference:
ICR CMCF LL_USART_ClearFlag_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2894 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_EOB ( USART_TypeDef * USARTx )

Clear End Of Block Flag.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR EOBCF LL_USART_ClearFlag_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2883 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_FE ( USART_TypeDef * USARTx )

Clear Framing Error Flag.

Reference Manual to LL API cross reference:
ICR FECF LL_USART_ClearFlag_FE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2788 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_IDLE ( USART_TypeDef * USARTx )

Clear IDLE line detected Flag.

Reference Manual to LL API cross reference:
ICR IDLECF LL_USART_ClearFlag_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2821 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_LBD ( USART_TypeDef * USARTx )

Clear LIN Break Detection Flag.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR LBDCF LL_USART_ClearFlag_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2846 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_nCTS ( USART_TypeDef * USARTx )

Clear CTS Interrupt Flag.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR CTSCF LL_USART_ClearFlag_nCTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2859 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_NE ( USART_TypeDef * USARTx )

Clear Noise detected Flag.

Reference Manual to LL API cross reference:
ICR NCF LL_USART_ClearFlag_NE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2799 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_ORE ( USART_TypeDef * USARTx )

Clear OverRun Error Flag.

Reference Manual to LL API cross reference:
ICR ORECF LL_USART_ClearFlag_ORE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2810 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_PE ( USART_TypeDef * USARTx )

Clear Parity Error Flag.

Reference Manual to LL API cross reference:
ICR PECF LL_USART_ClearFlag_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2777 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_RTO ( USART_TypeDef * USARTx )

Clear Receiver Time Out Flag.

Reference Manual to LL API cross reference:
ICR RTOCF LL_USART_ClearFlag_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2870 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_TC ( USART_TypeDef * USARTx )

Clear Transmission Complete Flag.

Reference Manual to LL API cross reference:
ICR TCCF LL_USART_ClearFlag_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2832 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_WKUP ( USART_TypeDef * USARTx )

Clear Wake Up from stop mode Flag.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR WUCF LL_USART_ClearFlag_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2907 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR ( USART_TypeDef * USARTx )

Check if the USART Auto-Baud Rate Flag is set or not.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR ABRF LL_USART_IsActiveFlag_ABR
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2686 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE ( USART_TypeDef * USARTx )

Check if the USART Auto-Baud Rate Error Flag is set or not.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR ABRE LL_USART_IsActiveFlag_ABRE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2673 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY ( USART_TypeDef * USARTx )

Check if the USART Busy Flag is set or not.

Reference Manual to LL API cross reference:
ISR BUSY LL_USART_IsActiveFlag_BUSY
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2697 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM ( USART_TypeDef * USARTx )

Check if the USART Character Match Flag is set or not.

Reference Manual to LL API cross reference:
ISR CMF LL_USART_IsActiveFlag_CM
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2708 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS ( USART_TypeDef * USARTx )

Check if the USART CTS Flag is set or not.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR CTS LL_USART_IsActiveFlag_CTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2636 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB ( USART_TypeDef * USARTx )

Check if the USART End Of Block Flag is set or not.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR EOBF LL_USART_IsActiveFlag_EOB
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2660 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE ( USART_TypeDef * USARTx )

Check if the USART Framing Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR FE LL_USART_IsActiveFlag_FE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2531 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE ( USART_TypeDef * USARTx )

Check if the USART IDLE line detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR IDLE LL_USART_IsActiveFlag_IDLE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2564 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD ( USART_TypeDef * USARTx )

Check if the USART LIN Break Detection Flag is set or not.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR LBDF LL_USART_IsActiveFlag_LBD
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2610 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS ( USART_TypeDef * USARTx )

Check if the USART CTS interrupt Flag is set or not.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR CTSIF LL_USART_IsActiveFlag_nCTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2623 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE ( USART_TypeDef * USARTx )

Check if the USART Noise error detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR NF LL_USART_IsActiveFlag_NE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2542 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE ( USART_TypeDef * USARTx )

Check if the USART OverRun Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR ORE LL_USART_IsActiveFlag_ORE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2553 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE ( USART_TypeDef * USARTx )

Check if the USART Parity Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR PE LL_USART_IsActiveFlag_PE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2520 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK ( USART_TypeDef * USARTx )

Check if the USART Receive Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR REACK LL_USART_IsActiveFlag_REACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2765 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO ( USART_TypeDef * USARTx )

Check if the USART Receiver Time Out Flag is set or not.

Reference Manual to LL API cross reference:
ISR RTOF LL_USART_IsActiveFlag_RTO
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2647 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU ( USART_TypeDef * USARTx )

Check if the USART Receive Wake Up from mute mode Flag is set or not.

Reference Manual to LL API cross reference:
ISR RWU LL_USART_IsActiveFlag_RWU
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2730 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE ( USART_TypeDef * USARTx )

Check if the USART Read Data Register Not Empty Flag is set or not.

Reference Manual to LL API cross reference:
ISR RXNE LL_USART_IsActiveFlag_RXNE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2575 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK ( USART_TypeDef * USARTx )

Check if the USART Send Break Flag is set or not.

Reference Manual to LL API cross reference:
ISR SBKF LL_USART_IsActiveFlag_SBK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2719 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC ( USART_TypeDef * USARTx )

Check if the USART Transmission Complete Flag is set or not.

Reference Manual to LL API cross reference:
ISR TC LL_USART_IsActiveFlag_TC
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2586 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK ( USART_TypeDef * USARTx )

Check if the USART Transmit Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR TEACK LL_USART_IsActiveFlag_TEACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2754 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE ( USART_TypeDef * USARTx )

Check if the USART Transmit Data Register Empty Flag is set or not.

Reference Manual to LL API cross reference:
ISR TXE LL_USART_IsActiveFlag_TXE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2597 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP ( USART_TypeDef * USARTx )

Check if the USART Wake Up from stop mode Flag is set or not.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR WUF LL_USART_IsActiveFlag_WKUP
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2743 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IT_Management

Functions
IT_Management
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableIT_IDLE (USART_TypeDef *USARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXNE (USART_TypeDef *USARTx)
Enable RX Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TC (USART_TypeDef *USARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXE (USART_TypeDef *USARTx)
Enable TX Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_PE (USART_TypeDef *USARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CM (USART_TypeDef *USARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RTO (USART_TypeDef *USARTx)
Enable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_EOB (USART_TypeDef *USARTx)
Enable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_LBD (USART_TypeDef *USARTx)
Enable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_ERROR (USART_TypeDef *USARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CTS (USART_TypeDef *USARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_WKUP (USART_TypeDef *USARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_IDLE (USART_TypeDef *USARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXNE (USART_TypeDef *USARTx)
Disable RX Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TC (USART_TypeDef *USARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXE (USART_TypeDef *USARTx)
Disable TX Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_PE (USART_TypeDef *USARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CM (USART_TypeDef *USARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RTO (USART_TypeDef *USARTx)
Disable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_EOB (USART_TypeDef *USARTx)
Disable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_LBD (USART_TypeDef *USARTx)
Disable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_ERROR (USART_TypeDef *USARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CTS (USART_TypeDef *USARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_WKUP (USART_TypeDef *USARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXNE (USART_TypeDef *USARTx)
Check if the USART RX Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXE (USART_TypeDef *USARTx)
Check if the USART TX Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CM (USART_TypeDef *USARTx)
Check if the USART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RTO (USART_TypeDef *USARTx)
Check if the USART Receiver Timeout Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_EOB (USART_TypeDef *USARTx)
Check if the USART End Of Block Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_ERROR (USART_TypeDef *USARTx)
Check if the USART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_WKUP (USART_TypeDef *USARTx)
Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_USART_DisableIT_CM ( USART_TypeDef * USARTx )

Disable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_DisableIT_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3126 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_CTS ( USART_TypeDef * USARTx )

Disable CTS Interrupt.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_DisableIT_CTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3191 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_EOB ( USART_TypeDef * USARTx )

Disable End Of Block Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_DisableIT_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3150 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_ERROR ( USART_TypeDef * USARTx )

Disable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 0: Interrupt is inhibited 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_USART_DisableIT_ERROR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3178 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_IDLE ( USART_TypeDef * USARTx )

Disable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_DisableIT_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3071 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_LBD ( USART_TypeDef * USARTx )

Disable LIN Break Detection Interrupt.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_DisableIT_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3163 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_PE ( USART_TypeDef * USARTx )

Disable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_DisableIT_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3115 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RTO ( USART_TypeDef * USARTx )

Disable Receiver Timeout Interrupt.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_DisableIT_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3137 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RXNE ( USART_TypeDef * USARTx )

Disable RX Not Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 RXNEIE LL_USART_DisableIT_RXNE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3082 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TC ( USART_TypeDef * USARTx )

Disable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_DisableIT_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3093 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TXE ( USART_TypeDef * USARTx )

Disable TX Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 TXEIE LL_USART_DisableIT_TXE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3104 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_WKUP ( USART_TypeDef * USARTx )

Disable Wake Up from Stop Mode Interrupt.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_DisableIT_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3204 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_CM ( USART_TypeDef * USARTx )

Enable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_EnableIT_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2981 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_CTS ( USART_TypeDef * USARTx )

Enable CTS Interrupt.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_EnableIT_CTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3046 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_EOB ( USART_TypeDef * USARTx )

Enable End Of Block Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_EnableIT_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3005 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_ERROR ( USART_TypeDef * USARTx )

Enable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 0: Interrupt is inhibited 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_USART_EnableIT_ERROR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3033 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_IDLE ( USART_TypeDef * USARTx )

Enable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_EnableIT_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2926 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_LBD ( USART_TypeDef * USARTx )

Enable LIN Break Detection Interrupt.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_EnableIT_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3018 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_PE ( USART_TypeDef * USARTx )

Enable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_EnableIT_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2970 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RTO ( USART_TypeDef * USARTx )

Enable Receiver Timeout Interrupt.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_EnableIT_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2992 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RXNE ( USART_TypeDef * USARTx )

Enable RX Not Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 RXNEIE LL_USART_EnableIT_RXNE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2937 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TC ( USART_TypeDef * USARTx )

Enable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_EnableIT_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2948 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TXE ( USART_TypeDef * USARTx )

Enable TX Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 TXEIE LL_USART_EnableIT_TXE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2959 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_WKUP ( USART_TypeDef * USARTx )

Enable Wake Up from Stop Mode Interrupt.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_EnableIT_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3059 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM ( USART_TypeDef * USARTx )

Check if the USART Character Match Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_IsEnabledIT_CM
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3271 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS ( USART_TypeDef * USARTx )

Check if the USART CTS Interrupt is enabled or disabled.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_IsEnabledIT_CTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3332 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB ( USART_TypeDef * USARTx )

Check if the USART End Of Block Interrupt is enabled or disabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_IsEnabledIT_EOB
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3295 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR ( USART_TypeDef * USARTx )

Check if the USART Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 EIE LL_USART_IsEnabledIT_ERROR
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3319 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE ( USART_TypeDef * USARTx )

Check if the USART IDLE Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3216 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD ( USART_TypeDef * USARTx )

Check if the USART LIN Break Detection Interrupt is enabled or disabled.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_IsEnabledIT_LBD
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3308 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE ( USART_TypeDef * USARTx )

Check if the USART Parity Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_IsEnabledIT_PE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3260 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO ( USART_TypeDef * USARTx )

Check if the USART Receiver Timeout Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_IsEnabledIT_RTO
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3282 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE ( USART_TypeDef * USARTx )

Check if the USART RX Not Empty Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXNEIE LL_USART_IsEnabledIT_RXNE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3227 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC ( USART_TypeDef * USARTx )

Check if the USART Transmission Complete Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_IsEnabledIT_TC
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3238 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE ( USART_TypeDef * USARTx )

Check if the USART TX Empty Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXEIE LL_USART_IsEnabledIT_TXE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3249 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP ( USART_TypeDef * USARTx )

Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_IsEnabledIT_WKUP
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3345 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA_Management

Functions
DMA_Management
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableDMAReq_RX (USART_TypeDef *USARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_USART_DisableDMAReq_RX (USART_TypeDef *USARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_RX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_USART_EnableDMAReq_TX (USART_TypeDef *USARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_USART_DisableDMAReq_TX (USART_TypeDef *USARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_TX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_USART_EnableDMADeactOnRxErr (USART_TypeDef *USARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_USART_DisableDMADeactOnRxErr (USART_TypeDef *USARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMADeactOnRxErr (USART_TypeDef *USARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_USART_DMA_GetRegAddr (USART_TypeDef *USARTx, uint32_t Direction)
Get the data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr ( USART_TypeDef * USARTx )

Disable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_DisableDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3442 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDMAReq_RX ( USART_TypeDef * USARTx )

Disable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_DisableDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3376 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDMAReq_TX ( USART_TypeDef * USARTx )

Disable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_DisableDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3409 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Direction
 | ) |  |

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
RDR RDR LL_USART_DMA_GetRegAddr
Reference Manual to LL API cross reference:
TDR TDR LL_USART_DMA_GetRegAddr
Parameters:
USARTx USART Instance
Direction This parameter can be one of the following values:
  • LL_USART_DMA_REG_DATA_TRANSMIT
  • LL_USART_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 3468 of file stm32f3xx_ll_usart.h.

References LL_USART_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr ( USART_TypeDef * USARTx )

Enable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_EnableDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3431 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDMAReq_RX ( USART_TypeDef * USARTx )

Enable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_EnableDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3365 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDMAReq_TX ( USART_TypeDef * USARTx )

Enable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_EnableDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3398 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr ( USART_TypeDef * USARTx )

Indicate if DMA Disabling on Reception Error is disabled.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3453 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX ( USART_TypeDef * USARTx )

Check if DMA Mode is enabled for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_IsEnabledDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3387 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX ( USART_TypeDef * USARTx )

Check if DMA Mode is enabled for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_IsEnabledDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3420 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data_Management

Functions
Data_Management
USART Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_USART_ReceiveData8 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_USART_ReceiveData9 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_USART_TransmitData8 (USART_TypeDef *USARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_USART_TransmitData9 (USART_TypeDef *USARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)

Function Documentation

__STATIC_INLINE uint8_t LL_USART_ReceiveData8 ( USART_TypeDef * USARTx )

Read Receiver Data register (Receive Data value, 8 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_USART_ReceiveData8
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 3500 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE uint16_t LL_USART_ReceiveData9 ( USART_TypeDef * USARTx )

Read Receiver Data register (Receive Data value, 9 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_USART_ReceiveData9
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x1FF

Definition at line 3511 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_TransmitData8 | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 8 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_USART_TransmitData8
Parameters:
USARTx | USART Instance
Value | between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 3523 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_TransmitData9 | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 9 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_USART_TransmitData9
Parameters:
USARTx | USART Instance
Value | between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 3535 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Execution

Functions
Execution
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_RequestAutoBaudRate (USART_TypeDef *USARTx)
Request an Automatic Baud Rate measurement on next received data frame.
__STATIC_INLINE void | LL_USART_RequestBreakSending (USART_TypeDef *USARTx)
Request Break sending.
__STATIC_INLINE void | LL_USART_RequestEnterMuteMode (USART_TypeDef *USARTx)
Put USART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_USART_RequestRxDataFlush (USART_TypeDef *USARTx)
Request a Receive Data flush.
__STATIC_INLINE void | LL_USART_RequestTxDataFlush (USART_TypeDef *USARTx)
Request a Transmit data flush.

Function Documentation

__STATIC_INLINE void LL_USART_RequestAutoBaudRate ( USART_TypeDef * USARTx )

Request an Automatic Baud Rate measurement on next received data frame.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
RQR ABRRQ LL_USART_RequestAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3556 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestBreakSending ( USART_TypeDef * USARTx )

Request Break sending.

Reference Manual to LL API cross reference:
RQR SBKRQ LL_USART_RequestBreakSending
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3567 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestEnterMuteMode ( USART_TypeDef * USARTx )

Put USART in mute mode and set the RWU flag.

Reference Manual to LL API cross reference:
RQR MMRQ LL_USART_RequestEnterMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3578 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestRxDataFlush ( USART_TypeDef * USARTx )

Request a Receive Data flush.

Reference Manual to LL API cross reference:
RQR RXFRQ LL_USART_RequestRxDataFlush
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3589 of file stm32f3xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestTxDataFlush ( USART_TypeDef * USARTx )

Request a Transmit data flush.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
RQR TXFRQ LL_USART_RequestTxDataFlush
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3602 of file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
USART Exported Functions

Functions

ErrorStatus | LL_USART_DeInit (USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Function Documentation

ErrorStatus LL_USART_ClockInit | ( | USART_TypeDef * | USARTx,
 |  | LL_USART_ClockInitTypeDef * | USART_ClockInitStruct
 | ) |  |

Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.

Note:
As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
USARTx | USART Instance
USART_ClockInitStruct | pointer to a LL_USART_ClockInitTypeDef structure that contains the Clock configuration information for the specified USART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
  • ERROR: Problem occurred during USART Registers initialization

Definition at line 369 of file stm32f3xx_ll_usart.c.

References assert_param, LL_USART_ClockInitTypeDef::ClockOutput, LL_USART_ClockInitTypeDef::ClockPhase, LL_USART_ClockInitTypeDef::ClockPolarity, IS_LL_USART_CLOCKOUTPUT, IS_LL_USART_CLOCKPHASE, IS_LL_USART_CLOCKPOLARITY, IS_LL_USART_LASTBITCLKOUTPUT, LL_USART_ClockInitTypeDef::LastBitClockPulse, LL_USART_CLOCK_DISABLE, LL_USART_DisableSCLKOutput(), and LL_USART_IsEnabled().

void LL_USART_ClockStructInit ( LL_USART_ClockInitTypeDef * USART_ClockInitStruct )

Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Parameters:
USART_ClockInitStruct pointer to a LL_USART_ClockInitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 428 of file stm32f3xx_ll_usart.c.

References LL_USART_ClockInitTypeDef::ClockOutput, LL_USART_ClockInitTypeDef::ClockPhase, LL_USART_ClockInitTypeDef::ClockPolarity, LL_USART_ClockInitTypeDef::LastBitClockPulse, LL_USART_CLOCK_DISABLE, LL_USART_LASTCLKPULSE_NO_OUTPUT, LL_USART_PHASE_1EDGE, and LL_USART_POLARITY_LOW.

ErrorStatus LL_USART_DeInit ( USART_TypeDef * USARTx )

De-initialize USART registers (Registers restored to their default values).

Parameters:
USARTx USART Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers are de-initialized
  • ERROR: USART registers are not de-initialized

Definition at line 149 of file stm32f3xx_ll_usart.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_USART2, LL_APB1_GRP1_PERIPH_USART3, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_USART1, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_USART_Init | ( | USART_TypeDef * | USARTx,
 |  | LL_USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Initialize USART registers according to the specified parameters in USART_InitStruct.

Note:
As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
Parameters:
USARTx | USART Instance
USART_InitStruct | pointer to a LL_USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers are initialized according to USART_InitStruct content
  • ERROR: Problem occurred during USART Registers initialization

Definition at line 221 of file stm32f3xx_ll_usart.c.

References assert_param, LL_USART_InitTypeDef::BaudRate, LL_USART_InitTypeDef::DataWidth, LL_USART_InitTypeDef::HardwareFlowControl, IS_LL_USART_BAUDRATE, IS_LL_USART_BRR_MAX, IS_LL_USART_BRR_MIN, IS_LL_USART_DATAWIDTH, IS_LL_USART_DIRECTION, IS_LL_USART_HWCONTROL, IS_LL_USART_OVERSAMPLING, IS_LL_USART_PARITY, IS_LL_USART_STOPBITS, LL_RCC_GetSystemClocksFreq(), LL_RCC_GetUSARTClockFreq(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_USART1_CLKSOURCE, LL_RCC_USART2_CLKSOURCE, LL_RCC_USART3_CLKSOURCE, LL_USART_IsEnabled(), LL_USART_SetBaudRate(), LL_USART_SetHWFlowCtrl(), LL_USART_SetStopBitsLength(), LL_USART_InitTypeDef::OverSampling, LL_USART_InitTypeDef::Parity, LL_RCC_ClocksTypeDef::PCLK1_Frequency, LL_USART_InitTypeDef::StopBits, and LL_USART_InitTypeDef::TransferDirection.

void LL_USART_StructInit ( LL_USART_InitTypeDef * USART_InitStruct )

Set each LL_USART_InitTypeDef field to default value.

Parameters:
USART_InitStruct pointer to a LL_USART_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 345 of file stm32f3xx_ll_usart.c.

References LL_USART_InitTypeDef::BaudRate, LL_USART_InitTypeDef::DataWidth, LL_USART_InitTypeDef::HardwareFlowControl, LL_USART_DATAWIDTH_8B, LL_USART_DIRECTION_TX_RX, LL_USART_HWCONTROL_NONE, LL_USART_OVERSAMPLING_16, LL_USART_PARITY_NONE, LL_USART_STOPBITS_1, LL_USART_InitTypeDef::OverSampling, LL_USART_InitTypeDef::Parity, LL_USART_InitTypeDef::StopBits, and LL_USART_InitTypeDef::TransferDirection.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UTILS Private functions

Functions
UTILS Private functions
UTILS

Functions

static uint32_t | UTILS_GetPLLOutputFrequency (uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
Function to check that PLL can be modified.
static ErrorStatus | UTILS_SetFlashLatency (uint32_t Frequency)
Update number of Flash wait states in line with new frequency and current voltage range.
static ErrorStatus | UTILS_EnablePLLAndSwitchSystem (uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
Function to enable PLL and switch system clock to PLL.
static ErrorStatus | UTILS_PLL_IsBusy (void)
Function to check that PLL can be modified.

Function Documentation

static ErrorStatus UTILS_EnablePLLAndSwitchSystem | ( | uint32_t | SYSCLK_Frequency,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  | [static]

Function to enable PLL and switch system clock to PLL.

Parameters:
SYSCLK_Frequency | SYSCLK frequency
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: No problem to switch system to PLL
  • ERROR: Problem to switch system to PLL

Definition at line 513 of file stm32f3xx_ll_utils.c.

References __LL_RCC_CALC_HCLK_FREQ, LL_UTILS_ClkInitTypeDef::AHBCLKDivider, LL_UTILS_ClkInitTypeDef::APB1CLKDivider, LL_UTILS_ClkInitTypeDef::APB2CLKDivider, assert_param, IS_LL_UTILS_APB1_DIV, IS_LL_UTILS_APB2_DIV, IS_LL_UTILS_SYSCLK_DIV, LL_RCC_GetSysClkSource(), LL_RCC_PLL_Enable(), LL_RCC_PLL_IsReady(), LL_RCC_SetAHBPrescaler(), LL_RCC_SetAPB1Prescaler(), LL_RCC_SetAPB2Prescaler(), LL_RCC_SetSysClkSource(), LL_RCC_SYS_CLKSOURCE_PLL, LL_RCC_SYS_CLKSOURCE_STATUS_PLL, LL_SetSystemCoreClock(), RCC_POSITION_HPRE, and UTILS_SetFlashLatency().

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

static uint32_t UTILS_GetPLLOutputFrequency | ( | uint32_t | PLL_InputFrequency,
 |  | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct
 | ) |  | [static]

Function to check that PLL can be modified.

Parameters:
PLL_InputFrequency | PLL input frequency (in Hz)
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
Return values:
PLL output frequency (in Hz)

Definition at line 464 of file stm32f3xx_ll_utils.c.

References __LL_RCC_CALC_PLLCLK_FREQ, assert_param, IS_LL_UTILS_PLL_FREQUENCY, IS_LL_UTILS_PLLMUL_VALUE, LL_UTILS_PLLInitTypeDef::PLLMul, and LL_UTILS_PLLInitTypeDef::Prediv.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

static ErrorStatus UTILS_PLL_IsBusy ( void ) [static]

Function to check that PLL can be modified.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: PLL modification can be done
  • ERROR: PLL is busy

Definition at line 490 of file stm32f3xx_ll_utils.c.

References LL_RCC_PLL_IsReady().

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

static ErrorStatus UTILS_SetFlashLatency ( uint32_t Frequency ) [static]

Update number of Flash wait states in line with new frequency and current voltage range.

Parameters:
Frequency SYSCLK frequency
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Latency has been modified
  • ERROR: Latency cannot be modified

Definition at line 416 of file stm32f3xx_ll_utils.c.

References LL_FLASH_GetLatency(), LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_SetLatency(), UTILS_LATENCY1_FREQ, and UTILS_LATENCY2_FREQ.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UTILS Private Constants

Defines
UTILS Private Constants
UTILS

Defines

#define | UTILS_PLL_OUTPUT_MAX 72000000U
#define | UTILS_HSE_FREQUENCY_MIN 4000000U
#define | UTILS_HSE_FREQUENCY_MAX 32000000U
#define | UTILS_LATENCY1_FREQ 24000000U
#define | UTILS_LATENCY2_FREQ 48000000U
#define | LL_MAX_DELAY 0xFFFFFFFFU
#define | UID_BASE_ADDRESS UID_BASE
Unique device ID register base address.
#define | FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
Flash size data register base address.
#define | PACKAGE_BASE_ADDRESS PACKAGE_BASE
Package data register base address.

Define Documentation

#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE

Flash size data register base address.

Definition at line 86 of file stm32f3xx_ll_utils.h.

Referenced by LL_GetFlashSize().

#define LL_MAX_DELAY 0xFFFFFFFFU

Definition at line 76 of file stm32f3xx_ll_utils.h.

Referenced by LL_mDelay().

#define PACKAGE_BASE_ADDRESS PACKAGE_BASE

Package data register base address.

Definition at line 91 of file stm32f3xx_ll_utils.h.

#define UID_BASE_ADDRESS UID_BASE

Unique device ID register base address.

Definition at line 81 of file stm32f3xx_ll_utils.h.

Referenced by LL_GetUID_Word0(), LL_GetUID_Word1(), and LL_GetUID_Word2().

#define UTILS_HSE_FREQUENCY_MAX 32000000U

Frequency max for HSE frequency, in Hz

Definition at line 66 of file stm32f3xx_ll_utils.c.

#define UTILS_HSE_FREQUENCY_MIN 4000000U

Frequency min for HSE frequency, in Hz

Definition at line 65 of file stm32f3xx_ll_utils.c.

#define UTILS_LATENCY1_FREQ 24000000U

SYSCLK frequency to set FLASH latency 1

Definition at line 69 of file stm32f3xx_ll_utils.c.

Referenced by UTILS_SetFlashLatency().

#define UTILS_LATENCY2_FREQ 48000000U

SYSCLK frequency to set FLASH latency 2

Definition at line 70 of file stm32f3xx_ll_utils.c.

Referenced by UTILS_SetFlashLatency().

#define UTILS_PLL_OUTPUT_MAX 72000000U

Frequency max for PLL output, in Hz

Definition at line 62 of file stm32f3xx_ll_utils.c.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UTILS Private Macros

Defines
UTILS Private Macros
UTILS

Defines

#define | IS_LL_UTILS_SYSCLK_DIV(__VALUE__)
#define | IS_LL_UTILS_APB1_DIV(__VALUE__)
#define | IS_LL_UTILS_APB2_DIV(__VALUE__)
#define | IS_LL_UTILS_PLLMUL_VALUE(__VALUE__)
#define | IS_LL_UTILS_PREDIV_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
#define | IS_LL_UTILS_HSE_BYPASS(__STATE__)
#define | IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Define Documentation

#define IS_LL_UTILS_APB1_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_APB1_DIV_1) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))

Definition at line 88 of file stm32f3xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define IS_LL_UTILS_APB2_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_APB2_DIV_1) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_16))

Definition at line 94 of file stm32f3xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define IS_LL_UTILS_HSE_BYPASS ( __STATE__ )
Value:
(((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))

Definition at line 128 of file stm32f3xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE().

#define IS_LL_UTILS_HSE_FREQUENCY ( __FREQUENCY__ ) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Definition at line 131 of file stm32f3xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE().

#define IS_LL_UTILS_PLL_FREQUENCY ( __VALUE__ ) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)

Definition at line 125 of file stm32f3xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLMUL_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_PLL_MUL_2) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_3) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_10) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_11) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_13) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_14) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_15) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_16))

Definition at line 100 of file stm32f3xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PREDIV_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_PREDIV_DIV_1)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_2)   || \
                                             ((__VALUE__) == LL_RCC_PREDIV_DIV_3)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_4)   || \
                                             ((__VALUE__) == LL_RCC_PREDIV_DIV_5)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_6)   || \
                                             ((__VALUE__) == LL_RCC_PREDIV_DIV_7)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_8)   || \
                                             ((__VALUE__) == LL_RCC_PREDIV_DIV_9)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_10)  || \
                                             ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12)  || \
                                             ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14)  || \
                                             ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))

Definition at line 116 of file stm32f3xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

#define IS_LL_UTILS_SYSCLK_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))

Definition at line 78 of file stm32f3xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_UTILS_PLLInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_UTILS_PLLInitTypeDef Struct Reference
UTILS Exported structures

UTILS PLL structure definition. More...

#include <stm32f3xx_ll_utils.h>

Data Fields

uint32_t | PLLMul
uint32_t | Prediv

Detailed Description

UTILS PLL structure definition.

Definition at line 111 of file stm32f3xx_ll_utils.h.

Field Documentation

uint32_t LL_UTILS_PLLInitTypeDef::PLLMul

Multiplication factor for PLL VCO input clock. This parameter can be a value of PLL Multiplicator factor

This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().

Definition at line 113 of file stm32f3xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

uint32_t LL_UTILS_PLLInitTypeDef::Prediv

Division factor for HSE used as PLL clock source. This parameter can be a value of PREDIV Division factor

This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().

Definition at line 126 of file stm32f3xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_utils.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LL_UTILS_ClkInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_UTILS_ClkInitTypeDef Struct Reference
UTILS Exported structures

UTILS System, AHB and APB buses clock configuration structure definition. More...

#include <stm32f3xx_ll_utils.h>

Data Fields

uint32_t | AHBCLKDivider
uint32_t | APB1CLKDivider
uint32_t | APB2CLKDivider

Detailed Description

UTILS System, AHB and APB buses clock configuration structure definition.

Definition at line 137 of file stm32f3xx_ll_utils.h.

Field Documentation

uint32_t LL_UTILS_ClkInitTypeDef::AHBCLKDivider

The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB prescaler

This feature can be modified afterwards using unitary function LL_RCC_SetAHBPrescaler().

Definition at line 139 of file stm32f3xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::APB1CLKDivider

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB low-speed prescaler (APB1)

This feature can be modified afterwards using unitary function LL_RCC_SetAPB1Prescaler().

Definition at line 145 of file stm32f3xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::APB2CLKDivider

The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB high-speed prescaler (APB2)

This feature can be modified afterwards using unitary function LL_RCC_SetAPB2Prescaler().

Definition at line 151 of file stm32f3xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

The documentation for this struct was generated from the following file:
  • stm32f3xx_ll_utils.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HSE Bypass activation

Defines
HSE Bypass activation
UTILS Exported Constants

Defines

#define | LL_UTILS_HSEBYPASS_OFF 0x00000000U
#define | LL_UTILS_HSEBYPASS_ON 0x00000001U

Define Documentation

#define LL_UTILS_HSEBYPASS_OFF 0x00000000U

HSE Bypass is not enabled

Definition at line 171 of file stm32f3xx_ll_utils.h.

#define LL_UTILS_HSEBYPASS_ON 0x00000001U

HSE Bypass is enabled

Definition at line 172 of file stm32f3xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

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STM32F373xC HAL User Manual: DEVICE ELECTRONIC SIGNATURE

Functions
DEVICE ELECTRONIC SIGNATURE
UTILS Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_GetUID_Word0 (void)
Get Word0 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word1 (void)
Get Word1 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word2 (void)
Get Word2 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetFlashSize (void)
Get Flash memory size.

Function Documentation

__STATIC_INLINE uint32_t LL_GetFlashSize ( void )

Get Flash memory size.

Note:
This bitfield indicates the size of the device Flash memory expressed in Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
Return values:
FLASH_SIZE[15:0],: Flash memory size

Definition at line 225 of file stm32f3xx_ll_utils.h.

References FLASHSIZE_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word0 ( void )

Get Word0 of the unique device identifier (UID based on 96 bits)

Return values:
UID[31:0],: X and Y coordinates on the wafer expressed in BCD format

Definition at line 196 of file stm32f3xx_ll_utils.h.

References UID_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word1 ( void )

Get Word1 of the unique device identifier (UID based on 96 bits)

Return values:
UID[63:32],: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])

Definition at line 205 of file stm32f3xx_ll_utils.h.

References UID_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word2 ( void )

Get Word2 of the unique device identifier (UID based on 96 bits)

Return values:
UID[95:64],: Lot number (ASCII encoded) - LOT_NUM[55:24]

Definition at line 214 of file stm32f3xx_ll_utils.h.

References UID_BASE_ADDRESS.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DELAY

Functions
DELAY
UTILS Exported Functions

Functions

void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
__STATIC_INLINE void | LL_InitTick (uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.

Function Documentation

void LL_Init1msTick ( uint32_t HCLKFrequency )

This function configures the Cortex-M SysTick source to have 1ms time base.

Note:
When a RTOS is used, it is recommended to avoid changing the Systick configuration by calling this function, for a delay use rather osDelay RTOS service.
Parameters:
HCLKFrequency HCLK frequency in Hz
Note:
HCLK frequency can be calculated thanks to RCC helper macro or function LL_RCC_GetSystemClocksFreq
Return values:
None

Definition at line 167 of file stm32f3xx_ll_utils.c.

References LL_InitTick().

__STATIC_INLINE void LL_InitTick | ( | uint32_t | HCLKFrequency,
 |  | uint32_t | Ticks
 | ) |  |

This function configures the Cortex-M SysTick source of the time base.

Parameters:
HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
Note:
When a RTOS is used, it is recommended to avoid changing the SysTick configuration by calling this function, for a delay use rather osDelay RTOS service.
Parameters:
Ticks Number of ticks
Return values:
None

Definition at line 247 of file stm32f3xx_ll_utils.h.

Referenced by LL_Init1msTick().

void LL_mDelay ( uint32_t Delay )

This function provides accurate delay (in milliseconds) based on SysTick counter flag.

Note:
When a RTOS is used, it is recommended to avoid using blocking delay and use rather osDelay service.
To respect 1ms timebase, user should call LL_Init1msTick function which will configure Systick to 1ms
Parameters:
Delay specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 183 of file stm32f3xx_ll_utils.c.

References LL_MAX_DELAY.

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STM32F373xC HAL User Manual: SYSTEM

Functions
SYSTEM
UTILS Exported Functions

System Configuration functions. More...

Functions

void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

System Configuration functions.

 ===============================================================================
           ##### System Configuration functions #####
 ===============================================================================
    [..]
         System, AHB and APB buses clocks configuration

         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72000000 Hz.

Function Documentation

ErrorStatus LL_PLL_ConfigSystemClock_HSE | ( | uint32_t | HSEFrequency,
 |  | uint32_t | HSEBypass,
 |  | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  |

This function configures system clock with HSE as clock source of the PLL.

Note:
The application need to ensure that PLL is disabled.
Function is based on the following formula:
  • PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
  • PREDIV: Set to 2 for few devices
  • PLLMUL: The application software must set correctly the PLL multiplication factor to not exceed UTILS_PLL_OUTPUT_MAX
FLASH latency can be modified through this function.
Parameters:
HSEFrequency | Value between Min_Data = 4000000 and Max_Data = 32000000
HSEBypass This parameter can be one of the following values:
  • LL_UTILS_HSEBYPASS_ON
  • LL_UTILS_HSEBYPASS_OFF
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 333 of file stm32f3xx_ll_utils.c.

References assert_param, IS_LL_UTILS_HSE_BYPASS, IS_LL_UTILS_HSE_FREQUENCY, IS_LL_UTILS_PREDIV_VALUE, LL_RCC_HSE_DisableBypass(), LL_RCC_HSE_Enable(), LL_RCC_HSE_EnableBypass(), LL_RCC_HSE_IsReady(), LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_HSE, LL_UTILS_HSEBYPASS_ON, LL_UTILS_PLLInitTypeDef::PLLMul, LL_UTILS_PLLInitTypeDef::Prediv, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

ErrorStatus LL_PLL_ConfigSystemClock_HSI | ( | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  |

This function configures system clock with HSI as clock source of the PLL.

Note:
The application need to ensure that PLL is disabled.
Function is based on the following formula:
  • PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
  • PREDIV: Set to 2 for few devices
  • PLLMUL: The application software must set correctly the PLL multiplication factor to not exceed 72MHz
FLASH latency can be modified through this function.
Parameters:
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 264 of file stm32f3xx_ll_utils.c.

References assert_param, HSI_VALUE, IS_LL_UTILS_PREDIV_VALUE, LL_RCC_HSI_Enable(), LL_RCC_HSI_IsReady(), LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_HSI_DIV_2, LL_RCC_PREDIV_DIV_2, LL_UTILS_PLLInitTypeDef::PLLMul, LL_UTILS_PLLInitTypeDef::Prediv, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

void LL_SetSystemCoreClock ( uint32_t HCLKFrequency )

This function sets directly SystemCoreClock CMSIS variable.

Note:
Variable can be calculated also through SystemCoreClockUpdate function.
Parameters:
HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
Return values:
None

Definition at line 241 of file stm32f3xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

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STM32F373xC HAL User Manual: WWDG

Modules
WWDG
STM32F3xx_LL_Driver

Modules

WWDG Exported Constants
WWDG Exported Macros
WWDG Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for WWDG registers.

Register | Bit | Function
CFR | EWI | LL_WWDG_EnableIT_EWKUP
 |  | LL_WWDG_IsEnabledIT_EWKUP
 | W | LL_WWDG_GetWindow
 |  | LL_WWDG_SetWindow
 | WDGTB | LL_WWDG_GetPrescaler
 |  | LL_WWDG_SetPrescaler
CR | T | LL_WWDG_GetCounter
 |  | LL_WWDG_SetCounter
 | WDGA | LL_WWDG_Enable
 |  | LL_WWDG_IsEnabled
SR | EWIF | LL_WWDG_ClearFlag_EWKUP
 |  | LL_WWDG_IsActiveFlag_EWKUP
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STM32F373xC HAL User Manual: IT Defines

Defines
IT Defines
WWDG Exported Constants

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions. More...

Defines

#define LL_WWDG_CFR_EWI WWDG_CFR_EWI

Detailed Description

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions.

Define Documentation

#define LL_WWDG_CFR_EWI WWDG_CFR_EWI

Definition at line 75 of file stm32f3xx_ll_wwdg.h.

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STM32F373xC HAL User Manual: PRESCALER

Defines
PRESCALER
WWDG Exported Constants

Defines

#define | LL_WWDG_PRESCALER_1 0x00000000U
#define | LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)

Define Documentation

#define LL_WWDG_PRESCALER_1 0x00000000U

WWDG counter clock = (PCLK1/4096)/1

Definition at line 83 of file stm32f3xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0

WWDG counter clock = (PCLK1/4096)/2

Definition at line 84 of file stm32f3xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1

WWDG counter clock = (PCLK1/4096)/4

Definition at line 85 of file stm32f3xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)

WWDG counter clock = (PCLK1/4096)/8

Definition at line 86 of file stm32f3xx_ll_wwdg.h.

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STM32F373xC HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
WWDG Exported Macros

Defines

#define | LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in WWDG register.
#define | LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in WWDG register.

Define Documentation

#define LL_WWDG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in WWDG register.

Parameters:
__INSTANCE__ | WWDG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 117 of file stm32f3xx_ll_wwdg.h.

#define LL_WWDG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in WWDG register.

Parameters:
__INSTANCE__ | WWDG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 109 of file stm32f3xx_ll_wwdg.h.

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STM32F373xC HAL User Manual: Configuration

Functions
Configuration
WWDG Exported Functions

Functions

__STATIC_INLINE void | LL_WWDG_Enable (WWDG_TypeDef *WWDGx)
Enable Window Watchdog.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabled (WWDG_TypeDef *WWDGx)
Checks if Window Watchdog is enabled.
__STATIC_INLINE void | LL_WWDG_SetCounter (WWDG_TypeDef *WWDGx, uint32_t Counter)
Set the Watchdog counter value to provided value (7-bits T[6:0])
__STATIC_INLINE uint32_t | LL_WWDG_GetCounter (WWDG_TypeDef *WWDGx)
Return current Watchdog Counter Value (7 bits counter value)
__STATIC_INLINE void | LL_WWDG_SetPrescaler (WWDG_TypeDef *WWDGx, uint32_t Prescaler)
Set the time base of the prescaler (WDGTB).
__STATIC_INLINE uint32_t | LL_WWDG_GetPrescaler (WWDG_TypeDef *WWDGx)
Return current Watchdog Prescaler Value.
__STATIC_INLINE void | LL_WWDG_SetWindow (WWDG_TypeDef *WWDGx, uint32_t Window)
Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
__STATIC_INLINE uint32_t | LL_WWDG_GetWindow (WWDG_TypeDef *WWDGx)
Return current Watchdog Window Value (7 bits value)

Function Documentation

__STATIC_INLINE void LL_WWDG_Enable ( WWDG_TypeDef * WWDGx )

Enable Window Watchdog.

The watchdog is always disabled after a reset.

Note:
It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot be disabled again except by a reset. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset.
Reference Manual to LL API cross reference:
CR WDGA LL_WWDG_Enable
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 145 of file stm32f3xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetCounter ( WWDG_TypeDef * WWDGx )

Return current Watchdog Counter Value (7 bits counter value)

Reference Manual to LL API cross reference:
CR T LL_WWDG_GetCounter
Parameters:
WWDGx WWDG Instance
Return values:
7 bit Watchdog Counter value

Definition at line 183 of file stm32f3xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler ( WWDG_TypeDef * WWDGx )

Return current Watchdog Prescaler Value.

Reference Manual to LL API cross reference:
CFR WDGTB LL_WWDG_GetPrescaler
Parameters:
WWDGx WWDG Instance
Return values:
Returned value can be one of the following values:
  • LL_WWDG_PRESCALER_1
  • LL_WWDG_PRESCALER_2
  • LL_WWDG_PRESCALER_4
  • LL_WWDG_PRESCALER_8

Definition at line 216 of file stm32f3xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetWindow ( WWDG_TypeDef * WWDGx )

Return current Watchdog Window Value (7 bits value)

Reference Manual to LL API cross reference:
CFR W LL_WWDG_GetWindow
Parameters:
WWDGx WWDG Instance
Return values:
7 bit Watchdog Window value

Definition at line 248 of file stm32f3xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsEnabled ( WWDG_TypeDef * WWDGx )

Checks if Window Watchdog is enabled.

Reference Manual to LL API cross reference:
CR WDGA LL_WWDG_IsEnabled
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 156 of file stm32f3xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetCounter | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Counter
 | ) |  |

Set the Watchdog counter value to provided value (7-bits T[6:0])

Note:
When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset This counter is decremented every (4096 x 2expWDGTB) PCLK cycles A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared) Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
Reference Manual to LL API cross reference:
CR T LL_WWDG_SetCounter
Parameters:
WWDGx | WWDG Instance
Counter | 0..0x7F (7 bit counter value)
Return values:
None

Definition at line 172 of file stm32f3xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetPrescaler | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Prescaler
 | ) |  |

Set the time base of the prescaler (WDGTB).

Note:
Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter is decremented every (4096 x 2expWDGTB) PCLK cycles
Reference Manual to LL API cross reference:
CFR WDGTB LL_WWDG_SetPrescaler
Parameters:
WWDGx WWDG Instance
Prescaler This parameter can be one of the following values:
  • LL_WWDG_PRESCALER_1
  • LL_WWDG_PRESCALER_2
  • LL_WWDG_PRESCALER_4
  • LL_WWDG_PRESCALER_8
Return values:
None

Definition at line 201 of file stm32f3xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetWindow | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Window
 | ) |  |

Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).

Note:
This window value defines when write in the WWDG_CR register to program Watchdog counter is allowed. Watchdog counter value update must occur only when the counter value is lower than the Watchdog window register value. Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value (in the control register) is refreshed before the downcounter has reached the watchdog window register value. Physically is possible to set the Window lower then 0x40 but it is not recommended. To generate an immediate reset, it is possible to set the Counter lower than 0x40.
Reference Manual to LL API cross reference:
CFR W LL_WWDG_SetWindow
Parameters:
WWDGx | WWDG Instance
Window | 0x00..0x7F (7 bit Window value)
Return values:
None

Definition at line 237 of file stm32f3xx_ll_wwdg.h.

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STM32F373xC HAL User Manual: FLAG_Management

Functions
FLAG_Management
WWDG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_WWDG_IsActiveFlag_EWKUP (WWDG_TypeDef *WWDGx)
Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
__STATIC_INLINE void | LL_WWDG_ClearFlag_EWKUP (WWDG_TypeDef *WWDGx)
Clear WWDG Early Wakeup Interrupt Flag (EWIF)

Function Documentation

__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP ( WWDG_TypeDef * WWDGx )

Clear WWDG Early Wakeup Interrupt Flag (EWIF)

Reference Manual to LL API cross reference:
SR EWIF LL_WWDG_ClearFlag_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 280 of file stm32f3xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP ( WWDG_TypeDef * WWDGx )

Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.

Note:
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
Reference Manual to LL API cross reference:
SR EWIF LL_WWDG_IsActiveFlag_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 269 of file stm32f3xx_ll_wwdg.h.

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STM32F373xC HAL User Manual: IT_Management

Functions
IT_Management
WWDG Exported Functions

Functions

__STATIC_INLINE void | LL_WWDG_EnableIT_EWKUP (WWDG_TypeDef *WWDGx)
Enable the Early Wakeup Interrupt.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabledIT_EWKUP (WWDG_TypeDef *WWDGx)
Check if Early Wakeup Interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP ( WWDG_TypeDef * WWDGx )

Enable the Early Wakeup Interrupt.

Note:
When set, an interrupt occurs whenever the counter reaches value 0x40. This interrupt is only cleared by hardware after a reset
Reference Manual to LL API cross reference:
CFR EWI LL_WWDG_EnableIT_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 300 of file stm32f3xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP ( WWDG_TypeDef * WWDGx )

Check if Early Wakeup Interrupt is enabled.

Reference Manual to LL API cross reference:
CFR EWI LL_WWDG_IsEnabledIT_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 311 of file stm32f3xx_ll_wwdg.h.

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STM32F373xC HAL User Manual: Constants

Defines
Constants
HAL

Defines

#define | __STM32F3xx_HAL_VERSION_MAIN (0x01U)
STM32F3xx HAL Driver version number V1.5.0.
#define | __STM32F3xx_HAL_VERSION_SUB1 (0x05U)
#define | __STM32F3xx_HAL_VERSION_SUB2 (0x00U)
#define | __STM32F3xx_HAL_VERSION_RC (0x00U)
#define | __STM32F3xx_HAL_VERSION
#define | IDCODE_DEVID_MASK (0x00000FFFU)

Define Documentation

#define __STM32F3xx_HAL_VERSION
Value:
((__STM32F3xx_HAL_VERSION_MAIN << 24U)\
                                        |(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\
                                        |(__STM32F3xx_HAL_VERSION_SUB2 << 8U )\
                                        |(__STM32F3xx_HAL_VERSION_RC))

Definition at line 77 of file stm32f3xx_hal.c.

Referenced by HAL_GetHalVersion().

#define __STM32F3xx_HAL_VERSION_MAIN (0x01U)

STM32F3xx HAL Driver version number V1.5.0.

[31:24] main version

Definition at line 73 of file stm32f3xx_hal.c.

#define __STM32F3xx_HAL_VERSION_RC (0x00U)

[7:0] release candidate

Definition at line 76 of file stm32f3xx_hal.c.

#define __STM32F3xx_HAL_VERSION_SUB1 (0x05U)

[23:16] sub1 version

Definition at line 74 of file stm32f3xx_hal.c.

#define __STM32F3xx_HAL_VERSION_SUB2 (0x00U)

[15:8] sub2 version

Definition at line 75 of file stm32f3xx_hal.c.

#define IDCODE_DEVID_MASK (0x00000FFFU)

Definition at line 82 of file stm32f3xx_hal.c.

Referenced by HAL_GetDEVID().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HAL Private Variables

Variables
HAL Private Variables
HAL

Variables

__IO uint32_t uwTick

Variable Documentation

__IO uint32_t uwTick

Definition at line 92 of file stm32f3xx_hal.c.

Referenced by HAL_GetTick(), and HAL_IncTick().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization Functions

Functions
Initialization and de-initialization Functions
HAL Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function configures the Flash prefetch, Configures time base source, NVIC and Low level hardware.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the source of time base.
__weak void | HAL_MspInit (void)
Initializes the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initializes the Flash interface, the NVIC allocation and initial clock
          configuration. It initializes the source of time base also when timeout
          is needed and the backup domain when enabled.
      (+) de-Initializes common part of the HAL.
      (+) Configure The time base source to have 1ms time base with a dedicated
          Tick interrupt priority.
        (++) Systick timer is used by default as source of time base, but user
             can eventually implement his proper time base source (a general purpose
             timer for example or other time source), keeping in mind that Time base
             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
             handled in milliseconds basis.
        (++) Time base configuration function (HAL_InitTick ()) is called automatically
             at the beginning of the program after reset by HAL_Init() or at any time
             when clock is configured, by HAL_RCC_ClockConfig().
        (++) Source of time base is configured  to generate interrupts at regular
             time intervals. Care must be taken if HAL_Delay() is called from a
             peripheral ISR process, the Tick interrupt line must have higher priority
            (numerically lower) than the peripheral interrupt. Otherwise the caller
            ISR process will be blocked.
       (++) functions affecting time base configurations are declared as __Weak
             to make  override possible  in case of other  implementations in user file.

Function Documentation

HAL_StatusTypeDef HAL_DeInit ( void )

This function de-Initializes common part of the HAL and stops the source of time base.

Note:
This function is optional.
Return values:
HAL status

Definition at line 178 of file stm32f3xx_hal.c.

References __HAL_RCC_AHB_FORCE_RESET, __HAL_RCC_AHB_RELEASE_RESET, __HAL_RCC_APB1_FORCE_RESET, __HAL_RCC_APB1_RELEASE_RESET, __HAL_RCC_APB2_FORCE_RESET, __HAL_RCC_APB2_RELEASE_RESET, and HAL_MspDeInit().

HAL_StatusTypeDef HAL_Init ( void )

This function configures the Flash prefetch, Configures time base source, NVIC and Low level hardware.

Note:
This function is called at the beginning of program after reset and before the clock configuration
The Systick configuration is based on HSI clock, as HSI is the clock used after a system Reset and the NVIC configuration is set to Priority group 4
The time base configuration is based on MSI clock when exting from Reset. Once done, time base tick start incrementing. In the default implementation,Systick is used as source of time base. The tick variable is incremented each 1ms in its ISR.
Return values:
HAL status

Definition at line 152 of file stm32f3xx_hal.c.

References __HAL_FLASH_PREFETCH_BUFFER_ENABLE, HAL_InitTick(), HAL_MspInit(), HAL_NVIC_SetPriorityGrouping(), NVIC_PRIORITYGROUP_4, and TICK_INT_PRIORITY.

HAL_StatusTypeDef HAL_InitTick ( uint32_t TickPriority )

This function configures the source of the time base.

The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.

Note:
This function is called automatically at the beginning of program after reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Care must be taken if HAL_Delay() is called from a peripheral ISR process, The the SysTick interrupt must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. The function is declared as __Weak to be overwritten in case of other implementation in user file.
Parameters:
TickPriority Tick interrupt priority.
Return values:
HAL status

Definition at line 235 of file stm32f3xx_hal.c.

References HAL_NVIC_SetPriority(), and HAL_SYSTICK_Config().

Referenced by HAL_Init(), and HAL_RCC_ClockConfig().

void HAL_MspDeInit ( void )

DeInitializes the MSP.

Return values:
None

Definition at line 212 of file stm32f3xx_hal.c.

Referenced by HAL_DeInit().

void HAL_MspInit ( void )

Initializes the MSP.

Return values:
None

Definition at line 201 of file stm32f3xx_hal.c.

Referenced by HAL_Init().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HAL Control functions

Functions
HAL Control functions
HAL Exported Functions

HAL Control functions. More...

Functions

__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Povides a tick value in millisecond.
__weak void | HAL_Delay (__IO uint32_t Delay)
This function provides accurate delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
This function returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
uint32_t | HAL_GetUIDw0 (void)
Returns first word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw1 (void)
Returns second word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw2 (void)
Returns third word of the unique device identifier (UID based on 96 bits)
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.

Detailed Description

HAL Control functions.

 ===============================================================================
                      ##### HAL Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Provide a tick value in millisecond
      (+) Provide a blocking delay in millisecond
      (+) Suspend the time base source interrupt
      (+) Resume the time base source interrupt
      (+) Get the HAL API driver version
      (+) Get the device identifier
      (+) Get the device revision identifier
      (+) Enable/Disable Debug module during Sleep mode
      (+) Enable/Disable Debug module during STOP mode
      (+) Enable/Disable Debug module during STANDBY mode

Function Documentation

void HAL_DBGMCU_DisableDBGSleepMode ( void )

Disable the Debug Module during SLEEP mode.

Return values:
None

Definition at line 428 of file stm32f3xx_hal.c.

void HAL_DBGMCU_DisableDBGStandbyMode ( void )

Disable the Debug Module during STANDBY mode.

Return values:
None

Definition at line 464 of file stm32f3xx_hal.c.

void HAL_DBGMCU_DisableDBGStopMode ( void )

Disable the Debug Module during STOP mode.

Return values:
None

Definition at line 446 of file stm32f3xx_hal.c.

void HAL_DBGMCU_EnableDBGSleepMode ( void )

Enable the Debug Module during SLEEP mode.

Return values:
None

Definition at line 419 of file stm32f3xx_hal.c.

void HAL_DBGMCU_EnableDBGStandbyMode ( void )

Enable the Debug Module during STANDBY mode.

Return values:
None

Definition at line 455 of file stm32f3xx_hal.c.

void HAL_DBGMCU_EnableDBGStopMode ( void )

Enable the Debug Module during STOP mode.

Return values:
None

Definition at line 437 of file stm32f3xx_hal.c.

void HAL_Delay ( __IO uint32_t Delay )

This function provides accurate delay (in milliseconds) based on variable incremented.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals where uwTick is incremented. The function is declared as __Weak to be overwritten in case of other implementations in user file.
Parameters:
Delay specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 310 of file stm32f3xx_hal.c.

References HAL_GetTick().

Referenced by HAL_OPAMPEx_SelfCalibrateAll(), and HAL_SDADC_Init().

uint32_t HAL_GetDEVID ( void )

Returns the device identifier.

Return values:
Device identifier

Definition at line 383 of file stm32f3xx_hal.c.

References IDCODE_DEVID_MASK.

uint32_t HAL_GetHalVersion ( void )

This function returns the HAL revision.

Return values:
version : 0xXYZR (8bits for each decimal, R for RC)

Definition at line 365 of file stm32f3xx_hal.c.

References __STM32F3xx_HAL_VERSION.

uint32_t HAL_GetREVID ( void )

Returns the device revision identifier.

Return values:
Device revision identifier

Definition at line 374 of file stm32f3xx_hal.c.

uint32_t HAL_GetTick ( void )

Povides a tick value in millisecond.

Note:
The function is declared as __Weak to be overwritten in case of other implementations in user file.
Return values:
tick value

Definition at line 294 of file stm32f3xx_hal.c.

References uwTick.

Referenced by ADC_ConversionStop_Disable(), ADC_Enable(), FLASH_WaitForLastOperation(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_CAN_Init(), HAL_CAN_Receive(), HAL_CAN_Sleep(), HAL_CAN_Transmit(), HAL_CAN_WakeUp(), HAL_Delay(), HAL_DMA_PollForTransfer(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), HAL_IRDA_Receive(), HAL_IRDA_Transmit(), HAL_IWDG_Init(), HAL_RCC_ClockConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_PeriphCLKConfig(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SDADC_PollForCalibEvent(), HAL_SDADC_PollForConversion(), HAL_SDADC_PollForInjectedConversion(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit(), HAL_SMBUS_IsDeviceReady(), HAL_SPI_Abort(), HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), I2C_IsAcknowledgeFailed(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), I2S_WaitFlagStateUntilTimeout(), IRDA_CheckIdleState(), IRDA_WaitOnFlagUntilTimeout(), RTC_EnterInitMode(), SDADC_EnterInitMode(), SDADC_InjConvStop(), SDADC_RegConvStop(), SMARTCARD_CheckIdleState(), SMARTCARD_WaitOnFlagUntilTimeout(), SMBUS_WaitOnFlagUntilTimeout(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), UART_CheckIdleState(), UART_WaitOnFlagUntilTimeout(), USART_CheckIdleState(), and USART_WaitOnFlagUntilTimeout().

uint32_t HAL_GetUIDw0 ( void )

Returns first word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 392 of file stm32f3xx_hal.c.

uint32_t HAL_GetUIDw1 ( void )

Returns second word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 401 of file stm32f3xx_hal.c.

uint32_t HAL_GetUIDw2 ( void )

Returns third word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 410 of file stm32f3xx_hal.c.

void HAL_IncTick ( void )

This function is called to increment a global variable "uwTick" used as application time base.

Note:
In the default implementation, this variable is incremented each 1ms in Systick ISR.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 283 of file stm32f3xx_hal.c.

References uwTick.

void HAL_ResumeTick ( void )

Resume Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_ResumeTick() is called, the the SysTick interrupt will be enabled and so Tick increment is resumed. The function is declared as __Weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 354 of file stm32f3xx_hal.c.

void HAL_SuspendTick ( void )

Suspend Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_SuspendTick() is called, the the SysTick interrupt will be disabled and so Tick increment is suspended.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 336 of file stm32f3xx_hal.c.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SYSCFG registers bit address in the alias region

Defines
SYSCFG registers bit address in the alias region
HAL Exported Constants

SYSCFG registers bit address in the alias region. More...

Defines

#define | SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
#define | CFGR2_OFFSET (SYSCFG_OFFSET + 0x18U)
#define | BYPADDRPAR_BitNumber 0x04U
#define | CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32U) + (BYPADDRPAR_BitNumber * 4U))

Detailed Description

SYSCFG registers bit address in the alias region.

Define Documentation

#define BYPADDRPAR_BitNumber 0x04U

Definition at line 82 of file stm32f3xx_hal.h.

#define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32U) + (BYPADDRPAR_BitNumber * 4U))

Definition at line 83 of file stm32f3xx_hal.h.

#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18U)

Definition at line 81 of file stm32f3xx_hal.h.

#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)

Definition at line 78 of file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HAL DMA Remapping

Defines
HAL DMA Remapping
HAL Exported Constants

Elements values convention: 0xXXYYYYYY. More...

Defines

#define | HAL_REMAPDMA_ADC24_DMA2_CH34 (0x00000100U)
#define | HAL_REMAPDMA_TIM16_DMA1_CH6 (0x00000800U)
#define | HAL_REMAPDMA_TIM17_DMA1_CH7 (0x00001000U)
#define | HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 (0x00002000U)
#define | HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 (0x00004000U)
#define | HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 (0x00008000U)
#define | HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U)
#define | IS_DMA_REMAP(RMP)

Detailed Description

Elements values convention: 0xXXYYYYYY.

  • YYYYYY : Position in the register
  • XX : Register index
    • 00: CFGR1 register in SYSCFG
    • 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices)

Define Documentation

#define HAL_REMAPDMA_ADC24_DMA2_CH34 (0x00000100U)

ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) 1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4)

Definition at line 97 of file stm32f3xx_hal.h.

#define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 (0x00008000U)

DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only) 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5)

Definition at line 107 of file stm32f3xx_hal.h.

#define HAL_REMAPDMA_TIM16_DMA1_CH6 (0x00000800U)

TIM16 DMA request remap 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6)

Definition at line 99 of file stm32f3xx_hal.h.

#define HAL_REMAPDMA_TIM17_DMA1_CH7 (0x00001000U)

TIM17 DMA request remap 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7)

Definition at line 101 of file stm32f3xx_hal.h.

#define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U)

DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only) 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5)

Definition at line 109 of file stm32f3xx_hal.h.

#define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 (0x00002000U)

TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) 1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3)

Definition at line 103 of file stm32f3xx_hal.h.

#define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 (0x00004000U)

TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4)

Definition at line 105 of file stm32f3xx_hal.h.

#define IS_DMA_REMAP ( RMP )
Value:
((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34)         == HAL_REMAPDMA_ADC24_DMA2_CH34)         || \
                              (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6)          == HAL_REMAPDMA_TIM16_DMA1_CH6)          || \
                              (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7)          == HAL_REMAPDMA_TIM17_DMA1_CH7)          || \
                              (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3)  == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3)  || \
                              (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4)  == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4)  || \
                              (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5)       == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5)       || \
                              (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5))

Definition at line 170 of file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HAL Trigger Remapping

Defines
HAL Trigger Remapping
HAL Exported Constants

Elements values convention: 0xXXYYYYYY. More...

Defines

#define | HAL_REMAPTRIGGER_DAC1_TRIG (0x00000080U)
#define | HAL_REMAPTRIGGER_TIM1_ITR3 (0x00000040U)
#define | IS_HAL_REMAPTRIGGER(RMP)

Detailed Description

Elements values convention: 0xXXYYYYYY.

  • YYYYYY : Position in the register
  • XX : Register index
    • 00: CFGR1 register in SYSCFG
    • 01: CFGR3 register in SYSCFG

Define Documentation

#define HAL_REMAPTRIGGER_DAC1_TRIG (0x00000080U)

DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices) 0: No remap (DAC trigger is TIM8_TRGO) 1: Remap (DAC trigger is TIM3_TRGO)

Definition at line 191 of file stm32f3xx_hal.h.

#define HAL_REMAPTRIGGER_TIM1_ITR3 (0x00000040U)

TIM1 ITR3 trigger remap 0: No remap 1: Remap (TIM1_TRG3 = TIM17_OC)

Definition at line 194 of file stm32f3xx_hal.h.

#define IS_HAL_REMAPTRIGGER ( RMP )
Value:
((((RMP) & HAL_REMAPTRIGGER_DAC1)       == HAL_REMAPTRIGGER_DAC1)       || \
                                  (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3)  == HAL_REMAPTRIGGER_TIM1_ITR3))

Definition at line 212 of file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Fast-mode Plus on GPIO

Defines
Fast-mode Plus on GPIO
HAL Exported Constants

Defines

#define | SYSCFG_FASTMODEPLUS_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP)
Fast-mode Plus driving capability on a specific GPIO.
#define | SYSCFG_FASTMODEPLUS_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP)
#define | SYSCFG_FASTMODEPLUS_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP)
#define | SYSCFG_FASTMODEPLUS_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP)

Define Documentation

#define SYSCFG_FASTMODEPLUS_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP)

Fast-mode Plus driving capability on a specific GPIO.

Enable Fast-mode Plus on PB6

Definition at line 334 of file stm32f3xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP)

Enable Fast-mode Plus on PB7

Definition at line 338 of file stm32f3xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP)

Enable Fast-mode Plus on PB8

Definition at line 342 of file stm32f3xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP)

Enable Fast-mode Plus on PB9

Definition at line 346 of file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HAL SYSCFG Interrupts

Defines
HAL SYSCFG Interrupts
HAL Exported Constants

Defines

#define | HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0)
#define | HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1)
#define | HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2)
#define | HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3)
#define | HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4)
#define | HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5)
#define | IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__)

Define Documentation

#define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1)

Floating Point Unit Divide-by-zero Interrupt

Definition at line 395 of file stm32f3xx_hal.h.

#define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4)

Floating Point Unit Input denormal Interrupt

Definition at line 398 of file stm32f3xx_hal.h.

#define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0)

Floating Point Unit Invalid operation Interrupt

Definition at line 394 of file stm32f3xx_hal.h.

#define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5)

Floating Point Unit Inexact Interrupt

Definition at line 399 of file stm32f3xx_hal.h.

#define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3)

Floating Point Unit Overflow Interrupt

Definition at line 397 of file stm32f3xx_hal.h.

#define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2)

Floating Point Unit Underflow Interrupt

Definition at line 396 of file stm32f3xx_hal.h.

#define IS_HAL_SYSCFG_INTERRUPT ( __INTERRUPT__ )
Value:
((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \
                                                (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \
                                                (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \
                                                (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \
                                                (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \
                                                (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5))

Definition at line 401 of file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Freeze/Unfreeze APB1 Peripherals in Debug mode

Defines
Freeze/Unfreeze APB1 Peripherals in Debug mode
HAL Exported Macros

Defines

#define | __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#define | __HAL_FREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP))
#define | __HAL_UNFREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP))
#define | __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
#define | __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
#define | __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#define | __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#define | __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#define | __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#define | __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
#define | __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
#define | __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))

Define Documentation

#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))

Definition at line 490 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))

Definition at line 495 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_FREEZE_IWDG ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))

Definition at line 485 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_FREEZE_RTC ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))

Definition at line 475 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM12 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))

Definition at line 455 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM13 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))

Definition at line 460 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM14 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))

Definition at line 465 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM2 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))

Definition at line 425 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM3 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))

Definition at line 430 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM4 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))

Definition at line 435 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM5 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))

Definition at line 440 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM6 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))

Definition at line 445 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM7 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))

Definition at line 450 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_FREEZE_WWDG ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))

Definition at line 480 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))

Definition at line 491 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))

Definition at line 496 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_IWDG ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))

Definition at line 486 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_RTC ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))

Definition at line 476 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM12 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))

Definition at line 456 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM13 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))

Definition at line 461 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM14 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))

Definition at line 466 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM2 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))

Definition at line 426 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM3 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))

Definition at line 431 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM4 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))

Definition at line 436 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM5 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))

Definition at line 441 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM6 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))

Definition at line 446 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM7 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))

Definition at line 451 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_WWDG ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))

Definition at line 481 of file stm32f3xx_hal.h.

#define __HAL_FREEZE_CAN_DBGMCU ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))

Definition at line 505 of file stm32f3xx_hal.h.

#define __HAL_FREEZE_TIM18_DBGMCU ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP))

Definition at line 470 of file stm32f3xx_hal.h.

#define __HAL_UNFREEZE_CAN_DBGMCU ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))

Definition at line 506 of file stm32f3xx_hal.h.

#define __HAL_UNFREEZE_TIM18_DBGMCU ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP))

Definition at line 471 of file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Freeze/Unfreeze APB2 Peripherals in Debug mode

Defines
Freeze/Unfreeze APB2 Peripherals in Debug mode
HAL Exported Macros

Defines

#define | __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
#define | __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
#define | __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))

Define Documentation

#define __HAL_DBGMCU_FREEZE_TIM15 ( ) (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))

Definition at line 526 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM16 ( ) (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))

Definition at line 531 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM17 ( ) (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))

Definition at line 536 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM15 ( ) (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))

Definition at line 527 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM16 ( ) (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))

Definition at line 532 of file stm32f3xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM17 ( ) (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))

Definition at line 537 of file stm32f3xx_hal.h.

#define __HAL_FREEZE_TIM19_DBGMCU ( ) (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))

Definition at line 541 of file stm32f3xx_hal.h.

#define __HAL_UNFREEZE_TIM19_DBGMCU ( ) (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))

Definition at line 542 of file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Memory Mapping Selection

Defines
Memory Mapping Selection
HAL Exported Macros

Defines

#define | __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
Main Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()
System Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SRAM()
Embedded SRAM mapped at 0x00000000.

Define Documentation

#define __HAL_SYSCFG_REMAPMEMORY_FLASH ( ) (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))

Main Flash memory mapped at 0x00000000.

Definition at line 564 of file stm32f3xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_SRAM ( )
Value:
do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
                                             SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
                                            }while(0U)

Embedded SRAM mapped at 0x00000000.

Definition at line 578 of file stm32f3xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH ( )
Value:
do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
                                             SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0;  \
                                            }while(0U)

System Flash memory mapped at 0x00000000.

Definition at line 570 of file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Encoder Mode

Encoder Mode
HAL Exported Macros
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Remap Enable

Defines
DMA Remap Enable
HAL Exported Macros

Defines

#define | __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__)
DMA remapping enable/disable macros.
#define | __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__)

Define Documentation

#define __HAL_DMA_REMAP_CHANNEL_DISABLE ( __DMA_REMAP__ )
Value:
do {assert_param(IS_DMA_REMAP((__DMA_REMAP__)));                  \
                                                           SYSCFG->CFGR1 &= ~(__DMA_REMAP__);                               \
                                                         }while(0U)

Definition at line 652 of file stm32f3xx_hal.h.

#define __HAL_DMA_REMAP_CHANNEL_ENABLE ( __DMA_REMAP__ )
Value:
do {assert_param(IS_DMA_REMAP((__DMA_REMAP__)));                  \
                                                           SYSCFG->CFGR1 |= (__DMA_REMAP__);                                \
                                                         }while(0U)

DMA remapping enable/disable macros.

Parameters:
__DMA_REMAP__ This parameter can be a value of HAL DMA Remapping

Definition at line 649 of file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Fast-mode Plus on GPIO

Defines
Fast-mode Plus on GPIO
HAL Exported Macros

Defines

#define | __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)
Fast-mode Plus driving capability enable/disable macros.
#define | __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__)

Define Documentation

#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE ( __FASTMODEPLUS__ )
Value:
do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
                                                                CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
                                                               }while(0U)

Definition at line 671 of file stm32f3xx_hal.h.

#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE ( __FASTMODEPLUS__ )
Value:
do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
                                                                SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
                                                               }while(0U)

Fast-mode Plus driving capability enable/disable macros.

Parameters:
__FASTMODEPLUS__ This parameter can be a value of Fast-mode Plus on GPIO values. That you can find above these macros.

Definition at line 667 of file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Floating Point Unit Interrupts Enable

Defines
Floating Point Unit Interrupts Enable
HAL Exported Macros

Defines

#define | __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__)
SYSCFG interrupt enable/disable macros.
#define | __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__)

Define Documentation

#define __HAL_SYSCFG_INTERRUPT_DISABLE ( __INTERRUPT__ )
Value:
do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
                                                                SYSCFG->CFGR1 &= ~(__INTERRUPT__);                      \
                                                               }while(0U)

Definition at line 688 of file stm32f3xx_hal.h.

#define __HAL_SYSCFG_INTERRUPT_ENABLE ( __INTERRUPT__ )
Value:
do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
                                                                SYSCFG->CFGR1 |= (__INTERRUPT__);                       \
                                                               }while(0U)

SYSCFG interrupt enable/disable macros.

Parameters:
__INTERRUPT__ This parameter can be a value of HAL SYSCFG Interrupts

Definition at line 684 of file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: VBAT Monitoring Enable

Defines
VBAT Monitoring Enable
HAL Exported Macros

Defines

#define | __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))
SYSCFG interrupt enable/disable macros.
#define | __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT))

Define Documentation

#define __HAL_SYSCFG_VBAT_MONITORING_DISABLE ( ) (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT))

Definition at line 715 of file stm32f3xx_hal.h.

#define __HAL_SYSCFG_VBAT_MONITORING_ENABLE ( ) (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))

SYSCFG interrupt enable/disable macros.

Definition at line 714 of file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Cortex Lockup Enable

Defines
Cortex Lockup Enable
HAL Exported Macros

Defines

#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()
SYSCFG Break Lockup lock Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input.

Define Documentation

#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK ( )
Value:
do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
                                               SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK;    \
                                              }while(0U)

SYSCFG Break Lockup lock Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input.

Note:
The selected configuration is locked and can be unlocked by system reset

Definition at line 729 of file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PVD Lock

Defines
PVD Lock
HAL Exported Macros

Defines

#define __HAL_SYSCFG_BREAK_PVD_LOCK()
SYSCFG Break PVD lock Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register.

Define Documentation

#define __HAL_SYSCFG_BREAK_PVD_LOCK ( )
Value:
do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
                                               SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK;    \
                                              }while(0U)

SYSCFG Break PVD lock Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register.

Note:
The selected configuration is locked and can be unlocked by system reset

Definition at line 745 of file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SRAM Parity Lock

Defines
SRAM Parity Lock
HAL Exported Macros

Defines

#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK()
SYSCFG Break SRAM PARITY lock Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17.

Define Documentation

#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK ( )
Value:
do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
                                                 SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK;    \
                                                }while(0U)

SYSCFG Break SRAM PARITY lock Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17.

Note:
The selected configuration is locked and can be unlocked by system reset

Definition at line 761 of file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Trigger Remapping Enable

Defines
Trigger Remapping Enable
HAL Exported Macros

Defines

#define | __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__)
Trigger remapping enable/disable macros.
#define | __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__)

Define Documentation

#define __HAL_REMAPTRIGGER_DISABLE ( __TRIGGER_REMAP__ )
Value:
do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__)));             \
                                                           (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__));                          \
                                                         }while(0U)

Definition at line 793 of file stm32f3xx_hal.h.

#define __HAL_REMAPTRIGGER_ENABLE ( __TRIGGER_REMAP__ )
Value:
do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__)));             \
                                                           (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__));                           \
                                                         }while(0U)

Trigger remapping enable/disable macros.

Parameters:
__TRIGGER_REMAP__ This parameter can be a value of HAL Trigger Remapping

Definition at line 790 of file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HAL_Private_Macros

Defines
HAL_Private_Macros
HAL

Defines

#define IS_SYSCFG_FASTMODEPLUS(__PIN__)

Define Documentation

#define IS_SYSCFG_FASTMODEPLUS ( __PIN__ )
Value:
((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6)  == SYSCFG_FASTMODEPLUS_PB6)  || \
                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7)  == SYSCFG_FASTMODEPLUS_PB7)  || \
                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8)  == SYSCFG_FASTMODEPLUS_PB8)  || \
                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9)  == SYSCFG_FASTMODEPLUS_PB9))

Definition at line 60 of file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
ADC Exported Functions

Initialization and Configuration functions. More...

Functions

__weak HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
__weak HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initializes the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitializes the ADC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the ADC.
      (+) De-initialize the ADC.

Function Documentation

HAL_StatusTypeDef HAL_ADC_DeInit ( ADC_HandleTypeDef * hadc )

Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.

Note:
For devices with several ADCs: reset of ADC common registers is done only if all ADCs sharing the same common group are disabled. If this is not the case, reset of these common parameters reset is bypassed without error reporting: it can be the intended behaviour in case of reset of a single ADC while the other ADCs sharing the same common group is still running.
For devices with several ADCs: Global reset of all ADCs sharing a common group is possible. As this function is intended to reset a single ADC, to not impact other ADCs, instructions for global reset of multiple ADCs have been let commented below. If needed, the example code can be copied and uncommented into function HAL_ADC_MspDeInit().
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 451 of file stm32f3xx_hal_adc.c.

HAL_StatusTypeDef HAL_ADC_Init ( ADC_HandleTypeDef * hadc )

Initializes the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".

Note:
As prerequisite, ADC clock must be configured at RCC top level depending on both possible clock sources: PLL clock or AHB clock. See commented example code below that can be copied and uncommented into HAL_ADC_MspInit().
Possibility to update parameters on the fly: This function initializes the ADC MSP (HAL_ADC_MspInit()) only when coming from ADC state reset. Following calls to this function can be used to reconfigure some parameters of ADC_InitTypeDef structure on the fly, without modifying MSP configuration. If ADC MSP has to be modified again, HAL_ADC_DeInit() must be called before HAL_ADC_Init(). The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_InitTypeDef".
This function configures the ADC within 2 scopes: scope of entire ADC and scope of regular group. For parameters details, see comments of structure "ADC_InitTypeDef".
For devices with several ADCs: parameters related to common ADC registers (ADC clock mode) are set only if all ADCs sharing the same common group are disabled. If this is not the case, these common parameters setting are bypassed without error reporting: it can be the intended behaviour in case of update of a parameter of ADC_InitTypeDef on the fly, without disabling the other ADCs sharing the same common group.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 420 of file stm32f3xx_hal_adc.c.

void HAL_ADC_MspDeInit ( ADC_HandleTypeDef * hadc )

DeInitializes the ADC MSP.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 483 of file stm32f3xx_hal_adc.c.

Referenced by HAL_ADC_DeInit().

void HAL_ADC_MspInit ( ADC_HandleTypeDef * hadc )

Initializes the ADC MSP.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 468 of file stm32f3xx_hal_adc.c.

Referenced by HAL_ADC_Init().

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STM32F373xC HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
ADC Exported Functions

IO operation functions. More...

Functions

__weak HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of regular group.
__weak HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC peripheral.
__weak HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
__weak HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for conversion event.
__weak HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of regular group with interruption.
__weak HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interruption of end-of-conversion, disable ADC peripheral.
__weak HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC, starts conversion of regular group and transfers result through DMA.
__weak HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
__weak uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
__weak void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handles ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog callback in non blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non blocking mode (ADC conversion with interruption or transfer by DMA)

Detailed Description

IO operation functions.

 ===============================================================================
             ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of regular group.
      (+) Stop conversion of regular group.
      (+) Poll for conversion complete on regular group.
      (+) Poll for conversion event.
      (+) Get result of regular channel conversion.
      (+) Start conversion of regular group and enable interruptions.
      (+) Stop conversion of regular group and disable interruptions.
      (+) Handle ADC interrupt request
      (+) Start conversion of regular group and enable DMA transfer.
      (+) Stop conversion of regular group and disable ADC DMA transfer.

Function Documentation

void HAL_ADC_ConvCpltCallback ( ADC_HandleTypeDef * hadc )

Conversion complete callback in non blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 756 of file stm32f3xx_hal_adc.c.

Referenced by ADC_DMAConvCplt(), and HAL_ADC_IRQHandler().

void HAL_ADC_ConvHalfCpltCallback ( ADC_HandleTypeDef * hadc )

Conversion DMA half-transfer callback in non blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 771 of file stm32f3xx_hal_adc.c.

Referenced by ADC_DMAHalfConvCplt().

void HAL_ADC_ErrorCallback ( ADC_HandleTypeDef * hadc )

ADC error callback in non blocking mode (ADC conversion with interruption or transfer by DMA)

Parameters:
hadc ADC handle
Return values:
None

Definition at line 802 of file stm32f3xx_hal_adc.c.

Referenced by ADC_DMAError().

uint32_t HAL_ADC_GetValue ( ADC_HandleTypeDef * hadc )

Get ADC regular group conversion result.

Note:
Reading DR register automatically clears EOC (end of conversion of regular group) flag. Additionally, this functions clears EOS (end of sequence of regular group) flag, in case of the end of the sequence is reached.
Parameters:
hadc ADC handle
Return values:
Converted value

Definition at line 728 of file stm32f3xx_hal_adc.c.

References __ADC_HandleTypeDef::Instance.

void HAL_ADC_IRQHandler ( ADC_HandleTypeDef * hadc )

Handles ADC interrupt request.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 742 of file stm32f3xx_hal_adc.c.

void HAL_ADC_LevelOutOfWindowCallback ( ADC_HandleTypeDef * hadc )

Analog watchdog callback in non blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 786 of file stm32f3xx_hal_adc.c.

Referenced by HAL_ADC_IRQHandler().

HAL_StatusTypeDef HAL_ADC_PollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Wait for regular group conversion to be completed.

Parameters:
hadc | ADC handle
Timeout | Timeout value in millisecond.
Return values:
HAL status

Definition at line 570 of file stm32f3xx_hal_adc.c.

HAL_StatusTypeDef HAL_ADC_PollForEvent | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | EventType,
 |  | uint32_t | Timeout
 | ) |  |

Poll for conversion event.

Parameters:
hadc | ADC handle
EventType the ADC event type. This parameter can be one of the following values:
  • ADC_AWD_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
  • ADC_AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, present only on STM32F3 devices)
  • ADC_AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, present only on STM32F3 devices)
  • ADC_OVR_EVENT: ADC Overrun event
  • ADC_JQOVF_EVENT: ADC Injected context queue overflow event
Timeout | Timeout value in millisecond.
Return values:
HAL status

Definition at line 596 of file stm32f3xx_hal_adc.c.

HAL_StatusTypeDef HAL_ADC_Start ( ADC_HandleTypeDef * hadc )

Enables ADC, starts conversion of regular group.

Interruptions enabled in this function: None.

Note:
: Case of multimode enabled (for devices with several ADCs): This function must be called for ADC slave first, then ADC master. For ADC slave, ADC is enabled only (conversion is not started). For ADC master, ADC is enabled and multimode conversion is started.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 529 of file stm32f3xx_hal_adc.c.

HAL_StatusTypeDef HAL_ADC_Start_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enables ADC, starts conversion of regular group and transfers result through DMA.

Interruptions enabled in this function:

  • DMA transfer complete
  • DMA half transfer
  • overrun (if available) Each of these interruptions has its dedicated callback function.
    Note:
    : Case of multimode enabled (for devices with several ADCs): This function is for single-ADC mode only. For multimode, use the dedicated MultimodeStart function.
    Parameters:
    hadc | ADC handle
    pData | The destination Buffer address.
    Length | The length of data to be transferred from ADC peripheral to memory.
    Return values:
    None

Definition at line 680 of file stm32f3xx_hal_adc.c.

HAL_StatusTypeDef HAL_ADC_Start_IT ( ADC_HandleTypeDef * hadc )

Enables ADC, starts conversion of regular group with interruption.

Interruptions enabled in this function:

  • EOC (end of conversion of regular group) or EOS (end of sequence of regular group) depending on ADC initialization parameter "EOCSelection" (if available)
  • overrun (if available) Each of these interruptions has its dedicated callback function.
    Note:
    : Case of multimode enabled (for devices with several ADCs): This function must be called for ADC slave first, then ADC master. For ADC slave, ADC is enabled only (conversion is not started). For ADC master, ADC is enabled and multimode conversion is started.
    Parameters:
    hadc ADC handle
    Return values:
    HAL status

Definition at line 625 of file stm32f3xx_hal_adc.c.

HAL_StatusTypeDef HAL_ADC_Stop ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC peripheral.

Note:
: ADC peripheral disable is forcing stop of potential conversion on injected group. If injected group is under use, it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
: Case of multimode enabled (for devices with several ADCs): This function must be called for ADC master first, then ADC slave. For ADC master, converson is stopped and ADC is disabled. For ADC slave, ADC is disabled only (conversion stop of ADC master has already stopped conversion of ADC slave).
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 552 of file stm32f3xx_hal_adc.c.

HAL_StatusTypeDef HAL_ADC_Stop_DMA ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.

Note:
: ADC peripheral disable is forcing stop of potential conversion on injected group. If injected group is under use, it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
: Case of multimode enabled (for devices with several ADCs): This function is for single-ADC mode only. For multimode, use the dedicated MultimodeStop function.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 707 of file stm32f3xx_hal_adc.c.

HAL_StatusTypeDef HAL_ADC_Stop_IT ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interruption of end-of-conversion, disable ADC peripheral.

Note:
: ADC peripheral disable is forcing stop of potential conversion on injected group. If injected group is under use, it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
: Case of multimode enabled (for devices with several ADCs): This function must be called for ADC master first, then ADC slave. For ADC master, conversion is stopped and ADC is disabled. For ADC slave, ADC is disabled only (conversion stop of ADC master has already stopped conversion of ADC slave).
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 652 of file stm32f3xx_hal_adc.c.

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STM32F373xC HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
ADC Exported Functions

Peripheral Control functions. More...

Functions

__weak HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configures the the selected channel to be linked to the regular group.
__weak HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configures the analog watchdog.

Detailed Description

Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels on regular group
      (+) Configure the analog watchdog

Function Documentation

HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_AnalogWDGConfTypeDef * | AnalogWDGConfig
 | ) |  |

Configures the analog watchdog.

Note:
Possibility to update parameters on the fly: This function initializes the selected analog watchdog, following calls to this function can be used to reconfigure some parameters of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting the ADC. The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_AnalogWDGConfTypeDef".
Parameters:
hadc | ADC handle
AnalogWDGConfig | Structure of ADC analog watchdog configuration
Return values:
HAL status

Definition at line 881 of file stm32f3xx_hal_adc.c.

HAL_StatusTypeDef HAL_ADC_ConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_ChannelConfTypeDef * | sConfig
 | ) |  |

Configures the the selected channel to be linked to the regular group.

Note:
In case of usage of internal measurement channels: Vbat/VrefInt/TempSensor. The recommended sampling time is at least:
  • For devices STM32F37x: 17.1us for temperature sensor
  • For the other STM32F3 devices: 2.2us for each of channels Vbat/VrefInt/TempSensor. These internal paths can be be disabled using function HAL_ADC_DeInit().
Possibility to update parameters on the fly: This function initializes channel into regular group, following calls to this function can be used to reconfigure some parameters of structure "ADC_ChannelConfTypeDef" on the fly, without reseting the ADC. The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_ChannelConfTypeDef".
Parameters:
hadc | ADC handle
sConfig | Structure of ADC channel for regular group.
Return values:
HAL status

Definition at line 854 of file stm32f3xx_hal_adc.c.

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STM32F373xC HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
ADC Exported Functions

ADC Peripheral State functions. More...

Functions

uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
return the ADC state
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.

Detailed Description

ADC Peripheral State functions.

 ===============================================================================
            ##### Peripheral state and errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions to get in run-time the status of the
    peripheral.
      (+) Check the ADC state
      (+) Check the ADC error code

Function Documentation

uint32_t HAL_ADC_GetError ( ADC_HandleTypeDef * hadc )

Return the ADC error code.

Parameters:
hadc ADC handle
Return values:
ADC Error Code

Definition at line 939 of file stm32f3xx_hal_adc.c.

References __ADC_HandleTypeDef::ErrorCode.

uint32_t HAL_ADC_GetState ( ADC_HandleTypeDef * hadc )

return the ADC state

Note:
ADC state machine is managed by bitfield, state must be compared with bit by bit. For example: " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
Parameters:
hadc ADC handle
Return values:
HAL state

Definition at line 925 of file stm32f3xx_hal_adc.c.

References assert_param, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Exported Types

Data Structures | Defines | Typedefs
ADC Exported Types
ADC

Data Structures

struct | __ADC_HandleTypeDef
ADC handle Structure definition. More...

Defines

#define | HAL_ADC_STATE_RESET (0x00000000U)
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY (0x00000001U)
#define | HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U)
#define | HAL_ADC_STATE_TIMEOUT (0x00000004U)
#define | HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U)
#define | HAL_ADC_STATE_ERROR_CONFIG (0x00000020U)
#define | HAL_ADC_STATE_ERROR_DMA (0x00000040U)
#define | HAL_ADC_STATE_REG_BUSY (0x00000100U)
#define | HAL_ADC_STATE_REG_EOC (0x00000200U)
#define | HAL_ADC_STATE_REG_OVR (0x00000400U)
#define | HAL_ADC_STATE_REG_EOSMP (0x00000800U)
#define | HAL_ADC_STATE_INJ_BUSY (0x00001000U)
#define | HAL_ADC_STATE_INJ_EOC (0x00002000U)
#define | HAL_ADC_STATE_INJ_JQOVF (0x00004000U)
#define | HAL_ADC_STATE_AWD1 (0x00010000U)
#define | HAL_ADC_STATE_AWD2 (0x00020000U)
#define | HAL_ADC_STATE_AWD3 (0x00040000U)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U)

Typedefs

typedef struct __ADC_HandleTypeDef | ADC_HandleTypeDef
ADC handle Structure definition.

Define Documentation

#define HAL_ADC_STATE_AWD1 (0x00010000U)

Out-of-window occurrence of analog watchdog 1

Definition at line 96 of file stm32f3xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_AWD2 (0x00020000U)

Out-of-window occurrence of analog watchdog 2

Definition at line 97 of file stm32f3xx_hal_adc.h.

#define HAL_ADC_STATE_AWD3 (0x00040000U)

Out-of-window occurrence of analog watchdog 3

Definition at line 98 of file stm32f3xx_hal_adc.h.

#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U)

ADC is busy to internal process (initialization, calibration)

Definition at line 74 of file stm32f3xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), and HAL_ADCEx_Calibration_Start().

#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U)

Configuration error occurrence

Definition at line 79 of file stm32f3xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_PollForConversion(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedStop(), and HAL_ADCEx_InjectedStop_IT().

#define HAL_ADC_STATE_ERROR_DMA (0x00000040U)

DMA error occurrence

Definition at line 80 of file stm32f3xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), and HAL_ADC_Stop_DMA().

#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U)

Internal error occurrence

Definition at line 78 of file stm32f3xx_hal_adc.h.

Referenced by ADC_ConversionStop_Disable(), ADC_DMAConvCplt(), ADC_Enable(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADCEx_Calibration_Start().

#define HAL_ADC_STATE_INJ_BUSY (0x00001000U)

A conversion on group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on, multimode ADC master control)

Definition at line 90 of file stm32f3xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), and HAL_ADCEx_InjectedStop_IT().

#define HAL_ADC_STATE_INJ_EOC (0x00002000U)

Conversion data available on group injected

Definition at line 92 of file stm32f3xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define HAL_ADC_STATE_INJ_JQOVF (0x00004000U)

Injected queue overflow occurrence

Definition at line 93 of file stm32f3xx_hal_adc.h.

#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U)

ADC in multimode slave state, controlled by another ADC master (

Definition at line 101 of file stm32f3xx_hal_adc.h.

#define HAL_ADC_STATE_READY (0x00000001U)

ADC peripheral ready for use

Definition at line 73 of file stm32f3xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), and HAL_ADCEx_InjectedStop_IT().

#define HAL_ADC_STATE_REG_BUSY (0x00000100U)

A conversion on group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on, multimode ADC master control)

Definition at line 83 of file stm32f3xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), and HAL_ADCEx_InjectedStop_IT().

#define HAL_ADC_STATE_REG_EOC (0x00000200U)

Conversion data available on group regular

Definition at line 85 of file stm32f3xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define HAL_ADC_STATE_REG_EOSMP (0x00000800U)

End Of Sampling flag raised

Definition at line 87 of file stm32f3xx_hal_adc.h.

#define HAL_ADC_STATE_REG_OVR (0x00000400U)

Overrun occurrence

Definition at line 86 of file stm32f3xx_hal_adc.h.

#define HAL_ADC_STATE_RESET (0x00000000U)

HAL ADC state machine: ADC states definition (bitfields)

Note:
ADC state machine is managed by bitfields, state must be compared with bit by bit. For example: " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " ADC not yet initialized or disabled

Definition at line 72 of file stm32f3xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_Init().

#define HAL_ADC_STATE_TIMEOUT (0x00000004U)

TimeOut occurrence

Definition at line 75 of file stm32f3xx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), and HAL_ADCEx_InjectedPollForConversion().

Typedef Documentation

typedef struct __ADC_HandleTypeDef ADC_HandleTypeDef

ADC handle Structure definition.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: __ADC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__ADC_HandleTypeDef Struct Reference
ADC Exported Types

ADC handle Structure definition. More...

#include <stm32f3xx_hal_adc.h>

Data Fields

ADC_TypeDef * | Instance
ADC_InitTypeDef Init
DMA_HandleTypeDef * DMA_Handle
HAL_LockTypeDef | Lock
__IO uint32_t | State
__IO uint32_t | ErrorCode

Detailed Description

ADC handle Structure definition.

Definition at line 107 of file stm32f3xx_hal_adc.h.

Field Documentation

DMA_HandleTypeDef* __ADC_HandleTypeDef::DMA_Handle

Pointer DMA Handler

Definition at line 113 of file stm32f3xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Start_DMA(), and HAL_ADC_Stop_DMA().

__IO uint32_t __ADC_HandleTypeDef::ErrorCode

ADC Error code

Definition at line 119 of file stm32f3xx_hal_adc.h.

Referenced by ADC_ConversionStop_Disable(), ADC_DMAError(), ADC_Enable(), HAL_ADC_GetError(), HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

ADC_InitTypeDef __ADC_HandleTypeDef::Init

ADC required parameters

Definition at line 111 of file stm32f3xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_InjectedPollForConversion().

ADC_TypeDef* __ADC_HandleTypeDef::Instance

Register base address

Definition at line 109 of file stm32f3xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetState(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), and HAL_ADCEx_InjectedStop_IT().

HAL_LockTypeDef __ADC_HandleTypeDef::Lock

ADC locking object

Definition at line 115 of file stm32f3xx_hal_adc.h.

Referenced by HAL_ADC_Init().

__IO uint32_t __ADC_HandleTypeDef::State

ADC communication state (bitmap of ADC states)

Definition at line 117 of file stm32f3xx_hal_adc.h.

Referenced by ADC_ConversionStop_Disable(), ADC_DMAConvCplt(), ADC_DMAError(), ADC_Enable(), HAL_ADC_DeInit(), HAL_ADC_GetState(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), and HAL_ADCEx_InjectedStop_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_adc.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Exported Macros

Defines
ADC Exported Macros
ADC

Defines

#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
Reset ADC handle state.

Define Documentation

#define __HAL_ADC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)

Reset ADC handle state.

Parameters:
__HANDLE__ ADC handle
Return values:
None

Definition at line 146 of file stm32f3xx_hal_adc.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Extended Internal HAL driver trigger selection for regular group

Defines
ADC Extended Internal HAL driver trigger selection for regular group
ADCEx Private Constants

Defines

#define | ADC_EXTERNALTRIG_T19_TRGO (0x00000000U)
#define | ADC_EXTERNALTRIG_T19_CC3 ((uint32_t)ADC_CR2_EXTSEL_0)
#define | ADC_EXTERNALTRIG_T19_CC4 ((uint32_t)ADC_CR2_EXTSEL_1)
#define | ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)
#define | ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
#define | ADC_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))

Define Documentation

#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))

Definition at line 1825 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIG_T19_CC3 ((uint32_t)ADC_CR2_EXTSEL_0)

Definition at line 1820 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIG_T19_CC4 ((uint32_t)ADC_CR2_EXTSEL_1)

Definition at line 1821 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIG_T19_TRGO (0x00000000U)

Definition at line 1819 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))

Definition at line 1822 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)

Definition at line 1823 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))

Definition at line 1824 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))

Definition at line 1826 of file stm32f3xx_hal_adc_ex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Extended Internal HAL driver trigger selection for injected group

Defines
ADC Extended Internal HAL driver trigger selection for injected group
ADCEx Private Constants

Defines

#define | ADC_EXTERNALTRIGINJEC_T19_CC1 ( 0x00000000U)
#define | ADC_EXTERNALTRIGINJEC_T19_CC2 ((uint32_t) ADC_CR2_JEXTSEL_0)
#define | ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t) ADC_CR2_JEXTSEL_1)
#define | ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t) ADC_CR2_JEXTSEL_2)
#define | ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
#define | ADC_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))

Define Documentation

#define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))

Definition at line 1844 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T19_CC1 ( 0x00000000U)

Definition at line 1838 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T19_CC2 ((uint32_t) ADC_CR2_JEXTSEL_0)

Definition at line 1839 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))

Definition at line 1841 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t) ADC_CR2_JEXTSEL_1)

Definition at line 1840 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t) ADC_CR2_JEXTSEL_2)

Definition at line 1842 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))

Definition at line 1843 of file stm32f3xx_hal_adc_ex.h.

#define ADC_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))

Definition at line 1845 of file stm32f3xx_hal_adc_ex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Extended Sampling Times All Channels

Defines
ADC Extended Sampling Times All Channels
ADCEx Private Constants

Defines

#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0
#define | ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS (0x00000000U)
#define | ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define | ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
#define | ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define | ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
#define | ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define | ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
#define | ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define | ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS (0x00000000U)
#define | ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define | ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
#define | ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define | ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
#define | ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define | ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
#define | ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define | ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )

Define Documentation

#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )

Definition at line 1896 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)

Definition at line 1888 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)

Definition at line 1879 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS (0x00000000U)

Definition at line 1886 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS (0x00000000U)

Definition at line 1877 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)

Definition at line 1893 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)

Definition at line 1884 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)

Definition at line 1889 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)

Definition at line 1880 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)

Definition at line 1890 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)

Definition at line 1881 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)

Definition at line 1891 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)

Definition at line 1882 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)

Definition at line 1892 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)

Definition at line 1883 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)

Definition at line 1887 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)

Definition at line 1878 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0
Value:
(ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
      ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )

Definition at line 1873 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1
Value:
(ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \
      ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )

Definition at line 1865 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2
Value:
(ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \
      ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )

Definition at line 1857 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0
Value:
(ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 |     \
      ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 |     \
      ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)

Definition at line 1869 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1
Value:
(ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 |     \
      ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 |     \
      ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)

Definition at line 1861 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2
Value:
(ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 |     \
      ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 |     \
      ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)

Definition at line 1853 of file stm32f3xx_hal_adc_ex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADCEx Private Constants

Modules | Defines
ADCEx Private Constants
ADCEx

Modules

ADC Extended Internal HAL driver trigger selection for regular group
ADC Extended Internal HAL driver trigger selection for injected group
ADC Extended Sampling Times All Channels

Defines

#define | ADC_ENABLE_TIMEOUT ( 2U)
#define | ADC_DISABLE_TIMEOUT ( 2U)
#define | ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ( 2U)
#define | ADC_CALIBRATION_TIMEOUT ( 10U)
#define | ADC_STAB_DELAY_US ( 1U)
#define | ADC_TEMPSENSOR_DELAY_US ( 10U)
#define | ADC_CYCLE_WORST_CASE_CPU_CYCLES ( 128U)
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ( 14U)
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ( 20U)
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ( 26U)
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ( 41U)
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ( 54U)
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ( 68U)
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ( 84U)
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 (252U)

Define Documentation

#define ADC_CALIBRATION_TIMEOUT ( 10U)

Definition at line 135 of file stm32f3xx_hal_adc_ex.c.

Referenced by HAL_ADCEx_Calibration_Start().

#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ( 26U)

Definition at line 160 of file stm32f3xx_hal_adc_ex.c.

#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ( 14U)

Definition at line 158 of file stm32f3xx_hal_adc_ex.c.

#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 (252U)

Definition at line 165 of file stm32f3xx_hal_adc_ex.c.

#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ( 41U)

Definition at line 161 of file stm32f3xx_hal_adc_ex.c.

#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ( 54U)

Definition at line 162 of file stm32f3xx_hal_adc_ex.c.

#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ( 68U)

Definition at line 163 of file stm32f3xx_hal_adc_ex.c.

#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ( 84U)

Definition at line 164 of file stm32f3xx_hal_adc_ex.c.

#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ( 20U)

Definition at line 159 of file stm32f3xx_hal_adc_ex.c.

#define ADC_CYCLE_WORST_CASE_CPU_CYCLES ( 128U)

Definition at line 153 of file stm32f3xx_hal_adc_ex.c.

Referenced by HAL_ADCEx_Calibration_Start().

#define ADC_DISABLE_TIMEOUT ( 2U)

Definition at line 121 of file stm32f3xx_hal_adc_ex.c.

Referenced by ADC_ConversionStop_Disable().

#define ADC_ENABLE_TIMEOUT ( 2U)

Definition at line 120 of file stm32f3xx_hal_adc_ex.c.

Referenced by ADC_Enable().

#define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ( 2U)

Definition at line 127 of file stm32f3xx_hal_adc_ex.c.

#define ADC_STAB_DELAY_US ( 1U)

Definition at line 140 of file stm32f3xx_hal_adc_ex.c.

Referenced by ADC_Enable().

#define ADC_TEMPSENSOR_DELAY_US ( 10U)

Definition at line 145 of file stm32f3xx_hal_adc_ex.c.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADCEx Initialization and de-initialization functions

Functions
ADCEx Initialization and de-initialization functions
ADCEx Exported Functions

ADC Extended Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to its default reset values.

Detailed Description

ADC Extended Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the ADC.
      (+) De-initialize the ADC.

Function Documentation

HAL_StatusTypeDef HAL_ADC_DeInit ( ADC_HandleTypeDef * hadc )

Deinitialize the ADC peripheral registers to its default reset values.

Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 1014 of file stm32f3xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CLEAR_ERRORCODE, ADC_ConversionStop_Disable(), ADC_FLAG_AWD, ADC_FLAG_EOC, ADC_FLAG_JEOC, ADC_FLAG_JSTRT, ADC_FLAG_STRT, assert_param, HAL_ADC_MspDeInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_RESET, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Init ( ADC_HandleTypeDef * hadc )

Initializes the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".

Note:
As prerequisite, ADC clock must be configured at RCC top level (clock source APB2). See commented example code below that can be copied and uncommented into HAL_ADC_MspInit().
Possibility to update parameters on the fly: This function initializes the ADC MSP (HAL_ADC_MspInit()) only when coming from ADC state reset. Following calls to this function can be used to reconfigure some parameters of ADC_InitTypeDef structure on the fly, without modifying MSP configuration. If ADC MSP has to be modified again, HAL_ADC_DeInit() must be called before HAL_ADC_Init(). The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_InitTypeDef".
This function configures the ADC within 2 scopes: scope of entire ADC and scope of regular group. For parameters details, see comments of structure "ADC_InitTypeDef".
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 571 of file stm32f3xx_hal_adc_ex.c.

References ADC_CLEAR_ERRORCODE, ADC_ConversionStop_Disable(), ADC_CR1_DISCONTINUOUS_NUM, ADC_CR1_SCAN_SET, ADC_CR2_CONTINUOUS, ADC_SCAN_DISABLE, ADC_SCAN_ENABLE, ADC_SQR1_L_SHIFT, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_InitTypeDef::DataAlign, ADC_InitTypeDef::DiscontinuousConvMode, __ADC_HandleTypeDef::ErrorCode, ADC_InitTypeDef::ExternalTrigConv, HAL_ADC_ERROR_INTERNAL, HAL_ADC_MspInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_RESET, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_DATA_ALIGN, IS_ADC_EXTTRIG, IS_ADC_REGULAR_DISCONT_NUMBER, IS_ADC_REGULAR_NB_CONV, IS_ADC_SCAN_MODE, __ADC_HandleTypeDef::Lock, ADC_InitTypeDef::NbrOfConversion, ADC_InitTypeDef::NbrOfDiscConversion, ADC_InitTypeDef::ScanConvMode, and __ADC_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADCEx Input and Output operation functions

Functions
ADCEx Input and Output operation functions
ADCEx Exported Functions

ADC Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for conversion event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC, starts conversion of regular group and transfers result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handles ADC interrupt request.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop (struct __ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_IT (struct __ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_DMA (struct __ADC_HandleTypeDef *hadc)

Detailed Description

ADC Extended IO operation functions.

 ===============================================================================
             ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of regular group.
      (+) Stop conversion of regular group.
      (+) Poll for conversion complete on regular group.
      (+) Poll for conversion event.
      (+) Get result of regular channel conversion.
      (+) Start conversion of regular group and enable interruptions.
      (+) Stop conversion of regular group and disable interruptions.
      (+) Handle ADC interrupt request
      (+) Start conversion of regular group and enable DMA transfer.
      (+) Stop conversion of regular group and disable ADC DMA transfer.

      (+) Start conversion of injected group.
      (+) Stop conversion of injected group.
      (+) Poll for conversion complete on injected group.
      (+) Get result of injected channel conversion.
      (+) Start conversion of injected group and enable interruptions.
      (+) Stop conversion of injected group and disable interruptions.

      (+) Start multimode and enable DMA transfer.
      (+) Stop multimode and disable ADC DMA transfer.
      (+) Get result of multimode conversion.

      (+) Perform the ADC self-calibration for single or differential ending.
      (+) Get calibration factors for single or differential ending.
      (+) Set calibration factors for single or differential ending.

Function Documentation

uint32_t HAL_ADC_GetValue ( ADC_HandleTypeDef * hadc )

Get ADC regular group conversion result.

Note:
Reading register DR automatically clears ADC flag EOC (ADC group regular end of unitary conversion).
This function does not clear ADC flag EOS (ADC group regular end of sequence conversion). Occurrence of flag EOS rising:
  • If sequencer is composed of 1 rank, flag EOS is equivalent to flag EOC.
  • If sequencer is composed of several ranks, during the scan sequence flag EOC only is raised, at the end of the scan sequence both flags EOC and EOS are raised. To clear this flag, either use function: in programming model IT: HAL_ADC_IRQHandler(), in programming model polling: HAL_ADC_PollForConversion() or __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
Parameters:
hadc ADC handle
Return values:
ADC group regular conversion data

Definition at line 2796 of file stm32f3xx_hal_adc_ex.c.

References assert_param, and __ADC_HandleTypeDef::Instance.

void HAL_ADC_IRQHandler ( ADC_HandleTypeDef * hadc )

Handles ADC interrupt request.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 3118 of file stm32f3xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_GET_FLAG, __HAL_ADC_GET_IT_SOURCE, ADC_FLAG_AWD, ADC_FLAG_EOC, ADC_FLAG_JEOC, ADC_FLAG_JSTRT, ADC_FLAG_STRT, ADC_IS_SOFTWARE_START_INJECTED, ADC_IS_SOFTWARE_START_REGULAR, ADC_IT_AWD, ADC_IT_EOC, ADC_IT_JEOC, assert_param, ADC_InitTypeDef::ContinuousConvMode, HAL_ADC_ConvCpltCallback(), HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_STATE_AWD1, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADCEx_InjectedConvCpltCallback(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_REGULAR_NB_CONV, ADC_InitTypeDef::NbrOfConversion, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_PollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Wait for regular group conversion to be completed.

Note:
This function cannot be used in a particular setup: ADC configured in DMA mode. In this case, DMA resets the flag EOC and polling cannot be performed on each conversion.
On STM32F37x devices, limitation in case of sequencer enabled (several ranks selected): polling cannot be done on each conversion inside the sequence. In this case, polling is replaced by wait for maximum conversion time.
Parameters:
hadc | ADC handle
Timeout | Timeout value in millisecond.
Return values:
HAL status

Definition at line 1679 of file stm32f3xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CLOCK_PRESCALER_RANGE, ADC_CONVCYCLES_MAX_RANGE, ADC_FLAG_EOC, ADC_FLAG_STRT, ADC_IS_SOFTWARE_START_REGULAR, assert_param, ADC_InitTypeDef::ContinuousConvMode, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_PollForEvent | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | EventType,
 |  | uint32_t | Timeout
 | ) |  |

Poll for conversion event.

Parameters:
hadc | ADC handle
EventType the ADC event type. This parameter can be one of the following values:
  • ADC_AWD_EVENT: ADC Analog watchdog event.
Timeout | Timeout value in millisecond.
Return values:
HAL status

Definition at line 1936 of file stm32f3xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_FLAG_AWD, assert_param, HAL_ADC_STATE_AWD1, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), __ADC_HandleTypeDef::Instance, IS_ADC_EVENT_TYPE, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start ( ADC_HandleTypeDef * hadc )

Enables ADC, starts conversion of regular group.

Interruptions enabled in this function: None.

Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 1318 of file stm32f3xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_EOC, ADC_IS_SOFTWARE_START_REGULAR, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enables ADC, starts conversion of regular group and transfers result through DMA.

Interruptions enabled in this function:

  • DMA transfer complete
  • DMA half transfer Each of these interruptions has its dedicated callback function.
    Note:
    For devices with several ADCs: This function is for single-ADC mode only. For multimode, use the dedicated MultimodeStart function.
    Parameters:
    hadc | ADC handle
    pData | The destination Buffer address.
    Length | The length of data to be transferred from ADC peripheral to memory.
    Return values:
    None

Definition at line 2492 of file stm32f3xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CLEAR_ERRORCODE, ADC_DMAConvCplt(), ADC_DMAError(), ADC_DMAHalfConvCplt(), ADC_Enable(), ADC_FLAG_EOC, ADC_IS_SOFTWARE_START_REGULAR, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::DMA_Handle, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_DMA_Start_IT(), __ADC_HandleTypeDef::Instance, __ADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_ADC_Start_IT ( ADC_HandleTypeDef * hadc )

Enables ADC, starts conversion of regular group with interruption.

Interruptions enabled in this function:

  • EOC (end of conversion of regular group) Each of these interruptions has its dedicated callback function.
    Parameters:
    hadc ADC handle
    Return values:
    HAL status

Definition at line 2136 of file stm32f3xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_EOC, ADC_IS_SOFTWARE_START_REGULAR, ADC_IT_EOC, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.

Note:
ADC peripheral disable is forcing interruption of potential conversion on injected group. If injected group is under use, it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 1460 of file stm32f3xx_hal_adc_ex.c.

References ADC_ConversionStop_Disable(), ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_DMA ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.

Note:
ADC peripheral disable is forcing interruption of potential conversion on injected group. If injected group is under use, it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
For devices with several ADCs: This function is for single-ADC mode only. For multimode, use the dedicated MultimodeStop function.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 2690 of file stm32f3xx_hal_adc_ex.c.

References ADC_ConversionStop_Disable(), ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_IT ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 2285 of file stm32f3xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop_Disable(), ADC_IT_EOC, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_Calibration_Start ( ADC_HandleTypeDef * hadc )

Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).

During calibration process, ADC is enabled. ADC is let enabled at the completion of this function.

Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 3324 of file stm32f3xx_hal_adc_ex.c.

References ADC_CALIBRATION_TIMEOUT, ADC_ConversionStop_Disable(), ADC_CYCLE_WORST_CASE_CPU_CYCLES, ADC_Enable(), ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_GetTick(), __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

void HAL_ADCEx_InjectedConvCpltCallback ( ADC_HandleTypeDef * hadc )

Injected conversion complete callback in non blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 5308 of file stm32f3xx_hal_adc_ex.c.

Referenced by HAL_ADC_IRQHandler().

uint32_t HAL_ADCEx_InjectedGetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | InjectedRank
 | ) |  |

Get ADC injected group conversion result.

Note:
Reading register JDRx automatically clears ADC flag JEOC (ADC group injected end of unitary conversion).
This function does not clear ADC flag JEOS (ADC group injected end of sequence conversion) Occurrence of flag JEOS rising:
  • If sequencer is composed of 1 rank, flag JEOS is equivalent to flag JEOC.
  • If sequencer is composed of several ranks, during the scan sequence flag JEOC only is raised, at the end of the scan sequence both flags JEOC and EOS are raised. Flag JEOS must not be cleared by this function because it would not be compliant with low power features (feature low power auto-wait, not available on all STM32 families). To clear this flag, either use function: in programming model IT: HAL_ADC_IRQHandler(), in programming model polling: HAL_ADCEx_InjectedPollForConversion() or __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
Parameters:
hadc ADC handle
InjectedRank the converted ADC injected rank. This parameter can be one of the following values:
  • ADC_INJECTED_RANK_1: Injected Channel1 selected
  • ADC_INJECTED_RANK_2: Injected Channel2 selected
  • ADC_INJECTED_RANK_3: Injected Channel3 selected
  • ADC_INJECTED_RANK_4: Injected Channel4 selected
Return values:
ADC group injected conversion data

Definition at line 4849 of file stm32f3xx_hal_adc_ex.c.

References ADC_INJECTED_RANK_1, ADC_INJECTED_RANK_2, ADC_INJECTED_RANK_3, ADC_INJECTED_RANK_4, assert_param, __ADC_HandleTypeDef::Instance, and IS_ADC_INJECTED_RANK.

HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Wait for injected group conversion to be completed.

Parameters:
hadc | ADC handle
Timeout | Timeout value in millisecond.
Return values:
HAL status

Definition at line 3964 of file stm32f3xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CLOCK_PRESCALER_RANGE, ADC_CONVCYCLES_MAX_RANGE, ADC_FLAG_EOC, ADC_FLAG_JEOC, ADC_FLAG_JSTRT, ADC_IS_SOFTWARE_START_INJECTED, ADC_IS_SOFTWARE_START_REGULAR, assert_param, ADC_InitTypeDef::ContinuousConvMode, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStart ( ADC_HandleTypeDef * hadc )

Enables ADC, starts conversion of injected group.

Interruptions enabled in this function: None.

Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 3631 of file stm32f3xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_JEOC, ADC_IS_SOFTWARE_START_INJECTED, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT ( ADC_HandleTypeDef * hadc )

Enables ADC, starts conversion of injected group with interruption.

Interruptions enabled in this function:

  • JEOC (end of conversion of injected group) Each of these interruptions has its dedicated callback function.
    Parameters:
    hadc ADC handle
    Return values:
    HAL status.

Definition at line 4212 of file stm32f3xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_JEOC, ADC_IS_SOFTWARE_START_INJECTED, ADC_IT_JEOC, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels.

Disable ADC peripheral if no regular conversion is on going.

Note:
If ADC must be disabled and if conversion is on going on regular group, function HAL_ADC_Stop must be used to stop both injected and regular groups, and disable the ADC.
In case of auto-injection mode, HAL_ADC_Stop must be used.
Parameters:
hadc ADC handle
Return values:
None

Definition at line 3807 of file stm32f3xx_hal_adc_ex.c.

References ADC_ConversionStop_Disable(), ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels, disable interruption of end-of-conversion.

Disable ADC peripheral if no regular conversion is on going.

Note:
If ADC must be disabled and if conversion is on going on regular group, function HAL_ADC_Stop must be used to stop both injected and regular groups, and disable the ADC.
Parameters:
hadc ADC handle
Return values:
None

Definition at line 4400 of file stm32f3xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop_Disable(), ADC_IT_JEOC, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularStop ( struct __ADC_HandleTypeDef * hadc )
HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA ( struct __ADC_HandleTypeDef * hadc )
HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT ( struct __ADC_HandleTypeDef * hadc )
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADCEx Peripheral Control functions

Functions
ADCEx Peripheral Control functions
ADCEx Exported Functions

ADC Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configures the the selected channel to be linked to the regular group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configures the ADC injected group and the selected channel to be linked to the injected group.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configures the analog watchdog.

Detailed Description

ADC Extended Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels on regular group
      (+) Configure channels on injected group
      (+) Configure multimode
      (+) Configure the analog watchdog

Function Documentation

HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_AnalogWDGConfTypeDef * | AnalogWDGConfig
 | ) |  |

Configures the analog watchdog.

Note:
Analog watchdog thresholds can be modified while ADC conversion is on going. In this case, some constraints must be taken into account: the programmed threshold values are effective from the next ADC EOC (end of unitary conversion). Considering that registers write delay may happen due to bus activity, this might cause an uncertainty on the effective timing of the new programmed threshold values.
Parameters:
hadc | ADC handle
AnalogWDGConfig | Structure of ADC analog watchdog configuration
Return values:
HAL status

Definition at line 6848 of file stm32f3xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, __HAL_ADC_ENABLE_IT, ADC_ANALOGWATCHDOG_SINGLE_INJEC, ADC_ANALOGWATCHDOG_SINGLE_REG, ADC_ANALOGWATCHDOG_SINGLE_REGINJEC, ADC_IT_AWD, assert_param, ADC_AnalogWDGConfTypeDef::Channel, ADC_AnalogWDGConfTypeDef::HighThreshold, __ADC_HandleTypeDef::Instance, IS_ADC_ANALOG_WATCHDOG_MODE, IS_ADC_CHANNEL, IS_ADC_RANGE, ADC_AnalogWDGConfTypeDef::ITMode, ADC_AnalogWDGConfTypeDef::LowThreshold, and ADC_AnalogWDGConfTypeDef::WatchdogMode.

HAL_StatusTypeDef HAL_ADC_ConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_ChannelConfTypeDef * | sConfig
 | ) |  |

Configures the the selected channel to be linked to the regular group.

Note:
In case of usage of internal measurement channels: Vbat/VrefInt/TempSensor. The recommended sampling time is at least:
  • For devices STM32F37x: 17.1us for temperature sensor
  • For the other STM32F3 devices: 2.2us for each of channels Vbat/VrefInt/TempSensor. These internal paths can be be disabled using function HAL_ADC_DeInit().
Possibility to update parameters on the fly: This function initializes channel into regular group, following calls to this function can be used to reconfigure some parameters of structure "ADC_ChannelConfTypeDef" on the fly, without reseting the ADC. The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_ChannelConfTypeDef".
Parameters:
hadc | ADC handle
sConfig | Structure of ADC channel for regular group.
Return values:
HAL status

Definition at line 5759 of file stm32f3xx_hal_adc_ex.c.

References ADC_CHANNEL_10, ADC_CHANNEL_TEMPSENSOR, ADC_CHANNEL_VBAT, ADC_CHANNEL_VREFINT, ADC_SMPR1, ADC_SMPR2, ADC_SQR1_RK, ADC_SQR2_RK, ADC_SQR3_RK, ADC_TEMPSENSOR_DELAY_US, assert_param, ADC_ChannelConfTypeDef::Channel, __ADC_HandleTypeDef::Instance, IS_ADC_CHANNEL, IS_ADC_REGULAR_RANK, IS_ADC_SAMPLE_TIME, ADC_ChannelConfTypeDef::Rank, and ADC_ChannelConfTypeDef::SamplingTime.

HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_InjectionConfTypeDef * | sConfigInjected
 | ) |  |

Configures the ADC injected group and the selected channel to be linked to the injected group.

Note:
Possibility to update parameters on the fly: This function initializes injected group, following calls to this function can be used to reconfigure some parameters of structure "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC. The setting of these parameters is conditioned to ADC state: this function must be called when ADC is not under conversion.
In case of usage of internal measurement channels: Vbat/VrefInt/TempSensor. The recommended sampling time is at least:
  • For devices STM32F37x: 17.1us for temperature sensor
  • For the other STM32F3 devices: 2.2us for each of channels Vbat/VrefInt/TempSensor. These internal paths can be be disabled using function HAL_ADC_DeInit().
Parameters:
hadc | ADC handle
sConfigInjected | Structure of ADC injected group and ADC channel for injected group.
Return values:
None

Definition at line 6397 of file stm32f3xx_hal_adc_ex.c.

References ADC_CHANNEL_10, ADC_CHANNEL_TEMPSENSOR, ADC_CHANNEL_VBAT, ADC_CHANNEL_VREFINT, ADC_INJECTED_RANK_1, ADC_INJECTED_SOFTWARE_START, ADC_IS_ENABLE, ADC_JSQR_JL_SHIFT, ADC_JSQR_RK_JL, ADC_SCAN_DISABLE, ADC_SMPR1, ADC_SMPR2, ADC_TEMPSENSOR_DELAY_US, assert_param, ADC_InjectionConfTypeDef::AutoInjectedConv, ADC_InjectionConfTypeDef::ExternalTrigInjecConv, HAL_ADC_STATE_ERROR_CONFIG, __ADC_HandleTypeDef::Init, ADC_InjectionConfTypeDef::InjectedChannel, ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode, ADC_InjectionConfTypeDef::InjectedNbrOfConversion, ADC_InjectionConfTypeDef::InjectedOffset, ADC_InjectionConfTypeDef::InjectedRank, ADC_InjectionConfTypeDef::InjectedSamplingTime, __ADC_HandleTypeDef::Instance, IS_ADC_CHANNEL, IS_ADC_EXTTRIGINJEC, IS_ADC_INJECTED_NB_CONV, IS_ADC_INJECTED_RANK, IS_ADC_RANGE, IS_ADC_SAMPLE_TIME, ADC_InitTypeDef::ScanConvMode, and __ADC_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADCEx Private Functions

Functions
ADCEx Private Functions
ADCEx

Functions

static void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
static void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
static void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
static HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
static HAL_StatusTypeDef | ADC_ConversionStop_Disable (ADC_HandleTypeDef *hadc)
Stop ADC conversion and disable the selected ADC.

Function Documentation

static HAL_StatusTypeDef ADC_ConversionStop_Disable ( ADC_HandleTypeDef * hadc ) [static]

Stop ADC conversion and disable the selected ADC.

Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 7428 of file stm32f3xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE, ADC_DISABLE_TIMEOUT, ADC_IS_ENABLE, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedStop(), and HAL_ADCEx_InjectedStop_IT().

static void ADC_DMAConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA transfer complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 7058 of file stm32f3xx_hal_adc_ex.c.

References ADC_IS_SOFTWARE_START_REGULAR, ADC_InitTypeDef::ContinuousConvMode, __ADC_HandleTypeDef::DMA_Handle, HAL_ADC_ConvCpltCallback(), HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::State, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_ADC_Start_DMA().

static void ADC_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 7115 of file stm32f3xx_hal_adc_ex.c.

References __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_DMA, and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start_DMA().

static void ADC_DMAHalfConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 7101 of file stm32f3xx_hal_adc_ex.c.

References HAL_ADC_ConvHalfCpltCallback().

Referenced by HAL_ADC_Start_DMA().

static HAL_StatusTypeDef ADC_Enable ( ADC_HandleTypeDef * hadc ) [static]

Enable the selected ADC.

Note:
Prerequisite condition to use this function: ADC must be disabled and voltage regulator must be enabled (done into HAL_ADC_Init()).
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 7375 of file stm32f3xx_hal_adc_ex.c.

References __HAL_ADC_ENABLE, ADC_ENABLE_TIMEOUT, ADC_IS_ENABLE, ADC_STAB_DELAY_US, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InitTypeDef Struct Reference
ADCEx Exported Types

Structure definition of ADC and regular group initialization. More...

#include <stm32f3xx_hal_adc_ex.h>

Data Fields

uint32_t | DataAlign
uint32_t | ScanConvMode
uint32_t | ContinuousConvMode
uint32_t | NbrOfConversion
uint32_t | DiscontinuousConvMode
uint32_t | NbrOfDiscConversion
uint32_t | ExternalTrigConv

Detailed Description

Structure definition of ADC and regular group initialization.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
  • Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. ADC can be either disabled or enabled without conversion on going on regular group.

Definition at line 364 of file stm32f3xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_InitTypeDef::ContinuousConvMode

Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, after the selected trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE.

Definition at line 380 of file stm32f3xx_hal_adc_ex.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), and HAL_ADCEx_InjectedPollForConversion().

uint32_t ADC_InitTypeDef::DataAlign

Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0U) (default setting) or to left (if regular group: MSB on register bit 15 and LSB on register bit 4U, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3U). This parameter can be a value of ADC Extended Data Alignment

Definition at line 366 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::DiscontinuousConvMode

Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE.

Definition at line 386 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ExternalTrigConv

Selects the external event used to trigger the conversion start of regular group. If set to ADC_SOFTWARE_START, external triggers are disabled. If set to external trigger source, triggering is on event rising edge. This parameter can be a value of ADC Extended External trigger selection for regular group

Definition at line 393 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::NbrOfConversion

Specifies the number of ranks that will be converted within the regular group sequencer. To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16.

Definition at line 383 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), and HAL_ADC_IRQHandler().

uint32_t ADC_InitTypeDef::NbrOfDiscConversion

Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8.

Definition at line 390 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ScanConvMode

Configures the sequencer of regular and injected groups. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1U). Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1U). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). Scan direction is upward: from rank1 to rank 'n'. This parameter can be a value of ADC Extended Scan Mode Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1U) or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the the last conversion of the sequence. All previous conversions would be overwritten by the last one. Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten.

Definition at line 369 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_adc_ex.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_ChannelConfTypeDef Struct Reference
ADCEx Exported Types

Structure definition of ADC channel for regular group. More...

#include <stm32f3xx_hal_adc_ex.h>

Data Fields

uint32_t | Channel
uint32_t | Rank
uint32_t | SamplingTime

Detailed Description

Structure definition of ADC channel for regular group.

Note:
The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. ADC can be either disabled or enabled without conversion on going on regular group.

Definition at line 404 of file stm32f3xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_ChannelConfTypeDef::Channel

Specifies the channel to configure into ADC regular group. This parameter can be a value of ADC Extended Channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.

Definition at line 406 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::Rank

Specifies the rank in the regular group sequencer This parameter can be a value of ADC Extended rank into regular group Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted)

Definition at line 409 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::SamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). This parameter can be a value of ADC Extended Sampling Times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min).

Definition at line 412 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_adc_ex.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC_InjectionConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjectionConfTypeDef Struct Reference
ADCEx Exported Types

ADC Configuration injected Channel structure definition. More...

#include <stm32f3xx_hal_adc_ex.h>

Data Fields

uint32_t | InjectedChannel
uint32_t | InjectedRank
uint32_t | InjectedSamplingTime
uint32_t | InjectedOffset
uint32_t | InjectedNbrOfConversion
uint32_t | InjectedDiscontinuousConvMode
uint32_t | AutoInjectedConv
uint32_t | ExternalTrigInjecConv

Detailed Description

ADC Configuration injected Channel structure definition.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
  • Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
  • For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.

Definition at line 434 of file stm32f3xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_InjectionConfTypeDef::AutoInjectedConv

Enables or disables the selected ADC automatic injected group conversion after regular one This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 467 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::ExternalTrigInjecConv

Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. If set to external trigger source, triggering is on event rising edge. This parameter can be a value of External Trigger Source of Injected Group Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 475 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedChannel

Selection of ADC channel to configure This parameter can be a value of ADC Extended Channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.

Definition at line 436 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode

Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 460 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedNbrOfConversion

Specifies the number of ranks that will be converted within the injected group sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 455 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedOffset

Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). Offset value must be a positive number. Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively.

Definition at line 451 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedRank

Rank in the injected group sequencer This parameter must be a value of ADC Extended Injected Channel Rank Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted)

Definition at line 439 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedSamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). This parameter can be a value of ADC Extended Sampling Times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min).

Definition at line 442 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_adc_ex.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC_AnalogWDGConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_AnalogWDGConfTypeDef Struct Reference
ADCEx Exported Types

ADC Configuration analog watchdog definition. More...

#include <stm32f3xx_hal_adc_ex.h>

Data Fields

uint32_t | WatchdogMode
uint32_t | Channel
uint32_t | ITMode
uint32_t | HighThreshold
uint32_t | LowThreshold
uint32_t | WatchdogNumber

Detailed Description

ADC Configuration analog watchdog definition.

Note:
The setting of these parameters with function is conditioned to ADC state. ADC state can be either disabled or enabled without conversion on going on regular and injected groups.

Definition at line 490 of file stm32f3xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_AnalogWDGConfTypeDef::Channel

Selects which ADC channel to monitor by analog watchdog. This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) This parameter can be a value of ADC Extended Channels.

Definition at line 494 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::HighThreshold

Configures the ADC analog watchdog High threshold value. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF.

Definition at line 499 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::ITMode

Specifies whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE

Definition at line 497 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::LowThreshold

Configures the ADC analog watchdog High threshold value. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF.

Definition at line 501 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogMode

Configures the ADC analog watchdog mode: single/all channels, regular/injected group. This parameter can be a value of ADC Extended analog watchdog mode.

Definition at line 492 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogNumber

Reserved for future use, can be set to 0U

Definition at line 503 of file stm32f3xx_hal_adc_ex.h.

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_adc_ex.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Extended Error Code

Defines
ADC Extended Error Code
ADCEx Exported Constants

Defines

#define | HAL_ADC_ERROR_NONE (0x00U)
#define | HAL_ADC_ERROR_INTERNAL (0x01U)
#define | HAL_ADC_ERROR_OVR (0x02U)
#define | HAL_ADC_ERROR_DMA (0x04U)
#define | HAL_ADC_ERROR_JQOVF (0x08U)

Define Documentation

#define HAL_ADC_ERROR_DMA (0x04U)

DMA transfer error

Definition at line 523 of file stm32f3xx_hal_adc_ex.h.

Referenced by ADC_DMAError(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define HAL_ADC_ERROR_INTERNAL (0x01U)

ADC IP internal error: if problem of clocking, enable/disable, erroneous state

Definition at line 520 of file stm32f3xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop_Disable(), ADC_Enable(), and HAL_ADC_Init().

#define HAL_ADC_ERROR_JQOVF (0x08U)

Injected context queue overflow error

Definition at line 524 of file stm32f3xx_hal_adc_ex.h.

#define HAL_ADC_ERROR_NONE (0x00U)

No error

Definition at line 519 of file stm32f3xx_hal_adc_ex.h.

#define HAL_ADC_ERROR_OVR (0x02U)

Overrun error

Definition at line 522 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Extended Data Alignment

Defines
ADC Extended Data Alignment
ADCEx Exported Constants

Defines

#define | ADC_DATAALIGN_RIGHT (0x00000000U)
#define | ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)

Define Documentation

#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)

Definition at line 1313 of file stm32f3xx_hal_adc_ex.h.

#define ADC_DATAALIGN_RIGHT (0x00000000U)

Definition at line 1312 of file stm32f3xx_hal_adc_ex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Extended Scan Mode

Defines
ADC Extended Scan Mode
ADCEx Exported Constants

Defines

#define | ADC_SCAN_DISABLE (0x00000000U)
#define | ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)

Define Documentation

#define ADC_SCAN_DISABLE (0x00000000U)

Definition at line 1321 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)

Definition at line 1322 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Extended External trigger enable for regular group

Defines
ADC Extended External trigger enable for regular group
ADCEx Exported Constants

Defines

#define | ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)

Define Documentation

#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U)

Definition at line 1330 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)

Definition at line 1331 of file stm32f3xx_hal_adc_ex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Extended External trigger selection for regular group

Defines
ADC Extended External trigger selection for regular group
ADCEx Exported Constants

Defines

#define | ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2
#define | ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO
#define | ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4
#define | ADC_EXTERNALTRIGCONV_T19_TRGO ADC_EXTERNALTRIG_T19_TRGO
#define | ADC_EXTERNALTRIGCONV_T19_CC3 ADC_EXTERNALTRIG_T19_CC3
#define | ADC_EXTERNALTRIGCONV_T19_CC4 ADC_EXTERNALTRIG_T19_CC4
#define | ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11
#define | ADC_SOFTWARE_START ADC_SWSTART

Define Documentation

#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11

Definition at line 1349 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGCONV_T19_CC3 ADC_EXTERNALTRIG_T19_CC3

Definition at line 1347 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGCONV_T19_CC4 ADC_EXTERNALTRIG_T19_CC4

Definition at line 1348 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGCONV_T19_TRGO ADC_EXTERNALTRIG_T19_TRGO

Definition at line 1346 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2

Definition at line 1343 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO

Definition at line 1344 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4

Definition at line 1345 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SOFTWARE_START ADC_SWSTART

Definition at line 1350 of file stm32f3xx_hal_adc_ex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Extended Channels

Defines
ADC Extended Channels
ADCEx Exported Constants

Defines

#define | ADC_CHANNEL_0 (0x00000000U)
#define | ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ1_1))
#define | ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ1_2))
#define | ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
#define | ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ1_3))
#define | ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1))
#define | ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2))
#define | ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
#define | ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4))
#define | ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_1))
#define | ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16
#define | ADC_CHANNEL_VREFINT ADC_CHANNEL_17
#define | ADC_CHANNEL_VBAT ADC_CHANNEL_18

Define Documentation

#define ADC_CHANNEL_0 (0x00000000U)

Definition at line 1360 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ1_0))

Definition at line 1361 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1))

Definition at line 1370 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))

Definition at line 1371 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2))

Definition at line 1372 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))

Definition at line 1373 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))

Definition at line 1374 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))

Definition at line 1375 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4))

Definition at line 1376 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))

Definition at line 1377 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_1))

Definition at line 1378 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ1_1))

Definition at line 1362 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))

Definition at line 1363 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ1_2))

Definition at line 1364 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))

Definition at line 1365 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))

Definition at line 1366 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))

Definition at line 1367 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ1_3))

Definition at line 1368 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))

Definition at line 1369 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16

Definition at line 1380 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_VBAT ADC_CHANNEL_18

Definition at line 1382 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17

Definition at line 1381 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

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STM32F373xC HAL User Manual: ADC Extended Sampling Times

Defines
ADC Extended Sampling Times
ADCEx Exported Constants

Defines

#define | ADC_SAMPLETIME_1CYCLE_5 (0x00000000U)
#define | ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_0)
#define | ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_1)
#define | ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0))
#define | ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_2)
#define | ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0))
#define | ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1))
#define | ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0)

Define Documentation

#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_1)

Sampling time 13.5 ADC clock cycles

Definition at line 1392 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_1CYCLE_5 (0x00000000U)

Sampling time 1.5 ADC clock cycle

Definition at line 1390 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0)

Sampling time 239.5 ADC clock cycles

Definition at line 1397 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0))

Sampling time 28.5 ADC clock cycles

Definition at line 1393 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_2)

Sampling time 41.5 ADC clock cycles

Definition at line 1394 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0))

Sampling time 55.5 ADC clock cycles

Definition at line 1395 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1))

Sampling time 71.5 ADC clock cycles

Definition at line 1396 of file stm32f3xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_0)

Sampling time 7.5 ADC clock cycles

Definition at line 1391 of file stm32f3xx_hal_adc_ex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Extended rank into regular group

Defines
ADC Extended rank into regular group
ADCEx Exported Constants

Defines

#define | ADC_REGULAR_RANK_1 (0x00000001U)
#define | ADC_REGULAR_RANK_2 (0x00000002U)
#define | ADC_REGULAR_RANK_3 (0x00000003U)
#define | ADC_REGULAR_RANK_4 (0x00000004U)
#define | ADC_REGULAR_RANK_5 (0x00000005U)
#define | ADC_REGULAR_RANK_6 (0x00000006U)
#define | ADC_REGULAR_RANK_7 (0x00000007U)
#define | ADC_REGULAR_RANK_8 (0x00000008U)
#define | ADC_REGULAR_RANK_9 (0x00000009U)
#define | ADC_REGULAR_RANK_10 (0x0000000AU)
#define | ADC_REGULAR_RANK_11 (0x0000000BU)
#define | ADC_REGULAR_RANK_12 (0x0000000CU)
#define | ADC_REGULAR_RANK_13 (0x0000000DU)
#define | ADC_REGULAR_RANK_14 (0x0000000EU)
#define | ADC_REGULAR_RANK_15 (0x0000000FU)
#define | ADC_REGULAR_RANK_16 (0x00000010U)

Define Documentation

#define ADC_REGULAR_RANK_1 (0x00000001U)

Definition at line 1405 of file stm32f3xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_10 (0x0000000AU)

Definition at line 1414 of file stm32f3xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_11 (0x0000000BU)

Definition at line 1415 of file stm32f3xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_12 (0x0000000CU)

Definition at line 1416 of file stm32f3xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_13 (0x0000000DU)

Definition at line 1417 of file stm32f3xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_14 (0x0000000EU)

Definition at line 1418 of file stm32f3xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_15 (0x0000000FU)

Definition at line 1419 of file stm32f3xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_16 (0x00000010U)

Definition at line 1420 of file stm32f3xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_2 (0x00000002U)

Definition at line 1406 of file stm32f3xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_3 (0x00000003U)

Definition at line 1407 of file stm32f3xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_4 (0x00000004U)

Definition at line 1408 of file stm32f3xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_5 (0x00000005U)

Definition at line 1409 of file stm32f3xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_6 (0x00000006U)

Definition at line 1410 of file stm32f3xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_7 (0x00000007U)

Definition at line 1411 of file stm32f3xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_8 (0x00000008U)

Definition at line 1412 of file stm32f3xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_9 (0x00000009U)

Definition at line 1413 of file stm32f3xx_hal_adc_ex.h.

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STM32F373xC HAL User Manual: ADC Extended Injected Channel Rank

Defines
ADC Extended Injected Channel Rank
ADCEx Exported Constants

Defines

#define | ADC_INJECTED_RANK_1 (0x00000001U)
#define | ADC_INJECTED_RANK_2 (0x00000002U)
#define | ADC_INJECTED_RANK_3 (0x00000003U)
#define | ADC_INJECTED_RANK_4 (0x00000004U)

Define Documentation

#define ADC_INJECTED_RANK_1 (0x00000001U)

Definition at line 1428 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_2 (0x00000002U)

Definition at line 1429 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_3 (0x00000003U)

Definition at line 1430 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_4 (0x00000004U)

Definition at line 1431 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: External Trigger Edge of Injected Group

Defines
External Trigger Edge of Injected Group
ADCEx Exported Constants

Defines

#define | ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)

Define Documentation

#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U)

Definition at line 1439 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)

Definition at line 1440 of file stm32f3xx_hal_adc_ex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: External Trigger Source of Injected Group

Defines
External Trigger Source of Injected Group
ADCEx Exported Constants

Defines

#define | ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1
#define | ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO
#define | ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4
#define | ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO
#define | ADC_EXTERNALTRIGINJECCONV_T19_CC1 ADC_EXTERNALTRIGINJEC_T19_CC1
#define | ADC_EXTERNALTRIGINJECCONV_T19_CC2 ADC_EXTERNALTRIGINJEC_T19_CC2
#define | ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15
#define | ADC_INJECTED_SOFTWARE_START ADC_JSWSTART

Define Documentation

#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15

Definition at line 1455 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T19_CC1 ADC_EXTERNALTRIGINJEC_T19_CC1

Definition at line 1453 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T19_CC2 ADC_EXTERNALTRIGINJEC_T19_CC2

Definition at line 1454 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1

Definition at line 1449 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO

Definition at line 1450 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4

Definition at line 1451 of file stm32f3xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO

Definition at line 1452 of file stm32f3xx_hal_adc_ex.h.

#define ADC_INJECTED_SOFTWARE_START ADC_JSWSTART

Definition at line 1456 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Extended analog watchdog mode

Defines
ADC Extended analog watchdog mode
ADCEx Exported Constants

Defines

#define | ADC_ANALOGWATCHDOG_NONE (0x00000000U)
#define | ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))

Define Documentation

#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)

Definition at line 1470 of file stm32f3xx_hal_adc_ex.h.

#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)

Definition at line 1469 of file stm32f3xx_hal_adc_ex.h.

#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))

Definition at line 1471 of file stm32f3xx_hal_adc_ex.h.

#define ADC_ANALOGWATCHDOG_NONE (0x00000000U)

Definition at line 1465 of file stm32f3xx_hal_adc_ex.h.

#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))

Definition at line 1467 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))

Definition at line 1466 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))

Definition at line 1468 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Conversion Group

Defines
ADC Conversion Group
ADCEx Exported Constants

Defines

#define | ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
#define | ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
#define | ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))

Define Documentation

#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))

Definition at line 1480 of file stm32f3xx_hal_adc_ex.h.

#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))

Definition at line 1479 of file stm32f3xx_hal_adc_ex.h.

#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))

Definition at line 1481 of file stm32f3xx_hal_adc_ex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Extended Event Type

Defines
ADC Extended Event Type
ADCEx Exported Constants

Defines

#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)

Define Documentation

#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)

ADC Analog watchdog event

Definition at line 1489 of file stm32f3xx_hal_adc_ex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Extended Interrupts Definition

Defines
ADC Extended Interrupts Definition
ADCEx Exported Constants

Defines

#define | ADC_IT_EOC ADC_CR1_EOCIE
#define | ADC_IT_JEOC ADC_CR1_JEOCIE
#define | ADC_IT_AWD ADC_CR1_AWDIE

Define Documentation

#define ADC_IT_AWD ADC_CR1_AWDIE

ADC Analog watchdog interrupt source

Definition at line 1499 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), and HAL_ADC_IRQHandler().

#define ADC_IT_EOC ADC_CR1_EOCIE

ADC End of Regular Conversion interrupt source

Definition at line 1497 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), and HAL_ADC_Stop_IT().

#define ADC_IT_JEOC ADC_CR1_JEOCIE

ADC End of Injected Conversion interrupt source

Definition at line 1498 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Extended Flags Definition

Defines
ADC Extended Flags Definition
ADCEx Exported Constants

Defines

#define | ADC_FLAG_AWD ADC_SR_AWD
#define | ADC_FLAG_EOC ADC_SR_EOC
#define | ADC_FLAG_JEOC ADC_SR_JEOC
#define | ADC_FLAG_JSTRT ADC_SR_JSTRT
#define | ADC_FLAG_STRT ADC_SR_STRT

Define Documentation

#define ADC_FLAG_AWD ADC_SR_AWD

ADC Analog watchdog flag

Definition at line 1507 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_EOC ADC_SR_EOC

ADC End of Regular conversion flag

Definition at line 1508 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_FLAG_JEOC ADC_SR_JEOC

ADC End of Injected conversion flag

Definition at line 1509 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_FLAG_JSTRT ADC_SR_JSTRT

ADC Injected group start flag

Definition at line 1510 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_FLAG_STRT ADC_SR_STRT

ADC Regular group start flag

Definition at line 1511 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForConversion().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADCEx Exported Macros

Defines
ADCEx Exported Macros
ADCEx

Defines

#define | __HAL_ADC_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
Enable the ADC peripheral.
#define | __HAL_ADC_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
Disable the ADC peripheral.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
Enable the ADC end of conversion interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
Disable the ADC end of conversion interrupt.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected ADC's flag status.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
Clear the ADC's pending flags.
#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
Reset ADC handle state.

Define Documentation

#define __HAL_ADC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))

Clear the ADC's pending flags.

Parameters:
__HANDLE__ ADC handle
__FLAG__ ADC flag This parameter can be any combination of the following values:
  • ADC_FLAG_STRT: ADC Regular group start flag
  • ADC_FLAG_JSTRT: ADC Injected group start flag
  • ADC_FLAG_EOC: ADC End of Regular conversion flag
  • ADC_FLAG_JEOC: ADC End of Injected conversion flag
  • ADC_FLAG_AWD: ADC Analog watchdog flag
Return values:
None

Definition at line 2154 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define __HAL_ADC_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))

Disable the ADC peripheral.

Parameters:
__HANDLE__ ADC handle
Return values:
None

Definition at line 2090 of file stm32f3xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop_Disable().

#define __HAL_ADC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))

Disable the ADC end of conversion interrupt.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC Interrupt This parameter can be any combination of the following values:
  • ADC_IT_EOC: ADC End of Regular Conversion interrupt source
  • ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
  • ADC_IT_AWD: ADC Analog watchdog interrupt source
Return values:
None

Definition at line 2114 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), HAL_ADC_Stop_IT(), and HAL_ADCEx_InjectedStop_IT().

#define __HAL_ADC_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))

Enable the ADC peripheral.

Note:
ADC enable requires a delay for ADC stabilization time (refer to device datasheet, parameter tSTAB)
On STM32F37x devices, if ADC is already enabled this macro trigs a conversion SW start on regular group.
Parameters:
__HANDLE__ ADC handle
Return values:
None

Definition at line 2082 of file stm32f3xx_hal_adc_ex.h.

Referenced by ADC_Enable().

#define __HAL_ADC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))

Enable the ADC end of conversion interrupt.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC Interrupt This parameter can be any combination of the following values:
  • ADC_IT_EOC: ADC End of Regular Conversion interrupt source
  • ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
  • ADC_IT_AWD: ADC Analog watchdog interrupt source
Return values:
None

Definition at line 2102 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_Start_IT(), and HAL_ADCEx_InjectedStart_IT().

#define __HAL_ADC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Get the selected ADC's flag status.

Parameters:
__HANDLE__ ADC handle
__FLAG__ ADC flag This parameter can be any combination of the following values:
  • ADC_FLAG_STRT: ADC Regular group start flag
  • ADC_FLAG_JSTRT: ADC Injected group start flag
  • ADC_FLAG_EOC: ADC End of Regular conversion flag
  • ADC_FLAG_JEOC: ADC End of Injected conversion flag
  • ADC_FLAG_AWD: ADC Analog watchdog flag
Return values:
None

Definition at line 2140 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define __HAL_ADC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))

Checks if the specified ADC interrupt source is enabled or disabled.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC interrupt source to check This parameter can be any combination of the following values:
  • ADC_IT_EOC: ADC End of Regular Conversion interrupt source
  • ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
  • ADC_IT_AWD: ADC Analog watchdog interrupt source
Return values:
State of interruption (SET or RESET)

Definition at line 2126 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler().

#define __HAL_ADC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)

Reset ADC handle state.

Parameters:
__HANDLE__ ADC handle
Return values:
None

Definition at line 2161 of file stm32f3xx_hal_adc_ex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Extended Range Verification

Defines
ADC Extended Range Verification
ADCEx Private Macros

For a unique ADC resolution: 12 bits. More...

Defines

#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= (0x0FFFU))

Detailed Description

For a unique ADC resolution: 12 bits.

Define Documentation

#define IS_ADC_RANGE ( ADC_VALUE ) ((ADC_VALUE) <= (0x0FFFU))

Definition at line 3825 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Injected Conversion Number Verification

Defines
ADC Injected Conversion Number Verification
ADCEx Private Macros

Defines

#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U)))

Define Documentation

#define IS_ADC_INJECTED_NB_CONV ( LENGTH ) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U)))

Definition at line 3833 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Regular Conversion Number Verification

Defines
ADC Regular Conversion Number Verification
ADCEx Private Macros

Defines

#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U)))

Define Documentation

#define IS_ADC_REGULAR_NB_CONV ( LENGTH ) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U)))

Definition at line 3841 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), and HAL_ADC_IRQHandler().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Regular Discontinuous Mode NumberVerification

Defines
ADC Regular Discontinuous Mode NumberVerification
ADCEx Private Macros

Defines

#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))

Define Documentation

#define IS_ADC_REGULAR_DISCONT_NUMBER ( NUMBER ) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))

Definition at line 3849 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADCEx Private Macros

Modules | Defines
ADCEx Private Macros
ADCEx

Modules

ADC Extended Range Verification

For a unique ADC resolution: 12 bits.

ADC Injected Conversion Number Verification
ADC Regular Conversion Number Verification
ADC Regular Discontinuous Mode NumberVerification

Defines

#define | ADC_IS_ENABLE(__HANDLE__)
Verification of ADC state: enabled or disabled.
#define | ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
Test if conversion trigger of regular group is software start or external trigger.
#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clears and sets specific bits of the handle State.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to error code: "no error")
#define | ADC_SQR1_L_SHIFT(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
Set ADC number of conversions into regular channel sequence length.
#define | ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U)))
Set the ADC's sample time for channel numbers between 10 and 18.
#define | ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (_CHANNELNB_)))
Set the ADC's sample time for channel numbers between 0 and 9.
#define | ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5U * ((_RANKNB_) - 1U)))
Set the selected regular channel rank for rank between 1 and 6.
#define | ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5U * ((_RANKNB_) - 7U)))
Set the selected regular channel rank for rank between 7 and 12.
#define | ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5U * ((_RANKNB_) - 13U)))
Set the selected regular channel rank for rank between 13 and 16.
#define | ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_) -1U) << 20U)
Set the injected sequence length.
#define | ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) ((_CHANNELNB_) << (5U * ((4U - ((_JSQR_JL_) - (_RANKNB_))) - 1U)))
Set the selected injected channel rank Note: on STM32F37x devices, channel rank position in JSQR register is depending on total number of ranks selected into injected sequencer (ranks sequence starting from 4-JL)
#define | ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U)
Enable ADC continuous conversion mode.
#define | ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 13U)
Configures the number of discontinuous conversions for the regular group channels.
#define | ADC_CR1_SCAN_SET(_SCAN_MODE_)
Enable ADC scan mode to convert multiple ranks with sequencer.
#define | ADC_CALFACT_DIFF_SET(_Calibration_Factor_) ((_Calibration_Factor_) << 16U)
Calibration factor in differential mode to be set into calibration register.
#define | ADC_CALFACT_DIFF_GET(_Calibration_Factor_) ((_Calibration_Factor_) >> 16U)
Calibration factor in differential mode to be retrieved from calibration register.
#define | ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)
Get the maximum ADC conversion cycles on all channels.
#define | ADC_CLOCK_PRESCALER_RANGE()
Get the total ADC clock prescaler (APB2 prescaler x ADC prescaler) from system clock configuration register.
#define | ADC_GET_CLOCK_PRESCALER() (((RCC->CFGR & RCC_CFGR_ADCPRE) >> 14U) +1U)
Get the ADC clock prescaler from system clock configuration register.
#define | IS_ADC_DATA_ALIGN(ALIGN)
#define | IS_ADC_SCAN_MODE(SCAN_MODE)
#define | IS_ADC_CHANNEL(CHANNEL)
#define | IS_ADC_SAMPLE_TIME(TIME)
#define | IS_ADC_REGULAR_RANK(CHANNEL)
#define | IS_ADC_EXTTRIG_EDGE(EDGE)
#define | IS_ADC_EXTTRIG(REGTRIG)
#define | IS_ADC_EXTTRIGINJEC_EDGE(EDGE)
#define | IS_ADC_EXTTRIGINJEC(INJTRIG)
#define | IS_ADC_INJECTED_RANK(CHANNEL)
#define | IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG)
#define | IS_ADC_CONVERSION_GROUP(CONVERSION)
#define | IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)

Define Documentation

#define ADC_CALFACT_DIFF_GET ( _Calibration_Factor_ ) ((_Calibration_Factor_) >> 16U)

Calibration factor in differential mode to be retrieved from calibration register.

Parameters:
_Calibration_Factor_ Calibration factor value
Return values:
None

Definition at line 3671 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CALFACT_DIFF_SET ( _Calibration_Factor_ ) ((_Calibration_Factor_) << 16U)

Calibration factor in differential mode to be set into calibration register.

Parameters:
_Calibration_Factor_ Calibration factor value
Return values:
None

Definition at line 3663 of file stm32f3xx_hal_adc_ex.h.

#define ADC_CLEAR_ERRORCODE ( __HANDLE__ ) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)

Clear ADC error code (set it to error code: "no error")

Parameters:
__HANDLE__ ADC handle
Return values:
None

Definition at line 3553 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_CLOCK_PRESCALER_RANGE ( )
Value:
(( (RCC->CFGR & (RCC_CFGR_ADCPRE_1 | RCC_CFGR_ADCPRE_0)) == RESET) ?         \
      (( (RCC->CFGR & RCC_CFGR_PPRE2_2) == RESET) ? 2 : 32U )                   \
      :                                                                        \
      (( (RCC->CFGR & RCC_CFGR_PPRE2_1) == RESET) ? 32 : 128U )                 \
  )

Get the total ADC clock prescaler (APB2 prescaler x ADC prescaler) from system clock configuration register.

Approximation within 3 ranges, returns the higher value: total prescaler minimum: 2 (ADC presc 2, APB2 presc 0) total prescaler 32 (ADC presc 0 and APB2 presc all, or ADC presc {4, 6, 8} and APB2 presc {0, 2, 4}) total prescaler maximum: 128 (ADC presc {4, 6, 8} and APB2 presc {8, 16}) Unit: none (prescaler factor)

Return values:
ADC and APB2 prescaler factor

Definition at line 3713 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForConversion(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_CONVCYCLES_MAX_RANGE ( __HANDLE__ )
Value:
(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET)  &&                     \
       (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ?                     \
                                                                                \
          (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET)  &&               \
             (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ?               \
               ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5)   \
          :                                                                                                      \
          ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET)  &&               \
             (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) ||               \
            ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET)  &&               \
             (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ?               \
               ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
     )

Get the maximum ADC conversion cycles on all channels.

Returns the selected sampling time + conversion time (12.5 ADC clock cycles) Approximation of sampling time within 4 ranges, returns the highest value: below 7.5 cycles {1.5 cycle; 7.5 cycles}, between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles} between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles} equal to 239.5 cycles Unit: ADC clock cycles

Parameters:
__HANDLE__ ADC handle
Return values:
ADC conversion cycles on all channels

Definition at line 3687 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForConversion(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_CR1_DISCONTINUOUS_NUM ( _NBR_DISCONTINUOUS_CONV_ ) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 13U)

Configures the number of discontinuous conversions for the regular group channels.

Parameters:
_NBR_DISCONTINUOUS_CONV_ Number of discontinuous conversions.
Return values:
None

Definition at line 3643 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CR1_SCAN_SET ( _SCAN_MODE_ )
Value:
(( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE)           \
   )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE)                                   \
  )

Enable ADC scan mode to convert multiple ranks with sequencer.

Parameters:
_SCAN_MODE_ Scan conversion mode.
Return values:
None

Definition at line 3653 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CR2_CONTINUOUS ( _CONTINUOUS_MODE_ ) ((_CONTINUOUS_MODE_) << 1U)

Enable ADC continuous conversion mode.

Parameters:
_CONTINUOUS_MODE_ Continuous mode.
Return values:
None

Definition at line 3635 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_GET_CLOCK_PRESCALER ( ) (((RCC->CFGR & RCC_CFGR_ADCPRE) >> 14U) +1U)

Get the ADC clock prescaler from system clock configuration register.

Return values:
None

Definition at line 3724 of file stm32f3xx_hal_adc_ex.h.

#define ADC_IS_ENABLE ( __HANDLE__ )
Value:
((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON )           \
   ) ? SET : RESET)

Verification of ADC state: enabled or disabled.

Parameters:
__HANDLE__ ADC handle
Return values:
SET (ADC enabled) or RESET (ADC disabled)

Definition at line 3517 of file stm32f3xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop_Disable(), ADC_Enable(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_IS_SOFTWARE_START_INJECTED ( __HANDLE__ ) (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)

Test if conversion trigger of injected group is software start or external trigger.

Parameters:
__HANDLE__ ADC handle
Return values:
SET (software start) or RESET (external trigger)

Definition at line 3536 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_IS_SOFTWARE_START_REGULAR ( __HANDLE__ ) (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)

Test if conversion trigger of regular group is software start or external trigger.

Parameters:
__HANDLE__ ADC handle
Return values:
SET (software start) or RESET (external trigger)

Definition at line 3527 of file stm32f3xx_hal_adc_ex.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_JSQR_JL_SHIFT ( _JSQR_JL_ ) (((_JSQR_JL_) -1U) << 20U)

Set the injected sequence length.

Parameters:
_JSQR_JL_ Sequence length.
Return values:
None

Definition at line 3614 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_JSQR_RK_JL | ( | _CHANNELNB_,
 |  | _RANKNB_,
 |  | _JSQR_JL_
 | ) | ((_CHANNELNB_) << (5U * ((4U - ((_JSQR_JL_) - (_RANKNB_))) - 1U)))

Set the selected injected channel rank Note: on STM32F37x devices, channel rank position in JSQR register is depending on total number of ranks selected into injected sequencer (ranks sequence starting from 4-JL)

Parameters:
_CHANNELNB_ | Channel number.
_RANKNB_ | Rank number.
_JSQR_JL_ | Sequence length.
Return values:
None

Definition at line 3627 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_SMPR1 | ( | _SAMPLETIME_,
 |  | _CHANNELNB_
 | ) | ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U)))

Set the ADC's sample time for channel numbers between 10 and 18.

Parameters:
_SAMPLETIME_ | Sample time parameter.
_CHANNELNB_ | Channel number.
Return values:
None

Definition at line 3570 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SMPR2 | ( | _SAMPLETIME_,
 |  | _CHANNELNB_
 | ) | ((_SAMPLETIME_) << (3U * (_CHANNELNB_)))

Set the ADC's sample time for channel numbers between 0 and 9.

Parameters:
_SAMPLETIME_ | Sample time parameter.
_CHANNELNB_ | Channel number.
Return values:
None

Definition at line 3579 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SQR1_L_SHIFT ( _NbrOfConversion_ ) (((_NbrOfConversion_) - (uint8_t)1U) << 20U)

Set ADC number of conversions into regular channel sequence length.

Parameters:
_NbrOfConversion_ Regular channel sequence length
Return values:
None

Definition at line 3561 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_SQR1_RK | ( | _CHANNELNB_,
 |  | _RANKNB_
 | ) | ((_CHANNELNB_) << (5U * ((_RANKNB_) - 13U)))

Set the selected regular channel rank for rank between 13 and 16.

Parameters:
_CHANNELNB_ | Channel number.
_RANKNB_ | Rank number.
Return values:
None

Definition at line 3606 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_SQR2_RK | ( | _CHANNELNB_,
 |  | _RANKNB_
 | ) | ((_CHANNELNB_) << (5U * ((_RANKNB_) - 7U)))

Set the selected regular channel rank for rank between 7 and 12.

Parameters:
_CHANNELNB_ | Channel number.
_RANKNB_ | Rank number.
Return values:
None

Definition at line 3597 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_SQR3_RK | ( | _CHANNELNB_,
 |  | _RANKNB_
 | ) | ((_CHANNELNB_) << (5U * ((_RANKNB_) - 1U)))

Set the selected regular channel rank for rank between 1 and 6.

Parameters:
_CHANNELNB_ | Channel number.
_RANKNB_ | Rank number.
Return values:
None

Definition at line 3588 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_STATE_CLR_SET MODIFY_REG

Simultaneously clears and sets specific bits of the handle State.

Note:
: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), the first parameter is the ADC handle State, the second parameter is the bit field to clear, the third and last parameter is the bit field to set.
Return values:
None

Definition at line 3546 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), and HAL_ADCEx_InjectedStop_IT().

#define IS_ADC_ANALOG_WATCHDOG_MODE ( WATCHDOG )
Value:
(((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)             || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )

Definition at line 3807 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == ADC_CHANNEL_0)           || \
                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
                                 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)  || \
                                 ((CHANNEL) == ADC_CHANNEL_VREFINT)     || \
                                 ((CHANNEL) == ADC_CHANNEL_VBAT)          )

Definition at line 3732 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_CONVERSION_GROUP ( CONVERSION )
Value:
(((CONVERSION) == ADC_REGULAR_GROUP)          || \
                                             ((CONVERSION) == ADC_INJECTED_GROUP)         || \
                                             ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP)   )

Definition at line 3815 of file stm32f3xx_hal_adc_ex.h.

#define IS_ADC_DATA_ALIGN ( ALIGN )
Value:
(((ALIGN) == ADC_DATAALIGN_RIGHT) || \
                                  ((ALIGN) == ADC_DATAALIGN_LEFT)    )

Definition at line 3726 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EVENT_TYPE ( EVENT ) ((EVENT) == ADC_AWD_EVENT)

Definition at line 3819 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForEvent().

#define IS_ADC_EXTTRIG ( REGTRIG )
Value:
(((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)   || \
                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)  || \
                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)   || \
                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_TRGO) || \
                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC3)  || \
                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC4)  || \
                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
                                 ((REGTRIG) == ADC_SOFTWARE_START)              )

Definition at line 3781 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EXTTRIG_EDGE ( EDGE )
Value:
(((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)  || \
                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)  )

Definition at line 3778 of file stm32f3xx_hal_adc_ex.h.

#define IS_ADC_EXTTRIGINJEC ( INJTRIG )
Value:
(((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC1)  || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC2)  || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
                                      ((INJTRIG) == ADC_INJECTED_SOFTWARE_START)          )

Definition at line 3793 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_EXTTRIGINJEC_EDGE ( EDGE )
Value:
(((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)  || \
                                        ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)  )

Definition at line 3790 of file stm32f3xx_hal_adc_ex.h.

#define IS_ADC_INJECTED_RANK ( CHANNEL )
Value:
(((CHANNEL) == ADC_INJECTED_RANK_1) || \
                                       ((CHANNEL) == ADC_INJECTED_RANK_2) || \
                                       ((CHANNEL) == ADC_INJECTED_RANK_3) || \
                                       ((CHANNEL) == ADC_INJECTED_RANK_4)   )

Definition at line 3802 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_InjectedGetValue().

#define IS_ADC_REGULAR_RANK ( CHANNEL )
Value:
(((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_10) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_11) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_12) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_13) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_14) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_15) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_16)   )

Definition at line 3761 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

#define IS_ADC_SAMPLE_TIME ( TIME )
Value:
(((TIME) == ADC_SAMPLETIME_1CYCLE_5)    || \
                                  ((TIME) == ADC_SAMPLETIME_7CYCLES_5)   || \
                                  ((TIME) == ADC_SAMPLETIME_13CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_28CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_41CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_55CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_71CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_239CYCLES_5)   )

Definition at line 3752 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_SCAN_MODE ( SCAN_MODE )
Value:
(((SCAN_MODE) == ADC_SCAN_DISABLE) || \
                                     ((SCAN_MODE) == ADC_SCAN_ENABLE)    )

Definition at line 3729 of file stm32f3xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Private Constants

Defines
CAN Private Constants
CAN

Defines

#define | CAN_TIMEOUT_VALUE 10U
#define | CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U)
#define | CAN_FLAG_MASK (0x000000FFU)

Define Documentation

#define CAN_FLAG_MASK (0x000000FFU)

Definition at line 729 of file stm32f3xx_hal_can.h.

#define CAN_TIMEOUT_VALUE 10U

Definition at line 128 of file stm32f3xx_hal_can.c.

Referenced by HAL_CAN_Init(), HAL_CAN_Sleep(), and HAL_CAN_WakeUp().

#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U)

CAN cell did not provide CAN_TxStatus_NoMailBox

Definition at line 728 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Private Functions

Functions
CAN Private Functions
CAN

CAN Frame message Rx/Tx functions. More...

Functions

static HAL_StatusTypeDef | CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receives a correct CAN frame.
static HAL_StatusTypeDef | CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiates and transmits a CAN frame message.

Detailed Description

CAN Frame message Rx/Tx functions.

Function Documentation

static HAL_StatusTypeDef CAN_Receive_IT | ( | CAN_HandleTypeDef * | hcan,
 |  | uint8_t | FIFONumber
 | ) |  | [static]

Receives a correct CAN frame.

Parameters:
hcan | Pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
FIFONumber | Specify the FIFO number
Return values:
HAL status
None

Definition at line 1563 of file stm32f3xx_hal_can.c.

References __HAL_CAN_DISABLE_IT, __HAL_CAN_FIFO_RELEASE, CAN_FIFO0, CAN_FIFO1, CAN_ID_STD, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FMP0, CAN_IT_FMP1, CAN_IT_FOV0, CAN_IT_FOV1, CAN_IT_LEC, CanRxMsgTypeDef::Data, CanRxMsgTypeDef::DLC, CanRxMsgTypeDef::ExtId, CanRxMsgTypeDef::FIFONumber, CanRxMsgTypeDef::FMI, HAL_CAN_RxCpltCallback(), HAL_CAN_STATE_BUSY_RX0, HAL_CAN_STATE_BUSY_RX0_RX1, HAL_CAN_STATE_BUSY_RX1, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX0, HAL_CAN_STATE_BUSY_TX_RX0_RX1, HAL_CAN_STATE_BUSY_TX_RX1, HAL_CAN_STATE_READY, CanRxMsgTypeDef::IDE, CAN_HandleTypeDef::Instance, CAN_HandleTypeDef::pRx1Msg, CAN_HandleTypeDef::pRxMsg, CanRxMsgTypeDef::RTR, CAN_HandleTypeDef::State, and CanRxMsgTypeDef::StdId.

Referenced by HAL_CAN_IRQHandler().

static HAL_StatusTypeDef CAN_Transmit_IT ( CAN_HandleTypeDef * hcan ) [static]

Initiates and transmits a CAN frame message.

Parameters:
hcan pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status

Definition at line 1512 of file stm32f3xx_hal_can.c.

References __HAL_CAN_DISABLE_IT, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_LEC, CAN_IT_TME, HAL_CAN_STATE_BUSY_RX0, HAL_CAN_STATE_BUSY_RX0_RX1, HAL_CAN_STATE_BUSY_RX1, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX0, HAL_CAN_STATE_BUSY_TX_RX0_RX1, HAL_CAN_STATE_BUSY_TX_RX1, HAL_CAN_STATE_READY, HAL_CAN_TxCpltCallback(), and CAN_HandleTypeDef::State.

Referenced by HAL_CAN_IRQHandler().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CAN Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CAN_Init (CAN_HandleTypeDef *hcan)
Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.
HAL_StatusTypeDef | HAL_CAN_ConfigFilter (CAN_HandleTypeDef *hcan, CAN_FilterConfTypeDef *sFilterConfig)
Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.
HAL_StatusTypeDef | HAL_CAN_DeInit (CAN_HandleTypeDef *hcan)
Deinitializes the CANx peripheral registers to their default reset values.
__weak void | HAL_CAN_MspInit (CAN_HandleTypeDef *hcan)
Initializes the CAN MSP.
__weak void | HAL_CAN_MspDeInit (CAN_HandleTypeDef *hcan)
DeInitializes the CAN MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the CAN.
      (+) De-initialize the CAN.

Function Documentation

HAL_StatusTypeDef HAL_CAN_ConfigFilter | ( | CAN_HandleTypeDef * | hcan,
 |  | CAN_FilterConfTypeDef * | sFilterConfig
 | ) |  |

Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.

Parameters:
hcan | pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
sFilterConfig | pointer to a CAN_FilterConfTypeDef structure that contains the filter configuration information.
Return values:
None

Definition at line 356 of file stm32f3xx_hal_can.c.

References assert_param, CAN_FILTER_FIFO0, CAN_FILTERMODE_IDMASK, CAN_FILTERSCALE_16BIT, CAN_FILTERSCALE_32BIT, CAN_FilterConfTypeDef::FilterActivation, CAN_FilterConfTypeDef::FilterFIFOAssignment, CAN_FilterConfTypeDef::FilterIdHigh, CAN_FilterConfTypeDef::FilterIdLow, CAN_FilterConfTypeDef::FilterMaskIdHigh, CAN_FilterConfTypeDef::FilterMaskIdLow, CAN_FilterConfTypeDef::FilterMode, CAN_FilterConfTypeDef::FilterNumber, CAN_FilterConfTypeDef::FilterScale, CAN_HandleTypeDef::Instance, IS_CAN_FILTER_FIFO, IS_CAN_FILTER_MODE, IS_CAN_FILTER_NUMBER, and IS_CAN_FILTER_SCALE.

HAL_StatusTypeDef HAL_CAN_DeInit ( CAN_HandleTypeDef * hcan )

Deinitializes the CANx peripheral registers to their default reset values.

Parameters:
hcan pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status

Definition at line 453 of file stm32f3xx_hal_can.c.

References assert_param, HAL_CAN_MspDeInit(), HAL_CAN_STATE_BUSY, HAL_CAN_STATE_RESET, CAN_HandleTypeDef::Instance, and CAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CAN_Init ( CAN_HandleTypeDef * hcan )

Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.

Parameters:
hcan pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status

Definition at line 172 of file stm32f3xx_hal_can.c.

References CAN_InitTypeDef::ABOM, assert_param, CAN_InitTypeDef::AWUM, CAN_InitTypeDef::BS1, CAN_InitTypeDef::BS2, CAN_INITSTATUS_FAILED, CAN_INITSTATUS_SUCCESS, CAN_TIMEOUT_VALUE, CAN_HandleTypeDef::ErrorCode, HAL_CAN_ERROR_NONE, HAL_CAN_MspInit(), HAL_CAN_STATE_BUSY, HAL_CAN_STATE_ERROR, HAL_CAN_STATE_READY, HAL_CAN_STATE_RESET, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CAN_HandleTypeDef::Init, CAN_HandleTypeDef::Instance, IS_CAN_BS1, IS_CAN_BS2, IS_CAN_MODE, IS_CAN_PRESCALER, IS_CAN_SJW, CAN_HandleTypeDef::Lock, CAN_InitTypeDef::Mode, CAN_InitTypeDef::NART, CAN_InitTypeDef::Prescaler, CAN_InitTypeDef::RFLM, CAN_InitTypeDef::SJW, CAN_HandleTypeDef::State, CAN_InitTypeDef::TTCM, and CAN_InitTypeDef::TXFP.

void HAL_CAN_MspDeInit ( CAN_HandleTypeDef * hcan )

DeInitializes the CAN MSP.

Parameters:
hcan pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 502 of file stm32f3xx_hal_can.c.

Referenced by HAL_CAN_DeInit().

void HAL_CAN_MspInit ( CAN_HandleTypeDef * hcan )

Initializes the CAN MSP.

Parameters:
hcan pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 486 of file stm32f3xx_hal_can.c.

Referenced by HAL_CAN_Init().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
CAN Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_CAN_Transmit (CAN_HandleTypeDef *hcan, uint32_t Timeout)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Receive (CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Sleep (CAN_HandleTypeDef *hcan)
Enters the Sleep (low power) mode.
HAL_StatusTypeDef | HAL_CAN_WakeUp (CAN_HandleTypeDef *hcan)
Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode.
void | HAL_CAN_IRQHandler (CAN_HandleTypeDef *hcan)
Handles CAN interrupt request.
__weak void | HAL_CAN_TxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_RxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_ErrorCallback (CAN_HandleTypeDef *hcan)
Error CAN callback.

Detailed Description

IO operation functions.

I/O operation functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Transmit a CAN frame message.
      (+) Receive a CAN frame message.
      (+) Enter CAN peripheral in sleep mode.
      (+) Wake up the CAN peripheral from sleep mode.

Function Documentation

void HAL_CAN_ErrorCallback ( CAN_HandleTypeDef * hcan )

Error CAN callback.

Parameters:
hcan pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 1439 of file stm32f3xx_hal_can.c.

Referenced by HAL_CAN_IRQHandler().

void HAL_CAN_IRQHandler ( CAN_HandleTypeDef * hcan )

Handles CAN interrupt request.

Parameters:
hcan pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 1223 of file stm32f3xx_hal_can.c.

References __HAL_CAN_CLEAR_FLAG, __HAL_CAN_DISABLE_IT, __HAL_CAN_GET_FLAG, __HAL_CAN_GET_IT_SOURCE, __HAL_CAN_MSG_PENDING, __HAL_CAN_TRANSMIT_STATUS, CAN_FIFO0, CAN_FIFO1, CAN_FLAG_BOF, CAN_FLAG_EPV, CAN_FLAG_EWG, CAN_FLAG_FOV0, CAN_FLAG_FOV1, CAN_FLAG_TXOK0, CAN_FLAG_TXOK1, CAN_FLAG_TXOK2, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FMP0, CAN_IT_FMP1, CAN_IT_FOV0, CAN_IT_FOV1, CAN_IT_LEC, CAN_IT_TME, CAN_Receive_IT(), CAN_Transmit_IT(), CAN_TXMAILBOX_0, CAN_TXMAILBOX_1, CAN_TXMAILBOX_2, CAN_HandleTypeDef::ErrorCode, HAL_CAN_ERROR_ACK, HAL_CAN_ERROR_BD, HAL_CAN_ERROR_BOF, HAL_CAN_ERROR_BR, HAL_CAN_ERROR_CRC, HAL_CAN_ERROR_EPV, HAL_CAN_ERROR_EWG, HAL_CAN_ERROR_FOR, HAL_CAN_ERROR_FOV0, HAL_CAN_ERROR_FOV1, HAL_CAN_ERROR_NONE, HAL_CAN_ERROR_STF, HAL_CAN_ERROR_TXFAIL, HAL_CAN_ErrorCallback(), HAL_CAN_STATE_READY, CAN_HandleTypeDef::Instance, and CAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CAN_Receive | ( | CAN_HandleTypeDef * | hcan,
 |  | uint8_t | FIFONumber,
 |  | uint32_t | Timeout
 | ) |  |

Receives a correct CAN frame.

Parameters:
hcan | pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
FIFONumber | FIFO number.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 805 of file stm32f3xx_hal_can.c.

References __HAL_CAN_FIFO_RELEASE, __HAL_CAN_MSG_PENDING, assert_param, CAN_FIFO0, CAN_FIFO1, CAN_ID_STD, CanRxMsgTypeDef::Data, CanRxMsgTypeDef::DLC, CanRxMsgTypeDef::ExtId, CanRxMsgTypeDef::FIFONumber, CanRxMsgTypeDef::FMI, HAL_CAN_STATE_BUSY_RX0, HAL_CAN_STATE_BUSY_RX0_RX1, HAL_CAN_STATE_BUSY_RX1, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX0, HAL_CAN_STATE_BUSY_TX_RX0_RX1, HAL_CAN_STATE_BUSY_TX_RX1, HAL_CAN_STATE_READY, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CanRxMsgTypeDef::IDE, CAN_HandleTypeDef::Instance, IS_CAN_FIFO, CAN_HandleTypeDef::pRx1Msg, CAN_HandleTypeDef::pRxMsg, CanRxMsgTypeDef::RTR, CAN_HandleTypeDef::State, and CanRxMsgTypeDef::StdId.

HAL_StatusTypeDef HAL_CAN_Receive_IT | ( | CAN_HandleTypeDef * | hcan,
 |  | uint8_t | FIFONumber
 | ) |  |

Receives a correct CAN frame.

Parameters:
hcan | pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
FIFONumber | FIFO number.
Return values:
HAL status

Definition at line 1000 of file stm32f3xx_hal_can.c.

References __HAL_CAN_ENABLE_IT, assert_param, CAN_FIFO0, CAN_FIFO1, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FMP0, CAN_IT_FMP1, CAN_IT_FOV0, CAN_IT_FOV1, CAN_IT_LEC, CAN_HandleTypeDef::ErrorCode, HAL_CAN_ERROR_NONE, HAL_CAN_STATE_BUSY_RX0, HAL_CAN_STATE_BUSY_RX0_RX1, HAL_CAN_STATE_BUSY_RX1, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX0, HAL_CAN_STATE_BUSY_TX_RX0_RX1, HAL_CAN_STATE_BUSY_TX_RX1, IS_CAN_FIFO, and CAN_HandleTypeDef::State.

void HAL_CAN_RxCpltCallback ( CAN_HandleTypeDef * hcan )

Transmission complete callback in non blocking mode.

Parameters:
hcan pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 1423 of file stm32f3xx_hal_can.c.

Referenced by CAN_Receive_IT().

HAL_StatusTypeDef HAL_CAN_Sleep ( CAN_HandleTypeDef * hcan )

Enters the Sleep (low power) mode.

Parameters:
hcan pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status.

Definition at line 1109 of file stm32f3xx_hal_can.c.

References CAN_TIMEOUT_VALUE, HAL_CAN_STATE_BUSY, HAL_CAN_STATE_READY, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CAN_HandleTypeDef::Instance, and CAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CAN_Transmit | ( | CAN_HandleTypeDef * | hcan,
 |  | uint32_t | Timeout
 | ) |  |

Initiates and transmits a CAN frame message.

Parameters:
hcan | pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 540 of file stm32f3xx_hal_can.c.

References __HAL_CAN_CANCEL_TRANSMIT, __HAL_CAN_TRANSMIT_STATUS, assert_param, CAN_ID_STD, CAN_TXMAILBOX_0, CAN_TXMAILBOX_1, CAN_TXMAILBOX_2, CAN_TXSTATUS_NOMAILBOX, CanTxMsgTypeDef::Data, CanTxMsgTypeDef::DLC, CanTxMsgTypeDef::ExtId, HAL_CAN_STATE_BUSY_RX0, HAL_CAN_STATE_BUSY_RX0_RX1, HAL_CAN_STATE_BUSY_RX1, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX0, HAL_CAN_STATE_BUSY_TX_RX0_RX1, HAL_CAN_STATE_BUSY_TX_RX1, HAL_CAN_STATE_ERROR, HAL_CAN_STATE_READY, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CanTxMsgTypeDef::IDE, CAN_HandleTypeDef::Instance, IS_CAN_DLC, IS_CAN_EXTID, IS_CAN_IDTYPE, IS_CAN_RTR, IS_CAN_STDID, CAN_HandleTypeDef::pTxMsg, CanTxMsgTypeDef::RTR, CAN_HandleTypeDef::State, and CanTxMsgTypeDef::StdId.

HAL_StatusTypeDef HAL_CAN_Transmit_IT ( CAN_HandleTypeDef * hcan )

Initiates and transmits a CAN frame message.

Parameters:
hcan pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status

Definition at line 684 of file stm32f3xx_hal_can.c.

References __HAL_CAN_ENABLE_IT, assert_param, CAN_ID_STD, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_LEC, CAN_IT_TME, CAN_TXMAILBOX_0, CAN_TXMAILBOX_1, CAN_TXMAILBOX_2, CAN_TXSTATUS_NOMAILBOX, CanTxMsgTypeDef::Data, CanTxMsgTypeDef::DLC, CAN_HandleTypeDef::ErrorCode, CanTxMsgTypeDef::ExtId, HAL_CAN_ERROR_NONE, HAL_CAN_STATE_BUSY_RX0, HAL_CAN_STATE_BUSY_RX0_RX1, HAL_CAN_STATE_BUSY_RX1, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX0, HAL_CAN_STATE_BUSY_TX_RX0_RX1, HAL_CAN_STATE_BUSY_TX_RX1, HAL_CAN_STATE_ERROR, CanTxMsgTypeDef::IDE, CAN_HandleTypeDef::Instance, IS_CAN_DLC, IS_CAN_EXTID, IS_CAN_IDTYPE, IS_CAN_RTR, IS_CAN_STDID, CAN_HandleTypeDef::pTxMsg, CanTxMsgTypeDef::RTR, CAN_HandleTypeDef::State, and CanTxMsgTypeDef::StdId.

void HAL_CAN_TxCpltCallback ( CAN_HandleTypeDef * hcan )

Transmission complete callback in non blocking mode.

Parameters:
hcan pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 1407 of file stm32f3xx_hal_can.c.

Referenced by CAN_Transmit_IT().

HAL_StatusTypeDef HAL_CAN_WakeUp ( CAN_HandleTypeDef * hcan )

Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode.

Parameters:
hcan pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status.

Definition at line 1168 of file stm32f3xx_hal_can.c.

References CAN_TIMEOUT_VALUE, HAL_CAN_STATE_BUSY, HAL_CAN_STATE_READY, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CAN_HandleTypeDef::Instance, and CAN_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
CAN Exported Functions

CAN Peripheral State functions. More...

Functions

HAL_CAN_StateTypeDef | HAL_CAN_GetState (CAN_HandleTypeDef *hcan)
return the CAN state
uint32_t | HAL_CAN_GetError (CAN_HandleTypeDef *hcan)
Return the CAN error code.

Detailed Description

CAN Peripheral State functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Check the CAN state.
      (+) Check CAN Errors detected during interrupt process

Function Documentation

uint32_t HAL_CAN_GetError ( CAN_HandleTypeDef * hcan )

Return the CAN error code.

Parameters:
hcan pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
CAN Error Code

Definition at line 1487 of file stm32f3xx_hal_can.c.

References CAN_HandleTypeDef::ErrorCode.

HAL_CAN_StateTypeDef HAL_CAN_GetState ( CAN_HandleTypeDef * hcan )

return the CAN state

Parameters:
hcan pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL state

Definition at line 1475 of file stm32f3xx_hal_can.c.

References CAN_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Exported Types

Data Structures | Enumerations
CAN Exported Types
CAN

Data Structures

struct | CAN_InitTypeDef
CAN init structure definition. More...
struct | CAN_FilterConfTypeDef
CAN filter configuration structure definition. More...
struct | CanTxMsgTypeDef
CAN Tx message structure definition. More...
struct | CanRxMsgTypeDef
CAN Rx message structure definition. More...
struct | CAN_HandleTypeDef
CAN handle Structure definition. More...

Enumerations

enum HAL_CAN_StateTypeDef {
HAL_CAN_STATE_RESET = 0x00U, HAL_CAN_STATE_READY = 0x01U, HAL_CAN_STATE_BUSY = 0x02U, HAL_CAN_STATE_BUSY_TX = 0x12U,
HAL_CAN_STATE_BUSY_RX0 = 0x22U, HAL_CAN_STATE_BUSY_RX1 = 0x32U, HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U,
HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, HAL_CAN_STATE_TIMEOUT = 0x03U, HAL_CAN_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_CAN_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_CAN_STATE_RESET

CAN not yet initialized or disabled

HAL_CAN_STATE_READY

CAN initialized and ready for use

HAL_CAN_STATE_BUSY

CAN process is ongoing

HAL_CAN_STATE_BUSY_TX

CAN process is ongoing

HAL_CAN_STATE_BUSY_RX0

CAN process is ongoing

HAL_CAN_STATE_BUSY_RX1

CAN process is ongoing

HAL_CAN_STATE_BUSY_TX_RX0

CAN process is ongoing

HAL_CAN_STATE_BUSY_TX_RX1

CAN process is ongoing

HAL_CAN_STATE_BUSY_RX0_RX1

CAN process is ongoing

HAL_CAN_STATE_BUSY_TX_RX0_RX1

CAN process is ongoing

HAL_CAN_STATE_TIMEOUT

CAN in Timeout state

HAL_CAN_STATE_ERROR

CAN error state

Definition at line 68 of file stm32f3xx_hal_can.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CAN_InitTypeDef Struct Reference
CAN Exported Types

CAN init structure definition. More...

#include <stm32f3xx_hal_can.h>

Data Fields

uint32_t | Prescaler
uint32_t | Mode
uint32_t | SJW
uint32_t | BS1
uint32_t | BS2
uint32_t | TTCM
uint32_t | ABOM
uint32_t | AWUM
uint32_t | NART
uint32_t | RFLM
uint32_t | TXFP

Detailed Description

CAN init structure definition.

Definition at line 88 of file stm32f3xx_hal_can.h.

Field Documentation

uint32_t CAN_InitTypeDef::ABOM

Enable or disable the automatic bus-off management. This parameter can be set to ENABLE or DISABLE.

Definition at line 110 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::AWUM

Enable or disable the automatic wake-up mode. This parameter can be set to ENABLE or DISABLE.

Definition at line 113 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::BS1

Specifies the number of time quanta in Bit Segment 1. This parameter can be a value of CAN Time Quantum in Bit Segment 1

Definition at line 101 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::BS2

Specifies the number of time quanta in Bit Segment 2. This parameter can be a value of CAN Time Quantum in Bit Segment 2

Definition at line 104 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::Mode

Specifies the CAN operating mode. This parameter can be a value of CAN Operating Mode

Definition at line 93 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::NART

Enable or disable the non-automatic retransmission mode. This parameter can be set to ENABLE or DISABLE.

Definition at line 116 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::Prescaler

Specifies the length of a time quantum. This parameter must be a number between Min_Data = 1 and Max_Data = 1024.

Definition at line 90 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::RFLM

Enable or disable the Receive FIFO Locked mode. This parameter can be set to ENABLE or DISABLE.

Definition at line 119 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::SJW

Specifies the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. This parameter can be a value of CAN Synchronization Jump Width

Definition at line 96 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::TTCM

Enable or disable the time triggered communication mode. This parameter can be set to ENABLE or DISABLE.

Definition at line 107 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::TXFP

Enable or disable the transmit FIFO priority. This parameter can be set to ENABLE or DISABLE.

Definition at line 122 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_can.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN_FilterConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CAN_FilterConfTypeDef Struct Reference
CAN Exported Types

CAN filter configuration structure definition. More...

#include <stm32f3xx_hal_can.h>

Data Fields

uint32_t | FilterIdHigh
uint32_t | FilterIdLow
uint32_t | FilterMaskIdHigh
uint32_t | FilterMaskIdLow
uint32_t | FilterFIFOAssignment
uint32_t | FilterNumber
uint32_t | FilterMode
uint32_t | FilterScale
uint32_t | FilterActivation
uint32_t | BankNumber

Detailed Description

CAN filter configuration structure definition.

Definition at line 129 of file stm32f3xx_hal_can.h.

Field Documentation

uint32_t CAN_FilterConfTypeDef::BankNumber

Select the start slave bank filter F3 devices don't support CAN2 interface (Slave). Therefore this parameter is meaningless but it has been kept for compatibility accross STM32 families

Definition at line 164 of file stm32f3xx_hal_can.h.

uint32_t CAN_FilterConfTypeDef::FilterActivation

Enable or disable the filter. This parameter can be set to ENABLE or DISABLE.

Definition at line 161 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterFIFOAssignment

Specifies the FIFO (0 or 1U) which will be assigned to the filter. This parameter can be a value of CAN Filter FIFO

Definition at line 149 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterIdHigh

Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 131 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterIdLow

Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 135 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterMaskIdHigh

Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 139 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterMaskIdLow

Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 144 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterMode

Specifies the filter mode to be initialized. This parameter can be a value of CAN Filter Mode

Definition at line 155 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterNumber

Specifies the filter which will be initialized. This parameter must be a number between Min_Data = 0 and Max_Data = 27.

Definition at line 152 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterScale

Specifies the filter scale. This parameter can be a value of CAN Filter Scale

Definition at line 158 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_can.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CanTxMsgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CanTxMsgTypeDef Struct Reference
CAN Exported Types

CAN Tx message structure definition. More...

#include <stm32f3xx_hal_can.h>

Data Fields

uint32_t | StdId
uint32_t | ExtId
uint32_t | IDE
uint32_t | RTR
uint32_t | DLC
uint8_t | Data [8]

Detailed Description

CAN Tx message structure definition.

Definition at line 173 of file stm32f3xx_hal_can.h.

Field Documentation

uint8_t CanTxMsgTypeDef::Data[8]

Contains the data to be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF.

Definition at line 190 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::DLC

Specifies the length of the frame that will be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 8.

Definition at line 187 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::ExtId

Specifies the extended identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF.

Definition at line 178 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::IDE

Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of CAN Identifier Type

Definition at line 181 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::RTR

Specifies the type of frame for the message that will be transmitted. This parameter can be a value of CAN Remote Transmission Request

Definition at line 184 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::StdId

Specifies the standard identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF.

Definition at line 175 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_can.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CanRxMsgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CanRxMsgTypeDef Struct Reference
CAN Exported Types

CAN Rx message structure definition. More...

#include <stm32f3xx_hal_can.h>

Data Fields

uint32_t | StdId
uint32_t | ExtId
uint32_t | IDE
uint32_t | RTR
uint32_t | DLC
uint8_t | Data [8]
uint32_t | FMI
uint32_t | FIFONumber

Detailed Description

CAN Rx message structure definition.

Definition at line 198 of file stm32f3xx_hal_can.h.

Field Documentation

uint8_t CanRxMsgTypeDef::Data[8]

Contains the data to be received. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF.

Definition at line 215 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::DLC

Specifies the length of the frame that will be received. This parameter must be a number between Min_Data = 0 and Max_Data = 8.

Definition at line 212 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::ExtId

Specifies the extended identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF.

Definition at line 203 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::FIFONumber

Specifies the receive FIFO number. This parameter can be CAN_FIFO0 or CAN_FIFO1

Definition at line 221 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::FMI

Specifies the index of the filter the message stored in the mailbox passes through. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF.

Definition at line 218 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::IDE

Specifies the type of identifier for the message that will be received. This parameter can be a value of CAN Identifier Type

Definition at line 206 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::RTR

Specifies the type of frame for the received message. This parameter can be a value of CAN Remote Transmission Request

Definition at line 209 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::StdId

Specifies the standard identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF.

Definition at line 200 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_can.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CAN_HandleTypeDef Struct Reference
CAN Exported Types

CAN handle Structure definition. More...

#include <stm32f3xx_hal_can.h>

Data Fields

CAN_TypeDef * | Instance
CAN_InitTypeDef Init
CanTxMsgTypeDef * pTxMsg
CanRxMsgTypeDef * pRxMsg
CanRxMsgTypeDef * pRx1Msg
HAL_LockTypeDef | Lock
__IO HAL_CAN_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

CAN handle Structure definition.

Definition at line 229 of file stm32f3xx_hal_can.h.

Field Documentation

__IO uint32_t CAN_HandleTypeDef::ErrorCode

CAN Error code This parameter can be a value of CAN Error Code

Definition at line 245 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_GetError(), HAL_CAN_Init(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

CAN_InitTypeDef CAN_HandleTypeDef::Init

CAN required parameters

Definition at line 233 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

CAN_TypeDef* CAN_HandleTypeDef::Instance

Register base address

Definition at line 231 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_ConfigFilter(), HAL_CAN_DeInit(), HAL_CAN_Init(), HAL_CAN_IRQHandler(), HAL_CAN_Receive(), HAL_CAN_Sleep(), HAL_CAN_Transmit(), HAL_CAN_Transmit_IT(), and HAL_CAN_WakeUp().

HAL_LockTypeDef CAN_HandleTypeDef::Lock

CAN locking object

Definition at line 241 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

CanRxMsgTypeDef* CAN_HandleTypeDef::pRx1Msg

Pointer to reception structure for RX FIFO1 msg

Definition at line 239 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

CanRxMsgTypeDef* CAN_HandleTypeDef::pRxMsg

Pointer to reception structure for RX FIFO0 msg

Definition at line 237 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

CanTxMsgTypeDef* CAN_HandleTypeDef::pTxMsg

Pointer to transmit structure

Definition at line 235 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

__IO HAL_CAN_StateTypeDef CAN_HandleTypeDef::State

CAN communication state

Definition at line 243 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_DeInit(), HAL_CAN_GetState(), HAL_CAN_Init(), HAL_CAN_IRQHandler(), HAL_CAN_Receive(), HAL_CAN_Receive_IT(), HAL_CAN_Sleep(), HAL_CAN_Transmit(), HAL_CAN_Transmit_IT(), and HAL_CAN_WakeUp().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_can.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Error Code

Defines
CAN Error Code
CAN Exported Constants

Defines

#define | HAL_CAN_ERROR_NONE (0x00000000U)
#define | HAL_CAN_ERROR_EWG (0x00000001U)
#define | HAL_CAN_ERROR_EPV (0x00000002U)
#define | HAL_CAN_ERROR_BOF (0x00000004U)
#define | HAL_CAN_ERROR_STF (0x00000008U)
#define | HAL_CAN_ERROR_FOR (0x00000010U)
#define | HAL_CAN_ERROR_ACK (0x00000020U)
#define | HAL_CAN_ERROR_BR (0x00000040U)
#define | HAL_CAN_ERROR_BD (0x00000080U)
#define | HAL_CAN_ERROR_CRC (0x00000100U)
#define | HAL_CAN_ERROR_FOV0 (0x00000200U)
#define | HAL_CAN_ERROR_FOV1 (0x00000400U)
#define | HAL_CAN_ERROR_TXFAIL (0x00000800U)

Define Documentation

#define HAL_CAN_ERROR_ACK (0x00000020U)

Acknowledgment error

Definition at line 268 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_BD (0x00000080U)

LEC dominant

Definition at line 270 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_BOF (0x00000004U)

BOF error

Definition at line 265 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_BR (0x00000040U)

Bit recessive

Definition at line 269 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_CRC (0x00000100U)

LEC transfer error

Definition at line 271 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_EPV (0x00000002U)

EPV error

Definition at line 264 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_EWG (0x00000001U)

EWG error

Definition at line 263 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_FOR (0x00000010U)

Form error

Definition at line 267 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_FOV0 (0x00000200U)

FIFO0 overrun error

Definition at line 272 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_FOV1 (0x00000400U)

FIFO1 overrun error

Definition at line 273 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_NONE (0x00000000U)

No error

Definition at line 262 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define HAL_CAN_ERROR_STF (0x00000008U)

Stuff error

Definition at line 266 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_TXFAIL (0x00000800U)

Transmit failure

Definition at line 274 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN InitStatus

Defines
CAN InitStatus
CAN Exported Constants

Defines

#define | CAN_INITSTATUS_FAILED (0x00000000U)
#define | CAN_INITSTATUS_SUCCESS (0x00000001U)

Define Documentation

#define CAN_INITSTATUS_FAILED (0x00000000U)

CAN initialization failed

Definition at line 282 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define CAN_INITSTATUS_SUCCESS (0x00000001U)

CAN initialization OK

Definition at line 283 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Operating Mode

Defines
CAN Operating Mode
CAN Exported Constants

Defines

#define | CAN_MODE_NORMAL (0x00000000U)
#define | CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM)
#define | CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM)
#define | CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))

Define Documentation

#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM)

Loopback mode

Definition at line 292 of file stm32f3xx_hal_can.h.

#define CAN_MODE_NORMAL (0x00000000U)

Normal mode

Definition at line 291 of file stm32f3xx_hal_can.h.

#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM)

Silent mode

Definition at line 293 of file stm32f3xx_hal_can.h.

#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))

Loopback combined with silent mode

Definition at line 294 of file stm32f3xx_hal_can.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Synchronization Jump Width

Defines
CAN Synchronization Jump Width
CAN Exported Constants

Defines

#define | CAN_SJW_1TQ (0x00000000U)
#define | CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0)
#define | CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1)
#define | CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW)

Define Documentation

#define CAN_SJW_1TQ (0x00000000U)

1 time quantum

Definition at line 303 of file stm32f3xx_hal_can.h.

#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0)

2 time quantum

Definition at line 304 of file stm32f3xx_hal_can.h.

#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1)

3 time quantum

Definition at line 305 of file stm32f3xx_hal_can.h.

#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW)

4 time quantum

Definition at line 306 of file stm32f3xx_hal_can.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Time Quantum in Bit Segment 1

Defines
CAN Time Quantum in Bit Segment 1
CAN Exported Constants

Defines

#define | CAN_BS1_1TQ (0x00000000U)
#define | CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0)
#define | CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1)
#define | CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2)
#define | CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
#define | CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
#define | CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3)
#define | CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))
#define | CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))
#define | CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))
#define | CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
#define | CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
#define | CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1)

Define Documentation

#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))

10 time quantum

Definition at line 323 of file stm32f3xx_hal_can.h.

#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))

11 time quantum

Definition at line 324 of file stm32f3xx_hal_can.h.

#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))

12 time quantum

Definition at line 325 of file stm32f3xx_hal_can.h.

#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))

13 time quantum

Definition at line 326 of file stm32f3xx_hal_can.h.

#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))

14 time quantum

Definition at line 327 of file stm32f3xx_hal_can.h.

#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))

15 time quantum

Definition at line 328 of file stm32f3xx_hal_can.h.

#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1)

16 time quantum

Definition at line 329 of file stm32f3xx_hal_can.h.

#define CAN_BS1_1TQ (0x00000000U)

1 time quantum

Definition at line 314 of file stm32f3xx_hal_can.h.

#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0)

2 time quantum

Definition at line 315 of file stm32f3xx_hal_can.h.

#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1)

3 time quantum

Definition at line 316 of file stm32f3xx_hal_can.h.

#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))

4 time quantum

Definition at line 317 of file stm32f3xx_hal_can.h.

#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2)

5 time quantum

Definition at line 318 of file stm32f3xx_hal_can.h.

#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))

6 time quantum

Definition at line 319 of file stm32f3xx_hal_can.h.

#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))

7 time quantum

Definition at line 320 of file stm32f3xx_hal_can.h.

#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))

8 time quantum

Definition at line 321 of file stm32f3xx_hal_can.h.

#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3)

9 time quantum

Definition at line 322 of file stm32f3xx_hal_can.h.

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STM32F373xC HAL User Manual: CAN Time Quantum in Bit Segment 2

Defines
CAN Time Quantum in Bit Segment 2
CAN Exported Constants

Defines

#define | CAN_BS2_1TQ (0x00000000U)
#define | CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0)
#define | CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1)
#define | CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))
#define | CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2)
#define | CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))
#define | CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))
#define | CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2)

Define Documentation

#define CAN_BS2_1TQ (0x00000000U)

1 time quantum

Definition at line 337 of file stm32f3xx_hal_can.h.

#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0)

2 time quantum

Definition at line 338 of file stm32f3xx_hal_can.h.

#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1)

3 time quantum

Definition at line 339 of file stm32f3xx_hal_can.h.

#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))

4 time quantum

Definition at line 340 of file stm32f3xx_hal_can.h.

#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2)

5 time quantum

Definition at line 341 of file stm32f3xx_hal_can.h.

#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))

6 time quantum

Definition at line 342 of file stm32f3xx_hal_can.h.

#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))

7 time quantum

Definition at line 343 of file stm32f3xx_hal_can.h.

#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2)

8 time quantum

Definition at line 344 of file stm32f3xx_hal_can.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Filter Mode

Defines
CAN Filter Mode
CAN Exported Constants

Defines

#define | CAN_FILTERMODE_IDMASK ((uint8_t)0x00U)
#define | CAN_FILTERMODE_IDLIST ((uint8_t)0x01U)

Define Documentation

#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U)

Identifier list mode

Definition at line 353 of file stm32f3xx_hal_can.h.

#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U)

Identifier mask mode

Definition at line 352 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Filter Scale

Defines
CAN Filter Scale
CAN Exported Constants

Defines

#define | CAN_FILTERSCALE_16BIT ((uint8_t)0x00U)
#define | CAN_FILTERSCALE_32BIT ((uint8_t)0x01U)

Define Documentation

#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U)

Two 16-bit filters

Definition at line 361 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U)

One 32-bit filter

Definition at line 362 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

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STM32F373xC HAL User Manual: CAN Filter FIFO

Defines
CAN Filter FIFO
CAN Exported Constants

Defines

#define | CAN_FILTER_FIFO0 ((uint8_t)0x00U)
#define | CAN_FILTER_FIFO1 ((uint8_t)0x01U)

Define Documentation

#define CAN_FILTER_FIFO0 ((uint8_t)0x00U)

Filter FIFO 0 assignment for filter x

Definition at line 370 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define CAN_FILTER_FIFO1 ((uint8_t)0x01U)

Filter FIFO 1 assignment for filter x

Definition at line 371 of file stm32f3xx_hal_can.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Identifier Type

Defines
CAN Identifier Type
CAN Exported Constants

Defines

#define | CAN_ID_STD (0x00000000U)
#define | CAN_ID_EXT (0x00000004U)

Define Documentation

#define CAN_ID_EXT (0x00000004U)

Extended Id

Definition at line 380 of file stm32f3xx_hal_can.h.

#define CAN_ID_STD (0x00000000U)

Standard Id

Definition at line 379 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_Receive(), HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Remote Transmission Request

Defines
CAN Remote Transmission Request
CAN Exported Constants

Defines

#define | CAN_RTR_DATA (0x00000000U)
#define | CAN_RTR_REMOTE (0x00000002U)

Define Documentation

#define CAN_RTR_DATA (0x00000000U)

Data frame

Definition at line 388 of file stm32f3xx_hal_can.h.

#define CAN_RTR_REMOTE (0x00000002U)

Remote frame

Definition at line 389 of file stm32f3xx_hal_can.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Receive FIFO Number

Defines
CAN Receive FIFO Number
CAN Exported Constants

Defines

#define | CAN_FIFO0 ((uint8_t)0x00U)
#define | CAN_FIFO1 ((uint8_t)0x01U)

Define Documentation

#define CAN_FIFO0 ((uint8_t)0x00U)

CAN FIFO 0 used to receive

Definition at line 397 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive(), and HAL_CAN_Receive_IT().

#define CAN_FIFO1 ((uint8_t)0x01U)

CAN FIFO 1 used to receive

Definition at line 398 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive(), and HAL_CAN_Receive_IT().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Flags

Defines
CAN Flags
CAN Exported Constants

Defines

#define | CAN_FLAG_RQCP0 (0x00000500U)
#define | CAN_FLAG_RQCP1 (0x00000508U)
#define | CAN_FLAG_RQCP2 (0x00000510U)
#define | CAN_FLAG_TXOK0 (0x00000501U)
#define | CAN_FLAG_TXOK1 (0x00000509U)
#define | CAN_FLAG_TXOK2 (0x00000511U)
#define | CAN_FLAG_TME0 (0x0000051AU)
#define | CAN_FLAG_TME1 (0x0000051BU)
#define | CAN_FLAG_TME2 (0x0000051CU)
#define | CAN_FLAG_FF0 (0x00000203U)
#define | CAN_FLAG_FOV0 (0x00000204U)
#define | CAN_FLAG_FF1 (0x00000403U)
#define | CAN_FLAG_FOV1 (0x00000404U)
#define | CAN_FLAG_INAK (0x00000100U)
#define | CAN_FLAG_SLAK (0x00000101U)
#define | CAN_FLAG_ERRI (0x00000102U)
#define | CAN_FLAG_WKU (0x00000103U)
#define | CAN_FLAG_SLAKI (0x00000104U)
#define | CAN_FLAG_EWG (0x00000300U)
#define | CAN_FLAG_EPV (0x00000301U)
#define | CAN_FLAG_BOF (0x00000302U)

Define Documentation

#define CAN_FLAG_BOF (0x00000302U)

Bus-Off flag

Definition at line 441 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_EPV (0x00000301U)

Error passive flag

Definition at line 440 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_ERRI (0x00000102U)

Error flag

Definition at line 432 of file stm32f3xx_hal_can.h.

#define CAN_FLAG_EWG (0x00000300U)

Error warning flag

Definition at line 439 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_FF0 (0x00000203U)

FIFO 0 Full flag

Definition at line 423 of file stm32f3xx_hal_can.h.

#define CAN_FLAG_FF1 (0x00000403U)

FIFO 1 Full flag

Definition at line 426 of file stm32f3xx_hal_can.h.

#define CAN_FLAG_FOV0 (0x00000204U)

FIFO 0 Overrun flag

Definition at line 424 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_FOV1 (0x00000404U)

FIFO 1 Overrun flag

Definition at line 427 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_INAK (0x00000100U)

Initialization acknowledge flag

Definition at line 430 of file stm32f3xx_hal_can.h.

#define CAN_FLAG_RQCP0 (0x00000500U)

Request MailBox0 flag

Definition at line 412 of file stm32f3xx_hal_can.h.

#define CAN_FLAG_RQCP1 (0x00000508U)

Request MailBox1 flag

Definition at line 413 of file stm32f3xx_hal_can.h.

#define CAN_FLAG_RQCP2 (0x00000510U)

Request MailBox2 flag

Definition at line 414 of file stm32f3xx_hal_can.h.

#define CAN_FLAG_SLAK (0x00000101U)

Sleep acknowledge flag

Definition at line 431 of file stm32f3xx_hal_can.h.

#define CAN_FLAG_SLAKI (0x00000104U)

Sleep acknowledge flag

Definition at line 434 of file stm32f3xx_hal_can.h.

#define CAN_FLAG_TME0 (0x0000051AU)

Transmit mailbox 0 empty flag

Definition at line 418 of file stm32f3xx_hal_can.h.

#define CAN_FLAG_TME1 (0x0000051BU)

Transmit mailbox 0 empty flag

Definition at line 419 of file stm32f3xx_hal_can.h.

#define CAN_FLAG_TME2 (0x0000051CU)

Transmit mailbox 0 empty flag

Definition at line 420 of file stm32f3xx_hal_can.h.

#define CAN_FLAG_TXOK0 (0x00000501U)

Transmission OK MailBox0 flag

Definition at line 415 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_TXOK1 (0x00000509U)

Transmission OK MailBox1 flag

Definition at line 416 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_TXOK2 (0x00000511U)

Transmission OK MailBox2 flag

Definition at line 417 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_WKU (0x00000103U)

Wake up flag

Definition at line 433 of file stm32f3xx_hal_can.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Interrupts

Defines
CAN Interrupts
CAN Exported Constants

Defines

#define | CAN_IT_TME ((uint32_t)CAN_IER_TMEIE)
#define | CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0)
#define | CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0)
#define | CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0)
#define | CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1)
#define | CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1)
#define | CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1)
#define | CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE)
#define | CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE)
#define | CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE)
#define | CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE)
#define | CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE)
#define | CAN_IT_LEC ((uint32_t)CAN_IER_LECIE)
#define | CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE)

Define Documentation

#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE)

Bus-off interrupt

Definition at line 468 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE)

Error passive interrupt

Definition at line 467 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE)

Error Interrupt

Definition at line 470 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE)

Error warning interrupt

Definition at line 466 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0)

FIFO 0 full interrupt

Definition at line 455 of file stm32f3xx_hal_can.h.

#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1)

FIFO 1 full interrupt

Definition at line 458 of file stm32f3xx_hal_can.h.

#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0)

FIFO 0 message pending interrupt

Definition at line 454 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Receive_IT().

#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1)

FIFO 1 message pending interrupt

Definition at line 457 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Receive_IT().

#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0)

FIFO 0 overrun interrupt

Definition at line 456 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Receive_IT().

#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1)

FIFO 1 overrun interrupt

Definition at line 459 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Receive_IT().

#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE)

Last error code interrupt

Definition at line 469 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE)

Sleep acknowledge interrupt

Definition at line 463 of file stm32f3xx_hal_can.h.

#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE)

Transmit mailbox empty interrupt

Definition at line 451 of file stm32f3xx_hal_can.h.

Referenced by CAN_Transmit_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Transmit_IT().

#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE)

Wake-up interrupt

Definition at line 462 of file stm32f3xx_hal_can.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Mailboxes

Defines
CAN Mailboxes
CAN Exported Constants

Defines

#define | CAN_TXMAILBOX_0 ((uint8_t)0x00U)
#define | CAN_TXMAILBOX_1 ((uint8_t)0x01U)
#define | CAN_TXMAILBOX_2 ((uint8_t)0x02U)

Define Documentation

#define CAN_TXMAILBOX_0 ((uint8_t)0x00U)

Definition at line 480 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler(), HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define CAN_TXMAILBOX_1 ((uint8_t)0x01U)

Definition at line 481 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler(), HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define CAN_TXMAILBOX_2 ((uint8_t)0x02U)

Definition at line 482 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler(), HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Exported Macros

Defines
CAN Exported Macros
CAN

Defines

#define | __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
Reset CAN handle state.
#define | __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable the specified CAN interrupts.
#define | __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable the specified CAN interrupts.
#define | __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__)
Return the number of pending received messages.
#define | __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__)
Check whether the specified CAN flag is set or not.
#define | __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the specified CAN pending flag.
#define | __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check if the specified CAN interrupt source is enabled or disabled.
#define | __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)
Check the transmission status of a CAN Frame.
#define | __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__)
Release the specified receive FIFO.
#define | __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)
Cancel a transmit request.
#define | __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__)
Enable or disables the DBG Freeze for CAN.

Define Documentation

#define __HAL_CAN_CANCEL_TRANSMIT | ( | __HANDLE__,
 |  | __TRANSMITMAILBOX__
 | ) |
Value:
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
 ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))

Cancel a transmit request.

Parameters:
__HANDLE__ | specifies the CAN Handle.
__TRANSMITMAILBOX__ | the number of the mailbox that is used for transmission.
Return values:
None

Definition at line 631 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Transmit().

#define __HAL_CAN_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)

Clear the specified CAN pending flag.

Parameters:
__HANDLE__ specifies the CAN Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • CAN_TSR_RQCP0: Request MailBox0 Flag
  • CAN_TSR_RQCP1: Request MailBox1 Flag
  • CAN_TSR_RQCP2: Request MailBox2 Flag
  • CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
  • CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
  • CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
  • CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
  • CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
  • CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
  • CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
  • CAN_FLAG_FF0: FIFO 0 Full Flag
  • CAN_FLAG_FOV0: FIFO 0 Overrun Flag
  • CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
  • CAN_FLAG_FF1: FIFO 1 Full Flag
  • CAN_FLAG_FOV1: FIFO 1 Overrun Flag
  • CAN_FLAG_WKU: Wake up Flag
  • CAN_FLAG_SLAKI: Sleep acknowledge Flag
  • CAN_FLAG_EWG: Error Warning Flag
  • CAN_FLAG_EPV: Error Passive Flag
  • CAN_FLAG_BOF: Bus-Off Flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 587 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define __HAL_CAN_DBG_FREEZE | ( | __HANDLE__,
 |  | __NEWSTATE__
 | ) |
Value:
(((__NEWSTATE__) == ENABLE)? \
((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))

Enable or disables the DBG Freeze for CAN.

Parameters:
__HANDLE__ | specifies the CAN Handle.
__NEWSTATE__ | new state of the CAN peripheral. This parameter can be: ENABLE (CAN reception/transmission is frozen during debug. Reception FIFOs can still be accessed/controlled normally) or DISABLE (CAN is working during debug).
Return values:
None

Definition at line 645 of file stm32f3xx_hal_can.h.

#define __HAL_CAN_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))

Disable the specified CAN interrupts.

Parameters:
__HANDLE__ | CAN handle.
__INTERRUPT__ | CAN Interrupt
Return values:
None

Definition at line 516 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), and HAL_CAN_IRQHandler().

#define __HAL_CAN_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))

Enable the specified CAN interrupts.

Parameters:
__HANDLE__ | CAN handle.
__INTERRUPT__ | CAN Interrupt
Return values:
None

Definition at line 508 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define __HAL_CAN_FIFO_RELEASE | ( | __HANDLE__,
 |  | __FIFONUMBER__
 | ) |
Value:
(((__FIFONUMBER__) == CAN_FIFO0)? \
((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))

Release the specified receive FIFO.

Parameters:
__HANDLE__ | CAN handle.
__FIFONUMBER__ | Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
Return values:
None

Definition at line 622 of file stm32f3xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

#define __HAL_CAN_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))

Check whether the specified CAN flag is set or not.

Parameters:
__HANDLE__ specifies the CAN Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • CAN_TSR_RQCP0: Request MailBox0 Flag
  • CAN_TSR_RQCP1: Request MailBox1 Flag
  • CAN_TSR_RQCP2: Request MailBox2 Flag
  • CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
  • CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
  • CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
  • CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
  • CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
  • CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
  • CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
  • CAN_FLAG_FF0: FIFO 0 Full Flag
  • CAN_FLAG_FOV0: FIFO 0 Overrun Flag
  • CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
  • CAN_FLAG_FF1: FIFO 1 Full Flag
  • CAN_FLAG_FOV1: FIFO 1 Overrun Flag
  • CAN_FLAG_WKU: Wake up Flag
  • CAN_FLAG_SLAK: Sleep acknowledge Flag
  • CAN_FLAG_SLAKI: Sleep acknowledge Flag
  • CAN_FLAG_EWG: Error Warning Flag
  • CAN_FLAG_EPV: Error Passive Flag
  • CAN_FLAG_BOF: Bus-Off Flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 554 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define __HAL_CAN_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check if the specified CAN interrupt source is enabled or disabled.

Parameters:
__HANDLE__ specifies the CAN Handle.
__INTERRUPT__ specifies the CAN interrupt source to check. This parameter can be one of the following values:
  • CAN_IT_TME: Transmit mailbox empty interrupt enable
  • CAN_IT_FMP0: FIFO0 message pending interrupt enablev
  • CAN_IT_FMP1: FIFO1 message pending interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 603 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define __HAL_CAN_MSG_PENDING | ( | __HANDLE__,
 |  | __FIFONUMBER__
 | ) |
Value:
(((__FIFONUMBER__) == CAN_FIFO0)? \
((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U)))

Return the number of pending received messages.

Parameters:
__HANDLE__ | CAN handle.
__FIFONUMBER__ | Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
Return values:
The number of pending message.

Definition at line 524 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler(), and HAL_CAN_Receive().

#define __HAL_CAN_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)

Reset CAN handle state.

Parameters:
__HANDLE__ CAN handle.
Return values:
None

Definition at line 500 of file stm32f3xx_hal_can.h.

#define __HAL_CAN_TRANSMIT_STATUS | ( | __HANDLE__,
 |  | __TRANSMITMAILBOX__
 | ) |
Value:
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
 ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))

Check the transmission status of a CAN Frame.

Parameters:
__HANDLE__ | CAN handle.
__TRANSMITMAILBOX__ | the number of the mailbox that is used for transmission.
Return values:
The new status of transmission (TRUE or FALSE).

Definition at line 611 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler(), and HAL_CAN_Transmit().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Private Types

CAN Private Types
CAN
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Private Variables

CAN Private Variables
CAN
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Private Macros

Defines
CAN Private Macros
CAN

Defines

#define | IS_CAN_MODE(MODE)
#define | IS_CAN_SJW(SJW)
#define | IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
#define | IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
#define | IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
#define | IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
#define | IS_CAN_FILTER_MODE(MODE)
#define | IS_CAN_FILTER_SCALE(SCALE)
#define | IS_CAN_FILTER_FIFO(FIFO)
#define | IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
#define | IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
#define | IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU))
#define | IS_CAN_EXTID(EXTID) ((EXTID) <= (0x1FFFFFFFU))
#define | IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U))
#define | IS_CAN_IDTYPE(IDTYPE)
#define | IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
#define | IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
#define | IS_CAN_IT(IT)
#define | IS_CAN_CLEAR_IT(IT)

Define Documentation

#define IS_CAN_BANKNUMBER ( BANKNUMBER ) ((BANKNUMBER) <= 28U)

Definition at line 764 of file stm32f3xx_hal_can.h.

#define IS_CAN_BS1 ( BS1 ) ((BS1) <= CAN_BS1_16TQ)

Definition at line 747 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_BS2 ( BS2 ) ((BS2) <= CAN_BS2_8TQ)

Definition at line 749 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_CLEAR_IT ( IT )
Value:
(((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
                             ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
                             ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
                             ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
                             ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
                             ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))

Definition at line 786 of file stm32f3xx_hal_can.h.

#define IS_CAN_DLC ( DLC ) ((DLC) <= ((uint8_t)0x08U))

Definition at line 769 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_EXTID ( EXTID ) ((EXTID) <= (0x1FFFFFFFU))

Definition at line 768 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_FIFO ( FIFO ) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))

Definition at line 776 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Receive(), and HAL_CAN_Receive_IT().

#define IS_CAN_FILTER_FIFO ( FIFO )
Value:
(((FIFO) == CAN_FILTER_FIFO0) || \
                                  ((FIFO) == CAN_FILTER_FIFO1))

Definition at line 761 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_FILTER_MODE ( MODE )
Value:
(((MODE) == CAN_FILTERMODE_IDMASK) || \
                                  ((MODE) == CAN_FILTERMODE_IDLIST))

Definition at line 755 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_FILTER_NUMBER ( NUMBER ) ((NUMBER) <= 27U)

Definition at line 753 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_FILTER_SCALE ( SCALE )
Value:
(((SCALE) == CAN_FILTERSCALE_16BIT) || \
                                    ((SCALE) == CAN_FILTERSCALE_32BIT))

Definition at line 758 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_IDTYPE ( IDTYPE )
Value:
(((IDTYPE) == CAN_ID_STD) || \
                                ((IDTYPE) == CAN_ID_EXT))

Definition at line 771 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_IT ( IT )
Value:
(((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
                             ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
                             ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
                             ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
                             ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
                             ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
                             ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))

Definition at line 778 of file stm32f3xx_hal_can.h.

#define IS_CAN_MODE ( MODE )
Value:
(((MODE) == CAN_MODE_NORMAL) || \
                           ((MODE) == CAN_MODE_LOOPBACK)|| \
                           ((MODE) == CAN_MODE_SILENT) || \
                           ((MODE) == CAN_MODE_SILENT_LOOPBACK))

Definition at line 739 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_PRESCALER ( PRESCALER ) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))

Definition at line 751 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_RTR ( RTR ) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))

Definition at line 774 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_SJW ( SJW )
Value:
(((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
                         ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))

Definition at line 744 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_STDID ( STDID ) ((STDID) <= (0x7FFU))

Definition at line 767 of file stm32f3xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_TRANSMITMAILBOX ( TRANSMITMAILBOX ) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))

Definition at line 766 of file stm32f3xx_hal_can.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC Private Constants

CEC Private Constants
CEC
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC Private Functions

CEC Private Functions
CEC
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CEC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CEC_Init (CEC_HandleTypeDef *hcec)
Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_CEC_DeInit (CEC_HandleTypeDef *hcec)
DeInitializes the CEC peripheral.
HAL_StatusTypeDef | HAL_CEC_SetDeviceAddress (CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
Initializes the Own Address of the CEC device.
__weak void | HAL_CEC_MspInit (CEC_HandleTypeDef *hcec)
CEC MSP Init.
__weak void | HAL_CEC_MspDeInit (CEC_HandleTypeDef *hcec)
CEC MSP DeInit.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the CEC
      (+) The following parameters need to be configured:
        (++) SignalFreeTime
        (++) Tolerance
        (++) BRERxStop                 (RX stopped or not upon Bit Rising Error)
        (++) BREErrorBitGen            (Error-Bit generation in case of Bit Rising Error)
        (++) LBPEErrorBitGen           (Error-Bit generation in case of Long Bit Period Error)
        (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
        (++) SignalFreeTimeOption      (SFT Timer start definition)
        (++) OwnAddress                (CEC device address)
        (++) ListenMode

Function Documentation

HAL_StatusTypeDef HAL_CEC_DeInit ( CEC_HandleTypeDef * hcec )

DeInitializes the CEC peripheral.

Parameters:
hcec CEC handle
Return values:
HAL status

Definition at line 216 of file stm32f3xx_hal_cec.c.

References __HAL_CEC_CLEAR_FLAG, __HAL_CEC_DISABLE, __HAL_CEC_DISABLE_IT, assert_param, CEC_FLAG_RXBR, CEC_FLAG_RXEND, CEC_FLAG_TXBR, CEC_FLAG_TXEND, CEC_IER_RX_ALL_ERR, CEC_IER_TX_ALL_ERR, CEC_ISR_ALL_ERROR, CEC_IT_RXBR, CEC_IT_RXEND, CEC_IT_TXBR, CEC_IT_TXEND, CEC_HandleTypeDef::ErrorCode, CEC_HandleTypeDef::gState, HAL_CEC_ERROR_NONE, HAL_CEC_MspDeInit(), HAL_CEC_STATE_BUSY, HAL_CEC_STATE_RESET, CEC_HandleTypeDef::Instance, and CEC_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_CEC_Init ( CEC_HandleTypeDef * hcec )

Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle .

Parameters:
hcec CEC handle
Return values:
HAL status

Definition at line 146 of file stm32f3xx_hal_cec.c.

References __HAL_CEC_DISABLE, __HAL_CEC_ENABLE, __HAL_CEC_ENABLE_IT, assert_param, CEC_InitTypeDef::BREErrorBitGen, CEC_InitTypeDef::BRERxStop, CEC_InitTypeDef::BroadcastMsgNoErrorBitGen, CEC_IER_RX_ALL_ERR, CEC_IER_TX_ALL_ERR, CEC_IT_RXBR, CEC_IT_RXEND, CEC_IT_TXBR, CEC_IT_TXEND, CEC_HandleTypeDef::ErrorCode, CEC_HandleTypeDef::gState, HAL_CEC_ERROR_NONE, HAL_CEC_MspInit(), HAL_CEC_STATE_BUSY, HAL_CEC_STATE_READY, HAL_CEC_STATE_RESET, CEC_HandleTypeDef::Init, CEC_HandleTypeDef::Instance, IS_CEC_BREERRORBITGEN, IS_CEC_BRERXSTOP, IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION, IS_CEC_LBPEERRORBITGEN, IS_CEC_LISTENING_MODE, IS_CEC_OWN_ADDRESS, IS_CEC_SFTOP, IS_CEC_SIGNALFREETIME, IS_CEC_TOLERANCE, CEC_InitTypeDef::LBPEErrorBitGen, CEC_InitTypeDef::ListenMode, CEC_HandleTypeDef::Lock, CEC_InitTypeDef::OwnAddress, CEC_InitTypeDef::RxBuffer, CEC_HandleTypeDef::RxState, CEC_InitTypeDef::SignalFreeTime, CEC_InitTypeDef::SignalFreeTimeOption, and CEC_InitTypeDef::Tolerance.

void HAL_CEC_MspDeInit ( CEC_HandleTypeDef * hcec )

CEC MSP DeInit.

Parameters:
hcec CEC handle
Return values:
None

Definition at line 330 of file stm32f3xx_hal_cec.c.

Referenced by HAL_CEC_DeInit().

void HAL_CEC_MspInit ( CEC_HandleTypeDef * hcec )

CEC MSP Init.

Parameters:
hcec CEC handle
Return values:
None

Definition at line 316 of file stm32f3xx_hal_cec.c.

Referenced by HAL_CEC_Init().

HAL_StatusTypeDef HAL_CEC_SetDeviceAddress | ( | CEC_HandleTypeDef * | hcec,
 |  | uint16_t | CEC_OwnAddress
 | ) |  |

Initializes the Own Address of the CEC device.

Parameters:
hcec | CEC handle
CEC_OwnAddress | The CEC own address.
Return values:
HAL status

Definition at line 270 of file stm32f3xx_hal_cec.c.

References __HAL_CEC_DISABLE, __HAL_CEC_ENABLE, assert_param, CEC_OWN_ADDRESS_NONE, CEC_HandleTypeDef::ErrorCode, CEC_HandleTypeDef::gState, HAL_CEC_ERROR_NONE, HAL_CEC_STATE_BUSY, HAL_CEC_STATE_READY, CEC_HandleTypeDef::Instance, IS_CEC_OWN_ADDRESS, and CEC_HandleTypeDef::RxState.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
CEC Exported Functions

CEC Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_CEC_Transmit_IT (CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
Send data in interrupt mode.
uint32_t | HAL_CEC_GetLastReceivedFrameSize (CEC_HandleTypeDef *hcec)
Get size of the received frame.
void | HAL_CEC_ChangeRxBuffer (CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
Change Rx Buffer.
void | HAL_CEC_IRQHandler (CEC_HandleTypeDef *hcec)
This function handles CEC interrupt requests.
__weak void | HAL_CEC_TxCpltCallback (CEC_HandleTypeDef *hcec)
Tx Transfer completed callback.
__weak void | HAL_CEC_RxCpltCallback (CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
Rx Transfer completed callback.
__weak void | HAL_CEC_ErrorCallback (CEC_HandleTypeDef *hcec)
CEC error callbacks.

Detailed Description

CEC Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the CEC data transfers.

    (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
        logical addresses (4-bit long addresses, 0x0F for broadcast messages destination)

    (#) The communication is performed using Interrupts.
           These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated CEC IRQ when using Interrupt mode.
           The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
           will be executed respectivelly at the end of the transmit or Receive process
           The HAL_CEC_ErrorCallback()user callback will be executed when a communication
           error is detected

    (#) API's with Interrupt are :
         (+) HAL_CEC_Transmit_IT()
         (+) HAL_CEC_IRQHandler()

    (#) A set of User Callbacks are provided:
         (+) HAL_CEC_TxCpltCallback()
         (+) HAL_CEC_RxCpltCallback()
         (+) HAL_CEC_ErrorCallback()

Function Documentation

void HAL_CEC_ChangeRxBuffer | ( | CEC_HandleTypeDef * | hcec,
 |  | uint8_t * | Rxbuffer
 | ) |  |

Change Rx Buffer.

Parameters:
hcec | CEC handle
Rxbuffer | Rx Buffer
Note:
This function can be called only inside the HAL_CEC_RxCpltCallback()
Return values:
Frame size

Definition at line 454 of file stm32f3xx_hal_cec.c.

References CEC_HandleTypeDef::Init, and CEC_InitTypeDef::RxBuffer.

void HAL_CEC_ErrorCallback ( CEC_HandleTypeDef * hcec )

CEC error callbacks.

Parameters:
hcec CEC handle
Return values:
None

Definition at line 599 of file stm32f3xx_hal_cec.c.

Referenced by HAL_CEC_IRQHandler().

uint32_t HAL_CEC_GetLastReceivedFrameSize ( CEC_HandleTypeDef * hcec )

Get size of the received frame.

Parameters:
hcec CEC handle
Return values:
Frame size

Definition at line 442 of file stm32f3xx_hal_cec.c.

References CEC_HandleTypeDef::RxXferSize.

void HAL_CEC_IRQHandler ( CEC_HandleTypeDef * hcec )

This function handles CEC interrupt requests.

Parameters:
hcec CEC handle
Return values:
None

Definition at line 464 of file stm32f3xx_hal_cec.c.

References __HAL_CEC_CLEAR_FLAG, __HAL_CEC_LAST_BYTE_TX_SET, CEC_FLAG_ARBLST, CEC_FLAG_LBPE, CEC_FLAG_RXBR, CEC_FLAG_RXEND, CEC_FLAG_SBPE, CEC_FLAG_TXBR, CEC_FLAG_TXEND, CEC_HandleTypeDef::ErrorCode, CEC_HandleTypeDef::gState, HAL_CEC_ERROR_ARBLST, HAL_CEC_ERROR_BRE, HAL_CEC_ERROR_NONE, HAL_CEC_ERROR_RXACKE, HAL_CEC_ERROR_RXOVR, HAL_CEC_ERROR_TXACKE, HAL_CEC_ERROR_TXERR, HAL_CEC_ERROR_TXUDR, HAL_CEC_ErrorCallback(), HAL_CEC_RxCpltCallback(), HAL_CEC_STATE_BUSY_RX, HAL_CEC_STATE_READY, HAL_CEC_TxCpltCallback(), CEC_HandleTypeDef::Init, CEC_HandleTypeDef::Instance, CEC_HandleTypeDef::pTxBuffPtr, CEC_InitTypeDef::RxBuffer, CEC_HandleTypeDef::RxState, CEC_HandleTypeDef::RxXferSize, and CEC_HandleTypeDef::TxXferCount.

void HAL_CEC_RxCpltCallback | ( | CEC_HandleTypeDef * | hcec,
 |  | uint32_t | RxFrameSize
 | ) |  |

Rx Transfer completed callback.

Parameters:
hcec | CEC handle
RxFrameSize | Size of frame
Return values:
None

Definition at line 584 of file stm32f3xx_hal_cec.c.

Referenced by HAL_CEC_IRQHandler().

HAL_StatusTypeDef HAL_CEC_Transmit_IT | ( | CEC_HandleTypeDef * | hcec,
 |  | uint8_t | InitiatorAddress,
 |  | uint8_t | DestinationAddress,
 |  | uint8_t * | pData,
 |  | uint32_t | Size
 | ) |  |

Send data in interrupt mode.

Parameters:
hcec | CEC handle
InitiatorAddress | Initiator address
DestinationAddress | destination logical address
pData | pointer to input byte data buffer
Size | amount of data to be sent in bytes (without counting the header). 0 means only the header is sent (ping operation). Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
Return values:
HAL status

Definition at line 388 of file stm32f3xx_hal_cec.c.

References __HAL_CEC_FIRST_BYTE_TX_SET, __HAL_CEC_LAST_BYTE_TX_SET, assert_param, CEC_INITIATOR_LSB_POS, CEC_HandleTypeDef::ErrorCode, CEC_HandleTypeDef::gState, HAL_CEC_ERROR_NONE, HAL_CEC_STATE_BUSY_TX, HAL_CEC_STATE_READY, CEC_HandleTypeDef::Instance, IS_CEC_ADDRESS, IS_CEC_MSGSIZE, CEC_HandleTypeDef::pTxBuffPtr, and CEC_HandleTypeDef::TxXferCount.

void HAL_CEC_TxCpltCallback ( CEC_HandleTypeDef * hcec )

Tx Transfer completed callback.

Parameters:
hcec CEC handle
Return values:
None

Definition at line 569 of file stm32f3xx_hal_cec.c.

Referenced by HAL_CEC_IRQHandler().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral Control function

Functions
Peripheral Control function
CEC Exported Functions

CEC control functions. More...

Functions

HAL_CEC_StateTypeDef | HAL_CEC_GetState (CEC_HandleTypeDef *hcec)
return the CEC state
uint32_t | HAL_CEC_GetError (CEC_HandleTypeDef *hcec)
Return the CEC error code.

Detailed Description

CEC control functions.

 ===============================================================================
                      ##### Peripheral Control function #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the CEC.
     (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
     (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.

Function Documentation

uint32_t HAL_CEC_GetError ( CEC_HandleTypeDef * hcec )

Return the CEC error code.

Parameters:
hcec pointer to a CEC_HandleTypeDef structure that contains the configuration information for the specified CEC.
Return values:
CEC Error Code

Definition at line 646 of file stm32f3xx_hal_cec.c.

References CEC_HandleTypeDef::ErrorCode.

HAL_CEC_StateTypeDef HAL_CEC_GetState ( CEC_HandleTypeDef * hcec )

return the CEC state

Parameters:
hcec pointer to a CEC_HandleTypeDef structure that contains the configuration information for the specified CEC module.
Return values:
HAL state

Definition at line 631 of file stm32f3xx_hal_cec.c.

References CEC_HandleTypeDef::gState, and CEC_HandleTypeDef::RxState.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC Exported Types

Data Structures | Enumerations
CEC Exported Types
CEC

Data Structures

struct | CEC_InitTypeDef
CEC Init Structure definition. More...
struct | CEC_HandleTypeDef
CEC handle Structure definition. More...

Enumerations

enum HAL_CEC_StateTypeDef {
HAL_CEC_STATE_RESET = 0x00U, HAL_CEC_STATE_READY = 0x20U, HAL_CEC_STATE_BUSY = 0x24U, HAL_CEC_STATE_BUSY_RX = 0x22U,
HAL_CEC_STATE_BUSY_TX = 0x21U, HAL_CEC_STATE_BUSY_RX_TX = 0x23U, HAL_CEC_STATE_ERROR = 0x60U
}
HAL CEC State structures definition. More...

Enumeration Type Documentation

enum HAL_CEC_StateTypeDef

HAL CEC State structures definition.

Note:
HAL CEC State value is a combination of 2 different substates: gState and RxState.
  • gState contains CEC state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7 (not used) x : Should be set to 0 b6 Error information 0 : No Error 1 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP initialized. HAL CEC Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
Enumerator:
HAL_CEC_STATE_RESET

Peripheral is not yet Initialized Value is allowed for gState and RxState

HAL_CEC_STATE_READY

Peripheral Initialized and ready for use Value is allowed for gState and RxState

HAL_CEC_STATE_BUSY

an internal process is ongoing Value is allowed for gState only

HAL_CEC_STATE_BUSY_RX

Data Reception process is ongoing Value is allowed for RxState only

HAL_CEC_STATE_BUSY_TX

Data Transmission process is ongoing Value is allowed for gState only

HAL_CEC_STATE_BUSY_RX_TX

an internal process is ongoing Value is allowed for gState only

HAL_CEC_STATE_ERROR

Error Value is allowed for gState only

Definition at line 167 of file stm32f3xx_hal_cec.h.

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STM32F373xC HAL User Manual: CEC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CEC_InitTypeDef Struct Reference
CEC Exported Types

CEC Init Structure definition. More...

#include <stm32f3xx_hal_cec.h>

Data Fields

uint32_t | SignalFreeTime
uint32_t | Tolerance
uint32_t | BRERxStop
uint32_t | BREErrorBitGen
uint32_t | LBPEErrorBitGen
uint32_t | BroadcastMsgNoErrorBitGen
uint32_t | SignalFreeTimeOption
uint32_t | ListenMode
uint16_t | OwnAddress
uint8_t * | RxBuffer

Detailed Description

CEC Init Structure definition.

Definition at line 64 of file stm32f3xx_hal_cec.h.

Field Documentation

uint32_t CEC_InitTypeDef::BREErrorBitGen

Set BREGEN bit CEC Error Bit Generation if Bit Rise Error reported : specifies whether or not an Error-Bit is generated on the CEC line upon Bit Rising Error detection. CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set.

Definition at line 80 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::BRERxStop

Set BRESTP bit CEC Reception Stop on Error : specifies whether or not a Bit Rising Error stops the reception. CEC_NO_RX_STOP_ON_BRE: reception is not stopped. CEC_RX_STOP_ON_BRE: reception is stopped.

Definition at line 76 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::BroadcastMsgNoErrorBitGen

Set BRDNOGEN bit CEC Error Bit Generation on Broadcast message : allows to avoid an Error-Bit generation on the CEC line upon an error detected on a broadcast message.

It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:

1U) CEC_BROADCASTERROR_ERRORBIT_GENERATION. a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. b) LBPE detection: error-bit generation on the CEC line if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.

2U) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. no error-bit generation in case neither a) nor b) are satisfied. Additionally, there is no error-bit generation in case of Short Bit Period Error detection in a broadcast message while LSTN bit is set.

Definition at line 90 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::LBPEErrorBitGen

Set LBPEGEN bit CEC Error Bit Generation if Long Bit Period Error reported : specifies whether or not an Error-Bit is generated on the CEC line upon Long Bit Period Error detection. CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. CEC_LBPE_ERRORBIT_GENERATION: error-bit generation.

Definition at line 85 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::ListenMode

Set LSTN bit CEC Listening mode option : specifies device listening mode. It can take two values:

CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its own address (OAR). Messages addressed to different destination are ignored. Broadcast messages are always received.

CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own address (OAR) with positive acknowledge. Messages addressed to different destination are received, but without interfering with the CEC bus: no acknowledge sent.

Definition at line 110 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint16_t CEC_InitTypeDef::OwnAddress

Own addresses configuration This parameter can be a value of CEC Own Address

Definition at line 120 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint8_t* CEC_InitTypeDef::RxBuffer

CEC Rx buffer pointeur

Definition at line 123 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_ChangeRxBuffer(), HAL_CEC_Init(), and HAL_CEC_IRQHandler().

uint32_t CEC_InitTypeDef::SignalFreeTime

Set SFT field, specifies the Signal Free Time. It can be one of CEC Signal Free Time setting parameter and belongs to the set {0U,...,7} where 0x0 is the default configuration else means 0.5U + (SignalFreeTime - 1U) nominal data bit periods

Definition at line 66 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::SignalFreeTimeOption

Set SFTOP bit CEC Signal Free Time start option : specifies when SFT timer starts. CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception.

Definition at line 106 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::Tolerance

Set RXTOL bit, specifies the tolerance accepted on the received waveforms, it can be a value of CEC Receiver Tolerance : it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE

Definition at line 72 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_cec.h
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STM32F373xC HAL User Manual: CEC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CEC_HandleTypeDef Struct Reference
CEC Exported Types

CEC handle Structure definition. More...

#include <stm32f3xx_hal_cec.h>

Data Fields

CEC_TypeDef * | Instance
CEC_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferCount
uint16_t | RxXferSize
HAL_LockTypeDef | Lock
HAL_CEC_StateTypeDef gState
HAL_CEC_StateTypeDef RxState
uint32_t | ErrorCode

Detailed Description

CEC handle Structure definition.

Definition at line 187 of file stm32f3xx_hal_cec.h.

Field Documentation

uint32_t CEC_HandleTypeDef::ErrorCode

For errors handling purposes, copy of ISR register in case error is reported

Definition at line 208 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_GetError(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_SetDeviceAddress(), and HAL_CEC_Transmit_IT().

HAL_CEC_StateTypeDef CEC_HandleTypeDef::gState

CEC state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_CEC_StateTypeDef

Definition at line 201 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_GetState(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_SetDeviceAddress(), and HAL_CEC_Transmit_IT().

CEC_InitTypeDef CEC_HandleTypeDef::Init

CEC communication parameters

Definition at line 191 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_ChangeRxBuffer(), HAL_CEC_Init(), and HAL_CEC_IRQHandler().

CEC_TypeDef* CEC_HandleTypeDef::Instance

CEC registers base address

Definition at line 189 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_SetDeviceAddress(), and HAL_CEC_Transmit_IT().

HAL_LockTypeDef CEC_HandleTypeDef::Lock

Locking object

Definition at line 199 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint8_t* CEC_HandleTypeDef::pTxBuffPtr

Pointer to CEC Tx transfer Buffer

Definition at line 193 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Transmit_IT().

HAL_CEC_StateTypeDef CEC_HandleTypeDef::RxState

CEC state information related to Rx operations. This parameter can be a value of HAL_CEC_StateTypeDef

Definition at line 205 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_GetState(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), and HAL_CEC_SetDeviceAddress().

uint16_t CEC_HandleTypeDef::RxXferSize

CEC Rx Transfer size, 0: header received only

Definition at line 197 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_GetLastReceivedFrameSize(), and HAL_CEC_IRQHandler().

uint16_t CEC_HandleTypeDef::TxXferCount

CEC Tx Transfer Counter

Definition at line 195 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_cec.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC Error Code

Defines
CEC Error Code
CEC Exported Constants

Defines

#define | HAL_CEC_ERROR_NONE (0x00000000U)
#define | HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR
#define | HAL_CEC_ERROR_BRE CEC_ISR_BRE
#define | HAL_CEC_ERROR_SBPE CEC_ISR_SBPE
#define | HAL_CEC_ERROR_LBPE CEC_ISR_LBPE
#define | HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE
#define | HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST
#define | HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR
#define | HAL_CEC_ERROR_TXERR CEC_ISR_TXERR
#define | HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE

Define Documentation

#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST

CEC Arbitration Lost

Definition at line 229 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_BRE CEC_ISR_BRE

CEC Rx Bit Rising Error

Definition at line 225 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE

CEC Rx Long Bit period Error

Definition at line 227 of file stm32f3xx_hal_cec.h.

#define HAL_CEC_ERROR_NONE (0x00000000U)

no error

Definition at line 223 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_SetDeviceAddress(), and HAL_CEC_Transmit_IT().

#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE

CEC Rx Missing Acknowledge

Definition at line 228 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR

CEC Rx-Overrun

Definition at line 224 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE

CEC Rx Short Bit period Error

Definition at line 226 of file stm32f3xx_hal_cec.h.

#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE

CEC Tx Missing Acknowledge

Definition at line 232 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR

CEC Tx-Error

Definition at line 231 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR

CEC Tx-Buffer Underrun

Definition at line 230 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

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STM32F373xC HAL User Manual: CEC Signal Free Time setting parameter

Defines
CEC Signal Free Time setting parameter
CEC Exported Constants

Defines

#define | CEC_DEFAULT_SFT (0x00000000U)
#define | CEC_0_5_BITPERIOD_SFT (0x00000001U)
#define | CEC_1_5_BITPERIOD_SFT (0x00000002U)
#define | CEC_2_5_BITPERIOD_SFT (0x00000003U)
#define | CEC_3_5_BITPERIOD_SFT (0x00000004U)
#define | CEC_4_5_BITPERIOD_SFT (0x00000005U)
#define | CEC_5_5_BITPERIOD_SFT (0x00000006U)
#define | CEC_6_5_BITPERIOD_SFT (0x00000007U)

Define Documentation

#define CEC_0_5_BITPERIOD_SFT (0x00000001U)

Definition at line 241 of file stm32f3xx_hal_cec.h.

#define CEC_1_5_BITPERIOD_SFT (0x00000002U)

Definition at line 242 of file stm32f3xx_hal_cec.h.

#define CEC_2_5_BITPERIOD_SFT (0x00000003U)

Definition at line 243 of file stm32f3xx_hal_cec.h.

#define CEC_3_5_BITPERIOD_SFT (0x00000004U)

Definition at line 244 of file stm32f3xx_hal_cec.h.

#define CEC_4_5_BITPERIOD_SFT (0x00000005U)

Definition at line 245 of file stm32f3xx_hal_cec.h.

#define CEC_5_5_BITPERIOD_SFT (0x00000006U)

Definition at line 246 of file stm32f3xx_hal_cec.h.

#define CEC_6_5_BITPERIOD_SFT (0x00000007U)

Definition at line 247 of file stm32f3xx_hal_cec.h.

#define CEC_DEFAULT_SFT (0x00000000U)

Definition at line 240 of file stm32f3xx_hal_cec.h.

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STM32F373xC HAL User Manual: CEC Receiver Tolerance

Defines
CEC Receiver Tolerance
CEC Exported Constants

Defines

#define | CEC_STANDARD_TOLERANCE (0x00000000U)
#define | CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)

Define Documentation

#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)

Definition at line 256 of file stm32f3xx_hal_cec.h.

#define CEC_STANDARD_TOLERANCE (0x00000000U)

Definition at line 255 of file stm32f3xx_hal_cec.h.

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STM32F373xC HAL User Manual: CEC Reception Stop on Error

Defines
CEC Reception Stop on Error
CEC Exported Constants

Defines

#define | CEC_NO_RX_STOP_ON_BRE (0x00000000U)
#define | CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)

Define Documentation

#define CEC_NO_RX_STOP_ON_BRE (0x00000000U)

Definition at line 264 of file stm32f3xx_hal_cec.h.

#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)

Definition at line 265 of file stm32f3xx_hal_cec.h.

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STM32F373xC HAL User Manual: CEC Error Bit Generation if Bit Rise Error reported

Defines
CEC Error Bit Generation if Bit Rise Error reported
CEC Exported Constants

Defines

#define | CEC_BRE_ERRORBIT_NO_GENERATION (0x00000000U)
#define | CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)

Define Documentation

#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)

Definition at line 274 of file stm32f3xx_hal_cec.h.

#define CEC_BRE_ERRORBIT_NO_GENERATION (0x00000000U)

Definition at line 273 of file stm32f3xx_hal_cec.h.

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STM32F373xC HAL User Manual: CEC Error Bit Generation if Long Bit Period Error reported

Defines
CEC Error Bit Generation if Long Bit Period Error reported
CEC Exported Constants

Defines

#define | CEC_LBPE_ERRORBIT_NO_GENERATION (0x00000000U)
#define | CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)

Define Documentation

#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)

Definition at line 283 of file stm32f3xx_hal_cec.h.

#define CEC_LBPE_ERRORBIT_NO_GENERATION (0x00000000U)

Definition at line 282 of file stm32f3xx_hal_cec.h.

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STM32F373xC HAL User Manual: CEC Error Bit Generation on Broadcast message

Defines
CEC Error Bit Generation on Broadcast message
CEC Exported Constants

Defines

#define | CEC_BROADCASTERROR_ERRORBIT_GENERATION (0x00000000U)
#define | CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)

Define Documentation

#define CEC_BROADCASTERROR_ERRORBIT_GENERATION (0x00000000U)

Definition at line 291 of file stm32f3xx_hal_cec.h.

#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)

Definition at line 292 of file stm32f3xx_hal_cec.h.

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STM32F373xC HAL User Manual: CEC Signal Free Time start option

Defines
CEC Signal Free Time start option
CEC Exported Constants

Defines

#define | CEC_SFT_START_ON_TXSOM (0x00000000U)
#define | CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)

Define Documentation

#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)

Definition at line 301 of file stm32f3xx_hal_cec.h.

#define CEC_SFT_START_ON_TXSOM (0x00000000U)

Definition at line 300 of file stm32f3xx_hal_cec.h.

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STM32F373xC HAL User Manual: CEC Listening mode option

Defines
CEC Listening mode option
CEC Exported Constants

Defines

#define | CEC_REDUCED_LISTENING_MODE (0x00000000U)
#define | CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)

Define Documentation

#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)

Definition at line 310 of file stm32f3xx_hal_cec.h.

#define CEC_REDUCED_LISTENING_MODE (0x00000000U)

Definition at line 309 of file stm32f3xx_hal_cec.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC Device Own Address position in CEC CFGR register

Defines
CEC Device Own Address position in CEC CFGR register
CEC Exported Constants

Defines

#define CEC_CFGR_OAR_LSB_POS (16U)

Define Documentation

#define CEC_CFGR_OAR_LSB_POS (16U)

Definition at line 318 of file stm32f3xx_hal_cec.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC Initiator logical address position in message header

Defines
CEC Initiator logical address position in message header
CEC Exported Constants

Defines

#define CEC_INITIATOR_LSB_POS (4U)

Define Documentation

#define CEC_INITIATOR_LSB_POS (4U)

Definition at line 326 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC Own Address

Defines
CEC Own Address
CEC Exported Constants

Defines

#define | CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
#define | CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0U */
#define | CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1U */
#define | CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2U */
#define | CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3U */
#define | CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4U */
#define | CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5U */
#define | CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6U */
#define | CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7U */
#define | CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9U */
#define | CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10U */
#define | CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11U */
#define | CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12U */
#define | CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13U */
#define | CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14U */
#define | CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15U */

Define Documentation

#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0U */

Definition at line 335 of file stm32f3xx_hal_cec.h.

#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1U */

Definition at line 336 of file stm32f3xx_hal_cec.h.

#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11U */

Definition at line 345 of file stm32f3xx_hal_cec.h.

#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12U */

Definition at line 346 of file stm32f3xx_hal_cec.h.

#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13U */

Definition at line 347 of file stm32f3xx_hal_cec.h.

#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14U */

Definition at line 348 of file stm32f3xx_hal_cec.h.

#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15U */

Definition at line 349 of file stm32f3xx_hal_cec.h.

#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2U */

Definition at line 337 of file stm32f3xx_hal_cec.h.

#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3U */

Definition at line 338 of file stm32f3xx_hal_cec.h.

#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4U */

Definition at line 339 of file stm32f3xx_hal_cec.h.

#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5U */

Definition at line 340 of file stm32f3xx_hal_cec.h.

#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6U */

Definition at line 341 of file stm32f3xx_hal_cec.h.

#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7U */

Definition at line 342 of file stm32f3xx_hal_cec.h.

#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9U */

Definition at line 343 of file stm32f3xx_hal_cec.h.

#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10U */

Definition at line 344 of file stm32f3xx_hal_cec.h.

#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */

Definition at line 334 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_SetDeviceAddress().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC Interrupts definition

Defines
CEC Interrupts definition
CEC Exported Constants

Defines

#define | CEC_IT_TXACKE CEC_IER_TXACKEIE
#define | CEC_IT_TXERR CEC_IER_TXERRIE
#define | CEC_IT_TXUDR CEC_IER_TXUDRIE
#define | CEC_IT_TXEND CEC_IER_TXENDIE
#define | CEC_IT_TXBR CEC_IER_TXBRIE
#define | CEC_IT_ARBLST CEC_IER_ARBLSTIE
#define | CEC_IT_RXACKE CEC_IER_RXACKEIE
#define | CEC_IT_LBPE CEC_IER_LBPEIE
#define | CEC_IT_SBPE CEC_IER_SBPEIE
#define | CEC_IT_BRE CEC_IER_BREIE
#define | CEC_IT_RXOVR CEC_IER_RXOVRIE
#define | CEC_IT_RXEND CEC_IER_RXENDIE
#define | CEC_IT_RXBR CEC_IER_RXBRIE

Define Documentation

#define CEC_IT_ARBLST CEC_IER_ARBLSTIE

Definition at line 362 of file stm32f3xx_hal_cec.h.

#define CEC_IT_BRE CEC_IER_BREIE

Definition at line 366 of file stm32f3xx_hal_cec.h.

#define CEC_IT_LBPE CEC_IER_LBPEIE

Definition at line 364 of file stm32f3xx_hal_cec.h.

#define CEC_IT_RXACKE CEC_IER_RXACKEIE

Definition at line 363 of file stm32f3xx_hal_cec.h.

#define CEC_IT_RXBR CEC_IER_RXBRIE

Definition at line 369 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

#define CEC_IT_RXEND CEC_IER_RXENDIE

Definition at line 368 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

#define CEC_IT_RXOVR CEC_IER_RXOVRIE

Definition at line 367 of file stm32f3xx_hal_cec.h.

#define CEC_IT_SBPE CEC_IER_SBPEIE

Definition at line 365 of file stm32f3xx_hal_cec.h.

#define CEC_IT_TXACKE CEC_IER_TXACKEIE

Definition at line 357 of file stm32f3xx_hal_cec.h.

#define CEC_IT_TXBR CEC_IER_TXBRIE

Definition at line 361 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

#define CEC_IT_TXEND CEC_IER_TXENDIE

Definition at line 360 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

#define CEC_IT_TXERR CEC_IER_TXERRIE

Definition at line 358 of file stm32f3xx_hal_cec.h.

#define CEC_IT_TXUDR CEC_IER_TXUDRIE

Definition at line 359 of file stm32f3xx_hal_cec.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC Flags definition

Defines
CEC Flags definition
CEC Exported Constants

Defines

#define | CEC_FLAG_TXACKE CEC_ISR_TXACKE
#define | CEC_FLAG_TXERR CEC_ISR_TXERR
#define | CEC_FLAG_TXUDR CEC_ISR_TXUDR
#define | CEC_FLAG_TXEND CEC_ISR_TXEND
#define | CEC_FLAG_TXBR CEC_ISR_TXBR
#define | CEC_FLAG_ARBLST CEC_ISR_ARBLST
#define | CEC_FLAG_RXACKE CEC_ISR_RXACKE
#define | CEC_FLAG_LBPE CEC_ISR_LBPE
#define | CEC_FLAG_SBPE CEC_ISR_SBPE
#define | CEC_FLAG_BRE CEC_ISR_BRE
#define | CEC_FLAG_RXOVR CEC_ISR_RXOVR
#define | CEC_FLAG_RXEND CEC_ISR_RXEND
#define | CEC_FLAG_RXBR CEC_ISR_RXBR

Define Documentation

#define CEC_FLAG_ARBLST CEC_ISR_ARBLST

Definition at line 382 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_FLAG_BRE CEC_ISR_BRE

Definition at line 386 of file stm32f3xx_hal_cec.h.

#define CEC_FLAG_LBPE CEC_ISR_LBPE

Definition at line 384 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_FLAG_RXACKE CEC_ISR_RXACKE

Definition at line 383 of file stm32f3xx_hal_cec.h.

#define CEC_FLAG_RXBR CEC_ISR_RXBR

Definition at line 389 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define CEC_FLAG_RXEND CEC_ISR_RXEND

Definition at line 388 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define CEC_FLAG_RXOVR CEC_ISR_RXOVR

Definition at line 387 of file stm32f3xx_hal_cec.h.

#define CEC_FLAG_SBPE CEC_ISR_SBPE

Definition at line 385 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_FLAG_TXACKE CEC_ISR_TXACKE

Definition at line 377 of file stm32f3xx_hal_cec.h.

#define CEC_FLAG_TXBR CEC_ISR_TXBR

Definition at line 381 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define CEC_FLAG_TXEND CEC_ISR_TXEND

Definition at line 380 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define CEC_FLAG_TXERR CEC_ISR_TXERR

Definition at line 378 of file stm32f3xx_hal_cec.h.

#define CEC_FLAG_TXUDR CEC_ISR_TXUDR

Definition at line 379 of file stm32f3xx_hal_cec.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC all RX or TX errors flags

Defines
CEC all RX or TX errors flags
CEC Exported Constants

Defines

#define CEC_ISR_ALL_ERROR

Define Documentation

#define CEC_ISR_ALL_ERROR
Value:
((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
                                                  CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)

Definition at line 397 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC all RX errors interrupts enabling flag

Defines
CEC all RX errors interrupts enabling flag
CEC Exported Constants

Defines

#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)

Define Documentation

#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)

Definition at line 406 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC all TX errors interrupts enabling flag

Defines
CEC all TX errors interrupts enabling flag
CEC Exported Constants

Defines

#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)

Define Documentation

#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)

Definition at line 414 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC Exported Macros

Defines
CEC Exported Macros
CEC

Defines

#define | __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__)
Reset CEC handle gstate & RxState.
#define | __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Checks whether or not the specified CEC interrupt flag is set.
#define | __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
Clears the interrupt or status flag when raised (write at 1U)
#define | __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enables the specified CEC interrupt.
#define | __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disables the specified CEC interrupt.
#define | __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
Checks whether or not the specified CEC interrupt is enabled.
#define | __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
Enables the CEC device.
#define | __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
Disables the CEC device.
#define | __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
Set Transmission Start flag.
#define | __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
Set Transmission End flag.
#define | __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
Get Transmission Start flag.
#define | __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
Get Transmission End flag.
#define | __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
Clear OAR register.
#define | __HAL_CEC_SET_OAR(__HANDLE__, __ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
Set OAR register (without resetting previously set address in case of multi-address mode) To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand.

Define Documentation

#define __HAL_CEC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR |= (__FLAG__))

Clears the interrupt or status flag when raised (write at 1U)

Parameters:
__HANDLE__ specifies the CEC Handle.
__FLAG__ specifies the interrupt/status flag to clear. This parameter can be one of the following values:
  • CEC_FLAG_TXACKE: Tx Missing acknowledge Error
  • CEC_FLAG_TXERR: Tx Error.
  • CEC_FLAG_TXUDR: Tx-Buffer Underrun.
  • CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
  • CEC_FLAG_TXBR: Tx-Byte Request.
  • CEC_FLAG_ARBLST: Arbitration Lost
  • CEC_FLAG_RXACKE: Rx-Missing Acknowledge
  • CEC_FLAG_LBPE: Rx Long period Error
  • CEC_FLAG_SBPE: Rx Short period Error
  • CEC_FLAG_BRE: Rx Bit Rising Error
  • CEC_FLAG_RXOVR: Rx Overrun.
  • CEC_FLAG_RXEND: End Of Reception.
  • CEC_FLAG_RXBR: Rx-Byte Received.
Return values:
none

Definition at line 476 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define __HAL_CEC_CLEAR_OAR ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)

Clear OAR register.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
none

Definition at line 582 of file stm32f3xx_hal_cec.h.

#define __HAL_CEC_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)

Disables the CEC device.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
none

Definition at line 551 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_Init(), and HAL_CEC_SetDeviceAddress().

#define __HAL_CEC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

Disables the specified CEC interrupt.

Parameters:
__HANDLE__ specifies the CEC Handle.
__INTERRUPT__ specifies the CEC interrupt to disable. This parameter can be one of the following values:
  • CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
  • CEC_IT_TXERR: Tx Error IT Enable
  • CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
  • CEC_IT_TXEND: End of transmission IT Enable
  • CEC_IT_TXBR: Tx-Byte Request IT Enable
  • CEC_IT_ARBLST: Arbitration Lost IT Enable
  • CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
  • CEC_IT_LBPE: Rx Long period Error IT Enable
  • CEC_IT_SBPE: Rx Short period Error IT Enable
  • CEC_IT_BRE: Rx Bit Rising Error IT Enable
  • CEC_IT_RXOVR: Rx Overrun IT Enable
  • CEC_IT_RXEND: End Of Reception IT Enable
  • CEC_IT_RXBR: Rx-Byte Received IT Enable
Return values:
none

Definition at line 518 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_DeInit().

#define __HAL_CEC_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)

Enables the CEC device.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
none

Definition at line 545 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init(), and HAL_CEC_SetDeviceAddress().

#define __HAL_CEC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enables the specified CEC interrupt.

Parameters:
__HANDLE__ specifies the CEC Handle.
__INTERRUPT__ specifies the CEC interrupt to enable. This parameter can be one of the following values:
  • CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
  • CEC_IT_TXERR: Tx Error IT Enable
  • CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
  • CEC_IT_TXEND: End of transmission IT Enable
  • CEC_IT_TXBR: Tx-Byte Request IT Enable
  • CEC_IT_ARBLST: Arbitration Lost IT Enable
  • CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
  • CEC_IT_LBPE: Rx Long period Error IT Enable
  • CEC_IT_SBPE: Rx Short period Error IT Enable
  • CEC_IT_BRE: Rx Bit Rising Error IT Enable
  • CEC_IT_RXOVR: Rx Overrun IT Enable
  • CEC_IT_RXEND: End Of Reception IT Enable
  • CEC_IT_RXBR: Rx-Byte Received IT Enable
Return values:
none

Definition at line 497 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define __HAL_CEC_FIRST_BYTE_TX_SET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)

Set Transmission Start flag.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
none

Definition at line 557 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

#define __HAL_CEC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR & (__FLAG__))

Checks whether or not the specified CEC interrupt flag is set.

Parameters:
__HANDLE__ specifies the CEC Handle.
__FLAG__ specifies the flag to check.
  • CEC_FLAG_TXACKE: Tx Missing acknowledge Error
  • CEC_FLAG_TXERR: Tx Error.
  • CEC_FLAG_TXUDR: Tx-Buffer Underrun.
  • CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
  • CEC_FLAG_TXBR: Tx-Byte Request.
  • CEC_FLAG_ARBLST: Arbitration Lost
  • CEC_FLAG_RXACKE: Rx-Missing Acknowledge
  • CEC_FLAG_LBPE: Rx Long period Error
  • CEC_FLAG_SBPE: Rx Short period Error
  • CEC_FLAG_BRE: Rx Bit Rising Error
  • CEC_FLAG_RXOVR: Rx Overrun.
  • CEC_FLAG_RXEND: End Of Reception.
  • CEC_FLAG_RXBR: Rx-Byte Received.
Return values:
ITStatus

Definition at line 455 of file stm32f3xx_hal_cec.h.

#define __HAL_CEC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER & (__INTERRUPT__))

Checks whether or not the specified CEC interrupt is enabled.

Parameters:
__HANDLE__ specifies the CEC Handle.
__INTERRUPT__ specifies the CEC interrupt to check. This parameter can be one of the following values:
  • CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
  • CEC_IT_TXERR: Tx Error IT Enable
  • CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
  • CEC_IT_TXEND: End of transmission IT Enable
  • CEC_IT_TXBR: Tx-Byte Request IT Enable
  • CEC_IT_ARBLST: Arbitration Lost IT Enable
  • CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
  • CEC_IT_LBPE: Rx Long period Error IT Enable
  • CEC_IT_SBPE: Rx Short period Error IT Enable
  • CEC_IT_BRE: Rx Bit Rising Error IT Enable
  • CEC_IT_RXOVR: Rx Overrun IT Enable
  • CEC_IT_RXEND: End Of Reception IT Enable
  • CEC_IT_RXBR: Rx-Byte Received IT Enable
Return values:
FlagStatus

Definition at line 539 of file stm32f3xx_hal_cec.h.

#define __HAL_CEC_GET_TRANSMISSION_END_FLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)

Get Transmission End flag.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
FlagStatus

Definition at line 576 of file stm32f3xx_hal_cec.h.

#define __HAL_CEC_GET_TRANSMISSION_START_FLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)

Get Transmission Start flag.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
FlagStatus

Definition at line 570 of file stm32f3xx_hal_cec.h.

#define __HAL_CEC_LAST_BYTE_TX_SET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)

Set Transmission End flag.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
none If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.

Definition at line 564 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Transmit_IT().

#define __HAL_CEC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \
                                                       (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \
                                                     } while(0U)

Reset CEC handle gstate & RxState.

Parameters:
__HANDLE__ CEC handle.
Return values:
None

Definition at line 432 of file stm32f3xx_hal_cec.h.

#define __HAL_CEC_SET_OAR | ( | __HANDLE__,
 |  | __ADDRESS__
 | ) | SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)

Set OAR register (without resetting previously set address in case of multi-address mode) To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand.

Parameters:
__HANDLE__ | specifies the CEC Handle.
__ADDRESS__ | Own Address value (CEC logical address is identified by bit position)
Return values:
none

Definition at line 590 of file stm32f3xx_hal_cec.h.

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STM32F373xC HAL User Manual: CEC Private Types

CEC Private Types
CEC
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC Private Variables

CEC Private Variables
CEC
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC Private Macros

Defines
CEC Private Macros
CEC

Defines

#define | IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
#define | IS_CEC_TOLERANCE(__RXTOL__)
#define | IS_CEC_BRERXSTOP(__BRERXSTOP__)
#define | IS_CEC_BREERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__)
#define | IS_CEC_SFTOP(__SFTOP__)
#define | IS_CEC_LISTENING_MODE(__MODE__)
#define | IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
Check CEC message size.
#define | IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
Check CEC device Own Address Register (OAR) setting.
#define | IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)
Check CEC initiator or destination logical address setting.

Define Documentation

#define IS_CEC_ADDRESS ( __ADDRESS__ ) ((__ADDRESS__) <= 0x0FU)

Check CEC initiator or destination logical address setting.

Initiator and destination addresses are coded over 4 bits.

Parameters:
__ADDRESS__ CEC initiator or logical address.
Return values:
Test result (TRUE or FALSE).

Definition at line 719 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

#define IS_CEC_BREERRORBITGEN ( __ERRORBITGEN__ )
Value:
(((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
                                                ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))

Definition at line 683 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_BRERXSTOP ( __BRERXSTOP__ )
Value:
(((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
                                           ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))

Definition at line 680 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ( __ERRORBITGEN__ )
Value:
(((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
                                                                       ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))

Definition at line 689 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_LBPEERRORBITGEN ( __ERRORBITGEN__ )
Value:
(((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
                                                 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))

Definition at line 686 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_LISTENING_MODE ( __MODE__ )
Value:
(((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
                                             ((__MODE__) == CEC_FULL_LISTENING_MODE))

Definition at line 695 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_MSGSIZE ( __SIZE__ ) ((__SIZE__) <= 0x10U)

Check CEC message size.

The message size is the payload size: without counting the header, it varies from 0 byte (ping operation, one header only, no payload) to 15 bytes (1 opcode and up to 14 operands following the header).

Parameters:
__SIZE__ CEC message size.
Return values:
Test result (TRUE or FALSE).

Definition at line 705 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

#define IS_CEC_OWN_ADDRESS ( __ADDRESS__ ) ((__ADDRESS__) <= 0x7FFFU)

Check CEC device Own Address Register (OAR) setting.

OAR address is written in a 15-bit field within CEC_CFGR register.

Parameters:
__ADDRESS__ CEC own address.
Return values:
Test result (TRUE or FALSE).

Definition at line 712 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init(), and HAL_CEC_SetDeviceAddress().

#define IS_CEC_SFTOP ( __SFTOP__ )
Value:
(((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
                                          ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))

Definition at line 692 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_SIGNALFREETIME ( __SFT__ ) ((__SFT__) <= CEC_CFGR_SFT)

Definition at line 675 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_TOLERANCE ( __RXTOL__ )
Value:
(((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
                                            ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))

Definition at line 677 of file stm32f3xx_hal_cec.h.

Referenced by HAL_CEC_Init().

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STM32F373xC HAL User Manual: COMP Private Constants

Defines
COMP Private Constants
COMP

Defines

#define | COMP_LOCK_DISABLE (0x00000000U)
#define | COMP_LOCK_ENABLE COMP_CSR_COMPxLOCK

Define Documentation

#define COMP_LOCK_DISABLE (0x00000000U)

Definition at line 262 of file stm32f3xx_hal_comp.c.

#define COMP_LOCK_ENABLE COMP_CSR_COMPxLOCK

Definition at line 263 of file stm32f3xx_hal_comp.c.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
COMP Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP peripheral according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions to initialize and de-initialize comparators.

Function Documentation

HAL_StatusTypeDef HAL_COMP_DeInit ( COMP_HandleTypeDef * hcomp )

DeInitialize the COMP peripheral.

Note:
If the selected comparator is locked, deinitialization cannot be performed. To unlock the configuration, perform a system reset.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 368 of file stm32f3xx_hal_comp.c.

References assert_param, COMP_DEINIT, COMP_STATE_BIT_LOCK, HAL_COMP_MspDeInit(), HAL_COMP_STATE_RESET, COMP_HandleTypeDef::Instance, and COMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_COMP_Init ( COMP_HandleTypeDef * hcomp )

Initialize the COMP peripheral according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.

Note:
If the selected comparator is locked, initialization cannot be performed. To unlock the configuration, perform a system reset.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 298 of file stm32f3xx_hal_comp.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, COMP_InitTypeDef::BlankingSrce, COMP_INIT, COMP_INVERTINGINPUT_SELECTION, COMP_STATE_BIT_LOCK, COMP_WINDOWMODE_DISABLE, HAL_COMP_MspInit(), HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, COMP_InitTypeDef::Hysteresis, COMP_HandleTypeDef::Init, COMP_HandleTypeDef::Instance, COMP_InitTypeDef::InvertingInput, IS_COMP_BLANKINGSRCE, IS_COMP_BLANKINGSRCE_INSTANCE, IS_COMP_HYSTERESIS, IS_COMP_INVERTINGINPUT, IS_COMP_MODE, IS_COMP_NONINVERTINGINPUT, IS_COMP_NONINVERTINGINPUT_INSTANCE, IS_COMP_OUTPUT, IS_COMP_OUTPUT_INSTANCE, IS_COMP_OUTPUTPOL, IS_COMP_TRIGGERMODE, IS_COMP_WINDOWMODE, COMP_HandleTypeDef::Lock, COMP_InitTypeDef::Mode, COMP_InitTypeDef::NonInvertingInput, COMP_InitTypeDef::Output, COMP_InitTypeDef::OutputPol, COMP_HandleTypeDef::State, COMP_InitTypeDef::TriggerMode, and COMP_InitTypeDef::WindowMode.

void HAL_COMP_MspDeInit ( COMP_HandleTypeDef * hcomp )

DeInitialize the COMP MSP.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 417 of file stm32f3xx_hal_comp.c.

Referenced by HAL_COMP_DeInit().

void HAL_COMP_MspInit ( COMP_HandleTypeDef * hcomp )

Initialize the COMP MSP.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 402 of file stm32f3xx_hal_comp.c.

Referenced by HAL_COMP_Init().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Start Stop operation functions

Functions
Start Stop operation functions
COMP Exported Functions

Start-Stop operation functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
HAL_StatusTypeDef | HAL_COMP_Start_IT (COMP_HandleTypeDef *hcomp)
Start the comparator in Interrupt mode.
HAL_StatusTypeDef | HAL_COMP_Stop_IT (COMP_HandleTypeDef *hcomp)
Stop the comparator in Interrupt mode.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ Handler.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator callback.

Detailed Description

Start-Stop operation functions.

 ===============================================================================
                      ##### Start Stop operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start a comparator without interrupt generation.
      (+) Stop a comparator without interrupt generation.
      (+) Start a comparator with interrupt generation.
      (+) Stop a comparator with interrupt generation.
      (+) Handle interrupts from a comparator with associated callback function.

Function Documentation

void HAL_COMP_IRQHandler ( COMP_HandleTypeDef * hcomp )

Comparator IRQ Handler.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 650 of file stm32f3xx_hal_comp.c.

References COMP_EXTI_CLEAR_FLAG, COMP_EXTI_GET_FLAG, COMP_GET_EXTI_LINE, HAL_COMP_TriggerCallback(), and COMP_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_COMP_Start ( COMP_HandleTypeDef * hcomp )

Start the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 454 of file stm32f3xx_hal_comp.c.

References __HAL_COMP_ENABLE, assert_param, COMP_EXTI_CLEAR_FLAG, COMP_EXTI_ENABLE_EVENT, COMP_EXTI_FALLING_DISABLE, COMP_EXTI_FALLING_ENABLE, COMP_EXTI_RISING_DISABLE, COMP_EXTI_RISING_ENABLE, COMP_GET_EXTI_LINE, COMP_STATE_BIT_LOCK, COMP_TRIGGERMODE_EVENT_FALLING, COMP_TRIGGERMODE_EVENT_RISING, HAL_COMP_STATE_BUSY, HAL_COMP_STATE_READY, COMP_HandleTypeDef::Init, COMP_HandleTypeDef::Instance, COMP_HandleTypeDef::State, and COMP_InitTypeDef::TriggerMode.

HAL_StatusTypeDef HAL_COMP_Start_IT ( COMP_HandleTypeDef * hcomp )

Start the comparator in Interrupt mode.

Parameters:
hcomp COMP handle
Return values:
HAL status.

Definition at line 561 of file stm32f3xx_hal_comp.c.

References __HAL_COMP_ENABLE, assert_param, COMP_EXTI_CLEAR_FLAG, COMP_EXTI_ENABLE_IT, COMP_EXTI_FALLING_DISABLE, COMP_EXTI_FALLING_ENABLE, COMP_EXTI_RISING_DISABLE, COMP_EXTI_RISING_ENABLE, COMP_GET_EXTI_LINE, COMP_STATE_BIT_LOCK, COMP_TRIGGERMODE_IT_FALLING, COMP_TRIGGERMODE_IT_RISING, HAL_COMP_STATE_BUSY, HAL_COMP_STATE_READY, COMP_HandleTypeDef::Init, COMP_HandleTypeDef::Instance, COMP_HandleTypeDef::State, and COMP_InitTypeDef::TriggerMode.

HAL_StatusTypeDef HAL_COMP_Stop ( COMP_HandleTypeDef * hcomp )

Stop the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 523 of file stm32f3xx_hal_comp.c.

References __HAL_COMP_DISABLE, assert_param, COMP_EXTI_DISABLE_EVENT, COMP_GET_EXTI_LINE, COMP_STATE_BIT_LOCK, HAL_COMP_STATE_BUSY, HAL_COMP_STATE_READY, COMP_HandleTypeDef::Instance, and COMP_HandleTypeDef::State.

Referenced by HAL_COMP_Stop_IT().

HAL_StatusTypeDef HAL_COMP_Stop_IT ( COMP_HandleTypeDef * hcomp )

Stop the comparator in Interrupt mode.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 633 of file stm32f3xx_hal_comp.c.

References COMP_EXTI_DISABLE_IT, COMP_GET_EXTI_LINE, HAL_COMP_Stop(), and COMP_HandleTypeDef::Instance.

void HAL_COMP_TriggerCallback ( COMP_HandleTypeDef * hcomp )

Comparator callback.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 670 of file stm32f3xx_hal_comp.c.

Referenced by HAL_COMP_IRQHandler().

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STM32F373xC HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
COMP Exported Functions

Management functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.

Detailed Description

Management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the comparators.

Function Documentation

uint32_t HAL_COMP_GetOutputLevel ( COMP_HandleTypeDef * hcomp )

Return the output level (high or low) of the selected comparator.

The output level depends on the selected polarity. If the polarity is not inverted:

  • Comparator output is low when the non-inverting input is at a lower voltage than the inverting input
  • Comparator output is high when the non-inverting input is at a higher voltage than the inverting input If the polarity is inverted:
  • Comparator output is high when the non-inverting input is at a lower voltage than the inverting input
  • Comparator output is low when the non-inverting input is at a higher voltage than the inverting input
    Parameters:
    hcomp COMP handle
    Return values:
    Returns the selected comparator output level:
    • COMP_OUTPUTLEVEL_LOW
    • COMP_OUTPUTLEVEL_HIGH

Definition at line 762 of file stm32f3xx_hal_comp.c.

References assert_param, COMP_OUTPUTLEVEL_HIGH, COMP_OUTPUTLEVEL_LOW, and COMP_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_COMP_Lock ( COMP_HandleTypeDef * hcomp )

Lock the selected comparator configuration.

Note:
A system reset is required to unlock the comparator configuration.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 704 of file stm32f3xx_hal_comp.c.

References __HAL_COMP_LOCK, assert_param, COMP_STATE_BIT_LOCK, HAL_COMP_STATE_BUSY, HAL_COMP_STATE_BUSY_LOCKED, HAL_COMP_STATE_READY, HAL_COMP_STATE_READY_LOCKED, COMP_HandleTypeDef::Instance, and COMP_HandleTypeDef::State.

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STM32F373xC HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
COMP Exported Functions

Peripheral State functions. More...

Functions

HAL_COMP_StateTypeDef HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_COMP_StateTypeDef HAL_COMP_GetState ( COMP_HandleTypeDef * hcomp )

Return the COMP handle state.

Parameters:
hcomp COMP handle
Return values:
HAL state

Definition at line 801 of file stm32f3xx_hal_comp.c.

References assert_param, HAL_COMP_STATE_RESET, COMP_HandleTypeDef::Instance, and COMP_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Exported Types

Data Structures | Enumerations
COMP Exported Types
COMP

Data Structures

struct | COMP_InitTypeDef
COMP Init structure definition. More...
struct | COMP_HandleTypeDef
COMP Handle Structure definition. More...

Enumerations

enum HAL_COMP_StateTypeDef {
HAL_COMP_STATE_RESET = 0x00U, HAL_COMP_STATE_READY = 0x01U, HAL_COMP_STATE_READY_LOCKED = 0x11U, HAL_COMP_STATE_BUSY = 0x02U,
HAL_COMP_STATE_BUSY_LOCKED = 0x12
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_COMP_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_COMP_STATE_RESET

COMP not yet initialized or disabled

HAL_COMP_STATE_READY

COMP initialized and ready for use

HAL_COMP_STATE_READY_LOCKED

COMP initialized but the configuration is locked

HAL_COMP_STATE_BUSY

COMP is running

HAL_COMP_STATE_BUSY_LOCKED

COMP is running and the configuration is locked

Definition at line 102 of file stm32f3xx_hal_comp.h.

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STM32F373xC HAL User Manual: COMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
COMP_InitTypeDef Struct Reference
COMP Exported Types

COMP Init structure definition. More...

#include <stm32f3xx_hal_comp.h>

Data Fields

uint32_t | InvertingInput
uint32_t | NonInvertingInput
uint32_t | Output
uint32_t | OutputPol
uint32_t | Hysteresis
uint32_t | BlankingSrce
uint32_t | Mode
uint32_t | WindowMode
uint32_t | TriggerMode

Detailed Description

COMP Init structure definition.

Definition at line 62 of file stm32f3xx_hal_comp.h.

Field Documentation

uint32_t COMP_InitTypeDef::BlankingSrce

Selects the output blanking source of the comparator. This parameter can be a value of COMP Extended Blanking Source (STM32F373xC/STM32F378xx Product devices) Note: Not available on STM32F373xB/C and STM32F378xx devices

Definition at line 82 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::Hysteresis

Selects the hysteresis voltage of the comparator. This parameter can be a value of COMP Extended Hysteresis Note: Only available on STM32F302xB/xC, STM32F303xB/xC, STM32F373xB/xC, STM32F358xx and STM32F378xx devices

Definition at line 78 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::InvertingInput

Selects the inverting input of the comparator. This parameter can be a value of COMP Extended InvertingInput (STM32F373xC/STM32F378xx Product devices)

Definition at line 65 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::Mode

Selects the operating consumption mode of the comparator to adjust the speed/consumption. This parameter can be a value of COMP Extended Mode Note: Not available on STM32F301x6/x8, STM32F302x6/x8, STM32F334x6/x8, STM32F318xx and STM32F328xx devices

Definition at line 86 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::NonInvertingInput

Selects the non inverting input of the comparator. This parameter can be a value of COMP Extended NonInvertingInput (STM32F373xC/STM32F378xx Product devices) Note: Only available on STM32F302xB/xC, STM32F303xB/xC and STM32F358xx devices

Definition at line 68 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::Output

Selects the output redirection of the comparator. This parameter can be a value of COMP Extended Output (STM32F373xC/STM32F378xx Product devices)

Definition at line 72 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::OutputPol

Selects the output polarity of the comparator. This parameter can be a value of COMP Output Polarity

Definition at line 75 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::TriggerMode

Selects the trigger mode of the comparator (interrupt mode). This parameter can be a value of COMP Trigger Mode

Definition at line 94 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_Init(), HAL_COMP_Start(), and HAL_COMP_Start_IT().

uint32_t COMP_InitTypeDef::WindowMode

Selects the window mode of the comparator X (X=2U, 4 or 6 if available). This parameter can be a value of COMP Extended WindowMode (STM32F373xC/STM32F378xx Product devices)

Definition at line 91 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_Init().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_comp.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
COMP_HandleTypeDef Struct Reference
COMP Exported Types

COMP Handle Structure definition. More...

#include <stm32f3xx_hal_comp.h>

Data Fields

COMP_TypeDef * | Instance
COMP_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_COMP_StateTypeDef | State

Detailed Description

COMP Handle Structure definition.

Definition at line 114 of file stm32f3xx_hal_comp.h.

Field Documentation

COMP_InitTypeDef COMP_HandleTypeDef::Init

COMP required parameters

Definition at line 117 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_Init(), HAL_COMP_Start(), and HAL_COMP_Start_IT().

COMP_TypeDef* COMP_HandleTypeDef::Instance

Register base address

Definition at line 116 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_GetOutputLevel(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_IRQHandler(), HAL_COMP_Lock(), HAL_COMP_Start(), HAL_COMP_Start_IT(), HAL_COMP_Stop(), and HAL_COMP_Stop_IT().

HAL_LockTypeDef COMP_HandleTypeDef::Lock

Locking object

Definition at line 118 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_Init().

__IO HAL_COMP_StateTypeDef COMP_HandleTypeDef::State

COMP communication state

Definition at line 119 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_Start(), HAL_COMP_Start_IT(), and HAL_COMP_Stop().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_comp.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Output Polarity

Defines
COMP Output Polarity
COMP Exported Constants

Defines

#define | COMP_OUTPUTPOL_NONINVERTED (0x00000000U)
#define | COMP_OUTPUTPOL_INVERTED COMP_CSR_COMPxPOL

Define Documentation

#define COMP_OUTPUTPOL_INVERTED COMP_CSR_COMPxPOL

COMP output on GPIO is inverted

Definition at line 135 of file stm32f3xx_hal_comp.h.

#define COMP_OUTPUTPOL_NONINVERTED (0x00000000U)

COMP output on GPIO isn't inverted

Definition at line 134 of file stm32f3xx_hal_comp.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Output Level

Defines
COMP Output Level
COMP Exported Constants

Defines

#define | COMP_OUTPUTLEVEL_LOW (0x00000000U)
#define | COMP_OUTPUTLEVEL_HIGH COMP_CSR_COMPxOUT

Define Documentation

#define COMP_OUTPUTLEVEL_HIGH COMP_CSR_COMPxOUT

Definition at line 148 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_GetOutputLevel().

#define COMP_OUTPUTLEVEL_LOW (0x00000000U)

Definition at line 145 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_GetOutputLevel().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Trigger Mode

Defines
COMP Trigger Mode
COMP Exported Constants

Defines

#define | COMP_TRIGGERMODE_NONE (0x00000000U)
#define | COMP_TRIGGERMODE_IT_RISING (0x00000001U)
#define | COMP_TRIGGERMODE_IT_FALLING (0x00000002U)
#define | COMP_TRIGGERMODE_IT_RISING_FALLING (0x00000003U)
#define | COMP_TRIGGERMODE_EVENT_RISING (0x00000010U)
#define | COMP_TRIGGERMODE_EVENT_FALLING (0x00000020U)
#define | COMP_TRIGGERMODE_EVENT_RISING_FALLING (0x00000030U)

Define Documentation

#define COMP_TRIGGERMODE_EVENT_FALLING (0x00000020U)

Event Mode with Falling edge trigger detection

Definition at line 161 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_Start().

#define COMP_TRIGGERMODE_EVENT_RISING (0x00000010U)

Event Mode with Rising edge trigger detection

Definition at line 160 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_Start().

#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (0x00000030U)

Event Mode with Rising/Falling edge trigger detection

Definition at line 162 of file stm32f3xx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_FALLING (0x00000002U)

External Interrupt Mode with Falling edge trigger detection

Definition at line 158 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_Start_IT().

#define COMP_TRIGGERMODE_IT_RISING (0x00000001U)

External Interrupt Mode with Rising edge trigger detection

Definition at line 157 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_Start_IT().

#define COMP_TRIGGERMODE_IT_RISING_FALLING (0x00000003U)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 159 of file stm32f3xx_hal_comp.h.

#define COMP_TRIGGERMODE_NONE (0x00000000U)

No External Interrupt trigger detection

Definition at line 156 of file stm32f3xx_hal_comp.h.

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STM32F373xC HAL User Manual: COMP State Lock

Defines
COMP State Lock
COMP Exported Constants

Defines

#define COMP_STATE_BIT_LOCK (0x00000010U) /* Lock bit in COMP handle state */

Define Documentation

#define COMP_STATE_BIT_LOCK (0x00000010U) /* Lock bit in COMP handle state */

Definition at line 170 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_Start(), HAL_COMP_Start_IT(), and HAL_COMP_Stop().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Exported Macros

Defines
COMP Exported Macros
COMP

Defines

#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
Reset COMP handle state.

Define Documentation

#define __HAL_COMP_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)

Reset COMP handle state.

Parameters:
__HANDLE__ COMP handle.
Return values:
None

Definition at line 188 of file stm32f3xx_hal_comp.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Private macros to check input parameters

Defines
COMP Private macros to check input parameters
COMP Private Macros

Defines

#define | IS_COMP_OUTPUTPOL(__POL__)
#define | IS_COMP_TRIGGERMODE(__MODE__)

Define Documentation

#define IS_COMP_OUTPUTPOL ( __POL__ )
Value:
(((__POL__) == COMP_OUTPUTPOL_NONINVERTED)  || \
                                     ((__POL__) == COMP_OUTPUTPOL_INVERTED))

Definition at line 259 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_TRIGGERMODE ( __MODE__ )
Value:
(((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
                                        ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
                                        ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
                                        ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
                                        ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
                                        ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
                                        ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))

Definition at line 262 of file stm32f3xx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Extended InvertingInput (STM32F373xC/STM32F378xx Product devices)

Defines
COMP Extended InvertingInput (STM32F373xC/STM32F378xx Product devices)
COMP Extended Exported Constants

Defines

#define | COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U)
#define | COMP_INVERTINGINPUT_1_2VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_0)
#define | COMP_INVERTINGINPUT_3_4VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_1)
#define | COMP_INVERTINGINPUT_VREFINT ((uint32_t)(COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0))
#define | COMP_INVERTINGINPUT_DAC1_CH1 ((uint32_t)COMP_CSR_COMPxINSEL_2)
#define | COMP_INVERTINGINPUT_DAC1_CH2 ((uint32_t)(COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0))
#define | COMP_INVERTINGINPUT_IO1 ((uint32_t)(COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1))
#define | COMP_INVERTINGINPUT_DAC2_CH1 ((uint32_t)COMP_CSR_COMPxINSEL)
#define | COMP_INVERTINGINPUT_DAC1 COMP_INVERTINGINPUT_DAC1_CH1
#define | COMP_INVERTINGINPUT_DAC2 COMP_INVERTINGINPUT_DAC1_CH2

Define Documentation

#define COMP_INVERTINGINPUT_1_2VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_0)

1U/2 VREFINT connected to comparator inverting input

Definition at line 130 of file stm32f3xx_hal_comp_ex.h.

#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U)

1U/4 VREFINT connected to comparator inverting input

Definition at line 129 of file stm32f3xx_hal_comp_ex.h.

#define COMP_INVERTINGINPUT_3_4VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_1)

3U/4 VREFINT connected to comparator inverting input

Definition at line 131 of file stm32f3xx_hal_comp_ex.h.

#define COMP_INVERTINGINPUT_DAC1 COMP_INVERTINGINPUT_DAC1_CH1

Definition at line 139 of file stm32f3xx_hal_comp_ex.h.

#define COMP_INVERTINGINPUT_DAC1_CH1 ((uint32_t)COMP_CSR_COMPxINSEL_2)

DAC1_CH1_OUT (PA4) connected to comparator inverting input

Definition at line 133 of file stm32f3xx_hal_comp_ex.h.

#define COMP_INVERTINGINPUT_DAC1_CH2 ((uint32_t)(COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0))

DAC1_CH2_OUT (PA5) connected to comparator inverting input

Definition at line 134 of file stm32f3xx_hal_comp_ex.h.

#define COMP_INVERTINGINPUT_DAC2 COMP_INVERTINGINPUT_DAC1_CH2

Definition at line 140 of file stm32f3xx_hal_comp_ex.h.

#define COMP_INVERTINGINPUT_DAC2_CH1 ((uint32_t)COMP_CSR_COMPxINSEL)

DAC2_CH1_OUT connected to comparator inverting input

Definition at line 136 of file stm32f3xx_hal_comp_ex.h.

#define COMP_INVERTINGINPUT_IO1 ((uint32_t)(COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1))

IO1 (PA0 for COMP1, PA2 for COMP2) connected to comparator inverting input

Definition at line 135 of file stm32f3xx_hal_comp_ex.h.

#define COMP_INVERTINGINPUT_VREFINT ((uint32_t)(COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0))

VREFINT connected to comparator inverting input

Definition at line 132 of file stm32f3xx_hal_comp_ex.h.

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STM32F373xC HAL User Manual: COMP Extended NonInvertingInput (STM32F373xC/STM32F378xx Product devices)

Defines
COMP Extended NonInvertingInput (STM32F373xC/STM32F378xx Product devices)
COMP Extended Exported Constants

Defines

#define | COMP_NONINVERTINGINPUT_IO1 (0x00000000U)
#define | COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP_CSR_COMP1SW1

Define Documentation

#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP_CSR_COMP1SW1

DAC ouput connected to comparator COMP1 non inverting input

Definition at line 176 of file stm32f3xx_hal_comp_ex.h.

#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U)

IO1 (PA1 for COMP1, PA3 for COMP2) connected to comparator non inverting input

Definition at line 174 of file stm32f3xx_hal_comp_ex.h.

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STM32F373xC HAL User Manual: COMP Extended Output (STM32F373xC/STM32F378xx Product devices)

Defines
COMP Extended Output (STM32F373xC/STM32F378xx Product devices)
COMP Extended Exported Constants

Elements value convention: 00000XXX000000YYb. More...

Defines

#define | COMP_OUTPUT_NONE (0x0003U)
#define | COMP_OUTPUT_TIM2IC4 (0x0403U)
#define | COMP_OUTPUT_TIM2OCREFCLR (0x0503U)
#define | COMP_OUTPUT_TIM15BKIN (0x0101U)
#define | COMP_OUTPUT_COMP1_TIM3IC1 (0x0201U)
#define | COMP_OUTPUT_COMP1_TIM3OCREFCLR (0x0301U)
#define | COMP_OUTPUT_TIM5IC4 (0x0601U)
#define | COMP_OUTPUT_TIM5OCREFCLR (0x0701U)
#define | COMP_OUTPUT_TIM16BKIN (0x0102U)
#define | COMP_OUTPUT_TIM4IC1 (0x0202U)
#define | COMP_OUTPUT_TIM4OCREFCLR (0x0302U)
#define | COMP_OUTPUT_COMP2_TIM3IC1 (0x0602U)
#define | COMP_OUTPUT_COMP2_TIM3OCREFCLR (0x0702U)

Detailed Description

Elements value convention: 00000XXX000000YYb.

  • YY : Applicable comparator instance number (bitmap format: 01 for COMP1, 10 for COMP2)
  • XXX : COMPxOUTSEL value

Define Documentation

#define COMP_OUTPUT_COMP1_TIM3IC1 (0x0201U)

COMP1 output connected to TIM3 Input Capture 1U

Definition at line 423 of file stm32f3xx_hal_comp_ex.h.

#define COMP_OUTPUT_COMP1_TIM3OCREFCLR (0x0301U)

COMP1 output connected to TIM3 OCREF Clear

Definition at line 424 of file stm32f3xx_hal_comp_ex.h.

#define COMP_OUTPUT_COMP2_TIM3IC1 (0x0602U)

COMP2 output connected to TIM3 Input Capture 1U

Definition at line 431 of file stm32f3xx_hal_comp_ex.h.

#define COMP_OUTPUT_COMP2_TIM3OCREFCLR (0x0702U)

COMP2 output connected to TIM3 OCREF Clear

Definition at line 432 of file stm32f3xx_hal_comp_ex.h.

#define COMP_OUTPUT_NONE (0x0003U)

COMP1 or COMP2 output isn't connected to other peripherals

Definition at line 418 of file stm32f3xx_hal_comp_ex.h.

#define COMP_OUTPUT_TIM15BKIN (0x0101U)

COMP1 output connected to TIM15 Break Input

Definition at line 422 of file stm32f3xx_hal_comp_ex.h.

#define COMP_OUTPUT_TIM16BKIN (0x0102U)

COMP2 output connected to TIM16 Break Input

Definition at line 428 of file stm32f3xx_hal_comp_ex.h.

#define COMP_OUTPUT_TIM2IC4 (0x0403U)

COMP1 or COMP2 output connected to TIM2 Input Capture 4U

Definition at line 419 of file stm32f3xx_hal_comp_ex.h.

#define COMP_OUTPUT_TIM2OCREFCLR (0x0503U)

COMP1 or COMP2 output connected to TIM2 OCREF Clear

Definition at line 420 of file stm32f3xx_hal_comp_ex.h.

#define COMP_OUTPUT_TIM4IC1 (0x0202U)

COMP2 output connected to TIM4 Input Capture 1U

Definition at line 429 of file stm32f3xx_hal_comp_ex.h.

#define COMP_OUTPUT_TIM4OCREFCLR (0x0302U)

COMP2 output connected to TIM4 OCREF Clear

Definition at line 430 of file stm32f3xx_hal_comp_ex.h.

#define COMP_OUTPUT_TIM5IC4 (0x0601U)

COMP1 output connected to TIM5 Input Capture 4U

Definition at line 425 of file stm32f3xx_hal_comp_ex.h.

#define COMP_OUTPUT_TIM5OCREFCLR (0x0701U)

COMP1 output connected to TIM5 OCREF Clear

Definition at line 426 of file stm32f3xx_hal_comp_ex.h.

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STM32F373xC HAL User Manual: COMP Extended WindowMode (STM32F373xC/STM32F378xx Product devices)

Defines
COMP Extended WindowMode (STM32F373xC/STM32F378xx Product devices)
COMP Extended Exported Constants

Defines

#define | COMP_WINDOWMODE_DISABLE (0x00000000U)
#define | COMP_WINDOWMODE_ENABLE ((uint32_t)COMP_CSR_COMPxWNDWEN)

Define Documentation

#define COMP_WINDOWMODE_DISABLE (0x00000000U)

Window mode disabled

Definition at line 452 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Init().

#define COMP_WINDOWMODE_ENABLE ((uint32_t)COMP_CSR_COMPxWNDWEN)

Window mode enabled: non inverting input of comparator 2 is connected to the non inverting input of comparator 1 (PA1)

Definition at line 453 of file stm32f3xx_hal_comp_ex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Extended Mode

Defines
COMP Extended Mode
COMP Extended Exported Constants

Defines

#define | COMP_MODE_HIGHSPEED (0x00000000U)
#define | COMP_MODE_MEDIUMSPEED COMP_CSR_COMPxMODE_0
#define | COMP_MODE_LOWPOWER COMP_CSR_COMPxMODE_1
#define | COMP_MODE_ULTRALOWPOWER COMP_CSR_COMPxMODE

Define Documentation

#define COMP_MODE_HIGHSPEED (0x00000000U)

High Speed

Definition at line 476 of file stm32f3xx_hal_comp_ex.h.

#define COMP_MODE_LOWPOWER COMP_CSR_COMPxMODE_1

Low power mode

Definition at line 478 of file stm32f3xx_hal_comp_ex.h.

#define COMP_MODE_MEDIUMSPEED COMP_CSR_COMPxMODE_0

Medium Speed

Definition at line 477 of file stm32f3xx_hal_comp_ex.h.

#define COMP_MODE_ULTRALOWPOWER COMP_CSR_COMPxMODE

Ultra-low power mode

Definition at line 479 of file stm32f3xx_hal_comp_ex.h.

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STM32F373xC HAL User Manual: COMP Extended Hysteresis

Defines
COMP Extended Hysteresis
COMP Extended Exported Constants

Defines

#define | COMP_HYSTERESIS_NONE (0x00000000U)
#define | COMP_HYSTERESIS_LOW COMP_CSR_COMPxHYST_0
#define | COMP_HYSTERESIS_MEDIUM COMP_CSR_COMPxHYST_1
#define | COMP_HYSTERESIS_HIGH COMP_CSR_COMPxHYST

Define Documentation

#define COMP_HYSTERESIS_HIGH COMP_CSR_COMPxHYST

Hysteresis level high

Definition at line 496 of file stm32f3xx_hal_comp_ex.h.

#define COMP_HYSTERESIS_LOW COMP_CSR_COMPxHYST_0

Hysteresis level low

Definition at line 494 of file stm32f3xx_hal_comp_ex.h.

#define COMP_HYSTERESIS_MEDIUM COMP_CSR_COMPxHYST_1

Hysteresis level medium

Definition at line 495 of file stm32f3xx_hal_comp_ex.h.

#define COMP_HYSTERESIS_NONE (0x00000000U)

No hysteresis

Definition at line 493 of file stm32f3xx_hal_comp_ex.h.

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STM32F373xC HAL User Manual: COMP Extended Blanking Source (STM32F373xC/STM32F378xx Product devices)

Defines
COMP Extended Blanking Source (STM32F373xC/STM32F378xx Product devices)
COMP Extended Exported Constants

Defines

#define COMP_BLANKINGSRCE_NONE (0x00000000U)

Define Documentation

#define COMP_BLANKINGSRCE_NONE (0x00000000U)

No blanking source

Definition at line 592 of file stm32f3xx_hal_comp_ex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Flag

Defines
COMP Flag
COMP Extended Exported Constants

Defines

#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK

Define Documentation

#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK

Lock flag

Definition at line 603 of file stm32f3xx_hal_comp_ex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Extended Exported Macros

Defines
COMP Extended Exported Macros
COMPEx

Defines

#define | __HAL_COMP_ENABLE(__HANDLE__)
Enable the specified comparator.
#define | __HAL_COMP_DISABLE(__HANDLE__)
Disable the specified comparator.
#define | __HAL_COMP_LOCK(__HANDLE__)
Lock a comparator instance.
#define | __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)
Check whether the specified COMP flag is set or not.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP1)
Generate a software interrupt on the COMP1 EXTI line.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1)
Check whether the COMP1 EXTI line flag is set or not.
#define | __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP1)
Clear the COMP1 EXTI flag.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP2)
Generate a software interrupt on the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2)
Check whether the COMP2 EXTI line flag is set or not.
#define | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2)
Clear the COMP2 EXTI flag.

Define Documentation

#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP1)

Clear the COMP1 EXTI flag.

Return values:
None

Definition at line 801 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line in event mode.

Return values:
None

Definition at line 789 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line falling edge trigger.

Return values:
None

Definition at line 741 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line in interrupt mode.

Return values:
None

Definition at line 771 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line rising edge trigger.

Return values:
None

Definition at line 729 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
                                                               __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
                                                             } while(0U)

Disable the COMP1 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 756 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line in event mode.

Return values:
None

Definition at line 783 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line falling edge trigger.

Return values:
None

Definition at line 735 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line in interrupt mode.

Return values:
None

Definition at line 765 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line rising edge trigger.

Return values:
None

Definition at line 723 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
                                                               __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
                                                             } while(0U)

Enable the COMP1 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 747 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP1)

Generate a software interrupt on the COMP1 EXTI line.

Return values:
None

Definition at line 777 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP1_EXTI_GET_FLAG ( ) READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1)

Check whether the COMP1 EXTI line flag is set or not.

Return values:
RESET or SET

Definition at line 795 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2)

Clear the COMP2 EXTI flag.

Return values:
None

Definition at line 889 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line in event mode.

Return values:
None

Definition at line 877 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line falling edge trigger.

Return values:
None

Definition at line 829 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line in interrupt mode.

Return values:
None

Definition at line 859 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line rising edge trigger.

Return values:
None

Definition at line 817 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
                                                               __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
                                                             } while(0U)

Disable the COMP2 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 844 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line in event mode.

Return values:
None

Definition at line 871 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line falling edge trigger.

Return values:
None

Definition at line 823 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line in interrupt mode.

Return values:
None

Definition at line 853 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line rising edge trigger.

Return values:
None

Definition at line 811 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
                                                               __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
                                                             } while(0U)

Enable the COMP2 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 835 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP2)

Generate a software interrupt on the COMP2 EXTI line.

Return values:
None

Definition at line 865 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_COMP2_EXTI_GET_FLAG ( ) READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2)

Check whether the COMP2 EXTI line flag is set or not.

Return values:
RESET or SET

Definition at line 883 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_DISABLE ( __HANDLE__ )
Value:
do {                                                                   \
          uint32_t regshift = COMP_CSR_COMP1_SHIFT;                            \
                                                                               \
          if((__HANDLE__)->Instance == COMP2)                                  \
          {                                                                    \
            regshift = COMP_CSR_COMP2_SHIFT;                                   \
          }                                                                    \
          CLEAR_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift);        \
        } while(0U)

Disable the specified comparator.

Parameters:
__HANDLE__ COMP handle.
Return values:
None

Definition at line 643 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Stop().

#define __HAL_COMP_ENABLE ( __HANDLE__ )
Value:
do {                                                                   \
          uint32_t regshift = COMP_CSR_COMP1_SHIFT;                            \
                                                                               \
          if((__HANDLE__)->Instance == COMP2)                                  \
          {                                                                    \
            regshift = COMP_CSR_COMP2_SHIFT;                                   \
          }                                                                    \
          SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift);          \
        } while(0U)

Enable the specified comparator.

Parameters:
__HANDLE__ COMP handle.
Return values:
None

Definition at line 627 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Start(), and HAL_COMP_Start_IT().

#define __HAL_COMP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((__HANDLE__)->Instance == COMP1) ? (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__)) \
         (((__HANDLE__)->Instance->CSR & (uint32_t)((__FLAG__) << COMP_CSR_COMP2_SHIFT) == (__FLAG__))))

Check whether the specified COMP flag is set or not.

Parameters:
__HANDLE__ COMP Handle.
__FLAG__ flag to check. This parameter can be one of the following values:
  • COMP_FLAG_LOCK lock flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 677 of file stm32f3xx_hal_comp_ex.h.

#define __HAL_COMP_LOCK ( __HANDLE__ )
Value:
do {                                                                   \
          uint32_t regshift = COMP_CSR_COMP1_SHIFT;                            \
                                                                               \
          if((__HANDLE__)->Instance == COMP2)                                  \
          {                                                                    \
            regshift = COMP_CSR_COMP2_SHIFT;                                   \
          }                                                                    \
          SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxLOCK << regshift);        \
        } while(0U)

Lock a comparator instance.

Parameters:
__HANDLE__ COMP handle
Return values:
None.

Definition at line 659 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Lock().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Extended EXTI lines

Defines
COMP Extended EXTI lines
COMP Extended Private Constants

Defines

#define | COMP_EXTI_LINE_COMP1 EXTI_IMR_MR21
#define | COMP_EXTI_LINE_COMP2 EXTI_IMR_MR22

Define Documentation

#define COMP_EXTI_LINE_COMP1 EXTI_IMR_MR21

External interrupt line 21 connected to COMP1

Definition at line 1403 of file stm32f3xx_hal_comp_ex.h.

#define COMP_EXTI_LINE_COMP2 EXTI_IMR_MR22

External interrupt line 22 connected to COMP2

Definition at line 1404 of file stm32f3xx_hal_comp_ex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Extended miscellaneous defines

Defines
COMP Extended miscellaneous defines
COMP Extended Private Constants

Defines

#define | COMP_CSR_COMPxINSEL_MASK COMP_CSR_COMPxINSEL
#define | COMP_CSR_COMPxOUTSEL_MASK COMP_CSR_COMPxOUTSEL
#define | COMP_CSR_COMPxPOL_MASK COMP_CSR_COMPxPOL
#define | COMP_CSR_RESET_VALUE (0x00000000U)
#define | COMP_CSR_RESET_PARAMETERS_MASK (0x00003FFFU)
#define | COMP_CSR_UPDATE_PARAMETERS_MASK (0x00003FFEU)
#define | COMP_CSR_COMP1_SHIFT 0U
#define | COMP_CSR_COMP2_SHIFT 16U
#define | COMP_CSR_COMPxNONINSEL_MASK (COMP_CSR_COMP1SW1)
#define | COMP_CSR_COMPxWNDWEN_MASK COMP_CSR_COMPxWNDWEN
#define | COMP_CSR_COMPxMODE_MASK COMP_CSR_COMPxMODE
#define | COMP_CSR_COMPxHYST_MASK COMP_CSR_COMPxHYST
#define | COMP_CSR_COMPxBLANKING_MASK (0x00000000U)

Define Documentation

#define COMP_CSR_COMP1_SHIFT 0U

Definition at line 1426 of file stm32f3xx_hal_comp_ex.h.

#define COMP_CSR_COMP2_SHIFT 16U

Definition at line 1427 of file stm32f3xx_hal_comp_ex.h.

#define COMP_CSR_COMPxBLANKING_MASK (0x00000000U)

Mask empty: feature not available

Definition at line 1470 of file stm32f3xx_hal_comp_ex.h.

#define COMP_CSR_COMPxHYST_MASK COMP_CSR_COMPxHYST

COMP_CSR_COMPxHYST Mask

Definition at line 1469 of file stm32f3xx_hal_comp_ex.h.

#define COMP_CSR_COMPxINSEL_MASK COMP_CSR_COMPxINSEL

COMP_CSR_COMPxINSEL Mask

Definition at line 1417 of file stm32f3xx_hal_comp_ex.h.

#define COMP_CSR_COMPxMODE_MASK COMP_CSR_COMPxMODE

COMP_CSR_COMPxMODE Mask

Definition at line 1468 of file stm32f3xx_hal_comp_ex.h.

#define COMP_CSR_COMPxNONINSEL_MASK (COMP_CSR_COMP1SW1)

COMP_CSR_COMPxNONINSEL mask

Definition at line 1466 of file stm32f3xx_hal_comp_ex.h.

#define COMP_CSR_COMPxOUTSEL_MASK COMP_CSR_COMPxOUTSEL

COMP_CSR_COMPxOUTSEL Mask

Definition at line 1418 of file stm32f3xx_hal_comp_ex.h.

#define COMP_CSR_COMPxPOL_MASK COMP_CSR_COMPxPOL

COMP_CSR_COMPxPOL Mask

Definition at line 1419 of file stm32f3xx_hal_comp_ex.h.

#define COMP_CSR_COMPxWNDWEN_MASK COMP_CSR_COMPxWNDWEN

COMP_CSR_COMPxWNDWEN mask

Definition at line 1467 of file stm32f3xx_hal_comp_ex.h.

#define COMP_CSR_RESET_PARAMETERS_MASK (0x00003FFFU)

Definition at line 1423 of file stm32f3xx_hal_comp_ex.h.

#define COMP_CSR_RESET_VALUE (0x00000000U)

Definition at line 1422 of file stm32f3xx_hal_comp_ex.h.

#define COMP_CSR_UPDATE_PARAMETERS_MASK (0x00003FFEU)

Definition at line 1424 of file stm32f3xx_hal_comp_ex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Extended Private macro to get the EXTI line associated with a comparator handle

Defines
COMP Extended Private macro to get the EXTI line associated with a comparator handle
COMP Extended Private Macros

Defines

#define COMP_GET_EXTI_LINE(__INSTANCE__)
Get the specified EXTI line for a comparator instance.

Define Documentation

#define COMP_GET_EXTI_LINE ( __INSTANCE__ )
Value:
(((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
                                          COMP_EXTI_LINE_COMP2)

Get the specified EXTI line for a comparator instance.

Parameters:
__INSTANCE__ specifies the COMP instance.
Return values:
value of COMP Extended EXTI lines

Definition at line 1538 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_IRQHandler(), HAL_COMP_Start(), HAL_COMP_Start_IT(), HAL_COMP_Stop(), and HAL_COMP_Stop_IT().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Extended miscellaneous private macros

Defines
COMP Extended miscellaneous private macros
COMP Extended Private Macros

Defines

#define | COMP_INIT(__HANDLE__)
Init a comparator instance.
#define | COMP_DEINIT(__HANDLE__)
DeInit a comparator instance.
#define | COMP_EXTI_RISING_ENABLE(__EXTILINE__) SET_BIT(EXTI->RTSR, (__EXTILINE__))
Enable the Exti Line rising edge trigger.
#define | COMP_EXTI_RISING_DISABLE(__EXTILINE__) CLEAR_BIT(EXTI->RTSR, (__EXTILINE__))
Disable the Exti Line rising edge trigger.
#define | COMP_EXTI_FALLING_ENABLE(__EXTILINE__) SET_BIT(EXTI->FTSR, (__EXTILINE__))
Enable the Exti Line falling edge trigger.
#define | COMP_EXTI_FALLING_DISABLE(__EXTILINE__) CLEAR_BIT(EXTI->FTSR, (__EXTILINE__))
Disable the Exti Line falling edge trigger.
#define | COMP_EXTI_ENABLE_IT(__EXTILINE__) SET_BIT(EXTI->IMR, (__EXTILINE__))
Enable the COMP Exti Line interrupt generation.
#define | COMP_EXTI_DISABLE_IT(__EXTILINE__) CLEAR_BIT(EXTI->IMR, (__EXTILINE__))
Disable the COMP Exti Line interrupt generation.
#define | COMP_EXTI_ENABLE_EVENT(__EXTILINE__) SET_BIT(EXTI->EMR, (__EXTILINE__))
Enable the COMP Exti Line event generation.
#define | COMP_EXTI_DISABLE_EVENT(__EXTILINE__) CLEAR_BIT(EXTI->EMR, (__EXTILINE__))
Disable the COMP Exti Line event generation.
#define | COMP_EXTI_GET_FLAG(__FLAG__) READ_BIT(EXTI->PR, (__FLAG__))
Check whether the specified EXTI line flag is set or not.
#define | COMP_EXTI_CLEAR_FLAG(__FLAG__) WRITE_REG(EXTI->PR, (__FLAG__))
Clear the COMP Exti flags.
#define | COMP_INVERTINGINPUT_SELECTION(__COMP_INSTANCE__, __INVERTINGINPUT__) (__INVERTINGINPUT__)
Manage inverting input comparator inverting input connected to a GPIO for STM32F302x, STM32F32xx, STM32F33x.

Define Documentation

#define COMP_DEINIT ( __HANDLE__ )
Value:
do {                                                                   \
          uint32_t regshift = COMP_CSR_COMP1_SHIFT;                            \
                                                                               \
          if((__HANDLE__)->Instance == COMP2)                                  \
          {                                                                    \
            regshift = COMP_CSR_COMP2_SHIFT;                                   \
          }                                                                    \
          MODIFY_REG(COMP->CSR,                                                \
                     COMP_CSR_RESET_PARAMETERS_MASK << regshift,               \
                     COMP_CSR_RESET_VALUE << regshift);                        \
        } while(0U)

DeInit a comparator instance.

Parameters:
__HANDLE__ COMP handle
Return values:
None.

Definition at line 1590 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_DeInit().

#define COMP_EXTI_CLEAR_FLAG ( __FLAG__ ) WRITE_REG(EXTI->PR, (__FLAG__))

Clear the COMP Exti flags.

Parameters:
__FLAG__ specifies the COMP Exti sources to be cleared. This parameter can be a value of COMP Extended EXTI lines
Return values:
None.

Definition at line 1682 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_IRQHandler(), HAL_COMP_Start(), and HAL_COMP_Start_IT().

#define COMP_EXTI_DISABLE_EVENT ( __EXTILINE__ ) CLEAR_BIT(EXTI->EMR, (__EXTILINE__))

Disable the COMP Exti Line event generation.

Parameters:
__EXTILINE__ specifies the COMP Exti sources to be disabled. This parameter can be a value of COMP Extended EXTI lines
Return values:
None.

Definition at line 1666 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Stop().

#define COMP_EXTI_DISABLE_IT ( __EXTILINE__ ) CLEAR_BIT(EXTI->IMR, (__EXTILINE__))

Disable the COMP Exti Line interrupt generation.

Parameters:
__EXTILINE__ specifies the COMP Exti sources to be disabled. This parameter can be a value of COMP Extended EXTI lines
Return values:
None.

Definition at line 1650 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Stop_IT().

#define COMP_EXTI_ENABLE_EVENT ( __EXTILINE__ ) SET_BIT(EXTI->EMR, (__EXTILINE__))

Enable the COMP Exti Line event generation.

Parameters:
__EXTILINE__ specifies the COMP Exti sources to be enabled. This parameter can be a value of COMP Extended EXTI lines
Return values:
None.

Definition at line 1658 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Start().

#define COMP_EXTI_ENABLE_IT ( __EXTILINE__ ) SET_BIT(EXTI->IMR, (__EXTILINE__))

Enable the COMP Exti Line interrupt generation.

Parameters:
__EXTILINE__ specifies the COMP Exti sources to be enabled. This parameter can be a value of COMP Extended EXTI lines
Return values:
None.

Definition at line 1642 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Start_IT().

#define COMP_EXTI_FALLING_DISABLE ( __EXTILINE__ ) CLEAR_BIT(EXTI->FTSR, (__EXTILINE__))

Disable the Exti Line falling edge trigger.

Parameters:
__EXTILINE__ specifies the COMP Exti sources to be disabled. This parameter can be a value of COMP Extended EXTI lines
Return values:
None.

Definition at line 1634 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Start(), and HAL_COMP_Start_IT().

#define COMP_EXTI_FALLING_ENABLE ( __EXTILINE__ ) SET_BIT(EXTI->FTSR, (__EXTILINE__))

Enable the Exti Line falling edge trigger.

Parameters:
__EXTILINE__ specifies the COMP Exti sources to be enabled. This parameter can be a value of COMP Extended EXTI lines
Return values:
None.

Definition at line 1626 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Start(), and HAL_COMP_Start_IT().

#define COMP_EXTI_GET_FLAG ( __FLAG__ ) READ_BIT(EXTI->PR, (__FLAG__))

Check whether the specified EXTI line flag is set or not.

Parameters:
__FLAG__ specifies the COMP Exti sources to be checked. This parameter can be a value of COMP Extended EXTI lines
Return values:
The state of __FLAG__ (SET or RESET).

Definition at line 1674 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_IRQHandler().

#define COMP_EXTI_RISING_DISABLE ( __EXTILINE__ ) CLEAR_BIT(EXTI->RTSR, (__EXTILINE__))

Disable the Exti Line rising edge trigger.

Parameters:
__EXTILINE__ specifies the COMP Exti sources to be disabled. This parameter can be a value of COMP Extended EXTI lines
Return values:
None.

Definition at line 1618 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Start(), and HAL_COMP_Start_IT().

#define COMP_EXTI_RISING_ENABLE ( __EXTILINE__ ) SET_BIT(EXTI->RTSR, (__EXTILINE__))

Enable the Exti Line rising edge trigger.

Parameters:
__EXTILINE__ specifies the COMP Exti sources to be enabled. This parameter can be a value of COMP Extended EXTI lines
Return values:
None.

Definition at line 1610 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Start(), and HAL_COMP_Start_IT().

#define COMP_INIT ( __HANDLE__ )
Value:
do {                                                                           \
          uint32_t regshift = COMP_CSR_COMP1_SHIFT;                                    \
          uint32_t compoutput = (__HANDLE__)->Init.Output & COMP_CSR_COMPxOUTSEL_MASK; \
                                                                                \
          if((__HANDLE__)->Instance == COMP2)                                          \
          {                                                                            \
            regshift = COMP_CSR_COMP2_SHIFT;                                           \
          }                                                                            \
                                                                                \
          MODIFY_REG(COMP->CSR,                                                        \
                     (COMP_CSR_COMPxINSEL  | COMP_CSR_COMPxNONINSEL_MASK |             \
                     COMP_CSR_COMPxOUTSEL  | COMP_CSR_COMPxPOL           |             \
                     COMP_CSR_COMPxHYST    | COMP_CSR_COMPxMODE) << regshift,          \
                     ((__HANDLE__)->Init.InvertingInput    |                           \
                     (__HANDLE__)->Init.NonInvertingInput  |                           \
                     compoutput                            |                           \
                     (__HANDLE__)->Init.OutputPol          |                           \
                     (__HANDLE__)->Init.Hysteresis         |                           \
                     (__HANDLE__)->Init.Mode) << regshift);                            \
                                                                                \
          if((__HANDLE__)->Init.WindowMode != COMP_WINDOWMODE_DISABLE)                 \
          {                                                                            \
            COMP->CSR |= COMP_CSR_WNDWEN;                                              \
          }                                                                            \
        } while(0U)

Init a comparator instance.

Parameters:
__HANDLE__ COMP handle
Note:
The common output selection is checked versus the COMP instance to set the right output configuration
Return values:
None.

Definition at line 1558 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Init().

#define COMP_INVERTINGINPUT_SELECTION | ( | __COMP_INSTANCE__,
 |  | __INVERTINGINPUT__
 | ) | (__INVERTINGINPUT__)

Manage inverting input comparator inverting input connected to a GPIO for STM32F302x, STM32F32xx, STM32F33x.

  • On devices STM32F302x, STM32F32xx, STM32F33x, there is only 1 comparator inverting input connected to a GPIO. Legacy definition of literal COMP_INVERTINGINPUT_IO1 was initially the only selection, but depending on comparator instance it corresponds to COMP_INVERTINGINPUT_IO2 (for instances COMP4, COMP6). Since, COMP_INVERTINGINPUT_IO2 has been created and this macro selects the correct literal COMP_INVERTINGINPUT_IOx in function of comparator instance.
  • On other STM32F3 devices, this macro performs no action.
    Parameters:
    __COMP_INSTANCE__ | COMP instance
    __INVERTINGINPUT__ | COMP inverting input
    Return values:
    None.

Definition at line 1833 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Init().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Extended Private macros to check input parameters

Defines
COMP Extended Private macros to check input parameters
COMP Extended Private Macros

Defines

#define | IS_COMP_INVERTINGINPUT(INPUT)
#define | IS_COMP_NONINVERTINGINPUT(INPUT)
#define | IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT)
#define | IS_COMP_WINDOWMODE(WINDOWMODE)
#define | IS_COMP_MODE(MODE)
#define | IS_COMP_HYSTERESIS(HYSTERESIS)
#define | IS_COMP_OUTPUT(OUTPUT)
#define | IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT)
#define | IS_COMP_BLANKINGSRCE(SOURCE) ((SOURCE) == (SOURCE))
#define | IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE)

Define Documentation

#define IS_COMP_BLANKINGSRCE ( SOURCE ) ((SOURCE) == (SOURCE))

Not available: check always true

Definition at line 2764 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_BLANKINGSRCE_INSTANCE | ( | INSTANCE,
 |  | BLANKINGSRCE
 | ) |
Value:
((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2))  &&     \
     ((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE))

Definition at line 2767 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_HYSTERESIS ( HYSTERESIS )
Value:
(((HYSTERESIS) == COMP_HYSTERESIS_NONE)   || \
                                           ((HYSTERESIS) == COMP_HYSTERESIS_LOW)    || \
                                           ((HYSTERESIS) == COMP_HYSTERESIS_MEDIUM) || \
                                           ((HYSTERESIS) == COMP_HYSTERESIS_HIGH))

Definition at line 2724 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_INVERTINGINPUT ( INPUT )
Value:
(((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT)       || \
                                       ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT)       || \
                                       ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT)       || \
                                       ((INPUT) == COMP_INVERTINGINPUT_VREFINT)          || \
                                       ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1)         || \
                                       ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH2)         || \
                                       ((INPUT) == COMP_INVERTINGINPUT_IO1)              || \
                                       ((INPUT) == COMP_INVERTINGINPUT_DAC2_CH1))

Definition at line 2696 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_MODE ( MODE )
Value:
(((MODE) == COMP_MODE_HIGHSPEED)     || \
                             ((MODE) == COMP_MODE_MEDIUMSPEED)   || \
                             ((MODE) == COMP_MODE_LOWPOWER)      || \
                             ((MODE) == COMP_MODE_ULTRALOWPOWER))

Definition at line 2719 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_NONINVERTINGINPUT ( INPUT )
Value:
(((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
                                          ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))

Definition at line 2705 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_NONINVERTINGINPUT_INSTANCE | ( | INSTANCE,
 |  | INPUT
 | ) |
Value:
((((INSTANCE) == COMP1)  &&                                 \
    (((INPUT) == COMP_NONINVERTINGINPUT_IO1)                || \
     ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED)))    \
    ||                                                         \
    (((INPUT) == COMP_NONINVERTINGINPUT_IO1)))

Definition at line 2709 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == COMP_OUTPUT_NONE)                || \
                                ((OUTPUT) == COMP_OUTPUT_TIM2IC4)             || \
                                ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)        || \
                                ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3IC1)       || \
                                ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3OCREFCLR)  || \
                                ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3IC1)       || \
                                ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3OCREFCLR)  || \
                                ((OUTPUT) == COMP_OUTPUT_TIM4IC1)             || \
                                ((OUTPUT) == COMP_OUTPUT_TIM4OCREFCLR)        || \
                                ((OUTPUT) == COMP_OUTPUT_TIM5IC4)             || \
                                ((OUTPUT) == COMP_OUTPUT_TIM5OCREFCLR)        || \
                                ((OUTPUT) == COMP_OUTPUT_TIM15BKIN)           || \
                                ((OUTPUT) == COMP_OUTPUT_TIM16BKIN))

Definition at line 2729 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_OUTPUT_INSTANCE | ( | INSTANCE,
 |  | OUTPUT
 | ) |
Value:
((((INSTANCE) == COMP1)  &&                         \
    (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
     ((OUTPUT) == COMP_OUTPUT_TIM2IC4)            ||   \
     ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)       ||   \
     ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3IC1)      ||   \
     ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3OCREFCLR) ||   \
     ((OUTPUT) == COMP_OUTPUT_TIM5IC4)            ||   \
     ((OUTPUT) == COMP_OUTPUT_TIM5OCREFCLR)       ||   \
     ((OUTPUT) == COMP_OUTPUT_TIM15BKIN)))             \
    ||                                                 \
    (((INSTANCE) == COMP2)  &&                         \
    (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
     ((OUTPUT) == COMP_OUTPUT_TIM2IC4)            ||   \
     ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)       ||   \
     ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3IC1)      ||   \
     ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3OCREFCLR) ||   \
     ((OUTPUT) == COMP_OUTPUT_TIM4IC1)            ||   \
     ((OUTPUT) == COMP_OUTPUT_TIM4OCREFCLR)       ||   \
     ((OUTPUT) == COMP_OUTPUT_TIM16BKIN))))

Definition at line 2743 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_WINDOWMODE ( WINDOWMODE )
Value:
(((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \
                                        ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE))

Definition at line 2716 of file stm32f3xx_hal_comp_ex.h.

Referenced by HAL_COMP_Init().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CORTEX Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (pre-emption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]
      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
      Systick functionalities

Function Documentation

void HAL_NVIC_DisableIRQ ( IRQn_Type IRQn )

Disables a device specific interrupt in the NVIC interrupt controller.

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
Return values:
None

Definition at line 245 of file stm32f3xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_EnableIRQ ( IRQn_Type IRQn )

Enables a device specific interrupt in the NVIC interrupt controller.

Note:
To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() function should be called before.
Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
Return values:
None

Definition at line 229 of file stm32f3xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_SetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PreemptPriority,
 |  | uint32_t | SubPriority
 | ) |  |

Sets the priority of an interrupt.

Parameters:
IRQn | External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
PreemptPriority | The pre-emption priority for the IRQn channel. This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table A lower priority value indicates a higher priority
SubPriority | the subpriority level for the IRQ channel. This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table A lower priority value indicates a higher priority.
Return values:
None

Definition at line 207 of file stm32f3xx_hal_cortex.c.

References assert_param, IS_NVIC_PREEMPTION_PRIORITY, and IS_NVIC_SUB_PRIORITY.

Referenced by HAL_InitTick().

void HAL_NVIC_SetPriorityGrouping ( uint32_t PriorityGroup )

Sets the priority grouping field (pre-emption priority and subpriority) using the required unlock sequence.

Parameters:
PriorityGroup The priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority 1 bits for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority 0 bits for subpriority
Note:
When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. The pending IRQ priority will be managed only by the subpriority.
Return values:
None

Definition at line 185 of file stm32f3xx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

Referenced by HAL_Init().

void HAL_NVIC_SystemReset ( void )

Initiates a system reset request to reset the MCU.

Return values:
None

Definition at line 258 of file stm32f3xx_hal_cortex.c.

uint32_t HAL_SYSTICK_Config ( uint32_t TicksNumb )

Initializes the System Timer and its interrupt, and starts the System Tick Timer.

Counter is in free running mode to generate periodic interrupts.

Parameters:
TicksNumb Specifies the ticks Number of ticks between two interrupts.
Return values:
status,: - 0 Function succeeded.
  • 1 Function failed.

Definition at line 271 of file stm32f3xx_hal_cortex.c.

Referenced by HAL_InitTick().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CORTEX Exported Functions

Cortex control functions. More...

Functions

void | HAL_MPU_Disable (void)
Disables the MPU also clears the HFNMIENA bit (ARM recommendation)
void | HAL_MPU_Enable (uint32_t MPU_Control)
Enables the MPU.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initializes and configures the Region and the memory to be protected.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.

Detailed Description

Cortex control functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
    [..]
      This subsection provides a set of functions allowing to control the CORTEX
      (NVIC, SYSTICK, MPU) functionalities.

Function Documentation

void HAL_MPU_ConfigRegion ( MPU_Region_InitTypeDef * MPU_Init )

Initializes and configures the Region and the memory to be protected.

Parameters:
MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains the initialization and configuration information.
Return values:
None

Definition at line 336 of file stm32f3xx_hal_cortex.c.

References MPU_Region_InitTypeDef::AccessPermission, assert_param, MPU_Region_InitTypeDef::BaseAddress, MPU_Region_InitTypeDef::DisableExec, MPU_Region_InitTypeDef::Enable, IS_MPU_ACCESS_BUFFERABLE, IS_MPU_ACCESS_CACHEABLE, IS_MPU_ACCESS_SHAREABLE, IS_MPU_INSTRUCTION_ACCESS, IS_MPU_REGION_ENABLE, IS_MPU_REGION_NUMBER, IS_MPU_REGION_PERMISSION_ATTRIBUTE, IS_MPU_REGION_SIZE, IS_MPU_SUB_REGION_DISABLE, IS_MPU_TEX_LEVEL, MPU_Region_InitTypeDef::IsBufferable, MPU_Region_InitTypeDef::IsCacheable, MPU_Region_InitTypeDef::IsShareable, MPU_Region_InitTypeDef::Number, MPU_Region_InitTypeDef::Size, MPU_Region_InitTypeDef::SubRegionDisable, and MPU_Region_InitTypeDef::TypeExtField.

void HAL_MPU_Disable ( void )

Disables the MPU also clears the HFNMIENA bit (ARM recommendation)

Return values:
None

Definition at line 301 of file stm32f3xx_hal_cortex.c.

void HAL_MPU_Enable ( uint32_t MPU_Control )

Enables the MPU.

Parameters:
MPU_Control Specifies the control mode of the MPU during hard fault, NMI, FAULTMASK and privileged access to the default memory This parameter can be one of the following values:
  • MPU_HFNMI_PRIVDEF_NONE
  • MPU_HARDFAULT_NMI
  • MPU_PRIVILEGED_DEFAULT
  • MPU_HFNMI_PRIVDEF
Return values:
None

Definition at line 321 of file stm32f3xx_hal_cortex.c.

void HAL_NVIC_ClearPendingIRQ ( IRQn_Type IRQn )

Clears the pending bit of an external interrupt.

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
Return values:
None

Definition at line 450 of file stm32f3xx_hal_cortex.c.

uint32_t HAL_NVIC_GetActive ( IRQn_Type IRQn )

Gets active interrupt ( reads the active register in NVIC and returns the active bit).

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
Return values:
status,: - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 464 of file stm32f3xx_hal_cortex.c.

uint32_t HAL_NVIC_GetPendingIRQ ( IRQn_Type IRQn )

Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
Return values:
status,: - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 437 of file stm32f3xx_hal_cortex.c.

void HAL_NVIC_GetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PriorityGroup,
 |  | uint32_t * | pPreemptPriority,
 |  | uint32_t * | pSubPriority
 | ) |  |

Gets the priority of an interrupt.

Parameters:
IRQn | External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
PriorityGroup,: the priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority 1 bits for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority 0 bits for subpriority
pPreemptPriority | Pointer on the Preemptive priority value (starting from 0).
pSubPriority | Pointer on the Subpriority value (starting from 0).
Return values:
None

Definition at line 407 of file stm32f3xx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

uint32_t HAL_NVIC_GetPriorityGrouping ( void )

Gets the priority grouping field from the NVIC Interrupt Controller.

Return values:
Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)

Definition at line 380 of file stm32f3xx_hal_cortex.c.

void HAL_NVIC_SetPendingIRQ ( IRQn_Type IRQn )

Sets Pending bit of an external interrupt.

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
Return values:
None

Definition at line 422 of file stm32f3xx_hal_cortex.c.

void HAL_SYSTICK_Callback ( void )

SYSTICK callback.

Return values:
None

Definition at line 505 of file stm32f3xx_hal_cortex.c.

Referenced by HAL_SYSTICK_IRQHandler().

void HAL_SYSTICK_CLKSourceConfig ( uint32_t CLKSource )

Configures the SysTick clock source.

Parameters:
CLKSource specifies the SysTick clock source. This parameter can be one of the following values:
  • SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
  • SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
Return values:
None

Definition at line 478 of file stm32f3xx_hal_cortex.c.

References assert_param, IS_SYSTICK_CLK_SOURCE, and SYSTICK_CLKSOURCE_HCLK.

void HAL_SYSTICK_IRQHandler ( void )

This function handles SYSTICK interrupt request.

Return values:
None

Definition at line 496 of file stm32f3xx_hal_cortex.c.

References HAL_SYSTICK_Callback().

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STM32F373xC HAL User Manual: MPU_Region_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MPU_Region_InitTypeDef Struct Reference
MPU Region Initialization Structure Definition

#include <stm32f3xx_hal_cortex.h>

Data Fields

uint8_t | Enable
uint8_t | Number
uint32_t | BaseAddress
uint8_t | Size
uint8_t | SubRegionDisable
uint8_t | TypeExtField
uint8_t | AccessPermission
uint8_t | DisableExec
uint8_t | IsShareable
uint8_t | IsCacheable
uint8_t | IsBufferable

Detailed Description

Definition at line 64 of file stm32f3xx_hal_cortex.h.

Field Documentation

uint8_t MPU_Region_InitTypeDef::AccessPermission

Specifies the region access permission type. This parameter can be a value of CORTEX MPU Region Permission Attributes

Definition at line 77 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint32_t MPU_Region_InitTypeDef::BaseAddress

Specifies the base address of the region to protect.

Definition at line 70 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::DisableExec

Specifies the instruction access status. This parameter can be a value of CORTEX MPU Instruction Access

Definition at line 79 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Enable

Specifies the status of the region. This parameter can be a value of CORTEX MPU Region Enable

Definition at line 66 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsBufferable

Specifies the bufferable status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Bufferable

Definition at line 85 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsCacheable

Specifies the cacheable status of the region protected. This parameter can be a value of CORTEX MPU Instruction Access Cacheable

Definition at line 83 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsShareable

Specifies the shareability status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Shareable

Definition at line 81 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Number

Specifies the number of the region to protect. This parameter can be a value of CORTEX MPU Region Number

Definition at line 68 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Size

Specifies the size of the region to protect. This parameter can be a value of CORTEX MPU Region Size

Definition at line 71 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::SubRegionDisable

Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 73 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::TypeExtField

Specifies the TEX field level. This parameter can be a value of MPU TEX Levels

Definition at line 75 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_cortex.h
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STM32F373xC HAL User Manual: CORTEX Preemption Priority Group

Defines
CORTEX Preemption Priority Group
CORTEX Exported Constants

Defines

#define | NVIC_PRIORITYGROUP_0 (0x00000007U)
#define | NVIC_PRIORITYGROUP_1 (0x00000006U)
#define | NVIC_PRIORITYGROUP_2 (0x00000005U)
#define | NVIC_PRIORITYGROUP_3 (0x00000004U)
#define | NVIC_PRIORITYGROUP_4 (0x00000003U)

Define Documentation

#define NVIC_PRIORITYGROUP_0 (0x00000007U)

0 bits for pre-emption priority 4 bits for subpriority

Definition at line 106 of file stm32f3xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_1 (0x00000006U)

1 bits for pre-emption priority 3 bits for subpriority

Definition at line 108 of file stm32f3xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_2 (0x00000005U)

2 bits for pre-emption priority 2 bits for subpriority

Definition at line 110 of file stm32f3xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_3 (0x00000004U)

3 bits for pre-emption priority 1 bits for subpriority

Definition at line 112 of file stm32f3xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_4 (0x00000003U)

4 bits for pre-emption priority 0 bits for subpriority

Definition at line 114 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_Init().

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STM32F373xC HAL User Manual: CORTEX SysTick clock source

Defines
CORTEX SysTick clock source
CORTEX Exported Constants

Defines

#define | SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U)
#define | SYSTICK_CLKSOURCE_HCLK (0x00000004U)

Define Documentation

#define SYSTICK_CLKSOURCE_HCLK (0x00000004U)

Definition at line 124 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U)

Definition at line 123 of file stm32f3xx_hal_cortex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: MPU HFNMI and PRIVILEGED Access control

Defines
MPU HFNMI and PRIVILEGED Access control
CORTEX Exported Constants

Defines

#define | MPU_HFNMI_PRIVDEF_NONE (0x00000000U)
#define | MPU_HARDFAULT_NMI (0x00000002U)
#define | MPU_PRIVILEGED_DEFAULT (0x00000004U)
#define | MPU_HFNMI_PRIVDEF (0x00000006U)

Define Documentation

#define MPU_HARDFAULT_NMI (0x00000002U)

Definition at line 134 of file stm32f3xx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF (0x00000006U)

Definition at line 136 of file stm32f3xx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF_NONE (0x00000000U)

Definition at line 133 of file stm32f3xx_hal_cortex.h.

#define MPU_PRIVILEGED_DEFAULT (0x00000004U)

Definition at line 135 of file stm32f3xx_hal_cortex.h.

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STM32F373xC HAL User Manual: CORTEX MPU Region Enable

Defines
CORTEX MPU Region Enable
CORTEX Exported Constants

Defines

#define | MPU_REGION_ENABLE ((uint8_t)0x01U)
#define | MPU_REGION_DISABLE ((uint8_t)0x00U)

Define Documentation

#define MPU_REGION_DISABLE ((uint8_t)0x00U)

Definition at line 145 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_ENABLE ((uint8_t)0x01U)

Definition at line 144 of file stm32f3xx_hal_cortex.h.

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STM32F373xC HAL User Manual: CORTEX MPU Instruction Access

Defines
CORTEX MPU Instruction Access
CORTEX Exported Constants

Defines

#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)

Define Documentation

#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)

Definition at line 154 of file stm32f3xx_hal_cortex.h.

#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)

Definition at line 153 of file stm32f3xx_hal_cortex.h.

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STM32F373xC HAL User Manual: CORTEX MPU Instruction Access Shareable

Defines
CORTEX MPU Instruction Access Shareable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)

Define Documentation

#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)

Definition at line 163 of file stm32f3xx_hal_cortex.h.

#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)

Definition at line 162 of file stm32f3xx_hal_cortex.h.

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STM32F373xC HAL User Manual: CORTEX MPU Instruction Access Cacheable

Defines
CORTEX MPU Instruction Access Cacheable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)

Define Documentation

#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)

Definition at line 171 of file stm32f3xx_hal_cortex.h.

#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)

Definition at line 172 of file stm32f3xx_hal_cortex.h.

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STM32F373xC HAL User Manual: CORTEX MPU Instruction Access Bufferable

Defines
CORTEX MPU Instruction Access Bufferable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)

Define Documentation

#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)

Definition at line 180 of file stm32f3xx_hal_cortex.h.

#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)

Definition at line 181 of file stm32f3xx_hal_cortex.h.

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STM32F373xC HAL User Manual: MPU TEX Levels

Defines
MPU TEX Levels
CORTEX Exported Constants

Defines

#define | MPU_TEX_LEVEL0 ((uint8_t)0x00U)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01U)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02U)

Define Documentation

#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)

Definition at line 189 of file stm32f3xx_hal_cortex.h.

#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)

Definition at line 190 of file stm32f3xx_hal_cortex.h.

#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)

Definition at line 191 of file stm32f3xx_hal_cortex.h.

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STM32F373xC HAL User Manual: CORTEX MPU Region Size

Defines
CORTEX MPU Region Size
CORTEX Exported Constants

Defines

#define | MPU_REGION_SIZE_32B ((uint8_t)0x04U)
#define | MPU_REGION_SIZE_64B ((uint8_t)0x05U)
#define | MPU_REGION_SIZE_128B ((uint8_t)0x06U)
#define | MPU_REGION_SIZE_256B ((uint8_t)0x07U)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08U)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)

Define Documentation

#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)

Definition at line 201 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)

Definition at line 211 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)

Definition at line 221 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)

Definition at line 208 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)

Definition at line 218 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)

Definition at line 224 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)

Definition at line 204 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)

Definition at line 214 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)

Definition at line 202 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)

Definition at line 212 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)

Definition at line 222 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)

Definition at line 225 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)

Definition at line 205 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)

Definition at line 215 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)

Definition at line 199 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)

Definition at line 209 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)

Definition at line 219 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)

Definition at line 226 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)

Definition at line 206 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)

Definition at line 216 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)

Definition at line 203 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)

Definition at line 213 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)

Definition at line 223 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)

Definition at line 200 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)

Definition at line 210 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)

Definition at line 220 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)

Definition at line 207 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)

Definition at line 217 of file stm32f3xx_hal_cortex.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CORTEX MPU Region Permission Attributes

Defines
CORTEX MPU Region Permission Attributes
CORTEX Exported Constants

Defines

#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01U)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05U)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)

Define Documentation

#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)

Definition at line 237 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)

Definition at line 234 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)

Definition at line 238 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)

Definition at line 239 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)

Definition at line 235 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)

Definition at line 236 of file stm32f3xx_hal_cortex.h.

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STM32F373xC HAL User Manual: CORTEX MPU Region Number

Defines
CORTEX MPU Region Number
CORTEX Exported Constants

Defines

#define | MPU_REGION_NUMBER0 ((uint8_t)0x00U)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01U)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02U)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03U)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04U)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05U)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06U)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07U)

Define Documentation

#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)

Definition at line 247 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)

Definition at line 248 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)

Definition at line 249 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)

Definition at line 250 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)

Definition at line 251 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)

Definition at line 252 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)

Definition at line 253 of file stm32f3xx_hal_cortex.h.

#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)

Definition at line 254 of file stm32f3xx_hal_cortex.h.

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STM32F373xC HAL User Manual: CORTEX SysTick clock source

Defines
CORTEX SysTick clock source
CORTEX Private Macros

Defines

#define IS_SYSTICK_CLK_SOURCE(SOURCE)

Define Documentation

#define IS_SYSTICK_CLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))

Definition at line 332 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CORTEX Private Macros

Modules | Defines
CORTEX Private Macros
CORTEX

Modules

CORTEX SysTick clock source

Defines

#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)

Define Documentation

#define IS_MPU_ACCESS_BUFFERABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_BUFFERABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))

Definition at line 351 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_CACHEABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_CACHEABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))

Definition at line 348 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_SHAREABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_SHAREABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))

Definition at line 345 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_INSTRUCTION_ACCESS ( STATE )
Value:
(((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))

Definition at line 342 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_ENABLE ( STATE )
Value:
(((STATE) == MPU_REGION_ENABLE) || \
                                     ((STATE) == MPU_REGION_DISABLE))

Definition at line 339 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_NUMBER ( NUMBER )
Value:
(((NUMBER) == MPU_REGION_NUMBER0) || \
                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
                                         ((NUMBER) == MPU_REGION_NUMBER7))

Definition at line 365 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_PERMISSION_ATTRIBUTE ( TYPE )
Value:
(((TYPE) == MPU_REGION_NO_ACCESS)   || \
                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))

Definition at line 358 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_SIZE ( SIZE )
Value:
(((SIZE) == MPU_REGION_SIZE_32B)   || \
                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4GB))

Definition at line 374 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_SUB_REGION_DISABLE ( SUBREGION ) ((SUBREGION) < (uint16_t)0x00FFU)

Definition at line 403 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_TEX_LEVEL ( TYPE )
Value:
(((TYPE) == MPU_TEX_LEVEL0)  || \
                                ((TYPE) == MPU_TEX_LEVEL1)  || \
                                ((TYPE) == MPU_TEX_LEVEL2))

Definition at line 354 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_NVIC_DEVICE_IRQ ( IRQ ) ((IRQ) >= 0x00)

Definition at line 327 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_NVIC_DisableIRQ(), and HAL_NVIC_EnableIRQ().

#define IS_NVIC_PREEMPTION_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10U)

Definition at line 323 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_NVIC_PRIORITY_GROUP ( GROUP )
Value:
(((GROUP) == NVIC_PRIORITYGROUP_0) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_4))

Definition at line 317 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_NVIC_GetPriority(), and HAL_NVIC_SetPriorityGrouping().

#define IS_NVIC_SUB_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10U)

Definition at line 325 of file stm32f3xx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CORTEX Private Functions

Functions
CORTEX Private Functions
CORTEX

CORTEX private functions. More...

Functions

void | HAL_MPU_Disable (void)
Disables the MPU also clears the HFNMIENA bit (ARM recommendation)
void | HAL_MPU_Enable (uint32_t MPU_Control)
Enables the MPU.

Detailed Description

CORTEX private functions.

Function Documentation

void HAL_MPU_Disable ( void )

Disables the MPU also clears the HFNMIENA bit (ARM recommendation)

Return values:
None

Definition at line 301 of file stm32f3xx_hal_cortex.c.

void HAL_MPU_Enable ( uint32_t MPU_Control )

Enables the MPU.

Parameters:
MPU_Control Specifies the control mode of the MPU during hard fault, NMI, FAULTMASK and privileged access to the default memory This parameter can be one of the following values:
  • MPU_HFNMI_PRIVDEF_NONE
  • MPU_HARDFAULT_NMI
  • MPU_PRIVILEGED_DEFAULT
  • MPU_HFNMI_PRIVDEF
Return values:
None

Definition at line 321 of file stm32f3xx_hal_cortex.c.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRC Private Functions

Functions
CRC Private Functions
CRC

Functions

static uint32_t | CRC_Handle_8 (CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
Enter 8-bit input data to the CRC calculator.
static uint32_t | CRC_Handle_16 (CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
Enter 16-bit input data to the CRC calculator.

Function Documentation

static uint32_t CRC_Handle_16 | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint16_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  | [static]

Enter 16-bit input data to the CRC calculator.

Specific data handling to optimize processing time.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer
BufferLength | input data buffer length
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 506 of file stm32f3xx_hal_crc.c.

References CRC_HandleTypeDef::Instance.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

static uint32_t CRC_Handle_8 | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint8_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  | [static]

Enter 8-bit input data to the CRC calculator.

Specific data handling to optimize processing time.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer
BufferLength | input data buffer length
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 463 of file stm32f3xx_hal_crc.c.

References CRC_HandleTypeDef::Instance.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the CRC according to the specified parameters
          in the CRC_InitTypeDef and create the associated handle
      (+) DeInitialize the CRC peripheral
      (+) Initialize the CRC MSP (MCU Specific Package)
      (+) DeInitialize the CRC MSP

Function Documentation

HAL_StatusTypeDef HAL_CRC_DeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC peripheral.

Parameters:
hcrc CRC handle
Return values:
HAL status

Definition at line 196 of file stm32f3xx_hal_crc.c.

References __HAL_CRC_DR_RESET, assert_param, HAL_CRC_MspDeInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_RESET, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRC_Init ( CRC_HandleTypeDef * hcrc )

Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and initialize the associated handle.

Parameters:
hcrc CRC handle
Return values:
HAL status

Definition at line 119 of file stm32f3xx_hal_crc.c.

References assert_param, CRC_POLYLENGTH_32B, CRC_InitTypeDef::CRCLength, DEFAULT_CRC32_POLY, DEFAULT_CRC_INITVALUE, DEFAULT_INIT_VALUE_ENABLE, DEFAULT_POLYNOMIAL_ENABLE, CRC_InitTypeDef::DefaultInitValueUse, CRC_InitTypeDef::DefaultPolynomialUse, CRC_InitTypeDef::GeneratingPolynomial, HAL_CRC_MspInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, HAL_CRC_STATE_RESET, HAL_CRCEx_Polynomial_Set(), CRC_HandleTypeDef::Init, CRC_InitTypeDef::InitValue, CRC_HandleTypeDef::InputDataFormat, CRC_InitTypeDef::InputDataInversionMode, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_FORMAT, IS_CRC_INPUTDATA_INVERSION_MODE, IS_CRC_OUTPUTDATA_INVERSION_MODE, IS_DEFAULT_INIT_VALUE, IS_DEFAULT_POLYNOMIAL, CRC_HandleTypeDef::Lock, CRC_InitTypeDef::OutputDataInversionMode, and CRC_HandleTypeDef::State.

void HAL_CRC_MspDeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC MSP.

Parameters:
hcrc CRC handle
Return values:
None

Definition at line 255 of file stm32f3xx_hal_crc.c.

Referenced by HAL_CRC_DeInit().

void HAL_CRC_MspInit ( CRC_HandleTypeDef * hcrc )

Initializes the CRC MSP.

Parameters:
hcrc CRC handle
Return values:
None

Definition at line 240 of file stm32f3xx_hal_crc.c.

Referenced by HAL_CRC_Init().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CRC Exported Functions

management functions. More...

Functions

uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Detailed Description

management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer
          using the combination of the previous CRC value and the new one

       [..]  or

      (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer
          independently of the previous CRC value.

Function Documentation

uint32_t HAL_CRC_Accumulate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength | input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 304 of file stm32f3xx_hal_crc.c.

References CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

uint32_t HAL_CRC_Calculate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength | input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 364 of file stm32f3xx_hal_crc.c.

References __HAL_CRC_DR_RESET, CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

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STM32F373xC HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
CRC Exported Functions

Peripheral State functions. More...

Functions

HAL_CRC_StateTypeDef HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_CRC_StateTypeDef HAL_CRC_GetState ( CRC_HandleTypeDef * hcrc )

Return the CRC handle state.

Parameters:
hcrc CRC handle
Return values:
HAL state

Definition at line 437 of file stm32f3xx_hal_crc.c.

References CRC_HandleTypeDef::State.

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STM32F373xC HAL User Manual: CRC Exported Types

Data Structures | Enumerations
CRC Exported Types
CRC

Data Structures

struct | CRC_InitTypeDef
CRC Init Structure definition. More...
struct | CRC_HandleTypeDef
CRC Handle Structure definition. More...

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00U, HAL_CRC_STATE_READY = 0x01U, HAL_CRC_STATE_BUSY = 0x02U, HAL_CRC_STATE_TIMEOUT = 0x03U,
HAL_CRC_STATE_ERROR = 0x04
}
CRC HAL State Structure definition. More...

Enumeration Type Documentation

enum HAL_CRC_StateTypeDef

CRC HAL State Structure definition.

Enumerator:
HAL_CRC_STATE_RESET

CRC not yet initialized or disabled

HAL_CRC_STATE_READY

CRC initialized and ready for use

HAL_CRC_STATE_BUSY

CRC internal process is ongoing

HAL_CRC_STATE_TIMEOUT

CRC timeout state

HAL_CRC_STATE_ERROR

CRC error state

Definition at line 62 of file stm32f3xx_hal_crc.h.

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STM32F373xC HAL User Manual: CRC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_InitTypeDef Struct Reference
CRC Exported Types

CRC Init Structure definition. More...

#include <stm32f3xx_hal_crc.h>

Data Fields

uint8_t | DefaultPolynomialUse
uint8_t | DefaultInitValueUse
uint32_t | GeneratingPolynomial
uint32_t | CRCLength
uint32_t | InitValue
uint32_t | InputDataInversionMode
uint32_t | OutputDataInversionMode

Detailed Description

CRC Init Structure definition.

Definition at line 75 of file stm32f3xx_hal_crc.h.

Field Documentation

uint32_t CRC_InitTypeDef::CRCLength

This parameter is a value of Polynomial sizes to configure the IP and indicates CRC length. Value can be either one of

  • CRC_POLYLENGTH_32B (32-bit CRC),
  • CRC_POLYLENGTH_16B (16-bit CRC),
  • CRC_POLYLENGTH_8B (8-bit CRC),
  • CRC_POLYLENGTH_7B (7-bit CRC).

Definition at line 93 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint8_t CRC_InitTypeDef::DefaultInitValueUse

This parameter is a value of Indicates whether or not default init value is used and indicates if default init value is used. If set to DEFAULT_INIT_VALUE_ENABLE, resort to default 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set.

Definition at line 83 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint8_t CRC_InitTypeDef::DefaultPolynomialUse

This parameter is a value of Indicates whether or not default polynomial is used and indicates if default polynomial is used. If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default X^32U + X^26U + X^23U + X^22U + X^16U + X^12U + X^11U + X^10U +X^8U + X^7U + X^5U + X^4U + X^2U+ X +1. In that case, there is no need to set GeneratingPolynomial field. If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set.

Definition at line 77 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::GeneratingPolynomial

Set CRC generating polynomial as a 7U, 8U, 16 or 32-bit long value for a polynomial degree respectively equal to 7U, 8U, 16 or 32. This field is written in normal representation, e.g., for a polynomial of degree 7U, X^7U + X^6U + X^5U + X^2U + 1 is written 0x65. No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE.

Definition at line 88 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::InitValue

Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse is set to DEFAULT_INIT_VALUE_ENABLE.

Definition at line 100 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::InputDataInversionMode

This parameter is a value of CRC Extended Input Data Inversion Modes and specifies input data inversion mode. Can be either one of the following values

  • CRC_INPUTDATA_INVERSION_NONE, no input data inversion
  • CRC_INPUTDATA_INVERSION_BYTE, byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
  • CRC_INPUTDATA_INVERSION_HALFWORD, halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
  • CRC_INPUTDATA_INVERSION_WORD, word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458U

Definition at line 103 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::OutputDataInversionMode

This parameter is a value of CRC Extended Output Data Inversion Modes and specifies output data (i.e. CRC) inversion mode. Can be either

  • CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion,
  • CRC_OUTPUTDATA_INVERSION_ENABLE: CRC 0x11223344 is converted into 0x22CC4488U

Definition at line 110 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Init().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_crc.h
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STM32F373xC HAL User Manual: CRC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_HandleTypeDef Struct Reference
CRC Exported Types

CRC Handle Structure definition. More...

#include <stm32f3xx_hal_crc.h>

Data Fields

CRC_TypeDef * | Instance
CRC_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_CRC_StateTypeDef | State
uint32_t | InputDataFormat

Detailed Description

CRC Handle Structure definition.

Definition at line 120 of file stm32f3xx_hal_crc.h.

Field Documentation

CRC_InitTypeDef CRC_HandleTypeDef::Init

CRC configuration parameters

Definition at line 124 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_HandleTypeDef::InputDataFormat

This parameter is a value of Input Buffer Format and specifies input data format. Can be either

  • CRC_INPUTDATA_FORMAT_BYTES, input data is a stream of bytes (8-bit data)
  • CRC_INPUTDATA_FORMAT_HALFWORDS, input data is a stream of half-words (16-bit data)
  • CRC_INPUTDATA_FORMAT_WORDS, input data is a stream of words (32-bit data)

Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error must occur if InputBufferFormat is not one of the three values listed above

Definition at line 130 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), and HAL_CRC_Init().

CRC_TypeDef* CRC_HandleTypeDef::Instance

Register base address

Definition at line 122 of file stm32f3xx_hal_crc.h.

Referenced by CRC_Handle_16(), CRC_Handle_8(), HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), HAL_CRCEx_Output_Data_Reverse(), and HAL_CRCEx_Polynomial_Set().

HAL_LockTypeDef CRC_HandleTypeDef::Lock

CRC Locking object

Definition at line 126 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Init().

__IO HAL_CRC_StateTypeDef CRC_HandleTypeDef::State

CRC communication state

Definition at line 128 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_GetState(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), and HAL_CRCEx_Output_Data_Reverse().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_crc.h
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STM32F373xC HAL User Manual: Default CRC generating polynomial

Defines
Default CRC generating polynomial
CRC Exported Constants

Defines

#define DEFAULT_CRC32_POLY 0x04C11DB7

Define Documentation

#define DEFAULT_CRC32_POLY 0x04C11DB7

X^32U + X^26U + X^23U + X^22U + X^16U + X^12U + X^11U + X^10U +X^8U + X^7U + X^5U + X^4U + X^2U+ X +1U

Definition at line 150 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32F373xC HAL User Manual: Default CRC computation initialization value

Defines
Default CRC computation initialization value
CRC Exported Constants

Defines

#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Define Documentation

#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Initial CRC default value

Definition at line 159 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32F373xC HAL User Manual: Indicates whether or not default polynomial is used

Defines
Indicates whether or not default polynomial is used
CRC Exported Constants

Defines

#define | DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)

Define Documentation

#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)

Disable default generating polynomial 0x04C11DB7U

Definition at line 169 of file stm32f3xx_hal_crc.h.

#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)

Enable default generating polynomial 0x04C11DB7

Definition at line 168 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32F373xC HAL User Manual: Indicates whether or not default init value is used

Defines
Indicates whether or not default init value is used
CRC Exported Constants

Defines

#define | DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)

Define Documentation

#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)

Disable initial CRC default value

Definition at line 178 of file stm32f3xx_hal_crc.h.

#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)

Enable initial CRC default value

Definition at line 177 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32F373xC HAL User Manual: Polynomial sizes to configure the IP

Defines
Polynomial sizes to configure the IP
CRC Exported Constants

Defines

#define | CRC_POLYLENGTH_32B (0x00000000U)
#define | CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
#define | CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
#define | CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)

Define Documentation

#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)

Resort to a 16-bit long generating polynomial

Definition at line 187 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_32B (0x00000000U)

Resort to a 32-bit long generating polynomial

Definition at line 186 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)

Resort to a 7-bit long generating polynomial

Definition at line 189 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)

Resort to a 8-bit long generating polynomial

Definition at line 188 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

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STM32F373xC HAL User Manual: CRC polynomial possible sizes actual definitions

Defines
CRC polynomial possible sizes actual definitions
CRC Exported Constants

Defines

#define | HAL_CRC_LENGTH_32B 32
#define | HAL_CRC_LENGTH_16B 16
#define | HAL_CRC_LENGTH_8B 8
#define | HAL_CRC_LENGTH_7B 7

Define Documentation

#define HAL_CRC_LENGTH_16B 16

16-bit long CRC

Definition at line 198 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define HAL_CRC_LENGTH_32B 32

32-bit long CRC

Definition at line 197 of file stm32f3xx_hal_crc.h.

#define HAL_CRC_LENGTH_7B 7

7-bit long CRC

Definition at line 200 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define HAL_CRC_LENGTH_8B 8

8-bit long CRC

Definition at line 199 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

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STM32F373xC HAL User Manual: Input Buffer Format

Defines
Input Buffer Format
CRC Exported Constants

Defines

#define | CRC_INPUTDATA_FORMAT_UNDEFINED (0x00000000U)
#define | CRC_INPUTDATA_FORMAT_BYTES (0x00000001U)
#define | CRC_INPUTDATA_FORMAT_HALFWORDS (0x00000002U)
#define | CRC_INPUTDATA_FORMAT_WORDS (0x00000003U)

Define Documentation

#define CRC_INPUTDATA_FORMAT_BYTES (0x00000001U)

Input data in byte format

Definition at line 214 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

#define CRC_INPUTDATA_FORMAT_HALFWORDS (0x00000002U)

Input data in half-word format

Definition at line 215 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

#define CRC_INPUTDATA_FORMAT_UNDEFINED (0x00000000U)

Undefined input data format

Definition at line 213 of file stm32f3xx_hal_crc.h.

#define CRC_INPUTDATA_FORMAT_WORDS (0x00000003U)

Input data in word format

Definition at line 216 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

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STM32F373xC HAL User Manual: CRC Exported Macros

Defines
CRC Exported Macros
CRC

Defines

#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Reset CRC Data Register.
#define | __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
Set CRC INIT non-default value.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Store a 8-bit data in the Independent Data(ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Return the 8-bit data stored in the Independent Data(ID) register.

Define Documentation

#define __HAL_CRC_DR_RESET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)

Reset CRC Data Register.

Parameters:
__HANDLE__ CRC handle
Return values:
None

Definition at line 242 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Calculate(), and HAL_CRC_DeInit().

#define __HAL_CRC_GET_IDR ( __HANDLE__ ) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)

Return the 8-bit data stored in the Independent Data(ID) register.

Parameters:
__HANDLE__ CRC handle
Return values:
8-bit value of the ID register

Definition at line 265 of file stm32f3xx_hal_crc.h.

#define __HAL_CRC_INITIALCRCVALUE_CONFIG | ( | __HANDLE__,
 |  | __INIT__
 | ) | ((__HANDLE__)->Instance->INIT = (__INIT__))

Set CRC INIT non-default value.

Parameters:
__HANDLE__ | CRC handle
__INIT__ | 32-bit initial value
Return values:
None

Definition at line 250 of file stm32f3xx_hal_crc.h.

#define __HAL_CRC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)

Reset CRC handle state.

Parameters:
__HANDLE__ CRC handle.
Return values:
None

Definition at line 235 of file stm32f3xx_hal_crc.h.

#define __HAL_CRC_SET_IDR | ( | __HANDLE__,
 |  | __VALUE__
 | ) | (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))

Store a 8-bit data in the Independent Data(ID) register.

Parameters:
__HANDLE__ | CRC handle
__VALUE__ | 8-bit value to be stored in the ID register
Return values:
None

Definition at line 258 of file stm32f3xx_hal_crc.h.

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STM32F373xC HAL User Manual: CRC aliases for Exported Functions

Defines
CRC aliases for Exported Functions
CRC

Defines

#define | HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
#define | HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse

Define Documentation

#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse

Definition at line 346 of file stm32f3xx_hal_crc.h.

#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse

Definition at line 347 of file stm32f3xx_hal_crc.h.

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STM32F373xC HAL User Manual: CRC Private Macros

Defines
CRC Private Macros
CRC

Defines

#define | IS_DEFAULT_POLYNOMIAL(DEFAULT)
#define | IS_DEFAULT_INIT_VALUE(VALUE)
#define | IS_CRC_POL_LENGTH(LENGTH)
#define | IS_CRC_INPUTDATA_FORMAT(FORMAT)

Define Documentation

#define IS_CRC_INPUTDATA_FORMAT ( FORMAT )
Value:
(((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))

Definition at line 288 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Init().

#define IS_CRC_POL_LENGTH ( LENGTH )
Value:
(((LENGTH) == CRC_POLYLENGTH_32B) || \
                                       ((LENGTH) == CRC_POLYLENGTH_16B) || \
                                       ((LENGTH) == CRC_POLYLENGTH_8B)  || \
                                       ((LENGTH) == CRC_POLYLENGTH_7B))

Definition at line 283 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define IS_DEFAULT_INIT_VALUE ( VALUE )
Value:
(((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
                                       ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))

Definition at line 280 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Init().

#define IS_DEFAULT_POLYNOMIAL ( DEFAULT )
Value:
(((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
                                        ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))

Definition at line 276 of file stm32f3xx_hal_crc.h.

Referenced by HAL_CRC_Init().

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRC Extended Initialization and de-initialization functions

Functions
CRC Extended Initialization and de-initialization functions
CRC Extended Exported Functions

CRC Extended Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

CRC Extended Initialization and Configuration functions.

Extended Initialization and Configuration functions.

 ===============================================================================
            ##### Extended configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the generating polynomial
      (+) Configure the input data inversion
      (+) Configure the output data inversion

Function Documentation

HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | InputReverseMode
 | ) |  |

Set the Reverse Input data mode.

Parameters:
hcrc CRC handle
InputReverseMode Input Data inversion mode. This parameter can be one of the following values:
  • CRC_INPUTDATA_NOINVERSION: no change in bit order (default value)
  • CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
  • CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal
  • CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal
Return values:
HAL status

Definition at line 169 of file stm32f3xx_hal_crc_ex.c.

References assert_param, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_INVERSION_MODE, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | OutputReverseMode
 | ) |  |

Set the Reverse Output data mode.

Parameters:
hcrc CRC handle
OutputReverseMode Output Data inversion mode. This parameter can be one of the following values:
  • CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
  • CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
Return values:
HAL status

Definition at line 195 of file stm32f3xx_hal_crc_ex.c.

References assert_param, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, IS_CRC_OUTPUTDATA_INVERSION_MODE, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | Pol,
 |  | uint32_t | PolyLength
 | ) |  |

Initialize the CRC polynomial if different from default one.

Parameters:
hcrc CRC handle
Pol CRC generating polynomial (7, 8, 16 or 32-bit long). This parameter is written in normal representation, e.g.
  • for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
  • for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
PolyLength CRC polynomial length. This parameter can be one of the following values:
  • CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
  • CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
  • CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)
  • CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)
Return values:
HAL status

Definition at line 105 of file stm32f3xx_hal_crc_ex.c.

References assert_param, CRC_POLYLENGTH_16B, CRC_POLYLENGTH_32B, CRC_POLYLENGTH_7B, CRC_POLYLENGTH_8B, HAL_CRC_LENGTH_16B, HAL_CRC_LENGTH_7B, HAL_CRC_LENGTH_8B, CRC_HandleTypeDef::Instance, and IS_CRC_POL_LENGTH.

Referenced by HAL_CRC_Init().

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STM32F373xC HAL User Manual: CRC Extended Input Data Inversion Modes

Defines
CRC Extended Input Data Inversion Modes
CRC Extended Exported Constants

Defines

#define | CRC_INPUTDATA_INVERSION_NONE (0x00000000U)
#define | CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
#define | CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
#define | CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)

Define Documentation

#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)

Byte-wise input data inversion

Definition at line 65 of file stm32f3xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)

HalfWord-wise input data inversion

Definition at line 66 of file stm32f3xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_NONE (0x00000000U)

No input data inversion

Definition at line 64 of file stm32f3xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)

Word-wise input data inversion

Definition at line 67 of file stm32f3xx_hal_crc_ex.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRC Extended Output Data Inversion Modes

Defines
CRC Extended Output Data Inversion Modes
CRC Extended Exported Constants

Defines

#define | CRC_OUTPUTDATA_INVERSION_DISABLE (0x00000000U)
#define | CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)

Define Documentation

#define CRC_OUTPUTDATA_INVERSION_DISABLE (0x00000000U)

No output data inversion

Definition at line 75 of file stm32f3xx_hal_crc_ex.h.

#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)

Bit-wise output data inversion

Definition at line 76 of file stm32f3xx_hal_crc_ex.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRC Extended Exported Macros

Defines
CRC Extended Exported Macros
CRCEx

Defines

#define | __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
Set CRC output reversal.
#define | __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
Unset CRC output reversal.
#define | __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
Set CRC non-default polynomial.

Define Documentation

#define __HAL_CRC_OUTPUTREVERSAL_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))

Unset CRC output reversal.

Parameters:
__HANDLE__ CRC handle
Return values:
None.

Definition at line 103 of file stm32f3xx_hal_crc_ex.h.

#define __HAL_CRC_OUTPUTREVERSAL_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)

Set CRC output reversal.

Parameters:
__HANDLE__ CRC handle
Return values:
None.

Definition at line 96 of file stm32f3xx_hal_crc_ex.h.

#define __HAL_CRC_POLYNOMIAL_CONFIG | ( | __HANDLE__,
 |  | __POLYNOMIAL__
 | ) | ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))

Set CRC non-default polynomial.

Parameters:
__HANDLE__ | CRC handle
__POLYNOMIAL__ | 7, 8, 16 or 32-bit polynomial
Return values:
None.

Definition at line 111 of file stm32f3xx_hal_crc_ex.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRCEx Private Macros

Defines
CRCEx Private Macros
CRCEx

Defines

#define | IS_CRC_INPUTDATA_INVERSION_MODE(MODE)
#define | IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)

Define Documentation

#define IS_CRC_INPUTDATA_INVERSION_MODE ( MODE )
Value:
(((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_WORD))

Definition at line 122 of file stm32f3xx_hal_crc_ex.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Input_Data_Reverse().

#define IS_CRC_OUTPUTDATA_INVERSION_MODE ( MODE )
Value:
(((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
                                                   ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))

Definition at line 128 of file stm32f3xx_hal_crc_ex.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Output_Data_Reverse().

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC Private Macros

Defines
DAC Private Macros
DAC

Defines

#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)
#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)

Define Documentation

#define IS_DAC_ALIGN ( ALIGN )
Value:
(((ALIGN) == DAC_ALIGN_12B_R) || \
                             ((ALIGN) == DAC_ALIGN_12B_L) || \
                             ((ALIGN) == DAC_ALIGN_8B_R))

Definition at line 359 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), HAL_DAC_Start_DMA(), and HAL_DACEx_DualSetValue().

#define IS_DAC_DATA ( DATA ) ((DATA) <= 0xFFF0U)

Definition at line 363 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), and HAL_DACEx_DualSetValue().

#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE ( VALUE )
Value:
(((VALUE) == DAC_LFSRUNMASK_BIT0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))

Definition at line 326 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DACEx_NoiseWaveGenerate(), and HAL_DACEx_TriangleWaveGenerate().

#define IS_DAC_OUTPUT_BUFFER_STATE ( STATE )
Value:
(((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))

Definition at line 351 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC Private Functions

DAC Private Functions
DAC
Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DAC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the DAC.
      (+) De-initialize the DAC.

Function Documentation

HAL_StatusTypeDef HAL_DAC_DeInit ( DAC_HandleTypeDef * hdac )

Deinitialize the DAC peripheral registers to their default reset values.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 317 of file stm32f3xx_hal_dac.c.

References assert_param, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_NONE, HAL_DAC_MspDeInit(), HAL_DAC_STATE_BUSY, HAL_DAC_STATE_RESET, __DAC_HandleTypeDef::Instance, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Init ( DAC_HandleTypeDef * hdac )

Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 279 of file stm32f3xx_hal_dac.c.

References assert_param, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_NONE, HAL_DAC_MspInit(), HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, __DAC_HandleTypeDef::Instance, __DAC_HandleTypeDef::Lock, and __DAC_HandleTypeDef::State.

void HAL_DAC_MspDeInit ( DAC_HandleTypeDef * hdac )

DeInitialize the DAC MSP.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 369 of file stm32f3xx_hal_dac.c.

Referenced by HAL_DAC_DeInit().

void HAL_DAC_MspInit ( DAC_HandleTypeDef * hdac )

Initialize the DAC MSP.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 353 of file stm32f3xx_hal_dac.c.

Referenced by HAL_DAC_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
DAC Exported Functions

IO operation functions. More...

Functions

__weak HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
__weak uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
__weak uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Returns the last data output value of the selected DAC channel.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for Channel1.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request This function uses the interruption of DMA underrun.

Detailed Description

IO operation functions.

  ==============================================================================
             ##### IO operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion.
      (+) Stop conversion.
      (+) Start conversion and enable DMA transfer.
      (+) Stop conversion and disable DMA transfer.
      (+) Get result of conversion.
      (+) Get result of dual mode conversion.

Function Documentation

HAL_StatusTypeDef HAL_DAC_ConfigChannel | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the selected DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC configuration structure.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC1 Channel1 selected
  • DAC_CHANNEL_2: DAC1 Channel2 selected
  • DAC_CHANNEL_1: DAC2 Channel1 selected
Return values:
HAL status

Definition at line 596 of file stm32f3xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, DAC_ChannelConfTypeDef::DAC_OutputBuffer, DAC_ChannelConfTypeDef::DAC_OutputSwitch, DAC_ChannelConfTypeDef::DAC_Trigger, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_OUTPUT_BUFFER_STATE, IS_DAC_TRIGGER, and __DAC_HandleTypeDef::State.

void HAL_DAC_ConvCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non blocking mode for Channel1.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 695 of file stm32f3xx_hal_dac.c.

Referenced by DAC_DMAConvCpltCh1().

void HAL_DAC_ConvHalfCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non blocking mode for Channel1.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 711 of file stm32f3xx_hal_dac.c.

Referenced by DAC_DMAHalfConvCpltCh1().

void HAL_DAC_DMAUnderrunCallbackCh1 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for Channel1.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 744 of file stm32f3xx_hal_dac.c.

Referenced by HAL_DAC_IRQHandler().

void HAL_DAC_ErrorCallbackCh1 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel1.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 727 of file stm32f3xx_hal_dac.c.

Referenced by DAC_DMAErrorCh1().

uint32_t HAL_DAC_GetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Returns the last data output value of the selected DAC channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC1 Channel1 selected
  • DAC_CHANNEL_2: DAC1 Channel2 selected
  • DAC_CHANNEL_1: DAC2 Channel1 selected
Return values:
The selected DAC channel data output value.

Definition at line 530 of file stm32f3xx_hal_dac.c.

void HAL_DAC_IRQHandler ( struct __DAC_HandleTypeDef * hdac )

Handles DAC interrupt request This function uses the interruption of DMA underrun.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 675 of file stm32f3xx_hal_dac_ex.c.

References __HAL_DAC_CLEAR_FLAG, __HAL_DAC_GET_FLAG, __HAL_DAC_GET_IT_SOURCE, DAC_FLAG_DMAUDR1, DAC_FLAG_DMAUDR2, DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_DMAUNDERRUNCH1, HAL_DAC_ERROR_DMAUNDERRUNCH2, HAL_DAC_STATE_ERROR, HAL_DACEx_DMAUnderrunCallbackCh2(), __DAC_HandleTypeDef::Instance, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Start | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Enables DAC and starts conversion of channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC1 Channel1 selected
  • DAC_CHANNEL_2: DAC1 Channel2 selected
  • DAC_CHANNEL_1: DAC2 Channel1 selected
Return values:
HAL status

Definition at line 413 of file stm32f3xx_hal_dac.c.

HAL_StatusTypeDef HAL_DAC_Start_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint32_t | Length,
 |  | uint32_t | Alignment
 | ) |  |

Enables DAC and starts conversion of channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC1 Channel1 selected
  • DAC_CHANNEL_2: DAC1 Channel2 selected
pData | The destination peripheral Buffer address.
Length | The length of data to be transferred from memory to DAC peripheral
Alignment Specifies the data alignment for DAC channel. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Return values:
HAL status

Definition at line 376 of file stm32f3xx_hal_dac_ex.c.

References __HAL_DAC_ENABLE, __HAL_DAC_ENABLE_IT, assert_param, DAC_ALIGN_12B_L, DAC_ALIGN_12B_R, DAC_ALIGN_8B_R, DAC_CHANNEL_1, DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), DAC_DMAHalfConvCpltCh1(), DAC_DMAHalfConvCpltCh2(), DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::DMA_Handle1, __DAC_HandleTypeDef::DMA_Handle2, HAL_DAC_STATE_BUSY, HAL_DMA_Start_IT(), __DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, __DAC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DAC_Stop | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disables DAC and stop conversion of channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC1 Channel1 selected
  • DAC_CHANNEL_2: DAC1 Channel2 selected
  • DAC_CHANNEL_1: DAC2 Channel1 selected
Return values:
HAL status

Definition at line 437 of file stm32f3xx_hal_dac.c.

References __HAL_DAC_DISABLE, assert_param, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Stop_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disables DAC and stop conversion of channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC1 Channel1 selected
  • DAC_CHANNEL_2: DAC1 Channel2 selected
  • DAC_CHANNEL_1: DAC2 Channel1 selected
Return values:
HAL status

Definition at line 463 of file stm32f3xx_hal_dac.c.

References __HAL_DAC_DISABLE, __HAL_DAC_DISABLE_IT, assert_param, DAC_CHANNEL_1, DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::DMA_Handle1, __DAC_HandleTypeDef::DMA_Handle2, HAL_DAC_STATE_ERROR, HAL_DAC_STATE_READY, HAL_DMA_Abort(), __DAC_HandleTypeDef::Instance, and __DAC_HandleTypeDef::State.

uint32_t HAL_DACEx_DualGetValue ( DAC_HandleTypeDef * hdac )

Returns the last data output value of the selected DAC channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
The selected DAC channel data output value.

Definition at line 549 of file stm32f3xx_hal_dac.c.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DAC Exported Functions

Peripheral Control functions. More...

Functions

__weak HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
__weak HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
__weak HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)

Detailed Description

Peripheral Control functions.

  ==============================================================================
             ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels.
      (+) Configure Triangle wave generation.
      (+) Configure Noise wave generation.
      (+) Set the specified data holding register value for DAC channel.
      (+) Set the specified data holding register value for Dual DAC channels.

Function Documentation

__weak HAL_StatusTypeDef HAL_DAC_ConfigChannel | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the selected DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC configuration structure.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC1 Channel1 selected
  • DAC_CHANNEL_2: DAC1 Channel2 selected
  • DAC_CHANNEL_1: DAC2 Channel1 selected
Return values:
HAL status

Definition at line 596 of file stm32f3xx_hal_dac.c.

HAL_StatusTypeDef HAL_DAC_SetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data
 | ) |  |

Definition at line 607 of file stm32f3xx_hal_dac.c.

__weak HAL_StatusTypeDef HAL_DACEx_DualSetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data1,
 |  | uint32_t | Data2
 | ) |  |

Definition at line 622 of file stm32f3xx_hal_dac.c.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
DAC Exported Functions

DAC Peripheral State and Error functions. More...

Functions

HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.

Detailed Description

DAC Peripheral State and Error functions.

  ==============================================================================
            ##### DAC Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DAC state.
      (+) Check the DAC Errors.

Function Documentation

uint32_t HAL_DAC_GetError ( DAC_HandleTypeDef * hdac )

Return the DAC error code.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
DAC Error Code

Definition at line 676 of file stm32f3xx_hal_dac.c.

References __DAC_HandleTypeDef::ErrorCode.

HAL_DAC_StateTypeDef HAL_DAC_GetState ( DAC_HandleTypeDef * hdac )

return the DAC handle state

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL state

Definition at line 664 of file stm32f3xx_hal_dac.c.

References __DAC_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC Exported Types

Data Structures | Typedefs | Enumerations
DAC Exported Types
DAC

Data Structures

struct | DAC_ChannelConfTypeDef
DAC Configuration regular Channel structure definition. More...
struct | __DAC_HandleTypeDef
DAC handle Structure definition. More...

Typedefs

typedef struct __DAC_HandleTypeDef | DAC_HandleTypeDef
DAC handle Structure definition.

Enumerations

enum HAL_DAC_StateTypeDef {
HAL_DAC_STATE_RESET = 0x00U, HAL_DAC_STATE_READY = 0x01U, HAL_DAC_STATE_BUSY = 0x02U, HAL_DAC_STATE_TIMEOUT = 0x03U,
HAL_DAC_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Typedef Documentation

typedef struct __DAC_HandleTypeDef DAC_HandleTypeDef

DAC handle Structure definition.

Enumeration Type Documentation

enum HAL_DAC_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_DAC_STATE_RESET

DAC not yet initialized or disabled

HAL_DAC_STATE_READY

DAC initialized and ready for use

HAL_DAC_STATE_BUSY

DAC internal processing is ongoing

HAL_DAC_STATE_TIMEOUT

DAC timeout state

HAL_DAC_STATE_ERROR

DAC error state

Definition at line 64 of file stm32f3xx_hal_dac.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DAC_ChannelConfTypeDef Struct Reference
DAC Exported Types

DAC Configuration regular Channel structure definition. More...

#include <stm32f3xx_hal_dac.h>

Data Fields

uint32_t | DAC_Trigger
uint32_t | DAC_OutputBuffer
uint32_t | DAC_OutputSwitch

Detailed Description

DAC Configuration regular Channel structure definition.

Definition at line 77 of file stm32f3xx_hal_dac.h.

Field Documentation

uint32_t DAC_ChannelConfTypeDef::DAC_OutputBuffer

Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of DAC output buffer For a given DAC channel, is this paramater applies then DAC_OutputSwitch does not apply

Definition at line 82 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_OutputSwitch

Specifies whether the DAC channel output switch is enabled or disabled. This parameter can be a value of DAC_OutputSwitch For a given DAC channel, is this paramater applies then DAC_OutputBuffer does not apply

Definition at line 87 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_Trigger

Specifies the external trigger for the selected DAC channel. This parameter can be a value of DACEx trigger selection

Definition at line 79 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_dac.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: __DAC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DAC_HandleTypeDef Struct Reference
DAC Exported Types

DAC handle Structure definition. More...

#include <stm32f3xx_hal_dac.h>

Data Fields

DAC_TypeDef * | Instance
__IO HAL_DAC_StateTypeDef | State
HAL_LockTypeDef | Lock
DMA_HandleTypeDef * DMA_Handle1
DMA_HandleTypeDef * DMA_Handle2
__IO uint32_t | ErrorCode

Detailed Description

DAC handle Structure definition.

Definition at line 97 of file stm32f3xx_hal_dac.h.

Field Documentation

DMA_HandleTypeDef* __DAC_HandleTypeDef::DMA_Handle1

Pointer DMA handler for channel 1U

Definition at line 105 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

DMA_HandleTypeDef* __DAC_HandleTypeDef::DMA_Handle2

Pointer DMA handler for channel 2U

Definition at line 107 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

__IO uint32_t __DAC_HandleTypeDef::ErrorCode

DAC Error code

Definition at line 109 of file stm32f3xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_DeInit(), HAL_DAC_GetError(), HAL_DAC_Init(), and HAL_DAC_IRQHandler().

DAC_TypeDef* __DAC_HandleTypeDef::Instance

Register base address

Definition at line 99 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetValue(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualGetValue(), HAL_DACEx_DualSetValue(), HAL_DACEx_NoiseWaveGenerate(), and HAL_DACEx_TriangleWaveGenerate().

HAL_LockTypeDef __DAC_HandleTypeDef::Lock

DAC locking object

Definition at line 103 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_Init().

__IO HAL_DAC_StateTypeDef __DAC_HandleTypeDef::State

DAC communication state

Definition at line 101 of file stm32f3xx_hal_dac.h.

Referenced by DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetState(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_NoiseWaveGenerate(), and HAL_DACEx_TriangleWaveGenerate().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_dac.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC Error Code

Defines
DAC Error Code
DAC Exported Constants

Defines

#define | HAL_DAC_ERROR_NONE 0x00
#define | HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01
#define | HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02
#define | HAL_DAC_ERROR_DMA 0x04

Define Documentation

#define HAL_DAC_ERROR_DMA 0x04

DMA error

Definition at line 127 of file stm32f3xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), and DAC_DMAErrorCh2().

#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01

DAC channel1 DMA underrun error

Definition at line 125 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02

DAC channel2 DMA underrun error

Definition at line 126 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define HAL_DAC_ERROR_NONE 0x00

No error

Definition at line 124 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_DeInit(), and HAL_DAC_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC lfsrunmask triangleamplitude

Defines
DAC lfsrunmask triangleamplitude
DAC Exported Constants

Defines

#define | DAC_LFSRUNMASK_BIT0 (0x00000000U)
#define | DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_1 (0x00000000U)
#define | DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define DAC_LFSRUNMASK_BIT0 (0x00000000U)

Unmask DAC channel LFSR bit0 for noise wave generation

Definition at line 135 of file stm32f3xx_hal_dac.h.

#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)

Unmask DAC channel LFSR bit[10:0] for noise wave generation

Definition at line 145 of file stm32f3xx_hal_dac.h.

#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[11:0] for noise wave generation

Definition at line 146 of file stm32f3xx_hal_dac.h.

#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[1:0] for noise wave generation

Definition at line 136 of file stm32f3xx_hal_dac.h.

#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1)

Unmask DAC channel LFSR bit[2:0] for noise wave generation

Definition at line 137 of file stm32f3xx_hal_dac.h.

#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[3:0] for noise wave generation

Definition at line 138 of file stm32f3xx_hal_dac.h.

#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2)

Unmask DAC channel LFSR bit[4:0] for noise wave generation

Definition at line 139 of file stm32f3xx_hal_dac.h.

#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[5:0] for noise wave generation

Definition at line 140 of file stm32f3xx_hal_dac.h.

#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)

Unmask DAC channel LFSR bit[6:0] for noise wave generation

Definition at line 141 of file stm32f3xx_hal_dac.h.

#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[7:0] for noise wave generation

Definition at line 142 of file stm32f3xx_hal_dac.h.

#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3)

Unmask DAC channel LFSR bit[8:0] for noise wave generation

Definition at line 143 of file stm32f3xx_hal_dac.h.

#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[9:0] for noise wave generation

Definition at line 144 of file stm32f3xx_hal_dac.h.

#define DAC_TRIANGLEAMPLITUDE_1 (0x00000000U)

Select max triangle amplitude of 1U

Definition at line 147 of file stm32f3xx_hal_dac.h.

#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 1023U

Definition at line 156 of file stm32f3xx_hal_dac.h.

#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)

Select max triangle amplitude of 127U

Definition at line 153 of file stm32f3xx_hal_dac.h.

#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 15U

Definition at line 150 of file stm32f3xx_hal_dac.h.

#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)

Select max triangle amplitude of 2047U

Definition at line 157 of file stm32f3xx_hal_dac.h.

#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 255U

Definition at line 154 of file stm32f3xx_hal_dac.h.

#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0)

Select max triangle amplitude of 3U

Definition at line 148 of file stm32f3xx_hal_dac.h.

#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2)

Select max triangle amplitude of 31U

Definition at line 151 of file stm32f3xx_hal_dac.h.

#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 4095U

Definition at line 158 of file stm32f3xx_hal_dac.h.

#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3)

Select max triangle amplitude of 511U

Definition at line 155 of file stm32f3xx_hal_dac.h.

#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 63U

Definition at line 152 of file stm32f3xx_hal_dac.h.

#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1)

Select max triangle amplitude of 7U

Definition at line 149 of file stm32f3xx_hal_dac.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC output buffer

Defines
DAC output buffer
DAC Exported Constants

Defines

#define | DAC_OUTPUTBUFFER_ENABLE (0x00000000U)
#define | DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)

Define Documentation

#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)

Definition at line 168 of file stm32f3xx_hal_dac.h.

#define DAC_OUTPUTBUFFER_ENABLE (0x00000000U)

Definition at line 167 of file stm32f3xx_hal_dac.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC data alignement

Defines
DAC data alignement
DAC Exported Constants

Defines

#define | DAC_ALIGN_12B_R (0x00000000U)
#define | DAC_ALIGN_12B_L (0x00000004U)
#define | DAC_ALIGN_8B_R (0x00000008U)

Define Documentation

#define DAC_ALIGN_12B_L (0x00000004U)

Definition at line 190 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

#define DAC_ALIGN_12B_R (0x00000000U)

Definition at line 189 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

#define DAC_ALIGN_8B_R (0x00000008U)

Definition at line 191 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualSetValue().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC flags definition

Defines
DAC flags definition
DAC Exported Constants

Defines

#define | DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Define Documentation

#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)

Definition at line 200 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Definition at line 201 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC interrupts definition

Defines
DAC interrupts definition
DAC Exported Constants

Defines

#define | DAC_IT_DMAUDR1 ((uint32_t)DAC_CR_DMAUDRIE1)
#define | DAC_IT_DMAUDR2 ((uint32_t)DAC_CR_DMAUDRIE2)

Define Documentation

#define DAC_IT_DMAUDR1 ((uint32_t)DAC_CR_DMAUDRIE1)

Definition at line 209 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler(), HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

#define DAC_IT_DMAUDR2 ((uint32_t)DAC_CR_DMAUDRIE2)

Definition at line 210 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler(), HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC Exported Macros

Defines
DAC Exported Macros
DAC

Defines

#define | __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
Reset DAC handle state.
#define | __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
Enable the DAC channel.
#define | __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
Disable the DAC channel.
#define | DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__))
Set DHR12R1 alignment.
#define | DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__))
Set DHR12R2 alignment.
#define | DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__))
Set DHR12RD alignment.
#define | __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the DAC interrupt.
#define | __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the DAC interrupt.
#define | __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified DAC interrupt source is enabled or not.
#define | __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected DAC's flag status.
#define | __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
Clear the DAC's flag.

Define Documentation

#define __HAL_DAC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR) = (__FLAG__))

Clear the DAC's flag.

Parameters:
__HANDLE__ specifies the DAC handle.
__FLAG__ specifies the DAC flag to clear. This parameter can be any combination of the following values:
  • DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
  • DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
Return values:
None

Definition at line 314 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_DISABLE | ( | __HANDLE__,
 |  | __DAC_Channel__
 | ) | ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))

Disable the DAC channel.

Parameters:
__HANDLE__ | specifies the DAC handle
__DAC_Channel__ | specifies the DAC channel.
Return values:
None

Definition at line 245 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_Stop(), and HAL_DAC_Stop_DMA().

#define __HAL_DAC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))

Disable the DAC interrupt.

Parameters:
__HANDLE__ specifies the DAC handle
__INTERRUPT__ specifies the DAC interrupt. This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
Return values:
None

Definition at line 284 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_Stop_DMA().

#define __HAL_DAC_ENABLE | ( | __HANDLE__,
 |  | __DAC_Channel__
 | ) | ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))

Enable the DAC channel.

Parameters:
__HANDLE__ | specifies the DAC handle.
__DAC_Channel__ | specifies the DAC channel
Return values:
None

Definition at line 237 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_Start(), and HAL_DAC_Start_DMA().

#define __HAL_DAC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))

Enable the DAC interrupt.

Parameters:
__HANDLE__ specifies the DAC handle
__INTERRUPT__ specifies the DAC interrupt. This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
Return values:
None

Definition at line 274 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

#define __HAL_DAC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Get the selected DAC's flag status.

Parameters:
__HANDLE__ specifies the DAC handle.
__FLAG__ specifies the DAC flag to get. This parameter can be any combination of the following values:
  • DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
  • DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
Return values:
None

Definition at line 304 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified DAC interrupt source is enabled or not.

Parameters:
__HANDLE__ DAC handle
__INTERRUPT__ DAC interrupt source to check This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
Return values:
State of interruption (SET or RESET)

Definition at line 294 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)

Reset DAC handle state.

Parameters:
__HANDLE__ specifies the DAC handle.
Return values:
None

Definition at line 230 of file stm32f3xx_hal_dac.h.

#define DAC_DHR12R1_ALIGNMENT ( __ALIGNMENT__ ) ((0x00000008U) + (__ALIGNMENT__))

Set DHR12R1 alignment.

Parameters:
__ALIGNMENT__ specifies the DAC alignment
Return values:
None

Definition at line 252 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_SetValue().

#define DAC_DHR12R2_ALIGNMENT ( __ALIGNMENT__ ) ((0x00000014U) + (__ALIGNMENT__))

Set DHR12R2 alignment.

Parameters:
__ALIGNMENT__ specifies the DAC alignment
Return values:
None

Definition at line 258 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DAC_SetValue().

#define DAC_DHR12RD_ALIGNMENT ( __ALIGNMENT__ ) ((0x00000020U) + (__ALIGNMENT__))

Set DHR12RD alignment.

Parameters:
__ALIGNMENT__ specifies the DAC alignment
Return values:
None

Definition at line 264 of file stm32f3xx_hal_dac.h.

Referenced by HAL_DACEx_DualSetValue().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DACEx Private Functions

Functions
DACEx Private Functions
DACEx | STM32F3xx_HAL_Driver

Functions

static void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
static void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.

Function Documentation

static void DAC_DMAConvCpltCh1 ( DMA_HandleTypeDef * hdma ) [static]

DMA conversion complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 1045 of file stm32f3xx_hal_dac_ex.c.

References HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_STATE_READY, and __DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

static void DAC_DMAConvCpltCh2 ( DMA_HandleTypeDef * hdma ) [static]

DMA conversion complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 1093 of file stm32f3xx_hal_dac_ex.c.

References HAL_DAC_STATE_READY, HAL_DACEx_ConvCpltCallbackCh2(), and __DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

static void DAC_DMAErrorCh1 ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 1071 of file stm32f3xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_ErrorCallbackCh1(), HAL_DAC_STATE_READY, and __DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

static void DAC_DMAErrorCh2 ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 1119 of file stm32f3xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_STATE_READY, HAL_DACEx_ErrorCallbackCh2(), and __DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

static void DAC_DMAHalfConvCpltCh1 ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 1059 of file stm32f3xx_hal_dac_ex.c.

References HAL_DAC_ConvHalfCpltCallbackCh1().

Referenced by HAL_DAC_Start_DMA().

static void DAC_DMAHalfConvCpltCh2 ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 1107 of file stm32f3xx_hal_dac_ex.c.

References HAL_DACEx_ConvHalfCpltCallbackCh2().

Referenced by HAL_DAC_Start_DMA().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DACEx Peripheral Control functions

Functions
DACEx Peripheral Control functions
DACEx Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.

Detailed Description

Peripheral Control functions.

  ==============================================================================
             ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Set the specified data holding register value for DAC channel.
      (+) Set the specified data holding register value for dual DAC channel
          (when DAC channel 2 is present in DAC 1U)

Function Documentation

HAL_StatusTypeDef HAL_DAC_SetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data
 | ) |  |

Set the specified data holding register value for DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel | The selected DAC channel.
Alignment Specifies the data alignment for DAC channel. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Data | Data to be loaded in the selected data holding register.
Return values:
HAL status

Definition at line 128 of file stm32f3xx_hal_dac_ex.c.

References assert_param, DAC_CHANNEL_1, DAC_DHR12R1_ALIGNMENT, DAC_DHR12R2_ALIGNMENT, __DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, IS_DAC_CHANNEL, and IS_DAC_DATA.

HAL_StatusTypeDef HAL_DACEx_DualSetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data1,
 |  | uint32_t | Data2
 | ) |  |

Set the specified data holding register value for dual DAC channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Alignment Specifies the data alignment for dual channel DAC. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Data2,: Data for DAC Channel2 to be loaded in the selected data holding register.
Data1,: Data for DAC Channel1 to be loaded in the selected data holding register.
Note:
In dual mode, a unique register access is required to write in both DAC channels at the same time.
Return values:
HAL status

Definition at line 186 of file stm32f3xx_hal_dac_ex.c.

References assert_param, DAC_ALIGN_8B_R, DAC_DHR12RD_ALIGNMENT, __DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, and IS_DAC_DATA.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DACEx Input and Output operation functions

Functions
DACEx Input and Output operation functions
DACEx Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
void | HAL_DAC_IRQHandler (struct __DAC_HandleTypeDef *hdac)
Handles DAC interrupt request This function uses the interruption of DMA underrun.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel2.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.

Detailed Description

IO operation functions.

  ==============================================================================
             ##### IO operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion.
      (+) Start conversion and enable DMA transfer.
      (+) Get result of conversion.
      (+) Handle DAC IRQ's.
      (+) Generate triangular-wave
      (+) Generate noise-wave
      (+) Callback functions for DAC1 Channel2 (when supported)

Function Documentation

HAL_StatusTypeDef HAL_DAC_ConfigChannel | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the selected DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC configuration structure.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC1 Channel1 selected
  • DAC_CHANNEL_2: DAC1 Channel2 selected
  • DAC_CHANNEL_1: DAC2 Channel1 selected
Return values:
HAL status

Definition at line 779 of file stm32f3xx_hal_dac_ex.c.

References assert_param, DAC_CHANNEL_1, DAC_ChannelConfTypeDef::DAC_OutputBuffer, DAC_ChannelConfTypeDef::DAC_OutputSwitch, DAC_ChannelConfTypeDef::DAC_Trigger, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_OUTPUT_BUFFER_STATE, IS_DAC_TRIGGER, and __DAC_HandleTypeDef::State.

uint32_t HAL_DAC_GetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Returns the last data output value of the selected DAC channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC1 Channel1 selected
  • DAC_CHANNEL_2: DAC1 Channel2 selected
Return values:
The selected DAC channel data output value.

Definition at line 590 of file stm32f3xx_hal_dac_ex.c.

References assert_param, DAC_CHANNEL_1, and __DAC_HandleTypeDef::Instance.

void HAL_DAC_IRQHandler ( struct __DAC_HandleTypeDef * hdac )

Handles DAC interrupt request This function uses the interruption of DMA underrun.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 675 of file stm32f3xx_hal_dac_ex.c.

References __HAL_DAC_CLEAR_FLAG, __HAL_DAC_GET_FLAG, __HAL_DAC_GET_IT_SOURCE, DAC_FLAG_DMAUDR1, DAC_FLAG_DMAUDR2, DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_DMAUNDERRUNCH1, HAL_DAC_ERROR_DMAUNDERRUNCH2, HAL_DAC_STATE_ERROR, HAL_DACEx_DMAUnderrunCallbackCh2(), __DAC_HandleTypeDef::Instance, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Start | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Enables DAC and starts conversion of channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC1 Channel1 or DAC2 Channel1 selected
  • DAC_CHANNEL_2: DAC1 Channel2 selected
Return values:
HAL status

Definition at line 258 of file stm32f3xx_hal_dac_ex.c.

References __HAL_DAC_ENABLE, assert_param, DAC_CHANNEL_1, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Start_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint32_t | Length,
 |  | uint32_t | Alignment
 | ) |  |

Enables DAC and starts conversion of channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC1 Channel1 selected
  • DAC_CHANNEL_2: DAC1 Channel2 selected
pData | The destination peripheral Buffer address.
Length | The length of data to be transferred from memory to DAC peripheral
Alignment Specifies the data alignment for DAC channel. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Return values:
HAL status

Definition at line 376 of file stm32f3xx_hal_dac_ex.c.

References __HAL_DAC_ENABLE, __HAL_DAC_ENABLE_IT, assert_param, DAC_ALIGN_12B_L, DAC_ALIGN_12B_R, DAC_ALIGN_8B_R, DAC_CHANNEL_1, DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), DAC_DMAHalfConvCpltCh1(), DAC_DMAHalfConvCpltCh2(), DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::DMA_Handle1, __DAC_HandleTypeDef::DMA_Handle2, HAL_DAC_STATE_BUSY, HAL_DMA_Start_IT(), __DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, __DAC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

void HAL_DACEx_ConvCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non blocking mode for Channel2.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 963 of file stm32f3xx_hal_dac_ex.c.

Referenced by DAC_DMAConvCpltCh2().

void HAL_DACEx_ConvHalfCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non blocking mode for Channel2.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 979 of file stm32f3xx_hal_dac_ex.c.

Referenced by DAC_DMAHalfConvCpltCh2().

void HAL_DACEx_DMAUnderrunCallbackCh2 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for channel2.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 1011 of file stm32f3xx_hal_dac_ex.c.

Referenced by HAL_DAC_IRQHandler().

uint32_t HAL_DACEx_DualGetValue ( DAC_HandleTypeDef * hdac )

Return the last data output value of the selected DAC channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
The selected DAC channel data output value.

Definition at line 641 of file stm32f3xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_DACEx_DualSetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data1,
 |  | uint32_t | Data2
 | ) |  |

Set the specified data holding register value for dual DAC channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Alignment Specifies the data alignment for dual channel DAC. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Data2,: Data for DAC Channel2 to be loaded in the selected data holding register.
Data1,: Data for DAC Channel1 to be loaded in the selected data holding register.
Note:
In dual mode, a unique register access is required to write in both DAC channels at the same time.
Return values:
HAL status

Definition at line 622 of file stm32f3xx_hal_dac.c.

References assert_param, DAC_ALIGN_8B_R, DAC_DHR12RD_ALIGNMENT, __DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, and IS_DAC_DATA.

void HAL_DACEx_ErrorCallbackCh2 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel2.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 995 of file stm32f3xx_hal_dac_ex.c.

Referenced by DAC_DMAErrorCh2().

HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Amplitude
 | ) |  |

Enables or disables the selected DAC channel wave generation.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC1 Channel1 selected
  • DAC_CHANNEL_2: DAC1 Channel2 selected
Amplitude Unmask DAC channel LFSR for noise wave generation. This parameter can be one of the following values:
  • DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
  • DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
Return values:
HAL status

Definition at line 927 of file stm32f3xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Amplitude
 | ) |  |

Enables or disables the selected DAC channel wave generation.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC1 Channel1 selected
  • DAC_CHANNEL_2: DAC1 Channel2 selected
Amplitude Select max triangle amplitude. This parameter can be one of the following values:
  • DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
  • DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
  • DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
  • DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
  • DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
  • DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
  • DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
  • DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
  • DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
  • DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
  • DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
  • DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
Note:
Wave generation is not available in DAC2.
Return values:
HAL status

Definition at line 878 of file stm32f3xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, and __DAC_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DACEx trigger selection

Defines
DACEx trigger selection
DACEx Exported Constants

Defines

#define | DAC_TRIGGER_NONE (0x00000000U)
#define | DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T18_TRGO DAC_TRIGGER_T5_TRGO
#define | DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1)
#define | DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1))
#define | IS_DAC_TRIGGER(TRIGGER)

Define Documentation

#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))

EXTI Line9 event selected as external conversion trigger for DAC channel

Definition at line 178 of file stm32f3xx_hal_dac_ex.h.

#define DAC_TRIGGER_NONE (0x00000000U)

Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger

Definition at line 167 of file stm32f3xx_hal_dac_ex.h.

#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1))

Conversion started by software trigger for DAC channel

Definition at line 179 of file stm32f3xx_hal_dac_ex.h.

#define DAC_TRIGGER_T18_TRGO DAC_TRIGGER_T5_TRGO

TIM18 TRGO selected as external conversion trigger for DAC channel (DAC2)

Definition at line 173 of file stm32f3xx_hal_dac_ex.h.

#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1))

TIM2 TRGO selected as external conversion trigger for DAC channel

Definition at line 170 of file stm32f3xx_hal_dac_ex.h.

#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1))

TIM3 TRGO selected as external conversion trigger for DAC channel

Definition at line 176 of file stm32f3xx_hal_dac_ex.h.

#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))

TIM4 TRGO selected as external conversion trigger for DAC channel

Definition at line 171 of file stm32f3xx_hal_dac_ex.h.

#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))

TIM5 TRGO selected as external conversion trigger for DAC channel (DAC1)

Definition at line 172 of file stm32f3xx_hal_dac_ex.h.

#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1)

TIM6 TRGO selected as external conversion trigger for DAC channel

Definition at line 174 of file stm32f3xx_hal_dac_ex.h.

#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1))

TIM7 TRGO selected as external conversion trigger for DAC channel

Definition at line 175 of file stm32f3xx_hal_dac_ex.h.

#define IS_DAC_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == DAC_TRIGGER_NONE) || \
                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))

Definition at line 182 of file stm32f3xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DACEx Channel selection

Defines
DACEx Channel selection
DACEx Exported Constants

Defines

#define | DAC_CHANNEL_1 (0x00000000U)
#define | DAC_CHANNEL_2 (0x00000010U)

Define Documentation

#define DAC_CHANNEL_1 (0x00000000U)

DAC Channel 1U

Definition at line 256 of file stm32f3xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_GetValue(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

#define DAC_CHANNEL_2 (0x00000010U)

DAC Channel 2U

Definition at line 257 of file stm32f3xx_hal_dac_ex.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DACEx Private Macros

Defines
DACEx Private Macros
DACEx

Defines

#define IS_DAC_CHANNEL(CHANNEL)

Define Documentation

#define IS_DAC_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == DAC_CHANNEL_1) || \
                                 ((CHANNEL) == DAC_CHANNEL_2))

Definition at line 297 of file stm32f3xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_SetValue(), HAL_DACEx_NoiseWaveGenerate(), and HAL_DACEx_TriangleWaveGenerate().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Private Functions

Functions
DMA Private Functions
DMA

Functions

static void | DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Set the DMA Transfer parameters.
static void | DMA_CalcBaseAndBitshift (DMA_HandleTypeDef *hdma)
Set the DMA base address and channel index depending on DMA instance.

Function Documentation

static void DMA_CalcBaseAndBitshift ( DMA_HandleTypeDef * hdma ) [static]

Set the DMA base address and channel index depending on DMA instance.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
None

Definition at line 863 of file stm32f3xx_hal_dma.c.

References __DMA_HandleTypeDef::ChannelIndex, __DMA_HandleTypeDef::DmaBaseAddress, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMA_DeInit(), and HAL_DMA_Init().

static void DMA_SetConfig | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  | [static]

Set the DMA Transfer parameters.

Parameters:
hdma | pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress | The source memory Buffer address
DstAddress | The destination memory Buffer address
DataLength | The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 829 of file stm32f3xx_hal_dma.c.

References __DMA_HandleTypeDef::ChannelIndex, DMA_InitTypeDef::Direction, DMA_FLAG_GL1, DMA_MEMORY_TO_PERIPH, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::Init, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
             ##### Initialization and de-initialization functions  #####
 ===============================================================================
    [..]
    This section provides functions allowing to initialize the DMA Channel source
    and destination addresses, incrementation and data sizes, transfer direction,
    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
    [..]
    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
    reference manual.

Function Documentation

HAL_StatusTypeDef HAL_DMA_DeInit ( DMA_HandleTypeDef * hdma )

DeInitialize the DMA peripheral.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 221 of file stm32f3xx_hal_dma.c.

References assert_param, __DMA_HandleTypeDef::ChannelIndex, DMA_CalcBaseAndBitshift(), DMA_FLAG_GL1, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_RESET, __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_Init ( DMA_HandleTypeDef * hdma )

Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 153 of file stm32f3xx_hal_dma.c.

References assert_param, DMA_InitTypeDef::Direction, DMA_CalcBaseAndBitshift(), __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, IS_DMA_DIRECTION, IS_DMA_MEMORY_DATA_SIZE, IS_DMA_MEMORY_INC_STATE, IS_DMA_MODE, IS_DMA_PERIPHERAL_DATA_SIZE, IS_DMA_PERIPHERAL_INC_STATE, IS_DMA_PRIORITY, __DMA_HandleTypeDef::Lock, DMA_InitTypeDef::MemDataAlignment, DMA_InitTypeDef::MemInc, DMA_InitTypeDef::Mode, DMA_InitTypeDef::PeriphDataAlignment, DMA_InitTypeDef::PeriphInc, DMA_InitTypeDef::Priority, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
DMA Exported Functions

I/O operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handle DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.

Detailed Description

I/O operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the source, destination address and data length and Start DMA transfer
      (+) Configure the source, destination address and data length and
          Start DMA transfer with interrupt
      (+) Abort DMA transfer
      (+) Poll for transfer complete
      (+) Handle DMA interrupt request

Function Documentation

HAL_StatusTypeDef HAL_DMA_Abort ( DMA_HandleTypeDef * hdma )

Abort the DMA Transfer.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 400 of file stm32f3xx_hal_dma.c.

References __DMA_HandleTypeDef::ChannelIndex, DMA_FLAG_GL1, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DmaBaseAddress, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

Referenced by HAL_ADC_Stop_DMA(), HAL_DAC_Stop_DMA(), HAL_I2S_DMAStop(), HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_SDADC_InjectedMultiModeStop_DMA(), HAL_SDADC_InjectedStop_DMA(), HAL_SDADC_MultiModeStop_DMA(), HAL_SDADC_Stop_DMA(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_SPI_Abort(), HAL_SPI_DMAStop(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_USART_Abort(), and HAL_USART_DMAStop().

HAL_StatusTypeDef HAL_DMA_Abort_IT ( DMA_HandleTypeDef * hdma )

Abort the DMA Transfer in Interrupt mode.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 426 of file stm32f3xx_hal_dma.c.

References __DMA_HandleTypeDef::ChannelIndex, DMA_FLAG_GL1, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_IRQHandler(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), and I2C_ITError().

void HAL_DMA_IRQHandler ( DMA_HandleTypeDef * hdma )

Handle DMA interrupt request.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
None

Definition at line 573 of file stm32f3xx_hal_dma.c.

References __DMA_HandleTypeDef::ChannelIndex, DMA_FLAG_GL1, DMA_FLAG_HT1, DMA_FLAG_TC1, DMA_FLAG_TE1, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_TE, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_PollForTransfer | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | CompleteLevel,
 |  | uint32_t | Timeout
 | ) |  |

Polling for transfer complete.

Parameters:
hdma | pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
CompleteLevel | Specifies the DMA level complete.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 472 of file stm32f3xx_hal_dma.c.

References __DMA_HandleTypeDef::ChannelIndex, DMA_FLAG_GL1, DMA_FLAG_HT1, DMA_FLAG_TC1, DMA_FLAG_TE1, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_ERROR_NOT_SUPPORTED, HAL_DMA_ERROR_TE, HAL_DMA_ERROR_TIMEOUT, HAL_DMA_FULL_TRANSFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, HAL_GetTick(), __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_RegisterCallback | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_CallbackIDTypeDef | CallbackID,
 |  | void(*)(DMA_HandleTypeDef *_hdma) | pCallback
 | ) |  |

Register callbacks.

Parameters:
hdma | pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
CallbackID | User Callback identifer a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
pCallback | pointer to private callback function which has pointer to a DMA_HandleTypeDef structure as parameter.
Return values:
HAL status

Definition at line 665 of file stm32f3xx_hal_dma.c.

References HAL_DMA_STATE_READY, HAL_DMA_XFER_ABORT_CB_ID, HAL_DMA_XFER_CPLT_CB_ID, HAL_DMA_XFER_ERROR_CB_ID, HAL_DMA_XFER_HALFCPLT_CB_ID, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_Start | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Start the DMA Transfer.

Parameters:
hdma | : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress | The source memory Buffer address
DstAddress | The destination memory Buffer address
DataLength | The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 297 of file stm32f3xx_hal_dma.c.

References assert_param, DMA_SetConfig(), __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, IS_DMA_BUFFER_SIZE, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_Start_IT | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Start the DMA Transfer with interrupt enabled.

Parameters:
hdma | pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress | The source memory Buffer address
DstAddress | The destination memory Buffer address
DataLength | The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 344 of file stm32f3xx_hal_dma.c.

References assert_param, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, DMA_SetConfig(), __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, IS_DMA_BUFFER_SIZE, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_ADC_Start_DMA(), HAL_DAC_Start_DMA(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_MultiModeStart_DMA(), HAL_SDADC_Start_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), I2C_DMAMasterReceiveCplt(), and I2C_DMAMasterTransmitCplt().

HAL_StatusTypeDef HAL_DMA_UnRegisterCallback | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_CallbackIDTypeDef | CallbackID
 | ) |  |

UnRegister callbacks.

Parameters:
hdma | pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
CallbackID | User Callback identifer a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
Return values:
HAL status

Definition at line 716 of file stm32f3xx_hal_dma.c.

References HAL_DMA_STATE_READY, HAL_DMA_XFER_ABORT_CB_ID, HAL_DMA_XFER_ALL_CB_ID, HAL_DMA_XFER_CPLT_CB_ID, HAL_DMA_XFER_ERROR_CB_ID, HAL_DMA_XFER_HALFCPLT_CB_ID, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
DMA Exported Functions

Peripheral State functions. More...

Functions

HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Returns the DMA state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                    ##### State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DMA state
      (+) Get error code

Function Documentation

uint32_t HAL_DMA_GetError ( DMA_HandleTypeDef * hdma )

Return the DMA error code.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
DMA Error Code

Definition at line 803 of file stm32f3xx_hal_dma.c.

References __DMA_HandleTypeDef::ErrorCode.

HAL_DMA_StateTypeDef HAL_DMA_GetState ( DMA_HandleTypeDef * hdma )

Returns the DMA state.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL state

Definition at line 792 of file stm32f3xx_hal_dma.c.

References __DMA_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Exported Types

Data Structures | Typedefs | Enumerations
DMA Exported Types
DMA

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum | HAL_DMA_StateTypeDef { HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_TIMEOUT = 0x03 }
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01 }
HAL DMA Error Code structure definition. More...
enum HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_ERROR_CB_ID = 0x02U, HAL_DMA_XFER_ABORT_CB_ID = 0x03U,
HAL_DMA_XFER_ALL_CB_ID = 0x04
}
HAL DMA Callback ID structure definition. More...

Typedef Documentation

typedef struct __DMA_HandleTypeDef DMA_HandleTypeDef

DMA handle Structure definition.

Enumeration Type Documentation

enum HAL_DMA_CallbackIDTypeDef

HAL DMA Callback ID structure definition.

Enumerator:
HAL_DMA_XFER_CPLT_CB_ID

Full transfer

HAL_DMA_XFER_HALFCPLT_CB_ID

Half transfer

HAL_DMA_XFER_ERROR_CB_ID

Error

HAL_DMA_XFER_ABORT_CB_ID

Abort

HAL_DMA_XFER_ALL_CB_ID

All

Definition at line 114 of file stm32f3xx_hal_dma.h.

enum HAL_DMA_LevelCompleteTypeDef

HAL DMA Error Code structure definition.

Enumerator:
HAL_DMA_FULL_TRANSFER

Full transfer

HAL_DMA_HALF_TRANSFER

Half Transfer

Definition at line 105 of file stm32f3xx_hal_dma.h.

enum HAL_DMA_StateTypeDef

HAL DMA State structures definition.

Enumerator:
HAL_DMA_STATE_RESET

DMA not yet initialized or disabled

HAL_DMA_STATE_READY

DMA initialized and ready for use

HAL_DMA_STATE_BUSY

DMA process is ongoing

HAL_DMA_STATE_TIMEOUT

DMA timeout state

Definition at line 94 of file stm32f3xx_hal_dma.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA_InitTypeDef Struct Reference
DMA Exported Types

DMA Configuration Structure definition. More...

#include <stm32f3xx_hal_dma.h>

Data Fields

uint32_t | Direction
uint32_t | PeriphInc
uint32_t | MemInc
uint32_t | PeriphDataAlignment
uint32_t | MemDataAlignment
uint32_t | Mode
uint32_t | Priority

Detailed Description

DMA Configuration Structure definition.

Definition at line 64 of file stm32f3xx_hal_dma.h.

Field Documentation

uint32_t DMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of DMA Data transfer direction

Definition at line 66 of file stm32f3xx_hal_dma.h.

Referenced by DMA_SetConfig(), and HAL_DMA_Init().

uint32_t DMA_InitTypeDef::MemDataAlignment

Specifies the Memory data width. This parameter can be a value of DMA Memory data size

Definition at line 79 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Init(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

uint32_t DMA_InitTypeDef::MemInc

Specifies whether the memory address register should be incremented or not. This parameter can be a value of DMA Memory incremented mode

Definition at line 73 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Mode

Specifies the operation mode of the DMAy Channelx. This parameter can be a value of DMA mode

Note:
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel

Definition at line 82 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Init(), HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_MultiModeStart_DMA(), and HAL_SDADC_Start_DMA().

uint32_t DMA_InitTypeDef::PeriphDataAlignment

Specifies the Peripheral data width. This parameter can be a value of DMA Peripheral data size

Definition at line 76 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::PeriphInc

Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of DMA Peripheral incremented mode

Definition at line 70 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Priority

Specifies the software priority for the DMAy Channelx. This parameter can be a value of DMA Priority level

Definition at line 87 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Init().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_dma.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: __DMA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DMA_HandleTypeDef Struct Reference
DMA Exported Types

DMA handle Structure definition. More...

#include <stm32f3xx_hal_dma.h>

Data Fields

DMA_Channel_TypeDef * | Instance
DMA_InitTypeDef Init
HAL_LockTypeDef | Lock
HAL_DMA_StateTypeDef State
void * | Parent
void(* | XferCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferHalfCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferErrorCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferAbortCallback )(struct __DMA_HandleTypeDef *hdma)
__IO uint32_t | ErrorCode
DMA_TypeDef * | DmaBaseAddress
uint32_t | ChannelIndex

Detailed Description

DMA handle Structure definition.

Definition at line 126 of file stm32f3xx_hal_dma.h.

Field Documentation

uint32_t __DMA_HandleTypeDef::ChannelIndex

DMA Channel Index

Definition at line 150 of file stm32f3xx_hal_dma.h.

Referenced by DMA_CalcBaseAndBitshift(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

DMA_TypeDef* __DMA_HandleTypeDef::DmaBaseAddress

DMA Channel Base Address

Definition at line 148 of file stm32f3xx_hal_dma.h.

Referenced by DMA_CalcBaseAndBitshift(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

__IO uint32_t __DMA_HandleTypeDef::ErrorCode

DMA Error code

Definition at line 146 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_GetError(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_Start(), and HAL_DMA_Start_IT().

DMA_InitTypeDef __DMA_HandleTypeDef::Init

DMA communication parameters

Definition at line 130 of file stm32f3xx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DMA_Init(), HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_MultiModeStart_DMA(), HAL_SDADC_Start_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

DMA_Channel_TypeDef* __DMA_HandleTypeDef::Instance

Register base address

Definition at line 128 of file stm32f3xx_hal_dma.h.

Referenced by DMA_CalcBaseAndBitshift(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_Start(), HAL_DMA_Start_IT(), I2S_DMARxCplt(), I2S_DMATxCplt(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), USART_DMAReceiveCplt(), and USART_DMATransmitCplt().

HAL_LockTypeDef __DMA_HandleTypeDef::Lock

DMA locking object

Definition at line 132 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Init().

void* __DMA_HandleTypeDef::Parent

Parent object state

Definition at line 136 of file stm32f3xx_hal_dma.h.

Referenced by IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMAReceiveHalfCplt(), IRDA_DMARxAbortCallback(), IRDA_DMATransmitCplt(), IRDA_DMATransmitHalfCplt(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATransmitCplt(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxHalfCplt(), UART_DMATransmitCplt(), UART_DMATxAbortCallback(), UART_DMATxHalfCplt(), UART_DMATxOnlyAbortCallback(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMARxHalfCplt(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), and USART_DMATxHalfCplt().

HAL_DMA_StateTypeDef __DMA_HandleTypeDef::State

DMA transfer state

Definition at line 134 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_GetState(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_RegisterCallback(), HAL_DMA_Start(), HAL_DMA_Start_IT(), and HAL_DMA_UnRegisterCallback().

void(* __DMA_HandleTypeDef::XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer abort callback

Definition at line 144 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Abort_IT(), HAL_DMA_Init(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), I2C_DMAAbort(), I2C_ITError(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

void(* __DMA_HandleTypeDef::XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer complete callback

Definition at line 138 of file stm32f3xx_hal_dma.h.

Referenced by HAL_ADC_Start_DMA(), HAL_DAC_Start_DMA(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_MultiModeStart_DMA(), HAL_SDADC_Start_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

void(* __DMA_HandleTypeDef::XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer error callback

Definition at line 142 of file stm32f3xx_hal_dma.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Start_DMA(), HAL_DAC_Start_DMA(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_MultiModeStart_DMA(), HAL_SDADC_Start_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

void(* __DMA_HandleTypeDef::XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA Half transfer complete callback

Definition at line 140 of file stm32f3xx_hal_dma.h.

Referenced by HAL_ADC_Start_DMA(), HAL_DAC_Start_DMA(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_Start_IT(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_MultiModeStart_DMA(), HAL_SDADC_Start_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_dma.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Error Code

Defines
DMA Error Code
DMA Exported Constants

Defines

#define | HAL_DMA_ERROR_NONE (0x00000000U)
#define | HAL_DMA_ERROR_TE (0x00000001U)
#define | HAL_DMA_ERROR_NO_XFER (0x00000004U)
#define | HAL_DMA_ERROR_TIMEOUT (0x00000020U)
#define | HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U)

Define Documentation

#define HAL_DMA_ERROR_NO_XFER (0x00000004U)

no ongoin transfer

Definition at line 167 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Abort_IT(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_NONE (0x00000000U)

No error

Definition at line 165 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U)

Not supported mode

Definition at line 169 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_TE (0x00000001U)

Transfer error

Definition at line 166 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_TIMEOUT (0x00000020U)

Timeout error

Definition at line 168 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Data transfer direction

Defines
DMA Data transfer direction
DMA Exported Constants

Defines

#define | DMA_PERIPH_TO_MEMORY (0x00000000U)
#define | DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR)
#define | DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM)

Define Documentation

#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM)

Memory to memory direction

Definition at line 179 of file stm32f3xx_hal_dma.h.

#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR)

Memory to peripheral direction

Definition at line 178 of file stm32f3xx_hal_dma.h.

Referenced by DMA_SetConfig().

#define DMA_PERIPH_TO_MEMORY (0x00000000U)

Peripheral to memory direction

Definition at line 177 of file stm32f3xx_hal_dma.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Peripheral incremented mode

Defines
DMA Peripheral incremented mode
DMA Exported Constants

Defines

#define | DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC)
#define | DMA_PINC_DISABLE (0x00000000U)

Define Documentation

#define DMA_PINC_DISABLE (0x00000000U)

Peripheral increment mode Disable

Definition at line 189 of file stm32f3xx_hal_dma.h.

#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC)

Peripheral increment mode Enable

Definition at line 188 of file stm32f3xx_hal_dma.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Memory incremented mode

Defines
DMA Memory incremented mode
DMA Exported Constants

Defines

#define | DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC)
#define | DMA_MINC_DISABLE (0x00000000U)

Define Documentation

#define DMA_MINC_DISABLE (0x00000000U)

Memory increment mode Disable

Definition at line 198 of file stm32f3xx_hal_dma.h.

#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC)

Memory increment mode Enable

Definition at line 197 of file stm32f3xx_hal_dma.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Peripheral data size

Defines
DMA Peripheral data size
DMA Exported Constants

Defines

#define | DMA_PDATAALIGN_BYTE (0x00000000U)
#define | DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0)
#define | DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1)

Define Documentation

#define DMA_PDATAALIGN_BYTE (0x00000000U)

Peripheral data alignment : Byte

Definition at line 206 of file stm32f3xx_hal_dma.h.

#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0)

Peripheral data alignment : HalfWord

Definition at line 207 of file stm32f3xx_hal_dma.h.

#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1)

Peripheral data alignment : Word

Definition at line 208 of file stm32f3xx_hal_dma.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Memory data size

Defines
DMA Memory data size
DMA Exported Constants

Defines

#define | DMA_MDATAALIGN_BYTE (0x00000000U)
#define | DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0)
#define | DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1)

Define Documentation

#define DMA_MDATAALIGN_BYTE (0x00000000U)

Memory data alignment : Byte

Definition at line 216 of file stm32f3xx_hal_dma.h.

#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0)

Memory data alignment : HalfWord

Definition at line 217 of file stm32f3xx_hal_dma.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1)

Memory data alignment : Word

Definition at line 218 of file stm32f3xx_hal_dma.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA mode

Defines
DMA mode
DMA Exported Constants

Defines

#define | DMA_NORMAL (0x00000000U)
#define | DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC)

Define Documentation

#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC)

Circular Mode

Definition at line 227 of file stm32f3xx_hal_dma.h.

Referenced by HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_MultiModeStart_DMA(), and HAL_SDADC_Start_DMA().

#define DMA_NORMAL (0x00000000U)

Normal Mode

Definition at line 226 of file stm32f3xx_hal_dma.h.

Referenced by HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_MultiModeStart_DMA(), and HAL_SDADC_Start_DMA().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Priority level

Defines
DMA Priority level
DMA Exported Constants

Defines

#define | DMA_PRIORITY_LOW (0x00000000U)
#define | DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0)
#define | DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1)
#define | DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL)

Define Documentation

#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1)

Priority level : High

Definition at line 237 of file stm32f3xx_hal_dma.h.

#define DMA_PRIORITY_LOW (0x00000000U)

Priority level : Low

Definition at line 235 of file stm32f3xx_hal_dma.h.

#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0)

Priority level : Medium

Definition at line 236 of file stm32f3xx_hal_dma.h.

#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL)

Priority level : Very_High

Definition at line 238 of file stm32f3xx_hal_dma.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA interrupt enable definitions

Defines
DMA interrupt enable definitions
DMA Exported Constants

Defines

#define | DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
#define | DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
#define | DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)

Define Documentation

#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)

Definition at line 248 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)

Definition at line 247 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)

Definition at line 249 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA flag definitions

Defines
DMA flag definitions
DMA Exported Constants

Defines

#define | DMA_FLAG_GL1 (0x00000001U)
#define | DMA_FLAG_TC1 (0x00000002U)
#define | DMA_FLAG_HT1 (0x00000004U)
#define | DMA_FLAG_TE1 (0x00000008U)
#define | DMA_FLAG_GL2 (0x00000010U)
#define | DMA_FLAG_TC2 (0x00000020U)
#define | DMA_FLAG_HT2 (0x00000040U)
#define | DMA_FLAG_TE2 (0x00000080U)
#define | DMA_FLAG_GL3 (0x00000100U)
#define | DMA_FLAG_TC3 (0x00000200U)
#define | DMA_FLAG_HT3 (0x00000400U)
#define | DMA_FLAG_TE3 (0x00000800U)
#define | DMA_FLAG_GL4 (0x00001000U)
#define | DMA_FLAG_TC4 (0x00002000U)
#define | DMA_FLAG_HT4 (0x00004000U)
#define | DMA_FLAG_TE4 (0x00008000U)
#define | DMA_FLAG_GL5 (0x00010000U)
#define | DMA_FLAG_TC5 (0x00020000U)
#define | DMA_FLAG_HT5 (0x00040000U)
#define | DMA_FLAG_TE5 (0x00080000U)
#define | DMA_FLAG_GL6 (0x00100000U)
#define | DMA_FLAG_TC6 (0x00200000U)
#define | DMA_FLAG_HT6 (0x00400000U)
#define | DMA_FLAG_TE6 (0x00800000U)
#define | DMA_FLAG_GL7 (0x01000000U)
#define | DMA_FLAG_TC7 (0x02000000U)
#define | DMA_FLAG_HT7 (0x04000000U)
#define | DMA_FLAG_TE7 (0x08000000U)

Define Documentation

#define DMA_FLAG_GL1 (0x00000001U)

Definition at line 257 of file stm32f3xx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_GL2 (0x00000010U)

Definition at line 261 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_GL3 (0x00000100U)

Definition at line 265 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_GL4 (0x00001000U)

Definition at line 269 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_GL5 (0x00010000U)

Definition at line 273 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_GL6 (0x00100000U)

Definition at line 277 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_GL7 (0x01000000U)

Definition at line 281 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_HT1 (0x00000004U)

Definition at line 259 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_HT2 (0x00000040U)

Definition at line 263 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_HT3 (0x00000400U)

Definition at line 267 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_HT4 (0x00004000U)

Definition at line 271 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_HT5 (0x00040000U)

Definition at line 275 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_HT6 (0x00400000U)

Definition at line 279 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_HT7 (0x04000000U)

Definition at line 283 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_TC1 (0x00000002U)

Definition at line 258 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TC2 (0x00000020U)

Definition at line 262 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_TC3 (0x00000200U)

Definition at line 266 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_TC4 (0x00002000U)

Definition at line 270 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_TC5 (0x00020000U)

Definition at line 274 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_TC6 (0x00200000U)

Definition at line 278 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_TC7 (0x02000000U)

Definition at line 282 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_TE1 (0x00000008U)

Definition at line 260 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TE2 (0x00000080U)

Definition at line 264 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_TE3 (0x00000800U)

Definition at line 268 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_TE4 (0x00008000U)

Definition at line 272 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_TE5 (0x00080000U)

Definition at line 276 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_TE6 (0x00800000U)

Definition at line 280 of file stm32f3xx_hal_dma.h.

#define DMA_FLAG_TE7 (0x08000000U)

Definition at line 284 of file stm32f3xx_hal_dma.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Exported Macros

Defines
DMA Exported Macros
DMA

Defines

#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
Enable the specified DMA Channel.
#define | __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
Disable the specified DMA Channel.
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
Enables the specified DMA Channel interrupts.
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
Disables the specified DMA Channel interrupts.
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
Checks whether the specified DMA Channel interrupt is enabled or disabled.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
Returns the number of remaining data units in the current DMAy Channelx transfer.

Define Documentation

#define __HAL_DMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)

Disable the specified DMA Channel.

Parameters:
__HANDLE__ DMA handle
Return values:
None

Definition at line 317 of file stm32f3xx_hal_dma.h.

Referenced by HAL_I2S_DMAStop().

#define __HAL_DMA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))

Disables the specified DMA Channel interrupts.

Parameters:
__HANDLE__ DMA handle
__INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer complete interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
Return values:
None

Definition at line 344 of file stm32f3xx_hal_dma.h.

#define __HAL_DMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)

Enable the specified DMA Channel.

Parameters:
__HANDLE__ DMA handle
Return values:
None

Definition at line 310 of file stm32f3xx_hal_dma.h.

#define __HAL_DMA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))

Enables the specified DMA Channel interrupts.

Parameters:
__HANDLE__ DMA handle
__INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer complete interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
Return values:
None

Definition at line 332 of file stm32f3xx_hal_dma.h.

#define __HAL_DMA_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CNDTR)

Returns the number of remaining data units in the current DMAy Channelx transfer.

Parameters:
__HANDLE__ DMA handle
Return values:
The number of remaining data units in the current DMA Channel transfer.

Definition at line 364 of file stm32f3xx_hal_dma.h.

#define __HAL_DMA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))

Checks whether the specified DMA Channel interrupt is enabled or disabled.

Parameters:
__HANDLE__ DMA handle
__INTERRUPT__ specifies the DMA interrupt source to check. This parameter can be one of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer complete interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
Return values:
The state of DMA_IT (SET or RESET).

Definition at line 356 of file stm32f3xx_hal_dma.h.

#define __HAL_DMA_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)

Reset DMA handle state.

Parameters:
__HANDLE__ DMA handle.
Return values:
None

Definition at line 303 of file stm32f3xx_hal_dma.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMA

DMA private macros. More...

Defines

#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)

Detailed Description

DMA private macros.

Define Documentation

#define IS_DMA_BUFFER_SIZE ( SIZE ) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))

Definition at line 423 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define IS_DMA_DIRECTION ( DIRECTION )
Value:
(((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))

Definition at line 425 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_MDATAALIGN_BYTE)     || \
                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
                                       ((SIZE) == DMA_MDATAALIGN_WORD ))

Definition at line 439 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_INC_STATE ( STATE )
Value:
(((STATE) == DMA_MINC_ENABLE)  || \
                                        ((STATE) == DMA_MINC_DISABLE))

Definition at line 432 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MODE ( MODE )
Value:
(((MODE) == DMA_NORMAL )  || \
                           ((MODE) == DMA_CIRCULAR))

Definition at line 443 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_PDATAALIGN_BYTE)     || \
                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
                                           ((SIZE) == DMA_PDATAALIGN_WORD))

Definition at line 435 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_INC_STATE ( STATE )
Value:
(((STATE) == DMA_PINC_ENABLE) || \
                                            ((STATE) == DMA_PINC_DISABLE))

Definition at line 429 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PRIORITY ( PRIORITY )
Value:
(((PRIORITY) == DMA_PRIORITY_LOW )   || \
                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))

Definition at line 446 of file stm32f3xx_hal_dma.h.

Referenced by HAL_DMA_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASH Private Constants

Defines
FLASH Private Constants
FLASH

Defines

#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */

Define Documentation

#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */

Definition at line 58 of file stm32f3xx_hal_flash.h.

Referenced by FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_ProgramData(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), HAL_FLASH_OB_Launch(), HAL_FLASH_Program(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_OBErase().

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STM32F373xC HAL User Manual: FLASH Private Macros

Defines
FLASH Private Macros
FLASH

Defines

#define | IS_FLASH_TYPEPROGRAM(VALUE)
#define | IS_FLASH_LATENCY(__LATENCY__)

Define Documentation

#define IS_FLASH_LATENCY ( __LATENCY__ )
Value:
(((__LATENCY__) == FLASH_LATENCY_0) || \
                                       ((__LATENCY__) == FLASH_LATENCY_1) || \
                                       ((__LATENCY__) == FLASH_LATENCY_2))

Definition at line 71 of file stm32f3xx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_FLASH_TYPEPROGRAM ( VALUE )
Value:
(((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
                                      ((VALUE) == FLASH_TYPEPROGRAM_WORD)     || \
                                      ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))

Definition at line 67 of file stm32f3xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

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STM32F373xC HAL User Manual: FLASH Private Variables

Variables
FLASH Private Variables
FLASH

Variables

FLASH_ProcessTypeDef pFlash
FLASH_ProcessTypeDef pFlash

Variable Documentation

FLASH_ProcessTypeDef pFlash

Definition at line 137 of file stm32f3xx_hal_flash.c.

FLASH_ProcessTypeDef pFlash

Definition at line 137 of file stm32f3xx_hal_flash.c.

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STM32F373xC HAL User Manual: FLASH Private Functions

Functions
FLASH Private Functions
FLASH

Functions

static void | FLASH_Program_HalfWord (uint32_t Address, uint16_t Data)
Program a half-word (16-bit) at a specified address.
static void | FLASH_SetErrorCode (void)
Set the specific FLASH error flag.
void | FLASH_PageErase (uint32_t PageAddress)
Erase the specified FLASH memory page.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Function Documentation

void FLASH_PageErase ( uint32_t PageAddress )

Erase the specified FLASH memory page.

Parameters:
PageAddress FLASH page to erase The value of this parameter depend on device used within the same series
Return values:
None

Definition at line 981 of file stm32f3xx_hal_flash_ex.c.

References FLASH_ProcessTypeDef::ErrorCode, and HAL_FLASH_ERROR_NONE.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

static void FLASH_Program_HalfWord | ( | uint32_t | Address,
 |  | uint16_t | Data
 | ) |  | [static]

Program a half-word (16-bit) at a specified address.

Parameters:
Address | specify the address to be programmed.
Data | specify the data to be programmed.
Return values:
None

Definition at line 616 of file stm32f3xx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode, and HAL_FLASH_ERROR_NONE.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

static void FLASH_SetErrorCode ( void ) [static]

Set the specific FLASH error flag.

Return values:
None

Definition at line 676 of file stm32f3xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::ErrorCode, FLASH_FLAG_PGERR, FLASH_FLAG_WRPERR, HAL_FLASH_ERROR_PROG, and HAL_FLASH_ERROR_WRP.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

HAL_StatusTypeDef FLASH_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH operation to complete.

Parameters:
Timeout maximum flash operation timeout
Return values:
HAL Status

Definition at line 633 of file stm32f3xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_GET_FLAG, FLASH_FLAG_BSY, FLASH_FLAG_EOP, FLASH_FLAG_PGERR, FLASH_FLAG_WRPERR, FLASH_SetErrorCode(), and HAL_GetTick().

Referenced by FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_ProgramData(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), HAL_FLASH_OB_Launch(), HAL_FLASH_Program(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_OBErase().

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STM32F373xC HAL User Manual: Programming operation functions

Functions
Programming operation functions
FLASH Exported Functions

Programming operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program halfword, word or double word at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program halfword, word or double word at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.

Detailed Description

Programming operation functions.

Function Documentation

          void HAL_FLASH_EndOfOperationCallback
          (
          uint32_t
          ReturnValue )

FLASH end of operation interrupt callback.

Parameters:

ReturnValue The value saved in this parameter depends on the ongoing procedure

  • Mass Erase: No return value expected
    •

  • Pages Erase: Address of the page which has been erased (if 0xFFFFFFFF, it means that all the selected pages have been erased)
    •

  • Program: Address which was selected for data program
    •

Return values:

none

Definition at line 445 of file stm32f3xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

          void HAL_FLASH_IRQHandler
          (
          void
           )

This function handles FLASH interrupt request.

Return values:

None

Definition at line 302 of file stm32f3xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_DISABLE_IT, __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::Address, FLASH_ProcessTypeDef::Data, FLASH_ProcessTypeDef::DataRemaining, FLASH_FLAG_EOP, FLASH_FLAG_PGERR, FLASH_FLAG_WRPERR, FLASH_IT_EOP, FLASH_IT_ERR, FLASH_PAGE_SIZE, FLASH_PageErase(), FLASH_PROC_MASSERASE, FLASH_PROC_NONE, FLASH_PROC_PAGEERASE, FLASH_PROC_PROGRAMHALFWORD, FLASH_PROC_PROGRAMWORD, FLASH_Program_HalfWord(), FLASH_SetErrorCode(), HAL_FLASH_EndOfOperationCallback(), HAL_FLASH_OperationErrorCallback(), and FLASH_ProcessTypeDef::ProcedureOnGoing.

          void HAL_FLASH_OperationErrorCallback
          (
          uint32_t
          ReturnValue )

FLASH operation error interrupt callback.

Parameters:

ReturnValue The value saved in this parameter depends on the ongoing procedure

  • Mass Erase: No return value expected
    •

  • Pages Erase: Address of the page which returned an error
    •

  • Program: Address which was selected for data program
    •

Return values:

none

Definition at line 463 of file stm32f3xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

HAL_StatusTypeDef HAL_FLASH_Program | ( | uint32_t | TypeProgram,
 |  | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Program halfword, word or double word at a specified address.

Note:
The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface The function HAL_FLASH_Lock() should be called after to lock the FLASH interface

If an erase and a program operations are requested simultaneously, the erase operation is performed before the program one.

FLASH should be previously erased before new programmation (only exception to this is when 0x0000 is programmed)

Parameters:

TypeProgram  | Indicate the way to program at a specified address. This parameter can be a value of FLASH Type Program

Address  | Specifie the address to be programmed.

Data  | Specifie the data to be programmed

Return values:

HAL_StatusTypeDef HAL Status

Definition at line 184 of file stm32f3xx_hal_flash.c.

References assert_param, FLASH_Program_HalfWord(), FLASH_TIMEOUT_VALUE, FLASH_TYPEPROGRAM_HALFWORD, FLASH_TYPEPROGRAM_WORD, FLASH_WaitForLastOperation(), IS_FLASH_PROGRAM_ADDRESS, and IS_FLASH_TYPEPROGRAM.

HAL_StatusTypeDef HAL_FLASH_Program_IT | ( | uint32_t | TypeProgram,
 |  | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Program halfword, word or double word at a specified address with interrupt enabled.

Note:
The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface The function HAL_FLASH_Lock() should be called after to lock the FLASH interface

If an erase and a program operations are requested simultaneously, the erase operation is performed before the program one.

Parameters:

TypeProgram  | Indicate the way to program at a specified address. This parameter can be a value of FLASH Type Program

Address  | Specifie the address to be programmed.

Data  | Specifie the data to be programmed

Return values:

HAL_StatusTypeDef HAL Status

Definition at line 256 of file stm32f3xx_hal_flash.c.

References __HAL_FLASH_ENABLE_IT, FLASH_ProcessTypeDef::Address, assert_param, FLASH_ProcessTypeDef::Data, FLASH_ProcessTypeDef::DataRemaining, FLASH_IT_EOP, FLASH_IT_ERR, FLASH_PROC_PROGRAMDOUBLEWORD, FLASH_PROC_PROGRAMHALFWORD, FLASH_PROC_PROGRAMWORD, FLASH_Program_HalfWord(), FLASH_TYPEPROGRAM_HALFWORD, FLASH_TYPEPROGRAM_WORD, IS_FLASH_PROGRAM_ADDRESS, IS_FLASH_TYPEPROGRAM, and FLASH_ProcessTypeDef::ProcedureOnGoing.

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  doxygen
 1.7.6.1


STM32F373xC HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
FLASH Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.

Detailed Description

management functions

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the FLASH
    memory operations.

Function Documentation

HAL_StatusTypeDef HAL_FLASH_Lock ( void )

Locks the FLASH control register access.

Return values:
HAL Status

Definition at line 516 of file stm32f3xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Launch ( void )

Launch the option byte loading.

Note:
This function will reset automatically the MCU.
Return values:
HAL Status

Definition at line 561 of file stm32f3xx_hal_flash.c.

References FLASH_TIMEOUT_VALUE, and FLASH_WaitForLastOperation().

HAL_StatusTypeDef HAL_FLASH_OB_Lock ( void )

Lock the FLASH Option Control Registers access.

Return values:
HAL Status

Definition at line 548 of file stm32f3xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Unlock ( void )

Unlock the FLASH Option Control Registers access.

Return values:
HAL Status

Definition at line 528 of file stm32f3xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_Unlock ( void )

Unlock the FLASH control register access.

Return values:
HAL Status

Definition at line 496 of file stm32f3xx_hal_flash.c.

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STM32F373xC HAL User Manual: Peripheral errors functions

Functions
Peripheral errors functions
FLASH Exported Functions

Peripheral errors functions. More...

Functions

uint32_t HAL_FLASH_GetError (void)
Get the specific FLASH error flag.

Detailed Description

Peripheral errors functions.

 ===============================================================================
                      ##### Peripheral Errors functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time errors of  the FLASH peripheral.

Function Documentation

uint32_t HAL_FLASH_GetError ( void )

Get the specific FLASH error flag.

Return values:
FLASH_ErrorCode The returned value can be: FLASH Error Codes

Definition at line 593 of file stm32f3xx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode.

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STM32F373xC HAL User Manual: FLASH Exported Types

Data Structures | Enumerations
FLASH Exported Types
FLASH

Data Structures

struct FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Enumerations

enum FLASH_ProcedureTypeDef {
FLASH_PROC_NONE = 0U, FLASH_PROC_PAGEERASE = 1U, FLASH_PROC_MASSERASE = 2U, FLASH_PROC_PROGRAMHALFWORD = 3U,
FLASH_PROC_PROGRAMWORD = 4U, FLASH_PROC_PROGRAMDOUBLEWORD = 5U
}
FLASH Procedure structure definition. More...

Enumeration Type Documentation

enum FLASH_ProcedureTypeDef

FLASH Procedure structure definition.

Enumerator:
FLASH_PROC_NONE
FLASH_PROC_PAGEERASE
FLASH_PROC_MASSERASE
FLASH_PROC_PROGRAMHALFWORD
FLASH_PROC_PROGRAMWORD
FLASH_PROC_PROGRAMDOUBLEWORD

Definition at line 87 of file stm32f3xx_hal_flash.h.

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STM32F373xC HAL User Manual: FLASH_ProcessTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_ProcessTypeDef Struct Reference
FLASH Exported Types

FLASH handle Structure definition. More...

#include <stm32f3xx_hal_flash.h>

Data Fields

__IO FLASH_ProcedureTypeDef | ProcedureOnGoing
__IO uint32_t | DataRemaining
__IO uint32_t | Address
__IO uint64_t | Data
HAL_LockTypeDef | Lock
__IO uint32_t | ErrorCode

Detailed Description

FLASH handle Structure definition.

Definition at line 100 of file stm32f3xx_hal_flash.h.

Field Documentation

__IO uint32_t FLASH_ProcessTypeDef::Address

Internal variable to save address selected for program or erase

Definition at line 106 of file stm32f3xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

__IO uint64_t FLASH_ProcessTypeDef::Data

Internal variable to save data to be programmed

Definition at line 108 of file stm32f3xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASH_Program_IT().

__IO uint32_t FLASH_ProcessTypeDef::DataRemaining

Internal variable to save the remaining pages to erase or half-word to program in IT context

Definition at line 104 of file stm32f3xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

__IO uint32_t FLASH_ProcessTypeDef::ErrorCode

FLASH error code This parameter can be a value of FLASH Error Codes

Definition at line 112 of file stm32f3xx_hal_flash.h.

Referenced by FLASH_MassErase(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_ProgramData(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), FLASH_PageErase(), FLASH_Program_HalfWord(), FLASH_SetErrorCode(), HAL_FLASH_GetError(), and HAL_FLASHEx_OBErase().

HAL_LockTypeDef FLASH_ProcessTypeDef::Lock

FLASH locking object

Definition at line 110 of file stm32f3xx_hal_flash.h.

__IO FLASH_ProcedureTypeDef FLASH_ProcessTypeDef::ProcedureOnGoing

Internal variable to indicate which procedure is ongoing or not in IT context

Definition at line 102 of file stm32f3xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_flash.h
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STM32F373xC HAL User Manual: FLASH Error Codes

Defines
FLASH Error Codes
FLASH Exported Constants

Defines

#define | HAL_FLASH_ERROR_NONE 0x00U
#define | HAL_FLASH_ERROR_PROG 0x01U
#define | HAL_FLASH_ERROR_WRP 0x02U

Define Documentation

#define HAL_FLASH_ERROR_NONE 0x00U

No error

Definition at line 129 of file stm32f3xx_hal_flash.h.

Referenced by FLASH_MassErase(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_ProgramData(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), FLASH_PageErase(), FLASH_Program_HalfWord(), and HAL_FLASHEx_OBErase().

#define HAL_FLASH_ERROR_PROG 0x01U

Programming error

Definition at line 130 of file stm32f3xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_WRP 0x02U

Write protection error

Definition at line 131 of file stm32f3xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

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STM32F373xC HAL User Manual: FLASH Type Program

Defines
FLASH Type Program
FLASH Exported Constants

Defines

#define | FLASH_TYPEPROGRAM_HALFWORD (0x01U)
#define | FLASH_TYPEPROGRAM_WORD (0x02U)
#define | FLASH_TYPEPROGRAM_DOUBLEWORD (0x03U)

Define Documentation

#define FLASH_TYPEPROGRAM_DOUBLEWORD (0x03U)

Program a double word (64-bit) at a specified address

Definition at line 142 of file stm32f3xx_hal_flash.h.

#define FLASH_TYPEPROGRAM_HALFWORD (0x01U)

Program a half-word (16-bit) at a specified address.

Definition at line 140 of file stm32f3xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define FLASH_TYPEPROGRAM_WORD (0x02U)

Program a word (32-bit) at a specified address.

Definition at line 141 of file stm32f3xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

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STM32F373xC HAL User Manual: FLASH Latency

Defines
FLASH Latency
FLASH Exported Constants

Defines

#define | FLASH_LATENCY_0 (0x00000000U)
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_0
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_1

Define Documentation

#define FLASH_LATENCY_0 (0x00000000U)

FLASH Zero Latency cycle

Definition at line 151 of file stm32f3xx_hal_flash.h.

#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0

FLASH One Latency cycle

Definition at line 152 of file stm32f3xx_hal_flash.h.

#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1

FLASH Two Latency cycles

Definition at line 153 of file stm32f3xx_hal_flash.h.

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STM32F373xC HAL User Manual: FLASH Flag definition

Defines
FLASH Flag definition
FLASH Exported Constants

Defines

#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_FLAG_PGERR FLASH_SR_PGERR
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | FLASH_FLAG_EOP FLASH_SR_EOP

Define Documentation

#define FLASH_FLAG_BSY FLASH_SR_BSY

FLASH Busy flag

Definition at line 163 of file stm32f3xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define FLASH_FLAG_EOP FLASH_SR_EOP

FLASH End of Operation flag

Definition at line 166 of file stm32f3xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_PGERR FLASH_SR_PGERR

FLASH Programming error flag

Definition at line 164 of file stm32f3xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR

FLASH Write protected error flag

Definition at line 165 of file stm32f3xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

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STM32F373xC HAL User Manual: FLASH Interrupt definition

Defines
FLASH Interrupt definition
FLASH Exported Constants

Defines

#define | FLASH_IT_EOP FLASH_CR_EOPIE
#define | FLASH_IT_ERR FLASH_CR_ERRIE

Define Documentation

#define FLASH_IT_EOP FLASH_CR_EOPIE

End of FLASH Operation Interrupt source

Definition at line 174 of file stm32f3xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_ERR FLASH_CR_ERRIE

Error Interrupt source

Definition at line 175 of file stm32f3xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASH Half Cycle

Defines
FLASH Half Cycle
FLASH Exported Macros

macros to handle FLASH half cycle More...

Defines

#define | __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)
Enable the FLASH half cycle access.
#define | __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
Disable the FLASH half cycle access.

Detailed Description

macros to handle FLASH half cycle

Define Documentation

#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE ( ) (FLASH->ACR &= (~FLASH_ACR_HLFCYA))

Disable the FLASH half cycle access.

Return values:
None

Definition at line 206 of file stm32f3xx_hal_flash.h.

#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE ( ) (FLASH->ACR |= FLASH_ACR_HLFCYA)

Enable the FLASH half cycle access.

Return values:
None

Definition at line 200 of file stm32f3xx_hal_flash.h.

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STM32F373xC HAL User Manual: FLASH Latency

Defines
FLASH Latency
FLASH Exported Macros

macros to handle FLASH Latency More...

Defines

#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
Get the FLASH Latency.

Detailed Description

macros to handle FLASH Latency

Define Documentation

#define __HAL_FLASH_GET_LATENCY ( ) (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))

Get the FLASH Latency.

Return values:
FLASH Latency This parameter can be one of the following values:
  • FLASH_LATENCY_0 FLASH Zero Latency cycle
  • FLASH_LATENCY_1 FLASH One Latency cycle
  • FLASH_LATENCY_2 FLASH Two Latency cycles

Definition at line 237 of file stm32f3xx_hal_flash.h.

#define __HAL_FLASH_SET_LATENCY ( __LATENCY__ ) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))

Set the FLASH Latency.

Parameters:
__LATENCY__ FLASH Latency This parameter can be one of the following values:
  • FLASH_LATENCY_0 FLASH Zero Latency cycle
  • FLASH_LATENCY_1 FLASH One Latency cycle
  • FLASH_LATENCY_2 FLASH Two Latency cycles
Return values:
None

Definition at line 226 of file stm32f3xx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASH Prefetch

Defines
FLASH Prefetch
FLASH Exported Macros

macros to handle FLASH Prefetch buffer More...

Defines

#define | __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
Enable the FLASH prefetch buffer.
#define | __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
Disable the FLASH prefetch buffer.

Detailed Description

macros to handle FLASH Prefetch buffer

Define Documentation

#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE ( ) (FLASH->ACR &= (~FLASH_ACR_PRFTBE))

Disable the FLASH prefetch buffer.

Return values:
None

Definition at line 257 of file stm32f3xx_hal_flash.h.

#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE ( ) (FLASH->ACR |= FLASH_ACR_PRFTBE)

Enable the FLASH prefetch buffer.

Return values:
None

Definition at line 251 of file stm32f3xx_hal_flash.h.

Referenced by HAL_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASH Interrupts

Defines
FLASH Interrupts
FLASH Exported Macros

macros to handle FLASH interrupts More...

Defines

#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__))
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__))
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__))
Get the specified FLASH flag status.
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__))
Clear the specified FLASH flag.

Detailed Description

macros to handle FLASH interrupts

Define Documentation

#define __HAL_FLASH_CLEAR_FLAG ( __FLAG__ ) ((FLASH->SR) = (__FLAG__))

Clear the specified FLASH flag.

Parameters:
__FLAG__ specifies the FLASH flags to clear. This parameter can be any combination of the following values:
  • FLASH_FLAG_EOP FLASH End of Operation flag
  • FLASH_FLAG_WRPERR FLASH Write protected error flag
  • FLASH_FLAG_PGERR FLASH Programming error flag
Return values:
none

Definition at line 309 of file stm32f3xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define __HAL_FLASH_DISABLE_IT ( __INTERRUPT__ ) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__))

Disable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ FLASH interrupt This parameter can be any combination of the following values:
  • FLASH_IT_EOP End of FLASH Operation Interrupt
  • FLASH_IT_ERR Error Interrupt
Return values:
none

Definition at line 286 of file stm32f3xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

#define __HAL_FLASH_ENABLE_IT ( __INTERRUPT__ ) SET_BIT((FLASH->CR), (__INTERRUPT__))

Enable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ FLASH interrupt This parameter can be any combination of the following values:
  • FLASH_IT_EOP End of FLASH Operation Interrupt
  • FLASH_IT_ERR Error Interrupt
Return values:
none

Definition at line 276 of file stm32f3xx_hal_flash.h.

Referenced by HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define __HAL_FLASH_GET_FLAG ( __FLAG__ ) (((FLASH->SR) & (__FLAG__)) == (__FLAG__))

Get the specified FLASH flag status.

Parameters:
__FLAG__ specifies the FLASH flag to check. This parameter can be one of the following values:
  • FLASH_FLAG_BSY FLASH Busy flag
  • FLASH_FLAG_EOP FLASH End of Operation flag
  • FLASH_FLAG_WRPERR FLASH Write protected error flag
  • FLASH_FLAG_PGERR FLASH Programming error flag
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 298 of file stm32f3xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASHEx Private Constants

Defines
FLASHEx Private Constants
FLASHEx

Defines

#define | FLASH_POSITION_IWDGSW_BIT (uint32_t)POSITION_VAL(FLASH_OBR_IWDG_SW)
#define | FLASH_POSITION_OB_USERDATA0_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA0)
#define | FLASH_POSITION_OB_USERDATA1_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA1)
#define | FLASH_SIZE_DATA_REGISTER (0x1FFFF7CCU)

Define Documentation

#define FLASH_POSITION_IWDGSW_BIT (uint32_t)POSITION_VAL(FLASH_OBR_IWDG_SW)

Definition at line 92 of file stm32f3xx_hal_flash_ex.c.

Referenced by FLASH_OB_GetUser().

#define FLASH_POSITION_OB_USERDATA0_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA0)

Definition at line 93 of file stm32f3xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetUserData().

#define FLASH_POSITION_OB_USERDATA1_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA1)

Definition at line 94 of file stm32f3xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetUserData().

#define FLASH_SIZE_DATA_REGISTER (0x1FFFF7CCU)

Definition at line 59 of file stm32f3xx_hal_flash_ex.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASHEx Private Macros

Defines
FLASHEx Private Macros
FLASHEx

Defines

#define | IS_FLASH_TYPEERASE(VALUE)
#define | IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))
#define | IS_WRPSTATE(VALUE)
#define | IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
#define | IS_OB_RDP_LEVEL(LEVEL)
#define | IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define | IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define | IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define | IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
#define | IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
#define | IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
#define | IS_OB_SDACD_VDD_MONITOR(VDD_MONITOR)
#define | IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
#define | IS_FLASH_PROGRAM_ADDRESS(ADDRESS)
#define | IS_FLASH_NB_PAGES(ADDRESS, NBPAGES)

Define Documentation

#define IS_FLASH_NB_PAGES | ( | ADDRESS,
 |  | NBPAGES
 | ) |
Value:
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0803FFFFU) : \
                                           (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U)  ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0801FFFFU) : \
                                            ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0800FFFFU)))

Definition at line 123 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_FLASH_PROGRAM_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \
                                           ((ADDRESS) <= 0x0803FFFFU) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
                                           ((ADDRESS) <= 0x0801FFFFU) :  ((ADDRESS) <= 0x0800FFFFU))))

Definition at line 103 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_FLASH_TYPEERASE ( VALUE )
Value:
(((VALUE) == FLASH_TYPEERASE_PAGES) || \
                             ((VALUE) == FLASH_TYPEERASE_MASSERASE))

Definition at line 68 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_OB_BOOT1 ( BOOT1 ) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))

Definition at line 87 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_DATA_ADDRESS ( ADDRESS ) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))

Definition at line 76 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_ProgramData().

#define IS_OB_IWDG_SOURCE ( SOURCE ) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))

Definition at line 81 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_RDP_LEVEL ( LEVEL )
Value:
(((LEVEL) == OB_RDP_LEVEL_0)   ||\
                                    ((LEVEL) == OB_RDP_LEVEL_1))/*||\
                                    ((LEVEL) == OB_RDP_LEVEL_2))*/

Definition at line 78 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_RDP_LevelConfig().

#define IS_OB_SDACD_VDD_MONITOR ( VDD_MONITOR )
Value:
(((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_SET) || \
                                              ((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_RESET))

Definition at line 95 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_SRAM_PARITY ( PARITY ) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))

Definition at line 91 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_STDBY_SOURCE ( SOURCE ) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))

Definition at line 85 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_STOP_SOURCE ( SOURCE ) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))

Definition at line 83 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_VDDA_ANALOG ( ANALOG ) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))

Definition at line 89 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_WRP ( PAGE ) (((PAGE) != 0x0000000U))

Definition at line 99 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_DisableWRP(), and FLASH_OB_EnableWRP().

#define IS_OPTIONBYTE ( VALUE ) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))

Definition at line 71 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define IS_WRPSTATE ( VALUE )
Value:
(((VALUE) == OB_WRPSTATE_DISABLE) || \
                            ((VALUE) == OB_WRPSTATE_ENABLE))

Definition at line 73 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASHEx Private Functions

Functions
FLASHEx Private Functions
FLASHEx

Functions

static void | FLASH_MassErase (void)
Full erase of FLASH memory Bank.
void | FLASH_PageErase (uint32_t PageAddress)
Erase the specified FLASH memory page.
static HAL_StatusTypeDef | FLASH_OB_EnableWRP (uint32_t WriteProtectPage)
Enable the write protection of the desired pages.
static HAL_StatusTypeDef | FLASH_OB_DisableWRP (uint32_t WriteProtectPage)
Disable the write protection of the desired pages.
static HAL_StatusTypeDef | FLASH_OB_RDP_LevelConfig (uint8_t ReadProtectLevel)
Set the read protection level.
static HAL_StatusTypeDef | FLASH_OB_UserConfig (uint8_t UserConfig)
Program the FLASH User Option Byte.
static HAL_StatusTypeDef | FLASH_OB_ProgramData (uint32_t Address, uint8_t Data)
Programs a half word at a specified Option Byte Data address.
static uint32_t | FLASH_OB_GetWRP (void)
Return the FLASH Write Protection Option Bytes value.
static uint32_t | FLASH_OB_GetRDP (void)
Returns the FLASH Read Protection level.
static uint8_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.

Function Documentation

static void FLASH_MassErase ( void ) [static]

Full erase of FLASH memory Bank.

Return values:
None

Definition at line 516 of file stm32f3xx_hal_flash_ex.c.

References FLASH_ProcessTypeDef::ErrorCode, and HAL_FLASH_ERROR_NONE.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

static HAL_StatusTypeDef FLASH_OB_DisableWRP ( uint32_t WriteProtectPage ) [static]

Disable the write protection of the desired pages.

Note:
An option byte erase is done automatically in this function.
When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase the flash page i if debug features are connected or boot code is executed in RAM, even if nWRPi = 1
Parameters:
WriteProtectPage specifies the page(s) to be write unprotected. The value of this parameter depend on device used within the same series
Return values:
HAL status

Definition at line 649 of file stm32f3xx_hal_flash_ex.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_OB_GetWRP(), FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, HAL_FLASHEx_OBErase(), IS_OB_WRP, OB_WRP_PAGES0TO15MASK, OB_WRP_PAGES16TO31MASK, OB_WRP_PAGES32TO47MASK, and OB_WRP_PAGES48TO127MASK.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_EnableWRP ( uint32_t WriteProtectPage ) [static]

Enable the write protection of the desired pages.

Note:
An option byte erase is done automatically in this function.
When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase the flash page i if debug features are connected or boot code is executed in RAM, even if nWRPi = 1
Parameters:
WriteProtectPage specifies the page(s) to be write protected. The value of this parameter depend on device used within the same series
Return values:
HAL status

Definition at line 537 of file stm32f3xx_hal_flash_ex.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_OB_GetWRP(), FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, HAL_FLASHEx_OBErase(), IS_OB_WRP, OB_WRP_PAGES0TO15MASK, OB_WRP_PAGES16TO31MASK, OB_WRP_PAGES32TO47MASK, and OB_WRP_PAGES48TO127MASK.

Referenced by HAL_FLASHEx_OBProgram().

static uint32_t FLASH_OB_GetRDP ( void ) [static]

Returns the FLASH Read Protection level.

Return values:
FLASH RDP level This parameter can be one of the following values:
  • OB_RDP_LEVEL_0 No protection
  • OB_RDP_LEVEL_1 Read protection of the memory
  • OB_RDP_LEVEL_2 Full chip protection

Definition at line 911 of file stm32f3xx_hal_flash_ex.c.

References OB_RDP_LEVEL_0, OB_RDP_LEVEL_1, and OB_RDP_LEVEL_2.

Referenced by HAL_FLASHEx_OBErase(), and HAL_FLASHEx_OBGetConfig().

static uint8_t FLASH_OB_GetUser ( void ) [static]

Return the FLASH User Option Byte value.

Return values:
The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4), VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .

Definition at line 952 of file stm32f3xx_hal_flash_ex.c.

References FLASH_POSITION_IWDGSW_BIT.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetWRP ( void ) [static]

Return the FLASH Write Protection Option Bytes value.

Return values:
The FLASH Write Protection Option Bytes value

Definition at line 897 of file stm32f3xx_hal_flash_ex.c.

Referenced by FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), and HAL_FLASHEx_OBGetConfig().

static HAL_StatusTypeDef FLASH_OB_ProgramData | ( | uint32_t | Address,
 |  | uint8_t | Data
 | ) |  | [static]

Programs a half word at a specified Option Byte Data address.

Note:
The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes (system reset will occur) Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
Parameters:
Address | specifies the address to be programmed. This parameter can be 0x1FFFF804 or 0x1FFFF806.
Data | specifies the data to be programmed.
Return values:
HAL status

Definition at line 864 of file stm32f3xx_hal_flash_ex.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, and IS_OB_DATA_ADDRESS.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig ( uint8_t ReadProtectLevel ) [static]

Set the read protection level.

Parameters:
ReadProtectLevel specifies the read protection level. This parameter can be one of the following values:
  • OB_RDP_LEVEL_0 No protection
  • OB_RDP_LEVEL_1 Read protection of the memory
  • OB_RDP_LEVEL_2 Full chip protection
Note:
Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
Return values:
HAL status

Definition at line 759 of file stm32f3xx_hal_flash_ex.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, and IS_OB_RDP_LEVEL.

Referenced by HAL_FLASHEx_OBErase(), and HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_UserConfig ( uint8_t UserConfig ) [static]

Program the FLASH User Option Byte.

Note:
Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
Parameters:
UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4), VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
Return values:
HAL status

Definition at line 810 of file stm32f3xx_hal_flash_ex.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_OB_BOOT1, IS_OB_IWDG_SOURCE, IS_OB_SDACD_VDD_MONITOR, IS_OB_SRAM_PARITY, IS_OB_STDBY_SOURCE, IS_OB_STOP_SOURCE, IS_OB_VDDA_ANALOG, OB_BOOT1_SET, OB_IWDG_SW, OB_SDACD_VDD_MONITOR_SET, OB_SRAM_PARITY_RESET, OB_STDBY_NO_RST, OB_STOP_NO_RST, and OB_VDDA_ANALOG_ON.

Referenced by HAL_FLASHEx_OBProgram().

void FLASH_PageErase ( uint32_t PageAddress )

Erase the specified FLASH memory page.

Parameters:
PageAddress FLASH page to erase The value of this parameter depend on device used within the same series
Return values:
None

Definition at line 981 of file stm32f3xx_hal_flash_ex.c.

References FLASH_ProcessTypeDef::ErrorCode, and HAL_FLASH_ERROR_NONE.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASHEx Memory Erasing functions

Functions
FLASHEx Memory Erasing functions
FLASHEx Exported Functions

FLASH Memory Erasing functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.

Detailed Description

FLASH Memory Erasing functions.

  ==============================================================================
                ##### FLASH Erasing Programming functions #####
  ==============================================================================

    [..] The FLASH Memory Erasing functions, includes the following functions:
    (+) @ref HAL_FLASHEx_Erase: return only when erase has been done
    (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback
        is called with parameter 0xFFFFFFFF

    [..] Any operation of erase should follow these steps:
    (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and
        program memory access.
    (#) Call the desired function to erase page.
    (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access
       (recommended to protect the FLASH memory against possible unwanted operation).

Function Documentation

HAL_StatusTypeDef HAL_FLASHEx_Erase | ( | FLASH_EraseInitTypeDef * | pEraseInit,
 |  | uint32_t * | PageError
 | ) |  |

Perform a mass erase or erase the specified FLASH memory pages.

Note:
To correctly run this function, the HAL_FLASH_Unlock() function must be called before. Call the HAL_FLASH_Lock() to disable the flash memory access (recommended to protect the FLASH memory against possible unwanted operation)
Parameters:
[in] | pEraseInit | pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
[out] | PageError | pointer to variable that contains the configuration information on faulty page in case of error (0xFFFFFFFF means that all the pages have been correctly erased)
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 175 of file stm32f3xx_hal_flash_ex.c.

References assert_param, FLASH_MassErase(), FLASH_PAGE_SIZE, FLASH_PageErase(), FLASH_TIMEOUT_VALUE, FLASH_TYPEERASE_MASSERASE, FLASH_WaitForLastOperation(), IS_FLASH_NB_PAGES, IS_FLASH_PROGRAM_ADDRESS, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbPages, FLASH_EraseInitTypeDef::PageAddress, and FLASH_EraseInitTypeDef::TypeErase.

HAL_StatusTypeDef HAL_FLASHEx_Erase_IT ( FLASH_EraseInitTypeDef * pEraseInit )

Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.

Note:
To correctly run this function, the HAL_FLASH_Unlock() function must be called before. Call the HAL_FLASH_Lock() to disable the flash memory access (recommended to protect the FLASH memory against possible unwanted operation)
Parameters:
pEraseInit pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 256 of file stm32f3xx_hal_flash_ex.c.

References __HAL_FLASH_ENABLE_IT, FLASH_ProcessTypeDef::Address, assert_param, FLASH_ProcessTypeDef::DataRemaining, FLASH_IT_EOP, FLASH_IT_ERR, FLASH_MassErase(), FLASH_PageErase(), FLASH_PROC_MASSERASE, FLASH_PROC_NONE, FLASH_PROC_PAGEERASE, FLASH_TYPEERASE_MASSERASE, IS_FLASH_NB_PAGES, IS_FLASH_PROGRAM_ADDRESS, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbPages, FLASH_EraseInitTypeDef::PageAddress, FLASH_ProcessTypeDef::ProcedureOnGoing, and FLASH_EraseInitTypeDef::TypeErase.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Option Bytes Programming functions

Functions
Option Bytes Programming functions
FLASHEx Exported Functions

Option Bytes Programming functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASHEx_OBErase (void)
Erases the FLASH option bytes.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
uint32_t | HAL_FLASHEx_OBGetUserData (uint32_t DATAAdress)
Get the Option byte user data.

Detailed Description

Option Bytes Programming functions.

  ==============================================================================
                ##### Option Bytes Programming functions #####
  ==============================================================================
    [..]
    This subsection provides a set of functions allowing to control the FLASH
    option bytes operations.

Function Documentation

HAL_StatusTypeDef HAL_FLASHEx_OBErase ( void )

Erases the FLASH option bytes.

Note:
This functions erases all option bytes except the Read protection (RDP). The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes (system reset will occur)
Return values:
HAL status

Definition at line 329 of file stm32f3xx_hal_flash_ex.c.

References FLASH_ProcessTypeDef::ErrorCode, FLASH_OB_GetRDP(), FLASH_OB_RDP_LevelConfig(), FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, and OB_RDP_LEVEL_0.

Referenced by FLASH_OB_DisableWRP(), and FLASH_OB_EnableWRP().

void HAL_FLASHEx_OBGetConfig ( FLASH_OBProgramInitTypeDef * pOBInit )

Get the Option byte configuration.

Parameters:
pOBInit pointer to an FLASH_OBInitStruct structure that contains the configuration information for the programming.
Return values:
None

Definition at line 459 of file stm32f3xx_hal_flash_ex.c.

References FLASH_OB_GetRDP(), FLASH_OB_GetUser(), FLASH_OB_GetWRP(), OPTIONBYTE_RDP, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::USERConfig, and FLASH_OBProgramInitTypeDef::WRPPage.

uint32_t HAL_FLASHEx_OBGetUserData ( uint32_t DATAAdress )

Get the Option byte user data.

Parameters:
DATAAdress Address of the option byte DATA This parameter can be one of the following values:
  • OB_DATA_ADDRESS_DATA0
  • OB_DATA_ADDRESS_DATA1
Return values:
Value programmed in USER data

Definition at line 481 of file stm32f3xx_hal_flash_ex.c.

References FLASH_POSITION_OB_USERDATA0_BIT, FLASH_POSITION_OB_USERDATA1_BIT, and OB_DATA_ADDRESS_DATA0.

HAL_StatusTypeDef HAL_FLASHEx_OBProgram ( FLASH_OBProgramInitTypeDef * pOBInit )

Program option bytes.

Note:
The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes (system reset will occur)
Parameters:
pOBInit pointer to an FLASH_OBInitStruct structure that contains the configuration information for the programming.
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 378 of file stm32f3xx_hal_flash_ex.c.

References assert_param, FLASH_OBProgramInitTypeDef::DATAAddress, FLASH_OBProgramInitTypeDef::DATAData, FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_ProgramData(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), IS_OPTIONBYTE, IS_WRPSTATE, OB_WRPSTATE_ENABLE, OPTIONBYTE_DATA, OPTIONBYTE_RDP, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::USERConfig, FLASH_OBProgramInitTypeDef::WRPPage, and FLASH_OBProgramInitTypeDef::WRPState.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASH_EraseInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_EraseInitTypeDef Struct Reference
FLASHEx Exported Types

FLASH Erase structure definition. More...

#include <stm32f3xx_hal_flash_ex.h>

Data Fields

uint32_t | TypeErase
uint32_t | PageAddress
uint32_t | NbPages

Detailed Description

FLASH Erase structure definition.

Definition at line 152 of file stm32f3xx_hal_flash_ex.h.

Field Documentation

uint32_t FLASH_EraseInitTypeDef::NbPages

NbPages: Number of pagess to be erased. This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)

Definition at line 160 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::PageAddress

PageAdress: Initial FLASH page address to erase when mass erase is disabled This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END

Definition at line 157 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::TypeErase

TypeErase: Mass erase or page erase. This parameter can be a value of FLASH Type Erase

Definition at line 154 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_flash_ex.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASH_OBProgramInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_OBProgramInitTypeDef Struct Reference
FLASHEx Exported Types

FLASH Options bytes program structure definition. More...

#include <stm32f3xx_hal_flash_ex.h>

Data Fields

uint32_t | OptionType
uint32_t | WRPState
uint32_t | WRPPage
uint8_t | RDPLevel
uint8_t | USERConfig
uint32_t | DATAAddress
uint8_t | DATAData

Detailed Description

FLASH Options bytes program structure definition.

Definition at line 168 of file stm32f3xx_hal_flash_ex.h.

Field Documentation

uint32_t FLASH_OBProgramInitTypeDef::DATAAddress

DATAAddress: Address of the option byte DATA to be programmed This parameter can be a value of Option Byte Data Address

Definition at line 195 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

uint8_t FLASH_OBProgramInitTypeDef::DATAData

DATAData: Data to be stored in the option byte DATA This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU

Definition at line 198 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::OptionType

OptionType: Option byte to be configured. This parameter can be a value of Option Bytes Type

Definition at line 170 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint8_t FLASH_OBProgramInitTypeDef::RDPLevel

RDPLevel: Set the read protection level.. This parameter can be a value of Option Byte Read Protection

Definition at line 179 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint8_t FLASH_OBProgramInitTypeDef::USERConfig

USERConfig: Program the FLASH User Option Byte: IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY / SDADC12_VDD_MONITOR This parameter can be a combination of Option Byte IWatchdog, Option Byte nRST STOP, Option Byte nRST STDBY, Option Byte BOOT1, Option Byte VDDA Analog Monitoring, Option Byte SRAM Parity Check Enable. And OB SDADC12 VDD MONITOR (only for STM32F373xC & STM32F378xx devices)

Definition at line 182 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPPage

WRPPage: specifies the page(s) to be write protected This parameter can be a value of FLASHEx OB Write Protection

Definition at line 176 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPState

WRPState: Write protection activation or deactivation. This parameter can be a value of Option Byte WRP State

Definition at line 173 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_flash_ex.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASHEx Page Size

Defines
FLASHEx Page Size
FLASHEx Exported Constants

Defines

#define FLASH_PAGE_SIZE 0x800

Define Documentation

#define FLASH_PAGE_SIZE 0x800

Definition at line 213 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASH Type Erase

Defines
FLASH Type Erase
FLASHEx Exported Constants

Defines

#define | FLASH_TYPEERASE_PAGES (0x00U)
#define | FLASH_TYPEERASE_MASSERASE (0x01U)

Define Documentation

#define FLASH_TYPEERASE_MASSERASE (0x01U)

Flash mass erase activation

Definition at line 222 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define FLASH_TYPEERASE_PAGES (0x00U)

Pages erase only

Definition at line 221 of file stm32f3xx_hal_flash_ex.h.

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STM32F373xC HAL User Manual: Option Bytes Type

Defines
Option Bytes Type
Option Byte Constants

Defines

#define | OPTIONBYTE_WRP (0x01U)
#define | OPTIONBYTE_RDP (0x02U)
#define | OPTIONBYTE_USER (0x04U)
#define | OPTIONBYTE_DATA (0x08U)

Define Documentation

#define OPTIONBYTE_DATA (0x08U)

DATA option byte configuration

Definition at line 238 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_RDP (0x02U)

RDP option byte configuration

Definition at line 236 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_USER (0x04U)

USER option byte configuration

Definition at line 237 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_WRP (0x01U)

WRP option byte configuration

Definition at line 235 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Option Byte WRP State

Defines
Option Byte WRP State
Option Byte Constants

Defines

#define | OB_WRPSTATE_DISABLE (0x00U)
#define | OB_WRPSTATE_ENABLE (0x01U)

Define Documentation

#define OB_WRPSTATE_DISABLE (0x00U)

Disable the write protection of the desired pages

Definition at line 247 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRPSTATE_ENABLE (0x01U)

Enable the write protection of the desired pagess

Definition at line 248 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASHEx OB Write Protection

Defines
FLASHEx OB Write Protection
Option Byte Constants

Defines

#define | OB_WRP_PAGES0TO1 (0x00000001U) /* Write protection of page 0 to 1 */
#define | OB_WRP_PAGES2TO3 (0x00000002U) /* Write protection of page 2 to 3 */
#define | OB_WRP_PAGES4TO5 (0x00000004U) /* Write protection of page 4 to 5 */
#define | OB_WRP_PAGES6TO7 (0x00000008U) /* Write protection of page 6 to 7 */
#define | OB_WRP_PAGES8TO9 (0x00000010U) /* Write protection of page 8 to 9 */
#define | OB_WRP_PAGES10TO11 (0x00000020U) /* Write protection of page 10 to 11 */
#define | OB_WRP_PAGES12TO13 (0x00000040U) /* Write protection of page 12 to 13 */
#define | OB_WRP_PAGES14TO15 (0x00000080U) /* Write protection of page 14 to 15 */
#define | OB_WRP_PAGES16TO17 (0x00000100U) /* Write protection of page 16 to 17 */
#define | OB_WRP_PAGES18TO19 (0x00000200U) /* Write protection of page 18 to 19 */
#define | OB_WRP_PAGES20TO21 (0x00000400U) /* Write protection of page 20 to 21 */
#define | OB_WRP_PAGES22TO23 (0x00000800U) /* Write protection of page 22 to 23 */
#define | OB_WRP_PAGES24TO25 (0x00001000U) /* Write protection of page 24 to 25 */
#define | OB_WRP_PAGES26TO27 (0x00002000U) /* Write protection of page 26 to 27 */
#define | OB_WRP_PAGES28TO29 (0x00004000U) /* Write protection of page 28 to 29 */
#define | OB_WRP_PAGES30TO31 (0x00008000U) /* Write protection of page 30 to 31 */
#define | OB_WRP_PAGES32TO33 (0x00010000U) /* Write protection of page 32 to 33 */
#define | OB_WRP_PAGES34TO35 (0x00020000U) /* Write protection of page 34 to 35 */
#define | OB_WRP_PAGES36TO37 (0x00040000U) /* Write protection of page 36 to 37 */
#define | OB_WRP_PAGES38TO39 (0x00080000U) /* Write protection of page 38 to 39 */
#define | OB_WRP_PAGES40TO41 (0x00100000U) /* Write protection of page 40 to 41 */
#define | OB_WRP_PAGES42TO43 (0x00200000U) /* Write protection of page 42 to 43 */
#define | OB_WRP_PAGES44TO45 (0x00400000U) /* Write protection of page 44 to 45 */
#define | OB_WRP_PAGES46TO47 (0x00800000U) /* Write protection of page 46 to 47 */
#define | OB_WRP_PAGES48TO49 (0x01000000U) /* Write protection of page 48 to 49 */
#define | OB_WRP_PAGES50TO51 (0x02000000U) /* Write protection of page 50 to 51 */
#define | OB_WRP_PAGES52TO53 (0x04000000U) /* Write protection of page 52 to 53 */
#define | OB_WRP_PAGES54TO55 (0x08000000U) /* Write protection of page 54 to 55 */
#define | OB_WRP_PAGES56TO57 (0x10000000U) /* Write protection of page 56 to 57 */
#define | OB_WRP_PAGES58TO59 (0x20000000U) /* Write protection of page 58 to 59 */
#define | OB_WRP_PAGES60TO61 (0x40000000U) /* Write protection of page 60 to 61 */
#define | OB_WRP_PAGES62TO127 (0x80000000U) /* Write protection of page 62 to 127 */
#define | OB_WRP_PAGES0TO15MASK (0x000000FFU)
#define | OB_WRP_PAGES16TO31MASK (0x0000FF00U)
#define | OB_WRP_PAGES32TO47MASK (0x00FF0000U)
#define | OB_WRP_PAGES32TO47MASK (0x00FF0000U)
#define | OB_WRP_PAGES48TO127MASK (0xFF000000U)
#define | OB_WRP_PAGES48TO127MASK (0xFF000000U)
#define | OB_WRP_ALLPAGES (0xFFFFFFFFU)

Define Documentation

#define OB_WRP_ALLPAGES (0xFFFFFFFFU)

Write protection of all pages

Definition at line 339 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES0TO1 (0x00000001U) /* Write protection of page 0 to 1 */

Definition at line 257 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES0TO15MASK (0x000000FFU)

Definition at line 314 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_DisableWRP(), and FLASH_OB_EnableWRP().

#define OB_WRP_PAGES10TO11 (0x00000020U) /* Write protection of page 10 to 11 */

Definition at line 262 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES12TO13 (0x00000040U) /* Write protection of page 12 to 13 */

Definition at line 263 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES14TO15 (0x00000080U) /* Write protection of page 14 to 15 */

Definition at line 264 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES16TO17 (0x00000100U) /* Write protection of page 16 to 17 */

Definition at line 265 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES16TO31MASK (0x0000FF00U)

Definition at line 315 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_DisableWRP(), and FLASH_OB_EnableWRP().

#define OB_WRP_PAGES18TO19 (0x00000200U) /* Write protection of page 18 to 19 */

Definition at line 266 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES20TO21 (0x00000400U) /* Write protection of page 20 to 21 */

Definition at line 267 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES22TO23 (0x00000800U) /* Write protection of page 22 to 23 */

Definition at line 268 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES24TO25 (0x00001000U) /* Write protection of page 24 to 25 */

Definition at line 269 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES26TO27 (0x00002000U) /* Write protection of page 26 to 27 */

Definition at line 270 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES28TO29 (0x00004000U) /* Write protection of page 28 to 29 */

Definition at line 271 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES2TO3 (0x00000002U) /* Write protection of page 2 to 3 */

Definition at line 258 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES30TO31 (0x00008000U) /* Write protection of page 30 to 31 */

Definition at line 272 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES32TO33 (0x00010000U) /* Write protection of page 32 to 33 */

Definition at line 276 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES32TO47MASK (0x00FF0000U)

Definition at line 331 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_DisableWRP(), and FLASH_OB_EnableWRP().

#define OB_WRP_PAGES32TO47MASK (0x00FF0000U)

Definition at line 331 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES34TO35 (0x00020000U) /* Write protection of page 34 to 35 */

Definition at line 277 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES36TO37 (0x00040000U) /* Write protection of page 36 to 37 */

Definition at line 278 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES38TO39 (0x00080000U) /* Write protection of page 38 to 39 */

Definition at line 279 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES40TO41 (0x00100000U) /* Write protection of page 40 to 41 */

Definition at line 280 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES42TO43 (0x00200000U) /* Write protection of page 42 to 43 */

Definition at line 281 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES44TO45 (0x00400000U) /* Write protection of page 44 to 45 */

Definition at line 282 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES46TO47 (0x00800000U) /* Write protection of page 46 to 47 */

Definition at line 283 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES48TO127MASK (0xFF000000U)

Definition at line 332 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_DisableWRP(), and FLASH_OB_EnableWRP().

#define OB_WRP_PAGES48TO127MASK (0xFF000000U)

Definition at line 332 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES48TO49 (0x01000000U) /* Write protection of page 48 to 49 */

Definition at line 284 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES4TO5 (0x00000004U) /* Write protection of page 4 to 5 */

Definition at line 259 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES50TO51 (0x02000000U) /* Write protection of page 50 to 51 */

Definition at line 285 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES52TO53 (0x04000000U) /* Write protection of page 52 to 53 */

Definition at line 286 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES54TO55 (0x08000000U) /* Write protection of page 54 to 55 */

Definition at line 287 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES56TO57 (0x10000000U) /* Write protection of page 56 to 57 */

Definition at line 288 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES58TO59 (0x20000000U) /* Write protection of page 58 to 59 */

Definition at line 289 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES60TO61 (0x40000000U) /* Write protection of page 60 to 61 */

Definition at line 290 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES62TO127 (0x80000000U) /* Write protection of page 62 to 127 */

Definition at line 291 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES6TO7 (0x00000008U) /* Write protection of page 6 to 7 */

Definition at line 260 of file stm32f3xx_hal_flash_ex.h.

#define OB_WRP_PAGES8TO9 (0x00000010U) /* Write protection of page 8 to 9 */

Definition at line 261 of file stm32f3xx_hal_flash_ex.h.

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STM32F373xC HAL User Manual: Option Byte Read Protection

Defines
Option Byte Read Protection
Option Byte Constants

Defines

#define | OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
#define | OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
#define | OB_RDP_LEVEL_2 ((uint8_t)0xCCU)

Define Documentation

#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)

Definition at line 357 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetRDP(), and HAL_FLASHEx_OBErase().

#define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)

Definition at line 358 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetRDP().

#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU)

Warning: When enabling read protection level 2 it's no more possible to go back to level 1 or 0U

Definition at line 359 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetRDP().

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STM32F373xC HAL User Manual: Option Byte IWatchdog

Defines
Option Byte IWatchdog
Option Byte Constants

Defines

#define | OB_IWDG_SW ((uint8_t)0x01U)
#define | OB_IWDG_HW ((uint8_t)0x00U)

Define Documentation

#define OB_IWDG_HW ((uint8_t)0x00U)

Hardware IWDG selected

Definition at line 369 of file stm32f3xx_hal_flash_ex.h.

#define OB_IWDG_SW ((uint8_t)0x01U)

Software IWDG selected

Definition at line 368 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Option Byte nRST STOP

Defines
Option Byte nRST STOP
Option Byte Constants

Defines

#define | OB_STOP_NO_RST ((uint8_t)0x02U)
#define | OB_STOP_RST ((uint8_t)0x00U)

Define Documentation

#define OB_STOP_NO_RST ((uint8_t)0x02U)

No reset generated when entering in STOP

Definition at line 377 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_STOP_RST ((uint8_t)0x00U)

Reset generated when entering in STOP

Definition at line 378 of file stm32f3xx_hal_flash_ex.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Option Byte nRST STDBY

Defines
Option Byte nRST STDBY
Option Byte Constants

Defines

#define | OB_STDBY_NO_RST ((uint8_t)0x04U)
#define | OB_STDBY_RST ((uint8_t)0x00U)

Define Documentation

#define OB_STDBY_NO_RST ((uint8_t)0x04U)

No reset generated when entering in STANDBY

Definition at line 386 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_STDBY_RST ((uint8_t)0x00U)

Reset generated when entering in STANDBY

Definition at line 387 of file stm32f3xx_hal_flash_ex.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Option Byte BOOT1

Defines
Option Byte BOOT1
Option Byte Constants

Defines

#define | OB_BOOT1_RESET ((uint8_t)0x00U)
#define | OB_BOOT1_SET ((uint8_t)0x10U)

Define Documentation

#define OB_BOOT1_RESET ((uint8_t)0x00U)

BOOT1 Reset

Definition at line 395 of file stm32f3xx_hal_flash_ex.h.

#define OB_BOOT1_SET ((uint8_t)0x10U)

BOOT1 Set

Definition at line 396 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Option Byte VDDA Analog Monitoring

Defines
Option Byte VDDA Analog Monitoring
Option Byte Constants

Defines

#define | OB_VDDA_ANALOG_ON ((uint8_t)0x20U)
#define | OB_VDDA_ANALOG_OFF ((uint8_t)0x00U)

Define Documentation

#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00U)

Analog monitoring on VDDA Power source OFF

Definition at line 405 of file stm32f3xx_hal_flash_ex.h.

#define OB_VDDA_ANALOG_ON ((uint8_t)0x20U)

Analog monitoring on VDDA Power source ON

Definition at line 404 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Option Byte SRAM Parity Check Enable

Defines
Option Byte SRAM Parity Check Enable
Option Byte Constants

Defines

#define | OB_SRAM_PARITY_SET ((uint8_t)0x00U)
#define | OB_SRAM_PARITY_RESET ((uint8_t)0x40U)

Define Documentation

#define OB_SRAM_PARITY_RESET ((uint8_t)0x40U)

SRAM parity check enable reset

Definition at line 414 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_SRAM_PARITY_SET ((uint8_t)0x00U)

SRAM parity check enable set

Definition at line 413 of file stm32f3xx_hal_flash_ex.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: OB SDADC12 VDD MONITOR

Defines
OB SDADC12 VDD MONITOR
Option Byte Constants

Defines

#define | OB_SDACD_VDD_MONITOR_RESET ((uint8_t)0x00U)
#define | OB_SDACD_VDD_MONITOR_SET ((uint8_t)0x80U)

Define Documentation

#define OB_SDACD_VDD_MONITOR_RESET ((uint8_t)0x00U)

SDADC VDD Monitor reset

Definition at line 424 of file stm32f3xx_hal_flash_ex.h.

#define OB_SDACD_VDD_MONITOR_SET ((uint8_t)0x80U)

SDADC VDD Monitor set

Definition at line 425 of file stm32f3xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Option Byte Data Address

Defines
Option Byte Data Address
Option Byte Constants

Defines

#define | OB_DATA_ADDRESS_DATA0 (0x1FFFF804U)
#define | OB_DATA_ADDRESS_DATA1 (0x1FFFF806U)

Define Documentation

#define OB_DATA_ADDRESS_DATA0 (0x1FFFF804U)

Definition at line 435 of file stm32f3xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetUserData().

#define OB_DATA_ADDRESS_DATA1 (0x1FFFF806U)

Definition at line 436 of file stm32f3xx_hal_flash_ex.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: GPIO Private Defines

Defines
GPIO Private Defines
GPIO

Defines

#define | GPIO_MODE (0x00000003U)
#define | EXTI_MODE (0x10000000U)
#define | GPIO_MODE_IT (0x00010000U)
#define | GPIO_MODE_EVT (0x00020000U)
#define | RISING_EDGE (0x00100000U)
#define | FALLING_EDGE (0x00200000U)
#define | GPIO_OUTPUT_TYPE (0x00000010U)
#define | GPIO_NUMBER (16U)

Define Documentation

#define EXTI_MODE (0x10000000U)

Definition at line 141 of file stm32f3xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define FALLING_EDGE (0x00200000U)

Definition at line 145 of file stm32f3xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE (0x00000003U)

Definition at line 140 of file stm32f3xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_EVT (0x00020000U)

Definition at line 143 of file stm32f3xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_IT (0x00010000U)

Definition at line 142 of file stm32f3xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_NUMBER (16U)

Definition at line 148 of file stm32f3xx_hal_gpio.c.

#define GPIO_OUTPUT_TYPE (0x00000010U)

Definition at line 146 of file stm32f3xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define RISING_EDGE (0x00100000U)

Definition at line 144 of file stm32f3xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: GPIO Private Macros

Defines
GPIO Private Macros
GPIO

Defines

#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(__PIN__)
#define | IS_GPIO_MODE(__MODE__)
#define | IS_GPIO_SPEED(__SPEED__)
#define | IS_GPIO_PULL(__PULL__)

Define Documentation

#define IS_GPIO_MODE ( __MODE__ )
Value:
(((__MODE__) == GPIO_MODE_INPUT)              ||\
                                     ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
                                     ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
                                     ((__MODE__) == GPIO_MODE_AF_PP)              ||\
                                     ((__MODE__) == GPIO_MODE_AF_OD)              ||\
                                     ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
                                     ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
                                     ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
                                     ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
                                     ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
                                     ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
                                     ((__MODE__) == GPIO_MODE_ANALOG))

Definition at line 233 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_PIN ( __PIN__ )
Value:
((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
                                     (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))

Definition at line 230 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_GPIO_DeInit(), HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), and HAL_GPIO_WritePin().

#define IS_GPIO_PIN_ACTION ( ACTION ) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))

Definition at line 228 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_GPIO_WritePin().

#define IS_GPIO_PULL ( __PULL__ )
Value:
(((__PULL__) == GPIO_NOPULL)   ||\
                                     ((__PULL__) == GPIO_PULLUP)   || \
                                     ((__PULL__) == GPIO_PULLDOWN))

Definition at line 250 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_SPEED ( __SPEED__ )
Value:
(((__SPEED__) == GPIO_SPEED_FREQ_LOW)    ||\
                                     ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
                                     ((__SPEED__) == GPIO_SPEED_FREQ_HIGH))

Definition at line 246 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
GPIO Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initialize the GPIOx peripheral registers to their default reset values.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================

Function Documentation

void HAL_GPIO_DeInit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | GPIO_Pin
 | ) |  |

De-initialize the GPIOx peripheral registers to their default reset values.

Parameters:
GPIOx | where x can be (A..F) to select the GPIO peripheral for STM32F30X device or STM32F37X device
GPIO_Pin | specifies the port bit to be written. This parameter can be one of GPIO_PIN_x where x can be (0..15).
Return values:
None

Definition at line 313 of file stm32f3xx_hal_gpio.c.

References assert_param, GPIO_GET_INDEX, and IS_GPIO_PIN.

void HAL_GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_InitTypeDef * | GPIO_Init
 | ) |  |

Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.

Parameters:
GPIOx | where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices
GPIO_Init | pointer to a GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
None

Definition at line 188 of file stm32f3xx_hal_gpio.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, GPIO_InitTypeDef::Alternate, assert_param, EXTI_MODE, FALLING_EDGE, GPIO_GET_INDEX, GPIO_MODE, GPIO_MODE_AF_OD, GPIO_MODE_AF_PP, GPIO_MODE_EVT, GPIO_MODE_IT, GPIO_MODE_OUTPUT_OD, GPIO_MODE_OUTPUT_PP, GPIO_OUTPUT_TYPE, IS_GPIO_AF, IS_GPIO_MODE, IS_GPIO_PIN, IS_GPIO_PULL, IS_GPIO_SPEED, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RISING_EDGE, and GPIO_InitTypeDef::Speed.

Referenced by HAL_RCC_MCOConfig().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IO operation functions

Functions
IO operation functions
GPIO Exported Functions

GPIO Read, Write, Toggle, Lock and EXTI management functions. More...

Functions

GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Read the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Set or clear the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggle the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Lock GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

GPIO Read, Write, Toggle, Lock and EXTI management functions.

 ===============================================================================
                       ##### IO operation functions #####
 ===============================================================================

Function Documentation

void HAL_GPIO_EXTI_Callback ( uint16_t GPIO_Pin )

EXTI line detection callback.

Parameters:
GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
Return values:
None

Definition at line 519 of file stm32f3xx_hal_gpio.c.

Referenced by HAL_GPIO_EXTI_IRQHandler().

void HAL_GPIO_EXTI_IRQHandler ( uint16_t GPIO_Pin )

Handle EXTI interrupt request.

Parameters:
GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
Return values:
None

Definition at line 504 of file stm32f3xx_hal_gpio.c.

References __HAL_GPIO_EXTI_CLEAR_IT, __HAL_GPIO_EXTI_GET_IT, and HAL_GPIO_EXTI_Callback().

HAL_StatusTypeDef HAL_GPIO_LockPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Lock GPIO Pins configuration registers.

Note:
The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The configuration of the locked GPIO pins can no longer be modified until the next reset.
Parameters:
GPIOx | where x can be (A..F) to select the GPIO peripheral for STM32F3 family
GPIO_Pin | specifies the port bits to be locked. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Return values:
None

Definition at line 470 of file stm32f3xx_hal_gpio.c.

References assert_param, and IS_GPIO_PIN.

GPIO_PinState HAL_GPIO_ReadPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Read the specified input port pin.

Parameters:
GPIOx | where x can be (A..F) to select the GPIO peripheral for STM32F3 family
GPIO_Pin | specifies the port bit to read. This parameter can be GPIO_PIN_x where x can be (0..15).
Return values:
The input port pin value.

Definition at line 395 of file stm32f3xx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, GPIO_PIN_SET, and IS_GPIO_PIN.

void HAL_GPIO_TogglePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Toggle the specified GPIO pin.

Parameters:
GPIOx | where x can be (A..F) to select the GPIO peripheral for STM32F3 family
GPIO_Pin | specifies the pin to be toggled.
Return values:
None

Definition at line 451 of file stm32f3xx_hal_gpio.c.

References assert_param, and IS_GPIO_PIN.

void HAL_GPIO_WritePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin,
 |  | GPIO_PinState | PinState
 | ) |  |

Set or clear the selected data port bit.

Note:
This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
Parameters:
GPIOx | where x can be (A..F) to select the GPIO peripheral for STM32F3 family
GPIO_Pin | specifies the port bit to be written. This parameter can be one of GPIO_PIN_x where x can be (0..15).
PinState specifies the value to be written to the selected bit. This parameter can be one of the GPIO_PinState enum values:
  • GPIO_PIN_RESET: to clear the port pin
  • GPIO_PIN_SET: to set the port pin
Return values:
None

Definition at line 429 of file stm32f3xx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, IS_GPIO_PIN, and IS_GPIO_PIN_ACTION.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: GPIO Exported Types

Data Structures | Enumerations
GPIO Exported Types
GPIO

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0U, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Enumeration Type Documentation

enum GPIO_PinState

GPIO Bit SET and Bit RESET enumeration.

Enumerator:
GPIO_PIN_RESET
GPIO_PIN_SET

Definition at line 84 of file stm32f3xx_hal_gpio.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: GPIO_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
GPIO_InitTypeDef Struct Reference
GPIO Exported Types

GPIO Init structure definition. More...

#include <stm32f3xx_hal_gpio.h>

Data Fields

uint32_t | Pin
uint32_t | Mode
uint32_t | Pull
uint32_t | Speed
uint32_t | Alternate

Detailed Description

GPIO Init structure definition.

Definition at line 63 of file stm32f3xx_hal_gpio.h.

Field Documentation

uint32_t GPIO_InitTypeDef::Alternate

Peripheral to be connected to the selected pins This parameter can be a value of GPIOEx Alternate function selection

Definition at line 77 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Mode

Specifies the operating mode for the selected pins. This parameter can be a value of GPIO mode

Definition at line 68 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Pin

Specifies the GPIO pins to be configured. This parameter can be any value of GPIO pins

Definition at line 65 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Pull

Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of GPIO pull

Definition at line 71 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Speed

Specifies the speed for the selected pins. This parameter can be a value of GPIO speed

Definition at line 74 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_gpio.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: GPIO pins

Defines
GPIO pins
GPIO Exported Constants

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
#define | GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */

Define Documentation

#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */

Definition at line 100 of file stm32f3xx_hal_gpio.h.

#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */

Definition at line 101 of file stm32f3xx_hal_gpio.h.

#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */

Definition at line 110 of file stm32f3xx_hal_gpio.h.

#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */

Definition at line 111 of file stm32f3xx_hal_gpio.h.

#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */

Definition at line 112 of file stm32f3xx_hal_gpio.h.

#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */

Definition at line 113 of file stm32f3xx_hal_gpio.h.

#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */

Definition at line 114 of file stm32f3xx_hal_gpio.h.

#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */

Definition at line 115 of file stm32f3xx_hal_gpio.h.

#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */

Definition at line 102 of file stm32f3xx_hal_gpio.h.

#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */

Definition at line 103 of file stm32f3xx_hal_gpio.h.

#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */

Definition at line 104 of file stm32f3xx_hal_gpio.h.

#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */

Definition at line 105 of file stm32f3xx_hal_gpio.h.

#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */

Definition at line 106 of file stm32f3xx_hal_gpio.h.

#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */

Definition at line 107 of file stm32f3xx_hal_gpio.h.

#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */

Definition at line 108 of file stm32f3xx_hal_gpio.h.

#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */

Definition at line 109 of file stm32f3xx_hal_gpio.h.

#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */

Definition at line 116 of file stm32f3xx_hal_gpio.h.

#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */

Definition at line 118 of file stm32f3xx_hal_gpio.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: GPIO mode

Defines
GPIO mode
GPIO Exported Constants

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ. More...

Defines

#define | GPIO_MODE_INPUT (0x00000000U)
#define | GPIO_MODE_OUTPUT_PP (0x00000001U)
#define | GPIO_MODE_OUTPUT_OD (0x00000011U)
#define | GPIO_MODE_AF_PP (0x00000002U)
#define | GPIO_MODE_AF_OD (0x00000012U)
#define | GPIO_MODE_ANALOG (0x00000003U)
#define | GPIO_MODE_IT_RISING (0x10110000U)
#define | GPIO_MODE_IT_FALLING (0x10210000U)
#define | GPIO_MODE_IT_RISING_FALLING (0x10310000U)
#define | GPIO_MODE_EVT_RISING (0x10120000U)
#define | GPIO_MODE_EVT_FALLING (0x10220000U)
#define | GPIO_MODE_EVT_RISING_FALLING (0x10320000U)

Detailed Description

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ.

  • X : GPIO mode or EXTI Mode
  • y : External IT or Event trigger detection
  • z : IO configuration on External IT or Event
  • Y : Output type (Push Pull or Open Drain)
  • Z : IO Direction mode (Input, Output, Alternate or Analog)

Define Documentation

#define GPIO_MODE_AF_OD (0x00000012U)

Alternate Function Open Drain Mode

Definition at line 137 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_AF_PP (0x00000002U)

Alternate Function Push Pull Mode

Definition at line 136 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

#define GPIO_MODE_ANALOG (0x00000003U)

Analog Mode

Definition at line 138 of file stm32f3xx_hal_gpio.h.

#define GPIO_MODE_EVT_FALLING (0x10220000U)

External Event Mode with Falling edge trigger detection

Definition at line 143 of file stm32f3xx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING (0x10120000U)

External Event Mode with Rising edge trigger detection

Definition at line 142 of file stm32f3xx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U)

External Event Mode with Rising/Falling edge trigger detection

Definition at line 144 of file stm32f3xx_hal_gpio.h.

#define GPIO_MODE_INPUT (0x00000000U)

Input Floating Mode

Definition at line 133 of file stm32f3xx_hal_gpio.h.

#define GPIO_MODE_IT_FALLING (0x10210000U)

External Interrupt Mode with Falling edge trigger detection

Definition at line 140 of file stm32f3xx_hal_gpio.h.

#define GPIO_MODE_IT_RISING (0x10110000U)

External Interrupt Mode with Rising edge trigger detection

Definition at line 139 of file stm32f3xx_hal_gpio.h.

#define GPIO_MODE_IT_RISING_FALLING (0x10310000U)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 141 of file stm32f3xx_hal_gpio.h.

#define GPIO_MODE_OUTPUT_OD (0x00000011U)

Output Open Drain Mode

Definition at line 135 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_OUTPUT_PP (0x00000001U)

Output Push Pull Mode

Definition at line 134 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: GPIO speed

Defines
GPIO speed
GPIO Exported Constants

GPIO Output Maximum frequency. More...

Defines

#define | GPIO_SPEED_FREQ_LOW (0x00000000U)
#define | GPIO_SPEED_FREQ_MEDIUM (0x00000001U)
#define | GPIO_SPEED_FREQ_HIGH (0x00000003U)

Detailed Description

GPIO Output Maximum frequency.

Define Documentation

#define GPIO_SPEED_FREQ_HIGH (0x00000003U)

range 10 MHz to 50 MHz, please refer to the product datasheet

Definition at line 155 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_SPEED_FREQ_LOW (0x00000000U)

range up to 2 MHz, please refer to the product datasheet

Definition at line 153 of file stm32f3xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U)

range 4 MHz to 10 MHz, please refer to the product datasheet

Definition at line 154 of file stm32f3xx_hal_gpio.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: GPIO pull

Defines
GPIO pull
GPIO Exported Constants

GPIO Pull-Up or Pull-Down Activation. More...

Defines

#define | GPIO_NOPULL (0x00000000U)
#define | GPIO_PULLUP (0x00000001U)
#define | GPIO_PULLDOWN (0x00000002U)

Detailed Description

GPIO Pull-Up or Pull-Down Activation.

Define Documentation

#define GPIO_NOPULL (0x00000000U)

No Pull-up or Pull-down activation

Definition at line 164 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_PULLDOWN (0x00000002U)

Pull-down activation

Definition at line 166 of file stm32f3xx_hal_gpio.h.

#define GPIO_PULLUP (0x00000001U)

Pull-up activation

Definition at line 165 of file stm32f3xx_hal_gpio.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: GPIO Exported Macros

Defines
GPIO Exported Macros
GPIO

Defines

#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
Check whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
Clear the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
Check whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
Clear the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
Generate a Software interrupt on selected EXTI line.

Define Documentation

#define __HAL_GPIO_EXTI_CLEAR_FLAG ( __EXTI_LINE__ ) (EXTI->PR = (__EXTI_LINE__))

Clear the EXTI's line pending flags.

Parameters:
__EXTI_LINE__ specifies the EXTI lines flags to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 194 of file stm32f3xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_CLEAR_IT ( __EXTI_LINE__ ) (EXTI->PR = (__EXTI_LINE__))

Clear the EXTI's line pending bits.

Parameters:
__EXTI_LINE__ specifies the EXTI lines to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 210 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

#define __HAL_GPIO_EXTI_GENERATE_SWIT ( __EXTI_LINE__ ) (EXTI->SWIER |= (__EXTI_LINE__))

Generate a Software interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__ specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
None

Definition at line 218 of file stm32f3xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_FLAG ( __EXTI_LINE__ ) (EXTI->PR & (__EXTI_LINE__))

Check whether the specified EXTI line flag is set or not.

Parameters:
__EXTI_LINE__ specifies the EXTI line flag to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 186 of file stm32f3xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_IT ( __EXTI_LINE__ ) (EXTI->PR & (__EXTI_LINE__))

Check whether the specified EXTI line is asserted or not.

Parameters:
__EXTI_LINE__ specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 202 of file stm32f3xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: GPIOEx Alternate function selection

Defines
GPIOEx Alternate function selection
GPIOEx Exported Constants

Defines

#define | GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
AF 0 selection.
#define | GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define | GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
#define | GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define | GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
#define | GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
AF 1 selection.
#define | GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
#define | GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
#define | GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
#define | GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
#define | GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
AF 2 selection.
#define | GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
#define | GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
#define | GPIO_AF2_TIM13 ((uint8_t)0x02U) /* TIM13 Alternate Function mapping */
#define | GPIO_AF2_TIM14 ((uint8_t)0x02U) /* TIM14 Alternate Function mapping */
#define | GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
#define | GPIO_AF2_TIM19 ((uint8_t)0x02U) /* TIM19 Alternate Function mapping */
#define | GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
AF 3 selection.
#define | GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
AF 4 selection.
#define | GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
#define | GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
AF 5 selection.
#define | GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
#define | GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
#define | GPIO_AF6_SPI1 ((uint8_t)0x06U) /* SPI1/I2S1 Alternate Function mapping */
AF 6 selection.
#define | GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
#define | GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
#define | GPIO_AF6_CEC ((uint8_t)0x06U) /* CEC Alternate Function mapping */
#define | GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
AF 7 selection.
#define | GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
#define | GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
#define | GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
#define | GPIO_AF7_CEC ((uint8_t)0x07U) /* CEC Alternate Function mapping */
#define | GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
AF 8 selection.
#define | GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
#define | GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
AF 9 selection.
#define | GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */
#define | GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
#define | GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
#define | GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
#define | GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
AF 10 selection.
#define | GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
#define | GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
#define | GPIO_AF10_TIM12 ((uint8_t)0xAU) /* TIM12 Alternate Function mapping */
#define | GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
#define | GPIO_AF11_TIM19 ((uint8_t)0x0BU) /* TIM19 Alternate Function mapping */
AF 11 selection.
#define | GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */
AF 14 selection.
#define | GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
AF 15 selection.
#define | IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0BU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))

Define Documentation

#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */

Definition at line 855 of file stm32f3xx_hal_gpio_ex.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */

AF 0 selection.

Definition at line 854 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */

Definition at line 857 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */

Definition at line 856 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */

Definition at line 858 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF10_TIM12 ((uint8_t)0xAU) /* TIM12 Alternate Function mapping */

Definition at line 931 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */

Definition at line 932 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */

AF 10 selection.

Definition at line 928 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */

Definition at line 929 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */

Definition at line 930 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF11_TIM19 ((uint8_t)0x0BU) /* TIM19 Alternate Function mapping */

AF 11 selection.

Definition at line 936 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */

AF 14 selection.

Definition at line 942 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */

AF 15 selection.

Definition at line 947 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */

Definition at line 867 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */

Definition at line 864 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */

Definition at line 865 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */

Definition at line 866 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */

AF 1 selection.

Definition at line 863 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM13 ((uint8_t)0x02U) /* TIM13 Alternate Function mapping */

Definition at line 874 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM14 ((uint8_t)0x02U) /* TIM14 Alternate Function mapping */

Definition at line 875 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */

Definition at line 876 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM19 ((uint8_t)0x02U) /* TIM19 Alternate Function mapping */

Definition at line 877 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */

AF 2 selection.

Definition at line 871 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */

Definition at line 872 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */

Definition at line 873 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */

AF 3 selection.

Definition at line 882 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */

AF 4 selection.

Definition at line 886 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */

Definition at line 887 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */

Definition at line 894 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */

AF 5 selection.

Definition at line 892 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */

Definition at line 893 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF6_CEC ((uint8_t)0x06U) /* CEC Alternate Function mapping */

Definition at line 901 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */

Definition at line 900 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF6_SPI1 ((uint8_t)0x06U) /* SPI1/I2S1 Alternate Function mapping */

AF 6 selection.

Definition at line 898 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */

Definition at line 899 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */

Definition at line 908 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF7_CEC ((uint8_t)0x07U) /* CEC Alternate Function mapping */

Definition at line 909 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */

AF 7 selection.

Definition at line 905 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */

Definition at line 906 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */

Definition at line 907 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */

AF 8 selection.

Definition at line 914 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */

Definition at line 915 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */

AF 9 selection.

Definition at line 920 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */

Definition at line 921 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */

Definition at line 922 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */

Definition at line 923 of file stm32f3xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */

Definition at line 924 of file stm32f3xx_hal_gpio_ex.h.

#define IS_GPIO_AF ( AF ) (((AF) <= (uint8_t)0x0BU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))

Definition at line 949 of file stm32f3xx_hal_gpio_ex.h.

Referenced by HAL_GPIO_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: GPIOEx_Get Port Index

Defines
GPIOEx_Get Port Index
GPIOEx Exported Macros

Defines

#define GPIO_GET_INDEX(__GPIOx__)

Define Documentation

#define GPIO_GET_INDEX ( __GPIOx__ )
Value:
(((__GPIOx__) == (GPIOA))? 0U :\
                                      ((__GPIOx__) == (GPIOB))? 1U :\
                                      ((__GPIOx__) == (GPIOC))? 2U :\
                                      ((__GPIOx__) == (GPIOD))? 3U :\
                                      ((__GPIOx__) == (GPIOE))? 4U : 5U)

Definition at line 1497 of file stm32f3xx_hal_gpio_ex.h.

Referenced by HAL_GPIO_DeInit(), and HAL_GPIO_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Private Define

Defines
I2C Private Define
I2C

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFU)
#define | I2C_TIMEOUT_ADDR (10000U)
#define | I2C_TIMEOUT_BUSY (25U)
#define | I2C_TIMEOUT_DIR (25U)
#define | I2C_TIMEOUT_RXNE (25U)
#define | I2C_TIMEOUT_STOPF (25U)
#define | I2C_TIMEOUT_TC (25U)
#define | I2C_TIMEOUT_TCR (25U)
#define | I2C_TIMEOUT_TXIS (25U)
#define | I2C_TIMEOUT_FLAG (25U)
#define | MAX_NBYTE_SIZE 255U
#define | SlaveAddr_SHIFT 7U
#define | SlaveAddr_MSK 0x06U
#define | I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY))))
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))
#define | I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))
#define | I2C_XFER_TX_IT (0x00000001U)
#define | I2C_XFER_RX_IT (0x00000002U)
#define | I2C_XFER_LISTEN_IT (0x00000004U)
#define | I2C_XFER_ERROR_IT (0x00000011U)
#define | I2C_XFER_CPLT_IT (0x00000012U)
#define | I2C_XFER_RELOAD_IT (0x00000012U)
#define | I2C_NO_OPTION_FRAME (0xFFFF0000U)

Define Documentation

#define I2C_NO_OPTION_FRAME (0xFFFF0000U)

Definition at line 297 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))

Master Busy RX, combinaison of State LSB and Mode enum

Definition at line 280 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Sequential_Receive_IT(), and I2C_ITMasterSequentialCplt().

#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))

Master Busy TX, combinaison of State LSB and Mode enum

Definition at line 279 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Sequential_Transmit_IT(), and I2C_ITMasterSequentialCplt().

#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))

Memory Busy RX, combinaison of State LSB and Mode enum

Definition at line 284 of file stm32f3xx_hal_i2c.c.

#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))

Memory Busy TX, combinaison of State LSB and Mode enum

Definition at line 283 of file stm32f3xx_hal_i2c.c.

#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY))))

Mask State define, keep only RX and TX bits

Definition at line 277 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT().

#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))

Default Value

Definition at line 278 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), and I2C_ITSlaveCplt().

#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))

Slave Busy RX, combinaison of State LSB and Mode enum

Definition at line 282 of file stm32f3xx_hal_i2c.c.

Referenced by I2C_ITSlaveSequentialCplt().

#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))

Slave Busy TX, combinaison of State LSB and Mode enum

Definition at line 281 of file stm32f3xx_hal_i2c.c.

Referenced by I2C_ITSlaveSequentialCplt().

#define I2C_TIMEOUT_ADDR (10000U)

10 s

Definition at line 262 of file stm32f3xx_hal_i2c.c.

#define I2C_TIMEOUT_BUSY (25U)

25 ms

Definition at line 263 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), and HAL_I2C_Mem_Write().

#define I2C_TIMEOUT_DIR (25U)

25 ms

Definition at line 264 of file stm32f3xx_hal_i2c.c.

#define I2C_TIMEOUT_FLAG (25U)

25 ms

Definition at line 270 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

#define I2C_TIMEOUT_RXNE (25U)

25 ms

Definition at line 265 of file stm32f3xx_hal_i2c.c.

#define I2C_TIMEOUT_STOPF (25U)

25 ms

Definition at line 266 of file stm32f3xx_hal_i2c.c.

#define I2C_TIMEOUT_TC (25U)

25 ms

Definition at line 267 of file stm32f3xx_hal_i2c.c.

#define I2C_TIMEOUT_TCR (25U)

25 ms

Definition at line 268 of file stm32f3xx_hal_i2c.c.

#define I2C_TIMEOUT_TXIS (25U)

25 ms

Definition at line 269 of file stm32f3xx_hal_i2c.c.

#define I2C_XFER_CPLT_IT (0x00000012U)

Definition at line 293 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), I2C_Disable_IRQ(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), and I2C_Master_ISR_DMA().

#define I2C_XFER_ERROR_IT (0x00000011U)

Definition at line 292 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), I2C_Disable_IRQ(), and I2C_Enable_IRQ().

#define I2C_XFER_LISTEN_IT (0x00000004U)

Definition at line 290 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), and I2C_ITSlaveCplt().

#define I2C_XFER_RELOAD_IT (0x00000012U)

Definition at line 294 of file stm32f3xx_hal_i2c.c.

Referenced by I2C_Disable_IRQ(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), and I2C_Enable_IRQ().

#define I2C_XFER_RX_IT (0x00000002U)

Definition at line 289 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

#define I2C_XFER_TX_IT (0x00000001U)

Definition at line 288 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

#define MAX_NBYTE_SIZE 255U

Definition at line 272 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define SlaveAddr_MSK 0x06U

Definition at line 274 of file stm32f3xx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

#define SlaveAddr_SHIFT 7U

Definition at line 273 of file stm32f3xx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

#define TIMING_CLEAR_MASK (0xF0FFFFFFU)

I2C TIMING clear register Mask

Definition at line 261 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Private Functions

Functions
I2C Private Functions
I2C

Functions

static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static void | I2C_DMAAbort (DMA_HandleTypeDef *hdma)
DMA I2C communication abort callback (To be called at end of DMA Abort procedure).
static void | I2C_ITAddrCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Address complete process callback.
static void | I2C_ITMasterSequentialCplt (I2C_HandleTypeDef *hi2c)
I2C Master sequential complete process.
static void | I2C_ITSlaveSequentialCplt (I2C_HandleTypeDef *hi2c)
I2C Slave sequential complete process.
static void | I2C_ITMasterCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Master complete process.
static void | I2C_ITSlaveCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Slave complete process.
static void | I2C_ITListenCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Listen complete process.
static void | I2C_ITError (I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
I2C interrupts error process.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_Master_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Slave_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Master_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
static HAL_StatusTypeDef | I2C_Slave_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnTXISFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsAcknowledgeFailed (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles Acknowledge failed detection during an I2C Communication.
static HAL_StatusTypeDef | I2C_Enable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static HAL_StatusTypeDef | I2C_Disable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static void | I2C_Flush_TXDR (I2C_HandleTypeDef *hi2c)
I2C Tx data register flush process.
static void | I2C_TransferConfig (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Function Documentation

static HAL_StatusTypeDef I2C_Disable_IRQ | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the disabling of Interrupts.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
InterruptRequest | Value of I2C Interrupt configuration definition.
Return values:
HAL status

Definition at line 4795 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_STATE_LISTEN, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_XFER_CPLT_IT, I2C_XFER_ERROR_IT, I2C_XFER_LISTEN_IT, I2C_XFER_RELOAD_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

static void I2C_DMAAbort ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication abort callback (To be called at end of DMA Abort procedure).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 4438 of file stm32f3xx_hal_i2c.c.

References HAL_I2C_AbortCpltCallback(), HAL_I2C_ErrorCallback(), HAL_I2C_STATE_ABORT, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by I2C_ITError().

static void I2C_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication error callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4421 of file stm32f3xx_hal_i2c.c.

References HAL_I2C_ERROR_DMA, I2C_ITError(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), and HAL_I2C_Slave_Transmit_DMA().

static void I2C_DMAMasterReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4364 of file stm32f3xx_hal_i2c.c.

References HAL_DMA_Start_IT(), __I2C_HandleTypeDef::hdmarx, I2C_Enable_IRQ(), I2C_XFER_CPLT_IT, I2C_XFER_RELOAD_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), and HAL_I2C_Mem_Read_DMA().

static void I2C_DMAMasterTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4307 of file stm32f3xx_hal_i2c.c.

References HAL_DMA_Start_IT(), __I2C_HandleTypeDef::hdmatx, I2C_Enable_IRQ(), I2C_XFER_CPLT_IT, I2C_XFER_RELOAD_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Transmit_DMA(), and HAL_I2C_Mem_Write_DMA().

static void I2C_DMASlaveReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4406 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_Slave_Receive_DMA().

static void I2C_DMASlaveTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4349 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_Slave_Transmit_DMA().

static HAL_StatusTypeDef I2C_Enable_IRQ | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the enabling of Interrupts.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
InterruptRequest | Value of I2C Interrupt configuration definition.
Return values:
HAL status

Definition at line 4722 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_Master_ISR_DMA(), I2C_Slave_ISR_DMA(), I2C_XFER_CPLT_IT, I2C_XFER_ERROR_IT, I2C_XFER_LISTEN_IT, I2C_XFER_RELOAD_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, and __I2C_HandleTypeDef::XferISR.

Referenced by HAL_I2C_EnableListen_IT(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), and I2C_Master_ISR_DMA().

static void I2C_Flush_TXDR ( I2C_HandleTypeDef * hi2c ) [static]

I2C Tx data register flush process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 4286 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_FLAG_TXE, I2C_FLAG_TXIS, and __I2C_HandleTypeDef::Instance.

Referenced by I2C_IsAcknowledgeFailed(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

static HAL_StatusTypeDef I2C_IsAcknowledgeFailed | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles Acknowledge failed detection during an I2C Communication.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 4626 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_RESET_CR2, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

static void I2C_ITAddrCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Address complete process callback.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 3770 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::AddrEventCount, HAL_I2C_AddrCallback(), HAL_I2C_STATE_LISTEN, I2C_ADDRESSINGMODE_10BIT, I2C_Disable_IRQ(), I2C_FLAG_ADDR, I2C_GET_ADDR_MATCH, I2C_GET_DIR, I2C_GET_OWN_ADDRESS1, I2C_GET_OWN_ADDRESS2, I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Init, SlaveAddr_MSK, SlaveAddr_SHIFT, and __I2C_HandleTypeDef::State.

Referenced by I2C_Slave_ISR_IT().

static void I2C_ITError | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ErrorCode
 | ) |  | [static]

I2C interrupts error process.

Parameters:
hi2c | I2C handle.
ErrorCode | Error code to handle.
Return values:
None

Definition at line 4184 of file stm32f3xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_I2C_AbortCpltCallback(), HAL_I2C_ErrorCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_STATE_NONE, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_DMAError(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

static void I2C_ITListenCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Listen complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 4140 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by I2C_ITSlaveCplt(), and I2C_Slave_ISR_IT().

static void I2C_ITMasterCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Master complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 3942 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_ITError(), I2C_NO_OPTION_FRAME, I2C_RESET_CR2, I2C_STATE_NONE, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferOptions.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

static void I2C_ITMasterSequentialCplt ( I2C_HandleTypeDef * hi2c ) [static]

I2C Master sequential complete process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 3853 of file stm32f3xx_hal_i2c.c.

References HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_STATE_MASTER_BUSY_RX, I2C_STATE_MASTER_BUSY_TX, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

Referenced by I2C_Master_ISR_IT().

static void I2C_ITSlaveCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Slave complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 4034 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_FLAG_ADDR, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_GET_DMA_REMAIN_DATA, I2C_ITError(), I2C_ITListenCplt(), I2C_NO_OPTION_FRAME, I2C_RESET_CR2, I2C_STATE_NONE, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITSlaveSequentialCplt ( I2C_HandleTypeDef * hi2c ) [static]

I2C Slave sequential complete process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 3898 of file stm32f3xx_hal_i2c.c.

References HAL_I2C_MODE_NONE, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_Disable_IRQ(), I2C_STATE_SLAVE_BUSY_RX, I2C_STATE_SLAVE_BUSY_TX, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, and __I2C_HandleTypeDef::State.

Referenced by I2C_Slave_ISR_IT().

static HAL_StatusTypeDef I2C_Master_ISR_DMA | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 3498 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_DISABLE_IT, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, HAL_I2C_STATE_BUSY_RX, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_Flush_TXDR(), I2C_IT_NACKI, I2C_IT_STOPI, I2C_IT_TCI, I2C_ITError(), I2C_ITMasterCplt(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_CPLT_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), and I2C_Enable_IRQ().

static HAL_StatusTypeDef I2C_Master_ISR_IT | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 3264 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, I2C_AUTOEND_MODE, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_GET_STOP_MODE, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_ITError(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_IT(), and HAL_I2C_Mem_Write_IT().

static HAL_StatusTypeDef I2C_RequestMemoryRead | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Master sends target device address followed by internal memory address for read request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 3709 of file stm32f3xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_FLAG_TC, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_SOFTEND_MODE, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), and HAL_I2C_Mem_Read_IT().

static HAL_StatusTypeDef I2C_RequestMemoryWrite | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Master sends target device address followed by internal memory address for write request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 3642 of file stm32f3xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_FLAG_TCR, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

static HAL_StatusTypeDef I2C_Slave_ISR_DMA | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 3587 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_GET_DMA_REMAIN_DATA, I2C_IT_ADDRI, I2C_IT_NACKI, I2C_IT_STOPI, and I2C_ITSlaveCplt().

Referenced by HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), and I2C_Enable_IRQ().

static HAL_StatusTypeDef I2C_Slave_ISR_IT | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 3385 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_IT_ADDRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TXI, I2C_ITAddrCplt(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSequentialCplt(), I2C_LAST_FRAME, I2C_NEXT_FRAME, I2C_NO_OPTION_FRAME, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_EnableListen_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), and I2C_ITError().

static void I2C_TransferConfig | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t | Size,
 |  | uint32_t | Mode,
 |  | uint32_t | Request
 | ) |  | [static]

Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Parameters:
hi2c | I2C handle.
DevAddress | Specifies the slave address to be programmed.
Size | Specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
Mode New state of the I2C START condition generation. This parameter can be one of the following values:
  • I2C_RELOAD_MODE Enable Reload mode .
  • I2C_AUTOEND_MODE Enable Automatic end mode.
  • I2C_SOFTEND_MODE Enable Software end mode.
Request New state of the I2C START condition generation. This parameter can be one of the following values:
  • I2C_NO_STARTSTOP Don't Generate stop and start condition.
  • I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
  • I2C_GENERATE_START_READ Generate Restart for read request.
  • I2C_GENERATE_START_WRITE Generate Restart for write request.
Return values:
None

Definition at line 4692 of file stm32f3xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::Instance, IS_TRANSFER_MODE, and IS_TRANSFER_REQUEST.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Flag | Specifies the I2C flag to check.
Status | The new Flag status (SET or RESET).
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 4474 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, HAL_GetTick(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of RXNE flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 4574 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_IsAcknowledgeFailed(), I2C_RESET_CR2, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Receive(), and HAL_I2C_Slave_Receive().

static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of STOP flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 4540 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_STOPF, I2C_IsAcknowledgeFailed(), __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of TXIS flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 4503 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_TXIS, I2C_IsAcknowledgeFailed(), __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Transmit(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2C Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          deinitialize the I2Cx peripheral:

      (+) User must Implement HAL_I2C_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_I2C_Init() to configure the selected device with
          the selected configuration:
        (++) Clock Timing
        (++) Own Address 1
        (++) Addressing mode (Master, Slave)
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) Own Address 2 Mask
        (++) General call mode
        (++) Nostretch mode

      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
          of the selected I2Cx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_I2C_DeInit ( I2C_HandleTypeDef * hi2c )

DeInitialize the I2C peripheral.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 491 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_DISABLE, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MspDeInit(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_RESET, I2C_STATE_NONE, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Init ( I2C_HandleTypeDef * hi2c )

Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 404 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, I2C_InitTypeDef::AddressingMode, assert_param, I2C_InitTypeDef::DualAddressMode, __I2C_HandleTypeDef::ErrorCode, I2C_InitTypeDef::GeneralCallMode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MspInit(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, I2C_ADDRESSINGMODE_10BIT, I2C_ADDRESSINGMODE_7BIT, I2C_DUALADDRESS_ENABLE, I2C_STATE_NONE, __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, IS_I2C_ADDRESSING_MODE, IS_I2C_DUAL_ADDRESS, IS_I2C_GENERAL_CALL, IS_I2C_NO_STRETCH, IS_I2C_OWN_ADDRESS1, IS_I2C_OWN_ADDRESS2, IS_I2C_OWN_ADDRESS2_MASK, __I2C_HandleTypeDef::Lock, __I2C_HandleTypeDef::Mode, I2C_InitTypeDef::NoStretchMode, I2C_InitTypeDef::OwnAddress1, I2C_InitTypeDef::OwnAddress2, I2C_InitTypeDef::OwnAddress2Masks, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, I2C_InitTypeDef::Timing, and TIMING_CLEAR_MASK.

void HAL_I2C_MspDeInit ( I2C_HandleTypeDef * hi2c )

DeInitialize the I2C MSP.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 543 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_DeInit().

void HAL_I2C_MspInit ( I2C_HandleTypeDef * hi2c )

Initialize the I2C MSP.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 527 of file stm32f3xx_hal_i2c.c.

Referenced by HAL_I2C_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
I2C Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2C data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2C_Master_Transmit()
        (++) HAL_I2C_Master_Receive()
        (++) HAL_I2C_Slave_Transmit()
        (++) HAL_I2C_Slave_Receive()
        (++) HAL_I2C_Mem_Write()
        (++) HAL_I2C_Mem_Read()
        (++) HAL_I2C_IsDeviceReady()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2C_Master_Transmit_IT()
        (++) HAL_I2C_Master_Receive_IT()
        (++) HAL_I2C_Slave_Transmit_IT()
        (++) HAL_I2C_Slave_Receive_IT()
        (++) HAL_I2C_Mem_Write_IT()
        (++) HAL_I2C_Mem_Read_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2C_Master_Transmit_DMA()
        (++) HAL_I2C_Master_Receive_DMA()
        (++) HAL_I2C_Slave_Transmit_DMA()
        (++) HAL_I2C_Slave_Receive_DMA()
        (++) HAL_I2C_Mem_Write_DMA()
        (++) HAL_I2C_Mem_Read_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2C_MemTxCpltCallback()
        (++) HAL_I2C_MemRxCpltCallback()
        (++) HAL_I2C_MasterTxCpltCallback()
        (++) HAL_I2C_MasterRxCpltCallback()
        (++) HAL_I2C_SlaveTxCpltCallback()
        (++) HAL_I2C_SlaveRxCpltCallback()
        (++) HAL_I2C_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_I2C_DisableListen_IT ( I2C_HandleTypeDef * hi2c )

Disable the Address listen mode with Interrupt.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C
Return values:
HAL status

Definition at line 2887 of file stm32f3xx_hal_i2c.c.

References HAL_I2C_MODE_NONE, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_STATE_MSK, I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_EnableListen_IT ( I2C_HandleTypeDef * hi2c )

Enable the Address listen mode with Interrupt.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 2863 of file stm32f3xx_hal_i2c.c.

References HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_IsDeviceReady | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Checks if target device is ready for communication.

Note:
This function is used with Memory devices
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2455 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, HAL_I2C_STATE_TIMEOUT, I2C_FLAG_AF, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_GENERATE_START, I2C_WaitOnFlagUntilTimeout(), __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Master_Abort_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master I2C IT or DMA process communication with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
Return values:
HAL status

Definition at line 2920 of file stm32f3xx_hal_i2c.c.

References HAL_I2C_MODE_MASTER, HAL_I2C_STATE_ABORT, I2C_AUTOEND_MODE, I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_GENERATE_STOP, I2C_TransferConfig(), I2C_XFER_CPLT_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Master_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives in master mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 751 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_READ, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1490 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1215 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_RX_IT, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 2648 of file stm32f3xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_RX, I2C_TransferConfig(), I2C_XFER_RX_IT, IS_I2C_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 2575 of file stm32f3xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_GENERATE_START_WRITE, I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_TX, I2C_TransferConfig(), I2C_XFER_TX_IT, IS_I2C_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in master mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 627 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_WRITE, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1382 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1146 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_TX_IT, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Read an amount of data in blocking mode from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1884 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_READ, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Reads an amount of data in non-blocking mode with DMA from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be read
Return values:
HAL status

Definition at line 2341 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_DMA(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_ERROR_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Read an amount of data in non-blocking mode with Interrupt from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2127 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_RX_IT, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Write an amount of data in blocking mode to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1731 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in non-blocking mode with DMA to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2225 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_Master_ISR_DMA(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_ERROR_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in non-blocking mode with Interrupt to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2028 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_TX_IT, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive in slave mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1014 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_ADDR, I2C_FLAG_BUSY, I2C_FLAG_DIR, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1661 of file stm32f3xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_DMAError(), I2C_DMASlaveReceiveCplt(), I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1331 of file stm32f3xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 2793 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_DIRECTION_TRANSMIT, I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 2719 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_DIRECTION_RECEIVE, I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in slave mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 874 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_ADDRESSINGMODE_10BIT, I2C_FLAG_ADDR, I2C_FLAG_BUSY, I2C_FLAG_DIR, I2C_FLAG_STOPF, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1595 of file stm32f3xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_DMAError(), I2C_DMASlaveTransmitCplt(), I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1282 of file stm32f3xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
I2C Exported Functions

Functions

void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.

Function Documentation

void HAL_I2C_AbortCpltCallback ( I2C_HandleTypeDef * hi2c )

I2C abort callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3181 of file stm32f3xx_hal_i2c.c.

Referenced by I2C_DMAAbort(), and I2C_ITError().

void HAL_I2C_AddrCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t | TransferDirection,
 |  | uint16_t | AddrMatchCode
 | ) |  |

Slave Address Match callback.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
TransferDirection | Master request Transfer Direction (Write/Read), value of I2C Transfer Direction Master Point of View
AddrMatchCode | Address Match Code
Return values:
None

Definition at line 3099 of file stm32f3xx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

void HAL_I2C_ER_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C error interrupt request.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 2989 of file stm32f3xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_ARLO, HAL_I2C_ERROR_BERR, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_OVR, I2C_FLAG_ARLO, I2C_FLAG_BERR, I2C_FLAG_OVR, I2C_IT_ERRI, I2C_ITError(), and __I2C_HandleTypeDef::Instance.

void HAL_I2C_ErrorCallback ( I2C_HandleTypeDef * hi2c )

I2C error callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3165 of file stm32f3xx_hal_i2c.c.

Referenced by I2C_DMAAbort(), and I2C_ITError().

void HAL_I2C_EV_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C event interrupt request.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 2970 of file stm32f3xx_hal_i2c.c.

References __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::XferISR.

void HAL_I2C_ListenCpltCallback ( I2C_HandleTypeDef * hi2c )

Listen Complete callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3117 of file stm32f3xx_hal_i2c.c.

Referenced by I2C_ITListenCplt(), and I2C_ITSlaveCplt().

void HAL_I2C_MasterRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3050 of file stm32f3xx_hal_i2c.c.

Referenced by I2C_ITMasterCplt(), and I2C_ITMasterSequentialCplt().

void HAL_I2C_MasterTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3034 of file stm32f3xx_hal_i2c.c.

Referenced by I2C_ITMasterCplt(), and I2C_ITMasterSequentialCplt().

void HAL_I2C_MemRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3149 of file stm32f3xx_hal_i2c.c.

Referenced by I2C_ITMasterCplt().

void HAL_I2C_MemTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3133 of file stm32f3xx_hal_i2c.c.

Referenced by I2C_ITMasterCplt().

void HAL_I2C_SlaveRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3081 of file stm32f3xx_hal_i2c.c.

Referenced by I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

void HAL_I2C_SlaveTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3065 of file stm32f3xx_hal_i2c.c.

Referenced by I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral State, Mode and Error functions

Functions
Peripheral State, Mode and Error functions
I2C Exported Functions

Peripheral State, Mode and Error functions. More...

Functions

HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Peripheral State, Mode and Error functions.

 ===============================================================================
            ##### Peripheral State, Mode and Error functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_I2C_GetError ( I2C_HandleTypeDef * hi2c )

Return the I2C error code.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
I2C Error Code

Definition at line 3239 of file stm32f3xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode.

HAL_I2C_ModeTypeDef HAL_I2C_GetMode ( I2C_HandleTypeDef * hi2c )

Returns the I2C Master, Slave, Memory or no mode.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL mode

Definition at line 3228 of file stm32f3xx_hal_i2c.c.

References __I2C_HandleTypeDef::Mode.

HAL_I2C_StateTypeDef HAL_I2C_GetState ( I2C_HandleTypeDef * hi2c )

Return the I2C handle state.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL state

Definition at line 3216 of file stm32f3xx_hal_i2c.c.

References __I2C_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2C_InitTypeDef Struct Reference
I2C Configuration Structure definition

#include <stm32f3xx_hal_i2c.h>

Data Fields

uint32_t | Timing
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | OwnAddress2Masks
uint32_t | GeneralCallMode
uint32_t | NoStretchMode

Detailed Description

Definition at line 64 of file stm32f3xx_hal_i2c.h.

Field Documentation

uint32_t I2C_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode is selected. This parameter can be a value of I2C Addressing Mode

Definition at line 73 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

uint32_t I2C_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of I2C Dual Addressing Mode

Definition at line 76 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of I2C General Call Addressing Mode

Definition at line 85 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of I2C No-Stretch Mode

Definition at line 88 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 70 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 79 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress2Masks

Specifies the acknowledge mask address second device own address if dual addressing mode is selected This parameter can be a value of I2C Own Address2 Masks

Definition at line 82 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::Timing

Specifies the I2C_TIMINGR_register value. This parameter calculated by referring to I2C initialization section in Reference manual

Definition at line 66 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_i2c.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HAL state structure definition

Enumerations
HAL state structure definition
I2C Exported Types

HAL State structure definition. More...

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_ABORT = 0x60U, HAL_I2C_STATE_TIMEOUT = 0xA0U, HAL_I2C_STATE_ERROR = 0xE0U
}

Detailed Description

HAL State structure definition.

Note:
HAL I2C State value coding follow below described bitmap :
b7-b6 Error information
00 : No Error
01 : Abort (Abort user request on going)
10 : Timeout
11 : Error
b5 IP initilisation status
0 : Reset (IP not initialized)
1 : Init done (IP initialized and ready to use. HAL I2C Init function called)
b4 (not used)
x : Should be set to 0
b3
0 : Ready or Busy (No Listen mode ongoing)
1 : Listen (IP in Address Listen Mode)
b2 Intrinsic process state
0 : Ready
1 : Busy (IP busy with some configuration or internal operations)
b1 Rx state
0 : Ready (no Rx operation ongoing)
1 : Busy (Rx operation ongoing)
b0 Tx state
0 : Ready (no Tx operation ongoing)
1 : Busy (Tx operation ongoing)

Enumeration Type Documentation

enum HAL_I2C_StateTypeDef
Enumerator:
HAL_I2C_STATE_RESET

Peripheral is not yet Initialized

HAL_I2C_STATE_READY

Peripheral Initialized and ready for use

HAL_I2C_STATE_BUSY

An internal process is ongoing

HAL_I2C_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX

Data Reception process is ongoing

HAL_I2C_STATE_LISTEN

Address Listen Mode is ongoing

HAL_I2C_STATE_BUSY_TX_LISTEN

Address Listen Mode and Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX_LISTEN

Address Listen Mode and Data Reception process is ongoing

HAL_I2C_STATE_ABORT

Abort user request ongoing

HAL_I2C_STATE_TIMEOUT

Timeout state

HAL_I2C_STATE_ERROR

Error

Definition at line 124 of file stm32f3xx_hal_i2c.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HAL mode structure definition

Enumerations
HAL mode structure definition
I2C Exported Types

HAL Mode structure definition. More...

Enumerations

enum HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }

Detailed Description

HAL Mode structure definition.

Note:
HAL I2C Mode value coding follow below described bitmap :
b7 (not used)
x : Should be set to 0
b6
0 : None
1 : Memory (HAL I2C communication is in Memory Mode)
b5
0 : None
1 : Slave (HAL I2C communication is in Slave Mode)
b4
0 : None
1 : Master (HAL I2C communication is in Master Mode)
b3-b2-b1-b0 (not used)
xxxx : Should be set to 0000

Enumeration Type Documentation

enum HAL_I2C_ModeTypeDef
Enumerator:
HAL_I2C_MODE_NONE

No I2C communication on going

HAL_I2C_MODE_MASTER

I2C communication is in Master Mode

HAL_I2C_MODE_SLAVE

I2C communication is in Slave Mode

HAL_I2C_MODE_MEM

I2C communication is in Memory Mode

Definition at line 164 of file stm32f3xx_hal_i2c.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Error Code definition

Defines
I2C Error Code definition
I2C Exported Types

I2C Error Code definition. More...

Defines

#define | HAL_I2C_ERROR_NONE (0x00000000U)
#define | HAL_I2C_ERROR_BERR (0x00000001U)
#define | HAL_I2C_ERROR_ARLO (0x00000002U)
#define | HAL_I2C_ERROR_AF (0x00000004U)
#define | HAL_I2C_ERROR_OVR (0x00000008U)
#define | HAL_I2C_ERROR_DMA (0x00000010U)
#define | HAL_I2C_ERROR_TIMEOUT (0x00000020U)
#define | HAL_I2C_ERROR_SIZE (0x00000040U)

Detailed Description

I2C Error Code definition.

Define Documentation

#define HAL_I2C_ERROR_AF (0x00000004U)

ACKF error

Definition at line 184 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_IsAcknowledgeFailed(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define HAL_I2C_ERROR_ARLO (0x00000002U)

ARLO error

Definition at line 183 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_BERR (0x00000001U)

BERR error

Definition at line 182 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 186 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_DMAError().

#define HAL_I2C_ERROR_NONE (0x00000000U)

No error

Definition at line 181 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define HAL_I2C_ERROR_OVR (0x00000008U)

OVR error

Definition at line 185 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_SIZE (0x00000040U)

Size Management error

Definition at line 188 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define HAL_I2C_ERROR_TIMEOUT (0x00000020U)

Timeout error

Definition at line 187 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C handle Structure definition

Data Structures | Typedefs
I2C handle Structure definition
I2C Exported Types

I2C handle Structure definition. More...

Data Structures

struct | __I2C_HandleTypeDef

Typedefs

typedef struct __I2C_HandleTypeDef | I2C_HandleTypeDef

Detailed Description

I2C handle Structure definition.

Typedef Documentation

typedef struct __I2C_HandleTypeDef I2C_HandleTypeDef
Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: __I2C_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__I2C_HandleTypeDef Struct Reference
I2C handle Structure definition

#include <stm32f3xx_hal_i2c.h>

Data Fields

I2C_TypeDef * | Instance
I2C_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
__IO uint32_t | XferOptions
__IO uint32_t | PreviousState
HAL_StatusTypeDef(* | XferISR )(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_I2C_StateTypeDef | State
__IO HAL_I2C_ModeTypeDef | Mode
__IO uint32_t | ErrorCode
__IO uint32_t | AddrEventCount

Detailed Description

Definition at line 197 of file stm32f3xx_hal_i2c.h.

Field Documentation

__IO uint32_t __I2C_HandleTypeDef::AddrEventCount

I2C Address Event counter

Definition at line 228 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

__IO uint32_t __I2C_HandleTypeDef::ErrorCode

I2C Error code

Definition at line 226 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_GetError(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_IsAcknowledgeFailed(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

DMA_HandleTypeDef* __I2C_HandleTypeDef::hdmarx

I2C Rx DMA handle parameters

Definition at line 218 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Slave_Receive_DMA(), I2C_DMAAbort(), I2C_DMAMasterReceiveCplt(), and I2C_ITError().

DMA_HandleTypeDef* __I2C_HandleTypeDef::hdmatx

I2C Tx DMA handle parameters

Definition at line 216 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Transmit_DMA(), I2C_DMAAbort(), I2C_DMAMasterTransmitCplt(), and I2C_ITError().

I2C_InitTypeDef __I2C_HandleTypeDef::Init

I2C communication parameters

Definition at line 201 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

I2C_TypeDef* __I2C_HandleTypeDef::Instance

I2C registers base address

Definition at line 199 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_EV_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableWakeUp(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Flush_TXDR(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_Slave_ISR_IT(), and I2C_TransferConfig().

HAL_LockTypeDef __I2C_HandleTypeDef::Lock

I2C locking object

Definition at line 220 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

__IO HAL_I2C_ModeTypeDef __I2C_HandleTypeDef::Mode

I2C communication mode

Definition at line 224 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_GetMode(), HAL_I2C_Init(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_IsAcknowledgeFailed(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSequentialCplt(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

uint8_t* __I2C_HandleTypeDef::pBuffPtr

Pointer to I2C transfer buffer

Definition at line 203 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

__IO uint32_t __I2C_HandleTypeDef::PreviousState

I2C communication Previous state

Definition at line 212 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_Init(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

__IO HAL_I2C_StateTypeDef __I2C_HandleTypeDef::State

I2C communication state

Definition at line 222 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_GetState(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableWakeUp(), I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_IsAcknowledgeFailed(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSequentialCplt(), I2C_Master_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

__IO uint16_t __I2C_HandleTypeDef::XferCount

I2C transfer counter

Definition at line 207 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

HAL_StatusTypeDef(* __I2C_HandleTypeDef::XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)

I2C transfer IRQ handler function pointer

Definition at line 214 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), and I2C_ITSlaveCplt().

__IO uint32_t __I2C_HandleTypeDef::XferOptions

I2C sequantial transfer options, this parameter can be a value of I2C Sequential Transfer Options

Definition at line 209 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

uint16_t __I2C_HandleTypeDef::XferSize

I2C transfer size

Definition at line 205 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_i2c.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Sequential Transfer Options

Defines
I2C Sequential Transfer Options
I2C Exported Constants

Defines

#define | I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)

Define Documentation

#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)

Definition at line 249 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_Slave_ISR_IT().

#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))

Definition at line 247 of file stm32f3xx_hal_i2c.h.

#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)

Definition at line 246 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_Slave_ISR_IT().

#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)

Definition at line 250 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_Slave_ISR_IT().

#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))

Definition at line 248 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_Slave_ISR_IT().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Addressing Mode

Defines
I2C Addressing Mode
I2C Exported Constants

Defines

#define | I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define | I2C_ADDRESSINGMODE_10BIT (0x00000002U)

Define Documentation

#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)

Definition at line 259 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)

Definition at line 258 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Dual Addressing Mode

Defines
I2C Dual Addressing Mode
I2C Exported Constants

Defines

#define | I2C_DUALADDRESS_DISABLE (0x00000000U)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Define Documentation

#define I2C_DUALADDRESS_DISABLE (0x00000000U)

Definition at line 267 of file stm32f3xx_hal_i2c.h.

#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Definition at line 268 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Own Address2 Masks

Defines
I2C Own Address2 Masks
I2C Exported Constants

Defines

#define | I2C_OA2_NOMASK ((uint8_t)0x00U)
#define | I2C_OA2_MASK01 ((uint8_t)0x01U)
#define | I2C_OA2_MASK02 ((uint8_t)0x02U)
#define | I2C_OA2_MASK03 ((uint8_t)0x03U)
#define | I2C_OA2_MASK04 ((uint8_t)0x04U)
#define | I2C_OA2_MASK05 ((uint8_t)0x05U)
#define | I2C_OA2_MASK06 ((uint8_t)0x06U)
#define | I2C_OA2_MASK07 ((uint8_t)0x07U)

Define Documentation

#define I2C_OA2_MASK01 ((uint8_t)0x01U)

Definition at line 277 of file stm32f3xx_hal_i2c.h.

#define I2C_OA2_MASK02 ((uint8_t)0x02U)

Definition at line 278 of file stm32f3xx_hal_i2c.h.

#define I2C_OA2_MASK03 ((uint8_t)0x03U)

Definition at line 279 of file stm32f3xx_hal_i2c.h.

#define I2C_OA2_MASK04 ((uint8_t)0x04U)

Definition at line 280 of file stm32f3xx_hal_i2c.h.

#define I2C_OA2_MASK05 ((uint8_t)0x05U)

Definition at line 281 of file stm32f3xx_hal_i2c.h.

#define I2C_OA2_MASK06 ((uint8_t)0x06U)

Definition at line 282 of file stm32f3xx_hal_i2c.h.

#define I2C_OA2_MASK07 ((uint8_t)0x07U)

Definition at line 283 of file stm32f3xx_hal_i2c.h.

#define I2C_OA2_NOMASK ((uint8_t)0x00U)

Definition at line 276 of file stm32f3xx_hal_i2c.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C General Call Addressing Mode

Defines
I2C General Call Addressing Mode
I2C Exported Constants

Defines

#define | I2C_GENERALCALL_DISABLE (0x00000000U)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_GCEN

Define Documentation

#define I2C_GENERALCALL_DISABLE (0x00000000U)

Definition at line 291 of file stm32f3xx_hal_i2c.h.

#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN

Definition at line 292 of file stm32f3xx_hal_i2c.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C No-Stretch Mode

Defines
I2C No-Stretch Mode
I2C Exported Constants

Defines

#define | I2C_NOSTRETCH_DISABLE (0x00000000U)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Define Documentation

#define I2C_NOSTRETCH_DISABLE (0x00000000U)

Definition at line 300 of file stm32f3xx_hal_i2c.h.

#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Definition at line 301 of file stm32f3xx_hal_i2c.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Memory Address Size

Defines
I2C Memory Address Size
I2C Exported Constants

Defines

#define | I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define | I2C_MEMADD_SIZE_16BIT (0x00000002U)

Define Documentation

#define I2C_MEMADD_SIZE_16BIT (0x00000002U)

Definition at line 310 of file stm32f3xx_hal_i2c.h.

#define I2C_MEMADD_SIZE_8BIT (0x00000001U)

Definition at line 309 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Transfer Direction Master Point of View

Defines
I2C Transfer Direction Master Point of View
I2C Exported Constants

Defines

#define | I2C_DIRECTION_TRANSMIT (0x00000000U)
#define | I2C_DIRECTION_RECEIVE (0x00000001U)

Define Documentation

#define I2C_DIRECTION_RECEIVE (0x00000001U)

Definition at line 319 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Sequential_Transmit_IT().

#define I2C_DIRECTION_TRANSMIT (0x00000000U)

Definition at line 318 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Sequential_Receive_IT().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Reload End Mode

Defines
I2C Reload End Mode
I2C Exported Constants

Defines

#define | I2C_RELOAD_MODE I2C_CR2_RELOAD
#define | I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define | I2C_SOFTEND_MODE (0x00000000U)

Define Documentation

#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND

Definition at line 328 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define I2C_RELOAD_MODE I2C_CR2_RELOAD

Definition at line 327 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_RequestMemoryWrite().

#define I2C_SOFTEND_MODE (0x00000000U)

Definition at line 329 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Start or Stop Mode

Defines
I2C Start or Stop Mode
I2C Exported Constants

Defines

#define | I2C_NO_STARTSTOP (0x00000000U)
#define | I2C_GENERATE_STOP I2C_CR2_STOP
#define | I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | I2C_GENERATE_START_WRITE I2C_CR2_START

Define Documentation

#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)

Definition at line 339 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), and HAL_I2C_Mem_Read_IT().

#define I2C_GENERATE_START_WRITE I2C_CR2_START

Definition at line 340 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_GENERATE_STOP I2C_CR2_STOP

Definition at line 338 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Abort_IT().

#define I2C_NO_STARTSTOP (0x00000000U)

Definition at line 337 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Interrupt configuration definition

Defines
I2C Interrupt configuration definition
I2C Exported Constants

I2C Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | I2C_IT_ERRI I2C_CR1_ERRIE
#define | I2C_IT_TCI I2C_CR1_TCIE
#define | I2C_IT_STOPI I2C_CR1_STOPIE
#define | I2C_IT_NACKI I2C_CR1_NACKIE
#define | I2C_IT_ADDRI I2C_CR1_ADDRIE
#define | I2C_IT_RXI I2C_CR1_RXIE
#define | I2C_IT_TXI I2C_CR1_TXIE

Detailed Description

I2C Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define I2C_IT_ADDRI I2C_CR1_ADDRIE

Definition at line 355 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_ERRI I2C_CR1_ERRIE

Definition at line 351 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_Disable_IRQ(), and I2C_Enable_IRQ().

#define I2C_IT_NACKI I2C_CR1_NACKIE

Definition at line 354 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_RXI I2C_CR1_RXIE

Definition at line 356 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

#define I2C_IT_STOPI I2C_CR1_STOPIE

Definition at line 353 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_TCI I2C_CR1_TCIE

Definition at line 352 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define I2C_IT_TXI I2C_CR1_TXIE

Definition at line 357 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Flag definition

Defines
I2C Flag definition
I2C Exported Constants

Defines

#define | I2C_FLAG_TXE I2C_ISR_TXE
#define | I2C_FLAG_TXIS I2C_ISR_TXIS
#define | I2C_FLAG_RXNE I2C_ISR_RXNE
#define | I2C_FLAG_ADDR I2C_ISR_ADDR
#define | I2C_FLAG_AF I2C_ISR_NACKF
#define | I2C_FLAG_STOPF I2C_ISR_STOPF
#define | I2C_FLAG_TC I2C_ISR_TC
#define | I2C_FLAG_TCR I2C_ISR_TCR
#define | I2C_FLAG_BERR I2C_ISR_BERR
#define | I2C_FLAG_ARLO I2C_ISR_ARLO
#define | I2C_FLAG_OVR I2C_ISR_OVR
#define | I2C_FLAG_PECERR I2C_ISR_PECERR
#define | I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | I2C_FLAG_ALERT I2C_ISR_ALERT
#define | I2C_FLAG_BUSY I2C_ISR_BUSY
#define | I2C_FLAG_DIR I2C_ISR_DIR

Define Documentation

#define I2C_FLAG_ADDR I2C_ISR_ADDR

Definition at line 368 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), I2C_ITAddrCplt(), I2C_ITSlaveCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_FLAG_AF I2C_ISR_NACKF

Definition at line 369 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), I2C_IsAcknowledgeFailed(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_FLAG_ALERT I2C_ISR_ALERT

Definition at line 378 of file stm32f3xx_hal_i2c.h.

#define I2C_FLAG_ARLO I2C_ISR_ARLO

Definition at line 374 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_BERR I2C_ISR_BERR

Definition at line 373 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_BUSY I2C_ISR_BUSY

Definition at line 379 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

#define I2C_FLAG_DIR I2C_ISR_DIR

Definition at line 380 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

#define I2C_FLAG_OVR I2C_ISR_OVR

Definition at line 375 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_PECERR I2C_ISR_PECERR

Definition at line 376 of file stm32f3xx_hal_i2c.h.

#define I2C_FLAG_RXNE I2C_ISR_RXNE

Definition at line 367 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Slave_Receive(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define I2C_FLAG_STOPF I2C_ISR_STOPF

Definition at line 370 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_IsAcknowledgeFailed(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnRXNEFlagUntilTimeout(), and I2C_WaitOnSTOPFlagUntilTimeout().

#define I2C_FLAG_TC I2C_ISR_TC

Definition at line 371 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_Master_ISR_IT(), and I2C_RequestMemoryRead().

#define I2C_FLAG_TCR I2C_ISR_TCR

Definition at line 372 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_RequestMemoryWrite().

#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT

Definition at line 377 of file stm32f3xx_hal_i2c.h.

#define I2C_FLAG_TXE I2C_ISR_TXE

Definition at line 365 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_Flush_TXDR().

#define I2C_FLAG_TXIS I2C_ISR_TXIS

Definition at line 366 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_Flush_TXDR(), I2C_Master_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnTXISFlagUntilTimeout().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Exported Macros

Defines
I2C Exported Macros
I2C

Defines

#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified I2C interrupt.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified I2C interrupt.
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified I2C interrupt source is enabled or not.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
Check whether the specified I2C flag is set or not.
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified I2C peripheral.
#define | __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge I2C peripheral in Slave mode.

Define Documentation

#define __HAL_I2C_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
                                                                                : ((__HANDLE__)->Instance->ICR = (__FLAG__)))

Clear the I2C pending flags which are cleared by writing 1 in a specific bit.

Parameters:
__HANDLE__ specifies the I2C Handle.
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • I2C_FLAG_TXE Transmit data register empty
  • I2C_FLAG_ADDR Address matched (slave mode)
  • I2C_FLAG_AF Acknowledge failure received flag
  • I2C_FLAG_STOPF STOP detection flag
  • I2C_FLAG_BERR Bus error
  • I2C_FLAG_ARLO Arbitration lost
  • I2C_FLAG_OVR Overrun/Underrun
  • I2C_FLAG_PECERR PEC error in reception
  • I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
  • I2C_FLAG_ALERT SMBus alert
Return values:
None

Definition at line 491 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), I2C_Flush_TXDR(), I2C_IsAcknowledgeFailed(), I2C_ITAddrCplt(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define __HAL_I2C_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Disable the specified I2C peripheral.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 504 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), and HAL_I2CEx_EnableWakeUp().

#define __HAL_I2C_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

Disable the specified I2C interrupt.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the interrupt source to disable. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
None

Definition at line 431 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), and I2C_Master_ISR_DMA().

#define __HAL_I2C_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Enable the specified I2C peripheral.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 498 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), and HAL_I2CEx_EnableWakeUp().

#define __HAL_I2C_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

Enable the specified I2C interrupt.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the interrupt source to enable. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
None

Definition at line 415 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_Enable_IRQ().

#define __HAL_I2C_GENERATE_NACK ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

Generate a Non-Acknowledge I2C peripheral in Slave mode.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 510 of file stm32f3xx_hal_i2c.h.

#define __HAL_I2C_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Check whether the specified I2C flag is set or not.

Parameters:
__HANDLE__ specifies the I2C Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • I2C_FLAG_TXE Transmit data register empty
  • I2C_FLAG_TXIS Transmit interrupt status
  • I2C_FLAG_RXNE Receive data register not empty
  • I2C_FLAG_ADDR Address matched (slave mode)
  • I2C_FLAG_AF Acknowledge failure received flag
  • I2C_FLAG_STOPF STOP detection flag
  • I2C_FLAG_TC Transfer complete (master mode)
  • I2C_FLAG_TCR Transfer complete reload
  • I2C_FLAG_BERR Bus error
  • I2C_FLAG_ARLO Arbitration lost
  • I2C_FLAG_OVR Overrun/Underrun
  • I2C_FLAG_PECERR PEC error in reception
  • I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
  • I2C_FLAG_ALERT SMBus alert
  • I2C_FLAG_BUSY Bus busy
  • I2C_FLAG_DIR Transfer direction (slave mode)
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 472 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), I2C_Flush_TXDR(), I2C_IsAcknowledgeFailed(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

#define __HAL_I2C_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified I2C interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the I2C interrupt source to check. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 447 of file stm32f3xx_hal_i2c.h.

#define __HAL_I2C_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)

Reset I2C handle state.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 399 of file stm32f3xx_hal_i2c.h.

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STM32F373xC HAL User Manual: I2C Private Constants

I2C Private Constants
I2C
Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Private Macros

Defines
I2C Private Macros
I2C

Defines

#define | IS_I2C_ADDRESSING_MODE(MODE)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
#define | I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define | I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
#define | I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define | I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_GENERATE_START(__ADDMODE__, __ADDRESS__)

Define Documentation

#define I2C_GENERATE_START | ( | __ADDMODE__,
 |  | __ADDRESS__
 | ) |
Value:
(((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

Definition at line 678 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady().

#define I2C_GET_ADDR_MATCH ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)

Definition at line 666 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_DIR ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)

Definition at line 667 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), and I2C_ITAddrCplt().

#define I2C_GET_OWN_ADDRESS1 ( __HANDLE__ ) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)

Definition at line 669 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_OWN_ADDRESS2 ( __HANDLE__ ) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)

Definition at line 670 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_STOP_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)

Definition at line 668 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_Master_ISR_IT().

#define I2C_MEM_ADD_LSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))

Definition at line 676 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_MEM_ADD_MSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))

Definition at line 675 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_RESET_CR2 ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))

Definition at line 664 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_IsAcknowledgeFailed(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define IS_I2C_ADDRESSING_MODE ( MODE )
Value:
(((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))

Definition at line 625 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))

Definition at line 628 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_GENERAL_CALL ( CALL )
Value:
(((CALL) == I2C_GENERALCALL_DISABLE) || \
                                         ((CALL) == I2C_GENERALCALL_ENABLE))

Definition at line 640 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_MEMADD_SIZE ( SIZE )
Value:
(((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))

Definition at line 646 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

#define IS_I2C_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))

Definition at line 643 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= 0x000003FFU)

Definition at line 672 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2 ( ADDRESS2 ) ((ADDRESS2) <= (uint16_t)0x00FFU)

Definition at line 673 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2_MASK ( MASK )
Value:
(((MASK) == I2C_OA2_NOMASK)  || \
                                         ((MASK) == I2C_OA2_MASK01) || \
                                         ((MASK) == I2C_OA2_MASK02) || \
                                         ((MASK) == I2C_OA2_MASK03) || \
                                         ((MASK) == I2C_OA2_MASK04) || \
                                         ((MASK) == I2C_OA2_MASK05) || \
                                         ((MASK) == I2C_OA2_MASK06) || \
                                         ((MASK) == I2C_OA2_MASK07))

Definition at line 631 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_TRANSFER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_FIRST_FRAME)          || \
                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
                                                   ((REQUEST) == I2C_LAST_FRAME))

Definition at line 658 of file stm32f3xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), and HAL_I2C_Slave_Sequential_Transmit_IT().

#define IS_TRANSFER_MODE ( MODE )
Value:
(((MODE) == I2C_RELOAD_MODE)   || \
                                         ((MODE) == I2C_AUTOEND_MODE) || \
                                         ((MODE) == I2C_SOFTEND_MODE))

Definition at line 649 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_TransferConfig().

#define IS_TRANSFER_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_GENERATE_STOP)        || \
                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
                                         ((REQUEST) == I2C_NO_STARTSTOP))

Definition at line 653 of file stm32f3xx_hal_i2c.h.

Referenced by I2C_TransferConfig().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C

Modules | Defines
I2C
STM32F3xx_HAL_Driver

I2C HAL module driver. More...

Modules

I2C Private Define
I2C Private Functions
I2C Exported Functions
I2C Exported Types
I2C Exported Constants
I2C Exported Macros
I2C Private Constants
I2C Private Macros

Defines

#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__)

Detailed Description

I2C HAL module driver.

Define Documentation

#define I2C_GET_DMA_REMAIN_DATA ( __HANDLE__ )
Value:
((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX)   ? \
                                            ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \
                                            ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR)))

Definition at line 303 of file stm32f3xx_hal_i2c.c.

Referenced by I2C_ITSlaveCplt(), and I2C_Slave_ISR_DMA().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Extended Private Constants

I2C Extended Private Constants
Extended features functions
Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Extended Private Macros

Defines
I2C Extended Private Macros
Extended features functions

Defines

#define | IS_I2C_ANALOG_FILTER(FILTER)
#define | IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_I2C_FASTMODEPLUS(__CONFIG__)

Define Documentation

#define IS_I2C_ANALOG_FILTER ( FILTER )
Value:
(((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))

Definition at line 131 of file stm32f3xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_ConfigAnalogFilter().

#define IS_I2C_DIGITAL_FILTER ( FILTER ) ((FILTER) <= 0x0000000FU)

Definition at line 134 of file stm32f3xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_ConfigDigitalFilter().

#define IS_I2C_FASTMODEPLUS ( __CONFIG__ )
Value:
((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
                                         ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6))  == I2C_FASTMODEPLUS_PB6)     || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7))  == I2C_FASTMODEPLUS_PB7)     || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8))  == I2C_FASTMODEPLUS_PB8)     || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9))  == I2C_FASTMODEPLUS_PB9)     || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)    || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)    || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)))

Definition at line 136 of file stm32f3xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_DisableFastModePlus(), and HAL_I2CEx_EnableFastModePlus().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Extended Private Functions

I2C Extended Private Functions
Extended features functions
Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Extended features functions

Modules | Functions
Extended features functions
I2C Extended Exported Functions

Extended features functions. More...

Modules

I2C Extended Private Constants
I2C Extended Private Macros
I2C Extended Private Functions

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from stop mode.
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from stop mode.
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

Extended features functions.

 ===============================================================================
                      ##### Extended features functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure Noise Filters
      (+) Configure Wake Up Feature

Function Documentation

HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | AnalogFilter
 | ) |  |

Configure I2C Analog noise filter.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
AnalogFilter | New state of the Analog filter.
Return values:
HAL status

Definition at line 111 of file stm32f3xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, IS_I2C_ANALOG_FILTER, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure I2C Digital noise filter.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
DigitalFilter | Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
Return values:
HAL status

Definition at line 155 of file stm32f3xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, IS_I2C_DIGITAL_FILTER, and __I2C_HandleTypeDef::State.

void HAL_I2CEx_DisableFastModePlus ( uint32_t ConfigFastModePlus )

Disable the I2C fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the I2C Extended Fast Mode Plus values
Note:
For I2C1, fast mode plus driving capability can be disabled on all selected I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently on each one of the following pins PB6, PB7, PB8 and PB9.
For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
For all I2C2 pins fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C2 parameter.
For all I2C3 pins fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C3 parameter.
Return values:
None

Definition at line 320 of file stm32f3xx_hal_i2c_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_I2C_FASTMODEPLUS.

HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp ( I2C_HandleTypeDef * hi2c )

Disable I2C wakeup from stop mode.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
Return values:
HAL status

Definition at line 245 of file stm32f3xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

void HAL_I2CEx_EnableFastModePlus ( uint32_t ConfigFastModePlus )

Enable the I2C fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the I2C Extended Fast Mode Plus values
Note:
For I2C1, fast mode plus driving capability can be enabled on all selected I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently on each one of the following pins PB6, PB7, PB8 and PB9.
For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
For all I2C2 pins fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C2 parameter.
For all I2C3 pins fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C3 parameter.
Return values:
None

Definition at line 293 of file stm32f3xx_hal_i2c_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_I2C_FASTMODEPLUS.

HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp ( I2C_HandleTypeDef * hi2c )

Enable I2C wakeup from stop mode.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
Return values:
HAL status

Definition at line 206 of file stm32f3xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Extended Analog Filter

Defines
I2C Extended Analog Filter
I2C Extended Exported Constants

Defines

#define | I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Definition at line 66 of file stm32f3xx_hal_i2c_ex.h.

#define I2C_ANALOGFILTER_ENABLE 0x00000000U

Definition at line 65 of file stm32f3xx_hal_i2c_ex.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Extended Fast Mode Plus

Defines
I2C Extended Fast Mode Plus
I2C Extended Exported Constants

Defines

#define | I2C_FMP_NOT_SUPPORTED 0xAAAA0000U
#define | I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED)

Define Documentation

#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP

Enable Fast Mode Plus on I2C1 pins

Definition at line 79 of file stm32f3xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP

Enable Fast Mode Plus on I2C2 pins

Definition at line 81 of file stm32f3xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED)

Fast Mode Plus I2C3 not supported

Definition at line 88 of file stm32f3xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP

Enable Fast Mode Plus on PB6

Definition at line 75 of file stm32f3xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP

Enable Fast Mode Plus on PB7

Definition at line 76 of file stm32f3xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP

Enable Fast Mode Plus on PB8

Definition at line 77 of file stm32f3xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

Enable Fast Mode Plus on PB9

Definition at line 78 of file stm32f3xx_hal_i2c_ex.h.

#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U

Fast Mode Plus not supported

Definition at line 74 of file stm32f3xx_hal_i2c_ex.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Private Functions

Functions
I2S Private Functions
I2S

Functions

static void | I2S_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process complete callback.
static void | I2S_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process half complete callback.
static void | I2S_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process complete callback.
static void | I2S_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process half complete callback.
static void | I2S_DMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
static void | I2S_Transmit_IT (I2S_HandleTypeDef *hi2s)
Transmit an amount of data in non-blocking mode with Interrupt.
static void | I2S_Receive_IT (I2S_HandleTypeDef *hi2s)
Receive an amount of data in non-blocking mode with Interrupt.
static HAL_StatusTypeDef | I2S_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
This function handles I2S Communication Timeout.

Function Documentation

static void I2S_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S communication error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1205 of file stm32f3xx_hal_i2s.c.

References I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_DMA, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_READY, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::State, and I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Receive_DMA(), and HAL_I2S_Transmit_DMA().

static void I2S_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1172 of file stm32f3xx_hal_i2s.c.

References HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_READY, I2S_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, I2S_HandleTypeDef::RxXferCount, and I2S_HandleTypeDef::State.

Referenced by HAL_I2S_Receive_DMA().

static void I2S_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S receive process half complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1192 of file stm32f3xx_hal_i2s.c.

References HAL_I2S_RxHalfCpltCallback().

Referenced by HAL_I2S_Receive_DMA().

static void I2S_DMATxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S transmit process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1138 of file stm32f3xx_hal_i2s.c.

References HAL_I2S_STATE_READY, HAL_I2S_TxCpltCallback(), I2S_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, I2S_HandleTypeDef::State, and I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Transmit_DMA().

static void I2S_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S transmit process half complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1159 of file stm32f3xx_hal_i2s.c.

References HAL_I2S_TxHalfCpltCallback().

Referenced by HAL_I2S_Transmit_DMA().

static void I2S_Receive_IT ( I2S_HandleTypeDef * hi2s ) [static]

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s,: I2S handle
Return values:
None

Definition at line 1248 of file stm32f3xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_READY, I2S_IT_ERR, I2S_IT_RXNE, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pRxBuffPtr, I2S_HandleTypeDef::RxXferCount, and I2S_HandleTypeDef::State.

Referenced by HAL_I2S_IRQHandler().

static void I2S_Transmit_IT ( I2S_HandleTypeDef * hi2s ) [static]

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1227 of file stm32f3xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, HAL_I2S_STATE_READY, HAL_I2S_TxCpltCallback(), I2S_IT_ERR, I2S_IT_TXE, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pTxBuffPtr, I2S_HandleTypeDef::State, and I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_IRQHandler().

static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint32_t | Flag,
 |  | uint32_t | State,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles I2S Communication Timeout.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Flag | Flag checked
State | Value of the flag expected
Timeout | Duration of the timeout
Return values:
HAL status

Definition at line 1273 of file stm32f3xx_hal_i2s.c.

References __HAL_I2S_GET_FLAG, HAL_GetTick(), HAL_I2S_STATE_READY, and I2S_HandleTypeDef::State.

Referenced by HAL_I2S_Receive(), and HAL_I2S_Transmit().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2S Exported Functions

Initialization and Configuration functions. More...

Functions

__weak HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialiaze the I2Sx peripheral in simplex mode:

      (+) User must Implement HAL_I2S_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_I2S_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Standard
        (++) Data Format
        (++) MCLK Output
        (++) Audio frequency
        (++) Polarity
        (++) Full duplex mode

      (+) Call the function HAL_I2S_DeInit() to restore the default configuration
          of the selected I2Sx periperal.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialiaze the I2Sx peripheral in simplex mode:

      (+) User must Implement HAL_I2S_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_I2S_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Standard
        (++) Data Format
        (++) MCLK Output
        (++) Audio frequency
        (++) Polarity

      (+) Call the function HAL_I2S_DeInit() to restore the default configuration
          of the selected I2Sx periperal.

Function Documentation

HAL_StatusTypeDef HAL_I2S_DeInit ( I2S_HandleTypeDef * hi2s )

DeInitializes the I2S peripheral.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 237 of file stm32f3xx_hal_i2s.c.

References assert_param, I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_MspDeInit(), HAL_I2S_STATE_BUSY, HAL_I2S_STATE_RESET, I2S_HandleTypeDef::Instance, and I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Init ( I2S_HandleTypeDef * hi2s )

Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status
Parameters:
hi2s,: I2S handle
Return values:
HAL status

Definition at line 218 of file stm32f3xx_hal_i2s.c.

void HAL_I2S_MspDeInit ( I2S_HandleTypeDef * hi2s )

I2S MSP DeInit.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 284 of file stm32f3xx_hal_i2s.c.

Referenced by HAL_I2S_DeInit().

void HAL_I2S_MspInit ( I2S_HandleTypeDef * hi2s )

I2S MSP Init.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 268 of file stm32f3xx_hal_i2s.c.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IO operation functions

Functions
IO operation functions
I2S Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
__weak HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio stream playing from the Media.
__weak HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
__weak HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2S data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2S_Transmit()
        (++) HAL_I2S_Receive()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2S_Transmit_IT()
        (++) HAL_I2S_Receive_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2S_Transmit_DMA()
        (++) HAL_I2S_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2S_TxCpltCallback()
        (++) HAL_I2S_RxCpltCallback()
        (++) HAL_I2S_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_I2S_DMAPause ( I2S_HandleTypeDef * hi2s )

Pauses the audio stream playing from the Media.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 830 of file stm32f3xx_hal_i2s.c.

References HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_BUSY_TX, I2S_HandleTypeDef::Instance, and I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_DMAResume ( I2S_HandleTypeDef * hi2s )

Resumes the audio stream playing from the Media.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 858 of file stm32f3xx_hal_i2s.c.

References __HAL_I2S_ENABLE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_BUSY_TX, I2S_HandleTypeDef::Instance, and I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_DMAStop ( I2S_HandleTypeDef * hi2s )

Resumes the audio stream playing from the Media.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 893 of file stm32f3xx_hal_i2s.c.

References __HAL_DMA_DISABLE, __HAL_I2S_DISABLE, HAL_DMA_Abort(), HAL_I2S_STATE_READY, I2S_HandleTypeDef::hdmarx, I2S_HandleTypeDef::hdmatx, I2S_HandleTypeDef::Instance, and I2S_HandleTypeDef::State.

void HAL_I2S_ErrorCallback ( I2S_HandleTypeDef * hi2s )

I2S error callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1071 of file stm32f3xx_hal_i2s.c.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Transmit(), and I2S_DMAError().

void HAL_I2S_IRQHandler ( I2S_HandleTypeDef * hi2s )

This function handles I2S interrupt request.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 934 of file stm32f3xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, __HAL_I2S_GET_IT_SOURCE, I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_OVR, HAL_I2S_ERROR_UDR, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_FLAG_OVR, I2S_FLAG_RXNE, I2S_FLAG_TXE, I2S_FLAG_UDR, I2S_IT_ERR, I2S_IT_RXNE, I2S_IT_TXE, I2S_Receive_IT(), I2S_Transmit_IT(), I2S_HandleTypeDef::Instance, and I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Receive | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
Parameters:
Timeout Timeout duration
Note:
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate in continouse way and as the I2S is not disabled at the end of the I2S transaction.
Return values:
HAL status

Definition at line 448 of file stm32f3xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_ENABLE, __HAL_I2S_GET_FLAG, I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_OVR, HAL_I2S_ERROR_TIMEOUT, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_FLAG_OVR, I2S_FLAG_RXNE, I2S_MODE_MASTER_RX, I2S_WaitFlagStateUntilTimeout(), I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::RxXferSize, and I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Receive_DMA | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to the Receive data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 753 of file stm32f3xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_ENABLE, I2S_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_HandleTypeDef::hdmarx, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_DMAError(), I2S_DMARxCplt(), I2S_DMARxHalfCplt(), I2S_MODE_MASTER_RX, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pRxBuffPtr, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::RxXferSize, I2S_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_I2S_Receive_IT | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to the Receive data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
It is recommended to use DMA for the I2S receiver to avoid de-synchronisation between Master and Slave otherwise the I2S interrupt should be optimized.
Return values:
HAL status

Definition at line 613 of file stm32f3xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __HAL_I2S_ENABLE_IT, I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_IT_ERR, I2S_IT_RXNE, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pRxBuffPtr, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::RxXferSize, and I2S_HandleTypeDef::State.

void HAL_I2S_RxCpltCallback ( I2S_HandleTypeDef * hi2s )

Rx Transfer completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1055 of file stm32f3xx_hal_i2s.c.

Referenced by I2S_DMARxCplt(), and I2S_Receive_IT().

void HAL_I2S_RxHalfCpltCallback ( I2S_HandleTypeDef * hi2s )

Rx Transfer half completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1039 of file stm32f3xx_hal_i2s.c.

Referenced by I2S_DMARxHalfCplt().

HAL_StatusTypeDef HAL_I2S_Transmit | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
Parameters:
Timeout Timeout duration
Note:
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 355 of file stm32f3xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __HAL_I2S_GET_FLAG, I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_TIMEOUT, HAL_I2S_ERROR_UDR, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_FLAG_TXE, I2S_FLAG_UDR, I2S_WaitFlagStateUntilTimeout(), I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::State, I2S_HandleTypeDef::TxXferCount, and I2S_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_I2S_Transmit_DMA | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to the Transmit data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 675 of file stm32f3xx_hal_i2s.c.

References __HAL_I2S_ENABLE, I2S_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_HandleTypeDef::hdmatx, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_DMAError(), I2S_DMATxCplt(), I2S_DMATxHalfCplt(), I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pTxBuffPtr, I2S_HandleTypeDef::State, I2S_HandleTypeDef::TxXferCount, I2S_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_I2S_Transmit_IT | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 548 of file stm32f3xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __HAL_I2S_ENABLE_IT, I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_IT_ERR, I2S_IT_TXE, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pTxBuffPtr, I2S_HandleTypeDef::State, I2S_HandleTypeDef::TxXferCount, and I2S_HandleTypeDef::TxXferSize.

void HAL_I2S_TxCpltCallback ( I2S_HandleTypeDef * hi2s )

Tx Transfer completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1023 of file stm32f3xx_hal_i2s.c.

Referenced by I2S_DMATxCplt(), and I2S_Transmit_IT().

void HAL_I2S_TxHalfCpltCallback ( I2S_HandleTypeDef * hi2s )

Tx Transfer Half completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1007 of file stm32f3xx_hal_i2s.c.

Referenced by I2S_DMATxHalfCplt().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
I2S Exported Functions

Peripheral State functions. More...

Functions

HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.
HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_StatusTypeDef HAL_I2S_DMAPause ( I2S_HandleTypeDef * hi2s )

Pauses the audio stream playing from the Media.

Parameters:
hi2s : I2S handle
Return values:
None

Definition at line 585 of file stm32f3xx_hal_i2s_ex.c.

References HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_BUSY_TX_RX, I2S_HandleTypeDef::Instance, and I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_DMAResume ( I2S_HandleTypeDef * hi2s )

Resumes the audio stream playing from the Media.

Parameters:
hi2s : I2S handle
Return values:
None

Definition at line 620 of file stm32f3xx_hal_i2s_ex.c.

References __HAL_I2S_ENABLE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_BUSY_TX_RX, I2S_HandleTypeDef::Instance, and I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_DMAStop ( I2S_HandleTypeDef * hi2s )

Resumes the audio stream playing from the Media.

Parameters:
hi2s,: I2S handle
Return values:
None

Definition at line 669 of file stm32f3xx_hal_i2s_ex.c.

References __HAL_I2S_DISABLE, HAL_DMA_Abort(), HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_BUSY_TX_RX, HAL_I2S_STATE_READY, I2S_HandleTypeDef::hdmarx, I2S_HandleTypeDef::hdmatx, I2S_HandleTypeDef::Instance, and I2S_HandleTypeDef::State.

uint32_t HAL_I2S_GetError ( I2S_HandleTypeDef * hi2s )

Return the I2S error code.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
I2S Error Code

Definition at line 1117 of file stm32f3xx_hal_i2s.c.

References I2S_HandleTypeDef::ErrorCode.

HAL_I2S_StateTypeDef HAL_I2S_GetState ( I2S_HandleTypeDef * hi2s )

Return the I2S state.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL state

Definition at line 1106 of file stm32f3xx_hal_i2s.c.

References I2S_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Exported Types

Data Structures | Enumerations
I2S Exported Types
I2S

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | I2S_HandleTypeDef
I2S handle Structure definition. More...

Enumerations

enum HAL_I2S_StateTypeDef {
HAL_I2S_STATE_RESET = 0x00U, HAL_I2S_STATE_READY = 0x01U, HAL_I2S_STATE_BUSY = 0x02U, HAL_I2S_STATE_BUSY_TX = 0x03U,
HAL_I2S_STATE_BUSY_RX = 0x04U, HAL_I2S_STATE_BUSY_TX_RX = 0x05U, HAL_I2S_STATE_TIMEOUT = 0x06U, HAL_I2S_STATE_ERROR = 0x07
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_I2S_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_I2S_STATE_RESET

I2S not yet initialized or disabled

HAL_I2S_STATE_READY

I2S initialized and ready for use

HAL_I2S_STATE_BUSY

I2S internal process is ongoing

HAL_I2S_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_I2S_STATE_BUSY_RX

Data Reception process is ongoing

HAL_I2S_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_I2S_STATE_TIMEOUT

I2S timeout state

HAL_I2S_STATE_ERROR

I2S error state

Definition at line 99 of file stm32f3xx_hal_i2s.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2S_InitTypeDef Struct Reference
I2S Exported Types

I2S Init structure definition. More...

#include <stm32f3xx_hal_i2s.h>

Data Fields

uint32_t | Mode
uint32_t | Standard
uint32_t | DataFormat
uint32_t | MCLKOutput
uint32_t | AudioFreq
uint32_t | CPOL
uint32_t | ClockSource
uint32_t | FullDuplexMode

Detailed Description

I2S Init structure definition.

Definition at line 68 of file stm32f3xx_hal_i2s.h.

Field Documentation

uint32_t I2S_InitTypeDef::AudioFreq

Specifies the frequency selected for the I2S communication. This parameter can be a value of I2S Audio Frequency

Definition at line 82 of file stm32f3xx_hal_i2s.h.

uint32_t I2S_InitTypeDef::ClockSource

Specifies the I2S Clock Source. This parameter can be a value of I2S Clock Source

Definition at line 88 of file stm32f3xx_hal_i2s.h.

uint32_t I2S_InitTypeDef::CPOL

Specifies the idle state of the I2S clock. This parameter can be a value of I2S Clock Polarity

Definition at line 85 of file stm32f3xx_hal_i2s.h.

uint32_t I2S_InitTypeDef::DataFormat

Specifies the data format for the I2S communication. This parameter can be a value of I2S Data Format

Definition at line 76 of file stm32f3xx_hal_i2s.h.

uint32_t I2S_InitTypeDef::FullDuplexMode

Specifies the I2S FullDuplex mode. This parameter can be a value of I2S Full Duplex Mode

Definition at line 91 of file stm32f3xx_hal_i2s.h.

uint32_t I2S_InitTypeDef::MCLKOutput

Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of I2S MCLK Output

Definition at line 79 of file stm32f3xx_hal_i2s.h.

uint32_t I2S_InitTypeDef::Mode

Specifies the I2S operating mode. This parameter can be a value of I2S Mode

Definition at line 70 of file stm32f3xx_hal_i2s.h.

uint32_t I2S_InitTypeDef::Standard

Specifies the standard used for the I2S communication. This parameter can be a value of I2S Standard

Definition at line 73 of file stm32f3xx_hal_i2s.h.

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_i2s.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2S_HandleTypeDef Struct Reference
I2S Exported Types

I2S handle Structure definition. More...

#include <stm32f3xx_hal_i2s.h>

Data Fields

SPI_TypeDef * | Instance
I2S_InitTypeDef Init
uint16_t * | pTxBuffPtr
__IO uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint16_t * | pRxBuffPtr
__IO uint16_t | RxXferSize
__IO uint16_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
__IO HAL_LockTypeDef | Lock
__IO HAL_I2S_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

I2S handle Structure definition.

Definition at line 114 of file stm32f3xx_hal_i2s.h.

Field Documentation

__IO uint32_t I2S_HandleTypeDef::ErrorCode

I2S Error code This parameter can be a value of I2S Error

Definition at line 145 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_GetError(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), and I2S_DMAError().

DMA_HandleTypeDef* I2S_HandleTypeDef::hdmarx

I2S Rx DMA handle parameters

Definition at line 139 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Receive_DMA().

DMA_HandleTypeDef* I2S_HandleTypeDef::hdmatx

I2S Tx DMA handle parameters

Definition at line 137 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Transmit_DMA().

I2S_InitTypeDef I2S_HandleTypeDef::Init

I2S communication parameters

Definition at line 118 of file stm32f3xx_hal_i2s.h.

SPI_TypeDef* I2S_HandleTypeDef::Instance

I2S registers base address

Definition at line 116 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_DMAStop(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2S_Receive_IT(), and I2S_Transmit_IT().

__IO HAL_LockTypeDef I2S_HandleTypeDef::Lock

I2S locking object

Definition at line 141 of file stm32f3xx_hal_i2s.h.

uint16_t* I2S_HandleTypeDef::pRxBuffPtr

Pointer to I2S Rx transfer buffer

Definition at line 126 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), and I2S_Receive_IT().

uint16_t* I2S_HandleTypeDef::pTxBuffPtr

Pointer to I2S Tx transfer buffer

Definition at line 120 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), and I2S_Transmit_IT().

__IO uint16_t I2S_HandleTypeDef::RxXferCount

I2S Rx transfer counter (This field is initialized at the same value as transfer size at the beginning of the transfer and decremented when a sample is received. NbSamplesReceived = RxBufferSize-RxBufferCount)

Definition at line 130 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), I2S_DMAError(), I2S_DMARxCplt(), and I2S_Receive_IT().

__IO uint16_t I2S_HandleTypeDef::RxXferSize

I2S Rx transfer size

Definition at line 128 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), and HAL_I2S_Receive_IT().

__IO HAL_I2S_StateTypeDef I2S_HandleTypeDef::State

I2S communication state

Definition at line 143 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_DMAStop(), HAL_I2S_GetState(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2S_Receive_IT(), I2S_Transmit_IT(), and I2S_WaitFlagStateUntilTimeout().

__IO uint16_t I2S_HandleTypeDef::TxXferCount

I2S Tx transfer Counter

Definition at line 124 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_DMAError(), I2S_DMATxCplt(), and I2S_Transmit_IT().

__IO uint16_t I2S_HandleTypeDef::TxXferSize

I2S Tx transfer size

Definition at line 122 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_i2s.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Error

Defines
I2S Error
I2S Exported Constants

Defines

#define | HAL_I2S_ERROR_NONE (0x00000000U)
#define | HAL_I2S_ERROR_TIMEOUT (0x00000001U)
#define | HAL_I2S_ERROR_OVR (0x00000002U)
#define | HAL_I2S_ERROR_UDR (0x00000004U)
#define | HAL_I2S_ERROR_DMA (0x00000008U)
#define | HAL_I2S_ERROR_UNKNOW (0x00000010U)

Define Documentation

#define HAL_I2S_ERROR_DMA (0x00000008U)

DMA transfer error

Definition at line 164 of file stm32f3xx_hal_i2s.h.

Referenced by I2S_DMAError().

#define HAL_I2S_ERROR_NONE (0x00000000U)

No error

Definition at line 160 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define HAL_I2S_ERROR_OVR (0x00000002U)

OVR error

Definition at line 162 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive().

#define HAL_I2S_ERROR_TIMEOUT (0x00000001U)

Timeout error

Definition at line 161 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), and HAL_I2S_Transmit().

#define HAL_I2S_ERROR_UDR (0x00000004U)

UDR error

Definition at line 163 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Transmit().

#define HAL_I2S_ERROR_UNKNOW (0x00000010U)

Unknow Error error

Definition at line 165 of file stm32f3xx_hal_i2s.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Clock Source

Defines
I2S Clock Source
I2S Exported Constants

Defines

#define | I2S_CLOCK_EXTERNAL (0x00000001U)
#define | I2S_CLOCK_SYSCLK (0x00000002U)
#define | IS_I2S_CLOCKSOURCE(CLOCK)

Define Documentation

#define I2S_CLOCK_EXTERNAL (0x00000001U)

Definition at line 173 of file stm32f3xx_hal_i2s.h.

#define I2S_CLOCK_SYSCLK (0x00000002U)

Definition at line 174 of file stm32f3xx_hal_i2s.h.

#define IS_I2S_CLOCKSOURCE ( CLOCK )
Value:
(((CLOCK) == I2S_CLOCK_EXTERNAL) || \
                                   ((CLOCK) == I2S_CLOCK_SYSCLK))

Definition at line 176 of file stm32f3xx_hal_i2s.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Mode

Defines
I2S Mode
I2S Exported Constants

Defines

#define | I2S_MODE_SLAVE_TX (0x00000000U)
#define | I2S_MODE_SLAVE_RX (0x00000100U)
#define | I2S_MODE_MASTER_TX (0x00000200U)
#define | I2S_MODE_MASTER_RX (0x00000300U)
#define | IS_I2S_MODE(MODE)

Define Documentation

#define I2S_MODE_MASTER_RX (0x00000300U)

Definition at line 188 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), and HAL_I2S_Receive_DMA().

#define I2S_MODE_MASTER_TX (0x00000200U)

Definition at line 187 of file stm32f3xx_hal_i2s.h.

#define I2S_MODE_SLAVE_RX (0x00000100U)

Definition at line 186 of file stm32f3xx_hal_i2s.h.

#define I2S_MODE_SLAVE_TX (0x00000000U)

Definition at line 185 of file stm32f3xx_hal_i2s.h.

#define IS_I2S_MODE ( MODE )
Value:
(((MODE) == I2S_MODE_SLAVE_TX) || \
                           ((MODE) == I2S_MODE_SLAVE_RX) || \
                           ((MODE) == I2S_MODE_MASTER_TX)|| \
                           ((MODE) == I2S_MODE_MASTER_RX))

Definition at line 190 of file stm32f3xx_hal_i2s.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Standard

Defines
I2S Standard
I2S Exported Constants

Defines

#define | I2S_STANDARD_PHILIPS (0x00000000U)
#define | I2S_STANDARD_MSB (0x00000010U)
#define | I2S_STANDARD_LSB (0x00000020U)
#define | I2S_STANDARD_PCM_SHORT (0x00000030U)
#define | I2S_STANDARD_PCM_LONG (0x000000B0U)
#define | IS_I2S_STANDARD(STANDARD)

Define Documentation

#define I2S_STANDARD_LSB (0x00000020U)

Definition at line 203 of file stm32f3xx_hal_i2s.h.

#define I2S_STANDARD_MSB (0x00000010U)

Definition at line 202 of file stm32f3xx_hal_i2s.h.

#define I2S_STANDARD_PCM_LONG (0x000000B0U)

Definition at line 205 of file stm32f3xx_hal_i2s.h.

#define I2S_STANDARD_PCM_SHORT (0x00000030U)

Definition at line 204 of file stm32f3xx_hal_i2s.h.

#define I2S_STANDARD_PHILIPS (0x00000000U)

Definition at line 201 of file stm32f3xx_hal_i2s.h.

#define IS_I2S_STANDARD ( STANDARD )
Value:
(((STANDARD) == I2S_STANDARD_PHILIPS) || \
                                   ((STANDARD) == I2S_STANDARD_MSB) || \
                                   ((STANDARD) == I2S_STANDARD_LSB) || \
                                   ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
                                   ((STANDARD) == I2S_STANDARD_PCM_LONG))

Definition at line 207 of file stm32f3xx_hal_i2s.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Data Format

Defines
I2S Data Format
I2S Exported Constants

Defines

#define | I2S_DATAFORMAT_16B (0x00000000U)
#define | I2S_DATAFORMAT_16B_EXTENDED (0x00000001U)
#define | I2S_DATAFORMAT_24B (0x00000003U)
#define | I2S_DATAFORMAT_32B (0x00000005U)
#define | IS_I2S_DATA_FORMAT(FORMAT)

Define Documentation

#define I2S_DATAFORMAT_16B (0x00000000U)

Definition at line 219 of file stm32f3xx_hal_i2s.h.

#define I2S_DATAFORMAT_16B_EXTENDED (0x00000001U)

Definition at line 220 of file stm32f3xx_hal_i2s.h.

#define I2S_DATAFORMAT_24B (0x00000003U)

Definition at line 221 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define I2S_DATAFORMAT_32B (0x00000005U)

Definition at line 222 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define IS_I2S_DATA_FORMAT ( FORMAT )
Value:
(((FORMAT) == I2S_DATAFORMAT_16B) || \
                                    ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
                                    ((FORMAT) == I2S_DATAFORMAT_24B) || \
                                    ((FORMAT) == I2S_DATAFORMAT_32B))

Definition at line 224 of file stm32f3xx_hal_i2s.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S MCLK Output

Defines
I2S MCLK Output
I2S Exported Constants

Defines

#define | I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
#define | I2S_MCLKOUTPUT_DISABLE (0x00000000U)
#define | IS_I2S_MCLK_OUTPUT(OUTPUT)

Define Documentation

#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)

Definition at line 236 of file stm32f3xx_hal_i2s.h.

#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)

Definition at line 235 of file stm32f3xx_hal_i2s.h.

#define IS_I2S_MCLK_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
                                    ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))

Definition at line 238 of file stm32f3xx_hal_i2s.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Audio Frequency

Defines
I2S Audio Frequency
I2S Exported Constants

Defines

#define | I2S_AUDIOFREQ_192K (192000U)
#define | I2S_AUDIOFREQ_96K (96000U)
#define | I2S_AUDIOFREQ_48K (48000U)
#define | I2S_AUDIOFREQ_44K (44100U)
#define | I2S_AUDIOFREQ_32K (32000U)
#define | I2S_AUDIOFREQ_22K (22050U)
#define | I2S_AUDIOFREQ_16K (16000U)
#define | I2S_AUDIOFREQ_11K (11025U)
#define | I2S_AUDIOFREQ_8K (8000U)
#define | I2S_AUDIOFREQ_DEFAULT (2U)
#define | IS_I2S_AUDIO_FREQ(FREQ)

Define Documentation

#define I2S_AUDIOFREQ_11K (11025U)

Definition at line 254 of file stm32f3xx_hal_i2s.h.

#define I2S_AUDIOFREQ_16K (16000U)

Definition at line 253 of file stm32f3xx_hal_i2s.h.

#define I2S_AUDIOFREQ_192K (192000U)

Definition at line 247 of file stm32f3xx_hal_i2s.h.

#define I2S_AUDIOFREQ_22K (22050U)

Definition at line 252 of file stm32f3xx_hal_i2s.h.

#define I2S_AUDIOFREQ_32K (32000U)

Definition at line 251 of file stm32f3xx_hal_i2s.h.

#define I2S_AUDIOFREQ_44K (44100U)

Definition at line 250 of file stm32f3xx_hal_i2s.h.

#define I2S_AUDIOFREQ_48K (48000U)

Definition at line 249 of file stm32f3xx_hal_i2s.h.

#define I2S_AUDIOFREQ_8K (8000U)

Definition at line 255 of file stm32f3xx_hal_i2s.h.

#define I2S_AUDIOFREQ_96K (96000U)

Definition at line 248 of file stm32f3xx_hal_i2s.h.

#define I2S_AUDIOFREQ_DEFAULT (2U)

Definition at line 256 of file stm32f3xx_hal_i2s.h.

#define IS_I2S_AUDIO_FREQ ( FREQ )
Value:
((((FREQ) >= I2S_AUDIOFREQ_8K) && \
                                 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
                                 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))

Definition at line 258 of file stm32f3xx_hal_i2s.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Full Duplex Mode

Defines
I2S Full Duplex Mode
I2S Exported Constants

Defines

#define | I2S_FULLDUPLEXMODE_DISABLE (0x00000000U)
#define | I2S_FULLDUPLEXMODE_ENABLE (0x00000001U)
#define | IS_I2S_FULLDUPLEX_MODE(MODE)

Define Documentation

#define I2S_FULLDUPLEXMODE_DISABLE (0x00000000U)

Definition at line 268 of file stm32f3xx_hal_i2s.h.

#define I2S_FULLDUPLEXMODE_ENABLE (0x00000001U)

Definition at line 269 of file stm32f3xx_hal_i2s.h.

#define IS_I2S_FULLDUPLEX_MODE ( MODE )
Value:
(((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
                                      ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))

Definition at line 271 of file stm32f3xx_hal_i2s.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Clock Polarity

Defines
I2S Clock Polarity
I2S Exported Constants

Defines

#define | I2S_CPOL_LOW (0x00000000U)
#define | I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
#define | IS_I2S_CPOL(CPOL)

Define Documentation

#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)

Definition at line 281 of file stm32f3xx_hal_i2s.h.

#define I2S_CPOL_LOW (0x00000000U)

Definition at line 280 of file stm32f3xx_hal_i2s.h.

#define IS_I2S_CPOL ( CPOL )
Value:
(((CPOL) == I2S_CPOL_LOW) || \
                           ((CPOL) == I2S_CPOL_HIGH))

Definition at line 283 of file stm32f3xx_hal_i2s.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Interrupt configuration definition

Defines
I2S Interrupt configuration definition
I2S Exported Constants

Defines

#define | I2S_IT_TXE SPI_CR2_TXEIE
#define | I2S_IT_RXNE SPI_CR2_RXNEIE
#define | I2S_IT_ERR SPI_CR2_ERRIE

Define Documentation

#define I2S_IT_ERR SPI_CR2_ERRIE

Definition at line 294 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit_IT(), I2S_Receive_IT(), and I2S_Transmit_IT().

#define I2S_IT_RXNE SPI_CR2_RXNEIE

Definition at line 293 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive_IT(), and I2S_Receive_IT().

#define I2S_IT_TXE SPI_CR2_TXEIE

Definition at line 292 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Transmit_IT(), and I2S_Transmit_IT().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Flag definition

Defines
I2S Flag definition
I2S Exported Constants

Defines

#define | I2S_FLAG_TXE SPI_SR_TXE
#define | I2S_FLAG_RXNE SPI_SR_RXNE
#define | I2S_FLAG_UDR SPI_SR_UDR
#define | I2S_FLAG_OVR SPI_SR_OVR
#define | I2S_FLAG_FRE SPI_SR_FRE
#define | I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define | I2S_FLAG_BSY SPI_SR_BSY

Define Documentation

#define I2S_FLAG_BSY SPI_SR_BSY

Definition at line 310 of file stm32f3xx_hal_i2s.h.

#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE

Definition at line 309 of file stm32f3xx_hal_i2s.h.

#define I2S_FLAG_FRE SPI_SR_FRE

Definition at line 307 of file stm32f3xx_hal_i2s.h.

#define I2S_FLAG_OVR SPI_SR_OVR

Definition at line 306 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive().

#define I2S_FLAG_RXNE SPI_SR_RXNE

Definition at line 303 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive().

#define I2S_FLAG_TXE SPI_SR_TXE

Definition at line 302 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Transmit().

#define I2S_FLAG_UDR SPI_SR_UDR

Definition at line 305 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Transmit().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Exported Macros

Defines
I2S Exported Macros
I2S

Defines

#define | __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
Reset I2S handle state.
#define | __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
Enable or disable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SE))
#define | __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enable or disable the specified I2S interrupts.
#define | __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__)))
#define | __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified I2S interrupt source is enabled or disabled.
#define | __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified I2S flag is set or not.
#define | __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)
Clears the I2S OVR pending flag.
#define | __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)
Clears the I2S UDR pending flag.

Define Documentation

#define __HAL_I2S_CLEAR_OVRFLAG ( __HANDLE__ )
Value:
do{ \
                                               __IO uint32_t tmpreg; \
                                               tmpreg = (__HANDLE__)->Instance->DR; \
                                               tmpreg = (__HANDLE__)->Instance->SR; \
                                               UNUSED(tmpreg); \
                                              }while(0U)

Clears the I2S OVR pending flag.

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 380 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), and HAL_I2S_Receive_DMA().

#define __HAL_I2S_CLEAR_UDRFLAG ( __HANDLE__ )
Value:
do{\
                                               __IO uint32_t tmpreg;\
                                               tmpreg = ((__HANDLE__)->Instance->SR);\
                                               UNUSED(tmpreg); \
                                              }while(0U)

Clears the I2S UDR pending flag.

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 390 of file stm32f3xx_hal_i2s.h.

#define __HAL_I2S_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SE))

Definition at line 335 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop().

#define __HAL_I2S_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__)))

Definition at line 347 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), I2S_Receive_IT(), and I2S_Transmit_IT().

#define __HAL_I2S_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)

Enable or disable the specified SPI peripheral (in I2S mode).

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 334 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_DMAResume(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define __HAL_I2S_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))

Enable or disable the specified I2S interrupts.

Parameters:
__HANDLE__ specifies the I2S Handle.
__INTERRUPT__ specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • I2S_IT_TXE: Tx buffer empty interrupt enable
  • I2S_IT_RXNE: RX buffer not empty interrupt enable
  • I2S_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 346 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_Receive_IT(), and HAL_I2S_Transmit_IT().

#define __HAL_I2S_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Checks whether the specified I2S flag is set or not.

Parameters:
__HANDLE__ specifies the I2S Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • I2S_FLAG_RXNE: Receive buffer not empty flag
  • I2S_FLAG_TXE: Transmit buffer empty flag
  • I2S_FLAG_UDR: Underrun flag
  • I2S_FLAG_OVR: Overrun flag
  • I2S_FLAG_FRE: Frame error flag
  • I2S_FLAG_CHSIDE: Channel Side flag
  • I2S_FLAG_BSY: Busy flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 374 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Transmit(), and I2S_WaitFlagStateUntilTimeout().

#define __HAL_I2S_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified I2S interrupt source is enabled or disabled.

Parameters:
__HANDLE__ specifies the I2S Handle. This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
__INTERRUPT__ specifies the I2S interrupt source to check. This parameter can be one of the following values:
  • I2S_IT_TXE: Tx buffer empty interrupt enable
  • I2S_IT_RXNE: RX buffer not empty interrupt enable
  • I2S_IT_ERR: Error interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 359 of file stm32f3xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

#define __HAL_I2S_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)

Reset I2S handle state.

Parameters:
__HANDLE__ I2S handle.
Return values:
None

Definition at line 328 of file stm32f3xx_hal_i2s.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Extended Exported Macros

I2S Extended Exported Macros
I2SEx
Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Extended Exported Functions

I2S Extended Exported Functions
I2SEx
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA Private Constants

Defines
IRDA Private Constants
IRDA

Defines

#define | IRDA_TEACK_REACK_TIMEOUT 1000
#define | IRDA_CR1_FIELDS

Define Documentation

#define IRDA_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE \
                                   | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))

UART or USART CR1 fields of parameters set by IRDA_SetConfig API

Definition at line 159 of file stm32f3xx_hal_irda.c.

Referenced by IRDA_SetConfig().

#define IRDA_TEACK_REACK_TIMEOUT 1000

IRDA TX or RX enable acknowledge time-out value

Definition at line 158 of file stm32f3xx_hal_irda.c.

Referenced by IRDA_CheckIdleState().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
IRDA Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USARTx
  in asynchronous IRDA mode.
  (+) For the asynchronous mode only these parameters can be configured:
      (++) Baud Rate
      (++) Word Length
      (++) Parity
      (++) Power mode
      (++) Prescaler setting
      (++) Receiver/transmitter modes

  [..]
  The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
  (details for the procedures are available in reference manual).

Function Documentation

HAL_StatusTypeDef HAL_IRDA_DeInit ( IRDA_HandleTypeDef * hirda )

DeInitialize the IRDA peripheral.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 322 of file stm32f3xx_hal_irda.c.

References __HAL_IRDA_DISABLE, assert_param, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_MspDeInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_Init ( IRDA_HandleTypeDef * hirda )

Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 269 of file stm32f3xx_hal_irda.c.

References __HAL_IRDA_DISABLE, __HAL_IRDA_ENABLE, assert_param, IRDA_HandleTypeDef::gState, HAL_IRDA_MspInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, IRDA_HandleTypeDef::Instance, IRDA_CheckIdleState(), IRDA_SetConfig(), and IRDA_HandleTypeDef::Lock.

void HAL_IRDA_MspDeInit ( IRDA_HandleTypeDef * hirda )

DeInitialize the IRDA MSP.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 372 of file stm32f3xx_hal_irda.c.

Referenced by HAL_IRDA_DeInit().

void HAL_IRDA_MspInit ( IRDA_HandleTypeDef * hirda )

Initialize the IRDA MSP.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 356 of file stm32f3xx_hal_irda.c.

Referenced by HAL_IRDA_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IO operation functions

Functions
IO operation functions
IRDA Exported Functions

IRDA Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.

Detailed Description

IRDA Transmit and Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the IRDA data transfers.

  [..]
    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
    While receiving data, transmission should be avoided as the data to be transmitted
    could be corrupted.

    (#) There are two mode of transfer:
        (++) Blocking mode: the communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) Non-Blocking mode: the communication is performed using Interrupts
             or DMA, these API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
             The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
             will be executed respectively at the end of the Transmit or Receive process
             The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected

    (#) Blocking mode APIs are :
        (++) HAL_IRDA_Transmit()
        (++) HAL_IRDA_Receive()

    (#) Non Blocking mode APIs with Interrupt are :
        (++) HAL_IRDA_Transmit_IT()
        (++) HAL_IRDA_Receive_IT()
        (++) HAL_IRDA_IRQHandler()

    (#) Non Blocking mode functions with DMA are :
        (++) HAL_IRDA_Transmit_DMA()
        (++) HAL_IRDA_Receive_DMA()
        (++) HAL_IRDA_DMAPause()
        (++) HAL_IRDA_DMAResume()
        (++) HAL_IRDA_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
        (++) HAL_IRDA_TxHalfCpltCallback()
        (++) HAL_IRDA_TxCpltCallback()
        (++) HAL_IRDA_RxHalfCpltCallback()
        (++) HAL_IRDA_RxCpltCallback()
        (++) HAL_IRDA_ErrorCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (++) HAL_IRDA_Abort()
        (++) HAL_IRDA_AbortTransmit()
        (++) HAL_IRDA_AbortReceive()
        (++) HAL_IRDA_Abort_IT()
        (++) HAL_IRDA_AbortTransmit_IT()
        (++) HAL_IRDA_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
        (++) HAL_IRDA_AbortCpltCallback()
        (++) HAL_IRDA_AbortTransmitCpltCallback()
        (++) HAL_IRDA_AbortReceiveCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
       (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
            and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
            If user wants to abort it, Abort services should be called by user.
       (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
            Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_IRDA_Abort ( IRDA_HandleTypeDef * hirda )

Abort ongoing transfers (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 968 of file stm32f3xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_Abort_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing transfers (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1128 of file stm32f3xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1606 of file stm32f3xx_hal_irda.c.

Referenced by HAL_IRDA_Abort_IT(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

HAL_StatusTypeDef HAL_IRDA_AbortReceive ( IRDA_HandleTypeDef * hirda )

Abort ongoing Receive transfer (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1079 of file stm32f3xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, HAL_DMA_Abort(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1320 of file stm32f3xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, HAL_DMA_Abort_IT(), HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMARxOnlyAbortCallback(), IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortReceiveCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Receive Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1638 of file stm32f3xx_hal_irda.c.

Referenced by HAL_IRDA_AbortReceive_IT(), and IRDA_DMARxOnlyAbortCallback().

HAL_StatusTypeDef HAL_IRDA_AbortTransmit ( IRDA_HandleTypeDef * hirda )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1036 of file stm32f3xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1254 of file stm32f3xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_DMATxOnlyAbortCallback(), IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortTransmitCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1622 of file stm32f3xx_hal_irda.c.

Referenced by HAL_IRDA_AbortTransmit_IT(), and IRDA_DMATxOnlyAbortCallback().

HAL_StatusTypeDef HAL_IRDA_DMAPause ( IRDA_HandleTypeDef * hirda )

Pause the DMA Transfer.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 844 of file stm32f3xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAResume ( IRDA_HandleTypeDef * hirda )

Resume the DMA Transfer.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 878 of file stm32f3xx_hal_irda.c.

References __HAL_IRDA_CLEAR_OREFLAG, IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAStop ( IRDA_HandleTypeDef * hirda )

Stop the DMA Transfer.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 913 of file stm32f3xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_EndRxTransfer(), IRDA_EndTxTransfer(), and IRDA_HandleTypeDef::RxState.

void HAL_IRDA_ErrorCallback ( IRDA_HandleTypeDef * hirda )

IRDA error callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1590 of file stm32f3xx_hal_irda.c.

Referenced by HAL_IRDA_IRQHandler(), IRDA_DMAAbortOnError(), and IRDA_DMAError().

void HAL_IRDA_IRQHandler ( IRDA_HandleTypeDef * hirda )

Handle IRDA interrupt request.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1384 of file stm32f3xx_hal_irda.c.

References __HAL_IRDA_CLEAR_IT, IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_IRDA_ERROR_FE, HAL_IRDA_ERROR_NE, HAL_IRDA_ERROR_NONE, HAL_IRDA_ERROR_ORE, HAL_IRDA_ERROR_PE, HAL_IRDA_ErrorCallback(), IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMAAbortOnError(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_Receive_IT(), IRDA_Transmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_Receive | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer.
Size | Amount of data to be received.
Timeout | Specify timeout value.
Return values:
HAL status

Definition at line 548 of file stm32f3xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_FLAG_RXNE, IRDA_MASK_COMPUTATION, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, IRDA_HandleTypeDef::Mask, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::RxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Receive_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer.
Size | Amount of data to be received.
Note:
When the IRDA parity is enabled (PCE = 1), the received data contains the parity bit (MSB position).
Return values:
HAL status

Definition at line 779 of file stm32f3xx_hal_irda.c.

References assert_param, IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::Instance, IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMAReceiveHalfCplt(), IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Receive_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer.
Size | Amount of data to be received.
Return values:
HAL status

Definition at line 664 of file stm32f3xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Instance, IRDA_MASK_COMPUTATION, IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and IRDA_HandleTypeDef::RxXferSize.

void HAL_IRDA_RxCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Transfer completed callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1558 of file stm32f3xx_hal_irda.c.

Referenced by IRDA_DMAReceiveCplt(), and IRDA_Receive_IT().

void HAL_IRDA_RxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Half Transfer complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1574 of file stm32f3xx_hal_irda.c.

Referenced by IRDA_DMAReceiveHalfCplt().

HAL_StatusTypeDef HAL_IRDA_Transmit | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer.
Size | Amount of data to be sent.
Timeout | Specify timeout value.
Return values:
HAL status

Definition at line 476 of file stm32f3xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_FLAG_TC, IRDA_FLAG_TXE, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::TxXferCount, IRDA_HandleTypeDef::TxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Transmit_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Return values:
HAL status

Definition at line 713 of file stm32f3xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, assert_param, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_CLEAR_TCF, IRDA_DMAError(), IRDA_DMATransmitCplt(), IRDA_DMATransmitHalfCplt(), IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::TxXferCount, IRDA_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Transmit_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer.
Size | Amount of data to be sent.
Return values:
HAL status

Definition at line 622 of file stm32f3xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Instance, IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::TxXferCount, and IRDA_HandleTypeDef::TxXferSize.

void HAL_IRDA_TxCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Transfer completed callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1526 of file stm32f3xx_hal_irda.c.

Referenced by IRDA_DMATransmitCplt(), and IRDA_EndTransmit_IT().

void HAL_IRDA_TxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Half Transfer completed callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1542 of file stm32f3xx_hal_irda.c.

Referenced by IRDA_DMATransmitHalfCplt().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
IRDA Exported Functions

IRDA State and Errors functions. More...

Functions

HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

IRDA State and Errors functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of IrDA
    communication process and also return Peripheral Errors occurred during communication process
     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
         of the IRDA peripheral handle.
     (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
         communication.

Function Documentation

uint32_t HAL_IRDA_GetError ( IRDA_HandleTypeDef * hirda )

Return the IRDA handle error code.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
IRDA Error Code

Definition at line 1693 of file stm32f3xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode.

HAL_IRDA_StateTypeDef HAL_IRDA_GetState ( IRDA_HandleTypeDef * hirda )

Return the IRDA handle state.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL state

Definition at line 1677 of file stm32f3xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, and IRDA_HandleTypeDef::RxState.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA Private Functions

Functions
IRDA Private Functions
IRDA

Functions

static HAL_StatusTypeDef | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configure the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_CheckIdleState (IRDA_HandleTypeDef *hirda)
Check the IRDA Idle State.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle IRDA Communication Timeout.
static void | IRDA_EndTxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
static void | IRDA_EndRxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static void | IRDA_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | IRDA_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | IRDA_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | IRDA_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | IRDA_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static HAL_StatusTypeDef | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in interrupt mode.
static HAL_StatusTypeDef | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receive an amount of data in interrupt mode.

Function Documentation

static HAL_StatusTypeDef IRDA_CheckIdleState ( IRDA_HandleTypeDef * hirda ) [static]

Check the IRDA Idle State.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1779 of file stm32f3xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Instance, IRDA_TEACK_REACK_TIMEOUT, IRDA_WaitOnFlagUntilTimeout(), and IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_Init().

static void IRDA_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2020 of file stm32f3xx_hal_irda.c.

References HAL_IRDA_ErrorCallback(), __DMA_HandleTypeDef::Parent, IRDA_HandleTypeDef::RxXferCount, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_IRQHandler().

static void IRDA_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA communication error callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1990 of file stm32f3xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_DMA, HAL_IRDA_ErrorCallback(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Instance, IRDA_EndRxTransfer(), IRDA_EndTxTransfer(), __DMA_HandleTypeDef::Parent, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Receive_DMA(), and HAL_IRDA_Transmit_DMA().

static void IRDA_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1947 of file stm32f3xx_hal_irda.c.

References HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_READY, __DMA_HandleTypeDef::Instance, IRDA_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, IRDA_HandleTypeDef::RxState, and IRDA_HandleTypeDef::RxXferCount.

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMAReceiveHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process half complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1977 of file stm32f3xx_hal_irda.c.

References HAL_IRDA_RxHalfCpltCallback(), and __DMA_HandleTypeDef::Parent.

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2079 of file stm32f3xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __DMA_HandleTypeDef::Parent, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_IRDA_Abort_IT().

static void IRDA_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2142 of file stm32f3xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_STATE_READY, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_HandleTypeDef::RxState, and IRDA_HandleTypeDef::RxXferCount.

Referenced by HAL_IRDA_AbortReceive_IT().

static void IRDA_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA transmit process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1904 of file stm32f3xx_hal_irda.c.

References HAL_IRDA_TxCpltCallback(), __DMA_HandleTypeDef::Instance, IRDA_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Transmit_DMA().

static void IRDA_DMATransmitHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA transmit process half complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1934 of file stm32f3xx_hal_irda.c.

References HAL_IRDA_TxHalfCpltCallback(), and __DMA_HandleTypeDef::Parent.

Referenced by HAL_IRDA_Transmit_DMA().

static void IRDA_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2037 of file stm32f3xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __DMA_HandleTypeDef::Parent, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_IRDA_Abort_IT().

static void IRDA_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2121 of file stm32f3xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_STATE_READY, __DMA_HandleTypeDef::Parent, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_AbortTransmit_IT().

static void IRDA_EndRxTransfer ( IRDA_HandleTypeDef * hirda ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1887 of file stm32f3xx_hal_irda.c.

References HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_DMAStop(), HAL_IRDA_IRQHandler(), and IRDA_DMAError().

static HAL_StatusTypeDef IRDA_EndTransmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 2212 of file stm32f3xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_READY, HAL_IRDA_TxCpltCallback(), and IRDA_HandleTypeDef::Instance.

Referenced by HAL_IRDA_IRQHandler().

static void IRDA_EndTxTransfer ( IRDA_HandleTypeDef * hirda ) [static]

End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1871 of file stm32f3xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_READY, and IRDA_HandleTypeDef::Instance.

Referenced by HAL_IRDA_DMAStop(), and IRDA_DMAError().

static HAL_StatusTypeDef IRDA_Receive_IT ( IRDA_HandleTypeDef * hirda ) [static]

Receive an amount of data in interrupt mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_IRDA_Receive_IT()
Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 2233 of file stm32f3xx_hal_irda.c.

References __HAL_IRDA_SEND_REQ, HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_PARITY_NONE, IRDA_RXDATA_FLUSH_REQUEST, IRDA_WORDLENGTH_9B, IRDA_HandleTypeDef::Mask, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_SetConfig ( IRDA_HandleTypeDef * hirda ) [static]

Configure the IRDA peripheral.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1716 of file stm32f3xx_hal_irda.c.

References assert_param, IRDA_InitTypeDef::BaudRate, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_CLOCKSOURCE_HSI, IRDA_CLOCKSOURCE_LSE, IRDA_CLOCKSOURCE_PCLK1, IRDA_CLOCKSOURCE_PCLK2, IRDA_CLOCKSOURCE_SYSCLK, IRDA_CLOCKSOURCE_UNDEFINED, IRDA_CR1_FIELDS, IRDA_GETCLOCKSOURCE, IS_IRDA_BAUDRATE, IS_IRDA_PARITY, IS_IRDA_POWERMODE, IS_IRDA_PRESCALER, IS_IRDA_TX_RX_MODE, IS_IRDA_WORD_LENGTH, LSE_VALUE, IRDA_InitTypeDef::Mode, IRDA_InitTypeDef::Parity, IRDA_InitTypeDef::PowerMode, IRDA_InitTypeDef::Prescaler, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_Init().

static HAL_StatusTypeDef IRDA_Transmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Send an amount of data in interrupt mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_IRDA_Transmit_IT().
Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 2166 of file stm32f3xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_PARITY_NONE, IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::TxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle IRDA Communication Timeout.

Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Flag | Specifies the IRDA flag to check.
Status | the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
Tickstart | Tick start value
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1837 of file stm32f3xx_hal_irda.c.

References __HAL_IRDA_GET_FLAG, IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), and IRDA_CheckIdleState().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA Exported Types

Data Structures | Enumerations
IRDA Exported Types
IRDA

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Enumerations

enum HAL_IRDA_StateTypeDef {
HAL_IRDA_STATE_RESET = 0x00U, HAL_IRDA_STATE_READY = 0x20U, HAL_IRDA_STATE_BUSY = 0x24U, HAL_IRDA_STATE_BUSY_TX = 0x21U,
HAL_IRDA_STATE_BUSY_RX = 0x22U, HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, HAL_IRDA_STATE_TIMEOUT = 0xA0U, HAL_IRDA_STATE_ERROR = 0xE0U
}
HAL IRDA State structures definition. More...
enum IRDA_ClockSourceTypeDef {
IRDA_CLOCKSOURCE_PCLK1 = 0x00U, IRDA_CLOCKSOURCE_PCLK2 = 0x01U, IRDA_CLOCKSOURCE_HSI = 0x02U, IRDA_CLOCKSOURCE_SYSCLK = 0x04U,
IRDA_CLOCKSOURCE_LSE = 0x08U, IRDA_CLOCKSOURCE_UNDEFINED = 0x10U
}
IRDA clock sources definition. More...
enum IRDA_ControlTypeDef {
IRDA_BAUDRATE = 0x00U, IRDA_PARITY = 0x01U, IRDA_WORDLENGTH = 0x02U, IRDA_MODE = 0x03U,
IRDA_PRESCALER = 0x04U, IRDA_POWERMODE = 0x05U
}
IRDA Configuration enumeration values definition. More...

Enumeration Type Documentation

enum HAL_IRDA_StateTypeDef

HAL IRDA State structures definition.

Note:
HAL IRDA State value is a combination of 2 different substates: gState and RxState.
  • gState contains IRDA state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized. HAL IRDA Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
Enumerator:
HAL_IRDA_STATE_RESET

Peripheral is not initialized Value is allowed for gState and RxState

HAL_IRDA_STATE_READY

Peripheral Initialized and ready for use Value is allowed for gState and RxState

HAL_IRDA_STATE_BUSY

an internal process is ongoing Value is allowed for gState only

HAL_IRDA_STATE_BUSY_TX

Data Transmission process is ongoing Value is allowed for gState only

HAL_IRDA_STATE_BUSY_RX

Data Reception process is ongoing Value is allowed for RxState only

HAL_IRDA_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

HAL_IRDA_STATE_TIMEOUT

Timeout state Value is allowed for gState only

HAL_IRDA_STATE_ERROR

Error Value is allowed for gState only

Definition at line 130 of file stm32f3xx_hal_irda.h.

enum IRDA_ClockSourceTypeDef

IRDA clock sources definition.

Enumerator:
IRDA_CLOCKSOURCE_PCLK1

PCLK1 clock source

IRDA_CLOCKSOURCE_PCLK2

PCLK2 clock source

IRDA_CLOCKSOURCE_HSI

HSI clock source

IRDA_CLOCKSOURCE_SYSCLK

SYSCLK clock source

IRDA_CLOCKSOURCE_LSE

LSE clock source

IRDA_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 154 of file stm32f3xx_hal_irda.h.

enum IRDA_ControlTypeDef

IRDA Configuration enumeration values definition.

Enumerator:
IRDA_BAUDRATE

IRDA Baud rate

IRDA_PARITY

IRDA frame parity

IRDA_WORDLENGTH

IRDA frame length

IRDA_MODE

IRDA communication mode

IRDA_PRESCALER

IRDA prescaling

IRDA_POWERMODE

IRDA power mode

Definition at line 208 of file stm32f3xx_hal_irda.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IRDA_InitTypeDef Struct Reference
IRDA Exported Types

IRDA Init Structure definition. More...

#include <stm32f3xx_hal_irda.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | Parity
uint32_t | Mode
uint8_t | Prescaler
uint16_t | PowerMode

Detailed Description

IRDA Init Structure definition.

Definition at line 64 of file stm32f3xx_hal_irda.h.

Field Documentation

uint32_t IRDA_InitTypeDef::BaudRate

This member configures the IRDA communication baud rate. The baud rate register is computed using the following formula: Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate)))

Definition at line 66 of file stm32f3xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of IRDA Transfer Mode

Definition at line 80 of file stm32f3xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of IRDA Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 73 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

uint16_t IRDA_InitTypeDef::PowerMode

Specifies the IRDA power mode. This parameter can be a value of IRDA Low Power

Definition at line 87 of file stm32f3xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint8_t IRDA_InitTypeDef::Prescaler

Specifies the Prescaler value for dividing the UART/USART source clock to achieve low-power frequency.

Note:
Prescaler value 0 is forbidden

Definition at line 83 of file stm32f3xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of IRDA Word Length

Definition at line 70 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_irda.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IRDA_HandleTypeDef Struct Reference
IRDA Exported Types

IRDA handle Structure definition. More...

#include <stm32f3xx_hal_irda.h>

Data Fields

USART_TypeDef * | Instance
IRDA_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_IRDA_StateTypeDef | gState
__IO HAL_IRDA_StateTypeDef | RxState
__IO uint32_t | ErrorCode

Detailed Description

IRDA handle Structure definition.

Definition at line 167 of file stm32f3xx_hal_irda.h.

Field Documentation

__IO uint32_t IRDA_HandleTypeDef::ErrorCode

IRDA Error code This parameter can be a value of IRDA Error

Definition at line 200 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_DeInit(), HAL_IRDA_GetError(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

__IO HAL_IRDA_StateTypeDef IRDA_HandleTypeDef::gState

IRDA state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_IRDA_StateTypeDef

Definition at line 193 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Init(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* IRDA_HandleTypeDef::hdmarx

IRDA Rx DMA Handle parameters

Definition at line 189 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_DMAStop(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_DMA(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

DMA_HandleTypeDef* IRDA_HandleTypeDef::hdmatx

IRDA Tx DMA Handle parameters

Definition at line 187 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DMAStop(), HAL_IRDA_Transmit_DMA(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

IRDA_InitTypeDef IRDA_HandleTypeDef::Init

IRDA communication parameters

Definition at line 171 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

USART_TypeDef* IRDA_HandleTypeDef::Instance

IRDA registers base address

Definition at line 169 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Init(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Receive_IT(), IRDA_SetConfig(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

HAL_LockTypeDef IRDA_HandleTypeDef::Lock

Locking object

Definition at line 191 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

uint16_t IRDA_HandleTypeDef::Mask

IRDA RX RDR register mask

Definition at line 185 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), and IRDA_Receive_IT().

uint8_t* IRDA_HandleTypeDef::pRxBuffPtr

Pointer to IRDA Rx transfer Buffer

Definition at line 179 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), and IRDA_Receive_IT().

uint8_t* IRDA_HandleTypeDef::pTxBuffPtr

Pointer to IRDA Tx transfer Buffer

Definition at line 173 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), and IRDA_Transmit_IT().

__IO HAL_IRDA_StateTypeDef IRDA_HandleTypeDef::RxState

IRDA state information related to Rx operations. This parameter can be a value of HAL_IRDA_StateTypeDef

Definition at line 197 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_EndRxTransfer(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

__IO uint16_t IRDA_HandleTypeDef::RxXferCount

IRDA Rx Transfer Counter

Definition at line 183 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_Receive(), HAL_IRDA_Receive_IT(), IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), and IRDA_Receive_IT().

uint16_t IRDA_HandleTypeDef::RxXferSize

IRDA Rx Transfer size

Definition at line 181 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), and HAL_IRDA_Receive_IT().

__IO uint16_t IRDA_HandleTypeDef::TxXferCount

IRDA Tx Transfer Counter

Definition at line 177 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), IRDA_DMATransmitCplt(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), and IRDA_Transmit_IT().

uint16_t IRDA_HandleTypeDef::TxXferSize

IRDA Tx Transfer size

Definition at line 175 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), and HAL_IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_irda.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA Error

Defines
IRDA Error
IRDA Exported Constants

Defines

#define | HAL_IRDA_ERROR_NONE (0x00000000U)
#define | HAL_IRDA_ERROR_PE (0x00000001U)
#define | HAL_IRDA_ERROR_NE (0x00000002U)
#define | HAL_IRDA_ERROR_FE (0x00000004U)
#define | HAL_IRDA_ERROR_ORE (0x00000008U)
#define | HAL_IRDA_ERROR_DMA (0x00000010U)
#define | HAL_IRDA_ERROR_BUSY (0x00000020U)

Define Documentation

#define HAL_IRDA_ERROR_BUSY (0x00000020U)

Busy Error

Definition at line 236 of file stm32f3xx_hal_irda.h.

#define HAL_IRDA_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 235 of file stm32f3xx_hal_irda.h.

Referenced by IRDA_DMAError().

#define HAL_IRDA_ERROR_FE (0x00000004U)

frame error

Definition at line 233 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_NE (0x00000002U)

Noise error

Definition at line 232 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_NONE (0x00000000U)

No error

Definition at line 230 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_DeInit(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

#define HAL_IRDA_ERROR_ORE (0x00000008U)

Overrun error

Definition at line 234 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_PE (0x00000001U)

Parity error

Definition at line 231 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA Parity

Defines
IRDA Parity
IRDA Exported Constants

Defines

#define | IRDA_PARITY_NONE (0x00000000U)
#define | IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Even parity

Definition at line 245 of file stm32f3xx_hal_irda.h.

#define IRDA_PARITY_NONE (0x00000000U)

No parity

Definition at line 244 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Odd parity

Definition at line 246 of file stm32f3xx_hal_irda.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA Transfer Mode

Defines
IRDA Transfer Mode
IRDA Exported Constants

Defines

#define | IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
#define | IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
#define | IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)

RX mode

Definition at line 254 of file stm32f3xx_hal_irda.h.

#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)

TX mode

Definition at line 255 of file stm32f3xx_hal_irda.h.

#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

RX and TX mode

Definition at line 256 of file stm32f3xx_hal_irda.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA Low Power

Defines
IRDA Low Power
IRDA Exported Constants

Defines

#define | IRDA_POWERMODE_NORMAL (0x00000000U)
#define | IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)

Define Documentation

#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)

IRDA low power mode

Definition at line 265 of file stm32f3xx_hal_irda.h.

#define IRDA_POWERMODE_NORMAL (0x00000000U)

IRDA normal power mode

Definition at line 264 of file stm32f3xx_hal_irda.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA State

Defines
IRDA State
IRDA Exported Constants

Defines

#define | IRDA_STATE_DISABLE (0x00000000U)
#define | IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)

Define Documentation

#define IRDA_STATE_DISABLE (0x00000000U)

IRDA disabled

Definition at line 273 of file stm32f3xx_hal_irda.h.

#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)

IRDA enabled

Definition at line 274 of file stm32f3xx_hal_irda.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA Mode

Defines
IRDA Mode
IRDA Exported Constants

Defines

#define | IRDA_MODE_DISABLE (0x00000000U)
#define | IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)

Define Documentation

#define IRDA_MODE_DISABLE (0x00000000U)

Associated UART disabled in IRDA mode

Definition at line 282 of file stm32f3xx_hal_irda.h.

#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)

Associated UART enabled in IRDA mode

Definition at line 283 of file stm32f3xx_hal_irda.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA One Bit Sampling

Defines
IRDA One Bit Sampling
IRDA Exported Constants

Defines

#define | IRDA_ONE_BIT_SAMPLE_DISABLE (0x00000000U)
#define | IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

Define Documentation

#define IRDA_ONE_BIT_SAMPLE_DISABLE (0x00000000U)

One-bit sampling disabled

Definition at line 291 of file stm32f3xx_hal_irda.h.

#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

One-bit sampling enabled

Definition at line 292 of file stm32f3xx_hal_irda.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA DMA Tx

Defines
IRDA DMA Tx
IRDA Exported Constants

Defines

#define | IRDA_DMA_TX_DISABLE (0x00000000U)
#define | IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)

Define Documentation

#define IRDA_DMA_TX_DISABLE (0x00000000U)

IRDA DMA TX disabled

Definition at line 300 of file stm32f3xx_hal_irda.h.

#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)

IRDA DMA TX enabled

Definition at line 301 of file stm32f3xx_hal_irda.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA DMA Rx

Defines
IRDA DMA Rx
IRDA Exported Constants

Defines

#define | IRDA_DMA_RX_DISABLE (0x00000000U)
#define | IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)

Define Documentation

#define IRDA_DMA_RX_DISABLE (0x00000000U)

IRDA DMA RX disabled

Definition at line 309 of file stm32f3xx_hal_irda.h.

#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)

IRDA DMA RX enabled

Definition at line 310 of file stm32f3xx_hal_irda.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA Request Parameters

Defines
IRDA Request Parameters
IRDA Exported Constants

Defines

#define | IRDA_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ)
#define | IRDA_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | IRDA_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Define Documentation

#define IRDA_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ)

Auto-Baud Rate Request

Definition at line 318 of file stm32f3xx_hal_irda.h.

#define IRDA_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)

Receive Data flush Request

Definition at line 319 of file stm32f3xx_hal_irda.h.

Referenced by IRDA_Receive_IT().

#define IRDA_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Transmit data flush Request

Definition at line 320 of file stm32f3xx_hal_irda.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA Flags

Defines
IRDA Flags
IRDA Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | IRDA_FLAG_REACK (0x00400000U)
#define | IRDA_FLAG_TEACK (0x00200000U)
#define | IRDA_FLAG_BUSY (0x00010000U)
#define | IRDA_FLAG_ABRF (0x00008000U)
#define | IRDA_FLAG_ABRE (0x00004000U)
#define | IRDA_FLAG_TXE (0x00000080U)
#define | IRDA_FLAG_TC (0x00000040U)
#define | IRDA_FLAG_RXNE (0x00000020U)
#define | IRDA_FLAG_ORE (0x00000008U)
#define | IRDA_FLAG_NE (0x00000004U)
#define | IRDA_FLAG_FE (0x00000002U)
#define | IRDA_FLAG_PE (0x00000001U)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define IRDA_FLAG_ABRE (0x00004000U)

IRDA Auto baud rate error

Definition at line 334 of file stm32f3xx_hal_irda.h.

#define IRDA_FLAG_ABRF (0x00008000U)

IRDA Auto baud rate flag

Definition at line 333 of file stm32f3xx_hal_irda.h.

#define IRDA_FLAG_BUSY (0x00010000U)

IRDA Busy flag

Definition at line 332 of file stm32f3xx_hal_irda.h.

#define IRDA_FLAG_FE (0x00000002U)

IRDA Framing error

Definition at line 340 of file stm32f3xx_hal_irda.h.

#define IRDA_FLAG_NE (0x00000004U)

IRDA Noise error

Definition at line 339 of file stm32f3xx_hal_irda.h.

#define IRDA_FLAG_ORE (0x00000008U)

IRDA Overrun error

Definition at line 338 of file stm32f3xx_hal_irda.h.

#define IRDA_FLAG_PE (0x00000001U)

IRDA Parity error

Definition at line 341 of file stm32f3xx_hal_irda.h.

#define IRDA_FLAG_REACK (0x00400000U)

IRDA Receive enable acknowledge flag

Definition at line 330 of file stm32f3xx_hal_irda.h.

#define IRDA_FLAG_RXNE (0x00000020U)

IRDA Read data register not empty

Definition at line 337 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Receive().

#define IRDA_FLAG_TC (0x00000040U)

IRDA Transmission complete

Definition at line 336 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit().

#define IRDA_FLAG_TEACK (0x00200000U)

IRDA Transmit enable acknowledge flag

Definition at line 331 of file stm32f3xx_hal_irda.h.

#define IRDA_FLAG_TXE (0x00000080U)

IRDA Transmit data register empty

Definition at line 335 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA Interrupts Definition

Defines
IRDA Interrupts Definition
IRDA Exported Constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | IRDA_IT_PE ((uint16_t)0x0028U)
#define | IRDA_IT_TXE ((uint16_t)0x0727U)
#define | IRDA_IT_TC ((uint16_t)0x0626U)
#define | IRDA_IT_RXNE ((uint16_t)0x0525U)
#define | IRDA_IT_IDLE ((uint16_t)0x0424U)
#define | IRDA_IT_ERR ((uint16_t)0x0060U)
#define | IRDA_IT_ORE ((uint16_t)0x0300U)
#define | IRDA_IT_NE ((uint16_t)0x0200U)
#define | IRDA_IT_FE ((uint16_t)0x0100U)

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define IRDA_IT_ERR ((uint16_t)0x0060U)

IRDA Error interruption

Definition at line 361 of file stm32f3xx_hal_irda.h.

#define IRDA_IT_FE ((uint16_t)0x0100U)

IRDA Frame error interruption

Definition at line 364 of file stm32f3xx_hal_irda.h.

#define IRDA_IT_IDLE ((uint16_t)0x0424U)

IRDA Idle interruption

Definition at line 360 of file stm32f3xx_hal_irda.h.

#define IRDA_IT_NE ((uint16_t)0x0200U)

IRDA Noise error interruption

Definition at line 363 of file stm32f3xx_hal_irda.h.

#define IRDA_IT_ORE ((uint16_t)0x0300U)

IRDA Overrun error interruption

Definition at line 362 of file stm32f3xx_hal_irda.h.

#define IRDA_IT_PE ((uint16_t)0x0028U)

IRDA Parity error interruption

Definition at line 356 of file stm32f3xx_hal_irda.h.

#define IRDA_IT_RXNE ((uint16_t)0x0525U)

IRDA Read data register not empty interruption

Definition at line 359 of file stm32f3xx_hal_irda.h.

#define IRDA_IT_TC ((uint16_t)0x0626U)

IRDA Transmission complete interruption

Definition at line 358 of file stm32f3xx_hal_irda.h.

#define IRDA_IT_TXE ((uint16_t)0x0727U)

IRDA Transmit data register empty interruption

Definition at line 357 of file stm32f3xx_hal_irda.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA Interruption Clear Flags

Defines
IRDA Interruption Clear Flags
IRDA Exported Constants

Defines

#define | IRDA_CLEAR_PEF USART_ICR_PECF
#define | IRDA_CLEAR_FEF USART_ICR_FECF
#define | IRDA_CLEAR_NEF USART_ICR_NCF
#define | IRDA_CLEAR_OREF USART_ICR_ORECF
#define | IRDA_CLEAR_IDLEF USART_ICR_IDLECF
#define | IRDA_CLEAR_TCF USART_ICR_TCCF

Define Documentation

#define IRDA_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 373 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 376 of file stm32f3xx_hal_irda.h.

#define IRDA_CLEAR_NEF USART_ICR_NCF

Noise detected Clear Flag

Definition at line 374 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 375 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 372 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 377 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA interruptions flags mask

Defines
IRDA interruptions flags mask
IRDA Exported Constants

Defines

#define IRDA_IT_MASK ((uint16_t)0x001FU)

Define Documentation

#define IRDA_IT_MASK ((uint16_t)0x001FU)

IRDA Interruptions flags mask

Definition at line 385 of file stm32f3xx_hal_irda.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA Exported Macros

Defines
IRDA Exported Macros
IRDA

Defines

#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle state.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)
Flush the IRDA DR register.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified IRDA interrupt source is enabled or not.
#define | __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
#define | __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific IRDA request flag.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the IRDA one bit sample method.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the IRDA one bit sample method.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.

Define Documentation

#define __HAL_IRDA_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)

Clear the IRDA FE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 444 of file stm32f3xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified IRDA pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • IRDA_CLEAR_PEF
  • IRDA_CLEAR_FEF
  • IRDA_CLEAR_NEF
  • IRDA_CLEAR_OREF
  • IRDA_CLEAR_TCF
  • IRDA_CLEAR_IDLEF
Return values:
None

Definition at line 431 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_Transmit_DMA(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define __HAL_IRDA_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)

Clear the IRDA IDLE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 462 of file stm32f3xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified IRDA ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • IRDA_CLEAR_PEF Parity Error Clear Flag
  • IRDA_CLEAR_FEF Framing Error Clear Flag
  • IRDA_CLEAR_NEF Noise detected Clear Flag
  • IRDA_CLEAR_OREF OverRun Error Clear Flag
  • IRDA_CLEAR_TCF Transmission Complete Clear Flag
Return values:
None

Definition at line 562 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define __HAL_IRDA_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)

Clear the IRDA NE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 450 of file stm32f3xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)

Clear the IRDA ORE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 456 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_DMAResume().

#define __HAL_IRDA_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)

Clear the IRDA PE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 437 of file stm32f3xx_hal_irda.h.

#define __HAL_IRDA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 599 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_Init().

#define __HAL_IRDA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))

Disable the specified IRDA interrupt.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to disable. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_PE Parity Error interrupt
  • IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 513 of file stm32f3xx_hal_irda.h.

#define __HAL_IRDA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 593 of file stm32f3xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

#define __HAL_IRDA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))

Enable the specified IRDA interrupt.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to enable. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_PE Parity Error interrupt
  • IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 497 of file stm32f3xx_hal_irda.h.

#define __HAL_IRDA_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                                                                    \
         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
      } while(0U)

Flush the IRDA DR register.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 413 of file stm32f3xx_hal_irda.h.

#define __HAL_IRDA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified IRDA flag is set or not.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • IRDA_FLAG_REACK Receive enable acknowledge flag
  • IRDA_FLAG_TEACK Transmit enable acknowledge flag
  • IRDA_FLAG_BUSY Busy flag
  • IRDA_FLAG_ABRF Auto Baud rate detection flag
  • IRDA_FLAG_ABRE Auto Baud rate detection error flag
  • IRDA_FLAG_TXE Transmit data register empty flag
  • IRDA_FLAG_TC Transmission Complete flag
  • IRDA_FLAG_RXNE Receive data register not empty flag
  • IRDA_FLAG_ORE OverRun Error flag
  • IRDA_FLAG_NE Noise Error flag
  • IRDA_FLAG_FE Framing Error flag
  • IRDA_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 482 of file stm32f3xx_hal_irda.h.

Referenced by IRDA_WaitOnFlagUntilTimeout().

#define __HAL_IRDA_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))

Check whether the specified IRDA interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__IT__ specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_ORE OverRun Error interrupt
  • IRDA_IT_NE Noise Error interrupt
  • IRDA_IT_FE Framing Error interrupt
  • IRDA_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 532 of file stm32f3xx_hal_irda.h.

#define __HAL_IRDA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))

Check whether the specified IRDA interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__IT__ specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_ERR Framing, overrun or noise error interrupt
  • IRDA_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 546 of file stm32f3xx_hal_irda.h.

#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the IRDA one bit sample method.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 587 of file stm32f3xx_hal_irda.h.

#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the IRDA one bit sample method.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 581 of file stm32f3xx_hal_irda.h.

#define __HAL_IRDA_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
                                                     } while(0U)

Reset IRDA handle state.

Parameters:
__HANDLE__ IRDA handle.
Return values:
None

Definition at line 404 of file stm32f3xx_hal_irda.h.

#define __HAL_IRDA_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific IRDA request flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__REQ__ specifies the request flag to set This parameter can be one of the following values:
  • IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
  • IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 575 of file stm32f3xx_hal_irda.h.

Referenced by IRDA_Receive_IT().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA Private Macros

Defines
IRDA Private Macros
IRDA

Defines

#define | IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
Ensure that IRDA Baud rate is less or equal to maximum value.
#define | IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
Ensure that IRDA prescaler value is strictly larger than 0.
#define | IS_IRDA_PARITY(__PARITY__)
Ensure that IRDA frame parity is valid.
#define | IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that IRDA communication mode is valid.
#define | IS_IRDA_POWERMODE(__MODE__)
Ensure that IRDA power mode is valid.
#define | IS_IRDA_STATE(__STATE__)
Ensure that IRDA state is valid.
#define | IS_IRDA_MODE(__MODE__)
Ensure that IRDA associated UART/USART mode is valid.
#define | IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that IRDA sampling rate is valid.
#define | IS_IRDA_DMA_TX(__DMATX__)
Ensure that IRDA DMA TX mode is valid.
#define | IS_IRDA_DMA_RX(__DMARX__)
Ensure that IRDA DMA RX mode is valid.
#define | IS_IRDA_REQUEST_PARAMETER(__PARAM__)
Ensure that IRDA request is valid.

Define Documentation

#define IS_IRDA_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 115201U)

Ensure that IRDA Baud rate is less or equal to maximum value.

Parameters:
__BAUDRATE__ specifies the IRDA Baudrate set by the user.
Return values:
True or False

Definition at line 614 of file stm32f3xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_DMA_RX ( __DMARX__ )
Value:
(((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
                                   ((__DMARX__) == IRDA_DMA_RX_ENABLE))

Ensure that IRDA DMA RX mode is valid.

Parameters:
__DMARX__ IRDA DMA RX mode.
Return values:
SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)

Definition at line 683 of file stm32f3xx_hal_irda.h.

#define IS_IRDA_DMA_TX ( __DMATX__ )
Value:
(((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
                                       ((__DMATX__) == IRDA_DMA_TX_ENABLE))

Ensure that IRDA DMA TX mode is valid.

Parameters:
__DMATX__ IRDA DMA TX mode.
Return values:
SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)

Definition at line 675 of file stm32f3xx_hal_irda.h.

#define IS_IRDA_MODE ( __MODE__ )
Value:
(((__MODE__) == IRDA_MODE_DISABLE) || \
                                 ((__MODE__) == IRDA_MODE_ENABLE))

Ensure that IRDA associated UART/USART mode is valid.

Parameters:
__MODE__ IRDA associated UART/USART mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 659 of file stm32f3xx_hal_irda.h.

#define IS_IRDA_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
                                                 ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))

Ensure that IRDA sampling rate is valid.

Parameters:
__ONEBIT__ IRDA sampling rate.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 667 of file stm32f3xx_hal_irda.h.

#define IS_IRDA_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == IRDA_PARITY_NONE) || \
                                    ((__PARITY__) == IRDA_PARITY_EVEN) || \
                                    ((__PARITY__) == IRDA_PARITY_ODD))

Ensure that IRDA frame parity is valid.

Parameters:
__PARITY__ IRDA frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 627 of file stm32f3xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_POWERMODE ( __MODE__ )
Value:
(((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
                                     ((__MODE__) == IRDA_POWERMODE_NORMAL))

Ensure that IRDA power mode is valid.

Parameters:
__MODE__ IRDA power mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 643 of file stm32f3xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_PRESCALER ( __PRESCALER__ ) ((__PRESCALER__) > 0U)

Ensure that IRDA prescaler value is strictly larger than 0.

Parameters:
__PRESCALER__ specifies the IRDA prescaler value set by the user.
Return values:
True or False

Definition at line 620 of file stm32f3xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
                                              ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
                                              ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))

Ensure that IRDA request is valid.

Parameters:
__PARAM__ IRDA request.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 691 of file stm32f3xx_hal_irda.h.

#define IS_IRDA_STATE ( __STATE__ )
Value:
(((__STATE__) == IRDA_STATE_DISABLE) || \
                                  ((__STATE__) == IRDA_STATE_ENABLE))

Ensure that IRDA state is valid.

Parameters:
__STATE__ IRDA state mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 651 of file stm32f3xx_hal_irda.h.

#define IS_IRDA_TX_RX_MODE ( __MODE__ ) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that IRDA communication mode is valid.

Parameters:
__MODE__ IRDA communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 636 of file stm32f3xx_hal_irda.h.

Referenced by IRDA_SetConfig().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IWDG Private Defines

Defines
IWDG Private Defines
IWDG

Defines

#define HAL_IWDG_DEFAULT_TIMEOUT 48u

Define Documentation

#define HAL_IWDG_DEFAULT_TIMEOUT 48u

Definition at line 130 of file stm32f3xx_hal_iwdg.c.

Referenced by HAL_IWDG_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_InitTypeDef Struct Reference
IWDG Exported Types

IWDG Init structure definition. More...

#include <stm32f3xx_hal_iwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Reload
uint32_t | Window

Detailed Description

IWDG Init structure definition.

Definition at line 63 of file stm32f3xx_hal_iwdg.h.

Field Documentation

uint32_t IWDG_InitTypeDef::Prescaler

Select the prescaler of the IWDG. This parameter can be a value of IWDG Prescaler

Definition at line 65 of file stm32f3xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Reload

Specifies the IWDG down-counter reload value. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFFU

Definition at line 68 of file stm32f3xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Window

Specifies the window value to be compared to the down-counter. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFFU

Definition at line 71 of file stm32f3xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_iwdg.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_HandleTypeDef Struct Reference
IWDG Exported Types

IWDG Handle Structure definition. More...

#include <stm32f3xx_hal_iwdg.h>

Data Fields

IWDG_TypeDef * Instance
IWDG_InitTypeDef Init

Detailed Description

IWDG Handle Structure definition.

Definition at line 79 of file stm32f3xx_hal_iwdg.h.

Field Documentation

IWDG_InitTypeDef IWDG_HandleTypeDef::Init

IWDG required parameters

Definition at line 83 of file stm32f3xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

IWDG_TypeDef* IWDG_HandleTypeDef::Instance

Register base address

Definition at line 81 of file stm32f3xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_iwdg.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IWDG Prescaler

Defines
IWDG Prescaler
IWDG Exported Constants

Defines

#define | IWDG_PRESCALER_4 0x00000000u
#define | IWDG_PRESCALER_8 IWDG_PR_PR_0
#define | IWDG_PRESCALER_16 IWDG_PR_PR_1
#define | IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_64 IWDG_PR_PR_2
#define | IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Define Documentation

#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)

IWDG prescaler set to 128U

Definition at line 104 of file stm32f3xx_hal_iwdg.h.

#define IWDG_PRESCALER_16 IWDG_PR_PR_1

IWDG prescaler set to 16

Definition at line 101 of file stm32f3xx_hal_iwdg.h.

#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

IWDG prescaler set to 256U

Definition at line 105 of file stm32f3xx_hal_iwdg.h.

#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)

IWDG prescaler set to 32

Definition at line 102 of file stm32f3xx_hal_iwdg.h.

#define IWDG_PRESCALER_4 0x00000000u

IWDG prescaler set to 4

Definition at line 99 of file stm32f3xx_hal_iwdg.h.

#define IWDG_PRESCALER_64 IWDG_PR_PR_2

IWDG prescaler set to 64

Definition at line 103 of file stm32f3xx_hal_iwdg.h.

#define IWDG_PRESCALER_8 IWDG_PR_PR_0

IWDG prescaler set to 8

Definition at line 100 of file stm32f3xx_hal_iwdg.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IWDG Window option

Defines
IWDG Window option
IWDG Exported Constants

Defines

#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN

Define Documentation

#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN

Definition at line 113 of file stm32f3xx_hal_iwdg.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IWDG Exported Macros

Defines
IWDG Exported Macros
IWDG

Defines

#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enable the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).

Define Documentation

#define __HAL_IWDG_RELOAD_COUNTER ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)

Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 140 of file stm32f3xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init(), and HAL_IWDG_Refresh().

#define __HAL_IWDG_START ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)

Enable the IWDG peripheral.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 132 of file stm32f3xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and Start functions

Functions
Initialization and Start functions
IWDG Exported Functions

Initialization and Start functions. More...

Functions

HAL_StatusTypeDef HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.

Detailed Description

Initialization and Start functions.

 ===============================================================================
          ##### Initialization and Start functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Initialize the IWDG according to the specified parameters in the
          IWDG_InitTypeDef of associated handle.
      (+) Manage Window option.
      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
          is reloaded in order to exit function with correct time base.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Init ( IWDG_HandleTypeDef * hiwdg )

Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.

Before exiting function, watchdog is refreshed in order to have correct time base.

Parameters:
hiwdg pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 170 of file stm32f3xx_hal_iwdg.c.

References __HAL_IWDG_RELOAD_COUNTER, __HAL_IWDG_START, assert_param, HAL_GetTick(), HAL_IWDG_DEFAULT_TIMEOUT, IWDG_HandleTypeDef::Init, IWDG_HandleTypeDef::Instance, IS_IWDG_PRESCALER, IS_IWDG_RELOAD, IS_IWDG_WINDOW, IWDG_ENABLE_WRITE_ACCESS, IWDG_InitTypeDef::Prescaler, IWDG_InitTypeDef::Reload, and IWDG_InitTypeDef::Window.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IO operation functions

Functions
IO operation functions
IWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Refresh the IWDG.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Refresh ( IWDG_HandleTypeDef * hiwdg )

Refresh the IWDG.

Parameters:
hiwdg pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 254 of file stm32f3xx_hal_iwdg.c.

References __HAL_IWDG_RELOAD_COUNTER.

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STM32F373xC HAL User Manual: IWDG Private Constants

Defines
IWDG Private Constants
IWDG

Defines

#define | IWDG_KEY_RELOAD 0x0000AAAAu
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE 0x0000CCCCu
#define | IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u
#define | IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u

Define Documentation

#define IWDG_KEY_ENABLE 0x0000CCCCu

IWDG Peripheral Enable

Definition at line 181 of file stm32f3xx_hal_iwdg.h.

#define IWDG_KEY_RELOAD 0x0000AAAAu

IWDG Key Register BitMask.

IWDG Reload Counter Enable

Definition at line 180 of file stm32f3xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u

IWDG KR Write Access Disable

Definition at line 183 of file stm32f3xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u

IWDG KR Write Access Enable

Definition at line 182 of file stm32f3xx_hal_iwdg.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IWDG Private Macros

Defines
IWDG Private Macros
IWDG

Defines

#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
Check IWDG reload value.
#define | IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
Check IWDG window value.

Define Documentation

#define IS_IWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == IWDG_PRESCALER_4)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
                                               ((__PRESCALER__) == IWDG_PRESCALER_256))

Check IWDG prescaler value.

Parameters:
__PRESCALER__ IWDG prescaler value
Return values:
None

Definition at line 212 of file stm32f3xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_RELOAD ( __RELOAD__ ) ((__RELOAD__) <= IWDG_RLR_RL)

Check IWDG reload value.

Parameters:
__RELOAD__ IWDG reload value
Return values:
None

Definition at line 225 of file stm32f3xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_WINDOW ( __WINDOW__ ) ((__WINDOW__) <= IWDG_WINR_WIN)

Check IWDG window value.

Parameters:
__WINDOW__ IWDG window value
Return values:
None

Definition at line 232 of file stm32f3xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IWDG_DISABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)

Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 205 of file stm32f3xx_hal_iwdg.h.

#define IWDG_ENABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)

Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 198 of file stm32f3xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD Private Define

Defines
PCD Private Define
PCD

Defines

#define BTABLE_ADDRESS (0x000U)

Define Documentation

#define BTABLE_ADDRESS (0x000U)

Definition at line 97 of file stm32f3xx_hal_pcd.c.

Referenced by HAL_PCD_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD Private Functions

Functions
PCD Private Functions
PCD

Functions

static HAL_StatusTypeDef PCD_EP_ISR_Handler (PCD_HandleTypeDef *hpcd)
This function handles PCD Endpoint interrupt request.

Function Documentation

static HAL_StatusTypeDef PCD_EP_ISR_Handler ( PCD_HandleTypeDef * hpcd ) [static]

This function handles PCD Endpoint interrupt request.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 339 of file stm32f3xx_hal_pcd.c.

References PCD_EPTypeDef::doublebuffer, HAL_PCD_DataInStageCallback(), HAL_PCD_DataOutStageCallback(), HAL_PCD_EP_Receive(), HAL_PCD_EP_Transmit(), HAL_PCD_SetupStageCallback(), PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, PCD_EPTypeDef::maxpacket, PCD_EPTypeDef::num, PCD_HandleTypeDef::OUT_ep, PCD_CLEAR_RX_EP_CTR, PCD_CLEAR_TX_EP_CTR, PCD_ENDP0, PCD_EP_DBUF_IN, PCD_EP_DBUF_OUT, PCD_FreeUserBuffer, PCD_GET_ENDPOINT, PCD_GET_EP_DBUF0_CNT, PCD_GET_EP_DBUF1_CNT, PCD_GET_EP_RX_CNT, PCD_GET_EP_TX_CNT, PCD_ReadPMA(), PCD_SET_EP_RX_CNT, PCD_SET_EP_RX_STATUS, PCD_WritePMA(), PCD_EPTypeDef::pmaaddr0, PCD_EPTypeDef::pmaaddr1, PCD_EPTypeDef::pmaadress, PCD_HandleTypeDef::Setup, PCD_HandleTypeDef::USB_Address, PCD_EPTypeDef::xfer_buff, PCD_EPTypeDef::xfer_count, and PCD_EPTypeDef::xfer_len.

Referenced by HAL_PCD_IRQHandler().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
PCD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

Function Documentation

HAL_StatusTypeDef HAL_PCD_DeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes the PCD peripheral.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 219 of file stm32f3xx_hal_pcd.c.

References HAL_PCD_MspDeInit(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_RESET, HAL_PCD_Stop(), and PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_Init ( PCD_HandleTypeDef * hpcd )

Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and create the associated handle.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 138 of file stm32f3xx_hal_pcd.c.

References assert_param, BTABLE_ADDRESS, PCD_InitTypeDef::dev_endpoints, HAL_PCD_MspInit(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_READY, HAL_PCD_STATE_RESET, PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Init, PCD_HandleTypeDef::Instance, PCD_EPTypeDef::is_in, IS_PCD_ALL_INSTANCE, PCD_HandleTypeDef::Lock, PCD_EPTypeDef::maxpacket, PCD_EPTypeDef::num, PCD_HandleTypeDef::OUT_ep, PCD_EP_TYPE_CTRL, PCD_HandleTypeDef::State, PCD_EPTypeDef::type, PCD_HandleTypeDef::USB_Address, PCD_EPTypeDef::xfer_buff, and PCD_EPTypeDef::xfer_len.

void HAL_PCD_MspDeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes PCD MSP.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 260 of file stm32f3xx_hal_pcd.c.

Referenced by HAL_PCD_DeInit().

void HAL_PCD_MspInit ( PCD_HandleTypeDef * hpcd )

Initializes the PCD MSP.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 245 of file stm32f3xx_hal_pcd.c.

Referenced by HAL_PCD_Init().

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STM32F373xC HAL User Manual: IO operation functions

Functions
IO operation functions
PCD Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start the USB device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop the USB device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data out stage callbacks.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callbacks.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callbacks.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callbacks.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callbacks.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callbacks.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callbacks.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callbacks.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callbacks.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callbacks.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the PCD data
    transfers.

Function Documentation

void HAL_PCD_ConnectCallback ( PCD_HandleTypeDef * hpcd )

Connection event callbacks.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 767 of file stm32f3xx_hal_pcd.c.

void HAL_PCD_DataInStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data IN stage callbacks.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 643 of file stm32f3xx_hal_pcd.c.

Referenced by PCD_EP_ISR_Handler().

void HAL_PCD_DataOutStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data out stage callbacks.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 626 of file stm32f3xx_hal_pcd.c.

Referenced by PCD_EP_ISR_Handler().

void HAL_PCD_DisconnectCallback ( PCD_HandleTypeDef * hpcd )

Disconnection event callbacks.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 782 of file stm32f3xx_hal_pcd.c.

void HAL_PCD_IRQHandler ( PCD_HandleTypeDef * hpcd )

This function handles PCD interrupt request.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 556 of file stm32f3xx_hal_pcd.c.

References __HAL_PCD_CLEAR_FLAG, __HAL_PCD_GET_FLAG, HAL_PCD_ResetCallback(), HAL_PCD_ResumeCallback(), HAL_PCD_SetAddress(), HAL_PCD_SOFCallback(), HAL_PCD_SuspendCallback(), PCD_HandleTypeDef::Instance, and PCD_EP_ISR_Handler().

void HAL_PCD_ISOINIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO IN callbacks.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 751 of file stm32f3xx_hal_pcd.c.

void HAL_PCD_ISOOUTIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO OUT callbacks.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 734 of file stm32f3xx_hal_pcd.c.

void HAL_PCD_ResetCallback ( PCD_HandleTypeDef * hpcd )

USB Reset callbacks.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 688 of file stm32f3xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_ResumeCallback ( PCD_HandleTypeDef * hpcd )

Resume event callbacks.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 718 of file stm32f3xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_SetupStageCallback ( PCD_HandleTypeDef * hpcd )

Setup stage callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 658 of file stm32f3xx_hal_pcd.c.

Referenced by PCD_EP_ISR_Handler().

void HAL_PCD_SOFCallback ( PCD_HandleTypeDef * hpcd )

USB Start Of Frame callbacks.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 673 of file stm32f3xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

HAL_StatusTypeDef HAL_PCD_Start ( PCD_HandleTypeDef * hpcd )

Start the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 294 of file stm32f3xx_hal_pcd.c.

References HAL_PCDEx_SetConnectionState().

HAL_StatusTypeDef HAL_PCD_Stop ( PCD_HandleTypeDef * hpcd )

Stop the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 307 of file stm32f3xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

Referenced by HAL_PCD_DeInit().

void HAL_PCD_SuspendCallback ( PCD_HandleTypeDef * hpcd )

Suspend event callbacks.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 703 of file stm32f3xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCD Exported Functions | PCD

management functions More...

Functions

HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint16_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_ActiveRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_StatusTypeDef | HAL_PCD_DeActiveRemoteWakeup (PCD_HandleTypeDef *hpcd)

Detailed Description

management functions

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the PCD data
    transfers.

Function Documentation

HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1267 of file stm32f3xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup ( PCD_HandleTypeDef * hpcd )
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1278 of file stm32f3xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup ( PCD_HandleTypeDef * hpcd )
HAL_StatusTypeDef HAL_PCD_DevConnect ( PCD_HandleTypeDef * hpcd )

Connect the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 815 of file stm32f3xx_hal_pcd.c.

References HAL_PCDEx_SetConnectionState().

HAL_StatusTypeDef HAL_PCD_DevDisconnect ( PCD_HandleTypeDef * hpcd )

Disconnect the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 831 of file stm32f3xx_hal_pcd.c.

References HAL_PCDEx_SetConnectionState().

HAL_StatusTypeDef HAL_PCD_EP_Close | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Deactivate an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 979 of file stm32f3xx_hal_pcd.c.

References PCD_EPTypeDef::doublebuffer, PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, PCD_EPTypeDef::is_in, PCD_EPTypeDef::num, PCD_HandleTypeDef::OUT_ep, PCD_CLEAR_RX_DTOG, PCD_CLEAR_TX_DTOG, PCD_RX_DTOG, PCD_SET_EP_RX_STATUS, PCD_SET_EP_TX_STATUS, and PCD_TX_DTOG.

HAL_StatusTypeDef HAL_PCD_EP_ClrStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Clear a STALL condition over in an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1217 of file stm32f3xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, PCD_EPTypeDef::is_in, PCD_EPTypeDef::is_stall, PCD_EPTypeDef::num, PCD_HandleTypeDef::OUT_ep, PCD_CLEAR_RX_DTOG, PCD_CLEAR_TX_DTOG, PCD_SET_EP_RX_STATUS, and PCD_SET_EP_TX_STATUS.

HAL_StatusTypeDef HAL_PCD_EP_Flush | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Flush an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1257 of file stm32f3xx_hal_pcd.c.

uint16_t HAL_PCD_EP_GetRxCount | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Get Received Data Size.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
Data Size

Definition at line 1101 of file stm32f3xx_hal_pcd.c.

References PCD_HandleTypeDef::OUT_ep, and PCD_EPTypeDef::xfer_count.

HAL_StatusTypeDef HAL_PCD_EP_Open | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint16_t | ep_mps,
 |  | uint8_t | ep_type
 | ) |  |

Open and configure an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
ep_mps | endpoint max packet size
ep_type | endpoint type
Return values:
HAL status

Definition at line 873 of file stm32f3xx_hal_pcd.c.

References PCD_EPTypeDef::doublebuffer, PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, PCD_EPTypeDef::is_in, PCD_EPTypeDef::maxpacket, PCD_EPTypeDef::num, PCD_HandleTypeDef::OUT_ep, PCD_CLEAR_RX_DTOG, PCD_CLEAR_TX_DTOG, PCD_EP_TYPE_BULK, PCD_EP_TYPE_CTRL, PCD_EP_TYPE_INTR, PCD_EP_TYPE_ISOC, PCD_RX_DTOG, PCD_SET_EP_ADDRESS, PCD_SET_EP_DBUF, PCD_SET_EP_DBUF_ADDR, PCD_SET_EP_RX_ADDRESS, PCD_SET_EP_RX_CNT, PCD_SET_EP_RX_STATUS, PCD_SET_EP_TX_ADDRESS, PCD_SET_EP_TX_STATUS, PCD_SET_EPTYPE, PCD_TX_DTOG, PCD_EPTypeDef::pmaaddr0, PCD_EPTypeDef::pmaaddr1, PCD_EPTypeDef::pmaadress, and PCD_EPTypeDef::type.

HAL_StatusTypeDef HAL_PCD_EP_Receive | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Receive an amount of data.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
pBuf | pointer to the reception buffer
len | amount of data to be received
Return values:
HAL status

Definition at line 1052 of file stm32f3xx_hal_pcd.c.

References PCD_EPTypeDef::doublebuffer, PCD_HandleTypeDef::Instance, PCD_EPTypeDef::is_in, PCD_EPTypeDef::maxpacket, PCD_EPTypeDef::num, PCD_HandleTypeDef::OUT_ep, PCD_SET_EP_DBUF1_CNT, PCD_SET_EP_RX_CNT, PCD_SET_EP_RX_STATUS, PCD_EPTypeDef::xfer_buff, PCD_EPTypeDef::xfer_count, and PCD_EPTypeDef::xfer_len.

Referenced by PCD_EP_ISR_Handler().

HAL_StatusTypeDef HAL_PCD_EP_SetStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Set a STALL condition over an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1171 of file stm32f3xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, PCD_EPTypeDef::is_in, PCD_EPTypeDef::is_stall, PCD_EPTypeDef::num, PCD_HandleTypeDef::OUT_ep, PCD_SET_EP_RX_STATUS, PCD_SET_EP_TX_STATUS, and PCD_SET_EP_TXRX_STATUS.

HAL_StatusTypeDef HAL_PCD_EP_Transmit | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Send an amount of data.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
pBuf | pointer to the transmission buffer
len | amount of data to be sent
Return values:
HAL status

Definition at line 1113 of file stm32f3xx_hal_pcd.c.

References PCD_EPTypeDef::doublebuffer, PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, PCD_EPTypeDef::is_in, PCD_EPTypeDef::maxpacket, PCD_EPTypeDef::num, PCD_FreeUserBuffer, PCD_GET_ENDPOINT, PCD_SET_EP_TX_CNT, PCD_SET_EP_TX_STATUS, PCD_WritePMA(), PCD_EPTypeDef::pmaaddr0, PCD_EPTypeDef::pmaaddr1, PCD_EPTypeDef::pmaadress, PCD_EPTypeDef::xfer_buff, PCD_EPTypeDef::xfer_count, and PCD_EPTypeDef::xfer_len.

Referenced by PCD_EP_ISR_Handler().

HAL_StatusTypeDef HAL_PCD_SetAddress | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | address
 | ) |  |

Set the USB Device address.

Parameters:
hpcd | PCD handle
address | new device address
Return values:
HAL status

Definition at line 848 of file stm32f3xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::USB_Address.

Referenced by HAL_PCD_IRQHandler().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
PCD Exported Functions | PCD

Peripheral State functions. More...

Functions

PCD_StateTypeDef HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

PCD_StateTypeDef HAL_PCD_GetState ( PCD_HandleTypeDef * hpcd )

Return the PCD state.

Parameters:
hpcd PCD handle
Return values:
HAL state

Definition at line 1308 of file stm32f3xx_hal_pcd.c.

References PCD_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD Exported Types

Data Structures | Typedefs | Enumerations
PCD Exported Types
PCD

Data Structures

struct | PCD_InitTypeDef
PCD Initialization Structure definition. More...
struct | PCD_EPTypeDef
struct | PCD_HandleTypeDef
PCD Handle Structure definition. More...

Typedefs

typedef USB_TypeDef | PCD_TypeDef

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00U, HAL_PCD_STATE_READY = 0x01U, HAL_PCD_STATE_ERROR = 0x02U, HAL_PCD_STATE_BUSY = 0x03U,
HAL_PCD_STATE_TIMEOUT = 0x04U
}
PCD State structure definition. More...
enum | PCD_EP_DBUF_DIR { PCD_EP_DBUF_OUT, PCD_EP_DBUF_IN, PCD_EP_DBUF_ERR }
PCD double buffered endpoint direction. More...
enum | PCD_EP_BUF_NUM { PCD_EP_NOBUF, PCD_EP_BUF0, PCD_EP_BUF1 }
PCD endpoint buffer number. More...

Typedef Documentation

typedef USB_TypeDef PCD_TypeDef

Definition at line 170 of file stm32f3xx_hal_pcd.h.

Enumeration Type Documentation

enum PCD_EP_BUF_NUM

PCD endpoint buffer number.

Enumerator:
PCD_EP_NOBUF
PCD_EP_BUF0
PCD_EP_BUF1

Definition at line 90 of file stm32f3xx_hal_pcd.h.

enum PCD_EP_DBUF_DIR

PCD double buffered endpoint direction.

Enumerator:
PCD_EP_DBUF_OUT
PCD_EP_DBUF_IN
PCD_EP_DBUF_ERR

Definition at line 80 of file stm32f3xx_hal_pcd.h.

enum PCD_StateTypeDef

PCD State structure definition.

Enumerator:
HAL_PCD_STATE_RESET
HAL_PCD_STATE_READY
HAL_PCD_STATE_ERROR
HAL_PCD_STATE_BUSY
HAL_PCD_STATE_TIMEOUT

Definition at line 68 of file stm32f3xx_hal_pcd.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PCD_InitTypeDef Struct Reference
PCD Exported Types

PCD Initialization Structure definition. More...

#include <stm32f3xx_hal_pcd.h>

Data Fields

uint32_t | dev_endpoints
uint32_t | speed
uint32_t | ep0_mps
uint32_t | phy_itface
uint32_t | Sof_enable
uint32_t | low_power_enable
uint32_t | lpm_enable
uint32_t | battery_charging_enable

Detailed Description

PCD Initialization Structure definition.

Definition at line 100 of file stm32f3xx_hal_pcd.h.

Field Documentation

uint32_t PCD_InitTypeDef::battery_charging_enable

Enable or disable Battery charging. This parameter can be set to ENABLE or DISABLE

Definition at line 124 of file stm32f3xx_hal_pcd.h.

uint32_t PCD_InitTypeDef::dev_endpoints

Device Endpoints number. This parameter depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15

Definition at line 102 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_Init().

uint32_t PCD_InitTypeDef::ep0_mps

Set the Endpoint 0 Max Packet size. This parameter can be any value of PCD EP0 MPS

Definition at line 109 of file stm32f3xx_hal_pcd.h.

uint32_t PCD_InitTypeDef::low_power_enable

Enable or disable Low Power mode This parameter can be set to ENABLE or DISABLE

Definition at line 118 of file stm32f3xx_hal_pcd.h.

uint32_t PCD_InitTypeDef::lpm_enable

Enable or disable the Link Power Management . This parameter can be set to ENABLE or DISABLE

Definition at line 121 of file stm32f3xx_hal_pcd.h.

uint32_t PCD_InitTypeDef::phy_itface

Select the used PHY interface. This parameter can be any value of PCD Core PHY

Definition at line 112 of file stm32f3xx_hal_pcd.h.

uint32_t PCD_InitTypeDef::Sof_enable

Enable or disable the output of the SOF signal. This parameter can be set to ENABLE or DISABLE

Definition at line 115 of file stm32f3xx_hal_pcd.h.

uint32_t PCD_InitTypeDef::speed

USB Core speed. This parameter can be any value of PCD Core Speed

Definition at line 106 of file stm32f3xx_hal_pcd.h.

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_pcd.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD_EPTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PCD_EPTypeDef Struct Reference
PCD Exported Types

#include <stm32f3xx_hal_pcd.h>

Data Fields

uint8_t | num
uint8_t | is_in
uint8_t | is_stall
uint8_t | type
uint16_t | pmaadress
uint16_t | pmaaddr0
uint16_t | pmaaddr1
uint8_t | doublebuffer
uint32_t | maxpacket
uint8_t * | xfer_buff
uint32_t | xfer_len
uint32_t | xfer_count

Detailed Description

Definition at line 129 of file stm32f3xx_hal_pcd.h.

Field Documentation

uint8_t PCD_EPTypeDef::doublebuffer

Double buffer enable This parameter can be 0 or 1

Definition at line 155 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_Transmit(), HAL_PCDEx_PMAConfig(), and PCD_EP_ISR_Handler().

uint8_t PCD_EPTypeDef::is_in

Endpoint direction This parameter must be a number between Min_Data = 0 and Max_Data = 1

Definition at line 134 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), and HAL_PCD_Init().

uint8_t PCD_EPTypeDef::is_stall

Endpoint stall condition This parameter must be a number between Min_Data = 0 and Max_Data = 1

Definition at line 137 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_ClrStall(), and HAL_PCD_EP_SetStall().

uint32_t PCD_EPTypeDef::maxpacket

Endpoint Max packet size This parameter must be a number between Min_Data = 0 and Max_Data = 64KB

Definition at line 158 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), and PCD_EP_ISR_Handler().

uint8_t PCD_EPTypeDef::num

Endpoint number This parameter must be a number between Min_Data = 1 and Max_Data = 15

Definition at line 131 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), and PCD_EP_ISR_Handler().

uint16_t PCD_EPTypeDef::pmaaddr0

PMA Address0 This parameter can be any value between Min_addr = 0 and Max_addr = 1K

Definition at line 147 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Open(), HAL_PCD_EP_Transmit(), HAL_PCDEx_PMAConfig(), and PCD_EP_ISR_Handler().

uint16_t PCD_EPTypeDef::pmaaddr1

PMA Address1 This parameter can be any value between Min_addr = 0 and Max_addr = 1K

Definition at line 151 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Open(), HAL_PCD_EP_Transmit(), HAL_PCDEx_PMAConfig(), and PCD_EP_ISR_Handler().

uint16_t PCD_EPTypeDef::pmaadress

PMA Address This parameter can be any value between Min_addr = 0 and Max_addr = 1K

Definition at line 143 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Open(), HAL_PCD_EP_Transmit(), HAL_PCDEx_PMAConfig(), and PCD_EP_ISR_Handler().

uint8_t PCD_EPTypeDef::type

Endpoint type This parameter can be any value of PCD EP Type

Definition at line 140 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Open(), and HAL_PCD_Init().

uint8_t* PCD_EPTypeDef::xfer_buff

Pointer to transfer buffer

Definition at line 161 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Receive(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), and PCD_EP_ISR_Handler().

uint32_t PCD_EPTypeDef::xfer_count

Partial transfer length in case of multi packet transfer

Definition at line 166 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_GetRxCount(), HAL_PCD_EP_Receive(), HAL_PCD_EP_Transmit(), and PCD_EP_ISR_Handler().

uint32_t PCD_EPTypeDef::xfer_len

Current transfer length

Definition at line 164 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Receive(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), and PCD_EP_ISR_Handler().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_pcd.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PCD_HandleTypeDef Struct Reference
PCD Exported Types

PCD Handle Structure definition. More...

#include <stm32f3xx_hal_pcd.h>

Data Fields

PCD_TypeDef * Instance
PCD_InitTypeDef Init
__IO uint8_t | USB_Address
PCD_EPTypeDef | IN_ep [15]
PCD_EPTypeDef | OUT_ep [15]
HAL_LockTypeDef | Lock
__IO PCD_StateTypeDef | State
uint32_t | Setup [12]
void * | pData

Detailed Description

PCD Handle Structure definition.

Definition at line 175 of file stm32f3xx_hal_pcd.h.

Field Documentation

PCD_EPTypeDef PCD_HandleTypeDef::IN_ep[15]

IN endpoint parameters

Definition at line 180 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Open(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCDEx_PMAConfig(), and PCD_EP_ISR_Handler().

PCD_InitTypeDef PCD_HandleTypeDef::Init

PCD required parameters

Definition at line 178 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_Init().

PCD_TypeDef* PCD_HandleTypeDef::Instance

Register base address

Definition at line 177 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_ActivateRemoteWakeup(), HAL_PCD_DeActivateRemoteWakeup(), HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_SetAddress(), HAL_PCD_Stop(), and PCD_EP_ISR_Handler().

HAL_LockTypeDef PCD_HandleTypeDef::Lock

PCD peripheral status

Definition at line 182 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_Init().

PCD_EPTypeDef PCD_HandleTypeDef::OUT_ep[15]

OUT endpoint parameters

Definition at line 181 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_GetRxCount(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_Init(), HAL_PCDEx_PMAConfig(), and PCD_EP_ISR_Handler().

void* PCD_HandleTypeDef::pData

Pointer to upper stack Handler

Definition at line 185 of file stm32f3xx_hal_pcd.h.

uint32_t PCD_HandleTypeDef::Setup[12]

Setup packet buffer

Definition at line 184 of file stm32f3xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

__IO PCD_StateTypeDef PCD_HandleTypeDef::State

PCD communication state

Definition at line 183 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_DeInit(), HAL_PCD_GetState(), and HAL_PCD_Init().

__IO uint8_t PCD_HandleTypeDef::USB_Address

USB Address

Definition at line 179 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_SetAddress(), and PCD_EP_ISR_Handler().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_pcd.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD Core Speed

Defines
PCD Core Speed
PCD Exported Constants

Defines

#define | PCD_SPEED_HIGH 0U /* Not Supported */
#define | PCD_SPEED_FULL 2U

Define Documentation

#define PCD_SPEED_FULL 2U

Definition at line 205 of file stm32f3xx_hal_pcd.h.

#define PCD_SPEED_HIGH 0U /* Not Supported */

Definition at line 204 of file stm32f3xx_hal_pcd.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD Core PHY

Defines
PCD Core PHY
PCD Exported Constants

Defines

#define PCD_PHY_EMBEDDED 2U

Define Documentation

#define PCD_PHY_EMBEDDED 2U

Definition at line 213 of file stm32f3xx_hal_pcd.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD Exported Macros

Defines
PCD Exported Macros
PCD

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) = (uint16_t)(~(__INTERRUPT__))))
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
#define | __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
#define | __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__))
#define | __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
#define | __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE()
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_PCD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->ISTR) = (uint16_t)(~(__INTERRUPT__))))

Definition at line 227 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_PCD_GET_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))

Definition at line 226 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_USB_EXTI_GENERATE_SWIT ( __EXTILINE__ ) (EXTI->SWIER |= (__EXTILINE__))

Definition at line 231 of file stm32f3xx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG ( ) EXTI->PR = USB_WAKEUP_EXTI_LINE

Definition at line 234 of file stm32f3xx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT ( ) EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)

Definition at line 230 of file stm32f3xx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE ( )
Value:
do {\
                                                     EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE);\
                                                     EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE);\
                                                   } while(0U)

Definition at line 241 of file stm32f3xx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT ( ) EXTI->IMR |= USB_WAKEUP_EXTI_LINE

Definition at line 229 of file stm32f3xx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE ( )
Value:
do {\
                                                     EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE);\
                                                     EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;\
                                                   } while(0U)

Definition at line 236 of file stm32f3xx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {\
                                                     EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE);\
                                                     EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE);\
                                                     EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;\
                                                     EXTI->FTSR |= USB_WAKEUP_EXTI_LINE;\
                                                   } while(0U)

Definition at line 246 of file stm32f3xx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_GET_FLAG ( ) EXTI->PR & (USB_WAKEUP_EXTI_LINE)

Definition at line 233 of file stm32f3xx_hal_pcd.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USB EXTI line interrupt

Defines
USB EXTI line interrupt
PCD Private Constants

Defines

#define USB_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR_MR18)

Define Documentation

#define USB_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR_MR18)

External interrupt line 18 Connected to the USB FS EXTI Line

Definition at line 338 of file stm32f3xx_hal_pcd.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD EP0 MPS

Defines
PCD EP0 MPS
PCD Private Constants

Defines

#define | DEP0CTL_MPS_64 0U
#define | DEP0CTL_MPS_32 1U
#define | DEP0CTL_MPS_16 2U
#define | DEP0CTL_MPS_8 3U
#define | PCD_EP0MPS_64 DEP0CTL_MPS_64
#define | PCD_EP0MPS_32 DEP0CTL_MPS_32
#define | PCD_EP0MPS_16 DEP0CTL_MPS_16
#define | PCD_EP0MPS_08 DEP0CTL_MPS_8

Define Documentation

#define DEP0CTL_MPS_16 2U

Definition at line 348 of file stm32f3xx_hal_pcd.h.

#define DEP0CTL_MPS_32 1U

Definition at line 347 of file stm32f3xx_hal_pcd.h.

#define DEP0CTL_MPS_64 0U

Definition at line 346 of file stm32f3xx_hal_pcd.h.

#define DEP0CTL_MPS_8 3U

Definition at line 349 of file stm32f3xx_hal_pcd.h.

#define PCD_EP0MPS_08 DEP0CTL_MPS_8

Definition at line 354 of file stm32f3xx_hal_pcd.h.

#define PCD_EP0MPS_16 DEP0CTL_MPS_16

Definition at line 353 of file stm32f3xx_hal_pcd.h.

#define PCD_EP0MPS_32 DEP0CTL_MPS_32

Definition at line 352 of file stm32f3xx_hal_pcd.h.

#define PCD_EP0MPS_64 DEP0CTL_MPS_64

Definition at line 351 of file stm32f3xx_hal_pcd.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD EP Type

Defines
PCD EP Type
PCD Private Constants

Defines

#define | PCD_EP_TYPE_CTRL 0U
#define | PCD_EP_TYPE_ISOC 1U
#define | PCD_EP_TYPE_BULK 2U
#define | PCD_EP_TYPE_INTR 3U

Define Documentation

#define PCD_EP_TYPE_BULK 2U

Definition at line 364 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Open().

#define PCD_EP_TYPE_CTRL 0U

Definition at line 362 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Open(), and HAL_PCD_Init().

#define PCD_EP_TYPE_INTR 3U

Definition at line 365 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Open().

#define PCD_EP_TYPE_ISOC 1U

Definition at line 363 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Open().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD ENDP

Defines
PCD ENDP
PCD Private Constants

Defines

#define | PCD_ENDP0 ((uint8_t)0U)
#define | PCD_ENDP1 ((uint8_t)1U)
#define | PCD_ENDP2 ((uint8_t)2U)
#define | PCD_ENDP3 ((uint8_t)3U)
#define | PCD_ENDP4 ((uint8_t)4U)
#define | PCD_ENDP5 ((uint8_t)5U)
#define | PCD_ENDP6 ((uint8_t)6U)
#define | PCD_ENDP7 ((uint8_t)7U)

Define Documentation

#define PCD_ENDP0 ((uint8_t)0U)

Definition at line 373 of file stm32f3xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_ENDP1 ((uint8_t)1U)

Definition at line 374 of file stm32f3xx_hal_pcd.h.

#define PCD_ENDP2 ((uint8_t)2U)

Definition at line 375 of file stm32f3xx_hal_pcd.h.

#define PCD_ENDP3 ((uint8_t)3U)

Definition at line 376 of file stm32f3xx_hal_pcd.h.

#define PCD_ENDP4 ((uint8_t)4U)

Definition at line 377 of file stm32f3xx_hal_pcd.h.

#define PCD_ENDP5 ((uint8_t)5U)

Definition at line 378 of file stm32f3xx_hal_pcd.h.

#define PCD_ENDP6 ((uint8_t)6U)

Definition at line 379 of file stm32f3xx_hal_pcd.h.

#define PCD_ENDP7 ((uint8_t)7U)

Definition at line 380 of file stm32f3xx_hal_pcd.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD Endpoint Kind

Defines
PCD Endpoint Kind
PCD Private Constants

Defines

#define | PCD_SNG_BUF 0U
#define | PCD_DBL_BUF 1U

Define Documentation

#define PCD_DBL_BUF 1U

Definition at line 389 of file stm32f3xx_hal_pcd.h.

#define PCD_SNG_BUF 0U

Definition at line 388 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCDEx_PMAConfig().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD Instance definition

Defines
PCD Instance definition
PCD

Defines

#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE

Define Documentation

#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE

Definition at line 827 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_Init().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD Private Macros

Defines
PCD Private Macros
PCD

Defines

#define | PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue))
#define | PCD_GET_ENDPOINT(USBx, bEpNum) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U)))))
#define | PCD_SET_EPTYPE(USBx, bEpNum, wType)
sets the type in the endpoint register(bits EP_TYPE[1:0])
#define | PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD)
gets the type in the endpoint register(bits EP_TYPE[1:0])
#define | PCD_FreeUserBuffer(USBx, bEpNum, bDir)
free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register
#define | PCD_GET_DB_DIR(USBx, bEpNum)
gets direction of the double buffered endpoint
#define | PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState)
sets the status for tx transfer (bits STAT_TX[1:0]).
#define | PCD_SET_EP_RX_STATUS(USBx, bEpNum, wState)
sets the status for rx transfer (bits STAT_TX[1:0])
#define | PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx)
sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
#define | PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT)
gets the status for tx/rx transfer (bits STAT_TX[1:0] /STAT_RX[1:0])
#define | PCD_GET_EP_RX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_STAT)
#define | PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
sets directly the VALID tx/rx-status into the endpoint register
#define | PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
#define | PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum)
checks stall condition in an endpoint.
#define | PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum)
#define | PCD_SET_EP_KIND(USBx, bEpNum)
set & clear EP_KIND bit.
#define | PCD_CLEAR_EP_KIND(USBx, bEpNum)
#define | PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
Sets/clears directly STATUS_OUT bit in the endpoint register.
#define | PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
#define | PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
Sets/clears directly EP_KIND bit in the endpoint register.
#define | PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
#define | PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)
Clears bit CTR_RX / CTR_TX in the endpoint register.
#define | PCD_CLEAR_TX_EP_CTR(USBx, bEpNum)
#define | PCD_RX_DTOG(USBx, bEpNum)
Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_TX_DTOG(USBx, bEpNum)
#define | PCD_CLEAR_RX_DTOG(USBx, bEpNum)
Clears DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_CLEAR_TX_DTOG(USBx, bEpNum)
#define | PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr)
Sets address in an endpoint register.
#define | PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
Gets address in an endpoint register.
#define | PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
sets address of the tx/rx buffer.
#define | PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
#define | PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
Gets address of the tx/rx buffer.
#define | PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
#define | PCD_CALC_BLK32(dwReg, wCount, wNBlocks)
Sets counter of rx buffer with no.
#define | PCD_CALC_BLK2(dwReg, wCount, wNBlocks)
#define | PCD_SET_EP_CNT_RX_REG(dwReg, wCount)
#define | PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount)
#define | PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
sets counter for the tx/rx buffer.
#define | PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
gets counter of the tx buffer.
#define | PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
#define | PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)))
Sets buffer 0/1 address in a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) (PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)))
#define | PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr)
Sets addresses in a double buffer endpoint.
#define | PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
#define | PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount)
#define | PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount)
#define | PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
Gets buffer 0/1 rx/tx counter for double buffering.
#define | PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))

Define Documentation

#define PCD_CALC_BLK2 | ( | dwReg,
 |  | wCount,
 |  | wNBlocks
 | ) |
Value:
{\
    (wNBlocks) = (wCount) >> 1U;\
    if(((wCount) & 0x1U) != 0U)\
    {                                                  \
      (wNBlocks)++;\
    }                                                  \
    *pdwReg = (uint16_t)((wNBlocks) << 10U);\
  }/* PCD_CALC_BLK2 */

Definition at line 701 of file stm32f3xx_hal_pcd.h.

#define PCD_CALC_BLK32 | ( | dwReg,
 |  | wCount,
 |  | wNBlocks
 | ) |
Value:
{\
    (wNBlocks) = (wCount) >> 5U;\
    if(((wCount) & 0x1fU) == 0U)\
    {                                                  \
      (wNBlocks)--;\
    }                                                  \
    *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | (uint16_t)0x8000U); \
  }/* PCD_CALC_BLK32 */

Sets counter of rx buffer with no.

of blocks.

Parameters:
dwReg | Register
wCount | Counter.
wNBlocks | no. of Blocks.
Return values:
None

Definition at line 691 of file stm32f3xx_hal_pcd.h.

#define PCD_CLEAR_EP_DBUF | ( | USBx,
 |  | bEpNum
 | ) | PCD_CLEAR_EP_KIND((USBx), (bEpNum))

Definition at line 608 of file stm32f3xx_hal_pcd.h.

#define PCD_CLEAR_EP_KIND | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_SET_ENDPOINT((USBx), (bEpNum), \
                                (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPKIND_MASK))))

Definition at line 589 of file stm32f3xx_hal_pcd.h.

#define PCD_CLEAR_OUT_STATUS | ( | USBx,
 |  | bEpNum
 | ) | PCD_CLEAR_EP_KIND((USBx), (bEpNum))

Definition at line 599 of file stm32f3xx_hal_pcd.h.

#define PCD_CLEAR_RX_DTOG | ( | USBx,
 |  | bEpNum
 | ) |
Value:
if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\
                                         {                                                              \
                                           PCD_RX_DTOG((USBx),(bEpNum));\
                                         }

Clears DTOG_RX / DTOG_TX bit in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 638 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), and HAL_PCD_EP_Open().

#define PCD_CLEAR_RX_EP_CTR | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_SET_ENDPOINT((USBx), (bEpNum),\
                                   PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))

Clears bit CTR_RX / CTR_TX in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 616 of file stm32f3xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_CLEAR_TX_DTOG | ( | USBx,
 |  | bEpNum
 | ) |
Value:
if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_TX) != 0)\
                                         {\
                                           PCD_TX_DTOG((USBx),(bEpNum));\
                                         }

Definition at line 642 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), and HAL_PCD_EP_Open().

#define PCD_CLEAR_TX_EP_CTR | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_SET_ENDPOINT((USBx), (bEpNum),\
                                   PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))

Definition at line 618 of file stm32f3xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_FreeUserBuffer | ( | USBx,
 |  | bEpNum,
 |  | bDir
 | ) |
Value:
{\
  if ((bDir) == PCD_EP_DBUF_OUT)\
  { /* OUT double buffered endpoint */\
    PCD_TX_DTOG((USBx), (bEpNum));\
  }\
  else if ((bDir) == PCD_EP_DBUF_IN)\
  { /* IN double buffered endpoint */\
    PCD_RX_DTOG((USBx), (bEpNum));\
  }\
}

free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
bDir | Direction
Return values:
None

Definition at line 439 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Transmit(), and PCD_EP_ISR_Handler().

#define PCD_GET_DB_DIR | ( | USBx,
 |  | bEpNum
 | ) |
Value:
{\
  if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00U) != 0U)\
    return(PCD_EP_DBUF_OUT);\
  else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FFU) != 0U)\
    return(PCD_EP_DBUF_IN);\
  else\
    return(PCD_EP_DBUF_ERR);\
}

gets direction of the double buffered endpoint

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
Return values:
EP_DBUF_OUT,EP_DBUF_IN,EP_DBUF_ERR if the endpoint counter not yet programmed.

Definition at line 458 of file stm32f3xx_hal_pcd.h.

#define PCD_GET_ENDPOINT | ( | USBx,
 |  | bEpNum
 | ) | (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U)))))

Definition at line 408 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Transmit(), and PCD_EP_ISR_Handler().

#define PCD_GET_EP_ADDRESS | ( | USBx,
 |  | bEpNum
 | ) | ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))

Gets address in an endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 663 of file stm32f3xx_hal_pcd.h.

#define PCD_GET_EP_DBUF0_ADDR | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))

Gets buffer 0/1 address of a double buffer endpoint.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 774 of file stm32f3xx_hal_pcd.h.

#define PCD_GET_EP_DBUF0_CNT | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))

Gets buffer 0/1 rx/tx counter for double buffering.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 818 of file stm32f3xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_DBUF1_ADDR | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))

Definition at line 775 of file stm32f3xx_hal_pcd.h.

#define PCD_GET_EP_DBUF1_CNT | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))

Definition at line 819 of file stm32f3xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_RX_ADDRESS | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))

Definition at line 682 of file stm32f3xx_hal_pcd.h.

#define PCD_GET_EP_RX_CNT | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)

Definition at line 743 of file stm32f3xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_RX_STALL_STATUS | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
                                   == USB_EP_RX_STALL)

Definition at line 578 of file stm32f3xx_hal_pcd.h.

#define PCD_GET_EP_RX_STATUS | ( | USBx,
 |  | bEpNum
 | ) | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_STAT)

Definition at line 558 of file stm32f3xx_hal_pcd.h.

#define PCD_GET_EP_TX_ADDRESS | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))

Gets address of the tx/rx buffer.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
address of the buffer.

Definition at line 681 of file stm32f3xx_hal_pcd.h.

#define PCD_GET_EP_TX_CNT | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)

gets counter of the tx buffer.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
Counter value

Definition at line 742 of file stm32f3xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_TX_STALL_STATUS | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
                                   == USB_EP_TX_STALL)

checks stall condition in an endpoint.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
TRUE = endpoint in stall condition.

Definition at line 576 of file stm32f3xx_hal_pcd.h.

#define PCD_GET_EP_TX_STATUS | ( | USBx,
 |  | bEpNum
 | ) | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT)

gets the status for tx/rx transfer (bits STAT_TX[1:0] /STAT_RX[1:0])

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
status

Definition at line 557 of file stm32f3xx_hal_pcd.h.

#define PCD_GET_EPTYPE | ( | USBx,
 |  | bEpNum
 | ) | (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD)

gets the type in the endpoint register(bits EP_TYPE[1:0])

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
Endpoint Type

Definition at line 428 of file stm32f3xx_hal_pcd.h.

#define PCD_RX_DTOG | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_SET_ENDPOINT((USBx), (bEpNum), \
                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))

Toggles DTOG_RX / DTOG_TX bit in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 627 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), and HAL_PCD_EP_Open().

#define PCD_SET_ENDPOINT | ( | USBx,
 |  | bEpNum,
 |  | wRegValue
 | ) | (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue))

Definition at line 405 of file stm32f3xx_hal_pcd.h.

#define PCD_SET_EP_ADDRESS | ( | USBx,
 |  | bEpNum,
 |  | bAddr
 | ) |
Value:
PCD_SET_ENDPOINT((USBx), (bEpNum),\
    USB_EP_CTR_RX|USB_EP_CTR_TX|(((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK) | (bAddr))

Sets address in an endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
bAddr | Address.
Return values:
None

Definition at line 654 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Open().

#define PCD_SET_EP_CNT_RX_REG | ( | dwReg,
 |  | wCount
 | ) |
Value:
{\
    uint16_t wNBlocks;\
    if((wCount) > 62U)                                \
    {                                                \
      PCD_CALC_BLK32((dwReg),(wCount),wNBlocks)     \
    }                                                \
    else                                             \
    {                                                \
      PCD_CALC_BLK2((dwReg),(wCount),wNBlocks)     \
    }                                                \
  }/* PCD_SET_EP_CNT_RX_REG */

Definition at line 710 of file stm32f3xx_hal_pcd.h.

#define PCD_SET_EP_DBUF | ( | USBx,
 |  | bEpNum
 | ) | PCD_SET_EP_KIND((USBx), (bEpNum))

Sets/clears directly EP_KIND bit in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 607 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Open().

#define PCD_SET_EP_DBUF0_ADDR | ( | USBx,
 |  | bEpNum,
 |  | wBuf0Addr
 | ) | (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)))

Sets buffer 0/1 address in a double buffer endpoint.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wBuf0Addr,: buffer 0 address.
Return values:
Counter value

Definition at line 752 of file stm32f3xx_hal_pcd.h.

#define PCD_SET_EP_DBUF0_CNT | ( | USBx,
 |  | bEpNum,
 |  | bDir,
 |  | wCount
 | ) |
Value:
{ \
    if((bDir) == PCD_EP_DBUF_OUT)\
      /* OUT endpoint */ \
    {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount))} \
    else if((bDir) == PCD_EP_DBUF_IN)\
      {                                                       \
      *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount);  \
      }                                                       \
  } /* SetEPDblBuf0Count*/

Gets buffer 0/1 address of a double buffer endpoint.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
bDir | endpoint dir EP_DBUF_OUT = OUT EP_DBUF_IN = IN
wCount | Counter value
Return values:
None

Definition at line 786 of file stm32f3xx_hal_pcd.h.

#define PCD_SET_EP_DBUF1_ADDR | ( | USBx,
 |  | bEpNum,
 |  | wBuf1Addr
 | ) | (PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)))

Definition at line 753 of file stm32f3xx_hal_pcd.h.

#define PCD_SET_EP_DBUF1_CNT | ( | USBx,
 |  | bEpNum,
 |  | bDir,
 |  | wCount
 | ) |
Value:
{ \
    if((bDir) == PCD_EP_DBUF_OUT)\
    {/* OUT endpoint */                                       \
      PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount))           \
    }                                                         \
    else if((bDir) == PCD_EP_DBUF_IN)\
    {/* IN endpoint */                                        \
      *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
    }                                                         \
  } /* SetEPDblBuf1Count */

Definition at line 796 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Receive().

#define PCD_SET_EP_DBUF_ADDR | ( | USBx,
 |  | bEpNum,
 |  | wBuf0Addr,
 |  | wBuf1Addr
 | ) |
Value:
{ \
    PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
    PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
  } /* PCD_SET_EP_DBUF_ADDR */

Sets addresses in a double buffer endpoint.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wBuf0Addr,: buffer 0 address.
wBuf1Addr | = buffer 1 address.
Return values:
None

Definition at line 763 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Open().

#define PCD_SET_EP_DBUF_CNT | ( | USBx,
 |  | bEpNum,
 |  | bDir,
 |  | wCount
 | ) |
Value:
{\
    PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)) \
    PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)) \
  } /

Definition at line 807 of file stm32f3xx_hal_pcd.h.

#define PCD_SET_EP_KIND | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_SET_ENDPOINT((USBx), (bEpNum), \
                                (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) | USB_EP_KIND) & USB_EPREG_MASK))))

set & clear EP_KIND bit.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 587 of file stm32f3xx_hal_pcd.h.

#define PCD_SET_EP_RX_ADDRESS | ( | USBx,
 |  | bEpNum,
 |  | wAddr
 | ) | (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))

Definition at line 673 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Open().

#define PCD_SET_EP_RX_DBUF0_CNT | ( | USBx,
 |  | bEpNum,
 |  | wCount
 | ) |
Value:
{\
    uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount))\
  }

Definition at line 722 of file stm32f3xx_hal_pcd.h.

#define PCD_SET_EP_RX_STATUS | ( | USBx,
 |  | bEpNum,
 |  | wState
 | ) |
Value:
{\
    register uint16_t _wRegVal;   \
    \
    _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_DTOGMASK);\
    /* toggle first bit ? */  \
    if((USB_EPRX_DTOG1 & (wState))!= 0U) \
    {                                                                             \
      _wRegVal ^= (uint16_t) USB_EPRX_DTOG1;  \
    }                                                                             \
    /* toggle second bit ? */  \
    if((USB_EPRX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
    {                                                                             \
      _wRegVal ^= (uint16_t) USB_EPRX_DTOG2;  \
    }                                                                             \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
  } /* PCD_SET_EP_RX_STATUS */

sets the status for rx transfer (bits STAT_TX[1:0])

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wState | new state
Return values:
None

Definition at line 498 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), and PCD_EP_ISR_Handler().

#define PCD_SET_EP_RX_VALID | ( | USBx,
 |  | bEpNum
 | ) | (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))

Definition at line 568 of file stm32f3xx_hal_pcd.h.

#define PCD_SET_EP_TX_ADDRESS | ( | USBx,
 |  | bEpNum,
 |  | wAddr
 | ) | (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))

sets address of the tx/rx buffer.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wAddr | address to be set (must be word aligned).
Return values:
None

Definition at line 672 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Open().

#define PCD_SET_EP_TX_CNT | ( | USBx,
 |  | bEpNum,
 |  | wCount
 | ) | (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))

sets counter for the tx/rx buffer.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wCount | Counter value.
Return values:
None

Definition at line 734 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Transmit().

#define PCD_SET_EP_TX_STATUS | ( | USBx,
 |  | bEpNum,
 |  | wState
 | ) |
Value:
{ register uint16_t _wRegVal;\
   \
    _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_DTOGMASK);\
   /* toggle first bit ? */     \
   if((USB_EPTX_DTOG1 & (wState))!= 0U)\
   {                                                                            \
     _wRegVal ^=(uint16_t) USB_EPTX_DTOG1;        \
   }                                                                            \
   /* toggle second bit ?  */         \
   if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U)      \
   {                                                                            \
     _wRegVal ^=(uint16_t) USB_EPTX_DTOG2;        \
   }                                                                            \
   PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX));\
  } /* PCD_SET_EP_TX_STATUS */

sets the status for tx transfer (bits STAT_TX[1:0]).

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wState | new state
Return values:
None

Definition at line 475 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Open(), HAL_PCD_EP_SetStall(), and HAL_PCD_EP_Transmit().

#define PCD_SET_EP_TX_VALID | ( | USBx,
 |  | bEpNum
 | ) | (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))

sets directly the VALID tx/rx-status into the endpoint register

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 566 of file stm32f3xx_hal_pcd.h.

#define PCD_SET_EP_TXRX_STATUS | ( | USBx,
 |  | bEpNum,
 |  | wStaterx,
 |  | wStatetx
 | ) |
Value:
{\
    register uint32_t _wRegVal;   \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
    /* toggle first bit ? */  \
    if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0U) \
    {                                                                                    \
      _wRegVal ^= USB_EPRX_DTOG1;  \
    }                                                                                    \
    /* toggle second bit ? */  \
    if((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
    {                                                                                    \
      _wRegVal ^= USB_EPRX_DTOG2;  \
    }                                                                                    \
    /* toggle first bit ? */     \
    if((USB_EPTX_DTOG1 & (wStatetx))!= 0U)      \
    {                                                                                    \
      _wRegVal ^= USB_EPTX_DTOG1;        \
    }                                                                                    \
    /* toggle second bit ?  */         \
    if((USB_EPTX_DTOG2 & (wStatetx))!= 0U)      \
    {                                                                                    \
      _wRegVal ^= USB_EPTX_DTOG2;        \
    }                                                                                    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX);    \
  } /* PCD_SET_EP_TXRX_STATUS */

sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wStaterx | new state.
wStatetx | new state.
Return values:
None

Definition at line 523 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_SetStall().

#define PCD_SET_EPTYPE | ( | USBx,
 |  | bEpNum,
 |  | wType
 | ) |
Value:
(PCD_SET_ENDPOINT((USBx), (bEpNum),\
                                  ((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & ((uint32_t)(USB_EP_T_MASK))) | ((uint32_t)(wType)) )))

sets the type in the endpoint register(bits EP_TYPE[1:0])

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wType | Endpoint Type.
Return values:
None

Definition at line 419 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Open().

#define PCD_SET_OUT_STATUS | ( | USBx,
 |  | bEpNum
 | ) | PCD_SET_EP_KIND((USBx), (bEpNum))

Sets/clears directly STATUS_OUT bit in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 598 of file stm32f3xx_hal_pcd.h.

#define PCD_TX_DTOG | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_SET_ENDPOINT((USBx), (bEpNum), \
                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))

Definition at line 629 of file stm32f3xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), and HAL_PCD_EP_Open().

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD Extended Private Functions

Functions
PCD Extended Private Functions
PCDEx | PCD

Functions

void | PCD_WritePMA (USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
Copy a buffer from user memory area to packet memory area (PMA)
void | PCD_ReadPMA (USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
Copy a buffer from user memory area to packet memory area (PMA)

Function Documentation

void PCD_ReadPMA | ( | USB_TypeDef * | USBx,
 |  | uint8_t * | pbUsrBuf,
 |  | uint16_t | wPMABufAddr,
 |  | uint16_t | wNBytes
 | ) |  |

Copy a buffer from user memory area to packet memory area (PMA)

Parameters:
USBx,: USB peripheral instance register address.
pbUsrBuf,: pointer to user memory area.
wPMABufAddr,: address into PMA.
wNBytes,: no. of bytes to be copied.
Return values:
None

Definition at line 190 of file stm32f3xx_hal_pcd_ex.c.

Referenced by PCD_EP_ISR_Handler().

void PCD_WritePMA | ( | USB_TypeDef * | USBx,
 |  | uint8_t * | pbUsrBuf,
 |  | uint16_t | wPMABufAddr,
 |  | uint16_t | wNBytes
 | ) |  |

Copy a buffer from user memory area to packet memory area (PMA)

Parameters:
USBx,: USB peripheral instance register address.
pbUsrBuf,: pointer to user memory area.
wPMABufAddr,: address into PMA.
wNBytes,: no. of bytes to be copied.
Return values:
None

Definition at line 163 of file stm32f3xx_hal_pcd_ex.c.

Referenced by HAL_PCD_EP_Transmit(), and PCD_EP_ISR_Handler().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCDEx Exported Functions

PCDEx control functions. More...

Functions

HAL_StatusTypeDef | HAL_PCDEx_PMAConfig (PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress)
Configure PMA for EP.
void | HAL_PCDEx_SetConnectionState (PCD_HandleTypeDef *hpcd, uint8_t state)
Software Device Connection.

Detailed Description

PCDEx control functions.

 ===============================================================================
              ##### Extended Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Update PMA configuration

Function Documentation

HAL_StatusTypeDef HAL_PCDEx_PMAConfig | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint16_t | ep_addr,
 |  | uint16_t | ep_kind,
 |  | uint32_t | pmaadress
 | ) |  |

Configure PMA for EP.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
ep_kind endpoint Kind
  • USB_SNG_BUF: Single Buffer used
  • USB_DBL_BUF: Double Buffer used
pmaadress | EP address in The PMA: In case of single buffer endpoint this parameter is 16-bit value providing the address in PMA allocated to endpoint. In case of double buffer endpoint this parameter is a 32-bit value providing the endpoint buffer 0 address in the LSB part of 32-bit value and endpoint buffer 1 address in the MSB part of 32-bit value.
Return values:
: status

Definition at line 101 of file stm32f3xx_hal_pcd_ex.c.

References PCD_EPTypeDef::doublebuffer, PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::OUT_ep, PCD_SNG_BUF, PCD_EPTypeDef::pmaaddr0, PCD_EPTypeDef::pmaaddr1, and PCD_EPTypeDef::pmaadress.

void HAL_PCDEx_SetConnectionState | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | state
 | ) |  |

Software Device Connection.

Parameters:
hpcd | PCD handle
state | Device state
Return values:
None

Definition at line 294 of file stm32f3xx_hal_pcd_ex.c.

Referenced by HAL_PCD_DevConnect(), HAL_PCD_DevDisconnect(), and HAL_PCD_Start().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Extended Initialization and de-initialization functions

Functions
Extended Initialization and de-initialization functions
PCDEx Exported Functions

Functions

__weak void HAL_PCDEx_SetConnectionState (PCD_HandleTypeDef *hpcd, uint8_t state)
Software Device Connection.

Function Documentation

__weak void HAL_PCDEx_SetConnectionState | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | state
 | ) |  |

Software Device Connection.

Parameters:
hpcd | PCD handle
state | Device state
Return values:
None

Definition at line 294 of file stm32f3xx_hal_pcd_ex.c.

Referenced by HAL_PCD_DevConnect(), HAL_PCD_DevDisconnect(), and HAL_PCD_Start().

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD Extended Exported Macros

Defines
PCD Extended Exported Macros
PCDEx

Defines

#define | PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)*2+ ((uint32_t)(USBx) + 0x400U)))))
Gets address in an endpoint register.
#define | PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400U)))))
#define | PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400U)))))
#define | PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400U)))))
#define | PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount)

Define Documentation

#define PCD_EP_RX_ADDRESS | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400U)))))

Definition at line 78 of file stm32f3xx_hal_pcd_ex.h.

#define PCD_EP_RX_CNT | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400U)))))

Definition at line 79 of file stm32f3xx_hal_pcd_ex.h.

#define PCD_EP_TX_ADDRESS | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)*2+ ((uint32_t)(USBx) + 0x400U)))))

Gets address in an endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 76 of file stm32f3xx_hal_pcd_ex.h.

#define PCD_EP_TX_CNT | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400U)))))

Definition at line 77 of file stm32f3xx_hal_pcd_ex.h.

#define PCD_SET_EP_RX_CNT | ( | USBx,
 |  | bEpNum,
 |  | wCount
 | ) |
Value:
{\
    uint16_t *pdwReg =PCD_EP_RX_CNT((USBx),(bEpNum)); \
    PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
  }

Definition at line 82 of file stm32f3xx_hal_pcd_ex.h.

Referenced by HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), and PCD_EP_ISR_Handler().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Extended Private Constants

Defines
PWR Extended Private Constants
PWREx

Defines

#define | PVD_MODE_IT (0x00010000U)
#define | PVD_MODE_EVT (0x00020000U)
#define | PVD_RISING_EDGE (0x00000001U)
#define | PVD_FALLING_EDGE (0x00000002U)

Define Documentation

#define PVD_FALLING_EDGE (0x00000002U)

Definition at line 63 of file stm32f3xx_hal_pwr_ex.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_MODE_EVT (0x00020000U)

Definition at line 61 of file stm32f3xx_hal_pwr_ex.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_MODE_IT (0x00010000U)

Definition at line 60 of file stm32f3xx_hal_pwr_ex.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_RISING_EDGE (0x00000001U)

Definition at line 62 of file stm32f3xx_hal_pwr_ex.c.

Referenced by HAL_PWR_ConfigPVD().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral Extended Control Functions

Functions
Peripheral Extended Control Functions
PWR Extended Exported Functions

Extended Peripheral Control functions. More...

Functions

void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enables the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disables the Power Voltage Detector(PVD).
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.
void | HAL_PWREx_EnableSDADC (uint32_t Analogx)
Enables the SDADC peripheral functionaliy.
void | HAL_PWREx_DisableSDADC (uint32_t Analogx)
Disables the SDADC peripheral functionaliy.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                 ##### Peripheral Extended control functions #####
 ===============================================================================
    *** PVD configuration (present on all other devices than STM32F3x8 devices) ***
    =========================
    [..]
      (+) The PVD is used to monitor the VDD power supply by comparing it to a
          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
          than the PVD threshold. This event is internally connected to the EXTI
          line16 and can generate an interrupt if enabled. This is done through
          __HAL_PWR_PVD_EXTI_ENABLE_IT() macro
      (+) The PVD is stopped in Standby mode.
      -@- PVD is not available on STM32F3x8 Product Line

    *** Voltage regulator ***
    =========================
    [..]
      (+) The voltage regulator is always enabled after Reset. It works in three different
          modes.
          In Run mode, the regulator supplies full power to the 1.8V domain (core, memories
          and digital peripherals).
          In Stop mode, the regulator supplies low power to the 1.8V domain, preserving
          contents of registers and SRAM.
          In Stop mode, the regulator is powered off. The contents of the registers and SRAM
          are lost except for the Standby circuitry and the Backup Domain.
          Note: in the STM32F3x8xx devices, the voltage regulator is bypassed and the
          microcontroller must be powered from a nominal VDD = 1.8V +/-8U% voltage.

      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
          than the PVD threshold. This event is internally connected to the EXTI
          line16 and can generate an interrupt if enabled. This is done through
          __HAL_PWR_PVD_EXTI_ENABLE_IT() macro
      (+) The PVD is stopped in Standby mode.

    *** SDADC power configuration ***
    ================================
    [..]
      (+) On STM32F373xC/STM32F378xx devices, there are up to
          3 SDADC instances that can be enabled/disabled.

Function Documentation

void HAL_PWR_ConfigPVD ( PWR_PVDTypeDef * sConfigPVD )

Configures the voltage threshold detected by the Power Voltage Detector(PVD).

Parameters:
sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration information for the PVD.
Note:
Refer to the electrical characteristics of your device datasheet for more details about the voltage threshold corresponding to each detection level.
Return values:
None

Definition at line 145 of file stm32f3xx_hal_pwr_ex.c.

References __HAL_PWR_PVD_EXTI_DISABLE_EVENT, __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_DISABLE_IT, __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_EVENT, __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_IT, __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE, assert_param, IS_PWR_PVD_LEVEL, IS_PWR_PVD_MODE, PWR_PVDTypeDef::Mode, PVD_FALLING_EDGE, PVD_MODE_EVT, PVD_MODE_IT, PVD_RISING_EDGE, and PWR_PVDTypeDef::PVDLevel.

void HAL_PWR_DisablePVD ( void )

Disables the Power Voltage Detector(PVD).

Return values:
None

Definition at line 196 of file stm32f3xx_hal_pwr_ex.c.

void HAL_PWR_EnablePVD ( void )

Enables the Power Voltage Detector(PVD).

Return values:
None

Definition at line 187 of file stm32f3xx_hal_pwr_ex.c.

void HAL_PWR_PVD_IRQHandler ( void )

This function handles the PWR PVD interrupt request.

Note:
This API should be called under the PVD_IRQHandler().
Return values:
None

Definition at line 206 of file stm32f3xx_hal_pwr_ex.c.

References __HAL_PWR_PVD_EXTI_CLEAR_FLAG, __HAL_PWR_PVD_EXTI_GET_FLAG, and HAL_PWR_PVDCallback().

void HAL_PWR_PVDCallback ( void )

PWR PVD interrupt callback.

Return values:
None

Definition at line 223 of file stm32f3xx_hal_pwr_ex.c.

Referenced by HAL_PWR_PVD_IRQHandler().

void HAL_PWREx_DisableSDADC ( uint32_t Analogx )

Disables the SDADC peripheral functionaliy.

Parameters:
Analogx specifies the SDADC peripheral instance. This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3.
Return values:
None

Definition at line 261 of file stm32f3xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_SDADC_ANALOG.

void HAL_PWREx_EnableSDADC ( uint32_t Analogx )

Enables the SDADC peripheral functionaliy.

Parameters:
Analogx specifies the SDADC peripheral instance. This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3.
Return values:
None

Definition at line 244 of file stm32f3xx_hal_pwr_ex.c.

References __HAL_RCC_PWR_CLK_ENABLE, assert_param, and IS_PWR_SDADC_ANALOG.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR_PVDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWR_PVDTypeDef Struct Reference
PWR Extended Exported Types

PWR PVD configuration structure definition. More...

#include <stm32f3xx_hal_pwr_ex.h>

Data Fields

uint32_t | PVDLevel
uint32_t | Mode

Detailed Description

PWR PVD configuration structure definition.

Definition at line 68 of file stm32f3xx_hal_pwr_ex.h.

Field Documentation

uint32_t PWR_PVDTypeDef::Mode

Mode: Specifies the operating mode for the selected pins. This parameter can be a value of PWR Extended PVD Mode

Definition at line 73 of file stm32f3xx_hal_pwr_ex.h.

Referenced by HAL_PWR_ConfigPVD().

uint32_t PWR_PVDTypeDef::PVDLevel

PVDLevel: Specifies the PVD detection level This parameter can be a value of PWR Extended PVD detection level

Definition at line 70 of file stm32f3xx_hal_pwr_ex.h.

Referenced by HAL_PWR_ConfigPVD().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_pwr_ex.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Extended PVD detection level

Defines
PWR Extended PVD detection level
PWR Extended Exported Constants

Defines

#define | PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
#define | PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
#define | PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
#define | PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
#define | PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
#define | PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
#define | PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
#define | PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7

Define Documentation

#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0

PVD threshold around 2.2 V

Definition at line 100 of file stm32f3xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1

PVD threshold around 2.3 V

Definition at line 101 of file stm32f3xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2

PVD threshold around 2.4 V

Definition at line 102 of file stm32f3xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3

PVD threshold around 2.5 V

Definition at line 103 of file stm32f3xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4

PVD threshold around 2.6 V

Definition at line 104 of file stm32f3xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5

PVD threshold around 2.7 V

Definition at line 105 of file stm32f3xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6

PVD threshold around 2.8 V

Definition at line 106 of file stm32f3xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7

PVD threshold around 2.9 V

Definition at line 107 of file stm32f3xx_hal_pwr_ex.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Extended PVD Mode

Defines
PWR Extended PVD Mode
PWR Extended Exported Constants

Defines

#define | PWR_PVD_MODE_NORMAL (0x00000000U)
#define | PWR_PVD_MODE_IT_RISING (0x00010001U)
#define | PWR_PVD_MODE_IT_FALLING (0x00010002U)
#define | PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U)
#define | PWR_PVD_MODE_EVENT_RISING (0x00020001U)
#define | PWR_PVD_MODE_EVENT_FALLING (0x00020002U)
#define | PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U)

Define Documentation

#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U)

Event Mode with Falling edge trigger detection

Definition at line 120 of file stm32f3xx_hal_pwr_ex.h.

#define PWR_PVD_MODE_EVENT_RISING (0x00020001U)

Event Mode with Rising edge trigger detection

Definition at line 119 of file stm32f3xx_hal_pwr_ex.h.

#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U)

Event Mode with Rising/Falling edge trigger detection

Definition at line 121 of file stm32f3xx_hal_pwr_ex.h.

#define PWR_PVD_MODE_IT_FALLING (0x00010002U)

External Interrupt Mode with Falling edge trigger detection

Definition at line 117 of file stm32f3xx_hal_pwr_ex.h.

#define PWR_PVD_MODE_IT_RISING (0x00010001U)

External Interrupt Mode with Rising edge trigger detection

Definition at line 116 of file stm32f3xx_hal_pwr_ex.h.

#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 118 of file stm32f3xx_hal_pwr_ex.h.

#define PWR_PVD_MODE_NORMAL (0x00000000U)

Basic mode is used

Definition at line 115 of file stm32f3xx_hal_pwr_ex.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Extended SDADC ANALOGx

Defines
PWR Extended SDADC ANALOGx
PWR Extended Exported Constants

Defines

#define | PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_ENSD1)
#define | PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_ENSD2)
#define | PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_ENSD3)

Define Documentation

#define PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_ENSD1)

Enable SDADC1

Definition at line 138 of file stm32f3xx_hal_pwr_ex.h.

#define PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_ENSD2)

Enable SDADC2

Definition at line 139 of file stm32f3xx_hal_pwr_ex.h.

#define PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_ENSD3)

Enable SDADC3

Definition at line 140 of file stm32f3xx_hal_pwr_ex.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Extended Exported Constants

Modules | Defines
PWR Extended Exported Constants
PWREx

Modules

PWR Extended PVD detection level
PWR Extended PVD Mode
PWR Extended SDADC ANALOGx

Defines

#define PWR_EXTI_LINE_PVD EXTI_IMR_MR16

Define Documentation

#define PWR_EXTI_LINE_PVD EXTI_IMR_MR16

External interrupt line 16 Connected to the PVD EXTI Line

Definition at line 126 of file stm32f3xx_hal_pwr_ex.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Extended Exported Macros

Defines
PWR Extended Exported Macros
PWREx

Defines

#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
Enable interrupt on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
Disable interrupt on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
Enable event on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
Disable event on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
PVD EXTI line configuration: set falling edge trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
PVD EXTI line configuration: set rising edge trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
Enable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
Check whether the specified PVD EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
Clear the PVD EXTI flag.

Define Documentation

#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG ( ) (EXTI->PR = (PWR_EXTI_LINE_PVD))

Clear the PVD EXTI flag.

Return values:
None.

Definition at line 237 of file stm32f3xx_hal_pwr_ex.h.

Referenced by HAL_PWR_PVD_IRQHandler().

#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT ( ) (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))

Disable event on PVD Exti Line 16.

Return values:
None.

Definition at line 189 of file stm32f3xx_hal_pwr_ex.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 201 of file stm32f3xx_hal_pwr_ex.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_IT ( ) (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))

Disable interrupt on PVD Exti Line 16.

Return values:
None.

Definition at line 171 of file stm32f3xx_hal_pwr_ex.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Rising Trigger.

Return values:
None.

Definition at line 195 of file stm32f3xx_hal_pwr_ex.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE ( ) __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();

Disable the PVD Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 207 of file stm32f3xx_hal_pwr_ex.h.

#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT ( ) (EXTI->EMR |= (PWR_EXTI_LINE_PVD))

Enable event on PVD Exti Line 16.

Return values:
None.

Definition at line 183 of file stm32f3xx_hal_pwr_ex.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ( ) EXTI->FTSR |= (PWR_EXTI_LINE_PVD)

PVD EXTI line configuration: set falling edge trigger.

Return values:
None.

Definition at line 213 of file stm32f3xx_hal_pwr_ex.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_IT ( ) (EXTI->IMR |= (PWR_EXTI_LINE_PVD))

Enable interrupt on PVD Exti Line 16.

Return values:
None.

Definition at line 165 of file stm32f3xx_hal_pwr_ex.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ( ) EXTI->RTSR |= (PWR_EXTI_LINE_PVD)

PVD EXTI line configuration: set rising edge trigger.

Return values:
None.

Definition at line 219 of file stm32f3xx_hal_pwr_ex.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE ( ) __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();

Enable the PVD Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 225 of file stm32f3xx_hal_pwr_ex.h.

#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))

Generate a Software interrupt on selected EXTI line.

Return values:
None.

Definition at line 177 of file stm32f3xx_hal_pwr_ex.h.

#define __HAL_PWR_PVD_EXTI_GET_FLAG ( ) (EXTI->PR & (PWR_EXTI_LINE_PVD))

Check whether the specified PVD EXTI interrupt flag is set or not.

Return values:
EXTI PVD Line Status.

Definition at line 231 of file stm32f3xx_hal_pwr_ex.h.

Referenced by HAL_PWR_PVD_IRQHandler().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Extended Private Macros

Defines
PWR Extended Private Macros
PWREx

Defines

#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_SDADC_ANALOG(SDADC)

Define Documentation

#define IS_PWR_PVD_LEVEL ( LEVEL )
Value:
(((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))

Definition at line 259 of file stm32f3xx_hal_pwr_ex.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_PVD_MODE ( MODE )
Value:
(((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
                              ((MODE) == PWR_PVD_MODE_NORMAL))

Definition at line 264 of file stm32f3xx_hal_pwr_ex.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_SDADC_ANALOG ( SDADC )
Value:
(((SDADC) == PWR_SDADC_ANALOG1) || \
                                    ((SDADC) == PWR_SDADC_ANALOG2) || \
                                    ((SDADC) == PWR_SDADC_ANALOG3))

Definition at line 275 of file stm32f3xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableSDADC(), and HAL_PWREx_EnableSDADC().

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Timeout

Defines
RCC Timeout
RCC Private Constants

Defines

#define | RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define | CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
#define | LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
#define | PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */

Define Documentation

#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */

Definition at line 67 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT

Definition at line 68 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */

Definition at line 69 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */

Definition at line 70 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */

Definition at line 71 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */

Definition at line 64 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT

Definition at line 66 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Register offsets

Defines
Register offsets
RCC Private Constants

Defines

#define | RCC_OFFSET (RCC_BASE - PERIPH_BASE)
#define | RCC_CR_OFFSET 0x00
#define | RCC_CFGR_OFFSET 0x04
#define | RCC_CIR_OFFSET 0x08
#define | RCC_BDCR_OFFSET 0x20
#define | RCC_CSR_OFFSET 0x24

Define Documentation

#define RCC_BDCR_OFFSET 0x20

Definition at line 83 of file stm32f3xx_hal_rcc.h.

#define RCC_CFGR_OFFSET 0x04

Definition at line 81 of file stm32f3xx_hal_rcc.h.

#define RCC_CIR_OFFSET 0x08

Definition at line 82 of file stm32f3xx_hal_rcc.h.

#define RCC_CR_OFFSET 0x00

Definition at line 80 of file stm32f3xx_hal_rcc.h.

#define RCC_CSR_OFFSET 0x24

Definition at line 84 of file stm32f3xx_hal_rcc.h.

#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)

Definition at line 79 of file stm32f3xx_hal_rcc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: BitAddress AliasRegion

Defines
BitAddress AliasRegion
RCC Private Constants

RCC registers bit address in the alias region. More...

Defines

#define | RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
#define | RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
#define | RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
#define | RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
#define | RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
#define | RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
#define | RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
#define | RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
#define | RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
#define | RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
#define | RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
#define | RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
#define | RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
#define | RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
#define | RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
#define | RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
#define | RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
#define | RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON)
#define | RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
#define | RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
#define | RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
#define | RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN)
#define | RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
#define | RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST)
#define | RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))

Detailed Description

RCC registers bit address in the alias region.

Define Documentation

#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))

Definition at line 138 of file stm32f3xx_hal_rcc.h.

#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))

Definition at line 130 of file stm32f3xx_hal_rcc.h.

#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))

Definition at line 126 of file stm32f3xx_hal_rcc.h.

#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)

Definition at line 97 of file stm32f3xx_hal_rcc.h.

#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))

Definition at line 134 of file stm32f3xx_hal_rcc.h.

#define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST)

Definition at line 137 of file stm32f3xx_hal_rcc.h.

#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)

Definition at line 95 of file stm32f3xx_hal_rcc.h.

#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)

Definition at line 96 of file stm32f3xx_hal_rcc.h.

#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))

Definition at line 109 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_DisableCSS(), and HAL_RCC_EnableCSS().

#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))

Definition at line 106 of file stm32f3xx_hal_rcc.h.

#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))

Definition at line 103 of file stm32f3xx_hal_rcc.h.

#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)

Definition at line 94 of file stm32f3xx_hal_rcc.h.

#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))

Definition at line 112 of file stm32f3xx_hal_rcc.h.

#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))

Definition at line 117 of file stm32f3xx_hal_rcc.h.

#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)

Definition at line 98 of file stm32f3xx_hal_rcc.h.

#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))

Definition at line 121 of file stm32f3xx_hal_rcc.h.

#define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)

Definition at line 108 of file stm32f3xx_hal_rcc.h.

#define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)

Definition at line 105 of file stm32f3xx_hal_rcc.h.

#define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)

Definition at line 102 of file stm32f3xx_hal_rcc.h.

#define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP)

Definition at line 129 of file stm32f3xx_hal_rcc.h.

#define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON)

Definition at line 125 of file stm32f3xx_hal_rcc.h.

#define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)

Definition at line 116 of file stm32f3xx_hal_rcc.h.

#define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)

Definition at line 111 of file stm32f3xx_hal_rcc.h.

#define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)

Definition at line 120 of file stm32f3xx_hal_rcc.h.

#define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN)

Definition at line 133 of file stm32f3xx_hal_rcc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Private Constants

Modules | Defines
RCC Private Constants
RCC

Modules

RCC Timeout
Register offsets
BitAddress AliasRegion

RCC registers bit address in the alias region.

Defines

#define | RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE)
#define | RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1)
#define | RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2)
#define | RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
#define | RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
#define | RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
#define | CR_REG_INDEX ((uint8_t)1U)
#define | BDCR_REG_INDEX ((uint8_t)2U)
#define | CSR_REG_INDEX ((uint8_t)3U)
#define | CFGR_REG_INDEX ((uint8_t)4U)
#define | RCC_FLAG_MASK ((uint8_t)0x1FU)

Define Documentation

#define BDCR_REG_INDEX ((uint8_t)2U)

Definition at line 155 of file stm32f3xx_hal_rcc.h.

#define CFGR_REG_INDEX ((uint8_t)4U)

Definition at line 157 of file stm32f3xx_hal_rcc.h.

#define CR_REG_INDEX ((uint8_t)1U)

Definition at line 154 of file stm32f3xx_hal_rcc.h.

#define CSR_REG_INDEX ((uint8_t)3U)

Definition at line 156 of file stm32f3xx_hal_rcc.h.

#define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE)

Definition at line 98 of file stm32f3xx_hal_rcc.c.

Referenced by HAL_RCC_ClockConfig().

#define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1)

Definition at line 99 of file stm32f3xx_hal_rcc.c.

Referenced by HAL_RCC_GetPCLK1Freq().

#define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2)

Definition at line 100 of file stm32f3xx_hal_rcc.c.

Referenced by HAL_RCC_GetPCLK2Freq().

#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))

Definition at line 148 of file stm32f3xx_hal_rcc.h.

#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))

Definition at line 151 of file stm32f3xx_hal_rcc.h.

#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))

Definition at line 145 of file stm32f3xx_hal_rcc.h.

#define RCC_FLAG_MASK ((uint8_t)0x1FU)

Definition at line 159 of file stm32f3xx_hal_rcc.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Private Macros

Defines
RCC Private Macros
RCC

Defines

#define | MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8
#define | IS_RCC_PLLSOURCE(__SOURCE__)
#define | IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)
#define | IS_RCC_HSE(__HSE__)
#define | IS_RCC_LSE(__LSE__)
#define | IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define | IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
#define | IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define | IS_RCC_PLL(__PLL__)
#define | IS_RCC_PLL_DIV(__DIV__)
#define | IS_RCC_HSE_PREDIV(DIV)
#define | IS_RCC_PLL_MUL(__MUL__)
#define | IS_RCC_CLOCKTYPE(CLK)
#define | IS_RCC_SYSCLKSOURCE(__SOURCE__)
#define | IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__)
#define | IS_RCC_HCLK(__HCLK__)
#define | IS_RCC_PCLK(__PCLK__)
#define | IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
#define | IS_RCC_RTCCLKSOURCE(__SOURCE__)
#define | IS_RCC_USART2CLKSOURCE(__SOURCE__)
#define | IS_RCC_USART3CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C1CLKSOURCE(__SOURCE__)

Define Documentation

#define IS_RCC_CALIBRATION_VALUE ( __VALUE__ ) ((__VALUE__) <= 0x1FU)

Definition at line 180 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_CLOCKTYPE ( CLK )
Value:
((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
                               (((CLK) & RCC_CLOCKTYPE_HCLK)   == RCC_CLOCKTYPE_HCLK)   || \
                               (((CLK) & RCC_CLOCKTYPE_PCLK1)  == RCC_CLOCKTYPE_PCLK1)  || \
                               (((CLK) & RCC_CLOCKTYPE_PCLK2)  == RCC_CLOCKTYPE_PCLK2))

Definition at line 216 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HCLK ( __HCLK__ )
Value:
(((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
                               ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
                               ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
                               ((__HCLK__) == RCC_SYSCLK_DIV512))

Definition at line 226 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HSE ( __HSE__ )
Value:
(((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
                             ((__HSE__) == RCC_HSE_BYPASS))

Definition at line 175 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSE_PREDIV ( DIV )
Value:
(((DIV) == RCC_HSE_PREDIV_DIV1)  || ((DIV) == RCC_HSE_PREDIV_DIV2)  || \
                                ((DIV) == RCC_HSE_PREDIV_DIV3)  || ((DIV) == RCC_HSE_PREDIV_DIV4)  || \
                                ((DIV) == RCC_HSE_PREDIV_DIV5)  || ((DIV) == RCC_HSE_PREDIV_DIV6)  || \
                                ((DIV) == RCC_HSE_PREDIV_DIV7)  || ((DIV) == RCC_HSE_PREDIV_DIV8)  || \
                                ((DIV) == RCC_HSE_PREDIV_DIV9)  || ((DIV) == RCC_HSE_PREDIV_DIV10) || \
                                ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \
                                ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \
                                ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16))

Definition at line 198 of file stm32f3xx_hal_rcc.h.

#define IS_RCC_HSI ( __HSI__ ) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))

Definition at line 179 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_I2C1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \
                                           ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))

Definition at line 251 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LSE ( __LSE__ )
Value:
(((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
                             ((__LSE__) == RCC_LSE_BYPASS))

Definition at line 177 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSI ( __LSI__ ) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))

Definition at line 181 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_MCO ( __MCO__ ) ((__MCO__) == RCC_MCO)

Definition at line 234 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_OSCILLATORTYPE ( __OSCILLATOR__ )
Value:
(((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))

Definition at line 170 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PCLK ( __PCLK__ )
Value:
(((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
                               ((__PCLK__) == RCC_HCLK_DIV16))

Definition at line 231 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_PLL ( __PLL__ )
Value:
(((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
                             ((__PLL__) == RCC_PLL_ON))

Definition at line 182 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLL_DIV ( __DIV__ )
Value:
(((__DIV__) == RCC_PLL_DIV2) || \
                                 ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))

Definition at line 194 of file stm32f3xx_hal_rcc.h.

#define IS_RCC_PLL_MUL ( __MUL__ )
Value:
(((__MUL__) == RCC_PLL_MUL2)  || ((__MUL__) == RCC_PLL_MUL3)   || \
                                 ((__MUL__) == RCC_PLL_MUL4)  || ((__MUL__) == RCC_PLL_MUL5)   || \
                                 ((__MUL__) == RCC_PLL_MUL6)  || ((__MUL__) == RCC_PLL_MUL7)   || \
                                 ((__MUL__) == RCC_PLL_MUL8)  || ((__MUL__) == RCC_PLL_MUL9)   || \
                                 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11)  || \
                                 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13)  || \
                                 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15)  || \
                                 ((__MUL__) == RCC_PLL_MUL16))

Definition at line 208 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))

Definition at line 168 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_RTCCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)  || \
                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)  || \
                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))

Definition at line 235 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SYSCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))

Definition at line 220 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_SYSCLKSOURCE_STATUS ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))

Definition at line 223 of file stm32f3xx_hal_rcc.h.

#define IS_RCC_USART2CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \
                                             ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
                                             ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \
                                             ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))

Definition at line 240 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USART3CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1)  || \
                                             ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
                                             ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)    || \
                                             ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))

Definition at line 246 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define MCO1_CLK_ENABLE ( ) __HAL_RCC_GPIOA_CLK_ENABLE()

Definition at line 109 of file stm32f3xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO1_GPIO_PORT GPIOA

Definition at line 110 of file stm32f3xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO1_PIN GPIO_PIN_8

Definition at line 111 of file stm32f3xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Private Variables

Variables
RCC Private Variables
RCC

Variables

const uint8_t | aPLLMULFactorTable [16]
const uint8_t | aPredivFactorTable [16]

Variable Documentation

const uint8_t aPLLMULFactorTable[16]
Initial value:
 { 2U,  3U,  4U,  5U,  6U,  7U,  8U,  9U,
                                       10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}

Definition at line 121 of file stm32f3xx_hal_rcc.c.

Referenced by HAL_RCC_GetSysClockFreq().

const uint8_t aPredivFactorTable[16]
Initial value:
 { 1U, 2U,  3U,  4U,  5U,  6U,  7U,  8U,
                                         9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}

Definition at line 123 of file stm32f3xx_hal_rcc.c.

Referenced by HAL_RCC_GetSysClockFreq().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RCC Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.

Detailed Description

Initialization and Configuration functions.

  ===============================================================================
           ##### Initialization and de-initialization functions #####
  ===============================================================================
    [..]
      This section provides functions allowing to configure the internal/external oscillators
      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
      and APB2).

    [..] Internal/external clock and PLL configuration
      (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
          the PLL as System clock source.
          The HSI clock can be used also to clock the USART and I2C peripherals.

      (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
          clock source.

      (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
          through the PLL as System clock source. Can be used also as RTC clock source.

      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.

      (#) PLL (clocked by HSI or HSE), featuring different output clocks:
        (++) The first output is used to generate the high speed system clock (up to 72 MHz)
        (++) The second output is used to generate the clock for the USB FS (48 MHz)
        (++) The third output may be used to generate the clock for the ADC peripherals (up to 72 MHz)
        (++) The fourth output may be used to generate the clock for the TIM peripherals (144 MHz)

      (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
          and if a HSE clock failure occurs(HSE used directly or through PLL as System
          clock source), the System clocks automatically switched to HSI and an interrupt
          is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
          (Non-Maskable Interrupt) exception vector.

      (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
          clock (divided by 2) output on pin (such as PA8 pin).

    [..] System, AHB and APB buses clocks configuration
      (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
          HSE and PLL.
          The AHB clock (HCLK) is derived from System clock through configurable
          prescaler and used to clock the CPU, memory and peripherals mapped
          on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
          from AHB clock through configurable prescalers and used to clock
          the peripherals mapped on these buses. You can use
          "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.

      (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
        (++) The FLASH program/erase clock  which is always HSI 8MHz clock.
        (++) The USB 48 MHz clock which is derived from the PLL VCO clock.
        (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
        (++) The I2C clock which can be derived as well from HSI 8MHz clock.
        (++) The ADC clock which is derived from PLL output.
        (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
             (HSE divided by a programmable prescaler). The System clock (SYSCLK)
             frequency must be higher or equal to the RTC clock frequency.
        (++) IWDG clock which is always the LSI clock.

         (#) For the STM32F3xx devices, the maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz,
             Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.

         (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
             prefetch is disabled.

Function Documentation

HAL_StatusTypeDef HAL_RCC_ClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t | FLatency
 | ) |  |

Initializes the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.

Parameters:
RCC_ClkInitStruct | pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC peripheral.
FLatency | FLASH Latency The value of this parameter depend on device used within the same series
Note:
The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated by HAL_RCC_GetHCLKFreq() function called within this function
The HSI is used (enabled by hardware) as system clock source after start-up from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after start-up delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use HAL_RCC_GetClockConfig() function to know which clock is currently used as system clock source.
Return values:
HAL status

Definition at line 626 of file stm32f3xx_hal_rcc.c.

References __HAL_FLASH_SET_LATENCY, __HAL_RCC_GET_FLAG, __HAL_RCC_GET_SYSCLK_SOURCE, __HAL_RCC_SYSCLK_CONFIG, RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, assert_param, CLOCKSWITCH_TIMEOUT_VALUE, RCC_ClkInitTypeDef::ClockType, HAL_GetTick(), HAL_InitTick(), HAL_RCC_GetSysClockFreq(), IS_FLASH_LATENCY, IS_RCC_CLOCKTYPE, IS_RCC_HCLK, IS_RCC_PCLK, IS_RCC_SYSCLKSOURCE, RCC_CFGR_HPRE_BITNUMBER, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, RCC_FLAG_HSERDY, RCC_FLAG_HSIRDY, RCC_FLAG_PLLRDY, RCC_SYSCLKSOURCE_HSE, RCC_SYSCLKSOURCE_PLLCLK, RCC_SYSCLKSOURCE_STATUS_HSE, RCC_SYSCLKSOURCE_STATUS_HSI, RCC_SYSCLKSOURCE_STATUS_PLLCLK, RCC_ClkInitTypeDef::SYSCLKSource, and TICK_INT_PRIORITY.

void HAL_RCC_DeInit ( void )

Resets the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • HSI ON and used as system clock source
  • HSE and PLL OFF
  • AHB, APB1 and APB2 prescaler set to 1.
  • CSS and MCO1 OFF
  • All interrupts disabled
This function does not modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
None

Definition at line 232 of file stm32f3xx_hal_rcc.c.

References HSI_VALUE.

HAL_StatusTypeDef HAL_RCC_OscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.

Parameters:
RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC Oscillators.
Note:
The PLL is not disabled when used as system clock.
Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. User should request a transition to HSE Off first and then HSE On or HSE Bypass.
Return values:
HAL status

Definition at line 276 of file stm32f3xx_hal_rcc.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_PLL_OSCSOURCE, __HAL_RCC_GET_SYSCLK_SOURCE, __HAL_RCC_HSE_CONFIG, __HAL_RCC_HSE_PREDIV_CONFIG, __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST, __HAL_RCC_HSI_DISABLE, __HAL_RCC_HSI_ENABLE, __HAL_RCC_LSE_CONFIG, __HAL_RCC_LSI_DISABLE, __HAL_RCC_LSI_ENABLE, __HAL_RCC_PLL_CONFIG, __HAL_RCC_PLL_DISABLE, __HAL_RCC_PLL_ENABLE, __HAL_RCC_PWR_CLK_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_PWR_IS_CLK_DISABLED, assert_param, HAL_GetTick(), HSE_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSEPredivValue, RCC_OscInitTypeDef::HSEState, HSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, IS_RCC_CALIBRATION_VALUE, IS_RCC_HSE, IS_RCC_HSI, IS_RCC_LSE, IS_RCC_LSI, IS_RCC_OSCILLATORTYPE, IS_RCC_PLL, IS_RCC_PLL_MUL, IS_RCC_PLLSOURCE, RCC_OscInitTypeDef::LSEState, LSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, PLL_TIMEOUT_VALUE, RCC_PLLInitTypeDef::PLLMUL, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_DBP_TIMEOUT_VALUE, RCC_FLAG_HSERDY, RCC_FLAG_HSIRDY, RCC_FLAG_LSERDY, RCC_FLAG_LSIRDY, RCC_FLAG_PLLRDY, RCC_HSE_OFF, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_OFF, RCC_LSE_TIMEOUT_VALUE, RCC_LSI_OFF, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_LSE, RCC_OSCILLATORTYPE_LSI, RCC_PLL_NONE, RCC_PLL_ON, RCC_PLLSOURCE_HSE, RCC_PLLSOURCE_HSI, RCC_SYSCLKSOURCE_STATUS_HSE, RCC_SYSCLKSOURCE_STATUS_HSI, and RCC_SYSCLKSOURCE_STATUS_PLLCLK.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RCC Exported Functions

RCC clocks control functions. More...

Functions

void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO pin.
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_DisableCSS (void)
Disables the Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

RCC clocks control functions.

  ===============================================================================
                  ##### Peripheral Control functions #####
  ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.

Function Documentation

void HAL_RCC_CSSCallback ( void )

RCC Clock Security System interrupt callback.

Return values:
none

Definition at line 1147 of file stm32f3xx_hal_rcc.c.

Referenced by HAL_RCC_NMI_IRQHandler().

void HAL_RCC_DisableCSS ( void )

Disables the Clock Security System.

Return values:
None

Definition at line 878 of file stm32f3xx_hal_rcc.c.

References RCC_CR_CSSON_BB.

void HAL_RCC_EnableCSS ( void )

Enables the Clock Security System.

Note:
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
Return values:
None

Definition at line 869 of file stm32f3xx_hal_rcc.c.

References RCC_CR_CSSON_BB.

void HAL_RCC_GetClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t * | pFLatency
 | ) |  |

Get the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_ClkInitStruct | pointer to an RCC_ClkInitTypeDef structure that contains the current clock configuration.
pFLatency | Pointer on the Flash Latency.
Return values:
None

Definition at line 1100 of file stm32f3xx_hal_rcc.c.

References RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, assert_param, RCC_ClkInitTypeDef::ClockType, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, and RCC_ClkInitTypeDef::SYSCLKSource.

uint32_t HAL_RCC_GetHCLKFreq ( void )

Returns the HCLK frequency.

Note:
Each time HCLK changes, this function must be called to update the right HCLK value. Otherwise, any configuration based on this function will be incorrect.
The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated within this function
Return values:
HCLK frequency

Definition at line 976 of file stm32f3xx_hal_rcc.c.

Referenced by HAL_RCC_GetPCLK1Freq(), and HAL_RCC_GetPCLK2Freq().

void HAL_RCC_GetOscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Configures the RCC_OscInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured.
Return values:
None

Definition at line 1012 of file stm32f3xx_hal_rcc.c.

References __HAL_RCC_HSE_GET_PREDIV, assert_param, RCC_OscInitTypeDef::HSEPredivValue, RCC_OscInitTypeDef::HSEState, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, RCC_OscInitTypeDef::LSEState, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, RCC_PLLInitTypeDef::PLLMUL, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_HSE_BYPASS, RCC_HSE_OFF, RCC_HSE_ON, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_BYPASS, RCC_LSE_OFF, RCC_LSE_ON, RCC_LSI_OFF, RCC_LSI_ON, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_LSE, RCC_OSCILLATORTYPE_LSI, RCC_PLL_OFF, and RCC_PLL_ON.

uint32_t HAL_RCC_GetPCLK1Freq ( void )

Returns the PCLK1 frequency.

Note:
Each time PCLK1 changes, this function must be called to update the right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK1 frequency

Definition at line 987 of file stm32f3xx_hal_rcc.c.

References HAL_RCC_GetHCLKFreq(), and RCC_CFGR_PPRE1_BITNUMBER.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetPCLK2Freq ( void )

Returns the PCLK2 frequency.

Note:
Each time PCLK2 changes, this function must be called to update the right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK2 frequency

Definition at line 999 of file stm32f3xx_hal_rcc.c.

References HAL_RCC_GetHCLKFreq(), and RCC_CFGR_PPRE2_BITNUMBER.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetSysClockFreq ( void )

Returns the SYSCLK frequency.

Note:
The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
If SYSCLK source is HSE, function returns a value based on HSE_VALUE divided by PREDIV factor(**)
If SYSCLK source is PLL, function returns a value based on HSE_VALUE divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
(*) HSI_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value 8 MHz) but the real value may vary depending on the variations in voltage and temperature.
(**) HSE_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be not correct when using fractional value for HSE crystal.
This function can be used by the user application to compute the baud-rate for the communication peripherals or configure other parameters.
Each time SYSCLK changes, this function must be called to update the right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
Return values:
SYSCLK frequency

Definition at line 912 of file stm32f3xx_hal_rcc.c.

References aPLLMULFactorTable, aPredivFactorTable, HSE_VALUE, HSI_VALUE, RCC_PLLSOURCE_HSI, RCC_SYSCLKSOURCE_STATUS_HSE, RCC_SYSCLKSOURCE_STATUS_HSI, and RCC_SYSCLKSOURCE_STATUS_PLLCLK.

Referenced by HAL_RCC_ClockConfig(), HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

void HAL_RCC_MCOConfig | ( | uint32_t | RCC_MCOx,
 |  | uint32_t | RCC_MCOSource,
 |  | uint32_t | RCC_MCODiv
 | ) |  |

Selects the clock source to output on MCO pin.

Note:
MCO pin should be configured in alternate function mode.
Parameters:
RCC_MCOx specifies the output direction for the clock source. This parameter can be one of the following values:
  • RCC_MCO1 Clock source to output on MCO1 pin(PA8).
RCC_MCOSource specifies the clock source to output. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
  • RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
  • RCC_MCO1SOURCE_HSI HSI selected as MCO clock
  • RCC_MCO1SOURCE_HSE HSE selected as MCO clock
  • RCC_MCO1SOURCE_LSI LSI selected as MCO clock
  • RCC_MCO1SOURCE_LSE LSE selected as MCO clock
  • RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
RCC_MCODiv specifies the MCO DIV. This parameter can be one of the following values:
  • RCC_MCODIV_1 no division applied to MCO clock
Return values:
None

Definition at line 835 of file stm32f3xx_hal_rcc.c.

References __HAL_RCC_MCO1_CONFIG, GPIO_InitTypeDef::Alternate, assert_param, GPIO_AF0_MCO, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_SPEED_FREQ_HIGH, HAL_GPIO_Init(), IS_RCC_MCO, IS_RCC_MCO1SOURCE, IS_RCC_MCODIV, MCO1_CLK_ENABLE, MCO1_GPIO_PORT, MCO1_PIN, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, and GPIO_InitTypeDef::Speed.

void HAL_RCC_NMI_IRQHandler ( void )

This function handles the RCC CSS interrupt request.

Note:
This API should be called under the NMI_Handler().
Return values:
None

Definition at line 1130 of file stm32f3xx_hal_rcc.c.

References __HAL_RCC_CLEAR_IT, __HAL_RCC_GET_IT, HAL_RCC_CSSCallback(), and RCC_IT_CSS.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC_PLLInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLLInitTypeDef Struct Reference
RCC Exported Types

RCC PLL configuration structure definition. More...

#include <stm32f3xx_hal_rcc.h>

Data Fields

uint32_t | PLLState
uint32_t | PLLSource
uint32_t | PLLMUL

Detailed Description

RCC PLL configuration structure definition.

Definition at line 267 of file stm32f3xx_hal_rcc.h.

Field Documentation

uint32_t RCC_PLLInitTypeDef::PLLMUL

PLLMUL: Multiplication factor for PLL VCO input clock This parameter must be a value of RCC PLL Multiplication Factor

Definition at line 275 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLSource

PLLSource: PLL entry clock source. This parameter must be a value of PLL Clock Source

Definition at line 272 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLState

PLLState: The new state of the PLL. This parameter can be a value of PLL Config

Definition at line 269 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_rcc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC_OscInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_OscInitTypeDef Struct Reference
RCC Exported Types

RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...

#include <stm32f3xx_hal_rcc.h>

Data Fields

uint32_t | OscillatorType
uint32_t | HSEState
uint32_t | HSEPredivValue
uint32_t | LSEState
uint32_t | HSIState
uint32_t | HSICalibrationValue
uint32_t | LSIState
RCC_PLLInitTypeDef PLL

Detailed Description

RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition.

Definition at line 288 of file stm32f3xx_hal_rcc.h.

Field Documentation

uint32_t RCC_OscInitTypeDef::HSEPredivValue

The HSE predivision factor value. This parameter can be a value of RCC PLL HSE Prediv Factor

Definition at line 297 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSEState

The new state of the HSE. This parameter can be a value of HSE Config

Definition at line 293 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSICalibrationValue

The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU

Definition at line 307 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSIState

The new state of the HSI. This parameter can be a value of HSI Config

Definition at line 304 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSEState

The new state of the LSE. This parameter can be a value of LSE Config

Definition at line 301 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSIState

The new state of the LSI. This parameter can be a value of LSI Config

Definition at line 310 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::OscillatorType

The oscillators to be configured. This parameter can be a value of Oscillator Type

Definition at line 290 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

RCC_PLLInitTypeDef RCC_OscInitTypeDef::PLL

PLL structure parameters

Definition at line 313 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_rcc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC_ClkInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_ClkInitTypeDef Struct Reference
RCC Exported Types

RCC System, AHB and APB busses clock configuration structure definition. More...

#include <stm32f3xx_hal_rcc.h>

Data Fields

uint32_t | ClockType
uint32_t | SYSCLKSource
uint32_t | AHBCLKDivider
uint32_t | APB1CLKDivider
uint32_t | APB2CLKDivider

Detailed Description

RCC System, AHB and APB busses clock configuration structure definition.

Definition at line 320 of file stm32f3xx_hal_rcc.h.

Field Documentation

uint32_t RCC_ClkInitTypeDef::AHBCLKDivider

The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB Clock Source

Definition at line 328 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB1CLKDivider

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB1 APB2 Clock Source

Definition at line 331 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB2CLKDivider

The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB1 APB2 Clock Source

Definition at line 334 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::ClockType

The clock to be configured. This parameter can be a value of System Clock Type

Definition at line 322 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::SYSCLKSource

The clock source (SYSCLKS) used as system clock. This parameter can be a value of System Clock Source

Definition at line 325 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_rcc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PLL Clock Source

Defines
PLL Clock Source
RCC Exported Constants

Defines

#define | RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
#define | RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV

Define Documentation

#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV

HSE clock selected as PLL entry clock source

Definition at line 357 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2

HSI clock divided by 2 selected as PLL entry clock source

Definition at line 355 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCC_OscConfig(), and RCC_GetPLLCLKFreq().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Oscillator Type

Defines
Oscillator Type
RCC Exported Constants

Defines

#define | RCC_OSCILLATORTYPE_NONE (0x00000000U)
#define | RCC_OSCILLATORTYPE_HSE (0x00000001U)
#define | RCC_OSCILLATORTYPE_HSI (0x00000002U)
#define | RCC_OSCILLATORTYPE_LSE (0x00000004U)
#define | RCC_OSCILLATORTYPE_LSI (0x00000008U)

Define Documentation

#define RCC_OSCILLATORTYPE_HSE (0x00000001U)

Definition at line 367 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_HSI (0x00000002U)

Definition at line 368 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSE (0x00000004U)

Definition at line 369 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSI (0x00000008U)

Definition at line 370 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_NONE (0x00000000U)

Definition at line 366 of file stm32f3xx_hal_rcc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HSE Config

Defines
HSE Config
RCC Exported Constants

Defines

#define | RCC_HSE_OFF (0x00000000U)
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))

Define Documentation

#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))

External clock source for HSE clock

Definition at line 380 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_HSE_OFF (0x00000000U)

HSE clock deactivation

Definition at line 378 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSE_ON RCC_CR_HSEON

HSE clock activation

Definition at line 379 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LSE Config

Defines
LSE Config
RCC Exported Constants

Defines

#define | RCC_LSE_OFF (0x00000000U)
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

Define Documentation

#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

External clock source for LSE clock

Definition at line 390 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_LSE_OFF (0x00000000U)

LSE clock deactivation

Definition at line 388 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSE_ON RCC_BDCR_LSEON

LSE clock activation

Definition at line 389 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HSI Config

Defines
HSI Config
RCC Exported Constants

Defines

#define | RCC_HSI_OFF (0x00000000U)
#define | RCC_HSI_ON RCC_CR_HSION
#define | RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */

Define Documentation

#define RCC_HSI_OFF (0x00000000U)

HSI clock deactivation

Definition at line 399 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSI_ON RCC_CR_HSION

HSI clock activation

Definition at line 400 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */

Definition at line 402 of file stm32f3xx_hal_rcc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LSI Config

Defines
LSI Config
RCC Exported Constants

Defines

#define | RCC_LSI_OFF (0x00000000U)
#define | RCC_LSI_ON RCC_CSR_LSION

Define Documentation

#define RCC_LSI_OFF (0x00000000U)

LSI clock deactivation

Definition at line 411 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSI_ON RCC_CSR_LSION

LSI clock activation

Definition at line 412 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PLL Config

Defines
PLL Config
RCC Exported Constants

Defines

#define | RCC_PLL_NONE (0x00000000U)
#define | RCC_PLL_OFF (0x00000001U)
#define | RCC_PLL_ON (0x00000002U)

Define Documentation

#define RCC_PLL_NONE (0x00000000U)

PLL is not configured

Definition at line 421 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_PLL_OFF (0x00000001U)

PLL deactivation

Definition at line 422 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_PLL_ON (0x00000002U)

PLL activation

Definition at line 423 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

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STM32F373xC HAL User Manual: System Clock Type

Defines
System Clock Type
RCC Exported Constants

Defines

#define | RCC_CLOCKTYPE_SYSCLK (0x00000001U)
#define | RCC_CLOCKTYPE_HCLK (0x00000002U)
#define | RCC_CLOCKTYPE_PCLK1 (0x00000004U)
#define | RCC_CLOCKTYPE_PCLK2 (0x00000008U)

Define Documentation

#define RCC_CLOCKTYPE_HCLK (0x00000002U)

HCLK to configure

Definition at line 433 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK1 (0x00000004U)

PCLK1 to configure

Definition at line 434 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK2 (0x00000008U)

PCLK2 to configure

Definition at line 435 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_SYSCLK (0x00000001U)

SYSCLK to configure

Definition at line 432 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

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STM32F373xC HAL User Manual: System Clock Source

Defines
System Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL

Define Documentation

#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE

HSE selected as system clock

Definition at line 445 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI

HSI selected as system clock

Definition at line 444 of file stm32f3xx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL

PLL selected as system clock

Definition at line 446 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

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STM32F373xC HAL User Manual: System Clock Source Status

Defines
System Clock Source Status
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL

Define Documentation

#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE

HSE used as system clock

Definition at line 456 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI

HSI used as system clock

Definition at line 455 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL

PLL used as system clock

Definition at line 457 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: AHB Clock Source

Defines
AHB Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
#define | RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
#define | RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
#define | RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
#define | RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
#define | RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
#define | RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
#define | RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
#define | RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512

Define Documentation

#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1

SYSCLK not divided

Definition at line 466 of file stm32f3xx_hal_rcc.h.

#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128

SYSCLK divided by 128

Definition at line 472 of file stm32f3xx_hal_rcc.h.

#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16

SYSCLK divided by 16

Definition at line 470 of file stm32f3xx_hal_rcc.h.

#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2

SYSCLK divided by 2

Definition at line 467 of file stm32f3xx_hal_rcc.h.

#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256

SYSCLK divided by 256

Definition at line 473 of file stm32f3xx_hal_rcc.h.

#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4

SYSCLK divided by 4

Definition at line 468 of file stm32f3xx_hal_rcc.h.

#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512

SYSCLK divided by 512

Definition at line 474 of file stm32f3xx_hal_rcc.h.

#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64

SYSCLK divided by 64

Definition at line 471 of file stm32f3xx_hal_rcc.h.

#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8

SYSCLK divided by 8

Definition at line 469 of file stm32f3xx_hal_rcc.h.

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STM32F373xC HAL User Manual: APB1 APB2 Clock Source

Defines
APB1 APB2 Clock Source
RCC Exported Constants

Defines

#define | RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
#define | RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
#define | RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
#define | RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
#define | RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16

Define Documentation

#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1

HCLK not divided

Definition at line 483 of file stm32f3xx_hal_rcc.h.

#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16

HCLK divided by 16

Definition at line 487 of file stm32f3xx_hal_rcc.h.

#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2

HCLK divided by 2

Definition at line 484 of file stm32f3xx_hal_rcc.h.

#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4

HCLK divided by 4

Definition at line 485 of file stm32f3xx_hal_rcc.h.

#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8

HCLK divided by 8

Definition at line 486 of file stm32f3xx_hal_rcc.h.

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STM32F373xC HAL User Manual: RTC Clock Source

Defines
RTC Clock Source
RCC Exported Constants

Defines

#define | RCC_RTCCLKSOURCE_NO_CLK RCC_BDCR_RTCSEL_NOCLOCK
#define | RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
#define | RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
#define | RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE

Define Documentation

#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE

HSE oscillator clock divided by 32 used as RTC clock

Definition at line 499 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE

LSE oscillator clock used as RTC clock

Definition at line 497 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI

LSI oscillator clock used as RTC clock

Definition at line 498 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RTCCLKSOURCE_NO_CLK RCC_BDCR_RTCSEL_NOCLOCK

No clock

Definition at line 496 of file stm32f3xx_hal_rcc.h.

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STM32F373xC HAL User Manual: RCC PLL Multiplication Factor

Defines
RCC PLL Multiplication Factor
RCC Exported Constants

Defines

#define | RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
#define | RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
#define | RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
#define | RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
#define | RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
#define | RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
#define | RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
#define | RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
#define | RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
#define | RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
#define | RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
#define | RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
#define | RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
#define | RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
#define | RCC_PLL_MUL16 RCC_CFGR_PLLMUL16

Define Documentation

#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10

Definition at line 515 of file stm32f3xx_hal_rcc.h.

#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11

Definition at line 516 of file stm32f3xx_hal_rcc.h.

#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12

Definition at line 517 of file stm32f3xx_hal_rcc.h.

#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13

Definition at line 518 of file stm32f3xx_hal_rcc.h.

#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14

Definition at line 519 of file stm32f3xx_hal_rcc.h.

#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15

Definition at line 520 of file stm32f3xx_hal_rcc.h.

#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16

Definition at line 521 of file stm32f3xx_hal_rcc.h.

#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2

Definition at line 507 of file stm32f3xx_hal_rcc.h.

#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3

Definition at line 508 of file stm32f3xx_hal_rcc.h.

#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4

Definition at line 509 of file stm32f3xx_hal_rcc.h.

#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5

Definition at line 510 of file stm32f3xx_hal_rcc.h.

#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6

Definition at line 511 of file stm32f3xx_hal_rcc.h.

#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7

Definition at line 512 of file stm32f3xx_hal_rcc.h.

#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8

Definition at line 513 of file stm32f3xx_hal_rcc.h.

#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9

Definition at line 514 of file stm32f3xx_hal_rcc.h.

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STM32F373xC HAL User Manual: RCC PLL HSE Prediv Factor

Defines
RCC PLL HSE Prediv Factor
RCC Exported Constants

Defines

#define | RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
#define | RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
#define | RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
#define | RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
#define | RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
#define | RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
#define | RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
#define | RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
#define | RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
#define | RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
#define | RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
#define | RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
#define | RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
#define | RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
#define | RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
#define | RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16

Define Documentation

#define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1

Definition at line 559 of file stm32f3xx_hal_rcc.h.

#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10

Definition at line 568 of file stm32f3xx_hal_rcc.h.

#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11

Definition at line 569 of file stm32f3xx_hal_rcc.h.

#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12

Definition at line 570 of file stm32f3xx_hal_rcc.h.

#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13

Definition at line 571 of file stm32f3xx_hal_rcc.h.

#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14

Definition at line 572 of file stm32f3xx_hal_rcc.h.

#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15

Definition at line 573 of file stm32f3xx_hal_rcc.h.

#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16

Definition at line 574 of file stm32f3xx_hal_rcc.h.

#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2

Definition at line 560 of file stm32f3xx_hal_rcc.h.

#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3

Definition at line 561 of file stm32f3xx_hal_rcc.h.

#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4

Definition at line 562 of file stm32f3xx_hal_rcc.h.

#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5

Definition at line 563 of file stm32f3xx_hal_rcc.h.

#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6

Definition at line 564 of file stm32f3xx_hal_rcc.h.

#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7

Definition at line 565 of file stm32f3xx_hal_rcc.h.

#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8

Definition at line 566 of file stm32f3xx_hal_rcc.h.

#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9

Definition at line 567 of file stm32f3xx_hal_rcc.h.

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STM32F373xC HAL User Manual: RCC USART2 Clock Source

Defines
RCC USART2 Clock Source
RCC Exported Constants

Defines

#define | RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
#define | RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
#define | RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
#define | RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI

Define Documentation

#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI

Definition at line 588 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE

Definition at line 587 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK

Definition at line 585 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK

Definition at line 586 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32F373xC HAL User Manual: RCC USART3 Clock Source

Defines
RCC USART3 Clock Source
RCC Exported Constants

Defines

#define | RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
#define | RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
#define | RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
#define | RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI

Define Documentation

#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI

Definition at line 602 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE

Definition at line 601 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK

Definition at line 599 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK

Definition at line 600 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32F373xC HAL User Manual: RCC I2C1 Clock Source

Defines
RCC I2C1 Clock Source
RCC Exported Constants

Defines

#define | RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
#define | RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK

Define Documentation

#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI

Definition at line 612 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK

Definition at line 613 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32F373xC HAL User Manual: MCO Index

Defines
MCO Index
RCC Exported Constants

Defines

#define | RCC_MCO1 (0x00000000U)
#define | RCC_MCO RCC_MCO1

Define Documentation

#define RCC_MCO RCC_MCO1

MCO1 to be compliant with other families with 2 MCOs

Definition at line 622 of file stm32f3xx_hal_rcc.h.

#define RCC_MCO1 (0x00000000U)

Definition at line 621 of file stm32f3xx_hal_rcc.h.

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STM32F373xC HAL User Manual: Interrupts

Defines
Interrupts
RCC Exported Constants

Defines

#define | RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF)
#define | RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF)
#define | RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF)
#define | RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF)
#define | RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF)
#define | RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF)

Define Documentation

#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF)

Clock Security System Interrupt flag

Definition at line 636 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF)

HSE Ready Interrupt flag

Definition at line 634 of file stm32f3xx_hal_rcc.h.

#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF)

HSI Ready Interrupt flag

Definition at line 633 of file stm32f3xx_hal_rcc.h.

#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF)

LSE Ready Interrupt flag

Definition at line 632 of file stm32f3xx_hal_rcc.h.

#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF)

LSI Ready Interrupt flag

Definition at line 631 of file stm32f3xx_hal_rcc.h.

#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF)

PLL Ready Interrupt flag

Definition at line 635 of file stm32f3xx_hal_rcc.h.

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STM32F373xC HAL User Manual: Flags

Defines
Flags
RCC Exported Constants

Elements values convention: XXXYYYYYb. More...

Defines

#define | RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY)))
#define | RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY)))
#define | RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY)))
#define | RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY)))
#define | RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_V18PWRRSTF)))
#define | RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF)))
#define | RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF)))
#define | RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF)))
#define | RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF)))
#define | RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF)))
#define | RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF)))
#define | RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF)))
#define | RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY)))

Detailed Description

Elements values convention: XXXYYYYYb.

  • YYYYY : Flag position in the register
  • XXX : Register index
    • 001: CR register
    • 010: BDCR register
    • 011: CSR register
    • 100: CFGR register

Define Documentation

#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY)))

External High Speed clock ready flag

Definition at line 653 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY)))

Internal High Speed clock ready flag

Definition at line 652 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF)))

Independent Watchdog reset flag

Definition at line 665 of file stm32f3xx_hal_rcc.h.

#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF)))

Low-Power reset flag

Definition at line 667 of file stm32f3xx_hal_rcc.h.

#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY)))

External Low Speed oscillator Ready

Definition at line 670 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY)))

Internal Low Speed oscillator Ready

Definition at line 657 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF)))

Options bytes loading reset flag

Definition at line 661 of file stm32f3xx_hal_rcc.h.

#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF)))

PIN reset flag

Definition at line 662 of file stm32f3xx_hal_rcc.h.

#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY)))

PLL clock ready flag

Definition at line 654 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF)))

POR/PDR reset flag

Definition at line 663 of file stm32f3xx_hal_rcc.h.

#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF)))

Software Reset flag

Definition at line 664 of file stm32f3xx_hal_rcc.h.

#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_V18PWRRSTF)))

Definition at line 659 of file stm32f3xx_hal_rcc.h.

#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF)))

Window watchdog reset flag

Definition at line 666 of file stm32f3xx_hal_rcc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC AHB Clock Enable Disable

Defines
RCC AHB Clock Enable Disable
RCC Exported Macros

Enable or disable the AHB peripheral clock. More...

Defines

#define | __HAL_RCC_GPIOA_CLK_ENABLE()
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOD_CLK_ENABLE()
#define | __HAL_RCC_GPIOF_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_ENABLE()
#define | __HAL_RCC_SRAM_CLK_ENABLE()
#define | __HAL_RCC_FLITF_CLK_ENABLE()
#define | __HAL_RCC_TSC_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
#define | __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
#define | __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
#define | __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
#define | __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
#define | __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
#define | __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
#define | __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
#define | __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
#define | __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))

Detailed Description

Enable or disable the AHB peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CRC_CLK_DISABLE ( ) (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))

Definition at line 774 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 733 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_DISABLE ( ) (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))

Definition at line 775 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 740 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_FLITF_CLK_DISABLE ( ) (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))

Definition at line 777 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_FLITF_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 754 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_DISABLE ( ) (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))

Definition at line 769 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 698 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_DISABLE ( ) (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))

Definition at line 770 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 705 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_DISABLE ( ) (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))

Definition at line 771 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 712 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_DISABLE ( ) (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))

Definition at line 772 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 719 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_DISABLE ( ) (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))

Definition at line 773 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 726 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_SRAM_CLK_DISABLE ( ) (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))

Definition at line 776 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_SRAM_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 747 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TSC_CLK_DISABLE ( ) (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))

Definition at line 778 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TSC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 761 of file stm32f3xx_hal_rcc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC APB1 Clock Enable Disable

Defines
RCC APB1 Clock Enable Disable
RCC Exported Macros

Enable or disable the Low Speed APB (APB1) peripheral clock. More...

Defines

#define | __HAL_RCC_TIM2_CLK_ENABLE()
#define | __HAL_RCC_TIM6_CLK_ENABLE()
#define | __HAL_RCC_WWDG_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_USART3_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_PWR_CLK_ENABLE()
#define | __HAL_RCC_DAC1_CLK_ENABLE()
#define | __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
#define | __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
#define | __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define | __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define | __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
#define | __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
#define | __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
#define | __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))

Detailed Description

Enable or disable the Low Speed APB (APB1) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_DAC1_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))

Definition at line 854 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_DAC1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 839 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))

Definition at line 852 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 825 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Definition at line 853 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PWR_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 832 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_PWREx_EnableSDADC(), HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_TIM2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))

Definition at line 847 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 790 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))

Definition at line 848 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 797 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))

Definition at line 850 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 811 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))

Definition at line 851 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 818 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))

Definition at line 849 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 804 of file stm32f3xx_hal_rcc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC APB2 Clock Enable Disable

Defines
RCC APB2 Clock Enable Disable
RCC Exported Macros

Enable or disable the High Speed APB (APB2) peripheral clock. More...

Defines

#define | __HAL_RCC_SYSCFG_CLK_ENABLE()
#define | __HAL_RCC_TIM15_CLK_ENABLE()
#define | __HAL_RCC_TIM16_CLK_ENABLE()
#define | __HAL_RCC_TIM17_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
#define | __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
#define | __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
#define | __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
#define | __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))

Detailed Description

Enable or disable the High Speed APB (APB2) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_SYSCFG_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))

Definition at line 902 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 866 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_COMP_Init(), HAL_GPIO_Init(), HAL_I2CEx_DisableFastModePlus(), and HAL_I2CEx_EnableFastModePlus().

#define __HAL_RCC_TIM15_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))

Definition at line 903 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 873 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))

Definition at line 904 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 880 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))

Definition at line 905 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 887 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))

Definition at line 906 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 894 of file stm32f3xx_hal_rcc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: AHB Peripheral Clock Enable Disable Status

Defines
AHB Peripheral Clock Enable Disable Status
RCC Exported Macros

Get the enable or disable status of the AHB peripheral clock. More...

Defines

#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
#define | __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
#define | __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
#define | __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
#define | __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
#define | __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
#define | __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
#define | __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)

Detailed Description

Get the enable or disable status of the AHB peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CRC_IS_CLK_DISABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)

Definition at line 934 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_ENABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)

Definition at line 923 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_DISABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)

Definition at line 935 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_ENABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)

Definition at line 924 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_FLITF_IS_CLK_DISABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)

Definition at line 937 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_FLITF_IS_CLK_ENABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)

Definition at line 926 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_DISABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)

Definition at line 929 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_ENABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)

Definition at line 918 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_DISABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)

Definition at line 930 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_ENABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)

Definition at line 919 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_DISABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)

Definition at line 931 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_ENABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)

Definition at line 920 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_DISABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)

Definition at line 932 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_ENABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)

Definition at line 921 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_DISABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)

Definition at line 933 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_ENABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)

Definition at line 922 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_SRAM_IS_CLK_DISABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)

Definition at line 936 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_SRAM_IS_CLK_ENABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)

Definition at line 925 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TSC_IS_CLK_DISABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)

Definition at line 938 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TSC_IS_CLK_ENABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)

Definition at line 927 of file stm32f3xx_hal_rcc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: APB1 Peripheral Clock Enable Disable Status

Defines
APB1 Peripheral Clock Enable Disable Status
RCC Exported Macros

Get the enable or disable status of the APB1 peripheral clock. More...

Defines

#define | __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
#define | __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
#define | __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
#define | __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
#define | __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
#define | __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
#define | __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
#define | __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
#define | __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
#define | __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
#define | __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
#define | __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
#define | __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)

Detailed Description

Get the enable or disable status of the APB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_DAC1_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)

Definition at line 966 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_DAC1_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)

Definition at line 957 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)

Definition at line 964 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)

Definition at line 955 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_PWR_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)

Definition at line 965 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PWR_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)

Definition at line 956 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)

Definition at line 959 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)

Definition at line 950 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)

Definition at line 960 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)

Definition at line 951 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)

Definition at line 962 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)

Definition at line 953 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)

Definition at line 963 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)

Definition at line 954 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)

Definition at line 961 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)

Definition at line 952 of file stm32f3xx_hal_rcc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: APB2 Peripheral Clock Enable Disable Status

Defines
APB2 Peripheral Clock Enable Disable Status
RCC Exported Macros

EGet the enable or disable status of the APB2 peripheral clock. More...

Defines

#define | __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
#define | __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
#define | __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
#define | __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
#define | __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
#define | __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
#define | __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)

Detailed Description

EGet the enable or disable status of the APB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)

Definition at line 984 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)

Definition at line 978 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)

Definition at line 985 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)

Definition at line 979 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)

Definition at line 986 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)

Definition at line 980 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)

Definition at line 987 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)

Definition at line 981 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)

Definition at line 988 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)

Definition at line 982 of file stm32f3xx_hal_rcc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC AHB Force Release Reset

Defines
RCC AHB Force Release Reset
RCC Exported Macros

Force or release AHB peripheral reset. More...

Defines

#define | __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
#define | __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
#define | __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
#define | __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
#define | __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
#define | __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
#define | __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
#define | __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
#define | __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
#define | __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
#define | __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
#define | __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
#define | __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))

Detailed Description

Force or release AHB peripheral reset.

Define Documentation

#define __HAL_RCC_AHB_FORCE_RESET ( ) (RCC->AHBRSTR = 0xFFFFFFFFU)

Definition at line 997 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB_RELEASE_RESET ( ) (RCC->AHBRSTR = 0x00000000U)

Definition at line 1005 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_GPIOA_FORCE_RESET ( ) (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))

Definition at line 998 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_RELEASE_RESET ( ) (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))

Definition at line 1006 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_FORCE_RESET ( ) (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))

Definition at line 999 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_RELEASE_RESET ( ) (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))

Definition at line 1007 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_FORCE_RESET ( ) (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))

Definition at line 1000 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_RELEASE_RESET ( ) (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))

Definition at line 1008 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_FORCE_RESET ( ) (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))

Definition at line 1001 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_RELEASE_RESET ( ) (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))

Definition at line 1009 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_FORCE_RESET ( ) (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))

Definition at line 1002 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_RELEASE_RESET ( ) (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))

Definition at line 1010 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TSC_FORCE_RESET ( ) (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))

Definition at line 1003 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TSC_RELEASE_RESET ( ) (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))

Definition at line 1011 of file stm32f3xx_hal_rcc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC APB1 Force Release Reset

Defines
RCC APB1 Force Release Reset
RCC Exported Macros

Force or release APB1 peripheral reset. More...

Defines

#define | __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
#define | __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
#define | __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
#define | __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
#define | __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
#define | __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
#define | __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
#define | __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST))
#define | __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
#define | __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
#define | __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
#define | __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
#define | __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
#define | __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
#define | __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
#define | __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
#define | __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))

Detailed Description

Force or release APB1 peripheral reset.

Define Documentation

#define __HAL_RCC_APB1_FORCE_RESET ( ) (RCC->APB1RSTR = 0xFFFFFFFFU)

Definition at line 1020 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB1_RELEASE_RESET ( ) (RCC->APB1RSTR = 0x00000000U)

Definition at line 1030 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_DAC1_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST))

Definition at line 1028 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_DAC1_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))

Definition at line 1038 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_I2C1_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))

Definition at line 1026 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_I2C1_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))

Definition at line 1036 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_PWR_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))

Definition at line 1027 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_PWR_DeInit().

#define __HAL_RCC_PWR_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))

Definition at line 1037 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_PWR_DeInit().

#define __HAL_RCC_TIM2_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))

Definition at line 1021 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM2_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))

Definition at line 1031 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM6_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))

Definition at line 1022 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM6_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))

Definition at line 1032 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART2_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))

Definition at line 1024 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART2_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))

Definition at line 1034 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART3_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))

Definition at line 1025 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART3_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))

Definition at line 1035 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_WWDG_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))

Definition at line 1023 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_WWDG_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))

Definition at line 1033 of file stm32f3xx_hal_rcc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC APB2 Force Release Reset

Defines
RCC APB2 Force Release Reset
RCC Exported Macros

Force or release APB2 peripheral reset. More...

Defines

#define | __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
#define | __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
#define | __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
#define | __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
#define | __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
#define | __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
#define | __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
#define | __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
#define | __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
#define | __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
#define | __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))

Detailed Description

Force or release APB2 peripheral reset.

Define Documentation

#define __HAL_RCC_APB2_FORCE_RESET ( ) (RCC->APB2RSTR = 0xFFFFFFFFU)

Definition at line 1047 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB2_RELEASE_RESET ( ) (RCC->APB2RSTR = 0x00000000U)

Definition at line 1054 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_SYSCFG_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))

Definition at line 1048 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))

Definition at line 1055 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM15_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))

Definition at line 1049 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM15_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))

Definition at line 1056 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM16_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))

Definition at line 1050 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM16_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))

Definition at line 1057 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM17_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))

Definition at line 1051 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_TIM17_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))

Definition at line 1058 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART1_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))

Definition at line 1052 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_USART1_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))

Definition at line 1059 of file stm32f3xx_hal_rcc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HSI Configuration

Defines
HSI Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
Macros to enable or disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

Define Documentation

#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST ( _HSICALIBRATIONVALUE_ ) (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))

Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.
Parameters:
_HSICALIBRATIONVALUE_ specifies the calibration trimming value. (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between 0 and 0x1F.

Definition at line 1092 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_DISABLE ( ) (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)

Definition at line 1083 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_ENABLE ( ) (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)

Macros to enable or disable the Internal High Speed oscillator (HSI).

Note:
The HSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.
After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source.
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.

Definition at line 1082 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LSI Configuration

Defines
LSI Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
Macro to enable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
Macro to disable the Internal Low Speed oscillator (LSI).

Define Documentation

#define __HAL_RCC_LSI_DISABLE ( ) (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)

Macro to disable the Internal Low Speed oscillator (LSI).

Note:
LSI can not be disabled if the IWDG is running.
When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.

Definition at line 1115 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSI_ENABLE ( ) (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)

Macro to enable the Internal Low Speed oscillator (LSI).

Note:
After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.

Definition at line 1108 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HSE Configuration

Defines
HSE Configuration
RCC Exported Macros

Defines

#define __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (HSE).

Define Documentation

#define __HAL_RCC_HSE_CONFIG ( __STATE__ )
Value:
do{                                                     \
                      if ((__STATE__) == RCC_HSE_ON)                        \
                      {                                                     \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
                      }                                                     \
                      else if ((__STATE__) == RCC_HSE_OFF)                  \
                      {                                                     \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
                      }                                                     \
                      else if ((__STATE__) == RCC_HSE_BYPASS)               \
                      {                                                     \
                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);                    \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
                      }                                                     \
                      else                                                  \
                      {                                                     \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
                      }                                                     \
                    }while(0U)

Macro to configure the External High Speed oscillator (HSE).

Note:
Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. User should request a transition to HSE Off first and then HSE On or HSE Bypass.
After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.
HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).
The HSE is stopped by hardware when entering STOP and STANDBY modes.
This function reset the CSSON bit, so if the clock security system(CSS) was previously enabled you have to enable it again after calling this function.
Parameters:
__STATE__ specifies the new state of the HSE. This parameter can be one of the following values:
  • RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
  • RCC_HSE_ON turn ON the HSE oscillator
  • RCC_HSE_BYPASS HSE oscillator bypassed with external clock

Definition at line 1147 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LSE Configuration

Defines
LSE Configuration
RCC Exported Macros

Defines

#define __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).

Define Documentation

#define __HAL_RCC_LSE_CONFIG ( __STATE__ )
Value:
do{                                                     \
                      if ((__STATE__) == RCC_LSE_ON)                        \
                      {                                                     \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
                      }                                                     \
                      else if ((__STATE__) == RCC_LSE_OFF)                  \
                      {                                                     \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
                      }                                                     \
                      else if ((__STATE__) == RCC_LSE_BYPASS)               \
                      {                                                     \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                  \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
                      }                                                     \
                      else                                                  \
                      {                                                     \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
                      }                                                     \
                    }while(0U)

Macro to configure the External Low Speed oscillator (LSE).

Note:
Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
Parameters:
__STATE__ specifies the new state of the LSE. This parameter can be one of the following values:
  • RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
  • RCC_LSE_ON turn ON the LSE oscillator.
  • RCC_LSE_BYPASS LSE oscillator bypassed with external clock.

Definition at line 1195 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC USARTx Clock Config

Defines
RCC USARTx Clock Config
RCC Exported Macros

Defines

#define | __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__))
Macro to configure the USART1 clock (USART1CLK).
#define | __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
Macro to get the USART1 clock source.
#define | __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__))
Macro to configure the USART2 clock (USART2CLK).
#define | __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
Macro to get the USART2 clock source.
#define | __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__))
Macro to configure the USART3 clock (USART3CLK).
#define | __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
Macro to get the USART3 clock source.

Define Documentation

#define __HAL_RCC_GET_USART1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))

Macro to get the USART1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock

Definition at line 1326 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USART2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))

Macro to get the USART2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock

Definition at line 1347 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USART3_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))

Macro to get the USART3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock

Definition at line 1369 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_USART1_CONFIG ( __USART1CLKSOURCE__ ) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__))

Macro to configure the USART1 clock (USART1CLK).

Parameters:
__USART1CLKSOURCE__ specifies the USART1 clock source. This parameter can be one of the following values:
  • RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock

Definition at line 1275 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART2_CONFIG ( __USART2CLKSOURCE__ ) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__))

Macro to configure the USART2 clock (USART2CLK).

Parameters:
__USART2CLKSOURCE__ specifies the USART2 clock source. This parameter can be one of the following values:
  • RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock

Definition at line 1337 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART3_CONFIG ( __USART3CLKSOURCE__ ) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__))

Macro to configure the USART3 clock (USART3CLK).

Parameters:
__USART3CLKSOURCE__ specifies the USART3 clock source. This parameter can be one of the following values:
  • RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock

Definition at line 1359 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC I2Cx Clock Config

Defines
RCC I2Cx Clock Config
RCC Exported Macros

Defines

#define | __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__))
Macro to configure the I2C1 clock (I2C1CLK).
#define | __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
Macro to get the I2C1 clock source.

Define Documentation

#define __HAL_RCC_GET_I2C1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))

Macro to get the I2C1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock

Definition at line 1393 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_I2C1_CONFIG ( __I2C1CLKSOURCE__ ) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__))

Macro to configure the I2C1 clock (I2C1CLK).

Parameters:
__I2C1CLKSOURCE__ specifies the I2C1 clock source. This parameter can be one of the following values:
  • RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock

Definition at line 1385 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PLL Configuration

Defines
PLL Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
Macro to enable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
Macro to disable the main PLL.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
Get oscillator clock selected as PLL input clock.

Define Documentation

#define __HAL_RCC_GET_PLL_OSCSOURCE ( ) ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))

Get oscillator clock selected as PLL input clock.

Return values:
The clock source used for PLL entry. The returned value can be one of the following:
  • RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
  • RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock

Definition at line 1422 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_DISABLE ( ) (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)

Macro to disable the main PLL.

Note:
The main PLL can not be disabled if it is used as system clock source

Definition at line 1413 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_ENABLE ( ) (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)

Macro to enable the main PLL.

Note:
After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
The main PLL is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 1408 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Get Clock source

Defines
Get Clock source
RCC Exported Macros

Defines

#define | __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
Macro to get the clock source used as system clock.

Define Documentation

#define __HAL_RCC_GET_SYSCLK_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))

Macro to get the clock source used as system clock.

Return values:
The clock source used as system clock. The returned value can be one of the following:
  • RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
  • RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock

Definition at line 1450 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define __HAL_RCC_SYSCLK_CONFIG ( __SYSCLKSOURCE__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))

Macro to configure the system clock source.

Parameters:
__SYSCLKSOURCE__ specifies the system clock source. This parameter can be one of the following values:
  • RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.

Definition at line 1440 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Extended MCOx Clock Config

Defines
RCC Extended MCOx Clock Config
RCC Exported Macros

Defines

#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
Macro to configure the MCO clock.

Define Documentation

#define __HAL_RCC_MCO1_CONFIG | ( | __MCOCLKSOURCE__,
 |  | __MCODIV__
 | ) | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))

Macro to configure the MCO clock.

Parameters:
__MCOCLKSOURCE__ specifies the MCO clock source. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
  • RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
  • RCC_MCO1SOURCE_HSI HSI selected as MCO clock
  • RCC_MCO1SOURCE_HSE HSE selected as MCO clock
  • RCC_MCO1SOURCE_LSI LSI selected as MCO clock
  • RCC_MCO1SOURCE_LSE LSE selected as MCO clock
  • RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
__MCODIV__ specifies the MCO clock prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1 No division applied on MCO clock source

Definition at line 1503 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC RTC Clock Configuration

Defines
RCC RTC Clock Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Macro to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
Macro to get the RTC clock source.
#define | __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
Macro to enable the the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
Macro to disable the the RTC clock.
#define | __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
Macro to force the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
Macros to release the Backup domain reset.

Define Documentation

#define __HAL_RCC_BACKUPRESET_FORCE ( ) (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)

Macro to force the Backup domain reset.

Note:
This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_BDCR register.

Definition at line 1563 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_BACKUPRESET_RELEASE ( ) (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)

Macros to release the Backup domain reset.

Definition at line 1567 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_RTC_SOURCE ( ) (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))

Macro to get the RTC clock source.

Return values:
The clock source can be one of the following values:
  • RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
  • RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
  • RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
  • RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32

Definition at line 1547 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_RTC_CONFIG ( __RTC_CLKSOURCE__ ) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))

Macro to configure the RTC clock (RTCCLK).

Note:
As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using the Power Backup Access macro before to configure the RTC clock source (to be done once after reset).
Once the RTC clock is configured it cannot be changed unless the Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by a Power On Reset (POR).
Parameters:
__RTC_CLKSOURCE__ specifies the RTC clock source. This parameter can be one of the following values:
  • RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
  • RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
  • RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
  • RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
Note:
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
The system must always be configured so as to get a PCLK frequency greater than or equal to the RTCCLK frequency for a proper operation of the RTC.

Definition at line 1538 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RTC_DISABLE ( ) (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)

Macro to disable the the RTC clock.

Note:
These macros must be used only after the RTC clock source was selected.

Definition at line 1557 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_RTC_ENABLE ( ) (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)

Macro to enable the the RTC clock.

Note:
These macros must be used only after the RTC clock source was selected.

Definition at line 1552 of file stm32f3xx_hal_rcc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Flags Interrupts Management

Defines
Flags Interrupts Management
RCC Exported Macros

macros to manage the specified RCC Flags and interrupts. More...

Defines

#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
Enable RCC interrupt.
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
Disable RCC interrupt.
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Clear the RCC's interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Check the RCC's interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
Set RMVF bit to clear the reset flags.
#define | __HAL_RCC_GET_FLAG(__FLAG__)
Check RCC flag is set or not.

Detailed Description

macros to manage the specified RCC Flags and interrupts.

Define Documentation

#define __HAL_RCC_CLEAR_IT ( __INTERRUPT__ ) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))

Clear the RCC's interrupt pending bits.

Parameters:
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt.
  • RCC_IT_LSERDY LSE ready interrupt.
  • RCC_IT_HSIRDY HSI ready interrupt.
  • RCC_IT_HSERDY HSE ready interrupt.
  • RCC_IT_PLLRDY Main PLL ready interrupt.
  • RCC_IT_CSS Clock Security System interrupt

Definition at line 1610 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define __HAL_RCC_CLEAR_RESET_FLAGS ( ) (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)

Set RMVF bit to clear the reset flags.

The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST

Definition at line 1629 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_DISABLE_IT ( __INTERRUPT__ ) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))

Disable RCC interrupt.

Parameters:
__INTERRUPT__ specifies the RCC interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt
  • RCC_IT_LSERDY LSE ready interrupt
  • RCC_IT_HSIRDY HSI ready interrupt
  • RCC_IT_HSERDY HSE ready interrupt
  • RCC_IT_PLLRDY main PLL ready interrupt

Definition at line 1598 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_ENABLE_IT ( __INTERRUPT__ ) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))

Enable RCC interrupt.

Parameters:
__INTERRUPT__ specifies the RCC interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt
  • RCC_IT_LSERDY LSE ready interrupt
  • RCC_IT_HSIRDY HSI ready interrupt
  • RCC_IT_HSERDY HSE ready interrupt
  • RCC_IT_PLLRDY main PLL ready interrupt

Definition at line 1587 of file stm32f3xx_hal_rcc.h.

#define __HAL_RCC_GET_FLAG ( __FLAG__ )
Value:
(((((__FLAG__) >> 5U) == CR_REG_INDEX)  ? RCC->CR   : \
                                       (((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
                                       (((__FLAG__) >> 5U) == CFGR_REG_INDEX)? RCC->CFGR : \
                                                                              RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))

Check RCC flag is set or not.

Parameters:
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • RCC_FLAG_HSIRDY HSI oscillator clock ready.
  • RCC_FLAG_HSERDY HSE oscillator clock ready.
  • RCC_FLAG_PLLRDY Main PLL clock ready.
  • RCC_FLAG_LSERDY LSE oscillator clock ready.
  • RCC_FLAG_LSIRDY LSI oscillator clock ready.
  • RCC_FLAG_OBLRST Option Byte Load reset
  • RCC_FLAG_PINRST Pin reset.
  • RCC_FLAG_PORRST POR/PDR reset.
  • RCC_FLAG_SFTRST Software reset.
  • RCC_FLAG_IWDGRST Independent Watchdog reset.
  • RCC_FLAG_WWDGRST Window Watchdog reset.
  • RCC_FLAG_LPWRRST Low Power reset.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1680 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_IT ( __INTERRUPT__ ) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))

Check the RCC's interrupt has occurred or not.

Parameters:
__INTERRUPT__ specifies the RCC interrupt source to check. This parameter can be one of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt.
  • RCC_IT_LSERDY LSE ready interrupt.
  • RCC_IT_HSIRDY HSI ready interrupt.
  • RCC_IT_HSERDY HSE ready interrupt.
  • RCC_IT_PLLRDY Main PLL ready interrupt.
  • RCC_IT_CSS Clock Security System interrupt
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 1623 of file stm32f3xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCCEx Private Macros

Defines
RCCEx Private Macros
RCCEx

Defines

#define | IS_RCC_MCO1SOURCE(SOURCE)
#define | IS_RCC_PERIPHCLOCK(SELECTION)
#define | IS_RCC_USART1CLKSOURCE(SOURCE)
#define | IS_RCC_I2C2CLKSOURCE(SOURCE)
#define | IS_RCC_ADC1PCLK2_DIV(ADCCLK)
#define | IS_RCC_CECCLKSOURCE(SOURCE)
#define | IS_RCC_SDADCSYSCLK_DIV(DIV)
#define | IS_RCC_USBCLKSOURCE(SOURCE)
#define | IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
#define | IS_RCC_LSE_DRIVE(__DRIVE__)

Define Documentation

#define IS_RCC_ADC1PCLK2_DIV ( ADCCLK )
Value:
(((ADCCLK) == RCC_ADC1PCLK2_DIV2) || ((ADCCLK) == RCC_ADC1PCLK2_DIV4) || \
                                      ((ADCCLK) == RCC_ADC1PCLK2_DIV6) || ((ADCCLK) == RCC_ADC1PCLK2_DIV8))

Definition at line 320 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_CECCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
                                      ((SOURCE) == RCC_CECCLKSOURCE_LSE))

Definition at line 322 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C2CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
                                       ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))

Definition at line 318 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LSE_DRIVE ( __DRIVE__ )
Value:
(((__DRIVE__) == RCC_LSEDRIVE_LOW)        || \
                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW)  || \
                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
                                     ((__DRIVE__) == RCC_LSEDRIVE_HIGH))

Definition at line 353 of file stm32f3xx_hal_rcc_ex.h.

#define IS_RCC_MCO1SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_MCO1SOURCE_NOCLOCK)    || \
                                   ((SOURCE) == RCC_MCO1SOURCE_LSI)     || \
                                   ((SOURCE) == RCC_MCO1SOURCE_LSE)     || \
                                   ((SOURCE) == RCC_MCO1SOURCE_SYSCLK)  || \
                                   ((SOURCE) == RCC_MCO1SOURCE_HSI)     || \
                                   ((SOURCE) == RCC_MCO1SOURCE_HSE)     || \
                                   ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2))

Definition at line 69 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCODIV ( DIV ) (((DIV) == RCC_MCODIV_1))

Definition at line 350 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_PERIPHCLOCK ( SELECTION )
Value:
((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
                                                     RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | \
                                                     RCC_PERIPHCLK_ADC1   | RCC_PERIPHCLK_SDADC  | \
                                                     RCC_PERIPHCLK_CEC    | RCC_PERIPHCLK_RTC    | \
                                                     RCC_PERIPHCLK_USB))

Definition at line 172 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SDADCSYSCLK_DIV ( DIV )
Value:
(((DIV) == RCC_SDADCSYSCLK_DIV1)  || ((DIV) == RCC_SDADCSYSCLK_DIV2)   || \
                                     ((DIV) == RCC_SDADCSYSCLK_DIV4)  || ((DIV) == RCC_SDADCSYSCLK_DIV6)   || \
                                     ((DIV) == RCC_SDADCSYSCLK_DIV8)  || ((DIV) == RCC_SDADCSYSCLK_DIV10)  || \
                                     ((DIV) == RCC_SDADCSYSCLK_DIV12) || ((DIV) == RCC_SDADCSYSCLK_DIV14)  || \
                                     ((DIV) == RCC_SDADCSYSCLK_DIV16) || ((DIV) == RCC_SDADCSYSCLK_DIV20)  || \
                                     ((DIV) == RCC_SDADCSYSCLK_DIV24) || ((DIV) == RCC_SDADCSYSCLK_DIV28)  || \
                                     ((DIV) == RCC_SDADCSYSCLK_DIV32) || ((DIV) == RCC_SDADCSYSCLK_DIV36)  || \
                                     ((DIV) == RCC_SDADCSYSCLK_DIV40) || ((DIV) == RCC_SDADCSYSCLK_DIV44)  || \
                                     ((DIV) == RCC_SDADCSYSCLK_DIV48))

Definition at line 324 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USART1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USART1CLKSOURCE_PCLK2)  || \
                                         ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
                                         ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
                                         ((SOURCE) == RCC_USART1CLKSOURCE_HSI))

Definition at line 314 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USBCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USBCLKSOURCE_PLL) || \
                                      ((SOURCE) == RCC_USBCLKSOURCE_PLL_DIV1_5))

Definition at line 338 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCCEx Private Functions

Functions
RCCEx Private Functions
RCCEx

Functions

static uint32_t RCC_GetPLLCLKFreq (void)

Function Documentation

static uint32_t RCC_GetPLLCLKFreq ( void ) [static]

Definition at line 1545 of file stm32f3xx_hal_rcc_ex.c.

References HSE_VALUE, HSI_VALUE, and RCC_PLLSOURCE_HSI.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
RCCEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Returns the peripheral clock frequency.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                ##### Extended Peripheral Control functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.
    [..]
    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
        select the RTC clock source; in this case the Backup domain will be reset in
        order to modify the RTC Clock source, as consequence RTC registers (including
        the backup registers) are set to their reset values.

Function Documentation

void HAL_RCCEx_GetPeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Get the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that returns the configuration information for the Extended Peripherals clocks (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB clocks).
Return values:
None

Definition at line 587 of file stm32f3xx_hal_rcc_ex.c.

References __HAL_RCC_GET_ADC1_SOURCE, __HAL_RCC_GET_CEC_SOURCE, __HAL_RCC_GET_I2C1_SOURCE, __HAL_RCC_GET_I2C2_SOURCE, __HAL_RCC_GET_RTC_SOURCE, __HAL_RCC_GET_SDADC_SOURCE, __HAL_RCC_GET_USART1_SOURCE, __HAL_RCC_GET_USART2_SOURCE, __HAL_RCC_GET_USART3_SOURCE, __HAL_RCC_GET_USB_SOURCE, RCC_PeriphCLKInitTypeDef::Adc1ClockSelection, RCC_PeriphCLKInitTypeDef::CecClockSelection, RCC_PeriphCLKInitTypeDef::I2c1ClockSelection, RCC_PeriphCLKInitTypeDef::I2c2ClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_PERIPHCLK_ADC1, RCC_PERIPHCLK_CEC, RCC_PERIPHCLK_I2C2, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_SDADC, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_USART3, RCC_PERIPHCLK_USB, RCC_PeriphCLKInitTypeDef::RTCClockSelection, RCC_PeriphCLKInitTypeDef::SdadcClockSelection, RCC_PeriphCLKInitTypeDef::Usart1ClockSelection, RCC_PeriphCLKInitTypeDef::Usart2ClockSelection, RCC_PeriphCLKInitTypeDef::Usart3ClockSelection, and RCC_PeriphCLKInitTypeDef::USBClockSelection.

uint32_t HAL_RCCEx_GetPeriphCLKFreq ( uint32_t PeriphClk )

Returns the peripheral clock frequency.

Note:
Returns 0 if peripheral clock is unknown or 0xDEADDEAD if not applicable.
Parameters:
PeriphClk Peripheral clock identifier This parameter can be one of the following values:
  • RCC_PERIPHCLK_RTC RTC peripheral clock
  • RCC_PERIPHCLK_USART1 USART1 peripheral clock
  • RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
  • RCC_PERIPHCLK_USART2 USART2 peripheral clock
  • RCC_PERIPHCLK_USART3 USART3 peripheral clock
  • RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
  • RCC_PERIPHCLK_USB USB peripheral clock
  • RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
  • RCC_PERIPHCLK_SDADC SDADC peripheral clock
  • RCC_PERIPHCLK_CEC CEC peripheral clock
Return values:
Frequency in Hz (0: means that no available frequency for the peripheral)

Definition at line 958 of file stm32f3xx_hal_rcc_ex.c.

References __HAL_RCC_GET_ADC1_SOURCE, __HAL_RCC_GET_CEC_SOURCE, __HAL_RCC_GET_I2C1_SOURCE, __HAL_RCC_GET_I2C2_SOURCE, __HAL_RCC_GET_RTC_SOURCE, __HAL_RCC_GET_SDADC_SOURCE, __HAL_RCC_GET_USART1_SOURCE, __HAL_RCC_GET_USART2_SOURCE, __HAL_RCC_GET_USART3_SOURCE, __HAL_RCC_GET_USB_SOURCE, assert_param, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSE_VALUE, HSI_VALUE, IS_RCC_PERIPHCLOCK, LSE_VALUE, LSI_VALUE, RCC_CECCLKSOURCE_HSI, RCC_CECCLKSOURCE_LSE, RCC_GetPLLCLKFreq(), RCC_I2C1CLKSOURCE_HSI, RCC_I2C1CLKSOURCE_SYSCLK, RCC_I2C2CLKSOURCE_HSI, RCC_I2C2CLKSOURCE_SYSCLK, RCC_PERIPHCLK_ADC1, RCC_PERIPHCLK_CEC, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_I2C2, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_SDADC, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_USART3, RCC_PERIPHCLK_USB, RCC_RTCCLKSOURCE_HSE_DIV32, RCC_RTCCLKSOURCE_LSE, RCC_RTCCLKSOURCE_LSI, RCC_USART1CLKSOURCE_HSI, RCC_USART1CLKSOURCE_LSE, RCC_USART1CLKSOURCE_PCLK2, RCC_USART1CLKSOURCE_SYSCLK, RCC_USART2CLKSOURCE_HSI, RCC_USART2CLKSOURCE_LSE, RCC_USART2CLKSOURCE_PCLK1, RCC_USART2CLKSOURCE_SYSCLK, RCC_USART3CLKSOURCE_HSI, RCC_USART3CLKSOURCE_LSE, RCC_USART3CLKSOURCE_PCLK1, RCC_USART3CLKSOURCE_SYSCLK, and RCC_USBCLKSOURCE_PLL.

HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.

Parameters:
PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that contains the configuration information for the Extended Peripherals clocks (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB).
Note:
Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source; in this case the Backup domain will be reset in order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) and RCC_BDCR register are set to their reset values.
Return values:
HAL status

Definition at line 119 of file stm32f3xx_hal_rcc_ex.c.

References __HAL_RCC_ADC1_CONFIG, __HAL_RCC_BACKUPRESET_FORCE, __HAL_RCC_BACKUPRESET_RELEASE, __HAL_RCC_CEC_CONFIG, __HAL_RCC_GET_FLAG, __HAL_RCC_I2C1_CONFIG, __HAL_RCC_I2C2_CONFIG, __HAL_RCC_PWR_CLK_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_PWR_IS_CLK_DISABLED, __HAL_RCC_RTC_CONFIG, __HAL_RCC_SDADC_CONFIG, __HAL_RCC_USART1_CONFIG, __HAL_RCC_USART2_CONFIG, __HAL_RCC_USART3_CONFIG, __HAL_RCC_USB_CONFIG, RCC_PeriphCLKInitTypeDef::Adc1ClockSelection, assert_param, RCC_PeriphCLKInitTypeDef::CecClockSelection, HAL_GetTick(), RCC_PeriphCLKInitTypeDef::I2c1ClockSelection, RCC_PeriphCLKInitTypeDef::I2c2ClockSelection, IS_RCC_ADC1PCLK2_DIV, IS_RCC_CECCLKSOURCE, IS_RCC_I2C1CLKSOURCE, IS_RCC_I2C2CLKSOURCE, IS_RCC_PERIPHCLOCK, IS_RCC_RTCCLKSOURCE, IS_RCC_SDADCSYSCLK_DIV, IS_RCC_USART1CLKSOURCE, IS_RCC_USART2CLKSOURCE, IS_RCC_USART3CLKSOURCE, IS_RCC_USBCLKSOURCE, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_DBP_TIMEOUT_VALUE, RCC_FLAG_LSERDY, RCC_LSE_TIMEOUT_VALUE, RCC_PERIPHCLK_ADC1, RCC_PERIPHCLK_CEC, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_I2C2, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_SDADC, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_USART3, RCC_PERIPHCLK_USB, RCC_PeriphCLKInitTypeDef::RTCClockSelection, RCC_PeriphCLKInitTypeDef::SdadcClockSelection, RCC_PeriphCLKInitTypeDef::Usart1ClockSelection, RCC_PeriphCLKInitTypeDef::Usart2ClockSelection, RCC_PeriphCLKInitTypeDef::Usart3ClockSelection, and RCC_PeriphCLKInitTypeDef::USBClockSelection.

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STM32F373xC HAL User Manual: RCC_PeriphCLKInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PeriphCLKInitTypeDef Struct Reference
RCCEx Exported Types

RCC extended clocks structure definition. More...

#include <stm32f3xx_hal_rcc_ex.h>

Data Fields

uint32_t | PeriphClockSelection
uint32_t | RTCClockSelection
uint32_t | Usart1ClockSelection
uint32_t | Usart2ClockSelection
uint32_t | Usart3ClockSelection
uint32_t | I2c1ClockSelection
uint32_t | I2c2ClockSelection
uint32_t | Adc1ClockSelection
uint32_t | SdadcClockSelection
uint32_t | CecClockSelection
uint32_t | USBClockSelection

Detailed Description

RCC extended clocks structure definition.

Definition at line 880 of file stm32f3xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PeriphCLKInitTypeDef::Adc1ClockSelection

ADC1 clock source This parameter can be a value of RCC Extended ADC1 Clock Source

Definition at line 903 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::CecClockSelection

HDMI CEC clock source This parameter can be a value of RCC Extended CEC Clock Source

Definition at line 909 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c1ClockSelection

I2C1 clock source This parameter can be a value of RCC I2C1 Clock Source

Definition at line 897 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c2ClockSelection

I2C2 clock source This parameter can be a value of RCC Extended I2C2 Clock Source

Definition at line 900 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::PeriphClockSelection

The Extended Clock to be configured. This parameter can be a value of RCC Extended Periph Clock Selection

Definition at line 882 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::RTCClockSelection

Specifies RTC Clock Prescalers Selection This parameter can be a value of RTC Clock Source

Definition at line 885 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::SdadcClockSelection

SDADC clock prescaler This parameter can be a value of RCC Extended SDADC Clock Prescaler

Definition at line 906 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart1ClockSelection

USART1 clock source This parameter can be a value of RCC Extended USART1 Clock Source

Definition at line 888 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart2ClockSelection

USART2 clock source This parameter can be a value of RCC USART2 Clock Source

Definition at line 891 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart3ClockSelection

USART3 clock source This parameter can be a value of RCC USART3 Clock Source

Definition at line 894 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::USBClockSelection

USB clock source This parameter can be a value of RCC Extended USB Clock Source

Definition at line 912 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_rcc_ex.h
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STM32F373xC HAL User Manual: RCC Extended MCO Clock Source

Defines
RCC Extended MCO Clock Source
RCC Extended Exported Constants

Defines

#define | RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
#define | RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
#define | RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
#define | RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
#define | RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
#define | RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
#define | RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL

Define Documentation

#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE

Definition at line 970 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI

Definition at line 969 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE

Definition at line 967 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI

Definition at line 966 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK

Definition at line 965 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL

Definition at line 974 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK

Definition at line 968 of file stm32f3xx_hal_rcc_ex.h.

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STM32F373xC HAL User Manual: RCC Extended Periph Clock Selection

Defines
RCC Extended Periph Clock Selection
RCC Extended Exported Constants

Defines

#define | RCC_PERIPHCLK_USART1 (0x00000001U)
#define | RCC_PERIPHCLK_USART2 (0x00000002U)
#define | RCC_PERIPHCLK_USART3 (0x00000004U)
#define | RCC_PERIPHCLK_I2C1 (0x00000020U)
#define | RCC_PERIPHCLK_I2C2 (0x00000040U)
#define | RCC_PERIPHCLK_ADC1 (0x00000080U)
#define | RCC_PERIPHCLK_CEC (0x00000400U)
#define | RCC_PERIPHCLK_SDADC (0x00000800U)
#define | RCC_PERIPHCLK_RTC (0x00010000U)
#define | RCC_PERIPHCLK_USB (0x00020000U)

Define Documentation

#define RCC_PERIPHCLK_ADC1 (0x00000080U)

Definition at line 1173 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_CEC (0x00000400U)

Definition at line 1174 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C1 (0x00000020U)

Definition at line 1171 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C2 (0x00000040U)

Definition at line 1172 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_RTC (0x00010000U)

Definition at line 1176 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SDADC (0x00000800U)

Definition at line 1175 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART1 (0x00000001U)

Definition at line 1168 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART2 (0x00000002U)

Definition at line 1169 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART3 (0x00000004U)

Definition at line 1170 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USB (0x00020000U)

Definition at line 1177 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

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STM32F373xC HAL User Manual: RCC Extended USART1 Clock Source

Defines
RCC Extended USART1 Clock Source
RCC Extended Exported Constants

Defines

#define | RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
#define | RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
#define | RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
#define | RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI

Define Documentation

#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI

Definition at line 1669 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE

Definition at line 1668 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2

Definition at line 1666 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK

Definition at line 1667 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32F373xC HAL User Manual: RCC Extended I2C2 Clock Source

Defines
RCC Extended I2C2 Clock Source
RCC Extended Exported Constants

Defines

#define | RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
#define | RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK

Define Documentation

#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI

Definition at line 1678 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK

Definition at line 1679 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32F373xC HAL User Manual: RCC Extended ADC1 Clock Source

Defines
RCC Extended ADC1 Clock Source
RCC Extended Exported Constants

Defines

#define | RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
#define | RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
#define | RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
#define | RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8

Define Documentation

#define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2

Definition at line 1690 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4

Definition at line 1691 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6

Definition at line 1692 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8

Definition at line 1693 of file stm32f3xx_hal_rcc_ex.h.

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STM32F373xC HAL User Manual: RCC Extended CEC Clock Source

Defines
RCC Extended CEC Clock Source
RCC Extended Exported Constants

Defines

#define | RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
#define | RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE

Define Documentation

#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244

Definition at line 1702 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE

Definition at line 1703 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32F373xC HAL User Manual: RCC Extended SDADC Clock Prescaler

Defines
RCC Extended SDADC Clock Prescaler
RCC Extended Exported Constants

Defines

#define | RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDPRE_DIV1
#define | RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDPRE_DIV2
#define | RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDPRE_DIV4
#define | RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDPRE_DIV6
#define | RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDPRE_DIV8
#define | RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDPRE_DIV10
#define | RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDPRE_DIV12
#define | RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDPRE_DIV14
#define | RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDPRE_DIV16
#define | RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDPRE_DIV20
#define | RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDPRE_DIV24
#define | RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDPRE_DIV28
#define | RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDPRE_DIV32
#define | RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDPRE_DIV36
#define | RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDPRE_DIV40
#define | RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDPRE_DIV44
#define | RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDPRE_DIV48

Define Documentation

#define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDPRE_DIV1

Definition at line 1712 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDPRE_DIV10

Definition at line 1717 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDPRE_DIV12

Definition at line 1718 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDPRE_DIV14

Definition at line 1719 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDPRE_DIV16

Definition at line 1720 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDPRE_DIV2

Definition at line 1713 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDPRE_DIV20

Definition at line 1721 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDPRE_DIV24

Definition at line 1722 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDPRE_DIV28

Definition at line 1723 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDPRE_DIV32

Definition at line 1724 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDPRE_DIV36

Definition at line 1725 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDPRE_DIV4

Definition at line 1714 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDPRE_DIV40

Definition at line 1726 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDPRE_DIV44

Definition at line 1727 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDPRE_DIV48

Definition at line 1728 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDPRE_DIV6

Definition at line 1715 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDPRE_DIV8

Definition at line 1716 of file stm32f3xx_hal_rcc_ex.h.

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STM32F373xC HAL User Manual: RCC Extended USB Clock Source

Defines
RCC Extended USB Clock Source
RCC Extended Exported Constants

Defines

#define | RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1
#define | RCC_USBCLKSOURCE_PLL_DIV1_5 RCC_CFGR_USBPRE_DIV1_5

Define Documentation

#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1

Definition at line 1744 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USBCLKSOURCE_PLL_DIV1_5 RCC_CFGR_USBPRE_DIV1_5

Definition at line 1745 of file stm32f3xx_hal_rcc_ex.h.

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STM32F373xC HAL User Manual: RCC Extended MCOx Clock Prescaler

Defines
RCC Extended MCOx Clock Prescaler
RCC Extended Exported Constants

Defines

#define RCC_MCODIV_1 (0x00000000U)

Define Documentation

#define RCC_MCODIV_1 (0x00000000U)

Definition at line 1773 of file stm32f3xx_hal_rcc_ex.h.

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STM32F373xC HAL User Manual: RCC LSE Drive Configuration

Defines
RCC LSE Drive Configuration
RCC Extended Exported Constants

Defines

#define | RCC_LSEDRIVE_LOW (0x00000000U)
#define | RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
#define | RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
#define | RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Define Documentation

#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Xtal mode higher driving capability

Definition at line 1788 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_LSEDRIVE_LOW (0x00000000U)

Xtal mode lower driving capability

Definition at line 1785 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0

Xtal mode medium high driving capability

Definition at line 1787 of file stm32f3xx_hal_rcc_ex.h.

#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1

Xtal mode medium low driving capability

Definition at line 1786 of file stm32f3xx_hal_rcc_ex.h.

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STM32F373xC HAL User Manual: RCC Extended PLL Configuration

Defines
RCC Extended PLL Configuration
RCC Extended Exported Macros

Defines

#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLMUL__) MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__)))
Macro to configure the PLL clock source and multiplication factor.

Define Documentation

#define __HAL_RCC_PLL_CONFIG | ( | __RCC_PLLSource__,
 |  | __PLLMUL__
 | ) | MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__)))

Macro to configure the PLL clock source and multiplication factor.

Note:
This macro must be used only when the PLL is disabled.
Parameters:
__RCC_PLLSource__ specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
__PLLMUL__ specifies the multiplication factor for PLL VCO input clock This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.

Definition at line 1842 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCC_OscConfig().

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STM32F373xC HAL User Manual: RCC Extended HSE Configuration

Defines
RCC Extended HSE Configuration
RCC Extended Exported Macros

Defines

#define | __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
#define | __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)
Macro to get prediv1 factor for PLL.

Define Documentation

#define __HAL_RCC_HSE_GET_PREDIV ( ) READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)

Macro to get prediv1 factor for PLL.

Definition at line 1874 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCC_GetOscConfig().

#define __HAL_RCC_HSE_PREDIV_CONFIG ( __HSE_PREDIV_VALUE__ ) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))

Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.

Note:
Predivision factor can not be changed if PLL is used as system clock In this case, you have to select another source of the system clock, disable the PLL and then change the HSE predivision factor.
Parameters:
__HSE_PREDIV_VALUE__ specifies the division value applied to HSE. This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.

Definition at line 1868 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCC_OscConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Extended AHB Clock Enable Disable

Defines
RCC Extended AHB Clock Enable Disable
RCC Extended Exported Macros

Enable or disable the AHB peripheral clock. More...

Defines

#define | __HAL_RCC_DMA2_CLK_ENABLE()
#define | __HAL_RCC_GPIOE_CLK_ENABLE()
#define | __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
#define | __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))

Detailed Description

Enable or disable the AHB peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_DMA2_CLK_DISABLE ( ) (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))

Definition at line 1986 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 1971 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_CLK_DISABLE ( ) (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))

Definition at line 1987 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 1978 of file stm32f3xx_hal_rcc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Extended APB1 Clock Enable Disable

Defines
RCC Extended APB1 Clock Enable Disable
RCC Extended Exported Macros

Enable or disable the Low Speed APB (APB1) peripheral clock. More...

Defines

#define | __HAL_RCC_TIM3_CLK_ENABLE()
#define | __HAL_RCC_TIM4_CLK_ENABLE()
#define | __HAL_RCC_TIM5_CLK_ENABLE()
#define | __HAL_RCC_TIM12_CLK_ENABLE()
#define | __HAL_RCC_TIM13_CLK_ENABLE()
#define | __HAL_RCC_TIM14_CLK_ENABLE()
#define | __HAL_RCC_TIM18_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_SPI3_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_DAC2_CLK_ENABLE()
#define | __HAL_RCC_CEC_CLK_ENABLE()
#define | __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
#define | __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
#define | __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
#define | __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
#define | __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
#define | __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
#define | __HAL_RCC_TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
#define | __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
#define | __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
#define | __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
#define | __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
#define | __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
#define | __HAL_RCC_TIM7_CLK_ENABLE()
#define | __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
#define | __HAL_RCC_USB_CLK_ENABLE()
#define | __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
#define | __HAL_RCC_CAN1_CLK_ENABLE()
#define | __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))

Detailed Description

Enable or disable the Low Speed APB (APB1) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CAN1_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))

Definition at line 2291 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2283 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))

Definition at line 2243 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2224 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))

Definition at line 2242 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2217 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))

Definition at line 2241 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2210 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))

Definition at line 2239 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2196 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))

Definition at line 2240 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2203 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))

Definition at line 2235 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2168 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))

Definition at line 2236 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2175 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))

Definition at line 2237 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2182 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM18_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))

Definition at line 2238 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM18_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2189 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))

Definition at line 2232 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2147 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))

Definition at line 2233 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2154 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))

Definition at line 2234 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2161 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))

Definition at line 2258 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2250 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))

Definition at line 2276 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2268 of file stm32f3xx_hal_rcc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Extended APB2 Clock Enable Disable

Defines
RCC Extended APB2 Clock Enable Disable
RCC Extended Exported Macros

Enable or disable the High Speed APB (APB2) peripheral clock. More...

Defines

#define | __HAL_RCC_ADC1_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_TIM19_CLK_ENABLE()
#define | __HAL_RCC_SDADC1_CLK_ENABLE()
#define | __HAL_RCC_SDADC2_CLK_ENABLE()
#define | __HAL_RCC_SDADC3_CLK_ENABLE()
#define | __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
#define | __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
#define | __HAL_RCC_TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
#define | __HAL_RCC_SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
#define | __HAL_RCC_SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
#define | __HAL_RCC_SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))

Detailed Description

Enable or disable the High Speed APB (APB2) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))

Definition at line 2412 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2369 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))

Definition at line 2415 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2390 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC2_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))

Definition at line 2416 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2397 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC3_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))

Definition at line 2417 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2404 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))

Definition at line 2413 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2376 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM19_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))

Definition at line 2414 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM19_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 2383 of file stm32f3xx_hal_rcc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Extended AHB Peripheral Clock Enable Disable Status

Defines
RCC Extended AHB Peripheral Clock Enable Disable Status
RCC Extended Exported Macros

Get the enable or disable status of the AHB peripheral clock. More...

Defines

#define | __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)

Detailed Description

Get the enable or disable status of the AHB peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_DMA2_IS_CLK_DISABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)

Definition at line 2508 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_IS_CLK_ENABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)

Definition at line 2505 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_IS_CLK_DISABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)

Definition at line 2509 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_IS_CLK_ENABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)

Definition at line 2506 of file stm32f3xx_hal_rcc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Extended APB1 Peripheral Clock Enable Disable Status

Defines
RCC Extended APB1 Peripheral Clock Enable Disable Status
RCC Extended Exported Macros

Get the enable or disable status of the APB1 peripheral clock. More...

Defines

#define | __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
#define | __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
#define | __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
#define | __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
#define | __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
#define | __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
#define | __HAL_RCC_TIM18_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
#define | __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
#define | __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
#define | __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)
#define | __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
#define | __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
#define | __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
#define | __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
#define | __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
#define | __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
#define | __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
#define | __HAL_RCC_TIM18_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
#define | __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
#define | __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
#define | __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)
#define | __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
#define | __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
#define | __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
#define | __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
#define | __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
#define | __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) != RESET)
#define | __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) == RESET)

Detailed Description

Get the enable or disable status of the APB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CAN1_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) == RESET)

Definition at line 2627 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) != RESET)

Definition at line 2625 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)

Definition at line 2597 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)

Definition at line 2584 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC2_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)

Definition at line 2596 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC2_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)

Definition at line 2583 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)

Definition at line 2595 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)

Definition at line 2582 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)

Definition at line 2593 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)

Definition at line 2580 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)

Definition at line 2594 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)

Definition at line 2581 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)

Definition at line 2589 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)

Definition at line 2576 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)

Definition at line 2590 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)

Definition at line 2577 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)

Definition at line 2591 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)

Definition at line 2578 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM18_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) == RESET)

Definition at line 2592 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM18_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) != RESET)

Definition at line 2579 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)

Definition at line 2586 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)

Definition at line 2573 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)

Definition at line 2587 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)

Definition at line 2574 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)

Definition at line 2588 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)

Definition at line 2575 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)

Definition at line 2606 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)

Definition at line 2604 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)

Definition at line 2618 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)

Definition at line 2616 of file stm32f3xx_hal_rcc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Extended APB2 Peripheral Clock Enable Disable Status

Defines
RCC Extended APB2 Peripheral Clock Enable Disable Status
RCC Extended Exported Macros

Get the enable or disable status of the APB2 peripheral clock. More...

Defines

#define | __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
#define | __HAL_RCC_TIM19_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) != RESET)
#define | __HAL_RCC_SDADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) != RESET)
#define | __HAL_RCC_SDADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) != RESET)
#define | __HAL_RCC_SDADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) != RESET)
#define | __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
#define | __HAL_RCC_TIM19_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) == RESET)
#define | __HAL_RCC_SDADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) == RESET)
#define | __HAL_RCC_SDADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) == RESET)
#define | __HAL_RCC_SDADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) == RESET)

Detailed Description

Get the enable or disable status of the APB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)

Definition at line 2682 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)

Definition at line 2675 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) == RESET)

Definition at line 2685 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) != RESET)

Definition at line 2678 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC2_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) == RESET)

Definition at line 2686 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC2_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) != RESET)

Definition at line 2679 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC3_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) == RESET)

Definition at line 2687 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC3_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) != RESET)

Definition at line 2680 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)

Definition at line 2683 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)

Definition at line 2676 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM19_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) == RESET)

Definition at line 2684 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM19_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) != RESET)

Definition at line 2677 of file stm32f3xx_hal_rcc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Extended AHB Force Release Reset

Defines
RCC Extended AHB Force Release Reset
RCC Extended Exported Macros

Force or release AHB peripheral reset. More...

Defines

#define | __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
#define | __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))

Detailed Description

Force or release AHB peripheral reset.

Define Documentation

#define __HAL_RCC_GPIOE_FORCE_RESET ( ) (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))

Definition at line 2764 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_RELEASE_RESET ( ) (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))

Definition at line 2766 of file stm32f3xx_hal_rcc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Extended APB1 Force Release Reset

Defines
RCC Extended APB1 Force Release Reset
RCC Extended Exported Macros

Force or release APB1 peripheral reset. More...

Defines

#define | __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
#define | __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
#define | __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
#define | __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
#define | __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
#define | __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
#define | __HAL_RCC_TIM18_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM18RST))
#define | __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
#define | __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
#define | __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
#define | __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
#define | __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
#define | __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
#define | __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
#define | __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
#define | __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
#define | __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
#define | __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
#define | __HAL_RCC_TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
#define | __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
#define | __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
#define | __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
#define | __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
#define | __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
#define | __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
#define | __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
#define | __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
#define | __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
#define | __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
#define | __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))

Detailed Description

Force or release APB1 peripheral reset.

Define Documentation

#define __HAL_RCC_CAN1_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))

Definition at line 2879 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))

Definition at line 2881 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))

Definition at line 2838 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))

Definition at line 2851 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC2_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))

Definition at line 2837 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC2_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))

Definition at line 2850 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))

Definition at line 2836 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))

Definition at line 2849 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))

Definition at line 2834 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))

Definition at line 2847 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))

Definition at line 2835 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))

Definition at line 2848 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))

Definition at line 2830 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))

Definition at line 2843 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))

Definition at line 2831 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))

Definition at line 2844 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))

Definition at line 2832 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))

Definition at line 2845 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM18_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM18RST))

Definition at line 2833 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM18_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))

Definition at line 2846 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))

Definition at line 2827 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))

Definition at line 2840 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))

Definition at line 2828 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))

Definition at line 2841 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))

Definition at line 2829 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))

Definition at line 2842 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))

Definition at line 2858 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))

Definition at line 2860 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))

Definition at line 2870 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))

Definition at line 2872 of file stm32f3xx_hal_rcc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Extended APB2 Force Release Reset

Defines
RCC Extended APB2 Force Release Reset
RCC Extended Exported Macros

Force or release APB2 peripheral reset. More...

Defines

#define | __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
#define | __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
#define | __HAL_RCC_TIM19_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM19RST))
#define | __HAL_RCC_SDADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC1RST))
#define | __HAL_RCC_SDADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC2RST))
#define | __HAL_RCC_SDADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC3RST))
#define | __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
#define | __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
#define | __HAL_RCC_TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
#define | __HAL_RCC_SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
#define | __HAL_RCC_SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
#define | __HAL_RCC_SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))

Detailed Description

Force or release APB2 peripheral reset.

Define Documentation

#define __HAL_RCC_ADC1_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))

Definition at line 2926 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC1_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))

Definition at line 2933 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC1_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC1RST))

Definition at line 2929 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC1_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))

Definition at line 2936 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC2_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC2RST))

Definition at line 2930 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC2_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))

Definition at line 2937 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC3_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC3RST))

Definition at line 2931 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SDADC3_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))

Definition at line 2938 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))

Definition at line 2927 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))

Definition at line 2934 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM19_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM19RST))

Definition at line 2928 of file stm32f3xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM19_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))

Definition at line 2935 of file stm32f3xx_hal_rcc_ex.h.

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STM32F373xC HAL User Manual: RCC Extended I2Cx Clock Config

Defines
RCC Extended I2Cx Clock Config
RCC Extended Exported Macros

Defines

#define | __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
Macro to configure the I2C2 clock (I2C2CLK).
#define | __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
Macro to get the I2C2 clock source.

Define Documentation

#define __HAL_RCC_GET_I2C2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))

Macro to get the I2C2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock

Definition at line 3505 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_I2C2_CONFIG ( __I2C2CLKSource__ ) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))

Macro to configure the I2C2 clock (I2C2CLK).

Parameters:
__I2C2CLKSource__ specifies the I2C2 clock source. This parameter can be one of the following values:
  • RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock

Definition at line 3497 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32F373xC HAL User Manual: RCC Extended ADCx Clock Config

Defines
RCC Extended ADCx Clock Config
RCC Extended Exported Macros

Defines

#define | __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
Macro to configure the ADC1 clock (ADC1CLK).
#define | __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
Macro to get the ADC1 clock (ADC1CLK).

Define Documentation

#define __HAL_RCC_ADC1_CONFIG ( __ADC1CLKSource__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))

Macro to configure the ADC1 clock (ADC1CLK).

Parameters:
__ADC1CLKSource__ specifies the ADC1 clock source. This parameter can be one of the following values:
  • RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock
  • RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock
  • RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock
  • RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock

Definition at line 3521 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_ADC1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))

Macro to get the ADC1 clock (ADC1CLK).

Return values:
The clock source can be one of the following values:
  • RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock
  • RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock
  • RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock
  • RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock

Definition at line 3531 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

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STM32F373xC HAL User Manual: RCC Extended SDADCx Clock Config

Defines
RCC Extended SDADCx Clock Config
RCC Extended Exported Macros

Defines

#define | __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, (uint32_t)(__SDADCPrescaler__))
Macro to configure the SDADCx clock (SDADCxCLK).
#define | __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDPRE)))
Macro to get the SDADCx clock prescaler.

Define Documentation

#define __HAL_RCC_GET_SDADC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDPRE)))

Macro to get the SDADCx clock prescaler.

Return values:
The clock source can be one of the following values:
  • RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock

Definition at line 3583 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_SDADC_CONFIG ( __SDADCPrescaler__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, (uint32_t)(__SDADCPrescaler__))

Macro to configure the SDADCx clock (SDADCxCLK).

Parameters:
__SDADCPrescaler__ specifies the SDADCx system clock prescaler. This parameter can be one of the following values:
  • RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock
  • RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock

Definition at line 3560 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32F373xC HAL User Manual: RCC Extended CECx Clock Config

Defines
RCC Extended CECx Clock Config
RCC Extended Exported Macros

Defines

#define | __HAL_RCC_CEC_CONFIG(__CECCLKSource__) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
Macro to configure the CEC clock.
#define | __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
Macro to get the HDMI CEC clock source.

Define Documentation

#define __HAL_RCC_CEC_CONFIG ( __CECCLKSource__ ) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))

Macro to configure the CEC clock.

Parameters:
__CECCLKSource__ specifies the CEC clock source. This parameter can be one of the following values:
  • RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
  • RCC_CECCLKSOURCE_LSE LSE selected as CEC clock

Definition at line 3597 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_CEC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))

Macro to get the HDMI CEC clock source.

Return values:
The clock source can be one of the following values:
  • RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
  • RCC_CECCLKSOURCE_LSE LSE selected as CEC clock

Definition at line 3605 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Extended USBx Clock Config

Defines
RCC Extended USBx Clock Config
RCC Extended Exported Macros

Defines

#define | __HAL_RCC_USB_CONFIG(__USBCLKSource__) MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
Macro to configure the USB clock (USBCLK).
#define | __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
Macro to get the USB clock source.

Define Documentation

#define __HAL_RCC_GET_USB_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))

Macro to get the USB clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock
  • RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock

Definition at line 3634 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_USB_CONFIG ( __USBCLKSource__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))

Macro to configure the USB clock (USBCLK).

Parameters:
__USBCLKSource__ specifies the USB clock source. This parameter can be one of the following values:
  • RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock
  • RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock

Definition at line 3626 of file stm32f3xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: LSE Drive Configuration

Defines
LSE Drive Configuration
RCC Extended Exported Macros

Defines

#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__)
Macro to configure the External Low Speed oscillator (LSE) drive capability.

Define Documentation

#define __HAL_RCC_LSEDRIVE_CONFIG ( __RCC_LSEDRIVE__ )
Value:
(MODIFY_REG(RCC->BDCR,\
        RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))

Macro to configure the External Low Speed oscillator (LSE) drive capability.

Parameters:
__RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. This parameter can be one of the following values:
  • RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
  • RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
  • RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
  • RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
Return values:
None

Definition at line 3796 of file stm32f3xx_hal_rcc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Exported Types

Data Structures | Enumerations
RTC Exported Types
RTC

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | RTC_HandleTypeDef
RTC Handle Structure definition. More...

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00U, HAL_RTC_STATE_READY = 0x01U, HAL_RTC_STATE_BUSY = 0x02U, HAL_RTC_STATE_TIMEOUT = 0x03U,
HAL_RTC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_RTCStateTypeDef

HAL State structures definition.

Enumerator:
HAL_RTC_STATE_RESET

RTC not yet initialized or disabled

HAL_RTC_STATE_READY

RTC initialized and ready for use

HAL_RTC_STATE_BUSY

RTC process is ongoing

HAL_RTC_STATE_TIMEOUT

RTC timeout state

HAL_RTC_STATE_ERROR

RTC error state

Definition at line 63 of file stm32f3xx_hal_rtc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_InitTypeDef Struct Reference
RTC Exported Types

RTC Configuration Structure definition. More...

#include <stm32f3xx_hal_rtc.h>

Data Fields

uint32_t | HourFormat
uint32_t | AsynchPrediv
uint32_t | SynchPrediv
uint32_t | OutPut
uint32_t | OutPutPolarity
uint32_t | OutPutType

Detailed Description

RTC Configuration Structure definition.

Definition at line 76 of file stm32f3xx_hal_rtc.h.

Field Documentation

uint32_t RTC_InitTypeDef::AsynchPrediv

Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

Definition at line 81 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::HourFormat

Specifies the RTC Hour Format. This parameter can be a value of RTC Hour Formats

Definition at line 78 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPut

Specifies which signal will be routed to the RTC output. This parameter can be a value of RTC Extended Output Selection Definition

Definition at line 87 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutPolarity

Specifies the polarity of the output signal. This parameter can be a value of RTC Output Polarity Definitions

Definition at line 90 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutType

Specifies the RTC Output Pin mode. This parameter can be a value of RTC Output Type ALARM OUT

Definition at line 93 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::SynchPrediv

Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF

Definition at line 84 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_rtc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC_TimeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TimeTypeDef Struct Reference
RTC Exported Types

RTC Time structure definition. More...

#include <stm32f3xx_hal_rtc.h>

Data Fields

uint8_t | Hours
uint8_t | Minutes
uint8_t | Seconds
uint8_t | TimeFormat
uint32_t | SubSeconds
uint32_t | SecondFraction
uint32_t | DayLightSaving
uint32_t | StoreOperation

Detailed Description

RTC Time structure definition.

Definition at line 100 of file stm32f3xx_hal_rtc.h.

Field Documentation

uint32_t RTC_TimeTypeDef::DayLightSaving

Specifies RTC_DayLightSaveOperation: the value of hour adjustment. This parameter can be a value of RTC DayLightSaving Definitions

Definition at line 125 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint8_t RTC_TimeTypeDef::Hours

Specifies the RTC Time Hour. This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected

Definition at line 102 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::Minutes

Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 106 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint32_t RTC_TimeTypeDef::SecondFraction

Specifies the range or granularity of Sub Second register content corresponding to Synchronous pre-scaler factor value (PREDIV_S) This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity. This field will be used only by HAL_RTC_GetTime function

Definition at line 119 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetTime().

uint8_t RTC_TimeTypeDef::Seconds

Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 109 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint32_t RTC_TimeTypeDef::StoreOperation

Specifies RTC_StoreOperation value to be written in the BCK bit in CR register to store the operation. This parameter can be a value of RTC StoreOperation Definitions

Definition at line 128 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint32_t RTC_TimeTypeDef::SubSeconds

Specifies the RTC_SSR RTC Sub Second register content. This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity

Definition at line 115 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::TimeFormat

Specifies the RTC AM/PM Time. This parameter can be a value of RTC AM PM Definitions

Definition at line 112 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_rtc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC_DateTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_DateTypeDef Struct Reference
RTC Exported Types

RTC Date structure definition. More...

#include <stm32f3xx_hal_rtc.h>

Data Fields

uint8_t | WeekDay
uint8_t | Month
uint8_t | Date
uint8_t | Year

Detailed Description

RTC Date structure definition.

Definition at line 136 of file stm32f3xx_hal_rtc.h.

Field Documentation

uint8_t RTC_DateTypeDef::Date

Specifies the RTC Date. This parameter must be a number between Min_Data = 1 and Max_Data = 31

Definition at line 144 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Month

Specifies the RTC Date Month (in BCD format). This parameter can be a value of RTC Month Date Definitions

Definition at line 141 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::WeekDay

Specifies the RTC Date WeekDay. This parameter can be a value of RTC WeekDay Definitions

Definition at line 138 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Year

Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99

Definition at line 147 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_rtc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC_AlarmTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_AlarmTypeDef Struct Reference
RTC Exported Types

RTC Alarm structure definition. More...

#include <stm32f3xx_hal_rtc.h>

Data Fields

RTC_TimeTypeDef AlarmTime
uint32_t | AlarmMask
uint32_t | AlarmSubSecondMask
uint32_t | AlarmDateWeekDaySel
uint8_t | AlarmDateWeekDay
uint32_t | Alarm

Detailed Description

RTC Alarm structure definition.

Definition at line 155 of file stm32f3xx_hal_rtc.h.

Field Documentation

uint32_t RTC_AlarmTypeDef::Alarm

Specifies the alarm . This parameter can be a value of RTC Alarms Definitions

Definition at line 172 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint8_t RTC_AlarmTypeDef::AlarmDateWeekDay

Specifies the RTC Alarm Date/WeekDay. If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. If the Alarm WeekDay is selected, this parameter can be a value of RTC WeekDay Definitions

Definition at line 168 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmDateWeekDaySel

Specifies the RTC Alarm is on Date or WeekDay. This parameter can be a value of RTC AlarmDateWeekDay Definitions

Definition at line 165 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmMask

Specifies the RTC Alarm Masks. This parameter can be a value of RTC AlarmMask Definitions

Definition at line 159 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmSubSecondMask

Specifies the RTC Alarm SubSeconds Masks. This parameter can be a value of RTC Alarm Sub Seconds Masks Definitions

Definition at line 162 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

RTC_TimeTypeDef RTC_AlarmTypeDef::AlarmTime

Specifies the RTC Alarm Time members

Definition at line 157 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_rtc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_HandleTypeDef Struct Reference
RTC Exported Types

RTC Handle Structure definition. More...

#include <stm32f3xx_hal_rtc.h>

Data Fields

RTC_TypeDef * | Instance
RTC_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_RTCStateTypeDef | State

Detailed Description

RTC Handle Structure definition.

Definition at line 179 of file stm32f3xx_hal_rtc.h.

Field Documentation

RTC_InitTypeDef RTC_HandleTypeDef::Init

RTC required parameters

Definition at line 183 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

RTC_TypeDef* RTC_HandleTypeDef::Instance

Register base address

Definition at line 181 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_DeInit(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_GetWakeUpTimer(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and RTC_EnterInitMode().

HAL_LockTypeDef RTC_HandleTypeDef::Lock

RTC locking object

Definition at line 185 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

__IO HAL_RTCStateTypeDef RTC_HandleTypeDef::State

Time communication state

Definition at line 187 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetState(), HAL_RTC_Init(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_RTCEx_TamperTimeStampIRQHandler(), and HAL_RTCEx_WakeUpTimerIRQHandler().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_rtc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Hour Formats

Defines
RTC Hour Formats
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT_24 0x00000000U
#define | RTC_HOURFORMAT_12 RTC_CR_FMT

Define Documentation

#define RTC_HOURFORMAT_12 RTC_CR_FMT

Definition at line 203 of file stm32f3xx_hal_rtc.h.

#define RTC_HOURFORMAT_24 0x00000000U

Definition at line 202 of file stm32f3xx_hal_rtc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Output Polarity Definitions

Defines
RTC Output Polarity Definitions
RTC Exported Constants

Defines

#define | RTC_OUTPUT_POLARITY_HIGH 0x00000000U
#define | RTC_OUTPUT_POLARITY_LOW RTC_CR_POL

Define Documentation

#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U

Definition at line 211 of file stm32f3xx_hal_rtc.h.

#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL

Definition at line 212 of file stm32f3xx_hal_rtc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Output Type ALARM OUT

Defines
RTC Output Type ALARM OUT
RTC Exported Constants

Defines

#define | RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U
#define | RTC_OUTPUT_TYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE

Define Documentation

#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U

Definition at line 220 of file stm32f3xx_hal_rtc.h.

#define RTC_OUTPUT_TYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE

Definition at line 221 of file stm32f3xx_hal_rtc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC AM PM Definitions

Defines
RTC AM PM Definitions
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define | RTC_HOURFORMAT12_PM ((uint8_t)0x40)

Define Documentation

#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)

Definition at line 229 of file stm32f3xx_hal_rtc.h.

#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)

Definition at line 230 of file stm32f3xx_hal_rtc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC DayLightSaving Definitions

Defines
RTC DayLightSaving Definitions
RTC Exported Constants

Defines

#define | RTC_DAYLIGHTSAVING_NONE 0x00000000U
#define | RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
#define | RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H

Define Documentation

#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H

Definition at line 240 of file stm32f3xx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_NONE 0x00000000U

Definition at line 238 of file stm32f3xx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H

Definition at line 239 of file stm32f3xx_hal_rtc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC StoreOperation Definitions

Defines
RTC StoreOperation Definitions
RTC Exported Constants

Defines

#define | RTC_STOREOPERATION_RESET 0x00000000U
#define | RTC_STOREOPERATION_SET RTC_CR_BCK

Define Documentation

#define RTC_STOREOPERATION_RESET 0x00000000U

Definition at line 248 of file stm32f3xx_hal_rtc.h.

#define RTC_STOREOPERATION_SET RTC_CR_BCK

Definition at line 249 of file stm32f3xx_hal_rtc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Input parameter format definitions

Defines
RTC Input parameter format definitions
RTC Exported Constants

Defines

#define | RTC_FORMAT_BIN 0x000000000U
#define | RTC_FORMAT_BCD 0x000000001U

Define Documentation

#define RTC_FORMAT_BCD 0x000000001U

Definition at line 258 of file stm32f3xx_hal_rtc.h.

#define RTC_FORMAT_BIN 0x000000000U

Definition at line 257 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Month Date Definitions

Defines
RTC Month Date Definitions
RTC Exported Constants

Defines

#define | RTC_MONTH_JANUARY ((uint8_t)0x01)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define | RTC_MONTH_MARCH ((uint8_t)0x03)
#define | RTC_MONTH_APRIL ((uint8_t)0x04)
#define | RTC_MONTH_MAY ((uint8_t)0x05)
#define | RTC_MONTH_JUNE ((uint8_t)0x06)
#define | RTC_MONTH_JULY ((uint8_t)0x07)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12)

Define Documentation

#define RTC_MONTH_APRIL ((uint8_t)0x04)

Definition at line 270 of file stm32f3xx_hal_rtc.h.

#define RTC_MONTH_AUGUST ((uint8_t)0x08)

Definition at line 274 of file stm32f3xx_hal_rtc.h.

#define RTC_MONTH_DECEMBER ((uint8_t)0x12)

Definition at line 278 of file stm32f3xx_hal_rtc.h.

#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)

Definition at line 268 of file stm32f3xx_hal_rtc.h.

#define RTC_MONTH_JANUARY ((uint8_t)0x01)

Definition at line 267 of file stm32f3xx_hal_rtc.h.

#define RTC_MONTH_JULY ((uint8_t)0x07)

Definition at line 273 of file stm32f3xx_hal_rtc.h.

#define RTC_MONTH_JUNE ((uint8_t)0x06)

Definition at line 272 of file stm32f3xx_hal_rtc.h.

#define RTC_MONTH_MARCH ((uint8_t)0x03)

Definition at line 269 of file stm32f3xx_hal_rtc.h.

#define RTC_MONTH_MAY ((uint8_t)0x05)

Definition at line 271 of file stm32f3xx_hal_rtc.h.

#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)

Definition at line 277 of file stm32f3xx_hal_rtc.h.

#define RTC_MONTH_OCTOBER ((uint8_t)0x10)

Definition at line 276 of file stm32f3xx_hal_rtc.h.

#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)

Definition at line 275 of file stm32f3xx_hal_rtc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC WeekDay Definitions

Defines
RTC WeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)

Define Documentation

#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)

Definition at line 290 of file stm32f3xx_hal_rtc.h.

#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)

Definition at line 286 of file stm32f3xx_hal_rtc.h.

#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)

Definition at line 291 of file stm32f3xx_hal_rtc.h.

#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)

Definition at line 292 of file stm32f3xx_hal_rtc.h.

#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)

Definition at line 289 of file stm32f3xx_hal_rtc.h.

#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)

Definition at line 287 of file stm32f3xx_hal_rtc.h.

#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)

Definition at line 288 of file stm32f3xx_hal_rtc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC AlarmDateWeekDay Definitions

Defines
RTC AlarmDateWeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Define Documentation

#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U

Definition at line 300 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Definition at line 301 of file stm32f3xx_hal_rtc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC AlarmMask Definitions

Defines
RTC AlarmMask Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMMASK_NONE 0x00000000U
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL

Define Documentation

#define RTC_ALARMMASK_ALL
Value:
(RTC_ALARMMASK_NONE        | \
                                           RTC_ALARMMASK_DATEWEEKDAY | \
                                           RTC_ALARMMASK_HOURS       | \
                                           RTC_ALARMMASK_MINUTES     | \
                                           RTC_ALARMMASK_SECONDS)

Definition at line 314 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4

Definition at line 310 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3

Definition at line 311 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2

Definition at line 312 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMMASK_NONE 0x00000000U

Definition at line 309 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1

Definition at line 313 of file stm32f3xx_hal_rtc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Alarms Definitions

Defines
RTC Alarms Definitions
RTC Exported Constants

Defines

#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE

Define Documentation

#define RTC_ALARM_A RTC_CR_ALRAE

Definition at line 326 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARM_B RTC_CR_ALRBE

Definition at line 327 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Alarm Sub Seconds Masks Definitions

Defines
RTC Alarm Sub Seconds Masks Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMSUBSECONDMASK_ALL 0x00000000U
#define | RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0
#define | RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1
#define | RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)
#define | RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2
#define | RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3
#define | RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS

Define Documentation

#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U

All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm

Definition at line 335 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS

SS[14:0] are compared and must match to activate alarm.

Definition at line 366 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)

SS[14] is don't care in Alarm comparison.Only SS[13:0] are compared

Definition at line 364 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0

SS[14:1] are ignored in Alarm comparison. Only SS[0] is compared.

Definition at line 338 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)

SS[14:10] are ignored in Alarm comparison. Only SS[9:0] are compared

Definition at line 356 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)

SS[14:11] are ignored in Alarm comparison. Only SS[10:0] are compared

Definition at line 358 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)

SS[14:12] are ignored in Alarm comparison.Only SS[11:0] are compared

Definition at line 360 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)

SS[14:13] are ignored in Alarm comparison. Only SS[12:0] are compared

Definition at line 362 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1

SS[14:2] are ignored in Alarm comparison. Only SS[1:0] are compared

Definition at line 340 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)

SS[14:3] are ignored in Alarm comparison. Only SS[2:0] are compared

Definition at line 342 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2

SS[14:4] are ignored in Alarm comparison. Only SS[3:0] are compared

Definition at line 344 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)

SS[14:5] are ignored in Alarm comparison. Only SS[4:0] are compared

Definition at line 346 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)

SS[14:6] are ignored in Alarm comparison. Only SS[5:0] are compared

Definition at line 348 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)

SS[14:7] are ignored in Alarm comparison. Only SS[6:0] are compared

Definition at line 350 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3

SS[14:8] are ignored in Alarm comparison. Only SS[7:0] are compared

Definition at line 352 of file stm32f3xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)

SS[14:9] are ignored in Alarm comparison. Only SS[8:0] are compared

Definition at line 354 of file stm32f3xx_hal_rtc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Interrupts Definitions

Defines
RTC Interrupts Definitions
RTC Exported Constants

Defines

#define | RTC_IT_TS RTC_CR_TSIE
#define | RTC_IT_WUT RTC_CR_WUTIE
#define | RTC_IT_ALRB RTC_CR_ALRBIE
#define | RTC_IT_ALRA RTC_CR_ALRAIE
#define | RTC_IT_TAMP RTC_TAFCR_TAMPIE /* Used only to Enable the Tamper Interrupt */
#define | RTC_IT_TAMP1 0x00020000U /*only for RTC_ISR flag check*/
#define | RTC_IT_TAMP2 0x00040000U /*only for RTC_ISR flag check*/
#define | RTC_IT_TAMP3 0x00080000U /*only for RTC_ISR flag check*/

Define Documentation

#define RTC_IT_ALRA RTC_CR_ALRAIE

Definition at line 378 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_IT_ALRB RTC_CR_ALRBIE

Definition at line 377 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_IT_TAMP RTC_TAFCR_TAMPIE /* Used only to Enable the Tamper Interrupt */

Definition at line 379 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_TAMP1 0x00020000U /*only for RTC_ISR flag check*/

Definition at line 380 of file stm32f3xx_hal_rtc.h.

#define RTC_IT_TAMP2 0x00040000U /*only for RTC_ISR flag check*/

Definition at line 381 of file stm32f3xx_hal_rtc.h.

#define RTC_IT_TAMP3 0x00080000U /*only for RTC_ISR flag check*/

Definition at line 383 of file stm32f3xx_hal_rtc.h.

#define RTC_IT_TS RTC_CR_TSIE

Definition at line 375 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_WUT RTC_CR_WUTIE

Definition at line 376 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Flags Definitions

Defines
RTC Flags Definitions
RTC Exported Constants

Defines

#define | RTC_FLAG_RECALPF RTC_ISR_RECALPF
#define | RTC_FLAG_TAMP3F RTC_ISR_TAMP3F
#define | RTC_FLAG_TAMP2F RTC_ISR_TAMP2F
#define | RTC_FLAG_TAMP1F RTC_ISR_TAMP1F
#define | RTC_FLAG_TSOVF RTC_ISR_TSOVF
#define | RTC_FLAG_TSF RTC_ISR_TSF
#define | RTC_FLAG_WUTF RTC_ISR_WUTF
#define | RTC_FLAG_ALRBF RTC_ISR_ALRBF
#define | RTC_FLAG_ALRAF RTC_ISR_ALRAF
#define | RTC_FLAG_INITF RTC_ISR_INITF
#define | RTC_FLAG_RSF RTC_ISR_RSF
#define | RTC_FLAG_INITS RTC_ISR_INITS
#define | RTC_FLAG_SHPF RTC_ISR_SHPF
#define | RTC_FLAG_WUTWF RTC_ISR_WUTWF
#define | RTC_FLAG_ALRBWF RTC_ISR_ALRBWF
#define | RTC_FLAG_ALRAWF RTC_ISR_ALRAWF

Define Documentation

#define RTC_FLAG_ALRAF RTC_ISR_ALRAF

Definition at line 402 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_PollForAlarmAEvent(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF

Definition at line 409 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_ALRBF RTC_ISR_ALRBF

Definition at line 401 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF

Definition at line 408 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_INITF RTC_ISR_INITF

Definition at line 403 of file stm32f3xx_hal_rtc.h.

#define RTC_FLAG_INITS RTC_ISR_INITS

Definition at line 405 of file stm32f3xx_hal_rtc.h.

#define RTC_FLAG_RECALPF RTC_ISR_RECALPF

Definition at line 392 of file stm32f3xx_hal_rtc.h.

#define RTC_FLAG_RSF RTC_ISR_RSF

Definition at line 404 of file stm32f3xx_hal_rtc.h.

#define RTC_FLAG_SHPF RTC_ISR_SHPF

Definition at line 406 of file stm32f3xx_hal_rtc.h.

#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F

Definition at line 397 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F

Definition at line 396 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTamper2Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F

Definition at line 394 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTamper3Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TSF RTC_ISR_TSF

Definition at line 399 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_PollForTimeStampEvent(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TSOVF RTC_ISR_TSOVF

Definition at line 398 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTimeStampEvent().

#define RTC_FLAG_WUTF RTC_ISR_WUTF

Definition at line 400 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define RTC_FLAG_WUTWF RTC_ISR_WUTWF

Definition at line 407 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Exported Macros

Defines
RTC Exported Macros
RTC

Defines

#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Alarm interrupt has been enabled or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Alarm's flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Alarm's pending flags.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
Clear the RTC Alarm associated Exti line flag.
#define | __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
Generate a Software interrupt on RTC Alarm associated Exti line.

Define Documentation

#define __HAL_RTC_ALARM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Alarm's pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Alarm Flag sources to clear. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
Return values:
None

Definition at line 544 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define __HAL_RTC_ALARM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC Alarm interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 498 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), and HAL_RTC_SetAlarm().

#define __HAL_RTC_ALARM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC Alarm interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 487 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG ( ) (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)

Clear the RTC Alarm associated Exti line flag.

Return values:
None.

Definition at line 616 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler().

#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT ( ) (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable event on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 568 of file stm32f3xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 580 of file stm32f3xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_IT ( ) (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 556 of file stm32f3xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable rising edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 592 of file stm32f3xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE ( ) __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();

Disable rising & falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 604 of file stm32f3xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT ( ) (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)

Enable event on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 562 of file stm32f3xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)

Enable falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 574 of file stm32f3xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_IT ( ) (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)

Enable interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 550 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)

Enable rising edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 586 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE ( ) __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();

Enable rising & falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 598 of file stm32f3xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)

Generate a Software interrupt on RTC Alarm associated Exti line.

Return values:
None.

Definition at line 622 of file stm32f3xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_GET_FLAG ( ) (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)

Check whether the RTC Alarm associated Exti line interrupt flag is set or not.

Return values:
Line Status.

Definition at line 610 of file stm32f3xx_hal_rtc.h.

#define __HAL_RTC_ALARM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)

Get the selected RTC Alarm's flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Alarm Flag sources to check. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
  • RTC_FLAG_ALRAWF
  • RTC_FLAG_ALRBWF
Return values:
None

Definition at line 533 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define __HAL_RTC_ALARM_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)

Check whether the specified RTC Alarm interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt to check. This parameter can be:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 509 of file stm32f3xx_hal_rtc.h.

#define __HAL_RTC_ALARM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Alarm interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to check. This parameter can be:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 520 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler().

#define __HAL_RTC_ALARMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))

Disable the RTC ALARMA peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 462 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))

Enable the RTC ALARMA peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 455 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMB_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))

Disable the RTC ALARMB peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 476 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMB_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))

Enable the RTC ALARMB peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 469 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)

Reset RTC handle state.

Parameters:
__HANDLE__ RTC handle.
Return values:
None

Definition at line 427 of file stm32f3xx_hal_rtc.h.

#define __HAL_RTC_WRITEPROTECTION_DISABLE ( __HANDLE__ )
Value:
do{                                       \
                            (__HANDLE__)->Instance->WPR = 0xCAU;   \
                            (__HANDLE__)->Instance->WPR = 0x53U;   \
                          } while(0U)

Disable the write protection for RTC registers.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 434 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WRITEPROTECTION_ENABLE ( __HANDLE__ )
Value:
do{                                       \
                            (__HANDLE__)->Instance->WPR = 0xFFU;   \
                          } while(0U)

Enable the write protection for RTC registers.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 445 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RTC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC according to the specified parameters in the RTC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
   [..] This section provides functions allowing to initialize and configure the
         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
         RTC registers Write protection, enter and exit the RTC initialization mode,
         RTC registers synchronization check and reference clock detection enable.
         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
             It is split into 2 programmable prescalers to minimize power consumption.
             (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
             (++) When both prescalers are used, it is recommended to configure the
                 asynchronous prescaler to a high value to minimize power consumption.
         (#) All RTC registers are Write protected. Writing to the RTC registers
             is enabled by writing a key into the Write Protection register, RTC_WPR.
         (#) To configure the RTC Calendar, user application should enter
             initialization mode. In this mode, the calendar counter is stopped
             and its value can be updated. When the initialization sequence is
             complete, the calendar restarts counting after 4 RTCCLK cycles.
         (#) To read the calendar through the shadow registers after Calendar
             initialization, calendar update or after wakeup from low power modes
             the software must first clear the RSF flag. The software must then
             wait until it is set again before reading the calendar, which means
             that the calendar registers have been correctly copied into the
             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
             implements the above software sequence (RSF clear and RSF check).

Function Documentation

HAL_StatusTypeDef HAL_RTC_DeInit ( RTC_HandleTypeDef * hrtc )

DeInitialize the RTC peripheral.

Parameters:
hrtc RTC handle
Note:
This function doesn't reset the RTC Backup Data registers.
Return values:
HAL status

Definition at line 331 of file stm32f3xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_MspDeInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_RESET, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_Init ( RTC_HandleTypeDef * hrtc )

Initialize the RTC according to the specified parameters in the RTC_InitTypeDef structure and initialize the associated handle.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 241 of file stm32f3xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_InitTypeDef::AsynchPrediv, HAL_RTC_MspInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, HAL_RTC_WaitForSynchro(), RTC_InitTypeDef::HourFormat, RTC_HandleTypeDef::Init, RTC_HandleTypeDef::Instance, IS_RTC_ASYNCH_PREDIV, IS_RTC_HOUR_FORMAT, IS_RTC_OUTPUT, IS_RTC_OUTPUT_POL, IS_RTC_OUTPUT_TYPE, IS_RTC_SYNCH_PREDIV, RTC_HandleTypeDef::Lock, RTC_InitTypeDef::OutPut, RTC_InitTypeDef::OutPutPolarity, RTC_InitTypeDef::OutPutType, RTC_EnterInitMode(), RTC_HandleTypeDef::State, and RTC_InitTypeDef::SynchPrediv.

void HAL_RTC_MspDeInit ( RTC_HandleTypeDef * hrtc )

DeInitialize the RTC MSP.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 446 of file stm32f3xx_hal_rtc.c.

Referenced by HAL_RTC_DeInit().

void HAL_RTC_MspInit ( RTC_HandleTypeDef * hrtc )

Initialize the RTC MSP.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 431 of file stm32f3xx_hal_rtc.c.

Referenced by HAL_RTC_Init().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Time and Date functions

Functions
RTC Time and Date functions
RTC Exported Functions

RTC Time and Date functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.

Detailed Description

RTC Time and Date functions.

 ===============================================================================
                 ##### RTC Time and Date functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Time and Date features

Function Documentation

HAL_StatusTypeDef HAL_RTC_GetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Get RTC current date.

Parameters:
hrtc | RTC handle
sDate | Pointer to Date structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN : Binary data format
  • RTC_FORMAT_BCD : BCD data format
Return values:
HAL status

Definition at line 766 of file stm32f3xx_hal_rtc.c.

References assert_param, RTC_DateTypeDef::Date, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FORMAT_BIN, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_GetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Get RTC current time.

Parameters:
hrtc | RTC handle
sTime | Pointer to Time structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds value in second fraction ratio with time unit following generic formula: Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers.
Return values:
HAL status

Definition at line 614 of file stm32f3xx_hal_rtc.c.

References assert_param, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::SecondFraction, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Set RTC current date.

Parameters:
hrtc | RTC handle
sDate | Pointer to date structure
Format specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 658 of file stm32f3xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_DateTypeDef::Date, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, IS_RTC_DATE, IS_RTC_FORMAT, IS_RTC_MONTH, IS_RTC_WEEKDAY, IS_RTC_YEAR, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_DR_RESERVED_MASK, RTC_EnterInitMode(), RTC_FORMAT_BIN, RTC_HandleTypeDef::State, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_SetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Set RTC current time.

Parameters:
hrtc | RTC handle
sTime | Pointer to Time structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 484 of file stm32f3xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_TimeTypeDef::DayLightSaving, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_WaitForSynchro(), RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_DAYLIGHT_SAVING, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, IS_RTC_STORE_OPERATION, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_EnterInitMode(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::StoreOperation, and RTC_TimeTypeDef::TimeFormat.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Alarm functions

Functions
RTC Alarm functions
RTC Exported Functions

RTC Alarm functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.

Detailed Description

RTC Alarm functions.

 ===============================================================================
                 ##### RTC Alarm functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Alarm feature

Function Documentation

void HAL_RTC_AlarmAEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm A callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1375 of file stm32f3xx_hal_rtc.c.

Referenced by HAL_RTC_AlarmIRQHandler().

void HAL_RTC_AlarmIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle Alarm interrupt request.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1333 of file stm32f3xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_EXTI_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARM_GET_IT_SOURCE, HAL_RTC_AlarmAEventCallback(), HAL_RTC_STATE_READY, HAL_RTCEx_AlarmBEventCallback(), RTC_FLAG_ALRAF, RTC_FLAG_ALRBF, RTC_IT_ALRA, RTC_IT_ALRB, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_DeactivateAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Alarm
 | ) |  |

Deactivate the specified RTC Alarm.

Parameters:
hrtc RTC handle
Alarm Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A : AlarmA
  • RTC_ALARM_B : AlarmB
Return values:
HAL status

Definition at line 1189 of file stm32f3xx_hal_rtc.c.

References __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, IS_RTC_ALARM, RTC_ALARM_A, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_GetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Alarm,
 |  | uint32_t | Format
 | ) |  |

Get the RTC Alarm value and masks.

Parameters:
hrtc | RTC handle
sAlarm | Pointer to Date structure
Alarm Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1283 of file stm32f3xx_hal_rtc.c.

References RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmTime, assert_param, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARM_B, RTC_ALARMMASK_ALL, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle AlarmA Polling request.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1391 of file stm32f3xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRAF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_SetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Set the specified RTC Alarm.

Parameters:
hrtc | RTC handle
sAlarm | Pointer to Alarm structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 820 of file stm32f3xx_hal_rtc.c.

References __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetAlarm_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Set the specified RTC Alarm with Interrupt.

Parameters:
hrtc | RTC handle
sAlarm | Pointer to Alarm structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
The Alarm register can only be written when the corresponding Alarm is disabled (Use the HAL_RTC_DeactivateAlarm()).
The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
Return values:
HAL status

Definition at line 1004 of file stm32f3xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_ENABLE_IT, __HAL_RTC_ALARM_EXTI_ENABLE_IT, __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_FLAG_ALRAF, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RTC Exported Functions

Functions

HAL_StatusTypeDef HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
@addtogroup RTC_Exported_Functions_Group4 Peripheral Control functions

Function Documentation

HAL_StatusTypeDef HAL_RTC_WaitForSynchro ( RTC_HandleTypeDef * hrtc )

@addtogroup RTC_Exported_Functions_Group4 Peripheral Control functions

Peripheral Control functions

 ===============================================================================
                     ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Wait for RTC Time and Date Synchronization

Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1450 of file stm32f3xx_hal_rtc.c.

References HAL_GetTick(), RTC_HandleTypeDef::Instance, RTC_RSF_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_SetSynchroShift().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RTC Exported Functions

Functions

HAL_RTCStateTypeDef HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
@addtogroup RTC_Exported_Functions_Group5 Peripheral State functions

Function Documentation

HAL_RTCStateTypeDef HAL_RTC_GetState ( RTC_HandleTypeDef * hrtc )

@addtogroup RTC_Exported_Functions_Group5 Peripheral State functions

Peripheral State functions

 ===============================================================================
                     ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Get RTC state

Return the RTC handle state.

Parameters:
hrtc RTC handle
Return values:
HAL state

Definition at line 1494 of file stm32f3xx_hal_rtc.c.

References RTC_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Exported Functions

Modules
RTC Exported Functions
RTC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

RTC Time and Date functions

RTC Time and Date functions.

RTC Alarm functions

RTC Alarm functions.

Peripheral Control functions
Peripheral State functions
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
@addtogroup RTC_Exported_Functions_Group4 Peripheral Control functions
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
@addtogroup RTC_Exported_Functions_Group5 Peripheral State functions

Function Documentation

HAL_RTCStateTypeDef HAL_RTC_GetState ( RTC_HandleTypeDef * hrtc )

@addtogroup RTC_Exported_Functions_Group5 Peripheral State functions

Peripheral State functions

 ===============================================================================
                     ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Get RTC state

Return the RTC handle state.

Parameters:
hrtc RTC handle
Return values:
HAL state

Definition at line 1494 of file stm32f3xx_hal_rtc.c.

References RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_WaitForSynchro ( RTC_HandleTypeDef * hrtc )

@addtogroup RTC_Exported_Functions_Group4 Peripheral Control functions

Peripheral Control functions

 ===============================================================================
                     ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Wait for RTC Time and Date Synchronization

Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1450 of file stm32f3xx_hal_rtc.c.

References HAL_GetTick(), RTC_HandleTypeDef::Instance, RTC_RSF_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_SetSynchroShift().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Private Constants

Defines
RTC Private Constants
RTC

Defines

#define | RTC_TR_RESERVED_MASK 0x007F7F7FU
#define | RTC_DR_RESERVED_MASK 0x00FFFF3FU
#define | RTC_INIT_MASK 0xFFFFFFFFU
#define | RTC_RSF_MASK 0xFFFFFF5FU
#define | RTC_FLAGS_MASK
#define | RTC_TIMEOUT_VALUE 1000
#define | RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17
#define | RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR_MR19
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR20

Define Documentation

#define RTC_DR_RESERVED_MASK 0x00FFFF3FU

Definition at line 706 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17

External interrupt line 17 Connected to the RTC Alarm event

Definition at line 718 of file stm32f3xx_hal_rtc.h.

#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR_MR19

External interrupt line 19 Connected to the RTC Tamper and Time Stamp events

Definition at line 719 of file stm32f3xx_hal_rtc.h.

#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR20

External interrupt line 20 Connected to the RTC Wakeup event

Definition at line 720 of file stm32f3xx_hal_rtc.h.

#define RTC_FLAGS_MASK
Value:
((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
                                             RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF       | \
                                             RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF      | \
                                             RTC_FLAG_INITF | RTC_FLAG_RSF                        | \
                                             RTC_FLAG_INITS | RTC_FLAG_SHPF | RTC_FLAG_WUTWF      | \
                                             RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF))

Definition at line 709 of file stm32f3xx_hal_rtc.h.

#define RTC_INIT_MASK 0xFFFFFFFFU

Definition at line 707 of file stm32f3xx_hal_rtc.h.

Referenced by RTC_EnterInitMode().

#define RTC_RSF_MASK 0xFFFFFF5FU

Definition at line 708 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_WaitForSynchro().

#define RTC_TIMEOUT_VALUE 1000

Definition at line 716 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and RTC_EnterInitMode().

#define RTC_TR_RESERVED_MASK 0x007F7F7FU

Definition at line 705 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetTime(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Private macros to check input parameters

Defines
RTC Private macros to check input parameters
RTC Private Macros

Defines

#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | IS_RTC_OUTPUT_POL(POL)
#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
#define | IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU)
#define | IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
#define | IS_RTC_HOURFORMAT12(PM)
#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
#define | IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
#define | IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)

Define Documentation

#define IS_RTC_ALARM ( ALARM ) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))

Definition at line 789 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_DATE ( DATE ) (((DATE) > 0U) && ((DATE) <= 31U))

Definition at line 774 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_SEL ( SEL )
Value:
(((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))

Definition at line 784 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

Definition at line 776 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_MASK ( MASK ) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)

Definition at line 787 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_MASK ( MASK )
Value:
(((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))

Definition at line 793 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_VALUE ( VALUE ) ((VALUE) <= 0x00007FFFU)

Definition at line 791 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ASYNCH_PREDIV ( PREDIV ) ((PREDIV) <= 0x7FU)

Definition at line 743 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_DATE ( DATE ) (((DATE) >= 1U) && ((DATE) <= 31U))

Definition at line 764 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_DAYLIGHT_SAVING ( SAVE )
Value:
(((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))

Definition at line 751 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_FORMAT ( FORMAT ) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))

Definition at line 758 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

#define IS_RTC_HOUR12 ( HOUR ) (((HOUR) > 0U) && ((HOUR) <= 12U))

Definition at line 741 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR24 ( HOUR ) ((HOUR) <= 23U)

Definition at line 742 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR_FORMAT ( FORMAT )
Value:
(((FORMAT) == RTC_HOURFORMAT_12) || \
                                        ((FORMAT) == RTC_HOURFORMAT_24))

Definition at line 733 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_HOURFORMAT12 ( PM )
Value:
(((PM) == RTC_HOURFORMAT12_AM) || \
                                  ((PM) == RTC_HOURFORMAT12_PM))

Definition at line 748 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MINUTES ( MINUTES ) ((MINUTES) <= 59U)

Definition at line 745 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MONTH ( MONTH ) (((MONTH) >= 1U) && ((MONTH) <= 12U))

Definition at line 762 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_OUTPUT_POL ( POL )
Value:
(((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
                                ((POL) == RTC_OUTPUT_POLARITY_LOW))

Definition at line 736 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_TYPE ( TYPE )
Value:
(((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))

Definition at line 739 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_SECONDS ( SECONDS ) ((SECONDS) <= 59U)

Definition at line 746 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_STORE_OPERATION ( OPERATION )
Value:
(((OPERATION) == RTC_STOREOPERATION_RESET) || \
                                           ((OPERATION) == RTC_STOREOPERATION_SET))

Definition at line 755 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_SYNCH_PREDIV ( PREDIV ) ((PREDIV) <= 0x7FFFU)

Definition at line 744 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

Definition at line 766 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_YEAR ( YEAR ) ((YEAR) <= 99U)

Definition at line 760 of file stm32f3xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Private Functions

Functions
RTC Private Functions
RTC

Functions

HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
@addtogroup RTC_Private_Functions RTC Private Functions
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Function Documentation

uint8_t RTC_Bcd2ToByte ( uint8_t Value )

Convert from 2 digit BCD to Binary.

Parameters:
Value BCD value to be converted
Return values:
Converted word

Definition at line 1569 of file stm32f3xx_hal_rtc.c.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_ByteToBcd2 ( uint8_t Value )

Convert a 2 digit decimal to BCD format.

Parameters:
Value Byte to be converted
Return values:
Converted byte

Definition at line 1551 of file stm32f3xx_hal_rtc.c.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

HAL_StatusTypeDef RTC_EnterInitMode ( RTC_HandleTypeDef * hrtc )

@addtogroup RTC_Private_Functions RTC Private Functions

Enter the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
Parameters:
hrtc RTC handle
Return values:
An ErrorStatus enumeration value:
  • HAL_OK : RTC is in Init mode
  • HAL_TIMEOUT : RTC is not in Init mode and in Timeout

Definition at line 1521 of file stm32f3xx_hal_rtc.c.

References HAL_GetTick(), RTC_HandleTypeDef::Instance, RTC_INIT_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateRefClock(), and HAL_RTCEx_SetRefClock().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC

Modules
RTC
STM32F3xx_HAL_Driver

RTC HAL module driver. More...

Modules

RTC Exported Types
RTC Exported Constants
RTC Exported Macros
RTC Exported Functions
RTC Private Constants
RTC Private Macros
RTC Private Functions
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
@addtogroup RTC_Private_Functions RTC Private Functions
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Detailed Description

RTC HAL module driver.

Function Documentation

uint8_t RTC_Bcd2ToByte ( uint8_t Value )

Convert from 2 digit BCD to Binary.

Parameters:
Value BCD value to be converted
Return values:
Converted word

Definition at line 1569 of file stm32f3xx_hal_rtc.c.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_ByteToBcd2 ( uint8_t Value )

Convert a 2 digit decimal to BCD format.

Parameters:
Value Byte to be converted
Return values:
Converted byte

Definition at line 1551 of file stm32f3xx_hal_rtc.c.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

HAL_StatusTypeDef RTC_EnterInitMode ( RTC_HandleTypeDef * hrtc )

@addtogroup RTC_Private_Functions RTC Private Functions

Enter the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
Parameters:
hrtc RTC handle
Return values:
An ErrorStatus enumeration value:
  • HAL_OK : RTC is in Init mode
  • HAL_TIMEOUT : RTC is not in Init mode and in Timeout

Definition at line 1521 of file stm32f3xx_hal_rtc.c.

References HAL_GetTick(), RTC_HandleTypeDef::Instance, RTC_INIT_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateRefClock(), and HAL_RTCEx_SetRefClock().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC_TamperTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TamperTypeDef Struct Reference
RTC Extended Exported Types

RTC Tamper structure definition. More...

#include <stm32f3xx_hal_rtc_ex.h>

Data Fields

uint32_t | Tamper
uint32_t | Trigger
uint32_t | Filter
uint32_t | SamplingFrequency
uint32_t | PrechargeDuration
uint32_t | TamperPullUp
uint32_t | TimeStampOnTamperDetection

Detailed Description

RTC Tamper structure definition.

Definition at line 64 of file stm32f3xx_hal_rtc_ex.h.

Field Documentation

uint32_t RTC_TamperTypeDef::Filter

Specifies the RTC Filter Tamper. This parameter can be a value of RTC Extended Tamper Filter Definition

Definition at line 72 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::PrechargeDuration

Specifies the Precharge Duration . This parameter can be a value of RTC Extended Tamper Pin Precharge Duration Definition

Definition at line 78 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::SamplingFrequency

Specifies the sampling frequency. This parameter can be a value of RTC Extended Tamper Sampling Frequencies Definition

Definition at line 75 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Tamper

Specifies the Tamper Pin. This parameter can be a value of RTC Extended Tamper Pins Definition

Definition at line 66 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TamperPullUp

Specifies the Tamper PullUp . This parameter can be a value of RTC Extended Tamper Pull UP Definition

Definition at line 81 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TimeStampOnTamperDetection

Specifies the TimeStampOnTamperDetection. This parameter can be a value of RTC Extended Tamper TimeStampOnTamperDetection Definition

Definition at line 84 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Trigger

Specifies the Tamper Trigger. This parameter can be a value of RTC Extended Tamper Trigger Definition

Definition at line 69 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_rtc_ex.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Output Selection Definition

Defines
RTC Extended Output Selection Definition
RTC Extended Exported Constants

Defines

#define | RTC_OUTPUT_DISABLE 0x00000000U
#define | RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
#define | RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
#define | RTC_OUTPUT_WAKEUP RTC_CR_OSEL

Define Documentation

#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0

Definition at line 100 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1

Definition at line 101 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_OUTPUT_DISABLE 0x00000000U

Definition at line 99 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL

Definition at line 102 of file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Backup Registers Definition

Defines
RTC Extended Backup Registers Definition
RTC Extended Exported Constants

Defines

#define | RTC_BKP_DR0 0x00000000U
#define | RTC_BKP_DR1 0x00000001U
#define | RTC_BKP_DR2 0x00000002U
#define | RTC_BKP_DR3 0x00000003U
#define | RTC_BKP_DR4 0x00000004U
#define | RTC_BKP_DR5 0x00000005U
#define | RTC_BKP_DR6 0x00000006U
#define | RTC_BKP_DR7 0x00000007U
#define | RTC_BKP_DR8 0x00000008U
#define | RTC_BKP_DR9 0x00000009U
#define | RTC_BKP_DR10 0x0000000AU
#define | RTC_BKP_DR11 0x0000000BU
#define | RTC_BKP_DR12 0x0000000CU
#define | RTC_BKP_DR13 0x0000000DU
#define | RTC_BKP_DR14 0x0000000EU
#define | RTC_BKP_DR15 0x0000000FU
#define | RTC_BKP_DR16 0x00000010U
#define | RTC_BKP_DR17 0x00000011U
#define | RTC_BKP_DR18 0x00000012U
#define | RTC_BKP_DR19 0x00000013U
#define | RTC_BKP_DR20 0x00000014U
#define | RTC_BKP_DR21 0x00000015U
#define | RTC_BKP_DR22 0x00000016U
#define | RTC_BKP_DR23 0x00000017U
#define | RTC_BKP_DR24 0x00000018U
#define | RTC_BKP_DR25 0x00000019U
#define | RTC_BKP_DR26 0x0000001AU
#define | RTC_BKP_DR27 0x0000001BU
#define | RTC_BKP_DR28 0x0000001CU
#define | RTC_BKP_DR29 0x0000001DU
#define | RTC_BKP_DR30 0x0000001EU
#define | RTC_BKP_DR31 0x0000001FU

Define Documentation

#define RTC_BKP_DR0 0x00000000U

Definition at line 111 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR1 0x00000001U

Definition at line 112 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR10 0x0000000AU

Definition at line 124 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR11 0x0000000BU

Definition at line 125 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR12 0x0000000CU

Definition at line 126 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR13 0x0000000DU

Definition at line 127 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR14 0x0000000EU

Definition at line 128 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR15 0x0000000FU

Definition at line 129 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR16 0x00000010U

Definition at line 133 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR17 0x00000011U

Definition at line 134 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR18 0x00000012U

Definition at line 135 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR19 0x00000013U

Definition at line 136 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR2 0x00000002U

Definition at line 113 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR20 0x00000014U

Definition at line 140 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR21 0x00000015U

Definition at line 141 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR22 0x00000016U

Definition at line 142 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR23 0x00000017U

Definition at line 143 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR24 0x00000018U

Definition at line 144 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR25 0x00000019U

Definition at line 145 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR26 0x0000001AU

Definition at line 146 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR27 0x0000001BU

Definition at line 147 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR28 0x0000001CU

Definition at line 148 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR29 0x0000001DU

Definition at line 149 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR3 0x00000003U

Definition at line 114 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR30 0x0000001EU

Definition at line 150 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR31 0x0000001FU

Definition at line 151 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR4 0x00000004U

Definition at line 115 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR5 0x00000005U

Definition at line 119 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR6 0x00000006U

Definition at line 120 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR7 0x00000007U

Definition at line 121 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR8 0x00000008U

Definition at line 122 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_BKP_DR9 0x00000009U

Definition at line 123 of file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Time Stamp Edges definition

Defines
RTC Extended Time Stamp Edges definition
RTC Extended Exported Constants

Defines

#define | RTC_TIMESTAMPEDGE_RISING 0x00000000U
#define | RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE

Define Documentation

#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE

Definition at line 161 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPEDGE_RISING 0x00000000U

Definition at line 160 of file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended TimeStamp Pin Selection

Defines
RTC Extended TimeStamp Pin Selection
RTC Extended Exported Constants

Defines

#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U

Define Documentation

#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U

Definition at line 169 of file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Tamper Pins Definition

Defines
RTC Extended Tamper Pins Definition
RTC Extended Exported Constants

Defines

#define | RTC_TAMPER_1 RTC_TAFCR_TAMP1E
#define | RTC_TAMPER_2 RTC_TAFCR_TAMP2E
#define | RTC_TAMPER_3 RTC_TAFCR_TAMP3E

Define Documentation

#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E

Definition at line 177 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPER_2 RTC_TAFCR_TAMP2E

Definition at line 178 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPER_3 RTC_TAFCR_TAMP3E

Definition at line 180 of file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Tamper Trigger Definition

Defines
RTC Extended Tamper Trigger Definition
RTC Extended Exported Constants

Defines

#define | RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U
#define | RTC_TAMPERTRIGGER_FALLINGEDGE RTC_TAFCR_TAMP1TRG
#define | RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define | RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE

Define Documentation

#define RTC_TAMPERTRIGGER_FALLINGEDGE RTC_TAFCR_TAMP1TRG

Definition at line 191 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE

Definition at line 193 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE

Definition at line 192 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U

Definition at line 190 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Tamper Filter Definition

Defines
RTC Extended Tamper Filter Definition
RTC Extended Exported Constants

Defines

#define | RTC_TAMPERFILTER_DISABLE 0x00000000U
#define | RTC_TAMPERFILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0
#define | RTC_TAMPERFILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1
#define | RTC_TAMPERFILTER_8SAMPLE RTC_TAFCR_TAMPFLT

Define Documentation

#define RTC_TAMPERFILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0

Tamper is activated after 2 consecutive samples at the active level

Definition at line 203 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1

Tamper is activated after 4 consecutive samples at the active level

Definition at line 205 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_8SAMPLE RTC_TAFCR_TAMPFLT

Tamper is activated after 8 consecutive samples at the active level.

Definition at line 207 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_DISABLE 0x00000000U

Tamper filter is disabled

Definition at line 201 of file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Tamper Sampling Frequencies Definition

Defines
RTC Extended Tamper Sampling Frequencies Definition
RTC Extended Exported Constants

Defines

#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAFCR_TAMPFREQ_0
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAFCR_TAMPFREQ_1
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAFCR_TAMPFREQ_2
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_2)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2)

Define Documentation

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_2)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024

Definition at line 226 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAFCR_TAMPFREQ_0

Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384U

Definition at line 218 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAFCR_TAMPFREQ_2

Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048

Definition at line 224 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 256

Definition at line 230 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U

Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768U

Definition at line 216 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096

Definition at line 222 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 512

Definition at line 228 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAFCR_TAMPFREQ_1

Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192

Definition at line 220 of file stm32f3xx_hal_rtc_ex.h.

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STM32F373xC HAL User Manual: RTC Extended Tamper Pin Precharge Duration Definition

Defines
RTC Extended Tamper Pin Precharge Duration Definition
RTC Extended Exported Constants

Defines

#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK (RTC_TAFCR_TAMPPRCH_0 | RTC_TAFCR_TAMPPRCH_1)

Define Documentation

#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U

Tamper pins are pre-charged before sampling during 1 RTCCLK cycle

Definition at line 239 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0

Tamper pins are pre-charged before sampling during 2 RTCCLK cycles

Definition at line 241 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1

Tamper pins are pre-charged before sampling during 4 RTCCLK cycles

Definition at line 243 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (RTC_TAFCR_TAMPPRCH_0 | RTC_TAFCR_TAMPPRCH_1)

Tamper pins are pre-charged before sampling during 8 RTCCLK cycles

Definition at line 245 of file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Tamper TimeStampOnTamperDetection Definition

Defines
RTC Extended Tamper TimeStampOnTamperDetection Definition
RTC Extended Exported Constants

Defines

#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS)
#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U

Define Documentation

#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U

TimeStamp on Tamper Detection event is not saved

Definition at line 255 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS)

TimeStamp on Tamper Detection event saved

Definition at line 254 of file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Tamper Pull UP Definition

Defines
RTC Extended Tamper Pull UP Definition
RTC Extended Exported Constants

Defines

#define | RTC_TAMPER_PULLUP_ENABLE 0x00000000U
#define | RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS)

Define Documentation

#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS)

Tamper pins are not pre-charged before sampling

Definition at line 264 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U

Tamper pins are pre-charged before sampling

Definition at line 263 of file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Wakeup Timer Definition

Defines
RTC Extended Wakeup Timer Definition
RTC Extended Exported Constants

Defines

#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS (RTC_CR_WUCKSEL_2)
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)

Define Documentation

#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS (RTC_CR_WUCKSEL_2)

Definition at line 276 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)

Definition at line 277 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U

Definition at line 272 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)

Definition at line 275 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1

Definition at line 274 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0

Definition at line 273 of file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Smooth calib period Definition

Defines
RTC Extended Smooth calib period Definition
RTC Extended Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U
#define | RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8

Define Documentation

#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16

If RTCCLK = 32768 Hz, Smooth calibation period is 16s, else 2exp19 RTCCLK seconds

Definition at line 287 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U

If RTCCLK = 32768 Hz, Smooth calibation period is 32s, else 2exp20 RTCCLK seconds

Definition at line 285 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8

If RTCCLK = 32768 Hz, Smooth calibation period is 8s, else 2exp18 RTCCLK seconds

Definition at line 289 of file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Smooth calib Plus pulses Definition

Defines
RTC Extended Smooth calib Plus pulses Definition
RTC Extended Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U
#define | RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP

Define Documentation

#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U

The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0]

Definition at line 298 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP

The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0] with Y = 512U, 256U, 128 when X = 32U, 16U, 8U

Definition at line 300 of file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Calib Output selection Definition

Defines
RTC Extended Calib Output selection Definition
RTC Extended Exported Constants

Defines

#define | RTC_CALIBOUTPUT_512HZ 0x00000000U
#define | RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL

Define Documentation

#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL

Definition at line 311 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_CALIBOUTPUT_512HZ 0x00000000U

Definition at line 310 of file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Add 1 Second Parameter Definition

Defines
RTC Extended Add 1 Second Parameter Definition
RTC Extended Exported Constants

Defines

#define | RTC_SHIFTADD1S_RESET 0x00000000U
#define | RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S

Define Documentation

#define RTC_SHIFTADD1S_RESET 0x00000000U

Definition at line 319 of file stm32f3xx_hal_rtc_ex.h.

#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S

Definition at line 320 of file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended WakeUp Timer

Defines
RTC Extended WakeUp Timer
RTC Extended Exported Macros

Defines

#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET) ? SET : RESET)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC WakeUpTimer's flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Wake Up timer's pending flags.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated Exti line flag.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.

Define Documentation

#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Wake Up timer's pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC WakeUpTimer Flag to clear. This parameter can be:
  • RTC_FLAG_WUTF
Return values:
None

Definition at line 411 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))

Disable the RTC WakeUp Timer peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 350 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 370 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer().

#define __HAL_RTC_WAKEUPTIMER_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))

Enable the RTC WakeUp Timer peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 343 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 360 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG ( ) (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Clear the RTC WakeUp Timer associated Exti line flag.

Return values:
None.

Definition at line 486 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT ( ) (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable event on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 437 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 449 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT ( ) (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 425 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 461 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE ( ) __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();

Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.

This parameter can be:

Return values:
None.

Definition at line 474 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT ( ) (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable event on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 431 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 443 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT ( ) (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 419 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 455 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE ( ) __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();

Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 467 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 492 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG ( ) (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.

Return values:
Line Status.

Definition at line 480 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC WakeUpTimer's flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC WakeUpTimer Flag is pending or not. This parameter can be:
  • RTC_FLAG_WUTF
  • RTC_FLAG_WUTWF
Return values:
None

Definition at line 401 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET) ? SET : RESET)

Check whether the specified RTC WakeUpTimer interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 380 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Wake Up timer interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 390 of file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Timestamp

Defines
RTC Extended Timestamp
RTC Extended Exported Macros

Defines

#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Time Stamp interrupt has been enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC TimeStamp's flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Time Stamp's pending flags.

Define Documentation

#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Time Stamp's pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Alarm Flag to clear. This parameter can be:
  • RTC_FLAG_TSF
Return values:
None

Definition at line 574 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_PollForTimeStampEvent(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TIMESTAMP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))

Disable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 513 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 533 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTimeStamp().

#define __HAL_RTC_TIMESTAMP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))

Enable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 506 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 523 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)

Get the selected RTC TimeStamp's flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC TimeStamp Flag is pending or not. This parameter can be:
  • RTC_FLAG_TSF
  • RTC_FLAG_TSOVF
Return values:
None

Definition at line 564 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTimeStampEvent(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TIMESTAMP_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)

Check whether the specified RTC TimeStamp interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC TimeStamp interrupt to check. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 543 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Time Stamp interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 553 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Tamper

Defines
RTC Extended Tamper
RTC Extended Exported Macros

Defines

#define | __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
Enable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
Disable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E))
Enable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))
Disable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP3E))
Enable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP3E))
Disable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR |= (__INTERRUPT__))
Enable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__))
Disable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
Check whether the specified RTC Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Tamper interrupt has been enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Tamper's pending flags.

Define Documentation

#define __HAL_RTC_TAMPER1_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))

Disable the RTC Tamper1 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 597 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER1_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))

Enable the RTC Tamper1 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 590 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER2_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))

Disable the RTC Tamper2 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 611 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER2_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E))

Enable the RTC Tamper2 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 604 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER3_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP3E))

Disable the RTC Tamper3 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 626 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER3_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP3E))

Enable the RTC Tamper3 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 619 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Tamper's pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Tamper Flag to clear. This parameter can be:
  • RTC_FLAG_TAMP1F
  • RTC_FLAG_TAMP2F
  • RTC_FLAG_TAMP3F (*)
Note:
(*) RTC_FLAG_TAMP3F not present on all the devices
Return values:
None

Definition at line 697 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__))

Disable the RTC Tamper interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RTC_IT_TAMP: Tamper interrupt
Return values:
None

Definition at line 647 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->TAFCR |= (__INTERRUPT__))

Enable the RTC Tamper interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RTC_IT_TAMP: Tamper interrupt
Return values:
None

Definition at line 637 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)

Get the selected RTC Tamper's flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Tamper Flag is pending or not. This parameter can be:
  • RTC_FLAG_TAMP1F
  • RTC_FLAG_TAMP2F
  • RTC_FLAG_TAMP3F (*)
Note:
(*) RTC_FLAG_TAMP3F not present on all the devices
Return values:
None

Definition at line 683 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)

Check whether the specified RTC Tamper interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Tamper interrupt to check. This parameter can be:
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt (*)
Note:
(*) RTC_IT_TAMP3 not present on all the devices
Return values:
None

Definition at line 660 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Tamper interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Tamper interrupt source to check. This parameter can be:
  • RTC_IT_TAMP: Tamper interrupt
Return values:
None

Definition at line 670 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: EXTI RTC Extended Tamper Timestamp EXTI

Defines
EXTI RTC Extended Tamper Timestamp EXTI
RTC Extended Exported Macros

Defines

#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Clear the RTC Tamper and Timestamp associated Exti line flag.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.

Define Documentation

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG ( ) (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Clear the RTC Tamper and Timestamp associated Exti line flag.

Return values:
None.

Definition at line 782 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT ( ) (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable event on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 733 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 745 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT ( ) (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 721 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 757 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE ( ) __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();

Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

This parameter can be:

Return values:
None.

Definition at line 770 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT ( ) (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable event on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 727 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 739 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT ( ) (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 715 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 751 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE ( ) __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();

Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 763 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 788 of file stm32f3xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG ( ) (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.

Return values:
Line Status.

Definition at line 776 of file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Calibration

Defines
RTC Extended Calibration
RTC Extended Exported Macros

Defines

#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC shift operation's flag status.

Define Documentation

#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))

Disable the calibration output.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 810 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateCalibrationOutPut().

#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))

Enable the RTC calibration output.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 803 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCalibrationOutPut().

#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))

Disable the clock reference detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 824 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateRefClock().

#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))

Enable the clock reference detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 817 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetRefClock().

#define __HAL_RTC_SHIFT_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)

Get the selected RTC shift operation's flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC shift operation Flag is pending or not. This parameter can be:
  • RTC_FLAG_SHPF
Return values:
None

Definition at line 834 of file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Extended RTC TimeStamp and Tamper functions

Functions
Extended RTC TimeStamp and Tamper functions
RTCEx Exported Functions

RTC TimeStamp and Tamper functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 3 Polling.

Detailed Description

RTC TimeStamp and Tamper functions.

 ===============================================================================
                 ##### RTC TimeStamp and Tamper functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure TimeStamp feature

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Tamper
 | ) |  |

Deactivate Tamper.

Parameters:
hrtc | RTC handle
Tamper | Selected tamper pin. This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3 (*)
Note:
(*) RTC_TAMPER_3 not present on all the devices
Return values:
HAL status

Definition at line 453 of file stm32f3xx_hal_rtc_ex.c.

References assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivate TimeStamp.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 253 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_DISABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_IT_TS, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTimeStamp,
 |  | RTC_DateTypeDef * | sTimeStampDate,
 |  | uint32_t | Format
 | ) |  |

Get the RTC TimeStamp value.

Parameters:
hrtc | RTC handle
sTimeStamp | Pointer to Time structure
sTimeStampDate | Pointer to Date structure
Format specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 296 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_CLEAR_FLAG, assert_param, RTC_DateTypeDef::Date, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FLAG_TSF, RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, RTC_TimeTypeDef::TimeFormat, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Tamper 1 Polling.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 652 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP1F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Tamper 2 Polling.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 684 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP2F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Tamper 3 Polling.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 717 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP3F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle TimeStamp polling request.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 613 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TSF, RTC_FLAG_TSOVF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Set Tamper.

Note:
By calling this API we disable the tamper interrupt for all tampers.
Parameters:
hrtc | RTC handle
sTamper | Pointer to Tamper Structure.
Return values:
HAL status

Definition at line 347 of file stm32f3xx_hal_rtc_ex.c.

References assert_param, RTC_TamperTypeDef::Filter, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::PrechargeDuration, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, RTC_HandleTypeDef::State, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Set Tamper with interrupt.

Note:
By calling this API we force the tamper interrupt for all tampers.
Parameters:
hrtc | RTC handle
sTamper | Pointer to RTC Tamper.
Return values:
HAL status

Definition at line 395 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE, assert_param, RTC_TamperTypeDef::Filter, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::PrechargeDuration, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, RTC_HandleTypeDef::State, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Set TimeStamp.

Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
hrtc RTC handle
TimeStampEdge Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
Return values:
HAL status

Definition at line 149 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Set TimeStamp with Interrupt.

Parameters:
hrtc RTC handle
Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
TimeStampEdge Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin Specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
Return values:
HAL status

Definition at line 203 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE, __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_TIMESTAMP_ENABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, RTC_IT_TS, and RTC_HandleTypeDef::State.

void HAL_RTCEx_Tamper1EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 1 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 565 of file stm32f3xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_Tamper2EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 2 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 580 of file stm32f3xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_Tamper3EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 3 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 596 of file stm32f3xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_TamperTimeStampIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle TimeStamp interrupt request.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 478 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, __HAL_RTC_TAMPER_GET_IT_SOURCE, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_GET_FLAG, __HAL_RTC_TIMESTAMP_GET_IT_SOURCE, HAL_RTC_STATE_READY, HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), HAL_RTCEx_TimeStampEventCallback(), RTC_FLAG_TAMP1F, RTC_FLAG_TAMP2F, RTC_FLAG_TAMP3F, RTC_FLAG_TSF, RTC_IT_TAMP, RTC_IT_TS, and RTC_HandleTypeDef::State.

void HAL_RTCEx_TimeStampEventCallback ( RTC_HandleTypeDef * hrtc )

TimeStamp callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 550 of file stm32f3xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Extended RTC Wake-up functions

Functions
Extended RTC Wake-up functions
RTCEx Exported Functions

RTC Wake-up functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
uint32_t | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.

Detailed Description

RTC Wake-up functions.

 ===============================================================================
                        ##### RTC Wake-up functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Wake-up feature

Function Documentation

uint32_t HAL_RTCEx_DeactivateWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Deactivate wake up timer counter.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 957 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_DISABLE_IT, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

uint32_t HAL_RTCEx_GetWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Get wake up timer counter.

Parameters:
hrtc RTC handle
Return values:
Counter value

Definition at line 1009 of file stm32f3xx_hal_rtc_ex.c.

References RTC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Wake Up Timer Polling.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1060 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_WUTF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Set wake up timer.

Parameters:
hrtc | RTC handle
WakeUpCounter | Wake up counter
WakeUpClock | Wake up clock
Return values:
HAL status

Definition at line 769 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_FLAG_WUTWF, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Set wake up timer with interrupt.

Parameters:
hrtc | RTC handle
WakeUpCounter | Wake up counter
WakeUpClock | Wake up clock
Return values:
HAL status

Definition at line 858 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_FLAG_WUTF, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

void HAL_RTCEx_WakeUpTimerEventCallback ( RTC_HandleTypeDef * hrtc )

Wake Up Timer callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1044 of file stm32f3xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_WakeUpTimerIRQHandler().

void HAL_RTCEx_WakeUpTimerIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle Wake Up Timer interrupt request.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1020 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_FLAG, HAL_RTC_STATE_READY, HAL_RTCEx_WakeUpTimerEventCallback(), RTC_FLAG_WUTF, and RTC_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
RTCEx Exported Functions

Extended Peripheral Control functions. More...

Functions

void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
              ##### Extended Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Write a data in a specified RTC Backup data register
      (+) Read a data in a specified RTC Backup data register
      (+) Set the Coarse calibration parameters.
      (+) Deactivate the Coarse calibration parameters
      (+) Set the Smooth calibration parameters.
      (+) Configure the Synchronization Shift Control Settings.
      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Enable the RTC reference clock detection.
      (+) Disable the RTC reference clock detection.
      (+) Enable the Bypass Shadow feature.
      (+) Disable the Bypass Shadow feature.

Function Documentation

uint32_t HAL_RTCEx_BKUPRead | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister
 | ) |  |

Reads data from the specified RTC Backup data Register.

Parameters:
hrtc | RTC handle
BackupRegister | RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Return values:
Read value

Definition at line 1148 of file stm32f3xx_hal_rtc_ex.c.

References assert_param, RTC_HandleTypeDef::Instance, and IS_RTC_BKP.

void HAL_RTCEx_BKUPWrite | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister,
 |  | uint32_t | Data
 | ) |  |

Write a data in a specified RTC Backup data register.

Parameters:
hrtc | RTC handle
BackupRegister | RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Data | Data to be written in the specified RTC Backup data register.
Return values:
None

Definition at line 1126 of file stm32f3xx_hal_rtc_ex.c.

References assert_param, RTC_HandleTypeDef::Instance, and IS_RTC_BKP.

HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut ( RTC_HandleTypeDef * hrtc )

Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1380 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock ( RTC_HandleTypeDef * hrtc )

Disable the RTC reference clock detection.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1458 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow ( RTC_HandleTypeDef * hrtc )

Disable the Bypass Shadow feature.

Parameters:
hrtc RTC handle
Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Return values:
HAL status

Definition at line 1541 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow ( RTC_HandleTypeDef * hrtc )

Enable the Bypass Shadow feature.

Parameters:
hrtc RTC handle
Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Return values:
HAL status

Definition at line 1509 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | CalibOutput
 | ) |  |

Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc RTC handle
CalibOutput Select the Calibration output Selection . This parameter can be one of the following values:
  • RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
  • RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
Return values:
HAL status

Definition at line 1342 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_CALIB_OUTPUT, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetRefClock ( RTC_HandleTypeDef * hrtc )

Enable the RTC reference clock detection.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1409 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | SmoothCalibPeriod,
 |  | uint32_t | SmoothCalibPlusPulses,
 |  | uint32_t | SmoothCalibMinusPulsesValue
 | ) |  |

Set the Smooth calibration parameters.

Parameters:
hrtc | RTC handle
SmoothCalibPeriod Select the Smooth Calibration Period. This parameter can be can be one of the following values :
  • RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
  • RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
  • RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
SmoothCalibPlusPulses Select to Set or reset the CALP bit. This parameter can be one of the following values:
  • RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
SmoothCalibMinusPulsesValue | Select the value of CALM[8:0] bits. This parameter can be one any value from 0 to 0x000001FF.
Note:
To deactivate the smooth calibration, the field SmoothCalibPlusPulses must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field SmoothCalibMinusPulsesValue mut be equal to 0.
Return values:
HAL status

Definition at line 1181 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_SMOOTH_CALIB_MINUS, IS_RTC_SMOOTH_CALIB_PERIOD, IS_RTC_SMOOTH_CALIB_PLUS, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | ShiftAdd1S,
 |  | uint32_t | ShiftSubFS
 | ) |  |

Configure the Synchronization Shift Control Settings.

Note:
When REFCKON is set, firmware must not write to Shift control register.
Parameters:
hrtc | RTC handle
ShiftAdd1S,: Select to add or not 1 second to the time calendar. This parameter can be one of the following values :
  • RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
  • RTC_SHIFTADD1S_RESET: No effect.
ShiftSubFS | Select the number of Second Fractions to substitute. This parameter can be one any value from 0 to 0x7FFF.
Return values:
HAL status

Definition at line 1249 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, IS_RTC_SHIFT_ADD1S, IS_RTC_SHIFT_SUBFS, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Extended features functions

Functions
Extended features functions
RTCEx Exported Functions

Extended features functions. More...

Functions

__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmB Polling request.

Detailed Description

Extended features functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) RTC Alram B callback
      (+) RTC Poll for Alarm B request

Function Documentation

void HAL_RTCEx_AlarmBEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm B callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1590 of file stm32f3xx_hal_rtc_ex.c.

Referenced by HAL_RTC_AlarmIRQHandler().

HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles AlarmB Polling request.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1606 of file stm32f3xx_hal_rtc_ex.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRBF, and RTC_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Private macros to check input parameters

Defines
Private macros to check input parameters
RTCEx Private Macros

Defines

#define | IS_RTC_OUTPUT(OUTPUT)
#define | IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
#define | IS_TIMESTAMP_EDGE(EDGE)
#define | IS_RTC_TAMPER(TAMPER) ((((TAMPER) & 0xFFFFFFD6U) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
#define | IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
#define | IS_RTC_TAMPER_TRIGGER(TRIGGER)
#define | IS_RTC_TAMPER_FILTER(FILTER)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(FREQ)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_TAMPER_PULLUP_STATE(STATE)
#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFFU)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU)
#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU)
#define | IS_RTC_CALIB_OUTPUT(OUTPUT)

Define Documentation

#define IS_RTC_BKP ( BKP ) ((BKP) < (uint32_t) RTC_BKP_NUMBER)

Definition at line 942 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_BKUPRead(), and HAL_RTCEx_BKUPWrite().

#define IS_RTC_CALIB_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))

Definition at line 998 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCalibrationOutPut().

#define IS_RTC_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_OUTPUT_DISABLE) || \
                               ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
                               ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
                               ((OUTPUT) == RTC_OUTPUT_WAKEUP))

Definition at line 937 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_SHIFT_ADD1S ( SEL )
Value:
(((SEL) == RTC_SHIFTADD1S_RESET) || \
                                 ((SEL) == RTC_SHIFTADD1S_SET))

Definition at line 995 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

#define IS_RTC_SHIFT_SUBFS ( FS ) ((FS) <= 0x00007FFFU)

Definition at line 997 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

#define IS_RTC_SMOOTH_CALIB_MINUS ( VALUE ) ((VALUE) <= 0x000001FFU)

Definition at line 994 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_SMOOTH_CALIB_PERIOD ( PERIOD )
Value:
(((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))

Definition at line 987 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_SMOOTH_CALIB_PLUS ( PLUS )
Value:
(((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))

Definition at line 990 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_TAMPER ( TAMPER ) ((((TAMPER) & 0xFFFFFFD6U) == 0x00U) && ((TAMPER) != (uint32_t)RESET))

Definition at line 947 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_FILTER ( FILTER )
Value:
(((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
                                       ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
                                       ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
                                       ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))

Definition at line 957 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PRECHARGE_DURATION ( DURATION )
Value:
(((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))

Definition at line 969 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PULLUP_STATE ( STATE )
Value:
(((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
                                           ((STATE) == RTC_TAMPER_PULLUP_DISABLE))

Definition at line 975 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_SAMPLING_FREQ ( FREQ )
Value:
(((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))

Definition at line 961 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION ( DETECTION )
Value:
(((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
                                                              ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))

Definition at line 973 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
                                        ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
                                        ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
                                        ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))

Definition at line 953 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TIMESTAMP_PIN ( PIN ) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))

Definition at line 950 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define IS_RTC_WAKEUP_CLOCK ( CLOCK )
Value:
(((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)   || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))

Definition at line 977 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_RTC_WAKEUP_COUNTER ( COUNTER ) ((COUNTER) <= 0xFFFFU)

Definition at line 984 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_TIMESTAMP_EDGE ( EDGE )
Value:
(((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))

Definition at line 944 of file stm32f3xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC Private Define

Defines
SDADC Private Define
SDADC

Defines

#define | SDADC_TIMEOUT 200
#define | SDADC_CONFREG_OFFSET 0x00000020
#define | SDADC_JDATAR_CH_OFFSET 24
#define | SDADC_MSB_MASK 0xFFFF0000U
#define | SDADC_LSB_MASK 0x0000FFFFU

Define Documentation

#define SDADC_CONFREG_OFFSET 0x00000020

Definition at line 209 of file stm32f3xx_hal_sdadc.c.

Referenced by HAL_SDADC_PrepareChannelConfig().

#define SDADC_JDATAR_CH_OFFSET 24

Definition at line 210 of file stm32f3xx_hal_sdadc.c.

Referenced by HAL_SDADC_InjectedGetValue().

#define SDADC_LSB_MASK 0x0000FFFFU

Definition at line 212 of file stm32f3xx_hal_sdadc.c.

Referenced by HAL_SDADC_InjectedConfigChannel(), and SDADC_GetInjChannelsNbr().

#define SDADC_MSB_MASK 0xFFFF0000U

Definition at line 211 of file stm32f3xx_hal_sdadc.c.

Referenced by HAL_SDADC_ConfigChannel().

#define SDADC_TIMEOUT 200

Definition at line 208 of file stm32f3xx_hal_sdadc.c.

Referenced by SDADC_EnterInitMode(), SDADC_InjConvStop(), and SDADC_RegConvStop().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC Private Functions

Functions
SDADC Private Functions
SDADC | SDADC Exported Functions

Functions

static HAL_StatusTypeDef | SDADC_EnterInitMode (SDADC_HandleTypeDef *hsdadc)
This function allows to enter in init mode for SDADC instance.
static void | SDADC_ExitInitMode (SDADC_HandleTypeDef *hsdadc)
This function allows to exit from init mode for SDADC instance.
static uint32_t | SDADC_GetInjChannelsNbr (uint32_t Channels)
This function allows to get the number of injected channels.
static HAL_StatusTypeDef | SDADC_RegConvStart (SDADC_HandleTypeDef *hsdadc)
This function allows to really start regular conversion.
static HAL_StatusTypeDef | SDADC_RegConvStop (SDADC_HandleTypeDef *hsdadc)
This function allows to really stop regular conversion.
static HAL_StatusTypeDef | SDADC_InjConvStart (SDADC_HandleTypeDef *hsdadc)
This function allows to really start injected conversion.
static HAL_StatusTypeDef | SDADC_InjConvStop (SDADC_HandleTypeDef *hsdadc)
This function allows to really stop injected conversion.

Function Documentation

static HAL_StatusTypeDef SDADC_EnterInitMode ( SDADC_HandleTypeDef * hsdadc ) [static]

This function allows to enter in init mode for SDADC instance.

Parameters:
hsdadc SDADC handle.
Return values:
HAL status.

Definition at line 2373 of file stm32f3xx_hal_sdadc.c.

References HAL_GetTick(), SDADC_HandleTypeDef::Instance, and SDADC_TIMEOUT.

Referenced by HAL_SDADC_AssociateChannelConfig(), HAL_SDADC_CalibrationStart(), HAL_SDADC_CalibrationStart_IT(), HAL_SDADC_PrepareChannelConfig(), HAL_SDADC_SelectInjectedDelay(), HAL_SDADC_SelectInjectedExtTrigger(), SDADC_InjConvStart(), SDADC_InjConvStop(), SDADC_RegConvStart(), and SDADC_RegConvStop().

static void SDADC_ExitInitMode ( SDADC_HandleTypeDef * hsdadc ) [static]

This function allows to exit from init mode for SDADC instance.

Parameters:
hsdadc SDADC handle.
Return values:
None.

Definition at line 2399 of file stm32f3xx_hal_sdadc.c.

References SDADC_HandleTypeDef::Instance.

Referenced by HAL_SDADC_AssociateChannelConfig(), HAL_SDADC_CalibrationStart(), HAL_SDADC_CalibrationStart_IT(), HAL_SDADC_PrepareChannelConfig(), HAL_SDADC_SelectInjectedDelay(), HAL_SDADC_SelectInjectedExtTrigger(), SDADC_InjConvStart(), SDADC_InjConvStop(), SDADC_RegConvStart(), and SDADC_RegConvStop().

static uint32_t SDADC_GetInjChannelsNbr ( uint32_t Channels ) [static]

This function allows to get the number of injected channels.

Parameters:
Channels bitfield of injected channels.
Return values:
Number of injected channels.

Definition at line 2410 of file stm32f3xx_hal_sdadc.c.

References SDADC_LSB_MASK.

Referenced by HAL_SDADC_InjectedConfigChannel().

static HAL_StatusTypeDef SDADC_InjConvStart ( SDADC_HandleTypeDef * hsdadc ) [static]

This function allows to really start injected conversion.

Parameters:
hsdadc SDADC handle.
Return values:
HAL status.

Definition at line 2547 of file stm32f3xx_hal_sdadc.c.

References SDADC_HandleTypeDef::ExtTriggerEdge, HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_INJ, HAL_SDADC_STATE_READY, HAL_SDADC_STATE_REG_INJ, SDADC_HandleTypeDef::InjConvRemaining, SDADC_HandleTypeDef::InjectedChannelsNbr, SDADC_HandleTypeDef::InjectedTrigger, SDADC_HandleTypeDef::Instance, SDADC_EnterInitMode(), SDADC_ExitInitMode(), SDADC_SOFTWARE_TRIGGER, SDADC_SYNCHRONOUS_TRIGGER, and SDADC_HandleTypeDef::State.

Referenced by HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedStart(), HAL_SDADC_InjectedStart_DMA(), and HAL_SDADC_InjectedStart_IT().

static HAL_StatusTypeDef SDADC_InjConvStop ( SDADC_HandleTypeDef * hsdadc ) [static]

This function allows to really stop injected conversion.

Parameters:
hsdadc SDADC handle.
Return values:
HAL status.

Definition at line 2600 of file stm32f3xx_hal_sdadc.c.

References HAL_GetTick(), HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_INJ, HAL_SDADC_STATE_READY, HAL_SDADC_STATE_REG, SDADC_HandleTypeDef::InjectedContMode, SDADC_HandleTypeDef::InjectedTrigger, SDADC_HandleTypeDef::Instance, SDADC_CONTINUOUS_CONV_ON, SDADC_EnterInitMode(), SDADC_ExitInitMode(), SDADC_SOFTWARE_TRIGGER, SDADC_SYNCHRONOUS_TRIGGER, SDADC_TIMEOUT, and SDADC_HandleTypeDef::State.

Referenced by HAL_SDADC_InjectedMultiModeStop_DMA(), HAL_SDADC_InjectedStop(), HAL_SDADC_InjectedStop_DMA(), and HAL_SDADC_InjectedStop_IT().

static HAL_StatusTypeDef SDADC_RegConvStart ( SDADC_HandleTypeDef * hsdadc ) [static]

This function allows to really start regular conversion.

Parameters:
hsdadc SDADC handle.
Return values:
HAL status.

Definition at line 2433 of file stm32f3xx_hal_sdadc.c.

References HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_READY, HAL_SDADC_STATE_REG, HAL_SDADC_STATE_REG_INJ, SDADC_HandleTypeDef::Instance, SDADC_HandleTypeDef::RegularTrigger, SDADC_EnterInitMode(), SDADC_ExitInitMode(), SDADC_SOFTWARE_TRIGGER, and SDADC_HandleTypeDef::State.

Referenced by HAL_SDADC_MultiModeStart_DMA(), HAL_SDADC_Start(), HAL_SDADC_Start_DMA(), and HAL_SDADC_Start_IT().

static HAL_StatusTypeDef SDADC_RegConvStop ( SDADC_HandleTypeDef * hsdadc ) [static]

This function allows to really stop regular conversion.

Parameters:
hsdadc SDADC handle.
Return values:
HAL status.

Definition at line 2476 of file stm32f3xx_hal_sdadc.c.

References HAL_GetTick(), HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_INJ, HAL_SDADC_STATE_READY, HAL_SDADC_STATE_REG, SDADC_HandleTypeDef::Instance, SDADC_HandleTypeDef::RegularContMode, SDADC_HandleTypeDef::RegularTrigger, SDADC_CONTINUOUS_CONV_ON, SDADC_EnterInitMode(), SDADC_ExitInitMode(), SDADC_SYNCHRONOUS_TRIGGER, SDADC_TIMEOUT, and SDADC_HandleTypeDef::State.

Referenced by HAL_SDADC_MultiModeStop_DMA(), HAL_SDADC_Stop(), HAL_SDADC_Stop_DMA(), and HAL_SDADC_Stop_IT().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SDADC Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_SDADC_Init (SDADC_HandleTypeDef *hsdadc)
Initializes the SDADC according to the specified parameters in the SDADC_InitTypeDef structure.
HAL_StatusTypeDef | HAL_SDADC_DeInit (SDADC_HandleTypeDef *hsdadc)
De-initializes the SDADC.
__weak void | HAL_SDADC_MspInit (SDADC_HandleTypeDef *hsdadc)
Initializes the SDADC MSP.
__weak void | HAL_SDADC_MspDeInit (SDADC_HandleTypeDef *hsdadc)
De-initializes the SDADC MSP.

Detailed Description

Initialization and de-initialization functions.

  ===============================================================================
              ##### Initialization and de-initialization functions #####
  ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the SDADC.
      (+) De-initialize the SDADC.

Function Documentation

HAL_StatusTypeDef HAL_SDADC_DeInit ( SDADC_HandleTypeDef * hsdadc )

De-initializes the SDADC.

Parameters:
hsdadc SDADC handle.
Return values:
HAL status.

Definition at line 341 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_MspDeInit(), HAL_SDADC_STATE_RESET, SDADC_HandleTypeDef::Instance, and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_Init ( SDADC_HandleTypeDef * hsdadc )

Initializes the SDADC according to the specified parameters in the SDADC_InitTypeDef structure.

Note:
If multiple SDADC are used, please configure first SDADC1 to set the common reference voltage.
Parameters:
hsdadc SDADC handle.
Return values:
HAL status.

Definition at line 269 of file stm32f3xx_hal_sdadc.c.

References assert_param, SDADC_HandleTypeDef::ErrorCode, SDADC_HandleTypeDef::ExtTriggerEdge, SDADC_InitTypeDef::FastConversionMode, HAL_Delay(), HAL_SDADC_MspInit(), HAL_SDADC_STATE_READY, SDADC_InitTypeDef::IdleLowPowerMode, SDADC_HandleTypeDef::Init, SDADC_HandleTypeDef::InjConvRemaining, SDADC_HandleTypeDef::InjectedChannelsNbr, SDADC_HandleTypeDef::InjectedContMode, SDADC_HandleTypeDef::InjectedMultimode, SDADC_HandleTypeDef::InjectedTrigger, SDADC_HandleTypeDef::Instance, IS_SDADC_FAST_CONV_MODE, IS_SDADC_LOWPOWER_MODE, IS_SDADC_SLOW_CLOCK_MODE, IS_SDADC_VREF, SDADC_InitTypeDef::ReferenceVoltage, SDADC_HandleTypeDef::RegularContMode, SDADC_HandleTypeDef::RegularMultimode, SDADC_HandleTypeDef::RegularTrigger, SDADC_CONTINUOUS_CONV_OFF, SDADC_ERROR_NONE, SDADC_EXT_TRIG_RISING_EDGE, SDADC_MULTIMODE_SDADC1_SDADC2, SDADC_SOFTWARE_TRIGGER, SDADC_InitTypeDef::SlowClockMode, and SDADC_HandleTypeDef::State.

void HAL_SDADC_MspDeInit ( SDADC_HandleTypeDef * hsdadc )

De-initializes the SDADC MSP.

Parameters:
hsdadc SDADC handle
Return values:
None

Definition at line 395 of file stm32f3xx_hal_sdadc.c.

Referenced by HAL_SDADC_DeInit().

void HAL_SDADC_MspInit ( SDADC_HandleTypeDef * hsdadc )

Initializes the SDADC MSP.

Parameters:
hsdadc SDADC handle
Return values:
None

Definition at line 380 of file stm32f3xx_hal_sdadc.c.

Referenced by HAL_SDADC_Init().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: peripheral control functions

Functions
peripheral control functions
SDADC Exported Functions

Peripheral control functions. More...

Functions

HAL_StatusTypeDef | HAL_SDADC_PrepareChannelConfig (SDADC_HandleTypeDef *hsdadc, uint32_t ConfIndex, SDADC_ConfParamTypeDef *ConfParamStruct)
This function allows the user to set parameters for a configuration.
HAL_StatusTypeDef | HAL_SDADC_AssociateChannelConfig (SDADC_HandleTypeDef *hsdadc, uint32_t Channel, uint32_t ConfIndex)
This function allows the user to associate a channel with one of the available configurations.
HAL_StatusTypeDef | HAL_SDADC_ConfigChannel (SDADC_HandleTypeDef *hsdadc, uint32_t Channel, uint32_t ContinuousMode)
This function allows to select channel for regular conversion and to enable/disable continuous mode for regular conversion.
HAL_StatusTypeDef | HAL_SDADC_InjectedConfigChannel (SDADC_HandleTypeDef *hsdadc, uint32_t Channel, uint32_t ContinuousMode)
This function allows to select channels for injected conversion and to enable/disable continuous mode for injected conversion.
HAL_StatusTypeDef | HAL_SDADC_SelectRegularTrigger (SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
This function allows to select trigger for regular conversions.
HAL_StatusTypeDef | HAL_SDADC_SelectInjectedTrigger (SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
This function allows to select trigger for injected conversions.
HAL_StatusTypeDef | HAL_SDADC_SelectInjectedExtTrigger (SDADC_HandleTypeDef *hsdadc, uint32_t InjectedExtTrigger, uint32_t ExtTriggerEdge)
This function allows to select and configure injected external trigger.
HAL_StatusTypeDef | HAL_SDADC_SelectInjectedDelay (SDADC_HandleTypeDef *hsdadc, uint32_t InjectedDelay)
This function allows to enable/disable delay addition for injected conversions.
HAL_StatusTypeDef | HAL_SDADC_MultiModeConfigChannel (SDADC_HandleTypeDef *hsdadc, uint32_t MultimodeType)
This function allows to configure multimode for regular conversions.
HAL_StatusTypeDef | HAL_SDADC_InjectedMultiModeConfigChannel (SDADC_HandleTypeDef *hsdadc, uint32_t MultimodeType)
This function allows to configure multimode for injected conversions.

Detailed Description

Peripheral control functions.

  ===============================================================================
              ##### Peripheral control functions #####
  ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Program one of the three different configurations for channels.
      (+) Associate channel to one of configurations.
      (+) Select regular and injected channels.
      (+) Enable/disable continuous mode for regular and injected conversions.
      (+) Select regular and injected triggers.
      (+) Select and configure injected external trigger.
      (+) Enable/disable delay addition for injected conversions.
      (+) Configure multimode.

Function Documentation

HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t | Channel,
 |  | uint32_t | ConfIndex
 | ) |  |

This function allows the user to associate a channel with one of the available configurations.

Note:
This function should be called only when SDADC instance is in idle state (neither calibration nor regular or injected conversion ongoing)
Parameters:
hsdadc | SDADC handle.
Channel | Channel to associate with configuration. This parameter can be a value of SDADC Channel Selection.
ConfIndex | Index of configuration to associate with channel. This parameter can be a value of SDADC Configuration Index.
Return values:
HAL status

Definition at line 501 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_READY, SDADC_HandleTypeDef::Instance, IS_SDADC_CONF_INDEX, IS_SDADC_REGULAR_CHANNEL, SDADC_CHANNEL_8, SDADC_EnterInitMode(), SDADC_ExitInitMode(), and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_ConfigChannel | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t | Channel,
 |  | uint32_t | ContinuousMode
 | ) |  |

This function allows to select channel for regular conversion and to enable/disable continuous mode for regular conversion.

Parameters:
hsdadc | SDADC handle.
Channel | Channel for regular conversion. This parameter can be a value of SDADC Channel Selection.
ContinuousMode | Enable/disable continuous mode for regular conversion. This parameter can be a value of SDADC Continuous Mode.
Return values:
HAL status

Definition at line 561 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_RESET, SDADC_HandleTypeDef::Instance, IS_SDADC_CONTINUOUS_MODE, IS_SDADC_REGULAR_CHANNEL, SDADC_HandleTypeDef::RegularContMode, SDADC_CONTINUOUS_CONV_ON, SDADC_MSB_MASK, and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t | Channel,
 |  | uint32_t | ContinuousMode
 | ) |  |

This function allows to select channels for injected conversion and to enable/disable continuous mode for injected conversion.

Parameters:
hsdadc | SDADC handle.
Channel | Channels for injected conversion. This parameter can be a values combination of SDADC Channel Selection.
ContinuousMode | Enable/disable continuous mode for injected conversion. This parameter can be a value of SDADC Continuous Mode.
Return values:
HAL status

Definition at line 606 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_RESET, SDADC_HandleTypeDef::InjectedChannelsNbr, SDADC_HandleTypeDef::InjectedContMode, SDADC_HandleTypeDef::Instance, IS_SDADC_CONTINUOUS_MODE, IS_SDADC_INJECTED_CHANNEL, SDADC_CONTINUOUS_CONV_ON, SDADC_GetInjChannelsNbr(), SDADC_LSB_MASK, and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t | MultimodeType
 | ) |  |

This function allows to configure multimode for injected conversions.

Note:
This function should not be called if injected conversion is ongoing and should be could only for SDADC1.
Parameters:
hsdadc | SDADC handle.
MultimodeType | Type of multimode for injected conversions. This parameter can be a value of SDADC Multimode Type.
Return values:
HAL status

Definition at line 870 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_CALIB, HAL_SDADC_STATE_READY, HAL_SDADC_STATE_REG, SDADC_HandleTypeDef::InjectedMultimode, SDADC_HandleTypeDef::Instance, IS_SDADC_MULTIMODE_TYPE, and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t | MultimodeType
 | ) |  |

This function allows to configure multimode for regular conversions.

Note:
This function should not be called if regular conversion is ongoing and should be could only for SDADC1.
Parameters:
hsdadc | SDADC handle.
MultimodeType | Type of multimode for regular conversions. This parameter can be a value of SDADC Multimode Type.
Return values:
HAL status

Definition at line 831 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_CALIB, HAL_SDADC_STATE_INJ, HAL_SDADC_STATE_READY, SDADC_HandleTypeDef::Instance, IS_SDADC_MULTIMODE_TYPE, SDADC_HandleTypeDef::RegularMultimode, and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t | ConfIndex,
 |  | SDADC_ConfParamTypeDef * | ConfParamStruct
 | ) |  |

This function allows the user to set parameters for a configuration.

Parameters are input mode, common mode, gain and offset.

Note:
This function should be called only when SDADC instance is in idle state (neither calibration nor regular or injected conversion ongoing)
Parameters:
hsdadc | SDADC handle.
ConfIndex | Index of configuration to modify. This parameter can be a value of SDADC Configuration Index.
ConfParamStruct | Parameters to apply for this configuration.
Return values:
HAL status

Definition at line 441 of file stm32f3xx_hal_sdadc.c.

References assert_param, SDADC_ConfParamTypeDef::CommonMode, SDADC_ConfParamTypeDef::Gain, HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_READY, SDADC_ConfParamTypeDef::InputMode, SDADC_HandleTypeDef::Instance, IS_SDADC_COMMON_MODE, IS_SDADC_CONF_INDEX, IS_SDADC_GAIN, IS_SDADC_INPUT_MODE, IS_SDADC_OFFSET_VALUE, SDADC_ConfParamTypeDef::Offset, SDADC_CONFREG_OFFSET, SDADC_EnterInitMode(), SDADC_ExitInitMode(), and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_SelectInjectedDelay | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t | InjectedDelay
 | ) |  |

This function allows to enable/disable delay addition for injected conversions.

Note:
This function should be called only when SDADC instance is in idle state (neither calibration nor regular or injected conversion ongoing)
Parameters:
hsdadc | SDADC handle.
InjectedDelay | Enable/disable delay for injected conversions. This parameter can be a value of SDADC Injected Conversion Delay.
Return values:
HAL status

Definition at line 785 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_READY, SDADC_HandleTypeDef::Instance, IS_SDADC_INJECTED_DELAY, SDADC_EnterInitMode(), SDADC_ExitInitMode(), and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_SelectInjectedExtTrigger | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t | InjectedExtTrigger,
 |  | uint32_t | ExtTriggerEdge
 | ) |  |

This function allows to select and configure injected external trigger.

Note:
This function should be called only when SDADC instance is in idle state (neither calibration nor regular or injected conversion ongoing)
Parameters:
hsdadc | SDADC handle.
InjectedExtTrigger | External trigger for injected conversions. This parameter can be a value of SDADC Injected External Trigger.
ExtTriggerEdge | Edge of external injected trigger. This parameter can be a value of SDADC External Trigger Edge.
Return values:
HAL status

Definition at line 734 of file stm32f3xx_hal_sdadc.c.

References assert_param, SDADC_HandleTypeDef::ExtTriggerEdge, HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_READY, SDADC_HandleTypeDef::Instance, IS_SDADC_EXT_INJEC_TRIG, IS_SDADC_EXT_TRIG_EDGE, SDADC_EnterInitMode(), SDADC_ExitInitMode(), and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t | Trigger
 | ) |  |

This function allows to select trigger for injected conversions.

Note:
This function should not be called if injected conversion is ongoing.
Parameters:
hsdadc SDADC handle.
Trigger Trigger for injected conversions. This parameter can be one of the following value :
  • SDADC_SOFTWARE_TRIGGER : Software trigger.
  • SDADC_SYNCHRONOUS_TRIGGER : Synchronous with SDADC1 (only for SDADC2 and SDADC3).
  • SDADC_EXTERNAL_TRIGGER : External trigger.
Return values:
HAL status

Definition at line 694 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_CALIB, HAL_SDADC_STATE_READY, HAL_SDADC_STATE_REG, SDADC_HandleTypeDef::InjectedTrigger, SDADC_HandleTypeDef::Instance, IS_SDADC_INJECTED_TRIGGER, SDADC_SYNCHRONOUS_TRIGGER, and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t | Trigger
 | ) |  |

This function allows to select trigger for regular conversions.

Note:
This function should not be called if regular conversion is ongoing.
Parameters:
hsdadc SDADC handle.
Trigger Trigger for regular conversions. This parameter can be one of the following value :
  • SDADC_SOFTWARE_TRIGGER : Software trigger.
  • SDADC_SYNCHRONOUS_TRIGGER : Synchronous with SDADC1 (only for SDADC2 and SDADC3).
Return values:
HAL status

Definition at line 654 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_CALIB, HAL_SDADC_STATE_INJ, HAL_SDADC_STATE_READY, SDADC_HandleTypeDef::Instance, IS_SDADC_REGULAR_TRIGGER, SDADC_HandleTypeDef::RegularTrigger, SDADC_SYNCHRONOUS_TRIGGER, and SDADC_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
SDADC Exported Functions

IO operation Control functions. More...

Functions

HAL_StatusTypeDef | HAL_SDADC_CalibrationStart (SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence)
This function allows to start calibration in polling mode.
HAL_StatusTypeDef | HAL_SDADC_PollForCalibEvent (SDADC_HandleTypeDef *hsdadc, uint32_t Timeout)
This function allows to poll for the end of calibration.
HAL_StatusTypeDef | HAL_SDADC_CalibrationStart_IT (SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence)
This function allows to start calibration in interrupt mode.
HAL_StatusTypeDef | HAL_SDADC_Start (SDADC_HandleTypeDef *hsdadc)
This function allows to start regular conversion in polling mode.
HAL_StatusTypeDef | HAL_SDADC_PollForConversion (SDADC_HandleTypeDef *hsdadc, uint32_t Timeout)
This function allows to poll for the end of regular conversion.
HAL_StatusTypeDef | HAL_SDADC_Stop (SDADC_HandleTypeDef *hsdadc)
This function allows to stop regular conversion in polling mode.
HAL_StatusTypeDef | HAL_SDADC_Start_IT (SDADC_HandleTypeDef *hsdadc)
This function allows to start regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_SDADC_Stop_IT (SDADC_HandleTypeDef *hsdadc)
This function allows to stop regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_SDADC_Start_DMA (SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode.
HAL_StatusTypeDef | HAL_SDADC_Stop_DMA (SDADC_HandleTypeDef *hsdadc)
This function allows to stop regular conversion in DMA mode.
uint32_t | HAL_SDADC_GetValue (SDADC_HandleTypeDef *hsdadc)
This function allows to get regular conversion value.
HAL_StatusTypeDef | HAL_SDADC_InjectedStart (SDADC_HandleTypeDef *hsdadc)
This function allows to start injected conversion in polling mode.
HAL_StatusTypeDef | HAL_SDADC_PollForInjectedConversion (SDADC_HandleTypeDef *hsdadc, uint32_t Timeout)
This function allows to poll for the end of injected conversion.
HAL_StatusTypeDef | HAL_SDADC_InjectedStop (SDADC_HandleTypeDef *hsdadc)
This function allows to stop injected conversion in polling mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedStart_IT (SDADC_HandleTypeDef *hsdadc)
This function allows to start injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedStop_IT (SDADC_HandleTypeDef *hsdadc)
This function allows to stop injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedStart_DMA (SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedStop_DMA (SDADC_HandleTypeDef *hsdadc)
This function allows to stop injected conversion in DMA mode.
uint32_t | HAL_SDADC_InjectedGetValue (SDADC_HandleTypeDef *hsdadc, uint32_t *Channel)
This function allows to get injected conversion value.
HAL_StatusTypeDef | HAL_SDADC_MultiModeStart_DMA (SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length)
This function allows to start multimode regular conversions in DMA mode.
HAL_StatusTypeDef | HAL_SDADC_MultiModeStop_DMA (SDADC_HandleTypeDef *hsdadc)
This function allows to stop multimode regular conversions in DMA mode.
uint32_t | HAL_SDADC_MultiModeGetValue (SDADC_HandleTypeDef *hsdadc)
This function allows to get multimode regular conversion value.
HAL_StatusTypeDef | HAL_SDADC_InjectedMultiModeStart_DMA (SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length)
This function allows to start multimode injected conversions in DMA mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedMultiModeStop_DMA (SDADC_HandleTypeDef *hsdadc)
This function allows to stop multimode injected conversions in DMA mode.
uint32_t | HAL_SDADC_InjectedMultiModeGetValue (SDADC_HandleTypeDef *hsdadc)
This function allows to get multimode injected conversion value.
void | HAL_SDADC_IRQHandler (SDADC_HandleTypeDef *hsdadc)
This function handles the SDADC interrupts.
__weak void | HAL_SDADC_CalibrationCpltCallback (SDADC_HandleTypeDef *hsdadc)
Calibration complete callback.
__weak void | HAL_SDADC_ConvHalfCpltCallback (SDADC_HandleTypeDef *hsdadc)
Half regular conversion complete callback.
__weak void | HAL_SDADC_ConvCpltCallback (SDADC_HandleTypeDef *hsdadc)
Regular conversion complete callback.
__weak void | HAL_SDADC_InjectedConvHalfCpltCallback (SDADC_HandleTypeDef *hsdadc)
Half injected conversion complete callback.
__weak void | HAL_SDADC_InjectedConvCpltCallback (SDADC_HandleTypeDef *hsdadc)
Injected conversion complete callback.
__weak void | HAL_SDADC_ErrorCallback (SDADC_HandleTypeDef *hsdadc)
Error callback.
static void | SDADC_DMARegularHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback for regular conversion.
static void | SDADC_DMARegularConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback for regular conversion.
static void | SDADC_DMAInjectedHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback for injected conversion.
static void | SDADC_DMAInjectedConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback for injected conversion.
static void | SDADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

IO operation Control functions.

  ===============================================================================
              ##### IO operation functions #####
  ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start calibration.
      (+) Poll for the end of calibration.
      (+) Start calibration and enable interrupt.
      (+) Start conversion of regular/injected channel.
      (+) Poll for the end of regular/injected conversion.
      (+) Stop conversion of regular/injected channel.
      (+) Start conversion of regular/injected channel and enable interrupt.
      (+) Stop conversion of regular/injected channel and disable interrupt.
      (+) Start conversion of regular/injected channel and enable DMA transfer.
      (+) Stop conversion of regular/injected channel and disable DMA transfer.
      (+) Start multimode and enable DMA transfer for regular/injected conversion.
      (+) Stop multimode and disable DMA transfer for regular/injected conversion..
      (+) Get result of regular channel conversion.
      (+) Get result of injected channel conversion.
      (+) Get result of multimode conversion.
      (+) Handle SDADC interrupt request.
      (+) Callbacks for calibration and regular/injected conversions.

Function Documentation

void HAL_SDADC_CalibrationCpltCallback ( SDADC_HandleTypeDef * hsdadc )

Calibration complete callback.

Parameters:
hsdadc SDADC handle.
Return values:
None

Definition at line 2159 of file stm32f3xx_hal_sdadc.c.

Referenced by HAL_SDADC_IRQHandler().

HAL_StatusTypeDef HAL_SDADC_CalibrationStart | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t | CalibrationSequence
 | ) |  |

This function allows to start calibration in polling mode.

Note:
This function should be called only when SDADC instance is in idle state (neither calibration nor regular or injected conversion ongoing).
Parameters:
hsdadc | SDADC handle.
CalibrationSequence | Calibration sequence. This parameter can be a value of SDADC Calibration Sequence.
Return values:
HAL status

Definition at line 943 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_CALIB, HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_READY, SDADC_HandleTypeDef::Instance, IS_SDADC_CALIB_SEQUENCE, SDADC_EnterInitMode(), SDADC_ExitInitMode(), and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t | CalibrationSequence
 | ) |  |

This function allows to start calibration in interrupt mode.

Note:
This function should be called only when SDADC instance is in idle state (neither calibration nor regular or injected conversion ongoing).
Parameters:
hsdadc | SDADC handle.
CalibrationSequence | Calibration sequence. This parameter can be a value of SDADC Calibration Sequence.
Return values:
HAL status

Definition at line 1044 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_CALIB, HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_READY, SDADC_HandleTypeDef::Instance, IS_SDADC_CALIB_SEQUENCE, SDADC_EnterInitMode(), SDADC_ExitInitMode(), and SDADC_HandleTypeDef::State.

void HAL_SDADC_ConvCpltCallback ( SDADC_HandleTypeDef * hsdadc )

Regular conversion complete callback.

Note:
In interrupt mode, user has to read conversion value in this function using HAL_SDADC_GetValue or HAL_SDADC_MultiModeGetValue.
Parameters:
hsdadc SDADC handle.
Return values:
None

Definition at line 2191 of file stm32f3xx_hal_sdadc.c.

Referenced by HAL_SDADC_IRQHandler(), and SDADC_DMARegularConvCplt().

void HAL_SDADC_ConvHalfCpltCallback ( SDADC_HandleTypeDef * hsdadc )

Half regular conversion complete callback.

Parameters:
hsdadc SDADC handle.
Return values:
None

Definition at line 2174 of file stm32f3xx_hal_sdadc.c.

Referenced by SDADC_DMARegularHalfConvCplt().

void HAL_SDADC_ErrorCallback ( SDADC_HandleTypeDef * hsdadc )

Error callback.

Parameters:
hsdadc SDADC handle.
Return values:
None

Definition at line 2238 of file stm32f3xx_hal_sdadc.c.

Referenced by HAL_SDADC_IRQHandler(), HAL_SDADC_PollForConversion(), HAL_SDADC_PollForInjectedConversion(), and SDADC_DMAError().

uint32_t HAL_SDADC_GetValue ( SDADC_HandleTypeDef * hsdadc )

This function allows to get regular conversion value.

Parameters:
hsdadc SDADC handle.
Return values:
Regular conversion value

Definition at line 1395 of file stm32f3xx_hal_sdadc.c.

References assert_param, and SDADC_HandleTypeDef::Instance.

void HAL_SDADC_InjectedConvCpltCallback ( SDADC_HandleTypeDef * hsdadc )

Injected conversion complete callback.

Note:
In interrupt mode, user has to read conversion value in this function using HAL_SDADC_InjectedGetValue or HAL_SDADC_InjectedMultiModeGetValue.
Parameters:
hsdadc SDADC handle.
Return values:
None

Definition at line 2223 of file stm32f3xx_hal_sdadc.c.

Referenced by HAL_SDADC_IRQHandler(), and SDADC_DMAInjectedConvCplt().

void HAL_SDADC_InjectedConvHalfCpltCallback ( SDADC_HandleTypeDef * hsdadc )

Half injected conversion complete callback.

Parameters:
hsdadc SDADC handle.
Return values:
None

Definition at line 2206 of file stm32f3xx_hal_sdadc.c.

Referenced by SDADC_DMAInjectedHalfConvCplt().

uint32_t HAL_SDADC_InjectedGetValue | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t * | Channel
 | ) |  |

This function allows to get injected conversion value.

Parameters:
hsdadc | SDADC handle.
Channel | Corresponding channel of injected conversion.
Return values:
Injected conversion value

Definition at line 1721 of file stm32f3xx_hal_sdadc.c.

References assert_param, SDADC_HandleTypeDef::Instance, and SDADC_JDATAR_CH_OFFSET.

uint32_t HAL_SDADC_InjectedMultiModeGetValue ( SDADC_HandleTypeDef * hsdadc )

This function allows to get multimode injected conversion value.

Parameters:
hsdadc SDADC handle.
Return values:
Multimode injected conversion value

Definition at line 2034 of file stm32f3xx_hal_sdadc.c.

References assert_param, SDADC_HandleTypeDef::InjectedMultimode, SDADC_HandleTypeDef::Instance, and SDADC_MULTIMODE_SDADC1_SDADC2.

HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

This function allows to start multimode injected conversions in DMA mode.

Note:
This function should be called only when SDADC instance is in idle state or if regular conversion is ongoing.
Parameters:
hsdadc | SDADC handle.
pData | The destination buffer address.
Length | The length of data to be transferred from SDADC peripheral to memory.
Return values:
HAL status

Definition at line 1903 of file stm32f3xx_hal_sdadc.c.

References assert_param, DMA_CIRCULAR, DMA_NORMAL, HAL_DMA_Start_IT(), HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_READY, HAL_SDADC_STATE_REG, SDADC_HandleTypeDef::hdma, __DMA_HandleTypeDef::Init, SDADC_HandleTypeDef::InjectedChannelsNbr, SDADC_HandleTypeDef::InjectedContMode, SDADC_HandleTypeDef::InjectedMultimode, SDADC_HandleTypeDef::InjectedTrigger, SDADC_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, SDADC_CONTINUOUS_CONV_OFF, SDADC_DMAError(), SDADC_DMAInjectedConvCplt(), SDADC_DMAInjectedHalfConvCplt(), SDADC_InjConvStart(), SDADC_MULTIMODE_SDADC1_SDADC2, SDADC_SOFTWARE_TRIGGER, SDADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA ( SDADC_HandleTypeDef * hsdadc )

This function allows to stop multimode injected conversions in DMA mode.

Note:
This function should be called only if injected conversion is ongoing.
Parameters:
hsdadc SDADC handle.
Return values:
HAL status

Definition at line 1988 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_DMA_Abort(), HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_INJ, HAL_SDADC_STATE_REG_INJ, SDADC_HandleTypeDef::hdma, SDADC_HandleTypeDef::Instance, SDADC_InjConvStop(), and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_InjectedStart ( SDADC_HandleTypeDef * hsdadc )

This function allows to start injected conversion in polling mode.

Note:
This function should be called only when SDADC instance is in idle state or if regular conversion is ongoing.
Parameters:
hsdadc SDADC handle.
Return values:
HAL status

Definition at line 1411 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_READY, HAL_SDADC_STATE_REG, SDADC_HandleTypeDef::Instance, SDADC_InjConvStart(), and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

This function allows to start injected conversion in DMA mode.

Note:
This function should be called only when SDADC instance is in idle state or if regular conversion is ongoing.
Parameters:
hsdadc | SDADC handle.
pData | The destination buffer address.
Length | The length of data to be transferred from SDADC peripheral to memory.
Return values:
HAL status

Definition at line 1607 of file stm32f3xx_hal_sdadc.c.

References assert_param, DMA_CIRCULAR, DMA_NORMAL, HAL_DMA_Start_IT(), HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_READY, HAL_SDADC_STATE_REG, SDADC_HandleTypeDef::hdma, __DMA_HandleTypeDef::Init, SDADC_HandleTypeDef::InjectedChannelsNbr, SDADC_HandleTypeDef::InjectedContMode, SDADC_HandleTypeDef::InjectedTrigger, SDADC_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, SDADC_CONTINUOUS_CONV_OFF, SDADC_DMAError(), SDADC_DMAInjectedConvCplt(), SDADC_DMAInjectedHalfConvCplt(), SDADC_InjConvStart(), SDADC_SOFTWARE_TRIGGER, SDADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT ( SDADC_HandleTypeDef * hsdadc )

This function allows to start injected conversion in interrupt mode.

Note:
This function should be called only when SDADC instance is in idle state or if regular conversion is ongoing.
Parameters:
hsdadc SDADC handle.
Return values:
HAL status

Definition at line 1541 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_READY, HAL_SDADC_STATE_REG, SDADC_HandleTypeDef::Instance, SDADC_InjConvStart(), and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_InjectedStop ( SDADC_HandleTypeDef * hsdadc )

This function allows to stop injected conversion in polling mode.

Note:
This function should be called only if injected conversion is ongoing.
Parameters:
hsdadc SDADC handle.
Return values:
HAL status

Definition at line 1511 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_INJ, HAL_SDADC_STATE_REG_INJ, SDADC_HandleTypeDef::Instance, SDADC_InjConvStop(), and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA ( SDADC_HandleTypeDef * hsdadc )

This function allows to stop injected conversion in DMA mode.

Note:
This function should be called only if injected conversion is ongoing.
Parameters:
hsdadc SDADC handle.
Return values:
HAL status

Definition at line 1679 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_DMA_Abort(), HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_INJ, HAL_SDADC_STATE_REG_INJ, SDADC_HandleTypeDef::hdma, SDADC_HandleTypeDef::Instance, SDADC_InjConvStop(), and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT ( SDADC_HandleTypeDef * hsdadc )

This function allows to stop injected conversion in interrupt mode.

Note:
This function should be called only if injected conversion is ongoing.
Parameters:
hsdadc SDADC handle.
Return values:
HAL status

Definition at line 1572 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_INJ, HAL_SDADC_STATE_REG_INJ, SDADC_HandleTypeDef::Instance, SDADC_InjConvStop(), and SDADC_HandleTypeDef::State.

void HAL_SDADC_IRQHandler ( SDADC_HandleTypeDef * hsdadc )

This function handles the SDADC interrupts.

Parameters:
hsdadc SDADC handle.
Return values:
None

Definition at line 2055 of file stm32f3xx_hal_sdadc.c.

References SDADC_HandleTypeDef::ErrorCode, HAL_SDADC_CalibrationCpltCallback(), HAL_SDADC_ConvCpltCallback(), HAL_SDADC_ErrorCallback(), HAL_SDADC_InjectedConvCpltCallback(), HAL_SDADC_STATE_INJ, HAL_SDADC_STATE_READY, HAL_SDADC_STATE_REG, SDADC_HandleTypeDef::InjConvRemaining, SDADC_HandleTypeDef::InjectedChannelsNbr, SDADC_HandleTypeDef::InjectedContMode, SDADC_HandleTypeDef::InjectedTrigger, SDADC_HandleTypeDef::Instance, SDADC_HandleTypeDef::RegularContMode, SDADC_HandleTypeDef::RegularTrigger, SDADC_CONTINUOUS_CONV_OFF, SDADC_ERROR_INJECTED_OVERRUN, SDADC_ERROR_REGULAR_OVERRUN, SDADC_SOFTWARE_TRIGGER, and SDADC_HandleTypeDef::State.

uint32_t HAL_SDADC_MultiModeGetValue ( SDADC_HandleTypeDef * hsdadc )

This function allows to get multimode regular conversion value.

Parameters:
hsdadc SDADC handle.
Return values:
Multimode regular conversion value

Definition at line 1878 of file stm32f3xx_hal_sdadc.c.

References assert_param, SDADC_HandleTypeDef::Instance, SDADC_HandleTypeDef::RegularMultimode, and SDADC_MULTIMODE_SDADC1_SDADC2.

HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

This function allows to start multimode regular conversions in DMA mode.

Note:
This function should be called only when SDADC instance is in idle state or if injected conversion is ongoing.
Parameters:
hsdadc | SDADC handle.
pData | The destination buffer address.
Length | The length of data to be transferred from SDADC peripheral to memory.
Return values:
HAL status

Definition at line 1747 of file stm32f3xx_hal_sdadc.c.

References assert_param, DMA_CIRCULAR, DMA_NORMAL, HAL_DMA_Start_IT(), HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_INJ, HAL_SDADC_STATE_READY, SDADC_HandleTypeDef::hdma, __DMA_HandleTypeDef::Init, SDADC_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, SDADC_HandleTypeDef::RegularContMode, SDADC_HandleTypeDef::RegularMultimode, SDADC_HandleTypeDef::RegularTrigger, SDADC_CONTINUOUS_CONV_OFF, SDADC_DMAError(), SDADC_DMARegularConvCplt(), SDADC_DMARegularHalfConvCplt(), SDADC_MULTIMODE_SDADC1_SDADC2, SDADC_RegConvStart(), SDADC_SOFTWARE_TRIGGER, SDADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA ( SDADC_HandleTypeDef * hsdadc )

This function allows to stop multimode regular conversions in DMA mode.

Note:
This function should be called only if regular conversion is ongoing.
Parameters:
hsdadc SDADC handle.
Return values:
HAL status

Definition at line 1832 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_DMA_Abort(), HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_REG, HAL_SDADC_STATE_REG_INJ, SDADC_HandleTypeDef::hdma, SDADC_HandleTypeDef::Instance, SDADC_RegConvStop(), and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t | Timeout
 | ) |  |

This function allows to poll for the end of calibration.

Note:
This function should be called only if calibration is ongoing.
Parameters:
hsdadc | SDADC handle.
Timeout | Timeout value in milliseconds.
Return values:
HAL status

Definition at line 993 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_GetTick(), HAL_SDADC_STATE_CALIB, HAL_SDADC_STATE_READY, SDADC_HandleTypeDef::Instance, and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_PollForConversion | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t | Timeout
 | ) |  |

This function allows to poll for the end of regular conversion.

Note:
This function should be called only if regular conversion is ongoing.
Parameters:
hsdadc | SDADC handle.
Timeout | Timeout value in milliseconds.
Return values:
HAL status

Definition at line 1126 of file stm32f3xx_hal_sdadc.c.

References assert_param, SDADC_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SDADC_ErrorCallback(), HAL_SDADC_STATE_INJ, HAL_SDADC_STATE_READY, HAL_SDADC_STATE_REG, HAL_SDADC_STATE_REG_INJ, SDADC_HandleTypeDef::Instance, SDADC_HandleTypeDef::RegularContMode, SDADC_HandleTypeDef::RegularTrigger, SDADC_CONTINUOUS_CONV_OFF, SDADC_ERROR_REGULAR_OVERRUN, SDADC_SOFTWARE_TRIGGER, and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t | Timeout
 | ) |  |

This function allows to poll for the end of injected conversion.

Note:
This function should be called only if injected conversion is ongoing.
Parameters:
hsdadc | SDADC handle.
Timeout | Timeout value in milliseconds.
Return values:
HAL status

Definition at line 1440 of file stm32f3xx_hal_sdadc.c.

References assert_param, SDADC_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SDADC_ErrorCallback(), HAL_SDADC_STATE_INJ, HAL_SDADC_STATE_READY, HAL_SDADC_STATE_REG, HAL_SDADC_STATE_REG_INJ, SDADC_HandleTypeDef::InjConvRemaining, SDADC_HandleTypeDef::InjectedChannelsNbr, SDADC_HandleTypeDef::InjectedContMode, SDADC_HandleTypeDef::InjectedTrigger, SDADC_HandleTypeDef::Instance, SDADC_CONTINUOUS_CONV_OFF, SDADC_ERROR_INJECTED_OVERRUN, SDADC_SOFTWARE_TRIGGER, and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_Start ( SDADC_HandleTypeDef * hsdadc )

This function allows to start regular conversion in polling mode.

Note:
This function should be called only when SDADC instance is in idle state or if injected conversion is ongoing.
Parameters:
hsdadc SDADC handle.
Return values:
HAL status

Definition at line 1097 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_INJ, HAL_SDADC_STATE_READY, SDADC_HandleTypeDef::Instance, SDADC_RegConvStart(), and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_Start_DMA | ( | SDADC_HandleTypeDef * | hsdadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

This function allows to start regular conversion in DMA mode.

Note:
This function should be called only when SDADC instance is in idle state or if injected conversion is ongoing.
Parameters:
hsdadc | SDADC handle.
pData | The destination buffer address.
Length | The length of data to be transferred from SDADC peripheral to memory.
Return values:
HAL status

Definition at line 1282 of file stm32f3xx_hal_sdadc.c.

References assert_param, DMA_CIRCULAR, DMA_NORMAL, HAL_DMA_Start_IT(), HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_INJ, HAL_SDADC_STATE_READY, SDADC_HandleTypeDef::hdma, __DMA_HandleTypeDef::Init, SDADC_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, SDADC_HandleTypeDef::RegularContMode, SDADC_HandleTypeDef::RegularTrigger, SDADC_CONTINUOUS_CONV_OFF, SDADC_DMAError(), SDADC_DMARegularConvCplt(), SDADC_DMARegularHalfConvCplt(), SDADC_RegConvStart(), SDADC_SOFTWARE_TRIGGER, SDADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SDADC_Start_IT ( SDADC_HandleTypeDef * hsdadc )

This function allows to start regular conversion in interrupt mode.

Note:
This function should be called only when SDADC instance is in idle state or if injected conversion is ongoing.
Parameters:
hsdadc SDADC handle.
Return values:
HAL status

Definition at line 1216 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_INJ, HAL_SDADC_STATE_READY, SDADC_HandleTypeDef::Instance, SDADC_RegConvStart(), and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_Stop ( SDADC_HandleTypeDef * hsdadc )

This function allows to stop regular conversion in polling mode.

Note:
This function should be called only if regular conversion is ongoing.
Parameters:
hsdadc SDADC handle.
Return values:
HAL status

Definition at line 1186 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_REG, HAL_SDADC_STATE_REG_INJ, SDADC_HandleTypeDef::Instance, SDADC_RegConvStop(), and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_Stop_DMA ( SDADC_HandleTypeDef * hsdadc )

This function allows to stop regular conversion in DMA mode.

Note:
This function should be called only if regular conversion is ongoing.
Parameters:
hsdadc SDADC handle.
Return values:
HAL status

Definition at line 1354 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_DMA_Abort(), HAL_SDADC_STATE_ERROR, HAL_SDADC_STATE_REG, HAL_SDADC_STATE_REG_INJ, SDADC_HandleTypeDef::hdma, SDADC_HandleTypeDef::Instance, SDADC_RegConvStop(), and SDADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDADC_Stop_IT ( SDADC_HandleTypeDef * hsdadc )

This function allows to stop regular conversion in interrupt mode.

Note:
This function should be called only if regular conversion is ongoing.
Parameters:
hsdadc SDADC handle.
Return values:
HAL status

Definition at line 1247 of file stm32f3xx_hal_sdadc.c.

References assert_param, HAL_SDADC_STATE_REG, HAL_SDADC_STATE_REG_INJ, SDADC_HandleTypeDef::Instance, SDADC_RegConvStop(), and SDADC_HandleTypeDef::State.

static void SDADC_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2309 of file stm32f3xx_hal_sdadc.c.

References SDADC_HandleTypeDef::ErrorCode, HAL_SDADC_ErrorCallback(), and SDADC_ERROR_DMA.

Referenced by HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_MultiModeStart_DMA(), and HAL_SDADC_Start_DMA().

static void SDADC_DMAInjectedConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA transfer complete callback for injected conversion.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2295 of file stm32f3xx_hal_sdadc.c.

References HAL_SDADC_InjectedConvCpltCallback().

Referenced by HAL_SDADC_InjectedMultiModeStart_DMA(), and HAL_SDADC_InjectedStart_DMA().

static void SDADC_DMAInjectedHalfConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback for injected conversion.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2281 of file stm32f3xx_hal_sdadc.c.

References HAL_SDADC_InjectedConvHalfCpltCallback().

Referenced by HAL_SDADC_InjectedMultiModeStart_DMA(), and HAL_SDADC_InjectedStart_DMA().

static void SDADC_DMARegularConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA transfer complete callback for regular conversion.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2267 of file stm32f3xx_hal_sdadc.c.

References HAL_SDADC_ConvCpltCallback().

Referenced by HAL_SDADC_MultiModeStart_DMA(), and HAL_SDADC_Start_DMA().

static void SDADC_DMARegularHalfConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback for regular conversion.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2253 of file stm32f3xx_hal_sdadc.c.

References HAL_SDADC_ConvHalfCpltCallback().

Referenced by HAL_SDADC_MultiModeStart_DMA(), and HAL_SDADC_Start_DMA().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
SDADC Exported Functions

SDADC Peripheral State functions. More...

Functions

HAL_SDADC_StateTypeDef | HAL_SDADC_GetState (SDADC_HandleTypeDef *hsdadc)
This function allows to get the current SDADC state.
uint32_t | HAL_SDADC_GetError (SDADC_HandleTypeDef *hsdadc)
This function allows to get the current SDADC error code.

Detailed Description

SDADC Peripheral State functions.

  ===============================================================================
             ##### ADC Peripheral State functions #####
  ===============================================================================
    [..] This subsection provides functions allowing to
      (+) Get the SDADC state
      (+) Get the SDADC Error

Function Documentation

uint32_t HAL_SDADC_GetError ( SDADC_HandleTypeDef * hsdadc )

This function allows to get the current SDADC error code.

Parameters:
hsdadc SDADC handle.
Return values:
SDADC error code.

Definition at line 2355 of file stm32f3xx_hal_sdadc.c.

References SDADC_HandleTypeDef::ErrorCode.

HAL_SDADC_StateTypeDef HAL_SDADC_GetState ( SDADC_HandleTypeDef * hsdadc )

This function allows to get the current SDADC state.

Parameters:
hsdadc SDADC handle.
Return values:
SDADC state.

Definition at line 2345 of file stm32f3xx_hal_sdadc.c.

References SDADC_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC Exported Types

Data Structures | Enumerations
SDADC Exported Types
SDADC

Data Structures

struct | SDADC_InitTypeDef
SDADC Init Structure definition. More...
struct | SDADC_HandleTypeDef
SDADC handle Structure definition. More...
struct | SDADC_ConfParamTypeDef
SDADC Configuration Register Parameter Structure. More...

Enumerations

enum HAL_SDADC_StateTypeDef {
HAL_SDADC_STATE_RESET = 0x00U, HAL_SDADC_STATE_READY = 0x01U, HAL_SDADC_STATE_CALIB = 0x02U, HAL_SDADC_STATE_REG = 0x03U,
HAL_SDADC_STATE_INJ = 0x04U, HAL_SDADC_STATE_REG_INJ = 0x05U, HAL_SDADC_STATE_ERROR = 0xFFU
}
HAL SDADC States definition. More...

Enumeration Type Documentation

enum HAL_SDADC_StateTypeDef

HAL SDADC States definition.

Enumerator:
HAL_SDADC_STATE_RESET

SDADC not initialized

HAL_SDADC_STATE_READY

SDADC initialized and ready for use

HAL_SDADC_STATE_CALIB

SDADC calibration in progress

HAL_SDADC_STATE_REG

SDADC regular conversion in progress

HAL_SDADC_STATE_INJ

SDADC injected conversion in progress

HAL_SDADC_STATE_REG_INJ

SDADC regular and injected conversions in progress

HAL_SDADC_STATE_ERROR

SDADC state error

Definition at line 67 of file stm32f3xx_hal_sdadc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SDADC_InitTypeDef Struct Reference
SDADC Exported Types

SDADC Init Structure definition. More...

#include <stm32f3xx_hal_sdadc.h>

Data Fields

uint32_t | IdleLowPowerMode
uint32_t | FastConversionMode
uint32_t | SlowClockMode
uint32_t | ReferenceVoltage

Detailed Description

SDADC Init Structure definition.

Definition at line 81 of file stm32f3xx_hal_sdadc.h.

Field Documentation

uint32_t SDADC_InitTypeDef::FastConversionMode

Specifies if Fast conversion mode is enabled or not. This parameter can be a value of SDADC Fast Conversion Mode

Definition at line 85 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init().

uint32_t SDADC_InitTypeDef::IdleLowPowerMode

Specifies if SDADC can enter in power down or standby when idle. This parameter can be a value of SDADC Idle Low Power Mode

Definition at line 83 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init().

uint32_t SDADC_InitTypeDef::ReferenceVoltage

Specifies the reference voltage. Note: This parameter is common to all SDADC instances. This parameter can be a value of SDADC Reference Voltage

Definition at line 89 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init().

uint32_t SDADC_InitTypeDef::SlowClockMode

Specifies if slow clock mode is enabled or not. This parameter can be a value of SDADC Slow Clock Mode

Definition at line 87 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_sdadc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SDADC_HandleTypeDef Struct Reference
SDADC Exported Types

SDADC handle Structure definition. More...

#include <stm32f3xx_hal_sdadc.h>

Data Fields

SDADC_TypeDef * | Instance
SDADC_InitTypeDef Init
DMA_HandleTypeDef * hdma
uint32_t | RegularContMode
uint32_t | InjectedContMode
uint32_t | InjectedChannelsNbr
uint32_t | InjConvRemaining
uint32_t | RegularTrigger
uint32_t | InjectedTrigger
uint32_t | ExtTriggerEdge
uint32_t | RegularMultimode
uint32_t | InjectedMultimode
HAL_SDADC_StateTypeDef State
uint32_t | ErrorCode

Detailed Description

SDADC handle Structure definition.

Definition at line 97 of file stm32f3xx_hal_sdadc.h.

Field Documentation

uint32_t SDADC_HandleTypeDef::ErrorCode

SDADC Error code

Definition at line 112 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_GetError(), HAL_SDADC_Init(), HAL_SDADC_IRQHandler(), HAL_SDADC_PollForConversion(), HAL_SDADC_PollForInjectedConversion(), and SDADC_DMAError().

uint32_t SDADC_HandleTypeDef::ExtTriggerEdge

Rising, falling or both edges selected

Definition at line 108 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init(), HAL_SDADC_SelectInjectedExtTrigger(), and SDADC_InjConvStart().

DMA_HandleTypeDef* SDADC_HandleTypeDef::hdma

SDADC DMA Handle parameters

Definition at line 101 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedMultiModeStop_DMA(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_InjectedStop_DMA(), HAL_SDADC_MultiModeStart_DMA(), HAL_SDADC_MultiModeStop_DMA(), HAL_SDADC_Start_DMA(), and HAL_SDADC_Stop_DMA().

SDADC_InitTypeDef SDADC_HandleTypeDef::Init

SDADC init parameters

Definition at line 100 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init().

uint32_t SDADC_HandleTypeDef::InjConvRemaining

Injected conversion remaining

Definition at line 105 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init(), HAL_SDADC_IRQHandler(), HAL_SDADC_PollForInjectedConversion(), and SDADC_InjConvStart().

uint32_t SDADC_HandleTypeDef::InjectedChannelsNbr

Number of channels in injected sequence

Definition at line 104 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init(), HAL_SDADC_InjectedConfigChannel(), HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_IRQHandler(), HAL_SDADC_PollForInjectedConversion(), and SDADC_InjConvStart().

uint32_t SDADC_HandleTypeDef::InjectedContMode

Injected conversion continuous mode

Definition at line 103 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init(), HAL_SDADC_InjectedConfigChannel(), HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_IRQHandler(), HAL_SDADC_PollForInjectedConversion(), and SDADC_InjConvStop().

uint32_t SDADC_HandleTypeDef::InjectedMultimode

Current type of injected multimode

Definition at line 110 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init(), HAL_SDADC_InjectedMultiModeConfigChannel(), HAL_SDADC_InjectedMultiModeGetValue(), and HAL_SDADC_InjectedMultiModeStart_DMA().

uint32_t SDADC_HandleTypeDef::InjectedTrigger

Current trigger used for injected conversion

Definition at line 107 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init(), HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_IRQHandler(), HAL_SDADC_PollForInjectedConversion(), HAL_SDADC_SelectInjectedTrigger(), SDADC_InjConvStart(), and SDADC_InjConvStop().

SDADC_TypeDef* SDADC_HandleTypeDef::Instance

SDADC registers base address

Definition at line 99 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_AssociateChannelConfig(), HAL_SDADC_CalibrationStart(), HAL_SDADC_CalibrationStart_IT(), HAL_SDADC_ConfigChannel(), HAL_SDADC_DeInit(), HAL_SDADC_GetValue(), HAL_SDADC_Init(), HAL_SDADC_InjectedConfigChannel(), HAL_SDADC_InjectedGetValue(), HAL_SDADC_InjectedMultiModeConfigChannel(), HAL_SDADC_InjectedMultiModeGetValue(), HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedMultiModeStop_DMA(), HAL_SDADC_InjectedStart(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_InjectedStart_IT(), HAL_SDADC_InjectedStop(), HAL_SDADC_InjectedStop_DMA(), HAL_SDADC_InjectedStop_IT(), HAL_SDADC_IRQHandler(), HAL_SDADC_MultiModeConfigChannel(), HAL_SDADC_MultiModeGetValue(), HAL_SDADC_MultiModeStart_DMA(), HAL_SDADC_MultiModeStop_DMA(), HAL_SDADC_PollForCalibEvent(), HAL_SDADC_PollForConversion(), HAL_SDADC_PollForInjectedConversion(), HAL_SDADC_PrepareChannelConfig(), HAL_SDADC_SelectInjectedDelay(), HAL_SDADC_SelectInjectedExtTrigger(), HAL_SDADC_SelectInjectedTrigger(), HAL_SDADC_SelectRegularTrigger(), HAL_SDADC_Start(), HAL_SDADC_Start_DMA(), HAL_SDADC_Start_IT(), HAL_SDADC_Stop(), HAL_SDADC_Stop_DMA(), HAL_SDADC_Stop_IT(), SDADC_EnterInitMode(), SDADC_ExitInitMode(), SDADC_InjConvStart(), SDADC_InjConvStop(), SDADC_RegConvStart(), and SDADC_RegConvStop().

uint32_t SDADC_HandleTypeDef::RegularContMode

Regular conversion continuous mode

Definition at line 102 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_ConfigChannel(), HAL_SDADC_Init(), HAL_SDADC_IRQHandler(), HAL_SDADC_MultiModeStart_DMA(), HAL_SDADC_PollForConversion(), HAL_SDADC_Start_DMA(), and SDADC_RegConvStop().

uint32_t SDADC_HandleTypeDef::RegularMultimode

current type of regular multimode

Definition at line 109 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init(), HAL_SDADC_MultiModeConfigChannel(), HAL_SDADC_MultiModeGetValue(), and HAL_SDADC_MultiModeStart_DMA().

uint32_t SDADC_HandleTypeDef::RegularTrigger

Current trigger used for regular conversion

Definition at line 106 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init(), HAL_SDADC_IRQHandler(), HAL_SDADC_MultiModeStart_DMA(), HAL_SDADC_PollForConversion(), HAL_SDADC_SelectRegularTrigger(), HAL_SDADC_Start_DMA(), SDADC_RegConvStart(), and SDADC_RegConvStop().

HAL_SDADC_StateTypeDef SDADC_HandleTypeDef::State

SDADC state

Definition at line 111 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_AssociateChannelConfig(), HAL_SDADC_CalibrationStart(), HAL_SDADC_CalibrationStart_IT(), HAL_SDADC_ConfigChannel(), HAL_SDADC_DeInit(), HAL_SDADC_GetState(), HAL_SDADC_Init(), HAL_SDADC_InjectedConfigChannel(), HAL_SDADC_InjectedMultiModeConfigChannel(), HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedMultiModeStop_DMA(), HAL_SDADC_InjectedStart(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_InjectedStart_IT(), HAL_SDADC_InjectedStop(), HAL_SDADC_InjectedStop_DMA(), HAL_SDADC_InjectedStop_IT(), HAL_SDADC_IRQHandler(), HAL_SDADC_MultiModeConfigChannel(), HAL_SDADC_MultiModeStart_DMA(), HAL_SDADC_MultiModeStop_DMA(), HAL_SDADC_PollForCalibEvent(), HAL_SDADC_PollForConversion(), HAL_SDADC_PollForInjectedConversion(), HAL_SDADC_PrepareChannelConfig(), HAL_SDADC_SelectInjectedDelay(), HAL_SDADC_SelectInjectedExtTrigger(), HAL_SDADC_SelectInjectedTrigger(), HAL_SDADC_SelectRegularTrigger(), HAL_SDADC_Start(), HAL_SDADC_Start_DMA(), HAL_SDADC_Start_IT(), HAL_SDADC_Stop(), HAL_SDADC_Stop_DMA(), HAL_SDADC_Stop_IT(), SDADC_InjConvStart(), SDADC_InjConvStop(), SDADC_RegConvStart(), and SDADC_RegConvStop().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_sdadc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC_ConfParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SDADC_ConfParamTypeDef Struct Reference
SDADC Exported Types

SDADC Configuration Register Parameter Structure. More...

#include <stm32f3xx_hal_sdadc.h>

Data Fields

uint32_t | InputMode
uint32_t | Gain
uint32_t | CommonMode
uint32_t | Offset

Detailed Description

SDADC Configuration Register Parameter Structure.

Definition at line 118 of file stm32f3xx_hal_sdadc.h.

Field Documentation

uint32_t SDADC_ConfParamTypeDef::CommonMode

Specifies the common mode setting (VSSA, VDDA, VDDA/2U). This parameter can be any value of SDADC Common Mode

Definition at line 124 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_PrepareChannelConfig().

uint32_t SDADC_ConfParamTypeDef::Gain

Specifies the gain setting. This parameter can be any value of SDADC Gain

Definition at line 122 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_PrepareChannelConfig().

uint32_t SDADC_ConfParamTypeDef::InputMode

Specifies the input mode (single ended, differential...) This parameter can be any value of SDADC Input Mode

Definition at line 120 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_PrepareChannelConfig().

uint32_t SDADC_ConfParamTypeDef::Offset

Specifies the 12-bit offset value. This parameter can be any value lower or equal to 0x00000FFFU

Definition at line 126 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_PrepareChannelConfig().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_sdadc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC Idle Low Power Mode

Defines
SDADC Idle Low Power Mode
SDADC Exported Constants

Defines

#define | SDADC_LOWPOWER_NONE (0x00000000U)
#define | SDADC_LOWPOWER_POWERDOWN SDADC_CR1_PDI
#define | SDADC_LOWPOWER_STANDBY SDADC_CR1_SBI

Define Documentation

#define SDADC_LOWPOWER_NONE (0x00000000U)

Definition at line 143 of file stm32f3xx_hal_sdadc.h.

#define SDADC_LOWPOWER_POWERDOWN SDADC_CR1_PDI

Definition at line 144 of file stm32f3xx_hal_sdadc.h.

#define SDADC_LOWPOWER_STANDBY SDADC_CR1_SBI

Definition at line 145 of file stm32f3xx_hal_sdadc.h.

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STM32F373xC HAL User Manual: SDADC Fast Conversion Mode

Defines
SDADC Fast Conversion Mode
SDADC Exported Constants

Defines

#define | SDADC_FAST_CONV_DISABLE (0x00000000U)
#define | SDADC_FAST_CONV_ENABLE SDADC_CR2_FAST

Define Documentation

#define SDADC_FAST_CONV_DISABLE (0x00000000U)

Definition at line 153 of file stm32f3xx_hal_sdadc.h.

#define SDADC_FAST_CONV_ENABLE SDADC_CR2_FAST

Definition at line 154 of file stm32f3xx_hal_sdadc.h.

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STM32F373xC HAL User Manual: SDADC Slow Clock Mode

Defines
SDADC Slow Clock Mode
SDADC Exported Constants

Defines

#define | SDADC_SLOW_CLOCK_DISABLE (0x00000000U)
#define | SDADC_SLOW_CLOCK_ENABLE SDADC_CR1_SLOWCK

Define Documentation

#define SDADC_SLOW_CLOCK_DISABLE (0x00000000U)

Definition at line 162 of file stm32f3xx_hal_sdadc.h.

#define SDADC_SLOW_CLOCK_ENABLE SDADC_CR1_SLOWCK

Definition at line 163 of file stm32f3xx_hal_sdadc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC Reference Voltage

Defines
SDADC Reference Voltage
SDADC Exported Constants

Defines

#define | SDADC_VREF_EXT (0x00000000U)
#define | SDADC_VREF_VREFINT1 SDADC_CR1_REFV_0
#define | SDADC_VREF_VREFINT2 SDADC_CR1_REFV_1
#define | SDADC_VREF_VDDA SDADC_CR1_REFV

Define Documentation

#define SDADC_VREF_EXT (0x00000000U)

The reference voltage is forced externally using VREF pin

Definition at line 171 of file stm32f3xx_hal_sdadc.h.

#define SDADC_VREF_VDDA SDADC_CR1_REFV

The reference voltage is forced internally to VDDA

Definition at line 174 of file stm32f3xx_hal_sdadc.h.

#define SDADC_VREF_VREFINT1 SDADC_CR1_REFV_0

The reference voltage is forced internally to 1.22V VREFINT

Definition at line 172 of file stm32f3xx_hal_sdadc.h.

#define SDADC_VREF_VREFINT2 SDADC_CR1_REFV_1

The reference voltage is forced internally to 1.8V VREFINT

Definition at line 173 of file stm32f3xx_hal_sdadc.h.

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STM32F373xC HAL User Manual: SDADC Configuration Index

Defines
SDADC Configuration Index
SDADC Exported Constants

Defines

#define | SDADC_CONF_INDEX_0 (0x00000000U)
#define | SDADC_CONF_INDEX_1 (0x00000001U)
#define | SDADC_CONF_INDEX_2 (0x00000002U)

Define Documentation

#define SDADC_CONF_INDEX_0 (0x00000000U)

Configuration 0 Register selected

Definition at line 183 of file stm32f3xx_hal_sdadc.h.

#define SDADC_CONF_INDEX_1 (0x00000001U)

Configuration 1 Register selected

Definition at line 184 of file stm32f3xx_hal_sdadc.h.

#define SDADC_CONF_INDEX_2 (0x00000002U)

Configuration 2 Register selected

Definition at line 185 of file stm32f3xx_hal_sdadc.h.

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STM32F373xC HAL User Manual: SDADC Input Mode

Defines
SDADC Input Mode
SDADC Exported Constants

Defines

#define | SDADC_INPUT_MODE_DIFF (0x00000000U)
#define | SDADC_INPUT_MODE_SE_OFFSET SDADC_CONF0R_SE0_0
#define | SDADC_INPUT_MODE_SE_ZERO_REFERENCE SDADC_CONF0R_SE0

Define Documentation

#define SDADC_INPUT_MODE_DIFF (0x00000000U)

Conversions are executed in differential mode

Definition at line 193 of file stm32f3xx_hal_sdadc.h.

#define SDADC_INPUT_MODE_SE_OFFSET SDADC_CONF0R_SE0_0

Conversions are executed in single ended offset mode

Definition at line 194 of file stm32f3xx_hal_sdadc.h.

#define SDADC_INPUT_MODE_SE_ZERO_REFERENCE SDADC_CONF0R_SE0

Conversions are executed in single ended zero-volt reference mode

Definition at line 195 of file stm32f3xx_hal_sdadc.h.

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STM32F373xC HAL User Manual: SDADC Gain

Defines
SDADC Gain
SDADC Exported Constants

Defines

#define | SDADC_GAIN_1 (0x00000000U)
#define | SDADC_GAIN_2 SDADC_CONF0R_GAIN0_0
#define | SDADC_GAIN_4 SDADC_CONF0R_GAIN0_1
#define | SDADC_GAIN_8 (0x00300000U)
#define | SDADC_GAIN_16 SDADC_CONF0R_GAIN0_2
#define | SDADC_GAIN_32 (0x00500000U)
#define | SDADC_GAIN_1_2 SDADC_CONF0R_GAIN0

Define Documentation

#define SDADC_GAIN_1 (0x00000000U)

Gain equal to 1U

Definition at line 203 of file stm32f3xx_hal_sdadc.h.

#define SDADC_GAIN_16 SDADC_CONF0R_GAIN0_2

Gain equal to 16U

Definition at line 207 of file stm32f3xx_hal_sdadc.h.

#define SDADC_GAIN_1_2 SDADC_CONF0R_GAIN0

Gain equal to 1U/2U

Definition at line 209 of file stm32f3xx_hal_sdadc.h.

#define SDADC_GAIN_2 SDADC_CONF0R_GAIN0_0

Gain equal to 2U

Definition at line 204 of file stm32f3xx_hal_sdadc.h.

#define SDADC_GAIN_32 (0x00500000U)

Gain equal to 32U

Definition at line 208 of file stm32f3xx_hal_sdadc.h.

#define SDADC_GAIN_4 SDADC_CONF0R_GAIN0_1

Gain equal to 4U

Definition at line 205 of file stm32f3xx_hal_sdadc.h.

#define SDADC_GAIN_8 (0x00300000U)

Gain equal to 8U

Definition at line 206 of file stm32f3xx_hal_sdadc.h.

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STM32F373xC HAL User Manual: SDADC Common Mode

Defines
SDADC Common Mode
SDADC Exported Constants

Defines

#define | SDADC_COMMON_MODE_VSSA (0x00000000U)
#define | SDADC_COMMON_MODE_VDDA_2 SDADC_CONF0R_COMMON0_0
#define | SDADC_COMMON_MODE_VDDA SDADC_CONF0R_COMMON0_1

Define Documentation

#define SDADC_COMMON_MODE_VDDA SDADC_CONF0R_COMMON0_1

Select SDADC VDDA as common mode

Definition at line 219 of file stm32f3xx_hal_sdadc.h.

#define SDADC_COMMON_MODE_VDDA_2 SDADC_CONF0R_COMMON0_0

Select SDADC VDDA/2 as common mode

Definition at line 218 of file stm32f3xx_hal_sdadc.h.

#define SDADC_COMMON_MODE_VSSA (0x00000000U)

Select SDADC VSSA as common mode

Definition at line 217 of file stm32f3xx_hal_sdadc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC Channel Selection

Defines
SDADC Channel Selection
SDADC Exported Constants

Defines

#define | SDADC_CHANNEL_0 (0x00000001U)
#define | SDADC_CHANNEL_1 (0x00010002U)
#define | SDADC_CHANNEL_2 (0x00020004U)
#define | SDADC_CHANNEL_3 (0x00030008U)
#define | SDADC_CHANNEL_4 (0x00040010U)
#define | SDADC_CHANNEL_5 (0x00050020U)
#define | SDADC_CHANNEL_6 (0x00060040U)
#define | SDADC_CHANNEL_7 (0x00070080U)
#define | SDADC_CHANNEL_8 (0x00080100U)

Define Documentation

#define SDADC_CHANNEL_0 (0x00000001U)

Definition at line 238 of file stm32f3xx_hal_sdadc.h.

#define SDADC_CHANNEL_1 (0x00010002U)

Definition at line 239 of file stm32f3xx_hal_sdadc.h.

#define SDADC_CHANNEL_2 (0x00020004U)

Definition at line 240 of file stm32f3xx_hal_sdadc.h.

#define SDADC_CHANNEL_3 (0x00030008U)

Definition at line 241 of file stm32f3xx_hal_sdadc.h.

#define SDADC_CHANNEL_4 (0x00040010U)

Definition at line 242 of file stm32f3xx_hal_sdadc.h.

#define SDADC_CHANNEL_5 (0x00050020U)

Definition at line 243 of file stm32f3xx_hal_sdadc.h.

#define SDADC_CHANNEL_6 (0x00060040U)

Definition at line 244 of file stm32f3xx_hal_sdadc.h.

#define SDADC_CHANNEL_7 (0x00070080U)

Definition at line 245 of file stm32f3xx_hal_sdadc.h.

#define SDADC_CHANNEL_8 (0x00080100U)

Definition at line 246 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_AssociateChannelConfig().

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STM32F373xC HAL User Manual: SDADC Calibration Sequence

Defines
SDADC Calibration Sequence
SDADC Exported Constants

Defines

#define | SDADC_CALIBRATION_SEQ_1 (0x00000000U)
#define | SDADC_CALIBRATION_SEQ_2 SDADC_CR2_CALIBCNT_0
#define | SDADC_CALIBRATION_SEQ_3 SDADC_CR2_CALIBCNT_1

Define Documentation

#define SDADC_CALIBRATION_SEQ_1 (0x00000000U)

One calibration sequence to calculate offset of conf0 (OFFSET0[11:0])

Definition at line 254 of file stm32f3xx_hal_sdadc.h.

#define SDADC_CALIBRATION_SEQ_2 SDADC_CR2_CALIBCNT_0

Two calibration sequences to calculate offset of conf0 and conf1 (OFFSET0[11:0] and OFFSET1[11:0])

Definition at line 255 of file stm32f3xx_hal_sdadc.h.

#define SDADC_CALIBRATION_SEQ_3 SDADC_CR2_CALIBCNT_1

Three calibration sequences to calculate offset of conf0, conf1 and conf2 (OFFSET0[11:0], OFFSET1[11:0], and OFFSET2[11:0])

Definition at line 256 of file stm32f3xx_hal_sdadc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC Continuous Mode

Defines
SDADC Continuous Mode
SDADC Exported Constants

Defines

#define | SDADC_CONTINUOUS_CONV_OFF (0x00000000U)
#define | SDADC_CONTINUOUS_CONV_ON (0x00000001U)

Define Documentation

#define SDADC_CONTINUOUS_CONV_OFF (0x00000000U)

Conversion are not continuous

Definition at line 264 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init(), HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_IRQHandler(), HAL_SDADC_MultiModeStart_DMA(), HAL_SDADC_PollForConversion(), HAL_SDADC_PollForInjectedConversion(), and HAL_SDADC_Start_DMA().

#define SDADC_CONTINUOUS_CONV_ON (0x00000001U)

Conversion are continuous

Definition at line 265 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_ConfigChannel(), HAL_SDADC_InjectedConfigChannel(), SDADC_InjConvStop(), and SDADC_RegConvStop().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC Trigger

Defines
SDADC Trigger
SDADC Exported Constants

Defines

#define | SDADC_SOFTWARE_TRIGGER (0x00000000U)
#define | SDADC_SYNCHRONOUS_TRIGGER (0x00000001U)
#define | SDADC_EXTERNAL_TRIGGER (0x00000002U)

Define Documentation

#define SDADC_EXTERNAL_TRIGGER (0x00000002U)

External trigger

Definition at line 275 of file stm32f3xx_hal_sdadc.h.

#define SDADC_SOFTWARE_TRIGGER (0x00000000U)

Software trigger

Definition at line 273 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init(), HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_IRQHandler(), HAL_SDADC_MultiModeStart_DMA(), HAL_SDADC_PollForConversion(), HAL_SDADC_PollForInjectedConversion(), HAL_SDADC_Start_DMA(), SDADC_InjConvStart(), SDADC_InjConvStop(), and SDADC_RegConvStart().

#define SDADC_SYNCHRONOUS_TRIGGER (0x00000001U)

Synchronous with SDADC1 (only for SDADC2 and SDADC3)

Definition at line 274 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_SelectInjectedTrigger(), HAL_SDADC_SelectRegularTrigger(), SDADC_InjConvStart(), SDADC_InjConvStop(), and SDADC_RegConvStop().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC Injected External Trigger

Defines
SDADC Injected External Trigger
SDADC Exported Constants

Defines

#define | SDADC_EXT_TRIG_TIM13_CC1 (0x00000000U)
#define | SDADC_EXT_TRIG_TIM14_CC1 (0x00000100U)
#define | SDADC_EXT_TRIG_TIM16_CC1 (0x00000000U)
#define | SDADC_EXT_TRIG_TIM17_CC1 (0x00000000U)
#define | SDADC_EXT_TRIG_TIM12_CC1 (0x00000100U)
#define | SDADC_EXT_TRIG_TIM12_CC2 (0x00000100U)
#define | SDADC_EXT_TRIG_TIM15_CC2 (0x00000200U)
#define | SDADC_EXT_TRIG_TIM2_CC3 (0x00000200U)
#define | SDADC_EXT_TRIG_TIM2_CC4 (0x00000200U)
#define | SDADC_EXT_TRIG_TIM3_CC1 (0x00000300U)
#define | SDADC_EXT_TRIG_TIM3_CC2 (0x00000300U)
#define | SDADC_EXT_TRIG_TIM3_CC3 (0x00000300U)
#define | SDADC_EXT_TRIG_TIM4_CC1 (0x00000400U)
#define | SDADC_EXT_TRIG_TIM4_CC2 (0x00000400U)
#define | SDADC_EXT_TRIG_TIM4_CC3 (0x00000400U)
#define | SDADC_EXT_TRIG_TIM19_CC2 (0x00000500U)
#define | SDADC_EXT_TRIG_TIM19_CC3 (0x00000500U)
#define | SDADC_EXT_TRIG_TIM19_CC4 (0x00000500U)
#define | SDADC_EXT_TRIG_EXTI11 (0x00000700U)
#define | SDADC_EXT_TRIG_EXTI15 (0x00000600U)

Define Documentation

#define SDADC_EXT_TRIG_EXTI11 (0x00000700U)

Trigger source for SDADC1, SDADC2 and SDADC3

Definition at line 301 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_EXTI15 (0x00000600U)

Trigger source for SDADC1, SDADC2 and SDADC3

Definition at line 302 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM12_CC1 (0x00000100U)

Trigger source for SDADC2

Definition at line 287 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM12_CC2 (0x00000100U)

Trigger source for SDADC3

Definition at line 288 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM13_CC1 (0x00000000U)

Trigger source for SDADC1

Definition at line 283 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM14_CC1 (0x00000100U)

Trigger source for SDADC1

Definition at line 284 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM15_CC2 (0x00000200U)

Trigger source for SDADC1

Definition at line 289 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM16_CC1 (0x00000000U)

Trigger source for SDADC3

Definition at line 285 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM17_CC1 (0x00000000U)

Trigger source for SDADC2

Definition at line 286 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM19_CC2 (0x00000500U)

Trigger source for SDADC1

Definition at line 298 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM19_CC3 (0x00000500U)

Trigger source for SDADC2

Definition at line 299 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM19_CC4 (0x00000500U)

Trigger source for SDADC3

Definition at line 300 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM2_CC3 (0x00000200U)

Trigger source for SDADC2

Definition at line 290 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM2_CC4 (0x00000200U)

Trigger source for SDADC3

Definition at line 291 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM3_CC1 (0x00000300U)

Trigger source for SDADC1

Definition at line 292 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM3_CC2 (0x00000300U)

Trigger source for SDADC2

Definition at line 293 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM3_CC3 (0x00000300U)

Trigger source for SDADC3

Definition at line 294 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM4_CC1 (0x00000400U)

Trigger source for SDADC1

Definition at line 295 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM4_CC2 (0x00000400U)

Trigger source for SDADC2

Definition at line 296 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_TIM4_CC3 (0x00000400U)

Trigger source for SDADC3

Definition at line 297 of file stm32f3xx_hal_sdadc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC External Trigger Edge

Defines
SDADC External Trigger Edge
SDADC Exported Constants

Defines

#define | SDADC_EXT_TRIG_RISING_EDGE SDADC_CR2_JEXTEN_0
#define | SDADC_EXT_TRIG_FALLING_EDGE SDADC_CR2_JEXTEN_1
#define | SDADC_EXT_TRIG_BOTH_EDGES SDADC_CR2_JEXTEN

Define Documentation

#define SDADC_EXT_TRIG_BOTH_EDGES SDADC_CR2_JEXTEN

External rising and falling edges

Definition at line 312 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_FALLING_EDGE SDADC_CR2_JEXTEN_1

External falling edge

Definition at line 311 of file stm32f3xx_hal_sdadc.h.

#define SDADC_EXT_TRIG_RISING_EDGE SDADC_CR2_JEXTEN_0

External rising edge

Definition at line 310 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC Injected Conversion Delay

Defines
SDADC Injected Conversion Delay
SDADC Exported Constants

Defines

#define | SDADC_INJECTED_DELAY_NONE (0x00000000U)
#define | SDADC_INJECTED_DELAY SDADC_CR2_JDS

Define Documentation

#define SDADC_INJECTED_DELAY SDADC_CR2_JDS

Delay on injected conversion

Definition at line 321 of file stm32f3xx_hal_sdadc.h.

#define SDADC_INJECTED_DELAY_NONE (0x00000000U)

No delay on injected conversion

Definition at line 320 of file stm32f3xx_hal_sdadc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC Multimode Type

Defines
SDADC Multimode Type
SDADC Exported Constants

Defines

#define | SDADC_MULTIMODE_SDADC1_SDADC2 (0x00000000U)
#define | SDADC_MULTIMODE_SDADC1_SDADC3 (0x00000001U)

Define Documentation

#define SDADC_MULTIMODE_SDADC1_SDADC2 (0x00000000U)

Get conversion values for SDADC1 and SDADC2

Definition at line 329 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init(), HAL_SDADC_InjectedMultiModeGetValue(), HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_MultiModeGetValue(), and HAL_SDADC_MultiModeStart_DMA().

#define SDADC_MULTIMODE_SDADC1_SDADC3 (0x00000001U)

Get conversion values for SDADC1 and SDADC3

Definition at line 330 of file stm32f3xx_hal_sdadc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC Error Code

Defines
SDADC Error Code
SDADC Exported Constants

Defines

#define | SDADC_ERROR_NONE (0x00000000U)
#define | SDADC_ERROR_REGULAR_OVERRUN (0x00000001U)
#define | SDADC_ERROR_INJECTED_OVERRUN (0x00000002U)
#define | SDADC_ERROR_DMA (0x00000003U)

Define Documentation

#define SDADC_ERROR_DMA (0x00000003U)

DMA error occurs

Definition at line 341 of file stm32f3xx_hal_sdadc.h.

Referenced by SDADC_DMAError().

#define SDADC_ERROR_INJECTED_OVERRUN (0x00000002U)

Overrun occurs during injected conversion

Definition at line 340 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_IRQHandler(), and HAL_SDADC_PollForInjectedConversion().

#define SDADC_ERROR_NONE (0x00000000U)

No error

Definition at line 338 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init().

#define SDADC_ERROR_REGULAR_OVERRUN (0x00000001U)

Overrun occurs during regular conversion

Definition at line 339 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_IRQHandler(), and HAL_SDADC_PollForConversion().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC interrupts definition

Defines
SDADC interrupts definition
SDADC Exported Constants

Defines

#define | SDADC_IT_EOCAL SDADC_CR1_EOCALIE
#define | SDADC_IT_JEOC SDADC_CR1_JEOCIE
#define | SDADC_IT_JOVR SDADC_CR1_JOVRIE
#define | SDADC_IT_REOC SDADC_CR1_REOCIE
#define | SDADC_IT_ROVR SDADC_CR1_ROVRIE

Define Documentation

#define SDADC_IT_EOCAL SDADC_CR1_EOCALIE

End of calibration interrupt enable

Definition at line 349 of file stm32f3xx_hal_sdadc.h.

#define SDADC_IT_JEOC SDADC_CR1_JEOCIE

Injected end of conversion interrupt enable

Definition at line 350 of file stm32f3xx_hal_sdadc.h.

#define SDADC_IT_JOVR SDADC_CR1_JOVRIE

Injected data overrun interrupt enable

Definition at line 351 of file stm32f3xx_hal_sdadc.h.

#define SDADC_IT_REOC SDADC_CR1_REOCIE

Regular end of conversion interrupt enable

Definition at line 352 of file stm32f3xx_hal_sdadc.h.

#define SDADC_IT_ROVR SDADC_CR1_ROVRIE

Regular data overrun interrupt enable

Definition at line 353 of file stm32f3xx_hal_sdadc.h.

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STM32F373xC HAL User Manual: SDADC flags definition

Defines
SDADC flags definition
SDADC Exported Constants

Defines

#define | SDADC_FLAG_EOCAL SDADC_ISR_EOCALF
#define | SDADC_FLAG_JEOC SDADC_ISR_JEOCF
#define | SDADC_FLAG_JOVR SDADC_ISR_JOVRF
#define | SDADC_FLAG_REOC SDADC_ISR_REOCF
#define | SDADC_FLAG_ROVR SDADC_ISR_ROVRF

Define Documentation

#define SDADC_FLAG_EOCAL SDADC_ISR_EOCALF

End of calibration flag

Definition at line 361 of file stm32f3xx_hal_sdadc.h.

#define SDADC_FLAG_JEOC SDADC_ISR_JEOCF

End of injected conversion flag

Definition at line 362 of file stm32f3xx_hal_sdadc.h.

#define SDADC_FLAG_JOVR SDADC_ISR_JOVRF

Injected conversion overrun flag

Definition at line 363 of file stm32f3xx_hal_sdadc.h.

#define SDADC_FLAG_REOC SDADC_ISR_REOCF

End of regular conversion flag

Definition at line 364 of file stm32f3xx_hal_sdadc.h.

#define SDADC_FLAG_ROVR SDADC_ISR_ROVRF

Regular conversion overrun flag

Definition at line 365 of file stm32f3xx_hal_sdadc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC Exported Macros

Defines
SDADC Exported Macros
SDADC

Defines

#define | __HAL_SDADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
Enable the ADC end of conversion interrupt.
#define | __HAL_SDADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
Disable the ADC end of conversion interrupt.
#define | __HAL_SDADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_SDADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
Get the selected ADC's flag status.
#define | __HAL_SDADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (CLEAR_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)))
Clear the ADC's pending flags.
#define | __HAL_SDADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDADC_STATE_RESET)
Reset SDADC handle state.

Define Documentation

#define __HAL_SDADC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (CLEAR_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)))

Clear the ADC's pending flags.

Parameters:
__HANDLE__ ADC handle
__FLAG__ ADC flag This parameter can be any combination of the following values:
  • SDADC_FLAG_EOCAL: End of calibration flag
  • SDADC_FLAG_JEOC: End of injected conversion flag
  • SDADC_FLAG_JOVR: Injected conversion overrun flag
  • SDADC_FLAG_REOC: End of regular conversion flag
  • SDADC_FLAG_ROVR: Regular conversion overrun flag
Return values:
None

Definition at line 449 of file stm32f3xx_hal_sdadc.h.

#define __HAL_SDADC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))

Disable the ADC end of conversion interrupt.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC Interrupt This parameter can be any combination of the following values:
  • SDADC_IT_EOCAL: End of calibration interrupt enable
  • SDADC_IT_JEOC: Injected end of conversion interrupt enable
  • SDADC_IT_JOVR: Injected data overrun interrupt enable
  • SDADC_IT_REOC: Regular end of conversion interrupt enable
  • SDADC_IT_ROVR: Regular data overrun interrupt enable
Return values:
None

Definition at line 407 of file stm32f3xx_hal_sdadc.h.

#define __HAL_SDADC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))

Enable the ADC end of conversion interrupt.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC Interrupt This parameter can be any combination of the following values:
  • SDADC_IT_EOCAL: End of calibration interrupt enable
  • SDADC_IT_JEOC: Injected end of conversion interrupt enable
  • SDADC_IT_JOVR: Injected data overrun interrupt enable
  • SDADC_IT_REOC: Regular end of conversion interrupt enable
  • SDADC_IT_ROVR: Regular data overrun interrupt enable
Return values:
None

Definition at line 393 of file stm32f3xx_hal_sdadc.h.

#define __HAL_SDADC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))

Get the selected ADC's flag status.

Parameters:
__HANDLE__ ADC handle
__FLAG__ ADC flag This parameter can be any combination of the following values:
  • SDADC_FLAG_EOCAL: End of calibration flag
  • SDADC_FLAG_JEOC: End of injected conversion flag
  • SDADC_FLAG_JOVR: Injected conversion overrun flag
  • SDADC_FLAG_REOC: End of regular conversion flag
  • SDADC_FLAG_ROVR: Regular conversion overrun flag
Return values:
None

Definition at line 435 of file stm32f3xx_hal_sdadc.h.

#define __HAL_SDADC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))

Checks if the specified ADC interrupt source is enabled or disabled.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC interrupt source to check This parameter can be any combination of the following values:
  • SDADC_IT_EOCAL: End of calibration interrupt enable
  • SDADC_IT_JEOC: Injected end of conversion interrupt enable
  • SDADC_IT_JOVR: Injected data overrun interrupt enable
  • SDADC_IT_REOC: Regular end of conversion interrupt enable
  • SDADC_IT_ROVR: Regular data overrun interrupt enable
Return values:
State of interruption (SET or RESET)

Definition at line 421 of file stm32f3xx_hal_sdadc.h.

#define __HAL_SDADC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SDADC_STATE_RESET)

Reset SDADC handle state.

Parameters:
__HANDLE__ SDADC handle.
Return values:
None

Definition at line 456 of file stm32f3xx_hal_sdadc.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC Private Macros

Defines
SDADC Private Macros
SDADC

Defines

#define | IS_SDADC_LOWPOWER_MODE(LOWPOWER)
#define | IS_SDADC_FAST_CONV_MODE(FAST)
#define | IS_SDADC_SLOW_CLOCK_MODE(MODE)
#define | IS_SDADC_VREF(VREF)
#define | IS_SDADC_CONF_INDEX(CONF)
#define | IS_SDADC_INPUT_MODE(MODE)
#define | IS_SDADC_GAIN(GAIN)
#define | IS_SDADC_COMMON_MODE(MODE)
#define | IS_SDADC_OFFSET_VALUE(VALUE) ((VALUE) <= 0x00000FFFU)
#define | IS_SDADC_REGULAR_CHANNEL(CHANNEL)
#define | IS_SDADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F01FFU))
#define | IS_SDADC_CALIB_SEQUENCE(SEQUENCE)
#define | IS_SDADC_CONTINUOUS_MODE(MODE)
#define | IS_SDADC_REGULAR_TRIGGER(TRIGGER)
#define | IS_SDADC_INJECTED_TRIGGER(TRIGGER)
#define | IS_SDADC_EXT_INJEC_TRIG(INJTRIG)
#define | IS_SDADC_EXT_TRIG_EDGE(TRIGGER)
#define | IS_SDADC_INJECTED_DELAY(DELAY)
#define | IS_SDADC_MULTIMODE_TYPE(TYPE)

Define Documentation

#define IS_SDADC_CALIB_SEQUENCE ( SEQUENCE )
Value:
(((SEQUENCE) == SDADC_CALIBRATION_SEQ_1)  || \
                                            ((SEQUENCE) == SDADC_CALIBRATION_SEQ_2)  || \
                                            ((SEQUENCE) == SDADC_CALIBRATION_SEQ_3))

Definition at line 519 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_CalibrationStart(), and HAL_SDADC_CalibrationStart_IT().

#define IS_SDADC_COMMON_MODE ( MODE )
Value:
(((MODE) == SDADC_COMMON_MODE_VSSA)   || \
                                    ((MODE) == SDADC_COMMON_MODE_VDDA_2) || \
                                    ((MODE) == SDADC_COMMON_MODE_VDDA))

Definition at line 498 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_PrepareChannelConfig().

#define IS_SDADC_CONF_INDEX ( CONF )
Value:
(((CONF) == SDADC_CONF_INDEX_0)  || \
                                   ((CONF) == SDADC_CONF_INDEX_1)  || \
                                   ((CONF) == SDADC_CONF_INDEX_2))

Definition at line 482 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_AssociateChannelConfig(), and HAL_SDADC_PrepareChannelConfig().

#define IS_SDADC_CONTINUOUS_MODE ( MODE )
Value:
(((MODE) == SDADC_CONTINUOUS_CONV_OFF)  || \
                                             ((MODE) == SDADC_CONTINUOUS_CONV_ON))

Definition at line 523 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_ConfigChannel(), and HAL_SDADC_InjectedConfigChannel().

#define IS_SDADC_EXT_INJEC_TRIG ( INJTRIG )
Value:
(((INJTRIG) == SDADC_EXT_TRIG_TIM13_CC1) || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_TIM14_CC1) || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_TIM16_CC1) || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_TIM17_CC1) || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC1) || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC2)  || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_TIM15_CC2)  || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC3)  || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC4)  || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC1)  || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC2)  || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC3) || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC1) || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC2) || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC3) || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC2) || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC3) || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC4) || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_EXTI11) || \
                                          ((INJTRIG) == SDADC_EXT_TRIG_EXTI15))

Definition at line 535 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_SelectInjectedExtTrigger().

#define IS_SDADC_EXT_TRIG_EDGE ( TRIGGER )
Value:
(((TRIGGER) == SDADC_EXT_TRIG_RISING_EDGE)  || \
                                             ((TRIGGER) == SDADC_EXT_TRIG_FALLING_EDGE)  || \
                                             ((TRIGGER) == SDADC_EXT_TRIG_BOTH_EDGES))

Definition at line 556 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_SelectInjectedExtTrigger().

#define IS_SDADC_FAST_CONV_MODE ( FAST )
Value:
(((FAST) == SDADC_FAST_CONV_DISABLE) || \
                                              ((FAST) == SDADC_FAST_CONV_ENABLE))

Definition at line 471 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init().

#define IS_SDADC_GAIN ( GAIN )
Value:
(((GAIN) == SDADC_GAIN_1)  || \
                             ((GAIN) == SDADC_GAIN_2)  || \
                             ((GAIN) == SDADC_GAIN_4)  || \
                             ((GAIN) == SDADC_GAIN_8)  || \
                             ((GAIN) == SDADC_GAIN_16)  || \
                             ((GAIN) == SDADC_GAIN_32)  || \
                             ((GAIN) == SDADC_GAIN_1_2))

Definition at line 490 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_PrepareChannelConfig().

#define IS_SDADC_INJECTED_CHANNEL ( CHANNEL ) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F01FFU))

Definition at line 516 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_InjectedConfigChannel().

#define IS_SDADC_INJECTED_DELAY ( DELAY )
Value:
(((DELAY) == SDADC_INJECTED_DELAY_NONE) || \
                                             ((DELAY) == SDADC_INJECTED_DELAY))

Definition at line 561 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_SelectInjectedDelay().

#define IS_SDADC_INJECTED_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == SDADC_SOFTWARE_TRIGGER)  || \
                                             ((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER)  || \
                                             ((TRIGGER) == SDADC_EXTERNAL_TRIGGER))

Definition at line 530 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_SelectInjectedTrigger().

#define IS_SDADC_INPUT_MODE ( MODE )
Value:
(((MODE) == SDADC_INPUT_MODE_DIFF)     || \
                                   ((MODE) == SDADC_INPUT_MODE_SE_OFFSET) || \
                                   ((MODE) == SDADC_INPUT_MODE_SE_ZERO_REFERENCE))

Definition at line 486 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_PrepareChannelConfig().

#define IS_SDADC_LOWPOWER_MODE ( LOWPOWER )
Value:
(((LOWPOWER) == SDADC_LOWPOWER_NONE)      || \
                                              ((LOWPOWER) == SDADC_LOWPOWER_POWERDOWN) || \
                                              ((LOWPOWER) == SDADC_LOWPOWER_STANDBY))

Definition at line 467 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init().

#define IS_SDADC_MULTIMODE_TYPE ( TYPE )
Value:
(((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC2) || \
                                             ((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC3))

Definition at line 564 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_InjectedMultiModeConfigChannel(), and HAL_SDADC_MultiModeConfigChannel().

#define IS_SDADC_OFFSET_VALUE ( VALUE ) ((VALUE) <= 0x00000FFFU)

Definition at line 502 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_PrepareChannelConfig().

#define IS_SDADC_REGULAR_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == SDADC_CHANNEL_0)  || \
                                           ((CHANNEL) == SDADC_CHANNEL_1)  || \
                                           ((CHANNEL) == SDADC_CHANNEL_2)  || \
                                           ((CHANNEL) == SDADC_CHANNEL_3)  || \
                                           ((CHANNEL) == SDADC_CHANNEL_4)  || \
                                           ((CHANNEL) == SDADC_CHANNEL_5)  || \
                                           ((CHANNEL) == SDADC_CHANNEL_6)  || \
                                           ((CHANNEL) == SDADC_CHANNEL_7)  || \
                                           ((CHANNEL) == SDADC_CHANNEL_8))

Definition at line 505 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_AssociateChannelConfig(), and HAL_SDADC_ConfigChannel().

#define IS_SDADC_REGULAR_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == SDADC_SOFTWARE_TRIGGER)  || \
                                             ((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER))

Definition at line 527 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_SelectRegularTrigger().

#define IS_SDADC_SLOW_CLOCK_MODE ( MODE )
Value:
(((MODE) == SDADC_SLOW_CLOCK_DISABLE) || \
                                              ((MODE) == SDADC_SLOW_CLOCK_ENABLE))

Definition at line 474 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init().

#define IS_SDADC_VREF ( VREF )
Value:
(((VREF) == SDADC_VREF_EXT)      || \
                                              ((VREF) == SDADC_VREF_VREFINT1) || \
                                              ((VREF) == SDADC_VREF_VREFINT2) || \
                                              ((VREF) == SDADC_VREF_VDDA))

Definition at line 477 of file stm32f3xx_hal_sdadc.h.

Referenced by HAL_SDADC_Init().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Private Constants

Defines
SMARTCARD Private Constants
SMARTCARD

Defines

#define | SMARTCARD_TEACK_REACK_TIMEOUT 1000
#define | USART_CR1_FIELDS
#define | USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))
#define | USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))
#define | USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))

Define Documentation

#define SMARTCARD_TEACK_REACK_TIMEOUT 1000

SMARTCARD TX or RX enable acknowledge time-out value

Definition at line 152 of file stm32f3xx_hal_smartcard.c.

Referenced by SMARTCARD_CheckIdleState().

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
                                          USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))

USART CR1 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 154 of file stm32f3xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))

SMARTCARD clock-related USART CR2 fields of parameters

Definition at line 156 of file stm32f3xx_hal_smartcard.c.

#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))

USART CR2 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 157 of file stm32f3xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))

USART CR3 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 158 of file stm32f3xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SMARTCARD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USARTx
  associated to the SmartCard.
  [..]
  The Smartcard interface is designed to support asynchronous protocol Smartcards as
  defined in the ISO 7816-3 standard.
  [..]
  The USART can provide a clock to the smartcard through the SCLK output.
  In smartcard mode, SCLK is not associated to the communication but is simply derived
  from the internal peripheral input clock through a 5-bit prescaler.
  [..]
  (+) These parameters can be configured:
      (++) Baud Rate
      (++) Parity: should be enabled
      (++) Receiver/transmitter modes
      (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
      (++) Prescaler value
      (++) Guard bit time
      (++) NACK enabling or disabling on transmission error

  (+) The following advanced features can be configured as well:
      (++) TX and/or RX pin level inversion
      (++) data logical level inversion
      (++) RX and TX pins swap
      (++) RX overrun detection disabling
      (++) DMA disabling on RX error
      (++) MSB first on communication line
      (++) Time out enabling (and if activated, timeout value)
      (++) Block length
      (++) Auto-retry counter
  [..]
  The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
  (details for the procedures are available in reference manual).

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARD_DeInit ( SMARTCARD_HandleTypeDef * hsmartcard )

DeInitialize the SMARTCARD peripheral.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 318 of file stm32f3xx_hal_smartcard.c.

References assert_param, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_MspDeInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_SMARTCARD_Init ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 260 of file stm32f3xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_MspInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::Lock, SMARTCARD_ADVFEATURE_NO_INIT, SMARTCARD_AdvFeatureConfig(), SMARTCARD_CheckIdleState(), and SMARTCARD_SetConfig().

void HAL_SMARTCARD_MspDeInit ( SMARTCARD_HandleTypeDef * hsmartcard )

DeInitialize the SMARTCARD MSP.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 375 of file stm32f3xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_DeInit().

void HAL_SMARTCARD_MspInit ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the SMARTCARD MSP.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 359 of file stm32f3xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_Init().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IO operation functions

Functions
IO operation functions
SMARTCARD Exported Functions

SMARTCARD Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.

Detailed Description

SMARTCARD Transmit and Receive functions.

  ==============================================================================
                         ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.

  [..]
    Smartcard is a single wire half duplex communication protocol.
    The Smartcard interface is designed to support asynchronous protocol Smartcards as
    defined in the ISO 7816-3 standard. The USART should be configured as:
    (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
    (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.

  [..]
    (#) There are two modes of transfer:
        (++) Blocking mode: The communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) Non-Blocking mode: The communication is performed using Interrupts
             or DMA, the relevant API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
        (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
             will be executed respectively at the end of the Transmit or Receive process
             The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
             error is detected.

    (#) Blocking mode APIs are :
        (++) HAL_SMARTCARD_Transmit()
        (++) HAL_SMARTCARD_Receive()

    (#) Non Blocking mode APIs with Interrupt are :
        (++) HAL_SMARTCARD_Transmit_IT()
        (++) HAL_SMARTCARD_Receive_IT()
        (++) HAL_SMARTCARD_IRQHandler()

    (#) Non Blocking mode functions with DMA are :
        (++) HAL_SMARTCARD_Transmit_DMA()
        (++) HAL_SMARTCARD_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_SMARTCARD_TxCpltCallback()
        (++) HAL_SMARTCARD_RxCpltCallback()
        (++) HAL_SMARTCARD_ErrorCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (++) HAL_SMARTCARD_Abort()
        (++) HAL_SMARTCARD_AbortTransmit()
        (++) HAL_SMARTCARD_AbortReceive()
        (++) HAL_SMARTCARD_Abort_IT()
        (++) HAL_SMARTCARD_AbortTransmit_IT()
        (++) HAL_SMARTCARD_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
        (++) HAL_SMARTCARD_AbortCpltCallback()
        (++) HAL_SMARTCARD_AbortTransmitCpltCallback()
        (++) HAL_SMARTCARD_AbortReceiveCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
             to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
             and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
             If user wants to abort it, Abort services should be called by user.
        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
             This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
             Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARD_Abort ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing transfers (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 855 of file stm32f3xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing transfers (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1031 of file stm32f3xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1557 of file stm32f3xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_Abort_IT(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Receive transfer (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 976 of file stm32f3xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1233 of file stm32f3xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMARxOnlyAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortReceiveCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Receive Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1589 of file stm32f3xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_AbortReceive_IT(), and SMARTCARD_DMARxOnlyAbortCallback().

HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 923 of file stm32f3xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_FEF, SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1157 of file stm32f3xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_FEF, SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortTransmitCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1573 of file stm32f3xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_AbortTransmit_IT(), and SMARTCARD_DMATxOnlyAbortCallback().

void HAL_SMARTCARD_ErrorCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD error callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1541 of file stm32f3xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMAAbortOnError(), and SMARTCARD_DMAError().

void HAL_SMARTCARD_IRQHandler ( SMARTCARD_HandleTypeDef * hsmartcard )

Handle SMARTCARD interrupt requests.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1303 of file stm32f3xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_IT, __HAL_SMARTCARD_GET_IT, __HAL_SMARTCARD_GET_IT_SOURCE, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_ERROR_FE, HAL_SMARTCARD_ERROR_NE, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_ERROR_ORE, HAL_SMARTCARD_ERROR_PE, HAL_SMARTCARD_ERROR_RTO, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMAAbortOnError(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_IT_TC, SMARTCARD_Receive_IT(), SMARTCARD_Transmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Receive | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 557 of file stm32f3xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_FLAG_RXNE, and SMARTCARD_WaitOnFlagUntilTimeout().

HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Note:
The SMARTCARD-associated USART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
Return values:
HAL status

Definition at line 790 of file stm32f3xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Return values:
HAL status

Definition at line 671 of file stm32f3xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, and SMARTCARD_HandleTypeDef::RxXferSize.

void HAL_SMARTCARD_RxCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

Rx Transfer completed callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1525 of file stm32f3xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMAReceiveCplt(), and SMARTCARD_Receive_IT().

HAL_StatusTypeDef HAL_SMARTCARD_Transmit | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 476 of file stm32f3xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, SMARTCARD_FLAG_TC, SMARTCARD_FLAG_TXE, SMARTCARD_MODE_TX_RX, SMARTCARD_RXDATA_FLUSH_REQUEST, SMARTCARD_WaitOnFlagUntilTimeout(), SMARTCARD_HandleTypeDef::TxXferCount, and SMARTCARD_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Return values:
HAL status

Definition at line 716 of file stm32f3xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_DMAError(), SMARTCARD_DMATransmitCplt(), SMARTCARD_RXDATA_FLUSH_REQUEST, SMARTCARD_HandleTypeDef::TxXferCount, SMARTCARD_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Return values:
HAL status

Definition at line 615 of file stm32f3xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_RXDATA_FLUSH_REQUEST, SMARTCARD_HandleTypeDef::TxXferCount, and SMARTCARD_HandleTypeDef::TxXferSize.

void HAL_SMARTCARD_TxCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

Tx Transfer completed callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1509 of file stm32f3xx_hal_smartcard.c.

Referenced by SMARTCARD_EndTransmit_IT().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SMARTCARD Exported Functions

SMARTCARD State and Errors functions. More...

Functions

HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

SMARTCARD State and Errors functions.

  ==============================================================================
                  ##### Peripheral State and Errors functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of SmartCard
    handle and also return Peripheral Errors occurred during communication process
     (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
         of the SMARTCARD peripheral.
     (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
         communication.

Function Documentation

uint32_t HAL_SMARTCARD_GetError ( SMARTCARD_HandleTypeDef * hsmartcard )

Return the SMARTCARD handle error code.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
SMARTCARD handle Error Code

Definition at line 1644 of file stm32f3xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode.

HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState ( SMARTCARD_HandleTypeDef * hsmartcard )

Return the SMARTCARD handle state.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
SMARTCARD handle state

Definition at line 1628 of file stm32f3xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::gState, and SMARTCARD_HandleTypeDef::RxState.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Private Functions

Functions
SMARTCARD Private Functions
SMARTCARD

Functions

static HAL_StatusTypeDef | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral.
static void | SMARTCARD_AdvFeatureConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral advanced features.
static HAL_StatusTypeDef | SMARTCARD_CheckIdleState (SMARTCARD_HandleTypeDef *hsmartcard)
Check the SMARTCARD Idle State.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle SMARTCARD Communication Timeout.
static void | SMARTCARD_EndTxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
static void | SMARTCARD_EndRxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static void | SMARTCARD_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SMARTCARD_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SMARTCARD_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | SMARTCARD_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | SMARTCARD_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static HAL_StatusTypeDef | SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.

Function Documentation

static void SMARTCARD_AdvFeatureConfig ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Configure the SMARTCARD associated USART peripheral advanced features.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1765 of file stm32f3xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, SMARTCARD_AdvFeatureInitTypeDef::DataInvert, SMARTCARD_AdvFeatureInitTypeDef::DMADisableonRxError, SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_ADVFEATURE_DATAINV, IS_SMARTCARD_ADVFEATURE_DMAONRXERROR, IS_SMARTCARD_ADVFEATURE_INIT, IS_SMARTCARD_ADVFEATURE_MSBFIRST, IS_SMARTCARD_ADVFEATURE_RXINV, IS_SMARTCARD_ADVFEATURE_SWAP, IS_SMARTCARD_ADVFEATURE_TXINV, IS_SMARTCARD_OVERRUN, SMARTCARD_AdvFeatureInitTypeDef::MSBFirst, SMARTCARD_AdvFeatureInitTypeDef::OverrunDisable, SMARTCARD_AdvFeatureInitTypeDef::RxPinLevelInvert, SMARTCARD_ADVFEATURE_DATAINVERT_INIT, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT, SMARTCARD_ADVFEATURE_MSBFIRST_INIT, SMARTCARD_ADVFEATURE_RXINVERT_INIT, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT, SMARTCARD_ADVFEATURE_SWAP_INIT, SMARTCARD_ADVFEATURE_TXINVERT_INIT, SMARTCARD_AdvFeatureInitTypeDef::Swap, and SMARTCARD_AdvFeatureInitTypeDef::TxPinLevelInvert.

Referenced by HAL_SMARTCARD_Init().

static HAL_StatusTypeDef SMARTCARD_CheckIdleState ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Check the SMARTCARD Idle State.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 1827 of file stm32f3xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_TEACK_REACK_TIMEOUT, and SMARTCARD_WaitOnFlagUntilTimeout().

Referenced by HAL_SMARTCARD_Init().

static void SMARTCARD_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2020 of file stm32f3xx_hal_smartcard.c.

References HAL_SMARTCARD_ErrorCallback(), __DMA_HandleTypeDef::Parent, SMARTCARD_HandleTypeDef::RxXferCount, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_IRQHandler().

static void SMARTCARD_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD communication error callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1990 of file stm32f3xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_BUSY_TX, SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_EndRxTransfer(), SMARTCARD_EndTxTransfer(), and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Transmit_DMA().

static void SMARTCARD_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD receive process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1965 of file stm32f3xx_hal_smartcard.c.

References HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, SMARTCARD_HandleTypeDef::RxState, and SMARTCARD_HandleTypeDef::RxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA().

static void SMARTCARD_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2079 of file stm32f3xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SMARTCARD_Abort_IT().

static void SMARTCARD_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2145 of file stm32f3xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_STATE_READY, __DMA_HandleTypeDef::Parent, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, and SMARTCARD_CLEAR_RTOF.

Referenced by HAL_SMARTCARD_AbortReceive_IT().

static void SMARTCARD_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD transmit process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1946 of file stm32f3xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, SMARTCARD_IT_TC, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_DMA().

static void SMARTCARD_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2037 of file stm32f3xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SMARTCARD_Abort_IT().

static void SMARTCARD_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2121 of file stm32f3xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_STATE_READY, __DMA_HandleTypeDef::Parent, SMARTCARD_CLEAR_FEF, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_AbortTransmit_IT().

static void SMARTCARD_EndRxTransfer ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1929 of file stm32f3xx_hal_smartcard.c.

References HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::RxState.

Referenced by HAL_SMARTCARD_IRQHandler(), and SMARTCARD_DMAError().

static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 2204 of file stm32f3xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE_IT, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_TxCpltCallback(), SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_IT_TC, and SMARTCARD_MODE_TX_RX.

Referenced by HAL_SMARTCARD_IRQHandler().

static void SMARTCARD_EndTxTransfer ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1912 of file stm32f3xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_READY, and SMARTCARD_HandleTypeDef::Instance.

Referenced by HAL_SMARTCARD_IRQHandler(), and SMARTCARD_DMAError().

static HAL_StatusTypeDef SMARTCARD_Receive_IT ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Receive an amount of data in non-blocking mode.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module. Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
Return values:
HAL status

Definition at line 2242 of file stm32f3xx_hal_smartcard.c.

References __HAL_SMARTCARD_SEND_REQ, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, and SMARTCARD_RXDATA_FLUSH_REQUEST.

Referenced by HAL_SMARTCARD_IRQHandler().

static HAL_StatusTypeDef SMARTCARD_SetConfig ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Configure the SMARTCARD associated USART peripheral.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 1667 of file stm32f3xx_hal_smartcard.c.

References assert_param, SMARTCARD_InitTypeDef::AutoRetryCount, SMARTCARD_InitTypeDef::BaudRate, SMARTCARD_InitTypeDef::BlockLength, SMARTCARD_InitTypeDef::CLKLastBit, SMARTCARD_InitTypeDef::CLKPhase, SMARTCARD_InitTypeDef::CLKPolarity, SMARTCARD_InitTypeDef::GuardTime, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_AUTORETRY_COUNT, IS_SMARTCARD_BAUDRATE, IS_SMARTCARD_LASTBIT, IS_SMARTCARD_MODE, IS_SMARTCARD_NACK, IS_SMARTCARD_ONE_BIT_SAMPLE, IS_SMARTCARD_PARITY, IS_SMARTCARD_PHASE, IS_SMARTCARD_POLARITY, IS_SMARTCARD_STOPBITS, IS_SMARTCARD_TIMEOUT, IS_SMARTCARD_TIMEOUT_VALUE, IS_SMARTCARD_WORD_LENGTH, LSE_VALUE, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKEnable, SMARTCARD_InitTypeDef::OneBitSampling, SMARTCARD_InitTypeDef::Parity, SMARTCARD_InitTypeDef::Prescaler, SMARTCARD_CLOCKSOURCE_HSI, SMARTCARD_CLOCKSOURCE_LSE, SMARTCARD_CLOCKSOURCE_PCLK1, SMARTCARD_CLOCKSOURCE_PCLK2, SMARTCARD_CLOCKSOURCE_SYSCLK, SMARTCARD_CLOCKSOURCE_UNDEFINED, SMARTCARD_CR3_SCARCNT_LSB_POS, SMARTCARD_GETCLOCKSOURCE, SMARTCARD_GTPR_GT_LSB_POS, SMARTCARD_RTOR_BLEN_LSB_POS, SMARTCARD_TIMEOUT_ENABLE, SMARTCARD_InitTypeDef::StopBits, SMARTCARD_InitTypeDef::TimeOutEnable, SMARTCARD_InitTypeDef::TimeOutValue, USART_CR1_FIELDS, USART_CR2_FIELDS, USART_CR3_FIELDS, and SMARTCARD_InitTypeDef::WordLength.

Referenced by HAL_SMARTCARD_Init().

static HAL_StatusTypeDef SMARTCARD_Transmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Send an amount of data in non-blocking mode.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module. Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
Return values:
HAL status

Definition at line 2169 of file stm32f3xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY_TX, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_IT_TC, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_IRQHandler().

static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SMARTCARD Communication Timeout.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Flag | Specifies the SMARTCARD flag to check.
Status | The new Flag status (SET or RESET).
Tickstart | Tick start value
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 1879 of file stm32f3xx_hal_smartcard.c.

References __HAL_SMARTCARD_GET_FLAG, SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::RxState.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit(), and SMARTCARD_CheckIdleState().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Exported Types

Data Structures | Enumerations
SMARTCARD Exported Types
SMARTCARD

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_AdvFeatureInitTypeDef
SMARTCARD advanced features initalization structure definition. More...
struct | SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Enumerations

enum HAL_SMARTCARD_StateTypeDef {
HAL_SMARTCARD_STATE_RESET = 0x00U, HAL_SMARTCARD_STATE_READY = 0x20U, HAL_SMARTCARD_STATE_BUSY = 0x24U, HAL_SMARTCARD_STATE_BUSY_TX = 0x21U,
HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, HAL_SMARTCARD_STATE_ERROR = 0xE0U
}
HAL SMARTCARD State structures definition. More...
enum SMARTCARD_ClockSourceTypeDef {
SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, SMARTCARD_CLOCKSOURCE_HSI = 0x02U, SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U,
SMARTCARD_CLOCKSOURCE_LSE = 0x08U, SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U
}
SMARTCARD clock sources. More...

Enumeration Type Documentation

enum HAL_SMARTCARD_StateTypeDef

HAL SMARTCARD State structures definition.

Note:
HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
  • gState contains SMARTCARD state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
Enumerator:
HAL_SMARTCARD_STATE_RESET

Peripheral is not initialized Value is allowed for gState and RxState

HAL_SMARTCARD_STATE_READY

Peripheral Initialized and ready for use Value is allowed for gState and RxState

HAL_SMARTCARD_STATE_BUSY

an internal process is ongoing Value is allowed for gState only

HAL_SMARTCARD_STATE_BUSY_TX

Data Transmission process is ongoing Value is allowed for gState only

HAL_SMARTCARD_STATE_BUSY_RX

Data Reception process is ongoing Value is allowed for RxState only

HAL_SMARTCARD_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

HAL_SMARTCARD_STATE_TIMEOUT

Timeout state Value is allowed for gState only

HAL_SMARTCARD_STATE_ERROR

Error Value is allowed for gState only

Definition at line 194 of file stm32f3xx_hal_smartcard.h.

enum SMARTCARD_ClockSourceTypeDef

SMARTCARD clock sources.

Enumerator:
SMARTCARD_CLOCKSOURCE_PCLK1

PCLK1 clock source

SMARTCARD_CLOCKSOURCE_PCLK2

PCLK2 clock source

SMARTCARD_CLOCKSOURCE_HSI

HSI clock source

SMARTCARD_CLOCKSOURCE_SYSCLK

SYSCLK clock source

SMARTCARD_CLOCKSOURCE_LSE

LSE clock source

SMARTCARD_CLOCKSOURCE_UNDEFINED

undefined clock source

Definition at line 259 of file stm32f3xx_hal_smartcard.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_InitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD Init Structure definition. More...

#include <stm32f3xx_hal_smartcard.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint16_t | Parity
uint16_t | Mode
uint16_t | CLKPolarity
uint16_t | CLKPhase
uint16_t | CLKLastBit
uint16_t | OneBitSampling
uint8_t | Prescaler
uint8_t | GuardTime
uint16_t | NACKEnable
uint32_t | TimeOutEnable
uint32_t | TimeOutValue
uint8_t | BlockLength
uint8_t | AutoRetryCount

Detailed Description

SMARTCARD Init Structure definition.

Definition at line 63 of file stm32f3xx_hal_smartcard.h.

Field Documentation

uint8_t SMARTCARD_InitTypeDef::AutoRetryCount

Specifies the SmartCard auto-retry count (number of retries in receive and transmit mode). When set to 0U, retransmission is disabled. Otherwise, its maximum value is 7 (before signalling an error)

Definition at line 116 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::BaudRate

Configures the SmartCard communication baud rate. The baud rate register is computed using the following formula: Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate)))

Definition at line 65 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::BlockLength

Specifies the SmartCard Block Length in T=1 Reception mode. This parameter can be any value from 0x0 to 0xFFU

Definition at line 113 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of SMARTCARD Last Bit

Definition at line 90 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of SMARTCARD Clock Phase

Definition at line 87 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of SMARTCARD Clock Polarity

Definition at line 84 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::GuardTime

Specifies the SmartCard Guard Time applied after stop bits.

Definition at line 100 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of SMARTCARD Transfer Mode

Definition at line 81 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::NACKEnable

Specifies whether the SmartCard NACK transmission is enabled in case of parity error. This parameter can be a value of SMARTCARD NACK Enable

Definition at line 102 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::OneBitSampling

Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of SMARTCARD One Bit Sampling Method.

Definition at line 94 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of SMARTCARD Parity

Note:
The parity is enabled by default (PCE is forced to 1U). Since the WordLength is forced to 8 bits + parity, M is forced to 1 and the parity bit is the 9th bit.

Definition at line 75 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::Prescaler

Specifies the SmartCard Prescaler.

Definition at line 98 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::StopBits

Specifies the number of stop bits. This parameter can be a value of SMARTCARD Number of Stop Bits.

Definition at line 72 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::TimeOutEnable

Specifies whether the receiver timeout is enabled. This parameter can be a value of SMARTCARD Timeout Enable

Definition at line 106 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::TimeOutValue

Specifies the receiver time out value in number of baud blocks: it is used to implement the Character Wait Time (CWT) and Block Wait Time (BWT). It is coded over 24 bits.

Definition at line 109 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_TimeOut_Config(), and SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter SMARTCARD Word Length can only be set to 9 (8 data + 1 parity bits).

Definition at line 69 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_smartcard.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD_AdvFeatureInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_AdvFeatureInitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD advanced features initalization structure definition. More...

#include <stm32f3xx_hal_smartcard.h>

Data Fields

uint32_t | AdvFeatureInit
uint32_t | TxPinLevelInvert
uint32_t | RxPinLevelInvert
uint32_t | DataInvert
uint32_t | Swap
uint32_t | OverrunDisable
uint32_t | DMADisableonRxError
uint32_t | MSBFirst

Detailed Description

SMARTCARD advanced features initalization structure definition.

Definition at line 126 of file stm32f3xx_hal_smartcard.h.

Field Documentation

uint32_t SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit

Specifies which advanced SMARTCARD features is initialized. Several advanced features may be initialized at the same time. This parameter can be a value of SMARTCARD advanced feature initialization type

Definition at line 128 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), and SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::DataInvert

Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of SMARTCARD advanced feature Binary Data inversion

Definition at line 138 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::DMADisableonRxError

Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of SMARTCARD advanced feature DMA Disable on Rx Error

Definition at line 148 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::MSBFirst

Specifies whether MSB is sent first on UART line. This parameter can be a value of SMARTCARD advanced feature MSB first

Definition at line 151 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::OverrunDisable

Specifies whether the reception overrun detection is disabled. This parameter can be a value of SMARTCARD advanced feature Overrun Disable

Definition at line 145 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::RxPinLevelInvert

Specifies whether the RX pin active level is inverted. This parameter can be a value of SMARTCARD advanced feature RX pin active level inversion

Definition at line 135 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::Swap

Specifies whether TX and RX pins are swapped. This parameter can be a value of SMARTCARD advanced feature RX TX pins swap

Definition at line 142 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::TxPinLevelInvert

Specifies whether the TX pin active level is inverted. This parameter can be a value of SMARTCARD advanced feature TX pin active level inversion

Definition at line 132 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_smartcard.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_HandleTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD handle Structure definition. More...

#include <stm32f3xx_hal_smartcard.h>

Data Fields

USART_TypeDef * | Instance
SMARTCARD_InitTypeDef Init
SMARTCARD_AdvFeatureInitTypeDef AdvancedInit
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SMARTCARD_StateTypeDef | gState
__IO HAL_SMARTCARD_StateTypeDef | RxState
__IO uint32_t | ErrorCode

Detailed Description

SMARTCARD handle Structure definition.

Definition at line 218 of file stm32f3xx_hal_smartcard.h.

Field Documentation

SMARTCARD_AdvFeatureInitTypeDef SMARTCARD_HandleTypeDef::AdvancedInit

SmartCard advanced features initialization parameters

Definition at line 224 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), and SMARTCARD_AdvFeatureConfig().

__IO uint32_t SMARTCARD_HandleTypeDef::ErrorCode

SmartCard Error code This parameter can be a value of SMARTCARD Error

Definition at line 251 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetError(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

__IO HAL_SMARTCARD_StateTypeDef SMARTCARD_HandleTypeDef::gState

SmartCard state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_SMARTCARD_StateTypeDef

Definition at line 244 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_Receive_IT(), SMARTCARD_Transmit_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* SMARTCARD_HandleTypeDef::hdmarx

SmartCard Rx DMA Handle parameters

Definition at line 240 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_DMA(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

DMA_HandleTypeDef* SMARTCARD_HandleTypeDef::hdmatx

SmartCard Tx DMA Handle parameters

Definition at line 238 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit_DMA(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

SMARTCARD_InitTypeDef SMARTCARD_HandleTypeDef::Init

SmartCard communication parameters

Definition at line 222 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARDEx_TimeOut_Config(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

USART_TypeDef* SMARTCARD_HandleTypeDef::Instance

USART registers base address

Definition at line 220 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARDEx_BlockLength_Config(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_TimeOut_Config(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_Receive_IT(), SMARTCARD_SetConfig(), SMARTCARD_Transmit_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

HAL_LockTypeDef SMARTCARD_HandleTypeDef::Lock

Locking object

Definition at line 242 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

uint8_t* SMARTCARD_HandleTypeDef::pRxBuffPtr

Pointer to SmartCard Rx transfer Buffer

Definition at line 232 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), and SMARTCARD_Receive_IT().

uint8_t* SMARTCARD_HandleTypeDef::pTxBuffPtr

Pointer to SmartCard Tx transfer Buffer

Definition at line 226 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_Transmit_IT().

__IO HAL_SMARTCARD_StateTypeDef SMARTCARD_HandleTypeDef::RxState

SmartCard state information related to Rx operations. This parameter can be a value of HAL_SMARTCARD_StateTypeDef

Definition at line 248 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_Receive_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

__IO uint16_t SMARTCARD_HandleTypeDef::RxXferCount

SmartCard Rx Transfer Counter

Definition at line 236 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_Receive_IT().

uint16_t SMARTCARD_HandleTypeDef::RxXferSize

SmartCard Rx Transfer size

Definition at line 234 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Receive_IT().

__IO uint16_t SMARTCARD_HandleTypeDef::TxXferCount

SmartCard Tx Transfer Counter

Definition at line 230 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATransmitCplt(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), and SMARTCARD_Transmit_IT().

uint16_t SMARTCARD_HandleTypeDef::TxXferSize

SmartCard Tx Transfer size

Definition at line 228 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), and HAL_SMARTCARD_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_smartcard.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Error

Defines
SMARTCARD Error
SMARTCARD Exported Constants

Defines

#define | HAL_SMARTCARD_ERROR_NONE (0x00000000U)
#define | HAL_SMARTCARD_ERROR_PE (0x00000001U)
#define | HAL_SMARTCARD_ERROR_NE (0x00000002U)
#define | HAL_SMARTCARD_ERROR_FE (0x00000004U)
#define | HAL_SMARTCARD_ERROR_ORE (0x00000008U)
#define | HAL_SMARTCARD_ERROR_DMA (0x00000010U)
#define | HAL_SMARTCARD_ERROR_RTO (0x00000020U)

Define Documentation

#define HAL_SMARTCARD_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 286 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_DMAError().

#define HAL_SMARTCARD_ERROR_FE (0x00000004U)

frame error

Definition at line 284 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_NE (0x00000002U)

Noise error

Definition at line 283 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_NONE (0x00000000U)

No error

Definition at line 281 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_CheckIdleState(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define HAL_SMARTCARD_ERROR_ORE (0x00000008U)

Overrun error

Definition at line 285 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_PE (0x00000001U)

Parity error

Definition at line 282 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_RTO (0x00000020U)

Receiver TimeOut error

Definition at line 287 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Word Length

Defines
SMARTCARD Word Length
SMARTCARD Exported Constants

Defines

#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

Define Documentation

#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

SMARTCARD frame length

Definition at line 295 of file stm32f3xx_hal_smartcard.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Number of Stop Bits

Defines
SMARTCARD Number of Stop Bits
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

Define Documentation

#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)

SMARTCARD frame with 0.5 stop bit

Definition at line 303 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

SMARTCARD frame with 1.5 stop bits

Definition at line 304 of file stm32f3xx_hal_smartcard.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Parity

Defines
SMARTCARD Parity
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

SMARTCARD frame even parity

Definition at line 312 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

SMARTCARD frame odd parity

Definition at line 313 of file stm32f3xx_hal_smartcard.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Transfer Mode

Defines
SMARTCARD Transfer Mode
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
#define | SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
#define | SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)

SMARTCARD RX mode

Definition at line 321 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)

SMARTCARD TX mode

Definition at line 322 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

SMARTCARD RX and TX mode

Definition at line 323 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), and SMARTCARD_EndTransmit_IT().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Clock Polarity

Defines
SMARTCARD Clock Polarity
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_POLARITY_LOW (0x00000000U)
#define | SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Define Documentation

#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

SMARTCARD frame high polarity

Definition at line 332 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_POLARITY_LOW (0x00000000U)

SMARTCARD frame low polarity

Definition at line 331 of file stm32f3xx_hal_smartcard.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Clock Phase

Defines
SMARTCARD Clock Phase
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PHASE_1EDGE (0x00000000U)
#define | SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Define Documentation

#define SMARTCARD_PHASE_1EDGE (0x00000000U)

SMARTCARD frame phase on first clock transition

Definition at line 340 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

SMARTCARD frame phase on second clock transition

Definition at line 341 of file stm32f3xx_hal_smartcard.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Last Bit

Defines
SMARTCARD Last Bit
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_LASTBIT_DISABLE (0x00000000U)
#define | SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Define Documentation

#define SMARTCARD_LASTBIT_DISABLE (0x00000000U)

SMARTCARD frame last data bit clock pulse not output to SCLK pin

Definition at line 349 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

SMARTCARD frame last data bit clock pulse output to SCLK pin

Definition at line 350 of file stm32f3xx_hal_smartcard.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD One Bit Sampling Method

Defines
SMARTCARD One Bit Sampling Method
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ONE_BIT_SAMPLE_DISABLE (0x00000000U)
#define | SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

Define Documentation

#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE (0x00000000U)

SMARTCARD frame one-bit sample disabled

Definition at line 358 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

SMARTCARD frame one-bit sample enabled

Definition at line 359 of file stm32f3xx_hal_smartcard.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD NACK Enable

Defines
SMARTCARD NACK Enable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define | SMARTCARD_NACK_DISABLE (0x00000000U)

Define Documentation

#define SMARTCARD_NACK_DISABLE (0x00000000U)

SMARTCARD NACK transmission enabled

Definition at line 369 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)

SMARTCARD NACK transmission disabled

Definition at line 368 of file stm32f3xx_hal_smartcard.h.

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STM32F373xC HAL User Manual: SMARTCARD Timeout Enable

Defines
SMARTCARD Timeout Enable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_TIMEOUT_DISABLE (0x00000000U)
#define | SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)

Define Documentation

#define SMARTCARD_TIMEOUT_DISABLE (0x00000000U)

SMARTCARD receiver timeout disabled

Definition at line 377 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)

SMARTCARD receiver timeout enabled

Definition at line 378 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

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STM32F373xC HAL User Manual: SMARTCARD advanced feature initialization type

Defines
SMARTCARD advanced feature initialization type
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_NO_INIT (0x00000000U)
#define | SMARTCARD_ADVFEATURE_TXINVERT_INIT (0x00000001U)
#define | SMARTCARD_ADVFEATURE_RXINVERT_INIT (0x00000002U)
#define | SMARTCARD_ADVFEATURE_DATAINVERT_INIT (0x00000004U)
#define | SMARTCARD_ADVFEATURE_SWAP_INIT (0x00000008U)
#define | SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U)
#define | SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_INIT (0x00000080U)

Define Documentation

#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT (0x00000004U)

Binary data inversion

Definition at line 389 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U)

DMA disable on Reception Error

Definition at line 392 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT (0x00000080U)

Most significant bit sent/received first

Definition at line 393 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_NO_INIT (0x00000000U)

No advanced feature initialization

Definition at line 386 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

#define SMARTCARD_ADVFEATURE_RXINVERT_INIT (0x00000002U)

RX pin active level inversion

Definition at line 388 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U)

RX overrun disable

Definition at line 391 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_SWAP_INIT (0x00000008U)

TX/RX pins swap

Definition at line 390 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_TXINVERT_INIT (0x00000001U)

TX pin active level inversion

Definition at line 387 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

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STM32F373xC HAL User Manual: SMARTCARD advanced feature TX pin active level inversion

Defines
SMARTCARD advanced feature TX pin active level inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_TXINV_DISABLE (0x00000000U)
#define | SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)

Define Documentation

#define SMARTCARD_ADVFEATURE_TXINV_DISABLE (0x00000000U)

TX pin active level inversion disable

Definition at line 401 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)

TX pin active level inversion enable

Definition at line 402 of file stm32f3xx_hal_smartcard.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD advanced feature RX pin active level inversion

Defines
SMARTCARD advanced feature RX pin active level inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_RXINV_DISABLE (0x00000000U)
#define | SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)

Define Documentation

#define SMARTCARD_ADVFEATURE_RXINV_DISABLE (0x00000000U)

RX pin active level inversion disable

Definition at line 410 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)

RX pin active level inversion enable

Definition at line 411 of file stm32f3xx_hal_smartcard.h.

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STM32F373xC HAL User Manual: SMARTCARD advanced feature Binary Data inversion

Defines
SMARTCARD advanced feature Binary Data inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_DATAINV_DISABLE (0x00000000U)
#define | SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)

Define Documentation

#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE (0x00000000U)

Binary data inversion disable

Definition at line 419 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)

Binary data inversion enable

Definition at line 420 of file stm32f3xx_hal_smartcard.h.

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STM32F373xC HAL User Manual: SMARTCARD advanced feature RX TX pins swap

Defines
SMARTCARD advanced feature RX TX pins swap
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_SWAP_DISABLE (0x00000000U)
#define | SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)

Define Documentation

#define SMARTCARD_ADVFEATURE_SWAP_DISABLE (0x00000000U)

TX/RX pins swap disable

Definition at line 428 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)

TX/RX pins swap enable

Definition at line 429 of file stm32f3xx_hal_smartcard.h.

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STM32F373xC HAL User Manual: SMARTCARD advanced feature Overrun Disable

Defines
SMARTCARD advanced feature Overrun Disable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_OVERRUN_ENABLE (0x00000000U)
#define | SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)

Define Documentation

#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)

RX overrun disable

Definition at line 438 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE (0x00000000U)

RX overrun enable

Definition at line 437 of file stm32f3xx_hal_smartcard.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD advanced feature DMA Disable on Rx Error

Defines
SMARTCARD advanced feature DMA Disable on Rx Error
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U)
#define | SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)

Define Documentation

#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)

DMA disable on Reception Error

Definition at line 447 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U)

DMA enable on Reception Error

Definition at line 446 of file stm32f3xx_hal_smartcard.h.

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STM32F373xC HAL User Manual: SMARTCARD advanced feature MSB first

Defines
SMARTCARD advanced feature MSB first
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)

Define Documentation

#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U)

Most significant bit sent/received first disable

Definition at line 455 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)

Most significant bit sent/received first enable

Definition at line 456 of file stm32f3xx_hal_smartcard.h.

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STM32F373xC HAL User Manual: SMARTCARD Flags

Defines
SMARTCARD Flags
SMARTCARD Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | SMARTCARD_FLAG_REACK USART_ISR_REACK
#define | SMARTCARD_FLAG_TEACK USART_ISR_TEACK
#define | SMARTCARD_FLAG_BUSY USART_ISR_BUSY
#define | SMARTCARD_FLAG_EOBF USART_ISR_EOBF
#define | SMARTCARD_FLAG_RTOF USART_ISR_RTOF
#define | SMARTCARD_FLAG_TXE USART_ISR_TXE
#define | SMARTCARD_FLAG_TC USART_ISR_TC
#define | SMARTCARD_FLAG_RXNE USART_ISR_RXNE
#define | SMARTCARD_FLAG_IDLE USART_ISR_IDLE
#define | SMARTCARD_FLAG_ORE USART_ISR_ORE
#define | SMARTCARD_FLAG_NE USART_ISR_NE
#define | SMARTCARD_FLAG_FE USART_ISR_FE
#define | SMARTCARD_FLAG_PE USART_ISR_PE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY

SMARTCARD busy flag

Definition at line 468 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF

SMARTCARD end of block flag

Definition at line 469 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_FLAG_FE USART_ISR_FE

SMARTCARD frame error

Definition at line 477 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE

SMARTCARD idle line detection

Definition at line 474 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_FLAG_NE USART_ISR_NE

SMARTCARD noise error

Definition at line 476 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_FLAG_ORE USART_ISR_ORE

SMARTCARD overrun error

Definition at line 475 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_FLAG_PE USART_ISR_PE

SMARTCARD parity error

Definition at line 478 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_FLAG_REACK USART_ISR_REACK

SMARTCARD receive enable acknowledge flag

Definition at line 466 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF

SMARTCARD receiver timeout flag

Definition at line 470 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE

SMARTCARD read data register not empty

Definition at line 473 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive().

#define SMARTCARD_FLAG_TC USART_ISR_TC

SMARTCARD transmission complete

Definition at line 472 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit().

#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK

SMARTCARD transmit enable acknowledge flag

Definition at line 467 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_FLAG_TXE USART_ISR_TXE

SMARTCARD transmit data register empty

Definition at line 471 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Interrupts Definition

Defines
SMARTCARD Interrupts Definition
SMARTCARD Exported Constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | SMARTCARD_IT_PE ((uint16_t)0x0028U)
#define | SMARTCARD_IT_TXE ((uint16_t)0x0727U)
#define | SMARTCARD_IT_TC ((uint16_t)0x0626U)
#define | SMARTCARD_IT_RXNE ((uint16_t)0x0525U)
#define | SMARTCARD_IT_IDLE ((uint16_t)0x0424U)
#define | SMARTCARD_IT_ERR ((uint16_t)0x0060U)
#define | SMARTCARD_IT_ORE ((uint16_t)0x0300U)
#define | SMARTCARD_IT_NE ((uint16_t)0x0200U)
#define | SMARTCARD_IT_FE ((uint16_t)0x0100U)
#define | SMARTCARD_IT_EOB ((uint16_t)0x0C3BU)
#define | SMARTCARD_IT_RTO ((uint16_t)0x0B3AU)

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define SMARTCARD_IT_EOB ((uint16_t)0x0C3BU)

SMARTCARD end of block interruption

Definition at line 505 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_IT_ERR ((uint16_t)0x0060U)

SMARTCARD error interruption

Definition at line 500 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_IT_FE ((uint16_t)0x0100U)

SMARTCARD frame error interruption

Definition at line 503 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_IT_IDLE ((uint16_t)0x0424U)

SMARTCARD idle line detection interruption

Definition at line 498 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_IT_NE ((uint16_t)0x0200U)

SMARTCARD noise error interruption

Definition at line 502 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_IT_ORE ((uint16_t)0x0300U)

SMARTCARD overrun error interruption

Definition at line 501 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_IT_PE ((uint16_t)0x0028U)

SMARTCARD parity error interruption

Definition at line 494 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_IT_RTO ((uint16_t)0x0B3AU)

SMARTCARD receiver timeout interruption

Definition at line 506 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_IT_RXNE ((uint16_t)0x0525U)

SMARTCARD read data register not empty interruption

Definition at line 497 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_IT_TC ((uint16_t)0x0626U)

SMARTCARD transmission complete interruption

Definition at line 496 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_Transmit_IT().

#define SMARTCARD_IT_TXE ((uint16_t)0x0727U)

SMARTCARD transmit data register empty interruption

Definition at line 495 of file stm32f3xx_hal_smartcard.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Interruption Clear Flags

Defines
SMARTCARD Interruption Clear Flags
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_CLEAR_PEF USART_ICR_PECF
#define | SMARTCARD_CLEAR_FEF USART_ICR_FECF
#define | SMARTCARD_CLEAR_NEF USART_ICR_NCF
#define | SMARTCARD_CLEAR_OREF USART_ICR_ORECF
#define | SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF
#define | SMARTCARD_CLEAR_TCF USART_ICR_TCCF
#define | SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF
#define | SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF

Define Documentation

#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF

SMARTCARD end of block clear flag

Definition at line 521 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_FEF USART_ICR_FECF

SMARTCARD framing error clear flag

Definition at line 515 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_DMATxOnlyAbortCallback().

#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF

SMARTCARD idle line detected clear flag

Definition at line 518 of file stm32f3xx_hal_smartcard.h.

#define SMARTCARD_CLEAR_NEF USART_ICR_NCF

SMARTCARD noise detected clear flag

Definition at line 516 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF

SMARTCARD overrun error clear flag

Definition at line 517 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_PEF USART_ICR_PECF

SMARTCARD parity error clear flag

Definition at line 514 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF

SMARTCARD receiver time out clear flag

Definition at line 520 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF

SMARTCARD transmission complete clear flag

Definition at line 519 of file stm32f3xx_hal_smartcard.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD auto retry counter LSB position in CR3 register

Defines
SMARTCARD auto retry counter LSB position in CR3 register
SMARTCARD Exported Constants

Defines

#define SMARTCARD_CR3_SCARCNT_LSB_POS ( 17U)

Define Documentation

#define SMARTCARD_CR3_SCARCNT_LSB_POS ( 17U)

SMARTCARD auto retry counter LSB position in CR3 register

Definition at line 529 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD guard time value LSB position in GTPR register

Defines
SMARTCARD guard time value LSB position in GTPR register
SMARTCARD Exported Constants

Defines

#define SMARTCARD_GTPR_GT_LSB_POS ( 8U)

Define Documentation

#define SMARTCARD_GTPR_GT_LSB_POS ( 8U)

SMARTCARD guard time value LSB position in GTPR register

Definition at line 537 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD block length LSB position in RTOR register

Defines
SMARTCARD block length LSB position in RTOR register
SMARTCARD Exported Constants

Defines

#define SMARTCARD_RTOR_BLEN_LSB_POS ( 24U)

Define Documentation

#define SMARTCARD_RTOR_BLEN_LSB_POS ( 24U)

SMARTCARD block length LSB position in RTOR register

Definition at line 545 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_BlockLength_Config(), and SMARTCARD_SetConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD interruptions flags mask

Defines
SMARTCARD interruptions flags mask
SMARTCARD Exported Constants

Defines

#define SMARTCARD_IT_MASK ((uint16_t)0x001FU)

Define Documentation

#define SMARTCARD_IT_MASK ((uint16_t)0x001FU)

SMARTCARD interruptions flags mask

Definition at line 553 of file stm32f3xx_hal_smartcard.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Request Parameters

Defines
SMARTCARD Request Parameters
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | SMARTCARD_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Define Documentation

#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)

Receive data flush request

Definition at line 561 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_Receive_IT().

#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Transmit data flush request

Definition at line 562 of file stm32f3xx_hal_smartcard.h.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Exported Macros

Defines
SMARTCARD Exported Macros
SMARTCARD

Defines

#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle states.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)
Flush the Smartcard Data registers.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified SMARTCARD pending flag.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
Check whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified SmartCard interrupt source is enabled or not.
#define | __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
#define | __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific SMARTCARD request flag.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.

Define Documentation

#define __HAL_SMARTCARD_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)

Clear the SMARTCARD FE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 622 of file stm32f3xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified SMARTCARD pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • SMARTCARD_CLEAR_PEF Parity error clear flag
  • SMARTCARD_CLEAR_FEF Framing error clear flag
  • SMARTCARD_CLEAR_NEF Noise detected clear flag
  • SMARTCARD_CLEAR_OREF OverRun error clear flag
  • SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
  • SMARTCARD_CLEAR_TCF Transmission complete clear flag
  • SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
  • SMARTCARD_CLEAR_EOBF End of block clear flag
Return values:
None

Definition at line 609 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_DMATxOnlyAbortCallback().

#define __HAL_SMARTCARD_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)

Clear the SMARTCARD IDLE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 640 of file stm32f3xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt. This parameter can be one of the following values:
  • SMARTCARD_CLEAR_PEF Parity error clear flag
  • SMARTCARD_CLEAR_FEF Framing error clear flag
  • SMARTCARD_CLEAR_NEF Noise detected clear flag
  • SMARTCARD_CLEAR_OREF OverRun error clear flag
  • SMARTCARD_CLEAR_IDLEF Idle line detection clear flag
  • SMARTCARD_CLEAR_TCF Transmission complete clear flag
  • SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
  • SMARTCARD_CLEAR_EOBF End of block clear flag
Return values:
None

Definition at line 753 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)

Clear the SMARTCARD NE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 628 of file stm32f3xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)

Clear the SMARTCARD ORE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 634 of file stm32f3xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)

Clear the SMARTCARD PE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 615 of file stm32f3xx_hal_smartcard.h.

#define __HAL_SMARTCARD_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 788 of file stm32f3xx_hal_smartcard.h.

#define __HAL_SMARTCARD_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

Disable the specified SmartCard interrupt.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt to disable. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
Return values:
None

Definition at line 696 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_EndTransmit_IT().

#define __HAL_SMARTCARD_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 782 of file stm32f3xx_hal_smartcard.h.

#define __HAL_SMARTCARD_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

Enable the specified SmartCard interrupt.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt to enable. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
Return values:
None

Definition at line 678 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_DMATransmitCplt(), and SMARTCARD_Transmit_IT().

#define __HAL_SMARTCARD_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                                                                     \
      SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
      SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
      } while(0U)

Flush the Smartcard Data registers.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 589 of file stm32f3xx_hal_smartcard.h.

#define __HAL_SMARTCARD_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified Smartcard flag is set or not.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SMARTCARD_FLAG_REACK Receive enable acknowledge flag
  • SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
  • SMARTCARD_FLAG_BUSY Busy flag
  • SMARTCARD_FLAG_EOBF End of block flag
  • SMARTCARD_FLAG_RTOF Receiver timeout flag
  • SMARTCARD_FLAG_TXE Transmit data register empty flag
  • SMARTCARD_FLAG_TC Transmission complete flag
  • SMARTCARD_FLAG_RXNE Receive data register not empty flag
  • SMARTCARD_FLAG_IDLE Idle line detection flag
  • SMARTCARD_FLAG_ORE Overrun error flag
  • SMARTCARD_FLAG_NE Noise error flag
  • SMARTCARD_FLAG_FE Framing error flag
  • SMARTCARD_FLAG_PE Parity error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 661 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_WaitOnFlagUntilTimeout().

#define __HAL_SMARTCARD_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))

Check whether the specified SmartCard interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__IT__ specifies the SMARTCARD interrupt to check. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_ORE Overrun error interrupt
  • SMARTCARD_IT_NE Noise error interrupt
  • SMARTCARD_IT_FE Framing error interrupt
  • SMARTCARD_IT_PE Parity error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 717 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
((((((__IT__) & 0xFFU) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1 : \
                                                           (((((__IT__) & 0xFFU) >> 5U) == 2U)? (__HANDLE__)->Instance->CR2 : \
                                                           (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))

Check whether the specified SmartCard interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__IT__ specifies the SMARTCARD interrupt source to check. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_ERR Framing, overrun or noise error interrupt
  • SMARTCARD_IT_PE Parity error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 733 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the SMARTCARD one bit sample method.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 776 of file stm32f3xx_hal_smartcard.h.

#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the SMARTCARD one bit sample method.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 770 of file stm32f3xx_hal_smartcard.h.

#define __HAL_SMARTCARD_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                       \
                                                           (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
                                                           (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
                                                          } while(0U)

Reset SMARTCARD handle states.

Parameters:
__HANDLE__ SMARTCARD handle.
Return values:
None

Definition at line 580 of file stm32f3xx_hal_smartcard.h.

#define __HAL_SMARTCARD_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific SMARTCARD request flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__REQ__ specifies the request flag to set This parameter can be one of the following values:
  • SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
  • SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 764 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_Receive_IT().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Private Macros

Defines
SMARTCARD Private Macros
SMARTCARD

Defines

#define | IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001U)
Check the Baud rate range.
#define | IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
Check the block length range.
#define | IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
Check the SMARTCARD autoretry counter value.
#define | IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
Ensure that SMARTCARD frame length is valid.
#define | IS_SMARTCARD_STOPBITS(__STOPBITS__)
Ensure that SMARTCARD frame number of stop bits is valid.
#define | IS_SMARTCARD_PARITY(__PARITY__)
Ensure that SMARTCARD frame parity is valid.
#define | IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3U) == 0x00U) && ((__MODE__) != (uint16_t)0x00U))
Ensure that SMARTCARD communication mode is valid.
#define | IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
Ensure that SMARTCARD frame polarity is valid.
#define | IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
Ensure that SMARTCARD frame phase is valid.
#define | IS_SMARTCARD_LASTBIT(__LASTBIT__)
Ensure that SMARTCARD frame last bit clock pulse setting is valid.
#define | IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that SMARTCARD frame sampling is valid.
#define | IS_SMARTCARD_NACK(__NACK__)
Ensure that SMARTCARD NACK transmission setting is valid.
#define | IS_SMARTCARD_TIMEOUT(__TIMEOUT__)
Ensure that SMARTCARD receiver timeout setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_INIT(__INIT__)
Ensure that SMARTCARD advanced features initialization is valid.
#define | IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__)
Ensure that SMARTCARD frame TX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__)
Ensure that SMARTCARD frame RX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that SMARTCARD frame data inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__)
Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
#define | IS_SMARTCARD_OVERRUN(__OVERRUN__)
Ensure that SMARTCARD frame overrun setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that SMARTCARD frame MSB first setting is valid.
#define | IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__)
Ensure that SMARTCARD request parameter is valid.

Define Documentation

#define IS_SMARTCARD_ADVFEATURE_DATAINV ( __DATAINV__ )
Value:
(((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
                                                      ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))

Ensure that SMARTCARD frame data inversion setting is valid.

Parameters:
__DATAINV__ SMARTCARD frame data inversion setting.
Return values:
SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)

Definition at line 939 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR ( __DMA__ )
Value:
(((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
                                                       ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))

Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.

Parameters:
__DMA__ SMARTCARD DMA enabling or disabling on error setting.
Return values:
SET (__DMA__ is valid) or RESET (__DMA__ is invalid)

Definition at line 963 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_INIT ( __INIT__ )
Value:
((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
                                                               SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
                                                               SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
                                                               SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
                                                               SMARTCARD_ADVFEATURE_SWAP_INIT              | \
                                                               SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
                                                               SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
                                                               SMARTCARD_ADVFEATURE_MSBFIRST_INIT))

Ensure that SMARTCARD advanced features initialization is valid.

Parameters:
__INIT__ SMARTCARD advanced features initialization.
Return values:
SET (__INIT__ is valid) or RESET (__INIT__ is invalid)

Definition at line 909 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_MSBFIRST ( __MSBFIRST__ )
Value:
(((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
                                                        ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))

Ensure that SMARTCARD frame MSB first setting is valid.

Parameters:
__MSBFIRST__ SMARTCARD frame MSB first setting.
Return values:
SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)

Definition at line 971 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_RXINV ( __RXINV__ )
Value:
(((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
                                                  ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))

Ensure that SMARTCARD frame RX inversion setting is valid.

Parameters:
__RXINV__ SMARTCARD frame RX inversion setting.
Return values:
SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)

Definition at line 931 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_SWAP ( __SWAP__ )
Value:
(((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
                                                ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))

Ensure that SMARTCARD frame RX/TX pins swap setting is valid.

Parameters:
__SWAP__ SMARTCARD frame RX/TX pins swap setting.
Return values:
SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)

Definition at line 947 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_TXINV ( __TXINV__ )
Value:
(((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
                                                  ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))

Ensure that SMARTCARD frame TX inversion setting is valid.

Parameters:
__TXINV__ SMARTCARD frame TX inversion setting.
Return values:
SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)

Definition at line 923 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_AUTORETRY_COUNT ( __COUNT__ ) ((__COUNT__) <= 0x7U)

Check the SMARTCARD autoretry counter value.

Note:
The maximum number of retransmissions is 0x7.
Parameters:
__COUNT__ number of retransmissions.
Return values:
Test result (TRUE or FALSE)

Definition at line 826 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 4500001U)

Check the Baud rate range.

Note:
The maximum Baud Rate is derived from the maximum clock on F3 (72 MHz) divided by the oversampling used on the SMARTCARD (i.e. 16).
Parameters:
__BAUDRATE__ Baud rate set by the configuration function.
Return values:
Test result (TRUE or FALSE)

Definition at line 805 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_BLOCKLENGTH ( __LENGTH__ ) ((__LENGTH__) <= 0xFFU)

Check the block length range.

Note:
The maximum SMARTCARD block length is 0xFF.
Parameters:
__LENGTH__ block length.
Return values:
Test result (TRUE or FALSE)

Definition at line 812 of file stm32f3xx_hal_smartcard.h.

#define IS_SMARTCARD_LASTBIT ( __LASTBIT__ )
Value:
(((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
                                           ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))

Ensure that SMARTCARD frame last bit clock pulse setting is valid.

Parameters:
__LASTBIT__ SMARTCARD frame last bit clock pulse setting.
Return values:
SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)

Definition at line 877 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_MODE ( __MODE__ ) ((((__MODE__) & (uint16_t)0xFFF3U) == 0x00U) && ((__MODE__) != (uint16_t)0x00U))

Ensure that SMARTCARD communication mode is valid.

Parameters:
__MODE__ SMARTCARD communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 856 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_NACK ( __NACK__ )
Value:
(((__NACK__) == SMARTCARD_NACK_ENABLE) || \
                                     ((__NACK__) == SMARTCARD_NACK_DISABLE))

Ensure that SMARTCARD NACK transmission setting is valid.

Parameters:
__NACK__ SMARTCARD NACK transmission setting.
Return values:
SET (__NACK__ is valid) or RESET (__NACK__ is invalid)

Definition at line 893 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
                                                 ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))

Ensure that SMARTCARD frame sampling is valid.

Parameters:
__ONEBIT__ SMARTCARD frame sampling.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 885 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_OVERRUN ( __OVERRUN__ )
Value:
(((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
                                           ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))

Ensure that SMARTCARD frame overrun setting is valid.

Parameters:
__OVERRUN__ SMARTCARD frame overrun setting.
Return values:
SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)

Definition at line 955 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
                                         ((__PARITY__) == SMARTCARD_PARITY_ODD))

Ensure that SMARTCARD frame parity is valid.

Parameters:
__PARITY__ SMARTCARD frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 848 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_PHASE ( __CPHA__ ) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))

Ensure that SMARTCARD frame phase is valid.

Parameters:
__CPHA__ SMARTCARD frame phase.
Return values:
SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)

Definition at line 870 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_POLARITY ( __CPOL__ ) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))

Ensure that SMARTCARD frame polarity is valid.

Parameters:
__CPOL__ SMARTCARD frame polarity.
Return values:
SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)

Definition at line 863 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
                                                   ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))

Ensure that SMARTCARD request parameter is valid.

Parameters:
__PARAM__ SMARTCARD request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 979 of file stm32f3xx_hal_smartcard.h.

#define IS_SMARTCARD_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
                                             ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))

Ensure that SMARTCARD frame number of stop bits is valid.

Parameters:
__STOPBITS__ SMARTCARD frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 840 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_TIMEOUT ( __TIMEOUT__ )
Value:
(((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
                                           ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))

Ensure that SMARTCARD receiver timeout setting is valid.

Parameters:
__TIMEOUT__ SMARTCARD receiver timeout setting.
Return values:
SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)

Definition at line 901 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_TIMEOUT_VALUE ( __TIMEOUTVALUE__ ) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)

Check the receiver timeout value.

Note:
The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
Parameters:
__TIMEOUTVALUE__ receiver timeout value.
Return values:
Test result (TRUE or FALSE)

Definition at line 819 of file stm32f3xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_TimeOut_Config(), and SMARTCARD_SetConfig().

#define IS_SMARTCARD_WORD_LENGTH ( __LENGTH__ ) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)

Ensure that SMARTCARD frame length is valid.

Parameters:
__LENGTH__ SMARTCARD frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 833 of file stm32f3xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
SMARTCARD Extended Exported Functions

Extended control functions. More...

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.

Detailed Description

Extended control functions.

  ===============================================================================
                      ##### Peripheral Control functions #####
  ===============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the SMARTCARD.
     (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
     (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
     (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
     (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature

Function Documentation

void HAL_SMARTCARDEx_BlockLength_Config | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t | BlockLength
 | ) |  |

Update on the fly the SMARTCARD block length in RTOR register.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
BlockLength | SMARTCARD block length (8-bit long at most)
Return values:
None

Definition at line 105 of file stm32f3xx_hal_smartcard_ex.c.

References SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_RTOR_BLEN_LSB_POS.

HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsmartcard )

Disable the SMARTCARD receiver timeout feature.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 162 of file stm32f3xx_hal_smartcard_ex.c.

References SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, and SMARTCARD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsmartcard )

Enable the SMARTCARD receiver timeout feature.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 130 of file stm32f3xx_hal_smartcard_ex.c.

References SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, and SMARTCARD_HandleTypeDef::Instance.

void HAL_SMARTCARDEx_TimeOut_Config | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | TimeOutValue
 | ) |  |

Update on the fly the receiver timeout value in RTOR register.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
TimeOutValue | receiver timeout value in number of baud blocks. The timeout value must be less or equal to 0x0FFFFFFFF.
Return values:
None

Definition at line 118 of file stm32f3xx_hal_smartcard_ex.c.

References assert_param, SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_TIMEOUT_VALUE, and SMARTCARD_InitTypeDef::TimeOutValue.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Extended Private Macros

Defines
SMARTCARD Extended Private Macros
SMARTCARDEx

Defines

#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the SMARTCARD clock source.

Define Documentation

#define SMARTCARD_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the SMARTCARD clock source.

Parameters:
__HANDLE__ | specifies the SMARTCARD Handle.
__CLOCKSOURCE__ | output variable.
Return values:
the SMARTCARD clocking source, written in __CLOCKSOURCE__.

Definition at line 107 of file stm32f3xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_SetConfig().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS Private Constants

Defines
SMBUS Private Constants
SMBUS

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFU)
#define | HAL_TIMEOUT_ADDR (10000U)
#define | HAL_TIMEOUT_BUSY (25U)
#define | HAL_TIMEOUT_DIR (25U)
#define | HAL_TIMEOUT_RXNE (25U)
#define | HAL_TIMEOUT_STOPF (25U)
#define | HAL_TIMEOUT_TC (25U)
#define | HAL_TIMEOUT_TCR (25U)
#define | HAL_TIMEOUT_TXIS (25U)
#define | MAX_NBYTE_SIZE 255U

Define Documentation

#define HAL_TIMEOUT_ADDR (10000U)

10 s

Definition at line 145 of file stm32f3xx_hal_smbus.c.

#define HAL_TIMEOUT_BUSY (25U)

25 ms

Definition at line 146 of file stm32f3xx_hal_smbus.c.

#define HAL_TIMEOUT_DIR (25U)

25 ms

Definition at line 147 of file stm32f3xx_hal_smbus.c.

#define HAL_TIMEOUT_RXNE (25U)

25 ms

Definition at line 148 of file stm32f3xx_hal_smbus.c.

#define HAL_TIMEOUT_STOPF (25U)

25 ms

Definition at line 149 of file stm32f3xx_hal_smbus.c.

#define HAL_TIMEOUT_TC (25U)

25 ms

Definition at line 150 of file stm32f3xx_hal_smbus.c.

#define HAL_TIMEOUT_TCR (25U)

25 ms

Definition at line 151 of file stm32f3xx_hal_smbus.c.

#define HAL_TIMEOUT_TXIS (25U)

25 ms

Definition at line 152 of file stm32f3xx_hal_smbus.c.

#define MAX_NBYTE_SIZE 255U

Definition at line 153 of file stm32f3xx_hal_smbus.c.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define TIMING_CLEAR_MASK (0xF0FFFFFFU)

SMBUS TIMING clear register Mask

Definition at line 144 of file stm32f3xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SMBUS Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_ConfigAnalogFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
Configure Analog noise filter.
HAL_StatusTypeDef | HAL_SMBUS_ConfigDigitalFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
Configure Digital noise filter.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          deinitialize the SMBUSx peripheral:

      (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, IT and NVIC ).

      (+) Call the function HAL_SMBUS_Init() to configure the selected device with
          the selected configuration:
        (++) Clock Timing
        (++) Bus Timeout
        (++) Analog Filer mode
        (++) Own Address 1
        (++) Addressing mode (Master, Slave)
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) Own Address 2 Mask
        (++) General call mode
        (++) Nostretch mode
        (++) Packet Error Check mode
        (++) Peripheral mode

      (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
          of the selected SMBUSx peripheral.

      (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
          HAL_SMBUS_ConfigDigitalFilter().

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | AnalogFilter
 | ) |  |

Configure Analog noise filter.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
AnalogFilter This parameter can be one of the following values:
  • SMBUS_ANALOGFILTER_ENABLE
  • SMBUS_ANALOGFILTER_DISABLE
Return values:
HAL status

Definition at line 404 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, assert_param, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, SMBUS_HandleTypeDef::Instance, IS_SMBUS_ANALOG_FILTER, and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure Digital noise filter.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DigitalFilter | Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
Return values:
HAL status

Definition at line 448 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, assert_param, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, SMBUS_HandleTypeDef::Instance, IS_SMBUS_DIGITAL_FILTER, and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_DeInit ( SMBUS_HandleTypeDef * hsmbus )

DeInitialize the SMBUS peripheral.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 334 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_MspDeInit(), HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_RESET, SMBUS_HandleTypeDef::Instance, SMBUS_HandleTypeDef::PreviousState, and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Init ( SMBUS_HandleTypeDef * hsmbus )

Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 232 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, SMBUS_InitTypeDef::AddressingMode, SMBUS_InitTypeDef::AnalogFilter, assert_param, SMBUS_InitTypeDef::DualAddressMode, SMBUS_HandleTypeDef::ErrorCode, SMBUS_InitTypeDef::GeneralCallMode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_MspInit(), HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_RESET, SMBUS_HandleTypeDef::Init, SMBUS_HandleTypeDef::Instance, IS_SMBUS_ADDRESSING_MODE, IS_SMBUS_ANALOG_FILTER, IS_SMBUS_DUAL_ADDRESS, IS_SMBUS_GENERAL_CALL, IS_SMBUS_NO_STRETCH, IS_SMBUS_OWN_ADDRESS1, IS_SMBUS_OWN_ADDRESS2, IS_SMBUS_OWN_ADDRESS2_MASK, IS_SMBUS_PEC, IS_SMBUS_PERIPHERAL_MODE, SMBUS_HandleTypeDef::Lock, SMBUS_InitTypeDef::NoStretchMode, SMBUS_InitTypeDef::OwnAddress1, SMBUS_InitTypeDef::OwnAddress2, SMBUS_InitTypeDef::OwnAddress2Masks, SMBUS_InitTypeDef::PacketErrorCheckMode, SMBUS_InitTypeDef::PeripheralMode, SMBUS_HandleTypeDef::PreviousState, SMBUS_ADDRESSINGMODE_10BIT, SMBUS_ADDRESSINGMODE_7BIT, SMBUS_PEC_ENABLE, SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE, SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP, SMBUS_InitTypeDef::SMBusTimeout, SMBUS_HandleTypeDef::State, SMBUS_InitTypeDef::Timing, and TIMING_CLEAR_MASK.

void HAL_SMBUS_MspDeInit ( SMBUS_HandleTypeDef * hsmbus )

DeInitialize the SMBUS MSP.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 385 of file stm32f3xx_hal_smbus.c.

Referenced by HAL_SMBUS_DeInit().

void HAL_SMBUS_MspInit ( SMBUS_HandleTypeDef * hsmbus )

Initialize the SMBUS MSP.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 369 of file stm32f3xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init().

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Blocking mode Polling

Functions
Blocking mode Polling
Input and Output operation functions

Functions

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Check if target device is ready for communication.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1039 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, SMBUS_InitTypeDef::AddressingMode, SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_TIMEOUT, SMBUS_HandleTypeDef::Init, SMBUS_HandleTypeDef::Instance, SMBUS_FLAG_AF, SMBUS_FLAG_BUSY, SMBUS_FLAG_STOPF, SMBUS_GENERATE_START, SMBUS_WaitOnFlagUntilTimeout(), and SMBUS_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Non-Blocking mode Interrupt

Functions
Non-Blocking mode Interrupt
Input and Output operation functions

Functions

HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1018 of file stm32f3xx_hal_smbus.c.

References SMBUS_HandleTypeDef::Instance, SMBUS_Disable_IRQ(), and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 975 of file stm32f3xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_Disable_IRQ(), SMBUS_IT_ADDR, and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 999 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, SMBUS_HandleTypeDef::Instance, SMBUS_Enable_IRQ(), SMBUS_FLAG_ALERT, and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 959 of file stm32f3xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, SMBUS_Enable_IRQ(), SMBUS_IT_ADDR, and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master/host SMBUS process communication with Interrupt.

Note:
This abort can be called only if state is ready
Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
Return values:
HAL status

Definition at line 728 of file stm32f3xx_hal_smbus.c.

References SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_TransferConfig(), and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 644 of file stm32f3xx_hal_smbus.c.

References assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_READ, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 551 of file stm32f3xx_hal_smbus.c.

References assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_WRITE, SMBUS_GET_PEC_MODE, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 882 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_RX, SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 789 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_TX, SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
SMBUS Exported Functions | Input and Output operation functions

Functions

void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.

Function Documentation

void HAL_SMBUS_AddrCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t | TransferDirection,
 |  | uint16_t | AddrMatchCode
 | ) |  |

Slave Address Match callback.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
TransferDirection | Master request Transfer Direction (Write/Read)
AddrMatchCode | Address Match Code
Return values:
None

Definition at line 1292 of file stm32f3xx_hal_smbus.c.

Referenced by SMBUS_Slave_ISR().

void HAL_SMBUS_ER_IRQHandler ( SMBUS_HandleTypeDef * hsmbus )

Handle SMBUS error interrupt request.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1216 of file stm32f3xx_hal_smbus.c.

References SMBUS_ITErrorHandler().

void HAL_SMBUS_ErrorCallback ( SMBUS_HandleTypeDef * hsmbus )

SMBUS error callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1326 of file stm32f3xx_hal_smbus.c.

Referenced by SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

void HAL_SMBUS_EV_IRQHandler ( SMBUS_HandleTypeDef * hsmbus )

Handle SMBUS event interrupt request.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1161 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_GET_IT_SOURCE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, SMBUS_CHECK_FLAG, SMBUS_FLAG_ADDR, SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TC, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_GET_ISR_REG, SMBUS_IT_ADDRI, SMBUS_IT_NACKI, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TXI, SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_HandleTypeDef::State.

void HAL_SMBUS_ListenCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Listen Complete callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1310 of file stm32f3xx_hal_smbus.c.

Referenced by SMBUS_Slave_ISR().

void HAL_SMBUS_MasterRxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Master Rx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1243 of file stm32f3xx_hal_smbus.c.

Referenced by SMBUS_Master_ISR().

void HAL_SMBUS_MasterTxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Master Tx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1227 of file stm32f3xx_hal_smbus.c.

Referenced by SMBUS_Master_ISR().

void HAL_SMBUS_SlaveRxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Slave Rx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1274 of file stm32f3xx_hal_smbus.c.

Referenced by SMBUS_Slave_ISR().

void HAL_SMBUS_SlaveTxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Slave Tx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1258 of file stm32f3xx_hal_smbus.c.

Referenced by SMBUS_Slave_ISR().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SMBUS Exported Functions | Input and Output operation functions

Peripheral State and Errors functions. More...

Functions

uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_SMBUS_GetError ( SMBUS_HandleTypeDef * hsmbus )

Return the SMBUS error code.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
SMBUS Error Code

Definition at line 1373 of file stm32f3xx_hal_smbus.c.

References SMBUS_HandleTypeDef::ErrorCode.

uint32_t HAL_SMBUS_GetState ( SMBUS_HandleTypeDef * hsmbus )

Return the SMBUS handle state.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL state

Definition at line 1361 of file stm32f3xx_hal_smbus.c.

References SMBUS_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Input and Output operation functions

Modules | Functions
Input and Output operation functions
SMBUS Exported Functions

Data transfers functions. More...

Modules

Blocking mode Polling
Non-Blocking mode Interrupt
IRQ Handler and Callbacks
Peripheral State and Errors functions

Peripheral State and Errors functions.

Functions

HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the SMBUS data
    transfers.

    (#) Blocking mode function to check if device is ready for usage is :
        (++) HAL_SMBUS_IsDeviceReady()

    (#) There is only one mode of transfer:
       (++) Non-Blocking mode : The communication is performed using Interrupts.
            These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated SMBUS IRQ when using Interrupt mode.

    (#) Non-Blocking mode functions with Interrupt are :
        (++) HAL_SMBUS_Master_Transmit_IT()
        (++) HAL_SMBUS_Master_Receive_IT()
        (++) HAL_SMBUS_Slave_Transmit_IT()
        (++) HAL_SMBUS_Slave_Receive_IT()
        (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
        (++) HAL_SMBUS_DisableListen_IT()
        (++) HAL_SMBUS_EnableAlert_IT()
        (++) HAL_SMBUS_DisableAlert_IT()

    (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
        (++) HAL_SMBUS_MasterTxCpltCallback()
        (++) HAL_SMBUS_MasterRxCpltCallback()
        (++) HAL_SMBUS_SlaveTxCpltCallback()
        (++) HAL_SMBUS_SlaveRxCpltCallback()
        (++) HAL_SMBUS_AddrCallback()
        (++) HAL_SMBUS_ListenCpltCallback()
        (++) HAL_SMBUS_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1018 of file stm32f3xx_hal_smbus.c.

References SMBUS_HandleTypeDef::Instance, SMBUS_Disable_IRQ(), and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 975 of file stm32f3xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_Disable_IRQ(), SMBUS_IT_ADDR, and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 999 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, SMBUS_HandleTypeDef::Instance, SMBUS_Enable_IRQ(), SMBUS_FLAG_ALERT, and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 959 of file stm32f3xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, SMBUS_Enable_IRQ(), SMBUS_IT_ADDR, and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Check if target device is ready for communication.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1039 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, SMBUS_InitTypeDef::AddressingMode, SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_TIMEOUT, SMBUS_HandleTypeDef::Init, SMBUS_HandleTypeDef::Instance, SMBUS_FLAG_AF, SMBUS_FLAG_BUSY, SMBUS_FLAG_STOPF, SMBUS_GENERATE_START, SMBUS_WaitOnFlagUntilTimeout(), and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master/host SMBUS process communication with Interrupt.

Note:
This abort can be called only if state is ready
Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
Return values:
HAL status

Definition at line 728 of file stm32f3xx_hal_smbus.c.

References SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_TransferConfig(), and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 644 of file stm32f3xx_hal_smbus.c.

References assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_READ, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 551 of file stm32f3xx_hal_smbus.c.

References assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_WRITE, SMBUS_GET_PEC_MODE, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 882 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_RX, SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 789 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_TX, SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS Private Functions

Functions
SMBUS Private Functions
SMBUS Exported Functions | SMBUS

Data transfers Private functions. More...

Functions

static HAL_StatusTypeDef | SMBUS_WaitOnFlagUntilTimeout (SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle SMBUS Communication Timeout.
static HAL_StatusTypeDef | SMBUS_Enable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static HAL_StatusTypeDef | SMBUS_Disable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static HAL_StatusTypeDef | SMBUS_Master_ISR (SMBUS_HandleTypeDef *hsmbus)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
static HAL_StatusTypeDef | SMBUS_Slave_ISR (SMBUS_HandleTypeDef *hsmbus)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
static void | SMBUS_ConvertOtherXferOptions (SMBUS_HandleTypeDef *hsmbus)
Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
static void | SMBUS_ITErrorHandler (SMBUS_HandleTypeDef *hsmbus)
SMBUS interrupts error handler.
static void | SMBUS_TransferConfig (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).

Detailed Description

Data transfers Private functions.

Function Documentation

static void SMBUS_ConvertOtherXferOptions ( SMBUS_HandleTypeDef * hsmbus ) [static]

Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.

Parameters:
hsmbus SMBUS handle.
Return values:
None

Definition at line 2126 of file stm32f3xx_hal_smbus.c.

References SMBUS_FIRST_AND_LAST_FRAME_NO_PEC, SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC, SMBUS_FIRST_FRAME, SMBUS_OTHER_AND_LAST_FRAME_NO_PEC, SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC, SMBUS_OTHER_FRAME_NO_PEC, SMBUS_OTHER_FRAME_WITH_PEC, SMBUS_SENDPEC_MODE, and SMBUS_HandleTypeDef::XferOptions.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

static HAL_StatusTypeDef SMBUS_Disable_IRQ | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the disabling of Interrupts.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
InterruptRequest | Value of SMBUS Interrupt configuration definition.
Return values:
HAL status

Definition at line 1868 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE_IT, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_GET_ALERT_ENABLED, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_ALERT, SMBUS_IT_ERRI, SMBUS_IT_NACKI, SMBUS_IT_RX, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TX, SMBUS_IT_TXI, and SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

static HAL_StatusTypeDef SMBUS_Enable_IRQ | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the enabling of Interrupts.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
InterruptRequest | Value of SMBUS Interrupt configuration definition.
Return values:
HAL status

Definition at line 1826 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_ENABLE_IT, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_ALERT, SMBUS_IT_ERRI, SMBUS_IT_NACKI, SMBUS_IT_RX, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TX, and SMBUS_IT_TXI.

Referenced by HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

static void SMBUS_ITErrorHandler ( SMBUS_HandleTypeDef * hsmbus ) [static]

SMBUS interrupts error handler.

Parameters:
hsmbus SMBUS handle.
Return values:
None

Definition at line 1941 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ERROR_ALERT, HAL_SMBUS_ERROR_ARLO, HAL_SMBUS_ERROR_BERR, HAL_SMBUS_ERROR_BUSTIMEOUT, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_ERROR_OVR, HAL_SMBUS_ERROR_PECERR, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, SMBUS_HandleTypeDef::Instance, SMBUS_HandleTypeDef::PreviousState, SMBUS_FLAG_ALERT, SMBUS_FLAG_ARLO, SMBUS_FLAG_BERR, SMBUS_FLAG_OVR, SMBUS_FLAG_PECERR, SMBUS_FLAG_TIMEOUT, SMBUS_IT_ERRI, and SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_ER_IRQHandler(), and SMBUS_Master_ISR().

static HAL_StatusTypeDef SMBUS_Master_ISR ( SMBUS_HandleTypeDef * hsmbus ) [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1397 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, __HAL_SMBUS_GET_FLAG, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_MasterRxCpltCallback(), HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, SMBUS_HandleTypeDef::Instance, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Disable_IRQ(), SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TC, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_GET_PEC_MODE, SMBUS_GET_STOP_MODE, SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_ITErrorHandler(), SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_RESET_CR2, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

Referenced by HAL_SMBUS_EV_IRQHandler().

static HAL_StatusTypeDef SMBUS_Slave_ISR ( SMBUS_HandleTypeDef * hsmbus ) [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1609 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_DISABLE_IT, __HAL_SMBUS_GET_FLAG, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_AddrCallback(), HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_ListenCpltCallback(), HAL_SMBUS_SlaveRxCpltCallback(), HAL_SMBUS_SlaveTxCpltCallback(), HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, SMBUS_HandleTypeDef::Instance, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_Disable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_GET_ADDR_MATCH, SMBUS_GET_DIR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_RESET_CR2, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

Referenced by HAL_SMBUS_EV_IRQHandler().

static void SMBUS_TransferConfig | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t | Size,
 |  | uint32_t | Mode,
 |  | uint32_t | Request
 | ) |  | [static]

Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).

Parameters:
hsmbus | SMBUS handle.
DevAddress | specifies the slave address to be programmed.
Size | specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
Mode New state of the SMBUS START condition generation. This parameter can be one or a combination of the following values:
  • SMBUS_RELOAD_MODE Enable Reload mode.
  • SMBUS_AUTOEND_MODE Enable Automatic end mode.
  • SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
  • SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
Request New state of the SMBUS START condition generation. This parameter can be one of the following values:
  • SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
  • SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
  • SMBUS_GENERATE_START_READ Generate Restart for read request.
  • SMBUS_GENERATE_START_WRITE Generate Restart for write request.
Return values:
None

Definition at line 2098 of file stm32f3xx_hal_smbus.c.

References assert_param, SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_MODE, and IS_SMBUS_TRANSFER_REQUEST.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SMBUS Communication Timeout.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Flag | Specifies the SMBUS flag to check.
Status | The new Flag status (SET or RESET).
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2030 of file stm32f3xx_hal_smbus.c.

References __HAL_SMBUS_GET_FLAG, HAL_GetTick(), HAL_SMBUS_STATE_READY, SMBUS_HandleTypeDef::PreviousState, and SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_IsDeviceReady().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMBUS_InitTypeDef Struct Reference
SMBUS Configuration Structure definition

#include <stm32f3xx_hal_smbus.h>

Data Fields

uint32_t | Timing
uint32_t | AnalogFilter
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | OwnAddress2Masks
uint32_t | GeneralCallMode
uint32_t | NoStretchMode
uint32_t | PacketErrorCheckMode
uint32_t | PeripheralMode
uint32_t | SMBusTimeout

Detailed Description

Definition at line 64 of file stm32f3xx_hal_smbus.h.

Field Documentation

uint32_t SMBUS_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode for master is selected. This parameter can be a value of SMBUS addressing mode

Definition at line 75 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

uint32_t SMBUS_InitTypeDef::AnalogFilter

Specifies if Analog Filter is enable or not. This parameter can be a value of SMBUS Analog Filter

Definition at line 69 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of SMBUS dual addressing mode

Definition at line 78 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of SMBUS general call addressing mode.

Definition at line 87 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of SMBUS nostretch mode

Definition at line 90 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 72 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 81 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress2Masks

Specifies the acknoledge mask address second device own address if dual addressing mode is selected This parameter can be a value of SMBUS ownaddress2 masks.

Definition at line 84 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::PacketErrorCheckMode

Specifies if Packet Error Check mode is selected. This parameter can be a value of SMBUS packet error check mode

Definition at line 93 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::PeripheralMode

Specifies which mode of Periphal is selected. This parameter can be a value of SMBUS peripheral mode

Definition at line 96 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::SMBusTimeout

Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. (Enable bits and different timeout values) This parameter calculated by referring to SMBUS initialization section in Reference manual

Definition at line 99 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::Timing

Specifies the SMBUS_TIMINGR_register value. This parameter calculated by referring to SMBUS initialization section in Reference manual

Definition at line 66 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_smbus.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HAL state definition

Defines
HAL state definition
SMBUS Exported Types

HAL State definition. More...

Defines

#define | HAL_SMBUS_STATE_RESET (0x00000000U)
#define | HAL_SMBUS_STATE_READY (0x00000001U)
#define | HAL_SMBUS_STATE_BUSY (0x00000002U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)
#define | HAL_SMBUS_STATE_TIMEOUT (0x00000003U)
#define | HAL_SMBUS_STATE_ERROR (0x00000004U)
#define | HAL_SMBUS_STATE_LISTEN (0x00000008U)

Detailed Description

HAL State definition.

Define Documentation

#define HAL_SMBUS_STATE_BUSY (0x00000002U)

SMBUS internal process is ongoing

Definition at line 114 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

#define HAL_SMBUS_STATE_ERROR (0x00000004U)

Reception process is ongoing

Definition at line 120 of file stm32f3xx_hal_smbus.h.

#define HAL_SMBUS_STATE_LISTEN (0x00000008U)

Address Listen Mode is ongoing

Definition at line 121 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_ITErrorHandler(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)

Master Data Reception process is ongoing

Definition at line 116 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), and SMBUS_Master_ISR().

#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)

Master Data Transmission process is ongoing

Definition at line 115 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Transmit_IT(), and SMBUS_Master_ISR().

#define HAL_SMBUS_STATE_READY (0x00000001U)

SMBUS initialized and ready for use

Definition at line 113 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

#define HAL_SMBUS_STATE_RESET (0x00000000U)

SMBUS not yet initialized or disabled

Definition at line 112 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), and HAL_SMBUS_Init().

#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)

Slave Data Reception process is ongoing

Definition at line 118 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), SMBUS_ITErrorHandler(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)

Slave Data Transmission process is ongoing

Definition at line 117 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ITErrorHandler(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U)

Timeout state

Definition at line 119 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS Error Code definition

Defines
SMBUS Error Code definition
SMBUS Exported Types

SMBUS Error Code definition. More...

Defines

#define | HAL_SMBUS_ERROR_NONE (0x00000000U)
#define | HAL_SMBUS_ERROR_BERR (0x00000001U)
#define | HAL_SMBUS_ERROR_ARLO (0x00000002U)
#define | HAL_SMBUS_ERROR_ACKF (0x00000004U)
#define | HAL_SMBUS_ERROR_OVR (0x00000008U)
#define | HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)
#define | HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)
#define | HAL_SMBUS_ERROR_ALERT (0x00000040U)
#define | HAL_SMBUS_ERROR_PECERR (0x00000080U)

Detailed Description

SMBUS Error Code definition.

Define Documentation

#define HAL_SMBUS_ERROR_ACKF (0x00000004U)

ACKF error

Definition at line 133 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_ERROR_ALERT (0x00000040U)

Alert error

Definition at line 137 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_ARLO (0x00000002U)

ARLO error

Definition at line 132 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_BERR (0x00000001U)

BERR error

Definition at line 131 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)

Bus Timeout error

Definition at line 136 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)

Timeout error

Definition at line 135 of file stm32f3xx_hal_smbus.h.

#define HAL_SMBUS_ERROR_NONE (0x00000000U)

No error

Definition at line 130 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), and SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_OVR (0x00000008U)

OVR error

Definition at line 134 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_PECERR (0x00000080U)

PEC error

Definition at line 138 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMBUS_HandleTypeDef Struct Reference
SMBUS handle Structure definition

#include <stm32f3xx_hal_smbus.h>

Data Fields

I2C_TypeDef * | Instance
SMBUS_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
__IO uint32_t | XferOptions
__IO uint32_t | PreviousState
HAL_LockTypeDef | Lock
__IO uint32_t | State
__IO uint32_t | ErrorCode

Detailed Description

Definition at line 147 of file stm32f3xx_hal_smbus.h.

Field Documentation

__IO uint32_t SMBUS_HandleTypeDef::ErrorCode

SMBUS Error code

Definition at line 167 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_GetError(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

SMBUS_InitTypeDef SMBUS_HandleTypeDef::Init

SMBUS communication parameters

Definition at line 151 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

I2C_TypeDef* SMBUS_HandleTypeDef::Instance

SMBUS registers base address

Definition at line 149 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_TransferConfig().

HAL_LockTypeDef SMBUS_HandleTypeDef::Lock

SMBUS locking object

Definition at line 163 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint8_t* SMBUS_HandleTypeDef::pBuffPtr

Pointer to SMBUS transfer buffer

Definition at line 153 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t SMBUS_HandleTypeDef::PreviousState

SMBUS communication Previous state

Definition at line 161 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

__IO uint32_t SMBUS_HandleTypeDef::State

SMBUS communication state

Definition at line 165 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_GetState(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

__IO uint16_t SMBUS_HandleTypeDef::XferCount

SMBUS transfer counter

Definition at line 157 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t SMBUS_HandleTypeDef::XferOptions

SMBUS transfer options

Definition at line 159 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ConvertOtherXferOptions(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

uint16_t SMBUS_HandleTypeDef::XferSize

SMBUS transfer size

Definition at line 155 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_smbus.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS Analog Filter

Defines
SMBUS Analog Filter
SMBUS Exported Constants

Defines

#define | SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
#define | SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Definition at line 187 of file stm32f3xx_hal_smbus.h.

#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)

Definition at line 186 of file stm32f3xx_hal_smbus.h.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS addressing mode

Defines
SMBUS addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
#define | SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)

Define Documentation

#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)

Definition at line 196 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)

Definition at line 195 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS dual addressing mode

Defines
SMBUS dual addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_DUALADDRESS_DISABLE (0x00000000U)
#define | SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Define Documentation

#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)

Definition at line 205 of file stm32f3xx_hal_smbus.h.

#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Definition at line 206 of file stm32f3xx_hal_smbus.h.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS ownaddress2 masks

Defines
SMBUS ownaddress2 masks
SMBUS Exported Constants

Defines

#define | SMBUS_OA2_NOMASK ((uint8_t)0x00U)
#define | SMBUS_OA2_MASK01 ((uint8_t)0x01U)
#define | SMBUS_OA2_MASK02 ((uint8_t)0x02U)
#define | SMBUS_OA2_MASK03 ((uint8_t)0x03U)
#define | SMBUS_OA2_MASK04 ((uint8_t)0x04U)
#define | SMBUS_OA2_MASK05 ((uint8_t)0x05U)
#define | SMBUS_OA2_MASK06 ((uint8_t)0x06U)
#define | SMBUS_OA2_MASK07 ((uint8_t)0x07U)

Define Documentation

#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)

Definition at line 216 of file stm32f3xx_hal_smbus.h.

#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)

Definition at line 217 of file stm32f3xx_hal_smbus.h.

#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)

Definition at line 218 of file stm32f3xx_hal_smbus.h.

#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)

Definition at line 219 of file stm32f3xx_hal_smbus.h.

#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)

Definition at line 220 of file stm32f3xx_hal_smbus.h.

#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)

Definition at line 221 of file stm32f3xx_hal_smbus.h.

#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)

Definition at line 222 of file stm32f3xx_hal_smbus.h.

#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)

Definition at line 215 of file stm32f3xx_hal_smbus.h.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS general call addressing mode

Defines
SMBUS general call addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_GENERALCALL_DISABLE (0x00000000U)
#define | SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN

Define Documentation

#define SMBUS_GENERALCALL_DISABLE (0x00000000U)

Definition at line 231 of file stm32f3xx_hal_smbus.h.

#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN

Definition at line 232 of file stm32f3xx_hal_smbus.h.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS nostretch mode

Defines
SMBUS nostretch mode
SMBUS Exported Constants

Defines

#define | SMBUS_NOSTRETCH_DISABLE (0x00000000U)
#define | SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Define Documentation

#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)

Definition at line 240 of file stm32f3xx_hal_smbus.h.

#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Definition at line 241 of file stm32f3xx_hal_smbus.h.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS packet error check mode

Defines
SMBUS packet error check mode
SMBUS Exported Constants

Defines

#define | SMBUS_PEC_DISABLE (0x00000000U)
#define | SMBUS_PEC_ENABLE I2C_CR1_PECEN

Define Documentation

#define SMBUS_PEC_DISABLE (0x00000000U)

Definition at line 249 of file stm32f3xx_hal_smbus.h.

#define SMBUS_PEC_ENABLE I2C_CR1_PECEN

Definition at line 250 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS peripheral mode

Defines
SMBUS peripheral mode
SMBUS Exported Constants

Defines

#define | SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN

Define Documentation

#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN

Definition at line 258 of file stm32f3xx_hal_smbus.h.

#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)

Definition at line 259 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN

Definition at line 260 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS ReloadEndMode definition

Defines
SMBUS ReloadEndMode definition
SMBUS Exported Constants

Defines

#define | SMBUS_SOFTEND_MODE (0x00000000U)
#define | SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define | SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define | SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE

Define Documentation

#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND

Definition at line 271 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), and SMBUS_Master_ISR().

#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD

Definition at line 270 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE

Definition at line 272 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ConvertOtherXferOptions(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_SOFTEND_MODE (0x00000000U)

Definition at line 269 of file stm32f3xx_hal_smbus.h.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS StartStopMode definition

Defines
SMBUS StartStopMode definition
SMBUS Exported Constants

Defines

#define | SMBUS_NO_STARTSTOP (0x00000000U)
#define | SMBUS_GENERATE_STOP I2C_CR2_STOP
#define | SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | SMBUS_GENERATE_START_WRITE I2C_CR2_START

Define Documentation

#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)

Definition at line 283 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT().

#define SMBUS_GENERATE_START_WRITE I2C_CR2_START

Definition at line 284 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT().

#define SMBUS_GENERATE_STOP I2C_CR2_STOP

Definition at line 282 of file stm32f3xx_hal_smbus.h.

#define SMBUS_NO_STARTSTOP (0x00000000U)

Definition at line 281 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS XferOptions definition

Defines
SMBUS XferOptions definition
SMBUS Exported Constants

Defines

#define | SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
#define | SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
#define | SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
#define | SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
#define | SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)

Define Documentation

#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE

Definition at line 299 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))

Definition at line 301 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE

Definition at line 297 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE

Definition at line 300 of file stm32f3xx_hal_smbus.h.

#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))

Definition at line 302 of file stm32f3xx_hal_smbus.h.

#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))

Definition at line 298 of file stm32f3xx_hal_smbus.h.

#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)

Definition at line 309 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)

Definition at line 310 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)

Definition at line 307 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)

Definition at line 308 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS Interrupt configuration definition

Defines
SMBUS Interrupt configuration definition
SMBUS Exported Constants

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | SMBUS_IT_ERRI I2C_CR1_ERRIE
#define | SMBUS_IT_TCI I2C_CR1_TCIE
#define | SMBUS_IT_STOPI I2C_CR1_STOPIE
#define | SMBUS_IT_NACKI I2C_CR1_NACKIE
#define | SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define | SMBUS_IT_RXI I2C_CR1_RXIE
#define | SMBUS_IT_TXI I2C_CR1_TXIE
#define | SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
#define | SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
#define | SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define | SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)

Detailed Description

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)

Definition at line 331 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_Slave_ISR().

#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE

Definition at line 325 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_Slave_ISR().

#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)

Definition at line 330 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_EnableAlert_IT(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_ERRI I2C_CR1_ERRIE

Definition at line 321 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_ITErrorHandler().

#define SMBUS_IT_NACKI I2C_CR1_NACKIE

Definition at line 324 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)

Definition at line 329 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Slave_Receive_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_IT_RXI I2C_CR1_RXIE

Definition at line 326 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_STOPI I2C_CR1_STOPIE

Definition at line 323 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_TCI I2C_CR1_TCIE

Definition at line 322 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)

Definition at line 328 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_IT_TXI I2C_CR1_TXIE

Definition at line 327 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS Flag definition

Defines
SMBUS Flag definition
SMBUS Exported Constants

Flag definition Elements values convention: 0xXXXXYYYY. More...

Defines

#define | SMBUS_FLAG_TXE I2C_ISR_TXE
#define | SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define | SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define | SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define | SMBUS_FLAG_AF I2C_ISR_NACKF
#define | SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define | SMBUS_FLAG_TC I2C_ISR_TC
#define | SMBUS_FLAG_TCR I2C_ISR_TCR
#define | SMBUS_FLAG_BERR I2C_ISR_BERR
#define | SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define | SMBUS_FLAG_OVR I2C_ISR_OVR
#define | SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define | SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define | SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define | SMBUS_FLAG_DIR I2C_ISR_DIR

Detailed Description

Flag definition Elements values convention: 0xXXXXYYYY.

  • XXXXXXXX : Flag mask

Define Documentation

#define SMBUS_FLAG_ADDR I2C_ISR_ADDR

Definition at line 346 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_AF I2C_ISR_NACKF

Definition at line 347 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_IsDeviceReady(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_ALERT I2C_ISR_ALERT

Definition at line 356 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EnableAlert_IT(), and SMBUS_ITErrorHandler().

#define SMBUS_FLAG_ARLO I2C_ISR_ARLO

Definition at line 352 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_BERR I2C_ISR_BERR

Definition at line 351 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_BUSY I2C_ISR_BUSY

Definition at line 357 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady().

#define SMBUS_FLAG_DIR I2C_ISR_DIR

Definition at line 358 of file stm32f3xx_hal_smbus.h.

#define SMBUS_FLAG_OVR I2C_ISR_OVR

Definition at line 353 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_PECERR I2C_ISR_PECERR

Definition at line 354 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_RXNE I2C_ISR_RXNE

Definition at line 345 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_STOPF I2C_ISR_STOPF

Definition at line 348 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_IsDeviceReady(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_TC I2C_ISR_TC

Definition at line 349 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), and SMBUS_Master_ISR().

#define SMBUS_FLAG_TCR I2C_ISR_TCR

Definition at line 350 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT

Definition at line 355 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_TXE I2C_ISR_TXE

Definition at line 343 of file stm32f3xx_hal_smbus.h.

#define SMBUS_FLAG_TXIS I2C_ISR_TXIS

Definition at line 344 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS Exported Macros

Defines
SMBUS Exported Macros
SMBUS

Defines

#define | __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
Reset SMBUS handle state.
#define | __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified SMBUS interrupts.
#define | __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified SMBUS interrupts.
#define | __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SMBUS interrupt source is enabled or not.
#define | SMBUS_FLAG_MASK (0x0001FFFFU)
Check whether the specified SMBUS flag is set or not.
#define | __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
#define | __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified SMBUS peripheral.
#define | __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified SMBUS peripheral.
#define | __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge SMBUS peripheral in Slave mode.

Define Documentation

#define __HAL_SMBUS_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • SMBUS_FLAG_ADDR Address matched (slave mode)
  • SMBUS_FLAG_AF NACK received flag
  • SMBUS_FLAG_STOPF STOP detection flag
  • SMBUS_FLAG_BERR Bus error
  • SMBUS_FLAG_ARLO Arbitration lost
  • SMBUS_FLAG_OVR Overrun/Underrun
  • SMBUS_FLAG_PECERR PEC error in reception
  • SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
  • SMBUS_FLAG_ALERT SMBus alert
Return values:
None

Definition at line 468 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define __HAL_SMBUS_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Disable the specified SMBUS peripheral.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 480 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), and SMBUS_Master_ISR().

#define __HAL_SMBUS_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

Disable the specified SMBUS interrupts.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__INTERRUPT__ specifies the interrupt source to disable. This parameter can be one of the following values:
  • SMBUS_IT_ERRI Errors interrupt enable
  • SMBUS_IT_TCI Transfer complete interrupt enable
  • SMBUS_IT_STOPI STOP detection interrupt enable
  • SMBUS_IT_NACKI NACK received interrupt enable
  • SMBUS_IT_ADDRI Address match interrupt enable
  • SMBUS_IT_RXI RX interrupt enable
  • SMBUS_IT_TXI TX interrupt enable
Return values:
None

Definition at line 408 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ(), and SMBUS_Slave_ISR().

#define __HAL_SMBUS_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Enable the specified SMBUS peripheral.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 474 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_Init(), and SMBUS_Master_ISR().

#define __HAL_SMBUS_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

Enable the specified SMBUS interrupts.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__INTERRUPT__ specifies the interrupt source to enable. This parameter can be one of the following values:
  • SMBUS_IT_ERRI Errors interrupt enable
  • SMBUS_IT_TCI Transfer complete interrupt enable
  • SMBUS_IT_STOPI STOP detection interrupt enable
  • SMBUS_IT_NACKI NACK received interrupt enable
  • SMBUS_IT_ADDRI Address match interrupt enable
  • SMBUS_IT_RXI RX interrupt enable
  • SMBUS_IT_TXI TX interrupt enable
Return values:
None

Definition at line 392 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_Enable_IRQ().

#define __HAL_SMBUS_GENERATE_NACK ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

Generate a Non-Acknowledge SMBUS peripheral in Slave mode.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 486 of file stm32f3xx_hal_smbus.h.

#define __HAL_SMBUS_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))

Definition at line 450 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

#define __HAL_SMBUS_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SMBUS interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__INTERRUPT__ specifies the SMBUS interrupt source to check. This parameter can be one of the following values:
  • SMBUS_IT_ERRI Errors interrupt enable
  • SMBUS_IT_TCI Transfer complete interrupt enable
  • SMBUS_IT_STOPI STOP detection interrupt enable
  • SMBUS_IT_NACKI NACK received interrupt enable
  • SMBUS_IT_ADDRI Address match interrupt enable
  • SMBUS_IT_RXI RX interrupt enable
  • SMBUS_IT_TXI TX interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 424 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler().

#define __HAL_SMBUS_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)

Reset SMBUS handle state.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 376 of file stm32f3xx_hal_smbus.h.

#define SMBUS_FLAG_MASK (0x0001FFFFU)

Check whether the specified SMBUS flag is set or not.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SMBUS_FLAG_TXE Transmit data register empty
  • SMBUS_FLAG_TXIS Transmit interrupt status
  • SMBUS_FLAG_RXNE Receive data register not empty
  • SMBUS_FLAG_ADDR Address matched (slave mode)
  • SMBUS_FLAG_AF NACK received flag
  • SMBUS_FLAG_STOPF STOP detection flag
  • SMBUS_FLAG_TC Transfer complete (master mode)
  • SMBUS_FLAG_TCR Transfer complete reload
  • SMBUS_FLAG_BERR Bus error
  • SMBUS_FLAG_ARLO Arbitration lost
  • SMBUS_FLAG_OVR Overrun/Underrun
  • SMBUS_FLAG_PECERR PEC error in reception
  • SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
  • SMBUS_FLAG_ALERT SMBus alert
  • SMBUS_FLAG_BUSY Bus busy
  • SMBUS_FLAG_DIR Transfer direction (slave mode)
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 449 of file stm32f3xx_hal_smbus.h.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS Private Macros

Defines
SMBUS Private Macros
SMBUS

Defines

#define | IS_SMBUS_ANALOG_FILTER(FILTER)
#define | IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_SMBUS_ADDRESSING_MODE(MODE)
#define | IS_SMBUS_DUAL_ADDRESS(ADDRESS)
#define | IS_SMBUS_OWN_ADDRESS2_MASK(MASK)
#define | IS_SMBUS_GENERAL_CALL(CALL)
#define | IS_SMBUS_NO_STRETCH(STRETCH)
#define | IS_SMBUS_PEC(PEC)
#define | IS_SMBUS_PERIPHERAL_MODE(MODE)
#define | IS_SMBUS_TRANSFER_MODE(MODE)
#define | IS_SMBUS_TRANSFER_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
#define | SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | SMBUS_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
#define | SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define | SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define | SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define | SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
#define | SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
#define | IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)

Define Documentation

#define IS_SMBUS_ADDRESSING_MODE ( MODE )
Value:
(((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
                                                          ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))

Definition at line 505 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_ANALOG_FILTER ( FILTER )
Value:
(((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
                                                          ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))

Definition at line 500 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), and HAL_SMBUS_Init().

#define IS_SMBUS_DIGITAL_FILTER ( FILTER ) ((FILTER) <= 0x0000000FU)

Definition at line 503 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigDigitalFilter().

#define IS_SMBUS_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
                                                          ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))

Definition at line 508 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_GENERAL_CALL ( CALL )
Value:
(((CALL) == SMBUS_GENERALCALL_DISABLE) || \
                                                         ((CALL) == SMBUS_GENERALCALL_ENABLE))

Definition at line 520 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
                                                         ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))

Definition at line 523 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= 0x000003FFU)

Definition at line 577 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS2 ( ADDRESS2 ) ((ADDRESS2) <= (uint16_t)0x00FFU)

Definition at line 578 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS2_MASK ( MASK )
Value:
(((MASK) == SMBUS_OA2_NOMASK)    || \
                                                         ((MASK) == SMBUS_OA2_MASK01)    || \
                                                         ((MASK) == SMBUS_OA2_MASK02)    || \
                                                         ((MASK) == SMBUS_OA2_MASK03)    || \
                                                         ((MASK) == SMBUS_OA2_MASK04)    || \
                                                         ((MASK) == SMBUS_OA2_MASK05)    || \
                                                         ((MASK) == SMBUS_OA2_MASK06)    || \
                                                         ((MASK) == SMBUS_OA2_MASK07))

Definition at line 511 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_PEC ( PEC )
Value:
(((PEC) == SMBUS_PEC_DISABLE) || \
                                                          ((PEC) == SMBUS_PEC_ENABLE))

Definition at line 526 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_PERIPHERAL_MODE ( MODE )
Value:
(((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)    || \
                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))

Definition at line 529 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_TRANSFER_MODE ( MODE )
Value:
(((MODE) == SMBUS_RELOAD_MODE)                           || \
                                                          ((MODE) == SMBUS_AUTOEND_MODE)                         || \
                                                          ((MODE) == SMBUS_SOFTEND_MODE)                         || \
                                                          ((MODE) == SMBUS_SENDPEC_MODE)                         || \
                                                          ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))

Definition at line 533 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_TransferConfig().

#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == SMBUS_FIRST_FRAME)                        || \
                                                          ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
                                                          ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
                                                          ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)               || \
                                                          IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))

Definition at line 549 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)                || \
                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)       || \
                                                          ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)              || \
                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))

Definition at line 557 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), and HAL_SMBUS_Master_Transmit_IT().

#define IS_SMBUS_TRANSFER_REQUEST ( REQUEST )
Value:
(((REQUEST) == SMBUS_GENERATE_STOP)              || \
                                                          ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
                                                          ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
                                                          ((REQUEST) == SMBUS_NO_STARTSTOP))

Definition at line 543 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_TransferConfig().

#define SMBUS_CHECK_FLAG | ( | __ISR__,
 |  | __FLAG__
 | ) | ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))

Definition at line 575 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler().

#define SMBUS_GENERATE_START | ( | __ADDMODE__,
 |  | __ADDRESS__
 | ) |
Value:
(((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
                                                                  (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

Definition at line 565 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady().

#define SMBUS_GET_ADDR_MATCH ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)

Definition at line 568 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_Slave_ISR().

#define SMBUS_GET_ALERT_ENABLED ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)

Definition at line 572 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ().

#define SMBUS_GET_DIR ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)

Definition at line 569 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_Slave_ISR().

#define SMBUS_GET_ISR_REG ( __HANDLE__ ) ((__HANDLE__)->Instance->ISR)

Definition at line 574 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler().

#define SMBUS_GET_PEC_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)

Definition at line 571 of file stm32f3xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_GET_STOP_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)

Definition at line 570 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_Master_ISR().

#define SMBUS_RESET_CR1 ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))

Definition at line 562 of file stm32f3xx_hal_smbus.h.

#define SMBUS_RESET_CR2 ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))

Definition at line 563 of file stm32f3xx_hal_smbus.h.

Referenced by SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Private Constants

Defines
SPI Private Constants
SPI

Defines

#define SPI_DEFAULT_TIMEOUT 100U

Define Documentation

#define SPI_DEFAULT_TIMEOUT 100U

Definition at line 175 of file stm32f3xx_hal_spi.c.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Private Functions

Functions
SPI Private Functions
SPI

Private functions. More...

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static void | SPI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SPI_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SPI_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static HAL_StatusTypeDef | SPI_WaitFifoStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI FIFO Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_RxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 8-bit receive in Interrupt context.
static void | SPI_RxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
static void | SPI_AbortRx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Rx transaction.
static void | SPI_AbortTx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Tx or Rx/Tx transaction.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.
static HAL_StatusTypeDef | SPI_EndRxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RX transaction complete.
static HAL_StatusTypeDef | SPI_EndRxTxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RXTX or TX transaction complete.

Detailed Description

Private functions.

Function Documentation

static void SPI_2linesRxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3188 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_2linesRxISR_16BITCRC(), SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesRxISR_16BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3222 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, SPI_CloseRxTx_ISR(), and SPI_IT_RXNE.

Referenced by SPI_2linesRxISR_16BIT().

static void SPI_2linesRxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3060 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_2linesRxISR_8BITCRC(), SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_ERR, SPI_IT_RXNE, SPI_RXFIFO_THRESHOLD, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesRxISR_8BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3110 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::CRCSize, __SPI_HandleTypeDef::Instance, SPI_CloseRxTx_ISR(), SPI_IT_ERR, SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by SPI_2linesRxISR_8BIT().

static void SPI_2linesTxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3246 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesTxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3142 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_AbortRx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle abort a Rx transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3768 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_ABORT, HAL_SPI_STATE_ABORT, __SPI_HandleTypeDef::Instance, SPI_DEFAULT_TIMEOUT, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), and HAL_SPI_Abort_IT().

static void SPI_AbortTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle abort a Tx or Rx/Tx transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3812 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_ABORT, HAL_SPI_STATE_ABORT, __SPI_HandleTypeDef::Instance, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), and HAL_SPI_Abort_IT().

static void SPI_CloseRx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the RX transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3687 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, SPI_DEFAULT_TIMEOUT, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_IT_ERR, SPI_IT_RXNE, and __SPI_HandleTypeDef::State.

Referenced by SPI_RxISR_16BIT(), SPI_RxISR_16BITCRC(), SPI_RxISR_8BIT(), and SPI_RxISR_8BITCRC().

static void SPI_CloseRxTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the RXTX transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3630 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_IT_ERR, and __SPI_HandleTypeDef::State.

Referenced by SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), and SPI_2linesTxISR_8BIT().

static void SPI_CloseTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the TX transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3729 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_IT_ERR, SPI_IT_TXE, and __SPI_HandleTypeDef::State.

Referenced by SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

static void SPI_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2920 of file stm32f3xx_hal_spi.c.

References HAL_SPI_ErrorCallback(), __SPI_HandleTypeDef::RxXferCount, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_IRQHandler().

static void SPI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI communication error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2902 of file stm32f3xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_DMA, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2876 of file stm32f3xx_hal_spi.c.

References HAL_SPI_RxHalfCpltCallback().

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2863 of file stm32f3xx_hal_spi.c.

References HAL_SPI_TxHalfCpltCallback().

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMAHalfTransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2889 of file stm32f3xx_hal_spi.c.

References HAL_SPI_TxRxHalfCpltCallback().

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2687 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DEFAULT_TIMEOUT, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_IT_ERR, SPI_WaitFlagStateUntilTimeout(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2999 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_DEFAULT_TIMEOUT, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SPI_Abort_IT().

static void SPI_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2640 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_IT_ERR, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMATransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2778 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_CRC_LENGTH_8BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_FRLVL_QUARTER_FULL, SPI_IT_ERR, SPI_WaitFifoStateUntilTimeout(), __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2937 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SPI_Abort_IT().

static HAL_StatusTypeDef SPI_EndRxTransaction | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle the check of the RX transaction complete.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Timeout | Timeout duration
Tickstart | tick start value
Return values:
HAL status

Definition at line 3563 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_DISABLE, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, __SPI_HandleTypeDef::Init, SPI_InitTypeDef::Mode, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_MODE_MASTER, SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Referenced by HAL_SPI_Receive(), SPI_CloseRx_ISR(), and SPI_DMAReceiveCplt().

static HAL_StatusTypeDef SPI_EndRxTxTransaction | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle the check of the RXTX or TX transaction complete.

Parameters:
hspi | SPI handle
Timeout | Timeout duration
Tickstart | tick start value
Return values:
HAL status

Definition at line 3599 of file stm32f3xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FLAG_FTLVL, SPI_FRLVL_EMPTY, SPI_FTLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Referenced by HAL_SPI_Abort(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_AbortTx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

static void SPI_RxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the 16-bit receive in Interrupt context.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3365 of file stm32f3xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRx_ISR(), SPI_CRCCALCULATION_ENABLE, and SPI_RxISR_16BITCRC().

Referenced by HAL_SPI_Receive_IT().

static void SPI_RxISR_16BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 16-bit receive in Interrupt context.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3342 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, SPI_CloseRx_ISR(), SPI_IT_ERR, and SPI_IT_RXNE.

Referenced by SPI_RxISR_16BIT().

static void SPI_RxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the receive 8-bit in Interrupt context.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3309 of file stm32f3xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRx_ISR(), SPI_CRCCALCULATION_ENABLE, and SPI_RxISR_8BITCRC().

Referenced by HAL_SPI_Receive_IT().

static void SPI_RxISR_8BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 8-bit receive in Interrupt context.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3284 of file stm32f3xx_hal_spi.c.

References __SPI_HandleTypeDef::CRCSize, __SPI_HandleTypeDef::Instance, and SPI_CloseRx_ISR().

Referenced by SPI_RxISR_8BIT().

static void SPI_TxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 16-bit transmit in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3422 of file stm32f3xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), SPI_CRCCALCULATION_ENABLE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static void SPI_TxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 8-bit transmit in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3398 of file stm32f3xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), SPI_CRCCALCULATION_ENABLE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Fifo,
 |  | uint32_t | State,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle SPI FIFO Communication Timeout.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Fifo | Fifo to check
State | Fifo state to check
Timeout | Timeout duration
Tickstart | tick start value
Return values:
HAL status

Definition at line 3504 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, HAL_GetTick(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_FRLVL_EMPTY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Flag,
 |  | uint32_t | State,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle SPI Communication Timeout.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Flag | SPI flag to check
State | flag state to check
Timeout | Timeout duration
Tickstart | tick start value
Return values:
HAL status

Definition at line 3452 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, HAL_GetTick(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, SPI_InitTypeDef::Mode, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_AbortRx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the SPIx peripheral:

      (+) User must implement HAL_SPI_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_SPI_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Direction
        (++) Data Size
        (++) Clock Polarity and Phase
        (++) NSS Management
        (++) BaudRate Prescaler
        (++) FirstBit
        (++) TIMode
        (++) CRC Calculation
        (++) CRC Polynomial if CRC enabled
        (++) CRC Length, used only with Data8 and Data16
        (++) FIFO reception threshold

      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
          of the selected SPIx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SPI_DeInit ( SPI_HandleTypeDef * hspi )

De-Initialize the SPI peripheral.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 397 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_DISABLE, assert_param, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_MspDeInit(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_RESET, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPI_Init ( SPI_HandleTypeDef * hspi )

Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 272 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_DISABLE, assert_param, SPI_InitTypeDef::BaudRatePrescaler, SPI_InitTypeDef::CLKPhase, SPI_InitTypeDef::CLKPolarity, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::CRCPolynomial, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, SPI_InitTypeDef::FirstBit, HAL_SPI_ERROR_NONE, HAL_SPI_MspInit(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_BAUDRATE_PRESCALER, IS_SPI_CPHA, IS_SPI_CPOL, IS_SPI_CRC_CALCULATION, IS_SPI_CRC_LENGTH, IS_SPI_CRC_POLYNOMIAL, IS_SPI_DATASIZE, IS_SPI_DIRECTION, IS_SPI_FIRST_BIT, IS_SPI_MODE, IS_SPI_NSS, IS_SPI_NSSP, IS_SPI_TIMODE, __SPI_HandleTypeDef::Lock, SPI_InitTypeDef::Mode, SPI_InitTypeDef::NSS, SPI_InitTypeDef::NSSPMode, SPI_CRC_LENGTH_16BIT, SPI_CRC_LENGTH_8BIT, SPI_CRC_LENGTH_DATASIZE, SPI_CRCCALCULATION_DISABLE, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_RXFIFO_THRESHOLD_HF, SPI_RXFIFO_THRESHOLD_QF, SPI_TIMODE_DISABLE, __SPI_HandleTypeDef::State, and SPI_InitTypeDef::TIMode.

void HAL_SPI_MspDeInit ( SPI_HandleTypeDef * hspi )

De-Initialize the SPI MSP.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 447 of file stm32f3xx_hal_spi.c.

Referenced by HAL_SPI_DeInit().

void HAL_SPI_MspInit ( SPI_HandleTypeDef * hspi )

Initialize the SPI MSP.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 431 of file stm32f3xx_hal_spi.c.

Referenced by HAL_SPI_Init().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IO operation functions

Functions
IO operation functions
SPI Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]
    This subsection provides a set of functions allowing to manage the SPI
    data transfers.

    [..] The SPI supports master and slave mode :

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode: The communication is performed using Interrupts
            or DMA, These APIs return the HAL status.
            The end of the data processing will be indicated through the
            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.
            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
            will be executed respectively at the end of the transmit or Receive process
            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected

    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
        exist for 1Line (simplex) and 2Lines (full duplex) modes.

Function Documentation

HAL_StatusTypeDef HAL_SPI_Abort ( SPI_HandleTypeDef * hspi )

Abort ongoing transfer (blocking mode).

Parameters:
hspi SPI handle.
Note:
This procedure could be used for aborting any ongoing transfer (Tx and Rx), started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SPI Interrupts (depending of transfer direction)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1943 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_GetTick(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_ABORT, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SPI_Abort_IT ( SPI_HandleTypeDef * hspi )

Abort ongoing transfer (Interrupt mode).

Parameters:
hspi SPI handle.
Note:
This procedure could be used for aborting any ongoing transfer (Tx and Rx), started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SPI Interrupts (depending of transfer direction)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 2097 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_ABORT, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DEFAULT_TIMEOUT, SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SPI_AbortCpltCallback ( SPI_HandleTypeDef * hspi )

SPI Abort Complete callback.

Parameters:
hspi SPI handle.
Return values:
None

Definition at line 2568 of file stm32f3xx_hal_spi.c.

Referenced by HAL_SPI_Abort_IT(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

HAL_StatusTypeDef HAL_SPI_DMAPause ( SPI_HandleTypeDef * hspi )

Pause the DMA Transfer.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 2287 of file stm32f3xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAResume ( SPI_HandleTypeDef * hspi )

Resume the DMA Transfer.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 2307 of file stm32f3xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAStop ( SPI_HandleTypeDef * hspi )

Stop the DMA Transfer.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 2327 of file stm32f3xx_hal_spi.c.

References HAL_DMA_Abort(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

void HAL_SPI_ErrorCallback ( SPI_HandleTypeDef * hspi )

SPI error callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2550 of file stm32f3xx_hal_spi.c.

Referenced by HAL_SPI_IRQHandler(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAAbortOnError(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_IRQHandler ( SPI_HandleTypeDef * hspi )

Handle SPI interrupt request.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
None

Definition at line 2358 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_MODFFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SPI_ERROR_FRE, HAL_SPI_ERROR_MODF, HAL_SPI_ERROR_NONE, HAL_SPI_ERROR_OVR, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, SPI_DMAAbortOnError(), SPI_FLAG_FRE, SPI_FLAG_MODF, SPI_FLAG_OVR, SPI_FLAG_RXNE, SPI_FLAG_TXE, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SPI_Receive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be received
Timeout | Timeout duration
Return values:
HAL status

Definition at line 683 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Receive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Note:
In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Note:
When the CRC feature is enabled the pData Length must be Size + 1.
Parameters:
Size amount of data to be sent
Return values:
HAL status

Definition at line 1618 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_DMA(), __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DMA_HANDLE, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAReceiveCplt(), SPI_IT_ERR, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Receive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be sent
Return values:
HAL status

Definition at line 1290 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, __SPI_HandleTypeDef::CRCSize, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_IT(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_RXNE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

void HAL_SPI_RxCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2470 of file stm32f3xx_hal_spi.c.

Referenced by SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), and SPI_DMAReceiveCplt().

void HAL_SPI_RxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Half Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2518 of file stm32f3xx_hal_spi.c.

Referenced by SPI_DMAHalfReceiveCplt().

HAL_StatusTypeDef HAL_SPI_Transmit | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 503 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_FLAG_TXE, SPI_MODE_SLAVE, SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Transmit_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be sent
Return values:
HAL status

Definition at line 1504 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, IS_SPI_DMA_HANDLE, DMA_InitTypeDef::MemDataAlignment, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DMAError(), SPI_DMAHalfTransmitCplt(), SPI_DMATransmitCplt(), SPI_IT_ERR, SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Transmit_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be sent
Return values:
HAL status

Definition at line 1206 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_IT_ERR, SPI_IT_TXE, SPI_RESET_CRC, SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_TransmitReceive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit and Receive an amount of data in blocking mode.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData | pointer to transmission data buffer
pRxData | pointer to reception data buffer
Size | amount of data to be sent and received
Timeout | Timeout duration
Return values:
HAL status

Definition at line 915 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_FLAG_TXE, SPI_MODE_MASTER, SPI_MODE_SLAVE, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with DMA.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData | pointer to transmission data buffer
pRxData | pointer to reception data buffer
Note:
When the CRC feature is enabled the pRxData Length must be Size + 1
Parameters:
Size amount of data to be sent
Return values:
HAL status

Definition at line 1761 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, IS_SPI_DMA_HANDLE, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAHalfTransmitReceiveCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_IT_ERR, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_SPI_Receive_DMA().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData | pointer to transmission data buffer
pRxData | pointer to reception data buffer
Size | amount of data to be sent and received
Return values:
HAL status

Definition at line 1396 of file stm32f3xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, __SPI_HandleTypeDef::CRCSize, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive_IT().

void HAL_SPI_TxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2454 of file stm32f3xx_hal_spi.c.

Referenced by SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

void HAL_SPI_TxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Half Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2502 of file stm32f3xx_hal_spi.c.

Referenced by SPI_DMAHalfTransmitCplt().

void HAL_SPI_TxRxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2486 of file stm32f3xx_hal_spi.c.

Referenced by SPI_CloseRxTx_ISR(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_TxRxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Half Transfer callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2534 of file stm32f3xx_hal_spi.c.

Referenced by SPI_DMAHalfTransmitReceiveCplt().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SPI Exported Functions

SPI control functions. More...

Functions

HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI control functions.

 ===============================================================================
                      ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SPI.
     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication

Function Documentation

uint32_t HAL_SPI_GetError ( SPI_HandleTypeDef * hspi )

Return the SPI error code.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI error code in bitmap format

Definition at line 2615 of file stm32f3xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode.

HAL_SPI_StateTypeDef HAL_SPI_GetState ( SPI_HandleTypeDef * hspi )

Return the SPI handle state.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI state

Definition at line 2603 of file stm32f3xx_hal_spi.c.

References __SPI_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Exported Types

Data Structures | Typedefs | Enumerations
SPI Exported Types
SPI

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00U, HAL_SPI_STATE_READY = 0x01U, HAL_SPI_STATE_BUSY = 0x02U, HAL_SPI_STATE_BUSY_TX = 0x03U,
HAL_SPI_STATE_BUSY_RX = 0x04U, HAL_SPI_STATE_BUSY_TX_RX = 0x05U, HAL_SPI_STATE_ERROR = 0x06U, HAL_SPI_STATE_ABORT = 0x07U
}
HAL SPI State structure definition. More...

Typedef Documentation

typedef struct __SPI_HandleTypeDef SPI_HandleTypeDef

SPI handle Structure definition.

Enumeration Type Documentation

enum HAL_SPI_StateTypeDef

HAL SPI State structure definition.

Enumerator:
HAL_SPI_STATE_RESET

Peripheral not Initialized

HAL_SPI_STATE_READY

Peripheral Initialized and ready for use

HAL_SPI_STATE_BUSY

an internal process is ongoing

HAL_SPI_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_SPI_STATE_BUSY_RX

Data Reception process is ongoing

HAL_SPI_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_SPI_STATE_ERROR

SPI error state

HAL_SPI_STATE_ABORT

SPI abort is ongoing

Definition at line 117 of file stm32f3xx_hal_spi.h.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPI_InitTypeDef Struct Reference
SPI Exported Types

SPI Configuration Structure definition. More...

#include <stm32f3xx_hal_spi.h>

Data Fields

uint32_t | Mode
uint32_t | Direction
uint32_t | DataSize
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | NSS
uint32_t | BaudRatePrescaler
uint32_t | FirstBit
uint32_t | TIMode
uint32_t | CRCCalculation
uint32_t | CRCPolynomial
uint32_t | CRCLength
uint32_t | NSSPMode

Detailed Description

SPI Configuration Structure definition.

Definition at line 63 of file stm32f3xx_hal_spi.h.

Field Documentation

uint32_t SPI_InitTypeDef::BaudRatePrescaler

Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of SPI BaudRate Prescaler

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

Definition at line 84 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of SPI Clock Phase

Definition at line 77 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPolarity

Specifies the serial clock steady state. This parameter can be a value of SPI Clock Polarity

Definition at line 74 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of SPI CRC Calculation

Definition at line 96 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::CRCLength

Specifies the CRC Length used for the CRC calculation. CRC Length is only used with Data8 and Data16, not other data size This parameter can be a value of SPI CRC Length

Definition at line 102 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

uint32_t SPI_InitTypeDef::CRCPolynomial

Specifies the polynomial used for the CRC calculation. This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535

Definition at line 99 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::DataSize

Specifies the SPI data size. This parameter can be a value of SPI Data Size

Definition at line 71 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

uint32_t SPI_InitTypeDef::Direction

Specifies the SPI bidirectional mode state. This parameter can be a value of SPI Direction Mode

Definition at line 68 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseTx_ISR(), SPI_DMATransmitCplt(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SPI MSB LSB Transmission

Definition at line 90 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::Mode

Specifies the SPI operating mode. This parameter can be a value of SPI Mode

Definition at line 65 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of SPI Slave Select Management

Definition at line 80 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::NSSPMode

Specifies whether the NSSP signal is enabled or not . This parameter can be a value of SPI NSS Pulse Mode This mode is activated by the NSSP bit in the SPIx_CR2 register and it takes effect only if the SPI interface is configured as Motorola SPI master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, CPOL setting is ignored)..

Definition at line 106 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::TIMode

Specifies if the TI mode is enabled or not. This parameter can be a value of SPI TI Mode

Definition at line 93 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_spi.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: __SPI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SPI_HandleTypeDef Struct Reference
SPI Exported Types

SPI handle Structure definition. More...

#include <stm32f3xx_hal_spi.h>

Data Fields

SPI_TypeDef * | Instance
SPI_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint32_t | CRCSize
void(* | RxISR )(struct __SPI_HandleTypeDef *hspi)
void(* | TxISR )(struct __SPI_HandleTypeDef *hspi)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SPI_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

SPI handle Structure definition.

Definition at line 132 of file stm32f3xx_hal_spi.h.

Field Documentation

uint32_t __SPI_HandleTypeDef::CRCSize

SPI CRC size used for the transfer

Definition at line 150 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_8BITCRC(), and SPI_RxISR_8BITCRC().

__IO uint32_t __SPI_HandleTypeDef::ErrorCode

SPI Error code

Definition at line 164 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_GetError(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmarx

SPI Rx DMA Handle parameters

Definition at line 158 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DMAStop(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_TransmitReceive_DMA(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmatx

SPI Tx DMA Handle parameters

Definition at line 156 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DMAStop(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

SPI_InitTypeDef __SPI_HandleTypeDef::Init

SPI communication parameters

Definition at line 136 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_EndRxTransaction(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

SPI_TypeDef* __SPI_HandleTypeDef::Instance

SPI registers base address

Definition at line 134 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_DMAPause(), HAL_SPI_DMAResume(), HAL_SPI_DMAStop(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPIEx_FlushRxFifo(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_RxISR_16BIT(), SPI_RxISR_16BITCRC(), SPI_RxISR_8BIT(), SPI_RxISR_8BITCRC(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), and SPI_WaitFifoStateUntilTimeout().

HAL_LockTypeDef __SPI_HandleTypeDef::Lock

Locking object

Definition at line 160 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint8_t* __SPI_HandleTypeDef::pRxBuffPtr

Pointer to SPI Rx transfer Buffer

Definition at line 144 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint8_t* __SPI_HandleTypeDef::pTxBuffPtr

Pointer to SPI Tx transfer Buffer

Definition at line 138 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

void(* __SPI_HandleTypeDef::RxISR)(struct __SPI_HandleTypeDef *hspi)

function pointer on Rx ISR

Definition at line 152 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

__IO uint16_t __SPI_HandleTypeDef::RxXferCount

SPI Rx Transfer Counter

Definition at line 148 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAAbortOnError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint16_t __SPI_HandleTypeDef::RxXferSize

SPI Rx Transfer size

Definition at line 146 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

__IO HAL_SPI_StateTypeDef __SPI_HandleTypeDef::State

SPI communication state

Definition at line 162 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_DMAStop(), HAL_SPI_GetState(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

void(* __SPI_HandleTypeDef::TxISR)(struct __SPI_HandleTypeDef *hspi)

function pointer on Tx ISR

Definition at line 154 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

__IO uint16_t __SPI_HandleTypeDef::TxXferCount

SPI Tx Transfer Counter

Definition at line 142 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAAbortOnError(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

uint16_t __SPI_HandleTypeDef::TxXferSize

SPI Tx Transfer size

Definition at line 140 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_spi.h
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Error Code

Defines
SPI Error Code
SPI Exported Constants

Defines

#define | HAL_SPI_ERROR_NONE (0x00000000U)
#define | HAL_SPI_ERROR_MODF (0x00000001U)
#define | HAL_SPI_ERROR_CRC (0x00000002U)
#define | HAL_SPI_ERROR_OVR (0x00000004U)
#define | HAL_SPI_ERROR_FRE (0x00000008U)
#define | HAL_SPI_ERROR_DMA (0x00000010U)
#define | HAL_SPI_ERROR_FLAG (0x00000020U)
#define | HAL_SPI_ERROR_ABORT (0x00000040U)

Define Documentation

#define HAL_SPI_ERROR_ABORT (0x00000040U)

Error during SPI Abort procedure

Definition at line 187 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

#define HAL_SPI_ERROR_CRC (0x00000002U)

CRC error

Definition at line 182 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define HAL_SPI_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 185 of file stm32f3xx_hal_spi.h.

Referenced by SPI_DMAError().

#define HAL_SPI_ERROR_FLAG (0x00000020U)

Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag

Definition at line 186 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define HAL_SPI_ERROR_FRE (0x00000008U)

FRE error

Definition at line 184 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_MODF (0x00000001U)

MODF error

Definition at line 181 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_NONE (0x00000000U)

No error

Definition at line 180 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

#define HAL_SPI_ERROR_OVR (0x00000004U)

OVR error

Definition at line 183 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Mode

Defines
SPI Mode
SPI Exported Constants

Defines

#define | SPI_MODE_SLAVE (0x00000000U)
#define | SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Define Documentation

#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Definition at line 196 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_MODE_SLAVE (0x00000000U)

Definition at line 195 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Direction Mode

Defines
SPI Direction Mode
SPI Exported Constants

Defines

#define | SPI_DIRECTION_2LINES (0x00000000U)
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define | SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE

Define Documentation

#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE

Definition at line 206 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_DIRECTION_2LINES (0x00000000U)

Definition at line 204 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY

Definition at line 205 of file stm32f3xx_hal_spi.h.

Referenced by SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Data Size

Defines
SPI Data Size
SPI Exported Constants

Defines

#define | SPI_DATASIZE_4BIT (0x00000300U)
#define | SPI_DATASIZE_5BIT (0x00000400U)
#define | SPI_DATASIZE_6BIT (0x00000500U)
#define | SPI_DATASIZE_7BIT (0x00000600U)
#define | SPI_DATASIZE_8BIT (0x00000700U)
#define | SPI_DATASIZE_9BIT (0x00000800U)
#define | SPI_DATASIZE_10BIT (0x00000900U)
#define | SPI_DATASIZE_11BIT (0x00000A00U)
#define | SPI_DATASIZE_12BIT (0x00000B00U)
#define | SPI_DATASIZE_13BIT (0x00000C00U)
#define | SPI_DATASIZE_14BIT (0x00000D00U)
#define | SPI_DATASIZE_15BIT (0x00000E00U)
#define | SPI_DATASIZE_16BIT (0x00000F00U)

Define Documentation

#define SPI_DATASIZE_10BIT (0x00000900U)

Definition at line 220 of file stm32f3xx_hal_spi.h.

#define SPI_DATASIZE_11BIT (0x00000A00U)

Definition at line 221 of file stm32f3xx_hal_spi.h.

#define SPI_DATASIZE_12BIT (0x00000B00U)

Definition at line 222 of file stm32f3xx_hal_spi.h.

#define SPI_DATASIZE_13BIT (0x00000C00U)

Definition at line 223 of file stm32f3xx_hal_spi.h.

#define SPI_DATASIZE_14BIT (0x00000D00U)

Definition at line 224 of file stm32f3xx_hal_spi.h.

#define SPI_DATASIZE_15BIT (0x00000E00U)

Definition at line 225 of file stm32f3xx_hal_spi.h.

#define SPI_DATASIZE_16BIT (0x00000F00U)

Definition at line 226 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), and HAL_SPI_TransmitReceive().

#define SPI_DATASIZE_4BIT (0x00000300U)

Definition at line 214 of file stm32f3xx_hal_spi.h.

#define SPI_DATASIZE_5BIT (0x00000400U)

Definition at line 215 of file stm32f3xx_hal_spi.h.

#define SPI_DATASIZE_6BIT (0x00000500U)

Definition at line 216 of file stm32f3xx_hal_spi.h.

#define SPI_DATASIZE_7BIT (0x00000600U)

Definition at line 217 of file stm32f3xx_hal_spi.h.

#define SPI_DATASIZE_8BIT (0x00000700U)

Definition at line 218 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_DATASIZE_9BIT (0x00000800U)

Definition at line 219 of file stm32f3xx_hal_spi.h.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Clock Polarity

Defines
SPI Clock Polarity
SPI Exported Constants

Defines

#define | SPI_POLARITY_LOW (0x00000000U)
#define | SPI_POLARITY_HIGH SPI_CR1_CPOL

Define Documentation

#define SPI_POLARITY_HIGH SPI_CR1_CPOL

Definition at line 235 of file stm32f3xx_hal_spi.h.

#define SPI_POLARITY_LOW (0x00000000U)

Definition at line 234 of file stm32f3xx_hal_spi.h.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Clock Phase

Defines
SPI Clock Phase
SPI Exported Constants

Defines

#define | SPI_PHASE_1EDGE (0x00000000U)
#define | SPI_PHASE_2EDGE SPI_CR1_CPHA

Define Documentation

#define SPI_PHASE_1EDGE (0x00000000U)

Definition at line 243 of file stm32f3xx_hal_spi.h.

#define SPI_PHASE_2EDGE SPI_CR1_CPHA

Definition at line 244 of file stm32f3xx_hal_spi.h.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Slave Select Management

Defines
SPI Slave Select Management
SPI Exported Constants

Defines

#define | SPI_NSS_SOFT SPI_CR1_SSM
#define | SPI_NSS_HARD_INPUT (0x00000000U)
#define | SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)

Define Documentation

#define SPI_NSS_HARD_INPUT (0x00000000U)

Definition at line 253 of file stm32f3xx_hal_spi.h.

#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)

Definition at line 254 of file stm32f3xx_hal_spi.h.

#define SPI_NSS_SOFT SPI_CR1_SSM

Definition at line 252 of file stm32f3xx_hal_spi.h.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI NSS Pulse Mode

Defines
SPI NSS Pulse Mode
SPI Exported Constants

Defines

#define | SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
#define | SPI_NSS_PULSE_DISABLE (0x00000000U)

Define Documentation

#define SPI_NSS_PULSE_DISABLE (0x00000000U)

Definition at line 263 of file stm32f3xx_hal_spi.h.

#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP

Definition at line 262 of file stm32f3xx_hal_spi.h.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI BaudRate Prescaler

Defines
SPI BaudRate Prescaler
SPI Exported Constants

Defines

#define | SPI_BAUDRATEPRESCALER_2 (0x00000000U)
#define | SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
#define | SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

Define Documentation

#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)

Definition at line 277 of file stm32f3xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)

Definition at line 274 of file stm32f3xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)

Definition at line 271 of file stm32f3xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

Definition at line 278 of file stm32f3xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)

Definition at line 275 of file stm32f3xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)

Definition at line 272 of file stm32f3xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)

Definition at line 276 of file stm32f3xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)

Definition at line 273 of file stm32f3xx_hal_spi.h.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI MSB LSB Transmission

Defines
SPI MSB LSB Transmission
SPI Exported Constants

Defines

#define | SPI_FIRSTBIT_MSB (0x00000000U)
#define | SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST

Define Documentation

#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST

Definition at line 287 of file stm32f3xx_hal_spi.h.

#define SPI_FIRSTBIT_MSB (0x00000000U)

Definition at line 286 of file stm32f3xx_hal_spi.h.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI TI Mode

Defines
SPI TI Mode
SPI Exported Constants

Defines

#define | SPI_TIMODE_DISABLE (0x00000000U)
#define | SPI_TIMODE_ENABLE SPI_CR2_FRF

Define Documentation

#define SPI_TIMODE_DISABLE (0x00000000U)

Definition at line 295 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_TIMODE_ENABLE SPI_CR2_FRF

Definition at line 296 of file stm32f3xx_hal_spi.h.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI CRC Calculation

Defines
SPI CRC Calculation
SPI Exported Constants

Defines

#define | SPI_CRCCALCULATION_DISABLE (0x00000000U)
#define | SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN

Define Documentation

#define SPI_CRCCALCULATION_DISABLE (0x00000000U)

Definition at line 304 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN

Definition at line 305 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI CRC Length

Defines
SPI CRC Length
SPI Exported Constants

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit. More...

Defines

#define | SPI_CRC_LENGTH_DATASIZE (0x00000000U)
#define | SPI_CRC_LENGTH_8BIT (0x00000001U)
#define | SPI_CRC_LENGTH_16BIT (0x00000002U)

Detailed Description

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit.

Define Documentation

#define SPI_CRC_LENGTH_16BIT (0x00000002U)

Definition at line 319 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT(), and SPI_DMAReceiveCplt().

#define SPI_CRC_LENGTH_8BIT (0x00000001U)

Definition at line 318 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init(), and SPI_DMATransmitReceiveCplt().

#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)

Definition at line 317 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI FIFO Reception Threshold

Defines
SPI FIFO Reception Threshold
SPI Exported Constants

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/2(16-bits). More...

Defines

#define | SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_HF (0x00000000U)

Detailed Description

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/2(16-bits).

SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO level is greater or equal to 1/4(8 bits).

Define Documentation

#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH

Definition at line 332 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), and SPI_2linesRxISR_8BIT().

#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)

Definition at line 334 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH

Definition at line 333 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Interrupt Definition

Defines
SPI Interrupt Definition
SPI Exported Constants

Defines

#define | SPI_IT_TXE SPI_CR2_TXEIE
#define | SPI_IT_RXNE SPI_CR2_RXNEIE
#define | SPI_IT_ERR SPI_CR2_ERRIE

Define Documentation

#define SPI_IT_ERR SPI_CR2_ERRIE

Definition at line 345 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_RXNE SPI_CR2_RXNEIE

Definition at line 344 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_CloseRx_ISR(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_TXE SPI_CR2_TXEIE

Definition at line 343 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseTx_ISR(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Flags Definition

Defines
SPI Flags Definition
SPI Exported Constants

Defines

#define | SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define | SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define | SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
#define | SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */

Define Documentation

#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */

Definition at line 355 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), SPI_AbortRx_ISR(), SPI_DMARxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */

Definition at line 356 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */

Definition at line 359 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */

Definition at line 361 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPIEx_FlushRxFifo(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */

Definition at line 360 of file stm32f3xx_hal_spi.h.

Referenced by SPI_EndRxTxTransaction().

#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */

Definition at line 357 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */

Definition at line 358 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */

Definition at line 353 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), and SPI_DMAReceiveCplt().

#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */

Definition at line 354 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Transmission FIFO Status Level

Defines
SPI Transmission FIFO Status Level
SPI Exported Constants

Defines

#define | SPI_FTLVL_EMPTY (0x00000000U)
#define | SPI_FTLVL_QUARTER_FULL (0x00000800U)
#define | SPI_FTLVL_HALF_FULL (0x00001000U)
#define | SPI_FTLVL_FULL (0x00001800U)

Define Documentation

#define SPI_FTLVL_EMPTY (0x00000000U)

Definition at line 369 of file stm32f3xx_hal_spi.h.

Referenced by SPI_EndRxTxTransaction().

#define SPI_FTLVL_FULL (0x00001800U)

Definition at line 372 of file stm32f3xx_hal_spi.h.

#define SPI_FTLVL_HALF_FULL (0x00001000U)

Definition at line 371 of file stm32f3xx_hal_spi.h.

#define SPI_FTLVL_QUARTER_FULL (0x00000800U)

Definition at line 370 of file stm32f3xx_hal_spi.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Reception FIFO Status Level

Defines
SPI Reception FIFO Status Level
SPI Exported Constants

Defines

#define | SPI_FRLVL_EMPTY (0x00000000U)
#define | SPI_FRLVL_QUARTER_FULL (0x00000200U)
#define | SPI_FRLVL_HALF_FULL (0x00000400U)
#define | SPI_FRLVL_FULL (0x00000600U)

Define Documentation

#define SPI_FRLVL_EMPTY (0x00000000U)

Definition at line 381 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPIEx_FlushRxFifo(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), SPI_EndRxTxTransaction(), and SPI_WaitFifoStateUntilTimeout().

#define SPI_FRLVL_FULL (0x00000600U)

Definition at line 384 of file stm32f3xx_hal_spi.h.

#define SPI_FRLVL_HALF_FULL (0x00000400U)

Definition at line 383 of file stm32f3xx_hal_spi.h.

Referenced by SPI_DMATransmitReceiveCplt().

#define SPI_FRLVL_QUARTER_FULL (0x00000200U)

Definition at line 382 of file stm32f3xx_hal_spi.h.

Referenced by SPI_DMATransmitReceiveCplt().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Exported Macros

Defines
SPI Exported Macros
SPI

Defines

#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Enable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Disable the specified SPI interrupts.
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)
Clear the SPI FRE pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Disable the SPI peripheral.

Define Documentation

#define __HAL_SPI_CLEAR_CRCERRFLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))

Clear the SPI CRCERR pending flag.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 464 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define __HAL_SPI_CLEAR_FREFLAG ( __HANDLE__ )
Value:
do{                                              \
  __IO uint32_t tmpreg_fre = 0x00U;                \
  tmpreg_fre = (__HANDLE__)->Instance->SR;         \
  UNUSED(tmpreg_fre);                              \
  }while(0U)

Clear the SPI FRE pending flag.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 497 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

#define __HAL_SPI_CLEAR_MODFFLAG ( __HANDLE__ )
Value:
do{                                                    \
    __IO uint32_t tmpreg_modf = 0x00U;                   \
    tmpreg_modf = (__HANDLE__)->Instance->SR;            \
    CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
    UNUSED(tmpreg_modf);                                 \
  } while(0U)

Clear the SPI MODF pending flag.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 471 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define __HAL_SPI_CLEAR_OVRFLAG ( __HANDLE__ )
Value:
do{                                              \
    __IO uint32_t tmpreg_ovr = 0x00U;              \
    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
    UNUSED(tmpreg_ovr);                            \
  } while(0U)

Clear the SPI OVR pending flag.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 484 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), SPI_CloseTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), and SPI_DMATxAbortCallback().

#define __HAL_SPI_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)

Disable the SPI peripheral.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 516 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_DeInit(), HAL_SPI_Init(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))

Disable the specified SPI interrupts.

Parameters:
__HANDLE__ specifies the SPI handle. This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__ specifies the interrupt source to disable. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 427 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)

Enable the SPI peripheral.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 509 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define __HAL_SPI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))

Enable the specified SPI interrupts.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__ specifies the interrupt source to enable. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 415 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define __HAL_SPI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Check whether the specified SPI flag is set or not.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SPI_FLAG_RXNE: Receive buffer not empty flag
  • SPI_FLAG_TXE: Transmit buffer empty flag
  • SPI_FLAG_CRCERR: CRC error flag
  • SPI_FLAG_MODF: Mode fault flag
  • SPI_FLAG_OVR: Overrun flag
  • SPI_FLAG_BSY: Busy flag
  • SPI_FLAG_FRE: Frame format error flag
  • SPI_FLAG_FTLVL: SPI fifo transmission level
  • SPI_FLAG_FRLVL: SPI fifo reception level
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 457 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SPI interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__ specifies the SPI interrupt source to check. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 439 of file stm32f3xx_hal_spi.h.

#define __HAL_SPI_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)

Reset SPI handle state.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 403 of file stm32f3xx_hal_spi.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Private Macros

Defines
SPI Private Macros
SPI

Defines

#define | SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Set the SPI receive-only mode.
#define | SPI_RESET_CRC(__HANDLE__)
Reset the CRC calculation of the SPI.
#define | IS_SPI_MODE(MODE)
#define | IS_SPI_DIRECTION(MODE)
#define | IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE)
#define | IS_SPI_DATASIZE(DATASIZE)
#define | IS_SPI_CPOL(CPOL)
#define | IS_SPI_CPHA(CPHA)
#define | IS_SPI_NSS(NSS)
#define | IS_SPI_NSSP(NSSP)
#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | IS_SPI_FIRST_BIT(BIT)
#define | IS_SPI_TIMODE(MODE)
#define | IS_SPI_CRC_CALCULATION(CALCULATION)
#define | IS_SPI_CRC_LENGTH(LENGTH)
#define | IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
#define | IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL)

Define Documentation

#define IS_SPI_BAUDRATE_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))

Definition at line 588 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPHA ( CPHA )
Value:
(((CPHA) == SPI_PHASE_1EDGE) || \
                           ((CPHA) == SPI_PHASE_2EDGE))

Definition at line 578 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPOL ( CPOL )
Value:
(((CPOL) == SPI_POLARITY_LOW) || \
                           ((CPOL) == SPI_POLARITY_HIGH))

Definition at line 575 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_CALCULATION ( CALCULATION )
Value:
(((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))

Definition at line 603 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_LENGTH ( LENGTH )
Value:
(((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_8BIT)  ||   \
                                   ((LENGTH) == SPI_CRC_LENGTH_16BIT))

Definition at line 606 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_POLYNOMIAL ( POLYNOMIAL ) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))

Definition at line 610 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SPI_DATASIZE_16BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_15BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_14BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_13BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_12BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_11BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_10BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_4BIT))

Definition at line 561 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION ( MODE )
Value:
(((MODE) == SPI_DIRECTION_2LINES)        || \
                                ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
                                ((MODE) == SPI_DIRECTION_1LINE))

Definition at line 552 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION_2LINES ( MODE ) ((MODE) == SPI_DIRECTION_2LINES)

Definition at line 556 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define IS_SPI_DIRECTION_2LINES_OR_1LINE ( MODE )
Value:
(((MODE) == SPI_DIRECTION_2LINES) || \
                                                ((MODE) == SPI_DIRECTION_1LINE))

Definition at line 558 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define IS_SPI_DMA_HANDLE ( HANDLE ) ((HANDLE) != NULL)

Definition at line 612 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

#define IS_SPI_FIRST_BIT ( BIT )
Value:
(((BIT) == SPI_FIRSTBIT_MSB) || \
                               ((BIT) == SPI_FIRSTBIT_LSB))

Definition at line 597 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_MODE ( MODE )
Value:
(((MODE) == SPI_MODE_SLAVE) || \
                           ((MODE) == SPI_MODE_MASTER))

Definition at line 549 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSS ( NSS )
Value:
(((NSS) == SPI_NSS_SOFT)       || \
                         ((NSS) == SPI_NSS_HARD_INPUT) || \
                         ((NSS) == SPI_NSS_HARD_OUTPUT))

Definition at line 581 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSSP ( NSSP )
Value:
(((NSSP) == SPI_NSS_PULSE_ENABLE) || \
                           ((NSSP) == SPI_NSS_PULSE_DISABLE))

Definition at line 585 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_TIMODE ( MODE )
Value:
(((MODE) == SPI_TIMODE_DISABLE) || \
                             ((MODE) == SPI_TIMODE_ENABLE))

Definition at line 600 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_1LINE_RX ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)

Set the SPI receive-only mode.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 539 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), and HAL_SPI_Receive_IT().

#define SPI_1LINE_TX ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)

Set the SPI transmit-only mode.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 532 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define SPI_RESET_CRC ( __HANDLE__ )
Value:
do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
                                       SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)

Reset the CRC calculation of the SPI.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 546 of file stm32f3xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPIEx Private Constants

Defines
SPIEx Private Constants
SPIEx

Defines

#define SPI_FIFO_SIZE 4

Define Documentation

#define SPI_FIFO_SIZE 4

Definition at line 58 of file stm32f3xx_hal_spi_ex.c.

Referenced by HAL_SPIEx_FlushRxFifo().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IO operation functions

Functions
IO operation functions
SPIEx Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]
    This subsection provides a set of extended functions to manage the SPI
    data transfers.

    (#) Rx data flush function:
        (++) HAL_SPIEx_FlushRxFifo()

Function Documentation

HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo ( SPI_HandleTypeDef * hspi )

Flush the RX fifo.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 96 of file stm32f3xx_hal_spi_ex.c.

References __SPI_HandleTypeDef::Instance, SPI_FIFO_SIZE, SPI_FLAG_FRLVL, and SPI_FRLVL_EMPTY.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Private Functions

Functions
TIM Private Functions
TIM

Functions

static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
Selects the Input Trigger source.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 1 configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 2 configuration.
void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 3 configuration.
void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 4 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.

Function Documentation

void TIM_Base_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_Base_InitTypeDef * | Structure
 | ) |  |

Time Base configuration.

Parameters:
TIMx | TIM periheral
Structure | TIM Base configuration structure
Return values:
None

Definition at line 4660 of file stm32f3xx_hal_tim.c.

References TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, TIM_Base_InitTypeDef::Period, TIM_Base_InitTypeDef::Prescaler, and TIM_Base_InitTypeDef::RepetitionCounter.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void TIM_CCxChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelState
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx | to select the TIM peripheral
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
ChannelState | specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
Return values:
None

Definition at line 5462 of file stm32f3xx_hal_tim.c.

References assert_param, and IS_TIM_CHANNELS.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

void TIM_DMACaptureCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 4598 of file stm32f3xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

void TIM_DMADelayPulseCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Delay Pulse complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 4566 of file stm32f3xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_DMAError ( DMA_HandleTypeDef * hdma )

TIM DMA error callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 4552 of file stm32f3xx_hal_tim.c.

References HAL_TIM_ErrorCallback(), HAL_TIM_STATE_READY, and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

static void TIM_DMAPeriodElapsedCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Period Elapse complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 4631 of file stm32f3xx_hal_tim.c.

References HAL_TIM_PeriodElapsedCallback(), HAL_TIM_STATE_READY, and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

static void TIM_DMATriggerCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Trigger callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 4645 of file stm32f3xx_hal_tim.c.

References HAL_TIM_STATE_READY, HAL_TIM_TriggerCallback(), and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

void TIM_ETR_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ExtTRGPrescaler,
 |  | uint32_t | TIM_ExtTRGPolarity,
 |  | uint32_t | ExtTRGFilter
 | ) |  |

Configures the TIMx External Trigger (ETR).

Parameters:
TIMx | to select the TIM peripheral
TIM_ExtTRGPrescaler The external Trigger Prescaler. This parameter can be one of the following values:
  • TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
  • TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
  • TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
  • TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
TIM_ExtTRGPolarity The external Trigger Polarity. This parameter can be one of the following values:
  • TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
  • TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
ExtTRGFilter | External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 5432 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), and TIM_SlaveTimer_SetConfig().

static void TIM_ITRx_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | InputTriggerSource
 | ) |  | [static]

Selects the Input Trigger source.

Parameters:
TIMx to select the TIM peripheral
InputTriggerSource The Input Trigger source. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal Trigger 0
  • TIM_TS_ITR1: Internal Trigger 1
  • TIM_TS_ITR2: Internal Trigger 2
  • TIM_TS_ITR3: Internal Trigger 3
  • TIM_TS_TI1F_ED: TI1 Edge Detector
  • TIM_TS_TI1FP1: Filtered Timer Input 1
  • TIM_TS_TI2FP2: Filtered Timer Input 2
  • TIM_TS_ETRF: External Trigger input
Return values:
None

Definition at line 5402 of file stm32f3xx_hal_tim.c.

References TIM_SLAVEMODE_EXTERNAL1.

Referenced by HAL_TIM_ConfigClockSource().

void TIM_OC1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Time Ouput Compare 1 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The ouput configuration structure
Return values:
None

Definition at line 4708 of file stm32f3xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_1.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_OC2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Time Ouput Compare 2 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The ouput configuration structure
Return values:
None

Definition at line 4782 of file stm32f3xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_2.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

void TIM_OC3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Time Ouput Compare 3 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The ouput configuration structure
Return values:
None

Definition at line 4862 of file stm32f3xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_3.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_OC4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Time Ouput Compare 4 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The ouput configuration structure
Return values:
None

Definition at line 4939 of file stm32f3xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_SlaveTimer_SetConfig | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  | [static]

Definition at line 4994 of file stm32f3xx_hal_tim.c.

References assert_param, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_TRIGGERFILTER, IS_TIM_TRIGGERPOLARITY, IS_TIM_TRIGGERPRESCALER, TIM_SlaveConfigTypeDef::SlaveMode, TIM_ETR_SetConfig(), TIM_TI1_ConfigInputStage(), TIM_TI2_ConfigInputStage(), TIM_TS_ETRF, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, TIM_TS_ITR3, TIM_TS_TI1F_ED, TIM_TS_TI1FP1, TIM_TS_TI2FP2, TIM_SlaveConfigTypeDef::TriggerFilter, TIM_SlaveConfigTypeDef::TriggerPolarity, and TIM_SlaveConfigTypeDef::TriggerPrescaler.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

static void TIM_TI1_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI1.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 5185 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

void TIM_TI1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  |

Configure the TI1 as Input.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
  • TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 (on channel2 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 5138 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

static void TIM_TI2_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI2.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 5268 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

static void TIM_TI2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
  • TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 (on channel1 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 5228 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), and HAL_TIM_OnePulse_ConfigChannel().

static void TIM_TI3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
  • TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.

Definition at line 5311 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

static void TIM_TI4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI4 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
  • TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.
Return values:
None

Definition at line 5359 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Time Base functions

Functions
Time Base functions
TIM Exported Functions

Time Base functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.

Detailed Description

Time Base functions.

  ==============================================================================
              ##### Time Base functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM base.
    (+) De-initialize the TIM base.
    (+) Start the Time Base.
    (+) Stop the Time Base.
    (+) Start the Time Base and enable interrupt.
    (+) Stop the Time Base and disable interrupt.
    (+) Start the Time Base and enable DMA transfer.
    (+) Stop the Time Base and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Base_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Base peripheral.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 240 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_Base_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 200 of file stm32f3xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_Base_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_Base_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Base MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 282 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_Base_DeInit().

void HAL_TIM_Base_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Base MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 267 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_Base_Init().

HAL_StatusTypeDef HAL_TIM_Base_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation.

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 298 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Base generation in DMA mode.

Parameters:
htim | TIM handle
pData | The source Buffer address.
Length | The length of data to be transferred from memory to peripheral.
Return values:
HAL status

Definition at line 385 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_DMA_ID_UPDATE, TIM_DMA_UPDATE, TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_Base_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation in interrupt mode.

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 344 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, and TIM_IT_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation.

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 321 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in DMA mode.

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 429 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in interrupt mode.

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 364 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, and TIM_IT_UPDATE.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Time Output Compare functions

Functions
Time Output Compare functions
TIM Exported Functions

Time Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.

Detailed Description

Time Output Compare functions.

  ==============================================================================
                  ##### Time Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Output Compare.
    (+) De-initialize the TIM Output Compare.
    (+) Start the Time Output Compare.
    (+) Stop the Time Output Compare.
    (+) Start the Time Output Compare and enable interrupt.
    (+) Stop the Time Output Compare and disable interrupt.
    (+) Start the Time Output Compare and enable DMA transfer.
    (+) Stop the Time Output Compare and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OC_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim TIM Output Compare handle
Return values:
HAL status

Definition at line 518 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_OC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_OC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim TIM Output Compare handle
Return values:
HAL status

Definition at line 478 of file stm32f3xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_OC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_OC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Output Compare MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 560 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_OC_DeInit().

void HAL_TIM_OC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 545 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_OC_Init().

HAL_StatusTypeDef HAL_TIM_OC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 581 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_OC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode.

Parameters:
htim | TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 779 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_OC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim TIM OC handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 645 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 613 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 896 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 711 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Time PWM functions

Functions
Time PWM functions
TIM Exported Functions

Time PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.

Detailed Description

Time PWM functions.

  ==============================================================================
                          ##### Time PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM OPWM.
    (+) De-initialize the TIM PWM.
    (+) Start the Time PWM.
    (+) Stop the Time PWM.
    (+) Start the Time PWM and enable interrupt.
    (+) Stop the Time PWM and disable interrupt.
    (+) Start the Time PWM and enable DMA transfer.
    (+) Stop the Time PWM and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_PWM_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 1025 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_PWM_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_PWM_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 985 of file stm32f3xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_PWM_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_PWM_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM PWM MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 1067 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_PWM_DeInit().

void HAL_TIM_PWM_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 1052 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_PWM_Init().

HAL_StatusTypeDef HAL_TIM_PWM_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation.

Parameters:
htim TIM handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1088 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode.

Parameters:
htim | TIM handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1289 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_PWM_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode.

Parameters:
htim TIM handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1155 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation.

Parameters:
htim TIM handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1120 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode.

Parameters:
htim TIM handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1406 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode.

Parameters:
htim TIM handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1221 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Time Input Capture functions

Functions
Time Input Capture functions
TIM Exported Functions

Time Input Capture functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.

Detailed Description

Time Input Capture functions.

  ==============================================================================
              ##### Time Input Capture functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
   (+) Initialize and configure the TIM Input Capture.
   (+) De-initialize the TIM Input Capture.
   (+) Start the Time Input Capture.
   (+) Stop the Time Input Capture.
   (+) Start the Time Input Capture and enable interrupt.
   (+) Stop the Time Input Capture and disable interrupt.
   (+) Start the Time Input Capture and enable DMA transfer.
   (+) Stop the Time Input Capture and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_IC_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim TIM Input Capture handle
Return values:
HAL status

Definition at line 1535 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_IC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim TIM Input Capture handle
Return values:
HAL status

Definition at line 1495 of file stm32f3xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_IC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_IC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Input Capture MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 1577 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_IC_DeInit().

void HAL_TIM_IC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Input Capture MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 1562 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_IC_Init().

HAL_StatusTypeDef HAL_TIM_IC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1598 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_IC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Input Capture measurement in DMA mode.

Parameters:
htim | TIM Input Capture handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The destination Buffer address.
Length | The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 1771 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMACaptureCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_IC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement in interrupt mode.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1650 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement.

Parameters:
htim TIM handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1624 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement in DMA mode.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1884 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement in interrupt mode.

Parameters:
htim TIM handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1709 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Time One Pulse functions

Functions
Time One Pulse functions
TIM Exported Functions

Time One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.

Detailed Description

Time One Pulse functions.

  ==============================================================================
                        ##### Time One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM One Pulse.
    (+) De-initialize the TIM One Pulse.
    (+) Start the Time One Pulse.
    (+) Stop the Time One Pulse.
    (+) Start the Time One Pulse and enable interrupt.
    (+) Stop the Time One Pulse and disable interrupt.
    (+) Start the Time One Pulse and enable DMA transfer.
    (+) Stop the Time One Pulse and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM One Pulse.

Parameters:
htim TIM One Pulse handle
Return values:
HAL status

Definition at line 2018 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_OnePulse_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_OnePulse_Init | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OnePulseMode
 | ) |  |

Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim TIM OnePulse handle
OnePulseMode Select the One pulse mode. This parameter can be one of the following values:
  • TIM_OPMODE_SINGLE: Only one pulse will be generated.
  • TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
Return values:
HAL status

Definition at line 1971 of file stm32f3xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_OnePulse_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_OPM_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_OnePulse_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM One Pulse MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2060 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_DeInit().

void HAL_TIM_OnePulse_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM One Pulse MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2045 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_Init().

HAL_StatusTypeDef HAL_TIM_OnePulse_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2079 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_MOE_ENABLE, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2145 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channels to be disable This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2112 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2184 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Time Encoder functions

Functions
Time Encoder functions
TIM Exported Functions

Time Encoder functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.

Detailed Description

Time Encoder functions.

  ==============================================================================
                          ##### Time Encoder functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Encoder.
    (+) De-initialize the TIM Encoder.
    (+) Start the Time Encoder.
    (+) Stop the Time Encoder.
    (+) Start the Time Encoder and enable interrupt.
    (+) Stop the Time Encoder and disable interrupt.
    (+) Start the Time Encoder and enable DMA transfer.
    (+) Stop the Time Encoder and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Encoder_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Encoder interface.

Parameters:
htim TIM Encoder handle
Return values:
HAL status

Definition at line 2337 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_Encoder_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Encoder_Init | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_Encoder_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Encoder Interface and create the associated handle.

Parameters:
htim | TIM Encoder Interface handle
sConfig | TIM Encoder Interface configuration structure
Return values:
HAL status

Definition at line 2244 of file stm32f3xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, TIM_Encoder_InitTypeDef::EncoderMode, HAL_TIM_Encoder_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_Encoder_InitTypeDef::IC1Filter, TIM_Encoder_InitTypeDef::IC1Polarity, TIM_Encoder_InitTypeDef::IC1Prescaler, TIM_Encoder_InitTypeDef::IC1Selection, TIM_Encoder_InitTypeDef::IC2Filter, TIM_Encoder_InitTypeDef::IC2Polarity, TIM_Encoder_InitTypeDef::IC2Prescaler, TIM_Encoder_InitTypeDef::IC2Selection, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_ENCODER_MODE, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_Encoder_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Encoder Interface MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2379 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_Encoder_DeInit().

void HAL_TIM_Encoder_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Encoder Interface MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2364 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_Encoder_Init().

HAL_StatusTypeDef HAL_TIM_Encoder_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2399 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData1,
 |  | uint32_t * | pData2,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Encoder Interface in DMA mode.

Parameters:
htim | TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
pData1,: The destination Buffer address for IC1.
pData2,: The destination Buffer address for IC2.
Length | The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 2587 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_ALL, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMACaptureCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface in interrupt mode.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2485 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2441 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in DMA mode.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2704 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_DMA_CC1, and TIM_DMA_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in interrupt mode.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2533 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM IRQ handler management

Functions
TIM IRQ handler management
TIM Exported Functions

IRQ handler management. More...

Functions

void HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.

Detailed Description

IRQ handler management.

  ==============================================================================
                        ##### IRQ handler management #####
  ==============================================================================
  [..]
    This section provides Timer IRQ handler function.

Function Documentation

void HAL_TIM_IRQHandler ( TIM_HandleTypeDef * htim )

This function handles TIM interrupts requests.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2766 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_CLEAR_FLAG, __HAL_TIM_GET_FLAG, __HAL_TIM_GET_IT_SOURCE, TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_TriggerCallback(), HAL_TIMEx_Break2Callback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutationCallback(), TIM_HandleTypeDef::Instance, TIM_FLAG_BREAK, TIM_FLAG_CC1, TIM_FLAG_CC2, TIM_FLAG_CC3, TIM_FLAG_CC4, TIM_FLAG_COM, TIM_FLAG_TRIGGER, TIM_FLAG_UPDATE, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4, TIM_IT_COM, TIM_IT_TRIGGER, and TIM_IT_UPDATE.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
TIM Exported Functions

Peripheral Control functions. More...

Functions

__weak HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
__weak HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiWriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
__weak HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.

Detailed Description

Peripheral Control functions.

  ==============================================================================
                   ##### Peripheral Control functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
      (+) Configure External Clock source.
      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master and the Slave synchronization.
      (+) Configure the DMA Burst Mode.

Function Documentation

HAL_StatusTypeDef HAL_TIM_ConfigClockSource | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_ClockConfigTypeDef * | sClockSourceConfig
 | ) |  |

Configures the clock source to be used.

Parameters:
htim | TIM handle
sClockSourceConfig | pointer to a TIM_ClockConfigTypeDef structure that contains the clock source information for the TIM peripheral.
Return values:
HAL status

Definition at line 4006 of file stm32f3xx_hal_tim.c.

References assert_param, TIM_ClockConfigTypeDef::ClockFilter, TIM_ClockConfigTypeDef::ClockPolarity, TIM_ClockConfigTypeDef::ClockPrescaler, TIM_ClockConfigTypeDef::ClockSource, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKFILTER, IS_TIM_CLOCKPOLARITY, IS_TIM_CLOCKPRESCALER, IS_TIM_CLOCKSOURCE, TIM_HandleTypeDef::State, TIM_CLOCKSOURCE_ETRMODE1, TIM_CLOCKSOURCE_ETRMODE2, TIM_CLOCKSOURCE_INTERNAL, TIM_CLOCKSOURCE_ITR0, TIM_CLOCKSOURCE_ITR1, TIM_CLOCKSOURCE_ITR2, TIM_CLOCKSOURCE_ITR3, TIM_CLOCKSOURCE_TI1, TIM_CLOCKSOURCE_TI1ED, TIM_CLOCKSOURCE_TI2, TIM_ETR_SetConfig(), TIM_ITRx_SetConfig(), TIM_SLAVEMODE_EXTERNAL1, TIM_TI1_ConfigInputStage(), and TIM_TI2_ConfigInputStage().

HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_ClearInputConfigTypeDef * | sClearInputConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the OCRef clear feature.

Parameters:
htim | TIM handle
sClearInputConfig | pointer to a TIM_ClearInputConfigTypeDef structure that contains the OCREF clear feature and parameters for the TIM peripheral.
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
Return values:
HAL status

Definition at line 3902 of file stm32f3xx_hal_tim.c.

References assert_param, TIM_ClearInputConfigTypeDef::ClearInputFilter, TIM_ClearInputConfigTypeDef::ClearInputPolarity, TIM_ClearInputConfigTypeDef::ClearInputPrescaler, TIM_ClearInputConfigTypeDef::ClearInputSource, TIM_ClearInputConfigTypeDef::ClearInputState, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_CLEARINPUT_FILTER, IS_TIM_CLEARINPUT_POLARITY, IS_TIM_CLEARINPUT_PRESCALER, IS_TIM_CLEARINPUT_SOURCE, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CLEARINPUTSOURCE_ETR, and TIM_ETR_SetConfig().

HAL_StatusTypeDef HAL_TIM_ConfigTI1Input | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | TI1_Selection
 | ) |  |

Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.

Parameters:
htim TIM handle.
TI1_Selection,: Indicate whether or not channel 1 is connected to the output of a XOR gate. This parameter can be one of the following values:
  • TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
  • TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Return values:
HAL status

Definition at line 4180 of file stm32f3xx_hal_tim.c.

References assert_param, TIM_HandleTypeDef::Instance, and IS_TIM_TI1SELECTION.

HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength,
 |  | uint32_t | DataLength
 | ) |  |

Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will starts the Data read This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_DCR
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
DataLength | Data length. This parameter can be one value between 1 and 0xFFFF.
Return values:
HAL status

Definition at line 3659 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_DATA_LENGTH, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, TIM_HandleTypeDef::State, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMACaptureCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), TIMEx_DMACommutationCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_TIM_DMABurst_ReadStart().

HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength,
 |  | uint32_t | DataLength
 | ) |  |

Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will start the Data write This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_DCR
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
DataLength | Data length. This parameter can be one value between 1 and 0xFFFF.
Return values:
HAL status

Definition at line 3389 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_DATA_LENGTH, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, TIM_HandleTypeDef::State, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMADelayPulseCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), TIMEx_DMACommutationCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_TIM_DMABurst_WriteStart().

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will starts the Data read This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_DCR
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
Return values:
HAL status

Definition at line 3613 of file stm32f3xx_hal_tim.c.

References HAL_TIM_DMABurst_MultiReadStart().

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stop the DMA burst reading.

Parameters:
htim | TIM handle
BurstRequestSrc | TIM DMA Request sources to disable.
Return values:
HAL status

Definition at line 3792 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort(), TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will start the Data write This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_DCR
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
Return values:
HAL status

Definition at line 3343 of file stm32f3xx_hal_tim.c.

References HAL_TIM_DMABurst_MultiWriteStart().

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stops the TIM DMA Burst mode.

Parameters:
htim | TIM handle
BurstRequestSrc | TIM DMA Request sources to disable
Return values:
HAL status

Definition at line 3521 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort(), TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_GenerateEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | EventSource
 | ) |  |

Generate a software event.

Parameters:
htim TIM handle
EventSource specifies the event source. This parameter can be one of the following values:
  • TIM_EVENTSOURCE_UPDATE: Timer update Event source
  • TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
  • TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
  • TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
  • TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
  • TIM_EVENTSOURCE_COM: Timer COM event source
  • TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
  • TIM_EVENTSOURCE_BREAK: Timer Break event source
  • TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
Return values:
HAL status
Note:
TIM_EVENTSOURCE_BREAK2 isn't relevant for STM32F37xx and STM32F38xx devices

Definition at line 3865 of file stm32f3xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_EVENT_SOURCE, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_IC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.

Parameters:
htim | TIM IC handle
sConfig | TIM Input Capture configuration structure
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 3011 of file stm32f3xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_IC_InitTypeDef::ICFilter, TIM_IC_InitTypeDef::ICPolarity, TIM_IC_InitTypeDef::ICPrescaler, TIM_IC_InitTypeDef::ICSelection, TIM_HandleTypeDef::Instance, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TI3_SetConfig(), and TIM_TI4_SetConfig().

HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim | TIM Output Compare handle
sConfig | TIM Output Compare configuration structure
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2942 of file stm32f3xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OnePulse_InitTypeDef * | sConfig,
 |  | uint32_t | OutputChannel,
 |  | uint32_t | InputChannel
 | ) |  |

Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.

Parameters:
htim | TIM One Pulse handle
sConfig | TIM One Pulse configuration structure
OutputChannel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
InputChannel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 3207 of file stm32f3xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_OnePulse_InitTypeDef::ICFilter, TIM_OnePulse_InitTypeDef::ICPolarity, TIM_OnePulse_InitTypeDef::ICSelection, TIM_HandleTypeDef::Instance, IS_TIM_OPM_CHANNELS, TIM_OC_InitTypeDef::OCIdleState, TIM_OnePulse_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OnePulse_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OnePulse_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OnePulse_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OnePulse_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, TIM_OnePulse_InitTypeDef::Pulse, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_SLAVEMODE_TRIGGER, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TS_TI1FP1, and TIM_TS_TI2FP2.

HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim | TIM handle
sConfig | TIM PWM configuration structure
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 3107 of file stm32f3xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_FAST_STATE, IS_TIM_OC_POLARITY, IS_TIM_PWM_MODE, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

uint32_t HAL_TIM_ReadCapturedValue | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Read the captured value from Capture Compare unit.

Parameters:
htim TIM handle.
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
Captured value

Definition at line 4285 of file stm32f3xx_hal_tim.c.

References assert_param, TIM_HandleTypeDef::Instance, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, and TIM_CHANNEL_4.

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode.

Parameters:
htim | TIM handle.
sSlaveConfig | pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the ) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 4212 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, TIM_SlaveConfigTypeDef::SlaveMode, TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode in interrupt mode.

Parameters:
htim | TIM handle.
sSlaveConfig | pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the ) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 4247 of file stm32f3xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, TIM_SlaveConfigTypeDef::SlaveMode, TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Callbacks functions

Functions
TIM Callbacks functions
TIM Exported Functions

TIM Callbacks functions. More...

Functions

__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non blocking mode.

Detailed Description

TIM Callbacks functions.

  ==============================================================================
                        ##### TIM Callbacks functions #####
  ==============================================================================
 [..]
   This section provides TIM callback functions:
   (+) Timer Period elapsed callback
   (+) Timer Output Compare callback
   (+) Timer Input capture callback
   (+) Timer Trigger callback
   (+) Timer Error callback

Function Documentation

void HAL_TIM_ErrorCallback ( TIM_HandleTypeDef * htim )

Timer error callback in non blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 4446 of file stm32f3xx_hal_tim.c.

Referenced by TIM_DMAError().

void HAL_TIM_IC_CaptureCallback ( TIM_HandleTypeDef * htim )

Input Capture callback in non blocking mode.

Parameters:
htim TIM IC handle
Return values:
None

Definition at line 4401 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMACaptureCplt().

void HAL_TIM_OC_DelayElapsedCallback ( TIM_HandleTypeDef * htim )

Output Compare callback in non blocking mode.

Parameters:
htim TIM OC handle
Return values:
None

Definition at line 4387 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler().

void HAL_TIM_PeriodElapsedCallback ( TIM_HandleTypeDef * htim )

Period elapsed callback in non blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 4372 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMAPeriodElapsedCplt().

void HAL_TIM_PWM_PulseFinishedCallback ( TIM_HandleTypeDef * htim )

PWM Pulse finished callback in non blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 4416 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMADelayPulseCplt().

void HAL_TIM_TriggerCallback ( TIM_HandleTypeDef * htim )

Hall Trigger detection callback in non blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 4431 of file stm32f3xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMATriggerCplt().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
TIM Exported Functions

Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                        ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIM_Base_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Base state.

Parameters:
htim TIM Base handle
Return values:
HAL state

Definition at line 4480 of file stm32f3xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Encoder Mode state.

Parameters:
htim TIM Encoder handle
Return values:
HAL state

Definition at line 4530 of file stm32f3xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_IC_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Input Capture state.

Parameters:
htim TIM IC handle
Return values:
HAL state

Definition at line 4510 of file stm32f3xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OC_GetState ( TIM_HandleTypeDef * htim )

Return the TIM OC state.

Parameters:
htim TIM Ouput Compare handle
Return values:
HAL state

Definition at line 4490 of file stm32f3xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState ( TIM_HandleTypeDef * htim )

Return the TIM One Pulse Mode state.

Parameters:
htim TIM OPM handle
Return values:
HAL state

Definition at line 4520 of file stm32f3xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState ( TIM_HandleTypeDef * htim )

Return the TIM PWM state.

Parameters:
htim TIM handle
Return values:
HAL state

Definition at line 4500 of file stm32f3xx_hal_tim.c.

References TIM_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Exported Types

Data Structures | Enumerations
TIM Exported Types
TIM

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
TIM Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04
}
HAL State structures definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00
}
HAL Active channel structures definition. More...

Enumeration Type Documentation

enum HAL_TIM_ActiveChannel

HAL Active channel structures definition.

Enumerator:
HAL_TIM_ACTIVE_CHANNEL_1

The active channel is 1

HAL_TIM_ACTIVE_CHANNEL_2

The active channel is 2

HAL_TIM_ACTIVE_CHANNEL_3

The active channel is 3

HAL_TIM_ACTIVE_CHANNEL_4

The active channel is 4

HAL_TIM_ACTIVE_CHANNEL_CLEARED

All active channels cleared

Definition at line 275 of file stm32f3xx_hal_tim.h.

enum HAL_TIM_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_TIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_TIM_STATE_READY

Peripheral Initialized and ready for use

HAL_TIM_STATE_BUSY

An internal process is ongoing

HAL_TIM_STATE_TIMEOUT

Timeout state

HAL_TIM_STATE_ERROR

Reception process is ongoing

Definition at line 263 of file stm32f3xx_hal_tim.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM_Base_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Base_InitTypeDef Struct Reference
TIM Exported Types

TIM Time base Configuration Structure definition. More...

#include <stm32f3xx_hal_tim.h>

Data Fields

uint32_t | Prescaler
uint32_t | CounterMode
uint32_t | Period
uint32_t | ClockDivision
uint32_t | RepetitionCounter
uint32_t | AutoReloadPreload

Detailed Description

TIM Time base Configuration Structure definition.

Definition at line 62 of file stm32f3xx_hal_tim.h.

Field Documentation

uint32_t TIM_Base_InitTypeDef::AutoReloadPreload

Specifies the auto-reload preload. This parameter can be a value of TIM Auto-Reload Preload

Definition at line 86 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::ClockDivision

Specifies the clock division. This parameter can be a value of TIM Clock Division

Definition at line 74 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::CounterMode

Specifies the counter mode. This parameter can be a value of TIM Counter Mode

Definition at line 67 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Period

Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 70 of file stm32f3xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU

Definition at line 64 of file stm32f3xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::RepetitionCounter

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1U) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 77 of file stm32f3xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_tim.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM_OC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OC_InitTypeDef Struct Reference
TIM Exported Types

TIM Output Compare Configuration Structure definition. More...

#include <stm32f3xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCFastMode
uint32_t | OCIdleState
uint32_t | OCNIdleState

Detailed Description

TIM Output Compare Configuration Structure definition.

Definition at line 93 of file stm32f3xx_hal_tim.h.

Field Documentation

uint32_t TIM_OC_InitTypeDef::OCFastMode

Specifies the Fast mode state. This parameter can be a value of TIM Output Fast State

Note:
This parameter is valid only in PWM1 and PWM2 mode.

Definition at line 108 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

uint32_t TIM_OC_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 113 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIMEx Output Compare and PWM Modes

Definition at line 95 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Complementary Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 117 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 104 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 101 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

uint32_t TIM_OC_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU

Definition at line 98 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_tim.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM_OnePulse_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OnePulse_InitTypeDef Struct Reference
TIM Exported Types

TIM One Pulse Mode Configuration Structure definition. More...

#include <stm32f3xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCIdleState
uint32_t | OCNIdleState
uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICFilter

Detailed Description

TIM One Pulse Mode Configuration Structure definition.

Definition at line 125 of file stm32f3xx_hal_tim.h.

Field Documentation

uint32_t TIM_OnePulse_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU

Definition at line 154 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 148 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 151 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 140 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIMEx Output Compare and PWM Modes

Definition at line 127 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Complementary Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 144 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 136 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 133 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU

Definition at line 130 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_tim.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM_IC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_IC_InitTypeDef Struct Reference
TIM Exported Types

TIM Input Capture Configuration Structure definition. More...

#include <stm32f3xx_hal_tim.h>

Data Fields

uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICPrescaler
uint32_t | ICFilter

Detailed Description

TIM Input Capture Configuration Structure definition.

Definition at line 162 of file stm32f3xx_hal_tim.h.

Field Documentation

uint32_t TIM_IC_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU

Definition at line 173 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 164 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 170 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 167 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_tim.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM_Encoder_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Encoder_InitTypeDef Struct Reference
TIM Exported Types

TIM Encoder Configuration Structure definition. More...

#include <stm32f3xx_hal_tim.h>

Data Fields

uint32_t | EncoderMode
uint32_t | IC1Polarity
uint32_t | IC1Selection
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | IC2Polarity
uint32_t | IC2Selection
uint32_t | IC2Prescaler
uint32_t | IC2Filter

Detailed Description

TIM Encoder Configuration Structure definition.

Definition at line 180 of file stm32f3xx_hal_tim.h.

Field Documentation

uint32_t TIM_Encoder_InitTypeDef::EncoderMode

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Mode

Definition at line 182 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU

Definition at line 194 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 185 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 191 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 188 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU

Definition at line 206 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 197 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 203 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 200 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_tim.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClockConfigTypeDef Struct Reference
TIM Exported Types

TIM Clock Configuration Handle Structure definition. More...

#include <stm32f3xx_hal_tim.h>

Data Fields

uint32_t | ClockSource
uint32_t | ClockPolarity
uint32_t | ClockPrescaler
uint32_t | ClockFilter

Detailed Description

TIM Clock Configuration Handle Structure definition.

Definition at line 214 of file stm32f3xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClockConfigTypeDef::ClockFilter

TIM clock filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU

Definition at line 222 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPolarity

TIM clock polarity This parameter can be a value of TIM Clock Polarity

Definition at line 218 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPrescaler

TIM clock prescaler This parameter can be a value of TIM Clock Prescaler

Definition at line 220 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockSource

TIM clock sources This parameter can be a value of TIM Clock Source

Definition at line 216 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_tim.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM_ClearInputConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClearInputConfigTypeDef Struct Reference
TIM Exported Types

TIM Clear Input Configuration Handle Structure definition. More...

#include <stm32f3xx_hal_tim.h>

Data Fields

uint32_t | ClearInputState
uint32_t | ClearInputSource
uint32_t | ClearInputPolarity
uint32_t | ClearInputPrescaler
uint32_t | ClearInputFilter

Detailed Description

TIM Clear Input Configuration Handle Structure definition.

Definition at line 229 of file stm32f3xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClearInputConfigTypeDef::ClearInputFilter

TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU

Definition at line 239 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPolarity

TIM Clear Input polarity This parameter can be a value of TIM Clear Input Polarity

Definition at line 235 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPrescaler

TIM Clear Input prescaler This parameter can be a value of TIM Clear Input Prescaler

Definition at line 237 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputSource

TIM clear Input sources This parameter can be a value of TIMEx Clear Input Source

Definition at line 233 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputState

TIM clear Input state This parameter can be ENABLE or DISABLE

Definition at line 231 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_tim.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM_SlaveConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_SlaveConfigTypeDef Struct Reference
TIM Exported Types

TIM Slave configuration Structure definition. More...

#include <stm32f3xx_hal_tim.h>

Data Fields

uint32_t | SlaveMode
uint32_t | InputTrigger
uint32_t | TriggerPolarity
uint32_t | TriggerPrescaler
uint32_t | TriggerFilter

Detailed Description

TIM Slave configuration Structure definition.

Definition at line 246 of file stm32f3xx_hal_tim.h.

Field Documentation

uint32_t TIM_SlaveConfigTypeDef::InputTrigger

Input Trigger source This parameter can be a value of TIM Trigger Selection

Definition at line 249 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::SlaveMode

Slave mode selection This parameter can be a value of TIMEx Slave Mode

Definition at line 247 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerFilter

Input trigger filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU

Definition at line 255 of file stm32f3xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPolarity

Input Trigger polarity This parameter can be a value of TIM Trigger Polarity

Definition at line 251 of file stm32f3xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPrescaler

Input trigger prescaler This parameter can be a value of TIM Trigger Prescaler

Definition at line 253 of file stm32f3xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_tim.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_HandleTypeDef Struct Reference
TIM Exported Types

TIM Time Base Handle Structure definition. More...

#include <stm32f3xx_hal_tim.h>

Data Fields

TIM_TypeDef * | Instance
TIM_Base_InitTypeDef Init
HAL_TIM_ActiveChannel Channel
DMA_HandleTypeDef * | hdma [7]
HAL_LockTypeDef | Lock
__IO HAL_TIM_StateTypeDef | State

Detailed Description

TIM Time Base Handle Structure definition.

Definition at line 287 of file stm32f3xx_hal_tim.h.

Field Documentation

HAL_TIM_ActiveChannel TIM_HandleTypeDef::Channel

Active channel

Definition at line 291 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

DMA_HandleTypeDef* TIM_HandleTypeDef::hdma[7]

DMA Handlers array This array is accessed by a TIM DMA Handle Index

Definition at line 292 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

TIM_Base_InitTypeDef TIM_HandleTypeDef::Init

TIM Time Base required parameters

Definition at line 290 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

TIM_TypeDef* TIM_HandleTypeDef::Instance

Register base address

Definition at line 289 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_RemapConfig(), and TIM_SlaveTimer_SetConfig().

HAL_LockTypeDef TIM_HandleTypeDef::Lock

Locking object

Definition at line 294 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

__IO HAL_TIM_StateTypeDef TIM_HandleTypeDef::State

TIM operation state

Definition at line 295 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_GetState(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_GetState(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_GetState(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_GetState(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_GetState(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_GetState(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_GetState(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_RemapConfig(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), and TIMEx_DMACommutationCplt().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_tim.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Input Channel Polarity

Defines
TIM Input Channel Polarity
TIM Exported Constants

Defines

#define | TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U)
#define | TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Define Documentation

#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Polarity for TIx source

Definition at line 313 of file stm32f3xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)

Polarity for TIx source

Definition at line 312 of file stm32f3xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U)

Polarity for TIx source

Definition at line 311 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM ETR Polarity

Defines
TIM ETR Polarity
TIM Exported Constants

Defines

#define | TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)
#define | TIM_ETRPOLARITY_NONINVERTED (0x0000U)

Define Documentation

#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)

Polarity for ETR source

Definition at line 321 of file stm32f3xx_hal_tim.h.

#define TIM_ETRPOLARITY_NONINVERTED (0x0000U)

Polarity for ETR source

Definition at line 322 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM ETR Prescaler

Defines
TIM ETR Prescaler
TIM Exported Constants

Defines

#define | TIM_ETRPRESCALER_DIV1 (0x0000U)
#define | TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)
#define | TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)
#define | TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)

Define Documentation

#define TIM_ETRPRESCALER_DIV1 (0x0000U)

No prescaler is used

Definition at line 330 of file stm32f3xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)

ETR input source is divided by 2U

Definition at line 331 of file stm32f3xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)

ETR input source is divided by 4U

Definition at line 332 of file stm32f3xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)

ETR input source is divided by 8U

Definition at line 333 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM Counter Mode

Defines
TIM Counter Mode
TIM Exported Constants

Defines

#define | TIM_COUNTERMODE_UP (0x0000U)
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Define Documentation

#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0

Definition at line 343 of file stm32f3xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1

Definition at line 344 of file stm32f3xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Definition at line 345 of file stm32f3xx_hal_tim.h.

#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR

Definition at line 342 of file stm32f3xx_hal_tim.h.

#define TIM_COUNTERMODE_UP (0x0000U)

Definition at line 341 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM Clock Division

Defines
TIM Clock Division
TIM Exported Constants

Defines

#define | TIM_CLOCKDIVISION_DIV1 (0x0000U)
#define | TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define | TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)

Define Documentation

#define TIM_CLOCKDIVISION_DIV1 (0x0000U)

Definition at line 353 of file stm32f3xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)

Definition at line 354 of file stm32f3xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)

Definition at line 355 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM Auto-Reload Preload

Defines
TIM Auto-Reload Preload
TIM Exported Constants

Defines

#define | TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U)
#define | TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE)

Define Documentation

#define TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U)

TIMx_ARR register is not buffered

Definition at line 363 of file stm32f3xx_hal_tim.h.

#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE)

TIMx_ARR register is buffered

Definition at line 364 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM Output Fast State

Defines
TIM Output Fast State
TIM Exported Constants

Defines

#define | TIM_OCFAST_DISABLE (0x0000U)
#define | TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)

Define Documentation

#define TIM_OCFAST_DISABLE (0x0000U)

Definition at line 373 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)

Definition at line 374 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM Output Compare Polarity

Defines
TIM Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCPOLARITY_HIGH (0x0000U)
#define | TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)

Define Documentation

#define TIM_OCPOLARITY_HIGH (0x0000U)

Definition at line 382 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)

Definition at line 383 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM Complementary Output Compare Polarity

Defines
TIM Complementary Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCNPOLARITY_HIGH (0x0000U)
#define | TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)

Define Documentation

#define TIM_OCNPOLARITY_HIGH (0x0000U)

Definition at line 391 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)

Definition at line 392 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM Output Compare Idle State

Defines
TIM Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
#define | TIM_OCIDLESTATE_RESET (0x0000U)

Define Documentation

#define TIM_OCIDLESTATE_RESET (0x0000U)

Definition at line 401 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)

Definition at line 400 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM Complementary Output Compare Idle State

Defines
TIM Complementary Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
#define | TIM_OCNIDLESTATE_RESET (0x0000U)

Define Documentation

#define TIM_OCNIDLESTATE_RESET (0x0000U)

Definition at line 410 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)

Definition at line 409 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM Input Capture Polarity

Defines
TIM Input Capture Polarity
TIM Exported Constants

Defines

#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Definition at line 420 of file stm32f3xx_hal_tim.h.

#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Definition at line 419 of file stm32f3xx_hal_tim.h.

#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Definition at line 418 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM Input Capture Selection

Defines
TIM Input Capture Selection
TIM Exported Constants

Defines

#define | TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)
#define | TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)
#define | TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)

Define Documentation

#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)

TIM Input 1U, 2U, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively

Definition at line 428 of file stm32f3xx_hal_tim.h.

#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)

TIM Input 1U, 2U, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively

Definition at line 430 of file stm32f3xx_hal_tim.h.

#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)

TIM Input 1U, 2U, 3 or 4 is selected to be connected to TRC

Definition at line 432 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

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STM32F373xC HAL User Manual: TIM Input Capture Prescaler

Defines
TIM Input Capture Prescaler
TIM Exported Constants

Defines

#define | TIM_ICPSC_DIV1 (0x0000U)
#define | TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)
#define | TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)
#define | TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)

Define Documentation

#define TIM_ICPSC_DIV1 (0x0000U)

Capture performed each time an edge is detected on the capture input

Definition at line 440 of file stm32f3xx_hal_tim.h.

#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)

Capture performed once every 2 events

Definition at line 441 of file stm32f3xx_hal_tim.h.

#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)

Capture performed once every 4 events

Definition at line 442 of file stm32f3xx_hal_tim.h.

#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)

Capture performed once every 8 events

Definition at line 443 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM One Pulse Mode

Defines
TIM One Pulse Mode
TIM Exported Constants

Defines

#define | TIM_OPMODE_SINGLE (TIM_CR1_OPM)
#define | TIM_OPMODE_REPETITIVE (0x0000U)

Define Documentation

#define TIM_OPMODE_REPETITIVE (0x0000U)

Definition at line 452 of file stm32f3xx_hal_tim.h.

#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)

Definition at line 451 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM Encoder Mode

Defines
TIM Encoder Mode
TIM Exported Constants

Defines

#define | TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Define Documentation

#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)

Definition at line 460 of file stm32f3xx_hal_tim.h.

#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Definition at line 462 of file stm32f3xx_hal_tim.h.

#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)

Definition at line 461 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM Interrupt Definition

Defines
TIM Interrupt Definition
TIM Exported Constants

Defines

#define | TIM_IT_UPDATE (TIM_DIER_UIE)
#define | TIM_IT_CC1 (TIM_DIER_CC1IE)
#define | TIM_IT_CC2 (TIM_DIER_CC2IE)
#define | TIM_IT_CC3 (TIM_DIER_CC3IE)
#define | TIM_IT_CC4 (TIM_DIER_CC4IE)
#define | TIM_IT_COM (TIM_DIER_COMIE)
#define | TIM_IT_TRIGGER (TIM_DIER_TIE)
#define | TIM_IT_BREAK (TIM_DIER_BIE)

Define Documentation

#define TIM_IT_BREAK (TIM_DIER_BIE)

Definition at line 477 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC1 (TIM_DIER_CC1IE)

Definition at line 471 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC2 (TIM_DIER_CC2IE)

Definition at line 472 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC3 (TIM_DIER_CC3IE)

Definition at line 473 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC4 (TIM_DIER_CC4IE)

Definition at line 474 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_COM (TIM_DIER_COMIE)

Definition at line 475 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_IT_TRIGGER (TIM_DIER_TIE)

Definition at line 476 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define TIM_IT_UPDATE (TIM_DIER_UIE)

Definition at line 470 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop_IT(), and HAL_TIM_IRQHandler().

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STM32F373xC HAL User Manual: TIM Commutation Source

Defines
TIM Commutation Source
TIM Exported Constants

Defines

#define | TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
#define | TIM_COMMUTATION_SOFTWARE (0x0000U)

Define Documentation

#define TIM_COMMUTATION_SOFTWARE (0x0000U)

Definition at line 486 of file stm32f3xx_hal_tim.h.

#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)

Definition at line 485 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM DMA Sources

Defines
TIM DMA Sources
TIM Exported Constants

Defines

#define | TIM_DMA_UPDATE (TIM_DIER_UDE)
#define | TIM_DMA_CC1 (TIM_DIER_CC1DE)
#define | TIM_DMA_CC2 (TIM_DIER_CC2DE)
#define | TIM_DMA_CC3 (TIM_DIER_CC3DE)
#define | TIM_DMA_CC4 (TIM_DIER_CC4DE)
#define | TIM_DMA_COM (TIM_DIER_COMDE)
#define | TIM_DMA_TRIGGER (TIM_DIER_TDE)

Define Documentation

#define TIM_DMA_CC1 (TIM_DIER_CC1DE)

Definition at line 496 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC2 (TIM_DIER_CC2DE)

Definition at line 497 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC3 (TIM_DIER_CC3DE)

Definition at line 498 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC4 (TIM_DIER_CC4DE)

Definition at line 499 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_COM (TIM_DIER_COMDE)

Definition at line 500 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), and HAL_TIM_DMABurst_WriteStop().

#define TIM_DMA_TRIGGER (TIM_DIER_TDE)

Definition at line 501 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define TIM_DMA_UPDATE (TIM_DIER_UDE)

Definition at line 495 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), and HAL_TIM_DMABurst_WriteStop().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Flag Definition

Defines
TIM Flag Definition
TIM Exported Constants

Defines

#define | TIM_FLAG_UPDATE (TIM_SR_UIF)
#define | TIM_FLAG_CC1 (TIM_SR_CC1IF)
#define | TIM_FLAG_CC2 (TIM_SR_CC2IF)
#define | TIM_FLAG_CC3 (TIM_SR_CC3IF)
#define | TIM_FLAG_CC4 (TIM_SR_CC4IF)
#define | TIM_FLAG_COM (TIM_SR_COMIF)
#define | TIM_FLAG_TRIGGER (TIM_SR_TIF)
#define | TIM_FLAG_BREAK (TIM_SR_BIF)
#define | TIM_FLAG_CC1OF (TIM_SR_CC1OF)
#define | TIM_FLAG_CC2OF (TIM_SR_CC2OF)
#define | TIM_FLAG_CC3OF (TIM_SR_CC3OF)
#define | TIM_FLAG_CC4OF (TIM_SR_CC4OF)

Define Documentation

#define TIM_FLAG_BREAK (TIM_SR_BIF)

Definition at line 516 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1 (TIM_SR_CC1IF)

Definition at line 510 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)

Definition at line 520 of file stm32f3xx_hal_tim.h.

#define TIM_FLAG_CC2 (TIM_SR_CC2IF)

Definition at line 511 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)

Definition at line 521 of file stm32f3xx_hal_tim.h.

#define TIM_FLAG_CC3 (TIM_SR_CC3IF)

Definition at line 512 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)

Definition at line 522 of file stm32f3xx_hal_tim.h.

#define TIM_FLAG_CC4 (TIM_SR_CC4IF)

Definition at line 513 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)

Definition at line 523 of file stm32f3xx_hal_tim.h.

#define TIM_FLAG_COM (TIM_SR_COMIF)

Definition at line 514 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_TRIGGER (TIM_SR_TIF)

Definition at line 515 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_UPDATE (TIM_SR_UIF)

Definition at line 509 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Clock Source

Defines
TIM Clock Source
TIM Exported Constants

Defines

#define | TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define | TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define | TIM_CLOCKSOURCE_ITR0 (0x0000U)
#define | TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define | TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)

Define Documentation

#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)

Definition at line 540 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)

Definition at line 531 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)

Definition at line 532 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR0 (0x0000U)

Definition at line 533 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)

Definition at line 534 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)

Definition at line 535 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)

Definition at line 536 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)

Definition at line 538 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)

Definition at line 537 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)

Definition at line 539 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Clock Polarity

Defines
TIM Clock Polarity
TIM Exported Constants

Defines

#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIx clock sources

Definition at line 552 of file stm32f3xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIx clock sources

Definition at line 551 of file stm32f3xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx clock sources

Definition at line 548 of file stm32f3xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx clock sources

Definition at line 549 of file stm32f3xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIx clock sources

Definition at line 550 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM Clock Prescaler

Defines
TIM Clock Prescaler
TIM Exported Constants

Defines

#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 560 of file stm32f3xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Clock: Capture performed once every 2 events.

Definition at line 561 of file stm32f3xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Clock: Capture performed once every 4 events.

Definition at line 562 of file stm32f3xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Clock: Capture performed once every 8 events.

Definition at line 563 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM Clear Input Polarity

Defines
TIM Clear Input Polarity
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Define Documentation

#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx pin

Definition at line 571 of file stm32f3xx_hal_tim.h.

#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx pin

Definition at line 572 of file stm32f3xx_hal_tim.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Clear Input Prescaler

Defines
TIM Clear Input Prescaler
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 580 of file stm32f3xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR pin: Capture performed once every 2 events.

Definition at line 581 of file stm32f3xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR pin: Capture performed once every 4 events.

Definition at line 582 of file stm32f3xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR pin: Capture performed once every 8 events.

Definition at line 583 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM OSSR Off State Selection for Run mode state

Defines
TIM OSSR Off State Selection for Run mode state
TIM Exported Constants

Defines

#define | TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
#define | TIM_OSSR_DISABLE (0x0000U)

Define Documentation

#define TIM_OSSR_DISABLE (0x0000U)

Definition at line 592 of file stm32f3xx_hal_tim.h.

#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)

Definition at line 591 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM OSSI Off State Selection for Idle mode state

Defines
TIM OSSI Off State Selection for Idle mode state
TIM Exported Constants

Defines

#define | TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
#define | TIM_OSSI_DISABLE (0x0000U)

Define Documentation

#define TIM_OSSI_DISABLE (0x0000U)

Definition at line 601 of file stm32f3xx_hal_tim.h.

#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)

Definition at line 600 of file stm32f3xx_hal_tim.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Lock level

Defines
TIM Lock level
TIM Exported Constants

Defines

#define | TIM_LOCKLEVEL_OFF (0x0000U)
#define | TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define | TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define | TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)

Define Documentation

#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)

Definition at line 610 of file stm32f3xx_hal_tim.h.

#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)

Definition at line 611 of file stm32f3xx_hal_tim.h.

#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)

Definition at line 612 of file stm32f3xx_hal_tim.h.

#define TIM_LOCKLEVEL_OFF (0x0000U)

Definition at line 609 of file stm32f3xx_hal_tim.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Break Input Enable Disable

Defines
TIM Break Input Enable Disable
TIM Exported Constants

Defines

#define | TIM_BREAK_ENABLE (TIM_BDTR_BKE)
#define | TIM_BREAK_DISABLE (0x0000U)

Define Documentation

#define TIM_BREAK_DISABLE (0x0000U)

Definition at line 621 of file stm32f3xx_hal_tim.h.

#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)

Definition at line 620 of file stm32f3xx_hal_tim.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Break Input Polarity

Defines
TIM Break Input Polarity
TIM Exported Constants

Defines

#define | TIM_BREAKPOLARITY_LOW (0x0000U)
#define | TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)

Define Documentation

#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)

Definition at line 630 of file stm32f3xx_hal_tim.h.

#define TIM_BREAKPOLARITY_LOW (0x0000U)

Definition at line 629 of file stm32f3xx_hal_tim.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Automatic Output Enable

Defines
TIM Automatic Output Enable
TIM Exported Constants

Defines

#define | TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
#define | TIM_AUTOMATICOUTPUT_DISABLE (0x0000U)

Define Documentation

#define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U)

Definition at line 638 of file stm32f3xx_hal_tim.h.

#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)

Definition at line 637 of file stm32f3xx_hal_tim.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Master Mode Selection

Defines
TIM Master Mode Selection
TIM Exported Constants

Defines

#define | TIM_TRGO_RESET (0x0000U)
#define | TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define | TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define | TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
#define | TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
#define | TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Define Documentation

#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)

Definition at line 647 of file stm32f3xx_hal_tim.h.

#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Definition at line 649 of file stm32f3xx_hal_tim.h.

#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)

Definition at line 650 of file stm32f3xx_hal_tim.h.

#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))

Definition at line 651 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))

Definition at line 652 of file stm32f3xx_hal_tim.h.

#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Definition at line 653 of file stm32f3xx_hal_tim.h.

#define TIM_TRGO_RESET (0x0000U)

Definition at line 646 of file stm32f3xx_hal_tim.h.

#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)

Definition at line 648 of file stm32f3xx_hal_tim.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Master Slave Mode

Defines
TIM Master Slave Mode
TIM Exported Constants

Defines

#define | TIM_MASTERSLAVEMODE_ENABLE (0x0080U)
#define | TIM_MASTERSLAVEMODE_DISABLE (0x0000U)

Define Documentation

#define TIM_MASTERSLAVEMODE_DISABLE (0x0000U)

Definition at line 662 of file stm32f3xx_hal_tim.h.

#define TIM_MASTERSLAVEMODE_ENABLE (0x0080U)

Definition at line 661 of file stm32f3xx_hal_tim.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Trigger Selection

Defines
TIM Trigger Selection
TIM Exported Constants

Defines

#define | TIM_TS_ITR0 (0x0000U)
#define | TIM_TS_ITR1 (0x0010U)
#define | TIM_TS_ITR2 (0x0020U)
#define | TIM_TS_ITR3 (0x0030U)
#define | TIM_TS_TI1F_ED (0x0040U)
#define | TIM_TS_TI1FP1 (0x0050U)
#define | TIM_TS_TI2FP2 (0x0060U)
#define | TIM_TS_ETRF (0x0070U)
#define | TIM_TS_NONE (0xFFFFU)

Define Documentation

#define TIM_TS_ETRF (0x0070U)

Definition at line 677 of file stm32f3xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR0 (0x0000U)

Definition at line 670 of file stm32f3xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR1 (0x0010U)

Definition at line 671 of file stm32f3xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR2 (0x0020U)

Definition at line 672 of file stm32f3xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR3 (0x0030U)

Definition at line 673 of file stm32f3xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_NONE (0xFFFFU)

Definition at line 678 of file stm32f3xx_hal_tim.h.

#define TIM_TS_TI1F_ED (0x0040U)

Definition at line 674 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI1FP1 (0x0050U)

Definition at line 675 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI2FP2 (0x0060U)

Definition at line 676 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Trigger Polarity

Defines
TIM Trigger Polarity
TIM Exported Constants

Defines

#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 690 of file stm32f3xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 689 of file stm32f3xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx trigger sources

Definition at line 686 of file stm32f3xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx trigger sources

Definition at line 687 of file stm32f3xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 688 of file stm32f3xx_hal_tim.h.

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STM32F373xC HAL User Manual: TIM Trigger Prescaler

Defines
TIM Trigger Prescaler
TIM Exported Constants

Defines

#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 698 of file stm32f3xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Trigger: Capture performed once every 2 events.

Definition at line 699 of file stm32f3xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Trigger: Capture performed once every 4 events.

Definition at line 700 of file stm32f3xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Trigger: Capture performed once every 8 events.

Definition at line 701 of file stm32f3xx_hal_tim.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM TI1 Input Selection

Defines
TIM TI1 Input Selection
TIM Exported Constants

Defines

#define | TIM_TI1SELECTION_CH1 (0x0000U)
#define | TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)

Define Documentation

#define TIM_TI1SELECTION_CH1 (0x0000U)

Definition at line 709 of file stm32f3xx_hal_tim.h.

#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)

Definition at line 710 of file stm32f3xx_hal_tim.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM DMA Burst Length

Defines
TIM DMA Burst Length
TIM Exported Constants

Defines

#define | TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
#define | TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
#define | TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
#define | TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
#define | TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
#define | TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
#define | TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
#define | TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
#define | TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
#define | TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
#define | TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
#define | TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
#define | TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
#define | TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
#define | TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
#define | TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
#define | TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
#define | TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)

Define Documentation

#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)

Definition at line 727 of file stm32f3xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)

Definition at line 728 of file stm32f3xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)

Definition at line 729 of file stm32f3xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)

Definition at line 730 of file stm32f3xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)

Definition at line 731 of file stm32f3xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)

Definition at line 732 of file stm32f3xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)

Definition at line 733 of file stm32f3xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)

Definition at line 734 of file stm32f3xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)

Definition at line 735 of file stm32f3xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)

Definition at line 718 of file stm32f3xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)

Definition at line 719 of file stm32f3xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)

Definition at line 720 of file stm32f3xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)

Definition at line 721 of file stm32f3xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)

Definition at line 722 of file stm32f3xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)

Definition at line 723 of file stm32f3xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)

Definition at line 724 of file stm32f3xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)

Definition at line 725 of file stm32f3xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)

Definition at line 726 of file stm32f3xx_hal_tim.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM DMA Handle Index

Defines
TIM DMA Handle Index
TIM Exported Constants

Defines

#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0U)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x1U)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x2U)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x3U)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x4U)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U)

Define Documentation

#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U)

Index of the DMA handle used for Capture/Compare 1 DMA requests

Definition at line 744 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U)

Index of the DMA handle used for Capture/Compare 2 DMA requests

Definition at line 745 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U)

Index of the DMA handle used for Capture/Compare 3 DMA requests

Definition at line 746 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U)

Index of the DMA handle used for Capture/Compare 4 DMA requests

Definition at line 747 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U)

Index of the DMA handle used for Commutation DMA requests

Definition at line 748 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), and HAL_TIM_DMABurst_WriteStop().

#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U)

Index of the DMA handle used for Trigger DMA requests

Definition at line 749 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), and HAL_TIM_DMABurst_WriteStop().

#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U)

Index of the DMA handle used for Update DMA requests

Definition at line 743 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), and HAL_TIM_DMABurst_WriteStop().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Capture/Compare Channel State

Defines
TIM Capture/Compare Channel State
TIM Exported Constants

Defines

#define | TIM_CCx_ENABLE (0x0001U)
#define | TIM_CCx_DISABLE (0x0000U)
#define | TIM_CCxN_ENABLE (0x0004U)
#define | TIM_CCxN_DISABLE (0x0000U)

Define Documentation

#define TIM_CCx_DISABLE (0x0000U)

Definition at line 758 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

#define TIM_CCx_ENABLE (0x0001U)

Definition at line 757 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), and HAL_TIMEx_HallSensor_Start_IT().

#define TIM_CCxN_DISABLE (0x0000U)

Definition at line 760 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CCxN_ENABLE (0x0004U)

Definition at line 759 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Exported Macros

Defines
TIM Exported Macros
TIM

Defines

#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
Enables the specified TIM interrupt.
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Disables the specified TIM interrupt.
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
Enables the specified DMA request.
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Disables the specified DMA request.
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Checks whether the specified TIM interrupt flag is set or not.
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clears the specified TIM interrupt flag.
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks whether the specified TIM interrupt has occurred or not.
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
Clear the TIM interrupt pending bits.
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
Indicates whether or not the TIM Counter is used as downcounter.
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
Sets the TIM active prescaler register value on update event.
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Sets the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Gets the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Sets the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Gets the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Sets the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Gets the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Sets the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Gets the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Sets the TIM Capture x input polarity on runtime.

Define Documentation

#define __HAL_TIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clears the specified TIM interrupt flag.

Parameters:
__HANDLE__ specifies the TIM Handle.
__FLAG__ specifies the TIM interrupt flag to clear. This parameter can be one of the following values:
  • TIM_FLAG_UPDATE: Update interrupt flag
  • TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  • TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  • TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  • TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  • TIM_FLAG_COM: Commutation interrupt flag
  • TIM_FLAG_TRIGGER: Trigger interrupt flag
  • TIM_FLAG_BREAK: Break interrupt flag
  • TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  • TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  • TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  • TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 944 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))

Clear the TIM interrupt pending bits.

Parameters:
__HANDLE__ | TIM handle
__INTERRUPT__ | specifies the interrupt pending bit to clear.
Return values:
None

Definition at line 960 of file stm32f3xx_hal_tim.h.

#define __HAL_TIM_DISABLE ( __HANDLE__ )
Value:
do { \
                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
                            { \
                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
                            { \
                              (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
                            } \
                          } \
                        } while(0U)

Disable the TIM peripheral.

Parameters:
__HANDLE__ TIM handle
Return values:
None

Definition at line 800 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_DISABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__DMA__))

Disables the specified DMA request.

Parameters:
__HANDLE__ specifies the TIM Handle.
__DMA__ specifies the TIM DMA request to disable. This parameter can be one of the following values:
  • TIM_DMA_UPDATE: Update DMA request
  • TIM_DMA_CC1: Capture/Compare 1 DMA request
  • TIM_DMA_CC2: Capture/Compare 2 DMA request
  • TIM_DMA_CC3: Capture/Compare 3 DMA request
  • TIM_DMA_CC4: Capture/Compare 4 DMA request
  • TIM_DMA_COM: Commutation DMA request
  • TIM_DMA_TRIGGER: Trigger DMA request
Return values:
None

Definition at line 902 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define __HAL_TIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))

Disables the specified TIM interrupt.

Parameters:
__HANDLE__ specifies the TIM Handle.
__INTERRUPT__ specifies the TIM interrupt source to disable. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 870 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))

Enable the TIM peripheral.

Parameters:
__HANDLE__ TIM handle
Return values:
None

Definition at line 786 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_ENABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER |= (__DMA__))

Enables the specified DMA request.

Parameters:
__HANDLE__ specifies the TIM Handle.
__DMA__ specifies the TIM DMA request to enable. This parameter can be one of the following values:
  • TIM_DMA_UPDATE: Update DMA request
  • TIM_DMA_CC1: Capture/Compare 1 DMA request
  • TIM_DMA_CC2: Capture/Compare 2 DMA request
  • TIM_DMA_CC3: Capture/Compare 3 DMA request
  • TIM_DMA_CC4: Capture/Compare 4 DMA request
  • TIM_DMA_COM: Commutation DMA request
  • TIM_DMA_TRIGGER: Trigger DMA request
Return values:
None

Definition at line 886 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

#define __HAL_TIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))

Enables the specified TIM interrupt.

Parameters:
__HANDLE__ specifies the TIM Handle.
__INTERRUPT__ specifies the TIM interrupt source to enable. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 853 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start_IT(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_GET_AUTORELOAD ( __HANDLE__ ) ((__HANDLE__)->Instance->ARR)

Gets the TIM Autoreload Register value on runtime.

Parameters:
__HANDLE__ TIM handle.
Return values:
16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)

Definition at line 1012 of file stm32f3xx_hal_tim.h.

#define __HAL_TIM_GET_CLOCKDIVISION ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)

Gets the TIM Clock Division value on runtime.

Parameters:
__HANDLE__ TIM handle.
Return values:
The clock division can be one of the following values:
  • TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  • TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  • TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT

Definition at line 1041 of file stm32f3xx_hal_tim.h.

#define __HAL_TIM_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CNT)

Gets the TIM Counter Register value on runtime.

Parameters:
__HANDLE__ TIM handle.
Return values:
16-bit or 32-bit value of the timer counter register (TIMx_CNT)

Definition at line 991 of file stm32f3xx_hal_tim.h.

#define __HAL_TIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))

Checks whether the specified TIM interrupt flag is set or not.

Parameters:
__HANDLE__ specifies the TIM Handle.
__FLAG__ specifies the TIM interrupt flag to check. This parameter can be one of the following values:
  • TIM_FLAG_UPDATE: Update interrupt flag
  • TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  • TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  • TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  • TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  • TIM_FLAG_COM: Commutation interrupt flag
  • TIM_FLAG_TRIGGER: Trigger interrupt flag
  • TIM_FLAG_BREAK: Break interrupt flag
  • TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  • TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  • TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  • TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 923 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_GET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)

Gets the TIM Input Capture prescaler on runtime.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: get input capture 1 prescaler value
  • TIM_CHANNEL_2: get input capture 2 prescaler value
  • TIM_CHANNEL_3: get input capture 3 prescaler value
  • TIM_CHANNEL_4: get input capture 4 prescaler value
Return values:
The input capture prescaler can be one of the following values:
  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events

Definition at line 1083 of file stm32f3xx_hal_tim.h.

#define __HAL_TIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks whether the specified TIM interrupt has occurred or not.

Parameters:
__HANDLE__ | TIM handle
__INTERRUPT__ | specifies the TIM interrupt source to check.
Return values:
The state of TIM_IT (SET or RESET).

Definition at line 952 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_IS_TIM_COUNTING_DOWN ( __HANDLE__ ) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))

Indicates whether or not the TIM Counter is used as downcounter.

Parameters:
__HANDLE__ TIM handle.
Return values:
False (Counter used as upcounter) or True (Counter used as downcounter)
Note:
This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder mode.

Definition at line 968 of file stm32f3xx_hal_tim.h.

#define __HAL_TIM_MOE_DISABLE ( __HANDLE__ )
Value:
do { \
                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
                          { \
                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
                            { \
                              (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
                            } \
                            } \
                        } while(0U)

Disable the TIM main Output.

Parameters:
__HANDLE__ TIM handle
Return values:
None
Note:
The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled

Definition at line 818 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY ( __HANDLE__ ) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)

Disable the TIM main Output.

Parameters:
__HANDLE__ TIM handle
Return values:
None
Note:
The Main Output Enable of a timer instance is disabled uncondiotionally

Definition at line 836 of file stm32f3xx_hal_tim.h.

#define __HAL_TIM_MOE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))

Enable the TIM main Output.

Parameters:
__HANDLE__ TIM handle
Return values:
None

Definition at line 793 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)

Reset TIM handle state.

Parameters:
__HANDLE__ TIM handle.
Return values:
None

Definition at line 779 of file stm32f3xx_hal_tim.h.

#define __HAL_TIM_SET_AUTORELOAD | ( | __HANDLE__,
 |  | __AUTORELOAD__
 | ) |
Value:
do{                                                    \
                              (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
                              (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
                          } while(0U)

Sets the TIM Autoreload Register value on runtime without calling another time any Init function.

Parameters:
__HANDLE__ | TIM handle.
__AUTORELOAD__ | specifies the Counter register new value.
Return values:
None

Definition at line 1001 of file stm32f3xx_hal_tim.h.

#define __HAL_TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
do{                                                                     \
          TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
          TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
        }while(0U)

Sets the TIM Capture x input polarity on runtime.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__POLARITY__ Polarity for TIx source
  • TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
  • TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
Return values:
None

Definition at line 1129 of file stm32f3xx_hal_tim.h.

#define __HAL_TIM_SET_CLOCKDIVISION | ( | __HANDLE__,
 |  | __CKD__
 | ) |
Value:
do{                                                    \
                              (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
                              (__HANDLE__)->Instance->CR1 |= (__CKD__);                   \
                              (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
                          } while(0U)

Sets the TIM Clock Division value on runtime without calling another time any Init function.

Parameters:
__HANDLE__ TIM handle.
__CKD__ specifies the clock division value. This parameter can be one of the following value:
  • TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  • TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  • TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
Return values:
None

Definition at line 1026 of file stm32f3xx_hal_tim.h.

#define __HAL_TIM_SET_COUNTER | ( | __HANDLE__,
 |  | __COUNTER__
 | ) | ((__HANDLE__)->Instance->CNT = (__COUNTER__))

Sets the TIM Counter Register value on runtime.

Parameters:
__HANDLE__ | TIM handle.
__COUNTER__ | specifies the Counter register new value.
Return values:
None

Definition at line 984 of file stm32f3xx_hal_tim.h.

#define __HAL_TIM_SET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
do{                                                    \
                              TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
                              TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
                          } while(0U)

Sets the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__ICPSC__ specifies the Input Capture4 prescaler new value. This parameter can be one of the following values:
  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1062 of file stm32f3xx_hal_tim.h.

#define __HAL_TIM_SET_PRESCALER | ( | __HANDLE__,
 |  | __PRESC__
 | ) | ((__HANDLE__)->Instance->PSC = (__PRESC__))

Sets the TIM active prescaler register value on update event.

Parameters:
__HANDLE__ | TIM handle.
__PRESC__ | specifies the active prescaler register new value.
Return values:
None

Definition at line 976 of file stm32f3xx_hal_tim.h.

#define __HAL_TIM_URS_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))

Reset the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__ TIM handle.
Note:
When the USR bit of the TIMx_CR1 register is reset, any of the following events generate an update interrupt or DMA request (if enabled): (+) Counter overflow/underflow (+) Setting the UG bit (+) Update generation through the slave mode controller
Return values:
None

Definition at line 1111 of file stm32f3xx_hal_tim.h.

#define __HAL_TIM_URS_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))

Set the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__ TIM handle.
Note:
When the USR bit of the TIMx_CR1 register is set, only counter overflow/underflow generates an update interrupt or DMA request (if enabled)
Return values:
None

Definition at line 1097 of file stm32f3xx_hal_tim.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Private Constants

Defines
TIM Private Constants
TIM

Defines

#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

Define Documentation

#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))

Definition at line 1147 of file stm32f3xx_hal_tim.h.

#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

Definition at line 1148 of file stm32f3xx_hal_tim.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Private Macros

Defines
TIM Private Macros
TIM | TIMEx

Defines

#define | IS_TIM_COUNTER_MODE(MODE)
#define | IS_TIM_CLOCKDIVISION_DIV(DIV)
#define | IS_TIM_AUTORELOAD_PRELOAD(PRELOAD)
#define | IS_TIM_FAST_STATE(STATE)
#define | IS_TIM_OC_POLARITY(POLARITY)
#define | IS_TIM_OCN_POLARITY(POLARITY)
#define | IS_TIM_OCIDLE_STATE(STATE)
#define | IS_TIM_OCNIDLE_STATE(STATE)
#define | IS_TIM_IC_POLARITY(POLARITY)
#define | IS_TIM_IC_SELECTION(SELECTION)
#define | IS_TIM_IC_PRESCALER(PRESCALER)
#define | IS_TIM_OPM_MODE(MODE)
#define | IS_TIM_ENCODER_MODE(MODE)
#define | IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define | IS_TIM_CLOCKSOURCE(CLOCK)
#define | IS_TIM_CLOCKPOLARITY(POLARITY)
#define | IS_TIM_CLOCKPRESCALER(PRESCALER)
#define | IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
#define | IS_TIM_CLEARINPUT_POLARITY(POLARITY)
#define | IS_TIM_CLEARINPUT_PRESCALER(PRESCALER)
#define | IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
#define | IS_TIM_OSSR_STATE(STATE)
#define | IS_TIM_OSSI_STATE(STATE)
#define | IS_TIM_LOCK_LEVEL(LEVEL)
#define | IS_TIM_BREAK_STATE(STATE)
#define | IS_TIM_BREAK_POLARITY(POLARITY)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE)
#define | IS_TIM_TRGO_SOURCE(SOURCE)
#define | IS_TIM_MSM_STATE(STATE)
#define | IS_TIM_TRIGGER_SELECTION(SELECTION)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION)
#define | IS_TIM_TRIGGERPOLARITY(POLARITY)
#define | IS_TIM_TRIGGERPRESCALER(PRESCALER)
#define | IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
#define | IS_TIM_TI1SELECTION(TI1SELECTION)
#define | IS_TIM_DMA_LENGTH(LENGTH)
#define | IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
#define | IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
Set TIM IC prescaler.
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
Reset TIM IC prescaler.
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Set TIM IC polarity.
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)
Reset TIM IC polarity.
#define | IS_TIM_CHANNELS(CHANNEL)
#define | IS_TIM_OPM_CHANNELS(CHANNEL)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL)
#define | IS_TIM_PWM_MODE(MODE)
#define | IS_TIM_OC_MODE(MODE)
#define | IS_TIM_CLEARINPUT_SOURCE(SOURCE)
#define | IS_TIM_SLAVE_MODE(MODE)
#define | IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define | IS_TIM_DMA_BASE(BASE)
#define | IS_TIM_REMAP(REMAP)
#define | IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU)

Define Documentation

#define IS_TIM_AUTOMATIC_OUTPUT_STATE ( STATE )
Value:
(((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
                                              ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))

Definition at line 1263 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_AUTORELOAD_PRELOAD ( PRELOAD )
Value:
(((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))

Definition at line 1170 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_BREAK_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
                                         ((POLARITY) == TIM_BREAKPOLARITY_HIGH))

Definition at line 1260 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_STATE ( STATE )
Value:
(((STATE) == TIM_BREAK_ENABLE) || \
                                   ((STATE) == TIM_BREAK_DISABLE))

Definition at line 1257 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_CHANNELS ( CHANNEL )
Value:
(((CHANNEL) == TIM_CHANNEL_1) || \
                                  ((CHANNEL) == TIM_CHANNEL_2) || \
                                  ((CHANNEL) == TIM_CHANNEL_3) || \
                                  ((CHANNEL) == TIM_CHANNEL_4) || \
                                  ((CHANNEL) == TIM_CHANNEL_ALL))

Definition at line 607 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and TIM_CCxChannelCmd().

#define IS_TIM_CLEARINPUT_FILTER ( ICFILTER ) ((ICFILTER) <= 0xFU)

Definition at line 1244 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
                                             ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))

Definition at line 1236 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
                                                ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
                                                ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
                                                ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))

Definition at line 1239 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_SOURCE ( SOURCE )
Value:
(((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
                                           ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))

Definition at line 630 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLOCKDIVISION_DIV ( DIV )
Value:
(((DIV) == TIM_CLOCKDIVISION_DIV1) || \
                                       ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
                                       ((DIV) == TIM_CLOCKDIVISION_DIV4))

Definition at line 1166 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_CLOCKFILTER ( ICFILTER ) ((ICFILTER) <= 0xFU)

Definition at line 1234 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPOLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_CLOCKPOLARITY_INVERTED)    || \
                                        ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
                                        ((POLARITY) == TIM_CLOCKPOLARITY_RISING)      || \
                                        ((POLARITY) == TIM_CLOCKPOLARITY_FALLING)     || \
                                        ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))

Definition at line 1223 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPRESCALER ( PRESCALER )
Value:
(((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))

Definition at line 1229 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKSOURCE ( CLOCK )
Value:
(((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR0)     || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR1)     || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR2)     || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR3)     || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1ED)    || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1)      || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_TI2)      || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))

Definition at line 1212 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_COMPLEMENTARY_CHANNELS ( CHANNEL )
Value:
(((CHANNEL) == TIM_CHANNEL_1) || \
                                                ((CHANNEL) == TIM_CHANNEL_2) || \
                                                ((CHANNEL) == TIM_CHANNEL_3))

Definition at line 616 of file stm32f3xx_hal_tim_ex.h.

#define IS_TIM_COUNTER_MODE ( MODE )
Value:
(((MODE) == TIM_COUNTERMODE_UP)              || \
                                   ((MODE) == TIM_COUNTERMODE_DOWN)            || \
                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))

Definition at line 1160 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_DEADTIME ( DEADTIME ) ((DEADTIME) <= 0xFFU)

Definition at line 894 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_DMA_BASE ( BASE )
Value:
(((BASE) == TIM_DMABASE_CR1) || \
                               ((BASE) == TIM_DMABASE_CR2) || \
                               ((BASE) == TIM_DMABASE_SMCR) || \
                               ((BASE) == TIM_DMABASE_DIER) || \
                               ((BASE) == TIM_DMABASE_SR) || \
                               ((BASE) == TIM_DMABASE_EGR) || \
                               ((BASE) == TIM_DMABASE_CCMR1) || \
                               ((BASE) == TIM_DMABASE_CCMR2) || \
                               ((BASE) == TIM_DMABASE_CCER) || \
                               ((BASE) == TIM_DMABASE_CNT) || \
                               ((BASE) == TIM_DMABASE_PSC) || \
                               ((BASE) == TIM_DMABASE_ARR) || \
                               ((BASE) == TIM_DMABASE_RCR) || \
                               ((BASE) == TIM_DMABASE_CCR1) || \
                               ((BASE) == TIM_DMABASE_CCR2) || \
                               ((BASE) == TIM_DMABASE_CCR3) || \
                               ((BASE) == TIM_DMABASE_CCR4) || \
                               ((BASE) == TIM_DMABASE_BDTR) || \
                               ((BASE) == TIM_DMABASE_DCR) || \
                               ((BASE) == TIM_DMABASE_OR))

Definition at line 641 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

#define IS_TIM_DMA_DATA_LENGTH ( LENGTH ) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))

Definition at line 1328 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

#define IS_TIM_DMA_LENGTH ( LENGTH )
Value:
(((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))

Definition at line 1309 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

#define IS_TIM_DMA_SOURCE ( SOURCE ) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))

Definition at line 1209 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), and HAL_TIM_DMABurst_WriteStop().

#define IS_TIM_ENCODER_MODE ( MODE )
Value:
(((MODE) == TIM_ENCODERMODE_TI1) || \
                                   ((MODE) == TIM_ENCODERMODE_TI2) || \
                                   ((MODE) == TIM_ENCODERMODE_TI12))

Definition at line 1205 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

#define IS_TIM_EVENT_SOURCE ( SOURCE ) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))

Definition at line 639 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIM_GenerateEvent().

#define IS_TIM_FAST_STATE ( STATE )
Value:
(((STATE) == TIM_OCFAST_DISABLE) || \
                                  ((STATE) == TIM_OCFAST_ENABLE))

Definition at line 1173 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_IC_FILTER ( ICFILTER ) ((ICFILTER) <= 0xFU)

Definition at line 1330 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_ICPOLARITY_RISING)   || \
                                      ((POLARITY) == TIM_ICPOLARITY_FALLING)  || \
                                      ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))

Definition at line 1189 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == TIM_ICPSC_DIV1) || \
                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
                                        ((PRESCALER) == TIM_ICPSC_DIV8))

Definition at line 1197 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_SELECTION ( SELECTION )
Value:
(((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
                                        ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
                                        ((SELECTION) == TIM_ICSELECTION_TRC))

Definition at line 1193 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), and HAL_TIM_IC_ConfigChannel().

#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION ( SELECTION )
Value:
(((SELECTION) == TIM_TS_ITR0) || \
                                                           ((SELECTION) == TIM_TS_ITR1) || \
                                                           ((SELECTION) == TIM_TS_ITR2) || \
                                                           ((SELECTION) == TIM_TS_ITR3) || \
                                                           ((SELECTION) == TIM_TS_NONE))

Definition at line 1287 of file stm32f3xx_hal_tim.h.

#define IS_TIM_LOCK_LEVEL ( LEVEL )
Value:
(((LEVEL) == TIM_LOCKLEVEL_OFF) || \
                                  ((LEVEL) == TIM_LOCKLEVEL_1) || \
                                  ((LEVEL) == TIM_LOCKLEVEL_2) || \
                                  ((LEVEL) == TIM_LOCKLEVEL_3))

Definition at line 1252 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_MSM_STATE ( STATE )
Value:
(((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
                                 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))

Definition at line 1275 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_OC_MODE ( MODE )
Value:
(((MODE) == TIM_OCMODE_TIMING)           || \
                              ((MODE) == TIM_OCMODE_ACTIVE)           || \
                              ((MODE) == TIM_OCMODE_INACTIVE)         || \
                              ((MODE) == TIM_OCMODE_TOGGLE)           || \
                              ((MODE) == TIM_OCMODE_FORCED_ACTIVE)    || \
                              ((MODE) == TIM_OCMODE_FORCED_INACTIVE))

Definition at line 623 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIM_OC_ConfigChannel().

#define IS_TIM_OC_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_OCPOLARITY_HIGH) || \
                                      ((POLARITY) == TIM_OCPOLARITY_LOW))

Definition at line 1176 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_OCIDLE_STATE ( STATE )
Value:
(((STATE) == TIM_OCIDLESTATE_SET) || \
                                    ((STATE) == TIM_OCIDLESTATE_RESET))

Definition at line 1182 of file stm32f3xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

#define IS_TIM_OCN_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
                                       ((POLARITY) == TIM_OCNPOLARITY_LOW))

Definition at line 1179 of file stm32f3xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

#define IS_TIM_OCNIDLE_STATE ( STATE )
Value:
(((STATE) == TIM_OCNIDLESTATE_SET) || \
                                     ((STATE) == TIM_OCNIDLESTATE_RESET))

Definition at line 1185 of file stm32f3xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

#define IS_TIM_OPM_CHANNELS ( CHANNEL )
Value:
(((CHANNEL) == TIM_CHANNEL_1) || \
                                      ((CHANNEL) == TIM_CHANNEL_2))

Definition at line 613 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

#define IS_TIM_OPM_MODE ( MODE )
Value:
(((MODE) == TIM_OPMODE_SINGLE) || \
                              ((MODE) == TIM_OPMODE_REPETITIVE))

Definition at line 1202 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_Init().

#define IS_TIM_OSSI_STATE ( STATE )
Value:
(((STATE) == TIM_OSSI_ENABLE) || \
                                  ((STATE) == TIM_OSSI_DISABLE))

Definition at line 1249 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_OSSR_STATE ( STATE )
Value:
(((STATE) == TIM_OSSR_ENABLE) || \
                                  ((STATE) == TIM_OSSR_DISABLE))

Definition at line 1246 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_PWM_MODE ( MODE )
Value:
(((MODE) == TIM_OCMODE_PWM1) || \
                               ((MODE) == TIM_OCMODE_PWM2))

Definition at line 620 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_REMAP ( REMAP )
Value:
(((REMAP) == TIM_TIM2_TIM8_TRGO)  ||\
                                ((REMAP) == TIM_TIM2_ETH_PTP)    ||\
                                ((REMAP) == TIM_TIM2_USBFS_SOF)  ||\
                                ((REMAP) == TIM_TIM2_USBHS_SOF)  ||\
                                ((REMAP) == TIM_TIM14_GPIO)      ||\
                                ((REMAP) == TIM_TIM14_RTC)       ||\
                                ((REMAP) == TIM_TIM14_HSE)       ||\
                                ((REMAP) == TIM_TIM14_MCO))

Definition at line 870 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_RemapConfig().

#define IS_TIM_SLAVE_MODE ( MODE )
Value:
(((MODE) == TIM_SLAVEMODE_DISABLE) || \
                                 ((MODE) == TIM_SLAVEMODE_RESET) || \
                                 ((MODE) == TIM_SLAVEMODE_GATED) || \
                                 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
                                 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))

Definition at line 633 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define IS_TIM_TI1SELECTION ( TI1SELECTION )
Value:
(((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
                                             ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))

Definition at line 1306 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_ConfigTI1Input().

#define IS_TIM_TRGO_SOURCE ( SOURCE )
Value:
(((SOURCE) == TIM_TRGO_RESET) || \
                                    ((SOURCE) == TIM_TRGO_ENABLE) || \
                                    ((SOURCE) == TIM_TRGO_UPDATE) || \
                                    ((SOURCE) == TIM_TRGO_OC1) || \
                                    ((SOURCE) == TIM_TRGO_OC1REF) || \
                                    ((SOURCE) == TIM_TRGO_OC2REF) || \
                                    ((SOURCE) == TIM_TRGO_OC3REF) || \
                                    ((SOURCE) == TIM_TRGO_OC4REF))

Definition at line 1266 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_TRIGGER_SELECTION ( SELECTION )
Value:
(((SELECTION) == TIM_TS_ITR0) || \
                                             ((SELECTION) == TIM_TS_ITR1) || \
                                             ((SELECTION) == TIM_TS_ITR2) || \
                                             ((SELECTION) == TIM_TS_ITR3) || \
                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
                                             ((SELECTION) == TIM_TS_TI1FP1) || \
                                             ((SELECTION) == TIM_TS_TI2FP2) || \
                                             ((SELECTION) == TIM_TS_ETRF))

Definition at line 1278 of file stm32f3xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define IS_TIM_TRIGGERFILTER ( ICFILTER ) ((ICFILTER) <= 0xFU)

Definition at line 1304 of file stm32f3xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPOLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
                                              ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
                                              ((POLARITY) == TIM_TRIGGERPOLARITY_RISING     ) || \
                                              ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING    ) || \
                                              ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))

Definition at line 1293 of file stm32f3xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPRESCALER ( PRESCALER )
Value:
(((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))

Definition at line 1299 of file stm32f3xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_RESET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
 ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))

Reset TIM IC polarity.

Parameters:
__HANDLE__ | TIM handle
__CHANNEL__ | specifies TIM Channel
Return values:
None

Definition at line 1372 of file stm32f3xx_hal_tim.h.

#define TIM_RESET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))

Reset TIM IC prescaler.

Parameters:
__HANDLE__ | TIM handle
__CHANNEL__ | specifies TIM Channel
Return values:
None

Definition at line 1349 of file stm32f3xx_hal_tim.h.

#define TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))

Set TIM IC polarity.

Parameters:
__HANDLE__ | TIM handle
__CHANNEL__ | specifies TIM Channel
__POLARITY__ | specifies TIM Channel Polarity
Return values:
None

Definition at line 1361 of file stm32f3xx_hal_tim.h.

#define TIM_SET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))

Set TIM IC prescaler.

Parameters:
__HANDLE__ | TIM handle
__CHANNEL__ | specifies TIM Channel
__ICPSC__ | specifies the prescaler value.
Return values:
None

Definition at line 1338 of file stm32f3xx_hal_tim.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIMEx Private Functions

Functions
TIMEx Private Functions
TIMEx

Functions

static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.

Function Documentation

static void TIM_CCxNChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelNState
 | ) |  | [static]

Enables or disables the TIM Capture Compare Channel xN.

Parameters:
TIMx | to select the TIM peripheral
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
ChannelNState | specifies the TIM Channel CCxNE bit new state. This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
Return values:
None

Definition at line 2662 of file stm32f3xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

void TIMEx_DMACommutationCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 2641 of file stm32f3xx_hal_tim_ex.c.

References HAL_TIM_STATE_READY, HAL_TIMEx_CommutationCallback(), and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Timer Hall Sensor functions

Functions
Timer Hall Sensor functions
TIMEx Exported Functions

Timer Hall Sensor functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.

Detailed Description

Timer Hall Sensor functions.

  ==============================================================================
                      ##### Timer Hall Sensor functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure TIM HAL Sensor.
    (+) De-initialize TIM HAL Sensor.
    (+) Start the Hall Sensor Interface.
    (+) Stop the Hall Sensor Interface.
    (+) Start the Hall Sensor Interface and enable interrupts.
    (+) Stop the Hall Sensor Interface and disable interrupts.
    (+) Start the Hall Sensor Interface and enable DMA transfers.
    (+) Stop the Hall Sensor Interface and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Hall Sensor interface.

Parameters:
htim TIM Hall Sensor handle
Return values:
HAL status

Definition at line 266 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspDeInit(), TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_HallSensor_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Hall Sensor Interface and create the associated handle.

Parameters:
htim | TIM Encoder Interface handle
sConfig | TIM Hall Sensor configuration structure
Return values:
HAL status

Definition at line 187 of file stm32f3xx_hal_tim_ex.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_HallSensor_InitTypeDef::Commutation_Delay, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspInit(), TIM_HallSensor_InitTypeDef::IC1Filter, TIM_HallSensor_InitTypeDef::IC1Polarity, TIM_HallSensor_InitTypeDef::IC1Prescaler, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, TIM_HandleTypeDef::Lock, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_ICSELECTION_TRC, TIM_OC2_SetConfig(), TIM_OCFAST_DISABLE, TIM_OCIDLESTATE_RESET, TIM_OCMODE_PWM2, TIM_OCNIDLESTATE_RESET, TIM_OCNPOLARITY_HIGH, TIM_OCPOLARITY_HIGH, TIM_SLAVEMODE_RESET, TIM_TI1_SetConfig(), TIM_TRGO_OC2REF, and TIM_TS_TI1F_ED.

void HAL_TIMEx_HallSensor_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Hall Sensor MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 308 of file stm32f3xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_HallSensor_DeInit().

void HAL_TIMEx_HallSensor_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Hall Sensor MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 293 of file stm32f3xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_HallSensor_Init().

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface.

Parameters:
htim TIM Hall Sensor handle
Return values:
HAL status

Definition at line 323 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim | TIM Hall Sensor handle
pData | The destination Buffer address.
Length | The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 415 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_DMA_CC1, TIM_DMA_ID_CC1, TIM_DMACaptureCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim TIM Hall Sensor handle
Return values:
HAL status

Definition at line 365 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_IT_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Hall sensor Interface.

Parameters:
htim TIM Hall Sensor handle
Return values:
HAL status

Definition at line 344 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 462 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_DMA_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 389 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_IT_CC1.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Timer Complementary Output Compare functions

Functions
Timer Complementary Output Compare functions
TIMEx Exported Functions

Timer Complementary Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary Output Compare functions.

  ==============================================================================
              ##### Timer Complementary Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary Output Compare.
    (+) Stop the Complementary Output Compare.
    (+) Start the Complementary Output Compare and enable interrupts.
    (+) Stop the Complementary Output Compare and disable interrupts.
    (+) Start the Complementary Output Compare and enable DMA transfers.
    (+) Stop the Complementary Output Compare and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OCN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation on the complementary output.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 518 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim | TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 720 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM OC handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 578 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 548 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 835 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 645 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Timer Complementary PWM functions

Functions
Timer Complementary PWM functions
TIMEx Exported Functions

Timer Complementary PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary PWM functions.

  ==============================================================================
                 ##### Timer Complementary PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary PWM.
    (+) Stop the Complementary PWM.
    (+) Start the Complementary PWM and enable interrupts.
    (+) Stop the Complementary PWM and disable interrupts.
    (+) Start the Complementary PWM and enable DMA transfers.
    (+) Stop the Complementary PWM and disable DMA transfers.
    (+) Start the Complementary Input Capture measurement.
    (+) Stop the Complementary Input Capture.
    (+) Start the Complementary Input Capture and enable interrupts.
    (+) Stop the Complementary Input Capture and disable interrupts.
    (+) Start the Complementary Input Capture and enable DMA transfers.
    (+) Stop the Complementary Input Capture and disable DMA transfers.
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 935 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim | TIM handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1136 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 994 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 964 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1251 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1061 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Timer Complementary One Pulse functions

Functions
Timer Complementary One Pulse functions
TIMEx Exported Functions

Timer Complementary One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complemetary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Detailed Description

Timer Complementary One Pulse functions.

  ==============================================================================
                ##### Timer Complementary One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation on the complemetary output.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1338 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1392 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation on the complementary output.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1363 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1423 of file stm32f3xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_IT_CC1, and TIM_IT_CC2.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
TIMEx Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIM2 and TIM14 Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)

Detailed Description

Peripheral Control functions.

  ==============================================================================
                    ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Configure the commutation event in case of use of the Hall sensor interface.
      (+) Configure Output channels for OC and PWM mode.

      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master synchronization.
      (+) Configure timer remapping capabilities.
      (+) Enable or disable channel grouping

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_BreakDeadTimeConfigTypeDef * | sBreakDeadTimeConfig
 | ) |  |

Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).

Parameters:
htim | TIM handle
sBreakDeadTimeConfig | pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that contains the BDTR Register configuration information for the TIM peripheral.
Return values:
HAL status

Definition at line 2070 of file stm32f3xx_hal_tim_ex.c.

References assert_param, TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput, TIM_BreakDeadTimeConfigTypeDef::BreakPolarity, TIM_BreakDeadTimeConfigTypeDef::BreakState, TIM_BreakDeadTimeConfigTypeDef::DeadTime, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_AUTOMATIC_OUTPUT_STATE, IS_TIM_BREAK_POLARITY, IS_TIM_BREAK_STATE, IS_TIM_DEADTIME, IS_TIM_LOCK_LEVEL, IS_TIM_OSSI_STATE, IS_TIM_OSSR_STATE, TIM_BreakDeadTimeConfigTypeDef::LockLevel, TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode, TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_MasterConfigTypeDef * | sMasterConfig
 | ) |  |

Configures the TIM in master mode.

Parameters:
htim | TIM handle.
sMasterConfig | pointer to a TIM_MasterConfigTypeDef structure that contains the selected trigger output (TRGO) and the Master/Slave mode.
Return values:
HAL status

Definition at line 1960 of file stm32f3xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_MSM_STATE, IS_TIM_TRGO_SOURCE, TIM_MasterConfigTypeDef::MasterOutputTrigger, TIM_MasterConfigTypeDef::MasterSlaveMode, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_RemapConfig | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Remap
 | ) |  |

Configures the TIM2 and TIM14 Remapping input capabilities.

Parameters:
htim TIM handle.
Remap specifies the TIM remapping source. This parameter can be one of the following values: STM32F373xC, STM32F378xx:
  • TIM_TIM2_TIM8_TRGO: TIM8 TRGOUT is connected to TIM2_ITR1
  • TIM_TIM2_ETH_PTP: PTP trigger output is connected to TIM2_ITR1
  • TIM_TIM2_USBFS_SOF: OTG FS SOF is connected to the TIM2_ITR1 input
  • TIM_TIM2_USBHS_SOF: OTG HS SOF is connected to the TIM2_ITR1 input
  • TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
  • TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
  • TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
  • TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
Return values:
HAL status

Definition at line 2276 of file stm32f3xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_REMAP, and TIM_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Extension Callbacks functions

Functions
Extension Callbacks functions
TIMEx Exported Functions

Extension Callbacks functions. More...

Functions

__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non blocking mode.
__weak void | HAL_TIMEx_Break2Callback (TIM_HandleTypeDef *htim)
Hall Break2 detection callback in non blocking mode.

Detailed Description

Extension Callbacks functions.

  ==============================================================================
                    ##### Extended Callbacks functions #####
  ==============================================================================
  [..]
    This section provides Extended TIM callback functions:
    (+) Timer Commutation callback
    (+) Timer Break callback

Function Documentation

void HAL_TIMEx_Break2Callback ( TIM_HandleTypeDef * htim )

Hall Break2 detection callback in non blocking mode.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 2586 of file stm32f3xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler().

void HAL_TIMEx_BreakCallback ( TIM_HandleTypeDef * htim )

Hall Break detection callback in non blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2571 of file stm32f3xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler().

void HAL_TIMEx_CommutationCallback ( TIM_HandleTypeDef * htim )

Hall commutation changed callback in non blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2556 of file stm32f3xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler(), and TIMEx_DMACommutationCplt().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Extended Peripheral State functions

Functions
Extended Peripheral State functions
TIMEx Exported Functions

Extended Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface state.

Detailed Description

Extended Peripheral State functions.

  ==============================================================================
                ##### Extended Peripheral State functions #####
  ==============================================================================
  [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Hall Sensor interface state.

Parameters:
htim TIM Hall Sensor handle
Return values:
HAL state

Definition at line 2620 of file stm32f3xx_hal_tim_ex.c.

References TIM_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM_HallSensor_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_HallSensor_InitTypeDef Struct Reference
TIMEx Exported Types

TIM Hall sensor Configuration Structure definition. More...

#include <stm32f3xx_hal_tim_ex.h>

Data Fields

uint32_t | IC1Polarity
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | Commutation_Delay

Detailed Description

TIM Hall sensor Configuration Structure definition.

Definition at line 64 of file stm32f3xx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_HallSensor_InitTypeDef::Commutation_Delay

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU

Definition at line 75 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU

Definition at line 73 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 67 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 70 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_tim_ex.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM_MasterConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_MasterConfigTypeDef Struct Reference
TIMEx Exported Types

TIM Master configuration Structure definition. More...

#include <stm32f3xx_hal_tim_ex.h>

Data Fields

uint32_t | MasterOutputTrigger
uint32_t | MasterSlaveMode

Detailed Description

TIM Master configuration Structure definition.

Note:
STM32F373xC and STM32F378xx: timer instances provide a single TRGO output

Definition at line 85 of file stm32f3xx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_MasterConfigTypeDef::MasterOutputTrigger

Trigger output (TRGO) selection This parameter can be a value of TIM Master Mode Selection

Definition at line 86 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

uint32_t TIM_MasterConfigTypeDef::MasterSlaveMode

Master/slave mode selection This parameter can be a value of TIM Master Slave Mode

Definition at line 88 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_tim_ex.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM_BreakDeadTimeConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_BreakDeadTimeConfigTypeDef Struct Reference
TIMEx Exported Types

TIM Break and Dead time configuration Structure definition. More...

#include <stm32f3xx_hal_tim_ex.h>

Data Fields

uint32_t | OffStateRunMode
uint32_t | OffStateIDLEMode
uint32_t | LockLevel
uint32_t | DeadTime
uint32_t | BreakState
uint32_t | BreakPolarity
uint32_t | AutomaticOutput

Detailed Description

TIM Break and Dead time configuration Structure definition.

Note:
STM32F373xC and STM32F378xx: single break input with configurable polarity.

Definition at line 96 of file stm32f3xx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput

TIM Automatic Output Enable state This parameter can be a value of TIM Automatic Output Enable

Definition at line 110 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakPolarity

TIM Break input polarity This parameter can be a value of TIM Break Input Polarity

Definition at line 108 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakState

TIM Break State This parameter can be a value of TIM Break Input Enable Disable

Definition at line 106 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::DeadTime

TIM dead Time This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFFU

Definition at line 104 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::LockLevel

TIM Lock level This parameter can be a value of TIM Lock level

Definition at line 102 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode

TIM off state in IDLE mode This parameter can be a value of TIM OSSI Off State Selection for Idle mode state

Definition at line 100 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode

TIM off state in run mode This parameter can be a value of TIM OSSR Off State Selection for Run mode state

Definition at line 98 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_tim_ex.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIMEx Channel

Defines
TIMEx Channel
TIMEx Exported Constants

Defines

#define | TIM_CHANNEL_1 (0x0000U)
#define | TIM_CHANNEL_2 (0x0004U)
#define | TIM_CHANNEL_3 (0x0008U)
#define | TIM_CHANNEL_4 (0x000CU)
#define | TIM_CHANNEL_ALL (0x0018U)

Define Documentation

#define TIM_CHANNEL_1 (0x0000U)

Definition at line 181 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), and TIM_OC1_SetConfig().

#define TIM_CHANNEL_2 (0x0004U)

Definition at line 182 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), and TIM_OC2_SetConfig().

#define TIM_CHANNEL_3 (0x0008U)

Definition at line 183 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), and TIM_OC3_SetConfig().

#define TIM_CHANNEL_4 (0x000CU)

Definition at line 184 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CHANNEL_ALL (0x0018U)

Definition at line 185 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIM_Encoder_Start_DMA().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIMEx Output Compare and PWM Modes

Defines
TIMEx Output Compare and PWM Modes
TIMEx Exported Constants

Defines

#define | TIM_OCMODE_TIMING (0x0000U)
#define | TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M)
#define | TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)

Define Documentation

#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)

Definition at line 194 of file stm32f3xx_hal_tim_ex.h.

#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)

Definition at line 199 of file stm32f3xx_hal_tim_ex.h.

#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)

Definition at line 200 of file stm32f3xx_hal_tim_ex.h.

#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)

Definition at line 195 of file stm32f3xx_hal_tim_ex.h.

#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)

Definition at line 197 of file stm32f3xx_hal_tim_ex.h.

#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M)

Definition at line 198 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCMODE_TIMING (0x0000U)

Definition at line 193 of file stm32f3xx_hal_tim_ex.h.

#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)

Definition at line 196 of file stm32f3xx_hal_tim_ex.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIMEx Clear Input Source

Defines
TIMEx Clear Input Source
TIMEx Exported Constants

Defines

#define | TIM_CLEARINPUTSOURCE_ETR (0x0001U)
#define | TIM_CLEARINPUTSOURCE_NONE (0x0000U)

Define Documentation

#define TIM_CLEARINPUTSOURCE_ETR (0x0001U)

Definition at line 208 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_NONE (0x0000U)

Definition at line 209 of file stm32f3xx_hal_tim_ex.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIMEx Slave Mode

Defines
TIMEx Slave Mode
TIMEx Exported Constants

Defines

#define | TIM_SLAVEMODE_DISABLE (0x0000U)
#define | TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
#define | TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
#define | TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
#define | TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))

Define Documentation

#define TIM_SLAVEMODE_DISABLE (0x0000U)

Definition at line 217 of file stm32f3xx_hal_tim_ex.h.

#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))

Definition at line 221 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_ITRx_SetConfig().

#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))

Definition at line 219 of file stm32f3xx_hal_tim_ex.h.

#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))

Definition at line 218 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))

Definition at line 220 of file stm32f3xx_hal_tim_ex.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIMEx Event Source

Defines
TIMEx Event Source
TIMEx Exported Constants

Defines

#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG

Define Documentation

#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG

A break event is generated

Definition at line 236 of file stm32f3xx_hal_tim_ex.h.

#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G

A capture/compare event is generated on channel 1U

Definition at line 230 of file stm32f3xx_hal_tim_ex.h.

#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G

A capture/compare event is generated on channel 2U

Definition at line 231 of file stm32f3xx_hal_tim_ex.h.

#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G

A capture/compare event is generated on channel 3U

Definition at line 232 of file stm32f3xx_hal_tim_ex.h.

#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G

A capture/compare event is generated on channel 4U

Definition at line 233 of file stm32f3xx_hal_tim_ex.h.

#define TIM_EVENTSOURCE_COM TIM_EGR_COMG

A commutation event is generated

Definition at line 234 of file stm32f3xx_hal_tim_ex.h.

#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG

A trigger event is generated

Definition at line 235 of file stm32f3xx_hal_tim_ex.h.

#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG

Reinitialize the counter and generates an update of the registers

Definition at line 229 of file stm32f3xx_hal_tim_ex.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIMEx DMA BAse Address

Defines
TIMEx DMA BAse Address
TIMEx Exported Constants

Defines

#define | TIM_DMABASE_CR1 (0x00000000U)
#define | TIM_DMABASE_CR2 (0x00000001U)
#define | TIM_DMABASE_SMCR (0x00000002U)
#define | TIM_DMABASE_DIER (0x00000003U)
#define | TIM_DMABASE_SR (0x00000004U)
#define | TIM_DMABASE_EGR (0x00000005U)
#define | TIM_DMABASE_CCMR1 (0x00000006U)
#define | TIM_DMABASE_CCMR2 (0x00000007U)
#define | TIM_DMABASE_CCER (0x00000008U)
#define | TIM_DMABASE_CNT (0x00000009U)
#define | TIM_DMABASE_PSC (0x0000000AU)
#define | TIM_DMABASE_ARR (0x0000000BU)
#define | TIM_DMABASE_RCR (0x0000000CU)
#define | TIM_DMABASE_CCR1 (0x0000000DU)
#define | TIM_DMABASE_CCR2 (0x0000000EU)
#define | TIM_DMABASE_CCR3 (0x0000000FU)
#define | TIM_DMABASE_CCR4 (0x00000010U)
#define | TIM_DMABASE_BDTR (0x00000011U)
#define | TIM_DMABASE_DCR (0x00000012U)
#define | TIM_DMABASE_OR (0x00000013U)

Define Documentation

#define TIM_DMABASE_ARR (0x0000000BU)

Definition at line 255 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_BDTR (0x00000011U)

Definition at line 261 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_CCER (0x00000008U)

Definition at line 252 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_CCMR1 (0x00000006U)

Definition at line 250 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_CCMR2 (0x00000007U)

Definition at line 251 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_CCR1 (0x0000000DU)

Definition at line 257 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_CCR2 (0x0000000EU)

Definition at line 258 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_CCR3 (0x0000000FU)

Definition at line 259 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_CCR4 (0x00000010U)

Definition at line 260 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_CNT (0x00000009U)

Definition at line 253 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_CR1 (0x00000000U)

Definition at line 244 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_CR2 (0x00000001U)

Definition at line 245 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_DCR (0x00000012U)

Definition at line 262 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_DIER (0x00000003U)

Definition at line 247 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_EGR (0x00000005U)

Definition at line 249 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_OR (0x00000013U)

Definition at line 263 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_PSC (0x0000000AU)

Definition at line 254 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_RCR (0x0000000CU)

Definition at line 256 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_SMCR (0x00000002U)

Definition at line 246 of file stm32f3xx_hal_tim_ex.h.

#define TIM_DMABASE_SR (0x00000004U)

Definition at line 248 of file stm32f3xx_hal_tim_ex.h.

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STM32F373xC HAL User Manual: TIMEx remapping

Defines
TIMEx remapping
TIMEx Exported Constants

Defines

#define | TIM_TIM2_TIM8_TRGO (0x00000000U)
#define | TIM_TIM2_ETH_PTP (0x00000400U)
#define | TIM_TIM2_USBFS_SOF (0x00000800U)
#define | TIM_TIM2_USBHS_SOF (0x00000C00U)
#define | TIM_TIM14_GPIO (0x00000000U)
#define | TIM_TIM14_RTC (0x00000001U)
#define | TIM_TIM14_HSE (0x00000002U)
#define | TIM_TIM14_MCO (0x00000003U)

Define Documentation

#define TIM_TIM14_GPIO (0x00000000U)

TIM14 TI1 is connected to GPIO

Definition at line 568 of file stm32f3xx_hal_tim_ex.h.

#define TIM_TIM14_HSE (0x00000002U)

TIM14 TI1 is connected to HSE/32U

Definition at line 570 of file stm32f3xx_hal_tim_ex.h.

#define TIM_TIM14_MCO (0x00000003U)

TIM14 TI1 is connected to MCO

Definition at line 571 of file stm32f3xx_hal_tim_ex.h.

#define TIM_TIM14_RTC (0x00000001U)

TIM14 TI1 is connected to RTC_clock

Definition at line 569 of file stm32f3xx_hal_tim_ex.h.

#define TIM_TIM2_ETH_PTP (0x00000400U)

PTP trigger output is connected to TIM2_ITR1

Definition at line 565 of file stm32f3xx_hal_tim_ex.h.

#define TIM_TIM2_TIM8_TRGO (0x00000000U)

TIM8 TRGOUT is connected to TIM2_ITR1

Definition at line 564 of file stm32f3xx_hal_tim_ex.h.

#define TIM_TIM2_USBFS_SOF (0x00000800U)

OTG FS SOF is connected to the TIM2_ITR1 input

Definition at line 566 of file stm32f3xx_hal_tim_ex.h.

#define TIM_TIM2_USBHS_SOF (0x00000C00U)

OTG HS SOF is connected to the TIM2_ITR1 input

Definition at line 567 of file stm32f3xx_hal_tim_ex.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIMEx Exported Macros

Defines
TIMEx Exported Macros
TIMEx

Defines

#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
Sets the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
Gets the TIM Capture Compare Register value on runtime.
#define | __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Sets the TIM Output compare preload.
#define | __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Resets the TIM Output compare preload.

Define Documentation

#define __HAL_TIM_DISABLE_OCxPRELOAD | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
         ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
         ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
         ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))

Resets the TIM Output compare preload.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
None

Definition at line 966 of file stm32f3xx_hal_tim_ex.h.

#define __HAL_TIM_ENABLE_OCxPRELOAD | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
         ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
         ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
         ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))

Sets the TIM Output compare preload.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
None

Definition at line 949 of file stm32f3xx_hal_tim_ex.h.

#define __HAL_TIM_GET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))

Gets the TIM Capture Compare Register value on runtime.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channel associated with the capture compare register This parameter can be one of the following values:
  • TIM_CHANNEL_1: get capture/compare 1 register value
  • TIM_CHANNEL_2: get capture/compare 2 register value
  • TIM_CHANNEL_3: get capture/compare 3 register value
  • TIM_CHANNEL_4: get capture/compare 4 register value
Return values:
None

Definition at line 935 of file stm32f3xx_hal_tim_ex.h.

#define __HAL_TIM_SET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __COMPARE__
 | ) | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))

Sets the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.

Parameters:
__HANDLE__ | TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__COMPARE__ | specifies the Capture Compare register new value.
Return values:
None

Definition at line 921 of file stm32f3xx_hal_tim_ex.h.

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STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_TSC_Init (TSC_HandleTypeDef *htsc)
Initialize the TSC peripheral according to the specified parameters in the TSC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_TSC_DeInit (TSC_HandleTypeDef *htsc)
Deinitialize the TSC peripheral registers to their default reset values.
__weak void | HAL_TSC_MspInit (TSC_HandleTypeDef *htsc)
Initialize the TSC MSP.
__weak void | HAL_TSC_MspDeInit (TSC_HandleTypeDef *htsc)
DeInitialize the TSC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the TSC.
      (+) De-initialize the TSC.

Function Documentation

HAL_StatusTypeDef HAL_TSC_DeInit ( TSC_HandleTypeDef * htsc )

Deinitialize the TSC peripheral registers to their default reset values.

Parameters:
htsc TSC handle
Return values:
HAL status

Definition at line 299 of file stm32f3xx_hal_tsc.c.

References assert_param, HAL_TSC_MspDeInit(), HAL_TSC_STATE_BUSY, HAL_TSC_STATE_RESET, TSC_HandleTypeDef::Instance, and TSC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TSC_Init ( TSC_HandleTypeDef * htsc )

Initialize the TSC peripheral according to the specified parameters in the TSC_InitTypeDef structure and initialize the associated handle.

Parameters:
htsc TSC handle
Return values:
HAL status

Definition at line 211 of file stm32f3xx_hal_tsc.c.

References TSC_InitTypeDef::AcquisitionMode, assert_param, TSC_InitTypeDef::ChannelIOs, TSC_InitTypeDef::CTPulseHighLength, TSC_InitTypeDef::CTPulseLowLength, HAL_TSC_MspInit(), HAL_TSC_STATE_BUSY, HAL_TSC_STATE_READY, HAL_TSC_STATE_RESET, TSC_HandleTypeDef::Init, TSC_HandleTypeDef::Instance, TSC_InitTypeDef::IODefaultMode, IS_TSC_ACQ_MODE, IS_TSC_CTPH, IS_TSC_CTPL, IS_TSC_IODEF, IS_TSC_MCE_IT, IS_TSC_MCV, IS_TSC_PG_PRESC, IS_TSC_SS, IS_TSC_SS_PRESC, IS_TSC_SSD, IS_TSC_SYNC_POL, TSC_HandleTypeDef::Lock, TSC_InitTypeDef::MaxCountInterrupt, TSC_InitTypeDef::MaxCountValue, TSC_InitTypeDef::PulseGeneratorPrescaler, TSC_InitTypeDef::SamplingIOs, TSC_InitTypeDef::ShieldIOs, TSC_InitTypeDef::SpreadSpectrum, TSC_InitTypeDef::SpreadSpectrumDeviation, TSC_InitTypeDef::SpreadSpectrumPrescaler, TSC_HandleTypeDef::State, TSC_InitTypeDef::SynchroPinPolarity, TSC_extract_groups(), TSC_FLAG_EOA, TSC_FLAG_MCE, TSC_IT_EOA, and TSC_IT_MCE.

void HAL_TSC_MspDeInit ( TSC_HandleTypeDef * htsc )

DeInitialize the TSC MSP.

Parameters:
htsc pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
None

Definition at line 348 of file stm32f3xx_hal_tsc.c.

Referenced by HAL_TSC_DeInit().

void HAL_TSC_MspInit ( TSC_HandleTypeDef * htsc )

Initialize the TSC MSP.

Parameters:
htsc pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
None

Definition at line 332 of file stm32f3xx_hal_tsc.c.

Referenced by HAL_TSC_Init().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
Exported Functions

Input and Output operation functions. More...

Functions

HAL_StatusTypeDef | HAL_TSC_Start (TSC_HandleTypeDef *htsc)
Start the acquisition.
HAL_StatusTypeDef | HAL_TSC_Start_IT (TSC_HandleTypeDef *htsc)
Start the acquisition in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_Stop (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in polling mode.
HAL_StatusTypeDef | HAL_TSC_Stop_IT (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_PollForAcquisition (TSC_HandleTypeDef *htsc)
Start acquisition and wait until completion.
TSC_GroupStatusTypeDef | HAL_TSC_GroupGetStatus (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition status for a group.
uint32_t | HAL_TSC_GroupGetValue (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition measure for a group.

Detailed Description

Input and Output operation functions.

 ===============================================================================
             ##### IO Operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start acquisition in polling mode.
      (+) Start acquisition in interrupt mode.
      (+) Stop conversion in polling mode.
      (+) Stop conversion in interrupt mode.
      (+) Poll for acquisition completed.
      (+) Get group acquisition status.
      (+) Get group acquisition value.

Function Documentation

TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus | ( | TSC_HandleTypeDef * | htsc,
 |  | uint32_t | gx_index
 | ) |  |

Get the acquisition status for a group.

Parameters:
htsc | pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
gx_index | Index of the group
Return values:
Group status

Definition at line 582 of file stm32f3xx_hal_tsc.c.

References __HAL_TSC_GET_GROUP_STATUS, assert_param, TSC_HandleTypeDef::Instance, and IS_TSC_GROUP_INDEX.

uint32_t HAL_TSC_GroupGetValue | ( | TSC_HandleTypeDef * | htsc,
 |  | uint32_t | gx_index
 | ) |  |

Get the acquisition measure for a group.

Parameters:
htsc | pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
gx_index | Index of the group
Return values:
Acquisition measure

Definition at line 599 of file stm32f3xx_hal_tsc.c.

References assert_param, TSC_HandleTypeDef::Instance, and IS_TSC_GROUP_INDEX.

HAL_StatusTypeDef HAL_TSC_PollForAcquisition ( TSC_HandleTypeDef * htsc )

Start acquisition and wait until completion.

Note:
There is no need of a timeout parameter as the max count error is already managed by the TSC peripheral.
Parameters:
htsc pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL state

Definition at line 555 of file stm32f3xx_hal_tsc.c.

References assert_param, HAL_TSC_GetState(), HAL_TSC_STATE_BUSY, and TSC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_TSC_Start ( TSC_HandleTypeDef * htsc )

Start the acquisition.

Parameters:
htsc pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL status

Definition at line 387 of file stm32f3xx_hal_tsc.c.

References __HAL_TSC_CLEAR_FLAG, __HAL_TSC_DISABLE_IT, __HAL_TSC_SET_IODEF_INFLOAT, __HAL_TSC_SET_IODEF_OUTPPLOW, __HAL_TSC_START_ACQ, assert_param, HAL_TSC_STATE_BUSY, TSC_HandleTypeDef::Init, TSC_HandleTypeDef::Instance, TSC_InitTypeDef::IODefaultMode, TSC_HandleTypeDef::State, TSC_FLAG_EOA, TSC_FLAG_MCE, TSC_IODEF_OUT_PP_LOW, TSC_IT_EOA, and TSC_IT_MCE.

HAL_StatusTypeDef HAL_TSC_Start_IT ( TSC_HandleTypeDef * htsc )

Start the acquisition in interrupt mode.

Parameters:
htsc pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL status.

Definition at line 430 of file stm32f3xx_hal_tsc.c.

References __HAL_TSC_CLEAR_FLAG, __HAL_TSC_DISABLE_IT, __HAL_TSC_ENABLE_IT, __HAL_TSC_SET_IODEF_INFLOAT, __HAL_TSC_SET_IODEF_OUTPPLOW, __HAL_TSC_START_ACQ, assert_param, HAL_TSC_STATE_BUSY, TSC_HandleTypeDef::Init, TSC_HandleTypeDef::Instance, TSC_InitTypeDef::IODefaultMode, IS_TSC_MCE_IT, TSC_InitTypeDef::MaxCountInterrupt, TSC_HandleTypeDef::State, TSC_FLAG_EOA, TSC_FLAG_MCE, TSC_IODEF_OUT_PP_LOW, TSC_IT_EOA, and TSC_IT_MCE.

HAL_StatusTypeDef HAL_TSC_Stop ( TSC_HandleTypeDef * htsc )

Stop the acquisition previously launched in polling mode.

Parameters:
htsc pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL status

Definition at line 484 of file stm32f3xx_hal_tsc.c.

References __HAL_TSC_CLEAR_FLAG, __HAL_TSC_SET_IODEF_OUTPPLOW, __HAL_TSC_STOP_ACQ, assert_param, HAL_TSC_STATE_READY, TSC_HandleTypeDef::Instance, TSC_HandleTypeDef::State, TSC_FLAG_EOA, and TSC_FLAG_MCE.

HAL_StatusTypeDef HAL_TSC_Stop_IT ( TSC_HandleTypeDef * htsc )

Stop the acquisition previously launched in interrupt mode.

Parameters:
htsc pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL status

Definition at line 517 of file stm32f3xx_hal_tsc.c.

References __HAL_TSC_CLEAR_FLAG, __HAL_TSC_DISABLE_IT, __HAL_TSC_SET_IODEF_OUTPPLOW, __HAL_TSC_STOP_ACQ, assert_param, HAL_TSC_STATE_READY, TSC_HandleTypeDef::Instance, TSC_HandleTypeDef::State, TSC_FLAG_EOA, TSC_FLAG_MCE, TSC_IT_EOA, and TSC_IT_MCE.

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STM32F373xC HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TSC_IOConfig (TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config)
Configure TSC IOs.
HAL_StatusTypeDef | HAL_TSC_IODischarge (TSC_HandleTypeDef *htsc, uint32_t choice)
Discharge TSC IOs.

Detailed Description

Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure TSC IOs
      (+) Discharge TSC IOs

Function Documentation

HAL_StatusTypeDef HAL_TSC_IOConfig | ( | TSC_HandleTypeDef * | htsc,
 |  | TSC_IOConfigTypeDef * | config
 | ) |  |

Configure TSC IOs.

Parameters:
htsc | pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
config | pointer to the configuration structure.
Return values:
HAL status

Definition at line 634 of file stm32f3xx_hal_tsc.c.

References __HAL_TSC_STOP_ACQ, assert_param, TSC_IOConfigTypeDef::ChannelIOs, TSC_HandleTypeDef::Instance, TSC_IOConfigTypeDef::SamplingIOs, TSC_IOConfigTypeDef::ShieldIOs, and TSC_extract_groups().

HAL_StatusTypeDef HAL_TSC_IODischarge | ( | TSC_HandleTypeDef * | htsc,
 |  | uint32_t | choice
 | ) |  |

Discharge TSC IOs.

Parameters:
htsc | pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
choice | enable or disable
Return values:
HAL status

Definition at line 671 of file stm32f3xx_hal_tsc.c.

References __HAL_TSC_SET_IODEF_INFLOAT, __HAL_TSC_SET_IODEF_OUTPPLOW, assert_param, and TSC_HandleTypeDef::Instance.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_TSC_StateTypeDef HAL_TSC_GetState (TSC_HandleTypeDef *htsc)
Return the TSC handle state.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Get TSC state.

Function Documentation

HAL_TSC_StateTypeDef HAL_TSC_GetState ( TSC_HandleTypeDef * htsc )

Return the TSC handle state.

Parameters:
htsc pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL state

Definition at line 720 of file stm32f3xx_hal_tsc.c.

References __HAL_TSC_GET_FLAG, assert_param, HAL_TSC_STATE_BUSY, HAL_TSC_STATE_ERROR, HAL_TSC_STATE_READY, TSC_HandleTypeDef::Instance, TSC_HandleTypeDef::State, TSC_FLAG_EOA, and TSC_FLAG_MCE.

Referenced by HAL_TSC_PollForAcquisition().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
Exported Functions

Functions

void | HAL_TSC_IRQHandler (TSC_HandleTypeDef *htsc)
Handle TSC interrupt request.
__weak void | HAL_TSC_ConvCpltCallback (TSC_HandleTypeDef *htsc)
Acquisition completed callback in non-blocking mode.
__weak void | HAL_TSC_ErrorCallback (TSC_HandleTypeDef *htsc)
Error callback in non-blocking mode.

Function Documentation

void HAL_TSC_ConvCpltCallback ( TSC_HandleTypeDef * htsc )

Acquisition completed callback in non-blocking mode.

Parameters:
htsc pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
None

Definition at line 799 of file stm32f3xx_hal_tsc.c.

Referenced by HAL_TSC_IRQHandler().

void HAL_TSC_ErrorCallback ( TSC_HandleTypeDef * htsc )

Error callback in non-blocking mode.

Parameters:
htsc pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
None

Definition at line 815 of file stm32f3xx_hal_tsc.c.

Referenced by HAL_TSC_IRQHandler().

void HAL_TSC_IRQHandler ( TSC_HandleTypeDef * htsc )

Handle TSC interrupt request.

Parameters:
htsc pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
None

Definition at line 762 of file stm32f3xx_hal_tsc.c.

References __HAL_TSC_CLEAR_FLAG, __HAL_TSC_GET_FLAG, assert_param, HAL_TSC_ConvCpltCallback(), HAL_TSC_ErrorCallback(), HAL_TSC_STATE_ERROR, HAL_TSC_STATE_READY, TSC_HandleTypeDef::Instance, TSC_HandleTypeDef::State, TSC_FLAG_EOA, and TSC_FLAG_MCE.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Private Functions

Functions
Private Functions
TSC

Functions

static uint32_t TSC_extract_groups (uint32_t iomask)
Utility function used to set the acquired groups mask.

Function Documentation

static uint32_t TSC_extract_groups ( uint32_t iomask ) [static]

Utility function used to set the acquired groups mask.

Parameters:
iomask Channels IOs mask
Return values:
Acquired groups mask

Definition at line 843 of file stm32f3xx_hal_tsc.c.

References TSC_NB_OF_GROUPS.

Referenced by HAL_TSC_Init(), and HAL_TSC_IOConfig().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TSC Exported Types

Data Structures | Enumerations
TSC Exported Types
TSC

Data Structures

struct | TSC_InitTypeDef
TSC init structure definition. More...
struct | TSC_IOConfigTypeDef
TSC IOs configuration structure definition. More...
struct | TSC_HandleTypeDef
TSC handle Structure definition. More...

Enumerations

enum | HAL_TSC_StateTypeDef { HAL_TSC_STATE_RESET = 0x00U, HAL_TSC_STATE_READY = 0x01U, HAL_TSC_STATE_BUSY = 0x02U, HAL_TSC_STATE_ERROR = 0x03U }
TSC state structure definition. More...
enum | TSC_GroupStatusTypeDef { TSC_GROUP_ONGOING = 0x00U, TSC_GROUP_COMPLETED = 0x01U }
TSC group status structure definition. More...

Enumeration Type Documentation

enum HAL_TSC_StateTypeDef

TSC state structure definition.

Enumerator:
HAL_TSC_STATE_RESET

TSC registers have their reset value

HAL_TSC_STATE_READY

TSC registers are initialized or acquisition is completed with success

HAL_TSC_STATE_BUSY

TSC initialization or acquisition is on-going

HAL_TSC_STATE_ERROR

Acquisition is completed with max count error

Definition at line 63 of file stm32f3xx_hal_tsc.h.

enum TSC_GroupStatusTypeDef

TSC group status structure definition.

Enumerator:
TSC_GROUP_ONGOING

Acquisition on group is on-going or not started

TSC_GROUP_COMPLETED

Acquisition on group is completed with success (no max count error)

Definition at line 74 of file stm32f3xx_hal_tsc.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TSC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TSC_InitTypeDef Struct Reference
TSC Exported Types

TSC init structure definition. More...

#include <stm32f3xx_hal_tsc.h>

Data Fields

uint32_t | CTPulseHighLength
uint32_t | CTPulseLowLength
uint32_t | SpreadSpectrum
uint32_t | SpreadSpectrumDeviation
uint32_t | SpreadSpectrumPrescaler
uint32_t | PulseGeneratorPrescaler
uint32_t | MaxCountValue
uint32_t | IODefaultMode
uint32_t | SynchroPinPolarity
uint32_t | AcquisitionMode
uint32_t | MaxCountInterrupt
uint32_t | ChannelIOs
uint32_t | ShieldIOs
uint32_t | SamplingIOs

Detailed Description

TSC init structure definition.

Definition at line 83 of file stm32f3xx_hal_tsc.h.

Field Documentation

uint32_t TSC_InitTypeDef::AcquisitionMode

Acquisition mode This parameter can be a value of Acquisition Mode

Definition at line 103 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::ChannelIOs

Channel IOs mask

Definition at line 107 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::CTPulseHighLength

Charge-transfer high pulse length This parameter can be a value of CTPulse High Length

Definition at line 85 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::CTPulseLowLength

Charge-transfer low pulse length This parameter can be a value of CTPulse Low Length

Definition at line 87 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::IODefaultMode

IO default mode This parameter can be a value of IO Default Mode

Definition at line 99 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init(), HAL_TSC_Start(), and HAL_TSC_Start_IT().

uint32_t TSC_InitTypeDef::MaxCountInterrupt

Max count interrupt activation This parameter can be set to ENABLE or DISABLE.

Definition at line 105 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init(), and HAL_TSC_Start_IT().

uint32_t TSC_InitTypeDef::MaxCountValue

Max count value This parameter can be a value of Max Count Value

Definition at line 97 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::PulseGeneratorPrescaler

Pulse generator prescaler This parameter can be a value of Pulse Generator Prescaler

Definition at line 95 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::SamplingIOs

Sampling IOs mask

Definition at line 109 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::ShieldIOs

Shield IOs mask

Definition at line 108 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::SpreadSpectrum

Spread spectrum activation This parameter can be a value of CTPulse Low Length

Definition at line 89 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::SpreadSpectrumDeviation

Spread spectrum deviation This parameter must be a number between Min_Data = 0 and Max_Data = 127U

Definition at line 91 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::SpreadSpectrumPrescaler

Spread spectrum prescaler This parameter can be a value of Spread Spectrum Prescaler

Definition at line 93 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::SynchroPinPolarity

Synchro pin polarity This parameter can be a value of Synchro Pin Polarity

Definition at line 101 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_tsc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TSC_IOConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TSC_IOConfigTypeDef Struct Reference
TSC Exported Types

TSC IOs configuration structure definition. More...

#include <stm32f3xx_hal_tsc.h>

Data Fields

uint32_t | ChannelIOs
uint32_t | ShieldIOs
uint32_t | SamplingIOs

Detailed Description

TSC IOs configuration structure definition.

Definition at line 115 of file stm32f3xx_hal_tsc.h.

Field Documentation

uint32_t TSC_IOConfigTypeDef::ChannelIOs

Channel IOs mask

Definition at line 117 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_IOConfig().

uint32_t TSC_IOConfigTypeDef::SamplingIOs

Sampling IOs mask

Definition at line 119 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_IOConfig().

uint32_t TSC_IOConfigTypeDef::ShieldIOs

Shield IOs mask

Definition at line 118 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_IOConfig().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_tsc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TSC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TSC_HandleTypeDef Struct Reference
TSC Exported Types

TSC handle Structure definition. More...

#include <stm32f3xx_hal_tsc.h>

Data Fields

TSC_TypeDef * | Instance
TSC_InitTypeDef Init
__IO HAL_TSC_StateTypeDef | State
HAL_LockTypeDef | Lock

Detailed Description

TSC handle Structure definition.

Definition at line 125 of file stm32f3xx_hal_tsc.h.

Field Documentation

TSC_InitTypeDef TSC_HandleTypeDef::Init

Initialization parameters

Definition at line 128 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init(), HAL_TSC_Start(), and HAL_TSC_Start_IT().

TSC_TypeDef* TSC_HandleTypeDef::Instance

Register base address

Definition at line 127 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_DeInit(), HAL_TSC_GetState(), HAL_TSC_GroupGetStatus(), HAL_TSC_GroupGetValue(), HAL_TSC_Init(), HAL_TSC_IOConfig(), HAL_TSC_IODischarge(), HAL_TSC_IRQHandler(), HAL_TSC_PollForAcquisition(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

HAL_LockTypeDef TSC_HandleTypeDef::Lock

Lock feature

Definition at line 130 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

__IO HAL_TSC_StateTypeDef TSC_HandleTypeDef::State

Peripheral state

Definition at line 129 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_DeInit(), HAL_TSC_GetState(), HAL_TSC_Init(), HAL_TSC_IRQHandler(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_tsc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CTPulse High Length

Defines
CTPulse High Length
TSC Exported Constants

Defines

#define | TSC_CTPH_1CYCLE ((uint32_t)( 0U << 28U))
#define | TSC_CTPH_2CYCLES ((uint32_t)( 1U << 28U))
#define | TSC_CTPH_3CYCLES ((uint32_t)( 2U << 28U))
#define | TSC_CTPH_4CYCLES ((uint32_t)( 3U << 28U))
#define | TSC_CTPH_5CYCLES ((uint32_t)( 4U << 28U))
#define | TSC_CTPH_6CYCLES ((uint32_t)( 5U << 28U))
#define | TSC_CTPH_7CYCLES ((uint32_t)( 6U << 28U))
#define | TSC_CTPH_8CYCLES ((uint32_t)( 7U << 28U))
#define | TSC_CTPH_9CYCLES ((uint32_t)( 8U << 28U))
#define | TSC_CTPH_10CYCLES ((uint32_t)( 9U << 28U))
#define | TSC_CTPH_11CYCLES ((uint32_t)(10U << 28U))
#define | TSC_CTPH_12CYCLES ((uint32_t)(11U << 28U))
#define | TSC_CTPH_13CYCLES ((uint32_t)(12U << 28U))
#define | TSC_CTPH_14CYCLES ((uint32_t)(13U << 28U))
#define | TSC_CTPH_15CYCLES ((uint32_t)(14U << 28U))
#define | TSC_CTPH_16CYCLES ((uint32_t)(15U << 28U))

Define Documentation

#define TSC_CTPH_10CYCLES ((uint32_t)( 9U << 28U))

Definition at line 154 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPH_11CYCLES ((uint32_t)(10U << 28U))

Definition at line 155 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPH_12CYCLES ((uint32_t)(11U << 28U))

Definition at line 156 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPH_13CYCLES ((uint32_t)(12U << 28U))

Definition at line 157 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPH_14CYCLES ((uint32_t)(13U << 28U))

Definition at line 158 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPH_15CYCLES ((uint32_t)(14U << 28U))

Definition at line 159 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPH_16CYCLES ((uint32_t)(15U << 28U))

Definition at line 160 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPH_1CYCLE ((uint32_t)( 0U << 28U))

Definition at line 145 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPH_2CYCLES ((uint32_t)( 1U << 28U))

Definition at line 146 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPH_3CYCLES ((uint32_t)( 2U << 28U))

Definition at line 147 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPH_4CYCLES ((uint32_t)( 3U << 28U))

Definition at line 148 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPH_5CYCLES ((uint32_t)( 4U << 28U))

Definition at line 149 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPH_6CYCLES ((uint32_t)( 5U << 28U))

Definition at line 150 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPH_7CYCLES ((uint32_t)( 6U << 28U))

Definition at line 151 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPH_8CYCLES ((uint32_t)( 7U << 28U))

Definition at line 152 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPH_9CYCLES ((uint32_t)( 8U << 28U))

Definition at line 153 of file stm32f3xx_hal_tsc.h.

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STM32F373xC HAL User Manual: CTPulse Low Length

Defines
CTPulse Low Length
TSC Exported Constants

Defines

#define | TSC_CTPL_1CYCLE ((uint32_t)( 0U << 24U))
#define | TSC_CTPL_2CYCLES ((uint32_t)( 1U << 24U))
#define | TSC_CTPL_3CYCLES ((uint32_t)( 2U << 24U))
#define | TSC_CTPL_4CYCLES ((uint32_t)( 3U << 24U))
#define | TSC_CTPL_5CYCLES ((uint32_t)( 4U << 24U))
#define | TSC_CTPL_6CYCLES ((uint32_t)( 5U << 24U))
#define | TSC_CTPL_7CYCLES ((uint32_t)( 6U << 24U))
#define | TSC_CTPL_8CYCLES ((uint32_t)( 7U << 24U))
#define | TSC_CTPL_9CYCLES ((uint32_t)( 8U << 24U))
#define | TSC_CTPL_10CYCLES ((uint32_t)( 9U << 24U))
#define | TSC_CTPL_11CYCLES ((uint32_t)(10U << 24U))
#define | TSC_CTPL_12CYCLES ((uint32_t)(11U << 24U))
#define | TSC_CTPL_13CYCLES ((uint32_t)(12U << 24U))
#define | TSC_CTPL_14CYCLES ((uint32_t)(13U << 24U))
#define | TSC_CTPL_15CYCLES ((uint32_t)(14U << 24U))
#define | TSC_CTPL_16CYCLES ((uint32_t)(15U << 24U))

Define Documentation

#define TSC_CTPL_10CYCLES ((uint32_t)( 9U << 24U))

Definition at line 177 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPL_11CYCLES ((uint32_t)(10U << 24U))

Definition at line 178 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPL_12CYCLES ((uint32_t)(11U << 24U))

Definition at line 179 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPL_13CYCLES ((uint32_t)(12U << 24U))

Definition at line 180 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPL_14CYCLES ((uint32_t)(13U << 24U))

Definition at line 181 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPL_15CYCLES ((uint32_t)(14U << 24U))

Definition at line 182 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPL_16CYCLES ((uint32_t)(15U << 24U))

Definition at line 183 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPL_1CYCLE ((uint32_t)( 0U << 24U))

Definition at line 168 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPL_2CYCLES ((uint32_t)( 1U << 24U))

Definition at line 169 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPL_3CYCLES ((uint32_t)( 2U << 24U))

Definition at line 170 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPL_4CYCLES ((uint32_t)( 3U << 24U))

Definition at line 171 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPL_5CYCLES ((uint32_t)( 4U << 24U))

Definition at line 172 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPL_6CYCLES ((uint32_t)( 5U << 24U))

Definition at line 173 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPL_7CYCLES ((uint32_t)( 6U << 24U))

Definition at line 174 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPL_8CYCLES ((uint32_t)( 7U << 24U))

Definition at line 175 of file stm32f3xx_hal_tsc.h.

#define TSC_CTPL_9CYCLES ((uint32_t)( 8U << 24U))

Definition at line 176 of file stm32f3xx_hal_tsc.h.

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STM32F373xC HAL User Manual: Spread Spectrum Prescaler

Defines
Spread Spectrum Prescaler
TSC Exported Constants

Defines

#define | TSC_SS_PRESC_DIV1 (0U)
#define | TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC)

Define Documentation

#define TSC_SS_PRESC_DIV1 (0U)

Definition at line 191 of file stm32f3xx_hal_tsc.h.

#define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC)

Definition at line 192 of file stm32f3xx_hal_tsc.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Pulse Generator Prescaler

Defines
Pulse Generator Prescaler
TSC Exported Constants

Defines

#define | TSC_PG_PRESC_DIV1 ((uint32_t)(0U << 12U))
#define | TSC_PG_PRESC_DIV2 ((uint32_t)(1U << 12U))
#define | TSC_PG_PRESC_DIV4 ((uint32_t)(2U << 12U))
#define | TSC_PG_PRESC_DIV8 ((uint32_t)(3U << 12U))
#define | TSC_PG_PRESC_DIV16 ((uint32_t)(4U << 12U))
#define | TSC_PG_PRESC_DIV32 ((uint32_t)(5U << 12U))
#define | TSC_PG_PRESC_DIV64 ((uint32_t)(6U << 12U))
#define | TSC_PG_PRESC_DIV128 ((uint32_t)(7U << 12U))

Define Documentation

#define TSC_PG_PRESC_DIV1 ((uint32_t)(0U << 12U))

Definition at line 200 of file stm32f3xx_hal_tsc.h.

#define TSC_PG_PRESC_DIV128 ((uint32_t)(7U << 12U))

Definition at line 207 of file stm32f3xx_hal_tsc.h.

#define TSC_PG_PRESC_DIV16 ((uint32_t)(4U << 12U))

Definition at line 204 of file stm32f3xx_hal_tsc.h.

#define TSC_PG_PRESC_DIV2 ((uint32_t)(1U << 12U))

Definition at line 201 of file stm32f3xx_hal_tsc.h.

#define TSC_PG_PRESC_DIV32 ((uint32_t)(5U << 12U))

Definition at line 205 of file stm32f3xx_hal_tsc.h.

#define TSC_PG_PRESC_DIV4 ((uint32_t)(2U << 12U))

Definition at line 202 of file stm32f3xx_hal_tsc.h.

#define TSC_PG_PRESC_DIV64 ((uint32_t)(6U << 12U))

Definition at line 206 of file stm32f3xx_hal_tsc.h.

#define TSC_PG_PRESC_DIV8 ((uint32_t)(3U << 12U))

Definition at line 203 of file stm32f3xx_hal_tsc.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Max Count Value

Defines
Max Count Value
TSC Exported Constants

Defines

#define | TSC_MCV_255 ((uint32_t)(0U << 5U))
#define | TSC_MCV_511 ((uint32_t)(1U << 5U))
#define | TSC_MCV_1023 ((uint32_t)(2U << 5U))
#define | TSC_MCV_2047 ((uint32_t)(3U << 5U))
#define | TSC_MCV_4095 ((uint32_t)(4U << 5U))
#define | TSC_MCV_8191 ((uint32_t)(5U << 5U))
#define | TSC_MCV_16383 ((uint32_t)(6U << 5U))

Define Documentation

#define TSC_MCV_1023 ((uint32_t)(2U << 5U))

Definition at line 217 of file stm32f3xx_hal_tsc.h.

#define TSC_MCV_16383 ((uint32_t)(6U << 5U))

Definition at line 221 of file stm32f3xx_hal_tsc.h.

#define TSC_MCV_2047 ((uint32_t)(3U << 5U))

Definition at line 218 of file stm32f3xx_hal_tsc.h.

#define TSC_MCV_255 ((uint32_t)(0U << 5U))

Definition at line 215 of file stm32f3xx_hal_tsc.h.

#define TSC_MCV_4095 ((uint32_t)(4U << 5U))

Definition at line 219 of file stm32f3xx_hal_tsc.h.

#define TSC_MCV_511 ((uint32_t)(1U << 5U))

Definition at line 216 of file stm32f3xx_hal_tsc.h.

#define TSC_MCV_8191 ((uint32_t)(5U << 5U))

Definition at line 220 of file stm32f3xx_hal_tsc.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IO Default Mode

Defines
IO Default Mode
TSC Exported Constants

Defines

#define | TSC_IODEF_OUT_PP_LOW (0U)
#define | TSC_IODEF_IN_FLOAT (TSC_CR_IODEF)

Define Documentation

#define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF)

Definition at line 230 of file stm32f3xx_hal_tsc.h.

#define TSC_IODEF_OUT_PP_LOW (0U)

Definition at line 229 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Start(), and HAL_TSC_Start_IT().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Synchro Pin Polarity

Defines
Synchro Pin Polarity
TSC Exported Constants

Defines

#define | TSC_SYNC_POLARITY_FALLING (0U)
#define | TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)

Define Documentation

#define TSC_SYNC_POLARITY_FALLING (0U)

Definition at line 238 of file stm32f3xx_hal_tsc.h.

#define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)

Definition at line 239 of file stm32f3xx_hal_tsc.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Acquisition Mode

Defines
Acquisition Mode
TSC Exported Constants

Defines

#define | TSC_ACQ_MODE_NORMAL (0U)
#define | TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)

Define Documentation

#define TSC_ACQ_MODE_NORMAL (0U)

Definition at line 247 of file stm32f3xx_hal_tsc.h.

#define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)

Definition at line 248 of file stm32f3xx_hal_tsc.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IO Mode

Defines
IO Mode
TSC Exported Constants

Defines

#define | TSC_IOMODE_UNUSED (0U)
#define | TSC_IOMODE_CHANNEL (1U)
#define | TSC_IOMODE_SHIELD (2U)
#define | TSC_IOMODE_SAMPLING (3U)

Define Documentation

#define TSC_IOMODE_CHANNEL (1U)

Definition at line 257 of file stm32f3xx_hal_tsc.h.

#define TSC_IOMODE_SAMPLING (3U)

Definition at line 259 of file stm32f3xx_hal_tsc.h.

#define TSC_IOMODE_SHIELD (2U)

Definition at line 258 of file stm32f3xx_hal_tsc.h.

#define TSC_IOMODE_UNUSED (0U)

Definition at line 256 of file stm32f3xx_hal_tsc.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Interrupts definition

Defines
Interrupts definition
TSC Exported Constants

Defines

#define | TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
#define | TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)

Define Documentation

#define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)

Definition at line 267 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init(), HAL_TSC_Start(), HAL_TSC_Start_IT(), and HAL_TSC_Stop_IT().

#define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)

Definition at line 268 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init(), HAL_TSC_Start(), HAL_TSC_Start_IT(), and HAL_TSC_Stop_IT().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Flags definition

Defines
Flags definition
TSC Exported Constants

Defines

#define | TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
#define | TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)

Define Documentation

#define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)

Definition at line 276 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_GetState(), HAL_TSC_Init(), HAL_TSC_IRQHandler(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

#define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)

Definition at line 277 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_GetState(), HAL_TSC_Init(), HAL_TSC_IRQHandler(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Group definition

Defines
Group definition
TSC Exported Constants

Defines

#define | TSC_NB_OF_GROUPS (8U)
#define | TSC_GROUP1 (0x00000001U)
#define | TSC_GROUP2 (0x00000002U)
#define | TSC_GROUP3 (0x00000004U)
#define | TSC_GROUP4 (0x00000008U)
#define | TSC_GROUP5 (0x00000010U)
#define | TSC_GROUP6 (0x00000020U)
#define | TSC_GROUP7 (0x00000040U)
#define | TSC_GROUP8 (0x00000080U)
#define | TSC_ALL_GROUPS (0x000000FFU)
#define | TSC_GROUP1_IDX (0U)
#define | TSC_GROUP2_IDX (1U)
#define | TSC_GROUP3_IDX (2U)
#define | TSC_GROUP4_IDX (3U)
#define | TSC_GROUP5_IDX (4U)
#define | TSC_GROUP6_IDX (5U)
#define | TSC_GROUP7_IDX (6U)
#define | TSC_GROUP8_IDX (7U)
#define | TSC_GROUP1_IO1 (0x00000001U)
#define | TSC_GROUP1_IO2 (0x00000002U)
#define | TSC_GROUP1_IO3 (0x00000004U)
#define | TSC_GROUP1_IO4 (0x00000008U)
#define | TSC_GROUP1_ALL_IOS (0x0000000FU)
#define | TSC_GROUP2_IO1 (0x00000010U)
#define | TSC_GROUP2_IO2 (0x00000020U)
#define | TSC_GROUP2_IO3 (0x00000040U)
#define | TSC_GROUP2_IO4 (0x00000080U)
#define | TSC_GROUP2_ALL_IOS (0x000000F0U)
#define | TSC_GROUP3_IO1 (0x00000100U)
#define | TSC_GROUP3_IO2 (0x00000200U)
#define | TSC_GROUP3_IO3 (0x00000400U)
#define | TSC_GROUP3_IO4 (0x00000800U)
#define | TSC_GROUP3_ALL_IOS (0x00000F00U)
#define | TSC_GROUP4_IO1 (0x00001000U)
#define | TSC_GROUP4_IO2 (0x00002000U)
#define | TSC_GROUP4_IO3 (0x00004000U)
#define | TSC_GROUP4_IO4 (0x00008000U)
#define | TSC_GROUP4_ALL_IOS (0x0000F000U)
#define | TSC_GROUP5_IO1 (0x00010000U)
#define | TSC_GROUP5_IO2 (0x00020000U)
#define | TSC_GROUP5_IO3 (0x00040000U)
#define | TSC_GROUP5_IO4 (0x00080000U)
#define | TSC_GROUP5_ALL_IOS (0x000F0000U)
#define | TSC_GROUP6_IO1 (0x00100000U)
#define | TSC_GROUP6_IO2 (0x00200000U)
#define | TSC_GROUP6_IO3 (0x00400000U)
#define | TSC_GROUP6_IO4 (0x00800000U)
#define | TSC_GROUP6_ALL_IOS (0x00F00000U)
#define | TSC_GROUP7_IO1 (0x01000000U)
#define | TSC_GROUP7_IO2 (0x02000000U)
#define | TSC_GROUP7_IO3 (0x04000000U)
#define | TSC_GROUP7_IO4 (0x08000000U)
#define | TSC_GROUP7_ALL_IOS (0x0F000000U)
#define | TSC_GROUP8_IO1 (0x10000000U)
#define | TSC_GROUP8_IO2 (0x20000000U)
#define | TSC_GROUP8_IO3 (0x40000000U)
#define | TSC_GROUP8_IO4 (0x80000000U)
#define | TSC_GROUP8_ALL_IOS (0xF0000000U)
#define | TSC_ALL_GROUPS_ALL_IOS (0xFFFFFFFFU)

Define Documentation

#define TSC_ALL_GROUPS (0x000000FFU)

Definition at line 295 of file stm32f3xx_hal_tsc.h.

#define TSC_ALL_GROUPS_ALL_IOS (0xFFFFFFFFU)

Definition at line 354 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP1 (0x00000001U)

Definition at line 287 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP1_ALL_IOS (0x0000000FU)

Definition at line 310 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP1_IDX (0U)

Definition at line 297 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP1_IO1 (0x00000001U)

Definition at line 306 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP1_IO2 (0x00000002U)

Definition at line 307 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP1_IO3 (0x00000004U)

Definition at line 308 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP1_IO4 (0x00000008U)

Definition at line 309 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP2 (0x00000002U)

Definition at line 288 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP2_ALL_IOS (0x000000F0U)

Definition at line 316 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP2_IDX (1U)

Definition at line 298 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP2_IO1 (0x00000010U)

Definition at line 312 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP2_IO2 (0x00000020U)

Definition at line 313 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP2_IO3 (0x00000040U)

Definition at line 314 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP2_IO4 (0x00000080U)

Definition at line 315 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP3 (0x00000004U)

Definition at line 289 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP3_ALL_IOS (0x00000F00U)

Definition at line 322 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP3_IDX (2U)

Definition at line 299 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP3_IO1 (0x00000100U)

Definition at line 318 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP3_IO2 (0x00000200U)

Definition at line 319 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP3_IO3 (0x00000400U)

Definition at line 320 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP3_IO4 (0x00000800U)

Definition at line 321 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP4 (0x00000008U)

Definition at line 290 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP4_ALL_IOS (0x0000F000U)

Definition at line 328 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP4_IDX (3U)

Definition at line 300 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP4_IO1 (0x00001000U)

Definition at line 324 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP4_IO2 (0x00002000U)

Definition at line 325 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP4_IO3 (0x00004000U)

Definition at line 326 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP4_IO4 (0x00008000U)

Definition at line 327 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP5 (0x00000010U)

Definition at line 291 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP5_ALL_IOS (0x000F0000U)

Definition at line 334 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP5_IDX (4U)

Definition at line 301 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP5_IO1 (0x00010000U)

Definition at line 330 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP5_IO2 (0x00020000U)

Definition at line 331 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP5_IO3 (0x00040000U)

Definition at line 332 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP5_IO4 (0x00080000U)

Definition at line 333 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP6 (0x00000020U)

Definition at line 292 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP6_ALL_IOS (0x00F00000U)

Definition at line 340 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP6_IDX (5U)

Definition at line 302 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP6_IO1 (0x00100000U)

Definition at line 336 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP6_IO2 (0x00200000U)

Definition at line 337 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP6_IO3 (0x00400000U)

Definition at line 338 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP6_IO4 (0x00800000U)

Definition at line 339 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP7 (0x00000040U)

Definition at line 293 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP7_ALL_IOS (0x0F000000U)

Definition at line 346 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP7_IDX (6U)

Definition at line 303 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP7_IO1 (0x01000000U)

Definition at line 342 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP7_IO2 (0x02000000U)

Definition at line 343 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP7_IO3 (0x04000000U)

Definition at line 344 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP7_IO4 (0x08000000U)

Definition at line 345 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP8 (0x00000080U)

Definition at line 294 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP8_ALL_IOS (0xF0000000U)

Definition at line 352 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP8_IDX (7U)

Definition at line 304 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP8_IO1 (0x10000000U)

Definition at line 348 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP8_IO2 (0x20000000U)

Definition at line 349 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP8_IO3 (0x40000000U)

Definition at line 350 of file stm32f3xx_hal_tsc.h.

#define TSC_GROUP8_IO4 (0x80000000U)

Definition at line 351 of file stm32f3xx_hal_tsc.h.

#define TSC_NB_OF_GROUPS (8U)

Definition at line 285 of file stm32f3xx_hal_tsc.h.

Referenced by TSC_extract_groups().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TSC Exported Macros

Defines
TSC Exported Macros
TSC

Defines

#define | __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
Reset TSC handle state.
#define | __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
Enable the TSC peripheral.
#define | __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
Disable the TSC peripheral.
#define | __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
Start acquisition.
#define | __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
Stop acquisition.
#define | __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
Set IO default mode to output push-pull low.
#define | __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
Set IO default mode to input floating.
#define | __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
Set synchronization polarity to falling edge.
#define | __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
Set synchronization polarity to rising edge and high level.
#define | __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable TSC interrupt.
#define | __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
Disable TSC interrupt.
#define | __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified TSC interrupt source is enabled or not.
#define | __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
Check whether the specified TSC flag is set or not.
#define | __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the TSC's pending flag.
#define | __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
Enable schmitt trigger hysteresis on a group of IOs.
#define | __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
Disable schmitt trigger hysteresis on a group of IOs.
#define | __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
Open analog switch on a group of IOs.
#define | __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
Close analog switch on a group of IOs.
#define | __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
Enable a group of IOs in channel mode.
#define | __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
Disable a group of channel IOs.
#define | __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
Enable a group of IOs in sampling mode.
#define | __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
Disable a group of sampling IOs.
#define | __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
Enable acquisition groups.
#define | __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
Disable acquisition groups.
#define | __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) == (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
Gets acquisition group status.

Define Documentation

#define __HAL_TSC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the TSC's pending flag.

Parameters:
__HANDLE__ | TSC handle
__FLAG__ | TSC flag
Return values:
None

Definition at line 468 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_IRQHandler(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

#define __HAL_TSC_CLOSE_ANALOG_SWITCH | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))

Close analog switch on a group of IOs.

Parameters:
__HANDLE__ | TSC handle
__GX_IOY_MASK__ | IOs mask
Return values:
None

Definition at line 500 of file stm32f3xx_hal_tsc.h.

#define __HAL_TSC_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))

Disable the TSC peripheral.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 387 of file stm32f3xx_hal_tsc.h.

#define __HAL_TSC_DISABLE_CHANNEL | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))

Disable a group of channel IOs.

Parameters:
__HANDLE__ | TSC handle
__GX_IOY_MASK__ | IOs mask
Return values:
None

Definition at line 516 of file stm32f3xx_hal_tsc.h.

#define __HAL_TSC_DISABLE_GROUP | ( | __HANDLE__,
 |  | __GX_MASK__
 | ) | ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))

Disable acquisition groups.

Parameters:
__HANDLE__ | TSC handle
__GX_MASK__ | Groups mask
Return values:
None

Definition at line 548 of file stm32f3xx_hal_tsc.h.

#define __HAL_TSC_DISABLE_HYSTERESIS | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))

Disable schmitt trigger hysteresis on a group of IOs.

Parameters:
__HANDLE__ | TSC handle
__GX_IOY_MASK__ | IOs mask
Return values:
None

Definition at line 484 of file stm32f3xx_hal_tsc.h.

#define __HAL_TSC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))

Disable TSC interrupt.

Parameters:
__HANDLE__ | TSC handle
__INTERRUPT__ | TSC interrupt
Return values:
None

Definition at line 445 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Start(), HAL_TSC_Start_IT(), and HAL_TSC_Stop_IT().

#define __HAL_TSC_DISABLE_SAMPLING | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))

Disable a group of sampling IOs.

Parameters:
__HANDLE__ | TSC handle
__GX_IOY_MASK__ | IOs mask
Return values:
None

Definition at line 532 of file stm32f3xx_hal_tsc.h.

#define __HAL_TSC_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)

Enable the TSC peripheral.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 380 of file stm32f3xx_hal_tsc.h.

#define __HAL_TSC_ENABLE_CHANNEL | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))

Enable a group of IOs in channel mode.

Parameters:
__HANDLE__ | TSC handle
__GX_IOY_MASK__ | IOs mask
Return values:
None

Definition at line 508 of file stm32f3xx_hal_tsc.h.

#define __HAL_TSC_ENABLE_GROUP | ( | __HANDLE__,
 |  | __GX_MASK__
 | ) | ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))

Enable acquisition groups.

Parameters:
__HANDLE__ | TSC handle
__GX_MASK__ | Groups mask
Return values:
None

Definition at line 540 of file stm32f3xx_hal_tsc.h.

#define __HAL_TSC_ENABLE_HYSTERESIS | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))

Enable schmitt trigger hysteresis on a group of IOs.

Parameters:
__HANDLE__ | TSC handle
__GX_IOY_MASK__ | IOs mask
Return values:
None

Definition at line 476 of file stm32f3xx_hal_tsc.h.

#define __HAL_TSC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable TSC interrupt.

Parameters:
__HANDLE__ | TSC handle
__INTERRUPT__ | TSC interrupt
Return values:
None

Definition at line 437 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Start_IT().

#define __HAL_TSC_ENABLE_SAMPLING | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))

Enable a group of IOs in sampling mode.

Parameters:
__HANDLE__ | TSC handle
__GX_IOY_MASK__ | IOs mask
Return values:
None

Definition at line 524 of file stm32f3xx_hal_tsc.h.

#define __HAL_TSC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Check whether the specified TSC flag is set or not.

Parameters:
__HANDLE__ | TSC handle
__FLAG__ | TSC flag
Return values:
SET or RESET

Definition at line 460 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_GetState(), and HAL_TSC_IRQHandler().

#define __HAL_TSC_GET_GROUP_STATUS | ( | __HANDLE__,
 |  | __GX_INDEX__
 | ) | ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) == (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)

Gets acquisition group status.

Parameters:
__HANDLE__ | TSC Handle
__GX_INDEX__ | Group index
Return values:
SET or RESET

Definition at line 555 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_GroupGetStatus().

#define __HAL_TSC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified TSC interrupt source is enabled or not.

Parameters:
__HANDLE__ | TSC Handle
__INTERRUPT__ | TSC interrupt
Return values:
SET or RESET

Definition at line 452 of file stm32f3xx_hal_tsc.h.

#define __HAL_TSC_OPEN_ANALOG_SWITCH | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))

Open analog switch on a group of IOs.

Parameters:
__HANDLE__ | TSC handle
__GX_IOY_MASK__ | IOs mask
Return values:
None

Definition at line 492 of file stm32f3xx_hal_tsc.h.

#define __HAL_TSC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)

Reset TSC handle state.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 373 of file stm32f3xx_hal_tsc.h.

#define __HAL_TSC_SET_IODEF_INFLOAT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)

Set IO default mode to input floating.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 415 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_IODischarge(), HAL_TSC_Start(), and HAL_TSC_Start_IT().

#define __HAL_TSC_SET_IODEF_OUTPPLOW ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))

Set IO default mode to output push-pull low.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 408 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_IODischarge(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

#define __HAL_TSC_SET_SYNC_POL_FALL ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))

Set synchronization polarity to falling edge.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 422 of file stm32f3xx_hal_tsc.h.

#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)

Set synchronization polarity to rising edge and high level.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 429 of file stm32f3xx_hal_tsc.h.

#define __HAL_TSC_START_ACQ ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= TSC_CR_START)

Start acquisition.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 394 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Start(), and HAL_TSC_Start_IT().

#define __HAL_TSC_STOP_ACQ ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))

Stop acquisition.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 401 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_IOConfig(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TSC Private Macros

Defines
TSC Private Macros
TSC

Defines

#define | IS_TSC_CTPH(VAL)
#define | IS_TSC_CTPL(VAL)
#define | IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
#define | IS_TSC_SSD(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < 128U)))
#define | IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
#define | IS_TSC_PG_PRESC(VAL)
#define | IS_TSC_MCV(VAL)
#define | IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
#define | IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
#define | IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
#define | IS_TSC_IOMODE(VAL)
#define | IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
#define | IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < TSC_NB_OF_GROUPS)))

Define Documentation

#define IS_TSC_ACQ_MODE ( VAL ) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))

Definition at line 629 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_CTPH ( VAL )
Value:
(((VAL) == TSC_CTPH_1CYCLE) || \
                          ((VAL) == TSC_CTPH_2CYCLES) || \
                          ((VAL) == TSC_CTPH_3CYCLES) || \
                          ((VAL) == TSC_CTPH_4CYCLES) || \
                          ((VAL) == TSC_CTPH_5CYCLES) || \
                          ((VAL) == TSC_CTPH_6CYCLES) || \
                          ((VAL) == TSC_CTPH_7CYCLES) || \
                          ((VAL) == TSC_CTPH_8CYCLES) || \
                          ((VAL) == TSC_CTPH_9CYCLES) || \
                          ((VAL) == TSC_CTPH_10CYCLES) || \
                          ((VAL) == TSC_CTPH_11CYCLES) || \
                          ((VAL) == TSC_CTPH_12CYCLES) || \
                          ((VAL) == TSC_CTPH_13CYCLES) || \
                          ((VAL) == TSC_CTPH_14CYCLES) || \
                          ((VAL) == TSC_CTPH_15CYCLES) || \
                          ((VAL) == TSC_CTPH_16CYCLES))

Definition at line 568 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_CTPL ( VAL )
Value:
(((VAL) == TSC_CTPL_1CYCLE) || \
                          ((VAL) == TSC_CTPL_2CYCLES) || \
                          ((VAL) == TSC_CTPL_3CYCLES) || \
                          ((VAL) == TSC_CTPL_4CYCLES) || \
                          ((VAL) == TSC_CTPL_5CYCLES) || \
                          ((VAL) == TSC_CTPL_6CYCLES) || \
                          ((VAL) == TSC_CTPL_7CYCLES) || \
                          ((VAL) == TSC_CTPL_8CYCLES) || \
                          ((VAL) == TSC_CTPL_9CYCLES) || \
                          ((VAL) == TSC_CTPL_10CYCLES) || \
                          ((VAL) == TSC_CTPL_11CYCLES) || \
                          ((VAL) == TSC_CTPL_12CYCLES) || \
                          ((VAL) == TSC_CTPL_13CYCLES) || \
                          ((VAL) == TSC_CTPL_14CYCLES) || \
                          ((VAL) == TSC_CTPL_15CYCLES) || \
                          ((VAL) == TSC_CTPL_16CYCLES))

Definition at line 585 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_GROUP_INDEX ( VAL ) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < TSC_NB_OF_GROUPS)))

Definition at line 638 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_GroupGetStatus(), and HAL_TSC_GroupGetValue().

#define IS_TSC_IODEF ( VAL ) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))

Definition at line 625 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_IOMODE ( VAL )
Value:
(((VAL) == TSC_IOMODE_UNUSED) || \
                            ((VAL) == TSC_IOMODE_CHANNEL) || \
                            ((VAL) == TSC_IOMODE_SHIELD) || \
                            ((VAL) == TSC_IOMODE_SAMPLING))

Definition at line 631 of file stm32f3xx_hal_tsc.h.

#define IS_TSC_MCE_IT ( VAL ) (((VAL) == DISABLE) || ((VAL) == ENABLE))

Definition at line 636 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init(), and HAL_TSC_Start_IT().

#define IS_TSC_MCV ( VAL )
Value:
(((VAL) == TSC_MCV_255) || \
                         ((VAL) == TSC_MCV_511) || \
                         ((VAL) == TSC_MCV_1023) || \
                         ((VAL) == TSC_MCV_2047) || \
                         ((VAL) == TSC_MCV_4095) || \
                         ((VAL) == TSC_MCV_8191) || \
                         ((VAL) == TSC_MCV_16383))

Definition at line 617 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_PG_PRESC ( VAL )
Value:
(((VAL) == TSC_PG_PRESC_DIV1) || \
                              ((VAL) == TSC_PG_PRESC_DIV2) || \
                              ((VAL) == TSC_PG_PRESC_DIV4) || \
                              ((VAL) == TSC_PG_PRESC_DIV8) || \
                              ((VAL) == TSC_PG_PRESC_DIV16) || \
                              ((VAL) == TSC_PG_PRESC_DIV32) || \
                              ((VAL) == TSC_PG_PRESC_DIV64) || \
                              ((VAL) == TSC_PG_PRESC_DIV128))

Definition at line 608 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_SS ( VAL ) (((VAL) == DISABLE) || ((VAL) == ENABLE))

Definition at line 602 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_SS_PRESC ( VAL ) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))

Definition at line 606 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_SSD ( VAL ) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < 128U)))

Definition at line 604 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_SYNC_POL ( VAL ) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))

Definition at line 627 of file stm32f3xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Private Constants

Defines
UART Private Constants
UART

Defines

#define UART_CR1_FIELDS

Define Documentation

#define UART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
                                     USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))

UART or USART CR1 fields of parameters set by UART_SetConfig API

Definition at line 178 of file stm32f3xx_hal_uart.c.

Referenced by UART_SetConfig().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in asynchronous mode.
      (+) For the asynchronous mode the parameters below can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity
        (++) Hardware flow control
        (++) Receiver/transmitter modes
        (++) Over Sampling Method
        (++) One-Bit Sampling Method
      (+) For the asynchronous mode, the following advanced features can be configured as well:
        (++) TX and/or RX pin level inversion
        (++) data logical level inversion
        (++) RX and TX pins swap
        (++) RX overrun detection disabling
        (++) DMA disabling on RX error
        (++) MSB first on communication line
        (++) auto Baud rate detection
    [..]
    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init()
    API follow respectively the UART asynchronous, UART Half duplex, UART LIN mode and
    multiprocessor configuration procedures (details for the procedures are available in reference manual).

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_Init ( UART_HandleTypeDef * huart )

Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 357 of file stm32f3xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Instance, UART_HandleTypeDef::Lock, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), and UART_SetConfig().

HAL_StatusTypeDef HAL_LIN_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | BreakDetectLength
 | ) |  |

Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .

Parameters:
huart UART handle.
BreakDetectLength specifies the LIN break detection length. This parameter can be one of the following values:
  • UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
  • UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
Return values:
HAL status

Definition at line 420 of file stm32f3xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_UART_LIN_BREAK_DETECT_LENGTH, UART_HandleTypeDef::Lock, UART_InitTypeDef::OverSampling, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_OVERSAMPLING_8, UART_SetConfig(), UART_WORDLENGTH_8B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_MultiProcessor_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t | Address,
 |  | uint32_t | WakeUpMethod
 | ) |  |

Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.

Parameters:
huart | UART handle.
Address | UART node address (4-, 6-, 7- or 8-bit long).
WakeUpMethod specifies the UART wakeup method. This parameter can be one of the following values:
  • UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
  • UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
Note:
If the user resorts to idle line detection wake up, the Address parameter is useless and ignored by the initialization function.
If the user resorts to address mark wake up, the address length detection is configured by default to 4 bits only. For the UART to be able to manage 6-, 7- or 8-bit long addresses detection, the API HAL_MultiProcessorEx_AddressLength_Set() must be called after HAL_MultiProcessor_Init().
Return values:
HAL status

Definition at line 507 of file stm32f3xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Instance, IS_UART_WAKEUPMETHOD, UART_HandleTypeDef::Lock, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_CR2_ADDRESS_LSB_POS, UART_SetConfig(), and UART_WAKEUPMETHOD_ADDRESSMARK.

HAL_StatusTypeDef HAL_UART_DeInit ( UART_HandleTypeDef * huart )

DeInitialize the UART peripheral.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 571 of file stm32f3xx_hal_uart.c.

References __HAL_UART_DISABLE, assert_param, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_MspDeInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_Init ( UART_HandleTypeDef * huart )

Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 294 of file stm32f3xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_InitTypeDef::HwFlowCtl, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_HandleTypeDef::Lock, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_HWCONTROL_NONE, and UART_SetConfig().

void HAL_UART_MspDeInit ( UART_HandleTypeDef * huart )

DeInitialize the UART MSP.

Parameters:
huart UART handle.
Return values:
None

Definition at line 624 of file stm32f3xx_hal_uart.c.

Referenced by HAL_UART_DeInit().

void HAL_UART_MspInit ( UART_HandleTypeDef * huart )

Initialize the UART MSP.

Parameters:
huart UART handle.
Return values:
None

Definition at line 609 of file stm32f3xx_hal_uart.c.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IO operation functions

Functions
IO operation functions
UART Exported Functions

UART Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.

Detailed Description

UART Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the UART asynchronous
    and Half duplex data transfers.

    (#) There are two mode of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
           The HAL status of all data processing is returned by the same function
           after finishing transfer.
       (++) Non-Blocking mode: The communication is performed using Interrupts
           or DMA, These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (++) HAL_UART_Transmit()
        (++) HAL_UART_Receive()

    (#) Non-Blocking mode API's with Interrupt are :
        (++) HAL_UART_Transmit_IT()
        (++) HAL_UART_Receive_IT()
        (++) HAL_UART_IRQHandler()

    (#) Non-Blocking mode API's with DMA are :
        (++) HAL_UART_Transmit_DMA()
        (++) HAL_UART_Receive_DMA()
        (++) HAL_UART_DMAPause()
        (++) HAL_UART_DMAResume()
        (++) HAL_UART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
        (++) HAL_UART_TxHalfCpltCallback()
        (++) HAL_UART_TxCpltCallback()
        (++) HAL_UART_RxHalfCpltCallback()
        (++) HAL_UART_RxCpltCallback()
        (++) HAL_UART_ErrorCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (++) HAL_UART_Abort()
        (++) HAL_UART_AbortTransmit()
        (++) HAL_UART_AbortReceive()
        (++) HAL_UART_Abort_IT()
        (++) HAL_UART_AbortTransmit_IT()
        (++) HAL_UART_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
        (++) HAL_UART_AbortCpltCallback()
        (++) HAL_UART_AbortTransmitCpltCallback()
        (++) HAL_UART_AbortReceiveCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
             to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
             and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
             If user wants to abort it, Abort services should be called by user.
        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
             This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
             Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.

    -@- In the Half duplex communication, it is forbidden to run the transmit
        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.

Function Documentation

HAL_StatusTypeDef HAL_UART_Abort ( UART_HandleTypeDef * huart )

Abort ongoing transfers (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1206 of file stm32f3xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_Abort_IT ( UART_HandleTypeDef * huart )

Abort ongoing transfers (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1363 of file stm32f3xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 1843 of file stm32f3xx_hal_uart.c.

Referenced by HAL_UART_Abort_IT(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

HAL_StatusTypeDef HAL_UART_AbortReceive ( UART_HandleTypeDef * huart )

Abort ongoing Receive transfer (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1315 of file stm32f3xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, HAL_DMA_Abort(), HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_AbortReceive_IT ( UART_HandleTypeDef * huart )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1553 of file stm32f3xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, HAL_DMA_Abort_IT(), HAL_UART_AbortReceiveCpltCallback(), HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_DMARxOnlyAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortReceiveCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Receive Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 1873 of file stm32f3xx_hal_uart.c.

Referenced by HAL_UART_AbortReceive_IT(), and UART_DMARxOnlyAbortCallback().

HAL_StatusTypeDef HAL_UART_AbortTransmit ( UART_HandleTypeDef * huart )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1273 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_UART_STATE_READY, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_AbortTransmit_IT ( UART_HandleTypeDef * huart )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1488 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_UART_AbortTransmitCpltCallback(), HAL_UART_STATE_READY, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::TxXferCount, UART_DMATxOnlyAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortTransmitCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 1858 of file stm32f3xx_hal_uart.c.

Referenced by HAL_UART_AbortTransmit_IT(), and UART_DMATxOnlyAbortCallback().

HAL_StatusTypeDef HAL_UART_DMAPause ( UART_HandleTypeDef * huart )

Pause the DMA Transfer.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1085 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_DMAResume ( UART_HandleTypeDef * huart )

Resume the DMA Transfer.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1118 of file stm32f3xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, and UART_CLEAR_OREF.

HAL_StatusTypeDef HAL_UART_DMAStop ( UART_HandleTypeDef * huart )

Stop the DMA Transfer.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1152 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_EndRxTransfer(), and UART_EndTxTransfer().

void HAL_UART_ErrorCallback ( UART_HandleTypeDef * huart )

UART error callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 1828 of file stm32f3xx_hal_uart.c.

Referenced by HAL_UART_IRQHandler(), UART_DMAAbortOnError(), and UART_DMAError().

void HAL_UART_IRQHandler ( UART_HandleTypeDef * huart )

Handle UART interrupt request.

Parameters:
huart UART handle.
Return values:
None

Definition at line 1616 of file stm32f3xx_hal_uart.c.

References __HAL_UART_CLEAR_IT, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_UART_ERROR_FE, HAL_UART_ERROR_NE, HAL_UART_ERROR_NONE, HAL_UART_ERROR_ORE, HAL_UART_ERROR_PE, HAL_UART_ErrorCallback(), HAL_UART_STATE_READY, HAL_UARTEx_WakeupCallback(), UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_CLEAR_WUF, UART_DMAAbortOnError(), UART_EndRxTransfer(), UART_EndTransmit_IT(), UART_Receive_IT(), UART_Transmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_Receive | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
huart | UART handle.
pData | pointer to data buffer.
Size | amount of data to be received.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 792 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_HandleTypeDef::Mask, UART_InitTypeDef::Parity, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::RxXferSize, UART_FLAG_RXNE, UART_MASK_COMPUTATION, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Receive_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
huart | UART handle.
pData | pointer to data buffer.
Size | amount of data to be received.
Note:
When the UART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
This function starts a DMA transfer in interrupt mode meaning that DMA half transfer complete, DMA transfer complete and DMA transfer error interrupts are enabled
Return values:
HAL status

Definition at line 1022 of file stm32f3xx_hal_uart.c.

References assert_param, UART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferSize, UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Receive_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Parameters:
huart | UART handle.
pData | pointer to data buffer.
Size | amount of data to be received.
Return values:
HAL status

Definition at line 904 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::RxXferSize, and UART_MASK_COMPUTATION.

void HAL_UART_RxCpltCallback ( UART_HandleTypeDef * huart )

Rx Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 1798 of file stm32f3xx_hal_uart.c.

Referenced by UART_DMAReceiveCplt(), and UART_Receive_IT().

void HAL_UART_RxHalfCpltCallback ( UART_HandleTypeDef * huart )

Rx Half Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 1813 of file stm32f3xx_hal_uart.c.

Referenced by UART_DMARxHalfCplt().

HAL_StatusTypeDef HAL_UART_Transmit | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Parameters:
huart | UART handle.
pData | Pointer to data buffer.
Size | Amount of data to be sent.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 723 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, UART_HandleTypeDef::TxXferCount, UART_HandleTypeDef::TxXferSize, UART_FLAG_TC, UART_FLAG_TXE, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Transmit_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
huart | UART handle.
pData | pointer to data buffer.
Size | amount of data to be sent.
Note:
This function starts a DMA transfer in interrupt mode meaning that DMA half transfer complete, DMA transfer complete and DMA transfer error interrupts are enabled
Return values:
HAL status

Definition at line 954 of file stm32f3xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, assert_param, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::TxXferCount, UART_HandleTypeDef::TxXferSize, UART_CLEAR_TCF, UART_DMAError(), UART_DMATransmitCplt(), UART_DMATxHalfCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Transmit_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Parameters:
huart | UART handle.
pData | pointer to data buffer.
Size | amount of data to be sent.
Return values:
HAL status

Definition at line 863 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::TxXferCount, and UART_HandleTypeDef::TxXferSize.

void HAL_UART_TxCpltCallback ( UART_HandleTypeDef * huart )

Tx Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 1768 of file stm32f3xx_hal_uart.c.

Referenced by UART_DMATransmitCplt(), and UART_EndTransmit_IT().

void HAL_UART_TxHalfCpltCallback ( UART_HandleTypeDef * huart )

Tx Half Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 1783 of file stm32f3xx_hal_uart.c.

Referenced by UART_DMATxHalfCplt().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
UART Exported Functions

UART control functions. More...

Functions

HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.

Detailed Description

UART control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the UART.
     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
     (+) HAL_LIN_SendBreak() API transmits the break characters

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver ( UART_HandleTypeDef * huart )

Enable the UART receiver and disable the UART transmitter.

Parameters:
huart UART handle.
Return values:
HAL status.

Definition at line 1988 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter ( UART_HandleTypeDef * huart )

Enable the UART transmitter and disable the UART receiver.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1964 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_LIN_SendBreak ( UART_HandleTypeDef * huart )

Transmit break characters.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2012 of file stm32f3xx_hal_uart.c.

References assert_param, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_SENDBREAK_REQUEST.

HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode ( UART_HandleTypeDef * huart )

Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1933 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_CheckIdleState().

HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode ( UART_HandleTypeDef * huart )

Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1912 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_CheckIdleState().

void HAL_MultiProcessor_EnterMuteMode ( UART_HandleTypeDef * huart )

Enter UART mute mode (means UART actually enters mute mode).

Note:
To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
Parameters:
huart UART handle.
Return values:
None

Definition at line 1954 of file stm32f3xx_hal_uart.c.

References __HAL_UART_SEND_REQ, and UART_MUTE_MODE_REQUEST.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
UART Exported Functions

UART Peripheral State functions. More...

Functions

HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART handle error code.

Detailed Description

UART Peripheral State functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Return the UART handle state.
      (+) Return the UART handle error code

Function Documentation

uint32_t HAL_UART_GetError ( UART_HandleTypeDef * huart )

Return the UART handle error code.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
UART Error Code

Definition at line 2075 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode.

HAL_UART_StateTypeDef HAL_UART_GetState ( UART_HandleTypeDef * huart )

Return the UART handle state.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
HAL state

Definition at line 2060 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::gState, and UART_HandleTypeDef::RxState.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Private Functions

Functions
UART Private Functions
UART

Functions

static void | UART_EndTxTransfer (UART_HandleTypeDef *huart)
End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
static void | UART_EndRxTransfer (UART_HandleTypeDef *huart)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static void | UART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | UART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | UART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | UART_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | UART_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
HAL_StatusTypeDef | UART_Transmit_IT (UART_HandleTypeDef *huart)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wrap up transmission in non-blocking mode.
HAL_StatusTypeDef | UART_Receive_IT (UART_HandleTypeDef *huart)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle UART Communication Timeout.
void | UART_Wakeup_AddressConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Initialize the UART wake-up from stop mode parameters when triggered by address detection.

Function Documentation

void UART_AdvFeatureConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral advanced features.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2207 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_AdvFeatureInitTypeDef::AutoBaudRateEnable, UART_AdvFeatureInitTypeDef::AutoBaudRateMode, UART_AdvFeatureInitTypeDef::DataInvert, UART_AdvFeatureInitTypeDef::DMADisableonRxError, UART_HandleTypeDef::Instance, IS_UART_ADVFEATURE_AUTOBAUDRATE, IS_UART_ADVFEATURE_AUTOBAUDRATEMODE, IS_UART_ADVFEATURE_DATAINV, IS_UART_ADVFEATURE_DMAONRXERROR, IS_UART_ADVFEATURE_INIT, IS_UART_ADVFEATURE_MSBFIRST, IS_UART_ADVFEATURE_RXINV, IS_UART_ADVFEATURE_SWAP, IS_UART_ADVFEATURE_TXINV, IS_UART_OVERRUN, UART_AdvFeatureInitTypeDef::MSBFirst, UART_AdvFeatureInitTypeDef::OverrunDisable, UART_AdvFeatureInitTypeDef::RxPinLevelInvert, UART_AdvFeatureInitTypeDef::Swap, UART_AdvFeatureInitTypeDef::TxPinLevelInvert, UART_ADVFEATURE_AUTOBAUDRATE_ENABLE, UART_ADVFEATURE_AUTOBAUDRATE_INIT, UART_ADVFEATURE_DATAINVERT_INIT, UART_ADVFEATURE_DMADISABLEONERROR_INIT, UART_ADVFEATURE_MSBFIRST_INIT, UART_ADVFEATURE_RXINVERT_INIT, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT, UART_ADVFEATURE_SWAP_INIT, and UART_ADVFEATURE_TXINVERT_INIT.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

HAL_StatusTypeDef UART_CheckIdleState ( UART_HandleTypeDef * huart )

Check the UART Idle State.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2281 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, HAL_UART_TIMEOUT_VALUE, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, and UART_WaitOnFlagUntilTimeout().

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), and HAL_UART_Init().

static void UART_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2506 of file stm32f3xx_hal_uart.c.

References HAL_UART_ErrorCallback(), __DMA_HandleTypeDef::Parent, UART_HandleTypeDef::RxXferCount, and UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_IRQHandler().

static void UART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication error callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2476 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_DMA, HAL_UART_ErrorCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::TxXferCount, UART_EndRxTransfer(), and UART_EndTxTransfer().

Referenced by HAL_UART_Receive_DMA(), and HAL_UART_Transmit_DMA().

static void UART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2435 of file stm32f3xx_hal_uart.c.

References HAL_UART_RxCpltCallback(), HAL_UART_STATE_READY, __DMA_HandleTypeDef::Instance, UART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, UART_HandleTypeDef::RxState, and UART_HandleTypeDef::RxXferCount.

Referenced by HAL_UART_Receive_DMA().

static void UART_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2565 of file stm32f3xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_UART_Abort_IT().

static void UART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2464 of file stm32f3xx_hal_uart.c.

References HAL_UART_RxHalfCpltCallback(), and __DMA_HandleTypeDef::Parent.

Referenced by HAL_UART_Receive_DMA().

static void UART_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2628 of file stm32f3xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, HAL_UART_AbortReceiveCpltCallback(), HAL_UART_STATE_READY, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, and UART_CLEAR_PEF.

Referenced by HAL_UART_AbortReceive_IT().

static void UART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2394 of file stm32f3xx_hal_uart.c.

References HAL_UART_TxCpltCallback(), __DMA_HandleTypeDef::Instance, UART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, and UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_DMA().

static void UART_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2523 of file stm32f3xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_UART_Abort_IT().

static void UART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2423 of file stm32f3xx_hal_uart.c.

References HAL_UART_TxHalfCpltCallback(), and __DMA_HandleTypeDef::Parent.

Referenced by HAL_UART_Transmit_DMA().

static void UART_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2607 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_AbortTransmitCpltCallback(), HAL_UART_STATE_READY, __DMA_HandleTypeDef::Parent, and UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_AbortTransmit_IT().

static void UART_EndRxTransfer ( UART_HandleTypeDef * huart ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
huart UART handle.
Return values:
None

Definition at line 2378 of file stm32f3xx_hal_uart.c.

References HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

Referenced by HAL_UART_DMAStop(), HAL_UART_IRQHandler(), and UART_DMAError().

HAL_StatusTypeDef UART_EndTransmit_IT ( UART_HandleTypeDef * huart )

Wrap up transmission in non-blocking mode.

Parameters:
huart pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 2697 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_READY, HAL_UART_TxCpltCallback(), and UART_HandleTypeDef::Instance.

Referenced by HAL_UART_IRQHandler().

static void UART_EndTxTransfer ( UART_HandleTypeDef * huart ) [static]

End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).

Parameters:
huart UART handle.
Return values:
None

Definition at line 2363 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

Referenced by HAL_UART_DMAStop(), and UART_DMAError().

HAL_StatusTypeDef UART_Receive_IT ( UART_HandleTypeDef * huart )

Receive an amount of data in interrupt mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()
Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2717 of file stm32f3xx_hal_uart.c.

References __HAL_UART_SEND_REQ, HAL_UART_RxCpltCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_HandleTypeDef::Mask, UART_InitTypeDef::Parity, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_PARITY_NONE, UART_RXDATA_FLUSH_REQUEST, UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

Referenced by HAL_UART_IRQHandler().

HAL_StatusTypeDef UART_SetConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2096 of file stm32f3xx_hal_uart.c.

References assert_param, UART_InitTypeDef::BaudRate, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, UART_InitTypeDef::HwFlowCtl, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_UART_BAUDRATE, IS_UART_HARDWARE_FLOW_CONTROL, IS_UART_MODE, IS_UART_ONE_BIT_SAMPLE, IS_UART_OVERSAMPLING, IS_UART_PARITY, IS_UART_STOPBITS, IS_UART_WORD_LENGTH, LSE_VALUE, UART_InitTypeDef::Mode, UART_InitTypeDef::OneBitSampling, UART_InitTypeDef::OverSampling, UART_InitTypeDef::Parity, UART_InitTypeDef::StopBits, UART_CLOCKSOURCE_HSI, UART_CLOCKSOURCE_LSE, UART_CLOCKSOURCE_PCLK1, UART_CLOCKSOURCE_PCLK2, UART_CLOCKSOURCE_SYSCLK, UART_CLOCKSOURCE_UNDEFINED, UART_CR1_FIELDS, UART_DIV_SAMPLING16, UART_DIV_SAMPLING8, UART_GETCLOCKSOURCE, UART_OVERSAMPLING_8, and UART_InitTypeDef::WordLength.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

HAL_StatusTypeDef UART_Transmit_IT ( UART_HandleTypeDef * huart )

Send an amount of data in interrupt mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2651 of file stm32f3xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::TxXferCount, UART_PARITY_NONE, UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

Referenced by HAL_UART_IRQHandler().

HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  |

Handle UART Communication Timeout.

Parameters:
huart | UART handle.
Flag | Specifies the UART flag to check
Status | Flag status (SET or RESET)
Tickstart | Tick start value
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2331 of file stm32f3xx_hal_uart.c.

References __HAL_UART_GET_FLAG, UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UARTEx_StopModeWakeUpSourceConfig(), and UART_CheckIdleState().

void UART_Wakeup_AddressConfig | ( | UART_HandleTypeDef * | huart,
 |  | UART_WakeUpTypeDef | WakeUpSelection
 | ) |  |

Initialize the UART wake-up from stop mode parameters when triggered by address detection.

Parameters:
huart | UART handle.
WakeUpSelection | UART wake up from stop mode parameters.
Return values:
None

Definition at line 2771 of file stm32f3xx_hal_uart.c.

References UART_WakeUpTypeDef::Address, UART_WakeUpTypeDef::AddressLength, assert_param, UART_HandleTypeDef::Instance, IS_UART_ADDRESSLENGTH_DETECT, and UART_CR2_ADDRESS_LSB_POS.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Exported Types

Data Structures | Enumerations
UART Exported Types
UART

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_AdvFeatureInitTypeDef
UART Advanced Features initalization structure definition. More...
struct | UART_WakeUpTypeDef
UART wake up from stop mode parameters. More...
struct | UART_HandleTypeDef
UART handle Structure definition. More...

Enumerations

enum HAL_UART_StateTypeDef {
HAL_UART_STATE_RESET = 0x00U, HAL_UART_STATE_READY = 0x20U, HAL_UART_STATE_BUSY = 0x24U, HAL_UART_STATE_BUSY_TX = 0x21U,
HAL_UART_STATE_BUSY_RX = 0x22U, HAL_UART_STATE_BUSY_TX_RX = 0x23U, HAL_UART_STATE_TIMEOUT = 0xA0U, HAL_UART_STATE_ERROR = 0xE0U
}
HAL UART State structures definition. More...
enum UART_ClockSourceTypeDef {
UART_CLOCKSOURCE_PCLK1 = 0x00U, UART_CLOCKSOURCE_PCLK2 = 0x01U, UART_CLOCKSOURCE_HSI = 0x02U, UART_CLOCKSOURCE_SYSCLK = 0x04U,
UART_CLOCKSOURCE_LSE = 0x08U, UART_CLOCKSOURCE_UNDEFINED = 0x10U
}
UART clock sources definition. More...

Enumeration Type Documentation

enum HAL_UART_StateTypeDef

HAL UART State structures definition.

Note:
HAL UART State value is a combination of 2 different substates: gState and RxState.
  • gState contains UART state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized. HAL UART Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
Enumerator:
HAL_UART_STATE_RESET

Peripheral is not initialized Value is allowed for gState and RxState

HAL_UART_STATE_READY

Peripheral Initialized and ready for use Value is allowed for gState and RxState

HAL_UART_STATE_BUSY

an internal process is ongoing Value is allowed for gState only

HAL_UART_STATE_BUSY_TX

Data Transmission process is ongoing Value is allowed for gState only

HAL_UART_STATE_BUSY_RX

Data Reception process is ongoing Value is allowed for RxState only

HAL_UART_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

HAL_UART_STATE_TIMEOUT

Timeout state Value is allowed for gState only

HAL_UART_STATE_ERROR

Error Value is allowed for gState only

Definition at line 196 of file stm32f3xx_hal_uart.h.

enum UART_ClockSourceTypeDef

UART clock sources definition.

Enumerator:
UART_CLOCKSOURCE_PCLK1

PCLK1 clock source

UART_CLOCKSOURCE_PCLK2

PCLK2 clock source

UART_CLOCKSOURCE_HSI

HSI clock source

UART_CLOCKSOURCE_SYSCLK

SYSCLK clock source

UART_CLOCKSOURCE_LSE

LSE clock source

UART_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 220 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_InitTypeDef Struct Reference
UART Exported Types

UART Init Structure definition. More...

#include <stm32f3xx_hal_uart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | HwFlowCtl
uint32_t | OverSampling
uint32_t | OneBitSampling

Detailed Description

UART Init Structure definition.

Definition at line 63 of file stm32f3xx_hal_uart.h.

Field Documentation

uint32_t UART_InitTypeDef::BaudRate

This member configures the UART communication baud rate. The baud rate register is computed using the following formula:

  • If oversampling is 16 or in LIN mode, Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
  • If oversampling is 8U, Baud Rate Register[15:4] = ((2U * PCLKx) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 Baud Rate Register[2:0] = (((2U * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1

Definition at line 65 of file stm32f3xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::HwFlowCtl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of UART Hardware Flow Control.

Definition at line 90 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of UART Transfer Mode.

Definition at line 87 of file stm32f3xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OneBitSampling

Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of UART One Bit Sampling Method.

Definition at line 97 of file stm32f3xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OverSampling

Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8U). This parameter can be a value of UART Over Sampling.

Definition at line 94 of file stm32f3xx_hal_uart.h.

Referenced by HAL_LIN_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of UART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 80 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

uint32_t UART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of UART Number of Stop Bits.

Definition at line 77 of file stm32f3xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of UARTEx Word Length.

Definition at line 74 of file stm32f3xx_hal_uart.h.

Referenced by HAL_LIN_Init(), HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_uart.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART_AdvFeatureInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_AdvFeatureInitTypeDef Struct Reference
UART Exported Types

UART Advanced Features initalization structure definition. More...

#include <stm32f3xx_hal_uart.h>

Data Fields

uint32_t | AdvFeatureInit
uint32_t | TxPinLevelInvert
uint32_t | RxPinLevelInvert
uint32_t | DataInvert
uint32_t | Swap
uint32_t | OverrunDisable
uint32_t | DMADisableonRxError
uint32_t | AutoBaudRateEnable
uint32_t | AutoBaudRateMode
uint32_t | MSBFirst

Detailed Description

UART Advanced Features initalization structure definition.

Definition at line 105 of file stm32f3xx_hal_uart.h.

Field Documentation

uint32_t UART_AdvFeatureInitTypeDef::AdvFeatureInit

Specifies which advanced UART features is initialized. Several Advanced Features may be initialized at the same time . This parameter can be a value of UART Advanced Feature Initialization Type.

Definition at line 107 of file stm32f3xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::AutoBaudRateEnable

Specifies whether auto Baud rate detection is enabled. This parameter can be a value of UART Advanced Feature Auto BaudRate Enable

Definition at line 130 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::AutoBaudRateMode

If auto Baud rate detection is enabled, specifies how the rate detection is carried out. This parameter can be a value of UART Advanced Feature AutoBaud Rate Mode.

Definition at line 133 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::DataInvert

Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of UART Advanced Feature Binary Data Inversion.

Definition at line 117 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::DMADisableonRxError

Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of UART Advanced Feature DMA Disable On Rx Error.

Definition at line 127 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::MSBFirst

Specifies whether MSB is sent first on UART line. This parameter can be a value of UART Advanced Feature MSB First.

Definition at line 137 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::OverrunDisable

Specifies whether the reception overrun detection is disabled. This parameter can be a value of UART Advanced Feature Overrun Disable.

Definition at line 124 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::RxPinLevelInvert

Specifies whether the RX pin active level is inverted. This parameter can be a value of UART Advanced Feature RX Pin Active Level Inversion.

Definition at line 114 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::Swap

Specifies whether TX and RX pins are swapped. This parameter can be a value of UART Advanced Feature RX TX Pins Swap.

Definition at line 121 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::TxPinLevelInvert

Specifies whether the TX pin active level is inverted. This parameter can be a value of UART Advanced Feature TX Pin Active Level Inversion.

Definition at line 111 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_uart.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART_WakeUpTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_WakeUpTypeDef Struct Reference
UART Exported Types

UART wake up from stop mode parameters. More...

#include <stm32f3xx_hal_uart.h>

Data Fields

uint32_t | WakeUpEvent
uint16_t | AddressLength
uint8_t | Address

Detailed Description

UART wake up from stop mode parameters.

Definition at line 144 of file stm32f3xx_hal_uart.h.

Field Documentation

uint8_t UART_WakeUpTypeDef::Address

UART/USART node address (7-bit long max).

Definition at line 154 of file stm32f3xx_hal_uart.h.

Referenced by UART_Wakeup_AddressConfig().

uint16_t UART_WakeUpTypeDef::AddressLength

Specifies whether the address is 4 or 7-bit long. This parameter can be a value of UART WakeUp Address Length.

Definition at line 151 of file stm32f3xx_hal_uart.h.

Referenced by UART_Wakeup_AddressConfig().

uint32_t UART_WakeUpTypeDef::WakeUpEvent

Specifies which event will activat the Wakeup from Stop mode flag (WUF). This parameter can be a value of UART WakeUp From Stop Selection. If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must be filled up.

Definition at line 146 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_uart.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_HandleTypeDef Struct Reference
UART Exported Types

UART handle Structure definition. More...

#include <stm32f3xx_hal_uart.h>

Data Fields

USART_TypeDef * | Instance
UART_InitTypeDef Init
UART_AdvFeatureInitTypeDef AdvancedInit
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_UART_StateTypeDef | gState
__IO HAL_UART_StateTypeDef | RxState
__IO uint32_t | ErrorCode

Detailed Description

UART handle Structure definition.

Definition at line 233 of file stm32f3xx_hal_uart.h.

Field Documentation

UART_AdvFeatureInitTypeDef UART_HandleTypeDef::AdvancedInit

UART Advanced Features initialization parameters

Definition at line 239 of file stm32f3xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and UART_AdvFeatureConfig().

__IO uint32_t UART_HandleTypeDef::ErrorCode

UART Error code

Definition at line 268 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_DeInit(), HAL_UART_GetError(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_CheckIdleState(), UART_DMAError(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

__IO HAL_UART_StateTypeDef UART_HandleTypeDef::gState

UART state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 261 of file stm32f3xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_GetState(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UARTEx_DisableStopMode(), HAL_UARTEx_EnableStopMode(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_CheckIdleState(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_Transmit_IT(), and UART_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* UART_HandleTypeDef::hdmarx

UART Rx DMA Handle parameters

Definition at line 257 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAStop(), HAL_UART_IRQHandler(), HAL_UART_Receive_DMA(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

DMA_HandleTypeDef* UART_HandleTypeDef::hdmatx

UART Tx DMA Handle parameters

Definition at line 255 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DMAStop(), HAL_UART_Transmit_DMA(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

UART_InitTypeDef UART_HandleTypeDef::Init

UART communication parameters

Definition at line 237 of file stm32f3xx_hal_uart.h.

Referenced by HAL_LIN_Init(), HAL_UART_Init(), HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

USART_TypeDef* UART_HandleTypeDef::Instance

UART registers base address

Definition at line 235 of file stm32f3xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UARTEx_DisableStopMode(), HAL_UARTEx_EnableStopMode(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), UART_EndRxTransfer(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_Receive_IT(), UART_SetConfig(), UART_Transmit_IT(), UART_WaitOnFlagUntilTimeout(), and UART_Wakeup_AddressConfig().

HAL_LockTypeDef UART_HandleTypeDef::Lock

Locking object

Definition at line 259 of file stm32f3xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

uint16_t UART_HandleTypeDef::Mask

UART Rx RDR register mask

Definition at line 253 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Receive(), and UART_Receive_IT().

uint8_t* UART_HandleTypeDef::pRxBuffPtr

Pointer to UART Rx transfer Buffer

Definition at line 247 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), and UART_Receive_IT().

uint8_t* UART_HandleTypeDef::pTxBuffPtr

Pointer to UART Tx transfer Buffer

Definition at line 241 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), and UART_Transmit_IT().

__IO HAL_UART_StateTypeDef UART_HandleTypeDef::RxState

UART state information related to Rx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 265 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_GetState(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), UART_CheckIdleState(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_EndRxTransfer(), UART_Receive_IT(), and UART_WaitOnFlagUntilTimeout().

__IO uint16_t UART_HandleTypeDef::RxXferCount

UART Rx Transfer Counter

Definition at line 251 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_Receive(), HAL_UART_Receive_IT(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), and UART_Receive_IT().

uint16_t UART_HandleTypeDef::RxXferSize

UART Rx Transfer size

Definition at line 249 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_DMA(), and HAL_UART_Receive_IT().

__IO uint16_t UART_HandleTypeDef::TxXferCount

UART Tx Transfer Counter

Definition at line 245 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATransmitCplt(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), and UART_Transmit_IT().

uint16_t UART_HandleTypeDef::TxXferSize

UART Tx Transfer size

Definition at line 243 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), and HAL_UART_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_uart.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Error

Defines
UART Error
UART Exported Constants

Defines

#define | HAL_UART_ERROR_NONE (0x00000000U)
#define | HAL_UART_ERROR_PE (0x00000001U)
#define | HAL_UART_ERROR_NE (0x00000002U)
#define | HAL_UART_ERROR_FE (0x00000004U)
#define | HAL_UART_ERROR_ORE (0x00000008U)
#define | HAL_UART_ERROR_DMA (0x00000010U)
#define | HAL_UART_ERROR_BUSY (0x00000020U)

Define Documentation

#define HAL_UART_ERROR_BUSY (0x00000020U)

Busy Error

Definition at line 290 of file stm32f3xx_hal_uart.h.

#define HAL_UART_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 289 of file stm32f3xx_hal_uart.h.

Referenced by UART_DMAError().

#define HAL_UART_ERROR_FE (0x00000004U)

frame error

Definition at line 287 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_NE (0x00000002U)

Noise error

Definition at line 286 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_NONE (0x00000000U)

No error

Definition at line 284 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_DeInit(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_CheckIdleState(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

#define HAL_UART_ERROR_ORE (0x00000008U)

Overrun error

Definition at line 288 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_PE (0x00000001U)

Parity error

Definition at line 285 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Number of Stop Bits

Defines
UART Number of Stop Bits
UART Exported Constants

Defines

#define | UART_STOPBITS_0_5 USART_CR2_STOP_0
#define | UART_STOPBITS_1 (0x00000000U)
#define | UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define | UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)

Define Documentation

#define UART_STOPBITS_0_5 USART_CR2_STOP_0

UART frame with 0.5 stop bit

Definition at line 298 of file stm32f3xx_hal_uart.h.

#define UART_STOPBITS_1 (0x00000000U)

UART frame with 1 stop bit

Definition at line 299 of file stm32f3xx_hal_uart.h.

#define UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

UART frame with 1.5 stop bits

Definition at line 300 of file stm32f3xx_hal_uart.h.

#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)

UART frame with 2 stop bits

Definition at line 301 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Parity

Defines
UART Parity
UART Exported Constants

Defines

#define | UART_PARITY_NONE (0x00000000U)
#define | UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Even parity

Definition at line 310 of file stm32f3xx_hal_uart.h.

#define UART_PARITY_NONE (0x00000000U)

No parity

Definition at line 309 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), and UART_Transmit_IT().

#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Odd parity

Definition at line 311 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Hardware Flow Control

Defines
UART Hardware Flow Control
UART Exported Constants

Defines

#define | UART_HWCONTROL_NONE (0x00000000U)
#define | UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define | UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define | UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))

Define Documentation

#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)

Clear To Send

Definition at line 321 of file stm32f3xx_hal_uart.h.

#define UART_HWCONTROL_NONE (0x00000000U)

No hardware control

Definition at line 319 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Init().

#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)

Request To Send

Definition at line 320 of file stm32f3xx_hal_uart.h.

#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))

Request and Clear To Send

Definition at line 322 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Transfer Mode

Defines
UART Transfer Mode
UART Exported Constants

Defines

#define | UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define UART_MODE_RX ((uint32_t)USART_CR1_RE)

RX mode

Definition at line 330 of file stm32f3xx_hal_uart.h.

#define UART_MODE_TX ((uint32_t)USART_CR1_TE)

TX mode

Definition at line 331 of file stm32f3xx_hal_uart.h.

#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

RX and TX mode

Definition at line 332 of file stm32f3xx_hal_uart.h.

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STM32F373xC HAL User Manual: UART State

Defines
UART State
UART Exported Constants

Defines

#define | UART_STATE_DISABLE (0x00000000U)
#define | UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)

Define Documentation

#define UART_STATE_DISABLE (0x00000000U)

UART disabled

Definition at line 340 of file stm32f3xx_hal_uart.h.

#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)

UART enabled

Definition at line 341 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Over Sampling

Defines
UART Over Sampling
UART Exported Constants

Defines

#define | UART_OVERSAMPLING_16 (0x00000000U)
#define | UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)

Define Documentation

#define UART_OVERSAMPLING_16 (0x00000000U)

Oversampling by 16U

Definition at line 349 of file stm32f3xx_hal_uart.h.

#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)

Oversampling by 8

Definition at line 350 of file stm32f3xx_hal_uart.h.

Referenced by HAL_LIN_Init(), and UART_SetConfig().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART One Bit Sampling Method

Defines
UART One Bit Sampling Method
UART Exported Constants

Defines

#define | UART_ONE_BIT_SAMPLE_DISABLE (0x00000000U)
#define | UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

Define Documentation

#define UART_ONE_BIT_SAMPLE_DISABLE (0x00000000U)

One-bit sampling disable

Definition at line 358 of file stm32f3xx_hal_uart.h.

#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

One-bit sampling enable

Definition at line 359 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Advanced Feature AutoBaud Rate Mode

Defines
UART Advanced Feature AutoBaud Rate Mode
UART Exported Constants

Defines

#define | UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT (0x00000000U)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)

Auto Baud rate detection on 0x55 frame detection

Definition at line 370 of file stm32f3xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)

Auto Baud rate detection on 0x7F frame detection

Definition at line 369 of file stm32f3xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)

Auto Baud rate detection on falling edge

Definition at line 368 of file stm32f3xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT (0x00000000U)

Auto Baud rate detection on start bit

Definition at line 367 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Receiver TimeOut

Defines
UART Receiver TimeOut
UART Exported Constants

Defines

#define | UART_RECEIVER_TIMEOUT_DISABLE (0x00000000U)
#define | UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)

Define Documentation

#define UART_RECEIVER_TIMEOUT_DISABLE (0x00000000U)

UART receiver timeout disable

Definition at line 378 of file stm32f3xx_hal_uart.h.

#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)

UART receiver timeout enable

Definition at line 379 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Local Interconnection Network mode

Defines
UART Local Interconnection Network mode
UART Exported Constants

Defines

#define | UART_LIN_DISABLE (0x00000000U)
#define | UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)

Define Documentation

#define UART_LIN_DISABLE (0x00000000U)

Local Interconnect Network disable

Definition at line 387 of file stm32f3xx_hal_uart.h.

#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)

Local Interconnect Network enable

Definition at line 388 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART LIN Break Detection

Defines
UART LIN Break Detection
UART Exported Constants

Defines

#define | UART_LINBREAKDETECTLENGTH_10B (0x00000000U)
#define | UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)

Define Documentation

#define UART_LINBREAKDETECTLENGTH_10B (0x00000000U)

LIN 10-bit break detection length

Definition at line 396 of file stm32f3xx_hal_uart.h.

#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)

LIN 11-bit break detection length

Definition at line 397 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART DMA Tx

Defines
UART DMA Tx
UART Exported Constants

Defines

#define | UART_DMA_TX_DISABLE (0x00000000U)
#define | UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)

Define Documentation

#define UART_DMA_TX_DISABLE (0x00000000U)

UART DMA TX disabled

Definition at line 405 of file stm32f3xx_hal_uart.h.

#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)

UART DMA TX enabled

Definition at line 406 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART DMA Rx

Defines
UART DMA Rx
UART Exported Constants

Defines

#define | UART_DMA_RX_DISABLE (0x00000000U)
#define | UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)

Define Documentation

#define UART_DMA_RX_DISABLE (0x00000000U)

UART DMA RX disabled

Definition at line 414 of file stm32f3xx_hal_uart.h.

#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)

UART DMA RX enabled

Definition at line 415 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Half Duplex Selection

Defines
UART Half Duplex Selection
UART Exported Constants

Defines

#define | UART_HALF_DUPLEX_DISABLE (0x00000000U)
#define | UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)

Define Documentation

#define UART_HALF_DUPLEX_DISABLE (0x00000000U)

UART half-duplex disabled

Definition at line 423 of file stm32f3xx_hal_uart.h.

#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)

UART half-duplex enabled

Definition at line 424 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART WakeUp Address Length

Defines
UART WakeUp Address Length
UART Exported Constants

Defines

#define | UART_ADDRESS_DETECT_4B (0x00000000U)
#define | UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)

Define Documentation

#define UART_ADDRESS_DETECT_4B (0x00000000U)

4-bit long wake-up address

Definition at line 432 of file stm32f3xx_hal_uart.h.

#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)

7-bit long wake-up address

Definition at line 433 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART WakeUp Methods

Defines
UART WakeUp Methods
UART Exported Constants

Defines

#define | UART_WAKEUPMETHOD_IDLELINE (0x00000000U)
#define | UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)

Define Documentation

#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)

UART wake-up on address mark

Definition at line 442 of file stm32f3xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define UART_WAKEUPMETHOD_IDLELINE (0x00000000U)

UART wake-up on idle line

Definition at line 441 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Status Flags

Defines
UART Status Flags
UART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | UART_FLAG_REACK (0x00400000U)
#define | UART_FLAG_TEACK (0x00200000U)
#define | UART_FLAG_WUF (0x00100000U)
#define | UART_FLAG_RWU (0x00080000U)
#define | UART_FLAG_SBKF (0x00040000U)
#define | UART_FLAG_CMF (0x00020000U)
#define | UART_FLAG_BUSY (0x00010000U)
#define | UART_FLAG_ABRF (0x00008000U)
#define | UART_FLAG_ABRE (0x00004000U)
#define | UART_FLAG_EOBF (0x00001000U)
#define | UART_FLAG_RTOF (0x00000800U)
#define | UART_FLAG_CTS (0x00000400U)
#define | UART_FLAG_CTSIF (0x00000200U)
#define | UART_FLAG_LBDF (0x00000100U)
#define | UART_FLAG_TXE (0x00000080U)
#define | UART_FLAG_TC (0x00000040U)
#define | UART_FLAG_RXNE (0x00000020U)
#define | UART_FLAG_IDLE (0x00000010U)
#define | UART_FLAG_ORE (0x00000008U)
#define | UART_FLAG_NE (0x00000004U)
#define | UART_FLAG_FE (0x00000002U)
#define | UART_FLAG_PE (0x00000001U)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define UART_FLAG_ABRE (0x00004000U)

UART auto Baud rate error

Definition at line 460 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_ABRF (0x00008000U)

UART auto Baud rate flag

Definition at line 459 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_BUSY (0x00010000U)

UART busy flag

Definition at line 458 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_CMF (0x00020000U)

UART character match flag

Definition at line 457 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_CTS (0x00000400U)

UART clear to send flag

Definition at line 463 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_CTSIF (0x00000200U)

UART clear to send interrupt flag

Definition at line 464 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_EOBF (0x00001000U)

UART end of block flag

Definition at line 461 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_FE (0x00000002U)

UART frame error

Definition at line 472 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_IDLE (0x00000010U)

UART idle flag

Definition at line 469 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_LBDF (0x00000100U)

UART LIN break detection flag

Definition at line 465 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_NE (0x00000004U)

UART noise error

Definition at line 471 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_ORE (0x00000008U)

UART overrun error

Definition at line 470 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_PE (0x00000001U)

UART parity error

Definition at line 473 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_REACK (0x00400000U)

UART receive enable acknowledge flag

Definition at line 452 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_RTOF (0x00000800U)

UART receiver timeout flag

Definition at line 462 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_RWU (0x00080000U)

UART receiver wake-up from mute mode flag

Definition at line 455 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_RXNE (0x00000020U)

UART read data register not empty

Definition at line 468 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Receive().

#define UART_FLAG_SBKF (0x00040000U)

UART send break flag

Definition at line 456 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_TC (0x00000040U)

UART transmission complete

Definition at line 467 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Transmit().

#define UART_FLAG_TEACK (0x00200000U)

UART transmit enable acknowledge flag

Definition at line 453 of file stm32f3xx_hal_uart.h.

#define UART_FLAG_TXE (0x00000080U)

UART transmit data register empty

Definition at line 466 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Transmit().

#define UART_FLAG_WUF (0x00100000U)

UART wake-up from stop mode flag

Definition at line 454 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Interrupts Definition

Defines
UART Interrupts Definition
UART Exported Constants

Elements values convention: 000ZZZZZ0XXYYYYYb. More...

Defines

#define | UART_IT_PE (0x0028U)
#define | UART_IT_TXE (0x0727U)
#define | UART_IT_TC (0x0626U)
#define | UART_IT_RXNE (0x0525U)
#define | UART_IT_IDLE (0x0424U)
#define | UART_IT_LBD (0x0846U)
#define | UART_IT_CTS (0x096AU)
#define | UART_IT_CM (0x112EU)
#define | UART_IT_WUF (0x1476U)
#define | UART_IT_ERR (0x0060U)
#define | UART_IT_ORE (0x0300U)
#define | UART_IT_NE (0x0200U)
#define | UART_IT_FE (0x0100U)

Detailed Description

Elements values convention: 000ZZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZZ : Flag position in the ISR register(5bits)

Define Documentation

#define UART_IT_CM (0x112EU)

UART character match interruption

Definition at line 495 of file stm32f3xx_hal_uart.h.

#define UART_IT_CTS (0x096AU)

UART CTS interruption

Definition at line 494 of file stm32f3xx_hal_uart.h.

#define UART_IT_ERR (0x0060U)

UART error interruption

Definition at line 497 of file stm32f3xx_hal_uart.h.

#define UART_IT_FE (0x0100U)

UART frame error interruption

Definition at line 500 of file stm32f3xx_hal_uart.h.

#define UART_IT_IDLE (0x0424U)

UART idle interruption

Definition at line 492 of file stm32f3xx_hal_uart.h.

#define UART_IT_LBD (0x0846U)

UART LIN break detection interruption

Definition at line 493 of file stm32f3xx_hal_uart.h.

#define UART_IT_NE (0x0200U)

UART noise error interruption

Definition at line 499 of file stm32f3xx_hal_uart.h.

#define UART_IT_ORE (0x0300U)

UART overrun error interruption

Definition at line 498 of file stm32f3xx_hal_uart.h.

#define UART_IT_PE (0x0028U)

UART parity error interruption

Definition at line 488 of file stm32f3xx_hal_uart.h.

#define UART_IT_RXNE (0x0525U)

UART read data register not empty interruption

Definition at line 491 of file stm32f3xx_hal_uart.h.

#define UART_IT_TC (0x0626U)

UART transmission complete interruption

Definition at line 490 of file stm32f3xx_hal_uart.h.

#define UART_IT_TXE (0x0727U)

UART transmit data register empty interruption

Definition at line 489 of file stm32f3xx_hal_uart.h.

#define UART_IT_WUF (0x1476U)

UART wake-up from stop mode interruption

Definition at line 496 of file stm32f3xx_hal_uart.h.

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STM32F373xC HAL User Manual: UART Interruption Clear Flags

Defines
UART Interruption Clear Flags
UART Exported Constants

Defines

#define | UART_CLEAR_PEF USART_ICR_PECF
#define | UART_CLEAR_FEF USART_ICR_FECF
#define | UART_CLEAR_NEF USART_ICR_NCF
#define | UART_CLEAR_OREF USART_ICR_ORECF
#define | UART_CLEAR_IDLEF USART_ICR_IDLECF
#define | UART_CLEAR_TCF USART_ICR_TCCF
#define | UART_CLEAR_LBDF USART_ICR_LBDCF
#define | UART_CLEAR_CTSF USART_ICR_CTSCF
#define | UART_CLEAR_RTOF USART_ICR_RTOCF
#define | UART_CLEAR_EOBF USART_ICR_EOBCF
#define | UART_CLEAR_CMF USART_ICR_CMCF
#define | UART_CLEAR_WUF USART_ICR_WUCF

Define Documentation

#define UART_CLEAR_CMF USART_ICR_CMCF

Character Match Clear Flag

Definition at line 518 of file stm32f3xx_hal_uart.h.

#define UART_CLEAR_CTSF USART_ICR_CTSCF

CTS Interrupt Clear Flag

Definition at line 515 of file stm32f3xx_hal_uart.h.

#define UART_CLEAR_EOBF USART_ICR_EOBCF

End Of Block Clear Flag

Definition at line 517 of file stm32f3xx_hal_uart.h.

#define UART_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 509 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define UART_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 512 of file stm32f3xx_hal_uart.h.

#define UART_CLEAR_LBDF USART_ICR_LBDCF

LIN Break Detection Clear Flag

Definition at line 514 of file stm32f3xx_hal_uart.h.

#define UART_CLEAR_NEF USART_ICR_NCF

Noise detected Clear Flag

Definition at line 510 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define UART_CLEAR_OREF USART_ICR_ORECF

Overrun Error Clear Flag

Definition at line 511 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAResume(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define UART_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 508 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define UART_CLEAR_RTOF USART_ICR_RTOCF

Receiver Time Out Clear Flag

Definition at line 516 of file stm32f3xx_hal_uart.h.

#define UART_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 513 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA().

#define UART_CLEAR_WUF USART_ICR_WUCF

Wake Up from stop mode Clear Flag

Definition at line 519 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

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STM32F373xC HAL User Manual: UART Request Parameters

Defines
UART Request Parameters
UART Exported Constants

Defines

#define | UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ)
#define | UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ)
#define | UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ)
#define | UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Define Documentation

#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ)

Auto-Baud Rate Request

Definition at line 527 of file stm32f3xx_hal_uart.h.

#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ)

Mute Mode Request

Definition at line 529 of file stm32f3xx_hal_uart.h.

Referenced by HAL_MultiProcessor_EnterMuteMode().

#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)

Receive Data flush Request

Definition at line 530 of file stm32f3xx_hal_uart.h.

Referenced by UART_Receive_IT().

#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ)

Send Break Request

Definition at line 528 of file stm32f3xx_hal_uart.h.

Referenced by HAL_LIN_SendBreak().

#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Transmit data flush Request

Definition at line 531 of file stm32f3xx_hal_uart.h.

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STM32F373xC HAL User Manual: UART Advanced Feature Initialization Type

Defines
UART Advanced Feature Initialization Type
UART Exported Constants

Defines

#define | UART_ADVFEATURE_NO_INIT (0x00000000U)
#define | UART_ADVFEATURE_TXINVERT_INIT (0x00000001U)
#define | UART_ADVFEATURE_RXINVERT_INIT (0x00000002U)
#define | UART_ADVFEATURE_DATAINVERT_INIT (0x00000004U)
#define | UART_ADVFEATURE_SWAP_INIT (0x00000008U)
#define | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U)
#define | UART_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U)
#define | UART_ADVFEATURE_AUTOBAUDRATE_INIT (0x00000040U)
#define | UART_ADVFEATURE_MSBFIRST_INIT (0x00000080U)

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_INIT (0x00000040U)

Auto Baud rate detection initialization

Definition at line 546 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_DATAINVERT_INIT (0x00000004U)

Binary data inversion

Definition at line 542 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U)

DMA disable on Reception Error

Definition at line 545 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_MSBFIRST_INIT (0x00000080U)

Most significant bit sent/received first

Definition at line 547 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_NO_INIT (0x00000000U)

No advanced feature initialization

Definition at line 539 of file stm32f3xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

#define UART_ADVFEATURE_RXINVERT_INIT (0x00000002U)

RX pin active level inversion

Definition at line 541 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U)

RX overrun disable

Definition at line 544 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_SWAP_INIT (0x00000008U)

TX/RX pins swap

Definition at line 543 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_TXINVERT_INIT (0x00000001U)

TX pin active level inversion

Definition at line 540 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

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STM32F373xC HAL User Manual: UART Advanced Feature TX Pin Active Level Inversion

Defines
UART Advanced Feature TX Pin Active Level Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_TXINV_DISABLE (0x00000000U)
#define | UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)

Define Documentation

#define UART_ADVFEATURE_TXINV_DISABLE (0x00000000U)

TX pin active level inversion disable

Definition at line 555 of file stm32f3xx_hal_uart.h.

#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)

TX pin active level inversion enable

Definition at line 556 of file stm32f3xx_hal_uart.h.

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STM32F373xC HAL User Manual: UART Advanced Feature RX Pin Active Level Inversion

Defines
UART Advanced Feature RX Pin Active Level Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_RXINV_DISABLE (0x00000000U)
#define | UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)

Define Documentation

#define UART_ADVFEATURE_RXINV_DISABLE (0x00000000U)

RX pin active level inversion disable

Definition at line 564 of file stm32f3xx_hal_uart.h.

#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)

RX pin active level inversion enable

Definition at line 565 of file stm32f3xx_hal_uart.h.

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STM32F373xC HAL User Manual: UART Advanced Feature Binary Data Inversion

Defines
UART Advanced Feature Binary Data Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_DATAINV_DISABLE (0x00000000U)
#define | UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)

Define Documentation

#define UART_ADVFEATURE_DATAINV_DISABLE (0x00000000U)

Binary data inversion disable

Definition at line 573 of file stm32f3xx_hal_uart.h.

#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)

Binary data inversion enable

Definition at line 574 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Advanced Feature RX TX Pins Swap

Defines
UART Advanced Feature RX TX Pins Swap
UART Exported Constants

Defines

#define | UART_ADVFEATURE_SWAP_DISABLE (0x00000000U)
#define | UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)

Define Documentation

#define UART_ADVFEATURE_SWAP_DISABLE (0x00000000U)

TX/RX pins swap disable

Definition at line 582 of file stm32f3xx_hal_uart.h.

#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)

TX/RX pins swap enable

Definition at line 583 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Advanced Feature Overrun Disable

Defines
UART Advanced Feature Overrun Disable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_OVERRUN_ENABLE (0x00000000U)
#define | UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)

Define Documentation

#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)

RX overrun disable

Definition at line 592 of file stm32f3xx_hal_uart.h.

#define UART_ADVFEATURE_OVERRUN_ENABLE (0x00000000U)

RX overrun enable

Definition at line 591 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Advanced Feature Auto BaudRate Enable

Defines
UART Advanced Feature Auto BaudRate Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE (0x00000000U)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE (0x00000000U)

RX Auto Baud rate detection enable

Definition at line 600 of file stm32f3xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)

RX Auto Baud rate detection disable

Definition at line 601 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Advanced Feature DMA Disable On Rx Error

Defines
UART Advanced Feature DMA Disable On Rx Error
UART Exported Constants

Defines

#define | UART_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U)
#define | UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)

Define Documentation

#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)

DMA disable on Reception Error

Definition at line 610 of file stm32f3xx_hal_uart.h.

#define UART_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U)

DMA enable on Reception Error

Definition at line 609 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Advanced Feature MSB First

Defines
UART Advanced Feature MSB First
UART Exported Constants

Defines

#define | UART_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U)
#define | UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)

Define Documentation

#define UART_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U)

Most significant bit sent/received first disable

Definition at line 618 of file stm32f3xx_hal_uart.h.

#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)

Most significant bit sent/received first enable

Definition at line 619 of file stm32f3xx_hal_uart.h.

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STM32F373xC HAL User Manual: UART Advanced Feature Stop Mode Enable

Defines
UART Advanced Feature Stop Mode Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_STOPMODE_DISABLE (0x00000000U)
#define | UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM)

Define Documentation

#define UART_ADVFEATURE_STOPMODE_DISABLE (0x00000000U)

UART stop mode disable

Definition at line 627 of file stm32f3xx_hal_uart.h.

#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM)

UART stop mode enable

Definition at line 628 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Advanced Feature Mute Mode Enable

Defines
UART Advanced Feature Mute Mode Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_MUTEMODE_DISABLE (0x00000000U)
#define | UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)

Define Documentation

#define UART_ADVFEATURE_MUTEMODE_DISABLE (0x00000000U)

UART mute mode disable

Definition at line 636 of file stm32f3xx_hal_uart.h.

#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)

UART mute mode enable

Definition at line 637 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Address-matching LSB Position In CR2 Register

Defines
UART Address-matching LSB Position In CR2 Register
UART Exported Constants

Defines

#define UART_CR2_ADDRESS_LSB_POS ( 24U)

Define Documentation

#define UART_CR2_ADDRESS_LSB_POS ( 24U)

UART address-matching LSB position in CR2 register

Definition at line 645 of file stm32f3xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init(), and UART_Wakeup_AddressConfig().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART WakeUp From Stop Selection

Defines
UART WakeUp From Stop Selection
UART Exported Constants

Defines

#define | UART_WAKEUP_ON_ADDRESS (0x00000000U)
#define | UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1)
#define | UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS)

Define Documentation

#define UART_WAKEUP_ON_ADDRESS (0x00000000U)

UART wake-up on address

Definition at line 653 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS)

UART wake-up on receive data register not empty

Definition at line 655 of file stm32f3xx_hal_uart.h.

#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1)

UART wake-up on start bit

Definition at line 654 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART DriverEnable Polarity

Defines
UART DriverEnable Polarity
UART Exported Constants

Defines

#define | UART_DE_POLARITY_HIGH (0x00000000U)
#define | UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)

Define Documentation

#define UART_DE_POLARITY_HIGH (0x00000000U)

Driver enable signal is active high

Definition at line 663 of file stm32f3xx_hal_uart.h.

#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)

Driver enable signal is active low

Definition at line 664 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Driver Enable Assertion Time LSB Position In CR1 Register

Defines
UART Driver Enable Assertion Time LSB Position In CR1 Register
UART Exported Constants

Defines

#define UART_CR1_DEAT_ADDRESS_LSB_POS ( 21U)

Define Documentation

#define UART_CR1_DEAT_ADDRESS_LSB_POS ( 21U)

UART Driver Enable assertion time LSB position in CR1 register

Definition at line 672 of file stm32f3xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Driver Enable DeAssertion Time LSB Position In CR1 Register

Defines
UART Driver Enable DeAssertion Time LSB Position In CR1 Register
UART Exported Constants

Defines

#define UART_CR1_DEDT_ADDRESS_LSB_POS ( 16U)

Define Documentation

#define UART_CR1_DEDT_ADDRESS_LSB_POS ( 16U)

UART Driver Enable de-assertion time LSB position in CR1 register

Definition at line 680 of file stm32f3xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

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STM32F373xC HAL User Manual: UART Interruptions Flag Mask

Defines
UART Interruptions Flag Mask
UART Exported Constants

Defines

#define UART_IT_MASK (0x001FU)

Define Documentation

#define UART_IT_MASK (0x001FU)

UART interruptions flags mask

Definition at line 688 of file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART polling-based communications time-out value

Defines
UART polling-based communications time-out value
UART Exported Constants

Defines

#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF

Define Documentation

#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF

UART polling-based communications time-out value

Definition at line 696 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig(), and UART_CheckIdleState().

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STM32F373xC HAL User Manual: UART Exported Macros

Defines
UART Exported Macros
UART

Defines

#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle states.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)
Flush the UART Data registers.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
Clear the UART IDLE pending flag.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified UART flag is set or not.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
Check whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified UART interrupt source is enabled or not.
#define | __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified UART ISR flag, in setting the proper ICR register flag.
#define | __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
Set a specific UART request flag.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the UART one bit sample method.
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the UART one bit sample method.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control.

Define Documentation

#define __HAL_UART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)

Clear the UART FE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 758 of file stm32f3xx_hal_uart.h.

#define __HAL_UART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified UART pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • UART_CLEAR_PEF Parity Error Clear Flag
  • UART_CLEAR_FEF Framing Error Clear Flag
  • UART_CLEAR_NEF Noise detected Clear Flag
  • UART_CLEAR_OREF Overrun Error Clear Flag
  • UART_CLEAR_IDLEF IDLE line detected Clear Flag
  • UART_CLEAR_TCF Transmission Complete Clear Flag
  • UART_CLEAR_LBDF LIN Break Detection Clear Flag (not available on all devices)
  • UART_CLEAR_CTSF CTS Interrupt Clear Flag
  • UART_CLEAR_RTOF Receiver Time Out Clear Flag
  • UART_CLEAR_EOBF End Of Block Clear Flag (not available on all devices)
  • UART_CLEAR_CMF Character Match Clear Flag
  • UART_CLEAR_WUF Wake Up from stop mode Clear Flag (not available on all devices)
Return values:
None

Definition at line 746 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAResume(), HAL_UART_Transmit_DMA(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define __HAL_UART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)

Clear the UART IDLE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 776 of file stm32f3xx_hal_uart.h.

#define __HAL_UART_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified UART ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the UART Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • UART_CLEAR_PEF Parity Error Clear Flag
  • UART_CLEAR_FEF Framing Error Clear Flag
  • UART_CLEAR_NEF Noise detected Clear Flag
  • UART_CLEAR_OREF Overrun Error Clear Flag
  • UART_CLEAR_IDLEF IDLE line detected Clear Flag
  • UART_CLEAR_TCF Transmission Complete Clear Flag
  • UART_CLEAR_LBDF LIN Break Detection Clear Flag
  • UART_CLEAR_CTSF CTS Interrupt Clear Flag
  • UART_CLEAR_RTOF Receiver Time Out Clear Flag
  • UART_CLEAR_EOBF End Of Block Clear Flag
  • UART_CLEAR_CMF Character Match Clear Flag
  • UART_CLEAR_WUF Wake Up from stop mode Clear Flag
Return values:
None

Definition at line 906 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define __HAL_UART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)

Clear the UART NE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 764 of file stm32f3xx_hal_uart.h.

#define __HAL_UART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)

Clear the UART ORE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 770 of file stm32f3xx_hal_uart.h.

#define __HAL_UART_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)

Clear the UART PE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 752 of file stm32f3xx_hal_uart.h.

#define __HAL_UART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 943 of file stm32f3xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_DeInit(), HAL_UART_Init(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define __HAL_UART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))

Disable the specified UART interrupt.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt source to disable. This parameter can be one of the following values:
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
Return values:
None

Definition at line 844 of file stm32f3xx_hal_uart.h.

#define __HAL_UART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 937 of file stm32f3xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Init(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define __HAL_UART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))

Enable the specified UART interrupt.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt source to enable. This parameter can be one of the following values:
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
Return values:
None

Definition at line 823 of file stm32f3xx_hal_uart.h.

#define __HAL_UART_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                \
      SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
      SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
    }  while(0U)

Flush the UART Data registers.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 722 of file stm32f3xx_hal_uart.h.

#define __HAL_UART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified UART flag is set or not.

Parameters:
__HANDLE__ specifies the UART Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • UART_FLAG_REACK Receive enable acknowledge flag
  • UART_FLAG_TEACK Transmit enable acknowledge flag
  • UART_FLAG_WUF Wake up from stop mode flag
  • UART_FLAG_RWU Receiver wake up flag
  • UART_FLAG_SBKF Send Break flag
  • UART_FLAG_CMF Character match flag
  • UART_FLAG_BUSY Busy flag
  • UART_FLAG_ABRF Auto Baud rate detection flag
  • UART_FLAG_ABRE Auto Baud rate detection error flag
  • UART_FLAG_EOBF End of block flag
  • UART_FLAG_RTOF Receiver timeout flag
  • UART_FLAG_CTS CTS Change flag (not available for UART4 and UART5)
  • UART_FLAG_LBDF LIN Break detection flag
  • UART_FLAG_TXE Transmit data register empty flag
  • UART_FLAG_TC Transmission Complete flag
  • UART_FLAG_RXNE Receive data register not empty flag
  • UART_FLAG_IDLE Idle Line detection flag
  • UART_FLAG_ORE Overrun Error flag
  • UART_FLAG_NE Noise Error flag
  • UART_FLAG_FE Framing Error flag
  • UART_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 805 of file stm32f3xx_hal_uart.h.

Referenced by UART_WaitOnFlagUntilTimeout().

#define __HAL_UART_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))

Check whether the specified UART interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the UART Handle.
__IT__ specifies the UART interrupt to check. This parameter can be one of the following values:
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt (not available for UART4 and UART5)
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_ORE Overrun Error interrupt
  • UART_IT_NE Noise Error interrupt
  • UART_IT_FE Framing Error interrupt
  • UART_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 866 of file stm32f3xx_hal_uart.h.

#define __HAL_UART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & UART_IT_MASK)))

Check whether the specified UART interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the UART Handle.
__IT__ specifies the UART interrupt source to check. This parameter can be one of the following values:
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt (not available for UART4 and UART5)
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
  • UART_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 884 of file stm32f3xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_DISABLE ( __HANDLE__ )
Value:
do{                                                       \
    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
  } while(0U)

Disable CTS flow control.

Note:
This macro allows to disable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 975 of file stm32f3xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_ENABLE ( __HANDLE__ )
Value:
do{                                                      \
    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
  } while(0U)

Enable CTS flow control.

Note:
This macro allows to enable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 957 of file stm32f3xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_DISABLE ( __HANDLE__ )
Value:
do{                                                      \
    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
  } while(0U)

Disable RTS flow control.

Note:
This macro allows to disable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1011 of file stm32f3xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_ENABLE ( __HANDLE__ )
Value:
do{                                                     \
    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
  } while(0U)

Enable RTS flow control.

Note:
This macro allows to enable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 993 of file stm32f3xx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the UART one bit sample method.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 931 of file stm32f3xx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the UART one bit sample method.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 925 of file stm32f3xx_hal_uart.h.

#define __HAL_UART_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
                                                     } while(0U)

Reset UART handle states.

Parameters:
__HANDLE__ UART handle.
Return values:
None

Definition at line 714 of file stm32f3xx_hal_uart.h.

#define __HAL_UART_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))

Set a specific UART request flag.

Parameters:
__HANDLE__ specifies the UART Handle.
__REQ__ specifies the request flag to set This parameter can be one of the following values:
  • UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
  • UART_SENDBREAK_REQUEST Send Break Request
  • UART_MUTE_MODE_REQUEST Mute Mode Request
  • UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 919 of file stm32f3xx_hal_uart.h.

Referenced by HAL_MultiProcessor_EnterMuteMode(), and UART_Receive_IT().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Private Macros

Defines
UART Private Macros
UART

Defines

#define | UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001U)
Check UART Baud rate.
#define | IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART assertion time.
#define | IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART deassertion time.
#define | IS_UART_STOPBITS(__STOPBITS__)
Ensure that UART frame number of stop bits is valid.
#define | IS_UART_PARITY(__PARITY__)
Ensure that UART frame parity is valid.
#define | IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)
Ensure that UART hardware flow control is valid.
#define | IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that UART communication mode is valid.
#define | IS_UART_STATE(__STATE__)
Ensure that UART state is valid.
#define | IS_UART_OVERSAMPLING(__SAMPLING__)
Ensure that UART oversampling is valid.
#define | IS_UART_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that UART frame sampling is valid.
#define | IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__)
Ensure that Address Length detection parameter is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)
Ensure that UART auto Baud rate detection mode is valid.
#define | IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)
Ensure that UART receiver timeout setting is valid.
#define | IS_UART_LIN(__LIN__)
Ensure that UART LIN state is valid.
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__)
Ensure that UART LIN break detection length is valid.
#define | IS_UART_DMA_TX(__DMATX__)
Ensure that UART DMA TX state is valid.
#define | IS_UART_DMA_RX(__DMARX__)
Ensure that UART DMA RX state is valid.
#define | IS_UART_HALF_DUPLEX(__HDSEL__)
Ensure that UART half-duplex state is valid.
#define | IS_UART_WAKEUPMETHOD(__WAKEUP__)
Ensure that UART wake-up method is valid.
#define | IS_UART_ADVFEATURE_INIT(__INIT__)
Ensure that UART advanced features initialization is valid.
#define | IS_UART_ADVFEATURE_TXINV(__TXINV__)
Ensure that UART frame TX inversion setting is valid.
#define | IS_UART_ADVFEATURE_RXINV(__RXINV__)
Ensure that UART frame RX inversion setting is valid.
#define | IS_UART_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that UART frame data inversion setting is valid.
#define | IS_UART_ADVFEATURE_SWAP(__SWAP__)
Ensure that UART frame RX/TX pins swap setting is valid.
#define | IS_UART_OVERRUN(__OVERRUN__)
Ensure that UART frame overrun setting is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)
Ensure that UART auto Baud rate state is valid.
#define | IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that UART DMA enabling or disabling on error setting is valid.
#define | IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that UART frame MSB first setting is valid.
#define | IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__)
Ensure that UART stop mode state is valid.
#define | IS_UART_MUTE_MODE(__MUTE__)
Ensure that UART mute mode state is valid.
#define | IS_UART_WAKEUP_SELECTION(__WAKE__)
Ensure that UART wake-up selection is valid.
#define | IS_UART_DE_POLARITY(__POLARITY__)
Ensure that UART driver enable polarity is valid.
#define | IS_UART_REQUEST_PARAMETER(__PARAM__)
Ensure that UART request parameter is valid.

Define Documentation

#define IS_UART_ADDRESSLENGTH_DETECT ( __ADDRESS__ )
Value:
(((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))

Ensure that Address Length detection parameter is valid.

Parameters:
__ADDRESS__ UART Adress length value.
Return values:
SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)

Definition at line 1125 of file stm32f3xx_hal_uart.h.

Referenced by HAL_MultiProcessorEx_AddressLength_Set(), and UART_Wakeup_AddressConfig().

#define IS_UART_ADVFEATURE_AUTOBAUDRATE ( __AUTOBAUDRATE__ )
Value:
(((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
                                                            ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))

Ensure that UART auto Baud rate state is valid.

Parameters:
__AUTOBAUDRATE__ UART auto Baud rate state.
Return values:
SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)

Definition at line 1254 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE ( __MODE__ )
Value:
(((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))

Ensure that UART auto Baud rate detection mode is valid.

Parameters:
__MODE__ UART auto Baud rate detection mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1133 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_DATAINV ( __DATAINV__ )
Value:
(((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))

Ensure that UART frame data inversion setting is valid.

Parameters:
__DATAINV__ UART frame data inversion setting.
Return values:
SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)

Definition at line 1230 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_DMAONRXERROR ( __DMA__ )
Value:
(((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))

Ensure that UART DMA enabling or disabling on error setting is valid.

Parameters:
__DMA__ UART DMA enabling or disabling on error setting.
Return values:
SET (__DMA__ is valid) or RESET (__DMA__ is invalid)

Definition at line 1262 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_INIT ( __INIT__ )
Value:
((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
                                                            UART_ADVFEATURE_TXINVERT_INIT          | \
                                                            UART_ADVFEATURE_RXINVERT_INIT          | \
                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \
                                                            UART_ADVFEATURE_SWAP_INIT              | \
                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
                                                            UART_ADVFEATURE_MSBFIRST_INIT))

Ensure that UART advanced features initialization is valid.

Parameters:
__INIT__ UART advanced features initialization.
Return values:
SET (__INIT__ is valid) or RESET (__INIT__ is invalid)

Definition at line 1199 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_MSBFIRST ( __MSBFIRST__ )
Value:
(((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))

Ensure that UART frame MSB first setting is valid.

Parameters:
__MSBFIRST__ UART frame MSB first setting.
Return values:
SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)

Definition at line 1270 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_RXINV ( __RXINV__ )
Value:
(((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))

Ensure that UART frame RX inversion setting is valid.

Parameters:
__RXINV__ UART frame RX inversion setting.
Return values:
SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)

Definition at line 1222 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_STOPMODE ( __STOPMODE__ )
Value:
(((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))

Ensure that UART stop mode state is valid.

Parameters:
__STOPMODE__ UART stop mode state.
Return values:
SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)

Definition at line 1278 of file stm32f3xx_hal_uart.h.

#define IS_UART_ADVFEATURE_SWAP ( __SWAP__ )
Value:
(((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))

Ensure that UART frame RX/TX pins swap setting is valid.

Parameters:
__SWAP__ UART frame RX/TX pins swap setting.
Return values:
SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)

Definition at line 1238 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_TXINV ( __TXINV__ )
Value:
(((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))

Ensure that UART frame TX inversion setting is valid.

Parameters:
__TXINV__ UART frame TX inversion setting.
Return values:
SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)

Definition at line 1214 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ASSERTIONTIME ( __TIME__ ) ((__TIME__) <= 0x1FU)

Check UART assertion time.

Parameters:
__TIME__ 5-bit value assertion time.
Return values:
Test result (TRUE or FALSE).

Definition at line 1051 of file stm32f3xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 9000001U)

Check UART Baud rate.

Parameters:
__BAUDRATE__ Baudrate specified by the user. The maximum Baud Rate is derived from the maximum clock on F3 (i.e. 72 MHz) divided by the smallest oversampling used on the USART (i.e. 8)
Return values:
SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)

Definition at line 1045 of file stm32f3xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_DE_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))

Ensure that UART driver enable polarity is valid.

Parameters:
__POLARITY__ UART driver enable polarity.
Return values:
SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)

Definition at line 1303 of file stm32f3xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_DEASSERTIONTIME ( __TIME__ ) ((__TIME__) <= 0x1FU)

Check UART deassertion time.

Parameters:
__TIME__ 5-bit value deassertion time.
Return values:
Test result (TRUE or FALSE).

Definition at line 1057 of file stm32f3xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_DMA_RX ( __DMARX__ )
Value:
(((__DMARX__) == UART_DMA_RX_DISABLE) || \
                                       ((__DMARX__) == UART_DMA_RX_ENABLE))

Ensure that UART DMA RX state is valid.

Parameters:
__DMARX__ UART DMA RX state.
Return values:
SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)

Definition at line 1175 of file stm32f3xx_hal_uart.h.

#define IS_UART_DMA_TX ( __DMATX__ )
Value:
(((__DMATX__) == UART_DMA_TX_DISABLE) || \
                                       ((__DMATX__) == UART_DMA_TX_ENABLE))

Ensure that UART DMA TX state is valid.

Parameters:
__DMATX__ UART DMA TX state.
Return values:
SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)

Definition at line 1167 of file stm32f3xx_hal_uart.h.

#define IS_UART_HALF_DUPLEX ( __HDSEL__ )
Value:
(((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))

Ensure that UART half-duplex state is valid.

Parameters:
__HDSEL__ UART half-duplex state.
Return values:
SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)

Definition at line 1183 of file stm32f3xx_hal_uart.h.

#define IS_UART_HARDWARE_FLOW_CONTROL ( __CONTROL__ )
Value:
(((__CONTROL__) == UART_HWCONTROL_NONE) || \
                                    ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
                                    ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
                                    ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))

Ensure that UART hardware flow control is valid.

Parameters:
__CONTROL__ UART hardware flow control.
Return values:
SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)

Definition at line 1083 of file stm32f3xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_LIN ( __LIN__ )
Value:
(((__LIN__) == UART_LIN_DISABLE) || \
                                         ((__LIN__) == UART_LIN_ENABLE))

Ensure that UART LIN state is valid.

Parameters:
__LIN__ UART LIN state.
Return values:
SET (__LIN__ is valid) or RESET (__LIN__ is invalid)

Definition at line 1151 of file stm32f3xx_hal_uart.h.

#define IS_UART_LIN_BREAK_DETECT_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))

Ensure that UART LIN break detection length is valid.

Parameters:
__LENGTH__ UART LIN break detection length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 1159 of file stm32f3xx_hal_uart.h.

Referenced by HAL_LIN_Init().

#define IS_UART_MODE ( __MODE__ ) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that UART communication mode is valid.

Parameters:
__MODE__ UART communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1094 of file stm32f3xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_MUTE_MODE ( __MUTE__ )
Value:
(((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))

Ensure that UART mute mode state is valid.

Parameters:
__MUTE__ UART mute mode state.
Return values:
SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)

Definition at line 1286 of file stm32f3xx_hal_uart.h.

#define IS_UART_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))

Ensure that UART frame sampling is valid.

Parameters:
__ONEBIT__ UART frame sampling.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 1117 of file stm32f3xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_OVERRUN ( __OVERRUN__ )
Value:
(((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))

Ensure that UART frame overrun setting is valid.

Parameters:
__OVERRUN__ UART frame overrun setting.
Return values:
SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)

Definition at line 1246 of file stm32f3xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_OVERSAMPLING ( __SAMPLING__ )
Value:
(((__SAMPLING__) == UART_OVERSAMPLING_16) || \
                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))

Ensure that UART oversampling is valid.

Parameters:
__SAMPLING__ UART oversampling.
Return values:
SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)

Definition at line 1109 of file stm32f3xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == UART_PARITY_NONE) || \
                                    ((__PARITY__) == UART_PARITY_EVEN) || \
                                    ((__PARITY__) == UART_PARITY_ODD))

Ensure that UART frame parity is valid.

Parameters:
__PARITY__ UART frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 1074 of file stm32f3xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_RECEIVER_TIMEOUT ( __TIMEOUT__ )
Value:
(((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
                                               ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))

Ensure that UART receiver timeout setting is valid.

Parameters:
__TIMEOUT__ UART receiver timeout setting.
Return values:
SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)

Definition at line 1143 of file stm32f3xx_hal_uart.h.

#define IS_UART_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))

Ensure that UART request parameter is valid.

Parameters:
__PARAM__ UART request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 1311 of file stm32f3xx_hal_uart.h.

#define IS_UART_STATE ( __STATE__ )
Value:
(((__STATE__) == UART_STATE_DISABLE) || \
                                  ((__STATE__) == UART_STATE_ENABLE))

Ensure that UART state is valid.

Parameters:
__STATE__ UART state.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 1101 of file stm32f3xx_hal_uart.h.

#define IS_UART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == UART_STOPBITS_0_5) || \
                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \
                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \
                                        ((__STOPBITS__) == UART_STOPBITS_2))

Ensure that UART frame number of stop bits is valid.

Parameters:
__STOPBITS__ UART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 1064 of file stm32f3xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_WAKEUP_SELECTION ( __WAKE__ )
Value:
(((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))

Ensure that UART wake-up selection is valid.

Parameters:
__WAKE__ UART wake-up selection.
Return values:
SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)

Definition at line 1294 of file stm32f3xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define IS_UART_WAKEUPMETHOD ( __WAKEUP__ )
Value:
(((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))

Ensure that UART wake-up method is valid.

Parameters:
__WAKEUP__ UART wake-up method .
Return values:
SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)

Definition at line 1191 of file stm32f3xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define UART_DIV_SAMPLING16 | ( | __PCLK__,
 |  | __BAUD__
 | ) | (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 16-bit oversampling mode.

Parameters:
__PCLK__ | UART clock.
__BAUD__ | Baud rate set by the user.
Return values:
Division result

Definition at line 1037 of file stm32f3xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_DIV_SAMPLING8 | ( | __PCLK__,
 |  | __BAUD__
 | ) | ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 8-bit oversampling mode.

Parameters:
__PCLK__ | UART clock.
__BAUD__ | Baud rate set by the user.
Return values:
Division result

Definition at line 1030 of file stm32f3xx_hal_uart.h.

Referenced by UART_SetConfig().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Extended Initialization and de-initialization functions

Functions
Extended Initialization and de-initialization functions
UARTEx Exported Functions

Extended Initialization and Configuration Functions. More...

Functions

HAL_StatusTypeDef HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Detailed Description

Extended Initialization and Configuration Functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ==============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in asynchronous mode.
      (+) For the asynchronous mode the parameters below can be configured:
        (++) Baud Rate
        (++) Word Length (Fixed to 8-bits only for LIN mode)
        (++) Stop Bit
        (++) Parity
        (++) Hardware flow control
        (++) Receiver/transmitter modes
        (++) Over Sampling Method
        (++) One-Bit Sampling Method
      (+) For the asynchronous mode, the following advanced features can be configured as well:
        (++) TX and/or RX pin level inversion
        (++) data logical level inversion
        (++) RX and TX pins swap
        (++) RX overrun detection disabling
        (++) DMA disabling on RX error
        (++) MSB first on communication line
        (++) auto Baud rate detection
    [..]
    The HAL_RS485Ex_Init() API follows respectively the UART RS485 mode
    configuration procedures (details for the procedures are available in reference manual).

Function Documentation

HAL_StatusTypeDef HAL_RS485Ex_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Polarity,
 |  | uint32_t | AssertionTime,
 |  | uint32_t | DeassertionTime
 | ) |  |

Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart | UART handle.
Polarity select the driver enable polarity. This parameter can be one of the following values:
  • UART_DE_POLARITY_HIGH DE signal is active high
  • UART_DE_POLARITY_LOW DE signal is active low
AssertionTime | Driver Enable assertion time: 5-bit value defining the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate)
DeassertionTime | Driver Enable deassertion time: 5-bit value defining the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate).
Return values:
HAL status

Definition at line 170 of file stm32f3xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Instance, IS_UART_ASSERTIONTIME, IS_UART_DE_POLARITY, IS_UART_DEASSERTIONTIME, UART_HandleTypeDef::Lock, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_CR1_DEAT_ADDRESS_LSB_POS, UART_CR1_DEDT_ADDRESS_LSB_POS, and UART_SetConfig().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Extended IO operation function

Functions
Extended IO operation function
UARTEx Exported Functions

Extended UART Interrupt handling function. More...

Functions

__weak void HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.

Detailed Description

Extended UART Interrupt handling function.

 ===============================================================================
                      ##### IO operation function #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to manage the UART interrupts
    and to handle Wake up interrupt call-back.

    (#) Callback provided in No_Blocking mode:
        (++) HAL_UARTEx_WakeupCallback()

Function Documentation

__weak void HAL_UARTEx_WakeupCallback ( UART_HandleTypeDef * huart )

UART wakeup from Stop mode callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 263 of file stm32f3xx_hal_uart_ex.c.

Referenced by HAL_UART_IRQHandler().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
UARTEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides extended functions allowing to control the UART.
     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API sets Wakeup from Stop mode interrupt flag selection
     (+) HAL_UARTEx_EnableStopMode() API allows the UART to wake up the MCU from Stop mode as
         long as UART clock is HSI or LSE
     (+) HAL_UARTEx_DisableStopMode() API disables the above feature
     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
         detection length to more than 4 bits for multiprocessor address mark wake up.

Function Documentation

HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | AddressLength
 | ) |  |

By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).

Note:
Addresses detection lengths are: 6-bit address detection in 7-bit data mode, 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
Parameters:
huart UART handle.
AddressLength this parameter can be one of the following values:
  • UART_ADDRESS_DETECT_4B 4-bit long address
  • UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
Return values:
HAL status

Definition at line 423 of file stm32f3xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, UART_HandleTypeDef::Instance, IS_UART_ADDRESSLENGTH_DETECT, and UART_CheckIdleState().

HAL_StatusTypeDef HAL_UARTEx_DisableStopMode ( UART_HandleTypeDef * huart )

Disable UART Stop Mode.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 389 of file stm32f3xx_hal_uart_ex.c.

References assert_param, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_UARTEx_EnableStopMode ( UART_HandleTypeDef * huart )

Enable UART Stop Mode.

Note:
The UART is able to wake up the MCU from Stop mode as long as UART clock is HSI or LSE.
Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 363 of file stm32f3xx_hal_uart_ex.c.

References assert_param, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig | ( | UART_HandleTypeDef * | huart,
 |  | UART_WakeUpTypeDef | WakeUpSelection
 | ) |  |

Set Wakeup from Stop mode interrupt flag selection.

Parameters:
huart UART handle.
WakeUpSelection address match, Start Bit detection or RXNE bit status. This parameter can be one of the following values:
  • UART_WAKEUP_ON_ADDRESS
  • UART_WAKEUP_ON_STARTBIT
  • UART_WAKEUP_ON_READDATA_NONEMPTY
Return values:
HAL status

Definition at line 307 of file stm32f3xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, HAL_UART_TIMEOUT_VALUE, UART_HandleTypeDef::Instance, IS_UART_WAKEUP_SELECTION, UART_WaitOnFlagUntilTimeout(), UART_Wakeup_AddressConfig(), UART_WAKEUP_ON_ADDRESS, and UART_WakeUpTypeDef::WakeUpEvent.

void HAL_UARTEx_WakeupCallback ( UART_HandleTypeDef * huart )

UART wakeup from Stop mode callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 263 of file stm32f3xx_hal_uart_ex.c.

Referenced by HAL_UART_IRQHandler().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UARTEx Word Length

Defines
UARTEx Word Length
UARTEx Exported Constants

Defines

#define | UART_WORDLENGTH_8B (0x00000000U)
#define | UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Define Documentation

#define UART_WORDLENGTH_8B (0x00000000U)

8-bit long UART frame

Definition at line 71 of file stm32f3xx_hal_uart_ex.h.

Referenced by HAL_LIN_Init().

#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

9-bit long UART frame

Definition at line 72 of file stm32f3xx_hal_uart_ex.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), and UART_Transmit_IT().

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UARTEx Private Macros

Defines
UARTEx Private Macros
UARTEx

Defines

#define | UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the UART clock source.
#define | UART_MASK_COMPUTATION(__HANDLE__)
Compute the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_UART_WORD_LENGTH(__LENGTH__)
Ensure that UART frame length is valid.

Define Documentation

#define IS_UART_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == UART_WORDLENGTH_8B) || \
                                         ((__LENGTH__) == UART_WORDLENGTH_9B))

Ensure that UART frame length is valid.

Parameters:
__LENGTH__ UART frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 449 of file stm32f3xx_hal_uart_ex.h.

Referenced by UART_SetConfig().

#define UART_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the UART clock source.

Parameters:
__HANDLE__ | specifies the UART Handle.
__CLOCKSOURCE__ | output variable.
Return values:
UART clocking source, written in __CLOCKSOURCE__.

Definition at line 285 of file stm32f3xx_hal_uart_ex.h.

Referenced by UART_SetConfig().

#define UART_MASK_COMPUTATION ( __HANDLE__ )
Value:
do {                                                                \
  if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)            \
  {                                                                   \
     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
     {                                                                \
        (__HANDLE__)->Mask = 0x01FFU ;                                \
     }                                                                \
     else                                                             \
     {                                                                \
        (__HANDLE__)->Mask = 0x00FFU ;                                \
     }                                                                \
  }                                                                   \
  else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)       \
  {                                                                   \
     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
     {                                                                \
        (__HANDLE__)->Mask = 0x00FFU ;                                \
     }                                                                \
     else                                                             \
     {                                                                \
        (__HANDLE__)->Mask = 0x007FU ;                                \
     }                                                                \
  }                                                                   \
} while(0U)

Compute the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Note:
If PCE = 1, the parity bit is not included in the data extracted by the reception API(). This masking operation is not carried out in the case of DMA transfers.
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None,the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 408 of file stm32f3xx_hal_uart_ex.h.

Referenced by HAL_UART_Receive(), and HAL_UART_Receive_IT().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Private Constants

Defines
USART Private Constants
USART

Defines

#define | USART_DUMMY_DATA ((uint16_t) 0xFFFFU)
#define | USART_TEACK_REACK_TIMEOUT ( 1000U)
#define | USART_CR1_FIELDS
#define | USART_CR2_FIELDS

Define Documentation

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
                                              USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8))

USART CR1 fields of parameters set by USART_SetConfig API

Definition at line 165 of file stm32f3xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_CR2_FIELDS
Value:
((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
                                              USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP))

USART CR2 fields of parameters set by USART_SetConfig API

Definition at line 167 of file stm32f3xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_DUMMY_DATA ((uint16_t) 0xFFFFU)

USART transmitted dummy data

Definition at line 163 of file stm32f3xx_hal_usart.c.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), and USART_Receive_IT().

#define USART_TEACK_REACK_TIMEOUT ( 1000U)

USART TX or RX enable acknowledge time-out value

Definition at line 164 of file stm32f3xx_hal_usart.c.

Referenced by USART_CheckIdleState().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
USART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USART
    in asynchronous and in synchronous modes.
      (+) For the asynchronous mode only these parameters can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity
        (++) USART polarity
        (++) USART phase
        (++) USART LastBit
        (++) Receiver/transmitter modes

    [..]
    The HAL_USART_Init() function follows the USART  synchronous configuration
    procedure (details for the procedure are available in reference manual).

Function Documentation

HAL_StatusTypeDef HAL_USART_DeInit ( USART_HandleTypeDef * husart )

DeInitialize the USART peripheral.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 325 of file stm32f3xx_hal_usart.c.

References assert_param, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_MspDeInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_Init ( USART_HandleTypeDef * husart )

Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 276 of file stm32f3xx_hal_usart.c.

References __HAL_USART_DISABLE, __HAL_USART_ENABLE, assert_param, HAL_USART_MspInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Lock, USART_HandleTypeDef::State, USART_CheckIdleState(), and USART_SetConfig().

void HAL_USART_MspDeInit ( USART_HandleTypeDef * husart )

DeInitialize the USART MSP.

Parameters:
husart USART handle.
Return values:
None

Definition at line 374 of file stm32f3xx_hal_usart.c.

Referenced by HAL_USART_DeInit().

void HAL_USART_MspInit ( USART_HandleTypeDef * husart )

Initialize the USART MSP.

Parameters:
husart USART handle.
Return values:
None

Definition at line 359 of file stm32f3xx_hal_usart.c.

Referenced by HAL_USART_Init().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IO operation functions

Functions
IO operation functions
USART Exported Functions

USART Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.

Detailed Description

USART Transmit and Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..] This subsection provides a set of functions allowing to manage the USART synchronous
    data transfers.

    [..] The USART supports master mode only: it cannot receive or send data related to an input
         clock (SCLK is always an output).

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode: The communication is performed using Interrupts
           or DMA, These APIs return the HAL status.
           The end of the data processing will be indicated through the
           dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected

    (#) Blocking mode APIs are :
        (++) HAL_USART_Transmit() in simplex mode
        (++) HAL_USART_Receive() in full duplex receive only
        (++) HAL_USART_TransmitReceive() in full duplex mode

    (#) No-Blocking mode APIs with Interrupt are :
        (++) HAL_USART_Transmit_IT() in simplex mode
        (++) HAL_USART_Receive_IT() in full duplex receive only
        (++) HAL_USART_TransmitReceive_IT()in full duplex mode
        (++) HAL_USART_IRQHandler()

    (#) No-Blocking mode APIs with DMA are :
        (++) HAL_USART_Transmit_DMA() in simplex mode
        (++) HAL_USART_Receive_DMA() in full duplex receive only
        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
        (++) HAL_USART_DMAPause()
        (++) HAL_USART_DMAResume()
        (++) HAL_USART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in No-Blocking mode:
        (++) HAL_USART_TxCpltCallback()
        (++) HAL_USART_RxCpltCallback()
        (++) HAL_USART_TxHalfCpltCallback()
        (++) HAL_USART_RxHalfCpltCallback()
        (++) HAL_USART_ErrorCallback()
        (++) HAL_USART_TxRxCpltCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (++) HAL_USART_Abort()
        (++) HAL_USART_Abort_IT()

    (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
        (++) HAL_USART_AbortCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
             to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
             and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
             If user wants to abort it, Abort services should be called by user.
        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
             This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
             Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_USART_Abort ( USART_HandleTypeDef * husart )

Abort ongoing transfers (blocking mode).

Parameters:
husart USART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable USART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1229 of file stm32f3xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_USART_Abort_IT ( USART_HandleTypeDef * husart )

Abort ongoing transfers (Interrupt mode).

Parameters:
husart USART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable USART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1297 of file stm32f3xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_USART_AbortCpltCallback ( USART_HandleTypeDef * husart )

USART Abort Complete callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 1676 of file stm32f3xx_hal_usart.c.

Referenced by HAL_USART_Abort_IT(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

HAL_StatusTypeDef HAL_USART_DMAPause ( USART_HandleTypeDef * husart )

Pause the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1107 of file stm32f3xx_hal_usart.c.

References HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_DMAResume ( USART_HandleTypeDef * husart )

Resume the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1148 of file stm32f3xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, USART_HandleTypeDef::Instance, USART_HandleTypeDef::State, and USART_CLEAR_OREF.

HAL_StatusTypeDef HAL_USART_DMAStop ( USART_HandleTypeDef * husart )

Stop the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1186 of file stm32f3xx_hal_usart.c.

References HAL_DMA_Abort(), HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::State, and USART_EndTransfer().

void HAL_USART_ErrorCallback ( USART_HandleTypeDef * husart )

USART error callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 1661 of file stm32f3xx_hal_usart.c.

Referenced by HAL_USART_IRQHandler(), USART_DMAAbortOnError(), and USART_DMAError().

void HAL_USART_IRQHandler ( USART_HandleTypeDef * husart )

Handle USART interrupt request.

Parameters:
husart USART handle.
Return values:
None

Definition at line 1412 of file stm32f3xx_hal_usart.c.

References __HAL_USART_CLEAR_IT, USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_USART_ERROR_FE, HAL_USART_ERROR_NE, HAL_USART_ERROR_NONE, HAL_USART_ERROR_ORE, HAL_USART_ERROR_PE, HAL_USART_ErrorCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::State, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_DMAAbortOnError(), USART_EndTransfer(), USART_EndTransmit_IT(), USART_Receive_IT(), USART_Transmit_IT(), USART_TransmitReceive_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_USART_Receive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
To receive synchronous data, dummy data are simultaneously transmitted.
Parameters:
husart | USART handle.
pRxData | Pointer to data buffer.
Size | Amount of data to be received.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 543 of file stm32f3xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_DUMMY_DATA, USART_FLAG_RXNE, USART_FLAG_TC, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Receive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
husart | USART handle.
pRxData | pointer to data buffer.
Size | amount of data to be received.
Note:
When the USART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
The USART DMA transmit channel must be configured in order to generate the clock for the slave.
This function starts a DMA transfer in interrupt mode meaning that DMA half transfer complete, DMA transfer complete and DMA transfer error interrupts are enabled
Return values:
HAL status

Definition at line 944 of file stm32f3xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferSize, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Receive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
To receive synchronous data, dummy data are simultaneously transmitted.
Parameters:
husart | USART handle.
pRxData | pointer to data buffer.
Size | amount of data to be received.
Return values:
HAL status

Definition at line 767 of file stm32f3xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_DUMMY_DATA, USART_MASK_COMPUTATION, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

void HAL_USART_RxCpltCallback ( USART_HandleTypeDef * husart )

Rx Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 1616 of file stm32f3xx_hal_usart.c.

Referenced by USART_DMAReceiveCplt(), and USART_Receive_IT().

void HAL_USART_RxHalfCpltCallback ( USART_HandleTypeDef * husart )

Rx Half Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 1631 of file stm32f3xx_hal_usart.c.

Referenced by USART_DMARxHalfCplt().

HAL_StatusTypeDef HAL_USART_Transmit | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Simplex send an amount of data in blocking mode.

Parameters:
husart | USART handle.
pTxData | Pointer to data buffer.
Size | Amount of data to be sent.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 471 of file stm32f3xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_FLAG_TC, USART_PARITY_NONE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Transmit_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
husart | USART handle.
pTxData | pointer to data buffer.
Size | amount of data to be sent.
Note:
This function starts a DMA transfer in interrupt mode meaning that DMA half transfer complete, DMA transfer complete and DMA transfer error interrupts are enabled
Return values:
HAL status

Definition at line 879 of file stm32f3xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_CLEAR_TCF, USART_DMAError(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Transmit_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Parameters:
husart | USART handle.
pTxData | pointer to data buffer.
Size | amount of data to be sent.
Return values:
HAL status

Definition at line 720 of file stm32f3xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, and USART_IT_TXE.

HAL_StatusTypeDef HAL_USART_TransmitReceive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Full-Duplex Send and Receive an amount of data in blocking mode.

Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer.
pRxData | pointer to RX data buffer.
Size | amount of data to be sent (same amount to be received).
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 628 of file stm32f3xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_FLAG_RXNE, USART_FLAG_TC, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Transmit Receive an amount of data in non-blocking mode.

Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer.
pRxData | pointer to RX data buffer.
Size | amount of data to be received/sent.
Note:
When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
This function starts a 2 DMA transfers in interrupt mode meaning that DMA half transfer complete, DMA transfer complete and DMA transfer error interrupts are enabled
Return values:
HAL status

Definition at line 1026 of file stm32f3xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferSize, USART_CLEAR_TCF, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_TransmitReceive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Send and Receive an amount of data in interrupt mode.

Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer.
pRxData | pointer to RX data buffer.
Size | amount of data to be sent (same amount to be received).
Return values:
HAL status

Definition at line 823 of file stm32f3xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, and USART_MASK_COMPUTATION.

void HAL_USART_TxCpltCallback ( USART_HandleTypeDef * husart )

Tx Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 1586 of file stm32f3xx_hal_usart.c.

Referenced by USART_DMATransmitCplt(), and USART_EndTransmit_IT().

void HAL_USART_TxHalfCpltCallback ( USART_HandleTypeDef * husart )

Tx Half Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 1601 of file stm32f3xx_hal_usart.c.

Referenced by USART_DMATxHalfCplt().

void HAL_USART_TxRxCpltCallback ( USART_HandleTypeDef * husart )

Tx/Rx Transfers completed callback for the non-blocking process.

Parameters:
husart USART handle.
Return values:
None

Definition at line 1646 of file stm32f3xx_hal_usart.c.

Referenced by USART_DMAReceiveCplt(), and USART_TransmitReceive_IT().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
USART Exported Functions

USART Peripheral State and Error functions. More...

Functions

HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART Peripheral State and Error functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Return the USART handle state
      (+) Return the USART handle error code

Function Documentation

uint32_t HAL_USART_GetError ( USART_HandleTypeDef * husart )

Return the USART error code.

Parameters:
husart pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART.
Return values:
USART handle Error Code

Definition at line 1724 of file stm32f3xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode.

HAL_USART_StateTypeDef HAL_USART_GetState ( USART_HandleTypeDef * husart )

Return the USART handle state.

Parameters:
husart pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART.
Return values:
USART handle state

Definition at line 1713 of file stm32f3xx_hal_usart.c.

References USART_HandleTypeDef::State.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Private Functions

Functions
USART Private Functions
USART

USART Private functions. More...

Functions

static void | USART_EndTransfer (USART_HandleTypeDef *husart)
End ongoing transfer on USART peripheral (following error detection or Transfer completion).
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static void | USART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | USART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | USART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle USART Communication Timeout.
static HAL_StatusTypeDef | USART_SetConfig (USART_HandleTypeDef *husart)
Configure the USART peripheral.
static HAL_StatusTypeDef | USART_CheckIdleState (USART_HandleTypeDef *husart)
Check the USART Idle State.
static HAL_StatusTypeDef | USART_Transmit_IT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non-blocking mode.
static HAL_StatusTypeDef | USART_Receive_IT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_TransmitReceive_IT (USART_HandleTypeDef *husart)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).

Detailed Description

USART Private functions.

    [..]
    This subsection provides a set of functions allowing to control the USART.
     (+) USART_SetConfig() API is used to set the USART communication parameters.
     (+) USART_CheckIdleState() APi ensures that TEACK and/or REACK bits are set after initialization

Function Documentation

static HAL_StatusTypeDef USART_CheckIdleState ( USART_HandleTypeDef * husart ) [static]

Check the USART Idle State.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 2113 of file stm32f3xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, USART_HandleTypeDef::State, USART_TEACK_REACK_TIMEOUT, and USART_WaitOnFlagUntilTimeout().

Referenced by HAL_USART_Init().

static void USART_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1900 of file stm32f3xx_hal_usart.c.

References HAL_USART_ErrorCallback(), __DMA_HandleTypeDef::Parent, USART_HandleTypeDef::RxXferCount, and USART_HandleTypeDef::TxXferCount.

Referenced by HAL_USART_IRQHandler().

static void USART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication error callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1880 of file stm32f3xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_DMA, HAL_USART_ErrorCallback(), HAL_USART_STATE_READY, __DMA_HandleTypeDef::Parent, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, and USART_EndTransfer().

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1816 of file stm32f3xx_hal_usart.c.

References HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __DMA_HandleTypeDef::Instance, USART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, USART_HandleTypeDef::RxXferCount, and USART_HandleTypeDef::State.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1958 of file stm32f3xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, USART_HandleTypeDef::ErrorCode, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_USART_Abort_IT().

static void USART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1868 of file stm32f3xx_hal_usart.c.

References HAL_USART_RxHalfCpltCallback(), and __DMA_HandleTypeDef::Parent.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1770 of file stm32f3xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, HAL_USART_TxCpltCallback(), __DMA_HandleTypeDef::Instance, USART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, and USART_IT_TC.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1917 of file stm32f3xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, USART_HandleTypeDef::ErrorCode, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_USART_Abort_IT().

static void USART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1804 of file stm32f3xx_hal_usart.c.

References HAL_USART_TxHalfCpltCallback(), and __DMA_HandleTypeDef::Parent.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_EndTransfer ( USART_HandleTypeDef * husart ) [static]

End ongoing transfer on USART peripheral (following error detection or Transfer completion).

Parameters:
husart USART handle.
Return values:
None

Definition at line 1754 of file stm32f3xx_hal_usart.c.

References HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

Referenced by HAL_USART_DMAStop(), HAL_USART_IRQHandler(), and USART_DMAError().

static HAL_StatusTypeDef USART_EndTransmit_IT ( USART_HandleTypeDef * husart ) [static]

Wraps up transmission in non-blocking mode.

Parameters:
husart Pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 2218 of file stm32f3xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, HAL_USART_STATE_READY, HAL_USART_TxCpltCallback(), USART_HandleTypeDef::State, USART_IT_ERR, and USART_IT_TC.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_Receive_IT ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
Parameters:
husart USART handle
Return values:
HAL status

Definition at line 2242 of file stm32f3xx_hal_usart.c.

References HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_DUMMY_DATA, USART_PARITY_NONE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_SetConfig ( USART_HandleTypeDef * husart ) [static]

Configure the USART peripheral.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 2032 of file stm32f3xx_hal_usart.c.

References assert_param, USART_InitTypeDef::BaudRate, USART_InitTypeDef::CLKLastBit, USART_InitTypeDef::CLKPhase, USART_InitTypeDef::CLKPolarity, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, IS_USART_BAUDRATE, IS_USART_LASTBIT, IS_USART_MODE, IS_USART_PARITY, IS_USART_PHASE, IS_USART_POLARITY, IS_USART_STOPBITS, IS_USART_WORD_LENGTH, LSE_VALUE, USART_InitTypeDef::Mode, USART_InitTypeDef::Parity, USART_InitTypeDef::StopBits, USART_CLOCK_ENABLE, USART_CLOCKSOURCE_HSI, USART_CLOCKSOURCE_LSE, USART_CLOCKSOURCE_PCLK1, USART_CLOCKSOURCE_PCLK2, USART_CLOCKSOURCE_SYSCLK, USART_CLOCKSOURCE_UNDEFINED, USART_CR1_FIELDS, USART_CR2_FIELDS, USART_GETCLOCKSOURCE, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_Init().

static HAL_StatusTypeDef USART_Transmit_IT ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 2169 of file stm32f3xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_IT_TC, USART_IT_TXE, USART_PARITY_NONE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_TransmitReceive_IT ( USART_HandleTypeDef * husart ) [static]

Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_TransmitReceive_IT().
Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 2295 of file stm32f3xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_GET_FLAG, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_FLAG_RXNE, USART_FLAG_TXE, USART_IT_TXE, USART_PARITY_NONE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle USART Communication Timeout.

Parameters:
husart | USART handle.
Flag | Specifies the USART flag to check.
Status | the Flag status (SET or RESET).
Tickstart | Tick start value
Timeout | timeout duration.
Return values:
HAL status

Definition at line 2000 of file stm32f3xx_hal_usart.c.

References __HAL_USART_GET_FLAG, HAL_GetTick(), HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), and USART_CheckIdleState().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Exported Types

Data Structures | Enumerations
USART Exported Types
USART

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | USART_HandleTypeDef
USART handle Structure definition. More...

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00U, HAL_USART_STATE_READY = 0x01U, HAL_USART_STATE_BUSY = 0x02U, HAL_USART_STATE_BUSY_TX = 0x12U,
HAL_USART_STATE_BUSY_RX = 0x22U, HAL_USART_STATE_BUSY_TX_RX = 0x32U, HAL_USART_STATE_TIMEOUT = 0x03U, HAL_USART_STATE_ERROR = 0x04U
}
HAL USART State structures definition. More...
enum USART_ClockSourceTypeDef {
USART_CLOCKSOURCE_PCLK1 = 0x00U, USART_CLOCKSOURCE_PCLK2 = 0x01U, USART_CLOCKSOURCE_HSI = 0x02U, USART_CLOCKSOURCE_SYSCLK = 0x04U,
USART_CLOCKSOURCE_LSE = 0x08U, USART_CLOCKSOURCE_UNDEFINED = 0x10U
}
USART clock sources definitions. More...

Enumeration Type Documentation

enum HAL_USART_StateTypeDef

HAL USART State structures definition.

Enumerator:
HAL_USART_STATE_RESET

Peripheral is not initialized

HAL_USART_STATE_READY

Peripheral Initialized and ready for use

HAL_USART_STATE_BUSY

an internal process is ongoing

HAL_USART_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_USART_STATE_BUSY_RX

Data Reception process is ongoing

HAL_USART_STATE_BUSY_TX_RX

Data Transmission Reception process is ongoing

HAL_USART_STATE_TIMEOUT

Timeout state

HAL_USART_STATE_ERROR

Error

Definition at line 99 of file stm32f3xx_hal_usart.h.

enum USART_ClockSourceTypeDef

USART clock sources definitions.

Enumerator:
USART_CLOCKSOURCE_PCLK1

PCLK1 clock source

USART_CLOCKSOURCE_PCLK2

PCLK2 clock source

USART_CLOCKSOURCE_HSI

HSI clock source

USART_CLOCKSOURCE_SYSCLK

SYSCLK clock source

USART_CLOCKSOURCE_LSE

LSE clock source

USART_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 114 of file stm32f3xx_hal_usart.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
USART_InitTypeDef Struct Reference
USART Exported Types

USART Init Structure definition. More...

#include <stm32f3xx_hal_usart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | CLKLastBit

Detailed Description

USART Init Structure definition.

Definition at line 63 of file stm32f3xx_hal_usart.h.

Field Documentation

uint32_t USART_InitTypeDef::BaudRate

This member configures the Usart communication baud rate. The baud rate is computed using the following formula: Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))).

Definition at line 65 of file stm32f3xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of USART Last Bit.

Definition at line 91 of file stm32f3xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of USART Clock Phase.

Definition at line 88 of file stm32f3xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of USART Clock Polarity.

Definition at line 85 of file stm32f3xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of USART Mode.

Definition at line 82 of file stm32f3xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of USART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 75 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

uint32_t USART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of USART Number of Stop Bits.

Definition at line 72 of file stm32f3xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of USARTEx Word Length.

Definition at line 69 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_usart.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
USART_HandleTypeDef Struct Reference
USART Exported Types

USART handle Structure definition. More...

#include <stm32f3xx_hal_usart.h>

Data Fields

USART_TypeDef * | Instance
USART_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_USART_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

USART handle Structure definition.

Definition at line 128 of file stm32f3xx_hal_usart.h.

Field Documentation

__IO uint32_t USART_HandleTypeDef::ErrorCode

USART Error code

Definition at line 156 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_GetError(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_CheckIdleState(), USART_DMAError(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

DMA_HandleTypeDef* USART_HandleTypeDef::hdmarx

USART Rx DMA Handle parameters

Definition at line 150 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAStop(), HAL_USART_IRQHandler(), HAL_USART_Receive_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

DMA_HandleTypeDef* USART_HandleTypeDef::hdmatx

USART Tx DMA Handle parameters

Definition at line 148 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAStop(), HAL_USART_IRQHandler(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

USART_InitTypeDef USART_HandleTypeDef::Init

USART communication parameters

Definition at line 132 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

USART_TypeDef* USART_HandleTypeDef::Instance

USART registers base address

Definition at line 130 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_CheckIdleState(), USART_DMAReceiveCplt(), USART_DMATransmitCplt(), USART_EndTransfer(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

HAL_LockTypeDef USART_HandleTypeDef::Lock

Locking object

Definition at line 152 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Init().

uint16_t USART_HandleTypeDef::Mask

USART Rx RDR register mask

Definition at line 146 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_TransmitReceive(), USART_Receive_IT(), and USART_TransmitReceive_IT().

uint8_t* USART_HandleTypeDef::pRxBuffPtr

Pointer to USART Rx transfer Buffer

Definition at line 140 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_Receive_IT(), and USART_TransmitReceive_IT().

uint8_t* USART_HandleTypeDef::pTxBuffPtr

Pointer to USART Tx transfer Buffer

Definition at line 134 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

__IO uint16_t USART_HandleTypeDef::RxXferCount

USART Rx Transfer Counter

Definition at line 144 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), USART_Receive_IT(), and USART_TransmitReceive_IT().

uint16_t USART_HandleTypeDef::RxXferSize

USART Rx Transfer size

Definition at line 142 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

__IO HAL_USART_StateTypeDef USART_HandleTypeDef::State

USART communication state

Definition at line 154 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_GetState(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_CheckIdleState(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), USART_EndTransfer(), USART_EndTransmit_IT(), USART_Receive_IT(), USART_Transmit_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

__IO uint16_t USART_HandleTypeDef::TxXferCount

USART Tx Transfer Counter

Definition at line 138 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMARxAbortCallback(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

uint16_t USART_HandleTypeDef::TxXferSize

USART Tx Transfer size

Definition at line 136 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_usart.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Error

Defines
USART Error
USART Exported Constants

Defines

#define | HAL_USART_ERROR_NONE (0x00000000U)
#define | HAL_USART_ERROR_PE (0x00000001U)
#define | HAL_USART_ERROR_NE (0x00000002U)
#define | HAL_USART_ERROR_FE (0x00000004U)
#define | HAL_USART_ERROR_ORE (0x00000008U)
#define | HAL_USART_ERROR_DMA (0x00000010U)

Define Documentation

#define HAL_USART_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 177 of file stm32f3xx_hal_usart.h.

Referenced by USART_DMAError().

#define HAL_USART_ERROR_FE (0x00000004U)

frame error

Definition at line 175 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_NE (0x00000002U)

Noise error

Definition at line 174 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_NONE (0x00000000U)

No error

Definition at line 172 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_CheckIdleState(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define HAL_USART_ERROR_ORE (0x00000008U)

Overrun error

Definition at line 176 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_PE (0x00000001U)

Parity error

Definition at line 173 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Number of Stop Bits

Defines
USART Number of Stop Bits
USART Exported Constants

Defines

#define | USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | USART_STOPBITS_1 (0x00000000U)
#define | USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define | USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)

Define Documentation

#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)

USART frame with 0.5 stop bit

Definition at line 185 of file stm32f3xx_hal_usart.h.

#define USART_STOPBITS_1 (0x00000000U)

USART frame with 1 stop bit

Definition at line 186 of file stm32f3xx_hal_usart.h.

#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

USART frame with 1.5 stop bits

Definition at line 187 of file stm32f3xx_hal_usart.h.

#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)

USART frame with 2 stop bits

Definition at line 188 of file stm32f3xx_hal_usart.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Parity

Defines
USART Parity
USART Exported Constants

Defines

#define | USART_PARITY_NONE (0x00000000U)
#define | USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Even parity

Definition at line 197 of file stm32f3xx_hal_usart.h.

#define USART_PARITY_NONE (0x00000000U)

No parity

Definition at line 196 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Odd parity

Definition at line 198 of file stm32f3xx_hal_usart.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Mode

Defines
USART Mode
USART Exported Constants

Defines

#define | USART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | USART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define USART_MODE_RX ((uint32_t)USART_CR1_RE)

RX mode

Definition at line 206 of file stm32f3xx_hal_usart.h.

#define USART_MODE_TX ((uint32_t)USART_CR1_TE)

TX mode

Definition at line 207 of file stm32f3xx_hal_usart.h.

#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

RX and TX mode

Definition at line 208 of file stm32f3xx_hal_usart.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Clock

Defines
USART Clock
USART Exported Constants

Defines

#define | USART_CLOCK_DISABLE (0x00000000U)
#define | USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)

Define Documentation

#define USART_CLOCK_DISABLE (0x00000000U)

USART clock disable

Definition at line 216 of file stm32f3xx_hal_usart.h.

#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)

USART clock enable

Definition at line 217 of file stm32f3xx_hal_usart.h.

Referenced by USART_SetConfig().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Clock Polarity

Defines
USART Clock Polarity
USART Exported Constants

Defines

#define | USART_POLARITY_LOW (0x00000000U)
#define | USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Define Documentation

#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

USART Clock signal is steady High

Definition at line 226 of file stm32f3xx_hal_usart.h.

#define USART_POLARITY_LOW (0x00000000U)

USART Clock signal is steady Low

Definition at line 225 of file stm32f3xx_hal_usart.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Clock Phase

Defines
USART Clock Phase
USART Exported Constants

Defines

#define | USART_PHASE_1EDGE (0x00000000U)
#define | USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Define Documentation

#define USART_PHASE_1EDGE (0x00000000U)

USART frame phase on first clock transition

Definition at line 234 of file stm32f3xx_hal_usart.h.

#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

USART frame phase on second clock transition

Definition at line 235 of file stm32f3xx_hal_usart.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Last Bit

Defines
USART Last Bit
USART Exported Constants

Defines

#define | USART_LASTBIT_DISABLE (0x00000000U)
#define | USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Define Documentation

#define USART_LASTBIT_DISABLE (0x00000000U)

USART frame last data bit clock pulse not output to SCLK pin

Definition at line 243 of file stm32f3xx_hal_usart.h.

#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

USART frame last data bit clock pulse output to SCLK pin

Definition at line 244 of file stm32f3xx_hal_usart.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Request Parameters

Defines
USART Request Parameters
USART Exported Constants

Defines

#define | USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Define Documentation

#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)

Receive Data flush Request

Definition at line 252 of file stm32f3xx_hal_usart.h.

#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Transmit data flush Request

Definition at line 253 of file stm32f3xx_hal_usart.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Flags

Defines
USART Flags
USART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | USART_FLAG_REACK (0x00400000U)
#define | USART_FLAG_TEACK (0x00200000U)
#define | USART_FLAG_BUSY (0x00010000U)
#define | USART_FLAG_CTS (0x00000400U)
#define | USART_FLAG_CTSIF (0x00000200U)
#define | USART_FLAG_LBDF (0x00000100U)
#define | USART_FLAG_TXE (0x00000080U)
#define | USART_FLAG_TC (0x00000040U)
#define | USART_FLAG_RXNE (0x00000020U)
#define | USART_FLAG_IDLE (0x00000010U)
#define | USART_FLAG_ORE (0x00000008U)
#define | USART_FLAG_NE (0x00000004U)
#define | USART_FLAG_FE (0x00000002U)
#define | USART_FLAG_PE (0x00000001U)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define USART_FLAG_BUSY (0x00010000U)

USART busy flag

Definition at line 265 of file stm32f3xx_hal_usart.h.

#define USART_FLAG_CTS (0x00000400U)

USART clear to send flag

Definition at line 266 of file stm32f3xx_hal_usart.h.

#define USART_FLAG_CTSIF (0x00000200U)

USART clear to send interrupt flag

Definition at line 267 of file stm32f3xx_hal_usart.h.

#define USART_FLAG_FE (0x00000002U)

USART frame error

Definition at line 275 of file stm32f3xx_hal_usart.h.

#define USART_FLAG_IDLE (0x00000010U)

USART idle flag

Definition at line 272 of file stm32f3xx_hal_usart.h.

#define USART_FLAG_LBDF (0x00000100U)

USART LIN break detection flag

Definition at line 268 of file stm32f3xx_hal_usart.h.

#define USART_FLAG_NE (0x00000004U)

USART noise error

Definition at line 274 of file stm32f3xx_hal_usart.h.

#define USART_FLAG_ORE (0x00000008U)

USART overrun error

Definition at line 273 of file stm32f3xx_hal_usart.h.

#define USART_FLAG_PE (0x00000001U)

USART parity error

Definition at line 276 of file stm32f3xx_hal_usart.h.

#define USART_FLAG_REACK (0x00400000U)

USART receive enable acknowledge flag

Definition at line 263 of file stm32f3xx_hal_usart.h.

#define USART_FLAG_RXNE (0x00000020U)

USART read data register not empty

Definition at line 271 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_TransmitReceive(), and USART_TransmitReceive_IT().

#define USART_FLAG_TC (0x00000040U)

USART transmission complete

Definition at line 270 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), and HAL_USART_TransmitReceive().

#define USART_FLAG_TEACK (0x00200000U)

USART transmit enable acknowledge flag

Definition at line 264 of file stm32f3xx_hal_usart.h.

#define USART_FLAG_TXE (0x00000080U)

USART transmit data register empty

Definition at line 269 of file stm32f3xx_hal_usart.h.

Referenced by USART_TransmitReceive_IT().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Interrupts Definition

Defines
USART Interrupts Definition
USART Exported Constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | USART_IT_PE ((uint16_t)0x0028U)
#define | USART_IT_TXE ((uint16_t)0x0727U)
#define | USART_IT_TC ((uint16_t)0x0626U)
#define | USART_IT_RXNE ((uint16_t)0x0525U)
#define | USART_IT_IDLE ((uint16_t)0x0424U)
#define | USART_IT_ERR ((uint16_t)0x0060U)
#define | USART_IT_ORE ((uint16_t)0x0300U)
#define | USART_IT_NE ((uint16_t)0x0200U)
#define | USART_IT_FE ((uint16_t)0x0100U)

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define USART_IT_ERR ((uint16_t)0x0060U)

USART error interruption

Definition at line 297 of file stm32f3xx_hal_usart.h.

Referenced by USART_EndTransmit_IT().

#define USART_IT_FE ((uint16_t)0x0100U)

USART frame error interruption

Definition at line 300 of file stm32f3xx_hal_usart.h.

#define USART_IT_IDLE ((uint16_t)0x0424U)

USART idle interruption

Definition at line 296 of file stm32f3xx_hal_usart.h.

#define USART_IT_NE ((uint16_t)0x0200U)

USART noise error interruption

Definition at line 299 of file stm32f3xx_hal_usart.h.

#define USART_IT_ORE ((uint16_t)0x0300U)

USART overrun error interruption

Definition at line 298 of file stm32f3xx_hal_usart.h.

#define USART_IT_PE ((uint16_t)0x0028U)

USART parity error interruption

Definition at line 292 of file stm32f3xx_hal_usart.h.

#define USART_IT_RXNE ((uint16_t)0x0525U)

USART read data register not empty interruption

Definition at line 295 of file stm32f3xx_hal_usart.h.

#define USART_IT_TC ((uint16_t)0x0626U)

USART transmission complete interruption

Definition at line 294 of file stm32f3xx_hal_usart.h.

Referenced by USART_DMATransmitCplt(), USART_EndTransmit_IT(), and USART_Transmit_IT().

#define USART_IT_TXE ((uint16_t)0x0727U)

USART transmit data register empty interruption

Definition at line 293 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Transmit_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Interruption Clear Flags

Defines
USART Interruption Clear Flags
USART Exported Constants

Defines

#define | USART_CLEAR_PEF USART_ICR_PECF
#define | USART_CLEAR_FEF USART_ICR_FECF
#define | USART_CLEAR_NEF USART_ICR_NCF
#define | USART_CLEAR_OREF USART_ICR_ORECF
#define | USART_CLEAR_IDLEF USART_ICR_IDLECF
#define | USART_CLEAR_TCF USART_ICR_TCCF
#define | USART_CLEAR_CTSF USART_ICR_CTSCF

Define Documentation

#define USART_CLEAR_CTSF USART_ICR_CTSCF

CTS Interrupt Clear Flag

Definition at line 314 of file stm32f3xx_hal_usart.h.

#define USART_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 309 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 312 of file stm32f3xx_hal_usart.h.

#define USART_CLEAR_NEF USART_ICR_NCF

Noise detected Clear Flag

Definition at line 310 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 311 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAResume(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 308 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 313 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Interruption Flags Mask

Defines
USART Interruption Flags Mask
USART Exported Constants

Defines

#define USART_IT_MASK ((uint16_t)0x001FU)

Define Documentation

#define USART_IT_MASK ((uint16_t)0x001FU)

USART interruptions flags mask

Definition at line 322 of file stm32f3xx_hal_usart.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Exported Macros

Defines
USART Exported Macros
USART

Defines

#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
Reset USART handle state.
#define | __HAL_USART_FLUSH_DRREGISTER(__HANDLE__)
Flush the USART Data registers.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified USART flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified USART pending flag.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
Clear the USART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
Clear the USART IDLE pending flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified USART interrupt.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified USART interrupt.
#define | __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
Check whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified USART interrupt source is enabled or not.
#define | __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified USART ISR flag, in setting the proper ICR register flag.
#define | __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__))
Set a specific USART request flag.
#define | __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the USART one bit sample method.
#define | __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the USART one bit sample method.
#define | __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.

Define Documentation

#define __HAL_USART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)

Clear the USART FE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 397 of file stm32f3xx_hal_usart.h.

#define __HAL_USART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified USART pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • USART_CLEAR_PEF
  • USART_CLEAR_FEF
  • USART_CLEAR_NEF
  • USART_CLEAR_OREF
  • USART_CLEAR_IDLEF
  • USART_CLEAR_TCF
  • USART_CLEAR_CTSF
Return values:
None

Definition at line 385 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAResume(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define __HAL_USART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)

Clear the USART IDLE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 415 of file stm32f3xx_hal_usart.h.

#define __HAL_USART_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified USART ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the USART Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt. This parameter can be one of the following values:
  • USART_CLEAR_PEF Parity Error Clear Flag
  • USART_CLEAR_FEF Framing Error Clear Flag
  • USART_CLEAR_NEF Noise detected Clear Flag
  • USART_CLEAR_OREF OverRun Error Clear Flag
  • USART_CLEAR_IDLEF IDLE line detected Clear Flag
  • USART_CLEAR_TCF Transmission Complete Clear Flag
  • USART_CLEAR_CTSF CTS Interrupt Clear Flag
Return values:
None

Definition at line 499 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define __HAL_USART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)

Clear the USART NE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 403 of file stm32f3xx_hal_usart.h.

#define __HAL_USART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)

Clear the USART ORE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 409 of file stm32f3xx_hal_usart.h.

#define __HAL_USART_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)

Clear the USART PE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 391 of file stm32f3xx_hal_usart.h.

#define __HAL_USART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable USART.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 534 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Init().

#define __HAL_USART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))

Disable the specified USART interrupt.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to disable. This parameter can be one of the following values:
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_PE Parity Error interrupt
  • USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 445 of file stm32f3xx_hal_usart.h.

Referenced by USART_EndTransmit_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

#define __HAL_USART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable USART.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 528 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Init().

#define __HAL_USART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))

Enable the specified USART interrupt.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to enable. This parameter can be one of the following values:
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_PE Parity Error interrupt
  • USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 429 of file stm32f3xx_hal_usart.h.

Referenced by HAL_USART_Transmit_IT(), USART_DMATransmitCplt(), and USART_Transmit_IT().

#define __HAL_USART_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                \
      SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
      SET_BIT((__HANDLE__)->Instance->RQR, USART_TXDATA_FLUSH_REQUEST); \
    }  while(0U)

Flush the USART Data registers.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 346 of file stm32f3xx_hal_usart.h.

#define __HAL_USART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified USART flag is set or not.

Parameters:
__HANDLE__ specifies the USART Handle
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • USART_FLAG_REACK Receive enable acknowledge flag
  • USART_FLAG_TEACK Transmit enable acknowledge flag
  • USART_FLAG_BUSY Busy flag
  • USART_FLAG_CTS CTS Change flag
  • USART_FLAG_TXE Transmit data register empty flag
  • USART_FLAG_TC Transmission Complete flag
  • USART_FLAG_RXNE Receive data register not empty flag
  • USART_FLAG_IDLE Idle Line detection flag
  • USART_FLAG_ORE OverRun Error flag
  • USART_FLAG_NE Noise Error flag
  • USART_FLAG_FE Framing Error flag
  • USART_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 370 of file stm32f3xx_hal_usart.h.

Referenced by USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

#define __HAL_USART_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))

Check whether the specified USART interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the USART Handle.
__IT__ specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_ORE OverRun Error interrupt
  • USART_IT_NE Noise Error interrupt
  • USART_IT_FE Framing Error interrupt
  • USART_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 464 of file stm32f3xx_hal_usart.h.

#define __HAL_USART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
                                                   (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << \
                                                   (((uint16_t)(__IT__)) & USART_IT_MASK)))

Check whether the specified USART interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the USART Handle.
__IT__ specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_ORE OverRun Error interrupt
  • USART_IT_NE Noise Error interrupt
  • USART_IT_FE Framing Error interrupt
  • USART_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 480 of file stm32f3xx_hal_usart.h.

#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the USART one bit sample method.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 522 of file stm32f3xx_hal_usart.h.

#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the USART one bit sample method.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 516 of file stm32f3xx_hal_usart.h.

#define __HAL_USART_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_USART_STATE_RESET)

Reset USART handle state.

Parameters:
__HANDLE__ USART handle.
Return values:
None

Definition at line 340 of file stm32f3xx_hal_usart.h.

#define __HAL_USART_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (__REQ__))

Set a specific USART request flag.

Parameters:
__HANDLE__ specifies the USART Handle.
__REQ__ specifies the request flag to set. This parameter can be one of the following values:
  • USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 510 of file stm32f3xx_hal_usart.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Private Macros

Defines
USART Private Macros
USART

Defines

#define | IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001U)
Check USART Baud rate.
#define | IS_USART_STOPBITS(__STOPBITS__)
Ensure that USART frame number of stop bits is valid.
#define | IS_USART_PARITY(__PARITY__)
Ensure that USART frame parity is valid.
#define | IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that USART communication mode is valid.
#define | IS_USART_CLOCK(__CLOCK__)
Ensure that USART clock state is valid.
#define | IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
Ensure that USART frame polarity is valid.
#define | IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
Ensure that USART frame phase is valid.
#define | IS_USART_LASTBIT(__LASTBIT__)
Ensure that USART frame last bit clock pulse setting is valid.
#define | IS_USART_REQUEST_PARAMETER(__PARAM__)
Ensure that USART request parameter is valid.

Define Documentation

#define IS_USART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 9000001U)

Check USART Baud rate.

Parameters:
__BAUDRATE__ Baudrate specified by the user. The maximum Baud Rate is derived from the maximum clock on F3 (i.e. 72 MHz) divided by the smallest oversampling used on the USART (i.e. 8).
Return values:
Test result (TRUE or FALSE).

Definition at line 551 of file stm32f3xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_CLOCK ( __CLOCK__ )
Value:
(((__CLOCK__) == USART_CLOCK_DISABLE) || \
                                   ((__CLOCK__) == USART_CLOCK_ENABLE))

Ensure that USART clock state is valid.

Parameters:
__CLOCK__ USART clock state.
Return values:
SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)

Definition at line 584 of file stm32f3xx_hal_usart.h.

#define IS_USART_LASTBIT ( __LASTBIT__ )
Value:
(((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
                                       ((__LASTBIT__) == USART_LASTBIT_ENABLE))

Ensure that USART frame last bit clock pulse setting is valid.

Parameters:
__LASTBIT__ USART frame last bit clock pulse setting.
Return values:
SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)

Definition at line 606 of file stm32f3xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_MODE ( __MODE__ ) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that USART communication mode is valid.

Parameters:
__MODE__ USART communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 577 of file stm32f3xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == USART_PARITY_NONE) || \
                                     ((__PARITY__) == USART_PARITY_EVEN) || \
                                     ((__PARITY__) == USART_PARITY_ODD))

Ensure that USART frame parity is valid.

Parameters:
__PARITY__ USART frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 568 of file stm32f3xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PHASE ( __CPHA__ ) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))

Ensure that USART frame phase is valid.

Parameters:
__CPHA__ USART frame phase.
Return values:
SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)

Definition at line 599 of file stm32f3xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_POLARITY ( __CPOL__ ) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))

Ensure that USART frame polarity is valid.

Parameters:
__CPOL__ USART frame polarity.
Return values:
SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)

Definition at line 592 of file stm32f3xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
                                               ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))

Ensure that USART request parameter is valid.

Parameters:
__PARAM__ USART request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 614 of file stm32f3xx_hal_usart.h.

#define IS_USART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == USART_STOPBITS_0_5) || \
                                         ((__STOPBITS__) == USART_STOPBITS_1)   || \
                                         ((__STOPBITS__) == USART_STOPBITS_1_5) || \
                                         ((__STOPBITS__) == USART_STOPBITS_2))

Ensure that USART frame number of stop bits is valid.

Parameters:
__STOPBITS__ USART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 558 of file stm32f3xx_hal_usart.h.

Referenced by USART_SetConfig().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
WWDG Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
          ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
      (+) Initialize and start the WWDG according to the specified parameters
          in the WWDG_InitTypeDef of associated handle.
      (+) Initialize the WWDG MSP.

Function Documentation

HAL_StatusTypeDef HAL_WWDG_Init ( WWDG_HandleTypeDef * hwwdg )

Initialize the WWDG according to the specified.

parameters in the WWDG_InitTypeDef of associated handle.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 172 of file stm32f3xx_hal_wwdg.c.

References assert_param, WWDG_InitTypeDef::Counter, WWDG_InitTypeDef::EWIMode, HAL_WWDG_MspInit(), WWDG_HandleTypeDef::Init, WWDG_HandleTypeDef::Instance, IS_WWDG_COUNTER, IS_WWDG_EWI_MODE, IS_WWDG_PRESCALER, IS_WWDG_WINDOW, WWDG_InitTypeDef::Prescaler, and WWDG_InitTypeDef::Window.

void HAL_WWDG_MspInit ( WWDG_HandleTypeDef * hwwdg )

Initialize the WWDG MSP.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Note:
When rewriting this function in user file, mechanism may be added to avoid multiple initialize when HAL_WWDG_Init function is called again to change parameters.
Return values:
None

Definition at line 210 of file stm32f3xx_hal_wwdg.c.

Referenced by HAL_WWDG_Init().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IO operation functions

Functions
IO operation functions
WWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

IO operation functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Refresh the WWDG.
    (+) Handle WWDG interrupt request and associated function callback.

Function Documentation

void HAL_WWDG_EarlyWakeupCallback ( WWDG_HandleTypeDef * hwwdg )

WWDG Early Wakeup callback.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 292 of file stm32f3xx_hal_wwdg.c.

Referenced by HAL_WWDG_IRQHandler().

void HAL_WWDG_IRQHandler ( WWDG_HandleTypeDef * hwwdg )

Handle WWDG interrupt request.

Note:
The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. The EWI interrupt is enabled by calling HAL_WWDG_Init function with EWIMode set to WWDG_EWI_ENABLE. When the downcounter reaches the value 0x40, and EWI interrupt is generated and the corresponding Interrupt Service Routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device.
Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 269 of file stm32f3xx_hal_wwdg.c.

References __HAL_WWDG_CLEAR_FLAG, __HAL_WWDG_GET_FLAG, __HAL_WWDG_GET_IT_SOURCE, HAL_WWDG_EarlyWakeupCallback(), WWDG_FLAG_EWIF, and WWDG_IT_EWI.

HAL_StatusTypeDef HAL_WWDG_Refresh ( WWDG_HandleTypeDef * hwwdg )

Refresh the WWDG.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 246 of file stm32f3xx_hal_wwdg.c.

References WWDG_InitTypeDef::Counter, WWDG_HandleTypeDef::Init, and WWDG_HandleTypeDef::Instance.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: WWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
WWDG_InitTypeDef Struct Reference
WWDG Exported Types

WWDG Init structure definition. More...

#include <stm32f3xx_hal_wwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Window
uint32_t | Counter
uint32_t | EWIMode

Detailed Description

WWDG Init structure definition.

Definition at line 64 of file stm32f3xx_hal_wwdg.h.

Field Documentation

uint32_t WWDG_InitTypeDef::Counter

Specifies the WWDG free-running downcounter value. This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7FU

Definition at line 72 of file stm32f3xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

uint32_t WWDG_InitTypeDef::EWIMode

Specifies if WWDG Early Wakeup Interupt is enable or not. This parameter can be a value of WWDG Early Wakeup Interrupt Mode

Definition at line 75 of file stm32f3xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Prescaler

Specifies the prescaler value of the WWDG. This parameter can be a value of WWDG Prescaler

Definition at line 66 of file stm32f3xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Window

Specifies the WWDG window value to be compared to the downcounter. This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7FU

Definition at line 69 of file stm32f3xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_wwdg.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: WWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
WWDG_HandleTypeDef Struct Reference
WWDG Exported Types

WWDG handle Structure definition. More...

#include <stm32f3xx_hal_wwdg.h>

Data Fields

WWDG_TypeDef * Instance
WWDG_InitTypeDef Init

Detailed Description

WWDG handle Structure definition.

Definition at line 83 of file stm32f3xx_hal_wwdg.h.

Field Documentation

WWDG_InitTypeDef WWDG_HandleTypeDef::Init

WWDG required parameters

Definition at line 87 of file stm32f3xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

WWDG_TypeDef* WWDG_HandleTypeDef::Instance

Register base address

Definition at line 85 of file stm32f3xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

The documentation for this struct was generated from the following file:
  • stm32f3xx_hal_wwdg.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: WWDG Interrupt definition

Defines
WWDG Interrupt definition
WWDG Exported Constants

Defines

#define WWDG_IT_EWI WWDG_CFR_EWI

Define Documentation

#define WWDG_IT_EWI WWDG_CFR_EWI

Early wakeup interrupt

Definition at line 103 of file stm32f3xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: WWDG Flag definition

Defines
WWDG Flag definition
WWDG Exported Constants

WWDG Flag definition. More...

Defines

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Detailed Description

WWDG Flag definition.

Define Documentation

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Early wakeup interrupt flag

Definition at line 112 of file stm32f3xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: WWDG Prescaler

Defines
WWDG Prescaler
WWDG Exported Constants

Defines

#define | WWDG_PRESCALER_1 0x00000000u
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | WWDG_PRESCALER_8 WWDG_CFR_WDGTB

Define Documentation

#define WWDG_PRESCALER_1 0x00000000u

WWDG counter clock = (PCLK1/4096U)/1U

Definition at line 120 of file stm32f3xx_hal_wwdg.h.

#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0

WWDG counter clock = (PCLK1/4096U)/2U

Definition at line 121 of file stm32f3xx_hal_wwdg.h.

#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1

WWDG counter clock = (PCLK1/4096U)/4U

Definition at line 122 of file stm32f3xx_hal_wwdg.h.

#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB

WWDG counter clock = (PCLK1/4096U)/8U

Definition at line 123 of file stm32f3xx_hal_wwdg.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: WWDG Early Wakeup Interrupt Mode

Defines
WWDG Early Wakeup Interrupt Mode
WWDG Exported Constants

Defines

#define | WWDG_EWI_DISABLE 0x00000000u
#define | WWDG_EWI_ENABLE WWDG_CFR_EWI

Define Documentation

#define WWDG_EWI_DISABLE 0x00000000u

EWI Disable

Definition at line 131 of file stm32f3xx_hal_wwdg.h.

#define WWDG_EWI_ENABLE WWDG_CFR_EWI

EWI Enable

Definition at line 132 of file stm32f3xx_hal_wwdg.h.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: WWDG Private Macros

Defines
WWDG Private Macros
WWDG

Defines

#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define | IS_WWDG_EWI_MODE(__MODE__)

Define Documentation

#define IS_WWDG_COUNTER ( __COUNTER__ ) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))

Definition at line 153 of file stm32f3xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_EWI_MODE ( __MODE__ )
Value:
(((__MODE__) == WWDG_EWI_ENABLE) || \
                                             ((__MODE__) == WWDG_EWI_DISABLE))

Definition at line 155 of file stm32f3xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == WWDG_PRESCALER_1) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_2) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_4) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_8))

Definition at line 146 of file stm32f3xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_WINDOW ( __WINDOW__ ) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))

Definition at line 151 of file stm32f3xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: WWDG Exported Macros

Defines
WWDG Exported Macros
WWDG

Defines

#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enable the WWDG peripheral.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enable the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Check whether the selected WWDG interrupt has occurred or not.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG interrupt pending bits.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified WWDG flag is set or not.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified WWDG interrupt source is enabled or not.

Define Documentation

#define __HAL_WWDG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clear the WWDG's pending flags.

Parameters:
__HANDLE__ WWDG handle
__FLAG__ specifies the flag to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
None

Definition at line 223 of file stm32f3xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))

Clear the WWDG interrupt pending bits.

bits to clear the selected interrupt pending bits.

Parameters:
__HANDLE__ WWDG handle
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag

Definition at line 203 of file stm32f3xx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)

Enable the WWDG peripheral.

Parameters:
__HANDLE__ WWDG handle
Return values:
None

Definition at line 173 of file stm32f3xx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))

Enable the WWDG early wakeup interrupt.

Parameters:
__HANDLE__ WWDG handle
__INTERRUPT__ specifies the interrupt to enable. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early wakeup interrupt
Note:
Once enabled this interrupt cannot be disabled except by a system reset.
Return values:
None

Definition at line 184 of file stm32f3xx_hal_wwdg.h.

#define __HAL_WWDG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check whether the specified WWDG flag is set or not.

Parameters:
__HANDLE__ WWDG handle
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 213 of file stm32f3xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))

Check whether the selected WWDG interrupt has occurred or not.

Parameters:
__HANDLE__ WWDG handle
__INTERRUPT__ specifies the it to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt IT
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 194 of file stm32f3xx_hal_wwdg.h.

#define __HAL_WWDG_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified WWDG interrupt source is enabled or not.

Parameters:
__HANDLE__ WWDG Handle.
__INTERRUPT__ specifies the WWDG interrupt source to check. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early Wakeup Interrupt
Return values:
state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 232 of file stm32f3xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Extended Exported Macros

Defines
DMA Extended Exported Macros
DMAEx

Defines

#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Returns the current DMA Channel transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Returns the current DMA Channel half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Returns the current DMA Channel transfer error flag.
#define | __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel Global interrupt flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Channel pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clears the DMA Channel pending flags.

Define Documentation

#define __HAL_DMA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
  (DMA1->IFCR = (__FLAG__)))

Clears the DMA Channel pending flags.

Parameters:
__HANDLE__ DMA handle
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • DMA_FLAG_TCx: Transfer complete flag
  • DMA_FLAG_HTx: Half transfer complete flag
  • DMA_FLAG_TEx: Transfer error flag Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
Return values:
None

Definition at line 168 of file stm32f3xx_hal_dma_ex.h.

#define __HAL_DMA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
  (DMA1->ISR & (__FLAG__)))

Get the DMA Channel pending flags.

Parameters:
__HANDLE__ DMA handle
__FLAG__ Get the specified flag. This parameter can be any combination of the following values:
  • DMA_FLAG_TCx: Transfer complete flag
  • DMA_FLAG_HTx: Half transfer complete flag
  • DMA_FLAG_TEx: Transfer error flag Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
Return values:
The state of FLAG (SET or RESET).

Definition at line 153 of file stm32f3xx_hal_dma_ex.h.

#define __HAL_DMA_GET_GI_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
   DMA_FLAG_GL5)

Return the current DMA Channel Global interrupt flag.

Parameters:
__HANDLE__ DMA handle
Return values:
The specified transfer error flag index.

Definition at line 128 of file stm32f3xx_hal_dma_ex.h.

#define __HAL_DMA_GET_HT_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
   DMA_FLAG_HT5)

Returns the current DMA Channel half transfer complete flag.

Parameters:
__HANDLE__ DMA handle
Return values:
The specified half transfer complete flag index.

Definition at line 90 of file stm32f3xx_hal_dma_ex.h.

#define __HAL_DMA_GET_TC_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
   DMA_FLAG_TC5)

Returns the current DMA Channel transfer complete flag.

Parameters:
__HANDLE__ DMA handle
Return values:
The specified transfer complete flag index.

Definition at line 71 of file stm32f3xx_hal_dma_ex.h.

#define __HAL_DMA_GET_TE_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
   DMA_FLAG_TE5)

Returns the current DMA Channel transfer error flag.

Parameters:
__HANDLE__ DMA handle
Return values:
The specified transfer error flag index.

Definition at line 109 of file stm32f3xx_hal_dma_ex.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA Word Length

Defines
IRDA Word Length
IRDAEx Exported Constants

Defines

#define | IRDA_WORDLENGTH_8B (0x00000000U)
#define | IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Define Documentation

#define IRDA_WORDLENGTH_8B (0x00000000U)

8-bit long frame

Definition at line 71 of file stm32f3xx_hal_irda_ex.h.

#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

9-bit long frame

Definition at line 72 of file stm32f3xx_hal_irda_ex.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDAEx Private Macros

Defines
IRDAEx Private Macros
IRDAEx

Defines

#define | IRDA_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the IRDA clock source.
#define | IRDA_MASK_COMPUTATION(__HANDLE__)
Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_IRDA_WORD_LENGTH(__LENGTH__)
Ensure that IRDA frame length is valid.

Define Documentation

#define IRDA_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the IRDA clock source.

Parameters:
__HANDLE__ | specifies the IRDA Handle.
__CLOCKSOURCE__ | output variable.
Return values:
IRDA clocking source, written in __CLOCKSOURCE__.

Definition at line 251 of file stm32f3xx_hal_irda_ex.h.

Referenced by IRDA_SetConfig().

#define IRDA_MASK_COMPUTATION ( __HANDLE__ )
Value:
do {                                                                \
  if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)            \
  {                                                                   \
     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
     {                                                                \
        (__HANDLE__)->Mask = 0x01FFU ;                                \
     }                                                                \
     else                                                             \
     {                                                                \
        (__HANDLE__)->Mask = 0x00FFU ;                                \
     }                                                                \
  }                                                                   \
  else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)       \
  {                                                                   \
     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
     {                                                                \
        (__HANDLE__)->Mask = 0x00FFU ;                                \
     }                                                                \
     else                                                             \
     {                                                                \
        (__HANDLE__)->Mask = 0x007FU ;                                \
     }                                                                \
  }                                                                   \
} while(0U)

Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Note:
If PCE = 1, the parity bit is not included in the data extracted by the reception API(). This masking operation is not carried out in the case of DMA transfers.
Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None,the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 374 of file stm32f3xx_hal_irda_ex.h.

Referenced by HAL_IRDA_Receive(), and HAL_IRDA_Receive_IT().

#define IS_IRDA_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
                                         ((__LENGTH__) == IRDA_WORDLENGTH_9B))

Ensure that IRDA frame length is valid.

Parameters:
__LENGTH__ IRDA frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 414 of file stm32f3xx_hal_irda_ex.h.

Referenced by IRDA_SetConfig().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR WakeUp Pins

Defines
PWR WakeUp Pins
PWR Exported Constants

Defines

#define | PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
#define | PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
#define | PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3)

Define Documentation

#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)

Wakeup pin 1U

Definition at line 65 of file stm32f3xx_hal_pwr.h.

#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)

Wakeup pin 2U

Definition at line 66 of file stm32f3xx_hal_pwr.h.

#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3)

Wakeup pin 3U

Definition at line 67 of file stm32f3xx_hal_pwr.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Regulator state in STOP mode

Defines
PWR Regulator state in STOP mode
PWR Exported Constants

Defines

#define | PWR_MAINREGULATOR_ON (0x00000000U)
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS

Define Documentation

#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS

Voltage regulator in low-power mode during STOP mode

Definition at line 76 of file stm32f3xx_hal_pwr.h.

#define PWR_MAINREGULATOR_ON (0x00000000U)

Voltage regulator on during STOP mode

Definition at line 75 of file stm32f3xx_hal_pwr.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR SLEEP mode entry

Defines
PWR SLEEP mode entry
PWR Exported Constants

Defines

#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)

Define Documentation

#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)

Wait For Event instruction to enter SLEEP mode

Definition at line 85 of file stm32f3xx_hal_pwr.h.

#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)

Wait For Interruption instruction to enter SLEEP mode

Definition at line 84 of file stm32f3xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR STOP mode entry

Defines
PWR STOP mode entry
PWR Exported Constants

Defines

#define | PWR_STOPENTRY_WFI ((uint8_t)0x01U)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02U)

Define Documentation

#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)

Wait For Event instruction to enter STOP mode

Definition at line 94 of file stm32f3xx_hal_pwr.h.

#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)

Wait For Interruption instruction to enter STOP mode

Definition at line 93 of file stm32f3xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode().

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Flag

Defines
PWR Flag
PWR Exported Constants

Defines

#define | PWR_FLAG_WU PWR_CSR_WUF
#define | PWR_FLAG_SB PWR_CSR_SBF
#define | PWR_FLAG_PVDO PWR_CSR_PVDO
#define | PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF

Define Documentation

#define PWR_FLAG_PVDO PWR_CSR_PVDO

Power Voltage Detector output flag

Definition at line 104 of file stm32f3xx_hal_pwr.h.

#define PWR_FLAG_SB PWR_CSR_SBF

Standby flag

Definition at line 103 of file stm32f3xx_hal_pwr.h.

#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF

VREFINT reference voltage ready

Definition at line 105 of file stm32f3xx_hal_pwr.h.

#define PWR_FLAG_WU PWR_CSR_WUF

Wakeup event from wakeup pin or RTC alarm

Definition at line 102 of file stm32f3xx_hal_pwr.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Exported Macro

Defines
PWR Exported Macro
PWR

Defines

#define | __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
Check PWR flag is set or not.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
Clear the PWR's pending flags.

Define Documentation

#define __HAL_PWR_CLEAR_FLAG ( __FLAG__ ) (PWR->CR |= (__FLAG__) << 2U)

Clear the PWR's pending flags.

Parameters:
__FLAG__ specifies the flag to clear. This parameter can be one of the following values:
  • PWR_FLAG_WU: Wake Up flag
  • PWR_FLAG_SB: StandBy flag

Definition at line 145 of file stm32f3xx_hal_pwr.h.

#define __HAL_PWR_GET_FLAG ( __FLAG__ ) ((PWR->CSR & (__FLAG__)) == (__FLAG__))

Check PWR flag is set or not.

Parameters:
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. An additional wakeup event is detected if the WKUP pin is enabled (by setting the EWUP bit) when the WKUP pin level is already high.
  • PWR_FLAG_SB: StandBy flag. This flag indicates that the system was resumed from StandBy mode.
  • PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode For this reason, this bit is equal to 0 after Standby or reset until the PVDE bit is set.
  • PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference voltage VREFINT is ready.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 137 of file stm32f3xx_hal_pwr.h.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Private Macros

Defines
PWR Private Macros
PWR

Defines

#define | IS_PWR_WAKEUP_PIN(PIN)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))

Define Documentation

#define IS_PWR_REGULATOR ( REGULATOR )
Value:
(((REGULATOR) == PWR_MAINREGULATOR_ON) || \
                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))

Definition at line 160 of file stm32f3xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode().

#define IS_PWR_SLEEP_ENTRY ( ENTRY ) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))

Definition at line 163 of file stm32f3xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

#define IS_PWR_STOP_ENTRY ( ENTRY ) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))

Definition at line 165 of file stm32f3xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode().

#define IS_PWR_WAKEUP_PIN ( PIN )
Value:
(((PIN) == PWR_WAKEUP_PIN1) || \
                                ((PIN) == PWR_WAKEUP_PIN2) || \
                                ((PIN) == PWR_WAKEUP_PIN3))

Definition at line 156 of file stm32f3xx_hal_pwr.h.

Referenced by HAL_PWR_DisableWakeUpPin(), and HAL_PWR_EnableWakeUpPin().

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
PWR Exported Functions

Functions

void | HAL_PWR_DeInit (void)
Deinitializes the PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_DisableBkUpAccess (void)
Disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Function Documentation

void HAL_PWR_DeInit ( void )

Deinitializes the PWR peripheral registers to their default reset values.

Return values:
None

Definition at line 91 of file stm32f3xx_hal_pwr.c.

References __HAL_RCC_PWR_FORCE_RESET, and __HAL_RCC_PWR_RELEASE_RESET.

void HAL_PWR_DisableBkUpAccess ( void )

Disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Note:
If the HSE divided by 32 is used as the RTC clock, the Backup Domain Access should be kept enabled.
Return values:
None

Definition at line 116 of file stm32f3xx_hal_pwr.c.

void HAL_PWR_EnableBkUpAccess ( void )

Enables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Note:
If the HSE divided by 32 is used as the RTC clock, the Backup Domain Access should be kept enabled.
Return values:
None

Definition at line 104 of file stm32f3xx_hal_pwr.c.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PWR Exported Functions

Low Power modes configuration functions. More...

Functions

void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinx)
Enables the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disables the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enters Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enters STOP mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enters STANDBY mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enables CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disables CORTEX M4 SEVONPEND bit.
void | HAL_PWR_EnableBkUpAccess (void)
Enables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_DisableBkUpAccess (void)
Disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Detailed Description

Low Power modes configuration functions.

 ===============================================================================
                 ##### Peripheral Control functions #####
 ===============================================================================

    *** WakeUp pin configuration ***
    ================================
    [..]
      (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
          forced in input pull down configuration and is active on rising edges.
      (+) There are up to three WakeUp pins:
          (++)WakeUp Pin 1 on PA.00.
          (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only).
          (++)WakeUp Pin 3 on PE.06.

    *** Main and Backup Regulators configuration ***
    ================================================
    [..]
      (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
          the backup SRAM is powered from VDD which replaces the VBAT power supply to
          save battery life.

      (+) The backup SRAM is not mass erased by a tamper event. It is read
          protected to prevent confidential data, such as cryptographic private
          key, from being accessed. The backup SRAM can be erased only through
          the Flash interface when a protection level change from level 1 to
          level 0 is requested.
      -@- Refer to the description of Read protection (RDP) in the Flash
          programming manual.

        Refer to the datasheets for more details.

    *** Low Power modes configuration ***
    =====================================
    [..]
      The devices feature 3 low-power modes:
      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
      (+) Stop mode: all clocks are stopped, regulator running, regulator
          in low power mode
      (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices).

   *** Sleep mode ***
   ==================
    [..]
      (+) Entry:
          The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
              functions with
          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction

      (+) Exit:
        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
              controller (NVIC) can wake up the device from Sleep mode.

   *** Stop mode ***
   =================
    [..]
      In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
      and the HSE RC oscillators are disabled. Internal SRAM and register contents
      are preserved.
      The voltage regulator can be configured either in normal or low-power mode to minimize the consumption.

      (+) Entry:
          The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI )
             function with:
          (++) Main regulator ON or
          (++) Low Power regulator ON.
          (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or
          (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
      (+) Exit:
          (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
          (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
               when programmed in wakeup mode (the peripheral must be
               programmed in wakeup mode and the corresponding interrupt vector
               must be enabled in the NVIC).

   *** Standby mode ***
   ====================
     [..]
      The Standby mode allows to achieve the lowest power consumption. It is based
      on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
      The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
      the HSE oscillator are also switched off. SRAM and register contents are lost
      except for the RTC registers, RTC backup registers, backup SRAM and Standby
      circuitry.
      The voltage regulator is OFF.

      (+) Entry:
          (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
      (+) Exit:
          (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
               tamper event, time-stamp event, external reset in NRST pin, IWDG reset.

   *** Auto-wakeup (AWU) from low-power mode ***
   =============================================
    [..]
      The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
      Wakeup event, a tamper event, a time-stamp event, or a comparator event,
      without depending on an external interrupt (Auto-wakeup mode).

    (+) RTC auto-wakeup (AWU) from the Stop and Standby modes

      (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
            configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.

      (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
           is necessary to configure the RTC to detect the tamper or time stamp event using the
           HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.

      (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
           configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function.

    (+) Comparator auto-wakeup (AWU) from the Stop mode

      (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
           (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2U)
                 to be sensitive to to the selected edges (falling, rising or falling
                 and rising) (Interrupt or Event modes) using the EXTI_Init() function.
           (+++) Configure the comparator to generate the event.

Function Documentation

void HAL_PWR_DisableBkUpAccess ( void )

Disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Note:
If the HSE divided by 32 is used as the RTC clock, the Backup Domain Access should be kept enabled.
Return values:
None

Definition at line 116 of file stm32f3xx_hal_pwr.c.

void HAL_PWR_DisableSEVOnPend ( void )

Disables CORTEX M4 SEVONPEND bit.

Note:
Clears SEVONPEND bit of SCR register. When this bit is set, this causes WFE to wake up when an interrupt moves from inactive to pended.
Return values:
None

Definition at line 455 of file stm32f3xx_hal_pwr.c.

void HAL_PWR_DisableSleepOnExit ( void )

Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.

Note:
Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over.
Return values:
None

Definition at line 428 of file stm32f3xx_hal_pwr.c.

void HAL_PWR_DisableWakeUpPin ( uint32_t WakeUpPinx )

Disables the WakeUp PINx functionality.

Parameters:
WakeUpPinx Specifies the Power Wake-Up pin to disable. This parameter can be values of : PWR WakeUp Pins
Return values:
None

Definition at line 274 of file stm32f3xx_hal_pwr.c.

References assert_param, and IS_PWR_WAKEUP_PIN.

void HAL_PWR_EnableBkUpAccess ( void )

Enables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Note:
If the HSE divided by 32 is used as the RTC clock, the Backup Domain Access should be kept enabled.
Return values:
None

Definition at line 104 of file stm32f3xx_hal_pwr.c.

void HAL_PWR_EnableSEVOnPend ( void )

Enables CORTEX M4 SEVONPEND bit.

Note:
Sets SEVONPEND bit of SCR register. When this bit is set, this causes WFE to wake up when an interrupt moves from inactive to pended.
Return values:
None

Definition at line 442 of file stm32f3xx_hal_pwr.c.

void HAL_PWR_EnableSleepOnExit ( void )

Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.

Note:
Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over. Setting this bit is useful when the processor is expected to run only on interruptions handling.
Return values:
None

Definition at line 415 of file stm32f3xx_hal_pwr.c.

void HAL_PWR_EnableWakeUpPin ( uint32_t WakeUpPinx )

Enables the WakeUp PINx functionality.

Parameters:
WakeUpPinx Specifies the Power Wake-Up pin to enable. This parameter can be value of : PWR WakeUp Pins
Return values:
None

Definition at line 259 of file stm32f3xx_hal_pwr.c.

References assert_param, and IS_PWR_WAKEUP_PIN.

void HAL_PWR_EnterSLEEPMode | ( | uint32_t | Regulator,
 |  | uint8_t | SLEEPEntry
 | ) |  |

Enters Sleep mode.

Note:
In Sleep mode, all I/O pins keep the same state as in Run mode.
Parameters:
Regulator Specifies the regulator state in SLEEP mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
  • PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
Note:
This parameter has no effect in F3 family and is just maintained to offer full portability of other STM32 families softwares.
Parameters:
SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction. When WFI entry is used, tick interrupt have to be disabled if not desired as the interrupt wake up source. This parameter can be one of the following values:
  • PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
  • PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
Return values:
None

Definition at line 299 of file stm32f3xx_hal_pwr.c.

References assert_param, IS_PWR_SLEEP_ENTRY, and PWR_SLEEPENTRY_WFI.

void HAL_PWR_EnterSTANDBYMode ( void )

Enters STANDBY mode.

Note:
In Standby mode, all I/O pins are high impedance except for:
  • Reset pad (still available),
  • RTC alternate function pins if configured for tamper, time-stamp, RTC Alarm out, or RTC clock calibration out,
  • WKUP pins if enabled.
Return values:
None

Definition at line 391 of file stm32f3xx_hal_pwr.c.

void HAL_PWR_EnterSTOPMode | ( | uint32_t | Regulator,
 |  | uint8_t | STOPEntry
 | ) |  |

Enters STOP mode.

Note:
In Stop mode, all I/O pins keep the same state as in Run mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.
When the voltage regulator operates in low power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.
Parameters:
Regulator Specifies the regulator state in STOP mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON: STOP mode with regulator ON
  • PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
  • PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
Return values:
None

Definition at line 341 of file stm32f3xx_hal_pwr.c.

References assert_param, IS_PWR_REGULATOR, IS_PWR_STOP_ENTRY, and PWR_STOPENTRY_WFI.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USARTEx Word Length

Defines
USARTEx Word Length
USARTEx Exported Constants

Defines

#define | USART_WORDLENGTH_8B (0x00000000U)
#define | USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Define Documentation

#define USART_WORDLENGTH_8B (0x00000000U)

8-bit long USART frame

Definition at line 71 of file stm32f3xx_hal_usart_ex.h.

#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

9-bit long USART frame

Definition at line 72 of file stm32f3xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USARTEx Private Macros

Defines
USARTEx Private Macros
USARTEx

Defines

#define | USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the USART clock source.
#define | USART_MASK_COMPUTATION(__HANDLE__)
Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_USART_WORD_LENGTH(__LENGTH__)
Ensure that USART frame length is valid.

Define Documentation

#define IS_USART_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == USART_WORDLENGTH_8B) || \
                                          ((__LENGTH__) == USART_WORDLENGTH_9B))

Ensure that USART frame length is valid.

Parameters:
__LENGTH__ USART frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 296 of file stm32f3xx_hal_usart_ex.h.

Referenced by USART_SetConfig().

#define USART_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the USART clock source.

Parameters:
__HANDLE__ | specifies the USART Handle.
__CLOCKSOURCE__ | output variable.
Return values:
the USART clocking source, written in __CLOCKSOURCE__.

Definition at line 133 of file stm32f3xx_hal_usart_ex.h.

Referenced by USART_SetConfig().

#define USART_MASK_COMPUTATION ( __HANDLE__ )
Value:
do {                                                                \
  if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)           \
  {                                                                   \
     if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
     {                                                                \
        (__HANDLE__)->Mask = 0x01FFU ;                                \
     }                                                                \
     else                                                             \
     {                                                                \
        (__HANDLE__)->Mask = 0x00FFU ;                                \
     }                                                                \
  }                                                                   \
  else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)      \
  {                                                                   \
     if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
     {                                                                \
        (__HANDLE__)->Mask = 0x00FFU ;                                \
     }                                                                \
     else                                                             \
     {                                                                \
        (__HANDLE__)->Mask = 0x007FU ;                                \
     }                                                                \
  }                                                                   \
} while(0U)

Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Note:
If PCE = 1, the parity bit is not included in the data extracted by the reception API(). This masking operation is not carried out in the case of DMA transfers.
Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None,the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 254 of file stm32f3xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), and HAL_USART_TransmitReceive_IT().

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- a -

  • ABOM : CAN_InitTypeDef
  • AccessPermission : MPU_Region_InitTypeDef
  • AcquisitionMode : TSC_InitTypeDef
  • Adc1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Address : FLASH_ProcessTypeDef , UART_WakeUpTypeDef
  • AddressingMode : SMBUS_InitTypeDef , I2C_InitTypeDef
  • AddressLength : UART_WakeUpTypeDef
  • AddrEventCount : __I2C_HandleTypeDef
  • AdvancedInit : SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • AdvFeatureInit : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • AHBCLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmDateWeekDay : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmMask : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • Alternate : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • AnalogFilter : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • APB1CLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • APB2CLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AsynchPrescaler : LL_RTC_InitTypeDef
  • AudioFreq : LL_I2S_InitTypeDef , I2S_InitTypeDef
  • AutoBaudRateEnable : UART_AdvFeatureInitTypeDef
  • AutoBaudRateMode : UART_AdvFeatureInitTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutomaticOutput : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • Autoreload : LL_TIM_InitTypeDef
  • AutoReloadPreload : TIM_Base_InitTypeDef
  • AutoRetryCount : SMARTCARD_InitTypeDef
  • AWUM : CAN_InitTypeDef
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STM32F373xC HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- b -

  • BankNumber : CAN_FilterConfTypeDef
  • BaseAddress : MPU_Region_InitTypeDef
  • battery_charging_enable : PCD_InitTypeDef
  • BaudRate : IRDA_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BitOrder : LL_SPI_InitTypeDef
  • BlankingSrce : COMP_InitTypeDef
  • BlockLength : SMARTCARD_InitTypeDef
  • BreakPolarity : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakState : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BREErrorBitGen : CEC_InitTypeDef
  • BRERxStop : CEC_InitTypeDef
  • BroadcastMsgNoErrorBitGen : CEC_InitTypeDef
  • BS1 : CAN_InitTypeDef
  • BS2 : CAN_InitTypeDef
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STM32F373xC HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- c -

  • CecClockSelection : RCC_PeriphCLKInitTypeDef
  • Channel : ADC_ChannelConfTypeDef , TIM_HandleTypeDef , ADC_AnalogWDGConfTypeDef
  • ChannelIndex : __DMA_HandleTypeDef
  • ChannelIOs : TSC_InitTypeDef , TSC_IOConfigTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SPI_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef
  • CLKPolarity : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockOutput : LL_USART_ClockInitTypeDef
  • ClockPhase : LL_SPI_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPolarity : TIM_ClockConfigTypeDef , LL_SPI_InitTypeDef , LL_I2S_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPrescaler : TIM_ClockConfigTypeDef
  • ClockSource : I2S_InitTypeDef , TIM_ClockConfigTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • CommonMode : SDADC_ConfParamTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • CommutationDelay : LL_TIM_HALLSENSOR_InitTypeDef
  • CompareValue : LL_TIM_OC_InitTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
  • ContinuousMode : LL_ADC_REG_InitTypeDef
  • Counter : WWDG_InitTypeDef
  • CounterMode : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • CPOL : I2S_InitTypeDef
  • CRCCalculation : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • CRCLength : CRC_InitTypeDef , SPI_InitTypeDef
  • CRCPoly : LL_SPI_InitTypeDef
  • CRCPolynomial : SPI_InitTypeDef
  • CRCSize : __SPI_HandleTypeDef
  • CTPulseHighLength : TSC_InitTypeDef
  • CTPulseLowLength : TSC_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- d -

  • DAC_OutputBuffer : DAC_ChannelConfTypeDef
  • DAC_OutputSwitch : DAC_ChannelConfTypeDef
  • DAC_Trigger : DAC_ChannelConfTypeDef
  • Data : CanTxMsgTypeDef , CanRxMsgTypeDef , FLASH_ProcessTypeDef
  • DATAAddress : FLASH_OBProgramInitTypeDef
  • DataAlign : ADC_InitTypeDef
  • DataAlignment : LL_ADC_InitTypeDef
  • DATAData : FLASH_OBProgramInitTypeDef
  • DataFormat : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • DataInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • DataRemaining : FLASH_ProcessTypeDef
  • DataSize : SPI_InitTypeDef
  • DataWidth : LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • Date : RTC_DateTypeDef
  • Day : LL_RTC_DateTypeDef
  • DayLightSaving : RTC_TimeTypeDef
  • DeadTime : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • DefaultInitValueUse : CRC_InitTypeDef
  • DefaultPolynomialUse : CRC_InitTypeDef
  • dev_endpoints : PCD_InitTypeDef
  • DigitalFilter : LL_I2C_InitTypeDef
  • Direction : DMA_InitTypeDef , SPI_InitTypeDef , LL_DMA_InitTypeDef
  • DisableExec : MPU_Region_InitTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • DLC : CanTxMsgTypeDef , CanRxMsgTypeDef
  • DMA_Handle : __ADC_HandleTypeDef
  • DMA_Handle1 : __DAC_HandleTypeDef
  • DMA_Handle2 : __DAC_HandleTypeDef
  • DmaBaseAddress : __DMA_HandleTypeDef
  • DMADisableonRxError : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • DMATransfer : LL_ADC_REG_InitTypeDef
  • doublebuffer : PCD_EPTypeDef
  • DualAddressMode : SMBUS_InitTypeDef , I2C_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- e -

  • Enable : MPU_Region_InitTypeDef
  • EncoderMode : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • ep0_mps : PCD_InitTypeDef
  • ErrorCode : __DAC_HandleTypeDef , SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __DMA_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , __ADC_HandleTypeDef , SMARTCARD_HandleTypeDef , SDADC_HandleTypeDef , IRDA_HandleTypeDef , FLASH_ProcessTypeDef , __I2C_HandleTypeDef , CAN_HandleTypeDef , I2S_HandleTypeDef , CEC_HandleTypeDef
  • EWIMode : WWDG_InitTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExtId : CanTxMsgTypeDef , CanRxMsgTypeDef
  • ExtTriggerEdge : SDADC_HandleTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- f -

  • FastConversionMode : SDADC_InitTypeDef
  • FIFONumber : CanRxMsgTypeDef
  • Filter : RTC_TamperTypeDef
  • FilterActivation : CAN_FilterConfTypeDef
  • FilterFIFOAssignment : CAN_FilterConfTypeDef
  • FilterIdHigh : CAN_FilterConfTypeDef
  • FilterIdLow : CAN_FilterConfTypeDef
  • FilterMaskIdHigh : CAN_FilterConfTypeDef
  • FilterMaskIdLow : CAN_FilterConfTypeDef
  • FilterMode : CAN_FilterConfTypeDef
  • FilterNumber : CAN_FilterConfTypeDef
  • FilterScale : CAN_FilterConfTypeDef
  • FirstBit : SPI_InitTypeDef
  • FMI : CanRxMsgTypeDef
  • FullDuplexMode : I2S_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- g -

  • Gain : SDADC_ConfParamTypeDef
  • GeneralCallMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • GeneratingPolynomial : CRC_InitTypeDef
  • gState : SMARTCARD_HandleTypeDef , CEC_HandleTypeDef , UART_HandleTypeDef , IRDA_HandleTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- h -

  • HardwareFlowControl : LL_USART_InitTypeDef
  • HCLK_Frequency : LL_RCC_ClocksTypeDef
  • hdma : TIM_HandleTypeDef , SDADC_HandleTypeDef
  • hdmarx : SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __I2C_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef
  • hdmatx : __SPI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , __I2C_HandleTypeDef , SMARTCARD_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef
  • HourFormat : RTC_InitTypeDef , LL_RTC_InitTypeDef
  • Hours : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • HSEPredivValue : RCC_OscInitTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HwFlowCtl : UART_InitTypeDef
  • Hysteresis : COMP_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- i -

  • I2c1ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c2ClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC1Filter : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Polarity : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Prescaler : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • ICActiveInput : LL_TIM_IC_InitTypeDef
  • ICFilter : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPolarity : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • IDE : CanTxMsgTypeDef , CanRxMsgTypeDef
  • IdleLowPowerMode : SDADC_InitTypeDef
  • IN_ep : PCD_HandleTypeDef
  • Init : __ADC_HandleTypeDef , CAN_HandleTypeDef , CEC_HandleTypeDef , COMP_HandleTypeDef , CRC_HandleTypeDef , __DMA_HandleTypeDef , __I2C_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , IWDG_HandleTypeDef , PCD_HandleTypeDef , RTC_HandleTypeDef , USART_HandleTypeDef , SDADC_HandleTypeDef , SMARTCARD_HandleTypeDef , SMBUS_HandleTypeDef , __SPI_HandleTypeDef , TIM_HandleTypeDef , TSC_HandleTypeDef , UART_HandleTypeDef , WWDG_HandleTypeDef
  • InitValue : CRC_InitTypeDef
  • InjConvRemaining : SDADC_HandleTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedChannelsNbr : SDADC_HandleTypeDef
  • InjectedContMode : SDADC_HandleTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedMultimode : SDADC_HandleTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InjectedTrigger : SDADC_HandleTypeDef
  • InputDataFormat : CRC_HandleTypeDef
  • InputDataInversionMode : CRC_InitTypeDef
  • InputHysteresis : LL_COMP_InitTypeDef
  • InputMinus : LL_COMP_InitTypeDef
  • InputMode : SDADC_ConfParamTypeDef
  • InputPlus : LL_COMP_InitTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : PCD_HandleTypeDef , IWDG_HandleTypeDef , TSC_HandleTypeDef , CAN_HandleTypeDef , TIM_HandleTypeDef , CEC_HandleTypeDef , I2S_HandleTypeDef , __ADC_HandleTypeDef , SMARTCARD_HandleTypeDef , USART_HandleTypeDef , WWDG_HandleTypeDef , SMBUS_HandleTypeDef , SDADC_HandleTypeDef , IRDA_HandleTypeDef , RTC_HandleTypeDef , __DAC_HandleTypeDef , __DMA_HandleTypeDef , __I2C_HandleTypeDef , CRC_HandleTypeDef , __SPI_HandleTypeDef , COMP_HandleTypeDef , UART_HandleTypeDef
  • InvertingInput : COMP_InitTypeDef
  • IODefaultMode : TSC_InitTypeDef
  • is_in : PCD_EPTypeDef
  • is_stall : PCD_EPTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • IsShareable : MPU_Region_InitTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- l -

  • LastBitClockPulse : LL_USART_ClockInitTypeDef
  • LBPEErrorBitGen : CEC_InitTypeDef
  • Line_0_31 : LL_EXTI_InitTypeDef
  • LineCommand : LL_EXTI_InitTypeDef
  • ListenMode : CEC_InitTypeDef
  • Lock : CEC_HandleTypeDef , IRDA_HandleTypeDef , PCD_HandleTypeDef , USART_HandleTypeDef , COMP_HandleTypeDef , TSC_HandleTypeDef , TIM_HandleTypeDef , __SPI_HandleTypeDef , RTC_HandleTypeDef , SMARTCARD_HandleTypeDef , CRC_HandleTypeDef , SMBUS_HandleTypeDef , __DAC_HandleTypeDef , I2S_HandleTypeDef , __I2C_HandleTypeDef , FLASH_ProcessTypeDef , UART_HandleTypeDef , __ADC_HandleTypeDef , __DMA_HandleTypeDef , CAN_HandleTypeDef
  • LockLevel : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • low_power_enable : PCD_InitTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef
  • lpm_enable : PCD_InitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- m -

  • Mask : IRDA_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef
  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • MaxCountInterrupt : TSC_InitTypeDef
  • MaxCountValue : TSC_InitTypeDef
  • maxpacket : PCD_EPTypeDef
  • MCLKOutput : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • MemoryOrM2MDstAddress : LL_DMA_InitTypeDef
  • MemoryOrM2MDstDataSize : LL_DMA_InitTypeDef
  • MemoryOrM2MDstIncMode : LL_DMA_InitTypeDef
  • Minutes : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • Mode : __I2C_HandleTypeDef , GPIO_InitTypeDef , I2S_InitTypeDef , COMP_InitTypeDef , USART_InitTypeDef , LL_GPIO_InitTypeDef , CAN_InitTypeDef , SPI_InitTypeDef , LL_I2S_InitTypeDef , LL_SPI_InitTypeDef , IRDA_InitTypeDef , LL_EXTI_InitTypeDef , LL_DMA_InitTypeDef , DMA_InitTypeDef , PWR_PVDTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • Month : RTC_DateTypeDef , LL_RTC_DateTypeDef
  • MSBFirst : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- n -

  • NACKEnable : SMARTCARD_InitTypeDef
  • NART : CAN_InitTypeDef
  • NbData : LL_DMA_InitTypeDef
  • NbPages : FLASH_EraseInitTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NonInvertingInput : COMP_InitTypeDef
  • NoStretchMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • NSS : SPI_InitTypeDef , LL_SPI_InitTypeDef
  • NSSPMode : SPI_InitTypeDef
  • num : PCD_EPTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

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  • u
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  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- o -

  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , LL_TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNState : LL_TIM_OC_InitTypeDef
  • OCPolarity : TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef , TIM_OC_InitTypeDef
  • OCState : LL_TIM_OC_InitTypeDef
  • Offset : SDADC_ConfParamTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OneBitSampling : SMARTCARD_InitTypeDef , UART_InitTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OSSIState : LL_TIM_BDTR_InitTypeDef
  • OSSRState : LL_TIM_BDTR_InitTypeDef
  • OUT_ep : PCD_HandleTypeDef
  • Output : COMP_InitTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputBuffer : LL_DAC_InitTypeDef
  • OutputDataInversionMode : CRC_InitTypeDef
  • OutputPol : COMP_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutputPolarity : LL_COMP_InitTypeDef
  • OutputSelection : LL_COMP_InitTypeDef
  • OutputType : LL_GPIO_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • OverrunDisable : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • OverSampling : LL_USART_InitTypeDef , UART_InitTypeDef
  • OwnAddress : CEC_InitTypeDef
  • OwnAddress1 : I2C_InitTypeDef , SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddress2Masks : SMBUS_InitTypeDef , I2C_InitTypeDef
  • OwnAddrSize : LL_I2C_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- p -

  • PacketErrorCheckMode : SMBUS_InitTypeDef
  • PageAddress : FLASH_EraseInitTypeDef
  • Parent : __DMA_HandleTypeDef
  • Parity : IRDA_InitTypeDef , LL_USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • pBuffPtr : __I2C_HandleTypeDef , SMBUS_HandleTypeDef
  • PCLK1_Frequency : LL_RCC_ClocksTypeDef
  • PCLK2_Frequency : LL_RCC_ClocksTypeDef
  • pData : PCD_HandleTypeDef
  • Period : TIM_Base_InitTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeripheralMode : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PeriphOrM2MSrcAddress : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcDataSize : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcIncMode : LL_DMA_InitTypeDef
  • phy_itface : PCD_InitTypeDef
  • Pin : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLLMUL : RCC_PLLInitTypeDef
  • PLLMul : LL_UTILS_PLLInitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • pmaaddr0 : PCD_EPTypeDef
  • pmaaddr1 : PCD_EPTypeDef
  • pmaadress : PCD_EPTypeDef
  • PowerMode : IRDA_InitTypeDef , LL_COMP_InitTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • Prediv : LL_UTILS_PLLInitTypeDef
  • Prescaler : IRDA_InitTypeDef , CAN_InitTypeDef , IWDG_InitTypeDef , SMARTCARD_InitTypeDef , TIM_Base_InitTypeDef , LL_TIM_InitTypeDef , WWDG_InitTypeDef
  • PreviousState : __I2C_HandleTypeDef , SMBUS_HandleTypeDef
  • Priority : DMA_InitTypeDef , LL_DMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • pRx1Msg : CAN_HandleTypeDef
  • pRxBuffPtr : UART_HandleTypeDef , __SPI_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , USART_HandleTypeDef
  • pRxMsg : CAN_HandleTypeDef
  • pTxBuffPtr : CEC_HandleTypeDef , USART_HandleTypeDef , UART_HandleTypeDef , __SPI_HandleTypeDef , SMARTCARD_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef
  • pTxMsg : CAN_HandleTypeDef
  • Pull : LL_GPIO_InitTypeDef , GPIO_InitTypeDef
  • Pulse : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • PulseGeneratorPrescaler : TSC_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
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  • d
  • e
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

  • Rank : ADC_ChannelConfTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • ReferenceVoltage : SDADC_InitTypeDef
  • RegularContMode : SDADC_HandleTypeDef
  • RegularMultimode : SDADC_HandleTypeDef
  • RegularTrigger : SDADC_HandleTypeDef
  • Reload : IWDG_InitTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • RFLM : CAN_InitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RTR : CanTxMsgTypeDef , CanRxMsgTypeDef
  • RxBuffer : CEC_InitTypeDef
  • RxISR : __SPI_HandleTypeDef
  • RxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • RxState : CEC_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • RxXferCount : IRDA_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef , I2S_HandleTypeDef
  • RxXferSize : SMARTCARD_HandleTypeDef , CEC_HandleTypeDef , USART_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- s -

  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingIOs : TSC_InitTypeDef , TSC_IOConfigTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • SdadcClockSelection : RCC_PeriphCLKInitTypeDef
  • SecondFraction : RTC_TimeTypeDef
  • Seconds : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • SequencerDiscont : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SequencerLength : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SequencersScanMode : LL_ADC_InitTypeDef
  • Setup : PCD_HandleTypeDef
  • ShieldIOs : TSC_InitTypeDef , TSC_IOConfigTypeDef
  • SignalFreeTime : CEC_InitTypeDef
  • SignalFreeTimeOption : CEC_InitTypeDef
  • Size : MPU_Region_InitTypeDef
  • SJW : CAN_InitTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef
  • SlowClockMode : SDADC_InitTypeDef
  • SMBusTimeout : SMBUS_InitTypeDef
  • Sof_enable : PCD_InitTypeDef
  • Speed : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • speed : PCD_InitTypeDef
  • SpreadSpectrum : TSC_InitTypeDef
  • SpreadSpectrumDeviation : TSC_InitTypeDef
  • SpreadSpectrumPrescaler : TSC_InitTypeDef
  • Standard : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • State : __ADC_HandleTypeDef , CAN_HandleTypeDef , COMP_HandleTypeDef , CRC_HandleTypeDef , __DAC_HandleTypeDef , SMBUS_HandleTypeDef , __I2C_HandleTypeDef , I2S_HandleTypeDef , PCD_HandleTypeDef , __SPI_HandleTypeDef , SDADC_HandleTypeDef , TIM_HandleTypeDef , TSC_HandleTypeDef , USART_HandleTypeDef , RTC_HandleTypeDef , __DMA_HandleTypeDef
  • StdId : CanTxMsgTypeDef , CanRxMsgTypeDef
  • StopBits : USART_InitTypeDef , LL_USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • Swap : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • SynchPrescaler : LL_RTC_InitTypeDef
  • SynchroPinPolarity : TSC_InitTypeDef
  • SYSCLK_Frequency : LL_RCC_ClocksTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
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  • d
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- t -

  • Tamper : RTC_TamperTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • TimeFormat : LL_RTC_TimeTypeDef , RTC_TimeTypeDef
  • TimeOutEnable : SMARTCARD_InitTypeDef
  • TimeOutValue : SMARTCARD_InitTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef
  • Timing : I2C_InitTypeDef , SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • Tolerance : CEC_InitTypeDef
  • TransferDirection : LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • TrigAuto : LL_ADC_INJ_InitTypeDef
  • Trigger : RTC_TamperTypeDef , LL_EXTI_InitTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerMode : COMP_InitTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriggerSource : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef , LL_DAC_InitTypeDef
  • TTCM : CAN_InitTypeDef
  • TXFP : CAN_InitTypeDef
  • TxISR : __SPI_HandleTypeDef
  • TxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • TxXferCount : USART_HandleTypeDef , __SPI_HandleTypeDef , CEC_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , I2S_HandleTypeDef , UART_HandleTypeDef
  • TxXferSize : UART_HandleTypeDef , __SPI_HandleTypeDef , IRDA_HandleTypeDef , I2S_HandleTypeDef , SMARTCARD_HandleTypeDef , USART_HandleTypeDef
  • type : PCD_EPTypeDef
  • TypeAcknowledge : LL_I2C_InitTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- u -

  • Usart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart3ClockSelection : RCC_PeriphCLKInitTypeDef
  • USB_Address : PCD_HandleTypeDef
  • USBClockSelection : RCC_PeriphCLKInitTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
  • a
  • b
  • c
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- w -

  • WakeUpEvent : UART_WakeUpTypeDef
  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WaveAutoGeneration : LL_DAC_InitTypeDef
  • WaveAutoGenerationConfig : LL_DAC_InitTypeDef
  • WeekDay : RTC_DateTypeDef , LL_RTC_DateTypeDef
  • Window : IWDG_InitTypeDef , WWDG_InitTypeDef
  • WindowMode : COMP_InitTypeDef
  • WordLength : USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , IRDA_InitTypeDef
  • WRPPage : FLASH_OBProgramInitTypeDef
  • WRPState : FLASH_OBProgramInitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
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  • b
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- x -

  • xfer_buff : PCD_EPTypeDef
  • xfer_count : PCD_EPTypeDef
  • xfer_len : PCD_EPTypeDef
  • XferAbortCallback : __DMA_HandleTypeDef
  • XferCount : __I2C_HandleTypeDef , SMBUS_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferISR : __I2C_HandleTypeDef
  • XferOptions : SMBUS_HandleTypeDef , __I2C_HandleTypeDef
  • XferSize : SMBUS_HandleTypeDef , __I2C_HandleTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- y -

  • Year : RTC_DateTypeDef , LL_RTC_DateTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • Variables
  • a
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- a -

  • ABOM : CAN_InitTypeDef
  • AccessPermission : MPU_Region_InitTypeDef
  • AcquisitionMode : TSC_InitTypeDef
  • Adc1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Address : FLASH_ProcessTypeDef , UART_WakeUpTypeDef
  • AddressingMode : SMBUS_InitTypeDef , I2C_InitTypeDef
  • AddressLength : UART_WakeUpTypeDef
  • AddrEventCount : __I2C_HandleTypeDef
  • AdvancedInit : SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • AdvFeatureInit : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • AHBCLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmDateWeekDay : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmMask : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • Alternate : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • AnalogFilter : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • APB1CLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • APB2CLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AsynchPrescaler : LL_RTC_InitTypeDef
  • AudioFreq : LL_I2S_InitTypeDef , I2S_InitTypeDef
  • AutoBaudRateEnable : UART_AdvFeatureInitTypeDef
  • AutoBaudRateMode : UART_AdvFeatureInitTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutomaticOutput : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • Autoreload : LL_TIM_InitTypeDef
  • AutoReloadPreload : TIM_Base_InitTypeDef
  • AutoRetryCount : SMARTCARD_InitTypeDef
  • AWUM : CAN_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • a
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- b -

  • BankNumber : CAN_FilterConfTypeDef
  • BaseAddress : MPU_Region_InitTypeDef
  • battery_charging_enable : PCD_InitTypeDef
  • BaudRate : IRDA_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BitOrder : LL_SPI_InitTypeDef
  • BlankingSrce : COMP_InitTypeDef
  • BlockLength : SMARTCARD_InitTypeDef
  • BreakPolarity : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakState : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BREErrorBitGen : CEC_InitTypeDef
  • BRERxStop : CEC_InitTypeDef
  • BroadcastMsgNoErrorBitGen : CEC_InitTypeDef
  • BS1 : CAN_InitTypeDef
  • BS2 : CAN_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • Variables
  • a
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- c -

  • CecClockSelection : RCC_PeriphCLKInitTypeDef
  • Channel : ADC_ChannelConfTypeDef , TIM_HandleTypeDef , ADC_AnalogWDGConfTypeDef
  • ChannelIndex : __DMA_HandleTypeDef
  • ChannelIOs : TSC_InitTypeDef , TSC_IOConfigTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SPI_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef
  • CLKPolarity : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockOutput : LL_USART_ClockInitTypeDef
  • ClockPhase : LL_SPI_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPolarity : TIM_ClockConfigTypeDef , LL_SPI_InitTypeDef , LL_I2S_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPrescaler : TIM_ClockConfigTypeDef
  • ClockSource : I2S_InitTypeDef , TIM_ClockConfigTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • CommonMode : SDADC_ConfParamTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • CommutationDelay : LL_TIM_HALLSENSOR_InitTypeDef
  • CompareValue : LL_TIM_OC_InitTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
  • ContinuousMode : LL_ADC_REG_InitTypeDef
  • Counter : WWDG_InitTypeDef
  • CounterMode : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • CPOL : I2S_InitTypeDef
  • CRCCalculation : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • CRCLength : CRC_InitTypeDef , SPI_InitTypeDef
  • CRCPoly : LL_SPI_InitTypeDef
  • CRCPolynomial : SPI_InitTypeDef
  • CRCSize : __SPI_HandleTypeDef
  • CTPulseHighLength : TSC_InitTypeDef
  • CTPulseLowLength : TSC_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
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- d -

  • DAC_OutputBuffer : DAC_ChannelConfTypeDef
  • DAC_OutputSwitch : DAC_ChannelConfTypeDef
  • DAC_Trigger : DAC_ChannelConfTypeDef
  • Data : CanTxMsgTypeDef , CanRxMsgTypeDef , FLASH_ProcessTypeDef
  • DATAAddress : FLASH_OBProgramInitTypeDef
  • DataAlign : ADC_InitTypeDef
  • DataAlignment : LL_ADC_InitTypeDef
  • DATAData : FLASH_OBProgramInitTypeDef
  • DataFormat : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • DataInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • DataRemaining : FLASH_ProcessTypeDef
  • DataSize : SPI_InitTypeDef
  • DataWidth : LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • Date : RTC_DateTypeDef
  • Day : LL_RTC_DateTypeDef
  • DayLightSaving : RTC_TimeTypeDef
  • DeadTime : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • DefaultInitValueUse : CRC_InitTypeDef
  • DefaultPolynomialUse : CRC_InitTypeDef
  • dev_endpoints : PCD_InitTypeDef
  • DigitalFilter : LL_I2C_InitTypeDef
  • Direction : DMA_InitTypeDef , SPI_InitTypeDef , LL_DMA_InitTypeDef
  • DisableExec : MPU_Region_InitTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • DLC : CanTxMsgTypeDef , CanRxMsgTypeDef
  • DMA_Handle : __ADC_HandleTypeDef
  • DMA_Handle1 : __DAC_HandleTypeDef
  • DMA_Handle2 : __DAC_HandleTypeDef
  • DmaBaseAddress : __DMA_HandleTypeDef
  • DMADisableonRxError : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • DMATransfer : LL_ADC_REG_InitTypeDef
  • doublebuffer : PCD_EPTypeDef
  • DualAddressMode : SMBUS_InitTypeDef , I2C_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- e -

  • Enable : MPU_Region_InitTypeDef
  • EncoderMode : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • ep0_mps : PCD_InitTypeDef
  • ErrorCode : __DAC_HandleTypeDef , SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __DMA_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , __ADC_HandleTypeDef , SMARTCARD_HandleTypeDef , SDADC_HandleTypeDef , IRDA_HandleTypeDef , FLASH_ProcessTypeDef , __I2C_HandleTypeDef , CAN_HandleTypeDef , I2S_HandleTypeDef , CEC_HandleTypeDef
  • EWIMode : WWDG_InitTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExtId : CanTxMsgTypeDef , CanRxMsgTypeDef
  • ExtTriggerEdge : SDADC_HandleTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
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- f -

  • FastConversionMode : SDADC_InitTypeDef
  • FIFONumber : CanRxMsgTypeDef
  • Filter : RTC_TamperTypeDef
  • FilterActivation : CAN_FilterConfTypeDef
  • FilterFIFOAssignment : CAN_FilterConfTypeDef
  • FilterIdHigh : CAN_FilterConfTypeDef
  • FilterIdLow : CAN_FilterConfTypeDef
  • FilterMaskIdHigh : CAN_FilterConfTypeDef
  • FilterMaskIdLow : CAN_FilterConfTypeDef
  • FilterMode : CAN_FilterConfTypeDef
  • FilterNumber : CAN_FilterConfTypeDef
  • FilterScale : CAN_FilterConfTypeDef
  • FirstBit : SPI_InitTypeDef
  • FMI : CanRxMsgTypeDef
  • FullDuplexMode : I2S_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • Variables
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  • Gain : SDADC_ConfParamTypeDef
  • GeneralCallMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • GeneratingPolynomial : CRC_InitTypeDef
  • gState : SMARTCARD_HandleTypeDef , CEC_HandleTypeDef , UART_HandleTypeDef , IRDA_HandleTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • Variables
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- h -

  • HardwareFlowControl : LL_USART_InitTypeDef
  • HCLK_Frequency : LL_RCC_ClocksTypeDef
  • hdma : TIM_HandleTypeDef , SDADC_HandleTypeDef
  • hdmarx : SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __I2C_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef
  • hdmatx : __SPI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , __I2C_HandleTypeDef , SMARTCARD_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef
  • HourFormat : RTC_InitTypeDef , LL_RTC_InitTypeDef
  • Hours : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • HSEPredivValue : RCC_OscInitTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HwFlowCtl : UART_InitTypeDef
  • Hysteresis : COMP_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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  • I2c1ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c2ClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC1Filter : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Polarity : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Prescaler : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • ICActiveInput : LL_TIM_IC_InitTypeDef
  • ICFilter : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPolarity : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • IDE : CanTxMsgTypeDef , CanRxMsgTypeDef
  • IdleLowPowerMode : SDADC_InitTypeDef
  • IN_ep : PCD_HandleTypeDef
  • Init : __ADC_HandleTypeDef , CAN_HandleTypeDef , CEC_HandleTypeDef , COMP_HandleTypeDef , CRC_HandleTypeDef , __DMA_HandleTypeDef , __I2C_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , IWDG_HandleTypeDef , PCD_HandleTypeDef , RTC_HandleTypeDef , USART_HandleTypeDef , SDADC_HandleTypeDef , SMARTCARD_HandleTypeDef , SMBUS_HandleTypeDef , __SPI_HandleTypeDef , TIM_HandleTypeDef , TSC_HandleTypeDef , UART_HandleTypeDef , WWDG_HandleTypeDef
  • InitValue : CRC_InitTypeDef
  • InjConvRemaining : SDADC_HandleTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedChannelsNbr : SDADC_HandleTypeDef
  • InjectedContMode : SDADC_HandleTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedMultimode : SDADC_HandleTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InjectedTrigger : SDADC_HandleTypeDef
  • InputDataFormat : CRC_HandleTypeDef
  • InputDataInversionMode : CRC_InitTypeDef
  • InputHysteresis : LL_COMP_InitTypeDef
  • InputMinus : LL_COMP_InitTypeDef
  • InputMode : SDADC_ConfParamTypeDef
  • InputPlus : LL_COMP_InitTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : PCD_HandleTypeDef , IWDG_HandleTypeDef , TSC_HandleTypeDef , CAN_HandleTypeDef , TIM_HandleTypeDef , CEC_HandleTypeDef , I2S_HandleTypeDef , __ADC_HandleTypeDef , SMARTCARD_HandleTypeDef , USART_HandleTypeDef , WWDG_HandleTypeDef , SMBUS_HandleTypeDef , SDADC_HandleTypeDef , IRDA_HandleTypeDef , RTC_HandleTypeDef , __DAC_HandleTypeDef , __DMA_HandleTypeDef , __I2C_HandleTypeDef , CRC_HandleTypeDef , __SPI_HandleTypeDef , COMP_HandleTypeDef , UART_HandleTypeDef
  • InvertingInput : COMP_InitTypeDef
  • IODefaultMode : TSC_InitTypeDef
  • is_in : PCD_EPTypeDef
  • is_stall : PCD_EPTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • IsShareable : MPU_Region_InitTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • Variables
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- l -

  • LastBitClockPulse : LL_USART_ClockInitTypeDef
  • LBPEErrorBitGen : CEC_InitTypeDef
  • Line_0_31 : LL_EXTI_InitTypeDef
  • LineCommand : LL_EXTI_InitTypeDef
  • ListenMode : CEC_InitTypeDef
  • Lock : CEC_HandleTypeDef , IRDA_HandleTypeDef , PCD_HandleTypeDef , USART_HandleTypeDef , COMP_HandleTypeDef , TSC_HandleTypeDef , TIM_HandleTypeDef , __SPI_HandleTypeDef , RTC_HandleTypeDef , SMARTCARD_HandleTypeDef , CRC_HandleTypeDef , SMBUS_HandleTypeDef , __DAC_HandleTypeDef , I2S_HandleTypeDef , __I2C_HandleTypeDef , FLASH_ProcessTypeDef , UART_HandleTypeDef , __ADC_HandleTypeDef , __DMA_HandleTypeDef , CAN_HandleTypeDef
  • LockLevel : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • low_power_enable : PCD_InitTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef
  • lpm_enable : PCD_InitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • Variables
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  • Mask : IRDA_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef
  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • MaxCountInterrupt : TSC_InitTypeDef
  • MaxCountValue : TSC_InitTypeDef
  • maxpacket : PCD_EPTypeDef
  • MCLKOutput : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • MemoryOrM2MDstAddress : LL_DMA_InitTypeDef
  • MemoryOrM2MDstDataSize : LL_DMA_InitTypeDef
  • MemoryOrM2MDstIncMode : LL_DMA_InitTypeDef
  • Minutes : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • Mode : __I2C_HandleTypeDef , GPIO_InitTypeDef , I2S_InitTypeDef , COMP_InitTypeDef , USART_InitTypeDef , LL_GPIO_InitTypeDef , CAN_InitTypeDef , SPI_InitTypeDef , LL_I2S_InitTypeDef , LL_SPI_InitTypeDef , IRDA_InitTypeDef , LL_EXTI_InitTypeDef , LL_DMA_InitTypeDef , DMA_InitTypeDef , PWR_PVDTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • Month : RTC_DateTypeDef , LL_RTC_DateTypeDef
  • MSBFirst : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • NACKEnable : SMARTCARD_InitTypeDef
  • NART : CAN_InitTypeDef
  • NbData : LL_DMA_InitTypeDef
  • NbPages : FLASH_EraseInitTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NonInvertingInput : COMP_InitTypeDef
  • NoStretchMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • NSS : SPI_InitTypeDef , LL_SPI_InitTypeDef
  • NSSPMode : SPI_InitTypeDef
  • num : PCD_EPTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- o -

  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , LL_TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNState : LL_TIM_OC_InitTypeDef
  • OCPolarity : TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef , TIM_OC_InitTypeDef
  • OCState : LL_TIM_OC_InitTypeDef
  • Offset : SDADC_ConfParamTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OneBitSampling : SMARTCARD_InitTypeDef , UART_InitTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OSSIState : LL_TIM_BDTR_InitTypeDef
  • OSSRState : LL_TIM_BDTR_InitTypeDef
  • OUT_ep : PCD_HandleTypeDef
  • Output : COMP_InitTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputBuffer : LL_DAC_InitTypeDef
  • OutputDataInversionMode : CRC_InitTypeDef
  • OutputPol : COMP_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutputPolarity : LL_COMP_InitTypeDef
  • OutputSelection : LL_COMP_InitTypeDef
  • OutputType : LL_GPIO_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • OverrunDisable : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • OverSampling : LL_USART_InitTypeDef , UART_InitTypeDef
  • OwnAddress : CEC_InitTypeDef
  • OwnAddress1 : I2C_InitTypeDef , SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddress2Masks : SMBUS_InitTypeDef , I2C_InitTypeDef
  • OwnAddrSize : LL_I2C_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- p -

  • PacketErrorCheckMode : SMBUS_InitTypeDef
  • PageAddress : FLASH_EraseInitTypeDef
  • Parent : __DMA_HandleTypeDef
  • Parity : IRDA_InitTypeDef , LL_USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • pBuffPtr : __I2C_HandleTypeDef , SMBUS_HandleTypeDef
  • PCLK1_Frequency : LL_RCC_ClocksTypeDef
  • PCLK2_Frequency : LL_RCC_ClocksTypeDef
  • pData : PCD_HandleTypeDef
  • Period : TIM_Base_InitTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeripheralMode : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PeriphOrM2MSrcAddress : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcDataSize : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcIncMode : LL_DMA_InitTypeDef
  • phy_itface : PCD_InitTypeDef
  • Pin : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLLMUL : RCC_PLLInitTypeDef
  • PLLMul : LL_UTILS_PLLInitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • pmaaddr0 : PCD_EPTypeDef
  • pmaaddr1 : PCD_EPTypeDef
  • pmaadress : PCD_EPTypeDef
  • PowerMode : IRDA_InitTypeDef , LL_COMP_InitTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • Prediv : LL_UTILS_PLLInitTypeDef
  • Prescaler : IRDA_InitTypeDef , CAN_InitTypeDef , IWDG_InitTypeDef , SMARTCARD_InitTypeDef , TIM_Base_InitTypeDef , LL_TIM_InitTypeDef , WWDG_InitTypeDef
  • PreviousState : __I2C_HandleTypeDef , SMBUS_HandleTypeDef
  • Priority : DMA_InitTypeDef , LL_DMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • pRx1Msg : CAN_HandleTypeDef
  • pRxBuffPtr : UART_HandleTypeDef , __SPI_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , USART_HandleTypeDef
  • pRxMsg : CAN_HandleTypeDef
  • pTxBuffPtr : CEC_HandleTypeDef , USART_HandleTypeDef , UART_HandleTypeDef , __SPI_HandleTypeDef , SMARTCARD_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef
  • pTxMsg : CAN_HandleTypeDef
  • Pull : LL_GPIO_InitTypeDef , GPIO_InitTypeDef
  • Pulse : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • PulseGeneratorPrescaler : TSC_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- r -

  • Rank : ADC_ChannelConfTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • ReferenceVoltage : SDADC_InitTypeDef
  • RegularContMode : SDADC_HandleTypeDef
  • RegularMultimode : SDADC_HandleTypeDef
  • RegularTrigger : SDADC_HandleTypeDef
  • Reload : IWDG_InitTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • RFLM : CAN_InitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RTR : CanTxMsgTypeDef , CanRxMsgTypeDef
  • RxBuffer : CEC_InitTypeDef
  • RxISR : __SPI_HandleTypeDef
  • RxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • RxState : CEC_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • RxXferCount : IRDA_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef , I2S_HandleTypeDef
  • RxXferSize : SMARTCARD_HandleTypeDef , CEC_HandleTypeDef , USART_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- s -

  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingIOs : TSC_InitTypeDef , TSC_IOConfigTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • SdadcClockSelection : RCC_PeriphCLKInitTypeDef
  • SecondFraction : RTC_TimeTypeDef
  • Seconds : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • SequencerDiscont : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SequencerLength : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SequencersScanMode : LL_ADC_InitTypeDef
  • Setup : PCD_HandleTypeDef
  • ShieldIOs : TSC_InitTypeDef , TSC_IOConfigTypeDef
  • SignalFreeTime : CEC_InitTypeDef
  • SignalFreeTimeOption : CEC_InitTypeDef
  • Size : MPU_Region_InitTypeDef
  • SJW : CAN_InitTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef
  • SlowClockMode : SDADC_InitTypeDef
  • SMBusTimeout : SMBUS_InitTypeDef
  • Sof_enable : PCD_InitTypeDef
  • Speed : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • speed : PCD_InitTypeDef
  • SpreadSpectrum : TSC_InitTypeDef
  • SpreadSpectrumDeviation : TSC_InitTypeDef
  • SpreadSpectrumPrescaler : TSC_InitTypeDef
  • Standard : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • State : __ADC_HandleTypeDef , CAN_HandleTypeDef , COMP_HandleTypeDef , CRC_HandleTypeDef , __DAC_HandleTypeDef , SMBUS_HandleTypeDef , __I2C_HandleTypeDef , I2S_HandleTypeDef , PCD_HandleTypeDef , __SPI_HandleTypeDef , SDADC_HandleTypeDef , TIM_HandleTypeDef , TSC_HandleTypeDef , USART_HandleTypeDef , RTC_HandleTypeDef , __DMA_HandleTypeDef
  • StdId : CanTxMsgTypeDef , CanRxMsgTypeDef
  • StopBits : USART_InitTypeDef , LL_USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • Swap : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • SynchPrescaler : LL_RTC_InitTypeDef
  • SynchroPinPolarity : TSC_InitTypeDef
  • SYSCLK_Frequency : LL_RCC_ClocksTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • Tamper : RTC_TamperTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • TimeFormat : LL_RTC_TimeTypeDef , RTC_TimeTypeDef
  • TimeOutEnable : SMARTCARD_InitTypeDef
  • TimeOutValue : SMARTCARD_InitTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef
  • Timing : I2C_InitTypeDef , SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • Tolerance : CEC_InitTypeDef
  • TransferDirection : LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • TrigAuto : LL_ADC_INJ_InitTypeDef
  • Trigger : RTC_TamperTypeDef , LL_EXTI_InitTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerMode : COMP_InitTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriggerSource : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef , LL_DAC_InitTypeDef
  • TTCM : CAN_InitTypeDef
  • TXFP : CAN_InitTypeDef
  • TxISR : __SPI_HandleTypeDef
  • TxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • TxXferCount : USART_HandleTypeDef , __SPI_HandleTypeDef , CEC_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , I2S_HandleTypeDef , UART_HandleTypeDef
  • TxXferSize : UART_HandleTypeDef , __SPI_HandleTypeDef , IRDA_HandleTypeDef , I2S_HandleTypeDef , SMARTCARD_HandleTypeDef , USART_HandleTypeDef
  • type : PCD_EPTypeDef
  • TypeAcknowledge : LL_I2C_InitTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- u -

  • Usart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart3ClockSelection : RCC_PeriphCLKInitTypeDef
  • USB_Address : PCD_HandleTypeDef
  • USBClockSelection : RCC_PeriphCLKInitTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • Variables
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- w -

  • WakeUpEvent : UART_WakeUpTypeDef
  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WaveAutoGeneration : LL_DAC_InitTypeDef
  • WaveAutoGenerationConfig : LL_DAC_InitTypeDef
  • WeekDay : RTC_DateTypeDef , LL_RTC_DateTypeDef
  • Window : IWDG_InitTypeDef , WWDG_InitTypeDef
  • WindowMode : COMP_InitTypeDef
  • WordLength : USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , IRDA_InitTypeDef
  • WRPPage : FLASH_OBProgramInitTypeDef
  • WRPState : FLASH_OBProgramInitTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- x -

  • xfer_buff : PCD_EPTypeDef
  • xfer_count : PCD_EPTypeDef
  • xfer_len : PCD_EPTypeDef
  • XferAbortCallback : __DMA_HandleTypeDef
  • XferCount : __I2C_HandleTypeDef , SMBUS_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferISR : __I2C_HandleTypeDef
  • XferOptions : SMBUS_HandleTypeDef , __I2C_HandleTypeDef
  • XferSize : SMBUS_HandleTypeDef , __I2C_HandleTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Data Fields - Variables

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  • Variables
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  • c
  • d
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  • g
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- y -

  • Year : RTC_DateTypeDef , LL_RTC_DateTypeDef
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_conf.h File Reference

  • File List
  • Globals
Defines
stm32f3xx_hal_conf.h File Reference

HAL configuration file. More...

#include "stm32f3xx_hal_rcc.h"
#include "stm32f3xx_hal_gpio.h"
#include "stm32f3xx_hal_dma.h"
#include "stm32f3xx_hal_cortex.h"
#include "stm32f3xx_hal_adc.h"
#include "stm32f3xx_hal_can.h"
#include "stm32f3xx_hal_cec.h"
#include "stm32f3xx_hal_comp.h"
#include "stm32f3xx_hal_crc.h"
#include "stm32f3xx_hal_dac.h"
#include "stm32f3xx_hal_flash.h"
#include "stm32f3xx_hal_sram.h"
#include "stm32f3xx_hal_nor.h"
#include "stm32f3xx_hal_nand.h"
#include "stm32f3xx_hal_pccard.h"
#include "stm32f3xx_hal_hrtim.h"
#include "stm32f3xx_hal_i2c.h"
#include "stm32f3xx_hal_i2s.h"
#include "stm32f3xx_hal_irda.h"
#include "stm32f3xx_hal_iwdg.h"
#include "stm32f3xx_hal_opamp.h"
#include "stm32f3xx_hal_pcd.h"
#include "stm32f3xx_hal_pwr.h"
#include "stm32f3xx_hal_rtc.h"
#include "stm32f3xx_hal_sdadc.h"
#include "stm32f3xx_hal_smartcard.h"
#include "stm32f3xx_hal_smbus.h"
#include "stm32f3xx_hal_spi.h"
#include "stm32f3xx_hal_tim.h"
#include "stm32f3xx_hal_tsc.h"
#include "stm32f3xx_hal_uart.h"
#include "stm32f3xx_hal_usart.h"
#include "stm32f3xx_hal_wwdg.h"

Go to the source code of this file.

Defines

#define | HAL_MODULE_ENABLED
This is the list of modules to be used in the HAL driver.
#define | HAL_ADC_MODULE_ENABLED
#define | HAL_CAN_MODULE_ENABLED
#define | HAL_CEC_MODULE_ENABLED
#define | HAL_COMP_MODULE_ENABLED
#define | HAL_CORTEX_MODULE_ENABLED
#define | HAL_CRC_MODULE_ENABLED
#define | HAL_DAC_MODULE_ENABLED
#define | HAL_DMA_MODULE_ENABLED
#define | HAL_FLASH_MODULE_ENABLED
#define | HAL_SRAM_MODULE_ENABLED
#define | HAL_NOR_MODULE_ENABLED
#define | HAL_NAND_MODULE_ENABLED
#define | HAL_PCCARD_MODULE_ENABLED
#define | HAL_GPIO_MODULE_ENABLED
#define | HAL_HRTIM_MODULE_ENABLED
#define | HAL_I2C_MODULE_ENABLED
#define | HAL_I2S_MODULE_ENABLED
#define | HAL_IRDA_MODULE_ENABLED
#define | HAL_IWDG_MODULE_ENABLED
#define | HAL_OPAMP_MODULE_ENABLED
#define | HAL_PCD_MODULE_ENABLED
#define | HAL_PWR_MODULE_ENABLED
#define | HAL_RCC_MODULE_ENABLED
#define | HAL_RTC_MODULE_ENABLED
#define | HAL_SDADC_MODULE_ENABLED
#define | HAL_SMARTCARD_MODULE_ENABLED
#define | HAL_SMBUS_MODULE_ENABLED
#define | HAL_SPI_MODULE_ENABLED
#define | HAL_TIM_MODULE_ENABLED
#define | HAL_TSC_MODULE_ENABLED
#define | HAL_UART_MODULE_ENABLED
#define | HAL_USART_MODULE_ENABLED
#define | HAL_WWDG_MODULE_ENABLED
#define | HSE_VALUE (8000000U)
Adjust the value of External High Speed oscillator (HSE) used in your application.
#define | HSE_STARTUP_TIMEOUT (100U)
In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value.
#define | HSI_VALUE (8000000U)
Internal High Speed oscillator (HSI) value.
#define | HSI_STARTUP_TIMEOUT (5000U)
In the following line adjust the Internal High Speed oscillator (HSI) Startup Timeout value.
#define | LSI_VALUE (40000U)
Internal Low Speed oscillator (LSI) value.
#define | LSE_VALUE (32768U)
External Low Speed oscillator (LSE) value.
#define | LSE_STARTUP_TIMEOUT (5000U)
Time out for LSE start up value in ms.
#define | EXTERNAL_CLOCK_VALUE (8000000U)
External clock source for I2S peripheral This value is used by the I2S HAL module to compute the I2S clock source frequency, this source is inserted directly through I2S_CKIN pad.
#define | VDD_VALUE (3300U)
This is the HAL system configuration section.
#define | TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U)
#define | USE_RTOS 0U
#define | PREFETCH_ENABLE 1U
#define | INSTRUCTION_CACHE_ENABLE 0U
#define | DATA_CACHE_ENABLE 0U
#define | USE_SPI_CRC 1U
#define | assert_param(expr) ((void)0U)
Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.

Detailed Description

HAL configuration file.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.

Include module's header file

Definition at line 327 of file stm32f3xx_hal_conf.h.

Referenced by FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_ProgramData(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetState(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_CAN_ConfigFilter(), HAL_CAN_DeInit(), HAL_CAN_Init(), HAL_CAN_Receive(), HAL_CAN_Receive_IT(), HAL_CAN_Transmit(), HAL_CAN_Transmit_IT(), HAL_CEC_DeInit(), HAL_CEC_Init(), HAL_CEC_SetDeviceAddress(), HAL_CEC_Transmit_IT(), HAL_COMP_DeInit(), HAL_COMP_GetOutputLevel(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_Start(), HAL_COMP_Start_IT(), HAL_COMP_Stop(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), HAL_CRCEx_Output_Data_Reverse(), HAL_CRCEx_Polynomial_Set(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetValue(), HAL_DAC_Init(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualSetValue(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_TriangleWaveGenerate(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), HAL_FLASHEx_OBProgram(), HAL_GPIO_DeInit(), HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), HAL_GPIO_WritePin(), HAL_HalfDuplex_Init(), HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableFastModePlus(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableFastModePlus(), HAL_I2CEx_EnableWakeUp(), HAL_I2S_DeInit(), HAL_IRDA_DeInit(), HAL_IRDA_Init(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_IWDG_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MPU_ConfigRegion(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetPriority(), HAL_NVIC_SetPriority(), HAL_NVIC_SetPriorityGrouping(), HAL_OPAMPEx_SelfCalibrateAll(), HAL_PCD_Init(), HAL_PWR_ConfigPVD(), HAL_PWR_DisableWakeUpPin(), HAL_PWR_EnableWakeUpPin(), HAL_PWR_EnterSLEEPMode(), HAL_PWR_EnterSTOPMode(), HAL_PWREx_DisableSDADC(), HAL_PWREx_EnableSDADC(), HAL_RCC_ClockConfig(), HAL_RCC_GetClockConfig(), HAL_RCC_GetOscConfig(), HAL_RCC_MCOConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), HAL_RS485Ex_Init(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SDADC_AssociateChannelConfig(), HAL_SDADC_CalibrationStart(), HAL_SDADC_CalibrationStart_IT(), HAL_SDADC_ConfigChannel(), HAL_SDADC_DeInit(), HAL_SDADC_GetValue(), HAL_SDADC_Init(), HAL_SDADC_InjectedConfigChannel(), HAL_SDADC_InjectedGetValue(), HAL_SDADC_InjectedMultiModeConfigChannel(), HAL_SDADC_InjectedMultiModeGetValue(), HAL_SDADC_InjectedMultiModeStart_DMA(), HAL_SDADC_InjectedMultiModeStop_DMA(), HAL_SDADC_InjectedStart(), HAL_SDADC_InjectedStart_DMA(), HAL_SDADC_InjectedStart_IT(), HAL_SDADC_InjectedStop(), HAL_SDADC_InjectedStop_DMA(), HAL_SDADC_InjectedStop_IT(), HAL_SDADC_MultiModeConfigChannel(), HAL_SDADC_MultiModeGetValue(), HAL_SDADC_MultiModeStart_DMA(), HAL_SDADC_MultiModeStop_DMA(), HAL_SDADC_PollForCalibEvent(), HAL_SDADC_PollForConversion(), HAL_SDADC_PollForInjectedConversion(), HAL_SDADC_PrepareChannelConfig(), HAL_SDADC_SelectInjectedDelay(), HAL_SDADC_SelectInjectedExtTrigger(), HAL_SDADC_SelectInjectedTrigger(), HAL_SDADC_SelectRegularTrigger(), HAL_SDADC_Start(), HAL_SDADC_Start_DMA(), HAL_SDADC_Start_IT(), HAL_SDADC_Stop(), HAL_SDADC_Stop_DMA(), HAL_SDADC_Stop_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARDEx_TimeOut_Config(), HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SYSTICK_CLKSourceConfig(), HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_RemapConfig(), HAL_TSC_DeInit(), HAL_TSC_GetState(), HAL_TSC_GroupGetStatus(), HAL_TSC_GroupGetValue(), HAL_TSC_Init(), HAL_TSC_IOConfig(), HAL_TSC_IODischarge(), HAL_TSC_IRQHandler(), HAL_TSC_PollForAcquisition(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), HAL_TSC_Stop_IT(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_UARTEx_DisableStopMode(), HAL_UARTEx_EnableStopMode(), HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_USART_DeInit(), HAL_USART_Init(), HAL_WWDG_Init(), I2C_TransferConfig(), IRDA_SetConfig(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_SetConfig(), SMBUS_TransferConfig(), TIM_CCxChannelCmd(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_SlaveTimer_SetConfig(), UART_AdvFeatureConfig(), UART_SetConfig(), UART_Wakeup_AddressConfig(), and USART_SetConfig().

#define DATA_CACHE_ENABLE 0U

Definition at line 166 of file stm32f3xx_hal_conf.h.

#define EXTERNAL_CLOCK_VALUE (8000000U)

External clock source for I2S peripheral This value is used by the I2S HAL module to compute the I2S clock source frequency, this source is inserted directly through I2S_CKIN pad.

  • External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
  • External clock not generated on EVAL 373 Value of the External oscillator in Hz

Definition at line 151 of file stm32f3xx_hal_conf.h.

#define HAL_ADC_MODULE_ENABLED

Definition at line 52 of file stm32f3xx_hal_conf.h.

#define HAL_CAN_MODULE_ENABLED

Definition at line 53 of file stm32f3xx_hal_conf.h.

#define HAL_CEC_MODULE_ENABLED

Definition at line 54 of file stm32f3xx_hal_conf.h.

#define HAL_COMP_MODULE_ENABLED

Definition at line 55 of file stm32f3xx_hal_conf.h.

#define HAL_CORTEX_MODULE_ENABLED

Definition at line 56 of file stm32f3xx_hal_conf.h.

#define HAL_CRC_MODULE_ENABLED

Definition at line 57 of file stm32f3xx_hal_conf.h.

#define HAL_DAC_MODULE_ENABLED

Definition at line 58 of file stm32f3xx_hal_conf.h.

#define HAL_DMA_MODULE_ENABLED

Definition at line 59 of file stm32f3xx_hal_conf.h.

#define HAL_FLASH_MODULE_ENABLED

Definition at line 60 of file stm32f3xx_hal_conf.h.

#define HAL_GPIO_MODULE_ENABLED

Definition at line 65 of file stm32f3xx_hal_conf.h.

#define HAL_HRTIM_MODULE_ENABLED

Definition at line 66 of file stm32f3xx_hal_conf.h.

#define HAL_I2C_MODULE_ENABLED

Definition at line 67 of file stm32f3xx_hal_conf.h.

#define HAL_I2S_MODULE_ENABLED

Definition at line 68 of file stm32f3xx_hal_conf.h.

#define HAL_IRDA_MODULE_ENABLED

Definition at line 69 of file stm32f3xx_hal_conf.h.

#define HAL_IWDG_MODULE_ENABLED

Definition at line 70 of file stm32f3xx_hal_conf.h.

#define HAL_MODULE_ENABLED

This is the list of modules to be used in the HAL driver.

Definition at line 51 of file stm32f3xx_hal_conf.h.

#define HAL_NAND_MODULE_ENABLED

Definition at line 63 of file stm32f3xx_hal_conf.h.

#define HAL_NOR_MODULE_ENABLED

Definition at line 62 of file stm32f3xx_hal_conf.h.

#define HAL_OPAMP_MODULE_ENABLED

Definition at line 71 of file stm32f3xx_hal_conf.h.

#define HAL_PCCARD_MODULE_ENABLED

Definition at line 64 of file stm32f3xx_hal_conf.h.

#define HAL_PCD_MODULE_ENABLED

Definition at line 72 of file stm32f3xx_hal_conf.h.

#define HAL_PWR_MODULE_ENABLED

Definition at line 73 of file stm32f3xx_hal_conf.h.

#define HAL_RCC_MODULE_ENABLED

Definition at line 74 of file stm32f3xx_hal_conf.h.

#define HAL_RTC_MODULE_ENABLED

Definition at line 75 of file stm32f3xx_hal_conf.h.

#define HAL_SDADC_MODULE_ENABLED

Definition at line 76 of file stm32f3xx_hal_conf.h.

#define HAL_SMARTCARD_MODULE_ENABLED

Definition at line 77 of file stm32f3xx_hal_conf.h.

#define HAL_SMBUS_MODULE_ENABLED

Definition at line 78 of file stm32f3xx_hal_conf.h.

#define HAL_SPI_MODULE_ENABLED

Definition at line 79 of file stm32f3xx_hal_conf.h.

#define HAL_SRAM_MODULE_ENABLED

Definition at line 61 of file stm32f3xx_hal_conf.h.

#define HAL_TIM_MODULE_ENABLED

Definition at line 80 of file stm32f3xx_hal_conf.h.

#define HAL_TSC_MODULE_ENABLED

Definition at line 81 of file stm32f3xx_hal_conf.h.

#define HAL_UART_MODULE_ENABLED

Definition at line 82 of file stm32f3xx_hal_conf.h.

#define HAL_USART_MODULE_ENABLED

Definition at line 83 of file stm32f3xx_hal_conf.h.

#define HAL_WWDG_MODULE_ENABLED

Definition at line 84 of file stm32f3xx_hal_conf.h.

#define HSE_STARTUP_TIMEOUT (100U)

In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value.

Time out for HSE start up, in ms

Definition at line 101 of file stm32f3xx_hal_conf.h.

#define HSE_VALUE (8000000U)

Adjust the value of External High Speed oscillator (HSE) used in your application.

This value is used by the RCC HAL module to compute the system frequency (when HSE is used as system clock source, directly or through the PLL). Value of the External oscillator in Hz

Definition at line 93 of file stm32f3xx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), RCC_GetPLLCLKFreq(), RCC_GetSystemClockFreq(), and RCC_PLL_GetFreqDomain_SYS().

#define HSI_STARTUP_TIMEOUT (5000U)

In the following line adjust the Internal High Speed oscillator (HSI) Startup Timeout value.

Time out for HSI start up

Definition at line 118 of file stm32f3xx_hal_conf.h.

#define HSI_VALUE (8000000U)

Internal High Speed oscillator (HSI) value.

This value is used by the RCC HAL module to compute the system frequency (when HSI is used as system clock source, directly or through the PLL). Value of the Internal oscillator in Hz

Definition at line 110 of file stm32f3xx_hal_conf.h.

Referenced by HAL_RCC_DeInit(), HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), LL_PLL_ConfigSystemClock_HSI(), LL_RCC_GetCECClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetUSARTClockFreq(), RCC_GetPLLCLKFreq(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_SYS(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define INSTRUCTION_CACHE_ENABLE 0U

Definition at line 165 of file stm32f3xx_hal_conf.h.

#define LSE_STARTUP_TIMEOUT (5000U)

Time out for LSE start up value in ms.

Time out for LSE start up, in ms

Definition at line 140 of file stm32f3xx_hal_conf.h.

#define LSE_VALUE (32768U)

External Low Speed oscillator (LSE) value.

< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. Value of the External Low Speed oscillator in Hz

Definition at line 133 of file stm32f3xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), LL_RCC_GetCECClockFreq(), LL_RCC_GetUSARTClockFreq(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define LSI_VALUE (40000U)

Internal Low Speed oscillator (LSI) value.

Definition at line 125 of file stm32f3xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define PREFETCH_ENABLE 1U

Definition at line 164 of file stm32f3xx_hal_conf.h.

#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U)

tick interrupt priority (lowest by default)

Definition at line 162 of file stm32f3xx_hal_conf.h.

Referenced by HAL_Init(), and HAL_RCC_ClockConfig().

#define USE_RTOS 0U

Definition at line 163 of file stm32f3xx_hal_conf.h.

#define USE_SPI_CRC 1U

Definition at line 167 of file stm32f3xx_hal_conf.h.

#define VDD_VALUE (3300U)

This is the HAL system configuration section.

Value of VDD in mv

Definition at line 161 of file stm32f3xx_hal_conf.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_hrtim.c File Reference

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stm32f3xx_hal_hrtim.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the High Resolution Timer (HRTIM) peripheral: + HRTIM Initialization + DLL Calibration Start + Timer Time Base Unit Configuration + Simple Time Base Start/Stop + Simple Time Base Start/Stop Interrupt + Simple Time Base Start/Stop DMA Request + Simple Output Compare/PWM Channel Configuration + Simple Output Compare/PWM Channel Start/Stop Interrupt + Simple Output Compare/PWM Channel Start/Stop DMA Request + Simple Input Capture Channel Configuration + Simple Input Capture Channel Start/Stop Interrupt + Simple Input Capture Channel Start/Stop DMA Request + Simple One Pulse Channel Configuration + Simple One Pulse Channel Start/Stop Interrupt + HRTIM External Synchronization Configuration + HRTIM Burst Mode Controller Configuration + HRTIM Burst Mode Controller Enabling + HRTIM External Events Conditioning Configuration + HRTIM Faults Conditioning Configuration + HRTIM Faults Enabling + HRTIM ADC trigger Configuration + Waveform Timer Configuration + Waveform Event Filtering Configuration + Waveform Dead Time Insertion Configuration + Waveform Chopper Mode Configuration + Waveform Compare Unit Configuration + Waveform Capture Unit Configuration + Waveform Output Configuration + Waveform Counter Start/Stop + Waveform Counter Start/Stop Interrupt + Waveform Counter Start/Stop DMA Request + Waveform Output Enabling + Waveform Output Level Set/Get + Waveform Output State Get + Waveform Burst DMA Operation Configuration + Waveform Burst DMA Operation Start + Waveform Timer Counter Software Reset + Waveform Capture Software Trigger + Waveform Burst Mode Controller Software Trigger + Waveform Timer Pre-loadable Registers Update Enabling + Waveform Timer Pre-loadable Registers Software Update + Waveform Timer Delayed Protection Status Get + Waveform Timer Burst Status Get + Waveform Timer Push-Pull Status Get + Peripheral State Get. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the High Resolution Timer (HRTIM) peripheral: + HRTIM Initialization + DLL Calibration Start + Timer Time Base Unit Configuration + Simple Time Base Start/Stop + Simple Time Base Start/Stop Interrupt + Simple Time Base Start/Stop DMA Request + Simple Output Compare/PWM Channel Configuration + Simple Output Compare/PWM Channel Start/Stop Interrupt + Simple Output Compare/PWM Channel Start/Stop DMA Request + Simple Input Capture Channel Configuration + Simple Input Capture Channel Start/Stop Interrupt + Simple Input Capture Channel Start/Stop DMA Request + Simple One Pulse Channel Configuration + Simple One Pulse Channel Start/Stop Interrupt + HRTIM External Synchronization Configuration + HRTIM Burst Mode Controller Configuration + HRTIM Burst Mode Controller Enabling + HRTIM External Events Conditioning Configuration + HRTIM Faults Conditioning Configuration + HRTIM Faults Enabling + HRTIM ADC trigger Configuration + Waveform Timer Configuration + Waveform Event Filtering Configuration + Waveform Dead Time Insertion Configuration + Waveform Chopper Mode Configuration + Waveform Compare Unit Configuration + Waveform Capture Unit Configuration + Waveform Output Configuration + Waveform Counter Start/Stop + Waveform Counter Start/Stop Interrupt + Waveform Counter Start/Stop DMA Request + Waveform Output Enabling + Waveform Output Level Set/Get + Waveform Output State Get + Waveform Burst DMA Operation Configuration + Waveform Burst DMA Operation Start + Waveform Timer Counter Software Reset + Waveform Capture Software Trigger + Waveform Burst Mode Controller Software Trigger + Waveform Timer Pre-loadable Registers Update Enabling + Waveform Timer Pre-loadable Registers Software Update + Waveform Timer Delayed Protection Status Get + Waveform Timer Burst Status Get + Waveform Timer Push-Pull Status Get + Peripheral State Get.

Author:
MCD Application Team
==============================================================================
                      ##### Simple mode v.s. waveform mode #####
==============================================================================
  [..] The HRTIM HAL API is split into 2 categories:
    (#)Simple functions: these functions allow for using a HRTIM timer as a
       general purpose timer with high resolution capabilities.
       HRTIM simple modes are managed through the set of functions named
       HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
       to the one defined for the TIM peripheral. When a HRTIM timer operates in
       simple mode, only a very limited set of HRTIM features are used.
       Following simple modes are proposed:
         (++)Output compare mode,
         (++)PWM output mode,
         (++)Input capture mode,
         (++)One pulse mode.
    (#)Waveform functions: These functions allow taking advantage of the HRTIM
       flexibility to produce numerous types of control signal. When a HRTIM timer
       operates in waveform mode, all the HRTIM features are accessible without
       any restriction.  HRTIM waveform modes are managed through the set of
       functions named HAL_HRTIM_Waveform<Function>
                      ##### How to use this driver #####
==============================================================================
    [..]
     (#)Initialize the HRTIM low level resources by implementing the
        HAL_HRTIM_MspInit() function:
        (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
        (##)Connect HRTIM pins to MCU I/Os
            (+++) Enable the clock for the HRTIM GPIOs using the following
                  function: __HAL_RCC_GPIOx_CLK_ENABLE()
            (+++) Configure these GPIO pins in Alternate Function mode using
                  HAL_GPIO_Init()
        (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
            (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
            (+++)Initialize the DMA handle
            (+++)Associate the initialized DMA handle to the appropriate DMA
                 handle of the HRTIM handle using  __HAL_LINKDMA()
            (+++)Initialize the DMA channel using HAL_DMA_Init()
            (+++)Configure the priority and enable the NVIC for the transfer
                 complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
                 and HAL_NVIC_EnableIRQ()
        (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
            (+++)Configure the priority and enable the NVIC for the concerned
                 HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()

    (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
       structure (field of the HRTIM handle) specifies which global interrupt of
       whole HRTIM must be enabled (Burst mode period, System fault, Faults).
       It also contains the HRTIM external synchronization configuration. HRTIM
       can act as a master (generating a synchronization signal) or as a slave
       (waiting for a trigger to be synchronized).

    (#)Start the high resolution unit using HAL_HRTIM_DLLCalibrationStart(). DLL
       calibration is executed periodically and compensate for potential voltage
       and temperature drifts. DLL calibration period is specified by the
       CalibrationRate argument.

    (#)HRTIM timers cannot be used until the high resolution unit is ready. This
       can be checked using HAL_HRTIM_PollForDLLCalibration(): this function returns
       HAL_OK if DLL calibration is completed or HAL_TIMEOUT if the DLL calibration
       is still going on when timeout given as argument expires. DLL calibration
       can also be started in interrupt mode using HAL_HRTIM_DLLCalibrationStart_IT().
       In that case an interrupt is generated when the DLL calibration is completed.
       Note that as DLL calibration is executed on a periodic basis an interrupt
       will be generated at the end of every DLL calibration operation
      (worst case: one interrupt every 14  micro seconds !).

     (#) Configure HRTIM resources shared by all HRTIM timers
        (##)Burst Mode Controller:
                (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
                     controller: operating mode (continuous or one-shot mode), clock
                     (source, prescaler) , trigger(s), period, idle duration.
        (##)External Events Conditionning:
                (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
                     external event channel: source, polarity, edge-sensitivity.
                     External event can be used as triggers (timer reset, input
                     capture, burst mode, ADC triggers, delayed protection)
                     They can also be used to set or reset timer outputs. Up to
                     10 event channels are available.
                (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
                     event sampling clock (used for digital filtering).
        (##)Fault Conditionning:
                (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
                     fault channel: source, polarity, edge-sensitivity.  Fault
                     channels are used to disable the outputs in case of an
                     abnormal operation. Up to 5 fault channels are available.
                (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
                     sampling clock (used for digital filtering).
                (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
                     circuitry. By default all fault inputs are disabled.
        (##)ADC trigger:
                (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
                     the update of the ADC trigger register and the ADC trigger.
                     4 independent triggers are available to start both the regular
                     and the injected sequencers of the 2 ADCs

     (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
         function must be called whatever the HRTIM timer operating mode is
         (simple v.s. waveform). It  configures mainly:
        (##)The HRTIM  timer counter operating mode (continuous v.s. one shot)
        (##)The HRTIM  timer clock prescaler
        (##)The HRTIM  timer period
        (##)The HRTIM  timer repetition counter

     *** If the HRTIM timer operates in simple mode ***
     ===================================================
     [..]
     (#) Start or Stop simple timers
              (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
                  HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
                  HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
              (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
                  HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
                  HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
                  HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
              (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
                  HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
                  HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
                  HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
              (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
                  HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
                  HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
                  HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
              (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
                  HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
                  HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().

     *** If the HRTIM timer operates in waveform mode ***
     ====================================================
     [..]
     (#) Completes waveform timer configuration
              (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
                  operating in wave form mode mainly consists in:
                (+++)Enabling the HRTIM timer interrupts and DMA requests.
                (+++)Enabling the half mode for the HRTIM timer.
                (+++)Defining how the HRTIM timer reacts to external synchronization input.
                (+++)Enabling the push-pull mode for the HRTIM timer.
                (+++)Enabling the fault channels for the HRTIM timer.
                (+++)Enabling the dead-time insertion for the HRTIM timer.
                (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
                     on which the delayed protection are applied).
                (+++)Specifying the HRTIM timer update and reset triggers.
                (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
              (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
                  event blanking and windowing circuitry of a HRTIM timer:
                (+++)Blanking:  to mask external events during a defined  time period a defined time period
                (+++)Windowing, to enable external events only during a defined time period
              (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
                  unit for a HRTIM timer. Allows to generate a couple of
                  complementary signals from a single reference waveform,
                  with programmable delays between active state.
              (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
                  the high-frequency carrier signal added on top of the timing
                  unit output. Chopper mode can be enabled or disabled for each
                   timer output separately (see  HAL_HRTIM_WaveformOutputConfig()).
              (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
                  controller. Allows having multiple HRTIM registers updated
                  with a single DMA request. The burst DMA operation is started
                  by calling HAL_HRTIM_BurstDMATransfer().
              (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
                  of a HRTIM timer. This operation consists in setting the
                  compare value and possibly specifying the auto delayed mode
                  for compare units 2 and 4 (allows to have compare events
                  generated relatively to capture events). Note that when auto
                  delayed mode is needed, the capture unit associated to the
                  compare unit must be configured separately.
              (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
                  of a HRTIM timer. This operation consists in specifying the
                  source(s)  triggering the capture (timer register update event,
                  external event, timer output set/reset event, other HRTIM
                  timer related events).
              (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
                  output mainly consists in:
                (+++)Setting the output polarity (active high or active low),
                (+++)Defining the set/reset crossbar for the output,
                (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,

     (#) Set waveform timer output(s) level
              (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
                  active or inactive level. For example, when deadtime insertion
                  is enabled it is necessary to force the output level by software
                  to have the outputs in a complementary state as soon as the RUN mode is entered.

     (#) Enable or Disable waveform timer output(s)
              (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().

     (#) Start or Stop waveform HRTIM timer(s).
              (++)HAL_HRTIM_WaveformCounterStart(),HAL_HRTIM_WaveformCounterStop(),
              (++)HAL_HRTIM_WaveformCounterStart_IT(),HAL_HRTIM_WaveformCounterStop_IT(),
              (++)HAL_HRTIM_WaveformCounterStart()_DMA,HAL_HRTIM_WaveformCounterStop_DMA(),
     (#) Burst mode controller enabling:
              (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
                  burst mode controller.

     (#) Some HRTIM operations can be triggered by software:
              (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
                  trigs the burst operation.
              (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
                  capture of the HRTIM timer counter.
              (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
                  update of the pre-loadable registers of the HRTIM timer
              (++)HAL_HRTIM_SoftwareReset():calling this function resets the
                  HRTIM timer counter.

     (#) Some functions can be used any time to retrieve HRTIM timer related
            information
              (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
                  capture register of the designated capture unit.
              (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
                 (ACTIVE/INACTIVE) of the designated timer output.
              (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
                 (IDLE/RUN/FAULT) of the designated timer output.
              (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
                 (ACTIVE/INACTIVE) of the designated output when the delayed
                  protection was triggered.
              (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
                 (ACTIVE/INACTIVE) of the burst mode controller.
              (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
                 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
                 the push-pull status indicates on which output the signal is currently
                 active (e.g signal applied on output 1 and output 2 forced
                 inactive or vice versa).
             (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
                 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
                 the idle push-pull status indicates during which period the
                 delayed protection request occurred (e.g. protection occurred
                 when the output 1 was active and output 2 forced inactive or
                 vice versa).

     (#) Some functions can be used any time to retrieve actual HRTIM status
             (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_hrtim.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_hrtim.h File Reference

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stm32f3xx_hal_hrtim.h File Reference

Header file of HRTIM HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of HRTIM HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_hrtim.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_nand.c File Reference

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stm32f3xx_hal_nand.c File Reference

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Detailed Description

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device.

Author:
MCD Application Team
  ==============================================================================
                         ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver is a generic layered driver which contains a set of APIs used to
      control NAND flash memories. It uses the FMC layer functions to interface
      with NAND devices. This driver is used as follows:

      (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
          with control and timing parameters for both common and attribute spaces.

      (+) Read NAND flash memory maker and device IDs using the function
          HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
          structure declared by the function caller.

      (+) Access NAND flash memory by read/write operations using the functions
          HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
          HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
          HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
          HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
          to read/write page(s)/spare area(s). These functions use specific device
          information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
          structure. The read/write address information is contained by the Nand_Address_Typedef
          structure passed as parameter.

      (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().

      (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
          The erase block address information is contained in the Nand_Address_Typedef
          structure passed as parameter.

      (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().

      (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
          HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
          feature or the function HAL_NAND_GetECC() to get the ECC correction code.

      (+) You can monitor the NAND device HAL state by calling the function
          HAL_NAND_GetState()

    [..]
      (@) This driver is a set of generic APIs which handle standard NAND flash operations.
          If a NAND flash device contains different operations and/or implementations,
          it should be implemented separately.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_nand.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_nand.h File Reference

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stm32f3xx_hal_nand.h File Reference

Header file of NAND HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of NAND HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_nand.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_nor.c File Reference

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stm32f3xx_hal_nor.c File Reference

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Detailed Description

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver is a generic layered driver which contains a set of APIs used to
      control NOR flash memories. It uses the FMC layer functions to interface
      with NOR devices. This driver is used as follows:

      (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
          with control and timing parameters for both normal and extended mode.

      (+) Read NOR flash memory manufacturer code and device IDs using the function
          HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
          structure declared by the function caller.

      (+) Access NOR flash memory by read/write data unit operations using the functions
          HAL_NOR_Read(), HAL_NOR_Program().

      (+) Perform NOR flash erase block/chip operations using the functions
          HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().

      (+) Read the NOR flash CFI (common flash interface) IDs using the function
          HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
          structure declared by the function caller.

      (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
          HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation

      (+) You can monitor the NOR device HAL state by calling the function
          HAL_NOR_GetState()
    [..]
     (@) This driver is a set of generic APIs which handle standard NOR flash operations.
         If a NOR flash device contains different operations and/or implementations,
         it should be implemented separately.

     *** NOR HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in NOR HAL driver.

      (+) NOR_WRITE: NOR memory write data to specified address
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_nor.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_nor.h File Reference

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stm32f3xx_hal_nor.h File Reference

Header file of NOR HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of NOR HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_nor.h.

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STM32F373xC HAL User Manual: stm32f3xx_hal_opamp.c File Reference

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stm32f3xx_hal_opamp.c File Reference

OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifiers (OPAMP1,...OPAMP4) peripheral: + OPAMP Configuration + OPAMP calibration Thanks to + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Detailed Description

OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifiers (OPAMP1,...OPAMP4) peripheral: + OPAMP Configuration + OPAMP calibration Thanks to + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
================================================================================
          ##### OPAMP Peripheral Features #####
================================================================================

  [..] The device integrates up to 4 operational amplifiers OPAMP1, OPAMP2,
       OPAMP3 and OPAMP4:

       (#) The OPAMP(s) provides several exclusive running modes.
       (++) Standalone mode
       (++) Programmable Gain Amplifier (PGA) mode (Resistor feedback output)
       (++) Follower mode

       (#) The OPAMP(s) provide(s) calibration capabilities.
       (++) Calibration aims at correcting some offset for running mode.
       (++) The OPAMP uses either factory calibration settings OR user defined
           calibration (trimming) settings (i.e. trimming mode).
       (++) The user defined settings can be figured out using self calibration
           handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
       (++) HAL_OPAMP_SelfCalibrate:
       (++) Runs automatically the calibration in 2 steps.
            (90U% of VDDA for NMOS transistors, 10U% of VDDA for PMOS transistors).
            (As OPAMP is Rail-to-rail input/output, these 2 steps calibration is
            appropriate and enough in most cases).
       (++) Enables the user trimming mode
       (++) Updates the init structure with trimming values with fresh calibration
            results.
            The user may store the calibration results for larger
            (ex monitoring the trimming as a function of temperature
            for instance)
       (++) for STM32F3 devices having 2 or 4 OPAMPs
            HAL_OPAMPEx_SelfCalibrateAll
            runs calibration of 2 or 4 OPAMPs in parallel.

       (#) For any running mode, an additional Timer-controlled Mux (multiplexer)
           mode can be set on top.
       (++) Timer-controlled Mux mode allows Automatic switching between inverting
           and non-inverting input.
       (++) Hence on top of defaults (primary) inverting and non-inverting inputs,
           the user shall select secondary inverting and non inverting inputs.
       (++) TIM1 CC6 provides the alternate switching tempo between defaults
           (primary) and secondary inputs.

       (#) Running mode: Standalone mode
       (++) Gain is set externally (gain depends on external loads).
       (++) Follower mode also possible externally by connecting the inverting input to
           the output.

       (#) Running mode: Follower mode
       (++) No Inverting Input is connected.

       (#) Running mode: Programmable Gain Amplifier (PGA) mode
           (Resistor feedback output)
       (++) The OPAMP(s) output(s) can be internally connected to resistor feedback
           output.
       (++) OPAMP gain is either 2U, 4U, 8 or 16.

            ##### How to use this driver #####
================================================================================
  [..]
    *** Calibration ***
    ============================================
    [..]
  To run the opamp calibration self calibration:

      (#) Start calibration using HAL_OPAMP_SelfCalibrate.
           Store the calibration results.

    *** Running mode ***
    ============================================
    [..]
  To use the opamp, perform the following steps:

      (#) Fill in the HAL_OPAMP_MspInit() to
      (++) Configure the opamp input AND output in analog mode using
          HAL_GPIO_Init() to map the opamp output to the GPIO pin.

      (#) Configure the opamp using HAL_OPAMP_Init() function:
      (++) Select the mode
      (++) Select the inverting input
      (++) Select the non-inverting input
      (++) Select if the Timer controlled Mux mode is enabled/disabled
      (++) If the Timer controlled Mux mode is enabled, select the secondary inverting input
      (++) If the Timer controlled Mux mode is enabled, Select the secondary non-inverting input
      (++) If PGA mode is enabled, Select if inverting input is connected.
      (++) Select either factory or user defined trimming mode.
      (++) If the user defined trimming mode is enabled, select PMOS & NMOS trimming values
          (typ. settings returned by HAL_OPAMP_SelfCalibrate function).

      (#) Enable the opamp using HAL_OPAMP_Start() function.

      (#) Disable the opamp using HAL_OPAMP_Stop() function.

      (#) Lock the opamp in running mode using HAL_OPAMP_Lock() function. From then The configuration
          can  be modified
      (++) After HW reset
      (++) OR thanks to HAL_OPAMP_MspDeInit called (user defined) from HAL_OPAMP_DeInit.

    *** Running mode: change of configuration while OPAMP ON  ***
    ============================================
    [..]
    To Re-configure OPAMP when OPAMP is ON (change on the fly)
      (#) If needed, Fill in the HAL_OPAMP_MspInit()
      (++) This is the case for instance if you wish to use new OPAMP I/O

      (#) Configure the opamp using HAL_OPAMP_Init() function:
      (++) As in configure case, selects first the parameters you wish to modify.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_opamp.c.

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STM32F373xC HAL User Manual: stm32f3xx_hal_opamp.h File Reference

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stm32f3xx_hal_opamp.h File Reference

Header file of OPAMP HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of OPAMP HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_opamp.h.

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STM32F373xC HAL User Manual: stm32f3xx_hal_opamp_ex.c File Reference

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stm32f3xx_hal_opamp_ex.c File Reference

Extended OPAMP HAL module driver. More...

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_OPAMPEx_SelfCalibrateAll (OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
Run the self calibration of 2 OPAMPs in parallel.
HAL_StatusTypeDef | HAL_OPAMPEx_SelfCalibrateAll (OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4)
Run the self calibration of 4 OPAMPs in parallel.

Detailed Description

Extended OPAMP HAL module driver.

Author:
MCD Application Team This file provides firmware functions to manage the following functionalities of the Power Controller (OPAMP) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"

/** @addtogroup STM32F3xx_HAL_Driver
  * @{
  */

#ifdef HAL_OPAMP_MODULE_ENABLED

#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
    defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
    defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
    defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)

/** @defgroup OPAMPEx OPAMPEx
  * @brief OPAMP Extended HAL module driver.
  * @{
  */

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions ---------------------------------------------------------*/

/** @defgroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
  * @{
  */

/** @defgroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
  * @brief    Extended Self calibration functions
  *
@verbatim
 ===============================================================================
              ##### Extended IO operation functions #####
 ===============================================================================
  [..]

Definition in file stm32f3xx_hal_opamp_ex.c.

Function Documentation

HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll | ( | OPAMP_HandleTypeDef * | hopamp1,
 |  | OPAMP_HandleTypeDef * | hopamp2
 | ) |  |

Run the self calibration of 2 OPAMPs in parallel.

Parameters:
hopamp1 | handle
hopamp2 | handle
Return values:
HAL status
Note:
Updated offset trimming values (PMOS & NMOS), user trimming is enabled
Calibration runs about 25 ms.

Definition at line 102 of file stm32f3xx_hal_opamp_ex.c.

References assert_param, and HAL_Delay().

HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll | ( | OPAMP_HandleTypeDef * | hopamp1,
 |  | OPAMP_HandleTypeDef * | hopamp2,
 |  | OPAMP_HandleTypeDef * | hopamp3,
 |  | OPAMP_HandleTypeDef * | hopamp4
 | ) |  |

Run the self calibration of 4 OPAMPs in parallel.

Parameters:
hopamp1 | handle
hopamp2 | handle
hopamp3 | handle
hopamp4 | handle
Return values:
HAL status
Note:
Updated offset trimming values (PMOS & NMOS), user trimming is enabled
Calibration runs about 25 ms.

Definition at line 359 of file stm32f3xx_hal_opamp_ex.c.

References assert_param, and HAL_Delay().

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STM32F373xC HAL User Manual: stm32f3xx_hal_opamp_ex.h File Reference

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stm32f3xx_hal_opamp_ex.h File Reference

Header file of OPAMP HAL Extended module. More...

Go to the source code of this file.

Detailed Description

Header file of OPAMP HAL Extended module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_opamp_ex.h.

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STM32F373xC HAL User Manual: stm32f3xx_hal_pccard.c File Reference

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stm32f3xx_hal_pccard.c File Reference

PCCARD HAL module driver. This file provides a generic firmware to drive PCCARD memories mounted as external device. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Detailed Description

PCCARD HAL module driver. This file provides a generic firmware to drive PCCARD memories mounted as external device.

Author:
MCD Application Team
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
   [..]
     This driver is a generic layered driver which contains a set of APIs used to
     control PCCARD/compact flash memories. It uses the FMC layer functions
     to interface with PCCARD devices. This driver is used for:

    (+) PCCARD/compact flash memory configuration sequence using the function
        HAL_PCCARD_Init() with control and timing parameters for both common and
        attribute spaces.

    (+) Read PCCARD/compact flash memory maker and device IDs using the function
        HAL_PCCARD_Read_ID(). The read information is stored in the CompactFlash_ID
        structure declared by the function caller.

    (+) Access PCCARD/compact flash memory by read/write operations using the functions
        HAL_PCCARD_Read_Sector()/HAL_PCCARD_Write_Sector(), to read/write sector.

    (+) Perform PCCARD/compact flash Reset chip operation using the function HAL_PCCARD_Reset().

    (+) Perform PCCARD/compact flash erase sector operation using the function
        HAL_PCCARD_Erase_Sector().

    (+) Read the PCCARD/compact flash status operation using the function HAL_PCCARD_ReadStatus().

    (+) You can monitor the PCCARD/compact flash  device HAL state by calling the function
        HAL_PCCARD_GetState()

   [..]
     (@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
         operations. If a PCCARD/compact flash device contains different operations
         and/or implementations, it should be implemented separately.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_pccard.c.

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STM32F373xC HAL User Manual: stm32f3xx_hal_pccard.h File Reference

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stm32f3xx_hal_pccard.h File Reference

Header file of PCCARD HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of PCCARD HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_pccard.h.

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STM32F373xC HAL User Manual: stm32f3xx_hal_sram.c File Reference

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stm32f3xx_hal_sram.c File Reference

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Detailed Description

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device.

Author:
MCD Application Team
  ==============================================================================
                          ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver is a generic layered driver which contains a set of APIs used to
    control SRAM memories. It uses the FMC layer functions to interface
    with SRAM devices.
    The following sequence should be followed to configure the FMC to interface
    with SRAM/PSRAM memories:

   (#) Declare a SRAM_HandleTypeDef handle structure, for example:
          SRAM_HandleTypeDef  hsram; and:

       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
            values of the structure member.

       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
            base register instance for NOR or SRAM device

       (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
            base register instance for NOR or SRAM extended mode

   (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
       mode timings; for example:
          FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
      and fill its fields with the allowed values of the structure member.

   (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
       performs the following sequence:

       (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
       (##) Control register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Init()
       (##) Timing register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Timing_Init()
       (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Extended_Timing_Init()
       (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()

   (#) At this stage you can perform read/write accesses from/to the memory connected
       to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
       following APIs:
       (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
       (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer

   (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation

   (#) You can continuously monitor the SRAM device HAL state by calling the function
       HAL_SRAM_GetState()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_sram.c.

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STM32F373xC HAL User Manual: stm32f3xx_hal_sram.h File Reference

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stm32f3xx_hal_sram.h File Reference

Header file of SRAM HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of SRAM HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_sram.h.

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STM32F373xC HAL User Manual: stm32f3xx_ll_adc.c File Reference

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Defines | Functions
stm32f3xx_ll_adc.c File Reference

ADC LL module driver. More...

#include "stm32f3xx_ll_adc.h"
#include "stm32f3xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)
#define | IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__)
#define | IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__)
#define | IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)
#define | IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)
#define | IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)
#define | IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)
#define | IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)

Functions

ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *ADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Detailed Description

ADC LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_adc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 44 of file stm32f3xx_ll_adc.c.

Referenced by LL_ADC_CommonDeInit(), LL_ADC_DeInit(), LL_ADC_Init(), LL_ADC_INJ_Init(), and LL_ADC_REG_Init().

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_comp.c File Reference

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Defines | Functions
stm32f3xx_ll_comp.c File Reference

COMP LL module driver. More...

#include "stm32f3xx_ll_comp.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_COMP_POWER_MODE(__POWER_MODE__)
#define | IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)
#define | IS_LL_COMP_OUTPUT_SELECTION(__OUTPUT_SELECTION__)
#define | IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)

Functions

ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Detailed Description

COMP LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_comp.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 43 of file stm32f3xx_ll_comp.c.

Referenced by LL_COMP_DeInit(), and LL_COMP_Init().

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_crc.c File Reference

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stm32f3xx_ll_crc.c File Reference

CRC LL module driver. More...

#include "stm32f3xx_ll_crc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)

Functions

ErrorStatus | LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Detailed Description

CRC LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_crc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 43 of file stm32f3xx_ll_crc.c.

Referenced by LL_CRC_DeInit().

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_dac.c File Reference

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Defines | Functions
stm32f3xx_ll_dac.c File Reference

DAC LL module driver. More...

#include "stm32f3xx_ll_dac.h"
#include "stm32f3xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)
#define | IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__)
#define | IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)

Functions

ErrorStatus | LL_DAC_DeInit (DAC_TypeDef *DACx)
De-initialize registers of the selected DAC instance to their default reset values.
ErrorStatus | LL_DAC_Init (DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
Initialize some features of DAC instance.
void | LL_DAC_StructInit (LL_DAC_InitTypeDef *DAC_InitStruct)
Set each LL_DAC_InitTypeDef field to default value.

Detailed Description

DAC LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_dac.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 44 of file stm32f3xx_ll_dac.c.

Referenced by LL_DAC_DeInit(), and LL_DAC_Init().

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_dma.c File Reference

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Defines | Functions
stm32f3xx_ll_dma.c File Reference

DMA LL module driver. More...

#include "stm32f3xx_ll_dma.h"
#include "stm32f3xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_DMA_DIRECTION(__VALUE__)
#define | IS_LL_DMA_MODE(__VALUE__)
#define | IS_LL_DMA_PERIPHINCMODE(__VALUE__)
#define | IS_LL_DMA_MEMORYINCMODE(__VALUE__)
#define | IS_LL_DMA_PERIPHDATASIZE(__VALUE__)
#define | IS_LL_DMA_MEMORYDATASIZE(__VALUE__)
#define | IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_DMA_PRIORITY(__VALUE__)
#define | IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)

Functions

uint32_t | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
uint32_t | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Detailed Description

DMA LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_dma.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 43 of file stm32f3xx_ll_dma.c.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_exti.c File Reference

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Defines | Functions
stm32f3xx_ll_exti.c File Reference

EXTI LL module driver. More...

#include "stm32f3xx_ll_exti.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define | IS_LL_EXTI_MODE(__VALUE__)
#define | IS_LL_EXTI_TRIGGER(__VALUE__)

Functions

uint32_t | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
uint32_t | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Detailed Description

EXTI LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_exti.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 42 of file stm32f3xx_ll_exti.c.

Referenced by LL_EXTI_Init().

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_gpio.c File Reference

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Defines | Functions
stm32f3xx_ll_gpio.c File Reference

GPIO LL module driver. More...

#include "stm32f3xx_ll_gpio.h"
#include "stm32f3xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define | IS_LL_GPIO_MODE(__VALUE__)
#define | IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)
#define | IS_LL_GPIO_SPEED(__VALUE__)
#define | IS_LL_GPIO_PULL(__VALUE__)
#define | IS_LL_GPIO_ALTERNATE(__VALUE__)

Functions

ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Detailed Description

GPIO LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_gpio.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 43 of file stm32f3xx_ll_gpio.c.

Referenced by LL_GPIO_DeInit(), and LL_GPIO_Init().

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_hrtim.c File Reference

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Defines
stm32f3xx_ll_hrtim.c File Reference

HRTIM LL module driver. More...

#include "stm32f3xx_ll_hrtim.h"
#include "stm32f3xx_ll_bus.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0U)

Detailed Description

HRTIM LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_hrtim.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 44 of file stm32f3xx_ll_hrtim.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_hrtim.h File Reference

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stm32f3xx_ll_hrtim.h File Reference

Header file of HRTIM LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Detailed Description

Header file of HRTIM LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_hrtim.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_i2c.c File Reference

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Defines | Functions
stm32f3xx_ll_i2c.c File Reference

I2C LL module driver. More...

#include "stm32f3xx_ll_i2c.h"
#include "stm32f3xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)
#define | IS_LL_I2C_ANALOG_FILTER(__VALUE__)
#define | IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
#define | IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
#define | IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)
#define | IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)

Functions

uint32_t | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
uint32_t | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Detailed Description

I2C LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_i2c.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 43 of file stm32f3xx_ll_i2c.c.

Referenced by LL_I2C_DeInit(), and LL_I2C_Init().

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_opamp.c File Reference

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Defines
stm32f3xx_ll_opamp.c File Reference

OPAMP LL module driver. More...

#include "stm32f3xx_ll_opamp.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0U)

Detailed Description

OPAMP LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_opamp.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 43 of file stm32f3xx_ll_opamp.c.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_opamp.h File Reference

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stm32f3xx_ll_opamp.h File Reference

Header file of OPAMP LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Detailed Description

Header file of OPAMP LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_opamp.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_rcc.c File Reference

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stm32f3xx_ll_rcc.c File Reference

RCC LL module driver. More...

#include "stm32f3xx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_RCC_USART_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
#define | IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
#define | IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
#define | IS_LL_RCC_SDADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDADC_CLKSOURCE))
#define | IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))

Functions

uint32_t | RCC_GetSystemClockFreq (void)
Return SYSTEM clock frequency.
uint32_t | RCC_GetHCLKClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK clock frequency.
uint32_t | RCC_GetPCLK1ClockFreq (uint32_t HCLK_Frequency)
Return PCLK1 clock frequency.
uint32_t | RCC_GetPCLK2ClockFreq (uint32_t HCLK_Frequency)
Return PCLK2 clock frequency.
uint32_t | RCC_PLL_GetFreqDomain_SYS (void)
Return PLL clock frequency used for system domain.
ErrorStatus | LL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.
uint32_t | LL_RCC_GetSDADCClockFreq (uint32_t SDADCxSource)
Return SDADCx clock frequency.
uint32_t | LL_RCC_GetCECClockFreq (uint32_t CECxSource)
Return CECx clock frequency.

Variables

const uint8_t | aSDADCPrescTable [16] = {2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U}

Detailed Description

RCC LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_rcc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 42 of file stm32f3xx_ll_rcc.c.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetCECClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetSDADCClockFreq(), LL_RCC_GetUSARTClockFreq(), and LL_RCC_GetUSBClockFreq().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_rtc.c File Reference

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stm32f3xx_ll_rtc.c File Reference

RTC LL module driver. More...

#include "stm32f3xx_ll_rtc.h"
#include "stm32f3xx_ll_cortex.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU
#define | RTC_SYNCH_PRESC_DEFAULT 0x000000FFU
#define | RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define | RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define | IS_LL_RTC_HOURFORMAT(__VALUE__)
#define | IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
#define | IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
#define | IS_LL_RTC_FORMAT(__VALUE__)
#define | IS_LL_RTC_TIME_FORMAT(__VALUE__)
#define | IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
#define | IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
#define | IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
#define | IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
#define | IS_LL_RTC_WEEKDAY(__VALUE__)
#define | IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
#define | IS_LL_RTC_MONTH(__VALUE__)
#define | IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
#define | IS_LL_RTC_ALMA_MASK(__VALUE__)
#define | IS_LL_RTC_ALMB_MASK(__VALUE__)
#define | IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__)
#define | IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__)

Functions

ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

RTC LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_rtc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 43 of file stm32f3xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_EnterInitMode(), LL_RTC_ExitInitMode(), LL_RTC_Init(), LL_RTC_TIME_Init(), and LL_RTC_WaitForSynchro().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_spi.c File Reference

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Defines | Functions
stm32f3xx_ll_spi.c File Reference

SPI LL module driver. More...

#include "stm32f3xx_ll_spi.h"
#include "stm32f3xx_ll_bus.h"
#include "stm32f3xx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | SPI_CR1_CLEAR_MASK
#define | IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)
#define | IS_LL_SPI_MODE(__VALUE__)
#define | IS_LL_SPI_DATAWIDTH(__VALUE__)
#define | IS_LL_SPI_POLARITY(__VALUE__)
#define | IS_LL_SPI_PHASE(__VALUE__)
#define | IS_LL_SPI_NSS(__VALUE__)
#define | IS_LL_SPI_BAUDRATE(__VALUE__)
#define | IS_LL_SPI_BITORDER(__VALUE__)
#define | IS_LL_SPI_CRCCALCULATION(__VALUE__)
#define | IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
#define | I2S_I2SCFGR_CLEAR_MASK
#define | I2S_I2SPR_CLEAR_MASK 0x0002U
#define | IS_LL_I2S_DATAFORMAT(__VALUE__)
#define | IS_LL_I2S_CPOL(__VALUE__)
#define | IS_LL_I2S_STANDARD(__VALUE__)
#define | IS_LL_I2S_MODE(__VALUE__)
#define | IS_LL_I2S_MCLK_OUTPUT(__VALUE__)
#define | IS_LL_I2S_AUDIO_FREQ(__VALUE__)
#define | IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
#define | IS_LL_I2S_PRESCALER_PARITY(__VALUE__)

Functions

ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.
ErrorStatus | LL_I2S_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI/I2S registers to their default reset values.
ErrorStatus | LL_I2S_Init (SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
void | LL_I2S_StructInit (LL_I2S_InitTypeDef *I2S_InitStruct)
Set each LL_I2S_InitTypeDef field to default value.
void | LL_I2S_ConfigPrescaler (SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
Set linear and parity prescaler.

Detailed Description

SPI LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_spi.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 45 of file stm32f3xx_ll_spi.c.

Referenced by LL_I2S_ConfigPrescaler(), LL_I2S_Init(), LL_SPI_DeInit(), and LL_SPI_Init().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_tim.c File Reference

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Defines | Functions
stm32f3xx_ll_tim.c File Reference

TIM LL module driver. More...

#include "stm32f3xx_ll_tim.h"
#include "stm32f3xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_TIM_COUNTERMODE(__VALUE__)
#define | IS_LL_TIM_CLOCKDIVISION(__VALUE__)
#define | IS_LL_TIM_OCMODE(__VALUE__)
#define | IS_LL_TIM_OCSTATE(__VALUE__)
#define | IS_LL_TIM_OCPOLARITY(__VALUE__)
#define | IS_LL_TIM_OCIDLESTATE(__VALUE__)
#define | IS_LL_TIM_ACTIVEINPUT(__VALUE__)
#define | IS_LL_TIM_ICPSC(__VALUE__)
#define | IS_LL_TIM_IC_FILTER(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY(__VALUE__)
#define | IS_LL_TIM_ENCODERMODE(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__)
#define | IS_LL_TIM_OSSR_STATE(__VALUE__)
#define | IS_LL_TIM_OSSI_STATE(__VALUE__)
#define | IS_LL_TIM_LOCK_LEVEL(__VALUE__)
#define | IS_LL_TIM_BREAK_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK_POLARITY(__VALUE__)
#define | IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__)

Functions

static ErrorStatus | OC1Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 1.
static ErrorStatus | OC2Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 2.
static ErrorStatus | OC3Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 3.
static ErrorStatus | OC4Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 4.
static ErrorStatus | IC1Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 1.
static ErrorStatus | IC2Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 2.
static ErrorStatus | IC3Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 3.
static ErrorStatus | IC4Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 4.
ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.

Detailed Description

TIM LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_tim.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 44 of file stm32f3xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_BDTR_Init(), LL_TIM_DeInit(), LL_TIM_ENCODER_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_usart.c File Reference

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Defines | Functions
stm32f3xx_ll_usart.c File Reference

USART LL module driver. More...

#include "stm32f3xx_ll_usart.h"
#include "stm32f3xx_ll_rcc.h"
#include "stm32f3xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 9000000U)
#define | IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
#define | IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_USART_DIRECTION(__VALUE__)
#define | IS_LL_USART_PARITY(__VALUE__)
#define | IS_LL_USART_DATAWIDTH(__VALUE__)
#define | IS_LL_USART_OVERSAMPLING(__VALUE__)
#define | IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__)
#define | IS_LL_USART_CLOCKPHASE(__VALUE__)
#define | IS_LL_USART_CLOCKPOLARITY(__VALUE__)
#define | IS_LL_USART_CLOCKOUTPUT(__VALUE__)
#define | IS_LL_USART_STOPBITS(__VALUE__)
#define | IS_LL_USART_HWCONTROL(__VALUE__)

Functions

ErrorStatus | LL_USART_DeInit (USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Detailed Description

USART LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_usart.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 44 of file stm32f3xx_ll_usart.c.

Referenced by LL_USART_ClockInit(), LL_USART_DeInit(), and LL_USART_Init().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_utils.c File Reference

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Defines | Functions
stm32f3xx_ll_utils.c File Reference

UTILS LL module driver. More...

#include "stm32f3xx_ll_rcc.h"
#include "stm32f3xx_ll_utils.h"
#include "stm32f3xx_ll_system.h"
#include "stm32f3xx_ll_pwr.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | UTILS_PLL_OUTPUT_MAX 72000000U
#define | UTILS_HSE_FREQUENCY_MIN 4000000U
#define | UTILS_HSE_FREQUENCY_MAX 32000000U
#define | UTILS_LATENCY1_FREQ 24000000U
#define | UTILS_LATENCY2_FREQ 48000000U
#define | IS_LL_UTILS_SYSCLK_DIV(__VALUE__)
#define | IS_LL_UTILS_APB1_DIV(__VALUE__)
#define | IS_LL_UTILS_APB2_DIV(__VALUE__)
#define | IS_LL_UTILS_PLLMUL_VALUE(__VALUE__)
#define | IS_LL_UTILS_PREDIV_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
#define | IS_LL_UTILS_HSE_BYPASS(__STATE__)
#define | IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Functions

static uint32_t | UTILS_GetPLLOutputFrequency (uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
Function to check that PLL can be modified.
static ErrorStatus | UTILS_SetFlashLatency (uint32_t Frequency)
Update number of Flash wait states in line with new frequency and current voltage range.
static ErrorStatus | UTILS_EnablePLLAndSwitchSystem (uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
Function to enable PLL and switch system clock to PLL.
static ErrorStatus | UTILS_PLL_IsBusy (void)
Function to check that PLL can be modified.
void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

UTILS LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_utils.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 43 of file stm32f3xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), UTILS_EnablePLLAndSwitchSystem(), and UTILS_GetPLLOutputFrequency().

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

  • __ADC_MASK_SHIFT : stm32f3xx_ll_adc.h
  • __ADC_PTR_REG_OFFSET : stm32f3xx_ll_adc.h
  • __COMP_BITOFFSET_INSTANCE : stm32f3xx_ll_comp.h
  • __COMP_IS_INSTANCE_EVEN : stm32f3xx_ll_comp.h
  • __COMP_IS_INSTANCE_ODD : stm32f3xx_ll_comp.h
  • __DAC_MASK_SHIFT : stm32f3xx_ll_dac.h
  • __DAC_PTR_REG_OFFSET : stm32f3xx_ll_dac.h
  • __HAL_ADC_CLEAR_FLAG : stm32f3xx_hal_adc_ex.h
  • __HAL_ADC_DISABLE : stm32f3xx_hal_adc_ex.h
  • __HAL_ADC_DISABLE_IT : stm32f3xx_hal_adc_ex.h
  • __HAL_ADC_ENABLE : stm32f3xx_hal_adc_ex.h
  • __HAL_ADC_ENABLE_IT : stm32f3xx_hal_adc_ex.h
  • __HAL_ADC_GET_FLAG : stm32f3xx_hal_adc_ex.h
  • __HAL_ADC_GET_IT_SOURCE : stm32f3xx_hal_adc_ex.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32f3xx_hal_adc_ex.h , stm32f3xx_hal_adc.h
  • __HAL_CAN_CANCEL_TRANSMIT : stm32f3xx_hal_can.h
  • __HAL_CAN_CLEAR_FLAG : stm32f3xx_hal_can.h
  • __HAL_CAN_DBG_FREEZE : stm32f3xx_hal_can.h
  • __HAL_CAN_DISABLE_IT : stm32f3xx_hal_can.h
  • __HAL_CAN_ENABLE_IT : stm32f3xx_hal_can.h
  • __HAL_CAN_FIFO_RELEASE : stm32f3xx_hal_can.h
  • __HAL_CAN_GET_FLAG : stm32f3xx_hal_can.h
  • __HAL_CAN_GET_IT_SOURCE : stm32f3xx_hal_can.h
  • __HAL_CAN_MSG_PENDING : stm32f3xx_hal_can.h
  • __HAL_CAN_RESET_HANDLE_STATE : stm32f3xx_hal_can.h
  • __HAL_CAN_TRANSMIT_STATUS : stm32f3xx_hal_can.h
  • __HAL_CEC_CLEAR_FLAG : stm32f3xx_hal_cec.h
  • __HAL_CEC_CLEAR_OAR : stm32f3xx_hal_cec.h
  • __HAL_CEC_DISABLE : stm32f3xx_hal_cec.h
  • __HAL_CEC_DISABLE_IT : stm32f3xx_hal_cec.h
  • __HAL_CEC_ENABLE : stm32f3xx_hal_cec.h
  • __HAL_CEC_ENABLE_IT : stm32f3xx_hal_cec.h
  • __HAL_CEC_FIRST_BYTE_TX_SET : stm32f3xx_hal_cec.h
  • __HAL_CEC_GET_FLAG : stm32f3xx_hal_cec.h
  • __HAL_CEC_GET_IT_SOURCE : stm32f3xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_END_FLAG : stm32f3xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_START_FLAG : stm32f3xx_hal_cec.h
  • __HAL_CEC_LAST_BYTE_TX_SET : stm32f3xx_hal_cec.h
  • __HAL_CEC_RESET_HANDLE_STATE : stm32f3xx_hal_cec.h
  • __HAL_CEC_SET_OAR : stm32f3xx_hal_cec.h
  • __HAL_COMP_COMP1_EXTI_CLEAR_FLAG : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_EVENT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_IT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_EVENT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_IT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_GENERATE_SWIT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_GET_FLAG : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_CLEAR_FLAG : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_EVENT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_IT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_EVENT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_IT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_GENERATE_SWIT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_GET_FLAG : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_DISABLE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_ENABLE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_GET_FLAG : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_LOCK : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_RESET_HANDLE_STATE : stm32f3xx_hal_comp.h
  • __HAL_CRC_DR_RESET : stm32f3xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32f3xx_hal_crc.h
  • __HAL_CRC_INITIALCRCVALUE_CONFIG : stm32f3xx_hal_crc.h
  • __HAL_CRC_OUTPUTREVERSAL_DISABLE : stm32f3xx_hal_crc_ex.h
  • __HAL_CRC_OUTPUTREVERSAL_ENABLE : stm32f3xx_hal_crc_ex.h
  • __HAL_CRC_POLYNOMIAL_CONFIG : stm32f3xx_hal_crc_ex.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32f3xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32f3xx_hal_crc.h
  • __HAL_DAC_CLEAR_FLAG : stm32f3xx_hal_dac.h
  • __HAL_DAC_DISABLE : stm32f3xx_hal_dac.h
  • __HAL_DAC_DISABLE_IT : stm32f3xx_hal_dac.h
  • __HAL_DAC_ENABLE : stm32f3xx_hal_dac.h
  • __HAL_DAC_ENABLE_IT : stm32f3xx_hal_dac.h
  • __HAL_DAC_GET_FLAG : stm32f3xx_hal_dac.h
  • __HAL_DAC_GET_IT_SOURCE : stm32f3xx_hal_dac.h
  • __HAL_DAC_RESET_HANDLE_STATE : stm32f3xx_hal_dac.h
  • __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM12 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM13 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM14 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM15 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM16 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM17 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM5 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM6 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM7 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_IWDG : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_RTC : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM12 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM13 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM14 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM15 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM16 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM17 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM2 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM3 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM4 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM5 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM6 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM7 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_WWDG : stm32f3xx_hal.h
  • __HAL_DMA_CLEAR_FLAG : stm32f3xx_hal_dma_ex.h
  • __HAL_DMA_DISABLE : stm32f3xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32f3xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32f3xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32f3xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32f3xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32f3xx_hal_dma_ex.h
  • __HAL_DMA_GET_GI_FLAG_INDEX : stm32f3xx_hal_dma_ex.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32f3xx_hal_dma_ex.h
  • __HAL_DMA_GET_IT_SOURCE : stm32f3xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32f3xx_hal_dma_ex.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32f3xx_hal_dma_ex.h
  • __HAL_DMA_REMAP_CHANNEL_DISABLE : stm32f3xx_hal.h
  • __HAL_DMA_REMAP_CHANNEL_ENABLE : stm32f3xx_hal.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32f3xx_hal_dma.h
  • __HAL_FLASH_CLEAR_FLAG : stm32f3xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32f3xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32f3xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32f3xx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32f3xx_hal_flash.h
  • __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE : stm32f3xx_hal_flash.h
  • __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE : stm32f3xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_DISABLE : stm32f3xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_ENABLE : stm32f3xx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32f3xx_hal_flash.h
  • __HAL_FREEZE_CAN_DBGMCU : stm32f3xx_hal.h
  • __HAL_FREEZE_TIM18_DBGMCU : stm32f3xx_hal.h
  • __HAL_FREEZE_TIM19_DBGMCU : stm32f3xx_hal.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32f3xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32f3xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32f3xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32f3xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32f3xx_hal_gpio.h
  • __HAL_I2C_CLEAR_FLAG : stm32f3xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32f3xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32f3xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32f3xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32f3xx_hal_i2c.h
  • __HAL_I2C_GENERATE_NACK : stm32f3xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32f3xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32f3xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32f3xx_hal_i2c.h
  • __HAL_I2S_CLEAR_OVRFLAG : stm32f3xx_hal_i2s.h
  • __HAL_I2S_CLEAR_UDRFLAG : stm32f3xx_hal_i2s.h
  • __HAL_I2S_DISABLE : stm32f3xx_hal_i2s.h
  • __HAL_I2S_DISABLE_IT : stm32f3xx_hal_i2s.h
  • __HAL_I2S_ENABLE : stm32f3xx_hal_i2s.h
  • __HAL_I2S_ENABLE_IT : stm32f3xx_hal_i2s.h
  • __HAL_I2S_GET_FLAG : stm32f3xx_hal_i2s.h
  • __HAL_I2S_GET_IT_SOURCE : stm32f3xx_hal_i2s.h
  • __HAL_I2S_RESET_HANDLE_STATE : stm32f3xx_hal_i2s.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32f3xx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32f3xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32f3xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IT : stm32f3xx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32f3xx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32f3xx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32f3xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32f3xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32f3xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32f3xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32f3xx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32f3xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32f3xx_hal_irda.h
  • __HAL_IRDA_GET_IT : stm32f3xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32f3xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE : stm32f3xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE : stm32f3xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32f3xx_hal_irda.h
  • __HAL_IRDA_SEND_REQ : stm32f3xx_hal_irda.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32f3xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32f3xx_hal_iwdg.h
  • __HAL_PCD_CLEAR_FLAG : stm32f3xx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32f3xx_hal_pcd.h
  • __HAL_PWR_CLEAR_FLAG : stm32f3xx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32f3xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32f3xx_hal_pwr_ex.h
  • __HAL_RCC_ADC1_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_CONFIG : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_AHB_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_AHB_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_APB1_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_APB1_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_CAN1_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_CONFIG : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CLEAR_IT : stm32f3xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32f3xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DAC1_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DAC1_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DAC2_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DAC2_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DAC2_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DAC2_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DAC2_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DAC2_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DISABLE_IT : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_ENABLE_IT : stm32f3xx_hal_rcc.h
  • __HAL_RCC_FLITF_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_FLITF_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_FLITF_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_FLITF_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_ADC1_SOURCE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GET_CEC_SOURCE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_I2C1_SOURCE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_I2C2_SOURCE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_RTC_SOURCE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_SDADC_SOURCE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_USART1_SOURCE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_USART2_SOURCE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_USART3_SOURCE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_USB_SOURCE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOF_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOF_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_HSE_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_HSE_GET_PREDIV : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_HSE_PREDIV_CONFIG : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32f3xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_I2C1_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_CONFIG : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_LSE_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_LSEDRIVE_CONFIG : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_LSI_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_PLL_CONFIG : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_PLL_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_PWR_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_PWR_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SDADC1_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC1_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC1_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC1_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC1_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC1_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC2_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC2_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC2_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC2_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC2_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC2_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC3_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC3_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC3_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC3_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC3_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC3_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC_CONFIG : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SRAM_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SRAM_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SRAM_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM15_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM15_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM15_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM16_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM16_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM17_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM17_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM18_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM18_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM18_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM18_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM18_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM18_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM19_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM19_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM19_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM19_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM19_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM19_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM6_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM6_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TSC_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TSC_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TSC_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART1_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART2_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART3_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART3_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART3_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_USB_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_USB_CONFIG : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_USB_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_USB_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_USB_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_USB_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_WWDG_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_WWDG_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_WWDG_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_REMAPTRIGGER_DISABLE : stm32f3xx_hal.h
  • __HAL_REMAPTRIGGER_ENABLE : stm32f3xx_hal.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_FLAG : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GENERATE_SWIT : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GET_FLAG : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_DISABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_ENABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_DISABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_ENABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_DISABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_ENABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32f3xx_hal_rtc.h
  • __HAL_SDADC_CLEAR_FLAG : stm32f3xx_hal_sdadc.h
  • __HAL_SDADC_DISABLE_IT : stm32f3xx_hal_sdadc.h
  • __HAL_SDADC_ENABLE_IT : stm32f3xx_hal_sdadc.h
  • __HAL_SDADC_GET_FLAG : stm32f3xx_hal_sdadc.h
  • __HAL_SDADC_GET_IT_SOURCE : stm32f3xx_hal_sdadc.h
  • __HAL_SDADC_RESET_HANDLE_STATE : stm32f3xx_hal_sdadc.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IT : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_SEND_REQ : stm32f3xx_hal_smartcard.h
  • __HAL_SMBUS_CLEAR_FLAG : stm32f3xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE : stm32f3xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE_IT : stm32f3xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE : stm32f3xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE_IT : stm32f3xx_hal_smbus.h
  • __HAL_SMBUS_GENERATE_NACK : stm32f3xx_hal_smbus.h
  • __HAL_SMBUS_GET_FLAG : stm32f3xx_hal_smbus.h
  • __HAL_SMBUS_GET_IT_SOURCE : stm32f3xx_hal_smbus.h
  • __HAL_SMBUS_RESET_HANDLE_STATE : stm32f3xx_hal_smbus.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32f3xx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32f3xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32f3xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32f3xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32f3xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32f3xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32f3xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32f3xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32f3xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32f3xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32f3xx_hal_spi.h
  • __HAL_SYSCFG_BREAK_LOCKUP_LOCK : stm32f3xx_hal.h
  • __HAL_SYSCFG_BREAK_PVD_LOCK : stm32f3xx_hal.h
  • __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK : stm32f3xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_DISABLE : stm32f3xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_ENABLE : stm32f3xx_hal.h
  • __HAL_SYSCFG_INTERRUPT_DISABLE : stm32f3xx_hal.h
  • __HAL_SYSCFG_INTERRUPT_ENABLE : stm32f3xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_FLASH : stm32f3xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SRAM : stm32f3xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH : stm32f3xx_hal.h
  • __HAL_SYSCFG_VBAT_MONITORING_DISABLE : stm32f3xx_hal.h
  • __HAL_SYSCFG_VBAT_MONITORING_ENABLE : stm32f3xx_hal.h
  • __HAL_TIM_CLEAR_FLAG : stm32f3xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32f3xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32f3xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32f3xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32f3xx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxPRELOAD : stm32f3xx_hal_tim_ex.h
  • __HAL_TIM_ENABLE : stm32f3xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32f3xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32f3xx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxPRELOAD : stm32f3xx_hal_tim_ex.h
  • __HAL_TIM_GET_AUTORELOAD : stm32f3xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32f3xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32f3xx_hal_tim_ex.h
  • __HAL_TIM_GET_COUNTER : stm32f3xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32f3xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32f3xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32f3xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32f3xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32f3xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY : stm32f3xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32f3xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32f3xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32f3xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32f3xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32f3xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32f3xx_hal_tim_ex.h
  • __HAL_TIM_SET_COUNTER : stm32f3xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32f3xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32f3xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32f3xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32f3xx_hal_tim.h
  • __HAL_TSC_CLEAR_FLAG : stm32f3xx_hal_tsc.h
  • __HAL_TSC_CLOSE_ANALOG_SWITCH : stm32f3xx_hal_tsc.h
  • __HAL_TSC_DISABLE : stm32f3xx_hal_tsc.h
  • __HAL_TSC_DISABLE_CHANNEL : stm32f3xx_hal_tsc.h
  • __HAL_TSC_DISABLE_GROUP : stm32f3xx_hal_tsc.h
  • __HAL_TSC_DISABLE_HYSTERESIS : stm32f3xx_hal_tsc.h
  • __HAL_TSC_DISABLE_IT : stm32f3xx_hal_tsc.h
  • __HAL_TSC_DISABLE_SAMPLING : stm32f3xx_hal_tsc.h
  • __HAL_TSC_ENABLE : stm32f3xx_hal_tsc.h
  • __HAL_TSC_ENABLE_CHANNEL : stm32f3xx_hal_tsc.h
  • __HAL_TSC_ENABLE_GROUP : stm32f3xx_hal_tsc.h
  • __HAL_TSC_ENABLE_HYSTERESIS : stm32f3xx_hal_tsc.h
  • __HAL_TSC_ENABLE_IT : stm32f3xx_hal_tsc.h
  • __HAL_TSC_ENABLE_SAMPLING : stm32f3xx_hal_tsc.h
  • __HAL_TSC_GET_FLAG : stm32f3xx_hal_tsc.h
  • __HAL_TSC_GET_GROUP_STATUS : stm32f3xx_hal_tsc.h
  • __HAL_TSC_GET_IT_SOURCE : stm32f3xx_hal_tsc.h
  • __HAL_TSC_OPEN_ANALOG_SWITCH : stm32f3xx_hal_tsc.h
  • __HAL_TSC_RESET_HANDLE_STATE : stm32f3xx_hal_tsc.h
  • __HAL_TSC_SET_IODEF_INFLOAT : stm32f3xx_hal_tsc.h
  • __HAL_TSC_SET_IODEF_OUTPPLOW : stm32f3xx_hal_tsc.h
  • __HAL_TSC_SET_SYNC_POL_FALL : stm32f3xx_hal_tsc.h
  • __HAL_TSC_SET_SYNC_POL_RISE_HIGH : stm32f3xx_hal_tsc.h
  • __HAL_TSC_START_ACQ : stm32f3xx_hal_tsc.h
  • __HAL_TSC_STOP_ACQ : stm32f3xx_hal_tsc.h
  • __HAL_UART_CLEAR_FEFLAG : stm32f3xx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32f3xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32f3xx_hal_uart.h
  • __HAL_UART_CLEAR_IT : stm32f3xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32f3xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32f3xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32f3xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32f3xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32f3xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32f3xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32f3xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32f3xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32f3xx_hal_uart.h
  • __HAL_UART_GET_IT : stm32f3xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32f3xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32f3xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32f3xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32f3xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32f3xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32f3xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32f3xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32f3xx_hal_uart.h
  • __HAL_UART_SEND_REQ : stm32f3xx_hal_uart.h
  • __HAL_UNFREEZE_CAN_DBGMCU : stm32f3xx_hal.h
  • __HAL_UNFREEZE_TIM18_DBGMCU : stm32f3xx_hal.h
  • __HAL_UNFREEZE_TIM19_DBGMCU : stm32f3xx_hal.h
  • __HAL_USART_CLEAR_FEFLAG : stm32f3xx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32f3xx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32f3xx_hal_usart.h
  • __HAL_USART_CLEAR_IT : stm32f3xx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32f3xx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32f3xx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32f3xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32f3xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32f3xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32f3xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32f3xx_hal_usart.h
  • __HAL_USART_FLUSH_DRREGISTER : stm32f3xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32f3xx_hal_usart.h
  • __HAL_USART_GET_IT : stm32f3xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32f3xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_DISABLE : stm32f3xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_ENABLE : stm32f3xx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32f3xx_hal_usart.h
  • __HAL_USART_SEND_REQ : stm32f3xx_hal_usart.h
  • __HAL_USB_EXTI_GENERATE_SWIT : stm32f3xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG : stm32f3xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_DISABLE_IT : stm32f3xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32f3xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_IT : stm32f3xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32f3xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f3xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_GET_FLAG : stm32f3xx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32f3xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32f3xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32f3xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32f3xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32f3xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32f3xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32f3xx_hal_wwdg.h
  • __LL_ADC_ANALOGWD_CHANNEL_GROUP : stm32f3xx_ll_adc.h
  • __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION : stm32f3xx_ll_adc.h
  • __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION : stm32f3xx_ll_adc.h
  • __LL_ADC_CALC_DATA_TO_VOLTAGE : stm32f3xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE : stm32f3xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32f3xx_ll_adc.h
  • __LL_ADC_CALC_VREFANALOG_VOLTAGE : stm32f3xx_ll_adc.h
  • __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32f3xx_ll_adc.h
  • __LL_ADC_CHANNEL_TO_DECIMAL_NB : stm32f3xx_ll_adc.h
  • __LL_ADC_COMMON_INSTANCE : stm32f3xx_ll_adc.h
  • __LL_ADC_CONVERT_DATA_RESOLUTION : stm32f3xx_ll_adc.h
  • __LL_ADC_DECIMAL_NB_TO_CHANNEL : stm32f3xx_ll_adc.h
  • __LL_ADC_DIGITAL_SCALE : stm32f3xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL : stm32f3xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32f3xx_ll_adc.h
  • __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32f3xx_ll_adc.h
  • __LL_COMP_COMMON_INSTANCE : stm32f3xx_ll_comp.h
  • __LL_DAC_CALC_VOLTAGE_TO_DATA : stm32f3xx_ll_dac.h
  • __LL_DAC_CHANNEL_TO_DECIMAL_NB : stm32f3xx_ll_dac.h
  • __LL_DAC_DECIMAL_NB_TO_CHANNEL : stm32f3xx_ll_dac.h
  • __LL_DAC_DIGITAL_SCALE : stm32f3xx_ll_dac.h
  • __LL_DMA_GET_CHANNEL : stm32f3xx_ll_dma.h
  • __LL_DMA_GET_CHANNEL_INSTANCE : stm32f3xx_ll_dma.h
  • __LL_DMA_GET_INSTANCE : stm32f3xx_ll_dma.h
  • __LL_I2C_CONVERT_TIMINGS : stm32f3xx_ll_i2c.h
  • __LL_RCC_CALC_HCLK_FREQ : stm32f3xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK1_FREQ : stm32f3xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK2_FREQ : stm32f3xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_FREQ : stm32f3xx_ll_rcc.h
  • __LL_RTC_CONVERT_BCD2BIN : stm32f3xx_ll_rtc.h
  • __LL_RTC_CONVERT_BIN2BCD : stm32f3xx_ll_rtc.h
  • __LL_RTC_GET_DAY : stm32f3xx_ll_rtc.h
  • __LL_RTC_GET_HOUR : stm32f3xx_ll_rtc.h
  • __LL_RTC_GET_MINUTE : stm32f3xx_ll_rtc.h
  • __LL_RTC_GET_MONTH : stm32f3xx_ll_rtc.h
  • __LL_RTC_GET_SECOND : stm32f3xx_ll_rtc.h
  • __LL_RTC_GET_WEEKDAY : stm32f3xx_ll_rtc.h
  • __LL_RTC_GET_YEAR : stm32f3xx_ll_rtc.h
  • __LL_TIM_CALC_ARR : stm32f3xx_ll_tim.h
  • __LL_TIM_CALC_DEADTIME : stm32f3xx_ll_tim.h
  • __LL_TIM_CALC_DELAY : stm32f3xx_ll_tim.h
  • __LL_TIM_CALC_PSC : stm32f3xx_ll_tim.h
  • __LL_TIM_CALC_PULSE : stm32f3xx_ll_tim.h
  • __LL_TIM_GET_ICPSC_RATIO : stm32f3xx_ll_tim.h
  • __LL_TIM_GETFLAG_UIFCPY : stm32f3xx_ll_tim.h
  • __LL_USART_DIV_SAMPLING16 : stm32f3xx_ll_usart.h
  • __LL_USART_DIV_SAMPLING8 : stm32f3xx_ll_usart.h
  • __STM32F3xx_HAL_VERSION : stm32f3xx_hal.c
  • __STM32F3xx_HAL_VERSION_MAIN : stm32f3xx_hal.c
  • __STM32F3xx_HAL_VERSION_RC : stm32f3xx_hal.c
  • __STM32F3xx_HAL_VERSION_SUB1 : stm32f3xx_hal.c
  • __STM32F3xx_HAL_VERSION_SUB2 : stm32f3xx_hal.c
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -

  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32f3xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32f3xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32f3xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_NONE : stm32f3xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32f3xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32f3xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32f3xx_hal_adc_ex.h
  • ADC_AWD_CR1_CHANNEL_MASK : stm32f3xx_ll_adc.h
  • ADC_AWD_CR1_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_AWD_CR_ALL_CHANNEL_MASK : stm32f3xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_MASK : stm32f3xx_ll_adc.h
  • ADC_AWD_EVENT : stm32f3xx_hal_adc_ex.h
  • ADC_AWD_TR1_HIGH_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_AWD_TR1_LOW_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_MASK : stm32f3xx_ll_adc.h
  • ADC_CALFACT_DIFF_GET : stm32f3xx_hal_adc_ex.h
  • ADC_CALFACT_DIFF_SET : stm32f3xx_hal_adc_ex.h
  • ADC_CALIBRATION_TIMEOUT : stm32f3xx_hal_adc_ex.c
  • ADC_CHANNEL_0 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_0_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_0_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_1 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_10 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_10_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_10_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_11 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_11_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_11_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_12 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_12_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_12_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_13 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_13_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_13_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_14 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_14_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_14_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_15 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_15_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_15_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_16 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_16_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_16_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_17 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_17_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_17_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_18 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_1_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_1_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_2 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_2_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_2_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_3 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_3_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_3_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_4 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_4_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_4_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_5 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_5_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_5_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_6 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_6_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_6_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_7 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_7_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_7_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_8 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_8_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_8_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_9 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_9_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_9_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_2 : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_MASK : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_ID_MASK : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_SMPRX_REGOFFSET_MASK : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_MASK : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_VBAT : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_VREFINT : stm32f3xx_hal_adc_ex.h
  • ADC_CLEAR_ERRORCODE : stm32f3xx_hal_adc_ex.h
  • ADC_CLOCK_PRESCALER_RANGE : stm32f3xx_hal_adc_ex.h
  • ADC_CONVCYCLES_MAX_RANGE : stm32f3xx_hal_adc_ex.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 : stm32f3xx_hal_adc_ex.c
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 : stm32f3xx_hal_adc_ex.c
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 : stm32f3xx_hal_adc_ex.c
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 : stm32f3xx_hal_adc_ex.c
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 : stm32f3xx_hal_adc_ex.c
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 : stm32f3xx_hal_adc_ex.c
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : stm32f3xx_hal_adc_ex.c
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : stm32f3xx_hal_adc_ex.c
  • ADC_ConversionStop_Disable() : stm32f3xx_hal_adc_ex.c
  • ADC_CR1_DISCONTINUOUS_NUM : stm32f3xx_hal_adc_ex.h
  • ADC_CR1_DUALMOD_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_CR1_SCAN_SET : stm32f3xx_hal_adc_ex.h
  • ADC_CR2_CONTINUOUS : stm32f3xx_hal_adc_ex.h
  • ADC_CYCLE_WORST_CASE_CPU_CYCLES : stm32f3xx_hal_adc_ex.c
  • ADC_DATAALIGN_LEFT : stm32f3xx_hal_adc_ex.h
  • ADC_DATAALIGN_RIGHT : stm32f3xx_hal_adc_ex.h
  • ADC_DISABLE_TIMEOUT : stm32f3xx_hal_adc_ex.c
  • ADC_DMAConvCplt() : stm32f3xx_hal_adc_ex.c
  • ADC_DMAError() : stm32f3xx_hal_adc_ex.c
  • ADC_DMAHalfConvCplt() : stm32f3xx_hal_adc_ex.c
  • ADC_Enable() : stm32f3xx_hal_adc_ex.c
  • ADC_ENABLE_TIMEOUT : stm32f3xx_hal_adc_ex.c
  • ADC_EXTERNALTRIG_EXT_IT11 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIG_T19_CC3 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIG_T19_CC4 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIG_T19_TRGO : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIG_T2_CC2 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIG_T3_TRGO : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIG_T4_CC4 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_EXT_IT11 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T19_CC3 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T19_CC4 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T19_TRGO : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T2_CC2 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T3_TRGO : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T4_CC4 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_EXT_IT15 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T19_CC1 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T19_CC2 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_CC1 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_TRGO : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC4 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T4_TRGO : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_NONE : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISING : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EXT_IT15 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T19_CC1 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T19_CC2 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T2_CC1 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T2_TRGO : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T3_CC4 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T4_TRGO : stm32f3xx_hal_adc_ex.h
  • ADC_FLAG_AWD : stm32f3xx_hal_adc_ex.h
  • ADC_FLAG_EOC : stm32f3xx_hal_adc_ex.h
  • ADC_FLAG_JEOC : stm32f3xx_hal_adc_ex.h
  • ADC_FLAG_JSTRT : stm32f3xx_hal_adc_ex.h
  • ADC_FLAG_POSTCONV_ALL : stm32f3xx_hal_adc_ex.h
  • ADC_FLAG_STRT : stm32f3xx_hal_adc_ex.h
  • ADC_GET_CLOCK_PRESCALER : stm32f3xx_hal_adc_ex.h
  • ADC_HandleTypeDef : stm32f3xx_hal_adc.h
  • ADC_INJ_JDRX_REGOFFSET_MASK : stm32f3xx_ll_adc.h
  • ADC_INJ_JOFRX_REGOFFSET_MASK : stm32f3xx_ll_adc.h
  • ADC_INJ_RANK_1_JSQR_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_INJ_RANK_2_JSQR_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_INJ_RANK_3_JSQR_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_INJ_RANK_4_JSQR_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_INJ_RANK_ID_JSQR_MASK : stm32f3xx_ll_adc.h
  • ADC_INJECTED_GROUP : stm32f3xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_1 : stm32f3xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32f3xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32f3xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32f3xx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32f3xx_hal_adc_ex.h
  • ADC_IS_ENABLE : stm32f3xx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32f3xx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_REGULAR : stm32f3xx_hal_adc_ex.h
  • ADC_IT_AWD : stm32f3xx_hal_adc_ex.h
  • ADC_IT_EOC : stm32f3xx_hal_adc_ex.h
  • ADC_IT_JEOC : stm32f3xx_hal_adc_ex.h
  • ADC_JDR1_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_JDR2_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_JDR3_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_JDR4_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_JOFR1_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_JOFR2_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_JOFR3_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_JOFR4_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_JSQR_JL_SHIFT : stm32f3xx_hal_adc_ex.h
  • ADC_JSQR_RK_JL : stm32f3xx_hal_adc_ex.h
  • ADC_JSWSTART : stm32f3xx_hal_adc_ex.h
  • ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES : stm32f3xx_hal_adc_ex.c
  • ADC_REG_RANK_10_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_11_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_12_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_13_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_14_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_15_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_16_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_1_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_2_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_3_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_4_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_5_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_6_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_7_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_8_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_9_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_ID_SQRX_MASK : stm32f3xx_ll_adc.h
  • ADC_REG_SQRX_REGOFFSET_MASK : stm32f3xx_ll_adc.h
  • ADC_REGULAR_GROUP : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_INJECTED_GROUP : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_1 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_10 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_11 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_12 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_13 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_14 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_15 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_16 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_2 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_3 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_4 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_5 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_6 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_7 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_8 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_9 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_13CYCLES_5 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_1CYCLE_5 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_239CYCLES_5 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_28CYCLES_5 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_41CYCLES_5 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_55CYCLES_5 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_71CYCLES_5 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_7CYCLES_5 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 : stm32f3xx_hal_adc_ex.h
  • ADC_SCAN_DISABLE : stm32f3xx_hal_adc_ex.h
  • ADC_SCAN_ENABLE : stm32f3xx_hal_adc_ex.h
  • ADC_SMPR1 : stm32f3xx_hal_adc_ex.h
  • ADC_SMPR1_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_SMPR2 : stm32f3xx_hal_adc_ex.h
  • ADC_SMPR2_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_SOFTWARE_START : stm32f3xx_hal_adc_ex.h
  • ADC_SQR1_L_SHIFT : stm32f3xx_hal_adc_ex.h
  • ADC_SQR1_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_SQR1_RK : stm32f3xx_hal_adc_ex.h
  • ADC_SQR2_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_SQR2_RK : stm32f3xx_hal_adc_ex.h
  • ADC_SQR3_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_SQR3_RK : stm32f3xx_hal_adc_ex.h
  • ADC_SQR4_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_STAB_DELAY_US : stm32f3xx_hal_adc_ex.c
  • ADC_STATE_CLR_SET : stm32f3xx_hal_adc_ex.h
  • ADC_SWSTART : stm32f3xx_hal_adc_ex.h
  • ADC_TEMPSENSOR_DELAY_US : stm32f3xx_hal_adc_ex.c
  • aPLLMULFactorTable : stm32f3xx_hal_rcc.c
  • aPredivFactorTable : stm32f3xx_hal_rcc.c
  • aSDADCPrescTable : stm32f3xx_ll_rcc.c
  • assert_param : stm32f3xx_ll_comp.c , stm32f3xx_ll_gpio.c , stm32f3xx_ll_rcc.c , stm32f3xx_ll_crc.c , stm32f3xx_ll_opamp.c , stm32f3xx_ll_dac.c , stm32f3xx_ll_tim.c , stm32f3xx_hal_conf.h , stm32f3xx_ll_usart.c , stm32f3xx_ll_utils.c , stm32f3xx_ll_spi.c , stm32f3xx_ll_hrtim.c , stm32f3xx_ll_i2c.c , stm32f3xx_ll_rtc.c , stm32f3xx_ll_exti.c , stm32f3xx_ll_adc.c , stm32f3xx_ll_dma.c
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- b -

  • BDCR_REG_INDEX : stm32f3xx_hal_rcc.h
  • BTABLE_ADDRESS : stm32f3xx_hal_pcd.c
  • BYPADDRPAR_BitNumber : stm32f3xx_hal.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- c -

  • CAN_BS1_10TQ : stm32f3xx_hal_can.h
  • CAN_BS1_11TQ : stm32f3xx_hal_can.h
  • CAN_BS1_12TQ : stm32f3xx_hal_can.h
  • CAN_BS1_13TQ : stm32f3xx_hal_can.h
  • CAN_BS1_14TQ : stm32f3xx_hal_can.h
  • CAN_BS1_15TQ : stm32f3xx_hal_can.h
  • CAN_BS1_16TQ : stm32f3xx_hal_can.h
  • CAN_BS1_1TQ : stm32f3xx_hal_can.h
  • CAN_BS1_2TQ : stm32f3xx_hal_can.h
  • CAN_BS1_3TQ : stm32f3xx_hal_can.h
  • CAN_BS1_4TQ : stm32f3xx_hal_can.h
  • CAN_BS1_5TQ : stm32f3xx_hal_can.h
  • CAN_BS1_6TQ : stm32f3xx_hal_can.h
  • CAN_BS1_7TQ : stm32f3xx_hal_can.h
  • CAN_BS1_8TQ : stm32f3xx_hal_can.h
  • CAN_BS1_9TQ : stm32f3xx_hal_can.h
  • CAN_BS2_1TQ : stm32f3xx_hal_can.h
  • CAN_BS2_2TQ : stm32f3xx_hal_can.h
  • CAN_BS2_3TQ : stm32f3xx_hal_can.h
  • CAN_BS2_4TQ : stm32f3xx_hal_can.h
  • CAN_BS2_5TQ : stm32f3xx_hal_can.h
  • CAN_BS2_6TQ : stm32f3xx_hal_can.h
  • CAN_BS2_7TQ : stm32f3xx_hal_can.h
  • CAN_BS2_8TQ : stm32f3xx_hal_can.h
  • CAN_FIFO0 : stm32f3xx_hal_can.h
  • CAN_FIFO1 : stm32f3xx_hal_can.h
  • CAN_FILTER_FIFO0 : stm32f3xx_hal_can.h
  • CAN_FILTER_FIFO1 : stm32f3xx_hal_can.h
  • CAN_FILTERMODE_IDLIST : stm32f3xx_hal_can.h
  • CAN_FILTERMODE_IDMASK : stm32f3xx_hal_can.h
  • CAN_FILTERSCALE_16BIT : stm32f3xx_hal_can.h
  • CAN_FILTERSCALE_32BIT : stm32f3xx_hal_can.h
  • CAN_FLAG_BOF : stm32f3xx_hal_can.h
  • CAN_FLAG_EPV : stm32f3xx_hal_can.h
  • CAN_FLAG_ERRI : stm32f3xx_hal_can.h
  • CAN_FLAG_EWG : stm32f3xx_hal_can.h
  • CAN_FLAG_FF0 : stm32f3xx_hal_can.h
  • CAN_FLAG_FF1 : stm32f3xx_hal_can.h
  • CAN_FLAG_FOV0 : stm32f3xx_hal_can.h
  • CAN_FLAG_FOV1 : stm32f3xx_hal_can.h
  • CAN_FLAG_INAK : stm32f3xx_hal_can.h
  • CAN_FLAG_MASK : stm32f3xx_hal_can.h
  • CAN_FLAG_RQCP0 : stm32f3xx_hal_can.h
  • CAN_FLAG_RQCP1 : stm32f3xx_hal_can.h
  • CAN_FLAG_RQCP2 : stm32f3xx_hal_can.h
  • CAN_FLAG_SLAK : stm32f3xx_hal_can.h
  • CAN_FLAG_SLAKI : stm32f3xx_hal_can.h
  • CAN_FLAG_TME0 : stm32f3xx_hal_can.h
  • CAN_FLAG_TME1 : stm32f3xx_hal_can.h
  • CAN_FLAG_TME2 : stm32f3xx_hal_can.h
  • CAN_FLAG_TXOK0 : stm32f3xx_hal_can.h
  • CAN_FLAG_TXOK1 : stm32f3xx_hal_can.h
  • CAN_FLAG_TXOK2 : stm32f3xx_hal_can.h
  • CAN_FLAG_WKU : stm32f3xx_hal_can.h
  • CAN_ID_EXT : stm32f3xx_hal_can.h
  • CAN_ID_STD : stm32f3xx_hal_can.h
  • CAN_INITSTATUS_FAILED : stm32f3xx_hal_can.h
  • CAN_INITSTATUS_SUCCESS : stm32f3xx_hal_can.h
  • CAN_IT_BOF : stm32f3xx_hal_can.h
  • CAN_IT_EPV : stm32f3xx_hal_can.h
  • CAN_IT_ERR : stm32f3xx_hal_can.h
  • CAN_IT_EWG : stm32f3xx_hal_can.h
  • CAN_IT_FF0 : stm32f3xx_hal_can.h
  • CAN_IT_FF1 : stm32f3xx_hal_can.h
  • CAN_IT_FMP0 : stm32f3xx_hal_can.h
  • CAN_IT_FMP1 : stm32f3xx_hal_can.h
  • CAN_IT_FOV0 : stm32f3xx_hal_can.h
  • CAN_IT_FOV1 : stm32f3xx_hal_can.h
  • CAN_IT_LEC : stm32f3xx_hal_can.h
  • CAN_IT_SLK : stm32f3xx_hal_can.h
  • CAN_IT_TME : stm32f3xx_hal_can.h
  • CAN_IT_WKU : stm32f3xx_hal_can.h
  • CAN_MODE_LOOPBACK : stm32f3xx_hal_can.h
  • CAN_MODE_NORMAL : stm32f3xx_hal_can.h
  • CAN_MODE_SILENT : stm32f3xx_hal_can.h
  • CAN_MODE_SILENT_LOOPBACK : stm32f3xx_hal_can.h
  • CAN_Receive_IT() : stm32f3xx_hal_can.c
  • CAN_RTR_DATA : stm32f3xx_hal_can.h
  • CAN_RTR_REMOTE : stm32f3xx_hal_can.h
  • CAN_SJW_1TQ : stm32f3xx_hal_can.h
  • CAN_SJW_2TQ : stm32f3xx_hal_can.h
  • CAN_SJW_3TQ : stm32f3xx_hal_can.h
  • CAN_SJW_4TQ : stm32f3xx_hal_can.h
  • CAN_TIMEOUT_VALUE : stm32f3xx_hal_can.c
  • CAN_Transmit_IT() : stm32f3xx_hal_can.c
  • CAN_TXMAILBOX_0 : stm32f3xx_hal_can.h
  • CAN_TXMAILBOX_1 : stm32f3xx_hal_can.h
  • CAN_TXMAILBOX_2 : stm32f3xx_hal_can.h
  • CAN_TXSTATUS_NOMAILBOX : stm32f3xx_hal_can.h
  • CEC_0_5_BITPERIOD_SFT : stm32f3xx_hal_cec.h
  • CEC_1_5_BITPERIOD_SFT : stm32f3xx_hal_cec.h
  • CEC_2_5_BITPERIOD_SFT : stm32f3xx_hal_cec.h
  • CEC_3_5_BITPERIOD_SFT : stm32f3xx_hal_cec.h
  • CEC_4_5_BITPERIOD_SFT : stm32f3xx_hal_cec.h
  • CEC_5_5_BITPERIOD_SFT : stm32f3xx_hal_cec.h
  • CEC_6_5_BITPERIOD_SFT : stm32f3xx_hal_cec.h
  • CEC_BRE_ERRORBIT_GENERATION : stm32f3xx_hal_cec.h
  • CEC_BRE_ERRORBIT_NO_GENERATION : stm32f3xx_hal_cec.h
  • CEC_BROADCASTERROR_ERRORBIT_GENERATION : stm32f3xx_hal_cec.h
  • CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32f3xx_hal_cec.h
  • CEC_CFGR_OAR_LSB_POS : stm32f3xx_hal_cec.h
  • CEC_DEFAULT_SFT : stm32f3xx_hal_cec.h
  • CEC_EXTENDED_TOLERANCE : stm32f3xx_hal_cec.h
  • CEC_FLAG_ARBLST : stm32f3xx_hal_cec.h
  • CEC_FLAG_BRE : stm32f3xx_hal_cec.h
  • CEC_FLAG_LBPE : stm32f3xx_hal_cec.h
  • CEC_FLAG_RXACKE : stm32f3xx_hal_cec.h
  • CEC_FLAG_RXBR : stm32f3xx_hal_cec.h
  • CEC_FLAG_RXEND : stm32f3xx_hal_cec.h
  • CEC_FLAG_RXOVR : stm32f3xx_hal_cec.h
  • CEC_FLAG_SBPE : stm32f3xx_hal_cec.h
  • CEC_FLAG_TXACKE : stm32f3xx_hal_cec.h
  • CEC_FLAG_TXBR : stm32f3xx_hal_cec.h
  • CEC_FLAG_TXEND : stm32f3xx_hal_cec.h
  • CEC_FLAG_TXERR : stm32f3xx_hal_cec.h
  • CEC_FLAG_TXUDR : stm32f3xx_hal_cec.h
  • CEC_FULL_LISTENING_MODE : stm32f3xx_hal_cec.h
  • CEC_IER_RX_ALL_ERR : stm32f3xx_hal_cec.h
  • CEC_IER_TX_ALL_ERR : stm32f3xx_hal_cec.h
  • CEC_INITIATOR_LSB_POS : stm32f3xx_hal_cec.h
  • CEC_ISR_ALL_ERROR : stm32f3xx_hal_cec.h
  • CEC_IT_ARBLST : stm32f3xx_hal_cec.h
  • CEC_IT_BRE : stm32f3xx_hal_cec.h
  • CEC_IT_LBPE : stm32f3xx_hal_cec.h
  • CEC_IT_RXACKE : stm32f3xx_hal_cec.h
  • CEC_IT_RXBR : stm32f3xx_hal_cec.h
  • CEC_IT_RXEND : stm32f3xx_hal_cec.h
  • CEC_IT_RXOVR : stm32f3xx_hal_cec.h
  • CEC_IT_SBPE : stm32f3xx_hal_cec.h
  • CEC_IT_TXACKE : stm32f3xx_hal_cec.h
  • CEC_IT_TXBR : stm32f3xx_hal_cec.h
  • CEC_IT_TXEND : stm32f3xx_hal_cec.h
  • CEC_IT_TXERR : stm32f3xx_hal_cec.h
  • CEC_IT_TXUDR : stm32f3xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_GENERATION : stm32f3xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_NO_GENERATION : stm32f3xx_hal_cec.h
  • CEC_NO_RX_STOP_ON_BRE : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_0 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_1 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_10 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_11 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_12 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_13 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_14 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_2 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_3 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_4 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_5 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_6 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_7 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_8 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_9 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_NONE : stm32f3xx_hal_cec.h
  • CEC_REDUCED_LISTENING_MODE : stm32f3xx_hal_cec.h
  • CEC_RX_STOP_ON_BRE : stm32f3xx_hal_cec.h
  • CEC_SFT_START_ON_TX_RX_END : stm32f3xx_hal_cec.h
  • CEC_SFT_START_ON_TXSOM : stm32f3xx_hal_cec.h
  • CEC_STANDARD_TOLERANCE : stm32f3xx_hal_cec.h
  • CFGR2_BYPADDRPAR_BB : stm32f3xx_hal.h
  • CFGR2_OFFSET : stm32f3xx_hal.h
  • CFGR_REG_INDEX : stm32f3xx_hal_rcc.h
  • CHANNEL_OFFSET_TAB : stm32f3xx_ll_dma.h
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32f3xx_hal_rcc.h
  • COMP_BLANKINGSRCE_NONE : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMP1_SHIFT : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMP2_SHIFT : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMPxBLANKING_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMPxHYST_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMPxINSEL_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMPxMODE_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMPxNONINSEL_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMPxOUTSEL_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMPxPOL_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMPxWNDWEN_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_RESET_PARAMETERS_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_RESET_VALUE : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_UPDATE_PARAMETERS_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_DEINIT : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_CLEAR_FLAG : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_DISABLE_EVENT : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_DISABLE_IT : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_ENABLE_EVENT : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_ENABLE_IT : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_FALLING_DISABLE : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_FALLING_ENABLE : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_GET_FLAG : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_LINE_COMP1 : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_LINE_COMP2 : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_RISING_DISABLE : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_RISING_ENABLE : stm32f3xx_hal_comp_ex.h
  • COMP_FLAG_LOCK : stm32f3xx_hal_comp_ex.h
  • COMP_GET_EXTI_LINE : stm32f3xx_hal_comp_ex.h
  • COMP_HYSTERESIS_HIGH : stm32f3xx_hal_comp_ex.h
  • COMP_HYSTERESIS_LOW : stm32f3xx_hal_comp_ex.h
  • COMP_HYSTERESIS_MEDIUM : stm32f3xx_hal_comp_ex.h
  • COMP_HYSTERESIS_NONE : stm32f3xx_hal_comp_ex.h
  • COMP_INIT : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_1_2VREFINT : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_1_4VREFINT : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_3_4VREFINT : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_DAC1 : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_DAC1_CH1 : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_DAC1_CH2 : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_DAC2 : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_DAC2_CH1 : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_IO1 : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_SELECTION : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_VREFINT : stm32f3xx_hal_comp_ex.h
  • COMP_LOCK_DISABLE : stm32f3xx_hal_comp.c
  • COMP_LOCK_ENABLE : stm32f3xx_hal_comp.c
  • COMP_MODE_HIGHSPEED : stm32f3xx_hal_comp_ex.h
  • COMP_MODE_LOWPOWER : stm32f3xx_hal_comp_ex.h
  • COMP_MODE_MEDIUMSPEED : stm32f3xx_hal_comp_ex.h
  • COMP_MODE_ULTRALOWPOWER : stm32f3xx_hal_comp_ex.h
  • COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED : stm32f3xx_hal_comp_ex.h
  • COMP_NONINVERTINGINPUT_IO1 : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_COMP1_TIM3IC1 : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_COMP1_TIM3OCREFCLR : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_COMP2_TIM3IC1 : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_COMP2_TIM3OCREFCLR : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_NONE : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_TIM15BKIN : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_TIM16BKIN : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_TIM2IC4 : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_TIM2OCREFCLR : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_TIM4IC1 : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_TIM4OCREFCLR : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_TIM5IC4 : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_TIM5OCREFCLR : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUTLEVEL_HIGH : stm32f3xx_hal_comp.h
  • COMP_OUTPUTLEVEL_LOW : stm32f3xx_hal_comp.h
  • COMP_OUTPUTPOL_INVERTED : stm32f3xx_hal_comp.h
  • COMP_OUTPUTPOL_NONINVERTED : stm32f3xx_hal_comp.h
  • COMP_STATE_BIT_LOCK : stm32f3xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_FALLING : stm32f3xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING : stm32f3xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING_FALLING : stm32f3xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_FALLING : stm32f3xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING : stm32f3xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING_FALLING : stm32f3xx_hal_comp.h
  • COMP_TRIGGERMODE_NONE : stm32f3xx_hal_comp.h
  • COMP_WINDOWMODE_DISABLE : stm32f3xx_hal_comp_ex.h
  • COMP_WINDOWMODE_ENABLE : stm32f3xx_hal_comp_ex.h
  • COMPX : stm32f3xx_ll_comp.h
  • COMPX_BASE : stm32f3xx_ll_comp.h
  • CR_REG_INDEX : stm32f3xx_hal_rcc.h
  • CRC_Handle_16() : stm32f3xx_hal_crc.c
  • CRC_Handle_8() : stm32f3xx_hal_crc.c
  • CRC_INPUTDATA_FORMAT_BYTES : stm32f3xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_HALFWORDS : stm32f3xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_UNDEFINED : stm32f3xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_WORDS : stm32f3xx_hal_crc.h
  • CRC_INPUTDATA_INVERSION_BYTE : stm32f3xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_HALFWORD : stm32f3xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_NONE : stm32f3xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_WORD : stm32f3xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_DISABLE : stm32f3xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_ENABLE : stm32f3xx_hal_crc_ex.h
  • CRC_POLYLENGTH_16B : stm32f3xx_hal_crc.h
  • CRC_POLYLENGTH_32B : stm32f3xx_hal_crc.h
  • CRC_POLYLENGTH_7B : stm32f3xx_hal_crc.h
  • CRC_POLYLENGTH_8B : stm32f3xx_hal_crc.h
  • CSR_REG_INDEX : stm32f3xx_hal_rcc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- d -

  • DAC_ALIGN_12B_L : stm32f3xx_hal_dac.h
  • DAC_ALIGN_12B_R : stm32f3xx_hal_dac.h
  • DAC_ALIGN_8B_R : stm32f3xx_hal_dac.h
  • DAC_CHANNEL_1 : stm32f3xx_hal_dac_ex.h
  • DAC_CHANNEL_2 : stm32f3xx_hal_dac_ex.h
  • DAC_CR_CH1_BITOFFSET : stm32f3xx_ll_dac.h
  • DAC_CR_CH2_BITOFFSET : stm32f3xx_ll_dac.h
  • DAC_CR_CHX_BITOFFSET_MASK : stm32f3xx_ll_dac.h
  • DAC_DHR12LD_DACC2DHR_BITOFFSET_POS : stm32f3xx_ll_dac.h
  • DAC_DHR12R1_ALIGNMENT : stm32f3xx_hal_dac.h
  • DAC_DHR12R2_ALIGNMENT : stm32f3xx_hal_dac.h
  • DAC_DHR12RD_ALIGNMENT : stm32f3xx_hal_dac.h
  • DAC_DHR12RD_DACC2DHR_BITOFFSET_POS : stm32f3xx_ll_dac.h
  • DAC_DHR8RD_DACC2DHR_BITOFFSET_POS : stm32f3xx_ll_dac.h
  • DAC_DIGITAL_SCALE_12BITS : stm32f3xx_ll_dac.h
  • DAC_DMAConvCpltCh1() : stm32f3xx_hal_dac_ex.c
  • DAC_DMAConvCpltCh2() : stm32f3xx_hal_dac_ex.c
  • DAC_DMAErrorCh1() : stm32f3xx_hal_dac_ex.c
  • DAC_DMAErrorCh2() : stm32f3xx_hal_dac_ex.c
  • DAC_DMAHalfConvCpltCh1() : stm32f3xx_hal_dac_ex.c
  • DAC_DMAHalfConvCpltCh2() : stm32f3xx_hal_dac_ex.c
  • DAC_FLAG_DMAUDR1 : stm32f3xx_hal_dac.h
  • DAC_FLAG_DMAUDR2 : stm32f3xx_hal_dac.h
  • DAC_HandleTypeDef : stm32f3xx_hal_dac.h
  • DAC_IT_DMAUDR1 : stm32f3xx_hal_dac.h
  • DAC_IT_DMAUDR2 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BIT0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS10_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS11_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS1_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS2_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS3_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS4_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS5_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS6_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS7_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS8_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS9_0 : stm32f3xx_hal_dac.h
  • DAC_OUTPUTBUFFER_DISABLE : stm32f3xx_hal_dac.h
  • DAC_OUTPUTBUFFER_ENABLE : stm32f3xx_hal_dac.h
  • DAC_REG_DHR12L1_REGOFFSET : stm32f3xx_ll_dac.h
  • DAC_REG_DHR12L2_REGOFFSET : stm32f3xx_ll_dac.h
  • DAC_REG_DHR12LX_REGOFFSET_MASK : stm32f3xx_ll_dac.h
  • DAC_REG_DHR12R1_REGOFFSET : stm32f3xx_ll_dac.h
  • DAC_REG_DHR12R2_REGOFFSET : stm32f3xx_ll_dac.h
  • DAC_REG_DHR12RX_REGOFFSET_MASK : stm32f3xx_ll_dac.h
  • DAC_REG_DHR8R1_REGOFFSET : stm32f3xx_ll_dac.h
  • DAC_REG_DHR8R2_REGOFFSET : stm32f3xx_ll_dac.h
  • DAC_REG_DHR8RX_REGOFFSET_MASK : stm32f3xx_ll_dac.h
  • DAC_REG_DHRX_REGOFFSET_MASK : stm32f3xx_ll_dac.h
  • DAC_REG_DOR1_REGOFFSET : stm32f3xx_ll_dac.h
  • DAC_REG_DOR2_REGOFFSET : stm32f3xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_MASK : stm32f3xx_ll_dac.h
  • DAC_SWTR_CH1 : stm32f3xx_ll_dac.h
  • DAC_SWTR_CH2 : stm32f3xx_ll_dac.h
  • DAC_SWTR_CHX_MASK : stm32f3xx_ll_dac.h
  • DAC_TRIANGLEAMPLITUDE_1 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_1023 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_127 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_15 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_2047 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_255 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_3 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_31 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_4095 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_511 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_63 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_7 : stm32f3xx_hal_dac.h
  • DAC_TRIGGER_EXT_IT9 : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_NONE : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_SOFTWARE : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_T18_TRGO : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_T2_TRGO : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_T3_TRGO : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_T4_TRGO : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_T5_TRGO : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_T6_TRGO : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_T7_TRGO : stm32f3xx_hal_dac_ex.h
  • DATA_CACHE_ENABLE : stm32f3xx_hal_conf.h
  • DEFAULT_CRC32_POLY : stm32f3xx_hal_crc.h
  • DEFAULT_CRC_INITVALUE : stm32f3xx_hal_crc.h
  • DEFAULT_INIT_VALUE_DISABLE : stm32f3xx_hal_crc.h
  • DEFAULT_INIT_VALUE_ENABLE : stm32f3xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_DISABLE : stm32f3xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_ENABLE : stm32f3xx_hal_crc.h
  • DEP0CTL_MPS_16 : stm32f3xx_hal_pcd.h
  • DEP0CTL_MPS_32 : stm32f3xx_hal_pcd.h
  • DEP0CTL_MPS_64 : stm32f3xx_hal_pcd.h
  • DEP0CTL_MPS_8 : stm32f3xx_hal_pcd.h
  • DMA_CalcBaseAndBitshift() : stm32f3xx_hal_dma.c
  • DMA_CIRCULAR : stm32f3xx_hal_dma.h
  • DMA_FLAG_GL1 : stm32f3xx_hal_dma.h
  • DMA_FLAG_GL2 : stm32f3xx_hal_dma.h
  • DMA_FLAG_GL3 : stm32f3xx_hal_dma.h
  • DMA_FLAG_GL4 : stm32f3xx_hal_dma.h
  • DMA_FLAG_GL5 : stm32f3xx_hal_dma.h
  • DMA_FLAG_GL6 : stm32f3xx_hal_dma.h
  • DMA_FLAG_GL7 : stm32f3xx_hal_dma.h
  • DMA_FLAG_HT1 : stm32f3xx_hal_dma.h
  • DMA_FLAG_HT2 : stm32f3xx_hal_dma.h
  • DMA_FLAG_HT3 : stm32f3xx_hal_dma.h
  • DMA_FLAG_HT4 : stm32f3xx_hal_dma.h
  • DMA_FLAG_HT5 : stm32f3xx_hal_dma.h
  • DMA_FLAG_HT6 : stm32f3xx_hal_dma.h
  • DMA_FLAG_HT7 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TC1 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TC2 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TC3 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TC4 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TC5 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TC6 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TC7 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TE1 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TE2 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TE3 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TE4 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TE5 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TE6 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TE7 : stm32f3xx_hal_dma.h
  • DMA_HandleTypeDef : stm32f3xx_hal_dma.h
  • DMA_IT_HT : stm32f3xx_hal_dma.h
  • DMA_IT_TC : stm32f3xx_hal_dma.h
  • DMA_IT_TE : stm32f3xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32f3xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32f3xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32f3xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32f3xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32f3xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32f3xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32f3xx_hal_dma.h
  • DMA_NORMAL : stm32f3xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32f3xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32f3xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32f3xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32f3xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32f3xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32f3xx_hal_dma.h
  • DMA_PRIORITY_HIGH : stm32f3xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32f3xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32f3xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32f3xx_hal_dma.h
  • DMA_SetConfig() : stm32f3xx_hal_dma.c
  • DT_DELAY_1 : stm32f3xx_ll_tim.h
  • DT_DELAY_2 : stm32f3xx_ll_tim.h
  • DT_DELAY_3 : stm32f3xx_ll_tim.h
  • DT_DELAY_4 : stm32f3xx_ll_tim.h
  • DT_RANGE_1 : stm32f3xx_ll_tim.h
  • DT_RANGE_2 : stm32f3xx_ll_tim.h
  • DT_RANGE_3 : stm32f3xx_ll_tim.h
  • DT_RANGE_4 : stm32f3xx_ll_tim.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- e -

  • EXTERNAL_CLOCK_VALUE : stm32f3xx_hal_conf.h
  • EXTI_MODE : stm32f3xx_hal_gpio.c
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- f -

  • FALLING_EDGE : stm32f3xx_hal_gpio.c
  • FLASH_FLAG_BSY : stm32f3xx_hal_flash.h
  • FLASH_FLAG_EOP : stm32f3xx_hal_flash.h
  • FLASH_FLAG_PGERR : stm32f3xx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32f3xx_hal_flash.h
  • FLASH_IT_EOP : stm32f3xx_hal_flash.h
  • FLASH_IT_ERR : stm32f3xx_hal_flash.h
  • FLASH_LATENCY_0 : stm32f3xx_hal_flash.h
  • FLASH_LATENCY_1 : stm32f3xx_hal_flash.h
  • FLASH_LATENCY_2 : stm32f3xx_hal_flash.h
  • FLASH_MassErase() : stm32f3xx_hal_flash_ex.c
  • FLASH_OB_DisableWRP() : stm32f3xx_hal_flash_ex.c
  • FLASH_OB_EnableWRP() : stm32f3xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32f3xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32f3xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32f3xx_hal_flash_ex.c
  • FLASH_OB_ProgramData() : stm32f3xx_hal_flash_ex.c
  • FLASH_OB_RDP_LevelConfig() : stm32f3xx_hal_flash_ex.c
  • FLASH_OB_UserConfig() : stm32f3xx_hal_flash_ex.c
  • FLASH_PAGE_SIZE : stm32f3xx_hal_flash_ex.h
  • FLASH_PageErase() : stm32f3xx_hal_flash.c , stm32f3xx_hal_flash_ex.c
  • FLASH_POSITION_IWDGSW_BIT : stm32f3xx_hal_flash_ex.c
  • FLASH_POSITION_OB_USERDATA0_BIT : stm32f3xx_hal_flash_ex.c
  • FLASH_POSITION_OB_USERDATA1_BIT : stm32f3xx_hal_flash_ex.c
  • FLASH_PROC_MASSERASE : stm32f3xx_hal_flash.h
  • FLASH_PROC_NONE : stm32f3xx_hal_flash.h
  • FLASH_PROC_PAGEERASE : stm32f3xx_hal_flash.h
  • FLASH_PROC_PROGRAMDOUBLEWORD : stm32f3xx_hal_flash.h
  • FLASH_PROC_PROGRAMHALFWORD : stm32f3xx_hal_flash.h
  • FLASH_PROC_PROGRAMWORD : stm32f3xx_hal_flash.h
  • FLASH_ProcedureTypeDef : stm32f3xx_hal_flash.h
  • FLASH_Program_HalfWord() : stm32f3xx_hal_flash.c
  • FLASH_SetErrorCode() : stm32f3xx_hal_flash.c
  • FLASH_SIZE_DATA_REGISTER : stm32f3xx_hal_flash_ex.h
  • FLASH_TIMEOUT_VALUE : stm32f3xx_hal_flash.h
  • FLASH_TYPEERASE_MASSERASE : stm32f3xx_hal_flash_ex.h
  • FLASH_TYPEERASE_PAGES : stm32f3xx_hal_flash_ex.h
  • FLASH_TYPEPROGRAM_DOUBLEWORD : stm32f3xx_hal_flash.h
  • FLASH_TYPEPROGRAM_HALFWORD : stm32f3xx_hal_flash.h
  • FLASH_TYPEPROGRAM_WORD : stm32f3xx_hal_flash.h
  • FLASH_WaitForLastOperation() : stm32f3xx_hal_flash.c
  • FLASHSIZE_BASE_ADDRESS : stm32f3xx_ll_utils.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- g -

  • GPIO_AF0_MCO : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF0_RTC_50Hz : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF0_SWJ : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF0_TAMPER : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF0_TRACE : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF10_TIM12 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF10_TIM17 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF10_TIM2 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF10_TIM3 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF10_TIM4 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF11_TIM19 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF14_USB : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF15_EVENTOUT : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF1_EVENTOUT : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF1_TIM15 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF1_TIM16 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF1_TIM17 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF1_TIM2 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF2_TIM13 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF2_TIM14 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF2_TIM15 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF2_TIM19 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF2_TIM3 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF2_TIM4 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF2_TIM5 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF3_TSC : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF4_I2C1 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF4_I2C2 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF5_IR : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF6_CEC : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF6_IR : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF6_SPI1 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF6_SPI3 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF7_CAN : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF7_CEC : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF7_USART1 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF7_USART2 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF7_USART3 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF8_COMP1 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF8_COMP2 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF9_CAN : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF9_TIM12 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF9_TIM13 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF9_TIM14 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF9_TIM15 : stm32f3xx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32f3xx_hal_gpio_ex.h
  • GPIO_MODE : stm32f3xx_hal_gpio.c
  • GPIO_MODE_AF_OD : stm32f3xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32f3xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32f3xx_hal_gpio.h
  • GPIO_MODE_EVT : stm32f3xx_hal_gpio.c
  • GPIO_MODE_EVT_FALLING : stm32f3xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32f3xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32f3xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32f3xx_hal_gpio.h
  • GPIO_MODE_IT : stm32f3xx_hal_gpio.c
  • GPIO_MODE_IT_FALLING : stm32f3xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32f3xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32f3xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32f3xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32f3xx_hal_gpio.h
  • GPIO_NOPULL : stm32f3xx_hal_gpio.h
  • GPIO_NUMBER : stm32f3xx_hal_gpio.c
  • GPIO_OUTPUT_TYPE : stm32f3xx_hal_gpio.c
  • GPIO_PIN_0 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_1 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_10 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_11 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_12 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_13 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_14 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_15 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_2 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_3 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_4 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_5 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_6 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_7 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_8 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_9 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_All : stm32f3xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32f3xx_hal_gpio.h
  • GPIO_PIN_RESET : stm32f3xx_hal_gpio.h
  • GPIO_PIN_SET : stm32f3xx_hal_gpio.h
  • GPIO_PinState : stm32f3xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32f3xx_hal_gpio.h
  • GPIO_PULLUP : stm32f3xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32f3xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32f3xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32f3xx_hal_gpio.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- h -

  • HAL_ADC_AnalogWDGConfig() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_ConfigChannel() : stm32f3xx_hal_adc_ex.c , stm32f3xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32f3xx_hal_adc.c
  • HAL_ADC_ConvHalfCpltCallback() : stm32f3xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32f3xx_hal_adc_ex.c , stm32f3xx_hal_adc.c
  • HAL_ADC_ERROR_DMA : stm32f3xx_hal_adc_ex.h
  • HAL_ADC_ERROR_INTERNAL : stm32f3xx_hal_adc_ex.h
  • HAL_ADC_ERROR_JQOVF : stm32f3xx_hal_adc_ex.h
  • HAL_ADC_ERROR_NONE : stm32f3xx_hal_adc_ex.h
  • HAL_ADC_ERROR_OVR : stm32f3xx_hal_adc_ex.h
  • HAL_ADC_ErrorCallback() : stm32f3xx_hal_adc.c
  • HAL_ADC_GetError() : stm32f3xx_hal_adc.c
  • HAL_ADC_GetState() : stm32f3xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_Init() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_IRQHandler() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_LevelOutOfWindowCallback() : stm32f3xx_hal_adc.c
  • HAL_ADC_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_ADC_MspDeInit() : stm32f3xx_hal_adc.c
  • HAL_ADC_MspInit() : stm32f3xx_hal_adc.c
  • HAL_ADC_PollForConversion() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_PollForEvent() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_Start() : stm32f3xx_hal_adc_ex.c , stm32f3xx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_Start_IT() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_STATE_AWD1 : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_INJ_JQOVF : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOSMP : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32f3xx_hal_adc.h
  • HAL_ADC_Stop() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_Stop_DMA() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_Stop_IT() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_Start() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop() : stm32f3xx_hal_adc_ex.h
  • HAL_ADCEx_RegularStop_DMA() : stm32f3xx_hal_adc_ex.h
  • HAL_ADCEx_RegularStop_IT() : stm32f3xx_hal_adc_ex.h
  • HAL_CAN_ConfigFilter() : stm32f3xx_hal_can.c
  • HAL_CAN_DeInit() : stm32f3xx_hal_can.c
  • HAL_CAN_ERROR_ACK : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_BD : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_BOF : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_BR : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_CRC : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_EPV : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_EWG : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_FOR : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_FOV0 : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_FOV1 : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_NONE : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_STF : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_TXFAIL : stm32f3xx_hal_can.h
  • HAL_CAN_ErrorCallback() : stm32f3xx_hal_can.c
  • HAL_CAN_GetError() : stm32f3xx_hal_can.c
  • HAL_CAN_GetState() : stm32f3xx_hal_can.c
  • HAL_CAN_Init() : stm32f3xx_hal_can.c
  • HAL_CAN_IRQHandler() : stm32f3xx_hal_can.c
  • HAL_CAN_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_CAN_MspDeInit() : stm32f3xx_hal_can.c
  • HAL_CAN_MspInit() : stm32f3xx_hal_can.c
  • HAL_CAN_Receive() : stm32f3xx_hal_can.c
  • HAL_CAN_Receive_IT() : stm32f3xx_hal_can.c
  • HAL_CAN_RxCpltCallback() : stm32f3xx_hal_can.c
  • HAL_CAN_Sleep() : stm32f3xx_hal_can.c
  • HAL_CAN_STATE_BUSY : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_BUSY_RX0 : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_BUSY_RX0_RX1 : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_BUSY_RX1 : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX_RX0 : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX_RX0_RX1 : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX_RX1 : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_ERROR : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_READY : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_RESET : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_TIMEOUT : stm32f3xx_hal_can.h
  • HAL_CAN_StateTypeDef : stm32f3xx_hal_can.h
  • HAL_CAN_Transmit() : stm32f3xx_hal_can.c
  • HAL_CAN_Transmit_IT() : stm32f3xx_hal_can.c
  • HAL_CAN_TxCpltCallback() : stm32f3xx_hal_can.c
  • HAL_CAN_WakeUp() : stm32f3xx_hal_can.c
  • HAL_CEC_ChangeRxBuffer() : stm32f3xx_hal_cec.c
  • HAL_CEC_DeInit() : stm32f3xx_hal_cec.c
  • HAL_CEC_ERROR_ARBLST : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_BRE : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_LBPE : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_NONE : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_RXACKE : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_RXOVR : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_SBPE : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_TXACKE : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_TXERR : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_TXUDR : stm32f3xx_hal_cec.h
  • HAL_CEC_ErrorCallback() : stm32f3xx_hal_cec.c
  • HAL_CEC_GetError() : stm32f3xx_hal_cec.c
  • HAL_CEC_GetLastReceivedFrameSize() : stm32f3xx_hal_cec.c
  • HAL_CEC_GetState() : stm32f3xx_hal_cec.c
  • HAL_CEC_Init() : stm32f3xx_hal_cec.c
  • HAL_CEC_IRQHandler() : stm32f3xx_hal_cec.c
  • HAL_CEC_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_CEC_MspDeInit() : stm32f3xx_hal_cec.c
  • HAL_CEC_MspInit() : stm32f3xx_hal_cec.c
  • HAL_CEC_RxCpltCallback() : stm32f3xx_hal_cec.c
  • HAL_CEC_SetDeviceAddress() : stm32f3xx_hal_cec.c
  • HAL_CEC_STATE_BUSY : stm32f3xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX : stm32f3xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX_TX : stm32f3xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_TX : stm32f3xx_hal_cec.h
  • HAL_CEC_STATE_ERROR : stm32f3xx_hal_cec.h
  • HAL_CEC_STATE_READY : stm32f3xx_hal_cec.h
  • HAL_CEC_STATE_RESET : stm32f3xx_hal_cec.h
  • HAL_CEC_StateTypeDef : stm32f3xx_hal_cec.h
  • HAL_CEC_Transmit_IT() : stm32f3xx_hal_cec.c
  • HAL_CEC_TxCpltCallback() : stm32f3xx_hal_cec.c
  • HAL_COMP_DeInit() : stm32f3xx_hal_comp.c
  • HAL_COMP_GetOutputLevel() : stm32f3xx_hal_comp.c
  • HAL_COMP_GetState() : stm32f3xx_hal_comp.c
  • HAL_COMP_Init() : stm32f3xx_hal_comp.c
  • HAL_COMP_IRQHandler() : stm32f3xx_hal_comp.c
  • HAL_COMP_Lock() : stm32f3xx_hal_comp.c
  • HAL_COMP_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_COMP_MspDeInit() : stm32f3xx_hal_comp.c
  • HAL_COMP_MspInit() : stm32f3xx_hal_comp.c
  • HAL_COMP_Start() : stm32f3xx_hal_comp.c
  • HAL_COMP_Start_IT() : stm32f3xx_hal_comp.c
  • HAL_COMP_STATE_BUSY : stm32f3xx_hal_comp.h
  • HAL_COMP_STATE_BUSY_LOCKED : stm32f3xx_hal_comp.h
  • HAL_COMP_STATE_READY : stm32f3xx_hal_comp.h
  • HAL_COMP_STATE_READY_LOCKED : stm32f3xx_hal_comp.h
  • HAL_COMP_STATE_RESET : stm32f3xx_hal_comp.h
  • HAL_COMP_StateTypeDef : stm32f3xx_hal_comp.h
  • HAL_COMP_Stop() : stm32f3xx_hal_comp.c
  • HAL_COMP_Stop_IT() : stm32f3xx_hal_comp.c
  • HAL_COMP_TriggerCallback() : stm32f3xx_hal_comp.c
  • HAL_CORTEX_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_CRC_Accumulate() : stm32f3xx_hal_crc.c
  • HAL_CRC_Calculate() : stm32f3xx_hal_crc.c
  • HAL_CRC_DeInit() : stm32f3xx_hal_crc.c
  • HAL_CRC_GetState() : stm32f3xx_hal_crc.c
  • HAL_CRC_Init() : stm32f3xx_hal_crc.c
  • HAL_CRC_Input_Data_Reverse : stm32f3xx_hal_crc.h
  • HAL_CRC_LENGTH_16B : stm32f3xx_hal_crc.h
  • HAL_CRC_LENGTH_32B : stm32f3xx_hal_crc.h
  • HAL_CRC_LENGTH_7B : stm32f3xx_hal_crc.h
  • HAL_CRC_LENGTH_8B : stm32f3xx_hal_crc.h
  • HAL_CRC_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_CRC_MspDeInit() : stm32f3xx_hal_crc.c
  • HAL_CRC_MspInit() : stm32f3xx_hal_crc.c
  • HAL_CRC_Output_Data_Reverse : stm32f3xx_hal_crc.h
  • HAL_CRC_STATE_BUSY : stm32f3xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32f3xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32f3xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32f3xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32f3xx_hal_crc.h
  • HAL_CRC_StateTypeDef : stm32f3xx_hal_crc.h
  • HAL_CRCEx_Input_Data_Reverse() : stm32f3xx_hal_crc_ex.c
  • HAL_CRCEx_Output_Data_Reverse() : stm32f3xx_hal_crc_ex.c
  • HAL_CRCEx_Polynomial_Set() : stm32f3xx_hal_crc_ex.c
  • HAL_DAC_ConfigChannel() : stm32f3xx_hal_dac.c , stm32f3xx_hal_dac.h , stm32f3xx_hal_dac_ex.c
  • HAL_DAC_ConvCpltCallbackCh1() : stm32f3xx_hal_dac.c
  • HAL_DAC_ConvHalfCpltCallbackCh1() : stm32f3xx_hal_dac.c
  • HAL_DAC_DeInit() : stm32f3xx_hal_dac.c
  • HAL_DAC_DMAUnderrunCallbackCh1() : stm32f3xx_hal_dac.c
  • HAL_DAC_ERROR_DMA : stm32f3xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH1 : stm32f3xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH2 : stm32f3xx_hal_dac.h
  • HAL_DAC_ERROR_NONE : stm32f3xx_hal_dac.h
  • HAL_DAC_ErrorCallbackCh1() : stm32f3xx_hal_dac.c
  • HAL_DAC_GetError() : stm32f3xx_hal_dac.c
  • HAL_DAC_GetState() : stm32f3xx_hal_dac.c
  • HAL_DAC_GetValue() : stm32f3xx_hal_dac.c , stm32f3xx_hal_dac_ex.c
  • HAL_DAC_Init() : stm32f3xx_hal_dac.c
  • HAL_DAC_IRQHandler() : stm32f3xx_hal_dac.h , stm32f3xx_hal_dac_ex.c
  • HAL_DAC_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_DAC_MspDeInit() : stm32f3xx_hal_dac.c
  • HAL_DAC_MspInit() : stm32f3xx_hal_dac.c
  • HAL_DAC_SetValue() : stm32f3xx_hal_dac.c , stm32f3xx_hal_dac_ex.c
  • HAL_DAC_Start() : stm32f3xx_hal_dac.c , stm32f3xx_hal_dac_ex.c
  • HAL_DAC_Start_DMA() : stm32f3xx_hal_dac.h , stm32f3xx_hal_dac_ex.c
  • HAL_DAC_STATE_BUSY : stm32f3xx_hal_dac.h
  • HAL_DAC_STATE_ERROR : stm32f3xx_hal_dac.h
  • HAL_DAC_STATE_READY : stm32f3xx_hal_dac.h
  • HAL_DAC_STATE_RESET : stm32f3xx_hal_dac.h
  • HAL_DAC_STATE_TIMEOUT : stm32f3xx_hal_dac.h
  • HAL_DAC_StateTypeDef : stm32f3xx_hal_dac.h
  • HAL_DAC_Stop() : stm32f3xx_hal_dac.c
  • HAL_DAC_Stop_DMA() : stm32f3xx_hal_dac.c
  • HAL_DACEx_ConvCpltCallbackCh2() : stm32f3xx_hal_dac_ex.c
  • HAL_DACEx_ConvHalfCpltCallbackCh2() : stm32f3xx_hal_dac_ex.c
  • HAL_DACEx_DMAUnderrunCallbackCh2() : stm32f3xx_hal_dac_ex.c
  • HAL_DACEx_DualGetValue() : stm32f3xx_hal_dac.c , stm32f3xx_hal_dac_ex.c
  • HAL_DACEx_DualSetValue() : stm32f3xx_hal_dac.c , stm32f3xx_hal_dac_ex.c , stm32f3xx_hal_dac_ex.h
  • HAL_DACEx_ErrorCallbackCh2() : stm32f3xx_hal_dac_ex.c
  • HAL_DACEx_NoiseWaveGenerate() : stm32f3xx_hal_dac_ex.c
  • HAL_DACEx_TriangleWaveGenerate() : stm32f3xx_hal_dac_ex.c
  • HAL_DBGMCU_DisableDBGSleepMode() : stm32f3xx_hal.c
  • HAL_DBGMCU_DisableDBGStandbyMode() : stm32f3xx_hal.c
  • HAL_DBGMCU_DisableDBGStopMode() : stm32f3xx_hal.c
  • HAL_DBGMCU_EnableDBGSleepMode() : stm32f3xx_hal.c
  • HAL_DBGMCU_EnableDBGStandbyMode() : stm32f3xx_hal.c
  • HAL_DBGMCU_EnableDBGStopMode() : stm32f3xx_hal.c
  • HAL_DeInit() : stm32f3xx_hal.c
  • HAL_Delay() : stm32f3xx_hal.c
  • HAL_DMA_Abort() : stm32f3xx_hal_dma.c
  • HAL_DMA_Abort_IT() : stm32f3xx_hal_dma.c
  • HAL_DMA_CallbackIDTypeDef : stm32f3xx_hal_dma.h
  • HAL_DMA_DeInit() : stm32f3xx_hal_dma.c
  • HAL_DMA_ERROR_NO_XFER : stm32f3xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32f3xx_hal_dma.h
  • HAL_DMA_ERROR_NOT_SUPPORTED : stm32f3xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32f3xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32f3xx_hal_dma.h
  • HAL_DMA_FULL_TRANSFER : stm32f3xx_hal_dma.h
  • HAL_DMA_GetError() : stm32f3xx_hal_dma.c
  • HAL_DMA_GetState() : stm32f3xx_hal_dma.c
  • HAL_DMA_HALF_TRANSFER : stm32f3xx_hal_dma.h
  • HAL_DMA_Init() : stm32f3xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32f3xx_hal_dma.c
  • HAL_DMA_LevelCompleteTypeDef : stm32f3xx_hal_dma.h
  • HAL_DMA_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_DMA_PollForTransfer() : stm32f3xx_hal_dma.c
  • HAL_DMA_RegisterCallback() : stm32f3xx_hal_dma.c
  • HAL_DMA_Start() : stm32f3xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32f3xx_hal_dma.c
  • HAL_DMA_STATE_BUSY : stm32f3xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32f3xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32f3xx_hal_dma.h
  • HAL_DMA_STATE_TIMEOUT : stm32f3xx_hal_dma.h
  • HAL_DMA_StateTypeDef : stm32f3xx_hal_dma.h
  • HAL_DMA_UnRegisterCallback() : stm32f3xx_hal_dma.c
  • HAL_DMA_XFER_ABORT_CB_ID : stm32f3xx_hal_dma.h
  • HAL_DMA_XFER_ALL_CB_ID : stm32f3xx_hal_dma.h
  • HAL_DMA_XFER_CPLT_CB_ID : stm32f3xx_hal_dma.h
  • HAL_DMA_XFER_ERROR_CB_ID : stm32f3xx_hal_dma.h
  • HAL_DMA_XFER_HALFCPLT_CB_ID : stm32f3xx_hal_dma.h
  • HAL_FLASH_EndOfOperationCallback() : stm32f3xx_hal_flash.c
  • HAL_FLASH_ERROR_NONE : stm32f3xx_hal_flash.h
  • HAL_FLASH_ERROR_PROG : stm32f3xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32f3xx_hal_flash.h
  • HAL_FLASH_GetError() : stm32f3xx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32f3xx_hal_flash.c
  • HAL_FLASH_Lock() : stm32f3xx_hal_flash.c
  • HAL_FLASH_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_FLASH_OB_Launch() : stm32f3xx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32f3xx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32f3xx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32f3xx_hal_flash.c
  • HAL_FLASH_Program() : stm32f3xx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32f3xx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32f3xx_hal_flash.c
  • HAL_FLASHEx_Erase() : stm32f3xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32f3xx_hal_flash_ex.c
  • HAL_FLASHEx_OBErase() : stm32f3xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32f3xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetUserData() : stm32f3xx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32f3xx_hal_flash_ex.c
  • HAL_GetDEVID() : stm32f3xx_hal.c
  • HAL_GetHalVersion() : stm32f3xx_hal.c
  • HAL_GetREVID() : stm32f3xx_hal.c
  • HAL_GetTick() : stm32f3xx_hal.c
  • HAL_GetUIDw0() : stm32f3xx_hal.c
  • HAL_GetUIDw1() : stm32f3xx_hal.c
  • HAL_GetUIDw2() : stm32f3xx_hal.c
  • HAL_GPIO_DeInit() : stm32f3xx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32f3xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32f3xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32f3xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32f3xx_hal_gpio.c
  • HAL_GPIO_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_GPIO_ReadPin() : stm32f3xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32f3xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32f3xx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32f3xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32f3xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32f3xx_hal_uart.c
  • HAL_HRTIM_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_I2C_AbortCpltCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_AddrCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_DeInit() : stm32f3xx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32f3xx_hal_i2c.c
  • HAL_I2C_ERROR_AF : stm32f3xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32f3xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32f3xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32f3xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32f3xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32f3xx_hal_i2c.h
  • HAL_I2C_ERROR_SIZE : stm32f3xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32f3xx_hal_i2c.h
  • HAL_I2C_ErrorCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32f3xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32f3xx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32f3xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Init() : stm32f3xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32f3xx_hal_i2c.c
  • HAL_I2C_ListenCpltCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Receive_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Transmit_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_MasterRxCpltCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Mem_Write() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_MODE_MASTER : stm32f3xx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32f3xx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32f3xx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32f3xx_hal_i2c.h
  • HAL_I2C_ModeTypeDef : stm32f3xx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_I2C_MspDeInit() : stm32f3xx_hal_i2c.c
  • HAL_I2C_MspInit() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Receive_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Transmit_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_SlaveRxCpltCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_STATE_ABORT : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32f3xx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32f3xx_hal_i2c.h
  • HAL_I2CEx_ConfigAnalogFilter() : stm32f3xx_hal_i2c_ex.c
  • HAL_I2CEx_ConfigDigitalFilter() : stm32f3xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableFastModePlus() : stm32f3xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableWakeUp() : stm32f3xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableFastModePlus() : stm32f3xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableWakeUp() : stm32f3xx_hal_i2c_ex.c
  • HAL_I2S_DeInit() : stm32f3xx_hal_i2s.c
  • HAL_I2S_DMAPause() : stm32f3xx_hal_i2s.c , stm32f3xx_hal_i2s_ex.c
  • HAL_I2S_DMAResume() : stm32f3xx_hal_i2s.c , stm32f3xx_hal_i2s_ex.c
  • HAL_I2S_DMAStop() : stm32f3xx_hal_i2s.c , stm32f3xx_hal_i2s_ex.c
  • HAL_I2S_ERROR_DMA : stm32f3xx_hal_i2s.h
  • HAL_I2S_ERROR_NONE : stm32f3xx_hal_i2s.h
  • HAL_I2S_ERROR_OVR : stm32f3xx_hal_i2s.h
  • HAL_I2S_ERROR_TIMEOUT : stm32f3xx_hal_i2s.h
  • HAL_I2S_ERROR_UDR : stm32f3xx_hal_i2s.h
  • HAL_I2S_ERROR_UNKNOW : stm32f3xx_hal_i2s.h
  • HAL_I2S_ErrorCallback() : stm32f3xx_hal_i2s.c
  • HAL_I2S_GetError() : stm32f3xx_hal_i2s.c
  • HAL_I2S_GetState() : stm32f3xx_hal_i2s.c
  • HAL_I2S_Init() : stm32f3xx_hal_i2s.c
  • HAL_I2S_IRQHandler() : stm32f3xx_hal_i2s.c
  • HAL_I2S_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_I2S_MspDeInit() : stm32f3xx_hal_i2s.c
  • HAL_I2S_MspInit() : stm32f3xx_hal_i2s.c
  • HAL_I2S_Receive() : stm32f3xx_hal_i2s.c
  • HAL_I2S_Receive_DMA() : stm32f3xx_hal_i2s.c
  • HAL_I2S_Receive_IT() : stm32f3xx_hal_i2s.c
  • HAL_I2S_RxCpltCallback() : stm32f3xx_hal_i2s.c
  • HAL_I2S_RxHalfCpltCallback() : stm32f3xx_hal_i2s.c
  • HAL_I2S_STATE_BUSY : stm32f3xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_RX : stm32f3xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX : stm32f3xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX_RX : stm32f3xx_hal_i2s.h
  • HAL_I2S_STATE_ERROR : stm32f3xx_hal_i2s.h
  • HAL_I2S_STATE_READY : stm32f3xx_hal_i2s.h
  • HAL_I2S_STATE_RESET : stm32f3xx_hal_i2s.h
  • HAL_I2S_STATE_TIMEOUT : stm32f3xx_hal_i2s.h
  • HAL_I2S_StateTypeDef : stm32f3xx_hal_i2s.h
  • HAL_I2S_Transmit() : stm32f3xx_hal_i2s.c
  • HAL_I2S_Transmit_DMA() : stm32f3xx_hal_i2s.c
  • HAL_I2S_Transmit_IT() : stm32f3xx_hal_i2s.c
  • HAL_I2S_TxCpltCallback() : stm32f3xx_hal_i2s.c
  • HAL_I2S_TxHalfCpltCallback() : stm32f3xx_hal_i2s.c
  • HAL_IncTick() : stm32f3xx_hal.c
  • HAL_Init() : stm32f3xx_hal.c
  • HAL_InitTick() : stm32f3xx_hal.c
  • HAL_IRDA_Abort() : stm32f3xx_hal_irda.c
  • HAL_IRDA_Abort_IT() : stm32f3xx_hal_irda.c
  • HAL_IRDA_AbortCpltCallback() : stm32f3xx_hal_irda.c
  • HAL_IRDA_AbortReceive() : stm32f3xx_hal_irda.c
  • HAL_IRDA_AbortReceive_IT() : stm32f3xx_hal_irda.c
  • HAL_IRDA_AbortReceiveCpltCallback() : stm32f3xx_hal_irda.c
  • HAL_IRDA_AbortTransmit() : stm32f3xx_hal_irda.c
  • HAL_IRDA_AbortTransmit_IT() : stm32f3xx_hal_irda.c
  • HAL_IRDA_AbortTransmitCpltCallback() : stm32f3xx_hal_irda.c
  • HAL_IRDA_DeInit() : stm32f3xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32f3xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32f3xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32f3xx_hal_irda.c
  • HAL_IRDA_ERROR_BUSY : stm32f3xx_hal_irda.h
  • HAL_IRDA_ERROR_DMA : stm32f3xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32f3xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32f3xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32f3xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32f3xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32f3xx_hal_irda.h
  • HAL_IRDA_ErrorCallback() : stm32f3xx_hal_irda.c
  • HAL_IRDA_GetError() : stm32f3xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32f3xx_hal_irda.c
  • HAL_IRDA_Init() : stm32f3xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32f3xx_hal_irda.c
  • HAL_IRDA_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_IRDA_MspDeInit() : stm32f3xx_hal_irda.c
  • HAL_IRDA_MspInit() : stm32f3xx_hal_irda.c
  • HAL_IRDA_Receive() : stm32f3xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32f3xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32f3xx_hal_irda.c
  • HAL_IRDA_RxCpltCallback() : stm32f3xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32f3xx_hal_irda.c
  • HAL_IRDA_STATE_BUSY : stm32f3xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32f3xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32f3xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32f3xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32f3xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32f3xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32f3xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32f3xx_hal_irda.h
  • HAL_IRDA_StateTypeDef : stm32f3xx_hal_irda.h
  • HAL_IRDA_Transmit() : stm32f3xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32f3xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32f3xx_hal_irda.c
  • HAL_IRDA_TxCpltCallback() : stm32f3xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32f3xx_hal_irda.c
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32f3xx_hal_iwdg.c
  • HAL_IWDG_Init() : stm32f3xx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_IWDG_Refresh() : stm32f3xx_hal_iwdg.c
  • HAL_LIN_Init() : stm32f3xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32f3xx_hal_uart.c
  • HAL_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_MPU_ConfigRegion() : stm32f3xx_hal_cortex.c
  • HAL_MPU_Disable() : stm32f3xx_hal_cortex.c , stm32f3xx_hal_cortex.h
  • HAL_MPU_Enable() : stm32f3xx_hal_cortex.c , stm32f3xx_hal_cortex.h
  • HAL_MspDeInit() : stm32f3xx_hal.c
  • HAL_MspInit() : stm32f3xx_hal.c
  • HAL_MultiProcessor_DisableMuteMode() : stm32f3xx_hal_uart.c
  • HAL_MultiProcessor_EnableMuteMode() : stm32f3xx_hal_uart.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32f3xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32f3xx_hal_uart.c
  • HAL_MultiProcessorEx_AddressLength_Set() : stm32f3xx_hal_uart_ex.c
  • HAL_NAND_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_NOR_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_NVIC_ClearPendingIRQ() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_GetActive() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32f3xx_hal_cortex.c
  • HAL_OPAMP_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_OPAMPEx_SelfCalibrateAll() : stm32f3xx_hal_opamp_ex.c
  • HAL_PCCARD_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_PCD_ActivateRemoteWakeup() : stm32f3xx_hal_pcd.c
  • HAL_PCD_ActiveRemoteWakeup() : stm32f3xx_hal_pcd.h
  • HAL_PCD_ConnectCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32f3xx_hal_pcd.c
  • HAL_PCD_DeActiveRemoteWakeup() : stm32f3xx_hal_pcd.h
  • HAL_PCD_DeInit() : stm32f3xx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32f3xx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32f3xx_hal_pcd.c
  • HAL_PCD_DisconnectCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32f3xx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32f3xx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32f3xx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32f3xx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32f3xx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32f3xx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32f3xx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32f3xx_hal_pcd.c
  • HAL_PCD_GetState() : stm32f3xx_hal_pcd.c
  • HAL_PCD_Init() : stm32f3xx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32f3xx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_PCD_MspDeInit() : stm32f3xx_hal_pcd.c
  • HAL_PCD_MspInit() : stm32f3xx_hal_pcd.c
  • HAL_PCD_ResetCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_ResumeCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32f3xx_hal_pcd.c
  • HAL_PCD_SetupStageCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_SOFCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_Start() : stm32f3xx_hal_pcd.c
  • HAL_PCD_STATE_BUSY : stm32f3xx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32f3xx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32f3xx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32f3xx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32f3xx_hal_pcd.h
  • HAL_PCD_Stop() : stm32f3xx_hal_pcd.c
  • HAL_PCD_SuspendCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCDEx_PMAConfig() : stm32f3xx_hal_pcd_ex.c
  • HAL_PCDEx_SetConnectionState() : stm32f3xx_hal_pcd_ex.c , stm32f3xx_hal_pcd_ex.h
  • HAL_PWR_ConfigPVD() : stm32f3xx_hal_pwr_ex.c
  • HAL_PWR_DeInit() : stm32f3xx_hal_pwr.c , stm32f3xx_hal_pwr.h
  • HAL_PWR_DisableBkUpAccess() : stm32f3xx_hal_pwr.c , stm32f3xx_hal_pwr.h
  • HAL_PWR_DisablePVD() : stm32f3xx_hal_pwr_ex.c
  • HAL_PWR_DisableSEVOnPend() : stm32f3xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32f3xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32f3xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32f3xx_hal_pwr.c , stm32f3xx_hal_pwr.h
  • HAL_PWR_EnablePVD() : stm32f3xx_hal_pwr_ex.c
  • HAL_PWR_EnableSEVOnPend() : stm32f3xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32f3xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32f3xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32f3xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32f3xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32f3xx_hal_pwr.c
  • HAL_PWR_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_PWR_PVD_IRQHandler() : stm32f3xx_hal_pwr_ex.c
  • HAL_PWR_PVDCallback() : stm32f3xx_hal_pwr_ex.c
  • HAL_PWREx_DisableSDADC() : stm32f3xx_hal_pwr_ex.c
  • HAL_PWREx_EnableSDADC() : stm32f3xx_hal_pwr_ex.c
  • HAL_RCC_ClockConfig() : stm32f3xx_hal_rcc.c
  • HAL_RCC_CSSCallback() : stm32f3xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32f3xx_hal_rcc.c
  • HAL_RCC_DisableCSS() : stm32f3xx_hal_rcc.c
  • HAL_RCC_EnableCSS() : stm32f3xx_hal_rcc.c
  • HAL_RCC_GetClockConfig() : stm32f3xx_hal_rcc.c
  • HAL_RCC_GetHCLKFreq() : stm32f3xx_hal_rcc.c
  • HAL_RCC_GetOscConfig() : stm32f3xx_hal_rcc.c
  • HAL_RCC_GetPCLK1Freq() : stm32f3xx_hal_rcc.c
  • HAL_RCC_GetPCLK2Freq() : stm32f3xx_hal_rcc.c
  • HAL_RCC_GetSysClockFreq() : stm32f3xx_hal_rcc.c
  • HAL_RCC_MCOConfig() : stm32f3xx_hal_rcc.c
  • HAL_RCC_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_RCC_NMI_IRQHandler() : stm32f3xx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32f3xx_hal_rcc.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32f3xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32f3xx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32f3xx_hal_rcc_ex.c
  • HAL_REMAPDMA_ADC24_DMA2_CH34 : stm32f3xx_hal.h
  • HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 : stm32f3xx_hal.h
  • HAL_REMAPDMA_TIM16_DMA1_CH6 : stm32f3xx_hal.h
  • HAL_REMAPDMA_TIM17_DMA1_CH7 : stm32f3xx_hal.h
  • HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 : stm32f3xx_hal.h
  • HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 : stm32f3xx_hal.h
  • HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 : stm32f3xx_hal.h
  • HAL_REMAPTRIGGER_DAC1_TRIG : stm32f3xx_hal.h
  • HAL_REMAPTRIGGER_TIM1_ITR3 : stm32f3xx_hal.h
  • HAL_ResumeTick() : stm32f3xx_hal.c
  • HAL_RS485Ex_Init() : stm32f3xx_hal_uart_ex.c
  • HAL_RTC_AlarmAEventCallback() : stm32f3xx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32f3xx_hal_rtc.c
  • HAL_RTC_DeactivateAlarm() : stm32f3xx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32f3xx_hal_rtc.c
  • HAL_RTC_GetAlarm() : stm32f3xx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32f3xx_hal_rtc.c
  • HAL_RTC_GetState() : stm32f3xx_hal_rtc.c , stm32f3xx_hal_rtc.h
  • HAL_RTC_GetTime() : stm32f3xx_hal_rtc.c
  • HAL_RTC_Init() : stm32f3xx_hal_rtc.c
  • HAL_RTC_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_RTC_MspDeInit() : stm32f3xx_hal_rtc.c
  • HAL_RTC_MspInit() : stm32f3xx_hal_rtc.c
  • HAL_RTC_PollForAlarmAEvent() : stm32f3xx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32f3xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32f3xx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32f3xx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32f3xx_hal_rtc.c
  • HAL_RTC_STATE_BUSY : stm32f3xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32f3xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32f3xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32f3xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32f3xx_hal_rtc.h
  • HAL_RTC_WaitForSynchro() : stm32f3xx_hal_rtc.c , stm32f3xx_hal_rtc.h
  • HAL_RTCEx_AlarmBEventCallback() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPRead() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateRefClock() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTimeStamp() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_DisableBypassShadow() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_EnableBypassShadow() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_GetTimeStamp() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_GetWakeUpTimer() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForAlarmBEvent() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper1Event() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper2Event() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper3Event() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTimeStampEvent() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetCalibrationOutPut() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetRefClock() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSynchroShift() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp_IT() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper2EventCallback() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper3EventCallback() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_TamperTimeStampIRQHandler() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampEventCallback() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCStateTypeDef : stm32f3xx_hal_rtc.h
  • HAL_SDADC_AssociateChannelConfig() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_CalibrationCpltCallback() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_CalibrationStart() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_CalibrationStart_IT() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_ConfigChannel() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_ConvCpltCallback() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_ConvHalfCpltCallback() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_DeInit() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_ErrorCallback() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_GetError() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_GetState() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_GetValue() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_Init() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedConfigChannel() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedConvCpltCallback() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedConvHalfCpltCallback() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedGetValue() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedMultiModeConfigChannel() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedMultiModeGetValue() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedMultiModeStart_DMA() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedMultiModeStop_DMA() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedStart() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedStart_DMA() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedStart_IT() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedStop() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedStop_DMA() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedStop_IT() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_IRQHandler() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_SDADC_MspDeInit() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_MspInit() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_MultiModeConfigChannel() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_MultiModeGetValue() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_MultiModeStart_DMA() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_MultiModeStop_DMA() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_PollForCalibEvent() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_PollForConversion() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_PollForInjectedConversion() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_PrepareChannelConfig() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_SelectInjectedDelay() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_SelectInjectedExtTrigger() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_SelectInjectedTrigger() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_SelectRegularTrigger() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_Start() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_Start_DMA() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_Start_IT() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_STATE_CALIB : stm32f3xx_hal_sdadc.h
  • HAL_SDADC_STATE_ERROR : stm32f3xx_hal_sdadc.h
  • HAL_SDADC_STATE_INJ : stm32f3xx_hal_sdadc.h
  • HAL_SDADC_STATE_READY : stm32f3xx_hal_sdadc.h
  • HAL_SDADC_STATE_REG : stm32f3xx_hal_sdadc.h
  • HAL_SDADC_STATE_REG_INJ : stm32f3xx_hal_sdadc.h
  • HAL_SDADC_STATE_RESET : stm32f3xx_hal_sdadc.h
  • HAL_SDADC_StateTypeDef : stm32f3xx_hal_sdadc.h
  • HAL_SDADC_Stop() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_Stop_DMA() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_Stop_IT() : stm32f3xx_hal_sdadc.c
  • HAL_SMARTCARD_Abort() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_Abort_IT() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortCpltCallback() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive_IT() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceiveCpltCallback() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit_IT() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmitCpltCallback() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_DeInit() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_ERROR_DMA : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_RTO : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_ErrorCallback() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_SMARTCARD_MspDeInit() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_MspInit() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_RxCpltCallback() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_STATE_BUSY : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_StateTypeDef : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_Transmit() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_TxCpltCallback() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARDEx_BlockLength_Config() : stm32f3xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableReceiverTimeOut() : stm32f3xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableReceiverTimeOut() : stm32f3xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TimeOut_Config() : stm32f3xx_hal_smartcard_ex.c
  • HAL_SMBUS_AddrCallback() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_ConfigAnalogFilter() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_ConfigDigitalFilter() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_DeInit() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_DisableAlert_IT() : stm32f3xx_hal_smbus.c , stm32f3xx_hal_smbus.h
  • HAL_SMBUS_DisableListen_IT() : stm32f3xx_hal_smbus.h , stm32f3xx_hal_smbus.c
  • HAL_SMBUS_EnableAlert_IT() : stm32f3xx_hal_smbus.h , stm32f3xx_hal_smbus.c
  • HAL_SMBUS_EnableListen_IT() : stm32f3xx_hal_smbus.h , stm32f3xx_hal_smbus.c
  • HAL_SMBUS_ER_IRQHandler() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_ERROR_ACKF : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ALERT : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ARLO : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BERR : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BUSTIMEOUT : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ERROR_HALTIMEOUT : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ERROR_NONE : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ERROR_OVR : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ERROR_PECERR : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ErrorCallback() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_EV_IRQHandler() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_GetError() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_GetState() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_Init() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_IsDeviceReady() : stm32f3xx_hal_smbus.c , stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ListenCpltCallback() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_Master_Abort_IT() : stm32f3xx_hal_smbus.h , stm32f3xx_hal_smbus.c
  • HAL_SMBUS_Master_Receive_IT() : stm32f3xx_hal_smbus.c , stm32f3xx_hal_smbus.h
  • HAL_SMBUS_Master_Transmit_IT() : stm32f3xx_hal_smbus.h , stm32f3xx_hal_smbus.c
  • HAL_SMBUS_MasterRxCpltCallback() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_MasterTxCpltCallback() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_SMBUS_MspDeInit() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_MspInit() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_Slave_Receive_IT() : stm32f3xx_hal_smbus.h , stm32f3xx_hal_smbus.c
  • HAL_SMBUS_Slave_Transmit_IT() : stm32f3xx_hal_smbus.c , stm32f3xx_hal_smbus.h
  • HAL_SMBUS_SlaveRxCpltCallback() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_SlaveTxCpltCallback() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_STATE_BUSY : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_ERROR : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_LISTEN : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_RX : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_TX : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_READY : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_RESET : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_RX : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_TX : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_TIMEOUT : stm32f3xx_hal_smbus.h
  • HAL_SPI_Abort() : stm32f3xx_hal_spi.c
  • HAL_SPI_Abort_IT() : stm32f3xx_hal_spi.c
  • HAL_SPI_AbortCpltCallback() : stm32f3xx_hal_spi.c
  • HAL_SPI_DeInit() : stm32f3xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32f3xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32f3xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32f3xx_hal_spi.c
  • HAL_SPI_ERROR_ABORT : stm32f3xx_hal_spi.h
  • HAL_SPI_ERROR_CRC : stm32f3xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32f3xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32f3xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32f3xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32f3xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32f3xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32f3xx_hal_spi.h
  • HAL_SPI_ErrorCallback() : stm32f3xx_hal_spi.c
  • HAL_SPI_GetError() : stm32f3xx_hal_spi.c
  • HAL_SPI_GetState() : stm32f3xx_hal_spi.c
  • HAL_SPI_Init() : stm32f3xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32f3xx_hal_spi.c
  • HAL_SPI_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_SPI_MspDeInit() : stm32f3xx_hal_spi.c
  • HAL_SPI_MspInit() : stm32f3xx_hal_spi.c
  • HAL_SPI_Receive() : stm32f3xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32f3xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32f3xx_hal_spi.c
  • HAL_SPI_RxCpltCallback() : stm32f3xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32f3xx_hal_spi.c
  • HAL_SPI_STATE_ABORT : stm32f3xx_hal_spi.h
  • HAL_SPI_STATE_BUSY : stm32f3xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32f3xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32f3xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32f3xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32f3xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32f3xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32f3xx_hal_spi.h
  • HAL_SPI_StateTypeDef : stm32f3xx_hal_spi.h
  • HAL_SPI_Transmit() : stm32f3xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32f3xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32f3xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32f3xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32f3xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32f3xx_hal_spi.c
  • HAL_SPI_TxCpltCallback() : stm32f3xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32f3xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32f3xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32f3xx_hal_spi.c
  • HAL_SPIEx_FlushRxFifo() : stm32f3xx_hal_spi_ex.c
  • HAL_SRAM_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_SuspendTick() : stm32f3xx_hal.c
  • HAL_SYSCFG_IT_FPU_DZC : stm32f3xx_hal.h
  • HAL_SYSCFG_IT_FPU_IDC : stm32f3xx_hal.h
  • HAL_SYSCFG_IT_FPU_IOC : stm32f3xx_hal.h
  • HAL_SYSCFG_IT_FPU_IXC : stm32f3xx_hal.h
  • HAL_SYSCFG_IT_FPU_OFC : stm32f3xx_hal.h
  • HAL_SYSCFG_IT_FPU_UFC : stm32f3xx_hal.h
  • HAL_SYSTICK_Callback() : stm32f3xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32f3xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32f3xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32f3xx_hal_cortex.c
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32f3xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32f3xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32f3xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32f3xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32f3xx_hal_tim.h
  • HAL_TIM_ActiveChannel : stm32f3xx_hal_tim.h
  • HAL_TIM_Base_DeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_MspInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_Start() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_ConfigClockSource() : stm32f3xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32f3xx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32f3xx_hal_tim.c
  • HAL_TIM_DMABurst_MultiReadStart() : stm32f3xx_hal_tim.c
  • HAL_TIM_DMABurst_MultiWriteStart() : stm32f3xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32f3xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32f3xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32f3xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_DeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_MspInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_Start() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_ErrorCallback() : stm32f3xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_CaptureCallback() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_MspInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_Start() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32f3xx_hal_tim.c
  • HAL_TIM_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_TIM_OC_ConfigChannel() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_DelayElapsedCallback() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_MspInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_Start() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_ConfigChannel() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_PeriodElapsedCallback() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_MspInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32f3xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization() : stm32f3xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_STATE_BUSY : stm32f3xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32f3xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32f3xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32f3xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32f3xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32f3xx_hal_tim.h
  • HAL_TIM_TriggerCallback() : stm32f3xx_hal_tim.c
  • HAL_TIMEOUT_ADDR : stm32f3xx_hal_smbus.c
  • HAL_TIMEOUT_BUSY : stm32f3xx_hal_smbus.c
  • HAL_TIMEOUT_DIR : stm32f3xx_hal_smbus.c
  • HAL_TIMEOUT_RXNE : stm32f3xx_hal_smbus.c
  • HAL_TIMEOUT_STOPF : stm32f3xx_hal_smbus.c
  • HAL_TIMEOUT_TC : stm32f3xx_hal_smbus.c
  • HAL_TIMEOUT_TCR : stm32f3xx_hal_smbus.c
  • HAL_TIMEOUT_TXIS : stm32f3xx_hal_smbus.c
  • HAL_TIMEx_Break2Callback() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_BreakCallback() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_CommutationCallback() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent() : stm32f3xx_hal_tim_ex.h
  • HAL_TIMEx_ConfigCommutationEvent_DMA() : stm32f3xx_hal_tim_ex.h
  • HAL_TIMEx_ConfigCommutationEvent_IT() : stm32f3xx_hal_tim_ex.h
  • HAL_TIMEx_HallSensor_DeInit() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32f3xx_hal_tim_ex.c
  • HAL_TSC_ConvCpltCallback() : stm32f3xx_hal_tsc.c
  • HAL_TSC_DeInit() : stm32f3xx_hal_tsc.c
  • HAL_TSC_ErrorCallback() : stm32f3xx_hal_tsc.c
  • HAL_TSC_GetState() : stm32f3xx_hal_tsc.c
  • HAL_TSC_GroupGetStatus() : stm32f3xx_hal_tsc.c
  • HAL_TSC_GroupGetValue() : stm32f3xx_hal_tsc.c
  • HAL_TSC_Init() : stm32f3xx_hal_tsc.c
  • HAL_TSC_IOConfig() : stm32f3xx_hal_tsc.c
  • HAL_TSC_IODischarge() : stm32f3xx_hal_tsc.c
  • HAL_TSC_IRQHandler() : stm32f3xx_hal_tsc.c
  • HAL_TSC_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_TSC_MspDeInit() : stm32f3xx_hal_tsc.c
  • HAL_TSC_MspInit() : stm32f3xx_hal_tsc.c
  • HAL_TSC_PollForAcquisition() : stm32f3xx_hal_tsc.c
  • HAL_TSC_Start() : stm32f3xx_hal_tsc.c
  • HAL_TSC_Start_IT() : stm32f3xx_hal_tsc.c
  • HAL_TSC_STATE_BUSY : stm32f3xx_hal_tsc.h
  • HAL_TSC_STATE_ERROR : stm32f3xx_hal_tsc.h
  • HAL_TSC_STATE_READY : stm32f3xx_hal_tsc.h
  • HAL_TSC_STATE_RESET : stm32f3xx_hal_tsc.h
  • HAL_TSC_StateTypeDef : stm32f3xx_hal_tsc.h
  • HAL_TSC_Stop() : stm32f3xx_hal_tsc.c
  • HAL_TSC_Stop_IT() : stm32f3xx_hal_tsc.c
  • HAL_UART_Abort() : stm32f3xx_hal_uart.c
  • HAL_UART_Abort_IT() : stm32f3xx_hal_uart.c
  • HAL_UART_AbortCpltCallback() : stm32f3xx_hal_uart.c
  • HAL_UART_AbortReceive() : stm32f3xx_hal_uart.c
  • HAL_UART_AbortReceive_IT() : stm32f3xx_hal_uart.c
  • HAL_UART_AbortReceiveCpltCallback() : stm32f3xx_hal_uart.c
  • HAL_UART_AbortTransmit() : stm32f3xx_hal_uart.c
  • HAL_UART_AbortTransmit_IT() : stm32f3xx_hal_uart.c
  • HAL_UART_AbortTransmitCpltCallback() : stm32f3xx_hal_uart.c
  • HAL_UART_DeInit() : stm32f3xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32f3xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32f3xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32f3xx_hal_uart.c
  • HAL_UART_ERROR_BUSY : stm32f3xx_hal_uart.h
  • HAL_UART_ERROR_DMA : stm32f3xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32f3xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32f3xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32f3xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32f3xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32f3xx_hal_uart.h
  • HAL_UART_ErrorCallback() : stm32f3xx_hal_uart.c
  • HAL_UART_GetError() : stm32f3xx_hal_uart.c
  • HAL_UART_GetState() : stm32f3xx_hal_uart.c
  • HAL_UART_Init() : stm32f3xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32f3xx_hal_uart.c
  • HAL_UART_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_UART_MspDeInit() : stm32f3xx_hal_uart.c
  • HAL_UART_MspInit() : stm32f3xx_hal_uart.c
  • HAL_UART_Receive() : stm32f3xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32f3xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32f3xx_hal_uart.c
  • HAL_UART_RxCpltCallback() : stm32f3xx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32f3xx_hal_uart.c
  • HAL_UART_STATE_BUSY : stm32f3xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32f3xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32f3xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32f3xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32f3xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32f3xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32f3xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32f3xx_hal_uart.h
  • HAL_UART_StateTypeDef : stm32f3xx_hal_uart.h
  • HAL_UART_TIMEOUT_VALUE : stm32f3xx_hal_uart.h
  • HAL_UART_Transmit() : stm32f3xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32f3xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32f3xx_hal_uart.c
  • HAL_UART_TxCpltCallback() : stm32f3xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32f3xx_hal_uart.c
  • HAL_UARTEx_DisableStopMode() : stm32f3xx_hal_uart_ex.c
  • HAL_UARTEx_EnableStopMode() : stm32f3xx_hal_uart_ex.c
  • HAL_UARTEx_StopModeWakeUpSourceConfig() : stm32f3xx_hal_uart_ex.c
  • HAL_UARTEx_WakeupCallback() : stm32f3xx_hal_uart_ex.c , stm32f3xx_hal_uart_ex.h
  • HAL_USART_Abort() : stm32f3xx_hal_usart.c
  • HAL_USART_Abort_IT() : stm32f3xx_hal_usart.c
  • HAL_USART_AbortCpltCallback() : stm32f3xx_hal_usart.c
  • HAL_USART_DeInit() : stm32f3xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32f3xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32f3xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32f3xx_hal_usart.c
  • HAL_USART_ERROR_DMA : stm32f3xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32f3xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32f3xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32f3xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32f3xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32f3xx_hal_usart.h
  • HAL_USART_ErrorCallback() : stm32f3xx_hal_usart.c
  • HAL_USART_GetError() : stm32f3xx_hal_usart.c
  • HAL_USART_GetState() : stm32f3xx_hal_usart.c
  • HAL_USART_Init() : stm32f3xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32f3xx_hal_usart.c
  • HAL_USART_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_USART_MspDeInit() : stm32f3xx_hal_usart.c
  • HAL_USART_MspInit() : stm32f3xx_hal_usart.c
  • HAL_USART_Receive() : stm32f3xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32f3xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32f3xx_hal_usart.c
  • HAL_USART_RxCpltCallback() : stm32f3xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32f3xx_hal_usart.c
  • HAL_USART_STATE_BUSY : stm32f3xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32f3xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32f3xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32f3xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32f3xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32f3xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32f3xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32f3xx_hal_usart.h
  • HAL_USART_StateTypeDef : stm32f3xx_hal_usart.h
  • HAL_USART_Transmit() : stm32f3xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32f3xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32f3xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32f3xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32f3xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32f3xx_hal_usart.c
  • HAL_USART_TxCpltCallback() : stm32f3xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32f3xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32f3xx_hal_usart.c
  • HAL_WWDG_EarlyWakeupCallback() : stm32f3xx_hal_wwdg.c
  • HAL_WWDG_Init() : stm32f3xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32f3xx_hal_wwdg.c
  • HAL_WWDG_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_WWDG_MspInit() : stm32f3xx_hal_wwdg.c
  • HAL_WWDG_Refresh() : stm32f3xx_hal_wwdg.c
  • HSE_STARTUP_TIMEOUT : stm32f3xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32f3xx_hal_rcc.h
  • HSE_VALUE : stm32f3xx_ll_rcc.h , stm32f3xx_hal_conf.h
  • HSI_STARTUP_TIMEOUT : stm32f3xx_hal_conf.h
  • HSI_TIMEOUT_VALUE : stm32f3xx_hal_rcc.h
  • HSI_VALUE : stm32f3xx_ll_rcc.h , stm32f3xx_hal_conf.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- i -

  • I2C_ADDRESSINGMODE_10BIT : stm32f3xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32f3xx_hal_i2c.h
  • I2C_ANALOGFILTER_DISABLE : stm32f3xx_hal_i2c_ex.h
  • I2C_ANALOGFILTER_ENABLE : stm32f3xx_hal_i2c_ex.h
  • I2C_AUTOEND_MODE : stm32f3xx_hal_i2c.h
  • I2C_DIRECTION_RECEIVE : stm32f3xx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32f3xx_hal_i2c.h
  • I2C_Disable_IRQ() : stm32f3xx_hal_i2c.c
  • I2C_DMAAbort() : stm32f3xx_hal_i2c.c
  • I2C_DMAError() : stm32f3xx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32f3xx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32f3xx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32f3xx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32f3xx_hal_i2c.c
  • I2C_DUALADDRESS_DISABLE : stm32f3xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32f3xx_hal_i2c.h
  • I2C_Enable_IRQ() : stm32f3xx_hal_i2c.c
  • I2C_FASTMODEPLUS_I2C1 : stm32f3xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C2 : stm32f3xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C3 : stm32f3xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB6 : stm32f3xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB7 : stm32f3xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB8 : stm32f3xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB9 : stm32f3xx_hal_i2c_ex.h
  • I2C_FIRST_AND_LAST_FRAME : stm32f3xx_hal_i2c.h
  • I2C_FIRST_AND_NEXT_FRAME : stm32f3xx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32f3xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32f3xx_hal_i2c.h
  • I2C_FLAG_AF : stm32f3xx_hal_i2c.h
  • I2C_FLAG_ALERT : stm32f3xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32f3xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32f3xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32f3xx_hal_i2c.h
  • I2C_FLAG_DIR : stm32f3xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32f3xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32f3xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32f3xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32f3xx_hal_i2c.h
  • I2C_FLAG_TC : stm32f3xx_hal_i2c.h
  • I2C_FLAG_TCR : stm32f3xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32f3xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32f3xx_hal_i2c.h
  • I2C_FLAG_TXIS : stm32f3xx_hal_i2c.h
  • I2C_Flush_TXDR() : stm32f3xx_hal_i2c.c
  • I2C_FMP_NOT_SUPPORTED : stm32f3xx_hal_i2c_ex.h
  • I2C_GENERALCALL_DISABLE : stm32f3xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32f3xx_hal_i2c.h
  • I2C_GENERATE_START : stm32f3xx_hal_i2c.h
  • I2C_GENERATE_START_READ : stm32f3xx_hal_i2c.h
  • I2C_GENERATE_START_WRITE : stm32f3xx_hal_i2c.h
  • I2C_GENERATE_STOP : stm32f3xx_hal_i2c.h
  • I2C_GET_ADDR_MATCH : stm32f3xx_hal_i2c.h
  • I2C_GET_DIR : stm32f3xx_hal_i2c.h
  • I2C_GET_DMA_REMAIN_DATA : stm32f3xx_hal_i2c.c
  • I2C_GET_OWN_ADDRESS1 : stm32f3xx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS2 : stm32f3xx_hal_i2c.h
  • I2C_GET_STOP_MODE : stm32f3xx_hal_i2c.h
  • I2C_HandleTypeDef : stm32f3xx_hal_i2c.h
  • I2C_IsAcknowledgeFailed() : stm32f3xx_hal_i2c.c
  • I2C_IT_ADDRI : stm32f3xx_hal_i2c.h
  • I2C_IT_ERRI : stm32f3xx_hal_i2c.h
  • I2C_IT_NACKI : stm32f3xx_hal_i2c.h
  • I2C_IT_RXI : stm32f3xx_hal_i2c.h
  • I2C_IT_STOPI : stm32f3xx_hal_i2c.h
  • I2C_IT_TCI : stm32f3xx_hal_i2c.h
  • I2C_IT_TXI : stm32f3xx_hal_i2c.h
  • I2C_ITAddrCplt() : stm32f3xx_hal_i2c.c
  • I2C_ITError() : stm32f3xx_hal_i2c.c
  • I2C_ITListenCplt() : stm32f3xx_hal_i2c.c
  • I2C_ITMasterCplt() : stm32f3xx_hal_i2c.c
  • I2C_ITMasterSequentialCplt() : stm32f3xx_hal_i2c.c
  • I2C_ITSlaveCplt() : stm32f3xx_hal_i2c.c
  • I2C_ITSlaveSequentialCplt() : stm32f3xx_hal_i2c.c
  • I2C_LAST_FRAME : stm32f3xx_hal_i2c.h
  • I2C_Master_ISR_DMA() : stm32f3xx_hal_i2c.c
  • I2C_Master_ISR_IT() : stm32f3xx_hal_i2c.c
  • I2C_MEM_ADD_LSB : stm32f3xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32f3xx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32f3xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32f3xx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32f3xx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32f3xx_hal_i2c.c
  • I2C_NO_STARTSTOP : stm32f3xx_hal_i2c.h
  • I2C_NOSTRETCH_DISABLE : stm32f3xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32f3xx_hal_i2c.h
  • I2C_OA2_MASK01 : stm32f3xx_hal_i2c.h
  • I2C_OA2_MASK02 : stm32f3xx_hal_i2c.h
  • I2C_OA2_MASK03 : stm32f3xx_hal_i2c.h
  • I2C_OA2_MASK04 : stm32f3xx_hal_i2c.h
  • I2C_OA2_MASK05 : stm32f3xx_hal_i2c.h
  • I2C_OA2_MASK06 : stm32f3xx_hal_i2c.h
  • I2C_OA2_MASK07 : stm32f3xx_hal_i2c.h
  • I2C_OA2_NOMASK : stm32f3xx_hal_i2c.h
  • I2C_RELOAD_MODE : stm32f3xx_hal_i2c.h
  • I2C_RequestMemoryRead() : stm32f3xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32f3xx_hal_i2c.c
  • I2C_RESET_CR2 : stm32f3xx_hal_i2c.h
  • I2C_Slave_ISR_DMA() : stm32f3xx_hal_i2c.c
  • I2C_Slave_ISR_IT() : stm32f3xx_hal_i2c.c
  • I2C_SOFTEND_MODE : stm32f3xx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32f3xx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32f3xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_RX : stm32f3xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_TX : stm32f3xx_hal_i2c.c
  • I2C_STATE_MSK : stm32f3xx_hal_i2c.c
  • I2C_STATE_NONE : stm32f3xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32f3xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_ADDR : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_DIR : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_RXNE : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_STOPF : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_TC : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_TCR : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_TXIS : stm32f3xx_hal_i2c.c
  • I2C_TransferConfig() : stm32f3xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32f3xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32f3xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32f3xx_hal_i2c.c
  • I2C_WaitOnTXISFlagUntilTimeout() : stm32f3xx_hal_i2c.c
  • I2C_XFER_CPLT_IT : stm32f3xx_hal_i2c.c
  • I2C_XFER_ERROR_IT : stm32f3xx_hal_i2c.c
  • I2C_XFER_LISTEN_IT : stm32f3xx_hal_i2c.c
  • I2C_XFER_RELOAD_IT : stm32f3xx_hal_i2c.c
  • I2C_XFER_RX_IT : stm32f3xx_hal_i2c.c
  • I2C_XFER_TX_IT : stm32f3xx_hal_i2c.c
  • I2S_AUDIOFREQ_11K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_16K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_192K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_22K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_32K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_44K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_48K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_8K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_96K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_DEFAULT : stm32f3xx_hal_i2s.h
  • I2S_CLOCK_EXTERNAL : stm32f3xx_hal_i2s.h
  • I2S_CLOCK_SYSCLK : stm32f3xx_hal_i2s.h
  • I2S_CPOL_HIGH : stm32f3xx_hal_i2s.h
  • I2S_CPOL_LOW : stm32f3xx_hal_i2s.h
  • I2S_DATAFORMAT_16B : stm32f3xx_hal_i2s.h
  • I2S_DATAFORMAT_16B_EXTENDED : stm32f3xx_hal_i2s.h
  • I2S_DATAFORMAT_24B : stm32f3xx_hal_i2s.h
  • I2S_DATAFORMAT_32B : stm32f3xx_hal_i2s.h
  • I2S_DMAError() : stm32f3xx_hal_i2s.c
  • I2S_DMARxCplt() : stm32f3xx_hal_i2s.c
  • I2S_DMARxHalfCplt() : stm32f3xx_hal_i2s.c
  • I2S_DMATxCplt() : stm32f3xx_hal_i2s.c
  • I2S_DMATxHalfCplt() : stm32f3xx_hal_i2s.c
  • I2S_FLAG_BSY : stm32f3xx_hal_i2s.h
  • I2S_FLAG_CHSIDE : stm32f3xx_hal_i2s.h
  • I2S_FLAG_FRE : stm32f3xx_hal_i2s.h
  • I2S_FLAG_OVR : stm32f3xx_hal_i2s.h
  • I2S_FLAG_RXNE : stm32f3xx_hal_i2s.h
  • I2S_FLAG_TXE : stm32f3xx_hal_i2s.h
  • I2S_FLAG_UDR : stm32f3xx_hal_i2s.h
  • I2S_FULLDUPLEXMODE_DISABLE : stm32f3xx_hal_i2s.h
  • I2S_FULLDUPLEXMODE_ENABLE : stm32f3xx_hal_i2s.h
  • I2S_I2SCFGR_CLEAR_MASK : stm32f3xx_ll_spi.c
  • I2S_I2SPR_CLEAR_MASK : stm32f3xx_ll_spi.c
  • I2S_IT_ERR : stm32f3xx_hal_i2s.h
  • I2S_IT_RXNE : stm32f3xx_hal_i2s.h
  • I2S_IT_TXE : stm32f3xx_hal_i2s.h
  • I2S_MCLKOUTPUT_DISABLE : stm32f3xx_hal_i2s.h
  • I2S_MCLKOUTPUT_ENABLE : stm32f3xx_hal_i2s.h
  • I2S_MODE_MASTER_RX : stm32f3xx_hal_i2s.h
  • I2S_MODE_MASTER_TX : stm32f3xx_hal_i2s.h
  • I2S_MODE_SLAVE_RX : stm32f3xx_hal_i2s.h
  • I2S_MODE_SLAVE_TX : stm32f3xx_hal_i2s.h
  • I2S_Receive_IT() : stm32f3xx_hal_i2s.c
  • I2S_STANDARD_LSB : stm32f3xx_hal_i2s.h
  • I2S_STANDARD_MSB : stm32f3xx_hal_i2s.h
  • I2S_STANDARD_PCM_LONG : stm32f3xx_hal_i2s.h
  • I2S_STANDARD_PCM_SHORT : stm32f3xx_hal_i2s.h
  • I2S_STANDARD_PHILIPS : stm32f3xx_hal_i2s.h
  • I2S_Transmit_IT() : stm32f3xx_hal_i2s.c
  • I2S_WaitFlagStateUntilTimeout() : stm32f3xx_hal_i2s.c
  • IC1Config() : stm32f3xx_ll_tim.c
  • IC2Config() : stm32f3xx_ll_tim.c
  • IC3Config() : stm32f3xx_ll_tim.c
  • IC4Config() : stm32f3xx_ll_tim.c
  • IDCODE_DEVID_MASK : stm32f3xx_hal.c
  • INSTRUCTION_CACHE_ENABLE : stm32f3xx_hal_conf.h
  • IRDA_AUTOBAUD_REQUEST : stm32f3xx_hal_irda.h
  • IRDA_BAUDRATE : stm32f3xx_hal_irda.h
  • IRDA_CheckIdleState() : stm32f3xx_hal_irda.c
  • IRDA_CLEAR_FEF : stm32f3xx_hal_irda.h
  • IRDA_CLEAR_IDLEF : stm32f3xx_hal_irda.h
  • IRDA_CLEAR_NEF : stm32f3xx_hal_irda.h
  • IRDA_CLEAR_OREF : stm32f3xx_hal_irda.h
  • IRDA_CLEAR_PEF : stm32f3xx_hal_irda.h
  • IRDA_CLEAR_TCF : stm32f3xx_hal_irda.h
  • IRDA_CLOCKSOURCE_HSI : stm32f3xx_hal_irda.h
  • IRDA_CLOCKSOURCE_LSE : stm32f3xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK1 : stm32f3xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK2 : stm32f3xx_hal_irda.h
  • IRDA_CLOCKSOURCE_SYSCLK : stm32f3xx_hal_irda.h
  • IRDA_CLOCKSOURCE_UNDEFINED : stm32f3xx_hal_irda.h
  • IRDA_ClockSourceTypeDef : stm32f3xx_hal_irda.h
  • IRDA_ControlTypeDef : stm32f3xx_hal_irda.h
  • IRDA_CR1_FIELDS : stm32f3xx_hal_irda.c
  • IRDA_DMA_RX_DISABLE : stm32f3xx_hal_irda.h
  • IRDA_DMA_RX_ENABLE : stm32f3xx_hal_irda.h
  • IRDA_DMA_TX_DISABLE : stm32f3xx_hal_irda.h
  • IRDA_DMA_TX_ENABLE : stm32f3xx_hal_irda.h
  • IRDA_DMAAbortOnError() : stm32f3xx_hal_irda.c
  • IRDA_DMAError() : stm32f3xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32f3xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32f3xx_hal_irda.c
  • IRDA_DMARxAbortCallback() : stm32f3xx_hal_irda.c
  • IRDA_DMARxOnlyAbortCallback() : stm32f3xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32f3xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32f3xx_hal_irda.c
  • IRDA_DMATxAbortCallback() : stm32f3xx_hal_irda.c
  • IRDA_DMATxOnlyAbortCallback() : stm32f3xx_hal_irda.c
  • IRDA_EndRxTransfer() : stm32f3xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32f3xx_hal_irda.c
  • IRDA_EndTxTransfer() : stm32f3xx_hal_irda.c
  • IRDA_FLAG_ABRE : stm32f3xx_hal_irda.h
  • IRDA_FLAG_ABRF : stm32f3xx_hal_irda.h
  • IRDA_FLAG_BUSY : stm32f3xx_hal_irda.h
  • IRDA_FLAG_FE : stm32f3xx_hal_irda.h
  • IRDA_FLAG_NE : stm32f3xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32f3xx_hal_irda.h
  • IRDA_FLAG_PE : stm32f3xx_hal_irda.h
  • IRDA_FLAG_REACK : stm32f3xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32f3xx_hal_irda.h
  • IRDA_FLAG_TC : stm32f3xx_hal_irda.h
  • IRDA_FLAG_TEACK : stm32f3xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32f3xx_hal_irda.h
  • IRDA_GETCLOCKSOURCE : stm32f3xx_hal_irda_ex.h
  • IRDA_IT_ERR : stm32f3xx_hal_irda.h
  • IRDA_IT_FE : stm32f3xx_hal_irda.h
  • IRDA_IT_IDLE : stm32f3xx_hal_irda.h
  • IRDA_IT_MASK : stm32f3xx_hal_irda.h
  • IRDA_IT_NE : stm32f3xx_hal_irda.h
  • IRDA_IT_ORE : stm32f3xx_hal_irda.h
  • IRDA_IT_PE : stm32f3xx_hal_irda.h
  • IRDA_IT_RXNE : stm32f3xx_hal_irda.h
  • IRDA_IT_TC : stm32f3xx_hal_irda.h
  • IRDA_IT_TXE : stm32f3xx_hal_irda.h
  • IRDA_MASK_COMPUTATION : stm32f3xx_hal_irda_ex.h
  • IRDA_MODE : stm32f3xx_hal_irda.h
  • IRDA_MODE_DISABLE : stm32f3xx_hal_irda.h
  • IRDA_MODE_ENABLE : stm32f3xx_hal_irda.h
  • IRDA_MODE_RX : stm32f3xx_hal_irda.h
  • IRDA_MODE_TX : stm32f3xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32f3xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_DISABLE : stm32f3xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_ENABLE : stm32f3xx_hal_irda.h
  • IRDA_PARITY : stm32f3xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32f3xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32f3xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32f3xx_hal_irda.h
  • IRDA_POWERMODE : stm32f3xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32f3xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32f3xx_hal_irda.h
  • IRDA_PRESCALER : stm32f3xx_hal_irda.h
  • IRDA_Receive_IT() : stm32f3xx_hal_irda.c
  • IRDA_RXDATA_FLUSH_REQUEST : stm32f3xx_hal_irda.h
  • IRDA_SetConfig() : stm32f3xx_hal_irda.c
  • IRDA_STATE_DISABLE : stm32f3xx_hal_irda.h
  • IRDA_STATE_ENABLE : stm32f3xx_hal_irda.h
  • IRDA_TEACK_REACK_TIMEOUT : stm32f3xx_hal_irda.c
  • IRDA_Transmit_IT() : stm32f3xx_hal_irda.c
  • IRDA_TXDATA_FLUSH_REQUEST : stm32f3xx_hal_irda.h
  • IRDA_WaitOnFlagUntilTimeout() : stm32f3xx_hal_irda.c
  • IRDA_WORDLENGTH : stm32f3xx_hal_irda.h
  • IRDA_WORDLENGTH_8B : stm32f3xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_9B : stm32f3xx_hal_irda_ex.h
  • IS_ADC_ANALOG_WATCHDOG_MODE : stm32f3xx_hal_adc_ex.h
  • IS_ADC_CHANNEL : stm32f3xx_hal_adc_ex.h
  • IS_ADC_CONVERSION_GROUP : stm32f3xx_hal_adc_ex.h
  • IS_ADC_DATA_ALIGN : stm32f3xx_hal_adc_ex.h
  • IS_ADC_EVENT_TYPE : stm32f3xx_hal_adc_ex.h
  • IS_ADC_EXTTRIG : stm32f3xx_hal_adc_ex.h
  • IS_ADC_EXTTRIG_EDGE : stm32f3xx_hal_adc_ex.h
  • IS_ADC_EXTTRIGINJEC : stm32f3xx_hal_adc_ex.h
  • IS_ADC_EXTTRIGINJEC_EDGE : stm32f3xx_hal_adc_ex.h
  • IS_ADC_INJECTED_NB_CONV : stm32f3xx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32f3xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32f3xx_hal_adc_ex.h
  • IS_ADC_REGULAR_DISCONT_NUMBER : stm32f3xx_hal_adc_ex.h
  • IS_ADC_REGULAR_NB_CONV : stm32f3xx_hal_adc_ex.h
  • IS_ADC_REGULAR_RANK : stm32f3xx_hal_adc_ex.h
  • IS_ADC_SAMPLE_TIME : stm32f3xx_hal_adc_ex.h
  • IS_ADC_SCAN_MODE : stm32f3xx_hal_adc_ex.h
  • IS_CAN_BANKNUMBER : stm32f3xx_hal_can.h
  • IS_CAN_BS1 : stm32f3xx_hal_can.h
  • IS_CAN_BS2 : stm32f3xx_hal_can.h
  • IS_CAN_CLEAR_IT : stm32f3xx_hal_can.h
  • IS_CAN_DLC : stm32f3xx_hal_can.h
  • IS_CAN_EXTID : stm32f3xx_hal_can.h
  • IS_CAN_FIFO : stm32f3xx_hal_can.h
  • IS_CAN_FILTER_FIFO : stm32f3xx_hal_can.h
  • IS_CAN_FILTER_MODE : stm32f3xx_hal_can.h
  • IS_CAN_FILTER_NUMBER : stm32f3xx_hal_can.h
  • IS_CAN_FILTER_SCALE : stm32f3xx_hal_can.h
  • IS_CAN_IDTYPE : stm32f3xx_hal_can.h
  • IS_CAN_IT : stm32f3xx_hal_can.h
  • IS_CAN_MODE : stm32f3xx_hal_can.h
  • IS_CAN_PRESCALER : stm32f3xx_hal_can.h
  • IS_CAN_RTR : stm32f3xx_hal_can.h
  • IS_CAN_SJW : stm32f3xx_hal_can.h
  • IS_CAN_STDID : stm32f3xx_hal_can.h
  • IS_CAN_TRANSMITMAILBOX : stm32f3xx_hal_can.h
  • IS_CEC_ADDRESS : stm32f3xx_hal_cec.h
  • IS_CEC_BREERRORBITGEN : stm32f3xx_hal_cec.h
  • IS_CEC_BRERXSTOP : stm32f3xx_hal_cec.h
  • IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32f3xx_hal_cec.h
  • IS_CEC_LBPEERRORBITGEN : stm32f3xx_hal_cec.h
  • IS_CEC_LISTENING_MODE : stm32f3xx_hal_cec.h
  • IS_CEC_MSGSIZE : stm32f3xx_hal_cec.h
  • IS_CEC_OWN_ADDRESS : stm32f3xx_hal_cec.h
  • IS_CEC_SFTOP : stm32f3xx_hal_cec.h
  • IS_CEC_SIGNALFREETIME : stm32f3xx_hal_cec.h
  • IS_CEC_TOLERANCE : stm32f3xx_hal_cec.h
  • IS_COMP_BLANKINGSRCE : stm32f3xx_hal_comp_ex.h
  • IS_COMP_BLANKINGSRCE_INSTANCE : stm32f3xx_hal_comp_ex.h
  • IS_COMP_HYSTERESIS : stm32f3xx_hal_comp_ex.h
  • IS_COMP_INVERTINGINPUT : stm32f3xx_hal_comp_ex.h
  • IS_COMP_MODE : stm32f3xx_hal_comp_ex.h
  • IS_COMP_NONINVERTINGINPUT : stm32f3xx_hal_comp_ex.h
  • IS_COMP_NONINVERTINGINPUT_INSTANCE : stm32f3xx_hal_comp_ex.h
  • IS_COMP_OUTPUT : stm32f3xx_hal_comp_ex.h
  • IS_COMP_OUTPUT_INSTANCE : stm32f3xx_hal_comp_ex.h
  • IS_COMP_OUTPUTPOL : stm32f3xx_hal_comp.h
  • IS_COMP_TRIGGERMODE : stm32f3xx_hal_comp.h
  • IS_COMP_WINDOWMODE : stm32f3xx_hal_comp_ex.h
  • IS_CRC_INPUTDATA_FORMAT : stm32f3xx_hal_crc.h
  • IS_CRC_INPUTDATA_INVERSION_MODE : stm32f3xx_hal_crc_ex.h
  • IS_CRC_OUTPUTDATA_INVERSION_MODE : stm32f3xx_hal_crc_ex.h
  • IS_CRC_POL_LENGTH : stm32f3xx_hal_crc.h
  • IS_DAC_ALIGN : stm32f3xx_hal_dac.h
  • IS_DAC_CHANNEL : stm32f3xx_hal_dac_ex.h
  • IS_DAC_DATA : stm32f3xx_hal_dac.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32f3xx_hal_dac.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32f3xx_hal_dac.h
  • IS_DAC_TRIGGER : stm32f3xx_hal_dac_ex.h
  • IS_DEFAULT_INIT_VALUE : stm32f3xx_hal_crc.h
  • IS_DEFAULT_POLYNOMIAL : stm32f3xx_hal_crc.h
  • IS_DMA_BUFFER_SIZE : stm32f3xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32f3xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32f3xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32f3xx_hal_dma.h
  • IS_DMA_MODE : stm32f3xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32f3xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32f3xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32f3xx_hal_dma.h
  • IS_DMA_REMAP : stm32f3xx_hal.h
  • IS_FLASH_LATENCY : stm32f3xx_hal_flash.h
  • IS_FLASH_NB_PAGES : stm32f3xx_hal_flash_ex.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32f3xx_hal_flash_ex.h
  • IS_FLASH_TYPEERASE : stm32f3xx_hal_flash_ex.h
  • IS_FLASH_TYPEPROGRAM : stm32f3xx_hal_flash.h
  • IS_GPIO_AF : stm32f3xx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32f3xx_hal_gpio.h
  • IS_GPIO_PIN : stm32f3xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32f3xx_hal_gpio.h
  • IS_GPIO_PULL : stm32f3xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32f3xx_hal_gpio.h
  • IS_HAL_REMAPTRIGGER : stm32f3xx_hal.h
  • IS_HAL_SYSCFG_INTERRUPT : stm32f3xx_hal.h
  • IS_I2C_ADDRESSING_MODE : stm32f3xx_hal_i2c.h
  • IS_I2C_ANALOG_FILTER : stm32f3xx_hal_i2c_ex.h
  • IS_I2C_DIGITAL_FILTER : stm32f3xx_hal_i2c_ex.h
  • IS_I2C_DUAL_ADDRESS : stm32f3xx_hal_i2c.h
  • IS_I2C_FASTMODEPLUS : stm32f3xx_hal_i2c_ex.h
  • IS_I2C_GENERAL_CALL : stm32f3xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32f3xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32f3xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32f3xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32f3xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2_MASK : stm32f3xx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32f3xx_hal_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32f3xx_hal_i2s.h
  • IS_I2S_CLOCKSOURCE : stm32f3xx_hal_i2s.h
  • IS_I2S_CPOL : stm32f3xx_hal_i2s.h
  • IS_I2S_DATA_FORMAT : stm32f3xx_hal_i2s.h
  • IS_I2S_FULLDUPLEX_MODE : stm32f3xx_hal_i2s.h
  • IS_I2S_MCLK_OUTPUT : stm32f3xx_hal_i2s.h
  • IS_I2S_MODE : stm32f3xx_hal_i2s.h
  • IS_I2S_STANDARD : stm32f3xx_hal_i2s.h
  • IS_IRDA_BAUDRATE : stm32f3xx_hal_irda.h
  • IS_IRDA_DMA_RX : stm32f3xx_hal_irda.h
  • IS_IRDA_DMA_TX : stm32f3xx_hal_irda.h
  • IS_IRDA_MODE : stm32f3xx_hal_irda.h
  • IS_IRDA_ONE_BIT_SAMPLE : stm32f3xx_hal_irda.h
  • IS_IRDA_PARITY : stm32f3xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32f3xx_hal_irda.h
  • IS_IRDA_PRESCALER : stm32f3xx_hal_irda.h
  • IS_IRDA_REQUEST_PARAMETER : stm32f3xx_hal_irda.h
  • IS_IRDA_STATE : stm32f3xx_hal_irda.h
  • IS_IRDA_TX_RX_MODE : stm32f3xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32f3xx_hal_irda_ex.h
  • IS_IWDG_PRESCALER : stm32f3xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32f3xx_hal_iwdg.h
  • IS_IWDG_WINDOW : stm32f3xx_hal_iwdg.h
  • IS_LL_ADC_DATA_ALIGN : stm32f3xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE : stm32f3xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_LENGTH : stm32f3xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_AUTO : stm32f3xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_SOURCE : stm32f3xx_ll_adc.c
  • IS_LL_ADC_REG_CONTINUOUS_MODE : stm32f3xx_ll_adc.c
  • IS_LL_ADC_REG_DMA_TRANSFER : stm32f3xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE : stm32f3xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_LENGTH : stm32f3xx_ll_adc.c
  • IS_LL_ADC_REG_TRIG_SOURCE : stm32f3xx_ll_adc.c
  • IS_LL_ADC_SCAN_SELECTION : stm32f3xx_ll_adc.c
  • IS_LL_ADC_SEQ_SCAN_MODE : stm32f3xx_ll_adc.c
  • IS_LL_COMP_INPUT_HYSTERESIS : stm32f3xx_ll_comp.c
  • IS_LL_COMP_INPUT_MINUS : stm32f3xx_ll_comp.c
  • IS_LL_COMP_INPUT_PLUS : stm32f3xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_POLARITY : stm32f3xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_SELECTION : stm32f3xx_ll_comp.c
  • IS_LL_COMP_POWER_MODE : stm32f3xx_ll_comp.c
  • IS_LL_DAC_CHANNEL : stm32f3xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_BUFFER : stm32f3xx_ll_dac.c
  • IS_LL_DAC_TRIGGER_SOURCE : stm32f3xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_CONFIG : stm32f3xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_MODE : stm32f3xx_ll_dac.c
  • IS_LL_DMA_ALL_CHANNEL_INSTANCE : stm32f3xx_ll_dma.c
  • IS_LL_DMA_DIRECTION : stm32f3xx_ll_dma.c
  • IS_LL_DMA_MEMORYDATASIZE : stm32f3xx_ll_dma.c
  • IS_LL_DMA_MEMORYINCMODE : stm32f3xx_ll_dma.c
  • IS_LL_DMA_MODE : stm32f3xx_ll_dma.c
  • IS_LL_DMA_NBDATA : stm32f3xx_ll_dma.c
  • IS_LL_DMA_PERIPHDATASIZE : stm32f3xx_ll_dma.c
  • IS_LL_DMA_PERIPHINCMODE : stm32f3xx_ll_dma.c
  • IS_LL_DMA_PRIORITY : stm32f3xx_ll_dma.c
  • IS_LL_EXTI_LINE_0_31 : stm32f3xx_ll_exti.c
  • IS_LL_EXTI_MODE : stm32f3xx_ll_exti.c
  • IS_LL_EXTI_TRIGGER : stm32f3xx_ll_exti.c
  • IS_LL_GPIO_ALTERNATE : stm32f3xx_ll_gpio.c
  • IS_LL_GPIO_MODE : stm32f3xx_ll_gpio.c
  • IS_LL_GPIO_OUTPUT_TYPE : stm32f3xx_ll_gpio.c
  • IS_LL_GPIO_PIN : stm32f3xx_ll_gpio.c
  • IS_LL_GPIO_PULL : stm32f3xx_ll_gpio.c
  • IS_LL_GPIO_SPEED : stm32f3xx_ll_gpio.c
  • IS_LL_I2C_ANALOG_FILTER : stm32f3xx_ll_i2c.c
  • IS_LL_I2C_DIGITAL_FILTER : stm32f3xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRESS1 : stm32f3xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRSIZE : stm32f3xx_ll_i2c.c
  • IS_LL_I2C_PERIPHERAL_MODE : stm32f3xx_ll_i2c.c
  • IS_LL_I2C_TYPE_ACKNOWLEDGE : stm32f3xx_ll_i2c.c
  • IS_LL_I2S_AUDIO_FREQ : stm32f3xx_ll_spi.c
  • IS_LL_I2S_CPOL : stm32f3xx_ll_spi.c
  • IS_LL_I2S_DATAFORMAT : stm32f3xx_ll_spi.c
  • IS_LL_I2S_MCLK_OUTPUT : stm32f3xx_ll_spi.c
  • IS_LL_I2S_MODE : stm32f3xx_ll_spi.c
  • IS_LL_I2S_PRESCALER_LINEAR : stm32f3xx_ll_spi.c
  • IS_LL_I2S_PRESCALER_PARITY : stm32f3xx_ll_spi.c
  • IS_LL_I2S_STANDARD : stm32f3xx_ll_spi.c
  • IS_LL_RCC_ADC_CLKSOURCE : stm32f3xx_ll_rcc.c
  • IS_LL_RCC_CEC_CLKSOURCE : stm32f3xx_ll_rcc.c
  • IS_LL_RCC_I2C_CLKSOURCE : stm32f3xx_ll_rcc.c
  • IS_LL_RCC_I2S_CLKSOURCE : stm32f3xx_ll_rcc.c
  • IS_LL_RCC_SDADC_CLKSOURCE : stm32f3xx_ll_rcc.c
  • IS_LL_RCC_USART_CLKSOURCE : stm32f3xx_ll_rcc.c
  • IS_LL_RCC_USB_CLKSOURCE : stm32f3xx_ll_rcc.c
  • IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_ALMA_MASK : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_ALMB_MASK : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_ASYNCH_PREDIV : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_DAY : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_FORMAT : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_HOUR12 : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_HOUR24 : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_HOURFORMAT : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_MINUTES : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_MONTH : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_SECONDS : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_SYNCH_PREDIV : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_TIME_FORMAT : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_WEEKDAY : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_YEAR : stm32f3xx_ll_rtc.c
  • IS_LL_SPI_BAUDRATE : stm32f3xx_ll_spi.c
  • IS_LL_SPI_BITORDER : stm32f3xx_ll_spi.c
  • IS_LL_SPI_CRC_POLYNOMIAL : stm32f3xx_ll_spi.c
  • IS_LL_SPI_CRCCALCULATION : stm32f3xx_ll_spi.c
  • IS_LL_SPI_DATAWIDTH : stm32f3xx_ll_spi.c
  • IS_LL_SPI_MODE : stm32f3xx_ll_spi.c
  • IS_LL_SPI_NSS : stm32f3xx_ll_spi.c
  • IS_LL_SPI_PHASE : stm32f3xx_ll_spi.c
  • IS_LL_SPI_POLARITY : stm32f3xx_ll_spi.c
  • IS_LL_SPI_TRANSFER_DIRECTION : stm32f3xx_ll_spi.c
  • IS_LL_TIM_ACTIVEINPUT : stm32f3xx_ll_tim.c
  • IS_LL_TIM_AUTOMATIC_OUTPUT_STATE : stm32f3xx_ll_tim.c
  • IS_LL_TIM_BREAK_POLARITY : stm32f3xx_ll_tim.c
  • IS_LL_TIM_BREAK_STATE : stm32f3xx_ll_tim.c
  • IS_LL_TIM_CLOCKDIVISION : stm32f3xx_ll_tim.c
  • IS_LL_TIM_COUNTERMODE : stm32f3xx_ll_tim.c
  • IS_LL_TIM_ENCODERMODE : stm32f3xx_ll_tim.c
  • IS_LL_TIM_IC_FILTER : stm32f3xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY : stm32f3xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY_ENCODER : stm32f3xx_ll_tim.c
  • IS_LL_TIM_ICPSC : stm32f3xx_ll_tim.c
  • IS_LL_TIM_LOCK_LEVEL : stm32f3xx_ll_tim.c
  • IS_LL_TIM_OCIDLESTATE : stm32f3xx_ll_tim.c
  • IS_LL_TIM_OCMODE : stm32f3xx_ll_tim.c
  • IS_LL_TIM_OCPOLARITY : stm32f3xx_ll_tim.c
  • IS_LL_TIM_OCSTATE : stm32f3xx_ll_tim.c
  • IS_LL_TIM_OSSI_STATE : stm32f3xx_ll_tim.c
  • IS_LL_TIM_OSSR_STATE : stm32f3xx_ll_tim.c
  • IS_LL_USART_BAUDRATE : stm32f3xx_ll_usart.c
  • IS_LL_USART_BRR_MAX : stm32f3xx_ll_usart.c
  • IS_LL_USART_BRR_MIN : stm32f3xx_ll_usart.c
  • IS_LL_USART_CLOCKOUTPUT : stm32f3xx_ll_usart.c
  • IS_LL_USART_CLOCKPHASE : stm32f3xx_ll_usart.c
  • IS_LL_USART_CLOCKPOLARITY : stm32f3xx_ll_usart.c
  • IS_LL_USART_DATAWIDTH : stm32f3xx_ll_usart.c
  • IS_LL_USART_DIRECTION : stm32f3xx_ll_usart.c
  • IS_LL_USART_HWCONTROL : stm32f3xx_ll_usart.c
  • IS_LL_USART_LASTBITCLKOUTPUT : stm32f3xx_ll_usart.c
  • IS_LL_USART_OVERSAMPLING : stm32f3xx_ll_usart.c
  • IS_LL_USART_PARITY : stm32f3xx_ll_usart.c
  • IS_LL_USART_STOPBITS : stm32f3xx_ll_usart.c
  • IS_LL_UTILS_APB1_DIV : stm32f3xx_ll_utils.c
  • IS_LL_UTILS_APB2_DIV : stm32f3xx_ll_utils.c
  • IS_LL_UTILS_HSE_BYPASS : stm32f3xx_ll_utils.c
  • IS_LL_UTILS_HSE_FREQUENCY : stm32f3xx_ll_utils.c
  • IS_LL_UTILS_PLL_FREQUENCY : stm32f3xx_ll_utils.c
  • IS_LL_UTILS_PLLMUL_VALUE : stm32f3xx_ll_utils.c
  • IS_LL_UTILS_PREDIV_VALUE : stm32f3xx_ll_utils.c
  • IS_LL_UTILS_SYSCLK_DIV : stm32f3xx_ll_utils.c
  • IS_MPU_ACCESS_BUFFERABLE : stm32f3xx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32f3xx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32f3xx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32f3xx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32f3xx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32f3xx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32f3xx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32f3xx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32f3xx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32f3xx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32f3xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32f3xx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32f3xx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32f3xx_hal_cortex.h
  • IS_OB_BOOT1 : stm32f3xx_hal_flash_ex.h
  • IS_OB_DATA_ADDRESS : stm32f3xx_hal_flash_ex.h
  • IS_OB_IWDG_SOURCE : stm32f3xx_hal_flash_ex.h
  • IS_OB_RDP_LEVEL : stm32f3xx_hal_flash_ex.h
  • IS_OB_SDACD_VDD_MONITOR : stm32f3xx_hal_flash_ex.h
  • IS_OB_SRAM_PARITY : stm32f3xx_hal_flash_ex.h
  • IS_OB_STDBY_SOURCE : stm32f3xx_hal_flash_ex.h
  • IS_OB_STOP_SOURCE : stm32f3xx_hal_flash_ex.h
  • IS_OB_VDDA_ANALOG : stm32f3xx_hal_flash_ex.h
  • IS_OB_WRP : stm32f3xx_hal_flash_ex.h
  • IS_OPTIONBYTE : stm32f3xx_hal_flash_ex.h
  • IS_PCD_ALL_INSTANCE : stm32f3xx_hal_pcd.h
  • IS_PWR_PVD_LEVEL : stm32f3xx_hal_pwr_ex.h
  • IS_PWR_PVD_MODE : stm32f3xx_hal_pwr_ex.h
  • IS_PWR_REGULATOR : stm32f3xx_hal_pwr.h
  • IS_PWR_SDADC_ANALOG : stm32f3xx_hal_pwr_ex.h
  • IS_PWR_SLEEP_ENTRY : stm32f3xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32f3xx_hal_pwr.h
  • IS_PWR_WAKEUP_PIN : stm32f3xx_hal_pwr.h
  • IS_RCC_ADC1PCLK2_DIV : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_CALIBRATION_VALUE : stm32f3xx_hal_rcc.h
  • IS_RCC_CECCLKSOURCE : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_CLOCKTYPE : stm32f3xx_hal_rcc.h
  • IS_RCC_HCLK : stm32f3xx_hal_rcc.h
  • IS_RCC_HSE : stm32f3xx_hal_rcc.h
  • IS_RCC_HSE_PREDIV : stm32f3xx_hal_rcc.h
  • IS_RCC_HSI : stm32f3xx_hal_rcc.h
  • IS_RCC_I2C1CLKSOURCE : stm32f3xx_hal_rcc.h
  • IS_RCC_I2C2CLKSOURCE : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32f3xx_hal_rcc.h
  • IS_RCC_LSE_DRIVE : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_LSI : stm32f3xx_hal_rcc.h
  • IS_RCC_MCO : stm32f3xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_MCODIV : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_OSCILLATORTYPE : stm32f3xx_hal_rcc.h
  • IS_RCC_PCLK : stm32f3xx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32f3xx_hal_rcc.h
  • IS_RCC_PLL_DIV : stm32f3xx_hal_rcc.h
  • IS_RCC_PLL_MUL : stm32f3xx_hal_rcc.h
  • IS_RCC_PLLSOURCE : stm32f3xx_hal_rcc.h
  • IS_RCC_RTCCLKSOURCE : stm32f3xx_hal_rcc.h
  • IS_RCC_SDADCSYSCLK_DIV : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_SYSCLKSOURCE : stm32f3xx_hal_rcc.h
  • IS_RCC_SYSCLKSOURCE_STATUS : stm32f3xx_hal_rcc.h
  • IS_RCC_USART1CLKSOURCE : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_USART2CLKSOURCE : stm32f3xx_hal_rcc.h
  • IS_RCC_USART3CLKSOURCE : stm32f3xx_hal_rcc.h
  • IS_RCC_USBCLKSOURCE : stm32f3xx_hal_rcc_ex.h
  • IS_RTC_ALARM : stm32f3xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32f3xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32f3xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32f3xx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32f3xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32f3xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32f3xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32f3xx_hal_rtc.h
  • IS_RTC_BKP : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32f3xx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32f3xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32f3xx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32f3xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32f3xx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32f3xx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32f3xx_hal_rtc.h
  • IS_RTC_MINUTES : stm32f3xx_hal_rtc.h
  • IS_RTC_MONTH : stm32f3xx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_OUTPUT_POL : stm32f3xx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32f3xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32f3xx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32f3xx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32f3xx_hal_rtc.h
  • IS_RTC_TAMPER : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32f3xx_hal_rtc.h
  • IS_RTC_YEAR : stm32f3xx_hal_rtc.h
  • IS_SDADC_CALIB_SEQUENCE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_COMMON_MODE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_CONF_INDEX : stm32f3xx_hal_sdadc.h
  • IS_SDADC_CONTINUOUS_MODE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_EXT_INJEC_TRIG : stm32f3xx_hal_sdadc.h
  • IS_SDADC_EXT_TRIG_EDGE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_FAST_CONV_MODE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_GAIN : stm32f3xx_hal_sdadc.h
  • IS_SDADC_INJECTED_CHANNEL : stm32f3xx_hal_sdadc.h
  • IS_SDADC_INJECTED_DELAY : stm32f3xx_hal_sdadc.h
  • IS_SDADC_INJECTED_TRIGGER : stm32f3xx_hal_sdadc.h
  • IS_SDADC_INPUT_MODE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_LOWPOWER_MODE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_MULTIMODE_TYPE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_OFFSET_VALUE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_REGULAR_CHANNEL : stm32f3xx_hal_sdadc.h
  • IS_SDADC_REGULAR_TRIGGER : stm32f3xx_hal_sdadc.h
  • IS_SDADC_SLOW_CLOCK_MODE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_VREF : stm32f3xx_hal_sdadc.h
  • IS_SMARTCARD_ADVFEATURE_DATAINV : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_DMAONRXERROR : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_INIT : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_MSBFIRST : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_RXINV : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_SWAP : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_TXINV : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_AUTORETRY_COUNT : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_BAUDRATE : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_BLOCKLENGTH : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_LASTBIT : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_NACK : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_ONE_BIT_SAMPLE : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_OVERRUN : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_REQUEST_PARAMETER : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_STOPBITS : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT_VALUE : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_WORD_LENGTH : stm32f3xx_hal_smartcard.h
  • IS_SMBUS_ADDRESSING_MODE : stm32f3xx_hal_smbus.h
  • IS_SMBUS_ANALOG_FILTER : stm32f3xx_hal_smbus.h
  • IS_SMBUS_DIGITAL_FILTER : stm32f3xx_hal_smbus.h
  • IS_SMBUS_DUAL_ADDRESS : stm32f3xx_hal_smbus.h
  • IS_SMBUS_GENERAL_CALL : stm32f3xx_hal_smbus.h
  • IS_SMBUS_NO_STRETCH : stm32f3xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS1 : stm32f3xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2 : stm32f3xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2_MASK : stm32f3xx_hal_smbus.h
  • IS_SMBUS_PEC : stm32f3xx_hal_smbus.h
  • IS_SMBUS_PERIPHERAL_MODE : stm32f3xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_MODE : stm32f3xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OPTIONS_REQUEST : stm32f3xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST : stm32f3xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_REQUEST : stm32f3xx_hal_smbus.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32f3xx_hal_spi.h
  • IS_SPI_CPHA : stm32f3xx_hal_spi.h
  • IS_SPI_CPOL : stm32f3xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32f3xx_hal_spi.h
  • IS_SPI_CRC_LENGTH : stm32f3xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32f3xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32f3xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32f3xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32f3xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE : stm32f3xx_hal_spi.h
  • IS_SPI_DMA_HANDLE : stm32f3xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32f3xx_hal_spi.h
  • IS_SPI_MODE : stm32f3xx_hal_spi.h
  • IS_SPI_NSS : stm32f3xx_hal_spi.h
  • IS_SPI_NSSP : stm32f3xx_hal_spi.h
  • IS_SPI_TIMODE : stm32f3xx_hal_spi.h
  • IS_SYSCFG_FASTMODEPLUS : stm32f3xx_hal.h
  • IS_SYSTICK_CLK_SOURCE : stm32f3xx_hal_cortex.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32f3xx_hal_tim.h
  • IS_TIM_AUTORELOAD_PRELOAD : stm32f3xx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32f3xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32f3xx_hal_tim.h
  • IS_TIM_CHANNELS : stm32f3xx_hal_tim_ex.h
  • IS_TIM_CLEARINPUT_FILTER : stm32f3xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32f3xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32f3xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32f3xx_hal_tim_ex.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32f3xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32f3xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32f3xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32f3xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32f3xx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32f3xx_hal_tim_ex.h
  • IS_TIM_COUNTER_MODE : stm32f3xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32f3xx_hal_tim_ex.h
  • IS_TIM_DMA_BASE : stm32f3xx_hal_tim_ex.h
  • IS_TIM_DMA_DATA_LENGTH : stm32f3xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32f3xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32f3xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32f3xx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32f3xx_hal_tim_ex.h
  • IS_TIM_FAST_STATE : stm32f3xx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32f3xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32f3xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32f3xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32f3xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32f3xx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32f3xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32f3xx_hal_tim.h
  • IS_TIM_OC_MODE : stm32f3xx_hal_tim_ex.h
  • IS_TIM_OC_POLARITY : stm32f3xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32f3xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32f3xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32f3xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32f3xx_hal_tim_ex.h
  • IS_TIM_OPM_MODE : stm32f3xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32f3xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32f3xx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32f3xx_hal_tim_ex.h
  • IS_TIM_REMAP : stm32f3xx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32f3xx_hal_tim_ex.h
  • IS_TIM_TI1SELECTION : stm32f3xx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32f3xx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32f3xx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32f3xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32f3xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32f3xx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32f3xx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32f3xx_hal_i2c.h
  • IS_TRANSFER_REQUEST : stm32f3xx_hal_i2c.h
  • IS_TSC_ACQ_MODE : stm32f3xx_hal_tsc.h
  • IS_TSC_CTPH : stm32f3xx_hal_tsc.h
  • IS_TSC_CTPL : stm32f3xx_hal_tsc.h
  • IS_TSC_GROUP_INDEX : stm32f3xx_hal_tsc.h
  • IS_TSC_IODEF : stm32f3xx_hal_tsc.h
  • IS_TSC_IOMODE : stm32f3xx_hal_tsc.h
  • IS_TSC_MCE_IT : stm32f3xx_hal_tsc.h
  • IS_TSC_MCV : stm32f3xx_hal_tsc.h
  • IS_TSC_PG_PRESC : stm32f3xx_hal_tsc.h
  • IS_TSC_SS : stm32f3xx_hal_tsc.h
  • IS_TSC_SS_PRESC : stm32f3xx_hal_tsc.h
  • IS_TSC_SSD : stm32f3xx_hal_tsc.h
  • IS_TSC_SYNC_POL : stm32f3xx_hal_tsc.h
  • IS_UART_ADDRESSLENGTH_DETECT : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATE : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATEMODE : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_DATAINV : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_DMAONRXERROR : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_INIT : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_MSBFIRST : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_RXINV : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_STOPMODE : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_SWAP : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_TXINV : stm32f3xx_hal_uart.h
  • IS_UART_ASSERTIONTIME : stm32f3xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32f3xx_hal_uart.h
  • IS_UART_DE_POLARITY : stm32f3xx_hal_uart.h
  • IS_UART_DEASSERTIONTIME : stm32f3xx_hal_uart.h
  • IS_UART_DMA_RX : stm32f3xx_hal_uart.h
  • IS_UART_DMA_TX : stm32f3xx_hal_uart.h
  • IS_UART_HALF_DUPLEX : stm32f3xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32f3xx_hal_uart.h
  • IS_UART_LIN : stm32f3xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32f3xx_hal_uart.h
  • IS_UART_MODE : stm32f3xx_hal_uart.h
  • IS_UART_MUTE_MODE : stm32f3xx_hal_uart.h
  • IS_UART_ONE_BIT_SAMPLE : stm32f3xx_hal_uart.h
  • IS_UART_OVERRUN : stm32f3xx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32f3xx_hal_uart.h
  • IS_UART_PARITY : stm32f3xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT : stm32f3xx_hal_uart.h
  • IS_UART_REQUEST_PARAMETER : stm32f3xx_hal_uart.h
  • IS_UART_STATE : stm32f3xx_hal_uart.h
  • IS_UART_STOPBITS : stm32f3xx_hal_uart.h
  • IS_UART_WAKEUP_SELECTION : stm32f3xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32f3xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32f3xx_hal_uart_ex.h
  • IS_USART_BAUDRATE : stm32f3xx_hal_usart.h
  • IS_USART_CLOCK : stm32f3xx_hal_usart.h
  • IS_USART_LASTBIT : stm32f3xx_hal_usart.h
  • IS_USART_MODE : stm32f3xx_hal_usart.h
  • IS_USART_PARITY : stm32f3xx_hal_usart.h
  • IS_USART_PHASE : stm32f3xx_hal_usart.h
  • IS_USART_POLARITY : stm32f3xx_hal_usart.h
  • IS_USART_REQUEST_PARAMETER : stm32f3xx_hal_usart.h
  • IS_USART_STOPBITS : stm32f3xx_hal_usart.h
  • IS_USART_WORD_LENGTH : stm32f3xx_hal_usart_ex.h
  • IS_WRPSTATE : stm32f3xx_hal_flash_ex.h
  • IS_WWDG_COUNTER : stm32f3xx_hal_wwdg.h
  • IS_WWDG_EWI_MODE : stm32f3xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32f3xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32f3xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32f3xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32f3xx_hal_iwdg.h
  • IWDG_KEY_ENABLE : stm32f3xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32f3xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32f3xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32f3xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32f3xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32f3xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32f3xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32f3xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32f3xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32f3xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32f3xx_hal_iwdg.h
  • IWDG_WINDOW_DISABLE : stm32f3xx_hal_iwdg.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- l -

  • LL_ADC_AWD1 : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_DISABLE : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_HIGH : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_LOW : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_0 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_1 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_10 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_11 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_12 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_13 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_14 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_15 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_16 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_17 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_2 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_3 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_4 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_5 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_6 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_7 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_8 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_9 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_TEMPSENSOR : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_VREFINT : stm32f3xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD1() : stm32f3xx_ll_adc.h
  • LL_ADC_ClearFlag_EOS() : stm32f3xx_ll_adc.h
  • LL_ADC_ClearFlag_JEOS() : stm32f3xx_ll_adc.h
  • LL_ADC_CommonDeInit() : stm32f3xx_ll_adc.c
  • LL_ADC_DATA_ALIGN_LEFT : stm32f3xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_RIGHT : stm32f3xx_ll_adc.h
  • LL_ADC_DeInit() : stm32f3xx_ll_adc.c
  • LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES : stm32f3xx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_STAB_US : stm32f3xx_ll_adc.h
  • LL_ADC_Disable() : stm32f3xx_ll_adc.h
  • LL_ADC_DisableIT_AWD1() : stm32f3xx_ll_adc.h
  • LL_ADC_DisableIT_EOS() : stm32f3xx_ll_adc.h
  • LL_ADC_DisableIT_JEOS() : stm32f3xx_ll_adc.h
  • LL_ADC_DMA_GetRegAddr() : stm32f3xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA : stm32f3xx_ll_adc.h
  • LL_ADC_Enable() : stm32f3xx_ll_adc.h
  • LL_ADC_EnableIT_AWD1() : stm32f3xx_ll_adc.h
  • LL_ADC_EnableIT_EOS() : stm32f3xx_ll_adc.h
  • LL_ADC_EnableIT_JEOS() : stm32f3xx_ll_adc.h
  • LL_ADC_FLAG_AWD1 : stm32f3xx_ll_adc.h
  • LL_ADC_FLAG_EOS : stm32f3xx_ll_adc.h
  • LL_ADC_FLAG_JEOS : stm32f3xx_ll_adc.h
  • LL_ADC_FLAG_JSTRT : stm32f3xx_ll_adc.h
  • LL_ADC_FLAG_STRT : stm32f3xx_ll_adc.h
  • LL_ADC_GetAnalogWDMonitChannels() : stm32f3xx_ll_adc.h
  • LL_ADC_GetAnalogWDThresholds() : stm32f3xx_ll_adc.h
  • LL_ADC_GetChannelSamplingTime() : stm32f3xx_ll_adc.h
  • LL_ADC_GetCommonPathInternalCh() : stm32f3xx_ll_adc.h
  • LL_ADC_GetDataAlignment() : stm32f3xx_ll_adc.h
  • LL_ADC_GetSequencersScanMode() : stm32f3xx_ll_adc.h
  • LL_ADC_GROUP_INJECTED : stm32f3xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR : stm32f3xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR_INJECTED : stm32f3xx_ll_adc.h
  • LL_ADC_Init() : stm32f3xx_ll_adc.c
  • LL_ADC_INJ_GetOffset() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerDiscont() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerLength() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerRanks() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_GetTrigAuto() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_GetTriggerSource() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_Init() : stm32f3xx_ll_adc.c
  • LL_ADC_INJ_IsTriggerSourceSWStart() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_RANK_1 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_RANK_2 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_RANK_3 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_RANK_4 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData12() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData32() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_1RANK : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_DISABLE : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SetOffset() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerDiscont() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerLength() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerRanks() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SetTrigAuto() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SetTriggerSource() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_StartConversion() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_StopConversionExtTrig() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_StructInit() : stm32f3xx_ll_adc.c
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISING : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM19_CH1 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM19_CH2 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_INDEPENDENT : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_SOFTWARE : stm32f3xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD1() : stm32f3xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOS() : stm32f3xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOS() : stm32f3xx_ll_adc.h
  • LL_ADC_IsCalibrationOnGoing() : stm32f3xx_ll_adc.h
  • LL_ADC_IsEnabled() : stm32f3xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD1() : stm32f3xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOS() : stm32f3xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOS() : stm32f3xx_ll_adc.h
  • LL_ADC_IT_AWD1 : stm32f3xx_ll_adc.h
  • LL_ADC_IT_EOS : stm32f3xx_ll_adc.h
  • LL_ADC_IT_JEOS : stm32f3xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_NONE : stm32f3xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR : stm32f3xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VREFINT : stm32f3xx_ll_adc.h
  • LL_ADC_ReadReg : stm32f3xx_ll_adc.h
  • LL_ADC_REG_CONV_CONTINUOUS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_CONV_SINGLE : stm32f3xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_NONE : stm32f3xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED : stm32f3xx_ll_adc.h
  • LL_ADC_REG_GetContinuousMode() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_GetDMATransfer() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_GetSequencerDiscont() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_GetSequencerLength() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_GetSequencerRanks() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_GetTriggerSource() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_Init() : stm32f3xx_ll_adc.c
  • LL_ADC_REG_IsTriggerSourceSWStart() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_1 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_10 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_11 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_12 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_13 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_14 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_15 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_16 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_2 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_3 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_4 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_5 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_6 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_7 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_8 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_9 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData12() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData32() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_1RANK : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_2RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_3RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_4RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_5RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_6RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_7RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_8RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_DISABLE : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DISABLE : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SetContinuousMode() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SetDMATransfer() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SetSequencerDiscont() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SetSequencerLength() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SetSequencerRanks() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SetTriggerSource() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_StartConversion() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_StopConversionExtTrig() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_StructInit() : stm32f3xx_ll_adc.c
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISING : stm32f3xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM19_CH3 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM19_CH4 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM19_TRGO : stm32f3xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO : stm32f3xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_CH2 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_TRIG_SOFTWARE : stm32f3xx_ll_adc.h
  • LL_ADC_RESOLUTION_12B : stm32f3xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_13CYCLES_5 : stm32f3xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_1CYCLE_5 : stm32f3xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_239CYCLES_5 : stm32f3xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_28CYCLES_5 : stm32f3xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_41CYCLES_5 : stm32f3xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_55CYCLES_5 : stm32f3xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_71CYCLES_5 : stm32f3xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_7CYCLES_5 : stm32f3xx_ll_adc.h
  • LL_ADC_SEQ_SCAN_DISABLE : stm32f3xx_ll_adc.h
  • LL_ADC_SEQ_SCAN_ENABLE : stm32f3xx_ll_adc.h
  • LL_ADC_SetAnalogWDMonitChannels() : stm32f3xx_ll_adc.h
  • LL_ADC_SetAnalogWDThresholds() : stm32f3xx_ll_adc.h
  • LL_ADC_SetChannelSamplingTime() : stm32f3xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalCh() : stm32f3xx_ll_adc.h
  • LL_ADC_SetDataAlignment() : stm32f3xx_ll_adc.h
  • LL_ADC_SetSequencersScanMode() : stm32f3xx_ll_adc.h
  • LL_ADC_StartCalibration() : stm32f3xx_ll_adc.h
  • LL_ADC_StructInit() : stm32f3xx_ll_adc.c
  • LL_ADC_WriteReg : stm32f3xx_ll_adc.h
  • LL_AHB1_GRP1_DisableClock() : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClock() : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_ForceReset() : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_IsEnabledClock() : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_ALL : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CRC : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA1 : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA2 : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_FLASH : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_GPIOA : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_GPIOB : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_GPIOC : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_GPIOD : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_GPIOE : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_GPIOF : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_SRAM : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_TSC : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_ReleaseReset() : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_DisableClock() : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_EnableClock() : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_ForceReset() : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_IsEnabledClock() : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_ALL : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CAN : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CEC : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_DAC1 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_DAC2 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C1 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C2 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_PWR : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI2 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI3 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM12 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM13 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM14 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM18 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM2 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM3 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM4 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM5 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM6 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM7 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART2 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART3 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USB : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_WWDG : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_ReleaseReset() : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_DisableClock() : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_EnableClock() : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_ForceReset() : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_IsEnabledClock() : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ADC1 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ALL : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SDADC1 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SDADC2 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SDADC3 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI1 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SYSCFG : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM15 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM16 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM17 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM19 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART1 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_ReleaseReset() : stm32f3xx_ll_bus.h
  • LL_COMP_ConfigInputs() : stm32f3xx_ll_comp.h
  • LL_COMP_DeInit() : stm32f3xx_ll_comp.c
  • LL_COMP_DELAY_STARTUP_US : stm32f3xx_ll_comp.h
  • LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32f3xx_ll_comp.h
  • LL_COMP_Disable() : stm32f3xx_ll_comp.h
  • LL_COMP_Enable() : stm32f3xx_ll_comp.h
  • LL_COMP_GetCommonWindowMode() : stm32f3xx_ll_comp.h
  • LL_COMP_GetInputHysteresis() : stm32f3xx_ll_comp.h
  • LL_COMP_GetInputMinus() : stm32f3xx_ll_comp.h
  • LL_COMP_GetInputPlus() : stm32f3xx_ll_comp.h
  • LL_COMP_GetOutputPolarity() : stm32f3xx_ll_comp.h
  • LL_COMP_GetOutputSelection() : stm32f3xx_ll_comp.h
  • LL_COMP_GetPowerMode() : stm32f3xx_ll_comp.h
  • LL_COMP_HYSTERESIS_HIGH : stm32f3xx_ll_comp.h
  • LL_COMP_HYSTERESIS_LOW : stm32f3xx_ll_comp.h
  • LL_COMP_HYSTERESIS_MEDIUM : stm32f3xx_ll_comp.h
  • LL_COMP_HYSTERESIS_NONE : stm32f3xx_ll_comp.h
  • LL_COMP_Init() : stm32f3xx_ll_comp.c
  • LL_COMP_INPUT_MINUS_1_2VREFINT : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_4VREFINT : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_3_4VREFINT : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH1 : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH2 : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC2_CH1 : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO1 : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO2 : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO3 : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO4 : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_VREFINT : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_DAC1_CH1 : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO1 : stm32f3xx_ll_comp.h
  • LL_COMP_IsEnabled() : stm32f3xx_ll_comp.h
  • LL_COMP_IsLocked() : stm32f3xx_ll_comp.h
  • LL_COMP_Lock() : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_HIGH : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_LOW : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_NONE : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM15_BKIN : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM15_BKIN_COMP1 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM16_BKIN : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM16_BKIN_COMP2 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM2_IC4 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM2_OCCLR : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM3_IC1_COMP1 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM3_IC1_COMP2 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM3_OCCLR_COMP1 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM3_OCCLR_COMP2 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM4_IC1 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM4_IC1_COMP2 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM4_OCCLR : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM4_OCCLR_COMP2 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM5_IC4 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM5_IC4_COMP1 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM5_OCCLR : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM5_OCCLR_COMP1 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_INVERTED : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_NONINVERTED : stm32f3xx_ll_comp.h
  • LL_COMP_POWERMODE_HIGHSPEED : stm32f3xx_ll_comp.h
  • LL_COMP_POWERMODE_LOWPOWER : stm32f3xx_ll_comp.h
  • LL_COMP_POWERMODE_MEDIUMSPEED : stm32f3xx_ll_comp.h
  • LL_COMP_POWERMODE_ULTRALOWPOWER : stm32f3xx_ll_comp.h
  • LL_COMP_ReadOutputLevel() : stm32f3xx_ll_comp.h
  • LL_COMP_ReadReg : stm32f3xx_ll_comp.h
  • LL_COMP_SetCommonWindowMode() : stm32f3xx_ll_comp.h
  • LL_COMP_SetInputHysteresis() : stm32f3xx_ll_comp.h
  • LL_COMP_SetInputMinus() : stm32f3xx_ll_comp.h
  • LL_COMP_SetInputPlus() : stm32f3xx_ll_comp.h
  • LL_COMP_SetOutputPolarity() : stm32f3xx_ll_comp.h
  • LL_COMP_SetOutputSelection() : stm32f3xx_ll_comp.h
  • LL_COMP_SetPowerMode() : stm32f3xx_ll_comp.h
  • LL_COMP_StructInit() : stm32f3xx_ll_comp.c
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32f3xx_ll_comp.h
  • LL_COMP_WINDOWMODE_DISABLE : stm32f3xx_ll_comp.h
  • LL_COMP_WriteReg : stm32f3xx_ll_comp.h
  • LL_CPUID_GetConstant() : stm32f3xx_ll_cortex.h
  • LL_CPUID_GetImplementer() : stm32f3xx_ll_cortex.h
  • LL_CPUID_GetParNo() : stm32f3xx_ll_cortex.h
  • LL_CPUID_GetRevision() : stm32f3xx_ll_cortex.h
  • LL_CPUID_GetVariant() : stm32f3xx_ll_cortex.h
  • LL_CRC_DEFAULT_CRC32_POLY : stm32f3xx_ll_crc.h
  • LL_CRC_DEFAULT_CRC_INITVALUE : stm32f3xx_ll_crc.h
  • LL_CRC_DeInit() : stm32f3xx_ll_crc.c
  • LL_CRC_FeedData16() : stm32f3xx_ll_crc.h
  • LL_CRC_FeedData32() : stm32f3xx_ll_crc.h
  • LL_CRC_FeedData8() : stm32f3xx_ll_crc.h
  • LL_CRC_GetInitialData() : stm32f3xx_ll_crc.h
  • LL_CRC_GetInputDataReverseMode() : stm32f3xx_ll_crc.h
  • LL_CRC_GetOutputDataReverseMode() : stm32f3xx_ll_crc.h
  • LL_CRC_GetPolynomialCoef() : stm32f3xx_ll_crc.h
  • LL_CRC_GetPolynomialSize() : stm32f3xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_BYTE : stm32f3xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_HALFWORD : stm32f3xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_NONE : stm32f3xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_WORD : stm32f3xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_BIT : stm32f3xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_NONE : stm32f3xx_ll_crc.h
  • LL_CRC_POLYLENGTH_16B : stm32f3xx_ll_crc.h
  • LL_CRC_POLYLENGTH_32B : stm32f3xx_ll_crc.h
  • LL_CRC_POLYLENGTH_7B : stm32f3xx_ll_crc.h
  • LL_CRC_POLYLENGTH_8B : stm32f3xx_ll_crc.h
  • LL_CRC_Read_IDR() : stm32f3xx_ll_crc.h
  • LL_CRC_ReadData16() : stm32f3xx_ll_crc.h
  • LL_CRC_ReadData32() : stm32f3xx_ll_crc.h
  • LL_CRC_ReadData7() : stm32f3xx_ll_crc.h
  • LL_CRC_ReadData8() : stm32f3xx_ll_crc.h
  • LL_CRC_ReadReg : stm32f3xx_ll_crc.h
  • LL_CRC_ResetCRCCalculationUnit() : stm32f3xx_ll_crc.h
  • LL_CRC_SetInitialData() : stm32f3xx_ll_crc.h
  • LL_CRC_SetInputDataReverseMode() : stm32f3xx_ll_crc.h
  • LL_CRC_SetOutputDataReverseMode() : stm32f3xx_ll_crc.h
  • LL_CRC_SetPolynomialCoef() : stm32f3xx_ll_crc.h
  • LL_CRC_SetPolynomialSize() : stm32f3xx_ll_crc.h
  • LL_CRC_Write_IDR() : stm32f3xx_ll_crc.h
  • LL_CRC_WriteReg : stm32f3xx_ll_crc.h
  • LL_DAC_CHANNEL_1 : stm32f3xx_ll_dac.h
  • LL_DAC_CHANNEL_2 : stm32f3xx_ll_dac.h
  • LL_DAC_ClearFlag_DMAUDR1() : stm32f3xx_ll_dac.h
  • LL_DAC_ClearFlag_DMAUDR2() : stm32f3xx_ll_dac.h
  • LL_DAC_ConvertData12LeftAligned() : stm32f3xx_ll_dac.h
  • LL_DAC_ConvertData12RightAligned() : stm32f3xx_ll_dac.h
  • LL_DAC_ConvertData8RightAligned() : stm32f3xx_ll_dac.h
  • LL_DAC_ConvertDualData12LeftAligned() : stm32f3xx_ll_dac.h
  • LL_DAC_ConvertDualData12RightAligned() : stm32f3xx_ll_dac.h
  • LL_DAC_ConvertDualData8RightAligned() : stm32f3xx_ll_dac.h
  • LL_DAC_DeInit() : stm32f3xx_ll_dac.c
  • LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US : stm32f3xx_ll_dac.h
  • LL_DAC_DELAY_VOLTAGE_SETTLING_US : stm32f3xx_ll_dac.h
  • LL_DAC_Disable() : stm32f3xx_ll_dac.h
  • LL_DAC_DisableDMAReq() : stm32f3xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR1() : stm32f3xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR2() : stm32f3xx_ll_dac.h
  • LL_DAC_DisableTrigger() : stm32f3xx_ll_dac.h
  • LL_DAC_DMA_GetRegAddr() : stm32f3xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED : stm32f3xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED : stm32f3xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED : stm32f3xx_ll_dac.h
  • LL_DAC_Enable() : stm32f3xx_ll_dac.h
  • LL_DAC_EnableDMAReq() : stm32f3xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR1() : stm32f3xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR2() : stm32f3xx_ll_dac.h
  • LL_DAC_EnableTrigger() : stm32f3xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR1 : stm32f3xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR2 : stm32f3xx_ll_dac.h
  • LL_DAC_GetOutputBuffer() : stm32f3xx_ll_dac.h
  • LL_DAC_GetTriggerSource() : stm32f3xx_ll_dac.h
  • LL_DAC_GetWaveAutoGeneration() : stm32f3xx_ll_dac.h
  • LL_DAC_GetWaveNoiseLFSR() : stm32f3xx_ll_dac.h
  • LL_DAC_GetWaveTriangleAmplitude() : stm32f3xx_ll_dac.h
  • LL_DAC_Init() : stm32f3xx_ll_dac.c
  • LL_DAC_IsActiveFlag_DMAUDR1() : stm32f3xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR2() : stm32f3xx_ll_dac.h
  • LL_DAC_IsDMAReqEnabled() : stm32f3xx_ll_dac.h
  • LL_DAC_IsEnabled() : stm32f3xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR1() : stm32f3xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR2() : stm32f3xx_ll_dac.h
  • LL_DAC_IsTriggerEnabled() : stm32f3xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE1 : stm32f3xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE2 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 : stm32f3xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_DISABLE : stm32f3xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_ENABLE : stm32f3xx_ll_dac.h
  • LL_DAC_ReadReg : stm32f3xx_ll_dac.h
  • LL_DAC_RESOLUTION_12B : stm32f3xx_ll_dac.h
  • LL_DAC_RESOLUTION_8B : stm32f3xx_ll_dac.h
  • LL_DAC_RetrieveOutputData() : stm32f3xx_ll_dac.h
  • LL_DAC_SetOutputBuffer() : stm32f3xx_ll_dac.h
  • LL_DAC_SetTriggerSource() : stm32f3xx_ll_dac.h
  • LL_DAC_SetWaveAutoGeneration() : stm32f3xx_ll_dac.h
  • LL_DAC_SetWaveNoiseLFSR() : stm32f3xx_ll_dac.h
  • LL_DAC_SetWaveTriangleAmplitude() : stm32f3xx_ll_dac.h
  • LL_DAC_StructInit() : stm32f3xx_ll_dac.c
  • LL_DAC_TRIANGLE_AMPLITUDE_1 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_1023 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_127 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_15 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_2047 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_255 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_3 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_31 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_4095 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_511 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_63 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_7 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_EXT_EXTI_LINE9 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM18_TRGO : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM2_TRGO : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM3_TRGO : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM4_TRGO : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM5_TRGO : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM6_TRGO : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM7_TRGO : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_SOFTWARE : stm32f3xx_ll_dac.h
  • LL_DAC_TrigSWConversion() : stm32f3xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE : stm32f3xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NONE : stm32f3xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE : stm32f3xx_ll_dac.h
  • LL_DAC_WriteReg : stm32f3xx_ll_dac.h
  • LL_DBGMCU_APB1_GRP1_CAN_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_FreezePeriph() : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_RTC_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM12_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM13_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM14_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM18_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM5_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_UnFreezePeriph() : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_FreezePeriph() : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM19_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_UnFreezePeriph() : stm32f3xx_ll_system.h
  • LL_DBGMCU_DisableDBGSleepMode() : stm32f3xx_ll_system.h
  • LL_DBGMCU_DisableDBGStandbyMode() : stm32f3xx_ll_system.h
  • LL_DBGMCU_DisableDBGStopMode() : stm32f3xx_ll_system.h
  • LL_DBGMCU_EnableDBGSleepMode() : stm32f3xx_ll_system.h
  • LL_DBGMCU_EnableDBGStandbyMode() : stm32f3xx_ll_system.h
  • LL_DBGMCU_EnableDBGStopMode() : stm32f3xx_ll_system.h
  • LL_DBGMCU_GetDeviceID() : stm32f3xx_ll_system.h
  • LL_DBGMCU_GetRevisionID() : stm32f3xx_ll_system.h
  • LL_DBGMCU_GetTracePinAssignment() : stm32f3xx_ll_system.h
  • LL_DBGMCU_SetTracePinAssignment() : stm32f3xx_ll_system.h
  • LL_DBGMCU_TRACE_ASYNCH : stm32f3xx_ll_system.h
  • LL_DBGMCU_TRACE_NONE : stm32f3xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE1 : stm32f3xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE2 : stm32f3xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE4 : stm32f3xx_ll_system.h
  • LL_DMA_CCR_HTIE : stm32f3xx_ll_dma.h
  • LL_DMA_CCR_TCIE : stm32f3xx_ll_dma.h
  • LL_DMA_CCR_TEIE : stm32f3xx_ll_dma.h
  • LL_DMA_CHANNEL_1 : stm32f3xx_ll_dma.h
  • LL_DMA_CHANNEL_2 : stm32f3xx_ll_dma.h
  • LL_DMA_CHANNEL_3 : stm32f3xx_ll_dma.h
  • LL_DMA_CHANNEL_4 : stm32f3xx_ll_dma.h
  • LL_DMA_CHANNEL_5 : stm32f3xx_ll_dma.h
  • LL_DMA_CHANNEL_6 : stm32f3xx_ll_dma.h
  • LL_DMA_CHANNEL_7 : stm32f3xx_ll_dma.h
  • LL_DMA_CHANNEL_ALL : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_GI1() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_GI2() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_GI3() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_GI4() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_GI5() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_GI6() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_GI7() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_HT1() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_HT2() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_HT3() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_HT4() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_HT5() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_HT6() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_HT7() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TC1() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TC2() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TC3() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TC4() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TC5() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TC6() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TC7() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TE1() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TE2() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TE3() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TE4() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TE5() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TE6() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TE7() : stm32f3xx_ll_dma.h
  • LL_DMA_ConfigAddresses() : stm32f3xx_ll_dma.h
  • LL_DMA_ConfigTransfer() : stm32f3xx_ll_dma.h
  • LL_DMA_DeInit() : stm32f3xx_ll_dma.c
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY : stm32f3xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH : stm32f3xx_ll_dma.h
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY : stm32f3xx_ll_dma.h
  • LL_DMA_DisableChannel() : stm32f3xx_ll_dma.h
  • LL_DMA_DisableIT_HT() : stm32f3xx_ll_dma.h
  • LL_DMA_DisableIT_TC() : stm32f3xx_ll_dma.h
  • LL_DMA_DisableIT_TE() : stm32f3xx_ll_dma.h
  • LL_DMA_EnableChannel() : stm32f3xx_ll_dma.h
  • LL_DMA_EnableIT_HT() : stm32f3xx_ll_dma.h
  • LL_DMA_EnableIT_TC() : stm32f3xx_ll_dma.h
  • LL_DMA_EnableIT_TE() : stm32f3xx_ll_dma.h
  • LL_DMA_GetChannelPriorityLevel() : stm32f3xx_ll_dma.h
  • LL_DMA_GetDataLength() : stm32f3xx_ll_dma.h
  • LL_DMA_GetDataTransferDirection() : stm32f3xx_ll_dma.h
  • LL_DMA_GetM2MDstAddress() : stm32f3xx_ll_dma.h
  • LL_DMA_GetM2MSrcAddress() : stm32f3xx_ll_dma.h
  • LL_DMA_GetMemoryAddress() : stm32f3xx_ll_dma.h
  • LL_DMA_GetMemoryIncMode() : stm32f3xx_ll_dma.h
  • LL_DMA_GetMemorySize() : stm32f3xx_ll_dma.h
  • LL_DMA_GetMode() : stm32f3xx_ll_dma.h
  • LL_DMA_GetPeriphAddress() : stm32f3xx_ll_dma.h
  • LL_DMA_GetPeriphIncMode() : stm32f3xx_ll_dma.h
  • LL_DMA_GetPeriphSize() : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CGIF1 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CGIF2 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CGIF3 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CGIF4 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CGIF5 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CGIF6 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CGIF7 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF1 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF2 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF3 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF4 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF5 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF6 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF7 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF1 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF2 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF3 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF4 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF5 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF6 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF7 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF1 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF2 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF3 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF4 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF5 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF6 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF7 : stm32f3xx_ll_dma.h
  • LL_DMA_Init() : stm32f3xx_ll_dma.c
  • LL_DMA_IsActiveFlag_GI1() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI2() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI3() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI4() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI5() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI6() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI7() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT1() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT2() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT3() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT4() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT5() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT6() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT7() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC1() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC2() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC3() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC4() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC5() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC6() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC7() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE1() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE2() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE3() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE4() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE5() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE6() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE7() : stm32f3xx_ll_dma.h
  • LL_DMA_IsEnabledChannel() : stm32f3xx_ll_dma.h
  • LL_DMA_IsEnabledIT_HT() : stm32f3xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TC() : stm32f3xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TE() : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_GIF1 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_GIF2 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_GIF3 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_GIF4 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_GIF5 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_GIF6 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_GIF7 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_HTIF1 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_HTIF2 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_HTIF3 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_HTIF4 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_HTIF5 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_HTIF6 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_HTIF7 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TCIF1 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TCIF2 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TCIF3 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TCIF4 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TCIF5 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TCIF6 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TCIF7 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TEIF1 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TEIF2 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TEIF3 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TEIF4 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TEIF5 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TEIF6 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TEIF7 : stm32f3xx_ll_dma.h
  • LL_DMA_MDATAALIGN_BYTE : stm32f3xx_ll_dma.h
  • LL_DMA_MDATAALIGN_HALFWORD : stm32f3xx_ll_dma.h
  • LL_DMA_MDATAALIGN_WORD : stm32f3xx_ll_dma.h
  • LL_DMA_MEMORY_INCREMENT : stm32f3xx_ll_dma.h
  • LL_DMA_MEMORY_NOINCREMENT : stm32f3xx_ll_dma.h
  • LL_DMA_MODE_CIRCULAR : stm32f3xx_ll_dma.h
  • LL_DMA_MODE_NORMAL : stm32f3xx_ll_dma.h
  • LL_DMA_PDATAALIGN_BYTE : stm32f3xx_ll_dma.h
  • LL_DMA_PDATAALIGN_HALFWORD : stm32f3xx_ll_dma.h
  • LL_DMA_PDATAALIGN_WORD : stm32f3xx_ll_dma.h
  • LL_DMA_PERIPH_INCREMENT : stm32f3xx_ll_dma.h
  • LL_DMA_PERIPH_NOINCREMENT : stm32f3xx_ll_dma.h
  • LL_DMA_PRIORITY_HIGH : stm32f3xx_ll_dma.h
  • LL_DMA_PRIORITY_LOW : stm32f3xx_ll_dma.h
  • LL_DMA_PRIORITY_MEDIUM : stm32f3xx_ll_dma.h
  • LL_DMA_PRIORITY_VERYHIGH : stm32f3xx_ll_dma.h
  • LL_DMA_ReadReg : stm32f3xx_ll_dma.h
  • LL_DMA_SetChannelPriorityLevel() : stm32f3xx_ll_dma.h
  • LL_DMA_SetDataLength() : stm32f3xx_ll_dma.h
  • LL_DMA_SetDataTransferDirection() : stm32f3xx_ll_dma.h
  • LL_DMA_SetM2MDstAddress() : stm32f3xx_ll_dma.h
  • LL_DMA_SetM2MSrcAddress() : stm32f3xx_ll_dma.h
  • LL_DMA_SetMemoryAddress() : stm32f3xx_ll_dma.h
  • LL_DMA_SetMemoryIncMode() : stm32f3xx_ll_dma.h
  • LL_DMA_SetMemorySize() : stm32f3xx_ll_dma.h
  • LL_DMA_SetMode() : stm32f3xx_ll_dma.h
  • LL_DMA_SetPeriphAddress() : stm32f3xx_ll_dma.h
  • LL_DMA_SetPeriphIncMode() : stm32f3xx_ll_dma.h
  • LL_DMA_SetPeriphSize() : stm32f3xx_ll_dma.h
  • LL_DMA_StructInit() : stm32f3xx_ll_dma.c
  • LL_DMA_WriteReg : stm32f3xx_ll_dma.h
  • LL_EXTI_ClearFlag_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_DeInit() : stm32f3xx_ll_exti.c
  • LL_EXTI_DisableEvent_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_DisableIT_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_EnableEvent_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_EnableIT_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_GenerateSWI_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_Init() : stm32f3xx_ll_exti.c
  • LL_EXTI_IsActiveFlag_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_0 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_1 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_10 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_11 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_12 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_13 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_14 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_15 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_16 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_17 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_18 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_19 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_2 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_20 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_21 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_22 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_23 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_24 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_25 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_26 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_27 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_28 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_3 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_4 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_5 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_6 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_7 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_8 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_9 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_ALL : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_ALL_0_31 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_NONE : stm32f3xx_ll_exti.h
  • LL_EXTI_MODE_EVENT : stm32f3xx_ll_exti.h
  • LL_EXTI_MODE_IT : stm32f3xx_ll_exti.h
  • LL_EXTI_MODE_IT_EVENT : stm32f3xx_ll_exti.h
  • LL_EXTI_ReadFlag_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_ReadReg : stm32f3xx_ll_exti.h
  • LL_EXTI_StructInit() : stm32f3xx_ll_exti.c
  • LL_EXTI_TRIGGER_FALLING : stm32f3xx_ll_exti.h
  • LL_EXTI_TRIGGER_NONE : stm32f3xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING : stm32f3xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING_FALLING : stm32f3xx_ll_exti.h
  • LL_EXTI_WriteReg : stm32f3xx_ll_exti.h
  • LL_FLASH_DisablePrefetch() : stm32f3xx_ll_system.h
  • LL_FLASH_EnablePrefetch() : stm32f3xx_ll_system.h
  • LL_FLASH_GetLatency() : stm32f3xx_ll_system.h
  • LL_FLASH_IsPrefetchEnabled() : stm32f3xx_ll_system.h
  • LL_FLASH_LATENCY_0 : stm32f3xx_ll_system.h
  • LL_FLASH_LATENCY_1 : stm32f3xx_ll_system.h
  • LL_FLASH_LATENCY_2 : stm32f3xx_ll_system.h
  • LL_FLASH_SetLatency() : stm32f3xx_ll_system.h
  • LL_GetFlashSize() : stm32f3xx_ll_utils.h
  • LL_GetUID_Word0() : stm32f3xx_ll_utils.h
  • LL_GetUID_Word1() : stm32f3xx_ll_utils.h
  • LL_GetUID_Word2() : stm32f3xx_ll_utils.h
  • LL_GPIO_AF_0 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_1 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_10 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_11 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_12 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_13 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_14 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_15 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_2 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_3 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_4 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_5 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_6 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_7 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_8 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_9 : stm32f3xx_ll_gpio.h
  • LL_GPIO_DeInit() : stm32f3xx_ll_gpio.c
  • LL_GPIO_GetAFPin_0_7() : stm32f3xx_ll_gpio.h
  • LL_GPIO_GetAFPin_8_15() : stm32f3xx_ll_gpio.h
  • LL_GPIO_GetPinMode() : stm32f3xx_ll_gpio.h
  • LL_GPIO_GetPinOutputType() : stm32f3xx_ll_gpio.h
  • LL_GPIO_GetPinPull() : stm32f3xx_ll_gpio.h
  • LL_GPIO_GetPinSpeed() : stm32f3xx_ll_gpio.h
  • LL_GPIO_Init() : stm32f3xx_ll_gpio.c
  • LL_GPIO_IsAnyPinLocked() : stm32f3xx_ll_gpio.h
  • LL_GPIO_IsInputPinSet() : stm32f3xx_ll_gpio.h
  • LL_GPIO_IsOutputPinSet() : stm32f3xx_ll_gpio.h
  • LL_GPIO_IsPinLocked() : stm32f3xx_ll_gpio.h
  • LL_GPIO_LockPin() : stm32f3xx_ll_gpio.h
  • LL_GPIO_MODE_ALTERNATE : stm32f3xx_ll_gpio.h
  • LL_GPIO_MODE_ANALOG : stm32f3xx_ll_gpio.h
  • LL_GPIO_MODE_INPUT : stm32f3xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT : stm32f3xx_ll_gpio.h
  • LL_GPIO_OUTPUT_OPENDRAIN : stm32f3xx_ll_gpio.h
  • LL_GPIO_OUTPUT_PUSHPULL : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_0 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_1 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_10 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_11 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_12 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_13 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_14 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_15 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_2 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_3 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_4 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_5 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_6 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_7 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_8 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_9 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_ALL : stm32f3xx_ll_gpio.h
  • LL_GPIO_PULL_DOWN : stm32f3xx_ll_gpio.h
  • LL_GPIO_PULL_NO : stm32f3xx_ll_gpio.h
  • LL_GPIO_PULL_UP : stm32f3xx_ll_gpio.h
  • LL_GPIO_ReadInputPort() : stm32f3xx_ll_gpio.h
  • LL_GPIO_ReadOutputPort() : stm32f3xx_ll_gpio.h
  • LL_GPIO_ReadReg : stm32f3xx_ll_gpio.h
  • LL_GPIO_ResetOutputPin() : stm32f3xx_ll_gpio.h
  • LL_GPIO_SetAFPin_0_7() : stm32f3xx_ll_gpio.h
  • LL_GPIO_SetAFPin_8_15() : stm32f3xx_ll_gpio.h
  • LL_GPIO_SetOutputPin() : stm32f3xx_ll_gpio.h
  • LL_GPIO_SetPinMode() : stm32f3xx_ll_gpio.h
  • LL_GPIO_SetPinOutputType() : stm32f3xx_ll_gpio.h
  • LL_GPIO_SetPinPull() : stm32f3xx_ll_gpio.h
  • LL_GPIO_SetPinSpeed() : stm32f3xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_HIGH : stm32f3xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_LOW : stm32f3xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_MEDIUM : stm32f3xx_ll_gpio.h
  • LL_GPIO_StructInit() : stm32f3xx_ll_gpio.c
  • LL_GPIO_TogglePin() : stm32f3xx_ll_gpio.h
  • LL_GPIO_WriteOutputPort() : stm32f3xx_ll_gpio.h
  • LL_GPIO_WriteReg : stm32f3xx_ll_gpio.h
  • LL_HANDLER_DisableFault() : stm32f3xx_ll_cortex.h
  • LL_HANDLER_EnableFault() : stm32f3xx_ll_cortex.h
  • LL_HANDLER_FAULT_BUS : stm32f3xx_ll_cortex.h
  • LL_HANDLER_FAULT_MEM : stm32f3xx_ll_cortex.h
  • LL_HANDLER_FAULT_USG : stm32f3xx_ll_cortex.h
  • LL_I2C_ACK : stm32f3xx_ll_i2c.h
  • LL_I2C_AcknowledgeNextData() : stm32f3xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_10BIT : stm32f3xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_7BIT : stm32f3xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_10BIT : stm32f3xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_7BIT : stm32f3xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_DISABLE : stm32f3xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_ENABLE : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearFlag_ADDR() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearFlag_ARLO() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearFlag_BERR() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearFlag_NACK() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearFlag_OVR() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearFlag_STOP() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearFlag_TXE() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_ALERT() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_PECERR() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_TIMEOUT() : stm32f3xx_ll_i2c.h
  • LL_I2C_ConfigFilters() : stm32f3xx_ll_i2c.h
  • LL_I2C_ConfigSMBusTimeout() : stm32f3xx_ll_i2c.h
  • LL_I2C_CR1_ADDRIE : stm32f3xx_ll_i2c.h
  • LL_I2C_CR1_ERRIE : stm32f3xx_ll_i2c.h
  • LL_I2C_CR1_NACKIE : stm32f3xx_ll_i2c.h
  • LL_I2C_CR1_RXIE : stm32f3xx_ll_i2c.h
  • LL_I2C_CR1_STOPIE : stm32f3xx_ll_i2c.h
  • LL_I2C_CR1_TCIE : stm32f3xx_ll_i2c.h
  • LL_I2C_CR1_TXIE : stm32f3xx_ll_i2c.h
  • LL_I2C_DeInit() : stm32f3xx_ll_i2c.c
  • LL_I2C_DIRECTION_READ : stm32f3xx_ll_i2c.h
  • LL_I2C_DIRECTION_WRITE : stm32f3xx_ll_i2c.h
  • LL_I2C_Disable() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableAnalogFilter() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableAuto10BitRead() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableAutoEndMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableClockStretching() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_RX() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_TX() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableGeneralCall() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableIT_ADDR() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableIT_ERR() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableIT_NACK() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableIT_RX() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableIT_STOP() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableIT_TC() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableIT_TX() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress1() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress2() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableReloadMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableSlaveByteControl() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableSMBusAlert() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableSMBusPEC() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableSMBusTimeout() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableWakeUpFromStop() : stm32f3xx_ll_i2c.h
  • LL_I2C_DMA_GetRegAddr() : stm32f3xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_RECEIVE : stm32f3xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_TRANSMIT : stm32f3xx_ll_i2c.h
  • LL_I2C_Enable() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableAnalogFilter() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableAuto10BitRead() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableAutoEndMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableClockStretching() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_RX() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_TX() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableGeneralCall() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableIT_ADDR() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableIT_ERR() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableIT_NACK() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableIT_RX() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableIT_STOP() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableIT_TC() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableIT_TX() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress1() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress2() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableReloadMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableSlaveByteControl() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableSMBusAlert() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableSMBusPEC() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableSMBusPECCompare() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableSMBusTimeout() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableWakeUpFromStop() : stm32f3xx_ll_i2c.h
  • LL_I2C_GENERATE_NOSTARTSTOP : stm32f3xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_READ : stm32f3xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE : stm32f3xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_READ : stm32f3xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE : stm32f3xx_ll_i2c.h
  • LL_I2C_GENERATE_START_READ : stm32f3xx_ll_i2c.h
  • LL_I2C_GENERATE_START_WRITE : stm32f3xx_ll_i2c.h
  • LL_I2C_GENERATE_STOP : stm32f3xx_ll_i2c.h
  • LL_I2C_GenerateStartCondition() : stm32f3xx_ll_i2c.h
  • LL_I2C_GenerateStopCondition() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetAddressMatchCode() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetClockHighPeriod() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetClockLowPeriod() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetDataHoldTime() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetDataSetupTime() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetDigitalFilter() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetMasterAddressingMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetSlaveAddr() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetSMBusPEC() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutA() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutAMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutB() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetTimingPrescaler() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetTransferDirection() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetTransferRequest() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetTransferSize() : stm32f3xx_ll_i2c.h
  • LL_I2C_HandleTransfer() : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_ADDRCF : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_ALERTCF : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_ARLOCF : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_BERRCF : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_NACKCF : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_OVRCF : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_PECCF : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_STOPCF : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_TIMOUTCF : stm32f3xx_ll_i2c.h
  • LL_I2C_Init() : stm32f3xx_ll_i2c.c
  • LL_I2C_IsActiveFlag_ADDR() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_ARLO() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BERR() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BUSY() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_NACK() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_OVR() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_RXNE() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_STOP() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TC() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TCR() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXE() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXIS() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_ALERT() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_PECERR() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_TIMEOUT() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabled() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledAnalogFilter() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledAuto10BitRead() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledAutoEndMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledClockStretching() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_RX() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_TX() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledGeneralCall() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ADDR() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ERR() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_NACK() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_RX() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_STOP() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TC() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TX() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress1() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress2() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledReloadMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledSlaveByteControl() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusAlert() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPEC() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPECCompare() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusTimeout() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledWakeUpFromStop() : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_ADDR : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_ALERT : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_ARLO : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_BERR : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_BUSY : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_NACKF : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_OVR : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_PECERR : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_RXNE : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_STOPF : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_TC : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_TCR : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_TIMEOUT : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_TXE : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_TXIS : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_AUTOEND : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_I2C : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_RELOAD : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE_ARP : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_HOST : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_RELOAD : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SOFTEND : stm32f3xx_ll_i2c.h
  • LL_I2C_NACK : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_10BIT : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_7BIT : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK01 : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK02 : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK03 : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK04 : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK05 : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK06 : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK07 : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_NOMASK : stm32f3xx_ll_i2c.h
  • LL_I2C_ReadReg : stm32f3xx_ll_i2c.h
  • LL_I2C_ReceiveData8() : stm32f3xx_ll_i2c.h
  • LL_I2C_REQUEST_READ : stm32f3xx_ll_i2c.h
  • LL_I2C_REQUEST_WRITE : stm32f3xx_ll_i2c.h
  • LL_I2C_SetDigitalFilter() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetMasterAddressingMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetOwnAddress1() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetOwnAddress2() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetSlaveAddr() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutA() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutAMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutB() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetTiming() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetTransferRequest() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetTransferSize() : stm32f3xx_ll_i2c.h
  • LL_I2C_SMBUS_ALL_TIMEOUT : stm32f3xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA : stm32f3xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW : stm32f3xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH : stm32f3xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTB : stm32f3xx_ll_i2c.h
  • LL_I2C_StructInit() : stm32f3xx_ll_i2c.c
  • LL_I2C_TransmitData8() : stm32f3xx_ll_i2c.h
  • LL_I2C_WriteReg : stm32f3xx_ll_i2c.h
  • LL_I2S_AUDIOFREQ_11K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_16K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_192K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_22K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_32K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_44K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_48K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_8K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_96K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_DEFAULT : stm32f3xx_ll_spi.h
  • LL_I2S_ClearFlag_FRE() : stm32f3xx_ll_spi.h
  • LL_I2S_ClearFlag_OVR() : stm32f3xx_ll_spi.h
  • LL_I2S_ClearFlag_UDR() : stm32f3xx_ll_spi.h
  • LL_I2S_ConfigPrescaler() : stm32f3xx_ll_spi.c
  • LL_I2S_CR2_ERRIE : stm32f3xx_ll_spi.h
  • LL_I2S_CR2_RXNEIE : stm32f3xx_ll_spi.h
  • LL_I2S_CR2_TXEIE : stm32f3xx_ll_spi.h
  • LL_I2S_DATAFORMAT_16B : stm32f3xx_ll_spi.h
  • LL_I2S_DATAFORMAT_16B_EXTENDED : stm32f3xx_ll_spi.h
  • LL_I2S_DATAFORMAT_24B : stm32f3xx_ll_spi.h
  • LL_I2S_DATAFORMAT_32B : stm32f3xx_ll_spi.h
  • LL_I2S_DeInit() : stm32f3xx_ll_spi.c
  • LL_I2S_Disable() : stm32f3xx_ll_spi.h
  • LL_I2S_DisableDMAReq_RX() : stm32f3xx_ll_spi.h
  • LL_I2S_DisableDMAReq_TX() : stm32f3xx_ll_spi.h
  • LL_I2S_DisableIT_ERR() : stm32f3xx_ll_spi.h
  • LL_I2S_DisableIT_RXNE() : stm32f3xx_ll_spi.h
  • LL_I2S_DisableIT_TXE() : stm32f3xx_ll_spi.h
  • LL_I2S_DisableMasterClock() : stm32f3xx_ll_spi.h
  • LL_I2S_Enable() : stm32f3xx_ll_spi.h
  • LL_I2S_EnableDMAReq_RX() : stm32f3xx_ll_spi.h
  • LL_I2S_EnableDMAReq_TX() : stm32f3xx_ll_spi.h
  • LL_I2S_EnableIT_ERR() : stm32f3xx_ll_spi.h
  • LL_I2S_EnableIT_RXNE() : stm32f3xx_ll_spi.h
  • LL_I2S_EnableIT_TXE() : stm32f3xx_ll_spi.h
  • LL_I2S_EnableMasterClock() : stm32f3xx_ll_spi.h
  • LL_I2S_GetClockPolarity() : stm32f3xx_ll_spi.h
  • LL_I2S_GetDataFormat() : stm32f3xx_ll_spi.h
  • LL_I2S_GetPrescalerLinear() : stm32f3xx_ll_spi.h
  • LL_I2S_GetPrescalerParity() : stm32f3xx_ll_spi.h
  • LL_I2S_GetStandard() : stm32f3xx_ll_spi.h
  • LL_I2S_GetTransferMode() : stm32f3xx_ll_spi.h
  • LL_I2S_Init() : stm32f3xx_ll_spi.c
  • LL_I2S_IsActiveFlag_BSY() : stm32f3xx_ll_spi.h
  • LL_I2S_IsActiveFlag_CHSIDE() : stm32f3xx_ll_spi.h
  • LL_I2S_IsActiveFlag_FRE() : stm32f3xx_ll_spi.h
  • LL_I2S_IsActiveFlag_OVR() : stm32f3xx_ll_spi.h
  • LL_I2S_IsActiveFlag_RXNE() : stm32f3xx_ll_spi.h
  • LL_I2S_IsActiveFlag_TXE() : stm32f3xx_ll_spi.h
  • LL_I2S_IsActiveFlag_UDR() : stm32f3xx_ll_spi.h
  • LL_I2S_IsEnabled() : stm32f3xx_ll_spi.h
  • LL_I2S_IsEnabledDMAReq_RX() : stm32f3xx_ll_spi.h
  • LL_I2S_IsEnabledDMAReq_TX() : stm32f3xx_ll_spi.h
  • LL_I2S_IsEnabledIT_ERR() : stm32f3xx_ll_spi.h
  • LL_I2S_IsEnabledIT_RXNE() : stm32f3xx_ll_spi.h
  • LL_I2S_IsEnabledIT_TXE() : stm32f3xx_ll_spi.h
  • LL_I2S_IsEnabledMasterClock() : stm32f3xx_ll_spi.h
  • LL_I2S_MCLK_OUTPUT_DISABLE : stm32f3xx_ll_spi.h
  • LL_I2S_MCLK_OUTPUT_ENABLE : stm32f3xx_ll_spi.h
  • LL_I2S_MODE_MASTER_RX : stm32f3xx_ll_spi.h
  • LL_I2S_MODE_MASTER_TX : stm32f3xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_RX : stm32f3xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_TX : stm32f3xx_ll_spi.h
  • LL_I2S_POLARITY_HIGH : stm32f3xx_ll_spi.h
  • LL_I2S_POLARITY_LOW : stm32f3xx_ll_spi.h
  • LL_I2S_PRESCALER_PARITY_EVEN : stm32f3xx_ll_spi.h
  • LL_I2S_PRESCALER_PARITY_ODD : stm32f3xx_ll_spi.h
  • LL_I2S_ReadReg : stm32f3xx_ll_spi.h
  • LL_I2S_ReceiveData16() : stm32f3xx_ll_spi.h
  • LL_I2S_SetClockPolarity() : stm32f3xx_ll_spi.h
  • LL_I2S_SetDataFormat() : stm32f3xx_ll_spi.h
  • LL_I2S_SetPrescalerLinear() : stm32f3xx_ll_spi.h
  • LL_I2S_SetPrescalerParity() : stm32f3xx_ll_spi.h
  • LL_I2S_SetStandard() : stm32f3xx_ll_spi.h
  • LL_I2S_SetTransferMode() : stm32f3xx_ll_spi.h
  • LL_I2S_SR_BSY : stm32f3xx_ll_spi.h
  • LL_I2S_SR_FRE : stm32f3xx_ll_spi.h
  • LL_I2S_SR_OVR : stm32f3xx_ll_spi.h
  • LL_I2S_SR_RXNE : stm32f3xx_ll_spi.h
  • LL_I2S_SR_TXE : stm32f3xx_ll_spi.h
  • LL_I2S_SR_UDR : stm32f3xx_ll_spi.h
  • LL_I2S_STANDARD_LSB : stm32f3xx_ll_spi.h
  • LL_I2S_STANDARD_MSB : stm32f3xx_ll_spi.h
  • LL_I2S_STANDARD_PCM_LONG : stm32f3xx_ll_spi.h
  • LL_I2S_STANDARD_PCM_SHORT : stm32f3xx_ll_spi.h
  • LL_I2S_STANDARD_PHILIPS : stm32f3xx_ll_spi.h
  • LL_I2S_StructInit() : stm32f3xx_ll_spi.c
  • LL_I2S_TransmitData16() : stm32f3xx_ll_spi.h
  • LL_I2S_WriteReg : stm32f3xx_ll_spi.h
  • LL_Init1msTick() : stm32f3xx_ll_utils.c
  • LL_InitTick() : stm32f3xx_ll_utils.h
  • LL_IWDG_DisableWriteAccess() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_Enable() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_EnableWriteAccess() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_GetPrescaler() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_GetReloadCounter() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_GetWindow() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_PVU() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_RVU() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_WVU() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_IsReady() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_KEY_ENABLE : stm32f3xx_ll_iwdg.h
  • LL_IWDG_KEY_RELOAD : stm32f3xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_DISABLE : stm32f3xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_ENABLE : stm32f3xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_128 : stm32f3xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_16 : stm32f3xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_256 : stm32f3xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_32 : stm32f3xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_4 : stm32f3xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_64 : stm32f3xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_8 : stm32f3xx_ll_iwdg.h
  • LL_IWDG_ReadReg : stm32f3xx_ll_iwdg.h
  • LL_IWDG_ReloadCounter() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_SetPrescaler() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_SetReloadCounter() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_SetWindow() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_SR_PVU : stm32f3xx_ll_iwdg.h
  • LL_IWDG_SR_RVU : stm32f3xx_ll_iwdg.h
  • LL_IWDG_SR_WVU : stm32f3xx_ll_iwdg.h
  • LL_IWDG_WriteReg : stm32f3xx_ll_iwdg.h
  • LL_LPM_DisableEventOnPend() : stm32f3xx_ll_cortex.h
  • LL_LPM_DisableSleepOnExit() : stm32f3xx_ll_cortex.h
  • LL_LPM_EnableDeepSleep() : stm32f3xx_ll_cortex.h
  • LL_LPM_EnableEventOnPend() : stm32f3xx_ll_cortex.h
  • LL_LPM_EnableSleep() : stm32f3xx_ll_cortex.h
  • LL_LPM_EnableSleepOnExit() : stm32f3xx_ll_cortex.h
  • LL_MAX_DELAY : stm32f3xx_ll_utils.h
  • LL_mDelay() : stm32f3xx_ll_utils.c
  • LL_MPU_ACCESS_BUFFERABLE : stm32f3xx_ll_cortex.h
  • LL_MPU_ACCESS_CACHEABLE : stm32f3xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_BUFFERABLE : stm32f3xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_CACHEABLE : stm32f3xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_SHAREABLE : stm32f3xx_ll_cortex.h
  • LL_MPU_ACCESS_SHAREABLE : stm32f3xx_ll_cortex.h
  • LL_MPU_ConfigRegion() : stm32f3xx_ll_cortex.h
  • LL_MPU_CTRL_HARDFAULT_NMI : stm32f3xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF : stm32f3xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE : stm32f3xx_ll_cortex.h
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT : stm32f3xx_ll_cortex.h
  • LL_MPU_Disable() : stm32f3xx_ll_cortex.h
  • LL_MPU_DisableRegion() : stm32f3xx_ll_cortex.h
  • LL_MPU_Enable() : stm32f3xx_ll_cortex.h
  • LL_MPU_EnableRegion() : stm32f3xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_DISABLE : stm32f3xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE : stm32f3xx_ll_cortex.h
  • LL_MPU_IsEnabled() : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_FULL_ACCESS : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NO_ACCESS : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER0 : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER1 : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER2 : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER3 : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER4 : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER5 : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER6 : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER7 : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO_URO : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW_URO : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128B : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1GB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256B : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2GB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32B : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4GB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512B : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64B : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8MB : stm32f3xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL0 : stm32f3xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL1 : stm32f3xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL2 : stm32f3xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL4 : stm32f3xx_ll_cortex.h
  • LL_PLL_ConfigSystemClock_HSE() : stm32f3xx_ll_utils.c
  • LL_PLL_ConfigSystemClock_HSI() : stm32f3xx_ll_utils.c
  • LL_PWR_ClearFlag_SB() : stm32f3xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU() : stm32f3xx_ll_pwr.h
  • LL_PWR_CR_CSBF : stm32f3xx_ll_pwr.h
  • LL_PWR_CR_CWUF : stm32f3xx_ll_pwr.h
  • LL_PWR_CSR_EWUP1 : stm32f3xx_ll_pwr.h
  • LL_PWR_CSR_EWUP2 : stm32f3xx_ll_pwr.h
  • LL_PWR_CSR_EWUP3 : stm32f3xx_ll_pwr.h
  • LL_PWR_CSR_PVDO : stm32f3xx_ll_pwr.h
  • LL_PWR_CSR_SBF : stm32f3xx_ll_pwr.h
  • LL_PWR_CSR_VREFINTRDYF : stm32f3xx_ll_pwr.h
  • LL_PWR_CSR_WUF : stm32f3xx_ll_pwr.h
  • LL_PWR_DeInit() : stm32f3xx_ll_pwr.c
  • LL_PWR_DisableBkUpAccess() : stm32f3xx_ll_pwr.h
  • LL_PWR_DisablePVD() : stm32f3xx_ll_pwr.h
  • LL_PWR_DisableSDADC() : stm32f3xx_ll_pwr.h
  • LL_PWR_DisableWakeUpPin() : stm32f3xx_ll_pwr.h
  • LL_PWR_EnableBkUpAccess() : stm32f3xx_ll_pwr.h
  • LL_PWR_EnablePVD() : stm32f3xx_ll_pwr.h
  • LL_PWR_EnableSDADC() : stm32f3xx_ll_pwr.h
  • LL_PWR_EnableWakeUpPin() : stm32f3xx_ll_pwr.h
  • LL_PWR_GetPowerMode() : stm32f3xx_ll_pwr.h
  • LL_PWR_GetPVDLevel() : stm32f3xx_ll_pwr.h
  • LL_PWR_GetRegulModeDS() : stm32f3xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVDO() : stm32f3xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_SB() : stm32f3xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VREFINTRDY() : stm32f3xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU() : stm32f3xx_ll_pwr.h
  • LL_PWR_IsEnabledBkUpAccess() : stm32f3xx_ll_pwr.h
  • LL_PWR_IsEnabledPVD() : stm32f3xx_ll_pwr.h
  • LL_PWR_IsEnabledSDADC() : stm32f3xx_ll_pwr.h
  • LL_PWR_IsEnabledWakeUpPin() : stm32f3xx_ll_pwr.h
  • LL_PWR_MODE_STANDBY : stm32f3xx_ll_pwr.h
  • LL_PWR_MODE_STOP_LPREGU : stm32f3xx_ll_pwr.h
  • LL_PWR_MODE_STOP_MAINREGU : stm32f3xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_0 : stm32f3xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_1 : stm32f3xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_2 : stm32f3xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_3 : stm32f3xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_4 : stm32f3xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_5 : stm32f3xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_6 : stm32f3xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_7 : stm32f3xx_ll_pwr.h
  • LL_PWR_ReadReg : stm32f3xx_ll_pwr.h
  • LL_PWR_REGU_DSMODE_LOW_POWER : stm32f3xx_ll_pwr.h
  • LL_PWR_REGU_DSMODE_MAIN : stm32f3xx_ll_pwr.h
  • LL_PWR_SDADC_ANALOG1 : stm32f3xx_ll_pwr.h
  • LL_PWR_SDADC_ANALOG2 : stm32f3xx_ll_pwr.h
  • LL_PWR_SDADC_ANALOG3 : stm32f3xx_ll_pwr.h
  • LL_PWR_SetPowerMode() : stm32f3xx_ll_pwr.h
  • LL_PWR_SetPVDLevel() : stm32f3xx_ll_pwr.h
  • LL_PWR_SetRegulModeDS() : stm32f3xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN1 : stm32f3xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN2 : stm32f3xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN3 : stm32f3xx_ll_pwr.h
  • LL_PWR_WriteReg : stm32f3xx_ll_pwr.h
  • LL_RCC_ADC_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 : stm32f3xx_ll_rcc.h
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 : stm32f3xx_ll_rcc.h
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB1_DIV_1 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB1_DIV_16 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB1_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB1_DIV_4 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB1_DIV_8 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB2_DIV_1 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB2_DIV_16 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB2_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB2_DIV_4 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB2_DIV_8 : stm32f3xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE_HSI_DIV244 : stm32f3xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE_LSE : stm32f3xx_ll_rcc.h
  • LL_RCC_CFGR_MCOF : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_CSSC : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_CSSF : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_HSERDYC : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_HSERDYF : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_HSERDYIE : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_HSIRDYC : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_HSIRDYF : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_HSIRDYIE : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_LSERDYC : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_LSERDYF : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_LSERDYIE : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_LSIRDYC : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_LSIRDYF : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_LSIRDYIE : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_PLLRDYC : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_PLLRDYF : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_PLLRDYIE : stm32f3xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSECSS() : stm32f3xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_ClearResetFlags() : stm32f3xx_ll_rcc.h
  • LL_RCC_ConfigMCO() : stm32f3xx_ll_rcc.h
  • LL_RCC_CSR_IWDGRSTF : stm32f3xx_ll_rcc.h
  • LL_RCC_CSR_LPWRRSTF : stm32f3xx_ll_rcc.h
  • LL_RCC_CSR_OBLRSTF : stm32f3xx_ll_rcc.h
  • LL_RCC_CSR_PINRSTF : stm32f3xx_ll_rcc.h
  • LL_RCC_CSR_PORRSTF : stm32f3xx_ll_rcc.h
  • LL_RCC_CSR_SFTRSTF : stm32f3xx_ll_rcc.h
  • LL_RCC_CSR_V18PWRRSTF : stm32f3xx_ll_rcc.h
  • LL_RCC_CSR_WWDGRSTF : stm32f3xx_ll_rcc.h
  • LL_RCC_DeInit() : stm32f3xx_ll_rcc.c
  • LL_RCC_DisableIT_HSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_DisableIT_HSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_DisableIT_LSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_DisableIT_LSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_DisableIT_PLLRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_DisableRTC() : stm32f3xx_ll_rcc.h
  • LL_RCC_EnableIT_HSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_EnableIT_HSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_EnableIT_LSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_EnableIT_LSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_EnableIT_PLLRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_EnableRTC() : stm32f3xx_ll_rcc.h
  • LL_RCC_ForceBackupDomainReset() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetADCClockFreq() : stm32f3xx_ll_rcc.c
  • LL_RCC_GetADCClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetAHBPrescaler() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetAPB1Prescaler() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetAPB2Prescaler() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetCECClockFreq() : stm32f3xx_ll_rcc.c
  • LL_RCC_GetCECClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetHRTIMClockFreq() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetI2CClockFreq() : stm32f3xx_ll_rcc.c
  • LL_RCC_GetI2CClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetRTCClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetSDADCClockFreq() : stm32f3xx_ll_rcc.c
  • LL_RCC_GetSDADCClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetSysClkSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetSystemClocksFreq() : stm32f3xx_ll_rcc.c
  • LL_RCC_GetUSARTClockFreq() : stm32f3xx_ll_rcc.c
  • LL_RCC_GetUSARTClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetUSBClockFreq() : stm32f3xx_ll_rcc.c
  • LL_RCC_GetUSBClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSE_Disable() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSE_DisableBypass() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSE_DisableCSS() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSE_Enable() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSE_EnableBypass() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSE_EnableCSS() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSE_IsReady() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSI_Disable() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSI_Enable() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibration() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibTrimming() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSI_IsReady() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSI_SetCalibTrimming() : stm32f3xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_HSI : stm32f3xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK : stm32f3xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_HSI : stm32f3xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_SYSCLK : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSECSS() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_IWDGRST() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LPWRRST() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_OBLRST() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PINRST() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PORRST() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_SFTRST() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_V18PWRRST() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_WWDGRST() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsEnabledRTC() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSE_Disable() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSE_DisableBypass() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSE_Enable() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSE_EnableBypass() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSE_GetDriveCapability() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSE_IsReady() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSE_SetDriveCapability() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_HIGH : stm32f3xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_LOW : stm32f3xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMHIGH : stm32f3xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMLOW : stm32f3xx_ll_rcc.h
  • LL_RCC_LSI_Disable() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSI_Enable() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSI_IsReady() : stm32f3xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_1 : stm32f3xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSE : stm32f3xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI : stm32f3xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSE : stm32f3xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSI : stm32f3xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_NOCLOCK : stm32f3xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_SYSCLK : stm32f3xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NA : stm32f3xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NO : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_SYS() : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_Disable() : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_Enable() : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_GetMainSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_GetMultiplicator() : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_GetPrediv() : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_IsReady() : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_10 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_11 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_12 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_13 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_14 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_15 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_16 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_3 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_4 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_5 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_6 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_7 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_8 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_9 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_1 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_10 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_11 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_12 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_13 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_14 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_15 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_16 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_3 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_4 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_5 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_6 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_7 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_8 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_9 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSI_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_1 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_10 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_11 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_12 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_13 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_14 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_15 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_16 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_3 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_4 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_5 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_6 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_7 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_8 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_9 : stm32f3xx_ll_rcc.h
  • LL_RCC_ReadReg : stm32f3xx_ll_rcc.h
  • LL_RCC_ReleaseBackupDomainReset() : stm32f3xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32 : stm32f3xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSE : stm32f3xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSI : stm32f3xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_NONE : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_1 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_10 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_12 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_14 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_16 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_20 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_24 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_28 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_32 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_36 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_4 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_40 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_44 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_48 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_6 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_8 : stm32f3xx_ll_rcc.h
  • LL_RCC_SetADCClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetAHBPrescaler() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetAPB1Prescaler() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetAPB2Prescaler() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetCECClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetI2CClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetRTCClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetSDADCClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetSysClkSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetUSARTClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetUSBClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSE : stm32f3xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSI : stm32f3xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_PLL : stm32f3xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE : stm32f3xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI : stm32f3xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_1 : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_128 : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_16 : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_256 : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_4 : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_512 : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_64 : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_8 : stm32f3xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_HSI : stm32f3xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_LSE : stm32f3xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_PCLK2 : stm32f3xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_SYSCLK : stm32f3xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_HSI : stm32f3xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_LSE : stm32f3xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_PCLK1 : stm32f3xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_SYSCLK : stm32f3xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_HSI : stm32f3xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_LSE : stm32f3xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_PCLK1 : stm32f3xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_SYSCLK : stm32f3xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL : stm32f3xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 : stm32f3xx_ll_rcc.h
  • LL_RCC_WriteReg : stm32f3xx_ll_rcc.h
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN : stm32f3xx_ll_rtc.h
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL : stm32f3xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMA : stm32f3xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMB : stm32f3xx_ll_rtc.h
  • LL_RTC_ALARMOUT_DISABLE : stm32f3xx_ll_rtc.h
  • LL_RTC_ALARMOUT_WAKEUP : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_ConfigTime() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_DATE : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_Disable() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_DisableWeekday() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_Enable() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_EnableWeekday() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetMask() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetMinute() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecondMask() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetTime() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetTimeFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetWeekDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_Init() : stm32f3xx_ll_rtc.c
  • LL_RTC_ALMA_MASK_ALL : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_DATEWEEKDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_HOURS : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_MINUTES : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_NONE : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_SECONDS : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_SetDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_SetHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_SetMask() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_SetMinute() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_SetSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecondMask() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_SetTimeFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_SetWeekDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_StructInit() : stm32f3xx_ll_rtc.c
  • LL_RTC_ALMA_TIME_FORMAT_AM : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_PM : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_ConfigTime() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_DATE : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_Disable() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_DisableWeekday() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_Enable() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_EnableWeekday() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetMask() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetMinute() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecondMask() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetTime() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetTimeFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetWeekDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_Init() : stm32f3xx_ll_rtc.c
  • LL_RTC_ALMB_MASK_ALL : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_DATEWEEKDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_HOURS : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_MINUTES : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_NONE : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_SECONDS : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_SetDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_SetHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_SetMask() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_SetMinute() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_SetSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecondMask() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_SetTimeFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_SetWeekDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_StructInit() : stm32f3xx_ll_rtc.c
  • LL_RTC_ALMB_TIME_FORMAT_AM : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_PM : stm32f3xx_ll_rtc.h
  • LL_RTC_BAK_GetRegister() : stm32f3xx_ll_rtc.h
  • LL_RTC_BAK_SetRegister() : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR0 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR1 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR10 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR11 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR12 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR13 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR14 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR15 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR16 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR17 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR18 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR19 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR2 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR20 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR21 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR22 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR23 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR24 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR25 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR26 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR27 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR28 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR29 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR3 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR30 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR31 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR4 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR5 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR6 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR7 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR8 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR9 : stm32f3xx_ll_rtc.h
  • LL_RTC_CAL_GetMinus() : stm32f3xx_ll_rtc.h
  • LL_RTC_CAL_GetOutputFreq() : stm32f3xx_ll_rtc.h
  • LL_RTC_CAL_GetPeriod() : stm32f3xx_ll_rtc.h
  • LL_RTC_CAL_IsPulseInserted() : stm32f3xx_ll_rtc.h
  • LL_RTC_CAL_SetMinus() : stm32f3xx_ll_rtc.h
  • LL_RTC_CAL_SetOutputFreq() : stm32f3xx_ll_rtc.h
  • LL_RTC_CAL_SetPeriod() : stm32f3xx_ll_rtc.h
  • LL_RTC_CAL_SetPulse() : stm32f3xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_NONE : stm32f3xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_SET : stm32f3xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_1HZ : stm32f3xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_512HZ : stm32f3xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_NONE : stm32f3xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_16SEC : stm32f3xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_32SEC : stm32f3xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_8SEC : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRA() : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRB() : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_RS() : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP1() : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP2() : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP3() : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_TS() : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_TSOV() : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_WUT() : stm32f3xx_ll_rtc.h
  • LL_RTC_CR_ALRAIE : stm32f3xx_ll_rtc.h
  • LL_RTC_CR_ALRBIE : stm32f3xx_ll_rtc.h
  • LL_RTC_CR_TSIE : stm32f3xx_ll_rtc.h
  • LL_RTC_CR_WUTIE : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_Config() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_Get() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_GetDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_GetMonth() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_GetWeekDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_GetYear() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_Init() : stm32f3xx_ll_rtc.c
  • LL_RTC_DATE_SetDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_SetMonth() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_SetWeekDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_SetYear() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_StructInit() : stm32f3xx_ll_rtc.c
  • LL_RTC_DeInit() : stm32f3xx_ll_rtc.c
  • LL_RTC_DisableInitMode() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRA() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRB() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisableIT_TS() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisableIT_WUT() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisablePushPullMode() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisableRefClock() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisableShadowRegBypass() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisableWriteProtection() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableInitMode() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRA() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRB() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableIT_TS() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableIT_WUT() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnablePushPullMode() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableRefClock() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableShadowRegBypass() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableWriteProtection() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnterInitMode() : stm32f3xx_ll_rtc.c
  • LL_RTC_ExitInitMode() : stm32f3xx_ll_rtc.c
  • LL_RTC_FORMAT_BCD : stm32f3xx_ll_rtc.h
  • LL_RTC_FORMAT_BIN : stm32f3xx_ll_rtc.h
  • LL_RTC_GetAlarmOutEvent() : stm32f3xx_ll_rtc.h
  • LL_RTC_GetAlarmOutputType() : stm32f3xx_ll_rtc.h
  • LL_RTC_GetAsynchPrescaler() : stm32f3xx_ll_rtc.h
  • LL_RTC_GetHourFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_GetOutputPolarity() : stm32f3xx_ll_rtc.h
  • LL_RTC_GetSynchPrescaler() : stm32f3xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_24HOUR : stm32f3xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_AMPM : stm32f3xx_ll_rtc.h
  • LL_RTC_Init() : stm32f3xx_ll_rtc.c
  • LL_RTC_IsActiveFlag_ALRA() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAW() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRB() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBW() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INIT() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INITS() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RECALP() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RS() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_SHP() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TS() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOV() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUT() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTW() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRA() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRB() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TS() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_WUT() : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_ALRAF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_ALRAWF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_ALRBF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_ALRBWF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_INITF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_INITS : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_RECALPF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_RSF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_SHPF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_TAMP1F : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_TAMP2F : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_TAMP3F : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_TSF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_TSOVF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_WUTF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_WUTWF : stm32f3xx_ll_rtc.h
  • LL_RTC_IsShadowRegBypassEnabled() : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_APRIL : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_AUGUST : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_DECEMBER : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_FEBRUARY : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_JANUARY : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_JULY : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_JUNE : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_MARCH : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_MAY : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_NOVEMBER : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_OCTOBER : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_SEPTEMBER : stm32f3xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH : stm32f3xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW : stm32f3xx_ll_rtc.h
  • LL_RTC_PIN_PC13 : stm32f3xx_ll_rtc.h
  • LL_RTC_PIN_PC14 : stm32f3xx_ll_rtc.h
  • LL_RTC_PIN_PC15 : stm32f3xx_ll_rtc.h
  • LL_RTC_ReadReg : stm32f3xx_ll_rtc.h
  • LL_RTC_ResetOutputPin() : stm32f3xx_ll_rtc.h
  • LL_RTC_SetAlarmOutEvent() : stm32f3xx_ll_rtc.h
  • LL_RTC_SetAlarmOutputType() : stm32f3xx_ll_rtc.h
  • LL_RTC_SetAsynchPrescaler() : stm32f3xx_ll_rtc.h
  • LL_RTC_SetHourFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_SetOutputPin() : stm32f3xx_ll_rtc.h
  • LL_RTC_SetOutputPolarity() : stm32f3xx_ll_rtc.h
  • LL_RTC_SetSynchPrescaler() : stm32f3xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_ADVANCE : stm32f3xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_DELAY : stm32f3xx_ll_rtc.h
  • LL_RTC_StructInit() : stm32f3xx_ll_rtc.c
  • LL_RTC_TAFCR_TAMPIE : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_1 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_2 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_3 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_Disable() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableActiveLevel() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_DisablePullUp() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_1RTCCLK : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_2RTCCLK : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_4RTCCLK : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_8RTCCLK : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_Enable() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableActiveLevel() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_EnablePullUp() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_2SAMPLE : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_4SAMPLE : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_8SAMPLE : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_DISABLE : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_GetFilterCount() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_GetPrecharge() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_GetSamplingFreq() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER1 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER2 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER3 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER1 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER2 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER3 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_256 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_512 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SetFilterCount() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SetPrecharge() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SetSamplingFreq() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_Config() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_DecHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_DisableDayLightStore() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_EnableDayLightStore() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_AM_OR_24 : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_PM : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_Get() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_GetFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_GetHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_GetMinute() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_GetSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_GetSubSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_IncHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_Init() : stm32f3xx_ll_rtc.c
  • LL_RTC_TIME_IsDayLightStoreEnabled() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_SetFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_SetHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_SetMinute() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_SetSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_StructInit() : stm32f3xx_ll_rtc.c
  • LL_RTC_TIME_Synchronize() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_FALLING : stm32f3xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_RISING : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_Disable() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_DisableOnTamper() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_Enable() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_EnableOnTamper() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetActiveEdge() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetDate() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetMinute() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetMonth() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetSubSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetTime() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetTimeFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetWeekDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_SetActiveEdge() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_AM : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_PM : stm32f3xx_ll_rtc.h
  • LL_RTC_WaitForSynchro() : stm32f3xx_ll_rtc.c
  • LL_RTC_WAKEUP_Disable() : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUP_Enable() : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetAutoReload() : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetClock() : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUP_IsEnabled() : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetAutoReload() : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetClock() : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_16 : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_2 : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_4 : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_8 : stm32f3xx_ll_rtc.h
  • LL_RTC_WEEKDAY_FRIDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_WEEKDAY_MONDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SATURDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SUNDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_WEEKDAY_THURSDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_WEEKDAY_TUESDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_WEEKDAY_WEDNESDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_WriteReg : stm32f3xx_ll_rtc.h
  • LL_SetSystemCoreClock() : stm32f3xx_ll_utils.c
  • LL_SPI_BAUDRATEPRESCALER_DIV128 : stm32f3xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV16 : stm32f3xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV2 : stm32f3xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV256 : stm32f3xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV32 : stm32f3xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV4 : stm32f3xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV64 : stm32f3xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV8 : stm32f3xx_ll_spi.h
  • LL_SPI_ClearFlag_CRCERR() : stm32f3xx_ll_spi.h
  • LL_SPI_ClearFlag_FRE() : stm32f3xx_ll_spi.h
  • LL_SPI_ClearFlag_MODF() : stm32f3xx_ll_spi.h
  • LL_SPI_ClearFlag_OVR() : stm32f3xx_ll_spi.h
  • LL_SPI_CR2_ERRIE : stm32f3xx_ll_spi.h
  • LL_SPI_CR2_RXNEIE : stm32f3xx_ll_spi.h
  • LL_SPI_CR2_TXEIE : stm32f3xx_ll_spi.h
  • LL_SPI_CRC_16BIT : stm32f3xx_ll_spi.h
  • LL_SPI_CRC_8BIT : stm32f3xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_DISABLE : stm32f3xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_ENABLE : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_10BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_11BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_12BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_13BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_14BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_15BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_16BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_4BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_5BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_6BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_7BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_8BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_9BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DeInit() : stm32f3xx_ll_spi.c
  • LL_SPI_Disable() : stm32f3xx_ll_spi.h
  • LL_SPI_DisableCRC() : stm32f3xx_ll_spi.h
  • LL_SPI_DisableDMAReq_RX() : stm32f3xx_ll_spi.h
  • LL_SPI_DisableDMAReq_TX() : stm32f3xx_ll_spi.h
  • LL_SPI_DisableIT_ERR() : stm32f3xx_ll_spi.h
  • LL_SPI_DisableIT_RXNE() : stm32f3xx_ll_spi.h
  • LL_SPI_DisableIT_TXE() : stm32f3xx_ll_spi.h
  • LL_SPI_DisableNSSPulseMgt() : stm32f3xx_ll_spi.h
  • LL_SPI_DMA_GetRegAddr() : stm32f3xx_ll_spi.h
  • LL_SPI_DMA_PARITY_EVEN : stm32f3xx_ll_spi.h
  • LL_SPI_DMA_PARITY_ODD : stm32f3xx_ll_spi.h
  • LL_SPI_Enable() : stm32f3xx_ll_spi.h
  • LL_SPI_EnableCRC() : stm32f3xx_ll_spi.h
  • LL_SPI_EnableDMAReq_RX() : stm32f3xx_ll_spi.h
  • LL_SPI_EnableDMAReq_TX() : stm32f3xx_ll_spi.h
  • LL_SPI_EnableIT_ERR() : stm32f3xx_ll_spi.h
  • LL_SPI_EnableIT_RXNE() : stm32f3xx_ll_spi.h
  • LL_SPI_EnableIT_TXE() : stm32f3xx_ll_spi.h
  • LL_SPI_EnableNSSPulseMgt() : stm32f3xx_ll_spi.h
  • LL_SPI_FULL_DUPLEX : stm32f3xx_ll_spi.h
  • LL_SPI_GetBaudRatePrescaler() : stm32f3xx_ll_spi.h
  • LL_SPI_GetClockPhase() : stm32f3xx_ll_spi.h
  • LL_SPI_GetClockPolarity() : stm32f3xx_ll_spi.h
  • LL_SPI_GetCRCPolynomial() : stm32f3xx_ll_spi.h
  • LL_SPI_GetCRCWidth() : stm32f3xx_ll_spi.h
  • LL_SPI_GetDataWidth() : stm32f3xx_ll_spi.h
  • LL_SPI_GetDMAParity_RX() : stm32f3xx_ll_spi.h
  • LL_SPI_GetDMAParity_TX() : stm32f3xx_ll_spi.h
  • LL_SPI_GetMode() : stm32f3xx_ll_spi.h
  • LL_SPI_GetNSSMode() : stm32f3xx_ll_spi.h
  • LL_SPI_GetRxCRC() : stm32f3xx_ll_spi.h
  • LL_SPI_GetRxFIFOLevel() : stm32f3xx_ll_spi.h
  • LL_SPI_GetRxFIFOThreshold() : stm32f3xx_ll_spi.h
  • LL_SPI_GetStandard() : stm32f3xx_ll_spi.h
  • LL_SPI_GetTransferBitOrder() : stm32f3xx_ll_spi.h
  • LL_SPI_GetTransferDirection() : stm32f3xx_ll_spi.h
  • LL_SPI_GetTxCRC() : stm32f3xx_ll_spi.h
  • LL_SPI_GetTxFIFOLevel() : stm32f3xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_RX : stm32f3xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_TX : stm32f3xx_ll_spi.h
  • LL_SPI_Init() : stm32f3xx_ll_spi.c
  • LL_SPI_IsActiveFlag_BSY() : stm32f3xx_ll_spi.h
  • LL_SPI_IsActiveFlag_CRCERR() : stm32f3xx_ll_spi.h
  • LL_SPI_IsActiveFlag_FRE() : stm32f3xx_ll_spi.h
  • LL_SPI_IsActiveFlag_MODF() : stm32f3xx_ll_spi.h
  • LL_SPI_IsActiveFlag_OVR() : stm32f3xx_ll_spi.h
  • LL_SPI_IsActiveFlag_RXNE() : stm32f3xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXE() : stm32f3xx_ll_spi.h
  • LL_SPI_IsEnabled() : stm32f3xx_ll_spi.h
  • LL_SPI_IsEnabledCRC() : stm32f3xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_RX() : stm32f3xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_TX() : stm32f3xx_ll_spi.h
  • LL_SPI_IsEnabledIT_ERR() : stm32f3xx_ll_spi.h
  • LL_SPI_IsEnabledIT_RXNE() : stm32f3xx_ll_spi.h
  • LL_SPI_IsEnabledIT_TXE() : stm32f3xx_ll_spi.h
  • LL_SPI_IsEnabledNSSPulse() : stm32f3xx_ll_spi.h
  • LL_SPI_LSB_FIRST : stm32f3xx_ll_spi.h
  • LL_SPI_MODE_MASTER : stm32f3xx_ll_spi.h
  • LL_SPI_MODE_SLAVE : stm32f3xx_ll_spi.h
  • LL_SPI_MSB_FIRST : stm32f3xx_ll_spi.h
  • LL_SPI_NSS_HARD_INPUT : stm32f3xx_ll_spi.h
  • LL_SPI_NSS_HARD_OUTPUT : stm32f3xx_ll_spi.h
  • LL_SPI_NSS_SOFT : stm32f3xx_ll_spi.h
  • LL_SPI_PHASE_1EDGE : stm32f3xx_ll_spi.h
  • LL_SPI_PHASE_2EDGE : stm32f3xx_ll_spi.h
  • LL_SPI_POLARITY_HIGH : stm32f3xx_ll_spi.h
  • LL_SPI_POLARITY_LOW : stm32f3xx_ll_spi.h
  • LL_SPI_PROTOCOL_MOTOROLA : stm32f3xx_ll_spi.h
  • LL_SPI_PROTOCOL_TI : stm32f3xx_ll_spi.h
  • LL_SPI_ReadReg : stm32f3xx_ll_spi.h
  • LL_SPI_ReceiveData16() : stm32f3xx_ll_spi.h
  • LL_SPI_ReceiveData8() : stm32f3xx_ll_spi.h
  • LL_SPI_RX_FIFO_EMPTY : stm32f3xx_ll_spi.h
  • LL_SPI_RX_FIFO_FULL : stm32f3xx_ll_spi.h
  • LL_SPI_RX_FIFO_HALF_FULL : stm32f3xx_ll_spi.h
  • LL_SPI_RX_FIFO_QUARTER_FULL : stm32f3xx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_HALF : stm32f3xx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_QUARTER : stm32f3xx_ll_spi.h
  • LL_SPI_SetBaudRatePrescaler() : stm32f3xx_ll_spi.h
  • LL_SPI_SetClockPhase() : stm32f3xx_ll_spi.h
  • LL_SPI_SetClockPolarity() : stm32f3xx_ll_spi.h
  • LL_SPI_SetCRCNext() : stm32f3xx_ll_spi.h
  • LL_SPI_SetCRCPolynomial() : stm32f3xx_ll_spi.h
  • LL_SPI_SetCRCWidth() : stm32f3xx_ll_spi.h
  • LL_SPI_SetDataWidth() : stm32f3xx_ll_spi.h
  • LL_SPI_SetDMAParity_RX() : stm32f3xx_ll_spi.h
  • LL_SPI_SetDMAParity_TX() : stm32f3xx_ll_spi.h
  • LL_SPI_SetMode() : stm32f3xx_ll_spi.h
  • LL_SPI_SetNSSMode() : stm32f3xx_ll_spi.h
  • LL_SPI_SetRxFIFOThreshold() : stm32f3xx_ll_spi.h
  • LL_SPI_SetStandard() : stm32f3xx_ll_spi.h
  • LL_SPI_SetTransferBitOrder() : stm32f3xx_ll_spi.h
  • LL_SPI_SetTransferDirection() : stm32f3xx_ll_spi.h
  • LL_SPI_SIMPLEX_RX : stm32f3xx_ll_spi.h
  • LL_SPI_SR_BSY : stm32f3xx_ll_spi.h
  • LL_SPI_SR_CRCERR : stm32f3xx_ll_spi.h
  • LL_SPI_SR_FRE : stm32f3xx_ll_spi.h
  • LL_SPI_SR_MODF : stm32f3xx_ll_spi.h
  • LL_SPI_SR_OVR : stm32f3xx_ll_spi.h
  • LL_SPI_SR_RXNE : stm32f3xx_ll_spi.h
  • LL_SPI_SR_TXE : stm32f3xx_ll_spi.h
  • LL_SPI_StructInit() : stm32f3xx_ll_spi.c
  • LL_SPI_TransmitData16() : stm32f3xx_ll_spi.h
  • LL_SPI_TransmitData8() : stm32f3xx_ll_spi.h
  • LL_SPI_TX_FIFO_EMPTY : stm32f3xx_ll_spi.h
  • LL_SPI_TX_FIFO_FULL : stm32f3xx_ll_spi.h
  • LL_SPI_TX_FIFO_HALF_FULL : stm32f3xx_ll_spi.h
  • LL_SPI_TX_FIFO_QUARTER_FULL : stm32f3xx_ll_spi.h
  • LL_SPI_WriteReg : stm32f3xx_ll_spi.h
  • LL_SYSCFG_ClearFlag_SP() : stm32f3xx_ll_system.h
  • LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3 : stm32f3xx_ll_system.h
  • LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3 : stm32f3xx_ll_system.h
  • LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 : stm32f3xx_ll_system.h
  • LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 : stm32f3xx_ll_system.h
  • LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 : stm32f3xx_ll_system.h
  • LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 : stm32f3xx_ll_system.h
  • LL_SYSCFG_DisableFastModePlus() : stm32f3xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_DZC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IDC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IOC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IXC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_OFC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_UFC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_DisableVBATMonitoring() : stm32f3xx_ll_system.h
  • LL_SYSCFG_EnableFastModePlus() : stm32f3xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_DZC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IDC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IOC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IXC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_OFC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_UFC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_EnableVBATMonitoring() : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE0 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE1 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE10 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE11 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE12 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE13 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE14 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE15 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE2 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE3 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE4 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE5 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE6 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE7 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE8 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE9 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTA : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTB : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTC : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTD : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTE : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTF : stm32f3xx_ll_system.h
  • LL_SYSCFG_GetEXTISource() : stm32f3xx_ll_system.h
  • LL_SYSCFG_GetRemapMemory() : stm32f3xx_ll_system.h
  • LL_SYSCFG_GetTIMBreakInputs() : stm32f3xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 : stm32f3xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 : stm32f3xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6 : stm32f3xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7 : stm32f3xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 : stm32f3xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 : stm32f3xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_SP() : stm32f3xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_DZC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IDC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IOC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IXC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_OFC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_UFC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_REMAP_FLASH : stm32f3xx_ll_system.h
  • LL_SYSCFG_REMAP_SRAM : stm32f3xx_ll_system.h
  • LL_SYSCFG_REMAP_SYSTEMFLASH : stm32f3xx_ll_system.h
  • LL_SYSCFG_SetEXTISource() : stm32f3xx_ll_system.h
  • LL_SYSCFG_SetRemapDMA_DAC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_SetRemapDMA_TIM() : stm32f3xx_ll_system.h
  • LL_SYSCFG_SetRemapMemory() : stm32f3xx_ll_system.h
  • LL_SYSCFG_SetTIMBreakInputs() : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM16_RMP_DMA1_CH3 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM16_RMP_DMA1_CH6 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM17_RMP_DMA1_CH1 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM17_RMP_DMA1_CH7 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM18_RMP_DMA1_CH5 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM18_RMP_DMA2_CH5 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM6_RMP_DMA1_CH3 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM6_RMP_DMA2_CH3 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM7_RMP_DMA1_CH4 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM7_RMP_DMA2_CH4 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_LOCKUP : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_PVD : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM_PARITY : stm32f3xx_ll_system.h
  • LL_SYSTICK_CLKSOURCE_HCLK : stm32f3xx_ll_cortex.h
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32f3xx_ll_cortex.h
  • LL_SYSTICK_DisableIT() : stm32f3xx_ll_cortex.h
  • LL_SYSTICK_EnableIT() : stm32f3xx_ll_cortex.h
  • LL_SYSTICK_GetClkSource() : stm32f3xx_ll_cortex.h
  • LL_SYSTICK_IsActiveCounterFlag() : stm32f3xx_ll_cortex.h
  • LL_SYSTICK_IsEnabledIT() : stm32f3xx_ll_cortex.h
  • LL_SYSTICK_SetClkSource() : stm32f3xx_ll_cortex.h
  • LL_TIM_ACTIVEINPUT_DIRECTTI : stm32f3xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_INDIRECTTI : stm32f3xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_TRC : stm32f3xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_DISABLE : stm32f3xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_ENABLE : stm32f3xx_ll_tim.h
  • LL_TIM_BDTR_Init() : stm32f3xx_ll_tim.c
  • LL_TIM_BDTR_StructInit() : stm32f3xx_ll_tim.c
  • LL_TIM_BREAK_DISABLE : stm32f3xx_ll_tim.h
  • LL_TIM_BREAK_ENABLE : stm32f3xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_HIGH : stm32f3xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_LOW : stm32f3xx_ll_tim.h
  • LL_TIM_CC_DisableChannel() : stm32f3xx_ll_tim.h
  • LL_TIM_CC_DisablePreload() : stm32f3xx_ll_tim.h
  • LL_TIM_CC_EnableChannel() : stm32f3xx_ll_tim.h
  • LL_TIM_CC_EnablePreload() : stm32f3xx_ll_tim.h
  • LL_TIM_CC_GetDMAReqTrigger() : stm32f3xx_ll_tim.h
  • LL_TIM_CC_IsEnabledChannel() : stm32f3xx_ll_tim.h
  • LL_TIM_CC_SetDMAReqTrigger() : stm32f3xx_ll_tim.h
  • LL_TIM_CC_SetLockLevel() : stm32f3xx_ll_tim.h
  • LL_TIM_CC_SetUpdate() : stm32f3xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_CC : stm32f3xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_UPDATE : stm32f3xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI : stm32f3xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY : stm32f3xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1 : stm32f3xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1N : stm32f3xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2 : stm32f3xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2N : stm32f3xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3 : stm32f3xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3N : stm32f3xx_ll_tim.h
  • LL_TIM_CHANNEL_CH4 : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1OVR() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2OVR() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3OVR() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4OVR() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV1 : stm32f3xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV2 : stm32f3xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV4 : stm32f3xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE1 : stm32f3xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE2 : stm32f3xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_INTERNAL : stm32f3xx_ll_tim.h
  • LL_TIM_ConfigBRK() : stm32f3xx_ll_tim.h
  • LL_TIM_ConfigDMABurst() : stm32f3xx_ll_tim.h
  • LL_TIM_ConfigETR() : stm32f3xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_DOWN : stm32f3xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_UP : stm32f3xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_DOWN : stm32f3xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP : stm32f3xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN : stm32f3xx_ll_tim.h
  • LL_TIM_COUNTERMODE_DOWN : stm32f3xx_ll_tim.h
  • LL_TIM_COUNTERMODE_UP : stm32f3xx_ll_tim.h
  • LL_TIM_DeInit() : stm32f3xx_ll_tim.c
  • LL_TIM_DIER_BIE : stm32f3xx_ll_tim.h
  • LL_TIM_DIER_CC1IE : stm32f3xx_ll_tim.h
  • LL_TIM_DIER_CC2IE : stm32f3xx_ll_tim.h
  • LL_TIM_DIER_CC3IE : stm32f3xx_ll_tim.h
  • LL_TIM_DIER_CC4IE : stm32f3xx_ll_tim.h
  • LL_TIM_DIER_COMIE : stm32f3xx_ll_tim.h
  • LL_TIM_DIER_TIE : stm32f3xx_ll_tim.h
  • LL_TIM_DIER_UIE : stm32f3xx_ll_tim.h
  • LL_TIM_DisableAllOutputs() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableARRPreload() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableAutomaticOutput() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableBRK() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableCounter() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableDMAReq_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableDMAReq_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableDMAReq_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableExternalClock() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableIT_BRK() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableIT_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableIT_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableIT_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableIT_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableIT_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableIT_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableIT_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableMasterSlaveMode() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableUpdateEvent() : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_ARR : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_BDTR : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCER : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR1 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR2 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR3 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR1 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR2 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR3 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR4 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CNT : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR1 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR2 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_DIER : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_EGR : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_OR : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_PSC : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_RCR : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SMCR : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SR : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_1TRANSFER : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_EnableAllOutputs() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableARRPreload() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableAutomaticOutput() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableBRK() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableCounter() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableDMAReq_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableDMAReq_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableDMAReq_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableExternalClock() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableIT_BRK() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableIT_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableIT_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableIT_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableIT_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableIT_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableIT_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableIT_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableMasterSlaveMode() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableUpdateEvent() : stm32f3xx_ll_tim.h
  • LL_TIM_ENCODER_Init() : stm32f3xx_ll_tim.c
  • LL_TIM_ENCODER_StructInit() : stm32f3xx_ll_tim.c
  • LL_TIM_ENCODERMODE_X2_TI1 : stm32f3xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI2 : stm32f3xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X4_TI12 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N5 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N2 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N4 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N5 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_INVERTED : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_NONINVERTED : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV1 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV2 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV4 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV8 : stm32f3xx_ll_tim.h
  • LL_TIM_GenerateEvent_BRK() : stm32f3xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_GenerateEvent_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_GenerateEvent_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_GenerateEvent_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_GetAutoReload() : stm32f3xx_ll_tim.h
  • LL_TIM_GetClockDivision() : stm32f3xx_ll_tim.h
  • LL_TIM_GetCounter() : stm32f3xx_ll_tim.h
  • LL_TIM_GetCounterMode() : stm32f3xx_ll_tim.h
  • LL_TIM_GetDirection() : stm32f3xx_ll_tim.h
  • LL_TIM_GetOnePulseMode() : stm32f3xx_ll_tim.h
  • LL_TIM_GetPrescaler() : stm32f3xx_ll_tim.h
  • LL_TIM_GetRepetitionCounter() : stm32f3xx_ll_tim.h
  • LL_TIM_GetUpdateSource() : stm32f3xx_ll_tim.h
  • LL_TIM_HALLSENSOR_Init() : stm32f3xx_ll_tim.h
  • LL_TIM_HALLSENSOR_StructInit() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_Config() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_DisableXORCombination() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_EnableXORCombination() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N5 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N2 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N4 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N5 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_GetActiveInput() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH1() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH2() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH3() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH4() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_GetFilter() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_GetPolarity() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_GetPrescaler() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_Init() : stm32f3xx_ll_tim.c
  • LL_TIM_IC_IsEnabledXORCombination() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_POLARITY_BOTHEDGE : stm32f3xx_ll_tim.h
  • LL_TIM_IC_POLARITY_FALLING : stm32f3xx_ll_tim.h
  • LL_TIM_IC_POLARITY_RISING : stm32f3xx_ll_tim.h
  • LL_TIM_IC_SetActiveInput() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_SetFilter() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_SetPolarity() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_SetPrescaler() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_StructInit() : stm32f3xx_ll_tim.c
  • LL_TIM_ICPSC_DIV1 : stm32f3xx_ll_tim.h
  • LL_TIM_ICPSC_DIV2 : stm32f3xx_ll_tim.h
  • LL_TIM_ICPSC_DIV4 : stm32f3xx_ll_tim.h
  • LL_TIM_ICPSC_DIV8 : stm32f3xx_ll_tim.h
  • LL_TIM_Init() : stm32f3xx_ll_tim.c
  • LL_TIM_IsActiveFlag_BRK() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1OVR() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2OVR() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3OVR() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4OVR() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledAllOutputs() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledARRPreload() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledAutomaticOutput() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledCounter() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledExternalClock() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledIT_BRK() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledIT_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledIT_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledIT_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledMasterSlaveMode() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledUpdateEvent() : stm32f3xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_1 : stm32f3xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_2 : stm32f3xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_3 : stm32f3xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_OFF : stm32f3xx_ll_tim.h
  • LL_TIM_OC_ConfigOutput() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_DisableClear() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_DisableFast() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_DisablePreload() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_EnableClear() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_EnableFast() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_EnablePreload() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH1() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH2() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH3() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH4() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_GetIdleState() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_GetMode() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_GetPolarity() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_Init() : stm32f3xx_ll_tim.c
  • LL_TIM_OC_IsEnabledClear() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_IsEnabledFast() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_IsEnabledPreload() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH1() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH2() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH3() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH4() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_SetDeadTime() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_SetIdleState() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_SetMode() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_SetPolarity() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_StructInit() : stm32f3xx_ll_tim.c
  • LL_TIM_OCIDLESTATE_HIGH : stm32f3xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_LOW : stm32f3xx_ll_tim.h
  • LL_TIM_OCMODE_ACTIVE : stm32f3xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_ACTIVE : stm32f3xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_INACTIVE : stm32f3xx_ll_tim.h
  • LL_TIM_OCMODE_FROZEN : stm32f3xx_ll_tim.h
  • LL_TIM_OCMODE_INACTIVE : stm32f3xx_ll_tim.h
  • LL_TIM_OCMODE_PWM1 : stm32f3xx_ll_tim.h
  • LL_TIM_OCMODE_PWM2 : stm32f3xx_ll_tim.h
  • LL_TIM_OCMODE_TOGGLE : stm32f3xx_ll_tim.h
  • LL_TIM_OCPOLARITY_HIGH : stm32f3xx_ll_tim.h
  • LL_TIM_OCPOLARITY_LOW : stm32f3xx_ll_tim.h
  • LL_TIM_OCSTATE_DISABLE : stm32f3xx_ll_tim.h
  • LL_TIM_OCSTATE_ENABLE : stm32f3xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_REPETITIVE : stm32f3xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_SINGLE : stm32f3xx_ll_tim.h
  • LL_TIM_OSSI_DISABLE : stm32f3xx_ll_tim.h
  • LL_TIM_OSSI_ENABLE : stm32f3xx_ll_tim.h
  • LL_TIM_OSSR_DISABLE : stm32f3xx_ll_tim.h
  • LL_TIM_OSSR_ENABLE : stm32f3xx_ll_tim.h
  • LL_TIM_ReadReg : stm32f3xx_ll_tim.h
  • LL_TIM_SetAutoReload() : stm32f3xx_ll_tim.h
  • LL_TIM_SetClockDivision() : stm32f3xx_ll_tim.h
  • LL_TIM_SetClockSource() : stm32f3xx_ll_tim.h
  • LL_TIM_SetCounter() : stm32f3xx_ll_tim.h
  • LL_TIM_SetCounterMode() : stm32f3xx_ll_tim.h
  • LL_TIM_SetEncoderMode() : stm32f3xx_ll_tim.h
  • LL_TIM_SetOffStates() : stm32f3xx_ll_tim.h
  • LL_TIM_SetOnePulseMode() : stm32f3xx_ll_tim.h
  • LL_TIM_SetPrescaler() : stm32f3xx_ll_tim.h
  • LL_TIM_SetRemap() : stm32f3xx_ll_tim.h
  • LL_TIM_SetRepetitionCounter() : stm32f3xx_ll_tim.h
  • LL_TIM_SetSlaveMode() : stm32f3xx_ll_tim.h
  • LL_TIM_SetTriggerInput() : stm32f3xx_ll_tim.h
  • LL_TIM_SetTriggerOutput() : stm32f3xx_ll_tim.h
  • LL_TIM_SetUpdateSource() : stm32f3xx_ll_tim.h
  • LL_TIM_SLAVEMODE_DISABLED : stm32f3xx_ll_tim.h
  • LL_TIM_SLAVEMODE_GATED : stm32f3xx_ll_tim.h
  • LL_TIM_SLAVEMODE_RESET : stm32f3xx_ll_tim.h
  • LL_TIM_SLAVEMODE_TRIGGER : stm32f3xx_ll_tim.h
  • LL_TIM_SR_B2IF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_BIF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_CC1IF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_CC1OF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_CC2IF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_CC2OF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_CC3IF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_CC3OF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_CC4IF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_CC4OF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_COMIF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_TIF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_UIF : stm32f3xx_ll_tim.h
  • LL_TIM_StructInit() : stm32f3xx_ll_tim.c
  • LL_TIM_TIM14_TI1_RMP_GPIO : stm32f3xx_ll_tim.h
  • LL_TIM_TIM14_TI1_RMP_HSE : stm32f3xx_ll_tim.h
  • LL_TIM_TIM14_TI1_RMP_MCO : stm32f3xx_ll_tim.h
  • LL_TIM_TIM14_TI1_RMP_RTC_CLK : stm32f3xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_GPIO : stm32f3xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_HSE_32 : stm32f3xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_MCO : stm32f3xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_RTC : stm32f3xx_ll_tim.h
  • LL_TIM_TRGO_CC1IF : stm32f3xx_ll_tim.h
  • LL_TIM_TRGO_ENABLE : stm32f3xx_ll_tim.h
  • LL_TIM_TRGO_OC1REF : stm32f3xx_ll_tim.h
  • LL_TIM_TRGO_OC2REF : stm32f3xx_ll_tim.h
  • LL_TIM_TRGO_OC3REF : stm32f3xx_ll_tim.h
  • LL_TIM_TRGO_OC4REF : stm32f3xx_ll_tim.h
  • LL_TIM_TRGO_RESET : stm32f3xx_ll_tim.h
  • LL_TIM_TRGO_UPDATE : stm32f3xx_ll_tim.h
  • LL_TIM_TS_ETRF : stm32f3xx_ll_tim.h
  • LL_TIM_TS_ITR0 : stm32f3xx_ll_tim.h
  • LL_TIM_TS_ITR1 : stm32f3xx_ll_tim.h
  • LL_TIM_TS_ITR2 : stm32f3xx_ll_tim.h
  • LL_TIM_TS_ITR3 : stm32f3xx_ll_tim.h
  • LL_TIM_TS_TI1F_ED : stm32f3xx_ll_tim.h
  • LL_TIM_TS_TI1FP1 : stm32f3xx_ll_tim.h
  • LL_TIM_TS_TI2FP2 : stm32f3xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_COUNTER : stm32f3xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_REGULAR : stm32f3xx_ll_tim.h
  • LL_TIM_WriteReg : stm32f3xx_ll_tim.h
  • LL_USART_ADDRESS_DETECT_4B : stm32f3xx_ll_usart.h
  • LL_USART_ADDRESS_DETECT_7B : stm32f3xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME : stm32f3xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME : stm32f3xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE : stm32f3xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT : stm32f3xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_NEGATIVE : stm32f3xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_POSITIVE : stm32f3xx_ll_usart.h
  • LL_USART_BITORDER_LSBFIRST : stm32f3xx_ll_usart.h
  • LL_USART_BITORDER_MSBFIRST : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_CM() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_EOB() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_FE() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_IDLE() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_LBD() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_nCTS() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_NE() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_ORE() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_PE() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_RTO() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_TC() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_WKUP() : stm32f3xx_ll_usart.h
  • LL_USART_CLOCK_DISABLE : stm32f3xx_ll_usart.h
  • LL_USART_CLOCK_ENABLE : stm32f3xx_ll_usart.h
  • LL_USART_ClockInit() : stm32f3xx_ll_usart.c
  • LL_USART_ClockStructInit() : stm32f3xx_ll_usart.c
  • LL_USART_ConfigAsyncMode() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigCharacter() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigClock() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigHalfDuplexMode() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigIrdaMode() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigLINMode() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigMultiProcessMode() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigNodeAddress() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigSmartcardMode() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigSyncMode() : stm32f3xx_ll_usart.h
  • LL_USART_CR1_CMIE : stm32f3xx_ll_usart.h
  • LL_USART_CR1_EOBIE : stm32f3xx_ll_usart.h
  • LL_USART_CR1_IDLEIE : stm32f3xx_ll_usart.h
  • LL_USART_CR1_PEIE : stm32f3xx_ll_usart.h
  • LL_USART_CR1_RTOIE : stm32f3xx_ll_usart.h
  • LL_USART_CR1_RXNEIE : stm32f3xx_ll_usart.h
  • LL_USART_CR1_TCIE : stm32f3xx_ll_usart.h
  • LL_USART_CR1_TXEIE : stm32f3xx_ll_usart.h
  • LL_USART_CR2_LBDIE : stm32f3xx_ll_usart.h
  • LL_USART_CR3_CTSIE : stm32f3xx_ll_usart.h
  • LL_USART_CR3_EIE : stm32f3xx_ll_usart.h
  • LL_USART_CR3_WUFIE : stm32f3xx_ll_usart.h
  • LL_USART_DATAWIDTH_8B : stm32f3xx_ll_usart.h
  • LL_USART_DATAWIDTH_9B : stm32f3xx_ll_usart.h
  • LL_USART_DE_POLARITY_HIGH : stm32f3xx_ll_usart.h
  • LL_USART_DE_POLARITY_LOW : stm32f3xx_ll_usart.h
  • LL_USART_DeInit() : stm32f3xx_ll_usart.c
  • LL_USART_DIRECTION_NONE : stm32f3xx_ll_usart.h
  • LL_USART_DIRECTION_RX : stm32f3xx_ll_usart.h
  • LL_USART_DIRECTION_TX : stm32f3xx_ll_usart.h
  • LL_USART_DIRECTION_TX_RX : stm32f3xx_ll_usart.h
  • LL_USART_Disable() : stm32f3xx_ll_usart.h
  • LL_USART_DisableAutoBaudRate() : stm32f3xx_ll_usart.h
  • LL_USART_DisableCTSHWFlowCtrl() : stm32f3xx_ll_usart.h
  • LL_USART_DisableDEMode() : stm32f3xx_ll_usart.h
  • LL_USART_DisableDirectionRx() : stm32f3xx_ll_usart.h
  • LL_USART_DisableDirectionTx() : stm32f3xx_ll_usart.h
  • LL_USART_DisableDMADeactOnRxErr() : stm32f3xx_ll_usart.h
  • LL_USART_DisableDMAReq_RX() : stm32f3xx_ll_usart.h
  • LL_USART_DisableDMAReq_TX() : stm32f3xx_ll_usart.h
  • LL_USART_DisableHalfDuplex() : stm32f3xx_ll_usart.h
  • LL_USART_DisableInStopMode() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIrda() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_CM() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_CTS() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_EOB() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_ERROR() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_IDLE() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_LBD() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_PE() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_RTO() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_RXNE() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_TC() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_TXE() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_WKUP() : stm32f3xx_ll_usart.h
  • LL_USART_DisableLIN() : stm32f3xx_ll_usart.h
  • LL_USART_DisableMuteMode() : stm32f3xx_ll_usart.h
  • LL_USART_DisableOneBitSamp() : stm32f3xx_ll_usart.h
  • LL_USART_DisableOverrunDetect() : stm32f3xx_ll_usart.h
  • LL_USART_DisableRTSHWFlowCtrl() : stm32f3xx_ll_usart.h
  • LL_USART_DisableRxTimeout() : stm32f3xx_ll_usart.h
  • LL_USART_DisableSCLKOutput() : stm32f3xx_ll_usart.h
  • LL_USART_DisableSmartcard() : stm32f3xx_ll_usart.h
  • LL_USART_DisableSmartcardNACK() : stm32f3xx_ll_usart.h
  • LL_USART_DMA_GetRegAddr() : stm32f3xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_RECEIVE : stm32f3xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_TRANSMIT : stm32f3xx_ll_usart.h
  • LL_USART_Enable() : stm32f3xx_ll_usart.h
  • LL_USART_EnableAutoBaudRate() : stm32f3xx_ll_usart.h
  • LL_USART_EnableCTSHWFlowCtrl() : stm32f3xx_ll_usart.h
  • LL_USART_EnableDEMode() : stm32f3xx_ll_usart.h
  • LL_USART_EnableDirectionRx() : stm32f3xx_ll_usart.h
  • LL_USART_EnableDirectionTx() : stm32f3xx_ll_usart.h
  • LL_USART_EnableDMADeactOnRxErr() : stm32f3xx_ll_usart.h
  • LL_USART_EnableDMAReq_RX() : stm32f3xx_ll_usart.h
  • LL_USART_EnableDMAReq_TX() : stm32f3xx_ll_usart.h
  • LL_USART_EnableHalfDuplex() : stm32f3xx_ll_usart.h
  • LL_USART_EnableInStopMode() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIrda() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_CM() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_CTS() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_EOB() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_ERROR() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_IDLE() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_LBD() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_PE() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_RTO() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_RXNE() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_TC() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_TXE() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_WKUP() : stm32f3xx_ll_usart.h
  • LL_USART_EnableLIN() : stm32f3xx_ll_usart.h
  • LL_USART_EnableMuteMode() : stm32f3xx_ll_usart.h
  • LL_USART_EnableOneBitSamp() : stm32f3xx_ll_usart.h
  • LL_USART_EnableOverrunDetect() : stm32f3xx_ll_usart.h
  • LL_USART_EnableRTSHWFlowCtrl() : stm32f3xx_ll_usart.h
  • LL_USART_EnableRxTimeout() : stm32f3xx_ll_usart.h
  • LL_USART_EnableSCLKOutput() : stm32f3xx_ll_usart.h
  • LL_USART_EnableSmartcard() : stm32f3xx_ll_usart.h
  • LL_USART_EnableSmartcardNACK() : stm32f3xx_ll_usart.h
  • LL_USART_GetAutoBaudRateMode() : stm32f3xx_ll_usart.h
  • LL_USART_GetBaudRate() : stm32f3xx_ll_usart.h
  • LL_USART_GetBinaryDataLogic() : stm32f3xx_ll_usart.h
  • LL_USART_GetBlockLength() : stm32f3xx_ll_usart.h
  • LL_USART_GetClockPhase() : stm32f3xx_ll_usart.h
  • LL_USART_GetClockPolarity() : stm32f3xx_ll_usart.h
  • LL_USART_GetDataWidth() : stm32f3xx_ll_usart.h
  • LL_USART_GetDEAssertionTime() : stm32f3xx_ll_usart.h
  • LL_USART_GetDEDeassertionTime() : stm32f3xx_ll_usart.h
  • LL_USART_GetDESignalPolarity() : stm32f3xx_ll_usart.h
  • LL_USART_GetHWFlowCtrl() : stm32f3xx_ll_usart.h
  • LL_USART_GetIrdaPowerMode() : stm32f3xx_ll_usart.h
  • LL_USART_GetIrdaPrescaler() : stm32f3xx_ll_usart.h
  • LL_USART_GetLastClkPulseOutput() : stm32f3xx_ll_usart.h
  • LL_USART_GetLINBrkDetectionLen() : stm32f3xx_ll_usart.h
  • LL_USART_GetNodeAddress() : stm32f3xx_ll_usart.h
  • LL_USART_GetNodeAddressLen() : stm32f3xx_ll_usart.h
  • LL_USART_GetOverSampling() : stm32f3xx_ll_usart.h
  • LL_USART_GetParity() : stm32f3xx_ll_usart.h
  • LL_USART_GetRXPinLevel() : stm32f3xx_ll_usart.h
  • LL_USART_GetRxTimeout() : stm32f3xx_ll_usart.h
  • LL_USART_GetSmartcardAutoRetryCount() : stm32f3xx_ll_usart.h
  • LL_USART_GetSmartcardGuardTime() : stm32f3xx_ll_usart.h
  • LL_USART_GetSmartcardPrescaler() : stm32f3xx_ll_usart.h
  • LL_USART_GetStopBitsLength() : stm32f3xx_ll_usart.h
  • LL_USART_GetTransferBitOrder() : stm32f3xx_ll_usart.h
  • LL_USART_GetTransferDirection() : stm32f3xx_ll_usart.h
  • LL_USART_GetTXPinLevel() : stm32f3xx_ll_usart.h
  • LL_USART_GetTXRXSwap() : stm32f3xx_ll_usart.h
  • LL_USART_GetWakeUpMethod() : stm32f3xx_ll_usart.h
  • LL_USART_GetWKUPType() : stm32f3xx_ll_usart.h
  • LL_USART_HWCONTROL_CTS : stm32f3xx_ll_usart.h
  • LL_USART_HWCONTROL_NONE : stm32f3xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS : stm32f3xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS_CTS : stm32f3xx_ll_usart.h
  • LL_USART_ICR_CMCF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_CTSCF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_EOBCF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_FECF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_IDLECF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_LBDCF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_NCF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_ORECF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_PECF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_RTOCF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_TCCF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_WUCF : stm32f3xx_ll_usart.h
  • LL_USART_Init() : stm32f3xx_ll_usart.c
  • LL_USART_IRDA_POWER_LOW : stm32f3xx_ll_usart.h
  • LL_USART_IRDA_POWER_NORMAL : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_ABR() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_ABRE() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_BUSY() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_CM() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_CTS() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_EOB() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_FE() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_IDLE() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_LBD() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_nCTS() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_NE() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_ORE() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_PE() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_REACK() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_RTO() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_RWU() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_SBK() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_TC() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_TEACK() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_WKUP() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabled() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledAutoBaud() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledDEMode() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledDMADeactOnRxErr() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_RX() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_TX() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledHalfDuplex() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledInStopMode() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIrda() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_CM() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_CTS() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_EOB() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_ERROR() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_IDLE() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_LBD() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_PE() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_RTO() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_TC() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_WKUP() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledLIN() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledMuteMode() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledOneBitSamp() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledOverrunDetect() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledRxTimeout() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledSCLKOutput() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledSmartcard() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledSmartcardNACK() : stm32f3xx_ll_usart.h
  • LL_USART_ISR_ABRE : stm32f3xx_ll_usart.h
  • LL_USART_ISR_ABRF : stm32f3xx_ll_usart.h
  • LL_USART_ISR_BUSY : stm32f3xx_ll_usart.h
  • LL_USART_ISR_CMF : stm32f3xx_ll_usart.h
  • LL_USART_ISR_CTS : stm32f3xx_ll_usart.h
  • LL_USART_ISR_CTSIF : stm32f3xx_ll_usart.h
  • LL_USART_ISR_EOBF : stm32f3xx_ll_usart.h
  • LL_USART_ISR_FE : stm32f3xx_ll_usart.h
  • LL_USART_ISR_IDLE : stm32f3xx_ll_usart.h
  • LL_USART_ISR_LBDF : stm32f3xx_ll_usart.h
  • LL_USART_ISR_NE : stm32f3xx_ll_usart.h
  • LL_USART_ISR_ORE : stm32f3xx_ll_usart.h
  • LL_USART_ISR_PE : stm32f3xx_ll_usart.h
  • LL_USART_ISR_REACK : stm32f3xx_ll_usart.h
  • LL_USART_ISR_RTOF : stm32f3xx_ll_usart.h
  • LL_USART_ISR_RWU : stm32f3xx_ll_usart.h
  • LL_USART_ISR_RXNE : stm32f3xx_ll_usart.h
  • LL_USART_ISR_SBKF : stm32f3xx_ll_usart.h
  • LL_USART_ISR_TC : stm32f3xx_ll_usart.h
  • LL_USART_ISR_TEACK : stm32f3xx_ll_usart.h
  • LL_USART_ISR_TXE : stm32f3xx_ll_usart.h
  • LL_USART_ISR_WUF : stm32f3xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_NO_OUTPUT : stm32f3xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_OUTPUT : stm32f3xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_10B : stm32f3xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_11B : stm32f3xx_ll_usart.h
  • LL_USART_OVERSAMPLING_16 : stm32f3xx_ll_usart.h
  • LL_USART_OVERSAMPLING_8 : stm32f3xx_ll_usart.h
  • LL_USART_PARITY_EVEN : stm32f3xx_ll_usart.h
  • LL_USART_PARITY_NONE : stm32f3xx_ll_usart.h
  • LL_USART_PARITY_ODD : stm32f3xx_ll_usart.h
  • LL_USART_PHASE_1EDGE : stm32f3xx_ll_usart.h
  • LL_USART_PHASE_2EDGE : stm32f3xx_ll_usart.h
  • LL_USART_POLARITY_HIGH : stm32f3xx_ll_usart.h
  • LL_USART_POLARITY_LOW : stm32f3xx_ll_usart.h
  • LL_USART_ReadReg : stm32f3xx_ll_usart.h
  • LL_USART_ReceiveData8() : stm32f3xx_ll_usart.h
  • LL_USART_ReceiveData9() : stm32f3xx_ll_usart.h
  • LL_USART_RequestAutoBaudRate() : stm32f3xx_ll_usart.h
  • LL_USART_RequestBreakSending() : stm32f3xx_ll_usart.h
  • LL_USART_RequestEnterMuteMode() : stm32f3xx_ll_usart.h
  • LL_USART_RequestRxDataFlush() : stm32f3xx_ll_usart.h
  • LL_USART_RequestTxDataFlush() : stm32f3xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_INVERTED : stm32f3xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_STANDARD : stm32f3xx_ll_usart.h
  • LL_USART_SetAutoBaudRateMode() : stm32f3xx_ll_usart.h
  • LL_USART_SetBaudRate() : stm32f3xx_ll_usart.h
  • LL_USART_SetBinaryDataLogic() : stm32f3xx_ll_usart.h
  • LL_USART_SetBlockLength() : stm32f3xx_ll_usart.h
  • LL_USART_SetClockPhase() : stm32f3xx_ll_usart.h
  • LL_USART_SetClockPolarity() : stm32f3xx_ll_usart.h
  • LL_USART_SetDataWidth() : stm32f3xx_ll_usart.h
  • LL_USART_SetDEAssertionTime() : stm32f3xx_ll_usart.h
  • LL_USART_SetDEDeassertionTime() : stm32f3xx_ll_usart.h
  • LL_USART_SetDESignalPolarity() : stm32f3xx_ll_usart.h
  • LL_USART_SetHWFlowCtrl() : stm32f3xx_ll_usart.h
  • LL_USART_SetIrdaPowerMode() : stm32f3xx_ll_usart.h
  • LL_USART_SetIrdaPrescaler() : stm32f3xx_ll_usart.h
  • LL_USART_SetLastClkPulseOutput() : stm32f3xx_ll_usart.h
  • LL_USART_SetLINBrkDetectionLen() : stm32f3xx_ll_usart.h
  • LL_USART_SetOverSampling() : stm32f3xx_ll_usart.h
  • LL_USART_SetParity() : stm32f3xx_ll_usart.h
  • LL_USART_SetRXPinLevel() : stm32f3xx_ll_usart.h
  • LL_USART_SetRxTimeout() : stm32f3xx_ll_usart.h
  • LL_USART_SetSmartcardAutoRetryCount() : stm32f3xx_ll_usart.h
  • LL_USART_SetSmartcardGuardTime() : stm32f3xx_ll_usart.h
  • LL_USART_SetSmartcardPrescaler() : stm32f3xx_ll_usart.h
  • LL_USART_SetStopBitsLength() : stm32f3xx_ll_usart.h
  • LL_USART_SetTransferBitOrder() : stm32f3xx_ll_usart.h
  • LL_USART_SetTransferDirection() : stm32f3xx_ll_usart.h
  • LL_USART_SetTXPinLevel() : stm32f3xx_ll_usart.h
  • LL_USART_SetTXRXSwap() : stm32f3xx_ll_usart.h
  • LL_USART_SetWakeUpMethod() : stm32f3xx_ll_usart.h
  • LL_USART_SetWKUPType() : stm32f3xx_ll_usart.h
  • LL_USART_STOPBITS_0_5 : stm32f3xx_ll_usart.h
  • LL_USART_STOPBITS_1 : stm32f3xx_ll_usart.h
  • LL_USART_STOPBITS_1_5 : stm32f3xx_ll_usart.h
  • LL_USART_STOPBITS_2 : stm32f3xx_ll_usart.h
  • LL_USART_StructInit() : stm32f3xx_ll_usart.c
  • LL_USART_TransmitData8() : stm32f3xx_ll_usart.h
  • LL_USART_TransmitData9() : stm32f3xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_INVERTED : stm32f3xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_STANDARD : stm32f3xx_ll_usart.h
  • LL_USART_TXRX_STANDARD : stm32f3xx_ll_usart.h
  • LL_USART_TXRX_SWAPPED : stm32f3xx_ll_usart.h
  • LL_USART_WAKEUP_ADDRESSMARK : stm32f3xx_ll_usart.h
  • LL_USART_WAKEUP_IDLELINE : stm32f3xx_ll_usart.h
  • LL_USART_WAKEUP_ON_ADDRESS : stm32f3xx_ll_usart.h
  • LL_USART_WAKEUP_ON_RXNE : stm32f3xx_ll_usart.h
  • LL_USART_WAKEUP_ON_STARTBIT : stm32f3xx_ll_usart.h
  • LL_USART_WriteReg : stm32f3xx_ll_usart.h
  • LL_UTILS_HSEBYPASS_OFF : stm32f3xx_ll_utils.h
  • LL_UTILS_HSEBYPASS_ON : stm32f3xx_ll_utils.h
  • LL_WWDG_CFR_EWI : stm32f3xx_ll_wwdg.h
  • LL_WWDG_ClearFlag_EWKUP() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_Enable() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_EnableIT_EWKUP() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_GetCounter() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_GetPrescaler() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_GetWindow() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_IsActiveFlag_EWKUP() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_IsEnabled() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_IsEnabledIT_EWKUP() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_1 : stm32f3xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_2 : stm32f3xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_4 : stm32f3xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_8 : stm32f3xx_ll_wwdg.h
  • LL_WWDG_ReadReg : stm32f3xx_ll_wwdg.h
  • LL_WWDG_SetCounter() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_SetPrescaler() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_SetWindow() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_WriteReg : stm32f3xx_ll_wwdg.h
  • LSE_STARTUP_TIMEOUT : stm32f3xx_hal_conf.h
  • LSE_VALUE : stm32f3xx_hal_conf.h , stm32f3xx_ll_rcc.h
  • LSI_TIMEOUT_VALUE : stm32f3xx_hal_rcc.h
  • LSI_VALUE : stm32f3xx_hal_conf.h , stm32f3xx_ll_rcc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
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  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- m -

  • MAX_NBYTE_SIZE : stm32f3xx_hal_i2c.c , stm32f3xx_hal_smbus.c
  • MCO1_CLK_ENABLE : stm32f3xx_hal_rcc.c
  • MCO1_GPIO_PORT : stm32f3xx_hal_rcc.c
  • MCO1_PIN : stm32f3xx_hal_rcc.c
  • MPU_ACCESS_BUFFERABLE : stm32f3xx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32f3xx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32f3xx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32f3xx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32f3xx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32f3xx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32f3xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32f3xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32f3xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32f3xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32f3xx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32f3xx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32f3xx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32f3xx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32f3xx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32f3xx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32f3xx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32f3xx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32f3xx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32f3xx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32f3xx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32f3xx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32f3xx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32f3xx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32f3xx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32f3xx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32f3xx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_128B : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_32B : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_64B : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32f3xx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32f3xx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32f3xx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32f3xx_hal_cortex.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
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  • d
  • e
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  • g
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- n -

  • NVIC_PRIORITYGROUP_0 : stm32f3xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32f3xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32f3xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32f3xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32f3xx_hal_cortex.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
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  • r
  • s
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- o -

  • OB_BOOT1_RESET : stm32f3xx_hal_flash_ex.h
  • OB_BOOT1_SET : stm32f3xx_hal_flash_ex.h
  • OB_DATA_ADDRESS_DATA0 : stm32f3xx_hal_flash_ex.h
  • OB_DATA_ADDRESS_DATA1 : stm32f3xx_hal_flash_ex.h
  • OB_IWDG_HW : stm32f3xx_hal_flash_ex.h
  • OB_IWDG_SW : stm32f3xx_hal_flash_ex.h
  • OB_RDP_LEVEL_0 : stm32f3xx_hal_flash_ex.h
  • OB_RDP_LEVEL_1 : stm32f3xx_hal_flash_ex.h
  • OB_RDP_LEVEL_2 : stm32f3xx_hal_flash_ex.h
  • OB_SDACD_VDD_MONITOR_RESET : stm32f3xx_hal_flash_ex.h
  • OB_SDACD_VDD_MONITOR_SET : stm32f3xx_hal_flash_ex.h
  • OB_SRAM_PARITY_RESET : stm32f3xx_hal_flash_ex.h
  • OB_SRAM_PARITY_SET : stm32f3xx_hal_flash_ex.h
  • OB_STDBY_NO_RST : stm32f3xx_hal_flash_ex.h
  • OB_STDBY_RST : stm32f3xx_hal_flash_ex.h
  • OB_STOP_NO_RST : stm32f3xx_hal_flash_ex.h
  • OB_STOP_RST : stm32f3xx_hal_flash_ex.h
  • OB_VDDA_ANALOG_OFF : stm32f3xx_hal_flash_ex.h
  • OB_VDDA_ANALOG_ON : stm32f3xx_hal_flash_ex.h
  • OB_WRP_ALLPAGES : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES0TO1 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES0TO15MASK : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES10TO11 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES12TO13 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES14TO15 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES16TO17 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES16TO31MASK : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES18TO19 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES20TO21 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES22TO23 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES24TO25 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES26TO27 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES28TO29 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES2TO3 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES30TO31 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES32TO33 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES32TO47MASK : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES34TO35 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES36TO37 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES38TO39 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES40TO41 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES42TO43 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES44TO45 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES46TO47 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES48TO127MASK : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES48TO49 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES4TO5 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES50TO51 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES52TO53 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES54TO55 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES56TO57 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES58TO59 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES60TO61 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES62TO127 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES6TO7 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES8TO9 : stm32f3xx_hal_flash_ex.h
  • OB_WRPSTATE_DISABLE : stm32f3xx_hal_flash_ex.h
  • OB_WRPSTATE_ENABLE : stm32f3xx_hal_flash_ex.h
  • OC1Config() : stm32f3xx_ll_tim.c
  • OC2Config() : stm32f3xx_ll_tim.c
  • OC3Config() : stm32f3xx_ll_tim.c
  • OC4Config() : stm32f3xx_ll_tim.c
  • OFFSET_TAB_CCMRx : stm32f3xx_ll_tim.h
  • OPTIONBYTE_DATA : stm32f3xx_hal_flash_ex.h
  • OPTIONBYTE_RDP : stm32f3xx_hal_flash_ex.h
  • OPTIONBYTE_USER : stm32f3xx_hal_flash_ex.h
  • OPTIONBYTE_WRP : stm32f3xx_hal_flash_ex.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
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  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- p -

  • PACKAGE_BASE_ADDRESS : stm32f3xx_ll_utils.h
  • PCD_CALC_BLK2 : stm32f3xx_hal_pcd.h
  • PCD_CALC_BLK32 : stm32f3xx_hal_pcd.h
  • PCD_CLEAR_EP_DBUF : stm32f3xx_hal_pcd.h
  • PCD_CLEAR_EP_KIND : stm32f3xx_hal_pcd.h
  • PCD_CLEAR_OUT_STATUS : stm32f3xx_hal_pcd.h
  • PCD_CLEAR_RX_DTOG : stm32f3xx_hal_pcd.h
  • PCD_CLEAR_RX_EP_CTR : stm32f3xx_hal_pcd.h
  • PCD_CLEAR_TX_DTOG : stm32f3xx_hal_pcd.h
  • PCD_CLEAR_TX_EP_CTR : stm32f3xx_hal_pcd.h
  • PCD_DBL_BUF : stm32f3xx_hal_pcd.h
  • PCD_ENDP0 : stm32f3xx_hal_pcd.h
  • PCD_ENDP1 : stm32f3xx_hal_pcd.h
  • PCD_ENDP2 : stm32f3xx_hal_pcd.h
  • PCD_ENDP3 : stm32f3xx_hal_pcd.h
  • PCD_ENDP4 : stm32f3xx_hal_pcd.h
  • PCD_ENDP5 : stm32f3xx_hal_pcd.h
  • PCD_ENDP6 : stm32f3xx_hal_pcd.h
  • PCD_ENDP7 : stm32f3xx_hal_pcd.h
  • PCD_EP0MPS_08 : stm32f3xx_hal_pcd.h
  • PCD_EP0MPS_16 : stm32f3xx_hal_pcd.h
  • PCD_EP0MPS_32 : stm32f3xx_hal_pcd.h
  • PCD_EP0MPS_64 : stm32f3xx_hal_pcd.h
  • PCD_EP_BUF0 : stm32f3xx_hal_pcd.h
  • PCD_EP_BUF1 : stm32f3xx_hal_pcd.h
  • PCD_EP_BUF_NUM : stm32f3xx_hal_pcd.h
  • PCD_EP_DBUF_DIR : stm32f3xx_hal_pcd.h
  • PCD_EP_DBUF_ERR : stm32f3xx_hal_pcd.h
  • PCD_EP_DBUF_IN : stm32f3xx_hal_pcd.h
  • PCD_EP_DBUF_OUT : stm32f3xx_hal_pcd.h
  • PCD_EP_ISR_Handler() : stm32f3xx_hal_pcd.c
  • PCD_EP_NOBUF : stm32f3xx_hal_pcd.h
  • PCD_EP_RX_ADDRESS : stm32f3xx_hal_pcd_ex.h
  • PCD_EP_RX_CNT : stm32f3xx_hal_pcd_ex.h
  • PCD_EP_TX_ADDRESS : stm32f3xx_hal_pcd_ex.h
  • PCD_EP_TX_CNT : stm32f3xx_hal_pcd_ex.h
  • PCD_EP_TYPE_BULK : stm32f3xx_hal_pcd.h
  • PCD_EP_TYPE_CTRL : stm32f3xx_hal_pcd.h
  • PCD_EP_TYPE_INTR : stm32f3xx_hal_pcd.h
  • PCD_EP_TYPE_ISOC : stm32f3xx_hal_pcd.h
  • PCD_FreeUserBuffer : stm32f3xx_hal_pcd.h
  • PCD_GET_DB_DIR : stm32f3xx_hal_pcd.h
  • PCD_GET_ENDPOINT : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_ADDRESS : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_DBUF0_ADDR : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_DBUF0_CNT : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_DBUF1_ADDR : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_DBUF1_CNT : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_RX_ADDRESS : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_RX_CNT : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_RX_STALL_STATUS : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_RX_STATUS : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_TX_ADDRESS : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_TX_CNT : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_TX_STALL_STATUS : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_TX_STATUS : stm32f3xx_hal_pcd.h
  • PCD_GET_EPTYPE : stm32f3xx_hal_pcd.h
  • PCD_PHY_EMBEDDED : stm32f3xx_hal_pcd.h
  • PCD_ReadPMA() : stm32f3xx_hal_pcd.h
  • PCD_RX_DTOG : stm32f3xx_hal_pcd.h
  • PCD_SET_ENDPOINT : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_ADDRESS : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_CNT_RX_REG : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_DBUF : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_DBUF0_ADDR : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_DBUF0_CNT : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_DBUF1_ADDR : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_DBUF1_CNT : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_DBUF_ADDR : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_DBUF_CNT : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_KIND : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_RX_ADDRESS : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_RX_CNT : stm32f3xx_hal_pcd_ex.h
  • PCD_SET_EP_RX_DBUF0_CNT : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_RX_STATUS : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_RX_VALID : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_TX_ADDRESS : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_TX_CNT : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_TX_STATUS : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_TX_VALID : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_TXRX_STATUS : stm32f3xx_hal_pcd.h
  • PCD_SET_EPTYPE : stm32f3xx_hal_pcd.h
  • PCD_SET_OUT_STATUS : stm32f3xx_hal_pcd.h
  • PCD_SNG_BUF : stm32f3xx_hal_pcd.h
  • PCD_SPEED_FULL : stm32f3xx_hal_pcd.h
  • PCD_SPEED_HIGH : stm32f3xx_hal_pcd.h
  • PCD_StateTypeDef : stm32f3xx_hal_pcd.h
  • PCD_TX_DTOG : stm32f3xx_hal_pcd.h
  • PCD_TypeDef : stm32f3xx_hal_pcd.h
  • PCD_WritePMA() : stm32f3xx_hal_pcd.h
  • pFlash : stm32f3xx_hal_flash.c , stm32f3xx_hal_flash_ex.c
  • PLL_TIMEOUT_VALUE : stm32f3xx_hal_rcc.h
  • PREFETCH_ENABLE : stm32f3xx_hal_conf.h
  • PVD_FALLING_EDGE : stm32f3xx_hal_pwr_ex.c
  • PVD_MODE_EVT : stm32f3xx_hal_pwr_ex.c
  • PVD_MODE_IT : stm32f3xx_hal_pwr_ex.c
  • PVD_RISING_EDGE : stm32f3xx_hal_pwr_ex.c
  • PWR_EXTI_LINE_PVD : stm32f3xx_hal_pwr_ex.h
  • PWR_FLAG_PVDO : stm32f3xx_hal_pwr.h
  • PWR_FLAG_SB : stm32f3xx_hal_pwr.h
  • PWR_FLAG_VREFINTRDY : stm32f3xx_hal_pwr.h
  • PWR_FLAG_WU : stm32f3xx_hal_pwr.h
  • PWR_LOWPOWERREGULATOR_ON : stm32f3xx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32f3xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_FALLING : stm32f3xx_hal_pwr_ex.h
  • PWR_PVD_MODE_EVENT_RISING : stm32f3xx_hal_pwr_ex.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32f3xx_hal_pwr_ex.h
  • PWR_PVD_MODE_IT_FALLING : stm32f3xx_hal_pwr_ex.h
  • PWR_PVD_MODE_IT_RISING : stm32f3xx_hal_pwr_ex.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32f3xx_hal_pwr_ex.h
  • PWR_PVD_MODE_NORMAL : stm32f3xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_0 : stm32f3xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_1 : stm32f3xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_2 : stm32f3xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_3 : stm32f3xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_4 : stm32f3xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_5 : stm32f3xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_6 : stm32f3xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_7 : stm32f3xx_hal_pwr_ex.h
  • PWR_SDADC_ANALOG1 : stm32f3xx_hal_pwr_ex.h
  • PWR_SDADC_ANALOG2 : stm32f3xx_hal_pwr_ex.h
  • PWR_SDADC_ANALOG3 : stm32f3xx_hal_pwr_ex.h
  • PWR_SLEEPENTRY_WFE : stm32f3xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32f3xx_hal_pwr.h
  • PWR_STOPENTRY_WFE : stm32f3xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32f3xx_hal_pwr.h
  • PWR_WAKEUP_PIN1 : stm32f3xx_hal_pwr.h
  • PWR_WAKEUP_PIN2 : stm32f3xx_hal_pwr.h
  • PWR_WAKEUP_PIN3 : stm32f3xx_hal_pwr.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- r -

  • RCC_ADC1PCLK2_DIV2 : stm32f3xx_hal_rcc_ex.h
  • RCC_ADC1PCLK2_DIV4 : stm32f3xx_hal_rcc_ex.h
  • RCC_ADC1PCLK2_DIV6 : stm32f3xx_hal_rcc_ex.h
  • RCC_ADC1PCLK2_DIV8 : stm32f3xx_hal_rcc_ex.h
  • RCC_BDCR_BDRST_BB : stm32f3xx_hal_rcc.h
  • RCC_BDCR_LSEBYP_BB : stm32f3xx_hal_rcc.h
  • RCC_BDCR_LSEON_BB : stm32f3xx_hal_rcc.h
  • RCC_BDCR_OFFSET : stm32f3xx_hal_rcc.h
  • RCC_BDCR_OFFSET_BB : stm32f3xx_hal_rcc.h
  • RCC_BDCR_RTCEN_BB : stm32f3xx_hal_rcc.h
  • RCC_BDRST_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_CECCLKSOURCE_HSI : stm32f3xx_hal_rcc_ex.h
  • RCC_CECCLKSOURCE_LSE : stm32f3xx_hal_rcc_ex.h
  • RCC_CFGR_HPRE_BITNUMBER : stm32f3xx_hal_rcc.c
  • RCC_CFGR_OFFSET : stm32f3xx_hal_rcc.h
  • RCC_CFGR_OFFSET_BB : stm32f3xx_hal_rcc.h
  • RCC_CFGR_PPRE1_BITNUMBER : stm32f3xx_hal_rcc.c
  • RCC_CFGR_PPRE2_BITNUMBER : stm32f3xx_hal_rcc.c
  • RCC_CIR_BYTE1_ADDRESS : stm32f3xx_hal_rcc.h
  • RCC_CIR_BYTE2_ADDRESS : stm32f3xx_hal_rcc.h
  • RCC_CIR_OFFSET : stm32f3xx_hal_rcc.h
  • RCC_CIR_OFFSET_BB : stm32f3xx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK : stm32f3xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32f3xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32f3xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32f3xx_hal_rcc.h
  • RCC_CR_BYTE2_ADDRESS : stm32f3xx_hal_rcc.h
  • RCC_CR_CSSON_BB : stm32f3xx_hal_rcc.h
  • RCC_CR_HSEON_BB : stm32f3xx_hal_rcc.h
  • RCC_CR_HSION_BB : stm32f3xx_hal_rcc.h
  • RCC_CR_OFFSET : stm32f3xx_hal_rcc.h
  • RCC_CR_OFFSET_BB : stm32f3xx_hal_rcc.h
  • RCC_CR_PLLON_BB : stm32f3xx_hal_rcc.h
  • RCC_CSR_LSION_BB : stm32f3xx_hal_rcc.h
  • RCC_CSR_OFFSET : stm32f3xx_hal_rcc.h
  • RCC_CSR_OFFSET_BB : stm32f3xx_hal_rcc.h
  • RCC_CSR_RMVF_BB : stm32f3xx_hal_rcc.h
  • RCC_CSSON_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_DBP_TIMEOUT_VALUE : stm32f3xx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32f3xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32f3xx_hal_rcc.h
  • RCC_FLAG_IWDGRST : stm32f3xx_hal_rcc.h
  • RCC_FLAG_LPWRRST : stm32f3xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32f3xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32f3xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32f3xx_hal_rcc.h
  • RCC_FLAG_OBLRST : stm32f3xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32f3xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32f3xx_hal_rcc.h
  • RCC_FLAG_PORRST : stm32f3xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32f3xx_hal_rcc.h
  • RCC_FLAG_V18PWRRST : stm32f3xx_hal_rcc.h
  • RCC_FLAG_WWDGRST : stm32f3xx_hal_rcc.h
  • RCC_GetHCLKClockFreq() : stm32f3xx_ll_rcc.c
  • RCC_GetPCLK1ClockFreq() : stm32f3xx_ll_rcc.c
  • RCC_GetPCLK2ClockFreq() : stm32f3xx_ll_rcc.c
  • RCC_GetPLLCLKFreq() : stm32f3xx_hal_rcc_ex.c
  • RCC_GetSystemClockFreq() : stm32f3xx_ll_rcc.c
  • RCC_HCLK_DIV1 : stm32f3xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32f3xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32f3xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32f3xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32f3xx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32f3xx_hal_rcc.h
  • RCC_HSE_OFF : stm32f3xx_hal_rcc.h
  • RCC_HSE_ON : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV1 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV10 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV11 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV12 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV13 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV14 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV15 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV16 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV2 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV3 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV4 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV5 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV6 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV7 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV8 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV9 : stm32f3xx_hal_rcc.h
  • RCC_HSEON_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_HSI_OFF : stm32f3xx_hal_rcc.h
  • RCC_HSI_ON : stm32f3xx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32f3xx_hal_rcc.h
  • RCC_HSION_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_I2C1CLKSOURCE_HSI : stm32f3xx_hal_rcc.h
  • RCC_I2C1CLKSOURCE_SYSCLK : stm32f3xx_hal_rcc.h
  • RCC_I2C2CLKSOURCE_HSI : stm32f3xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_SYSCLK : stm32f3xx_hal_rcc_ex.h
  • RCC_IT_CSS : stm32f3xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32f3xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32f3xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32f3xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32f3xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32f3xx_hal_rcc.h
  • RCC_LSE_BYPASS : stm32f3xx_hal_rcc.h
  • RCC_LSE_OFF : stm32f3xx_hal_rcc.h
  • RCC_LSE_ON : stm32f3xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32f3xx_hal_rcc.h
  • RCC_LSEBYP_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_LSEDRIVE_HIGH : stm32f3xx_hal_rcc_ex.h
  • RCC_LSEDRIVE_LOW : stm32f3xx_hal_rcc_ex.h
  • RCC_LSEDRIVE_MEDIUMHIGH : stm32f3xx_hal_rcc_ex.h
  • RCC_LSEDRIVE_MEDIUMLOW : stm32f3xx_hal_rcc_ex.h
  • RCC_LSEON_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_LSI_OFF : stm32f3xx_hal_rcc.h
  • RCC_LSI_ON : stm32f3xx_hal_rcc.h
  • RCC_LSION_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_MCO : stm32f3xx_hal_rcc.h
  • RCC_MCO1 : stm32f3xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32f3xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_HSI : stm32f3xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_LSE : stm32f3xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_LSI : stm32f3xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_NOCLOCK : stm32f3xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_PLLCLK_DIV2 : stm32f3xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_SYSCLK : stm32f3xx_hal_rcc_ex.h
  • RCC_MCODIV_1 : stm32f3xx_hal_rcc_ex.h
  • RCC_OFFSET : stm32f3xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32f3xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32f3xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32f3xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32f3xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32f3xx_hal_rcc.h
  • RCC_PERIPHCLK_ADC1 : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_CEC : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C1 : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C2 : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SDADC : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART1 : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART2 : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART3 : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USB : stm32f3xx_hal_rcc_ex.h
  • RCC_PLL_GetFreqDomain_SYS() : stm32f3xx_ll_rcc.c
  • RCC_PLL_MUL10 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL11 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL12 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL13 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL14 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL15 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL16 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL2 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL3 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL4 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL5 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL6 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL7 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL8 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL9 : stm32f3xx_hal_rcc.h
  • RCC_PLL_NONE : stm32f3xx_hal_rcc.h
  • RCC_PLL_OFF : stm32f3xx_hal_rcc.h
  • RCC_PLL_ON : stm32f3xx_hal_rcc.h
  • RCC_PLLON_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32f3xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32f3xx_hal_rcc.h
  • RCC_POSITION_HPRE : stm32f3xx_ll_rcc.h
  • RCC_POSITION_HSICAL : stm32f3xx_ll_rcc.h
  • RCC_POSITION_HSITRIM : stm32f3xx_ll_rcc.h
  • RCC_POSITION_PLLMUL : stm32f3xx_ll_rcc.h
  • RCC_POSITION_PPRE1 : stm32f3xx_ll_rcc.h
  • RCC_POSITION_PPRE2 : stm32f3xx_ll_rcc.h
  • RCC_POSITION_TIM15SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_TIM16SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_TIM17SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_TIM1SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_TIM20SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_TIM2SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_TIM34SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_TIM8SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_USART1SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_USART2SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_USART3SW : stm32f3xx_ll_rcc.h
  • RCC_RMVF_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV32 : stm32f3xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32f3xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32f3xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_NO_CLK : stm32f3xx_hal_rcc.h
  • RCC_RTCEN_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_SDADCSYSCLK_DIV1 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV10 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV12 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV14 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV16 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV2 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV20 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV24 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV28 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV32 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV36 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV4 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV40 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV44 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV48 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV6 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV8 : stm32f3xx_hal_rcc_ex.h
  • RCC_SYSCLK_DIV1 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32f3xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32f3xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32f3xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32f3xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32f3xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32f3xx_hal_rcc.h
  • RCC_USART1CLKSOURCE_HSI : stm32f3xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_LSE : stm32f3xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PCLK2 : stm32f3xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_SYSCLK : stm32f3xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_HSI : stm32f3xx_hal_rcc.h
  • RCC_USART2CLKSOURCE_LSE : stm32f3xx_hal_rcc.h
  • RCC_USART2CLKSOURCE_PCLK1 : stm32f3xx_hal_rcc.h
  • RCC_USART2CLKSOURCE_SYSCLK : stm32f3xx_hal_rcc.h
  • RCC_USART3CLKSOURCE_HSI : stm32f3xx_hal_rcc.h
  • RCC_USART3CLKSOURCE_LSE : stm32f3xx_hal_rcc.h
  • RCC_USART3CLKSOURCE_PCLK1 : stm32f3xx_hal_rcc.h
  • RCC_USART3CLKSOURCE_SYSCLK : stm32f3xx_hal_rcc.h
  • RCC_USBCLKSOURCE_PLL : stm32f3xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL_DIV1_5 : stm32f3xx_hal_rcc_ex.h
  • RISING_EDGE : stm32f3xx_hal_gpio.c
  • RTC_ALARM_A : stm32f3xx_hal_rtc.h
  • RTC_ALARM_B : stm32f3xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32f3xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32f3xx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32f3xx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32f3xx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32f3xx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32f3xx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32f3xx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32f3xx_hal_rtc.h
  • RTC_ASYNCH_PRESC_DEFAULT : stm32f3xx_ll_rtc.c
  • RTC_Bcd2ToByte() : stm32f3xx_hal_rtc.c , stm32f3xx_hal_rtc.h
  • RTC_BKP_DR0 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR11 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR12 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR13 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR14 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR15 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR16 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR17 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR18 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR19 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR20 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR21 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR22 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR23 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR24 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR25 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR26 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR27 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR28 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR29 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR30 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR31 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32f3xx_hal_rtc_ex.h
  • RTC_ByteToBcd2() : stm32f3xx_hal_rtc.c , stm32f3xx_hal_rtc.h
  • RTC_CALIBOUTPUT_1HZ : stm32f3xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32f3xx_hal_rtc_ex.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32f3xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32f3xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32f3xx_hal_rtc.h
  • RTC_DR_RESERVED_MASK : stm32f3xx_hal_rtc.h
  • RTC_EnterInitMode() : stm32f3xx_hal_rtc.c , stm32f3xx_hal_rtc.h
  • RTC_EXTI_LINE_ALARM_EVENT : stm32f3xx_hal_rtc.h
  • RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT : stm32f3xx_hal_rtc.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32f3xx_hal_rtc.h
  • RTC_FLAG_ALRAF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_INITF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_INITS : stm32f3xx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_TAMP1F : stm32f3xx_hal_rtc.h
  • RTC_FLAG_TAMP2F : stm32f3xx_hal_rtc.h
  • RTC_FLAG_TAMP3F : stm32f3xx_hal_rtc.h
  • RTC_FLAG_TSF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32f3xx_hal_rtc.h
  • RTC_FLAGS_MASK : stm32f3xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32f3xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32f3xx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32f3xx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32f3xx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32f3xx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32f3xx_hal_rtc.h
  • RTC_INIT_MASK : stm32f3xx_hal_rtc.h , stm32f3xx_ll_rtc.h
  • RTC_INITMODE_TIMEOUT : stm32f3xx_ll_rtc.c
  • RTC_IT_ALRA : stm32f3xx_hal_rtc.h
  • RTC_IT_ALRB : stm32f3xx_hal_rtc.h
  • RTC_IT_TAMP : stm32f3xx_hal_rtc.h
  • RTC_IT_TAMP1 : stm32f3xx_hal_rtc.h
  • RTC_IT_TAMP2 : stm32f3xx_hal_rtc.h
  • RTC_IT_TAMP3 : stm32f3xx_hal_rtc.h
  • RTC_IT_TS : stm32f3xx_hal_rtc.h
  • RTC_IT_WUT : stm32f3xx_hal_rtc.h
  • RTC_MONTH_APRIL : stm32f3xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32f3xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32f3xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32f3xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32f3xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32f3xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32f3xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32f3xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32f3xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32f3xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32f3xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32f3xx_hal_rtc.h
  • RTC_OFFSET_DAY : stm32f3xx_ll_rtc.h
  • RTC_OFFSET_HOUR : stm32f3xx_ll_rtc.h
  • RTC_OFFSET_MINUTE : stm32f3xx_ll_rtc.h
  • RTC_OFFSET_MONTH : stm32f3xx_ll_rtc.h
  • RTC_OFFSET_WEEKDAY : stm32f3xx_ll_rtc.h
  • RTC_OUTPUT_ALARMA : stm32f3xx_hal_rtc_ex.h
  • RTC_OUTPUT_ALARMB : stm32f3xx_hal_rtc_ex.h
  • RTC_OUTPUT_DISABLE : stm32f3xx_hal_rtc_ex.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32f3xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32f3xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32f3xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32f3xx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32f3xx_hal_rtc_ex.h
  • RTC_RSF_MASK : stm32f3xx_hal_rtc.h , stm32f3xx_ll_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32f3xx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32f3xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32f3xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32f3xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32f3xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32f3xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32f3xx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32f3xx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32f3xx_hal_rtc.h
  • RTC_SYNCH_PRESC_DEFAULT : stm32f3xx_ll_rtc.c
  • RTC_SYNCHRO_TIMEOUT : stm32f3xx_ll_rtc.c
  • RTC_TAMPER_1 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPER_3 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32f3xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32f3xx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32f3xx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32f3xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32f3xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32f3xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32f3xx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32f3xx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32f3xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32f3xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32f3xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32f3xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32f3xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32f3xx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32f3xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32f3xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32f3xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32f3xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32f3xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32f3xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32f3xx_hal_rtc.h
  • RTC_WRITE_PROTECTION_DISABLE : stm32f3xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_1 : stm32f3xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_2 : stm32f3xx_ll_rtc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- s -

  • SDADC_CALIBRATION_SEQ_1 : stm32f3xx_hal_sdadc.h
  • SDADC_CALIBRATION_SEQ_2 : stm32f3xx_hal_sdadc.h
  • SDADC_CALIBRATION_SEQ_3 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_0 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_1 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_2 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_3 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_4 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_5 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_6 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_7 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_8 : stm32f3xx_hal_sdadc.h
  • SDADC_COMMON_MODE_VDDA : stm32f3xx_hal_sdadc.h
  • SDADC_COMMON_MODE_VDDA_2 : stm32f3xx_hal_sdadc.h
  • SDADC_COMMON_MODE_VSSA : stm32f3xx_hal_sdadc.h
  • SDADC_CONF_INDEX_0 : stm32f3xx_hal_sdadc.h
  • SDADC_CONF_INDEX_1 : stm32f3xx_hal_sdadc.h
  • SDADC_CONF_INDEX_2 : stm32f3xx_hal_sdadc.h
  • SDADC_CONFREG_OFFSET : stm32f3xx_hal_sdadc.c
  • SDADC_CONTINUOUS_CONV_OFF : stm32f3xx_hal_sdadc.h
  • SDADC_CONTINUOUS_CONV_ON : stm32f3xx_hal_sdadc.h
  • SDADC_DMAError() : stm32f3xx_hal_sdadc.c
  • SDADC_DMAInjectedConvCplt() : stm32f3xx_hal_sdadc.c
  • SDADC_DMAInjectedHalfConvCplt() : stm32f3xx_hal_sdadc.c
  • SDADC_DMARegularConvCplt() : stm32f3xx_hal_sdadc.c
  • SDADC_DMARegularHalfConvCplt() : stm32f3xx_hal_sdadc.c
  • SDADC_EnterInitMode() : stm32f3xx_hal_sdadc.c
  • SDADC_ERROR_DMA : stm32f3xx_hal_sdadc.h
  • SDADC_ERROR_INJECTED_OVERRUN : stm32f3xx_hal_sdadc.h
  • SDADC_ERROR_NONE : stm32f3xx_hal_sdadc.h
  • SDADC_ERROR_REGULAR_OVERRUN : stm32f3xx_hal_sdadc.h
  • SDADC_ExitInitMode() : stm32f3xx_hal_sdadc.c
  • SDADC_EXT_TRIG_BOTH_EDGES : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_EXTI11 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_EXTI15 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_FALLING_EDGE : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_RISING_EDGE : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM12_CC1 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM12_CC2 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM13_CC1 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM14_CC1 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM15_CC2 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM16_CC1 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM17_CC1 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM19_CC2 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM19_CC3 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM19_CC4 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM2_CC3 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM2_CC4 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM3_CC1 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM3_CC2 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM3_CC3 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM4_CC1 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM4_CC2 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM4_CC3 : stm32f3xx_hal_sdadc.h
  • SDADC_EXTERNAL_TRIGGER : stm32f3xx_hal_sdadc.h
  • SDADC_FAST_CONV_DISABLE : stm32f3xx_hal_sdadc.h
  • SDADC_FAST_CONV_ENABLE : stm32f3xx_hal_sdadc.h
  • SDADC_FLAG_EOCAL : stm32f3xx_hal_sdadc.h
  • SDADC_FLAG_JEOC : stm32f3xx_hal_sdadc.h
  • SDADC_FLAG_JOVR : stm32f3xx_hal_sdadc.h
  • SDADC_FLAG_REOC : stm32f3xx_hal_sdadc.h
  • SDADC_FLAG_ROVR : stm32f3xx_hal_sdadc.h
  • SDADC_GAIN_1 : stm32f3xx_hal_sdadc.h
  • SDADC_GAIN_16 : stm32f3xx_hal_sdadc.h
  • SDADC_GAIN_1_2 : stm32f3xx_hal_sdadc.h
  • SDADC_GAIN_2 : stm32f3xx_hal_sdadc.h
  • SDADC_GAIN_32 : stm32f3xx_hal_sdadc.h
  • SDADC_GAIN_4 : stm32f3xx_hal_sdadc.h
  • SDADC_GAIN_8 : stm32f3xx_hal_sdadc.h
  • SDADC_GetInjChannelsNbr() : stm32f3xx_hal_sdadc.c
  • SDADC_InjConvStart() : stm32f3xx_hal_sdadc.c
  • SDADC_InjConvStop() : stm32f3xx_hal_sdadc.c
  • SDADC_INJECTED_DELAY : stm32f3xx_hal_sdadc.h
  • SDADC_INJECTED_DELAY_NONE : stm32f3xx_hal_sdadc.h
  • SDADC_INPUT_MODE_DIFF : stm32f3xx_hal_sdadc.h
  • SDADC_INPUT_MODE_SE_OFFSET : stm32f3xx_hal_sdadc.h
  • SDADC_INPUT_MODE_SE_ZERO_REFERENCE : stm32f3xx_hal_sdadc.h
  • SDADC_IT_EOCAL : stm32f3xx_hal_sdadc.h
  • SDADC_IT_JEOC : stm32f3xx_hal_sdadc.h
  • SDADC_IT_JOVR : stm32f3xx_hal_sdadc.h
  • SDADC_IT_REOC : stm32f3xx_hal_sdadc.h
  • SDADC_IT_ROVR : stm32f3xx_hal_sdadc.h
  • SDADC_JDATAR_CH_OFFSET : stm32f3xx_hal_sdadc.c
  • SDADC_LOWPOWER_NONE : stm32f3xx_hal_sdadc.h
  • SDADC_LOWPOWER_POWERDOWN : stm32f3xx_hal_sdadc.h
  • SDADC_LOWPOWER_STANDBY : stm32f3xx_hal_sdadc.h
  • SDADC_LSB_MASK : stm32f3xx_hal_sdadc.c
  • SDADC_MSB_MASK : stm32f3xx_hal_sdadc.c
  • SDADC_MULTIMODE_SDADC1_SDADC2 : stm32f3xx_hal_sdadc.h
  • SDADC_MULTIMODE_SDADC1_SDADC3 : stm32f3xx_hal_sdadc.h
  • SDADC_RegConvStart() : stm32f3xx_hal_sdadc.c
  • SDADC_RegConvStop() : stm32f3xx_hal_sdadc.c
  • SDADC_SLOW_CLOCK_DISABLE : stm32f3xx_hal_sdadc.h
  • SDADC_SLOW_CLOCK_ENABLE : stm32f3xx_hal_sdadc.h
  • SDADC_SOFTWARE_TRIGGER : stm32f3xx_hal_sdadc.h
  • SDADC_SYNCHRONOUS_TRIGGER : stm32f3xx_hal_sdadc.h
  • SDADC_TIMEOUT : stm32f3xx_hal_sdadc.c
  • SDADC_VREF_EXT : stm32f3xx_hal_sdadc.h
  • SDADC_VREF_VDDA : stm32f3xx_hal_sdadc.h
  • SDADC_VREF_VREFINT1 : stm32f3xx_hal_sdadc.h
  • SDADC_VREF_VREFINT2 : stm32f3xx_hal_sdadc.h
  • SHIFT_TAB_CCxP : stm32f3xx_ll_tim.h
  • SHIFT_TAB_ICxx : stm32f3xx_ll_tim.h
  • SHIFT_TAB_OCxx : stm32f3xx_ll_tim.h
  • SHIFT_TAB_OISx : stm32f3xx_ll_tim.h
  • SlaveAddr_MSK : stm32f3xx_hal_i2c.c
  • SlaveAddr_SHIFT : stm32f3xx_hal_i2c.c
  • SMARTCARD_ADVFEATURE_DATAINV_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINV_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINVERT_INIT : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_INIT : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_NO_INIT : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINVERT_INIT : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_INIT : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINVERT_INIT : stm32f3xx_hal_smartcard.h
  • SMARTCARD_AdvFeatureConfig() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_CheckIdleState() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_CLEAR_EOBF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLEAR_FEF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLEAR_IDLEF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLEAR_NEF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLEAR_OREF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLEAR_PEF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLEAR_RTOF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLEAR_TCF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_HSI : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_LSE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK1 : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK2 : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_SYSCLK : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_UNDEFINED : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ClockSourceTypeDef : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CR3_SCARCNT_LSB_POS : stm32f3xx_hal_smartcard.h
  • SMARTCARD_DMAAbortOnError() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_DMAError() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_DMARxAbortCallback() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_DMARxOnlyAbortCallback() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_DMATxAbortCallback() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_DMATxOnlyAbortCallback() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_EndRxTransfer() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_EndTxTransfer() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_FLAG_BUSY : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_EOBF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_FE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_IDLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_NE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_ORE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_PE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_REACK : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_RTOF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_RXNE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_TC : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_TEACK : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_TXE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_GETCLOCKSOURCE : stm32f3xx_hal_smartcard_ex.h
  • SMARTCARD_GTPR_GT_LSB_POS : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_EOB : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_ERR : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_FE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_IDLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_MASK : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_NE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_ORE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_PE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_RTO : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_RXNE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_TC : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_TXE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32f3xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32f3xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32f3xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32f3xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32f3xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32f3xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32f3xx_hal_smartcard.h
  • SMARTCARD_Receive_IT() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_RTOR_BLEN_LSB_POS : stm32f3xx_hal_smartcard.h
  • SMARTCARD_RXDATA_FLUSH_REQUEST : stm32f3xx_hal_smartcard.h
  • SMARTCARD_SetConfig() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_STOPBITS_0_5 : stm32f3xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32f3xx_hal_smartcard.h
  • SMARTCARD_TEACK_REACK_TIMEOUT : stm32f3xx_hal_smartcard.c
  • SMARTCARD_TIMEOUT_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_Transmit_IT() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_TXDATA_FLUSH_REQUEST : stm32f3xx_hal_smartcard.h
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_WORDLENGTH_9B : stm32f3xx_hal_smartcard.h
  • SMBUS_ADDRESSINGMODE_10BIT : stm32f3xx_hal_smbus.h
  • SMBUS_ADDRESSINGMODE_7BIT : stm32f3xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_DISABLE : stm32f3xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_ENABLE : stm32f3xx_hal_smbus.h
  • SMBUS_AUTOEND_MODE : stm32f3xx_hal_smbus.h
  • SMBUS_CHECK_FLAG : stm32f3xx_hal_smbus.h
  • SMBUS_ConvertOtherXferOptions() : stm32f3xx_hal_smbus.c
  • SMBUS_Disable_IRQ() : stm32f3xx_hal_smbus.c
  • SMBUS_DUALADDRESS_DISABLE : stm32f3xx_hal_smbus.h
  • SMBUS_DUALADDRESS_ENABLE : stm32f3xx_hal_smbus.h
  • SMBUS_Enable_IRQ() : stm32f3xx_hal_smbus.c
  • SMBUS_FIRST_AND_LAST_FRAME_NO_PEC : stm32f3xx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC : stm32f3xx_hal_smbus.h
  • SMBUS_FIRST_FRAME : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_ADDR : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_AF : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_ALERT : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_ARLO : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_BERR : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_BUSY : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_DIR : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_MASK : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_OVR : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_PECERR : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_RXNE : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_STOPF : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_TC : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_TCR : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_TIMEOUT : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_TXE : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_TXIS : stm32f3xx_hal_smbus.h
  • SMBUS_GENERALCALL_DISABLE : stm32f3xx_hal_smbus.h
  • SMBUS_GENERALCALL_ENABLE : stm32f3xx_hal_smbus.h
  • SMBUS_GENERATE_START : stm32f3xx_hal_smbus.h
  • SMBUS_GENERATE_START_READ : stm32f3xx_hal_smbus.h
  • SMBUS_GENERATE_START_WRITE : stm32f3xx_hal_smbus.h
  • SMBUS_GENERATE_STOP : stm32f3xx_hal_smbus.h
  • SMBUS_GET_ADDR_MATCH : stm32f3xx_hal_smbus.h
  • SMBUS_GET_ALERT_ENABLED : stm32f3xx_hal_smbus.h
  • SMBUS_GET_DIR : stm32f3xx_hal_smbus.h
  • SMBUS_GET_ISR_REG : stm32f3xx_hal_smbus.h
  • SMBUS_GET_PEC_MODE : stm32f3xx_hal_smbus.h
  • SMBUS_GET_STOP_MODE : stm32f3xx_hal_smbus.h
  • SMBUS_IT_ADDR : stm32f3xx_hal_smbus.h
  • SMBUS_IT_ADDRI : stm32f3xx_hal_smbus.h
  • SMBUS_IT_ALERT : stm32f3xx_hal_smbus.h
  • SMBUS_IT_ERRI : stm32f3xx_hal_smbus.h
  • SMBUS_IT_NACKI : stm32f3xx_hal_smbus.h
  • SMBUS_IT_RX : stm32f3xx_hal_smbus.h
  • SMBUS_IT_RXI : stm32f3xx_hal_smbus.h
  • SMBUS_IT_STOPI : stm32f3xx_hal_smbus.h
  • SMBUS_IT_TCI : stm32f3xx_hal_smbus.h
  • SMBUS_IT_TX : stm32f3xx_hal_smbus.h
  • SMBUS_IT_TXI : stm32f3xx_hal_smbus.h
  • SMBUS_ITErrorHandler() : stm32f3xx_hal_smbus.c
  • SMBUS_LAST_FRAME_NO_PEC : stm32f3xx_hal_smbus.h
  • SMBUS_LAST_FRAME_WITH_PEC : stm32f3xx_hal_smbus.h
  • SMBUS_Master_ISR() : stm32f3xx_hal_smbus.c
  • SMBUS_NEXT_FRAME : stm32f3xx_hal_smbus.h
  • SMBUS_NO_STARTSTOP : stm32f3xx_hal_smbus.h
  • SMBUS_NOSTRETCH_DISABLE : stm32f3xx_hal_smbus.h
  • SMBUS_NOSTRETCH_ENABLE : stm32f3xx_hal_smbus.h
  • SMBUS_OA2_MASK01 : stm32f3xx_hal_smbus.h
  • SMBUS_OA2_MASK02 : stm32f3xx_hal_smbus.h
  • SMBUS_OA2_MASK03 : stm32f3xx_hal_smbus.h
  • SMBUS_OA2_MASK04 : stm32f3xx_hal_smbus.h
  • SMBUS_OA2_MASK05 : stm32f3xx_hal_smbus.h
  • SMBUS_OA2_MASK06 : stm32f3xx_hal_smbus.h
  • SMBUS_OA2_MASK07 : stm32f3xx_hal_smbus.h
  • SMBUS_OA2_NOMASK : stm32f3xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_NO_PEC : stm32f3xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC : stm32f3xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_NO_PEC : stm32f3xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_WITH_PEC : stm32f3xx_hal_smbus.h
  • SMBUS_PEC_DISABLE : stm32f3xx_hal_smbus.h
  • SMBUS_PEC_ENABLE : stm32f3xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_HOST : stm32f3xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE : stm32f3xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP : stm32f3xx_hal_smbus.h
  • SMBUS_RELOAD_MODE : stm32f3xx_hal_smbus.h
  • SMBUS_RESET_CR1 : stm32f3xx_hal_smbus.h
  • SMBUS_RESET_CR2 : stm32f3xx_hal_smbus.h
  • SMBUS_SENDPEC_MODE : stm32f3xx_hal_smbus.h
  • SMBUS_Slave_ISR() : stm32f3xx_hal_smbus.c
  • SMBUS_SOFTEND_MODE : stm32f3xx_hal_smbus.h
  • SMBUS_TransferConfig() : stm32f3xx_hal_smbus.c
  • SMBUS_WaitOnFlagUntilTimeout() : stm32f3xx_hal_smbus.c
  • SPI_1LINE_RX : stm32f3xx_hal_spi.h
  • SPI_1LINE_TX : stm32f3xx_hal_spi.h
  • SPI_2linesRxISR_16BIT() : stm32f3xx_hal_spi.c
  • SPI_2linesRxISR_16BITCRC() : stm32f3xx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32f3xx_hal_spi.c
  • SPI_2linesRxISR_8BITCRC() : stm32f3xx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32f3xx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32f3xx_hal_spi.c
  • SPI_AbortRx_ISR() : stm32f3xx_hal_spi.c
  • SPI_AbortTx_ISR() : stm32f3xx_hal_spi.c
  • SPI_BAUDRATEPRESCALER_128 : stm32f3xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32f3xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32f3xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32f3xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32f3xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32f3xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32f3xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32f3xx_hal_spi.h
  • SPI_CloseRx_ISR() : stm32f3xx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32f3xx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32f3xx_hal_spi.c
  • SPI_CR1_CLEAR_MASK : stm32f3xx_ll_spi.c
  • SPI_CRC_LENGTH_16BIT : stm32f3xx_hal_spi.h
  • SPI_CRC_LENGTH_8BIT : stm32f3xx_hal_spi.h
  • SPI_CRC_LENGTH_DATASIZE : stm32f3xx_hal_spi.h
  • SPI_CRCCALCULATION_DISABLE : stm32f3xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_10BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_11BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_12BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_13BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_14BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_15BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_4BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_5BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_6BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_7BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_9BIT : stm32f3xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32f3xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32f3xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32f3xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32f3xx_hal_spi.h
  • SPI_DMAAbortOnError() : stm32f3xx_hal_spi.c
  • SPI_DMAError() : stm32f3xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32f3xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32f3xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32f3xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32f3xx_hal_spi.c
  • SPI_DMARxAbortCallback() : stm32f3xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32f3xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32f3xx_hal_spi.c
  • SPI_DMATxAbortCallback() : stm32f3xx_hal_spi.c
  • SPI_EndRxTransaction() : stm32f3xx_hal_spi.c
  • SPI_EndRxTxTransaction() : stm32f3xx_hal_spi.c
  • SPI_FIFO_SIZE : stm32f3xx_hal_spi_ex.c
  • SPI_FIRSTBIT_LSB : stm32f3xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32f3xx_hal_spi.h
  • SPI_FLAG_BSY : stm32f3xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32f3xx_hal_spi.h
  • SPI_FLAG_FRE : stm32f3xx_hal_spi.h
  • SPI_FLAG_FRLVL : stm32f3xx_hal_spi.h
  • SPI_FLAG_FTLVL : stm32f3xx_hal_spi.h
  • SPI_FLAG_MODF : stm32f3xx_hal_spi.h
  • SPI_FLAG_OVR : stm32f3xx_hal_spi.h
  • SPI_FLAG_RXNE : stm32f3xx_hal_spi.h
  • SPI_FLAG_TXE : stm32f3xx_hal_spi.h
  • SPI_FRLVL_EMPTY : stm32f3xx_hal_spi.h
  • SPI_FRLVL_FULL : stm32f3xx_hal_spi.h
  • SPI_FRLVL_HALF_FULL : stm32f3xx_hal_spi.h
  • SPI_FRLVL_QUARTER_FULL : stm32f3xx_hal_spi.h
  • SPI_FTLVL_EMPTY : stm32f3xx_hal_spi.h
  • SPI_FTLVL_FULL : stm32f3xx_hal_spi.h
  • SPI_FTLVL_HALF_FULL : stm32f3xx_hal_spi.h
  • SPI_FTLVL_QUARTER_FULL : stm32f3xx_hal_spi.h
  • SPI_HandleTypeDef : stm32f3xx_hal_spi.h
  • SPI_IT_ERR : stm32f3xx_hal_spi.h
  • SPI_IT_RXNE : stm32f3xx_hal_spi.h
  • SPI_IT_TXE : stm32f3xx_hal_spi.h
  • SPI_MODE_MASTER : stm32f3xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32f3xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32f3xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32f3xx_hal_spi.h
  • SPI_NSS_PULSE_DISABLE : stm32f3xx_hal_spi.h
  • SPI_NSS_PULSE_ENABLE : stm32f3xx_hal_spi.h
  • SPI_NSS_SOFT : stm32f3xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32f3xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32f3xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32f3xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32f3xx_hal_spi.h
  • SPI_RESET_CRC : stm32f3xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD : stm32f3xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_HF : stm32f3xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_QF : stm32f3xx_hal_spi.h
  • SPI_RxISR_16BIT() : stm32f3xx_hal_spi.c
  • SPI_RxISR_16BITCRC() : stm32f3xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32f3xx_hal_spi.c
  • SPI_RxISR_8BITCRC() : stm32f3xx_hal_spi.c
  • SPI_TIMODE_DISABLE : stm32f3xx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32f3xx_hal_spi.h
  • SPI_TxISR_16BIT() : stm32f3xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32f3xx_hal_spi.c
  • SPI_WaitFifoStateUntilTimeout() : stm32f3xx_hal_spi.c
  • SPI_WaitFlagStateUntilTimeout() : stm32f3xx_hal_spi.c
  • SYSCFG_FASTMODEPLUS_PB6 : stm32f3xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB7 : stm32f3xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB8 : stm32f3xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB9 : stm32f3xx_hal.h
  • SYSCFG_MASK_TIM_BREAK : stm32f3xx_ll_system.h
  • SYSCFG_OFFSET : stm32f3xx_hal.h
  • SYSCFG_OFFSET_CFGR1 : stm32f3xx_ll_system.h
  • SYSCFG_OFFSET_CFGR3 : stm32f3xx_ll_system.h
  • SYSTICK_CLKSOURCE_HCLK : stm32f3xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32f3xx_hal_cortex.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- t -

  • TEMPSENSOR_CAL1_ADDR : stm32f3xx_ll_adc.h
  • TEMPSENSOR_CAL1_TEMP : stm32f3xx_ll_adc.h
  • TEMPSENSOR_CAL2_ADDR : stm32f3xx_ll_adc.h
  • TEMPSENSOR_CAL2_TEMP : stm32f3xx_ll_adc.h
  • TEMPSENSOR_CAL_VREFANALOG : stm32f3xx_ll_adc.h
  • TICK_INT_PRIORITY : stm32f3xx_hal_conf.h
  • TIM14_OR_RMP_MASK : stm32f3xx_ll_tim.h
  • TIM16_OR_RMP_MASK : stm32f3xx_ll_tim.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32f3xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32f3xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_DISABLE : stm32f3xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_ENABLE : stm32f3xx_hal_tim.h
  • TIM_Base_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_BREAK_DISABLE : stm32f3xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32f3xx_hal_tim.h
  • TIM_BREAKPOLARITY_HIGH : stm32f3xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32f3xx_hal_tim.h
  • TIM_CALC_DTS : stm32f3xx_ll_tim.h
  • TIM_CCER_CCxE_MASK : stm32f3xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32f3xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32f3xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32f3xx_hal_tim.h
  • TIM_CCxChannelCmd() : stm32f3xx_hal_tim.c
  • TIM_CCxN_DISABLE : stm32f3xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32f3xx_hal_tim.h
  • TIM_CCxNChannelCmd() : stm32f3xx_hal_tim_ex.c
  • TIM_CHANNEL_1 : stm32f3xx_hal_tim_ex.h
  • TIM_CHANNEL_2 : stm32f3xx_hal_tim_ex.h
  • TIM_CHANNEL_3 : stm32f3xx_hal_tim_ex.h
  • TIM_CHANNEL_4 : stm32f3xx_hal_tim_ex.h
  • TIM_CHANNEL_ALL : stm32f3xx_hal_tim_ex.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32f3xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32f3xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32f3xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32f3xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32f3xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32f3xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32f3xx_hal_tim_ex.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32f3xx_hal_tim_ex.h
  • TIM_CLOCKDIVISION_DIV1 : stm32f3xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32f3xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32f3xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32f3xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32f3xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32f3xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32f3xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32f3xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32f3xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32f3xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32f3xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32f3xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32f3xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32f3xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32f3xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32f3xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32f3xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32f3xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32f3xx_hal_tim.h
  • TIM_DMA_CC1 : stm32f3xx_hal_tim.h
  • TIM_DMA_CC2 : stm32f3xx_hal_tim.h
  • TIM_DMA_CC3 : stm32f3xx_hal_tim.h
  • TIM_DMA_CC4 : stm32f3xx_hal_tim.h
  • TIM_DMA_COM : stm32f3xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32f3xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32f3xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32f3xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32f3xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32f3xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32f3xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32f3xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32f3xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32f3xx_hal_tim.h
  • TIM_DMABASE_ARR : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_BDTR : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CCER : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CCMR1 : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CCMR2 : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CCR1 : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CCR2 : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CCR3 : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CCR4 : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CNT : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CR1 : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CR2 : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_DCR : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_DIER : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_EGR : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_OR : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_PSC : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_RCR : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_SMCR : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_SR : stm32f3xx_hal_tim_ex.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMACaptureCplt() : stm32f3xx_hal_tim.c
  • TIM_DMADelayPulseCplt() : stm32f3xx_hal_tim.c
  • TIM_DMAError() : stm32f3xx_hal_tim.c
  • TIM_DMAPeriodElapsedCplt() : stm32f3xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32f3xx_hal_tim.c
  • TIM_ENCODERMODE_TI1 : stm32f3xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32f3xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32f3xx_hal_tim.h
  • TIM_ETR_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_ETRPOLARITY_INVERTED : stm32f3xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32f3xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32f3xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32f3xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32f3xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32f3xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32f3xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_CC1 : stm32f3xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_CC2 : stm32f3xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_CC3 : stm32f3xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_CC4 : stm32f3xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_COM : stm32f3xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_TRIGGER : stm32f3xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_UPDATE : stm32f3xx_hal_tim_ex.h
  • TIM_FLAG_BREAK : stm32f3xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32f3xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32f3xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32f3xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32f3xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32f3xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32f3xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32f3xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32f3xx_hal_tim.h
  • TIM_FLAG_COM : stm32f3xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32f3xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32f3xx_hal_tim.h
  • TIM_GET_CHANNEL_INDEX : stm32f3xx_ll_tim.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32f3xx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32f3xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32f3xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32f3xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32f3xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32f3xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32f3xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32f3xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32f3xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32f3xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32f3xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32f3xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32f3xx_hal_tim.h
  • TIM_IT_BREAK : stm32f3xx_hal_tim.h
  • TIM_IT_CC1 : stm32f3xx_hal_tim.h
  • TIM_IT_CC2 : stm32f3xx_hal_tim.h
  • TIM_IT_CC3 : stm32f3xx_hal_tim.h
  • TIM_IT_CC4 : stm32f3xx_hal_tim.h
  • TIM_IT_COM : stm32f3xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32f3xx_hal_tim.h
  • TIM_IT_UPDATE : stm32f3xx_hal_tim.h
  • TIM_ITRx_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_LOCKLEVEL_1 : stm32f3xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32f3xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32f3xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32f3xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32f3xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32f3xx_hal_tim.h
  • TIM_OC1_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_OC2_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_OC3_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_OCFAST_DISABLE : stm32f3xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32f3xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32f3xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32f3xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32f3xx_hal_tim_ex.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32f3xx_hal_tim_ex.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32f3xx_hal_tim_ex.h
  • TIM_OCMODE_INACTIVE : stm32f3xx_hal_tim_ex.h
  • TIM_OCMODE_PWM1 : stm32f3xx_hal_tim_ex.h
  • TIM_OCMODE_PWM2 : stm32f3xx_hal_tim_ex.h
  • TIM_OCMODE_TIMING : stm32f3xx_hal_tim_ex.h
  • TIM_OCMODE_TOGGLE : stm32f3xx_hal_tim_ex.h
  • TIM_OCNIDLESTATE_RESET : stm32f3xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32f3xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32f3xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32f3xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32f3xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32f3xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32f3xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32f3xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32f3xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32f3xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32f3xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32f3xx_hal_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32f3xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32f3xx_hal_tim.h
  • TIM_SET_CAPTUREPOLARITY : stm32f3xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32f3xx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32f3xx_hal_tim_ex.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32f3xx_hal_tim_ex.h
  • TIM_SLAVEMODE_GATED : stm32f3xx_hal_tim_ex.h
  • TIM_SLAVEMODE_RESET : stm32f3xx_hal_tim_ex.h
  • TIM_SLAVEMODE_TRIGGER : stm32f3xx_hal_tim_ex.h
  • TIM_SlaveTimer_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32f3xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_TI1SELECTION_CH1 : stm32f3xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32f3xx_hal_tim.h
  • TIM_TI2_ConfigInputStage() : stm32f3xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_TIM14_GPIO : stm32f3xx_hal_tim_ex.h
  • TIM_TIM14_HSE : stm32f3xx_hal_tim_ex.h
  • TIM_TIM14_MCO : stm32f3xx_hal_tim_ex.h
  • TIM_TIM14_RTC : stm32f3xx_hal_tim_ex.h
  • TIM_TIM2_ETH_PTP : stm32f3xx_hal_tim_ex.h
  • TIM_TIM2_TIM8_TRGO : stm32f3xx_hal_tim_ex.h
  • TIM_TIM2_USBFS_SOF : stm32f3xx_hal_tim_ex.h
  • TIM_TIM2_USBHS_SOF : stm32f3xx_hal_tim_ex.h
  • TIM_TRGO_ENABLE : stm32f3xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32f3xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32f3xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32f3xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32f3xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32f3xx_hal_tim.h
  • TIM_TRGO_RESET : stm32f3xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32f3xx_hal_tim.h
  • TIM_TS_ETRF : stm32f3xx_hal_tim.h
  • TIM_TS_ITR0 : stm32f3xx_hal_tim.h
  • TIM_TS_ITR1 : stm32f3xx_hal_tim.h
  • TIM_TS_ITR2 : stm32f3xx_hal_tim.h
  • TIM_TS_ITR3 : stm32f3xx_hal_tim.h
  • TIM_TS_NONE : stm32f3xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32f3xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32f3xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32f3xx_hal_tim.h
  • TIMEx_DMACommutationCplt() : stm32f3xx_hal_tim_ex.c
  • TIMING_CLEAR_MASK : stm32f3xx_hal_i2c.c , stm32f3xx_hal_smbus.c
  • TIMx_OR_RMP_MASK : stm32f3xx_ll_tim.h
  • TIMx_OR_RMP_SHIFT : stm32f3xx_ll_tim.h
  • TSC_ACQ_MODE_NORMAL : stm32f3xx_hal_tsc.h
  • TSC_ACQ_MODE_SYNCHRO : stm32f3xx_hal_tsc.h
  • TSC_ALL_GROUPS : stm32f3xx_hal_tsc.h
  • TSC_ALL_GROUPS_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_CTPH_10CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_11CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_12CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_13CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_14CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_15CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_16CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_1CYCLE : stm32f3xx_hal_tsc.h
  • TSC_CTPH_2CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_3CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_4CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_5CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_6CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_7CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_8CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_9CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_10CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_11CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_12CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_13CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_14CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_15CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_16CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_1CYCLE : stm32f3xx_hal_tsc.h
  • TSC_CTPL_2CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_3CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_4CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_5CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_6CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_7CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_8CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_9CYCLES : stm32f3xx_hal_tsc.h
  • TSC_extract_groups() : stm32f3xx_hal_tsc.c
  • TSC_FLAG_EOA : stm32f3xx_hal_tsc.h
  • TSC_FLAG_MCE : stm32f3xx_hal_tsc.h
  • TSC_GROUP1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP1_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_GROUP1_IDX : stm32f3xx_hal_tsc.h
  • TSC_GROUP1_IO1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP1_IO2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP1_IO3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP1_IO4 : stm32f3xx_hal_tsc.h
  • TSC_GROUP2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP2_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_GROUP2_IDX : stm32f3xx_hal_tsc.h
  • TSC_GROUP2_IO1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP2_IO2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP2_IO3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP2_IO4 : stm32f3xx_hal_tsc.h
  • TSC_GROUP3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP3_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_GROUP3_IDX : stm32f3xx_hal_tsc.h
  • TSC_GROUP3_IO1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP3_IO2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP3_IO3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP3_IO4 : stm32f3xx_hal_tsc.h
  • TSC_GROUP4 : stm32f3xx_hal_tsc.h
  • TSC_GROUP4_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_GROUP4_IDX : stm32f3xx_hal_tsc.h
  • TSC_GROUP4_IO1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP4_IO2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP4_IO3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP4_IO4 : stm32f3xx_hal_tsc.h
  • TSC_GROUP5 : stm32f3xx_hal_tsc.h
  • TSC_GROUP5_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_GROUP5_IDX : stm32f3xx_hal_tsc.h
  • TSC_GROUP5_IO1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP5_IO2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP5_IO3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP5_IO4 : stm32f3xx_hal_tsc.h
  • TSC_GROUP6 : stm32f3xx_hal_tsc.h
  • TSC_GROUP6_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_GROUP6_IDX : stm32f3xx_hal_tsc.h
  • TSC_GROUP6_IO1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP6_IO2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP6_IO3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP6_IO4 : stm32f3xx_hal_tsc.h
  • TSC_GROUP7 : stm32f3xx_hal_tsc.h
  • TSC_GROUP7_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_GROUP7_IDX : stm32f3xx_hal_tsc.h
  • TSC_GROUP7_IO1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP7_IO2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP7_IO3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP7_IO4 : stm32f3xx_hal_tsc.h
  • TSC_GROUP8 : stm32f3xx_hal_tsc.h
  • TSC_GROUP8_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_GROUP8_IDX : stm32f3xx_hal_tsc.h
  • TSC_GROUP8_IO1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP8_IO2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP8_IO3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP8_IO4 : stm32f3xx_hal_tsc.h
  • TSC_GROUP_COMPLETED : stm32f3xx_hal_tsc.h
  • TSC_GROUP_ONGOING : stm32f3xx_hal_tsc.h
  • TSC_GroupStatusTypeDef : stm32f3xx_hal_tsc.h
  • TSC_IODEF_IN_FLOAT : stm32f3xx_hal_tsc.h
  • TSC_IODEF_OUT_PP_LOW : stm32f3xx_hal_tsc.h
  • TSC_IOMODE_CHANNEL : stm32f3xx_hal_tsc.h
  • TSC_IOMODE_SAMPLING : stm32f3xx_hal_tsc.h
  • TSC_IOMODE_SHIELD : stm32f3xx_hal_tsc.h
  • TSC_IOMODE_UNUSED : stm32f3xx_hal_tsc.h
  • TSC_IT_EOA : stm32f3xx_hal_tsc.h
  • TSC_IT_MCE : stm32f3xx_hal_tsc.h
  • TSC_MCV_1023 : stm32f3xx_hal_tsc.h
  • TSC_MCV_16383 : stm32f3xx_hal_tsc.h
  • TSC_MCV_2047 : stm32f3xx_hal_tsc.h
  • TSC_MCV_255 : stm32f3xx_hal_tsc.h
  • TSC_MCV_4095 : stm32f3xx_hal_tsc.h
  • TSC_MCV_511 : stm32f3xx_hal_tsc.h
  • TSC_MCV_8191 : stm32f3xx_hal_tsc.h
  • TSC_NB_OF_GROUPS : stm32f3xx_hal_tsc.h
  • TSC_PG_PRESC_DIV1 : stm32f3xx_hal_tsc.h
  • TSC_PG_PRESC_DIV128 : stm32f3xx_hal_tsc.h
  • TSC_PG_PRESC_DIV16 : stm32f3xx_hal_tsc.h
  • TSC_PG_PRESC_DIV2 : stm32f3xx_hal_tsc.h
  • TSC_PG_PRESC_DIV32 : stm32f3xx_hal_tsc.h
  • TSC_PG_PRESC_DIV4 : stm32f3xx_hal_tsc.h
  • TSC_PG_PRESC_DIV64 : stm32f3xx_hal_tsc.h
  • TSC_PG_PRESC_DIV8 : stm32f3xx_hal_tsc.h
  • TSC_SS_PRESC_DIV1 : stm32f3xx_hal_tsc.h
  • TSC_SS_PRESC_DIV2 : stm32f3xx_hal_tsc.h
  • TSC_SYNC_POLARITY_FALLING : stm32f3xx_hal_tsc.h
  • TSC_SYNC_POLARITY_RISING : stm32f3xx_hal_tsc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • h
  • i
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- u -

  • UART_ADDRESS_DETECT_4B : stm32f3xx_hal_uart.h
  • UART_ADDRESS_DETECT_7B : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_INIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_DATAINVERT_INIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_DMA_DISABLEONRXERROR : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_DMA_ENABLEONRXERROR : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_DMADISABLEONERROR_INIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_INIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_NO_INIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_RXINVERT_INIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_INIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_TXINVERT_INIT : stm32f3xx_hal_uart.h
  • UART_AdvFeatureConfig() : stm32f3xx_hal_uart.c
  • UART_AUTOBAUD_REQUEST : stm32f3xx_hal_uart.h
  • UART_CheckIdleState() : stm32f3xx_hal_uart.c
  • UART_CLEAR_CMF : stm32f3xx_hal_uart.h
  • UART_CLEAR_CTSF : stm32f3xx_hal_uart.h
  • UART_CLEAR_EOBF : stm32f3xx_hal_uart.h
  • UART_CLEAR_FEF : stm32f3xx_hal_uart.h
  • UART_CLEAR_IDLEF : stm32f3xx_hal_uart.h
  • UART_CLEAR_LBDF : stm32f3xx_hal_uart.h
  • UART_CLEAR_NEF : stm32f3xx_hal_uart.h
  • UART_CLEAR_OREF : stm32f3xx_hal_uart.h
  • UART_CLEAR_PEF : stm32f3xx_hal_uart.h
  • UART_CLEAR_RTOF : stm32f3xx_hal_uart.h
  • UART_CLEAR_TCF : stm32f3xx_hal_uart.h
  • UART_CLEAR_WUF : stm32f3xx_hal_uart.h
  • UART_CLOCKSOURCE_HSI : stm32f3xx_hal_uart.h
  • UART_CLOCKSOURCE_LSE : stm32f3xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK1 : stm32f3xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK2 : stm32f3xx_hal_uart.h
  • UART_CLOCKSOURCE_SYSCLK : stm32f3xx_hal_uart.h
  • UART_CLOCKSOURCE_UNDEFINED : stm32f3xx_hal_uart.h
  • UART_ClockSourceTypeDef : stm32f3xx_hal_uart.h
  • UART_CR1_DEAT_ADDRESS_LSB_POS : stm32f3xx_hal_uart.h
  • UART_CR1_DEDT_ADDRESS_LSB_POS : stm32f3xx_hal_uart.h
  • UART_CR1_FIELDS : stm32f3xx_hal_uart.c
  • UART_CR2_ADDRESS_LSB_POS : stm32f3xx_hal_uart.h
  • UART_DE_POLARITY_HIGH : stm32f3xx_hal_uart.h
  • UART_DE_POLARITY_LOW : stm32f3xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32f3xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32f3xx_hal_uart.h
  • UART_DMA_RX_DISABLE : stm32f3xx_hal_uart.h
  • UART_DMA_RX_ENABLE : stm32f3xx_hal_uart.h
  • UART_DMA_TX_DISABLE : stm32f3xx_hal_uart.h
  • UART_DMA_TX_ENABLE : stm32f3xx_hal_uart.h
  • UART_DMAAbortOnError() : stm32f3xx_hal_uart.c
  • UART_DMAError() : stm32f3xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32f3xx_hal_uart.c
  • UART_DMARxAbortCallback() : stm32f3xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32f3xx_hal_uart.c
  • UART_DMARxOnlyAbortCallback() : stm32f3xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32f3xx_hal_uart.c
  • UART_DMATxAbortCallback() : stm32f3xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32f3xx_hal_uart.c
  • UART_DMATxOnlyAbortCallback() : stm32f3xx_hal_uart.c
  • UART_EndRxTransfer() : stm32f3xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32f3xx_hal_uart.c
  • UART_EndTxTransfer() : stm32f3xx_hal_uart.c
  • UART_FLAG_ABRE : stm32f3xx_hal_uart.h
  • UART_FLAG_ABRF : stm32f3xx_hal_uart.h
  • UART_FLAG_BUSY : stm32f3xx_hal_uart.h
  • UART_FLAG_CMF : stm32f3xx_hal_uart.h
  • UART_FLAG_CTS : stm32f3xx_hal_uart.h
  • UART_FLAG_CTSIF : stm32f3xx_hal_uart.h
  • UART_FLAG_EOBF : stm32f3xx_hal_uart.h
  • UART_FLAG_FE : stm32f3xx_hal_uart.h
  • UART_FLAG_IDLE : stm32f3xx_hal_uart.h
  • UART_FLAG_LBDF : stm32f3xx_hal_uart.h
  • UART_FLAG_NE : stm32f3xx_hal_uart.h
  • UART_FLAG_ORE : stm32f3xx_hal_uart.h
  • UART_FLAG_PE : stm32f3xx_hal_uart.h
  • UART_FLAG_REACK : stm32f3xx_hal_uart.h
  • UART_FLAG_RTOF : stm32f3xx_hal_uart.h
  • UART_FLAG_RWU : stm32f3xx_hal_uart.h
  • UART_FLAG_RXNE : stm32f3xx_hal_uart.h
  • UART_FLAG_SBKF : stm32f3xx_hal_uart.h
  • UART_FLAG_TC : stm32f3xx_hal_uart.h
  • UART_FLAG_TEACK : stm32f3xx_hal_uart.h
  • UART_FLAG_TXE : stm32f3xx_hal_uart.h
  • UART_FLAG_WUF : stm32f3xx_hal_uart.h
  • UART_GETCLOCKSOURCE : stm32f3xx_hal_uart_ex.h
  • UART_HALF_DUPLEX_DISABLE : stm32f3xx_hal_uart.h
  • UART_HALF_DUPLEX_ENABLE : stm32f3xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32f3xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32f3xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32f3xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32f3xx_hal_uart.h
  • UART_IT_CM : stm32f3xx_hal_uart.h
  • UART_IT_CTS : stm32f3xx_hal_uart.h
  • UART_IT_ERR : stm32f3xx_hal_uart.h
  • UART_IT_FE : stm32f3xx_hal_uart.h
  • UART_IT_IDLE : stm32f3xx_hal_uart.h
  • UART_IT_LBD : stm32f3xx_hal_uart.h
  • UART_IT_MASK : stm32f3xx_hal_uart.h
  • UART_IT_NE : stm32f3xx_hal_uart.h
  • UART_IT_ORE : stm32f3xx_hal_uart.h
  • UART_IT_PE : stm32f3xx_hal_uart.h
  • UART_IT_RXNE : stm32f3xx_hal_uart.h
  • UART_IT_TC : stm32f3xx_hal_uart.h
  • UART_IT_TXE : stm32f3xx_hal_uart.h
  • UART_IT_WUF : stm32f3xx_hal_uart.h
  • UART_LIN_DISABLE : stm32f3xx_hal_uart.h
  • UART_LIN_ENABLE : stm32f3xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32f3xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32f3xx_hal_uart.h
  • UART_MASK_COMPUTATION : stm32f3xx_hal_uart_ex.h
  • UART_MODE_RX : stm32f3xx_hal_uart.h
  • UART_MODE_TX : stm32f3xx_hal_uart.h
  • UART_MODE_TX_RX : stm32f3xx_hal_uart.h
  • UART_MUTE_MODE_REQUEST : stm32f3xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_DISABLE : stm32f3xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_ENABLE : stm32f3xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32f3xx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32f3xx_hal_uart.h
  • UART_PARITY_EVEN : stm32f3xx_hal_uart.h
  • UART_PARITY_NONE : stm32f3xx_hal_uart.h
  • UART_PARITY_ODD : stm32f3xx_hal_uart.h
  • UART_Receive_IT() : stm32f3xx_hal_uart.c
  • UART_RECEIVER_TIMEOUT_DISABLE : stm32f3xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_ENABLE : stm32f3xx_hal_uart.h
  • UART_RXDATA_FLUSH_REQUEST : stm32f3xx_hal_uart.h
  • UART_SENDBREAK_REQUEST : stm32f3xx_hal_uart.h
  • UART_SetConfig() : stm32f3xx_hal_uart.c
  • UART_STATE_DISABLE : stm32f3xx_hal_uart.h
  • UART_STATE_ENABLE : stm32f3xx_hal_uart.h
  • UART_STOPBITS_0_5 : stm32f3xx_hal_uart.h
  • UART_STOPBITS_1 : stm32f3xx_hal_uart.h
  • UART_STOPBITS_1_5 : stm32f3xx_hal_uart.h
  • UART_STOPBITS_2 : stm32f3xx_hal_uart.h
  • UART_Transmit_IT() : stm32f3xx_hal_uart.c
  • UART_TXDATA_FLUSH_REQUEST : stm32f3xx_hal_uart.h
  • UART_WaitOnFlagUntilTimeout() : stm32f3xx_hal_uart.c
  • UART_Wakeup_AddressConfig() : stm32f3xx_hal_uart.c
  • UART_WAKEUP_ON_ADDRESS : stm32f3xx_hal_uart.h
  • UART_WAKEUP_ON_READDATA_NONEMPTY : stm32f3xx_hal_uart.h
  • UART_WAKEUP_ON_STARTBIT : stm32f3xx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32f3xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32f3xx_hal_uart.h
  • UART_WORDLENGTH_8B : stm32f3xx_hal_uart_ex.h
  • UART_WORDLENGTH_9B : stm32f3xx_hal_uart_ex.h
  • UID_BASE_ADDRESS : stm32f3xx_ll_utils.h
  • USART_CheckIdleState() : stm32f3xx_hal_usart.c
  • USART_CLEAR_CTSF : stm32f3xx_hal_usart.h
  • USART_CLEAR_FEF : stm32f3xx_hal_usart.h
  • USART_CLEAR_IDLEF : stm32f3xx_hal_usart.h
  • USART_CLEAR_NEF : stm32f3xx_hal_usart.h
  • USART_CLEAR_OREF : stm32f3xx_hal_usart.h
  • USART_CLEAR_PEF : stm32f3xx_hal_usart.h
  • USART_CLEAR_TCF : stm32f3xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32f3xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32f3xx_hal_usart.h
  • USART_CLOCKSOURCE_HSI : stm32f3xx_hal_usart.h
  • USART_CLOCKSOURCE_LSE : stm32f3xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK1 : stm32f3xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK2 : stm32f3xx_hal_usart.h
  • USART_CLOCKSOURCE_SYSCLK : stm32f3xx_hal_usart.h
  • USART_CLOCKSOURCE_UNDEFINED : stm32f3xx_hal_usart.h
  • USART_ClockSourceTypeDef : stm32f3xx_hal_usart.h
  • USART_CR1_FIELDS : stm32f3xx_hal_smartcard.c , stm32f3xx_hal_usart.c
  • USART_CR2_CLK_FIELDS : stm32f3xx_hal_smartcard.c
  • USART_CR2_FIELDS : stm32f3xx_hal_smartcard.c , stm32f3xx_hal_usart.c
  • USART_CR3_FIELDS : stm32f3xx_hal_smartcard.c
  • USART_DMAAbortOnError() : stm32f3xx_hal_usart.c
  • USART_DMAError() : stm32f3xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32f3xx_hal_usart.c
  • USART_DMARxAbortCallback() : stm32f3xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32f3xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32f3xx_hal_usart.c
  • USART_DMATxAbortCallback() : stm32f3xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32f3xx_hal_usart.c
  • USART_DUMMY_DATA : stm32f3xx_hal_usart.c
  • USART_EndTransfer() : stm32f3xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32f3xx_hal_usart.c
  • USART_FLAG_BUSY : stm32f3xx_hal_usart.h
  • USART_FLAG_CTS : stm32f3xx_hal_usart.h
  • USART_FLAG_CTSIF : stm32f3xx_hal_usart.h
  • USART_FLAG_FE : stm32f3xx_hal_usart.h
  • USART_FLAG_IDLE : stm32f3xx_hal_usart.h
  • USART_FLAG_LBDF : stm32f3xx_hal_usart.h
  • USART_FLAG_NE : stm32f3xx_hal_usart.h
  • USART_FLAG_ORE : stm32f3xx_hal_usart.h
  • USART_FLAG_PE : stm32f3xx_hal_usart.h
  • USART_FLAG_REACK : stm32f3xx_hal_usart.h
  • USART_FLAG_RXNE : stm32f3xx_hal_usart.h
  • USART_FLAG_TC : stm32f3xx_hal_usart.h
  • USART_FLAG_TEACK : stm32f3xx_hal_usart.h
  • USART_FLAG_TXE : stm32f3xx_hal_usart.h
  • USART_GETCLOCKSOURCE : stm32f3xx_hal_usart_ex.h
  • USART_IT_ERR : stm32f3xx_hal_usart.h
  • USART_IT_FE : stm32f3xx_hal_usart.h
  • USART_IT_IDLE : stm32f3xx_hal_usart.h
  • USART_IT_MASK : stm32f3xx_hal_usart.h
  • USART_IT_NE : stm32f3xx_hal_usart.h
  • USART_IT_ORE : stm32f3xx_hal_usart.h
  • USART_IT_PE : stm32f3xx_hal_usart.h
  • USART_IT_RXNE : stm32f3xx_hal_usart.h
  • USART_IT_TC : stm32f3xx_hal_usart.h
  • USART_IT_TXE : stm32f3xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32f3xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32f3xx_hal_usart.h
  • USART_MASK_COMPUTATION : stm32f3xx_hal_usart_ex.h
  • USART_MODE_RX : stm32f3xx_hal_usart.h
  • USART_MODE_TX : stm32f3xx_hal_usart.h
  • USART_MODE_TX_RX : stm32f3xx_hal_usart.h
  • USART_PARITY_EVEN : stm32f3xx_hal_usart.h
  • USART_PARITY_NONE : stm32f3xx_hal_usart.h
  • USART_PARITY_ODD : stm32f3xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32f3xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32f3xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32f3xx_hal_usart.h
  • USART_POLARITY_LOW : stm32f3xx_hal_usart.h
  • USART_Receive_IT() : stm32f3xx_hal_usart.c
  • USART_RXDATA_FLUSH_REQUEST : stm32f3xx_hal_usart.h
  • USART_SetConfig() : stm32f3xx_hal_usart.c
  • USART_STOPBITS_0_5 : stm32f3xx_hal_usart.h
  • USART_STOPBITS_1 : stm32f3xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32f3xx_hal_usart.h
  • USART_STOPBITS_2 : stm32f3xx_hal_usart.h
  • USART_TEACK_REACK_TIMEOUT : stm32f3xx_hal_usart.c
  • USART_Transmit_IT() : stm32f3xx_hal_usart.c
  • USART_TransmitReceive_IT() : stm32f3xx_hal_usart.c
  • USART_TXDATA_FLUSH_REQUEST : stm32f3xx_hal_usart.h
  • USART_WaitOnFlagUntilTimeout() : stm32f3xx_hal_usart.c
  • USART_WORDLENGTH_8B : stm32f3xx_hal_usart_ex.h
  • USART_WORDLENGTH_9B : stm32f3xx_hal_usart_ex.h
  • USB_WAKEUP_EXTI_LINE : stm32f3xx_hal_pcd.h
  • USE_RTOS : stm32f3xx_hal_conf.h
  • USE_SPI_CRC : stm32f3xx_hal_conf.h
  • UTILS_EnablePLLAndSwitchSystem() : stm32f3xx_ll_utils.c
  • UTILS_GetPLLOutputFrequency() : stm32f3xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MAX : stm32f3xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MIN : stm32f3xx_ll_utils.c
  • UTILS_LATENCY1_FREQ : stm32f3xx_ll_utils.c
  • UTILS_LATENCY2_FREQ : stm32f3xx_ll_utils.c
  • UTILS_PLL_IsBusy() : stm32f3xx_ll_utils.c
  • UTILS_PLL_OUTPUT_MAX : stm32f3xx_ll_utils.c
  • UTILS_SetFlashLatency() : stm32f3xx_ll_utils.c
  • uwTick : stm32f3xx_hal.c
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- v -

  • VDD_VALUE : stm32f3xx_hal_conf.h
  • VREFINT_CAL_ADDR : stm32f3xx_ll_adc.h
  • VREFINT_CAL_VREF : stm32f3xx_ll_adc.h
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- w -

  • WWDG_EWI_DISABLE : stm32f3xx_hal_wwdg.h
  • WWDG_EWI_ENABLE : stm32f3xx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32f3xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32f3xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32f3xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32f3xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32f3xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32f3xx_hal_wwdg.h
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STM32F373xC HAL User Manual: Globals

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- a -

  • ADC_ConversionStop_Disable() : stm32f3xx_hal_adc_ex.c
  • ADC_DMAConvCplt() : stm32f3xx_hal_adc_ex.c
  • ADC_DMAError() : stm32f3xx_hal_adc_ex.c
  • ADC_DMAHalfConvCplt() : stm32f3xx_hal_adc_ex.c
  • ADC_Enable() : stm32f3xx_hal_adc_ex.c
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STM32F373xC HAL User Manual: Globals

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- c -

  • CAN_Receive_IT() : stm32f3xx_hal_can.c
  • CAN_Transmit_IT() : stm32f3xx_hal_can.c
  • CRC_Handle_16() : stm32f3xx_hal_crc.c
  • CRC_Handle_8() : stm32f3xx_hal_crc.c
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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- d -

  • DAC_DMAConvCpltCh1() : stm32f3xx_hal_dac_ex.c
  • DAC_DMAConvCpltCh2() : stm32f3xx_hal_dac_ex.c
  • DAC_DMAErrorCh1() : stm32f3xx_hal_dac_ex.c
  • DAC_DMAErrorCh2() : stm32f3xx_hal_dac_ex.c
  • DAC_DMAHalfConvCpltCh1() : stm32f3xx_hal_dac_ex.c
  • DAC_DMAHalfConvCpltCh2() : stm32f3xx_hal_dac_ex.c
  • DMA_CalcBaseAndBitshift() : stm32f3xx_hal_dma.c
  • DMA_SetConfig() : stm32f3xx_hal_dma.c
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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- f -

  • FLASH_MassErase() : stm32f3xx_hal_flash_ex.c
  • FLASH_OB_DisableWRP() : stm32f3xx_hal_flash_ex.c
  • FLASH_OB_EnableWRP() : stm32f3xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32f3xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32f3xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32f3xx_hal_flash_ex.c
  • FLASH_OB_ProgramData() : stm32f3xx_hal_flash_ex.c
  • FLASH_OB_RDP_LevelConfig() : stm32f3xx_hal_flash_ex.c
  • FLASH_OB_UserConfig() : stm32f3xx_hal_flash_ex.c
  • FLASH_PageErase() : stm32f3xx_hal_flash.c , stm32f3xx_hal_flash_ex.c
  • FLASH_Program_HalfWord() : stm32f3xx_hal_flash.c
  • FLASH_SetErrorCode() : stm32f3xx_hal_flash.c
  • FLASH_WaitForLastOperation() : stm32f3xx_hal_flash.c
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STM32F373xC HAL User Manual: Globals

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- h -

  • HAL_ADC_AnalogWDGConfig() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_ConfigChannel() : stm32f3xx_hal_adc_ex.c , stm32f3xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32f3xx_hal_adc.c
  • HAL_ADC_ConvHalfCpltCallback() : stm32f3xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32f3xx_hal_adc_ex.c , stm32f3xx_hal_adc.c
  • HAL_ADC_ErrorCallback() : stm32f3xx_hal_adc.c
  • HAL_ADC_GetError() : stm32f3xx_hal_adc.c
  • HAL_ADC_GetState() : stm32f3xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_Init() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_IRQHandler() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_LevelOutOfWindowCallback() : stm32f3xx_hal_adc.c
  • HAL_ADC_MspDeInit() : stm32f3xx_hal_adc.c
  • HAL_ADC_MspInit() : stm32f3xx_hal_adc.c
  • HAL_ADC_PollForConversion() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_PollForEvent() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_Start() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_Start_DMA() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_Start_IT() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_Stop() : stm32f3xx_hal_adc_ex.c , stm32f3xx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADC_Stop_IT() : stm32f3xx_hal_adc.c , stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_Start() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32f3xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop() : stm32f3xx_hal_adc_ex.h
  • HAL_ADCEx_RegularStop_DMA() : stm32f3xx_hal_adc_ex.h
  • HAL_ADCEx_RegularStop_IT() : stm32f3xx_hal_adc_ex.h
  • HAL_CAN_ConfigFilter() : stm32f3xx_hal_can.c
  • HAL_CAN_DeInit() : stm32f3xx_hal_can.c
  • HAL_CAN_ErrorCallback() : stm32f3xx_hal_can.c
  • HAL_CAN_GetError() : stm32f3xx_hal_can.c
  • HAL_CAN_GetState() : stm32f3xx_hal_can.c
  • HAL_CAN_Init() : stm32f3xx_hal_can.c
  • HAL_CAN_IRQHandler() : stm32f3xx_hal_can.c
  • HAL_CAN_MspDeInit() : stm32f3xx_hal_can.c
  • HAL_CAN_MspInit() : stm32f3xx_hal_can.c
  • HAL_CAN_Receive() : stm32f3xx_hal_can.c
  • HAL_CAN_Receive_IT() : stm32f3xx_hal_can.c
  • HAL_CAN_RxCpltCallback() : stm32f3xx_hal_can.c
  • HAL_CAN_Sleep() : stm32f3xx_hal_can.c
  • HAL_CAN_Transmit() : stm32f3xx_hal_can.c
  • HAL_CAN_Transmit_IT() : stm32f3xx_hal_can.c
  • HAL_CAN_TxCpltCallback() : stm32f3xx_hal_can.c
  • HAL_CAN_WakeUp() : stm32f3xx_hal_can.c
  • HAL_CEC_ChangeRxBuffer() : stm32f3xx_hal_cec.c
  • HAL_CEC_DeInit() : stm32f3xx_hal_cec.c
  • HAL_CEC_ErrorCallback() : stm32f3xx_hal_cec.c
  • HAL_CEC_GetError() : stm32f3xx_hal_cec.c
  • HAL_CEC_GetLastReceivedFrameSize() : stm32f3xx_hal_cec.c
  • HAL_CEC_GetState() : stm32f3xx_hal_cec.c
  • HAL_CEC_Init() : stm32f3xx_hal_cec.c
  • HAL_CEC_IRQHandler() : stm32f3xx_hal_cec.c
  • HAL_CEC_MspDeInit() : stm32f3xx_hal_cec.c
  • HAL_CEC_MspInit() : stm32f3xx_hal_cec.c
  • HAL_CEC_RxCpltCallback() : stm32f3xx_hal_cec.c
  • HAL_CEC_SetDeviceAddress() : stm32f3xx_hal_cec.c
  • HAL_CEC_Transmit_IT() : stm32f3xx_hal_cec.c
  • HAL_CEC_TxCpltCallback() : stm32f3xx_hal_cec.c
  • HAL_COMP_DeInit() : stm32f3xx_hal_comp.c
  • HAL_COMP_GetOutputLevel() : stm32f3xx_hal_comp.c
  • HAL_COMP_GetState() : stm32f3xx_hal_comp.c
  • HAL_COMP_Init() : stm32f3xx_hal_comp.c
  • HAL_COMP_IRQHandler() : stm32f3xx_hal_comp.c
  • HAL_COMP_Lock() : stm32f3xx_hal_comp.c
  • HAL_COMP_MspDeInit() : stm32f3xx_hal_comp.c
  • HAL_COMP_MspInit() : stm32f3xx_hal_comp.c
  • HAL_COMP_Start() : stm32f3xx_hal_comp.c
  • HAL_COMP_Start_IT() : stm32f3xx_hal_comp.c
  • HAL_COMP_Stop() : stm32f3xx_hal_comp.c
  • HAL_COMP_Stop_IT() : stm32f3xx_hal_comp.c
  • HAL_COMP_TriggerCallback() : stm32f3xx_hal_comp.c
  • HAL_CRC_Accumulate() : stm32f3xx_hal_crc.c
  • HAL_CRC_Calculate() : stm32f3xx_hal_crc.c
  • HAL_CRC_DeInit() : stm32f3xx_hal_crc.c
  • HAL_CRC_GetState() : stm32f3xx_hal_crc.c
  • HAL_CRC_Init() : stm32f3xx_hal_crc.c
  • HAL_CRC_MspDeInit() : stm32f3xx_hal_crc.c
  • HAL_CRC_MspInit() : stm32f3xx_hal_crc.c
  • HAL_CRCEx_Input_Data_Reverse() : stm32f3xx_hal_crc_ex.c
  • HAL_CRCEx_Output_Data_Reverse() : stm32f3xx_hal_crc_ex.c
  • HAL_CRCEx_Polynomial_Set() : stm32f3xx_hal_crc_ex.c
  • HAL_DAC_ConfigChannel() : stm32f3xx_hal_dac.c , stm32f3xx_hal_dac.h , stm32f3xx_hal_dac_ex.c
  • HAL_DAC_ConvCpltCallbackCh1() : stm32f3xx_hal_dac.c
  • HAL_DAC_ConvHalfCpltCallbackCh1() : stm32f3xx_hal_dac.c
  • HAL_DAC_DeInit() : stm32f3xx_hal_dac.c
  • HAL_DAC_DMAUnderrunCallbackCh1() : stm32f3xx_hal_dac.c
  • HAL_DAC_ErrorCallbackCh1() : stm32f3xx_hal_dac.c
  • HAL_DAC_GetError() : stm32f3xx_hal_dac.c
  • HAL_DAC_GetState() : stm32f3xx_hal_dac.c
  • HAL_DAC_GetValue() : stm32f3xx_hal_dac.c , stm32f3xx_hal_dac_ex.c
  • HAL_DAC_Init() : stm32f3xx_hal_dac.c
  • HAL_DAC_IRQHandler() : stm32f3xx_hal_dac.h , stm32f3xx_hal_dac_ex.c
  • HAL_DAC_MspDeInit() : stm32f3xx_hal_dac.c
  • HAL_DAC_MspInit() : stm32f3xx_hal_dac.c
  • HAL_DAC_SetValue() : stm32f3xx_hal_dac.c , stm32f3xx_hal_dac_ex.c
  • HAL_DAC_Start() : stm32f3xx_hal_dac.c , stm32f3xx_hal_dac_ex.c
  • HAL_DAC_Start_DMA() : stm32f3xx_hal_dac.h , stm32f3xx_hal_dac_ex.c
  • HAL_DAC_Stop() : stm32f3xx_hal_dac.c
  • HAL_DAC_Stop_DMA() : stm32f3xx_hal_dac.c
  • HAL_DACEx_ConvCpltCallbackCh2() : stm32f3xx_hal_dac_ex.c
  • HAL_DACEx_ConvHalfCpltCallbackCh2() : stm32f3xx_hal_dac_ex.c
  • HAL_DACEx_DMAUnderrunCallbackCh2() : stm32f3xx_hal_dac_ex.c
  • HAL_DACEx_DualGetValue() : stm32f3xx_hal_dac.c , stm32f3xx_hal_dac_ex.c
  • HAL_DACEx_DualSetValue() : stm32f3xx_hal_dac.c , stm32f3xx_hal_dac_ex.c , stm32f3xx_hal_dac_ex.h
  • HAL_DACEx_ErrorCallbackCh2() : stm32f3xx_hal_dac_ex.c
  • HAL_DACEx_NoiseWaveGenerate() : stm32f3xx_hal_dac_ex.c
  • HAL_DACEx_TriangleWaveGenerate() : stm32f3xx_hal_dac_ex.c
  • HAL_DBGMCU_DisableDBGSleepMode() : stm32f3xx_hal.c
  • HAL_DBGMCU_DisableDBGStandbyMode() : stm32f3xx_hal.c
  • HAL_DBGMCU_DisableDBGStopMode() : stm32f3xx_hal.c
  • HAL_DBGMCU_EnableDBGSleepMode() : stm32f3xx_hal.c
  • HAL_DBGMCU_EnableDBGStandbyMode() : stm32f3xx_hal.c
  • HAL_DBGMCU_EnableDBGStopMode() : stm32f3xx_hal.c
  • HAL_DeInit() : stm32f3xx_hal.c
  • HAL_Delay() : stm32f3xx_hal.c
  • HAL_DMA_Abort() : stm32f3xx_hal_dma.c
  • HAL_DMA_Abort_IT() : stm32f3xx_hal_dma.c
  • HAL_DMA_DeInit() : stm32f3xx_hal_dma.c
  • HAL_DMA_GetError() : stm32f3xx_hal_dma.c
  • HAL_DMA_GetState() : stm32f3xx_hal_dma.c
  • HAL_DMA_Init() : stm32f3xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32f3xx_hal_dma.c
  • HAL_DMA_PollForTransfer() : stm32f3xx_hal_dma.c
  • HAL_DMA_RegisterCallback() : stm32f3xx_hal_dma.c
  • HAL_DMA_Start() : stm32f3xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32f3xx_hal_dma.c
  • HAL_DMA_UnRegisterCallback() : stm32f3xx_hal_dma.c
  • HAL_FLASH_EndOfOperationCallback() : stm32f3xx_hal_flash.c
  • HAL_FLASH_GetError() : stm32f3xx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32f3xx_hal_flash.c
  • HAL_FLASH_Lock() : stm32f3xx_hal_flash.c
  • HAL_FLASH_OB_Launch() : stm32f3xx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32f3xx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32f3xx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32f3xx_hal_flash.c
  • HAL_FLASH_Program() : stm32f3xx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32f3xx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32f3xx_hal_flash.c
  • HAL_FLASHEx_Erase() : stm32f3xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32f3xx_hal_flash_ex.c
  • HAL_FLASHEx_OBErase() : stm32f3xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32f3xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetUserData() : stm32f3xx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32f3xx_hal_flash_ex.c
  • HAL_GetDEVID() : stm32f3xx_hal.c
  • HAL_GetHalVersion() : stm32f3xx_hal.c
  • HAL_GetREVID() : stm32f3xx_hal.c
  • HAL_GetTick() : stm32f3xx_hal.c
  • HAL_GetUIDw0() : stm32f3xx_hal.c
  • HAL_GetUIDw1() : stm32f3xx_hal.c
  • HAL_GetUIDw2() : stm32f3xx_hal.c
  • HAL_GPIO_DeInit() : stm32f3xx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32f3xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32f3xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32f3xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32f3xx_hal_gpio.c
  • HAL_GPIO_ReadPin() : stm32f3xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32f3xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32f3xx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32f3xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32f3xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32f3xx_hal_uart.c
  • HAL_I2C_AbortCpltCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_AddrCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_DeInit() : stm32f3xx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32f3xx_hal_i2c.c
  • HAL_I2C_ErrorCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32f3xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32f3xx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32f3xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Init() : stm32f3xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32f3xx_hal_i2c.c
  • HAL_I2C_ListenCpltCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Receive_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Transmit_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_MasterRxCpltCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Mem_Write() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_MspDeInit() : stm32f3xx_hal_i2c.c
  • HAL_I2C_MspInit() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Receive_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Transmit_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32f3xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32f3xx_hal_i2c.c
  • HAL_I2C_SlaveRxCpltCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32f3xx_hal_i2c.c
  • HAL_I2CEx_ConfigAnalogFilter() : stm32f3xx_hal_i2c_ex.c
  • HAL_I2CEx_ConfigDigitalFilter() : stm32f3xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableFastModePlus() : stm32f3xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableWakeUp() : stm32f3xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableFastModePlus() : stm32f3xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableWakeUp() : stm32f3xx_hal_i2c_ex.c
  • HAL_I2S_DeInit() : stm32f3xx_hal_i2s.c
  • HAL_I2S_DMAPause() : stm32f3xx_hal_i2s.c , stm32f3xx_hal_i2s_ex.c
  • HAL_I2S_DMAResume() : stm32f3xx_hal_i2s.c , stm32f3xx_hal_i2s_ex.c
  • HAL_I2S_DMAStop() : stm32f3xx_hal_i2s.c , stm32f3xx_hal_i2s_ex.c
  • HAL_I2S_ErrorCallback() : stm32f3xx_hal_i2s.c
  • HAL_I2S_GetError() : stm32f3xx_hal_i2s.c
  • HAL_I2S_GetState() : stm32f3xx_hal_i2s.c
  • HAL_I2S_Init() : stm32f3xx_hal_i2s.c
  • HAL_I2S_IRQHandler() : stm32f3xx_hal_i2s.c
  • HAL_I2S_MspDeInit() : stm32f3xx_hal_i2s.c
  • HAL_I2S_MspInit() : stm32f3xx_hal_i2s.c
  • HAL_I2S_Receive() : stm32f3xx_hal_i2s.c
  • HAL_I2S_Receive_DMA() : stm32f3xx_hal_i2s.c
  • HAL_I2S_Receive_IT() : stm32f3xx_hal_i2s.c
  • HAL_I2S_RxCpltCallback() : stm32f3xx_hal_i2s.c
  • HAL_I2S_RxHalfCpltCallback() : stm32f3xx_hal_i2s.c
  • HAL_I2S_Transmit() : stm32f3xx_hal_i2s.c
  • HAL_I2S_Transmit_DMA() : stm32f3xx_hal_i2s.c
  • HAL_I2S_Transmit_IT() : stm32f3xx_hal_i2s.c
  • HAL_I2S_TxCpltCallback() : stm32f3xx_hal_i2s.c
  • HAL_I2S_TxHalfCpltCallback() : stm32f3xx_hal_i2s.c
  • HAL_IncTick() : stm32f3xx_hal.c
  • HAL_Init() : stm32f3xx_hal.c
  • HAL_InitTick() : stm32f3xx_hal.c
  • HAL_IRDA_Abort() : stm32f3xx_hal_irda.c
  • HAL_IRDA_Abort_IT() : stm32f3xx_hal_irda.c
  • HAL_IRDA_AbortCpltCallback() : stm32f3xx_hal_irda.c
  • HAL_IRDA_AbortReceive() : stm32f3xx_hal_irda.c
  • HAL_IRDA_AbortReceive_IT() : stm32f3xx_hal_irda.c
  • HAL_IRDA_AbortReceiveCpltCallback() : stm32f3xx_hal_irda.c
  • HAL_IRDA_AbortTransmit() : stm32f3xx_hal_irda.c
  • HAL_IRDA_AbortTransmit_IT() : stm32f3xx_hal_irda.c
  • HAL_IRDA_AbortTransmitCpltCallback() : stm32f3xx_hal_irda.c
  • HAL_IRDA_DeInit() : stm32f3xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32f3xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32f3xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32f3xx_hal_irda.c
  • HAL_IRDA_ErrorCallback() : stm32f3xx_hal_irda.c
  • HAL_IRDA_GetError() : stm32f3xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32f3xx_hal_irda.c
  • HAL_IRDA_Init() : stm32f3xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32f3xx_hal_irda.c
  • HAL_IRDA_MspDeInit() : stm32f3xx_hal_irda.c
  • HAL_IRDA_MspInit() : stm32f3xx_hal_irda.c
  • HAL_IRDA_Receive() : stm32f3xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32f3xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32f3xx_hal_irda.c
  • HAL_IRDA_RxCpltCallback() : stm32f3xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32f3xx_hal_irda.c
  • HAL_IRDA_Transmit() : stm32f3xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32f3xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32f3xx_hal_irda.c
  • HAL_IRDA_TxCpltCallback() : stm32f3xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32f3xx_hal_irda.c
  • HAL_IWDG_Init() : stm32f3xx_hal_iwdg.c
  • HAL_IWDG_Refresh() : stm32f3xx_hal_iwdg.c
  • HAL_LIN_Init() : stm32f3xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32f3xx_hal_uart.c
  • HAL_MPU_ConfigRegion() : stm32f3xx_hal_cortex.c
  • HAL_MPU_Disable() : stm32f3xx_hal_cortex.c , stm32f3xx_hal_cortex.h
  • HAL_MPU_Enable() : stm32f3xx_hal_cortex.c , stm32f3xx_hal_cortex.h
  • HAL_MspDeInit() : stm32f3xx_hal.c
  • HAL_MspInit() : stm32f3xx_hal.c
  • HAL_MultiProcessor_DisableMuteMode() : stm32f3xx_hal_uart.c
  • HAL_MultiProcessor_EnableMuteMode() : stm32f3xx_hal_uart.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32f3xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32f3xx_hal_uart.c
  • HAL_MultiProcessorEx_AddressLength_Set() : stm32f3xx_hal_uart_ex.c
  • HAL_NVIC_ClearPendingIRQ() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_GetActive() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32f3xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32f3xx_hal_cortex.c
  • HAL_OPAMPEx_SelfCalibrateAll() : stm32f3xx_hal_opamp_ex.c
  • HAL_PCD_ActivateRemoteWakeup() : stm32f3xx_hal_pcd.c
  • HAL_PCD_ActiveRemoteWakeup() : stm32f3xx_hal_pcd.h
  • HAL_PCD_ConnectCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32f3xx_hal_pcd.c
  • HAL_PCD_DeActiveRemoteWakeup() : stm32f3xx_hal_pcd.h
  • HAL_PCD_DeInit() : stm32f3xx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32f3xx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32f3xx_hal_pcd.c
  • HAL_PCD_DisconnectCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32f3xx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32f3xx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32f3xx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32f3xx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32f3xx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32f3xx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32f3xx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32f3xx_hal_pcd.c
  • HAL_PCD_GetState() : stm32f3xx_hal_pcd.c
  • HAL_PCD_Init() : stm32f3xx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32f3xx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_MspDeInit() : stm32f3xx_hal_pcd.c
  • HAL_PCD_MspInit() : stm32f3xx_hal_pcd.c
  • HAL_PCD_ResetCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_ResumeCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32f3xx_hal_pcd.c
  • HAL_PCD_SetupStageCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_SOFCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCD_Start() : stm32f3xx_hal_pcd.c
  • HAL_PCD_Stop() : stm32f3xx_hal_pcd.c
  • HAL_PCD_SuspendCallback() : stm32f3xx_hal_pcd.c
  • HAL_PCDEx_PMAConfig() : stm32f3xx_hal_pcd_ex.c
  • HAL_PCDEx_SetConnectionState() : stm32f3xx_hal_pcd_ex.c , stm32f3xx_hal_pcd_ex.h
  • HAL_PWR_ConfigPVD() : stm32f3xx_hal_pwr_ex.c
  • HAL_PWR_DeInit() : stm32f3xx_hal_pwr.c , stm32f3xx_hal_pwr.h
  • HAL_PWR_DisableBkUpAccess() : stm32f3xx_hal_pwr.c , stm32f3xx_hal_pwr.h
  • HAL_PWR_DisablePVD() : stm32f3xx_hal_pwr_ex.c
  • HAL_PWR_DisableSEVOnPend() : stm32f3xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32f3xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32f3xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32f3xx_hal_pwr.c , stm32f3xx_hal_pwr.h
  • HAL_PWR_EnablePVD() : stm32f3xx_hal_pwr_ex.c
  • HAL_PWR_EnableSEVOnPend() : stm32f3xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32f3xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32f3xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32f3xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32f3xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32f3xx_hal_pwr.c
  • HAL_PWR_PVD_IRQHandler() : stm32f3xx_hal_pwr_ex.c
  • HAL_PWR_PVDCallback() : stm32f3xx_hal_pwr_ex.c
  • HAL_PWREx_DisableSDADC() : stm32f3xx_hal_pwr_ex.c
  • HAL_PWREx_EnableSDADC() : stm32f3xx_hal_pwr_ex.c
  • HAL_RCC_ClockConfig() : stm32f3xx_hal_rcc.c
  • HAL_RCC_CSSCallback() : stm32f3xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32f3xx_hal_rcc.c
  • HAL_RCC_DisableCSS() : stm32f3xx_hal_rcc.c
  • HAL_RCC_EnableCSS() : stm32f3xx_hal_rcc.c
  • HAL_RCC_GetClockConfig() : stm32f3xx_hal_rcc.c
  • HAL_RCC_GetHCLKFreq() : stm32f3xx_hal_rcc.c
  • HAL_RCC_GetOscConfig() : stm32f3xx_hal_rcc.c
  • HAL_RCC_GetPCLK1Freq() : stm32f3xx_hal_rcc.c
  • HAL_RCC_GetPCLK2Freq() : stm32f3xx_hal_rcc.c
  • HAL_RCC_GetSysClockFreq() : stm32f3xx_hal_rcc.c
  • HAL_RCC_MCOConfig() : stm32f3xx_hal_rcc.c
  • HAL_RCC_NMI_IRQHandler() : stm32f3xx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32f3xx_hal_rcc.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32f3xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32f3xx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32f3xx_hal_rcc_ex.c
  • HAL_ResumeTick() : stm32f3xx_hal.c
  • HAL_RS485Ex_Init() : stm32f3xx_hal_uart_ex.c
  • HAL_RTC_AlarmAEventCallback() : stm32f3xx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32f3xx_hal_rtc.c
  • HAL_RTC_DeactivateAlarm() : stm32f3xx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32f3xx_hal_rtc.c
  • HAL_RTC_GetAlarm() : stm32f3xx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32f3xx_hal_rtc.c
  • HAL_RTC_GetState() : stm32f3xx_hal_rtc.c , stm32f3xx_hal_rtc.h
  • HAL_RTC_GetTime() : stm32f3xx_hal_rtc.c
  • HAL_RTC_Init() : stm32f3xx_hal_rtc.c
  • HAL_RTC_MspDeInit() : stm32f3xx_hal_rtc.c
  • HAL_RTC_MspInit() : stm32f3xx_hal_rtc.c
  • HAL_RTC_PollForAlarmAEvent() : stm32f3xx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32f3xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32f3xx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32f3xx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32f3xx_hal_rtc.c
  • HAL_RTC_WaitForSynchro() : stm32f3xx_hal_rtc.h , stm32f3xx_hal_rtc.c
  • HAL_RTCEx_AlarmBEventCallback() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPRead() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateRefClock() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTimeStamp() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_DisableBypassShadow() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_EnableBypassShadow() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_GetTimeStamp() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_GetWakeUpTimer() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForAlarmBEvent() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper1Event() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper2Event() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper3Event() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTimeStampEvent() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetCalibrationOutPut() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetRefClock() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSynchroShift() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp_IT() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper2EventCallback() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper3EventCallback() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_TamperTimeStampIRQHandler() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampEventCallback() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32f3xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32f3xx_hal_rtc_ex.c
  • HAL_SDADC_AssociateChannelConfig() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_CalibrationCpltCallback() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_CalibrationStart() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_CalibrationStart_IT() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_ConfigChannel() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_ConvCpltCallback() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_ConvHalfCpltCallback() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_DeInit() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_ErrorCallback() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_GetError() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_GetState() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_GetValue() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_Init() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedConfigChannel() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedConvCpltCallback() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedConvHalfCpltCallback() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedGetValue() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedMultiModeConfigChannel() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedMultiModeGetValue() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedMultiModeStart_DMA() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedMultiModeStop_DMA() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedStart() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedStart_DMA() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedStart_IT() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedStop() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedStop_DMA() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_InjectedStop_IT() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_IRQHandler() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_MspDeInit() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_MspInit() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_MultiModeConfigChannel() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_MultiModeGetValue() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_MultiModeStart_DMA() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_MultiModeStop_DMA() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_PollForCalibEvent() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_PollForConversion() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_PollForInjectedConversion() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_PrepareChannelConfig() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_SelectInjectedDelay() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_SelectInjectedExtTrigger() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_SelectInjectedTrigger() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_SelectRegularTrigger() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_Start() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_Start_DMA() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_Start_IT() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_Stop() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_Stop_DMA() : stm32f3xx_hal_sdadc.c
  • HAL_SDADC_Stop_IT() : stm32f3xx_hal_sdadc.c
  • HAL_SMARTCARD_Abort() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_Abort_IT() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortCpltCallback() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive_IT() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceiveCpltCallback() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit_IT() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmitCpltCallback() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_DeInit() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_ErrorCallback() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_MspDeInit() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_MspInit() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_RxCpltCallback() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARD_TxCpltCallback() : stm32f3xx_hal_smartcard.c
  • HAL_SMARTCARDEx_BlockLength_Config() : stm32f3xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableReceiverTimeOut() : stm32f3xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableReceiverTimeOut() : stm32f3xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TimeOut_Config() : stm32f3xx_hal_smartcard_ex.c
  • HAL_SMBUS_AddrCallback() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_ConfigAnalogFilter() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_ConfigDigitalFilter() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_DeInit() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_DisableAlert_IT() : stm32f3xx_hal_smbus.c , stm32f3xx_hal_smbus.h
  • HAL_SMBUS_DisableListen_IT() : stm32f3xx_hal_smbus.h , stm32f3xx_hal_smbus.c
  • HAL_SMBUS_EnableAlert_IT() : stm32f3xx_hal_smbus.c , stm32f3xx_hal_smbus.h
  • HAL_SMBUS_EnableListen_IT() : stm32f3xx_hal_smbus.c , stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ER_IRQHandler() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_ErrorCallback() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_EV_IRQHandler() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_GetError() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_GetState() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_Init() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_IsDeviceReady() : stm32f3xx_hal_smbus.h , stm32f3xx_hal_smbus.c
  • HAL_SMBUS_ListenCpltCallback() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_Master_Abort_IT() : stm32f3xx_hal_smbus.h , stm32f3xx_hal_smbus.c
  • HAL_SMBUS_Master_Receive_IT() : stm32f3xx_hal_smbus.c , stm32f3xx_hal_smbus.h
  • HAL_SMBUS_Master_Transmit_IT() : stm32f3xx_hal_smbus.c , stm32f3xx_hal_smbus.h
  • HAL_SMBUS_MasterRxCpltCallback() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_MasterTxCpltCallback() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_MspDeInit() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_MspInit() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_Slave_Receive_IT() : stm32f3xx_hal_smbus.h , stm32f3xx_hal_smbus.c
  • HAL_SMBUS_Slave_Transmit_IT() : stm32f3xx_hal_smbus.h , stm32f3xx_hal_smbus.c
  • HAL_SMBUS_SlaveRxCpltCallback() : stm32f3xx_hal_smbus.c
  • HAL_SMBUS_SlaveTxCpltCallback() : stm32f3xx_hal_smbus.c
  • HAL_SPI_Abort() : stm32f3xx_hal_spi.c
  • HAL_SPI_Abort_IT() : stm32f3xx_hal_spi.c
  • HAL_SPI_AbortCpltCallback() : stm32f3xx_hal_spi.c
  • HAL_SPI_DeInit() : stm32f3xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32f3xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32f3xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32f3xx_hal_spi.c
  • HAL_SPI_ErrorCallback() : stm32f3xx_hal_spi.c
  • HAL_SPI_GetError() : stm32f3xx_hal_spi.c
  • HAL_SPI_GetState() : stm32f3xx_hal_spi.c
  • HAL_SPI_Init() : stm32f3xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32f3xx_hal_spi.c
  • HAL_SPI_MspDeInit() : stm32f3xx_hal_spi.c
  • HAL_SPI_MspInit() : stm32f3xx_hal_spi.c
  • HAL_SPI_Receive() : stm32f3xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32f3xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32f3xx_hal_spi.c
  • HAL_SPI_RxCpltCallback() : stm32f3xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32f3xx_hal_spi.c
  • HAL_SPI_Transmit() : stm32f3xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32f3xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32f3xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32f3xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32f3xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32f3xx_hal_spi.c
  • HAL_SPI_TxCpltCallback() : stm32f3xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32f3xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32f3xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32f3xx_hal_spi.c
  • HAL_SPIEx_FlushRxFifo() : stm32f3xx_hal_spi_ex.c
  • HAL_SuspendTick() : stm32f3xx_hal.c
  • HAL_SYSTICK_Callback() : stm32f3xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32f3xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32f3xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32f3xx_hal_cortex.c
  • HAL_TIM_Base_DeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_MspInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_Start() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_ConfigClockSource() : stm32f3xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32f3xx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32f3xx_hal_tim.c
  • HAL_TIM_DMABurst_MultiReadStart() : stm32f3xx_hal_tim.c
  • HAL_TIM_DMABurst_MultiWriteStart() : stm32f3xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32f3xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32f3xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32f3xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_DeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_MspInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_Start() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_ErrorCallback() : stm32f3xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_CaptureCallback() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_MspInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_Start() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_ConfigChannel() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_DelayElapsedCallback() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_MspInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_Start() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_ConfigChannel() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32f3xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_PeriodElapsedCallback() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_MspInit() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32f3xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32f3xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization() : stm32f3xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization_IT() : stm32f3xx_hal_tim.c
  • HAL_TIM_TriggerCallback() : stm32f3xx_hal_tim.c
  • HAL_TIMEx_Break2Callback() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_BreakCallback() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_CommutationCallback() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent() : stm32f3xx_hal_tim_ex.h
  • HAL_TIMEx_ConfigCommutationEvent_DMA() : stm32f3xx_hal_tim_ex.h
  • HAL_TIMEx_ConfigCommutationEvent_IT() : stm32f3xx_hal_tim_ex.h
  • HAL_TIMEx_HallSensor_DeInit() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32f3xx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32f3xx_hal_tim_ex.c
  • HAL_TSC_ConvCpltCallback() : stm32f3xx_hal_tsc.c
  • HAL_TSC_DeInit() : stm32f3xx_hal_tsc.c
  • HAL_TSC_ErrorCallback() : stm32f3xx_hal_tsc.c
  • HAL_TSC_GetState() : stm32f3xx_hal_tsc.c
  • HAL_TSC_GroupGetStatus() : stm32f3xx_hal_tsc.c
  • HAL_TSC_GroupGetValue() : stm32f3xx_hal_tsc.c
  • HAL_TSC_Init() : stm32f3xx_hal_tsc.c
  • HAL_TSC_IOConfig() : stm32f3xx_hal_tsc.c
  • HAL_TSC_IODischarge() : stm32f3xx_hal_tsc.c
  • HAL_TSC_IRQHandler() : stm32f3xx_hal_tsc.c
  • HAL_TSC_MspDeInit() : stm32f3xx_hal_tsc.c
  • HAL_TSC_MspInit() : stm32f3xx_hal_tsc.c
  • HAL_TSC_PollForAcquisition() : stm32f3xx_hal_tsc.c
  • HAL_TSC_Start() : stm32f3xx_hal_tsc.c
  • HAL_TSC_Start_IT() : stm32f3xx_hal_tsc.c
  • HAL_TSC_Stop() : stm32f3xx_hal_tsc.c
  • HAL_TSC_Stop_IT() : stm32f3xx_hal_tsc.c
  • HAL_UART_Abort() : stm32f3xx_hal_uart.c
  • HAL_UART_Abort_IT() : stm32f3xx_hal_uart.c
  • HAL_UART_AbortCpltCallback() : stm32f3xx_hal_uart.c
  • HAL_UART_AbortReceive() : stm32f3xx_hal_uart.c
  • HAL_UART_AbortReceive_IT() : stm32f3xx_hal_uart.c
  • HAL_UART_AbortReceiveCpltCallback() : stm32f3xx_hal_uart.c
  • HAL_UART_AbortTransmit() : stm32f3xx_hal_uart.c
  • HAL_UART_AbortTransmit_IT() : stm32f3xx_hal_uart.c
  • HAL_UART_AbortTransmitCpltCallback() : stm32f3xx_hal_uart.c
  • HAL_UART_DeInit() : stm32f3xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32f3xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32f3xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32f3xx_hal_uart.c
  • HAL_UART_ErrorCallback() : stm32f3xx_hal_uart.c
  • HAL_UART_GetError() : stm32f3xx_hal_uart.c
  • HAL_UART_GetState() : stm32f3xx_hal_uart.c
  • HAL_UART_Init() : stm32f3xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32f3xx_hal_uart.c
  • HAL_UART_MspDeInit() : stm32f3xx_hal_uart.c
  • HAL_UART_MspInit() : stm32f3xx_hal_uart.c
  • HAL_UART_Receive() : stm32f3xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32f3xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32f3xx_hal_uart.c
  • HAL_UART_RxCpltCallback() : stm32f3xx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32f3xx_hal_uart.c
  • HAL_UART_Transmit() : stm32f3xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32f3xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32f3xx_hal_uart.c
  • HAL_UART_TxCpltCallback() : stm32f3xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32f3xx_hal_uart.c
  • HAL_UARTEx_DisableStopMode() : stm32f3xx_hal_uart_ex.c
  • HAL_UARTEx_EnableStopMode() : stm32f3xx_hal_uart_ex.c
  • HAL_UARTEx_StopModeWakeUpSourceConfig() : stm32f3xx_hal_uart_ex.c
  • HAL_UARTEx_WakeupCallback() : stm32f3xx_hal_uart_ex.c , stm32f3xx_hal_uart_ex.h
  • HAL_USART_Abort() : stm32f3xx_hal_usart.c
  • HAL_USART_Abort_IT() : stm32f3xx_hal_usart.c
  • HAL_USART_AbortCpltCallback() : stm32f3xx_hal_usart.c
  • HAL_USART_DeInit() : stm32f3xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32f3xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32f3xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32f3xx_hal_usart.c
  • HAL_USART_ErrorCallback() : stm32f3xx_hal_usart.c
  • HAL_USART_GetError() : stm32f3xx_hal_usart.c
  • HAL_USART_GetState() : stm32f3xx_hal_usart.c
  • HAL_USART_Init() : stm32f3xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32f3xx_hal_usart.c
  • HAL_USART_MspDeInit() : stm32f3xx_hal_usart.c
  • HAL_USART_MspInit() : stm32f3xx_hal_usart.c
  • HAL_USART_Receive() : stm32f3xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32f3xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32f3xx_hal_usart.c
  • HAL_USART_RxCpltCallback() : stm32f3xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32f3xx_hal_usart.c
  • HAL_USART_Transmit() : stm32f3xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32f3xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32f3xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32f3xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32f3xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32f3xx_hal_usart.c
  • HAL_USART_TxCpltCallback() : stm32f3xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32f3xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32f3xx_hal_usart.c
  • HAL_WWDG_EarlyWakeupCallback() : stm32f3xx_hal_wwdg.c
  • HAL_WWDG_Init() : stm32f3xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32f3xx_hal_wwdg.c
  • HAL_WWDG_MspInit() : stm32f3xx_hal_wwdg.c
  • HAL_WWDG_Refresh() : stm32f3xx_hal_wwdg.c
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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- i -

  • I2C_Disable_IRQ() : stm32f3xx_hal_i2c.c
  • I2C_DMAAbort() : stm32f3xx_hal_i2c.c
  • I2C_DMAError() : stm32f3xx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32f3xx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32f3xx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32f3xx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32f3xx_hal_i2c.c
  • I2C_Enable_IRQ() : stm32f3xx_hal_i2c.c
  • I2C_Flush_TXDR() : stm32f3xx_hal_i2c.c
  • I2C_IsAcknowledgeFailed() : stm32f3xx_hal_i2c.c
  • I2C_ITAddrCplt() : stm32f3xx_hal_i2c.c
  • I2C_ITError() : stm32f3xx_hal_i2c.c
  • I2C_ITListenCplt() : stm32f3xx_hal_i2c.c
  • I2C_ITMasterCplt() : stm32f3xx_hal_i2c.c
  • I2C_ITMasterSequentialCplt() : stm32f3xx_hal_i2c.c
  • I2C_ITSlaveCplt() : stm32f3xx_hal_i2c.c
  • I2C_ITSlaveSequentialCplt() : stm32f3xx_hal_i2c.c
  • I2C_Master_ISR_DMA() : stm32f3xx_hal_i2c.c
  • I2C_Master_ISR_IT() : stm32f3xx_hal_i2c.c
  • I2C_RequestMemoryRead() : stm32f3xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32f3xx_hal_i2c.c
  • I2C_Slave_ISR_DMA() : stm32f3xx_hal_i2c.c
  • I2C_Slave_ISR_IT() : stm32f3xx_hal_i2c.c
  • I2C_TransferConfig() : stm32f3xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32f3xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32f3xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32f3xx_hal_i2c.c
  • I2C_WaitOnTXISFlagUntilTimeout() : stm32f3xx_hal_i2c.c
  • I2S_DMAError() : stm32f3xx_hal_i2s.c
  • I2S_DMARxCplt() : stm32f3xx_hal_i2s.c
  • I2S_DMARxHalfCplt() : stm32f3xx_hal_i2s.c
  • I2S_DMATxCplt() : stm32f3xx_hal_i2s.c
  • I2S_DMATxHalfCplt() : stm32f3xx_hal_i2s.c
  • I2S_Receive_IT() : stm32f3xx_hal_i2s.c
  • I2S_Transmit_IT() : stm32f3xx_hal_i2s.c
  • I2S_WaitFlagStateUntilTimeout() : stm32f3xx_hal_i2s.c
  • IC1Config() : stm32f3xx_ll_tim.c
  • IC2Config() : stm32f3xx_ll_tim.c
  • IC3Config() : stm32f3xx_ll_tim.c
  • IC4Config() : stm32f3xx_ll_tim.c
  • IRDA_CheckIdleState() : stm32f3xx_hal_irda.c
  • IRDA_DMAAbortOnError() : stm32f3xx_hal_irda.c
  • IRDA_DMAError() : stm32f3xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32f3xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32f3xx_hal_irda.c
  • IRDA_DMARxAbortCallback() : stm32f3xx_hal_irda.c
  • IRDA_DMARxOnlyAbortCallback() : stm32f3xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32f3xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32f3xx_hal_irda.c
  • IRDA_DMATxAbortCallback() : stm32f3xx_hal_irda.c
  • IRDA_DMATxOnlyAbortCallback() : stm32f3xx_hal_irda.c
  • IRDA_EndRxTransfer() : stm32f3xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32f3xx_hal_irda.c
  • IRDA_EndTxTransfer() : stm32f3xx_hal_irda.c
  • IRDA_Receive_IT() : stm32f3xx_hal_irda.c
  • IRDA_SetConfig() : stm32f3xx_hal_irda.c
  • IRDA_Transmit_IT() : stm32f3xx_hal_irda.c
  • IRDA_WaitOnFlagUntilTimeout() : stm32f3xx_hal_irda.c
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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- l -

  • LL_ADC_ClearFlag_AWD1() : stm32f3xx_ll_adc.h
  • LL_ADC_ClearFlag_EOS() : stm32f3xx_ll_adc.h
  • LL_ADC_ClearFlag_JEOS() : stm32f3xx_ll_adc.h
  • LL_ADC_CommonDeInit() : stm32f3xx_ll_adc.c
  • LL_ADC_DeInit() : stm32f3xx_ll_adc.c
  • LL_ADC_Disable() : stm32f3xx_ll_adc.h
  • LL_ADC_DisableIT_AWD1() : stm32f3xx_ll_adc.h
  • LL_ADC_DisableIT_EOS() : stm32f3xx_ll_adc.h
  • LL_ADC_DisableIT_JEOS() : stm32f3xx_ll_adc.h
  • LL_ADC_DMA_GetRegAddr() : stm32f3xx_ll_adc.h
  • LL_ADC_Enable() : stm32f3xx_ll_adc.h
  • LL_ADC_EnableIT_AWD1() : stm32f3xx_ll_adc.h
  • LL_ADC_EnableIT_EOS() : stm32f3xx_ll_adc.h
  • LL_ADC_EnableIT_JEOS() : stm32f3xx_ll_adc.h
  • LL_ADC_GetAnalogWDMonitChannels() : stm32f3xx_ll_adc.h
  • LL_ADC_GetAnalogWDThresholds() : stm32f3xx_ll_adc.h
  • LL_ADC_GetChannelSamplingTime() : stm32f3xx_ll_adc.h
  • LL_ADC_GetCommonPathInternalCh() : stm32f3xx_ll_adc.h
  • LL_ADC_GetDataAlignment() : stm32f3xx_ll_adc.h
  • LL_ADC_GetSequencersScanMode() : stm32f3xx_ll_adc.h
  • LL_ADC_Init() : stm32f3xx_ll_adc.c
  • LL_ADC_INJ_GetOffset() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerDiscont() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerLength() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerRanks() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_GetTrigAuto() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_GetTriggerSource() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_Init() : stm32f3xx_ll_adc.c
  • LL_ADC_INJ_IsTriggerSourceSWStart() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData12() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData32() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SetOffset() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerDiscont() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerLength() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerRanks() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SetTrigAuto() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SetTriggerSource() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_StartConversion() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_StopConversionExtTrig() : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_StructInit() : stm32f3xx_ll_adc.c
  • LL_ADC_IsActiveFlag_AWD1() : stm32f3xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOS() : stm32f3xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOS() : stm32f3xx_ll_adc.h
  • LL_ADC_IsCalibrationOnGoing() : stm32f3xx_ll_adc.h
  • LL_ADC_IsEnabled() : stm32f3xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD1() : stm32f3xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOS() : stm32f3xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOS() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_GetContinuousMode() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_GetDMATransfer() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_GetSequencerDiscont() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_GetSequencerLength() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_GetSequencerRanks() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_GetTriggerSource() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_Init() : stm32f3xx_ll_adc.c
  • LL_ADC_REG_IsTriggerSourceSWStart() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData12() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData32() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SetContinuousMode() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SetDMATransfer() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SetSequencerDiscont() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SetSequencerLength() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SetSequencerRanks() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SetTriggerSource() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_StartConversion() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_StopConversionExtTrig() : stm32f3xx_ll_adc.h
  • LL_ADC_REG_StructInit() : stm32f3xx_ll_adc.c
  • LL_ADC_SetAnalogWDMonitChannels() : stm32f3xx_ll_adc.h
  • LL_ADC_SetAnalogWDThresholds() : stm32f3xx_ll_adc.h
  • LL_ADC_SetChannelSamplingTime() : stm32f3xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalCh() : stm32f3xx_ll_adc.h
  • LL_ADC_SetDataAlignment() : stm32f3xx_ll_adc.h
  • LL_ADC_SetSequencersScanMode() : stm32f3xx_ll_adc.h
  • LL_ADC_StartCalibration() : stm32f3xx_ll_adc.h
  • LL_ADC_StructInit() : stm32f3xx_ll_adc.c
  • LL_AHB1_GRP1_DisableClock() : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClock() : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_ForceReset() : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_IsEnabledClock() : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_ReleaseReset() : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_DisableClock() : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_EnableClock() : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_ForceReset() : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_IsEnabledClock() : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_ReleaseReset() : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_DisableClock() : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_EnableClock() : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_ForceReset() : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_IsEnabledClock() : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_ReleaseReset() : stm32f3xx_ll_bus.h
  • LL_COMP_ConfigInputs() : stm32f3xx_ll_comp.h
  • LL_COMP_DeInit() : stm32f3xx_ll_comp.c
  • LL_COMP_Disable() : stm32f3xx_ll_comp.h
  • LL_COMP_Enable() : stm32f3xx_ll_comp.h
  • LL_COMP_GetCommonWindowMode() : stm32f3xx_ll_comp.h
  • LL_COMP_GetInputHysteresis() : stm32f3xx_ll_comp.h
  • LL_COMP_GetInputMinus() : stm32f3xx_ll_comp.h
  • LL_COMP_GetInputPlus() : stm32f3xx_ll_comp.h
  • LL_COMP_GetOutputPolarity() : stm32f3xx_ll_comp.h
  • LL_COMP_GetOutputSelection() : stm32f3xx_ll_comp.h
  • LL_COMP_GetPowerMode() : stm32f3xx_ll_comp.h
  • LL_COMP_Init() : stm32f3xx_ll_comp.c
  • LL_COMP_IsEnabled() : stm32f3xx_ll_comp.h
  • LL_COMP_IsLocked() : stm32f3xx_ll_comp.h
  • LL_COMP_Lock() : stm32f3xx_ll_comp.h
  • LL_COMP_ReadOutputLevel() : stm32f3xx_ll_comp.h
  • LL_COMP_SetCommonWindowMode() : stm32f3xx_ll_comp.h
  • LL_COMP_SetInputHysteresis() : stm32f3xx_ll_comp.h
  • LL_COMP_SetInputMinus() : stm32f3xx_ll_comp.h
  • LL_COMP_SetInputPlus() : stm32f3xx_ll_comp.h
  • LL_COMP_SetOutputPolarity() : stm32f3xx_ll_comp.h
  • LL_COMP_SetOutputSelection() : stm32f3xx_ll_comp.h
  • LL_COMP_SetPowerMode() : stm32f3xx_ll_comp.h
  • LL_COMP_StructInit() : stm32f3xx_ll_comp.c
  • LL_CPUID_GetConstant() : stm32f3xx_ll_cortex.h
  • LL_CPUID_GetImplementer() : stm32f3xx_ll_cortex.h
  • LL_CPUID_GetParNo() : stm32f3xx_ll_cortex.h
  • LL_CPUID_GetRevision() : stm32f3xx_ll_cortex.h
  • LL_CPUID_GetVariant() : stm32f3xx_ll_cortex.h
  • LL_CRC_DeInit() : stm32f3xx_ll_crc.c
  • LL_CRC_FeedData16() : stm32f3xx_ll_crc.h
  • LL_CRC_FeedData32() : stm32f3xx_ll_crc.h
  • LL_CRC_FeedData8() : stm32f3xx_ll_crc.h
  • LL_CRC_GetInitialData() : stm32f3xx_ll_crc.h
  • LL_CRC_GetInputDataReverseMode() : stm32f3xx_ll_crc.h
  • LL_CRC_GetOutputDataReverseMode() : stm32f3xx_ll_crc.h
  • LL_CRC_GetPolynomialCoef() : stm32f3xx_ll_crc.h
  • LL_CRC_GetPolynomialSize() : stm32f3xx_ll_crc.h
  • LL_CRC_Read_IDR() : stm32f3xx_ll_crc.h
  • LL_CRC_ReadData16() : stm32f3xx_ll_crc.h
  • LL_CRC_ReadData32() : stm32f3xx_ll_crc.h
  • LL_CRC_ReadData7() : stm32f3xx_ll_crc.h
  • LL_CRC_ReadData8() : stm32f3xx_ll_crc.h
  • LL_CRC_ResetCRCCalculationUnit() : stm32f3xx_ll_crc.h
  • LL_CRC_SetInitialData() : stm32f3xx_ll_crc.h
  • LL_CRC_SetInputDataReverseMode() : stm32f3xx_ll_crc.h
  • LL_CRC_SetOutputDataReverseMode() : stm32f3xx_ll_crc.h
  • LL_CRC_SetPolynomialCoef() : stm32f3xx_ll_crc.h
  • LL_CRC_SetPolynomialSize() : stm32f3xx_ll_crc.h
  • LL_CRC_Write_IDR() : stm32f3xx_ll_crc.h
  • LL_DAC_ClearFlag_DMAUDR1() : stm32f3xx_ll_dac.h
  • LL_DAC_ClearFlag_DMAUDR2() : stm32f3xx_ll_dac.h
  • LL_DAC_ConvertData12LeftAligned() : stm32f3xx_ll_dac.h
  • LL_DAC_ConvertData12RightAligned() : stm32f3xx_ll_dac.h
  • LL_DAC_ConvertData8RightAligned() : stm32f3xx_ll_dac.h
  • LL_DAC_ConvertDualData12LeftAligned() : stm32f3xx_ll_dac.h
  • LL_DAC_ConvertDualData12RightAligned() : stm32f3xx_ll_dac.h
  • LL_DAC_ConvertDualData8RightAligned() : stm32f3xx_ll_dac.h
  • LL_DAC_DeInit() : stm32f3xx_ll_dac.c
  • LL_DAC_Disable() : stm32f3xx_ll_dac.h
  • LL_DAC_DisableDMAReq() : stm32f3xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR1() : stm32f3xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR2() : stm32f3xx_ll_dac.h
  • LL_DAC_DisableTrigger() : stm32f3xx_ll_dac.h
  • LL_DAC_DMA_GetRegAddr() : stm32f3xx_ll_dac.h
  • LL_DAC_Enable() : stm32f3xx_ll_dac.h
  • LL_DAC_EnableDMAReq() : stm32f3xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR1() : stm32f3xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR2() : stm32f3xx_ll_dac.h
  • LL_DAC_EnableTrigger() : stm32f3xx_ll_dac.h
  • LL_DAC_GetOutputBuffer() : stm32f3xx_ll_dac.h
  • LL_DAC_GetTriggerSource() : stm32f3xx_ll_dac.h
  • LL_DAC_GetWaveAutoGeneration() : stm32f3xx_ll_dac.h
  • LL_DAC_GetWaveNoiseLFSR() : stm32f3xx_ll_dac.h
  • LL_DAC_GetWaveTriangleAmplitude() : stm32f3xx_ll_dac.h
  • LL_DAC_Init() : stm32f3xx_ll_dac.c
  • LL_DAC_IsActiveFlag_DMAUDR1() : stm32f3xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR2() : stm32f3xx_ll_dac.h
  • LL_DAC_IsDMAReqEnabled() : stm32f3xx_ll_dac.h
  • LL_DAC_IsEnabled() : stm32f3xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR1() : stm32f3xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR2() : stm32f3xx_ll_dac.h
  • LL_DAC_IsTriggerEnabled() : stm32f3xx_ll_dac.h
  • LL_DAC_RetrieveOutputData() : stm32f3xx_ll_dac.h
  • LL_DAC_SetOutputBuffer() : stm32f3xx_ll_dac.h
  • LL_DAC_SetTriggerSource() : stm32f3xx_ll_dac.h
  • LL_DAC_SetWaveAutoGeneration() : stm32f3xx_ll_dac.h
  • LL_DAC_SetWaveNoiseLFSR() : stm32f3xx_ll_dac.h
  • LL_DAC_SetWaveTriangleAmplitude() : stm32f3xx_ll_dac.h
  • LL_DAC_StructInit() : stm32f3xx_ll_dac.c
  • LL_DAC_TrigSWConversion() : stm32f3xx_ll_dac.h
  • LL_DBGMCU_APB1_GRP1_FreezePeriph() : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_UnFreezePeriph() : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_FreezePeriph() : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_UnFreezePeriph() : stm32f3xx_ll_system.h
  • LL_DBGMCU_DisableDBGSleepMode() : stm32f3xx_ll_system.h
  • LL_DBGMCU_DisableDBGStandbyMode() : stm32f3xx_ll_system.h
  • LL_DBGMCU_DisableDBGStopMode() : stm32f3xx_ll_system.h
  • LL_DBGMCU_EnableDBGSleepMode() : stm32f3xx_ll_system.h
  • LL_DBGMCU_EnableDBGStandbyMode() : stm32f3xx_ll_system.h
  • LL_DBGMCU_EnableDBGStopMode() : stm32f3xx_ll_system.h
  • LL_DBGMCU_GetDeviceID() : stm32f3xx_ll_system.h
  • LL_DBGMCU_GetRevisionID() : stm32f3xx_ll_system.h
  • LL_DBGMCU_GetTracePinAssignment() : stm32f3xx_ll_system.h
  • LL_DBGMCU_SetTracePinAssignment() : stm32f3xx_ll_system.h
  • LL_DMA_ClearFlag_GI1() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_GI2() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_GI3() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_GI4() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_GI5() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_GI6() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_GI7() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_HT1() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_HT2() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_HT3() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_HT4() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_HT5() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_HT6() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_HT7() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TC1() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TC2() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TC3() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TC4() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TC5() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TC6() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TC7() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TE1() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TE2() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TE3() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TE4() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TE5() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TE6() : stm32f3xx_ll_dma.h
  • LL_DMA_ClearFlag_TE7() : stm32f3xx_ll_dma.h
  • LL_DMA_ConfigAddresses() : stm32f3xx_ll_dma.h
  • LL_DMA_ConfigTransfer() : stm32f3xx_ll_dma.h
  • LL_DMA_DeInit() : stm32f3xx_ll_dma.c
  • LL_DMA_DisableChannel() : stm32f3xx_ll_dma.h
  • LL_DMA_DisableIT_HT() : stm32f3xx_ll_dma.h
  • LL_DMA_DisableIT_TC() : stm32f3xx_ll_dma.h
  • LL_DMA_DisableIT_TE() : stm32f3xx_ll_dma.h
  • LL_DMA_EnableChannel() : stm32f3xx_ll_dma.h
  • LL_DMA_EnableIT_HT() : stm32f3xx_ll_dma.h
  • LL_DMA_EnableIT_TC() : stm32f3xx_ll_dma.h
  • LL_DMA_EnableIT_TE() : stm32f3xx_ll_dma.h
  • LL_DMA_GetChannelPriorityLevel() : stm32f3xx_ll_dma.h
  • LL_DMA_GetDataLength() : stm32f3xx_ll_dma.h
  • LL_DMA_GetDataTransferDirection() : stm32f3xx_ll_dma.h
  • LL_DMA_GetM2MDstAddress() : stm32f3xx_ll_dma.h
  • LL_DMA_GetM2MSrcAddress() : stm32f3xx_ll_dma.h
  • LL_DMA_GetMemoryAddress() : stm32f3xx_ll_dma.h
  • LL_DMA_GetMemoryIncMode() : stm32f3xx_ll_dma.h
  • LL_DMA_GetMemorySize() : stm32f3xx_ll_dma.h
  • LL_DMA_GetMode() : stm32f3xx_ll_dma.h
  • LL_DMA_GetPeriphAddress() : stm32f3xx_ll_dma.h
  • LL_DMA_GetPeriphIncMode() : stm32f3xx_ll_dma.h
  • LL_DMA_GetPeriphSize() : stm32f3xx_ll_dma.h
  • LL_DMA_Init() : stm32f3xx_ll_dma.c
  • LL_DMA_IsActiveFlag_GI1() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI2() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI3() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI4() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI5() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI6() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI7() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT1() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT2() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT3() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT4() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT5() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT6() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT7() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC1() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC2() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC3() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC4() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC5() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC6() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC7() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE1() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE2() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE3() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE4() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE5() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE6() : stm32f3xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE7() : stm32f3xx_ll_dma.h
  • LL_DMA_IsEnabledChannel() : stm32f3xx_ll_dma.h
  • LL_DMA_IsEnabledIT_HT() : stm32f3xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TC() : stm32f3xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TE() : stm32f3xx_ll_dma.h
  • LL_DMA_SetChannelPriorityLevel() : stm32f3xx_ll_dma.h
  • LL_DMA_SetDataLength() : stm32f3xx_ll_dma.h
  • LL_DMA_SetDataTransferDirection() : stm32f3xx_ll_dma.h
  • LL_DMA_SetM2MDstAddress() : stm32f3xx_ll_dma.h
  • LL_DMA_SetM2MSrcAddress() : stm32f3xx_ll_dma.h
  • LL_DMA_SetMemoryAddress() : stm32f3xx_ll_dma.h
  • LL_DMA_SetMemoryIncMode() : stm32f3xx_ll_dma.h
  • LL_DMA_SetMemorySize() : stm32f3xx_ll_dma.h
  • LL_DMA_SetMode() : stm32f3xx_ll_dma.h
  • LL_DMA_SetPeriphAddress() : stm32f3xx_ll_dma.h
  • LL_DMA_SetPeriphIncMode() : stm32f3xx_ll_dma.h
  • LL_DMA_SetPeriphSize() : stm32f3xx_ll_dma.h
  • LL_DMA_StructInit() : stm32f3xx_ll_dma.c
  • LL_EXTI_ClearFlag_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_DeInit() : stm32f3xx_ll_exti.c
  • LL_EXTI_DisableEvent_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_DisableIT_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_EnableEvent_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_EnableIT_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_GenerateSWI_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_Init() : stm32f3xx_ll_exti.c
  • LL_EXTI_IsActiveFlag_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_ReadFlag_0_31() : stm32f3xx_ll_exti.h
  • LL_EXTI_StructInit() : stm32f3xx_ll_exti.c
  • LL_FLASH_DisablePrefetch() : stm32f3xx_ll_system.h
  • LL_FLASH_EnablePrefetch() : stm32f3xx_ll_system.h
  • LL_FLASH_GetLatency() : stm32f3xx_ll_system.h
  • LL_FLASH_IsPrefetchEnabled() : stm32f3xx_ll_system.h
  • LL_FLASH_SetLatency() : stm32f3xx_ll_system.h
  • LL_GetFlashSize() : stm32f3xx_ll_utils.h
  • LL_GetUID_Word0() : stm32f3xx_ll_utils.h
  • LL_GetUID_Word1() : stm32f3xx_ll_utils.h
  • LL_GetUID_Word2() : stm32f3xx_ll_utils.h
  • LL_GPIO_DeInit() : stm32f3xx_ll_gpio.c
  • LL_GPIO_GetAFPin_0_7() : stm32f3xx_ll_gpio.h
  • LL_GPIO_GetAFPin_8_15() : stm32f3xx_ll_gpio.h
  • LL_GPIO_GetPinMode() : stm32f3xx_ll_gpio.h
  • LL_GPIO_GetPinOutputType() : stm32f3xx_ll_gpio.h
  • LL_GPIO_GetPinPull() : stm32f3xx_ll_gpio.h
  • LL_GPIO_GetPinSpeed() : stm32f3xx_ll_gpio.h
  • LL_GPIO_Init() : stm32f3xx_ll_gpio.c
  • LL_GPIO_IsAnyPinLocked() : stm32f3xx_ll_gpio.h
  • LL_GPIO_IsInputPinSet() : stm32f3xx_ll_gpio.h
  • LL_GPIO_IsOutputPinSet() : stm32f3xx_ll_gpio.h
  • LL_GPIO_IsPinLocked() : stm32f3xx_ll_gpio.h
  • LL_GPIO_LockPin() : stm32f3xx_ll_gpio.h
  • LL_GPIO_ReadInputPort() : stm32f3xx_ll_gpio.h
  • LL_GPIO_ReadOutputPort() : stm32f3xx_ll_gpio.h
  • LL_GPIO_ResetOutputPin() : stm32f3xx_ll_gpio.h
  • LL_GPIO_SetAFPin_0_7() : stm32f3xx_ll_gpio.h
  • LL_GPIO_SetAFPin_8_15() : stm32f3xx_ll_gpio.h
  • LL_GPIO_SetOutputPin() : stm32f3xx_ll_gpio.h
  • LL_GPIO_SetPinMode() : stm32f3xx_ll_gpio.h
  • LL_GPIO_SetPinOutputType() : stm32f3xx_ll_gpio.h
  • LL_GPIO_SetPinPull() : stm32f3xx_ll_gpio.h
  • LL_GPIO_SetPinSpeed() : stm32f3xx_ll_gpio.h
  • LL_GPIO_StructInit() : stm32f3xx_ll_gpio.c
  • LL_GPIO_TogglePin() : stm32f3xx_ll_gpio.h
  • LL_GPIO_WriteOutputPort() : stm32f3xx_ll_gpio.h
  • LL_HANDLER_DisableFault() : stm32f3xx_ll_cortex.h
  • LL_HANDLER_EnableFault() : stm32f3xx_ll_cortex.h
  • LL_I2C_AcknowledgeNextData() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearFlag_ADDR() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearFlag_ARLO() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearFlag_BERR() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearFlag_NACK() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearFlag_OVR() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearFlag_STOP() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearFlag_TXE() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_ALERT() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_PECERR() : stm32f3xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_TIMEOUT() : stm32f3xx_ll_i2c.h
  • LL_I2C_ConfigFilters() : stm32f3xx_ll_i2c.h
  • LL_I2C_ConfigSMBusTimeout() : stm32f3xx_ll_i2c.h
  • LL_I2C_DeInit() : stm32f3xx_ll_i2c.c
  • LL_I2C_Disable() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableAnalogFilter() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableAuto10BitRead() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableAutoEndMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableClockStretching() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_RX() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_TX() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableGeneralCall() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableIT_ADDR() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableIT_ERR() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableIT_NACK() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableIT_RX() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableIT_STOP() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableIT_TC() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableIT_TX() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress1() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress2() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableReloadMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableSlaveByteControl() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableSMBusAlert() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableSMBusPEC() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableSMBusTimeout() : stm32f3xx_ll_i2c.h
  • LL_I2C_DisableWakeUpFromStop() : stm32f3xx_ll_i2c.h
  • LL_I2C_DMA_GetRegAddr() : stm32f3xx_ll_i2c.h
  • LL_I2C_Enable() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableAnalogFilter() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableAuto10BitRead() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableAutoEndMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableClockStretching() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_RX() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_TX() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableGeneralCall() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableIT_ADDR() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableIT_ERR() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableIT_NACK() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableIT_RX() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableIT_STOP() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableIT_TC() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableIT_TX() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress1() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress2() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableReloadMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableSlaveByteControl() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableSMBusAlert() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableSMBusPEC() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableSMBusPECCompare() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableSMBusTimeout() : stm32f3xx_ll_i2c.h
  • LL_I2C_EnableWakeUpFromStop() : stm32f3xx_ll_i2c.h
  • LL_I2C_GenerateStartCondition() : stm32f3xx_ll_i2c.h
  • LL_I2C_GenerateStopCondition() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetAddressMatchCode() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetClockHighPeriod() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetClockLowPeriod() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetDataHoldTime() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetDataSetupTime() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetDigitalFilter() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetMasterAddressingMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetSlaveAddr() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetSMBusPEC() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutA() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutAMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutB() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetTimingPrescaler() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetTransferDirection() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetTransferRequest() : stm32f3xx_ll_i2c.h
  • LL_I2C_GetTransferSize() : stm32f3xx_ll_i2c.h
  • LL_I2C_HandleTransfer() : stm32f3xx_ll_i2c.h
  • LL_I2C_Init() : stm32f3xx_ll_i2c.c
  • LL_I2C_IsActiveFlag_ADDR() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_ARLO() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BERR() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BUSY() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_NACK() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_OVR() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_RXNE() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_STOP() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TC() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TCR() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXE() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXIS() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_ALERT() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_PECERR() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_TIMEOUT() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabled() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledAnalogFilter() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledAuto10BitRead() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledAutoEndMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledClockStretching() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_RX() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_TX() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledGeneralCall() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ADDR() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ERR() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_NACK() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_RX() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_STOP() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TC() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TX() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress1() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress2() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledReloadMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledSlaveByteControl() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusAlert() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPEC() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPECCompare() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusTimeout() : stm32f3xx_ll_i2c.h
  • LL_I2C_IsEnabledWakeUpFromStop() : stm32f3xx_ll_i2c.h
  • LL_I2C_ReceiveData8() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetDigitalFilter() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetMasterAddressingMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetOwnAddress1() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetOwnAddress2() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetSlaveAddr() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutA() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutAMode() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutB() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetTiming() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetTransferRequest() : stm32f3xx_ll_i2c.h
  • LL_I2C_SetTransferSize() : stm32f3xx_ll_i2c.h
  • LL_I2C_StructInit() : stm32f3xx_ll_i2c.c
  • LL_I2C_TransmitData8() : stm32f3xx_ll_i2c.h
  • LL_I2S_ClearFlag_FRE() : stm32f3xx_ll_spi.h
  • LL_I2S_ClearFlag_OVR() : stm32f3xx_ll_spi.h
  • LL_I2S_ClearFlag_UDR() : stm32f3xx_ll_spi.h
  • LL_I2S_ConfigPrescaler() : stm32f3xx_ll_spi.c
  • LL_I2S_DeInit() : stm32f3xx_ll_spi.c
  • LL_I2S_Disable() : stm32f3xx_ll_spi.h
  • LL_I2S_DisableDMAReq_RX() : stm32f3xx_ll_spi.h
  • LL_I2S_DisableDMAReq_TX() : stm32f3xx_ll_spi.h
  • LL_I2S_DisableIT_ERR() : stm32f3xx_ll_spi.h
  • LL_I2S_DisableIT_RXNE() : stm32f3xx_ll_spi.h
  • LL_I2S_DisableIT_TXE() : stm32f3xx_ll_spi.h
  • LL_I2S_DisableMasterClock() : stm32f3xx_ll_spi.h
  • LL_I2S_Enable() : stm32f3xx_ll_spi.h
  • LL_I2S_EnableDMAReq_RX() : stm32f3xx_ll_spi.h
  • LL_I2S_EnableDMAReq_TX() : stm32f3xx_ll_spi.h
  • LL_I2S_EnableIT_ERR() : stm32f3xx_ll_spi.h
  • LL_I2S_EnableIT_RXNE() : stm32f3xx_ll_spi.h
  • LL_I2S_EnableIT_TXE() : stm32f3xx_ll_spi.h
  • LL_I2S_EnableMasterClock() : stm32f3xx_ll_spi.h
  • LL_I2S_GetClockPolarity() : stm32f3xx_ll_spi.h
  • LL_I2S_GetDataFormat() : stm32f3xx_ll_spi.h
  • LL_I2S_GetPrescalerLinear() : stm32f3xx_ll_spi.h
  • LL_I2S_GetPrescalerParity() : stm32f3xx_ll_spi.h
  • LL_I2S_GetStandard() : stm32f3xx_ll_spi.h
  • LL_I2S_GetTransferMode() : stm32f3xx_ll_spi.h
  • LL_I2S_Init() : stm32f3xx_ll_spi.c
  • LL_I2S_IsActiveFlag_BSY() : stm32f3xx_ll_spi.h
  • LL_I2S_IsActiveFlag_CHSIDE() : stm32f3xx_ll_spi.h
  • LL_I2S_IsActiveFlag_FRE() : stm32f3xx_ll_spi.h
  • LL_I2S_IsActiveFlag_OVR() : stm32f3xx_ll_spi.h
  • LL_I2S_IsActiveFlag_RXNE() : stm32f3xx_ll_spi.h
  • LL_I2S_IsActiveFlag_TXE() : stm32f3xx_ll_spi.h
  • LL_I2S_IsActiveFlag_UDR() : stm32f3xx_ll_spi.h
  • LL_I2S_IsEnabled() : stm32f3xx_ll_spi.h
  • LL_I2S_IsEnabledDMAReq_RX() : stm32f3xx_ll_spi.h
  • LL_I2S_IsEnabledDMAReq_TX() : stm32f3xx_ll_spi.h
  • LL_I2S_IsEnabledIT_ERR() : stm32f3xx_ll_spi.h
  • LL_I2S_IsEnabledIT_RXNE() : stm32f3xx_ll_spi.h
  • LL_I2S_IsEnabledIT_TXE() : stm32f3xx_ll_spi.h
  • LL_I2S_IsEnabledMasterClock() : stm32f3xx_ll_spi.h
  • LL_I2S_ReceiveData16() : stm32f3xx_ll_spi.h
  • LL_I2S_SetClockPolarity() : stm32f3xx_ll_spi.h
  • LL_I2S_SetDataFormat() : stm32f3xx_ll_spi.h
  • LL_I2S_SetPrescalerLinear() : stm32f3xx_ll_spi.h
  • LL_I2S_SetPrescalerParity() : stm32f3xx_ll_spi.h
  • LL_I2S_SetStandard() : stm32f3xx_ll_spi.h
  • LL_I2S_SetTransferMode() : stm32f3xx_ll_spi.h
  • LL_I2S_StructInit() : stm32f3xx_ll_spi.c
  • LL_I2S_TransmitData16() : stm32f3xx_ll_spi.h
  • LL_Init1msTick() : stm32f3xx_ll_utils.c
  • LL_InitTick() : stm32f3xx_ll_utils.h
  • LL_IWDG_DisableWriteAccess() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_Enable() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_EnableWriteAccess() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_GetPrescaler() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_GetReloadCounter() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_GetWindow() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_PVU() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_RVU() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_WVU() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_IsReady() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_ReloadCounter() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_SetPrescaler() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_SetReloadCounter() : stm32f3xx_ll_iwdg.h
  • LL_IWDG_SetWindow() : stm32f3xx_ll_iwdg.h
  • LL_LPM_DisableEventOnPend() : stm32f3xx_ll_cortex.h
  • LL_LPM_DisableSleepOnExit() : stm32f3xx_ll_cortex.h
  • LL_LPM_EnableDeepSleep() : stm32f3xx_ll_cortex.h
  • LL_LPM_EnableEventOnPend() : stm32f3xx_ll_cortex.h
  • LL_LPM_EnableSleep() : stm32f3xx_ll_cortex.h
  • LL_LPM_EnableSleepOnExit() : stm32f3xx_ll_cortex.h
  • LL_mDelay() : stm32f3xx_ll_utils.c
  • LL_MPU_ConfigRegion() : stm32f3xx_ll_cortex.h
  • LL_MPU_Disable() : stm32f3xx_ll_cortex.h
  • LL_MPU_DisableRegion() : stm32f3xx_ll_cortex.h
  • LL_MPU_Enable() : stm32f3xx_ll_cortex.h
  • LL_MPU_EnableRegion() : stm32f3xx_ll_cortex.h
  • LL_MPU_IsEnabled() : stm32f3xx_ll_cortex.h
  • LL_PLL_ConfigSystemClock_HSE() : stm32f3xx_ll_utils.c
  • LL_PLL_ConfigSystemClock_HSI() : stm32f3xx_ll_utils.c
  • LL_PWR_ClearFlag_SB() : stm32f3xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU() : stm32f3xx_ll_pwr.h
  • LL_PWR_DeInit() : stm32f3xx_ll_pwr.c
  • LL_PWR_DisableBkUpAccess() : stm32f3xx_ll_pwr.h
  • LL_PWR_DisablePVD() : stm32f3xx_ll_pwr.h
  • LL_PWR_DisableSDADC() : stm32f3xx_ll_pwr.h
  • LL_PWR_DisableWakeUpPin() : stm32f3xx_ll_pwr.h
  • LL_PWR_EnableBkUpAccess() : stm32f3xx_ll_pwr.h
  • LL_PWR_EnablePVD() : stm32f3xx_ll_pwr.h
  • LL_PWR_EnableSDADC() : stm32f3xx_ll_pwr.h
  • LL_PWR_EnableWakeUpPin() : stm32f3xx_ll_pwr.h
  • LL_PWR_GetPowerMode() : stm32f3xx_ll_pwr.h
  • LL_PWR_GetPVDLevel() : stm32f3xx_ll_pwr.h
  • LL_PWR_GetRegulModeDS() : stm32f3xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVDO() : stm32f3xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_SB() : stm32f3xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VREFINTRDY() : stm32f3xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU() : stm32f3xx_ll_pwr.h
  • LL_PWR_IsEnabledBkUpAccess() : stm32f3xx_ll_pwr.h
  • LL_PWR_IsEnabledPVD() : stm32f3xx_ll_pwr.h
  • LL_PWR_IsEnabledSDADC() : stm32f3xx_ll_pwr.h
  • LL_PWR_IsEnabledWakeUpPin() : stm32f3xx_ll_pwr.h
  • LL_PWR_SetPowerMode() : stm32f3xx_ll_pwr.h
  • LL_PWR_SetPVDLevel() : stm32f3xx_ll_pwr.h
  • LL_PWR_SetRegulModeDS() : stm32f3xx_ll_pwr.h
  • LL_RCC_ClearFlag_HSECSS() : stm32f3xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_ClearResetFlags() : stm32f3xx_ll_rcc.h
  • LL_RCC_ConfigMCO() : stm32f3xx_ll_rcc.h
  • LL_RCC_DeInit() : stm32f3xx_ll_rcc.c
  • LL_RCC_DisableIT_HSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_DisableIT_HSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_DisableIT_LSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_DisableIT_LSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_DisableIT_PLLRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_DisableRTC() : stm32f3xx_ll_rcc.h
  • LL_RCC_EnableIT_HSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_EnableIT_HSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_EnableIT_LSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_EnableIT_LSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_EnableIT_PLLRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_EnableRTC() : stm32f3xx_ll_rcc.h
  • LL_RCC_ForceBackupDomainReset() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetADCClockFreq() : stm32f3xx_ll_rcc.c
  • LL_RCC_GetADCClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetAHBPrescaler() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetAPB1Prescaler() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetAPB2Prescaler() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetCECClockFreq() : stm32f3xx_ll_rcc.c
  • LL_RCC_GetCECClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetHRTIMClockFreq() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetI2CClockFreq() : stm32f3xx_ll_rcc.c
  • LL_RCC_GetI2CClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetRTCClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetSDADCClockFreq() : stm32f3xx_ll_rcc.c
  • LL_RCC_GetSDADCClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetSysClkSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetSystemClocksFreq() : stm32f3xx_ll_rcc.c
  • LL_RCC_GetUSARTClockFreq() : stm32f3xx_ll_rcc.c
  • LL_RCC_GetUSARTClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_GetUSBClockFreq() : stm32f3xx_ll_rcc.c
  • LL_RCC_GetUSBClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSE_Disable() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSE_DisableBypass() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSE_DisableCSS() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSE_Enable() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSE_EnableBypass() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSE_EnableCSS() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSE_IsReady() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSI_Disable() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSI_Enable() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibration() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibTrimming() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSI_IsReady() : stm32f3xx_ll_rcc.h
  • LL_RCC_HSI_SetCalibTrimming() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSECSS() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_IWDGRST() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LPWRRST() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_OBLRST() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PINRST() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PORRST() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_SFTRST() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_V18PWRRST() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_WWDGRST() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSERDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSIRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLRDY() : stm32f3xx_ll_rcc.h
  • LL_RCC_IsEnabledRTC() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSE_Disable() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSE_DisableBypass() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSE_Enable() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSE_EnableBypass() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSE_GetDriveCapability() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSE_IsReady() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSE_SetDriveCapability() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSI_Disable() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSI_Enable() : stm32f3xx_ll_rcc.h
  • LL_RCC_LSI_IsReady() : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_SYS() : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_Disable() : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_Enable() : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_GetMainSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_GetMultiplicator() : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_GetPrediv() : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_IsReady() : stm32f3xx_ll_rcc.h
  • LL_RCC_ReleaseBackupDomainReset() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetADCClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetAHBPrescaler() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetAPB1Prescaler() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetAPB2Prescaler() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetCECClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetI2CClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetRTCClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetSDADCClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetSysClkSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetUSARTClockSource() : stm32f3xx_ll_rcc.h
  • LL_RCC_SetUSBClockSource() : stm32f3xx_ll_rcc.h
  • LL_RTC_ALMA_ConfigTime() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_Disable() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_DisableWeekday() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_Enable() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_EnableWeekday() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetMask() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetMinute() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecondMask() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetTime() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetTimeFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_GetWeekDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_Init() : stm32f3xx_ll_rtc.c
  • LL_RTC_ALMA_SetDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_SetHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_SetMask() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_SetMinute() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_SetSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecondMask() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_SetTimeFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_SetWeekDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_StructInit() : stm32f3xx_ll_rtc.c
  • LL_RTC_ALMB_ConfigTime() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_Disable() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_DisableWeekday() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_Enable() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_EnableWeekday() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetMask() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetMinute() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecondMask() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetTime() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetTimeFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_GetWeekDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_Init() : stm32f3xx_ll_rtc.c
  • LL_RTC_ALMB_SetDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_SetHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_SetMask() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_SetMinute() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_SetSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecondMask() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_SetTimeFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_SetWeekDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_StructInit() : stm32f3xx_ll_rtc.c
  • LL_RTC_BAK_GetRegister() : stm32f3xx_ll_rtc.h
  • LL_RTC_BAK_SetRegister() : stm32f3xx_ll_rtc.h
  • LL_RTC_CAL_GetMinus() : stm32f3xx_ll_rtc.h
  • LL_RTC_CAL_GetOutputFreq() : stm32f3xx_ll_rtc.h
  • LL_RTC_CAL_GetPeriod() : stm32f3xx_ll_rtc.h
  • LL_RTC_CAL_IsPulseInserted() : stm32f3xx_ll_rtc.h
  • LL_RTC_CAL_SetMinus() : stm32f3xx_ll_rtc.h
  • LL_RTC_CAL_SetOutputFreq() : stm32f3xx_ll_rtc.h
  • LL_RTC_CAL_SetPeriod() : stm32f3xx_ll_rtc.h
  • LL_RTC_CAL_SetPulse() : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRA() : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRB() : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_RS() : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP1() : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP2() : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP3() : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_TS() : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_TSOV() : stm32f3xx_ll_rtc.h
  • LL_RTC_ClearFlag_WUT() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_Config() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_Get() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_GetDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_GetMonth() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_GetWeekDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_GetYear() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_Init() : stm32f3xx_ll_rtc.c
  • LL_RTC_DATE_SetDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_SetMonth() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_SetWeekDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_SetYear() : stm32f3xx_ll_rtc.h
  • LL_RTC_DATE_StructInit() : stm32f3xx_ll_rtc.c
  • LL_RTC_DeInit() : stm32f3xx_ll_rtc.c
  • LL_RTC_DisableInitMode() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRA() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRB() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisableIT_TS() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisableIT_WUT() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisablePushPullMode() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisableRefClock() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisableShadowRegBypass() : stm32f3xx_ll_rtc.h
  • LL_RTC_DisableWriteProtection() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableInitMode() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRA() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRB() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableIT_TS() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableIT_WUT() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnablePushPullMode() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableRefClock() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableShadowRegBypass() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnableWriteProtection() : stm32f3xx_ll_rtc.h
  • LL_RTC_EnterInitMode() : stm32f3xx_ll_rtc.c
  • LL_RTC_ExitInitMode() : stm32f3xx_ll_rtc.c
  • LL_RTC_GetAlarmOutEvent() : stm32f3xx_ll_rtc.h
  • LL_RTC_GetAlarmOutputType() : stm32f3xx_ll_rtc.h
  • LL_RTC_GetAsynchPrescaler() : stm32f3xx_ll_rtc.h
  • LL_RTC_GetHourFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_GetOutputPolarity() : stm32f3xx_ll_rtc.h
  • LL_RTC_GetSynchPrescaler() : stm32f3xx_ll_rtc.h
  • LL_RTC_Init() : stm32f3xx_ll_rtc.c
  • LL_RTC_IsActiveFlag_ALRA() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAW() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRB() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBW() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INIT() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INITS() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RECALP() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RS() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_SHP() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TS() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOV() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUT() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTW() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRA() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRB() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TS() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_WUT() : stm32f3xx_ll_rtc.h
  • LL_RTC_IsShadowRegBypassEnabled() : stm32f3xx_ll_rtc.h
  • LL_RTC_ResetOutputPin() : stm32f3xx_ll_rtc.h
  • LL_RTC_SetAlarmOutEvent() : stm32f3xx_ll_rtc.h
  • LL_RTC_SetAlarmOutputType() : stm32f3xx_ll_rtc.h
  • LL_RTC_SetAsynchPrescaler() : stm32f3xx_ll_rtc.h
  • LL_RTC_SetHourFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_SetOutputPin() : stm32f3xx_ll_rtc.h
  • LL_RTC_SetOutputPolarity() : stm32f3xx_ll_rtc.h
  • LL_RTC_SetSynchPrescaler() : stm32f3xx_ll_rtc.h
  • LL_RTC_StructInit() : stm32f3xx_ll_rtc.c
  • LL_RTC_TAMPER_Disable() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableActiveLevel() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_DisablePullUp() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_Enable() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableActiveLevel() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_EnablePullUp() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_GetFilterCount() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_GetPrecharge() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_GetSamplingFreq() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SetFilterCount() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SetPrecharge() : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SetSamplingFreq() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_Config() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_DecHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_DisableDayLightStore() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_EnableDayLightStore() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_Get() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_GetFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_GetHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_GetMinute() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_GetSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_GetSubSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_IncHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_Init() : stm32f3xx_ll_rtc.c
  • LL_RTC_TIME_IsDayLightStoreEnabled() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_SetFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_SetHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_SetMinute() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_SetSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_StructInit() : stm32f3xx_ll_rtc.c
  • LL_RTC_TIME_Synchronize() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_Disable() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_DisableOnTamper() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_Enable() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_EnableOnTamper() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetActiveEdge() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetDate() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetHour() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetMinute() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetMonth() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetSubSecond() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetTime() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetTimeFormat() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_GetWeekDay() : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_SetActiveEdge() : stm32f3xx_ll_rtc.h
  • LL_RTC_WaitForSynchro() : stm32f3xx_ll_rtc.c
  • LL_RTC_WAKEUP_Disable() : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUP_Enable() : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetAutoReload() : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetClock() : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUP_IsEnabled() : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetAutoReload() : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetClock() : stm32f3xx_ll_rtc.h
  • LL_SetSystemCoreClock() : stm32f3xx_ll_utils.c
  • LL_SPI_ClearFlag_CRCERR() : stm32f3xx_ll_spi.h
  • LL_SPI_ClearFlag_FRE() : stm32f3xx_ll_spi.h
  • LL_SPI_ClearFlag_MODF() : stm32f3xx_ll_spi.h
  • LL_SPI_ClearFlag_OVR() : stm32f3xx_ll_spi.h
  • LL_SPI_DeInit() : stm32f3xx_ll_spi.c
  • LL_SPI_Disable() : stm32f3xx_ll_spi.h
  • LL_SPI_DisableCRC() : stm32f3xx_ll_spi.h
  • LL_SPI_DisableDMAReq_RX() : stm32f3xx_ll_spi.h
  • LL_SPI_DisableDMAReq_TX() : stm32f3xx_ll_spi.h
  • LL_SPI_DisableIT_ERR() : stm32f3xx_ll_spi.h
  • LL_SPI_DisableIT_RXNE() : stm32f3xx_ll_spi.h
  • LL_SPI_DisableIT_TXE() : stm32f3xx_ll_spi.h
  • LL_SPI_DisableNSSPulseMgt() : stm32f3xx_ll_spi.h
  • LL_SPI_DMA_GetRegAddr() : stm32f3xx_ll_spi.h
  • LL_SPI_Enable() : stm32f3xx_ll_spi.h
  • LL_SPI_EnableCRC() : stm32f3xx_ll_spi.h
  • LL_SPI_EnableDMAReq_RX() : stm32f3xx_ll_spi.h
  • LL_SPI_EnableDMAReq_TX() : stm32f3xx_ll_spi.h
  • LL_SPI_EnableIT_ERR() : stm32f3xx_ll_spi.h
  • LL_SPI_EnableIT_RXNE() : stm32f3xx_ll_spi.h
  • LL_SPI_EnableIT_TXE() : stm32f3xx_ll_spi.h
  • LL_SPI_EnableNSSPulseMgt() : stm32f3xx_ll_spi.h
  • LL_SPI_GetBaudRatePrescaler() : stm32f3xx_ll_spi.h
  • LL_SPI_GetClockPhase() : stm32f3xx_ll_spi.h
  • LL_SPI_GetClockPolarity() : stm32f3xx_ll_spi.h
  • LL_SPI_GetCRCPolynomial() : stm32f3xx_ll_spi.h
  • LL_SPI_GetCRCWidth() : stm32f3xx_ll_spi.h
  • LL_SPI_GetDataWidth() : stm32f3xx_ll_spi.h
  • LL_SPI_GetDMAParity_RX() : stm32f3xx_ll_spi.h
  • LL_SPI_GetDMAParity_TX() : stm32f3xx_ll_spi.h
  • LL_SPI_GetMode() : stm32f3xx_ll_spi.h
  • LL_SPI_GetNSSMode() : stm32f3xx_ll_spi.h
  • LL_SPI_GetRxCRC() : stm32f3xx_ll_spi.h
  • LL_SPI_GetRxFIFOLevel() : stm32f3xx_ll_spi.h
  • LL_SPI_GetRxFIFOThreshold() : stm32f3xx_ll_spi.h
  • LL_SPI_GetStandard() : stm32f3xx_ll_spi.h
  • LL_SPI_GetTransferBitOrder() : stm32f3xx_ll_spi.h
  • LL_SPI_GetTransferDirection() : stm32f3xx_ll_spi.h
  • LL_SPI_GetTxCRC() : stm32f3xx_ll_spi.h
  • LL_SPI_GetTxFIFOLevel() : stm32f3xx_ll_spi.h
  • LL_SPI_Init() : stm32f3xx_ll_spi.c
  • LL_SPI_IsActiveFlag_BSY() : stm32f3xx_ll_spi.h
  • LL_SPI_IsActiveFlag_CRCERR() : stm32f3xx_ll_spi.h
  • LL_SPI_IsActiveFlag_FRE() : stm32f3xx_ll_spi.h
  • LL_SPI_IsActiveFlag_MODF() : stm32f3xx_ll_spi.h
  • LL_SPI_IsActiveFlag_OVR() : stm32f3xx_ll_spi.h
  • LL_SPI_IsActiveFlag_RXNE() : stm32f3xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXE() : stm32f3xx_ll_spi.h
  • LL_SPI_IsEnabled() : stm32f3xx_ll_spi.h
  • LL_SPI_IsEnabledCRC() : stm32f3xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_RX() : stm32f3xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_TX() : stm32f3xx_ll_spi.h
  • LL_SPI_IsEnabledIT_ERR() : stm32f3xx_ll_spi.h
  • LL_SPI_IsEnabledIT_RXNE() : stm32f3xx_ll_spi.h
  • LL_SPI_IsEnabledIT_TXE() : stm32f3xx_ll_spi.h
  • LL_SPI_IsEnabledNSSPulse() : stm32f3xx_ll_spi.h
  • LL_SPI_ReceiveData16() : stm32f3xx_ll_spi.h
  • LL_SPI_ReceiveData8() : stm32f3xx_ll_spi.h
  • LL_SPI_SetBaudRatePrescaler() : stm32f3xx_ll_spi.h
  • LL_SPI_SetClockPhase() : stm32f3xx_ll_spi.h
  • LL_SPI_SetClockPolarity() : stm32f3xx_ll_spi.h
  • LL_SPI_SetCRCNext() : stm32f3xx_ll_spi.h
  • LL_SPI_SetCRCPolynomial() : stm32f3xx_ll_spi.h
  • LL_SPI_SetCRCWidth() : stm32f3xx_ll_spi.h
  • LL_SPI_SetDataWidth() : stm32f3xx_ll_spi.h
  • LL_SPI_SetDMAParity_RX() : stm32f3xx_ll_spi.h
  • LL_SPI_SetDMAParity_TX() : stm32f3xx_ll_spi.h
  • LL_SPI_SetMode() : stm32f3xx_ll_spi.h
  • LL_SPI_SetNSSMode() : stm32f3xx_ll_spi.h
  • LL_SPI_SetRxFIFOThreshold() : stm32f3xx_ll_spi.h
  • LL_SPI_SetStandard() : stm32f3xx_ll_spi.h
  • LL_SPI_SetTransferBitOrder() : stm32f3xx_ll_spi.h
  • LL_SPI_SetTransferDirection() : stm32f3xx_ll_spi.h
  • LL_SPI_StructInit() : stm32f3xx_ll_spi.c
  • LL_SPI_TransmitData16() : stm32f3xx_ll_spi.h
  • LL_SPI_TransmitData8() : stm32f3xx_ll_spi.h
  • LL_SYSCFG_ClearFlag_SP() : stm32f3xx_ll_system.h
  • LL_SYSCFG_DisableFastModePlus() : stm32f3xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_DZC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IDC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IOC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IXC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_OFC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_UFC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_DisableVBATMonitoring() : stm32f3xx_ll_system.h
  • LL_SYSCFG_EnableFastModePlus() : stm32f3xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_DZC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IDC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IOC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IXC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_OFC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_UFC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_EnableVBATMonitoring() : stm32f3xx_ll_system.h
  • LL_SYSCFG_GetEXTISource() : stm32f3xx_ll_system.h
  • LL_SYSCFG_GetRemapMemory() : stm32f3xx_ll_system.h
  • LL_SYSCFG_GetTIMBreakInputs() : stm32f3xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_SP() : stm32f3xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_DZC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IDC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IOC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IXC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_OFC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_UFC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_SetEXTISource() : stm32f3xx_ll_system.h
  • LL_SYSCFG_SetRemapDMA_DAC() : stm32f3xx_ll_system.h
  • LL_SYSCFG_SetRemapDMA_TIM() : stm32f3xx_ll_system.h
  • LL_SYSCFG_SetRemapMemory() : stm32f3xx_ll_system.h
  • LL_SYSCFG_SetTIMBreakInputs() : stm32f3xx_ll_system.h
  • LL_SYSTICK_DisableIT() : stm32f3xx_ll_cortex.h
  • LL_SYSTICK_EnableIT() : stm32f3xx_ll_cortex.h
  • LL_SYSTICK_GetClkSource() : stm32f3xx_ll_cortex.h
  • LL_SYSTICK_IsActiveCounterFlag() : stm32f3xx_ll_cortex.h
  • LL_SYSTICK_IsEnabledIT() : stm32f3xx_ll_cortex.h
  • LL_SYSTICK_SetClkSource() : stm32f3xx_ll_cortex.h
  • LL_TIM_BDTR_Init() : stm32f3xx_ll_tim.c
  • LL_TIM_BDTR_StructInit() : stm32f3xx_ll_tim.c
  • LL_TIM_CC_DisableChannel() : stm32f3xx_ll_tim.h
  • LL_TIM_CC_DisablePreload() : stm32f3xx_ll_tim.h
  • LL_TIM_CC_EnableChannel() : stm32f3xx_ll_tim.h
  • LL_TIM_CC_EnablePreload() : stm32f3xx_ll_tim.h
  • LL_TIM_CC_GetDMAReqTrigger() : stm32f3xx_ll_tim.h
  • LL_TIM_CC_IsEnabledChannel() : stm32f3xx_ll_tim.h
  • LL_TIM_CC_SetDMAReqTrigger() : stm32f3xx_ll_tim.h
  • LL_TIM_CC_SetLockLevel() : stm32f3xx_ll_tim.h
  • LL_TIM_CC_SetUpdate() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1OVR() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2OVR() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3OVR() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4OVR() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_ClearFlag_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_ConfigBRK() : stm32f3xx_ll_tim.h
  • LL_TIM_ConfigDMABurst() : stm32f3xx_ll_tim.h
  • LL_TIM_ConfigETR() : stm32f3xx_ll_tim.h
  • LL_TIM_DeInit() : stm32f3xx_ll_tim.c
  • LL_TIM_DisableAllOutputs() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableARRPreload() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableAutomaticOutput() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableBRK() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableCounter() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableDMAReq_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableDMAReq_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableDMAReq_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableExternalClock() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableIT_BRK() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableIT_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableIT_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableIT_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableIT_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableIT_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableIT_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableIT_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableMasterSlaveMode() : stm32f3xx_ll_tim.h
  • LL_TIM_DisableUpdateEvent() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableAllOutputs() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableARRPreload() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableAutomaticOutput() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableBRK() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableCounter() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableDMAReq_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableDMAReq_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableDMAReq_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableExternalClock() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableIT_BRK() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableIT_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableIT_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableIT_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableIT_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableIT_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableIT_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableIT_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableMasterSlaveMode() : stm32f3xx_ll_tim.h
  • LL_TIM_EnableUpdateEvent() : stm32f3xx_ll_tim.h
  • LL_TIM_ENCODER_Init() : stm32f3xx_ll_tim.c
  • LL_TIM_ENCODER_StructInit() : stm32f3xx_ll_tim.c
  • LL_TIM_GenerateEvent_BRK() : stm32f3xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_GenerateEvent_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_GenerateEvent_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_GenerateEvent_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_GetAutoReload() : stm32f3xx_ll_tim.h
  • LL_TIM_GetClockDivision() : stm32f3xx_ll_tim.h
  • LL_TIM_GetCounter() : stm32f3xx_ll_tim.h
  • LL_TIM_GetCounterMode() : stm32f3xx_ll_tim.h
  • LL_TIM_GetDirection() : stm32f3xx_ll_tim.h
  • LL_TIM_GetOnePulseMode() : stm32f3xx_ll_tim.h
  • LL_TIM_GetPrescaler() : stm32f3xx_ll_tim.h
  • LL_TIM_GetRepetitionCounter() : stm32f3xx_ll_tim.h
  • LL_TIM_GetUpdateSource() : stm32f3xx_ll_tim.h
  • LL_TIM_HALLSENSOR_Init() : stm32f3xx_ll_tim.h
  • LL_TIM_HALLSENSOR_StructInit() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_Config() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_DisableXORCombination() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_EnableXORCombination() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_GetActiveInput() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH1() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH2() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH3() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH4() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_GetFilter() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_GetPolarity() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_GetPrescaler() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_Init() : stm32f3xx_ll_tim.c
  • LL_TIM_IC_IsEnabledXORCombination() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_SetActiveInput() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_SetFilter() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_SetPolarity() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_SetPrescaler() : stm32f3xx_ll_tim.h
  • LL_TIM_IC_StructInit() : stm32f3xx_ll_tim.c
  • LL_TIM_Init() : stm32f3xx_ll_tim.c
  • LL_TIM_IsActiveFlag_BRK() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1OVR() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2OVR() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3OVR() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4OVR() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_IsActiveFlag_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledAllOutputs() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledARRPreload() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledAutomaticOutput() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledCounter() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledExternalClock() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledIT_BRK() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC1() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC2() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC3() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC4() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledIT_COM() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledIT_TRIG() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledIT_UPDATE() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledMasterSlaveMode() : stm32f3xx_ll_tim.h
  • LL_TIM_IsEnabledUpdateEvent() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_ConfigOutput() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_DisableClear() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_DisableFast() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_DisablePreload() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_EnableClear() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_EnableFast() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_EnablePreload() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH1() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH2() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH3() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH4() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_GetIdleState() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_GetMode() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_GetPolarity() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_Init() : stm32f3xx_ll_tim.c
  • LL_TIM_OC_IsEnabledClear() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_IsEnabledFast() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_IsEnabledPreload() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH1() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH2() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH3() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH4() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_SetDeadTime() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_SetIdleState() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_SetMode() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_SetPolarity() : stm32f3xx_ll_tim.h
  • LL_TIM_OC_StructInit() : stm32f3xx_ll_tim.c
  • LL_TIM_SetAutoReload() : stm32f3xx_ll_tim.h
  • LL_TIM_SetClockDivision() : stm32f3xx_ll_tim.h
  • LL_TIM_SetClockSource() : stm32f3xx_ll_tim.h
  • LL_TIM_SetCounter() : stm32f3xx_ll_tim.h
  • LL_TIM_SetCounterMode() : stm32f3xx_ll_tim.h
  • LL_TIM_SetEncoderMode() : stm32f3xx_ll_tim.h
  • LL_TIM_SetOffStates() : stm32f3xx_ll_tim.h
  • LL_TIM_SetOnePulseMode() : stm32f3xx_ll_tim.h
  • LL_TIM_SetPrescaler() : stm32f3xx_ll_tim.h
  • LL_TIM_SetRemap() : stm32f3xx_ll_tim.h
  • LL_TIM_SetRepetitionCounter() : stm32f3xx_ll_tim.h
  • LL_TIM_SetSlaveMode() : stm32f3xx_ll_tim.h
  • LL_TIM_SetTriggerInput() : stm32f3xx_ll_tim.h
  • LL_TIM_SetTriggerOutput() : stm32f3xx_ll_tim.h
  • LL_TIM_SetUpdateSource() : stm32f3xx_ll_tim.h
  • LL_TIM_StructInit() : stm32f3xx_ll_tim.c
  • LL_USART_ClearFlag_CM() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_EOB() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_FE() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_IDLE() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_LBD() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_nCTS() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_NE() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_ORE() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_PE() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_RTO() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_TC() : stm32f3xx_ll_usart.h
  • LL_USART_ClearFlag_WKUP() : stm32f3xx_ll_usart.h
  • LL_USART_ClockInit() : stm32f3xx_ll_usart.c
  • LL_USART_ClockStructInit() : stm32f3xx_ll_usart.c
  • LL_USART_ConfigAsyncMode() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigCharacter() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigClock() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigHalfDuplexMode() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigIrdaMode() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigLINMode() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigMultiProcessMode() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigNodeAddress() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigSmartcardMode() : stm32f3xx_ll_usart.h
  • LL_USART_ConfigSyncMode() : stm32f3xx_ll_usart.h
  • LL_USART_DeInit() : stm32f3xx_ll_usart.c
  • LL_USART_Disable() : stm32f3xx_ll_usart.h
  • LL_USART_DisableAutoBaudRate() : stm32f3xx_ll_usart.h
  • LL_USART_DisableCTSHWFlowCtrl() : stm32f3xx_ll_usart.h
  • LL_USART_DisableDEMode() : stm32f3xx_ll_usart.h
  • LL_USART_DisableDirectionRx() : stm32f3xx_ll_usart.h
  • LL_USART_DisableDirectionTx() : stm32f3xx_ll_usart.h
  • LL_USART_DisableDMADeactOnRxErr() : stm32f3xx_ll_usart.h
  • LL_USART_DisableDMAReq_RX() : stm32f3xx_ll_usart.h
  • LL_USART_DisableDMAReq_TX() : stm32f3xx_ll_usart.h
  • LL_USART_DisableHalfDuplex() : stm32f3xx_ll_usart.h
  • LL_USART_DisableInStopMode() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIrda() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_CM() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_CTS() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_EOB() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_ERROR() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_IDLE() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_LBD() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_PE() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_RTO() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_RXNE() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_TC() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_TXE() : stm32f3xx_ll_usart.h
  • LL_USART_DisableIT_WKUP() : stm32f3xx_ll_usart.h
  • LL_USART_DisableLIN() : stm32f3xx_ll_usart.h
  • LL_USART_DisableMuteMode() : stm32f3xx_ll_usart.h
  • LL_USART_DisableOneBitSamp() : stm32f3xx_ll_usart.h
  • LL_USART_DisableOverrunDetect() : stm32f3xx_ll_usart.h
  • LL_USART_DisableRTSHWFlowCtrl() : stm32f3xx_ll_usart.h
  • LL_USART_DisableRxTimeout() : stm32f3xx_ll_usart.h
  • LL_USART_DisableSCLKOutput() : stm32f3xx_ll_usart.h
  • LL_USART_DisableSmartcard() : stm32f3xx_ll_usart.h
  • LL_USART_DisableSmartcardNACK() : stm32f3xx_ll_usart.h
  • LL_USART_DMA_GetRegAddr() : stm32f3xx_ll_usart.h
  • LL_USART_Enable() : stm32f3xx_ll_usart.h
  • LL_USART_EnableAutoBaudRate() : stm32f3xx_ll_usart.h
  • LL_USART_EnableCTSHWFlowCtrl() : stm32f3xx_ll_usart.h
  • LL_USART_EnableDEMode() : stm32f3xx_ll_usart.h
  • LL_USART_EnableDirectionRx() : stm32f3xx_ll_usart.h
  • LL_USART_EnableDirectionTx() : stm32f3xx_ll_usart.h
  • LL_USART_EnableDMADeactOnRxErr() : stm32f3xx_ll_usart.h
  • LL_USART_EnableDMAReq_RX() : stm32f3xx_ll_usart.h
  • LL_USART_EnableDMAReq_TX() : stm32f3xx_ll_usart.h
  • LL_USART_EnableHalfDuplex() : stm32f3xx_ll_usart.h
  • LL_USART_EnableInStopMode() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIrda() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_CM() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_CTS() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_EOB() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_ERROR() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_IDLE() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_LBD() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_PE() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_RTO() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_RXNE() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_TC() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_TXE() : stm32f3xx_ll_usart.h
  • LL_USART_EnableIT_WKUP() : stm32f3xx_ll_usart.h
  • LL_USART_EnableLIN() : stm32f3xx_ll_usart.h
  • LL_USART_EnableMuteMode() : stm32f3xx_ll_usart.h
  • LL_USART_EnableOneBitSamp() : stm32f3xx_ll_usart.h
  • LL_USART_EnableOverrunDetect() : stm32f3xx_ll_usart.h
  • LL_USART_EnableRTSHWFlowCtrl() : stm32f3xx_ll_usart.h
  • LL_USART_EnableRxTimeout() : stm32f3xx_ll_usart.h
  • LL_USART_EnableSCLKOutput() : stm32f3xx_ll_usart.h
  • LL_USART_EnableSmartcard() : stm32f3xx_ll_usart.h
  • LL_USART_EnableSmartcardNACK() : stm32f3xx_ll_usart.h
  • LL_USART_GetAutoBaudRateMode() : stm32f3xx_ll_usart.h
  • LL_USART_GetBaudRate() : stm32f3xx_ll_usart.h
  • LL_USART_GetBinaryDataLogic() : stm32f3xx_ll_usart.h
  • LL_USART_GetBlockLength() : stm32f3xx_ll_usart.h
  • LL_USART_GetClockPhase() : stm32f3xx_ll_usart.h
  • LL_USART_GetClockPolarity() : stm32f3xx_ll_usart.h
  • LL_USART_GetDataWidth() : stm32f3xx_ll_usart.h
  • LL_USART_GetDEAssertionTime() : stm32f3xx_ll_usart.h
  • LL_USART_GetDEDeassertionTime() : stm32f3xx_ll_usart.h
  • LL_USART_GetDESignalPolarity() : stm32f3xx_ll_usart.h
  • LL_USART_GetHWFlowCtrl() : stm32f3xx_ll_usart.h
  • LL_USART_GetIrdaPowerMode() : stm32f3xx_ll_usart.h
  • LL_USART_GetIrdaPrescaler() : stm32f3xx_ll_usart.h
  • LL_USART_GetLastClkPulseOutput() : stm32f3xx_ll_usart.h
  • LL_USART_GetLINBrkDetectionLen() : stm32f3xx_ll_usart.h
  • LL_USART_GetNodeAddress() : stm32f3xx_ll_usart.h
  • LL_USART_GetNodeAddressLen() : stm32f3xx_ll_usart.h
  • LL_USART_GetOverSampling() : stm32f3xx_ll_usart.h
  • LL_USART_GetParity() : stm32f3xx_ll_usart.h
  • LL_USART_GetRXPinLevel() : stm32f3xx_ll_usart.h
  • LL_USART_GetRxTimeout() : stm32f3xx_ll_usart.h
  • LL_USART_GetSmartcardAutoRetryCount() : stm32f3xx_ll_usart.h
  • LL_USART_GetSmartcardGuardTime() : stm32f3xx_ll_usart.h
  • LL_USART_GetSmartcardPrescaler() : stm32f3xx_ll_usart.h
  • LL_USART_GetStopBitsLength() : stm32f3xx_ll_usart.h
  • LL_USART_GetTransferBitOrder() : stm32f3xx_ll_usart.h
  • LL_USART_GetTransferDirection() : stm32f3xx_ll_usart.h
  • LL_USART_GetTXPinLevel() : stm32f3xx_ll_usart.h
  • LL_USART_GetTXRXSwap() : stm32f3xx_ll_usart.h
  • LL_USART_GetWakeUpMethod() : stm32f3xx_ll_usart.h
  • LL_USART_GetWKUPType() : stm32f3xx_ll_usart.h
  • LL_USART_Init() : stm32f3xx_ll_usart.c
  • LL_USART_IsActiveFlag_ABR() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_ABRE() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_BUSY() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_CM() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_CTS() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_EOB() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_FE() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_IDLE() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_LBD() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_nCTS() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_NE() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_ORE() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_PE() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_REACK() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_RTO() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_RWU() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_SBK() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_TC() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_TEACK() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE() : stm32f3xx_ll_usart.h
  • LL_USART_IsActiveFlag_WKUP() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabled() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledAutoBaud() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledDEMode() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledDMADeactOnRxErr() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_RX() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_TX() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledHalfDuplex() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledInStopMode() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIrda() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_CM() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_CTS() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_EOB() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_ERROR() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_IDLE() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_LBD() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_PE() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_RTO() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_TC() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledIT_WKUP() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledLIN() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledMuteMode() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledOneBitSamp() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledOverrunDetect() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledRxTimeout() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledSCLKOutput() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledSmartcard() : stm32f3xx_ll_usart.h
  • LL_USART_IsEnabledSmartcardNACK() : stm32f3xx_ll_usart.h
  • LL_USART_ReceiveData8() : stm32f3xx_ll_usart.h
  • LL_USART_ReceiveData9() : stm32f3xx_ll_usart.h
  • LL_USART_RequestAutoBaudRate() : stm32f3xx_ll_usart.h
  • LL_USART_RequestBreakSending() : stm32f3xx_ll_usart.h
  • LL_USART_RequestEnterMuteMode() : stm32f3xx_ll_usart.h
  • LL_USART_RequestRxDataFlush() : stm32f3xx_ll_usart.h
  • LL_USART_RequestTxDataFlush() : stm32f3xx_ll_usart.h
  • LL_USART_SetAutoBaudRateMode() : stm32f3xx_ll_usart.h
  • LL_USART_SetBaudRate() : stm32f3xx_ll_usart.h
  • LL_USART_SetBinaryDataLogic() : stm32f3xx_ll_usart.h
  • LL_USART_SetBlockLength() : stm32f3xx_ll_usart.h
  • LL_USART_SetClockPhase() : stm32f3xx_ll_usart.h
  • LL_USART_SetClockPolarity() : stm32f3xx_ll_usart.h
  • LL_USART_SetDataWidth() : stm32f3xx_ll_usart.h
  • LL_USART_SetDEAssertionTime() : stm32f3xx_ll_usart.h
  • LL_USART_SetDEDeassertionTime() : stm32f3xx_ll_usart.h
  • LL_USART_SetDESignalPolarity() : stm32f3xx_ll_usart.h
  • LL_USART_SetHWFlowCtrl() : stm32f3xx_ll_usart.h
  • LL_USART_SetIrdaPowerMode() : stm32f3xx_ll_usart.h
  • LL_USART_SetIrdaPrescaler() : stm32f3xx_ll_usart.h
  • LL_USART_SetLastClkPulseOutput() : stm32f3xx_ll_usart.h
  • LL_USART_SetLINBrkDetectionLen() : stm32f3xx_ll_usart.h
  • LL_USART_SetOverSampling() : stm32f3xx_ll_usart.h
  • LL_USART_SetParity() : stm32f3xx_ll_usart.h
  • LL_USART_SetRXPinLevel() : stm32f3xx_ll_usart.h
  • LL_USART_SetRxTimeout() : stm32f3xx_ll_usart.h
  • LL_USART_SetSmartcardAutoRetryCount() : stm32f3xx_ll_usart.h
  • LL_USART_SetSmartcardGuardTime() : stm32f3xx_ll_usart.h
  • LL_USART_SetSmartcardPrescaler() : stm32f3xx_ll_usart.h
  • LL_USART_SetStopBitsLength() : stm32f3xx_ll_usart.h
  • LL_USART_SetTransferBitOrder() : stm32f3xx_ll_usart.h
  • LL_USART_SetTransferDirection() : stm32f3xx_ll_usart.h
  • LL_USART_SetTXPinLevel() : stm32f3xx_ll_usart.h
  • LL_USART_SetTXRXSwap() : stm32f3xx_ll_usart.h
  • LL_USART_SetWakeUpMethod() : stm32f3xx_ll_usart.h
  • LL_USART_SetWKUPType() : stm32f3xx_ll_usart.h
  • LL_USART_StructInit() : stm32f3xx_ll_usart.c
  • LL_USART_TransmitData8() : stm32f3xx_ll_usart.h
  • LL_USART_TransmitData9() : stm32f3xx_ll_usart.h
  • LL_WWDG_ClearFlag_EWKUP() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_Enable() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_EnableIT_EWKUP() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_GetCounter() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_GetPrescaler() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_GetWindow() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_IsActiveFlag_EWKUP() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_IsEnabled() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_IsEnabledIT_EWKUP() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_SetCounter() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_SetPrescaler() : stm32f3xx_ll_wwdg.h
  • LL_WWDG_SetWindow() : stm32f3xx_ll_wwdg.h
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STM32F373xC HAL User Manual: Globals

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- o -

  • OC1Config() : stm32f3xx_ll_tim.c
  • OC2Config() : stm32f3xx_ll_tim.c
  • OC3Config() : stm32f3xx_ll_tim.c
  • OC4Config() : stm32f3xx_ll_tim.c
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STM32F373xC HAL User Manual: Globals

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- p -

  • PCD_EP_ISR_Handler() : stm32f3xx_hal_pcd.c
  • PCD_ReadPMA() : stm32f3xx_hal_pcd.h
  • PCD_WritePMA() : stm32f3xx_hal_pcd.h
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STM32F373xC HAL User Manual: Globals

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- r -

  • RCC_GetHCLKClockFreq() : stm32f3xx_ll_rcc.c
  • RCC_GetPCLK1ClockFreq() : stm32f3xx_ll_rcc.c
  • RCC_GetPCLK2ClockFreq() : stm32f3xx_ll_rcc.c
  • RCC_GetPLLCLKFreq() : stm32f3xx_hal_rcc_ex.c
  • RCC_GetSystemClockFreq() : stm32f3xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_SYS() : stm32f3xx_ll_rcc.c
  • RTC_Bcd2ToByte() : stm32f3xx_hal_rtc.h , stm32f3xx_hal_rtc.c
  • RTC_ByteToBcd2() : stm32f3xx_hal_rtc.h , stm32f3xx_hal_rtc.c
  • RTC_EnterInitMode() : stm32f3xx_hal_rtc.c , stm32f3xx_hal_rtc.h
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STM32F373xC HAL User Manual: Globals

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- s -

  • SDADC_DMAError() : stm32f3xx_hal_sdadc.c
  • SDADC_DMAInjectedConvCplt() : stm32f3xx_hal_sdadc.c
  • SDADC_DMAInjectedHalfConvCplt() : stm32f3xx_hal_sdadc.c
  • SDADC_DMARegularConvCplt() : stm32f3xx_hal_sdadc.c
  • SDADC_DMARegularHalfConvCplt() : stm32f3xx_hal_sdadc.c
  • SDADC_EnterInitMode() : stm32f3xx_hal_sdadc.c
  • SDADC_ExitInitMode() : stm32f3xx_hal_sdadc.c
  • SDADC_GetInjChannelsNbr() : stm32f3xx_hal_sdadc.c
  • SDADC_InjConvStart() : stm32f3xx_hal_sdadc.c
  • SDADC_InjConvStop() : stm32f3xx_hal_sdadc.c
  • SDADC_RegConvStart() : stm32f3xx_hal_sdadc.c
  • SDADC_RegConvStop() : stm32f3xx_hal_sdadc.c
  • SMARTCARD_AdvFeatureConfig() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_CheckIdleState() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_DMAAbortOnError() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_DMAError() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_DMARxAbortCallback() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_DMARxOnlyAbortCallback() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_DMATxAbortCallback() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_DMATxOnlyAbortCallback() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_EndRxTransfer() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_EndTxTransfer() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_Receive_IT() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_SetConfig() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_Transmit_IT() : stm32f3xx_hal_smartcard.c
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32f3xx_hal_smartcard.c
  • SMBUS_ConvertOtherXferOptions() : stm32f3xx_hal_smbus.c
  • SMBUS_Disable_IRQ() : stm32f3xx_hal_smbus.c
  • SMBUS_Enable_IRQ() : stm32f3xx_hal_smbus.c
  • SMBUS_ITErrorHandler() : stm32f3xx_hal_smbus.c
  • SMBUS_Master_ISR() : stm32f3xx_hal_smbus.c
  • SMBUS_Slave_ISR() : stm32f3xx_hal_smbus.c
  • SMBUS_TransferConfig() : stm32f3xx_hal_smbus.c
  • SMBUS_WaitOnFlagUntilTimeout() : stm32f3xx_hal_smbus.c
  • SPI_2linesRxISR_16BIT() : stm32f3xx_hal_spi.c
  • SPI_2linesRxISR_16BITCRC() : stm32f3xx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32f3xx_hal_spi.c
  • SPI_2linesRxISR_8BITCRC() : stm32f3xx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32f3xx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32f3xx_hal_spi.c
  • SPI_AbortRx_ISR() : stm32f3xx_hal_spi.c
  • SPI_AbortTx_ISR() : stm32f3xx_hal_spi.c
  • SPI_CloseRx_ISR() : stm32f3xx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32f3xx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32f3xx_hal_spi.c
  • SPI_DMAAbortOnError() : stm32f3xx_hal_spi.c
  • SPI_DMAError() : stm32f3xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32f3xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32f3xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32f3xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32f3xx_hal_spi.c
  • SPI_DMARxAbortCallback() : stm32f3xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32f3xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32f3xx_hal_spi.c
  • SPI_DMATxAbortCallback() : stm32f3xx_hal_spi.c
  • SPI_EndRxTransaction() : stm32f3xx_hal_spi.c
  • SPI_EndRxTxTransaction() : stm32f3xx_hal_spi.c
  • SPI_RxISR_16BIT() : stm32f3xx_hal_spi.c
  • SPI_RxISR_16BITCRC() : stm32f3xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32f3xx_hal_spi.c
  • SPI_RxISR_8BITCRC() : stm32f3xx_hal_spi.c
  • SPI_TxISR_16BIT() : stm32f3xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32f3xx_hal_spi.c
  • SPI_WaitFifoStateUntilTimeout() : stm32f3xx_hal_spi.c
  • SPI_WaitFlagStateUntilTimeout() : stm32f3xx_hal_spi.c
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STM32F373xC HAL User Manual: Globals

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- t -

  • TIM_Base_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_CCxChannelCmd() : stm32f3xx_hal_tim.c
  • TIM_CCxNChannelCmd() : stm32f3xx_hal_tim_ex.c
  • TIM_DMACaptureCplt() : stm32f3xx_hal_tim.c
  • TIM_DMADelayPulseCplt() : stm32f3xx_hal_tim.c
  • TIM_DMAError() : stm32f3xx_hal_tim.c
  • TIM_DMAPeriodElapsedCplt() : stm32f3xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32f3xx_hal_tim.c
  • TIM_ETR_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_ITRx_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_OC1_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_OC2_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_OC3_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_SlaveTimer_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32f3xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_TI2_ConfigInputStage() : stm32f3xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32f3xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32f3xx_hal_tim.c
  • TIMEx_DMACommutationCplt() : stm32f3xx_hal_tim_ex.c
  • TSC_extract_groups() : stm32f3xx_hal_tsc.c
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STM32F373xC HAL User Manual: Globals

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- u -

  • UART_AdvFeatureConfig() : stm32f3xx_hal_uart.c
  • UART_CheckIdleState() : stm32f3xx_hal_uart.c
  • UART_DMAAbortOnError() : stm32f3xx_hal_uart.c
  • UART_DMAError() : stm32f3xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32f3xx_hal_uart.c
  • UART_DMARxAbortCallback() : stm32f3xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32f3xx_hal_uart.c
  • UART_DMARxOnlyAbortCallback() : stm32f3xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32f3xx_hal_uart.c
  • UART_DMATxAbortCallback() : stm32f3xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32f3xx_hal_uart.c
  • UART_DMATxOnlyAbortCallback() : stm32f3xx_hal_uart.c
  • UART_EndRxTransfer() : stm32f3xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32f3xx_hal_uart.c
  • UART_EndTxTransfer() : stm32f3xx_hal_uart.c
  • UART_Receive_IT() : stm32f3xx_hal_uart.c
  • UART_SetConfig() : stm32f3xx_hal_uart.c
  • UART_Transmit_IT() : stm32f3xx_hal_uart.c
  • UART_WaitOnFlagUntilTimeout() : stm32f3xx_hal_uart.c
  • UART_Wakeup_AddressConfig() : stm32f3xx_hal_uart.c
  • USART_CheckIdleState() : stm32f3xx_hal_usart.c
  • USART_DMAAbortOnError() : stm32f3xx_hal_usart.c
  • USART_DMAError() : stm32f3xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32f3xx_hal_usart.c
  • USART_DMARxAbortCallback() : stm32f3xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32f3xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32f3xx_hal_usart.c
  • USART_DMATxAbortCallback() : stm32f3xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32f3xx_hal_usart.c
  • USART_EndTransfer() : stm32f3xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32f3xx_hal_usart.c
  • USART_Receive_IT() : stm32f3xx_hal_usart.c
  • USART_SetConfig() : stm32f3xx_hal_usart.c
  • USART_Transmit_IT() : stm32f3xx_hal_usart.c
  • USART_TransmitReceive_IT() : stm32f3xx_hal_usart.c
  • USART_WaitOnFlagUntilTimeout() : stm32f3xx_hal_usart.c
  • UTILS_EnablePLLAndSwitchSystem() : stm32f3xx_ll_utils.c
  • UTILS_GetPLLOutputFrequency() : stm32f3xx_ll_utils.c
  • UTILS_PLL_IsBusy() : stm32f3xx_ll_utils.c
  • UTILS_SetFlashLatency() : stm32f3xx_ll_utils.c
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STM32F373xC HAL User Manual: Globals

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  • aPLLMULFactorTable : stm32f3xx_hal_rcc.c
  • aPredivFactorTable : stm32f3xx_hal_rcc.c
  • aSDADCPrescTable : stm32f3xx_ll_rcc.c
  • CHANNEL_OFFSET_TAB : stm32f3xx_ll_dma.h
  • OFFSET_TAB_CCMRx : stm32f3xx_ll_tim.h
  • pFlash : stm32f3xx_hal_flash.c , stm32f3xx_hal_flash_ex.c
  • SHIFT_TAB_CCxP : stm32f3xx_ll_tim.h
  • SHIFT_TAB_ICxx : stm32f3xx_ll_tim.h
  • SHIFT_TAB_OCxx : stm32f3xx_ll_tim.h
  • SHIFT_TAB_OISx : stm32f3xx_ll_tim.h
  • uwTick : stm32f3xx_hal.c
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STM32F373xC HAL User Manual: Globals

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  • ADC_HandleTypeDef : stm32f3xx_hal_adc.h
  • DAC_HandleTypeDef : stm32f3xx_hal_dac.h
  • DMA_HandleTypeDef : stm32f3xx_hal_dma.h
  • I2C_HandleTypeDef : stm32f3xx_hal_i2c.h
  • PCD_TypeDef : stm32f3xx_hal_pcd.h
  • SPI_HandleTypeDef : stm32f3xx_hal_spi.h
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STM32F373xC HAL User Manual: Globals

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- f -

  • FLASH_ProcedureTypeDef : stm32f3xx_hal_flash.h

- g -

  • GPIO_PinState : stm32f3xx_hal_gpio.h

- h -

  • HAL_CAN_StateTypeDef : stm32f3xx_hal_can.h
  • HAL_CEC_StateTypeDef : stm32f3xx_hal_cec.h
  • HAL_COMP_StateTypeDef : stm32f3xx_hal_comp.h
  • HAL_CRC_StateTypeDef : stm32f3xx_hal_crc.h
  • HAL_DAC_StateTypeDef : stm32f3xx_hal_dac.h
  • HAL_DMA_CallbackIDTypeDef : stm32f3xx_hal_dma.h
  • HAL_DMA_LevelCompleteTypeDef : stm32f3xx_hal_dma.h
  • HAL_DMA_StateTypeDef : stm32f3xx_hal_dma.h
  • HAL_I2C_ModeTypeDef : stm32f3xx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32f3xx_hal_i2c.h
  • HAL_I2S_StateTypeDef : stm32f3xx_hal_i2s.h
  • HAL_IRDA_StateTypeDef : stm32f3xx_hal_irda.h
  • HAL_RTCStateTypeDef : stm32f3xx_hal_rtc.h
  • HAL_SDADC_StateTypeDef : stm32f3xx_hal_sdadc.h
  • HAL_SMARTCARD_StateTypeDef : stm32f3xx_hal_smartcard.h
  • HAL_SPI_StateTypeDef : stm32f3xx_hal_spi.h
  • HAL_TIM_ActiveChannel : stm32f3xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32f3xx_hal_tim.h
  • HAL_TSC_StateTypeDef : stm32f3xx_hal_tsc.h
  • HAL_UART_StateTypeDef : stm32f3xx_hal_uart.h
  • HAL_USART_StateTypeDef : stm32f3xx_hal_usart.h

- i -

  • IRDA_ClockSourceTypeDef : stm32f3xx_hal_irda.h
  • IRDA_ControlTypeDef : stm32f3xx_hal_irda.h

- p -

  • PCD_EP_BUF_NUM : stm32f3xx_hal_pcd.h
  • PCD_EP_DBUF_DIR : stm32f3xx_hal_pcd.h
  • PCD_StateTypeDef : stm32f3xx_hal_pcd.h

- s -

  • SMARTCARD_ClockSourceTypeDef : stm32f3xx_hal_smartcard.h

- t -

  • TSC_GroupStatusTypeDef : stm32f3xx_hal_tsc.h

- u -

  • UART_ClockSourceTypeDef : stm32f3xx_hal_uart.h
  • USART_ClockSourceTypeDef : stm32f3xx_hal_usart.h
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STM32F373xC HAL User Manual: Globals

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- f -

  • FLASH_PROC_MASSERASE : stm32f3xx_hal_flash.h
  • FLASH_PROC_NONE : stm32f3xx_hal_flash.h
  • FLASH_PROC_PAGEERASE : stm32f3xx_hal_flash.h
  • FLASH_PROC_PROGRAMDOUBLEWORD : stm32f3xx_hal_flash.h
  • FLASH_PROC_PROGRAMHALFWORD : stm32f3xx_hal_flash.h
  • FLASH_PROC_PROGRAMWORD : stm32f3xx_hal_flash.h

- g -

  • GPIO_PIN_RESET : stm32f3xx_hal_gpio.h
  • GPIO_PIN_SET : stm32f3xx_hal_gpio.h

- h -

  • HAL_CAN_STATE_BUSY : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_BUSY_RX0 : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_BUSY_RX0_RX1 : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_BUSY_RX1 : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX_RX0 : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX_RX0_RX1 : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX_RX1 : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_ERROR : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_READY : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_RESET : stm32f3xx_hal_can.h
  • HAL_CAN_STATE_TIMEOUT : stm32f3xx_hal_can.h
  • HAL_CEC_STATE_BUSY : stm32f3xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX : stm32f3xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX_TX : stm32f3xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_TX : stm32f3xx_hal_cec.h
  • HAL_CEC_STATE_ERROR : stm32f3xx_hal_cec.h
  • HAL_CEC_STATE_READY : stm32f3xx_hal_cec.h
  • HAL_CEC_STATE_RESET : stm32f3xx_hal_cec.h
  • HAL_COMP_STATE_BUSY : stm32f3xx_hal_comp.h
  • HAL_COMP_STATE_BUSY_LOCKED : stm32f3xx_hal_comp.h
  • HAL_COMP_STATE_READY : stm32f3xx_hal_comp.h
  • HAL_COMP_STATE_READY_LOCKED : stm32f3xx_hal_comp.h
  • HAL_COMP_STATE_RESET : stm32f3xx_hal_comp.h
  • HAL_CRC_STATE_BUSY : stm32f3xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32f3xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32f3xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32f3xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32f3xx_hal_crc.h
  • HAL_DAC_STATE_BUSY : stm32f3xx_hal_dac.h
  • HAL_DAC_STATE_ERROR : stm32f3xx_hal_dac.h
  • HAL_DAC_STATE_READY : stm32f3xx_hal_dac.h
  • HAL_DAC_STATE_RESET : stm32f3xx_hal_dac.h
  • HAL_DAC_STATE_TIMEOUT : stm32f3xx_hal_dac.h
  • HAL_DMA_FULL_TRANSFER : stm32f3xx_hal_dma.h
  • HAL_DMA_HALF_TRANSFER : stm32f3xx_hal_dma.h
  • HAL_DMA_STATE_BUSY : stm32f3xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32f3xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32f3xx_hal_dma.h
  • HAL_DMA_STATE_TIMEOUT : stm32f3xx_hal_dma.h
  • HAL_DMA_XFER_ABORT_CB_ID : stm32f3xx_hal_dma.h
  • HAL_DMA_XFER_ALL_CB_ID : stm32f3xx_hal_dma.h
  • HAL_DMA_XFER_CPLT_CB_ID : stm32f3xx_hal_dma.h
  • HAL_DMA_XFER_ERROR_CB_ID : stm32f3xx_hal_dma.h
  • HAL_DMA_XFER_HALFCPLT_CB_ID : stm32f3xx_hal_dma.h
  • HAL_I2C_MODE_MASTER : stm32f3xx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32f3xx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32f3xx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_ABORT : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32f3xx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32f3xx_hal_i2c.h
  • HAL_I2S_STATE_BUSY : stm32f3xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_RX : stm32f3xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX : stm32f3xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX_RX : stm32f3xx_hal_i2s.h
  • HAL_I2S_STATE_ERROR : stm32f3xx_hal_i2s.h
  • HAL_I2S_STATE_READY : stm32f3xx_hal_i2s.h
  • HAL_I2S_STATE_RESET : stm32f3xx_hal_i2s.h
  • HAL_I2S_STATE_TIMEOUT : stm32f3xx_hal_i2s.h
  • HAL_IRDA_STATE_BUSY : stm32f3xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32f3xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32f3xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32f3xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32f3xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32f3xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32f3xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32f3xx_hal_irda.h
  • HAL_PCD_STATE_BUSY : stm32f3xx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32f3xx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32f3xx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32f3xx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32f3xx_hal_pcd.h
  • HAL_RTC_STATE_BUSY : stm32f3xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32f3xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32f3xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32f3xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32f3xx_hal_rtc.h
  • HAL_SDADC_STATE_CALIB : stm32f3xx_hal_sdadc.h
  • HAL_SDADC_STATE_ERROR : stm32f3xx_hal_sdadc.h
  • HAL_SDADC_STATE_INJ : stm32f3xx_hal_sdadc.h
  • HAL_SDADC_STATE_READY : stm32f3xx_hal_sdadc.h
  • HAL_SDADC_STATE_REG : stm32f3xx_hal_sdadc.h
  • HAL_SDADC_STATE_REG_INJ : stm32f3xx_hal_sdadc.h
  • HAL_SDADC_STATE_RESET : stm32f3xx_hal_sdadc.h
  • HAL_SMARTCARD_STATE_BUSY : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32f3xx_hal_smartcard.h
  • HAL_SPI_STATE_ABORT : stm32f3xx_hal_spi.h
  • HAL_SPI_STATE_BUSY : stm32f3xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32f3xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32f3xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32f3xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32f3xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32f3xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32f3xx_hal_spi.h
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32f3xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32f3xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32f3xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32f3xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32f3xx_hal_tim.h
  • HAL_TIM_STATE_BUSY : stm32f3xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32f3xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32f3xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32f3xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32f3xx_hal_tim.h
  • HAL_TSC_STATE_BUSY : stm32f3xx_hal_tsc.h
  • HAL_TSC_STATE_ERROR : stm32f3xx_hal_tsc.h
  • HAL_TSC_STATE_READY : stm32f3xx_hal_tsc.h
  • HAL_TSC_STATE_RESET : stm32f3xx_hal_tsc.h
  • HAL_UART_STATE_BUSY : stm32f3xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32f3xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32f3xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32f3xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32f3xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32f3xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32f3xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32f3xx_hal_uart.h
  • HAL_USART_STATE_BUSY : stm32f3xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32f3xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32f3xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32f3xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32f3xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32f3xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32f3xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32f3xx_hal_usart.h

- i -

  • IRDA_BAUDRATE : stm32f3xx_hal_irda.h
  • IRDA_CLOCKSOURCE_HSI : stm32f3xx_hal_irda.h
  • IRDA_CLOCKSOURCE_LSE : stm32f3xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK1 : stm32f3xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK2 : stm32f3xx_hal_irda.h
  • IRDA_CLOCKSOURCE_SYSCLK : stm32f3xx_hal_irda.h
  • IRDA_CLOCKSOURCE_UNDEFINED : stm32f3xx_hal_irda.h
  • IRDA_MODE : stm32f3xx_hal_irda.h
  • IRDA_PARITY : stm32f3xx_hal_irda.h
  • IRDA_POWERMODE : stm32f3xx_hal_irda.h
  • IRDA_PRESCALER : stm32f3xx_hal_irda.h
  • IRDA_WORDLENGTH : stm32f3xx_hal_irda.h

- p -

  • PCD_EP_BUF0 : stm32f3xx_hal_pcd.h
  • PCD_EP_BUF1 : stm32f3xx_hal_pcd.h
  • PCD_EP_DBUF_ERR : stm32f3xx_hal_pcd.h
  • PCD_EP_DBUF_IN : stm32f3xx_hal_pcd.h
  • PCD_EP_DBUF_OUT : stm32f3xx_hal_pcd.h
  • PCD_EP_NOBUF : stm32f3xx_hal_pcd.h

- s -

  • SMARTCARD_CLOCKSOURCE_HSI : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_LSE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK1 : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK2 : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_SYSCLK : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_UNDEFINED : stm32f3xx_hal_smartcard.h

- t -

  • TSC_GROUP_COMPLETED : stm32f3xx_hal_tsc.h
  • TSC_GROUP_ONGOING : stm32f3xx_hal_tsc.h

- u -

  • UART_CLOCKSOURCE_HSI : stm32f3xx_hal_uart.h
  • UART_CLOCKSOURCE_LSE : stm32f3xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK1 : stm32f3xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK2 : stm32f3xx_hal_uart.h
  • UART_CLOCKSOURCE_SYSCLK : stm32f3xx_hal_uart.h
  • UART_CLOCKSOURCE_UNDEFINED : stm32f3xx_hal_uart.h
  • USART_CLOCKSOURCE_HSI : stm32f3xx_hal_usart.h
  • USART_CLOCKSOURCE_LSE : stm32f3xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK1 : stm32f3xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK2 : stm32f3xx_hal_usart.h
  • USART_CLOCKSOURCE_SYSCLK : stm32f3xx_hal_usart.h
  • USART_CLOCKSOURCE_UNDEFINED : stm32f3xx_hal_usart.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
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- _ -

  • __ADC_MASK_SHIFT : stm32f3xx_ll_adc.h
  • __ADC_PTR_REG_OFFSET : stm32f3xx_ll_adc.h
  • __COMP_BITOFFSET_INSTANCE : stm32f3xx_ll_comp.h
  • __COMP_IS_INSTANCE_EVEN : stm32f3xx_ll_comp.h
  • __COMP_IS_INSTANCE_ODD : stm32f3xx_ll_comp.h
  • __DAC_MASK_SHIFT : stm32f3xx_ll_dac.h
  • __DAC_PTR_REG_OFFSET : stm32f3xx_ll_dac.h
  • __HAL_ADC_CLEAR_FLAG : stm32f3xx_hal_adc_ex.h
  • __HAL_ADC_DISABLE : stm32f3xx_hal_adc_ex.h
  • __HAL_ADC_DISABLE_IT : stm32f3xx_hal_adc_ex.h
  • __HAL_ADC_ENABLE : stm32f3xx_hal_adc_ex.h
  • __HAL_ADC_ENABLE_IT : stm32f3xx_hal_adc_ex.h
  • __HAL_ADC_GET_FLAG : stm32f3xx_hal_adc_ex.h
  • __HAL_ADC_GET_IT_SOURCE : stm32f3xx_hal_adc_ex.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32f3xx_hal_adc_ex.h , stm32f3xx_hal_adc.h
  • __HAL_CAN_CANCEL_TRANSMIT : stm32f3xx_hal_can.h
  • __HAL_CAN_CLEAR_FLAG : stm32f3xx_hal_can.h
  • __HAL_CAN_DBG_FREEZE : stm32f3xx_hal_can.h
  • __HAL_CAN_DISABLE_IT : stm32f3xx_hal_can.h
  • __HAL_CAN_ENABLE_IT : stm32f3xx_hal_can.h
  • __HAL_CAN_FIFO_RELEASE : stm32f3xx_hal_can.h
  • __HAL_CAN_GET_FLAG : stm32f3xx_hal_can.h
  • __HAL_CAN_GET_IT_SOURCE : stm32f3xx_hal_can.h
  • __HAL_CAN_MSG_PENDING : stm32f3xx_hal_can.h
  • __HAL_CAN_RESET_HANDLE_STATE : stm32f3xx_hal_can.h
  • __HAL_CAN_TRANSMIT_STATUS : stm32f3xx_hal_can.h
  • __HAL_CEC_CLEAR_FLAG : stm32f3xx_hal_cec.h
  • __HAL_CEC_CLEAR_OAR : stm32f3xx_hal_cec.h
  • __HAL_CEC_DISABLE : stm32f3xx_hal_cec.h
  • __HAL_CEC_DISABLE_IT : stm32f3xx_hal_cec.h
  • __HAL_CEC_ENABLE : stm32f3xx_hal_cec.h
  • __HAL_CEC_ENABLE_IT : stm32f3xx_hal_cec.h
  • __HAL_CEC_FIRST_BYTE_TX_SET : stm32f3xx_hal_cec.h
  • __HAL_CEC_GET_FLAG : stm32f3xx_hal_cec.h
  • __HAL_CEC_GET_IT_SOURCE : stm32f3xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_END_FLAG : stm32f3xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_START_FLAG : stm32f3xx_hal_cec.h
  • __HAL_CEC_LAST_BYTE_TX_SET : stm32f3xx_hal_cec.h
  • __HAL_CEC_RESET_HANDLE_STATE : stm32f3xx_hal_cec.h
  • __HAL_CEC_SET_OAR : stm32f3xx_hal_cec.h
  • __HAL_COMP_COMP1_EXTI_CLEAR_FLAG : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_EVENT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_IT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_EVENT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_IT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_GENERATE_SWIT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP1_EXTI_GET_FLAG : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_CLEAR_FLAG : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_EVENT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_IT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_EVENT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_IT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_GENERATE_SWIT : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_COMP2_EXTI_GET_FLAG : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_DISABLE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_ENABLE : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_GET_FLAG : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_LOCK : stm32f3xx_hal_comp_ex.h
  • __HAL_COMP_RESET_HANDLE_STATE : stm32f3xx_hal_comp.h
  • __HAL_CRC_DR_RESET : stm32f3xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32f3xx_hal_crc.h
  • __HAL_CRC_INITIALCRCVALUE_CONFIG : stm32f3xx_hal_crc.h
  • __HAL_CRC_OUTPUTREVERSAL_DISABLE : stm32f3xx_hal_crc_ex.h
  • __HAL_CRC_OUTPUTREVERSAL_ENABLE : stm32f3xx_hal_crc_ex.h
  • __HAL_CRC_POLYNOMIAL_CONFIG : stm32f3xx_hal_crc_ex.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32f3xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32f3xx_hal_crc.h
  • __HAL_DAC_CLEAR_FLAG : stm32f3xx_hal_dac.h
  • __HAL_DAC_DISABLE : stm32f3xx_hal_dac.h
  • __HAL_DAC_DISABLE_IT : stm32f3xx_hal_dac.h
  • __HAL_DAC_ENABLE : stm32f3xx_hal_dac.h
  • __HAL_DAC_ENABLE_IT : stm32f3xx_hal_dac.h
  • __HAL_DAC_GET_FLAG : stm32f3xx_hal_dac.h
  • __HAL_DAC_GET_IT_SOURCE : stm32f3xx_hal_dac.h
  • __HAL_DAC_RESET_HANDLE_STATE : stm32f3xx_hal_dac.h
  • __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM12 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM13 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM14 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM15 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM16 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM17 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM5 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM6 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM7 : stm32f3xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_IWDG : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_RTC : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM12 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM13 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM14 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM15 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM16 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM17 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM2 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM3 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM4 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM5 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM6 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM7 : stm32f3xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_WWDG : stm32f3xx_hal.h
  • __HAL_DMA_CLEAR_FLAG : stm32f3xx_hal_dma_ex.h
  • __HAL_DMA_DISABLE : stm32f3xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32f3xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32f3xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32f3xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32f3xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32f3xx_hal_dma_ex.h
  • __HAL_DMA_GET_GI_FLAG_INDEX : stm32f3xx_hal_dma_ex.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32f3xx_hal_dma_ex.h
  • __HAL_DMA_GET_IT_SOURCE : stm32f3xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32f3xx_hal_dma_ex.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32f3xx_hal_dma_ex.h
  • __HAL_DMA_REMAP_CHANNEL_DISABLE : stm32f3xx_hal.h
  • __HAL_DMA_REMAP_CHANNEL_ENABLE : stm32f3xx_hal.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32f3xx_hal_dma.h
  • __HAL_FLASH_CLEAR_FLAG : stm32f3xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32f3xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32f3xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32f3xx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32f3xx_hal_flash.h
  • __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE : stm32f3xx_hal_flash.h
  • __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE : stm32f3xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_DISABLE : stm32f3xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_ENABLE : stm32f3xx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32f3xx_hal_flash.h
  • __HAL_FREEZE_CAN_DBGMCU : stm32f3xx_hal.h
  • __HAL_FREEZE_TIM18_DBGMCU : stm32f3xx_hal.h
  • __HAL_FREEZE_TIM19_DBGMCU : stm32f3xx_hal.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32f3xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32f3xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32f3xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32f3xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32f3xx_hal_gpio.h
  • __HAL_I2C_CLEAR_FLAG : stm32f3xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32f3xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32f3xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32f3xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32f3xx_hal_i2c.h
  • __HAL_I2C_GENERATE_NACK : stm32f3xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32f3xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32f3xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32f3xx_hal_i2c.h
  • __HAL_I2S_CLEAR_OVRFLAG : stm32f3xx_hal_i2s.h
  • __HAL_I2S_CLEAR_UDRFLAG : stm32f3xx_hal_i2s.h
  • __HAL_I2S_DISABLE : stm32f3xx_hal_i2s.h
  • __HAL_I2S_DISABLE_IT : stm32f3xx_hal_i2s.h
  • __HAL_I2S_ENABLE : stm32f3xx_hal_i2s.h
  • __HAL_I2S_ENABLE_IT : stm32f3xx_hal_i2s.h
  • __HAL_I2S_GET_FLAG : stm32f3xx_hal_i2s.h
  • __HAL_I2S_GET_IT_SOURCE : stm32f3xx_hal_i2s.h
  • __HAL_I2S_RESET_HANDLE_STATE : stm32f3xx_hal_i2s.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32f3xx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32f3xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32f3xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IT : stm32f3xx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32f3xx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32f3xx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32f3xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32f3xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32f3xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32f3xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32f3xx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32f3xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32f3xx_hal_irda.h
  • __HAL_IRDA_GET_IT : stm32f3xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32f3xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE : stm32f3xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE : stm32f3xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32f3xx_hal_irda.h
  • __HAL_IRDA_SEND_REQ : stm32f3xx_hal_irda.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32f3xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32f3xx_hal_iwdg.h
  • __HAL_PCD_CLEAR_FLAG : stm32f3xx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32f3xx_hal_pcd.h
  • __HAL_PWR_CLEAR_FLAG : stm32f3xx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32f3xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32f3xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32f3xx_hal_pwr_ex.h
  • __HAL_RCC_ADC1_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_CONFIG : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_AHB_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_AHB_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_APB1_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_APB1_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_CAN1_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_CONFIG : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_CLEAR_IT : stm32f3xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32f3xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DAC1_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DAC1_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DAC2_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DAC2_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DAC2_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DAC2_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DAC2_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DAC2_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DISABLE_IT : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_ENABLE_IT : stm32f3xx_hal_rcc.h
  • __HAL_RCC_FLITF_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_FLITF_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_FLITF_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_FLITF_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_ADC1_SOURCE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GET_CEC_SOURCE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_I2C1_SOURCE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_I2C2_SOURCE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_RTC_SOURCE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_SDADC_SOURCE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_USART1_SOURCE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_USART2_SOURCE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_USART3_SOURCE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GET_USB_SOURCE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOF_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_GPIOF_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_HSE_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_HSE_GET_PREDIV : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_HSE_PREDIV_CONFIG : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32f3xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_I2C1_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_CONFIG : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_LSE_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_LSEDRIVE_CONFIG : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_LSI_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_PLL_CONFIG : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_PLL_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_PWR_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_PWR_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SDADC1_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC1_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC1_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC1_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC1_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC1_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC2_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC2_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC2_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC2_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC2_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC2_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC3_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC3_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC3_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC3_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC3_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC3_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SDADC_CONFIG : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SRAM_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SRAM_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SRAM_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM15_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM15_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM15_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM16_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM16_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM17_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM17_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM18_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM18_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM18_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM18_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM18_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM18_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM19_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM19_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM19_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM19_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM19_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM19_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM6_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM6_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_TSC_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TSC_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_TSC_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART1_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART2_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART3_CONFIG : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART3_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USART3_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_DISABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_USB_CLK_ENABLE : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_USB_CONFIG : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_USB_FORCE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_USB_IS_CLK_DISABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_USB_IS_CLK_ENABLED : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_USB_RELEASE_RESET : stm32f3xx_hal_rcc_ex.h
  • __HAL_RCC_WWDG_CLK_DISABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_ENABLE : stm32f3xx_hal_rcc.h
  • __HAL_RCC_WWDG_FORCE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_DISABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_ENABLED : stm32f3xx_hal_rcc.h
  • __HAL_RCC_WWDG_RELEASE_RESET : stm32f3xx_hal_rcc.h
  • __HAL_REMAPTRIGGER_DISABLE : stm32f3xx_hal.h
  • __HAL_REMAPTRIGGER_ENABLE : stm32f3xx_hal.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_FLAG : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GENERATE_SWIT : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GET_FLAG : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_DISABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_ENABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_DISABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_ENABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_DISABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_ENABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32f3xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32f3xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32f3xx_hal_rtc.h
  • __HAL_SDADC_CLEAR_FLAG : stm32f3xx_hal_sdadc.h
  • __HAL_SDADC_DISABLE_IT : stm32f3xx_hal_sdadc.h
  • __HAL_SDADC_ENABLE_IT : stm32f3xx_hal_sdadc.h
  • __HAL_SDADC_GET_FLAG : stm32f3xx_hal_sdadc.h
  • __HAL_SDADC_GET_IT_SOURCE : stm32f3xx_hal_sdadc.h
  • __HAL_SDADC_RESET_HANDLE_STATE : stm32f3xx_hal_sdadc.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IT : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32f3xx_hal_smartcard.h
  • __HAL_SMARTCARD_SEND_REQ : stm32f3xx_hal_smartcard.h
  • __HAL_SMBUS_CLEAR_FLAG : stm32f3xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE : stm32f3xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE_IT : stm32f3xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE : stm32f3xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE_IT : stm32f3xx_hal_smbus.h
  • __HAL_SMBUS_GENERATE_NACK : stm32f3xx_hal_smbus.h
  • __HAL_SMBUS_GET_FLAG : stm32f3xx_hal_smbus.h
  • __HAL_SMBUS_GET_IT_SOURCE : stm32f3xx_hal_smbus.h
  • __HAL_SMBUS_RESET_HANDLE_STATE : stm32f3xx_hal_smbus.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32f3xx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32f3xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32f3xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32f3xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32f3xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32f3xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32f3xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32f3xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32f3xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32f3xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32f3xx_hal_spi.h
  • __HAL_SYSCFG_BREAK_LOCKUP_LOCK : stm32f3xx_hal.h
  • __HAL_SYSCFG_BREAK_PVD_LOCK : stm32f3xx_hal.h
  • __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK : stm32f3xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_DISABLE : stm32f3xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_ENABLE : stm32f3xx_hal.h
  • __HAL_SYSCFG_INTERRUPT_DISABLE : stm32f3xx_hal.h
  • __HAL_SYSCFG_INTERRUPT_ENABLE : stm32f3xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_FLASH : stm32f3xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SRAM : stm32f3xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH : stm32f3xx_hal.h
  • __HAL_SYSCFG_VBAT_MONITORING_DISABLE : stm32f3xx_hal.h
  • __HAL_SYSCFG_VBAT_MONITORING_ENABLE : stm32f3xx_hal.h
  • __HAL_TIM_CLEAR_FLAG : stm32f3xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32f3xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32f3xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32f3xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32f3xx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxPRELOAD : stm32f3xx_hal_tim_ex.h
  • __HAL_TIM_ENABLE : stm32f3xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32f3xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32f3xx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxPRELOAD : stm32f3xx_hal_tim_ex.h
  • __HAL_TIM_GET_AUTORELOAD : stm32f3xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32f3xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32f3xx_hal_tim_ex.h
  • __HAL_TIM_GET_COUNTER : stm32f3xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32f3xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32f3xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32f3xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32f3xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32f3xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY : stm32f3xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32f3xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32f3xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32f3xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32f3xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32f3xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32f3xx_hal_tim_ex.h
  • __HAL_TIM_SET_COUNTER : stm32f3xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32f3xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32f3xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32f3xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32f3xx_hal_tim.h
  • __HAL_TSC_CLEAR_FLAG : stm32f3xx_hal_tsc.h
  • __HAL_TSC_CLOSE_ANALOG_SWITCH : stm32f3xx_hal_tsc.h
  • __HAL_TSC_DISABLE : stm32f3xx_hal_tsc.h
  • __HAL_TSC_DISABLE_CHANNEL : stm32f3xx_hal_tsc.h
  • __HAL_TSC_DISABLE_GROUP : stm32f3xx_hal_tsc.h
  • __HAL_TSC_DISABLE_HYSTERESIS : stm32f3xx_hal_tsc.h
  • __HAL_TSC_DISABLE_IT : stm32f3xx_hal_tsc.h
  • __HAL_TSC_DISABLE_SAMPLING : stm32f3xx_hal_tsc.h
  • __HAL_TSC_ENABLE : stm32f3xx_hal_tsc.h
  • __HAL_TSC_ENABLE_CHANNEL : stm32f3xx_hal_tsc.h
  • __HAL_TSC_ENABLE_GROUP : stm32f3xx_hal_tsc.h
  • __HAL_TSC_ENABLE_HYSTERESIS : stm32f3xx_hal_tsc.h
  • __HAL_TSC_ENABLE_IT : stm32f3xx_hal_tsc.h
  • __HAL_TSC_ENABLE_SAMPLING : stm32f3xx_hal_tsc.h
  • __HAL_TSC_GET_FLAG : stm32f3xx_hal_tsc.h
  • __HAL_TSC_GET_GROUP_STATUS : stm32f3xx_hal_tsc.h
  • __HAL_TSC_GET_IT_SOURCE : stm32f3xx_hal_tsc.h
  • __HAL_TSC_OPEN_ANALOG_SWITCH : stm32f3xx_hal_tsc.h
  • __HAL_TSC_RESET_HANDLE_STATE : stm32f3xx_hal_tsc.h
  • __HAL_TSC_SET_IODEF_INFLOAT : stm32f3xx_hal_tsc.h
  • __HAL_TSC_SET_IODEF_OUTPPLOW : stm32f3xx_hal_tsc.h
  • __HAL_TSC_SET_SYNC_POL_FALL : stm32f3xx_hal_tsc.h
  • __HAL_TSC_SET_SYNC_POL_RISE_HIGH : stm32f3xx_hal_tsc.h
  • __HAL_TSC_START_ACQ : stm32f3xx_hal_tsc.h
  • __HAL_TSC_STOP_ACQ : stm32f3xx_hal_tsc.h
  • __HAL_UART_CLEAR_FEFLAG : stm32f3xx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32f3xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32f3xx_hal_uart.h
  • __HAL_UART_CLEAR_IT : stm32f3xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32f3xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32f3xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32f3xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32f3xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32f3xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32f3xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32f3xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32f3xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32f3xx_hal_uart.h
  • __HAL_UART_GET_IT : stm32f3xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32f3xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32f3xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32f3xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32f3xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32f3xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32f3xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32f3xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32f3xx_hal_uart.h
  • __HAL_UART_SEND_REQ : stm32f3xx_hal_uart.h
  • __HAL_UNFREEZE_CAN_DBGMCU : stm32f3xx_hal.h
  • __HAL_UNFREEZE_TIM18_DBGMCU : stm32f3xx_hal.h
  • __HAL_UNFREEZE_TIM19_DBGMCU : stm32f3xx_hal.h
  • __HAL_USART_CLEAR_FEFLAG : stm32f3xx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32f3xx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32f3xx_hal_usart.h
  • __HAL_USART_CLEAR_IT : stm32f3xx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32f3xx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32f3xx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32f3xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32f3xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32f3xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32f3xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32f3xx_hal_usart.h
  • __HAL_USART_FLUSH_DRREGISTER : stm32f3xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32f3xx_hal_usart.h
  • __HAL_USART_GET_IT : stm32f3xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32f3xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_DISABLE : stm32f3xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_ENABLE : stm32f3xx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32f3xx_hal_usart.h
  • __HAL_USART_SEND_REQ : stm32f3xx_hal_usart.h
  • __HAL_USB_EXTI_GENERATE_SWIT : stm32f3xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG : stm32f3xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_DISABLE_IT : stm32f3xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32f3xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_IT : stm32f3xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32f3xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f3xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_GET_FLAG : stm32f3xx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32f3xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32f3xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32f3xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32f3xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32f3xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32f3xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32f3xx_hal_wwdg.h
  • __LL_ADC_ANALOGWD_CHANNEL_GROUP : stm32f3xx_ll_adc.h
  • __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION : stm32f3xx_ll_adc.h
  • __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION : stm32f3xx_ll_adc.h
  • __LL_ADC_CALC_DATA_TO_VOLTAGE : stm32f3xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE : stm32f3xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32f3xx_ll_adc.h
  • __LL_ADC_CALC_VREFANALOG_VOLTAGE : stm32f3xx_ll_adc.h
  • __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32f3xx_ll_adc.h
  • __LL_ADC_CHANNEL_TO_DECIMAL_NB : stm32f3xx_ll_adc.h
  • __LL_ADC_COMMON_INSTANCE : stm32f3xx_ll_adc.h
  • __LL_ADC_CONVERT_DATA_RESOLUTION : stm32f3xx_ll_adc.h
  • __LL_ADC_DECIMAL_NB_TO_CHANNEL : stm32f3xx_ll_adc.h
  • __LL_ADC_DIGITAL_SCALE : stm32f3xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL : stm32f3xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32f3xx_ll_adc.h
  • __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32f3xx_ll_adc.h
  • __LL_COMP_COMMON_INSTANCE : stm32f3xx_ll_comp.h
  • __LL_DAC_CALC_VOLTAGE_TO_DATA : stm32f3xx_ll_dac.h
  • __LL_DAC_CHANNEL_TO_DECIMAL_NB : stm32f3xx_ll_dac.h
  • __LL_DAC_DECIMAL_NB_TO_CHANNEL : stm32f3xx_ll_dac.h
  • __LL_DAC_DIGITAL_SCALE : stm32f3xx_ll_dac.h
  • __LL_DMA_GET_CHANNEL : stm32f3xx_ll_dma.h
  • __LL_DMA_GET_CHANNEL_INSTANCE : stm32f3xx_ll_dma.h
  • __LL_DMA_GET_INSTANCE : stm32f3xx_ll_dma.h
  • __LL_I2C_CONVERT_TIMINGS : stm32f3xx_ll_i2c.h
  • __LL_RCC_CALC_HCLK_FREQ : stm32f3xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK1_FREQ : stm32f3xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK2_FREQ : stm32f3xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_FREQ : stm32f3xx_ll_rcc.h
  • __LL_RTC_CONVERT_BCD2BIN : stm32f3xx_ll_rtc.h
  • __LL_RTC_CONVERT_BIN2BCD : stm32f3xx_ll_rtc.h
  • __LL_RTC_GET_DAY : stm32f3xx_ll_rtc.h
  • __LL_RTC_GET_HOUR : stm32f3xx_ll_rtc.h
  • __LL_RTC_GET_MINUTE : stm32f3xx_ll_rtc.h
  • __LL_RTC_GET_MONTH : stm32f3xx_ll_rtc.h
  • __LL_RTC_GET_SECOND : stm32f3xx_ll_rtc.h
  • __LL_RTC_GET_WEEKDAY : stm32f3xx_ll_rtc.h
  • __LL_RTC_GET_YEAR : stm32f3xx_ll_rtc.h
  • __LL_TIM_CALC_ARR : stm32f3xx_ll_tim.h
  • __LL_TIM_CALC_DEADTIME : stm32f3xx_ll_tim.h
  • __LL_TIM_CALC_DELAY : stm32f3xx_ll_tim.h
  • __LL_TIM_CALC_PSC : stm32f3xx_ll_tim.h
  • __LL_TIM_CALC_PULSE : stm32f3xx_ll_tim.h
  • __LL_TIM_GET_ICPSC_RATIO : stm32f3xx_ll_tim.h
  • __LL_TIM_GETFLAG_UIFCPY : stm32f3xx_ll_tim.h
  • __LL_USART_DIV_SAMPLING16 : stm32f3xx_ll_usart.h
  • __LL_USART_DIV_SAMPLING8 : stm32f3xx_ll_usart.h
  • __STM32F3xx_HAL_VERSION : stm32f3xx_hal.c
  • __STM32F3xx_HAL_VERSION_MAIN : stm32f3xx_hal.c
  • __STM32F3xx_HAL_VERSION_RC : stm32f3xx_hal.c
  • __STM32F3xx_HAL_VERSION_SUB1 : stm32f3xx_hal.c
  • __STM32F3xx_HAL_VERSION_SUB2 : stm32f3xx_hal.c
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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- a -

  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32f3xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32f3xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32f3xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_NONE : stm32f3xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32f3xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32f3xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32f3xx_hal_adc_ex.h
  • ADC_AWD_CR1_CHANNEL_MASK : stm32f3xx_ll_adc.h
  • ADC_AWD_CR1_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_AWD_CR_ALL_CHANNEL_MASK : stm32f3xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_MASK : stm32f3xx_ll_adc.h
  • ADC_AWD_EVENT : stm32f3xx_hal_adc_ex.h
  • ADC_AWD_TR1_HIGH_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_AWD_TR1_LOW_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_MASK : stm32f3xx_ll_adc.h
  • ADC_CALFACT_DIFF_GET : stm32f3xx_hal_adc_ex.h
  • ADC_CALFACT_DIFF_SET : stm32f3xx_hal_adc_ex.h
  • ADC_CALIBRATION_TIMEOUT : stm32f3xx_hal_adc_ex.c
  • ADC_CHANNEL_0 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_0_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_0_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_1 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_10 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_10_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_10_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_11 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_11_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_11_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_12 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_12_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_12_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_13 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_13_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_13_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_14 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_14_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_14_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_15 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_15_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_15_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_16 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_16_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_16_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_17 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_17_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_17_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_18 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_1_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_1_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_2 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_2_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_2_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_3 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_3_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_3_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_4 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_4_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_4_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_5 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_5_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_5_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_6 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_6_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_6_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_7 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_7_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_7_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_8 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_8_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_8_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_9 : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_9_NUMBER : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_9_SMP : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_2 : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_MASK : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_ID_MASK : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_SMPRX_REGOFFSET_MASK : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_MASK : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_VBAT : stm32f3xx_hal_adc_ex.h
  • ADC_CHANNEL_VREFINT : stm32f3xx_hal_adc_ex.h
  • ADC_CLEAR_ERRORCODE : stm32f3xx_hal_adc_ex.h
  • ADC_CLOCK_PRESCALER_RANGE : stm32f3xx_hal_adc_ex.h
  • ADC_CONVCYCLES_MAX_RANGE : stm32f3xx_hal_adc_ex.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 : stm32f3xx_hal_adc_ex.c
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 : stm32f3xx_hal_adc_ex.c
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 : stm32f3xx_hal_adc_ex.c
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 : stm32f3xx_hal_adc_ex.c
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 : stm32f3xx_hal_adc_ex.c
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 : stm32f3xx_hal_adc_ex.c
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : stm32f3xx_hal_adc_ex.c
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : stm32f3xx_hal_adc_ex.c
  • ADC_CR1_DISCONTINUOUS_NUM : stm32f3xx_hal_adc_ex.h
  • ADC_CR1_DUALMOD_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_CR1_SCAN_SET : stm32f3xx_hal_adc_ex.h
  • ADC_CR2_CONTINUOUS : stm32f3xx_hal_adc_ex.h
  • ADC_CYCLE_WORST_CASE_CPU_CYCLES : stm32f3xx_hal_adc_ex.c
  • ADC_DATAALIGN_LEFT : stm32f3xx_hal_adc_ex.h
  • ADC_DATAALIGN_RIGHT : stm32f3xx_hal_adc_ex.h
  • ADC_DISABLE_TIMEOUT : stm32f3xx_hal_adc_ex.c
  • ADC_ENABLE_TIMEOUT : stm32f3xx_hal_adc_ex.c
  • ADC_EXTERNALTRIG_EXT_IT11 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIG_T19_CC3 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIG_T19_CC4 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIG_T19_TRGO : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIG_T2_CC2 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIG_T3_TRGO : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIG_T4_CC4 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_EXT_IT11 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T19_CC3 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T19_CC4 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T19_TRGO : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T2_CC2 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T3_TRGO : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T4_CC4 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_EXT_IT15 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T19_CC1 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T19_CC2 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_CC1 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_TRGO : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC4 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T4_TRGO : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_NONE : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISING : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EXT_IT15 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T19_CC1 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T19_CC2 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T2_CC1 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T2_TRGO : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T3_CC4 : stm32f3xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T4_TRGO : stm32f3xx_hal_adc_ex.h
  • ADC_FLAG_AWD : stm32f3xx_hal_adc_ex.h
  • ADC_FLAG_EOC : stm32f3xx_hal_adc_ex.h
  • ADC_FLAG_JEOC : stm32f3xx_hal_adc_ex.h
  • ADC_FLAG_JSTRT : stm32f3xx_hal_adc_ex.h
  • ADC_FLAG_POSTCONV_ALL : stm32f3xx_hal_adc_ex.h
  • ADC_FLAG_STRT : stm32f3xx_hal_adc_ex.h
  • ADC_GET_CLOCK_PRESCALER : stm32f3xx_hal_adc_ex.h
  • ADC_INJ_JDRX_REGOFFSET_MASK : stm32f3xx_ll_adc.h
  • ADC_INJ_JOFRX_REGOFFSET_MASK : stm32f3xx_ll_adc.h
  • ADC_INJ_RANK_1_JSQR_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_INJ_RANK_2_JSQR_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_INJ_RANK_3_JSQR_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_INJ_RANK_4_JSQR_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_INJ_RANK_ID_JSQR_MASK : stm32f3xx_ll_adc.h
  • ADC_INJECTED_GROUP : stm32f3xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_1 : stm32f3xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32f3xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32f3xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32f3xx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32f3xx_hal_adc_ex.h
  • ADC_IS_ENABLE : stm32f3xx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32f3xx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_REGULAR : stm32f3xx_hal_adc_ex.h
  • ADC_IT_AWD : stm32f3xx_hal_adc_ex.h
  • ADC_IT_EOC : stm32f3xx_hal_adc_ex.h
  • ADC_IT_JEOC : stm32f3xx_hal_adc_ex.h
  • ADC_JDR1_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_JDR2_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_JDR3_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_JDR4_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_JOFR1_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_JOFR2_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_JOFR3_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_JOFR4_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_JSQR_JL_SHIFT : stm32f3xx_hal_adc_ex.h
  • ADC_JSQR_RK_JL : stm32f3xx_hal_adc_ex.h
  • ADC_JSWSTART : stm32f3xx_hal_adc_ex.h
  • ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES : stm32f3xx_hal_adc_ex.c
  • ADC_REG_RANK_10_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_11_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_12_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_13_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_14_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_15_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_16_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_1_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_2_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_3_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_4_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_5_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_6_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_7_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_8_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_9_SQRX_BITOFFSET_POS : stm32f3xx_ll_adc.h
  • ADC_REG_RANK_ID_SQRX_MASK : stm32f3xx_ll_adc.h
  • ADC_REG_SQRX_REGOFFSET_MASK : stm32f3xx_ll_adc.h
  • ADC_REGULAR_GROUP : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_INJECTED_GROUP : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_1 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_10 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_11 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_12 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_13 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_14 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_15 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_16 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_2 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_3 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_4 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_5 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_6 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_7 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_8 : stm32f3xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_9 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_13CYCLES_5 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_1CYCLE_5 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_239CYCLES_5 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_28CYCLES_5 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_41CYCLES_5 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_55CYCLES_5 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_71CYCLES_5 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_7CYCLES_5 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 : stm32f3xx_hal_adc_ex.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 : stm32f3xx_hal_adc_ex.h
  • ADC_SCAN_DISABLE : stm32f3xx_hal_adc_ex.h
  • ADC_SCAN_ENABLE : stm32f3xx_hal_adc_ex.h
  • ADC_SMPR1 : stm32f3xx_hal_adc_ex.h
  • ADC_SMPR1_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_SMPR2 : stm32f3xx_hal_adc_ex.h
  • ADC_SMPR2_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_SOFTWARE_START : stm32f3xx_hal_adc_ex.h
  • ADC_SQR1_L_SHIFT : stm32f3xx_hal_adc_ex.h
  • ADC_SQR1_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_SQR1_RK : stm32f3xx_hal_adc_ex.h
  • ADC_SQR2_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_SQR2_RK : stm32f3xx_hal_adc_ex.h
  • ADC_SQR3_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_SQR3_RK : stm32f3xx_hal_adc_ex.h
  • ADC_SQR4_REGOFFSET : stm32f3xx_ll_adc.h
  • ADC_STAB_DELAY_US : stm32f3xx_hal_adc_ex.c
  • ADC_STATE_CLR_SET : stm32f3xx_hal_adc_ex.h
  • ADC_SWSTART : stm32f3xx_hal_adc_ex.h
  • ADC_TEMPSENSOR_DELAY_US : stm32f3xx_hal_adc_ex.c
  • assert_param : stm32f3xx_ll_usart.c , stm32f3xx_ll_rcc.c , stm32f3xx_ll_dac.c , stm32f3xx_ll_tim.c , stm32f3xx_ll_crc.c , stm32f3xx_ll_rtc.c , stm32f3xx_ll_opamp.c , stm32f3xx_ll_exti.c , stm32f3xx_ll_adc.c , stm32f3xx_ll_spi.c , stm32f3xx_ll_i2c.c , stm32f3xx_ll_dma.c , stm32f3xx_hal_conf.h , stm32f3xx_ll_utils.c , stm32f3xx_ll_hrtim.c , stm32f3xx_ll_gpio.c , stm32f3xx_ll_comp.c
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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- b -

  • BDCR_REG_INDEX : stm32f3xx_hal_rcc.h
  • BTABLE_ADDRESS : stm32f3xx_hal_pcd.c
  • BYPADDRPAR_BitNumber : stm32f3xx_hal.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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  • Globals
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  • Typedefs
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- c -

  • CAN_BS1_10TQ : stm32f3xx_hal_can.h
  • CAN_BS1_11TQ : stm32f3xx_hal_can.h
  • CAN_BS1_12TQ : stm32f3xx_hal_can.h
  • CAN_BS1_13TQ : stm32f3xx_hal_can.h
  • CAN_BS1_14TQ : stm32f3xx_hal_can.h
  • CAN_BS1_15TQ : stm32f3xx_hal_can.h
  • CAN_BS1_16TQ : stm32f3xx_hal_can.h
  • CAN_BS1_1TQ : stm32f3xx_hal_can.h
  • CAN_BS1_2TQ : stm32f3xx_hal_can.h
  • CAN_BS1_3TQ : stm32f3xx_hal_can.h
  • CAN_BS1_4TQ : stm32f3xx_hal_can.h
  • CAN_BS1_5TQ : stm32f3xx_hal_can.h
  • CAN_BS1_6TQ : stm32f3xx_hal_can.h
  • CAN_BS1_7TQ : stm32f3xx_hal_can.h
  • CAN_BS1_8TQ : stm32f3xx_hal_can.h
  • CAN_BS1_9TQ : stm32f3xx_hal_can.h
  • CAN_BS2_1TQ : stm32f3xx_hal_can.h
  • CAN_BS2_2TQ : stm32f3xx_hal_can.h
  • CAN_BS2_3TQ : stm32f3xx_hal_can.h
  • CAN_BS2_4TQ : stm32f3xx_hal_can.h
  • CAN_BS2_5TQ : stm32f3xx_hal_can.h
  • CAN_BS2_6TQ : stm32f3xx_hal_can.h
  • CAN_BS2_7TQ : stm32f3xx_hal_can.h
  • CAN_BS2_8TQ : stm32f3xx_hal_can.h
  • CAN_FIFO0 : stm32f3xx_hal_can.h
  • CAN_FIFO1 : stm32f3xx_hal_can.h
  • CAN_FILTER_FIFO0 : stm32f3xx_hal_can.h
  • CAN_FILTER_FIFO1 : stm32f3xx_hal_can.h
  • CAN_FILTERMODE_IDLIST : stm32f3xx_hal_can.h
  • CAN_FILTERMODE_IDMASK : stm32f3xx_hal_can.h
  • CAN_FILTERSCALE_16BIT : stm32f3xx_hal_can.h
  • CAN_FILTERSCALE_32BIT : stm32f3xx_hal_can.h
  • CAN_FLAG_BOF : stm32f3xx_hal_can.h
  • CAN_FLAG_EPV : stm32f3xx_hal_can.h
  • CAN_FLAG_ERRI : stm32f3xx_hal_can.h
  • CAN_FLAG_EWG : stm32f3xx_hal_can.h
  • CAN_FLAG_FF0 : stm32f3xx_hal_can.h
  • CAN_FLAG_FF1 : stm32f3xx_hal_can.h
  • CAN_FLAG_FOV0 : stm32f3xx_hal_can.h
  • CAN_FLAG_FOV1 : stm32f3xx_hal_can.h
  • CAN_FLAG_INAK : stm32f3xx_hal_can.h
  • CAN_FLAG_MASK : stm32f3xx_hal_can.h
  • CAN_FLAG_RQCP0 : stm32f3xx_hal_can.h
  • CAN_FLAG_RQCP1 : stm32f3xx_hal_can.h
  • CAN_FLAG_RQCP2 : stm32f3xx_hal_can.h
  • CAN_FLAG_SLAK : stm32f3xx_hal_can.h
  • CAN_FLAG_SLAKI : stm32f3xx_hal_can.h
  • CAN_FLAG_TME0 : stm32f3xx_hal_can.h
  • CAN_FLAG_TME1 : stm32f3xx_hal_can.h
  • CAN_FLAG_TME2 : stm32f3xx_hal_can.h
  • CAN_FLAG_TXOK0 : stm32f3xx_hal_can.h
  • CAN_FLAG_TXOK1 : stm32f3xx_hal_can.h
  • CAN_FLAG_TXOK2 : stm32f3xx_hal_can.h
  • CAN_FLAG_WKU : stm32f3xx_hal_can.h
  • CAN_ID_EXT : stm32f3xx_hal_can.h
  • CAN_ID_STD : stm32f3xx_hal_can.h
  • CAN_INITSTATUS_FAILED : stm32f3xx_hal_can.h
  • CAN_INITSTATUS_SUCCESS : stm32f3xx_hal_can.h
  • CAN_IT_BOF : stm32f3xx_hal_can.h
  • CAN_IT_EPV : stm32f3xx_hal_can.h
  • CAN_IT_ERR : stm32f3xx_hal_can.h
  • CAN_IT_EWG : stm32f3xx_hal_can.h
  • CAN_IT_FF0 : stm32f3xx_hal_can.h
  • CAN_IT_FF1 : stm32f3xx_hal_can.h
  • CAN_IT_FMP0 : stm32f3xx_hal_can.h
  • CAN_IT_FMP1 : stm32f3xx_hal_can.h
  • CAN_IT_FOV0 : stm32f3xx_hal_can.h
  • CAN_IT_FOV1 : stm32f3xx_hal_can.h
  • CAN_IT_LEC : stm32f3xx_hal_can.h
  • CAN_IT_SLK : stm32f3xx_hal_can.h
  • CAN_IT_TME : stm32f3xx_hal_can.h
  • CAN_IT_WKU : stm32f3xx_hal_can.h
  • CAN_MODE_LOOPBACK : stm32f3xx_hal_can.h
  • CAN_MODE_NORMAL : stm32f3xx_hal_can.h
  • CAN_MODE_SILENT : stm32f3xx_hal_can.h
  • CAN_MODE_SILENT_LOOPBACK : stm32f3xx_hal_can.h
  • CAN_RTR_DATA : stm32f3xx_hal_can.h
  • CAN_RTR_REMOTE : stm32f3xx_hal_can.h
  • CAN_SJW_1TQ : stm32f3xx_hal_can.h
  • CAN_SJW_2TQ : stm32f3xx_hal_can.h
  • CAN_SJW_3TQ : stm32f3xx_hal_can.h
  • CAN_SJW_4TQ : stm32f3xx_hal_can.h
  • CAN_TIMEOUT_VALUE : stm32f3xx_hal_can.c
  • CAN_TXMAILBOX_0 : stm32f3xx_hal_can.h
  • CAN_TXMAILBOX_1 : stm32f3xx_hal_can.h
  • CAN_TXMAILBOX_2 : stm32f3xx_hal_can.h
  • CAN_TXSTATUS_NOMAILBOX : stm32f3xx_hal_can.h
  • CEC_0_5_BITPERIOD_SFT : stm32f3xx_hal_cec.h
  • CEC_1_5_BITPERIOD_SFT : stm32f3xx_hal_cec.h
  • CEC_2_5_BITPERIOD_SFT : stm32f3xx_hal_cec.h
  • CEC_3_5_BITPERIOD_SFT : stm32f3xx_hal_cec.h
  • CEC_4_5_BITPERIOD_SFT : stm32f3xx_hal_cec.h
  • CEC_5_5_BITPERIOD_SFT : stm32f3xx_hal_cec.h
  • CEC_6_5_BITPERIOD_SFT : stm32f3xx_hal_cec.h
  • CEC_BRE_ERRORBIT_GENERATION : stm32f3xx_hal_cec.h
  • CEC_BRE_ERRORBIT_NO_GENERATION : stm32f3xx_hal_cec.h
  • CEC_BROADCASTERROR_ERRORBIT_GENERATION : stm32f3xx_hal_cec.h
  • CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32f3xx_hal_cec.h
  • CEC_CFGR_OAR_LSB_POS : stm32f3xx_hal_cec.h
  • CEC_DEFAULT_SFT : stm32f3xx_hal_cec.h
  • CEC_EXTENDED_TOLERANCE : stm32f3xx_hal_cec.h
  • CEC_FLAG_ARBLST : stm32f3xx_hal_cec.h
  • CEC_FLAG_BRE : stm32f3xx_hal_cec.h
  • CEC_FLAG_LBPE : stm32f3xx_hal_cec.h
  • CEC_FLAG_RXACKE : stm32f3xx_hal_cec.h
  • CEC_FLAG_RXBR : stm32f3xx_hal_cec.h
  • CEC_FLAG_RXEND : stm32f3xx_hal_cec.h
  • CEC_FLAG_RXOVR : stm32f3xx_hal_cec.h
  • CEC_FLAG_SBPE : stm32f3xx_hal_cec.h
  • CEC_FLAG_TXACKE : stm32f3xx_hal_cec.h
  • CEC_FLAG_TXBR : stm32f3xx_hal_cec.h
  • CEC_FLAG_TXEND : stm32f3xx_hal_cec.h
  • CEC_FLAG_TXERR : stm32f3xx_hal_cec.h
  • CEC_FLAG_TXUDR : stm32f3xx_hal_cec.h
  • CEC_FULL_LISTENING_MODE : stm32f3xx_hal_cec.h
  • CEC_IER_RX_ALL_ERR : stm32f3xx_hal_cec.h
  • CEC_IER_TX_ALL_ERR : stm32f3xx_hal_cec.h
  • CEC_INITIATOR_LSB_POS : stm32f3xx_hal_cec.h
  • CEC_ISR_ALL_ERROR : stm32f3xx_hal_cec.h
  • CEC_IT_ARBLST : stm32f3xx_hal_cec.h
  • CEC_IT_BRE : stm32f3xx_hal_cec.h
  • CEC_IT_LBPE : stm32f3xx_hal_cec.h
  • CEC_IT_RXACKE : stm32f3xx_hal_cec.h
  • CEC_IT_RXBR : stm32f3xx_hal_cec.h
  • CEC_IT_RXEND : stm32f3xx_hal_cec.h
  • CEC_IT_RXOVR : stm32f3xx_hal_cec.h
  • CEC_IT_SBPE : stm32f3xx_hal_cec.h
  • CEC_IT_TXACKE : stm32f3xx_hal_cec.h
  • CEC_IT_TXBR : stm32f3xx_hal_cec.h
  • CEC_IT_TXEND : stm32f3xx_hal_cec.h
  • CEC_IT_TXERR : stm32f3xx_hal_cec.h
  • CEC_IT_TXUDR : stm32f3xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_GENERATION : stm32f3xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_NO_GENERATION : stm32f3xx_hal_cec.h
  • CEC_NO_RX_STOP_ON_BRE : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_0 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_1 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_10 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_11 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_12 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_13 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_14 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_2 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_3 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_4 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_5 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_6 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_7 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_8 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_9 : stm32f3xx_hal_cec.h
  • CEC_OWN_ADDRESS_NONE : stm32f3xx_hal_cec.h
  • CEC_REDUCED_LISTENING_MODE : stm32f3xx_hal_cec.h
  • CEC_RX_STOP_ON_BRE : stm32f3xx_hal_cec.h
  • CEC_SFT_START_ON_TX_RX_END : stm32f3xx_hal_cec.h
  • CEC_SFT_START_ON_TXSOM : stm32f3xx_hal_cec.h
  • CEC_STANDARD_TOLERANCE : stm32f3xx_hal_cec.h
  • CFGR2_BYPADDRPAR_BB : stm32f3xx_hal.h
  • CFGR2_OFFSET : stm32f3xx_hal.h
  • CFGR_REG_INDEX : stm32f3xx_hal_rcc.h
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32f3xx_hal_rcc.h
  • COMP_BLANKINGSRCE_NONE : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMP1_SHIFT : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMP2_SHIFT : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMPxBLANKING_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMPxHYST_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMPxINSEL_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMPxMODE_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMPxNONINSEL_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMPxOUTSEL_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMPxPOL_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_COMPxWNDWEN_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_RESET_PARAMETERS_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_RESET_VALUE : stm32f3xx_hal_comp_ex.h
  • COMP_CSR_UPDATE_PARAMETERS_MASK : stm32f3xx_hal_comp_ex.h
  • COMP_DEINIT : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_CLEAR_FLAG : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_DISABLE_EVENT : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_DISABLE_IT : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_ENABLE_EVENT : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_ENABLE_IT : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_FALLING_DISABLE : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_FALLING_ENABLE : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_GET_FLAG : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_LINE_COMP1 : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_LINE_COMP2 : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_RISING_DISABLE : stm32f3xx_hal_comp_ex.h
  • COMP_EXTI_RISING_ENABLE : stm32f3xx_hal_comp_ex.h
  • COMP_FLAG_LOCK : stm32f3xx_hal_comp_ex.h
  • COMP_GET_EXTI_LINE : stm32f3xx_hal_comp_ex.h
  • COMP_HYSTERESIS_HIGH : stm32f3xx_hal_comp_ex.h
  • COMP_HYSTERESIS_LOW : stm32f3xx_hal_comp_ex.h
  • COMP_HYSTERESIS_MEDIUM : stm32f3xx_hal_comp_ex.h
  • COMP_HYSTERESIS_NONE : stm32f3xx_hal_comp_ex.h
  • COMP_INIT : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_1_2VREFINT : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_1_4VREFINT : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_3_4VREFINT : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_DAC1 : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_DAC1_CH1 : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_DAC1_CH2 : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_DAC2 : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_DAC2_CH1 : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_IO1 : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_SELECTION : stm32f3xx_hal_comp_ex.h
  • COMP_INVERTINGINPUT_VREFINT : stm32f3xx_hal_comp_ex.h
  • COMP_LOCK_DISABLE : stm32f3xx_hal_comp.c
  • COMP_LOCK_ENABLE : stm32f3xx_hal_comp.c
  • COMP_MODE_HIGHSPEED : stm32f3xx_hal_comp_ex.h
  • COMP_MODE_LOWPOWER : stm32f3xx_hal_comp_ex.h
  • COMP_MODE_MEDIUMSPEED : stm32f3xx_hal_comp_ex.h
  • COMP_MODE_ULTRALOWPOWER : stm32f3xx_hal_comp_ex.h
  • COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED : stm32f3xx_hal_comp_ex.h
  • COMP_NONINVERTINGINPUT_IO1 : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_COMP1_TIM3IC1 : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_COMP1_TIM3OCREFCLR : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_COMP2_TIM3IC1 : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_COMP2_TIM3OCREFCLR : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_NONE : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_TIM15BKIN : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_TIM16BKIN : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_TIM2IC4 : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_TIM2OCREFCLR : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_TIM4IC1 : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_TIM4OCREFCLR : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_TIM5IC4 : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUT_TIM5OCREFCLR : stm32f3xx_hal_comp_ex.h
  • COMP_OUTPUTLEVEL_HIGH : stm32f3xx_hal_comp.h
  • COMP_OUTPUTLEVEL_LOW : stm32f3xx_hal_comp.h
  • COMP_OUTPUTPOL_INVERTED : stm32f3xx_hal_comp.h
  • COMP_OUTPUTPOL_NONINVERTED : stm32f3xx_hal_comp.h
  • COMP_STATE_BIT_LOCK : stm32f3xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_FALLING : stm32f3xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING : stm32f3xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING_FALLING : stm32f3xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_FALLING : stm32f3xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING : stm32f3xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING_FALLING : stm32f3xx_hal_comp.h
  • COMP_TRIGGERMODE_NONE : stm32f3xx_hal_comp.h
  • COMP_WINDOWMODE_DISABLE : stm32f3xx_hal_comp_ex.h
  • COMP_WINDOWMODE_ENABLE : stm32f3xx_hal_comp_ex.h
  • COMPX : stm32f3xx_ll_comp.h
  • COMPX_BASE : stm32f3xx_ll_comp.h
  • CR_REG_INDEX : stm32f3xx_hal_rcc.h
  • CRC_INPUTDATA_FORMAT_BYTES : stm32f3xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_HALFWORDS : stm32f3xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_UNDEFINED : stm32f3xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_WORDS : stm32f3xx_hal_crc.h
  • CRC_INPUTDATA_INVERSION_BYTE : stm32f3xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_HALFWORD : stm32f3xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_NONE : stm32f3xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_WORD : stm32f3xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_DISABLE : stm32f3xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_ENABLE : stm32f3xx_hal_crc_ex.h
  • CRC_POLYLENGTH_16B : stm32f3xx_hal_crc.h
  • CRC_POLYLENGTH_32B : stm32f3xx_hal_crc.h
  • CRC_POLYLENGTH_7B : stm32f3xx_hal_crc.h
  • CRC_POLYLENGTH_8B : stm32f3xx_hal_crc.h
  • CSR_REG_INDEX : stm32f3xx_hal_rcc.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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- d -

  • DAC_ALIGN_12B_L : stm32f3xx_hal_dac.h
  • DAC_ALIGN_12B_R : stm32f3xx_hal_dac.h
  • DAC_ALIGN_8B_R : stm32f3xx_hal_dac.h
  • DAC_CHANNEL_1 : stm32f3xx_hal_dac_ex.h
  • DAC_CHANNEL_2 : stm32f3xx_hal_dac_ex.h
  • DAC_CR_CH1_BITOFFSET : stm32f3xx_ll_dac.h
  • DAC_CR_CH2_BITOFFSET : stm32f3xx_ll_dac.h
  • DAC_CR_CHX_BITOFFSET_MASK : stm32f3xx_ll_dac.h
  • DAC_DHR12LD_DACC2DHR_BITOFFSET_POS : stm32f3xx_ll_dac.h
  • DAC_DHR12R1_ALIGNMENT : stm32f3xx_hal_dac.h
  • DAC_DHR12R2_ALIGNMENT : stm32f3xx_hal_dac.h
  • DAC_DHR12RD_ALIGNMENT : stm32f3xx_hal_dac.h
  • DAC_DHR12RD_DACC2DHR_BITOFFSET_POS : stm32f3xx_ll_dac.h
  • DAC_DHR8RD_DACC2DHR_BITOFFSET_POS : stm32f3xx_ll_dac.h
  • DAC_DIGITAL_SCALE_12BITS : stm32f3xx_ll_dac.h
  • DAC_FLAG_DMAUDR1 : stm32f3xx_hal_dac.h
  • DAC_FLAG_DMAUDR2 : stm32f3xx_hal_dac.h
  • DAC_IT_DMAUDR1 : stm32f3xx_hal_dac.h
  • DAC_IT_DMAUDR2 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BIT0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS10_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS11_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS1_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS2_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS3_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS4_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS5_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS6_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS7_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS8_0 : stm32f3xx_hal_dac.h
  • DAC_LFSRUNMASK_BITS9_0 : stm32f3xx_hal_dac.h
  • DAC_OUTPUTBUFFER_DISABLE : stm32f3xx_hal_dac.h
  • DAC_OUTPUTBUFFER_ENABLE : stm32f3xx_hal_dac.h
  • DAC_REG_DHR12L1_REGOFFSET : stm32f3xx_ll_dac.h
  • DAC_REG_DHR12L2_REGOFFSET : stm32f3xx_ll_dac.h
  • DAC_REG_DHR12LX_REGOFFSET_MASK : stm32f3xx_ll_dac.h
  • DAC_REG_DHR12R1_REGOFFSET : stm32f3xx_ll_dac.h
  • DAC_REG_DHR12R2_REGOFFSET : stm32f3xx_ll_dac.h
  • DAC_REG_DHR12RX_REGOFFSET_MASK : stm32f3xx_ll_dac.h
  • DAC_REG_DHR8R1_REGOFFSET : stm32f3xx_ll_dac.h
  • DAC_REG_DHR8R2_REGOFFSET : stm32f3xx_ll_dac.h
  • DAC_REG_DHR8RX_REGOFFSET_MASK : stm32f3xx_ll_dac.h
  • DAC_REG_DHRX_REGOFFSET_MASK : stm32f3xx_ll_dac.h
  • DAC_REG_DOR1_REGOFFSET : stm32f3xx_ll_dac.h
  • DAC_REG_DOR2_REGOFFSET : stm32f3xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_MASK : stm32f3xx_ll_dac.h
  • DAC_SWTR_CH1 : stm32f3xx_ll_dac.h
  • DAC_SWTR_CH2 : stm32f3xx_ll_dac.h
  • DAC_SWTR_CHX_MASK : stm32f3xx_ll_dac.h
  • DAC_TRIANGLEAMPLITUDE_1 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_1023 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_127 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_15 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_2047 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_255 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_3 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_31 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_4095 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_511 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_63 : stm32f3xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_7 : stm32f3xx_hal_dac.h
  • DAC_TRIGGER_EXT_IT9 : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_NONE : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_SOFTWARE : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_T18_TRGO : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_T2_TRGO : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_T3_TRGO : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_T4_TRGO : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_T5_TRGO : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_T6_TRGO : stm32f3xx_hal_dac_ex.h
  • DAC_TRIGGER_T7_TRGO : stm32f3xx_hal_dac_ex.h
  • DATA_CACHE_ENABLE : stm32f3xx_hal_conf.h
  • DEFAULT_CRC32_POLY : stm32f3xx_hal_crc.h
  • DEFAULT_CRC_INITVALUE : stm32f3xx_hal_crc.h
  • DEFAULT_INIT_VALUE_DISABLE : stm32f3xx_hal_crc.h
  • DEFAULT_INIT_VALUE_ENABLE : stm32f3xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_DISABLE : stm32f3xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_ENABLE : stm32f3xx_hal_crc.h
  • DEP0CTL_MPS_16 : stm32f3xx_hal_pcd.h
  • DEP0CTL_MPS_32 : stm32f3xx_hal_pcd.h
  • DEP0CTL_MPS_64 : stm32f3xx_hal_pcd.h
  • DEP0CTL_MPS_8 : stm32f3xx_hal_pcd.h
  • DMA_CIRCULAR : stm32f3xx_hal_dma.h
  • DMA_FLAG_GL1 : stm32f3xx_hal_dma.h
  • DMA_FLAG_GL2 : stm32f3xx_hal_dma.h
  • DMA_FLAG_GL3 : stm32f3xx_hal_dma.h
  • DMA_FLAG_GL4 : stm32f3xx_hal_dma.h
  • DMA_FLAG_GL5 : stm32f3xx_hal_dma.h
  • DMA_FLAG_GL6 : stm32f3xx_hal_dma.h
  • DMA_FLAG_GL7 : stm32f3xx_hal_dma.h
  • DMA_FLAG_HT1 : stm32f3xx_hal_dma.h
  • DMA_FLAG_HT2 : stm32f3xx_hal_dma.h
  • DMA_FLAG_HT3 : stm32f3xx_hal_dma.h
  • DMA_FLAG_HT4 : stm32f3xx_hal_dma.h
  • DMA_FLAG_HT5 : stm32f3xx_hal_dma.h
  • DMA_FLAG_HT6 : stm32f3xx_hal_dma.h
  • DMA_FLAG_HT7 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TC1 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TC2 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TC3 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TC4 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TC5 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TC6 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TC7 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TE1 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TE2 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TE3 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TE4 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TE5 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TE6 : stm32f3xx_hal_dma.h
  • DMA_FLAG_TE7 : stm32f3xx_hal_dma.h
  • DMA_IT_HT : stm32f3xx_hal_dma.h
  • DMA_IT_TC : stm32f3xx_hal_dma.h
  • DMA_IT_TE : stm32f3xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32f3xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32f3xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32f3xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32f3xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32f3xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32f3xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32f3xx_hal_dma.h
  • DMA_NORMAL : stm32f3xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32f3xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32f3xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32f3xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32f3xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32f3xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32f3xx_hal_dma.h
  • DMA_PRIORITY_HIGH : stm32f3xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32f3xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32f3xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32f3xx_hal_dma.h
  • DT_DELAY_1 : stm32f3xx_ll_tim.h
  • DT_DELAY_2 : stm32f3xx_ll_tim.h
  • DT_DELAY_3 : stm32f3xx_ll_tim.h
  • DT_DELAY_4 : stm32f3xx_ll_tim.h
  • DT_RANGE_1 : stm32f3xx_ll_tim.h
  • DT_RANGE_2 : stm32f3xx_ll_tim.h
  • DT_RANGE_3 : stm32f3xx_ll_tim.h
  • DT_RANGE_4 : stm32f3xx_ll_tim.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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- e -

  • EXTERNAL_CLOCK_VALUE : stm32f3xx_hal_conf.h
  • EXTI_MODE : stm32f3xx_hal_gpio.c
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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- f -

  • FALLING_EDGE : stm32f3xx_hal_gpio.c
  • FLASH_FLAG_BSY : stm32f3xx_hal_flash.h
  • FLASH_FLAG_EOP : stm32f3xx_hal_flash.h
  • FLASH_FLAG_PGERR : stm32f3xx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32f3xx_hal_flash.h
  • FLASH_IT_EOP : stm32f3xx_hal_flash.h
  • FLASH_IT_ERR : stm32f3xx_hal_flash.h
  • FLASH_LATENCY_0 : stm32f3xx_hal_flash.h
  • FLASH_LATENCY_1 : stm32f3xx_hal_flash.h
  • FLASH_LATENCY_2 : stm32f3xx_hal_flash.h
  • FLASH_PAGE_SIZE : stm32f3xx_hal_flash_ex.h
  • FLASH_POSITION_IWDGSW_BIT : stm32f3xx_hal_flash_ex.c
  • FLASH_POSITION_OB_USERDATA0_BIT : stm32f3xx_hal_flash_ex.c
  • FLASH_POSITION_OB_USERDATA1_BIT : stm32f3xx_hal_flash_ex.c
  • FLASH_SIZE_DATA_REGISTER : stm32f3xx_hal_flash_ex.h
  • FLASH_TIMEOUT_VALUE : stm32f3xx_hal_flash.h
  • FLASH_TYPEERASE_MASSERASE : stm32f3xx_hal_flash_ex.h
  • FLASH_TYPEERASE_PAGES : stm32f3xx_hal_flash_ex.h
  • FLASH_TYPEPROGRAM_DOUBLEWORD : stm32f3xx_hal_flash.h
  • FLASH_TYPEPROGRAM_HALFWORD : stm32f3xx_hal_flash.h
  • FLASH_TYPEPROGRAM_WORD : stm32f3xx_hal_flash.h
  • FLASHSIZE_BASE_ADDRESS : stm32f3xx_ll_utils.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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- g -

  • GPIO_AF0_MCO : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF0_RTC_50Hz : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF0_SWJ : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF0_TAMPER : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF0_TRACE : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF10_TIM12 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF10_TIM17 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF10_TIM2 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF10_TIM3 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF10_TIM4 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF11_TIM19 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF14_USB : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF15_EVENTOUT : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF1_EVENTOUT : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF1_TIM15 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF1_TIM16 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF1_TIM17 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF1_TIM2 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF2_TIM13 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF2_TIM14 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF2_TIM15 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF2_TIM19 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF2_TIM3 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF2_TIM4 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF2_TIM5 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF3_TSC : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF4_I2C1 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF4_I2C2 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF5_IR : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF6_CEC : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF6_IR : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF6_SPI1 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF6_SPI3 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF7_CAN : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF7_CEC : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF7_USART1 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF7_USART2 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF7_USART3 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF8_COMP1 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF8_COMP2 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF9_CAN : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF9_TIM12 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF9_TIM13 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF9_TIM14 : stm32f3xx_hal_gpio_ex.h
  • GPIO_AF9_TIM15 : stm32f3xx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32f3xx_hal_gpio_ex.h
  • GPIO_MODE : stm32f3xx_hal_gpio.c
  • GPIO_MODE_AF_OD : stm32f3xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32f3xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32f3xx_hal_gpio.h
  • GPIO_MODE_EVT : stm32f3xx_hal_gpio.c
  • GPIO_MODE_EVT_FALLING : stm32f3xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32f3xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32f3xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32f3xx_hal_gpio.h
  • GPIO_MODE_IT : stm32f3xx_hal_gpio.c
  • GPIO_MODE_IT_FALLING : stm32f3xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32f3xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32f3xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32f3xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32f3xx_hal_gpio.h
  • GPIO_NOPULL : stm32f3xx_hal_gpio.h
  • GPIO_NUMBER : stm32f3xx_hal_gpio.c
  • GPIO_OUTPUT_TYPE : stm32f3xx_hal_gpio.c
  • GPIO_PIN_0 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_1 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_10 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_11 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_12 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_13 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_14 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_15 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_2 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_3 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_4 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_5 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_6 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_7 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_8 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_9 : stm32f3xx_hal_gpio.h
  • GPIO_PIN_All : stm32f3xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32f3xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32f3xx_hal_gpio.h
  • GPIO_PULLUP : stm32f3xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32f3xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32f3xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32f3xx_hal_gpio.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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- h -

  • HAL_ADC_ERROR_DMA : stm32f3xx_hal_adc_ex.h
  • HAL_ADC_ERROR_INTERNAL : stm32f3xx_hal_adc_ex.h
  • HAL_ADC_ERROR_JQOVF : stm32f3xx_hal_adc_ex.h
  • HAL_ADC_ERROR_NONE : stm32f3xx_hal_adc_ex.h
  • HAL_ADC_ERROR_OVR : stm32f3xx_hal_adc_ex.h
  • HAL_ADC_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_ADC_STATE_AWD1 : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_INJ_JQOVF : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOSMP : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32f3xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32f3xx_hal_adc.h
  • HAL_CAN_ERROR_ACK : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_BD : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_BOF : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_BR : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_CRC : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_EPV : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_EWG : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_FOR : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_FOV0 : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_FOV1 : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_NONE : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_STF : stm32f3xx_hal_can.h
  • HAL_CAN_ERROR_TXFAIL : stm32f3xx_hal_can.h
  • HAL_CAN_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_CEC_ERROR_ARBLST : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_BRE : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_LBPE : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_NONE : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_RXACKE : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_RXOVR : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_SBPE : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_TXACKE : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_TXERR : stm32f3xx_hal_cec.h
  • HAL_CEC_ERROR_TXUDR : stm32f3xx_hal_cec.h
  • HAL_CEC_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_COMP_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_CORTEX_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_CRC_Input_Data_Reverse : stm32f3xx_hal_crc.h
  • HAL_CRC_LENGTH_16B : stm32f3xx_hal_crc.h
  • HAL_CRC_LENGTH_32B : stm32f3xx_hal_crc.h
  • HAL_CRC_LENGTH_7B : stm32f3xx_hal_crc.h
  • HAL_CRC_LENGTH_8B : stm32f3xx_hal_crc.h
  • HAL_CRC_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_CRC_Output_Data_Reverse : stm32f3xx_hal_crc.h
  • HAL_DAC_ERROR_DMA : stm32f3xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH1 : stm32f3xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH2 : stm32f3xx_hal_dac.h
  • HAL_DAC_ERROR_NONE : stm32f3xx_hal_dac.h
  • HAL_DAC_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_DMA_ERROR_NO_XFER : stm32f3xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32f3xx_hal_dma.h
  • HAL_DMA_ERROR_NOT_SUPPORTED : stm32f3xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32f3xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32f3xx_hal_dma.h
  • HAL_DMA_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_FLASH_ERROR_NONE : stm32f3xx_hal_flash.h
  • HAL_FLASH_ERROR_PROG : stm32f3xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32f3xx_hal_flash.h
  • HAL_FLASH_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_GPIO_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_HRTIM_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_I2C_ERROR_AF : stm32f3xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32f3xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32f3xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32f3xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32f3xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32f3xx_hal_i2c.h
  • HAL_I2C_ERROR_SIZE : stm32f3xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32f3xx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_I2S_ERROR_DMA : stm32f3xx_hal_i2s.h
  • HAL_I2S_ERROR_NONE : stm32f3xx_hal_i2s.h
  • HAL_I2S_ERROR_OVR : stm32f3xx_hal_i2s.h
  • HAL_I2S_ERROR_TIMEOUT : stm32f3xx_hal_i2s.h
  • HAL_I2S_ERROR_UDR : stm32f3xx_hal_i2s.h
  • HAL_I2S_ERROR_UNKNOW : stm32f3xx_hal_i2s.h
  • HAL_I2S_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_IRDA_ERROR_BUSY : stm32f3xx_hal_irda.h
  • HAL_IRDA_ERROR_DMA : stm32f3xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32f3xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32f3xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32f3xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32f3xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32f3xx_hal_irda.h
  • HAL_IRDA_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32f3xx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_NAND_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_NOR_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_OPAMP_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_PCCARD_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_PCD_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_PWR_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_RCC_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_REMAPDMA_ADC24_DMA2_CH34 : stm32f3xx_hal.h
  • HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 : stm32f3xx_hal.h
  • HAL_REMAPDMA_TIM16_DMA1_CH6 : stm32f3xx_hal.h
  • HAL_REMAPDMA_TIM17_DMA1_CH7 : stm32f3xx_hal.h
  • HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 : stm32f3xx_hal.h
  • HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 : stm32f3xx_hal.h
  • HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 : stm32f3xx_hal.h
  • HAL_REMAPTRIGGER_DAC1_TRIG : stm32f3xx_hal.h
  • HAL_REMAPTRIGGER_TIM1_ITR3 : stm32f3xx_hal.h
  • HAL_RTC_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_SDADC_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_SMARTCARD_ERROR_DMA : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_RTO : stm32f3xx_hal_smartcard.h
  • HAL_SMARTCARD_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_SMBUS_ERROR_ACKF : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ALERT : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ARLO : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BERR : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BUSTIMEOUT : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ERROR_HALTIMEOUT : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ERROR_NONE : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ERROR_OVR : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_ERROR_PECERR : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_SMBUS_STATE_BUSY : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_ERROR : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_LISTEN : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_RX : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_TX : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_READY : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_RESET : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_RX : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_TX : stm32f3xx_hal_smbus.h
  • HAL_SMBUS_STATE_TIMEOUT : stm32f3xx_hal_smbus.h
  • HAL_SPI_ERROR_ABORT : stm32f3xx_hal_spi.h
  • HAL_SPI_ERROR_CRC : stm32f3xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32f3xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32f3xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32f3xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32f3xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32f3xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32f3xx_hal_spi.h
  • HAL_SPI_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_SRAM_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_SYSCFG_IT_FPU_DZC : stm32f3xx_hal.h
  • HAL_SYSCFG_IT_FPU_IDC : stm32f3xx_hal.h
  • HAL_SYSCFG_IT_FPU_IOC : stm32f3xx_hal.h
  • HAL_SYSCFG_IT_FPU_IXC : stm32f3xx_hal.h
  • HAL_SYSCFG_IT_FPU_OFC : stm32f3xx_hal.h
  • HAL_SYSCFG_IT_FPU_UFC : stm32f3xx_hal.h
  • HAL_TIM_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_TIMEOUT_ADDR : stm32f3xx_hal_smbus.c
  • HAL_TIMEOUT_BUSY : stm32f3xx_hal_smbus.c
  • HAL_TIMEOUT_DIR : stm32f3xx_hal_smbus.c
  • HAL_TIMEOUT_RXNE : stm32f3xx_hal_smbus.c
  • HAL_TIMEOUT_STOPF : stm32f3xx_hal_smbus.c
  • HAL_TIMEOUT_TC : stm32f3xx_hal_smbus.c
  • HAL_TIMEOUT_TCR : stm32f3xx_hal_smbus.c
  • HAL_TIMEOUT_TXIS : stm32f3xx_hal_smbus.c
  • HAL_TSC_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_UART_ERROR_BUSY : stm32f3xx_hal_uart.h
  • HAL_UART_ERROR_DMA : stm32f3xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32f3xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32f3xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32f3xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32f3xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32f3xx_hal_uart.h
  • HAL_UART_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_UART_TIMEOUT_VALUE : stm32f3xx_hal_uart.h
  • HAL_USART_ERROR_DMA : stm32f3xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32f3xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32f3xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32f3xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32f3xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32f3xx_hal_usart.h
  • HAL_USART_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HAL_WWDG_MODULE_ENABLED : stm32f3xx_hal_conf.h
  • HSE_STARTUP_TIMEOUT : stm32f3xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32f3xx_hal_rcc.h
  • HSE_VALUE : stm32f3xx_ll_rcc.h , stm32f3xx_hal_conf.h
  • HSI_STARTUP_TIMEOUT : stm32f3xx_hal_conf.h
  • HSI_TIMEOUT_VALUE : stm32f3xx_hal_rcc.h
  • HSI_VALUE : stm32f3xx_hal_conf.h , stm32f3xx_ll_rcc.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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- i -

  • I2C_ADDRESSINGMODE_10BIT : stm32f3xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32f3xx_hal_i2c.h
  • I2C_ANALOGFILTER_DISABLE : stm32f3xx_hal_i2c_ex.h
  • I2C_ANALOGFILTER_ENABLE : stm32f3xx_hal_i2c_ex.h
  • I2C_AUTOEND_MODE : stm32f3xx_hal_i2c.h
  • I2C_DIRECTION_RECEIVE : stm32f3xx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32f3xx_hal_i2c.h
  • I2C_DUALADDRESS_DISABLE : stm32f3xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32f3xx_hal_i2c.h
  • I2C_FASTMODEPLUS_I2C1 : stm32f3xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C2 : stm32f3xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C3 : stm32f3xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB6 : stm32f3xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB7 : stm32f3xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB8 : stm32f3xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB9 : stm32f3xx_hal_i2c_ex.h
  • I2C_FIRST_AND_LAST_FRAME : stm32f3xx_hal_i2c.h
  • I2C_FIRST_AND_NEXT_FRAME : stm32f3xx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32f3xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32f3xx_hal_i2c.h
  • I2C_FLAG_AF : stm32f3xx_hal_i2c.h
  • I2C_FLAG_ALERT : stm32f3xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32f3xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32f3xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32f3xx_hal_i2c.h
  • I2C_FLAG_DIR : stm32f3xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32f3xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32f3xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32f3xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32f3xx_hal_i2c.h
  • I2C_FLAG_TC : stm32f3xx_hal_i2c.h
  • I2C_FLAG_TCR : stm32f3xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32f3xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32f3xx_hal_i2c.h
  • I2C_FLAG_TXIS : stm32f3xx_hal_i2c.h
  • I2C_FMP_NOT_SUPPORTED : stm32f3xx_hal_i2c_ex.h
  • I2C_GENERALCALL_DISABLE : stm32f3xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32f3xx_hal_i2c.h
  • I2C_GENERATE_START : stm32f3xx_hal_i2c.h
  • I2C_GENERATE_START_READ : stm32f3xx_hal_i2c.h
  • I2C_GENERATE_START_WRITE : stm32f3xx_hal_i2c.h
  • I2C_GENERATE_STOP : stm32f3xx_hal_i2c.h
  • I2C_GET_ADDR_MATCH : stm32f3xx_hal_i2c.h
  • I2C_GET_DIR : stm32f3xx_hal_i2c.h
  • I2C_GET_DMA_REMAIN_DATA : stm32f3xx_hal_i2c.c
  • I2C_GET_OWN_ADDRESS1 : stm32f3xx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS2 : stm32f3xx_hal_i2c.h
  • I2C_GET_STOP_MODE : stm32f3xx_hal_i2c.h
  • I2C_IT_ADDRI : stm32f3xx_hal_i2c.h
  • I2C_IT_ERRI : stm32f3xx_hal_i2c.h
  • I2C_IT_NACKI : stm32f3xx_hal_i2c.h
  • I2C_IT_RXI : stm32f3xx_hal_i2c.h
  • I2C_IT_STOPI : stm32f3xx_hal_i2c.h
  • I2C_IT_TCI : stm32f3xx_hal_i2c.h
  • I2C_IT_TXI : stm32f3xx_hal_i2c.h
  • I2C_LAST_FRAME : stm32f3xx_hal_i2c.h
  • I2C_MEM_ADD_LSB : stm32f3xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32f3xx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32f3xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32f3xx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32f3xx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32f3xx_hal_i2c.c
  • I2C_NO_STARTSTOP : stm32f3xx_hal_i2c.h
  • I2C_NOSTRETCH_DISABLE : stm32f3xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32f3xx_hal_i2c.h
  • I2C_OA2_MASK01 : stm32f3xx_hal_i2c.h
  • I2C_OA2_MASK02 : stm32f3xx_hal_i2c.h
  • I2C_OA2_MASK03 : stm32f3xx_hal_i2c.h
  • I2C_OA2_MASK04 : stm32f3xx_hal_i2c.h
  • I2C_OA2_MASK05 : stm32f3xx_hal_i2c.h
  • I2C_OA2_MASK06 : stm32f3xx_hal_i2c.h
  • I2C_OA2_MASK07 : stm32f3xx_hal_i2c.h
  • I2C_OA2_NOMASK : stm32f3xx_hal_i2c.h
  • I2C_RELOAD_MODE : stm32f3xx_hal_i2c.h
  • I2C_RESET_CR2 : stm32f3xx_hal_i2c.h
  • I2C_SOFTEND_MODE : stm32f3xx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32f3xx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32f3xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_RX : stm32f3xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_TX : stm32f3xx_hal_i2c.c
  • I2C_STATE_MSK : stm32f3xx_hal_i2c.c
  • I2C_STATE_NONE : stm32f3xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32f3xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_ADDR : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_DIR : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_RXNE : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_STOPF : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_TC : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_TCR : stm32f3xx_hal_i2c.c
  • I2C_TIMEOUT_TXIS : stm32f3xx_hal_i2c.c
  • I2C_XFER_CPLT_IT : stm32f3xx_hal_i2c.c
  • I2C_XFER_ERROR_IT : stm32f3xx_hal_i2c.c
  • I2C_XFER_LISTEN_IT : stm32f3xx_hal_i2c.c
  • I2C_XFER_RELOAD_IT : stm32f3xx_hal_i2c.c
  • I2C_XFER_RX_IT : stm32f3xx_hal_i2c.c
  • I2C_XFER_TX_IT : stm32f3xx_hal_i2c.c
  • I2S_AUDIOFREQ_11K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_16K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_192K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_22K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_32K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_44K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_48K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_8K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_96K : stm32f3xx_hal_i2s.h
  • I2S_AUDIOFREQ_DEFAULT : stm32f3xx_hal_i2s.h
  • I2S_CLOCK_EXTERNAL : stm32f3xx_hal_i2s.h
  • I2S_CLOCK_SYSCLK : stm32f3xx_hal_i2s.h
  • I2S_CPOL_HIGH : stm32f3xx_hal_i2s.h
  • I2S_CPOL_LOW : stm32f3xx_hal_i2s.h
  • I2S_DATAFORMAT_16B : stm32f3xx_hal_i2s.h
  • I2S_DATAFORMAT_16B_EXTENDED : stm32f3xx_hal_i2s.h
  • I2S_DATAFORMAT_24B : stm32f3xx_hal_i2s.h
  • I2S_DATAFORMAT_32B : stm32f3xx_hal_i2s.h
  • I2S_FLAG_BSY : stm32f3xx_hal_i2s.h
  • I2S_FLAG_CHSIDE : stm32f3xx_hal_i2s.h
  • I2S_FLAG_FRE : stm32f3xx_hal_i2s.h
  • I2S_FLAG_OVR : stm32f3xx_hal_i2s.h
  • I2S_FLAG_RXNE : stm32f3xx_hal_i2s.h
  • I2S_FLAG_TXE : stm32f3xx_hal_i2s.h
  • I2S_FLAG_UDR : stm32f3xx_hal_i2s.h
  • I2S_FULLDUPLEXMODE_DISABLE : stm32f3xx_hal_i2s.h
  • I2S_FULLDUPLEXMODE_ENABLE : stm32f3xx_hal_i2s.h
  • I2S_I2SCFGR_CLEAR_MASK : stm32f3xx_ll_spi.c
  • I2S_I2SPR_CLEAR_MASK : stm32f3xx_ll_spi.c
  • I2S_IT_ERR : stm32f3xx_hal_i2s.h
  • I2S_IT_RXNE : stm32f3xx_hal_i2s.h
  • I2S_IT_TXE : stm32f3xx_hal_i2s.h
  • I2S_MCLKOUTPUT_DISABLE : stm32f3xx_hal_i2s.h
  • I2S_MCLKOUTPUT_ENABLE : stm32f3xx_hal_i2s.h
  • I2S_MODE_MASTER_RX : stm32f3xx_hal_i2s.h
  • I2S_MODE_MASTER_TX : stm32f3xx_hal_i2s.h
  • I2S_MODE_SLAVE_RX : stm32f3xx_hal_i2s.h
  • I2S_MODE_SLAVE_TX : stm32f3xx_hal_i2s.h
  • I2S_STANDARD_LSB : stm32f3xx_hal_i2s.h
  • I2S_STANDARD_MSB : stm32f3xx_hal_i2s.h
  • I2S_STANDARD_PCM_LONG : stm32f3xx_hal_i2s.h
  • I2S_STANDARD_PCM_SHORT : stm32f3xx_hal_i2s.h
  • I2S_STANDARD_PHILIPS : stm32f3xx_hal_i2s.h
  • IDCODE_DEVID_MASK : stm32f3xx_hal.c
  • INSTRUCTION_CACHE_ENABLE : stm32f3xx_hal_conf.h
  • IRDA_AUTOBAUD_REQUEST : stm32f3xx_hal_irda.h
  • IRDA_CLEAR_FEF : stm32f3xx_hal_irda.h
  • IRDA_CLEAR_IDLEF : stm32f3xx_hal_irda.h
  • IRDA_CLEAR_NEF : stm32f3xx_hal_irda.h
  • IRDA_CLEAR_OREF : stm32f3xx_hal_irda.h
  • IRDA_CLEAR_PEF : stm32f3xx_hal_irda.h
  • IRDA_CLEAR_TCF : stm32f3xx_hal_irda.h
  • IRDA_CR1_FIELDS : stm32f3xx_hal_irda.c
  • IRDA_DMA_RX_DISABLE : stm32f3xx_hal_irda.h
  • IRDA_DMA_RX_ENABLE : stm32f3xx_hal_irda.h
  • IRDA_DMA_TX_DISABLE : stm32f3xx_hal_irda.h
  • IRDA_DMA_TX_ENABLE : stm32f3xx_hal_irda.h
  • IRDA_FLAG_ABRE : stm32f3xx_hal_irda.h
  • IRDA_FLAG_ABRF : stm32f3xx_hal_irda.h
  • IRDA_FLAG_BUSY : stm32f3xx_hal_irda.h
  • IRDA_FLAG_FE : stm32f3xx_hal_irda.h
  • IRDA_FLAG_NE : stm32f3xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32f3xx_hal_irda.h
  • IRDA_FLAG_PE : stm32f3xx_hal_irda.h
  • IRDA_FLAG_REACK : stm32f3xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32f3xx_hal_irda.h
  • IRDA_FLAG_TC : stm32f3xx_hal_irda.h
  • IRDA_FLAG_TEACK : stm32f3xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32f3xx_hal_irda.h
  • IRDA_GETCLOCKSOURCE : stm32f3xx_hal_irda_ex.h
  • IRDA_IT_ERR : stm32f3xx_hal_irda.h
  • IRDA_IT_FE : stm32f3xx_hal_irda.h
  • IRDA_IT_IDLE : stm32f3xx_hal_irda.h
  • IRDA_IT_MASK : stm32f3xx_hal_irda.h
  • IRDA_IT_NE : stm32f3xx_hal_irda.h
  • IRDA_IT_ORE : stm32f3xx_hal_irda.h
  • IRDA_IT_PE : stm32f3xx_hal_irda.h
  • IRDA_IT_RXNE : stm32f3xx_hal_irda.h
  • IRDA_IT_TC : stm32f3xx_hal_irda.h
  • IRDA_IT_TXE : stm32f3xx_hal_irda.h
  • IRDA_MASK_COMPUTATION : stm32f3xx_hal_irda_ex.h
  • IRDA_MODE_DISABLE : stm32f3xx_hal_irda.h
  • IRDA_MODE_ENABLE : stm32f3xx_hal_irda.h
  • IRDA_MODE_RX : stm32f3xx_hal_irda.h
  • IRDA_MODE_TX : stm32f3xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32f3xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_DISABLE : stm32f3xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_ENABLE : stm32f3xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32f3xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32f3xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32f3xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32f3xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32f3xx_hal_irda.h
  • IRDA_RXDATA_FLUSH_REQUEST : stm32f3xx_hal_irda.h
  • IRDA_STATE_DISABLE : stm32f3xx_hal_irda.h
  • IRDA_STATE_ENABLE : stm32f3xx_hal_irda.h
  • IRDA_TEACK_REACK_TIMEOUT : stm32f3xx_hal_irda.c
  • IRDA_TXDATA_FLUSH_REQUEST : stm32f3xx_hal_irda.h
  • IRDA_WORDLENGTH_8B : stm32f3xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_9B : stm32f3xx_hal_irda_ex.h
  • IS_ADC_ANALOG_WATCHDOG_MODE : stm32f3xx_hal_adc_ex.h
  • IS_ADC_CHANNEL : stm32f3xx_hal_adc_ex.h
  • IS_ADC_CONVERSION_GROUP : stm32f3xx_hal_adc_ex.h
  • IS_ADC_DATA_ALIGN : stm32f3xx_hal_adc_ex.h
  • IS_ADC_EVENT_TYPE : stm32f3xx_hal_adc_ex.h
  • IS_ADC_EXTTRIG : stm32f3xx_hal_adc_ex.h
  • IS_ADC_EXTTRIG_EDGE : stm32f3xx_hal_adc_ex.h
  • IS_ADC_EXTTRIGINJEC : stm32f3xx_hal_adc_ex.h
  • IS_ADC_EXTTRIGINJEC_EDGE : stm32f3xx_hal_adc_ex.h
  • IS_ADC_INJECTED_NB_CONV : stm32f3xx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32f3xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32f3xx_hal_adc_ex.h
  • IS_ADC_REGULAR_DISCONT_NUMBER : stm32f3xx_hal_adc_ex.h
  • IS_ADC_REGULAR_NB_CONV : stm32f3xx_hal_adc_ex.h
  • IS_ADC_REGULAR_RANK : stm32f3xx_hal_adc_ex.h
  • IS_ADC_SAMPLE_TIME : stm32f3xx_hal_adc_ex.h
  • IS_ADC_SCAN_MODE : stm32f3xx_hal_adc_ex.h
  • IS_CAN_BANKNUMBER : stm32f3xx_hal_can.h
  • IS_CAN_BS1 : stm32f3xx_hal_can.h
  • IS_CAN_BS2 : stm32f3xx_hal_can.h
  • IS_CAN_CLEAR_IT : stm32f3xx_hal_can.h
  • IS_CAN_DLC : stm32f3xx_hal_can.h
  • IS_CAN_EXTID : stm32f3xx_hal_can.h
  • IS_CAN_FIFO : stm32f3xx_hal_can.h
  • IS_CAN_FILTER_FIFO : stm32f3xx_hal_can.h
  • IS_CAN_FILTER_MODE : stm32f3xx_hal_can.h
  • IS_CAN_FILTER_NUMBER : stm32f3xx_hal_can.h
  • IS_CAN_FILTER_SCALE : stm32f3xx_hal_can.h
  • IS_CAN_IDTYPE : stm32f3xx_hal_can.h
  • IS_CAN_IT : stm32f3xx_hal_can.h
  • IS_CAN_MODE : stm32f3xx_hal_can.h
  • IS_CAN_PRESCALER : stm32f3xx_hal_can.h
  • IS_CAN_RTR : stm32f3xx_hal_can.h
  • IS_CAN_SJW : stm32f3xx_hal_can.h
  • IS_CAN_STDID : stm32f3xx_hal_can.h
  • IS_CAN_TRANSMITMAILBOX : stm32f3xx_hal_can.h
  • IS_CEC_ADDRESS : stm32f3xx_hal_cec.h
  • IS_CEC_BREERRORBITGEN : stm32f3xx_hal_cec.h
  • IS_CEC_BRERXSTOP : stm32f3xx_hal_cec.h
  • IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32f3xx_hal_cec.h
  • IS_CEC_LBPEERRORBITGEN : stm32f3xx_hal_cec.h
  • IS_CEC_LISTENING_MODE : stm32f3xx_hal_cec.h
  • IS_CEC_MSGSIZE : stm32f3xx_hal_cec.h
  • IS_CEC_OWN_ADDRESS : stm32f3xx_hal_cec.h
  • IS_CEC_SFTOP : stm32f3xx_hal_cec.h
  • IS_CEC_SIGNALFREETIME : stm32f3xx_hal_cec.h
  • IS_CEC_TOLERANCE : stm32f3xx_hal_cec.h
  • IS_COMP_BLANKINGSRCE : stm32f3xx_hal_comp_ex.h
  • IS_COMP_BLANKINGSRCE_INSTANCE : stm32f3xx_hal_comp_ex.h
  • IS_COMP_HYSTERESIS : stm32f3xx_hal_comp_ex.h
  • IS_COMP_INVERTINGINPUT : stm32f3xx_hal_comp_ex.h
  • IS_COMP_MODE : stm32f3xx_hal_comp_ex.h
  • IS_COMP_NONINVERTINGINPUT : stm32f3xx_hal_comp_ex.h
  • IS_COMP_NONINVERTINGINPUT_INSTANCE : stm32f3xx_hal_comp_ex.h
  • IS_COMP_OUTPUT : stm32f3xx_hal_comp_ex.h
  • IS_COMP_OUTPUT_INSTANCE : stm32f3xx_hal_comp_ex.h
  • IS_COMP_OUTPUTPOL : stm32f3xx_hal_comp.h
  • IS_COMP_TRIGGERMODE : stm32f3xx_hal_comp.h
  • IS_COMP_WINDOWMODE : stm32f3xx_hal_comp_ex.h
  • IS_CRC_INPUTDATA_FORMAT : stm32f3xx_hal_crc.h
  • IS_CRC_INPUTDATA_INVERSION_MODE : stm32f3xx_hal_crc_ex.h
  • IS_CRC_OUTPUTDATA_INVERSION_MODE : stm32f3xx_hal_crc_ex.h
  • IS_CRC_POL_LENGTH : stm32f3xx_hal_crc.h
  • IS_DAC_ALIGN : stm32f3xx_hal_dac.h
  • IS_DAC_CHANNEL : stm32f3xx_hal_dac_ex.h
  • IS_DAC_DATA : stm32f3xx_hal_dac.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32f3xx_hal_dac.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32f3xx_hal_dac.h
  • IS_DAC_TRIGGER : stm32f3xx_hal_dac_ex.h
  • IS_DEFAULT_INIT_VALUE : stm32f3xx_hal_crc.h
  • IS_DEFAULT_POLYNOMIAL : stm32f3xx_hal_crc.h
  • IS_DMA_BUFFER_SIZE : stm32f3xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32f3xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32f3xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32f3xx_hal_dma.h
  • IS_DMA_MODE : stm32f3xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32f3xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32f3xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32f3xx_hal_dma.h
  • IS_DMA_REMAP : stm32f3xx_hal.h
  • IS_FLASH_LATENCY : stm32f3xx_hal_flash.h
  • IS_FLASH_NB_PAGES : stm32f3xx_hal_flash_ex.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32f3xx_hal_flash_ex.h
  • IS_FLASH_TYPEERASE : stm32f3xx_hal_flash_ex.h
  • IS_FLASH_TYPEPROGRAM : stm32f3xx_hal_flash.h
  • IS_GPIO_AF : stm32f3xx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32f3xx_hal_gpio.h
  • IS_GPIO_PIN : stm32f3xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32f3xx_hal_gpio.h
  • IS_GPIO_PULL : stm32f3xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32f3xx_hal_gpio.h
  • IS_HAL_REMAPTRIGGER : stm32f3xx_hal.h
  • IS_HAL_SYSCFG_INTERRUPT : stm32f3xx_hal.h
  • IS_I2C_ADDRESSING_MODE : stm32f3xx_hal_i2c.h
  • IS_I2C_ANALOG_FILTER : stm32f3xx_hal_i2c_ex.h
  • IS_I2C_DIGITAL_FILTER : stm32f3xx_hal_i2c_ex.h
  • IS_I2C_DUAL_ADDRESS : stm32f3xx_hal_i2c.h
  • IS_I2C_FASTMODEPLUS : stm32f3xx_hal_i2c_ex.h
  • IS_I2C_GENERAL_CALL : stm32f3xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32f3xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32f3xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32f3xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32f3xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2_MASK : stm32f3xx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32f3xx_hal_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32f3xx_hal_i2s.h
  • IS_I2S_CLOCKSOURCE : stm32f3xx_hal_i2s.h
  • IS_I2S_CPOL : stm32f3xx_hal_i2s.h
  • IS_I2S_DATA_FORMAT : stm32f3xx_hal_i2s.h
  • IS_I2S_FULLDUPLEX_MODE : stm32f3xx_hal_i2s.h
  • IS_I2S_MCLK_OUTPUT : stm32f3xx_hal_i2s.h
  • IS_I2S_MODE : stm32f3xx_hal_i2s.h
  • IS_I2S_STANDARD : stm32f3xx_hal_i2s.h
  • IS_IRDA_BAUDRATE : stm32f3xx_hal_irda.h
  • IS_IRDA_DMA_RX : stm32f3xx_hal_irda.h
  • IS_IRDA_DMA_TX : stm32f3xx_hal_irda.h
  • IS_IRDA_MODE : stm32f3xx_hal_irda.h
  • IS_IRDA_ONE_BIT_SAMPLE : stm32f3xx_hal_irda.h
  • IS_IRDA_PARITY : stm32f3xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32f3xx_hal_irda.h
  • IS_IRDA_PRESCALER : stm32f3xx_hal_irda.h
  • IS_IRDA_REQUEST_PARAMETER : stm32f3xx_hal_irda.h
  • IS_IRDA_STATE : stm32f3xx_hal_irda.h
  • IS_IRDA_TX_RX_MODE : stm32f3xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32f3xx_hal_irda_ex.h
  • IS_IWDG_PRESCALER : stm32f3xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32f3xx_hal_iwdg.h
  • IS_IWDG_WINDOW : stm32f3xx_hal_iwdg.h
  • IS_LL_ADC_DATA_ALIGN : stm32f3xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE : stm32f3xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_LENGTH : stm32f3xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_AUTO : stm32f3xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_SOURCE : stm32f3xx_ll_adc.c
  • IS_LL_ADC_REG_CONTINUOUS_MODE : stm32f3xx_ll_adc.c
  • IS_LL_ADC_REG_DMA_TRANSFER : stm32f3xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE : stm32f3xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_LENGTH : stm32f3xx_ll_adc.c
  • IS_LL_ADC_REG_TRIG_SOURCE : stm32f3xx_ll_adc.c
  • IS_LL_ADC_SCAN_SELECTION : stm32f3xx_ll_adc.c
  • IS_LL_ADC_SEQ_SCAN_MODE : stm32f3xx_ll_adc.c
  • IS_LL_COMP_INPUT_HYSTERESIS : stm32f3xx_ll_comp.c
  • IS_LL_COMP_INPUT_MINUS : stm32f3xx_ll_comp.c
  • IS_LL_COMP_INPUT_PLUS : stm32f3xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_POLARITY : stm32f3xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_SELECTION : stm32f3xx_ll_comp.c
  • IS_LL_COMP_POWER_MODE : stm32f3xx_ll_comp.c
  • IS_LL_DAC_CHANNEL : stm32f3xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_BUFFER : stm32f3xx_ll_dac.c
  • IS_LL_DAC_TRIGGER_SOURCE : stm32f3xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_CONFIG : stm32f3xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_MODE : stm32f3xx_ll_dac.c
  • IS_LL_DMA_ALL_CHANNEL_INSTANCE : stm32f3xx_ll_dma.c
  • IS_LL_DMA_DIRECTION : stm32f3xx_ll_dma.c
  • IS_LL_DMA_MEMORYDATASIZE : stm32f3xx_ll_dma.c
  • IS_LL_DMA_MEMORYINCMODE : stm32f3xx_ll_dma.c
  • IS_LL_DMA_MODE : stm32f3xx_ll_dma.c
  • IS_LL_DMA_NBDATA : stm32f3xx_ll_dma.c
  • IS_LL_DMA_PERIPHDATASIZE : stm32f3xx_ll_dma.c
  • IS_LL_DMA_PERIPHINCMODE : stm32f3xx_ll_dma.c
  • IS_LL_DMA_PRIORITY : stm32f3xx_ll_dma.c
  • IS_LL_EXTI_LINE_0_31 : stm32f3xx_ll_exti.c
  • IS_LL_EXTI_MODE : stm32f3xx_ll_exti.c
  • IS_LL_EXTI_TRIGGER : stm32f3xx_ll_exti.c
  • IS_LL_GPIO_ALTERNATE : stm32f3xx_ll_gpio.c
  • IS_LL_GPIO_MODE : stm32f3xx_ll_gpio.c
  • IS_LL_GPIO_OUTPUT_TYPE : stm32f3xx_ll_gpio.c
  • IS_LL_GPIO_PIN : stm32f3xx_ll_gpio.c
  • IS_LL_GPIO_PULL : stm32f3xx_ll_gpio.c
  • IS_LL_GPIO_SPEED : stm32f3xx_ll_gpio.c
  • IS_LL_I2C_ANALOG_FILTER : stm32f3xx_ll_i2c.c
  • IS_LL_I2C_DIGITAL_FILTER : stm32f3xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRESS1 : stm32f3xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRSIZE : stm32f3xx_ll_i2c.c
  • IS_LL_I2C_PERIPHERAL_MODE : stm32f3xx_ll_i2c.c
  • IS_LL_I2C_TYPE_ACKNOWLEDGE : stm32f3xx_ll_i2c.c
  • IS_LL_I2S_AUDIO_FREQ : stm32f3xx_ll_spi.c
  • IS_LL_I2S_CPOL : stm32f3xx_ll_spi.c
  • IS_LL_I2S_DATAFORMAT : stm32f3xx_ll_spi.c
  • IS_LL_I2S_MCLK_OUTPUT : stm32f3xx_ll_spi.c
  • IS_LL_I2S_MODE : stm32f3xx_ll_spi.c
  • IS_LL_I2S_PRESCALER_LINEAR : stm32f3xx_ll_spi.c
  • IS_LL_I2S_PRESCALER_PARITY : stm32f3xx_ll_spi.c
  • IS_LL_I2S_STANDARD : stm32f3xx_ll_spi.c
  • IS_LL_RCC_ADC_CLKSOURCE : stm32f3xx_ll_rcc.c
  • IS_LL_RCC_CEC_CLKSOURCE : stm32f3xx_ll_rcc.c
  • IS_LL_RCC_I2C_CLKSOURCE : stm32f3xx_ll_rcc.c
  • IS_LL_RCC_I2S_CLKSOURCE : stm32f3xx_ll_rcc.c
  • IS_LL_RCC_SDADC_CLKSOURCE : stm32f3xx_ll_rcc.c
  • IS_LL_RCC_USART_CLKSOURCE : stm32f3xx_ll_rcc.c
  • IS_LL_RCC_USB_CLKSOURCE : stm32f3xx_ll_rcc.c
  • IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_ALMA_MASK : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_ALMB_MASK : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_ASYNCH_PREDIV : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_DAY : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_FORMAT : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_HOUR12 : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_HOUR24 : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_HOURFORMAT : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_MINUTES : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_MONTH : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_SECONDS : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_SYNCH_PREDIV : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_TIME_FORMAT : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_WEEKDAY : stm32f3xx_ll_rtc.c
  • IS_LL_RTC_YEAR : stm32f3xx_ll_rtc.c
  • IS_LL_SPI_BAUDRATE : stm32f3xx_ll_spi.c
  • IS_LL_SPI_BITORDER : stm32f3xx_ll_spi.c
  • IS_LL_SPI_CRC_POLYNOMIAL : stm32f3xx_ll_spi.c
  • IS_LL_SPI_CRCCALCULATION : stm32f3xx_ll_spi.c
  • IS_LL_SPI_DATAWIDTH : stm32f3xx_ll_spi.c
  • IS_LL_SPI_MODE : stm32f3xx_ll_spi.c
  • IS_LL_SPI_NSS : stm32f3xx_ll_spi.c
  • IS_LL_SPI_PHASE : stm32f3xx_ll_spi.c
  • IS_LL_SPI_POLARITY : stm32f3xx_ll_spi.c
  • IS_LL_SPI_TRANSFER_DIRECTION : stm32f3xx_ll_spi.c
  • IS_LL_TIM_ACTIVEINPUT : stm32f3xx_ll_tim.c
  • IS_LL_TIM_AUTOMATIC_OUTPUT_STATE : stm32f3xx_ll_tim.c
  • IS_LL_TIM_BREAK_POLARITY : stm32f3xx_ll_tim.c
  • IS_LL_TIM_BREAK_STATE : stm32f3xx_ll_tim.c
  • IS_LL_TIM_CLOCKDIVISION : stm32f3xx_ll_tim.c
  • IS_LL_TIM_COUNTERMODE : stm32f3xx_ll_tim.c
  • IS_LL_TIM_ENCODERMODE : stm32f3xx_ll_tim.c
  • IS_LL_TIM_IC_FILTER : stm32f3xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY : stm32f3xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY_ENCODER : stm32f3xx_ll_tim.c
  • IS_LL_TIM_ICPSC : stm32f3xx_ll_tim.c
  • IS_LL_TIM_LOCK_LEVEL : stm32f3xx_ll_tim.c
  • IS_LL_TIM_OCIDLESTATE : stm32f3xx_ll_tim.c
  • IS_LL_TIM_OCMODE : stm32f3xx_ll_tim.c
  • IS_LL_TIM_OCPOLARITY : stm32f3xx_ll_tim.c
  • IS_LL_TIM_OCSTATE : stm32f3xx_ll_tim.c
  • IS_LL_TIM_OSSI_STATE : stm32f3xx_ll_tim.c
  • IS_LL_TIM_OSSR_STATE : stm32f3xx_ll_tim.c
  • IS_LL_USART_BAUDRATE : stm32f3xx_ll_usart.c
  • IS_LL_USART_BRR_MAX : stm32f3xx_ll_usart.c
  • IS_LL_USART_BRR_MIN : stm32f3xx_ll_usart.c
  • IS_LL_USART_CLOCKOUTPUT : stm32f3xx_ll_usart.c
  • IS_LL_USART_CLOCKPHASE : stm32f3xx_ll_usart.c
  • IS_LL_USART_CLOCKPOLARITY : stm32f3xx_ll_usart.c
  • IS_LL_USART_DATAWIDTH : stm32f3xx_ll_usart.c
  • IS_LL_USART_DIRECTION : stm32f3xx_ll_usart.c
  • IS_LL_USART_HWCONTROL : stm32f3xx_ll_usart.c
  • IS_LL_USART_LASTBITCLKOUTPUT : stm32f3xx_ll_usart.c
  • IS_LL_USART_OVERSAMPLING : stm32f3xx_ll_usart.c
  • IS_LL_USART_PARITY : stm32f3xx_ll_usart.c
  • IS_LL_USART_STOPBITS : stm32f3xx_ll_usart.c
  • IS_LL_UTILS_APB1_DIV : stm32f3xx_ll_utils.c
  • IS_LL_UTILS_APB2_DIV : stm32f3xx_ll_utils.c
  • IS_LL_UTILS_HSE_BYPASS : stm32f3xx_ll_utils.c
  • IS_LL_UTILS_HSE_FREQUENCY : stm32f3xx_ll_utils.c
  • IS_LL_UTILS_PLL_FREQUENCY : stm32f3xx_ll_utils.c
  • IS_LL_UTILS_PLLMUL_VALUE : stm32f3xx_ll_utils.c
  • IS_LL_UTILS_PREDIV_VALUE : stm32f3xx_ll_utils.c
  • IS_LL_UTILS_SYSCLK_DIV : stm32f3xx_ll_utils.c
  • IS_MPU_ACCESS_BUFFERABLE : stm32f3xx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32f3xx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32f3xx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32f3xx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32f3xx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32f3xx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32f3xx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32f3xx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32f3xx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32f3xx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32f3xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32f3xx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32f3xx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32f3xx_hal_cortex.h
  • IS_OB_BOOT1 : stm32f3xx_hal_flash_ex.h
  • IS_OB_DATA_ADDRESS : stm32f3xx_hal_flash_ex.h
  • IS_OB_IWDG_SOURCE : stm32f3xx_hal_flash_ex.h
  • IS_OB_RDP_LEVEL : stm32f3xx_hal_flash_ex.h
  • IS_OB_SDACD_VDD_MONITOR : stm32f3xx_hal_flash_ex.h
  • IS_OB_SRAM_PARITY : stm32f3xx_hal_flash_ex.h
  • IS_OB_STDBY_SOURCE : stm32f3xx_hal_flash_ex.h
  • IS_OB_STOP_SOURCE : stm32f3xx_hal_flash_ex.h
  • IS_OB_VDDA_ANALOG : stm32f3xx_hal_flash_ex.h
  • IS_OB_WRP : stm32f3xx_hal_flash_ex.h
  • IS_OPTIONBYTE : stm32f3xx_hal_flash_ex.h
  • IS_PCD_ALL_INSTANCE : stm32f3xx_hal_pcd.h
  • IS_PWR_PVD_LEVEL : stm32f3xx_hal_pwr_ex.h
  • IS_PWR_PVD_MODE : stm32f3xx_hal_pwr_ex.h
  • IS_PWR_REGULATOR : stm32f3xx_hal_pwr.h
  • IS_PWR_SDADC_ANALOG : stm32f3xx_hal_pwr_ex.h
  • IS_PWR_SLEEP_ENTRY : stm32f3xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32f3xx_hal_pwr.h
  • IS_PWR_WAKEUP_PIN : stm32f3xx_hal_pwr.h
  • IS_RCC_ADC1PCLK2_DIV : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_CALIBRATION_VALUE : stm32f3xx_hal_rcc.h
  • IS_RCC_CECCLKSOURCE : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_CLOCKTYPE : stm32f3xx_hal_rcc.h
  • IS_RCC_HCLK : stm32f3xx_hal_rcc.h
  • IS_RCC_HSE : stm32f3xx_hal_rcc.h
  • IS_RCC_HSE_PREDIV : stm32f3xx_hal_rcc.h
  • IS_RCC_HSI : stm32f3xx_hal_rcc.h
  • IS_RCC_I2C1CLKSOURCE : stm32f3xx_hal_rcc.h
  • IS_RCC_I2C2CLKSOURCE : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32f3xx_hal_rcc.h
  • IS_RCC_LSE_DRIVE : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_LSI : stm32f3xx_hal_rcc.h
  • IS_RCC_MCO : stm32f3xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_MCODIV : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_OSCILLATORTYPE : stm32f3xx_hal_rcc.h
  • IS_RCC_PCLK : stm32f3xx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32f3xx_hal_rcc.h
  • IS_RCC_PLL_DIV : stm32f3xx_hal_rcc.h
  • IS_RCC_PLL_MUL : stm32f3xx_hal_rcc.h
  • IS_RCC_PLLSOURCE : stm32f3xx_hal_rcc.h
  • IS_RCC_RTCCLKSOURCE : stm32f3xx_hal_rcc.h
  • IS_RCC_SDADCSYSCLK_DIV : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_SYSCLKSOURCE : stm32f3xx_hal_rcc.h
  • IS_RCC_SYSCLKSOURCE_STATUS : stm32f3xx_hal_rcc.h
  • IS_RCC_USART1CLKSOURCE : stm32f3xx_hal_rcc_ex.h
  • IS_RCC_USART2CLKSOURCE : stm32f3xx_hal_rcc.h
  • IS_RCC_USART3CLKSOURCE : stm32f3xx_hal_rcc.h
  • IS_RCC_USBCLKSOURCE : stm32f3xx_hal_rcc_ex.h
  • IS_RTC_ALARM : stm32f3xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32f3xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32f3xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32f3xx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32f3xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32f3xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32f3xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32f3xx_hal_rtc.h
  • IS_RTC_BKP : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32f3xx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32f3xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32f3xx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32f3xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32f3xx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32f3xx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32f3xx_hal_rtc.h
  • IS_RTC_MINUTES : stm32f3xx_hal_rtc.h
  • IS_RTC_MONTH : stm32f3xx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_OUTPUT_POL : stm32f3xx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32f3xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32f3xx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32f3xx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32f3xx_hal_rtc.h
  • IS_RTC_TAMPER : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32f3xx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32f3xx_hal_rtc.h
  • IS_RTC_YEAR : stm32f3xx_hal_rtc.h
  • IS_SDADC_CALIB_SEQUENCE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_COMMON_MODE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_CONF_INDEX : stm32f3xx_hal_sdadc.h
  • IS_SDADC_CONTINUOUS_MODE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_EXT_INJEC_TRIG : stm32f3xx_hal_sdadc.h
  • IS_SDADC_EXT_TRIG_EDGE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_FAST_CONV_MODE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_GAIN : stm32f3xx_hal_sdadc.h
  • IS_SDADC_INJECTED_CHANNEL : stm32f3xx_hal_sdadc.h
  • IS_SDADC_INJECTED_DELAY : stm32f3xx_hal_sdadc.h
  • IS_SDADC_INJECTED_TRIGGER : stm32f3xx_hal_sdadc.h
  • IS_SDADC_INPUT_MODE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_LOWPOWER_MODE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_MULTIMODE_TYPE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_OFFSET_VALUE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_REGULAR_CHANNEL : stm32f3xx_hal_sdadc.h
  • IS_SDADC_REGULAR_TRIGGER : stm32f3xx_hal_sdadc.h
  • IS_SDADC_SLOW_CLOCK_MODE : stm32f3xx_hal_sdadc.h
  • IS_SDADC_VREF : stm32f3xx_hal_sdadc.h
  • IS_SMARTCARD_ADVFEATURE_DATAINV : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_DMAONRXERROR : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_INIT : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_MSBFIRST : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_RXINV : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_SWAP : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_TXINV : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_AUTORETRY_COUNT : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_BAUDRATE : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_BLOCKLENGTH : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_LASTBIT : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_NACK : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_ONE_BIT_SAMPLE : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_OVERRUN : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_REQUEST_PARAMETER : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_STOPBITS : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT_VALUE : stm32f3xx_hal_smartcard.h
  • IS_SMARTCARD_WORD_LENGTH : stm32f3xx_hal_smartcard.h
  • IS_SMBUS_ADDRESSING_MODE : stm32f3xx_hal_smbus.h
  • IS_SMBUS_ANALOG_FILTER : stm32f3xx_hal_smbus.h
  • IS_SMBUS_DIGITAL_FILTER : stm32f3xx_hal_smbus.h
  • IS_SMBUS_DUAL_ADDRESS : stm32f3xx_hal_smbus.h
  • IS_SMBUS_GENERAL_CALL : stm32f3xx_hal_smbus.h
  • IS_SMBUS_NO_STRETCH : stm32f3xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS1 : stm32f3xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2 : stm32f3xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2_MASK : stm32f3xx_hal_smbus.h
  • IS_SMBUS_PEC : stm32f3xx_hal_smbus.h
  • IS_SMBUS_PERIPHERAL_MODE : stm32f3xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_MODE : stm32f3xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OPTIONS_REQUEST : stm32f3xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST : stm32f3xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_REQUEST : stm32f3xx_hal_smbus.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32f3xx_hal_spi.h
  • IS_SPI_CPHA : stm32f3xx_hal_spi.h
  • IS_SPI_CPOL : stm32f3xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32f3xx_hal_spi.h
  • IS_SPI_CRC_LENGTH : stm32f3xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32f3xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32f3xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32f3xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32f3xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE : stm32f3xx_hal_spi.h
  • IS_SPI_DMA_HANDLE : stm32f3xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32f3xx_hal_spi.h
  • IS_SPI_MODE : stm32f3xx_hal_spi.h
  • IS_SPI_NSS : stm32f3xx_hal_spi.h
  • IS_SPI_NSSP : stm32f3xx_hal_spi.h
  • IS_SPI_TIMODE : stm32f3xx_hal_spi.h
  • IS_SYSCFG_FASTMODEPLUS : stm32f3xx_hal.h
  • IS_SYSTICK_CLK_SOURCE : stm32f3xx_hal_cortex.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32f3xx_hal_tim.h
  • IS_TIM_AUTORELOAD_PRELOAD : stm32f3xx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32f3xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32f3xx_hal_tim.h
  • IS_TIM_CHANNELS : stm32f3xx_hal_tim_ex.h
  • IS_TIM_CLEARINPUT_FILTER : stm32f3xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32f3xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32f3xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32f3xx_hal_tim_ex.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32f3xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32f3xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32f3xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32f3xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32f3xx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32f3xx_hal_tim_ex.h
  • IS_TIM_COUNTER_MODE : stm32f3xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32f3xx_hal_tim_ex.h
  • IS_TIM_DMA_BASE : stm32f3xx_hal_tim_ex.h
  • IS_TIM_DMA_DATA_LENGTH : stm32f3xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32f3xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32f3xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32f3xx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32f3xx_hal_tim_ex.h
  • IS_TIM_FAST_STATE : stm32f3xx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32f3xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32f3xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32f3xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32f3xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32f3xx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32f3xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32f3xx_hal_tim.h
  • IS_TIM_OC_MODE : stm32f3xx_hal_tim_ex.h
  • IS_TIM_OC_POLARITY : stm32f3xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32f3xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32f3xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32f3xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32f3xx_hal_tim_ex.h
  • IS_TIM_OPM_MODE : stm32f3xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32f3xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32f3xx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32f3xx_hal_tim_ex.h
  • IS_TIM_REMAP : stm32f3xx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32f3xx_hal_tim_ex.h
  • IS_TIM_TI1SELECTION : stm32f3xx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32f3xx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32f3xx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32f3xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32f3xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32f3xx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32f3xx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32f3xx_hal_i2c.h
  • IS_TRANSFER_REQUEST : stm32f3xx_hal_i2c.h
  • IS_TSC_ACQ_MODE : stm32f3xx_hal_tsc.h
  • IS_TSC_CTPH : stm32f3xx_hal_tsc.h
  • IS_TSC_CTPL : stm32f3xx_hal_tsc.h
  • IS_TSC_GROUP_INDEX : stm32f3xx_hal_tsc.h
  • IS_TSC_IODEF : stm32f3xx_hal_tsc.h
  • IS_TSC_IOMODE : stm32f3xx_hal_tsc.h
  • IS_TSC_MCE_IT : stm32f3xx_hal_tsc.h
  • IS_TSC_MCV : stm32f3xx_hal_tsc.h
  • IS_TSC_PG_PRESC : stm32f3xx_hal_tsc.h
  • IS_TSC_SS : stm32f3xx_hal_tsc.h
  • IS_TSC_SS_PRESC : stm32f3xx_hal_tsc.h
  • IS_TSC_SSD : stm32f3xx_hal_tsc.h
  • IS_TSC_SYNC_POL : stm32f3xx_hal_tsc.h
  • IS_UART_ADDRESSLENGTH_DETECT : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATE : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATEMODE : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_DATAINV : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_DMAONRXERROR : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_INIT : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_MSBFIRST : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_RXINV : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_STOPMODE : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_SWAP : stm32f3xx_hal_uart.h
  • IS_UART_ADVFEATURE_TXINV : stm32f3xx_hal_uart.h
  • IS_UART_ASSERTIONTIME : stm32f3xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32f3xx_hal_uart.h
  • IS_UART_DE_POLARITY : stm32f3xx_hal_uart.h
  • IS_UART_DEASSERTIONTIME : stm32f3xx_hal_uart.h
  • IS_UART_DMA_RX : stm32f3xx_hal_uart.h
  • IS_UART_DMA_TX : stm32f3xx_hal_uart.h
  • IS_UART_HALF_DUPLEX : stm32f3xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32f3xx_hal_uart.h
  • IS_UART_LIN : stm32f3xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32f3xx_hal_uart.h
  • IS_UART_MODE : stm32f3xx_hal_uart.h
  • IS_UART_MUTE_MODE : stm32f3xx_hal_uart.h
  • IS_UART_ONE_BIT_SAMPLE : stm32f3xx_hal_uart.h
  • IS_UART_OVERRUN : stm32f3xx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32f3xx_hal_uart.h
  • IS_UART_PARITY : stm32f3xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT : stm32f3xx_hal_uart.h
  • IS_UART_REQUEST_PARAMETER : stm32f3xx_hal_uart.h
  • IS_UART_STATE : stm32f3xx_hal_uart.h
  • IS_UART_STOPBITS : stm32f3xx_hal_uart.h
  • IS_UART_WAKEUP_SELECTION : stm32f3xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32f3xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32f3xx_hal_uart_ex.h
  • IS_USART_BAUDRATE : stm32f3xx_hal_usart.h
  • IS_USART_CLOCK : stm32f3xx_hal_usart.h
  • IS_USART_LASTBIT : stm32f3xx_hal_usart.h
  • IS_USART_MODE : stm32f3xx_hal_usart.h
  • IS_USART_PARITY : stm32f3xx_hal_usart.h
  • IS_USART_PHASE : stm32f3xx_hal_usart.h
  • IS_USART_POLARITY : stm32f3xx_hal_usart.h
  • IS_USART_REQUEST_PARAMETER : stm32f3xx_hal_usart.h
  • IS_USART_STOPBITS : stm32f3xx_hal_usart.h
  • IS_USART_WORD_LENGTH : stm32f3xx_hal_usart_ex.h
  • IS_WRPSTATE : stm32f3xx_hal_flash_ex.h
  • IS_WWDG_COUNTER : stm32f3xx_hal_wwdg.h
  • IS_WWDG_EWI_MODE : stm32f3xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32f3xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32f3xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32f3xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32f3xx_hal_iwdg.h
  • IWDG_KEY_ENABLE : stm32f3xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32f3xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32f3xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32f3xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32f3xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32f3xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32f3xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32f3xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32f3xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32f3xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32f3xx_hal_iwdg.h
  • IWDG_WINDOW_DISABLE : stm32f3xx_hal_iwdg.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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- l -

  • LL_ADC_AWD1 : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG_INJ : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_DISABLE : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_HIGH : stm32f3xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_LOW : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_0 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_1 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_10 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_11 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_12 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_13 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_14 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_15 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_16 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_17 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_2 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_3 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_4 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_5 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_6 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_7 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_8 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_9 : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_TEMPSENSOR : stm32f3xx_ll_adc.h
  • LL_ADC_CHANNEL_VREFINT : stm32f3xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_LEFT : stm32f3xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_RIGHT : stm32f3xx_ll_adc.h
  • LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES : stm32f3xx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_STAB_US : stm32f3xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA : stm32f3xx_ll_adc.h
  • LL_ADC_FLAG_AWD1 : stm32f3xx_ll_adc.h
  • LL_ADC_FLAG_EOS : stm32f3xx_ll_adc.h
  • LL_ADC_FLAG_JEOS : stm32f3xx_ll_adc.h
  • LL_ADC_FLAG_JSTRT : stm32f3xx_ll_adc.h
  • LL_ADC_FLAG_STRT : stm32f3xx_ll_adc.h
  • LL_ADC_GROUP_INJECTED : stm32f3xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR : stm32f3xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR_INJECTED : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_RANK_1 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_RANK_2 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_RANK_3 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_RANK_4 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_1RANK : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_DISABLE : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISING : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM19_CH1 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM19_CH2 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4 : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_INDEPENDENT : stm32f3xx_ll_adc.h
  • LL_ADC_INJ_TRIG_SOFTWARE : stm32f3xx_ll_adc.h
  • LL_ADC_IT_AWD1 : stm32f3xx_ll_adc.h
  • LL_ADC_IT_EOS : stm32f3xx_ll_adc.h
  • LL_ADC_IT_JEOS : stm32f3xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_NONE : stm32f3xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR : stm32f3xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VREFINT : stm32f3xx_ll_adc.h
  • LL_ADC_ReadReg : stm32f3xx_ll_adc.h
  • LL_ADC_REG_CONV_CONTINUOUS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_CONV_SINGLE : stm32f3xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_NONE : stm32f3xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_1 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_10 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_11 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_12 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_13 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_14 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_15 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_16 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_2 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_3 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_4 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_5 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_6 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_7 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_8 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_RANK_9 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_1RANK : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_2RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_3RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_4RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_5RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_6RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_7RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_8RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_DISABLE : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DISABLE : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS : stm32f3xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISING : stm32f3xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM19_CH3 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM19_CH4 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM19_TRGO : stm32f3xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO : stm32f3xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_CH2 : stm32f3xx_ll_adc.h
  • LL_ADC_REG_TRIG_SOFTWARE : stm32f3xx_ll_adc.h
  • LL_ADC_RESOLUTION_12B : stm32f3xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_13CYCLES_5 : stm32f3xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_1CYCLE_5 : stm32f3xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_239CYCLES_5 : stm32f3xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_28CYCLES_5 : stm32f3xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_41CYCLES_5 : stm32f3xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_55CYCLES_5 : stm32f3xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_71CYCLES_5 : stm32f3xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_7CYCLES_5 : stm32f3xx_ll_adc.h
  • LL_ADC_SEQ_SCAN_DISABLE : stm32f3xx_ll_adc.h
  • LL_ADC_SEQ_SCAN_ENABLE : stm32f3xx_ll_adc.h
  • LL_ADC_WriteReg : stm32f3xx_ll_adc.h
  • LL_AHB1_GRP1_PERIPH_ALL : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CRC : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA1 : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA2 : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_FLASH : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_GPIOA : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_GPIOB : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_GPIOC : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_GPIOD : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_GPIOE : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_GPIOF : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_SRAM : stm32f3xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_TSC : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_ALL : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CAN : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CEC : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_DAC1 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_DAC2 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C1 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C2 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_PWR : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI2 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI3 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM12 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM13 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM14 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM18 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM2 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM3 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM4 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM5 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM6 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM7 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART2 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART3 : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USB : stm32f3xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_WWDG : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ADC1 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ALL : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SDADC1 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SDADC2 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SDADC3 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI1 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SYSCFG : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM15 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM16 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM17 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM19 : stm32f3xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART1 : stm32f3xx_ll_bus.h
  • LL_COMP_DELAY_STARTUP_US : stm32f3xx_ll_comp.h
  • LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32f3xx_ll_comp.h
  • LL_COMP_HYSTERESIS_HIGH : stm32f3xx_ll_comp.h
  • LL_COMP_HYSTERESIS_LOW : stm32f3xx_ll_comp.h
  • LL_COMP_HYSTERESIS_MEDIUM : stm32f3xx_ll_comp.h
  • LL_COMP_HYSTERESIS_NONE : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_2VREFINT : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_4VREFINT : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_3_4VREFINT : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH1 : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH2 : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC2_CH1 : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO1 : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO2 : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO3 : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO4 : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_VREFINT : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_DAC1_CH1 : stm32f3xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO1 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_HIGH : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_LOW : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_NONE : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM15_BKIN : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM15_BKIN_COMP1 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM16_BKIN : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM16_BKIN_COMP2 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM2_IC4 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM2_OCCLR : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM3_IC1_COMP1 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM3_IC1_COMP2 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM3_OCCLR_COMP1 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM3_OCCLR_COMP2 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM4_IC1 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM4_IC1_COMP2 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM4_OCCLR : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM4_OCCLR_COMP2 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM5_IC4 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM5_IC4_COMP1 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM5_OCCLR : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUT_TIM5_OCCLR_COMP1 : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_INVERTED : stm32f3xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_NONINVERTED : stm32f3xx_ll_comp.h
  • LL_COMP_POWERMODE_HIGHSPEED : stm32f3xx_ll_comp.h
  • LL_COMP_POWERMODE_LOWPOWER : stm32f3xx_ll_comp.h
  • LL_COMP_POWERMODE_MEDIUMSPEED : stm32f3xx_ll_comp.h
  • LL_COMP_POWERMODE_ULTRALOWPOWER : stm32f3xx_ll_comp.h
  • LL_COMP_ReadReg : stm32f3xx_ll_comp.h
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32f3xx_ll_comp.h
  • LL_COMP_WINDOWMODE_DISABLE : stm32f3xx_ll_comp.h
  • LL_COMP_WriteReg : stm32f3xx_ll_comp.h
  • LL_CRC_DEFAULT_CRC32_POLY : stm32f3xx_ll_crc.h
  • LL_CRC_DEFAULT_CRC_INITVALUE : stm32f3xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_BYTE : stm32f3xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_HALFWORD : stm32f3xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_NONE : stm32f3xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_WORD : stm32f3xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_BIT : stm32f3xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_NONE : stm32f3xx_ll_crc.h
  • LL_CRC_POLYLENGTH_16B : stm32f3xx_ll_crc.h
  • LL_CRC_POLYLENGTH_32B : stm32f3xx_ll_crc.h
  • LL_CRC_POLYLENGTH_7B : stm32f3xx_ll_crc.h
  • LL_CRC_POLYLENGTH_8B : stm32f3xx_ll_crc.h
  • LL_CRC_ReadReg : stm32f3xx_ll_crc.h
  • LL_CRC_WriteReg : stm32f3xx_ll_crc.h
  • LL_DAC_CHANNEL_1 : stm32f3xx_ll_dac.h
  • LL_DAC_CHANNEL_2 : stm32f3xx_ll_dac.h
  • LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US : stm32f3xx_ll_dac.h
  • LL_DAC_DELAY_VOLTAGE_SETTLING_US : stm32f3xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED : stm32f3xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED : stm32f3xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED : stm32f3xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR1 : stm32f3xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR2 : stm32f3xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE1 : stm32f3xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE2 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 : stm32f3xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 : stm32f3xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_DISABLE : stm32f3xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_ENABLE : stm32f3xx_ll_dac.h
  • LL_DAC_ReadReg : stm32f3xx_ll_dac.h
  • LL_DAC_RESOLUTION_12B : stm32f3xx_ll_dac.h
  • LL_DAC_RESOLUTION_8B : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_1 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_1023 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_127 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_15 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_2047 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_255 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_3 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_31 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_4095 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_511 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_63 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_7 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_EXT_EXTI_LINE9 : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM18_TRGO : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM2_TRGO : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM3_TRGO : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM4_TRGO : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM5_TRGO : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM6_TRGO : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM7_TRGO : stm32f3xx_ll_dac.h
  • LL_DAC_TRIG_SOFTWARE : stm32f3xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE : stm32f3xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NONE : stm32f3xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE : stm32f3xx_ll_dac.h
  • LL_DAC_WriteReg : stm32f3xx_ll_dac.h
  • LL_DBGMCU_APB1_GRP1_CAN_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_RTC_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM12_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM13_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM14_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM18_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM5_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM19_STOP : stm32f3xx_ll_system.h
  • LL_DBGMCU_TRACE_ASYNCH : stm32f3xx_ll_system.h
  • LL_DBGMCU_TRACE_NONE : stm32f3xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE1 : stm32f3xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE2 : stm32f3xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE4 : stm32f3xx_ll_system.h
  • LL_DMA_CCR_HTIE : stm32f3xx_ll_dma.h
  • LL_DMA_CCR_TCIE : stm32f3xx_ll_dma.h
  • LL_DMA_CCR_TEIE : stm32f3xx_ll_dma.h
  • LL_DMA_CHANNEL_1 : stm32f3xx_ll_dma.h
  • LL_DMA_CHANNEL_2 : stm32f3xx_ll_dma.h
  • LL_DMA_CHANNEL_3 : stm32f3xx_ll_dma.h
  • LL_DMA_CHANNEL_4 : stm32f3xx_ll_dma.h
  • LL_DMA_CHANNEL_5 : stm32f3xx_ll_dma.h
  • LL_DMA_CHANNEL_6 : stm32f3xx_ll_dma.h
  • LL_DMA_CHANNEL_7 : stm32f3xx_ll_dma.h
  • LL_DMA_CHANNEL_ALL : stm32f3xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY : stm32f3xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH : stm32f3xx_ll_dma.h
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CGIF1 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CGIF2 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CGIF3 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CGIF4 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CGIF5 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CGIF6 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CGIF7 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF1 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF2 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF3 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF4 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF5 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF6 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF7 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF1 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF2 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF3 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF4 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF5 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF6 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF7 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF1 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF2 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF3 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF4 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF5 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF6 : stm32f3xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF7 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_GIF1 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_GIF2 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_GIF3 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_GIF4 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_GIF5 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_GIF6 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_GIF7 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_HTIF1 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_HTIF2 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_HTIF3 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_HTIF4 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_HTIF5 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_HTIF6 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_HTIF7 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TCIF1 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TCIF2 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TCIF3 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TCIF4 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TCIF5 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TCIF6 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TCIF7 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TEIF1 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TEIF2 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TEIF3 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TEIF4 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TEIF5 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TEIF6 : stm32f3xx_ll_dma.h
  • LL_DMA_ISR_TEIF7 : stm32f3xx_ll_dma.h
  • LL_DMA_MDATAALIGN_BYTE : stm32f3xx_ll_dma.h
  • LL_DMA_MDATAALIGN_HALFWORD : stm32f3xx_ll_dma.h
  • LL_DMA_MDATAALIGN_WORD : stm32f3xx_ll_dma.h
  • LL_DMA_MEMORY_INCREMENT : stm32f3xx_ll_dma.h
  • LL_DMA_MEMORY_NOINCREMENT : stm32f3xx_ll_dma.h
  • LL_DMA_MODE_CIRCULAR : stm32f3xx_ll_dma.h
  • LL_DMA_MODE_NORMAL : stm32f3xx_ll_dma.h
  • LL_DMA_PDATAALIGN_BYTE : stm32f3xx_ll_dma.h
  • LL_DMA_PDATAALIGN_HALFWORD : stm32f3xx_ll_dma.h
  • LL_DMA_PDATAALIGN_WORD : stm32f3xx_ll_dma.h
  • LL_DMA_PERIPH_INCREMENT : stm32f3xx_ll_dma.h
  • LL_DMA_PERIPH_NOINCREMENT : stm32f3xx_ll_dma.h
  • LL_DMA_PRIORITY_HIGH : stm32f3xx_ll_dma.h
  • LL_DMA_PRIORITY_LOW : stm32f3xx_ll_dma.h
  • LL_DMA_PRIORITY_MEDIUM : stm32f3xx_ll_dma.h
  • LL_DMA_PRIORITY_VERYHIGH : stm32f3xx_ll_dma.h
  • LL_DMA_ReadReg : stm32f3xx_ll_dma.h
  • LL_DMA_WriteReg : stm32f3xx_ll_dma.h
  • LL_EXTI_LINE_0 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_1 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_10 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_11 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_12 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_13 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_14 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_15 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_16 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_17 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_18 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_19 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_2 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_20 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_21 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_22 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_23 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_24 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_25 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_26 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_27 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_28 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_3 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_4 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_5 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_6 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_7 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_8 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_9 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_ALL : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_ALL_0_31 : stm32f3xx_ll_exti.h
  • LL_EXTI_LINE_NONE : stm32f3xx_ll_exti.h
  • LL_EXTI_MODE_EVENT : stm32f3xx_ll_exti.h
  • LL_EXTI_MODE_IT : stm32f3xx_ll_exti.h
  • LL_EXTI_MODE_IT_EVENT : stm32f3xx_ll_exti.h
  • LL_EXTI_ReadReg : stm32f3xx_ll_exti.h
  • LL_EXTI_TRIGGER_FALLING : stm32f3xx_ll_exti.h
  • LL_EXTI_TRIGGER_NONE : stm32f3xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING : stm32f3xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING_FALLING : stm32f3xx_ll_exti.h
  • LL_EXTI_WriteReg : stm32f3xx_ll_exti.h
  • LL_FLASH_LATENCY_0 : stm32f3xx_ll_system.h
  • LL_FLASH_LATENCY_1 : stm32f3xx_ll_system.h
  • LL_FLASH_LATENCY_2 : stm32f3xx_ll_system.h
  • LL_GPIO_AF_0 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_1 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_10 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_11 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_12 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_13 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_14 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_15 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_2 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_3 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_4 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_5 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_6 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_7 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_8 : stm32f3xx_ll_gpio.h
  • LL_GPIO_AF_9 : stm32f3xx_ll_gpio.h
  • LL_GPIO_MODE_ALTERNATE : stm32f3xx_ll_gpio.h
  • LL_GPIO_MODE_ANALOG : stm32f3xx_ll_gpio.h
  • LL_GPIO_MODE_INPUT : stm32f3xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT : stm32f3xx_ll_gpio.h
  • LL_GPIO_OUTPUT_OPENDRAIN : stm32f3xx_ll_gpio.h
  • LL_GPIO_OUTPUT_PUSHPULL : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_0 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_1 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_10 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_11 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_12 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_13 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_14 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_15 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_2 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_3 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_4 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_5 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_6 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_7 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_8 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_9 : stm32f3xx_ll_gpio.h
  • LL_GPIO_PIN_ALL : stm32f3xx_ll_gpio.h
  • LL_GPIO_PULL_DOWN : stm32f3xx_ll_gpio.h
  • LL_GPIO_PULL_NO : stm32f3xx_ll_gpio.h
  • LL_GPIO_PULL_UP : stm32f3xx_ll_gpio.h
  • LL_GPIO_ReadReg : stm32f3xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_HIGH : stm32f3xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_LOW : stm32f3xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_MEDIUM : stm32f3xx_ll_gpio.h
  • LL_GPIO_WriteReg : stm32f3xx_ll_gpio.h
  • LL_HANDLER_FAULT_BUS : stm32f3xx_ll_cortex.h
  • LL_HANDLER_FAULT_MEM : stm32f3xx_ll_cortex.h
  • LL_HANDLER_FAULT_USG : stm32f3xx_ll_cortex.h
  • LL_I2C_ACK : stm32f3xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_10BIT : stm32f3xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_7BIT : stm32f3xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_10BIT : stm32f3xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_7BIT : stm32f3xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_DISABLE : stm32f3xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_ENABLE : stm32f3xx_ll_i2c.h
  • LL_I2C_CR1_ADDRIE : stm32f3xx_ll_i2c.h
  • LL_I2C_CR1_ERRIE : stm32f3xx_ll_i2c.h
  • LL_I2C_CR1_NACKIE : stm32f3xx_ll_i2c.h
  • LL_I2C_CR1_RXIE : stm32f3xx_ll_i2c.h
  • LL_I2C_CR1_STOPIE : stm32f3xx_ll_i2c.h
  • LL_I2C_CR1_TCIE : stm32f3xx_ll_i2c.h
  • LL_I2C_CR1_TXIE : stm32f3xx_ll_i2c.h
  • LL_I2C_DIRECTION_READ : stm32f3xx_ll_i2c.h
  • LL_I2C_DIRECTION_WRITE : stm32f3xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_RECEIVE : stm32f3xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_TRANSMIT : stm32f3xx_ll_i2c.h
  • LL_I2C_GENERATE_NOSTARTSTOP : stm32f3xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_READ : stm32f3xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE : stm32f3xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_READ : stm32f3xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE : stm32f3xx_ll_i2c.h
  • LL_I2C_GENERATE_START_READ : stm32f3xx_ll_i2c.h
  • LL_I2C_GENERATE_START_WRITE : stm32f3xx_ll_i2c.h
  • LL_I2C_GENERATE_STOP : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_ADDRCF : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_ALERTCF : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_ARLOCF : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_BERRCF : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_NACKCF : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_OVRCF : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_PECCF : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_STOPCF : stm32f3xx_ll_i2c.h
  • LL_I2C_ICR_TIMOUTCF : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_ADDR : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_ALERT : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_ARLO : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_BERR : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_BUSY : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_NACKF : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_OVR : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_PECERR : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_RXNE : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_STOPF : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_TC : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_TCR : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_TIMEOUT : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_TXE : stm32f3xx_ll_i2c.h
  • LL_I2C_ISR_TXIS : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_AUTOEND : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_I2C : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_RELOAD : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE_ARP : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_HOST : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_RELOAD : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC : stm32f3xx_ll_i2c.h
  • LL_I2C_MODE_SOFTEND : stm32f3xx_ll_i2c.h
  • LL_I2C_NACK : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_10BIT : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_7BIT : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK01 : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK02 : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK03 : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK04 : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK05 : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK06 : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK07 : stm32f3xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_NOMASK : stm32f3xx_ll_i2c.h
  • LL_I2C_ReadReg : stm32f3xx_ll_i2c.h
  • LL_I2C_REQUEST_READ : stm32f3xx_ll_i2c.h
  • LL_I2C_REQUEST_WRITE : stm32f3xx_ll_i2c.h
  • LL_I2C_SMBUS_ALL_TIMEOUT : stm32f3xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA : stm32f3xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW : stm32f3xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH : stm32f3xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTB : stm32f3xx_ll_i2c.h
  • LL_I2C_WriteReg : stm32f3xx_ll_i2c.h
  • LL_I2S_AUDIOFREQ_11K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_16K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_192K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_22K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_32K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_44K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_48K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_8K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_96K : stm32f3xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_DEFAULT : stm32f3xx_ll_spi.h
  • LL_I2S_CR2_ERRIE : stm32f3xx_ll_spi.h
  • LL_I2S_CR2_RXNEIE : stm32f3xx_ll_spi.h
  • LL_I2S_CR2_TXEIE : stm32f3xx_ll_spi.h
  • LL_I2S_DATAFORMAT_16B : stm32f3xx_ll_spi.h
  • LL_I2S_DATAFORMAT_16B_EXTENDED : stm32f3xx_ll_spi.h
  • LL_I2S_DATAFORMAT_24B : stm32f3xx_ll_spi.h
  • LL_I2S_DATAFORMAT_32B : stm32f3xx_ll_spi.h
  • LL_I2S_MCLK_OUTPUT_DISABLE : stm32f3xx_ll_spi.h
  • LL_I2S_MCLK_OUTPUT_ENABLE : stm32f3xx_ll_spi.h
  • LL_I2S_MODE_MASTER_RX : stm32f3xx_ll_spi.h
  • LL_I2S_MODE_MASTER_TX : stm32f3xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_RX : stm32f3xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_TX : stm32f3xx_ll_spi.h
  • LL_I2S_POLARITY_HIGH : stm32f3xx_ll_spi.h
  • LL_I2S_POLARITY_LOW : stm32f3xx_ll_spi.h
  • LL_I2S_PRESCALER_PARITY_EVEN : stm32f3xx_ll_spi.h
  • LL_I2S_PRESCALER_PARITY_ODD : stm32f3xx_ll_spi.h
  • LL_I2S_ReadReg : stm32f3xx_ll_spi.h
  • LL_I2S_SR_BSY : stm32f3xx_ll_spi.h
  • LL_I2S_SR_FRE : stm32f3xx_ll_spi.h
  • LL_I2S_SR_OVR : stm32f3xx_ll_spi.h
  • LL_I2S_SR_RXNE : stm32f3xx_ll_spi.h
  • LL_I2S_SR_TXE : stm32f3xx_ll_spi.h
  • LL_I2S_SR_UDR : stm32f3xx_ll_spi.h
  • LL_I2S_STANDARD_LSB : stm32f3xx_ll_spi.h
  • LL_I2S_STANDARD_MSB : stm32f3xx_ll_spi.h
  • LL_I2S_STANDARD_PCM_LONG : stm32f3xx_ll_spi.h
  • LL_I2S_STANDARD_PCM_SHORT : stm32f3xx_ll_spi.h
  • LL_I2S_STANDARD_PHILIPS : stm32f3xx_ll_spi.h
  • LL_I2S_WriteReg : stm32f3xx_ll_spi.h
  • LL_IWDG_KEY_ENABLE : stm32f3xx_ll_iwdg.h
  • LL_IWDG_KEY_RELOAD : stm32f3xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_DISABLE : stm32f3xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_ENABLE : stm32f3xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_128 : stm32f3xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_16 : stm32f3xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_256 : stm32f3xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_32 : stm32f3xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_4 : stm32f3xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_64 : stm32f3xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_8 : stm32f3xx_ll_iwdg.h
  • LL_IWDG_ReadReg : stm32f3xx_ll_iwdg.h
  • LL_IWDG_SR_PVU : stm32f3xx_ll_iwdg.h
  • LL_IWDG_SR_RVU : stm32f3xx_ll_iwdg.h
  • LL_IWDG_SR_WVU : stm32f3xx_ll_iwdg.h
  • LL_IWDG_WriteReg : stm32f3xx_ll_iwdg.h
  • LL_MAX_DELAY : stm32f3xx_ll_utils.h
  • LL_MPU_ACCESS_BUFFERABLE : stm32f3xx_ll_cortex.h
  • LL_MPU_ACCESS_CACHEABLE : stm32f3xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_BUFFERABLE : stm32f3xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_CACHEABLE : stm32f3xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_SHAREABLE : stm32f3xx_ll_cortex.h
  • LL_MPU_ACCESS_SHAREABLE : stm32f3xx_ll_cortex.h
  • LL_MPU_CTRL_HARDFAULT_NMI : stm32f3xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF : stm32f3xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE : stm32f3xx_ll_cortex.h
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT : stm32f3xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_DISABLE : stm32f3xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_FULL_ACCESS : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NO_ACCESS : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER0 : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER1 : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER2 : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER3 : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER4 : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER5 : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER6 : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER7 : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO_URO : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW_URO : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128B : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1GB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256B : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2GB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32B : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4GB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512B : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64B : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64MB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8KB : stm32f3xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8MB : stm32f3xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL0 : stm32f3xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL1 : stm32f3xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL2 : stm32f3xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL4 : stm32f3xx_ll_cortex.h
  • LL_PWR_CR_CSBF : stm32f3xx_ll_pwr.h
  • LL_PWR_CR_CWUF : stm32f3xx_ll_pwr.h
  • LL_PWR_CSR_EWUP1 : stm32f3xx_ll_pwr.h
  • LL_PWR_CSR_EWUP2 : stm32f3xx_ll_pwr.h
  • LL_PWR_CSR_EWUP3 : stm32f3xx_ll_pwr.h
  • LL_PWR_CSR_PVDO : stm32f3xx_ll_pwr.h
  • LL_PWR_CSR_SBF : stm32f3xx_ll_pwr.h
  • LL_PWR_CSR_VREFINTRDYF : stm32f3xx_ll_pwr.h
  • LL_PWR_CSR_WUF : stm32f3xx_ll_pwr.h
  • LL_PWR_MODE_STANDBY : stm32f3xx_ll_pwr.h
  • LL_PWR_MODE_STOP_LPREGU : stm32f3xx_ll_pwr.h
  • LL_PWR_MODE_STOP_MAINREGU : stm32f3xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_0 : stm32f3xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_1 : stm32f3xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_2 : stm32f3xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_3 : stm32f3xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_4 : stm32f3xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_5 : stm32f3xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_6 : stm32f3xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_7 : stm32f3xx_ll_pwr.h
  • LL_PWR_ReadReg : stm32f3xx_ll_pwr.h
  • LL_PWR_REGU_DSMODE_LOW_POWER : stm32f3xx_ll_pwr.h
  • LL_PWR_REGU_DSMODE_MAIN : stm32f3xx_ll_pwr.h
  • LL_PWR_SDADC_ANALOG1 : stm32f3xx_ll_pwr.h
  • LL_PWR_SDADC_ANALOG2 : stm32f3xx_ll_pwr.h
  • LL_PWR_SDADC_ANALOG3 : stm32f3xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN1 : stm32f3xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN2 : stm32f3xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN3 : stm32f3xx_ll_pwr.h
  • LL_PWR_WriteReg : stm32f3xx_ll_pwr.h
  • LL_RCC_ADC_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 : stm32f3xx_ll_rcc.h
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 : stm32f3xx_ll_rcc.h
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB1_DIV_1 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB1_DIV_16 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB1_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB1_DIV_4 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB1_DIV_8 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB2_DIV_1 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB2_DIV_16 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB2_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB2_DIV_4 : stm32f3xx_ll_rcc.h
  • LL_RCC_APB2_DIV_8 : stm32f3xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE_HSI_DIV244 : stm32f3xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE_LSE : stm32f3xx_ll_rcc.h
  • LL_RCC_CFGR_MCOF : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_CSSC : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_CSSF : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_HSERDYC : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_HSERDYF : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_HSERDYIE : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_HSIRDYC : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_HSIRDYF : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_HSIRDYIE : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_LSERDYC : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_LSERDYF : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_LSERDYIE : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_LSIRDYC : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_LSIRDYF : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_LSIRDYIE : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_PLLRDYC : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_PLLRDYF : stm32f3xx_ll_rcc.h
  • LL_RCC_CIR_PLLRDYIE : stm32f3xx_ll_rcc.h
  • LL_RCC_CSR_IWDGRSTF : stm32f3xx_ll_rcc.h
  • LL_RCC_CSR_LPWRRSTF : stm32f3xx_ll_rcc.h
  • LL_RCC_CSR_OBLRSTF : stm32f3xx_ll_rcc.h
  • LL_RCC_CSR_PINRSTF : stm32f3xx_ll_rcc.h
  • LL_RCC_CSR_PORRSTF : stm32f3xx_ll_rcc.h
  • LL_RCC_CSR_SFTRSTF : stm32f3xx_ll_rcc.h
  • LL_RCC_CSR_V18PWRRSTF : stm32f3xx_ll_rcc.h
  • LL_RCC_CSR_WWDGRSTF : stm32f3xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_HSI : stm32f3xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK : stm32f3xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_HSI : stm32f3xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_SYSCLK : stm32f3xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_HIGH : stm32f3xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_LOW : stm32f3xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMHIGH : stm32f3xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMLOW : stm32f3xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_1 : stm32f3xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSE : stm32f3xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI : stm32f3xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSE : stm32f3xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSI : stm32f3xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_NOCLOCK : stm32f3xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_SYSCLK : stm32f3xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NA : stm32f3xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NO : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_10 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_11 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_12 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_13 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_14 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_15 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_16 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_3 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_4 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_5 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_6 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_7 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_8 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLL_MUL_9 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_1 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_10 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_11 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_12 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_13 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_14 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_15 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_16 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_3 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_4 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_5 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_6 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_7 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_8 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_9 : stm32f3xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSI_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_1 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_10 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_11 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_12 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_13 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_14 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_15 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_16 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_3 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_4 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_5 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_6 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_7 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_8 : stm32f3xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_9 : stm32f3xx_ll_rcc.h
  • LL_RCC_ReadReg : stm32f3xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32 : stm32f3xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSE : stm32f3xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSI : stm32f3xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_NONE : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_1 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_10 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_12 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_14 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_16 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_20 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_24 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_28 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_32 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_36 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_4 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_40 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_44 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_48 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_6 : stm32f3xx_ll_rcc.h
  • LL_RCC_SDADC_CLKSRC_SYS_DIV_8 : stm32f3xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSE : stm32f3xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSI : stm32f3xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_PLL : stm32f3xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE : stm32f3xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI : stm32f3xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_1 : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_128 : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_16 : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_2 : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_256 : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_4 : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_512 : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_64 : stm32f3xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_8 : stm32f3xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_HSI : stm32f3xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_LSE : stm32f3xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_PCLK2 : stm32f3xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_SYSCLK : stm32f3xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_HSI : stm32f3xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_LSE : stm32f3xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_PCLK1 : stm32f3xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_SYSCLK : stm32f3xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_HSI : stm32f3xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_LSE : stm32f3xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_PCLK1 : stm32f3xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_SYSCLK : stm32f3xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE : stm32f3xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL : stm32f3xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 : stm32f3xx_ll_rcc.h
  • LL_RCC_WriteReg : stm32f3xx_ll_rcc.h
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN : stm32f3xx_ll_rtc.h
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL : stm32f3xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMA : stm32f3xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMB : stm32f3xx_ll_rtc.h
  • LL_RTC_ALARMOUT_DISABLE : stm32f3xx_ll_rtc.h
  • LL_RTC_ALARMOUT_WAKEUP : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_DATE : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_ALL : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_DATEWEEKDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_HOURS : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_MINUTES : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_NONE : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_SECONDS : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_AM : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_PM : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_DATE : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_ALL : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_DATEWEEKDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_HOURS : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_MINUTES : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_NONE : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_SECONDS : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_AM : stm32f3xx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_PM : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR0 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR1 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR10 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR11 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR12 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR13 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR14 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR15 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR16 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR17 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR18 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR19 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR2 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR20 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR21 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR22 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR23 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR24 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR25 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR26 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR27 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR28 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR29 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR3 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR30 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR31 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR4 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR5 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR6 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR7 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR8 : stm32f3xx_ll_rtc.h
  • LL_RTC_BKP_DR9 : stm32f3xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_NONE : stm32f3xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_SET : stm32f3xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_1HZ : stm32f3xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_512HZ : stm32f3xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_NONE : stm32f3xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_16SEC : stm32f3xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_32SEC : stm32f3xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_8SEC : stm32f3xx_ll_rtc.h
  • LL_RTC_CR_ALRAIE : stm32f3xx_ll_rtc.h
  • LL_RTC_CR_ALRBIE : stm32f3xx_ll_rtc.h
  • LL_RTC_CR_TSIE : stm32f3xx_ll_rtc.h
  • LL_RTC_CR_WUTIE : stm32f3xx_ll_rtc.h
  • LL_RTC_FORMAT_BCD : stm32f3xx_ll_rtc.h
  • LL_RTC_FORMAT_BIN : stm32f3xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_24HOUR : stm32f3xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_AMPM : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_ALRAF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_ALRAWF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_ALRBF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_ALRBWF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_INITF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_INITS : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_RECALPF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_RSF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_SHPF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_TAMP1F : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_TAMP2F : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_TAMP3F : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_TSF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_TSOVF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_WUTF : stm32f3xx_ll_rtc.h
  • LL_RTC_ISR_WUTWF : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_APRIL : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_AUGUST : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_DECEMBER : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_FEBRUARY : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_JANUARY : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_JULY : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_JUNE : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_MARCH : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_MAY : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_NOVEMBER : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_OCTOBER : stm32f3xx_ll_rtc.h
  • LL_RTC_MONTH_SEPTEMBER : stm32f3xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH : stm32f3xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW : stm32f3xx_ll_rtc.h
  • LL_RTC_PIN_PC13 : stm32f3xx_ll_rtc.h
  • LL_RTC_PIN_PC14 : stm32f3xx_ll_rtc.h
  • LL_RTC_PIN_PC15 : stm32f3xx_ll_rtc.h
  • LL_RTC_ReadReg : stm32f3xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_ADVANCE : stm32f3xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_DELAY : stm32f3xx_ll_rtc.h
  • LL_RTC_TAFCR_TAMPIE : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_1 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_2 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_3 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_1RTCCLK : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_2RTCCLK : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_4RTCCLK : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_8RTCCLK : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_2SAMPLE : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_4SAMPLE : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_8SAMPLE : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_DISABLE : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER1 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER2 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER3 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER1 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER2 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER3 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_256 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_512 : stm32f3xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192 : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_AM_OR_24 : stm32f3xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_PM : stm32f3xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_FALLING : stm32f3xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_RISING : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_AM : stm32f3xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_PM : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_16 : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_2 : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_4 : stm32f3xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_8 : stm32f3xx_ll_rtc.h
  • LL_RTC_WEEKDAY_FRIDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_WEEKDAY_MONDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SATURDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SUNDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_WEEKDAY_THURSDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_WEEKDAY_TUESDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_WEEKDAY_WEDNESDAY : stm32f3xx_ll_rtc.h
  • LL_RTC_WriteReg : stm32f3xx_ll_rtc.h
  • LL_SPI_BAUDRATEPRESCALER_DIV128 : stm32f3xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV16 : stm32f3xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV2 : stm32f3xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV256 : stm32f3xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV32 : stm32f3xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV4 : stm32f3xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV64 : stm32f3xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV8 : stm32f3xx_ll_spi.h
  • LL_SPI_CR2_ERRIE : stm32f3xx_ll_spi.h
  • LL_SPI_CR2_RXNEIE : stm32f3xx_ll_spi.h
  • LL_SPI_CR2_TXEIE : stm32f3xx_ll_spi.h
  • LL_SPI_CRC_16BIT : stm32f3xx_ll_spi.h
  • LL_SPI_CRC_8BIT : stm32f3xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_DISABLE : stm32f3xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_ENABLE : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_10BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_11BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_12BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_13BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_14BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_15BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_16BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_4BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_5BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_6BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_7BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_8BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DATAWIDTH_9BIT : stm32f3xx_ll_spi.h
  • LL_SPI_DMA_PARITY_EVEN : stm32f3xx_ll_spi.h
  • LL_SPI_DMA_PARITY_ODD : stm32f3xx_ll_spi.h
  • LL_SPI_FULL_DUPLEX : stm32f3xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_RX : stm32f3xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_TX : stm32f3xx_ll_spi.h
  • LL_SPI_LSB_FIRST : stm32f3xx_ll_spi.h
  • LL_SPI_MODE_MASTER : stm32f3xx_ll_spi.h
  • LL_SPI_MODE_SLAVE : stm32f3xx_ll_spi.h
  • LL_SPI_MSB_FIRST : stm32f3xx_ll_spi.h
  • LL_SPI_NSS_HARD_INPUT : stm32f3xx_ll_spi.h
  • LL_SPI_NSS_HARD_OUTPUT : stm32f3xx_ll_spi.h
  • LL_SPI_NSS_SOFT : stm32f3xx_ll_spi.h
  • LL_SPI_PHASE_1EDGE : stm32f3xx_ll_spi.h
  • LL_SPI_PHASE_2EDGE : stm32f3xx_ll_spi.h
  • LL_SPI_POLARITY_HIGH : stm32f3xx_ll_spi.h
  • LL_SPI_POLARITY_LOW : stm32f3xx_ll_spi.h
  • LL_SPI_PROTOCOL_MOTOROLA : stm32f3xx_ll_spi.h
  • LL_SPI_PROTOCOL_TI : stm32f3xx_ll_spi.h
  • LL_SPI_ReadReg : stm32f3xx_ll_spi.h
  • LL_SPI_RX_FIFO_EMPTY : stm32f3xx_ll_spi.h
  • LL_SPI_RX_FIFO_FULL : stm32f3xx_ll_spi.h
  • LL_SPI_RX_FIFO_HALF_FULL : stm32f3xx_ll_spi.h
  • LL_SPI_RX_FIFO_QUARTER_FULL : stm32f3xx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_HALF : stm32f3xx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_QUARTER : stm32f3xx_ll_spi.h
  • LL_SPI_SIMPLEX_RX : stm32f3xx_ll_spi.h
  • LL_SPI_SR_BSY : stm32f3xx_ll_spi.h
  • LL_SPI_SR_CRCERR : stm32f3xx_ll_spi.h
  • LL_SPI_SR_FRE : stm32f3xx_ll_spi.h
  • LL_SPI_SR_MODF : stm32f3xx_ll_spi.h
  • LL_SPI_SR_OVR : stm32f3xx_ll_spi.h
  • LL_SPI_SR_RXNE : stm32f3xx_ll_spi.h
  • LL_SPI_SR_TXE : stm32f3xx_ll_spi.h
  • LL_SPI_TX_FIFO_EMPTY : stm32f3xx_ll_spi.h
  • LL_SPI_TX_FIFO_FULL : stm32f3xx_ll_spi.h
  • LL_SPI_TX_FIFO_HALF_FULL : stm32f3xx_ll_spi.h
  • LL_SPI_TX_FIFO_QUARTER_FULL : stm32f3xx_ll_spi.h
  • LL_SPI_WriteReg : stm32f3xx_ll_spi.h
  • LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3 : stm32f3xx_ll_system.h
  • LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3 : stm32f3xx_ll_system.h
  • LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 : stm32f3xx_ll_system.h
  • LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 : stm32f3xx_ll_system.h
  • LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 : stm32f3xx_ll_system.h
  • LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE0 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE1 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE10 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE11 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE12 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE13 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE14 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE15 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE2 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE3 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE4 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE5 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE6 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE7 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE8 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE9 : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTA : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTB : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTC : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTD : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTE : stm32f3xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTF : stm32f3xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 : stm32f3xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 : stm32f3xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6 : stm32f3xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7 : stm32f3xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 : stm32f3xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 : stm32f3xx_ll_system.h
  • LL_SYSCFG_REMAP_FLASH : stm32f3xx_ll_system.h
  • LL_SYSCFG_REMAP_SRAM : stm32f3xx_ll_system.h
  • LL_SYSCFG_REMAP_SYSTEMFLASH : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM16_RMP_DMA1_CH3 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM16_RMP_DMA1_CH6 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM17_RMP_DMA1_CH1 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM17_RMP_DMA1_CH7 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM18_RMP_DMA1_CH5 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM18_RMP_DMA2_CH5 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM6_RMP_DMA1_CH3 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM6_RMP_DMA2_CH3 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM7_RMP_DMA1_CH4 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIM7_RMP_DMA2_CH4 : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_LOCKUP : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_PVD : stm32f3xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM_PARITY : stm32f3xx_ll_system.h
  • LL_SYSTICK_CLKSOURCE_HCLK : stm32f3xx_ll_cortex.h
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32f3xx_ll_cortex.h
  • LL_TIM_ACTIVEINPUT_DIRECTTI : stm32f3xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_INDIRECTTI : stm32f3xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_TRC : stm32f3xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_DISABLE : stm32f3xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_ENABLE : stm32f3xx_ll_tim.h
  • LL_TIM_BREAK_DISABLE : stm32f3xx_ll_tim.h
  • LL_TIM_BREAK_ENABLE : stm32f3xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_HIGH : stm32f3xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_LOW : stm32f3xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_CC : stm32f3xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_UPDATE : stm32f3xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI : stm32f3xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY : stm32f3xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1 : stm32f3xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1N : stm32f3xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2 : stm32f3xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2N : stm32f3xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3 : stm32f3xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3N : stm32f3xx_ll_tim.h
  • LL_TIM_CHANNEL_CH4 : stm32f3xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV1 : stm32f3xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV2 : stm32f3xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV4 : stm32f3xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE1 : stm32f3xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE2 : stm32f3xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_INTERNAL : stm32f3xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_DOWN : stm32f3xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_UP : stm32f3xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_DOWN : stm32f3xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP : stm32f3xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN : stm32f3xx_ll_tim.h
  • LL_TIM_COUNTERMODE_DOWN : stm32f3xx_ll_tim.h
  • LL_TIM_COUNTERMODE_UP : stm32f3xx_ll_tim.h
  • LL_TIM_DIER_BIE : stm32f3xx_ll_tim.h
  • LL_TIM_DIER_CC1IE : stm32f3xx_ll_tim.h
  • LL_TIM_DIER_CC2IE : stm32f3xx_ll_tim.h
  • LL_TIM_DIER_CC3IE : stm32f3xx_ll_tim.h
  • LL_TIM_DIER_CC4IE : stm32f3xx_ll_tim.h
  • LL_TIM_DIER_COMIE : stm32f3xx_ll_tim.h
  • LL_TIM_DIER_TIE : stm32f3xx_ll_tim.h
  • LL_TIM_DIER_UIE : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_ARR : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_BDTR : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCER : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR1 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR2 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR3 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR1 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR2 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR3 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR4 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CNT : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR1 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR2 : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_DIER : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_EGR : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_OR : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_PSC : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_RCR : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SMCR : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SR : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_1TRANSFER : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS : stm32f3xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI1 : stm32f3xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI2 : stm32f3xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X4_TI12 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N5 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N2 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N4 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N5 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_INVERTED : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_NONINVERTED : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV1 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV2 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV4 : stm32f3xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV8 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N5 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N2 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N4 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N5 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N6 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N8 : stm32f3xx_ll_tim.h
  • LL_TIM_IC_POLARITY_BOTHEDGE : stm32f3xx_ll_tim.h
  • LL_TIM_IC_POLARITY_FALLING : stm32f3xx_ll_tim.h
  • LL_TIM_IC_POLARITY_RISING : stm32f3xx_ll_tim.h
  • LL_TIM_ICPSC_DIV1 : stm32f3xx_ll_tim.h
  • LL_TIM_ICPSC_DIV2 : stm32f3xx_ll_tim.h
  • LL_TIM_ICPSC_DIV4 : stm32f3xx_ll_tim.h
  • LL_TIM_ICPSC_DIV8 : stm32f3xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_1 : stm32f3xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_2 : stm32f3xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_3 : stm32f3xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_OFF : stm32f3xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_HIGH : stm32f3xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_LOW : stm32f3xx_ll_tim.h
  • LL_TIM_OCMODE_ACTIVE : stm32f3xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_ACTIVE : stm32f3xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_INACTIVE : stm32f3xx_ll_tim.h
  • LL_TIM_OCMODE_FROZEN : stm32f3xx_ll_tim.h
  • LL_TIM_OCMODE_INACTIVE : stm32f3xx_ll_tim.h
  • LL_TIM_OCMODE_PWM1 : stm32f3xx_ll_tim.h
  • LL_TIM_OCMODE_PWM2 : stm32f3xx_ll_tim.h
  • LL_TIM_OCMODE_TOGGLE : stm32f3xx_ll_tim.h
  • LL_TIM_OCPOLARITY_HIGH : stm32f3xx_ll_tim.h
  • LL_TIM_OCPOLARITY_LOW : stm32f3xx_ll_tim.h
  • LL_TIM_OCSTATE_DISABLE : stm32f3xx_ll_tim.h
  • LL_TIM_OCSTATE_ENABLE : stm32f3xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_REPETITIVE : stm32f3xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_SINGLE : stm32f3xx_ll_tim.h
  • LL_TIM_OSSI_DISABLE : stm32f3xx_ll_tim.h
  • LL_TIM_OSSI_ENABLE : stm32f3xx_ll_tim.h
  • LL_TIM_OSSR_DISABLE : stm32f3xx_ll_tim.h
  • LL_TIM_OSSR_ENABLE : stm32f3xx_ll_tim.h
  • LL_TIM_ReadReg : stm32f3xx_ll_tim.h
  • LL_TIM_SLAVEMODE_DISABLED : stm32f3xx_ll_tim.h
  • LL_TIM_SLAVEMODE_GATED : stm32f3xx_ll_tim.h
  • LL_TIM_SLAVEMODE_RESET : stm32f3xx_ll_tim.h
  • LL_TIM_SLAVEMODE_TRIGGER : stm32f3xx_ll_tim.h
  • LL_TIM_SR_B2IF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_BIF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_CC1IF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_CC1OF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_CC2IF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_CC2OF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_CC3IF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_CC3OF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_CC4IF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_CC4OF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_COMIF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_TIF : stm32f3xx_ll_tim.h
  • LL_TIM_SR_UIF : stm32f3xx_ll_tim.h
  • LL_TIM_TIM14_TI1_RMP_GPIO : stm32f3xx_ll_tim.h
  • LL_TIM_TIM14_TI1_RMP_HSE : stm32f3xx_ll_tim.h
  • LL_TIM_TIM14_TI1_RMP_MCO : stm32f3xx_ll_tim.h
  • LL_TIM_TIM14_TI1_RMP_RTC_CLK : stm32f3xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_GPIO : stm32f3xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_HSE_32 : stm32f3xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_MCO : stm32f3xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_RTC : stm32f3xx_ll_tim.h
  • LL_TIM_TRGO_CC1IF : stm32f3xx_ll_tim.h
  • LL_TIM_TRGO_ENABLE : stm32f3xx_ll_tim.h
  • LL_TIM_TRGO_OC1REF : stm32f3xx_ll_tim.h
  • LL_TIM_TRGO_OC2REF : stm32f3xx_ll_tim.h
  • LL_TIM_TRGO_OC3REF : stm32f3xx_ll_tim.h
  • LL_TIM_TRGO_OC4REF : stm32f3xx_ll_tim.h
  • LL_TIM_TRGO_RESET : stm32f3xx_ll_tim.h
  • LL_TIM_TRGO_UPDATE : stm32f3xx_ll_tim.h
  • LL_TIM_TS_ETRF : stm32f3xx_ll_tim.h
  • LL_TIM_TS_ITR0 : stm32f3xx_ll_tim.h
  • LL_TIM_TS_ITR1 : stm32f3xx_ll_tim.h
  • LL_TIM_TS_ITR2 : stm32f3xx_ll_tim.h
  • LL_TIM_TS_ITR3 : stm32f3xx_ll_tim.h
  • LL_TIM_TS_TI1F_ED : stm32f3xx_ll_tim.h
  • LL_TIM_TS_TI1FP1 : stm32f3xx_ll_tim.h
  • LL_TIM_TS_TI2FP2 : stm32f3xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_COUNTER : stm32f3xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_REGULAR : stm32f3xx_ll_tim.h
  • LL_TIM_WriteReg : stm32f3xx_ll_tim.h
  • LL_USART_ADDRESS_DETECT_4B : stm32f3xx_ll_usart.h
  • LL_USART_ADDRESS_DETECT_7B : stm32f3xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME : stm32f3xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME : stm32f3xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE : stm32f3xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT : stm32f3xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_NEGATIVE : stm32f3xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_POSITIVE : stm32f3xx_ll_usart.h
  • LL_USART_BITORDER_LSBFIRST : stm32f3xx_ll_usart.h
  • LL_USART_BITORDER_MSBFIRST : stm32f3xx_ll_usart.h
  • LL_USART_CLOCK_DISABLE : stm32f3xx_ll_usart.h
  • LL_USART_CLOCK_ENABLE : stm32f3xx_ll_usart.h
  • LL_USART_CR1_CMIE : stm32f3xx_ll_usart.h
  • LL_USART_CR1_EOBIE : stm32f3xx_ll_usart.h
  • LL_USART_CR1_IDLEIE : stm32f3xx_ll_usart.h
  • LL_USART_CR1_PEIE : stm32f3xx_ll_usart.h
  • LL_USART_CR1_RTOIE : stm32f3xx_ll_usart.h
  • LL_USART_CR1_RXNEIE : stm32f3xx_ll_usart.h
  • LL_USART_CR1_TCIE : stm32f3xx_ll_usart.h
  • LL_USART_CR1_TXEIE : stm32f3xx_ll_usart.h
  • LL_USART_CR2_LBDIE : stm32f3xx_ll_usart.h
  • LL_USART_CR3_CTSIE : stm32f3xx_ll_usart.h
  • LL_USART_CR3_EIE : stm32f3xx_ll_usart.h
  • LL_USART_CR3_WUFIE : stm32f3xx_ll_usart.h
  • LL_USART_DATAWIDTH_8B : stm32f3xx_ll_usart.h
  • LL_USART_DATAWIDTH_9B : stm32f3xx_ll_usart.h
  • LL_USART_DE_POLARITY_HIGH : stm32f3xx_ll_usart.h
  • LL_USART_DE_POLARITY_LOW : stm32f3xx_ll_usart.h
  • LL_USART_DIRECTION_NONE : stm32f3xx_ll_usart.h
  • LL_USART_DIRECTION_RX : stm32f3xx_ll_usart.h
  • LL_USART_DIRECTION_TX : stm32f3xx_ll_usart.h
  • LL_USART_DIRECTION_TX_RX : stm32f3xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_RECEIVE : stm32f3xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_TRANSMIT : stm32f3xx_ll_usart.h
  • LL_USART_HWCONTROL_CTS : stm32f3xx_ll_usart.h
  • LL_USART_HWCONTROL_NONE : stm32f3xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS : stm32f3xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS_CTS : stm32f3xx_ll_usart.h
  • LL_USART_ICR_CMCF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_CTSCF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_EOBCF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_FECF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_IDLECF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_LBDCF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_NCF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_ORECF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_PECF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_RTOCF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_TCCF : stm32f3xx_ll_usart.h
  • LL_USART_ICR_WUCF : stm32f3xx_ll_usart.h
  • LL_USART_IRDA_POWER_LOW : stm32f3xx_ll_usart.h
  • LL_USART_IRDA_POWER_NORMAL : stm32f3xx_ll_usart.h
  • LL_USART_ISR_ABRE : stm32f3xx_ll_usart.h
  • LL_USART_ISR_ABRF : stm32f3xx_ll_usart.h
  • LL_USART_ISR_BUSY : stm32f3xx_ll_usart.h
  • LL_USART_ISR_CMF : stm32f3xx_ll_usart.h
  • LL_USART_ISR_CTS : stm32f3xx_ll_usart.h
  • LL_USART_ISR_CTSIF : stm32f3xx_ll_usart.h
  • LL_USART_ISR_EOBF : stm32f3xx_ll_usart.h
  • LL_USART_ISR_FE : stm32f3xx_ll_usart.h
  • LL_USART_ISR_IDLE : stm32f3xx_ll_usart.h
  • LL_USART_ISR_LBDF : stm32f3xx_ll_usart.h
  • LL_USART_ISR_NE : stm32f3xx_ll_usart.h
  • LL_USART_ISR_ORE : stm32f3xx_ll_usart.h
  • LL_USART_ISR_PE : stm32f3xx_ll_usart.h
  • LL_USART_ISR_REACK : stm32f3xx_ll_usart.h
  • LL_USART_ISR_RTOF : stm32f3xx_ll_usart.h
  • LL_USART_ISR_RWU : stm32f3xx_ll_usart.h
  • LL_USART_ISR_RXNE : stm32f3xx_ll_usart.h
  • LL_USART_ISR_SBKF : stm32f3xx_ll_usart.h
  • LL_USART_ISR_TC : stm32f3xx_ll_usart.h
  • LL_USART_ISR_TEACK : stm32f3xx_ll_usart.h
  • LL_USART_ISR_TXE : stm32f3xx_ll_usart.h
  • LL_USART_ISR_WUF : stm32f3xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_NO_OUTPUT : stm32f3xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_OUTPUT : stm32f3xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_10B : stm32f3xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_11B : stm32f3xx_ll_usart.h
  • LL_USART_OVERSAMPLING_16 : stm32f3xx_ll_usart.h
  • LL_USART_OVERSAMPLING_8 : stm32f3xx_ll_usart.h
  • LL_USART_PARITY_EVEN : stm32f3xx_ll_usart.h
  • LL_USART_PARITY_NONE : stm32f3xx_ll_usart.h
  • LL_USART_PARITY_ODD : stm32f3xx_ll_usart.h
  • LL_USART_PHASE_1EDGE : stm32f3xx_ll_usart.h
  • LL_USART_PHASE_2EDGE : stm32f3xx_ll_usart.h
  • LL_USART_POLARITY_HIGH : stm32f3xx_ll_usart.h
  • LL_USART_POLARITY_LOW : stm32f3xx_ll_usart.h
  • LL_USART_ReadReg : stm32f3xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_INVERTED : stm32f3xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_STANDARD : stm32f3xx_ll_usart.h
  • LL_USART_STOPBITS_0_5 : stm32f3xx_ll_usart.h
  • LL_USART_STOPBITS_1 : stm32f3xx_ll_usart.h
  • LL_USART_STOPBITS_1_5 : stm32f3xx_ll_usart.h
  • LL_USART_STOPBITS_2 : stm32f3xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_INVERTED : stm32f3xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_STANDARD : stm32f3xx_ll_usart.h
  • LL_USART_TXRX_STANDARD : stm32f3xx_ll_usart.h
  • LL_USART_TXRX_SWAPPED : stm32f3xx_ll_usart.h
  • LL_USART_WAKEUP_ADDRESSMARK : stm32f3xx_ll_usart.h
  • LL_USART_WAKEUP_IDLELINE : stm32f3xx_ll_usart.h
  • LL_USART_WAKEUP_ON_ADDRESS : stm32f3xx_ll_usart.h
  • LL_USART_WAKEUP_ON_RXNE : stm32f3xx_ll_usart.h
  • LL_USART_WAKEUP_ON_STARTBIT : stm32f3xx_ll_usart.h
  • LL_USART_WriteReg : stm32f3xx_ll_usart.h
  • LL_UTILS_HSEBYPASS_OFF : stm32f3xx_ll_utils.h
  • LL_UTILS_HSEBYPASS_ON : stm32f3xx_ll_utils.h
  • LL_WWDG_CFR_EWI : stm32f3xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_1 : stm32f3xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_2 : stm32f3xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_4 : stm32f3xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_8 : stm32f3xx_ll_wwdg.h
  • LL_WWDG_ReadReg : stm32f3xx_ll_wwdg.h
  • LL_WWDG_WriteReg : stm32f3xx_ll_wwdg.h
  • LSE_STARTUP_TIMEOUT : stm32f3xx_hal_conf.h
  • LSE_VALUE : stm32f3xx_hal_conf.h , stm32f3xx_ll_rcc.h
  • LSI_TIMEOUT_VALUE : stm32f3xx_hal_rcc.h
  • LSI_VALUE : stm32f3xx_hal_conf.h , stm32f3xx_ll_rcc.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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- m -

  • MAX_NBYTE_SIZE : stm32f3xx_hal_i2c.c , stm32f3xx_hal_smbus.c
  • MCO1_CLK_ENABLE : stm32f3xx_hal_rcc.c
  • MCO1_GPIO_PORT : stm32f3xx_hal_rcc.c
  • MCO1_PIN : stm32f3xx_hal_rcc.c
  • MPU_ACCESS_BUFFERABLE : stm32f3xx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32f3xx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32f3xx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32f3xx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32f3xx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32f3xx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32f3xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32f3xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32f3xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32f3xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32f3xx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32f3xx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32f3xx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32f3xx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32f3xx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32f3xx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32f3xx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32f3xx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32f3xx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32f3xx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32f3xx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32f3xx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32f3xx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32f3xx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32f3xx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32f3xx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32f3xx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_128B : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_32B : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_64B : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32f3xx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32f3xx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32f3xx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32f3xx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32f3xx_hal_cortex.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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- n -

  • NVIC_PRIORITYGROUP_0 : stm32f3xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32f3xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32f3xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32f3xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32f3xx_hal_cortex.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
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- o -

  • OB_BOOT1_RESET : stm32f3xx_hal_flash_ex.h
  • OB_BOOT1_SET : stm32f3xx_hal_flash_ex.h
  • OB_DATA_ADDRESS_DATA0 : stm32f3xx_hal_flash_ex.h
  • OB_DATA_ADDRESS_DATA1 : stm32f3xx_hal_flash_ex.h
  • OB_IWDG_HW : stm32f3xx_hal_flash_ex.h
  • OB_IWDG_SW : stm32f3xx_hal_flash_ex.h
  • OB_RDP_LEVEL_0 : stm32f3xx_hal_flash_ex.h
  • OB_RDP_LEVEL_1 : stm32f3xx_hal_flash_ex.h
  • OB_RDP_LEVEL_2 : stm32f3xx_hal_flash_ex.h
  • OB_SDACD_VDD_MONITOR_RESET : stm32f3xx_hal_flash_ex.h
  • OB_SDACD_VDD_MONITOR_SET : stm32f3xx_hal_flash_ex.h
  • OB_SRAM_PARITY_RESET : stm32f3xx_hal_flash_ex.h
  • OB_SRAM_PARITY_SET : stm32f3xx_hal_flash_ex.h
  • OB_STDBY_NO_RST : stm32f3xx_hal_flash_ex.h
  • OB_STDBY_RST : stm32f3xx_hal_flash_ex.h
  • OB_STOP_NO_RST : stm32f3xx_hal_flash_ex.h
  • OB_STOP_RST : stm32f3xx_hal_flash_ex.h
  • OB_VDDA_ANALOG_OFF : stm32f3xx_hal_flash_ex.h
  • OB_VDDA_ANALOG_ON : stm32f3xx_hal_flash_ex.h
  • OB_WRP_ALLPAGES : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES0TO1 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES0TO15MASK : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES10TO11 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES12TO13 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES14TO15 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES16TO17 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES16TO31MASK : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES18TO19 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES20TO21 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES22TO23 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES24TO25 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES26TO27 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES28TO29 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES2TO3 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES30TO31 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES32TO33 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES32TO47MASK : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES34TO35 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES36TO37 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES38TO39 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES40TO41 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES42TO43 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES44TO45 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES46TO47 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES48TO127MASK : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES48TO49 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES4TO5 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES50TO51 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES52TO53 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES54TO55 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES56TO57 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES58TO59 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES60TO61 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES62TO127 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES6TO7 : stm32f3xx_hal_flash_ex.h
  • OB_WRP_PAGES8TO9 : stm32f3xx_hal_flash_ex.h
  • OB_WRPSTATE_DISABLE : stm32f3xx_hal_flash_ex.h
  • OB_WRPSTATE_ENABLE : stm32f3xx_hal_flash_ex.h
  • OPTIONBYTE_DATA : stm32f3xx_hal_flash_ex.h
  • OPTIONBYTE_RDP : stm32f3xx_hal_flash_ex.h
  • OPTIONBYTE_USER : stm32f3xx_hal_flash_ex.h
  • OPTIONBYTE_WRP : stm32f3xx_hal_flash_ex.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
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  • f
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- p -

  • PACKAGE_BASE_ADDRESS : stm32f3xx_ll_utils.h
  • PCD_CALC_BLK2 : stm32f3xx_hal_pcd.h
  • PCD_CALC_BLK32 : stm32f3xx_hal_pcd.h
  • PCD_CLEAR_EP_DBUF : stm32f3xx_hal_pcd.h
  • PCD_CLEAR_EP_KIND : stm32f3xx_hal_pcd.h
  • PCD_CLEAR_OUT_STATUS : stm32f3xx_hal_pcd.h
  • PCD_CLEAR_RX_DTOG : stm32f3xx_hal_pcd.h
  • PCD_CLEAR_RX_EP_CTR : stm32f3xx_hal_pcd.h
  • PCD_CLEAR_TX_DTOG : stm32f3xx_hal_pcd.h
  • PCD_CLEAR_TX_EP_CTR : stm32f3xx_hal_pcd.h
  • PCD_DBL_BUF : stm32f3xx_hal_pcd.h
  • PCD_ENDP0 : stm32f3xx_hal_pcd.h
  • PCD_ENDP1 : stm32f3xx_hal_pcd.h
  • PCD_ENDP2 : stm32f3xx_hal_pcd.h
  • PCD_ENDP3 : stm32f3xx_hal_pcd.h
  • PCD_ENDP4 : stm32f3xx_hal_pcd.h
  • PCD_ENDP5 : stm32f3xx_hal_pcd.h
  • PCD_ENDP6 : stm32f3xx_hal_pcd.h
  • PCD_ENDP7 : stm32f3xx_hal_pcd.h
  • PCD_EP0MPS_08 : stm32f3xx_hal_pcd.h
  • PCD_EP0MPS_16 : stm32f3xx_hal_pcd.h
  • PCD_EP0MPS_32 : stm32f3xx_hal_pcd.h
  • PCD_EP0MPS_64 : stm32f3xx_hal_pcd.h
  • PCD_EP_RX_ADDRESS : stm32f3xx_hal_pcd_ex.h
  • PCD_EP_RX_CNT : stm32f3xx_hal_pcd_ex.h
  • PCD_EP_TX_ADDRESS : stm32f3xx_hal_pcd_ex.h
  • PCD_EP_TX_CNT : stm32f3xx_hal_pcd_ex.h
  • PCD_EP_TYPE_BULK : stm32f3xx_hal_pcd.h
  • PCD_EP_TYPE_CTRL : stm32f3xx_hal_pcd.h
  • PCD_EP_TYPE_INTR : stm32f3xx_hal_pcd.h
  • PCD_EP_TYPE_ISOC : stm32f3xx_hal_pcd.h
  • PCD_FreeUserBuffer : stm32f3xx_hal_pcd.h
  • PCD_GET_DB_DIR : stm32f3xx_hal_pcd.h
  • PCD_GET_ENDPOINT : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_ADDRESS : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_DBUF0_ADDR : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_DBUF0_CNT : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_DBUF1_ADDR : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_DBUF1_CNT : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_RX_ADDRESS : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_RX_CNT : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_RX_STALL_STATUS : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_RX_STATUS : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_TX_ADDRESS : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_TX_CNT : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_TX_STALL_STATUS : stm32f3xx_hal_pcd.h
  • PCD_GET_EP_TX_STATUS : stm32f3xx_hal_pcd.h
  • PCD_GET_EPTYPE : stm32f3xx_hal_pcd.h
  • PCD_PHY_EMBEDDED : stm32f3xx_hal_pcd.h
  • PCD_RX_DTOG : stm32f3xx_hal_pcd.h
  • PCD_SET_ENDPOINT : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_ADDRESS : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_CNT_RX_REG : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_DBUF : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_DBUF0_ADDR : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_DBUF0_CNT : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_DBUF1_ADDR : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_DBUF1_CNT : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_DBUF_ADDR : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_DBUF_CNT : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_KIND : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_RX_ADDRESS : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_RX_CNT : stm32f3xx_hal_pcd_ex.h
  • PCD_SET_EP_RX_DBUF0_CNT : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_RX_STATUS : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_RX_VALID : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_TX_ADDRESS : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_TX_CNT : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_TX_STATUS : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_TX_VALID : stm32f3xx_hal_pcd.h
  • PCD_SET_EP_TXRX_STATUS : stm32f3xx_hal_pcd.h
  • PCD_SET_EPTYPE : stm32f3xx_hal_pcd.h
  • PCD_SET_OUT_STATUS : stm32f3xx_hal_pcd.h
  • PCD_SNG_BUF : stm32f3xx_hal_pcd.h
  • PCD_SPEED_FULL : stm32f3xx_hal_pcd.h
  • PCD_SPEED_HIGH : stm32f3xx_hal_pcd.h
  • PCD_TX_DTOG : stm32f3xx_hal_pcd.h
  • PLL_TIMEOUT_VALUE : stm32f3xx_hal_rcc.h
  • PREFETCH_ENABLE : stm32f3xx_hal_conf.h
  • PVD_FALLING_EDGE : stm32f3xx_hal_pwr_ex.c
  • PVD_MODE_EVT : stm32f3xx_hal_pwr_ex.c
  • PVD_MODE_IT : stm32f3xx_hal_pwr_ex.c
  • PVD_RISING_EDGE : stm32f3xx_hal_pwr_ex.c
  • PWR_EXTI_LINE_PVD : stm32f3xx_hal_pwr_ex.h
  • PWR_FLAG_PVDO : stm32f3xx_hal_pwr.h
  • PWR_FLAG_SB : stm32f3xx_hal_pwr.h
  • PWR_FLAG_VREFINTRDY : stm32f3xx_hal_pwr.h
  • PWR_FLAG_WU : stm32f3xx_hal_pwr.h
  • PWR_LOWPOWERREGULATOR_ON : stm32f3xx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32f3xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_FALLING : stm32f3xx_hal_pwr_ex.h
  • PWR_PVD_MODE_EVENT_RISING : stm32f3xx_hal_pwr_ex.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32f3xx_hal_pwr_ex.h
  • PWR_PVD_MODE_IT_FALLING : stm32f3xx_hal_pwr_ex.h
  • PWR_PVD_MODE_IT_RISING : stm32f3xx_hal_pwr_ex.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32f3xx_hal_pwr_ex.h
  • PWR_PVD_MODE_NORMAL : stm32f3xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_0 : stm32f3xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_1 : stm32f3xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_2 : stm32f3xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_3 : stm32f3xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_4 : stm32f3xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_5 : stm32f3xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_6 : stm32f3xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_7 : stm32f3xx_hal_pwr_ex.h
  • PWR_SDADC_ANALOG1 : stm32f3xx_hal_pwr_ex.h
  • PWR_SDADC_ANALOG2 : stm32f3xx_hal_pwr_ex.h
  • PWR_SDADC_ANALOG3 : stm32f3xx_hal_pwr_ex.h
  • PWR_SLEEPENTRY_WFE : stm32f3xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32f3xx_hal_pwr.h
  • PWR_STOPENTRY_WFE : stm32f3xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32f3xx_hal_pwr.h
  • PWR_WAKEUP_PIN1 : stm32f3xx_hal_pwr.h
  • PWR_WAKEUP_PIN2 : stm32f3xx_hal_pwr.h
  • PWR_WAKEUP_PIN3 : stm32f3xx_hal_pwr.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
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  • r
  • s
  • t
  • u
  • v
  • w

- r -

  • RCC_ADC1PCLK2_DIV2 : stm32f3xx_hal_rcc_ex.h
  • RCC_ADC1PCLK2_DIV4 : stm32f3xx_hal_rcc_ex.h
  • RCC_ADC1PCLK2_DIV6 : stm32f3xx_hal_rcc_ex.h
  • RCC_ADC1PCLK2_DIV8 : stm32f3xx_hal_rcc_ex.h
  • RCC_BDCR_BDRST_BB : stm32f3xx_hal_rcc.h
  • RCC_BDCR_LSEBYP_BB : stm32f3xx_hal_rcc.h
  • RCC_BDCR_LSEON_BB : stm32f3xx_hal_rcc.h
  • RCC_BDCR_OFFSET : stm32f3xx_hal_rcc.h
  • RCC_BDCR_OFFSET_BB : stm32f3xx_hal_rcc.h
  • RCC_BDCR_RTCEN_BB : stm32f3xx_hal_rcc.h
  • RCC_BDRST_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_CECCLKSOURCE_HSI : stm32f3xx_hal_rcc_ex.h
  • RCC_CECCLKSOURCE_LSE : stm32f3xx_hal_rcc_ex.h
  • RCC_CFGR_HPRE_BITNUMBER : stm32f3xx_hal_rcc.c
  • RCC_CFGR_OFFSET : stm32f3xx_hal_rcc.h
  • RCC_CFGR_OFFSET_BB : stm32f3xx_hal_rcc.h
  • RCC_CFGR_PPRE1_BITNUMBER : stm32f3xx_hal_rcc.c
  • RCC_CFGR_PPRE2_BITNUMBER : stm32f3xx_hal_rcc.c
  • RCC_CIR_BYTE1_ADDRESS : stm32f3xx_hal_rcc.h
  • RCC_CIR_BYTE2_ADDRESS : stm32f3xx_hal_rcc.h
  • RCC_CIR_OFFSET : stm32f3xx_hal_rcc.h
  • RCC_CIR_OFFSET_BB : stm32f3xx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK : stm32f3xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32f3xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32f3xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32f3xx_hal_rcc.h
  • RCC_CR_BYTE2_ADDRESS : stm32f3xx_hal_rcc.h
  • RCC_CR_CSSON_BB : stm32f3xx_hal_rcc.h
  • RCC_CR_HSEON_BB : stm32f3xx_hal_rcc.h
  • RCC_CR_HSION_BB : stm32f3xx_hal_rcc.h
  • RCC_CR_OFFSET : stm32f3xx_hal_rcc.h
  • RCC_CR_OFFSET_BB : stm32f3xx_hal_rcc.h
  • RCC_CR_PLLON_BB : stm32f3xx_hal_rcc.h
  • RCC_CSR_LSION_BB : stm32f3xx_hal_rcc.h
  • RCC_CSR_OFFSET : stm32f3xx_hal_rcc.h
  • RCC_CSR_OFFSET_BB : stm32f3xx_hal_rcc.h
  • RCC_CSR_RMVF_BB : stm32f3xx_hal_rcc.h
  • RCC_CSSON_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_DBP_TIMEOUT_VALUE : stm32f3xx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32f3xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32f3xx_hal_rcc.h
  • RCC_FLAG_IWDGRST : stm32f3xx_hal_rcc.h
  • RCC_FLAG_LPWRRST : stm32f3xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32f3xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32f3xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32f3xx_hal_rcc.h
  • RCC_FLAG_OBLRST : stm32f3xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32f3xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32f3xx_hal_rcc.h
  • RCC_FLAG_PORRST : stm32f3xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32f3xx_hal_rcc.h
  • RCC_FLAG_V18PWRRST : stm32f3xx_hal_rcc.h
  • RCC_FLAG_WWDGRST : stm32f3xx_hal_rcc.h
  • RCC_HCLK_DIV1 : stm32f3xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32f3xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32f3xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32f3xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32f3xx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32f3xx_hal_rcc.h
  • RCC_HSE_OFF : stm32f3xx_hal_rcc.h
  • RCC_HSE_ON : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV1 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV10 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV11 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV12 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV13 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV14 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV15 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV16 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV2 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV3 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV4 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV5 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV6 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV7 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV8 : stm32f3xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV9 : stm32f3xx_hal_rcc.h
  • RCC_HSEON_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_HSI_OFF : stm32f3xx_hal_rcc.h
  • RCC_HSI_ON : stm32f3xx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32f3xx_hal_rcc.h
  • RCC_HSION_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_I2C1CLKSOURCE_HSI : stm32f3xx_hal_rcc.h
  • RCC_I2C1CLKSOURCE_SYSCLK : stm32f3xx_hal_rcc.h
  • RCC_I2C2CLKSOURCE_HSI : stm32f3xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_SYSCLK : stm32f3xx_hal_rcc_ex.h
  • RCC_IT_CSS : stm32f3xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32f3xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32f3xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32f3xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32f3xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32f3xx_hal_rcc.h
  • RCC_LSE_BYPASS : stm32f3xx_hal_rcc.h
  • RCC_LSE_OFF : stm32f3xx_hal_rcc.h
  • RCC_LSE_ON : stm32f3xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32f3xx_hal_rcc.h
  • RCC_LSEBYP_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_LSEDRIVE_HIGH : stm32f3xx_hal_rcc_ex.h
  • RCC_LSEDRIVE_LOW : stm32f3xx_hal_rcc_ex.h
  • RCC_LSEDRIVE_MEDIUMHIGH : stm32f3xx_hal_rcc_ex.h
  • RCC_LSEDRIVE_MEDIUMLOW : stm32f3xx_hal_rcc_ex.h
  • RCC_LSEON_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_LSI_OFF : stm32f3xx_hal_rcc.h
  • RCC_LSI_ON : stm32f3xx_hal_rcc.h
  • RCC_LSION_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_MCO : stm32f3xx_hal_rcc.h
  • RCC_MCO1 : stm32f3xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32f3xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_HSI : stm32f3xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_LSE : stm32f3xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_LSI : stm32f3xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_NOCLOCK : stm32f3xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_PLLCLK_DIV2 : stm32f3xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_SYSCLK : stm32f3xx_hal_rcc_ex.h
  • RCC_MCODIV_1 : stm32f3xx_hal_rcc_ex.h
  • RCC_OFFSET : stm32f3xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32f3xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32f3xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32f3xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32f3xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32f3xx_hal_rcc.h
  • RCC_PERIPHCLK_ADC1 : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_CEC : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C1 : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C2 : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SDADC : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART1 : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART2 : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART3 : stm32f3xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USB : stm32f3xx_hal_rcc_ex.h
  • RCC_PLL_MUL10 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL11 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL12 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL13 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL14 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL15 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL16 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL2 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL3 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL4 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL5 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL6 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL7 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL8 : stm32f3xx_hal_rcc.h
  • RCC_PLL_MUL9 : stm32f3xx_hal_rcc.h
  • RCC_PLL_NONE : stm32f3xx_hal_rcc.h
  • RCC_PLL_OFF : stm32f3xx_hal_rcc.h
  • RCC_PLL_ON : stm32f3xx_hal_rcc.h
  • RCC_PLLON_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32f3xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32f3xx_hal_rcc.h
  • RCC_POSITION_HPRE : stm32f3xx_ll_rcc.h
  • RCC_POSITION_HSICAL : stm32f3xx_ll_rcc.h
  • RCC_POSITION_HSITRIM : stm32f3xx_ll_rcc.h
  • RCC_POSITION_PLLMUL : stm32f3xx_ll_rcc.h
  • RCC_POSITION_PPRE1 : stm32f3xx_ll_rcc.h
  • RCC_POSITION_PPRE2 : stm32f3xx_ll_rcc.h
  • RCC_POSITION_TIM15SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_TIM16SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_TIM17SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_TIM1SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_TIM20SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_TIM2SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_TIM34SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_TIM8SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_USART1SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_USART2SW : stm32f3xx_ll_rcc.h
  • RCC_POSITION_USART3SW : stm32f3xx_ll_rcc.h
  • RCC_RMVF_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV32 : stm32f3xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32f3xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32f3xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_NO_CLK : stm32f3xx_hal_rcc.h
  • RCC_RTCEN_BIT_NUMBER : stm32f3xx_hal_rcc.h
  • RCC_SDADCSYSCLK_DIV1 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV10 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV12 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV14 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV16 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV2 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV20 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV24 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV28 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV32 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV36 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV4 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV40 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV44 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV48 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV6 : stm32f3xx_hal_rcc_ex.h
  • RCC_SDADCSYSCLK_DIV8 : stm32f3xx_hal_rcc_ex.h
  • RCC_SYSCLK_DIV1 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32f3xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32f3xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32f3xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32f3xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32f3xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32f3xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32f3xx_hal_rcc.h
  • RCC_USART1CLKSOURCE_HSI : stm32f3xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_LSE : stm32f3xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PCLK2 : stm32f3xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_SYSCLK : stm32f3xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_HSI : stm32f3xx_hal_rcc.h
  • RCC_USART2CLKSOURCE_LSE : stm32f3xx_hal_rcc.h
  • RCC_USART2CLKSOURCE_PCLK1 : stm32f3xx_hal_rcc.h
  • RCC_USART2CLKSOURCE_SYSCLK : stm32f3xx_hal_rcc.h
  • RCC_USART3CLKSOURCE_HSI : stm32f3xx_hal_rcc.h
  • RCC_USART3CLKSOURCE_LSE : stm32f3xx_hal_rcc.h
  • RCC_USART3CLKSOURCE_PCLK1 : stm32f3xx_hal_rcc.h
  • RCC_USART3CLKSOURCE_SYSCLK : stm32f3xx_hal_rcc.h
  • RCC_USBCLKSOURCE_PLL : stm32f3xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL_DIV1_5 : stm32f3xx_hal_rcc_ex.h
  • RISING_EDGE : stm32f3xx_hal_gpio.c
  • RTC_ALARM_A : stm32f3xx_hal_rtc.h
  • RTC_ALARM_B : stm32f3xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32f3xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32f3xx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32f3xx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32f3xx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32f3xx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32f3xx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32f3xx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32f3xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32f3xx_hal_rtc.h
  • RTC_ASYNCH_PRESC_DEFAULT : stm32f3xx_ll_rtc.c
  • RTC_BKP_DR0 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR11 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR12 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR13 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR14 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR15 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR16 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR17 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR18 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR19 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR20 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR21 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR22 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR23 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR24 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR25 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR26 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR27 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR28 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR29 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR30 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR31 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32f3xx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32f3xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_1HZ : stm32f3xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32f3xx_hal_rtc_ex.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32f3xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32f3xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32f3xx_hal_rtc.h
  • RTC_DR_RESERVED_MASK : stm32f3xx_hal_rtc.h
  • RTC_EXTI_LINE_ALARM_EVENT : stm32f3xx_hal_rtc.h
  • RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT : stm32f3xx_hal_rtc.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32f3xx_hal_rtc.h
  • RTC_FLAG_ALRAF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_INITF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_INITS : stm32f3xx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_TAMP1F : stm32f3xx_hal_rtc.h
  • RTC_FLAG_TAMP2F : stm32f3xx_hal_rtc.h
  • RTC_FLAG_TAMP3F : stm32f3xx_hal_rtc.h
  • RTC_FLAG_TSF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32f3xx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32f3xx_hal_rtc.h
  • RTC_FLAGS_MASK : stm32f3xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32f3xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32f3xx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32f3xx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32f3xx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32f3xx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32f3xx_hal_rtc.h
  • RTC_INIT_MASK : stm32f3xx_hal_rtc.h , stm32f3xx_ll_rtc.h
  • RTC_INITMODE_TIMEOUT : stm32f3xx_ll_rtc.c
  • RTC_IT_ALRA : stm32f3xx_hal_rtc.h
  • RTC_IT_ALRB : stm32f3xx_hal_rtc.h
  • RTC_IT_TAMP : stm32f3xx_hal_rtc.h
  • RTC_IT_TAMP1 : stm32f3xx_hal_rtc.h
  • RTC_IT_TAMP2 : stm32f3xx_hal_rtc.h
  • RTC_IT_TAMP3 : stm32f3xx_hal_rtc.h
  • RTC_IT_TS : stm32f3xx_hal_rtc.h
  • RTC_IT_WUT : stm32f3xx_hal_rtc.h
  • RTC_MONTH_APRIL : stm32f3xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32f3xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32f3xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32f3xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32f3xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32f3xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32f3xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32f3xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32f3xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32f3xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32f3xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32f3xx_hal_rtc.h
  • RTC_OFFSET_DAY : stm32f3xx_ll_rtc.h
  • RTC_OFFSET_HOUR : stm32f3xx_ll_rtc.h
  • RTC_OFFSET_MINUTE : stm32f3xx_ll_rtc.h
  • RTC_OFFSET_MONTH : stm32f3xx_ll_rtc.h
  • RTC_OFFSET_WEEKDAY : stm32f3xx_ll_rtc.h
  • RTC_OUTPUT_ALARMA : stm32f3xx_hal_rtc_ex.h
  • RTC_OUTPUT_ALARMB : stm32f3xx_hal_rtc_ex.h
  • RTC_OUTPUT_DISABLE : stm32f3xx_hal_rtc_ex.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32f3xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32f3xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32f3xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32f3xx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32f3xx_hal_rtc_ex.h
  • RTC_RSF_MASK : stm32f3xx_hal_rtc.h , stm32f3xx_ll_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32f3xx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32f3xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32f3xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32f3xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32f3xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32f3xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32f3xx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32f3xx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32f3xx_hal_rtc.h
  • RTC_SYNCH_PRESC_DEFAULT : stm32f3xx_ll_rtc.c
  • RTC_SYNCHRO_TIMEOUT : stm32f3xx_ll_rtc.c
  • RTC_TAMPER_1 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPER_3 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32f3xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32f3xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32f3xx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32f3xx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32f3xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32f3xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32f3xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32f3xx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32f3xx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32f3xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32f3xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32f3xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32f3xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32f3xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32f3xx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32f3xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32f3xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32f3xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32f3xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32f3xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32f3xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32f3xx_hal_rtc.h
  • RTC_WRITE_PROTECTION_DISABLE : stm32f3xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_1 : stm32f3xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_2 : stm32f3xx_ll_rtc.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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- s -

  • SDADC_CALIBRATION_SEQ_1 : stm32f3xx_hal_sdadc.h
  • SDADC_CALIBRATION_SEQ_2 : stm32f3xx_hal_sdadc.h
  • SDADC_CALIBRATION_SEQ_3 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_0 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_1 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_2 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_3 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_4 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_5 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_6 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_7 : stm32f3xx_hal_sdadc.h
  • SDADC_CHANNEL_8 : stm32f3xx_hal_sdadc.h
  • SDADC_COMMON_MODE_VDDA : stm32f3xx_hal_sdadc.h
  • SDADC_COMMON_MODE_VDDA_2 : stm32f3xx_hal_sdadc.h
  • SDADC_COMMON_MODE_VSSA : stm32f3xx_hal_sdadc.h
  • SDADC_CONF_INDEX_0 : stm32f3xx_hal_sdadc.h
  • SDADC_CONF_INDEX_1 : stm32f3xx_hal_sdadc.h
  • SDADC_CONF_INDEX_2 : stm32f3xx_hal_sdadc.h
  • SDADC_CONFREG_OFFSET : stm32f3xx_hal_sdadc.c
  • SDADC_CONTINUOUS_CONV_OFF : stm32f3xx_hal_sdadc.h
  • SDADC_CONTINUOUS_CONV_ON : stm32f3xx_hal_sdadc.h
  • SDADC_ERROR_DMA : stm32f3xx_hal_sdadc.h
  • SDADC_ERROR_INJECTED_OVERRUN : stm32f3xx_hal_sdadc.h
  • SDADC_ERROR_NONE : stm32f3xx_hal_sdadc.h
  • SDADC_ERROR_REGULAR_OVERRUN : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_BOTH_EDGES : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_EXTI11 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_EXTI15 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_FALLING_EDGE : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_RISING_EDGE : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM12_CC1 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM12_CC2 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM13_CC1 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM14_CC1 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM15_CC2 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM16_CC1 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM17_CC1 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM19_CC2 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM19_CC3 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM19_CC4 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM2_CC3 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM2_CC4 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM3_CC1 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM3_CC2 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM3_CC3 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM4_CC1 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM4_CC2 : stm32f3xx_hal_sdadc.h
  • SDADC_EXT_TRIG_TIM4_CC3 : stm32f3xx_hal_sdadc.h
  • SDADC_EXTERNAL_TRIGGER : stm32f3xx_hal_sdadc.h
  • SDADC_FAST_CONV_DISABLE : stm32f3xx_hal_sdadc.h
  • SDADC_FAST_CONV_ENABLE : stm32f3xx_hal_sdadc.h
  • SDADC_FLAG_EOCAL : stm32f3xx_hal_sdadc.h
  • SDADC_FLAG_JEOC : stm32f3xx_hal_sdadc.h
  • SDADC_FLAG_JOVR : stm32f3xx_hal_sdadc.h
  • SDADC_FLAG_REOC : stm32f3xx_hal_sdadc.h
  • SDADC_FLAG_ROVR : stm32f3xx_hal_sdadc.h
  • SDADC_GAIN_1 : stm32f3xx_hal_sdadc.h
  • SDADC_GAIN_16 : stm32f3xx_hal_sdadc.h
  • SDADC_GAIN_1_2 : stm32f3xx_hal_sdadc.h
  • SDADC_GAIN_2 : stm32f3xx_hal_sdadc.h
  • SDADC_GAIN_32 : stm32f3xx_hal_sdadc.h
  • SDADC_GAIN_4 : stm32f3xx_hal_sdadc.h
  • SDADC_GAIN_8 : stm32f3xx_hal_sdadc.h
  • SDADC_INJECTED_DELAY : stm32f3xx_hal_sdadc.h
  • SDADC_INJECTED_DELAY_NONE : stm32f3xx_hal_sdadc.h
  • SDADC_INPUT_MODE_DIFF : stm32f3xx_hal_sdadc.h
  • SDADC_INPUT_MODE_SE_OFFSET : stm32f3xx_hal_sdadc.h
  • SDADC_INPUT_MODE_SE_ZERO_REFERENCE : stm32f3xx_hal_sdadc.h
  • SDADC_IT_EOCAL : stm32f3xx_hal_sdadc.h
  • SDADC_IT_JEOC : stm32f3xx_hal_sdadc.h
  • SDADC_IT_JOVR : stm32f3xx_hal_sdadc.h
  • SDADC_IT_REOC : stm32f3xx_hal_sdadc.h
  • SDADC_IT_ROVR : stm32f3xx_hal_sdadc.h
  • SDADC_JDATAR_CH_OFFSET : stm32f3xx_hal_sdadc.c
  • SDADC_LOWPOWER_NONE : stm32f3xx_hal_sdadc.h
  • SDADC_LOWPOWER_POWERDOWN : stm32f3xx_hal_sdadc.h
  • SDADC_LOWPOWER_STANDBY : stm32f3xx_hal_sdadc.h
  • SDADC_LSB_MASK : stm32f3xx_hal_sdadc.c
  • SDADC_MSB_MASK : stm32f3xx_hal_sdadc.c
  • SDADC_MULTIMODE_SDADC1_SDADC2 : stm32f3xx_hal_sdadc.h
  • SDADC_MULTIMODE_SDADC1_SDADC3 : stm32f3xx_hal_sdadc.h
  • SDADC_SLOW_CLOCK_DISABLE : stm32f3xx_hal_sdadc.h
  • SDADC_SLOW_CLOCK_ENABLE : stm32f3xx_hal_sdadc.h
  • SDADC_SOFTWARE_TRIGGER : stm32f3xx_hal_sdadc.h
  • SDADC_SYNCHRONOUS_TRIGGER : stm32f3xx_hal_sdadc.h
  • SDADC_TIMEOUT : stm32f3xx_hal_sdadc.c
  • SDADC_VREF_EXT : stm32f3xx_hal_sdadc.h
  • SDADC_VREF_VDDA : stm32f3xx_hal_sdadc.h
  • SDADC_VREF_VREFINT1 : stm32f3xx_hal_sdadc.h
  • SDADC_VREF_VREFINT2 : stm32f3xx_hal_sdadc.h
  • SlaveAddr_MSK : stm32f3xx_hal_i2c.c
  • SlaveAddr_SHIFT : stm32f3xx_hal_i2c.c
  • SMARTCARD_ADVFEATURE_DATAINV_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINV_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINVERT_INIT : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_INIT : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_NO_INIT : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINVERT_INIT : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_INIT : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINVERT_INIT : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLEAR_EOBF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLEAR_FEF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLEAR_IDLEF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLEAR_NEF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLEAR_OREF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLEAR_PEF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLEAR_RTOF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CLEAR_TCF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_CR3_SCARCNT_LSB_POS : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_BUSY : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_EOBF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_FE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_IDLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_NE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_ORE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_PE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_REACK : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_RTOF : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_RXNE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_TC : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_TEACK : stm32f3xx_hal_smartcard.h
  • SMARTCARD_FLAG_TXE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_GETCLOCKSOURCE : stm32f3xx_hal_smartcard_ex.h
  • SMARTCARD_GTPR_GT_LSB_POS : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_EOB : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_ERR : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_FE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_IDLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_MASK : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_NE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_ORE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_PE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_RTO : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_RXNE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_TC : stm32f3xx_hal_smartcard.h
  • SMARTCARD_IT_TXE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32f3xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32f3xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32f3xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32f3xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32f3xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32f3xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32f3xx_hal_smartcard.h
  • SMARTCARD_RTOR_BLEN_LSB_POS : stm32f3xx_hal_smartcard.h
  • SMARTCARD_RXDATA_FLUSH_REQUEST : stm32f3xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_0_5 : stm32f3xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32f3xx_hal_smartcard.h
  • SMARTCARD_TEACK_REACK_TIMEOUT : stm32f3xx_hal_smartcard.c
  • SMARTCARD_TIMEOUT_DISABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_ENABLE : stm32f3xx_hal_smartcard.h
  • SMARTCARD_TXDATA_FLUSH_REQUEST : stm32f3xx_hal_smartcard.h
  • SMARTCARD_WORDLENGTH_9B : stm32f3xx_hal_smartcard.h
  • SMBUS_ADDRESSINGMODE_10BIT : stm32f3xx_hal_smbus.h
  • SMBUS_ADDRESSINGMODE_7BIT : stm32f3xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_DISABLE : stm32f3xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_ENABLE : stm32f3xx_hal_smbus.h
  • SMBUS_AUTOEND_MODE : stm32f3xx_hal_smbus.h
  • SMBUS_CHECK_FLAG : stm32f3xx_hal_smbus.h
  • SMBUS_DUALADDRESS_DISABLE : stm32f3xx_hal_smbus.h
  • SMBUS_DUALADDRESS_ENABLE : stm32f3xx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_NO_PEC : stm32f3xx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC : stm32f3xx_hal_smbus.h
  • SMBUS_FIRST_FRAME : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_ADDR : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_AF : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_ALERT : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_ARLO : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_BERR : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_BUSY : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_DIR : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_MASK : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_OVR : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_PECERR : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_RXNE : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_STOPF : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_TC : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_TCR : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_TIMEOUT : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_TXE : stm32f3xx_hal_smbus.h
  • SMBUS_FLAG_TXIS : stm32f3xx_hal_smbus.h
  • SMBUS_GENERALCALL_DISABLE : stm32f3xx_hal_smbus.h
  • SMBUS_GENERALCALL_ENABLE : stm32f3xx_hal_smbus.h
  • SMBUS_GENERATE_START : stm32f3xx_hal_smbus.h
  • SMBUS_GENERATE_START_READ : stm32f3xx_hal_smbus.h
  • SMBUS_GENERATE_START_WRITE : stm32f3xx_hal_smbus.h
  • SMBUS_GENERATE_STOP : stm32f3xx_hal_smbus.h
  • SMBUS_GET_ADDR_MATCH : stm32f3xx_hal_smbus.h
  • SMBUS_GET_ALERT_ENABLED : stm32f3xx_hal_smbus.h
  • SMBUS_GET_DIR : stm32f3xx_hal_smbus.h
  • SMBUS_GET_ISR_REG : stm32f3xx_hal_smbus.h
  • SMBUS_GET_PEC_MODE : stm32f3xx_hal_smbus.h
  • SMBUS_GET_STOP_MODE : stm32f3xx_hal_smbus.h
  • SMBUS_IT_ADDR : stm32f3xx_hal_smbus.h
  • SMBUS_IT_ADDRI : stm32f3xx_hal_smbus.h
  • SMBUS_IT_ALERT : stm32f3xx_hal_smbus.h
  • SMBUS_IT_ERRI : stm32f3xx_hal_smbus.h
  • SMBUS_IT_NACKI : stm32f3xx_hal_smbus.h
  • SMBUS_IT_RX : stm32f3xx_hal_smbus.h
  • SMBUS_IT_RXI : stm32f3xx_hal_smbus.h
  • SMBUS_IT_STOPI : stm32f3xx_hal_smbus.h
  • SMBUS_IT_TCI : stm32f3xx_hal_smbus.h
  • SMBUS_IT_TX : stm32f3xx_hal_smbus.h
  • SMBUS_IT_TXI : stm32f3xx_hal_smbus.h
  • SMBUS_LAST_FRAME_NO_PEC : stm32f3xx_hal_smbus.h
  • SMBUS_LAST_FRAME_WITH_PEC : stm32f3xx_hal_smbus.h
  • SMBUS_NEXT_FRAME : stm32f3xx_hal_smbus.h
  • SMBUS_NO_STARTSTOP : stm32f3xx_hal_smbus.h
  • SMBUS_NOSTRETCH_DISABLE : stm32f3xx_hal_smbus.h
  • SMBUS_NOSTRETCH_ENABLE : stm32f3xx_hal_smbus.h
  • SMBUS_OA2_MASK01 : stm32f3xx_hal_smbus.h
  • SMBUS_OA2_MASK02 : stm32f3xx_hal_smbus.h
  • SMBUS_OA2_MASK03 : stm32f3xx_hal_smbus.h
  • SMBUS_OA2_MASK04 : stm32f3xx_hal_smbus.h
  • SMBUS_OA2_MASK05 : stm32f3xx_hal_smbus.h
  • SMBUS_OA2_MASK06 : stm32f3xx_hal_smbus.h
  • SMBUS_OA2_MASK07 : stm32f3xx_hal_smbus.h
  • SMBUS_OA2_NOMASK : stm32f3xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_NO_PEC : stm32f3xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC : stm32f3xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_NO_PEC : stm32f3xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_WITH_PEC : stm32f3xx_hal_smbus.h
  • SMBUS_PEC_DISABLE : stm32f3xx_hal_smbus.h
  • SMBUS_PEC_ENABLE : stm32f3xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_HOST : stm32f3xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE : stm32f3xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP : stm32f3xx_hal_smbus.h
  • SMBUS_RELOAD_MODE : stm32f3xx_hal_smbus.h
  • SMBUS_RESET_CR1 : stm32f3xx_hal_smbus.h
  • SMBUS_RESET_CR2 : stm32f3xx_hal_smbus.h
  • SMBUS_SENDPEC_MODE : stm32f3xx_hal_smbus.h
  • SMBUS_SOFTEND_MODE : stm32f3xx_hal_smbus.h
  • SPI_1LINE_RX : stm32f3xx_hal_spi.h
  • SPI_1LINE_TX : stm32f3xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_128 : stm32f3xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32f3xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32f3xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32f3xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32f3xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32f3xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32f3xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32f3xx_hal_spi.h
  • SPI_CR1_CLEAR_MASK : stm32f3xx_ll_spi.c
  • SPI_CRC_LENGTH_16BIT : stm32f3xx_hal_spi.h
  • SPI_CRC_LENGTH_8BIT : stm32f3xx_hal_spi.h
  • SPI_CRC_LENGTH_DATASIZE : stm32f3xx_hal_spi.h
  • SPI_CRCCALCULATION_DISABLE : stm32f3xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_10BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_11BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_12BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_13BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_14BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_15BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_4BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_5BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_6BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_7BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32f3xx_hal_spi.h
  • SPI_DATASIZE_9BIT : stm32f3xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32f3xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32f3xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32f3xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32f3xx_hal_spi.h
  • SPI_FIFO_SIZE : stm32f3xx_hal_spi_ex.c
  • SPI_FIRSTBIT_LSB : stm32f3xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32f3xx_hal_spi.h
  • SPI_FLAG_BSY : stm32f3xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32f3xx_hal_spi.h
  • SPI_FLAG_FRE : stm32f3xx_hal_spi.h
  • SPI_FLAG_FRLVL : stm32f3xx_hal_spi.h
  • SPI_FLAG_FTLVL : stm32f3xx_hal_spi.h
  • SPI_FLAG_MODF : stm32f3xx_hal_spi.h
  • SPI_FLAG_OVR : stm32f3xx_hal_spi.h
  • SPI_FLAG_RXNE : stm32f3xx_hal_spi.h
  • SPI_FLAG_TXE : stm32f3xx_hal_spi.h
  • SPI_FRLVL_EMPTY : stm32f3xx_hal_spi.h
  • SPI_FRLVL_FULL : stm32f3xx_hal_spi.h
  • SPI_FRLVL_HALF_FULL : stm32f3xx_hal_spi.h
  • SPI_FRLVL_QUARTER_FULL : stm32f3xx_hal_spi.h
  • SPI_FTLVL_EMPTY : stm32f3xx_hal_spi.h
  • SPI_FTLVL_FULL : stm32f3xx_hal_spi.h
  • SPI_FTLVL_HALF_FULL : stm32f3xx_hal_spi.h
  • SPI_FTLVL_QUARTER_FULL : stm32f3xx_hal_spi.h
  • SPI_IT_ERR : stm32f3xx_hal_spi.h
  • SPI_IT_RXNE : stm32f3xx_hal_spi.h
  • SPI_IT_TXE : stm32f3xx_hal_spi.h
  • SPI_MODE_MASTER : stm32f3xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32f3xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32f3xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32f3xx_hal_spi.h
  • SPI_NSS_PULSE_DISABLE : stm32f3xx_hal_spi.h
  • SPI_NSS_PULSE_ENABLE : stm32f3xx_hal_spi.h
  • SPI_NSS_SOFT : stm32f3xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32f3xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32f3xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32f3xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32f3xx_hal_spi.h
  • SPI_RESET_CRC : stm32f3xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD : stm32f3xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_HF : stm32f3xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_QF : stm32f3xx_hal_spi.h
  • SPI_TIMODE_DISABLE : stm32f3xx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32f3xx_hal_spi.h
  • SYSCFG_FASTMODEPLUS_PB6 : stm32f3xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB7 : stm32f3xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB8 : stm32f3xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB9 : stm32f3xx_hal.h
  • SYSCFG_MASK_TIM_BREAK : stm32f3xx_ll_system.h
  • SYSCFG_OFFSET : stm32f3xx_hal.h
  • SYSCFG_OFFSET_CFGR1 : stm32f3xx_ll_system.h
  • SYSCFG_OFFSET_CFGR3 : stm32f3xx_ll_system.h
  • SYSTICK_CLKSOURCE_HCLK : stm32f3xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32f3xx_hal_cortex.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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- t -

  • TEMPSENSOR_CAL1_ADDR : stm32f3xx_ll_adc.h
  • TEMPSENSOR_CAL1_TEMP : stm32f3xx_ll_adc.h
  • TEMPSENSOR_CAL2_ADDR : stm32f3xx_ll_adc.h
  • TEMPSENSOR_CAL2_TEMP : stm32f3xx_ll_adc.h
  • TEMPSENSOR_CAL_VREFANALOG : stm32f3xx_ll_adc.h
  • TICK_INT_PRIORITY : stm32f3xx_hal_conf.h
  • TIM14_OR_RMP_MASK : stm32f3xx_ll_tim.h
  • TIM16_OR_RMP_MASK : stm32f3xx_ll_tim.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32f3xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32f3xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_DISABLE : stm32f3xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_ENABLE : stm32f3xx_hal_tim.h
  • TIM_BREAK_DISABLE : stm32f3xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32f3xx_hal_tim.h
  • TIM_BREAKPOLARITY_HIGH : stm32f3xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32f3xx_hal_tim.h
  • TIM_CALC_DTS : stm32f3xx_ll_tim.h
  • TIM_CCER_CCxE_MASK : stm32f3xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32f3xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32f3xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32f3xx_hal_tim.h
  • TIM_CCxN_DISABLE : stm32f3xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32f3xx_hal_tim.h
  • TIM_CHANNEL_1 : stm32f3xx_hal_tim_ex.h
  • TIM_CHANNEL_2 : stm32f3xx_hal_tim_ex.h
  • TIM_CHANNEL_3 : stm32f3xx_hal_tim_ex.h
  • TIM_CHANNEL_4 : stm32f3xx_hal_tim_ex.h
  • TIM_CHANNEL_ALL : stm32f3xx_hal_tim_ex.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32f3xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32f3xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32f3xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32f3xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32f3xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32f3xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32f3xx_hal_tim_ex.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32f3xx_hal_tim_ex.h
  • TIM_CLOCKDIVISION_DIV1 : stm32f3xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32f3xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32f3xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32f3xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32f3xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32f3xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32f3xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32f3xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32f3xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32f3xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32f3xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32f3xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32f3xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32f3xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32f3xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32f3xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32f3xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32f3xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32f3xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32f3xx_hal_tim.h
  • TIM_DMA_CC1 : stm32f3xx_hal_tim.h
  • TIM_DMA_CC2 : stm32f3xx_hal_tim.h
  • TIM_DMA_CC3 : stm32f3xx_hal_tim.h
  • TIM_DMA_CC4 : stm32f3xx_hal_tim.h
  • TIM_DMA_COM : stm32f3xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32f3xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32f3xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32f3xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32f3xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32f3xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32f3xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32f3xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32f3xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32f3xx_hal_tim.h
  • TIM_DMABASE_ARR : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_BDTR : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CCER : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CCMR1 : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CCMR2 : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CCR1 : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CCR2 : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CCR3 : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CCR4 : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CNT : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CR1 : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_CR2 : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_DCR : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_DIER : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_EGR : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_OR : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_PSC : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_RCR : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_SMCR : stm32f3xx_hal_tim_ex.h
  • TIM_DMABASE_SR : stm32f3xx_hal_tim_ex.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32f3xx_hal_tim.h
  • TIM_ENCODERMODE_TI1 : stm32f3xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32f3xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32f3xx_hal_tim.h
  • TIM_ETRPOLARITY_INVERTED : stm32f3xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32f3xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32f3xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32f3xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32f3xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32f3xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32f3xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_CC1 : stm32f3xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_CC2 : stm32f3xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_CC3 : stm32f3xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_CC4 : stm32f3xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_COM : stm32f3xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_TRIGGER : stm32f3xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_UPDATE : stm32f3xx_hal_tim_ex.h
  • TIM_FLAG_BREAK : stm32f3xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32f3xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32f3xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32f3xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32f3xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32f3xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32f3xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32f3xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32f3xx_hal_tim.h
  • TIM_FLAG_COM : stm32f3xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32f3xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32f3xx_hal_tim.h
  • TIM_GET_CHANNEL_INDEX : stm32f3xx_ll_tim.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32f3xx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32f3xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32f3xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32f3xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32f3xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32f3xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32f3xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32f3xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32f3xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32f3xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32f3xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32f3xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32f3xx_hal_tim.h
  • TIM_IT_BREAK : stm32f3xx_hal_tim.h
  • TIM_IT_CC1 : stm32f3xx_hal_tim.h
  • TIM_IT_CC2 : stm32f3xx_hal_tim.h
  • TIM_IT_CC3 : stm32f3xx_hal_tim.h
  • TIM_IT_CC4 : stm32f3xx_hal_tim.h
  • TIM_IT_COM : stm32f3xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32f3xx_hal_tim.h
  • TIM_IT_UPDATE : stm32f3xx_hal_tim.h
  • TIM_LOCKLEVEL_1 : stm32f3xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32f3xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32f3xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32f3xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32f3xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32f3xx_hal_tim.h
  • TIM_OCFAST_DISABLE : stm32f3xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32f3xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32f3xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32f3xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32f3xx_hal_tim_ex.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32f3xx_hal_tim_ex.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32f3xx_hal_tim_ex.h
  • TIM_OCMODE_INACTIVE : stm32f3xx_hal_tim_ex.h
  • TIM_OCMODE_PWM1 : stm32f3xx_hal_tim_ex.h
  • TIM_OCMODE_PWM2 : stm32f3xx_hal_tim_ex.h
  • TIM_OCMODE_TIMING : stm32f3xx_hal_tim_ex.h
  • TIM_OCMODE_TOGGLE : stm32f3xx_hal_tim_ex.h
  • TIM_OCNIDLESTATE_RESET : stm32f3xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32f3xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32f3xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32f3xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32f3xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32f3xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32f3xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32f3xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32f3xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32f3xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32f3xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32f3xx_hal_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32f3xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32f3xx_hal_tim.h
  • TIM_SET_CAPTUREPOLARITY : stm32f3xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32f3xx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32f3xx_hal_tim_ex.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32f3xx_hal_tim_ex.h
  • TIM_SLAVEMODE_GATED : stm32f3xx_hal_tim_ex.h
  • TIM_SLAVEMODE_RESET : stm32f3xx_hal_tim_ex.h
  • TIM_SLAVEMODE_TRIGGER : stm32f3xx_hal_tim_ex.h
  • TIM_TI1SELECTION_CH1 : stm32f3xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32f3xx_hal_tim.h
  • TIM_TIM14_GPIO : stm32f3xx_hal_tim_ex.h
  • TIM_TIM14_HSE : stm32f3xx_hal_tim_ex.h
  • TIM_TIM14_MCO : stm32f3xx_hal_tim_ex.h
  • TIM_TIM14_RTC : stm32f3xx_hal_tim_ex.h
  • TIM_TIM2_ETH_PTP : stm32f3xx_hal_tim_ex.h
  • TIM_TIM2_TIM8_TRGO : stm32f3xx_hal_tim_ex.h
  • TIM_TIM2_USBFS_SOF : stm32f3xx_hal_tim_ex.h
  • TIM_TIM2_USBHS_SOF : stm32f3xx_hal_tim_ex.h
  • TIM_TRGO_ENABLE : stm32f3xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32f3xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32f3xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32f3xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32f3xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32f3xx_hal_tim.h
  • TIM_TRGO_RESET : stm32f3xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32f3xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32f3xx_hal_tim.h
  • TIM_TS_ETRF : stm32f3xx_hal_tim.h
  • TIM_TS_ITR0 : stm32f3xx_hal_tim.h
  • TIM_TS_ITR1 : stm32f3xx_hal_tim.h
  • TIM_TS_ITR2 : stm32f3xx_hal_tim.h
  • TIM_TS_ITR3 : stm32f3xx_hal_tim.h
  • TIM_TS_NONE : stm32f3xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32f3xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32f3xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32f3xx_hal_tim.h
  • TIMING_CLEAR_MASK : stm32f3xx_hal_i2c.c , stm32f3xx_hal_smbus.c
  • TIMx_OR_RMP_MASK : stm32f3xx_ll_tim.h
  • TIMx_OR_RMP_SHIFT : stm32f3xx_ll_tim.h
  • TSC_ACQ_MODE_NORMAL : stm32f3xx_hal_tsc.h
  • TSC_ACQ_MODE_SYNCHRO : stm32f3xx_hal_tsc.h
  • TSC_ALL_GROUPS : stm32f3xx_hal_tsc.h
  • TSC_ALL_GROUPS_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_CTPH_10CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_11CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_12CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_13CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_14CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_15CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_16CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_1CYCLE : stm32f3xx_hal_tsc.h
  • TSC_CTPH_2CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_3CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_4CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_5CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_6CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_7CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_8CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPH_9CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_10CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_11CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_12CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_13CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_14CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_15CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_16CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_1CYCLE : stm32f3xx_hal_tsc.h
  • TSC_CTPL_2CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_3CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_4CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_5CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_6CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_7CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_8CYCLES : stm32f3xx_hal_tsc.h
  • TSC_CTPL_9CYCLES : stm32f3xx_hal_tsc.h
  • TSC_FLAG_EOA : stm32f3xx_hal_tsc.h
  • TSC_FLAG_MCE : stm32f3xx_hal_tsc.h
  • TSC_GROUP1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP1_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_GROUP1_IDX : stm32f3xx_hal_tsc.h
  • TSC_GROUP1_IO1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP1_IO2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP1_IO3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP1_IO4 : stm32f3xx_hal_tsc.h
  • TSC_GROUP2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP2_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_GROUP2_IDX : stm32f3xx_hal_tsc.h
  • TSC_GROUP2_IO1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP2_IO2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP2_IO3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP2_IO4 : stm32f3xx_hal_tsc.h
  • TSC_GROUP3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP3_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_GROUP3_IDX : stm32f3xx_hal_tsc.h
  • TSC_GROUP3_IO1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP3_IO2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP3_IO3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP3_IO4 : stm32f3xx_hal_tsc.h
  • TSC_GROUP4 : stm32f3xx_hal_tsc.h
  • TSC_GROUP4_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_GROUP4_IDX : stm32f3xx_hal_tsc.h
  • TSC_GROUP4_IO1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP4_IO2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP4_IO3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP4_IO4 : stm32f3xx_hal_tsc.h
  • TSC_GROUP5 : stm32f3xx_hal_tsc.h
  • TSC_GROUP5_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_GROUP5_IDX : stm32f3xx_hal_tsc.h
  • TSC_GROUP5_IO1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP5_IO2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP5_IO3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP5_IO4 : stm32f3xx_hal_tsc.h
  • TSC_GROUP6 : stm32f3xx_hal_tsc.h
  • TSC_GROUP6_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_GROUP6_IDX : stm32f3xx_hal_tsc.h
  • TSC_GROUP6_IO1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP6_IO2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP6_IO3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP6_IO4 : stm32f3xx_hal_tsc.h
  • TSC_GROUP7 : stm32f3xx_hal_tsc.h
  • TSC_GROUP7_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_GROUP7_IDX : stm32f3xx_hal_tsc.h
  • TSC_GROUP7_IO1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP7_IO2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP7_IO3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP7_IO4 : stm32f3xx_hal_tsc.h
  • TSC_GROUP8 : stm32f3xx_hal_tsc.h
  • TSC_GROUP8_ALL_IOS : stm32f3xx_hal_tsc.h
  • TSC_GROUP8_IDX : stm32f3xx_hal_tsc.h
  • TSC_GROUP8_IO1 : stm32f3xx_hal_tsc.h
  • TSC_GROUP8_IO2 : stm32f3xx_hal_tsc.h
  • TSC_GROUP8_IO3 : stm32f3xx_hal_tsc.h
  • TSC_GROUP8_IO4 : stm32f3xx_hal_tsc.h
  • TSC_IODEF_IN_FLOAT : stm32f3xx_hal_tsc.h
  • TSC_IODEF_OUT_PP_LOW : stm32f3xx_hal_tsc.h
  • TSC_IOMODE_CHANNEL : stm32f3xx_hal_tsc.h
  • TSC_IOMODE_SAMPLING : stm32f3xx_hal_tsc.h
  • TSC_IOMODE_SHIELD : stm32f3xx_hal_tsc.h
  • TSC_IOMODE_UNUSED : stm32f3xx_hal_tsc.h
  • TSC_IT_EOA : stm32f3xx_hal_tsc.h
  • TSC_IT_MCE : stm32f3xx_hal_tsc.h
  • TSC_MCV_1023 : stm32f3xx_hal_tsc.h
  • TSC_MCV_16383 : stm32f3xx_hal_tsc.h
  • TSC_MCV_2047 : stm32f3xx_hal_tsc.h
  • TSC_MCV_255 : stm32f3xx_hal_tsc.h
  • TSC_MCV_4095 : stm32f3xx_hal_tsc.h
  • TSC_MCV_511 : stm32f3xx_hal_tsc.h
  • TSC_MCV_8191 : stm32f3xx_hal_tsc.h
  • TSC_NB_OF_GROUPS : stm32f3xx_hal_tsc.h
  • TSC_PG_PRESC_DIV1 : stm32f3xx_hal_tsc.h
  • TSC_PG_PRESC_DIV128 : stm32f3xx_hal_tsc.h
  • TSC_PG_PRESC_DIV16 : stm32f3xx_hal_tsc.h
  • TSC_PG_PRESC_DIV2 : stm32f3xx_hal_tsc.h
  • TSC_PG_PRESC_DIV32 : stm32f3xx_hal_tsc.h
  • TSC_PG_PRESC_DIV4 : stm32f3xx_hal_tsc.h
  • TSC_PG_PRESC_DIV64 : stm32f3xx_hal_tsc.h
  • TSC_PG_PRESC_DIV8 : stm32f3xx_hal_tsc.h
  • TSC_SS_PRESC_DIV1 : stm32f3xx_hal_tsc.h
  • TSC_SS_PRESC_DIV2 : stm32f3xx_hal_tsc.h
  • TSC_SYNC_POLARITY_FALLING : stm32f3xx_hal_tsc.h
  • TSC_SYNC_POLARITY_RISING : stm32f3xx_hal_tsc.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

  • File List
  • Globals
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- u -

  • UART_ADDRESS_DETECT_4B : stm32f3xx_hal_uart.h
  • UART_ADDRESS_DETECT_7B : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_INIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_DATAINVERT_INIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_DMA_DISABLEONRXERROR : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_DMA_ENABLEONRXERROR : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_DMADISABLEONERROR_INIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_INIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_NO_INIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_RXINVERT_INIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_INIT : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_DISABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_ENABLE : stm32f3xx_hal_uart.h
  • UART_ADVFEATURE_TXINVERT_INIT : stm32f3xx_hal_uart.h
  • UART_AUTOBAUD_REQUEST : stm32f3xx_hal_uart.h
  • UART_CLEAR_CMF : stm32f3xx_hal_uart.h
  • UART_CLEAR_CTSF : stm32f3xx_hal_uart.h
  • UART_CLEAR_EOBF : stm32f3xx_hal_uart.h
  • UART_CLEAR_FEF : stm32f3xx_hal_uart.h
  • UART_CLEAR_IDLEF : stm32f3xx_hal_uart.h
  • UART_CLEAR_LBDF : stm32f3xx_hal_uart.h
  • UART_CLEAR_NEF : stm32f3xx_hal_uart.h
  • UART_CLEAR_OREF : stm32f3xx_hal_uart.h
  • UART_CLEAR_PEF : stm32f3xx_hal_uart.h
  • UART_CLEAR_RTOF : stm32f3xx_hal_uart.h
  • UART_CLEAR_TCF : stm32f3xx_hal_uart.h
  • UART_CLEAR_WUF : stm32f3xx_hal_uart.h
  • UART_CR1_DEAT_ADDRESS_LSB_POS : stm32f3xx_hal_uart.h
  • UART_CR1_DEDT_ADDRESS_LSB_POS : stm32f3xx_hal_uart.h
  • UART_CR1_FIELDS : stm32f3xx_hal_uart.c
  • UART_CR2_ADDRESS_LSB_POS : stm32f3xx_hal_uart.h
  • UART_DE_POLARITY_HIGH : stm32f3xx_hal_uart.h
  • UART_DE_POLARITY_LOW : stm32f3xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32f3xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32f3xx_hal_uart.h
  • UART_DMA_RX_DISABLE : stm32f3xx_hal_uart.h
  • UART_DMA_RX_ENABLE : stm32f3xx_hal_uart.h
  • UART_DMA_TX_DISABLE : stm32f3xx_hal_uart.h
  • UART_DMA_TX_ENABLE : stm32f3xx_hal_uart.h
  • UART_FLAG_ABRE : stm32f3xx_hal_uart.h
  • UART_FLAG_ABRF : stm32f3xx_hal_uart.h
  • UART_FLAG_BUSY : stm32f3xx_hal_uart.h
  • UART_FLAG_CMF : stm32f3xx_hal_uart.h
  • UART_FLAG_CTS : stm32f3xx_hal_uart.h
  • UART_FLAG_CTSIF : stm32f3xx_hal_uart.h
  • UART_FLAG_EOBF : stm32f3xx_hal_uart.h
  • UART_FLAG_FE : stm32f3xx_hal_uart.h
  • UART_FLAG_IDLE : stm32f3xx_hal_uart.h
  • UART_FLAG_LBDF : stm32f3xx_hal_uart.h
  • UART_FLAG_NE : stm32f3xx_hal_uart.h
  • UART_FLAG_ORE : stm32f3xx_hal_uart.h
  • UART_FLAG_PE : stm32f3xx_hal_uart.h
  • UART_FLAG_REACK : stm32f3xx_hal_uart.h
  • UART_FLAG_RTOF : stm32f3xx_hal_uart.h
  • UART_FLAG_RWU : stm32f3xx_hal_uart.h
  • UART_FLAG_RXNE : stm32f3xx_hal_uart.h
  • UART_FLAG_SBKF : stm32f3xx_hal_uart.h
  • UART_FLAG_TC : stm32f3xx_hal_uart.h
  • UART_FLAG_TEACK : stm32f3xx_hal_uart.h
  • UART_FLAG_TXE : stm32f3xx_hal_uart.h
  • UART_FLAG_WUF : stm32f3xx_hal_uart.h
  • UART_GETCLOCKSOURCE : stm32f3xx_hal_uart_ex.h
  • UART_HALF_DUPLEX_DISABLE : stm32f3xx_hal_uart.h
  • UART_HALF_DUPLEX_ENABLE : stm32f3xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32f3xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32f3xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32f3xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32f3xx_hal_uart.h
  • UART_IT_CM : stm32f3xx_hal_uart.h
  • UART_IT_CTS : stm32f3xx_hal_uart.h
  • UART_IT_ERR : stm32f3xx_hal_uart.h
  • UART_IT_FE : stm32f3xx_hal_uart.h
  • UART_IT_IDLE : stm32f3xx_hal_uart.h
  • UART_IT_LBD : stm32f3xx_hal_uart.h
  • UART_IT_MASK : stm32f3xx_hal_uart.h
  • UART_IT_NE : stm32f3xx_hal_uart.h
  • UART_IT_ORE : stm32f3xx_hal_uart.h
  • UART_IT_PE : stm32f3xx_hal_uart.h
  • UART_IT_RXNE : stm32f3xx_hal_uart.h
  • UART_IT_TC : stm32f3xx_hal_uart.h
  • UART_IT_TXE : stm32f3xx_hal_uart.h
  • UART_IT_WUF : stm32f3xx_hal_uart.h
  • UART_LIN_DISABLE : stm32f3xx_hal_uart.h
  • UART_LIN_ENABLE : stm32f3xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32f3xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32f3xx_hal_uart.h
  • UART_MASK_COMPUTATION : stm32f3xx_hal_uart_ex.h
  • UART_MODE_RX : stm32f3xx_hal_uart.h
  • UART_MODE_TX : stm32f3xx_hal_uart.h
  • UART_MODE_TX_RX : stm32f3xx_hal_uart.h
  • UART_MUTE_MODE_REQUEST : stm32f3xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_DISABLE : stm32f3xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_ENABLE : stm32f3xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32f3xx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32f3xx_hal_uart.h
  • UART_PARITY_EVEN : stm32f3xx_hal_uart.h
  • UART_PARITY_NONE : stm32f3xx_hal_uart.h
  • UART_PARITY_ODD : stm32f3xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_DISABLE : stm32f3xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_ENABLE : stm32f3xx_hal_uart.h
  • UART_RXDATA_FLUSH_REQUEST : stm32f3xx_hal_uart.h
  • UART_SENDBREAK_REQUEST : stm32f3xx_hal_uart.h
  • UART_STATE_DISABLE : stm32f3xx_hal_uart.h
  • UART_STATE_ENABLE : stm32f3xx_hal_uart.h
  • UART_STOPBITS_0_5 : stm32f3xx_hal_uart.h
  • UART_STOPBITS_1 : stm32f3xx_hal_uart.h
  • UART_STOPBITS_1_5 : stm32f3xx_hal_uart.h
  • UART_STOPBITS_2 : stm32f3xx_hal_uart.h
  • UART_TXDATA_FLUSH_REQUEST : stm32f3xx_hal_uart.h
  • UART_WAKEUP_ON_ADDRESS : stm32f3xx_hal_uart.h
  • UART_WAKEUP_ON_READDATA_NONEMPTY : stm32f3xx_hal_uart.h
  • UART_WAKEUP_ON_STARTBIT : stm32f3xx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32f3xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32f3xx_hal_uart.h
  • UART_WORDLENGTH_8B : stm32f3xx_hal_uart_ex.h
  • UART_WORDLENGTH_9B : stm32f3xx_hal_uart_ex.h
  • UID_BASE_ADDRESS : stm32f3xx_ll_utils.h
  • USART_CLEAR_CTSF : stm32f3xx_hal_usart.h
  • USART_CLEAR_FEF : stm32f3xx_hal_usart.h
  • USART_CLEAR_IDLEF : stm32f3xx_hal_usart.h
  • USART_CLEAR_NEF : stm32f3xx_hal_usart.h
  • USART_CLEAR_OREF : stm32f3xx_hal_usart.h
  • USART_CLEAR_PEF : stm32f3xx_hal_usart.h
  • USART_CLEAR_TCF : stm32f3xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32f3xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32f3xx_hal_usart.h
  • USART_CR1_FIELDS : stm32f3xx_hal_smartcard.c , stm32f3xx_hal_usart.c
  • USART_CR2_CLK_FIELDS : stm32f3xx_hal_smartcard.c
  • USART_CR2_FIELDS : stm32f3xx_hal_usart.c , stm32f3xx_hal_smartcard.c
  • USART_CR3_FIELDS : stm32f3xx_hal_smartcard.c
  • USART_DUMMY_DATA : stm32f3xx_hal_usart.c
  • USART_FLAG_BUSY : stm32f3xx_hal_usart.h
  • USART_FLAG_CTS : stm32f3xx_hal_usart.h
  • USART_FLAG_CTSIF : stm32f3xx_hal_usart.h
  • USART_FLAG_FE : stm32f3xx_hal_usart.h
  • USART_FLAG_IDLE : stm32f3xx_hal_usart.h
  • USART_FLAG_LBDF : stm32f3xx_hal_usart.h
  • USART_FLAG_NE : stm32f3xx_hal_usart.h
  • USART_FLAG_ORE : stm32f3xx_hal_usart.h
  • USART_FLAG_PE : stm32f3xx_hal_usart.h
  • USART_FLAG_REACK : stm32f3xx_hal_usart.h
  • USART_FLAG_RXNE : stm32f3xx_hal_usart.h
  • USART_FLAG_TC : stm32f3xx_hal_usart.h
  • USART_FLAG_TEACK : stm32f3xx_hal_usart.h
  • USART_FLAG_TXE : stm32f3xx_hal_usart.h
  • USART_GETCLOCKSOURCE : stm32f3xx_hal_usart_ex.h
  • USART_IT_ERR : stm32f3xx_hal_usart.h
  • USART_IT_FE : stm32f3xx_hal_usart.h
  • USART_IT_IDLE : stm32f3xx_hal_usart.h
  • USART_IT_MASK : stm32f3xx_hal_usart.h
  • USART_IT_NE : stm32f3xx_hal_usart.h
  • USART_IT_ORE : stm32f3xx_hal_usart.h
  • USART_IT_PE : stm32f3xx_hal_usart.h
  • USART_IT_RXNE : stm32f3xx_hal_usart.h
  • USART_IT_TC : stm32f3xx_hal_usart.h
  • USART_IT_TXE : stm32f3xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32f3xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32f3xx_hal_usart.h
  • USART_MASK_COMPUTATION : stm32f3xx_hal_usart_ex.h
  • USART_MODE_RX : stm32f3xx_hal_usart.h
  • USART_MODE_TX : stm32f3xx_hal_usart.h
  • USART_MODE_TX_RX : stm32f3xx_hal_usart.h
  • USART_PARITY_EVEN : stm32f3xx_hal_usart.h
  • USART_PARITY_NONE : stm32f3xx_hal_usart.h
  • USART_PARITY_ODD : stm32f3xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32f3xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32f3xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32f3xx_hal_usart.h
  • USART_POLARITY_LOW : stm32f3xx_hal_usart.h
  • USART_RXDATA_FLUSH_REQUEST : stm32f3xx_hal_usart.h
  • USART_STOPBITS_0_5 : stm32f3xx_hal_usart.h
  • USART_STOPBITS_1 : stm32f3xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32f3xx_hal_usart.h
  • USART_STOPBITS_2 : stm32f3xx_hal_usart.h
  • USART_TEACK_REACK_TIMEOUT : stm32f3xx_hal_usart.c
  • USART_TXDATA_FLUSH_REQUEST : stm32f3xx_hal_usart.h
  • USART_WORDLENGTH_8B : stm32f3xx_hal_usart_ex.h
  • USART_WORDLENGTH_9B : stm32f3xx_hal_usart_ex.h
  • USB_WAKEUP_EXTI_LINE : stm32f3xx_hal_pcd.h
  • USE_RTOS : stm32f3xx_hal_conf.h
  • USE_SPI_CRC : stm32f3xx_hal_conf.h
  • UTILS_HSE_FREQUENCY_MAX : stm32f3xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MIN : stm32f3xx_ll_utils.c
  • UTILS_LATENCY1_FREQ : stm32f3xx_ll_utils.c
  • UTILS_LATENCY2_FREQ : stm32f3xx_ll_utils.c
  • UTILS_PLL_OUTPUT_MAX : stm32f3xx_ll_utils.c
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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  • Globals
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  • Typedefs
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  • VDD_VALUE : stm32f3xx_hal_conf.h
  • VREFINT_CAL_ADDR : stm32f3xx_ll_adc.h
  • VREFINT_CAL_VREF : stm32f3xx_ll_adc.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Globals

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  • WWDG_EWI_DISABLE : stm32f3xx_hal_wwdg.h
  • WWDG_EWI_ENABLE : stm32f3xx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32f3xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32f3xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32f3xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32f3xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32f3xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32f3xx_hal_wwdg.h
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal.h File Reference

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Defines | Functions
stm32f3xx_hal.h File Reference

This file contains all the functions prototypes for the HAL module driver. More...

#include "stm32f3xx_hal_conf.h"

Go to the source code of this file.

Defines

#define | IS_SYSCFG_FASTMODEPLUS(__PIN__)
#define | SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
#define | CFGR2_OFFSET (SYSCFG_OFFSET + 0x18U)
#define | BYPADDRPAR_BitNumber 0x04U
#define | CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32U) + (BYPADDRPAR_BitNumber * 4U))
#define | HAL_REMAPDMA_ADC24_DMA2_CH34 (0x00000100U)
#define | HAL_REMAPDMA_TIM16_DMA1_CH6 (0x00000800U)
#define | HAL_REMAPDMA_TIM17_DMA1_CH7 (0x00001000U)
#define | HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 (0x00002000U)
#define | HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 (0x00004000U)
#define | HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 (0x00008000U)
#define | HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U)
#define | IS_DMA_REMAP(RMP)
#define | HAL_REMAPTRIGGER_DAC1_TRIG (0x00000080U)
#define | HAL_REMAPTRIGGER_TIM1_ITR3 (0x00000040U)
#define | IS_HAL_REMAPTRIGGER(RMP)
#define | SYSCFG_FASTMODEPLUS_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP)
Fast-mode Plus driving capability on a specific GPIO.
#define | SYSCFG_FASTMODEPLUS_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP)
#define | SYSCFG_FASTMODEPLUS_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP)
#define | SYSCFG_FASTMODEPLUS_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP)
#define | HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0)
#define | HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1)
#define | HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2)
#define | HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3)
#define | HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4)
#define | HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5)
#define | IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__)
#define | __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#define | __HAL_FREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP))
#define | __HAL_UNFREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP))
#define | __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
#define | __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
#define | __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#define | __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#define | __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#define | __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#define | __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
#define | __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
#define | __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
#define | __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
#define | __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))
#define | __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
Main Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()
System Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SRAM()
Embedded SRAM mapped at 0x00000000.
#define | __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__)
DMA remapping enable/disable macros.
#define | __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__)
#define | __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)
Fast-mode Plus driving capability enable/disable macros.
#define | __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__)
#define | __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__)
SYSCFG interrupt enable/disable macros.
#define | __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__)
#define | __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))
SYSCFG interrupt enable/disable macros.
#define | __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT))
#define | __HAL_SYSCFG_BREAK_LOCKUP_LOCK()
SYSCFG Break Lockup lock Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input.
#define | __HAL_SYSCFG_BREAK_PVD_LOCK()
SYSCFG Break PVD lock Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register.
#define | __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK()
SYSCFG Break SRAM PARITY lock Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17.
#define | __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__)
Trigger remapping enable/disable macros.
#define | __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__)

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function configures the Flash prefetch, Configures time base source, NVIC and Low level hardware.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the source of time base.
__weak void | HAL_MspInit (void)
Initializes the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak void | HAL_Delay (__IO uint32_t Delay)
This function provides accurate delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
__weak uint32_t | HAL_GetTick (void)
Povides a tick value in millisecond.
uint32_t | HAL_GetHalVersion (void)
This function returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
uint32_t | HAL_GetUIDw0 (void)
Returns first word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw1 (void)
Returns second word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw2 (void)
Returns third word of the unique device identifier (UID based on 96 bits)
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.

Detailed Description

This file contains all the functions prototypes for the HAL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal.h.

Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_adc.h File Reference

  • File List
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  • STM32F3xx_HAL_Driver
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Data Structures | Defines | Typedefs | Functions
stm32f3xx_hal_adc.h File Reference

Header file containing functions prototypes of ADC HAL library. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_adc_ex.h"

Go to the source code of this file.

Data Structures

struct | __ADC_HandleTypeDef
ADC handle Structure definition. More...

Defines

#define | HAL_ADC_STATE_RESET (0x00000000U)
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY (0x00000001U)
#define | HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U)
#define | HAL_ADC_STATE_TIMEOUT (0x00000004U)
#define | HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U)
#define | HAL_ADC_STATE_ERROR_CONFIG (0x00000020U)
#define | HAL_ADC_STATE_ERROR_DMA (0x00000040U)
#define | HAL_ADC_STATE_REG_BUSY (0x00000100U)
#define | HAL_ADC_STATE_REG_EOC (0x00000200U)
#define | HAL_ADC_STATE_REG_OVR (0x00000400U)
#define | HAL_ADC_STATE_REG_EOSMP (0x00000800U)
#define | HAL_ADC_STATE_INJ_BUSY (0x00001000U)
#define | HAL_ADC_STATE_INJ_EOC (0x00002000U)
#define | HAL_ADC_STATE_INJ_JQOVF (0x00004000U)
#define | HAL_ADC_STATE_AWD1 (0x00010000U)
#define | HAL_ADC_STATE_AWD2 (0x00020000U)
#define | HAL_ADC_STATE_AWD3 (0x00040000U)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U)
#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
Reset ADC handle state.

Typedefs

typedef struct __ADC_HandleTypeDef | ADC_HandleTypeDef
ADC handle Structure definition.

Functions

__weak HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
__weak HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initializes the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitializes the ADC MSP.
__weak HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of regular group.
__weak HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC peripheral.
__weak HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
__weak HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for conversion event.
__weak HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of regular group with interruption.
__weak HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interruption of end-of-conversion, disable ADC peripheral.
__weak HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC, starts conversion of regular group and transfers result through DMA.
__weak HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
__weak uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
__weak void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handles ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog callback in non blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non blocking mode (ADC conversion with interruption or transfer by DMA)
__weak HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configures the the selected channel to be linked to the regular group.
__weak HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configures the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
return the ADC state
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.

Detailed Description

Header file containing functions prototypes of ADC HAL library.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_adc.h.

Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_adc_ex.h File Reference

  • File List
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  • Firmware
  • Drivers
  • STM32F3xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32f3xx_hal_adc_ex.h File Reference

Header file containing functions prototypes of ADC HAL library. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | ADC_InitTypeDef
Structure definition of ADC and regular group initialization. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_InjectionConfTypeDef
ADC Configuration injected Channel structure definition. More...
struct | ADC_AnalogWDGConfTypeDef
ADC Configuration analog watchdog definition. More...

Defines

#define | HAL_ADC_ERROR_NONE (0x00U)
#define | HAL_ADC_ERROR_INTERNAL (0x01U)
#define | HAL_ADC_ERROR_OVR (0x02U)
#define | HAL_ADC_ERROR_DMA (0x04U)
#define | HAL_ADC_ERROR_JQOVF (0x08U)
#define | ADC_DATAALIGN_RIGHT (0x00000000U)
#define | ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
#define | ADC_SCAN_DISABLE (0x00000000U)
#define | ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
#define | ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
#define | ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2
#define | ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO
#define | ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4
#define | ADC_EXTERNALTRIGCONV_T19_TRGO ADC_EXTERNALTRIG_T19_TRGO
#define | ADC_EXTERNALTRIGCONV_T19_CC3 ADC_EXTERNALTRIG_T19_CC3
#define | ADC_EXTERNALTRIGCONV_T19_CC4 ADC_EXTERNALTRIG_T19_CC4
#define | ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11
#define | ADC_SOFTWARE_START ADC_SWSTART
#define | ADC_CHANNEL_0 (0x00000000U)
#define | ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ1_1))
#define | ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ1_2))
#define | ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
#define | ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ1_3))
#define | ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1))
#define | ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2))
#define | ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
#define | ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4))
#define | ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_1))
#define | ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16
#define | ADC_CHANNEL_VREFINT ADC_CHANNEL_17
#define | ADC_CHANNEL_VBAT ADC_CHANNEL_18
#define | ADC_SAMPLETIME_1CYCLE_5 (0x00000000U)
#define | ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_0)
#define | ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_1)
#define | ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0))
#define | ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_2)
#define | ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0))
#define | ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1))
#define | ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0)
#define | ADC_REGULAR_RANK_1 (0x00000001U)
#define | ADC_REGULAR_RANK_2 (0x00000002U)
#define | ADC_REGULAR_RANK_3 (0x00000003U)
#define | ADC_REGULAR_RANK_4 (0x00000004U)
#define | ADC_REGULAR_RANK_5 (0x00000005U)
#define | ADC_REGULAR_RANK_6 (0x00000006U)
#define | ADC_REGULAR_RANK_7 (0x00000007U)
#define | ADC_REGULAR_RANK_8 (0x00000008U)
#define | ADC_REGULAR_RANK_9 (0x00000009U)
#define | ADC_REGULAR_RANK_10 (0x0000000AU)
#define | ADC_REGULAR_RANK_11 (0x0000000BU)
#define | ADC_REGULAR_RANK_12 (0x0000000CU)
#define | ADC_REGULAR_RANK_13 (0x0000000DU)
#define | ADC_REGULAR_RANK_14 (0x0000000EU)
#define | ADC_REGULAR_RANK_15 (0x0000000FU)
#define | ADC_REGULAR_RANK_16 (0x00000010U)
#define | ADC_INJECTED_RANK_1 (0x00000001U)
#define | ADC_INJECTED_RANK_2 (0x00000002U)
#define | ADC_INJECTED_RANK_3 (0x00000003U)
#define | ADC_INJECTED_RANK_4 (0x00000004U)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
#define | ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1
#define | ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO
#define | ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4
#define | ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO
#define | ADC_EXTERNALTRIGINJECCONV_T19_CC1 ADC_EXTERNALTRIGINJEC_T19_CC1
#define | ADC_EXTERNALTRIGINJECCONV_T19_CC2 ADC_EXTERNALTRIGINJEC_T19_CC2
#define | ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15
#define | ADC_INJECTED_SOFTWARE_START ADC_JSWSTART
#define | ADC_ANALOGWATCHDOG_NONE (0x00000000U)
#define | ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define | ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
#define | ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
#define | ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
#define | ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
#define | ADC_IT_EOC ADC_CR1_EOCIE
#define | ADC_IT_JEOC ADC_CR1_JEOCIE
#define | ADC_IT_AWD ADC_CR1_AWDIE
#define | ADC_FLAG_AWD ADC_SR_AWD
#define | ADC_FLAG_EOC ADC_SR_EOC
#define | ADC_FLAG_JEOC ADC_SR_JEOC
#define | ADC_FLAG_JSTRT ADC_SR_JSTRT
#define | ADC_FLAG_STRT ADC_SR_STRT
#define | ADC_EXTERNALTRIG_T19_TRGO (0x00000000U)
#define | ADC_EXTERNALTRIG_T19_CC3 ((uint32_t)ADC_CR2_EXTSEL_0)
#define | ADC_EXTERNALTRIG_T19_CC4 ((uint32_t)ADC_CR2_EXTSEL_1)
#define | ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)
#define | ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
#define | ADC_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T19_CC1 ( 0x00000000U)
#define | ADC_EXTERNALTRIGINJEC_T19_CC2 ((uint32_t) ADC_CR2_JEXTSEL_0)
#define | ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t) ADC_CR2_JEXTSEL_1)
#define | ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t) ADC_CR2_JEXTSEL_2)
#define | ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
#define | ADC_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0
#define | ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS (0x00000000U)
#define | ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define | ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
#define | ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define | ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
#define | ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define | ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
#define | ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define | ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS (0x00000000U)
#define | ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define | ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
#define | ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define | ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
#define | ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define | ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
#define | ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define | ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )
#define | __HAL_ADC_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
Enable the ADC peripheral.
#define | __HAL_ADC_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
Disable the ADC peripheral.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
Enable the ADC end of conversion interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
Disable the ADC end of conversion interrupt.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected ADC's flag status.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
Clear the ADC's pending flags.
#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
Reset ADC handle state.
#define | ADC_IS_ENABLE(__HANDLE__)
Verification of ADC state: enabled or disabled.
#define | ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
Test if conversion trigger of regular group is software start or external trigger.
#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clears and sets specific bits of the handle State.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to error code: "no error")
#define | ADC_SQR1_L_SHIFT(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
Set ADC number of conversions into regular channel sequence length.
#define | ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U)))
Set the ADC's sample time for channel numbers between 10 and 18.
#define | ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (_CHANNELNB_)))
Set the ADC's sample time for channel numbers between 0 and 9.
#define | ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5U * ((_RANKNB_) - 1U)))
Set the selected regular channel rank for rank between 1 and 6.
#define | ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5U * ((_RANKNB_) - 7U)))
Set the selected regular channel rank for rank between 7 and 12.
#define | ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5U * ((_RANKNB_) - 13U)))
Set the selected regular channel rank for rank between 13 and 16.
#define | ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_) -1U) << 20U)
Set the injected sequence length.
#define | ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) ((_CHANNELNB_) << (5U * ((4U - ((_JSQR_JL_) - (_RANKNB_))) - 1U)))
Set the selected injected channel rank Note: on STM32F37x devices, channel rank position in JSQR register is depending on total number of ranks selected into injected sequencer (ranks sequence starting from 4-JL)
#define | ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U)
Enable ADC continuous conversion mode.
#define | ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 13U)
Configures the number of discontinuous conversions for the regular group channels.
#define | ADC_CR1_SCAN_SET(_SCAN_MODE_)
Enable ADC scan mode to convert multiple ranks with sequencer.
#define | ADC_CALFACT_DIFF_SET(_Calibration_Factor_) ((_Calibration_Factor_) << 16U)
Calibration factor in differential mode to be set into calibration register.
#define | ADC_CALFACT_DIFF_GET(_Calibration_Factor_) ((_Calibration_Factor_) >> 16U)
Calibration factor in differential mode to be retrieved from calibration register.
#define | ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)
Get the maximum ADC conversion cycles on all channels.
#define | ADC_CLOCK_PRESCALER_RANGE()
Get the total ADC clock prescaler (APB2 prescaler x ADC prescaler) from system clock configuration register.
#define | ADC_GET_CLOCK_PRESCALER() (((RCC->CFGR & RCC_CFGR_ADCPRE) >> 14U) +1U)
Get the ADC clock prescaler from system clock configuration register.
#define | IS_ADC_DATA_ALIGN(ALIGN)
#define | IS_ADC_SCAN_MODE(SCAN_MODE)
#define | IS_ADC_CHANNEL(CHANNEL)
#define | IS_ADC_SAMPLE_TIME(TIME)
#define | IS_ADC_REGULAR_RANK(CHANNEL)
#define | IS_ADC_EXTTRIG_EDGE(EDGE)
#define | IS_ADC_EXTTRIG(REGTRIG)
#define | IS_ADC_EXTTRIGINJEC_EDGE(EDGE)
#define | IS_ADC_EXTTRIGINJEC(INJTRIG)
#define | IS_ADC_INJECTED_RANK(CHANNEL)
#define | IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG)
#define | IS_ADC_CONVERSION_GROUP(CONVERSION)
#define | IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
#define | IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= (0x0FFFU))
#define | IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U)))
#define | IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U)))
#define | IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop (struct __ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_IT (struct __ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_DMA (struct __ADC_HandleTypeDef *hadc)
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configures the ADC injected group and the selected channel to be linked to the injected group.

Detailed Description

Header file containing functions prototypes of ADC HAL library.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_adc_ex.h.

Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_can.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32f3xx_hal_can.h File Reference

Header file of CAN HAL module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | CAN_InitTypeDef
CAN init structure definition. More...
struct | CAN_FilterConfTypeDef
CAN filter configuration structure definition. More...
struct | CanTxMsgTypeDef
CAN Tx message structure definition. More...
struct | CanRxMsgTypeDef
CAN Rx message structure definition. More...
struct | CAN_HandleTypeDef
CAN handle Structure definition. More...

Defines

#define | HAL_CAN_ERROR_NONE (0x00000000U)
#define | HAL_CAN_ERROR_EWG (0x00000001U)
#define | HAL_CAN_ERROR_EPV (0x00000002U)
#define | HAL_CAN_ERROR_BOF (0x00000004U)
#define | HAL_CAN_ERROR_STF (0x00000008U)
#define | HAL_CAN_ERROR_FOR (0x00000010U)
#define | HAL_CAN_ERROR_ACK (0x00000020U)
#define | HAL_CAN_ERROR_BR (0x00000040U)
#define | HAL_CAN_ERROR_BD (0x00000080U)
#define | HAL_CAN_ERROR_CRC (0x00000100U)
#define | HAL_CAN_ERROR_FOV0 (0x00000200U)
#define | HAL_CAN_ERROR_FOV1 (0x00000400U)
#define | HAL_CAN_ERROR_TXFAIL (0x00000800U)
#define | CAN_INITSTATUS_FAILED (0x00000000U)
#define | CAN_INITSTATUS_SUCCESS (0x00000001U)
#define | CAN_MODE_NORMAL (0x00000000U)
#define | CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM)
#define | CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM)
#define | CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))
#define | CAN_SJW_1TQ (0x00000000U)
#define | CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0)
#define | CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1)
#define | CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW)
#define | CAN_BS1_1TQ (0x00000000U)
#define | CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0)
#define | CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1)
#define | CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2)
#define | CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
#define | CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
#define | CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3)
#define | CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))
#define | CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))
#define | CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))
#define | CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
#define | CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
#define | CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1)
#define | CAN_BS2_1TQ (0x00000000U)
#define | CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0)
#define | CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1)
#define | CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))
#define | CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2)
#define | CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))
#define | CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))
#define | CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2)
#define | CAN_FILTERMODE_IDMASK ((uint8_t)0x00U)
#define | CAN_FILTERMODE_IDLIST ((uint8_t)0x01U)
#define | CAN_FILTERSCALE_16BIT ((uint8_t)0x00U)
#define | CAN_FILTERSCALE_32BIT ((uint8_t)0x01U)
#define | CAN_FILTER_FIFO0 ((uint8_t)0x00U)
#define | CAN_FILTER_FIFO1 ((uint8_t)0x01U)
#define | CAN_ID_STD (0x00000000U)
#define | CAN_ID_EXT (0x00000004U)
#define | CAN_RTR_DATA (0x00000000U)
#define | CAN_RTR_REMOTE (0x00000002U)
#define | CAN_FIFO0 ((uint8_t)0x00U)
#define | CAN_FIFO1 ((uint8_t)0x01U)
#define | CAN_FLAG_RQCP0 (0x00000500U)
#define | CAN_FLAG_RQCP1 (0x00000508U)
#define | CAN_FLAG_RQCP2 (0x00000510U)
#define | CAN_FLAG_TXOK0 (0x00000501U)
#define | CAN_FLAG_TXOK1 (0x00000509U)
#define | CAN_FLAG_TXOK2 (0x00000511U)
#define | CAN_FLAG_TME0 (0x0000051AU)
#define | CAN_FLAG_TME1 (0x0000051BU)
#define | CAN_FLAG_TME2 (0x0000051CU)
#define | CAN_FLAG_FF0 (0x00000203U)
#define | CAN_FLAG_FOV0 (0x00000204U)
#define | CAN_FLAG_FF1 (0x00000403U)
#define | CAN_FLAG_FOV1 (0x00000404U)
#define | CAN_FLAG_INAK (0x00000100U)
#define | CAN_FLAG_SLAK (0x00000101U)
#define | CAN_FLAG_ERRI (0x00000102U)
#define | CAN_FLAG_WKU (0x00000103U)
#define | CAN_FLAG_SLAKI (0x00000104U)
#define | CAN_FLAG_EWG (0x00000300U)
#define | CAN_FLAG_EPV (0x00000301U)
#define | CAN_FLAG_BOF (0x00000302U)
#define | CAN_IT_TME ((uint32_t)CAN_IER_TMEIE)
#define | CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0)
#define | CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0)
#define | CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0)
#define | CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1)
#define | CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1)
#define | CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1)
#define | CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE)
#define | CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE)
#define | CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE)
#define | CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE)
#define | CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE)
#define | CAN_IT_LEC ((uint32_t)CAN_IER_LECIE)
#define | CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE)
#define | CAN_TXMAILBOX_0 ((uint8_t)0x00U)
#define | CAN_TXMAILBOX_1 ((uint8_t)0x01U)
#define | CAN_TXMAILBOX_2 ((uint8_t)0x02U)
#define | __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
Reset CAN handle state.
#define | __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable the specified CAN interrupts.
#define | __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable the specified CAN interrupts.
#define | __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__)
Return the number of pending received messages.
#define | __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__)
Check whether the specified CAN flag is set or not.
#define | __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the specified CAN pending flag.
#define | __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check if the specified CAN interrupt source is enabled or disabled.
#define | __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)
Check the transmission status of a CAN Frame.
#define | __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__)
Release the specified receive FIFO.
#define | __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)
Cancel a transmit request.
#define | __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__)
Enable or disables the DBG Freeze for CAN.
#define | CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U)
#define | CAN_FLAG_MASK (0x000000FFU)
#define | IS_CAN_MODE(MODE)
#define | IS_CAN_SJW(SJW)
#define | IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
#define | IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
#define | IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
#define | IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
#define | IS_CAN_FILTER_MODE(MODE)
#define | IS_CAN_FILTER_SCALE(SCALE)
#define | IS_CAN_FILTER_FIFO(FIFO)
#define | IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
#define | IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
#define | IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU))
#define | IS_CAN_EXTID(EXTID) ((EXTID) <= (0x1FFFFFFFU))
#define | IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U))
#define | IS_CAN_IDTYPE(IDTYPE)
#define | IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
#define | IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
#define | IS_CAN_IT(IT)
#define | IS_CAN_CLEAR_IT(IT)

Enumerations

enum HAL_CAN_StateTypeDef {
HAL_CAN_STATE_RESET = 0x00U, HAL_CAN_STATE_READY = 0x01U, HAL_CAN_STATE_BUSY = 0x02U, HAL_CAN_STATE_BUSY_TX = 0x12U,
HAL_CAN_STATE_BUSY_RX0 = 0x22U, HAL_CAN_STATE_BUSY_RX1 = 0x32U, HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U,
HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, HAL_CAN_STATE_TIMEOUT = 0x03U, HAL_CAN_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_CAN_Init (CAN_HandleTypeDef *hcan)
Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.
HAL_StatusTypeDef | HAL_CAN_ConfigFilter (CAN_HandleTypeDef *hcan, CAN_FilterConfTypeDef *sFilterConfig)
Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.
HAL_StatusTypeDef | HAL_CAN_DeInit (CAN_HandleTypeDef *hcan)
Deinitializes the CANx peripheral registers to their default reset values.
__weak void | HAL_CAN_MspInit (CAN_HandleTypeDef *hcan)
Initializes the CAN MSP.
__weak void | HAL_CAN_MspDeInit (CAN_HandleTypeDef *hcan)
DeInitializes the CAN MSP.
HAL_StatusTypeDef | HAL_CAN_Transmit (CAN_HandleTypeDef *hcan, uint32_t Timeout)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Receive (CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Sleep (CAN_HandleTypeDef *hcan)
Enters the Sleep (low power) mode.
HAL_StatusTypeDef | HAL_CAN_WakeUp (CAN_HandleTypeDef *hcan)
Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode.
void | HAL_CAN_IRQHandler (CAN_HandleTypeDef *hcan)
Handles CAN interrupt request.
__weak void | HAL_CAN_TxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_RxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_ErrorCallback (CAN_HandleTypeDef *hcan)
Error CAN callback.
uint32_t | HAL_CAN_GetError (CAN_HandleTypeDef *hcan)
Return the CAN error code.
HAL_CAN_StateTypeDef | HAL_CAN_GetState (CAN_HandleTypeDef *hcan)
return the CAN state

Detailed Description

Header file of CAN HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_can.h.

Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_cec.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32f3xx_hal_cec.h File Reference

Header file of CEC HAL module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | CEC_InitTypeDef
CEC Init Structure definition. More...
struct | CEC_HandleTypeDef
CEC handle Structure definition. More...

Defines

#define | HAL_CEC_ERROR_NONE (0x00000000U)
#define | HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR
#define | HAL_CEC_ERROR_BRE CEC_ISR_BRE
#define | HAL_CEC_ERROR_SBPE CEC_ISR_SBPE
#define | HAL_CEC_ERROR_LBPE CEC_ISR_LBPE
#define | HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE
#define | HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST
#define | HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR
#define | HAL_CEC_ERROR_TXERR CEC_ISR_TXERR
#define | HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE
#define | CEC_DEFAULT_SFT (0x00000000U)
#define | CEC_0_5_BITPERIOD_SFT (0x00000001U)
#define | CEC_1_5_BITPERIOD_SFT (0x00000002U)
#define | CEC_2_5_BITPERIOD_SFT (0x00000003U)
#define | CEC_3_5_BITPERIOD_SFT (0x00000004U)
#define | CEC_4_5_BITPERIOD_SFT (0x00000005U)
#define | CEC_5_5_BITPERIOD_SFT (0x00000006U)
#define | CEC_6_5_BITPERIOD_SFT (0x00000007U)
#define | CEC_STANDARD_TOLERANCE (0x00000000U)
#define | CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
#define | CEC_NO_RX_STOP_ON_BRE (0x00000000U)
#define | CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
#define | CEC_BRE_ERRORBIT_NO_GENERATION (0x00000000U)
#define | CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
#define | CEC_LBPE_ERRORBIT_NO_GENERATION (0x00000000U)
#define | CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
#define | CEC_BROADCASTERROR_ERRORBIT_GENERATION (0x00000000U)
#define | CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
#define | CEC_SFT_START_ON_TXSOM (0x00000000U)
#define | CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
#define | CEC_REDUCED_LISTENING_MODE (0x00000000U)
#define | CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
#define | CEC_CFGR_OAR_LSB_POS (16U)
#define | CEC_INITIATOR_LSB_POS (4U)
#define | CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
#define | CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0U */
#define | CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1U */
#define | CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2U */
#define | CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3U */
#define | CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4U */
#define | CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5U */
#define | CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6U */
#define | CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7U */
#define | CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9U */
#define | CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10U */
#define | CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11U */
#define | CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12U */
#define | CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13U */
#define | CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14U */
#define | CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15U */
#define | CEC_IT_TXACKE CEC_IER_TXACKEIE
#define | CEC_IT_TXERR CEC_IER_TXERRIE
#define | CEC_IT_TXUDR CEC_IER_TXUDRIE
#define | CEC_IT_TXEND CEC_IER_TXENDIE
#define | CEC_IT_TXBR CEC_IER_TXBRIE
#define | CEC_IT_ARBLST CEC_IER_ARBLSTIE
#define | CEC_IT_RXACKE CEC_IER_RXACKEIE
#define | CEC_IT_LBPE CEC_IER_LBPEIE
#define | CEC_IT_SBPE CEC_IER_SBPEIE
#define | CEC_IT_BRE CEC_IER_BREIE
#define | CEC_IT_RXOVR CEC_IER_RXOVRIE
#define | CEC_IT_RXEND CEC_IER_RXENDIE
#define | CEC_IT_RXBR CEC_IER_RXBRIE
#define | CEC_FLAG_TXACKE CEC_ISR_TXACKE
#define | CEC_FLAG_TXERR CEC_ISR_TXERR
#define | CEC_FLAG_TXUDR CEC_ISR_TXUDR
#define | CEC_FLAG_TXEND CEC_ISR_TXEND
#define | CEC_FLAG_TXBR CEC_ISR_TXBR
#define | CEC_FLAG_ARBLST CEC_ISR_ARBLST
#define | CEC_FLAG_RXACKE CEC_ISR_RXACKE
#define | CEC_FLAG_LBPE CEC_ISR_LBPE
#define | CEC_FLAG_SBPE CEC_ISR_SBPE
#define | CEC_FLAG_BRE CEC_ISR_BRE
#define | CEC_FLAG_RXOVR CEC_ISR_RXOVR
#define | CEC_FLAG_RXEND CEC_ISR_RXEND
#define | CEC_FLAG_RXBR CEC_ISR_RXBR
#define | CEC_ISR_ALL_ERROR
#define | CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
#define | CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
#define | __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__)
Reset CEC handle gstate & RxState.
#define | __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Checks whether or not the specified CEC interrupt flag is set.
#define | __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
Clears the interrupt or status flag when raised (write at 1U)
#define | __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enables the specified CEC interrupt.
#define | __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disables the specified CEC interrupt.
#define | __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
Checks whether or not the specified CEC interrupt is enabled.
#define | __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
Enables the CEC device.
#define | __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
Disables the CEC device.
#define | __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
Set Transmission Start flag.
#define | __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
Set Transmission End flag.
#define | __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
Get Transmission Start flag.
#define | __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
Get Transmission End flag.
#define | __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
Clear OAR register.
#define | __HAL_CEC_SET_OAR(__HANDLE__, __ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
Set OAR register (without resetting previously set address in case of multi-address mode) To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand.
#define | IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
#define | IS_CEC_TOLERANCE(__RXTOL__)
#define | IS_CEC_BRERXSTOP(__BRERXSTOP__)
#define | IS_CEC_BREERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__)
#define | IS_CEC_SFTOP(__SFTOP__)
#define | IS_CEC_LISTENING_MODE(__MODE__)
#define | IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
Check CEC message size.
#define | IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
Check CEC device Own Address Register (OAR) setting.
#define | IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)
Check CEC initiator or destination logical address setting.

Enumerations

enum HAL_CEC_StateTypeDef {
HAL_CEC_STATE_RESET = 0x00U, HAL_CEC_STATE_READY = 0x20U, HAL_CEC_STATE_BUSY = 0x24U, HAL_CEC_STATE_BUSY_RX = 0x22U,
HAL_CEC_STATE_BUSY_TX = 0x21U, HAL_CEC_STATE_BUSY_RX_TX = 0x23U, HAL_CEC_STATE_ERROR = 0x60U
}
HAL CEC State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_CEC_Init (CEC_HandleTypeDef *hcec)
Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_CEC_DeInit (CEC_HandleTypeDef *hcec)
DeInitializes the CEC peripheral.
HAL_StatusTypeDef | HAL_CEC_SetDeviceAddress (CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
Initializes the Own Address of the CEC device.
__weak void | HAL_CEC_MspInit (CEC_HandleTypeDef *hcec)
CEC MSP Init.
__weak void | HAL_CEC_MspDeInit (CEC_HandleTypeDef *hcec)
CEC MSP DeInit.
HAL_StatusTypeDef | HAL_CEC_Transmit_IT (CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
Send data in interrupt mode.
uint32_t | HAL_CEC_GetLastReceivedFrameSize (CEC_HandleTypeDef *hcec)
Get size of the received frame.
void | HAL_CEC_ChangeRxBuffer (CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
Change Rx Buffer.
void | HAL_CEC_IRQHandler (CEC_HandleTypeDef *hcec)
This function handles CEC interrupt requests.
__weak void | HAL_CEC_TxCpltCallback (CEC_HandleTypeDef *hcec)
Tx Transfer completed callback.
__weak void | HAL_CEC_RxCpltCallback (CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
Rx Transfer completed callback.
__weak void | HAL_CEC_ErrorCallback (CEC_HandleTypeDef *hcec)
CEC error callbacks.
HAL_CEC_StateTypeDef | HAL_CEC_GetState (CEC_HandleTypeDef *hcec)
return the CEC state
uint32_t | HAL_CEC_GetError (CEC_HandleTypeDef *hcec)
Return the CEC error code.

Detailed Description

Header file of CEC HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_cec.h.

Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_comp.h File Reference

  • File List
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  • Firmware
  • Drivers
  • STM32F3xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32f3xx_hal_comp.h File Reference

Header file of COMP HAL module. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_comp_ex.h"

Go to the source code of this file.

Data Structures

struct | COMP_InitTypeDef
COMP Init structure definition. More...
struct | COMP_HandleTypeDef
COMP Handle Structure definition. More...

Defines

#define | COMP_OUTPUTPOL_NONINVERTED (0x00000000U)
#define | COMP_OUTPUTPOL_INVERTED COMP_CSR_COMPxPOL
#define | COMP_OUTPUTLEVEL_LOW (0x00000000U)
#define | COMP_OUTPUTLEVEL_HIGH COMP_CSR_COMPxOUT
#define | COMP_TRIGGERMODE_NONE (0x00000000U)
#define | COMP_TRIGGERMODE_IT_RISING (0x00000001U)
#define | COMP_TRIGGERMODE_IT_FALLING (0x00000002U)
#define | COMP_TRIGGERMODE_IT_RISING_FALLING (0x00000003U)
#define | COMP_TRIGGERMODE_EVENT_RISING (0x00000010U)
#define | COMP_TRIGGERMODE_EVENT_FALLING (0x00000020U)
#define | COMP_TRIGGERMODE_EVENT_RISING_FALLING (0x00000030U)
#define | COMP_STATE_BIT_LOCK (0x00000010U) /* Lock bit in COMP handle state */
#define | __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
Reset COMP handle state.
#define | IS_COMP_OUTPUTPOL(__POL__)
#define | IS_COMP_TRIGGERMODE(__MODE__)

Enumerations

enum HAL_COMP_StateTypeDef {
HAL_COMP_STATE_RESET = 0x00U, HAL_COMP_STATE_READY = 0x01U, HAL_COMP_STATE_READY_LOCKED = 0x11U, HAL_COMP_STATE_BUSY = 0x02U,
HAL_COMP_STATE_BUSY_LOCKED = 0x12
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP peripheral according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
HAL_StatusTypeDef | HAL_COMP_Start_IT (COMP_HandleTypeDef *hcomp)
Start the comparator in Interrupt mode.
HAL_StatusTypeDef | HAL_COMP_Stop_IT (COMP_HandleTypeDef *hcomp)
Stop the comparator in Interrupt mode.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ Handler.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator callback.
HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
HAL_COMP_StateTypeDef | HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.

Detailed Description

Header file of COMP HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_comp.h.

Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_comp_ex.h File Reference

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Defines
stm32f3xx_hal_comp_ex.h File Reference

Header file of COMP HAL Extended module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Defines

#define | COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U)
#define | COMP_INVERTINGINPUT_1_2VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_0)
#define | COMP_INVERTINGINPUT_3_4VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_1)
#define | COMP_INVERTINGINPUT_VREFINT ((uint32_t)(COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0))
#define | COMP_INVERTINGINPUT_DAC1_CH1 ((uint32_t)COMP_CSR_COMPxINSEL_2)
#define | COMP_INVERTINGINPUT_DAC1_CH2 ((uint32_t)(COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0))
#define | COMP_INVERTINGINPUT_IO1 ((uint32_t)(COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1))
#define | COMP_INVERTINGINPUT_DAC2_CH1 ((uint32_t)COMP_CSR_COMPxINSEL)
#define | COMP_INVERTINGINPUT_DAC1 COMP_INVERTINGINPUT_DAC1_CH1
#define | COMP_INVERTINGINPUT_DAC2 COMP_INVERTINGINPUT_DAC1_CH2
#define | COMP_NONINVERTINGINPUT_IO1 (0x00000000U)
#define | COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP_CSR_COMP1SW1
#define | COMP_OUTPUT_NONE (0x0003U)
#define | COMP_OUTPUT_TIM2IC4 (0x0403U)
#define | COMP_OUTPUT_TIM2OCREFCLR (0x0503U)
#define | COMP_OUTPUT_TIM15BKIN (0x0101U)
#define | COMP_OUTPUT_COMP1_TIM3IC1 (0x0201U)
#define | COMP_OUTPUT_COMP1_TIM3OCREFCLR (0x0301U)
#define | COMP_OUTPUT_TIM5IC4 (0x0601U)
#define | COMP_OUTPUT_TIM5OCREFCLR (0x0701U)
#define | COMP_OUTPUT_TIM16BKIN (0x0102U)
#define | COMP_OUTPUT_TIM4IC1 (0x0202U)
#define | COMP_OUTPUT_TIM4OCREFCLR (0x0302U)
#define | COMP_OUTPUT_COMP2_TIM3IC1 (0x0602U)
#define | COMP_OUTPUT_COMP2_TIM3OCREFCLR (0x0702U)
#define | COMP_WINDOWMODE_DISABLE (0x00000000U)
#define | COMP_WINDOWMODE_ENABLE ((uint32_t)COMP_CSR_COMPxWNDWEN)
#define | COMP_MODE_HIGHSPEED (0x00000000U)
#define | COMP_MODE_MEDIUMSPEED COMP_CSR_COMPxMODE_0
#define | COMP_MODE_LOWPOWER COMP_CSR_COMPxMODE_1
#define | COMP_MODE_ULTRALOWPOWER COMP_CSR_COMPxMODE
#define | COMP_HYSTERESIS_NONE (0x00000000U)
#define | COMP_HYSTERESIS_LOW COMP_CSR_COMPxHYST_0
#define | COMP_HYSTERESIS_MEDIUM COMP_CSR_COMPxHYST_1
#define | COMP_HYSTERESIS_HIGH COMP_CSR_COMPxHYST
#define | COMP_BLANKINGSRCE_NONE (0x00000000U)
#define | COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
#define | __HAL_COMP_ENABLE(__HANDLE__)
Enable the specified comparator.
#define | __HAL_COMP_DISABLE(__HANDLE__)
Disable the specified comparator.
#define | __HAL_COMP_LOCK(__HANDLE__)
Lock a comparator instance.
#define | __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)
Check whether the specified COMP flag is set or not.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP1)
Generate a software interrupt on the COMP1 EXTI line.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1)
Check whether the COMP1 EXTI line flag is set or not.
#define | __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP1)
Clear the COMP1 EXTI flag.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP2)
Generate a software interrupt on the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2)
Check whether the COMP2 EXTI line flag is set or not.
#define | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2)
Clear the COMP2 EXTI flag.
#define | COMP_EXTI_LINE_COMP1 EXTI_IMR_MR21
#define | COMP_EXTI_LINE_COMP2 EXTI_IMR_MR22
#define | COMP_CSR_COMPxINSEL_MASK COMP_CSR_COMPxINSEL
#define | COMP_CSR_COMPxOUTSEL_MASK COMP_CSR_COMPxOUTSEL
#define | COMP_CSR_COMPxPOL_MASK COMP_CSR_COMPxPOL
#define | COMP_CSR_RESET_VALUE (0x00000000U)
#define | COMP_CSR_RESET_PARAMETERS_MASK (0x00003FFFU)
#define | COMP_CSR_UPDATE_PARAMETERS_MASK (0x00003FFEU)
#define | COMP_CSR_COMP1_SHIFT 0U
#define | COMP_CSR_COMP2_SHIFT 16U
#define | COMP_CSR_COMPxNONINSEL_MASK (COMP_CSR_COMP1SW1)
#define | COMP_CSR_COMPxWNDWEN_MASK COMP_CSR_COMPxWNDWEN
#define | COMP_CSR_COMPxMODE_MASK COMP_CSR_COMPxMODE
#define | COMP_CSR_COMPxHYST_MASK COMP_CSR_COMPxHYST
#define | COMP_CSR_COMPxBLANKING_MASK (0x00000000U)
#define | COMP_GET_EXTI_LINE(__INSTANCE__)
Get the specified EXTI line for a comparator instance.
#define | COMP_INIT(__HANDLE__)
Init a comparator instance.
#define | COMP_DEINIT(__HANDLE__)
DeInit a comparator instance.
#define | COMP_EXTI_RISING_ENABLE(__EXTILINE__) SET_BIT(EXTI->RTSR, (__EXTILINE__))
Enable the Exti Line rising edge trigger.
#define | COMP_EXTI_RISING_DISABLE(__EXTILINE__) CLEAR_BIT(EXTI->RTSR, (__EXTILINE__))
Disable the Exti Line rising edge trigger.
#define | COMP_EXTI_FALLING_ENABLE(__EXTILINE__) SET_BIT(EXTI->FTSR, (__EXTILINE__))
Enable the Exti Line falling edge trigger.
#define | COMP_EXTI_FALLING_DISABLE(__EXTILINE__) CLEAR_BIT(EXTI->FTSR, (__EXTILINE__))
Disable the Exti Line falling edge trigger.
#define | COMP_EXTI_ENABLE_IT(__EXTILINE__) SET_BIT(EXTI->IMR, (__EXTILINE__))
Enable the COMP Exti Line interrupt generation.
#define | COMP_EXTI_DISABLE_IT(__EXTILINE__) CLEAR_BIT(EXTI->IMR, (__EXTILINE__))
Disable the COMP Exti Line interrupt generation.
#define | COMP_EXTI_ENABLE_EVENT(__EXTILINE__) SET_BIT(EXTI->EMR, (__EXTILINE__))
Enable the COMP Exti Line event generation.
#define | COMP_EXTI_DISABLE_EVENT(__EXTILINE__) CLEAR_BIT(EXTI->EMR, (__EXTILINE__))
Disable the COMP Exti Line event generation.
#define | COMP_EXTI_GET_FLAG(__FLAG__) READ_BIT(EXTI->PR, (__FLAG__))
Check whether the specified EXTI line flag is set or not.
#define | COMP_EXTI_CLEAR_FLAG(__FLAG__) WRITE_REG(EXTI->PR, (__FLAG__))
Clear the COMP Exti flags.
#define | COMP_INVERTINGINPUT_SELECTION(__COMP_INSTANCE__, __INVERTINGINPUT__) (__INVERTINGINPUT__)
Manage inverting input comparator inverting input connected to a GPIO for STM32F302x, STM32F32xx, STM32F33x.
#define | IS_COMP_INVERTINGINPUT(INPUT)
#define | IS_COMP_NONINVERTINGINPUT(INPUT)
#define | IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT)
#define | IS_COMP_WINDOWMODE(WINDOWMODE)
#define | IS_COMP_MODE(MODE)
#define | IS_COMP_HYSTERESIS(HYSTERESIS)
#define | IS_COMP_OUTPUT(OUTPUT)
#define | IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT)
#define | IS_COMP_BLANKINGSRCE(SOURCE) ((SOURCE) == (SOURCE))
#define | IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE)

Detailed Description

Header file of COMP HAL Extended module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_comp_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_cortex.h File Reference

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Data Structures | Defines | Functions
stm32f3xx_hal_cortex.h File Reference

Header file of CORTEX HAL module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | MPU_Region_InitTypeDef

Defines

#define | NVIC_PRIORITYGROUP_0 (0x00000007U)
#define | NVIC_PRIORITYGROUP_1 (0x00000006U)
#define | NVIC_PRIORITYGROUP_2 (0x00000005U)
#define | NVIC_PRIORITYGROUP_3 (0x00000004U)
#define | NVIC_PRIORITYGROUP_4 (0x00000003U)
#define | SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U)
#define | SYSTICK_CLKSOURCE_HCLK (0x00000004U)
#define | MPU_HFNMI_PRIVDEF_NONE (0x00000000U)
#define | MPU_HARDFAULT_NMI (0x00000002U)
#define | MPU_PRIVILEGED_DEFAULT (0x00000004U)
#define | MPU_HFNMI_PRIVDEF (0x00000006U)
#define | MPU_REGION_ENABLE ((uint8_t)0x01U)
#define | MPU_REGION_DISABLE ((uint8_t)0x00U)
#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
#define | MPU_TEX_LEVEL0 ((uint8_t)0x00U)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01U)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02U)
#define | MPU_REGION_SIZE_32B ((uint8_t)0x04U)
#define | MPU_REGION_SIZE_64B ((uint8_t)0x05U)
#define | MPU_REGION_SIZE_128B ((uint8_t)0x06U)
#define | MPU_REGION_SIZE_256B ((uint8_t)0x07U)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08U)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01U)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05U)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
#define | MPU_REGION_NUMBER0 ((uint8_t)0x00U)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01U)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02U)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03U)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04U)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05U)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06U)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07U)
#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (pre-emption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initializes and configures the Region and the memory to be protected.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
void | HAL_MPU_Disable (void)
Disables the MPU also clears the HFNMIENA bit (ARM recommendation)
void | HAL_MPU_Enable (uint32_t MPU_Control)
Enables the MPU.

Detailed Description

Header file of CORTEX HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_cortex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_crc.h File Reference

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stm32f3xx_hal_crc.h File Reference

Header file of CRC HAL module. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_crc_ex.h"

Go to the source code of this file.

Data Structures

struct | CRC_InitTypeDef
CRC Init Structure definition. More...
struct | CRC_HandleTypeDef
CRC Handle Structure definition. More...

Defines

#define | DEFAULT_CRC32_POLY 0x04C11DB7
#define | DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
#define | DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)
#define | DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)
#define | CRC_POLYLENGTH_32B (0x00000000U)
#define | CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
#define | CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
#define | CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)
#define | HAL_CRC_LENGTH_32B 32
#define | HAL_CRC_LENGTH_16B 16
#define | HAL_CRC_LENGTH_8B 8
#define | HAL_CRC_LENGTH_7B 7
#define | CRC_INPUTDATA_FORMAT_UNDEFINED (0x00000000U)
#define | CRC_INPUTDATA_FORMAT_BYTES (0x00000001U)
#define | CRC_INPUTDATA_FORMAT_HALFWORDS (0x00000002U)
#define | CRC_INPUTDATA_FORMAT_WORDS (0x00000003U)
#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Reset CRC Data Register.
#define | __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
Set CRC INIT non-default value.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Store a 8-bit data in the Independent Data(ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Return the 8-bit data stored in the Independent Data(ID) register.
#define | IS_DEFAULT_POLYNOMIAL(DEFAULT)
#define | IS_DEFAULT_INIT_VALUE(VALUE)
#define | IS_CRC_POL_LENGTH(LENGTH)
#define | IS_CRC_INPUTDATA_FORMAT(FORMAT)
#define | HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
#define | HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00U, HAL_CRC_STATE_READY = 0x01U, HAL_CRC_STATE_BUSY = 0x02U, HAL_CRC_STATE_TIMEOUT = 0x03U,
HAL_CRC_STATE_ERROR = 0x04
}
CRC HAL State Structure definition. More...

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

Header file of CRC HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_crc.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_crc_ex.h File Reference

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stm32f3xx_hal_crc_ex.h File Reference

Header file of CRC HAL extension module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Defines

#define | CRC_INPUTDATA_INVERSION_NONE (0x00000000U)
#define | CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
#define | CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
#define | CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
#define | CRC_OUTPUTDATA_INVERSION_DISABLE (0x00000000U)
#define | CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)
#define | __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
Set CRC output reversal.
#define | __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
Unset CRC output reversal.
#define | __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
Set CRC non-default polynomial.
#define | IS_CRC_INPUTDATA_INVERSION_MODE(MODE)
#define | IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Header file of CRC HAL extension module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_crc_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_dac.h File Reference

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stm32f3xx_hal_dac.h File Reference

Header file of DAC HAL module. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_dac_ex.h"

Go to the source code of this file.

Data Structures

struct | DAC_ChannelConfTypeDef
DAC Configuration regular Channel structure definition. More...
struct | __DAC_HandleTypeDef
DAC handle Structure definition. More...

Defines

#define | HAL_DAC_ERROR_NONE 0x00
#define | HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01
#define | HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02
#define | HAL_DAC_ERROR_DMA 0x04
#define | DAC_LFSRUNMASK_BIT0 (0x00000000U)
#define | DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_1 (0x00000000U)
#define | DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_OUTPUTBUFFER_ENABLE (0x00000000U)
#define | DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
#define | DAC_ALIGN_12B_R (0x00000000U)
#define | DAC_ALIGN_12B_L (0x00000004U)
#define | DAC_ALIGN_8B_R (0x00000008U)
#define | DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#define | DAC_IT_DMAUDR1 ((uint32_t)DAC_CR_DMAUDRIE1)
#define | DAC_IT_DMAUDR2 ((uint32_t)DAC_CR_DMAUDRIE2)
#define | __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
Reset DAC handle state.
#define | __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
Enable the DAC channel.
#define | __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
Disable the DAC channel.
#define | DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__))
Set DHR12R1 alignment.
#define | DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__))
Set DHR12R2 alignment.
#define | DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__))
Set DHR12RD alignment.
#define | __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the DAC interrupt.
#define | __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the DAC interrupt.
#define | __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified DAC interrupt source is enabled or not.
#define | __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected DAC's flag status.
#define | __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
Clear the DAC's flag.
#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)
#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)

Typedefs

typedef struct __DAC_HandleTypeDef | DAC_HandleTypeDef
DAC handle Structure definition.

Enumerations

enum HAL_DAC_StateTypeDef {
HAL_DAC_STATE_RESET = 0x00U, HAL_DAC_STATE_READY = 0x01U, HAL_DAC_STATE_BUSY = 0x02U, HAL_DAC_STATE_TIMEOUT = 0x03U,
HAL_DAC_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.
__weak HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
__weak uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request This function uses the interruption of DMA underrun.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for Channel1.
__weak HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.

Detailed Description

Header file of DAC HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_dac.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_dac_ex.h File Reference

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stm32f3xx_hal_dac_ex.h File Reference

Header file of DAC HAL Extended module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Defines

#define | DAC_TRIGGER_NONE (0x00000000U)
#define | DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T18_TRGO DAC_TRIGGER_T5_TRGO
#define | DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1)
#define | DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1))
#define | IS_DAC_TRIGGER(TRIGGER)
#define | DAC_CHANNEL_1 (0x00000000U)
#define | DAC_CHANNEL_2 (0x00000010U)
#define | IS_DAC_CHANNEL(CHANNEL)

Functions

uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel2.

Detailed Description

Header file of DAC HAL Extended module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_dac_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_dma.h File Reference

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stm32f3xx_hal_dma.h File Reference

Header file of DMA HAL module. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_dma_ex.h"

Go to the source code of this file.

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Defines

#define | HAL_DMA_ERROR_NONE (0x00000000U)
#define | HAL_DMA_ERROR_TE (0x00000001U)
#define | HAL_DMA_ERROR_NO_XFER (0x00000004U)
#define | HAL_DMA_ERROR_TIMEOUT (0x00000020U)
#define | HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U)
#define | DMA_PERIPH_TO_MEMORY (0x00000000U)
#define | DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR)
#define | DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM)
#define | DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC)
#define | DMA_PINC_DISABLE (0x00000000U)
#define | DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC)
#define | DMA_MINC_DISABLE (0x00000000U)
#define | DMA_PDATAALIGN_BYTE (0x00000000U)
#define | DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0)
#define | DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1)
#define | DMA_MDATAALIGN_BYTE (0x00000000U)
#define | DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0)
#define | DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1)
#define | DMA_NORMAL (0x00000000U)
#define | DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC)
#define | DMA_PRIORITY_LOW (0x00000000U)
#define | DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0)
#define | DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1)
#define | DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL)
#define | DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
#define | DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
#define | DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
#define | DMA_FLAG_GL1 (0x00000001U)
#define | DMA_FLAG_TC1 (0x00000002U)
#define | DMA_FLAG_HT1 (0x00000004U)
#define | DMA_FLAG_TE1 (0x00000008U)
#define | DMA_FLAG_GL2 (0x00000010U)
#define | DMA_FLAG_TC2 (0x00000020U)
#define | DMA_FLAG_HT2 (0x00000040U)
#define | DMA_FLAG_TE2 (0x00000080U)
#define | DMA_FLAG_GL3 (0x00000100U)
#define | DMA_FLAG_TC3 (0x00000200U)
#define | DMA_FLAG_HT3 (0x00000400U)
#define | DMA_FLAG_TE3 (0x00000800U)
#define | DMA_FLAG_GL4 (0x00001000U)
#define | DMA_FLAG_TC4 (0x00002000U)
#define | DMA_FLAG_HT4 (0x00004000U)
#define | DMA_FLAG_TE4 (0x00008000U)
#define | DMA_FLAG_GL5 (0x00010000U)
#define | DMA_FLAG_TC5 (0x00020000U)
#define | DMA_FLAG_HT5 (0x00040000U)
#define | DMA_FLAG_TE5 (0x00080000U)
#define | DMA_FLAG_GL6 (0x00100000U)
#define | DMA_FLAG_TC6 (0x00200000U)
#define | DMA_FLAG_HT6 (0x00400000U)
#define | DMA_FLAG_TE6 (0x00800000U)
#define | DMA_FLAG_GL7 (0x01000000U)
#define | DMA_FLAG_TC7 (0x02000000U)
#define | DMA_FLAG_HT7 (0x04000000U)
#define | DMA_FLAG_TE7 (0x08000000U)
#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
Enable the specified DMA Channel.
#define | __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
Disable the specified DMA Channel.
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
Enables the specified DMA Channel interrupts.
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
Disables the specified DMA Channel interrupts.
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
Checks whether the specified DMA Channel interrupt is enabled or disabled.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
Returns the number of remaining data units in the current DMAy Channelx transfer.
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum | HAL_DMA_StateTypeDef { HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_TIMEOUT = 0x03 }
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01 }
HAL DMA Error Code structure definition. More...
enum HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_ERROR_CB_ID = 0x02U, HAL_DMA_XFER_ABORT_CB_ID = 0x03U,
HAL_DMA_XFER_ALL_CB_ID = 0x04
}
HAL DMA Callback ID structure definition. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handle DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Returns the DMA state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Header file of DMA HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_dma.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_dma_ex.h File Reference

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Defines
stm32f3xx_hal_dma_ex.h File Reference

Header file of DMA HAL extension module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Defines

#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Returns the current DMA Channel transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Returns the current DMA Channel half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Returns the current DMA Channel transfer error flag.
#define | __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel Global interrupt flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Channel pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clears the DMA Channel pending flags.

Detailed Description

Header file of DMA HAL extension module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_dma_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_flash.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32f3xx_hal_flash.h File Reference

Header file of Flash HAL module. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_flash_ex.h"

Go to the source code of this file.

Data Structures

struct | FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Defines

#define | FLASH_TIMEOUT_VALUE (50000U) /* 50 s */
#define | IS_FLASH_TYPEPROGRAM(VALUE)
#define | IS_FLASH_LATENCY(__LATENCY__)
#define | HAL_FLASH_ERROR_NONE 0x00U
#define | HAL_FLASH_ERROR_PROG 0x01U
#define | HAL_FLASH_ERROR_WRP 0x02U
#define | FLASH_TYPEPROGRAM_HALFWORD (0x01U)
#define | FLASH_TYPEPROGRAM_WORD (0x02U)
#define | FLASH_TYPEPROGRAM_DOUBLEWORD (0x03U)
#define | FLASH_LATENCY_0 (0x00000000U)
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_0
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_1
#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_FLAG_PGERR FLASH_SR_PGERR
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_IT_EOP FLASH_CR_EOPIE
#define | FLASH_IT_ERR FLASH_CR_ERRIE
#define | __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)
Enable the FLASH half cycle access.
#define | __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
Disable the FLASH half cycle access.
#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
Get the FLASH Latency.
#define | __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
Enable the FLASH prefetch buffer.
#define | __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
Disable the FLASH prefetch buffer.
#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__))
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__))
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__))
Get the specified FLASH flag status.
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__))
Clear the specified FLASH flag.

Enumerations

enum FLASH_ProcedureTypeDef {
FLASH_PROC_NONE = 0U, FLASH_PROC_PAGEERASE = 1U, FLASH_PROC_MASSERASE = 2U, FLASH_PROC_PROGRAMHALFWORD = 3U,
FLASH_PROC_PROGRAMWORD = 4U, FLASH_PROC_PROGRAMDOUBLEWORD = 5U
}
FLASH Procedure structure definition. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program halfword, word or double word at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program halfword, word or double word at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Detailed Description

Header file of Flash HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_flash.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_flash_ex.h File Reference

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stm32f3xx_hal_flash_ex.h File Reference

Header file of Flash HAL Extended module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Options bytes program structure definition. More...

Defines

#define | FLASH_SIZE_DATA_REGISTER (0x1FFFF7CCU)
#define | IS_FLASH_TYPEERASE(VALUE)
#define | IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))
#define | IS_WRPSTATE(VALUE)
#define | IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
#define | IS_OB_RDP_LEVEL(LEVEL)
#define | IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define | IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define | IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define | IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
#define | IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
#define | IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
#define | IS_OB_SDACD_VDD_MONITOR(VDD_MONITOR)
#define | IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
#define | IS_FLASH_PROGRAM_ADDRESS(ADDRESS)
#define | IS_FLASH_NB_PAGES(ADDRESS, NBPAGES)
#define | FLASH_PAGE_SIZE 0x800
#define | FLASH_TYPEERASE_PAGES (0x00U)
#define | FLASH_TYPEERASE_MASSERASE (0x01U)
#define | OPTIONBYTE_WRP (0x01U)
#define | OPTIONBYTE_RDP (0x02U)
#define | OPTIONBYTE_USER (0x04U)
#define | OPTIONBYTE_DATA (0x08U)
#define | OB_WRPSTATE_DISABLE (0x00U)
#define | OB_WRPSTATE_ENABLE (0x01U)
#define | OB_WRP_PAGES0TO1 (0x00000001U) /* Write protection of page 0 to 1 */
#define | OB_WRP_PAGES2TO3 (0x00000002U) /* Write protection of page 2 to 3 */
#define | OB_WRP_PAGES4TO5 (0x00000004U) /* Write protection of page 4 to 5 */
#define | OB_WRP_PAGES6TO7 (0x00000008U) /* Write protection of page 6 to 7 */
#define | OB_WRP_PAGES8TO9 (0x00000010U) /* Write protection of page 8 to 9 */
#define | OB_WRP_PAGES10TO11 (0x00000020U) /* Write protection of page 10 to 11 */
#define | OB_WRP_PAGES12TO13 (0x00000040U) /* Write protection of page 12 to 13 */
#define | OB_WRP_PAGES14TO15 (0x00000080U) /* Write protection of page 14 to 15 */
#define | OB_WRP_PAGES16TO17 (0x00000100U) /* Write protection of page 16 to 17 */
#define | OB_WRP_PAGES18TO19 (0x00000200U) /* Write protection of page 18 to 19 */
#define | OB_WRP_PAGES20TO21 (0x00000400U) /* Write protection of page 20 to 21 */
#define | OB_WRP_PAGES22TO23 (0x00000800U) /* Write protection of page 22 to 23 */
#define | OB_WRP_PAGES24TO25 (0x00001000U) /* Write protection of page 24 to 25 */
#define | OB_WRP_PAGES26TO27 (0x00002000U) /* Write protection of page 26 to 27 */
#define | OB_WRP_PAGES28TO29 (0x00004000U) /* Write protection of page 28 to 29 */
#define | OB_WRP_PAGES30TO31 (0x00008000U) /* Write protection of page 30 to 31 */
#define | OB_WRP_PAGES32TO33 (0x00010000U) /* Write protection of page 32 to 33 */
#define | OB_WRP_PAGES34TO35 (0x00020000U) /* Write protection of page 34 to 35 */
#define | OB_WRP_PAGES36TO37 (0x00040000U) /* Write protection of page 36 to 37 */
#define | OB_WRP_PAGES38TO39 (0x00080000U) /* Write protection of page 38 to 39 */
#define | OB_WRP_PAGES40TO41 (0x00100000U) /* Write protection of page 40 to 41 */
#define | OB_WRP_PAGES42TO43 (0x00200000U) /* Write protection of page 42 to 43 */
#define | OB_WRP_PAGES44TO45 (0x00400000U) /* Write protection of page 44 to 45 */
#define | OB_WRP_PAGES46TO47 (0x00800000U) /* Write protection of page 46 to 47 */
#define | OB_WRP_PAGES48TO49 (0x01000000U) /* Write protection of page 48 to 49 */
#define | OB_WRP_PAGES50TO51 (0x02000000U) /* Write protection of page 50 to 51 */
#define | OB_WRP_PAGES52TO53 (0x04000000U) /* Write protection of page 52 to 53 */
#define | OB_WRP_PAGES54TO55 (0x08000000U) /* Write protection of page 54 to 55 */
#define | OB_WRP_PAGES56TO57 (0x10000000U) /* Write protection of page 56 to 57 */
#define | OB_WRP_PAGES58TO59 (0x20000000U) /* Write protection of page 58 to 59 */
#define | OB_WRP_PAGES60TO61 (0x40000000U) /* Write protection of page 60 to 61 */
#define | OB_WRP_PAGES62TO127 (0x80000000U) /* Write protection of page 62 to 127 */
#define | OB_WRP_PAGES0TO15MASK (0x000000FFU)
#define | OB_WRP_PAGES16TO31MASK (0x0000FF00U)
#define | OB_WRP_PAGES32TO47MASK (0x00FF0000U)
#define | OB_WRP_PAGES48TO127MASK (0xFF000000U)
#define | OB_WRP_PAGES32TO47MASK (0x00FF0000U)
#define | OB_WRP_PAGES48TO127MASK (0xFF000000U)
#define | OB_WRP_ALLPAGES (0xFFFFFFFFU)
#define | OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
#define | OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
#define | OB_RDP_LEVEL_2 ((uint8_t)0xCCU)
#define | OB_IWDG_SW ((uint8_t)0x01U)
#define | OB_IWDG_HW ((uint8_t)0x00U)
#define | OB_STOP_NO_RST ((uint8_t)0x02U)
#define | OB_STOP_RST ((uint8_t)0x00U)
#define | OB_STDBY_NO_RST ((uint8_t)0x04U)
#define | OB_STDBY_RST ((uint8_t)0x00U)
#define | OB_BOOT1_RESET ((uint8_t)0x00U)
#define | OB_BOOT1_SET ((uint8_t)0x10U)
#define | OB_VDDA_ANALOG_ON ((uint8_t)0x20U)
#define | OB_VDDA_ANALOG_OFF ((uint8_t)0x00U)
#define | OB_SRAM_PARITY_SET ((uint8_t)0x00U)
#define | OB_SRAM_PARITY_RESET ((uint8_t)0x40U)
#define | OB_SDACD_VDD_MONITOR_RESET ((uint8_t)0x00U)
#define | OB_SDACD_VDD_MONITOR_SET ((uint8_t)0x80U)
#define | OB_DATA_ADDRESS_DATA0 (0x1FFFF804U)
#define | OB_DATA_ADDRESS_DATA1 (0x1FFFF806U)

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBErase (void)
Erases the FLASH option bytes.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
uint32_t | HAL_FLASHEx_OBGetUserData (uint32_t DATAAdress)
Get the Option byte user data.

Detailed Description

Header file of Flash HAL Extended module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_flash_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_gpio.h File Reference

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stm32f3xx_hal_gpio.h File Reference

Header file of GPIO HAL module. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_gpio_ex.h"

Go to the source code of this file.

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
#define | GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
#define | GPIO_MODE_INPUT (0x00000000U)
#define | GPIO_MODE_OUTPUT_PP (0x00000001U)
#define | GPIO_MODE_OUTPUT_OD (0x00000011U)
#define | GPIO_MODE_AF_PP (0x00000002U)
#define | GPIO_MODE_AF_OD (0x00000012U)
#define | GPIO_MODE_ANALOG (0x00000003U)
#define | GPIO_MODE_IT_RISING (0x10110000U)
#define | GPIO_MODE_IT_FALLING (0x10210000U)
#define | GPIO_MODE_IT_RISING_FALLING (0x10310000U)
#define | GPIO_MODE_EVT_RISING (0x10120000U)
#define | GPIO_MODE_EVT_FALLING (0x10220000U)
#define | GPIO_MODE_EVT_RISING_FALLING (0x10320000U)
#define | GPIO_SPEED_FREQ_LOW (0x00000000U)
#define | GPIO_SPEED_FREQ_MEDIUM (0x00000001U)
#define | GPIO_SPEED_FREQ_HIGH (0x00000003U)
#define | GPIO_NOPULL (0x00000000U)
#define | GPIO_PULLUP (0x00000001U)
#define | GPIO_PULLDOWN (0x00000002U)
#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
Check whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
Clear the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
Check whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
Clear the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
Generate a Software interrupt on selected EXTI line.
#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(__PIN__)
#define | IS_GPIO_MODE(__MODE__)
#define | IS_GPIO_SPEED(__SPEED__)
#define | IS_GPIO_PULL(__PULL__)

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0U, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initialize the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Read the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Set or clear the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggle the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Lock GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

Header file of GPIO HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_gpio.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_gpio_ex.h File Reference

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Defines
stm32f3xx_hal_gpio_ex.h File Reference

Header file of GPIO HAL Extended module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Defines

#define | GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
AF 0 selection.
#define | GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define | GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
#define | GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define | GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
#define | GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
AF 1 selection.
#define | GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
#define | GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
#define | GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
#define | GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
#define | GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
AF 2 selection.
#define | GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
#define | GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
#define | GPIO_AF2_TIM13 ((uint8_t)0x02U) /* TIM13 Alternate Function mapping */
#define | GPIO_AF2_TIM14 ((uint8_t)0x02U) /* TIM14 Alternate Function mapping */
#define | GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
#define | GPIO_AF2_TIM19 ((uint8_t)0x02U) /* TIM19 Alternate Function mapping */
#define | GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
AF 3 selection.
#define | GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
AF 4 selection.
#define | GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
#define | GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
AF 5 selection.
#define | GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
#define | GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
#define | GPIO_AF6_SPI1 ((uint8_t)0x06U) /* SPI1/I2S1 Alternate Function mapping */
AF 6 selection.
#define | GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
#define | GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
#define | GPIO_AF6_CEC ((uint8_t)0x06U) /* CEC Alternate Function mapping */
#define | GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
AF 7 selection.
#define | GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
#define | GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
#define | GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
#define | GPIO_AF7_CEC ((uint8_t)0x07U) /* CEC Alternate Function mapping */
#define | GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
AF 8 selection.
#define | GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
#define | GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
AF 9 selection.
#define | GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */
#define | GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
#define | GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
#define | GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
#define | GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
AF 10 selection.
#define | GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
#define | GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
#define | GPIO_AF10_TIM12 ((uint8_t)0xAU) /* TIM12 Alternate Function mapping */
#define | GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
#define | GPIO_AF11_TIM19 ((uint8_t)0x0BU) /* TIM19 Alternate Function mapping */
AF 11 selection.
#define | GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */
AF 14 selection.
#define | GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
AF 15 selection.
#define | IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0BU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
#define | GPIO_GET_INDEX(__GPIOx__)

Detailed Description

Header file of GPIO HAL Extended module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_gpio_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_i2c.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32f3xx_hal_i2c.h File Reference

Header file of I2C HAL module. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_i2c_ex.h"

Go to the source code of this file.

Data Structures

struct | I2C_InitTypeDef
struct | __I2C_HandleTypeDef

Defines

#define | HAL_I2C_ERROR_NONE (0x00000000U)
#define | HAL_I2C_ERROR_BERR (0x00000001U)
#define | HAL_I2C_ERROR_ARLO (0x00000002U)
#define | HAL_I2C_ERROR_AF (0x00000004U)
#define | HAL_I2C_ERROR_OVR (0x00000008U)
#define | HAL_I2C_ERROR_DMA (0x00000010U)
#define | HAL_I2C_ERROR_TIMEOUT (0x00000020U)
#define | HAL_I2C_ERROR_SIZE (0x00000040U)
#define | I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define | I2C_ADDRESSINGMODE_10BIT (0x00000002U)
#define | I2C_DUALADDRESS_DISABLE (0x00000000U)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define | I2C_OA2_NOMASK ((uint8_t)0x00U)
#define | I2C_OA2_MASK01 ((uint8_t)0x01U)
#define | I2C_OA2_MASK02 ((uint8_t)0x02U)
#define | I2C_OA2_MASK03 ((uint8_t)0x03U)
#define | I2C_OA2_MASK04 ((uint8_t)0x04U)
#define | I2C_OA2_MASK05 ((uint8_t)0x05U)
#define | I2C_OA2_MASK06 ((uint8_t)0x06U)
#define | I2C_OA2_MASK07 ((uint8_t)0x07U)
#define | I2C_GENERALCALL_DISABLE (0x00000000U)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
#define | I2C_NOSTRETCH_DISABLE (0x00000000U)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define | I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define | I2C_MEMADD_SIZE_16BIT (0x00000002U)
#define | I2C_DIRECTION_TRANSMIT (0x00000000U)
#define | I2C_DIRECTION_RECEIVE (0x00000001U)
#define | I2C_RELOAD_MODE I2C_CR2_RELOAD
#define | I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define | I2C_SOFTEND_MODE (0x00000000U)
#define | I2C_NO_STARTSTOP (0x00000000U)
#define | I2C_GENERATE_STOP I2C_CR2_STOP
#define | I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | I2C_GENERATE_START_WRITE I2C_CR2_START
#define | I2C_IT_ERRI I2C_CR1_ERRIE
#define | I2C_IT_TCI I2C_CR1_TCIE
#define | I2C_IT_STOPI I2C_CR1_STOPIE
#define | I2C_IT_NACKI I2C_CR1_NACKIE
#define | I2C_IT_ADDRI I2C_CR1_ADDRIE
#define | I2C_IT_RXI I2C_CR1_RXIE
#define | I2C_IT_TXI I2C_CR1_TXIE
#define | I2C_FLAG_TXE I2C_ISR_TXE
#define | I2C_FLAG_TXIS I2C_ISR_TXIS
#define | I2C_FLAG_RXNE I2C_ISR_RXNE
#define | I2C_FLAG_ADDR I2C_ISR_ADDR
#define | I2C_FLAG_AF I2C_ISR_NACKF
#define | I2C_FLAG_STOPF I2C_ISR_STOPF
#define | I2C_FLAG_TC I2C_ISR_TC
#define | I2C_FLAG_TCR I2C_ISR_TCR
#define | I2C_FLAG_BERR I2C_ISR_BERR
#define | I2C_FLAG_ARLO I2C_ISR_ARLO
#define | I2C_FLAG_OVR I2C_ISR_OVR
#define | I2C_FLAG_PECERR I2C_ISR_PECERR
#define | I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | I2C_FLAG_ALERT I2C_ISR_ALERT
#define | I2C_FLAG_BUSY I2C_ISR_BUSY
#define | I2C_FLAG_DIR I2C_ISR_DIR
#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified I2C interrupt.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified I2C interrupt.
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified I2C interrupt source is enabled or not.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
Check whether the specified I2C flag is set or not.
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified I2C peripheral.
#define | __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge I2C peripheral in Slave mode.
#define | IS_I2C_ADDRESSING_MODE(MODE)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
#define | I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define | I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
#define | I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define | I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_GENERATE_START(__ADDMODE__, __ADDRESS__)

Typedefs

typedef struct __I2C_HandleTypeDef | I2C_HandleTypeDef

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_ABORT = 0x60U, HAL_I2C_STATE_TIMEOUT = 0xA0U, HAL_I2C_STATE_ERROR = 0xE0U
}
enum | HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Header file of I2C HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_i2c.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_i2c_ex.h File Reference

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Defines | Functions
stm32f3xx_hal_i2c_ex.h File Reference

Header file of I2C HAL Extended module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Defines

#define | I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | I2C_FMP_NOT_SUPPORTED 0xAAAA0000U
#define | I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED)
#define | IS_I2C_ANALOG_FILTER(FILTER)
#define | IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_I2C_FASTMODEPLUS(__CONFIG__)

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from stop mode.
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from stop mode.
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

Header file of I2C HAL Extended module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_i2c_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_i2s.h File Reference

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stm32f3xx_hal_i2s.h File Reference

Header file of I2S HAL module. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_i2s_ex.h"

Go to the source code of this file.

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | I2S_HandleTypeDef
I2S handle Structure definition. More...

Defines

#define | HAL_I2S_ERROR_NONE (0x00000000U)
#define | HAL_I2S_ERROR_TIMEOUT (0x00000001U)
#define | HAL_I2S_ERROR_OVR (0x00000002U)
#define | HAL_I2S_ERROR_UDR (0x00000004U)
#define | HAL_I2S_ERROR_DMA (0x00000008U)
#define | HAL_I2S_ERROR_UNKNOW (0x00000010U)
#define | I2S_CLOCK_EXTERNAL (0x00000001U)
#define | I2S_CLOCK_SYSCLK (0x00000002U)
#define | IS_I2S_CLOCKSOURCE(CLOCK)
#define | I2S_MODE_SLAVE_TX (0x00000000U)
#define | I2S_MODE_SLAVE_RX (0x00000100U)
#define | I2S_MODE_MASTER_TX (0x00000200U)
#define | I2S_MODE_MASTER_RX (0x00000300U)
#define | IS_I2S_MODE(MODE)
#define | I2S_STANDARD_PHILIPS (0x00000000U)
#define | I2S_STANDARD_MSB (0x00000010U)
#define | I2S_STANDARD_LSB (0x00000020U)
#define | I2S_STANDARD_PCM_SHORT (0x00000030U)
#define | I2S_STANDARD_PCM_LONG (0x000000B0U)
#define | IS_I2S_STANDARD(STANDARD)
#define | I2S_DATAFORMAT_16B (0x00000000U)
#define | I2S_DATAFORMAT_16B_EXTENDED (0x00000001U)
#define | I2S_DATAFORMAT_24B (0x00000003U)
#define | I2S_DATAFORMAT_32B (0x00000005U)
#define | IS_I2S_DATA_FORMAT(FORMAT)
#define | I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
#define | I2S_MCLKOUTPUT_DISABLE (0x00000000U)
#define | IS_I2S_MCLK_OUTPUT(OUTPUT)
#define | I2S_AUDIOFREQ_192K (192000U)
#define | I2S_AUDIOFREQ_96K (96000U)
#define | I2S_AUDIOFREQ_48K (48000U)
#define | I2S_AUDIOFREQ_44K (44100U)
#define | I2S_AUDIOFREQ_32K (32000U)
#define | I2S_AUDIOFREQ_22K (22050U)
#define | I2S_AUDIOFREQ_16K (16000U)
#define | I2S_AUDIOFREQ_11K (11025U)
#define | I2S_AUDIOFREQ_8K (8000U)
#define | I2S_AUDIOFREQ_DEFAULT (2U)
#define | IS_I2S_AUDIO_FREQ(FREQ)
#define | I2S_FULLDUPLEXMODE_DISABLE (0x00000000U)
#define | I2S_FULLDUPLEXMODE_ENABLE (0x00000001U)
#define | IS_I2S_FULLDUPLEX_MODE(MODE)
#define | I2S_CPOL_LOW (0x00000000U)
#define | I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
#define | IS_I2S_CPOL(CPOL)
#define | I2S_IT_TXE SPI_CR2_TXEIE
#define | I2S_IT_RXNE SPI_CR2_RXNEIE
#define | I2S_IT_ERR SPI_CR2_ERRIE
#define | I2S_FLAG_TXE SPI_SR_TXE
#define | I2S_FLAG_RXNE SPI_SR_RXNE
#define | I2S_FLAG_UDR SPI_SR_UDR
#define | I2S_FLAG_OVR SPI_SR_OVR
#define | I2S_FLAG_FRE SPI_SR_FRE
#define | I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define | I2S_FLAG_BSY SPI_SR_BSY
#define | __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
Reset I2S handle state.
#define | __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
Enable or disable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SE))
#define | __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enable or disable the specified I2S interrupts.
#define | __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__)))
#define | __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified I2S interrupt source is enabled or disabled.
#define | __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified I2S flag is set or not.
#define | __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)
Clears the I2S OVR pending flag.
#define | __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)
Clears the I2S UDR pending flag.

Enumerations

enum HAL_I2S_StateTypeDef {
HAL_I2S_STATE_RESET = 0x00U, HAL_I2S_STATE_READY = 0x01U, HAL_I2S_STATE_BUSY = 0x02U, HAL_I2S_STATE_BUSY_TX = 0x03U,
HAL_I2S_STATE_BUSY_RX = 0x04U, HAL_I2S_STATE_BUSY_TX_RX = 0x05U, HAL_I2S_STATE_TIMEOUT = 0x06U, HAL_I2S_STATE_ERROR = 0x07
}
HAL State structures definition. More...

Functions

__weak HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.
HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
__weak HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio stream playing from the Media.
__weak HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
__weak HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.
HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

Header file of I2S HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_i2s.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_i2s_ex.h File Reference

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Functions
stm32f3xx_hal_i2s_ex.h File Reference

Header file of I2S HAL Extended module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.

Detailed Description

Header file of I2S HAL Extended module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_i2s_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_irda.h File Reference

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stm32f3xx_hal_irda.h File Reference

This file contains all the functions prototypes for the IRDA firmware library. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_irda_ex.h"

Go to the source code of this file.

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Defines

#define | HAL_IRDA_ERROR_NONE (0x00000000U)
#define | HAL_IRDA_ERROR_PE (0x00000001U)
#define | HAL_IRDA_ERROR_NE (0x00000002U)
#define | HAL_IRDA_ERROR_FE (0x00000004U)
#define | HAL_IRDA_ERROR_ORE (0x00000008U)
#define | HAL_IRDA_ERROR_DMA (0x00000010U)
#define | HAL_IRDA_ERROR_BUSY (0x00000020U)
#define | IRDA_PARITY_NONE (0x00000000U)
#define | IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
#define | IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
#define | IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | IRDA_POWERMODE_NORMAL (0x00000000U)
#define | IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
#define | IRDA_STATE_DISABLE (0x00000000U)
#define | IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)
#define | IRDA_MODE_DISABLE (0x00000000U)
#define | IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)
#define | IRDA_ONE_BIT_SAMPLE_DISABLE (0x00000000U)
#define | IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
#define | IRDA_DMA_TX_DISABLE (0x00000000U)
#define | IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
#define | IRDA_DMA_RX_DISABLE (0x00000000U)
#define | IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
#define | IRDA_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ)
#define | IRDA_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | IRDA_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)
#define | IRDA_FLAG_REACK (0x00400000U)
#define | IRDA_FLAG_TEACK (0x00200000U)
#define | IRDA_FLAG_BUSY (0x00010000U)
#define | IRDA_FLAG_ABRF (0x00008000U)
#define | IRDA_FLAG_ABRE (0x00004000U)
#define | IRDA_FLAG_TXE (0x00000080U)
#define | IRDA_FLAG_TC (0x00000040U)
#define | IRDA_FLAG_RXNE (0x00000020U)
#define | IRDA_FLAG_ORE (0x00000008U)
#define | IRDA_FLAG_NE (0x00000004U)
#define | IRDA_FLAG_FE (0x00000002U)
#define | IRDA_FLAG_PE (0x00000001U)
#define | IRDA_IT_PE ((uint16_t)0x0028U)
#define | IRDA_IT_TXE ((uint16_t)0x0727U)
#define | IRDA_IT_TC ((uint16_t)0x0626U)
#define | IRDA_IT_RXNE ((uint16_t)0x0525U)
#define | IRDA_IT_IDLE ((uint16_t)0x0424U)
#define | IRDA_IT_ERR ((uint16_t)0x0060U)
#define | IRDA_IT_ORE ((uint16_t)0x0300U)
#define | IRDA_IT_NE ((uint16_t)0x0200U)
#define | IRDA_IT_FE ((uint16_t)0x0100U)
#define | IRDA_CLEAR_PEF USART_ICR_PECF
#define | IRDA_CLEAR_FEF USART_ICR_FECF
#define | IRDA_CLEAR_NEF USART_ICR_NCF
#define | IRDA_CLEAR_OREF USART_ICR_ORECF
#define | IRDA_CLEAR_IDLEF USART_ICR_IDLECF
#define | IRDA_CLEAR_TCF USART_ICR_TCCF
#define | IRDA_IT_MASK ((uint16_t)0x001FU)
#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle state.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)
Flush the IRDA DR register.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified IRDA interrupt source is enabled or not.
#define | __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
#define | __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific IRDA request flag.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the IRDA one bit sample method.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the IRDA one bit sample method.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.
#define | IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
Ensure that IRDA Baud rate is less or equal to maximum value.
#define | IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
Ensure that IRDA prescaler value is strictly larger than 0.
#define | IS_IRDA_PARITY(__PARITY__)
Ensure that IRDA frame parity is valid.
#define | IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that IRDA communication mode is valid.
#define | IS_IRDA_POWERMODE(__MODE__)
Ensure that IRDA power mode is valid.
#define | IS_IRDA_STATE(__STATE__)
Ensure that IRDA state is valid.
#define | IS_IRDA_MODE(__MODE__)
Ensure that IRDA associated UART/USART mode is valid.
#define | IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that IRDA sampling rate is valid.
#define | IS_IRDA_DMA_TX(__DMATX__)
Ensure that IRDA DMA TX mode is valid.
#define | IS_IRDA_DMA_RX(__DMARX__)
Ensure that IRDA DMA RX mode is valid.
#define | IS_IRDA_REQUEST_PARAMETER(__PARAM__)
Ensure that IRDA request is valid.

Enumerations

enum HAL_IRDA_StateTypeDef {
HAL_IRDA_STATE_RESET = 0x00U, HAL_IRDA_STATE_READY = 0x20U, HAL_IRDA_STATE_BUSY = 0x24U, HAL_IRDA_STATE_BUSY_TX = 0x21U,
HAL_IRDA_STATE_BUSY_RX = 0x22U, HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, HAL_IRDA_STATE_TIMEOUT = 0xA0U, HAL_IRDA_STATE_ERROR = 0xE0U
}
HAL IRDA State structures definition. More...
enum IRDA_ClockSourceTypeDef {
IRDA_CLOCKSOURCE_PCLK1 = 0x00U, IRDA_CLOCKSOURCE_PCLK2 = 0x01U, IRDA_CLOCKSOURCE_HSI = 0x02U, IRDA_CLOCKSOURCE_SYSCLK = 0x04U,
IRDA_CLOCKSOURCE_LSE = 0x08U, IRDA_CLOCKSOURCE_UNDEFINED = 0x10U
}
IRDA clock sources definition. More...
enum IRDA_ControlTypeDef {
IRDA_BAUDRATE = 0x00U, IRDA_PARITY = 0x01U, IRDA_WORDLENGTH = 0x02U, IRDA_MODE = 0x03U,
IRDA_PRESCALER = 0x04U, IRDA_POWERMODE = 0x05U
}
IRDA Configuration enumeration values definition. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

This file contains all the functions prototypes for the IRDA firmware library.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_irda.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_irda_ex.h File Reference

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Defines
stm32f3xx_hal_irda_ex.h File Reference

Header file of IRDA HAL Extended module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Defines

#define | IRDA_WORDLENGTH_8B (0x00000000U)
#define | IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
#define | IRDA_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the IRDA clock source.
#define | IRDA_MASK_COMPUTATION(__HANDLE__)
Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_IRDA_WORD_LENGTH(__LENGTH__)
Ensure that IRDA frame length is valid.

Detailed Description

Header file of IRDA HAL Extended module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_irda_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_iwdg.h File Reference

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stm32f3xx_hal_iwdg.h File Reference

Header file of IWDG HAL module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...

Defines

#define | IWDG_PRESCALER_4 0x00000000u
#define | IWDG_PRESCALER_8 IWDG_PR_PR_0
#define | IWDG_PRESCALER_16 IWDG_PR_PR_1
#define | IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_64 IWDG_PR_PR_2
#define | IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)
#define | IWDG_WINDOW_DISABLE IWDG_WINR_WIN
#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enable the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
#define | IWDG_KEY_RELOAD 0x0000AAAAu
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE 0x0000CCCCu
#define | IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u
#define | IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u
#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
Check IWDG reload value.
#define | IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
Check IWDG window value.

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

Header file of IWDG HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_iwdg.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pcd.h File Reference

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stm32f3xx_hal_pcd.h File Reference

Header file of PCD HAL module. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_pcd_ex.h"

Go to the source code of this file.

Data Structures

struct | PCD_InitTypeDef
PCD Initialization Structure definition. More...
struct | PCD_EPTypeDef
struct | PCD_HandleTypeDef
PCD Handle Structure definition. More...

Defines

#define | PCD_SPEED_HIGH 0U /* Not Supported */
#define | PCD_SPEED_FULL 2U
#define | PCD_PHY_EMBEDDED 2U
#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) = (uint16_t)(~(__INTERRUPT__))))
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
#define | __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
#define | __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__))
#define | __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
#define | __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE()
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
#define | USB_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR_MR18)
#define | DEP0CTL_MPS_64 0U
#define | DEP0CTL_MPS_32 1U
#define | DEP0CTL_MPS_16 2U
#define | DEP0CTL_MPS_8 3U
#define | PCD_EP0MPS_64 DEP0CTL_MPS_64
#define | PCD_EP0MPS_32 DEP0CTL_MPS_32
#define | PCD_EP0MPS_16 DEP0CTL_MPS_16
#define | PCD_EP0MPS_08 DEP0CTL_MPS_8
#define | PCD_EP_TYPE_CTRL 0U
#define | PCD_EP_TYPE_ISOC 1U
#define | PCD_EP_TYPE_BULK 2U
#define | PCD_EP_TYPE_INTR 3U
#define | PCD_ENDP0 ((uint8_t)0U)
#define | PCD_ENDP1 ((uint8_t)1U)
#define | PCD_ENDP2 ((uint8_t)2U)
#define | PCD_ENDP3 ((uint8_t)3U)
#define | PCD_ENDP4 ((uint8_t)4U)
#define | PCD_ENDP5 ((uint8_t)5U)
#define | PCD_ENDP6 ((uint8_t)6U)
#define | PCD_ENDP7 ((uint8_t)7U)
#define | PCD_SNG_BUF 0U
#define | PCD_DBL_BUF 1U
#define | PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue))
#define | PCD_GET_ENDPOINT(USBx, bEpNum) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U)))))
#define | PCD_SET_EPTYPE(USBx, bEpNum, wType)
sets the type in the endpoint register(bits EP_TYPE[1:0])
#define | PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD)
gets the type in the endpoint register(bits EP_TYPE[1:0])
#define | PCD_FreeUserBuffer(USBx, bEpNum, bDir)
free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register
#define | PCD_GET_DB_DIR(USBx, bEpNum)
gets direction of the double buffered endpoint
#define | PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState)
sets the status for tx transfer (bits STAT_TX[1:0]).
#define | PCD_SET_EP_RX_STATUS(USBx, bEpNum, wState)
sets the status for rx transfer (bits STAT_TX[1:0])
#define | PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx)
sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
#define | PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT)
gets the status for tx/rx transfer (bits STAT_TX[1:0] /STAT_RX[1:0])
#define | PCD_GET_EP_RX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_STAT)
#define | PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
sets directly the VALID tx/rx-status into the endpoint register
#define | PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
#define | PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum)
checks stall condition in an endpoint.
#define | PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum)
#define | PCD_SET_EP_KIND(USBx, bEpNum)
set & clear EP_KIND bit.
#define | PCD_CLEAR_EP_KIND(USBx, bEpNum)
#define | PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
Sets/clears directly STATUS_OUT bit in the endpoint register.
#define | PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
#define | PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
Sets/clears directly EP_KIND bit in the endpoint register.
#define | PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
#define | PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)
Clears bit CTR_RX / CTR_TX in the endpoint register.
#define | PCD_CLEAR_TX_EP_CTR(USBx, bEpNum)
#define | PCD_RX_DTOG(USBx, bEpNum)
Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_TX_DTOG(USBx, bEpNum)
#define | PCD_CLEAR_RX_DTOG(USBx, bEpNum)
Clears DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_CLEAR_TX_DTOG(USBx, bEpNum)
#define | PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr)
Sets address in an endpoint register.
#define | PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
Gets address in an endpoint register.
#define | PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
sets address of the tx/rx buffer.
#define | PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
#define | PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
Gets address of the tx/rx buffer.
#define | PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
#define | PCD_CALC_BLK32(dwReg, wCount, wNBlocks)
Sets counter of rx buffer with no.
#define | PCD_CALC_BLK2(dwReg, wCount, wNBlocks)
#define | PCD_SET_EP_CNT_RX_REG(dwReg, wCount)
#define | PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount)
#define | PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
sets counter for the tx/rx buffer.
#define | PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
gets counter of the tx buffer.
#define | PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
#define | PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)))
Sets buffer 0/1 address in a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) (PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)))
#define | PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr)
Sets addresses in a double buffer endpoint.
#define | PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
#define | PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount)
#define | PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount)
#define | PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
Gets buffer 0/1 rx/tx counter for double buffering.
#define | PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
#define | IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE

Typedefs

typedef USB_TypeDef | PCD_TypeDef

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00U, HAL_PCD_STATE_READY = 0x01U, HAL_PCD_STATE_ERROR = 0x02U, HAL_PCD_STATE_BUSY = 0x03U,
HAL_PCD_STATE_TIMEOUT = 0x04U
}
PCD State structure definition. More...
enum | PCD_EP_DBUF_DIR { PCD_EP_DBUF_OUT, PCD_EP_DBUF_IN, PCD_EP_DBUF_ERR }
PCD double buffered endpoint direction. More...
enum | PCD_EP_BUF_NUM { PCD_EP_NOBUF, PCD_EP_BUF0, PCD_EP_BUF1 }
PCD endpoint buffer number. More...

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start the USB device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop the USB device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data out stage callbacks.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callbacks.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callbacks.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callbacks.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callbacks.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callbacks.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callbacks.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callbacks.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callbacks.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callbacks.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
uint16_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD state.
HAL_StatusTypeDef | HAL_PCD_ActiveRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_StatusTypeDef | HAL_PCD_DeActiveRemoteWakeup (PCD_HandleTypeDef *hpcd)
void | PCD_WritePMA (USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
Copy a buffer from user memory area to packet memory area (PMA)
void | PCD_ReadPMA (USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
Copy a buffer from user memory area to packet memory area (PMA)

Detailed Description

Header file of PCD HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_pcd.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pcd_ex.h File Reference

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stm32f3xx_hal_pcd_ex.h File Reference

Header file of PCD HAL Extension module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Defines

#define | PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)*2+ ((uint32_t)(USBx) + 0x400U)))))
Gets address in an endpoint register.
#define | PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400U)))))
#define | PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400U)))))
#define | PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400U)))))
#define | PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount)

Functions

HAL_StatusTypeDef | HAL_PCDEx_PMAConfig (PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress)
Configure PMA for EP.
void | HAL_PCDEx_SetConnectionState (PCD_HandleTypeDef *hpcd, uint8_t state)
Software Device Connection.

Detailed Description

Header file of PCD HAL Extension module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_pcd_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pwr.h File Reference

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Defines | Functions
stm32f3xx_hal_pwr.h File Reference

Header file of PWR HAL module. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_pwr_ex.h"

Go to the source code of this file.

Defines

#define | PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
#define | PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
#define | PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3)
#define | PWR_MAINREGULATOR_ON (0x00000000U)
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
#define | PWR_STOPENTRY_WFI ((uint8_t)0x01U)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02U)
#define | PWR_FLAG_WU PWR_CSR_WUF
#define | PWR_FLAG_SB PWR_CSR_SBF
#define | PWR_FLAG_PVDO PWR_CSR_PVDO
#define | PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
#define | __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
Check PWR flag is set or not.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
Clear the PWR's pending flags.
#define | IS_PWR_WAKEUP_PIN(PIN)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))

Functions

void | HAL_PWR_DeInit (void)
Deinitializes the PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_DisableBkUpAccess (void)
Disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinx)
Enables the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disables the WakeUp PINx functionality.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enters STOP mode.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enters Sleep mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enters STANDBY mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enables CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disables CORTEX M4 SEVONPEND bit.

Detailed Description

Header file of PWR HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_pwr.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pwr_ex.h File Reference

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stm32f3xx_hal_pwr_ex.h File Reference

Header file of PWR HAL Extended module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | PWR_PVDTypeDef
PWR PVD configuration structure definition. More...

Defines

#define | PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
#define | PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
#define | PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
#define | PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
#define | PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
#define | PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
#define | PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
#define | PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
#define | PWR_PVD_MODE_NORMAL (0x00000000U)
#define | PWR_PVD_MODE_IT_RISING (0x00010001U)
#define | PWR_PVD_MODE_IT_FALLING (0x00010002U)
#define | PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U)
#define | PWR_PVD_MODE_EVENT_RISING (0x00020001U)
#define | PWR_PVD_MODE_EVENT_FALLING (0x00020002U)
#define | PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U)
#define | PWR_EXTI_LINE_PVD EXTI_IMR_MR16
#define | PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_ENSD1)
#define | PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_ENSD2)
#define | PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_ENSD3)
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
Enable interrupt on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
Disable interrupt on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
Enable event on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
Disable event on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
PVD EXTI line configuration: set falling edge trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
PVD EXTI line configuration: set rising edge trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
Enable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
Check whether the specified PVD EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
Clear the PVD EXTI flag.
#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_SDADC_ANALOG(SDADC)

Functions

void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enables the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disables the Power Voltage Detector(PVD).
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.
void | HAL_PWREx_EnableSDADC (uint32_t Analogx)
Enables the SDADC peripheral functionaliy.
void | HAL_PWREx_DisableSDADC (uint32_t Analogx)
Disables the SDADC peripheral functionaliy.

Detailed Description

Header file of PWR HAL Extended module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_pwr_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_rcc.h File Reference

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stm32f3xx_hal_rcc.h File Reference

Header file of RCC HAL module. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_rcc_ex.h"

Go to the source code of this file.

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition. More...

Defines

#define | RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define | CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
#define | LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
#define | PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
#define | RCC_OFFSET (RCC_BASE - PERIPH_BASE)
#define | RCC_CR_OFFSET 0x00
#define | RCC_CFGR_OFFSET 0x04
#define | RCC_CIR_OFFSET 0x08
#define | RCC_BDCR_OFFSET 0x20
#define | RCC_CSR_OFFSET 0x24
#define | RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
#define | RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
#define | RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
#define | RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
#define | RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
#define | RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
#define | RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
#define | RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
#define | RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
#define | RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
#define | RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
#define | RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
#define | RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
#define | RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
#define | RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
#define | RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
#define | RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
#define | RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON)
#define | RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
#define | RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
#define | RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
#define | RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN)
#define | RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
#define | RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST)
#define | RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
#define | RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
#define | RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
#define | RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
#define | CR_REG_INDEX ((uint8_t)1U)
#define | BDCR_REG_INDEX ((uint8_t)2U)
#define | CSR_REG_INDEX ((uint8_t)3U)
#define | CFGR_REG_INDEX ((uint8_t)4U)
#define | RCC_FLAG_MASK ((uint8_t)0x1FU)
#define | IS_RCC_PLLSOURCE(__SOURCE__)
#define | IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)
#define | IS_RCC_HSE(__HSE__)
#define | IS_RCC_LSE(__LSE__)
#define | IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define | IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
#define | IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define | IS_RCC_PLL(__PLL__)
#define | IS_RCC_PLL_DIV(__DIV__)
#define | IS_RCC_HSE_PREDIV(DIV)
#define | IS_RCC_PLL_MUL(__MUL__)
#define | IS_RCC_CLOCKTYPE(CLK)
#define | IS_RCC_SYSCLKSOURCE(__SOURCE__)
#define | IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__)
#define | IS_RCC_HCLK(__HCLK__)
#define | IS_RCC_PCLK(__PCLK__)
#define | IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
#define | IS_RCC_RTCCLKSOURCE(__SOURCE__)
#define | IS_RCC_USART2CLKSOURCE(__SOURCE__)
#define | IS_RCC_USART3CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C1CLKSOURCE(__SOURCE__)
#define | RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
#define | RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
#define | RCC_OSCILLATORTYPE_NONE (0x00000000U)
#define | RCC_OSCILLATORTYPE_HSE (0x00000001U)
#define | RCC_OSCILLATORTYPE_HSI (0x00000002U)
#define | RCC_OSCILLATORTYPE_LSE (0x00000004U)
#define | RCC_OSCILLATORTYPE_LSI (0x00000008U)
#define | RCC_HSE_OFF (0x00000000U)
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
#define | RCC_LSE_OFF (0x00000000U)
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
#define | RCC_HSI_OFF (0x00000000U)
#define | RCC_HSI_ON RCC_CR_HSION
#define | RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */
#define | RCC_LSI_OFF (0x00000000U)
#define | RCC_LSI_ON RCC_CSR_LSION
#define | RCC_PLL_NONE (0x00000000U)
#define | RCC_PLL_OFF (0x00000001U)
#define | RCC_PLL_ON (0x00000002U)
#define | RCC_CLOCKTYPE_SYSCLK (0x00000001U)
#define | RCC_CLOCKTYPE_HCLK (0x00000002U)
#define | RCC_CLOCKTYPE_PCLK1 (0x00000004U)
#define | RCC_CLOCKTYPE_PCLK2 (0x00000008U)
#define | RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
#define | RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
#define | RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
#define | RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
#define | RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
#define | RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
#define | RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
#define | RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
#define | RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
#define | RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
#define | RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
#define | RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
#define | RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
#define | RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
#define | RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
#define | RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
#define | RCC_RTCCLKSOURCE_NO_CLK RCC_BDCR_RTCSEL_NOCLOCK
#define | RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
#define | RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
#define | RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
#define | RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
#define | RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
#define | RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
#define | RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
#define | RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
#define | RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
#define | RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
#define | RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
#define | RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
#define | RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
#define | RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
#define | RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
#define | RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
#define | RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
#define | RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
#define | RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
#define | RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
#define | RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
#define | RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
#define | RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
#define | RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
#define | RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
#define | RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
#define | RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
#define | RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
#define | RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
#define | RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
#define | RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
#define | RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
#define | RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
#define | RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
#define | RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
#define | RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
#define | RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
#define | RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
#define | RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
#define | RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
#define | RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
#define | RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
#define | RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
#define | RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
#define | RCC_MCO1 (0x00000000U)
#define | RCC_MCO RCC_MCO1
#define | RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF)
#define | RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF)
#define | RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF)
#define | RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF)
#define | RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF)
#define | RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF)
#define | RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY)))
#define | RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY)))
#define | RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY)))
#define | RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY)))
#define | RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_V18PWRRSTF)))
#define | RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF)))
#define | RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF)))
#define | RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF)))
#define | RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF)))
#define | RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF)))
#define | RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF)))
#define | RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF)))
#define | RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY)))
#define | __HAL_RCC_GPIOA_CLK_ENABLE()
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOD_CLK_ENABLE()
#define | __HAL_RCC_GPIOF_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_ENABLE()
#define | __HAL_RCC_SRAM_CLK_ENABLE()
#define | __HAL_RCC_FLITF_CLK_ENABLE()
#define | __HAL_RCC_TSC_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
#define | __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
#define | __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
#define | __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
#define | __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
#define | __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
#define | __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
#define | __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
#define | __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
#define | __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
#define | __HAL_RCC_TIM2_CLK_ENABLE()
#define | __HAL_RCC_TIM6_CLK_ENABLE()
#define | __HAL_RCC_WWDG_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_USART3_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_PWR_CLK_ENABLE()
#define | __HAL_RCC_DAC1_CLK_ENABLE()
#define | __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
#define | __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
#define | __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define | __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define | __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
#define | __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
#define | __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
#define | __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))
#define | __HAL_RCC_SYSCFG_CLK_ENABLE()
#define | __HAL_RCC_TIM15_CLK_ENABLE()
#define | __HAL_RCC_TIM16_CLK_ENABLE()
#define | __HAL_RCC_TIM17_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
#define | __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
#define | __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
#define | __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
#define | __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
#define | __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
#define | __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
#define | __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
#define | __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
#define | __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
#define | __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
#define | __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
#define | __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
#define | __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
#define | __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
#define | __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
#define | __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
#define | __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
#define | __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
#define | __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
#define | __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
#define | __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
#define | __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
#define | __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
#define | __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
#define | __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
#define | __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
#define | __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
#define | __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
#define | __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
#define | __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
#define | __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
#define | __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
#define | __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
#define | __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
#define | __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
#define | __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
#define | __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
#define | __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
#define | __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
#define | __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
#define | __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
#define | __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
#define | __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
#define | __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
#define | __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
#define | __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
#define | __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
#define | __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
#define | __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
#define | __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
#define | __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST))
#define | __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
#define | __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
#define | __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
#define | __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
#define | __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
#define | __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
#define | __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
#define | __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
#define | __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))
#define | __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
#define | __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
#define | __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
#define | __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
#define | __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
#define | __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
#define | __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
#define | __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
#define | __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
#define | __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
#define | __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
#define | __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
Macros to enable or disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
#define | __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
Macro to enable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
Macro to disable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (HSE).
#define | __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).
#define | __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__))
Macro to configure the USART1 clock (USART1CLK).
#define | __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
Macro to get the USART1 clock source.
#define | __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__))
Macro to configure the USART2 clock (USART2CLK).
#define | __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
Macro to get the USART2 clock source.
#define | __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__))
Macro to configure the USART3 clock (USART3CLK).
#define | __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
Macro to get the USART3 clock source.
#define | __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__))
Macro to configure the I2C1 clock (I2C1CLK).
#define | __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
Macro to get the I2C1 clock source.
#define | __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
Macro to enable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
Macro to disable the main PLL.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
Get oscillator clock selected as PLL input clock.
#define | __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
Macro to get the clock source used as system clock.
#define | __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
Macro to configure the MCO clock.
#define | __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Macro to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
Macro to get the RTC clock source.
#define | __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
Macro to enable the the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
Macro to disable the the RTC clock.
#define | __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
Macro to force the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
Macros to release the Backup domain reset.
#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
Enable RCC interrupt.
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
Disable RCC interrupt.
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Clear the RCC's interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Check the RCC's interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
Set RMVF bit to clear the reset flags.
#define | __HAL_RCC_GET_FLAG(__FLAG__)
Check RCC flag is set or not.

Functions

void | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO pin.
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.
void | HAL_RCC_DisableCSS (void)
Disables the Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.

Detailed Description

Header file of RCC HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_rcc.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_rcc_ex.h File Reference

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Data Structures | Defines | Functions
stm32f3xx_hal_rcc_ex.h File Reference

Header file of RCC HAL Extension module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...

Defines

#define | IS_RCC_MCO1SOURCE(SOURCE)
#define | IS_RCC_PERIPHCLOCK(SELECTION)
#define | IS_RCC_USART1CLKSOURCE(SOURCE)
#define | IS_RCC_I2C2CLKSOURCE(SOURCE)
#define | IS_RCC_ADC1PCLK2_DIV(ADCCLK)
#define | IS_RCC_CECCLKSOURCE(SOURCE)
#define | IS_RCC_SDADCSYSCLK_DIV(DIV)
#define | IS_RCC_USBCLKSOURCE(SOURCE)
#define | IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
#define | IS_RCC_LSE_DRIVE(__DRIVE__)
#define | RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
#define | RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
#define | RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
#define | RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
#define | RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
#define | RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
#define | RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
#define | RCC_PERIPHCLK_USART1 (0x00000001U)
#define | RCC_PERIPHCLK_USART2 (0x00000002U)
#define | RCC_PERIPHCLK_USART3 (0x00000004U)
#define | RCC_PERIPHCLK_I2C1 (0x00000020U)
#define | RCC_PERIPHCLK_I2C2 (0x00000040U)
#define | RCC_PERIPHCLK_ADC1 (0x00000080U)
#define | RCC_PERIPHCLK_CEC (0x00000400U)
#define | RCC_PERIPHCLK_SDADC (0x00000800U)
#define | RCC_PERIPHCLK_RTC (0x00010000U)
#define | RCC_PERIPHCLK_USB (0x00020000U)
#define | RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
#define | RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
#define | RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
#define | RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
#define | RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
#define | RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
#define | RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
#define | RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
#define | RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
#define | RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
#define | RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
#define | RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
#define | RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDPRE_DIV1
#define | RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDPRE_DIV2
#define | RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDPRE_DIV4
#define | RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDPRE_DIV6
#define | RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDPRE_DIV8
#define | RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDPRE_DIV10
#define | RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDPRE_DIV12
#define | RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDPRE_DIV14
#define | RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDPRE_DIV16
#define | RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDPRE_DIV20
#define | RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDPRE_DIV24
#define | RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDPRE_DIV28
#define | RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDPRE_DIV32
#define | RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDPRE_DIV36
#define | RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDPRE_DIV40
#define | RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDPRE_DIV44
#define | RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDPRE_DIV48
#define | RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1
#define | RCC_USBCLKSOURCE_PLL_DIV1_5 RCC_CFGR_USBPRE_DIV1_5
#define | RCC_MCODIV_1 (0x00000000U)
#define | RCC_LSEDRIVE_LOW (0x00000000U)
#define | RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
#define | RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
#define | RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
#define | __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLMUL__) MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__)))
Macro to configure the PLL clock source and multiplication factor.
#define | __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
#define | __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)
Macro to get prediv1 factor for PLL.
#define | __HAL_RCC_DMA2_CLK_ENABLE()
#define | __HAL_RCC_GPIOE_CLK_ENABLE()
#define | __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
#define | __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
#define | __HAL_RCC_TIM3_CLK_ENABLE()
#define | __HAL_RCC_TIM4_CLK_ENABLE()
#define | __HAL_RCC_TIM5_CLK_ENABLE()
#define | __HAL_RCC_TIM12_CLK_ENABLE()
#define | __HAL_RCC_TIM13_CLK_ENABLE()
#define | __HAL_RCC_TIM14_CLK_ENABLE()
#define | __HAL_RCC_TIM18_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_SPI3_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_DAC2_CLK_ENABLE()
#define | __HAL_RCC_CEC_CLK_ENABLE()
#define | __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
#define | __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
#define | __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
#define | __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
#define | __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
#define | __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
#define | __HAL_RCC_TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
#define | __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
#define | __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
#define | __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
#define | __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
#define | __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
#define | __HAL_RCC_TIM7_CLK_ENABLE()
#define | __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
#define | __HAL_RCC_USB_CLK_ENABLE()
#define | __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
#define | __HAL_RCC_CAN1_CLK_ENABLE()
#define | __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
#define | __HAL_RCC_ADC1_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_TIM19_CLK_ENABLE()
#define | __HAL_RCC_SDADC1_CLK_ENABLE()
#define | __HAL_RCC_SDADC2_CLK_ENABLE()
#define | __HAL_RCC_SDADC3_CLK_ENABLE()
#define | __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
#define | __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
#define | __HAL_RCC_TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
#define | __HAL_RCC_SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
#define | __HAL_RCC_SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
#define | __HAL_RCC_SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
#define | __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
#define | __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
#define | __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
#define | __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
#define | __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
#define | __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
#define | __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
#define | __HAL_RCC_TIM18_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
#define | __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
#define | __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
#define | __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)
#define | __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
#define | __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
#define | __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
#define | __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
#define | __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
#define | __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
#define | __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
#define | __HAL_RCC_TIM18_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
#define | __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
#define | __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
#define | __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)
#define | __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
#define | __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
#define | __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
#define | __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
#define | __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
#define | __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) != RESET)
#define | __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) == RESET)
#define | __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
#define | __HAL_RCC_TIM19_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) != RESET)
#define | __HAL_RCC_SDADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) != RESET)
#define | __HAL_RCC_SDADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) != RESET)
#define | __HAL_RCC_SDADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) != RESET)
#define | __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
#define | __HAL_RCC_TIM19_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) == RESET)
#define | __HAL_RCC_SDADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) == RESET)
#define | __HAL_RCC_SDADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) == RESET)
#define | __HAL_RCC_SDADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) == RESET)
#define | __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
#define | __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
#define | __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
#define | __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
#define | __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
#define | __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
#define | __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
#define | __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
#define | __HAL_RCC_TIM18_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM18RST))
#define | __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
#define | __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
#define | __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
#define | __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
#define | __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
#define | __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
#define | __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
#define | __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
#define | __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
#define | __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
#define | __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
#define | __HAL_RCC_TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
#define | __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
#define | __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
#define | __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
#define | __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
#define | __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
#define | __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
#define | __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
#define | __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
#define | __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
#define | __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
#define | __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
#define | __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
#define | __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
#define | __HAL_RCC_TIM19_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM19RST))
#define | __HAL_RCC_SDADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC1RST))
#define | __HAL_RCC_SDADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC2RST))
#define | __HAL_RCC_SDADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC3RST))
#define | __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
#define | __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
#define | __HAL_RCC_TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
#define | __HAL_RCC_SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
#define | __HAL_RCC_SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
#define | __HAL_RCC_SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
#define | __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
Macro to configure the I2C2 clock (I2C2CLK).
#define | __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
Macro to get the I2C2 clock source.
#define | __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
Macro to configure the ADC1 clock (ADC1CLK).
#define | __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
Macro to get the ADC1 clock (ADC1CLK).
#define | __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, (uint32_t)(__SDADCPrescaler__))
Macro to configure the SDADCx clock (SDADCxCLK).
#define | __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDPRE)))
Macro to get the SDADCx clock prescaler.
#define | __HAL_RCC_CEC_CONFIG(__CECCLKSource__) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
Macro to configure the CEC clock.
#define | __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
Macro to get the HDMI CEC clock source.
#define | __HAL_RCC_USB_CONFIG(__USBCLKSource__) MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
Macro to configure the USB clock (USBCLK).
#define | __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
Macro to get the USB clock source.
#define | __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__)
Macro to configure the External Low Speed oscillator (LSE) drive capability.

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Returns the peripheral clock frequency.

Detailed Description

Header file of RCC HAL Extension module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_rcc_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_rtc.h File Reference

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stm32f3xx_hal_rtc.h File Reference

Header file of RTC HAL module. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_rtc_ex.h"

Go to the source code of this file.

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | RTC_HandleTypeDef
RTC Handle Structure definition. More...

Defines

#define | RTC_HOURFORMAT_24 0x00000000U
#define | RTC_HOURFORMAT_12 RTC_CR_FMT
#define | RTC_OUTPUT_POLARITY_HIGH 0x00000000U
#define | RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
#define | RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U
#define | RTC_OUTPUT_TYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE
#define | RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define | RTC_HOURFORMAT12_PM ((uint8_t)0x40)
#define | RTC_DAYLIGHTSAVING_NONE 0x00000000U
#define | RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
#define | RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
#define | RTC_STOREOPERATION_RESET 0x00000000U
#define | RTC_STOREOPERATION_SET RTC_CR_BCK
#define | RTC_FORMAT_BIN 0x000000000U
#define | RTC_FORMAT_BCD 0x000000001U
#define | RTC_MONTH_JANUARY ((uint8_t)0x01)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define | RTC_MONTH_MARCH ((uint8_t)0x03)
#define | RTC_MONTH_APRIL ((uint8_t)0x04)
#define | RTC_MONTH_MAY ((uint8_t)0x05)
#define | RTC_MONTH_JUNE ((uint8_t)0x06)
#define | RTC_MONTH_JULY ((uint8_t)0x07)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12)
#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
#define | RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
#define | RTC_ALARMMASK_NONE 0x00000000U
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL
#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE
#define | RTC_ALARMSUBSECONDMASK_ALL 0x00000000U
#define | RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0
#define | RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1
#define | RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)
#define | RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2
#define | RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3
#define | RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS
#define | RTC_IT_TS RTC_CR_TSIE
#define | RTC_IT_WUT RTC_CR_WUTIE
#define | RTC_IT_ALRB RTC_CR_ALRBIE
#define | RTC_IT_ALRA RTC_CR_ALRAIE
#define | RTC_IT_TAMP RTC_TAFCR_TAMPIE /* Used only to Enable the Tamper Interrupt */
#define | RTC_IT_TAMP1 0x00020000U /*only for RTC_ISR flag check*/
#define | RTC_IT_TAMP2 0x00040000U /*only for RTC_ISR flag check*/
#define | RTC_IT_TAMP3 0x00080000U /*only for RTC_ISR flag check*/
#define | RTC_FLAG_RECALPF RTC_ISR_RECALPF
#define | RTC_FLAG_TAMP3F RTC_ISR_TAMP3F
#define | RTC_FLAG_TAMP2F RTC_ISR_TAMP2F
#define | RTC_FLAG_TAMP1F RTC_ISR_TAMP1F
#define | RTC_FLAG_TSOVF RTC_ISR_TSOVF
#define | RTC_FLAG_TSF RTC_ISR_TSF
#define | RTC_FLAG_WUTF RTC_ISR_WUTF
#define | RTC_FLAG_ALRBF RTC_ISR_ALRBF
#define | RTC_FLAG_ALRAF RTC_ISR_ALRAF
#define | RTC_FLAG_INITF RTC_ISR_INITF
#define | RTC_FLAG_RSF RTC_ISR_RSF
#define | RTC_FLAG_INITS RTC_ISR_INITS
#define | RTC_FLAG_SHPF RTC_ISR_SHPF
#define | RTC_FLAG_WUTWF RTC_ISR_WUTWF
#define | RTC_FLAG_ALRBWF RTC_ISR_ALRBWF
#define | RTC_FLAG_ALRAWF RTC_ISR_ALRAWF
#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Alarm interrupt has been enabled or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Alarm's flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Alarm's pending flags.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
Clear the RTC Alarm associated Exti line flag.
#define | __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
Generate a Software interrupt on RTC Alarm associated Exti line.
#define | RTC_TR_RESERVED_MASK 0x007F7F7FU
#define | RTC_DR_RESERVED_MASK 0x00FFFF3FU
#define | RTC_INIT_MASK 0xFFFFFFFFU
#define | RTC_RSF_MASK 0xFFFFFF5FU
#define | RTC_FLAGS_MASK
#define | RTC_TIMEOUT_VALUE 1000
#define | RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17
#define | RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR_MR19
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR20
#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | IS_RTC_OUTPUT_POL(POL)
#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
#define | IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU)
#define | IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
#define | IS_RTC_HOURFORMAT12(PM)
#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
#define | IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
#define | IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00U, HAL_RTC_STATE_READY = 0x01U, HAL_RTC_STATE_BUSY = 0x02U, HAL_RTC_STATE_TIMEOUT = 0x03U,
HAL_RTC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC according to the specified parameters in the RTC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
@addtogroup RTC_Exported_Functions_Group4 Peripheral Control functions
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
@addtogroup RTC_Exported_Functions_Group5 Peripheral State functions
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
@addtogroup RTC_Private_Functions RTC Private Functions
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Detailed Description

Header file of RTC HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_rtc.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_rtc_ex.h File Reference

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Data Structures | Defines | Functions
stm32f3xx_hal_rtc_ex.h File Reference

Header file of RTC HAL Extended module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RTC_TamperTypeDef
RTC Tamper structure definition. More...

Defines

#define | RTC_OUTPUT_DISABLE 0x00000000U
#define | RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
#define | RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
#define | RTC_OUTPUT_WAKEUP RTC_CR_OSEL
#define | RTC_BKP_DR0 0x00000000U
#define | RTC_BKP_DR1 0x00000001U
#define | RTC_BKP_DR2 0x00000002U
#define | RTC_BKP_DR3 0x00000003U
#define | RTC_BKP_DR4 0x00000004U
#define | RTC_BKP_DR5 0x00000005U
#define | RTC_BKP_DR6 0x00000006U
#define | RTC_BKP_DR7 0x00000007U
#define | RTC_BKP_DR8 0x00000008U
#define | RTC_BKP_DR9 0x00000009U
#define | RTC_BKP_DR10 0x0000000AU
#define | RTC_BKP_DR11 0x0000000BU
#define | RTC_BKP_DR12 0x0000000CU
#define | RTC_BKP_DR13 0x0000000DU
#define | RTC_BKP_DR14 0x0000000EU
#define | RTC_BKP_DR15 0x0000000FU
#define | RTC_BKP_DR16 0x00000010U
#define | RTC_BKP_DR17 0x00000011U
#define | RTC_BKP_DR18 0x00000012U
#define | RTC_BKP_DR19 0x00000013U
#define | RTC_BKP_DR20 0x00000014U
#define | RTC_BKP_DR21 0x00000015U
#define | RTC_BKP_DR22 0x00000016U
#define | RTC_BKP_DR23 0x00000017U
#define | RTC_BKP_DR24 0x00000018U
#define | RTC_BKP_DR25 0x00000019U
#define | RTC_BKP_DR26 0x0000001AU
#define | RTC_BKP_DR27 0x0000001BU
#define | RTC_BKP_DR28 0x0000001CU
#define | RTC_BKP_DR29 0x0000001DU
#define | RTC_BKP_DR30 0x0000001EU
#define | RTC_BKP_DR31 0x0000001FU
#define | RTC_TIMESTAMPEDGE_RISING 0x00000000U
#define | RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
#define | RTC_TIMESTAMPPIN_DEFAULT 0x00000000U
#define | RTC_TAMPER_1 RTC_TAFCR_TAMP1E
#define | RTC_TAMPER_2 RTC_TAFCR_TAMP2E
#define | RTC_TAMPER_3 RTC_TAFCR_TAMP3E
#define | RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U
#define | RTC_TAMPERTRIGGER_FALLINGEDGE RTC_TAFCR_TAMP1TRG
#define | RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define | RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
#define | RTC_TAMPERFILTER_DISABLE 0x00000000U
#define | RTC_TAMPERFILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0
#define | RTC_TAMPERFILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1
#define | RTC_TAMPERFILTER_8SAMPLE RTC_TAFCR_TAMPFLT
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAFCR_TAMPFREQ_0
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAFCR_TAMPFREQ_1
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAFCR_TAMPFREQ_2
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_2)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2)
#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK (RTC_TAFCR_TAMPPRCH_0 | RTC_TAFCR_TAMPPRCH_1)
#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS)
#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U
#define | RTC_TAMPER_PULLUP_ENABLE 0x00000000U
#define | RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS (RTC_CR_WUCKSEL_2)
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
#define | RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U
#define | RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8
#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U
#define | RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP
#define | RTC_CALIBOUTPUT_512HZ 0x00000000U
#define | RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
#define | RTC_SHIFTADD1S_RESET 0x00000000U
#define | RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET) ? SET : RESET)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC WakeUpTimer's flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Wake Up timer's pending flags.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated Exti line flag.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Time Stamp interrupt has been enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC TimeStamp's flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Time Stamp's pending flags.
#define | __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
Enable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
Disable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E))
Enable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))
Disable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP3E))
Enable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP3E))
Disable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR |= (__INTERRUPT__))
Enable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__))
Disable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
Check whether the specified RTC Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Tamper interrupt has been enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Tamper's pending flags.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Clear the RTC Tamper and Timestamp associated Exti line flag.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC shift operation's flag status.
#define | IS_RTC_OUTPUT(OUTPUT)
#define | IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
#define | IS_TIMESTAMP_EDGE(EDGE)
#define | IS_RTC_TAMPER(TAMPER) ((((TAMPER) & 0xFFFFFFD6U) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
#define | IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
#define | IS_RTC_TAMPER_TRIGGER(TRIGGER)
#define | IS_RTC_TAMPER_FILTER(FILTER)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(FREQ)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_TAMPER_PULLUP_STATE(STATE)
#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFFU)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU)
#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU)
#define | IS_RTC_CALIB_OUTPUT(OUTPUT)

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 3 Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
uint32_t | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.
__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmB Polling request.

Detailed Description

Header file of RTC HAL Extended module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_rtc_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_sdadc.h File Reference

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stm32f3xx_hal_sdadc.h File Reference

This file contains all the functions prototypes for the SDADC firmware library. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SDADC_InitTypeDef
SDADC Init Structure definition. More...
struct | SDADC_HandleTypeDef
SDADC handle Structure definition. More...
struct | SDADC_ConfParamTypeDef
SDADC Configuration Register Parameter Structure. More...

Defines

#define | SDADC_LOWPOWER_NONE (0x00000000U)
#define | SDADC_LOWPOWER_POWERDOWN SDADC_CR1_PDI
#define | SDADC_LOWPOWER_STANDBY SDADC_CR1_SBI
#define | SDADC_FAST_CONV_DISABLE (0x00000000U)
#define | SDADC_FAST_CONV_ENABLE SDADC_CR2_FAST
#define | SDADC_SLOW_CLOCK_DISABLE (0x00000000U)
#define | SDADC_SLOW_CLOCK_ENABLE SDADC_CR1_SLOWCK
#define | SDADC_VREF_EXT (0x00000000U)
#define | SDADC_VREF_VREFINT1 SDADC_CR1_REFV_0
#define | SDADC_VREF_VREFINT2 SDADC_CR1_REFV_1
#define | SDADC_VREF_VDDA SDADC_CR1_REFV
#define | SDADC_CONF_INDEX_0 (0x00000000U)
#define | SDADC_CONF_INDEX_1 (0x00000001U)
#define | SDADC_CONF_INDEX_2 (0x00000002U)
#define | SDADC_INPUT_MODE_DIFF (0x00000000U)
#define | SDADC_INPUT_MODE_SE_OFFSET SDADC_CONF0R_SE0_0
#define | SDADC_INPUT_MODE_SE_ZERO_REFERENCE SDADC_CONF0R_SE0
#define | SDADC_GAIN_1 (0x00000000U)
#define | SDADC_GAIN_2 SDADC_CONF0R_GAIN0_0
#define | SDADC_GAIN_4 SDADC_CONF0R_GAIN0_1
#define | SDADC_GAIN_8 (0x00300000U)
#define | SDADC_GAIN_16 SDADC_CONF0R_GAIN0_2
#define | SDADC_GAIN_32 (0x00500000U)
#define | SDADC_GAIN_1_2 SDADC_CONF0R_GAIN0
#define | SDADC_COMMON_MODE_VSSA (0x00000000U)
#define | SDADC_COMMON_MODE_VDDA_2 SDADC_CONF0R_COMMON0_0
#define | SDADC_COMMON_MODE_VDDA SDADC_CONF0R_COMMON0_1
#define | SDADC_CHANNEL_0 (0x00000001U)
#define | SDADC_CHANNEL_1 (0x00010002U)
#define | SDADC_CHANNEL_2 (0x00020004U)
#define | SDADC_CHANNEL_3 (0x00030008U)
#define | SDADC_CHANNEL_4 (0x00040010U)
#define | SDADC_CHANNEL_5 (0x00050020U)
#define | SDADC_CHANNEL_6 (0x00060040U)
#define | SDADC_CHANNEL_7 (0x00070080U)
#define | SDADC_CHANNEL_8 (0x00080100U)
#define | SDADC_CALIBRATION_SEQ_1 (0x00000000U)
#define | SDADC_CALIBRATION_SEQ_2 SDADC_CR2_CALIBCNT_0
#define | SDADC_CALIBRATION_SEQ_3 SDADC_CR2_CALIBCNT_1
#define | SDADC_CONTINUOUS_CONV_OFF (0x00000000U)
#define | SDADC_CONTINUOUS_CONV_ON (0x00000001U)
#define | SDADC_SOFTWARE_TRIGGER (0x00000000U)
#define | SDADC_SYNCHRONOUS_TRIGGER (0x00000001U)
#define | SDADC_EXTERNAL_TRIGGER (0x00000002U)
#define | SDADC_EXT_TRIG_TIM13_CC1 (0x00000000U)
#define | SDADC_EXT_TRIG_TIM14_CC1 (0x00000100U)
#define | SDADC_EXT_TRIG_TIM16_CC1 (0x00000000U)
#define | SDADC_EXT_TRIG_TIM17_CC1 (0x00000000U)
#define | SDADC_EXT_TRIG_TIM12_CC1 (0x00000100U)
#define | SDADC_EXT_TRIG_TIM12_CC2 (0x00000100U)
#define | SDADC_EXT_TRIG_TIM15_CC2 (0x00000200U)
#define | SDADC_EXT_TRIG_TIM2_CC3 (0x00000200U)
#define | SDADC_EXT_TRIG_TIM2_CC4 (0x00000200U)
#define | SDADC_EXT_TRIG_TIM3_CC1 (0x00000300U)
#define | SDADC_EXT_TRIG_TIM3_CC2 (0x00000300U)
#define | SDADC_EXT_TRIG_TIM3_CC3 (0x00000300U)
#define | SDADC_EXT_TRIG_TIM4_CC1 (0x00000400U)
#define | SDADC_EXT_TRIG_TIM4_CC2 (0x00000400U)
#define | SDADC_EXT_TRIG_TIM4_CC3 (0x00000400U)
#define | SDADC_EXT_TRIG_TIM19_CC2 (0x00000500U)
#define | SDADC_EXT_TRIG_TIM19_CC3 (0x00000500U)
#define | SDADC_EXT_TRIG_TIM19_CC4 (0x00000500U)
#define | SDADC_EXT_TRIG_EXTI11 (0x00000700U)
#define | SDADC_EXT_TRIG_EXTI15 (0x00000600U)
#define | SDADC_EXT_TRIG_RISING_EDGE SDADC_CR2_JEXTEN_0
#define | SDADC_EXT_TRIG_FALLING_EDGE SDADC_CR2_JEXTEN_1
#define | SDADC_EXT_TRIG_BOTH_EDGES SDADC_CR2_JEXTEN
#define | SDADC_INJECTED_DELAY_NONE (0x00000000U)
#define | SDADC_INJECTED_DELAY SDADC_CR2_JDS
#define | SDADC_MULTIMODE_SDADC1_SDADC2 (0x00000000U)
#define | SDADC_MULTIMODE_SDADC1_SDADC3 (0x00000001U)
#define | SDADC_ERROR_NONE (0x00000000U)
#define | SDADC_ERROR_REGULAR_OVERRUN (0x00000001U)
#define | SDADC_ERROR_INJECTED_OVERRUN (0x00000002U)
#define | SDADC_ERROR_DMA (0x00000003U)
#define | SDADC_IT_EOCAL SDADC_CR1_EOCALIE
#define | SDADC_IT_JEOC SDADC_CR1_JEOCIE
#define | SDADC_IT_JOVR SDADC_CR1_JOVRIE
#define | SDADC_IT_REOC SDADC_CR1_REOCIE
#define | SDADC_IT_ROVR SDADC_CR1_ROVRIE
#define | SDADC_FLAG_EOCAL SDADC_ISR_EOCALF
#define | SDADC_FLAG_JEOC SDADC_ISR_JEOCF
#define | SDADC_FLAG_JOVR SDADC_ISR_JOVRF
#define | SDADC_FLAG_REOC SDADC_ISR_REOCF
#define | SDADC_FLAG_ROVR SDADC_ISR_ROVRF
#define | __HAL_SDADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
Enable the ADC end of conversion interrupt.
#define | __HAL_SDADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
Disable the ADC end of conversion interrupt.
#define | __HAL_SDADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_SDADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
Get the selected ADC's flag status.
#define | __HAL_SDADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (CLEAR_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)))
Clear the ADC's pending flags.
#define | __HAL_SDADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDADC_STATE_RESET)
Reset SDADC handle state.
#define | IS_SDADC_LOWPOWER_MODE(LOWPOWER)
#define | IS_SDADC_FAST_CONV_MODE(FAST)
#define | IS_SDADC_SLOW_CLOCK_MODE(MODE)
#define | IS_SDADC_VREF(VREF)
#define | IS_SDADC_CONF_INDEX(CONF)
#define | IS_SDADC_INPUT_MODE(MODE)
#define | IS_SDADC_GAIN(GAIN)
#define | IS_SDADC_COMMON_MODE(MODE)
#define | IS_SDADC_OFFSET_VALUE(VALUE) ((VALUE) <= 0x00000FFFU)
#define | IS_SDADC_REGULAR_CHANNEL(CHANNEL)
#define | IS_SDADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F01FFU))
#define | IS_SDADC_CALIB_SEQUENCE(SEQUENCE)
#define | IS_SDADC_CONTINUOUS_MODE(MODE)
#define | IS_SDADC_REGULAR_TRIGGER(TRIGGER)
#define | IS_SDADC_INJECTED_TRIGGER(TRIGGER)
#define | IS_SDADC_EXT_INJEC_TRIG(INJTRIG)
#define | IS_SDADC_EXT_TRIG_EDGE(TRIGGER)
#define | IS_SDADC_INJECTED_DELAY(DELAY)
#define | IS_SDADC_MULTIMODE_TYPE(TYPE)

Enumerations

enum HAL_SDADC_StateTypeDef {
HAL_SDADC_STATE_RESET = 0x00U, HAL_SDADC_STATE_READY = 0x01U, HAL_SDADC_STATE_CALIB = 0x02U, HAL_SDADC_STATE_REG = 0x03U,
HAL_SDADC_STATE_INJ = 0x04U, HAL_SDADC_STATE_REG_INJ = 0x05U, HAL_SDADC_STATE_ERROR = 0xFFU
}
HAL SDADC States definition. More...

Functions

HAL_StatusTypeDef | HAL_SDADC_Init (SDADC_HandleTypeDef *hsdadc)
Initializes the SDADC according to the specified parameters in the SDADC_InitTypeDef structure.
HAL_StatusTypeDef | HAL_SDADC_DeInit (SDADC_HandleTypeDef *hsdadc)
De-initializes the SDADC.
__weak void | HAL_SDADC_MspInit (SDADC_HandleTypeDef *hsdadc)
Initializes the SDADC MSP.
__weak void | HAL_SDADC_MspDeInit (SDADC_HandleTypeDef *hsdadc)
De-initializes the SDADC MSP.
HAL_StatusTypeDef | HAL_SDADC_PrepareChannelConfig (SDADC_HandleTypeDef *hsdadc, uint32_t ConfIndex, SDADC_ConfParamTypeDef *ConfParamStruct)
This function allows the user to set parameters for a configuration.
HAL_StatusTypeDef | HAL_SDADC_AssociateChannelConfig (SDADC_HandleTypeDef *hsdadc, uint32_t Channel, uint32_t ConfIndex)
This function allows the user to associate a channel with one of the available configurations.
HAL_StatusTypeDef | HAL_SDADC_ConfigChannel (SDADC_HandleTypeDef *hsdadc, uint32_t Channel, uint32_t ContinuousMode)
This function allows to select channel for regular conversion and to enable/disable continuous mode for regular conversion.
HAL_StatusTypeDef | HAL_SDADC_InjectedConfigChannel (SDADC_HandleTypeDef *hsdadc, uint32_t Channel, uint32_t ContinuousMode)
This function allows to select channels for injected conversion and to enable/disable continuous mode for injected conversion.
HAL_StatusTypeDef | HAL_SDADC_SelectInjectedExtTrigger (SDADC_HandleTypeDef *hsdadc, uint32_t InjectedExtTrigger, uint32_t ExtTriggerEdge)
This function allows to select and configure injected external trigger.
HAL_StatusTypeDef | HAL_SDADC_SelectInjectedDelay (SDADC_HandleTypeDef *hsdadc, uint32_t InjectedDelay)
This function allows to enable/disable delay addition for injected conversions.
HAL_StatusTypeDef | HAL_SDADC_SelectRegularTrigger (SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
This function allows to select trigger for regular conversions.
HAL_StatusTypeDef | HAL_SDADC_SelectInjectedTrigger (SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
This function allows to select trigger for injected conversions.
HAL_StatusTypeDef | HAL_SDADC_MultiModeConfigChannel (SDADC_HandleTypeDef *hsdadc, uint32_t MultimodeType)
This function allows to configure multimode for regular conversions.
HAL_StatusTypeDef | HAL_SDADC_InjectedMultiModeConfigChannel (SDADC_HandleTypeDef *hsdadc, uint32_t MultimodeType)
This function allows to configure multimode for injected conversions.
HAL_StatusTypeDef | HAL_SDADC_CalibrationStart (SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence)
This function allows to start calibration in polling mode.
HAL_StatusTypeDef | HAL_SDADC_CalibrationStart_IT (SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence)
This function allows to start calibration in interrupt mode.
HAL_StatusTypeDef | HAL_SDADC_Start (SDADC_HandleTypeDef *hsdadc)
This function allows to start regular conversion in polling mode.
HAL_StatusTypeDef | HAL_SDADC_Start_IT (SDADC_HandleTypeDef *hsdadc)
This function allows to start regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_SDADC_Start_DMA (SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode.
HAL_StatusTypeDef | HAL_SDADC_Stop (SDADC_HandleTypeDef *hsdadc)
This function allows to stop regular conversion in polling mode.
HAL_StatusTypeDef | HAL_SDADC_Stop_IT (SDADC_HandleTypeDef *hsdadc)
This function allows to stop regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_SDADC_Stop_DMA (SDADC_HandleTypeDef *hsdadc)
This function allows to stop regular conversion in DMA mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedStart (SDADC_HandleTypeDef *hsdadc)
This function allows to start injected conversion in polling mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedStart_IT (SDADC_HandleTypeDef *hsdadc)
This function allows to start injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedStart_DMA (SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedStop (SDADC_HandleTypeDef *hsdadc)
This function allows to stop injected conversion in polling mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedStop_IT (SDADC_HandleTypeDef *hsdadc)
This function allows to stop injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedStop_DMA (SDADC_HandleTypeDef *hsdadc)
This function allows to stop injected conversion in DMA mode.
HAL_StatusTypeDef | HAL_SDADC_MultiModeStart_DMA (SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length)
This function allows to start multimode regular conversions in DMA mode.
HAL_StatusTypeDef | HAL_SDADC_MultiModeStop_DMA (SDADC_HandleTypeDef *hsdadc)
This function allows to stop multimode regular conversions in DMA mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedMultiModeStart_DMA (SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length)
This function allows to start multimode injected conversions in DMA mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedMultiModeStop_DMA (SDADC_HandleTypeDef *hsdadc)
This function allows to stop multimode injected conversions in DMA mode.
uint32_t | HAL_SDADC_GetValue (SDADC_HandleTypeDef *hsdadc)
This function allows to get regular conversion value.
uint32_t | HAL_SDADC_InjectedGetValue (SDADC_HandleTypeDef *hsdadc, uint32_t *Channel)
This function allows to get injected conversion value.
uint32_t | HAL_SDADC_MultiModeGetValue (SDADC_HandleTypeDef *hsdadc)
This function allows to get multimode regular conversion value.
uint32_t | HAL_SDADC_InjectedMultiModeGetValue (SDADC_HandleTypeDef *hsdadc)
This function allows to get multimode injected conversion value.
void | HAL_SDADC_IRQHandler (SDADC_HandleTypeDef *hsdadc)
This function handles the SDADC interrupts.
HAL_StatusTypeDef | HAL_SDADC_PollForCalibEvent (SDADC_HandleTypeDef *hsdadc, uint32_t Timeout)
This function allows to poll for the end of calibration.
HAL_StatusTypeDef | HAL_SDADC_PollForConversion (SDADC_HandleTypeDef *hsdadc, uint32_t Timeout)
This function allows to poll for the end of regular conversion.
HAL_StatusTypeDef | HAL_SDADC_PollForInjectedConversion (SDADC_HandleTypeDef *hsdadc, uint32_t Timeout)
This function allows to poll for the end of injected conversion.
__weak void | HAL_SDADC_CalibrationCpltCallback (SDADC_HandleTypeDef *hsdadc)
Calibration complete callback.
__weak void | HAL_SDADC_ConvHalfCpltCallback (SDADC_HandleTypeDef *hsdadc)
Half regular conversion complete callback.
__weak void | HAL_SDADC_ConvCpltCallback (SDADC_HandleTypeDef *hsdadc)
Regular conversion complete callback.
__weak void | HAL_SDADC_InjectedConvHalfCpltCallback (SDADC_HandleTypeDef *hsdadc)
Half injected conversion complete callback.
__weak void | HAL_SDADC_InjectedConvCpltCallback (SDADC_HandleTypeDef *hsdadc)
Injected conversion complete callback.
__weak void | HAL_SDADC_ErrorCallback (SDADC_HandleTypeDef *hsdadc)
Error callback.
HAL_SDADC_StateTypeDef | HAL_SDADC_GetState (SDADC_HandleTypeDef *hsdadc)
This function allows to get the current SDADC state.
uint32_t | HAL_SDADC_GetError (SDADC_HandleTypeDef *hsdadc)
This function allows to get the current SDADC error code.

Detailed Description

This file contains all the functions prototypes for the SDADC firmware library.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_sdadc.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_smartcard.h File Reference

  • File List
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  • Firmware
  • Drivers
  • STM32F3xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32f3xx_hal_smartcard.h File Reference

Header file of SMARTCARD HAL module. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_smartcard_ex.h"

Go to the source code of this file.

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_AdvFeatureInitTypeDef
SMARTCARD advanced features initalization structure definition. More...
struct | SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Defines

#define | HAL_SMARTCARD_ERROR_NONE (0x00000000U)
#define | HAL_SMARTCARD_ERROR_PE (0x00000001U)
#define | HAL_SMARTCARD_ERROR_NE (0x00000002U)
#define | HAL_SMARTCARD_ERROR_FE (0x00000004U)
#define | HAL_SMARTCARD_ERROR_ORE (0x00000008U)
#define | HAL_SMARTCARD_ERROR_DMA (0x00000010U)
#define | HAL_SMARTCARD_ERROR_RTO (0x00000020U)
#define | SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
#define | SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define | SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
#define | SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
#define | SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | SMARTCARD_POLARITY_LOW (0x00000000U)
#define | SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
#define | SMARTCARD_PHASE_1EDGE (0x00000000U)
#define | SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
#define | SMARTCARD_LASTBIT_DISABLE (0x00000000U)
#define | SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
#define | SMARTCARD_ONE_BIT_SAMPLE_DISABLE (0x00000000U)
#define | SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
#define | SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define | SMARTCARD_NACK_DISABLE (0x00000000U)
#define | SMARTCARD_TIMEOUT_DISABLE (0x00000000U)
#define | SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)
#define | SMARTCARD_ADVFEATURE_NO_INIT (0x00000000U)
#define | SMARTCARD_ADVFEATURE_TXINVERT_INIT (0x00000001U)
#define | SMARTCARD_ADVFEATURE_RXINVERT_INIT (0x00000002U)
#define | SMARTCARD_ADVFEATURE_DATAINVERT_INIT (0x00000004U)
#define | SMARTCARD_ADVFEATURE_SWAP_INIT (0x00000008U)
#define | SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U)
#define | SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_INIT (0x00000080U)
#define | SMARTCARD_ADVFEATURE_TXINV_DISABLE (0x00000000U)
#define | SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
#define | SMARTCARD_ADVFEATURE_RXINV_DISABLE (0x00000000U)
#define | SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
#define | SMARTCARD_ADVFEATURE_DATAINV_DISABLE (0x00000000U)
#define | SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
#define | SMARTCARD_ADVFEATURE_SWAP_DISABLE (0x00000000U)
#define | SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
#define | SMARTCARD_ADVFEATURE_OVERRUN_ENABLE (0x00000000U)
#define | SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
#define | SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U)
#define | SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
#define | SMARTCARD_FLAG_REACK USART_ISR_REACK
#define | SMARTCARD_FLAG_TEACK USART_ISR_TEACK
#define | SMARTCARD_FLAG_BUSY USART_ISR_BUSY
#define | SMARTCARD_FLAG_EOBF USART_ISR_EOBF
#define | SMARTCARD_FLAG_RTOF USART_ISR_RTOF
#define | SMARTCARD_FLAG_TXE USART_ISR_TXE
#define | SMARTCARD_FLAG_TC USART_ISR_TC
#define | SMARTCARD_FLAG_RXNE USART_ISR_RXNE
#define | SMARTCARD_FLAG_IDLE USART_ISR_IDLE
#define | SMARTCARD_FLAG_ORE USART_ISR_ORE
#define | SMARTCARD_FLAG_NE USART_ISR_NE
#define | SMARTCARD_FLAG_FE USART_ISR_FE
#define | SMARTCARD_FLAG_PE USART_ISR_PE
#define | SMARTCARD_IT_PE ((uint16_t)0x0028U)
#define | SMARTCARD_IT_TXE ((uint16_t)0x0727U)
#define | SMARTCARD_IT_TC ((uint16_t)0x0626U)
#define | SMARTCARD_IT_RXNE ((uint16_t)0x0525U)
#define | SMARTCARD_IT_IDLE ((uint16_t)0x0424U)
#define | SMARTCARD_IT_ERR ((uint16_t)0x0060U)
#define | SMARTCARD_IT_ORE ((uint16_t)0x0300U)
#define | SMARTCARD_IT_NE ((uint16_t)0x0200U)
#define | SMARTCARD_IT_FE ((uint16_t)0x0100U)
#define | SMARTCARD_IT_EOB ((uint16_t)0x0C3BU)
#define | SMARTCARD_IT_RTO ((uint16_t)0x0B3AU)
#define | SMARTCARD_CLEAR_PEF USART_ICR_PECF
#define | SMARTCARD_CLEAR_FEF USART_ICR_FECF
#define | SMARTCARD_CLEAR_NEF USART_ICR_NCF
#define | SMARTCARD_CLEAR_OREF USART_ICR_ORECF
#define | SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF
#define | SMARTCARD_CLEAR_TCF USART_ICR_TCCF
#define | SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF
#define | SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF
#define | SMARTCARD_CR3_SCARCNT_LSB_POS ( 17U)
#define | SMARTCARD_GTPR_GT_LSB_POS ( 8U)
#define | SMARTCARD_RTOR_BLEN_LSB_POS ( 24U)
#define | SMARTCARD_IT_MASK ((uint16_t)0x001FU)
#define | SMARTCARD_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | SMARTCARD_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)
#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle states.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)
Flush the Smartcard Data registers.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified SMARTCARD pending flag.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
Check whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified SmartCard interrupt source is enabled or not.
#define | __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
#define | __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific SMARTCARD request flag.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.
#define | IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001U)
Check the Baud rate range.
#define | IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
Check the block length range.
#define | IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
Check the SMARTCARD autoretry counter value.
#define | IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
Ensure that SMARTCARD frame length is valid.
#define | IS_SMARTCARD_STOPBITS(__STOPBITS__)
Ensure that SMARTCARD frame number of stop bits is valid.
#define | IS_SMARTCARD_PARITY(__PARITY__)
Ensure that SMARTCARD frame parity is valid.
#define | IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3U) == 0x00U) && ((__MODE__) != (uint16_t)0x00U))
Ensure that SMARTCARD communication mode is valid.
#define | IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
Ensure that SMARTCARD frame polarity is valid.
#define | IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
Ensure that SMARTCARD frame phase is valid.
#define | IS_SMARTCARD_LASTBIT(__LASTBIT__)
Ensure that SMARTCARD frame last bit clock pulse setting is valid.
#define | IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that SMARTCARD frame sampling is valid.
#define | IS_SMARTCARD_NACK(__NACK__)
Ensure that SMARTCARD NACK transmission setting is valid.
#define | IS_SMARTCARD_TIMEOUT(__TIMEOUT__)
Ensure that SMARTCARD receiver timeout setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_INIT(__INIT__)
Ensure that SMARTCARD advanced features initialization is valid.
#define | IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__)
Ensure that SMARTCARD frame TX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__)
Ensure that SMARTCARD frame RX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that SMARTCARD frame data inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__)
Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
#define | IS_SMARTCARD_OVERRUN(__OVERRUN__)
Ensure that SMARTCARD frame overrun setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that SMARTCARD frame MSB first setting is valid.
#define | IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__)
Ensure that SMARTCARD request parameter is valid.

Enumerations

enum HAL_SMARTCARD_StateTypeDef {
HAL_SMARTCARD_STATE_RESET = 0x00U, HAL_SMARTCARD_STATE_READY = 0x20U, HAL_SMARTCARD_STATE_BUSY = 0x24U, HAL_SMARTCARD_STATE_BUSY_TX = 0x21U,
HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, HAL_SMARTCARD_STATE_ERROR = 0xE0U
}
HAL SMARTCARD State structures definition. More...
enum SMARTCARD_ClockSourceTypeDef {
SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, SMARTCARD_CLOCKSOURCE_HSI = 0x02U, SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U,
SMARTCARD_CLOCKSOURCE_LSE = 0x08U, SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U
}
SMARTCARD clock sources. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

Header file of SMARTCARD HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_smartcard.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_smartcard_ex.h File Reference

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Defines | Functions
stm32f3xx_hal_smartcard_ex.h File Reference

Header file of SMARTCARD HAL Extended module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Defines

#define | SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the SMARTCARD clock source.

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.

Detailed Description

Header file of SMARTCARD HAL Extended module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_smartcard_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_smbus.h File Reference

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stm32f3xx_hal_smbus.h File Reference

Header file of SMBUS HAL module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SMBUS_InitTypeDef
struct | SMBUS_HandleTypeDef

Defines

#define | HAL_SMBUS_STATE_RESET (0x00000000U)
#define | HAL_SMBUS_STATE_READY (0x00000001U)
#define | HAL_SMBUS_STATE_BUSY (0x00000002U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)
#define | HAL_SMBUS_STATE_TIMEOUT (0x00000003U)
#define | HAL_SMBUS_STATE_ERROR (0x00000004U)
#define | HAL_SMBUS_STATE_LISTEN (0x00000008U)
#define | HAL_SMBUS_ERROR_NONE (0x00000000U)
#define | HAL_SMBUS_ERROR_BERR (0x00000001U)
#define | HAL_SMBUS_ERROR_ARLO (0x00000002U)
#define | HAL_SMBUS_ERROR_ACKF (0x00000004U)
#define | HAL_SMBUS_ERROR_OVR (0x00000008U)
#define | HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)
#define | HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)
#define | HAL_SMBUS_ERROR_ALERT (0x00000040U)
#define | HAL_SMBUS_ERROR_PECERR (0x00000080U)
#define | SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
#define | SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
#define | SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
#define | SMBUS_DUALADDRESS_DISABLE (0x00000000U)
#define | SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define | SMBUS_OA2_NOMASK ((uint8_t)0x00U)
#define | SMBUS_OA2_MASK01 ((uint8_t)0x01U)
#define | SMBUS_OA2_MASK02 ((uint8_t)0x02U)
#define | SMBUS_OA2_MASK03 ((uint8_t)0x03U)
#define | SMBUS_OA2_MASK04 ((uint8_t)0x04U)
#define | SMBUS_OA2_MASK05 ((uint8_t)0x05U)
#define | SMBUS_OA2_MASK06 ((uint8_t)0x06U)
#define | SMBUS_OA2_MASK07 ((uint8_t)0x07U)
#define | SMBUS_GENERALCALL_DISABLE (0x00000000U)
#define | SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
#define | SMBUS_NOSTRETCH_DISABLE (0x00000000U)
#define | SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define | SMBUS_PEC_DISABLE (0x00000000U)
#define | SMBUS_PEC_ENABLE I2C_CR1_PECEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
#define | SMBUS_SOFTEND_MODE (0x00000000U)
#define | SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define | SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define | SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
#define | SMBUS_NO_STARTSTOP (0x00000000U)
#define | SMBUS_GENERATE_STOP I2C_CR2_STOP
#define | SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | SMBUS_GENERATE_START_WRITE I2C_CR2_START
#define | SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
#define | SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
#define | SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
#define | SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
#define | SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
#define | SMBUS_IT_ERRI I2C_CR1_ERRIE
#define | SMBUS_IT_TCI I2C_CR1_TCIE
#define | SMBUS_IT_STOPI I2C_CR1_STOPIE
#define | SMBUS_IT_NACKI I2C_CR1_NACKIE
#define | SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define | SMBUS_IT_RXI I2C_CR1_RXIE
#define | SMBUS_IT_TXI I2C_CR1_TXIE
#define | SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
#define | SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
#define | SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define | SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
#define | SMBUS_FLAG_TXE I2C_ISR_TXE
#define | SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define | SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define | SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define | SMBUS_FLAG_AF I2C_ISR_NACKF
#define | SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define | SMBUS_FLAG_TC I2C_ISR_TC
#define | SMBUS_FLAG_TCR I2C_ISR_TCR
#define | SMBUS_FLAG_BERR I2C_ISR_BERR
#define | SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define | SMBUS_FLAG_OVR I2C_ISR_OVR
#define | SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define | SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define | SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define | SMBUS_FLAG_DIR I2C_ISR_DIR
#define | __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
Reset SMBUS handle state.
#define | __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified SMBUS interrupts.
#define | __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified SMBUS interrupts.
#define | __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SMBUS interrupt source is enabled or not.
#define | SMBUS_FLAG_MASK (0x0001FFFFU)
Check whether the specified SMBUS flag is set or not.
#define | __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
#define | __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified SMBUS peripheral.
#define | __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified SMBUS peripheral.
#define | __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
#define | IS_SMBUS_ANALOG_FILTER(FILTER)
#define | IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_SMBUS_ADDRESSING_MODE(MODE)
#define | IS_SMBUS_DUAL_ADDRESS(ADDRESS)
#define | IS_SMBUS_OWN_ADDRESS2_MASK(MASK)
#define | IS_SMBUS_GENERAL_CALL(CALL)
#define | IS_SMBUS_NO_STRETCH(STRETCH)
#define | IS_SMBUS_PEC(PEC)
#define | IS_SMBUS_PERIPHERAL_MODE(MODE)
#define | IS_SMBUS_TRANSFER_MODE(MODE)
#define | IS_SMBUS_TRANSFER_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
#define | SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | SMBUS_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
#define | SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define | SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define | SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define | SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
#define | SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
#define | IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)

Functions

HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_ConfigAnalogFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
Configure Analog noise filter.
HAL_StatusTypeDef | HAL_SMBUS_ConfigDigitalFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
Configure Digital noise filter.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.
HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.
uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

Header file of SMBUS HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_smbus.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_spi.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32f3xx_hal_spi.h File Reference

Header file of SPI HAL module. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_spi_ex.h"

Go to the source code of this file.

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Defines

#define | HAL_SPI_ERROR_NONE (0x00000000U)
#define | HAL_SPI_ERROR_MODF (0x00000001U)
#define | HAL_SPI_ERROR_CRC (0x00000002U)
#define | HAL_SPI_ERROR_OVR (0x00000004U)
#define | HAL_SPI_ERROR_FRE (0x00000008U)
#define | HAL_SPI_ERROR_DMA (0x00000010U)
#define | HAL_SPI_ERROR_FLAG (0x00000020U)
#define | HAL_SPI_ERROR_ABORT (0x00000040U)
#define | SPI_MODE_SLAVE (0x00000000U)
#define | SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | SPI_DIRECTION_2LINES (0x00000000U)
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define | SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
#define | SPI_DATASIZE_4BIT (0x00000300U)
#define | SPI_DATASIZE_5BIT (0x00000400U)
#define | SPI_DATASIZE_6BIT (0x00000500U)
#define | SPI_DATASIZE_7BIT (0x00000600U)
#define | SPI_DATASIZE_8BIT (0x00000700U)
#define | SPI_DATASIZE_9BIT (0x00000800U)
#define | SPI_DATASIZE_10BIT (0x00000900U)
#define | SPI_DATASIZE_11BIT (0x00000A00U)
#define | SPI_DATASIZE_12BIT (0x00000B00U)
#define | SPI_DATASIZE_13BIT (0x00000C00U)
#define | SPI_DATASIZE_14BIT (0x00000D00U)
#define | SPI_DATASIZE_15BIT (0x00000E00U)
#define | SPI_DATASIZE_16BIT (0x00000F00U)
#define | SPI_POLARITY_LOW (0x00000000U)
#define | SPI_POLARITY_HIGH SPI_CR1_CPOL
#define | SPI_PHASE_1EDGE (0x00000000U)
#define | SPI_PHASE_2EDGE SPI_CR1_CPHA
#define | SPI_NSS_SOFT SPI_CR1_SSM
#define | SPI_NSS_HARD_INPUT (0x00000000U)
#define | SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
#define | SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
#define | SPI_NSS_PULSE_DISABLE (0x00000000U)
#define | SPI_BAUDRATEPRESCALER_2 (0x00000000U)
#define | SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
#define | SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | SPI_FIRSTBIT_MSB (0x00000000U)
#define | SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
#define | SPI_TIMODE_DISABLE (0x00000000U)
#define | SPI_TIMODE_ENABLE SPI_CR2_FRF
#define | SPI_CRCCALCULATION_DISABLE (0x00000000U)
#define | SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
#define | SPI_CRC_LENGTH_DATASIZE (0x00000000U)
#define | SPI_CRC_LENGTH_8BIT (0x00000001U)
#define | SPI_CRC_LENGTH_16BIT (0x00000002U)
#define | SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
#define | SPI_IT_TXE SPI_CR2_TXEIE
#define | SPI_IT_RXNE SPI_CR2_RXNEIE
#define | SPI_IT_ERR SPI_CR2_ERRIE
#define | SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define | SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define | SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
#define | SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
#define | SPI_FTLVL_EMPTY (0x00000000U)
#define | SPI_FTLVL_QUARTER_FULL (0x00000800U)
#define | SPI_FTLVL_HALF_FULL (0x00001000U)
#define | SPI_FTLVL_FULL (0x00001800U)
#define | SPI_FRLVL_EMPTY (0x00000000U)
#define | SPI_FRLVL_QUARTER_FULL (0x00000200U)
#define | SPI_FRLVL_HALF_FULL (0x00000400U)
#define | SPI_FRLVL_FULL (0x00000600U)
#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Enable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Disable the specified SPI interrupts.
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)
Clear the SPI FRE pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Disable the SPI peripheral.
#define | SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Set the SPI receive-only mode.
#define | SPI_RESET_CRC(__HANDLE__)
Reset the CRC calculation of the SPI.
#define | IS_SPI_MODE(MODE)
#define | IS_SPI_DIRECTION(MODE)
#define | IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE)
#define | IS_SPI_DATASIZE(DATASIZE)
#define | IS_SPI_CPOL(CPOL)
#define | IS_SPI_CPHA(CPHA)
#define | IS_SPI_NSS(NSS)
#define | IS_SPI_NSSP(NSSP)
#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | IS_SPI_FIRST_BIT(BIT)
#define | IS_SPI_TIMODE(MODE)
#define | IS_SPI_CRC_CALCULATION(CALCULATION)
#define | IS_SPI_CRC_LENGTH(LENGTH)
#define | IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
#define | IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL)

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00U, HAL_SPI_STATE_READY = 0x01U, HAL_SPI_STATE_BUSY = 0x02U, HAL_SPI_STATE_BUSY_TX = 0x03U,
HAL_SPI_STATE_BUSY_RX = 0x04U, HAL_SPI_STATE_BUSY_TX_RX = 0x05U, HAL_SPI_STATE_ERROR = 0x06U, HAL_SPI_STATE_ABORT = 0x07U
}
HAL SPI State structure definition. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

Header file of SPI HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_spi.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_spi_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32F3xx_HAL_Driver
  • Inc
Functions
stm32f3xx_hal_spi_ex.h File Reference

Header file of SPI HAL Extended module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.

Detailed Description

Header file of SPI HAL Extended module.

Author:
MCD Application Team
Attention:

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Definition in file stm32f3xx_hal_spi_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_tim.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32f3xx_hal_tim.h File Reference

Header file of TIM HAL module. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_tim_ex.h"

Go to the source code of this file.

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
TIM Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Defines

#define | TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U)
#define | TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
#define | TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)
#define | TIM_ETRPOLARITY_NONINVERTED (0x0000U)
#define | TIM_ETRPRESCALER_DIV1 (0x0000U)
#define | TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)
#define | TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)
#define | TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)
#define | TIM_COUNTERMODE_UP (0x0000U)
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
#define | TIM_CLOCKDIVISION_DIV1 (0x0000U)
#define | TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define | TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
#define | TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U)
#define | TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE)
#define | TIM_OCFAST_DISABLE (0x0000U)
#define | TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
#define | TIM_OCPOLARITY_HIGH (0x0000U)
#define | TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
#define | TIM_OCNPOLARITY_HIGH (0x0000U)
#define | TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
#define | TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
#define | TIM_OCIDLESTATE_RESET (0x0000U)
#define | TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
#define | TIM_OCNIDLESTATE_RESET (0x0000U)
#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)
#define | TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)
#define | TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)
#define | TIM_ICPSC_DIV1 (0x0000U)
#define | TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)
#define | TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)
#define | TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)
#define | TIM_OPMODE_SINGLE (TIM_CR1_OPM)
#define | TIM_OPMODE_REPETITIVE (0x0000U)
#define | TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_IT_UPDATE (TIM_DIER_UIE)
#define | TIM_IT_CC1 (TIM_DIER_CC1IE)
#define | TIM_IT_CC2 (TIM_DIER_CC2IE)
#define | TIM_IT_CC3 (TIM_DIER_CC3IE)
#define | TIM_IT_CC4 (TIM_DIER_CC4IE)
#define | TIM_IT_COM (TIM_DIER_COMIE)
#define | TIM_IT_TRIGGER (TIM_DIER_TIE)
#define | TIM_IT_BREAK (TIM_DIER_BIE)
#define | TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
#define | TIM_COMMUTATION_SOFTWARE (0x0000U)
#define | TIM_DMA_UPDATE (TIM_DIER_UDE)
#define | TIM_DMA_CC1 (TIM_DIER_CC1DE)
#define | TIM_DMA_CC2 (TIM_DIER_CC2DE)
#define | TIM_DMA_CC3 (TIM_DIER_CC3DE)
#define | TIM_DMA_CC4 (TIM_DIER_CC4DE)
#define | TIM_DMA_COM (TIM_DIER_COMDE)
#define | TIM_DMA_TRIGGER (TIM_DIER_TDE)
#define | TIM_FLAG_UPDATE (TIM_SR_UIF)
#define | TIM_FLAG_CC1 (TIM_SR_CC1IF)
#define | TIM_FLAG_CC2 (TIM_SR_CC2IF)
#define | TIM_FLAG_CC3 (TIM_SR_CC3IF)
#define | TIM_FLAG_CC4 (TIM_SR_CC4IF)
#define | TIM_FLAG_COM (TIM_SR_COMIF)
#define | TIM_FLAG_TRIGGER (TIM_SR_TIF)
#define | TIM_FLAG_BREAK (TIM_SR_BIF)
#define | TIM_FLAG_CC1OF (TIM_SR_CC1OF)
#define | TIM_FLAG_CC2OF (TIM_SR_CC2OF)
#define | TIM_FLAG_CC3OF (TIM_SR_CC3OF)
#define | TIM_FLAG_CC4OF (TIM_SR_CC4OF)
#define | TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define | TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define | TIM_CLOCKSOURCE_ITR0 (0x0000U)
#define | TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define | TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
#define | TIM_OSSR_DISABLE (0x0000U)
#define | TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
#define | TIM_OSSI_DISABLE (0x0000U)
#define | TIM_LOCKLEVEL_OFF (0x0000U)
#define | TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define | TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define | TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
#define | TIM_BREAK_ENABLE (TIM_BDTR_BKE)
#define | TIM_BREAK_DISABLE (0x0000U)
#define | TIM_BREAKPOLARITY_LOW (0x0000U)
#define | TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
#define | TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
#define | TIM_AUTOMATICOUTPUT_DISABLE (0x0000U)
#define | TIM_TRGO_RESET (0x0000U)
#define | TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define | TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define | TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
#define | TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
#define | TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_MASTERSLAVEMODE_ENABLE (0x0080U)
#define | TIM_MASTERSLAVEMODE_DISABLE (0x0000U)
#define | TIM_TS_ITR0 (0x0000U)
#define | TIM_TS_ITR1 (0x0010U)
#define | TIM_TS_ITR2 (0x0020U)
#define | TIM_TS_ITR3 (0x0030U)
#define | TIM_TS_TI1F_ED (0x0040U)
#define | TIM_TS_TI1FP1 (0x0050U)
#define | TIM_TS_TI2FP2 (0x0060U)
#define | TIM_TS_ETRF (0x0070U)
#define | TIM_TS_NONE (0xFFFFU)
#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_TI1SELECTION_CH1 (0x0000U)
#define | TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
#define | TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
#define | TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
#define | TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
#define | TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
#define | TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
#define | TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
#define | TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
#define | TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
#define | TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
#define | TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
#define | TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
#define | TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
#define | TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
#define | TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
#define | TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
#define | TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
#define | TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
#define | TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0U)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x1U)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x2U)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x3U)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x4U)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U)
#define | TIM_CCx_ENABLE (0x0001U)
#define | TIM_CCx_DISABLE (0x0000U)
#define | TIM_CCxN_ENABLE (0x0004U)
#define | TIM_CCxN_DISABLE (0x0000U)
#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
Enables the specified TIM interrupt.
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Disables the specified TIM interrupt.
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
Enables the specified DMA request.
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Disables the specified DMA request.
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Checks whether the specified TIM interrupt flag is set or not.
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clears the specified TIM interrupt flag.
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks whether the specified TIM interrupt has occurred or not.
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
Clear the TIM interrupt pending bits.
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
Indicates whether or not the TIM Counter is used as downcounter.
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
Sets the TIM active prescaler register value on update event.
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Sets the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Gets the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Sets the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Gets the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Sets the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Gets the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Sets the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Gets the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Sets the TIM Capture x input polarity on runtime.
#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
#define | IS_TIM_COUNTER_MODE(MODE)
#define | IS_TIM_CLOCKDIVISION_DIV(DIV)
#define | IS_TIM_AUTORELOAD_PRELOAD(PRELOAD)
#define | IS_TIM_FAST_STATE(STATE)
#define | IS_TIM_OC_POLARITY(POLARITY)
#define | IS_TIM_OCN_POLARITY(POLARITY)
#define | IS_TIM_OCIDLE_STATE(STATE)
#define | IS_TIM_OCNIDLE_STATE(STATE)
#define | IS_TIM_IC_POLARITY(POLARITY)
#define | IS_TIM_IC_SELECTION(SELECTION)
#define | IS_TIM_IC_PRESCALER(PRESCALER)
#define | IS_TIM_OPM_MODE(MODE)
#define | IS_TIM_ENCODER_MODE(MODE)
#define | IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define | IS_TIM_CLOCKSOURCE(CLOCK)
#define | IS_TIM_CLOCKPOLARITY(POLARITY)
#define | IS_TIM_CLOCKPRESCALER(PRESCALER)
#define | IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
#define | IS_TIM_CLEARINPUT_POLARITY(POLARITY)
#define | IS_TIM_CLEARINPUT_PRESCALER(PRESCALER)
#define | IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
#define | IS_TIM_OSSR_STATE(STATE)
#define | IS_TIM_OSSI_STATE(STATE)
#define | IS_TIM_LOCK_LEVEL(LEVEL)
#define | IS_TIM_BREAK_STATE(STATE)
#define | IS_TIM_BREAK_POLARITY(POLARITY)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE)
#define | IS_TIM_TRGO_SOURCE(SOURCE)
#define | IS_TIM_MSM_STATE(STATE)
#define | IS_TIM_TRIGGER_SELECTION(SELECTION)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION)
#define | IS_TIM_TRIGGERPOLARITY(POLARITY)
#define | IS_TIM_TRIGGERPRESCALER(PRESCALER)
#define | IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
#define | IS_TIM_TI1SELECTION(TI1SELECTION)
#define | IS_TIM_DMA_LENGTH(LENGTH)
#define | IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
#define | IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
Set TIM IC prescaler.
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
Reset TIM IC prescaler.
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Set TIM IC polarity.
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)
Reset TIM IC polarity.

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04
}
HAL State structures definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00
}
HAL Active channel structures definition. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
__weak HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
__weak HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
__weak HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiWriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode state.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 1 configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 2 configuration.
void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 3 configuration.
void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 4 configuration.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.

Detailed Description

Header file of TIM HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_tim.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_tim_ex.h File Reference

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stm32f3xx_hal_tim_ex.h File Reference

Header file of TIM HAL Extended module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break and Dead time configuration Structure definition. More...

Defines

#define | TIM_CHANNEL_1 (0x0000U)
#define | TIM_CHANNEL_2 (0x0004U)
#define | TIM_CHANNEL_3 (0x0008U)
#define | TIM_CHANNEL_4 (0x000CU)
#define | TIM_CHANNEL_ALL (0x0018U)
#define | TIM_OCMODE_TIMING (0x0000U)
#define | TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M)
#define | TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
#define | TIM_CLEARINPUTSOURCE_ETR (0x0001U)
#define | TIM_CLEARINPUTSOURCE_NONE (0x0000U)
#define | TIM_SLAVEMODE_DISABLE (0x0000U)
#define | TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
#define | TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
#define | TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
#define | TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_DMABASE_CR1 (0x00000000U)
#define | TIM_DMABASE_CR2 (0x00000001U)
#define | TIM_DMABASE_SMCR (0x00000002U)
#define | TIM_DMABASE_DIER (0x00000003U)
#define | TIM_DMABASE_SR (0x00000004U)
#define | TIM_DMABASE_EGR (0x00000005U)
#define | TIM_DMABASE_CCMR1 (0x00000006U)
#define | TIM_DMABASE_CCMR2 (0x00000007U)
#define | TIM_DMABASE_CCER (0x00000008U)
#define | TIM_DMABASE_CNT (0x00000009U)
#define | TIM_DMABASE_PSC (0x0000000AU)
#define | TIM_DMABASE_ARR (0x0000000BU)
#define | TIM_DMABASE_RCR (0x0000000CU)
#define | TIM_DMABASE_CCR1 (0x0000000DU)
#define | TIM_DMABASE_CCR2 (0x0000000EU)
#define | TIM_DMABASE_CCR3 (0x0000000FU)
#define | TIM_DMABASE_CCR4 (0x00000010U)
#define | TIM_DMABASE_BDTR (0x00000011U)
#define | TIM_DMABASE_DCR (0x00000012U)
#define | TIM_DMABASE_OR (0x00000013U)
#define | TIM_TIM2_TIM8_TRGO (0x00000000U)
#define | TIM_TIM2_ETH_PTP (0x00000400U)
#define | TIM_TIM2_USBFS_SOF (0x00000800U)
#define | TIM_TIM2_USBHS_SOF (0x00000C00U)
#define | TIM_TIM14_GPIO (0x00000000U)
#define | TIM_TIM14_RTC (0x00000001U)
#define | TIM_TIM14_HSE (0x00000002U)
#define | TIM_TIM14_MCO (0x00000003U)
#define | IS_TIM_CHANNELS(CHANNEL)
#define | IS_TIM_OPM_CHANNELS(CHANNEL)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL)
#define | IS_TIM_PWM_MODE(MODE)
#define | IS_TIM_OC_MODE(MODE)
#define | IS_TIM_CLEARINPUT_SOURCE(SOURCE)
#define | IS_TIM_SLAVE_MODE(MODE)
#define | IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define | IS_TIM_DMA_BASE(BASE)
#define | IS_TIM_REMAP(REMAP)
#define | IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU)
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
Sets the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
Gets the TIM Capture Compare Register value on runtime.
#define | __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Sets the TIM Output compare preload.
#define | __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Resets the TIM Output compare preload.

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complemetary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIM2 and TIM14 Remapping input capabilities.
__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non blocking mode.
__weak void | HAL_TIMEx_Break2Callback (TIM_HandleTypeDef *htim)
Hall Break2 detection callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface state.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.

Detailed Description

Header file of TIM HAL Extended module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_tim_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_tsc.h File Reference

  • File List
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  • Firmware
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Data Structures | Defines | Enumerations | Functions
stm32f3xx_hal_tsc.h File Reference

Header file of TSC HAL module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | TSC_InitTypeDef
TSC init structure definition. More...
struct | TSC_IOConfigTypeDef
TSC IOs configuration structure definition. More...
struct | TSC_HandleTypeDef
TSC handle Structure definition. More...

Defines

#define | TSC_CTPH_1CYCLE ((uint32_t)( 0U << 28U))
#define | TSC_CTPH_2CYCLES ((uint32_t)( 1U << 28U))
#define | TSC_CTPH_3CYCLES ((uint32_t)( 2U << 28U))
#define | TSC_CTPH_4CYCLES ((uint32_t)( 3U << 28U))
#define | TSC_CTPH_5CYCLES ((uint32_t)( 4U << 28U))
#define | TSC_CTPH_6CYCLES ((uint32_t)( 5U << 28U))
#define | TSC_CTPH_7CYCLES ((uint32_t)( 6U << 28U))
#define | TSC_CTPH_8CYCLES ((uint32_t)( 7U << 28U))
#define | TSC_CTPH_9CYCLES ((uint32_t)( 8U << 28U))
#define | TSC_CTPH_10CYCLES ((uint32_t)( 9U << 28U))
#define | TSC_CTPH_11CYCLES ((uint32_t)(10U << 28U))
#define | TSC_CTPH_12CYCLES ((uint32_t)(11U << 28U))
#define | TSC_CTPH_13CYCLES ((uint32_t)(12U << 28U))
#define | TSC_CTPH_14CYCLES ((uint32_t)(13U << 28U))
#define | TSC_CTPH_15CYCLES ((uint32_t)(14U << 28U))
#define | TSC_CTPH_16CYCLES ((uint32_t)(15U << 28U))
#define | TSC_CTPL_1CYCLE ((uint32_t)( 0U << 24U))
#define | TSC_CTPL_2CYCLES ((uint32_t)( 1U << 24U))
#define | TSC_CTPL_3CYCLES ((uint32_t)( 2U << 24U))
#define | TSC_CTPL_4CYCLES ((uint32_t)( 3U << 24U))
#define | TSC_CTPL_5CYCLES ((uint32_t)( 4U << 24U))
#define | TSC_CTPL_6CYCLES ((uint32_t)( 5U << 24U))
#define | TSC_CTPL_7CYCLES ((uint32_t)( 6U << 24U))
#define | TSC_CTPL_8CYCLES ((uint32_t)( 7U << 24U))
#define | TSC_CTPL_9CYCLES ((uint32_t)( 8U << 24U))
#define | TSC_CTPL_10CYCLES ((uint32_t)( 9U << 24U))
#define | TSC_CTPL_11CYCLES ((uint32_t)(10U << 24U))
#define | TSC_CTPL_12CYCLES ((uint32_t)(11U << 24U))
#define | TSC_CTPL_13CYCLES ((uint32_t)(12U << 24U))
#define | TSC_CTPL_14CYCLES ((uint32_t)(13U << 24U))
#define | TSC_CTPL_15CYCLES ((uint32_t)(14U << 24U))
#define | TSC_CTPL_16CYCLES ((uint32_t)(15U << 24U))
#define | TSC_SS_PRESC_DIV1 (0U)
#define | TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC)
#define | TSC_PG_PRESC_DIV1 ((uint32_t)(0U << 12U))
#define | TSC_PG_PRESC_DIV2 ((uint32_t)(1U << 12U))
#define | TSC_PG_PRESC_DIV4 ((uint32_t)(2U << 12U))
#define | TSC_PG_PRESC_DIV8 ((uint32_t)(3U << 12U))
#define | TSC_PG_PRESC_DIV16 ((uint32_t)(4U << 12U))
#define | TSC_PG_PRESC_DIV32 ((uint32_t)(5U << 12U))
#define | TSC_PG_PRESC_DIV64 ((uint32_t)(6U << 12U))
#define | TSC_PG_PRESC_DIV128 ((uint32_t)(7U << 12U))
#define | TSC_MCV_255 ((uint32_t)(0U << 5U))
#define | TSC_MCV_511 ((uint32_t)(1U << 5U))
#define | TSC_MCV_1023 ((uint32_t)(2U << 5U))
#define | TSC_MCV_2047 ((uint32_t)(3U << 5U))
#define | TSC_MCV_4095 ((uint32_t)(4U << 5U))
#define | TSC_MCV_8191 ((uint32_t)(5U << 5U))
#define | TSC_MCV_16383 ((uint32_t)(6U << 5U))
#define | TSC_IODEF_OUT_PP_LOW (0U)
#define | TSC_IODEF_IN_FLOAT (TSC_CR_IODEF)
#define | TSC_SYNC_POLARITY_FALLING (0U)
#define | TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)
#define | TSC_ACQ_MODE_NORMAL (0U)
#define | TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
#define | TSC_IOMODE_UNUSED (0U)
#define | TSC_IOMODE_CHANNEL (1U)
#define | TSC_IOMODE_SHIELD (2U)
#define | TSC_IOMODE_SAMPLING (3U)
#define | TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
#define | TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)
#define | TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
#define | TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
#define | TSC_NB_OF_GROUPS (8U)
#define | TSC_GROUP1 (0x00000001U)
#define | TSC_GROUP2 (0x00000002U)
#define | TSC_GROUP3 (0x00000004U)
#define | TSC_GROUP4 (0x00000008U)
#define | TSC_GROUP5 (0x00000010U)
#define | TSC_GROUP6 (0x00000020U)
#define | TSC_GROUP7 (0x00000040U)
#define | TSC_GROUP8 (0x00000080U)
#define | TSC_ALL_GROUPS (0x000000FFU)
#define | TSC_GROUP1_IDX (0U)
#define | TSC_GROUP2_IDX (1U)
#define | TSC_GROUP3_IDX (2U)
#define | TSC_GROUP4_IDX (3U)
#define | TSC_GROUP5_IDX (4U)
#define | TSC_GROUP6_IDX (5U)
#define | TSC_GROUP7_IDX (6U)
#define | TSC_GROUP8_IDX (7U)
#define | TSC_GROUP1_IO1 (0x00000001U)
#define | TSC_GROUP1_IO2 (0x00000002U)
#define | TSC_GROUP1_IO3 (0x00000004U)
#define | TSC_GROUP1_IO4 (0x00000008U)
#define | TSC_GROUP1_ALL_IOS (0x0000000FU)
#define | TSC_GROUP2_IO1 (0x00000010U)
#define | TSC_GROUP2_IO2 (0x00000020U)
#define | TSC_GROUP2_IO3 (0x00000040U)
#define | TSC_GROUP2_IO4 (0x00000080U)
#define | TSC_GROUP2_ALL_IOS (0x000000F0U)
#define | TSC_GROUP3_IO1 (0x00000100U)
#define | TSC_GROUP3_IO2 (0x00000200U)
#define | TSC_GROUP3_IO3 (0x00000400U)
#define | TSC_GROUP3_IO4 (0x00000800U)
#define | TSC_GROUP3_ALL_IOS (0x00000F00U)
#define | TSC_GROUP4_IO1 (0x00001000U)
#define | TSC_GROUP4_IO2 (0x00002000U)
#define | TSC_GROUP4_IO3 (0x00004000U)
#define | TSC_GROUP4_IO4 (0x00008000U)
#define | TSC_GROUP4_ALL_IOS (0x0000F000U)
#define | TSC_GROUP5_IO1 (0x00010000U)
#define | TSC_GROUP5_IO2 (0x00020000U)
#define | TSC_GROUP5_IO3 (0x00040000U)
#define | TSC_GROUP5_IO4 (0x00080000U)
#define | TSC_GROUP5_ALL_IOS (0x000F0000U)
#define | TSC_GROUP6_IO1 (0x00100000U)
#define | TSC_GROUP6_IO2 (0x00200000U)
#define | TSC_GROUP6_IO3 (0x00400000U)
#define | TSC_GROUP6_IO4 (0x00800000U)
#define | TSC_GROUP6_ALL_IOS (0x00F00000U)
#define | TSC_GROUP7_IO1 (0x01000000U)
#define | TSC_GROUP7_IO2 (0x02000000U)
#define | TSC_GROUP7_IO3 (0x04000000U)
#define | TSC_GROUP7_IO4 (0x08000000U)
#define | TSC_GROUP7_ALL_IOS (0x0F000000U)
#define | TSC_GROUP8_IO1 (0x10000000U)
#define | TSC_GROUP8_IO2 (0x20000000U)
#define | TSC_GROUP8_IO3 (0x40000000U)
#define | TSC_GROUP8_IO4 (0x80000000U)
#define | TSC_GROUP8_ALL_IOS (0xF0000000U)
#define | TSC_ALL_GROUPS_ALL_IOS (0xFFFFFFFFU)
#define | __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
Reset TSC handle state.
#define | __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
Enable the TSC peripheral.
#define | __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
Disable the TSC peripheral.
#define | __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
Start acquisition.
#define | __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
Stop acquisition.
#define | __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
Set IO default mode to output push-pull low.
#define | __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
Set IO default mode to input floating.
#define | __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
Set synchronization polarity to falling edge.
#define | __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
Set synchronization polarity to rising edge and high level.
#define | __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable TSC interrupt.
#define | __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
Disable TSC interrupt.
#define | __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified TSC interrupt source is enabled or not.
#define | __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
Check whether the specified TSC flag is set or not.
#define | __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the TSC's pending flag.
#define | __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
Enable schmitt trigger hysteresis on a group of IOs.
#define | __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
Disable schmitt trigger hysteresis on a group of IOs.
#define | __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
Open analog switch on a group of IOs.
#define | __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
Close analog switch on a group of IOs.
#define | __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
Enable a group of IOs in channel mode.
#define | __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
Disable a group of channel IOs.
#define | __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
Enable a group of IOs in sampling mode.
#define | __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
Disable a group of sampling IOs.
#define | __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
Enable acquisition groups.
#define | __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
Disable acquisition groups.
#define | __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) == (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
Gets acquisition group status.
#define | IS_TSC_CTPH(VAL)
#define | IS_TSC_CTPL(VAL)
#define | IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
#define | IS_TSC_SSD(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < 128U)))
#define | IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
#define | IS_TSC_PG_PRESC(VAL)
#define | IS_TSC_MCV(VAL)
#define | IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
#define | IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
#define | IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
#define | IS_TSC_IOMODE(VAL)
#define | IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
#define | IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < TSC_NB_OF_GROUPS)))

Enumerations

enum | HAL_TSC_StateTypeDef { HAL_TSC_STATE_RESET = 0x00U, HAL_TSC_STATE_READY = 0x01U, HAL_TSC_STATE_BUSY = 0x02U, HAL_TSC_STATE_ERROR = 0x03U }
TSC state structure definition. More...
enum | TSC_GroupStatusTypeDef { TSC_GROUP_ONGOING = 0x00U, TSC_GROUP_COMPLETED = 0x01U }
TSC group status structure definition. More...

Functions

HAL_StatusTypeDef | HAL_TSC_Init (TSC_HandleTypeDef *htsc)
Initialize the TSC peripheral according to the specified parameters in the TSC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_TSC_DeInit (TSC_HandleTypeDef *htsc)
Deinitialize the TSC peripheral registers to their default reset values.
__weak void | HAL_TSC_MspInit (TSC_HandleTypeDef *htsc)
Initialize the TSC MSP.
__weak void | HAL_TSC_MspDeInit (TSC_HandleTypeDef *htsc)
DeInitialize the TSC MSP.
HAL_StatusTypeDef | HAL_TSC_Start (TSC_HandleTypeDef *htsc)
Start the acquisition.
HAL_StatusTypeDef | HAL_TSC_Start_IT (TSC_HandleTypeDef *htsc)
Start the acquisition in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_Stop (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in polling mode.
HAL_StatusTypeDef | HAL_TSC_Stop_IT (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_PollForAcquisition (TSC_HandleTypeDef *htsc)
Start acquisition and wait until completion.
TSC_GroupStatusTypeDef | HAL_TSC_GroupGetStatus (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition status for a group.
uint32_t | HAL_TSC_GroupGetValue (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition measure for a group.
HAL_StatusTypeDef | HAL_TSC_IOConfig (TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config)
Configure TSC IOs.
HAL_StatusTypeDef | HAL_TSC_IODischarge (TSC_HandleTypeDef *htsc, uint32_t choice)
Discharge TSC IOs.
HAL_TSC_StateTypeDef | HAL_TSC_GetState (TSC_HandleTypeDef *htsc)
Return the TSC handle state.
void | HAL_TSC_IRQHandler (TSC_HandleTypeDef *htsc)
Handle TSC interrupt request.
__weak void | HAL_TSC_ConvCpltCallback (TSC_HandleTypeDef *htsc)
Acquisition completed callback in non-blocking mode.
__weak void | HAL_TSC_ErrorCallback (TSC_HandleTypeDef *htsc)
Error callback in non-blocking mode.

Detailed Description

Header file of TSC HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_tsc.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_uart.h File Reference

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stm32f3xx_hal_uart.h File Reference

Header file of UART HAL module. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_uart_ex.h"

Go to the source code of this file.

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_AdvFeatureInitTypeDef
UART Advanced Features initalization structure definition. More...
struct | UART_WakeUpTypeDef
UART wake up from stop mode parameters. More...
struct | UART_HandleTypeDef
UART handle Structure definition. More...

Defines

#define | HAL_UART_ERROR_NONE (0x00000000U)
#define | HAL_UART_ERROR_PE (0x00000001U)
#define | HAL_UART_ERROR_NE (0x00000002U)
#define | HAL_UART_ERROR_FE (0x00000004U)
#define | HAL_UART_ERROR_ORE (0x00000008U)
#define | HAL_UART_ERROR_DMA (0x00000010U)
#define | HAL_UART_ERROR_BUSY (0x00000020U)
#define | UART_STOPBITS_0_5 USART_CR2_STOP_0
#define | UART_STOPBITS_1 (0x00000000U)
#define | UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define | UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define | UART_PARITY_NONE (0x00000000U)
#define | UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | UART_HWCONTROL_NONE (0x00000000U)
#define | UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define | UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define | UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
#define | UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | UART_STATE_DISABLE (0x00000000U)
#define | UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
#define | UART_OVERSAMPLING_16 (0x00000000U)
#define | UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
#define | UART_ONE_BIT_SAMPLE_DISABLE (0x00000000U)
#define | UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT (0x00000000U)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)
#define | UART_RECEIVER_TIMEOUT_DISABLE (0x00000000U)
#define | UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)
#define | UART_LIN_DISABLE (0x00000000U)
#define | UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)
#define | UART_LINBREAKDETECTLENGTH_10B (0x00000000U)
#define | UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
#define | UART_DMA_TX_DISABLE (0x00000000U)
#define | UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
#define | UART_DMA_RX_DISABLE (0x00000000U)
#define | UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
#define | UART_HALF_DUPLEX_DISABLE (0x00000000U)
#define | UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)
#define | UART_ADDRESS_DETECT_4B (0x00000000U)
#define | UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)
#define | UART_WAKEUPMETHOD_IDLELINE (0x00000000U)
#define | UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
#define | UART_FLAG_REACK (0x00400000U)
#define | UART_FLAG_TEACK (0x00200000U)
#define | UART_FLAG_WUF (0x00100000U)
#define | UART_FLAG_RWU (0x00080000U)
#define | UART_FLAG_SBKF (0x00040000U)
#define | UART_FLAG_CMF (0x00020000U)
#define | UART_FLAG_BUSY (0x00010000U)
#define | UART_FLAG_ABRF (0x00008000U)
#define | UART_FLAG_ABRE (0x00004000U)
#define | UART_FLAG_EOBF (0x00001000U)
#define | UART_FLAG_RTOF (0x00000800U)
#define | UART_FLAG_CTS (0x00000400U)
#define | UART_FLAG_CTSIF (0x00000200U)
#define | UART_FLAG_LBDF (0x00000100U)
#define | UART_FLAG_TXE (0x00000080U)
#define | UART_FLAG_TC (0x00000040U)
#define | UART_FLAG_RXNE (0x00000020U)
#define | UART_FLAG_IDLE (0x00000010U)
#define | UART_FLAG_ORE (0x00000008U)
#define | UART_FLAG_NE (0x00000004U)
#define | UART_FLAG_FE (0x00000002U)
#define | UART_FLAG_PE (0x00000001U)
#define | UART_IT_PE (0x0028U)
#define | UART_IT_TXE (0x0727U)
#define | UART_IT_TC (0x0626U)
#define | UART_IT_RXNE (0x0525U)
#define | UART_IT_IDLE (0x0424U)
#define | UART_IT_LBD (0x0846U)
#define | UART_IT_CTS (0x096AU)
#define | UART_IT_CM (0x112EU)
#define | UART_IT_WUF (0x1476U)
#define | UART_IT_ERR (0x0060U)
#define | UART_IT_ORE (0x0300U)
#define | UART_IT_NE (0x0200U)
#define | UART_IT_FE (0x0100U)
#define | UART_CLEAR_PEF USART_ICR_PECF
#define | UART_CLEAR_FEF USART_ICR_FECF
#define | UART_CLEAR_NEF USART_ICR_NCF
#define | UART_CLEAR_OREF USART_ICR_ORECF
#define | UART_CLEAR_IDLEF USART_ICR_IDLECF
#define | UART_CLEAR_TCF USART_ICR_TCCF
#define | UART_CLEAR_LBDF USART_ICR_LBDCF
#define | UART_CLEAR_CTSF USART_ICR_CTSCF
#define | UART_CLEAR_RTOF USART_ICR_RTOCF
#define | UART_CLEAR_EOBF USART_ICR_EOBCF
#define | UART_CLEAR_CMF USART_ICR_CMCF
#define | UART_CLEAR_WUF USART_ICR_WUCF
#define | UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ)
#define | UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ)
#define | UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ)
#define | UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)
#define | UART_ADVFEATURE_NO_INIT (0x00000000U)
#define | UART_ADVFEATURE_TXINVERT_INIT (0x00000001U)
#define | UART_ADVFEATURE_RXINVERT_INIT (0x00000002U)
#define | UART_ADVFEATURE_DATAINVERT_INIT (0x00000004U)
#define | UART_ADVFEATURE_SWAP_INIT (0x00000008U)
#define | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U)
#define | UART_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U)
#define | UART_ADVFEATURE_AUTOBAUDRATE_INIT (0x00000040U)
#define | UART_ADVFEATURE_MSBFIRST_INIT (0x00000080U)
#define | UART_ADVFEATURE_TXINV_DISABLE (0x00000000U)
#define | UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
#define | UART_ADVFEATURE_RXINV_DISABLE (0x00000000U)
#define | UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
#define | UART_ADVFEATURE_DATAINV_DISABLE (0x00000000U)
#define | UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
#define | UART_ADVFEATURE_SWAP_DISABLE (0x00000000U)
#define | UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
#define | UART_ADVFEATURE_OVERRUN_ENABLE (0x00000000U)
#define | UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
#define | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE (0x00000000U)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)
#define | UART_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U)
#define | UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
#define | UART_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U)
#define | UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
#define | UART_ADVFEATURE_STOPMODE_DISABLE (0x00000000U)
#define | UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM)
#define | UART_ADVFEATURE_MUTEMODE_DISABLE (0x00000000U)
#define | UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)
#define | UART_CR2_ADDRESS_LSB_POS ( 24U)
#define | UART_WAKEUP_ON_ADDRESS (0x00000000U)
#define | UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1)
#define | UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS)
#define | UART_DE_POLARITY_HIGH (0x00000000U)
#define | UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)
#define | UART_CR1_DEAT_ADDRESS_LSB_POS ( 21U)
#define | UART_CR1_DEDT_ADDRESS_LSB_POS ( 16U)
#define | UART_IT_MASK (0x001FU)
#define | HAL_UART_TIMEOUT_VALUE 0x1FFFFFF
#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle states.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)
Flush the UART Data registers.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
Clear the UART IDLE pending flag.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified UART flag is set or not.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
Check whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified UART interrupt source is enabled or not.
#define | __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified UART ISR flag, in setting the proper ICR register flag.
#define | __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
Set a specific UART request flag.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the UART one bit sample method.
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the UART one bit sample method.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control.
#define | UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001U)
Check UART Baud rate.
#define | IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART assertion time.
#define | IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART deassertion time.
#define | IS_UART_STOPBITS(__STOPBITS__)
Ensure that UART frame number of stop bits is valid.
#define | IS_UART_PARITY(__PARITY__)
Ensure that UART frame parity is valid.
#define | IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)
Ensure that UART hardware flow control is valid.
#define | IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that UART communication mode is valid.
#define | IS_UART_STATE(__STATE__)
Ensure that UART state is valid.
#define | IS_UART_OVERSAMPLING(__SAMPLING__)
Ensure that UART oversampling is valid.
#define | IS_UART_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that UART frame sampling is valid.
#define | IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__)
Ensure that Address Length detection parameter is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)
Ensure that UART auto Baud rate detection mode is valid.
#define | IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)
Ensure that UART receiver timeout setting is valid.
#define | IS_UART_LIN(__LIN__)
Ensure that UART LIN state is valid.
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__)
Ensure that UART LIN break detection length is valid.
#define | IS_UART_DMA_TX(__DMATX__)
Ensure that UART DMA TX state is valid.
#define | IS_UART_DMA_RX(__DMARX__)
Ensure that UART DMA RX state is valid.
#define | IS_UART_HALF_DUPLEX(__HDSEL__)
Ensure that UART half-duplex state is valid.
#define | IS_UART_WAKEUPMETHOD(__WAKEUP__)
Ensure that UART wake-up method is valid.
#define | IS_UART_ADVFEATURE_INIT(__INIT__)
Ensure that UART advanced features initialization is valid.
#define | IS_UART_ADVFEATURE_TXINV(__TXINV__)
Ensure that UART frame TX inversion setting is valid.
#define | IS_UART_ADVFEATURE_RXINV(__RXINV__)
Ensure that UART frame RX inversion setting is valid.
#define | IS_UART_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that UART frame data inversion setting is valid.
#define | IS_UART_ADVFEATURE_SWAP(__SWAP__)
Ensure that UART frame RX/TX pins swap setting is valid.
#define | IS_UART_OVERRUN(__OVERRUN__)
Ensure that UART frame overrun setting is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)
Ensure that UART auto Baud rate state is valid.
#define | IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that UART DMA enabling or disabling on error setting is valid.
#define | IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that UART frame MSB first setting is valid.
#define | IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__)
Ensure that UART stop mode state is valid.
#define | IS_UART_MUTE_MODE(__MUTE__)
Ensure that UART mute mode state is valid.
#define | IS_UART_WAKEUP_SELECTION(__WAKE__)
Ensure that UART wake-up selection is valid.
#define | IS_UART_DE_POLARITY(__POLARITY__)
Ensure that UART driver enable polarity is valid.
#define | IS_UART_REQUEST_PARAMETER(__PARAM__)
Ensure that UART request parameter is valid.

Enumerations

enum HAL_UART_StateTypeDef {
HAL_UART_STATE_RESET = 0x00U, HAL_UART_STATE_READY = 0x20U, HAL_UART_STATE_BUSY = 0x24U, HAL_UART_STATE_BUSY_TX = 0x21U,
HAL_UART_STATE_BUSY_RX = 0x22U, HAL_UART_STATE_BUSY_TX_RX = 0x23U, HAL_UART_STATE_TIMEOUT = 0xA0U, HAL_UART_STATE_ERROR = 0xE0U
}
HAL UART State structures definition. More...
enum UART_ClockSourceTypeDef {
UART_CLOCKSOURCE_PCLK1 = 0x00U, UART_CLOCKSOURCE_PCLK2 = 0x01U, UART_CLOCKSOURCE_HSI = 0x02U, UART_CLOCKSOURCE_SYSCLK = 0x04U,
UART_CLOCKSOURCE_LSE = 0x08U, UART_CLOCKSOURCE_UNDEFINED = 0x10U
}
UART clock sources definition. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.
HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART handle error code.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle UART Communication Timeout.
HAL_StatusTypeDef | UART_Transmit_IT (UART_HandleTypeDef *huart)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wrap up transmission in non-blocking mode.
HAL_StatusTypeDef | UART_Receive_IT (UART_HandleTypeDef *huart)
Receive an amount of data in interrupt mode.
void | UART_Wakeup_AddressConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Initialize the UART wake-up from stop mode parameters when triggered by address detection.

Detailed Description

Header file of UART HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_uart.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_uart_ex.h File Reference

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stm32f3xx_hal_uart_ex.h File Reference

Header file of UART HAL Extended module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Defines

#define | UART_WORDLENGTH_8B (0x00000000U)
#define | UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
#define | UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the UART clock source.
#define | UART_MASK_COMPUTATION(__HANDLE__)
Compute the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_UART_WORD_LENGTH(__LENGTH__)
Ensure that UART frame length is valid.

Functions

HAL_StatusTypeDef | HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.

Detailed Description

Header file of UART HAL Extended module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_uart_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_usart.h File Reference

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stm32f3xx_hal_usart.h File Reference

Header file of USART HAL module. More...

#include "stm32f3xx_hal_def.h"
#include "stm32f3xx_hal_usart_ex.h"

Go to the source code of this file.

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | USART_HandleTypeDef
USART handle Structure definition. More...

Defines

#define | HAL_USART_ERROR_NONE (0x00000000U)
#define | HAL_USART_ERROR_PE (0x00000001U)
#define | HAL_USART_ERROR_NE (0x00000002U)
#define | HAL_USART_ERROR_FE (0x00000004U)
#define | HAL_USART_ERROR_ORE (0x00000008U)
#define | HAL_USART_ERROR_DMA (0x00000010U)
#define | USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | USART_STOPBITS_1 (0x00000000U)
#define | USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define | USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define | USART_PARITY_NONE (0x00000000U)
#define | USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | USART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | USART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | USART_CLOCK_DISABLE (0x00000000U)
#define | USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
#define | USART_POLARITY_LOW (0x00000000U)
#define | USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
#define | USART_PHASE_1EDGE (0x00000000U)
#define | USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
#define | USART_LASTBIT_DISABLE (0x00000000U)
#define | USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
#define | USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)
#define | USART_FLAG_REACK (0x00400000U)
#define | USART_FLAG_TEACK (0x00200000U)
#define | USART_FLAG_BUSY (0x00010000U)
#define | USART_FLAG_CTS (0x00000400U)
#define | USART_FLAG_CTSIF (0x00000200U)
#define | USART_FLAG_LBDF (0x00000100U)
#define | USART_FLAG_TXE (0x00000080U)
#define | USART_FLAG_TC (0x00000040U)
#define | USART_FLAG_RXNE (0x00000020U)
#define | USART_FLAG_IDLE (0x00000010U)
#define | USART_FLAG_ORE (0x00000008U)
#define | USART_FLAG_NE (0x00000004U)
#define | USART_FLAG_FE (0x00000002U)
#define | USART_FLAG_PE (0x00000001U)
#define | USART_IT_PE ((uint16_t)0x0028U)
#define | USART_IT_TXE ((uint16_t)0x0727U)
#define | USART_IT_TC ((uint16_t)0x0626U)
#define | USART_IT_RXNE ((uint16_t)0x0525U)
#define | USART_IT_IDLE ((uint16_t)0x0424U)
#define | USART_IT_ERR ((uint16_t)0x0060U)
#define | USART_IT_ORE ((uint16_t)0x0300U)
#define | USART_IT_NE ((uint16_t)0x0200U)
#define | USART_IT_FE ((uint16_t)0x0100U)
#define | USART_CLEAR_PEF USART_ICR_PECF
#define | USART_CLEAR_FEF USART_ICR_FECF
#define | USART_CLEAR_NEF USART_ICR_NCF
#define | USART_CLEAR_OREF USART_ICR_ORECF
#define | USART_CLEAR_IDLEF USART_ICR_IDLECF
#define | USART_CLEAR_TCF USART_ICR_TCCF
#define | USART_CLEAR_CTSF USART_ICR_CTSCF
#define | USART_IT_MASK ((uint16_t)0x001FU)
#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
Reset USART handle state.
#define | __HAL_USART_FLUSH_DRREGISTER(__HANDLE__)
Flush the USART Data registers.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified USART flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified USART pending flag.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
Clear the USART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
Clear the USART IDLE pending flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified USART interrupt.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified USART interrupt.
#define | __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
Check whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified USART interrupt source is enabled or not.
#define | __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified USART ISR flag, in setting the proper ICR register flag.
#define | __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__))
Set a specific USART request flag.
#define | __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the USART one bit sample method.
#define | __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the USART one bit sample method.
#define | __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.
#define | IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001U)
Check USART Baud rate.
#define | IS_USART_STOPBITS(__STOPBITS__)
Ensure that USART frame number of stop bits is valid.
#define | IS_USART_PARITY(__PARITY__)
Ensure that USART frame parity is valid.
#define | IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that USART communication mode is valid.
#define | IS_USART_CLOCK(__CLOCK__)
Ensure that USART clock state is valid.
#define | IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
Ensure that USART frame polarity is valid.
#define | IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
Ensure that USART frame phase is valid.
#define | IS_USART_LASTBIT(__LASTBIT__)
Ensure that USART frame last bit clock pulse setting is valid.
#define | IS_USART_REQUEST_PARAMETER(__PARAM__)
Ensure that USART request parameter is valid.

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00U, HAL_USART_STATE_READY = 0x01U, HAL_USART_STATE_BUSY = 0x02U, HAL_USART_STATE_BUSY_TX = 0x12U,
HAL_USART_STATE_BUSY_RX = 0x22U, HAL_USART_STATE_BUSY_TX_RX = 0x32U, HAL_USART_STATE_TIMEOUT = 0x03U, HAL_USART_STATE_ERROR = 0x04U
}
HAL USART State structures definition. More...
enum USART_ClockSourceTypeDef {
USART_CLOCKSOURCE_PCLK1 = 0x00U, USART_CLOCKSOURCE_PCLK2 = 0x01U, USART_CLOCKSOURCE_HSI = 0x02U, USART_CLOCKSOURCE_SYSCLK = 0x04U,
USART_CLOCKSOURCE_LSE = 0x08U, USART_CLOCKSOURCE_UNDEFINED = 0x10U
}
USART clock sources definitions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.
HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

Header file of USART HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_usart.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_usart_ex.h File Reference

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Defines
stm32f3xx_hal_usart_ex.h File Reference

Header file of USART HAL Extended module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Defines

#define | USART_WORDLENGTH_8B (0x00000000U)
#define | USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
#define | USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the USART clock source.
#define | USART_MASK_COMPUTATION(__HANDLE__)
Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_USART_WORD_LENGTH(__LENGTH__)
Ensure that USART frame length is valid.

Detailed Description

Header file of USART HAL Extended module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_usart_ex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_wwdg.h File Reference

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stm32f3xx_hal_wwdg.h File Reference

Header file of WWDG HAL module. More...

#include "stm32f3xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | WWDG_HandleTypeDef
WWDG handle Structure definition. More...

Defines

#define | WWDG_IT_EWI WWDG_CFR_EWI
#define | WWDG_FLAG_EWIF WWDG_SR_EWIF
#define | WWDG_PRESCALER_1 0x00000000u
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | WWDG_PRESCALER_8 WWDG_CFR_WDGTB
#define | WWDG_EWI_DISABLE 0x00000000u
#define | WWDG_EWI_ENABLE WWDG_CFR_EWI
#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define | IS_WWDG_EWI_MODE(__MODE__)
#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enable the WWDG peripheral.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enable the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Check whether the selected WWDG interrupt has occurred or not.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG interrupt pending bits.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified WWDG flag is set or not.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified WWDG interrupt source is enabled or not.

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

Header file of WWDG HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_wwdg.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_adc.h File Reference

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stm32f3xx_ll_adc.h File Reference

Header file of ADC LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Data Structures

struct | LL_ADC_InitTypeDef
Structure definition of some features of ADC instance. More...
struct | LL_ADC_REG_InitTypeDef
Structure definition of some features of ADC group regular. More...
struct | LL_ADC_INJ_InitTypeDef
Structure definition of some features of ADC group injected. More...

Defines

#define | ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)
#define | ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)
#define | ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)
#define | ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
#define | ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
#define | ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
#define | ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
#define | ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
#define | ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
#define | ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
#define | ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
#define | ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
#define | ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
#define | ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
#define | ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
#define | ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
#define | ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
#define | ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
#define | ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
#define | ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
#define | ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)
#define | ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)
#define | ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)
#define | ADC_JOFR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_JOFR2_REGOFFSET ((uint32_t)0x00001000U)
#define | ADC_JOFR3_REGOFFSET ((uint32_t)0x00002000U)
#define | ADC_JOFR4_REGOFFSET ((uint32_t)0x00003000U)
#define | ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
#define | ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
#define | ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
#define | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
#define | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
#define | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
#define | ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
#define | ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t) 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
#define | ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
#define | ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
#define | ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */
#define | ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x40000000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define | ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
#define | ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)
#define | ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
#define | ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)
#define | ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
#define | ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
#define | ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
#define | ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
#define | ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
#define | ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
#define | ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
#define | ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
#define | ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
#define | ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
#define | ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
#define | ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
#define | ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
#define | ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
#define | ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
#define | ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
#define | ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
#define | ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
#define | ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
#define | ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
#define | ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
#define | ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
#define | ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
#define | ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
#define | ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
#define | ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
#define | ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
#define | ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
#define | ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
#define | ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
#define | ADC_AWD_TR1_HIGH_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_AWD_TR1_LOW_REGOFFSET ((uint32_t)0x00000001U)
#define | ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
#define | ADC_CR1_DUALMOD_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */
#define | VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define | VREFINT_CAL_VREF ((uint32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
#define | TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F37x, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F37x, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
#define | __ADC_MASK_SHIFT(__BITS__, __MASK__) (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).
#define | __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define | LL_ADC_FLAG_STRT ADC_SR_STRT
#define | LL_ADC_FLAG_EOS ADC_SR_EOC
#define | LL_ADC_FLAG_JSTRT ADC_SR_JSTRT
#define | LL_ADC_FLAG_JEOS ADC_SR_JEOC
#define | LL_ADC_FLAG_AWD1 ADC_SR_AWD
#define | LL_ADC_IT_EOS ADC_CR1_EOCIE
#define | LL_ADC_IT_JEOS ADC_CR1_JEOCIE
#define | LL_ADC_IT_AWD1 ADC_CR1_AWDIE
#define | LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
#define | LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)
#define | LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE)
#define | LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE)
#define | LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U)
#define | LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)
#define | LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN)
#define | LL_ADC_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_SEQ_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
#define | LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U)
#define | LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U)
#define | LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U)
#define | LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP)
#define | LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP)
#define | LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP)
#define | LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP)
#define | LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP)
#define | LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP)
#define | LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP)
#define | LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP)
#define | LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP)
#define | LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP)
#define | LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP)
#define | LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP)
#define | LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP)
#define | LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP)
#define | LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP)
#define | LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP)
#define | LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP)
#define | LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP)
#define | LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)
#define | LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)
#define | LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2)
#define | LL_ADC_REG_TRIG_EXT_TIM4_CH2 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)
#define | LL_ADC_REG_TRIG_EXT_TIM19_TRGO ((uint32_t)0x00000000U)
#define | LL_ADC_REG_TRIG_EXT_TIM19_CH3 (ADC_CR2_EXTSEL_0)
#define | LL_ADC_REG_TRIG_EXT_TIM19_CH4 (ADC_CR2_EXTSEL_1)
#define | LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)
#define | LL_ADC_REG_TRIG_EXT_RISING ((uint32_t)0x00000000U)
#define | LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT)
#define | LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA)
#define | LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)
#define | LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2)
#define | LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)
#define | LL_ADC_INJ_TRIG_EXT_TIM19_CH1 ((uint32_t)0x00000000U)
#define | LL_ADC_INJ_TRIG_EXT_TIM19_CH2 (ADC_CR2_JEXTSEL_0)
#define | LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)
#define | LL_ADC_INJ_TRIG_EXT_RISING ((uint32_t)0x00000000U)
#define | LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)
#define | LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO)
#define | LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN)
#define | LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)
#define | LL_ADC_SAMPLINGTIME_1CYCLE_5 ((uint32_t)0x00000000U)
#define | LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0)
#define | LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1)
#define | LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)
#define | LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2)
#define | LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)
#define | LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)
#define | LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)
#define | LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)
#define | LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN )
#define | LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN )
#define | LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN )
#define | LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET)
#define | LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET)
#define | LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 10U)
#define | LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES ((uint32_t) 2U)
#define | LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in ADC register.
#define | LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in ADC register.
#define | __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.
#define | __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.
#define | __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
#define | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)
Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.
#define | __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) ((__AWD_THRESHOLD__) << (0U))
Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) (__AWD_THRESHOLD_12_BITS__)
Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC1_COMMON)
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) LL_ADC_IsEnabled(ADC1)
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) ((uint32_t)0xFFFU)
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Functions

__STATIC_INLINE uint32_t | LL_ADC_DMA_GetRegAddr (ADC_TypeDef *ADCx, uint32_t Register)
Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE uint32_t | LL_ADC_GetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE void | LL_ADC_SetDataAlignment (ADC_TypeDef *ADCx, uint32_t DataAlignment)
Set ADC conversion data alignment.
__STATIC_INLINE uint32_t | LL_ADC_GetDataAlignment (ADC_TypeDef *ADCx)
Get ADC conversion data alignment.
__STATIC_INLINE void | LL_ADC_SetSequencersScanMode (ADC_TypeDef *ADCx, uint32_t ScanMode)
Set ADC sequencers scan mode, for all ADC groups (group regular, group injected).
__STATIC_INLINE uint32_t | LL_ADC_GetSequencersScanMode (ADC_TypeDef *ADCx)
Get ADC sequencers scan mode, for all ADC groups (group regular, group injected).
__STATIC_INLINE void | LL_ADC_REG_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group regular conversion trigger source: internal (SW start) or external from timer or external interrupt.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source: internal (SW start) or external from timer or external interrupt.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE void | LL_ADC_REG_SetContinuousMode (ADC_TypeDef *ADCx, uint32_t Continuous)
Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetContinuousMode (ADC_TypeDef *ADCx)
Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void | LL_ADC_REG_SetDMATransfer (ADC_TypeDef *ADCx, uint32_t DMATransfer)
Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetDMATransfer (ADC_TypeDef *ADCx)
Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE void | LL_ADC_INJ_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group injected conversion trigger source: internal (SW start) or external from timer or external interrupt.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source: internal (SW start) or external from timer or external interrupt.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group injected sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group injected sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE void | LL_ADC_INJ_SetTrigAuto (ADC_TypeDef *ADCx, uint32_t TrigAuto)
Set ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTrigAuto (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE void | LL_ADC_INJ_SetOffset (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
Set ADC group injected offset.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetOffset (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected offset.
__STATIC_INLINE void | LL_ADC_SetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel)
Get sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE void | LL_ADC_SetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
Set ADC analog watchdog monitored channels: a single channel or all channels, on ADC groups regular and-or injected.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDMonitChannels (ADC_TypeDef *ADCx)
Get ADC analog watchdog monitored channel.
__STATIC_INLINE void | LL_ADC_SetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
Get ADC analog watchdog threshold value of threshold high or threshold low.
__STATIC_INLINE void | LL_ADC_Enable (ADC_TypeDef *ADCx)
Enable the selected ADC instance.
__STATIC_INLINE void | LL_ADC_Disable (ADC_TypeDef *ADCx)
Disable the selected ADC instance.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance enable state.
__STATIC_INLINE void | LL_ADC_StartCalibration (ADC_TypeDef *ADCx)
Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_IsCalibrationOnGoing (ADC_TypeDef *ADCx)
Get ADC calibration state.
__STATIC_INLINE void | LL_ADC_REG_StartConversion (ADC_TypeDef *ADCx)
Start ADC group regular conversion.
__STATIC_INLINE void | LL_ADC_REG_StopConversionExtTrig (ADC_TypeDef *ADCx)
Stop ADC group regular conversion from external trigger.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadConversionData32 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData12 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE void | LL_ADC_INJ_StartConversion (ADC_TypeDef *ADCx)
Start ADC group injected conversion.
__STATIC_INLINE void | LL_ADC_INJ_StopConversionExtTrig (ADC_TypeDef *ADCx)
Stop ADC group injected conversion from external trigger.
__STATIC_INLINE uint32_t | LL_ADC_INJ_ReadConversionData32 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData12 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOS (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOS (ADC_TypeDef *ADCx)
Get flag ADC group injected end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD1 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOS (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOS (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD1 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_EnableIT_EOS (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOS (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD1 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_DisableIT_EOS (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOS (ADC_TypeDef *ADCx)
Disable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD1 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 1.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD1 (ADC_TypeDef *ADCx)
Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).
ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *ADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Detailed Description

Header file of ADC LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_adc.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_bus.h File Reference

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Defines | Functions
stm32f3xx_ll_bus.h File Reference

Header file of BUS LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Defines

#define | LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
#define | LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
#define | LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
#define | LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
#define | LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
#define | LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
#define | LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
#define | LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
#define | LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
#define | LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
#define | LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
#define | LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
#define | LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
#define | LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
#define | LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
#define | LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
#define | LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
#define | LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
#define | LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
#define | LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
#define | LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
#define | LL_APB1_GRP1_PERIPH_TIM18 RCC_APB1ENR_TIM18EN
#define | LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
#define | LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
#define | LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
#define | LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
#define | LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
#define | LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
#define | LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
#define | LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
#define | LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN
#define | LL_APB1_GRP1_PERIPH_DAC2 RCC_APB1ENR_DAC2EN
#define | LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
#define | LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DAC1EN
#define | LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
#define | LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
#define | LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
#define | LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
#define | LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
#define | LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
#define | LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
#define | LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
#define | LL_APB2_GRP1_PERIPH_TIM19 RCC_APB2ENR_TIM19EN
#define | LL_APB2_GRP1_PERIPH_SDADC1 RCC_APB2ENR_SDADC1EN
#define | LL_APB2_GRP1_PERIPH_SDADC2 RCC_APB2ENR_SDADC2EN
#define | LL_APB2_GRP1_PERIPH_SDADC3 RCC_APB2ENR_SDADC3EN

Functions

__STATIC_INLINE void | LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
Enable AHB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
Disable AHB1 peripherals clock.
__STATIC_INLINE void | LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
Force AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP1_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_EnableClock (uint32_t Periphs)
Enable APB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClock (uint32_t Periphs)
Disable APB2 peripherals clock.
__STATIC_INLINE void | LL_APB2_GRP1_ForceReset (uint32_t Periphs)
Force APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
Release APB2 peripherals reset.

Detailed Description

Header file of BUS LL module.

Author:
MCD Application Team
                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
        (++) AHB & APB peripherals, 1 dummy read is necessary

    [..]
      Workarounds:
      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_bus.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_comp.h File Reference

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Data Structures | Defines | Functions
stm32f3xx_ll_comp.h File Reference

Header file of COMP LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Data Structures

struct | LL_COMP_InitTypeDef
Structure definition of some features of COMP instance. More...

Defines

#define | COMPX_BASE COMP_BASE
#define | COMPX (COMP1 - COMP2)
#define | LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(COMP_CSR_COMP1OUT) */
#define | __COMP_IS_INSTANCE_ODD(__COMP_INSTANCE__) ((~(((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) >> 1U)) & 0x00000001)
Driver macro reserved for internal use: if COMP instance selected is odd (COMP1, COMP3, ...), return value '1', else return '0'.
#define | __COMP_IS_INSTANCE_EVEN(__COMP_INSTANCE__) (((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) >> 1U)
Driver macro reserved for internal use: if COMP instance selected is even (COMP2, COMP4, ...), return value '1', else return '0'.
#define | __COMP_BITOFFSET_INSTANCE(__COMP_INSTANCE__) (((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) << 3U)
Driver macro reserved for internal use: from COMP instance selected, set offset of bits into COMP register.
#define | LL_COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000U)
#define | LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WNDWEN)
#define | LL_COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000U)
#define | LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_COMP1MODE_0)
#define | LL_COMP_POWERMODE_LOWPOWER (COMP_CSR_COMP1MODE_1)
#define | LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_COMP1MODE_1 | COMP_CSR_COMP1MODE_0)
#define | LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U)
#define | LL_COMP_INPUT_PLUS_DAC1_CH1 (COMP_CSR_COMP1SW1)
#define | LL_COMP_INPUT_MINUS_1_4VREFINT ((uint32_t)0x00000000U)
#define | LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_COMP1INSEL_0)
#define | LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_COMP1INSEL_1 )
#define | LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0)
#define | LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_COMP1INSEL_2 )
#define | LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_0)
#define | LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 )
#define | LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0)
#define | LL_COMP_INPUT_MINUS_IO3 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_0)
#define | LL_COMP_INPUT_MINUS_IO4 (COMP_CSR_COMP1INSEL_2 )
#define | LL_COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0)
#define | LL_COMP_HYSTERESIS_NONE ((uint32_t)0x00000000U)
#define | LL_COMP_HYSTERESIS_LOW ( COMP_CSR_COMP1HYST_0)
#define | LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_COMP1HYST_1 )
#define | LL_COMP_HYSTERESIS_HIGH (COMP_CSR_COMP1HYST_1 | COMP_CSR_COMP1HYST_0)
#define | LL_COMP_OUTPUT_NONE ((uint32_t)0x00000000U)
#define | LL_COMP_OUTPUT_TIM2_IC4 (COMP_CSR_COMP1OUTSEL_2)
#define | LL_COMP_OUTPUT_TIM2_OCCLR (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_0)
#define | LL_COMP_OUTPUT_TIM15_BKIN_COMP1 (COMP_CSR_COMP1OUTSEL_0)
#define | LL_COMP_OUTPUT_TIM3_IC1_COMP1 (COMP_CSR_COMP1OUTSEL_1)
#define | LL_COMP_OUTPUT_TIM3_OCCLR_COMP1 (COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0)
#define | LL_COMP_OUTPUT_TIM5_IC4_COMP1 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1)
#define | LL_COMP_OUTPUT_TIM5_OCCLR_COMP1 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0)
#define | LL_COMP_OUTPUT_TIM16_BKIN_COMP2 (COMP_CSR_COMP1OUTSEL_0)
#define | LL_COMP_OUTPUT_TIM4_IC1_COMP2 (COMP_CSR_COMP1OUTSEL_1)
#define | LL_COMP_OUTPUT_TIM4_OCCLR_COMP2 (COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0)
#define | LL_COMP_OUTPUT_TIM3_IC1_COMP2 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1)
#define | LL_COMP_OUTPUT_TIM3_OCCLR_COMP2 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0)
#define | LL_COMP_OUTPUT_TIM15_BKIN LL_COMP_OUTPUT_TIM15_BKIN_COMP1
#define | LL_COMP_OUTPUT_TIM16_BKIN LL_COMP_OUTPUT_TIM16_BKIN_COMP2
#define | LL_COMP_OUTPUT_TIM4_IC1 LL_COMP_OUTPUT_TIM4_IC1_COMP2
#define | LL_COMP_OUTPUT_TIM4_OCCLR LL_COMP_OUTPUT_TIM4_OCCLR_COMP2
#define | LL_COMP_OUTPUT_TIM5_IC4 LL_COMP_OUTPUT_TIM5_IC1_COMP1
#define | LL_COMP_OUTPUT_TIM5_OCCLR LL_COMP_OUTPUT_TIM5_OCCLR_COMP1
#define | LL_COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000U)
#define | LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_COMP1POL)
#define | LL_COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000U)
#define | LL_COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001U)
#define | LL_COMP_DELAY_STARTUP_US ((uint32_t) 60U)
#define | LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)
#define | LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in COMP register.
#define | LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in COMP register.
#define | __LL_COMP_COMMON_INSTANCE(__COMPx__) (COMP12_COMMON)
Helper macro to select the COMP common instance to which is belonging the selected COMP instance.

Functions

__STATIC_INLINE void | LL_COMP_SetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
Set window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
__STATIC_INLINE uint32_t | LL_COMP_GetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON)
Get window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
__STATIC_INLINE void | LL_COMP_SetPowerMode (COMP_TypeDef *COMPx, uint32_t PowerMode)
Set comparator instance operating mode to adjust power and speed.
__STATIC_INLINE uint32_t | LL_COMP_GetPowerMode (COMP_TypeDef *COMPx)
Get comparator instance operating mode to adjust power and speed.
__STATIC_INLINE void | LL_COMP_ConfigInputs (COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
Set comparator inputs minus (inverting) and plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputPlus (COMP_TypeDef *COMPx, uint32_t InputPlus)
Set comparator input plus (non-inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputPlus (COMP_TypeDef *COMPx)
Get comparator input plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputMinus (COMP_TypeDef *COMPx, uint32_t InputMinus)
Set comparator input minus (inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputMinus (COMP_TypeDef *COMPx)
Get comparator input minus (inverting).
__STATIC_INLINE void | LL_COMP_SetInputHysteresis (COMP_TypeDef *COMPx, uint32_t InputHysteresis)
Set comparator instance hysteresis mode of the input minus (inverting input).
__STATIC_INLINE uint32_t | LL_COMP_GetInputHysteresis (COMP_TypeDef *COMPx)
Get comparator instance hysteresis mode of the minus (inverting) input.
__STATIC_INLINE void | LL_COMP_SetOutputSelection (COMP_TypeDef *COMPx, uint32_t OutputSelection)
Set comparator output selection.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputSelection (COMP_TypeDef *COMPx)
Get comparator output selection.
__STATIC_INLINE void | LL_COMP_SetOutputPolarity (COMP_TypeDef *COMPx, uint32_t OutputPolarity)
Set comparator instance output polarity.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputPolarity (COMP_TypeDef *COMPx)
Get comparator instance output polarity.
__STATIC_INLINE void | LL_COMP_Enable (COMP_TypeDef *COMPx)
Enable comparator instance.
__STATIC_INLINE void | LL_COMP_Disable (COMP_TypeDef *COMPx)
Disable comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsEnabled (COMP_TypeDef *COMPx)
Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)
__STATIC_INLINE void | LL_COMP_Lock (COMP_TypeDef *COMPx)
Lock comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsLocked (COMP_TypeDef *COMPx)
Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).
__STATIC_INLINE uint32_t | LL_COMP_ReadOutputLevel (COMP_TypeDef *COMPx)
Read comparator instance output level.
ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Detailed Description

Header file of COMP LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_comp.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_cortex.h File Reference

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Defines | Functions
stm32f3xx_ll_cortex.h File Reference

Header file of CORTEX LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Defines

#define | LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk
#define | LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk
#define | LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk
#define | LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U
#define | LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define | LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
#define | LL_MPU_REGION_NUMBER0 0x00U
#define | LL_MPU_REGION_NUMBER1 0x01U
#define | LL_MPU_REGION_NUMBER2 0x02U
#define | LL_MPU_REGION_NUMBER3 0x03U
#define | LL_MPU_REGION_NUMBER4 0x04U
#define | LL_MPU_REGION_NUMBER5 0x05U
#define | LL_MPU_REGION_NUMBER6 0x06U
#define | LL_MPU_REGION_NUMBER7 0x07U
#define | LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos)
#define | LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos)
#define | LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U
#define | LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk
#define | LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk
#define | LL_MPU_ACCESS_NOT_SHAREABLE 0x00U
#define | LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk
#define | LL_MPU_ACCESS_NOT_CACHEABLE 0x00U
#define | LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk
#define | LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U

Functions

__STATIC_INLINE uint32_t | LL_SYSTICK_IsActiveCounterFlag (void)
This function checks if the Systick counter flag is active or not.
__STATIC_INLINE void | LL_SYSTICK_SetClkSource (uint32_t Source)
Configures the SysTick clock source.
__STATIC_INLINE uint32_t | LL_SYSTICK_GetClkSource (void)
Get the SysTick clock source.
__STATIC_INLINE void | LL_SYSTICK_EnableIT (void)
Enable SysTick exception request.
__STATIC_INLINE void | LL_SYSTICK_DisableIT (void)
Disable SysTick exception request.
__STATIC_INLINE uint32_t | LL_SYSTICK_IsEnabledIT (void)
Checks if the SYSTICK interrupt is enabled or disabled.
__STATIC_INLINE void | LL_LPM_EnableSleep (void)
Processor uses sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableDeepSleep (void)
Processor uses deep sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableSleepOnExit (void)
Configures sleep-on-exit when returning from Handler mode to Thread mode.
__STATIC_INLINE void | LL_LPM_DisableSleepOnExit (void)
Do not sleep when returning to Thread mode.
__STATIC_INLINE void | LL_LPM_EnableEventOnPend (void)
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
__STATIC_INLINE void | LL_LPM_DisableEventOnPend (void)
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
__STATIC_INLINE void | LL_HANDLER_EnableFault (uint32_t Fault)
Enable a fault in System handler control register (SHCSR)
__STATIC_INLINE void | LL_HANDLER_DisableFault (uint32_t Fault)
Disable a fault in System handler control register (SHCSR)
__STATIC_INLINE uint32_t | LL_CPUID_GetImplementer (void)
Get Implementer code.
__STATIC_INLINE uint32_t | LL_CPUID_GetVariant (void)
Get Variant number (The r value in the rnpn product revision identifier)
__STATIC_INLINE uint32_t | LL_CPUID_GetConstant (void)
Get Constant number.
__STATIC_INLINE uint32_t | LL_CPUID_GetParNo (void)
Get Part number.
__STATIC_INLINE uint32_t | LL_CPUID_GetRevision (void)
Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
__STATIC_INLINE void | LL_MPU_Enable (uint32_t Options)
Enable MPU with input options.
__STATIC_INLINE void | LL_MPU_Disable (void)
Disable MPU.
__STATIC_INLINE uint32_t | LL_MPU_IsEnabled (void)
Check if MPU is enabled or not.
__STATIC_INLINE void | LL_MPU_EnableRegion (uint32_t Region)
Enable a MPU region.
__STATIC_INLINE void | LL_MPU_ConfigRegion (uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
Configure and enable a region.
__STATIC_INLINE void | LL_MPU_DisableRegion (uint32_t Region)
Disable a region.

Detailed Description

Header file of CORTEX LL module.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL CORTEX driver contains a set of generic APIs that can be
    used by user:
      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
          functions
      (+) Low power mode configuration (SCB register of Cortex-MCU)
      (+) MPU API to configure and enable regions
          (MPU services provided only on some devices)
      (+) API to access to MCU info (CPUID register)
      (+) API to enable fault handler (SHCSR accesses)
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_cortex.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_crc.h File Reference

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stm32f3xx_ll_crc.h File Reference

Header file of CRC LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Defines

#define | LL_CRC_POLYLENGTH_32B 0x00000000U
#define | LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)
#define | LL_CRC_INDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0
#define | LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1
#define | LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)
#define | LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT
#define | LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U
#define | LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
#define | LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in CRC register.
#define | LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRC register.

Functions

__STATIC_INLINE void | LL_CRC_ResetCRCCalculationUnit (CRC_TypeDef *CRCx)
Reset the CRC calculation unit.
__STATIC_INLINE void | LL_CRC_SetPolynomialSize (CRC_TypeDef *CRCx, uint32_t PolySize)
Configure size of the polynomial.
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialSize (CRC_TypeDef *CRCx)
Return size of the polynomial.
__STATIC_INLINE void | LL_CRC_SetInputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the input data.
__STATIC_INLINE uint32_t | LL_CRC_GetInputDataReverseMode (CRC_TypeDef *CRCx)
Return type of reversal for input data bit order.
__STATIC_INLINE void | LL_CRC_SetOutputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE uint32_t | LL_CRC_GetOutputDataReverseMode (CRC_TypeDef *CRCx)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE void | LL_CRC_SetInitialData (CRC_TypeDef *CRCx, uint32_t InitCrc)
Initialize the Programmable initial CRC value.
__STATIC_INLINE uint32_t | LL_CRC_GetInitialData (CRC_TypeDef *CRCx)
Return current Initial CRC value.
__STATIC_INLINE void | LL_CRC_SetPolynomialCoef (CRC_TypeDef *CRCx, uint32_t PolynomCoef)
Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialCoef (CRC_TypeDef *CRCx)
Return current Programmable polynomial value.
__STATIC_INLINE void | LL_CRC_FeedData32 (CRC_TypeDef *CRCx, uint32_t InData)
Write given 32-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData16 (CRC_TypeDef *CRCx, uint16_t InData)
Write given 16-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData8 (CRC_TypeDef *CRCx, uint8_t InData)
Write given 8-bit data to the CRC calculator.
__STATIC_INLINE uint32_t | LL_CRC_ReadData32 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint16_t | LL_CRC_ReadData16 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData8 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData7 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint32_t | LL_CRC_Read_IDR (CRC_TypeDef *CRCx)
Return data stored in the Independent Data(IDR) register.
__STATIC_INLINE void | LL_CRC_Write_IDR (CRC_TypeDef *CRCx, uint32_t InData)
Store data in the Independent Data(IDR) register.
ErrorStatus | LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Detailed Description

Header file of CRC LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_crc.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_dac.h File Reference

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Data Structures | Defines | Functions
stm32f3xx_ll_dac.h File Reference

Header file of DAC LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Data Structures

struct | LL_DAC_InitTypeDef
Structure definition of some features of DAC instance. More...

Defines

#define | DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
#define | DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
#define | DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
#define | DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
#define | DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
#define | DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
#define | DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
#define | DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
#define | DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
#define | DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
#define | DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
#define | DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
#define | DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
#define | DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
#define | DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
#define | DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
#define | DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
#define | DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
#define | DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
#define | DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
#define | DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
#define | DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
#define | DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
#define | __DAC_MASK_SHIFT(__BITS__, __MASK__) (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).
#define | __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define | LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define | LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
#define | LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)
#define | LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)
#define | LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1)
#define | LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2)
#define | LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U
#define | LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 )
#define | LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM18_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO)
#define | LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
#define | LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U
#define | LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0)
#define | LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1)
#define | LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U
#define | LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U
#define | LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1)
#define | LL_DAC_RESOLUTION_12B 0x00000000U
#define | LL_DAC_RESOLUTION_8B 0x00000002U
#define | LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK
#define | LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK
#define | LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK
#define | LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U
#define | LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U
#define | LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DAC register.
#define | LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DAC register.
#define | __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
Helper macro to get DAC channel number in decimal format from literals LL_DAC_CHANNEL_x.
#define | __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x from number in decimal format.
#define | __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
Helper macro to define the DAC conversion data full-scale digital value corresponding to the selected DAC resolution.
#define | __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__)
Helper macro to calculate the DAC conversion data (unit: digital value) corresponding to a voltage (unit: mVolt).

Functions

__STATIC_INLINE void | LL_DAC_SetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
Set the conversion trigger source for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the conversion trigger source for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
Set the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE uint32_t | LL_DAC_GetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE void | LL_DAC_SetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE void | LL_DAC_SetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
Set the output buffer for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output buffer state for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_EnableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC DMA transfer request of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC DMA transfer request of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsDMAReqEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC DMA transfer request state of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_DMA_GetRegAddr (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
Function to help to configure DMA transfer to DAC: retrieve the DAC register address from DAC instance and a list of DAC registers intended to be used (most commonly) with DMA transfer.
__STATIC_INLINE void | LL_DAC_Enable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC selected channel.
__STATIC_INLINE void | LL_DAC_Disable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC enable state of the selected channel.
__STATIC_INLINE void | LL_DAC_EnableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC trigger of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC trigger of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsTriggerEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC trigger state of the selected channel.
__STATIC_INLINE void | LL_DAC_TrigSWConversion (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Trig DAC conversion by software for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12LeftAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData8RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertDualData12RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData12LeftAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData8RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE uint32_t | LL_DAC_RetrieveOutputData (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Retrieve output data currently generated for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR1 (DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR2 (DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 2.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR1 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 1.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR2 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 2.
__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR1 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR2 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR1 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR2 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR1 (DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR2 (DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 2.
ErrorStatus | LL_DAC_DeInit (DAC_TypeDef *DACx)
De-initialize registers of the selected DAC instance to their default reset values.
ErrorStatus | LL_DAC_Init (DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
Initialize some features of DAC instance.
void | LL_DAC_StructInit (LL_DAC_InitTypeDef *DAC_InitStruct)
Set each LL_DAC_InitTypeDef field to default value.

Detailed Description

Header file of DAC LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_dac.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_dma.h File Reference

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stm32f3xx_ll_dma.h File Reference

Header file of DMA LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Data Structures

struct | LL_DMA_InitTypeDef

Defines

#define | LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1
#define | LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1
#define | LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1
#define | LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1
#define | LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2
#define | LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2
#define | LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2
#define | LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2
#define | LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3
#define | LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3
#define | LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3
#define | LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3
#define | LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4
#define | LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4
#define | LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4
#define | LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4
#define | LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5
#define | LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5
#define | LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5
#define | LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5
#define | LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6
#define | LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6
#define | LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6
#define | LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6
#define | LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7
#define | LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7
#define | LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7
#define | LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7
#define | LL_DMA_ISR_GIF1 DMA_ISR_GIF1
#define | LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1
#define | LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1
#define | LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1
#define | LL_DMA_ISR_GIF2 DMA_ISR_GIF2
#define | LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2
#define | LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2
#define | LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2
#define | LL_DMA_ISR_GIF3 DMA_ISR_GIF3
#define | LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3
#define | LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3
#define | LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3
#define | LL_DMA_ISR_GIF4 DMA_ISR_GIF4
#define | LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4
#define | LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4
#define | LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4
#define | LL_DMA_ISR_GIF5 DMA_ISR_GIF5
#define | LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5
#define | LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5
#define | LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5
#define | LL_DMA_ISR_GIF6 DMA_ISR_GIF6
#define | LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6
#define | LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6
#define | LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6
#define | LL_DMA_ISR_GIF7 DMA_ISR_GIF7
#define | LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7
#define | LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7
#define | LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7
#define | LL_DMA_CCR_TCIE DMA_CCR_TCIE
#define | LL_DMA_CCR_HTIE DMA_CCR_HTIE
#define | LL_DMA_CCR_TEIE DMA_CCR_TEIE
#define | LL_DMA_CHANNEL_1 0x00000001U
#define | LL_DMA_CHANNEL_2 0x00000002U
#define | LL_DMA_CHANNEL_3 0x00000003U
#define | LL_DMA_CHANNEL_4 0x00000004U
#define | LL_DMA_CHANNEL_5 0x00000005U
#define | LL_DMA_CHANNEL_6 0x00000006U
#define | LL_DMA_CHANNEL_7 0x00000007U
#define | LL_DMA_CHANNEL_ALL 0xFFFF0000U
#define | LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
#define | LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR
#define | LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM
#define | LL_DMA_MODE_NORMAL 0x00000000U
#define | LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC
#define | LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC
#define | LL_DMA_PERIPH_NOINCREMENT 0x00000000U
#define | LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC
#define | LL_DMA_MEMORY_NOINCREMENT 0x00000000U
#define | LL_DMA_PDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
#define | LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1
#define | LL_DMA_MDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
#define | LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1
#define | LL_DMA_PRIORITY_LOW 0x00000000U
#define | LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0
#define | LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1
#define | LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL
#define | LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMA register.
#define | LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMA register.
#define | __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
Convert DMAx_Channely into DMAx.
#define | __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)
Convert DMAx_Channely into LL_DMA_CHANNEL_y.
#define | __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)
Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Functions

__STATIC_INLINE void | LL_DMA_EnableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Enable DMA channel.
__STATIC_INLINE void | LL_DMA_DisableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Disable DMA channel.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Check if DMA channel is enabled or disabled.
__STATIC_INLINE void | LL_DMA_ConfigTransfer (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
Configure all parameters link to DMA transfer.
__STATIC_INLINE void | LL_DMA_SetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
Set Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE uint32_t | LL_DMA_GetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel)
Get Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE void | LL_DMA_SetMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
Set DMA mode circular or normal.
__STATIC_INLINE uint32_t | LL_DMA_GetMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA mode circular or normal.
__STATIC_INLINE void | LL_DMA_SetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
Set Peripheral increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral increment mode.
__STATIC_INLINE void | LL_DMA_SetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
Set Memory increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory increment mode.
__STATIC_INLINE void | LL_DMA_SetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
Set Peripheral size.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral size.
__STATIC_INLINE void | LL_DMA_SetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
Set Memory size.
__STATIC_INLINE uint32_t | LL_DMA_GetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory size.
__STATIC_INLINE void | LL_DMA_SetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
Set Channel priority level.
__STATIC_INLINE uint32_t | LL_DMA_GetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel)
Get Channel priority level.
__STATIC_INLINE void | LL_DMA_SetDataLength (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
Set Number of data to transfer.
__STATIC_INLINE uint32_t | LL_DMA_GetDataLength (DMA_TypeDef *DMAx, uint32_t Channel)
Get Number of data to transfer.
__STATIC_INLINE void | LL_DMA_ConfigAddresses (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_DMA_SetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory address.
__STATIC_INLINE void | LL_DMA_SetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
Set the Peripheral address.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory address.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral address.
__STATIC_INLINE void | LL_DMA_SetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Source address.
__STATIC_INLINE void | LL_DMA_SetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Source address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI1 (DMA_TypeDef *DMAx)
Get Channel 1 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI2 (DMA_TypeDef *DMAx)
Get Channel 2 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI3 (DMA_TypeDef *DMAx)
Get Channel 3 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI4 (DMA_TypeDef *DMAx)
Get Channel 4 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI5 (DMA_TypeDef *DMAx)
Get Channel 5 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI6 (DMA_TypeDef *DMAx)
Get Channel 6 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI7 (DMA_TypeDef *DMAx)
Get Channel 7 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT1 (DMA_TypeDef *DMAx)
Get Channel 1 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT2 (DMA_TypeDef *DMAx)
Get Channel 2 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT3 (DMA_TypeDef *DMAx)
Get Channel 3 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT4 (DMA_TypeDef *DMAx)
Get Channel 4 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT5 (DMA_TypeDef *DMAx)
Get Channel 5 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT6 (DMA_TypeDef *DMAx)
Get Channel 6 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT7 (DMA_TypeDef *DMAx)
Get Channel 7 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI1 (DMA_TypeDef *DMAx)
Clear Channel 1 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI2 (DMA_TypeDef *DMAx)
Clear Channel 2 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI3 (DMA_TypeDef *DMAx)
Clear Channel 3 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI4 (DMA_TypeDef *DMAx)
Clear Channel 4 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI5 (DMA_TypeDef *DMAx)
Clear Channel 5 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI6 (DMA_TypeDef *DMAx)
Clear Channel 6 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI7 (DMA_TypeDef *DMAx)
Clear Channel 7 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT1 (DMA_TypeDef *DMAx)
Clear Channel 1 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT2 (DMA_TypeDef *DMAx)
Clear Channel 2 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT3 (DMA_TypeDef *DMAx)
Clear Channel 3 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT4 (DMA_TypeDef *DMAx)
Clear Channel 4 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT5 (DMA_TypeDef *DMAx)
Clear Channel 5 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT6 (DMA_TypeDef *DMAx)
Clear Channel 6 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT7 (DMA_TypeDef *DMAx)
Clear Channel 7 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer error flag.
__STATIC_INLINE void | LL_DMA_EnableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer error interrupt.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer complete Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Half transfer Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer error Interrupt is enabled.
uint32_t | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
uint32_t | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Variables

static const uint8_t | CHANNEL_OFFSET_TAB []

Detailed Description

Header file of DMA LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_dma.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_exti.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32F3xx_HAL_Driver
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Data Structures | Defines | Functions
stm32f3xx_ll_exti.h File Reference

Header file of EXTI LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Data Structures

struct | LL_EXTI_InitTypeDef

Defines

#define | LL_EXTI_LINE_0 EXTI_IMR_IM0
#define | LL_EXTI_LINE_1 EXTI_IMR_IM1
#define | LL_EXTI_LINE_2 EXTI_IMR_IM2
#define | LL_EXTI_LINE_3 EXTI_IMR_IM3
#define | LL_EXTI_LINE_4 EXTI_IMR_IM4
#define | LL_EXTI_LINE_5 EXTI_IMR_IM5
#define | LL_EXTI_LINE_6 EXTI_IMR_IM6
#define | LL_EXTI_LINE_7 EXTI_IMR_IM7
#define | LL_EXTI_LINE_8 EXTI_IMR_IM8
#define | LL_EXTI_LINE_9 EXTI_IMR_IM9
#define | LL_EXTI_LINE_10 EXTI_IMR_IM10
#define | LL_EXTI_LINE_11 EXTI_IMR_IM11
#define | LL_EXTI_LINE_12 EXTI_IMR_IM12
#define | LL_EXTI_LINE_13 EXTI_IMR_IM13
#define | LL_EXTI_LINE_14 EXTI_IMR_IM14
#define | LL_EXTI_LINE_15 EXTI_IMR_IM15
#define | LL_EXTI_LINE_16 EXTI_IMR_IM16
#define | LL_EXTI_LINE_17 EXTI_IMR_IM17
#define | LL_EXTI_LINE_18 EXTI_IMR_IM18
#define | LL_EXTI_LINE_19 EXTI_IMR_IM19
#define | LL_EXTI_LINE_20 EXTI_IMR_IM20
#define | LL_EXTI_LINE_21 EXTI_IMR_IM21
#define | LL_EXTI_LINE_22 EXTI_IMR_IM22
#define | LL_EXTI_LINE_23 EXTI_IMR_IM23
#define | LL_EXTI_LINE_24 EXTI_IMR_IM24
#define | LL_EXTI_LINE_25 EXTI_IMR_IM25
#define | LL_EXTI_LINE_26 EXTI_IMR_IM26
#define | LL_EXTI_LINE_27 EXTI_IMR_IM27
#define | LL_EXTI_LINE_28 EXTI_IMR_IM28
#define | LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM
#define | LL_EXTI_LINE_ALL (0xFFFFFFFFU)
#define | LL_EXTI_LINE_NONE (0x00000000U)
#define | LL_EXTI_MODE_IT ((uint8_t)0x00U)
#define | LL_EXTI_MODE_EVENT ((uint8_t)0x01U)
#define | LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)
#define | LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)
#define | LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)
#define | LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
Write a value in EXTI register.
#define | LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
Read a value in EXTI register.

Functions

__STATIC_INLINE void | LL_EXTI_EnableIT_0_31 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableIT_0_31 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableEvent_0_31 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableEvent_0_31 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_0_31 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_0_31 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_0_31 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_0_31 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_0_31 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_ClearFlag_0_31 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 0 to 31.
uint32_t | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
uint32_t | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Detailed Description

Header file of EXTI LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_exti.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_gpio.h File Reference

  • File List
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  • STM32F3xx_HAL_Driver
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Data Structures | Defines | Functions
stm32f3xx_ll_gpio.h File Reference

Header file of GPIO LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Data Structures

struct | LL_GPIO_InitTypeDef
LL GPIO Init Structure definition. More...

Defines

#define | LL_GPIO_PIN_0 GPIO_BSRR_BS_0
#define | LL_GPIO_PIN_1 GPIO_BSRR_BS_1
#define | LL_GPIO_PIN_2 GPIO_BSRR_BS_2
#define | LL_GPIO_PIN_3 GPIO_BSRR_BS_3
#define | LL_GPIO_PIN_4 GPIO_BSRR_BS_4
#define | LL_GPIO_PIN_5 GPIO_BSRR_BS_5
#define | LL_GPIO_PIN_6 GPIO_BSRR_BS_6
#define | LL_GPIO_PIN_7 GPIO_BSRR_BS_7
#define | LL_GPIO_PIN_8 GPIO_BSRR_BS_8
#define | LL_GPIO_PIN_9 GPIO_BSRR_BS_9
#define | LL_GPIO_PIN_10 GPIO_BSRR_BS_10
#define | LL_GPIO_PIN_11 GPIO_BSRR_BS_11
#define | LL_GPIO_PIN_12 GPIO_BSRR_BS_12
#define | LL_GPIO_PIN_13 GPIO_BSRR_BS_13
#define | LL_GPIO_PIN_14 GPIO_BSRR_BS_14
#define | LL_GPIO_PIN_15 GPIO_BSRR_BS_15
#define | LL_GPIO_PIN_ALL
#define | LL_GPIO_MODE_INPUT (0x00000000U)
#define | LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0
#define | LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1
#define | LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0
#define | LL_GPIO_OUTPUT_PUSHPULL (0x00000000U)
#define | LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0
#define | LL_GPIO_SPEED_FREQ_LOW (0x00000000U)
#define | LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0
#define | LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0
#define | LL_GPIO_PULL_NO (0x00000000U)
#define | LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0
#define | LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1
#define | LL_GPIO_AF_0 (0x0000000U)
#define | LL_GPIO_AF_1 (0x0000001U)
#define | LL_GPIO_AF_2 (0x0000002U)
#define | LL_GPIO_AF_3 (0x0000003U)
#define | LL_GPIO_AF_4 (0x0000004U)
#define | LL_GPIO_AF_5 (0x0000005U)
#define | LL_GPIO_AF_6 (0x0000006U)
#define | LL_GPIO_AF_7 (0x0000007U)
#define | LL_GPIO_AF_8 (0x0000008U)
#define | LL_GPIO_AF_9 (0x0000009U)
#define | LL_GPIO_AF_10 (0x000000AU)
#define | LL_GPIO_AF_11 (0x000000BU)
#define | LL_GPIO_AF_12 (0x000000CU)
#define | LL_GPIO_AF_13 (0x000000DU)
#define | LL_GPIO_AF_14 (0x000000EU)
#define | LL_GPIO_AF_15 (0x000000FU)
#define | LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in GPIO register.
#define | LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in GPIO register.

Functions

__STATIC_INLINE void | LL_GPIO_SetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
Configure gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
Configure gpio output type for several pins on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio output type for several pins on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
Configure gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Lock configuration of several pins for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsPinLocked (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return 1 if all pins passed as parameter, of a dedicated port, are locked.
__STATIC_INLINE uint32_t | LL_GPIO_IsAnyPinLocked (GPIO_TypeDef *GPIOx)
Return 1 if one of the pin of a dedicated port is locked.
__STATIC_INLINE uint32_t | LL_GPIO_ReadInputPort (GPIO_TypeDef *GPIOx)
Return full input data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsInputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_WriteOutputPort (GPIO_TypeDef *GPIOx, uint32_t PortValue)
Write output data register for the port.
__STATIC_INLINE uint32_t | LL_GPIO_ReadOutputPort (GPIO_TypeDef *GPIOx)
Return full output data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsOutputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_SetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to high level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_ResetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to low level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Toggle data value for several pin of dedicated port.
ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Detailed Description

Header file of GPIO LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_gpio.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_i2c.h File Reference

  • File List
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  • Drivers
  • STM32F3xx_HAL_Driver
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Data Structures | Defines | Functions
stm32f3xx_ll_i2c.h File Reference

Header file of I2C LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Data Structures

struct | LL_I2C_InitTypeDef

Defines

#define | LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF
#define | LL_I2C_ICR_NACKCF I2C_ICR_NACKCF
#define | LL_I2C_ICR_STOPCF I2C_ICR_STOPCF
#define | LL_I2C_ICR_BERRCF I2C_ICR_BERRCF
#define | LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF
#define | LL_I2C_ICR_OVRCF I2C_ICR_OVRCF
#define | LL_I2C_ICR_PECCF I2C_ICR_PECCF
#define | LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF
#define | LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF
#define | LL_I2C_ISR_TXE I2C_ISR_TXE
#define | LL_I2C_ISR_TXIS I2C_ISR_TXIS
#define | LL_I2C_ISR_RXNE I2C_ISR_RXNE
#define | LL_I2C_ISR_ADDR I2C_ISR_ADDR
#define | LL_I2C_ISR_NACKF I2C_ISR_NACKF
#define | LL_I2C_ISR_STOPF I2C_ISR_STOPF
#define | LL_I2C_ISR_TC I2C_ISR_TC
#define | LL_I2C_ISR_TCR I2C_ISR_TCR
#define | LL_I2C_ISR_BERR I2C_ISR_BERR
#define | LL_I2C_ISR_ARLO I2C_ISR_ARLO
#define | LL_I2C_ISR_OVR I2C_ISR_OVR
#define | LL_I2C_ISR_PECERR I2C_ISR_PECERR
#define | LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT
#define | LL_I2C_ISR_ALERT I2C_ISR_ALERT
#define | LL_I2C_ISR_BUSY I2C_ISR_BUSY
#define | LL_I2C_CR1_TXIE I2C_CR1_TXIE
#define | LL_I2C_CR1_RXIE I2C_CR1_RXIE
#define | LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE
#define | LL_I2C_CR1_NACKIE I2C_CR1_NACKIE
#define | LL_I2C_CR1_STOPIE I2C_CR1_STOPIE
#define | LL_I2C_CR1_TCIE I2C_CR1_TCIE
#define | LL_I2C_CR1_ERRIE I2C_CR1_ERRIE
#define | LL_I2C_MODE_I2C 0x00000000U
#define | LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | LL_I2C_MODE_SMBUS_DEVICE 0x00000000U
#define | LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN
#define | LL_I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U
#define | LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10
#define | LL_I2C_OWNADDRESS1_7BIT 0x00000000U
#define | LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE
#define | LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK
#define | LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01
#define | LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02
#define | LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03
#define | LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04
#define | LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05
#define | LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06
#define | LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07
#define | LL_I2C_ACK 0x00000000U
#define | LL_I2C_NACK I2C_CR2_NACK
#define | LL_I2C_ADDRSLAVE_7BIT 0x00000000U
#define | LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10
#define | LL_I2C_REQUEST_WRITE 0x00000000U
#define | LL_I2C_REQUEST_READ I2C_CR2_RD_WRN
#define | LL_I2C_MODE_RELOAD I2C_CR2_RELOAD
#define | LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND
#define | LL_I2C_MODE_SOFTEND 0x00000000U
#define | LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD
#define | LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND
#define | LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND
#define | LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
#define | LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
#define | LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
#define | LL_I2C_GENERATE_STOP I2C_CR2_STOP
#define | LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_START_WRITE I2C_CR2_START
#define | LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START
#define | LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
#define | LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START
#define | LL_I2C_DIRECTION_WRITE 0x00000000U
#define | LL_I2C_DIRECTION_READ I2C_ISR_DIR
#define | LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE
#define | LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN
#define | LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN
#define | LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)
#define | LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2C register.
#define | LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2C register.
#define | __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)
Configure the SDA setup, hold time and the SCL high, low period.

Functions

__STATIC_INLINE void | LL_I2C_Enable (I2C_TypeDef *I2Cx)
Enable I2C peripheral (PE = 1).
__STATIC_INLINE void | LL_I2C_Disable (I2C_TypeDef *I2Cx)
Disable I2C peripheral (PE = 0).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabled (I2C_TypeDef *I2Cx)
Check if the I2C peripheral is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigFilters (I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
Configure Noise Filters (Analog and Digital).
__STATIC_INLINE void | LL_I2C_SetDigitalFilter (I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
Configure Digital Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_GetDigitalFilter (I2C_TypeDef *I2Cx)
Get the current Digital Noise Filter configuration.
__STATIC_INLINE void | LL_I2C_EnableAnalogFilter (I2C_TypeDef *I2Cx)
Enable Analog Noise Filter.
__STATIC_INLINE void | LL_I2C_DisableAnalogFilter (I2C_TypeDef *I2Cx)
Disable Analog Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAnalogFilter (I2C_TypeDef *I2Cx)
Check if Analog Noise Filter is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_TX (I2C_TypeDef *I2Cx)
Enable DMA transmission requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_TX (I2C_TypeDef *I2Cx)
Disable DMA transmission requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_TX (I2C_TypeDef *I2Cx)
Check if DMA transmission requests are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_RX (I2C_TypeDef *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_RX (I2C_TypeDef *I2Cx)
Disable DMA reception requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_RX (I2C_TypeDef *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_DMA_GetRegAddr (I2C_TypeDef *I2Cx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE void | LL_I2C_EnableClockStretching (I2C_TypeDef *I2Cx)
Enable Clock stretching.
__STATIC_INLINE void | LL_I2C_DisableClockStretching (I2C_TypeDef *I2Cx)
Disable Clock stretching.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledClockStretching (I2C_TypeDef *I2Cx)
Check if Clock stretching is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSlaveByteControl (I2C_TypeDef *I2Cx)
Enable hardware byte control in slave mode.
__STATIC_INLINE void | LL_I2C_DisableSlaveByteControl (I2C_TypeDef *I2Cx)
Disable hardware byte control in slave mode.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSlaveByteControl (I2C_TypeDef *I2Cx)
Check if hardware byte control in slave mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableWakeUpFromStop (I2C_TypeDef *I2Cx)
Enable Wakeup from STOP.
__STATIC_INLINE void | LL_I2C_DisableWakeUpFromStop (I2C_TypeDef *I2Cx)
Disable Wakeup from STOP.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledWakeUpFromStop (I2C_TypeDef *I2Cx)
Check if Wakeup from STOP is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableGeneralCall (I2C_TypeDef *I2Cx)
Enable General Call.
__STATIC_INLINE void | LL_I2C_DisableGeneralCall (I2C_TypeDef *I2Cx)
Disable General Call.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledGeneralCall (I2C_TypeDef *I2Cx)
Check if General Call is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetMasterAddressingMode (I2C_TypeDef *I2Cx, uint32_t AddressingMode)
Configure the Master to operate in 7-bit or 10-bit addressing mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMasterAddressingMode (I2C_TypeDef *I2Cx)
Get the Master addressing mode.
__STATIC_INLINE void | LL_I2C_SetOwnAddress1 (I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
Set the Own Address1.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress1 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address1 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress1 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address1 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress1 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetOwnAddress2 (I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
Set the 7bits Own Address2.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress2 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address2 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress2 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address2 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress2 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTiming (I2C_TypeDef *I2Cx, uint32_t Timing)
Configure the SDA setup, hold time and the SCL high, low period.
__STATIC_INLINE uint32_t | LL_I2C_GetTimingPrescaler (I2C_TypeDef *I2Cx)
Get the Timing Prescaler setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockLowPeriod (I2C_TypeDef *I2Cx)
Get the SCL low period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockHighPeriod (I2C_TypeDef *I2Cx)
Get the SCL high period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetDataHoldTime (I2C_TypeDef *I2Cx)
Get the SDA hold time.
__STATIC_INLINE uint32_t | LL_I2C_GetDataSetupTime (I2C_TypeDef *I2Cx)
Get the SDA setup time.
__STATIC_INLINE void | LL_I2C_SetMode (I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
Configure peripheral mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMode (I2C_TypeDef *I2Cx)
Get peripheral mode.
__STATIC_INLINE void | LL_I2C_EnableSMBusAlert (I2C_TypeDef *I2Cx)
Enable SMBus alert (Host or Device mode)
__STATIC_INLINE void | LL_I2C_DisableSMBusAlert (I2C_TypeDef *I2Cx)
Disable SMBus alert (Host or Device mode)
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusAlert (I2C_TypeDef *I2Cx)
Check if SMBus alert (Host or Device mode) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSMBusPEC (I2C_TypeDef *I2Cx)
Enable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE void | LL_I2C_DisableSMBusPEC (I2C_TypeDef *I2Cx)
Disable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPEC (I2C_TypeDef *I2Cx)
Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, uint32_t TimeoutB)
Configure the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutA (I2C_TypeDef *I2Cx, uint32_t TimeoutA)
Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutA (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA setting.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutAMode (I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
Set the SMBus Clock TimeoutA mode.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutAMode (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA mode.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutB (I2C_TypeDef *I2Cx, uint32_t TimeoutB)
Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutB (I2C_TypeDef *I2Cx)
Get the SMBus Extented Cumulative Clock TimeoutB setting.
__STATIC_INLINE void | LL_I2C_EnableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Enable the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_DisableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Disable the SMBus Clock Timeout.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Check if the SMBus Clock Timeout is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TX (I2C_TypeDef *I2Cx)
Enable TXIS interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TX (I2C_TypeDef *I2Cx)
Disable TXIS interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TX (I2C_TypeDef *I2Cx)
Check if the TXIS Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_RX (I2C_TypeDef *I2Cx)
Enable RXNE interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_RX (I2C_TypeDef *I2Cx)
Disable RXNE interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_RX (I2C_TypeDef *I2Cx)
Check if the RXNE Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ADDR (I2C_TypeDef *I2Cx)
Enable Address match interrupt (slave mode only).
__STATIC_INLINE void | LL_I2C_DisableIT_ADDR (I2C_TypeDef *I2Cx)
Disable Address match interrupt (slave mode only).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ADDR (I2C_TypeDef *I2Cx)
Check if Address match interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_NACK (I2C_TypeDef *I2Cx)
Enable Not acknowledge received interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_NACK (I2C_TypeDef *I2Cx)
Disable Not acknowledge received interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_NACK (I2C_TypeDef *I2Cx)
Check if Not acknowledge received interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_STOP (I2C_TypeDef *I2Cx)
Enable STOP detection interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_STOP (I2C_TypeDef *I2Cx)
Disable STOP detection interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_STOP (I2C_TypeDef *I2Cx)
Check if STOP detection interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TC (I2C_TypeDef *I2Cx)
Enable Transfer Complete interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TC (I2C_TypeDef *I2Cx)
Disable Transfer Complete interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TC (I2C_TypeDef *I2Cx)
Check if Transfer Complete interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ERR (I2C_TypeDef *I2Cx)
Enable Error interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_ERR (I2C_TypeDef *I2Cx)
Disable Error interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ERR (I2C_TypeDef *I2Cx)
Check if Error interrupts are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXE (I2C_TypeDef *I2Cx)
Indicate the status of Transmit data register empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXIS (I2C_TypeDef *I2Cx)
Indicate the status of Transmit interrupt flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_RXNE (I2C_TypeDef *I2Cx)
Indicate the status of Receive data register not empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ADDR (I2C_TypeDef *I2Cx)
Indicate the status of Address matched flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_NACK (I2C_TypeDef *I2Cx)
Indicate the status of Not Acknowledge received flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_STOP (I2C_TypeDef *I2Cx)
Indicate the status of Stop detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TC (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TCR (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BERR (I2C_TypeDef *I2Cx)
Indicate the status of Bus error flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ARLO (I2C_TypeDef *I2Cx)
Indicate the status of Arbitration lost flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_OVR (I2C_TypeDef *I2Cx)
Indicate the status of Overrun/Underrun flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Indicate the status of SMBus PEC error flag in reception.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus Timeout detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus alert flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BUSY (I2C_TypeDef *I2Cx)
Indicate the status of Bus Busy flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ADDR (I2C_TypeDef *I2Cx)
Clear Address Matched flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_NACK (I2C_TypeDef *I2Cx)
Clear Not Acknowledge flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_STOP (I2C_TypeDef *I2Cx)
Clear Stop detection flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_TXE (I2C_TypeDef *I2Cx)
Clear Transmit data register empty flag (TXE).
__STATIC_INLINE void | LL_I2C_ClearFlag_BERR (I2C_TypeDef *I2Cx)
Clear Bus error flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ARLO (I2C_TypeDef *I2Cx)
Clear Arbitration lost flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_OVR (I2C_TypeDef *I2Cx)
Clear Overrun/Underrun flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Clear SMBus PEC error flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Clear SMBus Timeout detection flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Clear SMBus Alert flag.
__STATIC_INLINE void | LL_I2C_EnableAutoEndMode (I2C_TypeDef *I2Cx)
Enable automatic STOP condition generation (master mode).
__STATIC_INLINE void | LL_I2C_DisableAutoEndMode (I2C_TypeDef *I2Cx)
Disable automatic STOP condition generation (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAutoEndMode (I2C_TypeDef *I2Cx)
Check if automatic STOP condition is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableReloadMode (I2C_TypeDef *I2Cx)
Enable reload mode (master mode).
__STATIC_INLINE void | LL_I2C_DisableReloadMode (I2C_TypeDef *I2Cx)
Disable reload mode (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledReloadMode (I2C_TypeDef *I2Cx)
Check if reload mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferSize (I2C_TypeDef *I2Cx, uint32_t TransferSize)
Configure the number of bytes for transfer.
__STATIC_INLINE uint32_t | LL_I2C_GetTransferSize (I2C_TypeDef *I2Cx)
Get the number of bytes configured for transfer.
__STATIC_INLINE void | LL_I2C_AcknowledgeNextData (I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
__STATIC_INLINE void | LL_I2C_GenerateStartCondition (I2C_TypeDef *I2Cx)
Generate a START or RESTART condition.
__STATIC_INLINE void | LL_I2C_GenerateStopCondition (I2C_TypeDef *I2Cx)
Generate a STOP condition after the current byte transfer (master mode).
__STATIC_INLINE void | LL_I2C_EnableAuto10BitRead (I2C_TypeDef *I2Cx)
Enable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE void | LL_I2C_DisableAuto10BitRead (I2C_TypeDef *I2Cx)
Disable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAuto10BitRead (I2C_TypeDef *I2Cx)
Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferRequest (I2C_TypeDef *I2Cx, uint32_t TransferRequest)
Configure the transfer direction (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferRequest (I2C_TypeDef *I2Cx)
Get the transfer direction requested (master mode).
__STATIC_INLINE void | LL_I2C_SetSlaveAddr (I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
Configure the slave address for transfer (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSlaveAddr (I2C_TypeDef *I2Cx)
Get the slave address programmed for transfer.
__STATIC_INLINE void | LL_I2C_HandleTransfer (I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferDirection (I2C_TypeDef *I2Cx)
Indicate the value of transfer direction (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetAddressMatchCode (I2C_TypeDef *I2Cx)
Return the slave matched address.
__STATIC_INLINE void | LL_I2C_EnableSMBusPECCompare (I2C_TypeDef *I2Cx)
Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPECCompare (I2C_TypeDef *I2Cx)
Check if the SMBus Packet Error byte internal comparison is requested or not.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusPEC (I2C_TypeDef *I2Cx)
Get the SMBus Packet Error byte calculated.
__STATIC_INLINE uint8_t | LL_I2C_ReceiveData8 (I2C_TypeDef *I2Cx)
Read Receive Data register.
__STATIC_INLINE void | LL_I2C_TransmitData8 (I2C_TypeDef *I2Cx, uint8_t Data)
Write in Transmit Data Register .
uint32_t | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
uint32_t | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Detailed Description

Header file of I2C LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_i2c.h.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_iwdg.h File Reference

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Defines | Functions
stm32f3xx_ll_iwdg.h File Reference

Header file of IWDG LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Defines

#define | LL_IWDG_KEY_RELOAD 0x0000AAAAU
#define | LL_IWDG_KEY_ENABLE 0x0000CCCCU
#define | LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U
#define | LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U
#define | LL_IWDG_SR_PVU IWDG_SR_PVU
#define | LL_IWDG_SR_RVU IWDG_SR_RVU
#define | LL_IWDG_SR_WVU IWDG_SR_WVU
#define | LL_IWDG_PRESCALER_4 0x00000000U
#define | LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)
#define | LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)
#define | LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)
#define | LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in IWDG register.
#define | LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in IWDG register.

Functions

__STATIC_INLINE void | LL_IWDG_Enable (IWDG_TypeDef *IWDGx)
Start the Independent Watchdog.
__STATIC_INLINE void | LL_IWDG_ReloadCounter (IWDG_TypeDef *IWDGx)
Reloads IWDG counter with value defined in the reload register.
__STATIC_INLINE void | LL_IWDG_EnableWriteAccess (IWDG_TypeDef *IWDGx)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_DisableWriteAccess (IWDG_TypeDef *IWDGx)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_SetPrescaler (IWDG_TypeDef *IWDGx, uint32_t Prescaler)
Select the prescaler of the IWDG.
__STATIC_INLINE uint32_t | LL_IWDG_GetPrescaler (IWDG_TypeDef *IWDGx)
Get the selected prescaler of the IWDG.
__STATIC_INLINE void | LL_IWDG_SetReloadCounter (IWDG_TypeDef *IWDGx, uint32_t Counter)
Specify the IWDG down-counter reload value.
__STATIC_INLINE uint32_t | LL_IWDG_GetReloadCounter (IWDG_TypeDef *IWDGx)
Get the specified IWDG down-counter reload value.
__STATIC_INLINE void | LL_IWDG_SetWindow (IWDG_TypeDef *IWDGx, uint32_t Window)
Specify high limit of the window value to be compared to the down-counter.
__STATIC_INLINE uint32_t | LL_IWDG_GetWindow (IWDG_TypeDef *IWDGx)
Get the high limit of the window value specified.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_PVU (IWDG_TypeDef *IWDGx)
Check if flag Prescaler Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_RVU (IWDG_TypeDef *IWDGx)
Check if flag Reload Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_WVU (IWDG_TypeDef *IWDGx)
Check if flag Window Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsReady (IWDG_TypeDef *IWDGx)
Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Detailed Description

Header file of IWDG LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_iwdg.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_pwr.h File Reference

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Defines | Functions
stm32f3xx_ll_pwr.h File Reference

Header file of PWR LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Defines

#define | LL_PWR_CR_CSBF PWR_CR_CSBF
#define | LL_PWR_CR_CWUF PWR_CR_CWUF
#define | LL_PWR_CSR_WUF PWR_CSR_WUF
#define | LL_PWR_CSR_SBF PWR_CSR_SBF
#define | LL_PWR_CSR_PVDO PWR_CSR_PVDO
#define | LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF
#define | LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1
#define | LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2
#define | LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3
#define | LL_PWR_MODE_STOP_MAINREGU 0x00000000U
#define | LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS)
#define | LL_PWR_MODE_STANDBY (PWR_CR_PDDS)
#define | LL_PWR_REGU_DSMODE_MAIN 0x00000000U
#define | LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS)
#define | LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0)
#define | LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1)
#define | LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2)
#define | LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3)
#define | LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4)
#define | LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5)
#define | LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6)
#define | LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7)
#define | LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1)
#define | LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2)
#define | LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3)
#define | LL_PWR_SDADC_ANALOG1 (PWR_CR_ENSD1)
#define | LL_PWR_SDADC_ANALOG2 (PWR_CR_ENSD2)
#define | LL_PWR_SDADC_ANALOG3 (PWR_CR_ENSD3)
#define | LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
Write a value in PWR register.
#define | LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
Read a value in PWR register.

Functions

__STATIC_INLINE void | LL_PWR_EnableSDADC (uint32_t Analogx)
Enables the SDADC peripheral functionality.
__STATIC_INLINE void | LL_PWR_DisableSDADC (uint32_t Analogx)
Disables the SDADC peripheral functionality.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledSDADC (uint32_t Analogx)
Check if SDADCx has been enabled or not.
__STATIC_INLINE void | LL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain.
__STATIC_INLINE void | LL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBkUpAccess (void)
Check if the backup domain is enabled.
__STATIC_INLINE void | LL_PWR_SetRegulModeDS (uint32_t RegulMode)
Set voltage Regulator mode during deep sleep mode.
__STATIC_INLINE uint32_t | LL_PWR_GetRegulModeDS (void)
Get voltage Regulator mode during deep sleep mode.
__STATIC_INLINE void | LL_PWR_SetPowerMode (uint32_t PDMode)
Set Power Down mode when CPU enters deepsleep.
__STATIC_INLINE uint32_t | LL_PWR_GetPowerMode (void)
Get Power Down mode when CPU enters deepsleep.
__STATIC_INLINE void | LL_PWR_SetPVDLevel (uint32_t PVDLevel)
Configure the voltage threshold detected by the Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetPVDLevel (void)
Get the voltage threshold detection.
__STATIC_INLINE void | LL_PWR_EnablePVD (void)
Enable Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_DisablePVD (void)
Disable Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVD (void)
Check if Power Voltage Detector is enabled.
__STATIC_INLINE void | LL_PWR_EnableWakeUpPin (uint32_t WakeUpPin)
Enable the WakeUp PINx functionality.
__STATIC_INLINE void | LL_PWR_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the WakeUp PINx functionality.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledWakeUpPin (uint32_t WakeUpPin)
Check if the WakeUp PINx functionality is enabled.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU (void)
Get Wake-up Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_SB (void)
Get Standby Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVDO (void)
Indicate whether VDD voltage is below the selected PVD threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_VREFINTRDY (void)
Get Internal Reference VrefInt Flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_SB (void)
Clear Standby Flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU (void)
Clear Wake-up Flags.
ErrorStatus | LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Detailed Description

Header file of PWR LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_pwr.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_rcc.h File Reference

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Data Structures | Defines | Functions
stm32f3xx_ll_rcc.h File Reference

Header file of RCC LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Data Structures

struct | LL_RCC_ClocksTypeDef
RCC Clocks Frequency Structure. More...

Defines

#define | RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE)
#define | RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1)
#define | RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2)
#define | RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_CR_HSICAL)
#define | RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_CR_HSITRIM)
#define | RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL)
#define | RCC_POSITION_USART1SW (uint32_t)0U
#define | RCC_POSITION_USART2SW (uint32_t)16U
#define | RCC_POSITION_USART3SW (uint32_t)18U
#define | RCC_POSITION_TIM1SW (uint32_t)8U
#define | RCC_POSITION_TIM8SW (uint32_t)9U
#define | RCC_POSITION_TIM15SW (uint32_t)10U
#define | RCC_POSITION_TIM16SW (uint32_t)11U
#define | RCC_POSITION_TIM17SW (uint32_t)13U
#define | RCC_POSITION_TIM20SW (uint32_t)15U
#define | RCC_POSITION_TIM2SW (uint32_t)24U
#define | RCC_POSITION_TIM34SW (uint32_t)25U
#define | HSE_VALUE 8000000U
#define | HSI_VALUE 8000000U
#define | LSE_VALUE 32768U
#define | LSI_VALUE 32000U
#define | LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC
#define | LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC
#define | LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC
#define | LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC
#define | LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC
#define | LL_RCC_CIR_CSSC RCC_CIR_CSSC
#define | LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF
#define | LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF
#define | LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF
#define | LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF
#define | LL_RCC_CFGR_MCOF RCC_CFGR_MCOF
#define | LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF
#define | LL_RCC_CIR_CSSF RCC_CIR_CSSF
#define | LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF
#define | LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF
#define | LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF
#define | LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF
#define | LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF
#define | LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF
#define | LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF
#define | LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF
#define | LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE
#define | LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE
#define | LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE
#define | LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE
#define | LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE
#define | LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)
#define | LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
#define | LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
#define | LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
#define | LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL
#define | LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1
#define | LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2
#define | LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4
#define | LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8
#define | LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16
#define | LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64
#define | LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128
#define | LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256
#define | LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512
#define | LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1
#define | LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2
#define | LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4
#define | LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8
#define | LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16
#define | LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1
#define | LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2
#define | LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4
#define | LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8
#define | LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16
#define | LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
#define | LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
#define | LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI
#define | LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE
#define | LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI
#define | LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE
#define | LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2
#define | LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)
#define | LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U
#define | LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU
#define | LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK2)
#define | LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_SYSCLK)
#define | LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_LSE)
#define | LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_HSI)
#define | LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_PCLK)
#define | LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_SYSCLK)
#define | LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_LSE)
#define | LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_HSI)
#define | LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_PCLK)
#define | LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_SYSCLK)
#define | LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_LSE)
#define | LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_HSI)
#define | LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_HSI)
#define | LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_SYSCLK)
#define | LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_HSI)
#define | LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_SYSCLK)
#define | LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244
#define | LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
#define | LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1
#define | LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 RCC_CFGR_USBPRE_DIV1_5
#define | LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2
#define | LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4
#define | LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6
#define | LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_1 RCC_CFGR_SDPRE_DIV1
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_2 RCC_CFGR_SDPRE_DIV2
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_4 RCC_CFGR_SDPRE_DIV4
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_6 RCC_CFGR_SDPRE_DIV6
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_8 RCC_CFGR_SDPRE_DIV8
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_10 RCC_CFGR_SDPRE_DIV10
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_12 RCC_CFGR_SDPRE_DIV12
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_14 RCC_CFGR_SDPRE_DIV14
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_16 RCC_CFGR_SDPRE_DIV16
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_20 RCC_CFGR_SDPRE_DIV20
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_24 RCC_CFGR_SDPRE_DIV24
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_28 RCC_CFGR_SDPRE_DIV28
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_32 RCC_CFGR_SDPRE_DIV32
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_36 RCC_CFGR_SDPRE_DIV36
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_40 RCC_CFGR_SDPRE_DIV40
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_44 RCC_CFGR_SDPRE_DIV44
#define | LL_RCC_SDADC_CLKSRC_SYS_DIV_48 RCC_CFGR_SDPRE_DIV48
#define | LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW
#define | LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW
#define | LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW
#define | LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW
#define | LL_RCC_I2C2_CLKSOURCE RCC_CFGR3_I2C2SW
#define | LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW
#define | LL_RCC_USB_CLKSOURCE RCC_CFGR_USBPRE
#define | LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE
#define | LL_RCC_SDADC_CLKSOURCE RCC_CFGR_SDPRE
#define | LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U
#define | LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL
#define | LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2
#define | LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3
#define | LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4
#define | LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5
#define | LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6
#define | LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7
#define | LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8
#define | LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9
#define | LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10
#define | LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11
#define | LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12
#define | LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13
#define | LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14
#define | LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15
#define | LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16
#define | LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
#define | LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2
#define | LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1)
#define | LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2)
#define | LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3)
#define | LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4)
#define | LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5)
#define | LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6)
#define | LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7)
#define | LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8)
#define | LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9)
#define | LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10)
#define | LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11)
#define | LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12)
#define | LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13)
#define | LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14)
#define | LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15)
#define | LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16)
#define | LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1
#define | LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2
#define | LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3
#define | LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4
#define | LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5
#define | LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6
#define | LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7
#define | LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8
#define | LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9
#define | LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10
#define | LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11
#define | LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12
#define | LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13
#define | LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14
#define | LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15
#define | LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16
#define | LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
Write a value in RCC register.
#define | LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
Read a value in RCC register.
#define | __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
Helper macro to calculate the PLLCLK frequency.
#define | __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
Helper macro to calculate the HCLK frequency.
#define | __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
Helper macro to calculate the PCLK1 frequency (ABP1)
#define | __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
Helper macro to calculate the PCLK2 frequency (ABP2)

Functions

__STATIC_INLINE void | LL_RCC_HSE_EnableCSS (void)
Enable the Clock Security System.
__STATIC_INLINE void | LL_RCC_HSE_DisableCSS (void)
Disable the Clock Security System.
__STATIC_INLINE void | LL_RCC_HSE_EnableBypass (void)
Enable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_DisableBypass (void)
Disable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_Enable (void)
Enable HSE crystal oscillator (HSE ON)
__STATIC_INLINE void | LL_RCC_HSE_Disable (void)
Disable HSE crystal oscillator (HSE ON)
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsReady (void)
Check if HSE oscillator Ready.
__STATIC_INLINE void | LL_RCC_HSI_Enable (void)
Enable HSI oscillator.
__STATIC_INLINE void | LL_RCC_HSI_Disable (void)
Disable HSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsReady (void)
Check if HSI clock is ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibration (void)
Get HSI Calibration value.
__STATIC_INLINE void | LL_RCC_HSI_SetCalibTrimming (uint32_t Value)
Set HSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibTrimming (void)
Get HSI Calibration trimming.
__STATIC_INLINE void | LL_RCC_LSE_Enable (void)
Enable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_Disable (void)
Disable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_EnableBypass (void)
Enable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_DisableBypass (void)
Disable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_SetDriveCapability (uint32_t LSEDrive)
Set LSE oscillator drive capability.
__STATIC_INLINE uint32_t | LL_RCC_LSE_GetDriveCapability (void)
Get LSE oscillator drive capability.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsReady (void)
Check if LSE oscillator Ready.
__STATIC_INLINE void | LL_RCC_LSI_Enable (void)
Enable LSI Oscillator.
__STATIC_INLINE void | LL_RCC_LSI_Disable (void)
Disable LSI Oscillator.
__STATIC_INLINE uint32_t | LL_RCC_LSI_IsReady (void)
Check if LSI is Ready.
__STATIC_INLINE void | LL_RCC_SetSysClkSource (uint32_t Source)
Configure the system clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSysClkSource (void)
Get the system clock source.
__STATIC_INLINE void | LL_RCC_SetAHBPrescaler (uint32_t Prescaler)
Set AHB prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB1Prescaler (uint32_t Prescaler)
Set APB1 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB2Prescaler (uint32_t Prescaler)
Set APB2 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAHBPrescaler (void)
Get AHB prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB1Prescaler (void)
Get APB1 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB2Prescaler (void)
Get APB2 prescaler.
__STATIC_INLINE void | LL_RCC_ConfigMCO (uint32_t MCOxSource, uint32_t MCOxPrescaler)
Configure MCOx.
__STATIC_INLINE void | LL_RCC_SetUSARTClockSource (uint32_t USARTxSource)
Configure USARTx clock source.
__STATIC_INLINE void | LL_RCC_SetI2CClockSource (uint32_t I2CxSource)
Configure I2Cx clock source.
__STATIC_INLINE void | LL_RCC_SetCECClockSource (uint32_t CECxSource)
Configure CEC clock source.
__STATIC_INLINE void | LL_RCC_SetUSBClockSource (uint32_t USBxSource)
Configure USB clock source.
__STATIC_INLINE void | LL_RCC_SetADCClockSource (uint32_t ADCxSource)
Configure ADC clock source.
__STATIC_INLINE void | LL_RCC_SetSDADCClockSource (uint32_t SDADCxSource)
Configure SDADCx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSARTClockSource (uint32_t USARTx)
Get USARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetI2CClockSource (uint32_t I2Cx)
Get I2Cx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetCECClockSource (uint32_t CECx)
Get CEC clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSBClockSource (uint32_t USBx)
Get USBx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetADCClockSource (uint32_t ADCx)
Get ADCx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSDADCClockSource (uint32_t SDADCx)
Get SDADCx clock source.
__STATIC_INLINE void | LL_RCC_SetRTCClockSource (uint32_t Source)
Set RTC Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_GetRTCClockSource (void)
Get RTC Clock Source.
__STATIC_INLINE void | LL_RCC_EnableRTC (void)
Enable RTC.
__STATIC_INLINE void | LL_RCC_DisableRTC (void)
Disable RTC.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledRTC (void)
Check if RTC has been enabled or not.
__STATIC_INLINE void | LL_RCC_ForceBackupDomainReset (void)
Force the Backup domain reset.
__STATIC_INLINE void | LL_RCC_ReleaseBackupDomainReset (void)
Release the Backup domain reset.
__STATIC_INLINE void | LL_RCC_PLL_Enable (void)
Enable PLL.
__STATIC_INLINE void | LL_RCC_PLL_Disable (void)
Disable PLL.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsReady (void)
Check if PLL Ready.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SYS (uint32_t Source, uint32_t PLLMul)
Configure PLL used for SYSCLK Domain.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMainSource (void)
Get the oscillator used as PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMultiplicator (void)
Get PLL multiplication Factor.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetPrediv (void)
Get PREDIV division factor for the main PLL.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSIRDY (void)
Clear LSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSERDY (void)
Clear LSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSIRDY (void)
Clear HSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSERDY (void)
Clear HSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLRDY (void)
Clear PLL ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSECSS (void)
Clear Clock security system interrupt flag.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSIRDY (void)
Check if LSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSERDY (void)
Check if LSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSIRDY (void)
Check if HSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSERDY (void)
Check if HSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLRDY (void)
Check if PLL ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSECSS (void)
Check if Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_IWDGRST (void)
Check if RCC flag Independent Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LPWRRST (void)
Check if RCC flag Low Power reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_OBLRST (void)
Check if RCC flag is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PINRST (void)
Check if RCC flag Pin reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PORRST (void)
Check if RCC flag POR/PDR reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SFTRST (void)
Check if RCC flag Software reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_WWDGRST (void)
Check if RCC flag Window Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_V18PWRRST (void)
Check if RCC Reset flag of the 1.8 V domain is set or not.
__STATIC_INLINE void | LL_RCC_ClearResetFlags (void)
Set RMVF bit to clear the reset flags.
__STATIC_INLINE void | LL_RCC_EnableIT_LSIRDY (void)
Enable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSERDY (void)
Enable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSIRDY (void)
Enable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSERDY (void)
Enable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLRDY (void)
Enable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSIRDY (void)
Disable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSERDY (void)
Disable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSIRDY (void)
Disable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSERDY (void)
Disable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLRDY (void)
Disable PLL ready interrupt.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSIRDY (void)
Checks if LSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSERDY (void)
Checks if LSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSIRDY (void)
Checks if HSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSERDY (void)
Checks if HSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLRDY (void)
Checks if PLL ready interrupt source is enabled or disabled.
ErrorStatus | LL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.
uint32_t | LL_RCC_GetSDADCClockFreq (uint32_t SDADCxSource)
Return SDADCx clock frequency.
uint32_t | LL_RCC_GetCECClockFreq (uint32_t CECxSource)
Return CECx clock frequency.
uint32_t | LL_RCC_GetHRTIMClockFreq (uint32_t HRTIMxSource)

Detailed Description

Header file of RCC LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_rcc.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_rtc.h File Reference

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Data Structures | Defines | Functions
stm32f3xx_ll_rtc.h File Reference

Header file of RTC LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Data Structures

struct | LL_RTC_InitTypeDef
RTC Init structures definition. More...
struct | LL_RTC_TimeTypeDef
RTC Time structure definition. More...
struct | LL_RTC_DateTypeDef
RTC Date structure definition. More...
struct | LL_RTC_AlarmTypeDef
RTC Alarm structure definition. More...

Defines

#define | RTC_INIT_MASK 0xFFFFFFFFU
#define | RTC_RSF_MASK 0xFFFFFF5FU
#define | RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)
#define | RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
#define | RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
#define | RTC_OFFSET_WEEKDAY 24U
#define | RTC_OFFSET_DAY 16U
#define | RTC_OFFSET_MONTH 8U
#define | RTC_OFFSET_HOUR 16U
#define | RTC_OFFSET_MINUTE 8U
#define | LL_RTC_FORMAT_BIN 0x000000000U
#define | LL_RTC_FORMAT_BCD 0x000000001U
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL
#define | LL_RTC_ISR_RECALPF RTC_ISR_RECALPF
#define | LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F
#define | LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F
#define | LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F
#define | LL_RTC_ISR_TSOVF RTC_ISR_TSOVF
#define | LL_RTC_ISR_TSF RTC_ISR_TSF
#define | LL_RTC_ISR_WUTF RTC_ISR_WUTF
#define | LL_RTC_ISR_ALRBF RTC_ISR_ALRBF
#define | LL_RTC_ISR_ALRAF RTC_ISR_ALRAF
#define | LL_RTC_ISR_INITF RTC_ISR_INITF
#define | LL_RTC_ISR_RSF RTC_ISR_RSF
#define | LL_RTC_ISR_INITS RTC_ISR_INITS
#define | LL_RTC_ISR_SHPF RTC_ISR_SHPF
#define | LL_RTC_ISR_WUTWF RTC_ISR_WUTWF
#define | LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF
#define | LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF
#define | LL_RTC_CR_TSIE RTC_CR_TSIE
#define | LL_RTC_CR_WUTIE RTC_CR_WUTIE
#define | LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
#define | LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
#define | LL_RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE
#define | LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define | LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define | LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define | LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define | LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define | LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define | LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
#define | LL_RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define | LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define | LL_RTC_MONTH_MARCH ((uint8_t)0x03U)
#define | LL_RTC_MONTH_APRIL ((uint8_t)0x04U)
#define | LL_RTC_MONTH_MAY ((uint8_t)0x05U)
#define | LL_RTC_MONTH_JUNE ((uint8_t)0x06U)
#define | LL_RTC_MONTH_JULY ((uint8_t)0x07U)
#define | LL_RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define | LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define | LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define | LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define | LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U)
#define | LL_RTC_HOURFORMAT_24HOUR 0x00000000U
#define | LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT
#define | LL_RTC_ALARMOUT_DISABLE 0x00000000U
#define | LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0
#define | LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1
#define | LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL
#define | LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U
#define | LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE
#define | LL_RTC_PIN_PC13 RTC_TAFCR_PC13MODE
#define | LL_RTC_PIN_PC14 RTC_TAFCR_PC14MODE
#define | LL_RTC_PIN_PC15 RTC_TAFCR_PC15MODE
#define | LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U
#define | LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL
#define | LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U
#define | LL_RTC_TIME_FORMAT_PM RTC_TR_PM
#define | LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
#define | LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
#define | LL_RTC_ALMA_MASK_NONE 0x00000000U
#define | LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3
#define | LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2
#define | LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1
#define | LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)
#define | LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM
#define | LL_RTC_ALMB_MASK_NONE 0x00000000U
#define | LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4
#define | LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3
#define | LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2
#define | LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1
#define | LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)
#define | LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM
#define | LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U
#define | LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE
#define | LL_RTC_TS_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM
#define | LL_RTC_TAMPER_1 RTC_TAFCR_TAMP1E
#define | LL_RTC_TAMPER_2 RTC_TAFCR_TAMP2E
#define | LL_RTC_TAMPER_3 RTC_TAFCR_TAMP3E
#define | LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAFCR_TAMP1MF
#define | LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAFCR_TAMP2MF
#define | LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAFCR_TAMP3MF
#define | LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAFCR_TAMP1NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAFCR_TAMP2NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAFCR_TAMP3NOERASE
#define | LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U
#define | LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0
#define | LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1
#define | LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAFCR_TAMPPRCH
#define | LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U
#define | LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0
#define | LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1
#define | LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAFCR_TAMPFLT
#define | LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U
#define | LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAFCR_TAMPFREQ_0
#define | LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAFCR_TAMPFREQ_1
#define | LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAFCR_TAMPFREQ_2
#define | LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_1)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAFCR_TAMPFREQ
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAFCR_TAMP1TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAFCR_TAMP2TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAFCR_TAMP3TRG
#define | LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U
#define | LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1)
#define | LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)
#define | LL_RTC_BKP_DR0 0x00000000U
#define | LL_RTC_BKP_DR1 0x00000001U
#define | LL_RTC_BKP_DR2 0x00000002U
#define | LL_RTC_BKP_DR3 0x00000003U
#define | LL_RTC_BKP_DR4 0x00000004U
#define | LL_RTC_BKP_DR5 0x00000005U
#define | LL_RTC_BKP_DR6 0x00000006U
#define | LL_RTC_BKP_DR7 0x00000007U
#define | LL_RTC_BKP_DR8 0x00000008U
#define | LL_RTC_BKP_DR9 0x00000009U
#define | LL_RTC_BKP_DR10 0x0000000AU
#define | LL_RTC_BKP_DR11 0x0000000BU
#define | LL_RTC_BKP_DR12 0x0000000CU
#define | LL_RTC_BKP_DR13 0x0000000DU
#define | LL_RTC_BKP_DR14 0x0000000EU
#define | LL_RTC_BKP_DR15 0x0000000FU
#define | LL_RTC_BKP_DR16 0x00000010U
#define | LL_RTC_BKP_DR17 0x00000011U
#define | LL_RTC_BKP_DR18 0x00000012U
#define | LL_RTC_BKP_DR19 0x00000013U
#define | LL_RTC_BKP_DR20 0x00000014U
#define | LL_RTC_BKP_DR21 0x00000015U
#define | LL_RTC_BKP_DR22 0x00000016U
#define | LL_RTC_BKP_DR23 0x00000017U
#define | LL_RTC_BKP_DR24 0x00000018U
#define | LL_RTC_BKP_DR25 0x00000019U
#define | LL_RTC_BKP_DR26 0x0000001AU
#define | LL_RTC_BKP_DR27 0x0000001BU
#define | LL_RTC_BKP_DR28 0x0000001CU
#define | LL_RTC_BKP_DR29 0x0000001DU
#define | LL_RTC_BKP_DR30 0x0000001EU
#define | LL_RTC_BKP_DR31 0x0000001FU
#define | LL_RTC_CALIB_OUTPUT_NONE 0x00000000U
#define | LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)
#define | LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE)
#define | LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U
#define | LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP
#define | LL_RTC_CALIB_PERIOD_32SEC 0x00000000U
#define | LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8
#define | LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RTC register.
#define | LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RTC register.
#define | __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
Helper macro to convert a value from 2 digit decimal format to BCD format.
#define | __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))
Helper macro to convert a value from BCD format to 2 digit decimal format.
#define | __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
Helper macro to retrieve weekday.
#define | __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
Helper macro to retrieve Year in BCD format.
#define | __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
Helper macro to retrieve Month in BCD format.
#define | __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
Helper macro to retrieve Day in BCD format.
#define | __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
Helper macro to retrieve hour in BCD format.
#define | __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
Helper macro to retrieve minute in BCD format.
#define | __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
Helper macro to retrieve second in BCD format.

Functions

__STATIC_INLINE void | LL_RTC_SetHourFormat (RTC_TypeDef *RTCx, uint32_t HourFormat)
Set Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE uint32_t | LL_RTC_GetHourFormat (RTC_TypeDef *RTCx)
Get Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE void | LL_RTC_SetAlarmOutEvent (RTC_TypeDef *RTCx, uint32_t AlarmOutput)
Select the flag to be routed to RTC_ALARM output.
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutEvent (RTC_TypeDef *RTCx)
Get the flag to be routed to RTC_ALARM output.
__STATIC_INLINE void | LL_RTC_SetAlarmOutputType (RTC_TypeDef *RTCx, uint32_t Output)
Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutputType (RTC_TypeDef *RTCx)
Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE void | LL_RTC_EnablePushPullMode (RTC_TypeDef *RTCx, uint32_t PinMask)
Enable push-pull output on PC13, PC14 and/or PC15.
__STATIC_INLINE void | LL_RTC_DisablePushPullMode (RTC_TypeDef *RTCx, uint32_t PinMask)
Disable push-pull output on PC13, PC14 and/or PC15.
__STATIC_INLINE void | LL_RTC_SetOutputPin (RTC_TypeDef *RTCx, uint32_t PinMask)
Set PC14 and/or PC15 to high level.
__STATIC_INLINE void | LL_RTC_ResetOutputPin (RTC_TypeDef *RTCx, uint32_t PinMask)
Set PC14 and/or PC15 to low level.
__STATIC_INLINE void | LL_RTC_EnableInitMode (RTC_TypeDef *RTCx)
Enable initialization mode.
__STATIC_INLINE void | LL_RTC_DisableInitMode (RTC_TypeDef *RTCx)
Disable initialization mode (Free running mode)
__STATIC_INLINE void | LL_RTC_SetOutputPolarity (RTC_TypeDef *RTCx, uint32_t Polarity)
Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
__STATIC_INLINE uint32_t | LL_RTC_GetOutputPolarity (RTC_TypeDef *RTCx)
Get Output polarity.
__STATIC_INLINE void | LL_RTC_EnableShadowRegBypass (RTC_TypeDef *RTCx)
Enable Bypass the shadow registers.
__STATIC_INLINE void | LL_RTC_DisableShadowRegBypass (RTC_TypeDef *RTCx)
Disable Bypass the shadow registers.
__STATIC_INLINE uint32_t | LL_RTC_IsShadowRegBypassEnabled (RTC_TypeDef *RTCx)
Check if Shadow registers bypass is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableRefClock (RTC_TypeDef *RTCx)
Enable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_DisableRefClock (RTC_TypeDef *RTCx)
Disable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_SetAsynchPrescaler (RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
Set Asynchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_SetSynchPrescaler (RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
Set Synchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetAsynchPrescaler (RTC_TypeDef *RTCx)
Get Asynchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetSynchPrescaler (RTC_TypeDef *RTCx)
Get Synchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_EnableWriteProtection (RTC_TypeDef *RTCx)
Enable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_DisableWriteProtection (RTC_TypeDef *RTCx)
Disable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_TIME_SetFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetFormat (RTC_TypeDef *RTCx)
Get time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_TIME_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetHour (RTC_TypeDef *RTCx)
Get Hours in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetMinute (RTC_TypeDef *RTCx)
Get Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSecond (RTC_TypeDef *RTCx)
Get Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_Config (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_Get (RTC_TypeDef *RTCx)
Get time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_EnableDayLightStore (RTC_TypeDef *RTCx)
Memorize whether the daylight saving time change has been performed.
__STATIC_INLINE void | LL_RTC_TIME_DisableDayLightStore (RTC_TypeDef *RTCx)
Disable memorization whether the daylight saving time change has been performed.
__STATIC_INLINE uint32_t | LL_RTC_TIME_IsDayLightStoreEnabled (RTC_TypeDef *RTCx)
Check if RTC Day Light Saving stored operation has been enabled or not.
__STATIC_INLINE void | LL_RTC_TIME_DecHour (RTC_TypeDef *RTCx)
Subtract 1 hour (winter time change)
__STATIC_INLINE void | LL_RTC_TIME_IncHour (RTC_TypeDef *RTCx)
Add 1 hour (summer time change)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSubSecond (RTC_TypeDef *RTCx)
Get Sub second value in the synchronous prescaler counter.
__STATIC_INLINE void | LL_RTC_TIME_Synchronize (RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
Synchronize to a remote clock with a high degree of precision.
__STATIC_INLINE void | LL_RTC_DATE_SetYear (RTC_TypeDef *RTCx, uint32_t Year)
Set Year in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetYear (RTC_TypeDef *RTCx)
Get Year in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set Week day.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetWeekDay (RTC_TypeDef *RTCx)
Get Week day.
__STATIC_INLINE void | LL_RTC_DATE_SetMonth (RTC_TypeDef *RTCx, uint32_t Month)
Set Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetMonth (RTC_TypeDef *RTCx)
Get Month in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetDay (RTC_TypeDef *RTCx)
Get Day in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_Config (RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
Set date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_Get (RTC_TypeDef *RTCx)
Get date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_Enable (RTC_TypeDef *RTCx)
Enable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_Disable (RTC_TypeDef *RTCx)
Disable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm A masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMask (RTC_TypeDef *RTCx)
Get the Alarm A masks.
__STATIC_INLINE void | LL_RTC_ALMA_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmA Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMA_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmA Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMA_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM A Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetDay (RTC_TypeDef *RTCx)
Get ALARM A Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM A Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM A Weekday.
__STATIC_INLINE void | LL_RTC_ALMA_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set Alarm A time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTimeFormat (RTC_TypeDef *RTCx)
Get Alarm A time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMA_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM A Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetHour (RTC_TypeDef *RTCx)
Get ALARM A Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM A Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMinute (RTC_TypeDef *RTCx)
Get ALARM A Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM A Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSecond (RTC_TypeDef *RTCx)
Get ALARM A Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm A Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm A Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm A Sub seconds value.
__STATIC_INLINE void | LL_RTC_ALMB_Enable (RTC_TypeDef *RTCx)
Enable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_Disable (RTC_TypeDef *RTCx)
Disable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm B masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMask (RTC_TypeDef *RTCx)
Get the Alarm B masks.
__STATIC_INLINE void | LL_RTC_ALMB_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmB Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMB_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmB Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMB_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM B Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetDay (RTC_TypeDef *RTCx)
Get ALARM B Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM B Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM B Weekday.
__STATIC_INLINE void | LL_RTC_ALMB_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set ALARM B time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTimeFormat (RTC_TypeDef *RTCx)
Get ALARM B time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMB_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM B Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetHour (RTC_TypeDef *RTCx)
Get ALARM B Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM B Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMinute (RTC_TypeDef *RTCx)
Get ALARM B Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM B Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSecond (RTC_TypeDef *RTCx)
Get ALARM B Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm B Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm B Sub seconds value.
__STATIC_INLINE void | LL_RTC_TS_Enable (RTC_TypeDef *RTCx)
Enable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_Disable (RTC_TypeDef *RTCx)
Disable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_SetActiveEdge (RTC_TypeDef *RTCx, uint32_t Edge)
Set Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetActiveEdge (RTC_TypeDef *RTCx)
Get Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTimeFormat (RTC_TypeDef *RTCx)
Get Timestamp AM/PM notation (AM or 24-hour format)
__STATIC_INLINE uint32_t | LL_RTC_TS_GetHour (RTC_TypeDef *RTCx)
Get Timestamp Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMinute (RTC_TypeDef *RTCx)
Get Timestamp Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSecond (RTC_TypeDef *RTCx)
Get Timestamp Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTime (RTC_TypeDef *RTCx)
Get Timestamp time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetWeekDay (RTC_TypeDef *RTCx)
Get Timestamp Week day.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMonth (RTC_TypeDef *RTCx)
Get Timestamp Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDay (RTC_TypeDef *RTCx)
Get Timestamp Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDate (RTC_TypeDef *RTCx)
Get Timestamp date (WeekDay, Day and Month) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSubSecond (RTC_TypeDef *RTCx)
Get time-stamp sub second value.
__STATIC_INLINE void | LL_RTC_TS_EnableOnTamper (RTC_TypeDef *RTCx)
Activate timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TS_DisableOnTamper (RTC_TypeDef *RTCx)
Disable timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TAMPER_Enable (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable RTC_TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_Disable (RTC_TypeDef *RTCx, uint32_t Tamper)
Clear RTC_TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisablePullUp (RTC_TypeDef *RTCx)
Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
__STATIC_INLINE void | LL_RTC_TAMPER_EnablePullUp (RTC_TypeDef *RTCx)
Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
__STATIC_INLINE void | LL_RTC_TAMPER_SetPrecharge (RTC_TypeDef *RTCx, uint32_t Duration)
Set RTC_TAMPx precharge duration.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetPrecharge (RTC_TypeDef *RTCx)
Get RTC_TAMPx precharge duration.
__STATIC_INLINE void | LL_RTC_TAMPER_SetFilterCount (RTC_TypeDef *RTCx, uint32_t FilterCount)
Set RTC_TAMPx filter count.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetFilterCount (RTC_TypeDef *RTCx)
Get RTC_TAMPx filter count.
__STATIC_INLINE void | LL_RTC_TAMPER_SetSamplingFreq (RTC_TypeDef *RTCx, uint32_t SamplingFreq)
Set Tamper sampling frequency.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetSamplingFreq (RTC_TypeDef *RTCx)
Get Tamper sampling frequency.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableActiveLevel (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableActiveLevel (RTC_TypeDef *RTCx, uint32_t Tamper)
Disable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_WAKEUP_Enable (RTC_TypeDef *RTCx)
Enable Wakeup timer.
__STATIC_INLINE void | LL_RTC_WAKEUP_Disable (RTC_TypeDef *RTCx)
Disable Wakeup timer.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_IsEnabled (RTC_TypeDef *RTCx)
Check if Wakeup timer is enabled or not.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetClock (RTC_TypeDef *RTCx, uint32_t WakeupClock)
Select Wakeup clock.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetClock (RTC_TypeDef *RTCx)
Get Wakeup clock.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetAutoReload (RTC_TypeDef *RTCx, uint32_t Value)
Set Wakeup auto-reload value.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetAutoReload (RTC_TypeDef *RTCx)
Get Wakeup auto-reload value.
__STATIC_INLINE void | LL_RTC_BAK_SetRegister (RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified RTC Backup data register.
__STATIC_INLINE uint32_t | LL_RTC_BAK_GetRegister (RTC_TypeDef *RTCx, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
__STATIC_INLINE void | LL_RTC_CAL_SetOutputFreq (RTC_TypeDef *RTCx, uint32_t Frequency)
Set Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetOutputFreq (RTC_TypeDef *RTCx)
Get Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE void | LL_RTC_CAL_SetPulse (RTC_TypeDef *RTCx, uint32_t Pulse)
Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE uint32_t | LL_RTC_CAL_IsPulseInserted (RTC_TypeDef *RTCx)
Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE void | LL_RTC_CAL_SetPeriod (RTC_TypeDef *RTCx, uint32_t Period)
Set the calibration cycle period.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetPeriod (RTC_TypeDef *RTCx)
Get the calibration cycle period.
__STATIC_INLINE void | LL_RTC_CAL_SetMinus (RTC_TypeDef *RTCx, uint32_t CalibMinus)
Set Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetMinus (RTC_TypeDef *RTCx)
Get Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RECALP (RTC_TypeDef *RTCx)
Get Recalibration pending Flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3 (RTC_TypeDef *RTCx)
Get RTC_TAMP3 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2 (RTC_TypeDef *RTCx)
Get RTC_TAMP2 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1 (RTC_TypeDef *RTCx)
Get RTC_TAMP1 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOV (RTC_TypeDef *RTCx)
Get Time-stamp overflow flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TS (RTC_TypeDef *RTCx)
Get Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUT (RTC_TypeDef *RTCx)
Get Wakeup timer flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRB (RTC_TypeDef *RTCx)
Get Alarm B flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRA (RTC_TypeDef *RTCx)
Get Alarm A flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP3 (RTC_TypeDef *RTCx)
Clear RTC_TAMP3 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP2 (RTC_TypeDef *RTCx)
Clear RTC_TAMP2 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP1 (RTC_TypeDef *RTCx)
Clear RTC_TAMP1 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TSOV (RTC_TypeDef *RTCx)
Clear Time-stamp overflow flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TS (RTC_TypeDef *RTCx)
Clear Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_WUT (RTC_TypeDef *RTCx)
Clear Wakeup timer flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRB (RTC_TypeDef *RTCx)
Clear Alarm B flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRA (RTC_TypeDef *RTCx)
Clear Alarm A flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INIT (RTC_TypeDef *RTCx)
Get Initialization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RS (RTC_TypeDef *RTCx)
Get Registers synchronization flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_RS (RTC_TypeDef *RTCx)
Clear Registers synchronization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INITS (RTC_TypeDef *RTCx)
Get Initialization status flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_SHP (RTC_TypeDef *RTCx)
Get Shift operation pending flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTW (RTC_TypeDef *RTCx)
Get Wakeup timer write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBW (RTC_TypeDef *RTCx)
Get Alarm B write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAW (RTC_TypeDef *RTCx)
Get Alarm A write flag.
__STATIC_INLINE void | LL_RTC_EnableIT_TS (RTC_TypeDef *RTCx)
Enable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TS (RTC_TypeDef *RTCx)
Disable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_WUT (RTC_TypeDef *RTCx)
Enable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_WUT (RTC_TypeDef *RTCx)
Disable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRB (RTC_TypeDef *RTCx)
Enable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRB (RTC_TypeDef *RTCx)
Disable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRA (RTC_TypeDef *RTCx)
Enable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRA (RTC_TypeDef *RTCx)
Disable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP (RTC_TypeDef *RTCx)
Enable all Tamper Interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP (RTC_TypeDef *RTCx)
Disable all Tamper Interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TS (RTC_TypeDef *RTCx)
Check if Time-stamp interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_WUT (RTC_TypeDef *RTCx)
Check if Wakeup timer interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRB (RTC_TypeDef *RTCx)
Check if Alarm B interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRA (RTC_TypeDef *RTCx)
Check if Alarm A interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP (RTC_TypeDef *RTCx)
Check if all the TAMPER interrupts are enabled or not.
ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

Header file of RTC LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_rtc.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_spi.h File Reference

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Data Structures | Defines | Functions
stm32f3xx_ll_spi.h File Reference

Header file of SPI LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Data Structures

struct | LL_SPI_InitTypeDef
SPI Init structures definition. More...
struct | LL_I2S_InitTypeDef
I2S Init structure definition. More...

Defines

#define | LL_SPI_SR_RXNE SPI_SR_RXNE
#define | LL_SPI_SR_TXE SPI_SR_TXE
#define | LL_SPI_SR_BSY SPI_SR_BSY
#define | LL_SPI_SR_CRCERR SPI_SR_CRCERR
#define | LL_SPI_SR_MODF SPI_SR_MODF
#define | LL_SPI_SR_OVR SPI_SR_OVR
#define | LL_SPI_SR_FRE SPI_SR_FRE
#define | LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE
#define | LL_SPI_CR2_TXEIE SPI_CR2_TXEIE
#define | LL_SPI_CR2_ERRIE SPI_CR2_ERRIE
#define | LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | LL_SPI_MODE_SLAVE 0x00000000U
#define | LL_SPI_PROTOCOL_MOTOROLA 0x00000000U
#define | LL_SPI_PROTOCOL_TI (SPI_CR2_FRF)
#define | LL_SPI_PHASE_1EDGE 0x00000000U
#define | LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)
#define | LL_SPI_POLARITY_LOW 0x00000000U
#define | LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)
#define | LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U
#define | LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)
#define | LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)
#define | LL_SPI_MSB_FIRST 0x00000000U
#define | LL_SPI_FULL_DUPLEX 0x00000000U
#define | LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)
#define | LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)
#define | LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)
#define | LL_SPI_NSS_SOFT (SPI_CR1_SSM)
#define | LL_SPI_NSS_HARD_INPUT 0x00000000U
#define | LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))
#define | LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3)
#define | LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_CRCCALCULATION_DISABLE 0x00000000U
#define | LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)
#define | LL_SPI_CRC_8BIT 0x00000000U
#define | LL_SPI_CRC_16BIT (SPI_CR1_CRCL)
#define | LL_SPI_RX_FIFO_TH_HALF 0x00000000U
#define | LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH)
#define | LL_SPI_RX_FIFO_EMPTY 0x00000000U
#define | LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0)
#define | LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1)
#define | LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0)
#define | LL_SPI_TX_FIFO_EMPTY 0x00000000U
#define | LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0)
#define | LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1)
#define | LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0)
#define | LL_SPI_DMA_PARITY_EVEN 0x00000000U
#define | LL_SPI_DMA_PARITY_ODD 0x00000001U
#define | LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SPI register.
#define | LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SPI register.
#define | LL_I2S_SR_RXNE LL_SPI_SR_RXNE
#define | LL_I2S_SR_TXE LL_SPI_SR_TXE
#define | LL_I2S_SR_BSY LL_SPI_SR_BSY
#define | LL_I2S_SR_UDR SPI_SR_UDR
#define | LL_I2S_SR_OVR LL_SPI_SR_OVR
#define | LL_I2S_SR_FRE LL_SPI_SR_FRE
#define | LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE
#define | LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE
#define | LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE
#define | LL_I2S_DATAFORMAT_16B 0x00000000U
#define | LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define | LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
#define | LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)
#define | LL_I2S_POLARITY_LOW 0x00000000U
#define | LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)
#define | LL_I2S_STANDARD_PHILIPS 0x00000000U
#define | LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define | LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
#define | LL_I2S_MODE_SLAVE_TX 0x00000000U
#define | LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define | LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define | LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)
#define | LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U
#define | LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U)
#define | LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U
#define | LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE)
#define | LL_I2S_AUDIOFREQ_192K 192000U
#define | LL_I2S_AUDIOFREQ_96K 96000U
#define | LL_I2S_AUDIOFREQ_48K 48000U
#define | LL_I2S_AUDIOFREQ_44K 44100U
#define | LL_I2S_AUDIOFREQ_32K 32000U
#define | LL_I2S_AUDIOFREQ_22K 22050U
#define | LL_I2S_AUDIOFREQ_16K 16000U
#define | LL_I2S_AUDIOFREQ_11K 11025U
#define | LL_I2S_AUDIOFREQ_8K 8000U
#define | LL_I2S_AUDIOFREQ_DEFAULT 2U
#define | LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2S register.
#define | LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2S register.

Functions

__STATIC_INLINE void | LL_SPI_Enable (SPI_TypeDef *SPIx)
Enable SPI peripheral.
__STATIC_INLINE void | LL_SPI_Disable (SPI_TypeDef *SPIx)
Disable SPI peripheral.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabled (SPI_TypeDef *SPIx)
Check if SPI peripheral is enabled.
__STATIC_INLINE void | LL_SPI_SetMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set SPI operation mode to Master or Slave.
__STATIC_INLINE uint32_t | LL_SPI_GetMode (SPI_TypeDef *SPIx)
Get SPI operation mode (Master or Slave)
__STATIC_INLINE void | LL_SPI_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set serial protocol used.
__STATIC_INLINE uint32_t | LL_SPI_GetStandard (SPI_TypeDef *SPIx)
Get serial protocol used.
__STATIC_INLINE void | LL_SPI_SetClockPhase (SPI_TypeDef *SPIx, uint32_t ClockPhase)
Set clock phase.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPhase (SPI_TypeDef *SPIx)
Get clock phase.
__STATIC_INLINE void | LL_SPI_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set clock polarity.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPolarity (SPI_TypeDef *SPIx)
Get clock polarity.
__STATIC_INLINE void | LL_SPI_SetBaudRatePrescaler (SPI_TypeDef *SPIx, uint32_t BaudRate)
Set baud rate prescaler.
__STATIC_INLINE uint32_t | LL_SPI_GetBaudRatePrescaler (SPI_TypeDef *SPIx)
Get baud rate prescaler.
__STATIC_INLINE void | LL_SPI_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder)
Set transfer bit order.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferBitOrder (SPI_TypeDef *SPIx)
Get transfer bit order.
__STATIC_INLINE void | LL_SPI_SetTransferDirection (SPI_TypeDef *SPIx, uint32_t TransferDirection)
Set transfer direction mode.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferDirection (SPI_TypeDef *SPIx)
Get transfer direction mode.
__STATIC_INLINE void | LL_SPI_SetDataWidth (SPI_TypeDef *SPIx, uint32_t DataWidth)
Set frame data width.
__STATIC_INLINE uint32_t | LL_SPI_GetDataWidth (SPI_TypeDef *SPIx)
Get frame data width.
__STATIC_INLINE void | LL_SPI_SetRxFIFOThreshold (SPI_TypeDef *SPIx, uint32_t Threshold)
Set threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOThreshold (SPI_TypeDef *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE void | LL_SPI_EnableCRC (SPI_TypeDef *SPIx)
Enable CRC.
__STATIC_INLINE void | LL_SPI_DisableCRC (SPI_TypeDef *SPIx)
Disable CRC.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledCRC (SPI_TypeDef *SPIx)
Check if CRC is enabled.
__STATIC_INLINE void | LL_SPI_SetCRCWidth (SPI_TypeDef *SPIx, uint32_t CRCLength)
Set CRC Length.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCWidth (SPI_TypeDef *SPIx)
Get CRC Length.
__STATIC_INLINE void | LL_SPI_SetCRCNext (SPI_TypeDef *SPIx)
Set CRCNext to transfer CRC on the line.
__STATIC_INLINE void | LL_SPI_SetCRCPolynomial (SPI_TypeDef *SPIx, uint32_t CRCPoly)
Set polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Get polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetRxCRC (SPI_TypeDef *SPIx)
Get Rx CRC.
__STATIC_INLINE uint32_t | LL_SPI_GetTxCRC (SPI_TypeDef *SPIx)
Get Tx CRC.
__STATIC_INLINE void | LL_SPI_SetNSSMode (SPI_TypeDef *SPIx, uint32_t NSS)
Set NSS mode.
__STATIC_INLINE uint32_t | LL_SPI_GetNSSMode (SPI_TypeDef *SPIx)
Get NSS mode.
__STATIC_INLINE void | LL_SPI_EnableNSSPulseMgt (SPI_TypeDef *SPIx)
Enable NSS pulse management.
__STATIC_INLINE void | LL_SPI_DisableNSSPulseMgt (SPI_TypeDef *SPIx)
Disable NSS pulse management.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledNSSPulse (SPI_TypeDef *SPIx)
Check if NSS pulse is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_CRCERR (SPI_TypeDef *SPIx)
Get CRC error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_MODF (SPI_TypeDef *SPIx)
Get mode fault error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO reception Level.
__STATIC_INLINE uint32_t | LL_SPI_GetTxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO Transmission Level.
__STATIC_INLINE void | LL_SPI_ClearFlag_CRCERR (SPI_TypeDef *SPIx)
Clear CRC error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_MODF (SPI_TypeDef *SPIx)
Clear mode fault error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.
__STATIC_INLINE void | LL_SPI_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty interrupt.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer not empty interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE void | LL_SPI_SetDMAParity_RX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA reception.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_RX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA reception.
__STATIC_INLINE void | LL_SPI_SetDMAParity_TX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_TX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_DMA_GetRegAddr (SPI_TypeDef *SPIx)
Get the data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_SPI_ReceiveData8 (SPI_TypeDef *SPIx)
Read 8-Bits in the data register.
__STATIC_INLINE uint16_t | LL_SPI_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData8 (SPI_TypeDef *SPIx, uint8_t TxData)
Write 8-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in the data register.
ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.
__STATIC_INLINE void | LL_I2S_Enable (SPI_TypeDef *SPIx)
Select I2S mode and Enable I2S peripheral.
__STATIC_INLINE void | LL_I2S_Disable (SPI_TypeDef *SPIx)
Disable I2S peripheral.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabled (SPI_TypeDef *SPIx)
Check if I2S peripheral is enabled.
__STATIC_INLINE void | LL_I2S_SetDataFormat (SPI_TypeDef *SPIx, uint32_t DataFormat)
Set I2S data frame length.
__STATIC_INLINE uint32_t | LL_I2S_GetDataFormat (SPI_TypeDef *SPIx)
Get I2S data frame length.
__STATIC_INLINE void | LL_I2S_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set I2S clock polarity.
__STATIC_INLINE uint32_t | LL_I2S_GetClockPolarity (SPI_TypeDef *SPIx)
Get I2S clock polarity.
__STATIC_INLINE void | LL_I2S_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set I2S standard protocol.
__STATIC_INLINE uint32_t | LL_I2S_GetStandard (SPI_TypeDef *SPIx)
Get I2S standard protocol.
__STATIC_INLINE void | LL_I2S_SetTransferMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set I2S transfer mode.
__STATIC_INLINE uint32_t | LL_I2S_GetTransferMode (SPI_TypeDef *SPIx)
Get I2S transfer mode.
__STATIC_INLINE void | LL_I2S_SetPrescalerLinear (SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
Set I2S linear prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerLinear (SPI_TypeDef *SPIx)
Get I2S linear prescaler.
__STATIC_INLINE void | LL_I2S_SetPrescalerParity (SPI_TypeDef *SPIx, uint32_t PrescalerParity)
Set I2S parity prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerParity (SPI_TypeDef *SPIx)
Get I2S parity prescaler.
__STATIC_INLINE void | LL_I2S_EnableMasterClock (SPI_TypeDef *SPIx)
Enable the master clock ouput (Pin MCK)
__STATIC_INLINE void | LL_I2S_DisableMasterClock (SPI_TypeDef *SPIx)
Disable the master clock ouput (Pin MCK)
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledMasterClock (SPI_TypeDef *SPIx)
Check if the master clock ouput (Pin MCK) is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_UDR (SPI_TypeDef *SPIx)
Get underrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_CHSIDE (SPI_TypeDef *SPIx)
Get channel side flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_UDR (SPI_TypeDef *SPIx)
Clear underrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.
__STATIC_INLINE void | LL_I2S_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error IT.
__STATIC_INLINE void | LL_I2S_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty IT.
__STATIC_INLINE void | LL_I2S_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty IT.
__STATIC_INLINE void | LL_I2S_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error IT.
__STATIC_INLINE void | LL_I2S_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty IT.
__STATIC_INLINE void | LL_I2S_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty IT.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if ERR IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if RXNE IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if TXE IT is enabled.
__STATIC_INLINE void | LL_I2S_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_I2S_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE uint16_t | LL_I2S_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in data register.
__STATIC_INLINE void | LL_I2S_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in data register.
ErrorStatus | LL_I2S_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI/I2S registers to their default reset values.
ErrorStatus | LL_I2S_Init (SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
void | LL_I2S_StructInit (LL_I2S_InitTypeDef *I2S_InitStruct)
Set each LL_I2S_InitTypeDef field to default value.
void | LL_I2S_ConfigPrescaler (SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
Set linear and parity prescaler.

Detailed Description

Header file of SPI LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_spi.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_system.h File Reference

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Defines | Functions
stm32f3xx_ll_system.h File Reference

Header file of SYSTEM LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Defines

#define | SYSCFG_OFFSET_CFGR1 0x00000000U
#define | SYSCFG_OFFSET_CFGR3 0x00000050U
#define | SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)
#define | LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /* Main Flash memory mapped at 0x00000000 */
#define | LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /* System Flash memory mapped at 0x00000000 */
#define | LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /* Embedded SRAM mapped at 0x00000000 */
#define | LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
#define | LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP)
#define | LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U)
#define | LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
#define | LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
#define | LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
#define | LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | (uint32_t)0x00000000U)
#define | LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP)
#define | LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | (uint32_t)0x00000000U)
#define | LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP)
#define | LL_SYSCFG_TIM6_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
#define | LL_SYSCFG_TIM6_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP)
#define | LL_SYSCFG_TIM7_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U)
#define | LL_SYSCFG_TIM7_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
#define | LL_SYSCFG_TIM18_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
#define | LL_SYSCFG_TIM18_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | LL_SYSCFG_EXTI_PORTA (uint32_t)0U
#define | LL_SYSCFG_EXTI_PORTB (uint32_t)1U
#define | LL_SYSCFG_EXTI_PORTC (uint32_t)2U
#define | LL_SYSCFG_EXTI_PORTD (uint32_t)3U
#define | LL_SYSCFG_EXTI_PORTE (uint32_t)4U
#define | LL_SYSCFG_EXTI_PORTF (uint32_t)5U
#define | LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* EXTI_POSITION_0 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* EXTI_POSITION_4 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* EXTI_POSITION_8 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* EXTI_POSITION_12 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* EXTI_POSITION_0 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* EXTI_POSITION_4 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* EXTI_POSITION_8 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* EXTI_POSITION_12 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* EXTI_POSITION_0 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* EXTI_POSITION_4 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* EXTI_POSITION_8 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* EXTI_POSITION_12 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* EXTI_POSITION_0 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* EXTI_POSITION_4 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* EXTI_POSITION_8 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* EXTI_POSITION_12 | EXTICR[3] */
#define | LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK
#define | LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK
#define | LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK
#define | LL_DBGMCU_TRACE_NONE 0x00000000U
#define | LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN
#define | LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)
#define | LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM18_STOP DBGMCU_APB1_FZ_DBG_TIM18_STOP
#define | LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP
#define | LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT
#define | LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT
#define | LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM19_STOP DBGMCU_APB2_FZ_DBG_TIM19_STOP
#define | LL_FLASH_LATENCY_0 0x00000000U
#define | LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0
#define | LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1

Functions

__STATIC_INLINE void | LL_SYSCFG_SetRemapMemory (uint32_t Memory)
Set memory mapping at address 0x00000000.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetRemapMemory (void)
Get memory mapping at address 0x00000000.
__STATIC_INLINE void | LL_SYSCFG_SetRemapDMA_DAC (uint32_t Remap)
Set DMA request remapping bits for DAC.
__STATIC_INLINE void | LL_SYSCFG_SetRemapDMA_TIM (uint32_t Remap)
Set DMA request remapping bits for TIM.
__STATIC_INLINE void | LL_SYSCFG_EnableVBATMonitoring (void)
Enable VBAT monitoring (to enable the power switch to deliver VBAT voltage on ADC channel 18 input)
__STATIC_INLINE void | LL_SYSCFG_DisableVBATMonitoring (void)
Disable VBAT monitoring.
__STATIC_INLINE void | LL_SYSCFG_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IOC (void)
Enable Floating Point Unit Invalid operation Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_DZC (void)
Enable Floating Point Unit Divide-by-zero Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_UFC (void)
Enable Floating Point Unit Underflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_OFC (void)
Enable Floating Point Unit Overflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IDC (void)
Enable Floating Point Unit Input denormal Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IXC (void)
Enable Floating Point Unit Inexact Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IOC (void)
Disable Floating Point Unit Invalid operation Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_DZC (void)
Disable Floating Point Unit Divide-by-zero Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_UFC (void)
Disable Floating Point Unit Underflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_OFC (void)
Disable Floating Point Unit Overflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IDC (void)
Disable Floating Point Unit Input denormal Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IXC (void)
Disable Floating Point Unit Inexact Interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IOC (void)
Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_DZC (void)
Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_UFC (void)
Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_OFC (void)
Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IDC (void)
Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IXC (void)
Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
__STATIC_INLINE void | LL_SYSCFG_SetEXTISource (uint32_t Port, uint32_t Line)
Configure source input for the EXTI external interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetEXTISource (uint32_t Line)
Get the configured defined for specific EXTI Line.
__STATIC_INLINE void | LL_SYSCFG_SetTIMBreakInputs (uint32_t Break)
Set connections to TIMx Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetTIMBreakInputs (void)
Get connections to TIMx Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_SP (void)
Check if SRAM parity error detected.
__STATIC_INLINE void | LL_SYSCFG_ClearFlag_SP (void)
Clear SRAM parity error flag.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetDeviceID (void)
Return the device identifier.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetRevisionID (void)
Return the device revision identifier.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_SetTracePinAssignment (uint32_t PinAssignment)
Set Trace pin assignment control.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetTracePinAssignment (void)
Get Trace pin assignment control.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB2 peripherals.
__STATIC_INLINE void | LL_FLASH_SetLatency (uint32_t Latency)
Set FLASH Latency.
__STATIC_INLINE uint32_t | LL_FLASH_GetLatency (void)
Get FLASH Latency.
__STATIC_INLINE void | LL_FLASH_EnablePrefetch (void)
Enable Prefetch.
__STATIC_INLINE void | LL_FLASH_DisablePrefetch (void)
Disable Prefetch.
__STATIC_INLINE uint32_t | LL_FLASH_IsPrefetchEnabled (void)
Check if Prefetch buffer is enabled.

Detailed Description

Header file of SYSTEM LL module.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL SYSTEM driver contains a set of generic APIs that can be
    used by user:
      (+) Some of the FLASH features need to be handled in the SYSTEM file.
      (+) Access to DBGCMU registers
      (+) Access to SYSCFG registers
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_system.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_tim.h File Reference

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Data Structures | Defines | Functions | Variables
stm32f3xx_ll_tim.h File Reference

Header file of TIM LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Data Structures

struct | LL_TIM_InitTypeDef
TIM Time Base configuration structure definition. More...
struct | LL_TIM_OC_InitTypeDef
TIM Output Compare configuration structure definition. More...
struct | LL_TIM_IC_InitTypeDef
TIM Input Capture configuration structure definition. More...
struct | LL_TIM_ENCODER_InitTypeDef
TIM Encoder interface configuration structure definition. More...
struct | LL_TIM_HALLSENSOR_InitTypeDef
TIM Hall sensor interface configuration structure definition. More...
struct | LL_TIM_BDTR_InitTypeDef
BDTR (Break and Dead Time) structure definition. More...

Defines

#define | TIMx_OR_RMP_SHIFT 16U
#define | TIMx_OR_RMP_MASK 0x0000FFFFU
#define | TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
#define | TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
#define | DT_DELAY_1 ((uint8_t)0x7FU)
#define | DT_DELAY_2 ((uint8_t)0x3FU)
#define | DT_DELAY_3 ((uint8_t)0x1FU)
#define | DT_DELAY_4 ((uint8_t)0x1FU)
#define | DT_RANGE_1 ((uint8_t)0x00U)
#define | DT_RANGE_2 ((uint8_t)0x80U)
#define | DT_RANGE_3 ((uint8_t)0xC0U)
#define | DT_RANGE_4 ((uint8_t)0xE0U)
#define | TIM_GET_CHANNEL_INDEX(__CHANNEL__)
Convert channel id into channel index.
#define | TIM_CALC_DTS(__TIMCLK__, __CKD__)
Calculate the deadtime sampling period(in ps).
#define | LL_TIM_SR_UIF TIM_SR_UIF
#define | LL_TIM_SR_CC1IF TIM_SR_CC1IF
#define | LL_TIM_SR_CC2IF TIM_SR_CC2IF
#define | LL_TIM_SR_CC3IF TIM_SR_CC3IF
#define | LL_TIM_SR_CC4IF TIM_SR_CC4IF
#define | LL_TIM_SR_COMIF TIM_SR_COMIF
#define | LL_TIM_SR_TIF TIM_SR_TIF
#define | LL_TIM_SR_BIF TIM_SR_BIF
#define | LL_TIM_SR_B2IF TIM_SR_B2IF
#define | LL_TIM_SR_CC1OF TIM_SR_CC1OF
#define | LL_TIM_SR_CC2OF TIM_SR_CC2OF
#define | LL_TIM_SR_CC3OF TIM_SR_CC3OF
#define | LL_TIM_SR_CC4OF TIM_SR_CC4OF
#define | LL_TIM_BREAK_DISABLE 0x00000000U
#define | LL_TIM_BREAK_ENABLE TIM_BDTR_BKE
#define | LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE
#define | LL_TIM_DIER_UIE TIM_DIER_UIE
#define | LL_TIM_DIER_CC1IE TIM_DIER_CC1IE
#define | LL_TIM_DIER_CC2IE TIM_DIER_CC2IE
#define | LL_TIM_DIER_CC3IE TIM_DIER_CC3IE
#define | LL_TIM_DIER_CC4IE TIM_DIER_CC4IE
#define | LL_TIM_DIER_COMIE TIM_DIER_COMIE
#define | LL_TIM_DIER_TIE TIM_DIER_TIE
#define | LL_TIM_DIER_BIE TIM_DIER_BIE
#define | LL_TIM_UPDATESOURCE_REGULAR 0x00000000U
#define | LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS
#define | LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM
#define | LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U
#define | LL_TIM_COUNTERMODE_UP 0x00000000U
#define | LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0
#define | LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1
#define | LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS
#define | LL_TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
#define | LL_TIM_COUNTERDIRECTION_UP 0x00000000U
#define | LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR
#define | LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U
#define | LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS
#define | LL_TIM_CCDMAREQUEST_CC 0x00000000U
#define | LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS
#define | LL_TIM_LOCKLEVEL_OFF 0x00000000U
#define | LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
#define | LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E
#define | LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE
#define | LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E
#define | LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE
#define | LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E
#define | LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE
#define | LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E
#define | LL_TIM_OCSTATE_DISABLE 0x00000000U
#define | LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E
#define | LL_TIM_OCMODE_FROZEN 0x00000000U
#define | LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCPOLARITY_HIGH 0x00000000U
#define | LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P
#define | LL_TIM_OCIDLESTATE_LOW 0x00000000U
#define | LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1
#define | LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)
#define | LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)
#define | LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)
#define | LL_TIM_ICPSC_DIV1 0x00000000U
#define | LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)
#define | LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)
#define | LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)
#define | LL_TIM_IC_FILTER_FDIV1 0x00000000U
#define | LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)
#define | LL_TIM_IC_POLARITY_RISING 0x00000000U
#define | LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P
#define | LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
#define | LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U
#define | LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE
#define | LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0
#define | LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1
#define | LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_TRGO_RESET 0x00000000U
#define | LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_SLAVEMODE_DISABLED 0x00000000U
#define | LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | LL_TIM_TS_ITR0 0x00000000U
#define | LL_TIM_TS_ITR1 TIM_SMCR_TS_0
#define | LL_TIM_TS_ITR2 TIM_SMCR_TS_1
#define | LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)
#define | LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U
#define | LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP
#define | LL_TIM_ETR_PRESCALER_DIV1 0x00000000U
#define | LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS
#define | LL_TIM_ETR_FILTER_FDIV1 0x00000000U
#define | LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0
#define | LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1
#define | LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2
#define | LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3
#define | LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)
#define | LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF
#define | LL_TIM_BREAK_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP
#define | LL_TIM_OSSI_DISABLE 0x00000000U
#define | LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI
#define | LL_TIM_OSSR_DISABLE 0x00000000U
#define | LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR
#define | LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U
#define | LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0
#define | LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1
#define | LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2
#define | LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3
#define | LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4
#define | LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U
#define | LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0
#define | LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1
#define | LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2
#define | LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3
#define | LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)
#define | LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4
#define | LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)
#define | LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK)
#define | LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR_TI1_RMP_1 | TIM16_OR_RMP_MASK)
#define | LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR_TI1_RMP_1 | TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK)
#define | LL_TIM_TIM14_TI1_RMP_GPIO TIM14_OR_RMP_MASK
#define | LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 | TIM14_OR_RMP_MASK)
#define | LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK)
#define | LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 | TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK)
#define | LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in TIM register.
#define | LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in TIM register.
#define | __LL_TIM_GETFLAG_UIFCPY(__CNT__) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
HELPER macro retrieving the UIFCPY flag from the counter value.
#define | __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)
HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
#define | __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
#define | __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
#define | __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
#define | __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
HELPER macro retrieving the ratio of the input capture prescaler.

Functions

__STATIC_INLINE void | LL_TIM_EnableCounter (TIM_TypeDef *TIMx)
Enable timer counter.
__STATIC_INLINE void | LL_TIM_DisableCounter (TIM_TypeDef *TIMx)
Disable timer counter.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledCounter (TIM_TypeDef *TIMx)
Indicates whether the timer counter is enabled.
__STATIC_INLINE void | LL_TIM_EnableUpdateEvent (TIM_TypeDef *TIMx)
Enable update event generation.
__STATIC_INLINE void | LL_TIM_DisableUpdateEvent (TIM_TypeDef *TIMx)
Disable update event generation.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledUpdateEvent (TIM_TypeDef *TIMx)
Indicates whether update event generation is enabled.
__STATIC_INLINE void | LL_TIM_SetUpdateSource (TIM_TypeDef *TIMx, uint32_t UpdateSource)
Set update event source.
__STATIC_INLINE uint32_t | LL_TIM_GetUpdateSource (TIM_TypeDef *TIMx)
Get actual event update source.
__STATIC_INLINE void | LL_TIM_SetOnePulseMode (TIM_TypeDef *TIMx, uint32_t OnePulseMode)
Set one pulse mode (one shot v.s.
__STATIC_INLINE uint32_t | LL_TIM_GetOnePulseMode (TIM_TypeDef *TIMx)
Get actual one pulse mode.
__STATIC_INLINE void | LL_TIM_SetCounterMode (TIM_TypeDef *TIMx, uint32_t CounterMode)
Set the timer counter counting mode.
__STATIC_INLINE uint32_t | LL_TIM_GetCounterMode (TIM_TypeDef *TIMx)
Get actual counter mode.
__STATIC_INLINE void | LL_TIM_EnableARRPreload (TIM_TypeDef *TIMx)
Enable auto-reload (ARR) preload.
__STATIC_INLINE void | LL_TIM_DisableARRPreload (TIM_TypeDef *TIMx)
Disable auto-reload (ARR) preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledARRPreload (TIM_TypeDef *TIMx)
Indicates whether auto-reload (ARR) preload is enabled.
__STATIC_INLINE void | LL_TIM_SetClockDivision (TIM_TypeDef *TIMx, uint32_t ClockDivision)
Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE uint32_t | LL_TIM_GetClockDivision (TIM_TypeDef *TIMx)
Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE void | LL_TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Set the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetCounter (TIM_TypeDef *TIMx)
Get the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetDirection (TIM_TypeDef *TIMx)
Get the current direction of the counter.
__STATIC_INLINE void | LL_TIM_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Prescaler)
Set the prescaler value.
__STATIC_INLINE uint32_t | LL_TIM_GetPrescaler (TIM_TypeDef *TIMx)
Get the prescaler value.
__STATIC_INLINE void | LL_TIM_SetAutoReload (TIM_TypeDef *TIMx, uint32_t AutoReload)
Set the auto-reload value.
__STATIC_INLINE uint32_t | LL_TIM_GetAutoReload (TIM_TypeDef *TIMx)
Get the auto-reload value.
__STATIC_INLINE void | LL_TIM_SetRepetitionCounter (TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
Set the repetition counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetRepetitionCounter (TIM_TypeDef *TIMx)
Get the repetition counter value.
__STATIC_INLINE void | LL_TIM_CC_EnablePreload (TIM_TypeDef *TIMx)
Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_DisablePreload (TIM_TypeDef *TIMx)
Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_SetUpdate (TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
__STATIC_INLINE void | LL_TIM_CC_SetDMAReqTrigger (TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
Set the trigger of the capture/compare DMA request.
__STATIC_INLINE uint32_t | LL_TIM_CC_GetDMAReqTrigger (TIM_TypeDef *TIMx)
Get actual trigger of the capture/compare DMA request.
__STATIC_INLINE void | LL_TIM_CC_SetLockLevel (TIM_TypeDef *TIMx, uint32_t LockLevel)
Set the lock level to freeze the configuration of several capture/compare parameters.
__STATIC_INLINE void | LL_TIM_CC_EnableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Enable capture/compare channels.
__STATIC_INLINE void | LL_TIM_CC_DisableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Disable capture/compare channels.
__STATIC_INLINE uint32_t | LL_TIM_CC_IsEnabledChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Indicate whether channel(s) is(are) enabled.
__STATIC_INLINE void | LL_TIM_OC_ConfigOutput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetMode (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetMode (TIM_TypeDef *TIMx, uint32_t Channel)
Get the output compare mode of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
Set the polarity of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the polarity of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetIdleState (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
Set the IDLE state of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetIdleState (TIM_TypeDef *TIMx, uint32_t Channel)
Get the IDLE state of an output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Enable fast mode for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Disable fast mode for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledFast (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether fast mode is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Enable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Disable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledPreload (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Enable clearing the output channel on an external event.
__STATIC_INLINE void | LL_TIM_OC_DisableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Disable clearing the output channel on an external event.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledClear (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates clearing the output channel on an external event is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_SetDeadTime (TIM_TypeDef *TIMx, uint32_t DeadTime)
Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH1 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 1 (TIMx_CCR1).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH2 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 2 (TIMx_CCR2).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH3 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 3 (TIMx_CCR3).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH4 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 4 (TIMx_CCR4).
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH1 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR1) set for output channel 1.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH2 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR2) set for output channel 2.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH3 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR3) set for output channel 3.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH4 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR4) set for output channel 4.
__STATIC_INLINE void | LL_TIM_IC_Config (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure input channel.
__STATIC_INLINE void | LL_TIM_IC_SetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
Set the active input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current active input.
__STATIC_INLINE void | LL_TIM_IC_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
Set the prescaler of input channel.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current prescaler value acting on an input channel.
__STATIC_INLINE void | LL_TIM_IC_SetFilter (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
Set the input filter duration.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetFilter (TIM_TypeDef *TIMx, uint32_t Channel)
Get the input filter duration.
__STATIC_INLINE void | LL_TIM_IC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
Set the input channel polarity.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current input channel polarity.
__STATIC_INLINE void | LL_TIM_IC_EnableXORCombination (TIM_TypeDef *TIMx)
Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
__STATIC_INLINE void | LL_TIM_IC_DisableXORCombination (TIM_TypeDef *TIMx)
Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_IsEnabledXORCombination (TIM_TypeDef *TIMx)
Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH1 (TIM_TypeDef *TIMx)
Get captured value for input channel 1.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH2 (TIM_TypeDef *TIMx)
Get captured value for input channel 2.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH3 (TIM_TypeDef *TIMx)
Get captured value for input channel 3.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH4 (TIM_TypeDef *TIMx)
Get captured value for input channel 4.
__STATIC_INLINE void | LL_TIM_EnableExternalClock (TIM_TypeDef *TIMx)
Enable external clock mode 2.
__STATIC_INLINE void | LL_TIM_DisableExternalClock (TIM_TypeDef *TIMx)
Disable external clock mode 2.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledExternalClock (TIM_TypeDef *TIMx)
Indicate whether external clock mode 2 is enabled.
__STATIC_INLINE void | LL_TIM_SetClockSource (TIM_TypeDef *TIMx, uint32_t ClockSource)
Set the clock source of the counter clock.
__STATIC_INLINE void | LL_TIM_SetEncoderMode (TIM_TypeDef *TIMx, uint32_t EncoderMode)
Set the encoder interface mode.
__STATIC_INLINE void | LL_TIM_SetTriggerOutput (TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
Set the trigger output (TRGO) used for timer synchronization .
__STATIC_INLINE void | LL_TIM_SetSlaveMode (TIM_TypeDef *TIMx, uint32_t SlaveMode)
Set the synchronization mode of a slave timer.
__STATIC_INLINE void | LL_TIM_SetTriggerInput (TIM_TypeDef *TIMx, uint32_t TriggerInput)
Set the selects the trigger input to be used to synchronize the counter.
__STATIC_INLINE void | LL_TIM_EnableMasterSlaveMode (TIM_TypeDef *TIMx)
Enable the Master/Slave mode.
__STATIC_INLINE void | LL_TIM_DisableMasterSlaveMode (TIM_TypeDef *TIMx)
Disable the Master/Slave mode.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledMasterSlaveMode (TIM_TypeDef *TIMx)
Indicates whether the Master/Slave mode is enabled.
__STATIC_INLINE void | LL_TIM_ConfigETR (TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
Configure the external trigger (ETR) input.
__STATIC_INLINE void | LL_TIM_EnableBRK (TIM_TypeDef *TIMx)
Enable the break function.
__STATIC_INLINE void | LL_TIM_DisableBRK (TIM_TypeDef *TIMx)
Disable the break function.
__STATIC_INLINE void | LL_TIM_ConfigBRK (TIM_TypeDef *TIMx, uint32_t BreakPolarity)
Configure the break input.
__STATIC_INLINE void | LL_TIM_SetOffStates (TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
Select the outputs off state (enabled v.s.
__STATIC_INLINE void | LL_TIM_EnableAutomaticOutput (TIM_TypeDef *TIMx)
Enable automatic output (MOE can be set by software or automatically when a break input is active).
__STATIC_INLINE void | LL_TIM_DisableAutomaticOutput (TIM_TypeDef *TIMx)
Disable automatic output (MOE can be set only by software).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAutomaticOutput (TIM_TypeDef *TIMx)
Indicate whether automatic output is enabled.
__STATIC_INLINE void | LL_TIM_EnableAllOutputs (TIM_TypeDef *TIMx)
Enable the outputs (set the MOE bit in TIMx_BDTR register).
__STATIC_INLINE void | LL_TIM_DisableAllOutputs (TIM_TypeDef *TIMx)
Disable the outputs (reset the MOE bit in TIMx_BDTR register).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAllOutputs (TIM_TypeDef *TIMx)
Indicates whether outputs are enabled.
__STATIC_INLINE void | LL_TIM_ConfigDMABurst (TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
Configures the timer DMA burst feature.
__STATIC_INLINE void | LL_TIM_SetRemap (TIM_TypeDef *TIMx, uint32_t Remap)
Remap TIM inputs (input channel, internal/external triggers).
__STATIC_INLINE void | LL_TIM_ClearFlag_UPDATE (TIM_TypeDef *TIMx)
Clear the update interrupt flag (UIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_UPDATE (TIM_TypeDef *TIMx)
Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 interrupt flag (CC1F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 interrupt flag (CC2F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 interrupt flag (CC3F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 interrupt flag (CC4F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_COM (TIM_TypeDef *TIMx)
Clear the commutation interrupt flag (COMIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_COM (TIM_TypeDef *TIMx)
Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_TRIG (TIM_TypeDef *TIMx)
Clear the trigger interrupt flag (TIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_TRIG (TIM_TypeDef *TIMx)
Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK (TIM_TypeDef *TIMx)
Clear the break interrupt flag (BIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK (TIM_TypeDef *TIMx)
Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_EnableIT_UPDATE (TIM_TypeDef *TIMx)
Enable update interrupt (UIE).
__STATIC_INLINE void | LL_TIM_DisableIT_UPDATE (TIM_TypeDef *TIMx)
Disable update interrupt (UIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update interrupt (UIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_COM (TIM_TypeDef *TIMx)
Enable commutation interrupt (COMIE).
__STATIC_INLINE void | LL_TIM_DisableIT_COM (TIM_TypeDef *TIMx)
Disable commutation interrupt (COMIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation interrupt (COMIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TIE).
__STATIC_INLINE void | LL_TIM_DisableIT_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_BRK (TIM_TypeDef *TIMx)
Enable break interrupt (BIE).
__STATIC_INLINE void | LL_TIM_DisableIT_BRK (TIM_TypeDef *TIMx)
Disable break interrupt (BIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_BRK (TIM_TypeDef *TIMx)
Indicates whether the break interrupt (BIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Enable update DMA request (UDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Disable update DMA request (UDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update DMA request (UDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_COM (TIM_TypeDef *TIMx)
Enable commutation DMA request (COMDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_COM (TIM_TypeDef *TIMx)
Disable commutation DMA request (COMDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation DMA request (COMDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TDE) is enabled.
__STATIC_INLINE void | LL_TIM_GenerateEvent_UPDATE (TIM_TypeDef *TIMx)
Generate an update event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC1 (TIM_TypeDef *TIMx)
Generate Capture/Compare 1 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC2 (TIM_TypeDef *TIMx)
Generate Capture/Compare 2 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC3 (TIM_TypeDef *TIMx)
Generate Capture/Compare 3 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC4 (TIM_TypeDef *TIMx)
Generate Capture/Compare 4 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_COM (TIM_TypeDef *TIMx)
Generate commutation event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_TRIG (TIM_TypeDef *TIMx)
Generate trigger event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK (TIM_TypeDef *TIMx)
Generate break event.
ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.

Variables

static const uint8_t | OFFSET_TAB_CCMRx []
static const uint8_t | SHIFT_TAB_OCxx []
static const uint8_t | SHIFT_TAB_ICxx []
static const uint8_t | SHIFT_TAB_CCxP []
static const uint8_t | SHIFT_TAB_OISx []

Detailed Description

Header file of TIM LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_tim.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_usart.h File Reference

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Data Structures | Defines | Functions
stm32f3xx_ll_usart.h File Reference

Header file of USART LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Data Structures

struct | LL_USART_InitTypeDef
LL USART Init Structure definition. More...
struct | LL_USART_ClockInitTypeDef
LL USART Clock Init Structure definition. More...

Defines

#define | LL_USART_ICR_PECF USART_ICR_PECF
#define | LL_USART_ICR_FECF USART_ICR_FECF
#define | LL_USART_ICR_NCF USART_ICR_NCF
#define | LL_USART_ICR_ORECF USART_ICR_ORECF
#define | LL_USART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_USART_ICR_TCCF USART_ICR_TCCF
#define | LL_USART_ICR_LBDCF USART_ICR_LBDCF
#define | LL_USART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_USART_ICR_RTOCF USART_ICR_RTOCF
#define | LL_USART_ICR_EOBCF USART_ICR_EOBCF
#define | LL_USART_ICR_CMCF USART_ICR_CMCF
#define | LL_USART_ICR_WUCF USART_ICR_WUCF
#define | LL_USART_ISR_PE USART_ISR_PE
#define | LL_USART_ISR_FE USART_ISR_FE
#define | LL_USART_ISR_NE USART_ISR_NE
#define | LL_USART_ISR_ORE USART_ISR_ORE
#define | LL_USART_ISR_IDLE USART_ISR_IDLE
#define | LL_USART_ISR_RXNE USART_ISR_RXNE
#define | LL_USART_ISR_TC USART_ISR_TC
#define | LL_USART_ISR_TXE USART_ISR_TXE
#define | LL_USART_ISR_LBDF USART_ISR_LBDF
#define | LL_USART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_USART_ISR_CTS USART_ISR_CTS
#define | LL_USART_ISR_RTOF USART_ISR_RTOF
#define | LL_USART_ISR_EOBF USART_ISR_EOBF
#define | LL_USART_ISR_ABRE USART_ISR_ABRE
#define | LL_USART_ISR_ABRF USART_ISR_ABRF
#define | LL_USART_ISR_BUSY USART_ISR_BUSY
#define | LL_USART_ISR_CMF USART_ISR_CMF
#define | LL_USART_ISR_SBKF USART_ISR_SBKF
#define | LL_USART_ISR_RWU USART_ISR_RWU
#define | LL_USART_ISR_WUF USART_ISR_WUF
#define | LL_USART_ISR_TEACK USART_ISR_TEACK
#define | LL_USART_ISR_REACK USART_ISR_REACK
#define | LL_USART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_USART_CR1_RXNEIE USART_CR1_RXNEIE
#define | LL_USART_CR1_TCIE USART_CR1_TCIE
#define | LL_USART_CR1_TXEIE USART_CR1_TXEIE
#define | LL_USART_CR1_PEIE USART_CR1_PEIE
#define | LL_USART_CR1_CMIE USART_CR1_CMIE
#define | LL_USART_CR1_RTOIE USART_CR1_RTOIE
#define | LL_USART_CR1_EOBIE USART_CR1_EOBIE
#define | LL_USART_CR2_LBDIE USART_CR2_LBDIE
#define | LL_USART_CR3_EIE USART_CR3_EIE
#define | LL_USART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_USART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_USART_DIRECTION_NONE 0x00000000U
#define | LL_USART_DIRECTION_RX USART_CR1_RE
#define | LL_USART_DIRECTION_TX USART_CR1_TE
#define | LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | LL_USART_PARITY_NONE 0x00000000U
#define | LL_USART_PARITY_EVEN USART_CR1_PCE
#define | LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | LL_USART_WAKEUP_IDLELINE 0x00000000U
#define | LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE
#define | LL_USART_DATAWIDTH_8B 0x00000000U
#define | LL_USART_DATAWIDTH_9B USART_CR1_M
#define | LL_USART_OVERSAMPLING_16 0x00000000U
#define | LL_USART_OVERSAMPLING_8 USART_CR1_OVER8
#define | LL_USART_CLOCK_DISABLE 0x00000000U
#define | LL_USART_CLOCK_ENABLE USART_CR2_CLKEN
#define | LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U
#define | LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL
#define | LL_USART_PHASE_1EDGE 0x00000000U
#define | LL_USART_PHASE_2EDGE USART_CR2_CPHA
#define | LL_USART_POLARITY_LOW 0x00000000U
#define | LL_USART_POLARITY_HIGH USART_CR2_CPOL
#define | LL_USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | LL_USART_STOPBITS_1 0x00000000U
#define | LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | LL_USART_STOPBITS_2 USART_CR2_STOP_1
#define | LL_USART_TXRX_STANDARD 0x00000000U
#define | LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)
#define | LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)
#define | LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)
#define | LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV
#define | LL_USART_BITORDER_LSBFIRST 0x00000000U
#define | LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST
#define | LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U
#define | LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0
#define | LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1
#define | LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)
#define | LL_USART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7
#define | LL_USART_HWCONTROL_NONE 0x00000000U
#define | LL_USART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_USART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define | LL_USART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
#define | LL_USART_IRDA_POWER_NORMAL 0x00000000U
#define | LL_USART_IRDA_POWER_LOW USART_CR3_IRLP
#define | LL_USART_LINBREAK_DETECT_10B 0x00000000U
#define | LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL
#define | LL_USART_DE_POLARITY_HIGH 0x00000000U
#define | LL_USART_DE_POLARITY_LOW USART_CR3_DEP
#define | LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U
#define | LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in USART register.
#define | LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in USART register.
#define | __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
#define | __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)

Functions

__STATIC_INLINE void | LL_USART_Enable (USART_TypeDef *USARTx)
USART Enable.
__STATIC_INLINE void | LL_USART_Disable (USART_TypeDef *USARTx)
USART Disable (all USART prescalers and outputs are disabled)
__STATIC_INLINE uint32_t | LL_USART_IsEnabled (USART_TypeDef *USARTx)
Indicate if USART is enabled.
__STATIC_INLINE void | LL_USART_EnableInStopMode (USART_TypeDef *USARTx)
USART enabled in STOP Mode.
__STATIC_INLINE void | LL_USART_DisableInStopMode (USART_TypeDef *USARTx)
USART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledInStopMode (USART_TypeDef *USARTx)
Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_USART_EnableDirectionRx (USART_TypeDef *USARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_USART_DisableDirectionRx (USART_TypeDef *USARTx)
Receiver Disable.
__STATIC_INLINE void | LL_USART_EnableDirectionTx (USART_TypeDef *USARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_USART_DisableDirectionTx (USART_TypeDef *USARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_USART_SetTransferDirection (USART_TypeDef *USARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_USART_GetTransferDirection (USART_TypeDef *USARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_USART_SetParity (USART_TypeDef *USARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled).
__STATIC_INLINE uint32_t | LL_USART_GetParity (USART_TypeDef *USARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_USART_SetWakeUpMethod (USART_TypeDef *USARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_USART_GetWakeUpMethod (USART_TypeDef *USARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_USART_SetDataWidth (USART_TypeDef *USARTx, uint32_t DataWidth)
Set Word length (i.e.
__STATIC_INLINE uint32_t | LL_USART_GetDataWidth (USART_TypeDef *USARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_USART_EnableMuteMode (USART_TypeDef *USARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_USART_DisableMuteMode (USART_TypeDef *USARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledMuteMode (USART_TypeDef *USARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_USART_SetOverSampling (USART_TypeDef *USARTx, uint32_t OverSampling)
Set Oversampling to 8-bit or 16-bit mode.
__STATIC_INLINE uint32_t | LL_USART_GetOverSampling (USART_TypeDef *USARTx)
Return Oversampling mode.
__STATIC_INLINE void | LL_USART_SetLastClkPulseOutput (USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
Configure if Clock pulse of the last data bit is output to the SCLK pin or not.
__STATIC_INLINE uint32_t | LL_USART_GetLastClkPulseOutput (USART_TypeDef *USARTx)
Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)
__STATIC_INLINE void | LL_USART_SetClockPhase (USART_TypeDef *USARTx, uint32_t ClockPhase)
Select the phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPhase (USART_TypeDef *USARTx)
Return phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_SetClockPolarity (USART_TypeDef *USARTx, uint32_t ClockPolarity)
Select the polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPolarity (USART_TypeDef *USARTx)
Return polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_ConfigClock (USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
__STATIC_INLINE void | LL_USART_EnableSCLKOutput (USART_TypeDef *USARTx)
Enable Clock output on SCLK pin.
__STATIC_INLINE void | LL_USART_DisableSCLKOutput (USART_TypeDef *USARTx)
Disable Clock output on SCLK pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSCLKOutput (USART_TypeDef *USARTx)
Indicate if Clock output on SCLK pin is enabled.
__STATIC_INLINE void | LL_USART_SetStopBitsLength (USART_TypeDef *USARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_USART_GetStopBitsLength (USART_TypeDef *USARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_USART_ConfigCharacter (USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_USART_SetTXRXSwap (USART_TypeDef *USARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_USART_GetTXRXSwap (USART_TypeDef *USARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_USART_SetRXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetRXPinLevel (USART_TypeDef *USARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetTXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetTXPinLevel (USART_TypeDef *USARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetBinaryDataLogic (USART_TypeDef *USARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_USART_GetBinaryDataLogic (USART_TypeDef *USARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_USART_SetTransferBitOrder (USART_TypeDef *USARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_USART_GetTransferBitOrder (USART_TypeDef *USARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_USART_EnableAutoBaudRate (USART_TypeDef *USARTx)
Enable Auto Baud-Rate Detection.
__STATIC_INLINE void | LL_USART_DisableAutoBaudRate (USART_TypeDef *USARTx)
Disable Auto Baud-Rate Detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledAutoBaud (USART_TypeDef *USARTx)
Indicate if Auto Baud-Rate Detection mechanism is enabled.
__STATIC_INLINE void | LL_USART_SetAutoBaudRateMode (USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
Set Auto Baud-Rate mode bits.
__STATIC_INLINE uint32_t | LL_USART_GetAutoBaudRateMode (USART_TypeDef *USARTx)
Return Auto Baud-Rate mode.
__STATIC_INLINE void | LL_USART_EnableRxTimeout (USART_TypeDef *USARTx)
Enable Receiver Timeout.
__STATIC_INLINE void | LL_USART_DisableRxTimeout (USART_TypeDef *USARTx)
Disable Receiver Timeout.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledRxTimeout (USART_TypeDef *USARTx)
Indicate if Receiver Timeout feature is enabled.
__STATIC_INLINE void | LL_USART_ConfigNodeAddress (USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the USART node.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddress (USART_TypeDef *USARTx)
Return 8 bit Address of the USART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddressLen (USART_TypeDef *USARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_USART_EnableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_EnableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_SetHWFlowCtrl (USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_USART_GetHWFlowCtrl (USART_TypeDef *USARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_USART_EnableOneBitSamp (USART_TypeDef *USARTx)
Enable One bit sampling method.
__STATIC_INLINE void | LL_USART_DisableOneBitSamp (USART_TypeDef *USARTx)
Disable One bit sampling method.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOneBitSamp (USART_TypeDef *USARTx)
Indicate if One bit sampling method is enabled.
__STATIC_INLINE void | LL_USART_EnableOverrunDetect (USART_TypeDef *USARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_USART_DisableOverrunDetect (USART_TypeDef *USARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOverrunDetect (USART_TypeDef *USARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_USART_SetWKUPType (USART_TypeDef *USARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetWKUPType (USART_TypeDef *USARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_USART_SetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, uint32_t BaudRate)
Configure USART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_USART_GetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.
__STATIC_INLINE void | LL_USART_SetRxTimeout (USART_TypeDef *USARTx, uint32_t Timeout)
Set Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE uint32_t | LL_USART_GetRxTimeout (USART_TypeDef *USARTx)
Get Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE void | LL_USART_SetBlockLength (USART_TypeDef *USARTx, uint32_t BlockLength)
Set Block Length value in reception.
__STATIC_INLINE uint32_t | LL_USART_GetBlockLength (USART_TypeDef *USARTx)
Get Block Length value in reception.
__STATIC_INLINE void | LL_USART_EnableIrda (USART_TypeDef *USARTx)
Enable IrDA mode.
__STATIC_INLINE void | LL_USART_DisableIrda (USART_TypeDef *USARTx)
Disable IrDA mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIrda (USART_TypeDef *USARTx)
Indicate if IrDA mode is enabled.
__STATIC_INLINE void | LL_USART_SetIrdaPowerMode (USART_TypeDef *USARTx, uint32_t PowerMode)
Configure IrDA Power Mode (Normal or Low Power)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPowerMode (USART_TypeDef *USARTx)
Retrieve IrDA Power Mode configuration (Normal or Low Power)
__STATIC_INLINE void | LL_USART_SetIrdaPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPrescaler (USART_TypeDef *USARTx)
Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE void | LL_USART_EnableSmartcardNACK (USART_TypeDef *USARTx)
Enable Smartcard NACK transmission.
__STATIC_INLINE void | LL_USART_DisableSmartcardNACK (USART_TypeDef *USARTx)
Disable Smartcard NACK transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcardNACK (USART_TypeDef *USARTx)
Indicate if Smartcard NACK transmission is enabled.
__STATIC_INLINE void | LL_USART_EnableSmartcard (USART_TypeDef *USARTx)
Enable Smartcard mode.
__STATIC_INLINE void | LL_USART_DisableSmartcard (USART_TypeDef *USARTx)
Disable Smartcard mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcard (USART_TypeDef *USARTx)
Indicate if Smartcard mode is enabled.
__STATIC_INLINE void | LL_USART_SetSmartcardAutoRetryCount (USART_TypeDef *USARTx, uint32_t AutoRetryCount)
Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardAutoRetryCount (USART_TypeDef *USARTx)
Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE void | LL_USART_SetSmartcardPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardPrescaler (USART_TypeDef *USARTx)
Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE void | LL_USART_SetSmartcardGuardTime (USART_TypeDef *USARTx, uint32_t GuardTime)
Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardGuardTime (USART_TypeDef *USARTx)
Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE void | LL_USART_EnableHalfDuplex (USART_TypeDef *USARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_USART_DisableHalfDuplex (USART_TypeDef *USARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledHalfDuplex (USART_TypeDef *USARTx)
Indicate if Single Wire Half-Duplex mode is enabled.
__STATIC_INLINE void | LL_USART_SetLINBrkDetectionLen (USART_TypeDef *USARTx, uint32_t LINBDLength)
Set LIN Break Detection Length.
__STATIC_INLINE uint32_t | LL_USART_GetLINBrkDetectionLen (USART_TypeDef *USARTx)
Return LIN Break Detection Length.
__STATIC_INLINE void | LL_USART_EnableLIN (USART_TypeDef *USARTx)
Enable LIN mode.
__STATIC_INLINE void | LL_USART_DisableLIN (USART_TypeDef *USARTx)
Disable LIN mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledLIN (USART_TypeDef *USARTx)
Indicate if LIN mode is enabled.
__STATIC_INLINE void | LL_USART_SetDEDeassertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEDeassertionTime (USART_TypeDef *USARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_USART_SetDEAssertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEAssertionTime (USART_TypeDef *USARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_USART_EnableDEMode (USART_TypeDef *USARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_USART_DisableDEMode (USART_TypeDef *USARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDEMode (USART_TypeDef *USARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_USART_SetDESignalPolarity (USART_TypeDef *USARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_USART_GetDESignalPolarity (USART_TypeDef *USARTx)
Return Driver Enable Polarity.
__STATIC_INLINE void | LL_USART_ConfigAsyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
__STATIC_INLINE void | LL_USART_ConfigSyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Synchronous Mode.
__STATIC_INLINE void | LL_USART_ConfigLINMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in LIN Mode.
__STATIC_INLINE void | LL_USART_ConfigHalfDuplexMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Half Duplex Mode.
__STATIC_INLINE void | LL_USART_ConfigSmartcardMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Smartcard Mode.
__STATIC_INLINE void | LL_USART_ConfigIrdaMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Irda Mode.
__STATIC_INLINE void | LL_USART_ConfigMultiProcessMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_FE (USART_TypeDef *USARTx)
Check if the USART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_NE (USART_TypeDef *USARTx)
Check if the USART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ORE (USART_TypeDef *USARTx)
Check if the USART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXNE (USART_TypeDef *USARTx)
Check if the USART Read Data Register Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXE (USART_TypeDef *USARTx)
Check if the USART Transmit Data Register Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_nCTS (USART_TypeDef *USARTx)
Check if the USART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RTO (USART_TypeDef *USARTx)
Check if the USART Receiver Time Out Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_EOB (USART_TypeDef *USARTx)
Check if the USART End Of Block Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABRE (USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABR (USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_BUSY (USART_TypeDef *USARTx)
Check if the USART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CM (USART_TypeDef *USARTx)
Check if the USART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_SBK (USART_TypeDef *USARTx)
Check if the USART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RWU (USART_TypeDef *USARTx)
Check if the USART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_WKUP (USART_TypeDef *USARTx)
Check if the USART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TEACK (USART_TypeDef *USARTx)
Check if the USART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_REACK (USART_TypeDef *USARTx)
Check if the USART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE void | LL_USART_ClearFlag_PE (USART_TypeDef *USARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_FE (USART_TypeDef *USARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_NE (USART_TypeDef *USARTx)
Clear Noise detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_ORE (USART_TypeDef *USARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_IDLE (USART_TypeDef *USARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TC (USART_TypeDef *USARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_LBD (USART_TypeDef *USARTx)
Clear LIN Break Detection Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_nCTS (USART_TypeDef *USARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_RTO (USART_TypeDef *USARTx)
Clear Receiver Time Out Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_EOB (USART_TypeDef *USARTx)
Clear End Of Block Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_CM (USART_TypeDef *USARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_WKUP (USART_TypeDef *USARTx)
Clear Wake Up from stop mode Flag.
__STATIC_INLINE void | LL_USART_EnableIT_IDLE (USART_TypeDef *USARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXNE (USART_TypeDef *USARTx)
Enable RX Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TC (USART_TypeDef *USARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXE (USART_TypeDef *USARTx)
Enable TX Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_PE (USART_TypeDef *USARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CM (USART_TypeDef *USARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RTO (USART_TypeDef *USARTx)
Enable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_EOB (USART_TypeDef *USARTx)
Enable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_LBD (USART_TypeDef *USARTx)
Enable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_ERROR (USART_TypeDef *USARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CTS (USART_TypeDef *USARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_WKUP (USART_TypeDef *USARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_IDLE (USART_TypeDef *USARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXNE (USART_TypeDef *USARTx)
Disable RX Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TC (USART_TypeDef *USARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXE (USART_TypeDef *USARTx)
Disable TX Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_PE (USART_TypeDef *USARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CM (USART_TypeDef *USARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RTO (USART_TypeDef *USARTx)
Disable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_EOB (USART_TypeDef *USARTx)
Disable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_LBD (USART_TypeDef *USARTx)
Disable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_ERROR (USART_TypeDef *USARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CTS (USART_TypeDef *USARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_WKUP (USART_TypeDef *USARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXNE (USART_TypeDef *USARTx)
Check if the USART RX Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXE (USART_TypeDef *USARTx)
Check if the USART TX Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CM (USART_TypeDef *USARTx)
Check if the USART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RTO (USART_TypeDef *USARTx)
Check if the USART Receiver Timeout Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_EOB (USART_TypeDef *USARTx)
Check if the USART End Of Block Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_ERROR (USART_TypeDef *USARTx)
Check if the USART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_WKUP (USART_TypeDef *USARTx)
Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_USART_EnableDMAReq_RX (USART_TypeDef *USARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_USART_DisableDMAReq_RX (USART_TypeDef *USARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_RX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_USART_EnableDMAReq_TX (USART_TypeDef *USARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_USART_DisableDMAReq_TX (USART_TypeDef *USARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_TX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_USART_EnableDMADeactOnRxErr (USART_TypeDef *USARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_USART_DisableDMADeactOnRxErr (USART_TypeDef *USARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMADeactOnRxErr (USART_TypeDef *USARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_USART_DMA_GetRegAddr (USART_TypeDef *USARTx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_USART_ReceiveData8 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_USART_ReceiveData9 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_USART_TransmitData8 (USART_TypeDef *USARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_USART_TransmitData9 (USART_TypeDef *USARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)
__STATIC_INLINE void | LL_USART_RequestAutoBaudRate (USART_TypeDef *USARTx)
Request an Automatic Baud Rate measurement on next received data frame.
__STATIC_INLINE void | LL_USART_RequestBreakSending (USART_TypeDef *USARTx)
Request Break sending.
__STATIC_INLINE void | LL_USART_RequestEnterMuteMode (USART_TypeDef *USARTx)
Put USART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_USART_RequestRxDataFlush (USART_TypeDef *USARTx)
Request a Receive Data flush.
__STATIC_INLINE void | LL_USART_RequestTxDataFlush (USART_TypeDef *USARTx)
Request a Transmit data flush.
ErrorStatus | LL_USART_DeInit (USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Detailed Description

Header file of USART LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_usart.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_utils.h File Reference

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Data Structures | Defines | Functions
stm32f3xx_ll_utils.h File Reference

Header file of UTILS LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Data Structures

struct | LL_UTILS_PLLInitTypeDef
UTILS PLL structure definition. More...
struct | LL_UTILS_ClkInitTypeDef
UTILS System, AHB and APB buses clock configuration structure definition. More...

Defines

#define | LL_MAX_DELAY 0xFFFFFFFFU
#define | UID_BASE_ADDRESS UID_BASE
Unique device ID register base address.
#define | FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
Flash size data register base address.
#define | PACKAGE_BASE_ADDRESS PACKAGE_BASE
Package data register base address.
#define | LL_UTILS_HSEBYPASS_OFF 0x00000000U
#define | LL_UTILS_HSEBYPASS_ON 0x00000001U

Functions

__STATIC_INLINE uint32_t | LL_GetUID_Word0 (void)
Get Word0 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word1 (void)
Get Word1 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word2 (void)
Get Word2 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetFlashSize (void)
Get Flash memory size.
__STATIC_INLINE void | LL_InitTick (uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.
void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

Header file of UTILS LL module.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL UTILS driver contains a set of generic APIs that can be
    used by user:
      (+) Device electronic signature
      (+) Timing functions
      (+) PLL configuration functions
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_utils.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_wwdg.h File Reference

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stm32f3xx_ll_wwdg.h File Reference

Header file of WWDG LL module. More...

#include "stm32f3xx.h"

Go to the source code of this file.

Defines

#define | LL_WWDG_CFR_EWI WWDG_CFR_EWI
#define | LL_WWDG_PRESCALER_1 0x00000000U
#define | LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in WWDG register.
#define | LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in WWDG register.

Functions

__STATIC_INLINE void | LL_WWDG_Enable (WWDG_TypeDef *WWDGx)
Enable Window Watchdog.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabled (WWDG_TypeDef *WWDGx)
Checks if Window Watchdog is enabled.
__STATIC_INLINE void | LL_WWDG_SetCounter (WWDG_TypeDef *WWDGx, uint32_t Counter)
Set the Watchdog counter value to provided value (7-bits T[6:0])
__STATIC_INLINE uint32_t | LL_WWDG_GetCounter (WWDG_TypeDef *WWDGx)
Return current Watchdog Counter Value (7 bits counter value)
__STATIC_INLINE void | LL_WWDG_SetPrescaler (WWDG_TypeDef *WWDGx, uint32_t Prescaler)
Set the time base of the prescaler (WDGTB).
__STATIC_INLINE uint32_t | LL_WWDG_GetPrescaler (WWDG_TypeDef *WWDGx)
Return current Watchdog Prescaler Value.
__STATIC_INLINE void | LL_WWDG_SetWindow (WWDG_TypeDef *WWDGx, uint32_t Window)
Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
__STATIC_INLINE uint32_t | LL_WWDG_GetWindow (WWDG_TypeDef *WWDGx)
Return current Watchdog Window Value (7 bits value)
__STATIC_INLINE uint32_t | LL_WWDG_IsActiveFlag_EWKUP (WWDG_TypeDef *WWDGx)
Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
__STATIC_INLINE void | LL_WWDG_ClearFlag_EWKUP (WWDG_TypeDef *WWDGx)
Clear WWDG Early Wakeup Interrupt Flag (EWIF)
__STATIC_INLINE void | LL_WWDG_EnableIT_EWKUP (WWDG_TypeDef *WWDGx)
Enable the Early Wakeup Interrupt.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabledIT_EWKUP (WWDG_TypeDef *WWDGx)
Check if Early Wakeup Interrupt is enabled.

Detailed Description

Header file of WWDG LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_wwdg.h.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal.c File Reference

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Defines | Functions | Variables
stm32f3xx_hal.c File Reference

HAL module driver. This is the common part of the HAL initialization. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | __STM32F3xx_HAL_VERSION_MAIN (0x01U)
STM32F3xx HAL Driver version number V1.5.0.
#define | __STM32F3xx_HAL_VERSION_SUB1 (0x05U)
#define | __STM32F3xx_HAL_VERSION_SUB2 (0x00U)
#define | __STM32F3xx_HAL_VERSION_RC (0x00U)
#define | __STM32F3xx_HAL_VERSION
#define | IDCODE_DEVID_MASK (0x00000FFFU)

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function configures the Flash prefetch, Configures time base source, NVIC and Low level hardware.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the source of time base.
__weak void | HAL_MspInit (void)
Initializes the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Povides a tick value in millisecond.
__weak void | HAL_Delay (__IO uint32_t Delay)
This function provides accurate delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
This function returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
uint32_t | HAL_GetUIDw0 (void)
Returns first word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw1 (void)
Returns second word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw2 (void)
Returns third word of the unique device identifier (UID based on 96 bits)
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.

Variables

__IO uint32_t | uwTick

Detailed Description

HAL module driver. This is the common part of the HAL initialization.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The common HAL driver contains a set of generic and common APIs that can be
    used by the PPP peripheral drivers and the user to start using the HAL.
    [..]
    The HAL contains two APIs categories:
         (+) HAL Initialization and de-initialization functions
         (+) HAL Control functions
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal.c.

Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_adc.c File Reference

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Functions
stm32f3xx_hal_adc.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of conversions of regular group, using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Channels configuration on injected group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32f3xx_hal_adc_ex.c". More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

__weak HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
__weak HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initializes the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitializes the ADC MSP.
__weak HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of regular group.
__weak HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC peripheral.
__weak HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
__weak HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for conversion event.
__weak HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of regular group with interruption.
__weak HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interruption of end-of-conversion, disable ADC peripheral.
__weak HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC, starts conversion of regular group and transfers result through DMA.
__weak HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
__weak uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
__weak void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handles ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog callback in non blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non blocking mode (ADC conversion with interruption or transfer by DMA)
__weak HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configures the the selected channel to be linked to the regular group.
__weak HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configures the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
return the ADC state
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of conversions of regular group, using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Channels configuration on injected group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32f3xx_hal_adc_ex.c".

Author:
MCD Application Team
  ==============================================================================
                     ##### ADC peripheral features #####
  ==============================================================================
  [..]
  (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution (available only on
      STM32F30xxC devices).

  (+) Interrupt generation at the end of regular conversion, end of injected
      conversion, and in case of analog watchdog or overrun events.

  (+) Single and continuous conversion modes.

  (+) Scan mode for conversion of several channels sequentially.

  (+) Data alignment with in-built data coherency.

  (+) Programmable sampling time (channel wise)

  (+) ADC conversion of regular group and injected group.

  (+) External trigger (timer or EXTI) with configurable polarity
      for both regular and injected groups.

  (+) DMA request generation for transfer of conversions data of regular group.

  (+) Multimode dual mode (available on devices with 2 ADCs or more).

  (+) Configurable DMA data storage in Multimode Dual mode (available on devices
      with 2 DCs or more).

  (+) Configurable delay between conversions in Dual interleaved mode (available
      on devices with 2 DCs or more).

  (+) ADC calibration

  (+) ADC channels selectable single/differential input (available only on
      STM32F30xxC devices)

  (+) ADC Injected sequencer&channels configuration context queue (available
      only on STM32F30xxC devices)

  (+) ADC offset on injected and regular groups (offset on regular group
      available only on STM32F30xxC devices)

  (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
      slower speed.

  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
      Vdda or to an external voltage reference).

                     ##### How to use this driver #####
  ==============================================================================
    [..]

     *** Configuration of top level parameters related to ADC ***
     ============================================================
     [..]

    (#) Enable the ADC interface
      (++) As prerequisite, ADC clock must be configured at RCC top level.

        (++) For STM32F30x/STM32F33x devices:
             Two possible clock sources: synchronous clock derived from AHB clock
             or asynchronous clock derived from ADC dedicated PLL 72MHz.
              - Synchronous clock is mandatory since used as ADC core clock.
                Synchronous clock can be used optionally as ADC conversion clock, depending on ADC init structure clock setting.
                Synchronous clock is configured using macro __ADCx_CLK_ENABLE().
              - Asynchronous can be used optionally as ADC conversion clock, depending on ADC init structure clock setting.
                Asynchronous clock is configured using function HAL_RCCEx_PeriphCLKConfig().
             (+++) For example, in case of device with a single ADC:
                   Into HAL_ADC_MspInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) __HAL_RCC_ADC1_CLK_ENABLE()                            (mandatory)
               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if ADC conversion from asynchronous clock)
               (+++) PeriphClkInit.Adc1ClockSelection = RCC_ADC1PLLCLK_DIV1 (optional, if ADC conversion from asynchronous clock)
               (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if ADC conversion from asynchronous clock)

             (+++) For example, in case of device with 4 ADCs:

               (+++) if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
               (+++) {
               (+++)   __HAL_RCC_ADC12_CLK_ENABLE()                             (mandatory)
               (+++)   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC   (optional, if ADC conversion from asynchronous clock)
               (+++)   PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_DIV1 (optional, if ADC conversion from asynchronous clock)
               (+++)   HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure)   (optional, if ADC conversion from asynchronous clock)
               (+++) }
               (+++) else
               (+++) {
               (+++)   __HAL_RCC_ADC34_CLK_ENABLE()                              (mandatory)
               (+++)   PeriphClkInit.Adc34ClockSelection = RCC_ADC34PLLCLK_DIV1; (optional, if ADC conversion from asynchronous clock)
               (+++)   HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure);   (optional, if ADC conversion from asynchronous clock)
               (+++) }

        (++) For STM32F37x devices:
             One clock setting is mandatory:
             ADC clock (core and conversion clock) from APB2 clock.
             (+++) Example:
                   Into HAL_ADC_MspInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
               (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK_DIV2
               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)

    (#) ADC pins configuration
         (++) Enable the clock for the ADC GPIOs
              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
         (++) Configure these ADC pins in analog mode
              using function HAL_GPIO_Init()

    (#) Optionally, in case of usage of ADC with interruptions:
         (++) Configure the NVIC for ADC
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
              into the function of corresponding ADC interruption vector
              ADCx_IRQHandler().

    (#) Optionally, in case of usage of DMA:
         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
              using function HAL_DMA_Init().
         (++) Configure the NVIC for DMA
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
              into the function of corresponding DMA interruption vector
              DMAx_Channelx_IRQHandler().

     *** Configuration of ADC, groups regular/injected, channels parameters ***
     ==========================================================================
     [..]

    (#) Configure the ADC parameters (resolution, data alignment, ...)
        and regular group parameters (conversion trigger, sequencer, ...)
        using function HAL_ADC_Init().

    (#) Configure the channels for regular group parameters (channel number,
        channel rank into sequencer, ..., into regular group)
        using function HAL_ADC_ConfigChannel().

    (#) Optionally, configure the injected group parameters (conversion trigger,
        sequencer, ..., of injected group)
        and the channels for injected group parameters (channel number,
        channel rank into sequencer, ..., into injected group)
        using function HAL_ADCEx_InjectedConfigChannel().

    (#) Optionally, configure the analog watchdog parameters (channels
        monitored, thresholds, ...)
        using function HAL_ADC_AnalogWDGConfig().

    (#) Optionally, for devices with several ADC instances: configure the
        multimode parameters
        using function HAL_ADCEx_MultiModeConfigChannel().

     *** Execution of ADC conversions ***
     ====================================
     [..]

    (#) Optionally, perform an automatic ADC calibration to improve the
        conversion accuracy
        using function HAL_ADCEx_Calibration_Start().

    (#) ADC driver can be used among three modes: polling, interruption,
        transfer by DMA.

        (++) ADC conversion by polling:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start()
          (+++) Wait for ADC conversion completion
                using function HAL_ADC_PollForConversion()
                (or for injected group: HAL_ADCEx_InjectedPollForConversion() )
          (+++) Retrieve conversion results
                using function HAL_ADC_GetValue()
                (or for injected group: HAL_ADCEx_InjectedGetValue() )
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop()

        (++) ADC conversion by interruption:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start_IT()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback()
                (this function must be implemented in user program)
                (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
          (+++) Retrieve conversion results
                using function HAL_ADC_GetValue()
                (or for injected group: HAL_ADCEx_InjectedGetValue() )
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop_IT()

        (++) ADC conversion with transfer by DMA:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start_DMA()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
                (these functions must be implemented in user program)
          (+++) Conversion results are automatically transferred by DMA into
                destination variable address.
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop_DMA()

        (++) For devices with several ADCs: ADC multimode conversion
             with transfer by DMA:
          (+++) Activate the ADC peripheral (slave)
                using function HAL_ADC_Start()
                (conversion start pending ADC master)
          (+++) Activate the ADC peripheral (master) and start conversions
                using function HAL_ADCEx_MultiModeStart_DMA()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
                (these functions must be implemented in user program)
          (+++) Conversion results are automatically transferred by DMA into
                destination variable address.
          (+++) Stop conversion and disable the ADC peripheral (master)
                using function HAL_ADCEx_MultiModeStop_DMA()
          (+++) Stop conversion and disable the ADC peripheral (slave)
                using function HAL_ADC_Stop_IT()

     [..]

    (@) Callback functions must be implemented in user program:
      (+@) HAL_ADC_ErrorCallback()
      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
      (+@) HAL_ADC_ConvCpltCallback()
      (+@) HAL_ADC_ConvHalfCpltCallback
      (+@) HAL_ADCEx_InjectedConvCpltCallback()
      (+@) HAL_ADCEx_InjectedQueueOverflowCallback() (for STM32F30x/STM32F33x devices)

     *** Deinitialization of ADC ***
     ============================================================
     [..]

    (#) Disable the ADC interface
      (++) ADC clock can be hard reset and disabled at RCC top level.
        (++) Hard reset of ADC peripherals
             using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
        (++) ADC clock disable
             using the equivalent macro/functions as configuration step.

        (++) For STM32F30x/STM32F33x devices:
           Caution: For devices with several ADCs:
           These settings impact both ADC of common group: ADC1&ADC2, ADC3&ADC4
           if available (ADC2, ADC3, ADC4 availability depends on STM32 product)

             (+++) For example, in case of device with a single ADC:
                   Into HAL_ADC_MspDeInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) __HAL_RCC_ADC1_FORCE_RESET()                           (optional)
               (+++) __HAL_RCC_ADC1_RELEASE_RESET()                         (optional)
               (+++) __HAL_RCC_ADC1_CLK_DISABLE()                           (mandatory)
               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if configured before)
               (+++) PeriphClkInit.Adc1ClockSelection = RCC_ADC1PLLCLK_OFF  (optional, if configured before)
               (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if configured before)

             (+++) For example, in case of device with 4 ADCs:
               (+++) if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
               (+++) {
               (+++)   __HAL_RCC_ADC12_FORCE_RESET()                            (optional)
               (+++)   __HAL_RCC_ADC12_RELEASE_RESET()                          (optional)
               (+++)   __HAL_RCC_ADC12_CLK_DISABLE()                            (mandatory)
               (+++)   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC   (optional, if configured before)
               (+++)   PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_OFF  (optional, if configured before)
               (+++)   HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure)   (optional, if configured before)
               (+++) }
               (+++) else
               (+++) {
               (+++)   __HAL_RCC_ADC32_FORCE_RESET()                            (optional)
               (+++)   __HAL_RCC_ADC32_RELEASE_RESET()                          (optional)
               (+++)   __HAL_RCC_ADC34_CLK_DISABLE()                            (mandatory)
               (+++)   PeriphClkInit.Adc34ClockSelection = RCC_ADC34PLLCLK_OFF  (optional, if configured before)
               (+++)   HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure)   (optional, if configured before)
               (+++) }

        (++) For STM32F37x devices:
             (+++) Example:
                   Into HAL_ADC_MspDeInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
               (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK_OFF
               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)

    (#) ADC pins configuration
         (++) Disable the clock for the ADC GPIOs
              using macro __HAL_RCC_GPIOx_CLK_DISABLE()

    (#) Optionally, in case of usage of ADC with interruptions:
         (++) Disable the NVIC for ADC
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)

    (#) Optionally, in case of usage of DMA:
         (++) Deinitialize the DMA
              using function HAL_DMA_Init().
         (++) Disable the NVIC for DMA
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)

    [..]
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_adc.c.

Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_adc_ex.c File Reference

  • File List
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  • Firmware
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  • STM32F3xx_HAL_Driver
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Defines | Functions
stm32f3xx_hal_adc_ex.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of injected group, using 2 possible modes: polling, interruption. ++ Multimode feature (available on devices with 2 ADCs or more) ++ Calibration (ADC automatic self-calibration) + Control functions ++ Channels configuration on injected group Other functions (generic functions) are available in file "stm32f3xx_hal_adc.c". More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | ADC_ENABLE_TIMEOUT ( 2U)
#define | ADC_DISABLE_TIMEOUT ( 2U)
#define | ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ( 2U)
#define | ADC_CALIBRATION_TIMEOUT ( 10U)
#define | ADC_STAB_DELAY_US ( 1U)
#define | ADC_TEMPSENSOR_DELAY_US ( 10U)
#define | ADC_CYCLE_WORST_CASE_CPU_CYCLES ( 128U)
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ( 14U)
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ( 20U)
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ( 26U)
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ( 41U)
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ( 54U)
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ( 68U)
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ( 84U)
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 (252U)

Functions

static HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
static HAL_StatusTypeDef | ADC_ConversionStop_Disable (ADC_HandleTypeDef *hadc)
Stop ADC conversion and disable the selected ADC.
static void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
static void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
static void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to its default reset values.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for conversion event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC, starts conversion of regular group and transfers result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handles ADC interrupt request.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non blocking mode.
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configures the the selected channel to be linked to the regular group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configures the ADC injected group and the selected channel to be linked to the injected group.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configures the analog watchdog.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of injected group, using 2 possible modes: polling, interruption. ++ Multimode feature (available on devices with 2 ADCs or more) ++ Calibration (ADC automatic self-calibration) + Control functions ++ Channels configuration on injected group Other functions (generic functions) are available in file "stm32f3xx_hal_adc.c".

Author:
MCD Application Team
  [..]
  (@) Sections "ADC peripheral features" and "How to use this driver" are
      available in file of generic functions "stm32f3xx_hal_adc.c".
  [..]
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_adc_ex.c.

Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_can.c File Reference

  • File List
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  • STM32F3xx_HAL_Driver
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Defines | Functions
stm32f3xx_hal_can.c File Reference

CAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | CAN_TIMEOUT_VALUE 10U

Functions

static HAL_StatusTypeDef | CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receives a correct CAN frame.
static HAL_StatusTypeDef | CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Init (CAN_HandleTypeDef *hcan)
Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.
HAL_StatusTypeDef | HAL_CAN_ConfigFilter (CAN_HandleTypeDef *hcan, CAN_FilterConfTypeDef *sFilterConfig)
Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.
HAL_StatusTypeDef | HAL_CAN_DeInit (CAN_HandleTypeDef *hcan)
Deinitializes the CANx peripheral registers to their default reset values.
__weak void | HAL_CAN_MspInit (CAN_HandleTypeDef *hcan)
Initializes the CAN MSP.
__weak void | HAL_CAN_MspDeInit (CAN_HandleTypeDef *hcan)
DeInitializes the CAN MSP.
HAL_StatusTypeDef | HAL_CAN_Transmit (CAN_HandleTypeDef *hcan, uint32_t Timeout)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Receive (CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Sleep (CAN_HandleTypeDef *hcan)
Enters the Sleep (low power) mode.
HAL_StatusTypeDef | HAL_CAN_WakeUp (CAN_HandleTypeDef *hcan)
Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode.
void | HAL_CAN_IRQHandler (CAN_HandleTypeDef *hcan)
Handles CAN interrupt request.
__weak void | HAL_CAN_TxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_RxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_ErrorCallback (CAN_HandleTypeDef *hcan)
Error CAN callback.
HAL_CAN_StateTypeDef | HAL_CAN_GetState (CAN_HandleTypeDef *hcan)
return the CAN state
uint32_t | HAL_CAN_GetError (CAN_HandleTypeDef *hcan)
Return the CAN error code.

Detailed Description

CAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      (#) Enable the CAN controller interface clock using __HAL_RCC_CAN1_CLK_ENABLE();

      (#) CAN pins configuration
        (++) Enable the clock for the CAN GPIOs using the following function:
             __HAL_RCC_GPIOx_CLK_ENABLE();
        (++) Connect and configure the involved CAN pins to AF9 using the
              following function HAL_GPIO_Init();

      (#) Initialise and configure the CAN using HAL_CAN_Init() function.

      (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.

      (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.

      (#) Receive a CAN frame using HAL_CAN_Receive() function.

      (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the CAN peripheral transmission and wait the end of this operation
           using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
           according to his end application
       (+) Start the CAN peripheral reception and wait the end of this operation
           using HAL_CAN_Receive(), at this stage user can specify the value of timeout
           according to his end application

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
       (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
       (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
       (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
            add his own code by customization of function pointer HAL_CAN_TxCpltCallback
       (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_CAN_ErrorCallback

     *** CAN HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in CAN HAL driver.

      (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
      (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
      (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
      (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
      (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status

     [..]
      (@) You can refer to the CAN HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_can.c.

Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_cec.c File Reference

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Functions
stm32f3xx_hal_cec.c File Reference

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CEC_Init (CEC_HandleTypeDef *hcec)
Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_CEC_DeInit (CEC_HandleTypeDef *hcec)
DeInitializes the CEC peripheral.
HAL_StatusTypeDef | HAL_CEC_SetDeviceAddress (CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
Initializes the Own Address of the CEC device.
__weak void | HAL_CEC_MspInit (CEC_HandleTypeDef *hcec)
CEC MSP Init.
__weak void | HAL_CEC_MspDeInit (CEC_HandleTypeDef *hcec)
CEC MSP DeInit.
HAL_StatusTypeDef | HAL_CEC_Transmit_IT (CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
Send data in interrupt mode.
uint32_t | HAL_CEC_GetLastReceivedFrameSize (CEC_HandleTypeDef *hcec)
Get size of the received frame.
void | HAL_CEC_ChangeRxBuffer (CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
Change Rx Buffer.
void | HAL_CEC_IRQHandler (CEC_HandleTypeDef *hcec)
This function handles CEC interrupt requests.
__weak void | HAL_CEC_TxCpltCallback (CEC_HandleTypeDef *hcec)
Tx Transfer completed callback.
__weak void | HAL_CEC_RxCpltCallback (CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
Rx Transfer completed callback.
__weak void | HAL_CEC_ErrorCallback (CEC_HandleTypeDef *hcec)
CEC error callbacks.
HAL_CEC_StateTypeDef | HAL_CEC_GetState (CEC_HandleTypeDef *hcec)
return the CEC state
uint32_t | HAL_CEC_GetError (CEC_HandleTypeDef *hcec)
Return the CEC error code.

Detailed Description

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

Author:
MCD Application Team
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
    The CEC HAL driver can be used as follow:

    (#) Declare a CEC_HandleTypeDef handle structure.
    (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
        (##) Enable the CEC interface clock.
        (##) CEC pins configuration:
            (+) Enable the clock for the CEC GPIOs.
            (+) Configure these CEC pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
             and HAL_CEC_Receive_IT() APIs):
            (+) Configure the CEC interrupt priority.
            (+) Enable the NVIC CEC IRQ handle.
            (@) The specific CEC interrupts (Transmission complete interrupt,
                RXNE interrupt and Error Interrupts) will be managed using the macros
                __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
                and receive process.

    (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
        in case of Bit Rising Error, Error-Bit generation conditions, device logical
        address and Listen mode in the hcec Init structure.

    (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.

    (@) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
        by calling the customed HAL_CEC_MspInit() API.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_cec.c.

Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_comp.c File Reference

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Defines | Functions
stm32f3xx_hal_comp.c File Reference

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | COMP_LOCK_DISABLE (0x00000000U)
#define | COMP_LOCK_ENABLE COMP_CSR_COMPxLOCK

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP peripheral according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
HAL_StatusTypeDef | HAL_COMP_Start_IT (COMP_HandleTypeDef *hcomp)
Start the comparator in Interrupt mode.
HAL_StatusTypeDef | HAL_COMP_Stop_IT (COMP_HandleTypeDef *hcomp)
Stop the comparator in Interrupt mode.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ Handler.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator callback.
HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
HAL_COMP_StateTypeDef | HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.

Detailed Description

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
================================================================================
          ##### COMP Peripheral features #####
================================================================================

  [..]
      The STM32F3xx device family integrates up to 7 analog comparators COMP1, COMP2...COMP7:
      (#) The non inverting input and inverting input can be set to GPIO pins.
          For STM32F3xx devices please refer to the COMP peripheral section in corresponding
          Reference Manual.

      (#) The COMP output is available using HAL_COMP_GetOutputLevel()
          and can be set on GPIO pins.
          For STM32F3xx devices please refer to the COMP peripheral section in corresponding
          Reference Manual.

      (#) The COMP output can be redirected to embedded timers (TIM1, TIM2, TIM3...).
          For STM32F3xx devices please refer to the COMP peripheral section in corresponding
          Reference Manual.

      (#) Each couple of comparators COMP1 and COMP2, COMP3 and COMP4, COMP5 and COMP6 can be combined in window
          mode and respectively COMP1, COMP3 and COMP5 non inverting input is used as common non-inverting input.

      (#) The seven comparators have interrupt capability with wake-up
          from Sleep and Stop modes (through the EXTI controller):
          (++) COMP1 is internally connected to EXTI Line 21
          (++) COMP2 is internally connected to EXTI Line 22
          (++) COMP3 is internally connected to EXTI Line 29
          (++) COMP4 is internally connected to EXTI Line 30
          (++) COMP5 is internally connected to EXTI Line 31
          (++) COMP6 is internally connected to EXTI Line 32
          (++) COMP7 is internally connected to EXTI Line 33.

          From the corresponding IRQ handler, the right interrupt source can be retrieved with the
          adequate macro __HAL_COMP_COMPx_EXTI_GET_FLAG().

            ##### How to use this driver #####
================================================================================
  [..]
      This driver provides functions to configure and program the Comparators of all STM32F3xx devices.

      To use the comparator, perform the following steps:

      (#) Fill in the HAL_COMP_MspInit() to
      (++) Configure the comparator input in analog mode using HAL_GPIO_Init()
      (++) Configure the comparator output in alternate function mode using HAL_GPIO_Init() to map the comparator
           output to the GPIO pin
      (++) If required enable the COMP interrupt (EXTI line Interrupt): by configuring and enabling EXTI line in Interrupt mode and
           selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
           interrupt vector using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() functions.

      (#) Configure the comparator using HAL_COMP_Init() function:
      (++) Select the inverting input (input minus)
      (++) Select the non-inverting input (input plus)
      (++) Select the output polarity
      (++) Select the output redirection
      (++) Select the hysteresis level
      (++) Select the power mode
      (++) Select the event/interrupt mode

      -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE() in order
          to enable the comparator(s).

      (#) On-the-fly reconfiguration of comparator(s) may be done by calling again HAL_COMP_Init(
          function with new input parameter values; HAL_COMP_MspInit() function shall be adapted
          to support multi configurations.

      (#) Enable the comparator using HAL_COMP_Start() or HAL_COMP_Start_IT() functions.

      (#) Use HAL_COMP_TriggerCallback() and/or HAL_COMP_GetOutputLevel() functions
          to manage comparator outputs (events and output level).

      (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT()
          function.

      (#) De-initialize the comparator using HAL_COMP_DeInit() function.

      (#) For safety purposes comparator(s) can be locked using HAL_COMP_Lock() function.
          Only a MCU reset can reset that protection.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_comp.c.

Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_cortex.c File Reference

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Functions
stm32f3xx_hal_cortex.c File Reference

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (pre-emption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.
void | HAL_MPU_Disable (void)
Disables the MPU also clears the HFNMIENA bit (ARM recommendation)
void | HAL_MPU_Enable (uint32_t MPU_Control)
Enables the MPU.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initializes and configures the Region and the memory to be protected.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.

Detailed Description

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================

    [..]
    *** How to configure Interrupts using CORTEX HAL driver ***
    ===========================================================
    [..]
    This section provides functions allowing to configure the NVIC interrupts (IRQ).
    The Cortex-M4 exceptions are managed by CMSIS functions.

    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function

     (#)  Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()

     (#)  Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()

     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
         The pending IRQ priority will be managed only by the sub priority.

     -@- IRQ priority order (sorted by highest to lowest priority):
        (+@) Lowest pre-emption priority
        (+@) Lowest sub priority
        (+@) Lowest hardware priority (IRQ number)

    [..]
    *** How to configure Systick using CORTEX HAL driver ***
    ========================================================
    [..]
    Setup SysTick Timer for time base

   (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
       is a CMSIS function that:
        (++) Configures the SysTick Reload register with value passed as function parameter.
        (++) Configures the SysTick IRQ priority to the lowest value (0x0FU).
        (++) Resets the SysTick Counter register.
        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
        (++) Enables the SysTick Interrupt.
        (++) Starts the SysTick Counter.

   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
       inside the stm32f3xx_hal_cortex.h file.

   (+) You can change the SysTick IRQ priority by calling the
       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.

   (+) To adjust the SysTick time base, use the following formula:

       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
       (++) Reload Value should not exceed 0xFFFFFF
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_cortex.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_crc.c File Reference

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stm32f3xx_hal_crc.c File Reference

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

static uint32_t | CRC_Handle_8 (CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
Enter 8-bit input data to the CRC calculator.
static uint32_t | CRC_Handle_16 (CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
Enter 16-bit input data to the CRC calculator.
HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
 ===============================================================================
                     ##### How to use this driver #####
 ===============================================================================
    [..]
         (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
         (+) Initialize CRC calculator
             (++)specify generating polynomial (IP default or non-default one)
             (++)specify initialization value (IP default or non-default one)
             (++)specify input data format
             (++)specify input or output data inversion mode if any
         (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
             input data buffer starting with the previously computed CRC as
             initialization value
         (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
             input data buffer starting with the defined initialization value
             (default or non-default) to initiate CRC calculation
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_crc.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_crc_ex.c File Reference

  • File List
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stm32f3xx_hal_crc_ex.c File Reference

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral.

Author:
MCD Application Team
================================================================================
            ##### How to use this driver #####
================================================================================
    [..]
         (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
         (+) Configure Input or Output data inversion
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_crc_ex.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_dac.c File Reference

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Functions
stm32f3xx_hal_dac.c File Reference

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.
__weak HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
__weak uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
__weak uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Returns the last data output value of the selected DAC channel.
__weak HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
__weak HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
__weak HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for Channel1.

Detailed Description

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
  ==============================================================================
                      ##### DAC Peripheral features #####
  ==============================================================================
    [..]
      *** DAC Channels ***
      ====================
    [..]
    The device integrates up to 3 12-bit Digital Analog Converters that can
    be used independently or simultaneously (dual mode):
      (#) DAC1 channel1 with DAC1_OUT1 (PA4) as output
      (#) DAC1 channel2 with DAC1_OUT2 (PA5) as output
          (for STM32F3 devices having 2 channels on DAC1)
      (#) DAC2 channel1 with DAC2_OUT1 (PA6) as output
          (for STM32F3 devices having 2 DAC)

      *** DAC Triggers ***
      ====================
    [..]
    Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
    and DAC1_OUT1/DAC1_OUT2/DAC2_OUT1 is available once writing to DHRx register.
    [..]
    Digital to Analog conversion can be triggered by:
      (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
          The used pin (GPIOx_PIN_9) must be configured in input mode.

      (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
          (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)

      (#) Software using DAC_TRIGGER_SOFTWARE

      *** DAC Buffer mode feature ***
      ===============================
      [..]
      Each DAC channel integrates an output buffer that can be used to
      reduce the output impedance, and to drive external loads directly
      without having to add an external operational amplifier.
      To enable, the output buffer use
      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
      Or
      An output switch
         (in STM32F303x4, STM32F303x6, STM32F303x8
             c, STM32F334x6, STM32F334x8
           & STM32F334xx).
      To enable, the output switch
      sConfig.DAC_OutputSwitch = DAC_OUTPUTSWITCH_ENABLE;
      [..]
      (@) Refer to the device datasheet for more details about output
          impedance value with and without output buffer.

      *** GPIO configurations guidelines ***
      =====================
      [..]
      When a DAC channel is used (ex channel1 on PA4) and the other is not
      (ex channel2 on PA5 is configured in Analog and disabled).
      Channel1 may disturb channel2 as coupling effect.
      Note that there is no coupling on channel2 as soon as channel2 is turned on.
      Coupling on adjacent channel could be avoided as follows:
      when unused PA5 is configured as INPUT PULL-UP or DOWN.
      PA5 is configured in ANALOG just before it is turned on.

       *** DAC wave generation feature ***
       ===================================
       [..]
       Both DAC channels of DAC1 can be used to generate
       note that wave generation is not available in DAC2.
         (#) Noise wave
         (#) Triangle wave

       Wave generation is NOT available in DAC2.

       *** DAC data format ***
       =======================
       [..]
       The DAC data format can be:
         (#) 8-bit right alignment using DAC_ALIGN_8B_R
         (#) 12-bit left alignment using DAC_ALIGN_12B_L
         (#) 12-bit right alignment using DAC_ALIGN_12B_R

       *** DAC data value to voltage correspondance ***
       ================================================
       [..]
       The analog output voltage on each DAC channel pin is determined
       by the following equation:
       [..]
       DAC_OUTx = VREF+ * DOR / 4095
       (+) with  DOR is the Data Output Register
       [..]
          VEF+ is the input voltage reference (refer to the device datasheet)
       [..]
        e.g. To set DAC_OUT1 to 0.7V, use
       (+)  Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3U * 868U) / 4095U = 0.7V

       *** DMA requests  ***
       =====================
       [..]
       A DMA1 or DMA2 request can be generated when an external trigger
       (but not a software trigger) occurs if DMA1 or DMA2 requests are
       enabled using HAL_DAC_Start_DMA().
       [..]
       DMA1 requests are mapped as following:
         (#) DAC1 channel1: mapped either on
         (++) DMA1 channel3
         (++) or DMA2 channel3 (for STM32F3 devices having 2 DMA)
             which must be already configured
         (#) DAC1 channel2:
             (for STM32F3 devices having 2 channels on DAC1)
             mapped either on
         (++) DMA1 channel4
         (++) or DMA2 channel4 (for STM32F3 devices having 2 DMA)
             which must be already configured

         (#) DAC2 channel1: mapped either on
             (for STM32F3 devices having 2 DAC)
         (++) DMA1 channel4
         (++) or DMA2 channel4 (for STM32F3 devices having 2 DMA)
             which must be already configured

       (@) For Dual mode and specific signal (Triangle and noise) generation please
       refer to Extended Features Driver description

                      ##### How to use this driver #####
  ==============================================================================
    [..]
      (+) DAC APB clock must be enabled to get write access to DAC
          registers using HAL_DAC_Init()
      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start()
       (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
       (+) Stop the DAC peripheral using HAL_DAC_Stop()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
           of data to be transferred at each end of conversion
       (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
       (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()

     *** DAC HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DAC HAL driver.

      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status

     [..]
      (@) You can refer to the DAC HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_dac.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_dac_ex.c File Reference

  • File List
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Functions
stm32f3xx_hal_dac_ex.c File Reference

DACEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

static void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
static void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
void | HAL_DAC_IRQHandler (struct __DAC_HandleTypeDef *hdac)
Handles DAC interrupt request This function uses the interruption of DMA underrun.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel2.

Detailed Description

DACEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral.

Author:
MCD Application Team
  ==============================================================================
                      ##### How to use this driver #####
  ==============================================================================
    [..]
      (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_dac_ex.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_dma.c File Reference

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Functions
stm32f3xx_hal_dma.c File Reference

DMA HAL module driver. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

static void | DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Set the DMA Transfer parameters.
static void | DMA_CalcBaseAndBitshift (DMA_HandleTypeDef *hdma)
Set the DMA base address and channel index depending on DMA instance.
HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handle DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Returns the DMA state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

DMA HAL module driver.

Author:
MCD Application Team This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   (#) Enable and configure the peripheral to be connected to the DMA Channel
       (except for internal SRAM / FLASH memories: no initialization is
       necessary). Please refer to Reference manual for connection between peripherals
       and DMA requests .

   (#) For a given Channel, program the required configuration through the following parameters:
       Transfer Direction, Source and Destination data formats,
       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
       using HAL_DMA_Init() function.

   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
       detection.

   (#) Use HAL_DMA_Abort() function to abort the current transfer

     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
     *** Polling mode IO operation ***
     =================================
    [..]
      (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
          address and destination address and the Length of data to be transferred
      (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
          case a fixed Timeout can be configured by User depending from his application.

     *** Interrupt mode IO operation ***
     ===================================
    [..]
      (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
      (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
      (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
          Source address and destination address and the Length of data to be transferred.
          In this case the DMA interrupt is configured
      (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
      (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
          add his own function by customization of function pointer XferCpltCallback and
          XferErrorCallback (i.e a member of DMA handle structure).

     *** DMA HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DMA HAL driver.

     [..]
      (@) You can refer to the DMA HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_dma.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_flash.c File Reference

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stm32f3xx_hal_flash.c File Reference

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral State functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

static void | FLASH_Program_HalfWord (uint32_t Address, uint16_t Data)
Program a half-word (16-bit) at a specified address.
static void | FLASH_SetErrorCode (void)
Set the specific FLASH error flag.
void | FLASH_PageErase (uint32_t PageAddress)
Erase the specified FLASH memory page.
HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program halfword, word or double word at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program halfword, word or double word at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Variables

FLASH_ProcessTypeDef pFlash

Detailed Description

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### FLASH peripheral features #####
  ==============================================================================
  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
       to the Flash memory. It implements the erase and program Flash memory operations
       and the read and write protection mechanisms.

  [..] The Flash memory interface accelerates code execution with a system of instruction
      prefetch.

  [..] The FLASH main features are:
      (+) Flash memory read operations
      (+) Flash memory program/erase operations
      (+) Read / write protections
      (+) Prefetch on I-Code
      (+) Option Bytes programming

                     ##### How to use this driver #####
  ==============================================================================
  [..]
      This driver provides functions and macros to configure and program the FLASH
      memory of all STM32F3xx devices.

      (#) FLASH Memory I/O Programming functions: this group includes all needed
          functions to erase and program the main memory:
        (++) Lock and Unlock the FLASH interface
        (++) Erase function: Erase page, erase all pages
        (++) Program functions: half word, word and doubleword
      (#) FLASH Option Bytes Programming functions: this group includes all needed
          functions to manage the Option Bytes:
        (++) Lock and Unlock the Option Bytes
        (++) Set/Reset the write protection
        (++) Set the Read protection Level
        (++) Program the user Option Bytes
        (++) Launch the Option Bytes loader
        (++) Erase Option Bytes
        (++) Program the data Option Bytes
        (++) Get the Write protection.
        (++) Get the user option bytes.

      (#) Interrupts and flags management functions : this group
          includes all needed functions to:
        (++) Handle FLASH interrupts
        (++) Wait for last FLASH operation according to its status
        (++) Get error flag status

  [..] In addition to these function, this driver includes a set of macros allowing
       to handle the following operations:

      (+) Set/Get the latency
      (+) Enable/Disable the prefetch buffer
      (+) Enable/Disable the half cycle access
      (+) Enable/Disable the FLASH interrupts
      (+) Monitor the FLASH flags status
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_flash.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_flash_ex.c File Reference

  • File List
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Defines | Functions | Variables
stm32f3xx_hal_flash_ex.c File Reference

Extended FLASH HAL module driver. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | FLASH_POSITION_IWDGSW_BIT (uint32_t)POSITION_VAL(FLASH_OBR_IWDG_SW)
#define | FLASH_POSITION_OB_USERDATA0_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA0)
#define | FLASH_POSITION_OB_USERDATA1_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA1)

Functions

static void | FLASH_MassErase (void)
Full erase of FLASH memory Bank.
void | FLASH_PageErase (uint32_t PageAddress)
Erase the specified FLASH memory page.
static HAL_StatusTypeDef | FLASH_OB_EnableWRP (uint32_t WriteProtectPage)
Enable the write protection of the desired pages.
static HAL_StatusTypeDef | FLASH_OB_DisableWRP (uint32_t WriteProtectPage)
Disable the write protection of the desired pages.
static HAL_StatusTypeDef | FLASH_OB_RDP_LevelConfig (uint8_t ReadProtectLevel)
Set the read protection level.
static HAL_StatusTypeDef | FLASH_OB_UserConfig (uint8_t UserConfig)
Program the FLASH User Option Byte.
static HAL_StatusTypeDef | FLASH_OB_ProgramData (uint32_t Address, uint8_t Data)
Programs a half word at a specified Option Byte Data address.
static uint32_t | FLASH_OB_GetWRP (void)
Return the FLASH Write Protection Option Bytes value.
static uint32_t | FLASH_OB_GetRDP (void)
Returns the FLASH Read Protection level.
static uint8_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBErase (void)
Erases the FLASH option bytes.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
uint32_t | HAL_FLASHEx_OBGetUserData (uint32_t DATAAdress)
Get the Option byte user data.
void | FLASH_PageErase (uint32_t PageAddress)
Erase the specified FLASH memory page.

Variables

FLASH_ProcessTypeDef pFlash

Detailed Description

Extended FLASH HAL module driver.

Author:
MCD Application Team This file provides firmware functions to manage the following functionalities of the FLASH peripheral: + Extended Initialization/de-initialization functions + Extended I/O operation functions + Extended Peripheral Control functions
  ==============================================================================
               ##### Flash peripheral extended features  #####
  ==============================================================================

                      ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to configure and program the FLASH memory
       of all STM32F3xxx devices. It includes

        (++) Set/Reset the write protection
        (++) Program the user Option Bytes
        (++) Get the Read protection Level
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_flash_ex.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_gpio.c File Reference

  • File List
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  • STM32F3xx_HAL_Driver
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Defines | Functions
stm32f3xx_hal_gpio.c File Reference

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | GPIO_MODE (0x00000003U)
#define | EXTI_MODE (0x10000000U)
#define | GPIO_MODE_IT (0x00010000U)
#define | GPIO_MODE_EVT (0x00020000U)
#define | RISING_EDGE (0x00100000U)
#define | FALLING_EDGE (0x00200000U)
#define | GPIO_OUTPUT_TYPE (0x00000010U)
#define | GPIO_NUMBER (16U)

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initialize the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Read the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Set or clear the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggle the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Lock GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

Author:
MCD Application Team
  ==============================================================================
                    ##### GPIO Peripheral features #####
  ==============================================================================
  [..]
    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
        configured by software in several modes:
        (++) Input mode
        (++) Analog mode
        (++) Output mode
        (++) Alternate function mode
        (++) External interrupt/event lines

    (+) During and just after reset, the alternate functions and external interrupt
        lines are not active and the I/O ports are configured in input floating mode.

    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
        activated or not.

    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
        type and the IO speed can be selected depending on the VDD value.

    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
        multiplexer that allows only one peripheral alternate function (AF) connected
       to an IO pin at a time. In this way, there can be no conflict between peripherals
       sharing the same IO pin.

    (+) All ports have external interrupt/event capability. To use external interrupt
        lines, the port must be configured in input mode. All available GPIO pins are
        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.

    (+) The external interrupt/event controller consists of up to 23 edge detectors
        (16 lines are connected to GPIO) for generating event/interrupt requests (each
        input line can be independently configured to select the type (interrupt or event)
        and the corresponding trigger event (rising or falling or both). Each line can
        also be masked independently.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().

    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
             structure.
        (++) In case of Output or alternate function mode selection: the speed is
             configured through "Speed" member from GPIO_InitTypeDef structure.
        (++) In alternate mode is selection, the alternate function connected to the IO
             is configured through "Alternate" member from GPIO_InitTypeDef structure.
        (++) Analog mode is required when a pin is to be used as ADC channel
             or DAC output.
        (++) In case of external interrupt/event selection the "Mode" member from
             GPIO_InitTypeDef structure select the type (interrupt or event) and
             the corresponding trigger event (rising or falling or both).

    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
        HAL_NVIC_EnableIRQ().

    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().

    (#) To set/reset the level of a pin configured in output mode use
        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().

   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().

    (#) During and just after reset, the alternate functions are not
        active and the GPIO pins are configured in input floating mode (except JTAG
        pins).

    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
        (PC14 and PC15U, respectively) when the LSE oscillator is off. The LSE has
        priority over the GPIO function.

    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
        general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
        The HSE has priority over the GPIO function.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_gpio.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_i2c.c File Reference

  • File List
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  • Firmware
  • Drivers
  • STM32F3xx_HAL_Driver
  • Src
Defines | Functions
stm32f3xx_hal_i2c.c File Reference

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFU)
#define | I2C_TIMEOUT_ADDR (10000U)
#define | I2C_TIMEOUT_BUSY (25U)
#define | I2C_TIMEOUT_DIR (25U)
#define | I2C_TIMEOUT_RXNE (25U)
#define | I2C_TIMEOUT_STOPF (25U)
#define | I2C_TIMEOUT_TC (25U)
#define | I2C_TIMEOUT_TCR (25U)
#define | I2C_TIMEOUT_TXIS (25U)
#define | I2C_TIMEOUT_FLAG (25U)
#define | MAX_NBYTE_SIZE 255U
#define | SlaveAddr_SHIFT 7U
#define | SlaveAddr_MSK 0x06U
#define | I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY))))
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))
#define | I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))
#define | I2C_XFER_TX_IT (0x00000001U)
#define | I2C_XFER_RX_IT (0x00000002U)
#define | I2C_XFER_LISTEN_IT (0x00000004U)
#define | I2C_XFER_ERROR_IT (0x00000011U)
#define | I2C_XFER_CPLT_IT (0x00000012U)
#define | I2C_XFER_RELOAD_IT (0x00000012U)
#define | I2C_NO_OPTION_FRAME (0xFFFF0000U)
#define | I2C_GET_DMA_REMAIN_DATA(__HANDLE__)

Functions

static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static void | I2C_DMAAbort (DMA_HandleTypeDef *hdma)
DMA I2C communication abort callback (To be called at end of DMA Abort procedure).
static void | I2C_ITAddrCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Address complete process callback.
static void | I2C_ITMasterSequentialCplt (I2C_HandleTypeDef *hi2c)
I2C Master sequential complete process.
static void | I2C_ITSlaveSequentialCplt (I2C_HandleTypeDef *hi2c)
I2C Slave sequential complete process.
static void | I2C_ITMasterCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Master complete process.
static void | I2C_ITSlaveCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Slave complete process.
static void | I2C_ITListenCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Listen complete process.
static void | I2C_ITError (I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
I2C interrupts error process.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_Master_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Slave_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Master_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
static HAL_StatusTypeDef | I2C_Slave_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnTXISFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsAcknowledgeFailed (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles Acknowledge failed detection during an I2C Communication.
static HAL_StatusTypeDef | I2C_Enable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static HAL_StatusTypeDef | I2C_Disable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static void | I2C_Flush_TXDR (I2C_HandleTypeDef *hi2c)
I2C Tx data register flush process.
static void | I2C_TransferConfig (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The I2C HAL driver can be used as follows:

    (#) Declare a I2C_HandleTypeDef handle structure, for example:
        I2C_HandleTypeDef  hi2c;

    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
        (##) Enable the I2Cx interface clock
        (##) I2C pins configuration
            (+++) Enable the clock for the I2C GPIOs
            (+++) Configure I2C pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the I2Cx interrupt priority
            (+++) Enable the NVIC I2C IRQ Channel
        (##) DMA Configuration if you need to use DMA process
            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
            (+++) Enable the DMAx interface clock using
            (+++) Configure the DMA handle parameters
            (+++) Configure the DMA Tx or Rx channel
            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
                  the DMA Tx or Rx channel

    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.

    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.

    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()

    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()

    *** Polling mode IO MEM operation ***
    =====================================
    [..]
      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** Interrupt mode IO sequential operation ***
    ==============================================
    [..]
      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
          when a direction change during transfer
    [..]
      (+) A specific option field manage the different steps of a sequential transfer
      (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
                            and data to transfer without a final stop condition
      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface
                            several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT())
      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to transfer
                            if no direction change and without a final stop condition in both cases
      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to transfer
                            if no direction change and with a final stop condition in both cases

      (+) Differents sequential I2C interfaces are listed below:
      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** Interrupt mode IO MEM operation ***
    =======================================
    [..]
      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
          HAL_I2C_Mem_Write_IT()
      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
          HAL_I2C_Mem_Read_IT()
      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()

    *** DMA mode IO operation ***
    ==============================
    [..]
      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Master_Transmit_DMA()
      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Master_Receive_DMA()
      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Slave_Transmit_DMA()
      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Slave_Receive_DMA()
      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** DMA mode IO MEM operation ***
    =================================
    [..]
      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
          HAL_I2C_Mem_Write_DMA()
      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
          HAL_I2C_Mem_Read_DMA()
      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()

     *** I2C HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in I2C HAL driver.

      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
      (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
      (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt

     [..]
       (@) You can refer to the I2C HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_i2c.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_i2c_ex.c File Reference

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stm32f3xx_hal_i2c_ex.c File Reference

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from stop mode.
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from stop mode.
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions.

Author:
MCD Application Team
  ==============================================================================
               ##### I2C peripheral Extended features  #####
  ==============================================================================

  [..] Comparing to other previous devices, the I2C interface for STM32F3xx
       devices contains the following additional features

       (+) Possibility to disable or enable Analog Noise Filter
       (+) Use of a configured Digital Noise Filter
       (+) Disable or enable wakeup from Stop mode

                     ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
          (++) HAL_I2CEx_EnableWakeUp()
          (++) HAL_I2CEx_DisableWakeUp()
    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
          (++) HAL_I2CEx_EnableFastModePlus()
          (++) HAL_I2CEx_DisableFastModePlus()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_i2c_ex.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_i2s.c File Reference

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  • STM32F3xx_HAL_Driver
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Functions
stm32f3xx_hal_i2s.c File Reference

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

static void | I2S_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process complete callback.
static void | I2S_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process half complete callback.
static void | I2S_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process complete callback.
static void | I2S_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process half complete callback.
static void | I2S_DMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
static void | I2S_Transmit_IT (I2S_HandleTypeDef *hi2s)
Transmit an amount of data in non-blocking mode with Interrupt.
static void | I2S_Receive_IT (I2S_HandleTypeDef *hi2s)
Receive an amount of data in non-blocking mode with Interrupt.
static HAL_StatusTypeDef | I2S_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
This function handles I2S Communication Timeout.
__weak HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.
HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
__weak HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio stream playing from the Media.
__weak HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
__weak HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.
HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
 ===============================================================================
                  ##### How to use this driver #####
 ===============================================================================
 [..]
    The I2S HAL driver can be used as follows:

    (#) Declare a I2S_HandleTypeDef handle structure.
    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
        (##) Enable the SPIx interface clock.
        (##) I2S pins configuration:
            (+++) Enable the clock for the I2S GPIOs.
            (+++) Configure these I2S pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
             and HAL_I2S_Receive_IT() APIs).
            (+++) Configure the I2Sx interrupt priority.
            (+++) Enable the NVIC I2S IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
             and HAL_I2S_Receive_DMA() APIs:
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Channel.
            (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                DMA Tx/Rx Channel.

   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
       using HAL_I2S_Init() function.

   -@- The specific I2S interrupts (Transmission complete interrupt,
       RXNE interrupt and Error Interrupts) will be managed using the macros
       __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
   -@- Make sure that either:
       (+@) I2S clock is configured based on SYSCLK or
       (+@) External clock source is configured after setting correctly
            the define constant EXTERNAL_CLOCK_VALUE in the stm32f3xx_hal_conf.h file.

   (#) Three mode of operations are available within this driver :

   *** Polling mode IO operation ***
   =================================
   [..]
     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()

   *** Interrupt mode IO operation ***
   ===================================
   [..]
     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback

   *** DMA mode IO operation ***
   ==============================
   [..]
     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback
     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()

   *** I2S HAL driver macros list ***
   =============================================
   [..]
     Below the list of most used macros in I2S HAL driver.

      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not

    [..]
      (@) You can refer to the I2S HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_i2s.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_i2s_ex.c File Reference

  • File List
  • Globals
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  • Drivers
  • STM32F3xx_HAL_Driver
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Functions
stm32f3xx_hal_i2s_ex.c File Reference

I2S Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2S Extended peripheral: + Extended features Functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

__weak HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.

Detailed Description

I2S Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2S Extended peripheral: + Extended features Functions.

Author:
MCD Application Team
  ==============================================================================
                    ##### I2S Extended features #####
  ==============================================================================
 [..]
    (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
        data simultaneously using two data lines. Each SPI peripheral has an extended block
        called I2Sxext ie. I2S2ext for SPI2 and I2S3ext for SPI3).
    (#) The Extended block is not a full SPI IP, it is used only as I2S slave to
        implement full duplex mode. The Extended block uses the same clock sources
        as its master.

    (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.

     -@- Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
         I2Sx can be I2S2 or I2S3.

 ===============================================================================
                  ##### How to use this driver #####
 ===============================================================================
 [..]
   Three mode of operations are available within this driver :

   *** Polling mode IO operation ***
   =================================
   [..]
     (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive()

   *** Interrupt mode IO operation ***
   ===================================
   [..]
     (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback

   *** DMA mode IO operation ***
   ==============================
   [..]
     (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback
     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_i2s_ex.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_irda.c File Reference

  • File List
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Defines | Functions
stm32f3xx_hal_irda.c File Reference

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | IRDA_TEACK_REACK_TIMEOUT 1000
#define | IRDA_CR1_FIELDS

Functions

static HAL_StatusTypeDef | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configure the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_CheckIdleState (IRDA_HandleTypeDef *hirda)
Check the IRDA Idle State.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle IRDA Communication Timeout.
static void | IRDA_EndTxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
static void | IRDA_EndRxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static void | IRDA_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | IRDA_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | IRDA_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | IRDA_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | IRDA_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static HAL_StatusTypeDef | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in interrupt mode.
static HAL_StatusTypeDef | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The IRDA HAL driver can be used as follows:

    (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
        in setting the associated USART or UART in IRDA mode:
        (++) Enable the USARTx/UARTx interface clock.
        (++) USARTx/UARTx pins configuration:
            (+++) Enable the clock for the USARTx/UARTx GPIOs.
            (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
        (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
             and HAL_IRDA_Receive_IT() APIs):
            (+++) Configure the USARTx/UARTx interrupt priority.
            (+++) Enable the NVIC USARTx/UARTx IRQ handle.
            (+++) The specific IRDA interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.

        (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
             and HAL_IRDA_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
        the normal or low power mode and the clock prescaler in the hirda handle Init structure.

    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
        (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_IRDA_MspInit() API.

         -@@- The specific IRDA interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
             __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.

    (#) Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
       (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
       (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()

     *** IRDA HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IRDA HAL driver.

       (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
       (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
       (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
       (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
       (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
       (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
       (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled

     [..]
       (@) You can refer to the IRDA HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_irda.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_iwdg.c File Reference

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stm32f3xx_hal_iwdg.c File Reference

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | HAL_IWDG_DEFAULT_TIMEOUT 48u

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions.

Author:
MCD Application Team
  ==============================================================================
                    ##### IWDG Generic features #####
  ==============================================================================
  [..]
    (+) The IWDG can be started by either software or hardware (configurable
        through option byte).

    (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
        if the main clock fails.

    (+) Once the IWDG is started, the LSI is forced ON and both can not be
        disabled. The counter starts counting down from the reset value (0xFFFU).
        When it reaches the end of count value (0x000U) a reset signal is
        generated (IWDG reset).

    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
        the IWDG_RLR value is reloaded in the counter and the watchdog reset is
        prevented.

    (+) The IWDG is implemented in the VDD voltage domain that is still functional
        in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
        reset occurs.

    (+) Debug mode : When the microcontroller enters debug mode (core halted),
        the IWDG counter either continues to work normally or stops, depending
        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros

    [..] Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s
         The IWDG timeout may vary due to LSI frequency dispersion. STM32F3xx
         devices provide the capability to measure the LSI frequency (LSI clock
         connected internally to TIM16 CH1 input capture). The measured value
         can be used to have an IWDG timeout with an acceptable accuracy.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Use IWDG using HAL_IWDG_Init() function to :
      (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
           clock is forced ON and IWDG counter starts downcounting.
      (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
           IWDG_WINR.
      (++) Configure the IWDG prescaler and counter reload value. This reload
           value will be loaded in the IWDG counter each time the watchdog is
           reloaded, then the IWDG will start counting down from this value.
      (++) wait for status flags to be reset"
      (++) Depending on window parameter:
        (+++) If Window Init parameter is same as Window register value,
             nothing more is done but reload counter value in order to exit
             function withy exact time base.
        (+++) Else modify Window register. This will automatically reload
             watchdog counter.

    (#) Then the application program must refresh the IWDG counter at regular
        intervals during normal operation to prevent an MCU reset, using
        HAL_IWDG_Refresh() function.

     *** IWDG HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IWDG HAL driver:
      (+) __HAL_IWDG_START: Enable the IWDG peripheral
      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
          the reload register
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_iwdg.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pcd.c File Reference

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  • STM32F3xx_HAL_Driver
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Defines | Functions
stm32f3xx_hal_pcd.c File Reference

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | BTABLE_ADDRESS (0x000U)

Functions

static HAL_StatusTypeDef | PCD_EP_ISR_Handler (PCD_HandleTypeDef *hpcd)
This function handles PCD Endpoint interrupt request.
HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start the USB device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop the USB device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data out stage callbacks.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callbacks.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callbacks.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callbacks.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callbacks.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callbacks.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callbacks.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callbacks.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callbacks.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callbacks.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint16_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD state.

Detailed Description

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
    [..]
      The PCD HAL driver can be used as follows:

     (#) Declare a PCD_HandleTypeDef handle structure, for example:
         PCD_HandleTypeDef  hpcd;

     (#) Fill parameters of Init structure in HCD handle

     (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...)

     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
         (##) Enable the PCD/USB Low Level interface clock using
              (+++) __HAL_RCC_USB_CLK_ENABLE();

         (##) Initialize the related GPIO clocks
         (##) Configure PCD pin-out
         (##) Configure PCD NVIC interrupt

     (#)Associate the Upper USB device stack to the HAL PCD Driver:
         (##) hpcd.pData = pdev;

     (#)Enable HCD transmission and reception:
         (##) HAL_PCD_Start();
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_pcd.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pcd_ex.c File Reference

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Functions
stm32f3xx_hal_pcd_ex.c File Reference

Extended PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Configuration of the PMA for EP. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_PCDEx_PMAConfig (PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress)
Configure PMA for EP.
void | PCD_WritePMA (USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
Copy a buffer from user memory area to packet memory area (PMA)
void | PCD_ReadPMA (USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
Copy a buffer from user memory area to packet memory area (PMA)
__weak void | HAL_PCDEx_SetConnectionState (PCD_HandleTypeDef *hpcd, uint8_t state)
Software Device Connection.

Detailed Description

Extended PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Configuration of the PMA for EP.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_pcd_ex.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pwr.c File Reference

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stm32f3xx_hal_pwr.c File Reference

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions. More...

Go to the source code of this file.

Functions

void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinx)
Enables the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disables the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enters Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enters STOP mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enters STANDBY mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enables CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disables CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DeInit (void)
Deinitializes the PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_DisableBkUpAccess (void)
Disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Detailed Description

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"

/** @addtogroup STM32F3xx_HAL_Driver
  * @{
  */

/** @defgroup PWR PWR
  * @brief PWR HAL module driver
  * @{
  */

#ifdef HAL_PWR_MODULE_ENABLED

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/

/** @defgroup PWR_Exported_Functions PWR Exported Functions
  * @{
  */

/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
  *  @brief    Initialization and de-initialization functions
  *
@verbatim
 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]
      After reset, the backup domain (RTC registers, RTC backup data
      registers and backup SRAM) is protected against possible unwanted
      write accesses.
      To enable access to the RTC Domain and RTC registers, proceed as follows:
        (+) Enable the Power Controller (PWR) APB1 interface clock using the
            __HAL_RCC_PWR_CLK_ENABLE() macro.
        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.

Definition in file stm32f3xx_hal_pwr.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pwr_ex.c File Reference

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Defines | Functions
stm32f3xx_hal_pwr_ex.c File Reference

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | PVD_MODE_IT (0x00010000U)
#define | PVD_MODE_EVT (0x00020000U)
#define | PVD_RISING_EDGE (0x00000001U)
#define | PVD_FALLING_EDGE (0x00000002U)

Functions

void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enables the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disables the Power Voltage Detector(PVD).
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.
void | HAL_PWREx_EnableSDADC (uint32_t Analogx)
Enables the SDADC peripheral functionaliy.
void | HAL_PWREx_DisableSDADC (uint32_t Analogx)
Disables the SDADC peripheral functionaliy.

Detailed Description

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_pwr_ex.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_rcc.c File Reference

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Defines | Functions | Variables
stm32f3xx_hal_rcc.c File Reference

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE)
#define | RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1)
#define | RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2)
#define | MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8

Functions

void | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO pin.
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_DisableCSS (void)
Disables the Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.

Variables

const uint8_t | aPLLMULFactorTable [16]
const uint8_t | aPredivFactorTable [16]

Detailed Description

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
  ==============================================================================
                      ##### RCC specific features #####
  ==============================================================================
    [..]
      After reset the device is running from Internal High Speed oscillator
      (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
      and all peripherals are off except internal SRAM, Flash and JTAG.
      (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
          all peripherals mapped on these buses are running at HSI speed.
      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
      (+) All GPIOs are in input floating state, except the JTAG pins which
          are assigned to be used for debug purpose.
    [..] Once the device started from reset, the user application has to:
      (+) Configure the clock source to be used to drive the System clock
          (if the application needs higher frequency/performance)
      (+) Configure the System clock frequency and Flash settings
      (+) Configure the AHB and APB buses prescalers
      (+) Enable the clock for the peripheral(s) to be used
      (+) Configure the clock source(s) for peripherals whose clocks are not
          derived from the System clock (RTC, ADC, I2C, I2S, TIM, USB FS)

                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
        (++) AHB & APB peripherals, 1 dummy read is necessary

    [..]
      Workarounds:
      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_rcc.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_rcc_ex.c File Reference

  • File List
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Functions
stm32f3xx_hal_rcc_ex.c File Reference

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

static uint32_t | RCC_GetPLLCLKFreq (void)
HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Returns the peripheral clock frequency.

Detailed Description

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_rcc_ex.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_rtc.c File Reference

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Functions
stm32f3xx_hal_rtc.c File Reference

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC according to the specified parameters in the RTC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
@addtogroup RTC_Exported_Functions_Group4 Peripheral Control functions
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
@addtogroup RTC_Exported_Functions_Group5 Peripheral State functions
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
@addtogroup RTC_Private_Functions RTC Private Functions
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Detailed Description

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management.

Author:
MCD Application Team

 ===============================================================================
                          ##### RTC Operating Condition #####
 ===============================================================================
    [..] The real-time clock (RTC) and the RTC backup registers can be powered
         from the VBAT voltage when the main VDD supply is powered off.
         To retain the content of the RTC backup registers and supply the RTC
         when VDD is turned off, VBAT pin can be connected to an optional
         standby voltage supplied by a battery or by another source.

    [..] To allow the RTC to operate even when the main digital supply (VDD)
         is turned off, the VBAT pin powers the following blocks:
           (#) The RTC
           (#) The LSE oscillator
           (#) PC13 to PC15 I/Os (when available)

    [..] When the backup domain is supplied by VDD (analog switch connected
         to VDD), the following functions are available:
           (#) PC14 and PC15 can be used as either GPIO or LSE pins
           (#) PC13 can be used as a GPIO or as the RTC_OUT pin

    [..] When the backup domain is supplied by VBAT (analog switch connected
         to VBAT because VDD is not present), the following functions are available:
           (#) PC14 and PC15 can be used as LSE pins only
           (#) PC13 can be used as the RTC_OUT pin

                        ##### Backup Domain Reset #####
 ===============================================================================
    [..] The backup domain reset sets all RTC registers and the RCC_BDCR
         register to their reset values.
         A backup domain reset is generated when one of the following events
         occurs:
           (#) Software reset, triggered by setting the BDRST bit in the
               RCC Backup domain control register (RCC_BDCR).
           (#) VDD or VBAT power on, if both supplies have previously been
               powered off.

                   ##### Backup Domain Access #####
 ===================================================================
    [..] After reset, the backup domain (RTC registers, RTC backup data
         registers and backup SRAM) is protected against possible unwanted write
         accesses.

    [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
           (#) Enable the Power Controller (PWR) APB1 interface clock using the
               __HAL_RCC_PWR_CLK_ENABLE() function.
           (#) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
           (#) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
           (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.

                  ##### How to use RTC Driver #####
 ===================================================================
    [..]
        (+) Enable the RTC domain access (see description in the section above).
        (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
            format using the HAL_RTC_Init() function.

    *** Time and Date configuration ***
    ===================================
    [..]
        (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
            and HAL_RTC_SetDate() functions.
        (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.

    *** Alarm configuration ***
    ===========================
    [..]
        (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
            You can also configure the RTC Alarm with interrupt mode using the
            HAL_RTC_SetAlarm_IT() function.
        (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.

    *** RTC Wakeup configuration ***
    ================================
    [..]
        (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
            function. You can also configure the RTC Wakeup timer with interrupt mode
            using the HAL_RTC_SetWakeUpTimer_IT() function.
        (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer()
            function.

    *** TimeStamp configuration ***
    ===============================
    [..]
        (+) Configure the RTC_AF trigger and enables the RTC TimeStamp using the
            HAL_RTC_SetTimeStamp() function. You can also configure the RTC TimeStamp with
            interrupt mode using the HAL_RTC_SetTimeStamp_IT() function.
        (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
            function.

    *** Tamper configuration ***
    ============================
    [..]
        (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge
            or Level according to the Tamper filter (if equal to 0 Edge else Level)
            value, sampling frequency, precharge or discharge and Pull-UP using the
            HAL_RTC_SetTamper() function. You can configure RTC Tamper with interrupt
            mode using HAL_RTC_SetTamper_IT() function.

    *** Backup Data Registers configuration ***
    ===========================================
    [..]
        (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
            function.
        (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
            function.

                  ##### RTC and low power modes #####
 ===================================================================
    [..] The MCU can be woken up from a low power mode by an RTC alternate
         function.
    [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
         RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
         These RTC alternate functions can wake up the system from the Stop and
         Standby low power modes.
    [..] The system can also wake up from low power modes without depending
         on an external interrupt (Auto-wakeup mode), by using the RTC alarm
         or the RTC wakeup events.
    [..] The RTC provides a programmable time base for waking up from the
         Stop or Standby mode at regular intervals.
         Wakeup from STOP and Standby modes is possible only when the RTC clock source
         is LSE or LSI.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_rtc.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_rtc_ex.c File Reference

  • File List
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  • STM32F3xx_HAL_Driver
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Functions
stm32f3xx_hal_rtc_ex.c File Reference

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 3 Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
uint32_t | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.
__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmB Polling request.

Detailed Description

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions.

Author:
MCD Application Team
  ==============================================================================
                  ##### How to use this driver #####
  ==============================================================================
  [..]
    (+) Enable the RTC domain access.
    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
        format using the HAL_RTC_Init() function.

  *** RTC Wakeup configuration ***
  ================================
  [..]
    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
        function. You can also configure the RTC Wakeup timer with interrupt mode
        using the HAL_RTCEx_SetWakeUpTimer_IT() function.
    (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
        function.

  *** TimeStamp configuration ***
  ===============================
  [..]
        (+) Configure the RTC_AF trigger and enable the RTC TimeStamp using the
        HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with
        interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function.
    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
        function.
    (+) The TIMESTAMP alternate function is mapped to RTC_AF1 (PC13U).

  *** Tamper configuration ***
  ============================
  [..]
        (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
        or Level according to the Tamper filter (if equal to 0 Edge else Level)
        value, sampling frequency, precharge or discharge and Pull-UP using the
        HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt
        mode using HAL_RTCEx_SetTamper_IT() function.
    (+) The TAMPER1 alternate function is mapped to RTC_AF1 (PC13U).

  *** Backup Data Registers configuration ***
  ===========================================
  [..]
    (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
        function.
    (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
        function.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_rtc_ex.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_sdadc.c File Reference

  • File List
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  • STM32F3xx_HAL_Driver
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Defines | Functions
stm32f3xx_hal_sdadc.c File Reference

This file provides firmware functions to manage the following functionalities of the Sigma-Delta Analog to Digital Converter (SDADC) peripherals: + Initialization and Configuration + Regular Channels Configuration + Injected channels Configuration + Power saving + Regular/Injected Channels DMA Configuration + Interrupts and flags management. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | SDADC_TIMEOUT 200
#define | SDADC_CONFREG_OFFSET 0x00000020
#define | SDADC_JDATAR_CH_OFFSET 24
#define | SDADC_MSB_MASK 0xFFFF0000U
#define | SDADC_LSB_MASK 0x0000FFFFU

Functions

static HAL_StatusTypeDef | SDADC_EnterInitMode (SDADC_HandleTypeDef *hsdadc)
This function allows to enter in init mode for SDADC instance.
static void | SDADC_ExitInitMode (SDADC_HandleTypeDef *hsdadc)
This function allows to exit from init mode for SDADC instance.
static uint32_t | SDADC_GetInjChannelsNbr (uint32_t Channels)
This function allows to get the number of injected channels.
static HAL_StatusTypeDef | SDADC_RegConvStart (SDADC_HandleTypeDef *hsdadc)
This function allows to really start regular conversion.
static HAL_StatusTypeDef | SDADC_RegConvStop (SDADC_HandleTypeDef *hsdadc)
This function allows to really stop regular conversion.
static HAL_StatusTypeDef | SDADC_InjConvStart (SDADC_HandleTypeDef *hsdadc)
This function allows to really start injected conversion.
static HAL_StatusTypeDef | SDADC_InjConvStop (SDADC_HandleTypeDef *hsdadc)
This function allows to really stop injected conversion.
static void | SDADC_DMARegularHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback for regular conversion.
static void | SDADC_DMARegularConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback for regular conversion.
static void | SDADC_DMAInjectedHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback for injected conversion.
static void | SDADC_DMAInjectedConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback for injected conversion.
static void | SDADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
HAL_StatusTypeDef | HAL_SDADC_Init (SDADC_HandleTypeDef *hsdadc)
Initializes the SDADC according to the specified parameters in the SDADC_InitTypeDef structure.
HAL_StatusTypeDef | HAL_SDADC_DeInit (SDADC_HandleTypeDef *hsdadc)
De-initializes the SDADC.
__weak void | HAL_SDADC_MspInit (SDADC_HandleTypeDef *hsdadc)
Initializes the SDADC MSP.
__weak void | HAL_SDADC_MspDeInit (SDADC_HandleTypeDef *hsdadc)
De-initializes the SDADC MSP.
HAL_StatusTypeDef | HAL_SDADC_PrepareChannelConfig (SDADC_HandleTypeDef *hsdadc, uint32_t ConfIndex, SDADC_ConfParamTypeDef *ConfParamStruct)
This function allows the user to set parameters for a configuration.
HAL_StatusTypeDef | HAL_SDADC_AssociateChannelConfig (SDADC_HandleTypeDef *hsdadc, uint32_t Channel, uint32_t ConfIndex)
This function allows the user to associate a channel with one of the available configurations.
HAL_StatusTypeDef | HAL_SDADC_ConfigChannel (SDADC_HandleTypeDef *hsdadc, uint32_t Channel, uint32_t ContinuousMode)
This function allows to select channel for regular conversion and to enable/disable continuous mode for regular conversion.
HAL_StatusTypeDef | HAL_SDADC_InjectedConfigChannel (SDADC_HandleTypeDef *hsdadc, uint32_t Channel, uint32_t ContinuousMode)
This function allows to select channels for injected conversion and to enable/disable continuous mode for injected conversion.
HAL_StatusTypeDef | HAL_SDADC_SelectRegularTrigger (SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
This function allows to select trigger for regular conversions.
HAL_StatusTypeDef | HAL_SDADC_SelectInjectedTrigger (SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
This function allows to select trigger for injected conversions.
HAL_StatusTypeDef | HAL_SDADC_SelectInjectedExtTrigger (SDADC_HandleTypeDef *hsdadc, uint32_t InjectedExtTrigger, uint32_t ExtTriggerEdge)
This function allows to select and configure injected external trigger.
HAL_StatusTypeDef | HAL_SDADC_SelectInjectedDelay (SDADC_HandleTypeDef *hsdadc, uint32_t InjectedDelay)
This function allows to enable/disable delay addition for injected conversions.
HAL_StatusTypeDef | HAL_SDADC_MultiModeConfigChannel (SDADC_HandleTypeDef *hsdadc, uint32_t MultimodeType)
This function allows to configure multimode for regular conversions.
HAL_StatusTypeDef | HAL_SDADC_InjectedMultiModeConfigChannel (SDADC_HandleTypeDef *hsdadc, uint32_t MultimodeType)
This function allows to configure multimode for injected conversions.
HAL_StatusTypeDef | HAL_SDADC_CalibrationStart (SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence)
This function allows to start calibration in polling mode.
HAL_StatusTypeDef | HAL_SDADC_PollForCalibEvent (SDADC_HandleTypeDef *hsdadc, uint32_t Timeout)
This function allows to poll for the end of calibration.
HAL_StatusTypeDef | HAL_SDADC_CalibrationStart_IT (SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence)
This function allows to start calibration in interrupt mode.
HAL_StatusTypeDef | HAL_SDADC_Start (SDADC_HandleTypeDef *hsdadc)
This function allows to start regular conversion in polling mode.
HAL_StatusTypeDef | HAL_SDADC_PollForConversion (SDADC_HandleTypeDef *hsdadc, uint32_t Timeout)
This function allows to poll for the end of regular conversion.
HAL_StatusTypeDef | HAL_SDADC_Stop (SDADC_HandleTypeDef *hsdadc)
This function allows to stop regular conversion in polling mode.
HAL_StatusTypeDef | HAL_SDADC_Start_IT (SDADC_HandleTypeDef *hsdadc)
This function allows to start regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_SDADC_Stop_IT (SDADC_HandleTypeDef *hsdadc)
This function allows to stop regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_SDADC_Start_DMA (SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode.
HAL_StatusTypeDef | HAL_SDADC_Stop_DMA (SDADC_HandleTypeDef *hsdadc)
This function allows to stop regular conversion in DMA mode.
uint32_t | HAL_SDADC_GetValue (SDADC_HandleTypeDef *hsdadc)
This function allows to get regular conversion value.
HAL_StatusTypeDef | HAL_SDADC_InjectedStart (SDADC_HandleTypeDef *hsdadc)
This function allows to start injected conversion in polling mode.
HAL_StatusTypeDef | HAL_SDADC_PollForInjectedConversion (SDADC_HandleTypeDef *hsdadc, uint32_t Timeout)
This function allows to poll for the end of injected conversion.
HAL_StatusTypeDef | HAL_SDADC_InjectedStop (SDADC_HandleTypeDef *hsdadc)
This function allows to stop injected conversion in polling mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedStart_IT (SDADC_HandleTypeDef *hsdadc)
This function allows to start injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedStop_IT (SDADC_HandleTypeDef *hsdadc)
This function allows to stop injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedStart_DMA (SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedStop_DMA (SDADC_HandleTypeDef *hsdadc)
This function allows to stop injected conversion in DMA mode.
uint32_t | HAL_SDADC_InjectedGetValue (SDADC_HandleTypeDef *hsdadc, uint32_t *Channel)
This function allows to get injected conversion value.
HAL_StatusTypeDef | HAL_SDADC_MultiModeStart_DMA (SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length)
This function allows to start multimode regular conversions in DMA mode.
HAL_StatusTypeDef | HAL_SDADC_MultiModeStop_DMA (SDADC_HandleTypeDef *hsdadc)
This function allows to stop multimode regular conversions in DMA mode.
uint32_t | HAL_SDADC_MultiModeGetValue (SDADC_HandleTypeDef *hsdadc)
This function allows to get multimode regular conversion value.
HAL_StatusTypeDef | HAL_SDADC_InjectedMultiModeStart_DMA (SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length)
This function allows to start multimode injected conversions in DMA mode.
HAL_StatusTypeDef | HAL_SDADC_InjectedMultiModeStop_DMA (SDADC_HandleTypeDef *hsdadc)
This function allows to stop multimode injected conversions in DMA mode.
uint32_t | HAL_SDADC_InjectedMultiModeGetValue (SDADC_HandleTypeDef *hsdadc)
This function allows to get multimode injected conversion value.
void | HAL_SDADC_IRQHandler (SDADC_HandleTypeDef *hsdadc)
This function handles the SDADC interrupts.
__weak void | HAL_SDADC_CalibrationCpltCallback (SDADC_HandleTypeDef *hsdadc)
Calibration complete callback.
__weak void | HAL_SDADC_ConvHalfCpltCallback (SDADC_HandleTypeDef *hsdadc)
Half regular conversion complete callback.
__weak void | HAL_SDADC_ConvCpltCallback (SDADC_HandleTypeDef *hsdadc)
Regular conversion complete callback.
__weak void | HAL_SDADC_InjectedConvHalfCpltCallback (SDADC_HandleTypeDef *hsdadc)
Half injected conversion complete callback.
__weak void | HAL_SDADC_InjectedConvCpltCallback (SDADC_HandleTypeDef *hsdadc)
Injected conversion complete callback.
__weak void | HAL_SDADC_ErrorCallback (SDADC_HandleTypeDef *hsdadc)
Error callback.
HAL_SDADC_StateTypeDef | HAL_SDADC_GetState (SDADC_HandleTypeDef *hsdadc)
This function allows to get the current SDADC state.
uint32_t | HAL_SDADC_GetError (SDADC_HandleTypeDef *hsdadc)
This function allows to get the current SDADC error code.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Sigma-Delta Analog to Digital Converter (SDADC) peripherals: + Initialization and Configuration + Regular Channels Configuration + Injected channels Configuration + Power saving + Regular/Injected Channels DMA Configuration + Interrupts and flags management.

Author:
MCD Application Team
  ==============================================================================
                    ##### SDADC specific features #####
  ==============================================================================
  [..]
  (#) 16-bit sigma delta architecture.
  (#) Self calibration.
  (#) Interrupt generation at the end of calibration, regular/injected conversion
      and in case of overrun events.
  (#) Single and continuous conversion modes.
  (#) External trigger option with configurable polarity for injected conversion.
  (#) Multi mode (synchronized another SDADC with SDADC1).
  (#) DMA request generation during regular or injected channel conversion.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    *** Initialization ***
    ======================
    [..]
      (#) As prerequisite, fill in the HAL_SDADC_MspInit() :
        (++) Enable SDADCx clock interface with __SDADCx_CLK_ENABLE().
        (++) Configure SDADCx clock divider with HAL_RCCEx_PeriphCLKConfig.
        (++) Enable power on SDADC with HAL_PWREx_EnableSDADC().
        (++) Enable the clocks for the SDADC GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
        (++) Configure these SDADC pins in analog mode using HAL_GPIO_Init().
        (++) If interrupt mode is used, enable and configure SDADC global
            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
        (++) If DMA mode is used, configure DMA with HAL_DMA_Init and link it
            with SDADC handle using __HAL_LINKDMA.
      (#) Configure the SDADC low power mode, fast conversion mode, slow clock
          mode and SDADC1 reference voltage using the HAL_ADC_Init() function.
          Note: Common reference voltage. is common to all SDADC instances.
      (#) Prepare channel configurations (input mode, common mode, gain and
          offset) using HAL_SDADC_PrepareChannelConfig and associate channel
          with one configuration using HAL_SDADC_AssociateChannelConfig.

    *** Calibration ***
    ============================================
    [..]
      (#) Start calibration using HAL_SDADC_StartCalibration or
          HAL_SDADC_CalibrationStart_IT.
      (#) In polling mode, use HAL_SDADC_PollForCalibEvent to detect the end of
          calibration.
      (#) In interrupt mode, HAL_SDADC_CalibrationCpltCallback will be called at
          the end of calibration.

    *** Regular channel conversion ***
    ============================================
    [..]
      (#) Select trigger for regular conversion using
          HAL_SDADC_SelectRegularTrigger.
      (#) Select regular channel and enable/disable continuous mode using
          HAL_SDADC_ConfigChannel.
      (#) Start regular conversion using HAL_SDADC_Start, HAL_SDADC_Start_IT
          or HAL_SDADC_Start_DMA.
      (#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
          regular conversion.
      (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
          end of regular conversion.
      (#) Get value of regular conversion using HAL_SDADC_GetValue.
      (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
          HAL_SDADC_ConvCpltCallback will be called respectively at the half
          transfer and at the transfer complete.
      (#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
          or HAL_SDADC_Stop_DMA.

    *** Injected channels conversion ***
    ============================================
    [..]
      (#) Enable/disable delay on injected conversion using
          HAL_SDADC_SelectInjectedDelay.
      (#) If external trigger is used for injected conversion, configure this
          trigger using HAL_SDADC_SelectInjectedExtTrigger.
      (#) Select trigger for injected conversion using
          HAL_SDADC_SelectInjectedTrigger.
      (#) Select injected channels and enable/disable continuous mode using
          HAL_SDADC_InjectedConfigChannel.
      (#) Start injected conversion using HAL_SDADC_InjectedStart,
          HAL_SDADC_InjectedStart_IT or HAL_SDADC_InjectedStart_DMA.
      (#) In polling mode, use HAL_SDADC_PollForInjectedConversion to detect the
          end of injected conversion.
      (#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
          at the end of injected conversion.
      (#) Get value of injected conversion and corresponding channel using
          HAL_SDADC_InjectedGetValue.
      (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
          HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
          half transfer and at the transfer complete.
      (#) Stop injected conversion using HAL_SDADC_InjectedStop,
          HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjectedStop_DMA.

    *** Multi mode regular channels conversions ***
    ======================================================
    [..]
      (#) Select type of multimode (SDADC1/SDADC2 or SDADC1/SDADC3) using
          HAL_SDADC_MultiModeConfigChannel.
      (#) Select software trigger for SDADC1 and synchronized trigger for
          SDADC2 (or SDADC3) using HAL_SDADC_SelectRegularTrigger.
      (#) Select regular channel for SDADC1 and SDADC2 (or SDADC3) using
          HAL_SDADC_ConfigChannel.
      (#) Start regular conversion for SDADC2 (or SDADC3) with HAL_SDADC_Start.
      (#) Start regular conversion for SDADC1 using HAL_SDADC_Start,
          HAL_SDADC_Start_IT or HAL_SDADC_MultiModeStart_DMA.
      (#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
          regular conversion for SDADC1.
      (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
          end of regular conversion for SDADC1.
      (#) Get value of regular conversions using HAL_SDADC_MultiModeGetValue.
      (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
          HAL_SDADC_ConvCpltCallback will be called respectively at the half
          transfer and at the transfer complete for SDADC1.
      (#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
          or HAL_SDADC_MultiModeStop_DMA for SDADC1.
      (#) Stop regular conversion using HAL_SDADC_Stop for SDADC2 (or SDADC3).

    *** Multi mode injected channels conversions ***
    ======================================================
    [..]
      (#) Select type of multimode (SDADC1/SDADC2 or SDADC1/SDADC3) using
          HAL_SDADC_InjectedMultiModeConfigChannel.
      (#) Select software or external trigger for SDADC1 and synchronized
          trigger for SDADC2 (or SDADC3) using HAL_SDADC_SelectInjectedTrigger.
      (#) Select injected channels for SDADC1 and SDADC2 (or SDADC3) using
          HAL_SDADC_InjectedConfigChannel.
      (#) Start injected conversion for SDADC2 (or SDADC3) with
          HAL_SDADC_InjectedStart.
      (#) Start injected conversion for SDADC1 using HAL_SDADC_InjectedStart,
          HAL_SDADC_InjectedStart_IT or HAL_SDADC_InjectedMultiModeStart_DMA.
      (#) In polling mode, use HAL_SDADC_InjectedPollForConversion to detect
          the end of injected conversion for SDADC1.
      (#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
          at the end of injected conversion for SDADC1.
      (#) Get value of injected conversions using
          HAL_SDADC_InjectedMultiModeGetValue.
      (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
          HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
          half transfer and at the transfer complete for SDADC1.
      (#) Stop injected conversion using HAL_SDADC_InjectedStop,
          HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjecteddMultiModeStop_DMA
          for SDADC1.
      (#) Stop injected conversion using HAL_SDADC_InjectedStop for SDADC2
          (or SDADC3).
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_sdadc.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_smartcard.c File Reference

  • File List
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Defines | Functions
stm32f3xx_hal_smartcard.c File Reference

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | SMARTCARD_TEACK_REACK_TIMEOUT 1000
#define | USART_CR1_FIELDS
#define | USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))
#define | USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))
#define | USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))

Functions

static HAL_StatusTypeDef | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral.
static void | SMARTCARD_AdvFeatureConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral advanced features.
static HAL_StatusTypeDef | SMARTCARD_CheckIdleState (SMARTCARD_HandleTypeDef *hsmartcard)
Check the SMARTCARD Idle State.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle SMARTCARD Communication Timeout.
static void | SMARTCARD_EndTxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
static void | SMARTCARD_EndRxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static void | SMARTCARD_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SMARTCARD_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SMARTCARD_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | SMARTCARD_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | SMARTCARD_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static HAL_StatusTypeDef | SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The SMARTCARD HAL driver can be used as follows:

    (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
    (#) Associate a USART to the SMARTCARD handle hsmartcard.
    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
        (++) Enable the USARTx interface clock.
        (++) USART pins configuration:
            (+++) Enable the clock for the USART GPIOs.
            (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
        (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
             and HAL_SMARTCARD_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
        (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
             and HAL_SMARTCARD_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
        the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
        error enabling or disabling in the hsmartcard handle Init structure.

    (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
        in the hsmartcard handle AdvancedInit structure.

    (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
        (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_SMARTCARD_MspInit() API.
        [..]
        (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
             __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.

    [..]
    [..] Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()

     *** SMARTCARD HAL driver macros list ***
     ========================================
     [..]
       Below the list of most used macros in SMARTCARD HAL driver.

       (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
       (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
       (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
       (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
       (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled

     [..]
       (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_smartcard.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_smartcard_ex.c File Reference

  • File List
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  • STM32F3xx_HAL_Driver
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Functions
stm32f3xx_hal_smartcard_ex.c File Reference

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.

Detailed Description

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
  =============================================================================
               ##### SMARTCARD peripheral extended features  #####
  =============================================================================
  [..]
  The Extended SMARTCARD HAL driver can be used as follows:

    (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
        then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
        auto-retry counter,...) in the hsmartcard AdvancedInit structure.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_smartcard_ex.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_smbus.c File Reference

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Defines | Functions
stm32f3xx_hal_smbus.c File Reference

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFU)
#define | HAL_TIMEOUT_ADDR (10000U)
#define | HAL_TIMEOUT_BUSY (25U)
#define | HAL_TIMEOUT_DIR (25U)
#define | HAL_TIMEOUT_RXNE (25U)
#define | HAL_TIMEOUT_STOPF (25U)
#define | HAL_TIMEOUT_TC (25U)
#define | HAL_TIMEOUT_TCR (25U)
#define | HAL_TIMEOUT_TXIS (25U)
#define | MAX_NBYTE_SIZE 255U

Functions

static HAL_StatusTypeDef | SMBUS_WaitOnFlagUntilTimeout (SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle SMBUS Communication Timeout.
static HAL_StatusTypeDef | SMBUS_Enable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static HAL_StatusTypeDef | SMBUS_Disable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static HAL_StatusTypeDef | SMBUS_Master_ISR (SMBUS_HandleTypeDef *hsmbus)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
static HAL_StatusTypeDef | SMBUS_Slave_ISR (SMBUS_HandleTypeDef *hsmbus)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
static void | SMBUS_ConvertOtherXferOptions (SMBUS_HandleTypeDef *hsmbus)
Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
static void | SMBUS_ITErrorHandler (SMBUS_HandleTypeDef *hsmbus)
SMBUS interrupts error handler.
static void | SMBUS_TransferConfig (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_ConfigAnalogFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
Configure Analog noise filter.
HAL_StatusTypeDef | HAL_SMBUS_ConfigDigitalFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
Configure Digital noise filter.
HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.
void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.
uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The SMBUS HAL driver can be used as follows:

    (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
        SMBUS_HandleTypeDef  hsmbus;

    (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
        (##) Enable the SMBUSx interface clock
        (##) SMBUS pins configuration
            (+++) Enable the clock for the SMBUS GPIOs
            (+++) Configure SMBUS pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the SMBUSx interrupt priority
            (+++) Enable the NVIC SMBUS IRQ Channel

    (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
        Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
        Peripheral mode and Packet Error Check mode in the hsmbus Init structure.

    (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
        (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.

    (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()

    (#) For SMBUS IO operations, only one mode of operations is available within this driver

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
      (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
      (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
      (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
      (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
      (++) The associated previous transfer callback is called at the end of abort process
      (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
      (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
      (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
           using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
      (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
           add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
      (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
      (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
      (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
      (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
      (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
      (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
      (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
           to check the Alert Error Code using function HAL_SMBUS_GetError()
      (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
      (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
           to check the Error Code using function HAL_SMBUS_GetError()

     *** SMBUS HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in SMBUS HAL driver.

      (+) __HAL_SMBUS_ENABLE:      Enable the SMBUS peripheral
      (+) __HAL_SMBUS_DISABLE:     Disable the SMBUS peripheral
      (+) __HAL_SMBUS_GET_FLAG:    Check whether the specified SMBUS flag is set or not
      (+) __HAL_SMBUS_CLEAR_FLAG:  Clear the specified SMBUS pending flag
      (+) __HAL_SMBUS_ENABLE_IT:   Enable the specified SMBUS interrupt
      (+) __HAL_SMBUS_DISABLE_IT:  Disable the specified SMBUS interrupt

     [..]
       (@) You can refer to the SMBUS HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_smbus.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_spi.c File Reference

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Defines | Functions
stm32f3xx_hal_spi.c File Reference

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | SPI_DEFAULT_TIMEOUT 100U

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static void | SPI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SPI_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SPI_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static HAL_StatusTypeDef | SPI_WaitFifoStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI FIFO Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_RxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 8-bit receive in Interrupt context.
static void | SPI_RxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
static void | SPI_AbortRx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Rx transaction.
static void | SPI_AbortTx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Tx or Rx/Tx transaction.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.
static HAL_StatusTypeDef | SPI_EndRxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RX transaction complete.
static HAL_StatusTypeDef | SPI_EndRxTxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RXTX or TX transaction complete.
HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      The SPI HAL driver can be used as follows:

      (#) Declare a SPI_HandleTypeDef handle structure, for example:
          SPI_HandleTypeDef  hspi;

      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
          (##) Enable the SPIx interface clock
          (##) SPI pins configuration
              (+++) Enable the clock for the SPI GPIOs
              (+++) Configure these SPI pins as alternate function push-pull
          (##) NVIC configuration if you need to use interrupt process
              (+++) Configure the SPIx interrupt priority
              (+++) Enable the NVIC SPI IRQ handle
          (##) DMA Configuration if you need to use DMA process
              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
              (+++) Enable the DMAx clock
              (+++) Configure the DMA handle parameters
              (+++) Configure the DMA Tx or Rx Stream/Channel
              (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel

      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.

      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
              by calling the customized HAL_SPI_MspInit() API.
     [..]
       Circular mode restriction:
      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
          (##) Master 2Lines RxOnly
          (##) Master 1Line Rx
      (#) The CRC feature is not managed when the DMA circular mode is enabled
      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
     [..]
       Master Receive mode restriction:
      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
          does not initiate a new transfer the following procedure has to be respected:
          (##) HAL_SPI_DeInit()
          (##) HAL_SPI_Init()
     [..]
       The HAL drivers do not allow reaching all supported SPI frequencies in the different SPI
       modes. Refer to the source code (stm32xxxx_hal_spi.c header) to get a summary of the
       maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on
       the APBx peripheral clock frequency (fPCLK) used by the SPI instance.

Additional table :

DataSize = SPI_DATASIZE_8BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | | Process | Tranfert mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | | X |----------------|----------|----------|-----------|----------|-----------|----------| | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | | R |----------------|----------|----------|-----------|----------|-----------|----------| | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |=========|================|==========|==========|===========|==========|===========|==========| | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | | X |----------------|----------|----------|-----------|----------|-----------|----------| | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | |=========|================|==========|==========|===========|==========|===========|==========| | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | | X |----------------|----------|----------|-----------|----------|-----------|----------| | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | +----------------------------------------------------------------------------------------------+

DataSize = SPI_DATASIZE_16BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | | Process | Tranfert mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | | X |----------------|----------|----------|-----------|----------|-----------|----------| | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | | R |----------------|----------|----------|-----------|----------|-----------|----------| | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |=========|================|==========|==========|===========|==========|===========|==========| | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | | X |----------------|----------|----------|-----------|----------|-----------|----------| | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | |=========|================|==========|==========|===========|==========|===========|==========| | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | | X |----------------|----------|----------|-----------|----------|-----------|----------| | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | +----------------------------------------------------------------------------------------------+

Note:
The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_spi.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_spi_ex.c File Reference

  • File List
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  • Firmware
  • Drivers
  • STM32F3xx_HAL_Driver
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Defines | Functions
stm32f3xx_hal_spi_ex.c File Reference

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | SPI_FIFO_SIZE 4

Functions

HAL_StatusTypeDef | HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.

Detailed Description

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_spi_ex.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_tim.c File Reference

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stm32f3xx_hal_tim.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
Selects the Input Trigger source.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
__weak HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
__weak HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiWriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
__weak HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode state.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 1 configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 2 configuration.
void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 3 configuration.
void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 4 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration.

Author:
MCD Application Team
  ==============================================================================
                      ##### TIMER Generic features #####
  ==============================================================================
  [..] The Timer features include:
       (#) 16-bit up, down, up/down auto-reload counter.
       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
           counter clock frequency either by any factor between 1 and 65536.
       (#) Up to 4 independent channels for:
           (++) Input Capture
           (++) Output Compare
           (++) PWM generation (Edge and Center-aligned Mode)
           (++) One-pulse mode output

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending from feature used :
           (++) Time Base : HAL_TIM_Base_MspInit()
           (++) Input Capture : HAL_TIM_IC_MspInit()
           (++) Output Compare : HAL_TIM_OC_MspInit()
           (++) PWM generation : HAL_TIM_PWM_MspInit()
           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE  ();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
             __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
       Initialization function of this driver:
       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
            Output Compare signal.
       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
            PWM signal.
       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
            external signal.
         (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
              in One Pulse Mode.
       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.

     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().

     (#) The DMA Burst is managed with the two following functions:
         HAL_TIM_DMABurst_WriteStart()
         HAL_TIM_DMABurst_ReadStart()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_tim.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_tim_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32F3xx_HAL_Driver
  • Src
Functions
stm32f3xx_hal_tim_ex.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complemetary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIM2 and TIM14 Remapping input capabilities.
__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non blocking mode.
__weak void | HAL_TIMEx_Break2Callback (TIM_HandleTypeDef *htim)
Hall Break2 detection callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface state.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration.

Author:
MCD Application Team
  ==============================================================================
                      ##### TIMER Extended features #####
  ==============================================================================
  [..]
    The Timer Extended features include:
    (#) Complementary outputs with programmable dead-time for :
        (++) Output Compare
        (++) PWM generation (Edge and Center-aligned Mode)
        (++) One-pulse mode output
    (#) Synchronization circuit to control the timer with external signals and to
        interconnect several timers together.
    (#) Break input to put the timer output signals in reset state or in a known state.
    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
        positioning purposes

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending from feature used :
           (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
           (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
           (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
           (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE  ();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
              __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
         initialization function of this driver:
          (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
              Timer Hall Sensor Interface and the commutation event with the corresponding
              Interrupt and DMA request if needed (Note that One Timer is used to interface
             with the Hall sensor Interface and another Timer should be used to use
             the commutation event).

     (#) Activate the TIM peripheral using one of the start functions:
           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_tim_ex.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_tsc.c File Reference

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Functions
stm32f3xx_hal_tsc.c File Reference

This file provides firmware functions to manage the following functionalities of the Touch Sensing Controller (TSC) peripheral: + Initialization and De-initialization + Channel IOs, Shield IOs and Sampling IOs configuration + Start and Stop an acquisition + Read acquisition result + Interrupts and flags management. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

static uint32_t | TSC_extract_groups (uint32_t iomask)
Utility function used to set the acquired groups mask.
HAL_StatusTypeDef | HAL_TSC_Init (TSC_HandleTypeDef *htsc)
Initialize the TSC peripheral according to the specified parameters in the TSC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_TSC_DeInit (TSC_HandleTypeDef *htsc)
Deinitialize the TSC peripheral registers to their default reset values.
__weak void | HAL_TSC_MspInit (TSC_HandleTypeDef *htsc)
Initialize the TSC MSP.
__weak void | HAL_TSC_MspDeInit (TSC_HandleTypeDef *htsc)
DeInitialize the TSC MSP.
HAL_StatusTypeDef | HAL_TSC_Start (TSC_HandleTypeDef *htsc)
Start the acquisition.
HAL_StatusTypeDef | HAL_TSC_Start_IT (TSC_HandleTypeDef *htsc)
Start the acquisition in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_Stop (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in polling mode.
HAL_StatusTypeDef | HAL_TSC_Stop_IT (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_PollForAcquisition (TSC_HandleTypeDef *htsc)
Start acquisition and wait until completion.
TSC_GroupStatusTypeDef | HAL_TSC_GroupGetStatus (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition status for a group.
uint32_t | HAL_TSC_GroupGetValue (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition measure for a group.
HAL_StatusTypeDef | HAL_TSC_IOConfig (TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config)
Configure TSC IOs.
HAL_StatusTypeDef | HAL_TSC_IODischarge (TSC_HandleTypeDef *htsc, uint32_t choice)
Discharge TSC IOs.
HAL_TSC_StateTypeDef | HAL_TSC_GetState (TSC_HandleTypeDef *htsc)
Return the TSC handle state.
void | HAL_TSC_IRQHandler (TSC_HandleTypeDef *htsc)
Handle TSC interrupt request.
__weak void | HAL_TSC_ConvCpltCallback (TSC_HandleTypeDef *htsc)
Acquisition completed callback in non-blocking mode.
__weak void | HAL_TSC_ErrorCallback (TSC_HandleTypeDef *htsc)
Error callback in non-blocking mode.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Touch Sensing Controller (TSC) peripheral: + Initialization and De-initialization + Channel IOs, Shield IOs and Sampling IOs configuration + Start and Stop an acquisition + Read acquisition result + Interrupts and flags management.

Author:
MCD Application Team
================================================================================
                       ##### TSC specific features #####
================================================================================
  [..]
  (#) Proven and robust surface charge transfer acquisition principle

  (#) Supports up to 3 capacitive sensing channels per group

  (#) Capacitive sensing channels can be acquired in parallel offering a very good
      response time

  (#) Spread spectrum feature to improve system robustness in noisy environments

  (#) Full hardware management of the charge transfer acquisition sequence

  (#) Programmable charge transfer frequency

  (#) Programmable sampling capacitor I/O pin

  (#) Programmable channel I/O pin

  (#) Programmable max count value to avoid long acquisition when a channel is faulty

  (#) Dedicated end of acquisition and max count error flags with interrupt capability

  (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
      components

  (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation

                          ##### How to use this driver #####
================================================================================
  [..]
    (#) Enable the TSC interface clock using __HAL_RCC_TSC_CLK_ENABLE() macro.

    (#) GPIO pins configuration
      (++) Enable the clock for the TSC GPIOs using __HAL_RCC_GPIOx_CLK_ENABLE() macro.
      (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode,
           and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode
           using HAL_GPIO_Init() function.

    (#) Interrupts configuration
      (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority()
           and HAL_NVIC_EnableIRQ() and function.

    (#) TSC configuration
      (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function.

   *** Acquisition sequence ***
  ===================================
  [..]
    (+) Discharge all IOs using HAL_TSC_IODischarge() function.
    (+) Wait a certain time allowing a good discharge of all capacitors. This delay depends
        of the sampling capacitor and electrodes design.
    (+) Select the channel IOs to be acquired using HAL_TSC_IOConfig() function.
    (+) Launch the acquisition using either HAL_TSC_Start() or HAL_TSC_Start_IT() function.
        If the synchronized mode is selected, the acquisition will start as soon as the signal
        is received on the synchro pin.
    (+) Wait the end of acquisition using either HAL_TSC_PollForAcquisition() or
        HAL_TSC_GetState() function or using WFI instruction for example.
    (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function.
    (+) Read the acquisition value using HAL_TSC_GroupGetValue() function.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_tsc.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_uart.c File Reference

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Defines | Functions
stm32f3xx_hal_uart.c File Reference

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | UART_CR1_FIELDS

Functions

static void | UART_EndTxTransfer (UART_HandleTypeDef *huart)
End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
static void | UART_EndRxTransfer (UART_HandleTypeDef *huart)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static void | UART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | UART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | UART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | UART_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | UART_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
HAL_StatusTypeDef | UART_Transmit_IT (UART_HandleTypeDef *huart)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wrap up transmission in non-blocking mode.
HAL_StatusTypeDef | UART_Receive_IT (UART_HandleTypeDef *huart)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.
HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART handle error code.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle UART Communication Timeout.
void | UART_Wakeup_AddressConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Initialize the UART wake-up from stop mode parameters when triggered by address detection.

Detailed Description

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
    The UART HAL driver can be used as follows:

    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
        (++) Enable the USARTx interface clock.
        (++) UART pins configuration:
            (+++) Enable the clock for the UART GPIOs.
            (+++) Configure these UART pins as alternate function pull-up.
        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
             and HAL_UART_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
        (++) UART interrupts handling:
              -@@-  The specific UART interrupts (Transmission complete interrupt,
                RXNE interrupt and Error Interrupts) are managed using the macros
                __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
             and HAL_UART_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.

    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
        in the huart handle AdvancedInit structure.

    (#) For the UART asynchronous mode, initialize the UART registers by calling
        the HAL_UART_Init() API.

    (#) For the UART Half duplex mode, initialize the UART registers by calling
        the HAL_HalfDuplex_Init() API.

    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
        by calling the HAL_LIN_Init() API.

    (#) For the UART Multiprocessor mode, initialize the UART registers
        by calling the HAL_MultiProcessor_Init() API.

    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
        by calling the HAL_RS485Ex_Init() API.

   [..]
    (@) These APIs (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(),
        also configure the low level Hardware (GPIO, CLOCK, CORTEX...etc) by
        calling the customized HAL_UART_MspInit() API.

   [..]
   [..] Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_UART_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_TxCpltCallback
       (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_RxCpltCallback
       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_UART_ErrorCallback

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_TxCpltCallback
       (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_RxCpltCallback
       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_UART_ErrorCallback
       (+) Pause the DMA Transfer using HAL_UART_DMAPause()
       (+) Resume the DMA Transfer using HAL_UART_DMAResume()
       (+) Stop the DMA Transfer using HAL_UART_DMAStop()

     *** UART HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in UART HAL driver.

      (+) __HAL_UART_ENABLE: Enable the UART peripheral
      (+) __HAL_UART_DISABLE: Disable the UART peripheral
      (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
      (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
      (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
      (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt

     [..]
       (@) You can refer to the UART HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_uart.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_uart_ex.c File Reference

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Functions
stm32f3xx_hal_uart_ex.c File Reference

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).

Detailed Description

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
  ==============================================================================
               ##### UART peripheral extended features  #####
  ==============================================================================

    (#) Declare a UART_HandleTypeDef handle structure.

    (#) For the UART RS485 Driver Enable mode, initialize the UART registers
        by calling the HAL_RS485Ex_Init() API.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_uart_ex.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_usart.c File Reference

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Defines | Functions
stm32f3xx_hal_usart.c File Reference

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Defines

#define | USART_DUMMY_DATA ((uint16_t) 0xFFFFU)
#define | USART_TEACK_REACK_TIMEOUT ( 1000U)
#define | USART_CR1_FIELDS
#define | USART_CR2_FIELDS

Functions

static void | USART_EndTransfer (USART_HandleTypeDef *husart)
End ongoing transfer on USART peripheral (following error detection or Transfer completion).
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static void | USART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | USART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | USART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle USART Communication Timeout.
static HAL_StatusTypeDef | USART_SetConfig (USART_HandleTypeDef *husart)
Configure the USART peripheral.
static HAL_StatusTypeDef | USART_CheckIdleState (USART_HandleTypeDef *husart)
Check the USART Idle State.
static HAL_StatusTypeDef | USART_Transmit_IT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non-blocking mode.
static HAL_StatusTypeDef | USART_Receive_IT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_TransmitReceive_IT (USART_HandleTypeDef *husart)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.
HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
      The USART HAL driver can be used as follows:

      (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
      (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
          (++) Enable the USARTx interface clock.
          (++) USART pins configuration:
            (+++) Enable the clock for the USART GPIOs.
            (+++) Configure these USART pins as alternate function pull-up.
          (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
                HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
            (++) USART interrupts handling:
              -@@-   The specific USART interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
          (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
               HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

      (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
          flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.

      (#) Initialize the USART registers by calling the HAL_USART_Init() API:
          (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
               by calling the customized HAL_USART_MspInit(&husart) API.

    (#) Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_USART_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
       (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
       (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_TxCpltCallback
       (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
       (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_RxCpltCallback
       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_USART_ErrorCallback

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
       (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
       (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_TxCpltCallback
       (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
       (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_RxCpltCallback
       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_USART_ErrorCallback
       (+) Pause the DMA Transfer using HAL_USART_DMAPause()
       (+) Resume the DMA Transfer using HAL_USART_DMAResume()
       (+) Stop the DMA Transfer using HAL_USART_DMAStop()

     *** USART HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in USART HAL driver.

       (+) __HAL_USART_ENABLE: Enable the USART peripheral
       (+) __HAL_USART_DISABLE: Disable the USART peripheral
       (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
       (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
       (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
       (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt

     [..]
       (@) You can refer to the USART HAL driver header file for more useful macros
     [..]
       (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
           HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
           HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_usart.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_wwdg.c File Reference

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Functions
stm32f3xx_hal_wwdg.c File Reference

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration function + IO operation functions. More...

#include "stm32f3xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration function + IO operation functions.

Author:
MCD Application Team
  ==============================================================================
                      ##### WWDG specific features #####
  ==============================================================================
  [..]
    Once enabled the WWDG generates a system reset on expiry of a programmed
    time period, unless the program refreshes the counter (T[6U;0] downcounter)
    before reaching 0x3F value (i.e. a reset is generated when the counter
    value rolls over from 0x40 to 0x3FU).

    (+) An MCU reset is also generated if the counter value is refreshed
        before the counter has reached the refresh window value. This
        implies that the counter must be refreshed in a limited window.

    (+) Once enabled the WWDG cannot be disabled except by a system reset.

    (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has
        occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).

    (+) The WWDG downcounter input clock is derived from the APB clock divided
        by a programmable prescaler.

    (+) WWDG downcounter clock (Hz) = PCLK1 / (4096U * Prescaler)

    (+) WWDG timeout (ms) = (1000U * (T[5U;0] + 1U)) / (WWDG downcounter clock)
        where T[5U;0] are the lowest 6 bits of downcounter.

    (+) WWDG Counter refresh is allowed between the following limits :
        (++) min time (ms) = (1000U * (T[5U;0] - Window)) / (WWDG downcounter clock)
        (++) max time (ms) = (1000U * (T[5U;0] - 0x40U)) / (WWDG downcounter clock)

    (+) Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms

    (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
        operations or data logging must be performed before the actual reset is
        generated. When the downcounter reaches the value 0x40U, an EWI interrupt
        is generated and the corresponding interrupt service routine (ISR) can
        be used to trigger specific actions (such as communications or data
        logging), before resetting the device.
        In some applications, the EWI interrupt can be used to manage a software
        system check and/or system recovery/graceful degradation, without
        generating a WWDG reset. In this case, the corresponding interrupt
        service routine (ISR) should reload the WWDG counter to avoid the WWDG
        reset, then trigger the required actions.
        Note:When the EWI interrupt cannot be served, e.g. due to a system lock
        in a higher priority task, the WWDG reset will eventually be generated.

    (+) Debug mode : When the microcontroller enters debug mode (core halted),
        the WWDG counter either continues to work normally or stops, depending
        on DBG_WWDG_STOP configuration bit in DBG module, accessible through
        __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().

    (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
        Interrupt mode using using HAL_WWDG_Init() function.
        This enables WWDG peripheral and the downcounter starts downcounting
        from given counter value.
        Init function can be called again to modify all watchdog parameters,
        however if EWI mode has been set once, it can't be clear until next
        reset.

    (+) The application program must refresh the WWDG counter at regular
        intervals during normal operation to prevent an MCU reset using
        HAL_WWDG_Refresh() function. This operation must occur only when
        the counter is lower than the window value already programmed.

    (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
        the counter reaches 0x40. User can add his own code in weak function
        HAL_WWDG_EarlyWakeupCallback().

     *** WWDG HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in WWDG HAL driver.

      (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_hal_wwdg.c.

Generated on Tue Jun 13 2017 08:20:11 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_pwr.c File Reference

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stm32f3xx_ll_pwr.c File Reference

PWR LL module driver. More...

#include "stm32f3xx_ll_pwr.h"
#include "stm32f3xx_ll_bus.h"

Go to the source code of this file.

Functions

ErrorStatus LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Detailed Description

PWR LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f3xx_ll_pwr.c.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC_rmtollPages.txt File Reference

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  • Globals
ADC_rmtollPages.txt File Reference
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STM32F373xC HAL User Manual: Data Structures

  • Data Structure Index
  • Data Fields
Data Structures
Here are the data structures with brief descriptions:
__ADC_HandleTypeDef | ADC handle Structure definition
__DAC_HandleTypeDef | DAC handle Structure definition
__DMA_HandleTypeDef | DMA handle Structure definition
__I2C_HandleTypeDef |
__SPI_HandleTypeDef | SPI handle Structure definition
ADC_AnalogWDGConfTypeDef | ADC Configuration analog watchdog definition
ADC_ChannelConfTypeDef | Structure definition of ADC channel for regular group
ADC_InitTypeDef | Structure definition of ADC and regular group initialization
ADC_InjectionConfTypeDef | ADC Configuration injected Channel structure definition
CAN_FilterConfTypeDef | CAN filter configuration structure definition
CAN_HandleTypeDef | CAN handle Structure definition
CAN_InitTypeDef | CAN init structure definition
CanRxMsgTypeDef | CAN Rx message structure definition
CanTxMsgTypeDef | CAN Tx message structure definition
CEC_HandleTypeDef | CEC handle Structure definition
CEC_InitTypeDef | CEC Init Structure definition
COMP_HandleTypeDef | COMP Handle Structure definition
COMP_InitTypeDef | COMP Init structure definition
CRC_HandleTypeDef | CRC Handle Structure definition
CRC_InitTypeDef | CRC Init Structure definition
DAC_ChannelConfTypeDef | DAC Configuration regular Channel structure definition
DMA_InitTypeDef | DMA Configuration Structure definition
FLASH_EraseInitTypeDef | FLASH Erase structure definition
FLASH_OBProgramInitTypeDef | FLASH Options bytes program structure definition
FLASH_ProcessTypeDef | FLASH handle Structure definition
GPIO_InitTypeDef | GPIO Init structure definition
I2C_InitTypeDef |
I2S_HandleTypeDef | I2S handle Structure definition
I2S_InitTypeDef | I2S Init structure definition
IRDA_HandleTypeDef | IRDA handle Structure definition
IRDA_InitTypeDef | IRDA Init Structure definition
IWDG_HandleTypeDef | IWDG Handle Structure definition
IWDG_InitTypeDef | IWDG Init structure definition
LL_ADC_InitTypeDef | Structure definition of some features of ADC instance
LL_ADC_INJ_InitTypeDef | Structure definition of some features of ADC group injected
LL_ADC_REG_InitTypeDef | Structure definition of some features of ADC group regular
LL_COMP_InitTypeDef | Structure definition of some features of COMP instance
LL_DAC_InitTypeDef | Structure definition of some features of DAC instance
LL_DMA_InitTypeDef |
LL_EXTI_InitTypeDef |
LL_GPIO_InitTypeDef | LL GPIO Init Structure definition
LL_I2C_InitTypeDef |
LL_I2S_InitTypeDef | I2S Init structure definition
LL_RCC_ClocksTypeDef | RCC Clocks Frequency Structure
LL_RTC_AlarmTypeDef | RTC Alarm structure definition
LL_RTC_DateTypeDef | RTC Date structure definition
LL_RTC_InitTypeDef | RTC Init structures definition
LL_RTC_TimeTypeDef | RTC Time structure definition
LL_SPI_InitTypeDef | SPI Init structures definition
LL_TIM_BDTR_InitTypeDef | BDTR (Break and Dead Time) structure definition
LL_TIM_ENCODER_InitTypeDef | TIM Encoder interface configuration structure definition
LL_TIM_HALLSENSOR_InitTypeDef | TIM Hall sensor interface configuration structure definition
LL_TIM_IC_InitTypeDef | TIM Input Capture configuration structure definition
LL_TIM_InitTypeDef | TIM Time Base configuration structure definition
LL_TIM_OC_InitTypeDef | TIM Output Compare configuration structure definition
LL_USART_ClockInitTypeDef | LL USART Clock Init Structure definition
LL_USART_InitTypeDef | LL USART Init Structure definition
LL_UTILS_ClkInitTypeDef | UTILS System, AHB and APB buses clock configuration structure definition
LL_UTILS_PLLInitTypeDef | UTILS PLL structure definition
MPU_Region_InitTypeDef |
PCD_EPTypeDef |
PCD_HandleTypeDef | PCD Handle Structure definition
PCD_InitTypeDef | PCD Initialization Structure definition
PWR_PVDTypeDef | PWR PVD configuration structure definition
RCC_ClkInitTypeDef | RCC System, AHB and APB busses clock configuration structure definition
RCC_OscInitTypeDef | RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
RCC_PeriphCLKInitTypeDef | RCC extended clocks structure definition
RCC_PLLInitTypeDef | RCC PLL configuration structure definition
RTC_AlarmTypeDef | RTC Alarm structure definition
RTC_DateTypeDef | RTC Date structure definition
RTC_HandleTypeDef | RTC Handle Structure definition
RTC_InitTypeDef | RTC Configuration Structure definition
RTC_TamperTypeDef | RTC Tamper structure definition
RTC_TimeTypeDef | RTC Time structure definition
SDADC_ConfParamTypeDef | SDADC Configuration Register Parameter Structure
SDADC_HandleTypeDef | SDADC handle Structure definition
SDADC_InitTypeDef | SDADC Init Structure definition
SMARTCARD_AdvFeatureInitTypeDef | SMARTCARD advanced features initalization structure definition
SMARTCARD_HandleTypeDef | SMARTCARD handle Structure definition
SMARTCARD_InitTypeDef | SMARTCARD Init Structure definition
SMBUS_HandleTypeDef |
SMBUS_InitTypeDef |
SPI_InitTypeDef | SPI Configuration Structure definition
TIM_Base_InitTypeDef | TIM Time base Configuration Structure definition
TIM_BreakDeadTimeConfigTypeDef | TIM Break and Dead time configuration Structure definition
TIM_ClearInputConfigTypeDef | TIM Clear Input Configuration Handle Structure definition
TIM_ClockConfigTypeDef | TIM Clock Configuration Handle Structure definition
TIM_Encoder_InitTypeDef | TIM Encoder Configuration Structure definition
TIM_HallSensor_InitTypeDef | TIM Hall sensor Configuration Structure definition
TIM_HandleTypeDef | TIM Time Base Handle Structure definition
TIM_IC_InitTypeDef | TIM Input Capture Configuration Structure definition
TIM_MasterConfigTypeDef | TIM Master configuration Structure definition
TIM_OC_InitTypeDef | TIM Output Compare Configuration Structure definition
TIM_OnePulse_InitTypeDef | TIM One Pulse Mode Configuration Structure definition
TIM_SlaveConfigTypeDef | TIM Slave configuration Structure definition
TSC_HandleTypeDef | TSC handle Structure definition
TSC_InitTypeDef | TSC init structure definition
TSC_IOConfigTypeDef | TSC IOs configuration structure definition
UART_AdvFeatureInitTypeDef | UART Advanced Features initalization structure definition
UART_HandleTypeDef | UART handle Structure definition
UART_InitTypeDef | UART Init Structure definition
UART_WakeUpTypeDef | UART wake up from stop mode parameters
USART_HandleTypeDef | USART handle Structure definition
USART_InitTypeDef | USART Init Structure definition
WWDG_HandleTypeDef | WWDG handle Structure definition
WWDG_InitTypeDef | WWDG Init structure definition
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STM32F373xC HAL User Manual: BUS_rmtollPages.txt File Reference

  • File List
  • Globals
BUS_rmtollPages.txt File Reference
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STM32F373xC HAL User Manual: Data Structure Index

  • Data Structure Index
  • Data Fields
Data Structure Index
A | C | D | F | G | I | L | M | P | R | S | T | U | W | _
A
G
LL_RTC_TimeTypeDef RTC_DateTypeDef TIM_OnePulse_InitTypeDef
LL_SPI_InitTypeDef RTC_HandleTypeDef TIM_SlaveConfigTypeDef
ADC_AnalogWDGConfTypeDef GPIO_InitTypeDef LL_TIM_BDTR_InitTypeDef RTC_InitTypeDef TSC_HandleTypeDef
ADC_ChannelConfTypeDef
I
LL_TIM_ENCODER_InitTypeDef RTC_TamperTypeDef TSC_InitTypeDef
ADC_InitTypeDef LL_TIM_HALLSENSOR_InitTypeDef RTC_TimeTypeDef TSC_IOConfigTypeDef
ADC_InjectionConfTypeDef I2C_InitTypeDef LL_TIM_IC_InitTypeDef
S
U
C
I2S_HandleTypeDef LL_TIM_InitTypeDef
I2S_InitTypeDef LL_TIM_OC_InitTypeDef SDADC_ConfParamTypeDef UART_AdvFeatureInitTypeDef
CAN_FilterConfTypeDef IRDA_HandleTypeDef LL_USART_ClockInitTypeDef SDADC_HandleTypeDef UART_HandleTypeDef
CAN_HandleTypeDef IRDA_InitTypeDef LL_USART_InitTypeDef SDADC_InitTypeDef UART_InitTypeDef
CAN_InitTypeDef IWDG_HandleTypeDef LL_UTILS_ClkInitTypeDef SMARTCARD_AdvFeatureInitTypeDef UART_WakeUpTypeDef
CanRxMsgTypeDef IWDG_InitTypeDef LL_UTILS_PLLInitTypeDef SMARTCARD_HandleTypeDef USART_HandleTypeDef
CanTxMsgTypeDef
L
M
SMARTCARD_InitTypeDef USART_InitTypeDef
CEC_HandleTypeDef SMBUS_HandleTypeDef
W
CEC_InitTypeDef LL_ADC_InitTypeDef MPU_Region_InitTypeDef SMBUS_InitTypeDef
COMP_HandleTypeDef LL_ADC_INJ_InitTypeDef
P
SPI_InitTypeDef WWDG_HandleTypeDef
COMP_InitTypeDef LL_ADC_REG_InitTypeDef
T
WWDG_InitTypeDef
CRC_HandleTypeDef LL_COMP_InitTypeDef PCD_EPTypeDef
_
CRC_InitTypeDef LL_DAC_InitTypeDef PCD_HandleTypeDef TIM_Base_InitTypeDef
D
LL_DMA_InitTypeDef PCD_InitTypeDef TIM_BreakDeadTimeConfigTypeDef __ADC_HandleTypeDef
LL_EXTI_InitTypeDef PWR_PVDTypeDef TIM_ClearInputConfigTypeDef __DAC_HandleTypeDef
DAC_ChannelConfTypeDef LL_GPIO_InitTypeDef
R
TIM_ClockConfigTypeDef __DMA_HandleTypeDef
DMA_InitTypeDef LL_I2C_InitTypeDef TIM_Encoder_InitTypeDef __I2C_HandleTypeDef
F
LL_I2S_InitTypeDef RCC_ClkInitTypeDef TIM_HallSensor_InitTypeDef __SPI_HandleTypeDef
LL_RCC_ClocksTypeDef RCC_OscInitTypeDef TIM_HandleTypeDef
FLASH_EraseInitTypeDef LL_RTC_AlarmTypeDef RCC_PeriphCLKInitTypeDef TIM_IC_InitTypeDef
FLASH_OBProgramInitTypeDef LL_RTC_DateTypeDef RCC_PLLInitTypeDef TIM_MasterConfigTypeDef
FLASH_ProcessTypeDef LL_RTC_InitTypeDef RTC_AlarmTypeDef TIM_OC_InitTypeDef
A | C | D | F | G | I | L | M | P | R | S | T | U | W | _
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STM32F373xC HAL User Manual: COMP_rmtollPages.txt File Reference

  • File List
  • Globals
COMP_rmtollPages.txt File Reference
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STM32F373xC HAL User Manual: CORTEX_rmtollPages.txt File Reference

  • File List
  • Globals
CORTEX_rmtollPages.txt File Reference
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STM32F373xC HAL User Manual: CRC_rmtollPages.txt File Reference

  • File List
  • Globals
CRC_rmtollPages.txt File Reference
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STM32F373xC HAL User Manual: DAC_rmtollPages.txt File Reference

  • File List
  • Globals
DAC_rmtollPages.txt File Reference
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: C:/NoBackup/git/f3_master/Firmware/Drivers/ Directory Reference

  • Firmware
  • Drivers
Drivers Directory Reference

Directories

directory STM32F3xx_HAL_Driver
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: C:/NoBackup/git/f3_master/Firmware/Drivers/STM32F3xx_HAL_Driver/Inc/ Directory Reference

  • Firmware
  • Drivers
  • STM32F3xx_HAL_Driver
  • Inc
Inc Directory Reference

Files

file | stm32f3xx_hal.h [code]

This file contains all the functions prototypes for the HAL module driver.

file | stm32f3xx_hal_adc.h [code]

Header file containing functions prototypes of ADC HAL library.

file | stm32f3xx_hal_adc_ex.h [code]

Header file containing functions prototypes of ADC HAL library.

file | stm32f3xx_hal_can.h [code]

Header file of CAN HAL module.

file | stm32f3xx_hal_cec.h [code]

Header file of CEC HAL module.

file | stm32f3xx_hal_comp.h [code]

Header file of COMP HAL module.

file | stm32f3xx_hal_comp_ex.h [code]

Header file of COMP HAL Extended module.

file | stm32f3xx_hal_cortex.h [code]

Header file of CORTEX HAL module.

file | stm32f3xx_hal_crc.h [code]

Header file of CRC HAL module.

file | stm32f3xx_hal_crc_ex.h [code]

Header file of CRC HAL extension module.

file | stm32f3xx_hal_dac.h [code]

Header file of DAC HAL module.

file | stm32f3xx_hal_dac_ex.h [code]

Header file of DAC HAL Extended module.

file | stm32f3xx_hal_dma.h [code]

Header file of DMA HAL module.

file | stm32f3xx_hal_dma_ex.h [code]

Header file of DMA HAL extension module.

file | stm32f3xx_hal_flash.h [code]

Header file of Flash HAL module.

file | stm32f3xx_hal_flash_ex.h [code]

Header file of Flash HAL Extended module.

file | stm32f3xx_hal_gpio.h [code]

Header file of GPIO HAL module.

file | stm32f3xx_hal_gpio_ex.h [code]

Header file of GPIO HAL Extended module.

file | stm32f3xx_hal_hrtim.h [code]

Header file of HRTIM HAL module.

file | stm32f3xx_hal_i2c.h [code]

Header file of I2C HAL module.

file | stm32f3xx_hal_i2c_ex.h [code]

Header file of I2C HAL Extended module.

file | stm32f3xx_hal_i2s.h [code]

Header file of I2S HAL module.

file | stm32f3xx_hal_i2s_ex.h [code]

Header file of I2S HAL Extended module.

file | stm32f3xx_hal_irda.h [code]

This file contains all the functions prototypes for the IRDA firmware library.

file | stm32f3xx_hal_irda_ex.h [code]

Header file of IRDA HAL Extended module.

file | stm32f3xx_hal_iwdg.h [code]

Header file of IWDG HAL module.

file | stm32f3xx_hal_nand.h [code]

Header file of NAND HAL module.

file | stm32f3xx_hal_nor.h [code]

Header file of NOR HAL module.

file | stm32f3xx_hal_opamp.h [code]

Header file of OPAMP HAL module.

file | stm32f3xx_hal_opamp_ex.h [code]

Header file of OPAMP HAL Extended module.

file | stm32f3xx_hal_pccard.h [code]

Header file of PCCARD HAL module.

file | stm32f3xx_hal_pcd.h [code]

Header file of PCD HAL module.

file | stm32f3xx_hal_pcd_ex.h [code]

Header file of PCD HAL Extension module.

file | stm32f3xx_hal_pwr.h [code]

Header file of PWR HAL module.

file | stm32f3xx_hal_pwr_ex.h [code]

Header file of PWR HAL Extended module.

file | stm32f3xx_hal_rcc.h [code]

Header file of RCC HAL module.

file | stm32f3xx_hal_rcc_ex.h [code]

Header file of RCC HAL Extension module.

file | stm32f3xx_hal_rtc.h [code]

Header file of RTC HAL module.

file | stm32f3xx_hal_rtc_ex.h [code]

Header file of RTC HAL Extended module.

file | stm32f3xx_hal_sdadc.h [code]

This file contains all the functions prototypes for the SDADC firmware library.

file | stm32f3xx_hal_smartcard.h [code]

Header file of SMARTCARD HAL module.

file | stm32f3xx_hal_smartcard_ex.h [code]

Header file of SMARTCARD HAL Extended module.

file | stm32f3xx_hal_smbus.h [code]

Header file of SMBUS HAL module.

file | stm32f3xx_hal_spi.h [code]

Header file of SPI HAL module.

file | stm32f3xx_hal_spi_ex.h [code]

Header file of SPI HAL Extended module.

file | stm32f3xx_hal_sram.h [code]

Header file of SRAM HAL module.

file | stm32f3xx_hal_tim.h [code]

Header file of TIM HAL module.

file | stm32f3xx_hal_tim_ex.h [code]

Header file of TIM HAL Extended module.

file | stm32f3xx_hal_tsc.h [code]

Header file of TSC HAL module.

file | stm32f3xx_hal_uart.h [code]

Header file of UART HAL module.

file | stm32f3xx_hal_uart_ex.h [code]

Header file of UART HAL Extended module.

file | stm32f3xx_hal_usart.h [code]

Header file of USART HAL module.

file | stm32f3xx_hal_usart_ex.h [code]

Header file of USART HAL Extended module.

file | stm32f3xx_hal_wwdg.h [code]

Header file of WWDG HAL module.

file | stm32f3xx_ll_adc.h [code]

Header file of ADC LL module.

file | stm32f3xx_ll_bus.h [code]

Header file of BUS LL module.

file | stm32f3xx_ll_comp.h [code]

Header file of COMP LL module.

file | stm32f3xx_ll_cortex.h [code]

Header file of CORTEX LL module.

file | stm32f3xx_ll_crc.h [code]

Header file of CRC LL module.

file | stm32f3xx_ll_dac.h [code]

Header file of DAC LL module.

file | stm32f3xx_ll_dma.h [code]

Header file of DMA LL module.

file | stm32f3xx_ll_exti.h [code]

Header file of EXTI LL module.

file | stm32f3xx_ll_gpio.h [code]

Header file of GPIO LL module.

file | stm32f3xx_ll_hrtim.h [code]

Header file of HRTIM LL module.

file | stm32f3xx_ll_i2c.h [code]

Header file of I2C LL module.

file | stm32f3xx_ll_iwdg.h [code]

Header file of IWDG LL module.

file | stm32f3xx_ll_opamp.h [code]

Header file of OPAMP LL module.

file | stm32f3xx_ll_pwr.h [code]

Header file of PWR LL module.

file | stm32f3xx_ll_rcc.h [code]

Header file of RCC LL module.

file | stm32f3xx_ll_rtc.h [code]

Header file of RTC LL module.

file | stm32f3xx_ll_spi.h [code]

Header file of SPI LL module.

file | stm32f3xx_ll_system.h [code]

Header file of SYSTEM LL module.

file | stm32f3xx_ll_tim.h [code]

Header file of TIM LL module.

file | stm32f3xx_ll_usart.h [code]

Header file of USART LL module.

file | stm32f3xx_ll_utils.h [code]

Header file of UTILS LL module.

file | stm32f3xx_ll_wwdg.h [code]

Header file of WWDG LL module.

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STM32F373xC HAL User Manual: C:/NoBackup/git/f3_master/Firmware/Drivers/STM32F3xx_HAL_Driver/ Directory Reference

  • Firmware
  • Drivers
  • STM32F3xx_HAL_Driver
STM32F3xx_HAL_Driver Directory Reference

Directories

directory | Inc
directory | Src
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: C:/NoBackup/git/f3_master/Firmware/ Directory Reference

  • Firmware
Firmware Directory Reference

Directories

directory Drivers
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: C:/NoBackup/git/f3_master/Firmware/Drivers/STM32F3xx_HAL_Driver/Src/ Directory Reference

  • Firmware
  • Drivers
  • STM32F3xx_HAL_Driver
  • Src
Src Directory Reference

Files

file | stm32f3xx_hal.c [code]

HAL module driver. This is the common part of the HAL initialization.

file | stm32f3xx_hal_adc.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of conversions of regular group, using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Channels configuration on injected group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32f3xx_hal_adc_ex.c".

file | stm32f3xx_hal_adc_ex.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of injected group, using 2 possible modes: polling, interruption. ++ Multimode feature (available on devices with 2 ADCs or more) ++ Calibration (ADC automatic self-calibration) + Control functions ++ Channels configuration on injected group Other functions (generic functions) are available in file "stm32f3xx_hal_adc.c".

file | stm32f3xx_hal_can.c [code]

CAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32f3xx_hal_cec.c [code]

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

file | stm32f3xx_hal_comp.c [code]

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Peripheral Control functions + Peripheral State functions.

file | stm32f3xx_hal_cortex.c [code]

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32f3xx_hal_crc.c [code]

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

file | stm32f3xx_hal_crc_ex.c [code]

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral.

file | stm32f3xx_hal_dac.c [code]

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f3xx_hal_dac_ex.c [code]

DACEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral.

file | stm32f3xx_hal_dma.c [code]

DMA HAL module driver.

file | stm32f3xx_hal_flash.c [code]

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral State functions.

file | stm32f3xx_hal_flash_ex.c [code]

Extended FLASH HAL module driver.

file | stm32f3xx_hal_gpio.c [code]

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

file | stm32f3xx_hal_hrtim.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the High Resolution Timer (HRTIM) peripheral: + HRTIM Initialization + DLL Calibration Start + Timer Time Base Unit Configuration + Simple Time Base Start/Stop + Simple Time Base Start/Stop Interrupt + Simple Time Base Start/Stop DMA Request + Simple Output Compare/PWM Channel Configuration + Simple Output Compare/PWM Channel Start/Stop Interrupt + Simple Output Compare/PWM Channel Start/Stop DMA Request + Simple Input Capture Channel Configuration + Simple Input Capture Channel Start/Stop Interrupt + Simple Input Capture Channel Start/Stop DMA Request + Simple One Pulse Channel Configuration + Simple One Pulse Channel Start/Stop Interrupt + HRTIM External Synchronization Configuration + HRTIM Burst Mode Controller Configuration + HRTIM Burst Mode Controller Enabling + HRTIM External Events Conditioning Configuration + HRTIM Faults Conditioning Configuration + HRTIM Faults Enabling + HRTIM ADC trigger Configuration + Waveform Timer Configuration + Waveform Event Filtering Configuration + Waveform Dead Time Insertion Configuration + Waveform Chopper Mode Configuration + Waveform Compare Unit Configuration + Waveform Capture Unit Configuration + Waveform Output Configuration + Waveform Counter Start/Stop + Waveform Counter Start/Stop Interrupt + Waveform Counter Start/Stop DMA Request + Waveform Output Enabling + Waveform Output Level Set/Get + Waveform Output State Get + Waveform Burst DMA Operation Configuration + Waveform Burst DMA Operation Start + Waveform Timer Counter Software Reset + Waveform Capture Software Trigger + Waveform Burst Mode Controller Software Trigger + Waveform Timer Pre-loadable Registers Update Enabling + Waveform Timer Pre-loadable Registers Software Update + Waveform Timer Delayed Protection Status Get + Waveform Timer Burst Status Get + Waveform Timer Push-Pull Status Get + Peripheral State Get.

file | stm32f3xx_hal_i2c.c [code]

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32f3xx_hal_i2c_ex.c [code]

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions.

file | stm32f3xx_hal_i2s.c [code]

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32f3xx_hal_i2s_ex.c [code]

I2S Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2S Extended peripheral: + Extended features Functions.

file | stm32f3xx_hal_irda.c [code]

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions.

file | stm32f3xx_hal_iwdg.c [code]

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions.

file | stm32f3xx_hal_nand.c [code]

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device.

file | stm32f3xx_hal_nor.c [code]

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device.

file | stm32f3xx_hal_opamp.c [code]

OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifiers (OPAMP1,...OPAMP4) peripheral: + OPAMP Configuration + OPAMP calibration Thanks to + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32f3xx_hal_opamp_ex.c [code]

Extended OPAMP HAL module driver.

file | stm32f3xx_hal_pccard.c [code]

PCCARD HAL module driver. This file provides a generic firmware to drive PCCARD memories mounted as external device.

file | stm32f3xx_hal_pcd.c [code]

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32f3xx_hal_pcd_ex.c [code]

Extended PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Configuration of the PMA for EP.

file | stm32f3xx_hal_pwr.c [code]

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions.

file | stm32f3xx_hal_pwr_ex.c [code]

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions.

file | stm32f3xx_hal_rcc.c [code]

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32f3xx_hal_rcc_ex.c [code]

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions.

file | stm32f3xx_hal_rtc.c [code]

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management.

file | stm32f3xx_hal_rtc_ex.c [code]

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions.

file | stm32f3xx_hal_sdadc.c [code]

This file provides firmware functions to manage the following functionalities of the Sigma-Delta Analog to Digital Converter (SDADC) peripherals: + Initialization and Configuration + Regular Channels Configuration + Injected channels Configuration + Power saving + Regular/Injected Channels DMA Configuration + Interrupts and flags management.

file | stm32f3xx_hal_smartcard.c [code]

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32f3xx_hal_smartcard_ex.c [code]

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32f3xx_hal_smbus.c [code]

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32f3xx_hal_spi.c [code]

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32f3xx_hal_spi_ex.c [code]

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions.

file | stm32f3xx_hal_sram.c [code]

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device.

file | stm32f3xx_hal_tim.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration.

file | stm32f3xx_hal_tim_ex.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration.

file | stm32f3xx_hal_tsc.c [code]

This file provides firmware functions to manage the following functionalities of the Touch Sensing Controller (TSC) peripheral: + Initialization and De-initialization + Channel IOs, Shield IOs and Sampling IOs configuration + Start and Stop an acquisition + Read acquisition result + Interrupts and flags management.

file | stm32f3xx_hal_uart.c [code]

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f3xx_hal_uart_ex.c [code]

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32f3xx_hal_usart.c [code]

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32f3xx_hal_wwdg.c [code]

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration function + IO operation functions.

file | stm32f3xx_ll_adc.c [code]

ADC LL module driver.

file | stm32f3xx_ll_comp.c [code]

COMP LL module driver.

file | stm32f3xx_ll_crc.c [code]

CRC LL module driver.

file | stm32f3xx_ll_dac.c [code]

DAC LL module driver.

file | stm32f3xx_ll_dma.c [code]

DMA LL module driver.

file | stm32f3xx_ll_exti.c [code]

EXTI LL module driver.

file | stm32f3xx_ll_gpio.c [code]

GPIO LL module driver.

file | stm32f3xx_ll_hrtim.c [code]

HRTIM LL module driver.

file | stm32f3xx_ll_i2c.c [code]

I2C LL module driver.

file | stm32f3xx_ll_opamp.c [code]

OPAMP LL module driver.

file | stm32f3xx_ll_pwr.c [code]

PWR LL module driver.

file | stm32f3xx_ll_rcc.c [code]

RCC LL module driver.

file | stm32f3xx_ll_rtc.c [code]

RTC LL module driver.

file | stm32f3xx_ll_spi.c [code]

SPI LL module driver.

file | stm32f3xx_ll_tim.c [code]

TIM LL module driver.

file | stm32f3xx_ll_usart.c [code]

USART LL module driver.

file | stm32f3xx_ll_utils.c [code]

UTILS LL module driver.

Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Directories

Directories
This directory hierarchy is sorted roughly, but not completely, alphabetically:
  • Firmware
    • Drivers
      • STM32F3xx_HAL_Driver
        • Inc
        • Src
Generated on Tue Jun 13 2017 08:20:23 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA_rmtollPages.txt File Reference

  • File List
  • Globals
DMA_rmtollPages.txt File Reference
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: EXTI_rmtollPages.txt File Reference

  • File List
  • Globals
EXTI_rmtollPages.txt File Reference
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: File List

  • File List
  • Globals
File List
Here is a list of all files with brief descriptions:
stm32f3xx_hal.c [code] | HAL module driver. This is the common part of the HAL initialization
stm32f3xx_hal.h [code] | This file contains all the functions prototypes for the HAL module driver
stm32f3xx_hal_adc.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of conversions of regular group, using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Channels configuration on injected group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32f3xx_hal_adc_ex.c"
stm32f3xx_hal_adc.h [code] | Header file containing functions prototypes of ADC HAL library
stm32f3xx_hal_adc_ex.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of injected group, using 2 possible modes: polling, interruption. ++ Multimode feature (available on devices with 2 ADCs or more) ++ Calibration (ADC automatic self-calibration) + Control functions ++ Channels configuration on injected group Other functions (generic functions) are available in file "stm32f3xx_hal_adc.c"
stm32f3xx_hal_adc_ex.h [code] | Header file containing functions prototypes of ADC HAL library
stm32f3xx_hal_can.c [code] | CAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32f3xx_hal_can.h [code] | Header file of CAN HAL module
stm32f3xx_hal_cec.c [code] | CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions
stm32f3xx_hal_cec.h [code] | Header file of CEC HAL module
stm32f3xx_hal_comp.c [code] | COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Peripheral Control functions + Peripheral State functions
stm32f3xx_hal_comp.h [code] | Header file of COMP HAL module
stm32f3xx_hal_comp_ex.h [code] | Header file of COMP HAL Extended module
stm32f3xx_hal_conf.h [code] | HAL configuration file
stm32f3xx_hal_cortex.c [code] | CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions
stm32f3xx_hal_cortex.h [code] | Header file of CORTEX HAL module
stm32f3xx_hal_crc.c [code] | CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions
stm32f3xx_hal_crc.h [code] | Header file of CRC HAL module
stm32f3xx_hal_crc_ex.c [code] | Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral
stm32f3xx_hal_crc_ex.h [code] | Header file of CRC HAL extension module
stm32f3xx_hal_dac.c [code] | DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f3xx_hal_dac.h [code] | Header file of DAC HAL module
stm32f3xx_hal_dac_ex.c [code] | DACEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral
stm32f3xx_hal_dac_ex.h [code] | Header file of DAC HAL Extended module
stm32f3xx_hal_dma.c [code] | DMA HAL module driver
stm32f3xx_hal_dma.h [code] | Header file of DMA HAL module
stm32f3xx_hal_dma_ex.h [code] | Header file of DMA HAL extension module
stm32f3xx_hal_flash.c [code] | FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral State functions
stm32f3xx_hal_flash.h [code] | Header file of Flash HAL module
stm32f3xx_hal_flash_ex.c [code] | Extended FLASH HAL module driver
stm32f3xx_hal_flash_ex.h [code] | Header file of Flash HAL Extended module
stm32f3xx_hal_gpio.c [code] | GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions
stm32f3xx_hal_gpio.h [code] | Header file of GPIO HAL module
stm32f3xx_hal_gpio_ex.h [code] | Header file of GPIO HAL Extended module
stm32f3xx_hal_hrtim.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the High Resolution Timer (HRTIM) peripheral: + HRTIM Initialization + DLL Calibration Start + Timer Time Base Unit Configuration + Simple Time Base Start/Stop + Simple Time Base Start/Stop Interrupt + Simple Time Base Start/Stop DMA Request + Simple Output Compare/PWM Channel Configuration + Simple Output Compare/PWM Channel Start/Stop Interrupt + Simple Output Compare/PWM Channel Start/Stop DMA Request + Simple Input Capture Channel Configuration + Simple Input Capture Channel Start/Stop Interrupt + Simple Input Capture Channel Start/Stop DMA Request + Simple One Pulse Channel Configuration + Simple One Pulse Channel Start/Stop Interrupt + HRTIM External Synchronization Configuration + HRTIM Burst Mode Controller Configuration + HRTIM Burst Mode Controller Enabling + HRTIM External Events Conditioning Configuration + HRTIM Faults Conditioning Configuration + HRTIM Faults Enabling + HRTIM ADC trigger Configuration + Waveform Timer Configuration + Waveform Event Filtering Configuration + Waveform Dead Time Insertion Configuration + Waveform Chopper Mode Configuration + Waveform Compare Unit Configuration + Waveform Capture Unit Configuration + Waveform Output Configuration + Waveform Counter Start/Stop + Waveform Counter Start/Stop Interrupt + Waveform Counter Start/Stop DMA Request + Waveform Output Enabling + Waveform Output Level Set/Get + Waveform Output State Get + Waveform Burst DMA Operation Configuration + Waveform Burst DMA Operation Start + Waveform Timer Counter Software Reset + Waveform Capture Software Trigger + Waveform Burst Mode Controller Software Trigger + Waveform Timer Pre-loadable Registers Update Enabling + Waveform Timer Pre-loadable Registers Software Update + Waveform Timer Delayed Protection Status Get + Waveform Timer Burst Status Get + Waveform Timer Push-Pull Status Get + Peripheral State Get
stm32f3xx_hal_hrtim.h [code] | Header file of HRTIM HAL module
stm32f3xx_hal_i2c.c [code] | I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32f3xx_hal_i2c.h [code] | Header file of I2C HAL module
stm32f3xx_hal_i2c_ex.c [code] | I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions
stm32f3xx_hal_i2c_ex.h [code] | Header file of I2C HAL Extended module
stm32f3xx_hal_i2s.c [code] | I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32f3xx_hal_i2s.h [code] | Header file of I2S HAL module
stm32f3xx_hal_i2s_ex.c [code] | I2S Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2S Extended peripheral: + Extended features Functions
stm32f3xx_hal_i2s_ex.h [code] | Header file of I2S HAL Extended module
stm32f3xx_hal_irda.c [code] | IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions
stm32f3xx_hal_irda.h [code] | This file contains all the functions prototypes for the IRDA firmware library
stm32f3xx_hal_irda_ex.h [code] | Header file of IRDA HAL Extended module
stm32f3xx_hal_iwdg.c [code] | IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions
stm32f3xx_hal_iwdg.h [code] | Header file of IWDG HAL module
stm32f3xx_hal_nand.c [code] | NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device
stm32f3xx_hal_nand.h [code] | Header file of NAND HAL module
stm32f3xx_hal_nor.c [code] | NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device
stm32f3xx_hal_nor.h [code] | Header file of NOR HAL module
stm32f3xx_hal_opamp.c [code] | OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifiers (OPAMP1,...OPAMP4) peripheral: + OPAMP Configuration + OPAMP calibration Thanks to + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions
stm32f3xx_hal_opamp.h [code] | Header file of OPAMP HAL module
stm32f3xx_hal_opamp_ex.c [code] | Extended OPAMP HAL module driver
stm32f3xx_hal_opamp_ex.h [code] | Header file of OPAMP HAL Extended module
stm32f3xx_hal_pccard.c [code] | PCCARD HAL module driver. This file provides a generic firmware to drive PCCARD memories mounted as external device
stm32f3xx_hal_pccard.h [code] | Header file of PCCARD HAL module
stm32f3xx_hal_pcd.c [code] | PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32f3xx_hal_pcd.h [code] | Header file of PCD HAL module
stm32f3xx_hal_pcd_ex.c [code] | Extended PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Configuration of the PMA for EP
stm32f3xx_hal_pcd_ex.h [code] | Header file of PCD HAL Extension module
stm32f3xx_hal_pwr.c [code] | PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions
stm32f3xx_hal_pwr.h [code] | Header file of PWR HAL module
stm32f3xx_hal_pwr_ex.c [code] | Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions
stm32f3xx_hal_pwr_ex.h [code] | Header file of PWR HAL Extended module
stm32f3xx_hal_rcc.c [code] | RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions
stm32f3xx_hal_rcc.h [code] | Header file of RCC HAL module
stm32f3xx_hal_rcc_ex.c [code] | Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions
stm32f3xx_hal_rcc_ex.h [code] | Header file of RCC HAL Extension module
stm32f3xx_hal_rtc.c [code] | RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management
stm32f3xx_hal_rtc.h [code] | Header file of RTC HAL module
stm32f3xx_hal_rtc_ex.c [code] | Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions
stm32f3xx_hal_rtc_ex.h [code] | Header file of RTC HAL Extended module
stm32f3xx_hal_sdadc.c [code] | This file provides firmware functions to manage the following functionalities of the Sigma-Delta Analog to Digital Converter (SDADC) peripherals: + Initialization and Configuration + Regular Channels Configuration + Injected channels Configuration + Power saving + Regular/Injected Channels DMA Configuration + Interrupts and flags management
stm32f3xx_hal_sdadc.h [code] | This file contains all the functions prototypes for the SDADC firmware library
stm32f3xx_hal_smartcard.c [code] | SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32f3xx_hal_smartcard.h [code] | Header file of SMARTCARD HAL module
stm32f3xx_hal_smartcard_ex.c [code] | SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions
stm32f3xx_hal_smartcard_ex.h [code] | Header file of SMARTCARD HAL Extended module
stm32f3xx_hal_smbus.c [code] | SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32f3xx_hal_smbus.h [code] | Header file of SMBUS HAL module
stm32f3xx_hal_spi.c [code] | SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32f3xx_hal_spi.h [code] | Header file of SPI HAL module
stm32f3xx_hal_spi_ex.c [code] | Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions
stm32f3xx_hal_spi_ex.h [code] | Header file of SPI HAL Extended module
stm32f3xx_hal_sram.c [code] | SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device
stm32f3xx_hal_sram.h [code] | Header file of SRAM HAL module
stm32f3xx_hal_tim.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration
stm32f3xx_hal_tim.h [code] | Header file of TIM HAL module
stm32f3xx_hal_tim_ex.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration
stm32f3xx_hal_tim_ex.h [code] | Header file of TIM HAL Extended module
stm32f3xx_hal_tsc.c [code] | This file provides firmware functions to manage the following functionalities of the Touch Sensing Controller (TSC) peripheral: + Initialization and De-initialization + Channel IOs, Shield IOs and Sampling IOs configuration + Start and Stop an acquisition + Read acquisition result + Interrupts and flags management
stm32f3xx_hal_tsc.h [code] | Header file of TSC HAL module
stm32f3xx_hal_uart.c [code] | UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f3xx_hal_uart.h [code] | Header file of UART HAL module
stm32f3xx_hal_uart_ex.c [code] | Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions
stm32f3xx_hal_uart_ex.h [code] | Header file of UART HAL Extended module
stm32f3xx_hal_usart.c [code] | USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32f3xx_hal_usart.h [code] | Header file of USART HAL module
stm32f3xx_hal_usart_ex.h [code] | Header file of USART HAL Extended module
stm32f3xx_hal_wwdg.c [code] | WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration function + IO operation functions
stm32f3xx_hal_wwdg.h [code] | Header file of WWDG HAL module
stm32f3xx_ll_adc.c [code] | ADC LL module driver
stm32f3xx_ll_adc.h [code] | Header file of ADC LL module
stm32f3xx_ll_bus.h [code] | Header file of BUS LL module
stm32f3xx_ll_comp.c [code] | COMP LL module driver
stm32f3xx_ll_comp.h [code] | Header file of COMP LL module
stm32f3xx_ll_cortex.h [code] | Header file of CORTEX LL module
stm32f3xx_ll_crc.c [code] | CRC LL module driver
stm32f3xx_ll_crc.h [code] | Header file of CRC LL module
stm32f3xx_ll_dac.c [code] | DAC LL module driver
stm32f3xx_ll_dac.h [code] | Header file of DAC LL module
stm32f3xx_ll_dma.c [code] | DMA LL module driver
stm32f3xx_ll_dma.h [code] | Header file of DMA LL module
stm32f3xx_ll_exti.c [code] | EXTI LL module driver
stm32f3xx_ll_exti.h [code] | Header file of EXTI LL module
stm32f3xx_ll_gpio.c [code] | GPIO LL module driver
stm32f3xx_ll_gpio.h [code] | Header file of GPIO LL module
stm32f3xx_ll_hrtim.c [code] | HRTIM LL module driver
stm32f3xx_ll_hrtim.h [code] | Header file of HRTIM LL module
stm32f3xx_ll_i2c.c [code] | I2C LL module driver
stm32f3xx_ll_i2c.h [code] | Header file of I2C LL module
stm32f3xx_ll_iwdg.h [code] | Header file of IWDG LL module
stm32f3xx_ll_opamp.c [code] | OPAMP LL module driver
stm32f3xx_ll_opamp.h [code] | Header file of OPAMP LL module
stm32f3xx_ll_pwr.c [code] | PWR LL module driver
stm32f3xx_ll_pwr.h [code] | Header file of PWR LL module
stm32f3xx_ll_rcc.c [code] | RCC LL module driver
stm32f3xx_ll_rcc.h [code] | Header file of RCC LL module
stm32f3xx_ll_rtc.c [code] | RTC LL module driver
stm32f3xx_ll_rtc.h [code] | Header file of RTC LL module
stm32f3xx_ll_spi.c [code] | SPI LL module driver
stm32f3xx_ll_spi.h [code] | Header file of SPI LL module
stm32f3xx_ll_system.h [code] | Header file of SYSTEM LL module
stm32f3xx_ll_tim.c [code] | TIM LL module driver
stm32f3xx_ll_tim.h [code] | Header file of TIM LL module
stm32f3xx_ll_usart.c [code] | USART LL module driver
stm32f3xx_ll_usart.h [code] | Header file of USART LL module
stm32f3xx_ll_utils.c [code] | UTILS LL module driver
stm32f3xx_ll_utils.h [code] | Header file of UTILS LL module
stm32f3xx_ll_wwdg.h [code] | Header file of WWDG LL module
Generated on Tue Jun 13 2017 08:20:22 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: GPIO_rmtollPages.txt File Reference

  • File List
  • Globals
GPIO_rmtollPages.txt File Reference
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC

Modules
ADC
STM32F3xx_HAL_Driver

ADC HAL module driver. More...

Modules

ADC Exported Functions
ADC Exported Types
ADC Exported Macros

Detailed Description

ADC HAL module driver.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Exported Functions

Modules
ADC Exported Functions
ADC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

ADC Peripheral State functions.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Exported Init structure

Data Structures
ADC Exported Init structure
ADC

Data Structures

struct | LL_ADC_InitTypeDef
Structure definition of some features of ADC instance. More...
struct | LL_ADC_REG_InitTypeDef
Structure definition of some features of ADC group regular. More...
struct | LL_ADC_INJ_InitTypeDef
Structure definition of some features of ADC group injected. More...
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Exported Constants

Modules
ADC Exported Constants
ADC

Modules

ADC flags

Flags defines which can be used with LL_ADC_ReadReg function.

ADC interruptions for configuration (interruption enable or disable)

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions.

ADC registers compliant with specific purpose
ADC common - Measurement path to internal channels
ADC instance - Resolution
ADC instance - Data alignment
ADC instance - Scan selection
ADC instance - Groups
ADC instance - Channel number
ADC group regular - Trigger source
ADC group regular - Trigger edge
ADC group regular - Continuous mode
ADC group regular - DMA transfer
ADC group regular - Sequencer scan length
ADC group regular - Sequencer discontinuous mode
ADC group regular - Sequencer ranks
ADC group injected - Trigger source
ADC group injected - Trigger edge
ADC group injected - Automatic trigger mode
ADC group injected - Sequencer scan length
ADC group injected - Sequencer discontinuous mode
ADC group injected - Sequencer ranks
Channel - Sampling time
Analog watchdog - Analog watchdog number
Analog watchdog - Monitored channels
Analog watchdog - Thresholds
Definitions of ADC hardware constraints delays
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Exported Functions

Modules
ADC Exported Functions
ADC

Modules

ADC DMA management
Configuration of ADC hierarchical scope: common to several ADC instances
Configuration of ADC hierarchical scope: ADC instance
Configuration of ADC hierarchical scope: group regular
Configuration of ADC hierarchical scope: group injected
Configuration of ADC hierarchical scope: channels
Configuration of ADC transversal scope: analog watchdog
Operation on ADC hierarchical scope: ADC instance
Operation on ADC hierarchical scope: group regular
Operation on ADC hierarchical scope: group injected
ADC flag management
ADC IT management
Initialization and de-initialization functions
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADC Exported Macros

Modules
ADC Exported Macros
ADC

Modules

Common write and read registers Macros
ADC helper macro
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STM32F373xC HAL User Manual: ADCEx

Modules
ADCEx
STM32F3xx_HAL_Driver

ADC Extended HAL module driver. More...

Modules

ADCEx Private Constants
ADCEx Exported Functions
ADCEx Private Functions
ADCEx Exported Types
ADCEx Exported Constants
ADCEx Exported Macros
ADCEx Private Macros

Detailed Description

ADC Extended HAL module driver.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADCEx Exported Constants

Modules
ADCEx Exported Constants
ADCEx

Modules

ADC Extended Error Code
ADC Extended Data Alignment
ADC Extended Scan Mode
ADC Extended External trigger enable for regular group
ADC Extended External trigger selection for regular group
ADC Extended Channels
ADC Extended Sampling Times
ADC Extended rank into regular group
ADC Extended Injected Channel Rank
External Trigger Edge of Injected Group
External Trigger Source of Injected Group
ADC Extended analog watchdog mode
ADC Conversion Group
ADC Extended Event Type
ADC Extended Interrupts Definition
ADC Extended Flags Definition
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADCEx Exported Functions

Modules
ADCEx Exported Functions
ADCEx

Modules

ADCEx Initialization and de-initialization functions

ADC Extended Initialization and Configuration functions.

ADCEx Input and Output operation functions

ADC Extended IO operation functions.

ADCEx Peripheral Control functions

ADC Extended Peripheral Control functions.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: ADCEx Exported Types

Data Structures
ADCEx Exported Types
ADCEx

Data Structures

struct | ADC_InitTypeDef
Structure definition of ADC and regular group initialization. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_InjectionConfTypeDef
ADC Configuration injected Channel structure definition. More...
struct | ADC_AnalogWDGConfTypeDef
ADC Configuration analog watchdog definition. More...
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: BUS Exported Constants

Modules
BUS Exported Constants
BUS

Modules

AHB1 GRP1 PERIPH
APB1 GRP1 PERIPH
APB2 GRP1 PERIPH
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: BUS Exported Functions

Modules
BUS Exported Functions
BUS

Modules

AHB1
APB1
APB2
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN

Modules
CAN
STM32F3xx_HAL_Driver

CAN driver modules. More...

Modules

CAN Private Constants
CAN Private Functions

CAN Frame message Rx/Tx functions.

CAN Exported Functions
CAN Exported Types
CAN Exported Constants
CAN Exported Macros
CAN Private Types
CAN Private Variables
CAN Private Macros

Detailed Description

CAN driver modules.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Exported Constants

Modules
CAN Exported Constants
CAN

Modules

CAN Error Code
CAN InitStatus
CAN Operating Mode
CAN Synchronization Jump Width
CAN Time Quantum in Bit Segment 1
CAN Time Quantum in Bit Segment 2
CAN Filter Mode
CAN Filter Scale
CAN Filter FIFO
CAN Identifier Type
CAN Remote Transmission Request
CAN Receive FIFO Number
CAN Flags
CAN Interrupts
CAN Mailboxes
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CAN Exported Functions

Modules
CAN Exported Functions
CAN

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

IO operation functions.

Peripheral State and Error functions

CAN Peripheral State functions.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC

Modules
CEC
STM32F3xx_HAL_Driver

HAL CEC module driver. More...

Modules

CEC Private Constants
CEC Private Functions
CEC Exported Functions
CEC Exported Types
CEC Exported Constants
CEC Exported Macros
CEC Private Types
CEC Private Variables
CEC Private Macros

Detailed Description

HAL CEC module driver.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC Exported Constants

Modules
CEC Exported Constants
CEC

Modules

CEC Error Code
CEC Signal Free Time setting parameter
CEC Receiver Tolerance
CEC Reception Stop on Error
CEC Error Bit Generation if Bit Rise Error reported
CEC Error Bit Generation if Long Bit Period Error reported
CEC Error Bit Generation on Broadcast message
CEC Signal Free Time start option
CEC Listening mode option
CEC Device Own Address position in CEC CFGR register
CEC Initiator logical address position in message header
CEC Own Address
CEC Interrupts definition
CEC Flags definition
CEC all RX or TX errors flags
CEC all RX errors interrupts enabling flag
CEC all TX errors interrupts enabling flag
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CEC Exported Functions

Modules
CEC Exported Functions
CEC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

CEC Transmit/Receive functions.

Peripheral Control function

CEC control functions.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP

Modules
COMP
STM32F3xx_HAL_Driver

COMP HAL module driver. More...

Modules

COMP Private Constants
COMP Exported Functions
COMP Exported Types
COMP Exported Constants
COMP Exported Macros
COMP Private Macros

Detailed Description

COMP HAL module driver.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Exported Constants

Modules
COMP Exported Constants
COMP

Modules

COMP Output Polarity
COMP Output Level
COMP Trigger Mode
COMP State Lock
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Exported Functions

Modules
COMP Exported Functions
COMP

Modules

Initialization/de-initialization functions

Initialization and de-initialization functions.

Start Stop operation functions

Start-Stop operation functions.

Peripheral Control functions

Management functions.

Peripheral State functions

Peripheral State functions.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Exported Init structure

Data Structures
COMP Exported Init structure
COMP

Data Structures

struct LL_COMP_InitTypeDef
Structure definition of some features of COMP instance. More...
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Exported Constants

Modules
COMP Exported Constants
COMP

Modules

Comparator common modes - Window mode
Comparator modes - Power mode
Comparator inputs - Input plus (input non-inverting) selection
Comparator inputs - Input minus (input inverting) selection
Comparator input - Hysteresis
Comparator output - Output selection
Comparator output - Output polarity
Comparator output - Output level
Definitions of COMP hardware constraints delays
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Exported Functions

Modules
COMP Exported Functions
COMP

Modules

Configuration of COMP hierarchical scope: common to several COMP instances
Configuration of comparator modes
Configuration of comparator inputs
Configuration of comparator output
Operation on comparator instance
Initialization and de-initialization functions
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Exported Macros

Modules
COMP Exported Macros
COMP

Modules

Common write and read registers macro
COMP helper macro
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Private Macros

Modules
COMP Private Macros
COMP

Modules

COMP Private macros to check input parameters
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMPEx

Modules
COMPEx
STM32F3xx_HAL_Driver

Modules

COMP Extended Exported Constants
COMP Extended Exported Macros
COMP Extended Private Constants
COMP Extended Private Macros
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Extended Exported Constants

Modules
COMP Extended Exported Constants
COMPEx

Modules

COMP Extended InvertingInput (STM32F373xC/STM32F378xx Product devices)
COMP Extended NonInvertingInput (STM32F373xC/STM32F378xx Product devices)
COMP Extended Output (STM32F373xC/STM32F378xx Product devices)

Elements value convention: 00000XXX000000YYb.

COMP Extended WindowMode (STM32F373xC/STM32F378xx Product devices)
COMP Extended Mode
COMP Extended Hysteresis
COMP Extended Blanking Source (STM32F373xC/STM32F378xx Product devices)
COMP Flag
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Extended Private Constants

Modules
COMP Extended Private Constants
COMPEx

Modules

COMP Extended EXTI lines
COMP Extended miscellaneous defines
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: COMP Extended Private Macros

Modules
COMP Extended Private Macros
COMPEx

Modules

COMP Extended Private macro to get the EXTI line associated with a comparator handle
COMP Extended miscellaneous private macros
COMP Extended Private macros to check input parameters
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CORTEX

Modules
CORTEX
STM32F3xx_HAL_Driver

CORTEX CORTEX HAL module driver. More...

Modules

CORTEX Exported Functions
CORTEX Exported Types
CORTEX Exported Constants
CORTEX Private Macros
CORTEX Private Functions

CORTEX private functions.

Detailed Description

CORTEX CORTEX HAL module driver.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CORTEX Exported Constants

Modules
CORTEX Exported Constants
CORTEX

Modules

CORTEX Preemption Priority Group
CORTEX SysTick clock source
MPU HFNMI and PRIVILEGED Access control
CORTEX MPU Region Enable
CORTEX MPU Instruction Access
CORTEX MPU Instruction Access Shareable
CORTEX MPU Instruction Access Cacheable
CORTEX MPU Instruction Access Bufferable
MPU TEX Levels
CORTEX MPU Region Size
CORTEX MPU Region Permission Attributes
CORTEX MPU Region Number
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CORTEX Exported Functions

Modules
CORTEX Exported Functions
CORTEX

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

Cortex control functions.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CORTEX Exported Types

Modules
CORTEX Exported Types
CORTEX

Modules

MPU Region Initialization Structure Definition

MPU Region initialization structure.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CORTEX Exported Constants

Modules
CORTEX Exported Constants
CORTEX

Modules

SYSTICK Clock Source
Handler Fault type
MPU Control
MPU Region Number
MPU Region Size
MPU Region Privileges
MPU TEX Level
MPU Instruction Access
MPU Shareable Access
MPU Cacheable Access
MPU Bufferable Access
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CORTEX Exported Functions

Modules
CORTEX Exported Functions
CORTEX

Modules

SYSTICK
LOW POWER MODE
HANDLER
MCU INFO
MPU
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: MPU Region Initialization Structure Definition

Data Structures
MPU Region Initialization Structure Definition
CORTEX Exported Types

MPU Region initialization structure. More...

Data Structures

struct MPU_Region_InitTypeDef

Detailed Description

MPU Region initialization structure.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRC

Modules
CRC
STM32F3xx_HAL_Driver

CRC HAL module driver. More...

Modules

CRC Private Functions
CRC Exported Functions
CRC Exported Types
CRC Exported Constants
CRC Exported Macros
CRC aliases for Exported Functions
CRC Private Macros

Detailed Description

CRC HAL module driver.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRC Exported Constants

Modules
CRC Exported Constants
CRC

Modules

Default CRC generating polynomial
Default CRC computation initialization value
Indicates whether or not default polynomial is used
Indicates whether or not default init value is used
Polynomial sizes to configure the IP
CRC polynomial possible sizes actual definitions
Input Buffer Format
Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRC Exported Functions

Modules
CRC Exported Functions
CRC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

management functions.

Peripheral State functions

Peripheral State functions.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRC Exported Constants

Modules
CRC Exported Constants
CRC

Modules

Polynomial length
Input Data Reverse
Output Data Reverse
Default CRC generating polynomial value

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .

Default CRC computation initialization value
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRC Exported Functions

Modules
CRC Exported Functions
CRC

Modules

CRC Configuration functions
Data_Management
Initialization and de-initialization functions
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRC Exported Macros

Modules
CRC Exported Macros
CRC

Modules

Common Write and read registers Macros
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRCEx

Modules
CRCEx
STM32F3xx_HAL_Driver

CRC Extended HAL module driver. More...

Modules

CRC Extended Exported Functions
CRC Extended Exported Constants
CRC Extended Exported Macros
CRCEx Private Macros

Detailed Description

CRC Extended HAL module driver.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRC Extended Exported Constants

Modules
CRC Extended Exported Constants
CRCEx

Modules

CRC Extended Input Data Inversion Modes
CRC Extended Output Data Inversion Modes
Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: CRC Extended Exported Functions

Modules
CRC Extended Exported Functions
CRCEx

Modules

CRC Extended Initialization and de-initialization functions

CRC Extended Initialization and Configuration functions.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC

Modules
DAC
STM32F3xx_HAL_Driver

DAC HAL module driver. More...

Modules

DAC Private Macros
DAC Private Functions
DAC Exported Functions
DAC Exported Types
DAC Exported Constants
DAC Exported Macros

Detailed Description

DAC HAL module driver.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC Exported Constants

Modules
DAC Exported Constants
DAC

Modules

DAC Error Code
DAC lfsrunmask triangleamplitude
DAC output buffer
DAC data alignement
DAC flags definition
DAC interrupts definition
Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC Exported Functions

Modules
DAC Exported Functions
DAC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State and Error functions

DAC Peripheral State and Error functions.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC Exported Init structure

Data Structures
DAC Exported Init structure
DAC

Data Structures

struct LL_DAC_InitTypeDef
Structure definition of some features of DAC instance. More...
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC Exported Constants

Modules
DAC Exported Constants
DAC

Modules

DAC flags

Flags defines which can be used with LL_DAC_ReadReg function.

DAC interruptions

IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions.

DAC channels
DAC trigger source
DAC waveform automatic generation mode
DAC wave generation - Noise LFSR unmask bits
DAC wave generation - Triangle amplitude
DAC channel output buffer
DAC channel output resolution
DAC registers compliant with specific purpose
Definitions of DAC hardware constraints delays
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC Exported Functions

Modules
DAC Exported Functions
DAC

Modules

Configuration of DAC channels
DMA Management
Operation on DAC channels
FLAG Management
IT management
Initialization and de-initialization functions
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DAC Exported Macros

Modules
DAC Exported Macros
DAC

Modules

Common write and read registers macros
DAC helper macro
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DACEx

Modules
DACEx
STM32F3xx_HAL_Driver

DAC HAL module driver. More...

Modules

DACEx Private Functions
DACEx Exported Functions
DACEx Exported Constants
DACEx Private Macros

Detailed Description

DAC HAL module driver.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DACEx Exported Constants

Modules
DACEx Exported Constants
DACEx

Modules

DACEx trigger selection
DACEx Channel selection
Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DACEx Exported Functions

Modules
DACEx Exported Functions
DACEx

Modules

DACEx Peripheral Control functions

Peripheral Control functions.

DACEx Input and Output operation functions

IO operation functions.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA

Modules
DMA
STM32F3xx_HAL_Driver

DMA HAL module driver. More...

Modules

DMA Private Functions
DMA Exported Functions
DMA Exported Types
DMA Exported Constants
DMA Exported Macros
DMA Private Macros

DMA private macros.

Detailed Description

DMA HAL module driver.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMA

Modules

DMA Error Code
DMA Data transfer direction
DMA Peripheral incremented mode
DMA Memory incremented mode
DMA Peripheral data size
DMA Memory data size
DMA mode
DMA Priority level
DMA interrupt enable definitions
DMA flag definitions
Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Exported Functions

Modules
DMA Exported Functions
DMA

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Input and Output operation functions

I/O operation functions.

Peripheral State functions

Peripheral State functions.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Exported Init structure

Data Structures
DMA Exported Init structure
DMA

Data Structures

struct LL_DMA_InitTypeDef
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMA

Modules

Clear Flags Defines

Flags defines which can be used with LL_DMA_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_DMA_ReadReg function.

IT Defines

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions.

CHANNEL
Transfer Direction
Transfer mode
Peripheral increment mode
Memory increment mode
Peripheral data alignment
Memory data alignment
Transfer Priority level
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STM32F373xC HAL User Manual: DMA Exported Functions

Modules
DMA Exported Functions
DMA

Modules

Configuration
FLAG_Management
IT_Management
Initialization and de-initialization functions
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: DMA Exported Macros

Modules
DMA Exported Macros
DMA

Modules

Common Write and read registers macros
Convert DMAxChannely
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STM32F373xC HAL User Manual: DMAEx

Modules
DMAEx
STM32F3xx_HAL_Driver

Modules

DMA Extended Exported Macros
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: EXTI Exported Init structure

Data Structures
EXTI Exported Init structure
EXTI

Data Structures

struct LL_EXTI_InitTypeDef
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: EXTI Exported Constants

Modules
EXTI Exported Constants
EXTI

Modules

LINE
Mode
Edge Trigger
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STM32F373xC HAL User Manual: EXTI Exported Functions

Modules
EXTI Exported Functions
EXTI

Modules

IT_Management
Event_Management
Rising_Trigger_Management
Falling_Trigger_Management
Software_Interrupt_Management
Flag_Management
Initialization and de-initialization functions
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STM32F373xC HAL User Manual: EXTI Exported Macros

Modules
EXTI Exported Macros
EXTI

Modules

Common Write and read registers Macros
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STM32F373xC HAL User Manual: FLASH

Modules
FLASH
STM32F3xx_HAL_Driver

FLASH HAL module driver. More...

Modules

FLASH Private Constants
FLASH Private Macros
FLASH Private Variables
FLASH Private Functions
FLASH Exported Functions
FLASH Exported Types
FLASH Exported Constants
FLASH Exported Macros

macros to control FLASH features

Detailed Description

FLASH HAL module driver.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASH Exported Constants

Modules
FLASH Exported Constants
FLASH

Modules

FLASH Error Codes
FLASH Type Program
FLASH Latency
FLASH Flag definition
FLASH Interrupt definition
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STM32F373xC HAL User Manual: FLASH Exported Functions

Modules
FLASH Exported Functions
FLASH

Modules

Programming operation functions

Programming operation functions.

Peripheral Control functions

management functions

Peripheral errors functions

Peripheral errors functions.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASH Exported Macros

Modules
FLASH Exported Macros
FLASH

macros to control FLASH features More...

Modules

FLASH Half Cycle

macros to handle FLASH half cycle

FLASH Latency

macros to handle FLASH Latency

FLASH Prefetch

macros to handle FLASH Prefetch buffer

FLASH Interrupts

macros to handle FLASH interrupts

Detailed Description

macros to control FLASH features

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASHEx

Modules
FLASHEx
STM32F3xx_HAL_Driver

FLASH HAL Extension module driver. More...

Modules

FLASHEx Private Constants
FLASHEx Private Macros
FLASHEx Private Functions
FLASHEx Exported Functions
FLASHEx Exported Types
FLASHEx Exported Constants

Detailed Description

FLASH HAL Extension module driver.

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STM32F373xC HAL User Manual: FLASHEx Exported Constants

Modules
FLASHEx Exported Constants
FLASHEx

Modules

FLASHEx Page Size
FLASH Type Erase
Option Byte Constants
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STM32F373xC HAL User Manual: FLASHEx Exported Functions

Modules
FLASHEx Exported Functions
FLASHEx

Modules

FLASHEx Memory Erasing functions

FLASH Memory Erasing functions.

Option Bytes Programming functions

Option Bytes Programming functions.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: FLASHEx Exported Types

Data Structures
FLASHEx Exported Types
FLASHEx

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Options bytes program structure definition. More...
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STM32F373xC HAL User Manual: Option Byte Constants

Modules
Option Byte Constants
FLASHEx Exported Constants

Modules

Option Bytes Type
Option Byte WRP State
FLASHEx OB Write Protection
Option Byte Read Protection
Option Byte IWatchdog
Option Byte nRST STOP
Option Byte nRST STDBY
Option Byte BOOT1
Option Byte VDDA Analog Monitoring
Option Byte SRAM Parity Check Enable
OB SDADC12 VDD MONITOR
Option Byte Data Address
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STM32F373xC HAL User Manual: GPIO

Modules
GPIO
STM32F3xx_HAL_Driver

GPIO HAL module driver. More...

Modules

GPIO Private Defines
GPIO Private Macros
GPIO Exported Functions
GPIO Exported Types
GPIO Exported Constants
GPIO Exported Macros

Detailed Description

GPIO HAL module driver.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: GPIO Exported Constants

Modules
GPIO Exported Constants
GPIO

Modules

GPIO pins
GPIO mode

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ.

GPIO speed

GPIO Output Maximum frequency.

GPIO pull

GPIO Pull-Up or Pull-Down Activation.

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STM32F373xC HAL User Manual: GPIO Exported Functions

Modules
GPIO Exported Functions
GPIO

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

IO operation functions

GPIO Read, Write, Toggle, Lock and EXTI management functions.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: GPIO Exported Init structures

Data Structures
GPIO Exported Init structures
GPIO

Data Structures

struct LL_GPIO_InitTypeDef
LL GPIO Init Structure definition. More...
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STM32F373xC HAL User Manual: GPIO Exported Constants

Modules
GPIO Exported Constants
GPIO

Modules

PIN
Mode
Output Type
Output Speed
Pull Up Pull Down
Alternate Function
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STM32F373xC HAL User Manual: GPIO Exported Functions

Modules
GPIO Exported Functions
GPIO

Modules

Port Configuration
Data Access
Initialization and de-initialization functions
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STM32F373xC HAL User Manual: GPIO Exported Macros

Modules
GPIO Exported Macros
GPIO

Modules

Common Write and read registers Macros
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STM32F373xC HAL User Manual: GPIOEx

Modules
GPIOEx
STM32F3xx_HAL_Driver

GPIO Extended HAL module driver. More...

Modules

GPIOEx Exported Constants
GPIOEx Exported Macros

Detailed Description

GPIO Extended HAL module driver.

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STM32F373xC HAL User Manual: GPIOEx Exported Constants

Modules
GPIOEx Exported Constants
GPIOEx

Modules

GPIOEx Alternate function selection
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STM32F373xC HAL User Manual: GPIOEx Exported Macros

Modules
GPIOEx Exported Macros
GPIOEx

Modules

GPIOEx_Get Port Index
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STM32F373xC HAL User Manual: HAL

Modules
HAL
STM32F3xx_HAL_Driver

HAL module driver. More...

Modules

Constants
HAL Private Variables
HAL Exported Functions
HAL Exported Constants
HAL Exported Macros
HAL_Private_Macros

Detailed Description

HAL module driver.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HAL Exported Constants

Modules
HAL Exported Constants
HAL

Modules

SYSCFG registers bit address in the alias region

SYSCFG registers bit address in the alias region.

HAL DMA Remapping

Elements values convention: 0xXXYYYYYY.

HAL Trigger Remapping

Elements values convention: 0xXXYYYYYY.

Fast-mode Plus on GPIO
HAL SYSCFG Interrupts
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STM32F373xC HAL User Manual: HAL Exported Functions

Modules
HAL Exported Functions
HAL

Modules

Initialization and de-initialization Functions

Initialization and de-initialization functions.

HAL Control functions

HAL Control functions.

Generated on Tue Jun 13 2017 08:20:12 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: HAL Exported Macros

Modules
HAL Exported Macros
HAL

Modules

Freeze/Unfreeze APB1 Peripherals in Debug mode
Freeze/Unfreeze APB2 Peripherals in Debug mode
Memory Mapping Selection
Encoder Mode
DMA Remap Enable
Fast-mode Plus on GPIO
Floating Point Unit Interrupts Enable
VBAT Monitoring Enable
Cortex Lockup Enable
PVD Lock
SRAM Parity Lock
Trigger Remapping Enable
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STM32F373xC HAL User Manual: I2C Configuration Structure definition

Data Structures
I2C Configuration Structure definition
I2C Exported Types

I2C Configuration Structure definition. More...

Data Structures

struct I2C_InitTypeDef

Detailed Description

I2C Configuration Structure definition.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C Exported Constants

Modules
I2C Exported Constants
I2C

Modules

I2C Sequential Transfer Options
I2C Addressing Mode
I2C Dual Addressing Mode
I2C Own Address2 Masks
I2C General Call Addressing Mode
I2C No-Stretch Mode
I2C Memory Address Size
I2C Transfer Direction Master Point of View
I2C Reload End Mode
I2C Start or Stop Mode
I2C Interrupt configuration definition

I2C Interrupt definition Elements values convention: 0xXXXXXXXX.

I2C Flag definition
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STM32F373xC HAL User Manual: I2C Exported Functions

Modules
I2C Exported Functions
I2C

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

IRQ Handler and Callbacks
Peripheral State, Mode and Error functions

Peripheral State, Mode and Error functions.

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STM32F373xC HAL User Manual: I2C Exported Types

Modules
I2C Exported Types
I2C

Modules

I2C Configuration Structure definition

I2C Configuration Structure definition.

HAL state structure definition

HAL State structure definition.

HAL mode structure definition

HAL Mode structure definition.

I2C Error Code definition

I2C Error Code definition.

I2C handle Structure definition

I2C handle Structure definition.

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STM32F373xC HAL User Manual: I2C Exported Init structure

Data Structures
I2C Exported Init structure
I2C

Data Structures

struct LL_I2C_InitTypeDef
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STM32F373xC HAL User Manual: I2C Exported Constants

Modules
I2C Exported Constants
I2C

Modules

Clear Flags Defines

Flags defines which can be used with LL_I2C_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_I2C_ReadReg function.

IT Defines

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions.

Peripheral Mode
Analog Filter Selection
Master Addressing Mode
Own Address 1 Length
Own Address 2 Masks
Acknowledge Generation
Slave Address Length
Transfer Request Direction
Transfer End Mode
Start And Stop Generation
Read Write Direction
DMA Register Data
SMBus TimeoutA Mode SCL SDA Timeout
SMBus Timeout Selection
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STM32F373xC HAL User Manual: I2C Exported Functions

Modules
I2C Exported Functions
I2C

Modules

Configuration
IT_Management
FLAG_management
Data_Management
Initialization and de-initialization functions
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STM32F373xC HAL User Manual: I2C Exported Macros

Modules
I2C Exported Macros
I2C

Modules

Common Write and read registers Macros
Convert SDA SCL timings
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2CEx

Modules
I2CEx
STM32F3xx_HAL_Driver

I2C Extended HAL module driver. More...

Modules

I2C Extended Exported Functions
I2C Extended Exported Constants

Detailed Description

I2C Extended HAL module driver.

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STM32F373xC HAL User Manual: I2C Extended Exported Constants

Modules
I2C Extended Exported Constants
I2CEx

Modules

I2C Extended Analog Filter
I2C Extended Fast Mode Plus
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STM32F373xC HAL User Manual: I2C Extended Exported Functions

Modules
I2C Extended Exported Functions
I2CEx

Modules

Extended features functions

Extended features functions.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S

Modules
I2S
STM32F3xx_HAL_Driver | I2SEx

I2S HAL module driver. More...

Modules

I2S Private Functions
I2S Exported Functions
I2S Exported Types
I2S Exported Constants
I2S Exported Macros

Detailed Description

I2S HAL module driver.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Exported Constants

Modules
I2S Exported Constants
I2S

Modules

I2S Error
I2S Clock Source
I2S Mode
I2S Standard
I2S Data Format
I2S MCLK Output
I2S Audio Frequency
I2S Full Duplex Mode
I2S Clock Polarity
I2S Interrupt configuration definition
I2S Flag definition
Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Exported Functions

Modules
I2S Exported Functions
I2S

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

Peripheral State functions.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Exported Init structure

Data Structures
I2S Exported Init structure
I2S

Data Structures

struct LL_I2S_InitTypeDef
I2S Init structure definition. More...
Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Exported Constants

Modules
I2S Exported Constants
I2S

Modules

Get Flags Defines

Flags defines which can be used with LL_I2S_ReadReg function.

IT Defines

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Data format
Clock Polarity
I2s Standard
Operation Mode
Prescaler Factor
MCLK Output
Audio Frequency
Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S Exported Functions

Modules
I2S Exported Functions
I2S

Modules

Configuration
FLAG Management
Interrupt Management
DMA Management
DATA Management
Initialization and de-initialization functions
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STM32F373xC HAL User Manual: I2S Exported Macros

Modules
I2S Exported Macros
I2S

Modules

Common Write and read registers Macros
Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2SEx

Modules
I2SEx
STM32F3xx_HAL_Driver

I2S Extended HAL module driver. More...

Modules

I2S Extended Exported Macros
I2S

I2S HAL module driver.

I2S Extended Exported Functions

Detailed Description

I2S Extended HAL module driver.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA

Modules
IRDA
STM32F3xx_HAL_Driver

IRDA HAL module driver. More...

Modules

IRDA Private Constants
IRDA Exported Functions
IRDA Private Functions
IRDA Exported Types
IRDA Exported Constants
IRDA Exported Macros
IRDA Private Macros

Detailed Description

IRDA HAL module driver.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDA Exported Constants

Modules
IRDA Exported Constants
IRDA

Modules

IRDA Error
IRDA Parity
IRDA Transfer Mode
IRDA Low Power
IRDA State
IRDA Mode
IRDA One Bit Sampling
IRDA DMA Tx
IRDA DMA Rx
IRDA Request Parameters
IRDA Flags

Elements values convention: 0xXXXX.

IRDA Interrupts Definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

IRDA Interruption Clear Flags
IRDA interruptions flags mask
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STM32F373xC HAL User Manual: IRDA Exported Functions

Modules
IRDA Exported Functions
IRDA

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IRDA Transmit and Receive functions.

Peripheral State and Error functions

IRDA State and Errors functions.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDAEx

Modules
IRDAEx
STM32F3xx_HAL_Driver

Modules

IRDAEx Exported Constants
IRDAEx Private Macros
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IRDAEx Exported Constants

Modules
IRDAEx Exported Constants
IRDAEx

Modules

IRDA Word Length
Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IWDG

Modules
IWDG
STM32F3xx_HAL_Driver

IWDG HAL module driver. More...

Modules

IWDG Private Defines
IWDG Exported Types
IWDG Exported Constants
IWDG Exported Macros
IWDG Exported Functions
IWDG Private Constants
IWDG Private Macros

Detailed Description

IWDG HAL module driver.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IWDG Exported Constants

Modules
IWDG Exported Constants
IWDG

Modules

IWDG Prescaler
IWDG Window option
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STM32F373xC HAL User Manual: IWDG Exported Functions

Modules
IWDG Exported Functions
IWDG

Modules

Initialization and Start functions

Initialization and Start functions.

IO operation functions

IO operation functions.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IWDG Exported Types

Data Structures
IWDG Exported Types
IWDG

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...
Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IWDG Exported Constants

Modules
IWDG Exported Constants
IWDG

Modules

Get Flags Defines

Flags defines which can be used with LL_IWDG_ReadReg function.

Prescaler Divider
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IWDG Exported Functions

Modules
IWDG Exported Functions
IWDG

Modules

Configuration
FLAG_Management
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IWDG Exported Macros

Modules
IWDG Exported Macros
IWDG

Modules

Common Write and read registers Macros
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Clocks Frequency Structure

Data Structures
Clocks Frequency Structure
RCC Exported Types

Data Structures

struct LL_RCC_ClocksTypeDef
RCC Clocks Frequency Structure. More...
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD

Modules
PCD
STM32F3xx_HAL_Driver

PCD HAL module driver. More...

Modules

PCD Private Define
PCD Private Functions
PCD Exported Functions
PCD Exported Types
PCD Exported Constants
PCD Exported Macros

macros to handle interrupts and specific clock configurations

PCD Private Constants
PCD Instance definition
PCD Private Macros
Peripheral Control functions

management functions

Peripheral State functions

Peripheral State functions.

PCD Extended Private Functions

Detailed Description

PCD HAL module driver.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD Exported Constants

Modules
PCD Exported Constants
PCD

Modules

PCD Core Speed
PCD Core PHY
Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD Exported Functions

Modules
PCD Exported Functions
PCD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral Control functions

management functions

Peripheral State functions

Peripheral State functions.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCD Private Constants

Modules
PCD Private Constants
PCD

Modules

USB EXTI line interrupt
PCD EP0 MPS
PCD EP Type
PCD ENDP
PCD Endpoint Kind
Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCDEx

Modules
PCDEx
STM32F3xx_HAL_Driver

PCD Extended HAL module driver. More...

Modules

PCDEx Exported Functions
PCD Extended Private Functions
PCD Extended Exported Macros

Detailed Description

PCD Extended HAL module driver.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PCDEx Exported Functions

Modules
PCDEx Exported Functions
PCDEx

Modules

Peripheral Control functions

PCDEx control functions.

Extended Initialization and de-initialization functions
Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR

Modules
PWR
STM32F3xx_HAL_Driver

Modules

PWR Exported Constants
PWR Exported Macro
PWR Private Macros
PWR Exported Functions
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Exported Constants

Modules
PWR Exported Constants
PWR

Modules

PWR WakeUp Pins
PWR Regulator state in STOP mode
PWR SLEEP mode entry
PWR STOP mode entry
PWR Flag
Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Exported Functions

Modules
PWR Exported Functions
PWR

Modules

Initialization and de-initialization functions
Peripheral Control functions

Low Power modes configuration functions.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Exported Constants

Modules
PWR Exported Constants
PWR

Modules

Clear Flags Defines

Flags defines which can be used with LL_PWR_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_PWR_ReadReg function.

Mode Power
Regulator Mode In Deep Sleep Mode
Power Voltage Detector Level
Wakeup Pins
SDADC Analogx
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Exported Functions

Modules
PWR Exported Functions
PWR

Modules

Configuration
FLAG_Management
De-initialization function
Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Exported Macros

Modules
PWR Exported Macros
PWR

Modules

Common write and read registers Macros
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STM32F373xC HAL User Manual: PWREx

Modules
PWREx
STM32F3xx_HAL_Driver

PWREx HAL module driver. More...

Modules

PWR Extended Private Constants
PWR Extended Exported Functions
PWR Extended Exported Types
PWR Extended Exported Constants
PWR Extended Exported Macros
PWR Extended Private Macros

Detailed Description

PWREx HAL module driver.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Extended Exported Functions

Modules
PWR Extended Exported Functions
PWREx

Modules

Peripheral Extended Control Functions

Extended Peripheral Control functions.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: PWR Extended Exported Types

Data Structures
PWR Extended Exported Types
PWREx

Data Structures

struct PWR_PVDTypeDef
PWR PVD configuration structure definition. More...
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STM32F373xC HAL User Manual: RCC

Modules
RCC
STM32F3xx_HAL_Driver

RCC HAL module driver. More...

Modules

RCC Private Constants
RCC Private Macros
RCC Private Variables
RCC Exported Functions
RCC Exported Types
RCC Exported Constants
RCC Exported Macros

Detailed Description

RCC HAL module driver.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Exported Constants

Modules
RCC Exported Constants
RCC

Modules

PLL Clock Source
Oscillator Type
HSE Config
LSE Config
HSI Config
LSI Config
PLL Config
System Clock Type
System Clock Source
System Clock Source Status
AHB Clock Source
APB1 APB2 Clock Source
RTC Clock Source
RCC PLL Multiplication Factor
RCC PLL HSE Prediv Factor
RCC USART2 Clock Source
RCC USART3 Clock Source
RCC I2C1 Clock Source
MCO Index
Interrupts
Flags

Elements values convention: XXXYYYYYb.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Exported Functions

Modules
RCC Exported Functions
RCC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

RCC clocks control functions.

Generated on Tue Jun 13 2017 08:20:13 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Exported Macros

Modules
RCC Exported Macros
RCC

Modules

RCC AHB Clock Enable Disable

Enable or disable the AHB peripheral clock.

RCC APB1 Clock Enable Disable

Enable or disable the Low Speed APB (APB1) peripheral clock.

RCC APB2 Clock Enable Disable

Enable or disable the High Speed APB (APB2) peripheral clock.

AHB Peripheral Clock Enable Disable Status

Get the enable or disable status of the AHB peripheral clock.

APB1 Peripheral Clock Enable Disable Status

Get the enable or disable status of the APB1 peripheral clock.

APB2 Peripheral Clock Enable Disable Status

EGet the enable or disable status of the APB2 peripheral clock.

RCC AHB Force Release Reset

Force or release AHB peripheral reset.

RCC APB1 Force Release Reset

Force or release APB1 peripheral reset.

RCC APB2 Force Release Reset

Force or release APB2 peripheral reset.

HSI Configuration
LSI Configuration
HSE Configuration
LSE Configuration
RCC USARTx Clock Config
RCC I2Cx Clock Config
PLL Configuration
Get Clock source
RCC Extended MCOx Clock Config
RCC RTC Clock Configuration
Flags Interrupts Management

macros to manage the specified RCC Flags and interrupts.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Exported Types

Data Structures
RCC Exported Types
RCC

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition. More...
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STM32F373xC HAL User Manual: RCC Exported Constants

Modules
RCC Exported Constants
RCC

Modules

Oscillator Values adaptation

Defines used to adapt values of different oscillators.

Clear Flags Defines

Flags defines which can be used with LL_RCC_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_RCC_ReadReg function.

IT Defines

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions.

LSE oscillator drive capability
System clock switch
System clock switch status
AHB prescaler
APB low-speed prescaler (APB1)
APB high-speed prescaler (APB2)
MCO1 SOURCE selection
MCO1 prescaler
Peripheral clock frequency
Peripheral USART clock source selection
Peripheral I2C clock source selection
Peripheral CEC clock source selection
Peripheral USB clock source selection
Peripheral ADC clock source selection
Peripheral SDADC clock source selection
Peripheral USART get clock source
Peripheral I2C get clock source
Peripheral CEC get clock source
Peripheral USB get clock source
Peripheral ADC get clock source
Peripheral SDADC get clock source
RTC clock source selection
PLL Multiplicator factor
PLL SOURCE
PREDIV Division factor
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STM32F373xC HAL User Manual: RCC Exported Functions

Modules
RCC Exported Functions
RCC

Modules

HSE
HSI
LSE
LSI
System
MCO
Peripheral Clock Source
RTC
PLL
FLAG Management
IT Management
De-initialization function
Get system and peripherals clocks frequency functions

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks and different peripheral clocks available on the device.

Generated on Tue Jun 13 2017 08:20:18 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Exported Macros

Modules
RCC Exported Macros
RCC

Modules

Common Write and read registers Macros
Calculate frequencies
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STM32F373xC HAL User Manual: RCC Exported Types

Modules
RCC Exported Types
RCC

Modules

Clocks Frequency Structure
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STM32F373xC HAL User Manual: RCCEx

Modules
RCCEx
STM32F3xx_HAL_Driver

RCC Extension HAL module driver. More...

Modules

RCCEx Private Macros
RCCEx Private Functions
RCCEx Exported Functions
RCCEx Exported Types
RCC Extended Exported Constants
RCC Extended Exported Macros

Detailed Description

RCC Extension HAL module driver.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Extended Exported Constants

Modules
RCC Extended Exported Constants
RCCEx

Modules

RCC Extended MCO Clock Source
RCC Extended Periph Clock Selection
RCC Extended USART1 Clock Source
RCC Extended I2C2 Clock Source
RCC Extended ADC1 Clock Source
RCC Extended CEC Clock Source
RCC Extended SDADC Clock Prescaler
RCC Extended USB Clock Source
RCC Extended MCOx Clock Prescaler
RCC LSE Drive Configuration
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STM32F373xC HAL User Manual: RCCEx Exported Functions

Modules
RCCEx Exported Functions
RCCEx

Modules

Extended Peripheral Control functions

Extended Peripheral Control functions.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RCC Extended Exported Macros

Modules
RCC Extended Exported Macros
RCCEx

Modules

RCC Extended PLL Configuration
RCC Extended HSE Configuration
RCC Extended AHB Clock Enable Disable

Enable or disable the AHB peripheral clock.

RCC Extended APB1 Clock Enable Disable

Enable or disable the Low Speed APB (APB1) peripheral clock.

RCC Extended APB2 Clock Enable Disable

Enable or disable the High Speed APB (APB2) peripheral clock.

RCC Extended AHB Peripheral Clock Enable Disable Status

Get the enable or disable status of the AHB peripheral clock.

RCC Extended APB1 Peripheral Clock Enable Disable Status

Get the enable or disable status of the APB1 peripheral clock.

RCC Extended APB2 Peripheral Clock Enable Disable Status

Get the enable or disable status of the APB2 peripheral clock.

RCC Extended AHB Force Release Reset

Force or release AHB peripheral reset.

RCC Extended APB1 Force Release Reset

Force or release APB1 peripheral reset.

RCC Extended APB2 Force Release Reset

Force or release APB2 peripheral reset.

RCC Extended I2Cx Clock Config
RCC Extended ADCx Clock Config
RCC Extended SDADCx Clock Config
RCC Extended CECx Clock Config
RCC Extended USBx Clock Config
LSE Drive Configuration
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STM32F373xC HAL User Manual: RCCEx Exported Types

Data Structures
RCCEx Exported Types
RCCEx

Data Structures

struct RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...
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STM32F373xC HAL User Manual: RTC Exported Constants

Modules
RTC Exported Constants
RTC

Modules

RTC Hour Formats
RTC Output Polarity Definitions
RTC Output Type ALARM OUT
RTC AM PM Definitions
RTC DayLightSaving Definitions
RTC StoreOperation Definitions
RTC Input parameter format definitions
RTC Month Date Definitions
RTC WeekDay Definitions
RTC AlarmDateWeekDay Definitions
RTC AlarmMask Definitions
RTC Alarms Definitions
RTC Alarm Sub Seconds Masks Definitions
RTC Interrupts Definitions
RTC Flags Definitions
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STM32F373xC HAL User Manual: RTC Exported Init structure

Data Structures
RTC Exported Init structure
RTC

Data Structures

struct | LL_RTC_InitTypeDef
RTC Init structures definition. More...
struct | LL_RTC_TimeTypeDef
RTC Time structure definition. More...
struct | LL_RTC_DateTypeDef
RTC Date structure definition. More...
struct | LL_RTC_AlarmTypeDef
RTC Alarm structure definition. More...
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STM32F373xC HAL User Manual: RTC Exported Constants

Modules
RTC Exported Constants
RTC

Modules

FORMAT
RTC Alarm A Date WeekDay
RTC Alarm B Date WeekDay
Get Flags Defines

Flags defines which can be used with LL_RTC_ReadReg function.

IT Defines

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions.

WEEK DAY
MONTH
HOUR FORMAT
ALARM OUTPUT
ALARM OUTPUT TYPE
PIN
OUTPUT POLARITY PIN
TIME FORMAT
SHIFT SECOND
ALARMA MASK
ALARMA TIME FORMAT
ALARMB MASK
ALARMB TIME FORMAT
TIMESTAMP EDGE
TIMESTAMP TIME FORMAT
TAMPER
TAMPER MASK
TAMPER NO ERASE
TAMPER DURATION
TAMPER FILTER
TAMPER SAMPLING FREQUENCY DIVIDER
TAMPER ACTIVE LEVEL
WAKEUP CLOCK DIV
BACKUP
Calibration output
Calibration pulse insertion
Calibration period
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STM32F373xC HAL User Manual: RTC Exported Functions

Modules
RTC Exported Functions
RTC

Modules

Configuration
Time
Date
ALARMA
ALARMB
Timestamp
Tamper
Wakeup
Backup_Registers
Calibration
FLAG_Management
IT_Management
Initialization and de-initialization functions
Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Exported Macros

Modules
RTC Exported Macros
RTC

Modules

Common Write and read registers Macros
Convert helper Macros
Date helper Macros
Time helper Macros
Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Private Macros

Modules
RTC Private Macros
RTC

Modules

RTC Private macros to check input parameters
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STM32F373xC HAL User Manual: RTCEx

Modules
RTCEx
STM32F3xx_HAL_Driver

RTC Extended HAL module driver. More...

Modules

RTC Extended Exported Types
RTC Extended Exported Constants
RTC Extended Exported Macros
RTCEx Exported Functions
RTCEx Private Macros

Detailed Description

RTC Extended HAL module driver.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Exported Constants

Modules
RTC Extended Exported Constants
RTCEx

Modules

RTC Extended Output Selection Definition
RTC Extended Backup Registers Definition
RTC Extended Time Stamp Edges definition
RTC Extended TimeStamp Pin Selection
RTC Extended Tamper Pins Definition
RTC Extended Tamper Trigger Definition
RTC Extended Tamper Filter Definition
RTC Extended Tamper Sampling Frequencies Definition
RTC Extended Tamper Pin Precharge Duration Definition
RTC Extended Tamper TimeStampOnTamperDetection Definition
RTC Extended Tamper Pull UP Definition
RTC Extended Wakeup Timer Definition
RTC Extended Smooth calib period Definition
RTC Extended Smooth calib Plus pulses Definition
RTC Extended Calib Output selection Definition
RTC Extended Add 1 Second Parameter Definition
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STM32F373xC HAL User Manual: RTCEx Exported Functions

Modules
RTCEx Exported Functions
RTCEx

Modules

Extended RTC TimeStamp and Tamper functions

RTC TimeStamp and Tamper functions.

Extended RTC Wake-up functions

RTC Wake-up functions.

Extended Peripheral Control functions

Extended Peripheral Control functions.

Extended features functions

Extended features functions.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: RTC Extended Exported Macros

Modules
RTC Extended Exported Macros
RTCEx

Modules

RTC Extended WakeUp Timer
RTC Extended Timestamp
RTC Extended Tamper
EXTI RTC Extended Tamper Timestamp EXTI
RTC Extended Calibration
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STM32F373xC HAL User Manual: RTC Extended Exported Types

Data Structures
RTC Extended Exported Types
RTCEx

Data Structures

struct RTC_TamperTypeDef
RTC Tamper structure definition. More...
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STM32F373xC HAL User Manual: RTCEx Private Macros

Modules
RTCEx Private Macros
RTCEx

Modules

Private macros to check input parameters
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STM32F373xC HAL User Manual: SDADC

Modules
SDADC
STM32F3xx_HAL_Driver

SDADC HAL driver modules. More...

Modules

SDADC Private Define
SDADC Private Functions
SDADC Exported Functions
SDADC Exported Types
SDADC Exported Constants
SDADC Exported Macros
SDADC Private Macros

Detailed Description

SDADC HAL driver modules.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SDADC Exported Constants

Modules
SDADC Exported Constants
SDADC

Modules

SDADC Idle Low Power Mode
SDADC Fast Conversion Mode
SDADC Slow Clock Mode
SDADC Reference Voltage
SDADC Configuration Index
SDADC Input Mode
SDADC Gain
SDADC Common Mode
SDADC Channel Selection
SDADC Calibration Sequence
SDADC Continuous Mode
SDADC Trigger
SDADC Injected External Trigger
SDADC External Trigger Edge
SDADC Injected Conversion Delay
SDADC Multimode Type
SDADC Error Code
SDADC interrupts definition
SDADC flags definition
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STM32F373xC HAL User Manual: SDADC Exported Functions

Modules
SDADC Exported Functions
SDADC

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

peripheral control functions

Peripheral control functions.

Input and Output operation functions

IO operation Control functions.

Peripheral State functions

SDADC Peripheral State functions.

SDADC Private Functions
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STM32F373xC HAL User Manual: SMARTCARD

Modules
SMARTCARD
STM32F3xx_HAL_Driver

SMARTCARD HAL module driver. More...

Modules

SMARTCARD Private Constants
SMARTCARD Exported Functions
SMARTCARD Private Functions
SMARTCARD Exported Types
SMARTCARD Exported Constants
SMARTCARD Exported Macros
SMARTCARD Private Macros

Detailed Description

SMARTCARD HAL module driver.

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STM32F373xC HAL User Manual: SMARTCARD Exported Constants

Modules
SMARTCARD Exported Constants
SMARTCARD

Modules

SMARTCARD Error
SMARTCARD Word Length
SMARTCARD Number of Stop Bits
SMARTCARD Parity
SMARTCARD Transfer Mode
SMARTCARD Clock Polarity
SMARTCARD Clock Phase
SMARTCARD Last Bit
SMARTCARD One Bit Sampling Method
SMARTCARD NACK Enable
SMARTCARD Timeout Enable
SMARTCARD advanced feature initialization type
SMARTCARD advanced feature TX pin active level inversion
SMARTCARD advanced feature RX pin active level inversion
SMARTCARD advanced feature Binary Data inversion
SMARTCARD advanced feature RX TX pins swap
SMARTCARD advanced feature Overrun Disable
SMARTCARD advanced feature DMA Disable on Rx Error
SMARTCARD advanced feature MSB first
SMARTCARD Flags

Elements values convention: 0xXXXX.

SMARTCARD Interrupts Definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

SMARTCARD Interruption Clear Flags
SMARTCARD auto retry counter LSB position in CR3 register
SMARTCARD guard time value LSB position in GTPR register
SMARTCARD block length LSB position in RTOR register
SMARTCARD interruptions flags mask
SMARTCARD Request Parameters
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STM32F373xC HAL User Manual: SMARTCARD Exported Functions

Modules
SMARTCARD Exported Functions
SMARTCARD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

SMARTCARD Transmit and Receive functions.

Peripheral State and Errors functions

SMARTCARD State and Errors functions.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARDEx

Modules
SMARTCARDEx
STM32F3xx_HAL_Driver

SMARTCARD Extension HAL module driver. More...

Modules

SMARTCARD Extended Exported Functions
SMARTCARD Extended Private Macros

Detailed Description

SMARTCARD Extension HAL module driver.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMARTCARD Extended Exported Functions

Modules
SMARTCARD Extended Exported Functions
SMARTCARDEx

Modules

Extended Peripheral Control functions

Extended control functions.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS

Modules
SMBUS
STM32F3xx_HAL_Driver

SMBUS HAL module driver. More...

Modules

SMBUS Private Constants
SMBUS Exported Functions
SMBUS Exported Types
SMBUS Exported Constants
SMBUS Exported Macros
SMBUS Private Macros
SMBUS Private Functions

Data transfers Private functions.

Detailed Description

SMBUS HAL module driver.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS Configuration Structure definition

Data Structures
SMBUS Configuration Structure definition
SMBUS Exported Types

SMBUS Configuration Structure definition. More...

Data Structures

struct SMBUS_InitTypeDef

Detailed Description

SMBUS Configuration Structure definition.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS Exported Constants

Modules
SMBUS Exported Constants
SMBUS

Modules

SMBUS Analog Filter
SMBUS addressing mode
SMBUS dual addressing mode
SMBUS ownaddress2 masks
SMBUS general call addressing mode
SMBUS nostretch mode
SMBUS packet error check mode
SMBUS peripheral mode
SMBUS ReloadEndMode definition
SMBUS StartStopMode definition
SMBUS XferOptions definition
SMBUS Interrupt configuration definition

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX.

SMBUS Flag definition

Flag definition Elements values convention: 0xXXXXYYYY.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS Exported Functions

Modules
SMBUS Exported Functions
SMBUS

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

IRQ Handler and Callbacks
Peripheral State and Errors functions

Peripheral State and Errors functions.

SMBUS Private Functions

Data transfers Private functions.

Generated on Tue Jun 13 2017 08:20:14 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS Exported Types

Modules
SMBUS Exported Types
SMBUS

Modules

SMBUS Configuration Structure definition

SMBUS Configuration Structure definition.

HAL state definition

HAL State definition.

SMBUS Error Code definition

SMBUS Error Code definition.

SMBUS handle Structure definition

SMBUS handle Structure definition.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SMBUS handle Structure definition

Data Structures
SMBUS handle Structure definition
SMBUS Exported Types

SMBUS handle Structure definition. More...

Data Structures

struct SMBUS_HandleTypeDef

Detailed Description

SMBUS handle Structure definition.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI

Modules
SPI
STM32F3xx_HAL_Driver

SPI HAL module driver. More...

Modules

SPI Private Constants
SPI Private Functions

Private functions.

SPI Exported Functions
SPI Exported Types
SPI Exported Constants
SPI Exported Macros
SPI Private Macros

Detailed Description

SPI HAL module driver.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Exported Constants

Modules
SPI Exported Constants
SPI

Modules

SPI Error Code
SPI Mode
SPI Direction Mode
SPI Data Size
SPI Clock Polarity
SPI Clock Phase
SPI Slave Select Management
SPI NSS Pulse Mode
SPI BaudRate Prescaler
SPI MSB LSB Transmission
SPI TI Mode
SPI CRC Calculation
SPI CRC Length

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit.

SPI FIFO Reception Threshold

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/2(16-bits).

SPI Interrupt Definition
SPI Flags Definition
SPI Transmission FIFO Status Level
SPI Reception FIFO Status Level
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STM32F373xC HAL User Manual: SPI Exported Functions

Modules
SPI Exported Functions
SPI

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

SPI control functions.

Generated on Tue Jun 13 2017 08:20:15 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Exported Init structure

Data Structures
SPI Exported Init structure
SPI

Data Structures

struct LL_SPI_InitTypeDef
SPI Init structures definition. More...
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STM32F373xC HAL User Manual: SPI Exported Constants

Modules
SPI Exported Constants
SPI

Modules

Get Flags Defines

Flags defines which can be used with LL_SPI_ReadReg function.

IT Defines

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Operation Mode
Serial Protocol
Clock Phase
Clock Polarity
Baud Rate Prescaler
Transmission Bit Order
Transfer Mode
Slave Select Pin Mode
Datawidth
CRC Calculation
CRC Length
RX FIFO Threshold
RX FIFO Level
TX FIFO Level
DMA Parity
Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Exported Functions

Modules
SPI Exported Functions
SPI

Modules

Configuration
CRC Management
Slave Select Pin Management
FLAG Management
Interrupt Management
DMA Management
DATA Management
Initialization and de-initialization functions
Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPI Exported Macros

Modules
SPI Exported Macros
SPI

Modules

Common Write and read registers Macros
Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPIEx

Modules
SPIEx
STM32F3xx_HAL_Driver

SPI Extended HAL module driver. More...

Modules

SPIEx Private Constants
SPIEx Exported Functions

Detailed Description

SPI Extended HAL module driver.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SPIEx Exported Functions

Modules
SPIEx Exported Functions
SPIEx

Modules

IO operation functions

Data transfers functions.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: STM32F3xx_HAL_Driver

Modules
STM32F3xx_HAL_Driver

Modules

HAL

HAL module driver.

ADC

ADC HAL module driver.

ADCEx

ADC Extended HAL module driver.

CAN

CAN driver modules.

CEC

HAL CEC module driver.

COMP

COMP HAL module driver.

COMPEx
CORTEX

CORTEX CORTEX HAL module driver.

CRC

CRC HAL module driver.

CRCEx

CRC Extended HAL module driver.

DAC

DAC HAL module driver.

DACEx

DAC HAL module driver.

DMA

DMA HAL module driver.

FLASH

FLASH HAL module driver.

FLASHEx

FLASH HAL Extension module driver.

GPIO

GPIO HAL module driver.

GPIOEx

GPIO Extended HAL module driver.

I2C

I2C HAL module driver.

I2CEx

I2C Extended HAL module driver.

I2S

I2S HAL module driver.

I2SEx

I2S Extended HAL module driver.

IRDA

IRDA HAL module driver.

IWDG

IWDG HAL module driver.

PCD

PCD HAL module driver.

PCDEx

PCD Extended HAL module driver.

PWREx

PWREx HAL module driver.

RCC

RCC HAL module driver.

RCCEx

RCC Extension HAL module driver.

RTC

RTC HAL module driver.

RTCEx

RTC Extended HAL module driver.

SDADC

SDADC HAL driver modules.

SMARTCARD

SMARTCARD HAL module driver.

SMARTCARDEx

SMARTCARD Extension HAL module driver.

SMBUS

SMBUS HAL module driver.

SPI

SPI HAL module driver.

SPIEx

SPI Extended HAL module driver.

TIM

TIM HAL module driver.

TIMEx

TIM Extended HAL module driver.

TSC

HAL TSC module driver.

UART

UART HAL module driver.

UARTEx

UART Extension HAL module driver.

USART

USART HAL module driver.

WWDG

WWDG HAL module driver.

DACEx Private Functions
DMAEx
IRDAEx
PWR
USARTEx
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: STM32F3xx_LL_Driver

Modules
STM32F3xx_LL_Driver

Modules

ADC
BUS
COMP
CORTEX
CRC
DAC
DMA
EXTI
GPIO
I2C
IWDG
PWR
RCC
RTC
SPI
I2S
SYSTEM
TIM
USART
UTILS
WWDG
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SYSTEM Exported Constants

Modules
SYSTEM Exported Constants
SYSTEM

Modules

SYSCFG REMAP
SYSCFG DAC1/2 DMA1/2 request REMAP
SYSCFG TIM DMA request REMAP
SYSCFG I2C FASTMODEPLUS
SYSCFG EXTI PORT
SYSCFG EXTI LINE
SYSCFG TIMER BREAK
DBGMCU TRACE Pin Assignment
DBGMCU APB1 GRP1 STOP IP
DBGMCU APB2 GRP1 STOP IP
FLASH LATENCY
Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: SYSTEM Exported Functions

Modules
SYSTEM Exported Functions
SYSTEM

Modules

SYSCFG
DBGMCU
FLASH
Generated on Tue Jun 13 2017 08:20:19 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM

Modules
TIM
STM32F3xx_HAL_Driver

TIM HAL module driver. More...

Modules

TIM Private Functions
TIM Exported Functions
TIM Exported Types
TIM Exported Constants
TIM Exported Macros
TIM Private Constants
TIM Private Macros

Detailed Description

TIM HAL module driver.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Exported Constants

Modules
TIM Exported Constants
TIM

Modules

TIM Input Channel Polarity
TIM ETR Polarity
TIM ETR Prescaler
TIM Counter Mode
TIM Clock Division
TIM Auto-Reload Preload
TIM Output Fast State
TIM Output Compare Polarity
TIM Complementary Output Compare Polarity
TIM Output Compare Idle State
TIM Complementary Output Compare Idle State
TIM Input Capture Polarity
TIM Input Capture Selection
TIM Input Capture Prescaler
TIM One Pulse Mode
TIM Encoder Mode
TIM Interrupt Definition
TIM Commutation Source
TIM DMA Sources
TIM Flag Definition
TIM Clock Source
TIM Clock Polarity
TIM Clock Prescaler
TIM Clear Input Polarity
TIM Clear Input Prescaler
TIM OSSR Off State Selection for Run mode state
TIM OSSI Off State Selection for Idle mode state
TIM Lock level
TIM Break Input Enable Disable
TIM Break Input Polarity
TIM Automatic Output Enable
TIM Master Mode Selection
TIM Master Slave Mode
TIM Trigger Selection
TIM Trigger Polarity
TIM Trigger Prescaler
TIM TI1 Input Selection
TIM DMA Burst Length
TIM DMA Handle Index
TIM Capture/Compare Channel State
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STM32F373xC HAL User Manual: TIM Exported Functions

Modules
TIM Exported Functions
TIM

Modules

Time Base functions

Time Base functions.

Time Output Compare functions

Time Output Compare functions.

Time PWM functions

Time PWM functions.

Time Input Capture functions

Time Input Capture functions.

Time One Pulse functions

Time One Pulse functions.

Time Encoder functions

Time Encoder functions.

TIM IRQ handler management

IRQ handler management.

Peripheral Control functions

Peripheral Control functions.

TIM Callbacks functions

TIM Callbacks functions.

Peripheral State functions

Peripheral State functions.

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STM32F373xC HAL User Manual: TIM Exported Init structure

Data Structures
TIM Exported Init structure
TIM

Data Structures

struct | LL_TIM_InitTypeDef
TIM Time Base configuration structure definition. More...
struct | LL_TIM_OC_InitTypeDef
TIM Output Compare configuration structure definition. More...
struct | LL_TIM_IC_InitTypeDef
TIM Input Capture configuration structure definition. More...
struct | LL_TIM_ENCODER_InitTypeDef
TIM Encoder interface configuration structure definition. More...
struct | LL_TIM_HALLSENSOR_InitTypeDef
TIM Hall sensor interface configuration structure definition. More...
struct | LL_TIM_BDTR_InitTypeDef
BDTR (Break and Dead Time) structure definition. More...
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STM32F373xC HAL User Manual: TIM Exported Constants

Modules
TIM Exported Constants
TIM

Modules

Get Flags Defines

Flags defines which can be used with LL_TIM_ReadReg function.

Break Enable
Automatic output enable
IT Defines

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.

Update Source
One Pulse Mode
Counter Mode
Clock Division
Counter Direction
Capture Compare Update Source
Capture Compare DMA Request
Lock Level
Channel
Output Configuration State
Output Configuration Mode
Output Configuration Polarity
Output Configuration Idle State
Active Input Selection
Input Configuration Prescaler
Input Configuration Filter
Input Configuration Polarity
Clock Source
Encoder Mode
Trigger Output
Slave Mode
Trigger Selection
External Trigger Polarity
External Trigger Prescaler
External Trigger Filter
break polarity
OSSI
OSSR
DMA Burst Base Address
DMA Burst Length
TIM16 External Input Ch1 Remap
TIM14 Timer Input1 Remap
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STM32F373xC HAL User Manual: TIM Exported Functions

Modules
TIM Exported Functions
TIM

Modules

Time Base configuration
Capture Compare configuration
Output channel configuration
Input channel configuration
Counter clock selection
Timer synchronisation configuration
Break function configuration
DMA burst mode configuration
Timer input remapping
FLAG-Management
IT-Management
DMA-Management
EVENT-Management
Initialisation and deinitialisation functions
Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIM Exported Macros

Modules
TIM Exported Macros
TIM

Modules

Common Write and read registers Macros
Exported_Macros
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STM32F373xC HAL User Manual: TIMEx

Modules
TIMEx
STM32F3xx_HAL_Driver

TIM Extended HAL module driver. More...

Modules

TIMEx Private Functions
TIMEx Exported Functions
TIMEx Exported Types
TIMEx Exported Constants
TIM Private Macros
TIMEx Exported Macros

Detailed Description

TIM Extended HAL module driver.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TIMEx Exported Constants

Modules
TIMEx Exported Constants
TIMEx

Modules

TIMEx Channel
TIMEx Output Compare and PWM Modes
TIMEx Clear Input Source
TIMEx Slave Mode
TIMEx Event Source
TIMEx DMA BAse Address
TIMEx remapping
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STM32F373xC HAL User Manual: TIMEx Exported Functions

Modules
TIMEx Exported Functions
TIMEx

Modules

Timer Hall Sensor functions

Timer Hall Sensor functions.

Timer Complementary Output Compare functions

Timer Complementary Output Compare functions.

Timer Complementary PWM functions

Timer Complementary PWM functions.

Timer Complementary One Pulse functions

Timer Complementary One Pulse functions.

Peripheral Control functions

Peripheral Control functions.

Extension Callbacks functions

Extension Callbacks functions.

Extended Peripheral State functions

Extended Peripheral State functions.

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STM32F373xC HAL User Manual: TIMEx Exported Types

Data Structures
TIMEx Exported Types
TIMEx

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break and Dead time configuration Structure definition. More...
Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TSC

Modules
TSC
STM32F3xx_HAL_Driver

HAL TSC module driver. More...

Modules

Exported Functions
Private Functions
TSC Exported Types
TSC Exported Constants
TSC Exported Macros
TSC Private Macros

Detailed Description

HAL TSC module driver.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: TSC Exported Constants

Modules
TSC Exported Constants
TSC

Modules

CTPulse High Length
CTPulse Low Length
Spread Spectrum Prescaler
Pulse Generator Prescaler
Max Count Value
IO Default Mode
Synchro Pin Polarity
Acquisition Mode
IO Mode
Interrupts definition
Flags definition
Group definition
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STM32F373xC HAL User Manual: Exported Functions

Modules
Exported Functions
TSC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Input and Output operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

IRQ Handler and Callbacks
Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART

Modules
UART
STM32F3xx_HAL_Driver

UART HAL module driver. More...

Modules

UART Private Constants
UART Exported Functions
UART Private Functions
UART Exported Types
UART Exported Constants
UART Exported Macros
UART Private Macros

Detailed Description

UART HAL module driver.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Exported Constants

Modules
UART Exported Constants
UART

Modules

UART Error
UART Number of Stop Bits
UART Parity
UART Hardware Flow Control
UART Transfer Mode
UART State
UART Over Sampling
UART One Bit Sampling Method
UART Advanced Feature AutoBaud Rate Mode
UART Receiver TimeOut
UART Local Interconnection Network mode
UART LIN Break Detection
UART DMA Tx
UART DMA Rx
UART Half Duplex Selection
UART WakeUp Address Length
UART WakeUp Methods
UART Status Flags

Elements values convention: 0xXXXX.

UART Interrupts Definition

Elements values convention: 000ZZZZZ0XXYYYYYb.

UART Interruption Clear Flags
UART Request Parameters
UART Advanced Feature Initialization Type
UART Advanced Feature TX Pin Active Level Inversion
UART Advanced Feature RX Pin Active Level Inversion
UART Advanced Feature Binary Data Inversion
UART Advanced Feature RX TX Pins Swap
UART Advanced Feature Overrun Disable
UART Advanced Feature Auto BaudRate Enable
UART Advanced Feature DMA Disable On Rx Error
UART Advanced Feature MSB First
UART Advanced Feature Stop Mode Enable
UART Advanced Feature Mute Mode Enable
UART Address-matching LSB Position In CR2 Register
UART WakeUp From Stop Selection
UART DriverEnable Polarity
UART Driver Enable Assertion Time LSB Position In CR1 Register
UART Driver Enable DeAssertion Time LSB Position In CR1 Register
UART Interruptions Flag Mask
UART polling-based communications time-out value
Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UART Exported Functions

Modules
UART Exported Functions
UART

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

UART Transmit/Receive functions.

Peripheral Control functions

UART control functions.

Peripheral State and Error functions

UART Peripheral State functions.

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STM32F373xC HAL User Manual: UARTEx

Modules
UARTEx
STM32F3xx_HAL_Driver

UART Extension HAL module driver. More...

Modules

UARTEx Exported Functions
UARTEx Exported Constants
UARTEx Private Macros

Detailed Description

UART Extension HAL module driver.

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STM32F373xC HAL User Manual: UARTEx Exported Constants

Modules
UARTEx Exported Constants
UARTEx

Modules

UARTEx Word Length
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STM32F373xC HAL User Manual: UARTEx Exported Functions

Modules
UARTEx Exported Functions
UARTEx

Modules

Extended Initialization and de-initialization functions

Extended Initialization and Configuration Functions.

Extended IO operation function

Extended UART Interrupt handling function.

Extended Peripheral Control functions

Extended Peripheral Control functions.

Generated on Tue Jun 13 2017 08:20:16 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART

Modules
USART
STM32F3xx_HAL_Driver

USART HAL module driver. More...

Modules

USART Private Constants
USART Exported Functions
USART Private Functions

USART Private functions.

USART Exported Types
USART Exported Constants
USART Exported Macros
USART Private Macros

Detailed Description

USART HAL module driver.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Exported Constants

Modules
USART Exported Constants
USART

Modules

USART Error
USART Number of Stop Bits
USART Parity
USART Mode
USART Clock
USART Clock Polarity
USART Clock Phase
USART Last Bit
USART Request Parameters
USART Flags

Elements values convention: 0xXXXX.

USART Interrupts Definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

USART Interruption Clear Flags
USART Interruption Flags Mask
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Exported Functions

Modules
USART Exported Functions
USART

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

USART Transmit and Receive functions.

Peripheral State and Error functions

USART Peripheral State and Error functions.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Exported Init structures

Data Structures
USART Exported Init structures
USART

Data Structures

struct | LL_USART_InitTypeDef
LL USART Init Structure definition. More...
struct | LL_USART_ClockInitTypeDef
LL USART Clock Init Structure definition. More...
Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Exported Constants

Modules
USART Exported Constants
USART

Modules

Clear Flags Defines

Flags defines which can be used with LL_USART_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_USART_ReadReg function.

IT Defines

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions.

Communication Direction
Parity Control
Wakeup
Datawidth
Oversampling
Clock Signal
Last Clock Pulse
Clock Phase
Clock Polarity
Stop Bits
TX RX Pins Swap
RX Pin Active Level Inversion
TX Pin Active Level Inversion
Binary Data Inversion
Bit Order
Autobaud Detection
Address Length Detection
Hardware Control
Wakeup Activation
IrDA Power
LIN Break Detection Length
Driver Enable Polarity
DMA Register Data
Generated on Tue Jun 13 2017 08:20:20 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Exported Functions

Modules
USART Exported Functions
USART

Modules

Configuration functions
Configuration functions related to Irda feature
Configuration functions related to Smartcard feature
Configuration functions related to Half Duplex feature
Configuration functions related to LIN feature
Configuration functions related to Driver Enable feature
Advanced Configurations services
FLAG_Management
IT_Management
DMA_Management
Data_Management
Execution
Initialization and de-initialization functions
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USART Exported Macros

Modules
USART Exported Macros
USART

Modules

Common Write and read registers Macros
Exported_Macros_Helper
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USARTEx

Modules
USARTEx
STM32F3xx_HAL_Driver

Modules

USARTEx Exported Constants
USARTEx Private Macros
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: USARTEx Exported Constants

Modules
USARTEx Exported Constants
USARTEx

Modules

USARTEx Word Length
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UTILS

Modules
UTILS
STM32F3xx_LL_Driver

Modules

UTILS Private functions
UTILS Private Constants
UTILS Private Macros
UTILS Exported structures
UTILS Exported Constants
UTILS Exported Functions
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STM32F373xC HAL User Manual: UTILS Exported structures

Data Structures
UTILS Exported structures
UTILS

Data Structures

struct | LL_UTILS_PLLInitTypeDef
UTILS PLL structure definition. More...
struct | LL_UTILS_ClkInitTypeDef
UTILS System, AHB and APB buses clock configuration structure definition. More...
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UTILS Exported Constants

Modules
UTILS Exported Constants
UTILS

Modules

HSE Bypass activation
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: UTILS Exported Functions

Modules
UTILS Exported Functions
UTILS

Modules

DEVICE ELECTRONIC SIGNATURE
DELAY
SYSTEM

System Configuration functions.

Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: WWDG

Modules
WWDG
STM32F3xx_HAL_Driver

WWDG HAL module driver. More...

Modules

WWDG Exported Functions
WWDG Exported Types
WWDG Exported Constants
WWDG Private Macros
WWDG Exported Macros

Detailed Description

WWDG HAL module driver.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: WWDG Exported Constants

Modules
WWDG Exported Constants
WWDG

Modules

WWDG Interrupt definition
WWDG Flag definition

WWDG Flag definition.

WWDG Prescaler
WWDG Early Wakeup Interrupt Mode
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STM32F373xC HAL User Manual: WWDG Exported Functions

Modules
WWDG Exported Functions
WWDG

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: WWDG Exported Types

Data Structures
WWDG Exported Types
WWDG

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | WWDG_HandleTypeDef
WWDG handle Structure definition. More...
Generated on Tue Jun 13 2017 08:20:17 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: WWDG Exported Constants

Modules
WWDG Exported Constants
WWDG

Modules

IT Defines

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions.

PRESCALER
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: WWDG Exported Functions

Modules
WWDG Exported Functions
WWDG

Modules

Configuration
FLAG_Management
IT_Management
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: WWDG Exported Macros

Modules
WWDG Exported Macros
WWDG

Modules

Common Write and read registers macros
Generated on Tue Jun 13 2017 08:20:21 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2C_rmtollPages.txt File Reference

  • File List
  • Globals
I2C_rmtollPages.txt File Reference
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: I2S_rmtollPages.txt File Reference

  • File List
  • Globals
I2S_rmtollPages.txt File Reference
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: IWDG_rmtollPages.txt File Reference

  • File List
  • Globals
IWDG_rmtollPages.txt File Reference
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: Modules

Modules
Here is a list of all modules:
  • STM32F3xx_LL_Driver
    • ADC
      • ADC Private Constants
      • ADC Private Macros
      • ADC Exported Init structure
      • ADC Exported Constants
        • ADC flags
        • ADC interruptions for configuration (interruption enable or disable)
        • ADC registers compliant with specific purpose
        • ADC common - Measurement path to internal channels
        • ADC instance - Resolution
        • ADC instance - Data alignment
        • ADC instance - Scan selection
        • ADC instance - Groups
        • ADC instance - Channel number
        • ADC group regular - Trigger source
        • ADC group regular - Trigger edge
        • ADC group regular - Continuous mode
        • ADC group regular - DMA transfer
        • ADC group regular - Sequencer scan length
        • ADC group regular - Sequencer discontinuous mode
        • ADC group regular - Sequencer ranks
        • ADC group injected - Trigger source
        • ADC group injected - Trigger edge
        • ADC group injected - Automatic trigger mode
        • ADC group injected - Sequencer scan length
        • ADC group injected - Sequencer discontinuous mode
        • ADC group injected - Sequencer ranks
        • Channel - Sampling time
        • Analog watchdog - Analog watchdog number
        • Analog watchdog - Monitored channels
        • Analog watchdog - Thresholds
        • Definitions of ADC hardware constraints delays
      • ADC Exported Macros
        • Common write and read registers Macros
        • ADC helper macro
      • ADC Exported Functions
        • ADC DMA management
        • Configuration of ADC hierarchical scope: common to several ADC instances
        • Configuration of ADC hierarchical scope: ADC instance
        • Configuration of ADC hierarchical scope: group regular
        • Configuration of ADC hierarchical scope: group injected
        • Configuration of ADC hierarchical scope: channels
        • Configuration of ADC transversal scope: analog watchdog
        • Operation on ADC hierarchical scope: ADC instance
        • Operation on ADC hierarchical scope: group regular
        • Operation on ADC hierarchical scope: group injected
        • ADC flag management
        • ADC IT management
        • Initialization and de-initialization functions
    • BUS
      • BUS Exported Constants
        • AHB1 GRP1 PERIPH
        • APB1 GRP1 PERIPH
        • APB2 GRP1 PERIPH
      • BUS Exported Functions
        • AHB1
        • APB1
        • APB2
    • COMP
      • COMP Private Constants
      • COMP Private Macros
      • COMP Exported Init structure
      • COMP Exported Constants
        • Comparator common modes - Window mode
        • Comparator modes - Power mode
        • Comparator inputs - Input plus (input non-inverting) selection
        • Comparator inputs - Input minus (input inverting) selection
        • Comparator input - Hysteresis
        • Comparator output - Output selection
        • Comparator output - Output polarity
        • Comparator output - Output level
        • Definitions of COMP hardware constraints delays
      • COMP Exported Macros
        • Common write and read registers macro
        • COMP helper macro
      • COMP Exported Functions
        • Configuration of COMP hierarchical scope: common to several COMP instances
        • Configuration of comparator modes
        • Configuration of comparator inputs
        • Configuration of comparator output
        • Operation on comparator instance
        • Initialization and de-initialization functions
    • CORTEX
      • CORTEX Exported Constants
        • SYSTICK Clock Source
        • Handler Fault type
        • MPU Control
        • MPU Region Number
        • MPU Region Size
        • MPU Region Privileges
        • MPU TEX Level
        • MPU Instruction Access
        • MPU Shareable Access
        • MPU Cacheable Access
        • MPU Bufferable Access
      • CORTEX Exported Functions
        • SYSTICK
        • LOW POWER MODE
        • HANDLER
        • MCU INFO
        • MPU
    • CRC
      • CRC Exported Constants
        • Polynomial length
        • Input Data Reverse
        • Output Data Reverse
        • Default CRC generating polynomial value
        • Default CRC computation initialization value
      • CRC Exported Macros
        • Common Write and read registers Macros
      • CRC Exported Functions
        • CRC Configuration functions
        • Data_Management
        • Initialization and de-initialization functions
    • DAC
      • DAC Private Constants
      • DAC Private Macros
      • DAC Exported Init structure
      • DAC Exported Constants
        • DAC flags
        • DAC interruptions
        • DAC channels
        • DAC trigger source
        • DAC waveform automatic generation mode
        • DAC wave generation - Noise LFSR unmask bits
        • DAC wave generation - Triangle amplitude
        • DAC channel output buffer
        • DAC channel output resolution
        • DAC registers compliant with specific purpose
        • Definitions of DAC hardware constraints delays
      • DAC Exported Macros
        • Common write and read registers macros
        • DAC helper macro
      • DAC Exported Functions
        • Configuration of DAC channels
        • DMA Management
        • Operation on DAC channels
        • FLAG Management
        • IT management
        • Initialization and de-initialization functions
    • DMA
      • DMA Private Variables
      • DMA Private Macros
      • DMA Exported Init structure
      • DMA Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • CHANNEL
        • Transfer Direction
        • Transfer mode
        • Peripheral increment mode
        • Memory increment mode
        • Peripheral data alignment
        • Memory data alignment
        • Transfer Priority level
      • DMA Exported Macros
        • Common Write and read registers macros
        • Convert DMAxChannely
      • DMA Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
    • EXTI
      • EXTI Private Macros
      • EXTI Exported Init structure
      • EXTI Exported Constants
        • LINE
        • Mode
        • Edge Trigger
      • EXTI Exported Macros
        • Common Write and read registers Macros
      • EXTI Exported Functions
        • IT_Management
        • Event_Management
        • Rising_Trigger_Management
        • Falling_Trigger_Management
        • Software_Interrupt_Management
        • Flag_Management
        • Initialization and de-initialization functions
    • GPIO
      • GPIO Private Macros
      • GPIO Exported Init structures
      • GPIO Exported Constants
        • PIN
        • Mode
        • Output Type
        • Output Speed
        • Pull Up Pull Down
        • Alternate Function
      • GPIO Exported Macros
        • Common Write and read registers Macros
      • GPIO Exported Functions
        • Port Configuration
        • Data Access
        • Initialization and de-initialization functions
    • I2C
      • I2C Private Constants
      • I2C Private Macros
      • I2C Exported Init structure
      • I2C Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • Peripheral Mode
        • Analog Filter Selection
        • Master Addressing Mode
        • Own Address 1 Length
        • Own Address 2 Masks
        • Acknowledge Generation
        • Slave Address Length
        • Transfer Request Direction
        • Transfer End Mode
        • Start And Stop Generation
        • Read Write Direction
        • DMA Register Data
        • SMBus TimeoutA Mode SCL SDA Timeout
        • SMBus Timeout Selection
      • I2C Exported Macros
        • Common Write and read registers Macros
        • Convert SDA SCL timings
      • I2C Exported Functions
        • Configuration
        • IT_Management
        • FLAG_management
        • Data_Management
        • Initialization and de-initialization functions
    • IWDG
      • IWDG Private Constants
      • IWDG Exported Constants
        • Get Flags Defines
        • Prescaler Divider
      • IWDG Exported Macros
        • Common Write and read registers Macros
      • IWDG Exported Functions
        • Configuration
        • FLAG_Management
    • PWR
      • PWR Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • Mode Power
        • Regulator Mode In Deep Sleep Mode
        • Power Voltage Detector Level
        • Wakeup Pins
        • SDADC Analogx
      • PWR Exported Macros
        • Common write and read registers Macros
      • PWR Exported Functions
        • Configuration
        • FLAG_Management
        • De-initialization function
    • RCC
      • RCC Private functions
      • RCC Private Constants
      • RCC Private Macros
      • RCC Exported Types
        • Clocks Frequency Structure
      • RCC Exported Constants
        • Oscillator Values adaptation
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • LSE oscillator drive capability
        • System clock switch
        • System clock switch status
        • AHB prescaler
        • APB low-speed prescaler (APB1)
        • APB high-speed prescaler (APB2)
        • MCO1 SOURCE selection
        • MCO1 prescaler
        • Peripheral clock frequency
        • Peripheral USART clock source selection
        • Peripheral I2C clock source selection
        • Peripheral CEC clock source selection
        • Peripheral USB clock source selection
        • Peripheral ADC clock source selection
        • Peripheral SDADC clock source selection
        • Peripheral USART get clock source
        • Peripheral I2C get clock source
        • Peripheral CEC get clock source
        • Peripheral USB get clock source
        • Peripheral ADC get clock source
        • Peripheral SDADC get clock source
        • RTC clock source selection
        • PLL Multiplicator factor
        • PLL SOURCE
        • PREDIV Division factor
      • RCC Exported Macros
        • Common Write and read registers Macros
        • Calculate frequencies
      • RCC Exported Functions
        • HSE
        • HSI
        • LSE
        • LSI
        • System
        • MCO
        • Peripheral Clock Source
        • RTC
        • PLL
        • FLAG Management
        • IT Management
        • De-initialization function
        • Get system and peripherals clocks frequency functions
      • RCC_LL_Private_Variables
    • RTC
      • RTC Private Constants
      • RTC Private Macros
      • RTC Exported Init structure
      • RTC Exported Constants
        • FORMAT
        • RTC Alarm A Date WeekDay
        • RTC Alarm B Date WeekDay
        • Get Flags Defines
        • IT Defines
        • WEEK DAY
        • MONTH
        • HOUR FORMAT
        • ALARM OUTPUT
        • ALARM OUTPUT TYPE
        • PIN
        • OUTPUT POLARITY PIN
        • TIME FORMAT
        • SHIFT SECOND
        • ALARMA MASK
        • ALARMA TIME FORMAT
        • ALARMB MASK
        • ALARMB TIME FORMAT
        • TIMESTAMP EDGE
        • TIMESTAMP TIME FORMAT
        • TAMPER
        • TAMPER MASK
        • TAMPER NO ERASE
        • TAMPER DURATION
        • TAMPER FILTER
        • TAMPER SAMPLING FREQUENCY DIVIDER
        • TAMPER ACTIVE LEVEL
        • WAKEUP CLOCK DIV
        • BACKUP
        • Calibration output
        • Calibration pulse insertion
        • Calibration period
      • RTC Exported Macros
        • Common Write and read registers Macros
        • Convert helper Macros
        • Date helper Macros
        • Time helper Macros
      • RTC Exported Functions
        • Configuration
        • Time
        • Date
        • ALARMA
        • ALARMB
        • Timestamp
        • Tamper
        • Wakeup
        • Backup_Registers
        • Calibration
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
    • SPI
      • SPI Private Constants
      • SPI Private Macros
      • SPI Exported Init structure
      • SPI Exported Constants
        • Get Flags Defines
        • IT Defines
        • Operation Mode
        • Serial Protocol
        • Clock Phase
        • Clock Polarity
        • Baud Rate Prescaler
        • Transmission Bit Order
        • Transfer Mode
        • Slave Select Pin Mode
        • Datawidth
        • CRC Calculation
        • CRC Length
        • RX FIFO Threshold
        • RX FIFO Level
        • TX FIFO Level
        • DMA Parity
      • SPI Exported Macros
        • Common Write and read registers Macros
      • SPI Exported Functions
        • Configuration
        • CRC Management
        • Slave Select Pin Management
        • FLAG Management
        • Interrupt Management
        • DMA Management
        • DATA Management
        • Initialization and de-initialization functions
    • I2S
      • I2S Private Constants
      • I2S Private Macros
      • I2S Exported Init structure
      • I2S Exported Constants
        • Get Flags Defines
        • IT Defines
        • Data format
        • Clock Polarity
        • I2s Standard
        • Operation Mode
        • Prescaler Factor
        • MCLK Output
        • Audio Frequency
      • I2S Exported Macros
        • Common Write and read registers Macros
      • I2S Exported Functions
        • Configuration
        • FLAG Management
        • Interrupt Management
        • DMA Management
        • DATA Management
        • Initialization and de-initialization functions
    • SYSTEM
      • SYSTEM Private Constants
      • SYSTEM Exported Constants
        • SYSCFG REMAP
        • SYSCFG DAC1/2 DMA1/2 request REMAP
        • SYSCFG TIM DMA request REMAP
        • SYSCFG I2C FASTMODEPLUS
        • SYSCFG EXTI PORT
        • SYSCFG EXTI LINE
        • SYSCFG TIMER BREAK
        • DBGMCU TRACE Pin Assignment
        • DBGMCU APB1 GRP1 STOP IP
        • DBGMCU APB2 GRP1 STOP IP
        • FLASH LATENCY
      • SYSTEM Exported Functions
        • SYSCFG
        • DBGMCU
        • FLASH
    • TIM
      • TIM Private Functions
      • TIM Private Variables
      • TIM Private Constants
      • TIM Private Macros
      • TIM Exported Init structure
      • TIM Exported Constants
        • Get Flags Defines
        • Break Enable
        • Automatic output enable
        • IT Defines
        • Update Source
        • One Pulse Mode
        • Counter Mode
        • Clock Division
        • Counter Direction
        • Capture Compare Update Source
        • Capture Compare DMA Request
        • Lock Level
        • Channel
        • Output Configuration State
        • Output Configuration Mode
        • Output Configuration Polarity
        • Output Configuration Idle State
        • Active Input Selection
        • Input Configuration Prescaler
        • Input Configuration Filter
        • Input Configuration Polarity
        • Clock Source
        • Encoder Mode
        • Trigger Output
        • Slave Mode
        • Trigger Selection
        • External Trigger Polarity
        • External Trigger Prescaler
        • External Trigger Filter
        • break polarity
        • OSSI
        • OSSR
        • DMA Burst Base Address
        • DMA Burst Length
        • TIM16 External Input Ch1 Remap
        • TIM14 Timer Input1 Remap
      • TIM Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros
      • TIM Exported Functions
        • Time Base configuration
        • Capture Compare configuration
        • Output channel configuration
        • Input channel configuration
        • Counter clock selection
        • Timer synchronisation configuration
        • Break function configuration
        • DMA burst mode configuration
        • Timer input remapping
        • FLAG-Management
        • IT-Management
        • DMA-Management
        • EVENT-Management
        • Initialisation and deinitialisation functions
    • USART
      • USART Private Constants
      • USART Private Macros
      • USART Exported Init structures
      • USART Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • Communication Direction
        • Parity Control
        • Wakeup
        • Datawidth
        • Oversampling
        • Clock Signal
        • Last Clock Pulse
        • Clock Phase
        • Clock Polarity
        • Stop Bits
        • TX RX Pins Swap
        • RX Pin Active Level Inversion
        • TX Pin Active Level Inversion
        • Binary Data Inversion
        • Bit Order
        • Autobaud Detection
        • Address Length Detection
        • Hardware Control
        • Wakeup Activation
        • IrDA Power
        • LIN Break Detection Length
        • Driver Enable Polarity
        • DMA Register Data
      • USART Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros_Helper
      • USART Exported Functions
        • Configuration functions
        • Configuration functions related to Irda feature
        • Configuration functions related to Smartcard feature
        • Configuration functions related to Half Duplex feature
        • Configuration functions related to LIN feature
        • Configuration functions related to Driver Enable feature
        • Advanced Configurations services
        • FLAG_Management
        • IT_Management
        • DMA_Management
        • Data_Management
        • Execution
        • Initialization and de-initialization functions
    • UTILS
      • UTILS Private functions
      • UTILS Private Constants
      • UTILS Private Macros
      • UTILS Exported structures
      • UTILS Exported Constants
        • HSE Bypass activation
      • UTILS Exported Functions
        • DEVICE ELECTRONIC SIGNATURE
        • DELAY
        • SYSTEM
    • WWDG
      • WWDG Exported Constants
        • IT Defines
        • PRESCALER
      • WWDG Exported Macros
        • Common Write and read registers macros
      • WWDG Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
  • STM32F3xx_HAL_Driver
    • HAL
      • Constants
      • HAL Private Variables
      • HAL Exported Functions
        • Initialization and de-initialization Functions
        • HAL Control functions
      • HAL Exported Constants
        • SYSCFG registers bit address in the alias region
        • HAL DMA Remapping
        • HAL Trigger Remapping
        • Fast-mode Plus on GPIO
        • HAL SYSCFG Interrupts
      • HAL Exported Macros
        • Freeze/Unfreeze APB1 Peripherals in Debug mode
        • Freeze/Unfreeze APB2 Peripherals in Debug mode
        • Memory Mapping Selection
        • Encoder Mode
        • DMA Remap Enable
        • Fast-mode Plus on GPIO
        • Floating Point Unit Interrupts Enable
        • VBAT Monitoring Enable
        • Cortex Lockup Enable
        • PVD Lock
        • SRAM Parity Lock
        • Trigger Remapping Enable
      • HAL_Private_Macros
    • ADC
      • ADC Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • ADC Exported Types
      • ADC Exported Macros
    • ADCEx
      • ADCEx Private Constants
        • ADC Extended Internal HAL driver trigger selection for regular group
        • ADC Extended Internal HAL driver trigger selection for injected group
        • ADC Extended Sampling Times All Channels
      • ADCEx Exported Functions
        • ADCEx Initialization and de-initialization functions
        • ADCEx Input and Output operation functions
        • ADCEx Peripheral Control functions
      • ADCEx Private Functions
      • ADCEx Exported Types
      • ADCEx Exported Constants
        • ADC Extended Error Code
        • ADC Extended Data Alignment
        • ADC Extended Scan Mode
        • ADC Extended External trigger enable for regular group
        • ADC Extended External trigger selection for regular group
        • ADC Extended Channels
        • ADC Extended Sampling Times
        • ADC Extended rank into regular group
        • ADC Extended Injected Channel Rank
        • External Trigger Edge of Injected Group
        • External Trigger Source of Injected Group
        • ADC Extended analog watchdog mode
        • ADC Conversion Group
        • ADC Extended Event Type
        • ADC Extended Interrupts Definition
        • ADC Extended Flags Definition
      • ADCEx Exported Macros
      • ADCEx Private Macros
        • ADC Extended Range Verification
        • ADC Injected Conversion Number Verification
        • ADC Regular Conversion Number Verification
        • ADC Regular Discontinuous Mode NumberVerification
    • CAN
      • CAN Private Constants
      • CAN Private Functions
      • CAN Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral State and Error functions
      • CAN Exported Types
      • CAN Exported Constants
        • CAN Error Code
        • CAN InitStatus
        • CAN Operating Mode
        • CAN Synchronization Jump Width
        • CAN Time Quantum in Bit Segment 1
        • CAN Time Quantum in Bit Segment 2
        • CAN Filter Mode
        • CAN Filter Scale
        • CAN Filter FIFO
        • CAN Identifier Type
        • CAN Remote Transmission Request
        • CAN Receive FIFO Number
        • CAN Flags
        • CAN Interrupts
        • CAN Mailboxes
      • CAN Exported Macros
      • CAN Private Types
      • CAN Private Variables
      • CAN Private Macros
    • CEC
      • CEC Private Constants
      • CEC Private Functions
      • CEC Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control function
      • CEC Exported Types
      • CEC Exported Constants
        • CEC Error Code
        • CEC Signal Free Time setting parameter
        • CEC Receiver Tolerance
        • CEC Reception Stop on Error
        • CEC Error Bit Generation if Bit Rise Error reported
        • CEC Error Bit Generation if Long Bit Period Error reported
        • CEC Error Bit Generation on Broadcast message
        • CEC Signal Free Time start option
        • CEC Listening mode option
        • CEC Device Own Address position in CEC CFGR register
        • CEC Initiator logical address position in message header
        • CEC Own Address
        • CEC Interrupts definition
        • CEC Flags definition
        • CEC all RX or TX errors flags
        • CEC all RX errors interrupts enabling flag
        • CEC all TX errors interrupts enabling flag
      • CEC Exported Macros
      • CEC Private Types
      • CEC Private Variables
      • CEC Private Macros
    • COMP
      • COMP Private Constants
      • COMP Exported Functions
        • Initialization/de-initialization functions
        • Start Stop operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • COMP Exported Types
      • COMP Exported Constants
        • COMP Output Polarity
        • COMP Output Level
        • COMP Trigger Mode
        • COMP State Lock
      • COMP Exported Macros
      • COMP Private Macros
        • COMP Private macros to check input parameters
    • COMPEx
      • COMP Extended Exported Constants
        • COMP Extended InvertingInput (STM32F373xC/STM32F378xx Product devices)
        • COMP Extended NonInvertingInput (STM32F373xC/STM32F378xx Product devices)
        • COMP Extended Output (STM32F373xC/STM32F378xx Product devices)
        • COMP Extended WindowMode (STM32F373xC/STM32F378xx Product devices)
        • COMP Extended Mode
        • COMP Extended Hysteresis
        • COMP Extended Blanking Source (STM32F373xC/STM32F378xx Product devices)
        • COMP Flag
      • COMP Extended Exported Macros
      • COMP Extended Private Constants
        • COMP Extended EXTI lines
        • COMP Extended miscellaneous defines
      • COMP Extended Private Macros
        • COMP Extended Private macro to get the EXTI line associated with a comparator handle
        • COMP Extended miscellaneous private macros
        • COMP Extended Private macros to check input parameters
    • CORTEX
      • CORTEX Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • CORTEX Exported Types
        • MPU Region Initialization Structure Definition
      • CORTEX Exported Constants
        • CORTEX Preemption Priority Group
        • CORTEX SysTick clock source
        • MPU HFNMI and PRIVILEGED Access control
        • CORTEX MPU Region Enable
        • CORTEX MPU Instruction Access
        • CORTEX MPU Instruction Access Shareable
        • CORTEX MPU Instruction Access Cacheable
        • CORTEX MPU Instruction Access Bufferable
        • MPU TEX Levels
        • CORTEX MPU Region Size
        • CORTEX MPU Region Permission Attributes
        • CORTEX MPU Region Number
      • CORTEX Private Macros
        • CORTEX SysTick clock source
      • CORTEX Private Functions
    • CRC
      • CRC Private Functions
      • CRC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
        • Peripheral State functions
      • CRC Exported Types
      • CRC Exported Constants
        • Default CRC generating polynomial
        • Default CRC computation initialization value
        • Indicates whether or not default polynomial is used
        • Indicates whether or not default init value is used
        • Polynomial sizes to configure the IP
        • CRC polynomial possible sizes actual definitions
        • Input Buffer Format
      • CRC Exported Macros
      • CRC aliases for Exported Functions
      • CRC Private Macros
    • CRCEx
      • CRC Extended Exported Functions
        • CRC Extended Initialization and de-initialization functions
      • CRC Extended Exported Constants
        • CRC Extended Input Data Inversion Modes
        • CRC Extended Output Data Inversion Modes
      • CRC Extended Exported Macros
      • CRCEx Private Macros
    • DAC
      • DAC Private Macros
      • DAC Private Functions
      • DAC Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State and Error functions
      • DAC Exported Types
      • DAC Exported Constants
        • DAC Error Code
        • DAC lfsrunmask triangleamplitude
        • DAC output buffer
        • DAC data alignement
        • DAC flags definition
        • DAC interrupts definition
      • DAC Exported Macros
    • DACEx
      • DACEx Private Functions
      • DACEx Exported Functions
        • DACEx Peripheral Control functions
        • DACEx Input and Output operation functions
      • DACEx Exported Constants
        • DACEx trigger selection
        • DACEx Channel selection
      • DACEx Private Macros
    • DMA
      • DMA Private Functions
      • DMA Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral State functions
      • DMA Exported Types
      • DMA Exported Constants
        • DMA Error Code
        • DMA Data transfer direction
        • DMA Peripheral incremented mode
        • DMA Memory incremented mode
        • DMA Peripheral data size
        • DMA Memory data size
        • DMA mode
        • DMA Priority level
        • DMA interrupt enable definitions
        • DMA flag definitions
      • DMA Exported Macros
      • DMA Private Macros
    • FLASH
      • FLASH Private Constants
      • FLASH Private Macros
      • FLASH Private Variables
      • FLASH Private Functions
      • FLASH Exported Functions
        • Programming operation functions
        • Peripheral Control functions
        • Peripheral errors functions
      • FLASH Exported Types
      • FLASH Exported Constants
        • FLASH Error Codes
        • FLASH Type Program
        • FLASH Latency
        • FLASH Flag definition
        • FLASH Interrupt definition
      • FLASH Exported Macros
        • FLASH Half Cycle
        • FLASH Latency
        • FLASH Prefetch
        • FLASH Interrupts
    • FLASHEx
      • FLASHEx Private Constants
      • FLASHEx Private Macros
      • FLASHEx Private Functions
      • FLASHEx Exported Functions
        • FLASHEx Memory Erasing functions
        • Option Bytes Programming functions
      • FLASHEx Exported Types
      • FLASHEx Exported Constants
        • FLASHEx Page Size
        • FLASH Type Erase
        • Option Byte Constants
          • Option Bytes Type
          • Option Byte WRP State
          • FLASHEx OB Write Protection
          • Option Byte Read Protection
          • Option Byte IWatchdog
          • Option Byte nRST STOP
          • Option Byte nRST STDBY
          • Option Byte BOOT1
          • Option Byte VDDA Analog Monitoring
          • Option Byte SRAM Parity Check Enable
          • OB SDADC12 VDD MONITOR
          • Option Byte Data Address
    • GPIO
      • GPIO Private Defines
      • GPIO Private Macros
      • GPIO Exported Functions
        • Initialization/de-initialization functions
        • IO operation functions
      • GPIO Exported Types
      • GPIO Exported Constants
        • GPIO pins
        • GPIO mode
        • GPIO speed
        • GPIO pull
      • GPIO Exported Macros
    • GPIOEx
      • GPIOEx Exported Constants
        • GPIOEx Alternate function selection
      • GPIOEx Exported Macros
        • GPIOEx_Get Port Index
    • I2C
      • I2C Private Define
      • I2C Private Functions
      • I2C Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • IRQ Handler and Callbacks
        • Peripheral State, Mode and Error functions
      • I2C Exported Types
        • I2C Configuration Structure definition
        • HAL state structure definition
        • HAL mode structure definition
        • I2C Error Code definition
        • I2C handle Structure definition
      • I2C Exported Constants
        • I2C Sequential Transfer Options
        • I2C Addressing Mode
        • I2C Dual Addressing Mode
        • I2C Own Address2 Masks
        • I2C General Call Addressing Mode
        • I2C No-Stretch Mode
        • I2C Memory Address Size
        • I2C Transfer Direction Master Point of View
        • I2C Reload End Mode
        • I2C Start or Stop Mode
        • I2C Interrupt configuration definition
        • I2C Flag definition
      • I2C Exported Macros
      • I2C Private Constants
      • I2C Private Macros
    • I2CEx
      • I2C Extended Exported Functions
        • Extended features functions
          • I2C Extended Private Constants
          • I2C Extended Private Macros
          • I2C Extended Private Functions
      • I2C Extended Exported Constants
        • I2C Extended Analog Filter
        • I2C Extended Fast Mode Plus
    • I2S
      • I2S Private Functions
      • I2S Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • I2S Exported Types
      • I2S Exported Constants
        • I2S Error
        • I2S Clock Source
        • I2S Mode
        • I2S Standard
        • I2S Data Format
        • I2S MCLK Output
        • I2S Audio Frequency
        • I2S Full Duplex Mode
        • I2S Clock Polarity
        • I2S Interrupt configuration definition
        • I2S Flag definition
      • I2S Exported Macros
    • I2SEx
      • I2S Extended Exported Macros
      • I2S
        • I2S Private Functions
        • I2S Exported Functions
          • Initialization and de-initialization functions
          • IO operation functions
          • Peripheral State and Errors functions
        • I2S Exported Types
        • I2S Exported Constants
          • I2S Error
          • I2S Clock Source
          • I2S Mode
          • I2S Standard
          • I2S Data Format
          • I2S MCLK Output
          • I2S Audio Frequency
          • I2S Full Duplex Mode
          • I2S Clock Polarity
          • I2S Interrupt configuration definition
          • I2S Flag definition
        • I2S Exported Macros
      • I2S Extended Exported Functions
    • IRDA
      • IRDA Private Constants
      • IRDA Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Error functions
      • IRDA Private Functions
      • IRDA Exported Types
      • IRDA Exported Constants
        • IRDA Error
        • IRDA Parity
        • IRDA Transfer Mode
        • IRDA Low Power
        • IRDA State
        • IRDA Mode
        • IRDA One Bit Sampling
        • IRDA DMA Tx
        • IRDA DMA Rx
        • IRDA Request Parameters
        • IRDA Flags
        • IRDA Interrupts Definition
        • IRDA Interruption Clear Flags
        • IRDA interruptions flags mask
      • IRDA Exported Macros
      • IRDA Private Macros
    • IWDG
      • IWDG Private Defines
      • IWDG Exported Types
      • IWDG Exported Constants
        • IWDG Prescaler
        • IWDG Window option
      • IWDG Exported Macros
      • IWDG Exported Functions
        • Initialization and Start functions
        • IO operation functions
      • IWDG Private Constants
      • IWDG Private Macros
    • PCD
      • PCD Private Define
      • PCD Private Functions
      • PCD Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • PCD Exported Types
      • PCD Exported Constants
        • PCD Core Speed
        • PCD Core PHY
      • PCD Exported Macros
      • PCD Private Constants
        • USB EXTI line interrupt
        • PCD EP0 MPS
        • PCD EP Type
        • PCD ENDP
        • PCD Endpoint Kind
      • PCD Instance definition
      • PCD Private Macros
      • Peripheral Control functions
      • Peripheral State functions
      • PCD Extended Private Functions
    • PCDEx
      • PCDEx Exported Functions
        • Peripheral Control functions
        • Extended Initialization and de-initialization functions
      • PCD Extended Private Functions
      • PCD Extended Exported Macros
    • PWREx
      • PWR Extended Private Constants
      • PWR Extended Exported Functions
        • Peripheral Extended Control Functions
      • PWR Extended Exported Types
      • PWR Extended Exported Constants
        • PWR Extended PVD detection level
        • PWR Extended PVD Mode
        • PWR Extended SDADC ANALOGx
      • PWR Extended Exported Macros
      • PWR Extended Private Macros
    • RCC
      • RCC Private Constants
        • RCC Timeout
        • Register offsets
        • BitAddress AliasRegion
      • RCC Private Macros
      • RCC Private Variables
      • RCC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • RCC Exported Types
      • RCC Exported Constants
        • PLL Clock Source
        • Oscillator Type
        • HSE Config
        • LSE Config
        • HSI Config
        • LSI Config
        • PLL Config
        • System Clock Type
        • System Clock Source
        • System Clock Source Status
        • AHB Clock Source
        • APB1 APB2 Clock Source
        • RTC Clock Source
        • RCC PLL Multiplication Factor
        • RCC PLL HSE Prediv Factor
        • RCC USART2 Clock Source
        • RCC USART3 Clock Source
        • RCC I2C1 Clock Source
        • MCO Index
        • Interrupts
        • Flags
      • RCC Exported Macros
        • RCC AHB Clock Enable Disable
        • RCC APB1 Clock Enable Disable
        • RCC APB2 Clock Enable Disable
        • AHB Peripheral Clock Enable Disable Status
        • APB1 Peripheral Clock Enable Disable Status
        • APB2 Peripheral Clock Enable Disable Status
        • RCC AHB Force Release Reset
        • RCC APB1 Force Release Reset
        • RCC APB2 Force Release Reset
        • HSI Configuration
        • LSI Configuration
        • HSE Configuration
        • LSE Configuration
        • RCC USARTx Clock Config
        • RCC I2Cx Clock Config
        • PLL Configuration
        • Get Clock source
        • RCC Extended MCOx Clock Config
        • RCC RTC Clock Configuration
        • Flags Interrupts Management
    • RCCEx
      • RCCEx Private Macros
      • RCCEx Private Functions
      • RCCEx Exported Functions
        • Extended Peripheral Control functions
      • RCCEx Exported Types
      • RCC Extended Exported Constants
        • RCC Extended MCO Clock Source
        • RCC Extended Periph Clock Selection
        • RCC Extended USART1 Clock Source
        • RCC Extended I2C2 Clock Source
        • RCC Extended ADC1 Clock Source
        • RCC Extended CEC Clock Source
        • RCC Extended SDADC Clock Prescaler
        • RCC Extended USB Clock Source
        • RCC Extended MCOx Clock Prescaler
        • RCC LSE Drive Configuration
      • RCC Extended Exported Macros
        • RCC Extended PLL Configuration
        • RCC Extended HSE Configuration
        • RCC Extended AHB Clock Enable Disable
        • RCC Extended APB1 Clock Enable Disable
        • RCC Extended APB2 Clock Enable Disable
        • RCC Extended AHB Peripheral Clock Enable Disable Status
        • RCC Extended APB1 Peripheral Clock Enable Disable Status
        • RCC Extended APB2 Peripheral Clock Enable Disable Status
        • RCC Extended AHB Force Release Reset
        • RCC Extended APB1 Force Release Reset
        • RCC Extended APB2 Force Release Reset
        • RCC Extended I2Cx Clock Config
        • RCC Extended ADCx Clock Config
        • RCC Extended SDADCx Clock Config
        • RCC Extended CECx Clock Config
        • RCC Extended USBx Clock Config
        • LSE Drive Configuration
    • RTC
      • RTC Exported Types
      • RTC Exported Constants
        • RTC Hour Formats
        • RTC Output Polarity Definitions
        • RTC Output Type ALARM OUT
        • RTC AM PM Definitions
        • RTC DayLightSaving Definitions
        • RTC StoreOperation Definitions
        • RTC Input parameter format definitions
        • RTC Month Date Definitions
        • RTC WeekDay Definitions
        • RTC AlarmDateWeekDay Definitions
        • RTC AlarmMask Definitions
        • RTC Alarms Definitions
        • RTC Alarm Sub Seconds Masks Definitions
        • RTC Interrupts Definitions
        • RTC Flags Definitions
      • RTC Exported Macros
      • RTC Exported Functions
        • Initialization and de-initialization functions
        • RTC Time and Date functions
        • RTC Alarm functions
        • Peripheral Control functions
        • Peripheral State functions
      • RTC Private Constants
      • RTC Private Macros
        • RTC Private macros to check input parameters
      • RTC Private Functions
    • RTCEx
      • RTC Extended Exported Types
      • RTC Extended Exported Constants
        • RTC Extended Output Selection Definition
        • RTC Extended Backup Registers Definition
        • RTC Extended Time Stamp Edges definition
        • RTC Extended TimeStamp Pin Selection
        • RTC Extended Tamper Pins Definition
        • RTC Extended Tamper Trigger Definition
        • RTC Extended Tamper Filter Definition
        • RTC Extended Tamper Sampling Frequencies Definition
        • RTC Extended Tamper Pin Precharge Duration Definition
        • RTC Extended Tamper TimeStampOnTamperDetection Definition
        • RTC Extended Tamper Pull UP Definition
        • RTC Extended Wakeup Timer Definition
        • RTC Extended Smooth calib period Definition
        • RTC Extended Smooth calib Plus pulses Definition
        • RTC Extended Calib Output selection Definition
        • RTC Extended Add 1 Second Parameter Definition
      • RTC Extended Exported Macros
        • RTC Extended WakeUp Timer
        • RTC Extended Timestamp
        • RTC Extended Tamper
        • EXTI RTC Extended Tamper Timestamp EXTI
        • RTC Extended Calibration
      • RTCEx Exported Functions
        • Extended RTC TimeStamp and Tamper functions
        • Extended RTC Wake-up functions
        • Extended Peripheral Control functions
        • Extended features functions
      • RTCEx Private Macros
        • Private macros to check input parameters
    • SDADC
      • SDADC Private Define
      • SDADC Private Functions
      • SDADC Exported Functions
        • Initialization and de-initialization functions
        • peripheral control functions
        • Input and Output operation functions
        • Peripheral State functions
        • SDADC Private Functions
      • SDADC Exported Types
      • SDADC Exported Constants
        • SDADC Idle Low Power Mode
        • SDADC Fast Conversion Mode
        • SDADC Slow Clock Mode
        • SDADC Reference Voltage
        • SDADC Configuration Index
        • SDADC Input Mode
        • SDADC Gain
        • SDADC Common Mode
        • SDADC Channel Selection
        • SDADC Calibration Sequence
        • SDADC Continuous Mode
        • SDADC Trigger
        • SDADC Injected External Trigger
        • SDADC External Trigger Edge
        • SDADC Injected Conversion Delay
        • SDADC Multimode Type
        • SDADC Error Code
        • SDADC interrupts definition
        • SDADC flags definition
      • SDADC Exported Macros
      • SDADC Private Macros
    • SMARTCARD
      • SMARTCARD Private Constants
      • SMARTCARD Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SMARTCARD Private Functions
      • SMARTCARD Exported Types
      • SMARTCARD Exported Constants
        • SMARTCARD Error
        • SMARTCARD Word Length
        • SMARTCARD Number of Stop Bits
        • SMARTCARD Parity
        • SMARTCARD Transfer Mode
        • SMARTCARD Clock Polarity
        • SMARTCARD Clock Phase
        • SMARTCARD Last Bit
        • SMARTCARD One Bit Sampling Method
        • SMARTCARD NACK Enable
        • SMARTCARD Timeout Enable
        • SMARTCARD advanced feature initialization type
        • SMARTCARD advanced feature TX pin active level inversion
        • SMARTCARD advanced feature RX pin active level inversion
        • SMARTCARD advanced feature Binary Data inversion
        • SMARTCARD advanced feature RX TX pins swap
        • SMARTCARD advanced feature Overrun Disable
        • SMARTCARD advanced feature DMA Disable on Rx Error
        • SMARTCARD advanced feature MSB first
        • SMARTCARD Flags
        • SMARTCARD Interrupts Definition
        • SMARTCARD Interruption Clear Flags
        • SMARTCARD auto retry counter LSB position in CR3 register
        • SMARTCARD guard time value LSB position in GTPR register
        • SMARTCARD block length LSB position in RTOR register
        • SMARTCARD interruptions flags mask
        • SMARTCARD Request Parameters
      • SMARTCARD Exported Macros
      • SMARTCARD Private Macros
    • SMARTCARDEx
      • SMARTCARD Extended Exported Functions
        • Extended Peripheral Control functions
      • SMARTCARD Extended Private Macros
    • SMBUS
      • SMBUS Private Constants
      • SMBUS Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
          • Blocking mode Polling
          • Non-Blocking mode Interrupt
          • IRQ Handler and Callbacks
          • Peripheral State and Errors functions
        • IRQ Handler and Callbacks
        • Peripheral State and Errors functions
        • SMBUS Private Functions
      • SMBUS Exported Types
        • SMBUS Configuration Structure definition
        • HAL state definition
        • SMBUS Error Code definition
        • SMBUS handle Structure definition
      • SMBUS Exported Constants
        • SMBUS Analog Filter
        • SMBUS addressing mode
        • SMBUS dual addressing mode
        • SMBUS ownaddress2 masks
        • SMBUS general call addressing mode
        • SMBUS nostretch mode
        • SMBUS packet error check mode
        • SMBUS peripheral mode
        • SMBUS ReloadEndMode definition
        • SMBUS StartStopMode definition
        • SMBUS XferOptions definition
        • SMBUS Interrupt configuration definition
        • SMBUS Flag definition
      • SMBUS Exported Macros
      • SMBUS Private Macros
      • SMBUS Private Functions
    • SPI
      • SPI Private Constants
      • SPI Private Functions
      • SPI Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SPI Exported Types
      • SPI Exported Constants
        • SPI Error Code
        • SPI Mode
        • SPI Direction Mode
        • SPI Data Size
        • SPI Clock Polarity
        • SPI Clock Phase
        • SPI Slave Select Management
        • SPI NSS Pulse Mode
        • SPI BaudRate Prescaler
        • SPI MSB LSB Transmission
        • SPI TI Mode
        • SPI CRC Calculation
        • SPI CRC Length
        • SPI FIFO Reception Threshold
        • SPI Interrupt Definition
        • SPI Flags Definition
        • SPI Transmission FIFO Status Level
        • SPI Reception FIFO Status Level
      • SPI Exported Macros
      • SPI Private Macros
    • SPIEx
      • SPIEx Private Constants
      • SPIEx Exported Functions
        • IO operation functions
    • TIM
      • TIM Private Functions
      • TIM Exported Functions
        • Time Base functions
        • Time Output Compare functions
        • Time PWM functions
        • Time Input Capture functions
        • Time One Pulse functions
        • Time Encoder functions
        • TIM IRQ handler management
        • Peripheral Control functions
        • TIM Callbacks functions
        • Peripheral State functions
      • TIM Exported Types
      • TIM Exported Constants
        • TIM Input Channel Polarity
        • TIM ETR Polarity
        • TIM ETR Prescaler
        • TIM Counter Mode
        • TIM Clock Division
        • TIM Auto-Reload Preload
        • TIM Output Fast State
        • TIM Output Compare Polarity
        • TIM Complementary Output Compare Polarity
        • TIM Output Compare Idle State
        • TIM Complementary Output Compare Idle State
        • TIM Input Capture Polarity
        • TIM Input Capture Selection
        • TIM Input Capture Prescaler
        • TIM One Pulse Mode
        • TIM Encoder Mode
        • TIM Interrupt Definition
        • TIM Commutation Source
        • TIM DMA Sources
        • TIM Flag Definition
        • TIM Clock Source
        • TIM Clock Polarity
        • TIM Clock Prescaler
        • TIM Clear Input Polarity
        • TIM Clear Input Prescaler
        • TIM OSSR Off State Selection for Run mode state
        • TIM OSSI Off State Selection for Idle mode state
        • TIM Lock level
        • TIM Break Input Enable Disable
        • TIM Break Input Polarity
        • TIM Automatic Output Enable
        • TIM Master Mode Selection
        • TIM Master Slave Mode
        • TIM Trigger Selection
        • TIM Trigger Polarity
        • TIM Trigger Prescaler
        • TIM TI1 Input Selection
        • TIM DMA Burst Length
        • TIM DMA Handle Index
        • TIM Capture/Compare Channel State
      • TIM Exported Macros
      • TIM Private Constants
      • TIM Private Macros
    • TIMEx
      • TIMEx Private Functions
      • TIMEx Exported Functions
        • Timer Hall Sensor functions
        • Timer Complementary Output Compare functions
        • Timer Complementary PWM functions
        • Timer Complementary One Pulse functions
        • Peripheral Control functions
        • Extension Callbacks functions
        • Extended Peripheral State functions
      • TIMEx Exported Types
      • TIMEx Exported Constants
        • TIMEx Channel
        • TIMEx Output Compare and PWM Modes
        • TIMEx Clear Input Source
        • TIMEx Slave Mode
        • TIMEx Event Source
        • TIMEx DMA BAse Address
        • TIMEx remapping
      • TIM Private Macros
      • TIMEx Exported Macros
    • TSC
      • Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
        • IRQ Handler and Callbacks
      • Private Functions
      • TSC Exported Types
      • TSC Exported Constants
        • CTPulse High Length
        • CTPulse Low Length
        • Spread Spectrum Prescaler
        • Pulse Generator Prescaler
        • Max Count Value
        • IO Default Mode
        • Synchro Pin Polarity
        • Acquisition Mode
        • IO Mode
        • Interrupts definition
        • Flags definition
        • Group definition
      • TSC Exported Macros
      • TSC Private Macros
    • UART
      • UART Private Constants
      • UART Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Error functions
      • UART Private Functions
      • UART Exported Types
      • UART Exported Constants
        • UART Error
        • UART Number of Stop Bits
        • UART Parity
        • UART Hardware Flow Control
        • UART Transfer Mode
        • UART State
        • UART Over Sampling
        • UART One Bit Sampling Method
        • UART Advanced Feature AutoBaud Rate Mode
        • UART Receiver TimeOut
        • UART Local Interconnection Network mode
        • UART LIN Break Detection
        • UART DMA Tx
        • UART DMA Rx
        • UART Half Duplex Selection
        • UART WakeUp Address Length
        • UART WakeUp Methods
        • UART Status Flags
        • UART Interrupts Definition
        • UART Interruption Clear Flags
        • UART Request Parameters
        • UART Advanced Feature Initialization Type
        • UART Advanced Feature TX Pin Active Level Inversion
        • UART Advanced Feature RX Pin Active Level Inversion
        • UART Advanced Feature Binary Data Inversion
        • UART Advanced Feature RX TX Pins Swap
        • UART Advanced Feature Overrun Disable
        • UART Advanced Feature Auto BaudRate Enable
        • UART Advanced Feature DMA Disable On Rx Error
        • UART Advanced Feature MSB First
        • UART Advanced Feature Stop Mode Enable
        • UART Advanced Feature Mute Mode Enable
        • UART Address-matching LSB Position In CR2 Register
        • UART WakeUp From Stop Selection
        • UART DriverEnable Polarity
        • UART Driver Enable Assertion Time LSB Position In CR1 Register
        • UART Driver Enable DeAssertion Time LSB Position In CR1 Register
        • UART Interruptions Flag Mask
        • UART polling-based communications time-out value
      • UART Exported Macros
      • UART Private Macros
    • UARTEx
      • UARTEx Exported Functions
        • Extended Initialization and de-initialization functions
        • Extended IO operation function
        • Extended Peripheral Control functions
      • UARTEx Exported Constants
        • UARTEx Word Length
      • UARTEx Private Macros
    • USART
      • USART Private Constants
      • USART Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Error functions
      • USART Private Functions
      • USART Exported Types
      • USART Exported Constants
        • USART Error
        • USART Number of Stop Bits
        • USART Parity
        • USART Mode
        • USART Clock
        • USART Clock Polarity
        • USART Clock Phase
        • USART Last Bit
        • USART Request Parameters
        • USART Flags
        • USART Interrupts Definition
        • USART Interruption Clear Flags
        • USART Interruption Flags Mask
      • USART Exported Macros
      • USART Private Macros
    • WWDG
      • WWDG Exported Functions
        • Initialization and Configuration functions
        • IO operation functions
      • WWDG Exported Types
      • WWDG Exported Constants
        • WWDG Interrupt definition
        • WWDG Flag definition
        • WWDG Prescaler
        • WWDG Early Wakeup Interrupt Mode
      • WWDG Private Macros
      • WWDG Exported Macros
    • DACEx Private Functions
    • DMAEx
      • DMA Extended Exported Macros
    • IRDAEx
      • IRDAEx Exported Constants
        • IRDA Word Length
      • IRDAEx Private Macros
    • PWR
      • PWR Exported Constants
        • PWR WakeUp Pins
        • PWR Regulator state in STOP mode
        • PWR SLEEP mode entry
        • PWR STOP mode entry
        • PWR Flag
      • PWR Exported Macro
      • PWR Private Macros
      • PWR Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
    • USARTEx
      • USARTEx Exported Constants
        • USARTEx Word Length
      • USARTEx Private Macros
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STM32F373xC HAL User Manual: PWR_rmtollPages.txt File Reference

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PWR_rmtollPages.txt File Reference
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STM32F373xC HAL User Manual: RCC_rmtollPages.txt File Reference

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RCC_rmtollPages.txt File Reference
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STM32F373xC HAL User Manual: RTC_rmtollPages.txt File Reference

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RTC_rmtollPages.txt File Reference
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STM32F373xC HAL User Manual: SPI_rmtollPages.txt File Reference

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SPI_rmtollPages.txt File Reference
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STM32F373xC HAL User Manual: stm32f3xx_hal.c Source File

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  • Drivers
  • STM32F3xx_HAL_Driver
  • Src
stm32f3xx_hal.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal.c
00004   * @author  MCD Application Team
00005   * @brief   HAL module driver.
00006   *          This is the common part of the HAL initialization
00007   *
00008   @verbatim
00009   ==============================================================================
00010                      ##### How to use this driver #####
00011   ==============================================================================
00012     [..]
00013     The common HAL driver contains a set of generic and common APIs that can be
00014     used by the PPP peripheral drivers and the user to start using the HAL.
00015     [..]
00016     The HAL contains two APIs categories:
00017          (+) HAL Initialization and de-initialization functions
00018          (+) HAL Control functions
00019
00020   @endverbatim
00021   ******************************************************************************
00022   * @attention
00023   *
00024   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00025   *
00026   * Redistribution and use in source and binary forms, with or without modification,
00027   * are permitted provided that the following conditions are met:
00028   *   1. Redistributions of source code must retain the above copyright notice,
00029   *      this list of conditions and the following disclaimer.
00030   *   2. Redistributions in binary form must reproduce the above copyright notice,
00031   *      this list of conditions and the following disclaimer in the documentation
00032   *      and/or other materials provided with the distribution.
00033   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00034   *      may be used to endorse or promote products derived from this software
00035   *      without specific prior written permission.
00036   *
00037   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00038   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00039   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00040   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00041   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00042   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00043   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00044   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00045   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00046   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00047   *
00048   ******************************************************************************
00049   */
00050
00051 /* Includes ------------------------------------------------------------------*/
00052 #include "stm32f3xx_hal.h"
00053
00054 /** @addtogroup STM32F3xx_HAL_Driver
00055   * @{
00056   */
00057
00058 /** @defgroup HAL HAL
00059   * @brief HAL module driver.
00060   * @{
00061   */
00062
00063 #ifdef HAL_MODULE_ENABLED
00064
00065 /* Private typedef -----------------------------------------------------------*/
00066 /* Private define ------------------------------------------------------------*/
00067 /** @defgroup HAL_Private Constants
00068   * @{
00069   */
00070 /**
00071  * @brief STM32F3xx HAL Driver version number V1.5.0
00072    */
00073 #define __STM32F3xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
00074 #define __STM32F3xx_HAL_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
00075 #define __STM32F3xx_HAL_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
00076 #define __STM32F3xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
00077 #define __STM32F3xx_HAL_VERSION         ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\
00078                                         |(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\
00079                                         |(__STM32F3xx_HAL_VERSION_SUB2 << 8U )\
00080                                         |(__STM32F3xx_HAL_VERSION_RC))
00081
00082 #define IDCODE_DEVID_MASK    (0x00000FFFU)
00083 /**
00084   * @}
00085   */
00086
00087 /* Private macro -------------------------------------------------------------*/
00088 /* Private variables ---------------------------------------------------------*/
00089 /** @defgroup HAL_Private_Variables HAL Private Variables
00090   * @{
00091   */
00092 __IO uint32_t uwTick;
00093 /**
00094   * @}
00095   */
00096 /* Private function prototypes -----------------------------------------------*/
00097 /* Exported functions ---------------------------------------------------------*/
00098
00099 /** @defgroup HAL_Exported_Functions HAL Exported Functions
00100   * @{
00101   */
00102
00103 /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
00104  *  @brief    Initialization and de-initialization functions
00105  *
00106 @verbatim
00107  ===============================================================================
00108               ##### Initialization and de-initialization functions #####
00109  ===============================================================================
00110     [..]  This section provides functions allowing to:
00111       (+) Initializes the Flash interface, the NVIC allocation and initial clock
00112           configuration. It initializes the source of time base also when timeout
00113           is needed and the backup domain when enabled.
00114       (+) de-Initializes common part of the HAL.
00115       (+) Configure The time base source to have 1ms time base with a dedicated
00116           Tick interrupt priority.
00117         (++) Systick timer is used by default as source of time base, but user
00118              can eventually implement his proper time base source (a general purpose
00119              timer for example or other time source), keeping in mind that Time base
00120              duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
00121              handled in milliseconds basis.
00122         (++) Time base configuration function (HAL_InitTick ()) is called automatically
00123              at the beginning of the program after reset by HAL_Init() or at any time
00124              when clock is configured, by HAL_RCC_ClockConfig().
00125         (++) Source of time base is configured  to generate interrupts at regular
00126              time intervals. Care must be taken if HAL_Delay() is called from a
00127              peripheral ISR process, the Tick interrupt line must have higher priority
00128             (numerically lower) than the peripheral interrupt. Otherwise the caller
00129             ISR process will be blocked.
00130        (++) functions affecting time base configurations are declared as __Weak
00131              to make  override possible  in case of other  implementations in user file.
00132
00133 @endverbatim
00134   * @{
00135   */
00136
00137 /**
00138   * @brief  This function configures the Flash prefetch,
00139   *         Configures time base source, NVIC and Low level hardware
00140   * @note   This function is called at the beginning of program after reset and before
00141   *         the clock configuration
00142   *
00143   * @note   The Systick configuration is based on HSI clock, as HSI is the clock
00144   *         used after a system Reset and the NVIC configuration is set to Priority group 4
00145   *
00146   * @note   The time base configuration is based on MSI clock when exting from Reset.
00147   *         Once done, time base tick start incrementing.
00148   *         In the default implementation,Systick is used as source of time base.
00149   *       The tick variable is incremented each 1ms in its ISR.
00150   * @retval HAL status
00151   */
00152 HAL_StatusTypeDef HAL_Init(void)
00153 {
00154   /* Configure Flash prefetch */
00155 #if (PREFETCH_ENABLE != 0U)
00156   __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
00157 #endif /* PREFETCH_ENABLE */
00158
00159   /* Set Interrupt Group Priority */
00160   HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
00161
00162   /* Enable systick and configure 1ms tick (default clock after Reset is HSI) */
00163   HAL_InitTick(TICK_INT_PRIORITY);
00164
00165   /* Init the low level hardware */
00166   HAL_MspInit();
00167
00168   /* Return function status */
00169   return HAL_OK;
00170 }
00171
00172 /**
00173   * @brief  This function de-Initializes common part of the HAL and stops the source
00174   *         of time base.
00175   * @note This function is optional.
00176   * @retval HAL status
00177   */
00178 HAL_StatusTypeDef HAL_DeInit(void)
00179 {
00180   /* Reset of all peripherals */
00181   __HAL_RCC_APB1_FORCE_RESET();
00182   __HAL_RCC_APB1_RELEASE_RESET();
00183
00184   __HAL_RCC_APB2_FORCE_RESET();
00185   __HAL_RCC_APB2_RELEASE_RESET();
00186
00187   __HAL_RCC_AHB_FORCE_RESET();
00188   __HAL_RCC_AHB_RELEASE_RESET();
00189
00190   /* De-Init the low level hardware */
00191   HAL_MspDeInit();
00192
00193   /* Return function status */
00194   return HAL_OK;
00195 }
00196
00197 /**
00198   * @brief  Initializes the MSP.
00199   * @retval None
00200   */
00201 __weak void HAL_MspInit(void)
00202 {
00203   /* NOTE : This function Should not be modified, when the callback is needed,
00204             the HAL_MspInit could be implemented in the user file
00205    */
00206 }
00207
00208 /**
00209   * @brief  DeInitializes the MSP.
00210   * @retval None
00211   */
00212 __weak void HAL_MspDeInit(void)
00213 {
00214   /* NOTE : This function Should not be modified, when the callback is needed,
00215             the HAL_MspDeInit could be implemented in the user file
00216    */
00217 }
00218
00219 /**
00220   * @brief  This function configures the source of the time base.
00221   *         The time source is configured  to have 1ms time base with a dedicated
00222   *         Tick interrupt priority.
00223   * @note   This function is called  automatically at the beginning of program after
00224   *         reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
00225   * @note   In the default implementation , SysTick timer is the source of time base.
00226   *         It is used to generate interrupts at regular time intervals.
00227   *         Care must be taken if HAL_Delay() is called from a peripheral ISR process,
00228   *         The the SysTick interrupt must have higher priority (numerically lower)
00229   *         than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
00230   *         The function is declared as __Weak  to be overwritten  in case of other
00231   *         implementation  in user file.
00232   * @param TickPriority Tick interrupt priority.
00233   * @retval HAL status
00234   */
00235 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
00236 {
00237   /*Configure the SysTick to have interrupt in 1ms time basis*/
00238   HAL_SYSTICK_Config(SystemCoreClock / 1000U);
00239
00240   /*Configure the SysTick IRQ priority */
00241   HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
00242
00243    /* Return function status */
00244   return HAL_OK;
00245 }
00246
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
00252  *  @brief    HAL Control functions
00253  *
00254 @verbatim
00255  ===============================================================================
00256                       ##### HAL Control functions #####
00257  ===============================================================================
00258     [..]  This section provides functions allowing to:
00259       (+) Provide a tick value in millisecond
00260       (+) Provide a blocking delay in millisecond
00261       (+) Suspend the time base source interrupt
00262       (+) Resume the time base source interrupt
00263       (+) Get the HAL API driver version
00264       (+) Get the device identifier
00265       (+) Get the device revision identifier
00266       (+) Enable/Disable Debug module during Sleep mode
00267       (+) Enable/Disable Debug module during STOP mode
00268       (+) Enable/Disable Debug module during STANDBY mode
00269
00270 @endverbatim
00271   * @{
00272   */
00273
00274 /**
00275   * @brief  This function is called to increment  a global variable "uwTick"
00276   *         used as application time base.
00277   * @note In the default implementation, this variable is incremented each 1ms
00278   *         in Systick ISR.
00279   * @note This function is declared as __weak to be overwritten in case of other
00280   *         implementations  in user file.
00281   * @retval None
00282   */
00283 __weak void HAL_IncTick(void)
00284 {
00285   uwTick++;
00286 }
00287
00288 /**
00289   * @brief  Povides a tick value in millisecond.
00290   * @note   The function is declared as __Weak  to be overwritten  in case of other
00291   *         implementations  in user file.
00292   * @retval tick value
00293   */
00294 __weak uint32_t HAL_GetTick(void)
00295 {
00296   return uwTick;
00297 }
00298
00299 /**
00300   * @brief  This function provides accurate delay (in milliseconds) based
00301   *         on variable incremented.
00302   * @note   In the default implementation , SysTick timer is the source of time base.
00303   *         It is used to generate interrupts at regular time intervals where uwTick
00304   *         is incremented.
00305   *         The function is declared as __Weak  to be overwritten  in case of other
00306   *         implementations  in user file.
00307   * @param  Delay specifies the delay time length, in milliseconds.
00308   * @retval None
00309   */
00310 __weak void HAL_Delay(__IO uint32_t Delay)
00311 {
00312   uint32_t tickstart = HAL_GetTick();
00313   uint32_t wait = Delay;
00314
00315   /* Add a period to guarantee minimum wait */
00316   if (wait < HAL_MAX_DELAY)
00317   {
00318      wait++;
00319   }
00320
00321   while((HAL_GetTick() - tickstart) < wait)
00322   {
00323   }
00324 }
00325
00326 /**
00327   * @brief  Suspend Tick increment.
00328   * @note   In the default implementation , SysTick timer is the source of time base. It is
00329   *         used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
00330   *         is called, the the SysTick interrupt will be disabled and so Tick increment
00331   *         is suspended.
00332   * @note This function is declared as __weak to be overwritten in case of other
00333   *         implementations  in user file.
00334   * @retval None
00335   */
00336 __weak void HAL_SuspendTick(void)
00337
00338 {
00339   /* Disable SysTick Interrupt */
00340   SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
00341
00342 }
00343
00344 /**
00345   * @brief  Resume Tick increment.
00346   * @note   In the default implementation , SysTick timer is the source of time base. It is
00347   *         used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
00348   *         is called, the the SysTick interrupt will be enabled and so Tick increment
00349   *         is resumed.
00350   *         The function is declared as __Weak  to be overwritten  in case of other
00351   *         implementations  in user file.
00352   * @retval None
00353   */
00354 __weak void HAL_ResumeTick(void)
00355 {
00356   /* Enable SysTick Interrupt */
00357   SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
00358
00359 }
00360
00361 /**
00362   * @brief  This function returns the HAL revision
00363   * @retval version : 0xXYZR (8bits for each decimal, R for RC)
00364   */
00365 uint32_t HAL_GetHalVersion(void)
00366 {
00367  return __STM32F3xx_HAL_VERSION;
00368 }
00369
00370 /**
00371   * @brief  Returns the device revision identifier.
00372   * @retval Device revision identifier
00373   */
00374 uint32_t HAL_GetREVID(void)
00375 {
00376   return((DBGMCU->IDCODE) >> 16U);
00377 }
00378
00379 /**
00380   * @brief  Returns the device identifier.
00381   * @retval Device identifier
00382   */
00383 uint32_t HAL_GetDEVID(void)
00384 {
00385   return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
00386 }
00387
00388 /**
00389   * @brief  Returns first word of the unique device identifier (UID based on 96 bits)
00390   * @retval Device identifier
00391   */
00392 uint32_t HAL_GetUIDw0(void)
00393 {
00394    return(READ_REG(*((uint32_t *)UID_BASE)));
00395 }
00396
00397 /**
00398   * @brief  Returns second word of the unique device identifier (UID based on 96 bits)
00399   * @retval Device identifier
00400   */
00401 uint32_t HAL_GetUIDw1(void)
00402 {
00403    return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
00404 }
00405
00406 /**
00407   * @brief  Returns third word of the unique device identifier (UID based on 96 bits)
00408   * @retval Device identifier
00409   */
00410 uint32_t HAL_GetUIDw2(void)
00411 {
00412    return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
00413 }
00414
00415 /**
00416   * @brief  Enable the Debug Module during SLEEP mode
00417   * @retval None
00418   */
00419 void HAL_DBGMCU_EnableDBGSleepMode(void)
00420 {
00421   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00422 }
00423
00424 /**
00425   * @brief  Disable the Debug Module during SLEEP mode
00426   * @retval None
00427   */
00428 void HAL_DBGMCU_DisableDBGSleepMode(void)
00429 {
00430   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00431 }
00432
00433 /**
00434   * @brief  Enable the Debug Module during STOP mode
00435   * @retval None
00436   */
00437 void HAL_DBGMCU_EnableDBGStopMode(void)
00438 {
00439   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00440 }
00441
00442 /**
00443   * @brief  Disable the Debug Module during STOP mode
00444   * @retval None
00445   */
00446 void HAL_DBGMCU_DisableDBGStopMode(void)
00447 {
00448   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00449 }
00450
00451 /**
00452   * @brief  Enable the Debug Module during STANDBY mode
00453   * @retval None
00454   */
00455 void HAL_DBGMCU_EnableDBGStandbyMode(void)
00456 {
00457   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
00458 }
00459
00460 /**
00461   * @brief  Disable the Debug Module during STANDBY mode
00462   * @retval None
00463   */
00464 void HAL_DBGMCU_DisableDBGStandbyMode(void)
00465 {
00466   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
00467 }
00468
00469 /**
00470   * @}
00471   */
00472
00473 /**
00474   * @}
00475   */
00476
00477 #endif /* HAL_MODULE_ENABLED */
00478 /**
00479   * @}
00480   */
00481
00482 /**
00483   * @}
00484   */
00485
00486 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal.h Source File

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stm32f3xx_hal.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal.h
00004   * @author  MCD Application Team
00005   * @brief   This file contains all the functions prototypes for the HAL
00006   *          module driver.
00007   ******************************************************************************
00008   * @attention
00009   *
00010   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00011   *
00012   * Redistribution and use in source and binary forms, with or without modification,
00013   * are permitted provided that the following conditions are met:
00014   *   1. Redistributions of source code must retain the above copyright notice,
00015   *      this list of conditions and the following disclaimer.
00016   *   2. Redistributions in binary form must reproduce the above copyright notice,
00017   *      this list of conditions and the following disclaimer in the documentation
00018   *      and/or other materials provided with the distribution.
00019   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00020   *      may be used to endorse or promote products derived from this software
00021   *      without specific prior written permission.
00022   *
00023   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00024   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00025   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00026   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00027   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00028   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00029   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00030   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00031   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00032   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00033   *
00034   ******************************************************************************
00035   */
00036
00037 /* Define to prevent recursive inclusion -------------------------------------*/
00038 #ifndef __STM32F3xx_HAL_H
00039 #define __STM32F3xx_HAL_H
00040
00041 #ifdef __cplusplus
00042  extern "C" {
00043 #endif
00044
00045 /* Includes ------------------------------------------------------------------*/
00046 #include "stm32f3xx_hal_conf.h"
00047
00048 /** @addtogroup STM32F3xx_HAL_Driver
00049   * @{
00050   */
00051
00052 /** @addtogroup HAL
00053   * @{
00054   */
00055
00056 /* Private macros ------------------------------------------------------------*/
00057 /** @addtogroup HAL_Private_Macros
00058   * @{
00059   */
00060 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6)  == SYSCFG_FASTMODEPLUS_PB6)  || \
00061                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7)  == SYSCFG_FASTMODEPLUS_PB7)  || \
00062                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8)  == SYSCFG_FASTMODEPLUS_PB8)  || \
00063                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9)  == SYSCFG_FASTMODEPLUS_PB9))
00064 /**
00065   * @}
00066   */
00067
00068 /* Exported types ------------------------------------------------------------*/
00069 /* Exported constants --------------------------------------------------------*/
00070 /** @defgroup HAL_Exported_Constants HAL Exported Constants
00071   * @{
00072   */
00073 /** @defgroup SYSCFG_BitAddress_AliasRegion SYSCFG registers bit address in the alias region
00074   * @brief SYSCFG registers bit address in the alias region
00075   * @{
00076   */
00077 /* ------------ SYSCFG registers bit address in the alias region -------------*/
00078 #define SYSCFG_OFFSET                (SYSCFG_BASE - PERIPH_BASE)
00079 /* --- CFGR2 Register ---*/
00080 /* Alias word address of BYP_ADDR_PAR bit */
00081 #define CFGR2_OFFSET                 (SYSCFG_OFFSET + 0x18U)
00082 #define BYPADDRPAR_BitNumber          0x04U
00083 #define CFGR2_BYPADDRPAR_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32U) + (BYPADDRPAR_BitNumber * 4U))
00084 /**
00085   * @}
00086   */
00087
00088 #if defined(SYSCFG_CFGR1_DMA_RMP)
00089 /** @defgroup HAL_DMA_Remapping HAL DMA Remapping
00090   *        Elements values convention: 0xXXYYYYYY
00091   *           - YYYYYY  : Position in the register
00092   *           - XX  : Register index
00093   *                 - 00: CFGR1 register in SYSCFG
00094   *                 - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices)
00095   * @{
00096   */
00097 #define HAL_REMAPDMA_ADC24_DMA2_CH34         (0x00000100U) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
00098                                                                           1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */
00099 #define HAL_REMAPDMA_TIM16_DMA1_CH6          (0x00000800U) /*!< TIM16 DMA request remap
00100                                                                          1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */
00101 #define HAL_REMAPDMA_TIM17_DMA1_CH7          (0x00001000U) /*!< TIM17 DMA request remap
00102                                                                          1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */
00103 #define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3  (0x00002000U) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
00104                                                                          1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */
00105 #define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4  (0x00004000U) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
00106                                                                          1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */
00107 #define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5       (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
00108                                                                          1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
00109 #define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
00110                                                                          1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
00111 #if defined(SYSCFG_CFGR3_DMA_RMP)
00112 #if !defined(HAL_REMAP_CFGR3_MASK)
00113 #define HAL_REMAP_CFGR3_MASK                 (0x01000000U)
00114 #endif
00115
00116 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH2        (0x01000003U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
00117                                                                          11: Map on DMA1 channel 2 */
00118 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH4        (0x01000001U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
00119                                                                          01: Map on DMA1 channel 4 */
00120 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH6        (0x01000002U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
00121                                                                          10: Map on DMA1 channel 6 */
00122 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH3        (0x0100000CU) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
00123                                                                          11: Map on DMA1 channel 3 */
00124 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH5        (0x01000004U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
00125                                                                          01: Map on DMA1 channel 5 */
00126 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH7        (0x01000008U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
00127                                                                          10: Map on DMA1 channel 7 */
00128 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH7        (0x01000030U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
00129                                                                          11: Map on DMA1 channel 7 */
00130 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH3        (0x01000010U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
00131                                                                          01: Map on DMA1 channel 3 */
00132 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH5        (0x01000020U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
00133                                                                          10: Map on DMA1 channel 5 */
00134 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH6        (0x010000C0U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
00135                                                                          11: Map on DMA1 channel 6 */
00136 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH2        (0x01000040U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
00137                                                                          01: Map on DMA1 channel 2 */
00138 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH4        (0x01000080U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
00139                                                                          10: Map on DMA1 channel 4 */
00140 #define HAL_REMAPDMA_ADC2_DMA1_CH2           (0x01000100U) /*!< ADC2 DMA remap
00141                                                                          x0: No remap (ADC2 on DMA2)
00142                                                                          10: Map on DMA1 channel 2 */
00143 #define HAL_REMAPDMA_ADC2_DMA1_CH4           (0x01000300U) /*!< ADC2 DMA remap
00144                                                                          11: Map on DMA1 channel 4 */
00145 #endif /* SYSCFG_CFGR3_DMA_RMP */
00146
00147 #if defined(SYSCFG_CFGR3_DMA_RMP)
00148 #define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34)         == HAL_REMAPDMA_ADC24_DMA2_CH34)         || \
00149                               (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6)          == HAL_REMAPDMA_TIM16_DMA1_CH6)          || \
00150                               (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7)          == HAL_REMAPDMA_TIM17_DMA1_CH7)          || \
00151                               (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3)  == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3)  || \
00152                               (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4)  == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4)  || \
00153                               (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5)       == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5)       || \
00154                               (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \
00155                               (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2)        == HAL_REMAPDMA_SPI1_RX_DMA1_CH2)  || \
00156                               (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4)        == HAL_REMAPDMA_SPI1_RX_DMA1_CH4)  || \
00157                               (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6)        == HAL_REMAPDMA_SPI1_RX_DMA1_CH6)  || \
00158                               (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3)        == HAL_REMAPDMA_SPI1_TX_DMA1_CH3)  || \
00159                               (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5)        == HAL_REMAPDMA_SPI1_TX_DMA1_CH5)  || \
00160                               (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7)        == HAL_REMAPDMA_SPI1_TX_DMA1_CH7)  || \
00161                               (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7)        == HAL_REMAPDMA_I2C1_RX_DMA1_CH7)  || \
00162                               (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3)        == HAL_REMAPDMA_I2C1_RX_DMA1_CH3)  || \
00163                               (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5)        == HAL_REMAPDMA_I2C1_RX_DMA1_CH5)  || \
00164                               (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6)        == HAL_REMAPDMA_I2C1_TX_DMA1_CH6)  || \
00165                               (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2)        == HAL_REMAPDMA_I2C1_TX_DMA1_CH2)  || \
00166                               (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4)        == HAL_REMAPDMA_I2C1_TX_DMA1_CH4)  || \
00167                               (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2)           == HAL_REMAPDMA_ADC2_DMA1_CH2)     || \
00168                               (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4)           == HAL_REMAPDMA_ADC2_DMA1_CH4))
00169 #else
00170 #define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34)         == HAL_REMAPDMA_ADC24_DMA2_CH34)         || \
00171                               (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6)          == HAL_REMAPDMA_TIM16_DMA1_CH6)          || \
00172                               (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7)          == HAL_REMAPDMA_TIM17_DMA1_CH7)          || \
00173                               (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3)  == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3)  || \
00174                               (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4)  == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4)  || \
00175                               (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5)       == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5)       || \
00176                               (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5))
00177 #endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/
00178 /**
00179   * @}
00180   */
00181 #endif /* SYSCFG_CFGR1_DMA_RMP */
00182
00183 /** @defgroup HAL_Trigger_Remapping HAL Trigger Remapping
00184   *        Elements values convention: 0xXXYYYYYY
00185   *           - YYYYYY  : Position in the register
00186   *           - XX  : Register index
00187   *                 - 00: CFGR1 register in SYSCFG
00188   *                 - 01: CFGR3 register in SYSCFG
00189   * @{
00190   */
00191 #define HAL_REMAPTRIGGER_DAC1_TRIG         (0x00000080U)  /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices)
00192                                                                         0: No remap (DAC trigger is TIM8_TRGO)
00193                                                                         1: Remap (DAC trigger is TIM3_TRGO) */
00194 #define HAL_REMAPTRIGGER_TIM1_ITR3         (0x00000040U)  /*!< TIM1 ITR3 trigger remap
00195                                                                         0: No remap
00196                                                                         1: Remap (TIM1_TRG3 = TIM17_OC) */
00197 #if defined(SYSCFG_CFGR3_TRIGGER_RMP)
00198 #if !defined(HAL_REMAP_CFGR3_MASK)
00199 #define HAL_REMAP_CFGR3_MASK               (0x01000000U)
00200 #endif
00201 #define HAL_REMAPTRIGGER_DAC1_TRIG3        (0x01010000U)  /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
00202                                                                         0: Remap (DAC trigger is TIM15_TRGO)
00203                                                                         1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */
00204 #define HAL_REMAPTRIGGER_DAC1_TRIG5        (0x01020000U)  /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
00205                                                                         0: No remap
00206                                                                         1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */
00207 #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1)       == HAL_REMAPTRIGGER_DAC1)       || \
00208                                   (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3)  == HAL_REMAPTRIGGER_TIM1_ITR3)  || \
00209                                   (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \
00210                                   (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5))
00211 #else
00212 #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1)       == HAL_REMAPTRIGGER_DAC1)       || \
00213                                   (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3)  == HAL_REMAPTRIGGER_TIM1_ITR3))
00214 #endif /* SYSCFG_CFGR3_TRIGGER_RMP */
00215 /**
00216   * @}
00217   */
00218
00219 #if defined (STM32F302xE)
00220 /** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping
00221   * @{
00222   */
00223 #define HAL_REMAPADCTRIGGER_ADC12_EXT2        SYSCFG_CFGR4_ADC12_EXT2_RMP   /*!< Input trigger of ADC12 regular channel EXT2
00224                                                                                  0: No remap (TIM1_CC3)
00225                                                                                  1: Remap (TIM20_TRGO) */
00226 #define HAL_REMAPADCTRIGGER_ADC12_EXT3        SYSCFG_CFGR4_ADC12_EXT3_RMP   /*!< Input trigger of ADC12 regular channel EXT3
00227                                                                                  0: No remap (TIM2_CC2)
00228                                                                                  1: Remap (TIM20_TRGO2) */
00229 #define HAL_REMAPADCTRIGGER_ADC12_EXT5        SYSCFG_CFGR4_ADC12_EXT5_RMP   /*!< Input trigger of ADC12 regular channel EXT5
00230                                                                                  0: No remap (TIM4_CC4)
00231                                                                                  1: Remap (TIM20_CC1) */
00232 #define HAL_REMAPADCTRIGGER_ADC12_EXT13       SYSCFG_CFGR4_ADC12_EXT13_RMP  /*!< Input trigger of ADC12 regular channel EXT13
00233                                                                                  0: No remap (TIM6_TRGO)
00234                                                                                  1: Remap (TIM20_CC2) */
00235 #define HAL_REMAPADCTRIGGER_ADC12_EXT15       SYSCFG_CFGR4_ADC12_EXT15_RMP  /*!< Input trigger of ADC12 regular channel EXT15
00236                                                                                  0: No remap (TIM3_CC4)
00237                                                                                  1: Remap (TIM20_CC3) */
00238 #define HAL_REMAPADCTRIGGER_ADC12_JEXT3       SYSCFG_CFGR4_ADC12_JEXT3_RMP  /*!< Input trigger of ADC12 injected channel JEXT3
00239                                                                                  0: No remap (TIM2_CC1)
00240                                                                                  1: Remap (TIM20_TRGO) */
00241 #define HAL_REMAPADCTRIGGER_ADC12_JEXT6       SYSCFG_CFGR4_ADC12_JEXT6_RMP  /*!< Input trigger of ADC12 injected channel JEXT6
00242                                                                                  0: No remap (EXTI line 15)
00243                                                                                  1: Remap (TIM20_TRGO2) */
00244 #define HAL_REMAPADCTRIGGER_ADC12_JEXT13      SYSCFG_CFGR4_ADC12_JEXT13_RMP  /*!< Input trigger of ADC12 injected channel JEXT13
00245                                                                                  0: No remap (TIM3_CC1)
00246                                                                                  1: Remap (TIM20_CC4) */
00247
00248 #define IS_HAL_REMAPADCTRIGGER(RMP)  ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2)   == HAL_REMAPADCTRIGGER_ADC12_EXT2)   || \
00249                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3)   == HAL_REMAPADCTRIGGER_ADC12_EXT3)   || \
00250                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5)   == HAL_REMAPADCTRIGGER_ADC12_EXT5)   || \
00251                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13)  == HAL_REMAPADCTRIGGER_ADC12_EXT13)  || \
00252                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15)  == HAL_REMAPADCTRIGGER_ADC12_EXT15)  || \
00253                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3)  == HAL_REMAPADCTRIGGER_ADC12_JEXT3)  || \
00254                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6)  == HAL_REMAPADCTRIGGER_ADC12_JEXT6)  || \
00255                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13))
00256 /**
00257   * @}
00258   */
00259 #endif /* STM32F302xE */
00260
00261 #if defined (STM32F303xE) || defined (STM32F398xx)
00262 /** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping
00263   * @{
00264   */
00265 #define HAL_REMAPADCTRIGGER_ADC12_EXT2        SYSCFG_CFGR4_ADC12_EXT2_RMP   /*!< Input trigger of ADC12 regular channel EXT2
00266                                                                                  0: No remap (TIM1_CC3)
00267                                                                                  1: Remap (TIM20_TRGO) */
00268 #define HAL_REMAPADCTRIGGER_ADC12_EXT3        SYSCFG_CFGR4_ADC12_EXT3_RMP   /*!< Input trigger of ADC12 regular channel EXT3
00269                                                                                  0: No remap (TIM2_CC2)
00270                                                                                  1: Remap (TIM20_TRGO2) */
00271 #define HAL_REMAPADCTRIGGER_ADC12_EXT5        SYSCFG_CFGR4_ADC12_EXT5_RMP   /*!< Input trigger of ADC12 regular channel EXT5
00272                                                                                  0: No remap (TIM4_CC4)
00273                                                                                  1: Remap (TIM20_CC1) */
00274 #define HAL_REMAPADCTRIGGER_ADC12_EXT13       SYSCFG_CFGR4_ADC12_EXT13_RMP  /*!< Input trigger of ADC12 regular channel EXT13
00275                                                                                  0: No remap (TIM6_TRGO)
00276                                                                                  1: Remap (TIM20_CC2) */
00277 #define HAL_REMAPADCTRIGGER_ADC12_EXT15       SYSCFG_CFGR4_ADC12_EXT15_RMP  /*!< Input trigger of ADC12 regular channel EXT15
00278                                                                                  0: No remap (TIM3_CC4)
00279                                                                                  1: Remap (TIM20_CC3) */
00280 #define HAL_REMAPADCTRIGGER_ADC12_JEXT3       SYSCFG_CFGR4_ADC12_JEXT3_RMP  /*!< Input trigger of ADC12 injected channel JEXT3
00281                                                                                  0: No remap (TIM2_CC1)
00282                                                                                  1: Remap (TIM20_TRGO) */
00283 #define HAL_REMAPADCTRIGGER_ADC12_JEXT6       SYSCFG_CFGR4_ADC12_JEXT6_RMP  /*!< Input trigger of ADC12 injected channel JEXT6
00284                                                                                  0: No remap (EXTI line 15)
00285                                                                                  1: Remap (TIM20_TRGO2) */
00286 #define HAL_REMAPADCTRIGGER_ADC12_JEXT13      SYSCFG_CFGR4_ADC12_JEXT13_RMP  /*!< Input trigger of ADC12 injected channel JEXT13
00287                                                                                  0: No remap (TIM3_CC1)
00288                                                                                  1: Remap (TIM20_CC4) */
00289 #define HAL_REMAPADCTRIGGER_ADC34_EXT5        SYSCFG_CFGR4_ADC34_EXT5_RMP   /*!< Input trigger of ADC34 regular channel EXT5
00290                                                                                  0: No remap (EXTI line 2)
00291                                                                                  1: Remap (TIM20_TRGO) */
00292 #define HAL_REMAPADCTRIGGER_ADC34_EXT6        SYSCFG_CFGR4_ADC34_EXT6_RMP   /*!< Input trigger of ADC34 regular channel EXT6
00293                                                                                  0: No remap (TIM4_CC1)
00294                                                                                  1: Remap (TIM20_TRGO2) */
00295 #define HAL_REMAPADCTRIGGER_ADC34_EXT15       SYSCFG_CFGR4_ADC34_EXT15_RMP  /*!< Input trigger of ADC34 regular channel EXT15
00296                                                                                  0: No remap (TIM2_CC1)
00297                                                                                  1: Remap (TIM20_CC1) */
00298 #define HAL_REMAPADCTRIGGER_ADC34_JEXT5       SYSCFG_CFGR4_ADC34_JEXT5_RMP  /*!< Input trigger of ADC34 injected channel JEXT5
00299                                                                                  0: No remap (TIM4_CC3)
00300                                                                                  1: Remap (TIM20_TRGO) */
00301 #define HAL_REMAPADCTRIGGER_ADC34_JEXT11      SYSCFG_CFGR4_ADC34_JEXT11_RMP /*!< Input trigger of ADC34 injected channel JEXT11
00302                                                                                  0: No remap (TIM1_CC3)
00303                                                                                  1: Remap (TIM20_TRGO2) */
00304 #define HAL_REMAPADCTRIGGER_ADC34_JEXT14      SYSCFG_CFGR4_ADC34_JEXT14_RMP /*!< Input trigger of ADC34 injected channel JEXT14
00305                                                                                  0: No remap (TIM7_TRGO)
00306                                                                                  1: Remap (TIM20_CC2) */
00307
00308 #define IS_HAL_REMAPADCTRIGGER(RMP)  ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2)   == HAL_REMAPADCTRIGGER_ADC12_EXT2)   || \
00309                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3)   == HAL_REMAPADCTRIGGER_ADC12_EXT3)   || \
00310                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5)   == HAL_REMAPADCTRIGGER_ADC12_EXT5)   || \
00311                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13)  == HAL_REMAPADCTRIGGER_ADC12_EXT13)  || \
00312                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15)  == HAL_REMAPADCTRIGGER_ADC12_EXT15)  || \
00313                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3)  == HAL_REMAPADCTRIGGER_ADC12_JEXT3)  || \
00314                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6)  == HAL_REMAPADCTRIGGER_ADC12_JEXT6)  || \
00315                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13) || \
00316                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5)   == HAL_REMAPADCTRIGGER_ADC34_EXT5)   || \
00317                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6)   == HAL_REMAPADCTRIGGER_ADC34_EXT6)   || \
00318                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15)  == HAL_REMAPADCTRIGGER_ADC34_EXT15)  || \
00319                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5)  == HAL_REMAPADCTRIGGER_ADC34_JEXT5)  || \
00320                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11) == HAL_REMAPADCTRIGGER_ADC34_JEXT11) || \
00321                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14) == HAL_REMAPADCTRIGGER_ADC34_JEXT14))
00322 /**
00323   * @}
00324   */
00325 #endif /* STM32F303xE || STM32F398xx */
00326
00327 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
00328   * @{
00329   */
00330
00331 /** @brief  Fast-mode Plus driving capability on a specific GPIO
00332   */
00333 #if defined(SYSCFG_CFGR1_I2C_PB6_FMP)
00334 #define SYSCFG_FASTMODEPLUS_PB6    ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP)  /*!< Enable Fast-mode Plus on PB6  */
00335 #endif /* SYSCFG_CFGR1_I2C_PB6_FMP */
00336
00337 #if defined(SYSCFG_CFGR1_I2C_PB7_FMP)
00338 #define SYSCFG_FASTMODEPLUS_PB7    ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP)  /*!< Enable Fast-mode Plus on PB7  */
00339 #endif /* SYSCFG_CFGR1_I2C_PB7_FMP */
00340
00341 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
00342 #define SYSCFG_FASTMODEPLUS_PB8    ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP)  /*!< Enable Fast-mode Plus on PB8  */
00343 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
00344
00345 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
00346 #define SYSCFG_FASTMODEPLUS_PB9    ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP)  /*!< Enable Fast-mode Plus on PB9  */
00347 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
00348 /**
00349   * @}
00350   */
00351
00352 #if defined(SYSCFG_RCR_PAGE0)
00353 /* CCM-SRAM defined */
00354 /** @defgroup HAL_Page_Write_Protection HAL CCM RAM page write protection
00355   * @{
00356   */
00357 #define HAL_SYSCFG_WP_PAGE0                    (SYSCFG_RCR_PAGE0)  /*!< ICODE SRAM Write protection page 0 */
00358 #define HAL_SYSCFG_WP_PAGE1                    (SYSCFG_RCR_PAGE1)  /*!< ICODE SRAM Write protection page 1 */
00359 #define HAL_SYSCFG_WP_PAGE2                    (SYSCFG_RCR_PAGE2)  /*!< ICODE SRAM Write protection page 2 */
00360 #define HAL_SYSCFG_WP_PAGE3                    (SYSCFG_RCR_PAGE3)  /*!< ICODE SRAM Write protection page 3 */
00361 #if defined(SYSCFG_RCR_PAGE4)
00362 /* More than 4KB CCM-SRAM defined */
00363 #define HAL_SYSCFG_WP_PAGE4                    (SYSCFG_RCR_PAGE4)  /*!< ICODE SRAM Write protection page 4 */
00364 #define HAL_SYSCFG_WP_PAGE5                    (SYSCFG_RCR_PAGE5)  /*!< ICODE SRAM Write protection page 5 */
00365 #define HAL_SYSCFG_WP_PAGE6                    (SYSCFG_RCR_PAGE6)  /*!< ICODE SRAM Write protection page 6 */
00366 #define HAL_SYSCFG_WP_PAGE7                    (SYSCFG_RCR_PAGE7)  /*!< ICODE SRAM Write protection page 7 */
00367 #endif /* SYSCFG_RCR_PAGE4 */
00368 #if defined(SYSCFG_RCR_PAGE8)
00369 #define HAL_SYSCFG_WP_PAGE8                    (SYSCFG_RCR_PAGE8)  /*!< ICODE SRAM Write protection page 8 */
00370 #define HAL_SYSCFG_WP_PAGE9                    (SYSCFG_RCR_PAGE9)  /*!< ICODE SRAM Write protection page 9 */
00371 #define HAL_SYSCFG_WP_PAGE10                   (SYSCFG_RCR_PAGE10) /*!< ICODE SRAM Write protection page 10 */
00372 #define HAL_SYSCFG_WP_PAGE11                   (SYSCFG_RCR_PAGE11) /*!< ICODE SRAM Write protection page 11 */
00373 #define HAL_SYSCFG_WP_PAGE12                   (SYSCFG_RCR_PAGE12) /*!< ICODE SRAM Write protection page 12 */
00374 #define HAL_SYSCFG_WP_PAGE13                   (SYSCFG_RCR_PAGE13) /*!< ICODE SRAM Write protection page 13 */
00375 #define HAL_SYSCFG_WP_PAGE14                   (SYSCFG_RCR_PAGE14) /*!< ICODE SRAM Write protection page 14 */
00376 #define HAL_SYSCFG_WP_PAGE15                   (SYSCFG_RCR_PAGE15) /*!< ICODE SRAM Write protection page 15 */
00377 #endif /* SYSCFG_RCR_PAGE8 */
00378
00379 #if defined(SYSCFG_RCR_PAGE8)
00380 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__)        (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFU))
00381 #elif defined(SYSCFG_RCR_PAGE4)
00382 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__)        (((__PAGE__) > 0U) && ((__PAGE__) <= 0x00FFU))
00383 #else
00384 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__)        (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000FU))
00385 #endif /* SYSCFG_RCR_PAGE8 */
00386 /**
00387   * @}
00388   */
00389 #endif /* SYSCFG_RCR_PAGE0 */
00390
00391 /** @defgroup HAL_SYSCFG_Interrupts HAL SYSCFG Interrupts
00392   * @{
00393   */
00394 #define HAL_SYSCFG_IT_FPU_IOC                  (SYSCFG_CFGR1_FPU_IE_0)  /*!< Floating Point Unit Invalid operation Interrupt */
00395 #define HAL_SYSCFG_IT_FPU_DZC                  (SYSCFG_CFGR1_FPU_IE_1)  /*!< Floating Point Unit Divide-by-zero Interrupt */
00396 #define HAL_SYSCFG_IT_FPU_UFC                  (SYSCFG_CFGR1_FPU_IE_2)  /*!< Floating Point Unit Underflow Interrupt */
00397 #define HAL_SYSCFG_IT_FPU_OFC                  (SYSCFG_CFGR1_FPU_IE_3)  /*!< Floating Point Unit Overflow Interrupt */
00398 #define HAL_SYSCFG_IT_FPU_IDC                  (SYSCFG_CFGR1_FPU_IE_4)  /*!< Floating Point Unit Input denormal Interrupt */
00399 #define HAL_SYSCFG_IT_FPU_IXC                  (SYSCFG_CFGR1_FPU_IE_5)  /*!< Floating Point Unit Inexact Interrupt */
00400
00401 #define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \
00402                                                 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \
00403                                                 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \
00404                                                 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \
00405                                                 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \
00406                                                 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5))
00407
00408 /**
00409   * @}
00410   */
00411
00412 /**
00413  * @}
00414  */
00415
00416 /* Exported macros -----------------------------------------------------------*/
00417 /** @defgroup HAL_Exported_Macros HAL Exported Macros
00418   * @{
00419   */
00420
00421 /** @defgroup Debug_MCU_APB1_Freeze Freeze/Unfreeze APB1 Peripherals in Debug mode
00422   * @{
00423   */
00424 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
00425 #define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
00426 #define __HAL_DBGMCU_UNFREEZE_TIM2()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
00427 #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
00428
00429 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
00430 #define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
00431 #define __HAL_DBGMCU_UNFREEZE_TIM3()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
00432 #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
00433
00434 #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
00435 #define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
00436 #define __HAL_DBGMCU_UNFREEZE_TIM4()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
00437 #endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
00438
00439 #if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
00440 #define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
00441 #define __HAL_DBGMCU_UNFREEZE_TIM5()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
00442 #endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */
00443
00444 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
00445 #define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
00446 #define __HAL_DBGMCU_UNFREEZE_TIM6()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
00447 #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
00448
00449 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
00450 #define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
00451 #define __HAL_DBGMCU_UNFREEZE_TIM7()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
00452 #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
00453
00454 #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
00455 #define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
00456 #define __HAL_DBGMCU_UNFREEZE_TIM12()        (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
00457 #endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
00458
00459 #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
00460 #define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
00461 #define __HAL_DBGMCU_UNFREEZE_TIM13()        (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
00462 #endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
00463
00464 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
00465 #define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
00466 #define __HAL_DBGMCU_UNFREEZE_TIM14()        (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
00467 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
00468
00469 #if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
00470 #define __HAL_FREEZE_TIM18_DBGMCU()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP))
00471 #define __HAL_UNFREEZE_TIM18_DBGMCU()        (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP))
00472 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
00473
00474 #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
00475 #define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
00476 #define __HAL_DBGMCU_UNFREEZE_RTC()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
00477 #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
00478
00479 #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
00480 #define __HAL_DBGMCU_FREEZE_WWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
00481 #define __HAL_DBGMCU_UNFREEZE_WWDG()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
00482 #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
00483
00484 #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
00485 #define __HAL_DBGMCU_FREEZE_IWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
00486 #define __HAL_DBGMCU_UNFREEZE_IWDG()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
00487 #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
00488
00489 #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
00490 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
00491 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
00492 #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
00493
00494 #if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
00495 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
00496 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
00497 #endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */
00498
00499 #if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
00500 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
00501 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
00502 #endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
00503
00504 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
00505 #define __HAL_FREEZE_CAN_DBGMCU()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
00506 #define __HAL_UNFREEZE_CAN_DBGMCU()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
00507 #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
00508 /**
00509  * @}
00510  */
00511
00512 /** @defgroup Debug_MCU_APB2_Freeze Freeze/Unfreeze APB2 Peripherals in Debug mode
00513   * @{
00514   */
00515 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
00516 #define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
00517 #define __HAL_DBGMCU_UNFREEZE_TIM1()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
00518 #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
00519
00520 #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
00521 #define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
00522 #define __HAL_DBGMCU_UNFREEZE_TIM8()         (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
00523 #endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
00524
00525 #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
00526 #define __HAL_DBGMCU_FREEZE_TIM15()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
00527 #define __HAL_DBGMCU_UNFREEZE_TIM15()        (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
00528 #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
00529
00530 #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
00531 #define __HAL_DBGMCU_FREEZE_TIM16()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
00532 #define __HAL_DBGMCU_UNFREEZE_TIM16()        (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
00533 #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
00534
00535 #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
00536 #define __HAL_DBGMCU_FREEZE_TIM17()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
00537 #define __HAL_DBGMCU_UNFREEZE_TIM17()        (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
00538 #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
00539
00540 #if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
00541 #define __HAL_FREEZE_TIM19_DBGMCU()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
00542 #define __HAL_UNFREEZE_TIM19_DBGMCU()        (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))
00543 #endif /* DBGMCU_APB2_FZ_DBG_TIM19_STOP */
00544
00545 #if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
00546 #define __HAL_FREEZE_TIM20_DBGMCU()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM20_STOP))
00547 #define __HAL_UNFREEZE_TIM20_DBGMCU()        (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM20_STOP))
00548 #endif /* DBGMCU_APB2_FZ_DBG_TIM20_STOP */
00549
00550 #if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
00551 #define __HAL_FREEZE_HRTIM1_DBGMCU()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
00552 #define __HAL_UNFREEZE_HRTIM1_DBGMCU()        (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
00553 #endif /* DBGMCU_APB2_FZ_DBG_HRTIM1_STOP */
00554 /**
00555  * @}
00556  */
00557
00558 /** @defgroup Memory_Mapping_Selection Memory Mapping Selection
00559   * @{
00560   */
00561 #if defined(SYSCFG_CFGR1_MEM_MODE)
00562 /** @brief  Main Flash memory mapped at 0x00000000
00563   */
00564 #define __HAL_SYSCFG_REMAPMEMORY_FLASH()        (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
00565 #endif /* SYSCFG_CFGR1_MEM_MODE */
00566
00567 #if defined(SYSCFG_CFGR1_MEM_MODE_0)
00568 /** @brief  System Flash memory mapped at 0x00000000
00569   */
00570 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()  do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
00571                                              SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0;  \
00572                                             }while(0U)
00573 #endif /* SYSCFG_CFGR1_MEM_MODE_0 */
00574
00575 #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
00576 /** @brief  Embedded SRAM mapped at 0x00000000
00577   */
00578 #define __HAL_SYSCFG_REMAPMEMORY_SRAM()         do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
00579                                              SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
00580                                             }while(0U)
00581 #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
00582
00583 #if defined(SYSCFG_CFGR1_MEM_MODE_2)
00584 #define __HAL_SYSCFG_FMC_BANK()         do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
00585                                      SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_2); \
00586                                     }while(0U)
00587 #endif /* SYSCFG_CFGR1_MEM_MODE_2 */
00588 /**
00589  * @}
00590  */
00591
00592 /** @defgroup Encoder_Mode Encoder Mode
00593   * @{
00594   */
00595 #if defined(SYSCFG_CFGR1_ENCODER_MODE)
00596 /** @brief  No Encoder mode
00597   */
00598 #define __HAL_REMAPENCODER_NONE()        (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE))
00599 #endif /* SYSCFG_CFGR1_ENCODER_MODE */
00600
00601 #if defined(SYSCFG_CFGR1_ENCODER_MODE_0)
00602 /** @brief  Encoder mode : TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
00603   */
00604 #define __HAL_REMAPENCODER_TIM2()        do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
00605                                              SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0;  \
00606                                             }while(0U)
00607 #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */
00608
00609 #if defined(SYSCFG_CFGR1_ENCODER_MODE_1)
00610 /** @brief  Encoder mode : TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
00611   */
00612 #define __HAL_REMAPENCODER_TIM3()        do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
00613                                              SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1;  \
00614                                             }while(0U)
00615 #endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */
00616
00617 #if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1)
00618 /** @brief  Encoder mode : TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 (STM32F303xB/C and STM32F358xx devices)
00619   */
00620 #define __HAL_REMAPENCODER_TIM4()        do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
00621                                              SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1);  \
00622                                             }while(0U)
00623 #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */
00624 /**
00625  * @}
00626  */
00627
00628 /** @defgroup DMA_Remap_Enable DMA Remap Enable
00629   * @{
00630   */
00631 #if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
00632 /** @brief  DMA remapping enable/disable macros
00633   * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping
00634   */
00635 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__)   do {assert_param(IS_DMA_REMAP((__DMA_REMAP__)));                  \
00636                                                            (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ?                      \
00637                                                              (SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
00638                                                              (SYSCFG->CFGR1 |= (__DMA_REMAP__)));                           \
00639                                                          }while(0U)
00640 #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__)  do {assert_param(IS_DMA_REMAP((__DMA_REMAP__)));                  \
00641                                                            (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ?                      \
00642                                                              (SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
00643                                                              (SYSCFG->CFGR1 &= ~(__DMA_REMAP__)));                          \
00644                                                          }while(0U)
00645 #elif defined(SYSCFG_CFGR1_DMA_RMP)
00646 /** @brief  DMA remapping enable/disable macros
00647   * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping
00648   */
00649 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__)   do {assert_param(IS_DMA_REMAP((__DMA_REMAP__)));                  \
00650                                                            SYSCFG->CFGR1 |= (__DMA_REMAP__);                                \
00651                                                          }while(0U)
00652 #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__)  do {assert_param(IS_DMA_REMAP((__DMA_REMAP__)));                  \
00653                                                            SYSCFG->CFGR1 &= ~(__DMA_REMAP__);                               \
00654                                                          }while(0U)
00655 #endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */
00656 /**
00657  * @}
00658  */
00659
00660 /** @defgroup FastModePlus_GPIO Fast-mode Plus on GPIO
00661   * @{
00662   */
00663 /** @brief  Fast-mode Plus driving capability enable/disable macros
00664   * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
00665   *                          That you can find above these macros.
00666   */
00667 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
00668                                                                 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
00669                                                                }while(0U)
00670
00671 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
00672                                                                 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
00673                                                                }while(0U)
00674 /**
00675  * @}
00676  */
00677
00678 /** @defgroup Floating_Point_Unit_Interrupts_Enable Floating Point Unit Interrupts Enable
00679   * @{
00680   */
00681 /** @brief  SYSCFG interrupt enable/disable macros
00682   * @param __INTERRUPT__ This parameter can be a value of @ref HAL_SYSCFG_Interrupts
00683   */
00684 #define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__)        do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
00685                                                                 SYSCFG->CFGR1 |= (__INTERRUPT__);                       \
00686                                                                }while(0U)
00687
00688 #define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__)       do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
00689                                                                 SYSCFG->CFGR1 &= ~(__INTERRUPT__);                      \
00690                                                                }while(0U)
00691 /**
00692  * @}
00693  */
00694
00695 #if defined(SYSCFG_CFGR1_USB_IT_RMP)
00696 /** @defgroup USB_Interrupt_Remap USB Interrupt Remap
00697   * @{
00698   */
00699 /** @brief  USB interrupt remapping enable/disable macros
00700   */
00701 #define __HAL_REMAPINTERRUPT_USB_ENABLE()              (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP))
00702 #define __HAL_REMAPINTERRUPT_USB_DISABLE()             (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP))
00703 /**
00704  * @}
00705  */
00706 #endif /* SYSCFG_CFGR1_USB_IT_RMP */
00707
00708 #if defined(SYSCFG_CFGR1_VBAT)
00709 /** @defgroup VBAT_Monitoring_Enable VBAT Monitoring Enable
00710   * @{
00711   */
00712 /** @brief  SYSCFG interrupt enable/disable macros
00713   */
00714 #define __HAL_SYSCFG_VBAT_MONITORING_ENABLE()          (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))
00715 #define __HAL_SYSCFG_VBAT_MONITORING_DISABLE()         (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT))
00716 /**
00717  * @}
00718  */
00719 #endif /* SYSCFG_CFGR1_VBAT */
00720
00721 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
00722 /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
00723   * @{
00724   */
00725 /** @brief  SYSCFG Break Lockup lock
00726   *         Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
00727   * @note   The selected configuration is locked and can be unlocked by system reset
00728   */
00729 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()   do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
00730                                                SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK;    \
00731                                               }while(0U)
00732 /**
00733  * @}
00734  */
00735 #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
00736
00737 #if defined(SYSCFG_CFGR2_PVD_LOCK)
00738 /** @defgroup PVD_Lock_Enable PVD Lock
00739   * @{
00740   */
00741 /** @brief  SYSCFG Break PVD lock
00742   *         Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
00743   * @note   The selected configuration is locked and can be unlocked by system reset
00744   */
00745 #define __HAL_SYSCFG_BREAK_PVD_LOCK()      do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
00746                                                SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK;    \
00747                                               }while(0U)
00748 /**
00749  * @}
00750  */
00751 #endif /* SYSCFG_CFGR2_PVD_LOCK */
00752
00753 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
00754 /** @defgroup SRAM_Parity_Lock SRAM Parity Lock
00755   * @{
00756   */
00757 /** @brief  SYSCFG Break SRAM PARITY lock
00758   *         Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
00759   * @note   The selected configuration is locked and can be unlocked by system reset
00760   */
00761 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
00762                                                  SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK;    \
00763                                                 }while(0U)
00764 /**
00765  * @}
00766  */
00767 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
00768
00769 /** @defgroup Trigger_Remapping_Enable Trigger Remapping Enable
00770   * @{
00771   */
00772 #if defined(SYSCFG_CFGR3_TRIGGER_RMP)
00773 /** @brief  Trigger remapping enable/disable macros
00774   * @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping
00775   */
00776 #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__)   do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__)));             \
00777                                                            (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ?                     \
00778                                                              (SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
00779                                                              (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)));                           \
00780                                                          }while(0U)
00781 #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__)  do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__)));             \
00782                                                            (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ?                     \
00783                                                              (SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
00784                                                              (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)));                          \
00785                                                          }while(0U)
00786 #else
00787 /** @brief  Trigger remapping enable/disable macros
00788   * @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping
00789   */
00790 #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__)   do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__)));             \
00791                                                            (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__));                           \
00792                                                          }while(0U)
00793 #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__)  do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__)));             \
00794                                                            (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__));                          \
00795                                                          }while(0U)
00796 #endif /* SYSCFG_CFGR3_TRIGGER_RMP */
00797 /**
00798  * @}
00799  */
00800
00801 #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
00802 /** @defgroup ADC_Trigger_Remapping_Enable ADC Trigger Remapping Enable
00803   * @{
00804   */
00805 /** @brief  ADC trigger remapping enable/disable macros
00806   * @param __ADCTRIGGER_REMAP__ This parameter can be a value of @ref HAL_ADC_Trigger_Remapping
00807   */
00808 #define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__)   do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__)));   \
00809                                                              (SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__));                          \
00810                                                          }while(0U)
00811 #define __HAL_REMAPADCTRIGGER_DISABLE(__ADCTRIGGER_REMAP__)  do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__)));   \
00812                                                              (SYSCFG->CFGR4 &= ~(__ADCTRIGGER_REMAP__));                         \
00813                                                          }while(0U)
00814 /**
00815  * @}
00816  */
00817 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
00818
00819 #if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
00820 /** @defgroup RAM_Parity_Check_Disable RAM Parity Check Disable
00821   * @{
00822   */
00823 /**
00824   * @brief  Parity check on RAM disable macro
00825   * @note   Disabling the parity check on RAM locks the configuration bit.
00826   *         To re-enable the parity check on RAM perform a system reset.
00827   */
00828 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE()         (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = 0x00000001U)
00829 /**
00830  * @}
00831  */
00832 #endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
00833
00834 #if defined(SYSCFG_RCR_PAGE0)
00835 /** @defgroup CCM_RAM_Page_Write_Protection_Enable CCM RAM page write protection enable
00836   * @{
00837   */
00838 /** @brief  CCM RAM page write protection enable macro
00839   * @param __PAGE_WP__ This parameter can be a value of @ref HAL_Page_Write_Protection
00840   * @note   write protection can only be disabled by a system reset
00841   */
00842 #define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__)      do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \
00843                                                            SYSCFG->RCR |= (__PAGE_WP__);                       \
00844                                                           }while(0U)
00845 /**
00846  * @}
00847  */
00848 #endif /* SYSCFG_RCR_PAGE0 */
00849
00850 /**
00851  * @}
00852  */
00853 /* Exported functions --------------------------------------------------------*/
00854 /** @addtogroup HAL_Exported_Functions HAL Exported Functions
00855   * @{
00856   */
00857
00858 /** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
00859  *  @brief    Initialization and de-initialization functions
00860  * @{
00861  */
00862 /* Initialization and de-initialization functions  ******************************/
00863 HAL_StatusTypeDef HAL_Init(void);
00864 HAL_StatusTypeDef HAL_DeInit(void);
00865 void HAL_MspInit(void);
00866 void HAL_MspDeInit(void);
00867 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
00868 /**
00869  * @}
00870  */
00871
00872 /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
00873  *  @brief    HAL Control functions
00874  * @{
00875  */
00876 /* Peripheral Control functions  ************************************************/
00877 void     HAL_IncTick(void);
00878 void     HAL_Delay(__IO uint32_t Delay);
00879 void     HAL_SuspendTick(void);
00880 void     HAL_ResumeTick(void);
00881 uint32_t HAL_GetTick(void);
00882 uint32_t HAL_GetHalVersion(void);
00883 uint32_t HAL_GetREVID(void);
00884 uint32_t HAL_GetDEVID(void);
00885 uint32_t HAL_GetUIDw0(void);
00886 uint32_t HAL_GetUIDw1(void);
00887 uint32_t HAL_GetUIDw2(void);
00888 void     HAL_DBGMCU_EnableDBGSleepMode(void);
00889 void     HAL_DBGMCU_DisableDBGSleepMode(void);
00890 void     HAL_DBGMCU_EnableDBGStopMode(void);
00891 void     HAL_DBGMCU_DisableDBGStopMode(void);
00892 void     HAL_DBGMCU_EnableDBGStandbyMode(void);
00893 void     HAL_DBGMCU_DisableDBGStandbyMode(void);
00894 /**
00895  * @}
00896  */
00897
00898 /**
00899  * @}
00900  */
00901
00902 /**
00903   * @}
00904   */
00905
00906 /**
00907   * @}
00908   */
00909
00910 #ifdef __cplusplus
00911 }
00912 #endif
00913
00914 #endif /* __STM32F3xx_HAL_H */
00915
00916 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_adc.c Source File

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stm32f3xx_hal_adc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_adc.c
00004   * @author  MCD Application Team
00005   * @brief   This file provides firmware functions to manage the following
00006   *          functionalities of the Analog to Digital Convertor (ADC)
00007   *          peripheral:
00008   *           + Initialization and de-initialization functions
00009   *             ++ Initialization and Configuration of ADC
00010   *           + Operation functions
00011   *             ++ Start, stop, get result of conversions of regular
00012   *                group, using 3 possible modes: polling, interruption or DMA.
00013   *           + Control functions
00014   *             ++ Channels configuration on regular group
00015   *             ++ Channels configuration on injected group
00016   *             ++ Analog Watchdog configuration
00017   *           + State functions
00018   *             ++ ADC state machine management
00019   *             ++ Interrupts and flags management
00020   *          Other functions (extended functions) are available in file
00021   *          "stm32f3xx_hal_adc_ex.c".
00022   *
00023   @verbatim
00024   ==============================================================================
00025                      ##### ADC peripheral features #####
00026   ==============================================================================
00027   [..]
00028   (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution (available only on
00029       STM32F30xxC devices).
00030
00031   (+) Interrupt generation at the end of regular conversion, end of injected
00032       conversion, and in case of analog watchdog or overrun events.
00033
00034   (+) Single and continuous conversion modes.
00035
00036   (+) Scan mode for conversion of several channels sequentially.
00037
00038   (+) Data alignment with in-built data coherency.
00039
00040   (+) Programmable sampling time (channel wise)
00041
00042   (+) ADC conversion of regular group and injected group.
00043
00044   (+) External trigger (timer or EXTI) with configurable polarity
00045       for both regular and injected groups.
00046
00047   (+) DMA request generation for transfer of conversions data of regular group.
00048
00049   (+) Multimode dual mode (available on devices with 2 ADCs or more).
00050
00051   (+) Configurable DMA data storage in Multimode Dual mode (available on devices
00052       with 2 DCs or more).
00053
00054   (+) Configurable delay between conversions in Dual interleaved mode (available
00055       on devices with 2 DCs or more).
00056
00057   (+) ADC calibration
00058
00059   (+) ADC channels selectable single/differential input (available only on
00060       STM32F30xxC devices)
00061
00062   (+) ADC Injected sequencer&channels configuration context queue (available
00063       only on STM32F30xxC devices)
00064
00065   (+) ADC offset on injected and regular groups (offset on regular group
00066       available only on STM32F30xxC devices)
00067
00068   (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
00069       slower speed.
00070
00071   (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
00072       Vdda or to an external voltage reference).
00073
00074
00075                      ##### How to use this driver #####
00076   ==============================================================================
00077     [..]
00078
00079      *** Configuration of top level parameters related to ADC ***
00080      ============================================================
00081      [..]
00082
00083     (#) Enable the ADC interface
00084       (++) As prerequisite, ADC clock must be configured at RCC top level.
00085
00086         (++) For STM32F30x/STM32F33x devices:
00087              Two possible clock sources: synchronous clock derived from AHB clock
00088              or asynchronous clock derived from ADC dedicated PLL 72MHz.
00089               - Synchronous clock is mandatory since used as ADC core clock.
00090                 Synchronous clock can be used optionally as ADC conversion clock, depending on ADC init structure clock setting.
00091                 Synchronous clock is configured using macro __ADCx_CLK_ENABLE().
00092               - Asynchronous can be used optionally as ADC conversion clock, depending on ADC init structure clock setting.
00093                 Asynchronous clock is configured using function HAL_RCCEx_PeriphCLKConfig().
00094              (+++) For example, in case of device with a single ADC:
00095                    Into HAL_ADC_MspInit() (recommended code location) or with
00096                    other device clock parameters configuration:
00097                (+++) __HAL_RCC_ADC1_CLK_ENABLE()                            (mandatory)
00098                (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if ADC conversion from asynchronous clock)
00099                (+++) PeriphClkInit.Adc1ClockSelection = RCC_ADC1PLLCLK_DIV1 (optional, if ADC conversion from asynchronous clock)
00100                (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if ADC conversion from asynchronous clock)
00101
00102              (+++) For example, in case of device with 4 ADCs:
00103
00104                (+++) if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
00105                (+++) {
00106                (+++)   __HAL_RCC_ADC12_CLK_ENABLE()                             (mandatory)
00107                (+++)   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC   (optional, if ADC conversion from asynchronous clock)
00108                (+++)   PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_DIV1 (optional, if ADC conversion from asynchronous clock)
00109                (+++)   HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure)   (optional, if ADC conversion from asynchronous clock)
00110                (+++) }
00111                (+++) else
00112                (+++) {
00113                (+++)   __HAL_RCC_ADC34_CLK_ENABLE()                              (mandatory)
00114                (+++)   PeriphClkInit.Adc34ClockSelection = RCC_ADC34PLLCLK_DIV1; (optional, if ADC conversion from asynchronous clock)
00115                (+++)   HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure);   (optional, if ADC conversion from asynchronous clock)
00116                (+++) }
00117
00118         (++) For STM32F37x devices:
00119              One clock setting is mandatory:
00120              ADC clock (core and conversion clock) from APB2 clock.
00121              (+++) Example:
00122                    Into HAL_ADC_MspInit() (recommended code location) or with
00123                    other device clock parameters configuration:
00124                (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
00125                (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK_DIV2
00126                (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)
00127
00128     (#) ADC pins configuration
00129          (++) Enable the clock for the ADC GPIOs
00130               using macro __HAL_RCC_GPIOx_CLK_ENABLE()
00131          (++) Configure these ADC pins in analog mode
00132               using function HAL_GPIO_Init()
00133
00134     (#) Optionally, in case of usage of ADC with interruptions:
00135          (++) Configure the NVIC for ADC
00136               using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
00137          (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
00138               into the function of corresponding ADC interruption vector
00139               ADCx_IRQHandler().
00140
00141     (#) Optionally, in case of usage of DMA:
00142          (++) Configure the DMA (DMA channel, mode normal or circular, ...)
00143               using function HAL_DMA_Init().
00144          (++) Configure the NVIC for DMA
00145               using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
00146          (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
00147               into the function of corresponding DMA interruption vector
00148               DMAx_Channelx_IRQHandler().
00149
00150      *** Configuration of ADC, groups regular/injected, channels parameters ***
00151      ==========================================================================
00152      [..]
00153
00154     (#) Configure the ADC parameters (resolution, data alignment, ...)
00155         and regular group parameters (conversion trigger, sequencer, ...)
00156         using function HAL_ADC_Init().
00157
00158     (#) Configure the channels for regular group parameters (channel number,
00159         channel rank into sequencer, ..., into regular group)
00160         using function HAL_ADC_ConfigChannel().
00161
00162     (#) Optionally, configure the injected group parameters (conversion trigger,
00163         sequencer, ..., of injected group)
00164         and the channels for injected group parameters (channel number,
00165         channel rank into sequencer, ..., into injected group)
00166         using function HAL_ADCEx_InjectedConfigChannel().
00167
00168     (#) Optionally, configure the analog watchdog parameters (channels
00169         monitored, thresholds, ...)
00170         using function HAL_ADC_AnalogWDGConfig().
00171
00172     (#) Optionally, for devices with several ADC instances: configure the
00173         multimode parameters
00174         using function HAL_ADCEx_MultiModeConfigChannel().
00175
00176      *** Execution of ADC conversions ***
00177      ====================================
00178      [..]
00179
00180     (#) Optionally, perform an automatic ADC calibration to improve the
00181         conversion accuracy
00182         using function HAL_ADCEx_Calibration_Start().
00183
00184     (#) ADC driver can be used among three modes: polling, interruption,
00185         transfer by DMA.
00186
00187         (++) ADC conversion by polling:
00188           (+++) Activate the ADC peripheral and start conversions
00189                 using function HAL_ADC_Start()
00190           (+++) Wait for ADC conversion completion
00191                 using function HAL_ADC_PollForConversion()
00192                 (or for injected group: HAL_ADCEx_InjectedPollForConversion() )
00193           (+++) Retrieve conversion results
00194                 using function HAL_ADC_GetValue()
00195                 (or for injected group: HAL_ADCEx_InjectedGetValue() )
00196           (+++) Stop conversion and disable the ADC peripheral
00197                 using function HAL_ADC_Stop()
00198
00199         (++) ADC conversion by interruption:
00200           (+++) Activate the ADC peripheral and start conversions
00201                 using function HAL_ADC_Start_IT()
00202           (+++) Wait for ADC conversion completion by call of function
00203                 HAL_ADC_ConvCpltCallback()
00204                 (this function must be implemented in user program)
00205                 (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
00206           (+++) Retrieve conversion results
00207                 using function HAL_ADC_GetValue()
00208                 (or for injected group: HAL_ADCEx_InjectedGetValue() )
00209           (+++) Stop conversion and disable the ADC peripheral
00210                 using function HAL_ADC_Stop_IT()
00211
00212         (++) ADC conversion with transfer by DMA:
00213           (+++) Activate the ADC peripheral and start conversions
00214                 using function HAL_ADC_Start_DMA()
00215           (+++) Wait for ADC conversion completion by call of function
00216                 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
00217                 (these functions must be implemented in user program)
00218           (+++) Conversion results are automatically transferred by DMA into
00219                 destination variable address.
00220           (+++) Stop conversion and disable the ADC peripheral
00221                 using function HAL_ADC_Stop_DMA()
00222
00223         (++) For devices with several ADCs: ADC multimode conversion
00224              with transfer by DMA:
00225           (+++) Activate the ADC peripheral (slave)
00226                 using function HAL_ADC_Start()
00227                 (conversion start pending ADC master)
00228           (+++) Activate the ADC peripheral (master) and start conversions
00229                 using function HAL_ADCEx_MultiModeStart_DMA()
00230           (+++) Wait for ADC conversion completion by call of function
00231                 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
00232                 (these functions must be implemented in user program)
00233           (+++) Conversion results are automatically transferred by DMA into
00234                 destination variable address.
00235           (+++) Stop conversion and disable the ADC peripheral (master)
00236                 using function HAL_ADCEx_MultiModeStop_DMA()
00237           (+++) Stop conversion and disable the ADC peripheral (slave)
00238                 using function HAL_ADC_Stop_IT()
00239
00240      [..]
00241
00242     (@) Callback functions must be implemented in user program:
00243       (+@) HAL_ADC_ErrorCallback()
00244       (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
00245       (+@) HAL_ADC_ConvCpltCallback()
00246       (+@) HAL_ADC_ConvHalfCpltCallback
00247       (+@) HAL_ADCEx_InjectedConvCpltCallback()
00248       (+@) HAL_ADCEx_InjectedQueueOverflowCallback() (for STM32F30x/STM32F33x devices)
00249
00250      *** Deinitialization of ADC ***
00251      ============================================================
00252      [..]
00253
00254     (#) Disable the ADC interface
00255       (++) ADC clock can be hard reset and disabled at RCC top level.
00256         (++) Hard reset of ADC peripherals
00257              using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
00258         (++) ADC clock disable
00259              using the equivalent macro/functions as configuration step.
00260
00261         (++) For STM32F30x/STM32F33x devices:
00262            Caution: For devices with several ADCs:
00263            These settings impact both ADC of common group: ADC1&ADC2, ADC3&ADC4
00264            if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
00265
00266              (+++) For example, in case of device with a single ADC:
00267                    Into HAL_ADC_MspDeInit() (recommended code location) or with
00268                    other device clock parameters configuration:
00269                (+++) __HAL_RCC_ADC1_FORCE_RESET()                           (optional)
00270                (+++) __HAL_RCC_ADC1_RELEASE_RESET()                         (optional)
00271                (+++) __HAL_RCC_ADC1_CLK_DISABLE()                           (mandatory)
00272                (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if configured before)
00273                (+++) PeriphClkInit.Adc1ClockSelection = RCC_ADC1PLLCLK_OFF  (optional, if configured before)
00274                (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if configured before)
00275
00276              (+++) For example, in case of device with 4 ADCs:
00277                (+++) if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
00278                (+++) {
00279                (+++)   __HAL_RCC_ADC12_FORCE_RESET()                            (optional)
00280                (+++)   __HAL_RCC_ADC12_RELEASE_RESET()                          (optional)
00281                (+++)   __HAL_RCC_ADC12_CLK_DISABLE()                            (mandatory)
00282                (+++)   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC   (optional, if configured before)
00283                (+++)   PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_OFF  (optional, if configured before)
00284                (+++)   HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure)   (optional, if configured before)
00285                (+++) }
00286                (+++) else
00287                (+++) {
00288                (+++)   __HAL_RCC_ADC32_FORCE_RESET()                            (optional)
00289                (+++)   __HAL_RCC_ADC32_RELEASE_RESET()                          (optional)
00290                (+++)   __HAL_RCC_ADC34_CLK_DISABLE()                            (mandatory)
00291                (+++)   PeriphClkInit.Adc34ClockSelection = RCC_ADC34PLLCLK_OFF  (optional, if configured before)
00292                (+++)   HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure)   (optional, if configured before)
00293                (+++) }
00294
00295         (++) For STM32F37x devices:
00296              (+++) Example:
00297                    Into HAL_ADC_MspDeInit() (recommended code location) or with
00298                    other device clock parameters configuration:
00299                (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
00300                (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK_OFF
00301                (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)
00302
00303     (#) ADC pins configuration
00304          (++) Disable the clock for the ADC GPIOs
00305               using macro __HAL_RCC_GPIOx_CLK_DISABLE()
00306
00307     (#) Optionally, in case of usage of ADC with interruptions:
00308          (++) Disable the NVIC for ADC
00309               using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
00310
00311     (#) Optionally, in case of usage of DMA:
00312          (++) Deinitialize the DMA
00313               using function HAL_DMA_Init().
00314          (++) Disable the NVIC for DMA
00315               using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
00316
00317     [..]
00318
00319     @endverbatim
00320   ******************************************************************************
00321   * @attention
00322   *
00323   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00324   *
00325   * Redistribution and use in source and binary forms, with or without modification,
00326   * are permitted provided that the following conditions are met:
00327   *   1. Redistributions of source code must retain the above copyright notice,
00328   *      this list of conditions and the following disclaimer.
00329   *   2. Redistributions in binary form must reproduce the above copyright notice,
00330   *      this list of conditions and the following disclaimer in the documentation
00331   *      and/or other materials provided with the distribution.
00332   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00333   *      may be used to endorse or promote products derived from this software
00334   *      without specific prior written permission.
00335   *
00336   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00337   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00338   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00339   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00340   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00341   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00342   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00343   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00344   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00345   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00346   *
00347   ******************************************************************************
00348   */
00349
00350 /* Includes ------------------------------------------------------------------*/
00351 #include "stm32f3xx_hal.h"
00352
00353 /** @addtogroup STM32F3xx_HAL_Driver
00354   * @{
00355   */
00356
00357 /** @defgroup ADC ADC
00358   * @brief ADC HAL module driver
00359   * @{
00360   */
00361
00362 #ifdef HAL_ADC_MODULE_ENABLED
00363
00364 /* Private typedef -----------------------------------------------------------*/
00365 /* Private define ------------------------------------------------------------*/
00366 /* Private macro -------------------------------------------------------------*/
00367 /* Private variables ---------------------------------------------------------*/
00368 /* Private function prototypes -----------------------------------------------*/
00369 /* Exported functions --------------------------------------------------------*/
00370
00371 /** @defgroup ADC_Exported_Functions ADC Exported Functions
00372   * @{
00373   */
00374
00375 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
00376  *  @brief    Initialization and Configuration functions
00377  *
00378 @verbatim
00379  ===============================================================================
00380               ##### Initialization and de-initialization functions #####
00381  ===============================================================================
00382     [..]  This section provides functions allowing to:
00383       (+) Initialize and configure the ADC.
00384       (+) De-initialize the ADC.
00385
00386 @endverbatim
00387   * @{
00388   */
00389
00390 /**
00391   * @brief  Initializes the ADC peripheral and regular group according to
00392   *         parameters specified in structure "ADC_InitTypeDef".
00393   * @note   As prerequisite, ADC clock must be configured at RCC top level
00394   *         depending on both possible clock sources: PLL clock or AHB clock.
00395   *         See commented example code below that can be copied and uncommented
00396   *         into HAL_ADC_MspInit().
00397   * @note   Possibility to update parameters on the fly:
00398   *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
00399   *         coming from ADC state reset. Following calls to this function can
00400   *         be used to reconfigure some parameters of ADC_InitTypeDef
00401   *         structure on the fly, without modifying MSP configuration. If ADC
00402   *         MSP has to be modified again, HAL_ADC_DeInit() must be called
00403   *         before HAL_ADC_Init().
00404   *         The setting of these parameters is conditioned to ADC state.
00405   *         For parameters constraints, see comments of structure
00406   *         "ADC_InitTypeDef".
00407   * @note   This function configures the ADC within 2 scopes: scope of entire
00408   *         ADC and scope of regular group. For parameters details, see comments
00409   *         of structure "ADC_InitTypeDef".
00410   * @note   For devices with several ADCs: parameters related to common ADC
00411   *         registers (ADC clock mode) are set only if all ADCs sharing the
00412   *         same common group are disabled.
00413   *         If this is not the case, these common parameters setting are
00414   *         bypassed without error reporting: it can be the intended behaviour in
00415   *         case of update of a parameter of ADC_InitTypeDef on the fly,
00416   *         without  disabling the other ADCs sharing the same common group.
00417   * @param  hadc ADC handle
00418   * @retval HAL status
00419   */
00420 __weak HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
00421 {
00422   /* Prevent unused argument(s) compilation warning */
00423   UNUSED(hadc);
00424
00425   /* Note : This function is defined into this file for library reference. */
00426   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
00427
00428   /* Return function status */
00429   return HAL_ERROR;
00430 }
00431
00432 /**
00433   * @brief  Deinitialize the ADC peripheral registers to their default reset
00434   *         values, with deinitialization of the ADC MSP.
00435   * @note   For devices with several ADCs: reset of ADC common registers is done
00436   *         only if all ADCs sharing the same common group are disabled.
00437   *         If this is not the case, reset of these common parameters reset is
00438   *         bypassed without error reporting: it can be the intended behaviour in
00439   *         case of reset of a single ADC while the other ADCs sharing the same
00440   *         common group is still running.
00441   * @note   For devices with several ADCs: Global reset of all ADCs sharing a
00442   *         common group is possible.
00443   *         As this function is intended to reset a single ADC, to not impact
00444   *         other ADCs, instructions for global reset of multiple ADCs have been
00445   *         let commented below.
00446   *         If needed, the example code can be copied and uncommented into
00447   *         function HAL_ADC_MspDeInit().
00448   * @param  hadc ADC handle
00449   * @retval HAL status
00450   */
00451 __weak HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
00452 {
00453   /* Prevent unused argument(s) compilation warning */
00454   UNUSED(hadc);
00455
00456   /* Note : This function is defined into this file for library reference. */
00457   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
00458
00459   /* Return function status */
00460   return HAL_ERROR;
00461 }
00462
00463 /**
00464   * @brief  Initializes the ADC MSP.
00465   * @param  hadc ADC handle
00466   * @retval None
00467   */
00468 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
00469 {
00470   /* Prevent unused argument(s) compilation warning */
00471   UNUSED(hadc);
00472
00473   /* NOTE : This function should not be modified. When the callback is needed,
00474             function HAL_ADC_MspInit must be implemented in the user file.
00475    */
00476 }
00477
00478 /**
00479   * @brief  DeInitializes the ADC MSP.
00480   * @param  hadc ADC handle
00481   * @retval None
00482   */
00483 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
00484 {
00485   /* Prevent unused argument(s) compilation warning */
00486   UNUSED(hadc);
00487
00488   /* NOTE : This function should not be modified. When the callback is needed,
00489             function HAL_ADC_MspDeInit must be implemented in the user file.
00490    */
00491 }
00492
00493 /**
00494   * @}
00495   */
00496
00497 /** @defgroup ADC_Exported_Functions_Group2 Input and Output operation functions
00498  *  @brief    IO operation functions
00499  *
00500 @verbatim
00501  ===============================================================================
00502              ##### IO operation functions #####
00503  ===============================================================================
00504     [..]  This section provides functions allowing to:
00505       (+) Start conversion of regular group.
00506       (+) Stop conversion of regular group.
00507       (+) Poll for conversion complete on regular group.
00508       (+) Poll for conversion event.
00509       (+) Get result of regular channel conversion.
00510       (+) Start conversion of regular group and enable interruptions.
00511       (+) Stop conversion of regular group and disable interruptions.
00512       (+) Handle ADC interrupt request
00513       (+) Start conversion of regular group and enable DMA transfer.
00514       (+) Stop conversion of regular group and disable ADC DMA transfer.
00515
00516 @endverbatim
00517   * @{
00518   */
00519 /**
00520   * @brief  Enables ADC, starts conversion of regular group.
00521   *         Interruptions enabled in this function: None.
00522   * @note:  Case of multimode enabled (for devices with several ADCs): This
00523   *         function must be called for ADC slave first, then ADC master.
00524   *         For ADC slave, ADC is enabled only (conversion is not started).
00525   *         For ADC master, ADC is enabled and multimode conversion is started.
00526   * @param  hadc ADC handle
00527   * @retval HAL status
00528   */
00529 __weak HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
00530 {
00531   /* Prevent unused argument(s) compilation warning */
00532   UNUSED(hadc);
00533
00534   /* Return function status */
00535   return HAL_ERROR;
00536 }
00537
00538 /**
00539   * @brief  Stop ADC conversion of regular group (and injected group in
00540   *         case of auto_injection mode), disable ADC peripheral.
00541   * @note:  ADC peripheral disable is forcing stop of potential
00542   *         conversion on injected group. If injected group is under use, it
00543   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
00544   * @note:  Case of multimode enabled (for devices with several ADCs): This
00545   *         function must be called for ADC master first, then ADC slave.
00546   *         For ADC master, converson is stopped and ADC is disabled.
00547   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
00548   *         has already stopped conversion of ADC slave).
00549   * @param  hadc ADC handle
00550   * @retval HAL status.
00551   */
00552 __weak HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
00553 {
00554   /* Prevent unused argument(s) compilation warning */
00555   UNUSED(hadc);
00556
00557   /* Note : This function is defined into this file for library reference. */
00558   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
00559
00560   /* Return function status */
00561   return HAL_ERROR;
00562 }
00563
00564 /**
00565   * @brief  Wait for regular group conversion to be completed.
00566   * @param  hadc ADC handle
00567   * @param  Timeout Timeout value in millisecond.
00568   * @retval HAL status
00569   */
00570 __weak HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
00571 {
00572   /* Prevent unused argument(s) compilation warning */
00573   UNUSED(hadc);
00574   UNUSED(Timeout);
00575
00576   /* Note : This function is defined into this file for library reference. */
00577   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
00578
00579   /* Return function status */
00580   return HAL_ERROR;
00581 }
00582
00583 /**
00584   * @brief  Poll for conversion event.
00585   * @param  hadc ADC handle
00586   * @param  EventType the ADC event type.
00587   *          This parameter can be one of the following values:
00588   *            @arg ADC_AWD_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
00589   *            @arg ADC_AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, present only on STM32F3 devices)
00590   *            @arg ADC_AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, present only on STM32F3 devices)
00591   *            @arg ADC_OVR_EVENT: ADC Overrun event
00592   *            @arg ADC_JQOVF_EVENT: ADC Injected context queue overflow event
00593   * @param  Timeout Timeout value in millisecond.
00594   * @retval HAL status
00595   */
00596 __weak HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
00597 {
00598   /* Prevent unused argument(s) compilation warning */
00599   UNUSED(hadc);
00600   UNUSED(EventType);
00601   UNUSED(Timeout);
00602
00603   /* Note : This function is defined into this file for library reference. */
00604   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
00605
00606   /* Return function status */
00607   return HAL_ERROR;
00608 }
00609
00610 /**
00611   * @brief  Enables ADC, starts conversion of regular group with interruption.
00612   *         Interruptions enabled in this function:
00613   *          - EOC (end of conversion of regular group) or EOS (end of
00614   *            sequence of regular group) depending on ADC initialization
00615   *            parameter "EOCSelection" (if available)
00616   *          - overrun (if available)
00617   *         Each of these interruptions has its dedicated callback function.
00618   * @note:  Case of multimode enabled (for devices with several ADCs): This
00619   *         function must be called for ADC slave first, then ADC master.
00620   *         For ADC slave, ADC is enabled only (conversion is not started).
00621   *         For ADC master, ADC is enabled and multimode conversion is started.
00622   * @param  hadc ADC handle
00623   * @retval HAL status
00624   */
00625 __weak HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
00626 {
00627   /* Prevent unused argument(s) compilation warning */
00628   UNUSED(hadc);
00629
00630   /* Note : This function is defined into this file for library reference. */
00631   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
00632
00633   /* Return function status */
00634   return HAL_ERROR;
00635 }
00636
00637 /**
00638   * @brief  Stop ADC conversion of regular group (and injected group in
00639   *         case of auto_injection mode), disable interruption of
00640   *         end-of-conversion, disable ADC peripheral.
00641   * @note:  ADC peripheral disable is forcing stop of potential
00642   *         conversion on injected group. If injected group is under use, it
00643   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
00644   * @note:  Case of multimode enabled (for devices with several ADCs): This
00645   *         function must be called for ADC master first, then ADC slave.
00646   *         For ADC master, conversion is stopped and ADC is disabled.
00647   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
00648   *         has already stopped conversion of ADC slave).
00649   * @param  hadc ADC handle
00650   * @retval HAL status.
00651   */
00652 __weak HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
00653 {
00654   /* Prevent unused argument(s) compilation warning */
00655   UNUSED(hadc);
00656
00657   /* Note : This function is defined into this file for library reference. */
00658   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
00659
00660   /* Return function status */
00661   return HAL_ERROR;
00662 }
00663
00664 /**
00665   * @brief  Enables ADC, starts conversion of regular group and transfers result
00666   *         through DMA.
00667   *         Interruptions enabled in this function:
00668   *          - DMA transfer complete
00669   *          - DMA half transfer
00670   *          - overrun (if available)
00671   *         Each of these interruptions has its dedicated callback function.
00672   * @note:  Case of multimode enabled (for devices with several ADCs): This
00673   *         function is for single-ADC mode only. For multimode, use the
00674   *         dedicated MultimodeStart function.
00675   * @param  hadc ADC handle
00676   * @param  pData The destination Buffer address.
00677   * @param  Length The length of data to be transferred from ADC peripheral to memory.
00678   * @retval None
00679   */
00680 __weak HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
00681 {
00682   /* Prevent unused argument(s) compilation warning */
00683   UNUSED(hadc);
00684   UNUSED(pData);
00685   UNUSED(Length);
00686
00687   /* Note : This function is defined into this file for library reference. */
00688   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
00689
00690   /* Return function status */
00691   return HAL_ERROR;
00692 }
00693
00694 /**
00695   * @brief  Stop ADC conversion of regular group (and injected group in
00696   *         case of auto_injection mode), disable ADC DMA transfer, disable
00697   *         ADC peripheral.
00698   * @note:  ADC peripheral disable is forcing stop of potential
00699   *         conversion on injected group. If injected group is under use, it
00700   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
00701   * @note:  Case of multimode enabled (for devices with several ADCs): This
00702   *         function is for single-ADC mode only. For multimode, use the
00703   *         dedicated MultimodeStop function.
00704   * @param  hadc ADC handle
00705   * @retval HAL status.
00706   */
00707 __weak HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
00708 {
00709   /* Prevent unused argument(s) compilation warning */
00710   UNUSED(hadc);
00711
00712   /* Note : This function is defined into this file for library reference. */
00713   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
00714
00715   /* Return function status */
00716   return HAL_ERROR;
00717 }
00718
00719 /**
00720   * @brief  Get ADC regular group conversion result.
00721   * @note   Reading DR register automatically clears EOC (end of conversion of
00722   *         regular group) flag.
00723   *         Additionally, this functions clears EOS (end of sequence of
00724   *         regular group) flag, in case of the end of the sequence is reached.
00725   * @param  hadc ADC handle
00726   * @retval Converted value
00727   */
00728 __weak uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
00729 {
00730   /* Note : This function is defined into this file for library reference. */
00731   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
00732
00733   /* Return ADC converted value */
00734   return hadc->Instance->DR;
00735 }
00736
00737 /**
00738   * @brief  Handles ADC interrupt request.
00739   * @param  hadc ADC handle
00740   * @retval None
00741   */
00742 __weak void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
00743 {
00744   /* Prevent unused argument(s) compilation warning */
00745   UNUSED(hadc);
00746
00747   /* Note : This function is defined into this file for library reference. */
00748   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
00749 }
00750
00751 /**
00752   * @brief  Conversion complete callback in non blocking mode
00753   * @param  hadc ADC handle
00754   * @retval None
00755   */
00756 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
00757 {
00758   /* Prevent unused argument(s) compilation warning */
00759   UNUSED(hadc);
00760
00761   /* NOTE : This function should not be modified. When the callback is needed,
00762             function HAL_ADC_ConvCpltCallback must be implemented in the user file.
00763    */
00764 }
00765
00766 /**
00767   * @brief  Conversion DMA half-transfer callback in non blocking mode
00768   * @param  hadc ADC handle
00769   * @retval None
00770   */
00771 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
00772 {
00773   /* Prevent unused argument(s) compilation warning */
00774   UNUSED(hadc);
00775
00776   /* NOTE : This function should not be modified. When the callback is needed,
00777             function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
00778   */
00779 }
00780
00781 /**
00782   * @brief  Analog watchdog callback in non blocking mode.
00783   * @param  hadc ADC handle
00784   * @retval None
00785   */
00786 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
00787 {
00788   /* Prevent unused argument(s) compilation warning */
00789   UNUSED(hadc);
00790
00791   /* NOTE : This function should not be modified. When the callback is needed,
00792             function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file.
00793   */
00794 }
00795
00796 /**
00797   * @brief  ADC error callback in non blocking mode
00798   *        (ADC conversion with interruption or transfer by DMA)
00799   * @param  hadc ADC handle
00800   * @retval None
00801   */
00802 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
00803 {
00804   /* Prevent unused argument(s) compilation warning */
00805   UNUSED(hadc);
00806
00807   /* NOTE : This function should not be modified. When the callback is needed,
00808             function HAL_ADC_ErrorCallback must be implemented in the user file.
00809   */
00810 }
00811
00812 /**
00813   * @}
00814   */
00815
00816 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
00817  *  @brief    Peripheral Control functions
00818  *
00819 @verbatim
00820  ===============================================================================
00821              ##### Peripheral Control functions #####
00822  ===============================================================================
00823     [..]  This section provides functions allowing to:
00824       (+) Configure channels on regular group
00825       (+) Configure the analog watchdog
00826
00827 @endverbatim
00828   * @{
00829   */
00830
00831 /**
00832   * @brief  Configures the the selected channel to be linked to the regular
00833   *         group.
00834   * @note   In case of usage of internal measurement channels:
00835   *         Vbat/VrefInt/TempSensor.
00836   *         The recommended sampling time is at least:
00837   *          - For devices STM32F37x: 17.1us for temperature sensor
00838   *          - For the other STM32F3 devices: 2.2us for each of channels
00839   *            Vbat/VrefInt/TempSensor.
00840   *         These internal paths can be be disabled using function
00841   *         HAL_ADC_DeInit().
00842   * @note   Possibility to update parameters on the fly:
00843   *         This function initializes channel into regular group, following
00844   *         calls to this function can be used to reconfigure some parameters
00845   *         of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
00846   *         the ADC.
00847   *         The setting of these parameters is conditioned to ADC state.
00848   *         For parameters constraints, see comments of structure
00849   *         "ADC_ChannelConfTypeDef".
00850   * @param  hadc ADC handle
00851   * @param  sConfig Structure of ADC channel for regular group.
00852   * @retval HAL status
00853   */
00854 __weak HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
00855 {
00856   /* Prevent unused argument(s) compilation warning */
00857   UNUSED(hadc);
00858   UNUSED(sConfig);
00859
00860   /* Note : This function is defined into this file for library reference. */
00861   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
00862
00863   /* Return function status */
00864   return HAL_ERROR;
00865 }
00866
00867 /**
00868   * @brief  Configures the analog watchdog.
00869   * @note   Possibility to update parameters on the fly:
00870   *         This function initializes the selected analog watchdog, following
00871   *         calls to this function can be used to reconfigure some parameters
00872   *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
00873   *         the ADC.
00874   *         The setting of these parameters is conditioned to ADC state.
00875   *         For parameters constraints, see comments of structure
00876   *         "ADC_AnalogWDGConfTypeDef".
00877   * @param  hadc ADC handle
00878   * @param  AnalogWDGConfig Structure of ADC analog watchdog configuration
00879   * @retval HAL status
00880   */
00881 __weak HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
00882 {
00883   /* Prevent unused argument(s) compilation warning */
00884   UNUSED(hadc);
00885   UNUSED(AnalogWDGConfig);
00886
00887   /* Note : This function is defined into this file for library reference. */
00888   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
00889
00890   /* Return function status */
00891   return HAL_ERROR;
00892 }
00893
00894 /**
00895   * @}
00896   */
00897
00898 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
00899  *  @brief   ADC Peripheral State functions
00900  *
00901 @verbatim
00902  ===============================================================================
00903             ##### Peripheral state and errors functions #####
00904  ===============================================================================
00905     [..]
00906     This subsection provides functions to get in run-time the status of the
00907     peripheral.
00908       (+) Check the ADC state
00909       (+) Check the ADC error code
00910
00911 @endverbatim
00912   * @{
00913   */
00914
00915 /**
00916   * @brief  return the ADC state
00917   * @note   ADC state machine is managed by bitfield, state must be compared
00918   *         with bit by bit.
00919   *         For example:
00920   *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
00921   *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)    ) "
00922   * @param  hadc ADC handle
00923   * @retval HAL state
00924   */
00925 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
00926 {
00927   /* Check the parameters */
00928   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00929
00930   /* Return ADC state */
00931   return hadc->State;
00932 }
00933
00934 /**
00935   * @brief  Return the ADC error code
00936   * @param  hadc ADC handle
00937   * @retval ADC Error Code
00938   */
00939 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
00940 {
00941   return hadc->ErrorCode;
00942 }
00943
00944 /**
00945   * @}
00946   */
00947
00948 /**
00949   * @}
00950   */
00951
00952 #endif /* HAL_ADC_MODULE_ENABLED */
00953 /**
00954   * @}
00955   */
00956
00957 /**
00958   * @}
00959   */
00960
00961 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_adc.h Source File

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stm32f3xx_hal_adc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_adc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file containing functions prototypes of ADC HAL library.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_ADC_H
00038 #define __STM32F3xx_ADC_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /* Include ADC HAL Extended module */
00048 /* (include on top of file since ADC structures are defined in extended file) */
00049 #include "stm32f3xx_hal_adc_ex.h"
00050
00051 /** @addtogroup STM32F3xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @addtogroup ADC
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /** @defgroup ADC_Exported_Types ADC Exported Types
00061   * @{
00062   */
00063 /**
00064   * @brief  HAL ADC state machine: ADC states definition (bitfields)
00065   * @note   ADC state machine is managed by bitfields, state must be compared
00066   *         with bit by bit.
00067   *         For example:
00068   *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
00069   *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)    ) "
00070   */
00071 /* States of ADC global scope */
00072 #define HAL_ADC_STATE_RESET             (0x00000000U)    /*!< ADC not yet initialized or disabled */
00073 #define HAL_ADC_STATE_READY             (0x00000001U)    /*!< ADC peripheral ready for use */
00074 #define HAL_ADC_STATE_BUSY_INTERNAL     (0x00000002U)    /*!< ADC is busy to internal process (initialization, calibration) */
00075 #define HAL_ADC_STATE_TIMEOUT           (0x00000004U)    /*!< TimeOut occurrence */
00076
00077 /* States of ADC errors */
00078 #define HAL_ADC_STATE_ERROR_INTERNAL    (0x00000010U)    /*!< Internal error occurrence */
00079 #define HAL_ADC_STATE_ERROR_CONFIG      (0x00000020U)    /*!< Configuration error occurrence */
00080 #define HAL_ADC_STATE_ERROR_DMA         (0x00000040U)    /*!< DMA error occurrence */
00081
00082 /* States of ADC group regular */
00083 #define HAL_ADC_STATE_REG_BUSY          (0x00000100U)    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
00084                                                                        external trigger, low power auto power-on, multimode ADC master control) */
00085 #define HAL_ADC_STATE_REG_EOC           (0x00000200U)    /*!< Conversion data available on group regular */
00086 #define HAL_ADC_STATE_REG_OVR           (0x00000400U)    /*!< Overrun occurrence */
00087 #define HAL_ADC_STATE_REG_EOSMP         (0x00000800U)    /*!< End Of Sampling flag raised  */
00088
00089 /* States of ADC group injected */
00090 #define HAL_ADC_STATE_INJ_BUSY          (0x00001000U)    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
00091                                                                        external trigger, low power auto power-on, multimode ADC master control) */
00092 #define HAL_ADC_STATE_INJ_EOC           (0x00002000U)    /*!< Conversion data available on group injected */
00093 #define HAL_ADC_STATE_INJ_JQOVF         (0x00004000U)    /*!< Injected queue overflow occurrence */
00094
00095 /* States of ADC analog watchdogs */
00096 #define HAL_ADC_STATE_AWD1              (0x00010000U)    /*!< Out-of-window occurrence of analog watchdog 1 */
00097 #define HAL_ADC_STATE_AWD2              (0x00020000U)    /*!< Out-of-window occurrence of analog watchdog 2 */
00098 #define HAL_ADC_STATE_AWD3              (0x00040000U)    /*!< Out-of-window occurrence of analog watchdog 3 */
00099
00100 /* States of ADC multi-mode */
00101 #define HAL_ADC_STATE_MULTIMODE_SLAVE   (0x00100000U)    /*!< ADC in multimode slave state, controlled by another ADC master ( */
00102
00103
00104 /**
00105   * @brief  ADC handle Structure definition
00106   */
00107 typedef struct __ADC_HandleTypeDef
00108 {
00109   ADC_TypeDef                   *Instance;              /*!< Register base address */
00110
00111   ADC_InitTypeDef               Init;                   /*!< ADC required parameters */
00112
00113   DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
00114
00115   HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
00116
00117   __IO uint32_t                 State;                  /*!< ADC communication state (bitmap of ADC states) */
00118
00119   __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
00120
00121 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00122     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00123     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00124     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00125   ADC_InjectionConfigTypeDef    InjectionConfig ;       /*!< ADC injected channel configuration build-up structure */
00126 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00127        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00128        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00129        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00130
00131 }ADC_HandleTypeDef;
00132 /**
00133   * @}
00134   */
00135
00136 /* Exported constants --------------------------------------------------------*/
00137 /* Exported macros -----------------------------------------------------------*/
00138
00139 /** @defgroup ADC_Exported_Macro ADC Exported Macros
00140   * @{
00141   */
00142 /** @brief  Reset ADC handle state
00143   * @param  __HANDLE__ ADC handle
00144   * @retval None
00145   */
00146 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
00147
00148 /**
00149   * @}
00150   */
00151
00152
00153
00154 /* Exported functions --------------------------------------------------------*/
00155 /** @addtogroup ADC_Exported_Functions ADC Exported Functions
00156   * @{
00157   */
00158
00159 /** @addtogroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
00160  * @{
00161  */
00162 /* Initialization and de-initialization functions  **********************************/
00163 HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef* hadc);
00164 HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
00165 void                    HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
00166 void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
00167 /**
00168   * @}
00169   */
00170
00171 /** @addtogroup ADC_Exported_Functions_Group2 Input and Output operation functions
00172  * @{
00173  */
00174 /* Blocking mode: Polling */
00175 HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef* hadc);
00176 HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
00177 HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
00178 HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
00179
00180 /* Non-blocking mode: Interruption */
00181 HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
00182 HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
00183
00184 /* Non-blocking mode: DMA */
00185 HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
00186 HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
00187
00188 /* ADC retrieve conversion value intended to be used with polling or interruption */
00189 uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
00190
00191 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
00192 void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
00193 void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
00194 void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
00195 void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
00196 void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
00197 /**
00198   * @}
00199   */
00200
00201 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
00202  * @{
00203  */
00204 /* Peripheral Control functions ***********************************************/
00205 HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
00206 HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
00212  *  @brief   ADC Peripheral State functions
00213  * @{
00214  */
00215 /* Peripheral State functions *************************************************/
00216 uint32_t                HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
00217 uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
00218 /**
00219   * @}
00220   */
00221
00222 /**
00223   * @}
00224   */
00225
00226 /**
00227   * @}
00228   */
00229
00230 /**
00231   * @}
00232   */
00233
00234 #ifdef __cplusplus
00235 }
00236 #endif
00237
00238 #endif /*__STM32F3xx_ADC_H */
00239
00240
00241 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_adc_ex.c Source File

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stm32f3xx_hal_adc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_adc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   This file provides firmware functions to manage the following
00006   *          functionalities of the Analog to Digital Convertor (ADC)
00007   *          peripheral:
00008   *           + Operation functions
00009   *             ++ Start, stop, get result of conversions of injected
00010   *                group, using 2 possible modes: polling, interruption.
00011   *             ++ Multimode feature (available on devices with 2 ADCs or more)
00012   *             ++ Calibration (ADC automatic self-calibration)
00013   *           + Control functions
00014   *             ++ Channels configuration on injected group
00015   *          Other functions (generic functions) are available in file
00016   *          "stm32f3xx_hal_adc.c".
00017   *
00018   @verbatim
00019   [..]
00020   (@) Sections "ADC peripheral features" and "How to use this driver" are
00021       available in file of generic functions "stm32f3xx_hal_adc.c".
00022   [..]
00023   @endverbatim
00024   ******************************************************************************
00025   * @attention
00026   *
00027   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00028   *
00029   * Redistribution and use in source and binary forms, with or without modification,
00030   * are permitted provided that the following conditions are met:
00031   *   1. Redistributions of source code must retain the above copyright notice,
00032   *      this list of conditions and the following disclaimer.
00033   *   2. Redistributions in binary form must reproduce the above copyright notice,
00034   *      this list of conditions and the following disclaimer in the documentation
00035   *      and/or other materials provided with the distribution.
00036   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00037   *      may be used to endorse or promote products derived from this software
00038   *      without specific prior written permission.
00039   *
00040   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00041   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00042   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00043   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00044   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00045   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00046   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00047   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00048   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00049   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00050   *
00051   ******************************************************************************
00052   */
00053
00054 /* Includes ------------------------------------------------------------------*/
00055 #include "stm32f3xx_hal.h"
00056
00057 /** @addtogroup STM32F3xx_HAL_Driver
00058   * @{
00059   */
00060
00061 /** @defgroup ADCEx ADCEx
00062   * @brief ADC Extended HAL module driver
00063   * @{
00064   */
00065
00066 #ifdef HAL_ADC_MODULE_ENABLED
00067
00068 /* Private typedef -----------------------------------------------------------*/
00069 /* Private define ------------------------------------------------------------*/
00070 /** @defgroup ADCEx_Private_Constants ADCEx Private Constants
00071   * @{
00072   */
00073 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00074     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00075     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00076     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00077   /* Fixed timeout values for ADC calibration, enable settling time, disable  */
00078   /* settling time.                                                           */
00079   /* Values defined to be higher than worst cases: low clock frequency,       */
00080   /* maximum prescalers.                                                      */
00081   /* Ex of profile low frequency : Clock source at 0.5 MHz, ADC clock         */
00082   /* prescaler 256 (devices STM32F30xx), sampling time 7.5 ADC clock cycles,  */
00083   /* resolution 12 bits.                                                      */
00084   /* Unit: ms                                                                 */
00085   #define ADC_CALIBRATION_TIMEOUT         ( 10U)
00086   #define ADC_ENABLE_TIMEOUT              (  2U)
00087   #define ADC_DISABLE_TIMEOUT             (  2U)
00088   #define ADC_STOP_CONVERSION_TIMEOUT     ( 11U)
00089
00090   /* Timeout to wait for current conversion on going to be completed.         */
00091   /* Timeout fixed to worst case, for 1 channel.                              */
00092   /*   - maximum sampling time (601.5 adc_clk)                                */
00093   /*   - ADC resolution (Tsar 12 bits= 12.5 adc_clk)                          */
00094   /*   - ADC clock (from PLL with prescaler 256 (devices STM32F30xx))         */
00095   /* Unit: cycles of CPU clock.                                               */
00096   #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ( 156928U)
00097
00098   /* Delay for ADC stabilization time (ADC voltage regulator start-up time)   */
00099   /* Maximum delay is 10us (refer to device datasheet, param. TADCVREG_STUP). */
00100   /* Unit: us                                                                 */
00101   #define ADC_STAB_DELAY_US               ( 10U)
00102
00103   /* Delay for temperature sensor stabilization time.                         */
00104   /* Maximum delay is 10us (refer device datasheet, parameter tSTART).        */
00105   /* Unit: us                                                                 */
00106   #define ADC_TEMPSENSOR_DELAY_US         ( 10U)
00107
00108 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00109        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00110        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00111        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00112
00113 #if defined(STM32F373xC) || defined(STM32F378xx)
00114   /* Timeout values for ADC enable and disable settling time.                 */
00115   /* Values defined to be higher than worst cases: low clocks freq,           */
00116   /* maximum prescaler.                                                       */
00117   /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock         */
00118   /* prescaler 4U, sampling time 12.5 ADC clock cycles, resolution 12 bits.    */
00119   /* Unit: ms                                                                 */
00120   #define ADC_ENABLE_TIMEOUT              ( 2U)
00121   #define ADC_DISABLE_TIMEOUT             ( 2U)
00122
00123   /* Delay for ADC calibration:                                               */
00124   /* Hardware prerequisite before starting a calibration: the ADC must have   */
00125   /* been in power-on state for at least two ADC clock cycles.                */
00126   /* Unit: ADC clock cycles                                                   */
00127   #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES       ( 2U)
00128
00129   /* Timeout value for ADC calibration                                        */
00130   /* Value defined to be higher than worst cases: low clocks freq,            */
00131   /* maximum prescaler.                                                       */
00132   /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock         */
00133   /* prescaler 4U, sampling time 12.5 ADC clock cycles, resolution 12 bits.    */
00134   /* Unit: ms                                                                 */
00135   #define ADC_CALIBRATION_TIMEOUT         ( 10U)
00136
00137   /* Delay for ADC stabilization time.                                        */
00138   /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */
00139   /* Unit: us                                                                 */
00140   #define ADC_STAB_DELAY_US               ( 1U)
00141
00142   /* Delay for temperature sensor stabilization time.                         */
00143   /* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
00144   /* Unit: us                                                                 */
00145   #define ADC_TEMPSENSOR_DELAY_US         ( 10U)
00146
00147   /* Maximum number of CPU cycles corresponding to 1 ADC cycle                */
00148   /* Value fixed to worst case: clock prescalers slowing down ADC clock to    */
00149   /* minimum frequency                                                        */
00150   /*   - AHB prescaler: 16                                                    */
00151   /*   - ADC prescaler: 8                                                     */
00152   /* Unit: cycles of CPU clock.                                               */
00153   #define ADC_CYCLE_WORST_CASE_CPU_CYCLES ( 128U)
00154
00155   /* ADC conversion cycles (unit: ADC clock cycles)                           */
00156   /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
00157   /* resolution 12 bits)                                                      */
00158   #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5    ( 14U)
00159   #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5   ( 20U)
00160   #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5  ( 26U)
00161   #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5  ( 41U)
00162   #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5  ( 54U)
00163   #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5  ( 68U)
00164   #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5  ( 84U)
00165   #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 (252U)
00166 #endif /* STM32F373xC || STM32F378xx */
00167 /**
00168   * @}
00169   */
00170
00171 /* Private macro -------------------------------------------------------------*/
00172 /* Private variables ---------------------------------------------------------*/
00173 /* Private function prototypes -----------------------------------------------*/
00174 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00175     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00176     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00177     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00178 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
00179 static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
00180 static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);
00181 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00182        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00183        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00184        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00185
00186 #if defined(STM32F373xC) || defined(STM32F378xx)
00187 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
00188 static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
00189 #endif /* STM32F373xC || STM32F378xx */
00190
00191 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
00192 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
00193 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
00194
00195 /* Exported functions --------------------------------------------------------*/
00196
00197 /** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
00198   * @{
00199   */
00200
00201 /** @defgroup ADCEx_Exported_Functions_Group1 ADCEx Initialization and de-initialization functions
00202   * @brief    ADC Extended Initialization and Configuration functions
00203   *
00204 @verbatim
00205  ===============================================================================
00206               ##### Initialization and de-initialization functions #####
00207  ===============================================================================
00208     [..]  This section provides functions allowing to:
00209       (+) Initialize and configure the ADC.
00210       (+) De-initialize the ADC.
00211
00212 @endverbatim
00213   * @{
00214   */
00215
00216 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00217     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00218     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00219     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00220 /**
00221   * @brief  Initializes the ADC peripheral and regular group according to
00222   *         parameters specified in structure "ADC_InitTypeDef".
00223   * @note   As prerequisite, ADC clock must be configured at RCC top level
00224   *         depending on possible clock sources: AHB clock or PLL clock.
00225   *         See commented example code below that can be copied and uncommented
00226   *         into HAL_ADC_MspInit().
00227   * @note   Possibility to update parameters on the fly:
00228   *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
00229   *         coming from ADC state reset. Following calls to this function can
00230   *         be used to reconfigure some parameters of ADC_InitTypeDef
00231   *         structure on the fly, without modifying MSP configuration. If ADC
00232   *         MSP has to be modified again, HAL_ADC_DeInit() must be called
00233   *         before HAL_ADC_Init().
00234   *         The setting of these parameters is conditioned by ADC state.
00235   *         For parameters constraints, see comments of structure
00236   *         "ADC_InitTypeDef".
00237   * @note   This function configures the ADC within 2 scopes: scope of entire
00238   *         ADC and scope of regular group. For parameters details, see comments
00239   *         of structure "ADC_InitTypeDef".
00240   * @note   For devices with several ADCs: parameters related to common ADC
00241   *         registers (ADC clock mode) are set only if all ADCs sharing the
00242   *         same common group are disabled.
00243   *         If this is not the case, these common parameters setting are
00244   *         bypassed without error reporting: it can be the intended behaviour in
00245   *         case of update of a parameter of ADC_InitTypeDef on the fly,
00246   *         without  disabling the other ADCs sharing the same common group.
00247   * @param  hadc ADC handle
00248   * @retval HAL status
00249   */
00250 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
00251 {
00252   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00253   ADC_Common_TypeDef *tmpADC_Common;
00254   ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
00255   uint32_t tmpCFGR = 0U;
00256   __IO uint32_t wait_loop_index = 0U;
00257
00258   /* Check ADC handle */
00259   if(hadc == NULL)
00260   {
00261     return HAL_ERROR;
00262   }
00263
00264   /* Check the parameters */
00265   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00266   assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
00267   assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
00268   assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
00269   assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
00270   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00271   assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00272   assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
00273   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
00274   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
00275   assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
00276   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
00277
00278   if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
00279   {
00280     assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
00281     assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
00282     if(hadc->Init.DiscontinuousConvMode != DISABLE)
00283     {
00284       assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
00285     }
00286   }
00287
00288   /* Configuration of ADC core parameters and ADC MSP related parameters */
00289   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
00290   {
00291     /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured  */
00292     /* at RCC top level.                                                      */
00293     /* Refer to header of this file for more details on clock enabling        */
00294     /* procedure.                                                             */
00295
00296     /* Actions performed only if ADC is coming from state reset:              */
00297     /* - Initialization of ADC MSP                                            */
00298     /* - ADC voltage regulator enable                                         */
00299     if (hadc->State == HAL_ADC_STATE_RESET)
00300     {
00301       /* Initialize ADC error code */
00302       ADC_CLEAR_ERRORCODE(hadc);
00303
00304       /* Initialize HAL ADC API internal variables */
00305       hadc->InjectionConfig.ChannelCount = 0U;
00306       hadc->InjectionConfig.ContextQueue = 0U;
00307
00308       /* Allocate lock resource and initialize it */
00309       hadc->Lock = HAL_UNLOCKED;
00310
00311       /* Init the low level hardware */
00312       HAL_ADC_MspInit(hadc);
00313
00314       /* Enable voltage regulator (if disabled at this step) */
00315       if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0))
00316       {
00317         /* Note: The software must wait for the startup time of the ADC       */
00318         /*       voltage regulator before launching a calibration or          */
00319         /*       enabling the ADC. This temporization must be implemented by  */
00320         /*       software and is equal to 10 us in the worst case             */
00321         /*       process/temperature/power supply.                            */
00322
00323         /* Disable the ADC (if not already disabled) */
00324         tmp_hal_status = ADC_Disable(hadc);
00325
00326         /* Check if ADC is effectively disabled */
00327         /* Configuration of ADC parameters if previous preliminary actions    */
00328         /* are correctly completed.                                           */
00329         if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
00330             (tmp_hal_status == HAL_OK)                                  )
00331         {
00332           /* Set ADC state */
00333           ADC_STATE_CLR_SET(hadc->State,
00334                             HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00335                             HAL_ADC_STATE_BUSY_INTERNAL);
00336
00337           /* Set the intermediate state before moving the ADC voltage         */
00338           /* regulator to state enable.                                       */
00339           CLEAR_BIT(hadc->Instance->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0));
00340           /* Set ADVREGEN bits to 0x01U */
00341           SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_0);
00342
00343           /* Delay for ADC stabilization time.                                */
00344           /* Compute number of CPU cycles to wait for */
00345           wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
00346           while(wait_loop_index != 0U)
00347           {
00348             wait_loop_index--;
00349           }
00350         }
00351       }
00352     }
00353
00354     /* Verification that ADC voltage regulator is correctly enabled, whether  */
00355     /* or not ADC is coming from state reset (if any potential problem of     */
00356     /* clocking, voltage regulator would not be enabled).                     */
00357     if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) ||
00358         HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADVREGEN_1)   )
00359     {
00360       /* Update ADC state machine to error */
00361       ADC_STATE_CLR_SET(hadc->State,
00362                         HAL_ADC_STATE_BUSY_INTERNAL,
00363                         HAL_ADC_STATE_ERROR_INTERNAL);
00364
00365       /* Set ADC error code to ADC IP internal error */
00366       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00367
00368       tmp_hal_status = HAL_ERROR;
00369     }
00370   }
00371
00372
00373   /* Configuration of ADC parameters if previous preliminary actions are      */
00374   /* correctly completed and if there is no conversion on going on regular    */
00375   /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
00376   /* called to update a parameter on the fly).                                */
00377   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
00378       (tmp_hal_status == HAL_OK)                                &&
00379       (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)          )
00380   {
00381     /* Set ADC state */
00382     ADC_STATE_CLR_SET(hadc->State,
00383                       HAL_ADC_STATE_REG_BUSY,
00384                       HAL_ADC_STATE_BUSY_INTERNAL);
00385
00386     /* Configuration of common ADC parameters                                 */
00387
00388     /* Pointer to the common control register to which is belonging hadc      */
00389     /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common   */
00390     /* control registers)                                                     */
00391     tmpADC_Common = ADC_COMMON_REGISTER(hadc);
00392
00393     /* Set handle of the other ADC sharing the same common register           */
00394     ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
00395
00396
00397     /* Parameters update conditioned to ADC state:                            */
00398     /* Parameters that can be updated only when ADC is disabled:              */
00399     /*  - Multimode clock configuration                                       */
00400     if ((ADC_IS_ENABLE(hadc) == RESET)                                   &&
00401         ((tmphadcSharingSameCommonRegister.Instance == NULL)         ||
00402          (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET)   )   )
00403     {
00404       /* Reset configuration of ADC common register CCR:                      */
00405       /*   - ADC clock mode: CKMODE                                           */
00406       /* Some parameters of this register are not reset, since they are set   */
00407       /* by other functions and must be kept in case of usage of this         */
00408       /* function on the fly (update of a parameter of ADC_InitTypeDef        */
00409       /* without needing to reconfigure all other ADC groups/channels         */
00410       /* parameters):                                                         */
00411       /*   - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set    */
00412       /*     into HAL_ADCEx_MultiModeConfigChannel() )                        */
00413       /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
00414       /*     (set into HAL_ADC_ConfigChannel() or                             */
00415       /*     HAL_ADCEx_InjectedConfigChannel() )                              */
00416
00417       MODIFY_REG(tmpADC_Common->CCR       ,
00418                  ADC_CCR_CKMODE           ,
00419                  hadc->Init.ClockPrescaler );
00420     }
00421
00422
00423     /* Configuration of ADC:                                                  */
00424     /*  - resolution                                                          */
00425     /*  - data alignment                                                      */
00426     /*  - external trigger to start conversion                                */
00427     /*  - external trigger polarity                                           */
00428     /*  - continuous conversion mode                                          */
00429     /*  - overrun                                                             */
00430     /*  - discontinuous mode                                                  */
00431     SET_BIT(tmpCFGR, ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode) |
00432                      ADC_CFGR_OVERRUN(hadc->Init.Overrun)               |
00433                      hadc->Init.DataAlign                               |
00434                      hadc->Init.Resolution                               );
00435
00436     /* Enable discontinuous mode only if continuous mode is disabled */
00437     if (hadc->Init.DiscontinuousConvMode == ENABLE)
00438     {
00439       if (hadc->Init.ContinuousConvMode == DISABLE)
00440       {
00441         /* Enable the selected ADC regular discontinuous mode */
00442         /* Set the number of channels to be converted in discontinuous mode */
00443         SET_BIT(tmpCFGR, ADC_CFGR_DISCEN                                            |
00444                          ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion)  );
00445       }
00446       else
00447       {
00448         /* ADC regular group discontinuous was intended to be enabled,        */
00449         /* but ADC regular group modes continuous and sequencer discontinuous */
00450         /* cannot be enabled simultaneously.                                  */
00451
00452         /* Update ADC state machine to error */
00453         ADC_STATE_CLR_SET(hadc->State,
00454                           HAL_ADC_STATE_BUSY_INTERNAL,
00455                           HAL_ADC_STATE_ERROR_CONFIG);
00456
00457         /* Set ADC error code to ADC IP internal error */
00458         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00459       }
00460     }
00461
00462     /* Enable external trigger if trigger selection is different of software  */
00463     /* start.                                                                 */
00464     /* Note: This configuration keeps the hardware feature of parameter       */
00465     /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
00466     /*       software start.                                                  */
00467     if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
00468     {
00469       SET_BIT(tmpCFGR, ADC_CFGR_EXTSEL_SET(hadc, hadc->Init.ExternalTrigConv) |
00470                        hadc->Init.ExternalTrigConvEdge                         );
00471     }
00472
00473     /* Parameters update conditioned to ADC state:                            */
00474     /* Parameters that can be updated when ADC is disabled or enabled without */
00475     /* conversion on going on regular and injected groups:                    */
00476     /*  - DMA continuous request                                              */
00477     /*  - LowPowerAutoWait feature                                            */
00478     if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
00479     {
00480       CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY |
00481                                       ADC_CFGR_DMACFG  );
00482
00483       SET_BIT(tmpCFGR, ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait)       |
00484                        ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
00485     }
00486
00487     /* Update ADC configuration register with previous settings */
00488     MODIFY_REG(hadc->Instance->CFGR,
00489                ADC_CFGR_DISCNUM |
00490                ADC_CFGR_DISCEN  |
00491                ADC_CFGR_CONT    |
00492                ADC_CFGR_OVRMOD  |
00493                ADC_CFGR_EXTSEL  |
00494                ADC_CFGR_EXTEN   |
00495                ADC_CFGR_ALIGN   |
00496                ADC_CFGR_RES        ,
00497                tmpCFGR              );
00498
00499
00500     /* Configuration of regular group sequencer:                              */
00501     /* - if scan mode is disabled, regular channels sequence length is set to */
00502     /*   0x00: 1 channel converted (channel on regular rank 1U)                */
00503     /*   Parameter "NbrOfConversion" is discarded.                            */
00504     /*   Note: Scan mode is not present by hardware on this device, but       */
00505     /*   emulated by software for alignment over all STM32 devices.           */
00506     /* - if scan mode is enabled, regular channels sequence length is set to  */
00507     /*   parameter "NbrOfConversion"                                          */
00508     if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
00509     {
00510       /* Set number of ranks in regular group sequencer */
00511       MODIFY_REG(hadc->Instance->SQR1                     ,
00512                  ADC_SQR1_L                               ,
00513                  (hadc->Init.NbrOfConversion - (uint8_t)1U) );
00514     }
00515     else
00516     {
00517       CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
00518     }
00519
00520     /* Set ADC error code to none */
00521     ADC_CLEAR_ERRORCODE(hadc);
00522
00523     /* Set the ADC state */
00524     ADC_STATE_CLR_SET(hadc->State,
00525                       HAL_ADC_STATE_BUSY_INTERNAL,
00526                       HAL_ADC_STATE_READY);
00527   }
00528   else
00529   {
00530     /* Update ADC state machine to error */
00531     ADC_STATE_CLR_SET(hadc->State,
00532                       HAL_ADC_STATE_BUSY_INTERNAL,
00533                       HAL_ADC_STATE_ERROR_INTERNAL);
00534
00535     tmp_hal_status = HAL_ERROR;
00536   }
00537
00538
00539   /* Return function status */
00540   return tmp_hal_status;
00541 }
00542 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00543        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00544        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00545        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00546
00547 #if defined(STM32F373xC) || defined(STM32F378xx)
00548 /**
00549   * @brief  Initializes the ADC peripheral and regular group according to
00550   *         parameters specified in structure "ADC_InitTypeDef".
00551   * @note   As prerequisite, ADC clock must be configured at RCC top level
00552   *         (clock source APB2).
00553   *         See commented example code below that can be copied and uncommented
00554   *         into HAL_ADC_MspInit().
00555   * @note   Possibility to update parameters on the fly:
00556   *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
00557   *         coming from ADC state reset. Following calls to this function can
00558   *         be used to reconfigure some parameters of ADC_InitTypeDef
00559   *         structure on the fly, without modifying MSP configuration. If ADC
00560   *         MSP has to be modified again, HAL_ADC_DeInit() must be called
00561   *         before HAL_ADC_Init().
00562   *         The setting of these parameters is conditioned to ADC state.
00563   *         For parameters constraints, see comments of structure
00564   *         "ADC_InitTypeDef".
00565   * @note   This function configures the ADC within 2 scopes: scope of entire
00566   *         ADC and scope of regular group. For parameters details, see comments
00567   *         of structure "ADC_InitTypeDef".
00568   * @param  hadc ADC handle
00569   * @retval HAL status
00570   */
00571 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
00572 {
00573   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00574   uint32_t tmp_cr1 = 0U;
00575   uint32_t tmp_cr2 = 0U;
00576   uint32_t tmp_sqr1 = 0U;
00577
00578   /* Check ADC handle */
00579   if(hadc == NULL)
00580   {
00581     return HAL_ERROR;
00582   }
00583
00584   /* Check the parameters */
00585   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00586   assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
00587   assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
00588   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00589   assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
00590
00591   if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
00592   {
00593     assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
00594     assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
00595     if(hadc->Init.DiscontinuousConvMode != DISABLE)
00596     {
00597       assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
00598     }
00599   }
00600
00601   /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured    */
00602   /* at RCC top level.                                                        */
00603   /* Refer to header of this file for more details on clock enabling          */
00604   /* procedure.                                                               */
00605
00606   /* Actions performed only if ADC is coming from state reset:                */
00607   /* - Initialization of ADC MSP                                              */
00608   if (hadc->State == HAL_ADC_STATE_RESET)
00609   {
00610     /* Initialize ADC error code */
00611     ADC_CLEAR_ERRORCODE(hadc);
00612
00613     /* Allocate lock resource and initialize it */
00614     hadc->Lock = HAL_UNLOCKED;
00615
00616     /* Init the low level hardware */
00617     HAL_ADC_MspInit(hadc);
00618   }
00619
00620   /* Stop potential conversion on going, on regular and injected groups */
00621   /* Disable ADC peripheral */
00622   /* Note: In case of ADC already enabled, precaution to not launch an        */
00623   /*       unwanted conversion while modifying register CR2 by writing 1 to   */
00624   /*       bit ADON.                                                          */
00625   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
00626
00627
00628   /* Configuration of ADC parameters if previous preliminary actions are      */
00629   /* correctly completed.                                                     */
00630   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
00631       (tmp_hal_status == HAL_OK)                                  )
00632   {
00633     /* Set ADC state */
00634     ADC_STATE_CLR_SET(hadc->State,
00635                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00636                       HAL_ADC_STATE_BUSY_INTERNAL);
00637
00638     /* Set ADC parameters */
00639
00640     /* Configuration of ADC:                                                  */
00641     /*  - data alignment                                                      */
00642     /*  - external trigger to start conversion                                */
00643     /*  - external trigger polarity (always set to 1U, because needed for all  */
00644     /*    triggers: external trigger of SW start)                             */
00645     /*  - continuous conversion mode                                          */
00646     /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into          */
00647     /*       HAL_ADC_Start_xxx functions because if set in this function,     */
00648     /*       a conversion on injected group would start a conversion also on  */
00649     /*       regular group after ADC enabling.                                */
00650     tmp_cr2 |= (hadc->Init.DataAlign                             |
00651                 hadc->Init.ExternalTrigConv                      |
00652                 ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) );
00653
00654     /* Configuration of ADC:                                                  */
00655     /*  - scan mode                                                           */
00656     /*  - discontinuous mode disable/enable                                   */
00657     /*  - discontinuous mode number of conversions                            */
00658     tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
00659
00660     /* Enable discontinuous mode only if continuous mode is disabled */
00661     /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter    */
00662     /*       discontinuous is set anyway, but will have no effect on ADC HW.  */
00663     if (hadc->Init.DiscontinuousConvMode == ENABLE)
00664     {
00665       if (hadc->Init.ContinuousConvMode == DISABLE)
00666       {
00667         /* Enable the selected ADC regular discontinuous mode */
00668         /* Set the number of channels to be converted in discontinuous mode */
00669       tmp_cr1 |= (ADC_CR1_DISCEN                                           |
00670                   ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
00671       }
00672       else
00673       {
00674         /* ADC regular group discontinuous was intended to be enabled,        */
00675         /* but ADC regular group modes continuous and sequencer discontinuous */
00676         /* cannot be enabled simultaneously.                                  */
00677
00678         /* Update ADC state machine to error */
00679         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00680
00681         /* Set ADC error code to ADC IP internal error */
00682         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00683       }
00684     }
00685
00686     /* Update ADC configuration register CR1 with previous settings */
00687       MODIFY_REG(hadc->Instance->CR1,
00688                  ADC_CR1_SCAN    |
00689                  ADC_CR1_DISCEN  |
00690                  ADC_CR1_DISCNUM    ,
00691                  tmp_cr1             );
00692
00693     /* Update ADC configuration register CR2 with previous settings */
00694       MODIFY_REG(hadc->Instance->CR2,
00695                  ADC_CR2_ALIGN   |
00696                  ADC_CR2_EXTSEL  |
00697                  ADC_CR2_EXTTRIG |
00698                  ADC_CR2_CONT       ,
00699                  tmp_cr2             );
00700
00701     /* Configuration of regular group sequencer:                              */
00702     /* - if scan mode is disabled, regular channels sequence length is set to */
00703     /*   0x00: 1 channel converted (channel on regular rank 1U)                */
00704     /*   Parameter "NbrOfConversion" is discarded.                            */
00705     /*   Note: Scan mode is present by hardware on this device and, if        */
00706     /*   disabled, discards automatically nb of conversions. Anyway, nb of    */
00707     /*   conversions is forced to 0x00 for alignment over all STM32 devices.  */
00708     /* - if scan mode is enabled, regular channels sequence length is set to  */
00709     /*   parameter "NbrOfConversion"                                          */
00710     if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
00711     {
00712       tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
00713     }
00714
00715     MODIFY_REG(hadc->Instance->SQR1,
00716                ADC_SQR1_L          ,
00717                tmp_sqr1             );
00718
00719     /* Check back that ADC registers have effectively been configured to      */
00720     /* ensure of no potential problem of ADC core IP clocking.                */
00721     /* Check through register CR2 (excluding bits set in other functions:     */
00722     /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits   */
00723     /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal    */
00724     /* measurement path bit (TSVREFE).                                        */
00725     if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
00726                                         ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
00727                                         ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
00728                                         ADC_CR2_TSVREFE                     ))
00729          == tmp_cr2)
00730     {
00731       /* Set ADC error code to none */
00732       ADC_CLEAR_ERRORCODE(hadc);
00733
00734       /* Set the ADC state */
00735       ADC_STATE_CLR_SET(hadc->State,
00736                         HAL_ADC_STATE_BUSY_INTERNAL,
00737                         HAL_ADC_STATE_READY);
00738     }
00739     else
00740     {
00741       /* Update ADC state machine to error */
00742       ADC_STATE_CLR_SET(hadc->State,
00743                         HAL_ADC_STATE_BUSY_INTERNAL,
00744                         HAL_ADC_STATE_ERROR_INTERNAL);
00745
00746       /* Set ADC error code to ADC IP internal error */
00747       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00748
00749       tmp_hal_status = HAL_ERROR;
00750     }
00751
00752   }
00753   else
00754   {
00755     /* Update ADC state machine to error */
00756     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00757
00758     tmp_hal_status = HAL_ERROR;
00759   }
00760
00761   /* Return function status */
00762   return tmp_hal_status;
00763 }
00764 #endif /* STM32F373xC || STM32F378xx */
00765
00766 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00767     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00768     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00769     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00770 /**
00771   * @brief  Deinitialize the ADC peripheral registers to their default reset
00772   *         values, with deinitialization of the ADC MSP.
00773   * @note   For devices with several ADCs: reset of ADC common registers is done
00774   *         only if all ADCs sharing the same common group are disabled.
00775   *         If this is not the case, reset of these common parameters reset is
00776   *         bypassed without error reporting: it can be the intended behaviour in
00777   *         case of reset of a single ADC while the other ADCs sharing the same
00778   *         common group is still running.
00779   * @note   For devices with several ADCs: Global reset of all ADCs sharing a
00780   *         common group is possible.
00781   *         As this function is intended to reset a single ADC, to not impact
00782   *         other ADCs, instructions for global reset of multiple ADCs have been
00783   *         let commented below.
00784   *         If needed, the example code can be copied and uncommented into
00785   *         function HAL_ADC_MspDeInit().
00786   * @param  hadc ADC handle
00787   * @retval HAL status
00788   */
00789 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
00790 {
00791   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00792   ADC_Common_TypeDef *tmpADC_Common;
00793   ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
00794
00795   /* Check ADC handle */
00796   if(hadc == NULL)
00797   {
00798      return HAL_ERROR;
00799   }
00800
00801   /* Check the parameters */
00802   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00803
00804   /* Set ADC state */
00805   SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
00806
00807   /* Stop potential conversion on going, on regular and injected groups */
00808   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
00809
00810   /* Disable ADC peripheral if conversions are effectively stopped */
00811   if (tmp_hal_status == HAL_OK)
00812   {
00813     /* Flush register JSQR: queue sequencer reset when injected queue         */
00814     /* sequencer is enabled and ADC disabled.                                 */
00815     /* Enable injected queue sequencer after injected conversion stop         */
00816     SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
00817
00818     /* Disable the ADC peripheral */
00819     tmp_hal_status = ADC_Disable(hadc);
00820
00821     /* Check if ADC is effectively disabled */
00822     if (tmp_hal_status == HAL_OK)
00823     {
00824       /* Change ADC state */
00825       hadc->State = HAL_ADC_STATE_READY;
00826     }
00827     else
00828     {
00829       tmp_hal_status = HAL_ERROR;
00830     }
00831   }
00832
00833
00834   /* Configuration of ADC parameters if previous preliminary actions are      */
00835   /* correctly completed.                                                     */
00836   if (tmp_hal_status == HAL_OK)
00837   {
00838     /* ========== Reset ADC registers ========== */
00839     /* Reset register IER */
00840     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3  | ADC_IT_AWD2 | ADC_IT_AWD1 |
00841                                 ADC_IT_JQOVF | ADC_IT_OVR  |
00842                                 ADC_IT_JEOS  | ADC_IT_JEOC |
00843                                 ADC_IT_EOS   | ADC_IT_EOC  |
00844                                 ADC_IT_EOSMP | ADC_IT_RDY                 ) );
00845
00846     /* Reset register ISR */
00847     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3  | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
00848                                 ADC_FLAG_JQOVF | ADC_FLAG_OVR  |
00849                                 ADC_FLAG_JEOS  | ADC_FLAG_JEOC |
00850                                 ADC_FLAG_EOS   | ADC_FLAG_EOC  |
00851                                 ADC_FLAG_EOSMP | ADC_FLAG_RDY                   ) );
00852
00853     /* Reset register CR */
00854     /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART are  */
00855     /* in access mode "read-set": no direct reset applicable.                 */
00856     /* Reset Calibration mode to default setting (single ended):              */
00857     /* Disable voltage regulator:                                             */
00858     /* Note: Voltage regulator disable is conditioned to ADC state disabled:  */
00859     /*       already done above.                                              */
00860     /* Note: Voltage regulator disable is intended for power saving.          */
00861     /* Sequence to disable voltage regulator:                                 */
00862     /* 1. Set the intermediate state before moving the ADC voltage regulator  */
00863     /*    to disable state.                                                   */
00864     CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0 | ADC_CR_ADCALDIF);
00865     /* 2. Set ADVREGEN bits to 0x10U */
00866     SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1);
00867
00868     /* Reset register CFGR */
00869     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN |
00870                                     ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM     |
00871                                     ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN  |
00872                                     ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD  |
00873                                     ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN   |
00874                                     ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN    );
00875
00876     /* Reset register SMPR1 */
00877     CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |
00878                                      ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |
00879                                      ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1  );
00880
00881     /* Reset register SMPR2 */
00882     CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
00883                                      ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
00884                                      ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10  );
00885
00886     /* Reset register TR1 */
00887     CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
00888
00889     /* Reset register TR2 */
00890     CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
00891
00892     /* Reset register TR3 */
00893     CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
00894
00895     /* Reset register SQR1 */
00896     CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
00897                                     ADC_SQR1_SQ1 | ADC_SQR1_L);
00898
00899     /* Reset register SQR2 */
00900     CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
00901                                     ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
00902
00903     /* Reset register SQR3 */
00904     CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
00905                                     ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
00906
00907     /* Reset register SQR4 */
00908     CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
00909
00910     /* Reset register DR */
00911     /* bits in access mode read only, no direct reset applicable*/
00912
00913     /* Reset register OFR1 */
00914     CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
00915     /* Reset register OFR2 */
00916     CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
00917     /* Reset register OFR3 */
00918     CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
00919     /* Reset register OFR4 */
00920     CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
00921
00922     /* Reset registers JDR1, JDR2, JDR3, JDR4 */
00923     /* bits in access mode read only, no direct reset applicable*/
00924
00925     /* Reset register AWD2CR */
00926     CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
00927
00928     /* Reset register AWD3CR */
00929     CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
00930
00931     /* Reset register DIFSEL */
00932     CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
00933
00934     /* Reset register CALFACT */
00935     CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
00936
00937
00938
00939
00940
00941
00942     /* ========== Reset common ADC registers ========== */
00943
00944     /* Pointer to the common control register to which is belonging hadc      */
00945     /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common   */
00946     /* control registers)                                                     */
00947     tmpADC_Common = ADC_COMMON_REGISTER(hadc);
00948
00949     /* Set handle of the other ADC sharing the same common register           */
00950     ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
00951
00952     /* Software is allowed to change common parameters only when all ADCs of  */
00953     /* the common group are disabled.                                         */
00954     if ((ADC_IS_ENABLE(hadc) == RESET)                                  &&
00955         ( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
00956           (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) )   )
00957     {
00958       /* Reset configuration of ADC common register CCR:
00959         - clock mode: CKMODE
00960         - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set into
00961           HAL_ADCEx_MultiModeConfigChannel() )
00962         - internal measurement paths: Vbat, temperature sensor, Vref (set into
00963           HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
00964       */
00965       CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_CKMODE |
00966                                     ADC_CCR_VBATEN |
00967                                     ADC_CCR_TSEN   |
00968                                     ADC_CCR_VREFEN |
00969                                     ADC_CCR_MDMA   |
00970                                     ADC_CCR_DMACFG |
00971                                     ADC_CCR_DELAY  |
00972                                     ADC_CCR_MULTI   );
00973
00974       /* Other ADC common registers (CSR, CDR) are in access mode read only,
00975          no direct reset applicable */
00976     }
00977
00978
00979     /* ========== Hard reset and clock disable of ADC peripheral ========== */
00980     /* Into HAL_ADC_MspDeInit(), ADC clock can be hard reset and disabled     */
00981     /* at RCC top level.                                                      */
00982     /* Refer to header of this file for more details on clock disabling       */
00983     /* procedure.                                                             */
00984
00985
00986     /* DeInit the low level hardware */
00987     HAL_ADC_MspDeInit(hadc);
00988
00989     /* Set ADC error code to none */
00990     ADC_CLEAR_ERRORCODE(hadc);
00991
00992     /* Set ADC state */
00993     hadc->State = HAL_ADC_STATE_RESET;
00994   }
00995
00996   /* Process unlocked */
00997   __HAL_UNLOCK(hadc);
00998
00999
01000   /* Return function status */
01001   return tmp_hal_status;
01002 }
01003 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
01004        /* STM32F302xC || STM32F303xC || STM32F358xx || */
01005        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
01006        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
01007
01008 #if defined(STM32F373xC) || defined(STM32F378xx)
01009 /**
01010   * @brief  Deinitialize the ADC peripheral registers to its default reset values.
01011   * @param  hadc ADC handle
01012   * @retval HAL status
01013   */
01014 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
01015 {
01016   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01017
01018   /* Check ADC handle */
01019   if(hadc == NULL)
01020   {
01021      return HAL_ERROR;
01022   }
01023
01024   /* Check the parameters */
01025   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01026
01027   /* Set ADC state */
01028   SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
01029
01030   /* Stop potential conversion on going, on regular and injected groups */
01031   /* Disable ADC peripheral */
01032   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
01033
01034
01035   /* Configuration of ADC parameters if previous preliminary actions are      */
01036   /* correctly completed.                                                     */
01037   if (tmp_hal_status == HAL_OK)
01038   {
01039     /* ========== Reset ADC registers ========== */
01040     /* Reset register SR */
01041     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC |
01042                                 ADC_FLAG_JSTRT | ADC_FLAG_STRT));
01043
01044     /* Reset register CR1 */
01045     CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN   | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM |
01046                                     ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO   |
01047                                     ADC_CR1_AWDSGL  | ADC_CR1_SCAN   | ADC_CR1_JEOCIE  |
01048                                     ADC_CR1_AWDIE   | ADC_CR1_EOCIE  | ADC_CR1_AWDCH    ));
01049
01050     /* Reset register CR2 */
01051     CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
01052                                     ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL  | ADC_CR2_JEXTTRIG |
01053                                     ADC_CR2_JEXTSEL | ADC_CR2_ALIGN   | ADC_CR2_DMA      |
01054                                     ADC_CR2_RSTCAL  | ADC_CR2_CAL     | ADC_CR2_CONT     |
01055                                     ADC_CR2_ADON                                          ));
01056
01057     /* Reset register SMPR1 */
01058     CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP15 |
01059                                       ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 |
01060                                       ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10  ));
01061
01062     /* Reset register SMPR2 */
01063     CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 |
01064                                       ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 |
01065                                       ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 |
01066                                       ADC_SMPR2_SMP0                                    ));
01067
01068     /* Reset register JOFR1 */
01069     CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
01070     /* Reset register JOFR2 */
01071     CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
01072     /* Reset register JOFR3 */
01073     CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
01074     /* Reset register JOFR4 */
01075     CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
01076
01077     /* Reset register HTR */
01078     CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
01079     /* Reset register LTR */
01080     CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
01081
01082     /* Reset register SQR1 */
01083     CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L    |
01084                                     ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
01085                                     ADC_SQR1_SQ14 | ADC_SQR1_SQ13  );
01086
01087     /* Reset register SQR1 */
01088     CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L    |
01089                                     ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
01090                                     ADC_SQR1_SQ14 | ADC_SQR1_SQ13  );
01091
01092     /* Reset register SQR2 */
01093     CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
01094                                     ADC_SQR2_SQ9  | ADC_SQR2_SQ8  | ADC_SQR2_SQ7   );
01095
01096     /* Reset register SQR3 */
01097     CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 |
01098                                     ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1  );
01099
01100     /* Reset register JSQR */
01101     CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
01102                                     ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
01103                                     ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1  );
01104
01105     /* Reset register JSQR */
01106     CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
01107                                     ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
01108                                     ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1  );
01109
01110     /* Reset register DR */
01111     /* bits in access mode read only, no direct reset applicable*/
01112
01113     /* Reset registers JDR1, JDR2, JDR3, JDR4 */
01114     /* bits in access mode read only, no direct reset applicable*/
01115
01116     /* Reset VBAT measurement path, in case of enabled before by selecting    */
01117     /* channel ADC_CHANNEL_VBAT. */
01118     SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT);
01119
01120
01121     /* ========== Hard reset ADC peripheral ========== */
01122     /* Performs a global reset of the entire ADC peripheral: ADC state is     */
01123     /* forced to a similar state after device power-on.                       */
01124     /* If needed, copy-paste and uncomment the following reset code into      */
01125     /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)":              */
01126     /*                                                                        */
01127     /*  __HAL_RCC_ADC1_FORCE_RESET()                                          */
01128     /*  __HAL_RCC_ADC1_RELEASE_RESET()                                        */
01129
01130     /* DeInit the low level hardware */
01131     HAL_ADC_MspDeInit(hadc);
01132
01133     /* Set ADC error code to none */
01134     ADC_CLEAR_ERRORCODE(hadc);
01135
01136     /* Set ADC state */
01137     hadc->State = HAL_ADC_STATE_RESET;
01138
01139   }
01140
01141   /* Process unlocked */
01142   __HAL_UNLOCK(hadc);
01143
01144   /* Return function status */
01145   return tmp_hal_status;
01146 }
01147 #endif /* STM32F373xC || STM32F378xx */
01148
01149 /**
01150   * @}
01151   */
01152
01153 /** @defgroup ADCEx_Exported_Functions_Group2 ADCEx Input and Output operation functions
01154   * @brief    ADC Extended IO operation functions
01155   *
01156 @verbatim
01157  ===============================================================================
01158              ##### IO operation functions #####
01159  ===============================================================================
01160     [..]  This section provides functions allowing to:
01161       (+) Start conversion of regular group.
01162       (+) Stop conversion of regular group.
01163       (+) Poll for conversion complete on regular group.
01164       (+) Poll for conversion event.
01165       (+) Get result of regular channel conversion.
01166       (+) Start conversion of regular group and enable interruptions.
01167       (+) Stop conversion of regular group and disable interruptions.
01168       (+) Handle ADC interrupt request
01169       (+) Start conversion of regular group and enable DMA transfer.
01170       (+) Stop conversion of regular group and disable ADC DMA transfer.
01171
01172       (+) Start conversion of injected group.
01173       (+) Stop conversion of injected group.
01174       (+) Poll for conversion complete on injected group.
01175       (+) Get result of injected channel conversion.
01176       (+) Start conversion of injected group and enable interruptions.
01177       (+) Stop conversion of injected group and disable interruptions.
01178
01179       (+) Start multimode and enable DMA transfer.
01180       (+) Stop multimode and disable ADC DMA transfer.
01181       (+) Get result of multimode conversion.
01182
01183       (+) Perform the ADC self-calibration for single or differential ending.
01184       (+) Get calibration factors for single or differential ending.
01185       (+) Set calibration factors for single or differential ending.
01186
01187 @endverbatim
01188   * @{
01189   */
01190
01191 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
01192     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
01193     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
01194     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01195 /**
01196   * @brief  Enables ADC, starts conversion of regular group.
01197   *         Interruptions enabled in this function: None.
01198   * @note   Case of multimode enabled (for devices with several ADCs):
01199   *         if ADC is slave, ADC is enabled only (conversion is not started).
01200   *         if ADC is master, ADC is enabled and multimode conversion is started.
01201   * @param  hadc ADC handle
01202   * @retval HAL status
01203   */
01204 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
01205 {
01206   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01207
01208   /* Check the parameters */
01209   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01210
01211   /* Perform ADC enable and conversion start if no conversion is on going */
01212   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
01213   {
01214     /* Process locked */
01215     __HAL_LOCK(hadc);
01216
01217     /* Enable the ADC peripheral */
01218     tmp_hal_status = ADC_Enable(hadc);
01219
01220     /* Start conversion if ADC is effectively enabled */
01221     if (tmp_hal_status == HAL_OK)
01222     {
01223       /* Set ADC state                                                        */
01224       /* - Clear state bitfield related to regular group conversion results   */
01225       /* - Set state bitfield related to regular operation                    */
01226       ADC_STATE_CLR_SET(hadc->State,
01227                         HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
01228                         HAL_ADC_STATE_REG_BUSY);
01229
01230       /* Set group injected state (from auto-injection) and multimode state   */
01231       /* for all cases of multimode: independent mode, multimode ADC master   */
01232       /* or multimode ADC slave (for devices with several ADCs):              */
01233       if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
01234       {
01235         /* Set ADC state (ADC independent or master) */
01236         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01237
01238         /* If conversions on group regular are also triggering group injected,*/
01239         /* update ADC state.                                                  */
01240         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
01241         {
01242           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01243         }
01244       }
01245       else
01246       {
01247         /* Set ADC state (ADC slave) */
01248         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01249
01250         /* If conversions on group regular are also triggering group injected,*/
01251         /* update ADC state.                                                  */
01252         if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
01253         {
01254           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01255         }
01256       }
01257
01258       /* State machine update: Check if an injected conversion is ongoing */
01259       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01260       {
01261         /* Reset ADC error code fields related to conversions on group regular*/
01262         CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
01263       }
01264       else
01265       {
01266         /* Reset ADC all error code fields */
01267         ADC_CLEAR_ERRORCODE(hadc);
01268       }
01269
01270       /* Process unlocked */
01271       /* Unlock before starting ADC conversions: in case of potential         */
01272       /* interruption, to let the process to ADC IRQ Handler.                 */
01273       __HAL_UNLOCK(hadc);
01274
01275       /* Clear regular group conversion flag and overrun flag */
01276       /* (To ensure of no unknown state from potential previous ADC           */
01277       /* operations)                                                          */
01278       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01279
01280       /* Enable conversion of regular group.                                  */
01281       /* If software start has been selected, conversion starts immediately.  */
01282       /* If external trigger has been selected, conversion will start at next */
01283       /* trigger event.                                                       */
01284       /* Case of multimode enabled (for devices with several ADCs):           */
01285       /*  - if ADC is slave, ADC is enabled only (conversion is not started). */
01286       /*  - if ADC is master, ADC is enabled and conversion is started.       */
01287       if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
01288       {
01289         SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
01290       }
01291     }
01292     else
01293     {
01294       /* Process unlocked */
01295       __HAL_UNLOCK(hadc);
01296     }
01297   }
01298   else
01299   {
01300     tmp_hal_status = HAL_BUSY;
01301   }
01302
01303   /* Return function status */
01304   return tmp_hal_status;
01305 }
01306 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
01307        /* STM32F302xC || STM32F303xC || STM32F358xx || */
01308        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
01309        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
01310
01311 #if defined(STM32F373xC) || defined(STM32F378xx)
01312 /**
01313   * @brief  Enables ADC, starts conversion of regular group.
01314   *         Interruptions enabled in this function: None.
01315   * @param  hadc ADC handle
01316   * @retval HAL status
01317   */
01318 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
01319 {
01320   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01321
01322   /* Check the parameters */
01323   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01324
01325   /* Process locked */
01326   __HAL_LOCK(hadc);
01327
01328   /* Enable the ADC peripheral */
01329   tmp_hal_status = ADC_Enable(hadc);
01330
01331   /* Start conversion if ADC is effectively enabled */
01332   if (tmp_hal_status == HAL_OK)
01333   {
01334     /* Set ADC state                                                          */
01335     /* - Clear state bitfield related to regular group conversion results     */
01336     /* - Set state bitfield related to regular operation                      */
01337     ADC_STATE_CLR_SET(hadc->State,
01338                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
01339                       HAL_ADC_STATE_REG_BUSY);
01340
01341     /* Set group injected state (from auto-injection) */
01342     /* If conversions on group regular are also triggering group injected,    */
01343     /* update ADC state.                                                      */
01344     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
01345     {
01346       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01347     }
01348
01349     /* State machine update: Check if an injected conversion is ongoing */
01350     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01351     {
01352       /* Reset ADC error code fields related to conversions on group regular */
01353       CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
01354     }
01355     else
01356     {
01357       /* Reset ADC all error code fields */
01358       ADC_CLEAR_ERRORCODE(hadc);
01359     }
01360
01361     /* Process unlocked */
01362     /* Unlock before starting ADC conversions: in case of potential           */
01363     /* interruption, to let the process to ADC IRQ Handler.                   */
01364     __HAL_UNLOCK(hadc);
01365
01366     /* Clear regular group conversion flag and overrun flag */
01367     /* (To ensure of no unknown state from potential previous ADC operations) */
01368     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
01369
01370     /* Enable conversion of regular group.                                    */
01371     /* If software start has been selected, conversion starts immediately.    */
01372     /* If external trigger has been selected, conversion will start at next   */
01373     /* trigger event.                                                         */
01374     /* Note: Alternate trigger for single conversion could be to force an     */
01375     /*       additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
01376     if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
01377     {
01378       /* Start ADC conversion on regular group with SW start */
01379       SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
01380     }
01381     else
01382     {
01383       /* Start ADC conversion on regular group with external trigger */
01384       SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
01385     }
01386   }
01387
01388   /* Return function status */
01389   return tmp_hal_status;
01390 }
01391 #endif /* STM32F373xC || STM32F378xx */
01392
01393 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
01394     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
01395     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
01396     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01397 /**
01398   * @brief  Stop ADC conversion of both groups regular and injected,
01399   *         disable ADC peripheral.
01400   * @note   ADC peripheral disable is forcing interruption of potential
01401   *         conversion on injected group. If injected group is under use,
01402   *         it should be preliminarily stopped using function
01403   *         @ref HAL_ADCEx_InjectedStop().
01404   *         To stop ADC conversion only on ADC group regular
01405   *         while letting ADC group injected conversions running,
01406   *         use function @ref HAL_ADCEx_RegularStop().
01407   * @param  hadc ADC handle
01408   * @retval HAL status.
01409   */
01410 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
01411 {
01412   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01413
01414   /* Check the parameters */
01415   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01416
01417   /* Process locked */
01418   __HAL_LOCK(hadc);
01419
01420   /* 1. Stop potential conversion on going, on regular and injected groups */
01421   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01422
01423   /* Disable ADC peripheral if conversions are effectively stopped */
01424   if (tmp_hal_status == HAL_OK)
01425   {
01426     /* 2. Disable the ADC peripheral */
01427     tmp_hal_status = ADC_Disable(hadc);
01428
01429     /* Check if ADC is effectively disabled */
01430     if (tmp_hal_status == HAL_OK)
01431     {
01432       /* Set ADC state */
01433       ADC_STATE_CLR_SET(hadc->State,
01434                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
01435                         HAL_ADC_STATE_READY);
01436     }
01437   }
01438
01439   /* Process unlocked */
01440   __HAL_UNLOCK(hadc);
01441
01442   /* Return function status */
01443   return tmp_hal_status;
01444 }
01445 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
01446        /* STM32F302xC || STM32F303xC || STM32F358xx || */
01447        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
01448        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
01449
01450 #if defined(STM32F373xC) || defined(STM32F378xx)
01451 /**
01452   * @brief  Stop ADC conversion of regular group (and injected channels in
01453   *         case of auto_injection mode), disable ADC peripheral.
01454   * @note   ADC peripheral disable is forcing interruption of potential
01455   *         conversion on injected group. If injected group is under use, it
01456   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
01457   * @param  hadc ADC handle
01458   * @retval HAL status.
01459   */
01460 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
01461 {
01462   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01463
01464   /* Check the parameters */
01465   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01466
01467   /* Process locked */
01468   __HAL_LOCK(hadc);
01469
01470   /* Stop potential conversion on going, on regular and injected groups */
01471   /* Disable ADC peripheral */
01472   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
01473
01474   /* Check if ADC is effectively disabled */
01475   if (tmp_hal_status == HAL_OK)
01476   {
01477     /* Set ADC state */
01478     ADC_STATE_CLR_SET(hadc->State,
01479                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
01480                       HAL_ADC_STATE_READY);
01481   }
01482
01483   /* Process unlocked */
01484   __HAL_UNLOCK(hadc);
01485
01486   /* Return function status */
01487   return tmp_hal_status;
01488 }
01489 #endif /* STM32F373xC || STM32F378xx */
01490
01491 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
01492     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
01493     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
01494     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01495 /**
01496   * @brief  Wait for regular group conversion to be completed.
01497   * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
01498   *         conversion) are cleared by this function, with an exception:
01499   *         if low power feature "LowPowerAutoWait" is enabled, flags are
01500   *         not cleared to not interfere with this feature until data register
01501   *         is read using function HAL_ADC_GetValue().
01502   * @note   This function cannot be used in a particular setup: ADC configured
01503   *         in DMA mode and polling for end of each conversion (ADC init
01504   *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
01505   *         In this case, DMA resets the flag EOC and polling cannot be
01506   *         performed on each conversion. Nevertheless, polling can still
01507   *         be performed on the complete sequence (ADC init
01508   *         parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
01509   * @param  hadc ADC handle
01510   * @param  Timeout Timeout value in millisecond.
01511   * @note   Depending on init parameter "EOCSelection", flags EOS or EOC is
01512   *         checked and cleared depending on autodelay status (bit AUTDLY).
01513   * @retval HAL status
01514   */
01515 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
01516 {
01517   uint32_t tickstart;
01518   uint32_t tmp_Flag_EOC;
01519   ADC_Common_TypeDef *tmpADC_Common;
01520   uint32_t tmp_cfgr     = 0x0U;
01521
01522   /* Check the parameters */
01523   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01524
01525 /* If end of conversion selected to end of sequence */
01526   if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
01527   {
01528     tmp_Flag_EOC = ADC_FLAG_EOS;
01529   }
01530   /* If end of conversion selected to end of each conversion */
01531   else /* ADC_EOC_SINGLE_CONV */
01532   {
01533     /* Verification that ADC configuration is compliant with polling for      */
01534     /* each conversion:                                                       */
01535     /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
01536     /* several ranks and polling for end of each conversion.                  */
01537     /* For code simplicity sake, this particular case is generalized to       */
01538     /* ADC configured in DMA mode and and polling for end of each conversion. */
01539
01540     /* Pointer to the common control register to which is belonging hadc      */
01541     /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */
01542     /* control registers)                                                     */
01543     tmpADC_Common = ADC_COMMON_REGISTER(hadc);
01544
01545     /* Check DMA configuration, depending on MultiMode set or not */
01546     if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT)
01547     {
01548       if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
01549       {
01550         /* Update ADC state machine to error */
01551         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01552
01553         /* Process unlocked */
01554         __HAL_UNLOCK(hadc);
01555
01556         return HAL_ERROR;
01557       }
01558     }
01559     else
01560     {
01561       /* MultiMode is enabled, Common Control Register MDMA bits must be checked */
01562       if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET)
01563       {
01564         /* Update ADC state machine to error */
01565         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01566
01567         /* Process unlocked */
01568         __HAL_UNLOCK(hadc);
01569
01570         return HAL_ERROR;
01571       }
01572     }
01573
01574     tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS);
01575
01576   }
01577
01578   /* Get relevant register CFGR in ADC instance of ADC master or slave      */
01579   /* in function of multimode state (for devices with multimode             */
01580   /* available).                                                            */
01581   if(ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
01582   {
01583     tmp_cfgr = READ_REG(hadc->Instance->CFGR);
01584   }
01585   else
01586   {
01587     tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
01588   }
01589
01590   /* Get tick count */
01591   tickstart = HAL_GetTick();
01592
01593   /* Wait until End of Conversion or End of Sequence flag is raised */
01594   while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
01595   {
01596     /* Check if timeout is disabled (set to infinite wait) */
01597     if(Timeout != HAL_MAX_DELAY)
01598     {
01599       if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
01600       {
01601         /* Update ADC state machine to timeout */
01602         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01603
01604         /* Process unlocked */
01605         __HAL_UNLOCK(hadc);
01606
01607         return HAL_TIMEOUT;
01608       }
01609     }
01610   }
01611
01612   /* Update ADC state machine */
01613   SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
01614
01615   /* Determine whether any further conversion upcoming on group regular       */
01616   /* by external trigger, continuous mode or scan sequence on going.          */
01617   if(ADC_IS_SOFTWARE_START_REGULAR(hadc)           &&
01618      (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET)   )
01619   {
01620     /* If End of Sequence is reached, disable interrupts */
01621     if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
01622     {
01623       /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit             */
01624       /* ADSTART==0 (no conversion on going)                                  */
01625       if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
01626       {
01627         /* Set ADC state */
01628         CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01629
01630         if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01631         {
01632           SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01633         }
01634       }
01635       else
01636       {
01637         /* Change ADC state to error state */
01638         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01639
01640         /* Set ADC error code to ADC IP internal error */
01641         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
01642       }
01643     }
01644   }
01645
01646   /* Clear end of conversion flag of regular group if low power feature       */
01647   /* "LowPowerAutoWait " is disabled, to not interfere with this feature      */
01648   /* until data register is read using function HAL_ADC_GetValue().           */
01649   if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
01650   {
01651     /* Clear regular group conversion flag */
01652     /* (EOC or EOS depending on HAL ADC initialization parameter) */
01653     __HAL_ADC_CLEAR_FLAG(hadc, tmp_Flag_EOC);
01654   }
01655
01656   /* Return ADC state */
01657   return HAL_OK;
01658 }
01659 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
01660        /* STM32F302xC || STM32F303xC || STM32F358xx || */
01661        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
01662        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
01663
01664 #if defined(STM32F373xC) || defined(STM32F378xx)
01665 /**
01666   * @brief  Wait for regular group conversion to be completed.
01667   * @note   This function cannot be used in a particular setup: ADC configured
01668   *         in DMA mode.
01669   *         In this case, DMA resets the flag EOC and polling cannot be
01670   *         performed on each conversion.
01671   * @note   On STM32F37x devices, limitation in case of sequencer enabled
01672   *         (several ranks selected): polling cannot be done on each
01673   *         conversion inside the sequence. In this case, polling is replaced by
01674   *         wait for maximum conversion time.
01675   * @param  hadc ADC handle
01676   * @param  Timeout Timeout value in millisecond.
01677   * @retval HAL status
01678   */
01679 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
01680 {
01681   uint32_t tickstart;
01682
01683   /* Variables for polling in case of scan mode enabled */
01684   uint32_t Conversion_Timeout_CPU_cycles_max = 0U;
01685   uint32_t Conversion_Timeout_CPU_cycles = 0U;
01686
01687   /* Check the parameters */
01688   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01689
01690   /* Verification that ADC configuration is compliant with polling for        */
01691   /* each conversion:                                                         */
01692   /* Particular case is ADC configured in DMA mode                            */
01693   if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA))
01694   {
01695     /* Update ADC state machine to error */
01696     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01697
01698     /* Process unlocked */
01699     __HAL_UNLOCK(hadc);
01700
01701     return HAL_ERROR;
01702   }
01703
01704   /* Get tick count */
01705   tickstart = HAL_GetTick();
01706
01707   /* Polling for end of conversion: differentiation if single/sequence        */
01708   /* conversion.                                                              */
01709   /*  - If single conversion for regular group (Scan mode disabled or enabled */
01710   /*    with NbrOfConversion =1U), flag EOC is used to determine the           */
01711   /*    conversion completion.                                                */
01712   /*  - If sequence conversion for regular group (scan mode enabled and       */
01713   /*    NbrOfConversion >=2U), flag EOC is set only at the end of the          */
01714   /*    sequence.                                                             */
01715   /*    To poll for each conversion, the maximum conversion time is computed  */
01716   /*    from ADC conversion time (selected sampling time + conversion time of */
01717   /*    12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on    */
01718   /*    settings, conversion time range can be from 28 to 32256 CPU cycles).  */
01719   /*    As flag EOC is not set after each conversion, no timeout status can   */
01720   /*    be set.                                                               */
01721   if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) &&
01722       HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L)    )
01723   {
01724     /* Wait until End of Conversion flag is raised */
01725     while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
01726     {
01727       /* Check if timeout is disabled (set to infinite wait) */
01728       if(Timeout != HAL_MAX_DELAY)
01729       {
01730         if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
01731         {
01732           /* Update ADC state machine to timeout */
01733           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01734
01735           /* Process unlocked */
01736           __HAL_UNLOCK(hadc);
01737
01738           return HAL_TIMEOUT;
01739         }
01740       }
01741     }
01742   }
01743   else
01744   {
01745     /* Replace polling by wait for maximum conversion time */
01746     /* Calculation of CPU cycles corresponding to ADC conversion cycles.      */
01747     /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all  */
01748     /* channels.                                                              */
01749     Conversion_Timeout_CPU_cycles_max = ADC_CLOCK_PRESCALER_RANGE() ;
01750     Conversion_Timeout_CPU_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc);
01751
01752     /* Poll with maximum conversion time */
01753     while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
01754     {
01755       /* Check if timeout is disabled (set to infinite wait) */
01756       if(Timeout != HAL_MAX_DELAY)
01757       {
01758         if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
01759         {
01760           /* Update ADC state machine to timeout */
01761           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01762
01763           /* Process unlocked */
01764           __HAL_UNLOCK(hadc);
01765
01766           return HAL_TIMEOUT;
01767         }
01768       }
01769       Conversion_Timeout_CPU_cycles ++;
01770     }
01771   }
01772
01773   /* Clear regular group conversion flag */
01774   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
01775
01776   /* Update ADC state machine */
01777   SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
01778
01779   /* Determine whether any further conversion upcoming on group regular       */
01780   /* by external trigger, continuous mode or scan sequence on going.          */
01781   /* Note: On STM32F37x devices, in case of sequencer enabled                 */
01782   /*       (several ranks selected), end of conversion flag is raised         */
01783   /*       at the end of the sequence.                                        */
01784   if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
01785      (hadc->Init.ContinuousConvMode == DISABLE)   )
01786   {
01787     /* Set ADC state */
01788     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01789
01790     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01791     {
01792       SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01793     }
01794   }
01795
01796   /* Return ADC state */
01797   return HAL_OK;
01798 }
01799 #endif /* STM32F373xC || STM32F378xx */
01800
01801 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
01802     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
01803     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
01804     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01805 /**
01806   * @brief  Poll for conversion event.
01807   * @param  hadc ADC handle
01808   * @param  EventType the ADC event type.
01809   *          This parameter can be one of the following values:
01810   *            @arg ADC_AWD1_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
01811   *            @arg ADC_AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
01812   *            @arg ADC_AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
01813   *            @arg ADC_OVR_EVENT: ADC Overrun event
01814   *            @arg ADC_JQOVF_EVENT: ADC Injected context queue overflow event
01815   * @param  Timeout Timeout value in millisecond.
01816   * @retval HAL status
01817   */
01818 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
01819 {
01820   uint32_t tickstart;
01821
01822   /* Check the parameters */
01823   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01824   assert_param(IS_ADC_EVENT_TYPE(EventType));
01825
01826   /* Get start tick count */
01827   tickstart = HAL_GetTick();
01828
01829   /* Check selected event flag */
01830   while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
01831   {
01832     /* Check if timeout is disabled (set to infinite wait) */
01833     if(Timeout != HAL_MAX_DELAY)
01834     {
01835       if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
01836       {
01837         /* Update ADC state machine to timeout */
01838         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01839
01840         /* Process unlocked */
01841         __HAL_UNLOCK(hadc);
01842
01843         return HAL_TIMEOUT;
01844       }
01845     }
01846   }
01847
01848
01849   switch(EventType)
01850   {
01851   /* Analog watchdog (level out of window) event */
01852   /* Note: In case of several analog watchdog enabled, if needed to know      */
01853   /* which one triggered and on which ADCx, test ADC state of analog watchdog */
01854   /* flags HAL_ADC_STATE_AWD1/2U/3 using function "HAL_ADC_GetState()".        */
01855   /* For example:                                                             */
01856   /*  " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)) "    */
01857   /*  " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD2)) "    */
01858   /*  " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD3)) "    */
01859   /* Check analog watchdog 1 flag */
01860   case ADC_AWD_EVENT:
01861     /* Set ADC state */
01862     SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
01863
01864     /* Clear ADC analog watchdog flag */
01865     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
01866     break;
01867
01868   /* Check analog watchdog 2 flag */
01869   case ADC_AWD2_EVENT:
01870     /* Set ADC state */
01871     SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
01872
01873     /* Clear ADC analog watchdog flag */
01874     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
01875     break;
01876
01877   /* Check analog watchdog 3 flag */
01878   case ADC_AWD3_EVENT:
01879     /* Set ADC state */
01880     SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
01881
01882     /* Clear ADC analog watchdog flag */
01883     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
01884     break;
01885
01886   /* Injected context queue overflow event */
01887   case ADC_JQOVF_EVENT:
01888     /* Set ADC state */
01889     SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
01890
01891     /* Set ADC error code to Injected context queue overflow */
01892     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
01893
01894     /* Clear ADC Injected context queue overflow flag */
01895     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
01896     break;
01897
01898   /* Overrun event */
01899   default: /* Case ADC_OVR_EVENT */
01900     /* If overrun is set to overwrite previous data, overrun event is not     */
01901     /* considered as an error.                                                */
01902     /* (cf ref manual "Managing conversions without using the DMA and without */
01903     /* overrun ")                                                             */
01904     if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
01905     {
01906       /* Set ADC state */
01907       SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
01908
01909       /* Set ADC error code to overrun */
01910       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
01911     }
01912
01913     /* Clear ADC Overrun flag */
01914     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
01915     break;
01916   }
01917
01918   /* Return ADC state */
01919   return HAL_OK;
01920 }
01921 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
01922        /* STM32F302xC || STM32F303xC || STM32F358xx || */
01923        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
01924        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
01925
01926 #if defined(STM32F373xC) || defined(STM32F378xx)
01927 /**
01928   * @brief  Poll for conversion event.
01929   * @param  hadc ADC handle
01930   * @param  EventType the ADC event type.
01931   *          This parameter can be one of the following values:
01932   *            @arg ADC_AWD_EVENT: ADC Analog watchdog event.
01933   * @param  Timeout Timeout value in millisecond.
01934   * @retval HAL status
01935   */
01936 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
01937 {
01938   uint32_t tickstart;
01939
01940   /* Check the parameters */
01941   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01942   assert_param(IS_ADC_EVENT_TYPE(EventType));
01943
01944   tickstart = HAL_GetTick();
01945
01946   /* Check selected event flag */
01947   while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
01948   {
01949     /* Check if timeout is disabled (set to infinite wait) */
01950     if(Timeout != HAL_MAX_DELAY)
01951     {
01952       if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
01953       {
01954         /* Update ADC state machine to timeout */
01955         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01956
01957         /* Process unlocked */
01958         __HAL_UNLOCK(hadc);
01959
01960         return HAL_ERROR;
01961       }
01962     }
01963   }
01964
01965   /* Analog watchdog (level out of window) event */
01966     /* Set ADC state */
01967     SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
01968
01969   /* Clear ADC analog watchdog flag */
01970   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
01971
01972   /* Return ADC state */
01973   return HAL_OK;
01974 }
01975 #endif /* STM32F373xC || STM32F378xx */
01976
01977 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
01978     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
01979     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
01980     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01981 /**
01982   * @brief  Enables ADC, starts conversion of regular group with interruption.
01983   *         Interruptions enabled in this function:
01984   *          - EOC (end of conversion of regular group) or EOS (end of
01985   *            sequence of regular group) depending on ADC initialization
01986   *            parameter "EOCSelection"
01987   *          - overrun, depending on ADC initialization parameter "Overrun"
01988   *         Each of these interruptions has its dedicated callback function.
01989   * @note   Case of multimode enabled (for devices with several ADCs): This
01990   *         function must be called for ADC slave first, then ADC master.
01991   *         For ADC slave, ADC is enabled only (conversion is not started).
01992   *         For ADC master, ADC is enabled and multimode conversion is started.
01993   * @param  hadc ADC handle
01994   * @retval HAL status
01995   */
01996 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
01997 {
01998   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01999
02000   /* Check the parameters */
02001   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02002
02003   /* Perform ADC enable and conversion start if no conversion is on going */
02004   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
02005   {
02006     /* Process locked */
02007     __HAL_LOCK(hadc);
02008
02009     /* Enable the ADC peripheral */
02010     tmp_hal_status = ADC_Enable(hadc);
02011
02012     /* Start conversion if ADC is effectively enabled */
02013     if (tmp_hal_status == HAL_OK)
02014     {
02015       /* Set ADC state                                                        */
02016       /* - Clear state bitfield related to regular group conversion results   */
02017       /* - Set state bitfield related to regular operation                    */
02018       ADC_STATE_CLR_SET(hadc->State,
02019                         HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
02020                         HAL_ADC_STATE_REG_BUSY);
02021
02022       /* Set group injected state (from auto-injection) and multimode state   */
02023       /* for all cases of multimode: independent mode, multimode ADC master   */
02024       /* or multimode ADC slave (for devices with several ADCs):              */
02025       if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
02026       {
02027         /* Set ADC state (ADC independent or master) */
02028         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
02029
02030         /* If conversions on group regular are also triggering group injected,*/
02031         /* update ADC state.                                                  */
02032         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
02033         {
02034           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
02035         }
02036       }
02037       else
02038       {
02039         /* Set ADC state (ADC slave) */
02040         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
02041
02042         /* If conversions on group regular are also triggering group injected,*/
02043         /* update ADC state.                                                  */
02044         if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
02045         {
02046           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
02047         }
02048       }
02049
02050       /* State machine update: Check if an injected conversion is ongoing */
02051       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
02052       {
02053         /* Reset ADC error code fields related to conversions on group regular*/
02054         CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
02055       }
02056       else
02057       {
02058         /* Reset ADC all error code fields */
02059         ADC_CLEAR_ERRORCODE(hadc);
02060       }
02061
02062       /* Process unlocked */
02063       /* Unlock before starting ADC conversions: in case of potential         */
02064       /* interruption, to let the process to ADC IRQ Handler.                 */
02065       __HAL_UNLOCK(hadc);
02066
02067       /* Clear regular group conversion flag and overrun flag */
02068       /* (To ensure of no unknown state from potential previous ADC           */
02069       /* operations)                                                          */
02070       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
02071
02072       /* Enable ADC end of conversion interrupt */
02073       /* Enable ADC overrun interrupt */
02074       switch(hadc->Init.EOCSelection)
02075       {
02076         case ADC_EOC_SEQ_CONV:
02077           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
02078           __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS));
02079           break;
02080         /* case ADC_EOC_SINGLE_CONV */
02081         default:
02082           __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS));
02083           break;
02084       }
02085
02086       /* If overrun is set to overwrite previous data (default setting),      */
02087       /* overrun interrupt is not activated (overrun event is not considered  */
02088       /* as an error).                                                        */
02089       /* (cf ref manual "Managing conversions without using the DMA and       */
02090       /* without overrun ")                                                   */
02091       if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
02092       {
02093         __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
02094       }
02095
02096       /* Enable conversion of regular group.                                  */
02097       /* If software start has been selected, conversion starts immediately.  */
02098       /* If external trigger has been selected, conversion will start at next */
02099       /* trigger event.                                                       */
02100       /* Case of multimode enabled (for devices with several ADCs):           */
02101       /*  - if ADC is slave, ADC is enabled only (conversion is not started). */
02102       /*  - if ADC is master, ADC is enabled and conversion is started.       */
02103       if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
02104       {
02105         SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
02106       }
02107     }
02108     else
02109     {
02110       /* Process unlocked */
02111       __HAL_UNLOCK(hadc);
02112     }
02113   }
02114   else
02115   {
02116     tmp_hal_status = HAL_BUSY;
02117   }
02118
02119   /* Return function status */
02120   return tmp_hal_status;
02121 }
02122 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02123        /* STM32F302xC || STM32F303xC || STM32F358xx || */
02124        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02125        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
02126
02127 #if defined(STM32F373xC) || defined(STM32F378xx)
02128 /**
02129   * @brief  Enables ADC, starts conversion of regular group with interruption.
02130   *         Interruptions enabled in this function:
02131   *          - EOC (end of conversion of regular group)
02132   *         Each of these interruptions has its dedicated callback function.
02133   * @param  hadc ADC handle
02134   * @retval HAL status
02135   */
02136 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
02137 {
02138   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02139
02140   /* Check the parameters */
02141   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02142
02143   /* Process locked */
02144   __HAL_LOCK(hadc);
02145
02146   /* Enable the ADC peripheral */
02147   tmp_hal_status = ADC_Enable(hadc);
02148
02149   /* Start conversion if ADC is effectively enabled */
02150   if (tmp_hal_status == HAL_OK)
02151   {
02152     /* Set ADC state                                                          */
02153     /* - Clear state bitfield related to regular group conversion results     */
02154     /* - Set state bitfield related to regular operation                      */
02155     ADC_STATE_CLR_SET(hadc->State,
02156                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
02157                       HAL_ADC_STATE_REG_BUSY);
02158
02159     /* Set group injected state (from auto-injection) */
02160     /* If conversions on group regular are also triggering group injected,    */
02161     /* update ADC state.                                                      */
02162     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
02163     {
02164       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
02165     }
02166
02167     /* State machine update: Check if an injected conversion is ongoing */
02168     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
02169     {
02170       /* Reset ADC error code fields related to conversions on group regular */
02171       CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
02172     }
02173     else
02174     {
02175       /* Reset ADC all error code fields */
02176       ADC_CLEAR_ERRORCODE(hadc);
02177     }
02178
02179     /* Process unlocked */
02180     /* Unlock before starting ADC conversions: in case of potential           */
02181     /* interruption, to let the process to ADC IRQ Handler.                   */
02182     __HAL_UNLOCK(hadc);
02183
02184     /* Clear regular group conversion flag and overrun flag */
02185     /* (To ensure of no unknown state from potential previous ADC operations) */
02186     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
02187
02188     /* Enable end of conversion interrupt for regular group */
02189     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
02190
02191     /* Enable conversion of regular group.                                    */
02192     /* If software start has been selected, conversion starts immediately.    */
02193     /* If external trigger has been selected, conversion will start at next   */
02194     /* trigger event.                                                         */
02195     if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
02196     {
02197       /* Start ADC conversion on regular group with SW start */
02198       SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
02199     }
02200     else
02201     {
02202       /* Start ADC conversion on regular group with external trigger */
02203       SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
02204     }
02205   }
02206
02207   /* Return function status */
02208   return tmp_hal_status;
02209 }
02210 #endif /* STM32F373xC || STM32F378xx */
02211
02212 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
02213     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
02214     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
02215     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02216 /**
02217   * @brief  Stop ADC conversion of both groups regular and injected,
02218   *         disable ADC peripheral.
02219   *         Interruptions disabled in this function:
02220   *          - EOC (end of conversion of regular group) and EOS (end of
02221   *            sequence of regular group)
02222   *          - overrun
02223   * @note   ADC peripheral disable is forcing interruption of potential
02224   *         conversion on injected group. If injected group is under use,
02225   *         it should be preliminarily stopped using function
02226   *         @ref HAL_ADCEx_InjectedStop().
02227   *         To stop ADC conversion only on ADC group regular
02228   *         while letting ADC group injected conversions running,
02229   *         use function @ref HAL_ADCEx_RegularStop_IT().
02230   * @param  hadc ADC handle
02231   * @retval HAL status.
02232   */
02233 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
02234 {
02235   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02236
02237   /* Check the parameters */
02238   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02239
02240   /* Process locked */
02241   __HAL_LOCK(hadc);
02242
02243   /* 1. Stop potential conversion on going, on regular and injected groups */
02244   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
02245
02246   /* Disable ADC peripheral if conversions are effectively stopped */
02247   if (tmp_hal_status == HAL_OK)
02248   {
02249     /* Disable ADC end of conversion interrupt for regular group */
02250     /* Disable ADC overrun interrupt */
02251     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
02252
02253     /* 2. Disable the ADC peripheral */
02254     tmp_hal_status = ADC_Disable(hadc);
02255
02256     /* Check if ADC is effectively disabled */
02257     if (tmp_hal_status == HAL_OK)
02258     {
02259       /* Set ADC state */
02260       ADC_STATE_CLR_SET(hadc->State,
02261                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
02262                         HAL_ADC_STATE_READY);
02263     }
02264   }
02265
02266   /* Process unlocked */
02267   __HAL_UNLOCK(hadc);
02268
02269   /* Return function status */
02270   return tmp_hal_status;
02271 }
02272 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02273        /* STM32F302xC || STM32F303xC || STM32F358xx || */
02274        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02275        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
02276
02277 #if defined(STM32F373xC) || defined(STM32F378xx)
02278 /**
02279   * @brief  Stop ADC conversion of regular group (and injected group in
02280   *         case of auto_injection mode), disable interrution of
02281   *         end-of-conversion, disable ADC peripheral.
02282   * @param  hadc ADC handle
02283   * @retval None
02284   */
02285 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
02286 {
02287   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02288
02289   /* Check the parameters */
02290   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02291
02292   /* Process locked */
02293   __HAL_LOCK(hadc);
02294
02295   /* Stop potential conversion on going, on regular and injected groups */
02296   /* Disable ADC peripheral */
02297   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
02298
02299   /* Check if ADC is effectively disabled */
02300   if (tmp_hal_status == HAL_OK)
02301   {
02302     /* Disable ADC end of conversion interrupt for regular group */
02303     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
02304
02305     /* Set ADC state */
02306     ADC_STATE_CLR_SET(hadc->State,
02307                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
02308                       HAL_ADC_STATE_READY);
02309   }
02310
02311   /* Process unlocked */
02312   __HAL_UNLOCK(hadc);
02313
02314   /* Return function status */
02315   return tmp_hal_status;
02316 }
02317 #endif /* STM32F373xC || STM32F378xx */
02318
02319 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
02320     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
02321     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
02322     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02323 /**
02324   * @brief  Enables ADC, starts conversion of regular group and transfers result
02325   *         through DMA.
02326   *         Interruptions enabled in this function:
02327   *          - DMA transfer complete
02328   *          - DMA half transfer
02329   *          - overrun
02330   *         Each of these interruptions has its dedicated callback function.
02331   * @note   Case of multimode enabled (for devices with several ADCs): This
02332   *         function is for single-ADC mode only. For multimode, use the
02333   *         dedicated MultimodeStart function.
02334   * @param  hadc ADC handle
02335   * @param  pData The destination Buffer address.
02336   * @param  Length The length of data to be transferred from ADC peripheral to memory.
02337   * @retval None
02338   */
02339 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
02340 {
02341   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02342
02343   /* Check the parameters */
02344   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02345
02346   /* Perform ADC enable and conversion start if no conversion is on going */
02347   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
02348   {
02349     /* Process locked */
02350     __HAL_LOCK(hadc);
02351
02352     /* Verification if multimode is disabled (for devices with several ADC)   */
02353     /* If multimode is enabled, dedicated function multimode conversion       */
02354     /* start DMA must be used.                                                */
02355     if(ADC_COMMON_CCR_MULTI(hadc) == RESET)
02356     {
02357       /* Enable the ADC peripheral */
02358       tmp_hal_status = ADC_Enable(hadc);
02359
02360       /* Start conversion if ADC is effectively enabled */
02361       if (tmp_hal_status == HAL_OK)
02362       {
02363         /* Set ADC state                                                      */
02364         /* - Clear state bitfield related to regular group conversion results */
02365         /* - Set state bitfield related to regular operation                  */
02366         ADC_STATE_CLR_SET(hadc->State,
02367                           HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
02368                           HAL_ADC_STATE_REG_BUSY);
02369
02370         /* Set group injected state (from auto-injection) and multimode state */
02371         /* for all cases of multimode: independent mode, multimode ADC master */
02372         /* or multimode ADC slave (for devices with several ADCs):            */
02373         if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
02374         {
02375           /* Set ADC state (ADC independent or master) */
02376           CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
02377
02378           /* If conversions on group regular are also triggering group injected,*/
02379           /* update ADC state.                                                  */
02380           if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
02381           {
02382             ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
02383           }
02384         }
02385         else
02386         {
02387           /* Set ADC state (ADC slave) */
02388           SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
02389
02390           /* If conversions on group regular are also triggering group injected,*/
02391           /* update ADC state.                                                  */
02392           if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
02393           {
02394             ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
02395           }
02396         }
02397
02398         /* State machine update: Check if an injected conversion is ongoing */
02399         if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
02400         {
02401           /* Reset ADC error code fields related to conversions on group regular*/
02402           CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
02403         }
02404         else
02405         {
02406           /* Reset ADC all error code fields */
02407           ADC_CLEAR_ERRORCODE(hadc);
02408         }
02409
02410         /* Process unlocked */
02411         /* Unlock before starting ADC conversions: in case of potential         */
02412         /* interruption, to let the process to ADC IRQ Handler.                 */
02413         __HAL_UNLOCK(hadc);
02414
02415
02416         /* Set the DMA transfer complete callback */
02417         hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
02418
02419         /* Set the DMA half transfer complete callback */
02420         hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
02421
02422         /* Set the DMA error callback */
02423         hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
02424
02425
02426         /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
02427         /* start (in case of SW start):                                       */
02428
02429         /* Clear regular group conversion flag and overrun flag */
02430         /* (To ensure of no unknown state from potential previous ADC         */
02431         /* operations)                                                        */
02432         __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
02433
02434         /* Enable ADC overrun interrupt */
02435         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
02436
02437         /* Enable ADC DMA mode */
02438         SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
02439
02440         /* Start the DMA channel */
02441         HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
02442
02443         /* Enable conversion of regular group.                                */
02444         /* If software start has been selected, conversion starts immediately.*/
02445         /* If external trigger has been selected, conversion will start at    */
02446         /* next trigger event.                                                */
02447         SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
02448
02449       }
02450       else
02451       {
02452         /* Process unlocked */
02453         __HAL_UNLOCK(hadc);
02454       }
02455     }
02456     else
02457     {
02458       tmp_hal_status = HAL_ERROR;
02459
02460       /* Process unlocked */
02461       __HAL_UNLOCK(hadc);
02462     }
02463   }
02464   else
02465   {
02466     tmp_hal_status = HAL_BUSY;
02467   }
02468
02469   /* Return function status */
02470   return tmp_hal_status;
02471 }
02472 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02473        /* STM32F302xC || STM32F303xC || STM32F358xx || */
02474        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02475        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
02476
02477 #if defined(STM32F373xC) || defined(STM32F378xx)
02478 /**
02479   * @brief  Enables ADC, starts conversion of regular group and transfers result
02480   *         through DMA.
02481   *         Interruptions enabled in this function:
02482   *          - DMA transfer complete
02483   *          - DMA half transfer
02484   *         Each of these interruptions has its dedicated callback function.
02485   * @note   For devices with several ADCs: This function is for single-ADC mode
02486   *         only. For multimode, use the dedicated MultimodeStart function.
02487   * @param  hadc ADC handle
02488   * @param  pData The destination Buffer address.
02489   * @param  Length The length of data to be transferred from ADC peripheral to memory.
02490   * @retval None
02491   */
02492 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
02493 {
02494   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02495
02496   /* Check the parameters */
02497   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02498
02499   /* Process locked */
02500   __HAL_LOCK(hadc);
02501
02502   /* Enable the ADC peripheral */
02503   tmp_hal_status = ADC_Enable(hadc);
02504
02505   /* Start conversion if ADC is effectively enabled */
02506   if (tmp_hal_status == HAL_OK)
02507   {
02508     /* Set ADC state                                                          */
02509     /* - Clear state bitfield related to regular group conversion results     */
02510     /* - Set state bitfield related to regular operation                      */
02511     ADC_STATE_CLR_SET(hadc->State,
02512                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
02513                       HAL_ADC_STATE_REG_BUSY);
02514
02515     /* Set group injected state (from auto-injection) */
02516     /* If conversions on group regular are also triggering group injected,    */
02517     /* update ADC state.                                                      */
02518     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
02519     {
02520       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
02521     }
02522
02523     /* State machine update: Check if an injected conversion is ongoing */
02524     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
02525     {
02526       /* Reset ADC error code fields related to conversions on group regular */
02527       CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
02528     }
02529     else
02530     {
02531       /* Reset ADC all error code fields */
02532       ADC_CLEAR_ERRORCODE(hadc);
02533     }
02534
02535     /* Process unlocked */
02536     /* Unlock before starting ADC conversions: in case of potential           */
02537     /* interruption, to let the process to ADC IRQ Handler.                   */
02538     __HAL_UNLOCK(hadc);
02539
02540     /* Set the DMA transfer complete callback */
02541     hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
02542
02543     /* Set the DMA half transfer complete callback */
02544     hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
02545
02546     /* Set the DMA error callback */
02547     hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
02548
02549
02550     /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
02551     /* start (in case of SW start):                                           */
02552
02553     /* Clear regular group conversion flag and overrun flag */
02554     /* (To ensure of no unknown state from potential previous ADC operations) */
02555     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
02556
02557     /* Enable ADC DMA mode */
02558     hadc->Instance->CR2 |= ADC_CR2_DMA;
02559
02560     /* Start the DMA channel */
02561     HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
02562
02563     /* Enable conversion of regular group.                                    */
02564     /* If software start has been selected, conversion starts immediately.    */
02565     /* If external trigger has been selected, conversion will start at next   */
02566     /* trigger event.                                                         */
02567     /* Note: Alternate trigger for single conversion could be to force an     */
02568     /*       additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
02569     if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
02570     {
02571       /* Start ADC conversion on regular group with SW start */
02572       SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
02573     }
02574     else
02575     {
02576       /* Start ADC conversion on regular group with external trigger */
02577       SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
02578     }
02579   }
02580
02581   /* Return function status */
02582   return tmp_hal_status;
02583 }
02584 #endif /* STM32F373xC || STM32F378xx */
02585
02586 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
02587     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
02588     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
02589     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02590 /**
02591   * @brief  Stop ADC conversion of both groups regular and injected,
02592   *         disable ADC DMA transfer, disable ADC peripheral.
02593   *         Interruptions disabled in this function:
02594   *          - DMA transfer complete
02595   *          - DMA half transfer
02596   *          - overrun
02597   * @note   ADC peripheral disable is forcing interruption of potential
02598   *         conversion on injected group. If injected group is under use,
02599   *         it should be preliminarily stopped using function
02600   *         @ref HAL_ADCEx_InjectedStop().
02601   *         To stop ADC conversion only on ADC group regular
02602   *         while letting ADC group injected conversions running,
02603   *         use function @ref HAL_ADCEx_RegularStop_DMA().
02604   * @note   Case of multimode enabled (for devices with several ADCs): This
02605   *         function is for single-ADC mode only. For multimode, use the
02606   *         dedicated MultimodeStop function.
02607   * @param  hadc ADC handle
02608   * @retval HAL status.
02609   */
02610 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
02611 {
02612   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02613
02614   /* Check the parameters */
02615   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02616
02617   /* Process locked */
02618   __HAL_LOCK(hadc);
02619
02620   /* 1. Stop potential conversion on going, on regular and injected groups */
02621   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
02622
02623   /* Disable ADC peripheral if conversions are effectively stopped */
02624   if (tmp_hal_status == HAL_OK)
02625   {
02626     /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
02627     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
02628
02629     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
02630     /* while DMA transfer is on going)                                        */
02631     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
02632
02633     /* Check if DMA channel effectively disabled */
02634     if (tmp_hal_status != HAL_OK)
02635     {
02636       /* Update ADC state machine to error */
02637       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
02638     }
02639
02640     /* Disable ADC overrun interrupt */
02641     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
02642
02643     /* 2. Disable the ADC peripheral */
02644     /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
02645     /* to retain a potential failing status.                                  */
02646     if (tmp_hal_status == HAL_OK)
02647     {
02648       tmp_hal_status = ADC_Disable(hadc);
02649     }
02650     else
02651     {
02652       ADC_Disable(hadc);
02653     }
02654
02655     /* Check if ADC is effectively disabled */
02656     if (tmp_hal_status == HAL_OK)
02657     {
02658       /* Set ADC state */
02659       ADC_STATE_CLR_SET(hadc->State,
02660                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
02661                         HAL_ADC_STATE_READY);
02662     }
02663
02664   }
02665
02666   /* Process unlocked */
02667   __HAL_UNLOCK(hadc);
02668
02669   /* Return function status */
02670   return tmp_hal_status;
02671 }
02672 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02673        /* STM32F302xC || STM32F303xC || STM32F358xx || */
02674        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02675        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
02676
02677 #if defined(STM32F373xC) || defined(STM32F378xx)
02678 /**
02679   * @brief  Stop ADC conversion of regular group (and injected group in
02680   *         case of auto_injection mode), disable ADC DMA transfer, disable
02681   *         ADC peripheral.
02682   * @note   ADC peripheral disable is forcing interruption of potential
02683   *         conversion on injected group. If injected group is under use, it
02684   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
02685   * @note   For devices with several ADCs: This function is for single-ADC mode
02686   *         only. For multimode, use the dedicated MultimodeStop function.
02687   * @param  hadc ADC handle
02688   * @retval HAL status.
02689   */
02690 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
02691 {
02692   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02693
02694   /* Check the parameters */
02695   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02696
02697   /* Process locked */
02698   __HAL_LOCK(hadc);
02699
02700   /* Stop potential conversion on going, on regular and injected groups */
02701   /* Disable ADC peripheral */
02702   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
02703
02704   /* Check if ADC is effectively disabled */
02705   if (tmp_hal_status == HAL_OK)
02706   {
02707     /* Disable ADC DMA mode */
02708     hadc->Instance->CR2 &= ~ADC_CR2_DMA;
02709
02710     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
02711     /* while DMA transfer is on going)                                        */
02712     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
02713
02714     /* Check if DMA channel effectively disabled */
02715     if (tmp_hal_status == HAL_OK)
02716     {
02717       /* Set ADC state */
02718       ADC_STATE_CLR_SET(hadc->State,
02719                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
02720                         HAL_ADC_STATE_READY);
02721     }
02722     else
02723     {
02724       /* Update ADC state machine to error */
02725       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
02726     }
02727   }
02728
02729   /* Process unlocked */
02730   __HAL_UNLOCK(hadc);
02731
02732   /* Return function status */
02733   return tmp_hal_status;
02734 }
02735 #endif /* STM32F373xC || STM32F378xx */
02736
02737 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
02738     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
02739     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
02740     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02741 /**
02742   * @brief  Get ADC regular group conversion result.
02743   * @note   Reading register DR automatically clears ADC flag EOC
02744   *         (ADC group regular end of unitary conversion).
02745   * @note   This function does not clear ADC flag EOS
02746   *         (ADC group regular end of sequence conversion).
02747   *         Occurrence of flag EOS rising:
02748   *          - If sequencer is composed of 1 rank, flag EOS is equivalent
02749   *            to flag EOC.
02750   *          - If sequencer is composed of several ranks, during the scan
02751   *            sequence flag EOC only is raised, at the end of the scan sequence
02752   *            both flags EOC and EOS are raised.
02753   *         To clear this flag, either use function:
02754   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
02755   *         model polling: @ref HAL_ADC_PollForConversion()
02756   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
02757   * @param  hadc ADC handle
02758   * @retval ADC group regular conversion data
02759   */
02760 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
02761 {
02762   /* Check the parameters */
02763   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02764
02765   /* Note: ADC flag EOC is not cleared here by software because               */
02766   /*       automatically cleared by hardware when reading register DR.        */
02767
02768   /* Return ADC converted value */
02769   return hadc->Instance->DR;
02770 }
02771 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02772        /* STM32F302xC || STM32F303xC || STM32F358xx || */
02773        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02774        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
02775
02776 #if defined(STM32F373xC) || defined(STM32F378xx)
02777 /**
02778   * @brief  Get ADC regular group conversion result.
02779   * @note   Reading register DR automatically clears ADC flag EOC
02780   *         (ADC group regular end of unitary conversion).
02781   * @note   This function does not clear ADC flag EOS
02782   *         (ADC group regular end of sequence conversion).
02783   *         Occurrence of flag EOS rising:
02784   *          - If sequencer is composed of 1 rank, flag EOS is equivalent
02785   *            to flag EOC.
02786   *          - If sequencer is composed of several ranks, during the scan
02787   *            sequence flag EOC only is raised, at the end of the scan sequence
02788   *            both flags EOC and EOS are raised.
02789   *         To clear this flag, either use function:
02790   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
02791   *         model polling: @ref HAL_ADC_PollForConversion()
02792   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
02793   * @param  hadc ADC handle
02794   * @retval ADC group regular conversion data
02795   */
02796 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
02797 {
02798   /* Check the parameters */
02799   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02800
02801   /* Note: EOC flag is not cleared here by software because automatically     */
02802   /*       cleared by hardware when reading register DR.                      */
02803
02804   /* Return ADC converted value */
02805   return hadc->Instance->DR;
02806 }
02807 #endif /* STM32F373xC || STM32F378xx */
02808
02809 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
02810     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
02811     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
02812     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02813 /**
02814   * @brief  Handles ADC interrupt request.
02815   * @param  hadc ADC handle
02816   * @retval None
02817   */
02818 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
02819 {
02820   uint32_t overrun_error = 0U; /* flag set if overrun occurrence has to be considered as an error */
02821   ADC_Common_TypeDef *tmpADC_Common;
02822   uint32_t tmp_cfgr     = 0x0U;
02823   uint32_t tmp_cfgr_jqm = 0x0U;
02824
02825   /* Check the parameters */
02826   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02827   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
02828   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
02829
02830   /* ========== Check End of Conversion flag for regular group ========== */
02831   if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) ||
02832       (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS))   )
02833   {
02834     /* Update state machine on conversion status if not in error state */
02835     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
02836     {
02837       /* Set ADC state */
02838       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
02839     }
02840
02841     /* Get relevant register CFGR in ADC instance of ADC master or slave    */
02842     /* in function of multimode state (for devices with multimode           */
02843     /* available).                                                          */
02844     if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
02845     {
02846       tmp_cfgr = READ_REG(hadc->Instance->CFGR);
02847     }
02848     else
02849     {
02850       tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
02851     }
02852
02853     /* Disable interruption if no further conversion upcoming by regular      */
02854     /* external trigger or by continuous mode,                                */
02855     /* and if scan sequence if completed.                                     */
02856     if(ADC_IS_SOFTWARE_START_REGULAR(hadc)         &&
02857        (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == RESET)  )
02858     {
02859       /* If End of Sequence is reached, disable interrupts */
02860       if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
02861       {
02862         /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit           */
02863         /* ADSTART==0 (no conversion on going)                                */
02864         if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
02865         {
02866           /* Disable ADC end of sequence conversion interrupt */
02867           /* Note: Overrun interrupt was enabled with EOC interrupt in        */
02868           /* HAL_Start_IT(), but is not disabled here because can be used     */
02869           /* by overrun IRQ process below.                                    */
02870           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
02871
02872           /* Set ADC state */
02873           CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
02874
02875           if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
02876           {
02877             SET_BIT(hadc->State, HAL_ADC_STATE_READY);
02878           }
02879         }
02880         else
02881         {
02882           /* Update ADC state machine to error */
02883           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02884
02885           /* Set ADC error code to ADC IP internal error */
02886           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02887         }
02888       }
02889     }
02890
02891     /* Conversion complete callback */
02892     /* Note: into callback, to determine if conversion has been triggered     */
02893     /*       from EOC or EOS, possibility to use:                             */
02894     /*        " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) "                */
02895       HAL_ADC_ConvCpltCallback(hadc);
02896
02897
02898     /* Clear regular group conversion flag */
02899     /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of         */
02900     /*       conversion flags clear induces the release of the preserved      */
02901     /*       data.                                                            */
02902     /*       Therefore, if the preserved data value is needed, it must be     */
02903     /*       read preliminarily into HAL_ADC_ConvCpltCallback().              */
02904     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
02905   }
02906
02907
02908   /* ========== Check End of Conversion flag for injected group ========== */
02909   if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) ||
02910       (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOS))   )
02911   {
02912     /* Set ADC state */
02913     SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
02914
02915     /* Get relevant register CFGR in ADC instance of ADC master or slave      */
02916     /* in function of multimode state (for devices with multimode             */
02917     /* available).                                                            */
02918     if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
02919     {
02920       tmp_cfgr = READ_REG(hadc->Instance->CFGR);
02921     }
02922     else
02923     {
02924       tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
02925     }
02926
02927     /* Disable interruption if no further conversion upcoming by injected     */
02928     /* external trigger or by automatic injected conversion with regular      */
02929     /* group having no further conversion upcoming (same conditions as        */
02930     /* regular group interruption disabling above),                           */
02931     /* and if injected scan sequence is completed.                            */
02932     if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                   ||
02933        ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET)    &&
02934         (ADC_IS_SOFTWARE_START_REGULAR(hadc)          &&
02935         (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET)   )   )   )
02936     {
02937       /* If End of Sequence is reached, disable interrupts */
02938       if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
02939       {
02940
02941         /* Get relevant register CFGR in ADC instance of ADC master or slave  */
02942         /* in function of multimode state (for devices with multimode         */
02943         /* available).                                                        */
02944         if (ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc))
02945         {
02946           tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR);
02947         }
02948         else
02949         {
02950           tmp_cfgr_jqm = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
02951         }
02952
02953         /* Particular case if injected contexts queue is enabled:             */
02954         /* when the last context has been fully processed, JSQR is reset      */
02955         /* by the hardware. Even if no injected conversion is planned to come */
02956         /* (queue empty, triggers are ignored), it can start again            */
02957         /* immediately after setting a new context (JADSTART is still set).   */
02958         /* Therefore, state of HAL ADC injected group is kept to busy.        */
02959         if(READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) == RESET)
02960         {
02961           /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit       */
02962           /* JADSTART==0 (no conversion on going)                             */
02963           if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
02964           {
02965             /* Disable ADC end of sequence conversion interrupt  */
02966             __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
02967
02968             /* Set ADC state */
02969             CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
02970
02971             if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
02972             {
02973               SET_BIT(hadc->State, HAL_ADC_STATE_READY);
02974             }
02975           }
02976           else
02977           {
02978             /* Update ADC state machine to error */
02979             SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02980
02981             /* Set ADC error code to ADC IP internal error */
02982             SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02983           }
02984         }
02985       }
02986     }
02987
02988     /* Conversion complete callback */
02989     /* Note: into callback, to determine if conversion has been triggered     */
02990     /*       from JEOC or JEOS, possibility to use:                           */
02991     /*        " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) "               */
02992     HAL_ADCEx_InjectedConvCpltCallback(hadc);
02993
02994     /* Clear injected group conversion flag */
02995     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
02996   }
02997
02998   /* ========== Check analog watchdog 1 flag ========== */
02999   if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD1) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD1))
03000   {
03001     /* Set ADC state */
03002     SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
03003
03004     /* Level out of window 1 callback */
03005     HAL_ADC_LevelOutOfWindowCallback(hadc);
03006     /* Clear ADC analog watchdog flag */
03007     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
03008   }
03009
03010   /* ========== Check analog watchdog 2 flag ========== */
03011   if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD2) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD2))
03012   {
03013     /* Set ADC state */
03014     SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
03015
03016     /* Level out of window 2 callback */
03017     HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
03018     /* Clear ADC analog watchdog flag */
03019     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
03020   }
03021
03022   /* ========== Check analog watchdog 3 flag ========== */
03023   if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD3) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD3))
03024   {
03025     /* Set ADC state */
03026     SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
03027
03028     /* Level out of window 3 callback */
03029     HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
03030     /* Clear ADC analog watchdog flag */
03031     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
03032   }
03033
03034   /* ========== Check Overrun flag ========== */
03035   if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
03036   {
03037     /* If overrun is set to overwrite previous data (default setting),        */
03038     /* overrun event is not considered as an error.                           */
03039     /* (cf ref manual "Managing conversions without using the DMA and         */
03040     /* without overrun ")                                                     */
03041     /* Exception for usage with DMA overrun event always considered as an     */
03042     /* error.                                                                 */
03043     if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
03044     {
03045       overrun_error = 1U;
03046     }
03047     else
03048     {
03049       /* Pointer to the common control register to which is belonging hadc    */
03050       /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
03051       /* control registers)                                                   */
03052       tmpADC_Common = ADC_COMMON_REGISTER(hadc);
03053
03054       /* Check DMA configuration, depending on MultiMode set or not */
03055       if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT)
03056       {
03057         if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
03058         {
03059           overrun_error = 1U;
03060         }
03061       }
03062       else
03063       {
03064         /* MultiMode is enabled, Common Control Register MDMA bits must be checked */
03065         if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET)
03066         {
03067           overrun_error = 1U;
03068         }
03069       }
03070     }
03071
03072     if (overrun_error == 1U)
03073     {
03074       /* Update ADC state machine to error */
03075       SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
03076
03077       /* Set ADC error code to ADC IP internal error */
03078       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
03079
03080       /* Error callback */
03081       HAL_ADC_ErrorCallback(hadc);
03082     }
03083
03084     /* Clear the Overrun flag */
03085     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
03086
03087   }
03088
03089
03090   /* ========== Check Injected context queue overflow flag ========== */
03091   if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JQOVF) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JQOVF))
03092   {
03093       /* Update ADC state machine to error */
03094       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
03095
03096       /* Set ADC error code to ADC IP internal error */
03097       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
03098
03099     /* Clear the Injected context queue overflow flag */
03100     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
03101
03102     /* Error callback */
03103     HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
03104   }
03105
03106 }
03107 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
03108        /* STM32F302xC || STM32F303xC || STM32F358xx || */
03109        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
03110        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
03111
03112 #if defined(STM32F373xC) || defined(STM32F378xx)
03113 /**
03114   * @brief  Handles ADC interrupt request
03115   * @param  hadc ADC handle
03116   * @retval None
03117   */
03118 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
03119 {
03120   /* Check the parameters */
03121   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03122   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
03123   assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
03124
03125
03126   /* ========== Check End of Conversion flag for regular group ========== */
03127   if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
03128   {
03129     if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
03130     {
03131       /* Update state machine on conversion status if not in error state */
03132       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
03133       {
03134         /* Set ADC state */
03135         SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
03136       }
03137
03138       /* Determine whether any further conversion upcoming on group regular   */
03139       /* by external trigger, continuous mode or scan sequence on going.      */
03140       /* Note: On STM32F37x devices, in case of sequencer enabled             */
03141       /*       (several ranks selected), end of conversion flag is raised     */
03142       /*       at the end of the sequence.                                    */
03143       if(ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&
03144          (hadc->Init.ContinuousConvMode == DISABLE)  )
03145       {
03146         /* Disable ADC end of single conversion interrupt  */
03147         __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
03148
03149         /* Set ADC state */
03150         CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
03151
03152         if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
03153         {
03154           SET_BIT(hadc->State, HAL_ADC_STATE_READY);
03155         }
03156       }
03157
03158       /* Conversion complete callback */
03159       HAL_ADC_ConvCpltCallback(hadc);
03160
03161       /* Clear regular group conversion flag */
03162       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
03163     }
03164   }
03165
03166   /* ========== Check End of Conversion flag for injected group ========== */
03167   if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
03168   {
03169     if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
03170     {
03171       /* Update state machine on conversion status if not in error state */
03172       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
03173       {
03174         /* Set ADC state */
03175         SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
03176       }
03177
03178       /* Determine whether any further conversion upcoming on group injected  */
03179       /* by external trigger, scan sequence on going or by automatic injected */
03180       /* conversion from group regular (same conditions as group regular      */
03181       /* interruption disabling above).                                       */
03182       /* Note: On STM32F37x devices, in case of sequencer enabled             */
03183       /*       (several ranks selected), end of conversion flag is raised     */
03184       /*       at the end of the sequence.                                    */
03185       if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                     ||
03186          (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
03187          (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&
03188           (hadc->Init.ContinuousConvMode == DISABLE)  )         )   )
03189       {
03190         /* Disable ADC end of single conversion interrupt  */
03191         __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
03192
03193         /* Set ADC state */
03194         CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
03195
03196         if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
03197         {
03198           SET_BIT(hadc->State, HAL_ADC_STATE_READY);
03199         }
03200       }
03201
03202       /* Conversion complete callback */
03203       HAL_ADCEx_InjectedConvCpltCallback(hadc);
03204
03205       /* Clear injected group conversion flag */
03206       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
03207     }
03208   }
03209
03210   /* ========== Check Analog watchdog flags ========== */
03211   if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
03212   {
03213     if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
03214     {
03215       /* Set ADC state */
03216       SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
03217
03218       /* Level out of window callback */
03219       HAL_ADC_LevelOutOfWindowCallback(hadc);
03220
03221       /* Clear the ADC analog watchdog flag */
03222       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
03223     }
03224   }
03225
03226 }
03227 #endif /* STM32F373xC || STM32F378xx */
03228
03229
03230 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
03231     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
03232     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
03233     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
03234 /**
03235   * @brief  Perform an ADC automatic self-calibration
03236   *         Calibration prerequisite: ADC must be disabled (execute this
03237   *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
03238   * @param  hadc ADC handle
03239   * @param  SingleDiff Selection of single-ended or differential input
03240   *          This parameter can be one of the following values:
03241   *            @arg ADC_SINGLE_ENDED: Channel in mode input single ended
03242   *            @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
03243   * @retval HAL status
03244   */
03245 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
03246 {
03247   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
03248   uint32_t tickstart;
03249
03250   /* Check the parameters */
03251   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03252   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
03253
03254   /* Process locked */
03255   __HAL_LOCK(hadc);
03256
03257   /* Calibration prerequisite: ADC must be disabled. */
03258
03259   /* Disable the ADC (if not already disabled) */
03260   tmp_hal_status = ADC_Disable(hadc);
03261
03262   /* Check if ADC is effectively disabled */
03263   if (tmp_hal_status == HAL_OK)
03264   {
03265     /* Change ADC state */
03266     hadc->State = HAL_ADC_STATE_READY;
03267
03268     /* Select calibration mode single ended or differential ended */
03269     hadc->Instance->CR &= (~ADC_CR_ADCALDIF);
03270     if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
03271     {
03272       hadc->Instance->CR |= ADC_CR_ADCALDIF;
03273     }
03274
03275     /* Start ADC calibration */
03276     hadc->Instance->CR |= ADC_CR_ADCAL;
03277
03278     tickstart = HAL_GetTick();
03279
03280     /* Wait for calibration completion */
03281     while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
03282     {
03283       if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
03284       {
03285         /* Update ADC state machine to error */
03286         ADC_STATE_CLR_SET(hadc->State,
03287                           HAL_ADC_STATE_BUSY_INTERNAL,
03288                           HAL_ADC_STATE_ERROR_INTERNAL);
03289
03290         /* Process unlocked */
03291         __HAL_UNLOCK(hadc);
03292
03293         return HAL_ERROR;
03294       }
03295     }
03296
03297     /* Set ADC state */
03298     ADC_STATE_CLR_SET(hadc->State,
03299                       HAL_ADC_STATE_BUSY_INTERNAL,
03300                       HAL_ADC_STATE_READY);
03301   }
03302
03303   /* Process unlocked */
03304   __HAL_UNLOCK(hadc);
03305
03306   /* Return function status */
03307   return tmp_hal_status;
03308 }
03309 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
03310        /* STM32F302xC || STM32F303xC || STM32F358xx || */
03311        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
03312        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
03313
03314 #if defined(STM32F373xC) || defined(STM32F378xx)
03315 /**
03316   * @brief  Perform an ADC automatic self-calibration
03317   *         Calibration prerequisite: ADC must be disabled (execute this
03318   *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
03319   *         During calibration process, ADC is enabled. ADC is let enabled at
03320   *         the completion of this function.
03321   * @param  hadc ADC handle
03322   * @retval HAL status
03323   */
03324 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
03325 {
03326   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
03327   uint32_t tickstart;
03328   __IO uint32_t wait_loop_index = 0U;
03329
03330   /* Check the parameters */
03331   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03332
03333   /* Process locked */
03334   __HAL_LOCK(hadc);
03335
03336   /* 1. Calibration prerequisite:                                             */
03337   /*    - ADC must be disabled for at least two ADC clock cycles in disable   */
03338   /*      mode before ADC enable                                              */
03339   /* Stop potential conversion on going, on regular and injected groups       */
03340   /* Disable ADC peripheral */
03341   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
03342
03343   /* Check if ADC is effectively disabled */
03344   if (tmp_hal_status == HAL_OK)
03345   {
03346     /* Set ADC state */
03347     ADC_STATE_CLR_SET(hadc->State,
03348                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
03349                       HAL_ADC_STATE_BUSY_INTERNAL);
03350
03351     /* Wait two ADC clock cycles */
03352     while(wait_loop_index < ADC_CYCLE_WORST_CASE_CPU_CYCLES *2U)
03353     {
03354       wait_loop_index++;
03355     }
03356
03357     /* 2. Enable the ADC peripheral */
03358     ADC_Enable(hadc);
03359
03360
03361     /* 3. Resets ADC calibration registers */
03362     SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
03363
03364     tickstart = HAL_GetTick();
03365
03366     /* Wait for calibration reset completion */
03367     while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
03368     {
03369       if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
03370       {
03371         /* Update ADC state machine to error */
03372         ADC_STATE_CLR_SET(hadc->State,
03373                           HAL_ADC_STATE_BUSY_INTERNAL,
03374                           HAL_ADC_STATE_ERROR_INTERNAL);
03375
03376         /* Process unlocked */
03377         __HAL_UNLOCK(hadc);
03378
03379         return HAL_ERROR;
03380       }
03381     }
03382
03383
03384     /* 4. Start ADC calibration */
03385     SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
03386
03387     tickstart = HAL_GetTick();
03388
03389     /* Wait for calibration completion */
03390     while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
03391     {
03392       if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
03393       {
03394         /* Update ADC state machine to error */
03395         ADC_STATE_CLR_SET(hadc->State,
03396                           HAL_ADC_STATE_BUSY_INTERNAL,
03397                           HAL_ADC_STATE_ERROR_INTERNAL);
03398
03399         /* Process unlocked */
03400         __HAL_UNLOCK(hadc);
03401
03402         return HAL_ERROR;
03403       }
03404     }
03405
03406     /* Set ADC state */
03407     ADC_STATE_CLR_SET(hadc->State,
03408                       HAL_ADC_STATE_BUSY_INTERNAL,
03409                       HAL_ADC_STATE_READY);
03410   }
03411
03412   /* Process unlocked */
03413   __HAL_UNLOCK(hadc);
03414
03415   /* Return function status */
03416   return tmp_hal_status;
03417 }
03418
03419 #endif /* STM32F373xC || STM32F378xx */
03420
03421 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
03422     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
03423     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
03424     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
03425 /**
03426   * @brief  Get the calibration factor from automatic conversion result
03427   * @param  hadc ADC handle
03428   * @param  SingleDiff Selection of single-ended or differential input
03429   *          This parameter can be one of the following values:
03430   *            @arg ADC_SINGLE_ENDED: Channel in mode input single ended
03431   *            @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
03432   * @retval Converted value
03433   */
03434 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
03435 {
03436   /* Check the parameters */
03437   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03438   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
03439
03440   /* Return the selected ADC calibration value */
03441   if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
03442   {
03443     return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT);
03444   }
03445   else
03446   {
03447     return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S);
03448   }
03449 }
03450 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
03451        /* STM32F302xC || STM32F303xC || STM32F358xx || */
03452        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
03453        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
03454
03455 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
03456     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
03457     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
03458     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
03459 /**
03460   * @brief  Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going.
03461   * @param  hadc ADC handle
03462   * @param  SingleDiff Selection of single-ended or differential input
03463   *          This parameter can be one of the following values:
03464   *            @arg ADC_SINGLE_ENDED: Channel in mode input single ended
03465   *            @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
03466   * @param  CalibrationFactor Calibration factor (coded on 7 bits maximum)
03467   * @retval HAL state
03468   */
03469 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
03470 {
03471   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
03472
03473   /* Check the parameters */
03474   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03475   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
03476   assert_param(IS_ADC_CALFACT(CalibrationFactor));
03477
03478   /* Process locked */
03479   __HAL_LOCK(hadc);
03480
03481   /* Verification of hardware constraints before modifying the calibration    */
03482   /* factors register: ADC must be enabled, no conversion on going.           */
03483   if ( (ADC_IS_ENABLE(hadc) != RESET)                              &&
03484        (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)   )
03485   {
03486     /* Set the selected ADC calibration value */
03487     if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
03488     {
03489       MODIFY_REG(hadc->Instance->CALFACT                ,
03490                  ADC_CALFACT_CALFACT_D                  ,
03491                  ADC_CALFACT_DIFF_SET(CalibrationFactor) );
03492     }
03493     else
03494     {
03495       MODIFY_REG(hadc->Instance->CALFACT,
03496                  ADC_CALFACT_CALFACT_S  ,
03497                  CalibrationFactor       );
03498     }
03499   }
03500   else
03501   {
03502     /* Update ADC state machine to error */
03503     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
03504
03505     /* Set ADC error code to ADC IP internal error */
03506     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03507   }
03508
03509   /* Process unlocked */
03510   __HAL_UNLOCK(hadc);
03511
03512   /* Return function status */
03513   return tmp_hal_status;
03514 }
03515 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
03516        /* STM32F302xC || STM32F303xC || STM32F358xx || */
03517        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
03518        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
03519
03520 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
03521     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
03522     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
03523     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
03524 /**
03525   * @brief  Enables ADC, starts conversion of injected group.
03526   *         Interruptions enabled in this function: None.
03527   * @note   Case of multimode enabled (for devices with several ADCs): This
03528   *         function must be called for ADC slave first, then ADC master.
03529   *         For ADC slave, ADC is enabled only (conversion is not started).
03530   *         For ADC master, ADC is enabled and multimode conversion is started.
03531   * @param  hadc ADC handle
03532   * @retval HAL status
03533   */
03534 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
03535 {
03536   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
03537
03538   /* Check the parameters */
03539   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03540
03541   /* Perform ADC enable and conversion start if no conversion is on going */
03542   if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
03543   {
03544     /* Process locked */
03545     __HAL_LOCK(hadc);
03546
03547     /* Enable the ADC peripheral */
03548     tmp_hal_status = ADC_Enable(hadc);
03549
03550       /* Start conversion if ADC is effectively enabled */
03551     if (tmp_hal_status == HAL_OK)
03552     {
03553       /* Set ADC state                                                        */
03554       /* - Clear state bitfield related to injected group conversion results  */
03555       /* - Set state bitfield related to injected operation                   */
03556       ADC_STATE_CLR_SET(hadc->State,
03557                         HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
03558                         HAL_ADC_STATE_INJ_BUSY);
03559
03560       /* Case of independent mode or multimode(for devices with several ADCs):*/
03561       /* Set multimode state.                                                 */
03562       if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
03563       {
03564         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
03565       }
03566       else
03567       {
03568         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
03569       }
03570
03571       /* Check if a regular conversion is ongoing */
03572       /* Note: On this device, there is no ADC error code fields related to   */
03573       /*       conversions on group injected only. In case of conversion on   */
03574       /*       going on group regular, no error code is reset.                */
03575       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
03576       {
03577         /* Reset ADC all error code fields */
03578         ADC_CLEAR_ERRORCODE(hadc);
03579       }
03580
03581       /* Process unlocked */
03582       /* Unlock before starting ADC conversions: in case of potential         */
03583       /* interruption, to let the process to ADC IRQ Handler.                 */
03584       __HAL_UNLOCK(hadc);
03585
03586       /* Clear injected group conversion flag */
03587       /* (To ensure of no unknown state from potential previous ADC           */
03588       /* operations)                                                          */
03589       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
03590
03591       /* Enable conversion of injected group, if automatic injected           */
03592       /* conversion is disabled.                                              */
03593       /* If software start has been selected, conversion starts immediately.  */
03594       /* If external trigger has been selected, conversion will start at next */
03595       /* trigger event.                                                       */
03596       /* Case of multimode enabled (for devices with several ADCs):           */
03597       /*  - if ADC is slave, ADC is enabled only (conversion is not started). */
03598       /*  - if ADC is master, ADC is enabled and conversion is started.       */
03599       if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) &&
03600           ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc)          )
03601       {
03602         SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART);
03603       }
03604     }
03605     else
03606     {
03607       /* Process unlocked */
03608       __HAL_UNLOCK(hadc);
03609     }
03610   }
03611   else
03612   {
03613     tmp_hal_status = HAL_BUSY;
03614   }
03615
03616   /* Return function status */
03617   return tmp_hal_status;
03618 }
03619 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
03620        /* STM32F302xC || STM32F303xC || STM32F358xx || */
03621        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
03622        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
03623
03624 #if defined(STM32F373xC) || defined(STM32F378xx)
03625 /**
03626   * @brief  Enables ADC, starts conversion of injected group.
03627   *         Interruptions enabled in this function: None.
03628   * @param  hadc ADC handle
03629   * @retval HAL status
03630   */
03631 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
03632 {
03633   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
03634
03635   /* Check the parameters */
03636   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03637
03638   /* Process locked */
03639   __HAL_LOCK(hadc);
03640
03641   /* Enable the ADC peripheral */
03642   tmp_hal_status = ADC_Enable(hadc);
03643
03644   /* Start conversion if ADC is effectively enabled */
03645   if (tmp_hal_status == HAL_OK)
03646   {
03647     /* Set ADC state                                                          */
03648     /* - Clear state bitfield related to injected group conversion results    */
03649     /* - Set state bitfield related to injected operation                     */
03650     ADC_STATE_CLR_SET(hadc->State,
03651                       HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
03652                       HAL_ADC_STATE_INJ_BUSY);
03653
03654     /* Check if a regular conversion is ongoing */
03655     /* Note: On this device, there is no ADC error code fields related to     */
03656     /*       conversions on group injected only. In case of conversion on     */
03657     /*       going on group regular, no error code is reset.                  */
03658     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
03659     {
03660       /* Reset ADC all error code fields */
03661       ADC_CLEAR_ERRORCODE(hadc);
03662     }
03663
03664     /* Process unlocked */
03665     /* Unlock before starting ADC conversions: in case of potential           */
03666     /* interruption, to let the process to ADC IRQ Handler.                   */
03667     __HAL_UNLOCK(hadc);
03668
03669     /* Clear injected group conversion flag */
03670     /* (To ensure of no unknown state from potential previous ADC operations) */
03671     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
03672
03673     /* Enable conversion of injected group.                                   */
03674     /* If software start has been selected, conversion starts immediately.    */
03675     /* If external trigger has been selected, conversion will start at next   */
03676     /* trigger event.                                                         */
03677     /* If external trigger has been selected, conversion will start at next   */
03678     /* trigger event.                                                         */
03679     /* If automatic injected conversion is enabled, conversion will start     */
03680     /* after next regular group conversion.                                   */
03681     if (ADC_IS_SOFTWARE_START_INJECTED(hadc)               &&
03682         HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
03683     {
03684       /* Start ADC conversion on injected group with SW start */
03685       SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
03686     }
03687     else
03688     {
03689       /* Start ADC conversion on injected group with external trigger */
03690       SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
03691     }
03692   }
03693
03694   /* Return function status */
03695   return tmp_hal_status;
03696 }
03697 #endif /* STM32F373xC || STM32F378xx */
03698
03699 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
03700     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
03701     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
03702     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
03703 /**
03704   * @brief  Stop ADC group injected conversion (potential conversion on going
03705   *         on ADC group regular is not impacted), disable ADC peripheral
03706   *         if no conversion is on going on group regular.
03707   * @note   To stop ADC conversion of both groups regular and injected and to
03708   *         to disable ADC peripheral, instead of using 2 functions
03709   *         @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
03710   *         use function @ref HAL_ADC_Stop().
03711   * @note   If injected group mode auto-injection is enabled,
03712   *         function HAL_ADC_Stop must be used.
03713   * @note   Case of multimode enabled (for devices with several ADCs): This
03714   *         function must be called for ADC master first, then ADC slave.
03715   *         For ADC master, conversion is stopped and ADC is disabled.
03716   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
03717   *         has already stopped conversion of ADC slave).
03718   * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
03719   * @param  hadc ADC handle
03720   * @retval None
03721   */
03722 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
03723 {
03724   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
03725
03726   /* Check the parameters */
03727   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03728
03729   /* Process locked */
03730   __HAL_LOCK(hadc);
03731
03732   /* Stop potential ADC conversion on going and disable ADC peripheral        */
03733   /* conditioned to:                                                          */
03734   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
03735   /* - For ADC injected group conversion stop:                                */
03736   /*   On this STM32 family, conversion on the other group                    */
03737   /*   (group regular) can continue (groups regular and injected              */
03738   /*   conversion stop commands are independent)                              */
03739   /* - For ADC disable:                                                       */
03740   /*   No conversion on the other group (group regular) must be intended to   */
03741   /*   continue (groups regular and injected are both impacted by             */
03742   /*   ADC disable)                                                           */
03743   if(HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
03744   {
03745     /* 1. Stop potential conversion on going on injected group only. */
03746     tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
03747
03748     /* Disable ADC peripheral if conversion on ADC group injected is          */
03749     /* effectively stopped and if no conversion on the other group            */
03750     /* (ADC group regular) is intended to continue.                           */
03751     if (tmp_hal_status == HAL_OK)
03752     {
03753       if((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) &&
03754          ((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)    )
03755       {
03756         /* 2. Disable the ADC peripheral */
03757         tmp_hal_status = ADC_Disable(hadc);
03758
03759         /* Check if ADC is effectively disabled */
03760         if (tmp_hal_status == HAL_OK)
03761         {
03762           /* Set ADC state */
03763           ADC_STATE_CLR_SET(hadc->State,
03764                             HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
03765                             HAL_ADC_STATE_READY);
03766         }
03767       }
03768       /* Conversion on ADC group injected group is stopped, but ADC is not    */
03769       /* disabled since conversion on ADC group regular is still on going.    */
03770       else
03771       {
03772         /* Set ADC state */
03773         CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
03774       }
03775     }
03776   }
03777   else
03778   {
03779     /* Update ADC state machine to error */
03780     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
03781
03782     tmp_hal_status = HAL_ERROR;
03783   }
03784
03785   /* Process unlocked */
03786   __HAL_UNLOCK(hadc);
03787
03788   /* Return function status */
03789   return tmp_hal_status;
03790 }
03791 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
03792        /* STM32F302xC || STM32F303xC || STM32F358xx || */
03793        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
03794        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
03795
03796 #if defined(STM32F373xC) || defined(STM32F378xx)
03797 /**
03798   * @brief  Stop conversion of injected channels. Disable ADC peripheral if
03799   *         no regular conversion is on going.
03800   * @note   If ADC must be disabled and if conversion is on going on
03801   *         regular group, function HAL_ADC_Stop must be used to stop both
03802   *         injected and regular groups, and disable the ADC.
03803   * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
03804   * @param  hadc ADC handle
03805   * @retval None
03806   */
03807 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
03808 {
03809   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
03810
03811   /* Check the parameters */
03812   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03813
03814   /* Process locked */
03815   __HAL_LOCK(hadc);
03816
03817   /* Stop potential conversion and disable ADC peripheral                     */
03818   /* Conditioned to:                                                          */
03819   /* - No conversion on the other group (regular group) is intended to        */
03820   /*   continue (injected and regular groups stop conversion and ADC disable  */
03821   /*   are common)                                                            */
03822   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
03823   if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
03824      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
03825   {
03826     /* Stop potential conversion on going, on regular and injected groups */
03827     /* Disable ADC peripheral */
03828     tmp_hal_status = ADC_ConversionStop_Disable(hadc);
03829
03830     /* Check if ADC is effectively disabled */
03831     if (tmp_hal_status == HAL_OK)
03832     {
03833       /* Set ADC state */
03834       ADC_STATE_CLR_SET(hadc->State,
03835                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
03836                         HAL_ADC_STATE_READY);
03837     }
03838   }
03839   else
03840   {
03841     /* Update ADC state machine to error */
03842     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
03843
03844     tmp_hal_status = HAL_ERROR;
03845   }
03846
03847   /* Process unlocked */
03848   __HAL_UNLOCK(hadc);
03849
03850   /* Return function status */
03851   return tmp_hal_status;
03852 }
03853 #endif /* STM32F373xC || STM32F378xx */
03854
03855 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
03856     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
03857     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
03858     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
03859 /**
03860   * @brief  Wait for injected group conversion to be completed.
03861   * @param  hadc ADC handle
03862   * @param  Timeout Timeout value in millisecond.
03863   * @retval HAL status
03864   */
03865 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
03866 {
03867   uint32_t tickstart;
03868   uint32_t tmp_Flag_EOC;
03869   uint32_t tmp_cfgr = 0x00000000U;
03870
03871   /* Check the parameters */
03872   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03873
03874   /* If end of conversion selected to end of sequence */
03875   if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
03876   {
03877     tmp_Flag_EOC = ADC_FLAG_JEOS;
03878   }
03879   /* If end of conversion selected to end of each conversion */
03880   else /* ADC_EOC_SINGLE_CONV */
03881   {
03882     tmp_Flag_EOC = (ADC_FLAG_JEOC | ADC_FLAG_JEOS);
03883   }
03884
03885   /* Get relevant register CFGR in ADC instance of ADC master or slave      */
03886   /* in function of multimode state (for devices with multimode             */
03887   /* available).                                                            */
03888   if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
03889   {
03890     tmp_cfgr = READ_REG(hadc->Instance->CFGR);
03891   }
03892   else
03893   {
03894     tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
03895   }
03896
03897   /* Get tick count */
03898   tickstart = HAL_GetTick();
03899
03900   /* Wait until End of Conversion flag is raised */
03901   while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
03902   {
03903     /* Check if timeout is disabled (set to infinite wait) */
03904     if(Timeout != HAL_MAX_DELAY)
03905     {
03906       if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
03907       {
03908         /* Update ADC state machine to timeout */
03909         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
03910
03911         /* Process unlocked */
03912         __HAL_UNLOCK(hadc);
03913
03914         return HAL_TIMEOUT;
03915       }
03916     }
03917   }
03918
03919   /* Update ADC state machine */
03920   SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
03921
03922   /* Determine whether any further conversion upcoming on group injected      */
03923   /* by external trigger or by automatic injected conversion                  */
03924   /* from group regular.                                                      */
03925   if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                   ||
03926      ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET)    &&
03927       (ADC_IS_SOFTWARE_START_REGULAR(hadc)          &&
03928       (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET)   )   )   )
03929   {
03930     /* Set ADC state */
03931     CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
03932
03933     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
03934     {
03935       SET_BIT(hadc->State, HAL_ADC_STATE_READY);
03936     }
03937   }
03938
03939   /* Clear end of conversion flag of injected group if low power feature      */
03940   /* "Auto Wait" is disabled, to not interfere with this feature until data   */
03941   /* register is read using function HAL_ADC_GetValue().                      */
03942   if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
03943   {
03944     /* Clear injected group conversion flag */
03945     /* (JEOC or JEOS depending on HAL ADC initialization parameter) */
03946     __HAL_ADC_CLEAR_FLAG(hadc, tmp_Flag_EOC);
03947   }
03948
03949   /* Return ADC state */
03950   return HAL_OK;
03951 }
03952 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
03953        /* STM32F302xC || STM32F303xC || STM32F358xx || */
03954        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
03955        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
03956
03957 #if defined(STM32F373xC) || defined(STM32F378xx)
03958 /**
03959   * @brief  Wait for injected group conversion to be completed.
03960   * @param  hadc ADC handle
03961   * @param  Timeout Timeout value in millisecond.
03962   * @retval HAL status
03963   */
03964 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
03965 {
03966   uint32_t tickstart = 0U;
03967
03968   /* Variables for polling in case of scan mode enabled */
03969   uint32_t Conversion_Timeout_CPU_cycles_max =0U;
03970   uint32_t Conversion_Timeout_CPU_cycles =0U;
03971
03972   /* Check the parameters */
03973   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03974
03975   /* Get tick count */
03976   tickstart = HAL_GetTick();
03977
03978   /* Polling for end of conversion: differentiation if single/sequence        */
03979   /* conversion.                                                              */
03980   /* For injected group, flag JEOC is set only at the end of the sequence,    */
03981   /* not for each conversion within the sequence.                             */
03982   /*  - If single conversion for injected group (scan mode disabled or        */
03983   /*    InjectedNbrOfConversion ==1U), flag JEOC is used to determine the      */
03984   /*    conversion completion.                                                */
03985   /*  - If sequence conversion for injected group (scan mode enabled and      */
03986   /*    InjectedNbrOfConversion >=2U), flag JEOC is set only at the end of the */
03987   /*    sequence.                                                             */
03988   /*    To poll for each conversion, the maximum conversion time is computed  */
03989   /*    from ADC conversion time (selected sampling time + conversion time of */
03990   /*    12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on    */
03991   /*    settings, conversion time range can be from 28 to 32256 CPU cycles).  */
03992   /*    As flag JEOC is not set after each conversion, no timeout status can  */
03993   /*    be set.                                                               */
03994   if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET)
03995   {
03996     /* Wait until End of Conversion flag is raised */
03997     while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
03998     {
03999       /* Check if timeout is disabled (set to infinite wait) */
04000       if(Timeout != HAL_MAX_DELAY)
04001       {
04002         if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
04003         {
04004           /* Update ADC state machine to timeout */
04005           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
04006
04007           /* Process unlocked */
04008           __HAL_UNLOCK(hadc);
04009
04010           return HAL_TIMEOUT;
04011         }
04012       }
04013     }
04014   }
04015   else
04016   {
04017     /* Replace polling by wait for maximum conversion time */
04018     /* Calculation of CPU cycles corresponding to ADC conversion cycles.      */
04019     /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all  */
04020     /* channels.                                                              */
04021     Conversion_Timeout_CPU_cycles_max = ADC_CLOCK_PRESCALER_RANGE();
04022     Conversion_Timeout_CPU_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc);
04023
04024     /* Poll with maximum conversion time */
04025     while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
04026     {
04027       /* Check if timeout is disabled (set to infinite wait) */
04028       if(Timeout != HAL_MAX_DELAY)
04029       {
04030         if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
04031         {
04032           /* Update ADC state machine to timeout */
04033           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
04034
04035           /* Process unlocked */
04036           __HAL_UNLOCK(hadc);
04037
04038           return HAL_TIMEOUT;
04039         }
04040       }
04041       Conversion_Timeout_CPU_cycles ++;
04042     }
04043   }
04044
04045
04046   /* Clear injected group conversion flag (and regular conversion flag raised simultaneously) */
04047   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC);
04048
04049   /* Update ADC state machine */
04050   SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
04051
04052   /* Determine whether any further conversion upcoming on group injected      */
04053   /* by external trigger or by automatic injected conversion                  */
04054   /* from group regular.                                                      */
04055   if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                     ||
04056      (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
04057      (ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
04058       (hadc->Init.ContinuousConvMode == DISABLE)   )        )   )
04059   {
04060     /* Set ADC state */
04061     CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
04062
04063     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
04064     {
04065       SET_BIT(hadc->State, HAL_ADC_STATE_READY);
04066     }
04067   }
04068
04069   /* Return ADC state */
04070   return HAL_OK;
04071 }
04072 #endif /* STM32F373xC || STM32F378xx */
04073
04074 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
04075     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
04076     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
04077     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
04078 /**
04079   * @brief  Enables ADC, starts conversion of injected group with interruption.
04080   *         Interruptions enabled in this function:
04081   *          - JEOC (end of conversion of injected group) or JEOS (end of
04082   *            sequence of injected group) depending on ADC initialization
04083   *            parameter "EOCSelection"
04084   *         Each of these interruptions has its dedicated callback function.
04085   * @note   Case of multimode enabled (for devices with several ADCs): This
04086   *         function must be called for ADC slave first, then ADC master.
04087   *         For ADC slave, ADC is enabled only (conversion is not started).
04088   *         For ADC master, ADC is enabled and multimode conversion is started.
04089   * @param  hadc ADC handle
04090   * @retval HAL status.
04091   */
04092 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
04093 {
04094   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
04095
04096   /* Check the parameters */
04097   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
04098
04099   /* Perform ADC enable and conversion start if no conversion is on going */
04100   if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
04101   {
04102     /* Process locked */
04103     __HAL_LOCK(hadc);
04104
04105     /* Enable the ADC peripheral */
04106     tmp_hal_status = ADC_Enable(hadc);
04107
04108     /* Start conversion if ADC is effectively enabled */
04109       /* Start conversion if ADC is effectively enabled */
04110     if (tmp_hal_status == HAL_OK)
04111     {
04112       /* Set ADC state                                                        */
04113       /* - Clear state bitfield related to injected group conversion results  */
04114       /* - Set state bitfield related to injected operation                   */
04115       ADC_STATE_CLR_SET(hadc->State,
04116                         HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
04117                         HAL_ADC_STATE_INJ_BUSY);
04118
04119       /* Case of independent mode or multimode(for devices with several ADCs):*/
04120       /* Set multimode state.                                                 */
04121       if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
04122       {
04123         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
04124       }
04125       else
04126       {
04127         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
04128       }
04129
04130       /* Check if a regular conversion is ongoing */
04131       /* Note: On this device, there is no ADC error code fields related to   */
04132       /*       conversions on group injected only. In case of conversion on   */
04133       /*       going on group regular, no error code is reset.                */
04134       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
04135       {
04136         /* Reset ADC all error code fields */
04137         ADC_CLEAR_ERRORCODE(hadc);
04138       }
04139
04140       /* Process unlocked */
04141       /* Unlock before starting ADC conversions: in case of potential         */
04142       /* interruption, to let the process to ADC IRQ Handler.                 */
04143       __HAL_UNLOCK(hadc);
04144
04145       /* Clear injected group conversion flag */
04146       /* (To ensure of no unknown state from potential previous ADC           */
04147       /* operations)                                                          */
04148       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
04149
04150       /* Enable ADC Injected context queue overflow interrupt if this feature */
04151       /* is enabled.                                                          */
04152       if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET)
04153       {
04154         __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
04155       }
04156
04157       /* Enable ADC end of conversion interrupt */
04158       switch(hadc->Init.EOCSelection)
04159       {
04160         case ADC_EOC_SEQ_CONV:
04161           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
04162           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
04163           break;
04164         /* case ADC_EOC_SINGLE_CONV */
04165         default:
04166           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
04167           break;
04168       }
04169
04170       /* Enable conversion of injected group, if automatic injected           */
04171       /* conversion is disabled.                                              */
04172       /* If software start has been selected, conversion starts immediately.  */
04173       /* If external trigger has been selected, conversion will start at next */
04174       /* trigger event.                                                       */
04175       /* Case of multimode enabled (for devices with several ADCs):           */
04176       /*  - if ADC is slave, ADC is enabled only (conversion is not started). */
04177       /*  - if ADC is master, ADC is enabled and conversion is started.       */
04178       if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) &&
04179           ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc)          )
04180       {
04181         SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART);
04182       }
04183     }
04184     else
04185     {
04186       /* Process unlocked */
04187       __HAL_UNLOCK(hadc);
04188     }
04189   }
04190   else
04191   {
04192     tmp_hal_status = HAL_BUSY;
04193   }
04194
04195   /* Return function status */
04196   return tmp_hal_status;
04197 }
04198 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
04199        /* STM32F302xC || STM32F303xC || STM32F358xx || */
04200        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
04201        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
04202
04203 #if defined(STM32F373xC) || defined(STM32F378xx)
04204 /**
04205   * @brief  Enables ADC, starts conversion of injected group with interruption.
04206   *         Interruptions enabled in this function:
04207   *          - JEOC (end of conversion of injected group)
04208   *         Each of these interruptions has its dedicated callback function.
04209   * @param  hadc ADC handle
04210   * @retval HAL status.
04211   */
04212 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
04213 {
04214   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
04215
04216   /* Check the parameters */
04217   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
04218
04219   /* Process locked */
04220   __HAL_LOCK(hadc);
04221
04222   /* Enable the ADC peripheral */
04223   tmp_hal_status = ADC_Enable(hadc);
04224
04225   /* Start conversion if ADC is effectively enabled */
04226   if (tmp_hal_status == HAL_OK)
04227   {
04228     /* Set ADC state                                                          */
04229     /* - Clear state bitfield related to injected group conversion results    */
04230     /* - Set state bitfield related to injected operation                     */
04231     ADC_STATE_CLR_SET(hadc->State,
04232                       HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
04233                       HAL_ADC_STATE_INJ_BUSY);
04234
04235     /* Check if a regular conversion is ongoing */
04236     /* Note: On this device, there is no ADC error code fields related to     */
04237     /*       conversions on group injected only. In case of conversion on     */
04238     /*       going on group regular, no error code is reset.                  */
04239     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
04240     {
04241       /* Reset ADC all error code fields */
04242       ADC_CLEAR_ERRORCODE(hadc);
04243     }
04244
04245     /* Process unlocked */
04246     /* Unlock before starting ADC conversions: in case of potential           */
04247     /* interruption, to let the process to ADC IRQ Handler.                   */
04248     __HAL_UNLOCK(hadc);
04249
04250     /* Set ADC error code to none */
04251     ADC_CLEAR_ERRORCODE(hadc);
04252
04253     /* Clear injected group conversion flag */
04254     /* (To ensure of no unknown state from potential previous ADC operations) */
04255     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
04256
04257     /* Enable end of conversion interrupt for injected channels */
04258     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
04259
04260     /* Enable conversion of injected group.                                   */
04261     /* If software start has been selected, conversion starts immediately.    */
04262     /* If external trigger has been selected, conversion will start at next   */
04263     /* trigger event.                                                         */
04264     /* If external trigger has been selected, conversion will start at next   */
04265     /* trigger event.                                                         */
04266     /* If automatic injected conversion is enabled, conversion will start     */
04267     /* after next regular group conversion.                                   */
04268     if (ADC_IS_SOFTWARE_START_INJECTED(hadc)              &&
04269         HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)  )
04270     {
04271       /* Start ADC conversion on injected group with SW start */
04272       SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
04273     }
04274     else
04275     {
04276       /* Start ADC conversion on injected group with external trigger */
04277       SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
04278     }
04279   }
04280
04281   /* Return function status */
04282   return tmp_hal_status;
04283 }
04284 #endif /* STM32F373xC || STM32F378xx */
04285
04286 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
04287     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
04288     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
04289     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
04290 /**
04291   * @brief  Stop ADC group injected conversion (potential conversion on going
04292   *         on ADC group regular is not impacted), disable ADC peripheral
04293   *         if no conversion is on going on group regular.
04294   *         Interruptions disabled in this function:
04295   *          - JEOC (end of conversion of injected group) and JEOS (end of
04296   *            sequence of injected group)
04297   * @note   To stop ADC conversion of both groups regular and injected and to
04298   *         to disable ADC peripheral, instead of using 2 functions
04299   *         @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
04300   *         use function @ref HAL_ADC_Stop().
04301   * @note   If injected group mode auto-injection is enabled,
04302   *         function HAL_ADC_Stop must be used.
04303   * @note   Case of multimode enabled (for devices with several ADCs): This
04304   *         function must be called for ADC master first, then ADC slave.
04305   *         For ADC master, conversion is stopped and ADC is disabled.
04306   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
04307   *         has already stopped conversion of ADC slave).
04308   * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
04309   * @param  hadc ADC handle
04310   * @retval None
04311   */
04312 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
04313 {
04314   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
04315
04316   /* Check the parameters */
04317   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
04318
04319   /* Process locked */
04320   __HAL_LOCK(hadc);
04321
04322   /* Stop potential ADC conversion on going and disable ADC peripheral        */
04323   /* conditioned to:                                                          */
04324   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
04325   /* - For ADC injected group conversion stop:                                */
04326   /*   On this STM32 family, conversion on the other group                    */
04327   /*   (group regular) can continue (groups regular and injected              */
04328   /*   conversion stop commands are independent)                              */
04329   /* - For ADC disable:                                                       */
04330   /*   No conversion on the other group (group regular) must be intended to   */
04331   /*   continue (groups regular and injected are both impacted by             */
04332   /*   ADC disable)                                                           */
04333   if(HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
04334   {
04335     /* 1. Stop potential conversion on going on injected group only. */
04336     tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
04337
04338     /* Disable ADC peripheral if conversion on ADC group injected is          */
04339     /* effectively stopped and if no conversion on the other group            */
04340     /* (ADC group regular) is intended to continue.                           */
04341     if (tmp_hal_status == HAL_OK)
04342     {
04343       /* Disable ADC end of conversion interrupt for injected channels */
04344       __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_IT_JQOVF));
04345
04346       if((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) &&
04347          ((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)    )
04348       {
04349         /* 2. Disable the ADC peripheral */
04350         tmp_hal_status = ADC_Disable(hadc);
04351
04352         /* Check if ADC is effectively disabled */
04353         if (tmp_hal_status == HAL_OK)
04354         {
04355           /* Set ADC state */
04356           ADC_STATE_CLR_SET(hadc->State,
04357                             HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
04358                             HAL_ADC_STATE_READY);
04359         }
04360       }
04361       /* Conversion on ADC group injected group is stopped, but ADC is not    */
04362       /* disabled since conversion on ADC group regular is still on going.    */
04363       else
04364       {
04365         /* Set ADC state */
04366         CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
04367       }
04368     }
04369   }
04370   else
04371   {
04372     /* Update ADC state machine to error */
04373     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
04374
04375     tmp_hal_status = HAL_ERROR;
04376   }
04377
04378   /* Process unlocked */
04379   __HAL_UNLOCK(hadc);
04380
04381   /* Return function status */
04382   return tmp_hal_status;
04383 }
04384 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
04385        /* STM32F302xC || STM32F303xC || STM32F358xx || */
04386        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
04387        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
04388
04389 #if defined(STM32F373xC) || defined(STM32F378xx)
04390 /**
04391   * @brief  Stop conversion of injected channels, disable interruption of
04392   *         end-of-conversion. Disable ADC peripheral if no regular conversion
04393   *         is on going.
04394   * @note   If ADC must be disabled and if conversion is on going on
04395   *         regular group, function HAL_ADC_Stop must be used to stop both
04396   *         injected and regular groups, and disable the ADC.
04397   * @param  hadc ADC handle
04398   * @retval None
04399   */
04400 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
04401 {
04402   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
04403
04404   /* Check the parameters */
04405   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
04406
04407   /* Process locked */
04408   __HAL_LOCK(hadc);
04409
04410   /* Stop potential conversion and disable ADC peripheral                     */
04411   /* Conditioned to:                                                          */
04412   /* - No conversion on the other group (regular group) is intended to        */
04413   /*   continue (injected and regular groups stop conversion and ADC disable  */
04414   /*   are common)                                                            */
04415   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
04416   if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
04417      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
04418   {
04419     /* Stop potential conversion on going, on regular and injected groups */
04420     /* Disable ADC peripheral */
04421     tmp_hal_status = ADC_ConversionStop_Disable(hadc);
04422
04423     /* Check if ADC is effectively disabled */
04424     if (tmp_hal_status == HAL_OK)
04425     {
04426       /* Disable ADC end of conversion interrupt for injected channels */
04427       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
04428
04429       /* Set ADC state */
04430       ADC_STATE_CLR_SET(hadc->State,
04431                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
04432                         HAL_ADC_STATE_READY);
04433     }
04434   }
04435   else
04436   {
04437     /* Update ADC state machine to error */
04438     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
04439
04440     tmp_hal_status = HAL_ERROR;
04441   }
04442
04443   /* Process unlocked */
04444   __HAL_UNLOCK(hadc);
04445
04446   /* Return function status */
04447   return tmp_hal_status;
04448 }
04449 #endif /* STM32F373xC || STM32F378xx */
04450
04451 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
04452     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
04453     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
04454 /**
04455   * @brief  With ADC configured in multimode, for ADC master:
04456   *         Enables ADC, starts conversion of regular group and transfers result
04457   *         through DMA.
04458   *         Multimode must have been previously configured using
04459   *         HAL_ADCEx_MultiModeConfigChannel() function.
04460   *         Interruptions enabled in this function:
04461   *          - DMA transfer complete
04462   *          - DMA half transfer
04463   *          - overrun
04464   *         Each of these interruptions has its dedicated callback function.
04465   * @note   ADC slave must be preliminarily enabled using single-mode
04466   *         HAL_ADC_Start() function.
04467   * @param  hadc ADC handle of ADC master (handle of ADC slave must not be used)
04468   * @param  pData The destination Buffer address.
04469   * @param  Length The length of data to be transferred from ADC peripheral to memory.
04470   * @retval None
04471   */
04472 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
04473 {
04474   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
04475   ADC_HandleTypeDef tmphadcSlave;
04476   ADC_Common_TypeDef *tmpADC_Common;
04477
04478   /* Check the parameters */
04479   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
04480   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
04481   assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
04482   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
04483
04484   /* Process locked */
04485   __HAL_LOCK(hadc);
04486
04487   /* Perform ADC enable and conversion start if no conversion is on going */
04488   /* (check on ADC master only) */
04489   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
04490   {
04491     /* Set a temporary handle of the ADC slave associated to the ADC master   */
04492     /* (Depending on STM32F3 product, there may be up to 2 ADC slaves)        */
04493     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
04494
04495     if (tmphadcSlave.Instance == NULL)
04496     {
04497       /* Update ADC state machine to error */
04498       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
04499
04500       /* Process unlocked */
04501       __HAL_UNLOCK(hadc);
04502
04503       return HAL_ERROR;
04504     }
04505
04506
04507     /* Enable the ADC peripherals: master and slave (in case if not already   */
04508     /* enabled previously)                                                    */
04509     tmp_hal_status = ADC_Enable(hadc);
04510     if (tmp_hal_status == HAL_OK)
04511     {
04512       tmp_hal_status = ADC_Enable(&tmphadcSlave);
04513     }
04514
04515     /* Start conversion all ADCs of multimode are effectively enabled */
04516     if (tmp_hal_status == HAL_OK)
04517     {
04518       /* Set ADC state (ADC master)                                           */
04519       /* - Clear state bitfield related to regular group conversion results   */
04520       /* - Set state bitfield related to regular operation                    */
04521       ADC_STATE_CLR_SET(hadc->State,
04522                         HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP | HAL_ADC_STATE_MULTIMODE_SLAVE,
04523                         HAL_ADC_STATE_REG_BUSY);
04524
04525       /* If conversions on group regular are also triggering group injected,  */
04526       /* update ADC state.                                                    */
04527       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
04528       {
04529         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
04530       }
04531
04532       /* Process unlocked */
04533       /* Unlock before starting ADC conversions: in case of potential         */
04534       /* interruption, to let the process to ADC IRQ Handler.                 */
04535       __HAL_UNLOCK(hadc);
04536
04537       /* Set ADC error code to none */
04538       ADC_CLEAR_ERRORCODE(hadc);
04539
04540
04541       /* Set the DMA transfer complete callback */
04542       hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
04543
04544       /* Set the DMA half transfer complete callback */
04545       hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
04546
04547       /* Set the DMA error callback */
04548       hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
04549
04550       /* Pointer to the common control register to which is belonging hadc    */
04551       /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
04552       /* control registers)                                                   */
04553       tmpADC_Common = ADC_COMMON_REGISTER(hadc);
04554
04555
04556       /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC   */
04557       /* start (in case of SW start):                                         */
04558
04559       /* Clear regular group conversion flag and overrun flag */
04560       /* (To ensure of no unknown state from potential previous ADC operations) */
04561       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
04562
04563       /* Enable ADC overrun interrupt */
04564       __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
04565
04566       /* Start the DMA channel */
04567       HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
04568
04569       /* Enable conversion of regular group.                                  */
04570       /* If software start has been selected, conversion starts immediately.  */
04571       /* If external trigger has been selected, conversion will start at next */
04572       /* trigger event.                                                       */
04573       SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
04574
04575     }
04576     else
04577     {
04578       /* Process unlocked */
04579       __HAL_UNLOCK(hadc);
04580     }
04581   }
04582   else
04583   {
04584     tmp_hal_status = HAL_BUSY;
04585   }
04586
04587   /* Return function status */
04588   return tmp_hal_status;
04589 }
04590
04591 /**
04592   * @brief  With ADC configured in multimode, for ADC master:
04593   *         Stop ADC group regular conversion (potential conversion on going
04594   *         on ADC group injected is not impacted),
04595   *         disable ADC DMA transfer, disable ADC peripheral
04596   *         if no conversion is on going on group injected.
04597   *         Interruptions disabled in this function:
04598   *          - DMA transfer complete
04599   *          - DMA half transfer
04600   *          - overrun
04601   * @note   In case of auto-injection mode, this function also stop conversion
04602   *         on ADC group injected.
04603   * @note   Multimode is kept enabled after this function. To disable multimode
04604   *         (set with HAL_ADCEx_MultiModeConfigChannel() ), ADC must be
04605   *         reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
04606   * @note   In case of DMA configured in circular mode, function
04607   *         HAL_ADC_Stop_DMA must be called after this function with handle of
04608   *         ADC slave, to properly disable the DMA channel of ADC slave.
04609   * @param  hadc ADC handle of ADC master (handle of ADC slave must not be used)
04610   * @retval None
04611   */
04612 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
04613 {
04614   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
04615   uint32_t tickstart;
04616   ADC_HandleTypeDef tmphadcSlave;
04617
04618   /* Check the parameters */
04619   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
04620
04621   /* Process locked */
04622   __HAL_LOCK(hadc);
04623
04624   /* 1. Stop potential multimode conversion on going, on regular and          */
04625   /*    injected groups.                                                      */
04626   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
04627
04628   /* Disable ADC peripheral if conversions are effectively stopped */
04629   if (tmp_hal_status == HAL_OK)
04630   {
04631     /* Set a temporary handle of the ADC slave associated to the ADC master   */
04632     /* (Depending on STM32F3 product, there may be up to 2 ADC slaves)        */
04633     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
04634
04635     if (tmphadcSlave.Instance == NULL)
04636     {
04637       /* Update ADC state machine (ADC master) to error */
04638       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
04639
04640       /* Process unlocked */
04641       __HAL_UNLOCK(hadc);
04642
04643       return HAL_ERROR;
04644     }
04645
04646     /* Procedure to disable the ADC peripheral: wait for conversions          */
04647     /* effectively stopped (ADC master and ADC slave), then disable ADC       */
04648
04649     /* 1. Wait until ADSTP=0 for ADC master and ADC slave */
04650     tickstart = HAL_GetTick();
04651
04652     while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)          ||
04653           ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave)   )
04654     {
04655       if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
04656       {
04657         /* Update ADC state machine (ADC master) to error */
04658         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
04659
04660         /* Process unlocked */
04661         __HAL_UNLOCK(hadc);
04662
04663         return HAL_ERROR;
04664       }
04665     }
04666
04667     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
04668     /* while DMA transfer is on going)                                        */
04669     /* Note: In case of ADC slave using its own DMA channel (multimode        */
04670     /*       parameter "DMAAccessMode" set to disabled):                      */
04671     /*       DMA channel of ADC slave should stopped after this function with */
04672     /*       function HAL_ADC_Stop_DMA.                                       */
04673     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
04674
04675     /* Check if DMA channel effectively disabled */
04676     if (tmp_hal_status != HAL_OK)
04677     {
04678       /* Update ADC state machine to error */
04679       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
04680     }
04681
04682     /* Disable ADC overrun interrupt */
04683     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
04684
04685
04686
04687     /* 2. Disable the ADC peripherals: master and slave */
04688     /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
04689     /* to retain a potential failing status.                                  */
04690     if (tmp_hal_status == HAL_OK)
04691     {
04692       /* Check if ADC are effectively disabled */
04693       if ((ADC_Disable(hadc) != HAL_ERROR)          &&
04694           (ADC_Disable(&tmphadcSlave) != HAL_ERROR)   )
04695       {
04696         tmp_hal_status = HAL_OK;
04697
04698         /* Change ADC state (ADC master) */
04699         ADC_STATE_CLR_SET(hadc->State,
04700                           HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
04701                           HAL_ADC_STATE_READY);
04702       }
04703     }
04704     else
04705     {
04706       /* In case of error, attempt to disable ADC instances anyway */
04707       ADC_Disable(hadc);
04708       ADC_Disable(&tmphadcSlave);
04709
04710       /* Update ADC state machine (ADC master) to error */
04711       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
04712     }
04713
04714   }
04715
04716   /* Process unlocked */
04717   __HAL_UNLOCK(hadc);
04718
04719   /* Return function status */
04720   return tmp_hal_status;
04721 }
04722
04723 /**
04724   * @brief  Returns the last ADC Master&Slave regular conversions results data
04725   *         in the selected multi mode.
04726   * @note   Reading register CDR does not clear flag ADC flag EOC
04727   *         (ADC group regular end of unitary conversion),
04728   *         as it is the case for independent mode data register.
04729   * @param  hadc ADC handle of ADC master (handle of ADC slave must not be used)
04730   * @retval The converted data value.
04731   */
04732 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
04733 {
04734   ADC_Common_TypeDef *tmpADC_Common;
04735
04736   /* Check the parameters */
04737   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
04738
04739   /* Pointer to the common control register to which is belonging hadc        */
04740   /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common     */
04741   /* control registers)                                                       */
04742   tmpADC_Common = ADC_COMMON_REGISTER(hadc);
04743
04744   /* Return the multi mode conversion value */
04745   return tmpADC_Common->CDR;
04746 }
04747 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
04748        /* STM32F302xC || STM32F303xC || STM32F358xx || */
04749        /* STM32F303x8 || STM32F334x8 || STM32F328xx    */
04750
04751 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
04752     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
04753     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
04754     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
04755 /**
04756   * @brief  Get ADC injected group conversion result.
04757   * @note   Reading register JDRx automatically clears ADC flag JEOC
04758   *         (ADC group injected end of unitary conversion).
04759   * @note   This function does not clear ADC flag JEOS
04760   *         (ADC group injected end of sequence conversion)
04761   *         Occurrence of flag JEOS rising:
04762   *          - If sequencer is composed of 1 rank, flag JEOS is equivalent
04763   *            to flag JEOC.
04764   *          - If sequencer is composed of several ranks, during the scan
04765   *            sequence flag JEOC only is raised, at the end of the scan sequence
04766   *            both flags JEOC and EOS are raised.
04767   *         Flag JEOS must not be cleared by this function because
04768   *         it would not be compliant with low power features
04769   *         (feature low power auto-wait, not available on all STM32 families).
04770   *         To clear this flag, either use function:
04771   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
04772   *         model polling: @ref HAL_ADCEx_InjectedPollForConversion()
04773   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
04774   * @param  hadc ADC handle
04775   * @param  InjectedRank the converted ADC injected rank.
04776   *          This parameter can be one of the following values:
04777   *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
04778   *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
04779   *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
04780   *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
04781   * @retval ADC group injected conversion data
04782   */
04783 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
04784 {
04785   uint32_t tmp_jdr = 0U;
04786
04787   /* Check the parameters */
04788   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
04789   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
04790
04791   /* Note: ADC flag JEOC is not cleared here by software because              */
04792   /*       automatically cleared by hardware when reading register JDRx.      */
04793
04794   /* Get ADC converted value */
04795   switch(InjectedRank)
04796   {
04797     case ADC_INJECTED_RANK_4:
04798       tmp_jdr = hadc->Instance->JDR4;
04799       break;
04800     case ADC_INJECTED_RANK_3:
04801       tmp_jdr = hadc->Instance->JDR3;
04802       break;
04803     case ADC_INJECTED_RANK_2:
04804       tmp_jdr = hadc->Instance->JDR2;
04805       break;
04806     case ADC_INJECTED_RANK_1:
04807     default:
04808       tmp_jdr = hadc->Instance->JDR1;
04809       break;
04810   }
04811
04812   /* Return ADC converted value */
04813   return tmp_jdr;
04814 }
04815 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
04816        /* STM32F302xC || STM32F303xC || STM32F358xx || */
04817        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
04818        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
04819
04820 #if defined(STM32F373xC) || defined(STM32F378xx)
04821 /**
04822   * @brief  Get ADC injected group conversion result.
04823   * @note   Reading register JDRx automatically clears ADC flag JEOC
04824   *         (ADC group injected end of unitary conversion).
04825   * @note   This function does not clear ADC flag JEOS
04826   *         (ADC group injected end of sequence conversion)
04827   *         Occurrence of flag JEOS rising:
04828   *          - If sequencer is composed of 1 rank, flag JEOS is equivalent
04829   *            to flag JEOC.
04830   *          - If sequencer is composed of several ranks, during the scan
04831   *            sequence flag JEOC only is raised, at the end of the scan sequence
04832   *            both flags JEOC and EOS are raised.
04833   *         Flag JEOS must not be cleared by this function because
04834   *         it would not be compliant with low power features
04835   *         (feature low power auto-wait, not available on all STM32 families).
04836   *         To clear this flag, either use function:
04837   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
04838   *         model polling: @ref HAL_ADCEx_InjectedPollForConversion()
04839   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
04840   * @param  hadc ADC handle
04841   * @param  InjectedRank the converted ADC injected rank.
04842   *          This parameter can be one of the following values:
04843   *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
04844   *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
04845   *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
04846   *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
04847   * @retval ADC group injected conversion data
04848   */
04849 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
04850 {
04851   uint32_t tmp_jdr = 0U;
04852
04853   /* Check the parameters */
04854   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
04855   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
04856
04857   /* Get ADC converted value */
04858   switch(InjectedRank)
04859   {
04860     case ADC_INJECTED_RANK_4:
04861       tmp_jdr = hadc->Instance->JDR4;
04862       break;
04863     case ADC_INJECTED_RANK_3:
04864       tmp_jdr = hadc->Instance->JDR3;
04865       break;
04866     case ADC_INJECTED_RANK_2:
04867       tmp_jdr = hadc->Instance->JDR2;
04868       break;
04869     case ADC_INJECTED_RANK_1:
04870     default:
04871       tmp_jdr = hadc->Instance->JDR1;
04872       break;
04873   }
04874
04875   /* Return ADC converted value */
04876   return tmp_jdr;
04877 }
04878 #endif /* STM32F373xC || STM32F378xx */
04879
04880 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
04881     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
04882     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
04883     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
04884 /**
04885   * @brief  Stop ADC group regular conversion (potential conversion on going
04886   *         on ADC group injected is not impacted), disable ADC peripheral
04887   *         if no conversion is on going on group injected.
04888   * @note   To stop ADC conversion of both groups regular and injected and to
04889   *         to disable ADC peripheral, instead of using 2 functions
04890   *         @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
04891   *         use function @ref HAL_ADC_Stop().
04892   * @note   In case of auto-injection mode, this function also stop conversion
04893   *         on ADC group injected.
04894   * @param  hadc ADC handle
04895   * @retval HAL status.
04896   */
04897 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
04898 {
04899   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
04900
04901   /* Check the parameters */
04902   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
04903
04904   /* Process locked */
04905   __HAL_LOCK(hadc);
04906
04907   /* Stop potential ADC conversion on going and disable ADC peripheral        */
04908   /* conditioned to:                                                          */
04909   /* - For ADC regular group conversion stop:                                 */
04910   /*   On this STM32 family, conversion on the other group                    */
04911   /*   (group injected) can continue (groups regular and injected             */
04912   /*   conversion stop commands are independent)                              */
04913   /* - For ADC disable:                                                       */
04914   /*   No conversion on the other group (group injected) must be intended to  */
04915   /*   continue (groups regular and injected are both impacted by             */
04916   /*   ADC disable)                                                           */
04917
04918   /* 1. Stop potential conversion on going, on regular group only */
04919   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
04920
04921   /* Disable ADC peripheral if conversion on ADC group regular is             */
04922   /* effectively stopped and if no conversion on the other group              */
04923   /* (ADC group injected) is intended to continue.                            */
04924   if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
04925      ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET)     )
04926   {
04927     /* 2. Disable the ADC peripheral */
04928     tmp_hal_status = ADC_Disable(hadc);
04929
04930     /* Check if ADC is effectively disabled */
04931     if (tmp_hal_status == HAL_OK)
04932     {
04933       /* Set ADC state */
04934       ADC_STATE_CLR_SET(hadc->State,
04935                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
04936                         HAL_ADC_STATE_READY);
04937     }
04938   }
04939   /* Conversion on ADC group regular group is stopped, but ADC is not         */
04940   /* disabled since conversion on ADC group injected is still on going.       */
04941   else
04942   {
04943     /* Set ADC state */
04944     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
04945   }
04946
04947   /* Process unlocked */
04948   __HAL_UNLOCK(hadc);
04949
04950   /* Return function status */
04951   return tmp_hal_status;
04952 }
04953
04954 /**
04955   * @brief  Stop ADC group regular conversion (potential conversion on going
04956   *         on ADC group injected is not impacted), disable ADC peripheral
04957   *         if no conversion is on going on group injected.
04958   *         Interruptions disabled in this function:
04959   *          - EOC (end of conversion of regular group) and EOS (end of
04960   *            sequence of regular group)
04961   *          - overrun
04962   * @note   To stop ADC conversion of both groups regular and injected and to
04963   *         to disable ADC peripheral, instead of using 2 functions
04964   *         @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
04965   *         use function @ref HAL_ADC_Stop().
04966   * @note   In case of auto-injection mode, this function also stop conversion
04967   *         on ADC group injected.
04968   * @param  hadc ADC handle
04969   * @retval HAL status.
04970   */
04971 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
04972 {
04973   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
04974
04975   /* Check the parameters */
04976   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
04977
04978   /* Process locked */
04979   __HAL_LOCK(hadc);
04980
04981   /* Stop potential ADC conversion on going and disable ADC peripheral        */
04982   /* conditioned to:                                                          */
04983   /* - For ADC regular group conversion stop:                                 */
04984   /*   On this STM32 family, conversion on the other group                    */
04985   /*   (group injected) can continue (groups regular and injected             */
04986   /*   conversion stop commands are independent)                              */
04987   /* - For ADC disable:                                                       */
04988   /*   No conversion on the other group (group injected) must be intended to  */
04989   /*   continue (groups regular and injected are both impacted by             */
04990   /*   ADC disable)                                                           */
04991
04992   /* 1. Stop potential conversion on going, on regular group only */
04993   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
04994
04995   /* Disable ADC peripheral if conversion on ADC group regular is             */
04996   /* effectively stopped and if no conversion on the other group              */
04997   /* (ADC group injected) is intended to continue.                            */
04998   if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
04999      ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET)     )
05000   {
05001     /* Disable ADC end of conversion interrupt for regular group */
05002     /* Disable ADC overrun interrupt */
05003     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
05004
05005     /* 2. Disable the ADC peripheral */
05006     tmp_hal_status = ADC_Disable(hadc);
05007
05008     /* Check if ADC is effectively disabled */
05009     if (tmp_hal_status == HAL_OK)
05010     {
05011       /* Set ADC state */
05012       ADC_STATE_CLR_SET(hadc->State,
05013                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
05014                         HAL_ADC_STATE_READY);
05015     }
05016   }
05017   /* Conversion on ADC group regular group is stopped, but ADC is not         */
05018   /* disabled since conversion on ADC group injected is still on going.       */
05019   else
05020   {
05021     /* Set ADC state */
05022     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
05023   }
05024
05025   /* Process unlocked */
05026   __HAL_UNLOCK(hadc);
05027
05028   /* Return function status */
05029   return tmp_hal_status;
05030 }
05031
05032 /**
05033   * @brief  Stop ADC group regular conversion (potential conversion on going
05034   *         on ADC group injected is not impacted),
05035   *         disable ADC DMA transfer, disable ADC peripheral
05036   *         if no conversion is on going on group injected.
05037   *         Interruptions disabled in this function:
05038   *          - DMA transfer complete
05039   *          - DMA half transfer
05040   *          - overrun
05041   * @note   To stop ADC conversion of both groups regular and injected and to
05042   *         to disable ADC peripheral, instead of using 2 functions
05043   *         @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
05044   *         use function @ref HAL_ADC_Stop().
05045   * @note   Case of multimode enabled (for devices with several ADCs): This
05046   *         function is for single-ADC mode only. For multimode, use the
05047   *         dedicated MultimodeStop function.
05048   * @param  hadc ADC handle
05049   * @retval HAL status.
05050   */
05051 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
05052 {
05053   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
05054
05055   /* Check the parameters */
05056   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
05057
05058   /* Process locked */
05059   __HAL_LOCK(hadc);
05060
05061   /* Stop potential ADC conversion on going and disable ADC peripheral        */
05062   /* conditioned to:                                                          */
05063   /* - For ADC regular group conversion stop:                                 */
05064   /*   On this STM32 family, conversion on the other group                    */
05065   /*   (group injected) can continue (groups regular and injected             */
05066   /*   conversion stop commands are independent)                              */
05067   /* - For ADC disable:                                                       */
05068   /*   No conversion on the other group (group injected) must be intended to  */
05069   /*   continue (groups regular and injected are both impacted by             */
05070   /*   ADC disable)                                                           */
05071
05072   /* 1. Stop potential conversion on going, on regular group only */
05073   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
05074
05075   /* Disable ADC peripheral if conversion on ADC group regular is             */
05076   /* effectively stopped and if no conversion on the other group              */
05077   /* (ADC group injected) is intended to continue.                            */
05078   if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
05079      ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET)     )
05080   {
05081     /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
05082     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
05083
05084     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
05085     /* while DMA transfer is on going)                                        */
05086     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
05087
05088     /* Check if DMA channel effectively disabled */
05089     if (tmp_hal_status != HAL_OK)
05090     {
05091       /* Update ADC state machine to error */
05092       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
05093     }
05094
05095     /* Disable ADC overrun interrupt */
05096     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
05097
05098     /* 2. Disable the ADC peripheral */
05099     /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
05100     /* to retain a potential failing status.                                  */
05101     if (tmp_hal_status == HAL_OK)
05102     {
05103       tmp_hal_status = ADC_Disable(hadc);
05104     }
05105     else
05106     {
05107       ADC_Disable(hadc);
05108     }
05109
05110     /* Check if ADC is effectively disabled */
05111     if (tmp_hal_status == HAL_OK)
05112     {
05113       /* Set ADC state */
05114       ADC_STATE_CLR_SET(hadc->State,
05115                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
05116                         HAL_ADC_STATE_READY);
05117     }
05118   }
05119   /* Conversion on ADC group regular group is stopped, but ADC is not         */
05120   /* disabled since conversion on ADC group injected is still on going.       */
05121   else
05122   {
05123     /* Set ADC state */
05124     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
05125   }
05126
05127   /* Process unlocked */
05128   __HAL_UNLOCK(hadc);
05129
05130   /* Return function status */
05131   return tmp_hal_status;
05132 }
05133
05134 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
05135     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
05136     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
05137 /**
05138   * @brief  With ADC configured in multimode, for ADC master:
05139   *         Stop ADC group regular conversion (potential conversion on going
05140   *         on ADC group injected is not impacted),
05141   *         disable ADC DMA transfer, disable ADC peripheral
05142   *         if no conversion is on going on group injected.
05143   *         Interruptions disabled in this function:
05144   *          - DMA transfer complete
05145   *          - DMA half transfer
05146   *          - overrun
05147   * @note   To stop ADC conversion of both groups regular and injected and to
05148   *         to disable ADC peripheral, instead of using 2 functions
05149   *         @ref HAL_ADCEx_RegularMultiModeStop_DMA() and
05150   *         @ref HAL_ADCEx_InjectedStop(), use function
05151   *         @ref HAL_ADCEx_MultiModeStop_DMA.
05152   * @note   In case of auto-injection mode, this function also stop conversion
05153   *         on ADC group injected.
05154   * @note   Multimode is kept enabled after this function. To disable multimode
05155   *         (set with HAL_ADCEx_MultiModeConfigChannel() ), ADC must be
05156   *         reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
05157   * @note   In case of DMA configured in circular mode, function
05158   *         HAL_ADC_Stop_DMA must be called after this function with handle of
05159   *         ADC slave, to properly disable the DMA channel of ADC slave.
05160   * @param  hadc ADC handle of ADC master (handle of ADC slave must not be used)
05161   * @retval None
05162   */
05163 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
05164 {
05165   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
05166   uint32_t tickstart;
05167   ADC_HandleTypeDef tmphadcSlave;
05168
05169   /* Check the parameters */
05170   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
05171
05172   /* Process locked */
05173   __HAL_LOCK(hadc);
05174
05175   /* Stop potential ADC conversion on going and disable ADC peripheral        */
05176   /* conditioned to:                                                          */
05177   /* - For ADC regular group conversion stop:                                 */
05178   /*   On this STM32 family, conversion on the other group                    */
05179   /*   (group injected) can continue (groups regular and injected             */
05180   /*   conversion stop commands are independent)                              */
05181   /* - For ADC disable:                                                       */
05182   /*   No conversion on the other group (group injected) must be intended to  */
05183   /*   continue (groups regular and injected are both impacted by             */
05184   /*   ADC disable)                                                           */
05185
05186   /* 1. Stop potential conversion on going, on regular group only */
05187   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
05188
05189   /* Disable ADC peripheral if conversion on ADC group regular is             */
05190   /* effectively stopped and if no conversion on the other group              */
05191   /* (ADC group injected) is intended to continue.                            */
05192   if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
05193      ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET)     )
05194   {
05195     /* Set a temporary handle of the ADC slave associated to the ADC master   */
05196     /* (Depending on STM32F3 product, there may be up to 2 ADC slaves)        */
05197     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
05198
05199     if (tmphadcSlave.Instance == NULL)
05200     {
05201       /* Update ADC state machine (ADC master) to error */
05202       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
05203
05204       /* Process unlocked */
05205       __HAL_UNLOCK(hadc);
05206
05207       return HAL_ERROR;
05208     }
05209
05210     /* Procedure to disable the ADC peripheral: wait for conversions          */
05211     /* effectively stopped (ADC master and ADC slave), then disable ADC       */
05212
05213     /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
05214     tickstart = HAL_GetTick();
05215
05216     while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)          ||
05217           ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave)   )
05218     {
05219       if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
05220       {
05221         /* Update ADC state machine (ADC master) to error */
05222         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
05223
05224         /* Process unlocked */
05225         __HAL_UNLOCK(hadc);
05226
05227         return HAL_ERROR;
05228       }
05229     }
05230
05231     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
05232     /* while DMA transfer is on going)                                        */
05233     /* Note: In case of ADC slave using its own DMA channel (multimode        */
05234     /*       parameter "DMAAccessMode" set to disabled):                      */
05235     /*       DMA channel of ADC slave should stopped after this function with */
05236     /*       function HAL_ADC_Stop_DMA.                                       */
05237     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
05238
05239     /* Check if DMA channel effectively disabled */
05240     if (tmp_hal_status != HAL_OK)
05241     {
05242       /* Update ADC state machine to error */
05243       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
05244     }
05245
05246     /* Disable ADC overrun interrupt */
05247     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
05248
05249
05250
05251     /* 2. Disable the ADC peripherals: master and slave */
05252     /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
05253     /* to retain a potential failing status.                                  */
05254     if (tmp_hal_status == HAL_OK)
05255     {
05256       /* Check if ADC are effectively disabled */
05257       if ((ADC_Disable(hadc) != HAL_ERROR)          &&
05258           (ADC_Disable(&tmphadcSlave) != HAL_ERROR)   )
05259       {
05260         tmp_hal_status = HAL_OK;
05261
05262         /* Change ADC state (ADC master) */
05263         ADC_STATE_CLR_SET(hadc->State,
05264                           HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
05265                           HAL_ADC_STATE_READY);
05266       }
05267     }
05268     else
05269     {
05270       /* In case of error, attempt to disable ADC instances anyway */
05271       ADC_Disable(hadc);
05272       ADC_Disable(&tmphadcSlave);
05273
05274       /* Update ADC state machine (ADC master) to error */
05275       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
05276     }
05277
05278   }
05279   /* Conversion on ADC group regular group is stopped, but ADC is not         */
05280   /* disabled since conversion on ADC group injected is still on going.       */
05281   else
05282   {
05283     /* Set ADC state */
05284     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
05285   }
05286
05287   /* Process unlocked */
05288   __HAL_UNLOCK(hadc);
05289
05290   /* Return function status */
05291   return tmp_hal_status;
05292 }
05293 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
05294        /* STM32F302xC || STM32F303xC || STM32F358xx || */
05295        /* STM32F303x8 || STM32F334x8 || STM32F328xx    */
05296
05297
05298 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
05299        /* STM32F302xC || STM32F303xC || STM32F358xx || */
05300        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
05301        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
05302
05303 /**
05304   * @brief  Injected conversion complete callback in non blocking mode
05305   * @param  hadc ADC handle
05306   * @retval None
05307   */
05308 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
05309 {
05310   /* Prevent unused argument(s) compilation warning */
05311   UNUSED(hadc);
05312
05313   /* NOTE : This function Should not be modified, when the callback is needed,
05314             the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
05315   */
05316 }
05317
05318 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
05319     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
05320     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
05321     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
05322 /**
05323   * @brief  Injected context queue overflow flag callback.
05324   * @note   This callback is called if injected context queue is enabled
05325             (parameter "QueueInjectedContext" in injected channel configuration)
05326             and if a new injected context is set when queue is full (maximum 2
05327             contexts).
05328   * @param  hadc ADC handle
05329   * @retval None
05330   */
05331 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
05332 {
05333   /* Prevent unused argument(s) compilation warning */
05334   UNUSED(hadc);
05335
05336   /* NOTE : This function should not be modified. When the callback is needed,
05337             function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented
05338             in the user file.
05339   */
05340 }
05341
05342 /**
05343   * @brief  Analog watchdog 2 callback in non blocking mode.
05344   * @param  hadc ADC handle
05345   * @retval None
05346   */
05347 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
05348 {
05349   /* Prevent unused argument(s) compilation warning */
05350   UNUSED(hadc);
05351
05352   /* NOTE : This function should not be modified. When the callback is needed,
05353             function HAL_ADC_LevelOoutOfWindow2Callback must be implemented in the user file.
05354   */
05355 }
05356
05357 /**
05358   * @brief  Analog watchdog 3 callback in non blocking mode.
05359   * @param  hadc ADC handle
05360   * @retval None
05361   */
05362 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
05363 {
05364   /* Prevent unused argument(s) compilation warning */
05365   UNUSED(hadc);
05366
05367   /* NOTE : This function should not be modified. When the callback is needed,
05368             function HAL_ADC_LevelOoutOfWindow3Callback must be implemented in the user file.
05369   */
05370 }
05371 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
05372        /* STM32F302xC || STM32F303xC || STM32F358xx || */
05373        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
05374        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
05375
05376 /**
05377   * @}
05378   */
05379
05380 /** @defgroup ADCEx_Exported_Functions_Group3 ADCEx Peripheral Control functions
05381   * @brief    ADC Extended Peripheral Control functions
05382   *
05383 @verbatim
05384  ===============================================================================
05385              ##### Peripheral Control functions #####
05386  ===============================================================================
05387     [..]  This section provides functions allowing to:
05388       (+) Configure channels on regular group
05389       (+) Configure channels on injected group
05390       (+) Configure multimode
05391       (+) Configure the analog watchdog
05392
05393 @endverbatim
05394   * @{
05395   */
05396
05397
05398 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
05399     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
05400     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
05401     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
05402 /**
05403   * @brief  Configures the the selected channel to be linked to the regular
05404   *         group.
05405   * @note   In case of usage of internal measurement channels:
05406   *         Vbat/VrefInt/TempSensor.
05407   *         The recommended sampling time is at least:
05408   *          - For devices STM32F37x: 17.1us for temperature sensor
05409   *          - For the other STM32F3 devices: 2.2us for each of channels
05410   *            Vbat/VrefInt/TempSensor.
05411   *         These internal paths can be be disabled using function
05412   *         HAL_ADC_DeInit().
05413   * @note   Possibility to update parameters on the fly:
05414   *         This function initializes channel into regular group, following
05415   *         calls to this function can be used to reconfigure some parameters
05416   *         of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
05417   *         the ADC.
05418   *         The setting of these parameters is conditioned to ADC state.
05419   *         For parameters constraints, see comments of structure
05420   *         "ADC_ChannelConfTypeDef".
05421   * @param  hadc ADC handle
05422   * @param  sConfig Structure ADC channel for regular group.
05423   * @retval HAL status
05424   */
05425 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
05426 {
05427   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
05428   ADC_Common_TypeDef *tmpADC_Common;
05429   ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
05430   uint32_t tmpOffsetShifted;
05431   __IO uint32_t wait_loop_index = 0U;
05432
05433   /* Check the parameters */
05434   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
05435   assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
05436   assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
05437   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
05438   assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
05439   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
05440
05441
05442   /* Verification of channel number: Channels 1 to 14 are available in        */
05443   /* differential mode. Channels 15U, 16U, 17U, 18 can be used only in           */
05444   /* single-ended mode.                                                       */
05445   if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
05446   {
05447     assert_param(IS_ADC_CHANNEL(sConfig->Channel));
05448   }
05449   else
05450   {
05451     assert_param(IS_ADC_DIFF_CHANNEL(sConfig->Channel));
05452   }
05453
05454   /* Process locked */
05455   __HAL_LOCK(hadc);
05456
05457
05458   /* Parameters update conditioned to ADC state:                              */
05459   /* Parameters that can be updated when ADC is disabled or enabled without   */
05460   /* conversion on going on regular group:                                    */
05461   /*  - Channel number                                                        */
05462   /*  - Channel rank                                                          */
05463   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
05464   {
05465     /* Regular sequence configuration */
05466     /* For Rank 1 to 4U */
05467     if (sConfig->Rank < 5U)
05468     {
05469       MODIFY_REG(hadc->Instance->SQR1,
05470                  ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank)    ,
05471                  ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
05472     }
05473     /* For Rank 5 to 9U */
05474     else if (sConfig->Rank < 10U)
05475     {
05476       MODIFY_REG(hadc->Instance->SQR2,
05477                  ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank)    ,
05478                  ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
05479     }
05480     /* For Rank 10 to 14U */
05481     else if (sConfig->Rank < 15U)
05482     {
05483       MODIFY_REG(hadc->Instance->SQR3                        ,
05484                  ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank)   ,
05485                  ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
05486     }
05487     /* For Rank 15 to 16U */
05488     else
05489     {
05490       MODIFY_REG(hadc->Instance->SQR4                        ,
05491                  ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank)   ,
05492                  ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) );
05493     }
05494
05495
05496   /* Parameters update conditioned to ADC state:                              */
05497   /* Parameters that can be updated when ADC is disabled or enabled without   */
05498   /* conversion on going on regular group:                                    */
05499   /*  - Channel sampling time                                                 */
05500   /*  - Channel offset                                                        */
05501   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
05502   {
05503     /* Channel sampling time configuration */
05504     /* For channels 10 to 18U */
05505     if (sConfig->Channel >= ADC_CHANNEL_10)
05506     {
05507       MODIFY_REG(hadc->Instance->SMPR2                             ,
05508                  ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel)      ,
05509                  ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
05510     }
05511     else /* For channels 1 to 9U */
05512     {
05513       MODIFY_REG(hadc->Instance->SMPR1                             ,
05514                  ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel)       ,
05515                  ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
05516     }
05517
05518
05519     /* Configure the offset: offset enable/disable, channel, offset value */
05520
05521     /* Shift the offset in function of the selected ADC resolution. */
05522     /* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set  */
05523     /* to 0.                                                                  */
05524     tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
05525
05526     /* Configure the selected offset register:                                */
05527     /* - Enable offset                                                        */
05528     /* - Set channel number                                                   */
05529     /* - Set offset value                                                     */
05530     switch (sConfig->OffsetNumber)
05531     {
05532     case ADC_OFFSET_1:
05533       /* Configure offset register 1U */
05534       MODIFY_REG(hadc->Instance->OFR1               ,
05535                  ADC_OFR1_OFFSET1_CH |
05536                  ADC_OFR1_OFFSET1                   ,
05537                  ADC_OFR1_OFFSET1_EN               |
05538                  ADC_OFR_CHANNEL(sConfig->Channel) |
05539                  tmpOffsetShifted                    );
05540       break;
05541
05542     case ADC_OFFSET_2:
05543       /* Configure offset register 2U */
05544       MODIFY_REG(hadc->Instance->OFR2               ,
05545                  ADC_OFR2_OFFSET2_CH |
05546                  ADC_OFR2_OFFSET2                   ,
05547                  ADC_OFR2_OFFSET2_EN               |
05548                  ADC_OFR_CHANNEL(sConfig->Channel) |
05549                  tmpOffsetShifted                    );
05550       break;
05551
05552     case ADC_OFFSET_3:
05553       /* Configure offset register 3U */
05554       MODIFY_REG(hadc->Instance->OFR3               ,
05555                  ADC_OFR3_OFFSET3_CH |
05556                  ADC_OFR3_OFFSET3                   ,
05557                  ADC_OFR3_OFFSET3_EN               |
05558                  ADC_OFR_CHANNEL(sConfig->Channel) |
05559                  tmpOffsetShifted                    );
05560       break;
05561
05562     case ADC_OFFSET_4:
05563       /* Configure offset register 4U */
05564       MODIFY_REG(hadc->Instance->OFR4               ,
05565                  ADC_OFR4_OFFSET4_CH |
05566                  ADC_OFR4_OFFSET4                   ,
05567                  ADC_OFR4_OFFSET4_EN               |
05568                  ADC_OFR_CHANNEL(sConfig->Channel) |
05569                  tmpOffsetShifted                    );
05570       break;
05571
05572     /* Case ADC_OFFSET_NONE */
05573     default :
05574     /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is        */
05575     /* enabled. If this is the case, offset OFRx is disabled.                 */
05576       if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
05577       {
05578         /* Disable offset OFR1*/
05579         CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
05580       }
05581       if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
05582       {
05583         /* Disable offset OFR2*/
05584         CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
05585       }
05586       if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
05587       {
05588         /* Disable offset OFR3*/
05589         CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
05590       }
05591       if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
05592       {
05593         /* Disable offset OFR4*/
05594         CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
05595       }
05596       break;
05597     }
05598
05599   }
05600
05601
05602   /* Parameters update conditioned to ADC state:                              */
05603   /* Parameters that can be updated only when ADC is disabled:                */
05604   /*  - Single or differential mode                                           */
05605   /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
05606   if (ADC_IS_ENABLE(hadc) == RESET)
05607   {
05608     /* Configuration of differential mode */
05609     if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
05610     {
05611       /* Disable differential mode (default mode: single-ended) */
05612       CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
05613     }
05614     else
05615     {
05616       /* Enable differential mode */
05617       SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
05618
05619       /* Channel sampling time configuration (channel ADC_INx +1              */
05620       /* corresponding to differential negative input).                       */
05621       /* For channels 10 to 18U */
05622       if (sConfig->Channel >= ADC_CHANNEL_10)
05623       {
05624         MODIFY_REG(hadc->Instance->SMPR2,
05625                    ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1U)      ,
05626                    ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1U) );
05627       }
05628       else /* For channels 1 to 9U */
05629       {
05630         MODIFY_REG(hadc->Instance->SMPR1,
05631                    ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel +1U)       ,
05632                    ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel +1U) );
05633       }
05634     }
05635
05636
05637     /* Management of internal measurement channels: VrefInt/TempSensor/Vbat   */
05638     /* internal measurement paths enable: If internal channel selected,       */
05639     /* enable dedicated internal buffers and path.                            */
05640     /* Note: these internal measurement paths can be disabled using           */
05641     /* HAL_ADC_DeInit().                                                      */
05642
05643     /* Configuration of common ADC parameters                                 */
05644     /* Pointer to the common control register to which is belonging hadc      */
05645     /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common   */
05646     /* control registers)                                                     */
05647     tmpADC_Common = ADC_COMMON_REGISTER(hadc);
05648
05649     /* If the requested internal measurement path has already been enabled,   */
05650     /* bypass the configuration processing.                                   */
05651     if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
05652           (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN))            ) ||
05653         ( (sConfig->Channel == ADC_CHANNEL_VBAT)       &&
05654           (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN))          ) ||
05655         ( (sConfig->Channel == ADC_CHANNEL_VREFINT)    &&
05656           (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
05657        )
05658     {
05659       /* Configuration of common ADC parameters (continuation)                */
05660       /* Set handle of the other ADC sharing the same common register         */
05661       ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
05662
05663       /* Software is allowed to change common parameters only when all ADCs   */
05664       /* of the common group are disabled.                                    */
05665       if ((ADC_IS_ENABLE(hadc) == RESET)                                    &&
05666           ( (tmphadcSharingSameCommonRegister.Instance == NULL)         ||
05667             (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET)   )   )
05668       {
05669         /* If Channel_16 is selected, enable Temp. sensor measurement path    */
05670         /* Note: Temp. sensor internal channels available on ADC1 only        */
05671         if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
05672         {
05673           SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
05674
05675           /* Delay for temperature sensor stabilization time */
05676           /* Compute number of CPU cycles to wait for */
05677           wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
05678           while(wait_loop_index != 0U)
05679           {
05680             wait_loop_index--;
05681           }
05682         }
05683         /* If Channel_17 is selected, enable VBAT measurement path            */
05684         /* Note: VBAT internal channels available on ADC1 only                */
05685         else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1))
05686         {
05687           SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
05688         }
05689         /* If Channel_18 is selected, enable VREFINT measurement path         */
05690         /* Note: VrefInt internal channels available on all ADCs, but only    */
05691         /*       one ADC is allowed to be connected to VrefInt at the same    */
05692         /*       time.                                                        */
05693         else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
05694         {
05695           SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
05696         }
05697       }
05698       /* If the requested internal measurement path has already been          */
05699       /* enabled and other ADC of the common group are enabled, internal      */
05700       /* measurement paths cannot be enabled.                                 */
05701       else
05702       {
05703         /* Update ADC state machine to error */
05704         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
05705
05706         tmp_hal_status = HAL_ERROR;
05707       }
05708     }
05709
05710   }
05711
05712   }
05713   /* If a conversion is on going on regular group, no update on regular       */
05714   /* channel could be done on neither of the channel configuration structure  */
05715   /* parameters.                                                              */
05716   else
05717   {
05718     /* Update ADC state machine to error */
05719     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
05720
05721     tmp_hal_status = HAL_ERROR;
05722   }
05723
05724   /* Process unlocked */
05725   __HAL_UNLOCK(hadc);
05726
05727   /* Return function status */
05728   return tmp_hal_status;
05729 }
05730 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
05731        /* STM32F302xC || STM32F303xC || STM32F358xx || */
05732        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
05733        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
05734
05735 #if defined(STM32F373xC) || defined(STM32F378xx)
05736 /**
05737   * @brief  Configures the the selected channel to be linked to the regular
05738   *         group.
05739   * @note   In case of usage of internal measurement channels:
05740   *         Vbat/VrefInt/TempSensor.
05741   *         The recommended sampling time is at least:
05742   *          - For devices STM32F37x: 17.1us for temperature sensor
05743   *          - For the other STM32F3 devices: 2.2us for each of channels
05744   *            Vbat/VrefInt/TempSensor.
05745   *         These internal paths can be be disabled using function
05746   *         HAL_ADC_DeInit().
05747   * @note   Possibility to update parameters on the fly:
05748   *         This function initializes channel into regular group, following
05749   *         calls to this function can be used to reconfigure some parameters
05750   *         of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
05751   *         the ADC.
05752   *         The setting of these parameters is conditioned to ADC state.
05753   *         For parameters constraints, see comments of structure
05754   *         "ADC_ChannelConfTypeDef".
05755   * @param  hadc ADC handle
05756   * @param  sConfig Structure of ADC channel for regular group.
05757   * @retval HAL status
05758   */
05759 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
05760 {
05761   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
05762   __IO uint32_t wait_loop_index = 0U;
05763
05764   /* Check the parameters */
05765   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
05766   assert_param(IS_ADC_CHANNEL(sConfig->Channel));
05767   assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
05768   assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
05769
05770   /* Process locked */
05771   __HAL_LOCK(hadc);
05772
05773
05774   /* Regular sequence configuration */
05775   /* For Rank 1 to 6U */
05776   if (sConfig->Rank < 7U)
05777   {
05778     MODIFY_REG(hadc->Instance->SQR3                        ,
05779                ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank)    ,
05780                ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
05781   }
05782   /* For Rank 7 to 12U */
05783   else if (sConfig->Rank < 13U)
05784   {
05785     MODIFY_REG(hadc->Instance->SQR2                        ,
05786                ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank)    ,
05787                ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
05788   }
05789   /* For Rank 13 to 16U */
05790   else
05791   {
05792     MODIFY_REG(hadc->Instance->SQR1                        ,
05793                ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank)   ,
05794                ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
05795   }
05796
05797
05798   /* Channel sampling time configuration */
05799   /* For channels 10 to 18U */
05800   if (sConfig->Channel > ADC_CHANNEL_10)
05801   {
05802     MODIFY_REG(hadc->Instance->SMPR1                             ,
05803                ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel)      ,
05804                ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
05805   }
05806   else   /* For channels 0 to 9U */
05807   {
05808     MODIFY_REG(hadc->Instance->SMPR2                             ,
05809                ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel)       ,
05810                ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
05811   }
05812
05813   /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
05814   /* and VREFINT measurement path.                                            */
05815   if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
05816       (sConfig->Channel == ADC_CHANNEL_VREFINT)      )
05817   {
05818     SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
05819
05820     if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
05821     {
05822       /* Delay for temperature sensor stabilization time */
05823       /* Compute number of CPU cycles to wait for */
05824       wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
05825       while(wait_loop_index != 0U)
05826       {
05827         wait_loop_index--;
05828       }
05829     }
05830   }
05831   /* if ADC1 Channel_18 is selected, enable VBAT measurement path */
05832   else if (sConfig->Channel == ADC_CHANNEL_VBAT)
05833   {
05834     SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
05835   }
05836
05837
05838   /* Process unlocked */
05839   __HAL_UNLOCK(hadc);
05840
05841   /* Return function status */
05842   return tmp_hal_status;
05843 }
05844 #endif /* STM32F373xC || STM32F378xx */
05845
05846 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
05847     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
05848     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
05849     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
05850 /**
05851   * @brief  Configures the ADC injected group and the selected channel to be
05852   *         linked to the injected group.
05853   * @note   Possibility to update parameters on the fly:
05854   *         This function initializes injected group, following calls to this
05855   *         function can be used to reconfigure some parameters of structure
05856   *         "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
05857   *         The setting of these parameters is conditioned to ADC state.
05858   *         For parameters constraints, see comments of structure
05859   *         "ADC_InjectionConfTypeDef".
05860   * @note   In case of usage of internal measurement channels:
05861   *         Vbat/VrefInt/TempSensor.
05862   *         The recommended sampling time is at least:
05863   *          - For devices STM32F37x: 17.1us for temperature sensor
05864   *          - For the other STM32F3 devices: 2.2us for each of channels
05865   *            Vbat/VrefInt/TempSensor.
05866   *         These internal paths can be be disabled using function
05867   *         HAL_ADC_DeInit().
05868   * @note   To reset injected sequencer, function HAL_ADCEx_InjectedStop() can
05869   *         be used.
05870   * @note   Caution: For Injected Context Queue use: a context must be fully
05871   * defined before start of injected conversion: all channels configured
05872   * consecutively for the same ADC instance. Therefore, Number of calls of
05873   * HAL_ADCEx_InjectedConfigChannel() must correspond to value of parameter
05874   * InjectedNbrOfConversion for each context.
05875   *  - Example 1: If 1 context intended to be used (or not use of this feature:
05876   *    QueueInjectedContext=DISABLE) and usage of the 3 first injected ranks
05877   *    (InjectedNbrOfConversion=3), HAL_ADCEx_InjectedConfigChannel() must be
05878   *    called once for each channel (3 times) before launching a conversion.
05879   *    This function must not be called to configure the 4th injected channel:
05880   *    it would start a new context into context queue.
05881   *  - Example 2: If 2 contexts intended to be used and usage of the 3 first
05882   *    injected ranks (InjectedNbrOfConversion=3),
05883   *    HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
05884   *    for each context (3 channels x 2 contexts = 6 calls). Conversion can
05885   *    start once the 1st context is set. The 2nd context can be set on the fly.
05886   * @param  hadc ADC handle
05887   * @param  sConfigInjected Structure of ADC injected group and ADC channel for
05888   *         injected group.
05889   * @retval None
05890   */
05891 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
05892 {
05893   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
05894   ADC_Common_TypeDef *tmpADC_Common;
05895   ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
05896   uint32_t tmpOffsetShifted;
05897   __IO uint32_t wait_loop_index = 0U;
05898
05899   /* Injected context queue feature: temporary JSQR variables defined in      */
05900   /* static to be passed over calls of this function                          */
05901   uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
05902
05903   /* Check the parameters */
05904   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
05905   assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
05906   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
05907   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
05908   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
05909   assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
05910   assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
05911   assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
05912   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
05913
05914   if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
05915   {
05916     assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
05917     assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
05918     assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
05919   }
05920
05921   /* Verification of channel number: Channels 1 to 14 are available in        */
05922   /* differential mode. Channels 15U, 16U, 17U, 18 can be used only in           */
05923   /* single-ended mode.                                                       */
05924   if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
05925   {
05926     assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
05927   }
05928   else
05929   {
05930     assert_param(IS_ADC_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
05931   }
05932
05933   /* Process locked */
05934   __HAL_LOCK(hadc);
05935
05936   /* Configuration of Injected group sequencer.                               */
05937   /* Hardware constraint: Must fully define injected context register JSQR    */
05938   /* before make it entering into injected sequencer queue.                   */
05939   /*                                                                          */
05940   /* - if scan mode is disabled:                                              */
05941   /*    * Injected channels sequence length is set to 0x00: 1 channel         */
05942   /*      converted (channel on injected rank 1U)                              */
05943   /*      Parameter "InjectedNbrOfConversion" is discarded.                   */
05944   /*    * Injected context register JSQR setting is simple: register is fully */
05945   /*      defined on one call of this function (for injected rank 1U) and can  */
05946   /*      be entered into queue directly.                                     */
05947   /* - if scan mode is enabled:                                               */
05948   /*    * Injected channels sequence length is set to parameter               */
05949   /*      "InjectedNbrOfConversion".                                          */
05950   /*    * Injected context register JSQR setting more complex: register is    */
05951   /*      fully defined over successive calls of this function, for each      */
05952   /*      injected channel rank. It is entered into queue only when all       */
05953   /*      injected ranks have been set.                                       */
05954   /*   Note: Scan mode is not present by hardware on this device, but used    */
05955   /*   by software for alignment over all STM32 devices.                      */
05956
05957   if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)  ||
05958       (sConfigInjected->InjectedNbrOfConversion == 1U)  )
05959   {
05960     /* Configuration of context register JSQR:                                */
05961     /*  - number of ranks in injected group sequencer: fixed to 1st rank      */
05962     /*    (scan mode disabled, only rank 1 used)                              */
05963     /*  - external trigger to start conversion                                */
05964     /*  - external trigger polarity                                           */
05965     /*  - channel set to rank 1 (scan mode disabled, only rank 1 used)        */
05966
05967     if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
05968     {
05969       /* Enable external trigger if trigger selection is different of         */
05970       /* software start.                                                      */
05971       /* Note: This configuration keeps the hardware feature of parameter     */
05972       /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
05973       /*       software start.                                                */
05974       if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
05975       {
05976         SET_BIT(tmp_JSQR_ContextQueueBeingBuilt, ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) |
05977                                                  ADC_JSQR_JEXTSEL_SET(hadc, sConfigInjected->ExternalTrigInjecConv) |
05978                                                  sConfigInjected->ExternalTrigInjecConvEdge                          );
05979       }
05980       else
05981       {
05982         SET_BIT(tmp_JSQR_ContextQueueBeingBuilt, ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) );
05983       }
05984
05985       /* Update ADC register JSQR */
05986       MODIFY_REG(hadc->Instance->JSQR           ,
05987                  ADC_JSQR_JSQ4    |
05988                  ADC_JSQR_JSQ3    |
05989                  ADC_JSQR_JSQ2    |
05990                  ADC_JSQR_JSQ1    |
05991                  ADC_JSQR_JEXTEN  |
05992                  ADC_JSQR_JEXTSEL |
05993                  ADC_JSQR_JL                    ,
05994                  tmp_JSQR_ContextQueueBeingBuilt );
05995
05996       /* For debug and informative reasons, hadc handle saves JSQR setting */
05997       hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
05998     }
05999     /* If another injected rank than rank1 was intended to be set, and could  */
06000     /* not due to ScanConvMode disabled, error is reported.                   */
06001     else
06002     {
06003       /* Update ADC state machine to error */
06004       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
06005
06006       tmp_hal_status = HAL_ERROR;
06007     }
06008
06009   }
06010   else
06011   {
06012     /* Case of scan mode enabled, several channels to set into injected group */
06013     /* sequencer.                                                             */
06014     /* Procedure to define injected context register JSQR over successive     */
06015     /* calls of this function, for each injected channel rank:                */
06016
06017     /* 1. Start new context and set parameters related to all injected        */
06018     /*    channels: injected sequence length and trigger                      */
06019     if (hadc->InjectionConfig.ChannelCount == 0U)
06020     {
06021       /* Initialize number of channels that will be configured on the context */
06022       /*  being built                                                         */
06023       hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
06024       /* Initialize value that will be set into register JSQR */
06025       hadc->InjectionConfig.ContextQueue = 0x00000000U;
06026
06027       /* Configuration of context register JSQR:                              */
06028       /*  - number of ranks in injected group sequencer                       */
06029       /*  - external trigger to start conversion                              */
06030       /*  - external trigger polarity                                         */
06031
06032       /* Enable external trigger if trigger selection is different of         */
06033       /* software start.                                                      */
06034       /* Note: This configuration keeps the hardware feature of parameter     */
06035       /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
06036       /*       software start.                                                */
06037       if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
06038       {
06039         SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - 1U)           |
06040                                                     ADC_JSQR_JEXTSEL_SET(hadc, sConfigInjected->ExternalTrigInjecConv) |
06041                                                     sConfigInjected->ExternalTrigInjecConvEdge                          );
06042       }
06043       else
06044       {
06045         SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - 1U) );
06046       }
06047
06048     }
06049
06050       /* 2. Continue setting of context under definition with parameter       */
06051       /*    related to each channel: channel rank sequence                    */
06052
06053       /* Set the JSQx bits for the selected rank */
06054       MODIFY_REG(hadc->InjectionConfig.ContextQueue                                          ,
06055                  ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank)                   ,
06056                  ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank) );
06057
06058       /* Decrease channel count after setting into temporary JSQR variable */
06059       hadc->InjectionConfig.ChannelCount --;
06060
06061       /* 3. End of context setting: If last channel set, then write context   */
06062       /*    into register JSQR and make it enter into queue                   */
06063       if (hadc->InjectionConfig.ChannelCount == 0U)
06064       {
06065         /* Update ADC register JSQR */
06066         MODIFY_REG(hadc->Instance->JSQR              ,
06067                    ADC_JSQR_JSQ4    |
06068                    ADC_JSQR_JSQ3    |
06069                    ADC_JSQR_JSQ2    |
06070                    ADC_JSQR_JSQ1    |
06071                    ADC_JSQR_JEXTEN  |
06072                    ADC_JSQR_JEXTSEL |
06073                    ADC_JSQR_JL                       ,
06074                    hadc->InjectionConfig.ContextQueue );
06075       }
06076
06077   }
06078
06079
06080   /* Parameters update conditioned to ADC state:                              */
06081   /* Parameters that can be updated when ADC is disabled or enabled without   */
06082   /* conversion on going on injected group:                                   */
06083   /*  - Injected context queue: Queue disable (active context is kept) or     */
06084   /*    enable (context decremented, up to 2 contexts queued)                 */
06085   /*  - Injected discontinuous mode: can be enabled only if auto-injected     */
06086   /*    mode is disabled.                                                     */
06087   if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
06088   {
06089     /* If auto-injected mode is disabled: no constraint                       */
06090     if (sConfigInjected->AutoInjectedConv == DISABLE)
06091     {
06092       MODIFY_REG(hadc->Instance->CFGR                                                            ,
06093                  ADC_CFGR_JQM    |
06094                  ADC_CFGR_JDISCEN                                                                ,
06095                  ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext)           |
06096                  ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode)   );
06097     }
06098     /* If auto-injected mode is enabled: Injected discontinuous setting is    */
06099     /* discarded.                                                             */
06100     else
06101     {
06102       MODIFY_REG(hadc->Instance->CFGR                                                ,
06103                  ADC_CFGR_JQM    |
06104                  ADC_CFGR_JDISCEN                                                    ,
06105                  ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) );
06106
06107       /* If injected discontinuous mode was intended to be set and could not  */
06108       /* due to auto-injected enabled, error is reported.                     */
06109       if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
06110       {
06111         /* Update ADC state machine to error */
06112         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
06113
06114         tmp_hal_status = HAL_ERROR;
06115       }
06116     }
06117
06118   }
06119
06120
06121   /* Parameters update conditioned to ADC state:                              */
06122   /* Parameters that can be updated when ADC is disabled or enabled without   */
06123   /* conversion on going on regular and injected groups:                      */
06124   /*  - Automatic injected conversion: can be enabled if injected group       */
06125   /*    external triggers are disabled.                                       */
06126   /*  - Channel sampling time                                                 */
06127   /*  - Channel offset                                                        */
06128   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
06129   {
06130     /* If injected group external triggers are disabled (set to injected      */
06131     /* software start): no constraint                                         */
06132     if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
06133     {
06134       MODIFY_REG(hadc->Instance->CFGR                                              ,
06135                  ADC_CFGR_JAUTO                                                    ,
06136                  ADC_CFGR_INJECT_AUTO_CONVERSION(sConfigInjected->AutoInjectedConv) );
06137     }
06138     /* If Automatic injected conversion was intended to be set and could not  */
06139     /* due to injected group external triggers enabled, error is reported.    */
06140     else
06141     {
06142       /* Disable Automatic injected conversion */
06143       CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
06144
06145       if (sConfigInjected->AutoInjectedConv == ENABLE)
06146       {
06147         /* Update ADC state machine to error */
06148         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
06149
06150         tmp_hal_status = HAL_ERROR;
06151       }
06152     }
06153
06154
06155     /* Channel sampling time configuration */
06156     /* For channels 10 to 18U */
06157     if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
06158     {
06159       MODIFY_REG(hadc->Instance->SMPR2                                                             ,
06160                  ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel)                      ,
06161                  ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
06162     }
06163     else /* For channels 1 to 9U */
06164     {
06165       MODIFY_REG(hadc->Instance->SMPR1                                                             ,
06166                  ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel)                       ,
06167                  ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
06168     }
06169
06170     /* Configure the offset: offset enable/disable, channel, offset value */
06171
06172     /* Shift the offset in function of the selected ADC resolution. */
06173     /* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set  */
06174     /* to 0.                                                                  */
06175     tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
06176
06177     /* Configure the selected offset register:                                */
06178     /* - Enable offset                                                        */
06179     /* - Set channel number                                                   */
06180     /* - Set offset value                                                     */
06181     switch (sConfigInjected->InjectedOffsetNumber)
06182     {
06183     case ADC_OFFSET_1:
06184       /* Configure offset register 1U */
06185       MODIFY_REG(hadc->Instance->OFR1                               ,
06186                  ADC_OFR1_OFFSET1_CH |
06187                  ADC_OFR1_OFFSET1                                   ,
06188                  ADC_OFR1_OFFSET1_EN                               |
06189                  ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
06190                  tmpOffsetShifted                                    );
06191       break;
06192
06193     case ADC_OFFSET_2:
06194       /* Configure offset register 2U */
06195       MODIFY_REG(hadc->Instance->OFR2                               ,
06196                  ADC_OFR2_OFFSET2_CH |
06197                  ADC_OFR2_OFFSET2                                   ,
06198                  ADC_OFR2_OFFSET2_EN                               |
06199                  ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
06200                  tmpOffsetShifted                                    );
06201       break;
06202
06203     case ADC_OFFSET_3:
06204       /* Configure offset register 3U */
06205       MODIFY_REG(hadc->Instance->OFR3                               ,
06206                  ADC_OFR3_OFFSET3_CH |
06207                  ADC_OFR3_OFFSET3                                   ,
06208                  ADC_OFR3_OFFSET3_EN                               |
06209                  ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
06210                  tmpOffsetShifted                                    );
06211       break;
06212
06213     case ADC_OFFSET_4:
06214       /* Configure offset register 4U */
06215       MODIFY_REG(hadc->Instance->OFR4                               ,
06216                  ADC_OFR4_OFFSET4_CH |
06217                  ADC_OFR4_OFFSET4                                   ,
06218                  ADC_OFR4_OFFSET4_EN                               |
06219                  ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
06220                  tmpOffsetShifted                                    );
06221       break;
06222
06223     /* Case ADC_OFFSET_NONE */
06224     default :
06225     /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is        */
06226     /* enabled. If this is the case, offset OFRx is disabled.                 */
06227       if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
06228       {
06229         /* Disable offset OFR1*/
06230         CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
06231       }
06232       if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
06233       {
06234         /* Disable offset OFR2*/
06235         CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
06236       }
06237       if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
06238       {
06239         /* Disable offset OFR3*/
06240         CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
06241       }
06242       if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
06243       {
06244         /* Disable offset OFR4*/
06245         CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
06246       }
06247       break;
06248     }
06249
06250   }
06251
06252
06253   /* Parameters update conditioned to ADC state:                              */
06254   /* Parameters that can be updated only when ADC is disabled:                */
06255   /*  - Single or differential mode                                           */
06256   /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
06257   if (ADC_IS_ENABLE(hadc) == RESET)
06258   {
06259     /* Configuration of differential mode */
06260     if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
06261     {
06262       /* Disable differential mode (default mode: single-ended) */
06263       CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
06264     }
06265     else
06266     {
06267       /* Enable differential mode */
06268       SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
06269
06270       /* Channel sampling time configuration (channel ADC_INx +1              */
06271       /* corresponding to differential negative input).                       */
06272       /* For channels 10 to 18U */
06273       if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
06274       {
06275         MODIFY_REG(hadc->Instance->SMPR2,
06276                    ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel +1U),
06277                    ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1U) );
06278       }
06279       else /* For channels 1 to 9U */
06280       {
06281         MODIFY_REG(hadc->Instance->SMPR1,
06282                    ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel +1U),
06283                    ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1U) );
06284       }
06285     }
06286
06287
06288     /* Management of internal measurement channels: VrefInt/TempSensor/Vbat   */
06289     /* internal measurement paths enable: If internal channel selected,       */
06290     /* enable dedicated internal buffers and path.                            */
06291     /* Note: these internal measurement paths can be disabled using           */
06292     /* HAL_ADC_deInit().                                                      */
06293
06294     /* Configuration of common ADC parameters                                 */
06295     /* Pointer to the common control register to which is belonging hadc      */
06296     /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common   */
06297     /* control registers)                                                     */
06298     tmpADC_Common = ADC_COMMON_REGISTER(hadc);
06299
06300     /* If the requested internal measurement path has already been enabled,   */
06301     /* bypass the configuration processing.                                   */
06302     if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
06303           (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN))            ) ||
06304         ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)       &&
06305           (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN))          ) ||
06306         ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)    &&
06307           (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
06308        )
06309     {
06310       /* Configuration of common ADC parameters (continuation)                */
06311       /* Set handle of the other ADC sharing the same common register         */
06312       ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
06313
06314       /* Software is allowed to change common parameters only when all ADCs   */
06315       /* of the common group are disabled.                                    */
06316       if ((ADC_IS_ENABLE(hadc) == RESET)                                    &&
06317           ( (tmphadcSharingSameCommonRegister.Instance == NULL)         ||
06318             (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET)   )   )
06319       {
06320         /* If Channel_16 is selected, enable Temp. sensor measurement path    */
06321         /* Note: Temp. sensor internal channels available on ADC1 only        */
06322         if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
06323         {
06324           SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
06325
06326           /* Delay for temperature sensor stabilization time */
06327           /* Compute number of CPU cycles to wait for */
06328           wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
06329           while(wait_loop_index != 0U)
06330           {
06331             wait_loop_index--;
06332           }
06333         }
06334         /* If Channel_17 is selected, enable VBAT measurement path            */
06335         /* Note: VBAT internal channels available on ADC1 only                */
06336         else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1))
06337         {
06338           SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
06339         }
06340         /* If Channel_18 is selected, enable VREFINT measurement path         */
06341         /* Note: VrefInt internal channels available on all ADCs, but only    */
06342         /*       one ADC is allowed to be connected to VrefInt at the same    */
06343         /*       time.                                                        */
06344         else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
06345         {
06346           SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
06347         }
06348       }
06349       /* If the requested internal measurement path has already been enabled  */
06350       /* and other ADC of the common group are enabled, internal              */
06351       /* measurement paths cannot be enabled.                                 */
06352       else
06353       {
06354         /* Update ADC state machine to error */
06355         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
06356
06357         tmp_hal_status = HAL_ERROR;
06358       }
06359     }
06360
06361   }
06362
06363   /* Process unlocked */
06364   __HAL_UNLOCK(hadc);
06365
06366   /* Return function status */
06367   return tmp_hal_status;
06368 }
06369 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
06370        /* STM32F302xC || STM32F303xC || STM32F358xx || */
06371        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
06372        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
06373
06374 #if defined(STM32F373xC) || defined(STM32F378xx)
06375 /**
06376   * @brief  Configures the ADC injected group and the selected channel to be
06377   *         linked to the injected group.
06378   * @note   Possibility to update parameters on the fly:
06379   *         This function initializes injected group, following calls to this
06380   *         function can be used to reconfigure some parameters of structure
06381   *         "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
06382   *         The setting of these parameters is conditioned to ADC state:
06383   *         this function must be called when ADC is not under conversion.
06384   * @note   In case of usage of internal measurement channels:
06385   *         Vbat/VrefInt/TempSensor.
06386   *         The recommended sampling time is at least:
06387   *          - For devices STM32F37x: 17.1us for temperature sensor
06388   *          - For the other STM32F3 devices: 2.2us for each of channels
06389   *            Vbat/VrefInt/TempSensor.
06390   *         These internal paths can be be disabled using function
06391   *         HAL_ADC_DeInit().
06392   * @param  hadc ADC handle
06393   * @param  sConfigInjected Structure of ADC injected group and ADC channel for
06394   *         injected group.
06395   * @retval None
06396   */
06397 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
06398 {
06399   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
06400   __IO uint32_t wait_loop_index = 0U;
06401
06402   /* Check the parameters */
06403   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
06404   assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
06405   assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
06406   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
06407   assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
06408   assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));
06409
06410   if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
06411   {
06412     assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
06413     assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
06414     assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
06415   }
06416
06417   /* Process locked */
06418   __HAL_LOCK(hadc);
06419
06420   /* Configuration of injected group sequencer:                               */
06421   /* - if scan mode is disabled, injected channels sequence length is set to  */
06422   /*   0x00: 1 channel converted (channel on regular rank 1U)                  */
06423   /*   Parameter "InjectedNbrOfConversion" is discarded.                      */
06424   /*   Note: Scan mode is present by hardware on this device and, if          */
06425   /*   disabled, discards automatically nb of conversions. Anyway, nb of      */
06426   /*   conversions is forced to 0x00 for alignment over all STM32 devices.    */
06427   /* - if scan mode is enabled, injected channels sequence length is set to   */
06428   /*   parameter "InjectedNbrOfConversion".                                   */
06429   if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
06430   {
06431     if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
06432     {
06433       /* Clear the old SQx bits for all injected ranks */
06434       MODIFY_REG(hadc->Instance->JSQR                           ,
06435                  ADC_JSQR_JL   |
06436                  ADC_JSQR_JSQ4 |
06437                  ADC_JSQR_JSQ3 |
06438                  ADC_JSQR_JSQ2 |
06439                  ADC_JSQR_JSQ1                                  ,
06440                  ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
06441                                       ADC_INJECTED_RANK_1,
06442                                       0x01U)                      );
06443     }
06444     /* If another injected rank than rank1 was intended to be set, and could  */
06445     /* not due to ScanConvMode disabled, error is reported.                   */
06446     else
06447     {
06448       /* Update ADC state machine to error */
06449       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
06450
06451       tmp_hal_status = HAL_ERROR;
06452     }
06453   }
06454   else
06455   {
06456     /* Since injected channels rank conv. order depends on total number of   */
06457     /* injected conversions, selected rank must be below or equal to total   */
06458     /* number of injected conversions to be updated.                         */
06459     if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
06460     {
06461       /* Clear the old SQx bits for the selected rank */
06462       /* Set the SQx bits for the selected rank */
06463       MODIFY_REG(hadc->Instance->JSQR                                         ,
06464
06465                  ADC_JSQR_JL                                                 |
06466                  ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
06467                                 sConfigInjected->InjectedRank,
06468                                 sConfigInjected->InjectedNbrOfConversion)     ,
06469
06470                  ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
06471                  ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
06472                                 sConfigInjected->InjectedRank,
06473                                 sConfigInjected->InjectedNbrOfConversion)      );
06474     }
06475     else
06476     {
06477       /* Clear the old SQx bits for the selected rank */
06478       MODIFY_REG(hadc->Instance->JSQR                                     ,
06479
06480                  ADC_JSQR_JL                                             |
06481                  ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
06482                                 sConfigInjected->InjectedRank,
06483                                 sConfigInjected->InjectedNbrOfConversion) ,
06484
06485                  0x00000000                                                );
06486     }
06487   }
06488
06489   /* Configuration of injected group                                          */
06490   /* Parameters update conditioned to ADC state:                              */
06491   /* Parameters that can be updated only when ADC is disabled:                */
06492   /*  - external trigger to start conversion                                  */
06493   /* Parameters update not conditioned to ADC state:                          */
06494   /*  - Automatic injected conversion                                         */
06495   /*  - Injected discontinuous mode                                           */
06496   /* Note: In case of ADC already enabled, caution to not launch an unwanted  */
06497   /*       conversion while modifying register CR2 by writing 1 to bit ADON.  */
06498   if (ADC_IS_ENABLE(hadc) == RESET)
06499   {
06500     MODIFY_REG(hadc->Instance->CR2                   ,
06501                ADC_CR2_JEXTSEL |
06502                ADC_CR2_ADON                          ,
06503                sConfigInjected->ExternalTrigInjecConv );
06504   }
06505
06506   /* Configuration of injected group                                          */
06507   /*  - Automatic injected conversion                                         */
06508   /*  - Injected discontinuous mode                                           */
06509
06510     /* Automatic injected conversion can be enabled if injected group         */
06511     /* external triggers are disabled.                                        */
06512     if (sConfigInjected->AutoInjectedConv == ENABLE)
06513     {
06514       if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
06515       {
06516         SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
06517       }
06518       else
06519       {
06520         /* Update ADC state machine to error */
06521         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
06522
06523         tmp_hal_status = HAL_ERROR;
06524       }
06525     }
06526
06527     /* Injected discontinuous can be enabled only if auto-injected mode is    */
06528     /* disabled.                                                              */
06529     if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
06530     {
06531       if (sConfigInjected->AutoInjectedConv == DISABLE)
06532       {
06533         SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
06534       }
06535       else
06536       {
06537         /* Update ADC state machine to error */
06538         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
06539
06540         tmp_hal_status = HAL_ERROR;
06541       }
06542     }
06543
06544
06545   /* InjectedChannel sampling time configuration */
06546   /* For channels 10 to 18 */
06547   if (sConfigInjected->InjectedChannel > ADC_CHANNEL_10)
06548   {
06549     MODIFY_REG(hadc->Instance->SMPR1,
06550                ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel),
06551                ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
06552   }
06553   else /* For channels 1 to 9 */
06554   {
06555     MODIFY_REG(hadc->Instance->SMPR2,
06556                ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel),
06557                ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
06558   }
06559
06560
06561   /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
06562   switch(sConfigInjected->InjectedRank)
06563   {
06564     case 1:
06565       /* Set injected channel 1 offset */
06566       MODIFY_REG(hadc->Instance->JOFR1,
06567                  ADC_JOFR1_JOFFSET1,
06568                  sConfigInjected->InjectedOffset);
06569       break;
06570     case 2:
06571       /* Set injected channel 2 offset */
06572       MODIFY_REG(hadc->Instance->JOFR2,
06573                  ADC_JOFR2_JOFFSET2,
06574                  sConfigInjected->InjectedOffset);
06575       break;
06576     case 3:
06577       /* Set injected channel 3 offset */
06578       MODIFY_REG(hadc->Instance->JOFR3,
06579                  ADC_JOFR3_JOFFSET3,
06580                  sConfigInjected->InjectedOffset);
06581       break;
06582     case 4:
06583     default:
06584       MODIFY_REG(hadc->Instance->JOFR4,
06585                  ADC_JOFR4_JOFFSET4,
06586                  sConfigInjected->InjectedOffset);
06587       break;
06588   }
06589
06590   /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
06591   /* and VREFINT measurement path.                                            */
06592   if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
06593       (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)      )
06594   {
06595     if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
06596     {
06597       SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
06598
06599       if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
06600       {
06601         /* Delay for temperature sensor stabilization time */
06602         /* Compute number of CPU cycles to wait for */
06603         wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
06604         while(wait_loop_index != 0U)
06605         {
06606           wait_loop_index--;
06607         }
06608       }
06609     }
06610   }
06611   /* if ADC1 Channel_18 is selected, enable VBAT measurement path */
06612   else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
06613   {
06614     SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
06615   }
06616
06617   /* Process unlocked */
06618   __HAL_UNLOCK(hadc);
06619
06620   /* Return function status */
06621   return tmp_hal_status;
06622 }
06623 #endif /* STM32F373xC || STM32F378xx */
06624
06625 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
06626     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
06627     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
06628     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
06629 /**
06630   * @brief  Configures the analog watchdog.
06631   * @note   Possibility to update parameters on the fly:
06632   *         This function initializes the selected analog watchdog, following
06633   *         calls to this function can be used to reconfigure some parameters
06634   *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
06635   *         the ADC.
06636   *         The setting of these parameters is conditioned to ADC state.
06637   *         For parameters constraints, see comments of structure
06638   *         "ADC_AnalogWDGConfTypeDef".
06639   * @param  hadc ADC handle
06640   * @param  AnalogWDGConfig Structure of ADC analog watchdog configuration
06641   * @retval HAL status
06642   */
06643 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
06644 {
06645   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
06646
06647   uint32_t tmpAWDHighThresholdShifted;
06648   uint32_t tmpAWDLowThresholdShifted;
06649
06650   uint32_t tmpADCFlagAWD2orAWD3;
06651   uint32_t tmpADCITAWD2orAWD3;
06652
06653   /* Check the parameters */
06654   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
06655   assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
06656   assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
06657   assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
06658
06659   /* Verify if threshold is within the selected ADC resolution */
06660   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
06661   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
06662
06663   if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
06664      (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
06665      (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  )
06666   {
06667     assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
06668   }
06669
06670   /* Process locked */
06671   __HAL_LOCK(hadc);
06672
06673   /* Parameters update conditioned to ADC state:                              */
06674   /* Parameters that can be updated when ADC is disabled or enabled without   */
06675   /* conversion on going on regular and injected groups:                      */
06676   /*  - Analog watchdog channels                                              */
06677   /*  - Analog watchdog thresholds                                            */
06678   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
06679   {
06680
06681     /* Analog watchdogs configuration */
06682     if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
06683     {
06684       /* Configuration of analog watchdog:                                    */
06685       /*  - Set the analog watchdog enable mode: regular and/or injected      */
06686       /*    groups, one or overall group of channels.                         */
06687       /*  - Set the Analog watchdog channel (is not used if watchdog          */
06688       /*    mode "all channels": ADC_CFGR_AWD1SGL=0U).                         */
06689       MODIFY_REG(hadc->Instance->CFGR                             ,
06690                  ADC_CFGR_AWD1SGL |
06691                  ADC_CFGR_JAWD1EN |
06692                  ADC_CFGR_AWD1EN  |
06693                  ADC_CFGR_AWD1CH                                  ,
06694                  AnalogWDGConfig->WatchdogMode                   |
06695                  ADC_CFGR_AWD1CH_SHIFT(AnalogWDGConfig->Channel)   );
06696
06697       /* Shift the offset in function of the selected ADC resolution:         */
06698       /* Thresholds have to be left-aligned on bit 11U, the LSB (right bits)   */
06699       /* are set to 0                                                         */
06700       tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
06701       tmpAWDLowThresholdShifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
06702
06703       /* Set the high and low thresholds */
06704       MODIFY_REG(hadc->Instance->TR1                                ,
06705                  ADC_TR1_HT1 |
06706                  ADC_TR1_LT1                                        ,
06707                  ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
06708                  tmpAWDLowThresholdShifted                           );
06709
06710       /* Clear the ADC Analog watchdog flag (in case of left enabled by       */
06711       /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
06712       /* or HAL_ADC_PollForEvent().                                           */
06713       __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
06714
06715       /* Configure ADC Analog watchdog interrupt */
06716       if(AnalogWDGConfig->ITMode == ENABLE)
06717       {
06718         /* Enable the ADC Analog watchdog interrupt */
06719         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
06720       }
06721       else
06722       {
06723         /* Disable the ADC Analog watchdog interrupt */
06724         __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
06725       }
06726
06727     }
06728     /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
06729     else
06730     {
06731     /* Shift the threshold in function of the selected ADC resolution */
06732     /* have to be left-aligned on bit 7U, the LSB (right bits) are set to 0    */
06733       tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
06734       tmpAWDLowThresholdShifted  = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
06735
06736       if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
06737       {
06738         /* Set the Analog watchdog channel or group of channels. This also    */
06739         /* enables the watchdog.                                              */
06740         /* Note: Conditional register reset, because several channels can be  */
06741         /*       set by successive calls of this function.                    */
06742         if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
06743         {
06744           /* Set the high and low thresholds */
06745           MODIFY_REG(hadc->Instance->TR2                                ,
06746                      ADC_TR2_HT2 |
06747                      ADC_TR2_LT2                                        ,
06748                      ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
06749                      tmpAWDLowThresholdShifted                           );
06750
06751           SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel));
06752         }
06753         else
06754         {
06755           CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
06756           CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
06757         }
06758
06759         /* Set temporary variable to flag and IT of AWD2 or AWD3 for further  */
06760         /* settings.                                                          */
06761         tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
06762         tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
06763       }
06764       /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
06765       else
06766       {
06767         /* Set the Analog watchdog channel or group of channels. This also    */
06768         /* enables the watchdog.                                              */
06769         /* Note: Conditionnal register reset, because several channels can be */
06770         /*       set by successive calls of this function.                    */
06771         if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
06772         {
06773           /* Set the high and low thresholds */
06774           MODIFY_REG(hadc->Instance->TR3                                ,
06775                      ADC_TR3_HT3 |
06776                      ADC_TR3_LT3                                        ,
06777                      ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
06778                      tmpAWDLowThresholdShifted                           );
06779
06780           SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel));
06781         }
06782         else
06783         {
06784           CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
06785           CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
06786         }
06787
06788         /* Set temporary variable to flag and IT of AWD2 or AWD3 for further  */
06789         /* settings.                                                          */
06790         tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
06791         tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
06792       }
06793
06794       /* Clear the ADC Analog watchdog flag (in case of left enabled by       */
06795       /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
06796       /* or HAL_ADC_PollForEvent().                                           */
06797       __HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
06798
06799       /* Configure ADC Analog watchdog interrupt */
06800       if(AnalogWDGConfig->ITMode == ENABLE)
06801       {
06802         __HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
06803       }
06804       else
06805       {
06806         __HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
06807       }
06808     }
06809
06810   }
06811   /* If a conversion is on going on regular or injected groups, no update     */
06812   /* could be done on neither of the AWD configuration structure parameters.  */
06813   else
06814   {
06815     /* Update ADC state machine to error */
06816     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
06817
06818     tmp_hal_status = HAL_ERROR;
06819   }
06820
06821
06822   /* Process unlocked */
06823   __HAL_UNLOCK(hadc);
06824
06825   /* Return function status */
06826   return tmp_hal_status;
06827 }
06828 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
06829        /* STM32F302xC || STM32F303xC || STM32F358xx || */
06830        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
06831        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
06832
06833 #if defined(STM32F373xC) || defined(STM32F378xx)
06834 /**
06835   * @brief  Configures the analog watchdog.
06836   * @note   Analog watchdog thresholds can be modified while ADC conversion
06837   *         is on going.
06838   *         In this case, some constraints must be taken into account:
06839   *         the programmed threshold values are effective from the next
06840   *         ADC EOC (end of unitary conversion).
06841   *         Considering that registers write delay may happen due to
06842   *         bus activity, this might cause an uncertainty on the
06843   *         effective timing of the new programmed threshold values.
06844   * @param  hadc ADC handle
06845   * @param  AnalogWDGConfig Structure of ADC analog watchdog configuration
06846   * @retval HAL status
06847   */
06848 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
06849 {
06850   /* Check the parameters */
06851   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
06852   assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
06853   assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
06854   assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
06855   assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
06856
06857   if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
06858      (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
06859      (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  )
06860   {
06861     assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
06862   }
06863
06864   /* Process locked */
06865   __HAL_LOCK(hadc);
06866
06867   /* Analog watchdog configuration */
06868
06869   /* Configure ADC Analog watchdog interrupt */
06870   if(AnalogWDGConfig->ITMode == ENABLE)
06871   {
06872     /* Enable the ADC Analog watchdog interrupt */
06873     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
06874   }
06875   else
06876   {
06877     /* Disable the ADC Analog watchdog interrupt */
06878     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
06879   }
06880
06881   /* Configuration of analog watchdog:                                        */
06882   /*  - Set the analog watchdog enable mode: regular and/or injected groups,  */
06883   /*    one or all channels.                                                  */
06884   /*  - Set the Analog watchdog channel (is not used if watchdog              */
06885   /*    mode "all channels": ADC_CFGR_AWD1SGL=0U).                             */
06886   MODIFY_REG(hadc->Instance->CR1            ,
06887              ADC_CR1_AWDSGL |
06888              ADC_CR1_JAWDEN |
06889              ADC_CR1_AWDEN  |
06890              ADC_CR1_AWDCH                  ,
06891              AnalogWDGConfig->WatchdogMode |
06892              AnalogWDGConfig->Channel       );
06893
06894   /* Set the high threshold */
06895   WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold);
06896
06897   /* Set the low threshold */
06898   WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold);
06899
06900   /* Process unlocked */
06901   __HAL_UNLOCK(hadc);
06902
06903   /* Return function status */
06904   return HAL_OK;
06905 }
06906 #endif /* STM32F373xC || STM32F378xx */
06907
06908
06909 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
06910     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
06911     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
06912 /**
06913   * @brief  Enable ADC multimode and configure multimode parameters
06914   * @note   Possibility to update parameters on the fly:
06915   *         This function initializes multimode parameters, following
06916   *         calls to this function can be used to reconfigure some parameters
06917   *         of structure "ADC_MultiModeTypeDef" on the fly, without reseting
06918   *         the ADCs (both ADCs of the common group).
06919   *         The setting of these parameters is conditioned to ADC state.
06920   *         For parameters constraints, see comments of structure
06921   *         "ADC_MultiModeTypeDef".
06922   * @note   To change back configuration from multimode to single mode, ADC must
06923   *         be reset (using function HAL_ADC_Init() ).
06924   * @param  hadc ADC handle
06925   * @param  multimode Structure of ADC multimode configuration
06926   * @retval HAL status
06927   */
06928 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
06929 {
06930   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
06931   ADC_Common_TypeDef *tmpADC_Common;
06932   ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
06933
06934   /* Check the parameters */
06935   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
06936   assert_param(IS_ADC_MODE(multimode->Mode));
06937   if(multimode->Mode != ADC_MODE_INDEPENDENT)
06938   {
06939     assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
06940     assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
06941   }
06942
06943   /* Set handle of the other ADC sharing the same common register             */
06944   ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
06945   if (tmphadcSharingSameCommonRegister.Instance == NULL)
06946   {
06947     /* Return function status */
06948     return HAL_ERROR;
06949   }
06950
06951   /* Process locked */
06952   __HAL_LOCK(hadc);
06953
06954   /* Parameters update conditioned to ADC state:                              */
06955   /* Parameters that can be updated when ADC is disabled or enabled without   */
06956   /* conversion on going on regular group:                                    */
06957   /*  - Multimode DMA configuration                                           */
06958   /*  - Multimode DMA mode                                                    */
06959   if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
06960     && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSharingSameCommonRegister) == RESET) )
06961   {
06962     /* Pointer to the common control register to which is belonging hadc      */
06963     /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */
06964     /* control registers)                                                     */
06965     tmpADC_Common = ADC_COMMON_REGISTER(hadc);
06966
06967     /* If multimode is selected, configure all multimode paramaters.          */
06968     /* Otherwise, reset multimode parameters (can be used in case of          */
06969     /* transition from multimode to independent mode).                        */
06970     if(multimode->Mode != ADC_MODE_INDEPENDENT)
06971     {
06972       /* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available    */
06973       /* (ADC2, ADC3, ADC4 availability depends on STM32 product)               */
06974       /*  - DMA access mode                                                     */
06975       MODIFY_REG(tmpADC_Common->CCR                                          ,
06976                  ADC_CCR_MDMA  |
06977                  ADC_CCR_DMACFG                                              ,
06978                  multimode->DMAAccessMode                                   |
06979                  ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests)   );
06980
06981       /* Parameters that can be updated only when ADC is disabled:              */
06982       /*  - Multimode mode selection                                            */
06983       /*  - Set delay between two sampling phases                               */
06984       /*    Note: Delay range depends on selected resolution:                   */
06985       /*      from 1 to 12 clock cycles for 12 bits                             */
06986       /*      from 1 to 10 clock cycles for 10 bits,                            */
06987       /*      from 1 to 8 clock cycles for 8 bits                               */
06988       /*      from 1 to 6 clock cycles for 6 bits                               */
06989       /*    If a higher delay is selected, it will be clamped to maximum delay  */
06990       /*    range                                                               */
06991       /* Note: If ADC is not in the appropriate state to modify these           */
06992       /*       parameters, their setting is bypassed without error reporting    */
06993       /*       (as it can be the expected behaviour in case of intended action  */
06994       /*       to update parameter above (which fulfills the ADC state          */
06995       /*       condition: no conversion on going on group regular)              */
06996       /*       on the fly).                                                     */
06997       if ((ADC_IS_ENABLE(hadc) == RESET)                              &&
06998           (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET)   )
06999       {
07000         MODIFY_REG(tmpADC_Common->CCR                                          ,
07001                    ADC_CCR_MULTI |
07002                    ADC_CCR_DELAY                                               ,
07003                    multimode->Mode                                            |
07004                    multimode->TwoSamplingDelay                                  );
07005       }
07006     }
07007     else /* ADC_MODE_INDEPENDENT */
07008     {
07009       CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
07010
07011       /* Parameters that can be updated only when ADC is disabled:                */
07012       /*  - Multimode mode selection                                              */
07013       /*  - Multimode delay                                                       */
07014       if ((ADC_IS_ENABLE(hadc) == RESET)                              &&
07015           (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET)   )
07016       {
07017         CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI | ADC_CCR_DELAY);
07018       }
07019     }
07020   }
07021   /* If one of the ADC sharing the same common group is enabled, no update    */
07022   /* could be done on neither of the multimode structure parameters.          */
07023   else
07024   {
07025     /* Update ADC state machine to error */
07026     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
07027
07028     tmp_hal_status = HAL_ERROR;
07029   }
07030
07031
07032   /* Process unlocked */
07033   __HAL_UNLOCK(hadc);
07034
07035   /* Return function status */
07036   return tmp_hal_status;
07037 }
07038 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
07039        /* STM32F302xC || STM32F303xC || STM32F358xx || */
07040        /* STM32F303x8 || STM32F328xx || STM32F334x8    */
07041
07042 /**
07043   * @}
07044   */
07045
07046 /**
07047   * @}
07048   */
07049
07050 /** @defgroup ADCEx_Private_Functions ADCEx Private Functions
07051   * @{
07052   */
07053 /**
07054   * @brief  DMA transfer complete callback.
07055   * @param  hdma pointer to DMA handle.
07056   * @retval None
07057   */
07058 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
07059 {
07060   /* Retrieve ADC handle corresponding to current DMA handle */
07061   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
07062
07063   /* Update state machine on conversion status if not in error state */
07064   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
07065   {
07066     /* Update ADC state machine */
07067     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
07068
07069     /* Determine whether any further conversion upcoming on group regular     */
07070     /* by external trigger, continuous mode or scan sequence on going.        */
07071     /* Note: On STM32F3 devices, in case of sequencer enabled                 */
07072     /*       (several ranks selected), end of conversion flag is raised       */
07073     /*       at the end of the sequence.                                      */
07074     if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
07075        (hadc->Init.ContinuousConvMode == DISABLE)   )
07076     {
07077       /* Set ADC state */
07078       CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
07079
07080       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
07081       {
07082         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
07083       }
07084     }
07085
07086     /* Conversion complete callback */
07087     HAL_ADC_ConvCpltCallback(hadc);
07088   }
07089   else
07090   {
07091     /* Call DMA error callback */
07092     hadc->DMA_Handle->XferErrorCallback(hdma);
07093   }
07094 }
07095
07096 /**
07097   * @brief  DMA half transfer complete callback.
07098   * @param  hdma pointer to DMA handle.
07099   * @retval None
07100   */
07101 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
07102 {
07103   /* Retrieve ADC handle corresponding to current DMA handle */
07104   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
07105
07106   /* Half conversion callback */
07107   HAL_ADC_ConvHalfCpltCallback(hadc);
07108 }
07109
07110 /**
07111   * @brief  DMA error callback
07112   * @param  hdma pointer to DMA handle.
07113   * @retval None
07114   */
07115 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
07116 {
07117   /* Retrieve ADC handle corresponding to current DMA handle */
07118   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
07119
07120   /* Set ADC state */
07121   SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
07122
07123   /* Set ADC error code to DMA error */
07124   SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
07125
07126   /* Error callback */
07127   HAL_ADC_ErrorCallback(hadc);
07128 }
07129
07130 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
07131     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
07132     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
07133     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
07134 /**
07135   * @brief  Enable the selected ADC.
07136   * @note   Prerequisite condition to use this function: ADC must be disabled
07137   *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
07138   * @param  hadc ADC handle
07139   * @retval HAL status.
07140   */
07141 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
07142 {
07143   uint32_t tickstart = 0U;
07144
07145   /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
07146   /* enabling phase not yet completed: flag ADC ready not yet set).           */
07147   /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
07148   /* causes: ADC clock not running, ...).                                     */
07149   if (ADC_IS_ENABLE(hadc) == RESET)
07150   {
07151     /* Check if conditions to enable the ADC are fulfilled */
07152     if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
07153     {
07154       /* Update ADC state machine to error */
07155       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
07156
07157       /* Set ADC error code to ADC IP internal error */
07158       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
07159
07160       return HAL_ERROR;
07161     }
07162
07163     /* Enable the ADC peripheral */
07164     __HAL_ADC_ENABLE(hadc);
07165
07166     /* Wait for ADC effectively enabled */
07167     tickstart = HAL_GetTick();
07168
07169     while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
07170     {
07171       if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
07172       {
07173         /* Update ADC state machine to error */
07174         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
07175
07176         /* Set ADC error code to ADC IP internal error */
07177         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
07178
07179         return HAL_ERROR;
07180       }
07181     }
07182   }
07183
07184   /* Return HAL status */
07185   return HAL_OK;
07186 }
07187
07188 /**
07189   * @brief  Disable the selected ADC.
07190   * @note   Prerequisite condition to use this function: ADC conversions must be
07191   *         stopped.
07192   * @param  hadc ADC handle
07193   * @retval HAL status.
07194   */
07195 static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
07196 {
07197   uint32_t tickstart = 0U;
07198
07199   /* Verification if ADC is not already disabled:                             */
07200   /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
07201   /* disabled.                                                                */
07202   if (ADC_IS_ENABLE(hadc) != RESET )
07203   {
07204     /* Check if conditions to disable the ADC are fulfilled */
07205     if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
07206     {
07207       /* Disable the ADC peripheral */
07208       __HAL_ADC_DISABLE(hadc);
07209     }
07210     else
07211     {
07212       /* Update ADC state machine to error */
07213       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
07214
07215       /* Set ADC error code to ADC IP internal error */
07216       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
07217
07218       return HAL_ERROR;
07219     }
07220
07221     /* Wait for ADC effectively disabled */
07222     tickstart = HAL_GetTick();
07223
07224     while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
07225     {
07226       if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
07227       {
07228         /* Update ADC state machine to error */
07229         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
07230
07231         /* Set ADC error code to ADC IP internal error */
07232         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
07233
07234         return HAL_ERROR;
07235       }
07236     }
07237   }
07238
07239   /* Return HAL status */
07240   return HAL_OK;
07241 }
07242
07243
07244 /**
07245   * @brief  Stop ADC conversion.
07246   * @param  hadc ADC handle
07247   * @param  ConversionGroup ADC group regular and/or injected.
07248   *          This parameter can be one of the following values:
07249   *            @arg ADC_REGULAR_GROUP: ADC regular conversion type.
07250   *            @arg ADC_INJECTED_GROUP: ADC injected conversion type.
07251   *            @arg ADC_REGULAR_INJECTED_GROUP: ADC regular and injected conversion type.
07252   * @retval HAL status.
07253   */
07254 static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
07255 {
07256   uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0U;
07257   uint32_t tickstart = 0U;
07258   uint32_t Conversion_Timeout_CPU_cycles = 0U;
07259
07260   /* Check the parameters */
07261   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
07262   assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
07263
07264   /* Verification if ADC is not already stopped (on regular and injected      */
07265   /* groups) to bypass this function if not needed.                           */
07266   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc))
07267   {
07268     /* Particular case of continuous auto-injection mode combined with        */
07269     /* auto-delay mode.                                                       */
07270     /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not   */
07271     /* injected group stop ADC_CR_JADSTP).                                    */
07272     /* Procedure to be followed: Wait until JEOS=1U, clear JEOS, set ADSTP=1   */
07273     /* (see reference manual).                                                */
07274     if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) &&
07275          (hadc->Init.ContinuousConvMode==ENABLE)               &&
07276          (hadc->Init.LowPowerAutoWait==ENABLE)                   )
07277     {
07278       /* Use stop of regular group */
07279       ConversionGroup = ADC_REGULAR_GROUP;
07280
07281       /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
07282       while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
07283       {
07284         if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4U))
07285         {
07286           /* Update ADC state machine to error */
07287           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
07288
07289           /* Set ADC error code to ADC IP internal error */
07290           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
07291
07292           return HAL_ERROR;
07293         }
07294         Conversion_Timeout_CPU_cycles ++;
07295       }
07296
07297       /* Clear JEOS */
07298       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
07299     }
07300
07301     /* Stop potential conversion on going on regular group */
07302     if (ConversionGroup != ADC_INJECTED_GROUP)
07303     {
07304       /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0U */
07305       if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
07306           HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS)     )
07307       {
07308         /* Stop conversions on regular group */
07309         hadc->Instance->CR |= ADC_CR_ADSTP;
07310       }
07311     }
07312
07313     /* Stop potential conversion on going on injected group */
07314     if (ConversionGroup != ADC_REGULAR_GROUP)
07315     {
07316       /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0U */
07317       if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) &&
07318           HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS)      )
07319       {
07320         /* Stop conversions on injected group */
07321         hadc->Instance->CR |= ADC_CR_JADSTP;
07322       }
07323     }
07324
07325     /* Selection of start and stop bits in function of regular or injected group */
07326     switch(ConversionGroup)
07327     {
07328     case ADC_REGULAR_INJECTED_GROUP:
07329         tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
07330         break;
07331     case ADC_INJECTED_GROUP:
07332         tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
07333         break;
07334     /* Case ADC_REGULAR_GROUP */
07335     default:
07336         tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
07337         break;
07338     }
07339
07340     /* Wait for conversion effectively stopped */
07341     tickstart = HAL_GetTick();
07342
07343     while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
07344     {
07345       if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
07346       {
07347         /* Update ADC state machine to error */
07348         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
07349
07350         /* Set ADC error code to ADC IP internal error */
07351         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
07352
07353         return HAL_ERROR;
07354       }
07355     }
07356
07357   }
07358
07359   /* Return HAL status */
07360   return HAL_OK;
07361 }
07362 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
07363        /* STM32F302xC || STM32F303xC || STM32F358xx || */
07364        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
07365        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
07366
07367 #if defined(STM32F373xC) || defined(STM32F378xx)
07368 /**
07369   * @brief  Enable the selected ADC.
07370   * @note   Prerequisite condition to use this function: ADC must be disabled
07371   *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
07372   * @param  hadc ADC handle
07373   * @retval HAL status.
07374   */
07375 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
07376 {
07377   uint32_t tickstart = 0U;
07378   __IO uint32_t wait_loop_index = 0U;
07379
07380   /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
07381   /* enabling phase not yet completed: flag ADC ready not yet set).           */
07382   /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
07383   /* causes: ADC clock not running, ...).                                     */
07384   if (ADC_IS_ENABLE(hadc) == RESET)
07385   {
07386     /* Enable the Peripheral */
07387     __HAL_ADC_ENABLE(hadc);
07388
07389     /* Delay for ADC stabilization time */
07390     /* Compute number of CPU cycles to wait for */
07391     wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
07392     while(wait_loop_index != 0U)
07393     {
07394       wait_loop_index--;
07395     }
07396
07397     /* Get tick count */
07398     tickstart = HAL_GetTick();
07399
07400     /* Wait for ADC effectively enabled */
07401     while(ADC_IS_ENABLE(hadc) == RESET)
07402     {
07403       if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
07404       {
07405         /* Update ADC state machine to error */
07406         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
07407
07408         /* Set ADC error code to ADC IP internal error */
07409         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
07410
07411         /* Process unlocked */
07412         __HAL_UNLOCK(hadc);
07413
07414         return HAL_ERROR;
07415       }
07416     }
07417   }
07418
07419   /* Return HAL status */
07420   return HAL_OK;
07421 }
07422
07423 /**
07424   * @brief  Stop ADC conversion and disable the selected ADC
07425   * @param  hadc ADC handle
07426   * @retval HAL status.
07427   */
07428 static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
07429 {
07430   uint32_t tickstart = 0U;
07431
07432   /* Verification if ADC is not already disabled:                             */
07433   if (ADC_IS_ENABLE(hadc) != RESET)
07434   {
07435     /* Disable the ADC peripheral */
07436     __HAL_ADC_DISABLE(hadc);
07437
07438     /* Get tick count */
07439     tickstart = HAL_GetTick();
07440
07441     /* Wait for ADC effectively disabled */
07442     while(ADC_IS_ENABLE(hadc) != RESET)
07443     {
07444       if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
07445       {
07446         /* Update ADC state machine to error */
07447         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
07448
07449         /* Set ADC error code to ADC IP internal error */
07450         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
07451
07452         return HAL_ERROR;
07453       }
07454     }
07455   }
07456
07457   /* Return HAL status */
07458   return HAL_OK;
07459 }
07460 #endif /* STM32F373xC || STM32F378xx */
07461 /**
07462   * @}
07463   */
07464
07465 #endif /* HAL_ADC_MODULE_ENABLED */
07466 /**
07467   * @}
07468   */
07469
07470 /**
07471   * @}
07472   */
07473
07474 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_adc_ex.h Source File

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stm32f3xx_hal_adc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_adc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file containing functions prototypes of ADC HAL library.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_ADC_EX_H
00038 #define __STM32F3xx_ADC_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup ADCEx ADCEx
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /** @defgroup ADCEx_Exported_Types ADCEx Exported Types
00057   * @{
00058   */
00059 struct __ADC_HandleTypeDef;
00060
00061 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00062     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00063     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00064     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00065 /**
00066   * @brief  Structure definition of ADC initialization and regular group
00067   * @note   Parameters of this structure are shared within 2 scopes:
00068   *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, DataAlign,
00069   *            ScanConvMode, EOCSelection, LowPowerAutoWait.
00070   *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv, DMAContinuousRequests, Overrun.
00071   * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
00072   *         ADC state can be either:
00073   *          - For all parameters: ADC disabled
00074   *          - For all parameters except 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular group.
00075   *          - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular and injected groups.
00076   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00077   *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
00078   */
00079 typedef struct
00080 {
00081   uint32_t ClockPrescaler;        /*!< Select ADC clock source (synchronous clock derived from AHB clock or asynchronous clock derived from ADC dedicated PLL 72MHz) and clock prescaler.
00082                                        The clock is common for all the ADCs.
00083                                        This parameter can be a value of @ref ADCEx_ClockPrescaler
00084                                        Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
00085                                              AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
00086                                        Note: In case of usage of the ADC dedicated PLL clock, this clock must be preliminarily enabled and prescaler set at RCC top level.
00087                                        Note: This parameter can be modified only if all ADCs of the common ADC group are disabled (for products with several ADCs) */
00088   uint32_t Resolution;            /*!< Configures the ADC resolution.
00089                                        This parameter can be a value of @ref ADCEx_Resolution */
00090   uint32_t DataAlign;             /*!< Specifies ADC data alignment to right (for resolution 12 bits: MSB on register bit 11 and LSB on register bit 0U) (default setting)
00091                                        or to left (for resolution 12 bits, if offset disabled: MSB on register bit 15 and LSB on register bit 4U, if offset enabled: MSB on register bit 14 and LSB on register bit 3U).
00092                                        See reference manual for alignments with other resolutions.
00093                                        This parameter can be a value of @ref ADCEx_Data_align */
00094   uint32_t ScanConvMode;          /*!< Configures the sequencer of regular and injected groups.
00095                                        This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
00096                                        If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1U).
00097                                                     Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1U).
00098                                        If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
00099                                                     Scan direction is upward: from rank1 to rank 'n'.
00100                                        This parameter can be a value of @ref ADCEx_Scan_mode */
00101   uint32_t EOCSelection;          /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
00102                                        This parameter can be a value of @ref ADCEx_EOCSelection. */
00103   uint32_t LowPowerAutoWait;      /*!< Selects the dynamic low power Auto Delay: ADC conversions are performed only when necessary.
00104                                        New conversion starts only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
00105                                        This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
00106                                        This parameter can be set to ENABLE or DISABLE.
00107                                        Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
00108                                              Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
00109                                              and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
00110   uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
00111                                        after the selected trigger occurred (software start or external trigger).
00112                                        This parameter can be set to ENABLE or DISABLE. */
00113   uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
00114                                        To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00115                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16.
00116                                        Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
00117   uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
00118                                        Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00119                                        Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
00120                                        This parameter can be set to ENABLE or DISABLE. */
00121   uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
00122                                        If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
00123                                        This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
00124   uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.
00125                                        If set to ADC_SOFTWARE_START, external triggers are disabled.
00126                                        This parameter can be a value of @ref ADCEx_External_trigger_source_Regular
00127                                        Caution: For devices with several ADCs, external trigger source is common to ADC common group (for example: ADC1&ADC2, ADC3&ADC4, if available)  */
00128   uint32_t ExternalTrigConvEdge;  /*!< Selects the external trigger edge of regular group.
00129                                        If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
00130                                        This parameter can be a value of @ref ADCEx_External_trigger_edge_Regular */
00131   uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
00132                                        or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
00133                                        Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
00134                                        This parameter can be set to ENABLE or DISABLE.
00135                                        Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
00136   uint32_t Overrun;               /*!< Select the behaviour in case of overrun: data overwritten (default) or preserved.
00137                                        This parameter is for regular group only.
00138                                        This parameter can be a value of @ref ADCEx_Overrun
00139                                        Note: Case of overrun set to data preserved and usage with end on conversion interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved into function HAL_ADC_ConvCpltCallback() (called before end of conversion flags clear).
00140                                        Note: Error reporting in function of conversion mode:
00141                                         - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read the conversion data each time, this is not considered as an erroneous case.
00142                                         - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register, any data missed would be abnormal). */
00143 }ADC_InitTypeDef;
00144
00145 /**
00146   * @brief  Structure definition of ADC channel for regular group
00147   * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
00148   *         ADC state can be either:
00149   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
00150   *          - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
00151   *          - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
00152   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00153   *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
00154   */
00155 typedef struct
00156 {
00157   uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
00158                                         This parameter can be a value of @ref ADCEx_channels
00159                                         Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
00160   uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer.
00161                                         This parameter can be a value of @ref ADCEx_regular_rank
00162                                         Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
00163   uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
00164                                         Unit: ADC clock cycles
00165                                         Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
00166                                         This parameter can be a value of @ref ADCEx_sampling_times
00167                                         Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
00168                                                  If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
00169                                         Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00170                                               sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00171                                               Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 2.2us min). */
00172   uint32_t SingleDiff;             /*!< Selection of single-ended or differential input.
00173                                         In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
00174                                                               Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
00175                                         This parameter must be a value of @ref ADCEx_SingleDifferential
00176                                         Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
00177                                                  If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
00178                                         Note: Channels 1 to 14 are available in differential mode. Channels 15U, 16U, 17U, 18 can be used only in single-ended mode.
00179                                         Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
00180                                         Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00181                                               If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */
00182   uint32_t OffsetNumber;           /*!< Selects the offset number
00183                                         This parameter can be a value of @ref ADCEx_OffsetNumber
00184                                         Caution: Only one channel is allowed per channel. If another channel was on this offset number, the offset will be changed to the new channel */
00185   uint32_t Offset;                 /*!< Defines the offset to be subtracted from the raw converted data when convert channels.
00186                                         Offset value must be a positive number.
00187                                         Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively.
00188                                         Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
00189 }ADC_ChannelConfTypeDef;
00190
00191 /**
00192   * @brief  Structure definition of ADC injected group and ADC channel for injected group
00193   * @note   Parameters of this structure are shared within 2 scopes:
00194   *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
00195   *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
00196   *            AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
00197   * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
00198   *         ADC state can be either:
00199   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
00200   *          - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext': ADC enabled without conversion on going on injected group.
00201   *          - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
00202   *          - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on regular and injected groups.
00203   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00204   *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
00205   */
00206 typedef struct
00207 {
00208   uint32_t InjectedChannel;               /*!< Configure the ADC injected channel
00209                                                This parameter can be a value of @ref ADCEx_channels
00210                                                Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
00211   uint32_t InjectedRank;                  /*!< The rank in the regular group sequencer
00212                                                This parameter must be a value of @ref ADCEx_injected_rank
00213                                                Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
00214   uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
00215                                                Unit: ADC clock cycles
00216                                                Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
00217                                                This parameter can be a value of @ref ADCEx_sampling_times
00218                                                Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
00219                                                         If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
00220                                                Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00221                                                      sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00222                                                      Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 2.2us min). */
00223   uint32_t InjectedSingleDiff;            /*!< Selection of single-ended or differential input.
00224                                                In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
00225                                                               Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
00226                                                This parameter must be a value of @ref ADCEx_SingleDifferential
00227                                                Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
00228                                                         If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
00229                                                Note: Channels 1 to 14 are available in differential mode. Channels 15U, 16U, 17U, 18 can be used only in single-ended mode.
00230                                                Note: When configuring a channel 'i' in differential mode, the channel 'i-1' is not usable separately.
00231                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00232                                                      If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */
00233   uint32_t InjectedOffsetNumber;          /*!< Selects the offset number
00234                                                This parameter can be a value of @ref ADCEx_OffsetNumber
00235                                                Caution: Only one channel is allowed per offset number. If another channel was on this offset number, the offset will be changed to the new channel. */
00236   uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data.
00237                                                Offset value must be a positive number.
00238                                                Depending of ADC resolution selected (12U, 10U, 8 or 6 bits),
00239                                                this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. */
00240   uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
00241                                                To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00242                                                This parameter must be a number between Min_Data = 1 and Max_Data = 4.
00243                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00244                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00245   uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
00246                                                Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00247                                                Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
00248                                                This parameter can be set to ENABLE or DISABLE.
00249                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00250                                                Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
00251                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00252                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00253   uint32_t AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
00254                                                This parameter can be set to ENABLE or DISABLE.
00255                                                Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
00256                                                Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
00257                                                Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
00258                                                      To maintain JAUTO always enabled, DMA must be configured in circular mode.
00259                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00260                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00261   uint32_t QueueInjectedContext;          /*!< Specifies whether the context queue feature is enabled.
00262                                                This parameter can be set to ENABLE or DISABLE.
00263                                                If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
00264                                                new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'.
00265                                                Caution: This feature request that the sequence is fully configured before injected conversion start.
00266                                                         Therefore, configure channels with HAL_ADCEx_InjectedConfigChannel() as many times as value of 'InjectedNbrOfConversion' parameter.
00267                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00268                                                         configure a channel on injected group can impact the configuration of other channels previously set.
00269                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
00270   uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
00271                                                If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
00272                                                This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
00273                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00274                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00275   uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
00276                                                This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
00277                                                If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
00278                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00279                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00280 }ADC_InjectionConfTypeDef;
00281
00282 /**
00283   * @brief  ADC Injection Configuration
00284   */
00285 typedef struct
00286 {
00287   uint32_t ContextQueue;                 /*!< Injected channel configuration context: build-up over each
00288                                               HAL_ADCEx_InjectedConfigChannel() call to finally initialize
00289                                               JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
00290
00291   uint32_t ChannelCount;                 /*!< Number of channels in the injected sequence */
00292 }ADC_InjectionConfigTypeDef;
00293
00294 /**
00295   * @brief  Structure definition of ADC analog watchdog
00296   * @note   The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
00297   *         ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular and injected groups.
00298   */
00299 typedef struct
00300 {
00301   uint32_t WatchdogNumber;    /*!< Selects which ADC analog watchdog to apply to the selected channel.
00302                                    For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
00303                                    For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
00304                                    This parameter can be a value of @ref ADCEx_analog_watchdog_number. */
00305   uint32_t WatchdogMode;      /*!< For Analog Watchdog 1: Configures the ADC analog watchdog mode: single channel/overall group of channels, regular/injected group.
00306                                    For Analog Watchdog 2 and 3: There is no configuration for overall group of channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset channels group programmed with parameter 'Channel', set any other value to not use this parameter.
00307                                    This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
00308   uint32_t Channel;           /*!< Selects which ADC channel to monitor by analog watchdog.
00309                                    For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored.
00310                                    For Analog Watchdog 2 and 3: Several channels can be monitored (successive calls of HAL_ADC_AnalogWDGConfig() must be done, one for each channel.
00311                                                                 Channels group reset can be done by setting WatchdogMode to 'ADC_ANALOGWATCHDOG_NONE').
00312                                    This parameter can be a value of @ref ADCEx_channels. */
00313   uint32_t ITMode;            /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
00314                                    This parameter can be set to ENABLE or DISABLE */
00315   uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
00316                                    Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively.
00317                                    Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
00318                                          the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
00319   uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
00320                                    Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively.
00321                                    Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
00322                                          the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
00323 }ADC_AnalogWDGConfTypeDef;
00324
00325 /**
00326   * @brief  Structure definition of ADC multimode
00327   * @note   The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
00328   *         ADC state can be either:
00329   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'DMAAccessMode')
00330   *          - For parameter 'DMAAccessMode': ADC enabled without conversion on going on regular group.
00331   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00332   *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
00333   */
00334 typedef struct
00335 {
00336   uint32_t Mode;              /*!< Configures the ADC to operate in independent or multi mode.
00337                                    This parameter can be a value of @ref ADCEx_Common_mode */
00338   uint32_t DMAAccessMode;     /*!< Configures the DMA mode for multi ADC mode:
00339                                    selection whether 2 DMA channels (each ADC use its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
00340                                    This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode
00341                                    Caution: Limitations with multimode DMA access enabled (1 DMA channel used): In case of dual mode in high speed (more than 5Msps) or high activity of DMA by other peripherals, there is a risk of DMA overrun.
00342                                             Therefore, it is recommended to disable multimode DMA access: each ADC uses its own DMA channel.
00343                                             Refer to device errata sheet for more details. */
00344   uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.
00345                                    This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases
00346                                    Delay range depends on selected resolution: from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits
00347                                                                                from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits     */
00348 }ADC_MultiModeTypeDef;
00349 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00350        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00351        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00352        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00353
00354
00355 #if defined(STM32F373xC) || defined(STM32F378xx)
00356 /**
00357   * @brief  Structure definition of ADC and regular group initialization
00358   * @note   Parameters of this structure are shared within 2 scopes:
00359   *          - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
00360   *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
00361   * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
00362   *         ADC can be either disabled or enabled without conversion on going on regular group.
00363   */
00364 typedef struct
00365 {
00366   uint32_t DataAlign;             /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0U) (default setting)
00367                                        or to left (if regular group: MSB on register bit 15 and LSB on register bit 4U, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3U).
00368                                        This parameter can be a value of @ref ADCEx_Data_align */
00369   uint32_t ScanConvMode;          /*!< Configures the sequencer of regular and injected groups.
00370                                        This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
00371                                        If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1U).
00372                                                     Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1U).
00373                                        If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
00374                                                     Scan direction is upward: from rank1 to rank 'n'.
00375                                        This parameter can be a value of @ref ADCEx_Scan_mode
00376                                        Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1U)
00377                                              or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
00378                                              the last conversion of the sequence. All previous conversions would be overwritten by the last one.
00379                                              Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
00380   uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
00381                                        after the selected trigger occurred (software start or external trigger).
00382                                        This parameter can be set to ENABLE or DISABLE. */
00383   uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
00384                                        To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00385                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
00386   uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
00387                                        Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00388                                        Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
00389                                        This parameter can be set to ENABLE or DISABLE. */
00390   uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
00391                                        If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
00392                                        This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
00393   uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.
00394                                        If set to ADC_SOFTWARE_START, external triggers are disabled.
00395                                        If set to external trigger source, triggering is on event rising edge.
00396                                        This parameter can be a value of @ref ADCEx_External_trigger_source_Regular */
00397 }ADC_InitTypeDef;
00398
00399 /**
00400   * @brief  Structure definition of ADC channel for regular group
00401   * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
00402   *         ADC can be either disabled or enabled without conversion on going on regular group.
00403   */
00404 typedef struct
00405 {
00406   uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
00407                                         This parameter can be a value of @ref ADCEx_channels
00408                                         Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
00409   uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer
00410                                         This parameter can be a value of @ref ADCEx_regular_rank
00411                                         Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
00412   uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
00413                                         Unit: ADC clock cycles
00414                                         Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
00415                                         This parameter can be a value of @ref ADCEx_sampling_times
00416                                         Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
00417                                                  If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
00418                                         Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00419                                               sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00420                                               Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */
00421 }ADC_ChannelConfTypeDef;
00422
00423 /**
00424   * @brief  ADC Configuration injected Channel structure definition
00425   * @note   Parameters of this structure are shared within 2 scopes:
00426   *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
00427   *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
00428   *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
00429   * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
00430   *         ADC state can be either:
00431   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
00432   *          - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
00433   */
00434 typedef struct
00435 {
00436   uint32_t InjectedChannel;               /*!< Selection of ADC channel to configure
00437                                                This parameter can be a value of @ref ADCEx_channels
00438                                                Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
00439   uint32_t InjectedRank;                  /*!< Rank in the injected group sequencer
00440                                                This parameter must be a value of @ref ADCEx_injected_rank
00441                                                Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
00442   uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
00443                                                Unit: ADC clock cycles
00444                                                Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
00445                                                This parameter can be a value of @ref ADCEx_sampling_times
00446                                                Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
00447                                                         If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
00448                                                Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00449                                                      sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00450                                                      Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */
00451   uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
00452                                                Offset value must be a positive number.
00453                                                Depending of ADC resolution selected (12U, 10U, 8 or 6 bits),
00454                                                this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. */
00455   uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
00456                                                To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00457                                                This parameter must be a number between Min_Data = 1 and Max_Data = 4.
00458                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00459                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00460   uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
00461                                                Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00462                                                Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
00463                                                This parameter can be set to ENABLE or DISABLE.
00464                                                Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
00465                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00466                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00467   uint32_t AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
00468                                                This parameter can be set to ENABLE or DISABLE.
00469                                                Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
00470                                                Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
00471                                                Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
00472                                                      To maintain JAUTO always enabled, DMA must be configured in circular mode.
00473                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00474                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00475   uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
00476                                                If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
00477                                                If set to external trigger source, triggering is on event rising edge.
00478                                                This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
00479                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00480                                                      If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
00481                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00482                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00483 }ADC_InjectionConfTypeDef;
00484
00485 /**
00486   * @brief  ADC Configuration analog watchdog definition
00487   * @note   The setting of these parameters with function is conditioned to ADC state.
00488   *         ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
00489   */
00490 typedef struct
00491 {
00492   uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
00493                                    This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
00494   uint32_t Channel;           /*!< Selects which ADC channel to monitor by analog watchdog.
00495                                    This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
00496                                    This parameter can be a value of @ref ADCEx_channels. */
00497   uint32_t ITMode;            /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
00498                                    This parameter can be set to ENABLE or DISABLE */
00499   uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
00500                                    This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
00501   uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
00502                                    This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
00503   uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0U */
00504 }ADC_AnalogWDGConfTypeDef;
00505 #endif /* STM32F373xC || STM32F378xx */
00506 /**
00507   * @}
00508   */
00509
00510 /* Exported constants --------------------------------------------------------*/
00511
00512 /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
00513   * @{
00514   */
00515
00516 /** @defgroup ADCEx_Error_Code ADC Extended Error Code
00517   * @{
00518   */
00519 #define HAL_ADC_ERROR_NONE        (0x00U)   /*!< No error                                              */
00520 #define HAL_ADC_ERROR_INTERNAL    (0x01U)   /*!< ADC IP internal error: if problem of clocking,
00521                                                           enable/disable, erroneous state                       */
00522 #define HAL_ADC_ERROR_OVR         (0x02U)   /*!< Overrun error                                         */
00523 #define HAL_ADC_ERROR_DMA         (0x04U)   /*!< DMA transfer error                                    */
00524 #define HAL_ADC_ERROR_JQOVF       (0x08U)   /*!< Injected context queue overflow error                 */
00525 /**
00526   * @}
00527   */
00528
00529 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00530     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00531     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00532     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00533 /** @defgroup ADCEx_ClockPrescaler ADC Extended Clock Prescaler
00534   * @{
00535   */
00536 #define ADC_CLOCK_ASYNC_DIV1          (0x00000000U)          /*!< ADC asynchronous clock derived from ADC dedicated PLL */
00537
00538 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00539     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00540     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
00541 #define ADC_CLOCK_SYNC_PCLK_DIV1      ((uint32_t)ADC12_CCR_CKMODE_0)  /*!< ADC synchronous clock derived from AHB clock without prescaler */
00542 #define ADC_CLOCK_SYNC_PCLK_DIV2      ((uint32_t)ADC12_CCR_CKMODE_1)  /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2U */
00543 #define ADC_CLOCK_SYNC_PCLK_DIV4      ((uint32_t)ADC12_CCR_CKMODE)    /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4U */
00544 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00545        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00546        /* STM32F303x8 || STM32F334x8 || STM32F328xx    */
00547
00548 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00549 #define ADC_CLOCK_SYNC_PCLK_DIV1      ((uint32_t)ADC1_CCR_CKMODE_0)   /*!< ADC synchronous clock derived from AHB clock without prescaler */
00550 #define ADC_CLOCK_SYNC_PCLK_DIV2      ((uint32_t)ADC1_CCR_CKMODE_1)   /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2U */
00551 #define ADC_CLOCK_SYNC_PCLK_DIV4      ((uint32_t)ADC1_CCR_CKMODE)     /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4U */
00552 #endif /* STM32F301x8 || STM32F318xx || STM32F302x8 */
00553
00554 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1)     || \
00555                                           ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
00556                                           ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
00557                                           ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4)   )
00558 /**
00559   * @}
00560   */
00561
00562 /** @defgroup ADCEx_Resolution ADC Extended Resolution
00563   * @{
00564   */
00565 #define ADC_RESOLUTION_12B      (0x00000000U)          /*!<  ADC 12-bit resolution */
00566 #define ADC_RESOLUTION_10B      ((uint32_t)ADC_CFGR_RES_0)      /*!<  ADC 10-bit resolution */
00567 #define ADC_RESOLUTION_8B       ((uint32_t)ADC_CFGR_RES_1)      /*!<  ADC 8-bit resolution */
00568 #define ADC_RESOLUTION_6B       ((uint32_t)ADC_CFGR_RES)        /*!<  ADC 6-bit resolution */
00569 /**
00570   * @}
00571   */
00572
00573 /** @defgroup ADCEx_Data_align ADC Extended Data Alignment
00574   * @{
00575   */
00576 #define ADC_DATAALIGN_RIGHT      (0x00000000U)
00577 #define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CFGR_ALIGN)
00578 /**
00579   * @}
00580   */
00581
00582 /** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode
00583   * @{
00584   */
00585 #define ADC_SCAN_DISABLE         (0x00000000U)
00586 #define ADC_SCAN_ENABLE          (0x00000001U)
00587 /**
00588   * @}
00589   */
00590
00591 /** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable and polarity selection for regular group
00592   * @{
00593   */
00594 #define ADC_EXTERNALTRIGCONVEDGE_NONE           (0x00000000U)
00595 #define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CFGR_EXTEN_0)
00596 #define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CFGR_EXTEN_1)
00597 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CFGR_EXTEN)
00598 /**
00599   * @}
00600   */
00601
00602 /** @defgroup ADCEx_External_trigger_source_Regular ADC Extended External trigger selection for regular group
00603   * @{
00604   */
00605 #if defined(STM32F303xE) || defined(STM32F398xx) || \
00606     defined(STM32F303xC) || defined(STM32F358xx)
00607 /*!< List of external triggers with generic trigger name, independently of    */
00608 /* ADC target (caution: applies to other ADCs sharing the same common group), */
00609 /* sorted by trigger name:                                                    */
00610
00611 /*!< External triggers of regular group for ADC1&ADC2 only */
00612 #define ADC_EXTERNALTRIGCONV_T1_CC1         ADC1_2_EXTERNALTRIG_T1_CC1
00613 #define ADC_EXTERNALTRIGCONV_T1_CC2         ADC1_2_EXTERNALTRIG_T1_CC2
00614 #define ADC_EXTERNALTRIGCONV_T2_CC2         ADC1_2_EXTERNALTRIG_T2_CC2
00615 #define ADC_EXTERNALTRIGCONV_T3_CC4         ADC1_2_EXTERNALTRIG_T3_CC4
00616 #define ADC_EXTERNALTRIGCONV_T4_CC4         ADC1_2_EXTERNALTRIG_T4_CC4
00617 #define ADC_EXTERNALTRIGCONV_T6_TRGO        ADC1_2_EXTERNALTRIG_T6_TRGO
00618 #define ADC_EXTERNALTRIGCONV_EXT_IT11       ADC1_2_EXTERNALTRIG_EXT_IT11
00619
00620 /*!< External triggers of regular group for ADC3&ADC4 only */
00621 #define ADC_EXTERNALTRIGCONV_T2_CC1         ADC3_4_EXTERNALTRIG_T2_CC1
00622 #define ADC_EXTERNALTRIGCONV_T2_CC3         ADC3_4_EXTERNALTRIG_T2_CC3
00623 #define ADC_EXTERNALTRIGCONV_T3_CC1         ADC3_4_EXTERNALTRIG_T3_CC1
00624 #define ADC_EXTERNALTRIGCONV_T4_CC1         ADC3_4_EXTERNALTRIG_T4_CC1
00625 #define ADC_EXTERNALTRIGCONV_T7_TRGO        ADC3_4_EXTERNALTRIG_T7_TRGO
00626 #define ADC_EXTERNALTRIGCONV_T8_CC1         ADC3_4_EXTERNALTRIG_T8_CC1
00627 #define ADC_EXTERNALTRIGCONV_EXT_IT2        ADC3_4_EXTERNALTRIG_EXT_IT2
00628
00629 /*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4 */
00630 /* Note: Triggers affected to group ADC1_2 by default, redirected to group    */
00631 /*       ADC3_4 by driver when needed.                                        */
00632 #define ADC_EXTERNALTRIGCONV_T1_CC3         ADC1_2_EXTERNALTRIG_T1_CC3
00633 #define ADC_EXTERNALTRIGCONV_T1_TRGO        ADC1_2_EXTERNALTRIG_T1_TRGO
00634 #define ADC_EXTERNALTRIGCONV_T1_TRGO2       ADC1_2_EXTERNALTRIG_T1_TRGO2
00635 #define ADC_EXTERNALTRIGCONV_T2_TRGO        ADC1_2_EXTERNALTRIG_T2_TRGO
00636 #define ADC_EXTERNALTRIGCONV_T3_TRGO        ADC1_2_EXTERNALTRIG_T3_TRGO
00637 #define ADC_EXTERNALTRIGCONV_T4_TRGO        ADC1_2_EXTERNALTRIG_T4_TRGO
00638 #define ADC_EXTERNALTRIGCONV_T8_TRGO        ADC1_2_EXTERNALTRIG_T8_TRGO
00639 #define ADC_EXTERNALTRIGCONV_T8_TRGO2       ADC1_2_EXTERNALTRIG_T8_TRGO2
00640 #define ADC_EXTERNALTRIGCONV_T15_TRGO       ADC1_2_EXTERNALTRIG_T15_TRGO
00641
00642 #define ADC_SOFTWARE_START                  (0x00000001U)
00643
00644 #if defined(STM32F303xE) || defined(STM32F398xx)
00645 /* ADC external triggers specific to device STM303xE: mask to differentiate   */
00646 /* standard triggers from specific timer 20U, needed for reallocation of       */
00647 /* triggers common to ADC1&2U/ADC3&4 and to avoid mixing with standard         */
00648 /* triggers without remap.                                                    */
00649 #define ADC_EXTERNALTRIGCONV_T20_MASK       0x1000
00650
00651 /*!< List of external triggers specific to device STM303xE: using Timer20     */
00652 /* with ADC trigger input remap.                                              */
00653 /* To remap ADC trigger from other timers/ExtLine to timer20: use macro       */
00654 /* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below:     */
00655
00656 /*!< External triggers of regular group for ADC1&ADC2 only, specific to       */
00657 /* device STM303xE: : using Timer20 with ADC trigger input remap              */
00658 #define ADC_EXTERNALTRIGCONV_T20_CC2        ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13U) */
00659 #define ADC_EXTERNALTRIGCONV_T20_CC3        ADC_EXTERNALTRIGCONV_T3_CC4  /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15U) */
00660
00661 /*!< External triggers of regular group for ADC3&ADC4 only, specific to       */
00662 /* device STM303xE: : using Timer20 with ADC trigger input remap              */
00663 /* None */
00664
00665 /*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to */
00666 /* device STM303xE: : using Timer20 with ADC trigger input remap              */
00667 /* Note: Triggers affected to group ADC1_2 by default, redirected to group    */
00668 /*       ADC3_4 by driver when needed.                                        */
00669 #define ADC_EXTERNALTRIGCONV_T20_CC1        (ADC_EXTERNALTRIGCONV_T4_CC4 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT5) */
00670                                                                                                           /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT15U) */
00671 #define ADC_EXTERNALTRIGCONV_T20_TRGO       (ADC_EXTERNALTRIGCONV_T1_CC3 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT2) */
00672                                                                                                           /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT5) */
00673 #define ADC_EXTERNALTRIGCONV_T20_TRGO2      (ADC_EXTERNALTRIGCONV_T2_CC2 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT3) */
00674                                                                                                           /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT6) */
00675 #endif /* STM32F303xE || STM32F398xx */
00676
00677 #endif /* STM32F303xE || STM32F398xx || */
00678        /* STM32F303xC || STM32F358xx    */
00679
00680 #if defined(STM32F302xE) || \
00681     defined(STM32F302xC)
00682 /*!< List of external triggers with generic trigger name, independently of    */
00683 /* ADC target (caution: applies to other ADCs sharing the same common group), */
00684 /* sorted by trigger name:                                                    */
00685
00686 /*!< External triggers of regular group for ADC1&ADC2 */
00687 #define ADC_EXTERNALTRIGCONV_T1_CC1         ADC1_2_EXTERNALTRIG_T1_CC1
00688 #define ADC_EXTERNALTRIGCONV_T1_CC2         ADC1_2_EXTERNALTRIG_T1_CC2
00689 #define ADC_EXTERNALTRIGCONV_T1_CC3         ADC1_2_EXTERNALTRIG_T1_CC3
00690 #define ADC_EXTERNALTRIGCONV_T1_TRGO        ADC1_2_EXTERNALTRIG_T1_TRGO
00691 #define ADC_EXTERNALTRIGCONV_T1_TRGO2       ADC1_2_EXTERNALTRIG_T1_TRGO2
00692 #define ADC_EXTERNALTRIGCONV_T2_CC2         ADC1_2_EXTERNALTRIG_T2_CC2
00693 #define ADC_EXTERNALTRIGCONV_T2_TRGO        ADC1_2_EXTERNALTRIG_T2_TRGO
00694 #define ADC_EXTERNALTRIGCONV_T3_CC4         ADC1_2_EXTERNALTRIG_T3_CC4
00695 #define ADC_EXTERNALTRIGCONV_T3_TRGO        ADC1_2_EXTERNALTRIG_T3_TRGO
00696 #define ADC_EXTERNALTRIGCONV_T4_CC4         ADC1_2_EXTERNALTRIG_T4_CC4
00697 #define ADC_EXTERNALTRIGCONV_T4_TRGO        ADC1_2_EXTERNALTRIG_T4_TRGO
00698 #define ADC_EXTERNALTRIGCONV_T6_TRGO        ADC1_2_EXTERNALTRIG_T6_TRGO
00699 #define ADC_EXTERNALTRIGCONV_T15_TRGO       ADC1_2_EXTERNALTRIG_T15_TRGO
00700 #define ADC_EXTERNALTRIGCONV_EXT_IT11       ADC1_2_EXTERNALTRIG_EXT_IT11
00701 #define ADC_SOFTWARE_START                  (0x00000001U)
00702
00703 #if defined(STM32F302xE)
00704 /* ADC external triggers specific to device STM302xE: mask to differentiate   */
00705 /* standard triggers from specific timer 20U, needed for reallocation of       */
00706 /* triggers common to ADC1&2 and to avoind mixing with standard               */
00707 /* triggers without remap.                                                    */
00708 #define ADC_EXTERNALTRIGCONV_T20_MASK       0x1000
00709
00710 /*!< List of external triggers specific to device STM302xE: using Timer20     */
00711 /* with ADC trigger input remap.                                              */
00712 /* To remap ADC trigger from other timers/ExtLine to timer20: use macro       */
00713 /* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below:     */
00714
00715 /*!< External triggers of regular group for ADC1&ADC2 only, specific to       */
00716 /* device STM302xE: : using Timer20 with ADC trigger input remap              */
00717 #define ADC_EXTERNALTRIGCONV_T20_CC2        ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13U) */
00718 #define ADC_EXTERNALTRIGCONV_T20_CC3        ADC_EXTERNALTRIGCONV_T3_CC4  /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15U) */
00719 #endif /* STM32F302xE */
00720
00721 #endif /* STM32F302xE || */
00722        /* STM32F302xC    */
00723
00724 #if defined(STM32F303x8) || defined(STM32F328xx)
00725 /*!< List of external triggers with generic trigger name, independently of    */
00726 /* ADC target (caution: applies to other ADCs sharing the same common group), */
00727 /* sorted by trigger name:                                                    */
00728
00729 /*!< External triggers of regular group for ADC1&ADC2 */
00730 #define ADC_EXTERNALTRIGCONV_T1_CC1         ADC1_2_EXTERNALTRIG_T1_CC1
00731 #define ADC_EXTERNALTRIGCONV_T1_CC2         ADC1_2_EXTERNALTRIG_T1_CC2
00732 #define ADC_EXTERNALTRIGCONV_T1_CC3         ADC1_2_EXTERNALTRIG_T1_CC3
00733 #define ADC_EXTERNALTRIGCONV_T1_TRGO        ADC1_2_EXTERNALTRIG_T1_TRGO
00734 #define ADC_EXTERNALTRIGCONV_T1_TRGO2       ADC1_2_EXTERNALTRIG_T1_TRGO2
00735 #define ADC_EXTERNALTRIGCONV_T2_CC2         ADC1_2_EXTERNALTRIG_T2_CC2
00736 #define ADC_EXTERNALTRIGCONV_T2_TRGO        ADC1_2_EXTERNALTRIG_T2_TRGO
00737 #define ADC_EXTERNALTRIGCONV_T3_CC4         ADC1_2_EXTERNALTRIG_T3_CC4
00738 #define ADC_EXTERNALTRIGCONV_T3_TRGO        ADC1_2_EXTERNALTRIG_T3_TRGO
00739 #define ADC_EXTERNALTRIGCONV_T4_CC4         ADC1_2_EXTERNALTRIG_T4_CC4
00740 #define ADC_EXTERNALTRIGCONV_T4_TRGO        ADC1_2_EXTERNALTRIG_T4_TRGO
00741 #define ADC_EXTERNALTRIGCONV_T8_TRGO        ADC1_2_EXTERNALTRIG_T8_TRGO
00742 #define ADC_EXTERNALTRIGCONV_T8_TRGO2       ADC1_2_EXTERNALTRIG_T8_TRGO2
00743 #define ADC_EXTERNALTRIGCONV_T6_TRGO        ADC1_2_EXTERNALTRIG_T6_TRGO
00744 #define ADC_EXTERNALTRIGCONV_T15_TRGO       ADC1_2_EXTERNALTRIG_T15_TRGO
00745 #define ADC_EXTERNALTRIGCONV_EXT_IT11       ADC1_2_EXTERNALTRIG_EXT_IT11
00746 #define ADC_SOFTWARE_START                  (0x00000001U)
00747
00748 #endif /* STM32F303x8 || STM32F328xx */
00749
00750 #if defined(STM32F334x8)
00751 /*!< List of external triggers with generic trigger name, independently of    */
00752 /* ADC target (caution: applies to other ADCs sharing the same common group), */
00753 /* sorted by trigger name:                                                    */
00754
00755 /*!< External triggers of regular group for ADC1&ADC2 */
00756 #define ADC_EXTERNALTRIGCONV_T1_CC1         ADC1_2_EXTERNALTRIG_T1_CC1
00757 #define ADC_EXTERNALTRIGCONV_T1_CC2         ADC1_2_EXTERNALTRIG_T1_CC2
00758 #define ADC_EXTERNALTRIGCONV_T1_CC3         ADC1_2_EXTERNALTRIG_T1_CC3
00759 #define ADC_EXTERNALTRIGCONV_T1_TRGO        ADC1_2_EXTERNALTRIG_T1_TRGO
00760 #define ADC_EXTERNALTRIGCONV_T1_TRGO2       ADC1_2_EXTERNALTRIG_T1_TRGO2
00761 #define ADC_EXTERNALTRIGCONV_T2_CC2         ADC1_2_EXTERNALTRIG_T2_CC2
00762 #define ADC_EXTERNALTRIGCONV_T2_TRGO        ADC1_2_EXTERNALTRIG_T2_TRGO
00763 #define ADC_EXTERNALTRIGCONV_T3_CC4         ADC1_2_EXTERNALTRIG_T3_CC4
00764 #define ADC_EXTERNALTRIGCONV_T3_TRGO        ADC1_2_EXTERNALTRIG_T3_TRGO
00765 #define ADC_EXTERNALTRIGCONV_T6_TRGO        ADC1_2_EXTERNALTRIG_T6_TRGO
00766 #define ADC_EXTERNALTRIGCONV_T15_TRGO       ADC1_2_EXTERNALTRIG_T15_TRGO
00767 #define ADC_EXTERNALTRIGCONVHRTIM_TRG1      ADC1_2_EXTERNALTRIG_HRTIM_TRG1
00768 #define ADC_EXTERNALTRIGCONVHRTIM_TRG3      ADC1_2_EXTERNALTRIG_HRTIM_TRG3
00769 #define ADC_EXTERNALTRIGCONV_EXT_IT11       ADC1_2_EXTERNALTRIG_EXT_IT11
00770 #define ADC_SOFTWARE_START                  (0x00000001U)
00771 #endif /* STM32F334x8 */
00772
00773 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00774 /* List of external triggers with generic trigger name, sorted by trigger     */
00775 /* name:                                                                      */
00776
00777 /* External triggers of regular group for ADC1 */
00778 #define ADC_EXTERNALTRIGCONV_T1_CC1         ADC1_EXTERNALTRIG_T1_CC1
00779 #define ADC_EXTERNALTRIGCONV_T1_CC2         ADC1_EXTERNALTRIG_T1_CC2
00780 #define ADC_EXTERNALTRIGCONV_T1_CC3         ADC1_EXTERNALTRIG_T1_CC3
00781 #define ADC_EXTERNALTRIGCONV_EXT_IT11       ADC1_EXTERNALTRIG_EXT_IT11
00782 #define ADC_EXTERNALTRIGCONV_T1_TRGO        ADC1_EXTERNALTRIG_T1_TRGO
00783 #define ADC_EXTERNALTRIGCONV_T1_TRGO2       ADC1_EXTERNALTRIG_T1_TRGO2
00784 #define ADC_EXTERNALTRIGCONV_T2_TRGO        ADC1_EXTERNALTRIG_T2_TRGO
00785 #define ADC_EXTERNALTRIGCONV_T6_TRGO        ADC1_EXTERNALTRIG_T6_TRGO
00786 #define ADC_EXTERNALTRIGCONV_T15_TRGO       ADC1_EXTERNALTRIG_T15_TRGO
00787 #define ADC_SOFTWARE_START                  (0x00000001U)
00788 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
00789 /**
00790   * @}
00791   */
00792
00793 /** @defgroup ADCEx_EOCSelection ADC Extended End of Regular Sequence/Conversion
00794   * @{
00795   */
00796 #define ADC_EOC_SINGLE_CONV         ((uint32_t) ADC_ISR_EOC)
00797 #define ADC_EOC_SEQ_CONV            ((uint32_t) ADC_ISR_EOS)
00798 /**
00799   * @}
00800   */
00801
00802 /** @defgroup ADCEx_Overrun ADC Extended overrun
00803   * @{
00804   */
00805 #define ADC_OVR_DATA_OVERWRITTEN    (0x00000000U)   /*!< Default setting, to be used for compatibility with other STM32 devices */
00806 #define ADC_OVR_DATA_PRESERVED      (0x00000001U)
00807 /**
00808   * @}
00809   */
00810
00811 /** @defgroup ADCEx_channels ADC Extended Channels
00812   * @{
00813   */
00814 /* Note: Depending on devices, some channels may not be available on package  */
00815 /*       pins. Refer to device datasheet for channels availability.           */
00816 #define ADC_CHANNEL_1           ((uint32_t)(ADC_SQR3_SQ10_0))
00817 #define ADC_CHANNEL_2           ((uint32_t)(ADC_SQR3_SQ10_1))
00818 #define ADC_CHANNEL_3           ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
00819 #define ADC_CHANNEL_4           ((uint32_t)(ADC_SQR3_SQ10_2))
00820 #define ADC_CHANNEL_5           ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
00821 #define ADC_CHANNEL_6           ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
00822 #define ADC_CHANNEL_7           ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
00823 #define ADC_CHANNEL_8           ((uint32_t)(ADC_SQR3_SQ10_3))
00824 #define ADC_CHANNEL_9           ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0))
00825 #define ADC_CHANNEL_10          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1))
00826 #define ADC_CHANNEL_11          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
00827 #define ADC_CHANNEL_12          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2))
00828 #define ADC_CHANNEL_13          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
00829 #define ADC_CHANNEL_14          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
00830 #define ADC_CHANNEL_15          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
00831 #define ADC_CHANNEL_16          ((uint32_t)(ADC_SQR3_SQ10_4))
00832 #define ADC_CHANNEL_17          ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0))
00833 #define ADC_CHANNEL_18          ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1))
00834
00835 /* Note: Vopamp1, TempSensor and Vbat internal channels available on ADC1 only */
00836 #define ADC_CHANNEL_VOPAMP1     ADC_CHANNEL_15
00837 #define ADC_CHANNEL_TEMPSENSOR  ADC_CHANNEL_16
00838 #define ADC_CHANNEL_VBAT        ADC_CHANNEL_17
00839
00840 /* Note: Vopamp2/3U/4 internal channels available on ADC2/3U/4 respectively     */
00841 #define ADC_CHANNEL_VOPAMP2     ADC_CHANNEL_17
00842 #define ADC_CHANNEL_VOPAMP3     ADC_CHANNEL_17
00843 #define ADC_CHANNEL_VOPAMP4     ADC_CHANNEL_17
00844
00845 /* Note: VrefInt internal channels available on all ADCs, but only            */
00846 /*       one ADC is allowed to be connected to VrefInt at the same time.      */
00847 #define ADC_CHANNEL_VREFINT     ((uint32_t)ADC_CHANNEL_18)
00848 /**
00849   * @}
00850   */
00851
00852 /** @defgroup ADCEx_sampling_times ADC Extended Sampling Times
00853   * @{
00854   */
00855 #define ADC_SAMPLETIME_1CYCLE_5       (0x00000000U)                              /*!< Sampling time 1.5 ADC clock cycle */
00856 #define ADC_SAMPLETIME_2CYCLES_5      ((uint32_t)ADC_SMPR2_SMP10_0)                       /*!< Sampling time 2.5 ADC clock cycles */
00857 #define ADC_SAMPLETIME_4CYCLES_5      ((uint32_t)ADC_SMPR2_SMP10_1)                       /*!< Sampling time 4.5 ADC clock cycles */
00858 #define ADC_SAMPLETIME_7CYCLES_5      ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 7.5 ADC clock cycles */
00859 #define ADC_SAMPLETIME_19CYCLES_5     ((uint32_t)ADC_SMPR2_SMP10_2)                       /*!< Sampling time 19.5 ADC clock cycles */
00860 #define ADC_SAMPLETIME_61CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 61.5 ADC clock cycles */
00861 #define ADC_SAMPLETIME_181CYCLES_5    ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)) /*!< Sampling time 181.5 ADC clock cycles */
00862 #define ADC_SAMPLETIME_601CYCLES_5    ((uint32_t)ADC_SMPR2_SMP10)                         /*!< Sampling time 601.5 ADC clock cycles */
00863 /**
00864   * @}
00865   */
00866
00867 /** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode
00868   * @{
00869   */
00870 #define ADC_SINGLE_ENDED                (0x00000000U)
00871 #define ADC_DIFFERENTIAL_ENDED          (0x00000001U)
00872 /**
00873   * @}
00874   */
00875
00876 /** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number
00877   * @{
00878   */
00879 #define ADC_OFFSET_NONE               (0x00U)
00880 #define ADC_OFFSET_1                  (0x01U)
00881 #define ADC_OFFSET_2                  (0x02U)
00882 #define ADC_OFFSET_3                  (0x03U)
00883 #define ADC_OFFSET_4                  (0x04U)
00884 /**
00885   * @}
00886   */
00887
00888 /** @defgroup ADCEx_regular_rank ADC Extended rank into regular group
00889   * @{
00890   */
00891 #define ADC_REGULAR_RANK_1    (0x00000001U)
00892 #define ADC_REGULAR_RANK_2    (0x00000002U)
00893 #define ADC_REGULAR_RANK_3    (0x00000003U)
00894 #define ADC_REGULAR_RANK_4    (0x00000004U)
00895 #define ADC_REGULAR_RANK_5    (0x00000005U)
00896 #define ADC_REGULAR_RANK_6    (0x00000006U)
00897 #define ADC_REGULAR_RANK_7    (0x00000007U)
00898 #define ADC_REGULAR_RANK_8    (0x00000008U)
00899 #define ADC_REGULAR_RANK_9    (0x00000009U)
00900 #define ADC_REGULAR_RANK_10   (0x0000000AU)
00901 #define ADC_REGULAR_RANK_11   (0x0000000BU)
00902 #define ADC_REGULAR_RANK_12   (0x0000000CU)
00903 #define ADC_REGULAR_RANK_13   (0x0000000DU)
00904 #define ADC_REGULAR_RANK_14   (0x0000000EU)
00905 #define ADC_REGULAR_RANK_15   (0x0000000FU)
00906 #define ADC_REGULAR_RANK_16   (0x00000010U)
00907 /**
00908   * @}
00909   */
00910
00911 /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
00912   * @{
00913   */
00914 #define ADC_INJECTED_RANK_1    (0x00000001U)
00915 #define ADC_INJECTED_RANK_2    (0x00000002U)
00916 #define ADC_INJECTED_RANK_3    (0x00000003U)
00917 #define ADC_INJECTED_RANK_4    (0x00000004U)
00918 /**
00919   * @}
00920   */
00921
00922 /** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group
00923   * @{
00924   */
00925 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           (0x00000000U)
00926 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         ((uint32_t)ADC_JSQR_JEXTEN_0)
00927 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING        ((uint32_t)ADC_JSQR_JEXTEN_1)
00928 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING  ((uint32_t)ADC_JSQR_JEXTEN)
00929 /**
00930   * @}
00931   */
00932
00933 /** @defgroup ADCEx_External_trigger_source_Injected External Trigger Source of Injected Group
00934   * @{
00935   */
00936 #if defined(STM32F303xE) || defined(STM32F398xx) || \
00937     defined(STM32F303xC) || defined(STM32F358xx)
00938 /* List of external triggers with generic trigger name, independently of ADC  */
00939 /* target (caution: applies to other ADCs sharing the same common group),     */
00940 /* sorted by trigger name:                                                    */
00941
00942 /* External triggers of injected group for ADC1&ADC2 only */
00943 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1    ADC1_2_EXTERNALTRIGINJEC_T2_CC1
00944 #define ADC_EXTERNALTRIGINJECCONV_T3_CC1    ADC1_2_EXTERNALTRIGINJEC_T3_CC1
00945 #define ADC_EXTERNALTRIGINJECCONV_T3_CC3    ADC1_2_EXTERNALTRIGINJEC_T3_CC3
00946 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4    ADC1_2_EXTERNALTRIGINJEC_T3_CC4
00947 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO   ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
00948 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15  ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
00949
00950 /* External triggers of injected group for ADC3&ADC4 only */
00951 #define ADC_EXTERNALTRIGINJECCONV_T1_CC3    ADC3_4_EXTERNALTRIGINJEC_T1_CC3
00952 #define ADC_EXTERNALTRIGINJECCONV_T4_CC3    ADC3_4_EXTERNALTRIGINJEC_T4_CC3
00953 #define ADC_EXTERNALTRIGINJECCONV_T4_CC4    ADC3_4_EXTERNALTRIGINJEC_T4_CC4
00954 #define ADC_EXTERNALTRIGINJECCONV_T7_TRGO   ADC3_4_EXTERNALTRIGINJEC_T7_TRGO
00955 #define ADC_EXTERNALTRIGINJECCONV_T8_CC2    ADC3_4_EXTERNALTRIGINJEC_T8_CC2
00956
00957 /* External triggers of injected group for ADC1&ADC2, ADC3&ADC4 */
00958 /* Note: Triggers affected to group ADC1_2 by default, redirected to group    */
00959 /*       ADC3_4 by driver when needed.                                        */
00960 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4    ADC1_2_EXTERNALTRIGINJEC_T1_CC4
00961 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO   ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
00962 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2  ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
00963 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO   ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
00964 #define ADC_EXTERNALTRIGINJECCONV_T3_TRGO   ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
00965 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO   ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
00966 #define ADC_EXTERNALTRIGINJECCONV_T8_CC4    ADC1_2_EXTERNALTRIGINJEC_T8_CC4
00967 #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO   ADC1_2_EXTERNALTRIGINJEC_T8_TRGO
00968 #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2  ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2
00969 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO  ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
00970
00971 #define ADC_INJECTED_SOFTWARE_START     (0x00000001U)
00972
00973 #if defined(STM32F303xE) || defined(STM32F398xx)
00974 /*!< List of external triggers specific to device STM303xE: using Timer20     */
00975 /* with ADC trigger input remap.                                              */
00976 /* To remap ADC trigger from other timers/ExtLine to timer20: use macro       */
00977 /* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below:     */
00978
00979 /*!< External triggers of injected group for ADC1&ADC2 only, specific to      */
00980 /* device STM303xE: : using Timer20 with ADC trigger input remap              */
00981 #define ADC_EXTERNALTRIGINJECCONV_T20_CC4        ADC_EXTERNALTRIGINJECCONV_T3_CC1  /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13U) */
00982
00983 /*!< External triggers of injected group for ADC3&ADC4 only, specific to      */
00984 /* device STM303xE: : using Timer20 with ADC trigger input remap              */
00985 #define ADC_EXTERNALTRIGINJECCONV_T20_CC2        ADC_EXTERNALTRIGINJECCONV_T7_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT14U) */
00986
00987 /*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to */
00988 /* device STM303xE: : using Timer20 with ADC trigger input remap              */
00989 /* Note: Triggers affected to group ADC1_2 by default, redirected to group    */
00990 /*       ADC3_4 by driver when needed.                                        */
00991 #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO       (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK)   /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */
00992                                                                                                                       /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT5) */
00993 #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2      (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */
00994                                                                                                                       /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT11U) */
00995 #endif /* STM32F303xE || STM32F398xx */
00996
00997 #if defined(STM32F303xC) || defined(STM32F358xx)
00998 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
00999                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1)   || \
01000                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
01001                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)  || \
01002                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
01003                                                                                            \
01004                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3)   || \
01005                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4)   || \
01006                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO)  || \
01007                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2)   || \
01008                                                                                            \
01009                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
01010                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
01011                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
01012                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
01013                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3)   || \
01014                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO)  || \
01015                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
01016                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)   || \
01017                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO)  || \
01018                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
01019                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
01020                                                                                            \
01021                                       ((INJTRIG) == ADC_INJECTED_SOFTWARE_START)          )
01022 #endif /* STM32F303xC || STM32F358xx */
01023
01024 #if defined(STM32F303xE) || defined(STM32F398xx)
01025 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)    || \
01026                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1)    || \
01027                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)    || \
01028                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)   || \
01029                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)  || \
01030                                                                                             \
01031                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3)    || \
01032                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4)    || \
01033                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO)   || \
01034                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2)    || \
01035                                                                                             \
01036                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)    || \
01037                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)   || \
01038                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2)  || \
01039                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)   || \
01040                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3)    || \
01041                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO)   || \
01042                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)   || \
01043                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)    || \
01044                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO)   || \
01045                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2)  || \
01046                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO)  || \
01047                                                                                             \
01048                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4)   || \
01049                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC2)   || \
01050                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO)  || \
01051                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \
01052                                                                                             \
01053                                       ((INJTRIG) == ADC_INJECTED_SOFTWARE_START)           )
01054 #endif /* STM32F303xE || STM32F398xx */
01055
01056 #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
01057
01058 #if defined(STM32F302xE) || \
01059     defined(STM32F302xC)
01060 /*!< List of external triggers with generic trigger name, independently of    */
01061 /* ADC target (caution: applies to other ADCs sharing the same common group), */
01062 /* sorted by trigger name:                                                    */
01063
01064 /* External triggers of injected group for ADC1&ADC2 */
01065 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4    ADC1_2_EXTERNALTRIGINJEC_T1_CC4
01066 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO   ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
01067 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2  ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
01068 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1    ADC1_2_EXTERNALTRIGINJEC_T2_CC1
01069 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO   ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
01070 #define ADC_EXTERNALTRIGINJECCONV_T3_CC1    ADC1_2_EXTERNALTRIGINJEC_T3_CC1
01071 #define ADC_EXTERNALTRIGINJECCONV_T3_CC3    ADC1_2_EXTERNALTRIGINJEC_T3_CC3
01072 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4    ADC1_2_EXTERNALTRIGINJEC_T3_CC4
01073 #define ADC_EXTERNALTRIGINJECCONV_T3_TRGO   ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
01074 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO   ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
01075 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO   ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
01076 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO  ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
01077 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15  ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
01078
01079 #define ADC_INJECTED_SOFTWARE_START     (0x00000001U)
01080
01081 #if defined(STM32F302xE)
01082 /*!< List of external triggers specific to device STM302xE: using Timer20     */
01083 /* with ADC trigger input remap.                                              */
01084 /* To remap ADC trigger from other timers/ExtLine to timer20: use macro       */
01085 /* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below:     */
01086
01087 /*!< External triggers of injected group for ADC1&ADC2 only, specific to      */
01088 /* device STM302xE: : using Timer20 with ADC trigger input remap              */
01089 #define ADC_EXTERNALTRIGINJECCONV_T20_CC4        ADC_EXTERNALTRIGINJECCONV_T3_CC1  /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13U) */
01090 #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO       (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK)   /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */
01091 #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2      (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */
01092 #endif /* STM32F302xE */
01093
01094 #endif /* STM32F302xE || */
01095        /* STM32F302xC    */
01096
01097 #if defined(STM32F303x8) || defined(STM32F328xx)
01098 /*!< List of external triggers with generic trigger name, independently of    */
01099 /* ADC target (caution: applies to other ADCs sharing the same common group), */
01100 /* sorted by trigger name:                                                    */
01101
01102 /* External triggers of injected group for ADC1&ADC2 */
01103 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4       ADC1_2_EXTERNALTRIGINJEC_T1_CC4
01104 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO      ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
01105 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2     ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
01106 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1       ADC1_2_EXTERNALTRIGINJEC_T2_CC1
01107 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO      ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
01108 #define ADC_EXTERNALTRIGINJECCONV_T3_CC1       ADC1_2_EXTERNALTRIGINJEC_T3_CC1
01109 #define ADC_EXTERNALTRIGINJECCONV_T3_CC3       ADC1_2_EXTERNALTRIGINJEC_T3_CC3
01110 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4       ADC1_2_EXTERNALTRIGINJEC_T3_CC4
01111 #define ADC_EXTERNALTRIGINJECCONV_T3_TRGO      ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
01112 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO      ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
01113 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO      ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
01114 #define ADC_EXTERNALTRIGINJECCONV_T8_CC4       ADC1_2_EXTERNALTRIGINJEC_T8_CC4
01115 #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO      ADC1_2_EXTERNALTRIGINJEC_T8_TRGO
01116 #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2     ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2
01117 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO     ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
01118 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15     ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
01119
01120 #define ADC_INJECTED_SOFTWARE_START     (0x00000001U)
01121 #endif /* STM32F303x8 || STM32F328xx */
01122
01123 #if defined(STM32F334x8)
01124 /*!< List of external triggers with generic trigger name, independently of    */
01125 /* ADC target (caution: applies to other ADCs sharing the same common group), */
01126 /* sorted by trigger name:                                                    */
01127
01128 /* External triggers of injected group for ADC1&ADC2 */
01129 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4       ADC1_2_EXTERNALTRIGINJEC_T1_CC4
01130 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO      ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
01131 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2     ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
01132 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1       ADC1_2_EXTERNALTRIGINJEC_T2_CC1
01133 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO      ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
01134 #define ADC_EXTERNALTRIGINJECCONV_T3_CC1       ADC1_2_EXTERNALTRIGINJEC_T3_CC1
01135 #define ADC_EXTERNALTRIGINJECCONV_T3_CC3       ADC1_2_EXTERNALTRIGINJEC_T3_CC3
01136 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4       ADC1_2_EXTERNALTRIGINJEC_T3_CC4
01137 #define ADC_EXTERNALTRIGINJECCONV_T3_TRGO      ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
01138 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO      ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
01139 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO     ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
01140 #define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG2   ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG2
01141 #define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4   ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4
01142 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15     ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
01143
01144 #define ADC_INJECTED_SOFTWARE_START     (0x00000001U)
01145 #endif /* STM32F334x8 */
01146
01147 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01148 /* List of external triggers with generic trigger name, sorted by trigger     */
01149 /* name:                                                                      */
01150
01151 /* External triggers of injected group for ADC1 */
01152 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4     ADC1_EXTERNALTRIGINJEC_T1_CC4
01153 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO    ADC1_EXTERNALTRIGINJEC_T1_TRGO
01154 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2   ADC1_EXTERNALTRIGINJEC_T1_TRGO2
01155 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1     ADC1_EXTERNALTRIGINJEC_T2_CC1
01156 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO    ADC1_EXTERNALTRIGINJEC_T2_TRGO
01157 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO    ADC1_EXTERNALTRIGINJEC_T6_TRGO
01158 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO   ADC1_EXTERNALTRIGINJEC_T15_TRGO
01159 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15   ADC1_EXTERNALTRIGINJEC_EXT_IT15
01160
01161 #define ADC_INJECTED_SOFTWARE_START     (0x00000001U)
01162 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
01163 /**
01164   * @}
01165   */
01166
01167
01168 /** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
01169   * @{
01170   */
01171 #define ADC_MODE_INDEPENDENT                  ((uint32_t)(0x00000000U))
01172 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)(ADC12_CCR_MULTI_0))
01173 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)(ADC12_CCR_MULTI_1))
01174 #define ADC_DUALMODE_REGINTERL_INJECSIMULT    ((uint32_t)(ADC12_CCR_MULTI_1 | ADC12_CCR_MULTI_0))
01175 #define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_0))
01176 #define ADC_DUALMODE_REGSIMULT                ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_1))
01177 #define ADC_DUALMODE_INTERL                   ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_1 | ADC12_CCR_MULTI_0))
01178 #define ADC_DUALMODE_ALTERTRIG                ((uint32_t)(ADC12_CCR_MULTI_3 | ADC12_CCR_MULTI_0))
01179 /**
01180   * @}
01181   */
01182
01183
01184 /** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA Mode for Dual ADC Mode
01185   * @{
01186   */
01187 #define ADC_DMAACCESSMODE_DISABLED      (0x00000000U)         /*!< DMA multimode disabled: each ADC will use its own DMA channel */
01188 #define ADC_DMAACCESSMODE_12_10_BITS    ((uint32_t)ADC12_CCR_MDMA_1)   /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
01189 #define ADC_DMAACCESSMODE_8_6_BITS      ((uint32_t)ADC12_CCR_MDMA)     /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
01190 /**
01191   * @}
01192   */
01193
01194 /** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended Delay Between 2 Sampling Phases
01195   * @{
01196   */
01197 #define ADC_TWOSAMPLINGDELAY_1CYCLE     ((uint32_t)(0x00000000U))
01198 #define ADC_TWOSAMPLINGDELAY_2CYCLES    ((uint32_t)(ADC12_CCR_DELAY_0))
01199 #define ADC_TWOSAMPLINGDELAY_3CYCLES    ((uint32_t)(ADC12_CCR_DELAY_1))
01200 #define ADC_TWOSAMPLINGDELAY_4CYCLES    ((uint32_t)(ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0))
01201 #define ADC_TWOSAMPLINGDELAY_5CYCLES    ((uint32_t)(ADC12_CCR_DELAY_2))
01202 #define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_0))
01203 #define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_1))
01204 #define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0))
01205 #define ADC_TWOSAMPLINGDELAY_9CYCLES    ((uint32_t)(ADC12_CCR_DELAY_3))
01206 #define ADC_TWOSAMPLINGDELAY_10CYCLES   ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_0))
01207 #define ADC_TWOSAMPLINGDELAY_11CYCLES   ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_1))
01208 #define ADC_TWOSAMPLINGDELAY_12CYCLES   ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0))
01209 /**
01210   * @}
01211   */
01212
01213 /** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection
01214   * @{
01215   */
01216 #define ADC_ANALOGWATCHDOG_1                    (0x00000001U)
01217 #define ADC_ANALOGWATCHDOG_2                    (0x00000002U)
01218 #define ADC_ANALOGWATCHDOG_3                    (0x00000003U)
01219 /**
01220   * @}
01221   */
01222
01223 /** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode
01224   * @{
01225   */
01226 #define ADC_ANALOGWATCHDOG_NONE                 ( 0x00000000U)
01227 #define ADC_ANALOGWATCHDOG_SINGLE_REG           ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN))
01228 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC         ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN))
01229 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))
01230 #define ADC_ANALOGWATCHDOG_ALL_REG              ((uint32_t) ADC_CFGR_AWD1EN)
01231 #define ADC_ANALOGWATCHDOG_ALL_INJEC            ((uint32_t) ADC_CFGR_JAWD1EN)
01232 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC         ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))
01233 /**
01234   * @}
01235   */
01236
01237 /** @defgroup ADC_conversion_group ADC Conversion Group
01238   * @{
01239   */
01240 #define ADC_REGULAR_GROUP             ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))
01241 #define ADC_INJECTED_GROUP            ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS))
01242 #define ADC_REGULAR_INJECTED_GROUP    ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS))
01243
01244 /**
01245   * @}
01246   */
01247
01248 /** @defgroup ADCEx_Event_type ADC Extended Event Type
01249   * @{
01250   */
01251 #define ADC_AWD1_EVENT           ((uint32_t)ADC_FLAG_AWD1)  /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) */
01252 #define ADC_AWD2_EVENT           ((uint32_t)ADC_FLAG_AWD2)  /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families) */
01253 #define ADC_AWD3_EVENT           ((uint32_t)ADC_FLAG_AWD3)  /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families) */
01254 #define ADC_OVR_EVENT            ((uint32_t)ADC_FLAG_OVR)   /*!< ADC overrun event */
01255 #define ADC_JQOVF_EVENT          ((uint32_t)ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
01256
01257 #define ADC_AWD_EVENT            ADC_AWD1_EVENT         /* ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */
01258 /**
01259   * @}
01260   */
01261
01262 /** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
01263   * @{
01264   */
01265 #define ADC_IT_RDY           ADC_IER_RDY        /*!< ADC Ready (ADRDY) interrupt source */
01266 #define ADC_IT_EOSMP         ADC_IER_EOSMP      /*!< ADC End of Sampling interrupt source */
01267 #define ADC_IT_EOC           ADC_IER_EOC        /*!< ADC End of Regular Conversion interrupt source */
01268 #define ADC_IT_EOS           ADC_IER_EOS        /*!< ADC End of Regular sequence of Conversions interrupt source */
01269 #define ADC_IT_OVR           ADC_IER_OVR        /*!< ADC overrun interrupt source */
01270 #define ADC_IT_JEOC          ADC_IER_JEOC       /*!< ADC End of Injected Conversion interrupt source */
01271 #define ADC_IT_JEOS          ADC_IER_JEOS       /*!< ADC End of Injected sequence of Conversions interrupt source */
01272 #define ADC_IT_AWD1          ADC_IER_AWD1       /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices) */
01273 #define ADC_IT_AWD2          ADC_IER_AWD2       /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices) */
01274 #define ADC_IT_AWD3          ADC_IER_AWD3       /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices) */
01275 #define ADC_IT_JQOVF         ADC_IER_JQOVF      /*!< ADC Injected Context Queue Overflow interrupt source */
01276
01277 #define ADC_IT_AWD           ADC_IT_AWD1        /* ADC Analog watchdog 1 interrupt source: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */
01278 /**
01279   * @}
01280   */
01281
01282 /** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
01283   * @{
01284   */
01285 #define ADC_FLAG_RDY           ADC_ISR_ADRD     /*!< ADC Ready (ADRDY) flag */
01286 #define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
01287 #define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
01288 #define ADC_FLAG_EOS           ADC_ISR_EOS      /*!< ADC End of Regular sequence of Conversions flag */
01289 #define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
01290 #define ADC_FLAG_JEOC          ADC_ISR_JEOC     /*!< ADC End of Injected Conversion flag */
01291 #define ADC_FLAG_JEOS          ADC_ISR_JEOS     /*!< ADC End of Injected sequence of Conversions flag */
01292 #define ADC_FLAG_AWD1          ADC_ISR_AWD1     /*!< ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices) */
01293 #define ADC_FLAG_AWD2          ADC_ISR_AWD2     /*!< ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices) */
01294 #define ADC_FLAG_AWD3          ADC_ISR_AWD3     /*!< ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices) */
01295 #define ADC_FLAG_JQOVF         ADC_ISR_JQOVF    /*!< ADC Injected Context Queue Overflow flag */
01296
01297 #define ADC_FLAG_AWD           ADC_FLAG_AWD1    /* ADC Analog watchdog 1 flag: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */
01298 /**
01299   * @}
01300   */
01301
01302 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
01303        /* STM32F302xC || STM32F303xC || STM32F358xx || */
01304        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
01305        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
01306
01307
01308 #if defined(STM32F373xC) || defined(STM32F378xx)
01309 /** @defgroup ADCEx_Data_align ADC Extended Data Alignment
01310   * @{
01311   */
01312 #define ADC_DATAALIGN_RIGHT      (0x00000000U)
01313 #define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)
01314 /**
01315   * @}
01316   */
01317
01318 /** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode
01319   * @{
01320   */
01321 #define ADC_SCAN_DISABLE         (0x00000000U)
01322 #define ADC_SCAN_ENABLE          ((uint32_t)ADC_CR1_SCAN)
01323 /**
01324   * @}
01325   */
01326
01327 /** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable for regular group
01328   * @{
01329   */
01330 #define ADC_EXTERNALTRIGCONVEDGE_NONE           (0x00000000U)
01331 #define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTTRIG)
01332 /**
01333   * @}
01334   */
01335
01336 /** @defgroup ADCEx_External_trigger_source_Regular ADC Extended External trigger selection for regular group
01337   * @{
01338   */
01339 /* List of external triggers with generic trigger name, sorted by trigger     */
01340 /* name:                                                                      */
01341
01342 /* External triggers of regular group for ADC1 */
01343 #define ADC_EXTERNALTRIGCONV_T2_CC2      ADC_EXTERNALTRIG_T2_CC2
01344 #define ADC_EXTERNALTRIGCONV_T3_TRGO     ADC_EXTERNALTRIG_T3_TRGO
01345 #define ADC_EXTERNALTRIGCONV_T4_CC4      ADC_EXTERNALTRIG_T4_CC4
01346 #define ADC_EXTERNALTRIGCONV_T19_TRGO    ADC_EXTERNALTRIG_T19_TRGO
01347 #define ADC_EXTERNALTRIGCONV_T19_CC3     ADC_EXTERNALTRIG_T19_CC3
01348 #define ADC_EXTERNALTRIGCONV_T19_CC4     ADC_EXTERNALTRIG_T19_CC4
01349 #define ADC_EXTERNALTRIGCONV_EXT_IT11    ADC_EXTERNALTRIG_EXT_IT11
01350 #define ADC_SOFTWARE_START               ADC_SWSTART
01351 /**
01352   * @}
01353   */
01354
01355 /** @defgroup ADCEx_channels ADC Extended Channels
01356   * @{
01357   */
01358 /* Note: Depending on devices, some channels may not be available on package  */
01359 /*       pins. Refer to device datasheet for channels availability.           */
01360 #define ADC_CHANNEL_0           (0x00000000U)
01361 #define ADC_CHANNEL_1           ((uint32_t)(ADC_SQR3_SQ1_0))
01362 #define ADC_CHANNEL_2           ((uint32_t)(ADC_SQR3_SQ1_1))
01363 #define ADC_CHANNEL_3           ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
01364 #define ADC_CHANNEL_4           ((uint32_t)(ADC_SQR3_SQ1_2))
01365 #define ADC_CHANNEL_5           ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
01366 #define ADC_CHANNEL_6           ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
01367 #define ADC_CHANNEL_7           ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
01368 #define ADC_CHANNEL_8           ((uint32_t)(ADC_SQR3_SQ1_3))
01369 #define ADC_CHANNEL_9           ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
01370 #define ADC_CHANNEL_10          ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1))
01371 #define ADC_CHANNEL_11          ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
01372 #define ADC_CHANNEL_12          ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2))
01373 #define ADC_CHANNEL_13          ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
01374 #define ADC_CHANNEL_14          ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
01375 #define ADC_CHANNEL_15          ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
01376 #define ADC_CHANNEL_16          ((uint32_t)(ADC_SQR3_SQ1_4))
01377 #define ADC_CHANNEL_17          ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
01378 #define ADC_CHANNEL_18          ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_1))
01379
01380 #define ADC_CHANNEL_TEMPSENSOR  ADC_CHANNEL_16
01381 #define ADC_CHANNEL_VREFINT     ADC_CHANNEL_17
01382 #define ADC_CHANNEL_VBAT        ADC_CHANNEL_18
01383 /**
01384   * @}
01385   */
01386
01387 /** @defgroup ADCEx_sampling_times ADC Extended Sampling Times
01388   * @{
01389   */
01390 #define ADC_SAMPLETIME_1CYCLE_5       (0x00000000U)                            /*!< Sampling time 1.5 ADC clock cycle */
01391 #define ADC_SAMPLETIME_7CYCLES_5      ((uint32_t) ADC_SMPR2_SMP0_0)                     /*!< Sampling time 7.5 ADC clock cycles */
01392 #define ADC_SAMPLETIME_13CYCLES_5     ((uint32_t) ADC_SMPR2_SMP0_1)                     /*!< Sampling time 13.5 ADC clock cycles */
01393 #define ADC_SAMPLETIME_28CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */
01394 #define ADC_SAMPLETIME_41CYCLES_5     ((uint32_t) ADC_SMPR2_SMP0_2)                     /*!< Sampling time 41.5 ADC clock cycles */
01395 #define ADC_SAMPLETIME_55CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */
01396 #define ADC_SAMPLETIME_71CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)) /*!< Sampling time 71.5 ADC clock cycles */
01397 #define ADC_SAMPLETIME_239CYCLES_5    ((uint32_t) ADC_SMPR2_SMP0)                       /*!< Sampling time 239.5 ADC clock cycles */
01398 /**
01399   * @}
01400   */
01401
01402 /** @defgroup ADCEx_regular_rank ADC Extended rank into regular group
01403   * @{
01404   */
01405 #define ADC_REGULAR_RANK_1    (0x00000001U)
01406 #define ADC_REGULAR_RANK_2    (0x00000002U)
01407 #define ADC_REGULAR_RANK_3    (0x00000003U)
01408 #define ADC_REGULAR_RANK_4    (0x00000004U)
01409 #define ADC_REGULAR_RANK_5    (0x00000005U)
01410 #define ADC_REGULAR_RANK_6    (0x00000006U)
01411 #define ADC_REGULAR_RANK_7    (0x00000007U)
01412 #define ADC_REGULAR_RANK_8    (0x00000008U)
01413 #define ADC_REGULAR_RANK_9    (0x00000009U)
01414 #define ADC_REGULAR_RANK_10   (0x0000000AU)
01415 #define ADC_REGULAR_RANK_11   (0x0000000BU)
01416 #define ADC_REGULAR_RANK_12   (0x0000000CU)
01417 #define ADC_REGULAR_RANK_13   (0x0000000DU)
01418 #define ADC_REGULAR_RANK_14   (0x0000000EU)
01419 #define ADC_REGULAR_RANK_15   (0x0000000FU)
01420 #define ADC_REGULAR_RANK_16   (0x00000010U)
01421 /**
01422   * @}
01423   */
01424
01425 /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
01426   * @{
01427   */
01428 #define ADC_INJECTED_RANK_1    (0x00000001U)
01429 #define ADC_INJECTED_RANK_2    (0x00000002U)
01430 #define ADC_INJECTED_RANK_3    (0x00000003U)
01431 #define ADC_INJECTED_RANK_4    (0x00000004U)
01432 /**
01433   * @}
01434   */
01435
01436 /** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group
01437   * @{
01438   */
01439 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           (0x00000000U)
01440 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         ((uint32_t)ADC_CR2_JEXTTRIG)
01441 /**
01442   * @}
01443   */
01444
01445 /** @defgroup ADCEx_External_trigger_source_Injected External Trigger Source of Injected Group
01446   * @{
01447   */
01448 /* External triggers for injected groups of ADC1 */
01449 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1       ADC_EXTERNALTRIGINJEC_T2_CC1
01450 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO      ADC_EXTERNALTRIGINJEC_T2_TRGO
01451 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4       ADC_EXTERNALTRIGINJEC_T3_CC4
01452 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO      ADC_EXTERNALTRIGINJEC_T4_TRGO
01453 #define ADC_EXTERNALTRIGINJECCONV_T19_CC1      ADC_EXTERNALTRIGINJEC_T19_CC1
01454 #define ADC_EXTERNALTRIGINJECCONV_T19_CC2      ADC_EXTERNALTRIGINJEC_T19_CC2
01455 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15     ADC_EXTERNALTRIGINJEC_EXT_IT15
01456 #define ADC_INJECTED_SOFTWARE_START            ADC_JSWSTART
01457 /**
01458   * @}
01459   */
01460
01461
01462 /** @defgroup ADCEx_analog_watchdog_mode ADC Extended analog watchdog mode
01463   * @{
01464   */
01465 #define ADC_ANALOGWATCHDOG_NONE                 (0x00000000U)
01466 #define ADC_ANALOGWATCHDOG_SINGLE_REG           ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
01467 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
01468 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
01469 #define ADC_ANALOGWATCHDOG_ALL_REG              ((uint32_t) ADC_CR1_AWDEN)
01470 #define ADC_ANALOGWATCHDOG_ALL_INJEC            ((uint32_t) ADC_CR1_JAWDEN)
01471 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC         ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
01472 /**
01473   * @}
01474   */
01475
01476 /** @defgroup ADC_conversion_group ADC Conversion Group
01477   * @{
01478   */
01479 #define ADC_REGULAR_GROUP             ((uint32_t)(ADC_FLAG_EOC))
01480 #define ADC_INJECTED_GROUP            ((uint32_t)(ADC_FLAG_JEOC))
01481 #define ADC_REGULAR_INJECTED_GROUP    ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
01482 /**
01483   * @}
01484   */
01485
01486 /** @defgroup ADCEx_Event_type ADC Extended Event Type
01487   * @{
01488   */
01489 #define ADC_AWD_EVENT               ((uint32_t)ADC_FLAG_AWD)   /*!< ADC Analog watchdog event */
01490 /**
01491   * @}
01492   */
01493
01494 /** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
01495   * @{
01496   */
01497 #define ADC_IT_EOC           ADC_CR1_EOCIE        /*!< ADC End of Regular Conversion interrupt source */
01498 #define ADC_IT_JEOC          ADC_CR1_JEOCIE       /*!< ADC End of Injected Conversion interrupt source */
01499 #define ADC_IT_AWD           ADC_CR1_AWDIE        /*!< ADC Analog watchdog interrupt source */
01500 /**
01501   * @}
01502   */
01503
01504 /** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
01505   * @{
01506   */
01507 #define ADC_FLAG_AWD           ADC_SR_AWD      /*!< ADC Analog watchdog flag */
01508 #define ADC_FLAG_EOC           ADC_SR_EOC      /*!< ADC End of Regular conversion flag */
01509 #define ADC_FLAG_JEOC          ADC_SR_JEOC     /*!< ADC End of Injected conversion flag */
01510 #define ADC_FLAG_JSTRT         ADC_SR_JSTRT    /*!< ADC Injected group start flag */
01511 #define ADC_FLAG_STRT          ADC_SR_STRT     /*!< ADC Regular group start flag */
01512
01513 /**
01514   * @}
01515   */
01516 #endif /* STM32F373xC || STM32F378xx */
01517
01518 /**
01519   * @}
01520   */
01521
01522
01523
01524 /* Private constants ---------------------------------------------------------*/
01525
01526 /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
01527   * @{
01528   */
01529
01530 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
01531     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
01532     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
01533     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01534
01535
01536 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
01537   * @{
01538   */
01539 #if defined(STM32F303xE) || defined(STM32F398xx) || \
01540     defined(STM32F303xC) || defined(STM32F358xx)
01541 /* List of external triggers for common groups ADC1&ADC2 and/or ADC3&ADC4:    */
01542 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
01543
01544 /* External triggers of regular group for ADC1 & ADC2 */
01545 #define ADC1_2_EXTERNALTRIG_T1_CC1           (0x00000000U)
01546 #define ADC1_2_EXTERNALTRIG_T1_CC2           ((uint32_t)ADC_CFGR_EXTSEL_0)
01547 #define ADC1_2_EXTERNALTRIG_T1_CC3           ((uint32_t)ADC_CFGR_EXTSEL_1)
01548 #define ADC1_2_EXTERNALTRIG_T2_CC2           ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
01549 #define ADC1_2_EXTERNALTRIG_T3_TRGO          ((uint32_t)ADC_CFGR_EXTSEL_2)
01550 #define ADC1_2_EXTERNALTRIG_T4_CC4           ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
01551 #define ADC1_2_EXTERNALTRIG_EXT_IT11         ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
01552 #define ADC1_2_EXTERNALTRIG_T8_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
01553 #define ADC1_2_EXTERNALTRIG_T8_TRGO2         ((uint32_t) ADC_CFGR_EXTSEL_3)
01554 #define ADC1_2_EXTERNALTRIG_T1_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
01555 #define ADC1_2_EXTERNALTRIG_T1_TRGO2         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
01556 #define ADC1_2_EXTERNALTRIG_T2_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
01557 #define ADC1_2_EXTERNALTRIG_T4_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
01558 #define ADC1_2_EXTERNALTRIG_T6_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
01559 #define ADC1_2_EXTERNALTRIG_T15_TRGO         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
01560 #define ADC1_2_EXTERNALTRIG_T3_CC4           ((uint32_t)ADC_CFGR_EXTSEL)
01561
01562 /* External triggers of regular group for ADC3 & ADC4 */
01563 #define ADC3_4_EXTERNALTRIG_T3_CC1           (0x00000000U)
01564 #define ADC3_4_EXTERNALTRIG_T2_CC3           ((uint32_t)ADC_CFGR_EXTSEL_0)
01565 #define ADC3_4_EXTERNALTRIG_T1_CC3           ((uint32_t)ADC_CFGR_EXTSEL_1)
01566 #define ADC3_4_EXTERNALTRIG_T8_CC1           ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
01567 #define ADC3_4_EXTERNALTRIG_T8_TRGO          ((uint32_t)ADC_CFGR_EXTSEL_2)
01568 #define ADC3_4_EXTERNALTRIG_EXT_IT2          ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
01569 #define ADC3_4_EXTERNALTRIG_T4_CC1           ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
01570 #define ADC3_4_EXTERNALTRIG_T2_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
01571 #define ADC3_4_EXTERNALTRIG_T8_TRGO2         ((uint32_t)ADC_CFGR_EXTSEL_3)
01572 #define ADC3_4_EXTERNALTRIG_T1_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
01573 #define ADC3_4_EXTERNALTRIG_T1_TRGO2         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
01574 #define ADC3_4_EXTERNALTRIG_T3_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
01575 #define ADC3_4_EXTERNALTRIG_T4_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
01576 #define ADC3_4_EXTERNALTRIG_T7_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
01577 #define ADC3_4_EXTERNALTRIG_T15_TRGO         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
01578 #define ADC3_4_EXTERNALTRIG_T2_CC1           ((uint32_t)ADC_CFGR_EXTSEL)
01579 #endif /* STM32F303xE || STM32F398xx || */
01580        /* STM32F303xC || STM32F358xx    */
01581
01582 #if defined(STM32F302xE) || \
01583     defined(STM32F302xC)
01584 /* List of external triggers of common group ADC1&ADC2:                       */
01585 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
01586 #define ADC1_2_EXTERNALTRIG_T1_CC1           (0x00000000U)
01587 #define ADC1_2_EXTERNALTRIG_T1_CC2           ((uint32_t)ADC_CFGR_EXTSEL_0)
01588 #define ADC1_2_EXTERNALTRIG_T1_CC3           ((uint32_t)ADC_CFGR_EXTSEL_1)
01589 #define ADC1_2_EXTERNALTRIG_T1_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
01590 #define ADC1_2_EXTERNALTRIG_T1_TRGO2         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
01591 #define ADC1_2_EXTERNALTRIG_T2_CC2           ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
01592 #define ADC1_2_EXTERNALTRIG_T2_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
01593 #define ADC1_2_EXTERNALTRIG_T3_CC4           ((uint32_t)ADC_CFGR_EXTSEL)
01594 #define ADC1_2_EXTERNALTRIG_T3_TRGO          ((uint32_t)ADC_CFGR_EXTSEL_2)
01595 #define ADC1_2_EXTERNALTRIG_T4_CC4           ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
01596 #define ADC1_2_EXTERNALTRIG_T4_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
01597 #define ADC1_2_EXTERNALTRIG_T6_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
01598 #define ADC1_2_EXTERNALTRIG_T15_TRGO         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
01599 #define ADC1_2_EXTERNALTRIG_EXT_IT11         ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
01600 #endif /* STM32F302xE || */
01601        /* STM32F302xC    */
01602
01603 #if defined(STM32F303x8) || defined(STM32F328xx)
01604 /* List of external triggers of common group ADC1&ADC2:                       */
01605 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
01606 #define ADC1_2_EXTERNALTRIG_T1_CC1           (0x00000000U)
01607 #define ADC1_2_EXTERNALTRIG_T1_CC2           ((uint32_t)ADC_CFGR_EXTSEL_0)
01608 #define ADC1_2_EXTERNALTRIG_T1_CC3           ((uint32_t)ADC_CFGR_EXTSEL_1)
01609 #define ADC1_2_EXTERNALTRIG_T2_CC2           ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
01610 #define ADC1_2_EXTERNALTRIG_T3_TRGO          ((uint32_t)ADC_CFGR_EXTSEL_2)
01611 #define ADC1_2_EXTERNALTRIG_T4_CC4           ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
01612 #define ADC1_2_EXTERNALTRIG_EXT_IT11         ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
01613 #define ADC1_2_EXTERNALTRIG_T8_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
01614 #define ADC1_2_EXTERNALTRIG_T8_TRGO2         ((uint32_t) ADC_CFGR_EXTSEL_3)
01615 #define ADC1_2_EXTERNALTRIG_T1_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
01616 #define ADC1_2_EXTERNALTRIG_T1_TRGO2         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
01617 #define ADC1_2_EXTERNALTRIG_T2_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
01618 #define ADC1_2_EXTERNALTRIG_T4_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
01619 #define ADC1_2_EXTERNALTRIG_T6_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
01620 #define ADC1_2_EXTERNALTRIG_T15_TRGO         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
01621 #define ADC1_2_EXTERNALTRIG_T3_CC4           ((uint32_t)ADC_CFGR_EXTSEL)
01622 #endif /* STM32F303x8 || STM32F328xx */
01623
01624 #if defined(STM32F334x8)
01625 /* List of external triggers of common group ADC1&ADC2:                       */
01626 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
01627 #define ADC1_2_EXTERNALTRIG_T1_CC1           (0x00000000U)
01628 #define ADC1_2_EXTERNALTRIG_T1_CC2           ((uint32_t)ADC_CFGR_EXTSEL_0)
01629 #define ADC1_2_EXTERNALTRIG_T1_CC3           ((uint32_t)ADC_CFGR_EXTSEL_1)
01630 #define ADC1_2_EXTERNALTRIG_T2_CC2           ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
01631 #define ADC1_2_EXTERNALTRIG_T3_TRGO          ((uint32_t)ADC_CFGR_EXTSEL_2)
01632 #define ADC1_2_EXTERNALTRIG_EXT_IT11         ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
01633 #define ADC1_2_EXTERNALTRIG_HRTIM_TRG1       ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
01634 #define ADC1_2_EXTERNALTRIG_HRTIM_TRG3       ((uint32_t) ADC_CFGR_EXTSEL_3)
01635 #define ADC1_2_EXTERNALTRIG_T1_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
01636 #define ADC1_2_EXTERNALTRIG_T1_TRGO2         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
01637 #define ADC1_2_EXTERNALTRIG_T2_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
01638 #define ADC1_2_EXTERNALTRIG_T6_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
01639 #define ADC1_2_EXTERNALTRIG_T15_TRGO         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
01640 #define ADC1_2_EXTERNALTRIG_T3_CC4           ((uint32_t)ADC_CFGR_EXTSEL)
01641 #endif /* STM32F334x8 */
01642
01643 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01644 /* List of external triggers of regular group for ADC1:                       */
01645 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
01646 #define ADC1_EXTERNALTRIG_T1_CC1           (0x00000000U)
01647 #define ADC1_EXTERNALTRIG_T1_CC2           ((uint32_t)ADC_CFGR_EXTSEL_0)
01648 #define ADC1_EXTERNALTRIG_T1_CC3           ((uint32_t)ADC_CFGR_EXTSEL_1)
01649 #define ADC1_EXTERNALTRIG_EXT_IT11         ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
01650 #define ADC1_EXTERNALTRIG_T1_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
01651 #define ADC1_EXTERNALTRIG_T1_TRGO2         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
01652 #define ADC1_EXTERNALTRIG_T2_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
01653 #define ADC1_EXTERNALTRIG_T6_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
01654 #define ADC1_EXTERNALTRIG_T15_TRGO         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
01655 #define ADC_SOFTWARE_START                 (0x00000001U)
01656 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
01657 /**
01658   * @}
01659   */
01660
01661
01662 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
01663   * @{
01664   */
01665 #if defined(STM32F303xE) || defined(STM32F398xx) || \
01666     defined(STM32F303xC) || defined(STM32F358xx)
01667 /* List of external triggers sorted of groups ADC1&ADC2 and/or ADC3&ADC4:     */
01668 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
01669
01670 /* External triggers for injected groups of ADC1 & ADC2 */
01671 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO    (0x00000000U)
01672 #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4     ((uint32_t)ADC_JSQR_JEXTSEL_0)
01673 #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO    ((uint32_t)ADC_JSQR_JEXTSEL_1)
01674 #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1     ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
01675 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4     ((uint32_t)ADC_JSQR_JEXTSEL_2)
01676 #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
01677 #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15   ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
01678 #define ADC1_2_EXTERNALTRIGINJEC_T8_CC4     ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
01679 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2   ((uint32_t)ADC_JSQR_JEXTSEL_3)
01680 #define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
01681 #define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2   ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
01682 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC3     ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
01683 #define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
01684 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC1     ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
01685 #define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
01686 #define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO   ((uint32_t)ADC_JSQR_JEXTSEL)
01687
01688 /* External triggers for injected groups of ADC3 & ADC4 */
01689 /* Note: External triggers JEXT2 and JEXT5 are the same (TIM4_CC3 event).     */
01690 /*       JEXT2 is the main trigger, JEXT5 could be redirected to another      */
01691 /*       in future devices.                                                   */
01692 /*       However, this channel is implemented with a SW offset of 0x10000 for */
01693 /*       differentiation between similar triggers of common groups ADC1&ADC2, */
01694 /*       ADC3&ADC4 (Differentiation processed into macro                      */
01695 /*       ADC_JSQR_JEXTSEL_SET)                                                */
01696 #define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO    (0x00000000U)
01697 #define ADC3_4_EXTERNALTRIGINJEC_T1_CC4     ((uint32_t)ADC_JSQR_JEXTSEL_0)
01698 #define ADC3_4_EXTERNALTRIGINJEC_T4_CC3     ((uint32_t)ADC_JSQR_JEXTSEL_1 | 0x10000U)
01699 #define ADC3_4_EXTERNALTRIGINJEC_T8_CC2     ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
01700 #define ADC3_4_EXTERNALTRIGINJEC_T8_CC4     ((uint32_t)ADC_JSQR_JEXTSEL_2)
01701
01702 #if defined(STM32F303xE) || defined(STM32F398xx)
01703 #define ADC3_4_EXTERNALTRIGINJEC_T20_TRGO   ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
01704 #endif /* STM32F303xE || STM32F398xx */
01705
01706 #define ADC3_4_EXTERNALTRIGINJEC_T4_CC4     ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
01707 #define ADC3_4_EXTERNALTRIGINJEC_T4_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
01708 #define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO2   ((uint32_t)ADC_JSQR_JEXTSEL_3)
01709 #define ADC3_4_EXTERNALTRIGINJEC_T8_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
01710 #define ADC3_4_EXTERNALTRIGINJEC_T8_TRGO2   ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
01711 #define ADC3_4_EXTERNALTRIGINJEC_T1_CC3     ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
01712 #define ADC3_4_EXTERNALTRIGINJEC_T3_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
01713 #define ADC3_4_EXTERNALTRIGINJEC_T2_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
01714 #define ADC3_4_EXTERNALTRIGINJEC_T7_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
01715 #define ADC3_4_EXTERNALTRIGINJEC_T15_TRGO   ((uint32_t)ADC_JSQR_JEXTSEL)
01716 #endif /* STM32F303xE || STM32F398xx || */
01717        /* STM32F303xC || STM32F358xx    */
01718
01719 #if defined(STM32F302xE) || \
01720     defined(STM32F302xC)
01721 /* List of external triggers of group ADC1&ADC2:                              */
01722 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
01723 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO    (0x00000000U)
01724 #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4     ((uint32_t)ADC_JSQR_JEXTSEL_0)
01725 #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO    ((uint32_t)ADC_JSQR_JEXTSEL_1)
01726 #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1     ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
01727 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4     ((uint32_t)ADC_JSQR_JEXTSEL_2)
01728 #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
01729 #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15   ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
01730 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2   ((uint32_t)ADC_JSQR_JEXTSEL_3)
01731 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC3     ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
01732 #define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
01733 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC1     ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
01734 #define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
01735 #define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO   ((uint32_t)ADC_JSQR_JEXTSEL)
01736 #endif /* STM32F302xE || */
01737        /* STM32F302xC    */
01738
01739 #if defined(STM32F303x8) || defined(STM32F328xx)
01740 /* List of external triggers of group ADC1&ADC2:                              */
01741 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
01742 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO    (0x00000000U)
01743 #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4     ((uint32_t)ADC_JSQR_JEXTSEL_0)
01744 #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO    ((uint32_t)ADC_JSQR_JEXTSEL_1)
01745 #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1     ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
01746 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4     ((uint32_t)ADC_JSQR_JEXTSEL_2)
01747 #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
01748 #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15   ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
01749 #define ADC1_2_EXTERNALTRIGINJEC_T8_CC4     ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
01750 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2   ((uint32_t)ADC_JSQR_JEXTSEL_3)
01751 #define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
01752 #define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2   ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
01753 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC3     ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
01754 #define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
01755 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC1     ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
01756 #define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
01757 #define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO   ((uint32_t)ADC_JSQR_JEXTSEL)
01758 #endif /* STM32F303x8 || STM32F328xx */
01759
01760 #if defined(STM32F334x8)
01761 /* List of external triggers of group ADC1&ADC2:                              */
01762 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
01763 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO     (0x00000000U)
01764 #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4      ((uint32_t)ADC_JSQR_JEXTSEL_0)
01765 #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO     ((uint32_t)ADC_JSQR_JEXTSEL_1)
01766 #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1      ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
01767 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4      ((uint32_t)ADC_JSQR_JEXTSEL_2)
01768 #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15    ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
01769 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2    ((uint32_t)ADC_JSQR_JEXTSEL_3)
01770 #define ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG2  ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
01771 #define ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4  ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
01772 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC3      ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
01773 #define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO     ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
01774 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC1      ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
01775 #define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO     ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
01776 #define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO    ((uint32_t)ADC_JSQR_JEXTSEL)
01777 #endif /* STM32F334x8 */
01778
01779 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01780 /* List of external triggers of injected group for ADC1:                      */
01781 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
01782 #define ADC1_EXTERNALTRIGINJEC_T1_TRGO    (0x00000000U)
01783 #define ADC1_EXTERNALTRIGINJEC_T1_CC4     ((uint32_t)ADC_JSQR_JEXTSEL_0)
01784 #define ADC1_EXTERNALTRIGINJEC_T2_TRGO    ((uint32_t)ADC_JSQR_JEXTSEL_1)
01785 #define ADC1_EXTERNALTRIGINJEC_T2_CC1     ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
01786 #define ADC1_EXTERNALTRIGINJEC_EXT_IT15   ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
01787 #define ADC1_EXTERNALTRIGINJEC_T1_TRGO2   ((uint32_t)ADC_JSQR_JEXTSEL_3)
01788 #define ADC1_EXTERNALTRIGINJEC_T6_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
01789 #define ADC1_EXTERNALTRIGINJEC_T15_TRGO   ((uint32_t)ADC_JSQR_JEXTSEL)
01790 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
01791 /**
01792   * @}
01793   */
01794
01795 #define ADC_FLAG_ALL    (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS |  \
01796                          ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
01797                          ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF)
01798
01799 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
01800 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS  | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \
01801                                ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \
01802                                ADC_FLAG_JQOVF)
01803
01804 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
01805        /* STM32F302xC || STM32F303xC || STM32F358xx || */
01806        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
01807        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
01808
01809
01810 #if defined(STM32F373xC) || defined(STM32F378xx)
01811
01812 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
01813   * @{
01814   */
01815 /* List of external triggers of regular group for ADC1:                       */
01816 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
01817
01818 /* External triggers of regular group for ADC1 */
01819 #define ADC_EXTERNALTRIG_T19_TRGO          (0x00000000U)
01820 #define ADC_EXTERNALTRIG_T19_CC3           ((uint32_t)ADC_CR2_EXTSEL_0)
01821 #define ADC_EXTERNALTRIG_T19_CC4           ((uint32_t)ADC_CR2_EXTSEL_1)
01822 #define ADC_EXTERNALTRIG_T2_CC2            ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
01823 #define ADC_EXTERNALTRIG_T3_TRGO           ((uint32_t)ADC_CR2_EXTSEL_2)
01824 #define ADC_EXTERNALTRIG_T4_CC4            ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
01825 #define ADC_EXTERNALTRIG_EXT_IT11          ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
01826 #define ADC_SWSTART                        ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
01827 /**
01828   * @}
01829   */
01830
01831 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
01832   * @{
01833   */
01834 /* List of external triggers of injected group for ADC1:                      */
01835 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
01836
01837 /* External triggers of injected group for ADC1 */
01838 #define ADC_EXTERNALTRIGINJEC_T19_CC1      ( 0x00000000U)
01839 #define ADC_EXTERNALTRIGINJEC_T19_CC2      ((uint32_t) ADC_CR2_JEXTSEL_0)
01840 #define ADC_EXTERNALTRIGINJEC_T2_TRGO      ((uint32_t) ADC_CR2_JEXTSEL_1)
01841 #define ADC_EXTERNALTRIGINJEC_T2_CC1       ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
01842 #define ADC_EXTERNALTRIGINJEC_T3_CC4       ((uint32_t) ADC_CR2_JEXTSEL_2)
01843 #define ADC_EXTERNALTRIGINJEC_T4_TRGO      ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
01844 #define ADC_EXTERNALTRIGINJEC_EXT_IT15     ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
01845 #define ADC_JSWSTART                       ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
01846 /**
01847   * @}
01848   */
01849
01850 /** @defgroup ADCEx_sampling_times_all_channels ADC Extended Sampling Times All Channels
01851   * @{
01852   */
01853 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2                                          \
01854      (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 |     \
01855       ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 |     \
01856       ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
01857 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2                                          \
01858      (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \
01859       ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )
01860
01861 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1                                          \
01862      (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 |     \
01863       ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 |     \
01864       ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
01865 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1                                          \
01866      (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \
01867       ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )
01868
01869 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0                                          \
01870      (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 |     \
01871       ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 |     \
01872       ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
01873 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0                                          \
01874      (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
01875       ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
01876
01877 #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS    (0x00000000U)
01878 #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS   (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
01879 #define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
01880 #define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
01881 #define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
01882 #define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
01883 #define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
01884 #define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
01885
01886 #define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS    (0x00000000U)
01887 #define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS   (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
01888 #define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
01889 #define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
01890 #define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
01891 #define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
01892 #define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
01893 #define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
01894
01895 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
01896 #define ADC_FLAG_POSTCONV_ALL   (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )
01897 /**
01898   * @}
01899   */
01900
01901 #endif /* STM32F373xC || STM32F378xx */
01902
01903 /**
01904   * @}
01905   */
01906
01907 /* Exported macro ------------------------------------------------------------*/
01908
01909 /** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros
01910   * @{
01911   */
01912 /* Macro for internal HAL driver usage, and possibly can be used into code of */
01913 /* final user.                                                                */
01914
01915 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
01916     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
01917     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
01918     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01919
01920 /**
01921   * @brief Enable the ADC peripheral
01922   * @param __HANDLE__ ADC handle
01923   * @note ADC enable requires a delay for ADC stabilization time
01924   *       (refer to device datasheet, parameter tSTAB)
01925   * @note On STM32F3 devices, some hardware constraints must be strictly
01926   *       respected before using this macro:
01927   *        - ADC internal voltage regulator must be preliminarily enabled.
01928   *          This is performed by function HAL_ADC_Init().
01929   *        - ADC state requirements: ADC must be disabled, no conversion on
01930   *          going, no calibration on going.
01931   *          These checks are performed by functions HAL_ADC_start_xxx().
01932   * @retval None
01933   */
01934 #define __HAL_ADC_ENABLE(__HANDLE__)                                           \
01935  (SET_BIT((__HANDLE__)->Instance->CR, ADC_CR_ADEN))
01936
01937 /**
01938   * @brief Disable the ADC peripheral
01939   * @param __HANDLE__ ADC handle
01940   * @note On STM32F3 devices, some hardware constraints must be strictly
01941   *       respected before using this macro:
01942   *        - ADC state requirements: ADC must be enabled, no conversion on
01943   *          going.
01944   *          These checks are performed by functions HAL_ADC_start_xxx().
01945   * @retval None
01946   */
01947 #define __HAL_ADC_DISABLE(__HANDLE__)                                          \
01948   do{                                                                          \
01949       SET_BIT((__HANDLE__)->Instance->CR, ADC_CR_ADDIS);                       \
01950       __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY));     \
01951   } while(0U)
01952
01953 /**
01954   * @brief Enable the ADC end of conversion interrupt.
01955   * @param __HANDLE__ ADC handle
01956   * @param __INTERRUPT__ ADC Interrupt
01957   *          This parameter can be any combination of the following values:
01958   *            @arg ADC_IT_RDY:   ADC Ready (ADRDY) interrupt source
01959   *            @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
01960   *            @arg ADC_IT_EOC:   ADC End of Regular Conversion interrupt source
01961   *            @arg ADC_IT_EOS:   ADC End of Regular sequence of Conversions interrupt source
01962   *            @arg ADC_IT_OVR:   ADC overrun interrupt source
01963   *            @arg ADC_IT_JEOC:  ADC End of Injected Conversion interrupt source
01964   *            @arg ADC_IT_JEOS:  ADC End of Injected sequence of Conversions interrupt source
01965   *            @arg ADC_IT_AWD1:  ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices)
01966   *            @arg ADC_IT_AWD2:  ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices)
01967   *            @arg ADC_IT_AWD3:  ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices)
01968   *            @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
01969   * @retval None
01970   */
01971 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
01972   (SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)))
01973
01974 /**
01975   * @brief Disable the ADC end of conversion interrupt.
01976   * @param __HANDLE__ ADC handle
01977   * @param __INTERRUPT__ ADC Interrupt
01978   *          This parameter can be any combination of the following values:
01979   *            @arg ADC_IT_RDY:   ADC Ready (ADRDY) interrupt source
01980   *            @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
01981   *            @arg ADC_IT_EOC:   ADC End of Regular Conversion interrupt source
01982   *            @arg ADC_IT_EOS:   ADC End of Regular sequence of Conversions interrupt source
01983   *            @arg ADC_IT_OVR:   ADC overrun interrupt source
01984   *            @arg ADC_IT_JEOC:  ADC End of Injected Conversion interrupt source
01985   *            @arg ADC_IT_JEOS:  ADC End of Injected sequence of Conversions interrupt source
01986   *            @arg ADC_IT_AWD1:  ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices)
01987   *            @arg ADC_IT_AWD2:  ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices)
01988   *            @arg ADC_IT_AWD3:  ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices)
01989   *            @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
01990   * @retval None
01991   */
01992 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
01993   (CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)))
01994
01995 /** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
01996   * @param __HANDLE__ ADC handle
01997   * @param __INTERRUPT__ ADC interrupt source to check
01998   *          This parameter can be any combination of the following values:
01999   *            @arg ADC_IT_RDY:   ADC Ready (ADRDY) interrupt source
02000   *            @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
02001   *            @arg ADC_IT_EOC:   ADC End of Regular Conversion interrupt source
02002   *            @arg ADC_IT_EOS:   ADC End of Regular sequence of Conversions interrupt source
02003   *            @arg ADC_IT_OVR:   ADC overrun interrupt source
02004   *            @arg ADC_IT_JEOC:  ADC End of Injected Conversion interrupt source
02005   *            @arg ADC_IT_JEOS:  ADC End of Injected sequence of Conversions interrupt source
02006   *            @arg ADC_IT_AWD1:  ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices)
02007   *            @arg ADC_IT_AWD2:  ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices)
02008   *            @arg ADC_IT_AWD3:  ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices)
02009   *            @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
02010   * @retval State of interruption (SET or RESET)
02011   */
02012 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
02013   (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
02014
02015 /**
02016   * @brief Get the selected ADC's flag status.
02017   * @param __HANDLE__ ADC handle
02018   * @param __FLAG__ ADC flag
02019   *          This parameter can be any combination of the following values:
02020   *            @arg ADC_FLAG_RDY:   ADC Ready (ADRDY) flag
02021   *            @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
02022   *            @arg ADC_FLAG_EOC:   ADC End of Regular Conversion flag
02023   *            @arg ADC_FLAG_EOS:   ADC End of Regular sequence of Conversions flag
02024   *            @arg ADC_FLAG_OVR:   ADC overrun flag
02025   *            @arg ADC_FLAG_JEOC:  ADC End of Injected Conversion flag
02026   *            @arg ADC_FLAG_JEOS:  ADC End of Injected sequence of Conversions flag
02027   *            @arg ADC_FLAG_AWD1:  ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices)
02028   *            @arg ADC_FLAG_AWD2:  ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices)
02029   *            @arg ADC_FLAG_AWD3:  ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices)
02030   *            @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag
02031   * @retval None
02032   */
02033 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
02034   ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
02035
02036 /**
02037   * @brief Clear the ADC's pending flags
02038   * @param __HANDLE__ ADC handle
02039   * @param __FLAG__ ADC flag
02040   *          This parameter can be any combination of the following values:
02041   *            @arg ADC_FLAG_RDY:   ADC Ready (ADRDY) flag
02042   *            @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
02043   *            @arg ADC_FLAG_EOC:   ADC End of Regular Conversion flag
02044   *            @arg ADC_FLAG_EOS:   ADC End of Regular sequence of Conversions flag
02045   *            @arg ADC_FLAG_OVR:   ADC overrun flag
02046   *            @arg ADC_FLAG_JEOC:  ADC End of Injected Conversion flag
02047   *            @arg ADC_FLAG_JEOS:  ADC End of Injected sequence of Conversions flag
02048   *            @arg ADC_FLAG_AWD1:  ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices)
02049   *            @arg ADC_FLAG_AWD2:  ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices)
02050   *            @arg ADC_FLAG_AWD3:  ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices)
02051   *            @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag
02052   * @retval None
02053   */
02054 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of  */
02055 /*       register ISR).                                                       */
02056 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \
02057   (WRITE_REG((__HANDLE__)->Instance->ISR, (__FLAG__)))
02058
02059 /** @brief  Reset ADC handle state
02060   * @param  __HANDLE__ ADC handle
02061   * @retval None
02062   */
02063 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
02064   ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
02065 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02066        /* STM32F302xC || STM32F303xC || STM32F358xx || */
02067        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02068        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
02069
02070
02071 #if defined(STM32F373xC) || defined(STM32F378xx)
02072
02073 /**
02074   * @brief Enable the ADC peripheral
02075   * @note ADC enable requires a delay for ADC stabilization time
02076   *       (refer to device datasheet, parameter tSTAB)
02077   * @note On STM32F37x devices, if ADC is already enabled this macro trigs
02078   *       a conversion SW start on regular group.
02079   * @param __HANDLE__ ADC handle
02080   * @retval None
02081   */
02082 #define __HAL_ADC_ENABLE(__HANDLE__)                                           \
02083   (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
02084
02085 /**
02086   * @brief Disable the ADC peripheral
02087   * @param __HANDLE__ ADC handle
02088   * @retval None
02089   */
02090 #define __HAL_ADC_DISABLE(__HANDLE__)                                          \
02091   (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
02092
02093 /** @brief Enable the ADC end of conversion interrupt.
02094   * @param __HANDLE__ ADC handle
02095   * @param __INTERRUPT__ ADC Interrupt
02096   *          This parameter can be any combination of the following values:
02097   *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
02098   *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
02099   *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
02100   * @retval None
02101   */
02102 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
02103   (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
02104
02105 /** @brief Disable the ADC end of conversion interrupt.
02106   * @param __HANDLE__ ADC handle
02107   * @param __INTERRUPT__ ADC Interrupt
02108   *          This parameter can be any combination of the following values:
02109   *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
02110   *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
02111   *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
02112   * @retval None
02113   */
02114 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
02115   (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
02116
02117 /** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
02118   * @param __HANDLE__ ADC handle
02119   * @param __INTERRUPT__ ADC interrupt source to check
02120   *          This parameter can be any combination of the following values:
02121   *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
02122   *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
02123   *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
02124   * @retval State of interruption (SET or RESET)
02125   */
02126 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
02127   (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
02128
02129 /** @brief Get the selected ADC's flag status.
02130   * @param __HANDLE__ ADC handle
02131   * @param __FLAG__ ADC flag
02132   *          This parameter can be any combination of the following values:
02133   *            @arg ADC_FLAG_STRT: ADC Regular group start flag
02134   *            @arg ADC_FLAG_JSTRT: ADC Injected group start flag
02135   *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
02136   *            @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
02137   *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
02138   * @retval None
02139   */
02140 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
02141   ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
02142
02143 /** @brief Clear the ADC's pending flags
02144   * @param __HANDLE__ ADC handle
02145   * @param __FLAG__ ADC flag
02146   *          This parameter can be any combination of the following values:
02147   *            @arg ADC_FLAG_STRT: ADC Regular group start flag
02148   *            @arg ADC_FLAG_JSTRT: ADC Injected group start flag
02149   *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
02150   *            @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
02151   *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
02152   * @retval None
02153   */
02154 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \
02155   (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
02156
02157 /** @brief  Reset ADC handle state
02158   * @param  __HANDLE__ ADC handle
02159   * @retval None
02160   */
02161 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
02162   ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
02163 #endif /* STM32F373xC || STM32F378xx */
02164
02165 /**
02166   * @}
02167   */
02168
02169 /* Private macro ------------------------------------------------------------*/
02170
02171 /** @addtogroup ADCEx_Private_Macro ADCEx Private Macros
02172   * @{
02173   */
02174 /* Macro reserved for internal HAL driver usage, not intended to be used in   */
02175 /* code of final user.                                                        */
02176
02177 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
02178     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
02179     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
02180     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02181
02182 /**
02183   * @brief Verification of hardware constraints before ADC can be enabled
02184   * @param __HANDLE__ ADC handle
02185   * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
02186   */
02187 #define ADC_ENABLING_CONDITIONS(__HANDLE__)                                    \
02188   (( HAL_IS_BIT_CLR((__HANDLE__)->Instance->CR                        ,        \
02189                     (ADC_CR_ADCAL    | ADC_CR_JADSTP | ADC_CR_ADSTP |          \
02190                      ADC_CR_JADSTART |ADC_CR_ADSTART | ADC_CR_ADDIS |          \
02191                      ADC_CR_ADEN                                     ) )       \
02192    ) ? SET : RESET)
02193
02194 /**
02195   * @brief Verification of ADC state: enabled or disabled
02196   * @param __HANDLE__ ADC handle
02197   * @retval SET (ADC enabled) or RESET (ADC disabled)
02198   */
02199 #define ADC_IS_ENABLE(__HANDLE__)                                                      \
02200   (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
02201      ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
02202    ) ? SET : RESET)
02203
02204 /**
02205   * @brief Test if conversion trigger of regular group is software start
02206   *        or external trigger.
02207   * @param __HANDLE__ ADC handle
02208   * @retval SET (software start) or RESET (external trigger)
02209   */
02210 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
02211   (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
02212
02213 /**
02214   * @brief Test if conversion trigger of injected group is software start
02215   *        or external trigger.
02216   * @param __HANDLE__ ADC handle
02217   * @retval SET (software start) or RESET (external trigger)
02218   */
02219 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
02220   (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
02221
02222 /**
02223   * @brief Check if no conversion on going on regular and/or injected groups
02224   * @param __HANDLE__ ADC handle
02225   * @retval SET (conversion is on going) or RESET (no conversion is on going)
02226   */
02227 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__)                     \
02228   (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET  \
02229    ) ? RESET : SET)
02230
02231 /**
02232   * @brief Check if no conversion on going on regular group
02233   * @param __HANDLE__ ADC handle
02234   * @retval SET (conversion is on going) or RESET (no conversion is on going)
02235   */
02236 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)                          \
02237   (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET                  \
02238    ) ? RESET : SET)
02239
02240 /**
02241   * @brief Check if no conversion on going on injected group
02242   * @param __HANDLE__ ADC handle
02243   * @retval SET (conversion is on going) or RESET (no conversion is on going)
02244   */
02245 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__)                         \
02246   (( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET                 \
02247    ) ? RESET : SET)
02248
02249 /**
02250   * @brief Returns resolution bits in CFGR1 register: RES[1:0].
02251   *        Returned value is among parameters to @ref ADCEx_Resolution.
02252   * @param __HANDLE__ ADC handle
02253   * @retval None
02254   */
02255 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
02256
02257 /**
02258   * @brief Simultaneously clears and sets specific bits of the handle State
02259   * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
02260   *        the first parameter is the ADC handle State, the second parameter is the
02261   *        bit field to clear, the third and last parameter is the bit field to set.
02262   * @retval None
02263   */
02264 #define ADC_STATE_CLR_SET MODIFY_REG
02265
02266 /**
02267   * @brief Clear ADC error code (set it to error code: "no error")
02268   * @param __HANDLE__ ADC handle
02269   * @retval None
02270   */
02271 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
02272
02273 /**
02274   * @brief Set the ADC's sample time for Channels numbers between 0 and 9.
02275   * @param _SAMPLETIME_ Sample time parameter.
02276   * @param _CHANNELNB_ Channel number.
02277   * @retval None
02278   */
02279 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (_CHANNELNB_)))
02280
02281 /**
02282   * @brief Set the ADC's sample time for Channels numbers between 10 and 18.
02283   * @param _SAMPLETIME_ Sample time parameter.
02284   * @param _CHANNELNB_ Channel number.
02285   * @retval None
02286   */
02287 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U)))
02288
02289 /**
02290   * @brief Set the selected regular Channel rank for rank between 1 and 4.
02291   * @param _CHANNELNB_ Channel number.
02292   * @param _RANKNB_ Rank number.
02293   * @retval None
02294   */
02295 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_)))
02296
02297 /**
02298   * @brief Set the selected regular Channel rank for rank between 5 and 9.
02299   * @param _CHANNELNB_ Channel number.
02300   * @param _RANKNB_ Rank number.
02301   * @retval None
02302   */
02303 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 5U)))
02304
02305 /**
02306   * @brief Set the selected regular Channel rank for rank between 10 and 14.
02307   * @param _CHANNELNB_ Channel number.
02308   * @param _RANKNB_ Rank number.
02309   * @retval None
02310   */
02311 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 10U)))
02312
02313 /**
02314   * @brief Set the selected regular Channel rank for rank between 15 and 16.
02315   * @param _CHANNELNB_ Channel number.
02316   * @param _RANKNB_ Rank number.
02317   * @retval None
02318   */
02319 #define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 15U)))
02320
02321 /**
02322   * @brief Set the selected injected Channel rank.
02323   * @param _CHANNELNB_ Channel number.
02324   * @param _RANKNB_ Rank number.
02325   * @retval None
02326   */
02327 #define ADC_JSQR_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_) +2U))
02328
02329
02330 /**
02331   * @brief Set the Analog Watchdog 1 channel.
02332   * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1.
02333   * @retval None
02334   */
02335 #define ADC_CFGR_AWD1CH_SHIFT(_CHANNEL_) ((_CHANNEL_) << 26U)
02336
02337 /**
02338   * @brief Configure the channel number into Analog Watchdog 2 or 3.
02339   * @param _CHANNEL_ ADC Channel
02340   * @retval None
02341   */
02342 #define ADC_CFGR_AWD23CR(_CHANNEL_) (1U << (_CHANNEL_))
02343
02344 /**
02345   * @brief Enable automatic conversion of injected group
02346   * @param _INJECT_AUTO_CONVERSION_ Injected automatic conversion.
02347   * @retval None
02348   */
02349 #define ADC_CFGR_INJECT_AUTO_CONVERSION(_INJECT_AUTO_CONVERSION_) ((_INJECT_AUTO_CONVERSION_) << 25U)
02350
02351 /**
02352   * @brief Enable ADC injected context queue
02353   * @param _INJECT_CONTEXT_QUEUE_MODE_ Injected context queue mode.
02354   * @retval None
02355   */
02356 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(_INJECT_CONTEXT_QUEUE_MODE_) ((_INJECT_CONTEXT_QUEUE_MODE_) << 21U)
02357
02358 /**
02359   * @brief Enable ADC discontinuous conversion mode for injected group
02360   * @param _INJECT_DISCONTINUOUS_MODE_ Injected discontinuous mode.
02361   * @retval None
02362   */
02363 #define ADC_CFGR_INJECT_DISCCONTINUOUS(_INJECT_DISCONTINUOUS_MODE_) ((_INJECT_DISCONTINUOUS_MODE_) << 20U)
02364
02365 /**
02366   * @brief Enable ADC discontinuous conversion mode for regular group
02367   * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode.
02368   * @retval None
02369   */
02370 #define ADC_CFGR_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16U)
02371
02372 /**
02373   * @brief Configures the number of discontinuous conversions for regular group.
02374   * @param _NBR_DISCONTINUOUS_CONV_ Number of discontinuous conversions.
02375   * @retval None
02376   */
02377 #define ADC_CFGR_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U)
02378
02379 /**
02380   * @brief Enable the ADC auto delay mode.
02381   * @param _AUTOWAIT_ Auto delay bit enable or disable.
02382   * @retval None
02383   */
02384 #define ADC_CFGR_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14U)
02385
02386 /**
02387   * @brief Enable ADC continuous conversion mode.
02388   * @param _CONTINUOUS_MODE_ Continuous mode.
02389   * @retval None
02390   */
02391 #define ADC_CFGR_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U)
02392
02393 /**
02394   * @brief Enable ADC overrun mode.
02395   * @param _OVERRUN_MODE_ Overrun mode.
02396   * @retval Overrun bit setting to be programmed into CFGR register
02397   */
02398 /* Note: Bit ADC_CFGR_OVRMOD not used directly in constant                    */
02399 /* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00U, to set it    */
02400 /* as the default case to be compliant with other STM32 devices.              */
02401 #define ADC_CFGR_OVERRUN(_OVERRUN_MODE_)                                       \
02402   ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED)                             \
02403     )? (ADC_CFGR_OVRMOD) : (0x00000000U)                                        \
02404   )
02405
02406 /**
02407   * @brief Enable the ADC DMA continuous request.
02408   * @param _DMACONTREQ_MODE_ DMA continuous request mode.
02409   * @retval None
02410   */
02411 #define ADC_CFGR_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1U)
02412
02413 /**
02414   * @brief For devices with 3 ADCs or more: Defines the external trigger source
02415   *        for regular group according to ADC into common group ADC1&ADC2 or
02416   *        ADC3&ADC4 (some triggers with same source have different value to
02417   *        be programmed into ADC EXTSEL bits of CFGR register).
02418   *        Note: No risk of trigger bits value of common group ADC1&ADC2
02419   *        misleading to another trigger at same bits value, because the 3
02420   *        exceptions below are circular and do not point to any other trigger
02421   *        with direct treatment.
02422   *        For devices with 2 ADCs or less: this macro makes no change.
02423   * @param __HANDLE__ ADC handle
02424   * @param __EXT_TRIG_CONV__ External trigger selected for regular group.
02425   * @retval External trigger to be programmed into EXTSEL bits of CFGR register
02426   */
02427 #if defined(STM32F303xE) || defined(STM32F398xx) || \
02428     defined(STM32F303xC) || defined(STM32F358xx)
02429
02430 #if defined(STM32F303xC) || defined(STM32F358xx)
02431 #define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__)                     \
02432  (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
02433   )?                                                                           \
02434    ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T2_TRGO                     \
02435      )?                                                                        \
02436       (ADC3_4_EXTERNALTRIG_T2_TRGO)                                            \
02437       :                                                                        \
02438       ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T3_TRGO                  \
02439         )?                                                                     \
02440          (ADC3_4_EXTERNALTRIG_T3_TRGO)                                         \
02441          :                                                                     \
02442          ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO               \
02443            )?                                                                  \
02444             (ADC3_4_EXTERNALTRIG_T8_TRGO)                                      \
02445             :                                                                  \
02446             (__EXT_TRIG_CONV__)                                                \
02447          )                                                                     \
02448       )                                                                        \
02449    )                                                                           \
02450    :                                                                           \
02451    (__EXT_TRIG_CONV__)                                                         \
02452  )
02453 #endif /* STM32F303xC || STM32F358xx */
02454
02455 #if defined(STM32F303xE) || defined(STM32F398xx)
02456 /* Note: Macro including external triggers specific to device STM303xE: using */
02457 /*       Timer20 with ADC trigger input remap.                                */
02458 #define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__)                     \
02459  (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
02460   )?                                                                           \
02461    ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T2_TRGO                     \
02462      )?                                                                        \
02463       (ADC3_4_EXTERNALTRIG_T2_TRGO)                                            \
02464       :                                                                        \
02465       ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T3_TRGO                  \
02466         )?                                                                     \
02467          (ADC3_4_EXTERNALTRIG_T3_TRGO)                                         \
02468          :                                                                     \
02469          ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO               \
02470            )?                                                                  \
02471             (ADC3_4_EXTERNALTRIG_T8_TRGO)                                      \
02472             :                                                                  \
02473             ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_CC1            \
02474               )?                                                               \
02475                (ADC3_4_EXTERNALTRIG_T2_CC1)                                    \
02476                :                                                               \
02477                 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_TRGO       \
02478                   )?                                                           \
02479                    (ADC3_4_EXTERNALTRIG_EXT_IT2)                               \
02480                    :                                                           \
02481                     ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_TRGO2  \
02482                       )?                                                       \
02483                        (ADC3_4_EXTERNALTRIG_T4_CC1)                            \
02484                        :                                                       \
02485                        (__EXT_TRIG_CONV__)                                     \
02486                   )                                                            \
02487                )                                                               \
02488             )                                                                  \
02489          )                                                                     \
02490       )                                                                        \
02491    )                                                                           \
02492    :                                                                           \
02493    (__EXT_TRIG_CONV__ & (~ADC_EXTERNALTRIGCONV_T20_MASK))                      \
02494  )
02495 #endif /* STM32F303xE || STM32F398xx */
02496 #else
02497 #define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__)                     \
02498    (__EXT_TRIG_CONV__)
02499 #endif /* STM32F303xE || STM32F398xx || */
02500        /* STM32F303xC || STM32F358xx    */
02501
02502 /**
02503   * @brief For devices with 3 ADCs or more: Defines the external trigger source
02504   *        for injected group according to ADC into common group ADC1&ADC2 or
02505   *        ADC3&ADC4 (some triggers with same source have different value to
02506   *        be programmed into ADC JEXTSEL bits of JSQR register).
02507   *        Note: No risk of trigger bits value of common group ADC1&ADC2
02508   *        misleading to another trigger at same bits value, because the 3
02509   *        exceptions below are circular and do not point to any other trigger
02510   *        with direct treatment, except trigger
02511   *        ADC_EXTERNALTRIGINJECCONV_T4_CC3 differentiated with SW offset.
02512   *        For devices with 2 ADCs or less: this macro makes no change.
02513   * @param __HANDLE__ ADC handle
02514   * @param __EXT_TRIG_INJECTCONV__ External trigger selected for injected group
02515   * @retval External trigger to be programmed into JEXTSEL bits of JSQR register
02516   */
02517 #if defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F358xx)
02518 #if defined(STM32F303xC) || defined(STM32F358xx)
02519 #define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__)              \
02520  (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
02521   )?                                                                           \
02522    ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO          \
02523      )?                                                                        \
02524       (ADC3_4_EXTERNALTRIGINJEC_T2_TRGO)                                       \
02525       :                                                                        \
02526       ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO       \
02527         )?                                                                     \
02528          (ADC3_4_EXTERNALTRIGINJEC_T4_TRGO)                                    \
02529          :                                                                     \
02530          ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4     \
02531            )?                                                                  \
02532             (ADC3_4_EXTERNALTRIGINJEC_T8_CC4)                                  \
02533             :                                                                  \
02534             ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_CC3  \
02535               )?                                                               \
02536                (ADC3_4_EXTERNALTRIGINJEC_T4_CC3)                               \
02537                :                                                               \
02538                (__EXT_TRIG_INJECTCONV__)                                       \
02539             )                                                                  \
02540          )                                                                     \
02541       )                                                                        \
02542    )                                                                           \
02543    :                                                                           \
02544    (__EXT_TRIG_INJECTCONV__)                                                   \
02545  )
02546 #endif /* STM32F303xC || STM32F358xx */
02547
02548 #if defined(STM32F303xE) || defined(STM32F398xx)
02549 /* Note: Macro including external triggers specific to device STM303xE: using */
02550 /*       Timer20 with ADC trigger input remap.                                */
02551 #define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__)              \
02552  (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
02553   )?                                                                           \
02554    ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO          \
02555      )?                                                                        \
02556       (ADC3_4_EXTERNALTRIGINJEC_T2_TRGO)                                       \
02557       :                                                                        \
02558       ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO       \
02559         )?                                                                     \
02560          (ADC3_4_EXTERNALTRIGINJEC_T4_TRGO)                                    \
02561          :                                                                     \
02562          ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4     \
02563            )?                                                                  \
02564             (ADC3_4_EXTERNALTRIGINJEC_T8_CC4)                                  \
02565             :                                                                  \
02566             ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_CC3  \
02567               )?                                                               \
02568                (ADC3_4_EXTERNALTRIGINJEC_T4_CC3)                               \
02569                :                                                               \
02570                 ( ( (__EXT_TRIG_INJECTCONV__)                                  \
02571                                          == ADC_EXTERNALTRIGINJECCONV_T20_TRGO \
02572                   )?                                                           \
02573                    (ADC3_4_EXTERNALTRIGINJEC_T20_TRGO)                         \
02574                    :                                                           \
02575                     ( ( (__EXT_TRIG_INJECTCONV__)                              \
02576                                        == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2  \
02577                       )?                                                       \
02578                        (ADC3_4_EXTERNALTRIGINJEC_T1_CC3)                       \
02579                        :                                                       \
02580                        (__EXT_TRIG_INJECTCONV__)                               \
02581                   )                                                            \
02582                )                                                               \
02583             )                                                                  \
02584          )                                                                     \
02585       )                                                                        \
02586    )                                                                           \
02587    :                                                                           \
02588    (__EXT_TRIG_INJECTCONV__ & (~ADC_EXTERNALTRIGCONV_T20_MASK))                \
02589  )
02590 #endif /* STM32F303xE || STM32F398xx */
02591 #else
02592 #define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__)              \
02593    (__EXT_TRIG_INJECTCONV__)
02594 #endif /* STM32F303xE || STM32F398xx || */
02595        /* STM32F303xC || STM32F358xx    */
02596
02597 /**
02598   * @brief Configure the channel number into offset OFRx register
02599   * @param _CHANNEL_ ADC Channel
02600   * @retval None
02601   */
02602 #define ADC_OFR_CHANNEL(_CHANNEL_) ((_CHANNEL_) << 26U)
02603
02604 /**
02605   * @brief Configure the channel number into differential mode selection register
02606   * @param _CHANNEL_ ADC Channel
02607   * @retval None
02608   */
02609 #define ADC_DIFSEL_CHANNEL(_CHANNEL_) (1U << (_CHANNEL_))
02610
02611 /**
02612   * @brief Calibration factor in differential mode to be set into calibration register
02613   * @param _Calibration_Factor_ Calibration factor value
02614   * @retval None
02615   */
02616 #define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) ((_Calibration_Factor_) << 16U)
02617
02618 /**
02619   * @brief Calibration factor in differential mode to be retrieved from calibration register
02620   * @param _Calibration_Factor_ Calibration factor value
02621   * @retval None
02622   */
02623 #define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) ((_Calibration_Factor_) >> 16U)
02624
02625 /**
02626   * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
02627   * @param _Threshold_ Threshold value
02628   * @retval None
02629   */
02630 #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U)
02631
02632 /**
02633   * @brief Enable the ADC DMA continuous request for ADC multimode.
02634   * @param _DMAContReq_MODE_ DMA continuous request mode.
02635   * @retval None
02636   */
02637 #define ADC_CCR_MULTI_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 13U)
02638
02639 /**
02640   * @brief Verification of hardware constraints before ADC can be disabled
02641   * @param __HANDLE__ ADC handle
02642   * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
02643   */
02644 #define ADC_DISABLING_CONDITIONS(__HANDLE__)                                   \
02645        (( ( ((__HANDLE__)->Instance->CR) &                                     \
02646             (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN   \
02647         ) ? SET : RESET)
02648
02649
02650 /**
02651   * @brief Shift the offset in function of the selected ADC resolution.
02652   *        Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
02653   *        If resolution 12 bits, no shift.
02654   *        If resolution 10 bits, shift of 2 ranks on the left.
02655   *        If resolution 8 bits, shift of 4 ranks on the left.
02656   *        If resolution 6 bits, shift of 6 ranks on the left.
02657   *        therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
02658   * @param __HANDLE__ ADC handle
02659   * @param _Offset_ Value to be shifted
02660   * @retval None
02661   */
02662 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_)                      \
02663         ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U))
02664
02665 /**
02666   * @brief Shift the AWD1 threshold in function of the selected ADC resolution.
02667   *        Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
02668   *        If resolution 12 bits, no shift.
02669   *        If resolution 10 bits, shift of 2 ranks on the left.
02670   *        If resolution 8 bits, shift of 4 ranks on the left.
02671   *        If resolution 6 bits, shift of 6 ranks on the left.
02672   *        therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
02673   * @param __HANDLE__ ADC handle
02674   * @param _Threshold_ Value to be shifted
02675   * @retval None
02676   */
02677 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_)            \
02678         ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U))
02679
02680 /**
02681   * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
02682   *        Thresholds have to be left-aligned on bit 7.
02683   *        If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded)
02684   *        If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded)
02685   *        If resolution 8 bits, no shift.
02686   *        If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0)
02687   * @param __HANDLE__ ADC handle
02688   * @param _Threshold_ Value to be shifted
02689   * @retval None
02690   */
02691 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_)           \
02692          ( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \
02693             ((_Threshold_) >> (4U- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U))) : \
02694             (_Threshold_) << 2U )
02695
02696 /**
02697   * @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4
02698   * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
02699   * @param __HANDLE__ ADC handle
02700   * @retval Common control register ADC1_2 or ADC3_4
02701   */
02702 #if defined(STM32F303xE) || defined(STM32F398xx) || \
02703     defined(STM32F303xC) || defined(STM32F358xx)
02704 #define ADC_MASTER_INSTANCE(__HANDLE__)                                          \
02705   ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
02706     )? (ADC1) : (ADC3)                                                           \
02707   )
02708 #endif /* STM32F303xE || STM32F398xx || */
02709        /* STM32F303xC || STM32F358xx    */
02710
02711 #if defined(STM32F302xE)                                                ||     \
02712     defined(STM32F302xC)                                                ||     \
02713     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
02714 #define ADC_MASTER_INSTANCE(__HANDLE__)                                        \
02715   (ADC1)
02716 #endif /* STM32F302xE                               || */
02717        /* STM32F302xC                               || */
02718        /* STM32F303x8 || STM32F328xx || STM32F334x8    */
02719
02720 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02721 #define ADC_MASTER_INSTANCE(__HANDLE__)                                        \
02722   (ADC1)
02723 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
02724
02725 /**
02726   * @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4
02727   * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
02728   * @param __HANDLE__ ADC handle
02729   * @retval Common control register ADC1_2 or ADC3_4
02730   */
02731 #if defined(STM32F303xE) || defined(STM32F398xx) || \
02732     defined(STM32F303xC) || defined(STM32F358xx)
02733 #define ADC_COMMON_REGISTER(__HANDLE__)                                          \
02734   ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
02735     )? (ADC1_2_COMMON) : (ADC3_4_COMMON)                                         \
02736   )
02737 #endif /* STM32F303xE || STM32F398xx || */
02738        /* STM32F303xC || STM32F358xx    */
02739
02740 #if defined(STM32F302xE)                                                ||     \
02741     defined(STM32F302xC)                                                ||     \
02742     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
02743 #define ADC_COMMON_REGISTER(__HANDLE__)                                        \
02744   (ADC1_2_COMMON)
02745 #endif /* STM32F302xE                               || */
02746        /* STM32F302xC                               || */
02747        /* STM32F303x8 || STM32F328xx || STM32F334x8    */
02748
02749 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02750 #define ADC_COMMON_REGISTER(__HANDLE__)                                        \
02751   (ADC1_COMMON)
02752 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
02753
02754 /**
02755   * @brief Selection of ADC common register CCR bits MULTI[4:0]corresponding to the selected ADC (applicable for devices with several ADCs)
02756   * @param __HANDLE__ ADC handle
02757   * @retval None
02758   */
02759 #if defined(STM32F303xE) || defined(STM32F398xx) || \
02760     defined(STM32F303xC) || defined(STM32F358xx)
02761 #define ADC_COMMON_CCR_MULTI(__HANDLE__)                                         \
02762   ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
02763     )?                                                                           \
02764      (ADC1_2_COMMON->CCR & ADC12_CCR_MULTI)                                      \
02765      :                                                                           \
02766      (ADC3_4_COMMON->CCR & ADC34_CCR_MULTI)                                      \
02767   )
02768 #endif /* STM32F303xE || STM32F398xx || */
02769        /* STM32F303xC || STM32F358xx    */
02770
02771 #if defined(STM32F302xE)                                                ||    \
02772     defined(STM32F302xC)                                                ||    \
02773     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
02774 #define ADC_COMMON_CCR_MULTI(__HANDLE__)                                      \
02775   (ADC1_2_COMMON->CCR & ADC12_CCR_MULTI)
02776 #endif /* STM32F302xE                               || */
02777        /* STM32F302xC                               || */
02778        /* STM32F303x8 || STM32F328xx || STM32F334x8    */
02779
02780 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02781 #define ADC_COMMON_CCR_MULTI(__HANDLE__)                                      \
02782   (RESET)
02783 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
02784
02785 /**
02786   * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
02787   * @param __HANDLE__ ADC handle
02788   * @retval None
02789   */
02790 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
02791     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
02792     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
02793 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                        \
02794   ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) ||               \
02795    (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance))   )
02796 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02797        /* STM32F302xC || STM32F303xC || STM32F358xx || */
02798        /* STM32F303x8 || STM32F334x8 || STM32F328xx    */
02799
02800 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02801 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                        \
02802   (!RESET)
02803 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
02804
02805 /**
02806   * @brief Verification of condition for ADC group regular start conversion: ADC must be in non-multimode or multimode on group injected only, or multimode with handle of ADC master (applicable for devices with several ADCs)
02807   * @param __HANDLE__ ADC handle.
02808   * @retval None
02809   */
02810 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
02811     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
02812     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
02813 #define ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(__HANDLE__)                    \
02814   ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT)     ||           \
02815    (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_INJECSIMULT) ||           \
02816    (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_ALTERTRIG)   ||           \
02817    (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance))       )
02818 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02819        /* STM32F302xC || STM32F303xC || STM32F358xx || */
02820        /* STM32F303x8 || STM32F334x8 || STM32F328xx    */
02821
02822 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02823 #define ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(__HANDLE__)                    \
02824   (!RESET)
02825 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
02826
02827 /**
02828   * @brief Verification of condition for ADC group injected start conversion: ADC must be in non-multimode or multimode on group regular only, or multimode with handle of ADC master (applicable for devices with several ADCs)
02829   * @param __HANDLE__ ADC handle.
02830   * @retval None
02831   */
02832 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
02833     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
02834     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
02835 #define ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(__HANDLE__)                    \
02836   ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT)   ||             \
02837    (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_REGSIMULT) ||             \
02838    (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_INTERL)    ||             \
02839    (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance))     )
02840 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02841        /* STM32F302xC || STM32F303xC || STM32F358xx || */
02842        /* STM32F303x8 || STM32F334x8 || STM32F328xx    */
02843
02844 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02845 #define ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(__HANDLE__)                    \
02846   (!RESET)
02847 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
02848
02849 /**
02850   * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
02851   * @param __HANDLE__ ADC handle
02852   * @retval None
02853   */
02854 #if defined(STM32F303xE) || defined(STM32F398xx) || \
02855     defined(STM32F303xC) || defined(STM32F358xx)
02856 #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__)                                \
02857   (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)  \
02858    )?                                                                          \
02859     (ADC1->CFGR & ADC_CFGR_JAUTO)                                              \
02860     :                                                                          \
02861     (ADC3->CFGR & ADC_CFGR_JAUTO)                                              \
02862   )
02863 #elif defined(STM32F302xE)                                                || \
02864       defined(STM32F302xC)                                                || \
02865       defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
02866 #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__)                                \
02867   (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)  \
02868    )?                                                                          \
02869     (ADC1->CFGR & ADC_CFGR_JAUTO)                                              \
02870     :                                                                          \
02871     (RESET)                                                                    \
02872   )
02873 #else
02874 #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__)                                \
02875   (RESET)
02876 #endif
02877
02878 /**
02879   * @brief Set handle of the other ADC sharing the same common register ADC1_2 or ADC3_4
02880   * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
02881   * @param __HANDLE__ ADC handle
02882   * @param __HANDLE_OTHER_ADC__ other ADC handle
02883   * @retval None
02884   */
02885 #if defined(STM32F303xE) || defined(STM32F398xx) || \
02886     defined(STM32F303xC) || defined(STM32F358xx)
02887 #define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__)                 \
02888   ( ( ((__HANDLE__)->Instance == ADC1)                                         \
02889     )?                                                                         \
02890      ((__HANDLE_OTHER_ADC__)->Instance = ADC2)                                 \
02891      :                                                                         \
02892      ( ( ((__HANDLE__)->Instance == ADC2)                                      \
02893        )?                                                                      \
02894         ((__HANDLE_OTHER_ADC__)->Instance = ADC1)                              \
02895         :                                                                      \
02896         ( ( ((__HANDLE__)->Instance == ADC3)                                   \
02897           )?                                                                   \
02898            ((__HANDLE_OTHER_ADC__)->Instance = ADC4)                           \
02899            :                                                                   \
02900            ( ( ((__HANDLE__)->Instance == ADC4)                                \
02901              )?                                                                \
02902               ((__HANDLE_OTHER_ADC__)->Instance = ADC3)                        \
02903               :                                                                \
02904               ((__HANDLE_OTHER_ADC__)->Instance = NULL)                        \
02905            )                                                                   \
02906          )                                                                     \
02907      )                                                                         \
02908   )
02909 #endif /* STM32F303xE || STM32F398xx || */
02910        /* STM32F303xC || STM32F358xx    */
02911
02912 #if defined(STM32F302xE)                                                || \
02913     defined(STM32F302xC)                                                || \
02914     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
02915 #define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__)                 \
02916   ( ( ((__HANDLE__)->Instance == ADC1)                                         \
02917     )?                                                                         \
02918      ((__HANDLE_OTHER_ADC__)->Instance = ADC2)                                 \
02919      :                                                                         \
02920      ((__HANDLE_OTHER_ADC__)->Instance = ADC1)                                 \
02921   )
02922 #endif /* STM32F302xE                               || */
02923        /* STM32F302xC                               || */
02924        /* STM32F303x8 || STM32F328xx || STM32F334x8    */
02925
02926 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02927 #define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__)                 \
02928   ((__HANDLE_OTHER_ADC__)->Instance = NULL)
02929 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
02930
02931 /**
02932   * @brief Set handle of the ADC slave associated to the ADC master
02933   * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
02934   * @param __HANDLE_MASTER__ ADC master handle
02935   * @param __HANDLE_SLAVE__ ADC slave handle
02936   * @retval None
02937   */
02938 #if defined(STM32F303xE) || defined(STM32F398xx) || \
02939     defined(STM32F303xC) || defined(STM32F358xx)
02940 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)                   \
02941   ( ( ((__HANDLE_MASTER__)->Instance == ADC1)                                  \
02942     )?                                                                         \
02943      ((__HANDLE_SLAVE__)->Instance = ADC2)                                     \
02944      :                                                                         \
02945      ( ( ((__HANDLE_MASTER__)->Instance == ADC3)                               \
02946        )?                                                                      \
02947         ((__HANDLE_SLAVE__)->Instance = ADC4)                                  \
02948         :                                                                      \
02949         ((__HANDLE_SLAVE__)->Instance = NULL)                                  \
02950      )                                                                         \
02951   )
02952 #endif /* STM32F303xE || STM32F398xx || */
02953        /* STM32F303xC || STM32F358xx    */
02954
02955 #if defined(STM32F302xE)                                                || \
02956     defined(STM32F302xC)                                                || \
02957     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
02958 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)             \
02959   ( ( ((__HANDLE_MASTER__)->Instance == ADC1)                                  \
02960     )?                                                                         \
02961      ((__HANDLE_SLAVE__)->Instance = ADC2)                                     \
02962      :                                                                         \
02963      ( NULL )                                                                  \
02964   )
02965 #endif /* STM32F302xE                               || */
02966        /* STM32F302xC                               || */
02967        /* STM32F303x8 || STM32F328xx || STM32F334x8    */
02968
02969
02970 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
02971                                        ((RESOLUTION) == ADC_RESOLUTION_10B) || \
02972                                        ((RESOLUTION) == ADC_RESOLUTION_8B)  || \
02973                                        ((RESOLUTION) == ADC_RESOLUTION_6B)    )
02974
02975 #define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \
02976                                                 ((RESOLUTION) == ADC_RESOLUTION_6B)   )
02977
02978
02979 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
02980                                   ((ALIGN) == ADC_DATAALIGN_LEFT)    )
02981
02982 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
02983                                      ((SCAN_MODE) == ADC_SCAN_ENABLE)    )
02984
02985 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV)    || \
02986                                              ((EOC_SELECTION) == ADC_EOC_SEQ_CONV)   )
02987
02988 #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED)  || \
02989                              ((OVR) == ADC_OVR_DATA_OVERWRITTEN)  )
02990
02991 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_1)           || \
02992                                  ((CHANNEL) == ADC_CHANNEL_2)           || \
02993                                  ((CHANNEL) == ADC_CHANNEL_3)           || \
02994                                  ((CHANNEL) == ADC_CHANNEL_4)           || \
02995                                  ((CHANNEL) == ADC_CHANNEL_5)           || \
02996                                  ((CHANNEL) == ADC_CHANNEL_6)           || \
02997                                  ((CHANNEL) == ADC_CHANNEL_7)           || \
02998                                  ((CHANNEL) == ADC_CHANNEL_8)           || \
02999                                  ((CHANNEL) == ADC_CHANNEL_9)           || \
03000                                  ((CHANNEL) == ADC_CHANNEL_10)          || \
03001                                  ((CHANNEL) == ADC_CHANNEL_11)          || \
03002                                  ((CHANNEL) == ADC_CHANNEL_12)          || \
03003                                  ((CHANNEL) == ADC_CHANNEL_13)          || \
03004                                  ((CHANNEL) == ADC_CHANNEL_14)          || \
03005                                  ((CHANNEL) == ADC_CHANNEL_15)          || \
03006                                  ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)  || \
03007                                  ((CHANNEL) == ADC_CHANNEL_VBAT)        || \
03008                                  ((CHANNEL) == ADC_CHANNEL_VREFINT)     || \
03009                                  ((CHANNEL) == ADC_CHANNEL_VOPAMP1)     || \
03010                                  ((CHANNEL) == ADC_CHANNEL_VOPAMP2)     || \
03011                                  ((CHANNEL) == ADC_CHANNEL_VOPAMP3)     || \
03012                                  ((CHANNEL) == ADC_CHANNEL_VOPAMP4)       )
03013
03014 #define IS_ADC_DIFF_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_1)      || \
03015                                       ((CHANNEL) == ADC_CHANNEL_2)      || \
03016                                       ((CHANNEL) == ADC_CHANNEL_3)      || \
03017                                       ((CHANNEL) == ADC_CHANNEL_4)      || \
03018                                       ((CHANNEL) == ADC_CHANNEL_5)      || \
03019                                       ((CHANNEL) == ADC_CHANNEL_6)      || \
03020                                       ((CHANNEL) == ADC_CHANNEL_7)      || \
03021                                       ((CHANNEL) == ADC_CHANNEL_8)      || \
03022                                       ((CHANNEL) == ADC_CHANNEL_9)      || \
03023                                       ((CHANNEL) == ADC_CHANNEL_10)     || \
03024                                       ((CHANNEL) == ADC_CHANNEL_11)     || \
03025                                       ((CHANNEL) == ADC_CHANNEL_12)     || \
03026                                       ((CHANNEL) == ADC_CHANNEL_13)     || \
03027                                       ((CHANNEL) == ADC_CHANNEL_14)       )
03028
03029 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5)    || \
03030                                   ((TIME) == ADC_SAMPLETIME_2CYCLES_5)   || \
03031                                   ((TIME) == ADC_SAMPLETIME_4CYCLES_5)   || \
03032                                   ((TIME) == ADC_SAMPLETIME_7CYCLES_5)   || \
03033                                   ((TIME) == ADC_SAMPLETIME_19CYCLES_5)  || \
03034                                   ((TIME) == ADC_SAMPLETIME_61CYCLES_5)  || \
03035                                   ((TIME) == ADC_SAMPLETIME_181CYCLES_5) || \
03036                                   ((TIME) == ADC_SAMPLETIME_601CYCLES_5)   )
03037
03038 #define IS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF) (((SING_DIFF) == ADC_SINGLE_ENDED)      || \
03039                                                ((SING_DIFF) == ADC_DIFFERENTIAL_ENDED)  )
03040
03041 #define IS_ADC_OFFSET_NUMBER(OFFSET_NUMBER) (((OFFSET_NUMBER) == ADC_OFFSET_NONE) || \
03042                                              ((OFFSET_NUMBER) == ADC_OFFSET_1)    || \
03043                                              ((OFFSET_NUMBER) == ADC_OFFSET_2)    || \
03044                                              ((OFFSET_NUMBER) == ADC_OFFSET_3)    || \
03045                                              ((OFFSET_NUMBER) == ADC_OFFSET_4)      )
03046
03047 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
03048                                       ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
03049                                       ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
03050                                       ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
03051                                       ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
03052                                       ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
03053                                       ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
03054                                       ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
03055                                       ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
03056                                       ((CHANNEL) == ADC_REGULAR_RANK_10) || \
03057                                       ((CHANNEL) == ADC_REGULAR_RANK_11) || \
03058                                       ((CHANNEL) == ADC_REGULAR_RANK_12) || \
03059                                       ((CHANNEL) == ADC_REGULAR_RANK_13) || \
03060                                       ((CHANNEL) == ADC_REGULAR_RANK_14) || \
03061                                       ((CHANNEL) == ADC_REGULAR_RANK_15) || \
03062                                       ((CHANNEL) == ADC_REGULAR_RANK_16)   )
03063
03064 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
03065                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
03066                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
03067                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
03068
03069 #if defined(STM32F303xE) || defined(STM32F398xx) || \
03070     defined(STM32F303xC) || defined(STM32F358xx)
03071
03072 #if defined(STM32F303xC) || defined(STM32F358xx)
03073 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)   || \
03074                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)   || \
03075                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)   || \
03076                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4)   || \
03077                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)   || \
03078                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO)  || \
03079                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
03080                                                                                  \
03081                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC1)   || \
03082                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3)   || \
03083                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1)   || \
03084                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC1)   || \
03085                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T7_TRGO)  || \
03086                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1)   || \
03087                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT2)  || \
03088                                                                                  \
03089                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)   || \
03090                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO)  || \
03091                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
03092                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO)  || \
03093                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)  || \
03094                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO)  || \
03095                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO)  || \
03096                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
03097                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
03098                                                                                  \
03099                                  ((REGTRIG) == ADC_SOFTWARE_START)              )
03100 #endif /* STM32F303xC || STM32F358xx */
03101
03102 #if defined(STM32F303xE) || defined(STM32F398xx)
03103 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)    || \
03104                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)    || \
03105                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)    || \
03106                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4)    || \
03107                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)    || \
03108                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO)   || \
03109                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11)  || \
03110                                                                                   \
03111                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC1)    || \
03112                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3)    || \
03113                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1)    || \
03114                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC1)    || \
03115                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T7_TRGO)   || \
03116                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1)    || \
03117                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT2)   || \
03118                                                                                   \
03119                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)    || \
03120                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO)   || \
03121                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2)  || \
03122                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO)   || \
03123                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)   || \
03124                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO)   || \
03125                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO)   || \
03126                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2)  || \
03127                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO)  || \
03128                                                                                   \
03129                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC2)   || \
03130                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC3)   || \
03131                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC1)   || \
03132                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_TRGO)  || \
03133                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_TRGO2) || \
03134                                                                                   \
03135                                  ((REGTRIG) == ADC_SOFTWARE_START)               )
03136 #endif /* STM32F303xE || STM32F398xx */
03137
03138 #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
03139
03140 #if defined(STM32F302xE) || \
03141     defined(STM32F302xC)
03142
03143 #if defined(STM32F302xE)
03144 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)   || \
03145                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)   || \
03146                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)   || \
03147                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)   || \
03148                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)  || \
03149                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)   || \
03150                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
03151                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO)  || \
03152                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
03153                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO)  || \
03154                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO)  || \
03155                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO)  || \
03156                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
03157                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4)   || \
03158                                                                                  \
03159                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC2)  || \
03160                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC3)  || \
03161                                                                                  \
03162                                  ((REGTRIG) == ADC_SOFTWARE_START)              )
03163 #endif /* STM32F302xE */
03164
03165 #if defined(STM32F302xC)
03166 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)   || \
03167                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)   || \
03168                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)   || \
03169                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)   || \
03170                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)  || \
03171                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)   || \
03172                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
03173                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO)  || \
03174                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
03175                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO)  || \
03176                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO)  || \
03177                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO)  || \
03178                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
03179                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4)   || \
03180                                                                                  \
03181                                  ((REGTRIG) == ADC_SOFTWARE_START)              )
03182 #endif /* STM32F302xC */
03183
03184 #endif /* STM32F302xE || */
03185        /* STM32F302xC    */
03186
03187 #if defined(STM32F303x8) || defined(STM32F328xx)
03188 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)   || \
03189                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)   || \
03190                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)   || \
03191                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)   || \
03192                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)  || \
03193                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)   || \
03194                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
03195                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO)  || \
03196                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
03197                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO)  || \
03198                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
03199                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO)  || \
03200                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO)  || \
03201                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO)  || \
03202                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
03203                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4)   || \
03204                                                                                  \
03205                                  ((REGTRIG) == ADC_SOFTWARE_START)              )
03206 #endif /* STM32F303x8 || STM32F328xx */
03207
03208 #if defined(STM32F334x8)
03209 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)    || \
03210                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)    || \
03211                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)    || \
03212                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)    || \
03213                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)   || \
03214                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11)  || \
03215                                  ((REGTRIG) == ADC_EXTERNALTRIGCONVHRTIM_TRG1) || \
03216                                  ((REGTRIG) == ADC_EXTERNALTRIGCONVHRTIM_TRG3) || \
03217                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO)   || \
03218                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2)  || \
03219                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO)   || \
03220                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO)   || \
03221                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO)  || \
03222                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4)    || \
03223                                                                                   \
03224                                  ((REGTRIG) == ADC_SOFTWARE_START)               )
03225 #endif /* STM32F334x8 */
03226
03227 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
03228 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)   || \
03229                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)   || \
03230                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)   || \
03231                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
03232                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO)  || \
03233                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
03234                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO)  || \
03235                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO)  || \
03236                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
03237                                  ((REGTRIG) == ADC_SOFTWARE_START)              )
03238 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
03239
03240 #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \
03241                                         ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
03242                                         ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
03243                                         ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING)  )
03244
03245
03246 #if defined(STM32F303xE) || defined(STM32F398xx) || \
03247     defined(STM32F303xC) || defined(STM32F358xx)
03248
03249 #if defined(STM32F303xC) || defined(STM32F358xx)
03250 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
03251                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1)   || \
03252                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
03253                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)  || \
03254                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
03255                                                                                            \
03256                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3)   || \
03257                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4)   || \
03258                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO)  || \
03259                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2)   || \
03260                                                                                            \
03261                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
03262                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
03263                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
03264                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
03265                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3)   || \
03266                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO)  || \
03267                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
03268                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)   || \
03269                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO)  || \
03270                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
03271                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
03272                                                                                            \
03273                                       ((INJTRIG) == ADC_INJECTED_SOFTWARE_START)          )
03274 #endif /* STM32F303xC || STM32F358xx */
03275
03276 #if defined(STM32F303xE) || defined(STM32F398xx)
03277 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)    || \
03278                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1)    || \
03279                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)    || \
03280                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)   || \
03281                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)  || \
03282                                                                                             \
03283                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3)    || \
03284                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4)    || \
03285                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO)   || \
03286                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2)    || \
03287                                                                                             \
03288                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)    || \
03289                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)   || \
03290                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2)  || \
03291                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)   || \
03292                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3)    || \
03293                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO)   || \
03294                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)   || \
03295                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)    || \
03296                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO)   || \
03297                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2)  || \
03298                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO)  || \
03299                                                                                             \
03300                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4)   || \
03301                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC2)   || \
03302                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO)  || \
03303                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \
03304                                                                                             \
03305                                       ((INJTRIG) == ADC_INJECTED_SOFTWARE_START)           )
03306 #endif /* STM32F303xE || STM32F398xx */
03307
03308 #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
03309
03310 #if defined(STM32F302xE) || \
03311     defined(STM32F302xC)
03312
03313 #if defined(STM32F302xE)
03314 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)    || \
03315                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)   || \
03316                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2)  || \
03317                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)    || \
03318                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)   || \
03319                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1)    || \
03320                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3)    || \
03321                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)    || \
03322                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO)   || \
03323                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)   || \
03324                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)   || \
03325                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO)  || \
03326                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)  || \
03327                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4)   || \
03328                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO)  || \
03329                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \
03330                                       ((INJTRIG) == ADC_INJECTED_SOFTWARE_START)             )
03331 #endif /* STM32F302xE */
03332
03333 #if defined(STM32F302xC)
03334 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
03335                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
03336                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
03337                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
03338                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
03339                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1)   || \
03340                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3)   || \
03341                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
03342                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO)  || \
03343                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
03344                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)  || \
03345                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
03346                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
03347                                       ((INJTRIG) == ADC_INJECTED_SOFTWARE_START)          )
03348 #endif /* STM32F302xC */
03349
03350 #endif /* STM32F302xE || */
03351        /* STM32F302xC    */
03352
03353 #if defined(STM32F303x8) || defined(STM32F328xx)
03354 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
03355                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
03356                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
03357                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
03358                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
03359                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
03360                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
03361                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)   || \
03362                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
03363                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO)  || \
03364                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
03365                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3)   || \
03366                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO)  || \
03367                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1)   || \
03368                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)  || \
03369                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
03370                                       ((INJTRIG) == ADC_INJECTED_SOFTWARE_START)          )
03371 #endif /* STM32F303x8 || STM32F328xx */
03372
03373 #if defined(STM32F334x8)
03374 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)    || \
03375                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)     || \
03376                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)    || \
03377                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)     || \
03378                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)     || \
03379                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)   || \
03380                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2)   || \
03381                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG2) || \
03382                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4) || \
03383                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3)     || \
03384                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO)    || \
03385                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1)     || \
03386                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)    || \
03387                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO)   || \
03388                                       ((INJTRIG) == ADC_INJECTED_SOFTWARE_START)            )
03389 #endif /* STM32F334x8 */
03390
03391 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
03392 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
03393                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
03394                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
03395                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
03396                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)  || \
03397                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
03398                                       ((INJTRIG) == ADC_INJECTED_SOFTWARE_START)          )
03399 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
03400
03401 #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
03402                                        ((CHANNEL) == ADC_INJECTED_RANK_2) || \
03403                                        ((CHANNEL) == ADC_INJECTED_RANK_3) || \
03404                                        ((CHANNEL) == ADC_INJECTED_RANK_4)   )
03405
03406 #define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT)               || \
03407                            ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
03408                            ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \
03409                            ((MODE) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
03410                            ((MODE) == ADC_DUALMODE_INJECSIMULT)           || \
03411                            ((MODE) == ADC_DUALMODE_REGSIMULT)             || \
03412                            ((MODE) == ADC_DUALMODE_INTERL)                || \
03413                            ((MODE) == ADC_DUALMODE_ALTERTRIG)               )
03414
03415 #define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED)   || \
03416                                       ((MODE) == ADC_DMAACCESSMODE_12_10_BITS) || \
03417                                       ((MODE) == ADC_DMAACCESSMODE_8_6_BITS)     )
03418
03419 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_1CYCLE)   || \
03420                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_2CYCLES)  || \
03421                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_3CYCLES)  || \
03422                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_4CYCLES)  || \
03423                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
03424                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
03425                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
03426                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
03427                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
03428                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
03429                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
03430                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES)   )
03431
03432 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \
03433                                                  ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \
03434                                                  ((WATCHDOG) == ADC_ANALOGWATCHDOG_3)   )
03435
03436 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)             || \
03437                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
03438                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
03439                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
03440                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
03441                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
03442                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )
03443
03444 #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP)         || \
03445                                              ((CONVERSION) == ADC_INJECTED_GROUP)        || \
03446                                              ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP)  )
03447
03448 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT)  || \
03449                                   ((EVENT) == ADC_AWD2_EVENT) || \
03450                                   ((EVENT) == ADC_AWD3_EVENT) || \
03451                                   ((EVENT) == ADC_OVR_EVENT)  || \
03452                                   ((EVENT) == ADC_JQOVF_EVENT)  )
03453
03454 /** @defgroup ADCEx_range_verification ADC Extended Range Verification
03455   * in function of ADC resolution selected (12, 10, 8 or 6 bits)
03456   * @{
03457   */
03458 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE)                                         \
03459    ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \
03460     (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \
03461     (((RESOLUTION) == ADC_RESOLUTION_8B)  && ((ADC_VALUE) <= (0x00FFU))) || \
03462     (((RESOLUTION) == ADC_RESOLUTION_6B)  && ((ADC_VALUE) <= (0x003FU)))   )
03463 /**
03464   * @}
03465   */
03466
03467 /** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification
03468   * @{
03469   */
03470 #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U)))
03471 /**
03472   * @}
03473   */
03474
03475 /** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
03476   * @{
03477   */
03478 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U)))
03479 /**
03480   * @}
03481   */
03482
03483 /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification
03484   * @{
03485   */
03486 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))
03487 /**
03488   * @}
03489   */
03490
03491 /** @defgroup ADC_calibration_factor_length_verification ADC Calibration Factor Length Verification
03492   * @{
03493   */
03494 /**
03495   * @brief Calibration factor length verification (7 bits maximum)
03496   * @param _Calibration_Factor_ Calibration factor value
03497   * @retval None
03498   */
03499 #define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= (0x7FU))
03500 /**
03501   * @}
03502   */
03503
03504 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
03505        /* STM32F302xC || STM32F303xC || STM32F358xx || */
03506        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
03507        /* STM32F301x8 || STM32F302x8 || STM32F318xx */
03508
03509
03510 #if defined(STM32F373xC) || defined(STM32F378xx)
03511
03512 /**
03513   * @brief Verification of ADC state: enabled or disabled
03514   * @param __HANDLE__ ADC handle
03515   * @retval SET (ADC enabled) or RESET (ADC disabled)
03516   */
03517 #define ADC_IS_ENABLE(__HANDLE__)                                              \
03518   ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON )           \
03519    ) ? SET : RESET)
03520
03521 /**
03522   * @brief Test if conversion trigger of regular group is software start
03523   *        or external trigger.
03524   * @param __HANDLE__ ADC handle
03525   * @retval SET (software start) or RESET (external trigger)
03526   */
03527 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
03528   (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
03529
03530 /**
03531   * @brief Test if conversion trigger of injected group is software start
03532   *        or external trigger.
03533   * @param __HANDLE__ ADC handle
03534   * @retval SET (software start) or RESET (external trigger)
03535   */
03536 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
03537   (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
03538
03539 /**
03540   * @brief Simultaneously clears and sets specific bits of the handle State
03541   * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
03542   *        the first parameter is the ADC handle State, the second parameter is the
03543   *        bit field to clear, the third and last parameter is the bit field to set.
03544   * @retval None
03545   */
03546 #define ADC_STATE_CLR_SET MODIFY_REG
03547
03548 /**
03549   * @brief Clear ADC error code (set it to error code: "no error")
03550   * @param __HANDLE__ ADC handle
03551   * @retval None
03552   */
03553 #define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
03554   ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
03555
03556 /**
03557   * @brief Set ADC number of conversions into regular channel sequence length.
03558   * @param _NbrOfConversion_ Regular channel sequence length
03559   * @retval None
03560   */
03561 #define ADC_SQR1_L_SHIFT(_NbrOfConversion_)                                    \
03562   (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
03563
03564 /**
03565   * @brief Set the ADC's sample time for channel numbers between 10 and 18.
03566   * @param _SAMPLETIME_ Sample time parameter.
03567   * @param _CHANNELNB_ Channel number.
03568   * @retval None
03569   */
03570 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_)                                   \
03571   ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U)))
03572
03573 /**
03574   * @brief Set the ADC's sample time for channel numbers between 0 and 9.
03575   * @param _SAMPLETIME_ Sample time parameter.
03576   * @param _CHANNELNB_ Channel number.
03577   * @retval None
03578   */
03579 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_)                                   \
03580   ((_SAMPLETIME_) << (3U * (_CHANNELNB_)))
03581
03582 /**
03583   * @brief Set the selected regular channel rank for rank between 1 and 6.
03584   * @param _CHANNELNB_ Channel number.
03585   * @param _RANKNB_ Rank number.
03586   * @retval None
03587   */
03588 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_)                                     \
03589   ((_CHANNELNB_) << (5U * ((_RANKNB_) - 1U)))
03590
03591 /**
03592   * @brief Set the selected regular channel rank for rank between 7 and 12.
03593   * @param _CHANNELNB_ Channel number.
03594   * @param _RANKNB_ Rank number.
03595   * @retval None
03596   */
03597 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_)                                     \
03598   ((_CHANNELNB_) << (5U * ((_RANKNB_) - 7U)))
03599
03600 /**
03601   * @brief Set the selected regular channel rank for rank between 13 and 16.
03602   * @param _CHANNELNB_ Channel number.
03603   * @param _RANKNB_ Rank number.
03604   * @retval None
03605   */
03606 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_)                                     \
03607   ((_CHANNELNB_) << (5U * ((_RANKNB_) - 13U)))
03608
03609 /**
03610   * @brief Set the injected sequence length.
03611   * @param _JSQR_JL_ Sequence length.
03612   * @retval None
03613   */
03614 #define ADC_JSQR_JL_SHIFT(_JSQR_JL_)                                           \
03615   (((_JSQR_JL_) -1U) << 20U)
03616
03617 /**
03618   * @brief Set the selected injected channel rank
03619   *        Note: on STM32F37x devices, channel rank position in JSQR register
03620   *              is depending on total number of ranks selected into
03621   *              injected sequencer (ranks sequence starting from 4-JL)
03622   * @param _CHANNELNB_ Channel number.
03623   * @param _RANKNB_ Rank number.
03624   * @param _JSQR_JL_ Sequence length.
03625   * @retval None
03626   */
03627 #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_)                       \
03628   ((_CHANNELNB_) << (5U * ((4U - ((_JSQR_JL_) - (_RANKNB_))) - 1U)))
03629
03630 /**
03631   * @brief Enable ADC continuous conversion mode.
03632   * @param _CONTINUOUS_MODE_ Continuous mode.
03633   * @retval None
03634   */
03635 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_)                                  \
03636   ((_CONTINUOUS_MODE_) << 1U)
03637
03638 /**
03639   * @brief Configures the number of discontinuous conversions for the regular group channels.
03640   * @param _NBR_DISCONTINUOUS_CONV_ Number of discontinuous conversions.
03641   * @retval None
03642   */
03643 #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_)                    \
03644   (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 13U)
03645
03646 /**
03647   * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
03648   * @param _SCAN_MODE_ Scan conversion mode.
03649   * @retval None
03650   */
03651 /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter   */
03652 /*       is equivalent to ADC_SCAN_ENABLE.                                    */
03653 #define ADC_CR1_SCAN_SET(_SCAN_MODE_)                                          \
03654   (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE)           \
03655    )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE)                                   \
03656   )
03657
03658 /**
03659   * @brief Calibration factor in differential mode to be set into calibration register
03660   * @param _Calibration_Factor_ Calibration factor value
03661   * @retval None
03662   */
03663 #define ADC_CALFACT_DIFF_SET(_Calibration_Factor_)                             \
03664   ((_Calibration_Factor_) << 16U)
03665
03666 /**
03667   * @brief Calibration factor in differential mode to be retrieved from calibration register
03668   * @param _Calibration_Factor_ Calibration factor value
03669   * @retval None
03670   */
03671 #define ADC_CALFACT_DIFF_GET(_Calibration_Factor_)                             \
03672   ((_Calibration_Factor_) >> 16U)
03673
03674
03675 /**
03676   * @brief Get the maximum ADC conversion cycles on all channels.
03677   * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
03678   * Approximation of sampling time within 4 ranges, returns the highest value:
03679   *   below 7.5 cycles {1.5 cycle; 7.5 cycles},
03680   *   between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
03681   *   between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
03682   *   equal to 239.5 cycles
03683   * Unit: ADC clock cycles
03684   * @param __HANDLE__ ADC handle
03685   * @retval ADC conversion cycles on all channels
03686   */
03687 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)                                                                     \
03688     (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET)  &&                     \
03689        (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ?                     \
03690                                                                                                                  \
03691           (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET)  &&               \
03692              (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ?               \
03693                ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5)   \
03694           :                                                                                                      \
03695           ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET)  &&               \
03696              (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) ||               \
03697             ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET)  &&               \
03698              (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ?               \
03699                ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
03700      )
03701
03702 /**
03703   * @brief Get the total ADC clock prescaler (APB2 prescaler x ADC prescaler)
03704   * from system clock configuration register.
03705   * Approximation within 3 ranges, returns the higher value:
03706   *   total prescaler minimum: 2 (ADC presc 2, APB2 presc 0)
03707   *   total prescaler 32 (ADC presc 0 and APB2 presc all, or
03708   *                       ADC presc {4, 6, 8} and APB2 presc {0, 2, 4})
03709   *   total prescaler maximum: 128 (ADC presc {4, 6, 8} and APB2 presc {8, 16})
03710   * Unit: none (prescaler factor)
03711   * @retval ADC and APB2 prescaler factor
03712   */
03713 #define ADC_CLOCK_PRESCALER_RANGE()                                            \
03714   (( (RCC->CFGR & (RCC_CFGR_ADCPRE_1 | RCC_CFGR_ADCPRE_0)) == RESET) ?         \
03715       (( (RCC->CFGR & RCC_CFGR_PPRE2_2) == RESET) ? 2 : 32U )                   \
03716       :                                                                        \
03717       (( (RCC->CFGR & RCC_CFGR_PPRE2_1) == RESET) ? 32 : 128U )                 \
03718   )
03719
03720 /**
03721   * @brief Get the ADC clock prescaler from system clock configuration register.
03722   * @retval None
03723   */
03724 #define ADC_GET_CLOCK_PRESCALER() (((RCC->CFGR & RCC_CFGR_ADCPRE) >> 14U) +1U)
03725
03726 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
03727                                   ((ALIGN) == ADC_DATAALIGN_LEFT)    )
03728
03729 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
03730                                      ((SCAN_MODE) == ADC_SCAN_ENABLE)    )
03731
03732 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
03733                                  ((CHANNEL) == ADC_CHANNEL_1)           || \
03734                                  ((CHANNEL) == ADC_CHANNEL_2)           || \
03735                                  ((CHANNEL) == ADC_CHANNEL_3)           || \
03736                                  ((CHANNEL) == ADC_CHANNEL_4)           || \
03737                                  ((CHANNEL) == ADC_CHANNEL_5)           || \
03738                                  ((CHANNEL) == ADC_CHANNEL_6)           || \
03739                                  ((CHANNEL) == ADC_CHANNEL_7)           || \
03740                                  ((CHANNEL) == ADC_CHANNEL_8)           || \
03741                                  ((CHANNEL) == ADC_CHANNEL_9)           || \
03742                                  ((CHANNEL) == ADC_CHANNEL_10)          || \
03743                                  ((CHANNEL) == ADC_CHANNEL_11)          || \
03744                                  ((CHANNEL) == ADC_CHANNEL_12)          || \
03745                                  ((CHANNEL) == ADC_CHANNEL_13)          || \
03746                                  ((CHANNEL) == ADC_CHANNEL_14)          || \
03747                                  ((CHANNEL) == ADC_CHANNEL_15)          || \
03748                                  ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)  || \
03749                                  ((CHANNEL) == ADC_CHANNEL_VREFINT)     || \
03750                                  ((CHANNEL) == ADC_CHANNEL_VBAT)          )
03751
03752 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5)    || \
03753                                   ((TIME) == ADC_SAMPLETIME_7CYCLES_5)   || \
03754                                   ((TIME) == ADC_SAMPLETIME_13CYCLES_5)  || \
03755                                   ((TIME) == ADC_SAMPLETIME_28CYCLES_5)  || \
03756                                   ((TIME) == ADC_SAMPLETIME_41CYCLES_5)  || \
03757                                   ((TIME) == ADC_SAMPLETIME_55CYCLES_5)  || \
03758                                   ((TIME) == ADC_SAMPLETIME_71CYCLES_5)  || \
03759                                   ((TIME) == ADC_SAMPLETIME_239CYCLES_5)   )
03760
03761 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
03762                                       ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
03763                                       ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
03764                                       ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
03765                                       ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
03766                                       ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
03767                                       ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
03768                                       ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
03769                                       ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
03770                                       ((CHANNEL) == ADC_REGULAR_RANK_10) || \
03771                                       ((CHANNEL) == ADC_REGULAR_RANK_11) || \
03772                                       ((CHANNEL) == ADC_REGULAR_RANK_12) || \
03773                                       ((CHANNEL) == ADC_REGULAR_RANK_13) || \
03774                                       ((CHANNEL) == ADC_REGULAR_RANK_14) || \
03775                                       ((CHANNEL) == ADC_REGULAR_RANK_15) || \
03776                                       ((CHANNEL) == ADC_REGULAR_RANK_16)   )
03777
03778 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)  || \
03779                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)  )
03780
03781 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)   || \
03782                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)  || \
03783                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)   || \
03784                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_TRGO) || \
03785                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC3)  || \
03786                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC4)  || \
03787                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
03788                                  ((REGTRIG) == ADC_SOFTWARE_START)              )
03789
03790 #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)  || \
03791                                         ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)  )
03792
03793 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
03794                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
03795                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
03796                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
03797                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC1)  || \
03798                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC2)  || \
03799                                       ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
03800                                       ((INJTRIG) == ADC_INJECTED_SOFTWARE_START)          )
03801
03802 #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
03803                                        ((CHANNEL) == ADC_INJECTED_RANK_2) || \
03804                                        ((CHANNEL) == ADC_INJECTED_RANK_3) || \
03805                                        ((CHANNEL) == ADC_INJECTED_RANK_4)   )
03806
03807 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)             || \
03808                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
03809                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
03810                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
03811                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
03812                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
03813                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )
03814
03815 #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP)          || \
03816                                              ((CONVERSION) == ADC_INJECTED_GROUP)         || \
03817                                              ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP)   )
03818
03819 #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
03820
03821 /** @defgroup ADCEx_range_verification ADC Extended Range Verification
03822   * For a unique ADC resolution: 12 bits
03823   * @{
03824   */
03825 #define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= (0x0FFFU))
03826 /**
03827   * @}
03828   */
03829
03830 /** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification
03831   * @{
03832   */
03833 #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U)))
03834 /**
03835   * @}
03836   */
03837
03838 /** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
03839   * @{
03840   */
03841 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U)))
03842 /**
03843   * @}
03844   */
03845
03846 /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification
03847   * @{
03848   */
03849 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))
03850 /**
03851   * @}
03852   */
03853
03854 #endif /* STM32F373xC || STM32F378xx */
03855 /**
03856   * @}
03857   */
03858
03859
03860 /* Exported functions --------------------------------------------------------*/
03861 /** @addtogroup ADCEx_Exported_Functions ADCEx Exported Functions
03862   * @{
03863   */
03864
03865 /* Initialization/de-initialization functions *********************************/
03866
03867 /** @addtogroup ADCEx_Exported_Functions_Group2 ADCEx Input and Output operation functions
03868   * @{
03869   */
03870 /* I/O operation functions ****************************************************/
03871
03872 /* ADC calibration */
03873 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
03874     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
03875     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
03876     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
03877 HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(struct __ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
03878 uint32_t                HAL_ADCEx_Calibration_GetValue(struct __ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
03879 HAL_StatusTypeDef       HAL_ADCEx_Calibration_SetValue(struct __ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
03880 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
03881        /* STM32F302xC || STM32F303xC || STM32F358xx || */
03882        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
03883        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
03884
03885 #if defined(STM32F373xC) || defined(STM32F378xx)
03886 HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(struct __ADC_HandleTypeDef* hadc);
03887 #endif /* STM32F373xC || STM32F378xx */
03888
03889 /* Blocking mode: Polling */
03890 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(struct __ADC_HandleTypeDef* hadc);
03891 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(struct __ADC_HandleTypeDef* hadc);
03892 HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(struct __ADC_HandleTypeDef* hadc, uint32_t Timeout);
03893
03894 /* Non-blocking mode: Interruption */
03895 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(struct __ADC_HandleTypeDef* hadc);
03896 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(struct __ADC_HandleTypeDef* hadc);
03897
03898 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
03899     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
03900     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
03901     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
03902 /* ADC multimode */
03903 HAL_StatusTypeDef       HAL_ADCEx_MultiModeStart_DMA(struct __ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
03904 HAL_StatusTypeDef       HAL_ADCEx_MultiModeStop_DMA(struct __ADC_HandleTypeDef *hadc);
03905 uint32_t                HAL_ADCEx_MultiModeGetValue(struct __ADC_HandleTypeDef *hadc);
03906 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
03907        /* STM32F302xC || STM32F303xC || STM32F358xx || */
03908        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
03909        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
03910
03911 /* ADC group regular stop conversion without impacting group injected */
03912 /* Blocking mode: Polling */
03913 HAL_StatusTypeDef       HAL_ADCEx_RegularStop(struct __ADC_HandleTypeDef* hadc);
03914 /* Non-blocking mode: Interruption */
03915 HAL_StatusTypeDef       HAL_ADCEx_RegularStop_IT(struct __ADC_HandleTypeDef* hadc);
03916 /* Non-blocking mode: DMA */
03917 HAL_StatusTypeDef       HAL_ADCEx_RegularStop_DMA(struct __ADC_HandleTypeDef* hadc);
03918 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
03919     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
03920     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
03921     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
03922 /* ADC multimode */
03923 HAL_StatusTypeDef       HAL_ADCEx_RegularMultiModeStop_DMA(struct __ADC_HandleTypeDef *hadc);
03924 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
03925        /* STM32F302xC || STM32F303xC || STM32F358xx || */
03926        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
03927        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
03928
03929 /* ADC retrieve conversion value intended to be used with polling or interruption */
03930 uint32_t                HAL_ADCEx_InjectedGetValue(struct __ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
03931
03932 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
03933 void                    HAL_ADCEx_InjectedConvCpltCallback(struct __ADC_HandleTypeDef* hadc);
03934
03935 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
03936     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
03937     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
03938     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
03939 void                    HAL_ADCEx_InjectedQueueOverflowCallback(struct __ADC_HandleTypeDef* hadc);
03940 void                    HAL_ADCEx_LevelOutOfWindow2Callback(struct __ADC_HandleTypeDef* hadc);
03941 void                    HAL_ADCEx_LevelOutOfWindow3Callback(struct __ADC_HandleTypeDef* hadc);
03942 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
03943        /* STM32F302xC || STM32F303xC || STM32F358xx || */
03944        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
03945        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
03946 /**
03947   * @}
03948   */
03949
03950 /** @addtogroup ADCEx_Exported_Functions_Group3 ADCEx Peripheral Control functions
03951   * @{
03952   */
03953 /* Peripheral Control functions ***********************************************/
03954 HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(struct __ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
03955
03956 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
03957     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
03958     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
03959     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
03960 HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(struct __ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
03961 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
03962        /* STM32F302xC || STM32F303xC || STM32F358xx || */
03963        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
03964        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
03965 /**
03966   * @}
03967   */
03968
03969 /**
03970   * @}
03971   */
03972
03973 /**
03974   * @}
03975   */
03976
03977 /**
03978   * @}
03979   */
03980
03981 #ifdef __cplusplus
03982 }
03983 #endif
03984
03985 #endif /*__STM32F3xx_ADC_H */
03986
03987
03988 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_can.c Source File

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stm32f3xx_hal_can.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_can.c
00004   * @author  MCD Application Team
00005   * @brief   CAN HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Controller Area Network (CAN) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State and Error functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018       (#) Enable the CAN controller interface clock using __HAL_RCC_CAN1_CLK_ENABLE();
00019
00020       (#) CAN pins configuration
00021         (++) Enable the clock for the CAN GPIOs using the following function:
00022              __HAL_RCC_GPIOx_CLK_ENABLE();
00023         (++) Connect and configure the involved CAN pins to AF9 using the
00024               following function HAL_GPIO_Init();
00025
00026       (#) Initialise and configure the CAN using HAL_CAN_Init() function.
00027
00028       (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
00029
00030       (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
00031
00032       (#) Receive a CAN frame using HAL_CAN_Receive() function.
00033
00034       (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
00035
00036      *** Polling mode IO operation ***
00037      =================================
00038      [..]
00039        (+) Start the CAN peripheral transmission and wait the end of this operation
00040            using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
00041            according to his end application
00042        (+) Start the CAN peripheral reception and wait the end of this operation
00043            using HAL_CAN_Receive(), at this stage user can specify the value of timeout
00044            according to his end application
00045
00046      *** Interrupt mode IO operation ***
00047      ===================================
00048      [..]
00049        (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
00050        (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
00051        (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
00052        (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
00053             add his own code by customization of function pointer HAL_CAN_TxCpltCallback
00054        (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
00055             add his own code by customization of function pointer HAL_CAN_ErrorCallback
00056
00057      *** CAN HAL driver macros list ***
00058      =============================================
00059      [..]
00060        Below the list of most used macros in CAN HAL driver.
00061
00062       (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
00063       (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
00064       (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
00065       (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
00066       (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
00067
00068      [..]
00069       (@) You can refer to the CAN HAL driver header file for more useful macros
00070
00071   @endverbatim
00072
00073   ******************************************************************************
00074   * @attention
00075   *
00076   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00077   *
00078   * Redistribution and use in source and binary forms, with or without modification,
00079   * are permitted provided that the following conditions are met:
00080   *   1. Redistributions of source code must retain the above copyright notice,
00081   *      this list of conditions and the following disclaimer.
00082   *   2. Redistributions in binary form must reproduce the above copyright notice,
00083   *      this list of conditions and the following disclaimer in the documentation
00084   *      and/or other materials provided with the distribution.
00085   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00086   *      may be used to endorse or promote products derived from this software
00087   *      without specific prior written permission.
00088   *
00089   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00090   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00091   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00092   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00093   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00094   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00095   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00096   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00097   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00098   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00099   *
00100   ******************************************************************************
00101   */
00102
00103 /* Includes ------------------------------------------------------------------*/
00104 #include "stm32f3xx_hal.h"
00105
00106 /** @addtogroup STM32F3xx_HAL_Driver
00107   * @{
00108   */
00109
00110 /** @defgroup CAN CAN
00111   * @brief CAN driver modules
00112   * @{
00113   */
00114
00115 #ifdef HAL_CAN_MODULE_ENABLED
00116
00117 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00118     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00119     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00120     defined(STM32F302x8)                                                 || \
00121     defined(STM32F373xC) || defined(STM32F378xx)
00122
00123 /* Private typedef -----------------------------------------------------------*/
00124 /* Private define ------------------------------------------------------------*/
00125 /** @defgroup CAN_Private_Constants CAN Private Constants
00126   * @{
00127   */
00128 #define CAN_TIMEOUT_VALUE 10U
00129 /**
00130   * @}
00131   */
00132 /* Private macro -------------------------------------------------------------*/
00133 /* Private variables ---------------------------------------------------------*/
00134 /* Private function prototypes -----------------------------------------------*/
00135 /** @defgroup CAN_Private_Functions CAN Private Functions
00136   * @{
00137   */
00138 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
00139 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
00140 /**
00141   * @}
00142   */
00143
00144 /* Exported functions ---------------------------------------------------------*/
00145
00146 /** @defgroup CAN_Exported_Functions CAN Exported Functions
00147   * @{
00148   */
00149
00150 /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
00151  *  @brief    Initialization and Configuration functions
00152  *
00153 @verbatim
00154   ==============================================================================
00155               ##### Initialization and de-initialization functions #####
00156   ==============================================================================
00157     [..]  This section provides functions allowing to:
00158       (+) Initialize and configure the CAN.
00159       (+) De-initialize the CAN.
00160
00161 @endverbatim
00162   * @{
00163   */
00164
00165 /**
00166   * @brief Initializes the CAN peripheral according to the specified
00167   *        parameters in the CAN_InitStruct.
00168   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
00169   *             the configuration information for the specified CAN.
00170   * @retval HAL status
00171   */
00172 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
00173 {
00174   uint32_t status = CAN_INITSTATUS_FAILED;  /* Default init status */
00175   uint32_t tickstart = 0U;
00176
00177   /* Check CAN handle */
00178   if(hcan == NULL)
00179   {
00180      return HAL_ERROR;
00181   }
00182
00183   /* Check the parameters */
00184   assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
00185   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
00186   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
00187   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
00188   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
00189   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
00190   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
00191   assert_param(IS_CAN_MODE(hcan->Init.Mode));
00192   assert_param(IS_CAN_SJW(hcan->Init.SJW));
00193   assert_param(IS_CAN_BS1(hcan->Init.BS1));
00194   assert_param(IS_CAN_BS2(hcan->Init.BS2));
00195   assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
00196
00197   if(hcan->State == HAL_CAN_STATE_RESET)
00198   {
00199     /* Allocate lock resource and initialize it */
00200     hcan->Lock = HAL_UNLOCKED;
00201     /* Init the low level hardware */
00202     HAL_CAN_MspInit(hcan);
00203   }
00204
00205   /* Initialize the CAN state*/
00206   hcan->State = HAL_CAN_STATE_BUSY;
00207
00208   /* Exit from sleep mode */
00209   CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
00210
00211   /* Request initialisation */
00212   SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
00213
00214   /* Get tick */
00215   tickstart = HAL_GetTick();
00216
00217   /* Wait the acknowledge */
00218   while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
00219   {
00220     if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
00221     {
00222       hcan->State= HAL_CAN_STATE_TIMEOUT;
00223       /* Process unlocked */
00224       __HAL_UNLOCK(hcan);
00225       return HAL_TIMEOUT;
00226     }
00227   }
00228
00229   /* Check acknowledge */
00230   if (HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
00231   {
00232     /* Set the time triggered communication mode */
00233     if (hcan->Init.TTCM == ENABLE)
00234     {
00235       SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
00236     }
00237     else
00238     {
00239       CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
00240     }
00241
00242     /* Set the automatic bus-off management */
00243     if (hcan->Init.ABOM == ENABLE)
00244     {
00245       SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
00246     }
00247     else
00248     {
00249       CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
00250     }
00251
00252     /* Set the automatic wake-up mode */
00253     if (hcan->Init.AWUM == ENABLE)
00254     {
00255       SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
00256     }
00257     else
00258     {
00259       CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
00260     }
00261
00262     /* Set the no automatic retransmission */
00263     if (hcan->Init.NART == ENABLE)
00264     {
00265       SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
00266     }
00267     else
00268     {
00269       CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
00270     }
00271
00272     /* Set the receive FIFO locked mode */
00273     if (hcan->Init.RFLM == ENABLE)
00274     {
00275       SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
00276     }
00277     else
00278     {
00279       CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
00280     }
00281
00282     /* Set the transmit FIFO priority */
00283     if (hcan->Init.TXFP == ENABLE)
00284     {
00285       SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
00286     }
00287     else
00288     {
00289       CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
00290     }
00291
00292     /* Set the bit timing register */
00293     WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode           |
00294                                               hcan->Init.SJW            |
00295                                               hcan->Init.BS1            |
00296                                               hcan->Init.BS2            |
00297                                               (hcan->Init.Prescaler - 1U) ));
00298
00299     /* Request leave initialisation */
00300     CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
00301
00302     /* Get tick */
00303     tickstart = HAL_GetTick();
00304
00305     /* Wait the acknowledge */
00306     while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
00307     {
00308       if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
00309       {
00310          hcan->State= HAL_CAN_STATE_TIMEOUT;
00311
00312        /* Process unlocked */
00313        __HAL_UNLOCK(hcan);
00314
00315        return HAL_TIMEOUT;
00316       }
00317     }
00318
00319     /* Check acknowledged */
00320     if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
00321     {
00322       status = CAN_INITSTATUS_SUCCESS;
00323     }
00324   }
00325
00326   if(status == CAN_INITSTATUS_SUCCESS)
00327   {
00328     /* Set CAN error code to none */
00329     hcan->ErrorCode = HAL_CAN_ERROR_NONE;
00330
00331     /* Initialize the CAN state */
00332     hcan->State = HAL_CAN_STATE_READY;
00333
00334     /* Return function status */
00335     return HAL_OK;
00336   }
00337   else
00338   {
00339     /* Initialize the CAN state */
00340     hcan->State = HAL_CAN_STATE_ERROR;
00341
00342     /* Return function status */
00343     return HAL_ERROR;
00344   }
00345 }
00346
00347 /**
00348   * @brief  Configures the CAN reception filter according to the specified
00349   *         parameters in the CAN_FilterInitStruct.
00350   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
00351   *         the configuration information for the specified CAN.
00352   * @param  sFilterConfig pointer to a CAN_FilterConfTypeDef structure that
00353   *         contains the filter configuration information.
00354   * @retval None
00355   */
00356 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
00357 {
00358   uint32_t filternbrbitpos = 0U;
00359
00360   /* Check the parameters */
00361   assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
00362   assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
00363   assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
00364   assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
00365   assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
00366
00367   filternbrbitpos = (1U) << sFilterConfig->FilterNumber;
00368
00369   /* Initialisation mode for the filter */
00370   SET_BIT(hcan->Instance->FMR, CAN_FMR_FINIT);
00371
00372   /* Filter Deactivation */
00373   CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos);
00374
00375   /* Filter Scale */
00376   if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
00377   {
00378     /* 16-bit scale for the filter */
00379     CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos);
00380
00381     /* First 16-bit identifier and First 16-bit mask */
00382     /* Or First 16-bit identifier and Second 16-bit identifier */
00383     hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
00384        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
00385         (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
00386
00387     /* Second 16-bit identifier and Second 16-bit mask */
00388     /* Or Third 16-bit identifier and Fourth 16-bit identifier */
00389     hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
00390        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
00391         (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
00392   }
00393
00394   if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
00395   {
00396     /* 32-bit scale for the filter */
00397     SET_BIT(hcan->Instance->FS1R, filternbrbitpos);
00398
00399     /* 32-bit identifier or First 32-bit identifier */
00400     hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
00401        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
00402         (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
00403
00404     /* 32-bit mask or Second 32-bit identifier */
00405     hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
00406        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
00407         (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
00408   }
00409
00410   /* Filter Mode */
00411   if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
00412   {
00413     /*Id/Mask mode for the filter*/
00414     CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos);
00415   }
00416   else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
00417   {
00418     /*Identifier list mode for the filter*/
00419     SET_BIT(hcan->Instance->FM1R, filternbrbitpos);
00420   }
00421
00422   /* Filter FIFO assignment */
00423   if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
00424   {
00425     /* FIFO 0 assignation for the filter */
00426     CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos);
00427   }
00428   else
00429   {
00430     /* FIFO 1 assignation for the filter */
00431     SET_BIT(hcan->Instance->FFA1R, filternbrbitpos);
00432   }
00433
00434   /* Filter activation */
00435   if (sFilterConfig->FilterActivation == ENABLE)
00436   {
00437     SET_BIT(hcan->Instance->FA1R, filternbrbitpos);
00438   }
00439
00440   /* Leave the initialisation mode for the filter */
00441   CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT));
00442
00443   /* Return function status */
00444   return HAL_OK;
00445 }
00446
00447 /**
00448   * @brief  Deinitializes the CANx peripheral registers to their default reset values.
00449   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
00450   *         the configuration information for the specified CAN.
00451   * @retval HAL status
00452   */
00453 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
00454 {
00455   /* Check CAN handle */
00456   if(hcan == NULL)
00457   {
00458      return HAL_ERROR;
00459   }
00460
00461   /* Check the parameters */
00462   assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
00463
00464   /* Change CAN state */
00465   hcan->State = HAL_CAN_STATE_BUSY;
00466
00467   /* DeInit the low level hardware */
00468   HAL_CAN_MspDeInit(hcan);
00469
00470   /* Change CAN state */
00471   hcan->State = HAL_CAN_STATE_RESET;
00472
00473   /* Release Lock */
00474   __HAL_UNLOCK(hcan);
00475
00476   /* Return function status */
00477   return HAL_OK;
00478 }
00479
00480 /**
00481   * @brief  Initializes the CAN MSP.
00482   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
00483   *         the configuration information for the specified CAN.
00484   * @retval None
00485   */
00486 __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
00487 {
00488   /* Prevent unused argument(s) compilation warning */
00489   UNUSED(hcan);
00490
00491   /* NOTE : This function Should not be modified, when the callback is needed,
00492             the HAL_CAN_MspInit could be implemented in the user file
00493    */
00494 }
00495
00496 /**
00497   * @brief  DeInitializes the CAN MSP.
00498   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
00499   *         the configuration information for the specified CAN.
00500   * @retval None
00501   */
00502 __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
00503 {
00504   /* Prevent unused argument(s) compilation warning */
00505   UNUSED(hcan);
00506
00507   /* NOTE : This function Should not be modified, when the callback is needed,
00508             the HAL_CAN_MspDeInit could be implemented in the user file
00509    */
00510 }
00511
00512 /**
00513   * @}
00514   */
00515
00516 /** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
00517  *  @brief    IO operation functions
00518  *
00519 @verbatim
00520   ==============================================================================
00521                       ##### IO operation functions #####
00522   ==============================================================================
00523     [..]  This section provides functions allowing to:
00524       (+) Transmit a CAN frame message.
00525       (+) Receive a CAN frame message.
00526       (+) Enter CAN peripheral in sleep mode.
00527       (+) Wake up the CAN peripheral from sleep mode.
00528
00529 @endverbatim
00530   * @{
00531   */
00532
00533 /**
00534   * @brief  Initiates and transmits a CAN frame message.
00535   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
00536   *         the configuration information for the specified CAN.
00537   * @param  Timeout Timeout duration.
00538   * @retval HAL status
00539   */
00540 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
00541 {
00542   uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
00543   uint32_t tickstart = 0U;
00544
00545   /* Check the parameters */
00546   assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
00547   assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
00548   assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
00549
00550   if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
00551      ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
00552      ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
00553   {
00554     /* Process locked */
00555     __HAL_LOCK(hcan);
00556
00557     /* Change CAN state */
00558     switch(hcan->State)
00559     {
00560       case(HAL_CAN_STATE_BUSY_RX0):
00561           hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
00562           break;
00563       case(HAL_CAN_STATE_BUSY_RX1):
00564           hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
00565           break;
00566       case(HAL_CAN_STATE_BUSY_RX0_RX1):
00567           hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
00568           break;
00569       default: /* HAL_CAN_STATE_READY */
00570           hcan->State = HAL_CAN_STATE_BUSY_TX;
00571           break;
00572     }
00573
00574     /* Select one empty transmit mailbox */
00575     if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
00576     {
00577       transmitmailbox = CAN_TXMAILBOX_0;
00578     }
00579     else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
00580     {
00581       transmitmailbox = CAN_TXMAILBOX_1;
00582     }
00583     else
00584     {
00585       transmitmailbox = CAN_TXMAILBOX_2;
00586     }
00587
00588     /* Set up the Id */
00589     hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
00590     if (hcan->pTxMsg->IDE == CAN_ID_STD)
00591     {
00592       assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
00593       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
00594                                                            hcan->pTxMsg->RTR);
00595     }
00596     else
00597     {
00598       assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
00599       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
00600                                                            hcan->pTxMsg->IDE | \
00601                                                            hcan->pTxMsg->RTR);
00602     }
00603
00604     /* Set up the DLC */
00605     hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
00606     hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
00607     hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
00608
00609     /* Set up the data field */
00610     WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
00611                                                                 ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
00612                                                                 ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
00613                                                                 ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
00614     WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
00615                                                                 ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
00616                                                                 ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
00617                                                                 ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
00618
00619     /* Request transmission */
00620     SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
00621
00622     /* Get tick */
00623     tickstart = HAL_GetTick();
00624
00625     /* Check End of transmission flag */
00626     while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
00627     {
00628       /* Check for the Timeout */
00629       if(Timeout != HAL_MAX_DELAY)
00630       {
00631         if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
00632         {
00633           hcan->State = HAL_CAN_STATE_TIMEOUT;
00634
00635           /* Cancel transmission */
00636           __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
00637
00638           /* Process unlocked */
00639           __HAL_UNLOCK(hcan);
00640           return HAL_TIMEOUT;
00641         }
00642       }
00643     }
00644
00645     /* Change CAN state */
00646     switch(hcan->State)
00647     {
00648       case(HAL_CAN_STATE_BUSY_TX_RX0):
00649           hcan->State = HAL_CAN_STATE_BUSY_RX0;
00650           break;
00651       case(HAL_CAN_STATE_BUSY_TX_RX1):
00652           hcan->State = HAL_CAN_STATE_BUSY_RX1;
00653           break;
00654       case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
00655           hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
00656           break;
00657       default: /* HAL_CAN_STATE_BUSY_TX */
00658           hcan->State = HAL_CAN_STATE_READY;
00659           break;
00660     }
00661
00662     /* Process unlocked */
00663     __HAL_UNLOCK(hcan);
00664
00665     /* Return function status */
00666     return HAL_OK;
00667   }
00668   else
00669   {
00670     /* Change CAN state */
00671     hcan->State = HAL_CAN_STATE_ERROR;
00672
00673     /* Return function status */
00674     return HAL_ERROR;
00675   }
00676 }
00677
00678 /**
00679   * @brief  Initiates and transmits a CAN frame message.
00680   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
00681   *         the configuration information for the specified CAN.
00682   * @retval HAL status
00683   */
00684 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
00685 {
00686   uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
00687
00688   /* Check the parameters */
00689   assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
00690   assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
00691   assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
00692
00693   if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
00694      ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
00695      ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
00696   {
00697     /* Process Locked */
00698     __HAL_LOCK(hcan);
00699
00700     /* Select one empty transmit mailbox */
00701     if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
00702     {
00703       transmitmailbox = CAN_TXMAILBOX_0;
00704     }
00705     else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
00706     {
00707       transmitmailbox = CAN_TXMAILBOX_1;
00708     }
00709     else
00710     {
00711       transmitmailbox = CAN_TXMAILBOX_2;
00712     }
00713
00714     /* Set up the Id */
00715     hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
00716     if(hcan->pTxMsg->IDE == CAN_ID_STD)
00717     {
00718       assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
00719       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
00720                                                            hcan->pTxMsg->RTR);
00721     }
00722     else
00723     {
00724       assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
00725       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
00726                                                            hcan->pTxMsg->IDE |                         \
00727                                                            hcan->pTxMsg->RTR);
00728     }
00729
00730     /* Set up the DLC */
00731     hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
00732     hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
00733     hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
00734
00735     /* Set up the data field */
00736     WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
00737                                                                 ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
00738                                                                 ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
00739                                                                 ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
00740     WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
00741                                                                 ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
00742                                                                 ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
00743                                                                 ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
00744
00745     /* Change CAN state */
00746     switch(hcan->State)
00747     {
00748       case(HAL_CAN_STATE_BUSY_RX0):
00749           hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
00750           break;
00751       case(HAL_CAN_STATE_BUSY_RX1):
00752           hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
00753           break;
00754       case(HAL_CAN_STATE_BUSY_RX0_RX1):
00755           hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
00756           break;
00757       default: /* HAL_CAN_STATE_READY */
00758           hcan->State = HAL_CAN_STATE_BUSY_TX;
00759           break;
00760     }
00761
00762     /* Set CAN error code to none */
00763     hcan->ErrorCode = HAL_CAN_ERROR_NONE;
00764
00765     /* Process Unlocked */
00766     __HAL_UNLOCK(hcan);
00767
00768     /* Request transmission */
00769     hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
00770
00771     /* Enable interrupts: */
00772     /*  - Enable Error warning Interrupt */
00773     /*  - Enable Error passive Interrupt */
00774     /*  - Enable Bus-off Interrupt */
00775     /*  - Enable Last error code Interrupt */
00776     /*  - Enable Error Interrupt */
00777     /*  - Enable Transmit mailbox empty Interrupt */
00778     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
00779                               CAN_IT_EPV |
00780                               CAN_IT_BOF |
00781                               CAN_IT_LEC |
00782                               CAN_IT_ERR |
00783                               CAN_IT_TME  );
00784   }
00785   else
00786   {
00787     /* Change CAN state */
00788     hcan->State = HAL_CAN_STATE_ERROR;
00789
00790     /* Return function status */
00791     return HAL_ERROR;
00792   }
00793
00794   return HAL_OK;
00795 }
00796
00797 /**
00798   * @brief  Receives a correct CAN frame.
00799   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
00800   *         the configuration information for the specified CAN.
00801   * @param  FIFONumber    FIFO number.
00802   * @param  Timeout       Timeout duration.
00803   * @retval HAL status
00804   */
00805 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
00806 {
00807   uint32_t tickstart = 0U;
00808   CanRxMsgTypeDef* pRxMsg = NULL;
00809
00810   /* Check the parameters */
00811   assert_param(IS_CAN_FIFO(FIFONumber));
00812
00813   /* Process locked */
00814   __HAL_LOCK(hcan);
00815
00816   /* Check if CAN state is not busy for RX FIFO0 */
00817   if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) ||         \
00818                                     (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) ||      \
00819                                     (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) ||     \
00820                                     (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
00821   {
00822     /* Process unlocked */
00823     __HAL_UNLOCK(hcan);
00824
00825     return HAL_BUSY;
00826   }
00827
00828   /* Check if CAN state is not busy for RX FIFO1 */
00829   if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) ||         \
00830                                     (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) ||      \
00831                                     (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) ||     \
00832                                     (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
00833   {
00834     /* Process unlocked */
00835     __HAL_UNLOCK(hcan);
00836
00837     return HAL_BUSY;
00838   }
00839
00840   /* Change CAN state */
00841   if (FIFONumber == CAN_FIFO0)
00842   {
00843     switch(hcan->State)
00844     {
00845       case(HAL_CAN_STATE_BUSY_TX):
00846         hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
00847         break;
00848       case(HAL_CAN_STATE_BUSY_RX1):
00849         hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
00850         break;
00851       case(HAL_CAN_STATE_BUSY_TX_RX1):
00852         hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
00853         break;
00854       default: /* HAL_CAN_STATE_READY */
00855         hcan->State = HAL_CAN_STATE_BUSY_RX0;
00856         break;
00857     }
00858   }
00859   else /* FIFONumber == CAN_FIFO1 */
00860   {
00861     switch(hcan->State)
00862     {
00863       case(HAL_CAN_STATE_BUSY_TX):
00864         hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
00865         break;
00866       case(HAL_CAN_STATE_BUSY_RX0):
00867         hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
00868         break;
00869       case(HAL_CAN_STATE_BUSY_TX_RX0):
00870         hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
00871         break;
00872       default: /* HAL_CAN_STATE_READY */
00873         hcan->State = HAL_CAN_STATE_BUSY_RX1;
00874         break;
00875     }
00876   }
00877
00878   /* Get tick */
00879   tickstart = HAL_GetTick();
00880
00881   /* Check pending message */
00882   while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
00883   {
00884     /* Check for the Timeout */
00885     if(Timeout != HAL_MAX_DELAY)
00886     {
00887       if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
00888       {
00889         hcan->State = HAL_CAN_STATE_TIMEOUT;
00890
00891         /* Process unlocked */
00892         __HAL_UNLOCK(hcan);
00893
00894         return HAL_TIMEOUT;
00895       }
00896     }
00897   }
00898
00899   /* Set RxMsg pointer */
00900   if(FIFONumber == CAN_FIFO0)
00901   {
00902     pRxMsg = hcan->pRxMsg;
00903   }
00904   else /* FIFONumber == CAN_FIFO1 */
00905   {
00906     pRxMsg = hcan->pRx1Msg;
00907   }
00908
00909   /* Get the Id */
00910   pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
00911   if (pRxMsg->IDE == CAN_ID_STD)
00912   {
00913     pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos;
00914   }
00915   else
00916   {
00917     pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos;
00918   }
00919   pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos;
00920   /* Get the DLC */
00921   pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos;
00922   /* Get the FMI */
00923   pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos;
00924   /* Get the FIFONumber */
00925   pRxMsg->FIFONumber = FIFONumber;
00926   /* Get the data field */
00927   pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos;
00928   pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos;
00929   pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos;
00930   pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos;
00931   pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos;
00932   pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos;
00933   pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos;
00934   pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos;
00935
00936   /* Release the FIFO */
00937   if(FIFONumber == CAN_FIFO0)
00938   {
00939     /* Release FIFO0 */
00940     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
00941   }
00942   else /* FIFONumber == CAN_FIFO1 */
00943   {
00944     /* Release FIFO1 */
00945     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
00946   }
00947
00948   /* Change CAN state */
00949   if (FIFONumber == CAN_FIFO0)
00950   {
00951     switch(hcan->State)
00952     {
00953       case(HAL_CAN_STATE_BUSY_TX_RX0):
00954         hcan->State = HAL_CAN_STATE_BUSY_TX;
00955         break;
00956       case(HAL_CAN_STATE_BUSY_RX0_RX1):
00957         hcan->State = HAL_CAN_STATE_BUSY_RX1;
00958         break;
00959       case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
00960         hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
00961         break;
00962       default: /* HAL_CAN_STATE_BUSY_RX0 */
00963         hcan->State = HAL_CAN_STATE_READY;
00964         break;
00965     }
00966   }
00967   else /* FIFONumber == CAN_FIFO1 */
00968   {
00969     switch(hcan->State)
00970     {
00971       case(HAL_CAN_STATE_BUSY_TX_RX1):
00972         hcan->State = HAL_CAN_STATE_BUSY_TX;
00973         break;
00974       case(HAL_CAN_STATE_BUSY_RX0_RX1):
00975         hcan->State = HAL_CAN_STATE_BUSY_RX0;
00976         break;
00977       case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
00978         hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
00979         break;
00980       default: /* HAL_CAN_STATE_BUSY_RX1 */
00981         hcan->State = HAL_CAN_STATE_READY;
00982         break;
00983     }
00984   }
00985
00986   /* Process unlocked */
00987   __HAL_UNLOCK(hcan);
00988
00989   /* Return function status */
00990   return HAL_OK;
00991 }
00992
00993 /**
00994   * @brief  Receives a correct CAN frame.
00995   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
00996   *         the configuration information for the specified CAN.
00997   * @param  FIFONumber    FIFO number.
00998   * @retval HAL status
00999   */
01000 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
01001 {
01002   /* Check the parameters */
01003   assert_param(IS_CAN_FIFO(FIFONumber));
01004
01005   /* Process locked */
01006   __HAL_LOCK(hcan);
01007
01008   /* Check if CAN state is not busy for RX FIFO0 */
01009   if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) ||        \
01010                                     (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) ||      \
01011                                     (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) ||     \
01012                                     (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
01013   {
01014     /* Process unlocked */
01015     __HAL_UNLOCK(hcan);
01016
01017     return HAL_BUSY;
01018   }
01019
01020   /* Check if CAN state is not busy for RX FIFO1 */
01021   if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) ||        \
01022                                     (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) ||      \
01023                                     (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) ||     \
01024                                     (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
01025   {
01026     /* Process unlocked */
01027     __HAL_UNLOCK(hcan);
01028
01029     return HAL_BUSY;
01030   }
01031
01032   /* Change CAN state */
01033   if (FIFONumber == CAN_FIFO0)
01034   {
01035     switch(hcan->State)
01036     {
01037       case(HAL_CAN_STATE_BUSY_TX):
01038         hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
01039         break;
01040       case(HAL_CAN_STATE_BUSY_RX1):
01041         hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
01042         break;
01043       case(HAL_CAN_STATE_BUSY_TX_RX1):
01044         hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
01045         break;
01046       default: /* HAL_CAN_STATE_READY */
01047         hcan->State = HAL_CAN_STATE_BUSY_RX0;
01048         break;
01049     }
01050   }
01051   else /* FIFONumber == CAN_FIFO1 */
01052   {
01053     switch(hcan->State)
01054     {
01055       case(HAL_CAN_STATE_BUSY_TX):
01056         hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
01057         break;
01058       case(HAL_CAN_STATE_BUSY_RX0):
01059         hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
01060         break;
01061       case(HAL_CAN_STATE_BUSY_TX_RX0):
01062         hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
01063         break;
01064       default: /* HAL_CAN_STATE_READY */
01065         hcan->State = HAL_CAN_STATE_BUSY_RX1;
01066         break;
01067     }
01068   }
01069
01070   /* Set CAN error code to none */
01071   hcan->ErrorCode = HAL_CAN_ERROR_NONE;
01072
01073   /* Enable interrupts: */
01074   /*  - Enable Error warning Interrupt */
01075   /*  - Enable Error passive Interrupt */
01076   /*  - Enable Bus-off Interrupt */
01077   /*  - Enable Last error code Interrupt */
01078   /*  - Enable Error Interrupt */
01079   __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
01080                             CAN_IT_EPV |
01081                             CAN_IT_BOF |
01082                             CAN_IT_LEC |
01083                             CAN_IT_ERR);
01084
01085   /* Process unlocked */
01086   __HAL_UNLOCK(hcan);
01087
01088   if(FIFONumber == CAN_FIFO0)
01089   {
01090     /* Enable FIFO 0 overrun and message pending Interrupt */
01091     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
01092   }
01093   else
01094   {
01095     /* Enable FIFO 1 overrun and message pending Interrupt */
01096     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
01097   }
01098
01099   /* Return function status */
01100   return HAL_OK;
01101 }
01102
01103 /**
01104   * @brief  Enters the Sleep (low power) mode.
01105   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
01106   *         the configuration information for the specified CAN.
01107   * @retval HAL status.
01108   */
01109 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
01110 {
01111   uint32_t tickstart = 0U;
01112
01113   /* Process locked */
01114   __HAL_LOCK(hcan);
01115
01116   /* Change CAN state */
01117   hcan->State = HAL_CAN_STATE_BUSY;
01118
01119   /* Request Sleep mode */
01120   MODIFY_REG(hcan->Instance->MCR,
01121              CAN_MCR_INRQ       ,
01122              CAN_MCR_SLEEP       );
01123
01124   /* Sleep mode status */
01125   if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
01126       HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)   )
01127   {
01128     /* Process unlocked */
01129     __HAL_UNLOCK(hcan);
01130
01131     /* Return function status */
01132     return HAL_ERROR;
01133   }
01134
01135   /* Get tick */
01136   tickstart = HAL_GetTick();
01137
01138   /* Wait the acknowledge */
01139   while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
01140          HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)   )
01141   {
01142     if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
01143     {
01144       hcan->State = HAL_CAN_STATE_TIMEOUT;
01145       /* Process unlocked */
01146       __HAL_UNLOCK(hcan);
01147       return HAL_TIMEOUT;
01148     }
01149   }
01150
01151   /* Change CAN state */
01152   hcan->State = HAL_CAN_STATE_READY;
01153
01154   /* Process unlocked */
01155   __HAL_UNLOCK(hcan);
01156
01157   /* Return function status */
01158   return HAL_OK;
01159 }
01160
01161 /**
01162   * @brief  Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
01163   *         is in the normal mode.
01164   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
01165   *         the configuration information for the specified CAN.
01166   * @retval HAL status.
01167   */
01168 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
01169 {
01170   uint32_t tickstart = 0U;
01171
01172   /* Process locked */
01173   __HAL_LOCK(hcan);
01174
01175   /* Change CAN state */
01176   hcan->State = HAL_CAN_STATE_BUSY;
01177
01178   /* Wake up request */
01179   CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
01180
01181   /* Get tick */
01182   tickstart = HAL_GetTick();
01183
01184   /* Sleep mode status */
01185   while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
01186   {
01187     if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
01188     {
01189       hcan->State= HAL_CAN_STATE_TIMEOUT;
01190
01191       /* Process unlocked */
01192       __HAL_UNLOCK(hcan);
01193
01194       return HAL_TIMEOUT;
01195     }
01196   }
01197
01198   if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
01199   {
01200     /* Process unlocked */
01201     __HAL_UNLOCK(hcan);
01202
01203     /* Return function status */
01204     return HAL_ERROR;
01205   }
01206
01207   /* Change CAN state */
01208   hcan->State = HAL_CAN_STATE_READY;
01209
01210   /* Process unlocked */
01211   __HAL_UNLOCK(hcan);
01212
01213   /* Return function status */
01214   return HAL_OK;
01215 }
01216
01217 /**
01218   * @brief  Handles CAN interrupt request
01219   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
01220   *         the configuration information for the specified CAN.
01221   * @retval None
01222   */
01223 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
01224 {
01225   uint32_t errorcode = HAL_CAN_ERROR_NONE;
01226
01227   /* Check Overrun flag for FIFO0 */
01228   if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0))    &&
01229      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0)))
01230   {
01231     /* Set CAN error code to FOV0 error */
01232     errorcode |= HAL_CAN_ERROR_FOV0;
01233
01234     /* Clear FIFO0 Overrun Flag */
01235     __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
01236   }
01237
01238   /* Check Overrun flag for FIFO1 */
01239   if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1))    &&
01240      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1)))
01241   {
01242     /* Set CAN error code to FOV1 error */
01243     errorcode |= HAL_CAN_ERROR_FOV1;
01244
01245     /* Clear FIFO1 Overrun Flag */
01246     __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
01247   }
01248
01249   /* Check End of transmission flag */
01250   if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
01251   {
01252     /* Check Transmit request completion status */
01253     if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) ||
01254        (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) ||
01255        (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2)))
01256     {
01257       /* Check Transmit success */
01258       if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0)) ||
01259          (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1)) ||
01260          (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2)))
01261       {
01262         /* Call transmit function */
01263         CAN_Transmit_IT(hcan);
01264       }
01265       else /* Transmit failure */
01266       {
01267         /* Set CAN error code to TXFAIL error */
01268         errorcode |= HAL_CAN_ERROR_TXFAIL;
01269       }
01270
01271       /* Clear transmission status flags (RQCPx and TXOKx) */
01272       SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0  | CAN_TSR_RQCP1  | CAN_TSR_RQCP2 | \
01273                                    CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
01274     }
01275   }
01276
01277   /* Check End of reception flag for FIFO0 */
01278   if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) &&
01279      (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0U))
01280   {
01281     /* Call receive function */
01282     CAN_Receive_IT(hcan, CAN_FIFO0);
01283   }
01284
01285   /* Check End of reception flag for FIFO1 */
01286   if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) &&
01287      (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0U))
01288   {
01289     /* Call receive function */
01290     CAN_Receive_IT(hcan, CAN_FIFO1);
01291   }
01292
01293   /* Set error code in handle */
01294   hcan->ErrorCode |= errorcode;
01295
01296   /* Check Error Warning Flag */
01297   if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG))    &&
01298      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
01299      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
01300   {
01301     /* Set CAN error code to EWG error */
01302     hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
01303     /* No need for clear of Error Warning Flag as read-only */
01304   }
01305
01306   /* Check Error Passive Flag */
01307   if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV))    &&
01308      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) &&
01309      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
01310   {
01311     /* Set CAN error code to EPV error */
01312     hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
01313     /* No need for clear of Error Passive Flag as read-only */
01314   }
01315
01316   /* Check Bus-Off Flag */
01317   if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF))    &&
01318      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) &&
01319      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
01320   {
01321     /* Set CAN error code to BOF error */
01322     hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
01323     /* No need for clear of Bus-Off Flag as read-only */
01324   }
01325
01326   /* Check Last error code Flag */
01327   if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) &&
01328      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC))         &&
01329      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
01330   {
01331     switch(hcan->Instance->ESR & CAN_ESR_LEC)
01332     {
01333       case(CAN_ESR_LEC_0):
01334           /* Set CAN error code to STF error */
01335           hcan->ErrorCode |= HAL_CAN_ERROR_STF;
01336           break;
01337       case(CAN_ESR_LEC_1):
01338           /* Set CAN error code to FOR error */
01339           hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
01340           break;
01341       case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
01342           /* Set CAN error code to ACK error */
01343           hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
01344           break;
01345       case(CAN_ESR_LEC_2):
01346           /* Set CAN error code to BR error */
01347           hcan->ErrorCode |= HAL_CAN_ERROR_BR;
01348           break;
01349       case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
01350           /* Set CAN error code to BD error */
01351           hcan->ErrorCode |= HAL_CAN_ERROR_BD;
01352           break;
01353       case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
01354           /* Set CAN error code to CRC error */
01355           hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
01356           break;
01357       default:
01358           break;
01359     }
01360
01361     /* Clear Last error code Flag */
01362     CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
01363   }
01364
01365   /* Call the Error call Back in case of Errors */
01366   if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
01367   {
01368     /* Clear ERRI Flag */
01369     SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI);
01370
01371     /* Set the CAN state ready to be able to start again the process */
01372     hcan->State = HAL_CAN_STATE_READY;
01373
01374     /* Disable interrupts: */
01375     /*  - Disable Error warning Interrupt */
01376     /*  - Disable Error passive Interrupt */
01377     /*  - Disable Bus-off Interrupt */
01378     /*  - Disable Last error code Interrupt */
01379     /*  - Disable Error Interrupt */
01380     /*  - Disable FIFO 0 message pending Interrupt */
01381     /*  - Disable FIFO 0 Overrun Interrupt */
01382     /*  - Disable FIFO 1 message pending Interrupt */
01383     /*  - Disable FIFO 1 Overrun Interrupt */
01384     /*  - Disable Transmit mailbox empty Interrupt */
01385     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
01386                                CAN_IT_EPV |
01387                                CAN_IT_BOF |
01388                                CAN_IT_LEC |
01389                                CAN_IT_ERR |
01390                                CAN_IT_FMP0|
01391                                CAN_IT_FOV0|
01392                                CAN_IT_FMP1|
01393                                CAN_IT_FOV1|
01394                                CAN_IT_TME  );
01395
01396     /* Call Error callback function */
01397     HAL_CAN_ErrorCallback(hcan);
01398   }
01399 }
01400
01401 /**
01402   * @brief  Transmission  complete callback in non blocking mode
01403   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
01404   *         the configuration information for the specified CAN.
01405   * @retval None
01406   */
01407 __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
01408 {
01409   /* Prevent unused argument(s) compilation warning */
01410   UNUSED(hcan);
01411
01412   /* NOTE : This function Should not be modified, when the callback is needed,
01413             the HAL_CAN_TxCpltCallback could be implemented in the user file
01414    */
01415 }
01416
01417 /**
01418   * @brief  Transmission  complete callback in non blocking mode
01419   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
01420   *         the configuration information for the specified CAN.
01421   * @retval None
01422   */
01423 __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
01424 {
01425   /* Prevent unused argument(s) compilation warning */
01426   UNUSED(hcan);
01427
01428   /* NOTE : This function Should not be modified, when the callback is needed,
01429             the HAL_CAN_RxCpltCallback could be implemented in the user file
01430    */
01431 }
01432
01433 /**
01434   * @brief  Error CAN callback.
01435   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
01436   *         the configuration information for the specified CAN.
01437   * @retval None
01438   */
01439 __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
01440 {
01441   /* Prevent unused argument(s) compilation warning */
01442   UNUSED(hcan);
01443
01444   /* NOTE : This function Should not be modified, when the callback is needed,
01445             the HAL_CAN_ErrorCallback could be implemented in the user file
01446    */
01447 }
01448
01449 /**
01450   * @}
01451   */
01452
01453 /** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
01454  *  @brief   CAN Peripheral State functions
01455  *
01456 @verbatim
01457   ==============================================================================
01458             ##### Peripheral State and Error functions #####
01459   ==============================================================================
01460     [..]
01461     This subsection provides functions allowing to :
01462       (+) Check the CAN state.
01463       (+) Check CAN Errors detected during interrupt process
01464
01465 @endverbatim
01466   * @{
01467   */
01468
01469 /**
01470   * @brief  return the CAN state
01471   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
01472   *         the configuration information for the specified CAN.
01473   * @retval HAL state
01474   */
01475 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
01476 {
01477   /* Return CAN state */
01478   return hcan->State;
01479 }
01480
01481 /**
01482   * @brief  Return the CAN error code
01483   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
01484   *         the configuration information for the specified CAN.
01485   * @retval CAN Error Code
01486   */
01487 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
01488 {
01489   return hcan->ErrorCode;
01490 }
01491
01492 /**
01493   * @}
01494   */
01495
01496 /**
01497   * @}
01498   */
01499
01500 /** @addtogroup CAN_Private_Functions CAN Private Functions
01501  *  @brief    CAN Frame message Rx/Tx functions
01502  *
01503  * @{
01504  */
01505
01506 /**
01507   * @brief  Initiates and transmits a CAN frame message.
01508   * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
01509   *         the configuration information for the specified CAN.
01510   * @retval HAL status
01511   */
01512 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
01513 {
01514   /* Disable Transmit mailbox empty Interrupt */
01515   __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
01516
01517   if(hcan->State == HAL_CAN_STATE_BUSY_TX)
01518   {
01519     /* Disable interrupts: */
01520     /*  - Disable Error warning Interrupt */
01521     /*  - Disable Error passive Interrupt */
01522     /*  - Disable Bus-off Interrupt */
01523     /*  - Disable Last error code Interrupt */
01524     /*  - Disable Error Interrupt */
01525     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
01526                                CAN_IT_EPV |
01527                                CAN_IT_BOF |
01528                                CAN_IT_LEC |
01529                                CAN_IT_ERR );
01530   }
01531
01532   /* Change CAN state */
01533   switch(hcan->State)
01534   {
01535     case(HAL_CAN_STATE_BUSY_TX_RX0):
01536       hcan->State = HAL_CAN_STATE_BUSY_RX0;
01537       break;
01538     case(HAL_CAN_STATE_BUSY_TX_RX1):
01539       hcan->State = HAL_CAN_STATE_BUSY_RX1;
01540       break;
01541     case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
01542       hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
01543       break;
01544     default: /* HAL_CAN_STATE_BUSY_TX */
01545       hcan->State = HAL_CAN_STATE_READY;
01546       break;
01547   }
01548
01549   /* Transmission complete callback */
01550   HAL_CAN_TxCpltCallback(hcan);
01551
01552   return HAL_OK;
01553 }
01554
01555 /**
01556   * @brief  Receives a correct CAN frame.
01557   * @param  hcan       Pointer to a CAN_HandleTypeDef structure that contains
01558   *         the configuration information for the specified CAN.
01559   * @param  FIFONumber Specify the FIFO number
01560   * @retval HAL status
01561   * @retval None
01562   */
01563 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
01564 {
01565   CanRxMsgTypeDef* pRxMsg = NULL;
01566
01567   /* Set RxMsg pointer */
01568   if(FIFONumber == CAN_FIFO0)
01569   {
01570     pRxMsg = hcan->pRxMsg;
01571   }
01572   else /* FIFONumber == CAN_FIFO1 */
01573   {
01574     pRxMsg = hcan->pRx1Msg;
01575   }
01576
01577   /* Get the Id */
01578   pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
01579   if (pRxMsg->IDE == CAN_ID_STD)
01580   {
01581     pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos;
01582   }
01583   else
01584   {
01585     pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos;
01586   }
01587   pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos;
01588   /* Get the DLC */
01589   pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos;
01590   /* Get the FMI */
01591   pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos;
01592   /* Get the FIFONumber */
01593   pRxMsg->FIFONumber = FIFONumber;
01594   /* Get the data field */
01595   pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos;
01596   pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos;
01597   pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos;
01598   pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos;
01599   pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos;
01600   pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos;
01601   pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos;
01602   pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos;
01603
01604   /* Release the FIFO */
01605   /* Release FIFO0 */
01606   if (FIFONumber == CAN_FIFO0)
01607   {
01608     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
01609
01610     /* Disable FIFO 0 overrun and message pending Interrupt */
01611     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
01612   }
01613   /* Release FIFO1 */
01614   else /* FIFONumber == CAN_FIFO1 */
01615   {
01616     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
01617
01618     /* Disable FIFO 1 overrun and message pending Interrupt */
01619     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
01620   }
01621
01622   if((hcan->State == HAL_CAN_STATE_BUSY_RX0) || (hcan->State == HAL_CAN_STATE_BUSY_RX1))
01623   {
01624     /* Disable interrupts: */
01625     /*  - Disable Error warning Interrupt */
01626     /*  - Disable Error passive Interrupt */
01627     /*  - Disable Bus-off Interrupt */
01628     /*  - Disable Last error code Interrupt */
01629     /*  - Disable Error Interrupt */
01630     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
01631                                CAN_IT_EPV |
01632                                CAN_IT_BOF |
01633                                CAN_IT_LEC |
01634                                CAN_IT_ERR );
01635   }
01636
01637   /* Change CAN state */
01638   if (FIFONumber == CAN_FIFO0)
01639   {
01640     switch(hcan->State)
01641     {
01642       case(HAL_CAN_STATE_BUSY_TX_RX0):
01643         hcan->State = HAL_CAN_STATE_BUSY_TX;
01644         break;
01645       case(HAL_CAN_STATE_BUSY_RX0_RX1):
01646         hcan->State = HAL_CAN_STATE_BUSY_RX1;
01647         break;
01648       case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
01649         hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
01650         break;
01651       default: /* HAL_CAN_STATE_BUSY_RX0 */
01652         hcan->State = HAL_CAN_STATE_READY;
01653         break;
01654     }
01655   }
01656   else /* FIFONumber == CAN_FIFO1 */
01657   {
01658     switch(hcan->State)
01659     {
01660       case(HAL_CAN_STATE_BUSY_TX_RX1):
01661         hcan->State = HAL_CAN_STATE_BUSY_TX;
01662         break;
01663       case(HAL_CAN_STATE_BUSY_RX0_RX1):
01664         hcan->State = HAL_CAN_STATE_BUSY_RX0;
01665         break;
01666       case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
01667         hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
01668         break;
01669       default: /* HAL_CAN_STATE_BUSY_RX1 */
01670         hcan->State = HAL_CAN_STATE_READY;
01671         break;
01672     }
01673   }
01674
01675   /* Receive complete callback */
01676   HAL_CAN_RxCpltCallback(hcan);
01677
01678   /* Return function status */
01679   return HAL_OK;
01680 }
01681
01682 /**
01683   * @}
01684   */
01685 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
01686        /* STM32F302xC || STM32F303xC || STM32F358xx || */
01687        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
01688        /* STM32F302x8                               || */
01689        /* STM32F373xC || STM32F378xx                   */
01690
01691 #endif /* HAL_CAN_MODULE_ENABLED */
01692 /**
01693   * @}
01694   */
01695
01696 /**
01697   * @}
01698   */
01699
01700 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_can.h Source File

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stm32f3xx_hal_can.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_can.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CAN HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_CAN_H
00038 #define __STM32F3xx_CAN_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00045     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00046     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00047     defined(STM32F302x8)                                                 || \
00048     defined(STM32F373xC) || defined(STM32F378xx)
00049
00050 /* Includes ------------------------------------------------------------------*/
00051 #include "stm32f3xx_hal_def.h"
00052
00053 /** @addtogroup STM32F3xx_HAL_Driver
00054   * @{
00055   */
00056
00057 /** @addtogroup CAN
00058   * @{
00059   */
00060
00061 /* Exported types ------------------------------------------------------------*/
00062 /** @defgroup CAN_Exported_Types CAN Exported Types
00063   * @{
00064   */
00065 /**
00066   * @brief  HAL State structures definition
00067   */
00068 typedef enum
00069 {
00070   HAL_CAN_STATE_RESET             = 0x00U,  /*!< CAN not yet initialized or disabled */
00071   HAL_CAN_STATE_READY             = 0x01U,  /*!< CAN initialized and ready for use   */
00072   HAL_CAN_STATE_BUSY              = 0x02U,  /*!< CAN process is ongoing              */
00073   HAL_CAN_STATE_BUSY_TX           = 0x12U,  /*!< CAN process is ongoing              */
00074   HAL_CAN_STATE_BUSY_RX0          = 0x22U,  /*!< CAN process is ongoing              */
00075   HAL_CAN_STATE_BUSY_RX1          = 0x32U,  /*!< CAN process is ongoing              */
00076   HAL_CAN_STATE_BUSY_TX_RX0       = 0x42U,  /*!< CAN process is ongoing              */
00077   HAL_CAN_STATE_BUSY_TX_RX1       = 0x52U,  /*!< CAN process is ongoing              */
00078   HAL_CAN_STATE_BUSY_RX0_RX1      = 0x62U,  /*!< CAN process is ongoing              */
00079   HAL_CAN_STATE_BUSY_TX_RX0_RX1   = 0x72U,  /*!< CAN process is ongoing              */
00080   HAL_CAN_STATE_TIMEOUT           = 0x03U,  /*!< CAN in Timeout state                */
00081   HAL_CAN_STATE_ERROR             = 0x04U   /*!< CAN error state                     */
00082
00083 }HAL_CAN_StateTypeDef;
00084
00085 /**
00086   * @brief  CAN init structure definition
00087   */
00088 typedef struct
00089 {
00090   uint32_t Prescaler;  /*!< Specifies the length of a time quantum.
00091                             This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
00092
00093   uint32_t Mode;       /*!< Specifies the CAN operating mode.
00094                             This parameter can be a value of @ref CAN_operating_mode */
00095
00096   uint32_t SJW;        /*!< Specifies the maximum number of time quanta
00097                             the CAN hardware is allowed to lengthen or
00098                             shorten a bit to perform resynchronization.
00099                             This parameter can be a value of @ref CAN_synchronisation_jump_width */
00100
00101   uint32_t BS1;        /*!< Specifies the number of time quanta in Bit Segment 1.
00102                             This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
00103
00104   uint32_t BS2;        /*!< Specifies the number of time quanta in Bit Segment 2.
00105                             This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
00106
00107   uint32_t TTCM;       /*!< Enable or disable the time triggered communication mode.
00108                             This parameter can be set to ENABLE or DISABLE. */
00109
00110   uint32_t ABOM;       /*!< Enable or disable the automatic bus-off management.
00111                             This parameter can be set to ENABLE or DISABLE. */
00112
00113   uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode.
00114                             This parameter can be set to ENABLE or DISABLE. */
00115
00116   uint32_t NART;       /*!< Enable or disable the non-automatic retransmission mode.
00117                             This parameter can be set to ENABLE or DISABLE. */
00118
00119   uint32_t RFLM;       /*!< Enable or disable the Receive FIFO Locked mode.
00120                             This parameter can be set to ENABLE or DISABLE. */
00121
00122   uint32_t TXFP;       /*!< Enable or disable the transmit FIFO priority.
00123                             This parameter can be set to ENABLE or DISABLE. */
00124 }CAN_InitTypeDef;
00125
00126 /**
00127   * @brief  CAN filter configuration structure definition
00128   */
00129 typedef struct
00130 {
00131   uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit
00132                                        configuration, first one for a 16-bit configuration).
00133                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
00134
00135   uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit
00136                                        configuration, second one for a 16-bit configuration).
00137                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
00138
00139   uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,
00140                                        according to the mode (MSBs for a 32-bit configuration,
00141                                        first one for a 16-bit configuration).
00142                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
00143
00144   uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,
00145                                        according to the mode (LSBs for a 32-bit configuration,
00146                                        second one for a 16-bit configuration).
00147                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
00148
00149   uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
00150                                        This parameter can be a value of @ref CAN_filter_FIFO */
00151
00152   uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized.
00153                                        This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
00154
00155   uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.
00156                                        This parameter can be a value of @ref CAN_filter_mode */
00157
00158   uint32_t FilterScale;           /*!< Specifies the filter scale.
00159                                        This parameter can be a value of @ref CAN_filter_scale */
00160
00161   uint32_t FilterActivation;      /*!< Enable or disable the filter.
00162                                        This parameter can be set to ENABLE or DISABLE. */
00163
00164   uint32_t BankNumber;            /*!< Select the start slave bank filter
00165                                        F3 devices don't support CAN2 interface (Slave). Therefore this parameter
00166                                        is meaningless but it has been kept for compatibility accross STM32 families */
00167
00168 }CAN_FilterConfTypeDef;
00169
00170 /**
00171   * @brief  CAN Tx message structure definition
00172   */
00173 typedef struct
00174 {
00175   uint32_t StdId;    /*!< Specifies the standard identifier.
00176                           This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
00177
00178   uint32_t ExtId;    /*!< Specifies the extended identifier.
00179                           This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
00180
00181   uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
00182                           This parameter can be a value of @ref CAN_identifier_type */
00183
00184   uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
00185                           This parameter can be a value of @ref CAN_remote_transmission_request */
00186
00187   uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
00188                           This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
00189
00190   uint8_t Data[8];   /*!< Contains the data to be transmitted.
00191                           This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
00192
00193 }CanTxMsgTypeDef;
00194
00195 /**
00196   * @brief  CAN Rx message structure definition
00197   */
00198 typedef struct
00199 {
00200   uint32_t StdId;       /*!< Specifies the standard identifier.
00201                              This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
00202
00203   uint32_t ExtId;       /*!< Specifies the extended identifier.
00204                              This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
00205
00206   uint32_t IDE;         /*!< Specifies the type of identifier for the message that will be received.
00207                              This parameter can be a value of @ref CAN_identifier_type */
00208
00209   uint32_t RTR;         /*!< Specifies the type of frame for the received message.
00210                              This parameter can be a value of @ref CAN_remote_transmission_request */
00211
00212   uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
00213                              This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
00214
00215   uint8_t Data[8];      /*!< Contains the data to be received.
00216                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
00217
00218   uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
00219                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
00220
00221   uint32_t FIFONumber;  /*!< Specifies the receive FIFO number.
00222                              This parameter can be CAN_FIFO0 or CAN_FIFO1 */
00223
00224 }CanRxMsgTypeDef;
00225
00226 /**
00227   * @brief  CAN handle Structure definition
00228   */
00229 typedef struct
00230 {
00231   CAN_TypeDef                 *Instance;  /*!< Register base address          */
00232
00233   CAN_InitTypeDef             Init;       /*!< CAN required parameters        */
00234
00235   CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
00236
00237   CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure for RX FIFO0 msg */
00238
00239   CanRxMsgTypeDef*            pRx1Msg;    /*!< Pointer to reception structure for RX FIFO1 msg */
00240
00241   HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
00242
00243   __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */
00244
00245   __IO uint32_t               ErrorCode;  /*!< CAN Error code
00246                                                This parameter can be a value of @ref CAN_Error_Code */
00247
00248 }CAN_HandleTypeDef;
00249 /**
00250   * @}
00251   */
00252
00253 /* Exported constants --------------------------------------------------------*/
00254
00255 /** @defgroup CAN_Exported_Constants CAN Exported Constants
00256   * @{
00257   */
00258
00259 /** @defgroup CAN_Error_Code CAN Error Code
00260   * @{
00261   */
00262 #define HAL_CAN_ERROR_NONE          (0x00000000U)  /*!< No error             */
00263 #define HAL_CAN_ERROR_EWG           (0x00000001U)  /*!< EWG error            */
00264 #define HAL_CAN_ERROR_EPV           (0x00000002U)  /*!< EPV error            */
00265 #define HAL_CAN_ERROR_BOF           (0x00000004U)  /*!< BOF error            */
00266 #define HAL_CAN_ERROR_STF           (0x00000008U)  /*!< Stuff error          */
00267 #define HAL_CAN_ERROR_FOR           (0x00000010U)  /*!< Form error           */
00268 #define HAL_CAN_ERROR_ACK           (0x00000020U)  /*!< Acknowledgment error */
00269 #define HAL_CAN_ERROR_BR            (0x00000040U)  /*!< Bit recessive        */
00270 #define HAL_CAN_ERROR_BD            (0x00000080U)  /*!< LEC dominant         */
00271 #define HAL_CAN_ERROR_CRC           (0x00000100U)  /*!< LEC transfer error   */
00272 #define HAL_CAN_ERROR_FOV0          (0x00000200U)  /*!< FIFO0 overrun error  */
00273 #define HAL_CAN_ERROR_FOV1          (0x00000400U)  /*!< FIFO1 overrun error  */
00274 #define HAL_CAN_ERROR_TXFAIL        (0x00000800U)  /*!< Transmit failure     */
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup CAN_InitStatus CAN InitStatus
00280   * @{
00281   */
00282 #define CAN_INITSTATUS_FAILED       (0x00000000U)  /*!< CAN initialization failed */
00283 #define CAN_INITSTATUS_SUCCESS      (0x00000001U)  /*!< CAN initialization OK */
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup CAN_operating_mode CAN Operating Mode
00289   * @{
00290   */
00291 #define CAN_MODE_NORMAL             (0x00000000U)                              /*!< Normal mode   */
00292 #define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
00293 #define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
00294 #define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
00295 /**
00296   * @}
00297   */
00298
00299
00300 /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
00301   * @{
00302   */
00303 #define CAN_SJW_1TQ                 (0x00000000U)              /*!< 1 time quantum */
00304 #define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
00305 #define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
00306 #define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
00312   * @{
00313   */
00314 #define CAN_BS1_1TQ                 (0x00000000U)                                                /*!< 1 time quantum  */
00315 #define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
00316 #define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
00317 #define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
00318 #define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */
00319 #define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */
00320 #define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */
00321 #define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */
00322 #define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */
00323 #define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */
00324 #define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */
00325 #define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */
00326 #define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */
00327 #define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */
00328 #define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */
00329 #define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
00330 /**
00331   * @}
00332   */
00333
00334 /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
00335   * @{
00336   */
00337 #define CAN_BS2_1TQ                 (0x00000000U)                                /*!< 1 time quantum */
00338 #define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
00339 #define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
00340 #define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
00341 #define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */
00342 #define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */
00343 #define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */
00344 #define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup CAN_filter_mode CAN Filter Mode
00350   * @{
00351   */
00352 #define CAN_FILTERMODE_IDMASK       ((uint8_t)0x00U)  /*!< Identifier mask mode */
00353 #define CAN_FILTERMODE_IDLIST       ((uint8_t)0x01U)  /*!< Identifier list mode */
00354 /**
00355   * @}
00356   */
00357
00358 /** @defgroup CAN_filter_scale CAN Filter Scale
00359   * @{
00360   */
00361 #define CAN_FILTERSCALE_16BIT       ((uint8_t)0x00U)  /*!< Two 16-bit filters */
00362 #define CAN_FILTERSCALE_32BIT       ((uint8_t)0x01U)  /*!< One 32-bit filter  */
00363 /**
00364   * @}
00365   */
00366
00367 /** @defgroup CAN_filter_FIFO CAN Filter FIFO
00368   * @{
00369   */
00370 #define CAN_FILTER_FIFO0             ((uint8_t)0x00U)  /*!< Filter FIFO 0 assignment for filter x */
00371 #define CAN_FILTER_FIFO1             ((uint8_t)0x01U)  /*!< Filter FIFO 1 assignment for filter x */
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup CAN_identifier_type CAN Identifier Type
00377   * @{
00378   */
00379 #define CAN_ID_STD             (0x00000000U)  /*!< Standard Id */
00380 #define CAN_ID_EXT             (0x00000004U)  /*!< Extended Id */
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
00386   * @{
00387   */
00388 #define CAN_RTR_DATA                (0x00000000U)  /*!< Data frame */
00389 #define CAN_RTR_REMOTE              (0x00000002U)  /*!< Remote frame */
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
00395   * @{
00396   */
00397 #define CAN_FIFO0                   ((uint8_t)0x00U)  /*!< CAN FIFO 0 used to receive */
00398 #define CAN_FIFO1                   ((uint8_t)0x01U)  /*!< CAN FIFO 1 used to receive */
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup CAN_flags CAN Flags
00404   * @{
00405   */
00406 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
00407    and CAN_ClearFlag() functions. */
00408 /* If the flag is 0x1XXXXXXX, it means that it can only be used with
00409    CAN_GetFlagStatus() function.  */
00410
00411 /* Transmit Flags */
00412 #define CAN_FLAG_RQCP0             (0x00000500U)  /*!< Request MailBox0 flag         */
00413 #define CAN_FLAG_RQCP1             (0x00000508U)  /*!< Request MailBox1 flag         */
00414 #define CAN_FLAG_RQCP2             (0x00000510U)  /*!< Request MailBox2 flag         */
00415 #define CAN_FLAG_TXOK0             (0x00000501U)  /*!< Transmission OK MailBox0 flag */
00416 #define CAN_FLAG_TXOK1             (0x00000509U)  /*!< Transmission OK MailBox1 flag */
00417 #define CAN_FLAG_TXOK2             (0x00000511U)  /*!< Transmission OK MailBox2 flag */
00418 #define CAN_FLAG_TME0              (0x0000051AU)  /*!< Transmit mailbox 0 empty flag */
00419 #define CAN_FLAG_TME1              (0x0000051BU)  /*!< Transmit mailbox 0 empty flag */
00420 #define CAN_FLAG_TME2              (0x0000051CU)  /*!< Transmit mailbox 0 empty flag */
00421
00422 /* Receive Flags */
00423 #define CAN_FLAG_FF0               (0x00000203U)  /*!< FIFO 0 Full flag    */
00424 #define CAN_FLAG_FOV0              (0x00000204U)  /*!< FIFO 0 Overrun flag */
00425
00426 #define CAN_FLAG_FF1               (0x00000403U)  /*!< FIFO 1 Full flag    */
00427 #define CAN_FLAG_FOV1              (0x00000404U)  /*!< FIFO 1 Overrun flag */
00428
00429 /* Operating Mode Flags */
00430 #define CAN_FLAG_INAK              (0x00000100U)  /*!< Initialization acknowledge flag */
00431 #define CAN_FLAG_SLAK              (0x00000101U)  /*!< Sleep acknowledge flag          */
00432 #define CAN_FLAG_ERRI              (0x00000102U)  /*!< Error flag                      */
00433 #define CAN_FLAG_WKU               (0x00000103U)  /*!< Wake up flag                    */
00434 #define CAN_FLAG_SLAKI             (0x00000104U)  /*!< Sleep acknowledge flag          */
00435 /* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible.
00436          In this case the SLAK bit can be polled.*/
00437
00438 /* Error Flags */
00439 #define CAN_FLAG_EWG               (0x00000300U)  /*!< Error warning flag   */
00440 #define CAN_FLAG_EPV               (0x00000301U)  /*!< Error passive flag   */
00441 #define CAN_FLAG_BOF               (0x00000302U)  /*!< Bus-Off flag         */
00442
00443 /**
00444   * @}
00445   */
00446
00447
00448 /** @defgroup CAN_interrupts CAN Interrupts
00449   * @{
00450   */
00451 #define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
00452
00453 /* Receive Interrupts */
00454 #define CAN_IT_FMP0                 ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
00455 #define CAN_IT_FF0                  ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
00456 #define CAN_IT_FOV0                 ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
00457 #define CAN_IT_FMP1                 ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
00458 #define CAN_IT_FF1                  ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
00459 #define CAN_IT_FOV1                 ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
00460
00461 /* Operating Mode Interrupts */
00462 #define CAN_IT_WKU                  ((uint32_t)CAN_IER_WKUIE)  /*!< Wake-up interrupt           */
00463 #define CAN_IT_SLK                  ((uint32_t)CAN_IER_SLKIE)  /*!< Sleep acknowledge interrupt */
00464
00465 /* Error Interrupts */
00466 #define CAN_IT_EWG                  ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt   */
00467 #define CAN_IT_EPV                  ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt   */
00468 #define CAN_IT_BOF                  ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt         */
00469 #define CAN_IT_LEC                  ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
00470 #define CAN_IT_ERR                  ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt           */
00471
00472 /**
00473   * @}
00474   */
00475
00476 /** @defgroup CAN_Mailboxes CAN Mailboxes
00477 * @{
00478 */
00479 /* Mailboxes definition */
00480 #define CAN_TXMAILBOX_0   ((uint8_t)0x00U)
00481 #define CAN_TXMAILBOX_1   ((uint8_t)0x01U)
00482 #define CAN_TXMAILBOX_2   ((uint8_t)0x02U)
00483 /**
00484   * @}
00485   */
00486
00487 /**
00488   * @}
00489   */
00490
00491 /* Exported macros -----------------------------------------------------------*/
00492 /** @defgroup CAN_Exported_Macros CAN Exported Macros
00493   * @{
00494   */
00495
00496 /** @brief  Reset CAN handle state
00497   * @param  __HANDLE__ CAN handle.
00498   * @retval None
00499   */
00500 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
00501
00502 /**
00503   * @brief  Enable the specified CAN interrupts.
00504   * @param  __HANDLE__ CAN handle.
00505   * @param  __INTERRUPT__ CAN Interrupt
00506   * @retval None
00507   */
00508 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
00509
00510 /**
00511   * @brief  Disable the specified CAN interrupts.
00512   * @param  __HANDLE__ CAN handle.
00513   * @param  __INTERRUPT__ CAN Interrupt
00514   * @retval None
00515   */
00516 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
00517
00518 /**
00519   * @brief  Return the number of pending received messages.
00520   * @param  __HANDLE__ CAN handle.
00521   * @param  __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
00522   * @retval The number of pending message.
00523   */
00524 #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
00525 ((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U)))
00526
00527 /** @brief  Check whether the specified CAN flag is set or not.
00528   * @param  __HANDLE__ specifies the CAN Handle.
00529   * @param  __FLAG__ specifies the flag to check.
00530   *         This parameter can be one of the following values:
00531   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
00532   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
00533   *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
00534   *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
00535   *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
00536   *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
00537   *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
00538   *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
00539   *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
00540   *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
00541   *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
00542   *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
00543   *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
00544   *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
00545   *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
00546   *            @arg CAN_FLAG_WKU: Wake up Flag
00547   *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
00548   *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
00549   *            @arg CAN_FLAG_EWG: Error Warning Flag
00550   *            @arg CAN_FLAG_EPV: Error Passive Flag
00551   *            @arg CAN_FLAG_BOF: Bus-Off Flag
00552   * @retval The new state of __FLAG__ (TRUE or FALSE).
00553   */
00554 #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
00555 ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00556  (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00557  (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00558  (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00559  ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
00560
00561 /** @brief  Clear the specified CAN pending flag.
00562   * @param  __HANDLE__ specifies the CAN Handle.
00563   * @param  __FLAG__ specifies the flag to check.
00564   *         This parameter can be one of the following values:
00565   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
00566   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
00567   *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
00568   *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
00569   *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
00570   *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
00571   *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
00572   *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
00573   *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
00574   *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
00575   *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
00576   *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
00577   *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
00578   *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
00579   *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
00580   *            @arg CAN_FLAG_WKU: Wake up Flag
00581   *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
00582   *            @arg CAN_FLAG_EWG: Error Warning Flag
00583   *            @arg CAN_FLAG_EPV: Error Passive Flag
00584   *            @arg CAN_FLAG_BOF: Bus-Off Flag
00585   * @retval The new state of __FLAG__ (TRUE or FALSE).
00586   */
00587 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
00588 ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00589  (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00590  (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00591  (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
00592
00593
00594 /** @brief  Check if the specified CAN interrupt source is enabled or disabled.
00595   * @param  __HANDLE__ specifies the CAN Handle.
00596   * @param  __INTERRUPT__ specifies the CAN interrupt source to check.
00597   *         This parameter can be one of the following values:
00598   *            @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
00599   *            @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
00600   *            @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
00601   * @retval The new state of __IT__ (TRUE or FALSE).
00602   */
00603 #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00604
00605 /**
00606   * @brief  Check the transmission status of a CAN Frame.
00607   * @param  __HANDLE__ CAN handle.
00608   * @param  __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
00609   * @retval The new status of transmission  (TRUE or FALSE).
00610   */
00611 #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
00612 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
00613  ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
00614  ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
00615
00616  /**
00617   * @brief  Release the specified receive FIFO.
00618   * @param  __HANDLE__ CAN handle.
00619   * @param  __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
00620   * @retval None
00621   */
00622 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
00623 ((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
00624
00625 /**
00626   * @brief  Cancel a transmit request.
00627   * @param  __HANDLE__ specifies the CAN Handle.
00628   * @param  __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
00629   * @retval None
00630   */
00631 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
00632 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
00633  ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
00634  ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
00635
00636 /**
00637   * @brief  Enable or disables the DBG Freeze for CAN.
00638   * @param  __HANDLE__ specifies the CAN Handle.
00639   * @param  __NEWSTATE__ new state of the CAN peripheral.
00640   *         This parameter can be: ENABLE (CAN reception/transmission is frozen
00641   *         during debug. Reception FIFOs can still be accessed/controlled normally)
00642   *         or DISABLE (CAN is working during debug).
00643   * @retval None
00644   */
00645 #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
00646 ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
00647
00648 /**
00649  * @}
00650  */
00651
00652 /* Exported functions --------------------------------------------------------*/
00653 /** @addtogroup CAN_Exported_Functions CAN Exported Functions
00654   * @{
00655   */
00656
00657 /** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
00658  *  @brief    Initialization and Configuration functions
00659  * @{
00660  */
00661
00662 /* Initialization and de-initialization functions *****************************/
00663 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
00664 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
00665 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
00666 void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
00667 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
00668 /**
00669  * @}
00670  */
00671
00672 /** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
00673  *  @brief    I/O operation functions
00674  * @{
00675  */
00676 /* IO operation functions *****************************************************/
00677 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
00678 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
00679 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
00680 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
00681 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
00682 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
00683 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
00684 void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
00685 void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
00686 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
00687 /**
00688  * @}
00689  */
00690
00691 /** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
00692  *  @brief   CAN Peripheral State functions
00693  * @{
00694  */
00695 /* Peripheral State and Error functions ***************************************/
00696 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
00697 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
00698 /**
00699  * @}
00700  */
00701
00702 /**
00703  * @}
00704  */
00705
00706 /* Private types -------------------------------------------------------------*/
00707 /** @defgroup CAN_Private_Types CAN Private Types
00708   * @{
00709   */
00710
00711 /**
00712   * @}
00713   */
00714
00715 /* Private variables ---------------------------------------------------------*/
00716 /** @defgroup CAN_Private_Variables CAN Private Variables
00717   * @{
00718   */
00719
00720 /**
00721   * @}
00722   */
00723
00724 /* Private constants ---------------------------------------------------------*/
00725 /** @defgroup CAN_Private_Constants CAN Private Constants
00726   * @{
00727   */
00728 #define CAN_TXSTATUS_NOMAILBOX      ((uint8_t)0x04U)  /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
00729 #define CAN_FLAG_MASK  (0x000000FFU)
00730 /**
00731   * @}
00732   */
00733
00734 /* Private Macros -----------------------------------------------------------*/
00735 /** @defgroup CAN_Private_Macros CAN Private Macros
00736   * @{
00737   */
00738
00739 #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
00740                            ((MODE) == CAN_MODE_LOOPBACK)|| \
00741                            ((MODE) == CAN_MODE_SILENT) || \
00742                            ((MODE) == CAN_MODE_SILENT_LOOPBACK))
00743
00744 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
00745                          ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
00746
00747 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
00748
00749 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
00750
00751 #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
00752
00753 #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
00754
00755 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
00756                                   ((MODE) == CAN_FILTERMODE_IDLIST))
00757
00758 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
00759                                     ((SCALE) == CAN_FILTERSCALE_32BIT))
00760
00761 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
00762                                   ((FIFO) == CAN_FILTER_FIFO1))
00763
00764 #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
00765
00766 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
00767 #define IS_CAN_STDID(STDID)   ((STDID) <= (0x7FFU))
00768 #define IS_CAN_EXTID(EXTID)   ((EXTID) <= (0x1FFFFFFFU))
00769 #define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08U))
00770
00771 #define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
00772                                 ((IDTYPE) == CAN_ID_EXT))
00773
00774 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
00775
00776 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
00777
00778 #define IS_CAN_IT(IT)        (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
00779                              ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
00780                              ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
00781                              ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
00782                              ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
00783                              ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
00784                              ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))
00785
00786 #define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
00787                              ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
00788                              ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
00789                              ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
00790                              ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
00791                              ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
00792
00793 /**
00794   * @}
00795   */
00796 /* End of private macros -----------------------------------------------------*/
00797
00798 /**
00799   * @}
00800   */
00801
00802 /**
00803   * @}
00804   */
00805
00806 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00807        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00808        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00809        /* STM32F302x8                               || */
00810        /* STM32F373xC || STM32F378xx                   */
00811
00812 #ifdef __cplusplus
00813 }
00814 #endif
00815
00816 #endif /* __STM32F3xx_CAN_H */
00817
00818
00819 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_cec.c Source File

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stm32f3xx_hal_cec.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_cec.c
00004   * @author  MCD Application Team
00005   * @brief   CEC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the High Definition Multimedia Interface
00008   *          Consumer Electronics Control Peripheral (CEC).
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral Control functions
00012   *
00013   *
00014   @verbatim
00015  ===============================================================================
00016                         ##### How to use this driver #####
00017  ===============================================================================
00018     [..]
00019     The CEC HAL driver can be used as follow:
00020
00021     (#) Declare a CEC_HandleTypeDef handle structure.
00022     (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
00023         (##) Enable the CEC interface clock.
00024         (##) CEC pins configuration:
00025             (+) Enable the clock for the CEC GPIOs.
00026             (+) Configure these CEC pins as alternate function pull-up.
00027         (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
00028              and HAL_CEC_Receive_IT() APIs):
00029             (+) Configure the CEC interrupt priority.
00030             (+) Enable the NVIC CEC IRQ handle.
00031             (@) The specific CEC interrupts (Transmission complete interrupt,
00032                 RXNE interrupt and Error Interrupts) will be managed using the macros
00033                 __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
00034                 and receive process.
00035
00036     (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
00037         in case of Bit Rising Error, Error-Bit generation conditions, device logical
00038         address and Listen mode in the hcec Init structure.
00039
00040     (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
00041
00042     (@) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00043         by calling the customed HAL_CEC_MspInit() API.
00044
00045   @endverbatim
00046   ******************************************************************************
00047   * @attention
00048   *
00049   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00050   *
00051   * Redistribution and use in source and binary forms, with or without modification,
00052   * are permitted provided that the following conditions are met:
00053   *   1. Redistributions of source code must retain the above copyright notice,
00054   *      this list of conditions and the following disclaimer.
00055   *   2. Redistributions in binary form must reproduce the above copyright notice,
00056   *      this list of conditions and the following disclaimer in the documentation
00057   *      and/or other materials provided with the distribution.
00058   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00059   *      may be used to endorse or promote products derived from this software
00060   *      without specific prior written permission.
00061   *
00062   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00063   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00064   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00065   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00066   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00067   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00068   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00069   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00070   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00071   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00072   *
00073   ******************************************************************************
00074   */
00075
00076 /* Includes ------------------------------------------------------------------*/
00077 #include "stm32f3xx_hal.h"
00078
00079 /** @addtogroup STM32F3xx_HAL_Driver
00080   * @{
00081   */
00082
00083 #ifdef HAL_CEC_MODULE_ENABLED
00084
00085 #if defined(STM32F373xC) || defined(STM32F378xx)
00086 /** @defgroup CEC CEC
00087   * @brief HAL CEC module driver
00088   * @{
00089   */
00090
00091 /* Private typedef -----------------------------------------------------------*/
00092 /* Private define ------------------------------------------------------------*/
00093 /** @defgroup CEC_Private_Constants CEC Private Constants
00094   * @{
00095   */
00096 /**
00097   * @}
00098   */
00099
00100 /* Private macro -------------------------------------------------------------*/
00101 /* Private variables ---------------------------------------------------------*/
00102 /* Private function prototypes -----------------------------------------------*/
00103 /** @defgroup CEC_Private_Functions CEC Private Functions
00104   * @{
00105   */
00106 /**
00107   * @}
00108   */
00109
00110 /* Exported functions ---------------------------------------------------------*/
00111
00112 /** @defgroup CEC_Exported_Functions CEC Exported Functions
00113   * @{
00114   */
00115
00116 /** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
00117   *  @brief    Initialization and Configuration functions
00118   *
00119 @verbatim
00120 ===============================================================================
00121             ##### Initialization and Configuration functions #####
00122  ===============================================================================
00123     [..]
00124     This subsection provides a set of functions allowing to initialize the CEC
00125       (+) The following parameters need to be configured:
00126         (++) SignalFreeTime
00127         (++) Tolerance
00128         (++) BRERxStop                 (RX stopped or not upon Bit Rising Error)
00129         (++) BREErrorBitGen            (Error-Bit generation in case of Bit Rising Error)
00130         (++) LBPEErrorBitGen           (Error-Bit generation in case of Long Bit Period Error)
00131         (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
00132         (++) SignalFreeTimeOption      (SFT Timer start definition)
00133         (++) OwnAddress                (CEC device address)
00134         (++) ListenMode
00135
00136 @endverbatim
00137   * @{
00138   */
00139
00140 /**
00141   * @brief Initializes the CEC mode according to the specified
00142   *         parameters in the CEC_InitTypeDef and creates the associated handle .
00143   * @param hcec CEC handle
00144   * @retval HAL status
00145   */
00146 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
00147 {
00148   /* Check the CEC handle allocation */
00149   if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
00150   {
00151     return HAL_ERROR;
00152   }
00153
00154   /* Check the parameters */
00155   assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
00156   assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
00157   assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
00158   assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
00159   assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
00160   assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
00161   assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
00162   assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
00163   assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
00164   assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
00165
00166   if(hcec->gState == HAL_CEC_STATE_RESET)
00167   {
00168     /* Allocate lock resource and initialize it */
00169     hcec->Lock = HAL_UNLOCKED;
00170     /* Init the low level hardware : GPIO, CLOCK */
00171     HAL_CEC_MspInit(hcec);
00172   }
00173   hcec->gState = HAL_CEC_STATE_BUSY;
00174
00175   /* Disable the Peripheral */
00176   __HAL_CEC_DISABLE(hcec);
00177
00178   /* Write to CEC Control Register */
00179   hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\
00180                          hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\
00181                          hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\
00182                          hcec->Init.ListenMode;
00183
00184   /* Enable the following CEC Transmission/Reception interrupts as
00185    * well as the following CEC Transmission/Reception Errors interrupts
00186    * Rx Byte Received IT
00187    * End of Reception IT
00188    * Rx overrun
00189    * Rx bit rising error
00190    * Rx short bit period error
00191    * Rx long bit period error
00192    * Rx missing acknowledge
00193    * Tx Byte Request IT
00194    * End of Transmission IT
00195    * Tx Missing Acknowledge IT
00196    * Tx-Error IT
00197    * Tx-Buffer Underrun IT
00198    * Tx arbitration lost   */
00199  __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
00200
00201   /* Enable the CEC Peripheral */
00202   __HAL_CEC_ENABLE(hcec);
00203
00204   hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00205   hcec->gState = HAL_CEC_STATE_READY;
00206   hcec->RxState = HAL_CEC_STATE_READY;
00207
00208   return HAL_OK;
00209 }
00210
00211 /**
00212   * @brief DeInitializes the CEC peripheral
00213   * @param hcec CEC handle
00214   * @retval HAL status
00215   */
00216 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
00217 {
00218   /* Check the CEC handle allocation */
00219   if(hcec == NULL)
00220   {
00221     return HAL_ERROR;
00222   }
00223
00224   /* Check the parameters */
00225   assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
00226
00227   hcec->gState = HAL_CEC_STATE_BUSY;
00228
00229   /* DeInit the low level hardware */
00230   HAL_CEC_MspDeInit(hcec);
00231   /* Disable the Peripheral */
00232   __HAL_CEC_DISABLE(hcec);
00233
00234   /* Clear Flags */
00235   __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR);
00236
00237   /* Disable the following CEC Transmission/Reception interrupts as
00238    * well as the following CEC Transmission/Reception Errors interrupts
00239    * Rx Byte Received IT
00240    * End of Reception IT
00241    * Rx overrun
00242    * Rx bit rising error
00243    * Rx short bit period error
00244    * Rx long bit period error
00245    * Rx missing acknowledge
00246    * Tx Byte Request IT
00247    * End of Transmission IT
00248    * Tx Missing Acknowledge IT
00249    * Tx-Error IT
00250    * Tx-Buffer Underrun IT
00251    * Tx arbitration lost   */
00252   __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
00253
00254   hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00255   hcec->gState = HAL_CEC_STATE_RESET;
00256   hcec->RxState = HAL_CEC_STATE_RESET;
00257
00258   /* Process Unlock */
00259   __HAL_UNLOCK(hcec);
00260
00261   return HAL_OK;
00262 }
00263
00264 /**
00265   * @brief Initializes the Own Address of the CEC device
00266   * @param hcec CEC handle
00267   * @param  CEC_OwnAddress The CEC own address.
00268   * @retval HAL status
00269   */
00270 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
00271 {
00272   /* Check the parameters */
00273   assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
00274
00275   if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
00276   {
00277     /* Process Locked */
00278     __HAL_LOCK(hcec);
00279
00280     hcec->gState = HAL_CEC_STATE_BUSY;
00281
00282     /* Disable the Peripheral */
00283     __HAL_CEC_DISABLE(hcec);
00284
00285     if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
00286     {
00287       hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16U);
00288     }
00289     else
00290     {
00291       hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);
00292     }
00293
00294     hcec->gState = HAL_CEC_STATE_READY;
00295     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00296
00297     /* Process Unlocked */
00298     __HAL_UNLOCK(hcec);
00299
00300     /* Enable the Peripheral */
00301     __HAL_CEC_ENABLE(hcec);
00302
00303     return  HAL_OK;
00304   }
00305   else
00306   {
00307     return HAL_BUSY;
00308   }
00309 }
00310
00311 /**
00312   * @brief CEC MSP Init
00313   * @param hcec CEC handle
00314   * @retval None
00315   */
00316  __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
00317 {
00318   /* Prevent unused argument(s) compilation warning */
00319   UNUSED(hcec);
00320   /* NOTE : This function should not be modified, when the callback is needed,
00321             the HAL_CEC_MspInit can be implemented in the user file
00322    */
00323 }
00324
00325 /**
00326   * @brief CEC MSP DeInit
00327   * @param hcec CEC handle
00328   * @retval None
00329   */
00330  __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
00331 {
00332   /* Prevent unused argument(s) compilation warning */
00333   UNUSED(hcec);
00334   /* NOTE : This function should not be modified, when the callback is needed,
00335             the HAL_CEC_MspDeInit can be implemented in the user file
00336    */
00337 }
00338
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
00344   *  @brief CEC Transmit/Receive functions
00345   *
00346 @verbatim
00347  ===============================================================================
00348                       ##### IO operation functions #####
00349  ===============================================================================
00350     This subsection provides a set of functions allowing to manage the CEC data transfers.
00351
00352     (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
00353         logical addresses (4-bit long addresses, 0x0F for broadcast messages destination)
00354
00355     (#) The communication is performed using Interrupts.
00356            These API's return the HAL status.
00357            The end of the data processing will be indicated through the
00358            dedicated CEC IRQ when using Interrupt mode.
00359            The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
00360            will be executed respectivelly at the end of the transmit or Receive process
00361            The HAL_CEC_ErrorCallback()user callback will be executed when a communication
00362            error is detected
00363
00364     (#) API's with Interrupt are :
00365          (+) HAL_CEC_Transmit_IT()
00366          (+) HAL_CEC_IRQHandler()
00367
00368     (#) A set of User Callbacks are provided:
00369          (+) HAL_CEC_TxCpltCallback()
00370          (+) HAL_CEC_RxCpltCallback()
00371          (+) HAL_CEC_ErrorCallback()
00372
00373 @endverbatim
00374   * @{
00375   */
00376
00377 /**
00378   * @brief Send data in interrupt mode
00379   * @param hcec CEC handle
00380   * @param InitiatorAddress Initiator address
00381   * @param DestinationAddress destination logical address
00382   * @param pData pointer to input byte data buffer
00383   * @param Size amount of data to be sent in bytes (without counting the header).
00384   *              0 means only the header is sent (ping operation).
00385   *              Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
00386   * @retval HAL status
00387   */
00388 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
00389 {
00390   /* if the IP isn't already busy and if there is no previous transmission
00391      already pending due to arbitration lost */
00392   if (hcec->gState == HAL_CEC_STATE_READY)
00393   {
00394     if((pData == NULL ) && (Size > 0U))
00395     {
00396       return  HAL_ERROR;
00397     }
00398
00399     assert_param(IS_CEC_ADDRESS(DestinationAddress));
00400     assert_param(IS_CEC_ADDRESS(InitiatorAddress));
00401     assert_param(IS_CEC_MSGSIZE(Size));
00402
00403     /* Process Locked */
00404     __HAL_LOCK(hcec);
00405     hcec->pTxBuffPtr = pData;
00406     hcec->gState = HAL_CEC_STATE_BUSY_TX;
00407     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00408
00409     /* initialize the number of bytes to send,
00410      * 0 means only one header is sent (ping operation) */
00411     hcec->TxXferCount = Size;
00412
00413     /* in case of no payload (Size = 0U), sender is only pinging the system;
00414        Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
00415     if (Size == 0U)
00416     {
00417       __HAL_CEC_LAST_BYTE_TX_SET(hcec);
00418     }
00419
00420     /* send header block */
00421     hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress);
00422     /* Set TX Start of Message  (TXSOM) bit */
00423     __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
00424
00425     /* Process Unlocked */
00426     __HAL_UNLOCK(hcec);
00427
00428     return HAL_OK;
00429
00430   }
00431   else
00432   {
00433     return HAL_BUSY;
00434   }
00435 }
00436
00437 /**
00438   * @brief Get size of the received frame.
00439   * @param hcec CEC handle
00440   * @retval Frame size
00441   */
00442 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
00443 {
00444   return hcec->RxXferSize;
00445 }
00446
00447 /**
00448   * @brief Change Rx Buffer.
00449   * @param hcec CEC handle
00450   * @param Rxbuffer Rx Buffer
00451   * @note  This function can be called only inside the HAL_CEC_RxCpltCallback()
00452   * @retval Frame size
00453   */
00454 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
00455 {
00456   hcec->Init.RxBuffer = Rxbuffer;
00457 }
00458
00459 /**
00460   * @brief This function handles CEC interrupt requests.
00461   * @param hcec CEC handle
00462   * @retval None
00463   */
00464 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
00465 {
00466
00467   /* save interrupts register for further error or interrupts handling purposes */
00468   uint32_t reg = 0U;
00469   reg = hcec->Instance->ISR;
00470
00471
00472   /* ----------------------------Arbitration Lost Management----------------------------------*/
00473   /* CEC TX arbitration error interrupt occurred --------------------------------------*/
00474   if((reg & CEC_FLAG_ARBLST) != RESET)
00475   {
00476     hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
00477     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
00478   }
00479
00480   /* ----------------------------Rx Management----------------------------------*/
00481   /* CEC RX byte received interrupt  ---------------------------------------------------*/
00482   if((reg & CEC_FLAG_RXBR) != RESET)
00483   {
00484     /* reception is starting */
00485     hcec->RxState = HAL_CEC_STATE_BUSY_RX;
00486     hcec->RxXferSize++;
00487     /* read received byte */
00488     *hcec->Init.RxBuffer++ = hcec->Instance->RXDR;
00489     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
00490   }
00491
00492   /* CEC RX end received interrupt  ---------------------------------------------------*/
00493   if((reg & CEC_FLAG_RXEND) != RESET)
00494   {
00495     /* clear IT */
00496     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
00497
00498     /* Rx process is completed, restore hcec->RxState to Ready */
00499     hcec->RxState = HAL_CEC_STATE_READY;
00500     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00501     hcec->Init.RxBuffer -= hcec->RxXferSize;
00502     HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
00503     hcec->RxXferSize = 0U;
00504   }
00505
00506   /* ----------------------------Tx Management----------------------------------*/
00507   /* CEC TX byte request interrupt ------------------------------------------------*/
00508   if((reg & CEC_FLAG_TXBR) != RESET)
00509   {
00510     if (hcec->TxXferCount == 0U)
00511     {
00512       /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
00513       __HAL_CEC_LAST_BYTE_TX_SET(hcec);
00514       hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
00515     }
00516     else
00517     {
00518       hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
00519       hcec->TxXferCount--;
00520     }
00521     /* clear Tx-Byte request flag */
00522     __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
00523   }
00524
00525   /* CEC TX end interrupt ------------------------------------------------*/
00526   if((reg & CEC_FLAG_TXEND) != RESET)
00527   {
00528     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
00529
00530     /* Tx process is ended, restore hcec->gState to Ready */
00531     hcec->gState = HAL_CEC_STATE_READY;
00532     /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
00533     start again the Transmission under the Tx call back API */
00534     __HAL_UNLOCK(hcec);
00535     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00536     HAL_CEC_TxCpltCallback(hcec);
00537   }
00538
00539   /* ----------------------------Rx/Tx Error Management----------------------------------*/
00540   if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0U)
00541   {
00542     hcec->ErrorCode = reg;
00543     __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE);
00544
00545
00546     if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET)
00547     {
00548       hcec->Init.RxBuffer-=hcec->RxXferSize;
00549       hcec->RxXferSize = 0U;
00550       hcec->RxState = HAL_CEC_STATE_READY;
00551     }
00552     else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET))
00553     {
00554       /* Set the CEC state ready to be able to start again the process */
00555       hcec->gState = HAL_CEC_STATE_READY;
00556     }
00557
00558     /* Error  Call Back */
00559     HAL_CEC_ErrorCallback(hcec);
00560   }
00561
00562 }
00563
00564 /**
00565   * @brief Tx Transfer completed callback
00566   * @param hcec CEC handle
00567   * @retval None
00568   */
00569  __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
00570 {
00571   /* Prevent unused argument(s) compilation warning */
00572   UNUSED(hcec);
00573   /* NOTE : This function should not be modified, when the callback is needed,
00574             the HAL_CEC_TxCpltCallback can be implemented in the user file
00575    */
00576 }
00577
00578 /**
00579   * @brief Rx Transfer completed callback
00580   * @param hcec CEC handle
00581   * @param RxFrameSize Size of frame
00582   * @retval None
00583   */
00584 __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
00585 {
00586   /* Prevent unused argument(s) compilation warning */
00587   UNUSED(hcec);
00588   UNUSED(RxFrameSize);
00589   /* NOTE : This function should not be modified, when the callback is needed,
00590             the HAL_CEC_RxCpltCallback can be implemented in the user file
00591    */
00592 }
00593
00594 /**
00595   * @brief CEC error callbacks
00596   * @param hcec CEC handle
00597   * @retval None
00598   */
00599  __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
00600 {
00601   /* Prevent unused argument(s) compilation warning */
00602   UNUSED(hcec);
00603   /* NOTE : This function should not be modified, when the callback is needed,
00604             the HAL_CEC_ErrorCallback can be implemented in the user file
00605    */
00606 }
00607 /**
00608   * @}
00609   */
00610
00611 /** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
00612   *  @brief   CEC control functions
00613   *
00614 @verbatim
00615  ===============================================================================
00616                       ##### Peripheral Control function #####
00617  ===============================================================================
00618     [..]
00619     This subsection provides a set of functions allowing to control the CEC.
00620      (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
00621          (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
00622 @endverbatim
00623   * @{
00624   */
00625 /**
00626   * @brief return the CEC state
00627   * @param hcec pointer to a CEC_HandleTypeDef structure that contains
00628   *              the configuration information for the specified CEC module.
00629   * @retval HAL state
00630   */
00631 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
00632 {
00633   uint32_t temp1 = 0x00U, temp2 = 0x00U;
00634   temp1 = hcec->gState;
00635   temp2 = hcec->RxState;
00636
00637   return (HAL_CEC_StateTypeDef)(temp1 | temp2);
00638 }
00639
00640 /**
00641   * @brief  Return the CEC error code
00642   * @param  hcec pointer to a CEC_HandleTypeDef structure that contains
00643   *              the configuration information for the specified CEC.
00644   * @retval CEC Error Code
00645   */
00646 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
00647 {
00648   return hcec->ErrorCode;
00649 }
00650
00651 /**
00652   * @}
00653   */
00654
00655 /**
00656   * @}
00657   */
00658
00659
00660 #endif /* defined(STM32F373xC) || defined(STM32F378xx) */
00661
00662 #endif /* HAL_CEC_MODULE_ENABLED */
00663 /**
00664   * @}
00665   */
00666
00667 /**
00668   * @}
00669   */
00670
00671 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_cec.h Source File

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stm32f3xx_hal_cec.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_cec.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CEC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_CEC_H
00038 #define __STM32F3xx_HAL_CEC_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 #if defined(STM32F373xC) || defined(STM32F378xx)
00045 /* Includes ------------------------------------------------------------------*/
00046 #include "stm32f3xx_hal_def.h"
00047
00048 /** @addtogroup STM32F3xx_HAL_Driver
00049   * @{
00050   */
00051
00052 /** @addtogroup CEC
00053   * @{
00054   */
00055
00056 /* Exported types ------------------------------------------------------------*/
00057 /** @defgroup CEC_Exported_Types CEC Exported Types
00058   * @{
00059   */
00060
00061 /**
00062   * @brief CEC Init Structure definition
00063   */
00064 typedef struct
00065 {
00066   uint32_t SignalFreeTime;               /*!< Set SFT field, specifies the Signal Free Time.
00067                                               It can be one of @ref CEC_Signal_Free_Time
00068                                               and belongs to the set {0U,...,7} where
00069                                               0x0 is the default configuration
00070                                               else means 0.5U + (SignalFreeTime - 1U) nominal data bit periods */
00071
00072   uint32_t Tolerance;                    /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
00073                                               it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
00074                                               or CEC_EXTENDED_TOLERANCE */
00075
00076   uint32_t BRERxStop;                    /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
00077                                               CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
00078                                               CEC_RX_STOP_ON_BRE:    reception is stopped. */
00079
00080   uint32_t BREErrorBitGen;               /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
00081                                               CEC line upon Bit Rising Error detection.
00082                                               CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
00083                                               CEC_BRE_ERRORBIT_GENERATION:    error-bit generation if BRESTP is set. */
00084
00085   uint32_t LBPEErrorBitGen;              /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
00086                                               CEC line upon Long Bit Period Error detection.
00087                                               CEC_LBPE_ERRORBIT_NO_GENERATION:  no error-bit generation.
00088                                               CEC_LBPE_ERRORBIT_GENERATION:     error-bit generation. */
00089
00090   uint32_t BroadcastMsgNoErrorBitGen;    /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
00091                                               upon an error detected on a broadcast message.
00092
00093                                               It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
00094
00095                                               1U) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
00096                                                  a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
00097                                                     and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
00098                                                  b) LBPE detection: error-bit generation on the CEC line
00099                                                     if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
00100
00101                                               2U) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
00102                                                  no error-bit generation in case neither a) nor b) are satisfied. Additionally,
00103                                                  there is no error-bit generation in case of Short Bit Period Error detection in
00104                                                  a broadcast message while LSTN bit is set. */
00105
00106   uint32_t SignalFreeTimeOption;         /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
00107                                               CEC_SFT_START_ON_TXSOM SFT:    timer starts when TXSOM is set by software.
00108                                               CEC_SFT_START_ON_TX_RX_END:  SFT timer starts automatically at the end of message transmission/reception. */
00109
00110   uint32_t ListenMode;                   /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
00111
00112                                               CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
00113                                                 own address (OAR). Messages addressed to different destination are ignored.
00114                                                 Broadcast messages are always received.
00115
00116                                               CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
00117                                                 address (OAR) with positive acknowledge. Messages addressed to different destination
00118                                                 are received, but without interfering with the CEC bus: no acknowledge sent.  */
00119
00120   uint16_t  OwnAddress;                 /*!< Own addresses configuration
00121                                              This parameter can be a value of @ref CEC_OWN_ADDRESS */
00122
00123   uint8_t  *RxBuffer;                    /*!< CEC Rx buffer pointeur */
00124
00125
00126 }CEC_InitTypeDef;
00127
00128 /**
00129   * @brief HAL CEC State structures definition
00130   * @note  HAL CEC State value is a combination of 2 different substates: gState and RxState.
00131   *        - gState contains CEC state information related to global Handle management
00132   *          and also information related to Tx operations.
00133   *          gState value coding follow below described bitmap :
00134   *          b7 (not used)
00135   *             x  : Should be set to 0
00136   *          b6  Error information
00137   *             0  : No Error
00138   *             1  : Error
00139   *          b5     IP initilisation status
00140   *             0  : Reset (IP not initialized)
00141   *             1  : Init done (IP initialized. HAL CEC Init function already called)
00142   *          b4-b3  (not used)
00143   *             xx : Should be set to 00
00144   *          b2     Intrinsic process state
00145   *             0  : Ready
00146   *             1  : Busy (IP busy with some configuration or internal operations)
00147   *          b1     (not used)
00148   *             x  : Should be set to 0
00149   *          b0     Tx state
00150   *             0  : Ready (no Tx operation ongoing)
00151   *             1  : Busy (Tx operation ongoing)
00152   *        - RxState contains information related to Rx operations.
00153   *          RxState value coding follow below described bitmap :
00154   *          b7-b6  (not used)
00155   *             xx : Should be set to 00
00156   *          b5     IP initilisation status
00157   *             0  : Reset (IP not initialized)
00158   *             1  : Init done (IP initialized)
00159   *          b4-b2  (not used)
00160   *            xxx : Should be set to 000
00161   *          b1     Rx state
00162   *             0  : Ready (no Rx operation ongoing)
00163   *             1  : Busy (Rx operation ongoing)
00164   *          b0     (not used)
00165   *             x  : Should be set to 0.
00166   */
00167 typedef enum
00168 {
00169   HAL_CEC_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
00170                                                    Value is allowed for gState and RxState             */
00171   HAL_CEC_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
00172                                                    Value is allowed for gState and RxState             */
00173   HAL_CEC_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
00174                                                    Value is allowed for gState only                    */
00175   HAL_CEC_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
00176                                                    Value is allowed for RxState only                   */
00177   HAL_CEC_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
00178                                                    Value is allowed for gState only                    */
00179   HAL_CEC_STATE_BUSY_RX_TX        = 0x23U,    /*!< an internal process is ongoing
00180                                                    Value is allowed for gState only                    */
00181 HAL_CEC_STATE_ERROR             = 0x60U     /*!< Error Value is allowed for gState only              */
00182 }HAL_CEC_StateTypeDef;
00183
00184 /**
00185   * @brief  CEC handle Structure definition
00186   */
00187 typedef struct
00188 {
00189   CEC_TypeDef             *Instance;      /*!< CEC registers base address */
00190
00191   CEC_InitTypeDef         Init;           /*!< CEC communication parameters */
00192
00193   uint8_t                 *pTxBuffPtr;    /*!< Pointer to CEC Tx transfer Buffer */
00194
00195   uint16_t                TxXferCount;    /*!< CEC Tx Transfer Counter */
00196
00197   uint16_t                RxXferSize;     /*!< CEC Rx Transfer size, 0: header received only */
00198
00199   HAL_LockTypeDef         Lock;           /*!< Locking object */
00200
00201   HAL_CEC_StateTypeDef    gState;         /*!< CEC state information related to global Handle management
00202                                                and also related to Tx operations.
00203                                                This parameter can be a value of @ref HAL_CEC_StateTypeDef */
00204
00205   HAL_CEC_StateTypeDef    RxState;        /*!< CEC state information related to Rx operations.
00206                                                This parameter can be a value of @ref HAL_CEC_StateTypeDef */
00207
00208   uint32_t                ErrorCode;      /*!< For errors handling purposes, copy of ISR register
00209                                                in case error is reported */
00210 }CEC_HandleTypeDef;
00211 /**
00212   * @}
00213   */
00214
00215 /* Exported constants --------------------------------------------------------*/
00216 /** @defgroup CEC_Exported_Constants CEC Exported Constants
00217   * @{
00218   */
00219
00220 /** @defgroup CEC_Error_Code CEC Error Code
00221   * @{
00222   */
00223 #define HAL_CEC_ERROR_NONE    (0x00000000U)          /*!< no error                      */
00224 #define HAL_CEC_ERROR_RXOVR   CEC_ISR_RXOVR          /*!< CEC Rx-Overrun                */
00225 #define HAL_CEC_ERROR_BRE     CEC_ISR_BRE            /*!< CEC Rx Bit Rising Error       */
00226 #define HAL_CEC_ERROR_SBPE    CEC_ISR_SBPE           /*!< CEC Rx Short Bit period Error */
00227 #define HAL_CEC_ERROR_LBPE    CEC_ISR_LBPE           /*!< CEC Rx Long Bit period Error  */
00228 #define HAL_CEC_ERROR_RXACKE  CEC_ISR_RXACKE         /*!< CEC Rx Missing Acknowledge    */
00229 #define HAL_CEC_ERROR_ARBLST  CEC_ISR_ARBLST         /*!< CEC Arbitration Lost          */
00230 #define HAL_CEC_ERROR_TXUDR   CEC_ISR_TXUDR          /*!< CEC Tx-Buffer Underrun        */
00231 #define HAL_CEC_ERROR_TXERR   CEC_ISR_TXERR          /*!< CEC Tx-Error                  */
00232 #define HAL_CEC_ERROR_TXACKE  CEC_ISR_TXACKE         /*!< CEC Tx Missing Acknowledge    */
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup CEC_Signal_Free_Time  CEC Signal Free Time setting parameter
00238   * @{
00239   */
00240 #define CEC_DEFAULT_SFT                    (0x00000000U)
00241 #define CEC_0_5_BITPERIOD_SFT              (0x00000001U)
00242 #define CEC_1_5_BITPERIOD_SFT              (0x00000002U)
00243 #define CEC_2_5_BITPERIOD_SFT              (0x00000003U)
00244 #define CEC_3_5_BITPERIOD_SFT              (0x00000004U)
00245 #define CEC_4_5_BITPERIOD_SFT              (0x00000005U)
00246 #define CEC_5_5_BITPERIOD_SFT              (0x00000006U)
00247 #define CEC_6_5_BITPERIOD_SFT              (0x00000007U)
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup CEC_Tolerance CEC Receiver Tolerance
00253   * @{
00254   */
00255 #define CEC_STANDARD_TOLERANCE             (0x00000000U)
00256 #define CEC_EXTENDED_TOLERANCE             ((uint32_t)CEC_CFGR_RXTOL)
00257 /**
00258   * @}
00259   */
00260
00261 /** @defgroup CEC_BRERxStop CEC Reception Stop on Error
00262   * @{
00263   */
00264 #define CEC_NO_RX_STOP_ON_BRE             (0x00000000U)
00265 #define CEC_RX_STOP_ON_BRE                ((uint32_t)CEC_CFGR_BRESTP)
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup CEC_BREErrorBitGen  CEC Error Bit Generation if Bit Rise Error reported
00271   * @{
00272   */
00273 #define CEC_BRE_ERRORBIT_NO_GENERATION     (0x00000000U)
00274 #define CEC_BRE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_BREGEN)
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup CEC_LBPEErrorBitGen  CEC Error Bit Generation if Long Bit Period Error reported
00280   * @{
00281   */
00282 #define CEC_LBPE_ERRORBIT_NO_GENERATION     (0x00000000U)
00283 #define CEC_LBPE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_LBPEGEN)
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup CEC_BroadCastMsgErrorBitGen  CEC Error Bit Generation on Broadcast message
00289   * @{
00290   */
00291 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION     (0x00000000U)
00292 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION  ((uint32_t)CEC_CFGR_BRDNOGEN)
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup CEC_SFT_Option     CEC Signal Free Time start option
00298   * @{
00299   */
00300 #define CEC_SFT_START_ON_TXSOM           (0x00000000U)
00301 #define CEC_SFT_START_ON_TX_RX_END       ((uint32_t)CEC_CFGR_SFTOPT)
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup CEC_Listening_Mode    CEC Listening mode option
00307   * @{
00308   */
00309 #define CEC_REDUCED_LISTENING_MODE          (0x00000000U)
00310 #define CEC_FULL_LISTENING_MODE             ((uint32_t)CEC_CFGR_LSTN)
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup CEC_OAR_Position   CEC Device Own Address position in CEC CFGR register
00316   * @{
00317   */
00318 #define CEC_CFGR_OAR_LSB_POS            (16U)
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup CEC_Initiator_Position   CEC Initiator logical address position in message header
00324   * @{
00325   */
00326 #define CEC_INITIATOR_LSB_POS           (4U)
00327 /**
00328   * @}
00329   */
00330
00331 /** @defgroup CEC_OWN_ADDRESS   CEC Own Address
00332   * @{
00333   */
00334 #define CEC_OWN_ADDRESS_NONE           ((uint16_t) 0x0000U)   /* Reset value */
00335 #define CEC_OWN_ADDRESS_0              ((uint16_t) 0x0001U)   /* Logical Address 0U */
00336 #define CEC_OWN_ADDRESS_1              ((uint16_t) 0x0002U)   /* Logical Address 1U */
00337 #define CEC_OWN_ADDRESS_2              ((uint16_t) 0x0004U)   /* Logical Address 2U */
00338 #define CEC_OWN_ADDRESS_3              ((uint16_t) 0x0008U)   /* Logical Address 3U */
00339 #define CEC_OWN_ADDRESS_4              ((uint16_t) 0x0010U)   /* Logical Address 4U */
00340 #define CEC_OWN_ADDRESS_5              ((uint16_t) 0x0020U)   /* Logical Address 5U */
00341 #define CEC_OWN_ADDRESS_6              ((uint16_t) 0x0040U)   /* Logical Address 6U */
00342 #define CEC_OWN_ADDRESS_7              ((uint16_t) 0x0080U)   /* Logical Address 7U */
00343 #define CEC_OWN_ADDRESS_8              ((uint16_t) 0x0100U)   /* Logical Address 9U */
00344 #define CEC_OWN_ADDRESS_9              ((uint16_t) 0x0200U)   /* Logical Address 10U */
00345 #define CEC_OWN_ADDRESS_10             ((uint16_t) 0x0400U)   /* Logical Address 11U */
00346 #define CEC_OWN_ADDRESS_11             ((uint16_t) 0x0800U)   /* Logical Address 12U */
00347 #define CEC_OWN_ADDRESS_12             ((uint16_t) 0x1000U)   /* Logical Address 13U */
00348 #define CEC_OWN_ADDRESS_13             ((uint16_t) 0x2000U)   /* Logical Address 14U */
00349 #define CEC_OWN_ADDRESS_14             ((uint16_t) 0x4000U)   /* Logical Address 15U */
00350 /**
00351   * @}
00352   */
00353
00354 /** @defgroup CEC_Interrupts_Definitions  CEC Interrupts definition
00355   * @{
00356   */
00357 #define CEC_IT_TXACKE                   CEC_IER_TXACKEIE
00358 #define CEC_IT_TXERR                    CEC_IER_TXERRIE
00359 #define CEC_IT_TXUDR                    CEC_IER_TXUDRIE
00360 #define CEC_IT_TXEND                    CEC_IER_TXENDIE
00361 #define CEC_IT_TXBR                     CEC_IER_TXBRIE
00362 #define CEC_IT_ARBLST                   CEC_IER_ARBLSTIE
00363 #define CEC_IT_RXACKE                   CEC_IER_RXACKEIE
00364 #define CEC_IT_LBPE                     CEC_IER_LBPEIE
00365 #define CEC_IT_SBPE                     CEC_IER_SBPEIE
00366 #define CEC_IT_BRE                      CEC_IER_BREIE
00367 #define CEC_IT_RXOVR                    CEC_IER_RXOVRIE
00368 #define CEC_IT_RXEND                    CEC_IER_RXENDIE
00369 #define CEC_IT_RXBR                     CEC_IER_RXBRIE
00370 /**
00371   * @}
00372   */
00373
00374 /** @defgroup CEC_Flags_Definitions  CEC Flags definition
00375   * @{
00376   */
00377 #define CEC_FLAG_TXACKE                 CEC_ISR_TXACKE
00378 #define CEC_FLAG_TXERR                  CEC_ISR_TXERR
00379 #define CEC_FLAG_TXUDR                  CEC_ISR_TXUDR
00380 #define CEC_FLAG_TXEND                  CEC_ISR_TXEND
00381 #define CEC_FLAG_TXBR                   CEC_ISR_TXBR
00382 #define CEC_FLAG_ARBLST                 CEC_ISR_ARBLST
00383 #define CEC_FLAG_RXACKE                 CEC_ISR_RXACKE
00384 #define CEC_FLAG_LBPE                   CEC_ISR_LBPE
00385 #define CEC_FLAG_SBPE                   CEC_ISR_SBPE
00386 #define CEC_FLAG_BRE                    CEC_ISR_BRE
00387 #define CEC_FLAG_RXOVR                  CEC_ISR_RXOVR
00388 #define CEC_FLAG_RXEND                  CEC_ISR_RXEND
00389 #define CEC_FLAG_RXBR                   CEC_ISR_RXBR
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
00395   * @{
00396   */
00397 #define CEC_ISR_ALL_ERROR              ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
00398                                                   CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
00404   * @{
00405   */
00406 #define CEC_IER_RX_ALL_ERR              ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
00407 /**
00408   * @}
00409   */
00410
00411 /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
00412   * @{
00413   */
00414 #define CEC_IER_TX_ALL_ERR              ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
00415 /**
00416   * @}
00417   */
00418
00419 /**
00420   * @}
00421   */
00422
00423 /* Exported macros -----------------------------------------------------------*/
00424 /** @defgroup CEC_Exported_Macros CEC Exported Macros
00425   * @{
00426   */
00427
00428 /** @brief  Reset CEC handle gstate & RxState
00429   * @param  __HANDLE__ CEC handle.
00430   * @retval None
00431   */
00432 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \
00433                                                        (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \
00434                                                        (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \
00435                                                      } while(0U)
00436
00437 /** @brief  Checks whether or not the specified CEC interrupt flag is set.
00438   * @param  __HANDLE__ specifies the CEC Handle.
00439   * @param  __FLAG__ specifies the flag to check.
00440   *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
00441   *            @arg CEC_FLAG_TXERR: Tx Error.
00442   *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
00443   *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
00444   *            @arg CEC_FLAG_TXBR: Tx-Byte Request.
00445   *            @arg CEC_FLAG_ARBLST: Arbitration Lost
00446   *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
00447   *            @arg CEC_FLAG_LBPE: Rx Long period Error
00448   *            @arg CEC_FLAG_SBPE: Rx Short period Error
00449   *            @arg CEC_FLAG_BRE: Rx Bit Rising Error
00450   *            @arg CEC_FLAG_RXOVR: Rx Overrun.
00451   *            @arg CEC_FLAG_RXEND: End Of Reception.
00452   *            @arg CEC_FLAG_RXBR: Rx-Byte Received.
00453   * @retval ITStatus
00454   */
00455 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ISR & (__FLAG__))
00456
00457 /** @brief  Clears the interrupt or status flag when raised (write at 1U)
00458   * @param  __HANDLE__ specifies the CEC Handle.
00459   * @param  __FLAG__ specifies the interrupt/status flag to clear.
00460   *        This parameter can be one of the following values:
00461   *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
00462   *            @arg CEC_FLAG_TXERR: Tx Error.
00463   *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
00464   *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
00465   *            @arg CEC_FLAG_TXBR: Tx-Byte Request.
00466   *            @arg CEC_FLAG_ARBLST: Arbitration Lost
00467   *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
00468   *            @arg CEC_FLAG_LBPE: Rx Long period Error
00469   *            @arg CEC_FLAG_SBPE: Rx Short period Error
00470   *            @arg CEC_FLAG_BRE: Rx Bit Rising Error
00471   *            @arg CEC_FLAG_RXOVR: Rx Overrun.
00472   *            @arg CEC_FLAG_RXEND: End Of Reception.
00473   *            @arg CEC_FLAG_RXBR: Rx-Byte Received.
00474   * @retval none
00475   */
00476 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ISR |= (__FLAG__))
00477
00478 /** @brief  Enables the specified CEC interrupt.
00479   * @param  __HANDLE__ specifies the CEC Handle.
00480   * @param  __INTERRUPT__ specifies the CEC interrupt to enable.
00481   *          This parameter can be one of the following values:
00482   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00483   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00484   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00485   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00486   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00487   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00488   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00489   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00490   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00491   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00492   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00493   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00494   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00495   * @retval none
00496   */
00497 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00498
00499 /** @brief  Disables the specified CEC interrupt.
00500   * @param  __HANDLE__ specifies the CEC Handle.
00501   * @param  __INTERRUPT__ specifies the CEC interrupt to disable.
00502   *          This parameter can be one of the following values:
00503   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00504   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00505   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00506   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00507   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00508   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00509   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00510   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00511   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00512   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00513   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00514   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00515   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00516   * @retval none
00517   */
00518 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
00519
00520 /** @brief  Checks whether or not the specified CEC interrupt is enabled.
00521   * @param  __HANDLE__ specifies the CEC Handle.
00522   * @param  __INTERRUPT__ specifies the CEC interrupt to check.
00523   *          This parameter can be one of the following values:
00524   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00525   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00526   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00527   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00528   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00529   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00530   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00531   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00532   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00533   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00534   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00535   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00536   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00537   * @retval FlagStatus
00538   */
00539 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
00540
00541 /** @brief  Enables the CEC device
00542   * @param  __HANDLE__ specifies the CEC Handle.
00543   * @retval none
00544   */
00545 #define __HAL_CEC_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR |=  CEC_CR_CECEN)
00546
00547 /** @brief  Disables the CEC device
00548   * @param  __HANDLE__ specifies the CEC Handle.
00549   * @retval none
00550   */
00551 #define __HAL_CEC_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR &=  ~CEC_CR_CECEN)
00552
00553 /** @brief  Set Transmission Start flag
00554   * @param  __HANDLE__ specifies the CEC Handle.
00555   * @retval none
00556   */
00557 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__)        ((__HANDLE__)->Instance->CR |=  CEC_CR_TXSOM)
00558
00559 /** @brief  Set Transmission End flag
00560   * @param  __HANDLE__ specifies the CEC Handle.
00561   * @retval none
00562   * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
00563   */
00564 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__)         ((__HANDLE__)->Instance->CR |=  CEC_CR_TXEOM)
00565
00566 /** @brief  Get Transmission Start flag
00567   * @param  __HANDLE__ specifies the CEC Handle.
00568   * @retval FlagStatus
00569   */
00570 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
00571
00572 /** @brief  Get Transmission End flag
00573   * @param  __HANDLE__ specifies the CEC Handle.
00574   * @retval FlagStatus
00575   */
00576 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__)   ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
00577
00578 /** @brief  Clear OAR register
00579   * @param  __HANDLE__ specifies the CEC Handle.
00580   * @retval none
00581   */
00582 #define __HAL_CEC_CLEAR_OAR(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
00583
00584 /** @brief  Set OAR register (without resetting previously set address in case of multi-address mode)
00585   *          To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
00586   * @param  __HANDLE__ specifies the CEC Handle.
00587   * @param  __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
00588   * @retval none
00589   */
00590 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__)   SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
00591
00592 /**
00593   * @}
00594   */
00595
00596 /* Exported functions --------------------------------------------------------*/
00597 /** @addtogroup CEC_Exported_Functions
00598   * @{
00599   */
00600
00601 /** @addtogroup CEC_Exported_Functions_Group1
00602   * @{
00603   */
00604 /* Initialization and de-initialization functions  ****************************/
00605 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
00606 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
00607 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
00608 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
00609 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
00610 /**
00611   * @}
00612   */
00613
00614 /** @addtogroup CEC_Exported_Functions_Group2
00615   * @{
00616   */
00617 /* I/O operation functions  ***************************************************/
00618 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
00619 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
00620 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
00621 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
00622 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
00623 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
00624 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
00625 /**
00626   * @}
00627   */
00628
00629 /** @addtogroup CEC_Exported_Functions_Group3
00630   * @{
00631   */
00632 /* Peripheral State functions  ************************************************/
00633 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
00634 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
00635 /**
00636   * @}
00637   */
00638
00639 /**
00640   * @}
00641   */
00642
00643 /* Private types -------------------------------------------------------------*/
00644 /** @defgroup CEC_Private_Types CEC Private Types
00645   * @{
00646   */
00647
00648 /**
00649   * @}
00650   */
00651
00652 /* Private variables ---------------------------------------------------------*/
00653 /** @defgroup CEC_Private_Variables CEC Private Variables
00654   * @{
00655   */
00656
00657 /**
00658   * @}
00659   */
00660
00661 /* Private constants ---------------------------------------------------------*/
00662 /** @defgroup CEC_Private_Constants CEC Private Constants
00663   * @{
00664   */
00665
00666 /**
00667   * @}
00668   */
00669
00670 /* Private macros ------------------------------------------------------------*/
00671 /** @defgroup CEC_Private_Macros CEC Private Macros
00672   * @{
00673   */
00674
00675 #define IS_CEC_SIGNALFREETIME(__SFT__)     ((__SFT__) <= CEC_CFGR_SFT)
00676
00677 #define IS_CEC_TOLERANCE(__RXTOL__)        (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
00678                                             ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
00679
00680 #define IS_CEC_BRERXSTOP(__BRERXSTOP__)   (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
00681                                            ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
00682
00683 #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
00684                                                 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
00685
00686 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
00687                                                  ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
00688
00689 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
00690                                                                        ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
00691
00692 #define IS_CEC_SFTOP(__SFTOP__)          (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
00693                                           ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
00694
00695 #define IS_CEC_LISTENING_MODE(__MODE__)     (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
00696                                              ((__MODE__) == CEC_FULL_LISTENING_MODE))
00697
00698 /** @brief Check CEC message size.
00699   *       The message size is the payload size: without counting the header,
00700   *       it varies from 0 byte (ping operation, one header only, no payload) to
00701   *       15 bytes (1 opcode and up to 14 operands following the header).
00702   * @param  __SIZE__ CEC message size.
00703   * @retval Test result (TRUE or FALSE).
00704   */
00705 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
00706
00707 /** @brief Check CEC device Own Address Register (OAR) setting.
00708   *        OAR address is written in a 15-bit field within CEC_CFGR register.
00709   * @param  __ADDRESS__ CEC own address.
00710   * @retval Test result (TRUE or FALSE).
00711   */
00712 #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
00713
00714 /** @brief Check CEC initiator or destination logical address setting.
00715   *        Initiator and destination addresses are coded over 4 bits.
00716   * @param  __ADDRESS__ CEC initiator or logical address.
00717   * @retval Test result (TRUE or FALSE).
00718   */
00719 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)
00720 /**
00721   * @}
00722   */
00723 /* Private functions ---------------------------------------------------------*/
00724 /** @defgroup CEC_Private_Functions CEC Private Functions
00725   * @{
00726   */
00727
00728 /**
00729   * @}
00730   */
00731
00732 /**
00733   * @}
00734   */
00735
00736 /**
00737   * @}
00738   */
00739
00740 #endif /* defined(STM32F373xC) || defined(STM32F378xx) */
00741
00742 #ifdef __cplusplus
00743 }
00744 #endif
00745
00746 #endif /* __STM32F3xx_HAL_CEC_H */
00747
00748 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00749
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_comp.c Source File

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stm32f3xx_hal_comp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_comp.c
00004   * @author  MCD Application Team
00005   * @brief   COMP HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the COMP peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Start/Stop operation functions in polling mode.
00010   *           + Start/Stop operation functions in interrupt mode.
00011   *           + Peripheral Control functions
00012   *           + Peripheral State functions
00013   *
00014   @verbatim
00015 ================================================================================
00016           ##### COMP Peripheral features #####
00017 ================================================================================
00018
00019   [..]
00020       The STM32F3xx device family integrates up to 7 analog comparators COMP1, COMP2...COMP7:
00021       (#) The non inverting input and inverting input can be set to GPIO pins.
00022           For STM32F3xx devices please refer to the COMP peripheral section in corresponding
00023           Reference Manual.
00024
00025       (#) The COMP output is available using HAL_COMP_GetOutputLevel()
00026           and can be set on GPIO pins.
00027           For STM32F3xx devices please refer to the COMP peripheral section in corresponding
00028           Reference Manual.
00029
00030       (#) The COMP output can be redirected to embedded timers (TIM1, TIM2, TIM3...).
00031           For STM32F3xx devices please refer to the COMP peripheral section in corresponding
00032           Reference Manual.
00033
00034       (#) Each couple of comparators COMP1 and COMP2, COMP3 and COMP4, COMP5 and COMP6 can be combined in window
00035           mode and respectively COMP1, COMP3 and COMP5 non inverting input is used as common non-inverting input.
00036
00037       (#) The seven comparators have interrupt capability with wake-up
00038           from Sleep and Stop modes (through the EXTI controller):
00039           (++) COMP1 is internally connected to EXTI Line 21
00040           (++) COMP2 is internally connected to EXTI Line 22
00041           (++) COMP3 is internally connected to EXTI Line 29
00042           (++) COMP4 is internally connected to EXTI Line 30
00043           (++) COMP5 is internally connected to EXTI Line 31
00044           (++) COMP6 is internally connected to EXTI Line 32
00045           (++) COMP7 is internally connected to EXTI Line 33.
00046
00047           From the corresponding IRQ handler, the right interrupt source can be retrieved with the
00048           adequate macro __HAL_COMP_COMPx_EXTI_GET_FLAG().
00049
00050
00051             ##### How to use this driver #####
00052 ================================================================================
00053   [..]
00054       This driver provides functions to configure and program the Comparators of all STM32F3xx devices.
00055
00056       To use the comparator, perform the following steps:
00057
00058       (#) Fill in the HAL_COMP_MspInit() to
00059       (++) Configure the comparator input in analog mode using HAL_GPIO_Init()
00060       (++) Configure the comparator output in alternate function mode using HAL_GPIO_Init() to map the comparator
00061            output to the GPIO pin
00062       (++) If required enable the COMP interrupt (EXTI line Interrupt): by configuring and enabling EXTI line in Interrupt mode and
00063            selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
00064            interrupt vector using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() functions.
00065
00066       (#) Configure the comparator using HAL_COMP_Init() function:
00067       (++) Select the inverting input (input minus)
00068       (++) Select the non-inverting input (input plus)
00069       (++) Select the output polarity
00070       (++) Select the output redirection
00071       (++) Select the hysteresis level
00072       (++) Select the power mode
00073       (++) Select the event/interrupt mode
00074
00075       -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE() in order
00076           to enable the comparator(s).
00077
00078       (#) On-the-fly reconfiguration of comparator(s) may be done by calling again HAL_COMP_Init(
00079           function with new input parameter values; HAL_COMP_MspInit() function shall be adapted
00080           to support multi configurations.
00081
00082       (#) Enable the comparator using HAL_COMP_Start() or HAL_COMP_Start_IT() functions.
00083
00084       (#) Use HAL_COMP_TriggerCallback() and/or HAL_COMP_GetOutputLevel() functions
00085           to manage comparator outputs (events and output level).
00086
00087       (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT()
00088           function.
00089
00090       (#) De-initialize the comparator using HAL_COMP_DeInit() function.
00091
00092       (#) For safety purposes comparator(s) can be locked using HAL_COMP_Lock() function.
00093           Only a MCU reset can reset that protection.
00094
00095   @endverbatim
00096   ******************************************************************************
00097   * @attention
00098   *
00099   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00100   *
00101   * Redistribution and use in source and binary forms, with or without modification,
00102   * are permitted provided that the following conditions are met:
00103   *   1. Redistributions of source code must retain the above copyright notice,
00104   *      this list of conditions and the following disclaimer.
00105   *   2. Redistributions in binary form must reproduce the above copyright notice,
00106   *      this list of conditions and the following disclaimer in the documentation
00107   *      and/or other materials provided with the distribution.
00108   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00109   *      may be used to endorse or promote products derived from this software
00110   *      without specific prior written permission.
00111   *
00112   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00113   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00114   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00115   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00116   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00117   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00118   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00119   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00120   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00121   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00122   *
00123   ******************************************************************************
00124   */
00125
00126 /*
00127   Additional Tables:
00128
00129     Table 1. COMP Inputs for the STM32F303xB/STM32F303xC/STM32F303xE devices
00130     +------------------------------------------------------------------------------------------+
00131     |                 |                | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
00132     |-----------------|----------------|---------------|---------------------------------------|
00133     |                 | 1U/4 VREFINT    |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |
00134     |                 | 1U/2 VREFINT    |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |
00135     |                 | 3U/4 VREFINT    |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |
00136     | Inverting Input | VREFINT        |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |
00137     |                 | DAC1 OUT (PA4) |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |
00138     |                 | DAC2 OUT (PA5) |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |
00139     |                 | IO1            |  PA0  |  PA2  |  PD15U |  PE8  |  PD13U |  PD10U |  PC0  |
00140     |                 | IO2            |  ---  |  ---  |  PB12U |  PB2  |  PB10U |  PB15U |  ---  |
00141     |-----------------|----------------|-------|-------|-------|-------|-------|-------|-------|
00142     |  Non Inverting  | IO1            |  PA1  |  PA7  |  PB14U |  PB0  |  PD12U |  PD11U |  PA0  |
00143     |    Input        | IO2            |  ---  |  PA3  |  PD14U |  PE7  |  PB13U |  PB11U |  PC1  |
00144     +------------------------------------------------------------------------------------------+
00145
00146     Table 2. COMP Outputs for the STM32F303xB/STM32F303xC/STM32F303xE devices
00147     +-------------------------------------------------------+
00148     | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
00149     |-------|-------|-------|-------|-------|-------|-------|
00150     |  PA0  |  PA2  |  PB1  |  PC8  |  PC7  |  PA10U |  PC2  |
00151     |  PF4  |  PA7  |  ---  |  PA8  |  PA9  |  PC6  |  ---  |
00152     |  PA6  |  PA12U |  ---  |  ---  |  ---  |  ---  |  ---  |
00153     |  PA11U |  PB9  |  ---  |  ---  |  ---  |  ---  |  ---  |
00154     |  PB8  |  ---  |  ---  |  ---  |  ---  |  ---  |  ---  |
00155     +-------------------------------------------------------+
00156
00157     Table 3. COMP Outputs redirection to embedded timers for the STM32F303xB/STM32F303xC devices
00158     +----------------------------------------------------------------------------------------------------------------------+
00159     |     COMP1      |     COMP2      |     COMP3      |     COMP4      |     COMP5      |     COMP6      |     COMP7      |
00160     |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
00161     |  TIM1 BKIN     |  TIM1 BKIN     |  TIM1 BKIN     |  TIM1 BKIN     |  TIM1 BKIN     |  TIM1 BKIN     |  TIM1 BKIN     |
00162     |                |                |                |                |                |                |                |
00163     |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |
00164     |                |                |                |                |                |                |                |
00165     |  TIM8 BKIN     |  TIM8 BKIN     |  TIM8 BKIN     |  TIM8 BKIN     |  TIM8 BKIN     |  TIM8 BKIN     |  TIM8 BKIN     |
00166     |                |                |                |                |                |                |                |
00167     |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |
00168     |                |                |                |                |                |                |                |
00169     |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |
00170     |     +          |     +          |     +          |     +          |     +          |     +          |     +          |
00171     |  TIM8BKIN2     |  TIM8BKIN2     |  TIM8BKIN2     |  TIM8BKIN2     |  TIM8BKIN2     |  TIM8BKIN2     |  TIM8BKIN2     |
00172     |                |                |                |                |                |                |                |
00173     |  TIM1 OCREFCLR |  TIM1 OCREFCLR |  TIM1 OCREFCLR |  TIM8 OCREFCLR |  TIM8 OCREFCLR |  TIM8 OCREFCLR |  TIM1 OCREFCLR |
00174     |                |                |                |                |                |                |                |
00175     |  TIM1 IC1      |  TIM1 IC1      |  TIM2 OCREFCLR |  TIM3 IC3      |  TIM2 IC1      |  TIM2 IC2      |  TIM8 OCREFCLR |
00176     |                |                |                |                |                |                |                |
00177     |  TIM2 IC4      |  TIM2 IC4      |  TIM3 IC2      |  TIM3 OCREFCLR |  TIM3 OCREFCLR |  TIM2 OCREFCLR |  TIM2 IC3      |
00178     |                |                |                |                |                |                |                |
00179     |  TIM2 OCREFCLR |  TIM2 OCREFCLR |  TIM4 IC1      |  TIM4 IC2      |  TIM4 IC3      |  TIM16 OCREFCLR|  TIM1 IC2      |
00180     |                |                |                |                |                |                |                |
00181     |  TIM3 IC1      |  TIM3 IC1      |  TIM15 IC1     |  TIM15 OCREFCLR|  TIM16 BKIN    |  TIM16 IC1     |  TIM17 OCREFCLR|
00182     |                |                |                |                |                |                |                |
00183     |  TIM3 OCREFCLR |  TIM3 OCREFCLR |  TIM15 BKIN    |  TIM15 IC2     |  TIM17 IC1     |  TIM4 IC4      |  TIM17 BKIN    |
00184     +----------------------------------------------------------------------------------------------------------------------+
00185
00186     Table 4. COMP Outputs redirection to embedded timers for the STM32F303xE devices
00187     +----------------------------------------------------------------------------------------------------------------------+
00188     |     COMP1      |     COMP2      |     COMP3      |     COMP4      |     COMP5      |     COMP6      |     COMP7      |
00189     |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
00190     |  TIM1 BKIN     |  TIM1 BKIN     |  TIM1 BKIN     |  TIM1 BKIN (1U) |  TIM1 BKIN     |  TIM1 BKIN     |  TIM1 BKIN (1U) |
00191     |                |                |                |                |                |                |                |
00192     |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |
00193     |                |                |                |                |                |                |                |
00194     |  TIM8 BKIN     |  TIM8 BKIN     |  TIM8 BKIN     |  TIM8 BKIN (1U) |  TIM8 BKIN     |  TIM8 BKIN     |  TIM8 BKIN (1U) |
00195     |                |                |                |                |                |                |                |
00196     |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |
00197     |                |                |                |                |                |                |                |
00198     |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |
00199     |     +          |     +          |     +          |     +          |     +          |     +          |     +          |
00200     |  TIM8BKIN2     |  TIM8BKIN2     |  TIM8BKIN2     |  TIM8BKIN2     |  TIM8BKIN2     |  TIM8BKIN2     |  TIM8BKIN2     |
00201     |                |                |                |                |                |                |                |
00202     |  TIM1 OCREFCLR |  TIM1 OCREFCLR |  TIM1 OCREFCLR |  TIM8 OCREFCLR |  TIM8 OCREFCLR |  TIM8 OCREFCLR |  TIM1 OCREFCLR |
00203     |                |                |                |                |                |                |                |
00204     |  TIM1 IC1      |  TIM1 IC1      |  TIM2 OCREFCLR |  TIM3 IC3      |  TIM2 IC1      |  TIM2 IC2      |  TIM8 OCREFCLR |
00205     |                |                |                |                |                |                |                |
00206     |  TIM2 IC4      |  TIM2 IC4      |  TIM3 IC2      |  TIM3 OCREFCLR |  TIM3 OCREFCLR |  TIM2 OCREFCLR |  TIM2 IC3      |
00207     |                |                |                |                |                |                |                |
00208     |  TIM2 OCREFCLR |  TIM2 OCREFCLR |  TIM4 IC1      |  TIM4 IC2      |  TIM4 IC3      |  TIM16 OCREFCLR|  TIM1 IC2      |
00209     |                |                |                |                |                |                |                |
00210     |  TIM3 IC1      |  TIM3 IC1      |  TIM15 IC1     |  TIM15 OCREFCLR|  TIM16 BKIN    |  TIM16 IC1     |  TIM17 OCREFCLR|
00211     |                |                |                |                |                |                |                |
00212     |  TIM3 OCREFCLR |  TIM3 OCREFCLR |  TIM15 BKIN    |  TIM15 IC2     |  TIM17 IC1     |  TIM4 IC4      |  TIM17 BKIN    |
00213     |                |                |                |                |                |                |                |
00214     |  TIM20 BKIN    |  TIM20 BKIN    |  TIM20 BKIN    |  TIM20 BKIN (1U)|  TIM20 BKIN    |  TIM20 BKIN    |  TIM20 BKIN (1U)|
00215     |                |                |                |                |                |                |                |
00216     |  TIM20 BKIN2   |  TIM20 BKIN2   |  TIM20 BKIN2   |  TIM20 BKIN2   |  TIM20 BKIN2   |  TIM20 BKIN2   |  TIM20 BKIN2   |
00217     |                |                |                |                |                |                |                |
00218     |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |
00219     |     +          |     +          |     +          |     +          |     +          |     +          |     +          |
00220     |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |
00221     |     +          |     +          |     +          |     +          |     +          |     +          |     +          |
00222     |  TIM20 BKIN2   |  TIM20 BKIN2   |  TIM20 BKIN2   |  TIM20 BKIN2   |  TIM20 BKIN2   |  TIM20 BKIN2   |  TIM20 BKIN2   |
00223     |                |                |                |                |                |                |                |
00224     +----------------------------------------------------------------------------------------------------------------------+
00225     (1U):  This connection consists of connecting both GPIO and COMP output to TIM1/8U/20 BRK input through an OR gate, instead
00226           of connecting the GPIO to the TIM1/8U/20 BRK input and the COMP output to the TIM1/8U/20 BRK_ACTH input. The aim is to
00227           add a digital filter (3  bits) on the COMP output.
00228
00229     Table 5. COMP Outputs blanking sources for the STM32F303xB/STM32F303xC/STM32F303xE devices
00230     +----------------------------------------------------------------------------------------------------------------------+
00231     |     COMP1      |     COMP2      |     COMP3      |     COMP4      |     COMP5      |     COMP6      |     COMP7      |
00232     |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
00233     |  TIM1 OC5      |  TIM1 OC5      |  TIM1 OC5      |  TIM3 OC4      |  --------      |  TIM8 OC5      |  TIM1 OC5      |
00234     |                |                |                |                |                |                |                |
00235     |  TIM2 OC3      |  TIM2 OC3      |  --------      |  TIM8 OC5      |  TIM3 OC3      |  TIM2 OC4      |  TIM8 OC5      |
00236     |                |                |                |                |                |                |                |
00237     |  TIM3 OC3      |  TIM3 OC3      |  TIM2 OC4      |  TIM15 OC1     |  TIM8 OC5      |  TIM15 OC2     |  TIM15 OC2     |
00238     |                |                |                |                |                |                |                |
00239     +----------------------------------------------------------------------------------------------------------------------+
00240
00241 */
00242
00243 /* Includes ------------------------------------------------------------------*/
00244 #include "stm32f3xx_hal.h"
00245
00246 /** @addtogroup STM32F3xx_HAL_Driver
00247   * @{
00248   */
00249
00250 /** @defgroup COMP COMP
00251   * @brief COMP HAL module driver
00252   * @{
00253   */
00254
00255 #ifdef HAL_COMP_MODULE_ENABLED
00256
00257 /* Private typedef -----------------------------------------------------------*/
00258 /* Private define ------------------------------------------------------------*/
00259 /** @defgroup COMP_Private_Constants COMP Private Constants
00260   * @{
00261   */
00262 #define COMP_LOCK_DISABLE                      (0x00000000U)
00263 #define COMP_LOCK_ENABLE                       COMP_CSR_COMPxLOCK
00264 /**
00265   * @}
00266   */
00267
00268 /* Private macro -------------------------------------------------------------*/
00269 /* Private variables ---------------------------------------------------------*/
00270 /* Private function prototypes -----------------------------------------------*/
00271 /* Exported functions --------------------------------------------------------*/
00272
00273 /** @defgroup COMP_Exported_Functions COMP Exported Functions
00274   * @{
00275   */
00276
00277 /** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
00278  *  @brief    Initialization and de-initialization functions.
00279  *
00280 @verbatim
00281  ===============================================================================
00282               ##### Initialization and de-initialization functions #####
00283  ===============================================================================
00284     [..]  This section provides functions to initialize and de-initialize comparators.
00285
00286 @endverbatim
00287   * @{
00288   */
00289
00290 /**
00291   * @brief  Initialize the COMP peripheral according to the specified
00292   *         parameters in the COMP_InitTypeDef and initialize the associated handle.
00293   * @note   If the selected comparator is locked, initialization cannot be performed.
00294   *         To unlock the configuration, perform a system reset.
00295   * @param  hcomp  COMP handle
00296   * @retval HAL status
00297   */
00298 HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
00299 {
00300   HAL_StatusTypeDef status = HAL_OK;
00301
00302   /* Check the COMP handle allocation and lock status */
00303   if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
00304   {
00305     status = HAL_ERROR;
00306   }
00307   else
00308   {
00309     /* Check the parameters */
00310     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00311     assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput));
00312     assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput));
00313     assert_param(IS_COMP_NONINVERTINGINPUT_INSTANCE(hcomp->Instance, hcomp->Init.NonInvertingInput));
00314     assert_param(IS_COMP_OUTPUT(hcomp->Init.Output));
00315     assert_param(IS_COMP_OUTPUT_INSTANCE(hcomp->Instance, hcomp->Init.Output));
00316     assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
00317     assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
00318     assert_param(IS_COMP_MODE(hcomp->Init.Mode));
00319     assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce));
00320     assert_param(IS_COMP_BLANKINGSRCE_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce));
00321     assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
00322
00323     if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE)
00324     {
00325       assert_param(IS_COMP_WINDOWMODE_INSTANCE(hcomp->Instance));
00326       assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
00327     }
00328
00329     /* Init SYSCFG and the low level hardware to access comparators */
00330     __HAL_RCC_SYSCFG_CLK_ENABLE();
00331     /* Init the low level hardware : SYSCFG to access comparators */
00332     HAL_COMP_MspInit(hcomp);
00333
00334     if(hcomp->State == HAL_COMP_STATE_RESET)
00335     {
00336       /* Allocate lock resource and initialize it */
00337       hcomp->Lock = HAL_UNLOCKED;
00338     }
00339
00340     /* Manage inverting input comparator inverting input connected to a GPIO  */
00341     /* for STM32F302x, STM32F32xx, STM32F33x.                                 */
00342     hcomp->Init.InvertingInput = COMP_INVERTINGINPUT_SELECTION(hcomp->Instance, hcomp->Init.InvertingInput);
00343
00344     /* Set COMP parameters */
00345     /*     Set COMPxINSEL bits according to hcomp->Init.InvertingInput value        */
00346     /*     Set COMPxNONINSEL bits according to hcomp->Init.NonInvertingInput value  */
00347     /*     Set COMPxBLANKING bits according to hcomp->Init.BlankingSrce value       */
00348     /*     Set COMPxOUTSEL bits according to hcomp->Init.Output value               */
00349     /*     Set COMPxPOL bit according to hcomp->Init.OutputPol value                */
00350     /*     Set COMPxHYST bits according to hcomp->Init.Hysteresis value             */
00351     /*     Set COMPxMODE bits according to hcomp->Init.Mode value                   */
00352     COMP_INIT(hcomp);
00353
00354     /* Initialize the COMP state*/
00355     hcomp->State = HAL_COMP_STATE_READY;
00356   }
00357
00358   return status;
00359 }
00360
00361 /**
00362   * @brief  DeInitialize the COMP peripheral.
00363   * @note   If the selected comparator is locked, deinitialization cannot be performed.
00364   *         To unlock the configuration, perform a system reset.
00365   * @param  hcomp  COMP handle
00366   * @retval HAL status
00367   */
00368 HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
00369 {
00370   HAL_StatusTypeDef status = HAL_OK;
00371
00372   /* Check the COMP handle allocation and lock status */
00373   if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
00374   {
00375     status = HAL_ERROR;
00376   }
00377   else
00378   {
00379     /* Check the parameter */
00380     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00381
00382     /* Set COMP_CSR register to reset value */
00383     COMP_DEINIT(hcomp);
00384
00385     /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
00386     HAL_COMP_MspDeInit(hcomp);
00387
00388     hcomp->State = HAL_COMP_STATE_RESET;
00389
00390     /* Release Lock */
00391     __HAL_UNLOCK(hcomp);
00392   }
00393
00394   return status;
00395 }
00396
00397 /**
00398   * @brief  Initialize the COMP MSP.
00399   * @param  hcomp  COMP handle
00400   * @retval None
00401   */
00402 __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
00403 {
00404   /* Prevent unused argument(s) compilation warning */
00405   UNUSED(hcomp);
00406
00407   /* NOTE : This function should not be modified, when the callback is needed,
00408             the HAL_COMP_MspInit could be implemented in the user file
00409    */
00410 }
00411
00412 /**
00413   * @brief  DeInitialize the COMP MSP.
00414   * @param  hcomp  COMP handle
00415   * @retval None
00416   */
00417 __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
00418 {
00419   /* Prevent unused argument(s) compilation warning */
00420   UNUSED(hcomp);
00421
00422   /* NOTE : This function should not be modified, when the callback is needed,
00423             the HAL_COMP_MspDeInit could be implemented in the user file
00424    */
00425 }
00426
00427 /**
00428   * @}
00429   */
00430
00431 /** @defgroup COMP_Exported_Functions_Group2 Start Stop operation functions
00432  *  @brief   Start-Stop operation functions.
00433  *
00434 @verbatim
00435  ===============================================================================
00436                       ##### Start Stop operation functions #####
00437  ===============================================================================
00438     [..]  This section provides functions allowing to:
00439       (+) Start a comparator without interrupt generation.
00440       (+) Stop a comparator without interrupt generation.
00441       (+) Start a comparator with interrupt generation.
00442       (+) Stop a comparator with interrupt generation.
00443       (+) Handle interrupts from a comparator with associated callback function.
00444
00445 @endverbatim
00446   * @{
00447   */
00448
00449 /**
00450   * @brief  Start the comparator.
00451   * @param  hcomp  COMP handle
00452   * @retval HAL status
00453   */
00454 HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
00455 {
00456   HAL_StatusTypeDef status = HAL_OK;
00457   uint32_t extiline = 0U;
00458
00459   /* Check the COMP handle allocation and lock status */
00460   if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
00461   {
00462     status = HAL_ERROR;
00463   }
00464   else
00465   {
00466     /* Check the parameter */
00467     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00468
00469     if(hcomp->State == HAL_COMP_STATE_READY)
00470     {
00471       /* Get the EXTI Line output configuration */
00472       extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
00473
00474       /* Configure the event generation */
00475       if((hcomp->Init.TriggerMode & (COMP_TRIGGERMODE_EVENT_RISING|COMP_TRIGGERMODE_EVENT_FALLING)) != RESET)
00476       {
00477         /* Configure the event trigger rising edge */
00478         if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_EVENT_RISING) != RESET)
00479         {
00480           COMP_EXTI_RISING_ENABLE(extiline);
00481         }
00482         else
00483         {
00484           COMP_EXTI_RISING_DISABLE(extiline);
00485         }
00486
00487         /* Configure the trigger falling edge */
00488         if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_EVENT_FALLING) != RESET)
00489         {
00490           COMP_EXTI_FALLING_ENABLE(extiline);
00491         }
00492         else
00493         {
00494           COMP_EXTI_FALLING_DISABLE(extiline);
00495         }
00496
00497         /* Enable EXTI event generation */
00498         COMP_EXTI_ENABLE_EVENT(extiline);
00499
00500         /* Clear COMP EXTI pending bit */
00501         COMP_EXTI_CLEAR_FLAG(extiline);
00502       }
00503
00504       /* Enable the selected comparator */
00505       __HAL_COMP_ENABLE(hcomp);
00506
00507       hcomp->State = HAL_COMP_STATE_BUSY;
00508     }
00509     else
00510     {
00511       status = HAL_ERROR;
00512     }
00513   }
00514
00515   return status;
00516 }
00517
00518 /**
00519   * @brief  Stop the comparator.
00520   * @param  hcomp  COMP handle
00521   * @retval HAL status
00522   */
00523 HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
00524 {
00525   HAL_StatusTypeDef status = HAL_OK;
00526
00527   /* Check the COMP handle allocation and lock status */
00528   if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
00529   {
00530     status = HAL_ERROR;
00531   }
00532   else
00533   {
00534     /* Check the parameter */
00535     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00536
00537     if(hcomp->State == HAL_COMP_STATE_BUSY)
00538     {
00539       /* Disable the EXTI Line event mode if any */
00540       COMP_EXTI_DISABLE_EVENT(COMP_GET_EXTI_LINE(hcomp->Instance));
00541
00542       /* Disable the selected comparator */
00543       __HAL_COMP_DISABLE(hcomp);
00544
00545       hcomp->State = HAL_COMP_STATE_READY;
00546     }
00547     else
00548     {
00549       status = HAL_ERROR;
00550     }
00551   }
00552
00553   return status;
00554 }
00555
00556 /**
00557   * @brief  Start the comparator in Interrupt mode.
00558   * @param  hcomp  COMP handle
00559   * @retval HAL status.
00560   */
00561 HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
00562 {
00563   HAL_StatusTypeDef status = HAL_OK;
00564   uint32_t extiline = 0U;
00565
00566   /* Check the COMP handle allocation and lock status */
00567   if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
00568   {
00569     status = HAL_ERROR;
00570   }
00571   else
00572   {
00573     /* Check the parameter */
00574     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00575
00576     if(hcomp->State == HAL_COMP_STATE_READY)
00577     {
00578       /* Configure the EXTI event generation */
00579       if((hcomp->Init.TriggerMode & (COMP_TRIGGERMODE_IT_RISING|COMP_TRIGGERMODE_IT_FALLING)) != RESET)
00580       {
00581         /* Get the EXTI Line output configuration */
00582         extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
00583
00584         /* Configure the trigger rising edge */
00585         if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET)
00586         {
00587           COMP_EXTI_RISING_ENABLE(extiline);
00588         }
00589         else
00590         {
00591           COMP_EXTI_RISING_DISABLE(extiline);
00592         }
00593         /* Configure the trigger falling edge */
00594         if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET)
00595         {
00596           COMP_EXTI_FALLING_ENABLE(extiline);
00597         }
00598         else
00599         {
00600           COMP_EXTI_FALLING_DISABLE(extiline);
00601         }
00602
00603         /* Clear COMP EXTI pending bit if any */
00604         COMP_EXTI_CLEAR_FLAG(extiline);
00605
00606         /* Enable EXTI interrupt mode */
00607         COMP_EXTI_ENABLE_IT(extiline);
00608
00609         /* Enable the selected comparator */
00610         __HAL_COMP_ENABLE(hcomp);
00611
00612         hcomp->State = HAL_COMP_STATE_BUSY;
00613       }
00614       else
00615       {
00616         status = HAL_ERROR;
00617       }
00618     }
00619     else
00620     {
00621       status = HAL_ERROR;
00622     }
00623   }
00624
00625   return status;
00626 }
00627
00628 /**
00629   * @brief  Stop the comparator in Interrupt mode.
00630   * @param  hcomp  COMP handle
00631   * @retval HAL status
00632   */
00633 HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
00634 {
00635   HAL_StatusTypeDef status = HAL_OK;
00636
00637   /* Disable the EXTI Line interrupt mode */
00638   COMP_EXTI_DISABLE_IT(COMP_GET_EXTI_LINE(hcomp->Instance));
00639
00640   status = HAL_COMP_Stop(hcomp);
00641
00642   return status;
00643 }
00644
00645 /**
00646   * @brief  Comparator IRQ Handler.
00647   * @param  hcomp  COMP handle
00648   * @retval HAL status
00649   */
00650 void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
00651 {
00652   uint32_t extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
00653
00654   /* Check COMP EXTI flag */
00655   if(COMP_EXTI_GET_FLAG(extiline) != RESET)
00656   {
00657     /* Clear COMP EXTI pending bit */
00658     COMP_EXTI_CLEAR_FLAG(extiline);
00659
00660     /* COMP trigger user callback */
00661     HAL_COMP_TriggerCallback(hcomp);
00662   }
00663 }
00664
00665 /**
00666   * @brief  Comparator callback.
00667   * @param  hcomp  COMP handle
00668   * @retval None
00669   */
00670 __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
00671 {
00672   /* Prevent unused argument(s) compilation warning */
00673   UNUSED(hcomp);
00674
00675   /* NOTE : This function should not be modified, when the callback is needed,
00676             the HAL_COMP_TriggerCallback should be implemented in the user file
00677    */
00678 }
00679
00680 /**
00681   * @}
00682   */
00683
00684 /** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
00685  *  @brief   Management functions.
00686  *
00687 @verbatim
00688  ===============================================================================
00689                       ##### Peripheral Control functions #####
00690  ===============================================================================
00691     [..]
00692     This subsection provides a set of functions allowing to control the comparators.
00693
00694 @endverbatim
00695   * @{
00696   */
00697
00698 /**
00699   * @brief  Lock the selected comparator configuration.
00700   * @note   A system reset is required to unlock the comparator configuration.
00701   * @param  hcomp  COMP handle
00702   * @retval HAL status
00703   */
00704 HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
00705 {
00706   HAL_StatusTypeDef status = HAL_OK;
00707
00708   /* Check the COMP handle allocation and lock status */
00709   if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
00710   {
00711     status = HAL_ERROR;
00712   }
00713   else
00714   {
00715     /* Check the parameter */
00716     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00717
00718     /* Set lock flag on state */
00719     switch(hcomp->State)
00720     {
00721     case HAL_COMP_STATE_BUSY:
00722       hcomp->State = HAL_COMP_STATE_BUSY_LOCKED;
00723       break;
00724     case HAL_COMP_STATE_READY:
00725       hcomp->State = HAL_COMP_STATE_READY_LOCKED;
00726       break;
00727     default:
00728       /* unexpected state */
00729       status = HAL_ERROR;
00730       break;
00731     }
00732   }
00733
00734   if(status == HAL_OK)
00735   {
00736     /* Set the lock bit corresponding to selected comparator */
00737     __HAL_COMP_LOCK(hcomp);
00738   }
00739
00740   return status;
00741 }
00742
00743 /**
00744   * @brief  Return the output level (high or low) of the selected comparator.
00745   *         The output level depends on the selected polarity.
00746   *         If the polarity is not inverted:
00747   *           - Comparator output is low when the non-inverting input is at a lower
00748   *             voltage than the inverting input
00749   *           - Comparator output is high when the non-inverting input is at a higher
00750   *             voltage than the inverting input
00751   *         If the polarity is inverted:
00752   *           - Comparator output is high when the non-inverting input is at a lower
00753   *             voltage than the inverting input
00754   *           - Comparator output is low when the non-inverting input is at a higher
00755   *             voltage than the inverting input
00756   * @param  hcomp  COMP handle
00757   * @retval Returns the selected comparator output level:
00758   *         @arg @ref COMP_OUTPUTLEVEL_LOW
00759   *         @arg @ref COMP_OUTPUTLEVEL_HIGH
00760   *
00761   */
00762 uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
00763 {
00764   uint32_t level=0U;
00765
00766   /* Check the parameter */
00767   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00768
00769   level = READ_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxOUT);
00770
00771   if(level != 0U)
00772   {
00773     return(COMP_OUTPUTLEVEL_HIGH);
00774   }
00775   return(COMP_OUTPUTLEVEL_LOW);
00776 }
00777
00778 /**
00779   * @}
00780   */
00781
00782 /** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
00783  *  @brief   Peripheral State functions.
00784  *
00785 @verbatim
00786  ===============================================================================
00787                       ##### Peripheral State functions #####
00788  ===============================================================================
00789     [..]
00790     This subsection permits to get in run-time the status of the peripheral.
00791
00792 @endverbatim
00793   * @{
00794   */
00795
00796 /**
00797   * @brief  Return the COMP handle state.
00798   * @param  hcomp  COMP handle
00799   * @retval HAL state
00800   */
00801 HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
00802 {
00803   /* Check the COMP handle allocation */
00804   if(hcomp == NULL)
00805   {
00806     return HAL_COMP_STATE_RESET;
00807   }
00808
00809   /* Check the parameter */
00810   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00811
00812   /* Return COMP handle state */
00813   return hcomp->State;
00814 }
00815 /**
00816   * @}
00817   */
00818
00819 /**
00820   * @}
00821   */
00822
00823 #endif /* HAL_COMP_MODULE_ENABLED */
00824 /**
00825   * @}
00826   */
00827
00828 /**
00829   * @}
00830   */
00831
00832 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_comp.h Source File

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stm32f3xx_hal_comp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_comp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of COMP HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_COMP_H
00038 #define __STM32F3xx_HAL_COMP_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup COMP
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /** @defgroup COMP_Exported_Types COMP Exported Types
00057   * @{
00058   */
00059 /**
00060   * @brief  COMP Init structure definition
00061   */
00062 typedef struct
00063 {
00064
00065   uint32_t InvertingInput;     /*!< Selects the inverting input of the comparator.
00066                                     This parameter can be a value of @ref COMPEx_InvertingInput */
00067
00068   uint32_t NonInvertingInput;  /*!< Selects the non inverting input of the comparator.
00069                                     This parameter can be a value of @ref COMPEx_NonInvertingInput
00070                                     Note: Only available on STM32F302xB/xC, STM32F303xB/xC and STM32F358xx devices */
00071
00072   uint32_t Output;             /*!< Selects the output redirection of the comparator.
00073                                     This parameter can be a value of @ref COMPEx_Output */
00074
00075   uint32_t OutputPol;          /*!< Selects the output polarity of the comparator.
00076                                     This parameter can be a value of @ref COMP_OutputPolarity */
00077
00078   uint32_t Hysteresis;         /*!< Selects the hysteresis voltage of the comparator.
00079                                     This parameter can be a value of @ref COMPEx_Hysteresis
00080                                     Note: Only available on STM32F302xB/xC, STM32F303xB/xC, STM32F373xB/xC, STM32F358xx and STM32F378xx devices */
00081
00082   uint32_t BlankingSrce;       /*!< Selects the output blanking source of the comparator.
00083                                     This parameter can be a value of @ref COMPEx_BlankingSrce
00084                                     Note: Not available on STM32F373xB/C and STM32F378xx devices */
00085
00086   uint32_t Mode;               /*!< Selects the operating consumption mode of the comparator
00087                                     to adjust the speed/consumption.
00088                                     This parameter can be a value of @ref COMPEx_Mode
00089                                     Note: Not available on STM32F301x6/x8, STM32F302x6/x8, STM32F334x6/x8, STM32F318xx and STM32F328xx devices */
00090
00091   uint32_t WindowMode;         /*!< Selects the window mode of the comparator X (X=2U, 4 or 6 if available).
00092                                     This parameter can be a value of @ref COMPEx_WindowMode */
00093
00094   uint32_t TriggerMode;        /*!< Selects the trigger mode of the comparator (interrupt mode).
00095                                     This parameter can be a value of @ref COMP_TriggerMode */
00096
00097 }COMP_InitTypeDef;
00098
00099 /**
00100   * @brief  HAL State structures definition
00101   */
00102 typedef enum
00103 {
00104   HAL_COMP_STATE_RESET             = 0x00U,    /*!< COMP not yet initialized or disabled             */
00105   HAL_COMP_STATE_READY             = 0x01U,    /*!< COMP initialized and ready for use               */
00106   HAL_COMP_STATE_READY_LOCKED      = 0x11U,    /*!< COMP initialized but the configuration is locked */
00107   HAL_COMP_STATE_BUSY              = 0x02U,    /*!< COMP is running                                  */
00108   HAL_COMP_STATE_BUSY_LOCKED       = 0x12     /*!< COMP is running and the configuration is locked  */
00109 }HAL_COMP_StateTypeDef;
00110
00111 /**
00112   * @brief  COMP Handle Structure definition
00113   */
00114 typedef struct
00115 {
00116   COMP_TypeDef                *Instance; /*!< Register base address    */
00117   COMP_InitTypeDef            Init;      /*!< COMP required parameters */
00118   HAL_LockTypeDef             Lock;      /*!< Locking object           */
00119   __IO HAL_COMP_StateTypeDef  State;     /*!< COMP communication state */
00120 }COMP_HandleTypeDef;
00121
00122 /**
00123   * @}
00124   */
00125
00126 /* Exported constants --------------------------------------------------------*/
00127 /** @defgroup COMP_Exported_Constants COMP Exported Constants
00128   * @{
00129   */
00130
00131 /** @defgroup COMP_OutputPolarity COMP Output Polarity
00132   * @{
00133   */
00134 #define COMP_OUTPUTPOL_NONINVERTED             (0x00000000U)  /*!< COMP output on GPIO isn't inverted */
00135 #define COMP_OUTPUTPOL_INVERTED                COMP_CSR_COMPxPOL       /*!< COMP output on GPIO is inverted  */
00136 /**
00137   * @}
00138   */
00139
00140 /** @defgroup COMP_OutputLevel COMP Output Level
00141   * @{
00142   */
00143 /* When output polarity is not inverted, comparator output is low when
00144    the non-inverting input is at a lower voltage than the inverting input*/
00145 #define COMP_OUTPUTLEVEL_LOW                   (0x00000000U)
00146 /* When output polarity is not inverted, comparator output is high when
00147    the non-inverting input is at a higher voltage than the inverting input */
00148 #define COMP_OUTPUTLEVEL_HIGH                  COMP_CSR_COMPxOUT
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup COMP_TriggerMode COMP Trigger Mode
00154   * @{
00155   */
00156 #define COMP_TRIGGERMODE_NONE                 (0x00000000U)   /*!< No External Interrupt trigger detection */
00157 #define COMP_TRIGGERMODE_IT_RISING            (0x00000001U)   /*!< External Interrupt Mode with Rising edge trigger detection */
00158 #define COMP_TRIGGERMODE_IT_FALLING           (0x00000002U)   /*!< External Interrupt Mode with Falling edge trigger detection */
00159 #define COMP_TRIGGERMODE_IT_RISING_FALLING    (0x00000003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00160 #define COMP_TRIGGERMODE_EVENT_RISING         (0x00000010U)   /*!< Event Mode with Rising edge trigger detection */
00161 #define COMP_TRIGGERMODE_EVENT_FALLING        (0x00000020U)   /*!< Event Mode with Falling edge trigger detection */
00162 #define COMP_TRIGGERMODE_EVENT_RISING_FALLING (0x00000030U)   /*!< Event Mode with Rising/Falling edge trigger detection */
00163 /**
00164   * @}
00165   */
00166
00167 /** @defgroup COMP_State_Lock COMP State Lock
00168   * @{
00169   */
00170 #define COMP_STATE_BIT_LOCK                   (0x00000010U)   /* Lock bit in COMP handle state */
00171 /**
00172   * @}
00173   */
00174
00175 /**
00176   * @}
00177   */
00178
00179 /* Exported macros -----------------------------------------------------------*/
00180 /** @defgroup COMP_Exported_Macros COMP Exported Macros
00181   * @{
00182   */
00183
00184 /** @brief  Reset COMP handle state.
00185   * @param  __HANDLE__  COMP handle.
00186   * @retval None
00187   */
00188 #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
00189 /**
00190   * @}
00191   */
00192
00193 /* Include COMP HAL Extended module */
00194 #include "stm32f3xx_hal_comp_ex.h"
00195
00196 /* Exported functions --------------------------------------------------------*/
00197 /** @addtogroup COMP_Exported_Functions
00198   * @{
00199   */
00200 /** @addtogroup COMP_Exported_Functions_Group1
00201  * @{
00202  */
00203 /* Initialization and de-initialization functions  ****************************/
00204 HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
00205 HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
00206 void              HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
00207 void              HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
00208 /**
00209  * @}
00210  */
00211
00212 /* IO operation functions  *****************************************************/
00213 /** @addtogroup COMP_Exported_Functions_Group2
00214  * @{
00215  */
00216 HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
00217 HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
00218 HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp);
00219 HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);
00220 void              HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
00221 /* Callback in Interrupt mode */
00222 void              HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
00223 /**
00224   * @}
00225   */
00226
00227 /* Peripheral Control functions  ************************************************/
00228 /** @addtogroup COMP_Exported_Functions_Group3
00229  * @{
00230  */
00231 HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
00232 uint32_t          HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
00233 /**
00234   * @}
00235   */
00236
00237 /* Peripheral State functions  **************************************************/
00238 /** @addtogroup COMP_Exported_Functions_Group4
00239   * @{
00240   */
00241 HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
00242 /**
00243   * @}
00244   */
00245
00246 /**
00247   * @}
00248   */
00249
00250 /* Private macros ------------------------------------------------------------*/
00251 /** @defgroup COMP_Private_Macros COMP Private Macros
00252   * @{
00253   */
00254
00255 /** @defgroup COMP_IS_COMP_Definitions COMP Private macros to check input parameters
00256   * @{
00257   */
00258
00259 #define IS_COMP_OUTPUTPOL(__POL__)  (((__POL__) == COMP_OUTPUTPOL_NONINVERTED)  || \
00260                                      ((__POL__) == COMP_OUTPUTPOL_INVERTED))
00261
00262 #define IS_COMP_TRIGGERMODE(__MODE__)  (((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
00263                                         ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
00264                                         ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
00265                                         ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
00266                                         ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
00267                                         ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
00268                                         ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
00269
00270 /**
00271   * @}
00272   */
00273
00274 /**
00275   * @}
00276   */
00277
00278 /**
00279   * @}
00280   */
00281
00282 /**
00283   * @}
00284   */
00285
00286 #ifdef __cplusplus
00287 }
00288 #endif
00289
00290 #endif /* __STM32F3xx_HAL_COMP_H */
00291
00292 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_comp_ex.h Source File

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stm32f3xx_hal_comp_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_comp_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of COMP HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_COMP_EX_H
00038 #define __STM32F3xx_HAL_COMP_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @defgroup COMPEx COMPEx
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /* Exported constants --------------------------------------------------------*/
00057 /** @defgroup COMPEx_Exported_Constants COMP Extended Exported Constants
00058   * @{
00059   */
00060
00061 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00062     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
00063 /** @defgroup COMPEx_InvertingInput  COMP Extended InvertingInput (STM32F302xE/STM32F303xE/STM32F398xx/STM32F302xC/STM32F303xC/STM32F358xx Product devices)
00064   * @{
00065   */
00066 #define COMP_INVERTINGINPUT_1_4VREFINT       (0x00000000U)                        /*!< 1U/4 VREFINT connected to comparator inverting input */
00067 #define COMP_INVERTINGINPUT_1_2VREFINT       COMP_CSR_COMPxINSEL_0                         /*!< 1U/2 VREFINT connected to comparator inverting input */
00068 #define COMP_INVERTINGINPUT_3_4VREFINT       COMP_CSR_COMPxINSEL_1                         /*!< 3U/4 VREFINT connected to comparator inverting input */
00069 #define COMP_INVERTINGINPUT_VREFINT          (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */
00070 #define COMP_INVERTINGINPUT_DAC1_CH1         COMP_CSR_COMPxINSEL_2                         /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
00071 #define COMP_INVERTINGINPUT_DAC1_CH2         (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */
00072 #define COMP_INVERTINGINPUT_IO1              (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA0 for COMP1, PA2 for COMP2, PD15 for COMP3,
00073                                                                                                 PE8 for COMP4, PD13 for COMP5, PD10 for COMP6,
00074                                                                                                 PC0 for COMP7) connected to comparator inverting input */
00075 #define COMP_INVERTINGINPUT_IO2               COMP_CSR_COMPxINSEL                          /*!< IO2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5,
00076                                                                                                PB15 for COMP6) connected to comparator inverting input */
00077 /* Aliases for compatibility */
00078 #define COMP_INVERTINGINPUT_DAC1              COMP_INVERTINGINPUT_DAC1_CH1
00079 #define COMP_INVERTINGINPUT_DAC2              COMP_INVERTINGINPUT_DAC1_CH2
00080 /**
00081   * @}
00082   */
00083 #elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00084 /** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F301x8/STM32F302x8/STM32F318xx Product devices)
00085   * @{
00086   */
00087 #define COMP_INVERTINGINPUT_1_4VREFINT     (0x00000000U)                        /*!< 1U/4 VREFINT connected to comparator inverting input */
00088 #define COMP_INVERTINGINPUT_1_2VREFINT     COMP_CSR_COMPxINSEL_0                         /*!< 1U/2 VREFINT connected to comparator inverting input */
00089 #define COMP_INVERTINGINPUT_3_4VREFINT     COMP_CSR_COMPxINSEL_1                         /*!< 3U/4 VREFINT connected to comparator inverting input */
00090 #define COMP_INVERTINGINPUT_VREFINT        (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */
00091 #define COMP_INVERTINGINPUT_DAC1_CH1       COMP_CSR_COMPxINSEL_2                         /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
00092 #define COMP_INVERTINGINPUT_IO1            (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA2 for COMP2, PB2 for COMP4, PB15 for COMP6)
00093                                                                                               connected to comparator inverting input */
00094 /* Aliases for compatibility */
00095 #define COMP_INVERTINGINPUT_DAC1           COMP_INVERTINGINPUT_DAC1_CH1
00096 /**
00097   * @}
00098   */
00099 #elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
00100 /** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F303x8/STM32F334x8/STM32F328xx Product devices)
00101   * @{
00102   */
00103 /* Note: On these STM32 devices, there is only 1 comparator inverting input   */
00104 /*       connected to a GPIO.                                                 */
00105 /*       It must be chosen among the 2 literals COMP_INVERTINGINPUT_IOx       */
00106 /*       depending on comparator instance COMPx.                              */
00107 #define COMP_INVERTINGINPUT_1_4VREFINT     (0x00000000U)                        /*!< 1U/4 VREFINT connected to comparator inverting input */
00108 #define COMP_INVERTINGINPUT_1_2VREFINT     COMP_CSR_COMPxINSEL_0                         /*!< 1U/2 VREFINT connected to comparator inverting input */
00109 #define COMP_INVERTINGINPUT_3_4VREFINT     COMP_CSR_COMPxINSEL_1                         /*!< 3U/4 VREFINT connected to comparator inverting input */
00110 #define COMP_INVERTINGINPUT_VREFINT        (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */
00111 #define COMP_INVERTINGINPUT_DAC1_CH1       COMP_CSR_COMPxINSEL_2                         /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
00112 #define COMP_INVERTINGINPUT_DAC1_CH2       (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */
00113 #define COMP_INVERTINGINPUT_IO1            (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA2 for COMP2),
00114                                                                                               connected to comparator inverting input */
00115 #define COMP_INVERTINGINPUT_IO2            (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< IO2 (PB2 for COMP4, PB15 for COMP6)
00116                                                                                               connected to comparator inverting input */
00117 #define COMP_INVERTINGINPUT_DAC2_CH1       COMP_CSR_COMPxINSEL_3                         /*!< DAC2_CH1_OUT connected to comparator inverting input */
00118
00119 /* Aliases for compatibility */
00120 #define COMP_INVERTINGINPUT_DAC1           COMP_INVERTINGINPUT_DAC1_CH1
00121 #define COMP_INVERTINGINPUT_DAC2           COMP_INVERTINGINPUT_DAC1_CH2
00122 /**
00123   * @}
00124   */
00125 #elif defined(STM32F373xC) || defined(STM32F378xx)
00126 /** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F373xC/STM32F378xx Product devices)
00127   * @{
00128   */
00129 #define COMP_INVERTINGINPUT_1_4VREFINT  (0x00000000U)                        /*!< 1U/4 VREFINT connected to comparator inverting input */
00130 #define COMP_INVERTINGINPUT_1_2VREFINT  ((uint32_t)COMP_CSR_COMPxINSEL_0)             /*!< 1U/2 VREFINT connected to comparator inverting input */
00131 #define COMP_INVERTINGINPUT_3_4VREFINT  ((uint32_t)COMP_CSR_COMPxINSEL_1)             /*!< 3U/4 VREFINT connected to comparator inverting input */
00132 #define COMP_INVERTINGINPUT_VREFINT     ((uint32_t)(COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0)) /*!< VREFINT connected to comparator inverting input */
00133 #define COMP_INVERTINGINPUT_DAC1_CH1    ((uint32_t)COMP_CSR_COMPxINSEL_2)                         /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
00134 #define COMP_INVERTINGINPUT_DAC1_CH2    ((uint32_t)(COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0)) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */
00135 #define COMP_INVERTINGINPUT_IO1         ((uint32_t)(COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1)) /*!< IO1 (PA0 for COMP1, PA2 for COMP2) connected to comparator inverting input */
00136 #define COMP_INVERTINGINPUT_DAC2_CH1    ((uint32_t)COMP_CSR_COMPxINSEL)                          /*!< DAC2_CH1_OUT connected to comparator inverting input */
00137
00138 /* Aliases for compatibility */
00139 #define COMP_INVERTINGINPUT_DAC1        COMP_INVERTINGINPUT_DAC1_CH1
00140 #define COMP_INVERTINGINPUT_DAC2        COMP_INVERTINGINPUT_DAC1_CH2
00141 /**
00142   * @}
00143   */
00144 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00145        /* STM32F302xC || STM32F303xC || STM32F358xx */
00146
00147 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
00148 /** @defgroup COMPEx_NonInvertingInput  COMP Extended NonInvertingInput (STM32F302xC/STM32F303xC/STM32F358xx Product devices)
00149   * @{
00150   */
00151 #define COMP_NONINVERTINGINPUT_IO1               (0x00000000U) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
00152                                                                              PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
00153                                                                              PA0 for COMP7) connected to comparator non inverting input */
00154 #define COMP_NONINVERTINGINPUT_IO2               COMP_CSR_COMPxNONINSEL /*!< IO2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5,
00155                                                                              PB11 for COMP6, PC1 for COMP7) connected to comparator non inverting input */
00156 #define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED  COMP1_CSR_COMP1SW1     /*!< DAC ouput connected to comparator COMP1 non inverting input */
00157 /**
00158   * @}
00159   */
00160 #elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00161 /** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F301x8/STM32F302x8/STM32F318xx Product devices)
00162   * @{
00163   */
00164 #define COMP_NONINVERTINGINPUT_IO1               (0x00000000U) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6)
00165                                                                              connected to comparator non inverting input */
00166 #define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED  COMP2_CSR_COMP2INPDAC  /*!< DAC ouput connected to comparator COMP2 non inverting input */
00167 /**
00168   * @}
00169   */
00170 #elif defined(STM32F373xC) || defined(STM32F378xx)
00171 /** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F373xC/STM32F378xx Product devices)
00172   * @{
00173   */
00174 #define COMP_NONINVERTINGINPUT_IO1               (0x00000000U) /*!< IO1 (PA1 for COMP1, PA3 for COMP2)
00175                                                                              connected to comparator non inverting input */
00176 #define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED  COMP_CSR_COMP1SW1  /*!< DAC ouput connected to comparator COMP1 non inverting input */
00177 /**
00178   * @}
00179   */
00180 #elif defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
00181 /** @defgroup COMPEx_NonInvertingInput  COMP Extended NonInvertingInput (STM32F302xE/STM32F303xE/STM32F398xx Product devices)
00182   * @{
00183   */
00184 #define COMP_NONINVERTINGINPUT_IO1             (0x00000000U)   /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
00185                                                                             PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
00186                                                                             PA0 for COMP7) connected to comparator non inverting input */
00187 #define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP1_CSR_COMP1SW1      /*!< DAC ouput connected to comparator COMP1 non inverting input */
00188 /**
00189   * @}
00190   */
00191 #else
00192 /** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (Other Product devices)
00193   * @{
00194   */
00195 #define COMP_NONINVERTINGINPUT_IO1             (0x00000000U) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6)
00196                                                                            connected to comparator non inverting input */
00197 /**
00198   * @}
00199   */
00200 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
00201
00202 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00203 /** @defgroup COMPEx_Output COMP Extended Output (STM32F301x8/STM32F302x8/STM32F318xx Product devices)
00204   *        Elements value convention on 16 LSB: 00XXXX0000YYYYYYb
00205   *           - YYYYYY : Applicable comparator instance number (bitmap format: 000010 for COMP2, 100000 for COMP6)
00206   *           - XXXX   : COMPxOUTSEL value
00207   * @{
00208   */
00209 /* Output Redirection values common to all comparators COMP2, COMP4 and COMP6 */
00210 #define COMP_OUTPUT_NONE                  (0x0000002AU)   /*!< COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
00211 #define COMP_OUTPUT_TIM1BKIN              (0x0000042AU)   /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
00212 #define COMP_OUTPUT_TIM1BKIN2_BRK2        (0x0000082AU)   /*!< COMP2, COMP4 or COMP6  output connected to TIM1 Break Input 2 (BRK2) */
00213 #define COMP_OUTPUT_TIM1BKIN2             (0x0000142AU)   /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
00214 /* Output Redirection specific to COMP2 */
00215 #define COMP_OUTPUT_TIM1OCREFCLR          (0x00001802U)   /*!< COMP2 output connected to TIM1 OCREF Clear */
00216 #define COMP_OUTPUT_TIM1IC1               (0x00001C02U)   /*!< COMP2 output connected to TIM1 Input Capture 1U */
00217 #define COMP_OUTPUT_TIM2IC4               (0x00002002U)   /*!< COMP2 output connected to TIM2 Input Capture 4U */
00218 #define COMP_OUTPUT_TIM2OCREFCLR          (0x00002402U)   /*!< COMP2 output connected to TIM2 OCREF Clear */
00219 /* Output Redirection specific to COMP4 */
00220 #define COMP_OUTPUT_TIM15IC2              (0x00002008U)   /*!< COMP4 output connected to TIM15 Input Capture 2U */
00221 #define COMP_OUTPUT_TIM15OCREFCLR         (0x00002808U)   /*!< COMP4 output connected to TIM15 OCREF Clear */
00222 /* Output Redirection specific to COMP6 */
00223 #define COMP_OUTPUT_TIM2IC2               (0x00001820U)   /*!< COMP6 output connected to TIM2 Input Capture 2U */
00224 #define COMP_OUTPUT_COMP6_TIM2OCREFCLR    (0x00002020U)   /*!< COMP6 output connected to TIM2 OCREF Clear */
00225 #define COMP_OUTPUT_TIM16OCREFCLR         (0x00002420U)   /*!< COMP6 output connected to TIM16 OCREF Clear */
00226 #define COMP_OUTPUT_TIM16IC1              (0x00002820U)   /*!< COMP6 output connected to TIM16 Input Capture 1U */
00227 /**
00228   * @}
00229   */
00230 #elif  defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
00231 /** @defgroup COMPEx_Output COMP Extended Output (STM32F303x8/STM32F334x8/STM32F328xx Product devices)
00232   *        Elements value convention on 16 LSB: 00XXXX0000YYYYYYb
00233   *           - YYYYYY : Applicable comparator instance number (bitmap format: 000010 for COMP2, 100000 for COMP6)
00234   *           - XXXX   : COMPxOUTSEL value
00235   * @{
00236   */
00237 /* Output Redirection values common to all comparators COMP2, COMP4 and COMP6 */
00238 #define COMP_OUTPUT_NONE                  (0x0000002AU)   /*!< COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
00239 #define COMP_OUTPUT_TIM1BKIN              (0x0000042AU)   /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
00240 #define COMP_OUTPUT_TIM1BKIN2             (0x0000082AU)   /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
00241 /* Output Redirection common to COMP2 and COMP4 */
00242 #define COMP_OUTPUT_TIM3OCREFCLR          (0x00002C0AU)   /*!< COMP2 or COMP4 output connected to TIM3 OCREF Clear */
00243 /* Output Redirection specific to COMP2 */
00244 #define COMP_OUTPUT_TIM1OCREFCLR          (0x00001802U)   /*!< COMP2 output connected to TIM1 OCREF Clear */
00245 #define COMP_OUTPUT_TIM1IC1               (0x00001C02U)   /*!< COMP2 output connected to TIM1 Input Capture 1U */
00246 #define COMP_OUTPUT_TIM2IC4               (0x00002002U)   /*!< COMP2 output connected to TIM2 Input Capture 4U */
00247 #define COMP_OUTPUT_TIM2OCREFCLR          (0x00002402U)   /*!< COMP2 output connected to TIM2 OCREF Clear */
00248 #define COMP_OUTPUT_TIM3IC1               (0x00002802U)   /*!< COMP2 output connected to TIM3 Input Capture 1U */
00249 /* Output Redirection specific to COMP4 */
00250 #define COMP_OUTPUT_TIM3IC3               (0x00001808U)   /*!< COMP4 output connected to TIM3 Input Capture 3U */
00251 #define COMP_OUTPUT_TIM15IC2              (0x00002008U)   /*!< COMP4 output connected to TIM15 Input Capture 2U */
00252 #define COMP_OUTPUT_TIM15OCREFCLR         (0x00002808U)   /*!< COMP4 output connected to TIM15 OCREF Clear */
00253 /* Output Redirection specific to COMP6 */
00254 #define COMP_OUTPUT_TIM2IC2               (0x00001820U)   /*!< COMP6 output connected to TIM2 Input Capture 2U */
00255 #define COMP_OUTPUT_COMP6_TIM2OCREFCLR    (0x00002020U)   /*!< COMP6 output connected to TIM2 OCREF Clear */
00256 #define COMP_OUTPUT_TIM16OCREFCLR         (0x00002420U)   /*!< COMP6 output connected to TIM16 OCREF Clear */
00257 #define COMP_OUTPUT_TIM16IC1              (0x00002820U)   /*!< COMP6 output connected to TIM16 Input Capture 1U */
00258 /**
00259   * @}
00260   */
00261 #elif  defined(STM32F302xC) || defined(STM32F302xE)
00262 /** @defgroup COMPEx_Output COMP Extended Output (STM32F302xC/STM32F302xE Product devices)
00263   *        Elements value convention on 16 LSB: 00XXXX0000YYYYYYb
00264   *           - YYYYYY : Applicable comparator instance number (bitmap format: 000001 for COMP1, 100000 for COMP6)
00265   *           - XXXX   : COMPxOUTSEL value
00266   * @{
00267   */
00268 /* Output Redirection values common to all comparators COMP1, COMP2, COMP4, COMP6 */
00269 #define COMP_OUTPUT_NONE                  (0x0000002BU)   /*!< COMP1, COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
00270 #define COMP_OUTPUT_TIM1BKIN              (0x0000042BU)   /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
00271 #define COMP_OUTPUT_TIM1BKIN2_BRK2        (0x0000082BU)   /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BRK2) */
00272 #define COMP_OUTPUT_TIM1BKIN2             (0x0000142BU)   /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
00273 /* Output Redirection common to COMP1 and COMP2 */
00274 #define COMP_OUTPUT_TIM1OCREFCLR          (0x00001803U)   /*!< COMP1 or COMP2 output connected to TIM1 OCREF Clear */
00275 #define COMP_OUTPUT_TIM1IC1               (0x00001C03U)   /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1U */
00276 #define COMP_OUTPUT_TIM2IC4               (0x00002003U)   /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */
00277 #define COMP_OUTPUT_TIM2OCREFCLR          (0x00002403U)   /*!< COMP1 or COMP2 output connected to TIM2 OCREF Clear */
00278 #define COMP_OUTPUT_TIM3IC1               (0x00002803U)   /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1U */
00279 /* Output Redirection common to COMP1,COMP2 and COMP4 */
00280 #define COMP_OUTPUT_TIM3OCREFCLR          (0x00002C0BU)   /*!< COMP1, COMP2 or COMP4 output connected to TIM3 OCREF Clear */
00281 /* Output Redirection specific to COMP4 */
00282 #define COMP_OUTPUT_TIM3IC3               (0x00001808U)   /*!< COMP4 output connected to TIM3 Input Capture 3U */
00283 #define COMP_OUTPUT_TIM15IC2              (0x00002008U)   /*!< COMP4 output connected to TIM15 Input Capture 2U */
00284 #define COMP_OUTPUT_TIM4IC2               (0x00002408U)   /*!< COMP4 output connected to TIM4 Input Capture 2U */
00285 #define COMP_OUTPUT_TIM15OCREFCLR         (0x00002808U)   /*!< COMP4 output connected to TIM15 OCREF Clear */
00286 /* Output Redirection specific to COMP6 */
00287 #define COMP_OUTPUT_TIM2IC2               (0x00001820U)   /*!< COMP6 output connected to TIM2 Input Capture 2U */
00288 #define COMP_OUTPUT_COMP6_TIM2OCREFCLR    (0x00002020U)   /*!< COMP6 output connected to TIM2 OCREF Clear */
00289 #define COMP_OUTPUT_TIM16OCREFCLR         (0x00002420U)   /*!< COMP6 output connected to TIM16 OCREF Clear */
00290 #define COMP_OUTPUT_TIM16IC1              (0x00002820U)   /*!< COMP6 output connected to TIM16 Input Capture 1U */
00291 #define COMP_OUTPUT_TIM4IC4               (0x00002C20U)   /*!< COMP6 output connected to TIM4 Input Capture 4U */
00292 /**
00293   * @}
00294   */
00295 #elif  defined(STM32F303xC) || defined(STM32F358xx)
00296 /** @defgroup COMPEx_Output COMP Extended Output (STM32F303xC/STM32F358xx Product devices)
00297   *        Elements value convention on 16 LSB: 00XXXX000YYYYYYYb
00298   *           - YYYYYYY : Applicable comparator instance number (bitmap format: 0000001 for COMP1, 1000000 for COMP7)
00299   *           - XXXX    : COMPxOUTSEL value
00300   * @{
00301   */
00302 /* Output Redirection values common to all comparators COMP1...COMP7 */
00303 #define COMP_OUTPUT_NONE                  (0x0000007FU)   /*!< COMP1, COMP2... or COMP7 output isn't connected to other peripherals */
00304 #define COMP_OUTPUT_TIM1BKIN              (0x0000047FU)   /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input (BKIN) */
00305 #define COMP_OUTPUT_TIM1BKIN2             (0x0000087FU)   /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 (BKIN2) */
00306 #define COMP_OUTPUT_TIM8BKIN              (0x00000C7FU)   /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input (BKIN) */
00307 #define COMP_OUTPUT_TIM8BKIN2             (0x0000107FU)   /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input 2 (BKIN2) */
00308 #define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2   (0x0000147FU)   /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 and TIM8 Break Input 2U */
00309 /* Output Redirection common to COMP1, COMP2, COMP3 and COMP7 */
00310 #define COMP_OUTPUT_TIM1OCREFCLR          (0x00001847U)   /*!< COMP1, COMP2, COMP3 or COMP7 output connected to TIM1 OCREF Clear */
00311 /* Output Redirection common to COMP1, COMP2 and COMP3 */
00312 #define COMP_OUTPUT_TIM2OCREFCLR          (0x00002407U)   /*!< COMP1, COMP2 or COMP3 output connected to TIM2 OCREF Clear */
00313 /* Output Redirection common to COMP1, COMP2, COMP4 and COMP5 */
00314 #define COMP_OUTPUT_TIM3OCREFCLR          (0x00002C1BU)   /*!< COMP1, COMP2, COMP4 or COMP5 output connected to TIM3 OCREF Clear */
00315 /* Output Redirection common to COMP4, COMP5, COMP6 and COMP7 */
00316 #define COMP_OUTPUT_TIM8OCREFCLR          (0x00001C78U)   /*!< COMP4, COMP5, COMP6 or COMP7 output connected to TIM8 OCREF Clear */
00317 /* Output Redirection common to COMP1 and COMP2 */
00318 #define COMP_OUTPUT_TIM1IC1               (0x00001C03U)   /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1U */
00319 #define COMP_OUTPUT_TIM2IC4               (0x00002003U)   /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */
00320 #define COMP_OUTPUT_TIM3IC1               (0x00002803U)   /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1U */
00321 /* Output Redirection specific to COMP3 */
00322 #define COMP_OUTPUT_TIM4IC1               (0x00001C04U)   /*!< COMP3 output connected to TIM4 Input Capture 1U */
00323 #define COMP_OUTPUT_TIM3IC2               (0x00002004U)   /*!< COMP3 output connected to TIM3 Input Capture 2U */
00324 #define COMP_OUTPUT_TIM15IC1              (0x00002804U)   /*!< COMP3 output connected to TIM15 Input Capture 1U */
00325 #define COMP_OUTPUT_TIM15BKIN             (0x00002C04U)   /*!< COMP3 output connected to TIM15 Break Input (BKIN) */
00326 /* Output Redirection specific to COMP4 */
00327 #define COMP_OUTPUT_TIM3IC3               (0x00001808U)   /*!< COMP4 output connected to TIM3 Input Capture 3U */
00328 #define COMP_OUTPUT_TIM15IC2              (0x00002008U)   /*!< COMP4 output connected to TIM15 Input Capture 2U */
00329 #define COMP_OUTPUT_TIM4IC2               (0x00002408U)   /*!< COMP4 output connected to TIM4 Input Capture 2U */
00330 #define COMP_OUTPUT_TIM15OCREFCLR         (0x00002808U)   /*!< COMP4 output connected to TIM15 OCREF Clear */
00331 /* Output Redirection specific to COMP5 */
00332 #define COMP_OUTPUT_TIM2IC1               (0x00001810U)   /*!< COMP5 output connected to TIM2 Input Capture 1U */
00333 #define COMP_OUTPUT_TIM17IC1              (0x00002010U)   /*!< COMP5 output connected to TIM17 Input Capture 1U */
00334 #define COMP_OUTPUT_TIM4IC3               (0x00002410U)   /*!< COMP5 output connected to TIM4 Input Capture 3U */
00335 #define COMP_OUTPUT_TIM16BKIN             (0x00002810U)   /*!< COMP5 output connected to TIM16 Break Input (BKIN) */
00336 /* Output Redirection specific to COMP6 */
00337 #define COMP_OUTPUT_TIM2IC2               (0x00001820U)   /*!< COMP6 output connected to TIM2 Input Capture 2U */
00338 #define COMP_OUTPUT_COMP6_TIM2OCREFCLR    (0x00002020U)   /*!< COMP6 output connected to TIM2 OCREF Clear */
00339 #define COMP_OUTPUT_TIM16OCREFCLR         (0x00002420U)   /*!< COMP6 output connected to TIM16 OCREF Clear */
00340 #define COMP_OUTPUT_TIM16IC1              (0x00002820U)   /*!< COMP6 output connected to TIM16 Input Capture 1U */
00341 #define COMP_OUTPUT_TIM4IC4               (0x00002C20U)   /*!< COMP6 output connected to TIM4 Input Capture 4U */
00342 /* Output Redirection specific to COMP7 */
00343 #define COMP_OUTPUT_TIM2IC3               (0x00002040U)   /*!< COMP7 output connected to TIM2 Input Capture 3U */
00344 #define COMP_OUTPUT_TIM1IC2               (0x00002440U)   /*!< COMP7 output connected to TIM1 Input Capture 2U */
00345 #define COMP_OUTPUT_TIM17OCREFCLR         (0x00002840U)   /*!< COMP7 output connected to TIM17 OCREF Clear */
00346 #define COMP_OUTPUT_TIM17BKIN             (0x00002C40U)   /*!< COMP7 output connected to TIM17 Break Input (BKIN) */
00347 /**
00348   * @}
00349   */
00350 #elif defined(STM32F303xE) || defined(STM32F398xx)
00351 /** @defgroup COMPEx_Output COMP Extended Output (STM32F303xE/STM32F398xx Product devices)
00352   *        Elements value convention on 16 LSB: 00XXXX000YYYYYYYb
00353   *           - YYYYYYY : Applicable comparator instance number (bitmap format: 0000001 for COMP1, 1000000 for COMP7)
00354   *           - XXXX    : COMPxOUTSEL value
00355   * @{
00356   */
00357 /* Output Redirection values common to all comparators COMP1...COMP7 */
00358 #define COMP_OUTPUT_NONE                  (0x0000007FU)   /*!< COMP1, COMP2... or COMP7 output isn't connected to other peripherals */
00359 #define COMP_OUTPUT_TIM1BKIN              (0x0000047FU)   /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input (BKIN) */
00360 #define COMP_OUTPUT_TIM1BKIN2             (0x0000087FU)   /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 (BKIN2) */
00361 #define COMP_OUTPUT_TIM8BKIN              (0x00000C7FU)   /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input (BKIN) */
00362 #define COMP_OUTPUT_TIM8BKIN2             (0x0000107FU)   /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input 2 (BKIN2) */
00363 #define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2   (0x0000147FU)   /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 and TIM8 Break Input 2U */
00364 #define COMP_OUTPUT_TIM20BKIN             (0x0000307FU)   /*!< COMP1, COMP2... or COMP7 output connected to TIM20 Break Input (BKIN) */
00365 #define COMP_OUTPUT_TIM20BKIN2            (0x0000347FU)   /*!< COMP1, COMP2... or COMP7 output connected to TIM20 Break Input 2 (BKIN2) */
00366 #define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2    (0x0000387FU)   /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2U, TIM8 Break Input 2 and TIM20 Break Input 2  */
00367 /* Output Redirection common to COMP1, COMP2, COMP3 and COMP7 */
00368 #define COMP_OUTPUT_TIM1OCREFCLR          (0x00001847U)   /*!< COMP1, COMP2, COMP3 or COMP7 output connected to TIM1 OCREF Clear */
00369 /* Output Redirection common to COMP1, COMP2 and COMP3 */
00370 #define COMP_OUTPUT_TIM2OCREFCLR          (0x00002407U)   /*!< COMP1, COMP2 or COMP3 output connected to TIM2 OCREF Clear */
00371 /* Output Redirection common to COMP1, COMP2, COMP4 and COMP5 */
00372 #define COMP_OUTPUT_TIM3OCREFCLR          (0x00002C1BU)   /*!< COMP1, COMP2, COMP4 or COMP5 output connected to TIM3 OCREF Clear */
00373 /* Output Redirection common to COMP4, COMP5, COMP6 and COMP7 */
00374 #define COMP_OUTPUT_TIM8OCREFCLR          (0x00001C78U)   /*!< COMP4, COMP5, COMP6 or COMP7 output connected to TIM8 OCREF Clear */
00375 /* Output Redirection common to COMP1 and COMP2 */
00376 #define COMP_OUTPUT_TIM1IC1               (0x00001C03U)   /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1U */
00377 #define COMP_OUTPUT_TIM2IC4               (0x00002003U)   /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */
00378 #define COMP_OUTPUT_TIM3IC1               (0x00002803U)   /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1U */
00379 /* Output Redirection specific to COMP2 */
00380 #define COMP_OUTPUT_TIM20OCREFCLR         (0x00003C04U)   /*!< COMP2 output connected to TIM20 OCREF Clear */
00381 /* Output Redirection specific to COMP3 */
00382 #define COMP_OUTPUT_TIM4IC1               (0x00001C04U)   /*!< COMP3 output connected to TIM4 Input Capture 1U */
00383 #define COMP_OUTPUT_TIM3IC2               (0x00002004U)   /*!< COMP3 output connected to TIM3 Input Capture 2U */
00384 #define COMP_OUTPUT_TIM15IC1              (0x00002804U)   /*!< COMP3 output connected to TIM15 Input Capture 1U */
00385 #define COMP_OUTPUT_TIM15BKIN             (0x00002C04U)   /*!< COMP3 output connected to TIM15 Break Input (BKIN) */
00386 /* Output Redirection specific to COMP4 */
00387 #define COMP_OUTPUT_TIM3IC3               (0x00001808U)   /*!< COMP4 output connected to TIM3 Input Capture 3U */
00388 #define COMP_OUTPUT_TIM15IC2              (0x00002008U)   /*!< COMP4 output connected to TIM15 Input Capture 2U */
00389 #define COMP_OUTPUT_TIM4IC2               (0x00002408U)   /*!< COMP4 output connected to TIM4 Input Capture 2U */
00390 #define COMP_OUTPUT_TIM15OCREFCLR         (0x00002808U)   /*!< COMP4 output connected to TIM15 OCREF Clear */
00391 /* Output Redirection specific to COMP5 */
00392 #define COMP_OUTPUT_TIM2IC1               (0x00001810U)   /*!< COMP5 output connected to TIM2 Input Capture 1U */
00393 #define COMP_OUTPUT_TIM17IC1              (0x00002010U)   /*!< COMP5 output connected to TIM17 Input Capture 1U */
00394 #define COMP_OUTPUT_TIM4IC3               (0x00002410U)   /*!< COMP5 output connected to TIM4 Input Capture 3U */
00395 #define COMP_OUTPUT_TIM16BKIN             (0x00002810U)   /*!< COMP5 output connected to TIM16 Break Input (BKIN) */
00396 /* Output Redirection specific to COMP6 */
00397 #define COMP_OUTPUT_TIM2IC2               (0x00001820U)   /*!< COMP6 output connected to TIM2 Input Capture 2U */
00398 #define COMP_OUTPUT_COMP6_TIM2OCREFCLR    (0x00002020U)   /*!< COMP6 output connected to TIM2 OCREF Clear */
00399 #define COMP_OUTPUT_TIM16OCREFCLR         (0x00002420U)   /*!< COMP6 output connected to TIM16 OCREF Clear */
00400 #define COMP_OUTPUT_TIM16IC1              (0x00002820U)   /*!< COMP6 output connected to TIM16 Input Capture 1U */
00401 #define COMP_OUTPUT_TIM4IC4               (0x00002C20U)   /*!< COMP6 output connected to TIM4 Input Capture 4U */
00402 /* Output Redirection specific to COMP7 */
00403 #define COMP_OUTPUT_TIM2IC3               (0x00002040U)   /*!< COMP7 output connected to TIM2 Input Capture 3U */
00404 #define COMP_OUTPUT_TIM1IC2               (0x00002440U)   /*!< COMP7 output connected to TIM1 Input Capture 2U */
00405 #define COMP_OUTPUT_TIM17OCREFCLR         (0x00002840U)   /*!< COMP7 output connected to TIM17 OCREF Clear */
00406 #define COMP_OUTPUT_TIM17BKIN             (0x00002C40U)   /*!< COMP7 output connected to TIM17 Break Input (BKIN) */
00407 /**
00408   * @}
00409   */
00410 #elif  defined(STM32F373xC) || defined(STM32F378xx)
00411 /** @defgroup COMPEx_Output COMP Extended Output (STM32F373xC/STM32F378xx Product devices)
00412   *        Elements value convention: 00000XXX000000YYb
00413   *           - YY   : Applicable comparator instance number (bitmap format: 01 for COMP1, 10 for COMP2)
00414   *           - XXX  : COMPxOUTSEL value
00415   * @{
00416   */
00417 /* Output Redirection values common to all comparators COMP1 and COMP2 */
00418 #define COMP_OUTPUT_NONE                  (0x0003U)   /*!< COMP1 or COMP2 output isn't connected to other peripherals */
00419 #define COMP_OUTPUT_TIM2IC4               (0x0403U)   /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */
00420 #define COMP_OUTPUT_TIM2OCREFCLR          (0x0503U)   /*!< COMP1 or COMP2 output connected to TIM2 OCREF Clear */
00421 /* Output Redirection specific to COMP1 */
00422 #define COMP_OUTPUT_TIM15BKIN             (0x0101U)   /*!< COMP1 output connected to TIM15 Break Input */
00423 #define COMP_OUTPUT_COMP1_TIM3IC1         (0x0201U)   /*!< COMP1 output connected to TIM3 Input Capture 1U */
00424 #define COMP_OUTPUT_COMP1_TIM3OCREFCLR    (0x0301U)   /*!< COMP1 output connected to TIM3 OCREF Clear */
00425 #define COMP_OUTPUT_TIM5IC4               (0x0601U)   /*!< COMP1 output connected to TIM5 Input Capture 4U */
00426 #define COMP_OUTPUT_TIM5OCREFCLR          (0x0701U)   /*!< COMP1 output connected to TIM5 OCREF Clear */
00427 /* Output Redirection specific to COMP2 */
00428 #define COMP_OUTPUT_TIM16BKIN             (0x0102U)   /*!< COMP2 output connected to TIM16 Break Input */
00429 #define COMP_OUTPUT_TIM4IC1               (0x0202U)   /*!< COMP2 output connected to TIM4 Input Capture 1U */
00430 #define COMP_OUTPUT_TIM4OCREFCLR          (0x0302U)   /*!< COMP2 output connected to TIM4 OCREF Clear */
00431 #define COMP_OUTPUT_COMP2_TIM3IC1         (0x0602U)   /*!< COMP2 output connected to TIM3 Input Capture 1U */
00432 #define COMP_OUTPUT_COMP2_TIM3OCREFCLR    (0x0702U)   /*!< COMP2 output connected to TIM3 OCREF Clear */
00433 /**
00434   * @}
00435   */
00436 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
00437
00438 #if  defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
00439 /** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F302xC/STM32F303xC/STM32F358xx Product devices)
00440   * @{
00441   */
00442 #define COMP_WINDOWMODE_DISABLE           (0x00000000U)  /*!< Window mode disabled */
00443 #define COMP_WINDOWMODE_ENABLE            COMP_CSR_COMPxWNDWEN    /*!< Window mode enabled: non inverting input of comparator X (x=2U,4,6U)
00444                                                                        is connected to the non inverting input of comparator X-1U */
00445 /**
00446   * @}
00447   */
00448 #elif defined(STM32F373xC) || defined(STM32F378xx)
00449 /** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F373xC/STM32F378xx Product devices)
00450   * @{
00451   */
00452 #define COMP_WINDOWMODE_DISABLE           (0x00000000U)  /*!< Window mode disabled */
00453 #define COMP_WINDOWMODE_ENABLE            ((uint32_t)COMP_CSR_COMPxWNDWEN) /*!< Window mode enabled: non inverting input of comparator 2
00454                                                                                 is connected to the non inverting input of comparator 1 (PA1) */
00455 /**
00456   * @}
00457   */
00458 #else
00459 /** @defgroup COMPEx_WindowMode COMP Extended WindowMode (Other Product devices)
00460   * @{
00461   */
00462 #define COMP_WINDOWMODE_DISABLE           (0x00000000U)  /*!< Window mode disabled (not available) */
00463 /**
00464   * @}
00465   */
00466 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
00467
00468 /** @defgroup COMPEx_Mode COMP Extended Mode
00469   * @{
00470   */
00471 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00472     defined(STM32F373xC) || defined(STM32F378xx)
00473
00474 /* Please refer to the electrical characteristics in the device datasheet for
00475    the power consumption values */
00476 #define COMP_MODE_HIGHSPEED               (0x00000000U) /*!< High Speed */
00477 #define COMP_MODE_MEDIUMSPEED             COMP_CSR_COMPxMODE_0   /*!< Medium Speed */
00478 #define COMP_MODE_LOWPOWER                COMP_CSR_COMPxMODE_1   /*!< Low power mode */
00479 #define COMP_MODE_ULTRALOWPOWER           COMP_CSR_COMPxMODE     /*!< Ultra-low power mode */
00480
00481 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
00482        /* STM32F373xC || STM32F378xx */
00483 /**
00484   * @}
00485   */
00486
00487 /** @defgroup COMPEx_Hysteresis COMP Extended Hysteresis
00488   * @{
00489   */
00490 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00491     defined(STM32F373xC) || defined(STM32F378xx)
00492
00493 #define COMP_HYSTERESIS_NONE              (0x00000000U)  /*!< No hysteresis */
00494 #define COMP_HYSTERESIS_LOW               COMP_CSR_COMPxHYST_0    /*!< Hysteresis level low */
00495 #define COMP_HYSTERESIS_MEDIUM            COMP_CSR_COMPxHYST_1    /*!< Hysteresis level medium */
00496 #define COMP_HYSTERESIS_HIGH              COMP_CSR_COMPxHYST      /*!< Hysteresis level high */
00497
00498 #else
00499
00500 #define COMP_HYSTERESIS_NONE              (0x00000000U)  /*!< No hysteresis */
00501
00502 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
00503        /* STM32F373xC || STM32F378xx */
00504 /**
00505   * @}
00506   */
00507
00508 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
00509     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
00510 /** @defgroup COMPEx_BlankingSrce  COMP Extended Blanking Source (STM32F301x8/STM32F302x8/STM32F303x8/STM32F334x8/STM32F318xx/STM32F328xx Product devices)
00511   * @{
00512   */
00513 /* No blanking source can be selected for all comparators */
00514 #define COMP_BLANKINGSRCE_NONE                 (0x00000000U)    /*!< No blanking source */
00515 /* Blanking source for COMP2 */
00516 #define COMP_BLANKINGSRCE_TIM1OC5              COMP_CSR_COMPxBLANKING_0  /*!< TIM1 OC5 selected as blanking source for COMP2 */
00517 #define COMP_BLANKINGSRCE_TIM2OC3              COMP_CSR_COMPxBLANKING_1  /*!< TIM2 OC3 selected as blanking source for COMP2 */
00518 #define COMP_BLANKINGSRCE_TIM3OC3              (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1)    /*!< TIM3 OC3 selected as blanking source for COMP2 */
00519 /* Blanking source for COMP4 */
00520 #define COMP_BLANKINGSRCE_TIM3OC4              COMP_CSR_COMPxBLANKING_0    /*!< TIM3 OC4 selected as blanking source for COMP4 */
00521 #define COMP_BLANKINGSRCE_TIM15OC1             (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1)    /*!< TIM15 OC1 selected as blanking source for COMP4 */
00522 /* Blanking source for COMP6 */
00523 #define COMP_BLANKINGSRCE_TIM2OC4              (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1)    /*!< TIM2 OC4 selected as blanking source for COMP6 */
00524 #define COMP_BLANKINGSRCE_TIM15OC2             COMP_CSR_COMPxBLANKING_2    /*!< TIM15 OC2 selected as blanking source for COMP6 */
00525 /**
00526   * @}
00527   */
00528
00529 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
00530        /* STM32F303x8 || STM32F334x8 || STM32F328xx */
00531
00532 #if defined(STM32F302xE) ||\
00533     defined(STM32F302xC)
00534 /** @defgroup COMPEx_BlankingSrce COMP Extended Blanking Source (STM32F302xE/STM32F302xC Product devices)
00535   * @{
00536   */
00537 /* No blanking source can be selected for all comparators */
00538 #define COMP_BLANKINGSRCE_NONE                 (0x00000000U)    /*!< No blanking source */
00539 /* Blanking source common for COMP1 and COMP2 */
00540 #define COMP_BLANKINGSRCE_TIM1OC5              COMP_CSR_COMPxBLANKING_0  /*!< TIM1 OC5 selected as blanking source for COMP1 and COMP2 */
00541 /* Blanking source common for COMP1 and COMP2 */
00542 #define COMP_BLANKINGSRCE_TIM2OC3              COMP_CSR_COMPxBLANKING_1  /*!< TIM2 OC3 selected as blanking source for COMP1 and COMP2 */
00543 /* Blanking source common for COMP1 and COMP2 */
00544 #define COMP_BLANKINGSRCE_TIM3OC3              (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1)    /*!< TIM3 OC3 selected as blanking source for COMP1 and COMP2 */
00545 /* Blanking source for COMP4 */
00546 #define COMP_BLANKINGSRCE_TIM3OC4              COMP_CSR_COMPxBLANKING_0    /*!< TIM3 OC4 selected as blanking source for COMP4 */
00547 #define COMP_BLANKINGSRCE_TIM15OC1             (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1)    /*!< TIM15 OC1 selected as blanking source for COMP4 */
00548 /* Blanking source for COMP6 */
00549 #define COMP_BLANKINGSRCE_TIM2OC4              (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1)    /*!< TIM2 OC4 selected as blanking source for COMP6 */
00550 #define COMP_BLANKINGSRCE_TIM15OC2             COMP_CSR_COMPxBLANKING_2    /*!< TIM15 OC2 selected as blanking source for COMP6 */
00551 /**
00552   * @}
00553   */
00554
00555 #endif /* STM32F302xE || */
00556        /* STM32F302xC    */
00557
00558 #if defined(STM32F303xE) || defined(STM32F398xx) || \
00559     defined(STM32F303xC) || defined(STM32F358xx)
00560 /** @defgroup COMPEx_BlankingSrce COMP Extended Blanking Source (STM32F303xE/STM32F398xx/STM32F303xC/STM32F358xx Product devices)
00561   * @{
00562   */
00563 /* No blanking source can be selected for all comparators */
00564 #define COMP_BLANKINGSRCE_NONE                 (0x00000000U)    /*!< No blanking source */
00565 /* Blanking source common for COMP1, COMP2, COMP3 and COMP7 */
00566 #define COMP_BLANKINGSRCE_TIM1OC5              COMP_CSR_COMPxBLANKING_0  /*!< TIM1 OC5 selected as blanking source for COMP1, COMP2, COMP3 and COMP7 */
00567 /* Blanking source common for COMP1 and COMP2 */
00568 #define COMP_BLANKINGSRCE_TIM2OC3              COMP_CSR_COMPxBLANKING_1  /*!< TIM2 OC5 selected as blanking source for COMP1 and COMP2 */
00569 /* Blanking source common for COMP1, COMP2 and COMP5 */
00570 #define COMP_BLANKINGSRCE_TIM3OC3              (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1)    /*!< TIM2 OC3 selected as blanking source for COMP1, COMP2 and COMP5 */
00571 /* Blanking source common for COMP3 and COMP6 */
00572 #define COMP_BLANKINGSRCE_TIM2OC4              (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1)    /*!< TIM2 OC4 selected as blanking source for COMP3 and COMP6 */
00573 /* Blanking source common for COMP4, COMP5, COMP6 and COMP7 */
00574 #define COMP_BLANKINGSRCE_TIM8OC5              COMP_CSR_COMPxBLANKING_1  /*!< TIM8 OC5 selected as blanking source for COMP4, COMP5, COMP6 and COMP7 */
00575 /* Blanking source for COMP4 */
00576 #define COMP_BLANKINGSRCE_TIM3OC4              COMP_CSR_COMPxBLANKING_0  /*!< TIM3 OC4 selected as blanking source for COMP4 */
00577 #define COMP_BLANKINGSRCE_TIM15OC1             (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1)    /*!< TIM15 OC1 selected as blanking source for COMP4 */
00578 /* Blanking source common for COMP6 and COMP7 */
00579 #define COMP_BLANKINGSRCE_TIM15OC2             COMP_CSR_COMPxBLANKING_2  /*!< TIM15 OC2 selected as blanking source for COMP6 and COMP7 */
00580 /**
00581   * @}
00582   */
00583
00584 #endif /* STM32F303xE || STM32F398xx || */
00585        /* STM32F303xC || STM32F358xx    */
00586
00587 #if defined(STM32F373xC) || defined(STM32F378xx)
00588 /** @defgroup COMPEx_BlankingSrce COMP Extended Blanking Source (STM32F373xC/STM32F378xx Product devices)
00589   * @{
00590   */
00591 /* No blanking source can be selected for all comparators */
00592 #define COMP_BLANKINGSRCE_NONE                 (0x00000000U)     /*!< No blanking source */
00593 /**
00594   * @}
00595   */
00596
00597 #endif /* STM32F373xC || STM32F378xx */
00598
00599 /** @defgroup COMP_Flag COMP Flag
00600   * @{
00601   */
00602 #if defined(STM32F373xC) || defined(STM32F378xx)
00603 #define COMP_FLAG_LOCK                         COMP_CSR_COMP1LOCK      /*!< Lock flag */
00604 #else
00605 #define COMP_FLAG_LOCK                         COMP_CSR_LOCK           /*!< Lock flag */
00606 #endif /* STM32F373xC || STM32F378xx */
00607 /**
00608   * @}
00609   */
00610
00611
00612 /**
00613   * @}
00614   */
00615
00616 /* Exported macro ------------------------------------------------------------*/
00617 /** @defgroup COMPEx_Exported_Macros COMP Extended Exported Macros
00618   * @{
00619   */
00620 #if defined(STM32F373xC) || defined(STM32F378xx)
00621
00622 /**
00623   * @brief  Enable the specified comparator.
00624   * @param  __HANDLE__  COMP handle.
00625   * @retval None
00626   */
00627 #define __HAL_COMP_ENABLE(__HANDLE__)                                          \
00628         do {                                                                   \
00629           uint32_t regshift = COMP_CSR_COMP1_SHIFT;                            \
00630                                                                                \
00631           if((__HANDLE__)->Instance == COMP2)                                  \
00632           {                                                                    \
00633             regshift = COMP_CSR_COMP2_SHIFT;                                   \
00634           }                                                                    \
00635           SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift);          \
00636         } while(0U)
00637
00638 /**
00639   * @brief  Disable the specified comparator.
00640   * @param  __HANDLE__  COMP handle.
00641   * @retval None
00642   */
00643 #define __HAL_COMP_DISABLE(__HANDLE__)                                         \
00644         do {                                                                   \
00645           uint32_t regshift = COMP_CSR_COMP1_SHIFT;                            \
00646                                                                                \
00647           if((__HANDLE__)->Instance == COMP2)                                  \
00648           {                                                                    \
00649             regshift = COMP_CSR_COMP2_SHIFT;                                   \
00650           }                                                                    \
00651           CLEAR_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift);        \
00652         } while(0U)
00653
00654 /**
00655   * @brief  Lock a comparator instance
00656   * @param  __HANDLE__  COMP handle
00657   * @retval None.
00658   */
00659 #define __HAL_COMP_LOCK(__HANDLE__)                                            \
00660         do {                                                                   \
00661           uint32_t regshift = COMP_CSR_COMP1_SHIFT;                            \
00662                                                                                \
00663           if((__HANDLE__)->Instance == COMP2)                                  \
00664           {                                                                    \
00665             regshift = COMP_CSR_COMP2_SHIFT;                                   \
00666           }                                                                    \
00667           SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxLOCK << regshift);        \
00668         } while(0U)
00669
00670 /** @brief  Check whether the specified COMP flag is set or not.
00671   * @param  __HANDLE__  COMP Handle.
00672   * @param  __FLAG__  flag to check.
00673   *        This parameter can be one of the following values:
00674   *            @arg @ref COMP_FLAG_LOCK   lock flag
00675   * @retval The new state of __FLAG__ (TRUE or FALSE).
00676   */
00677 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)                              \
00678         (((__HANDLE__)->Instance == COMP1) ? (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__)) \
00679          (((__HANDLE__)->Instance->CSR & (uint32_t)((__FLAG__) << COMP_CSR_COMP2_SHIFT) == (__FLAG__))))
00680
00681 #else
00682
00683 /**
00684   * @brief  Enable the specified comparator.
00685   * @param  __HANDLE__  COMP handle.
00686   * @retval None
00687   */
00688 #define __HAL_COMP_ENABLE(__HANDLE__)    SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxEN)
00689
00690 /**
00691   * @brief  Disable the specified comparator.
00692   * @param  __HANDLE__  COMP handle.
00693   * @retval None
00694   */
00695 #define __HAL_COMP_DISABLE(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxEN)
00696
00697 /**
00698   * @brief  Lock a comparator instance
00699   * @param  __HANDLE__  COMP handle
00700   * @retval None.
00701   */
00702 #define __HAL_COMP_LOCK(__HANDLE__)      SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxLOCK)
00703
00704 /** @brief  Check whether the specified COMP flag is set or not.
00705   * @param  __HANDLE__  COMP Handle.
00706   * @param  __FLAG__  flag to check.
00707   *        This parameter can be one of the following values:
00708   *            @arg @ref COMP_FLAG_LOCK   lock flag
00709   * @retval The new state of __FLAG__ (TRUE or FALSE).
00710   */
00711 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)     (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__))
00712
00713 #endif /* STM32F373xC || STM32F378xx */
00714
00715 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) ||  \
00716     defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) ||  \
00717     defined(STM32F373xC) || defined(STM32F378xx)
00718
00719 /**
00720   * @brief  Enable the COMP1 EXTI line rising edge trigger.
00721   * @retval None
00722   */
00723 #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
00724
00725 /**
00726   * @brief  Disable the COMP1 EXTI line rising edge trigger.
00727   * @retval None
00728   */
00729 #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
00730
00731 /**
00732   * @brief  Enable the COMP1 EXTI line falling edge trigger.
00733   * @retval None
00734   */
00735 #define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
00736
00737 /**
00738   * @brief  Disable the COMP1 EXTI line falling edge trigger.
00739   * @retval None
00740   */
00741 #define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
00742
00743 /**
00744   * @brief  Enable the COMP1 EXTI line rising & falling edge trigger.
00745   * @retval None
00746   */
00747 #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
00748                                                                __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
00749                                                                __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
00750                                                              } while(0U)
00751
00752 /**
00753   * @brief  Disable the COMP1 EXTI line rising & falling edge trigger.
00754   * @retval None
00755   */
00756 #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00757                                                                __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
00758                                                                __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
00759                                                              } while(0U)
00760
00761 /**
00762   * @brief  Enable the COMP1 EXTI line in interrupt mode.
00763   * @retval None
00764   */
00765 #define __HAL_COMP_COMP1_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
00766
00767 /**
00768   * @brief  Disable the COMP1 EXTI line in interrupt mode.
00769   * @retval None
00770   */
00771 #define __HAL_COMP_COMP1_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
00772
00773 /**
00774   * @brief  Generate a software interrupt on the COMP1 EXTI line.
00775   * @retval None
00776   */
00777 #define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP1)
00778
00779 /**
00780   * @brief  Enable the COMP1 EXTI line in event mode.
00781   * @retval None
00782   */
00783 #define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT()           SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
00784
00785 /**
00786   * @brief  Disable the COMP1 EXTI line in event mode.
00787   * @retval None
00788   */
00789 #define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT()          CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
00790
00791 /**
00792   * @brief  Check whether the COMP1 EXTI line flag is set or not.
00793   * @retval RESET or SET
00794   */
00795 #define __HAL_COMP_COMP1_EXTI_GET_FLAG()              READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1)
00796
00797 /**
00798   * @brief  Clear the COMP1 EXTI flag.
00799   * @retval None
00800   */
00801 #define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP1)
00802
00803 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
00804        /* STM32F302xE || STM32F303xE || STM32F398xx || */
00805        /* STM32F373xC || STM32F378xx */
00806
00807 /**
00808   * @brief  Enable the COMP2 EXTI line rising edge trigger.
00809   * @retval None
00810   */
00811 #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
00812
00813 /**
00814   * @brief  Disable the COMP2 EXTI line rising edge trigger.
00815   * @retval None
00816   */
00817 #define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
00818
00819 /**
00820   * @brief  Enable the COMP2 EXTI line falling edge trigger.
00821   * @retval None
00822   */
00823 #define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
00824
00825 /**
00826   * @brief  Disable the COMP2 EXTI line falling edge trigger.
00827   * @retval None
00828   */
00829 #define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
00830
00831 /**
00832   * @brief  Enable the COMP2 EXTI line rising & falling edge trigger.
00833   * @retval None
00834   */
00835 #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
00836                                                                __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
00837                                                                __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
00838                                                              } while(0U)
00839
00840 /**
00841   * @brief  Disable the COMP2 EXTI line rising & falling edge trigger.
00842   * @retval None
00843   */
00844 #define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()   do { \
00845                                                                __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
00846                                                                __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
00847                                                              } while(0U)
00848
00849 /**
00850   * @brief  Enable the COMP2 EXTI line in interrupt mode.
00851   * @retval None
00852   */
00853 #define __HAL_COMP_COMP2_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
00854
00855 /**
00856   * @brief  Disable the COMP2 EXTI line in interrupt mode.
00857   * @retval None
00858   */
00859 #define __HAL_COMP_COMP2_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
00860
00861 /**
00862   * @brief  Generate a software interrupt on the COMP2 EXTI line.
00863   * @retval None
00864   */
00865 #define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP2)
00866
00867 /**
00868   * @brief  Enable the COMP2 EXTI line in event mode.
00869   * @retval None
00870   */
00871 #define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT()          SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
00872
00873 /**
00874   * @brief  Disable the COMP2 EXTI line in event mode.
00875   * @retval None
00876   */
00877 #define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT()         CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
00878
00879 /**
00880   * @brief  Check whether the COMP2 EXTI line flag is set or not.
00881   * @retval RESET or SET
00882   */
00883 #define __HAL_COMP_COMP2_EXTI_GET_FLAG()              READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2)
00884
00885 /**
00886   * @brief  Clear the COMP2 EXTI flag.
00887   * @retval None
00888   */
00889 #define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2)
00890
00891 #if defined(STM32F303xE) || defined(STM32F398xx) || \
00892     defined(STM32F303xC) || defined(STM32F358xx)
00893
00894 /**
00895   * @brief  Enable the COMP3 EXTI line rising edge trigger.
00896   * @retval None
00897   */
00898 #define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP3)
00899
00900 /**
00901   * @brief  Disable the COMP3 EXTI line rising edge trigger.
00902   * @retval None
00903   */
00904 #define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP3)
00905
00906 /**
00907   * @brief  Enable the COMP3 EXTI line falling edge trigger.
00908   * @retval None
00909   */
00910 #define __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP3)
00911
00912 /**
00913   * @brief  Disable the COMP3 EXTI line falling edge trigger.
00914   * @retval None
00915   */
00916 #define __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP3)
00917
00918 /**
00919   * @brief  Enable the COMP3 EXTI line rising & falling edge trigger.
00920   * @retval None
00921   */
00922 #define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
00923                                                                __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE(); \
00924                                                                __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE(); \
00925                                                              } while(0U)
00926
00927 /**
00928   * @brief  Disable the COMP3 EXTI line rising & falling edge trigger.
00929   * @retval None
00930   */
00931 #define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE()   do { \
00932                                                                __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE(); \
00933                                                                __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE(); \
00934                                                              } while(0U)
00935
00936 /**
00937   * @brief  Enable the COMP3 EXTI line in interrupt mode.
00938   * @retval None
00939   */
00940 #define __HAL_COMP_COMP3_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP3)
00941
00942 /**
00943   * @brief  Disable the COMP3 EXTI line in interrupt mode.
00944   * @retval None
00945   */
00946 #define __HAL_COMP_COMP3_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP3)
00947
00948 /**
00949   * @brief  Generate a software interrupt on the COMP3 EXTI line.
00950   * @retval None
00951   */
00952 #define __HAL_COMP_COMP3_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP3)
00953
00954 /**
00955   * @brief  Enable the COMP3 EXTI line in event mode.
00956   * @retval None
00957   */
00958 #define __HAL_COMP_COMP3_EXTI_ENABLE_EVENT()          SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP3)
00959
00960 /**
00961   * @brief  Disable the COMP3 EXTI line in event mode.
00962   * @retval None
00963   */
00964 #define __HAL_COMP_COMP3_EXTI_DISABLE_EVENT()         CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP3)
00965
00966 /**
00967   * @brief  Check whether the COMP3 EXTI line flag is set or not.
00968   * @retval RESET or SET
00969   */
00970 #define __HAL_COMP_COMP3_EXTI_GET_FLAG()              READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP3)
00971
00972 /**
00973   * @brief  Clear the COMP3 EXTI flag.
00974   * @retval None
00975   */
00976 #define __HAL_COMP_COMP3_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP3)
00977
00978 #endif /* STM32F303xE || STM32F398xx || */
00979        /* STM32F303xC || STM32F358xx    */
00980
00981 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) ||  \
00982     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) ||  \
00983     defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) ||  \
00984     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
00985
00986 /**
00987   * @brief  Enable the COMP4 EXTI line rising edge trigger.
00988   * @retval None
00989   */
00990 #define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP4)
00991
00992 /**
00993   * @brief  Disable the COMP4 EXTI line rising edge trigger.
00994   * @retval None
00995   */
00996 #define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP4)
00997
00998 /**
00999   * @brief  Enable the COMP4 EXTI line falling edge trigger.
01000   * @retval None
01001   */
01002 #define __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP4)
01003
01004 /**
01005   * @brief  Disable the COMP4 EXTI line falling edge trigger.
01006   * @retval None
01007   */
01008 #define __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP4)
01009
01010 /**
01011   * @brief  Enable the COMP4 EXTI line rising & falling edge trigger.
01012   * @retval None
01013   */
01014 #define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
01015                                                                __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE(); \
01016                                                                __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE(); \
01017                                                              } while(0U)
01018
01019 /**
01020   * @brief  Disable the COMP4 EXTI line rising & falling edge trigger.
01021   * @retval None
01022   */
01023 #define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE()   do { \
01024                                                                __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE(); \
01025                                                                __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE(); \
01026                                                              } while(0U)
01027
01028 /**
01029   * @brief  Enable the COMP4 EXTI line in interrupt mode.
01030   * @retval None
01031   */
01032 #define __HAL_COMP_COMP4_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP4)
01033
01034 /**
01035   * @brief  Disable the COMP4 EXTI line in interrupt mode.
01036   * @retval None
01037   */
01038 #define __HAL_COMP_COMP4_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP4)
01039
01040 /**
01041   * @brief  Generate a software interrupt on the COMP4 EXTI line.
01042   * @retval None
01043   */
01044 #define __HAL_COMP_COMP4_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP4)
01045
01046 /**
01047   * @brief  Enable the COMP4 EXTI line in event mode.
01048   * @retval None
01049   */
01050 #define __HAL_COMP_COMP4_EXTI_ENABLE_EVENT()          SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP4)
01051
01052 /**
01053   * @brief  Disable the COMP4 EXTI line in event mode.
01054   * @retval None
01055   */
01056 #define __HAL_COMP_COMP4_EXTI_DISABLE_EVENT()         CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP4)
01057
01058 /**
01059   * @brief  Check whether the COMP4 EXTI line flag is set or not.
01060   * @retval RESET or SET
01061   */
01062 #define __HAL_COMP_COMP4_EXTI_GET_FLAG()              READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP4)
01063
01064 /**
01065   * @brief  Clear the COMP4 EXTI flag.
01066   * @retval None
01067   */
01068 #define __HAL_COMP_COMP4_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP4)
01069
01070 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
01071        /* STM32F302xC || STM32F303xC || STM32F358xx || */
01072        /* STM32F302xE || STM32F303xE || STM32F398xx || */
01073        /* STM32F303x8 || STM32F334x8 || STM32F328xx    */
01074
01075 #if defined(STM32F303xE) || defined(STM32F398xx) || \
01076     defined(STM32F303xC) || defined(STM32F358xx)
01077
01078 /**
01079   * @brief  Enable the COMP5 EXTI line rising edge trigger.
01080   * @retval None
01081   */
01082 #define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP5)
01083
01084 /**
01085   * @brief  Disable the COMP5 EXTI line rising edge trigger.
01086   * @retval None
01087   */
01088 #define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP5)
01089
01090 /**
01091   * @brief  Enable the COMP5 EXTI line falling edge trigger.
01092   * @retval None
01093   */
01094 #define __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP5)
01095
01096 /**
01097   * @brief  Disable the COMP5 EXTI line falling edge trigger.
01098   * @retval None
01099   */
01100 #define __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP5)
01101
01102 /**
01103   * @brief  Enable the COMP5 EXTI line rising & falling edge trigger.
01104   * @retval None
01105   */
01106 #define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
01107                                                                __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE(); \
01108                                                                __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE(); \
01109                                                              } while(0U)
01110
01111 /**
01112   * @brief  Disable the COMP5 EXTI line rising & falling edge trigger.
01113   * @retval None
01114   */
01115 #define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE()   do { \
01116                                                                __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE(); \
01117                                                                __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE(); \
01118                                                              } while(0U)
01119
01120 /**
01121   * @brief  Enable the COMP5 EXTI line in interrupt mode.
01122   * @retval None
01123   */
01124 #define __HAL_COMP_COMP5_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP5)
01125
01126 /**
01127   * @brief  Disable the COMP5 EXTI line in interrupt mode.
01128   * @retval None
01129   */
01130 #define __HAL_COMP_COMP5_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP5)
01131
01132 /**
01133   * @brief  Generate a software interrupt on the COMP5 EXTI line.
01134   * @retval None
01135   */
01136 #define __HAL_COMP_COMP5_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP5)
01137
01138 /**
01139   * @brief  Enable the COMP5 EXTI line in event mode.
01140   * @retval None
01141   */
01142 #define __HAL_COMP_COMP5_EXTI_ENABLE_EVENT()          SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP5)
01143
01144 /**
01145   * @brief  Disable the COMP5 EXTI line in event mode.
01146   * @retval None
01147   */
01148 #define __HAL_COMP_COMP5_EXTI_DISABLE_EVENT()         CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP5)
01149
01150 /**
01151   * @brief  Check whether the COMP5 EXTI line flag is set or not.
01152   * @retval RESET or SET
01153   */
01154 #define __HAL_COMP_COMP5_EXTI_GET_FLAG()              READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP5)
01155
01156 /**
01157   * @brief  Clear the COMP5 EXTI flag.
01158   * @retval None
01159   */
01160 #define __HAL_COMP_COMP5_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP5)
01161
01162 #endif /* STM32F303xE || STM32F398xx || */
01163        /* STM32F303xC || STM32F358xx    */
01164
01165 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) ||  \
01166     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) ||  \
01167     defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) ||  \
01168     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
01169
01170 /**
01171   * @brief  Enable the COMP6 EXTI line rising edge trigger.
01172   * @retval None
01173   */
01174 #define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP6)
01175
01176 /**
01177   * @brief  Disable the COMP6 EXTI line rising edge trigger.
01178   * @retval None
01179   */
01180 #define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP6)
01181
01182 /**
01183   * @brief  Enable the COMP6 EXTI line falling edge trigger.
01184   * @retval None
01185   */
01186 #define __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP6)
01187
01188 /**
01189   * @brief  Disable the COMP6 EXTI line falling edge trigger.
01190   * @retval None
01191   */
01192 #define __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP6)
01193
01194 /**
01195   * @brief  Enable the COMP6 EXTI line rising & falling edge trigger.
01196   * @retval None
01197   */
01198 #define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
01199                                                                __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE(); \
01200                                                                __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE(); \
01201                                                              } while(0U)
01202
01203 /**
01204   * @brief  Disable the COMP6 EXTI line rising & falling edge trigger.
01205   * @retval None
01206   */
01207 #define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE()   do { \
01208                                                                __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE(); \
01209                                                                __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE(); \
01210                                                              } while(0U)
01211
01212 /**
01213   * @brief  Enable the COMP6 EXTI line in interrupt mode.
01214   * @retval None
01215   */
01216 #define __HAL_COMP_COMP6_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP6)
01217
01218 /**
01219   * @brief  Disable the COMP6 EXTI line in interrupt mode.
01220   * @retval None
01221   */
01222 #define __HAL_COMP_COMP6_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP6)
01223
01224 /**
01225   * @brief  Generate a software interrupt on the COMP6 EXTI line.
01226   * @retval None
01227   */
01228 #define __HAL_COMP_COMP6_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER2, COMP_EXTI_LINE_COMP6)
01229
01230 /**
01231   * @brief  Enable the COMP6 EXTI line in event mode.
01232   * @retval None
01233   */
01234 #define __HAL_COMP_COMP6_EXTI_ENABLE_EVENT()          SET_BIT(EXTI->EMR2, COMP_EXTI_LINE_COMP6)
01235
01236 /**
01237   * @brief  Disable the COMP6 EXTI line in event mode.
01238   * @retval None
01239   */
01240 #define __HAL_COMP_COMP6_EXTI_DISABLE_EVENT()         CLEAR_BIT(EXTI->EMR2, COMP_EXTI_LINE_COMP6)
01241
01242 /**
01243   * @brief  Check whether the COMP6 EXTI line flag is set or not.
01244   * @retval RESET or SET
01245   */
01246 #define __HAL_COMP_COMP6_EXTI_GET_FLAG()              READ_BIT(EXTI->PR2, COMP_EXTI_LINE_COMP6)
01247
01248 /**
01249   * @brief  Clear the COMP6 EXTI flag.
01250   * @retval None
01251   */
01252 #define __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR2, COMP_EXTI_LINE_COMP6)
01253
01254 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
01255        /* STM32F302xC || STM32F303xC || STM32F358xx || */
01256        /* STM32F302xE || STM32F303xE || STM32F398xx || */
01257        /* STM32F303x8 || STM32F334x8 || STM32F328xx    */
01258
01259 #if defined(STM32F303xE) || defined(STM32F398xx) || \
01260     defined(STM32F303xC) || defined(STM32F358xx)
01261 /**
01262   * @brief  Enable the COMP7 EXTI line rising edge trigger.
01263   * @retval None
01264   */
01265 #define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP7)
01266
01267 /**
01268   * @brief  Disable the COMP7 EXTI line rising edge trigger.
01269   * @retval None
01270   */
01271 #define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP7)
01272
01273 /**
01274   * @brief  Enable the COMP7 EXTI line falling edge trigger.
01275   * @retval None
01276   */
01277 #define __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP7)
01278
01279 /**
01280   * @brief  Disable the COMP7 EXTI line falling edge trigger.
01281   * @retval None
01282   */
01283 #define __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP7)
01284
01285 /**
01286   * @brief  Enable the COMP7 EXTI line rising & falling edge trigger.
01287   * @retval None
01288   */
01289 #define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
01290                                                                __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE(); \
01291                                                                __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE(); \
01292                                                              } while(0U)
01293
01294 /**
01295   * @brief  Disable the COMP7 EXTI line rising & falling edge trigger.
01296   * @retval None
01297   */
01298 #define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE()   do { \
01299                                                                __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE(); \
01300                                                                __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE(); \
01301                                                              } while(0U)
01302
01303 /**
01304   * @brief  Enable the COMP7 EXTI line in interrupt mode.
01305   * @retval None
01306   */
01307 #define __HAL_COMP_COMP7_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP7)
01308
01309 /**
01310   * @brief  Disable the COMP7 EXTI line in interrupt mode.
01311   * @retval None
01312   */
01313 #define __HAL_COMP_COMP7_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP7)
01314
01315 /**
01316   * @brief  Generate a software interrupt on the COMP7 EXTI line.
01317   * @retval None
01318   */
01319 #define __HAL_COMP_COMP7_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER2, COMP_EXTI_LINE_COMP7)
01320
01321 /**
01322   * @brief  Enable the COMP7 EXTI line in event mode.
01323   * @retval None
01324   */
01325 #define __HAL_COMP_COMP7_EXTI_ENABLE_EVENT()          SET_BIT(EXTI->EMR2, COMP_EXTI_LINE_COMP7)
01326
01327 /**
01328   * @brief  Disable the COMP7 EXTI line in event mode.
01329   * @retval None
01330   */
01331 #define __HAL_COMP_COMP7_EXTI_DISABLE_EVENT()         CLEAR_BIT(EXTI->EMR2, COMP_EXTI_LINE_COMP7)
01332
01333 /**
01334   * @brief  Check whether the COMP7 EXTI line flag is set or not.
01335   * @retval RESET or SET
01336   */
01337 #define __HAL_COMP_COMP7_EXTI_GET_FLAG()              READ_BIT(EXTI->PR2, COMP_EXTI_LINE_COMP7)
01338
01339 /**
01340   * @brief  Clear the COMP7 EXTI flag.
01341   * @retval None
01342   */
01343 #define __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR2, COMP_EXTI_LINE_COMP7)
01344
01345 #endif /* STM32F303xE || STM32F398xx || */
01346        /* STM32F303xC || STM32F358xx    */
01347
01348 /**
01349   * @}
01350   */
01351
01352 /* Private types -------------------------------------------------------------*/
01353 /* Private constants ---------------------------------------------------------*/
01354 /** @defgroup COMPEx_Private_Constants COMP Extended Private Constants
01355   * @{
01356   */
01357 /** @defgroup COMPEx_ExtiLineEvent COMP Extended EXTI lines
01358   * @{
01359   */
01360 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
01361     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
01362
01363 #define COMP_EXTI_LINE_COMP2                   EXTI_IMR_MR22    /*!< External interrupt line 22 connected to COMP2 */
01364 #define COMP_EXTI_LINE_COMP4                   EXTI_IMR_MR30    /*!< External interrupt line 30 connected to COMP4 */
01365 #define COMP_EXTI_LINE_COMP6                   EXTI_IMR2_MR32   /*!< External interrupt line 32 connected to COMP6 */
01366
01367 #define COMP_EXTI_LINE_REG2_MASK               EXTI_IMR2_MR32   /*!< Mask for External interrupt line control in register xxx2 */
01368
01369 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
01370        /* STM32F303x8 || STM32F334x8 || STM32F328xx */
01371
01372 #if defined(STM32F302xE) || \
01373     defined(STM32F302xC)
01374
01375 #define COMP_EXTI_LINE_COMP1                   EXTI_IMR_MR21    /*!< External interrupt line 21 connected to COMP1 */
01376 #define COMP_EXTI_LINE_COMP2                   EXTI_IMR_MR22    /*!< External interrupt line 22 connected to COMP2 */
01377 #define COMP_EXTI_LINE_COMP4                   EXTI_IMR_MR30    /*!< External interrupt line 30 connected to COMP4 */
01378 #define COMP_EXTI_LINE_COMP6                   EXTI_IMR2_MR32   /*!< External interrupt line 32 connected to COMP6 */
01379
01380 #define COMP_EXTI_LINE_REG2_MASK               EXTI_IMR2_MR32   /*!< Mask for External interrupt line control in register xxx2 */
01381
01382 #endif /* STM32F302xE || */
01383        /* STM32F302xC    */
01384
01385 #if defined(STM32F303xE) || defined(STM32F398xx) || \
01386     defined(STM32F303xC) || defined(STM32F358xx)
01387
01388 #define COMP_EXTI_LINE_COMP1                   EXTI_IMR_MR21    /*!< External interrupt line 21 connected to COMP1 */
01389 #define COMP_EXTI_LINE_COMP2                   EXTI_IMR_MR22    /*!< External interrupt line 22 connected to COMP2 */
01390 #define COMP_EXTI_LINE_COMP3                   EXTI_IMR_MR29    /*!< External interrupt line 29 connected to COMP3 */
01391 #define COMP_EXTI_LINE_COMP4                   EXTI_IMR_MR30    /*!< External interrupt line 30 connected to COMP4 */
01392 #define COMP_EXTI_LINE_COMP5                   EXTI_IMR_MR31    /*!< External interrupt line 31 connected to COMP5 */
01393 #define COMP_EXTI_LINE_COMP6                   EXTI_IMR2_MR32   /*!< External interrupt line 32 connected to COMP6 */
01394 #define COMP_EXTI_LINE_COMP7                   EXTI_IMR2_MR33   /*!< External interrupt line 33 connected to COMP7 */
01395
01396 #define COMP_EXTI_LINE_REG2_MASK               (EXTI_IMR2_MR33 | EXTI_IMR2_MR32) /*!< Mask for External interrupt line control in register xxx2 */
01397
01398 #endif /* STM32F303xE || STM32F398xx || */
01399        /* STM32F303xC || STM32F358xx    */
01400
01401 #if defined(STM32F373xC) || defined(STM32F378xx)
01402
01403 #define COMP_EXTI_LINE_COMP1                   EXTI_IMR_MR21    /*!< External interrupt line 21 connected to COMP1 */
01404 #define COMP_EXTI_LINE_COMP2                   EXTI_IMR_MR22    /*!< External interrupt line 22 connected to COMP2 */
01405
01406 #endif /* STM32F373xC || STM32F378xx */
01407
01408 /**
01409   * @}
01410   */
01411
01412 /** @defgroup COMPEx_Misc COMP Extended miscellaneous defines
01413   * @{
01414   */
01415
01416 /* CSR masks redefinition for internal use */
01417 #define COMP_CSR_COMPxINSEL_MASK              COMP_CSR_COMPxINSEL   /*!< COMP_CSR_COMPxINSEL Mask */
01418 #define COMP_CSR_COMPxOUTSEL_MASK             COMP_CSR_COMPxOUTSEL  /*!< COMP_CSR_COMPxOUTSEL Mask */
01419 #define COMP_CSR_COMPxPOL_MASK                COMP_CSR_COMPxPOL     /*!< COMP_CSR_COMPxPOL Mask   */
01420 #if  defined(STM32F373xC) || defined(STM32F378xx)
01421 /* CSR register reset value */
01422 #define COMP_CSR_RESET_VALUE                  (0x00000000U)
01423 #define COMP_CSR_RESET_PARAMETERS_MASK        (0x00003FFFU)
01424 #define COMP_CSR_UPDATE_PARAMETERS_MASK       (0x00003FFEU)
01425 /* CSR COMP1/COMP2 shift */
01426 #define COMP_CSR_COMP1_SHIFT                  0U
01427 #define COMP_CSR_COMP2_SHIFT                  16U
01428 #else
01429 /* CSR register reset value */
01430 #define COMP_CSR_RESET_VALUE                  (0x00000000U)
01431 #endif /* STM32F373xC || STM32F378xx */
01432
01433 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01434 #define COMP_CSR_COMPxNONINSEL_MASK            (COMP2_CSR_COMP2INPDAC) /*!< COMP_CSR_COMPxNONINSEL mask */
01435 #define COMP_CSR_COMPxWNDWEN_MASK              (0x00000000U) /*!< Mask empty: feature not available */
01436 #define COMP_CSR_COMPxMODE_MASK                (0x00000000U) /*!< Mask empty: feature not available */
01437 #define COMP_CSR_COMPxHYST_MASK                (0x00000000U) /*!< Mask empty: feature not available */
01438 #define COMP_CSR_COMPxBLANKING_MASK            COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
01439 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
01440
01441 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
01442 #define COMP_CSR_COMPxNONINSEL_MASK            (0x00000000U) /*!< Mask empty: feature not available */
01443 #define COMP_CSR_COMPxWNDWEN_MASK              (0x00000000U) /*!< Mask empty: feature not available */
01444 #define COMP_CSR_COMPxMODE_MASK                (0x00000000U) /*!< Mask empty: feature not available */
01445 #define COMP_CSR_COMPxHYST_MASK                (0x00000000U) /*!< Mask empty: feature not available */
01446 #define COMP_CSR_COMPxBLANKING_MASK            COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
01447 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
01448
01449 #if  defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
01450 #define COMP_CSR_COMPxNONINSEL_MASK            (COMP_CSR_COMPxNONINSEL | COMP1_CSR_COMP1SW1) /*!< COMP_CSR_COMPxNONINSEL mask */
01451 #define COMP_CSR_COMPxWNDWEN_MASK              COMP_CSR_COMPxWNDWEN   /*!< COMP_CSR_COMPxWNDWEN mask */
01452 #define COMP_CSR_COMPxMODE_MASK                COMP_CSR_COMPxMODE     /*!< COMP_CSR_COMPxMODE Mask */
01453 #define COMP_CSR_COMPxHYST_MASK                COMP_CSR_COMPxHYST     /*!< COMP_CSR_COMPxHYST Mask */
01454 #define COMP_CSR_COMPxBLANKING_MASK            COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
01455 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
01456
01457 #if  defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
01458 #define COMP_CSR_COMPxNONINSEL_MASK            (COMP1_CSR_COMP1SW1) /*!< COMP_CSR_COMPxNONINSEL mask */
01459 #define COMP_CSR_COMPxWNDWEN_MASK              (0x00000000U) /*!< Mask empty: feature not available */
01460 #define COMP_CSR_COMPxMODE_MASK                (0x00000000U) /*!< Mask empty: feature not available */
01461 #define COMP_CSR_COMPxHYST_MASK                (0x00000000U) /*!< Mask empty: feature not available */
01462 #define COMP_CSR_COMPxBLANKING_MASK            COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
01463 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
01464
01465 #if defined(STM32F373xC) || defined(STM32F378xx)
01466 #define COMP_CSR_COMPxNONINSEL_MASK            (COMP_CSR_COMP1SW1)  /*!< COMP_CSR_COMPxNONINSEL mask */
01467 #define COMP_CSR_COMPxWNDWEN_MASK              COMP_CSR_COMPxWNDWEN /*!< COMP_CSR_COMPxWNDWEN mask */
01468 #define COMP_CSR_COMPxMODE_MASK                COMP_CSR_COMPxMODE   /*!< COMP_CSR_COMPxMODE Mask */
01469 #define COMP_CSR_COMPxHYST_MASK                COMP_CSR_COMPxHYST   /*!< COMP_CSR_COMPxHYST Mask */
01470 #define COMP_CSR_COMPxBLANKING_MASK            (0x00000000U) /*!< Mask empty: feature not available */
01471 #endif /* STM32F373xC || STM32F378xx */
01472
01473 /**
01474   * @}
01475   */
01476
01477 /**
01478   * @}
01479   */
01480
01481 /* Private macros ------------------------------------------------------------*/
01482 /** @defgroup COMPEx_Private_Macros COMP Extended Private Macros
01483   * @{
01484   */
01485 /** @defgroup COMP_GET_EXTI_LINE COMP Extended Private macro to get the EXTI line associated with a comparator handle
01486   * @{
01487   */
01488 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
01489     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
01490 /**
01491   * @brief  Get the specified EXTI line for a comparator instance
01492   * @param  __INSTANCE__ specifies the COMP instance.
01493   * @retval value of @ref COMPEx_ExtiLineEvent
01494   */
01495 #define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 : \
01496                                           ((__INSTANCE__) == COMP4) ? COMP_EXTI_LINE_COMP4 : \
01497                                           COMP_EXTI_LINE_COMP6)
01498 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
01499        /* STM32F303x8 || STM32F334x8 || STM32F328xx */
01500
01501 #if defined(STM32F302xE) || \
01502     defined(STM32F302xC)
01503 /**
01504   * @brief  Get the specified EXTI line for a comparator instance
01505   * @param  __INSTANCE__ specifies the COMP instance.
01506   * @retval value of @ref COMPEx_ExtiLineEvent
01507   */
01508 #define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
01509                                           ((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 : \
01510                                           ((__INSTANCE__) == COMP4) ? COMP_EXTI_LINE_COMP4 : \
01511                                           COMP_EXTI_LINE_COMP6)
01512 #endif /* STM32F302xE || */
01513        /* STM32F302xC    */
01514
01515 #if defined(STM32F303xE) || defined(STM32F398xx) || \
01516     defined(STM32F303xC) || defined(STM32F358xx)
01517 /**
01518   * @brief  Get the specified EXTI line for a comparator instance
01519   * @param  __INSTANCE__ specifies the COMP instance.
01520   * @retval value of @ref COMPEx_ExtiLineEvent
01521   */
01522 #define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
01523                                           ((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 : \
01524                                           ((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 : \
01525                                           ((__INSTANCE__) == COMP4) ? COMP_EXTI_LINE_COMP4 : \
01526                                           ((__INSTANCE__) == COMP5) ? COMP_EXTI_LINE_COMP5 : \
01527                                           ((__INSTANCE__) == COMP6) ? COMP_EXTI_LINE_COMP6 : \
01528                                           COMP_EXTI_LINE_COMP7)
01529 #endif /* STM32F303xE || STM32F398xx || */
01530        /* STM32F303xC || STM32F358xx    */
01531
01532 #if defined(STM32F373xC) || defined(STM32F378xx)
01533 /**
01534   * @brief  Get the specified EXTI line for a comparator instance
01535   * @param  __INSTANCE__ specifies the COMP instance.
01536   * @retval value of @ref COMPEx_ExtiLineEvent
01537   */
01538 #define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
01539                                           COMP_EXTI_LINE_COMP2)
01540 #endif /* STM32F373xC || STM32F378xx */
01541
01542 /**
01543   * @}
01544   */
01545
01546 /** @defgroup COMPEx_Private_Macros_Misc COMP Extended miscellaneous private macros
01547   * @{
01548   */
01549
01550 #if defined(STM32F373xC) || defined(STM32F378xx)
01551 /**
01552   * @brief  Init a comparator instance
01553   * @param  __HANDLE__  COMP handle
01554   * @note   The common output selection is checked versus the COMP instance to set the right output configuration
01555   * @retval None.
01556   */
01557
01558 #define COMP_INIT(__HANDLE__)                                                          \
01559         do {                                                                           \
01560           uint32_t regshift = COMP_CSR_COMP1_SHIFT;                                    \
01561           uint32_t compoutput = (__HANDLE__)->Init.Output & COMP_CSR_COMPxOUTSEL_MASK; \
01562                                                                                        \
01563           if((__HANDLE__)->Instance == COMP2)                                          \
01564           {                                                                            \
01565             regshift = COMP_CSR_COMP2_SHIFT;                                           \
01566           }                                                                            \
01567                                                                                        \
01568           MODIFY_REG(COMP->CSR,                                                        \
01569                      (COMP_CSR_COMPxINSEL  | COMP_CSR_COMPxNONINSEL_MASK |             \
01570                      COMP_CSR_COMPxOUTSEL  | COMP_CSR_COMPxPOL           |             \
01571                      COMP_CSR_COMPxHYST    | COMP_CSR_COMPxMODE) << regshift,          \
01572                      ((__HANDLE__)->Init.InvertingInput    |                           \
01573                      (__HANDLE__)->Init.NonInvertingInput  |                           \
01574                      compoutput                            |                           \
01575                      (__HANDLE__)->Init.OutputPol          |                           \
01576                      (__HANDLE__)->Init.Hysteresis         |                           \
01577                      (__HANDLE__)->Init.Mode) << regshift);                            \
01578                                                                                        \
01579           if((__HANDLE__)->Init.WindowMode != COMP_WINDOWMODE_DISABLE)                 \
01580           {                                                                            \
01581             COMP->CSR |= COMP_CSR_WNDWEN;                                              \
01582           }                                                                            \
01583         } while(0U)
01584
01585 /**
01586   * @brief  DeInit a comparator instance
01587   * @param  __HANDLE__  COMP handle
01588   * @retval None.
01589   */
01590 #define COMP_DEINIT(__HANDLE__)                                                \
01591         do {                                                                   \
01592           uint32_t regshift = COMP_CSR_COMP1_SHIFT;                            \
01593                                                                                \
01594           if((__HANDLE__)->Instance == COMP2)                                  \
01595           {                                                                    \
01596             regshift = COMP_CSR_COMP2_SHIFT;                                   \
01597           }                                                                    \
01598           MODIFY_REG(COMP->CSR,                                                \
01599                      COMP_CSR_RESET_PARAMETERS_MASK << regshift,               \
01600                      COMP_CSR_RESET_VALUE << regshift);                        \
01601         } while(0U)
01602
01603
01604 /**
01605   * @brief  Enable the Exti Line rising edge trigger.
01606   * @param  __EXTILINE__ specifies the COMP Exti sources to be enabled.
01607   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent
01608   * @retval None.
01609   */
01610 #define COMP_EXTI_RISING_ENABLE(__EXTILINE__)      SET_BIT(EXTI->RTSR, (__EXTILINE__))
01611
01612 /**
01613   * @brief  Disable the Exti Line rising edge trigger.
01614   * @param  __EXTILINE__ specifies the COMP Exti sources to be disabled.
01615   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent
01616   * @retval None.
01617   */
01618 #define COMP_EXTI_RISING_DISABLE(__EXTILINE__)     CLEAR_BIT(EXTI->RTSR, (__EXTILINE__))
01619
01620 /**
01621   * @brief  Enable the Exti Line falling edge trigger.
01622   * @param  __EXTILINE__ specifies the COMP Exti sources to be enabled.
01623   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent
01624   * @retval None.
01625   */
01626 #define COMP_EXTI_FALLING_ENABLE(__EXTILINE__)     SET_BIT(EXTI->FTSR, (__EXTILINE__))
01627
01628 /**
01629   * @brief  Disable the Exti Line falling edge trigger.
01630   * @param  __EXTILINE__ specifies the COMP Exti sources to be disabled.
01631   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent
01632   * @retval None.
01633   */
01634 #define COMP_EXTI_FALLING_DISABLE(__EXTILINE__)    CLEAR_BIT(EXTI->FTSR, (__EXTILINE__))
01635
01636 /**
01637   * @brief  Enable the COMP Exti Line interrupt generation.
01638   * @param  __EXTILINE__ specifies the COMP Exti sources to be enabled.
01639   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent
01640   * @retval None.
01641   */
01642 #define COMP_EXTI_ENABLE_IT(__EXTILINE__)          SET_BIT(EXTI->IMR, (__EXTILINE__))
01643
01644 /**
01645   * @brief  Disable the COMP Exti Line interrupt generation.
01646   * @param  __EXTILINE__ specifies the COMP Exti sources to be disabled.
01647   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent
01648   * @retval None.
01649   */
01650 #define COMP_EXTI_DISABLE_IT(__EXTILINE__)         CLEAR_BIT(EXTI->IMR, (__EXTILINE__))
01651
01652 /**
01653   * @brief  Enable the COMP Exti Line event generation.
01654   * @param  __EXTILINE__ specifies the COMP Exti sources to be enabled.
01655   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent
01656   * @retval None.
01657   */
01658 #define COMP_EXTI_ENABLE_EVENT(__EXTILINE__)       SET_BIT(EXTI->EMR, (__EXTILINE__))
01659
01660 /**
01661   * @brief  Disable the COMP Exti Line event generation.
01662   * @param  __EXTILINE__ specifies the COMP Exti sources to be disabled.
01663   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent
01664   * @retval None.
01665   */
01666 #define COMP_EXTI_DISABLE_EVENT(__EXTILINE__)      CLEAR_BIT(EXTI->EMR, (__EXTILINE__))
01667
01668 /**
01669   * @brief  Check whether the specified EXTI line flag is set or not.
01670   * @param  __FLAG__ specifies the COMP Exti sources to be checked.
01671   *          This parameter can be a value of @ref COMPEx_ExtiLineEvent
01672   * @retval The state of __FLAG__ (SET or RESET).
01673   */
01674 #define COMP_EXTI_GET_FLAG(__FLAG__)               READ_BIT(EXTI->PR, (__FLAG__))
01675
01676 /**
01677   * @brief Clear the COMP Exti flags.
01678   * @param  __FLAG__ specifies the COMP Exti sources to be cleared.
01679   *          This parameter can be a value of @ref COMPEx_ExtiLineEvent
01680   * @retval None.
01681   */
01682 #define COMP_EXTI_CLEAR_FLAG(__FLAG__)             WRITE_REG(EXTI->PR, (__FLAG__))
01683
01684 #else /* STM32F30x, STM32F32xx, STM32F35x, STM32F39x, STM32F33x */
01685
01686
01687 /**
01688   * @brief  Init a comparator instance
01689   * @param  __HANDLE__  COMP handle
01690   * @retval None.
01691   */
01692 #define COMP_INIT(__HANDLE__)                                                                                   \
01693         do {                                                                                                    \
01694           __IO uint32_t     csrreg = 0U;                                                                         \
01695                                                                                                                 \
01696           csrreg = READ_REG((__HANDLE__)->Instance->CSR);                                                       \
01697           MODIFY_REG(csrreg, COMP_CSR_COMPxINSEL_MASK, (__HANDLE__)->Init.InvertingInput);                      \
01698           MODIFY_REG(csrreg, COMP_CSR_COMPxNONINSEL_MASK, (__HANDLE__)->Init.NonInvertingInput);                \
01699           MODIFY_REG(csrreg, COMP_CSR_COMPxBLANKING_MASK, (__HANDLE__)->Init.BlankingSrce);                     \
01700           MODIFY_REG(csrreg, COMP_CSR_COMPxOUTSEL_MASK, (__HANDLE__)->Init.Output & COMP_CSR_COMPxOUTSEL_MASK); \
01701           MODIFY_REG(csrreg, COMP_CSR_COMPxPOL_MASK, (__HANDLE__)->Init.OutputPol);                             \
01702           MODIFY_REG(csrreg, COMP_CSR_COMPxHYST_MASK, (__HANDLE__)->Init.Hysteresis);                           \
01703           MODIFY_REG(csrreg, COMP_CSR_COMPxMODE_MASK, (__HANDLE__)->Init.Mode);                                 \
01704           MODIFY_REG(csrreg, COMP_CSR_COMPxWNDWEN_MASK, (__HANDLE__)->Init.WindowMode);                         \
01705           WRITE_REG((__HANDLE__)->Instance->CSR, csrreg);                                                       \
01706         } while(0U)
01707
01708 /**
01709   * @brief  DeInit a comparator instance
01710   * @param  __HANDLE__  COMP handle
01711   * @retval None.
01712   */
01713 #define COMP_DEINIT(__HANDLE__)    WRITE_REG((__HANDLE__)->Instance->CSR, COMP_CSR_RESET_VALUE)
01714
01715 /**
01716   * @brief  Enable the Exti Line rising edge trigger.
01717   * @param  __EXTILINE__ specifies the COMP Exti sources to be enabled.
01718   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent
01719   * @retval None.
01720   */
01721 #define COMP_EXTI_RISING_ENABLE(__EXTILINE__)      ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->RTSR2, (__EXTILINE__)) : SET_BIT(EXTI->RTSR, (__EXTILINE__)))
01722
01723 /**
01724   * @brief  Disable the Exti Line rising edge trigger.
01725   * @param  __EXTILINE__ specifies the COMP Exti sources to be disabled.
01726   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent
01727   * @retval None.
01728   */
01729 #define COMP_EXTI_RISING_DISABLE(__EXTILINE__)     ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->RTSR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->RTSR, (__EXTILINE__)))
01730
01731 /**
01732   * @brief  Enable the Exti Line falling edge trigger.
01733   * @param  __EXTILINE__ specifies the COMP Exti sources to be enabled.
01734   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent
01735   * @retval None.
01736   */
01737 #define COMP_EXTI_FALLING_ENABLE(__EXTILINE__)     ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->FTSR2, (__EXTILINE__)) : SET_BIT(EXTI->FTSR, (__EXTILINE__)))
01738
01739 /**
01740   * @brief  Disable the Exti Line falling edge trigger.
01741   * @param  __EXTILINE__ specifies the COMP Exti sources to be disabled.
01742   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent
01743   * @retval None.
01744   */
01745 #define COMP_EXTI_FALLING_DISABLE(__EXTILINE__)    ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->FTSR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->FTSR, (__EXTILINE__)))
01746
01747 /**
01748   * @brief  Enable the COMP Exti Line interrupt generation.
01749   * @param  __EXTILINE__ specifies the COMP Exti sources to be enabled.
01750   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent
01751   * @retval None.
01752   */
01753 #define COMP_EXTI_ENABLE_IT(__EXTILINE__)          ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->IMR2, (__EXTILINE__)) : SET_BIT(EXTI->IMR, (__EXTILINE__)))
01754
01755 /**
01756   * @brief  Disable the COMP Exti Line interrupt generation.
01757   * @param  __EXTILINE__ specifies the COMP Exti sources to be disabled.
01758   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent
01759   * @retval None.
01760   */
01761 #define COMP_EXTI_DISABLE_IT(__EXTILINE__)         ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->IMR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->IMR, (__EXTILINE__)))
01762
01763 /**
01764   * @brief  Enable the COMP Exti Line event generation.
01765   * @param  __EXTILINE__ specifies the COMP Exti sources to be enabled.
01766   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent
01767   * @retval None.
01768   */
01769 #define COMP_EXTI_ENABLE_EVENT(__EXTILINE__)       ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->EMR2, (__EXTILINE__)) : SET_BIT(EXTI->EMR, (__EXTILINE__)))
01770
01771 /**
01772   * @brief  Disable the COMP Exti Line event generation.
01773   * @param  __EXTILINE__ specifies the COMP Exti sources to be disabled.
01774   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent
01775   * @retval None.
01776   */
01777 #define COMP_EXTI_DISABLE_EVENT(__EXTILINE__)      ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->EMR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->EMR, (__EXTILINE__)))
01778
01779 /**
01780   * @brief  Check whether the specified EXTI line flag is set or not.
01781   * @param  __FLAG__ specifies the COMP Exti sources to be checked.
01782   *          This parameter can be a value of @ref COMPEx_ExtiLineEvent
01783   * @retval The state of __FLAG__ (SET or RESET).
01784   */
01785 #define COMP_EXTI_GET_FLAG(__FLAG__)               ((((__FLAG__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? READ_BIT(EXTI->PR2, (__FLAG__)) : READ_BIT(EXTI->PR, (__FLAG__)))
01786
01787 /**
01788   * @brief Clear the COMP Exti flags.
01789   * @param  __FLAG__ specifies the COMP Exti sources to be cleared.
01790   *          This parameter can be a value of @ref COMPEx_ExtiLineEvent
01791   * @retval None.
01792   */
01793 #define COMP_EXTI_CLEAR_FLAG(__FLAG__)             ((((__FLAG__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? WRITE_REG(EXTI->PR2, (__FLAG__)) : WRITE_REG(EXTI->PR, (__FLAG__)))
01794
01795 #endif /* STM32F373xC || STM32F378xx */
01796
01797
01798 /**
01799   * @brief  Manage inverting input comparator inverting input connected to a GPIO
01800   *         for STM32F302x, STM32F32xx, STM32F33x.
01801   *         - On devices STM32F302x, STM32F32xx, STM32F33x, there is
01802   *           only 1 comparator inverting input connected to a GPIO.
01803   *           Legacy definition of literal COMP_INVERTINGINPUT_IO1
01804   *           was initially the only selection, but depending on
01805   *           comparator instance it corresponds to COMP_INVERTINGINPUT_IO2
01806   *           (for instances COMP4, COMP6).
01807   *           Since, COMP_INVERTINGINPUT_IO2 has been created and this macro
01808   *           selects the correct literal COMP_INVERTINGINPUT_IOx in function
01809   *           of comparator instance.
01810   *         - On other STM32F3 devices, this macro performs no action.
01811   * @param  __COMP_INSTANCE__  COMP instance
01812   * @param  __INVERTINGINPUT__  COMP inverting input
01813   * @retval None.
01814   */
01815 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
01816 #define COMP_INVERTINGINPUT_SELECTION(__COMP_INSTANCE__, __INVERTINGINPUT__)   \
01817   (((__INVERTINGINPUT__) != COMP_INVERTINGINPUT_IO1)                           \
01818     ? (                                                                        \
01819        (__INVERTINGINPUT__)                                                    \
01820       )                                                                        \
01821       :                                                                        \
01822       (((__COMP_INSTANCE__) == COMP2)                                          \
01823         ? (                                                                    \
01824            (COMP_INVERTINGINPUT_IO1)                                           \
01825           )                                                                    \
01826           :                                                                    \
01827           (                                                                    \
01828            (COMP_INVERTINGINPUT_IO2)                                           \
01829           )                                                                    \
01830       )                                                                        \
01831   )
01832 #else
01833 #define COMP_INVERTINGINPUT_SELECTION(__COMP_INSTANCE__, __INVERTINGINPUT__)   \
01834   (__INVERTINGINPUT__)
01835 #endif
01836
01837 /**
01838   * @}
01839   */
01840
01841 /** @defgroup COMPEx_IS_COMP_Definitions COMP Extended Private macros to check input parameters
01842   * @{
01843   */
01844
01845 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01846
01847 #define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT)       || \
01848                                        ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT)       || \
01849                                        ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT)       || \
01850                                        ((INPUT) == COMP_INVERTINGINPUT_VREFINT)          || \
01851                                        ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1)         || \
01852                                        ((INPUT) == COMP_INVERTINGINPUT_IO1))
01853
01854 #define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
01855                                           ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
01856
01857 /* STM32F301x6/x8, STM32F302x6/x8, STM32F318xx devices comparator instances non inverting source values */
01858 #define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT)    \
01859    ((((INSTANCE) == COMP2)  &&                                 \
01860     (((INPUT) == COMP_NONINVERTINGINPUT_IO1)                || \
01861      ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED)))    \
01862     ||                                                         \
01863     (((INPUT) == COMP_NONINVERTINGINPUT_IO1)))
01864
01865 #define IS_COMP_WINDOWMODE(WINDOWMODE) ((WINDOWMODE) == (WINDOWMODE)) /*!< Not available: check always true */
01866
01867 #define IS_COMP_MODE(MODE)  ((MODE) == (MODE))  /*!< Not available: check always true */
01868
01869 #define IS_COMP_HYSTERESIS(HYSTERESIS)    ((HYSTERESIS) == (HYSTERESIS)) /*!< Not available: check always true */
01870
01871 #define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE)                || \
01872                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)            || \
01873                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2)      || \
01874                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)           || \
01875                                 ((OUTPUT) == COMP_OUTPUT_TIM1IC1)             || \
01876                                 ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)        || \
01877                                 ((OUTPUT) == COMP_OUTPUT_TIM2IC2)             || \
01878                                 ((OUTPUT) == COMP_OUTPUT_TIM2IC4)             || \
01879                                 ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)        || \
01880                                 ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR)  || \
01881                                 ((OUTPUT) == COMP_OUTPUT_TIM15IC2)            || \
01882                                 ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR)       || \
01883                                 ((OUTPUT) == COMP_OUTPUT_TIM16IC1)            || \
01884                                 ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))
01885
01886 #define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT)      \
01887    ((((INSTANCE) == COMP2)  &&                         \
01888     (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
01889      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)           ||   \
01890      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2)     ||   \
01891      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)          ||   \
01892      ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)       ||   \
01893      ((OUTPUT) == COMP_OUTPUT_TIM1IC1)            ||   \
01894      ((OUTPUT) == COMP_OUTPUT_TIM2IC4)            ||   \
01895      ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)))          \
01896     ||                                                 \
01897     (((INSTANCE) == COMP4)  &&                         \
01898     (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
01899      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)           ||   \
01900      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2)     ||   \
01901      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)          ||   \
01902      ((OUTPUT) == COMP_OUTPUT_TIM15IC2)           ||   \
01903      ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR)))         \
01904     ||                                                 \
01905     (((INSTANCE) == COMP6)  &&                         \
01906     (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
01907      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)           ||   \
01908      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2)     ||   \
01909      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)          ||   \
01910      ((OUTPUT) == COMP_OUTPUT_TIM2IC2)            ||   \
01911      ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) ||   \
01912      ((OUTPUT) == COMP_OUTPUT_TIM16IC1)           ||   \
01913      ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))))
01914
01915 #define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE)     || \
01916                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5)  || \
01917                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3)  || \
01918                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3)  || \
01919                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4)  || \
01920                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4)  || \
01921                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
01922                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
01923
01924 /* STM32F301x6/x8, STM32F302x6/x8, STM32F303x6/x8, STM32F334x4/6U/8U, STM32F318xx/STM32F328xx devices comparator instances blanking source values */
01925 #define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
01926    ((((INSTANCE) == COMP2)  &&                                \
01927     (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)     ||        \
01928      ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5)  ||        \
01929      ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3)  ||        \
01930      ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3)))          \
01931     ||                                                        \
01932     (((INSTANCE) == COMP4) &&                                 \
01933      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
01934       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) ||        \
01935       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1)))        \
01936     ||                                                        \
01937     (((INSTANCE) == COMP6) &&                                 \
01938      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
01939       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) ||        \
01940       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
01941
01942 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
01943
01944 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
01945
01946 #define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT)       || \
01947                                        ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT)       || \
01948                                        ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT)       || \
01949                                        ((INPUT) == COMP_INVERTINGINPUT_VREFINT)          || \
01950                                        ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1)         || \
01951                                        ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH2)         || \
01952                                        ((INPUT) == COMP_INVERTINGINPUT_IO1)              || \
01953                                        ((INPUT) == COMP_INVERTINGINPUT_IO2)              || \
01954                                        ((INPUT) == COMP_INVERTINGINPUT_DAC2_CH1))
01955
01956 /*!< Non inverting input not available */
01957 #define IS_COMP_NONINVERTINGINPUT(INPUT) ((INPUT) == (INPUT))  /*!< Multiple selection not available: check always true */
01958
01959 #define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT) ((INPUT) == (INPUT))   /*!< Multiple selection not available: check always true */
01960
01961 #define IS_COMP_WINDOWMODE(WINDOWMODE) ((WINDOWMODE) == (WINDOWMODE)) /*!< Not available: check always true */
01962
01963 #define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE)                || \
01964                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)            || \
01965                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)           || \
01966                                 ((OUTPUT) == COMP_OUTPUT_TIM1IC1)             || \
01967                                 ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)        || \
01968                                 ((OUTPUT) == COMP_OUTPUT_TIM2IC2)             || \
01969                                 ((OUTPUT) == COMP_OUTPUT_TIM2IC4)             || \
01970                                 ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)        || \
01971                                 ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR)  || \
01972                                 ((OUTPUT) == COMP_OUTPUT_TIM3IC1)             || \
01973                                 ((OUTPUT) == COMP_OUTPUT_TIM3IC3)             || \
01974                                 ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)        || \
01975                                 ((OUTPUT) == COMP_OUTPUT_TIM15IC2)            || \
01976                                 ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR)       || \
01977                                 ((OUTPUT) == COMP_OUTPUT_TIM16IC1)            || \
01978                                 ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))
01979
01980 #define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT)      \
01981    ((((INSTANCE) == COMP2)  &&                         \
01982     (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
01983      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)           ||   \
01984      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)          ||   \
01985      ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)       ||   \
01986      ((OUTPUT) == COMP_OUTPUT_TIM1IC1)            ||   \
01987      ((OUTPUT) == COMP_OUTPUT_TIM2IC4)            ||   \
01988      ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)       ||   \
01989      ((OUTPUT) == COMP_OUTPUT_TIM3IC1)            ||   \
01990      ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)))          \
01991     ||                                                 \
01992     (((INSTANCE) == COMP4)  &&                         \
01993     (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
01994      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)           ||   \
01995      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)          ||   \
01996      ((OUTPUT) == COMP_OUTPUT_TIM3IC3)            ||   \
01997      ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)       ||   \
01998      ((OUTPUT) == COMP_OUTPUT_TIM15IC2)           ||   \
01999      ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR)))         \
02000     ||                                                 \
02001     (((INSTANCE) == COMP6)  &&                         \
02002     (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
02003      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)           ||   \
02004      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)          ||   \
02005      ((OUTPUT) == COMP_OUTPUT_TIM2IC2)            ||   \
02006      ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) ||   \
02007      ((OUTPUT) == COMP_OUTPUT_TIM16IC1)           ||   \
02008      ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))))
02009
02010 #define IS_COMP_MODE(MODE)  ((MODE) == (MODE))  /*!< Not available: check always true */
02011
02012 #define IS_COMP_HYSTERESIS(HYSTERESIS)    ((HYSTERESIS) == (HYSTERESIS)) /*!< Not available: check always true */
02013
02014 #define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE)     || \
02015                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5)  || \
02016                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3)  || \
02017                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3)  || \
02018                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4)  || \
02019                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4)  || \
02020                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
02021                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
02022
02023 /* STM32F301x6/x8, STM32F302x6/x8, STM32F303x6/x8, STM32F334x4/6U/8U, STM32F318xx/STM32F328xx devices comparator instances blanking source values */
02024 #define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
02025    ((((INSTANCE) == COMP2)  &&                                \
02026     (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)     ||        \
02027      ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5)  ||        \
02028      ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3)  ||        \
02029      ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3)))          \
02030     ||                                                        \
02031     (((INSTANCE) == COMP4) &&                                 \
02032      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02033       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) ||        \
02034       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1)))        \
02035     ||                                                        \
02036     (((INSTANCE) == COMP6) &&                                 \
02037      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02038       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) ||        \
02039       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
02040
02041 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
02042
02043 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
02044
02045 #define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT)       || \
02046                                        ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT)       || \
02047                                        ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT)       || \
02048                                        ((INPUT) == COMP_INVERTINGINPUT_VREFINT)          || \
02049                                        ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1)         || \
02050                                        ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH2)         || \
02051                                        ((INPUT) == COMP_INVERTINGINPUT_IO1)              || \
02052                                        ((INPUT) == COMP_INVERTINGINPUT_IO2))
02053
02054 #define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
02055                                           ((INPUT) == COMP_NONINVERTINGINPUT_IO2) || \
02056                                           ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
02057
02058 /* STM32F302xB/xC, STM32F303xB/xC, STM32F358xx devices comparator instances non inverting source values */
02059 #define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT)    \
02060    ((((INSTANCE) == COMP1)  &&                                 \
02061     (((INPUT) == COMP_NONINVERTINGINPUT_IO1)                || \
02062      ((INPUT) == COMP_NONINVERTINGINPUT_IO2)                || \
02063      ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED)))    \
02064     ||                                                         \
02065     ((((INPUT) == COMP_NONINVERTINGINPUT_IO1)               || \
02066       ((INPUT) == COMP_NONINVERTINGINPUT_IO2))))
02067
02068 #define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \
02069                                         ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE))
02070
02071 #define IS_COMP_MODE(MODE)  (((MODE) == COMP_MODE_HIGHSPEED)     || \
02072                              ((MODE) == COMP_MODE_MEDIUMSPEED)   || \
02073                              ((MODE) == COMP_MODE_LOWPOWER)      || \
02074                              ((MODE) == COMP_MODE_ULTRALOWPOWER))
02075
02076 #define IS_COMP_HYSTERESIS(HYSTERESIS)    (((HYSTERESIS) == COMP_HYSTERESIS_NONE)   || \
02077                                            ((HYSTERESIS) == COMP_HYSTERESIS_LOW)    || \
02078                                            ((HYSTERESIS) == COMP_HYSTERESIS_MEDIUM) || \
02079                                            ((HYSTERESIS) == COMP_HYSTERESIS_HIGH))
02080
02081 #if  defined(STM32F302xC)
02082
02083 #define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE)                || \
02084                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)            || \
02085                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2)      || \
02086                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)           || \
02087                                 ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)        || \
02088                                 ((OUTPUT) == COMP_OUTPUT_TIM1IC1)             || \
02089                                 ((OUTPUT) == COMP_OUTPUT_TIM2IC4)             || \
02090                                 ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)        || \
02091                                 ((OUTPUT) == COMP_OUTPUT_TIM3IC1)             || \
02092                                 ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)        || \
02093                                 ((OUTPUT) == COMP_OUTPUT_TIM3IC3)             || \
02094                                 ((OUTPUT) == COMP_OUTPUT_TIM15IC2)            || \
02095                                 ((OUTPUT) == COMP_OUTPUT_TIM4IC2)             || \
02096                                 ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR)       || \
02097                                 ((OUTPUT) == COMP_OUTPUT_TIM2IC2)             || \
02098                                 ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR)  || \
02099                                 ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR)       || \
02100                                 ((OUTPUT) == COMP_OUTPUT_TIM16IC1)            || \
02101                                 ((OUTPUT) == COMP_OUTPUT_TIM4IC4))
02102
02103 #define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT)      \
02104    ((((INSTANCE) == COMP1)  &&                         \
02105     (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
02106      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)           ||   \
02107      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2)     ||   \
02108      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)          ||   \
02109      ((OUTPUT) == COMP_OUTPUT_TIM1IC1)            ||   \
02110      ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)       ||   \
02111      ((OUTPUT) == COMP_OUTPUT_TIM2IC4)            ||   \
02112      ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)       ||   \
02113      ((OUTPUT) == COMP_OUTPUT_TIM3IC1)            ||   \
02114      ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)))          \
02115     ||                                                 \
02116     (((INSTANCE) == COMP2)  &&                         \
02117     (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
02118      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)           ||   \
02119      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2)     ||   \
02120      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)          ||   \
02121      ((OUTPUT) == COMP_OUTPUT_TIM1IC1)            ||   \
02122      ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)       ||   \
02123      ((OUTPUT) == COMP_OUTPUT_TIM2IC4)            ||   \
02124      ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)       ||   \
02125      ((OUTPUT) == COMP_OUTPUT_TIM3IC1)            ||   \
02126      ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)))          \
02127     ||                                                 \
02128     (((INSTANCE) == COMP4)  &&                         \
02129     (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
02130      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)           ||   \
02131      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2)     ||   \
02132      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)          ||   \
02133      ((OUTPUT) == COMP_OUTPUT_TIM3IC3)            ||   \
02134      ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)       ||   \
02135      ((OUTPUT) == COMP_OUTPUT_TIM4IC2)            ||   \
02136      ((OUTPUT) == COMP_OUTPUT_TIM15IC2)           ||   \
02137      ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR)))         \
02138     ||                                                 \
02139     (((INSTANCE) == COMP6)  &&                         \
02140     (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
02141      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)           ||   \
02142      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2)     ||   \
02143      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)          ||   \
02144      ((OUTPUT) == COMP_OUTPUT_TIM2IC2)            ||   \
02145      ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) ||   \
02146      ((OUTPUT) == COMP_OUTPUT_TIM4IC4)            ||   \
02147      ((OUTPUT) == COMP_OUTPUT_TIM16IC1)           ||   \
02148      ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))))
02149
02150 #define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE)     || \
02151                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5)  || \
02152                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3)  || \
02153                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3)  || \
02154                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4)  || \
02155                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4)  || \
02156                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
02157                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
02158
02159 /* STM32F302xB/STM32F302xC/STM32F302xE devices comparator instances blanking source values */
02160 #define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
02161    (((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2))  &&     \
02162      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02163       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) ||        \
02164       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) ||        \
02165       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3)))         \
02166     ||                                                        \
02167     (((INSTANCE) == COMP4) &&                                 \
02168      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02169       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) ||        \
02170       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1)))        \
02171     ||                                                        \
02172     (((INSTANCE) == COMP6) &&                                 \
02173      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02174       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) ||        \
02175       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
02176
02177 #endif /* STM32F302xC */
02178
02179 #if  defined(STM32F303xC) || defined(STM32F358xx)
02180
02181 #define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE)                || \
02182                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)            || \
02183                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)           || \
02184                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
02185                                 ((OUTPUT) == COMP_OUTPUT_TIM1IC1)             || \
02186                                 ((OUTPUT) == COMP_OUTPUT_TIM1IC2)             || \
02187                                 ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)        || \
02188                                 ((OUTPUT) == COMP_OUTPUT_TIM2IC1)             || \
02189                                 ((OUTPUT) == COMP_OUTPUT_TIM2IC2)             || \
02190                                 ((OUTPUT) == COMP_OUTPUT_TIM2IC3)             || \
02191                                 ((OUTPUT) == COMP_OUTPUT_TIM2IC4)             || \
02192                                 ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)        || \
02193                                 ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR)  || \
02194                                 ((OUTPUT) == COMP_OUTPUT_TIM3IC1)             || \
02195                                 ((OUTPUT) == COMP_OUTPUT_TIM3IC2)             || \
02196                                 ((OUTPUT) == COMP_OUTPUT_TIM3IC3)             || \
02197                                 ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)        || \
02198                                 ((OUTPUT) == COMP_OUTPUT_TIM4IC1)             || \
02199                                 ((OUTPUT) == COMP_OUTPUT_TIM4IC2)             || \
02200                                 ((OUTPUT) == COMP_OUTPUT_TIM4IC3)             || \
02201                                 ((OUTPUT) == COMP_OUTPUT_TIM4IC4)             || \
02202                                 ((OUTPUT) == COMP_OUTPUT_TIM8BKIN)            || \
02203                                 ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2)           || \
02204                                 ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR)        || \
02205                                 ((OUTPUT) == COMP_OUTPUT_TIM15IC1)            || \
02206                                 ((OUTPUT) == COMP_OUTPUT_TIM15IC2)            || \
02207                                 ((OUTPUT) == COMP_OUTPUT_TIM15BKIN)           || \
02208                                 ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR)       || \
02209                                 ((OUTPUT) == COMP_OUTPUT_TIM16BKIN)           || \
02210                                 ((OUTPUT) == COMP_OUTPUT_TIM16IC1)            || \
02211                                 ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR)       || \
02212                                 ((OUTPUT) == COMP_OUTPUT_TIM17BKIN)           || \
02213                                 ((OUTPUT) == COMP_OUTPUT_TIM17IC1)            || \
02214                                 ((OUTPUT) == COMP_OUTPUT_TIM17OCREFCLR))
02215
02216 #define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT)       \
02217    ((((INSTANCE) == COMP1)  &&                          \
02218     (((OUTPUT) == COMP_OUTPUT_NONE)                ||   \
02219      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)            ||   \
02220      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)           ||   \
02221      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN)            ||   \
02222      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2)           ||   \
02223      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) ||   \
02224      ((OUTPUT) == COMP_OUTPUT_TIM1IC1)             ||   \
02225      ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)        ||   \
02226      ((OUTPUT) == COMP_OUTPUT_TIM2IC4)             ||   \
02227      ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)        ||   \
02228      ((OUTPUT) == COMP_OUTPUT_TIM3IC1)             ||   \
02229      ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)))           \
02230     ||                                                  \
02231     (((INSTANCE) == COMP2)  &&                          \
02232     (((OUTPUT) == COMP_OUTPUT_NONE)                ||   \
02233      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)            ||   \
02234      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)           ||   \
02235      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN)            ||   \
02236      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2)           ||   \
02237      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) ||   \
02238      ((OUTPUT) == COMP_OUTPUT_TIM1IC1)             ||   \
02239      ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)        ||   \
02240      ((OUTPUT) == COMP_OUTPUT_TIM2IC4)             ||   \
02241      ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)        ||   \
02242      ((OUTPUT) == COMP_OUTPUT_TIM3IC1)             ||   \
02243      ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)))           \
02244     ||                                                  \
02245     (((INSTANCE) == COMP3)  &&                          \
02246     (((OUTPUT) == COMP_OUTPUT_NONE)                ||   \
02247      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)            ||   \
02248      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)           ||   \
02249      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN)            ||   \
02250      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2)           ||   \
02251      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) ||   \
02252      ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)        ||   \
02253      ((OUTPUT) == COMP_OUTPUT_TIM3IC2)             ||   \
02254      ((OUTPUT) == COMP_OUTPUT_TIM4IC1)             ||   \
02255      ((OUTPUT) == COMP_OUTPUT_TIM15IC1)            ||   \
02256      ((OUTPUT) == COMP_OUTPUT_TIM15BKIN)))              \
02257     ||                                                  \
02258     (((INSTANCE) == COMP4)  &&                          \
02259     (((OUTPUT) == COMP_OUTPUT_NONE)                ||   \
02260      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)            ||   \
02261      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)           ||   \
02262      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN)            ||   \
02263      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2)           ||   \
02264      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) ||   \
02265      ((OUTPUT) == COMP_OUTPUT_TIM3IC3)             ||   \
02266      ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)        ||   \
02267      ((OUTPUT) == COMP_OUTPUT_TIM4IC2)             ||   \
02268      ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR)        ||   \
02269      ((OUTPUT) == COMP_OUTPUT_TIM15IC2)            ||   \
02270      ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR)))          \
02271     ||                                                  \
02272     (((INSTANCE) == COMP5)  &&                          \
02273     (((OUTPUT) == COMP_OUTPUT_NONE)                ||   \
02274      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)            ||   \
02275      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)           ||   \
02276      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN)            ||   \
02277      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2)           ||   \
02278      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) ||   \
02279      ((OUTPUT) == COMP_OUTPUT_TIM2IC1)             ||   \
02280      ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)        ||   \
02281      ((OUTPUT) == COMP_OUTPUT_TIM4IC3)             ||   \
02282      ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR)        ||   \
02283      ((OUTPUT) == COMP_OUTPUT_TIM16BKIN)           ||   \
02284      ((OUTPUT) == COMP_OUTPUT_TIM17IC1)))               \
02285     ||                                                  \
02286     (((INSTANCE) == COMP6)  &&                          \
02287     (((OUTPUT) == COMP_OUTPUT_NONE)                ||   \
02288      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)            ||   \
02289      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)           ||   \
02290      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN)            ||   \
02291      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2)           ||   \
02292      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) ||   \
02293      ((OUTPUT) == COMP_OUTPUT_TIM2IC2)             ||   \
02294      ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR)  ||   \
02295      ((OUTPUT) == COMP_OUTPUT_TIM4IC4)             ||   \
02296      ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR)        ||   \
02297      ((OUTPUT) == COMP_OUTPUT_TIM16IC1)            ||   \
02298      ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR)))          \
02299     ||                                                  \
02300     (((INSTANCE) == COMP7)  &&                          \
02301     (((OUTPUT) == COMP_OUTPUT_NONE)                ||   \
02302      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)            ||   \
02303      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)           ||   \
02304      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN)            ||   \
02305      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2)           ||   \
02306      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) ||   \
02307      ((OUTPUT) == COMP_OUTPUT_TIM1IC2)             ||   \
02308      ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)        ||   \
02309      ((OUTPUT) == COMP_OUTPUT_TIM2IC3)             ||   \
02310      ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR)        ||   \
02311      ((OUTPUT) == COMP_OUTPUT_TIM17BKIN)           ||   \
02312      ((OUTPUT) == COMP_OUTPUT_TIM17OCREFCLR))))
02313
02314 #define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE)     || \
02315                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5)  || \
02316                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3)  || \
02317                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3)  || \
02318                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4)  || \
02319                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM8OC5)  || \
02320                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4)  || \
02321                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
02322                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
02323
02324 /* STM32F303xE/STM32F398xx/STM32F303xB/STM32F303xC/STM32F358xx devices comparator instances blanking source values */
02325 #define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
02326    (((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2))  &&     \
02327      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02328       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) ||        \
02329       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) ||        \
02330       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3)))         \
02331     ||                                                        \
02332     (((INSTANCE) == COMP3) &&                                 \
02333      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02334       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) ||        \
02335       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4)))         \
02336     ||                                                        \
02337     (((INSTANCE) == COMP4) &&                                 \
02338      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02339       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) ||        \
02340       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) ||        \
02341       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1)))        \
02342     ||                                                        \
02343     (((INSTANCE) == COMP5) &&                                 \
02344      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02345       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) ||        \
02346       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3)))         \
02347     ||                                                        \
02348     (((INSTANCE) == COMP6) &&                                 \
02349      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02350       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) ||        \
02351       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) ||        \
02352       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2)))        \
02353     ||                                                        \
02354     (((INSTANCE) == COMP7) &&                                 \
02355      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02356       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) ||        \
02357       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) ||        \
02358       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
02359
02360 #endif /* STM32F303xC || STM32F358xx */
02361
02362 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
02363
02364 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
02365
02366 #define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT)       || \
02367                                        ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT)       || \
02368                                        ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT)       || \
02369                                        ((INPUT) == COMP_INVERTINGINPUT_VREFINT)          || \
02370                                        ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1)         || \
02371                                        ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH2)         || \
02372                                        ((INPUT) == COMP_INVERTINGINPUT_IO1)              || \
02373                                        ((INPUT) == COMP_INVERTINGINPUT_IO2))
02374
02375 #define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
02376                                           ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
02377
02378 /* STM32F302xE/STM32F303xE/STM32F398xx devices comparator instances non inverting source values */
02379 #define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT)    \
02380    ((((INSTANCE) == COMP1)  &&                                 \
02381     (((INPUT) == COMP_NONINVERTINGINPUT_IO1)                || \
02382      ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED)))    \
02383     ||                                                         \
02384     (((INPUT) == COMP_NONINVERTINGINPUT_IO1)))
02385
02386 #define IS_COMP_WINDOWMODE(WINDOWMODE) ((WINDOWMODE) == (WINDOWMODE))    /*!< Not available: check always true */
02387
02388 #define IS_COMP_MODE(MODE)  ((MODE) == (MODE))  /*!< Not available: check always true */
02389
02390 #define IS_COMP_HYSTERESIS(HYSTERESIS)    ((HYSTERESIS) == (HYSTERESIS)) /*!< Not available: check always true */
02391
02392 #if defined(STM32F302xE)
02393
02394 #define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE)                || \
02395                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)            || \
02396                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2)      || \
02397                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)           || \
02398                                 ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)        || \
02399                                 ((OUTPUT) == COMP_OUTPUT_TIM1IC1)             || \
02400                                 ((OUTPUT) == COMP_OUTPUT_TIM2IC4)             || \
02401                                 ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)        || \
02402                                 ((OUTPUT) == COMP_OUTPUT_TIM3IC1)             || \
02403                                 ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)        || \
02404                                 ((OUTPUT) == COMP_OUTPUT_TIM3IC3)             || \
02405                                 ((OUTPUT) == COMP_OUTPUT_TIM15IC2)            || \
02406                                 ((OUTPUT) == COMP_OUTPUT_TIM4IC2)             || \
02407                                 ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR)       || \
02408                                 ((OUTPUT) == COMP_OUTPUT_TIM2IC2)             || \
02409                                 ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR)  || \
02410                                 ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR)       || \
02411                                 ((OUTPUT) == COMP_OUTPUT_TIM16IC1)            || \
02412                                 ((OUTPUT) == COMP_OUTPUT_TIM4IC4))
02413
02414 #define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT)      \
02415    ((((INSTANCE) == COMP1)  &&                         \
02416     (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
02417      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)           ||   \
02418      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2)     ||   \
02419      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)          ||   \
02420      ((OUTPUT) == COMP_OUTPUT_TIM1IC1)            ||   \
02421      ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)       ||   \
02422      ((OUTPUT) == COMP_OUTPUT_TIM2IC4)            ||   \
02423      ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)       ||   \
02424      ((OUTPUT) == COMP_OUTPUT_TIM3IC1)            ||   \
02425      ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)))          \
02426     ||                                                 \
02427     (((INSTANCE) == COMP2)  &&                         \
02428     (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
02429      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)           ||   \
02430      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2)     ||   \
02431      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)          ||   \
02432      ((OUTPUT) == COMP_OUTPUT_TIM1IC1)            ||   \
02433      ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)       ||   \
02434      ((OUTPUT) == COMP_OUTPUT_TIM2IC4)            ||   \
02435      ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)       ||   \
02436      ((OUTPUT) == COMP_OUTPUT_TIM3IC1)            ||   \
02437      ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)))          \
02438     ||                                                 \
02439     (((INSTANCE) == COMP4)  &&                         \
02440     (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
02441      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)           ||   \
02442      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2)     ||   \
02443      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)          ||   \
02444      ((OUTPUT) == COMP_OUTPUT_TIM3IC3)            ||   \
02445      ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)       ||   \
02446      ((OUTPUT) == COMP_OUTPUT_TIM4IC2)            ||   \
02447      ((OUTPUT) == COMP_OUTPUT_TIM15IC2)           ||   \
02448      ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR)))         \
02449     ||                                                 \
02450     (((INSTANCE) == COMP6)  &&                         \
02451     (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
02452      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)           ||   \
02453      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2)     ||   \
02454      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)          ||   \
02455      ((OUTPUT) == COMP_OUTPUT_TIM2IC2)            ||   \
02456      ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) ||   \
02457      ((OUTPUT) == COMP_OUTPUT_TIM4IC4)            ||   \
02458      ((OUTPUT) == COMP_OUTPUT_TIM16IC1)           ||   \
02459      ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))))
02460
02461 #define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE)     || \
02462                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5)  || \
02463                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3)  || \
02464                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3)  || \
02465                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4)  || \
02466                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4)  || \
02467                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
02468                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
02469
02470 /* STM32F302xB/STM32F302xC/STM32F302xE devices comparator instances blanking source values */
02471 #define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
02472    (((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2))  &&     \
02473      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02474       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) ||        \
02475       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) ||        \
02476       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3)))         \
02477     ||                                                        \
02478     (((INSTANCE) == COMP4) &&                                 \
02479      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02480       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) ||        \
02481       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1)))        \
02482     ||                                                        \
02483     (((INSTANCE) == COMP6) &&                                 \
02484      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02485       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) ||        \
02486       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
02487
02488 #endif /* STM32F302xE */
02489
02490 #if defined(STM32F303xE) || defined(STM32F398xx)
02491
02492 #define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE)                || \
02493                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)            || \
02494                                 ((OUTPUT) == COMP_OUTPUT_TIM1IC1)             || \
02495                                 ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)        || \
02496                                 ((OUTPUT) == COMP_OUTPUT_TIM2IC4)             || \
02497                                 ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)        || \
02498                                 ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR)  || \
02499                                 ((OUTPUT) == COMP_OUTPUT_TIM3IC1)             || \
02500                                 ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)        || \
02501                                 ((OUTPUT) == COMP_OUTPUT_TIM20OCREFCLR)       || \
02502                                 ((OUTPUT) == COMP_OUTPUT_TIM8BKIN)            || \
02503                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)           || \
02504                                 ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2)           || \
02505                                 ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)        || \
02506                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
02507                                 ((OUTPUT) == COMP_OUTPUT_TIM20BKIN)           || \
02508                                 ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2)          || \
02509                                 ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
02510                                 ((OUTPUT) == COMP_OUTPUT_TIM3IC2)             || \
02511                                 ((OUTPUT) == COMP_OUTPUT_TIM4IC1)             || \
02512                                 ((OUTPUT) == COMP_OUTPUT_TIM15IC1)            || \
02513                                 ((OUTPUT) == COMP_OUTPUT_TIM15BKIN)           || \
02514                                 ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR)        || \
02515                                 ((OUTPUT) == COMP_OUTPUT_TIM3IC3)             || \
02516                                 ((OUTPUT) == COMP_OUTPUT_TIM4IC1)             || \
02517                                 ((OUTPUT) == COMP_OUTPUT_TIM15IC1)            || \
02518                                 ((OUTPUT) == COMP_OUTPUT_TIM2IC1)             || \
02519                                 ((OUTPUT) == COMP_OUTPUT_TIM4IC3)             || \
02520                                 ((OUTPUT) == COMP_OUTPUT_TIM16BKIN)           || \
02521                                 ((OUTPUT) == COMP_OUTPUT_TIM17IC1)            || \
02522                                 ((OUTPUT) == COMP_OUTPUT_TIM2IC2)             || \
02523                                 ((OUTPUT) == COMP_OUTPUT_TIM16IC1)            || \
02524                                 ((OUTPUT) == COMP_OUTPUT_TIM4IC4)             || \
02525                                 ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR)       || \
02526                                 ((OUTPUT) == COMP_OUTPUT_TIM2IC3)             || \
02527                                 ((OUTPUT) == COMP_OUTPUT_TIM1IC2)             || \
02528                                 ((OUTPUT) == COMP_OUTPUT_TIM17BKIN)           || \
02529                                 ((OUTPUT) == COMP_OUTPUT_TIM17OCREFCLR))
02530
02531 #define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT)                  \
02532    ((((INSTANCE) == COMP1)  &&                                     \
02533     (((OUTPUT) == COMP_OUTPUT_NONE)                           ||   \
02534      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)                       ||   \
02535      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)                      ||   \
02536      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN)                       ||   \
02537      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2)                      ||   \
02538      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2)            ||   \
02539      ((OUTPUT) == COMP_OUTPUT_TIM20BKIN)                      ||   \
02540      ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2)                     ||   \
02541      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) ||   \
02542      ((OUTPUT) == COMP_OUTPUT_TIM1IC1)                        ||   \
02543      ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)                   ||   \
02544      ((OUTPUT) == COMP_OUTPUT_TIM2IC4)                        ||   \
02545      ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)                   ||   \
02546      ((OUTPUT) == COMP_OUTPUT_TIM3IC1)                        ||   \
02547      ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)))                      \
02548     ||                                                             \
02549     (((INSTANCE) == COMP2)  &&                                     \
02550     (((OUTPUT) == COMP_OUTPUT_NONE)                           ||   \
02551      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)                       ||   \
02552      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)                      ||   \
02553      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN)                       ||   \
02554      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2)                      ||   \
02555      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2)            ||   \
02556      ((OUTPUT) == COMP_OUTPUT_TIM20BKIN)                      ||   \
02557      ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2)                     ||   \
02558      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) ||   \
02559      ((OUTPUT) == COMP_OUTPUT_TIM1IC1)                        ||   \
02560      ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR)                   ||   \
02561      ((OUTPUT) == COMP_OUTPUT_TIM2IC4)                        ||   \
02562      ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)                   ||   \
02563      ((OUTPUT) == COMP_OUTPUT_TIM3IC1)                        ||   \
02564      ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)                   ||   \
02565      ((OUTPUT) == COMP_OUTPUT_TIM20OCREFCLR)))                     \
02566     ||                                                             \
02567     (((INSTANCE) == COMP3)  &&                                     \
02568     (((OUTPUT) == COMP_OUTPUT_NONE)                           ||   \
02569      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)                       ||   \
02570      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)                      ||   \
02571      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN)                       ||   \
02572      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2)                      ||   \
02573      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2)            ||   \
02574      ((OUTPUT) == COMP_OUTPUT_TIM20BKIN)                      ||   \
02575      ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2)                     ||   \
02576      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) ||   \
02577      ((OUTPUT) == COMP_OUTPUT_TIM3IC2)                        ||   \
02578      ((OUTPUT) == COMP_OUTPUT_TIM4IC1)                        ||   \
02579      ((OUTPUT) == COMP_OUTPUT_TIM15IC1)                       ||   \
02580      ((OUTPUT) == COMP_OUTPUT_TIM15BKIN)))                         \
02581     ||                                                             \
02582     (((INSTANCE) == COMP4)  &&                                     \
02583     (((OUTPUT) == COMP_OUTPUT_NONE)                           ||   \
02584      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)                       ||   \
02585      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)                      ||   \
02586      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN)                       ||   \
02587      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2)                      ||   \
02588      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2)            ||   \
02589      ((OUTPUT) == COMP_OUTPUT_TIM20BKIN)                      ||   \
02590      ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2)                     ||   \
02591      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) ||   \
02592      ((OUTPUT) == COMP_OUTPUT_TIM3IC3)                        ||   \
02593      ((OUTPUT) == COMP_OUTPUT_TIM4IC2)                        ||   \
02594      ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR)                   ||   \
02595      ((OUTPUT) == COMP_OUTPUT_TIM15IC2)                       ||   \
02596      ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR)))                     \
02597     ||                                                             \
02598     (((INSTANCE) == COMP5)  &&                                     \
02599     (((OUTPUT) == COMP_OUTPUT_NONE)                           ||   \
02600      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)                       ||   \
02601      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)                      ||   \
02602      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN)                       ||   \
02603      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2)                      ||   \
02604      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2)            ||   \
02605      ((OUTPUT) == COMP_OUTPUT_TIM20BKIN)                      ||   \
02606      ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2)                     ||   \
02607      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) ||   \
02608      ((OUTPUT) == COMP_OUTPUT_TIM2IC1)                        ||   \
02609      ((OUTPUT) == COMP_OUTPUT_TIM4IC3)                        ||   \
02610      ((OUTPUT) == COMP_OUTPUT_TIM16BKIN)                      ||   \
02611      ((OUTPUT) == COMP_OUTPUT_TIM17IC1)))                          \
02612     ||                                                             \
02613     (((INSTANCE) == COMP6)  &&                                     \
02614     (((OUTPUT) == COMP_OUTPUT_NONE)                           ||   \
02615      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)                       ||   \
02616      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)                      ||   \
02617      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN)                       ||   \
02618      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2)                      ||   \
02619      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2)            ||   \
02620      ((OUTPUT) == COMP_OUTPUT_TIM20BKIN)                      ||   \
02621      ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2)                     ||   \
02622      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) ||   \
02623      ((OUTPUT) == COMP_OUTPUT_TIM2IC2)                        ||   \
02624      ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR)             ||   \
02625      ((OUTPUT) == COMP_OUTPUT_TIM4IC4)                        ||   \
02626      ((OUTPUT) == COMP_OUTPUT_TIM16IC1)                       ||   \
02627      ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR)))                     \
02628     ||                                                             \
02629     (((INSTANCE) == COMP7)  &&                                     \
02630     (((OUTPUT) == COMP_OUTPUT_NONE)                           ||   \
02631      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN)                       ||   \
02632      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2)                      ||   \
02633      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN)                       ||   \
02634      ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2)                      ||   \
02635      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2)            ||   \
02636      ((OUTPUT) == COMP_OUTPUT_TIM20BKIN)                      ||   \
02637      ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2)                     ||   \
02638      ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) ||   \
02639      ((OUTPUT) == COMP_OUTPUT_TIM1IC2)                        ||   \
02640      ((OUTPUT) == COMP_OUTPUT_TIM2IC3)                        ||   \
02641      ((OUTPUT) == COMP_OUTPUT_TIM17BKIN)                      ||   \
02642      ((OUTPUT) == COMP_OUTPUT_TIM17OCREFCLR))))
02643
02644 #define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE)     || \
02645                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5)  || \
02646                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3)  || \
02647                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3)  || \
02648                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4)  || \
02649                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM8OC5)  || \
02650                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4)  || \
02651                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
02652                                       ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
02653
02654 /* STM32F303xE/STM32F398xx/STM32F303xB/STM32F303xC/STM32F358xx devices comparator instances blanking source values */
02655 #define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
02656    (((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2))  &&     \
02657      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02658       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) ||        \
02659       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) ||        \
02660       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3)))         \
02661     ||                                                        \
02662     (((INSTANCE) == COMP3) &&                                 \
02663      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02664       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) ||        \
02665       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4)))         \
02666     ||                                                        \
02667     (((INSTANCE) == COMP4) &&                                 \
02668      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02669       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) ||        \
02670       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) ||        \
02671       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1)))        \
02672     ||                                                        \
02673     (((INSTANCE) == COMP5) &&                                 \
02674      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02675       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) ||        \
02676       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3)))         \
02677     ||                                                        \
02678     (((INSTANCE) == COMP6) &&                                 \
02679      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02680       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) ||        \
02681       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) ||        \
02682       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2)))        \
02683     ||                                                        \
02684     (((INSTANCE) == COMP7) &&                                 \
02685      (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE)    ||        \
02686       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) ||        \
02687       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) ||        \
02688       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
02689
02690 #endif /* STM32F303xE || STM32F398xx */
02691
02692 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
02693
02694 #if defined(STM32F373xC) || defined(STM32F378xx)
02695
02696 #define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT)       || \
02697                                        ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT)       || \
02698                                        ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT)       || \
02699                                        ((INPUT) == COMP_INVERTINGINPUT_VREFINT)          || \
02700                                        ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1)         || \
02701                                        ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH2)         || \
02702                                        ((INPUT) == COMP_INVERTINGINPUT_IO1)              || \
02703                                        ((INPUT) == COMP_INVERTINGINPUT_DAC2_CH1))
02704
02705 #define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
02706                                           ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
02707
02708 /* STM32F373xB/xC, STM32F378xx devices comparator instances non inverting source values */
02709 #define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT)    \
02710    ((((INSTANCE) == COMP1)  &&                                 \
02711     (((INPUT) == COMP_NONINVERTINGINPUT_IO1)                || \
02712      ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED)))    \
02713     ||                                                         \
02714     (((INPUT) == COMP_NONINVERTINGINPUT_IO1)))
02715
02716 #define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \
02717                                         ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE))
02718
02719 #define IS_COMP_MODE(MODE)  (((MODE) == COMP_MODE_HIGHSPEED)     || \
02720                              ((MODE) == COMP_MODE_MEDIUMSPEED)   || \
02721                              ((MODE) == COMP_MODE_LOWPOWER)      || \
02722                              ((MODE) == COMP_MODE_ULTRALOWPOWER))
02723
02724 #define IS_COMP_HYSTERESIS(HYSTERESIS)    (((HYSTERESIS) == COMP_HYSTERESIS_NONE)   || \
02725                                            ((HYSTERESIS) == COMP_HYSTERESIS_LOW)    || \
02726                                            ((HYSTERESIS) == COMP_HYSTERESIS_MEDIUM) || \
02727                                            ((HYSTERESIS) == COMP_HYSTERESIS_HIGH))
02728
02729 #define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE)                || \
02730                                 ((OUTPUT) == COMP_OUTPUT_TIM2IC4)             || \
02731                                 ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)        || \
02732                                 ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3IC1)       || \
02733                                 ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3OCREFCLR)  || \
02734                                 ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3IC1)       || \
02735                                 ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3OCREFCLR)  || \
02736                                 ((OUTPUT) == COMP_OUTPUT_TIM4IC1)             || \
02737                                 ((OUTPUT) == COMP_OUTPUT_TIM4OCREFCLR)        || \
02738                                 ((OUTPUT) == COMP_OUTPUT_TIM5IC4)             || \
02739                                 ((OUTPUT) == COMP_OUTPUT_TIM5OCREFCLR)        || \
02740                                 ((OUTPUT) == COMP_OUTPUT_TIM15BKIN)           || \
02741                                 ((OUTPUT) == COMP_OUTPUT_TIM16BKIN))
02742
02743 #define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT)      \
02744    ((((INSTANCE) == COMP1)  &&                         \
02745     (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
02746      ((OUTPUT) == COMP_OUTPUT_TIM2IC4)            ||   \
02747      ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)       ||   \
02748      ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3IC1)      ||   \
02749      ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3OCREFCLR) ||   \
02750      ((OUTPUT) == COMP_OUTPUT_TIM5IC4)            ||   \
02751      ((OUTPUT) == COMP_OUTPUT_TIM5OCREFCLR)       ||   \
02752      ((OUTPUT) == COMP_OUTPUT_TIM15BKIN)))             \
02753     ||                                                 \
02754     (((INSTANCE) == COMP2)  &&                         \
02755     (((OUTPUT) == COMP_OUTPUT_NONE)               ||   \
02756      ((OUTPUT) == COMP_OUTPUT_TIM2IC4)            ||   \
02757      ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR)       ||   \
02758      ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3IC1)      ||   \
02759      ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3OCREFCLR) ||   \
02760      ((OUTPUT) == COMP_OUTPUT_TIM4IC1)            ||   \
02761      ((OUTPUT) == COMP_OUTPUT_TIM4OCREFCLR)       ||   \
02762      ((OUTPUT) == COMP_OUTPUT_TIM16BKIN))))
02763
02764 #define IS_COMP_BLANKINGSRCE(SOURCE) ((SOURCE) == (SOURCE)) /*!< Not available: check always true */
02765
02766 /* STM32F373xB/STM32F373xC/STM32F378xx devices comparator instances blanking source values */
02767 #define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
02768    ((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2))  &&     \
02769      ((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE))
02770
02771 #endif /* STM32F373xC || STM32F378xx */
02772
02773 /**
02774   * @}
02775   */
02776
02777 /**
02778   * @}
02779   */
02780
02781 /**
02782   * @}
02783   */
02784
02785 /**
02786   * @}
02787   */
02788
02789 #ifdef __cplusplus
02790 }
02791 #endif
02792
02793 #endif /* __STM32F3xx_HAL_COMP_EX_H */
02794
02795 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_conf.h Source File

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stm32f3xx_hal_conf.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_conf.h
00004   * @author  MCD Application Team
00005   * @brief   HAL configuration file.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_CONF_H
00038 #define __STM32F3xx_HAL_CONF_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Exported types ------------------------------------------------------------*/
00045 /* Exported constants --------------------------------------------------------*/
00046
00047 /* ########################## Module Selection ############################## */
00048 /**
00049   * @brief This is the list of modules to be used in the HAL driver
00050   */
00051 #define HAL_MODULE_ENABLED
00052 #define HAL_ADC_MODULE_ENABLED
00053 #define HAL_CAN_MODULE_ENABLED
00054 #define HAL_CEC_MODULE_ENABLED
00055 #define HAL_COMP_MODULE_ENABLED
00056 #define HAL_CORTEX_MODULE_ENABLED
00057 #define HAL_CRC_MODULE_ENABLED
00058 #define HAL_DAC_MODULE_ENABLED
00059 #define HAL_DMA_MODULE_ENABLED
00060 #define HAL_FLASH_MODULE_ENABLED
00061 #define HAL_SRAM_MODULE_ENABLED
00062 #define HAL_NOR_MODULE_ENABLED
00063 #define HAL_NAND_MODULE_ENABLED
00064 #define HAL_PCCARD_MODULE_ENABLED
00065 #define HAL_GPIO_MODULE_ENABLED
00066 #define HAL_HRTIM_MODULE_ENABLED
00067 #define HAL_I2C_MODULE_ENABLED
00068 #define HAL_I2S_MODULE_ENABLED
00069 #define HAL_IRDA_MODULE_ENABLED
00070 #define HAL_IWDG_MODULE_ENABLED
00071 #define HAL_OPAMP_MODULE_ENABLED
00072 #define HAL_PCD_MODULE_ENABLED
00073 #define HAL_PWR_MODULE_ENABLED
00074 #define HAL_RCC_MODULE_ENABLED
00075 #define HAL_RTC_MODULE_ENABLED
00076 #define HAL_SDADC_MODULE_ENABLED
00077 #define HAL_SMARTCARD_MODULE_ENABLED
00078 #define HAL_SMBUS_MODULE_ENABLED
00079 #define HAL_SPI_MODULE_ENABLED
00080 #define HAL_TIM_MODULE_ENABLED
00081 #define HAL_TSC_MODULE_ENABLED
00082 #define HAL_UART_MODULE_ENABLED
00083 #define HAL_USART_MODULE_ENABLED
00084 #define HAL_WWDG_MODULE_ENABLED
00085
00086 /* ########################## HSE/HSI Values adaptation ##################### */
00087 /**
00088   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
00089   *        This value is used by the RCC HAL module to compute the system frequency
00090   *        (when HSE is used as system clock source, directly or through the PLL).
00091   */
00092 #if !defined  (HSE_VALUE)
00093   #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
00094 #endif /* HSE_VALUE */
00095
00096 /**
00097   * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
00098   *        Timeout value
00099   */
00100 #if !defined  (HSE_STARTUP_TIMEOUT)
00101   #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
00102 #endif /* HSE_STARTUP_TIMEOUT */
00103
00104 /**
00105   * @brief Internal High Speed oscillator (HSI) value.
00106   *        This value is used by the RCC HAL module to compute the system frequency
00107   *        (when HSI is used as system clock source, directly or through the PLL).
00108   */
00109 #if !defined  (HSI_VALUE)
00110   #define HSI_VALUE    (8000000U) /*!< Value of the Internal oscillator in Hz*/
00111 #endif /* HSI_VALUE */
00112
00113 /**
00114   * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
00115   *        Timeout value
00116   */
00117 #if !defined  (HSI_STARTUP_TIMEOUT)
00118  #define HSI_STARTUP_TIMEOUT   (5000U) /*!< Time out for HSI start up */
00119 #endif /* HSI_STARTUP_TIMEOUT */
00120
00121 /**
00122   * @brief Internal Low Speed oscillator (LSI) value.
00123   */
00124 #if !defined  (LSI_VALUE)
00125  #define LSI_VALUE  (40000U)
00126 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
00127                                              The real value may vary depending on the variations
00128                                              in voltage and temperature.  */
00129 /**
00130   * @brief External Low Speed oscillator (LSE) value.
00131   */
00132 #if !defined  (LSE_VALUE)
00133  #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
00134 #endif /* LSE_VALUE */
00135
00136 /**
00137   * @brief Time out for LSE start up value in ms.
00138   */
00139 #if !defined  (LSE_STARTUP_TIMEOUT)
00140   #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
00141 #endif /* LSE_STARTUP_TIMEOUT */
00142
00143 /**
00144   * @brief External clock source for I2S peripheral
00145   *        This value is used by the I2S HAL module to compute the I2S clock source
00146   *        frequency, this source is inserted directly through I2S_CKIN pad.
00147   *        - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
00148   *        - External clock not generated on EVAL 373
00149   */
00150 #if !defined  (EXTERNAL_CLOCK_VALUE)
00151   #define EXTERNAL_CLOCK_VALUE    (8000000U) /*!< Value of the External oscillator in Hz*/
00152 #endif /* EXTERNAL_CLOCK_VALUE */
00153
00154 /* Tip: To avoid modifying this file each time you need to use different HSE,
00155    ===  you can define the HSE value in your toolchain compiler preprocessor. */
00156
00157 /* ########################### System Configuration ######################### */
00158 /**
00159   * @brief This is the HAL system configuration section
00160   */
00161 #define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
00162 #define  TICK_INT_PRIORITY            ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U)   /*!< tick interrupt priority (lowest by default) */
00163 #define  USE_RTOS                     0U
00164 #define  PREFETCH_ENABLE              1U
00165 #define  INSTRUCTION_CACHE_ENABLE     0U
00166 #define  DATA_CACHE_ENABLE            0U
00167 #define  USE_SPI_CRC                  1U
00168
00169 /* ########################## Assert Selection ############################## */
00170 /**
00171   * @brief Uncomment the line below to expanse the "assert_param" macro in the
00172   *        HAL drivers code
00173   */
00174 /*#define USE_FULL_ASSERT    1U*/
00175
00176 /* Includes ------------------------------------------------------------------*/
00177 /**
00178   * @brief Include module's header file
00179   */
00180
00181 #ifdef HAL_RCC_MODULE_ENABLED
00182  #include "stm32f3xx_hal_rcc.h"
00183 #endif /* HAL_RCC_MODULE_ENABLED */
00184
00185 #ifdef HAL_GPIO_MODULE_ENABLED
00186  #include "stm32f3xx_hal_gpio.h"
00187 #endif /* HAL_GPIO_MODULE_ENABLED */
00188
00189 #ifdef HAL_DMA_MODULE_ENABLED
00190   #include "stm32f3xx_hal_dma.h"
00191 #endif /* HAL_DMA_MODULE_ENABLED */
00192
00193 #ifdef HAL_CORTEX_MODULE_ENABLED
00194  #include "stm32f3xx_hal_cortex.h"
00195 #endif /* HAL_CORTEX_MODULE_ENABLED */
00196
00197 #ifdef HAL_ADC_MODULE_ENABLED
00198  #include "stm32f3xx_hal_adc.h"
00199 #endif /* HAL_ADC_MODULE_ENABLED */
00200
00201 #ifdef HAL_CAN_MODULE_ENABLED
00202  #include "stm32f3xx_hal_can.h"
00203 #endif /* HAL_CAN_MODULE_ENABLED */
00204
00205 #ifdef HAL_CEC_MODULE_ENABLED
00206  #include "stm32f3xx_hal_cec.h"
00207 #endif /* HAL_CEC_MODULE_ENABLED */
00208
00209 #ifdef HAL_COMP_MODULE_ENABLED
00210  #include "stm32f3xx_hal_comp.h"
00211 #endif /* HAL_COMP_MODULE_ENABLED */
00212
00213 #ifdef HAL_CRC_MODULE_ENABLED
00214  #include "stm32f3xx_hal_crc.h"
00215 #endif /* HAL_CRC_MODULE_ENABLED */
00216
00217 #ifdef HAL_DAC_MODULE_ENABLED
00218  #include "stm32f3xx_hal_dac.h"
00219 #endif /* HAL_DAC_MODULE_ENABLED */
00220
00221 #ifdef HAL_FLASH_MODULE_ENABLED
00222  #include "stm32f3xx_hal_flash.h"
00223 #endif /* HAL_FLASH_MODULE_ENABLED */
00224
00225 #ifdef HAL_SRAM_MODULE_ENABLED
00226   #include "stm32f3xx_hal_sram.h"
00227 #endif /* HAL_SRAM_MODULE_ENABLED */
00228
00229 #ifdef HAL_NOR_MODULE_ENABLED
00230   #include "stm32f3xx_hal_nor.h"
00231 #endif /* HAL_NOR_MODULE_ENABLED */
00232
00233 #ifdef HAL_NAND_MODULE_ENABLED
00234   #include "stm32f3xx_hal_nand.h"
00235 #endif /* HAL_NAND_MODULE_ENABLED */
00236
00237 #ifdef HAL_PCCARD_MODULE_ENABLED
00238   #include "stm32f3xx_hal_pccard.h"
00239 #endif /* HAL_PCCARD_MODULE_ENABLED */
00240
00241 #ifdef HAL_HRTIM_MODULE_ENABLED
00242  #include "stm32f3xx_hal_hrtim.h"
00243 #endif /* HAL_HRTIM_MODULE_ENABLED */
00244
00245 #ifdef HAL_I2C_MODULE_ENABLED
00246  #include "stm32f3xx_hal_i2c.h"
00247 #endif /* HAL_I2C_MODULE_ENABLED */
00248
00249 #ifdef HAL_I2S_MODULE_ENABLED
00250  #include "stm32f3xx_hal_i2s.h"
00251 #endif /* HAL_I2S_MODULE_ENABLED */
00252
00253 #ifdef HAL_IRDA_MODULE_ENABLED
00254  #include "stm32f3xx_hal_irda.h"
00255 #endif /* HAL_IRDA_MODULE_ENABLED */
00256
00257 #ifdef HAL_IWDG_MODULE_ENABLED
00258  #include "stm32f3xx_hal_iwdg.h"
00259 #endif /* HAL_IWDG_MODULE_ENABLED */
00260
00261 #ifdef HAL_OPAMP_MODULE_ENABLED
00262  #include "stm32f3xx_hal_opamp.h"
00263 #endif /* HAL_OPAMP_MODULE_ENABLED */
00264
00265 #ifdef HAL_PCD_MODULE_ENABLED
00266  #include "stm32f3xx_hal_pcd.h"
00267 #endif /* HAL_PCD_MODULE_ENABLED */
00268
00269 #ifdef HAL_PWR_MODULE_ENABLED
00270  #include "stm32f3xx_hal_pwr.h"
00271 #endif /* HAL_PWR_MODULE_ENABLED */
00272
00273 #ifdef HAL_RTC_MODULE_ENABLED
00274  #include "stm32f3xx_hal_rtc.h"
00275 #endif /* HAL_RTC_MODULE_ENABLED */
00276
00277 #ifdef HAL_SDADC_MODULE_ENABLED
00278  #include "stm32f3xx_hal_sdadc.h"
00279 #endif /* HAL_SDADC_MODULE_ENABLED */
00280
00281 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00282  #include "stm32f3xx_hal_smartcard.h"
00283 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00284
00285 #ifdef HAL_SMBUS_MODULE_ENABLED
00286  #include "stm32f3xx_hal_smbus.h"
00287 #endif /* HAL_SMBUS_MODULE_ENABLED */
00288
00289 #ifdef HAL_SPI_MODULE_ENABLED
00290  #include "stm32f3xx_hal_spi.h"
00291 #endif /* HAL_SPI_MODULE_ENABLED */
00292
00293 #ifdef HAL_TIM_MODULE_ENABLED
00294  #include "stm32f3xx_hal_tim.h"
00295 #endif /* HAL_TIM_MODULE_ENABLED */
00296
00297 #ifdef HAL_TSC_MODULE_ENABLED
00298  #include "stm32f3xx_hal_tsc.h"
00299 #endif /* HAL_TSC_MODULE_ENABLED */
00300
00301 #ifdef HAL_UART_MODULE_ENABLED
00302  #include "stm32f3xx_hal_uart.h"
00303 #endif /* HAL_UART_MODULE_ENABLED */
00304
00305 #ifdef HAL_USART_MODULE_ENABLED
00306  #include "stm32f3xx_hal_usart.h"
00307 #endif /* HAL_USART_MODULE_ENABLED */
00308
00309 #ifdef HAL_WWDG_MODULE_ENABLED
00310  #include "stm32f3xx_hal_wwdg.h"
00311 #endif /* HAL_WWDG_MODULE_ENABLED */
00312
00313 /* Exported macro ------------------------------------------------------------*/
00314 #ifdef  USE_FULL_ASSERT
00315 /**
00316   * @brief  The assert_param macro is used for function's parameters check.
00317   * @param  expr If expr is false, it calls assert_failed function
00318   *         which reports the name of the source file and the source
00319   *         line number of the call that failed.
00320   *         If expr is true, it returns no value.
00321   * @retval None
00322   */
00323   #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
00324 /* Exported functions ------------------------------------------------------- */
00325   void assert_failed(char* file, uint32_t line);
00326 #else
00327   #define assert_param(expr) ((void)0U)
00328 #endif /* USE_FULL_ASSERT */
00329
00330 #ifdef __cplusplus
00331 }
00332 #endif
00333
00334 #endif /* __STM32F3xx_HAL_CONF_H */
00335
00336
00337 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_cortex.c Source File

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stm32f3xx_hal_cortex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_cortex.c
00004   * @author  MCD Application Team
00005   * @brief   CORTEX HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the CORTEX:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   *  @verbatim
00012   ==============================================================================
00013                         ##### How to use this driver #####
00014   ==============================================================================
00015
00016     [..]
00017     *** How to configure Interrupts using CORTEX HAL driver ***
00018     ===========================================================
00019     [..]
00020     This section provides functions allowing to configure the NVIC interrupts (IRQ).
00021     The Cortex-M4 exceptions are managed by CMSIS functions.
00022
00023     (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function
00024
00025      (#)  Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
00026
00027      (#)  Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
00028
00029
00030      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
00031          The pending IRQ priority will be managed only by the sub priority.
00032
00033      -@- IRQ priority order (sorted by highest to lowest priority):
00034         (+@) Lowest pre-emption priority
00035         (+@) Lowest sub priority
00036         (+@) Lowest hardware priority (IRQ number)
00037
00038     [..]
00039     *** How to configure Systick using CORTEX HAL driver ***
00040     ========================================================
00041     [..]
00042     Setup SysTick Timer for time base
00043
00044    (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
00045        is a CMSIS function that:
00046         (++) Configures the SysTick Reload register with value passed as function parameter.
00047         (++) Configures the SysTick IRQ priority to the lowest value (0x0FU).
00048         (++) Resets the SysTick Counter register.
00049         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
00050         (++) Enables the SysTick Interrupt.
00051         (++) Starts the SysTick Counter.
00052
00053    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
00054        __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
00055        HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
00056        inside the stm32f3xx_hal_cortex.h file.
00057
00058    (+) You can change the SysTick IRQ priority by calling the
00059        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
00060        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
00061
00062    (+) To adjust the SysTick time base, use the following formula:
00063
00064        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
00065        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
00066        (++) Reload Value should not exceed 0xFFFFFF
00067
00068   @endverbatim
00069   ******************************************************************************
00070   * @attention
00071   *
00072   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00073   *
00074   * Redistribution and use in source and binary forms, with or without modification,
00075   * are permitted provided that the following conditions are met:
00076   *   1. Redistributions of source code must retain the above copyright notice,
00077   *      this list of conditions and the following disclaimer.
00078   *   2. Redistributions in binary form must reproduce the above copyright notice,
00079   *      this list of conditions and the following disclaimer in the documentation
00080   *      and/or other materials provided with the distribution.
00081   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00082   *      may be used to endorse or promote products derived from this software
00083   *      without specific prior written permission.
00084   *
00085   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00086   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00087   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00088   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00089   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00090   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00091   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00092   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00093   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00094   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00095   *
00096   ******************************************************************************
00097   */
00098
00099 /*
00100   Additional Tables: CORTEX_NVIC_Priority_Table
00101      The table below gives the allowed values of the pre-emption priority and subpriority according
00102      to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function
00103        ==========================================================================================================================
00104          NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
00105        ==========================================================================================================================
00106         NVIC_PRIORITYGROUP_0  |                0                  |            0U-15             | 0 bits for pre-emption priority
00107                               |                                   |                             | 4 bits for subpriority
00108        --------------------------------------------------------------------------------------------------------------------------
00109         NVIC_PRIORITYGROUP_1  |                0U-1                |            0U-7              | 1 bits for pre-emption priority
00110                               |                                   |                             | 3 bits for subpriority
00111        --------------------------------------------------------------------------------------------------------------------------
00112         NVIC_PRIORITYGROUP_2  |                0U-3                |            0U-3              | 2 bits for pre-emption priority
00113                               |                                   |                             | 2 bits for subpriority
00114        --------------------------------------------------------------------------------------------------------------------------
00115         NVIC_PRIORITYGROUP_3  |                0U-7                |            0U-1              | 3 bits for pre-emption priority
00116                               |                                   |                             | 1 bits for subpriority
00117        --------------------------------------------------------------------------------------------------------------------------
00118         NVIC_PRIORITYGROUP_4  |                0U-15               |            0                | 4 bits for pre-emption priority
00119                               |                                   |                             | 0 bits for subpriority
00120        ==========================================================================================================================
00121
00122 */
00123
00124 /* Includes ------------------------------------------------------------------*/
00125 #include "stm32f3xx_hal.h"
00126
00127 /** @addtogroup STM32F3xx_HAL_Driver
00128   * @{
00129   */
00130
00131 /** @defgroup CORTEX CORTEX
00132   * @brief CORTEX CORTEX HAL module driver
00133   * @{
00134   */
00135
00136 #ifdef HAL_CORTEX_MODULE_ENABLED
00137
00138 /* Private typedef -----------------------------------------------------------*/
00139 /* Private define ------------------------------------------------------------*/
00140 /* Private macro -------------------------------------------------------------*/
00141 /* Private variables ---------------------------------------------------------*/
00142 /* Private function prototypes -----------------------------------------------*/
00143 /* Exported functions ---------------------------------------------------------*/
00144
00145 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
00146   * @{
00147   */
00148
00149
00150 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
00151  *  @brief    Initialization and Configuration functions
00152  *
00153 @verbatim
00154   ==============================================================================
00155               ##### Initialization and de-initialization functions #####
00156   ==============================================================================
00157     [..]
00158       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
00159       Systick functionalities
00160
00161 @endverbatim
00162   * @{
00163   */
00164
00165
00166 /**
00167   * @brief  Sets the priority grouping field (pre-emption priority and subpriority)
00168   *         using the required unlock sequence.
00169   * @param  PriorityGroup The priority grouping bits length.
00170   *         This parameter can be one of the following values:
00171   *         @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
00172   *                                    4 bits for subpriority
00173   *         @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
00174   *                                    3 bits for subpriority
00175   *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
00176   *                                    2 bits for subpriority
00177   *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
00178   *                                    1 bits for subpriority
00179   *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
00180   *                                    0 bits for subpriority
00181   * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
00182   *         The pending IRQ priority will be managed only by the subpriority.
00183   * @retval None
00184   */
00185 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
00186 {
00187   /* Check the parameters */
00188   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00189
00190   /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
00191   NVIC_SetPriorityGrouping(PriorityGroup);
00192 }
00193
00194 /**
00195   * @brief  Sets the priority of an interrupt.
00196   * @param  IRQn External interrupt number
00197   *         This parameter can be an enumerator of IRQn_Type enumeration
00198   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
00199   * @param  PreemptPriority The pre-emption priority for the IRQn channel.
00200   *         This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
00201   *         A lower priority value indicates a higher priority
00202   * @param  SubPriority the subpriority level for the IRQ channel.
00203   *         This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
00204   *         A lower priority value indicates a higher priority.
00205   * @retval None
00206   */
00207 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
00208 {
00209   uint32_t prioritygroup = 0x00U;
00210
00211   /* Check the parameters */
00212   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
00213   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
00214
00215   prioritygroup = NVIC_GetPriorityGrouping();
00216
00217   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
00218 }
00219
00220 /**
00221   * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
00222   * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
00223   *         function should be called before.
00224   * @param  IRQn External interrupt number
00225   *         This parameter can be an enumerator of IRQn_Type enumeration
00226   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
00227   * @retval None
00228   */
00229 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
00230 {
00231   /* Check the parameters */
00232   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00233
00234   /* Enable interrupt */
00235   NVIC_EnableIRQ(IRQn);
00236 }
00237
00238 /**
00239   * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
00240   * @param  IRQn External interrupt number
00241   *         This parameter can be an enumerator of IRQn_Type enumeration
00242   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
00243   * @retval None
00244   */
00245 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
00246 {
00247   /* Check the parameters */
00248   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00249
00250   /* Disable interrupt */
00251   NVIC_DisableIRQ(IRQn);
00252 }
00253
00254 /**
00255   * @brief  Initiates a system reset request to reset the MCU.
00256   * @retval None
00257   */
00258 void HAL_NVIC_SystemReset(void)
00259 {
00260   /* System Reset */
00261   NVIC_SystemReset();
00262 }
00263
00264 /**
00265   * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
00266   *         Counter is in free running mode to generate periodic interrupts.
00267   * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
00268   * @retval status:  - 0  Function succeeded.
00269   *                  - 1  Function failed.
00270   */
00271 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
00272 {
00273    return SysTick_Config(TicksNumb);
00274 }
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
00280  *  @brief   Cortex control functions
00281  *
00282 @verbatim
00283   ==============================================================================
00284                       ##### Peripheral Control functions #####
00285   ==============================================================================
00286     [..]
00287       This subsection provides a set of functions allowing to control the CORTEX
00288       (NVIC, SYSTICK, MPU) functionalities.
00289
00290
00291 @endverbatim
00292   * @{
00293   */
00294
00295 #if (__MPU_PRESENT == 1U)
00296
00297 /**
00298   * @brief  Disables the MPU also clears the HFNMIENA bit (ARM recommendation)
00299   * @retval None
00300   */
00301 void HAL_MPU_Disable(void)
00302 {
00303   /* Disable fault exceptions */
00304   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
00305
00306   /* Disable the MPU */
00307   MPU->CTRL = 0U;
00308 }
00309
00310 /**
00311   * @brief  Enables the MPU
00312   * @param  MPU_Control Specifies the control mode of the MPU during hard fault,
00313   *          NMI, FAULTMASK and privileged access to the default memory
00314   *          This parameter can be one of the following values:
00315   *            @arg MPU_HFNMI_PRIVDEF_NONE
00316   *            @arg MPU_HARDFAULT_NMI
00317   *            @arg MPU_PRIVILEGED_DEFAULT
00318   *            @arg MPU_HFNMI_PRIVDEF
00319   * @retval None
00320   */
00321 void HAL_MPU_Enable(uint32_t MPU_Control)
00322 {
00323   /* Enable the MPU */
00324   MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
00325
00326   /* Enable fault exceptions */
00327   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
00328 }
00329
00330         /**
00331   * @brief  Initializes and configures the Region and the memory to be protected.
00332   * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
00333   *                the initialization and configuration information.
00334   * @retval None
00335   */
00336 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
00337 {
00338   /* Check the parameters */
00339   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
00340   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
00341
00342   /* Set the Region number */
00343   MPU->RNR = MPU_Init->Number;
00344
00345   if ((MPU_Init->Enable) != RESET)
00346   {
00347     /* Check the parameters */
00348     assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
00349     assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
00350     assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
00351     assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
00352     assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
00353     assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
00354     assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
00355     assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
00356
00357     MPU->RBAR = MPU_Init->BaseAddress;
00358     MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
00359                 ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
00360                 ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
00361                 ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
00362                 ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
00363                 ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
00364                 ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
00365                 ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
00366                 ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
00367   }
00368   else
00369   {
00370     MPU->RBAR = 0x00U;
00371     MPU->RASR = 0x00U;
00372   }
00373 }
00374 #endif /* __MPU_PRESENT */
00375
00376 /**
00377   * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
00378   * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
00379   */
00380 uint32_t HAL_NVIC_GetPriorityGrouping(void)
00381 {
00382   /* Get the PRIGROUP[10:8] field value */
00383   return NVIC_GetPriorityGrouping();
00384 }
00385
00386 /**
00387   * @brief  Gets the priority of an interrupt.
00388   * @param  IRQn External interrupt number
00389   *         This parameter can be an enumerator of IRQn_Type enumeration
00390   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
00391   * @param   PriorityGroup: the priority grouping bits length.
00392   *         This parameter can be one of the following values:
00393   *           @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
00394   *                                      4 bits for subpriority
00395   *           @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
00396   *                                      3 bits for subpriority
00397   *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
00398   *                                      2 bits for subpriority
00399   *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
00400   *                                      1 bits for subpriority
00401   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
00402   *                                      0 bits for subpriority
00403   * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
00404   * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
00405   * @retval None
00406   */
00407 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
00408 {
00409   /* Check the parameters */
00410   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00411   /* Get priority for Cortex-M system or device specific interrupts */
00412   NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
00413 }
00414
00415 /**
00416   * @brief  Sets Pending bit of an external interrupt.
00417   * @param  IRQn External interrupt number
00418   *         This parameter can be an enumerator of IRQn_Type enumeration
00419   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
00420   * @retval None
00421   */
00422 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
00423 {
00424   /* Set interrupt pending */
00425   NVIC_SetPendingIRQ(IRQn);
00426 }
00427
00428 /**
00429   * @brief  Gets Pending Interrupt (reads the pending register in the NVIC
00430   *         and returns the pending bit for the specified interrupt).
00431   * @param  IRQn External interrupt number
00432   *         This parameter can be an enumerator of IRQn_Type enumeration
00433   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
00434   * @retval status: - 0  Interrupt status is not pending.
00435   *                 - 1  Interrupt status is pending.
00436   */
00437 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
00438 {
00439   /* Return 1 if pending else 0U */
00440   return NVIC_GetPendingIRQ(IRQn);
00441 }
00442
00443 /**
00444   * @brief  Clears the pending bit of an external interrupt.
00445   * @param  IRQn External interrupt number
00446   *         This parameter can be an enumerator of IRQn_Type enumeration
00447   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
00448   * @retval None
00449   */
00450 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
00451 {
00452   /* Clear pending interrupt */
00453   NVIC_ClearPendingIRQ(IRQn);
00454 }
00455
00456 /**
00457   * @brief  Gets active interrupt ( reads the active register in NVIC and returns the active bit).
00458   * @param  IRQn External interrupt number
00459   *         This parameter can be an enumerator of IRQn_Type enumeration
00460   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
00461   * @retval status: - 0  Interrupt status is not pending.
00462   *                 - 1  Interrupt status is pending.
00463   */
00464 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
00465 {
00466   /* Return 1 if active else 0U */
00467   return NVIC_GetActive(IRQn);
00468 }
00469
00470 /**
00471   * @brief  Configures the SysTick clock source.
00472   * @param  CLKSource specifies the SysTick clock source.
00473   *         This parameter can be one of the following values:
00474   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
00475   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
00476   * @retval None
00477   */
00478 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
00479 {
00480   /* Check the parameters */
00481   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
00482   if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
00483   {
00484     SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
00485   }
00486   else
00487   {
00488     SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
00489   }
00490 }
00491
00492 /**
00493   * @brief  This function handles SYSTICK interrupt request.
00494   * @retval None
00495   */
00496 void HAL_SYSTICK_IRQHandler(void)
00497 {
00498   HAL_SYSTICK_Callback();
00499 }
00500
00501 /**
00502   * @brief  SYSTICK callback.
00503   * @retval None
00504   */
00505 __weak void HAL_SYSTICK_Callback(void)
00506 {
00507   /* NOTE : This function Should not be modified, when the callback is needed,
00508             the HAL_SYSTICK_Callback could be implemented in the user file
00509    */
00510 }
00511
00512 /**
00513   * @}
00514   */
00515
00516 /**
00517   * @}
00518   */
00519
00520 #endif /* HAL_CORTEX_MODULE_ENABLED */
00521 /**
00522   * @}
00523   */
00524
00525 /**
00526   * @}
00527   */
00528
00529 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_cortex.h Source File

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stm32f3xx_hal_cortex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_cortex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CORTEX HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_CORTEX_H
00038 #define __STM32F3xx_HAL_CORTEX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup CORTEX
00052   * @{
00053   */
00054 /* Exported types ------------------------------------------------------------*/
00055 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types
00056   * @{
00057   */
00058
00059 #if (__MPU_PRESENT == 1U)
00060 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
00061   * @brief  MPU Region initialization structure
00062   * @{
00063   */
00064 typedef struct
00065 {
00066   uint8_t                Enable;                /*!< Specifies the status of the region.
00067                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
00068   uint8_t                Number;                /*!< Specifies the number of the region to protect.
00069                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
00070   uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
00071   uint8_t                Size;                  /*!< Specifies the size of the region to protect.
00072                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
00073   uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
00074                                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
00075   uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
00076                                                      This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
00077   uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
00078                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
00079   uint8_t                DisableExec;           /*!< Specifies the instruction access status.
00080                                                      This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
00081   uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
00082                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
00083   uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
00084                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
00085   uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
00086                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
00087 }MPU_Region_InitTypeDef;
00088 /**
00089   * @}
00090   */
00091 #endif /* __MPU_PRESENT */
00092
00093 /**
00094   * @}
00095   */
00096
00097 /* Exported constants --------------------------------------------------------*/
00098
00099 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
00100   * @{
00101   */
00102
00103 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
00104   * @{
00105   */
00106 #define NVIC_PRIORITYGROUP_0         (0x00000007U) /*!< 0 bits for pre-emption priority
00107                                                                  4 bits for subpriority */
00108 #define NVIC_PRIORITYGROUP_1         (0x00000006U) /*!< 1 bits for pre-emption priority
00109                                                                  3 bits for subpriority */
00110 #define NVIC_PRIORITYGROUP_2         (0x00000005U) /*!< 2 bits for pre-emption priority
00111                                                                  2 bits for subpriority */
00112 #define NVIC_PRIORITYGROUP_3         (0x00000004U) /*!< 3 bits for pre-emption priority
00113                                                                  1 bits for subpriority */
00114 #define NVIC_PRIORITYGROUP_4         (0x00000003U) /*!< 4 bits for pre-emption priority
00115                                                                  0 bits for subpriority */
00116 /**
00117   * @}
00118   */
00119
00120 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
00121   * @{
00122   */
00123 #define SYSTICK_CLKSOURCE_HCLK_DIV8    (0x00000000U)
00124 #define SYSTICK_CLKSOURCE_HCLK         (0x00000004U)
00125 /**
00126   * @}
00127   */
00128
00129 #if (__MPU_PRESENT == 1U)
00130 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
00131   * @{
00132   */
00133 #define  MPU_HFNMI_PRIVDEF_NONE      (0x00000000U)
00134 #define  MPU_HARDFAULT_NMI           (0x00000002U)
00135 #define  MPU_PRIVILEGED_DEFAULT      (0x00000004U)
00136 #define  MPU_HFNMI_PRIVDEF           (0x00000006U)
00137 /**
00138   * @}
00139   */
00140
00141 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
00142   * @{
00143   */
00144 #define  MPU_REGION_ENABLE     ((uint8_t)0x01U)
00145 #define  MPU_REGION_DISABLE    ((uint8_t)0x00U)
00146 /**
00147   * @}
00148   */
00149
00150 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
00151   * @{
00152   */
00153 #define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00U)
00154 #define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01U)
00155 /**
00156   * @}
00157   */
00158
00159 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
00160   * @{
00161   */
00162 #define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01U)
00163 #define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00U)
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
00169   * @{
00170   */
00171 #define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01U)
00172 #define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00U)
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
00178   * @{
00179   */
00180 #define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01U)
00181 #define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00U)
00182 /**
00183   * @}
00184   */
00185
00186 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
00187   * @{
00188   */
00189 #define  MPU_TEX_LEVEL0    ((uint8_t)0x00U)
00190 #define  MPU_TEX_LEVEL1    ((uint8_t)0x01U)
00191 #define  MPU_TEX_LEVEL2    ((uint8_t)0x02U)
00192 /**
00193   * @}
00194   */
00195
00196 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
00197   * @{
00198   */
00199 #define   MPU_REGION_SIZE_32B      ((uint8_t)0x04U)
00200 #define   MPU_REGION_SIZE_64B      ((uint8_t)0x05U)
00201 #define   MPU_REGION_SIZE_128B     ((uint8_t)0x06U)
00202 #define   MPU_REGION_SIZE_256B     ((uint8_t)0x07U)
00203 #define   MPU_REGION_SIZE_512B     ((uint8_t)0x08U)
00204 #define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09U)
00205 #define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU)
00206 #define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU)
00207 #define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU)
00208 #define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU)
00209 #define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU)
00210 #define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU)
00211 #define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10U)
00212 #define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11U)
00213 #define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12U)
00214 #define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13U)
00215 #define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14U)
00216 #define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15U)
00217 #define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16U)
00218 #define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17U)
00219 #define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18U)
00220 #define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19U)
00221 #define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU)
00222 #define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU)
00223 #define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU)
00224 #define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU)
00225 #define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU)
00226 #define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU)
00227 /**
00228   * @}
00229   */
00230
00231 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
00232   * @{
00233   */
00234 #define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00U)
00235 #define  MPU_REGION_PRIV_RW        ((uint8_t)0x01U)
00236 #define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02U)
00237 #define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03U)
00238 #define  MPU_REGION_PRIV_RO        ((uint8_t)0x05U)
00239 #define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06U)
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
00245   * @{
00246   */
00247 #define  MPU_REGION_NUMBER0    ((uint8_t)0x00U)
00248 #define  MPU_REGION_NUMBER1    ((uint8_t)0x01U)
00249 #define  MPU_REGION_NUMBER2    ((uint8_t)0x02U)
00250 #define  MPU_REGION_NUMBER3    ((uint8_t)0x03U)
00251 #define  MPU_REGION_NUMBER4    ((uint8_t)0x04U)
00252 #define  MPU_REGION_NUMBER5    ((uint8_t)0x05U)
00253 #define  MPU_REGION_NUMBER6    ((uint8_t)0x06U)
00254 #define  MPU_REGION_NUMBER7    ((uint8_t)0x07U)
00255 /**
00256   * @}
00257   */
00258 #endif /* __MPU_PRESENT */
00259
00260 /**
00261   * @}
00262   */
00263
00264 /* Exported Macros -----------------------------------------------------------*/
00265
00266
00267 /* Exported functions --------------------------------------------------------*/
00268 /** @addtogroup CORTEX_Exported_Functions
00269   * @{
00270   */
00271
00272 /** @addtogroup CORTEX_Exported_Functions_Group1
00273  * @{
00274  */
00275 /* Initialization and de-initialization functions *****************************/
00276 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
00277 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
00278 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
00279 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
00280 void HAL_NVIC_SystemReset(void);
00281 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
00282 /**
00283   * @}
00284   */
00285
00286 /** @addtogroup CORTEX_Exported_Functions_Group2
00287  * @{
00288  */
00289 /* Peripheral Control functions ***********************************************/
00290 #if (__MPU_PRESENT == 1U)
00291 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
00292 #endif /* __MPU_PRESENT */
00293 uint32_t HAL_NVIC_GetPriorityGrouping(void);
00294 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
00295 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
00296 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
00297 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
00298 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
00299 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
00300 void HAL_SYSTICK_IRQHandler(void);
00301 void HAL_SYSTICK_Callback(void);
00302 /**
00303   * @}
00304   */
00305
00306 /**
00307   * @}
00308   */
00309
00310 /* Private types -------------------------------------------------------------*/
00311 /* Private variables ---------------------------------------------------------*/
00312 /* Private constants ---------------------------------------------------------*/
00313 /* Private macros ------------------------------------------------------------*/
00314 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
00315   * @{
00316   */
00317 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
00318                                        ((GROUP) == NVIC_PRIORITYGROUP_1) || \
00319                                        ((GROUP) == NVIC_PRIORITYGROUP_2) || \
00320                                        ((GROUP) == NVIC_PRIORITYGROUP_3) || \
00321                                        ((GROUP) == NVIC_PRIORITYGROUP_4))
00322
00323 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
00324
00325 #define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
00326
00327 #define IS_NVIC_DEVICE_IRQ(IRQ)  ((IRQ) >= 0x00)
00328
00329 /** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
00330   * @{
00331   */
00332 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
00333                                        ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
00334 /**
00335   * @}
00336   */
00337
00338 #if (__MPU_PRESENT == 1U)
00339 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
00340                                      ((STATE) == MPU_REGION_DISABLE))
00341
00342 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
00343                                           ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
00344
00345 #define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
00346                                           ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
00347
00348 #define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
00349                                           ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
00350
00351 #define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
00352                                           ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
00353
00354 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
00355                                 ((TYPE) == MPU_TEX_LEVEL1)  || \
00356                                 ((TYPE) == MPU_TEX_LEVEL2))
00357
00358 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
00359                                                   ((TYPE) == MPU_REGION_PRIV_RW)     || \
00360                                                   ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
00361                                                   ((TYPE) == MPU_REGION_FULL_ACCESS) || \
00362                                                   ((TYPE) == MPU_REGION_PRIV_RO)     || \
00363                                                   ((TYPE) == MPU_REGION_PRIV_RO_URO))
00364
00365 #define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
00366                                          ((NUMBER) == MPU_REGION_NUMBER1) || \
00367                                          ((NUMBER) == MPU_REGION_NUMBER2) || \
00368                                          ((NUMBER) == MPU_REGION_NUMBER3) || \
00369                                          ((NUMBER) == MPU_REGION_NUMBER4) || \
00370                                          ((NUMBER) == MPU_REGION_NUMBER5) || \
00371                                          ((NUMBER) == MPU_REGION_NUMBER6) || \
00372                                          ((NUMBER) == MPU_REGION_NUMBER7))
00373
00374 #define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
00375                                      ((SIZE) == MPU_REGION_SIZE_64B)   || \
00376                                      ((SIZE) == MPU_REGION_SIZE_128B)  || \
00377                                      ((SIZE) == MPU_REGION_SIZE_256B)  || \
00378                                      ((SIZE) == MPU_REGION_SIZE_512B)  || \
00379                                      ((SIZE) == MPU_REGION_SIZE_1KB)   || \
00380                                      ((SIZE) == MPU_REGION_SIZE_2KB)   || \
00381                                      ((SIZE) == MPU_REGION_SIZE_4KB)   || \
00382                                      ((SIZE) == MPU_REGION_SIZE_8KB)   || \
00383                                      ((SIZE) == MPU_REGION_SIZE_16KB)  || \
00384                                      ((SIZE) == MPU_REGION_SIZE_32KB)  || \
00385                                      ((SIZE) == MPU_REGION_SIZE_64KB)  || \
00386                                      ((SIZE) == MPU_REGION_SIZE_128KB) || \
00387                                      ((SIZE) == MPU_REGION_SIZE_256KB) || \
00388                                      ((SIZE) == MPU_REGION_SIZE_512KB) || \
00389                                      ((SIZE) == MPU_REGION_SIZE_1MB)   || \
00390                                      ((SIZE) == MPU_REGION_SIZE_2MB)   || \
00391                                      ((SIZE) == MPU_REGION_SIZE_4MB)   || \
00392                                      ((SIZE) == MPU_REGION_SIZE_8MB)   || \
00393                                      ((SIZE) == MPU_REGION_SIZE_16MB)  || \
00394                                      ((SIZE) == MPU_REGION_SIZE_32MB)  || \
00395                                      ((SIZE) == MPU_REGION_SIZE_64MB)  || \
00396                                      ((SIZE) == MPU_REGION_SIZE_128MB) || \
00397                                      ((SIZE) == MPU_REGION_SIZE_256MB) || \
00398                                      ((SIZE) == MPU_REGION_SIZE_512MB) || \
00399                                      ((SIZE) == MPU_REGION_SIZE_1GB)   || \
00400                                      ((SIZE) == MPU_REGION_SIZE_2GB)   || \
00401                                      ((SIZE) == MPU_REGION_SIZE_4GB))
00402
00403 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FFU)
00404 #endif /* __MPU_PRESENT */
00405
00406 /**
00407   * @}
00408   */
00409
00410 /* Private functions ---------------------------------------------------------*/
00411 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
00412   * @brief    CORTEX private  functions
00413   * @{
00414   */
00415
00416 #if (__MPU_PRESENT == 1U)
00417
00418 void HAL_MPU_Disable(void);
00419 void HAL_MPU_Enable(uint32_t MPU_Control);
00420
00421 #endif /* __MPU_PRESENT */
00422
00423 /**
00424   * @}
00425   */
00426
00427 /**
00428   * @}
00429   */
00430
00431 /**
00432   * @}
00433   */
00434
00435 #ifdef __cplusplus
00436 }
00437 #endif
00438
00439 #endif /* __STM32F3xx_HAL_CORTEX_H */
00440
00441
00442 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_crc.c Source File

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stm32f3xx_hal_crc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_crc.c
00004   * @author  MCD Application Team
00005   * @brief   CRC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *           + Peripheral State functions
00011   *
00012   @verbatim
00013  ===============================================================================
00014                      ##### How to use this driver #####
00015  ===============================================================================
00016     [..]
00017          (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
00018          (+) Initialize CRC calculator
00019              (++)specify generating polynomial (IP default or non-default one)
00020              (++)specify initialization value (IP default or non-default one)
00021              (++)specify input data format
00022              (++)specify input or output data inversion mode if any
00023          (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
00024              input data buffer starting with the previously computed CRC as
00025              initialization value
00026          (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
00027              input data buffer starting with the defined initialization value
00028              (default or non-default) to initiate CRC calculation
00029
00030   @endverbatim
00031   ******************************************************************************
00032   * @attention
00033   *
00034   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00035   *
00036   * Redistribution and use in source and binary forms, with or without modification,
00037   * are permitted provided that the following conditions are met:
00038   *   1. Redistributions of source code must retain the above copyright notice,
00039   *      this list of conditions and the following disclaimer.
00040   *   2. Redistributions in binary form must reproduce the above copyright notice,
00041   *      this list of conditions and the following disclaimer in the documentation
00042   *      and/or other materials provided with the distribution.
00043   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00044   *      may be used to endorse or promote products derived from this software
00045   *      without specific prior written permission.
00046   *
00047   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00048   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00049   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00050   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00051   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00052   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00053   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00054   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00055   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00056   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00057   *
00058   ******************************************************************************
00059   */
00060
00061 /* Includes ------------------------------------------------------------------*/
00062 #include "stm32f3xx_hal.h"
00063
00064 /** @addtogroup STM32F3xx_HAL_Driver
00065   * @{
00066   */
00067
00068 /** @defgroup CRC CRC
00069   * @brief CRC HAL module driver.
00070   * @{
00071   */
00072
00073 #ifdef HAL_CRC_MODULE_ENABLED
00074
00075 /* Private typedef -----------------------------------------------------------*/
00076 /* Private define ------------------------------------------------------------*/
00077 /* Private macro -------------------------------------------------------------*/
00078 /* Private variables ---------------------------------------------------------*/
00079 /* Private function prototypes -----------------------------------------------*/
00080 /** @defgroup CRC_Private_Functions CRC Private Functions
00081   * @{
00082   */
00083 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
00084 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
00085 /**
00086   * @}
00087   */
00088
00089 /* Exported functions --------------------------------------------------------*/
00090
00091 /** @defgroup CRC_Exported_Functions CRC Exported Functions
00092   * @{
00093   */
00094
00095 /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
00096  *  @brief    Initialization and Configuration functions.
00097  *
00098 @verbatim
00099  ===============================================================================
00100             ##### Initialization and de-initialization functions #####
00101  ===============================================================================
00102     [..]  This section provides functions allowing to:
00103       (+) Initialize the CRC according to the specified parameters
00104           in the CRC_InitTypeDef and create the associated handle
00105       (+) DeInitialize the CRC peripheral
00106       (+) Initialize the CRC MSP (MCU Specific Package)
00107       (+) DeInitialize the CRC MSP
00108
00109 @endverbatim
00110   * @{
00111   */
00112
00113 /**
00114   * @brief  Initialize the CRC according to the specified
00115   *         parameters in the CRC_InitTypeDef and initialize the associated handle.
00116   * @param  hcrc CRC handle
00117   * @retval HAL status
00118   */
00119 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
00120 {
00121   /* Check the CRC handle allocation */
00122   if(hcrc == NULL)
00123   {
00124     return HAL_ERROR;
00125   }
00126
00127   /* Check the parameters */
00128   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00129
00130   if(hcrc->State == HAL_CRC_STATE_RESET)
00131   {
00132     /* Allocate lock resource and initialize it */
00133     hcrc->Lock = HAL_UNLOCKED;
00134
00135     /* Init the low level hardware */
00136     HAL_CRC_MspInit(hcrc);
00137   }
00138
00139   hcrc->State = HAL_CRC_STATE_BUSY;
00140
00141   /* check whether or not non-default generating polynomial has been
00142    * picked up by user */
00143   assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
00144   if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
00145   {
00146     /* initialize IP with default generating polynomial */
00147     WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
00148     MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
00149   }
00150   else
00151   {
00152     /* initialize CRC IP with generating polynomial defined by user */
00153     if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
00154     {
00155       return HAL_ERROR;
00156     }
00157   }
00158
00159   /* check whether or not non-default CRC initial value has been
00160    * picked up by user */
00161   assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
00162   if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
00163   {
00164     WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
00165   }
00166   else
00167   {
00168     WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
00169   }
00170
00171
00172   /* set input data inversion mode */
00173   assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
00174   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
00175
00176   /* set output data inversion mode */
00177   assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
00178   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
00179
00180   /* makes sure the input data format (bytes, halfwords or words stream)
00181    * is properly specified by user */
00182   assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
00183
00184   /* Change CRC peripheral state */
00185   hcrc->State = HAL_CRC_STATE_READY;
00186
00187   /* Return function status */
00188   return HAL_OK;
00189 }
00190
00191 /**
00192   * @brief  DeInitialize the CRC peripheral.
00193   * @param  hcrc CRC handle
00194   * @retval HAL status
00195   */
00196 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
00197 {
00198   /* Check the CRC handle allocation */
00199   if(hcrc == NULL)
00200   {
00201     return HAL_ERROR;
00202   }
00203
00204   /* Check the parameters */
00205   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00206
00207   /* Check the CRC peripheral state */
00208   if(hcrc->State == HAL_CRC_STATE_BUSY)
00209   {
00210     return HAL_BUSY;
00211   }
00212
00213   /* Change CRC peripheral state */
00214   hcrc->State = HAL_CRC_STATE_BUSY;
00215
00216   /* Reset CRC calculation unit */
00217   __HAL_CRC_DR_RESET(hcrc);
00218
00219   /* Reset IDR register content */
00220   CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ;
00221
00222   /* DeInit the low level hardware */
00223   HAL_CRC_MspDeInit(hcrc);
00224
00225   /* Change CRC peripheral state */
00226   hcrc->State = HAL_CRC_STATE_RESET;
00227
00228   /* Process unlocked */
00229   __HAL_UNLOCK(hcrc);
00230
00231   /* Return function status */
00232   return HAL_OK;
00233 }
00234
00235 /**
00236   * @brief  Initializes the CRC MSP.
00237   * @param  hcrc CRC handle
00238   * @retval None
00239   */
00240 __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
00241 {
00242   /* Prevent unused argument(s) compilation warning */
00243   UNUSED(hcrc);
00244
00245   /* NOTE : This function should not be modified, when the callback is needed,
00246             the HAL_CRC_MspInit can be implemented in the user file
00247    */
00248 }
00249
00250 /**
00251   * @brief  DeInitialize the CRC MSP.
00252   * @param  hcrc CRC handle
00253   * @retval None
00254   */
00255 __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
00256 {
00257   /* Prevent unused argument(s) compilation warning */
00258   UNUSED(hcrc);
00259
00260   /* NOTE : This function should not be modified, when the callback is needed,
00261             the HAL_CRC_MspDeInit can be implemented in the user file
00262    */
00263 }
00264
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
00270  *  @brief    management functions.
00271  *
00272 @verbatim
00273  ===============================================================================
00274                       ##### Peripheral Control functions #####
00275  ===============================================================================
00276     [..]  This section provides functions allowing to:
00277       (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer
00278           using the combination of the previous CRC value and the new one
00279
00280        [..]  or
00281
00282       (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer
00283           independently of the previous CRC value.
00284
00285 @endverbatim
00286   * @{
00287   */
00288
00289 /**
00290   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00291   *         starting with the previously computed CRC as initialization value.
00292   * @param  hcrc CRC handle
00293   * @param  pBuffer pointer to the input data buffer, exact input data format is
00294   *         provided by hcrc->InputDataFormat.
00295   * @param  BufferLength input data buffer length (number of bytes if pBuffer
00296   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
00297   *         number of words if pBuffer type is * uint32_t).
00298   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
00299   *        Input buffer pointers with other types simply need to be cast in uint32_t
00300   *        and the API will internally adjust its input data processing based on the
00301   *        handle field hcrc->InputDataFormat.
00302   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00303   */
00304 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00305 {
00306   uint32_t index = 0U; /* CRC input data buffer index */
00307   uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
00308
00309   /* Process locked */
00310   __HAL_LOCK(hcrc);
00311
00312   /* Change CRC peripheral state */
00313   hcrc->State = HAL_CRC_STATE_BUSY;
00314
00315   switch (hcrc->InputDataFormat)
00316   {
00317     case CRC_INPUTDATA_FORMAT_WORDS:
00318       /* Enter Data to the CRC calculator */
00319       for(index = 0U; index < BufferLength; index++)
00320       {
00321         hcrc->Instance->DR = pBuffer[index];
00322       }
00323       temp = hcrc->Instance->DR;
00324       break;
00325
00326     case CRC_INPUTDATA_FORMAT_BYTES:
00327       temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
00328       break;
00329
00330     case CRC_INPUTDATA_FORMAT_HALFWORDS:
00331       temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
00332       break;
00333
00334     default:
00335       break;
00336   }
00337
00338   /* Change CRC peripheral state */
00339   hcrc->State = HAL_CRC_STATE_READY;
00340
00341   /* Process unlocked */
00342   __HAL_UNLOCK(hcrc);
00343
00344   /* Return the CRC computed value */
00345   return temp;
00346 }
00347
00348
00349 /**
00350   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00351   *         starting with hcrc->Instance->INIT as initialization value.
00352   * @param  hcrc CRC handle
00353   * @param  pBuffer pointer to the input data buffer, exact input data format is
00354   *         provided by hcrc->InputDataFormat.
00355   * @param  BufferLength input data buffer length (number of bytes if pBuffer
00356   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
00357   *         number of words if pBuffer type is * uint32_t).
00358   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
00359   *        Input buffer pointers with other types simply need to be cast in uint32_t
00360   *        and the API will internally adjust its input data processing based on the
00361   *        handle field hcrc->InputDataFormat.
00362   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00363   */
00364 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00365 {
00366   uint32_t index = 0U; /* CRC input data buffer index */
00367   uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
00368
00369   /* Process locked */
00370   __HAL_LOCK(hcrc);
00371
00372   /* Change CRC peripheral state */
00373   hcrc->State = HAL_CRC_STATE_BUSY;
00374
00375   /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
00376   *  written in hcrc->Instance->DR) */
00377   __HAL_CRC_DR_RESET(hcrc);
00378
00379   switch (hcrc->InputDataFormat)
00380   {
00381     case CRC_INPUTDATA_FORMAT_WORDS:
00382       /* Enter 32-bit input data to the CRC calculator */
00383       for(index = 0U; index < BufferLength; index++)
00384       {
00385         hcrc->Instance->DR = pBuffer[index];
00386       }
00387       temp = hcrc->Instance->DR;
00388       break;
00389
00390     case CRC_INPUTDATA_FORMAT_BYTES:
00391       /* Specific 8-bit input data handling  */
00392       temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
00393       break;
00394
00395     case CRC_INPUTDATA_FORMAT_HALFWORDS:
00396       /* Specific 16-bit input data handling  */
00397       temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
00398       break;
00399
00400     default:
00401       break;
00402   }
00403
00404   /* Change CRC peripheral state */
00405   hcrc->State = HAL_CRC_STATE_READY;
00406
00407   /* Process unlocked */
00408   __HAL_UNLOCK(hcrc);
00409
00410   /* Return the CRC computed value */
00411   return temp;
00412 }
00413
00414 /**
00415   * @}
00416   */
00417
00418 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
00419  *  @brief    Peripheral State functions.
00420  *
00421 @verbatim
00422  ===============================================================================
00423                       ##### Peripheral State functions #####
00424  ===============================================================================
00425     [..]
00426     This subsection permits to get in run-time the status of the peripheral.
00427
00428 @endverbatim
00429   * @{
00430   */
00431
00432 /**
00433   * @brief  Return the CRC handle state.
00434   * @param  hcrc CRC handle
00435   * @retval HAL state
00436   */
00437 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
00438 {
00439   /* Return CRC handle state */
00440   return hcrc->State;
00441 }
00442
00443 /**
00444   * @}
00445   */
00446
00447 /**
00448   * @}
00449   */
00450
00451 /** @defgroup CRC_Private_Functions CRC Private Functions
00452   * @{
00453   */
00454
00455 /**
00456   * @brief  Enter 8-bit input data to the CRC calculator.
00457   *         Specific data handling to optimize processing time.
00458   * @param  hcrc CRC handle
00459   * @param  pBuffer pointer to the input data buffer
00460   * @param  BufferLength input data buffer length
00461   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00462   */
00463 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
00464 {
00465   uint32_t i = 0U; /* input data buffer index */
00466
00467    /* Processing time optimization: 4 bytes are entered in a row with a single word write,
00468     * last bytes must be carefully fed to the CRC calculator to ensure a correct type
00469     * handling by the IP */
00470    for(i = 0U; i < (BufferLength/4U); i++)
00471    {
00472       hcrc->Instance->DR = ((uint32_t)pBuffer[4U*i]<<24U) | ((uint32_t)pBuffer[4U*i+1]<<16U) | ((uint32_t)pBuffer[4U*i+2]<<8U) | (uint32_t)pBuffer[4U*i+3];
00473    }
00474    /* last bytes specific handling */
00475    if ((BufferLength%4U) != 0U)
00476    {
00477      if  (BufferLength%4U == 1U)
00478      {
00479        *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i];
00480      }
00481      if  (BufferLength%4U == 2U)
00482      {
00483        *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
00484      }
00485      if  (BufferLength%4U == 3U)
00486      {
00487        *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
00488        *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
00489      }
00490    }
00491
00492   /* Return the CRC computed value */
00493   return hcrc->Instance->DR;
00494 }
00495
00496
00497
00498 /**
00499   * @brief  Enter 16-bit input data to the CRC calculator.
00500   *         Specific data handling to optimize processing time.
00501   * @param  hcrc CRC handle
00502   * @param  pBuffer pointer to the input data buffer
00503   * @param  BufferLength input data buffer length
00504   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00505   */
00506 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
00507 {
00508   uint32_t i = 0U;  /* input data buffer index */
00509
00510   /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
00511    * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
00512    * a correct type handling by the IP */
00513   for(i = 0U; i < (BufferLength/2U); i++)
00514   {
00515     hcrc->Instance->DR = ((uint32_t)pBuffer[2U*i]<<16U) | (uint32_t)pBuffer[2U*i+1];
00516   }
00517   if ((BufferLength%2U) != 0U)
00518   {
00519        *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i];
00520   }
00521
00522   /* Return the CRC computed value */
00523   return hcrc->Instance->DR;
00524 }
00525
00526 /**
00527   * @}
00528   */
00529
00530 #endif /* HAL_CRC_MODULE_ENABLED */
00531 /**
00532   * @}
00533   */
00534
00535 /**
00536   * @}
00537   */
00538
00539 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_crc.h Source File

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stm32f3xx_hal_crc.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_crc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_CRC_H
00038 #define __STM32F3xx_HAL_CRC_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup CRC CRC
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /** @defgroup CRC_Exported_Types CRC Exported Types
00057   * @{
00058   */
00059 /**
00060   * @brief  CRC HAL State Structure definition
00061   */
00062 typedef enum
00063 {
00064   HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
00065   HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
00066   HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
00067   HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
00068   HAL_CRC_STATE_ERROR     = 0x04   /*!< CRC error state                     */
00069 }HAL_CRC_StateTypeDef;
00070
00071
00072 /**
00073   * @brief CRC Init Structure definition
00074   */
00075 typedef struct
00076 {
00077   uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
00078                                             If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
00079                                             X^32U + X^26U + X^23U + X^22U + X^16U + X^12U + X^11U + X^10U +X^8U + X^7U + X^5U + X^4U + X^2U+ X +1.
00080                                             In that case, there is no need to set GeneratingPolynomial field.
00081                                             If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
00082
00083   uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
00084                                            If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
00085                                            0xFFFFFFFF value. In that case, there is no need to set InitValue field.
00086                                            If otherwise set to DEFAULT_INIT_VALUE_DISABLE,  InitValue field must be set. */
00087
00088   uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial as a 7U, 8U, 16 or 32-bit long value for a polynomial degree
00089                                            respectively equal to 7U, 8U, 16 or 32. This field is written in normal representation,
00090                                            e.g., for a polynomial of degree 7U, X^7U + X^6U + X^5U + X^2U + 1 is written 0x65.
00091                                            No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE.   */
00092
00093   uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
00094                                            Value can be either one of
00095                                            @arg CRC_POLYLENGTH_32B                  (32-bit CRC),
00096                                            @arg CRC_POLYLENGTH_16B                  (16-bit CRC),
00097                                            @arg CRC_POLYLENGTH_8B                   (8-bit CRC),
00098                                            @arg CRC_POLYLENGTH_7B                   (7-bit CRC). */
00099
00100   uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
00101                                            is set to DEFAULT_INIT_VALUE_ENABLE.   */
00102
00103   uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
00104                                            Can be either one of the following values
00105                                            @arg CRC_INPUTDATA_INVERSION_NONE,      no input data inversion
00106                                            @arg CRC_INPUTDATA_INVERSION_BYTE,      byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
00107                                            @arg CRC_INPUTDATA_INVERSION_HALFWORD,  halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
00108                                            @arg CRC_INPUTDATA_INVERSION_WORD,      word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458U */
00109
00110   uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
00111                                             Can be either
00112                                             @arg CRC_OUTPUTDATA_INVERSION_DISABLE:   no CRC inversion,
00113                                             @arg CRC_OUTPUTDATA_INVERSION_ENABLE:    CRC 0x11223344 is converted into 0x22CC4488U */
00114 }CRC_InitTypeDef;
00115
00116
00117 /**
00118   * @brief  CRC Handle Structure definition
00119   */
00120 typedef struct
00121 {
00122   CRC_TypeDef                 *Instance;   /*!< Register base address        */
00123
00124   CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */
00125
00126   HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
00127
00128   __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
00129
00130   uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
00131                                             Can be either
00132                                             @arg CRC_INPUTDATA_FORMAT_BYTES,       input data is a stream of bytes (8-bit data)
00133                                             @arg CRC_INPUTDATA_FORMAT_HALFWORDS,   input data is a stream of half-words (16-bit data)
00134                                             @arg CRC_INPUTDATA_FORMAT_WORDS,       input data is a stream of words (32-bit data)
00135
00136                                            Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
00137                                            must occur if InputBufferFormat is not one of the three values listed above  */
00138 }CRC_HandleTypeDef;
00139 /**
00140   * @}
00141   */
00142
00143 /* Exported constants --------------------------------------------------------*/
00144 /** @defgroup CRC_Exported_Constants CRC Exported Constants
00145   * @{
00146   */
00147 /** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial
00148   * @{
00149   */
00150 #define DEFAULT_CRC32_POLY      0x04C11DB7   /*!<  X^32U + X^26U + X^23U + X^22U + X^16U + X^12U + X^11U + X^10U +X^8U + X^7U + X^5U + X^4U + X^2U+ X +1U */
00151
00152 /**
00153   * @}
00154   */
00155
00156 /** @defgroup CRC_Default_InitValue    Default CRC computation initialization value
00157   * @{
00158   */
00159 #define DEFAULT_CRC_INITVALUE   0xFFFFFFFFU   /*!< Initial CRC default value */
00160
00161 /**
00162   * @}
00163   */
00164
00165 /** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used
00166   * @{
00167   */
00168 #define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00U)   /*!< Enable default generating polynomial 0x04C11DB7  */
00169 #define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01U)   /*!< Disable default generating polynomial 0x04C11DB7U */
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used
00175   * @{
00176   */
00177 #define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00U)   /*!< Enable initial CRC default value  */
00178 #define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01U)   /*!< Disable initial CRC default value */
00179 /**
00180   * @}
00181   */
00182
00183 /** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
00184   * @{
00185   */
00186 #define CRC_POLYLENGTH_32B                  (0x00000000U)          /*!< Resort to a 32-bit long generating polynomial */
00187 #define CRC_POLYLENGTH_16B                  ((uint32_t)CRC_CR_POLYSIZE_0)   /*!< Resort to a 16-bit long generating polynomial */
00188 #define CRC_POLYLENGTH_8B                   ((uint32_t)CRC_CR_POLYSIZE_1)   /*!< Resort to a 8-bit long generating polynomial  */
00189 #define CRC_POLYLENGTH_7B                   ((uint32_t)CRC_CR_POLYSIZE)     /*!< Resort to a 7-bit long generating polynomial  */
00190 /**
00191   * @}
00192   */
00193
00194 /** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
00195   * @{
00196   */
00197 #define HAL_CRC_LENGTH_32B     32     /*!< 32-bit long CRC */
00198 #define HAL_CRC_LENGTH_16B     16     /*!< 16-bit long CRC */
00199 #define HAL_CRC_LENGTH_8B       8     /*!< 8-bit long CRC  */
00200 #define HAL_CRC_LENGTH_7B       7     /*!< 7-bit long CRC  */
00201
00202 /**
00203   * @}
00204   */
00205
00206 /** @defgroup CRC_Input_Buffer_Format Input Buffer Format
00207   * @{
00208   */
00209 /* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
00210  * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
00211  * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
00212  * the CRC APIs to provide a correct result */
00213 #define CRC_INPUTDATA_FORMAT_UNDEFINED             (0x00000000U)   /*!< Undefined input data format    */
00214 #define CRC_INPUTDATA_FORMAT_BYTES                 (0x00000001U)   /*!< Input data in byte format      */
00215 #define CRC_INPUTDATA_FORMAT_HALFWORDS             (0x00000002U)   /*!< Input data in half-word format */
00216 #define CRC_INPUTDATA_FORMAT_WORDS                 (0x00000003U)   /*!< Input data in word format      */
00217 /**
00218   * @}
00219   */
00220
00221 /**
00222   * @}
00223   */
00224
00225 /* Exported macros -----------------------------------------------------------*/
00226
00227 /** @defgroup CRC_Exported_Macros CRC Exported Macros
00228   * @{
00229   */
00230
00231 /** @brief Reset CRC handle state.
00232   * @param  __HANDLE__ CRC handle.
00233   * @retval None
00234   */
00235 #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
00236
00237 /**
00238   * @brief  Reset CRC Data Register.
00239   * @param  __HANDLE__ CRC handle
00240   * @retval None
00241   */
00242 #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
00243
00244 /**
00245   * @brief  Set CRC INIT non-default value
00246 * @param  __HANDLE__ CRC handle
00247   * @param  __INIT__ 32-bit initial value
00248   * @retval None
00249   */
00250 #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
00251
00252 /**
00253   * @brief Store a 8-bit data in the Independent Data(ID) register.
00254   * @param __HANDLE__ CRC handle
00255   * @param __VALUE__ 8-bit value to be stored in the ID register
00256   * @retval None
00257   */
00258 #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
00259
00260 /**
00261   * @brief Return the 8-bit data stored in the Independent Data(ID) register.
00262   * @param __HANDLE__ CRC handle
00263   * @retval 8-bit value of the ID register
00264   */
00265 #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
00266 /**
00267   * @}
00268   */
00269
00270
00271 /* Private macros --------------------------------------------------------*/
00272 /** @addtogroup  CRC_Private_Macros   CRC Private Macros
00273   * @{
00274   */
00275
00276 #define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
00277                                         ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
00278
00279
00280 #define IS_DEFAULT_INIT_VALUE(VALUE)  (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
00281                                        ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
00282
00283 #define IS_CRC_POL_LENGTH(LENGTH)     (((LENGTH) == CRC_POLYLENGTH_32B) || \
00284                                        ((LENGTH) == CRC_POLYLENGTH_16B) || \
00285                                        ((LENGTH) == CRC_POLYLENGTH_8B)  || \
00286                                        ((LENGTH) == CRC_POLYLENGTH_7B))
00287
00288 #define IS_CRC_INPUTDATA_FORMAT(FORMAT)           (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
00289                                                    ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
00290                                                    ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
00291
00292 /**
00293   * @}
00294   */
00295
00296 /* Include CRC HAL Extended module */
00297 #include "stm32f3xx_hal_crc_ex.h"
00298
00299 /* Exported functions --------------------------------------------------------*/
00300 /** @addtogroup CRC_Exported_Functions CRC Exported Functions
00301   * @{
00302   */
00303
00304 /** @addtogroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
00305  *  @brief    Initialization and Configuration functions.
00306  * @{
00307  */
00308 /* Initialization and de-initialization functions  ****************************/
00309 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
00310 HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
00311 void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
00312 void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
00313 /**
00314   * @}
00315   */
00316
00317 /** @addtogroup CRC_Exported_Functions_Group2 Peripheral Control functions
00318  *  @brief    management functions.
00319  * @{
00320  */
00321 /* Peripheral Control functions ***********************************************/
00322 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00323 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00324 /**
00325   * @}
00326   */
00327
00328 /** @addtogroup CRC_Exported_Functions_Group3 Peripheral State functions
00329  *  @brief    Peripheral State functions.
00330  * @{
00331  */
00332 /* Peripheral State and Error functions ***************************************/
00333 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
00334 /**
00335   * @}
00336   */
00337
00338 /**
00339   * @}
00340   */
00341
00342   /** @defgroup HAL_CRC_Alias_Exported_Functions CRC aliases for Exported Functions
00343  * @{
00344  */
00345 /* Aliases for inter STM32 series compatibility */
00346 #define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse
00347 #define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse
00348 /**
00349   * @}
00350   */
00351
00352 /**
00353   * @}
00354   */
00355
00356 /**
00357   * @}
00358   */
00359
00360 #ifdef __cplusplus
00361 }
00362 #endif
00363
00364 #endif /* __STM32F3xx_HAL_CRC_H */
00365
00366 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_crc_ex.c Source File

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stm32f3xx_hal_crc_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_crc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended CRC HAL module driver.
00006   *          This file provides firmware functions to manage the extended
00007   *          functionalities of the CRC peripheral.
00008   *
00009   @verbatim
00010 ================================================================================
00011             ##### How to use this driver #####
00012 ================================================================================
00013     [..]
00014          (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
00015          (+) Configure Input or Output data inversion
00016
00017   @endverbatim
00018   ******************************************************************************
00019   * @attention
00020   *
00021   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00022   *
00023   * Redistribution and use in source and binary forms, with or without modification,
00024   * are permitted provided that the following conditions are met:
00025   *   1. Redistributions of source code must retain the above copyright notice,
00026   *      this list of conditions and the following disclaimer.
00027   *   2. Redistributions in binary form must reproduce the above copyright notice,
00028   *      this list of conditions and the following disclaimer in the documentation
00029   *      and/or other materials provided with the distribution.
00030   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00031   *      may be used to endorse or promote products derived from this software
00032   *      without specific prior written permission.
00033   *
00034   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00035   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00036   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00037   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00038   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00039   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00040   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00041   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00042   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00043   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00044   *
00045   ******************************************************************************
00046   */
00047
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32f3xx_hal.h"
00050
00051 /** @addtogroup STM32F3xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @defgroup CRCEx CRCEx
00056   * @brief CRC Extended HAL module driver
00057   * @{
00058   */
00059
00060 #ifdef HAL_CRC_MODULE_ENABLED
00061
00062 /* Private typedef -----------------------------------------------------------*/
00063 /* Private define ------------------------------------------------------------*/
00064 /* Private macro -------------------------------------------------------------*/
00065 /* Private variables ---------------------------------------------------------*/
00066 /* Private function prototypes -----------------------------------------------*/
00067 /* Exported functions --------------------------------------------------------*/
00068
00069 /** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
00070   * @{
00071   */
00072
00073 /** @defgroup CRCEx_Exported_Functions_Group1 CRC Extended Initialization and de-initialization functions
00074   * @brief    CRC Extended Initialization and Configuration functions.
00075   *
00076 @verbatim
00077  ===============================================================================
00078             ##### Extended configuration functions #####
00079  ===============================================================================
00080     [..]  This section provides functions allowing to:
00081       (+) Configure the generating polynomial
00082       (+) Configure the input data inversion
00083       (+) Configure the output data inversion
00084
00085 @endverbatim
00086   * @{
00087   */
00088
00089
00090 /**
00091   * @brief  Initialize the CRC polynomial if different from default one.
00092   * @param  hcrc CRC handle
00093   * @param  Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
00094   *         This parameter is written in normal representation, e.g.
00095   *         @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00096   *         @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
00097   * @param  PolyLength CRC polynomial length.
00098   *         This parameter can be one of the following values:
00099   *          @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
00100   *          @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
00101   *          @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)
00102   *          @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)
00103   * @retval HAL status
00104   */
00105 HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
00106 {
00107   uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
00108
00109   /* Check the parameters */
00110   assert_param(IS_CRC_POL_LENGTH(PolyLength));
00111
00112   /* check polynomial definition vs polynomial size:
00113    * polynomial length must be aligned with polynomial
00114    * definition. HAL_ERROR is reported if Pol degree is
00115    * larger than that indicated by PolyLength.
00116    * Look for MSB position: msb will contain the degree of
00117    *  the second to the largest polynomial member. E.g., for
00118    *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
00119   while (((Pol & (1U << msb)) == 0U) && (msb-- > 0U)){}
00120
00121   switch (PolyLength)
00122   {
00123     case CRC_POLYLENGTH_7B:
00124       if (msb >= HAL_CRC_LENGTH_7B)
00125       {
00126         return  HAL_ERROR;
00127       }
00128       break;
00129     case CRC_POLYLENGTH_8B:
00130       if (msb >= HAL_CRC_LENGTH_8B)
00131       {
00132         return  HAL_ERROR;
00133       }
00134       break;
00135     case CRC_POLYLENGTH_16B:
00136       if (msb >= HAL_CRC_LENGTH_16B)
00137       {
00138         return  HAL_ERROR;
00139       }
00140       break;
00141     case CRC_POLYLENGTH_32B:
00142       /* no polynomial definition vs. polynomial length issue possible */
00143       break;
00144     default:
00145       break;
00146   }
00147
00148   /* set generating polynomial */
00149   WRITE_REG(hcrc->Instance->POL, Pol);
00150
00151   /* set generating polynomial size */
00152   MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
00153
00154   /* Return function status */
00155   return HAL_OK;
00156 }
00157
00158 /**
00159   * @brief  Set the Reverse Input data mode.
00160   * @param  hcrc CRC handle
00161   * @param  InputReverseMode Input Data inversion mode.
00162   *         This parameter can be one of the following values:
00163   *          @arg CRC_INPUTDATA_NOINVERSION: no change in bit order (default value)
00164   *          @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
00165   *          @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal
00166   *          @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal
00167   * @retval HAL status
00168   */
00169 HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
00170 {
00171   /* Check the parameters */
00172   assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
00173
00174   /* Change CRC peripheral state */
00175   hcrc->State = HAL_CRC_STATE_BUSY;
00176
00177   /* set input data inversion mode */
00178   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
00179   /* Change CRC peripheral state */
00180   hcrc->State = HAL_CRC_STATE_READY;
00181
00182   /* Return function status */
00183   return HAL_OK;
00184 }
00185
00186 /**
00187   * @brief  Set the Reverse Output data mode.
00188   * @param  hcrc CRC handle
00189   * @param  OutputReverseMode Output Data inversion mode.
00190   *         This parameter can be one of the following values:
00191   *          @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
00192   *          @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
00193   * @retval HAL status
00194   */
00195 HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
00196 {
00197   /* Check the parameters */
00198   assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
00199
00200   /* Change CRC peripheral state */
00201   hcrc->State = HAL_CRC_STATE_BUSY;
00202
00203   /* set output data inversion mode */
00204   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
00205
00206   /* Change CRC peripheral state */
00207   hcrc->State = HAL_CRC_STATE_READY;
00208
00209   /* Return function status */
00210   return HAL_OK;
00211 }
00212
00213
00214
00215
00216 /**
00217   * @}
00218   */
00219
00220
00221 /**
00222   * @}
00223   */
00224
00225
00226 #endif /* HAL_CRC_MODULE_ENABLED */
00227 /**
00228   * @}
00229   */
00230
00231 /**
00232   * @}
00233   */
00234
00235 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_crc_ex.h Source File

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stm32f3xx_hal_crc_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_crc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRC HAL extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_CRC_EX_H
00038 #define __STM32F3xx_HAL_CRC_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup CRCEx CRCEx
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /* Exported constants --------------------------------------------------------*/
00057 /** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
00058   * @{
00059   */
00060
00061 /** @defgroup CRCEx_Input_Data_Inversion CRC Extended Input Data Inversion Modes
00062   * @{
00063   */
00064 #define CRC_INPUTDATA_INVERSION_NONE              (0x00000000U)      /*!< No input data inversion            */
00065 #define CRC_INPUTDATA_INVERSION_BYTE              ((uint32_t)CRC_CR_REV_IN_0) /*!< Byte-wise input data inversion     */
00066 #define CRC_INPUTDATA_INVERSION_HALFWORD          ((uint32_t)CRC_CR_REV_IN_1) /*!< HalfWord-wise input data inversion */
00067 #define CRC_INPUTDATA_INVERSION_WORD              ((uint32_t)CRC_CR_REV_IN)   /*!< Word-wise input data inversion     */
00068 /**
00069   * @}
00070   */
00071
00072 /** @defgroup CRCEx_Output_Data_Inversion CRC Extended Output Data Inversion Modes
00073   * @{
00074   */
00075 #define CRC_OUTPUTDATA_INVERSION_DISABLE         (0x00000000U)      /*!< No output data inversion       */
00076 #define CRC_OUTPUTDATA_INVERSION_ENABLE          ((uint32_t)CRC_CR_REV_OUT)  /*!< Bit-wise output data inversion */
00077 /**
00078   * @}
00079   */
00080
00081 /**
00082   * @}
00083   */
00084
00085 /* Exported macro ------------------------------------------------------------*/
00086
00087 /** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
00088   * @{
00089   */
00090
00091 /**
00092   * @brief  Set CRC output reversal
00093   * @param  __HANDLE__ CRC handle
00094   * @retval None.
00095   */
00096 #define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
00097
00098 /**
00099   * @brief  Unset CRC output reversal
00100   * @param  __HANDLE__ CRC handle
00101   * @retval None.
00102   */
00103 #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
00104
00105 /**
00106   * @brief  Set CRC non-default polynomial
00107   * @param  __HANDLE__ CRC handle
00108   * @param  __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
00109   * @retval None.
00110   */
00111 #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
00112
00113 /**
00114   * @}
00115   */
00116
00117 /* Private macros --------------------------------------------------------*/
00118 /** @addtogroup  CRCEx_Private_Macros   CRCEx Private Macros
00119   * @{
00120   */
00121
00122 #define IS_CRC_INPUTDATA_INVERSION_MODE(MODE)     (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
00123                                                    ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
00124                                                    ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
00125                                                    ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
00126
00127
00128 #define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)    (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
00129                                                    ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
00130
00131 /**
00132   * @}
00133   */
00134
00135 /* Exported functions --------------------------------------------------------*/
00136 /** @addtogroup CRCEx_Exported_Functions CRC Extended Exported Functions
00137   * @{
00138   */
00139
00140 /** @addtogroup CRCEx_Exported_Functions_Group1 CRC Extended Initialization and de-initialization functions
00141   * @brief    Extended Initialization and Configuration functions.
00142   * @{
00143   */
00144 /* Initialization and de-initialization functions  ****************************/
00145 HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
00146 HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
00147 HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
00148 /**
00149   * @}
00150   */
00151
00152 /* Peripheral Control functions ***********************************************/
00153 /* Peripheral State and Error functions ***************************************/
00154
00155 /**
00156   * @}
00157   */
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 #ifdef __cplusplus
00168 }
00169 #endif
00170
00171 #endif /* __STM32F3xx_HAL_CRC_EX_H */
00172
00173 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_dac.c Source File

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stm32f3xx_hal_dac.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_dac.c
00004   * @author  MCD Application Team
00005   * @brief   DAC HAL module driver.
00006   *         This file provides firmware functions to manage the following
00007   *         functionalities of the Digital to Analog Converter (DAC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State and Errors functions
00012   *
00013   *
00014  @verbatim
00015   ==============================================================================
00016                       ##### DAC Peripheral features #####
00017   ==============================================================================
00018     [..]
00019       *** DAC Channels ***
00020       ====================
00021     [..]
00022     The device integrates up to 3 12-bit Digital Analog Converters that can
00023     be used independently or simultaneously (dual mode):
00024       (#) DAC1 channel1 with DAC1_OUT1 (PA4) as output
00025       (#) DAC1 channel2 with DAC1_OUT2 (PA5) as output
00026           (for STM32F3 devices having 2 channels on DAC1)
00027       (#) DAC2 channel1 with DAC2_OUT1 (PA6) as output
00028           (for STM32F3 devices having 2 DAC)
00029
00030       *** DAC Triggers ***
00031       ====================
00032     [..]
00033     Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
00034     and DAC1_OUT1/DAC1_OUT2/DAC2_OUT1 is available once writing to DHRx register.
00035     [..]
00036     Digital to Analog conversion can be triggered by:
00037       (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
00038           The used pin (GPIOx_PIN_9) must be configured in input mode.
00039
00040       (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
00041           (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
00042
00043       (#) Software using DAC_TRIGGER_SOFTWARE
00044
00045       *** DAC Buffer mode feature ***
00046       ===============================
00047       [..]
00048       Each DAC channel integrates an output buffer that can be used to
00049       reduce the output impedance, and to drive external loads directly
00050       without having to add an external operational amplifier.
00051       To enable, the output buffer use
00052       sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
00053       Or
00054       An output switch
00055          (in STM32F303x4, STM32F303x6, STM32F303x8
00056              c, STM32F334x6, STM32F334x8
00057            & STM32F334xx).
00058       To enable, the output switch
00059       sConfig.DAC_OutputSwitch = DAC_OUTPUTSWITCH_ENABLE;
00060       [..]
00061       (@) Refer to the device datasheet for more details about output
00062           impedance value with and without output buffer.
00063
00064       *** GPIO configurations guidelines ***
00065       =====================
00066       [..]
00067       When a DAC channel is used (ex channel1 on PA4) and the other is not
00068       (ex channel2 on PA5 is configured in Analog and disabled).
00069       Channel1 may disturb channel2 as coupling effect.
00070       Note that there is no coupling on channel2 as soon as channel2 is turned on.
00071       Coupling on adjacent channel could be avoided as follows:
00072       when unused PA5 is configured as INPUT PULL-UP or DOWN.
00073       PA5 is configured in ANALOG just before it is turned on.
00074
00075
00076        *** DAC wave generation feature ***
00077        ===================================
00078        [..]
00079        Both DAC channels of DAC1 can be used to generate
00080        note that wave generation is not available in DAC2.
00081          (#) Noise wave
00082          (#) Triangle wave
00083
00084        Wave generation is NOT available in DAC2.
00085
00086        *** DAC data format ***
00087        =======================
00088        [..]
00089        The DAC data format can be:
00090          (#) 8-bit right alignment using DAC_ALIGN_8B_R
00091          (#) 12-bit left alignment using DAC_ALIGN_12B_L
00092          (#) 12-bit right alignment using DAC_ALIGN_12B_R
00093
00094        *** DAC data value to voltage correspondance ***
00095        ================================================
00096        [..]
00097        The analog output voltage on each DAC channel pin is determined
00098        by the following equation:
00099        [..]
00100        DAC_OUTx = VREF+ * DOR / 4095
00101        (+) with  DOR is the Data Output Register
00102        [..]
00103           VEF+ is the input voltage reference (refer to the device datasheet)
00104        [..]
00105         e.g. To set DAC_OUT1 to 0.7V, use
00106        (+)  Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3U * 868U) / 4095U = 0.7V
00107
00108        *** DMA requests  ***
00109        =====================
00110        [..]
00111        A DMA1 or DMA2 request can be generated when an external trigger
00112        (but not a software trigger) occurs if DMA1 or DMA2 requests are
00113        enabled using HAL_DAC_Start_DMA().
00114        [..]
00115        DMA1 requests are mapped as following:
00116          (#) DAC1 channel1: mapped either on
00117          (++) DMA1 channel3
00118          (++) or DMA2 channel3 (for STM32F3 devices having 2 DMA)
00119              which must be already configured
00120          (#) DAC1 channel2:
00121              (for STM32F3 devices having 2 channels on DAC1)
00122              mapped either on
00123          (++) DMA1 channel4
00124          (++) or DMA2 channel4 (for STM32F3 devices having 2 DMA)
00125              which must be already configured
00126
00127          (#) DAC2 channel1: mapped either on
00128              (for STM32F3 devices having 2 DAC)
00129          (++) DMA1 channel4
00130          (++) or DMA2 channel4 (for STM32F3 devices having 2 DMA)
00131              which must be already configured
00132
00133
00134        (@) For Dual mode and specific signal (Triangle and noise) generation please
00135        refer to Extended Features Driver description
00136
00137                       ##### How to use this driver #####
00138   ==============================================================================
00139     [..]
00140       (+) DAC APB clock must be enabled to get write access to DAC
00141           registers using HAL_DAC_Init()
00142       (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
00143       (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
00144       (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions
00145
00146      *** Polling mode IO operation ***
00147      =================================
00148      [..]
00149        (+) Start the DAC peripheral using HAL_DAC_Start()
00150        (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
00151        (+) Stop the DAC peripheral using HAL_DAC_Stop()
00152
00153      *** DMA mode IO operation ***
00154      ==============================
00155      [..]
00156        (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
00157            of data to be transferred at each end of conversion
00158        (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00159            function is executed and user can add his own code by customization of function pointer
00160            HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00161        (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00162            function is executed and user can add his own code by customization of function pointer
00163            HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00164        (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
00165             add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
00166        (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
00167            HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
00168            function is executed and user can add his own code by customization of function pointer
00169            HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
00170            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
00171        (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
00172
00173      *** DAC HAL driver macros list ***
00174      =============================================
00175      [..]
00176        Below the list of most used macros in DAC HAL driver.
00177
00178       (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
00179       (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
00180       (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
00181       (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
00182
00183      [..]
00184       (@) You can refer to the DAC HAL driver header file for more useful macros
00185
00186  @endverbatim
00187   ******************************************************************************
00188   * @attention
00189   *
00190   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00191   *
00192   * Redistribution and use in source and binary forms, with or without modification,
00193   * are permitted provided that the following conditions are met:
00194   *   1. Redistributions of source code must retain the above copyright notice,
00195   *      this list of conditions and the following disclaimer.
00196   *   2. Redistributions in binary form must reproduce the above copyright notice,
00197   *      this list of conditions and the following disclaimer in the documentation
00198   *      and/or other materials provided with the distribution.
00199   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00200   *      may be used to endorse or promote products derived from this software
00201   *      without specific prior written permission.
00202   *
00203   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00204   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00205   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00206   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00207   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00208   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00209   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00210   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00211   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00212   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00213   *
00214   ******************************************************************************
00215   */
00216
00217
00218 /* Includes ------------------------------------------------------------------*/
00219 #include "stm32f3xx_hal.h"
00220
00221 /** @addtogroup STM32F3xx_HAL_Driver
00222   * @{
00223   */
00224
00225 /** @defgroup DAC DAC
00226   * @brief DAC HAL module driver
00227   * @{
00228   */
00229
00230 #ifdef HAL_DAC_MODULE_ENABLED
00231
00232 /* Private typedef -----------------------------------------------------------*/
00233 /* Private define ------------------------------------------------------------*/
00234 /* Private macro -------------------------------------------------------------*/
00235 /** @defgroup DAC_Private_Macros DAC Private Macros
00236   * @{
00237   */
00238 /**
00239   * @}
00240   */
00241
00242 /* Private variables ---------------------------------------------------------*/
00243 /* Private function prototypes -----------------------------------------------*/
00244 /** @defgroup DAC_Private_Functions DAC Private Functions
00245   * @{
00246   */
00247 /**
00248   * @}
00249   */
00250
00251 /* Exported functions -------------------------------------------------------*/
00252
00253 /** @defgroup DAC_Exported_Functions DAC Exported Functions
00254   * @{
00255   */
00256
00257 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
00258  *  @brief    Initialization and Configuration functions
00259  *
00260 @verbatim
00261   ==============================================================================
00262               ##### Initialization and de-initialization functions #####
00263   ==============================================================================
00264     [..]  This section provides functions allowing to:
00265       (+) Initialize and configure the DAC.
00266       (+) De-initialize the DAC.
00267
00268 @endverbatim
00269   * @{
00270   */
00271
00272 /**
00273   * @brief  Initialize the DAC peripheral according to the specified parameters
00274   *         in the DAC_InitStruct and initialize the associated handle.
00275   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00276   *         the configuration information for the specified DAC.
00277   * @retval HAL status
00278   */
00279 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
00280 {
00281   /* Check DAC handle */
00282   if(hdac == NULL)
00283   {
00284      return HAL_ERROR;
00285   }
00286   /* Check the parameters */
00287   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00288
00289   if(hdac->State == HAL_DAC_STATE_RESET)
00290   {
00291     /* Allocate lock resource and initialize it */
00292     hdac->Lock = HAL_UNLOCKED;
00293
00294     /* Init the low level hardware */
00295     HAL_DAC_MspInit(hdac);
00296   }
00297
00298   /* Initialize the DAC state*/
00299   hdac->State = HAL_DAC_STATE_BUSY;
00300
00301   /* Set DAC error code to none */
00302   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00303
00304   /* Initialize the DAC state*/
00305   hdac->State = HAL_DAC_STATE_READY;
00306
00307   /* Return function status */
00308   return HAL_OK;
00309 }
00310
00311 /**
00312   * @brief  Deinitialize the DAC peripheral registers to their default reset values.
00313   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00314   *         the configuration information for the specified DAC.
00315   * @retval HAL status
00316   */
00317 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
00318 {
00319   /* Check DAC handle */
00320   if(hdac == NULL)
00321   {
00322     return HAL_ERROR;
00323   }
00324
00325   /* Check the parameters */
00326   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00327
00328   /* Change DAC state */
00329   hdac->State = HAL_DAC_STATE_BUSY;
00330
00331   /* DeInit the low level hardware */
00332   HAL_DAC_MspDeInit(hdac);
00333
00334   /* Set DAC error code to none */
00335   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00336
00337   /* Change DAC state */
00338   hdac->State = HAL_DAC_STATE_RESET;
00339
00340   /* Release Lock */
00341   __HAL_UNLOCK(hdac);
00342
00343   /* Return function status */
00344   return HAL_OK;
00345 }
00346
00347 /**
00348   * @brief  Initialize the DAC MSP.
00349   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00350   *         the configuration information for the specified DAC.
00351   * @retval None
00352   */
00353 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
00354 {
00355   /* Prevent unused argument(s) compilation warning */
00356   UNUSED(hdac);
00357
00358   /* NOTE : This function should not be modified, when the callback is needed,
00359             the HAL_DAC_MspInit could be implemented in the user file
00360    */
00361 }
00362
00363 /**
00364   * @brief  DeInitialize the DAC MSP.
00365   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00366   *         the configuration information for the specified DAC.
00367   * @retval None
00368   */
00369 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
00370 {
00371   /* Prevent unused argument(s) compilation warning */
00372   UNUSED(hdac);
00373
00374   /* NOTE : This function should not be modified, when the callback is needed,
00375             the HAL_DAC_MspDeInit could be implemented in the user file
00376    */
00377 }
00378
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup DAC_Exported_Functions_Group2 Input and Output operation functions
00384  *  @brief    IO operation functions
00385  *
00386 @verbatim
00387   ==============================================================================
00388              ##### IO operation functions #####
00389   ==============================================================================
00390     [..]  This section provides functions allowing to:
00391       (+) Start conversion.
00392       (+) Stop conversion.
00393       (+) Start conversion and enable DMA transfer.
00394       (+) Stop conversion and disable DMA transfer.
00395       (+) Get result of conversion.
00396       (+) Get result of dual mode conversion.
00397
00398 @endverbatim
00399   * @{
00400   */
00401
00402 /**
00403   * @brief  Enables DAC and starts conversion of channel.
00404   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00405   *         the configuration information for the specified DAC.
00406   * @param  Channel The selected DAC channel.
00407   *          This parameter can be one of the following values:
00408   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
00409   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
00410   *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected
00411   * @retval HAL status
00412   */
00413 __weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
00414 {
00415   /* Prevent unused argument(s) compilation warning */
00416   UNUSED(hdac);
00417   UNUSED(Channel);
00418
00419   /* Note : This function is defined into this file for library reference */
00420   /*        Function content is located into file stm32f3xx_hal_dac_ex.c  */
00421
00422   /* Return function status */
00423   return HAL_ERROR;
00424 }
00425
00426 /**
00427   * @brief  Disables DAC and stop conversion of channel.
00428   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00429   *         the configuration information for the specified DAC.
00430   * @param  Channel The selected DAC channel.
00431   *          This parameter can be one of the following values:
00432   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
00433   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
00434   *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected
00435   * @retval HAL status
00436   */
00437 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
00438 {
00439   /* Check the parameters */
00440   assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
00441
00442   /* Disable the Peripheral */
00443   __HAL_DAC_DISABLE(hdac, Channel);
00444
00445   /* Change DAC state */
00446   hdac->State = HAL_DAC_STATE_READY;
00447
00448   /* Return function status */
00449   return HAL_OK;
00450 }
00451
00452 /**
00453   * @brief  Disables DAC and stop conversion of channel.
00454   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00455   *         the configuration information for the specified DAC.
00456   * @param  Channel The selected DAC channel.
00457   *          This parameter can be one of the following values:
00458   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
00459   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
00460   *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected
00461   * @retval HAL status
00462   */
00463 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
00464 {
00465   HAL_StatusTypeDef status = HAL_OK;
00466
00467   /* Check the parameters */
00468   assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
00469
00470   /* Disable the selected DAC channel DMA request */
00471     hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
00472
00473   /* Disable the Peripheral */
00474   __HAL_DAC_DISABLE(hdac, Channel);
00475
00476   /* Disable the DMA channel */
00477   /* Channel1 is used */
00478   if (Channel == DAC_CHANNEL_1)
00479   {
00480     /* Disable the DMA channel */
00481     status = HAL_DMA_Abort(hdac->DMA_Handle1);
00482
00483     /* Disable the DAC DMA underrun interrupt */
00484     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
00485   }
00486 #if defined(STM32F303xE) || defined(STM32F398xx)                         || \
00487     defined(STM32F303xC) || defined(STM32F358xx)                         || \
00488     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00489     defined(STM32F373xC) || defined(STM32F378xx)
00490
00491   /* For all products including channel 2U */
00492   /* DAC channel 2 is available on top of DAC channel 1U */
00493   else /* Channel2 is used for */
00494   {
00495     /* Disable the DMA channel */
00496     status = HAL_DMA_Abort(hdac->DMA_Handle2);
00497
00498     /* Disable the DAC DMA underrun interrupt */
00499     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
00500   }
00501 #endif
00502
00503   /* Check if DMA Channel effectively disabled */
00504   if (status != HAL_OK)
00505   {
00506     /* Update DAC state machine to error */
00507     hdac->State = HAL_DAC_STATE_ERROR;
00508   }
00509   else
00510   {
00511     /* Change DAC state */
00512     hdac->State = HAL_DAC_STATE_READY;
00513   }
00514
00515   /* Return function status */
00516   return status;
00517 }
00518
00519 /**
00520   * @brief  Returns the last data output value of the selected DAC channel.
00521   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00522   *         the configuration information for the specified DAC.
00523   * @param  Channel The selected DAC channel.
00524   *          This parameter can be one of the following values:
00525   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
00526   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
00527   *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected
00528   * @retval The selected DAC channel data output value.
00529   */
00530 __weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
00531 {
00532   /* Prevent unused argument(s) compilation warning */
00533   UNUSED(hdac);
00534   UNUSED(Channel);
00535
00536   /* Note : This function is defined into this file for library reference */
00537   /*        Function content is located into file stm32f3xx_hal_dac_ex.c  */
00538
00539   /* Return function status */
00540   return HAL_OK;
00541 }
00542
00543 /**
00544   * @brief  Returns the last data output value of the selected DAC channel.
00545   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00546   *         the configuration information for the specified DAC.
00547   * @retval The selected DAC channel data output value.
00548   */
00549 __weak uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
00550 {
00551   /* Prevent unused argument(s) compilation warning */
00552   UNUSED(hdac);
00553
00554   /* Note : This function is defined into this file for library reference */
00555   /*        Function content is located into file stm32f3xx_hal_dac_ex.c  */
00556
00557   /* Return function status */
00558   return HAL_OK;
00559 }
00560
00561 /**
00562   * @}
00563   */
00564
00565 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
00566  *  @brief    Peripheral Control functions
00567  *
00568 @verbatim
00569   ==============================================================================
00570              ##### Peripheral Control functions #####
00571   ==============================================================================
00572     [..]  This section provides functions allowing to:
00573       (+) Configure channels.
00574       (+) Configure Triangle wave generation.
00575       (+) Configure Noise wave generation.
00576       (+) Set the specified data holding register value for DAC channel.
00577       (+) Set the specified data holding register value for Dual DAC channels.
00578
00579 @endverbatim
00580   * @{
00581   */
00582
00583 /**
00584   * @brief  Configures the selected DAC channel.
00585   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00586   *         the configuration information for the specified DAC.
00587   * @param  sConfig DAC configuration structure.
00588   * @param  Channel The selected DAC channel.
00589   *          This parameter can be one of the following values:
00590   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
00591   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
00592   *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected
00593   * @retval HAL status
00594   */
00595
00596 __weak HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
00597 {
00598   /* Prevent unused argument(s) compilation warning */
00599   UNUSED(hdac);
00600   UNUSED(sConfig);
00601   UNUSED(Channel);
00602
00603   /* Return function status */
00604   return HAL_OK;
00605 }
00606
00607 __weak HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
00608 {
00609   /* Prevent unused argument(s) compilation warning */
00610   UNUSED(hdac);
00611   UNUSED(Channel);
00612   UNUSED(Alignment);
00613   UNUSED(Data);
00614
00615   /* Note : This function is defined into this file for library reference */
00616   /*        Function content is located into file stm32f3xx_hal_dac_ex.c  */
00617
00618   /* Return function status */
00619   return HAL_ERROR;
00620 }
00621
00622 __weak HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
00623 {
00624   /* Prevent unused argument(s) compilation warning */
00625   UNUSED(hdac);
00626   UNUSED(Alignment);
00627   UNUSED(Data1);
00628   UNUSED(Data2);
00629
00630   /* Note : This function is defined into this file for library reference */
00631   /*        Function content is located into file stm32f3xx_hal_dac_ex.c  */
00632
00633   /* Return function status */
00634   return HAL_ERROR;
00635 }
00636
00637 /**
00638   * @}
00639   */
00640
00641 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Error functions
00642  *  @brief   DAC Peripheral State and Error functions
00643  *
00644 @verbatim
00645   ==============================================================================
00646             ##### DAC Peripheral State and Error functions #####
00647   ==============================================================================
00648     [..]
00649     This subsection provides functions allowing to
00650       (+) Check the DAC state.
00651       (+) Check the DAC Errors.
00652
00653
00654 @endverbatim
00655   * @{
00656   */
00657
00658 /**
00659   * @brief  return the DAC handle state
00660   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00661   *         the configuration information for the specified DAC.
00662   * @retval HAL state
00663   */
00664 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
00665 {
00666   /* Return DAC handle state */
00667   return hdac->State;
00668 }
00669
00670 /**
00671   * @brief  Return the DAC error code
00672   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00673   *         the configuration information for the specified DAC.
00674   * @retval DAC Error Code
00675   */
00676 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
00677 {
00678   return hdac->ErrorCode;
00679 }
00680
00681 /**
00682   * @}
00683   */
00684
00685 /** @addtogroup DAC_Exported_Functions_Group2 Input and Output operation functions
00686   * @{
00687   */
00688
00689 /**
00690   * @brief  Conversion complete callback in non blocking mode for Channel1
00691   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00692   *         the configuration information for the specified DAC.
00693   * @retval None
00694   */
00695 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
00696 {
00697   /* Prevent unused argument(s) compilation warning */
00698   UNUSED(hdac);
00699
00700   /* NOTE : This function Should not be modified, when the callback is needed,
00701             the HAL_DAC_ConvCpltCallback1 could be implemented in the user file
00702    */
00703 }
00704
00705 /**
00706   * @brief  Conversion half DMA transfer callback in non blocking mode for Channel1
00707   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00708   *         the configuration information for the specified DAC.
00709   * @retval None
00710   */
00711 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
00712 {
00713   /* Prevent unused argument(s) compilation warning */
00714   UNUSED(hdac);
00715
00716   /* NOTE : This function Should not be modified, when the callback is needed,
00717             the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
00718    */
00719 }
00720
00721 /**
00722   * @brief  Error DAC callback for Channel1.
00723   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00724   *         the configuration information for the specified DAC.
00725   * @retval None
00726   */
00727 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
00728 {
00729   /* Prevent unused argument(s) compilation warning */
00730   UNUSED(hdac);
00731
00732   /* NOTE : This function Should not be modified, when the callback is needed,
00733             the HAL_DAC_ErrorCallback could be implemented in the user file
00734    */
00735 }
00736
00737
00738 /**
00739   * @brief  DMA underrun DAC callback for Channel1.
00740   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00741   *         the configuration information for the specified DAC.
00742   * @retval None
00743   */
00744 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
00745 {
00746   /* Prevent unused argument(s) compilation warning */
00747   UNUSED(hdac);
00748
00749   /* NOTE : This function Should not be modified, when the callback is needed,
00750             the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
00751    */
00752 }
00753
00754 /**
00755   * @}
00756   */
00757
00758 /**
00759   * @}
00760   */
00761
00762 #endif /* HAL_DAC_MODULE_ENABLED */
00763
00764 /**
00765   * @}
00766   */
00767
00768 /**
00769   * @}
00770   */
00771
00772 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_dac.h Source File

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stm32f3xx_hal_dac.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_dac.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DAC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_DAC_H
00038 #define __STM32F3xx_HAL_DAC_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup DAC
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056
00057 /** @defgroup DAC_Exported_Types DAC Exported Types
00058   * @{
00059   */
00060
00061 /**
00062   * @brief  HAL State structures definition
00063   */
00064 typedef enum
00065 {
00066   HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */
00067   HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */
00068   HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */
00069   HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
00070   HAL_DAC_STATE_ERROR             = 0x04   /*!< DAC error state                      */
00071
00072 }HAL_DAC_StateTypeDef;
00073
00074 /**
00075   * @brief   DAC Configuration regular Channel structure definition
00076   */
00077 typedef struct
00078 {
00079   uint32_t DAC_Trigger;                 /*!< Specifies the external trigger for the selected DAC channel.
00080                                         This parameter can be a value of @ref DACEx_trigger_selection */
00081
00082   uint32_t DAC_OutputBuffer;            /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
00083                                         This parameter can be a value of @ref DAC_output_buffer
00084                                         For a given DAC channel, is this paramater applies then DAC_OutputSwitch
00085                                         does not apply */
00086
00087   uint32_t DAC_OutputSwitch;            /*!< Specifies whether the DAC channel output switch is enabled or disabled.
00088                                         This parameter can be a value of @ref DAC_OutputSwitch
00089                                         For a given DAC channel, is this paramater applies then DAC_OutputBuffer
00090                                         does not apply */
00091
00092 }DAC_ChannelConfTypeDef;
00093
00094 /**
00095   * @brief  DAC handle Structure definition
00096   */
00097 typedef struct __DAC_HandleTypeDef
00098 {
00099   DAC_TypeDef                 *Instance;      /*!< Register base address             */
00100
00101   __IO HAL_DAC_StateTypeDef   State;          /*!< DAC communication state           */
00102
00103   HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
00104
00105   DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1U */
00106
00107   DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2U */
00108
00109   __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
00110
00111 }DAC_HandleTypeDef;
00112 /**
00113   * @}
00114   */
00115
00116 /* Exported constants --------------------------------------------------------*/
00117 /** @defgroup DAC_Exported_Constants DAC Exported Constants
00118   * @{
00119   */
00120
00121 /** @defgroup DAC_Error_Code DAC Error Code
00122   * @{
00123   */
00124 #define  HAL_DAC_ERROR_NONE              0x00    /*!< No error                          */
00125 #define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01    /*!< DAC channel1 DMA underrun error   */
00126 #define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02    /*!< DAC channel2 DMA underrun error   */
00127 #define  HAL_DAC_ERROR_DMA               0x04    /*!< DMA error                         */
00128 /**
00129   * @}
00130   */
00131
00132 /** @defgroup DAC_lfsrunmask_triangleamplitude DAC lfsrunmask triangleamplitude
00133   * @{
00134   */
00135 #define DAC_LFSRUNMASK_BIT0                (0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
00136 #define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
00137 #define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
00138 #define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
00139 #define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
00140 #define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
00141 #define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
00142 #define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
00143 #define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
00144 #define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
00145 #define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
00146 #define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
00147 #define DAC_TRIANGLEAMPLITUDE_1            (0x00000000U) /*!< Select max triangle amplitude of 1U */
00148 #define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3U */
00149 #define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7U */
00150 #define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15U */
00151 #define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31U */
00152 #define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63U */
00153 #define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127U */
00154 #define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255U */
00155 #define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511U */
00156 #define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023U */
00157 #define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047U */
00158 #define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095U */
00159
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup DAC_output_buffer DAC output buffer
00165   * @{
00166   */
00167 #define DAC_OUTPUTBUFFER_ENABLE            (0x00000000U)
00168 #define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_CR_BOFF1)
00169
00170 /**
00171   * @}
00172   */
00173
00174 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
00175 /** @defgroup DAC_output_switch DAC output switch
00176   * @{
00177   */
00178 #define DAC_OUTPUTSWITCH_DISABLE           (0x00000000U)
00179 #define DAC_OUTPUTSWITCH_ENABLE            ((uint32_t)DAC_CR_OUTEN1)
00180
00181 /**
00182   * @}
00183   */
00184
00185 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00186 /** @defgroup DAC_data_alignement DAC data alignement
00187   * @{
00188   */
00189 #define DAC_ALIGN_12B_R                    (0x00000000U)
00190 #define DAC_ALIGN_12B_L                    (0x00000004U)
00191 #define DAC_ALIGN_8B_R                     (0x00000008U)
00192
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup DAC_flags_definition DAC flags definition
00198   * @{
00199   */
00200 #define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
00201 #define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
00202 /**
00203   * @}
00204   */
00205
00206 /** @defgroup DAC_interrupts_definition DAC interrupts definition
00207   * @{
00208   */
00209 #define DAC_IT_DMAUDR1                   ((uint32_t)DAC_CR_DMAUDRIE1)
00210 #define DAC_IT_DMAUDR2                   ((uint32_t)DAC_CR_DMAUDRIE2)
00211
00212 /**
00213   * @}
00214   */
00215
00216 /**
00217   * @}
00218   */
00219
00220 /* Exported macro ------------------------------------------------------------*/
00221
00222 /** @defgroup DAC_Exported_Macros DAC Exported Macros
00223   * @{
00224   */
00225
00226 /** @brief Reset DAC handle state
00227   * @param  __HANDLE__ specifies the DAC handle.
00228   * @retval None
00229   */
00230 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
00231
00232 /** @brief Enable the DAC channel
00233   * @param  __HANDLE__ specifies the DAC handle.
00234   * @param  __DAC_Channel__ specifies the DAC channel
00235   * @retval None
00236   */
00237 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
00238 ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_Channel__)))
00239
00240 /** @brief Disable the DAC channel
00241   * @param  __HANDLE__ specifies the DAC handle
00242   * @param  __DAC_Channel__ specifies the DAC channel.
00243   * @retval None
00244   */
00245 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
00246 ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
00247
00248 /** @brief Set DHR12R1 alignment
00249   * @param  __ALIGNMENT__ specifies the DAC alignment
00250   * @retval None
00251   */
00252 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__))
00253
00254 /** @brief  Set DHR12R2 alignment
00255   * @param  __ALIGNMENT__ specifies the DAC alignment
00256   * @retval None
00257   */
00258 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__))
00259
00260 /** @brief  Set DHR12RD alignment
00261   * @param  __ALIGNMENT__ specifies the DAC alignment
00262   * @retval None
00263   */
00264 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__))
00265
00266 /** @brief Enable the DAC interrupt
00267   * @param  __HANDLE__ specifies the DAC handle
00268   * @param  __INTERRUPT__ specifies the DAC interrupt.
00269   *          This parameter can be any combination of the following values:
00270   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
00271   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
00272   * @retval None
00273   */
00274 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
00275
00276 /** @brief Disable the DAC interrupt
00277   * @param  __HANDLE__ specifies the DAC handle
00278   * @param  __INTERRUPT__ specifies the DAC interrupt.
00279   *          This parameter can be any combination of the following values:
00280   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
00281   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
00282   * @retval None
00283   */
00284 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
00285
00286 /** @brief  Check whether the specified DAC interrupt source is enabled or not
00287   * @param __HANDLE__ DAC handle
00288   * @param __INTERRUPT__ DAC interrupt source to check
00289   *          This parameter can be any combination of the following values:
00290   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
00291   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
00292   * @retval State of interruption (SET or RESET)
00293   */
00294 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
00295
00296 /** @brief  Get the selected DAC's flag status
00297   * @param  __HANDLE__ specifies the DAC handle.
00298   * @param  __FLAG__ specifies the DAC flag to get.
00299   *          This parameter can be any combination of the following values:
00300   *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
00301   *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
00302   * @retval None
00303   */
00304 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00305
00306 /** @brief  Clear the DAC's flag
00307   * @param  __HANDLE__ specifies the DAC handle.
00308   * @param  __FLAG__ specifies the DAC flag to clear.
00309   *          This parameter can be any combination of the following values:
00310   *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
00311   *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
00312   * @retval None
00313   */
00314 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
00315
00316 /**
00317   * @}
00318   */
00319
00320 /* Private macro -------------------------------------------------------------*/
00321
00322 /** @addtogroup DAC_Private_Macros
00323   * @{
00324   */
00325
00326 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
00327                                                       ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
00328                                                       ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
00329                                                       ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
00330                                                       ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
00331                                                       ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
00332                                                       ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
00333                                                       ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
00334                                                       ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
00335                                                       ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
00336                                                       ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
00337                                                       ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
00338                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
00339                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
00340                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
00341                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
00342                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
00343                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
00344                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
00345                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
00346                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
00347                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
00348                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
00349                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
00350
00351 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
00352                                            ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
00353
00354 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
00355 #define IS_DAC_OUTPUT_SWITCH_STATE(STATE) (((STATE) == DAC_OUTPUTSWITCH_DISABLE) || \
00356                                            ((STATE) == DAC_OUTPUTSWITCH_ENABLE))
00357
00358 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00359 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
00360                              ((ALIGN) == DAC_ALIGN_12B_L) || \
00361                              ((ALIGN) == DAC_ALIGN_8B_R))
00362
00363 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
00364
00365
00366
00367 /**
00368   * @}
00369   */
00370
00371
00372 /* Include DAC HAL Extended module */
00373 #include "stm32f3xx_hal_dac_ex.h"
00374
00375 /* Exported functions --------------------------------------------------------*/
00376
00377 /** @addtogroup DAC_Exported_Functions
00378   * @{
00379   */
00380
00381 /** @addtogroup DAC_Exported_Functions_Group1
00382   * @{
00383   */
00384 /* Initialization and de-initialization functions *****************************/
00385 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
00386 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
00387 void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
00388 void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
00389
00390 /**
00391   * @}
00392   */
00393
00394 /** @addtogroup DAC_Exported_Functions_Group2
00395   * @{
00396   */
00397 /* IO operation functions *****************************************************/
00398 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
00399 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
00400 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
00401 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
00402 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
00403 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
00404
00405 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
00406 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
00407 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
00408 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
00409 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
00410
00411 /**
00412   * @}
00413   */
00414
00415 /** @addtogroup DAC_Exported_Functions_Group3
00416   * @{
00417   */
00418 /* Peripheral Control functions ***********************************************/
00419 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
00420
00421 /**
00422   * @}
00423   */
00424
00425 /** @addtogroup DAC_Exported_Functions_Group4
00426   * @{
00427   */
00428 /* Peripheral State and Error functions ***************************************/
00429 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
00430 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
00431
00432 /**
00433   * @}
00434   */
00435
00436 /**
00437   * @}
00438   */
00439
00440 /**
00441   * @}
00442   */
00443
00444 /**
00445   * @}
00446   */
00447
00448 #ifdef __cplusplus
00449 }
00450 #endif
00451
00452 #endif /*__STM32F3xx_HAL_DAC_H */
00453
00454 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_dac_ex.c Source File

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stm32f3xx_hal_dac_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_dac_ex.c
00004   * @author  MCD Application Team
00005   * @brief   DACEx HAL module driver.
00006   *          This file provides firmware functions to manage the extended
00007   *          functionalities of the DAC peripheral.
00008   *
00009   *
00010   @verbatim
00011   ==============================================================================
00012                       ##### How to use this driver #####
00013   ==============================================================================
00014     [..]
00015       (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
00016           Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
00017           HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
00018       (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
00019       (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
00020
00021  @endverbatim
00022   ******************************************************************************
00023   * @attention
00024   *
00025   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00026   *
00027   * Redistribution and use in source and binary forms, with or without modification,
00028   * are permitted provided that the following conditions are met:
00029   *   1. Redistributions of source code must retain the above copyright notice,
00030   *      this list of conditions and the following disclaimer.
00031   *   2. Redistributions in binary form must reproduce the above copyright notice,
00032   *      this list of conditions and the following disclaimer in the documentation
00033   *      and/or other materials provided with the distribution.
00034   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00035   *      may be used to endorse or promote products derived from this software
00036   *      without specific prior written permission.
00037   *
00038   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00039   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00040   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00041   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00042   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00043   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00044   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00045   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00046   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00047   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00048   *
00049   ******************************************************************************
00050   */
00051
00052 /* Includes ------------------------------------------------------------------*/
00053 #include "stm32f3xx_hal.h"
00054
00055 /** @addtogroup STM32F3xx_HAL_Driver
00056   * @{
00057   */
00058
00059 #ifdef HAL_DAC_MODULE_ENABLED
00060
00061 /** @defgroup DACEx DACEx
00062   * @brief DAC HAL module driver
00063   * @{
00064   */
00065
00066 /* Private typedef -----------------------------------------------------------*/
00067 /* Private define ------------------------------------------------------------*/
00068 /* Private macro -------------------------------------------------------------*/
00069 /* Private variables ---------------------------------------------------------*/
00070 /* Private function prototypes -----------------------------------------------*/
00071 /** @defgroup DACEx_Private_Functions DACEx Private Functions
00072   * @{
00073   */
00074 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
00075 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
00076 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
00077
00078 #if defined(STM32F303xE) || defined(STM32F398xx)                         || \
00079     defined(STM32F303xC) || defined(STM32F358xx)                         || \
00080     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00081     defined(STM32F373xC) || defined(STM32F378xx)
00082 /* DAC channel 2 is available on top of DAC channel 1U */
00083 static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
00084 static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
00085 static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
00086 #endif /* STM32F303xE || STM32F398xx                || */
00087        /* STM32F303xC || STM32F358xx                || */
00088        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00089        /* STM32F373xC || STM32F378xx                   */
00090 /**
00091   * @}
00092   */
00093
00094 /* Exported functions ---------------------------------------------------------*/
00095 /** @defgroup DACEx_Exported_Functions DACEx Exported Functions
00096   * @{
00097   */
00098
00099 /** @defgroup DACEx_Exported_Functions_Group3 DACEx Peripheral Control functions
00100  *  @brief      Peripheral Control functions
00101  *
00102 @verbatim
00103   ==============================================================================
00104              ##### Peripheral Control functions #####
00105   ==============================================================================
00106     [..]  This section provides functions allowing to:
00107       (+) Set the specified data holding register value for DAC channel.
00108       (+) Set the specified data holding register value for dual DAC channel
00109               (when DAC channel 2 is present in DAC 1U)
00110
00111 @endverbatim
00112   * @{
00113   */
00114
00115 /**
00116   * @brief  Set the specified data holding register value for DAC channel.
00117   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00118   *         the configuration information for the specified DAC.
00119   * @param  Channel The selected DAC channel.
00120   * @param  Alignment Specifies the data alignment for DAC channel.
00121   *          This parameter can be one of the following values:
00122   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00123   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00124   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00125   * @param  Data Data to be loaded in the selected data holding register.
00126   * @retval HAL status
00127   */
00128 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
00129 {
00130   __IO uint32_t tmp = 0U;
00131
00132   /* Check the parameters */
00133   assert_param(IS_DAC_CHANNEL(Channel));
00134   assert_param(IS_DAC_ALIGN(Alignment));
00135   assert_param(IS_DAC_DATA(Data));
00136
00137   tmp = (uint32_t) (hdac->Instance);
00138
00139 /* DAC 1 has 1 or 2 channels - no DAC2 */
00140 /* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
00141
00142   if(Channel == DAC_CHANNEL_1)
00143   {
00144     tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
00145   }
00146 #if defined(STM32F303xE) || defined(STM32F398xx)                         || \
00147     defined(STM32F303xC) || defined(STM32F358xx)                         || \
00148     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00149     defined(STM32F373xC) || defined(STM32F378xx)
00150   else /* channel = DAC_CHANNEL_2  */
00151   {
00152     tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
00153   }
00154 #endif /* STM32F303xE || STM32F398xx                || */
00155        /* STM32F303xC || STM32F358xx                || */
00156        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00157        /* STM32F373xC || STM32F378xx                   */
00158
00159   /* Set the DAC channel1 selected data holding register */
00160   *(__IO uint32_t *) tmp = Data;
00161
00162   /* Return function status */
00163   return HAL_OK;
00164 }
00165
00166 #if  defined(STM32F303xE) || defined(STM32F398xx)                         || \
00167      defined(STM32F303xC) || defined(STM32F358xx)                         || \
00168      defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00169      defined(STM32F373xC) || defined(STM32F378xx)
00170 /* DAC channel 2 is present in DAC 1U */
00171 /**
00172   * @brief  Set the specified data holding register value for dual DAC channel.
00173   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00174   *         the configuration information for the specified DAC.
00175   * @param  Alignment Specifies the data alignment for dual channel DAC.
00176   *          This parameter can be one of the following values:
00177   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00178   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00179   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00180   * @param  Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
00181   * @param  Data1: Data for DAC Channel1 to be loaded in the selected data  holding register.
00182   * @note   In dual mode, a unique register access is required to write in both
00183   *          DAC channels at the same time.
00184   * @retval HAL status
00185   */
00186 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
00187 {
00188   uint32_t data = 0U, tmp = 0U;
00189
00190   /* Check the parameters */
00191   assert_param(IS_DAC_ALIGN(Alignment));
00192   assert_param(IS_DAC_DATA(Data1));
00193   assert_param(IS_DAC_DATA(Data2));
00194
00195   /* Calculate and set dual DAC data holding register value */
00196   if (Alignment == DAC_ALIGN_8B_R)
00197   {
00198     data = ((uint32_t)Data2 << 8U) | Data1;
00199   }
00200   else
00201   {
00202     data = ((uint32_t)Data2 << 16U) | Data1;
00203   }
00204
00205     tmp = (uint32_t) (hdac->Instance);
00206     tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
00207
00208   /* Set the dual DAC selected data holding register */
00209   *(__IO uint32_t *)tmp = data;
00210
00211   /* Return function status */
00212   return HAL_OK;
00213 }
00214 #endif /* STM32F303xE || STM32F398xx                || */
00215        /* STM32F303xC || STM32F358xx                || */
00216        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00217        /* STM32F373xC || STM32F378xx                   */
00218
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup DACEx_Exported_Functions_Group2 DACEx Input and Output operation functions
00224  *  @brief    IO operation functions
00225  *
00226 @verbatim
00227   ==============================================================================
00228              ##### IO operation functions #####
00229   ==============================================================================
00230     [..]  This section provides functions allowing to:
00231       (+) Start conversion.
00232       (+) Start conversion and enable DMA transfer.
00233       (+) Get result of conversion.
00234       (+) Handle DAC IRQ's.
00235       (+) Generate triangular-wave
00236       (+) Generate noise-wave
00237           (+) Callback functions for DAC1 Channel2 (when supported)
00238 @endverbatim
00239   * @{
00240   */
00241
00242 #if  defined(STM32F303xE) || defined(STM32F398xx)                         || \
00243      defined(STM32F303xC) || defined(STM32F358xx)                         || \
00244      defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00245      defined(STM32F373xC) || defined(STM32F378xx)
00246
00247 /* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
00248 /**
00249   * @brief  Enables DAC and starts conversion of channel.
00250   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00251   *         the configuration information for the specified DAC.
00252   * @param  Channel The selected DAC channel.
00253   *          This parameter can be one of the following values:
00254   *            @arg DAC_CHANNEL_1: DAC1 Channel1 or DAC2 Channel1 selected
00255   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
00256   * @retval HAL status
00257   */
00258 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
00259 {
00260   /* Check the parameters */
00261   assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
00262
00263   /* Process locked */
00264   __HAL_LOCK(hdac);
00265
00266   /* Change DAC state */
00267   hdac->State = HAL_DAC_STATE_BUSY;
00268
00269   /* Enable the Peripheral */
00270   __HAL_DAC_ENABLE(hdac, Channel);
00271
00272   if(Channel == DAC_CHANNEL_1)
00273   {
00274     /* Check if software trigger enabled */
00275     if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
00276     {
00277       /* Enable the selected DAC software conversion */
00278       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
00279     }
00280   }
00281   else
00282   {
00283     /* Check if software trigger enabled */
00284     if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2))
00285     {
00286       /* Enable the selected DAC software conversion */
00287       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
00288     }
00289   }
00290
00291   /* Change DAC state */
00292   hdac->State = HAL_DAC_STATE_READY;
00293
00294   /* Process unlocked */
00295   __HAL_UNLOCK(hdac);
00296
00297   /* Return function status */
00298   return HAL_OK;
00299 }
00300 #endif /* STM32F303xE || STM32F398xx                || */
00301        /* STM32F303xC || STM32F358xx                || */
00302        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00303        /* STM32F373xC || STM32F378xx                   */
00304
00305 #if defined(STM32F302xE) || \
00306     defined(STM32F302xC) || \
00307     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00308 /* DAC 1 has 1 channels 1U */
00309 /**
00310   * @brief  Enables DAC and starts conversion of channel.
00311   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00312   *         the configuration information for the specified DAC.
00313   * @param  Channel The selected DAC channel.
00314   *          This parameter can be one of the following values:
00315   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
00316   * @retval HAL status
00317   */
00318
00319 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
00320 {
00321   /* Check the parameters */
00322   assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
00323
00324   /* Process locked */
00325   __HAL_LOCK(hdac);
00326
00327   /* Change DAC state */
00328   hdac->State = HAL_DAC_STATE_BUSY;
00329
00330   /* Enable the Peripheral */
00331   __HAL_DAC_ENABLE(hdac, Channel);
00332
00333   /* Check if software trigger enabled */
00334   if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
00335   {
00336     /* Enable the selected DAC software conversion */
00337     SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
00338   }
00339
00340   /* Change DAC state */
00341   hdac->State = HAL_DAC_STATE_READY;
00342
00343   /* Process unlocked */
00344   __HAL_UNLOCK(hdac);
00345
00346   /* Return function status */
00347   return HAL_OK;
00348 }
00349 #endif /* STM32F302xE                               || */
00350        /* STM32F302xC                               || */
00351        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00352
00353 /* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
00354 #if defined(STM32F303xE) || defined(STM32F398xx)                         || \
00355     defined(STM32F303xC) || defined(STM32F358xx)                         || \
00356     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00357     defined(STM32F373xC) || defined(STM32F378xx)
00358 /* DAC 1 has 2 channels 1U & 2U */
00359 /**
00360   * @brief  Enables DAC and starts conversion of channel.
00361   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00362   *         the configuration information for the specified DAC.
00363   * @param  Channel The selected DAC channel.
00364   *          This parameter can be one of the following values:
00365   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
00366   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
00367   * @param  pData The destination peripheral Buffer address.
00368   * @param  Length The length of data to be transferred from memory to DAC peripheral
00369   * @param  Alignment Specifies the data alignment for DAC channel.
00370   *          This parameter can be one of the following values:
00371   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00372   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00373   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00374   * @retval HAL status
00375   */
00376 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
00377 {
00378   uint32_t tmpreg = 0U;
00379
00380   /* Check the parameters */
00381   assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
00382   assert_param(IS_DAC_ALIGN(Alignment));
00383
00384   /* Process locked */
00385   __HAL_LOCK(hdac);
00386
00387   /* Change DAC state */
00388   hdac->State = HAL_DAC_STATE_BUSY;
00389
00390   if(Channel == DAC_CHANNEL_1)
00391   {
00392     /* Set the DMA transfer complete callback for channel1 */
00393     hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
00394
00395     /* Set the DMA half transfer complete callback for channel1 */
00396     hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
00397
00398     /* Set the DMA error callback for channel1 */
00399     hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
00400
00401     /* Enable the selected DAC channel1 DMA request */
00402     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00403
00404     /* Case of use of channel 1U */
00405     switch(Alignment)
00406     {
00407       case DAC_ALIGN_12B_R:
00408         /* Get DHR12R1 address */
00409         tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
00410         break;
00411       case DAC_ALIGN_12B_L:
00412         /* Get DHR12L1 address */
00413         tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
00414         break;
00415       case DAC_ALIGN_8B_R:
00416         /* Get DHR8R1 address */
00417         tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
00418         break;
00419       default:
00420         break;
00421     }
00422   }
00423   else
00424   {
00425     /* Set the DMA transfer complete callback for channel2 */
00426     hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
00427
00428     /* Set the DMA half transfer complete callback for channel2 */
00429     hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
00430
00431     /* Set the DMA error callback for channel2 */
00432     hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
00433
00434     /* Enable the selected DAC channel2 DMA request */
00435     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
00436
00437     /* Case of use of channel 2U */
00438     switch(Alignment)
00439     {
00440       case DAC_ALIGN_12B_R:
00441         /* Get DHR12R2 address */
00442         tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
00443         break;
00444       case DAC_ALIGN_12B_L:
00445         /* Get DHR12L2 address */
00446         tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
00447         break;
00448       case DAC_ALIGN_8B_R:
00449         /* Get DHR8R2 address */
00450         tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
00451         break;
00452       default:
00453         break;
00454     }
00455   }
00456
00457   /* Enable the DMA Channel */
00458   if(Channel == DAC_CHANNEL_1)
00459   {
00460     /* Enable the DAC DMA underrun interrupt */
00461     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
00462
00463     /* Enable the DMA Channel */
00464     HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
00465   }
00466   else
00467   {
00468     /* Enable the DAC DMA underrun interrupt */
00469     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
00470
00471     /* Enable the DMA Channel */
00472     HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
00473   }
00474
00475   /* Process Unlocked */
00476   __HAL_UNLOCK(hdac);
00477
00478   /* Enable the Peripheral */
00479   __HAL_DAC_ENABLE(hdac, Channel);
00480
00481   /* Return function status */
00482   return HAL_OK;
00483 }
00484 #endif /* STM32F303xE || STM32F398xx                || */
00485        /* STM32F303xC || STM32F358xx                || */
00486        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00487        /* STM32F373xC || STM32F378xx                   */
00488
00489 #if defined(STM32F302xE) || \
00490     defined(STM32F302xC) || \
00491     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00492 /* DAC 1 has 1 channel (channel 1U)  */
00493 /**
00494   * @brief  Enables DAC and starts conversion of channel.
00495   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00496   *         the configuration information for the specified DAC.
00497   * @param  Channel The selected DAC channel.
00498   *          This parameter can be one of the following values:
00499   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
00500   * @param  pData The destination peripheral Buffer address.
00501   * @param  Length The length of data to be transferred from memory to DAC peripheral
00502   * @param  Alignment Specifies the data alignment for DAC channel.
00503   *          This parameter can be one of the following values:
00504   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00505   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00506   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00507   * @retval HAL status
00508   */
00509 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
00510 {
00511   uint32_t tmpreg = 0U;
00512
00513   /* Check the parameters */
00514   assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
00515   assert_param(IS_DAC_ALIGN(Alignment));
00516
00517   /* Process locked */
00518   __HAL_LOCK(hdac);
00519
00520   /* Change DAC state */
00521   hdac->State = HAL_DAC_STATE_BUSY;
00522
00523   /* Set the DMA transfer complete callback for channel1 */
00524   hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
00525
00526   /* Set the DMA half transfer complete callback for channel1 */
00527   hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
00528
00529   /* Set the DMA error callback for channel1 */
00530   hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
00531
00532   /* Enable the selected DAC channel1 DMA request */
00533   SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00534
00535   /* Case of use of channel 1U */
00536   switch(Alignment)
00537   {
00538     case DAC_ALIGN_12B_R:
00539       /* Get DHR12R1 address */
00540       tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
00541       break;
00542     case DAC_ALIGN_12B_L:
00543       /* Get DHR12L1 address */
00544       tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
00545       break;
00546     case DAC_ALIGN_8B_R:
00547       /* Get DHR8R1 address */
00548       tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
00549       break;
00550     default:
00551       break;
00552   }
00553
00554   /* Enable the DMA Channel */
00555   /* Enable the DAC DMA underrun interrupt */
00556   __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
00557
00558   /* Enable the DMA Channel */
00559   HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
00560
00561   /* Process Unlocked */
00562   __HAL_UNLOCK(hdac);
00563
00564   /* Enable the Peripheral */
00565   __HAL_DAC_ENABLE(hdac, Channel);
00566
00567   /* Return function status */
00568   return HAL_OK;
00569 }
00570 #endif /* STM32F302xE                               || */
00571        /* STM32F302xC                               || */
00572        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00573
00574 /* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
00575 #if  defined(STM32F303xE) || defined(STM32F398xx)                         || \
00576      defined(STM32F303xC) || defined(STM32F358xx)                         || \
00577      defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00578      defined(STM32F373xC) || defined(STM32F378xx)
00579 /* DAC 1 has 2 channels 1U & 2U */
00580 /**
00581   * @brief  Returns the last data output value of the selected DAC channel.
00582   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00583   *         the configuration information for the specified DAC.
00584   * @param  Channel The selected DAC channel.
00585   *          This parameter can be one of the following values:
00586   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
00587   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
00588   * @retval The selected DAC channel data output value.
00589   */
00590 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
00591 {
00592   /* Check the parameters */
00593   assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
00594
00595   /* Returns the DAC channel data output register value */
00596   if(Channel == DAC_CHANNEL_1)
00597   {
00598     return hdac->Instance->DOR1;
00599   }
00600   else /* channel = DAC_CHANNEL_2  */
00601   {
00602     return hdac->Instance->DOR2;
00603   }
00604 }
00605 #endif /* STM32F303xE || STM32F398xx                || */
00606        /* STM32F303xC || STM32F358xx                || */
00607        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00608        /* STM32F373xC || STM32F378xx                   */
00609
00610 #if defined(STM32F302xE) || \
00611     defined(STM32F302xC) || \
00612     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00613 /* DAC 1 has 1 channel (channel 1U)  */
00614 /**
00615   * @brief  Returns the last data output value of the selected DAC channel.
00616   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00617   *         the configuration information for the specified DAC.
00618   * @param  channel The selected DAC channel.
00619   *          This parameter can be one of the following values:
00620   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
00621   * @retval The selected DAC channel data output value.
00622   */
00623 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
00624 {
00625   /* Check the parameters */
00626   assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
00627
00628   /* Returns the DAC channel data output register value */
00629   return hdac->Instance->DOR1;
00630 }
00631 #endif /* STM32F302xE                               || */
00632        /* STM32F302xC                               || */
00633        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00634
00635 /**
00636   * @brief  Return the last data output value of the selected DAC channel.
00637   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00638   *         the configuration information for the specified DAC.
00639   * @retval The selected DAC channel data output value.
00640   */
00641 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
00642 {
00643   uint32_t tmp = 0U;
00644
00645   tmp |= hdac->Instance->DOR1;
00646
00647 #if  defined(STM32F303xE) || defined(STM32F398xx)                         || \
00648      defined(STM32F303xC) || defined(STM32F358xx)                         || \
00649      defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00650      defined(STM32F373xC) || defined(STM32F378xx)
00651 /* DAC channel 2 is present in DAC 1U */
00652   tmp |= hdac->Instance->DOR2 << 16U;
00653 #endif /* STM32F303xE || STM32F398xx                || */
00654        /* STM32F303xC || STM32F358xx                || */
00655        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00656        /* STM32F373xC || STM32F378xx                   */
00657
00658   /* Returns the DAC channel data output register value */
00659   return tmp;
00660 }
00661
00662 #if  defined(STM32F303xE) || defined(STM32F398xx)                         || \
00663      defined(STM32F303xC) || defined(STM32F358xx)                         || \
00664      defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00665      defined(STM32F373xC) || defined(STM32F378xx)
00666 /* DAC channel 2 is available on top of DAC channel 1U */
00667 /**
00668   * @brief  Handles DAC interrupt request
00669   *         This function uses the interruption of DMA
00670   *         underrun.
00671   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00672   *         the configuration information for the specified DAC.
00673   * @retval None
00674   */
00675 void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
00676 {
00677   if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
00678   {
00679     /* Check underrun flag of DAC channel 1U */
00680     if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
00681     {
00682       /* Change DAC state to error state */
00683       hdac->State = HAL_DAC_STATE_ERROR;
00684
00685       /* Set DAC error code to chanel1 DMA underrun error */
00686       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
00687
00688       /* Clear the underrun flag */
00689       __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
00690
00691       /* Disable the selected DAC channel1 DMA request */
00692       CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00693
00694       /* Error callback */
00695       HAL_DAC_DMAUnderrunCallbackCh1(hdac);
00696     }
00697   }
00698
00699   if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
00700   {
00701     /* Check underrun flag of DAC channel 1U */
00702     if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
00703     {
00704       /* Change DAC state to error state */
00705       hdac->State = HAL_DAC_STATE_ERROR;
00706
00707       /* Set DAC error code to channel2 DMA underrun error */
00708       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
00709
00710       /* Clear the underrun flag */
00711       __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
00712
00713       /* Disable the selected DAC channel1 DMA request */
00714       CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
00715
00716       /* Error callback */
00717       HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
00718     }
00719   }
00720 }
00721 #endif /* STM32F303xE || STM32F398xx                || */
00722        /* STM32F303xC || STM32F358xx                || */
00723        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00724        /* STM32F373xC || STM32F378xx                   */
00725
00726 #if defined(STM32F302xE) || \
00727     defined(STM32F302xC) || \
00728     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00729 /* DAC channel 2 is NOT available. Only DAC channel 1 is available */
00730 /**
00731   * @brief  Handles DAC interrupt request
00732   *         This function uses the interruption of DMA
00733   *         underrun.
00734   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00735   *         the configuration information for the specified DAC.
00736   * @retval None
00737   */
00738 void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
00739 {
00740   if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
00741   {
00742     /* Check underrun flag of DAC channel 1U */
00743     if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
00744     {
00745       /* Change DAC state to error state */
00746       hdac->State = HAL_DAC_STATE_ERROR;
00747
00748       /* Set DAC error code to chanel1 DMA underrun error */
00749       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
00750
00751       /* Clear the underrun flag */
00752       __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
00753
00754       /* Disable the selected DAC channel1 DMA request */
00755       CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00756
00757       /* Error callback */
00758       HAL_DAC_DMAUnderrunCallbackCh1(hdac);
00759     }
00760   }
00761 }
00762 #endif /* STM32F302xE                               || */
00763        /* STM32F302xC                               || */
00764        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00765
00766 /**
00767   * @brief  Configures the selected DAC channel.
00768   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00769   *         the configuration information for the specified DAC.
00770   * @param  sConfig DAC configuration structure.
00771   * @param  Channel The selected DAC channel.
00772   *          This parameter can be one of the following values:
00773   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
00774   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
00775   *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected
00776   * @retval HAL status
00777   */
00778
00779 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
00780 {
00781   uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
00782
00783   /* Check the DAC parameters */
00784   assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
00785
00786 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
00787   if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1))
00788   {
00789     /* Output Buffer (BOFF1) control */
00790     assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
00791   }
00792   else /* DAC1 channel 2U & DAC2 channel 1U */
00793   {
00794     /* Output Switch (OUTEN) control */
00795     assert_param(IS_DAC_OUTPUT_SWITCH_STATE(sConfig->DAC_OutputSwitch));
00796   }
00797 #else
00798   assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
00799 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00800   assert_param(IS_DAC_CHANNEL(Channel));
00801
00802   /* Process locked */
00803   __HAL_LOCK(hdac);
00804
00805   /* Change DAC state */
00806   hdac->State = HAL_DAC_STATE_BUSY;
00807
00808   /* Get the DAC CR value */
00809   tmpreg1 = hdac->Instance->CR;
00810
00811   /* Clear BOFFx-OUTENx, TENx, TSELx, WAVEx and MAMPx bits */
00812
00813   /* Configure for the selected DAC channel: buffer output or switch output, trigger */
00814   /* Set TSELx and TENx bits according to DAC_Trigger value */
00815   /* Set BOFFx bit according to DAC_OutputBuffer value OR */
00816   /* Set OUTEN bit according to DAC_OutputSwitch value */
00817 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
00818   if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1))
00819   {
00820     /* Output Buffer (BOFF1) control */
00821     tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
00822     tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
00823   }
00824   else /* DAC1 channel 2U & DAC2 channel 1U */
00825   {
00826     /* Output Switch (OUTEN) control */
00827     tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_OUTEN1)) << Channel);
00828     tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputSwitch);
00829   }
00830 #else
00831   tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
00832   tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
00833 #endif  /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00834
00835   /* Calculate CR register value depending on DAC_Channel */
00836   tmpreg1 |= tmpreg2 << Channel;
00837   /* Write to DAC CR */
00838   hdac->Instance->CR = tmpreg1;
00839
00840   /* Disable wave generation */
00841   hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
00842
00843   /* Change DAC state */
00844   hdac->State = HAL_DAC_STATE_READY;
00845
00846   /* Process unlocked */
00847   __HAL_UNLOCK(hdac);
00848
00849   /* Return function status */
00850   return HAL_OK;
00851 }
00852
00853 /**
00854   * @brief  Enables or disables the selected DAC channel wave generation.
00855   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00856   *         the configuration information for the specified DAC.
00857   * @param  Channel The selected DAC channel.
00858   *          This parameter can be one of the following values:
00859   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
00860   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
00861   * @param  Amplitude Select max triangle amplitude.
00862   *          This parameter can be one of the following values:
00863   *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
00864   *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
00865   *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
00866   *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
00867   *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
00868   *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
00869   *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
00870   *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
00871   *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
00872   *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
00873   *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
00874   *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
00875   * @note   Wave generation is not available in DAC2.
00876   * @retval HAL status
00877   */
00878 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
00879 {
00880   /* Check the parameters */
00881   assert_param(IS_DAC_CHANNEL(Channel));
00882   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00883
00884   /* Process locked */
00885   __HAL_LOCK(hdac);
00886
00887   /* Change DAC state */
00888   hdac->State = HAL_DAC_STATE_BUSY;
00889
00890   /* Enable the selected wave generation for the selected DAC channel */
00891   MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
00892
00893   /* Change DAC state */
00894   hdac->State = HAL_DAC_STATE_READY;
00895
00896   /* Process unlocked */
00897   __HAL_UNLOCK(hdac);
00898
00899   /* Return function status */
00900   return HAL_OK;
00901 }
00902
00903 /**
00904   * @brief  Enables or disables the selected DAC channel wave generation.
00905   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00906   *         the configuration information for the specified DAC.
00907   * @param  Channel The selected DAC channel.
00908   *          This parameter can be one of the following values:
00909   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
00910   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
00911   * @param  Amplitude Unmask DAC channel LFSR for noise wave generation.
00912   *          This parameter can be one of the following values:
00913   *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
00914   *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
00915   *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
00916   *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
00917   *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
00918   *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
00919   *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
00920   *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
00921   *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
00922   *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
00923   *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
00924   *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
00925   * @retval HAL status
00926   */
00927 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
00928 {
00929   /* Check the parameters */
00930   assert_param(IS_DAC_CHANNEL(Channel));
00931   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00932
00933   /* Process locked */
00934   __HAL_LOCK(hdac);
00935
00936   /* Change DAC state */
00937   hdac->State = HAL_DAC_STATE_BUSY;
00938
00939   /* Enable the selected wave generation for the selected DAC channel */
00940   MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
00941
00942   /* Change DAC state */
00943   hdac->State = HAL_DAC_STATE_READY;
00944
00945   /* Process unlocked */
00946   __HAL_UNLOCK(hdac);
00947
00948   /* Return function status */
00949   return HAL_OK;
00950 }
00951
00952 #if  defined(STM32F303xE) || defined(STM32F398xx)                         || \
00953      defined(STM32F303xC) || defined(STM32F358xx)                         || \
00954      defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00955      defined(STM32F373xC) || defined(STM32F378xx)
00956 /* DAC channel 2 is available on top of DAC channel 1U */
00957 /**
00958   * @brief  Conversion complete callback in non blocking mode for Channel2
00959   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00960   *         the configuration information for the specified DAC.
00961   * @retval None
00962   */
00963 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
00964 {
00965   /* Prevent unused argument(s) compilation warning */
00966   UNUSED(hdac);
00967
00968   /* NOTE : This function Should not be modified, when the callback is needed,
00969             the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
00970    */
00971 }
00972
00973 /**
00974   * @brief  Conversion half DMA transfer callback in non blocking mode for Channel2
00975   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00976   *         the configuration information for the specified DAC.
00977   * @retval None
00978   */
00979 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
00980 {
00981   /* Prevent unused argument(s) compilation warning */
00982   UNUSED(hdac);
00983
00984   /* NOTE : This function Should not be modified, when the callback is needed,
00985             the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
00986    */
00987 }
00988
00989 /**
00990   * @brief  Error DAC callback for Channel2.
00991   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00992   *         the configuration information for the specified DAC.
00993   * @retval None
00994   */
00995 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
00996 {
00997   /* Prevent unused argument(s) compilation warning */
00998   UNUSED(hdac);
00999
01000   /* NOTE : This function Should not be modified, when the callback is needed,
01001             the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
01002    */
01003 }
01004
01005 /**
01006   * @brief  DMA underrun DAC callback for channel2.
01007   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
01008   *         the configuration information for the specified DAC.
01009   * @retval None
01010   */
01011 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
01012 {
01013   /* Prevent unused argument(s) compilation warning */
01014   UNUSED(hdac);
01015
01016   /* NOTE : This function Should not be modified, when the callback is needed,
01017             the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
01018    */
01019 }
01020 #endif /* STM32F303xE || STM32F398xx                || */
01021        /* STM32F303xC || STM32F358xx                || */
01022        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
01023        /* STM32F373xC || STM32F378xx                   */
01024 /**
01025   * @}
01026   */
01027
01028 /**
01029   * @}
01030   */
01031
01032 /**
01033   * @}
01034   */
01035
01036 /** @addtogroup DACEx_Private_Functions
01037   * @{
01038   */
01039
01040 /**
01041   * @brief  DMA conversion complete callback.
01042   * @param  hdma pointer to DMA handle.
01043   * @retval None
01044   */
01045 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
01046 {
01047   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01048
01049   HAL_DAC_ConvCpltCallbackCh1(hdac);
01050
01051   hdac->State= HAL_DAC_STATE_READY;
01052 }
01053
01054 /**
01055   * @brief  DMA half transfer complete callback.
01056   * @param  hdma pointer to DMA handle.
01057   * @retval None
01058   */
01059 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
01060 {
01061     DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01062     /* Conversion complete callback */
01063     HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
01064 }
01065
01066 /**
01067   * @brief  DMA error callback
01068   * @param  hdma pointer to DMA handle.
01069   * @retval None
01070   */
01071 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
01072 {
01073   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01074
01075   /* Set DAC error code to DMA error */
01076   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
01077
01078   HAL_DAC_ErrorCallbackCh1(hdac);
01079
01080   hdac->State= HAL_DAC_STATE_READY;
01081 }
01082
01083 #if  defined(STM32F303xE) || defined(STM32F398xx)                         || \
01084      defined(STM32F303xC) || defined(STM32F358xx)                         || \
01085      defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
01086      defined(STM32F373xC) || defined(STM32F378xx)
01087 /* DAC channel 2 is available on top of DAC channel 1U */
01088 /**
01089   * @brief  DMA conversion complete callback.
01090   * @param  hdma pointer to DMA handle.
01091   * @retval None
01092   */
01093 static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
01094 {
01095   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01096
01097   HAL_DACEx_ConvCpltCallbackCh2(hdac);
01098
01099   hdac->State= HAL_DAC_STATE_READY;
01100 }
01101
01102 /**
01103   * @brief  DMA half transfer complete callback.
01104   * @param  hdma pointer to DMA handle.
01105   * @retval None
01106   */
01107 static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
01108 {
01109     DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01110     /* Conversion complete callback */
01111     HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
01112 }
01113
01114 /**
01115   * @brief  DMA error callback
01116   * @param  hdma pointer to DMA handle.
01117   * @retval None
01118   */
01119 static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
01120 {
01121   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01122
01123   /* Set DAC error code to DMA error */
01124   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
01125
01126   HAL_DACEx_ErrorCallbackCh2(hdac);
01127
01128   hdac->State= HAL_DAC_STATE_READY;
01129 }
01130 #endif /* STM32F303xE || STM32F398xx                || */
01131        /* STM32F303xC || STM32F358xx                || */
01132        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
01133        /* STM32F373xC || STM32F378xx                   */
01134
01135 /**
01136   * @}
01137   */
01138
01139 #endif /* HAL_DAC_MODULE_ENABLED */
01140 /**
01141   * @}
01142   */
01143
01144 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_dac_ex.h Source File

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stm32f3xx_hal_dac_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_dac_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DAC HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_DAC_EX_H
00038 #define __STM32F3xx_HAL_DAC_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup DACEx
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /* Exported constants --------------------------------------------------------*/
00057 /** @defgroup DACEx_Exported_Constants DACEx Exported Constants
00058   * @{
00059   */
00060
00061 /** @defgroup DACEx_trigger_selection DACEx trigger selection
00062   * @{
00063   */
00064
00065 #if defined(STM32F301x8) || defined(STM32F318xx)
00066 #define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
00067                                                                      has been loaded, and not by external trigger */
00068 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
00069 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
00070 #define DAC_TRIGGER_T15_TRGO               ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
00071 #define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
00072 #define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
00073
00074 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
00075                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
00076                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
00077                                  ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
00078                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
00079                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
00080 #endif /* STM32F301x8 || STM32F318xx */
00081
00082 #if defined(STM32F302xE) || \
00083     defined(STM32F302xC) || \
00084     defined(STM32F302x8)
00085
00086 #define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
00087                                                                      has been loaded, and not by external trigger */
00088 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
00089 #define DAC_TRIGGER_T3_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
00090 #define DAC_TRIGGER_T15_TRGO               ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
00091 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
00092 #define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
00093 #define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
00094 #define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
00095
00096 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
00097                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
00098                                  ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
00099                                  ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
00100                                  ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
00101                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
00102                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
00103                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
00104
00105 #endif /* STM32F302xE || */
00106        /* STM32F302xC || */
00107        /* STM32F302x8 */
00108
00109 #if defined(STM32F303xE) || defined(STM32F398xx) || \
00110     defined(STM32F303xC) || defined(STM32F358xx)
00111
00112 #define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
00113                                                                      has been loaded, and not by external trigger */
00114 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
00115 #define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
00116 #define DAC_TRIGGER_T15_TRGO               ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
00117 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
00118 #define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
00119 #define DAC_TRIGGER_T3_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
00120                                                                                            Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 selection */
00121 #define DAC_TRIGGER_T8_TRGO                DAC_TRIGGER_T3_TRGO                        /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
00122                                                                                            Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM8 selection */
00123
00124 #define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
00125 #define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
00126
00127 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
00128                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
00129                                  ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
00130                                  ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
00131                                  ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
00132                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
00133                                  ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
00134                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
00135                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
00136 #endif /* STM32F303xE || STM32F398xx || */
00137        /* STM32F303xC || STM32F358xx    */
00138
00139
00140 #if defined(STM32F303x8) || defined(STM32F328xx)
00141
00142 #define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
00143                                                                      has been loaded, and not by external trigger */
00144 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
00145 #define DAC_TRIGGER_T15_TRGO               ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
00146 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
00147 #define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
00148 #define DAC_TRIGGER_T3_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
00149
00150 #define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
00151 #define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
00152
00153 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
00154                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
00155                                  ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
00156                                  ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
00157                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
00158                                  ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
00159                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
00160                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
00161
00162 #endif /* STM32F303x8 || STM32F328xx */
00163
00164
00165 #if defined(STM32F373xC) || defined(STM32F378xx)
00166
00167 #define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
00168                                                                      has been loaded, and not by external trigger */
00169
00170 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
00171 #define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
00172 #define DAC_TRIGGER_T5_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel (DAC1) */
00173 #define DAC_TRIGGER_T18_TRGO               DAC_TRIGGER_T5_TRGO                                         /*!< TIM18 TRGO selected as external conversion trigger for DAC channel (DAC2) */
00174 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
00175 #define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
00176 #define DAC_TRIGGER_T3_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
00177
00178 #define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
00179 #define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
00180
00181
00182 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
00183                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
00184                                  ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
00185                                  ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
00186                                  ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
00187                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
00188                                  ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
00189                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
00190                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
00191 #endif /* STM32F373xC || STM32F378xx */
00192
00193 #if defined(STM32F334x8)
00194
00195 #define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
00196                                                                      has been loaded, and not by external trigger */
00197 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
00198 #define DAC_TRIGGER_T3_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
00199                                                                                            Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 remap */
00200
00201 #define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
00202 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
00203 #define DAC_TRIGGER_T15_TRGO               ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
00204                                                                                                             Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for TIM15 selection */
00205 #define DAC_TRIGGER_HRTIM1_DACTRG1         DAC_TRIGGER_T15_TRGO      /*!< HRTIM1 DACTRG1 selected as external conversion trigger for DAC
00206                                                                           Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for HRTIM1 DACTRG1 selection */
00207
00208 #define DAC_TRIGGER_HRTIM1_DACTRG2         ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< HRTIM1 DACTRG2 selected as external conversion trigger for DAC channel (DAC1)
00209                                                                                                             Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG5) for HRTIM1 DACTRG2 remap */
00210 #define DAC_TRIGGER_HRTIM1_DACTRG3         DAC_TRIGGER_HRTIM1_DACTRG2                                  /*!< HRTIM1 DACTRG3 selected as external conversion trigger for DAC channel (DAC2)*/
00211
00212 #define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
00213 #define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
00214
00215 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
00216                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
00217                                  ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
00218                                  ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
00219                                  ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
00220                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
00221                                  ((TRIGGER) == DAC_TRIGGER_HRTIM1_DACTRG2) || \
00222                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
00223                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
00224
00225 #endif /* STM32F334x8 */
00226
00227 /**
00228   * @}
00229   */
00230
00231 /** @defgroup DACEx_Channel_selection DACEx Channel selection
00232   * @{
00233   */
00234
00235 #if defined(STM32F302xE) || \
00236     defined(STM32F302xC) || \
00237     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00238 #define DAC_CHANNEL_1                      (0x00000000U)               /*!< DAC Channel 1U */
00239
00240 #endif  /* STM32F302xE                               || */
00241         /* STM32F302xC                               || */
00242         /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00243
00244
00245 #if defined(STM32F303xE) || defined(STM32F398xx) || \
00246     defined(STM32F303xC) || defined(STM32F358xx)
00247 #define DAC_CHANNEL_1                     (0x00000000U)       /*!< DAC Channel 1U */
00248 #define DAC_CHANNEL_2                     (0x00000010U)       /*!< DAC Channel 2U */
00249
00250 #endif /* STM32F303xE || STM32F398xx || */
00251        /* STM32F303xC || STM32F358xx    */
00252
00253 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00254     defined(STM32F373xC) || defined(STM32F378xx)
00255
00256 #define DAC_CHANNEL_1                     (0x00000000U)       /*!< DAC Channel 1U */
00257 #define DAC_CHANNEL_2                     (0x00000010U)       /*!< DAC Channel 2U */
00258
00259 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00260        /* STM32F373xC || STM32F378xx                   */
00261
00262 /**
00263   * @}
00264   */
00265
00266 /**
00267   * @}
00268   */
00269
00270 /* Private macro -------------------------------------------------------------*/
00271
00272 /** @defgroup DACEx_Private_Macros DACEx Private Macros
00273   * @{
00274   */
00275
00276 #if defined(STM32F302xE) || \
00277     defined(STM32F302xC) || \
00278     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00279
00280 #define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
00281 #endif  /* STM32F302xE                               || */
00282         /* STM32F302xC                               || */
00283         /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00284
00285
00286 #if defined(STM32F303xE) || defined(STM32F398xx) || \
00287     defined(STM32F303xC) || defined(STM32F358xx)
00288
00289 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
00290                                  ((CHANNEL) == DAC_CHANNEL_2))
00291 #endif /* STM32F303xE || STM32F398xx || */
00292        /* STM32F303xC || STM32F358xx    */
00293
00294 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00295     defined(STM32F373xC) || defined(STM32F378xx)
00296
00297 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
00298                                  ((CHANNEL) == DAC_CHANNEL_2))
00299 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00300        /* STM32F373xC || STM32F378xx  */
00301
00302
00303
00304 /**
00305   * @}
00306   */
00307
00308 /* Exported functions --------------------------------------------------------*/
00309
00310 /** @addtogroup DACEx_Exported_Functions
00311   * @{
00312   */
00313
00314 /** @addtogroup DACEx_Exported_Functions_Group2
00315  * @{
00316  */
00317 /* IO operation functions *****************************************************/
00318
00319 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
00320 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
00321 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
00322 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
00323
00324 #if  defined(STM32F303xE) || defined(STM32F398xx)                         || \
00325      defined(STM32F303xC) || defined(STM32F358xx)                         || \
00326      defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00327      defined(STM32F373xC) || defined(STM32F378xx)
00328 void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
00329 void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
00330 void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
00331 void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
00332 #endif /* STM32F303xE || STM32F398xx                || */
00333        /* STM32F303xC || STM32F358xx                || */
00334        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00335        /* STM32F373xC || STM32F378xx                   */
00336
00337 /**
00338   * @}
00339   */
00340
00341 /**
00342   * @}
00343   */
00344
00345 /**
00346    * @}
00347    */
00348
00349 /**
00350    * @}
00351    */
00352
00353 #ifdef __cplusplus
00354 }
00355 #endif
00356
00357 #endif /* __STM32F3xx_HAL_HAL_EX_H */
00358
00359 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_dma.c Source File

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stm32f3xx_hal_dma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_dma.c
00004   * @author  MCD Application Team
00005   * @brief   DMA HAL module driver.
00006   *
00007   *         This file provides firmware functions to manage the following
00008   *         functionalities of the Direct Memory Access (DMA) peripheral:
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral State and errors functions
00012   @verbatim
00013   ==============================================================================
00014                         ##### How to use this driver #####
00015   ==============================================================================
00016   [..]
00017    (#) Enable and configure the peripheral to be connected to the DMA Channel
00018        (except for internal SRAM / FLASH memories: no initialization is
00019        necessary). Please refer to Reference manual for connection between peripherals
00020        and DMA requests .
00021
00022    (#) For a given Channel, program the required configuration through the following parameters:
00023        Transfer Direction, Source and Destination data formats,
00024        Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
00025        using HAL_DMA_Init() function.
00026
00027    (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
00028        detection.
00029
00030    (#) Use HAL_DMA_Abort() function to abort the current transfer
00031
00032      -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
00033      *** Polling mode IO operation ***
00034      =================================
00035     [..]
00036       (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
00037           address and destination address and the Length of data to be transferred
00038       (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
00039           case a fixed Timeout can be configured by User depending from his application.
00040
00041      *** Interrupt mode IO operation ***
00042      ===================================
00043     [..]
00044       (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
00045       (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
00046       (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
00047           Source address and destination address and the Length of data to be transferred.
00048           In this case the DMA interrupt is configured
00049       (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
00050       (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
00051           add his own function by customization of function pointer XferCpltCallback and
00052           XferErrorCallback (i.e a member of DMA handle structure).
00053
00054      *** DMA HAL driver macros list ***
00055      =============================================
00056      [..]
00057        Below the list of most used macros in DMA HAL driver.
00058
00059      [..]
00060       (@) You can refer to the DMA HAL driver header file for more useful macros
00061
00062   @endverbatim
00063   ******************************************************************************
00064   * @attention
00065   *
00066   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00067   *
00068   * Redistribution and use in source and binary forms, with or without modification,
00069   * are permitted provided that the following conditions are met:
00070   *   1. Redistributions of source code must retain the above copyright notice,
00071   *      this list of conditions and the following disclaimer.
00072   *   2. Redistributions in binary form must reproduce the above copyright notice,
00073   *      this list of conditions and the following disclaimer in the documentation
00074   *      and/or other materials provided with the distribution.
00075   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00076   *      may be used to endorse or promote products derived from this software
00077   *      without specific prior written permission.
00078   *
00079   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00080   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00081   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00082   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00083   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00084   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00085   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00086   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00087   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00088   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00089   *
00090   ******************************************************************************
00091   */
00092
00093 /* Includes ------------------------------------------------------------------*/
00094 #include "stm32f3xx_hal.h"
00095
00096 /** @addtogroup STM32F3xx_HAL_Driver
00097   * @{
00098   */
00099
00100 /** @defgroup DMA DMA
00101   * @brief DMA HAL module driver
00102   * @{
00103   */
00104
00105 #ifdef HAL_DMA_MODULE_ENABLED
00106
00107 /* Private typedef -----------------------------------------------------------*/
00108 /* Private define ------------------------------------------------------------*/
00109 /* Private macro -------------------------------------------------------------*/
00110 /* Private variables ---------------------------------------------------------*/
00111 /* Private function prototypes -----------------------------------------------*/
00112 /** @defgroup DMA_Private_Functions DMA Private Functions
00113   * @{
00114   */
00115 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00116 static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
00117 /**
00118   * @}
00119   */
00120
00121 /* Exported functions ---------------------------------------------------------*/
00122
00123 /** @defgroup DMA_Exported_Functions DMA Exported Functions
00124   * @{
00125   */
00126
00127 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
00128  *  @brief   Initialization and de-initialization functions
00129  *
00130 @verbatim
00131  ===============================================================================
00132              ##### Initialization and de-initialization functions  #####
00133  ===============================================================================
00134     [..]
00135     This section provides functions allowing to initialize the DMA Channel source
00136     and destination addresses, incrementation and data sizes, transfer direction,
00137     circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
00138     [..]
00139     The HAL_DMA_Init() function follows the DMA configuration procedures as described in
00140     reference manual.
00141
00142 @endverbatim
00143   * @{
00144   */
00145
00146 /**
00147   * @brief  Initialize the DMA according to the specified
00148   *         parameters in the DMA_InitTypeDef and initialize the associated handle.
00149   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
00150   *               the configuration information for the specified DMA Channel.
00151   * @retval HAL status
00152   */
00153 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
00154 {
00155   uint32_t tmp = 0U;
00156
00157   /* Check the DMA handle allocation */
00158   if(NULL == hdma)
00159   {
00160     return HAL_ERROR;
00161   }
00162
00163   /* Check the parameters */
00164   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00165   assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
00166   assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
00167   assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
00168   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
00169   assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
00170   assert_param(IS_DMA_MODE(hdma->Init.Mode));
00171   assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
00172
00173   /* Change DMA peripheral state */
00174   hdma->State = HAL_DMA_STATE_BUSY;
00175
00176   /* Get the CR register value */
00177   tmp = hdma->Instance->CCR;
00178
00179   /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
00180   tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
00181                       DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
00182                       DMA_CCR_DIR));
00183
00184   /* Prepare the DMA Channel configuration */
00185   tmp |=  hdma->Init.Direction        |
00186           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
00187           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
00188           hdma->Init.Mode                | hdma->Init.Priority;
00189
00190   /* Write to DMA Channel CR register */
00191   hdma->Instance->CCR = tmp;
00192
00193   /* Initialize DmaBaseAddress and ChannelIndex parameters used
00194      by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
00195   DMA_CalcBaseAndBitshift(hdma);
00196
00197   /* Clean callbacks */
00198   hdma->XferCpltCallback = NULL;
00199   hdma->XferHalfCpltCallback = NULL;
00200   hdma->XferErrorCallback = NULL;
00201   hdma->XferAbortCallback = NULL;
00202
00203   /* Initialise the error code */
00204   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00205
00206   /* Initialize the DMA state*/
00207   hdma->State = HAL_DMA_STATE_READY;
00208
00209   /* Allocate lock resource and initialize it */
00210   hdma->Lock = HAL_UNLOCKED;
00211
00212   return HAL_OK;
00213 }
00214
00215 /**
00216   * @brief  DeInitialize the DMA peripheral
00217   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00218   *               the configuration information for the specified DMA Channel.
00219   * @retval HAL status
00220   */
00221 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
00222 {
00223   /* Check the DMA handle allocation */
00224   if(NULL == hdma)
00225   {
00226     return HAL_ERROR;
00227   }
00228
00229   /* Check the parameters */
00230   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00231
00232   /* Disable the selected DMA Channelx */
00233   hdma->Instance->CCR &= ~DMA_CCR_EN;
00234
00235   /* Reset DMA Channel control register */
00236   hdma->Instance->CCR  = 0U;
00237
00238   /* Reset DMA Channel Number of Data to Transfer register */
00239   hdma->Instance->CNDTR = 0U;
00240
00241   /* Reset DMA Channel peripheral address register */
00242   hdma->Instance->CPAR  = 0U;
00243
00244   /* Reset DMA Channel memory address register */
00245   hdma->Instance->CMAR = 0U;
00246
00247   /* Get DMA Base Address */
00248   DMA_CalcBaseAndBitshift(hdma);
00249
00250   /* Clear all flags */
00251   hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
00252
00253   /* Initialize the error code */
00254   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00255
00256   /* Initialize the DMA state */
00257   hdma->State = HAL_DMA_STATE_RESET;
00258
00259   /* Release Lock */
00260   __HAL_UNLOCK(hdma);
00261
00262   return HAL_OK;
00263 }
00264
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
00270  *  @brief   I/O operation functions
00271  *
00272 @verbatim
00273  ===============================================================================
00274                       #####  IO operation functions  #####
00275  ===============================================================================
00276     [..]  This section provides functions allowing to:
00277       (+) Configure the source, destination address and data length and Start DMA transfer
00278       (+) Configure the source, destination address and data length and
00279           Start DMA transfer with interrupt
00280       (+) Abort DMA transfer
00281       (+) Poll for transfer complete
00282       (+) Handle DMA interrupt request
00283
00284 @endverbatim
00285   * @{
00286   */
00287
00288 /**
00289   * @brief  Start the DMA Transfer.
00290   * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
00291   *                     the configuration information for the specified DMA Channel.
00292   * @param  SrcAddress The source memory Buffer address
00293   * @param  DstAddress The destination memory Buffer address
00294   * @param  DataLength The length of data to be transferred from source to destination
00295   * @retval HAL status
00296   */
00297 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00298 {
00299         HAL_StatusTypeDef status = HAL_OK;
00300
00301   /* Check the parameters */
00302   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00303
00304   /* Process locked */
00305   __HAL_LOCK(hdma);
00306
00307   if(HAL_DMA_STATE_READY == hdma->State)
00308   {
00309         /* Change DMA peripheral state */
00310         hdma->State = HAL_DMA_STATE_BUSY;
00311
00312         hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00313
00314         /* Disable the peripheral */
00315         hdma->Instance->CCR &= ~DMA_CCR_EN;
00316
00317         /* Configure the source, destination address and the data length */
00318         DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00319
00320         /* Enable the Peripheral */
00321         hdma->Instance->CCR |= DMA_CCR_EN;
00322   }
00323   else
00324   {
00325         /* Process Unlocked */
00326         __HAL_UNLOCK(hdma);
00327
00328         /* Remain BUSY */
00329         status = HAL_BUSY;
00330   }
00331
00332   return status;
00333 }
00334
00335 /**
00336   * @brief  Start the DMA Transfer with interrupt enabled.
00337   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
00338   *                     the configuration information for the specified DMA Channel.
00339   * @param  SrcAddress The source memory Buffer address
00340   * @param  DstAddress The destination memory Buffer address
00341   * @param  DataLength The length of data to be transferred from source to destination
00342   * @retval HAL status
00343   */
00344 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00345 {
00346         HAL_StatusTypeDef status = HAL_OK;
00347
00348   /* Check the parameters */
00349   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00350
00351   /* Process locked */
00352   __HAL_LOCK(hdma);
00353
00354   if(HAL_DMA_STATE_READY == hdma->State)
00355   {
00356         /* Change DMA peripheral state */
00357         hdma->State = HAL_DMA_STATE_BUSY;
00358
00359         hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00360
00361         /* Disable the peripheral */
00362         hdma->Instance->CCR &= ~DMA_CCR_EN;
00363
00364         /* Configure the source, destination address and the data length */
00365         DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00366
00367         /* Enable the transfer complete, & transfer error interrupts */
00368         /* Half transfer interrupt is optional: enable it only if associated callback is available */
00369     if(NULL != hdma->XferHalfCpltCallback )
00370     {
00371       hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
00372     }
00373         else
00374         {
00375                 hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
00376                 hdma->Instance->CCR &= ~DMA_IT_HT;
00377         }
00378
00379         /* Enable the Peripheral */
00380         hdma->Instance->CCR |= DMA_CCR_EN;
00381   }
00382   else
00383   {
00384         /* Process Unlocked */
00385     __HAL_UNLOCK(hdma);
00386
00387     /* Remain BUSY */
00388     status = HAL_BUSY;
00389   }
00390
00391   return status;
00392 }
00393
00394 /**
00395   * @brief  Abort the DMA Transfer.
00396   * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
00397   *                 the configuration information for the specified DMA Channel.
00398   * @retval HAL status
00399   */
00400 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
00401 {
00402         /* Disable DMA IT */
00403          hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
00404
00405         /* Disable the channel */
00406         hdma->Instance->CCR &= ~DMA_CCR_EN;
00407
00408         /* Clear all flags */
00409         hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
00410
00411         /* Change the DMA state*/
00412         hdma->State = HAL_DMA_STATE_READY;
00413
00414         /* Process Unlocked */
00415         __HAL_UNLOCK(hdma);
00416
00417         return HAL_OK;
00418 }
00419
00420 /**
00421   * @brief  Abort the DMA Transfer in Interrupt mode.
00422   * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
00423   *                 the configuration information for the specified DMA Stream.
00424   * @retval HAL status
00425   */
00426 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
00427 {
00428   HAL_StatusTypeDef status = HAL_OK;
00429
00430   if(HAL_DMA_STATE_BUSY != hdma->State)
00431   {
00432     /* no transfer ongoing */
00433     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00434
00435     status = HAL_ERROR;
00436   }
00437   else
00438   {
00439
00440     /* Disable DMA IT */
00441     hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
00442
00443     /* Disable the channel */
00444     hdma->Instance->CCR &= ~DMA_CCR_EN;
00445
00446     /* Clear all flags */
00447     hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
00448
00449     /* Change the DMA state */
00450     hdma->State = HAL_DMA_STATE_READY;
00451
00452     /* Process Unlocked */
00453     __HAL_UNLOCK(hdma);
00454
00455     /* Call User Abort callback */
00456     if(hdma->XferAbortCallback != NULL)
00457     {
00458       hdma->XferAbortCallback(hdma);
00459     }
00460   }
00461   return status;
00462 }
00463
00464 /**
00465   * @brief  Polling for transfer complete.
00466   * @param  hdma    pointer to a DMA_HandleTypeDef structure that contains
00467   *                  the configuration information for the specified DMA Channel.
00468   * @param  CompleteLevel Specifies the DMA level complete.
00469   * @param  Timeout       Timeout duration.
00470   * @retval HAL status
00471   */
00472 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
00473 {
00474   uint32_t temp;
00475   uint32_t tickstart = 0U;
00476
00477   if(HAL_DMA_STATE_BUSY != hdma->State)
00478   {
00479     /* no transfer ongoing */
00480     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00481     __HAL_UNLOCK(hdma);
00482     return HAL_ERROR;
00483   }
00484
00485   /* Polling mode not supported in circular mode */
00486   if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
00487   {
00488     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
00489     return HAL_ERROR;
00490   }
00491
00492   /* Get the level transfer complete flag */
00493   if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
00494   {
00495     /* Transfer Complete flag */
00496     temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
00497   }
00498   else
00499   {
00500     /* Half Transfer Complete flag */
00501     temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
00502   }
00503
00504   /* Get tick */
00505   tickstart = HAL_GetTick();
00506
00507   while(RESET == (hdma->DmaBaseAddress->ISR & temp))
00508   {
00509     if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))
00510     {
00511       /* When a DMA transfer error occurs */
00512       /* A hardware clear of its EN bits is performed */
00513       /* Clear all flags */
00514       hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
00515
00516       /* Update error code */
00517       hdma->ErrorCode = HAL_DMA_ERROR_TE;
00518
00519       /* Change the DMA state */
00520       hdma->State= HAL_DMA_STATE_READY;
00521
00522       /* Process Unlocked */
00523       __HAL_UNLOCK(hdma);
00524
00525       return HAL_ERROR;
00526     }
00527     /* Check for the Timeout */
00528     if(Timeout != HAL_MAX_DELAY)
00529     {
00530       if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
00531       {
00532         /* Update error code */
00533         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
00534
00535         /* Change the DMA state */
00536         hdma->State = HAL_DMA_STATE_READY;
00537
00538         /* Process Unlocked */
00539         __HAL_UNLOCK(hdma);
00540
00541         return HAL_ERROR;
00542       }
00543     }
00544   }
00545
00546   if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
00547   {
00548     /* Clear the transfer complete flag */
00549     hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
00550
00551     /* The selected Channelx EN bit is cleared (DMA is disabled and
00552     all transfers are complete) */
00553     hdma->State = HAL_DMA_STATE_READY;
00554   }
00555   else
00556   {
00557     /* Clear the half transfer complete flag */
00558     hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
00559   }
00560
00561   /* Process unlocked */
00562   __HAL_UNLOCK(hdma);
00563
00564   return HAL_OK;
00565 }
00566
00567 /**
00568   * @brief  Handle DMA interrupt request.
00569   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00570   *               the configuration information for the specified DMA Channel.
00571   * @retval None
00572   */
00573 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
00574 {
00575         uint32_t flag_it = hdma->DmaBaseAddress->ISR;
00576   uint32_t source_it = hdma->Instance->CCR;
00577
00578   /* Half Transfer Complete Interrupt management ******************************/
00579   if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
00580   {
00581         /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
00582         if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
00583         {
00584                 /* Disable the half transfer interrupt */
00585                 hdma->Instance->CCR &= ~DMA_IT_HT;
00586         }
00587
00588         /* Clear the half transfer complete flag */
00589         hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
00590
00591         /* DMA peripheral state is not updated in Half Transfer */
00592         /* State is updated only in Transfer Complete case */
00593
00594         if(hdma->XferHalfCpltCallback != NULL)
00595         {
00596                 /* Half transfer callback */
00597                 hdma->XferHalfCpltCallback(hdma);
00598         }
00599   }
00600
00601   /* Transfer Complete Interrupt management ***********************************/
00602   else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
00603   {
00604         if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
00605         {
00606                 /* Disable the transfer complete  & transfer error interrupts */
00607                 /* if the DMA mode is not CIRCULAR */
00608                 hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
00609
00610                 /* Change the DMA state */
00611                 hdma->State = HAL_DMA_STATE_READY;
00612         }
00613
00614         /* Clear the transfer complete flag */
00615         hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
00616
00617         /* Process Unlocked */
00618         __HAL_UNLOCK(hdma);
00619
00620         if(hdma->XferCpltCallback != NULL)
00621         {
00622                 /* Transfer complete callback */
00623                 hdma->XferCpltCallback(hdma);
00624         }
00625   }
00626
00627   /* Transfer Error Interrupt management ***************************************/
00628   else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
00629   {
00630         /* When a DMA transfer error occurs */
00631     /* A hardware clear of its EN bits is performed */
00632     /* Then, disable all DMA interrupts */
00633     hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
00634
00635     /* Clear all flags */
00636     hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
00637
00638     /* Update error code */
00639     hdma->ErrorCode = HAL_DMA_ERROR_TE;
00640
00641     /* Change the DMA state */
00642     hdma->State = HAL_DMA_STATE_READY;
00643
00644     /* Process Unlocked */
00645     __HAL_UNLOCK(hdma);
00646
00647     if(hdma->XferErrorCallback != NULL)
00648     {
00649         /* Transfer error callback */
00650         hdma->XferErrorCallback(hdma);
00651     }
00652   }
00653 }
00654
00655 /**
00656   * @brief  Register callbacks
00657   * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
00658   *                               the configuration information for the specified DMA Stream.
00659   * @param  CallbackID           User Callback identifer
00660   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
00661   * @param  pCallback            pointer to private callback function which has pointer to
00662   *                               a DMA_HandleTypeDef structure as parameter.
00663   * @retval HAL status
00664   */
00665 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
00666 {
00667   HAL_StatusTypeDef status = HAL_OK;
00668
00669   /* Process locked */
00670   __HAL_LOCK(hdma);
00671
00672   if(HAL_DMA_STATE_READY == hdma->State)
00673   {
00674     switch (CallbackID)
00675     {
00676      case  HAL_DMA_XFER_CPLT_CB_ID:
00677            hdma->XferCpltCallback = pCallback;
00678            break;
00679
00680      case  HAL_DMA_XFER_HALFCPLT_CB_ID:
00681            hdma->XferHalfCpltCallback = pCallback;
00682            break;
00683
00684      case  HAL_DMA_XFER_ERROR_CB_ID:
00685            hdma->XferErrorCallback = pCallback;
00686            break;
00687
00688      case  HAL_DMA_XFER_ABORT_CB_ID:
00689            hdma->XferAbortCallback = pCallback;
00690            break;
00691
00692      default:
00693            status = HAL_ERROR;
00694            break;
00695     }
00696   }
00697   else
00698   {
00699     status = HAL_ERROR;
00700   }
00701
00702   /* Release Lock */
00703   __HAL_UNLOCK(hdma);
00704
00705   return status;
00706 }
00707
00708 /**
00709   * @brief  UnRegister callbacks
00710   * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
00711   *                               the configuration information for the specified DMA Stream.
00712   * @param  CallbackID           User Callback identifer
00713   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
00714   * @retval HAL status
00715   */
00716 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
00717 {
00718   HAL_StatusTypeDef status = HAL_OK;
00719
00720     /* Process locked */
00721   __HAL_LOCK(hdma);
00722
00723   if(HAL_DMA_STATE_READY == hdma->State)
00724   {
00725     switch (CallbackID)
00726     {
00727      case  HAL_DMA_XFER_CPLT_CB_ID:
00728            hdma->XferCpltCallback = NULL;
00729            break;
00730
00731      case  HAL_DMA_XFER_HALFCPLT_CB_ID:
00732            hdma->XferHalfCpltCallback = NULL;
00733            break;
00734
00735      case  HAL_DMA_XFER_ERROR_CB_ID:
00736            hdma->XferErrorCallback = NULL;
00737            break;
00738
00739      case  HAL_DMA_XFER_ABORT_CB_ID:
00740            hdma->XferAbortCallback = NULL;
00741            break;
00742
00743     case   HAL_DMA_XFER_ALL_CB_ID:
00744            hdma->XferCpltCallback = NULL;
00745            hdma->XferHalfCpltCallback = NULL;
00746            hdma->XferErrorCallback = NULL;
00747            hdma->XferAbortCallback = NULL;
00748            break;
00749
00750     default:
00751            status = HAL_ERROR;
00752            break;
00753     }
00754   }
00755   else
00756   {
00757     status = HAL_ERROR;
00758   }
00759
00760   /* Release Lock */
00761   __HAL_UNLOCK(hdma);
00762
00763   return status;
00764 }
00765
00766 /**
00767   * @}
00768   */
00769
00770 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
00771  *  @brief    Peripheral State functions
00772  *
00773 @verbatim
00774  ===============================================================================
00775                     ##### State and Errors functions #####
00776  ===============================================================================
00777     [..]
00778     This subsection provides functions allowing to
00779       (+) Check the DMA state
00780       (+) Get error code
00781
00782 @endverbatim
00783   * @{
00784   */
00785
00786 /**
00787   * @brief  Returns the DMA state.
00788   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00789   *               the configuration information for the specified DMA Channel.
00790   * @retval HAL state
00791   */
00792 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
00793 {
00794   return hdma->State;
00795 }
00796
00797 /**
00798   * @brief  Return the DMA error code
00799   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00800   *              the configuration information for the specified DMA Channel.
00801   * @retval DMA Error Code
00802   */
00803 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
00804 {
00805   return hdma->ErrorCode;
00806 }
00807
00808 /**
00809   * @}
00810   */
00811
00812 /**
00813   * @}
00814   */
00815
00816 /** @addtogroup DMA_Private_Functions
00817   * @{
00818   */
00819
00820 /**
00821   * @brief  Set the DMA Transfer parameters.
00822   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
00823   *                     the configuration information for the specified DMA Channel.
00824   * @param  SrcAddress The source memory Buffer address
00825   * @param  DstAddress The destination memory Buffer address
00826   * @param  DataLength The length of data to be transferred from source to destination
00827   * @retval HAL status
00828   */
00829 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00830 {
00831         /* Clear all flags */
00832   hdma->DmaBaseAddress->IFCR  = (DMA_FLAG_GL1 << hdma->ChannelIndex);
00833
00834   /* Configure DMA Channel data length */
00835   hdma->Instance->CNDTR = DataLength;
00836
00837   /* Peripheral to Memory */
00838   if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
00839   {
00840     /* Configure DMA Channel destination address */
00841     hdma->Instance->CPAR = DstAddress;
00842
00843     /* Configure DMA Channel source address */
00844     hdma->Instance->CMAR = SrcAddress;
00845   }
00846   /* Memory to Peripheral */
00847   else
00848   {
00849     /* Configure DMA Channel source address */
00850     hdma->Instance->CPAR = SrcAddress;
00851
00852     /* Configure DMA Channel destination address */
00853     hdma->Instance->CMAR = DstAddress;
00854   }
00855 }
00856
00857 /**
00858   * @brief  Set the DMA base address and channel index depending on DMA instance
00859   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
00860   *                     the configuration information for the specified DMA Stream.
00861   * @retval None
00862   */
00863 static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
00864 {
00865 #if defined (DMA2)
00866   /* calculation of the channel index */
00867   if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
00868   {
00869     /* DMA1 */
00870     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
00871     hdma->DmaBaseAddress = DMA1;
00872   }
00873   else
00874   {
00875     /* DMA2 */
00876     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
00877     hdma->DmaBaseAddress = DMA2;
00878   }
00879 #else
00880   /* calculation of the channel index */
00881   /* DMA1 */
00882   hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
00883   hdma->DmaBaseAddress = DMA1;
00884 #endif
00885 }
00886
00887 /**
00888   * @}
00889   */
00890
00891 /**
00892   * @}
00893   */
00894 #endif /* HAL_DMA_MODULE_ENABLED */
00895
00896 /**
00897   * @}
00898   */
00899
00900   /**
00901   * @}
00902   */
00903
00904 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_dma.h Source File

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stm32f3xx_hal_dma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_dma.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_DMA_H
00038 #define __STM32F3xx_HAL_DMA_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup DMA
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056
00057 /** @defgroup DMA_Exported_Types DMA Exported Types
00058   * @{
00059   */
00060
00061 /**
00062   * @brief  DMA Configuration Structure definition
00063   */
00064 typedef struct
00065 {
00066   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
00067                                            from memory to memory or from peripheral to memory.
00068                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
00069
00070   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
00071                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
00072
00073   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
00074                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
00075
00076   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
00077                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
00078
00079   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
00080                                            This parameter can be a value of @ref DMA_Memory_data_size */
00081
00082   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
00083                                            This parameter can be a value of @ref DMA_mode
00084                                            @note The circular buffer mode cannot be used if the memory-to-memory
00085                                            data transfer is configured on the selected Channel */
00086
00087   uint32_t Priority;                   /*!< Specifies the software priority for the DMAy Channelx.
00088                                             This parameter can be a value of @ref DMA_Priority_level */
00089 } DMA_InitTypeDef;
00090
00091 /**
00092   * @brief  HAL DMA State structures definition
00093   */
00094 typedef enum
00095 {
00096   HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
00097   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
00098   HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
00099   HAL_DMA_STATE_TIMEOUT           = 0x03   /*!< DMA timeout state                   */
00100 }HAL_DMA_StateTypeDef;
00101
00102 /**
00103   * @brief  HAL DMA Error Code structure definition
00104   */
00105 typedef enum
00106 {
00107   HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
00108   HAL_DMA_HALF_TRANSFER      = 0x01     /*!< Half Transfer     */
00109 }HAL_DMA_LevelCompleteTypeDef;
00110
00111 /**
00112   * @brief  HAL DMA Callback ID structure definition
00113   */
00114 typedef enum
00115 {
00116   HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
00117   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half transfer     */
00118   HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,    /*!< Error             */
00119   HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,    /*!< Abort             */
00120   HAL_DMA_XFER_ALL_CB_ID           = 0x04     /*!< All               */
00121 }HAL_DMA_CallbackIDTypeDef;
00122
00123 /**
00124   * @brief  DMA handle Structure definition
00125   */
00126 typedef struct __DMA_HandleTypeDef
00127 {
00128   DMA_Channel_TypeDef   *Instance;                                                    /*!< Register base address                  */
00129
00130   DMA_InitTypeDef       Init;                                                         /*!< DMA communication parameters           */
00131
00132   HAL_LockTypeDef       Lock;                                                         /*!< DMA locking object                     */
00133
00134   HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
00135
00136   void                  *Parent;                                                      /*!< Parent object state                    */
00137
00138   void                  (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
00139
00140   void                  (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
00141
00142   void                  (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
00143
00144   void                  (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer abort callback            */
00145
00146   __IO uint32_t         ErrorCode;                                                    /*!< DMA Error code                         */
00147
00148   DMA_TypeDef          *DmaBaseAddress;                                               /*!< DMA Channel Base Address               */
00149
00150   uint32_t              ChannelIndex;                                                 /*!< DMA Channel Index                      */
00151 } DMA_HandleTypeDef;
00152 /**
00153   * @}
00154   */
00155
00156 /* Exported constants --------------------------------------------------------*/
00157
00158 /** @defgroup DMA_Exported_Constants DMA Exported Constants
00159   * @{
00160   */
00161
00162 /** @defgroup DMA_Error_Code DMA Error Code
00163   * @{
00164   */
00165 #define HAL_DMA_ERROR_NONE          (0x00000000U)    /*!< No error             */
00166 #define HAL_DMA_ERROR_TE            (0x00000001U)    /*!< Transfer error       */
00167 #define HAL_DMA_ERROR_NO_XFER       (0x00000004U)    /*!< no ongoin transfer   */
00168 #define HAL_DMA_ERROR_TIMEOUT       (0x00000020U)    /*!< Timeout error        */
00169 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U)    /*!< Not supported mode */
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
00175   * @{
00176   */
00177 #define DMA_PERIPH_TO_MEMORY         (0x00000000U)        /*!< Peripheral to memory direction */
00178 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)       /*!< Memory to peripheral direction */
00179 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM)   /*!< Memory to memory direction     */
00180
00181 /**
00182   * @}
00183   */
00184
00185 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
00186   * @{
00187   */
00188 #define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)  /*!< Peripheral increment mode Enable */
00189 #define DMA_PINC_DISABLE       (0x00000000U)    /*!< Peripheral increment mode Disable */
00190 /**
00191   * @}
00192   */
00193
00194 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
00195   * @{
00196   */
00197 #define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */
00198 #define DMA_MINC_DISABLE        (0x00000000U)    /*!< Memory increment mode Disable */
00199 /**
00200   * @}
00201   */
00202
00203 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
00204   * @{
00205   */
00206 #define DMA_PDATAALIGN_BYTE          (0x00000000U)       /*!< Peripheral data alignment : Byte     */
00207 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment : HalfWord */
00208 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment : Word     */
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup DMA_Memory_data_size DMA Memory data size
00214   * @{
00215   */
00216 #define DMA_MDATAALIGN_BYTE          (0x00000000U)       /*!< Memory data alignment : Byte     */
00217 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment : HalfWord */
00218 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)  /*!< Memory data alignment : Word     */
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup DMA_mode DMA mode
00224   * @{
00225   */
00226 #define DMA_NORMAL         (0x00000000U)      /*!< Normal Mode                  */
00227 #define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)    /*!< Circular Mode                */
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup DMA_Priority_level DMA Priority level
00233   * @{
00234   */
00235 #define DMA_PRIORITY_LOW             (0x00000000U)    /*!< Priority level : Low       */
00236 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)  /*!< Priority level : Medium    */
00237 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)  /*!< Priority level : High      */
00238 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */
00239 /**
00240   * @}
00241   */
00242
00243
00244 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
00245   * @{
00246   */
00247 #define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
00248 #define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
00249 #define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup DMA_flag_definitions DMA flag definitions
00255   * @{
00256   */
00257 #define DMA_FLAG_GL1                      (0x00000001U)
00258 #define DMA_FLAG_TC1                      (0x00000002U)
00259 #define DMA_FLAG_HT1                      (0x00000004U)
00260 #define DMA_FLAG_TE1                      (0x00000008U)
00261 #define DMA_FLAG_GL2                      (0x00000010U)
00262 #define DMA_FLAG_TC2                      (0x00000020U)
00263 #define DMA_FLAG_HT2                      (0x00000040U)
00264 #define DMA_FLAG_TE2                      (0x00000080U)
00265 #define DMA_FLAG_GL3                      (0x00000100U)
00266 #define DMA_FLAG_TC3                      (0x00000200U)
00267 #define DMA_FLAG_HT3                      (0x00000400U)
00268 #define DMA_FLAG_TE3                      (0x00000800U)
00269 #define DMA_FLAG_GL4                      (0x00001000U)
00270 #define DMA_FLAG_TC4                      (0x00002000U)
00271 #define DMA_FLAG_HT4                      (0x00004000U)
00272 #define DMA_FLAG_TE4                      (0x00008000U)
00273 #define DMA_FLAG_GL5                      (0x00010000U)
00274 #define DMA_FLAG_TC5                      (0x00020000U)
00275 #define DMA_FLAG_HT5                      (0x00040000U)
00276 #define DMA_FLAG_TE5                      (0x00080000U)
00277 #define DMA_FLAG_GL6                      (0x00100000U)
00278 #define DMA_FLAG_TC6                      (0x00200000U)
00279 #define DMA_FLAG_HT6                      (0x00400000U)
00280 #define DMA_FLAG_TE6                      (0x00800000U)
00281 #define DMA_FLAG_GL7                      (0x01000000U)
00282 #define DMA_FLAG_TC7                      (0x02000000U)
00283 #define DMA_FLAG_HT7                      (0x04000000U)
00284 #define DMA_FLAG_TE7                      (0x08000000U)
00285 /**
00286   * @}
00287   */
00288
00289 /**
00290   * @}
00291   */
00292
00293
00294 /* Exported macro ------------------------------------------------------------*/
00295 /** @defgroup DMA_Exported_Macros DMA Exported Macros
00296   * @{
00297   */
00298
00299 /** @brief  Reset DMA handle state
00300   * @param  __HANDLE__ DMA handle.
00301   * @retval None
00302   */
00303 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
00304
00305 /**
00306   * @brief  Enable the specified DMA Channel.
00307   * @param  __HANDLE__ DMA handle
00308   * @retval None
00309   */
00310 #define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
00311
00312 /**
00313   * @brief  Disable the specified DMA Channel.
00314   * @param  __HANDLE__ DMA handle
00315   * @retval None
00316   */
00317 #define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
00318
00319
00320 /* Interrupt & Flag management */
00321
00322 /**
00323   * @brief  Enables the specified DMA Channel interrupts.
00324   * @param  __HANDLE__ DMA handle
00325   * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
00326   *          This parameter can be any combination of the following values:
00327   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00328   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00329   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00330   * @retval None
00331   */
00332 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
00333
00334 /**
00335   * @brief  Disables the specified DMA Channel interrupts.
00336   * @param  __HANDLE__ DMA handle
00337   * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
00338   *          This parameter can be any combination of the following values:
00339   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00340   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00341   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00342   * @retval None
00343   */
00344 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
00345
00346 /**
00347   * @brief  Checks whether the specified DMA Channel interrupt is enabled or disabled.
00348   * @param  __HANDLE__ DMA handle
00349   * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
00350   *          This parameter can be one of the following values:
00351   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00352   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00353   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00354   * @retval The state of DMA_IT (SET or RESET).
00355   */
00356 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
00357
00358 /**
00359   * @brief  Returns the number of remaining data units in the current DMAy Channelx transfer.
00360   * @param  __HANDLE__ DMA handle
00361   *
00362   * @retval The number of remaining data units in the current DMA Channel transfer.
00363   */
00364 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
00365
00366 /**
00367   * @}
00368   */
00369
00370 /* Include DMA HAL Extended module */
00371 #include "stm32f3xx_hal_dma_ex.h"
00372
00373 /* Exported functions --------------------------------------------------------*/
00374 /** @addtogroup DMA_Exported_Functions
00375   * @{
00376   */
00377
00378 /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
00379   * @{
00380   */
00381 /* Initialization and de-initialization functions *****************************/
00382 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
00383 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
00384 /**
00385   * @}
00386   */
00387
00388 /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
00389   * @{
00390   */
00391 /* Input and Output operation functions *****************************************************/
00392 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00393 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00394 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
00395 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
00396 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
00397 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
00398 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
00399 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
00400 /**
00401   * @}
00402   */
00403
00404 /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
00405   * @{
00406   */
00407 /* Peripheral State and Error functions ***************************************/
00408 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
00409 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
00410 /**
00411   * @}
00412   */
00413
00414 /**
00415   * @}
00416   */
00417 /* Private macros ------------------------------------------------------------*/
00418 /** @defgroup DMA_Private_Macros DMA Private Macros
00419   * @brief    DMA private macros
00420   * @{
00421   */
00422
00423 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
00424
00425 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
00426                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
00427                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
00428
00429 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
00430                                             ((STATE) == DMA_PINC_DISABLE))
00431
00432 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
00433                                         ((STATE) == DMA_MINC_DISABLE))
00434
00435 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
00436                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
00437                                            ((SIZE) == DMA_PDATAALIGN_WORD))
00438
00439 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
00440                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
00441                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
00442
00443 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
00444                            ((MODE) == DMA_CIRCULAR))
00445
00446 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
00447                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
00448                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
00449                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
00450
00451 /**
00452   * @}
00453   */
00454
00455
00456 /**
00457   * @}
00458   */
00459
00460 /**
00461   * @}
00462   */
00463
00464 #ifdef __cplusplus
00465 }
00466 #endif
00467
00468 #endif /* __STM32F3xx_HAL_DMA_H */
00469
00470 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_dma_ex.h Source File

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stm32f3xx_hal_dma_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_dma_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA HAL extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_DMA_EX_H
00038 #define __STM32F3xx_HAL_DMA_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup DMAEx
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /* Exported constants --------------------------------------------------------*/
00057 /* Exported macro ------------------------------------------------------------*/
00058 /** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
00059   * @{
00060   */
00061 /* Interrupt & Flag management */
00062
00063 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00064     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00065     defined(STM32F373xC) || defined(STM32F378xx)
00066 /**
00067   * @brief  Returns the current DMA Channel transfer complete flag.
00068   * @param  __HANDLE__ DMA handle
00069   * @retval The specified transfer complete flag index.
00070   */
00071 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00072 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
00073  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
00074  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
00075  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
00076  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
00077  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
00078  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
00079  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
00080  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
00081  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
00082  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
00083    DMA_FLAG_TC5)
00084
00085 /**
00086   * @brief  Returns the current DMA Channel half transfer complete flag.
00087   * @param  __HANDLE__ DMA handle
00088   * @retval The specified half transfer complete flag index.
00089   */
00090 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
00091 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
00092  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
00093  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
00094  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
00095  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
00096  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
00097  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
00098  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
00099  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
00100  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
00101  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
00102    DMA_FLAG_HT5)
00103
00104 /**
00105   * @brief  Returns the current DMA Channel transfer error flag.
00106   * @param  __HANDLE__ DMA handle
00107   * @retval The specified transfer error flag index.
00108   */
00109 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
00110 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
00111  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
00112  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
00113  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
00114  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
00115  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
00116  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
00117  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
00118  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
00119  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
00120  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
00121    DMA_FLAG_TE5)
00122
00123 /**
00124   * @brief  Return the current DMA Channel Global interrupt flag.
00125   * @param  __HANDLE__ DMA handle
00126   * @retval The specified transfer error flag index.
00127   */
00128 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
00129 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
00130  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
00131  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
00132  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
00133  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
00134  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
00135  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
00136  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
00137  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
00138  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
00139  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
00140    DMA_FLAG_GL5)
00141
00142 /**
00143   * @brief  Get the DMA Channel pending flags.
00144   * @param  __HANDLE__ DMA handle
00145   * @param  __FLAG__ Get the specified flag.
00146   *          This parameter can be any combination of the following values:
00147   *            @arg DMA_FLAG_TCx:  Transfer complete flag
00148   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
00149   *            @arg DMA_FLAG_TEx:  Transfer error flag
00150   *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
00151   * @retval The state of FLAG (SET or RESET).
00152   */
00153 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
00154 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
00155   (DMA1->ISR & (__FLAG__)))
00156
00157 /**
00158   * @brief  Clears the DMA Channel pending flags.
00159   * @param  __HANDLE__ DMA handle
00160   * @param  __FLAG__ specifies the flag to clear.
00161   *          This parameter can be any combination of the following values:
00162   *            @arg DMA_FLAG_TCx:  Transfer complete flag
00163   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
00164   *            @arg DMA_FLAG_TEx:  Transfer error flag
00165   *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
00166   * @retval None
00167   */
00168 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
00169 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
00170   (DMA1->IFCR = (__FLAG__)))
00171
00172 /**
00173   * @}
00174   */
00175
00176 #else /* STM32F301x8_STM32F302x8_STM32F318xx_STM32F303x8_STM32F334x8_STM32F328xx Product devices */
00177 /** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
00178   * @{
00179   */
00180
00181 /**
00182   * @brief  Returns the current DMA Channel transfer complete flag.
00183   * @param  __HANDLE__ DMA handle
00184   * @retval The specified transfer complete flag index.
00185   */
00186 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00187 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
00188  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
00189  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
00190  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
00191  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
00192  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
00193    DMA_FLAG_TC7)
00194
00195 /**
00196   * @brief  Returns the current DMA Channel half transfer complete flag.
00197   * @param  __HANDLE__ DMA handle
00198   * @retval The specified half transfer complete flag index.
00199   */
00200 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
00201 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
00202  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
00203  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
00204  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
00205  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
00206  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
00207    DMA_FLAG_HT7)
00208
00209 /**
00210   * @brief  Returns the current DMA Channel transfer error flag.
00211   * @param  __HANDLE__ DMA handle
00212   * @retval The specified transfer error flag index.
00213   */
00214 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
00215 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
00216  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
00217  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
00218  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
00219  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
00220  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
00221    DMA_FLAG_TE7)
00222
00223 /**
00224   * @brief  Return the current DMA Channel Global interrupt flag.
00225   * @param  __HANDLE__ DMA handle
00226   * @retval The specified transfer error flag index.
00227   */
00228 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
00229 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
00230  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
00231  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
00232  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
00233  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
00234  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
00235    DMA_FLAG_GL7)
00236
00237 /**
00238   * @brief  Get the DMA Channel pending flags.
00239   * @param  __HANDLE__ DMA handle
00240   * @param  __FLAG__ Get the specified flag.
00241   *          This parameter can be any combination of the following values:
00242   *            @arg DMA_FLAG_TCx:  Transfer complete flag
00243   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
00244   *            @arg DMA_FLAG_TEx:  Transfer error flag
00245   *         Where x can be 1_7 to select the DMA Channel flag.
00246   * @retval The state of FLAG (SET or RESET).
00247   */
00248
00249 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)   (DMA1->ISR & (__FLAG__))
00250
00251 /**
00252   * @brief  Clears the DMA Channel pending flags.
00253   * @param  __HANDLE__ DMA handle
00254   * @param  __FLAG__ specifies the flag to clear.
00255   *          This parameter can be any combination of the following values:
00256   *            @arg DMA_FLAG_TCx:  Transfer complete flag
00257   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
00258   *            @arg DMA_FLAG_TEx:  Transfer error flag
00259   *         Where x can be 1_7 to select the DMA Channel flag.
00260   * @retval None
00261   */
00262 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
00263
00264 /**
00265   * @}
00266   */
00267
00268 #endif
00269
00270 /**
00271   * @}
00272   */
00273
00274 /**
00275   * @}
00276   */
00277
00278 /**
00279   * @}
00280   */
00281
00282 #ifdef __cplusplus
00283 }
00284 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00285        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00286        /* STM32F373xC || STM32F378xx                   */
00287
00288 #endif /* __STM32F3xx_HAL_DMA_H */
00289
00290 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_flash.c Source File

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stm32f3xx_hal_flash.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_flash.c
00004   * @author  MCD Application Team
00005   * @brief   FLASH HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the internal FLASH memory:
00008   *           + Program operations functions
00009   *           + Memory Control functions
00010   *           + Peripheral State functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                         ##### FLASH peripheral features #####
00015   ==============================================================================
00016   [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
00017        to the Flash memory. It implements the erase and program Flash memory operations
00018        and the read and write protection mechanisms.
00019
00020   [..] The Flash memory interface accelerates code execution with a system of instruction
00021       prefetch.
00022
00023   [..] The FLASH main features are:
00024       (+) Flash memory read operations
00025       (+) Flash memory program/erase operations
00026       (+) Read / write protections
00027       (+) Prefetch on I-Code
00028       (+) Option Bytes programming
00029
00030
00031                      ##### How to use this driver #####
00032   ==============================================================================
00033   [..]
00034       This driver provides functions and macros to configure and program the FLASH
00035       memory of all STM32F3xx devices.
00036
00037       (#) FLASH Memory I/O Programming functions: this group includes all needed
00038           functions to erase and program the main memory:
00039         (++) Lock and Unlock the FLASH interface
00040         (++) Erase function: Erase page, erase all pages
00041         (++) Program functions: half word, word and doubleword
00042       (#) FLASH Option Bytes Programming functions: this group includes all needed
00043           functions to manage the Option Bytes:
00044         (++) Lock and Unlock the Option Bytes
00045         (++) Set/Reset the write protection
00046         (++) Set the Read protection Level
00047         (++) Program the user Option Bytes
00048         (++) Launch the Option Bytes loader
00049         (++) Erase Option Bytes
00050         (++) Program the data Option Bytes
00051         (++) Get the Write protection.
00052         (++) Get the user option bytes.
00053
00054       (#) Interrupts and flags management functions : this group
00055           includes all needed functions to:
00056         (++) Handle FLASH interrupts
00057         (++) Wait for last FLASH operation according to its status
00058         (++) Get error flag status
00059
00060   [..] In addition to these function, this driver includes a set of macros allowing
00061        to handle the following operations:
00062
00063       (+) Set/Get the latency
00064       (+) Enable/Disable the prefetch buffer
00065       (+) Enable/Disable the half cycle access
00066       (+) Enable/Disable the FLASH interrupts
00067       (+) Monitor the FLASH flags status
00068
00069   @endverbatim
00070   ******************************************************************************
00071   * @attention
00072   *
00073   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00074   *
00075   * Redistribution and use in source and binary forms, with or without modification,
00076   * are permitted provided that the following conditions are met:
00077   *   1. Redistributions of source code must retain the above copyright notice,
00078   *      this list of conditions and the following disclaimer.
00079   *   2. Redistributions in binary form must reproduce the above copyright notice,
00080   *      this list of conditions and the following disclaimer in the documentation
00081   *      and/or other materials provided with the distribution.
00082   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00083   *      may be used to endorse or promote products derived from this software
00084   *      without specific prior written permission.
00085   *
00086   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00087   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00088   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00089   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00090   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00091   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00092   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00093   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00094   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00095   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00096   *
00097   ******************************************************************************
00098   */
00099
00100 /* Includes ------------------------------------------------------------------*/
00101 #include "stm32f3xx_hal.h"
00102
00103 /** @addtogroup STM32F3xx_HAL_Driver
00104   * @{
00105   */
00106
00107 #ifdef HAL_FLASH_MODULE_ENABLED
00108
00109 /** @defgroup FLASH FLASH
00110   * @brief FLASH HAL module driver
00111   * @{
00112   */
00113
00114 /* Private typedef -----------------------------------------------------------*/
00115 /* Private define ------------------------------------------------------------*/
00116 /** @defgroup FLASH_Private_Constants FLASH Private Constants
00117   * @{
00118   */
00119 /**
00120   * @}
00121   */
00122
00123 /* Private macro ---------------------------- ---------------------------------*/
00124 /** @defgroup FLASH_Private_Macros FLASH Private Macros
00125   * @{
00126   */
00127
00128 /**
00129   * @}
00130   */
00131
00132 /* Private variables ---------------------------------------------------------*/
00133 /** @defgroup FLASH_Private_Variables FLASH Private Variables
00134   * @{
00135   */
00136 /* Variables used for Erase pages under interruption*/
00137 FLASH_ProcessTypeDef pFlash;
00138 /**
00139   * @}
00140   */
00141
00142 /* Private function prototypes -----------------------------------------------*/
00143 /** @defgroup FLASH_Private_Functions FLASH Private Functions
00144   * @{
00145   */
00146 static  void   FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
00147 static  void   FLASH_SetErrorCode(void);
00148 extern void    FLASH_PageErase(uint32_t PageAddress);
00149 /**
00150   * @}
00151   */
00152
00153 /* Exported functions ---------------------------------------------------------*/
00154 /** @defgroup FLASH_Exported_Functions FLASH Exported Functions
00155   * @{
00156   */
00157
00158 /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
00159   *  @brief   Programming operation functions
00160   *
00161 @verbatim
00162 @endverbatim
00163   * @{
00164   */
00165
00166 /**
00167   * @brief  Program halfword, word or double word at a specified address
00168   * @note   The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
00169   *         The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
00170   *
00171   * @note   If an erase and a program operations are requested simultaneously,
00172   *         the erase operation is performed before the program one.
00173   *
00174   * @note   FLASH should be previously erased before new programmation (only exception to this
00175   *         is when 0x0000 is programmed)
00176   *
00177   * @param  TypeProgram   Indicate the way to program at a specified address.
00178   *                       This parameter can be a value of @ref FLASH_Type_Program
00179   * @param  Address       Specifie the address to be programmed.
00180   * @param  Data          Specifie the data to be programmed
00181   *
00182   * @retval HAL_StatusTypeDef HAL Status
00183   */
00184 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
00185 {
00186   HAL_StatusTypeDef status = HAL_ERROR;
00187   uint8_t index = 0U;
00188   uint8_t nbiterations = 0U;
00189
00190   /* Process Locked */
00191   __HAL_LOCK(&pFlash);
00192
00193   /* Check the parameters */
00194   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00195   assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
00196
00197     /* Wait for last operation to be completed */
00198     status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00199
00200   if(status == HAL_OK)
00201   {
00202     if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
00203     {
00204       /* Program halfword (16-bit) at a specified address. */
00205       nbiterations = 1U;
00206     }
00207     else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
00208     {
00209       /* Program word (32-bit = 2*16-bit) at a specified address. */
00210       nbiterations = 2U;
00211     }
00212     else
00213     {
00214       /* Program double word (64-bit = 4*16-bit) at a specified address. */
00215       nbiterations = 4U;
00216     }
00217
00218     for (index = 0U; index < nbiterations; index++)
00219     {
00220       FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
00221
00222         /* Wait for last operation to be completed */
00223         status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00224
00225         /* If the program operation is completed, disable the PG Bit */
00226         CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
00227       /* In case of error, stop programation procedure */
00228       if (status != HAL_OK)
00229       {
00230         break;
00231       }
00232     }
00233   }
00234
00235   /* Process Unlocked */
00236   __HAL_UNLOCK(&pFlash);
00237
00238   return status;
00239 }
00240
00241 /**
00242   * @brief  Program halfword, word or double word at a specified address  with interrupt enabled.
00243   * @note   The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
00244   *         The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
00245   *
00246   * @note   If an erase and a program operations are requested simultaneously,
00247   *         the erase operation is performed before the program one.
00248   *
00249   * @param  TypeProgram  Indicate the way to program at a specified address.
00250   *                      This parameter can be a value of @ref FLASH_Type_Program
00251   * @param  Address      Specifie the address to be programmed.
00252   * @param  Data         Specifie the data to be programmed
00253   *
00254   * @retval HAL_StatusTypeDef HAL Status
00255   */
00256 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
00257 {
00258   HAL_StatusTypeDef status = HAL_OK;
00259
00260   /* Process Locked */
00261   __HAL_LOCK(&pFlash);
00262
00263   /* Check the parameters */
00264   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00265   assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
00266
00267   /* Enable End of FLASH Operation and Error source interrupts */
00268   __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
00269
00270   pFlash.Address = Address;
00271   pFlash.Data = Data;
00272
00273   if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
00274   {
00275     pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
00276     /* Program halfword (16-bit) at a specified address. */
00277     pFlash.DataRemaining = 1U;
00278   }
00279   else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
00280   {
00281     pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
00282     /* Program word (32-bit : 2*16-bit) at a specified address. */
00283     pFlash.DataRemaining = 2U;
00284   }
00285   else
00286   {
00287     pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
00288     /* Program double word (64-bit : 4*16-bit) at a specified address. */
00289     pFlash.DataRemaining = 4U;
00290   }
00291
00292   /* Program halfword (16-bit) at a specified address. */
00293   FLASH_Program_HalfWord(Address, (uint16_t)Data);
00294
00295   return status;
00296 }
00297
00298 /**
00299   * @brief This function handles FLASH interrupt request.
00300   * @retval None
00301   */
00302 void HAL_FLASH_IRQHandler(void)
00303 {
00304   uint32_t addresstmp = 0U;
00305
00306   /* Check FLASH operation error flags */
00307   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
00308   {
00309     /* Return the faulty address */
00310     addresstmp = pFlash.Address;
00311     /* Reset address */
00312     pFlash.Address = 0xFFFFFFFFU;
00313
00314     /* Save the Error code */
00315     FLASH_SetErrorCode();
00316
00317     /* FLASH error interrupt user callback */
00318     HAL_FLASH_OperationErrorCallback(addresstmp);
00319
00320     /* Stop the procedure ongoing */
00321     pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00322   }
00323
00324   /* Check FLASH End of Operation flag  */
00325   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
00326   {
00327     /* Clear FLASH End of Operation pending bit */
00328     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
00329
00330     /* Process can continue only if no error detected */
00331     if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
00332     {
00333       if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
00334       {
00335         /* Nb of pages to erased can be decreased */
00336         pFlash.DataRemaining--;
00337
00338         /* Check if there are still pages to erase */
00339         if(pFlash.DataRemaining != 0U)
00340         {
00341           addresstmp = pFlash.Address;
00342           /*Indicate user which sector has been erased */
00343           HAL_FLASH_EndOfOperationCallback(addresstmp);
00344
00345           /*Increment sector number*/
00346           addresstmp = pFlash.Address + FLASH_PAGE_SIZE;
00347           pFlash.Address = addresstmp;
00348
00349           /* If the erase operation is completed, disable the PER Bit */
00350           CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
00351
00352           FLASH_PageErase(addresstmp);
00353         }
00354         else
00355         {
00356           /* No more pages to Erase, user callback can be called. */
00357           /* Reset Sector and stop Erase pages procedure */
00358           pFlash.Address = addresstmp = 0xFFFFFFFFU;
00359           pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00360           /* FLASH EOP interrupt user callback */
00361           HAL_FLASH_EndOfOperationCallback(addresstmp);
00362         }
00363       }
00364       else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
00365       {
00366         /* Operation is completed, disable the MER Bit */
00367         CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
00368
00369           /* MassErase ended. Return the selected bank */
00370           /* FLASH EOP interrupt user callback */
00371           HAL_FLASH_EndOfOperationCallback(0U);
00372
00373           /* Stop Mass Erase procedure*/
00374           pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00375         }
00376       else
00377       {
00378         /* Nb of 16-bit data to program can be decreased */
00379         pFlash.DataRemaining--;
00380
00381         /* Check if there are still 16-bit data to program */
00382         if(pFlash.DataRemaining != 0U)
00383         {
00384           /* Increment address to 16-bit */
00385           pFlash.Address += 2U;
00386           addresstmp = pFlash.Address;
00387
00388           /* Shift to have next 16-bit data */
00389           pFlash.Data = (pFlash.Data >> 16U);
00390
00391           /* Operation is completed, disable the PG Bit */
00392           CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
00393
00394           /*Program halfword (16-bit) at a specified address.*/
00395           FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
00396         }
00397         else
00398         {
00399           /* Program ended. Return the selected address */
00400           /* FLASH EOP interrupt user callback */
00401           if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
00402           {
00403             HAL_FLASH_EndOfOperationCallback(pFlash.Address);
00404           }
00405           else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
00406           {
00407             HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
00408           }
00409           else
00410           {
00411             HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
00412           }
00413
00414           /* Reset Address and stop Program procedure */
00415           pFlash.Address = 0xFFFFFFFFU;
00416           pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00417         }
00418       }
00419     }
00420   }
00421
00422
00423   if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
00424   {
00425     /* Operation is completed, disable the PG, PER and MER Bits */
00426     CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
00427
00428     /* Disable End of FLASH Operation and Error source interrupts */
00429     __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
00430
00431     /* Process Unlocked */
00432     __HAL_UNLOCK(&pFlash);
00433   }
00434 }
00435
00436 /**
00437   * @brief  FLASH end of operation interrupt callback
00438   * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
00439   *                 - Mass Erase: No return value expected
00440   *                 - Pages Erase: Address of the page which has been erased
00441   *                    (if 0xFFFFFFFF, it means that all the selected pages have been erased)
00442   *                 - Program: Address which was selected for data program
00443   * @retval none
00444   */
00445 __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
00446 {
00447   /* Prevent unused argument(s) compilation warning */
00448   UNUSED(ReturnValue);
00449
00450   /* NOTE : This function Should not be modified, when the callback is needed,
00451             the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
00452    */
00453 }
00454
00455 /**
00456   * @brief  FLASH operation error interrupt callback
00457   * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
00458   *                 - Mass Erase: No return value expected
00459   *                 - Pages Erase: Address of the page which returned an error
00460   *                 - Program: Address which was selected for data program
00461   * @retval none
00462   */
00463 __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
00464 {
00465   /* Prevent unused argument(s) compilation warning */
00466   UNUSED(ReturnValue);
00467
00468   /* NOTE : This function Should not be modified, when the callback is needed,
00469             the HAL_FLASH_OperationErrorCallback could be implemented in the user file
00470    */
00471 }
00472
00473 /**
00474   * @}
00475   */
00476
00477 /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
00478  *  @brief   management functions
00479  *
00480 @verbatim
00481  ===============================================================================
00482                       ##### Peripheral Control functions #####
00483  ===============================================================================
00484     [..]
00485     This subsection provides a set of functions allowing to control the FLASH
00486     memory operations.
00487
00488 @endverbatim
00489   * @{
00490   */
00491
00492 /**
00493   * @brief  Unlock the FLASH control register access
00494   * @retval HAL Status
00495   */
00496 HAL_StatusTypeDef HAL_FLASH_Unlock(void)
00497 {
00498   if (HAL_IS_BIT_SET(FLASH->CR, FLASH_CR_LOCK))
00499   {
00500     /* Authorize the FLASH Registers access */
00501     WRITE_REG(FLASH->KEYR, FLASH_KEY1);
00502     WRITE_REG(FLASH->KEYR, FLASH_KEY2);
00503   }
00504   else
00505   {
00506     return HAL_ERROR;
00507   }
00508
00509   return HAL_OK;
00510 }
00511
00512 /**
00513   * @brief  Locks the FLASH control register access
00514   * @retval HAL Status
00515   */
00516 HAL_StatusTypeDef HAL_FLASH_Lock(void)
00517 {
00518   /* Set the LOCK Bit to lock the FLASH Registers access */
00519   SET_BIT(FLASH->CR, FLASH_CR_LOCK);
00520
00521   return HAL_OK;
00522 }
00523
00524 /**
00525   * @brief  Unlock the FLASH Option Control Registers access.
00526   * @retval HAL Status
00527   */
00528 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
00529 {
00530   if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE))
00531   {
00532     /* Authorizes the Option Byte register programming */
00533     WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
00534     WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
00535   }
00536   else
00537   {
00538     return HAL_ERROR;
00539   }
00540
00541   return HAL_OK;
00542 }
00543
00544 /**
00545   * @brief  Lock the FLASH Option Control Registers access.
00546   * @retval HAL Status
00547   */
00548 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
00549 {
00550   /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
00551   CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
00552
00553   return HAL_OK;
00554 }
00555
00556 /**
00557   * @brief  Launch the option byte loading.
00558   * @note   This function will reset automatically the MCU.
00559   * @retval HAL Status
00560   */
00561 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
00562 {
00563   /* Set the OBL_Launch bit to launch the option byte loading */
00564   SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
00565
00566   /* Wait for last operation to be completed */
00567   return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE));
00568 }
00569
00570 /**
00571   * @}
00572   */
00573
00574 /** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
00575  *  @brief    Peripheral errors functions
00576  *
00577 @verbatim
00578  ===============================================================================
00579                       ##### Peripheral Errors functions #####
00580  ===============================================================================
00581     [..]
00582     This subsection permit to get in run-time errors of  the FLASH peripheral.
00583
00584 @endverbatim
00585   * @{
00586   */
00587
00588 /**
00589   * @brief  Get the specific FLASH error flag.
00590   * @retval FLASH_ErrorCode The returned value can be:
00591   *            @ref FLASH_Error_Codes
00592   */
00593 uint32_t HAL_FLASH_GetError(void)
00594 {
00595    return pFlash.ErrorCode;
00596 }
00597
00598 /**
00599   * @}
00600   */
00601
00602 /**
00603   * @}
00604   */
00605
00606 /** @addtogroup FLASH_Private_Functions
00607  * @{
00608  */
00609
00610 /**
00611   * @brief  Program a half-word (16-bit) at a specified address.
00612   * @param  Address specify the address to be programmed.
00613   * @param  Data    specify the data to be programmed.
00614   * @retval None
00615   */
00616 static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
00617 {
00618   /* Clean the error context */
00619   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00620
00621     /* Proceed to program the new data */
00622     SET_BIT(FLASH->CR, FLASH_CR_PG);
00623
00624   /* Write data in the address */
00625   *(__IO uint16_t*)Address = Data;
00626 }
00627
00628 /**
00629   * @brief  Wait for a FLASH operation to complete.
00630   * @param  Timeout  maximum flash operation timeout
00631   * @retval HAL Status
00632   */
00633 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
00634 {
00635   /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
00636      Even if the FLASH operation fails, the BUSY flag will be reset and an error
00637      flag will be set */
00638
00639   uint32_t tickstart = HAL_GetTick();
00640
00641   while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
00642   {
00643     if (Timeout != HAL_MAX_DELAY)
00644     {
00645       if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
00646       {
00647         return HAL_TIMEOUT;
00648       }
00649     }
00650   }
00651
00652   /* Check FLASH End of Operation flag  */
00653   if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
00654   {
00655     /* Clear FLASH End of Operation pending bit */
00656     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
00657   }
00658
00659   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)  ||
00660      __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
00661   {
00662     /*Save the error code*/
00663     FLASH_SetErrorCode();
00664     return HAL_ERROR;
00665   }
00666
00667   /* There is no error flag set */
00668   return HAL_OK;
00669 }
00670
00671
00672 /**
00673   * @brief  Set the specific FLASH error flag.
00674   * @retval None
00675   */
00676 static void FLASH_SetErrorCode(void)
00677 {
00678   uint32_t flags = 0U;
00679
00680   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
00681   {
00682     pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
00683     flags |= FLASH_FLAG_WRPERR;
00684   }
00685   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
00686   {
00687     pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
00688     flags |= FLASH_FLAG_PGERR;
00689   }
00690   /* Clear FLASH error pending bits */
00691   __HAL_FLASH_CLEAR_FLAG(flags);
00692 }
00693 /**
00694   * @}
00695   */
00696
00697 /**
00698   * @}
00699   */
00700
00701 #endif /* HAL_FLASH_MODULE_ENABLED */
00702
00703 /**
00704   * @}
00705   */
00706
00707 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_flash.h Source File

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stm32f3xx_hal_flash.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_flash.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of Flash HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_FLASH_H
00038 #define __STM32F3xx_HAL_FLASH_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup FLASH
00052   * @{
00053   */
00054
00055 /** @addtogroup FLASH_Private_Constants
00056   * @{
00057   */
00058 #define FLASH_TIMEOUT_VALUE      (50000U) /* 50 s */
00059 /**
00060   * @}
00061   */
00062
00063 /** @addtogroup FLASH_Private_Macros
00064   * @{
00065   */
00066
00067 #define IS_FLASH_TYPEPROGRAM(VALUE)  (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
00068                                       ((VALUE) == FLASH_TYPEPROGRAM_WORD)     || \
00069                                       ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
00070
00071 #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
00072                                        ((__LATENCY__) == FLASH_LATENCY_1) || \
00073                                        ((__LATENCY__) == FLASH_LATENCY_2))
00074
00075 /**
00076   * @}
00077   */
00078
00079 /* Exported types ------------------------------------------------------------*/
00080 /** @defgroup FLASH_Exported_Types FLASH Exported Types
00081   * @{
00082   */
00083
00084 /**
00085   * @brief  FLASH Procedure structure definition
00086   */
00087 typedef enum
00088 {
00089   FLASH_PROC_NONE              = 0U,
00090   FLASH_PROC_PAGEERASE         = 1U,
00091   FLASH_PROC_MASSERASE         = 2U,
00092   FLASH_PROC_PROGRAMHALFWORD   = 3U,
00093   FLASH_PROC_PROGRAMWORD       = 4U,
00094   FLASH_PROC_PROGRAMDOUBLEWORD = 5U
00095 } FLASH_ProcedureTypeDef;
00096
00097 /**
00098   * @brief  FLASH handle Structure definition
00099   */
00100 typedef struct
00101 {
00102   __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
00103
00104   __IO uint32_t               DataRemaining;    /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
00105
00106   __IO uint32_t               Address;          /*!< Internal variable to save address selected for program or erase */
00107
00108   __IO uint64_t               Data;             /*!< Internal variable to save data to be programmed */
00109
00110   HAL_LockTypeDef             Lock;             /*!< FLASH locking object                */
00111
00112   __IO uint32_t               ErrorCode;        /*!< FLASH error code
00113                                                      This parameter can be a value of @ref FLASH_Error_Codes  */
00114 } FLASH_ProcessTypeDef;
00115
00116 /**
00117   * @}
00118   */
00119
00120 /* Exported constants --------------------------------------------------------*/
00121 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
00122   * @{
00123   */
00124
00125 /** @defgroup FLASH_Error_Codes FLASH Error Codes
00126   * @{
00127   */
00128
00129 #define HAL_FLASH_ERROR_NONE      0x00U  /*!< No error */
00130 #define HAL_FLASH_ERROR_PROG      0x01U  /*!< Programming error */
00131 #define HAL_FLASH_ERROR_WRP       0x02U  /*!< Write protection error */
00132
00133 /**
00134   * @}
00135   */
00136
00137 /** @defgroup FLASH_Type_Program FLASH Type Program
00138   * @{
00139   */
00140 #define FLASH_TYPEPROGRAM_HALFWORD   (0x01U)  /*!<Program a half-word (16-bit) at a specified address.*/
00141 #define FLASH_TYPEPROGRAM_WORD       (0x02U)  /*!<Program a word (32-bit) at a specified address.*/
00142 #define FLASH_TYPEPROGRAM_DOUBLEWORD (0x03U)  /*!<Program a double word (64-bit) at a specified address*/
00143
00144 /**
00145   * @}
00146   */
00147
00148 /** @defgroup FLASH_Latency FLASH Latency
00149   * @{
00150   */
00151 #define FLASH_LATENCY_0            (0x00000000U)    /*!< FLASH Zero Latency cycle */
00152 #define FLASH_LATENCY_1            FLASH_ACR_LATENCY_0       /*!< FLASH One Latency cycle */
00153 #define FLASH_LATENCY_2            FLASH_ACR_LATENCY_1       /*!< FLASH Two Latency cycles */
00154
00155 /**
00156   * @}
00157   */
00158
00159
00160 /** @defgroup FLASH_Flag_definition FLASH Flag definition
00161   * @{
00162   */
00163 #define FLASH_FLAG_BSY             FLASH_SR_BSY            /*!< FLASH Busy flag                           */
00164 #define FLASH_FLAG_PGERR           FLASH_SR_PGERR          /*!< FLASH Programming error flag    */
00165 #define FLASH_FLAG_WRPERR          FLASH_SR_WRPERR         /*!< FLASH Write protected error flag          */
00166 #define FLASH_FLAG_EOP             FLASH_SR_EOP            /*!< FLASH End of Operation flag               */
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
00172   * @{
00173   */
00174 #define FLASH_IT_EOP               FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */
00175 #define FLASH_IT_ERR               FLASH_CR_ERRIE  /*!< Error Interrupt source */
00176 /**
00177   * @}
00178   */
00179
00180 /**
00181   * @}
00182   */
00183
00184 /* Exported macro ------------------------------------------------------------*/
00185
00186 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
00187  *  @brief macros to control FLASH features
00188  *  @{
00189  */
00190
00191 /** @defgroup FLASH_Half_Cycle FLASH Half Cycle
00192  *  @brief macros to handle FLASH half cycle
00193  * @{
00194  */
00195
00196 /**
00197   * @brief  Enable the FLASH half cycle access.
00198   * @retval None
00199   */
00200 #define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE()  (FLASH->ACR |= FLASH_ACR_HLFCYA)
00201
00202 /**
00203   * @brief  Disable the FLASH half cycle access.
00204   * @retval None
00205   */
00206 #define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
00207
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup FLASH_EM_Latency FLASH Latency
00213  *  @brief macros to handle FLASH Latency
00214  * @{
00215  */
00216
00217 /**
00218   * @brief  Set the FLASH Latency.
00219   * @param  __LATENCY__ FLASH Latency
00220   *         This parameter can be one of the following values:
00221   *         @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
00222   *         @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
00223   *         @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles
00224   * @retval None
00225   */
00226 #define __HAL_FLASH_SET_LATENCY(__LATENCY__)    (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
00227
00228
00229 /**
00230   * @brief  Get the FLASH Latency.
00231   * @retval FLASH Latency
00232   *         This parameter can be one of the following values:
00233   *         @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
00234   *         @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
00235   *         @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles
00236   */
00237 #define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
00238
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup FLASH_Prefetch FLASH Prefetch
00244  *  @brief macros to handle FLASH Prefetch buffer
00245  * @{
00246  */
00247 /**
00248   * @brief  Enable the FLASH prefetch buffer.
00249   * @retval None
00250   */
00251 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    (FLASH->ACR |= FLASH_ACR_PRFTBE)
00252
00253 /**
00254   * @brief  Disable the FLASH prefetch buffer.
00255   * @retval None
00256   */
00257 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
00258
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup FLASH_Interrupt FLASH Interrupts
00264  *  @brief macros to handle FLASH interrupts
00265  * @{
00266  */
00267
00268 /**
00269   * @brief  Enable the specified FLASH interrupt.
00270   * @param  __INTERRUPT__  FLASH interrupt
00271   *         This parameter can be any combination of the following values:
00272   *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
00273   *     @arg @ref FLASH_IT_ERR Error Interrupt
00274   * @retval none
00275   */
00276 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  SET_BIT((FLASH->CR), (__INTERRUPT__))
00277
00278 /**
00279   * @brief  Disable the specified FLASH interrupt.
00280   * @param  __INTERRUPT__  FLASH interrupt
00281   *         This parameter can be any combination of the following values:
00282   *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
00283   *     @arg @ref FLASH_IT_ERR Error Interrupt
00284   * @retval none
00285   */
00286 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__))
00287
00288 /**
00289   * @brief  Get the specified FLASH flag status.
00290   * @param  __FLAG__ specifies the FLASH flag to check.
00291   *          This parameter can be one of the following values:
00292   *            @arg @ref FLASH_FLAG_BSY         FLASH Busy flag
00293   *            @arg @ref FLASH_FLAG_EOP         FLASH End of Operation flag
00294   *            @arg @ref FLASH_FLAG_WRPERR      FLASH Write protected error flag
00295   *            @arg @ref FLASH_FLAG_PGERR       FLASH Programming error flag
00296   * @retval The new state of __FLAG__ (SET or RESET).
00297   */
00298 #define __HAL_FLASH_GET_FLAG(__FLAG__)   (((FLASH->SR) & (__FLAG__)) == (__FLAG__))
00299
00300 /**
00301   * @brief  Clear the specified FLASH flag.
00302   * @param  __FLAG__ specifies the FLASH flags to clear.
00303   *          This parameter can be any combination of the following values:
00304   *            @arg @ref FLASH_FLAG_EOP         FLASH End of Operation flag
00305   *            @arg @ref FLASH_FLAG_WRPERR      FLASH Write protected error flag
00306   *            @arg @ref FLASH_FLAG_PGERR       FLASH Programming error flag
00307   * @retval none
00308   */
00309 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   ((FLASH->SR) = (__FLAG__))
00310
00311 /**
00312   * @}
00313   */
00314
00315 /**
00316   * @}
00317   */
00318
00319 /* Include FLASH HAL Extended module */
00320 #include "stm32f3xx_hal_flash_ex.h"
00321
00322 /* Exported functions --------------------------------------------------------*/
00323 /** @addtogroup FLASH_Exported_Functions
00324   * @{
00325   */
00326
00327 /** @addtogroup FLASH_Exported_Functions_Group1
00328   * @{
00329   */
00330 /* IO operation functions *****************************************************/
00331 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
00332 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
00333
00334 /* FLASH IRQ handler function */
00335 void       HAL_FLASH_IRQHandler(void);
00336 /* Callbacks in non blocking modes */
00337 void       HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
00338 void       HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
00339
00340 /**
00341   * @}
00342   */
00343
00344 /** @addtogroup FLASH_Exported_Functions_Group2
00345   * @{
00346   */
00347 /* Peripheral Control functions ***********************************************/
00348 HAL_StatusTypeDef HAL_FLASH_Unlock(void);
00349 HAL_StatusTypeDef HAL_FLASH_Lock(void);
00350 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
00351 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
00352 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
00353
00354 /**
00355   * @}
00356   */
00357
00358 /** @addtogroup FLASH_Exported_Functions_Group3
00359   * @{
00360   */
00361 /* Peripheral State and Error functions ***************************************/
00362 uint32_t HAL_FLASH_GetError(void);
00363
00364 /**
00365   * @}
00366   */
00367
00368 /**
00369   * @}
00370   */
00371
00372 /* Private function -------------------------------------------------*/
00373 /** @addtogroup FLASH_Private_Functions
00374  * @{
00375  */
00376 HAL_StatusTypeDef       FLASH_WaitForLastOperation(uint32_t Timeout);
00377
00378 /**
00379   * @}
00380   */
00381
00382 /**
00383   * @}
00384   */
00385
00386 /**
00387   * @}
00388   */
00389
00390 #ifdef __cplusplus
00391 }
00392 #endif
00393
00394 #endif /* __STM32F3xx_HAL_FLASH_H */
00395
00396 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00397
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_flash_ex.c Source File

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stm32f3xx_hal_flash_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_flash_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended FLASH HAL module driver.
00006   *
00007   *          This file provides firmware functions to manage the following
00008   *          functionalities of the FLASH peripheral:
00009   *           + Extended Initialization/de-initialization functions
00010   *           + Extended I/O operation functions
00011   *           + Extended Peripheral Control functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                ##### Flash peripheral extended features  #####
00016   ==============================================================================
00017
00018                       ##### How to use this driver #####
00019   ==============================================================================
00020   [..] This driver provides functions to configure and program the FLASH memory
00021        of all STM32F3xxx devices. It includes
00022
00023         (++) Set/Reset the write protection
00024         (++) Program the user Option Bytes
00025         (++) Get the Read protection Level
00026
00027   @endverbatim
00028   ******************************************************************************
00029   * @attention
00030   *
00031   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00032   *
00033   * Redistribution and use in source and binary forms, with or without modification,
00034   * are permitted provided that the following conditions are met:
00035   *   1. Redistributions of source code must retain the above copyright notice,
00036   *      this list of conditions and the following disclaimer.
00037   *   2. Redistributions in binary form must reproduce the above copyright notice,
00038   *      this list of conditions and the following disclaimer in the documentation
00039   *      and/or other materials provided with the distribution.
00040   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00041   *      may be used to endorse or promote products derived from this software
00042   *      without specific prior written permission.
00043   *
00044   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00045   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00046   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00047   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00048   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00049   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00050   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00051   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00052   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00053   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00054   *
00055   ******************************************************************************
00056   */
00057
00058 /* Includes ------------------------------------------------------------------*/
00059 #include "stm32f3xx_hal.h"
00060
00061 /** @addtogroup STM32F3xx_HAL_Driver
00062   * @{
00063   */
00064 #ifdef HAL_FLASH_MODULE_ENABLED
00065
00066 /** @addtogroup FLASH
00067   * @{
00068   */
00069 /** @addtogroup FLASH_Private_Variables
00070  * @{
00071  */
00072 /* Variables used for Erase pages under interruption*/
00073 extern FLASH_ProcessTypeDef pFlash;
00074 /**
00075   * @}
00076   */
00077
00078 /**
00079   * @}
00080   */
00081
00082 /** @defgroup FLASHEx FLASHEx
00083   * @brief FLASH HAL Extension module driver
00084   * @{
00085   */
00086
00087 /* Private typedef -----------------------------------------------------------*/
00088 /* Private define ------------------------------------------------------------*/
00089 /** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
00090  * @{
00091  */
00092 #define FLASH_POSITION_IWDGSW_BIT        (uint32_t)POSITION_VAL(FLASH_OBR_IWDG_SW)
00093 #define FLASH_POSITION_OB_USERDATA0_BIT  (uint32_t)POSITION_VAL(FLASH_OBR_DATA0)
00094 #define FLASH_POSITION_OB_USERDATA1_BIT  (uint32_t)POSITION_VAL(FLASH_OBR_DATA1)
00095 /**
00096   * @}
00097   */
00098
00099 /* Private macro -------------------------------------------------------------*/
00100 /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
00101   * @{
00102   */
00103 /**
00104   * @}
00105   */
00106
00107 /* Private variables ---------------------------------------------------------*/
00108 /* Private function prototypes -----------------------------------------------*/
00109 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
00110  * @{
00111  */
00112 /* Erase operations */
00113 static void              FLASH_MassErase(void);
00114 void    FLASH_PageErase(uint32_t PageAddress);
00115
00116 /* Option bytes control */
00117 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
00118 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);
00119 static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);
00120 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
00121 static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
00122 static uint32_t          FLASH_OB_GetWRP(void);
00123 static uint32_t          FLASH_OB_GetRDP(void);
00124 static uint8_t           FLASH_OB_GetUser(void);
00125
00126 /**
00127   * @}
00128   */
00129
00130 /* Exported functions ---------------------------------------------------------*/
00131 /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
00132   * @{
00133   */
00134
00135 /** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions
00136  *  @brief   FLASH Memory Erasing functions
00137   *
00138 @verbatim
00139   ==============================================================================
00140                 ##### FLASH Erasing Programming functions #####
00141   ==============================================================================
00142
00143     [..] The FLASH Memory Erasing functions, includes the following functions:
00144     (+) @ref HAL_FLASHEx_Erase: return only when erase has been done
00145     (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback
00146         is called with parameter 0xFFFFFFFF
00147
00148     [..] Any operation of erase should follow these steps:
00149     (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and
00150         program memory access.
00151     (#) Call the desired function to erase page.
00152     (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access
00153        (recommended to protect the FLASH memory against possible unwanted operation).
00154
00155 @endverbatim
00156   * @{
00157   */
00158
00159
00160 /**
00161   * @brief  Perform a mass erase or erase the specified FLASH memory pages
00162   * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
00163   *         must be called before.
00164   *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access
00165   *         (recommended to protect the FLASH memory against possible unwanted operation)
00166   * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
00167   *         contains the configuration information for the erasing.
00168   *
00169   * @param[out]  PageError pointer to variable  that
00170   *         contains the configuration information on faulty page in case of error
00171   *         (0xFFFFFFFF means that all the pages have been correctly erased)
00172   *
00173   * @retval HAL_StatusTypeDef HAL Status
00174   */
00175 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
00176 {
00177   HAL_StatusTypeDef status = HAL_ERROR;
00178   uint32_t address = 0U;
00179
00180   /* Process Locked */
00181   __HAL_LOCK(&pFlash);
00182
00183   /* Check the parameters */
00184   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00185
00186   if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00187   {
00188       /* Mass Erase requested for Bank1 */
00189       /* Wait for last operation to be completed */
00190       if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
00191       {
00192         /*Mass erase to be done*/
00193         FLASH_MassErase();
00194
00195         /* Wait for last operation to be completed */
00196         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00197
00198         /* If the erase operation is completed, disable the MER Bit */
00199         CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
00200       }
00201   }
00202   else
00203   {
00204     /* Page Erase is requested */
00205     /* Check the parameters */
00206     assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
00207     assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
00208
00209       /* Page Erase requested on address located on bank1 */
00210       /* Wait for last operation to be completed */
00211       if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
00212       {
00213         /*Initialization of PageError variable*/
00214         *PageError = 0xFFFFFFFFU;
00215
00216         /* Erase page by page to be done*/
00217         for(address = pEraseInit->PageAddress;
00218             address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
00219             address += FLASH_PAGE_SIZE)
00220         {
00221           FLASH_PageErase(address);
00222
00223           /* Wait for last operation to be completed */
00224           status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00225
00226           /* If the erase operation is completed, disable the PER Bit */
00227           CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
00228
00229           if (status != HAL_OK)
00230           {
00231             /* In case of error, stop erase procedure and return the faulty address */
00232             *PageError = address;
00233             break;
00234           }
00235         }
00236       }
00237   }
00238
00239   /* Process Unlocked */
00240   __HAL_UNLOCK(&pFlash);
00241
00242   return status;
00243 }
00244
00245 /**
00246   * @brief  Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled
00247   * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
00248   *         must be called before.
00249   *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access
00250   *         (recommended to protect the FLASH memory against possible unwanted operation)
00251   * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
00252   *         contains the configuration information for the erasing.
00253   *
00254   * @retval HAL_StatusTypeDef HAL Status
00255   */
00256 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
00257 {
00258   HAL_StatusTypeDef status = HAL_OK;
00259
00260   /* Process Locked */
00261   __HAL_LOCK(&pFlash);
00262
00263   /* If procedure already ongoing, reject the next one */
00264   if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
00265   {
00266     return HAL_ERROR;
00267   }
00268
00269   /* Check the parameters */
00270   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00271
00272   /* Enable End of FLASH Operation and Error source interrupts */
00273   __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
00274
00275   if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00276   {
00277     /*Mass erase to be done*/
00278     pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
00279         FLASH_MassErase();
00280   }
00281   else
00282   {
00283     /* Erase by page to be done*/
00284
00285     /* Check the parameters */
00286     assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
00287     assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
00288
00289     pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
00290     pFlash.DataRemaining = pEraseInit->NbPages;
00291     pFlash.Address = pEraseInit->PageAddress;
00292
00293     /*Erase 1st page and wait for IT*/
00294     FLASH_PageErase(pEraseInit->PageAddress);
00295   }
00296
00297   return status;
00298 }
00299
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
00305  *  @brief   Option Bytes Programming functions
00306   *
00307 @verbatim
00308   ==============================================================================
00309                 ##### Option Bytes Programming functions #####
00310   ==============================================================================
00311     [..]
00312     This subsection provides a set of functions allowing to control the FLASH
00313     option bytes operations.
00314
00315 @endverbatim
00316   * @{
00317   */
00318
00319 /**
00320   * @brief  Erases the FLASH option bytes.
00321   * @note   This functions erases all option bytes except the Read protection (RDP).
00322   *         The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
00323   *         The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
00324   *         The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
00325   *         (system reset will occur)
00326   * @retval HAL status
00327   */
00328
00329 HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
00330 {
00331   uint8_t rdptmp = OB_RDP_LEVEL_0;
00332   HAL_StatusTypeDef status = HAL_ERROR;
00333
00334   /* Get the actual read protection Option Byte value */
00335   rdptmp = FLASH_OB_GetRDP();
00336
00337   /* Wait for last operation to be completed */
00338   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00339
00340   if(status == HAL_OK)
00341   {
00342     /* Clean the error context */
00343     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00344
00345     /* If the previous operation is completed, proceed to erase the option bytes */
00346     SET_BIT(FLASH->CR, FLASH_CR_OPTER);
00347     SET_BIT(FLASH->CR, FLASH_CR_STRT);
00348
00349     /* Wait for last operation to be completed */
00350     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00351
00352     /* If the erase operation is completed, disable the OPTER Bit */
00353     CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
00354
00355     if(status == HAL_OK)
00356     {
00357       /* Restore the last read protection Option Byte value */
00358       status = FLASH_OB_RDP_LevelConfig(rdptmp);
00359     }
00360   }
00361
00362   /* Return the erase status */
00363   return status;
00364 }
00365
00366 /**
00367   * @brief  Program option bytes
00368   * @note   The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
00369   *         The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
00370   *         The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
00371   *         (system reset will occur)
00372   *
00373   * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
00374   *         contains the configuration information for the programming.
00375   *
00376   * @retval HAL_StatusTypeDef HAL Status
00377   */
00378 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
00379 {
00380   HAL_StatusTypeDef status = HAL_ERROR;
00381
00382   /* Process Locked */
00383   __HAL_LOCK(&pFlash);
00384
00385   /* Check the parameters */
00386   assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
00387
00388   /* Write protection configuration */
00389   if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
00390   {
00391     assert_param(IS_WRPSTATE(pOBInit->WRPState));
00392     if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
00393     {
00394       /* Enable of Write protection on the selected page */
00395       status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
00396     }
00397     else
00398     {
00399       /* Disable of Write protection on the selected page */
00400       status = FLASH_OB_DisableWRP(pOBInit->WRPPage);
00401     }
00402     if (status != HAL_OK)
00403     {
00404       /* Process Unlocked */
00405       __HAL_UNLOCK(&pFlash);
00406       return status;
00407     }
00408   }
00409
00410   /* Read protection configuration */
00411   if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
00412   {
00413     status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
00414     if (status != HAL_OK)
00415     {
00416       /* Process Unlocked */
00417       __HAL_UNLOCK(&pFlash);
00418       return status;
00419     }
00420   }
00421
00422   /* USER configuration */
00423   if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
00424   {
00425     status = FLASH_OB_UserConfig(pOBInit->USERConfig);
00426     if (status != HAL_OK)
00427     {
00428       /* Process Unlocked */
00429       __HAL_UNLOCK(&pFlash);
00430       return status;
00431     }
00432   }
00433
00434   /* DATA configuration*/
00435   if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)
00436   {
00437     status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);
00438     if (status != HAL_OK)
00439     {
00440       /* Process Unlocked */
00441       __HAL_UNLOCK(&pFlash);
00442       return status;
00443     }
00444   }
00445
00446   /* Process Unlocked */
00447   __HAL_UNLOCK(&pFlash);
00448
00449   return status;
00450 }
00451
00452 /**
00453   * @brief  Get the Option byte configuration
00454   * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
00455   *         contains the configuration information for the programming.
00456   *
00457   * @retval None
00458   */
00459 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
00460 {
00461   pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;
00462
00463   /*Get WRP*/
00464   pOBInit->WRPPage = FLASH_OB_GetWRP();
00465
00466   /*Get RDP Level*/
00467   pOBInit->RDPLevel = FLASH_OB_GetRDP();
00468
00469   /*Get USER*/
00470   pOBInit->USERConfig = FLASH_OB_GetUser();
00471 }
00472
00473 /**
00474   * @brief  Get the Option byte user data
00475   * @param  DATAAdress Address of the option byte DATA
00476   *          This parameter can be one of the following values:
00477   *            @arg @ref OB_DATA_ADDRESS_DATA0
00478   *            @arg @ref OB_DATA_ADDRESS_DATA1
00479   * @retval Value programmed in USER data
00480   */
00481 uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
00482 {
00483   uint32_t value = 0U;
00484
00485   if (DATAAdress == OB_DATA_ADDRESS_DATA0)
00486   {
00487     /* Get value programmed in OB USER Data0 */
00488     value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT;
00489   }
00490   else
00491   {
00492     /* Get value programmed in OB USER Data1 */
00493     value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT;
00494   }
00495
00496   return value;
00497 }
00498
00499 /**
00500   * @}
00501   */
00502
00503 /**
00504   * @}
00505   */
00506
00507 /** @addtogroup FLASHEx_Private_Functions
00508  * @{
00509  */
00510
00511 /**
00512   * @brief  Full erase of FLASH memory Bank
00513   *
00514   * @retval None
00515   */
00516 static void FLASH_MassErase(void)
00517 {
00518   /* Clean the error context */
00519   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00520
00521     /* Only bank1 will be erased*/
00522     SET_BIT(FLASH->CR, FLASH_CR_MER);
00523     SET_BIT(FLASH->CR, FLASH_CR_STRT);
00524 }
00525
00526 /**
00527   * @brief  Enable the write protection of the desired pages
00528   * @note   An option byte erase is done automatically in this function.
00529   * @note   When the memory read protection level is selected (RDP level = 1),
00530   *         it is not possible to program or erase the flash page i if
00531   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
00532   *
00533   * @param  WriteProtectPage specifies the page(s) to be write protected.
00534   *         The value of this parameter depend on device used within the same series
00535   * @retval HAL status
00536   */
00537 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
00538 {
00539   HAL_StatusTypeDef status = HAL_OK;
00540   uint16_t WRP0_Data = 0xFFFFU;
00541 #if defined(OB_WRP1_WRP1)
00542   uint16_t WRP1_Data = 0xFFFFU;
00543 #endif /* OB_WRP1_WRP1 */
00544 #if defined(OB_WRP2_WRP2)
00545   uint16_t WRP2_Data = 0xFFFFU;
00546 #endif /* OB_WRP2_WRP2 */
00547 #if defined(OB_WRP3_WRP3)
00548   uint16_t WRP3_Data = 0xFFFFU;
00549 #endif /* OB_WRP3_WRP3 */
00550
00551   /* Check the parameters */
00552   assert_param(IS_OB_WRP(WriteProtectPage));
00553
00554   /* Get current write protected pages and the new pages to be protected ******/
00555   WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage));
00556
00557 #if defined(OB_WRP_PAGES0TO15MASK)
00558   WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
00559 #endif /* OB_WRP_PAGES0TO31MASK */
00560
00561 #if defined(OB_WRP_PAGES16TO31MASK)
00562   WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
00563 #endif /* OB_WRP_PAGES32TO63MASK */
00564
00565 #if defined(OB_WRP_PAGES32TO47MASK)
00566   WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
00567 #endif /* OB_WRP_PAGES32TO47MASK */
00568
00569 #if defined(OB_WRP_PAGES48TO127MASK)
00570   WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
00571 #elif defined(OB_WRP_PAGES48TO255MASK)
00572   WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
00573 #endif /* OB_WRP_PAGES48TO63MASK */
00574
00575   /* Wait for last operation to be completed */
00576   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00577
00578   if(status == HAL_OK)
00579   {
00580     /* Clean the error context */
00581     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00582
00583     /* To be able to write again option byte, need to perform a option byte erase */
00584     status = HAL_FLASHEx_OBErase();
00585     if (status == HAL_OK)
00586     {
00587       /* Enable write protection */
00588       SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
00589
00590 #if defined(OB_WRP0_WRP0)
00591       if(WRP0_Data != 0xFFU)
00592       {
00593         OB->WRP0 &= WRP0_Data;
00594
00595         /* Wait for last operation to be completed */
00596         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00597       }
00598 #endif /* OB_WRP0_WRP0 */
00599
00600 #if defined(OB_WRP1_WRP1)
00601       if((status == HAL_OK) && (WRP1_Data != 0xFFU))
00602       {
00603         OB->WRP1 &= WRP1_Data;
00604
00605         /* Wait for last operation to be completed */
00606         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00607       }
00608 #endif /* OB_WRP1_WRP1 */
00609
00610 #if defined(OB_WRP2_WRP2)
00611       if((status == HAL_OK) && (WRP2_Data != 0xFFU))
00612       {
00613         OB->WRP2 &= WRP2_Data;
00614
00615         /* Wait for last operation to be completed */
00616         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00617       }
00618 #endif /* OB_WRP2_WRP2 */
00619
00620 #if defined(OB_WRP3_WRP3)
00621       if((status == HAL_OK) && (WRP3_Data != 0xFFU))
00622       {
00623         OB->WRP3 &= WRP3_Data;
00624
00625         /* Wait for last operation to be completed */
00626         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00627       }
00628 #endif /* OB_WRP3_WRP3 */
00629
00630       /* if the program operation is completed, disable the OPTPG Bit */
00631       CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
00632     }
00633   }
00634
00635   return status;
00636 }
00637
00638 /**
00639   * @brief  Disable the write protection of the desired pages
00640   * @note   An option byte erase is done automatically in this function.
00641   * @note   When the memory read protection level is selected (RDP level = 1),
00642   *         it is not possible to program or erase the flash page i if
00643   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
00644   *
00645   * @param  WriteProtectPage specifies the page(s) to be write unprotected.
00646   *         The value of this parameter depend on device used within the same series
00647   * @retval HAL status
00648   */
00649 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
00650 {
00651   HAL_StatusTypeDef status = HAL_OK;
00652   uint16_t WRP0_Data = 0xFFFFU;
00653 #if defined(OB_WRP1_WRP1)
00654   uint16_t WRP1_Data = 0xFFFFU;
00655 #endif /* OB_WRP1_WRP1 */
00656 #if defined(OB_WRP2_WRP2)
00657   uint16_t WRP2_Data = 0xFFFFU;
00658 #endif /* OB_WRP2_WRP2 */
00659 #if defined(OB_WRP3_WRP3)
00660   uint16_t WRP3_Data = 0xFFFFU;
00661 #endif /* OB_WRP3_WRP3 */
00662
00663   /* Check the parameters */
00664   assert_param(IS_OB_WRP(WriteProtectPage));
00665
00666   /* Get current write protected pages and the new pages to be unprotected ******/
00667   WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage);
00668
00669 #if defined(OB_WRP_PAGES0TO15MASK)
00670   WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
00671 #endif /* OB_WRP_PAGES0TO31MASK */
00672
00673 #if defined(OB_WRP_PAGES16TO31MASK)
00674   WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
00675 #endif /* OB_WRP_PAGES32TO63MASK */
00676
00677 #if defined(OB_WRP_PAGES32TO47MASK)
00678   WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
00679 #endif /* OB_WRP_PAGES32TO47MASK */
00680
00681 #if defined(OB_WRP_PAGES48TO127MASK)
00682   WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
00683 #elif defined(OB_WRP_PAGES48TO255MASK)
00684   WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
00685 #endif /* OB_WRP_PAGES48TO63MASK */
00686
00687
00688   /* Wait for last operation to be completed */
00689   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00690
00691   if(status == HAL_OK)
00692   {
00693     /* Clean the error context */
00694     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00695
00696     /* To be able to write again option byte, need to perform a option byte erase */
00697     status = HAL_FLASHEx_OBErase();
00698     if (status == HAL_OK)
00699     {
00700       SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
00701
00702 #if defined(OB_WRP0_WRP0)
00703       if(WRP0_Data != 0xFFU)
00704       {
00705         OB->WRP0 |= WRP0_Data;
00706
00707         /* Wait for last operation to be completed */
00708         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00709       }
00710 #endif /* OB_WRP0_WRP0 */
00711
00712 #if defined(OB_WRP1_WRP1)
00713       if((status == HAL_OK) && (WRP1_Data != 0xFFU))
00714       {
00715         OB->WRP1 |= WRP1_Data;
00716
00717         /* Wait for last operation to be completed */
00718         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00719       }
00720 #endif /* OB_WRP1_WRP1 */
00721
00722 #if defined(OB_WRP2_WRP2)
00723       if((status == HAL_OK) && (WRP2_Data != 0xFFU))
00724       {
00725         OB->WRP2 |= WRP2_Data;
00726
00727         /* Wait for last operation to be completed */
00728         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00729       }
00730 #endif /* OB_WRP2_WRP2 */
00731
00732 #if defined(OB_WRP3_WRP3)
00733       if((status == HAL_OK) && (WRP3_Data != 0xFFU))
00734       {
00735         OB->WRP3 |= WRP3_Data;
00736
00737         /* Wait for last operation to be completed */
00738         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00739       }
00740 #endif /* OB_WRP3_WRP3 */
00741
00742       /* if the program operation is completed, disable the OPTPG Bit */
00743       CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
00744     }
00745   }
00746   return status;
00747 }
00748
00749 /**
00750   * @brief  Set the read protection level.
00751   * @param  ReadProtectLevel specifies the read protection level.
00752   *         This parameter can be one of the following values:
00753   *            @arg @ref OB_RDP_LEVEL_0 No protection
00754   *            @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
00755   *            @arg @ref OB_RDP_LEVEL_2 Full chip protection
00756   * @note   Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
00757   * @retval HAL status
00758   */
00759 static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
00760 {
00761   HAL_StatusTypeDef status = HAL_OK;
00762
00763   /* Check the parameters */
00764   assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
00765
00766   /* Wait for last operation to be completed */
00767   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00768
00769   if(status == HAL_OK)
00770   {
00771     /* Clean the error context */
00772     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00773
00774     /* If the previous operation is completed, proceed to erase the option bytes */
00775     SET_BIT(FLASH->CR, FLASH_CR_OPTER);
00776     SET_BIT(FLASH->CR, FLASH_CR_STRT);
00777
00778     /* Wait for last operation to be completed */
00779     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00780
00781     /* If the erase operation is completed, disable the OPTER Bit */
00782     CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
00783
00784     if(status == HAL_OK)
00785     {
00786       /* Enable the Option Bytes Programming operation */
00787       SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
00788
00789       WRITE_REG(OB->RDP, ReadProtectLevel);
00790
00791       /* Wait for last operation to be completed */
00792       status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00793
00794       /* if the program operation is completed, disable the OPTPG Bit */
00795       CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
00796     }
00797   }
00798
00799   return status;
00800 }
00801
00802 /**
00803   * @brief  Program the FLASH User Option Byte.
00804   * @note   Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
00805   * @param  UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
00806   *         VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
00807   *         And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
00808   * @retval HAL status
00809   */
00810 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
00811 {
00812   HAL_StatusTypeDef status = HAL_OK;
00813
00814   /* Check the parameters */
00815   assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW)));
00816   assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST)));
00817   assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST)));
00818   assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
00819   assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON)));
00820   assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET)));
00821 #if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
00822   assert_param(IS_OB_SDACD_VDD_MONITOR((UserConfig&OB_SDACD_VDD_MONITOR_SET)));
00823 #endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
00824
00825   /* Wait for last operation to be completed */
00826   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00827
00828   if(status == HAL_OK)
00829   {
00830     /* Clean the error context */
00831     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00832
00833     /* Enable the Option Bytes Programming operation */
00834     SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
00835
00836 #if   defined(FLASH_OBR_SDADC12_VDD_MONITOR)
00837     OB->USER = (UserConfig | 0x08U);
00838 #else
00839     OB->USER = (UserConfig | 0x88U);
00840 #endif
00841
00842     /* Wait for last operation to be completed */
00843     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00844
00845     /* if the program operation is completed, disable the OPTPG Bit */
00846     CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
00847   }
00848
00849   return status;
00850 }
00851
00852 /**
00853   * @brief  Programs a half word at a specified Option Byte Data address.
00854   * @note   The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
00855   *         The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
00856   *         The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
00857   *         (system reset will occur)
00858   *         Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
00859   * @param  Address specifies the address to be programmed.
00860   *         This parameter can be 0x1FFFF804 or 0x1FFFF806.
00861   * @param  Data specifies the data to be programmed.
00862   * @retval HAL status
00863   */
00864 static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
00865 {
00866   HAL_StatusTypeDef status = HAL_ERROR;
00867
00868   /* Check the parameters */
00869   assert_param(IS_OB_DATA_ADDRESS(Address));
00870
00871   /* Wait for last operation to be completed */
00872   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00873
00874   if(status == HAL_OK)
00875   {
00876     /* Clean the error context */
00877     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00878
00879     /* Enables the Option Bytes Programming operation */
00880     SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
00881     *(__IO uint16_t*)Address = Data;
00882
00883     /* Wait for last operation to be completed */
00884     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00885
00886     /* If the program operation is completed, disable the OPTPG Bit */
00887     CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
00888   }
00889   /* Return the Option Byte Data Program Status */
00890   return status;
00891 }
00892
00893 /**
00894   * @brief  Return the FLASH Write Protection Option Bytes value.
00895   * @retval The FLASH Write Protection Option Bytes value
00896   */
00897 static uint32_t FLASH_OB_GetWRP(void)
00898 {
00899   /* Return the FLASH write protection Register value */
00900   return (uint32_t)(READ_REG(FLASH->WRPR));
00901 }
00902
00903 /**
00904   * @brief  Returns the FLASH Read Protection level.
00905   * @retval FLASH RDP level
00906   *         This parameter can be one of the following values:
00907   *            @arg @ref OB_RDP_LEVEL_0 No protection
00908   *            @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
00909   *            @arg @ref OB_RDP_LEVEL_2 Full chip protection
00910   */
00911 static uint32_t FLASH_OB_GetRDP(void)
00912 {
00913   uint32_t tmp_reg = 0U;
00914
00915   /* Read RDP level bits */
00916 #if defined(FLASH_OBR_RDPRT)
00917   tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT);
00918 #endif
00919 #if defined(FLASH_OBR_LEVEL1_PROT)
00920   tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_LEVEL1_PROT | FLASH_OBR_LEVEL2_PROT));
00921 #endif /* FLASH_OBR_LEVEL1_PROT */
00922
00923 #if defined(FLASH_OBR_RDPRT)
00924   if (tmp_reg == FLASH_OBR_RDPRT_1)
00925 #endif
00926 #if defined(FLASH_OBR_LEVEL1_PROT)
00927   if (tmp_reg == FLASH_OBR_LEVEL1_PROT)
00928 #endif /* FLASH_OBR_LEVEL1_PROT */
00929   {
00930     return OB_RDP_LEVEL_1;
00931   }
00932 #if   defined(FLASH_OBR_RDPRT)
00933   else if (tmp_reg == FLASH_OBR_RDPRT_2)
00934 #elif defined(FLASH_OBR_LEVEL2_PROT)
00935   else if (tmp_reg == FLASH_OBR_LEVEL2_PROT)
00936 #endif
00937   {
00938     return OB_RDP_LEVEL_2;
00939   }
00940   else
00941   {
00942     return OB_RDP_LEVEL_0;
00943   }
00944 }
00945
00946 /**
00947   * @brief  Return the FLASH User Option Byte value.
00948   * @retval  The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
00949   *         VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
00950   *         And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
00951   */
00952 static uint8_t FLASH_OB_GetUser(void)
00953 {
00954   /* Return the User Option Byte */
00955   return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT);
00956 }
00957
00958 /**
00959   * @}
00960   */
00961
00962 /**
00963   * @}
00964   */
00965
00966 /** @addtogroup FLASH
00967   * @{
00968   */
00969
00970 /** @addtogroup FLASH_Private_Functions
00971  * @{
00972  */
00973
00974 /**
00975   * @brief  Erase the specified FLASH memory page
00976   * @param  PageAddress FLASH page to erase
00977   *         The value of this parameter depend on device used within the same series
00978   *
00979   * @retval None
00980   */
00981 void FLASH_PageErase(uint32_t PageAddress)
00982 {
00983   /* Clean the error context */
00984   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00985
00986     /* Proceed to erase the page */
00987     SET_BIT(FLASH->CR, FLASH_CR_PER);
00988     WRITE_REG(FLASH->AR, PageAddress);
00989     SET_BIT(FLASH->CR, FLASH_CR_STRT);
00990 }
00991
00992 /**
00993   * @}
00994   */
00995
00996 /**
00997   * @}
00998   */
00999
01000 #endif /* HAL_FLASH_MODULE_ENABLED */
01001 /**
01002   * @}
01003   */
01004
01005 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_flash_ex.h Source File

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stm32f3xx_hal_flash_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_flash_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of Flash HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_FLASH_EX_H
00038 #define __STM32F3xx_HAL_FLASH_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup FLASHEx
00052   * @{
00053   */
00054
00055 /** @addtogroup FLASHEx_Private_Constants
00056   * @{
00057   */
00058
00059 #define FLASH_SIZE_DATA_REGISTER (0x1FFFF7CCU)
00060
00061 /**
00062   * @}
00063   */
00064
00065 /** @addtogroup FLASHEx_Private_Macros
00066   * @{
00067   */
00068 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
00069                              ((VALUE) == FLASH_TYPEERASE_MASSERASE))
00070
00071 #define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))
00072
00073 #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
00074                             ((VALUE) == OB_WRPSTATE_ENABLE))
00075
00076 #define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
00077
00078 #define IS_OB_RDP_LEVEL(LEVEL)     (((LEVEL) == OB_RDP_LEVEL_0)   ||\
00079                                     ((LEVEL) == OB_RDP_LEVEL_1))/*||\
00080                                     ((LEVEL) == OB_RDP_LEVEL_2))*/
00081
00082 #define IS_OB_IWDG_SOURCE(SOURCE)  (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
00083
00084 #define IS_OB_STOP_SOURCE(SOURCE)  (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
00085
00086 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
00087
00088 #define IS_OB_BOOT1(BOOT1)         (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
00089
00090 #define IS_OB_VDDA_ANALOG(ANALOG)  (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
00091
00092 #define IS_OB_SRAM_PARITY(PARITY)  (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
00093
00094
00095 #if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
00096 #define IS_OB_SDACD_VDD_MONITOR(VDD_MONITOR) (((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_SET) || \
00097                                               ((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_RESET))
00098 #endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
00099
00100 #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
00101
00102 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
00103  || defined(STM32F373xC) || defined(STM32F378xx)
00104 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \
00105                                            ((ADDRESS) <= 0x0803FFFFU) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
00106                                            ((ADDRESS) <= 0x0801FFFFU) :  ((ADDRESS) <= 0x0800FFFFU))))
00107 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
00108        /* STM32F373xC || STM32F378xx */
00109
00110 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
00111 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= 0x0807FFFFU))
00112 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
00113
00114 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
00115  || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
00116 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
00117                                            ((ADDRESS) <= 0x0800FFFFU) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
00118                                            ((ADDRESS) <= 0x08007FFFU) :  ((ADDRESS) <= 0x08003FFFU))))
00119 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
00120        /* STM32F303x8 || STM32F334x8 || STM32F328xx */
00121
00122 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
00123  || defined(STM32F373xC) || defined(STM32F378xx)
00124 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0803FFFFU) : \
00125                                            (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U)  ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0801FFFFU) : \
00126                                             ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0800FFFFU)))
00127 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
00128        /* STM32F373xC || STM32F378xx */
00129
00130 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
00131 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0807FFFFU)
00132 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
00133
00134 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
00135  || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
00136 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0800FFFFU) : \
00137                                            (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x08007FFFU) : \
00138                                             ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x08003FFFU)))
00139 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
00140        /* STM32F303x8 || STM32F334x8 || STM32F328xx */
00141
00142 /**
00143   * @}
00144   */
00145
00146 /* Exported types ------------------------------------------------------------*/
00147 /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
00148   * @{
00149   */
00150 /**
00151   * @brief  FLASH Erase structure definition
00152   */
00153 typedef struct
00154 {
00155   uint32_t TypeErase;   /*!< TypeErase: Mass erase or page erase.
00156                              This parameter can be a value of @ref FLASHEx_Type_Erase */
00157
00158   uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
00159                              This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */
00160
00161   uint32_t NbPages;     /*!< NbPages: Number of pagess to be erased.
00162                              This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
00163
00164 } FLASH_EraseInitTypeDef;
00165
00166 /**
00167   * @brief  FLASH Options bytes program structure definition
00168   */
00169 typedef struct
00170 {
00171   uint32_t OptionType;  /*!< OptionType: Option byte to be configured.
00172                              This parameter can be a value of @ref FLASHEx_OB_Type */
00173
00174   uint32_t WRPState;    /*!< WRPState: Write protection activation or deactivation.
00175                              This parameter can be a value of @ref FLASHEx_OB_WRP_State */
00176
00177   uint32_t WRPPage;     /*!< WRPPage: specifies the page(s) to be write protected
00178                              This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
00179
00180   uint8_t RDPLevel;     /*!< RDPLevel: Set the read protection level..
00181                              This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
00182
00183   uint8_t USERConfig;   /*!< USERConfig: Program the FLASH User Option Byte:
00184                              IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY / SDADC12_VDD_MONITOR
00185                              This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
00186                              @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring,
00187                              @ref FLASHEx_OB_RAM_Parity_Check_Enable.
00188                              @if STM32F373xC
00189                              And @ref FLASHEx_OB_SDADC12_VDD_MONITOR (only for STM32F373xC & STM32F378xx devices)
00190                              @endif
00191                              @if STM32F378xx
00192                              And @ref FLASHEx_OB_SDADC12_VDD_MONITOR (only for STM32F373xC & STM32F378xx devices)
00193                              @endif
00194                              */
00195
00196   uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
00197                              This parameter can be a value of @ref FLASHEx_OB_Data_Address */
00198
00199   uint8_t DATAData;     /*!< DATAData: Data to be stored in the option byte DATA
00200                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
00201 } FLASH_OBProgramInitTypeDef;
00202 /**
00203   * @}
00204   */
00205
00206 /* Exported constants --------------------------------------------------------*/
00207 /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
00208   * @{
00209   */
00210
00211 /** @defgroup FLASHEx_Page_Size FLASHEx Page Size
00212   * @{
00213   */
00214 #define FLASH_PAGE_SIZE          0x800
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup FLASHEx_Type_Erase FLASH Type Erase
00220   * @{
00221   */
00222 #define FLASH_TYPEERASE_PAGES     (0x00U)  /*!<Pages erase only*/
00223 #define FLASH_TYPEERASE_MASSERASE (0x01U)  /*!<Flash mass erase activation*/
00224
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
00230   * @{
00231   */
00232
00233 /** @defgroup FLASHEx_OB_Type Option Bytes Type
00234   * @{
00235   */
00236 #define OPTIONBYTE_WRP       (0x01U)  /*!<WRP option byte configuration*/
00237 #define OPTIONBYTE_RDP       (0x02U)  /*!<RDP option byte configuration*/
00238 #define OPTIONBYTE_USER      (0x04U)  /*!<USER option byte configuration*/
00239 #define OPTIONBYTE_DATA      (0x08U)  /*!<DATA option byte configuration*/
00240
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
00246   * @{
00247   */
00248 #define OB_WRPSTATE_DISABLE   (0x00U)  /*!<Disable the write protection of the desired pages*/
00249 #define OB_WRPSTATE_ENABLE    (0x01U)  /*!<Enable the write protection of the desired pagess*/
00250
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup FLASHEx_OB_Write_Protection FLASHEx OB Write Protection
00256   * @{
00257   */
00258 #define OB_WRP_PAGES0TO1               (0x00000001U) /* Write protection of page 0 to 1 */
00259 #define OB_WRP_PAGES2TO3               (0x00000002U) /* Write protection of page 2 to 3 */
00260 #define OB_WRP_PAGES4TO5               (0x00000004U) /* Write protection of page 4 to 5 */
00261 #define OB_WRP_PAGES6TO7               (0x00000008U) /* Write protection of page 6 to 7 */
00262 #define OB_WRP_PAGES8TO9               (0x00000010U) /* Write protection of page 8 to 9 */
00263 #define OB_WRP_PAGES10TO11             (0x00000020U) /* Write protection of page 10 to 11 */
00264 #define OB_WRP_PAGES12TO13             (0x00000040U) /* Write protection of page 12 to 13 */
00265 #define OB_WRP_PAGES14TO15             (0x00000080U) /* Write protection of page 14 to 15 */
00266 #define OB_WRP_PAGES16TO17             (0x00000100U) /* Write protection of page 16 to 17 */
00267 #define OB_WRP_PAGES18TO19             (0x00000200U) /* Write protection of page 18 to 19 */
00268 #define OB_WRP_PAGES20TO21             (0x00000400U) /* Write protection of page 20 to 21 */
00269 #define OB_WRP_PAGES22TO23             (0x00000800U) /* Write protection of page 22 to 23 */
00270 #define OB_WRP_PAGES24TO25             (0x00001000U) /* Write protection of page 24 to 25 */
00271 #define OB_WRP_PAGES26TO27             (0x00002000U) /* Write protection of page 26 to 27 */
00272 #define OB_WRP_PAGES28TO29             (0x00004000U) /* Write protection of page 28 to 29 */
00273 #define OB_WRP_PAGES30TO31             (0x00008000U) /* Write protection of page 30 to 31 */
00274
00275 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
00276  || defined(STM32F373xC) || defined(STM32F378xx)
00277 #define OB_WRP_PAGES32TO33             (0x00010000U) /* Write protection of page 32 to 33 */
00278 #define OB_WRP_PAGES34TO35             (0x00020000U) /* Write protection of page 34 to 35 */
00279 #define OB_WRP_PAGES36TO37             (0x00040000U) /* Write protection of page 36 to 37 */
00280 #define OB_WRP_PAGES38TO39             (0x00080000U) /* Write protection of page 38 to 39 */
00281 #define OB_WRP_PAGES40TO41             (0x00100000U) /* Write protection of page 40 to 41 */
00282 #define OB_WRP_PAGES42TO43             (0x00200000U) /* Write protection of page 42 to 43 */
00283 #define OB_WRP_PAGES44TO45             (0x00400000U) /* Write protection of page 44 to 45 */
00284 #define OB_WRP_PAGES46TO47             (0x00800000U) /* Write protection of page 46 to 47 */
00285 #define OB_WRP_PAGES48TO49             (0x01000000U) /* Write protection of page 48 to 49 */
00286 #define OB_WRP_PAGES50TO51             (0x02000000U) /* Write protection of page 50 to 51 */
00287 #define OB_WRP_PAGES52TO53             (0x04000000U) /* Write protection of page 52 to 53 */
00288 #define OB_WRP_PAGES54TO55             (0x08000000U) /* Write protection of page 54 to 55 */
00289 #define OB_WRP_PAGES56TO57             (0x10000000U) /* Write protection of page 56 to 57 */
00290 #define OB_WRP_PAGES58TO59             (0x20000000U) /* Write protection of page 58 to 59 */
00291 #define OB_WRP_PAGES60TO61             (0x40000000U) /* Write protection of page 60 to 61 */
00292 #define OB_WRP_PAGES62TO127            (0x80000000U) /* Write protection of page 62 to 127 */
00293 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
00294        /* STM32F373xC || STM32F378xx                   */
00295
00296 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
00297 #define OB_WRP_PAGES32TO33             (0x00010000U) /* Write protection of page 32 to 33 */
00298 #define OB_WRP_PAGES34TO35             (0x00020000U) /* Write protection of page 34 to 35 */
00299 #define OB_WRP_PAGES36TO37             (0x00040000U) /* Write protection of page 36 to 37 */
00300 #define OB_WRP_PAGES38TO39             (0x00080000U) /* Write protection of page 38 to 39 */
00301 #define OB_WRP_PAGES40TO41             (0x00100000U) /* Write protection of page 40 to 41 */
00302 #define OB_WRP_PAGES42TO43             (0x00200000U) /* Write protection of page 42 to 43 */
00303 #define OB_WRP_PAGES44TO45             (0x00400000U) /* Write protection of page 44 to 45 */
00304 #define OB_WRP_PAGES46TO47             (0x00800000U) /* Write protection of page 46 to 47 */
00305 #define OB_WRP_PAGES48TO49             (0x01000000U) /* Write protection of page 48 to 49 */
00306 #define OB_WRP_PAGES50TO51             (0x02000000U) /* Write protection of page 50 to 51 */
00307 #define OB_WRP_PAGES52TO53             (0x04000000U) /* Write protection of page 52 to 53 */
00308 #define OB_WRP_PAGES54TO55             (0x08000000U) /* Write protection of page 54 to 55 */
00309 #define OB_WRP_PAGES56TO57             (0x10000000U) /* Write protection of page 56 to 57 */
00310 #define OB_WRP_PAGES58TO59             (0x20000000U) /* Write protection of page 58 to 59 */
00311 #define OB_WRP_PAGES60TO61             (0x40000000U) /* Write protection of page 60 to 61 */
00312 #define OB_WRP_PAGES62TO255            (0x80000000U) /* Write protection of page 62 to 255 */
00313 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
00314
00315 #define OB_WRP_PAGES0TO15MASK          (0x000000FFU)
00316 #define OB_WRP_PAGES16TO31MASK         (0x0000FF00U)
00317
00318 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
00319  || defined(STM32F373xC) || defined(STM32F378xx)
00320 #define OB_WRP_PAGES32TO47MASK         (0x00FF0000U)
00321 #define OB_WRP_PAGES48TO127MASK        (0xFF000000U)
00322 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
00323        /* STM32F373xC || STM32F378xx                   */
00324
00325 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
00326 #define OB_WRP_PAGES32TO47MASK         (0x00FF0000U)
00327 #define OB_WRP_PAGES48TO255MASK        (0xFF000000U)
00328 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
00329
00330 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
00331  || defined(STM32F373xC) || defined(STM32F378xx)
00332 #define OB_WRP_PAGES32TO47MASK         (0x00FF0000U)
00333 #define OB_WRP_PAGES48TO127MASK        (0xFF000000U)
00334 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
00335        /* STM32F373xC || STM32F378xx                   */
00336
00337 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) \
00338  || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
00339  || defined(STM32F373xC) || defined(STM32F378xx)
00340 #define OB_WRP_ALLPAGES                (0xFFFFFFFFU) /*!< Write protection of all pages */
00341 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00342        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00343        /* STM32F373xC || STM32F378xx                   */
00344
00345 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
00346  || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
00347 #define OB_WRP_ALLPAGES                (0x0000FFFFU) /*!< Write protection of all pages */
00348 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
00349        /* STM32F303x8 || STM32F334x8 || STM32F328xx    */
00350
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
00356   * @{
00357   */
00358 #define OB_RDP_LEVEL_0             ((uint8_t)0xAAU)
00359 #define OB_RDP_LEVEL_1             ((uint8_t)0xBBU)
00360 #define OB_RDP_LEVEL_2             ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2
00361                                                       it's no more possible to go back to level 1 or 0U */
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
00367   * @{
00368   */
00369 #define OB_IWDG_SW                 ((uint8_t)0x01U)  /*!< Software IWDG selected */
00370 #define OB_IWDG_HW                 ((uint8_t)0x00U)  /*!< Hardware IWDG selected */
00371 /**
00372   * @}
00373   */
00374
00375 /** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
00376   * @{
00377   */
00378 #define OB_STOP_NO_RST             ((uint8_t)0x02U) /*!< No reset generated when entering in STOP */
00379 #define OB_STOP_RST                ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
00380 /**
00381   * @}
00382   */
00383
00384 /** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
00385   * @{
00386   */
00387 #define OB_STDBY_NO_RST            ((uint8_t)0x04U) /*!< No reset generated when entering in STANDBY */
00388 #define OB_STDBY_RST               ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
00389 /**
00390   * @}
00391   */
00392
00393 /** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
00394   * @{
00395   */
00396 #define OB_BOOT1_RESET             ((uint8_t)0x00U) /*!< BOOT1 Reset */
00397 #define OB_BOOT1_SET               ((uint8_t)0x10U) /*!< BOOT1 Set */
00398 /**
00399   * @}
00400   */
00401
00402 /** @defgroup FLASHEx_OB_VDDA_Analog_Monitoring Option Byte VDDA Analog Monitoring
00403   * @{
00404   */
00405 #define OB_VDDA_ANALOG_ON          ((uint8_t)0x20U) /*!< Analog monitoring on VDDA Power source ON */
00406 #define OB_VDDA_ANALOG_OFF         ((uint8_t)0x00U) /*!< Analog monitoring on VDDA Power source OFF */
00407 /**
00408   * @}
00409   */
00410
00411 /** @defgroup FLASHEx_OB_RAM_Parity_Check_Enable Option Byte SRAM Parity Check Enable
00412   * @{
00413   */
00414 #define OB_SRAM_PARITY_SET         ((uint8_t)0x00U) /*!< SRAM parity check enable set */
00415 #define OB_SRAM_PARITY_RESET       ((uint8_t)0x40U) /*!< SRAM parity check enable reset */
00416 /**
00417   * @}
00418   */
00419
00420
00421 #if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
00422 /** @defgroup FLASHEx_OB_SDADC12_VDD_MONITOR OB SDADC12 VDD MONITOR
00423   * @{
00424   */
00425 #define OB_SDACD_VDD_MONITOR_RESET           ((uint8_t)0x00U) /*!< SDADC VDD Monitor reset */
00426 #define OB_SDACD_VDD_MONITOR_SET             ((uint8_t)0x80U) /*!< SDADC VDD Monitor set */
00427
00428 /**
00429   * @}
00430   */
00431 #endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
00432
00433 /** @defgroup FLASHEx_OB_Data_Address  Option Byte Data Address
00434   * @{
00435   */
00436 #define OB_DATA_ADDRESS_DATA0     (0x1FFFF804U)
00437 #define OB_DATA_ADDRESS_DATA1     (0x1FFFF806U)
00438 /**
00439   * @}
00440   */
00441
00442 /**
00443   * @}
00444   */
00445
00446 /**
00447   * @}
00448   */
00449
00450 /* Exported functions --------------------------------------------------------*/
00451 /** @addtogroup FLASHEx_Exported_Functions
00452   * @{
00453   */
00454
00455 /** @addtogroup FLASHEx_Exported_Functions_Group1
00456   * @{
00457   */
00458 /* IO operation functions *****************************************************/
00459 HAL_StatusTypeDef  HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
00460 HAL_StatusTypeDef  HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
00461
00462 /**
00463   * @}
00464   */
00465
00466 /** @addtogroup FLASHEx_Exported_Functions_Group2
00467   * @{
00468   */
00469 /* Peripheral Control functions ***********************************************/
00470 HAL_StatusTypeDef  HAL_FLASHEx_OBErase(void);
00471 HAL_StatusTypeDef  HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
00472 void               HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
00473 uint32_t           HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
00474
00475 /**
00476   * @}
00477   */
00478
00479 /**
00480   * @}
00481   */
00482
00483 /**
00484   * @}
00485   */
00486
00487 /**
00488   * @}
00489   */
00490
00491 #ifdef __cplusplus
00492 }
00493 #endif
00494
00495 #endif /* __STM32F3xx_HAL_FLASH_EX_H */
00496
00497 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00498
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_gpio.c Source File

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stm32f3xx_hal_gpio.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_gpio.c
00004   * @author  MCD Application Team
00005   * @brief   GPIO HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                     ##### GPIO Peripheral features #####
00014   ==============================================================================
00015   [..]
00016     (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
00017         configured by software in several modes:
00018         (++) Input mode
00019         (++) Analog mode
00020         (++) Output mode
00021         (++) Alternate function mode
00022         (++) External interrupt/event lines
00023
00024     (+) During and just after reset, the alternate functions and external interrupt
00025         lines are not active and the I/O ports are configured in input floating mode.
00026
00027     (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
00028         activated or not.
00029
00030     (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
00031         type and the IO speed can be selected depending on the VDD value.
00032
00033     (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
00034         multiplexer that allows only one peripheral alternate function (AF) connected
00035        to an IO pin at a time. In this way, there can be no conflict between peripherals
00036        sharing the same IO pin.
00037
00038     (+) All ports have external interrupt/event capability. To use external interrupt
00039         lines, the port must be configured in input mode. All available GPIO pins are
00040         connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
00041
00042     (+) The external interrupt/event controller consists of up to 23 edge detectors
00043         (16 lines are connected to GPIO) for generating event/interrupt requests (each
00044         input line can be independently configured to select the type (interrupt or event)
00045         and the corresponding trigger event (rising or falling or both). Each line can
00046         also be masked independently.
00047
00048                      ##### How to use this driver #####
00049   ==============================================================================
00050   [..]
00051     (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
00052
00053     (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
00054         (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
00055         (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
00056              structure.
00057         (++) In case of Output or alternate function mode selection: the speed is
00058              configured through "Speed" member from GPIO_InitTypeDef structure.
00059         (++) In alternate mode is selection, the alternate function connected to the IO
00060              is configured through "Alternate" member from GPIO_InitTypeDef structure.
00061         (++) Analog mode is required when a pin is to be used as ADC channel
00062              or DAC output.
00063         (++) In case of external interrupt/event selection the "Mode" member from
00064              GPIO_InitTypeDef structure select the type (interrupt or event) and
00065              the corresponding trigger event (rising or falling or both).
00066
00067     (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
00068         mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
00069         HAL_NVIC_EnableIRQ().
00070
00071     (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
00072
00073     (#) To set/reset the level of a pin configured in output mode use
00074         HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
00075
00076    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
00077
00078     (#) During and just after reset, the alternate functions are not
00079         active and the GPIO pins are configured in input floating mode (except JTAG
00080         pins).
00081
00082     (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
00083         (PC14 and PC15U, respectively) when the LSE oscillator is off. The LSE has
00084         priority over the GPIO function.
00085
00086     (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
00087         general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
00088         The HSE has priority over the GPIO function.
00089
00090   @endverbatim
00091   ******************************************************************************
00092   * @attention
00093   *
00094   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00095   *
00096   * Redistribution and use in source and binary forms, with or without modification,
00097   * are permitted provided that the following conditions are met:
00098   *   1. Redistributions of source code must retain the above copyright notice,
00099   *      this list of conditions and the following disclaimer.
00100   *   2. Redistributions in binary form must reproduce the above copyright notice,
00101   *      this list of conditions and the following disclaimer in the documentation
00102   *      and/or other materials provided with the distribution.
00103   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00104   *      may be used to endorse or promote products derived from this software
00105   *      without specific prior written permission.
00106   *
00107   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00108   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00109   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00110   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00111   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00112   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00113   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00114   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00115   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00116   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00117   *
00118   ******************************************************************************
00119   */
00120
00121 /* Includes ------------------------------------------------------------------*/
00122 #include "stm32f3xx_hal.h"
00123
00124 /** @addtogroup STM32F3xx_HAL_Driver
00125   * @{
00126   */
00127
00128 /** @defgroup GPIO GPIO
00129   * @brief GPIO HAL module driver
00130   * @{
00131   */
00132
00133 #ifdef HAL_GPIO_MODULE_ENABLED
00134
00135 /* Private typedef -----------------------------------------------------------*/
00136 /* Private defines -----------------------------------------------------------*/
00137 /** @defgroup GPIO_Private_Defines GPIO Private Defines
00138   * @{
00139   */
00140 #define GPIO_MODE             (0x00000003U)
00141 #define EXTI_MODE             (0x10000000U)
00142 #define GPIO_MODE_IT          (0x00010000U)
00143 #define GPIO_MODE_EVT         (0x00020000U)
00144 #define RISING_EDGE           (0x00100000U)
00145 #define FALLING_EDGE          (0x00200000U)
00146 #define GPIO_OUTPUT_TYPE      (0x00000010U)
00147
00148 #define GPIO_NUMBER           (16U)
00149 /**
00150   * @}
00151   */
00152
00153 /* Private macros ------------------------------------------------------------*/
00154 /* Private macros ------------------------------------------------------------*/
00155 /** @defgroup GPIO_Private_Macros GPIO Private Macros
00156   * @{
00157   */
00158 /**
00159   * @}
00160   */
00161 /* Private variables ---------------------------------------------------------*/
00162 /* Private function prototypes -----------------------------------------------*/
00163 /* Exported functions --------------------------------------------------------*/
00164
00165 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
00166   * @{
00167   */
00168
00169 /** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
00170  *  @brief    Initialization and Configuration functions
00171  *
00172 @verbatim
00173  ===============================================================================
00174               ##### Initialization and de-initialization functions #####
00175  ===============================================================================
00176
00177 @endverbatim
00178   * @{
00179   */
00180
00181 /**
00182   * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
00183   * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices
00184   * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
00185   *         the configuration information for the specified GPIO peripheral.
00186   * @retval None
00187   */
00188 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
00189 {
00190   uint32_t position = 0x00U;
00191   uint32_t iocurrent = 0x00U;
00192   uint32_t temp = 0x00U;
00193
00194   /* Check the parameters */
00195   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00196   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
00197   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
00198   assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
00199
00200   /* Configure the port pins */
00201   while (((GPIO_Init->Pin) >> position) != RESET)
00202   {
00203     /* Get current io position */
00204     iocurrent = (GPIO_Init->Pin) & (1U << position);
00205
00206     if(iocurrent)
00207     {
00208       /*--------------------- GPIO Mode Configuration ------------------------*/
00209       /* In case of Alternate function mode selection */
00210       if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
00211       {
00212         /* Check the Alternate function parameters */
00213         assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
00214         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
00215
00216         /* Configure Alternate function mapped with the current IO */
00217         temp = GPIOx->AFR[position >> 3];
00218         temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
00219         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
00220         GPIOx->AFR[position >> 3] = temp;
00221       }
00222
00223       /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
00224       temp = GPIOx->MODER;
00225       temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
00226       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
00227       GPIOx->MODER = temp;
00228
00229       /* In case of Output or Alternate function mode selection */
00230       if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
00231          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
00232       {
00233         /* Check the Speed parameter */
00234         assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
00235         /* Configure the IO Speed */
00236         temp = GPIOx->OSPEEDR;
00237         temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
00238         temp |= (GPIO_Init->Speed << (position * 2U));
00239         GPIOx->OSPEEDR = temp;
00240
00241         /* Configure the IO Output Type */
00242         temp = GPIOx->OTYPER;
00243         temp &= ~(GPIO_OTYPER_OT_0 << position) ;
00244         temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
00245         GPIOx->OTYPER = temp;
00246       }
00247
00248       /* Activate the Pull-up or Pull down resistor for the current IO */
00249       temp = GPIOx->PUPDR;
00250       temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
00251       temp |= ((GPIO_Init->Pull) << (position * 2U));
00252       GPIOx->PUPDR = temp;
00253
00254       /*--------------------- EXTI Mode Configuration ------------------------*/
00255       /* Configure the External Interrupt or event for the current IO */
00256       if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
00257       {
00258         /* Enable SYSCFG Clock */
00259         __HAL_RCC_SYSCFG_CLK_ENABLE();
00260
00261         temp = SYSCFG->EXTICR[position >> 2];
00262         temp &= ~((0x0FU) << (4U * (position & 0x03U)));
00263         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
00264         SYSCFG->EXTICR[position >> 2] = temp;
00265
00266         /* Clear EXTI line configuration */
00267         temp = EXTI->IMR;
00268         temp &= ~((uint32_t)iocurrent);
00269         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
00270         {
00271           temp |= iocurrent;
00272         }
00273         EXTI->IMR = temp;
00274
00275         temp = EXTI->EMR;
00276         temp &= ~((uint32_t)iocurrent);
00277         if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
00278         {
00279           temp |= iocurrent;
00280         }
00281         EXTI->EMR = temp;
00282
00283         /* Clear Rising Falling edge configuration */
00284         temp = EXTI->RTSR;
00285         temp &= ~((uint32_t)iocurrent);
00286         if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
00287         {
00288           temp |= iocurrent;
00289         }
00290         EXTI->RTSR = temp;
00291
00292         temp = EXTI->FTSR;
00293         temp &= ~((uint32_t)iocurrent);
00294         if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
00295         {
00296           temp |= iocurrent;
00297         }
00298         EXTI->FTSR = temp;
00299       }
00300     }
00301
00302     position++;
00303   }
00304 }
00305
00306 /**
00307   * @brief  De-initialize the GPIOx peripheral registers to their default reset values.
00308   * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F30X device or STM32F37X device
00309   * @param  GPIO_Pin specifies the port bit to be written.
00310   *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
00311   * @retval None
00312   */
00313 void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
00314 {
00315   uint32_t position = 0x00U;
00316   uint32_t iocurrent = 0x00U;
00317   uint32_t tmp = 0x00U;
00318
00319   /* Check the parameters */
00320   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00321   assert_param(IS_GPIO_PIN(GPIO_Pin));
00322
00323   /* Configure the port pins */
00324   while ((GPIO_Pin >> position) != RESET)
00325   {
00326     /* Get current io position */
00327     iocurrent = GPIO_Pin & (1U << position);
00328
00329     if (iocurrent)
00330     {
00331       /*------------------------- GPIO Mode Configuration --------------------*/
00332       /* Configure IO Direction in Input Floting Mode */
00333       GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
00334
00335       /* Configure the default Alternate Function in current IO */
00336       GPIOx->AFR[position >> 3] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
00337
00338       /* Configure the default value for IO Speed */
00339       GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
00340
00341       /* Configure the default value IO Output Type */
00342       GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;
00343
00344       /* Deactivate the Pull-up and Pull-down resistor for the current IO */
00345       GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
00346
00347
00348       /*------------------------- EXTI Mode Configuration --------------------*/
00349       /* Clear the External Interrupt or Event for the current IO */
00350
00351       tmp = SYSCFG->EXTICR[position >> 2];
00352       tmp &= ((0x0FU) << (4U * (position & 0x03U)));
00353       if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
00354       {
00355         tmp = (0x0FU) << (4U * (position & 0x03U));
00356         SYSCFG->EXTICR[position >> 2] &= ~tmp;
00357
00358         /* Clear EXTI line configuration */
00359         EXTI->IMR &= ~((uint32_t)iocurrent);
00360         EXTI->EMR &= ~((uint32_t)iocurrent);
00361
00362         /* Clear Rising Falling edge configuration */
00363         EXTI->RTSR &= ~((uint32_t)iocurrent);
00364         EXTI->FTSR &= ~((uint32_t)iocurrent);
00365       }
00366     }
00367
00368     position++;
00369   }
00370 }
00371
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
00377  *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
00378  *
00379 @verbatim
00380  ===============================================================================
00381                        ##### IO operation functions #####
00382  ===============================================================================
00383
00384 @endverbatim
00385   * @{
00386   */
00387
00388 /**
00389   * @brief  Read the specified input port pin.
00390   * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
00391   * @param  GPIO_Pin specifies the port bit to read.
00392   *         This parameter can be GPIO_PIN_x where x can be (0..15).
00393   * @retval The input port pin value.
00394   */
00395 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00396 {
00397   GPIO_PinState bitstatus;
00398
00399   /* Check the parameters */
00400   assert_param(IS_GPIO_PIN(GPIO_Pin));
00401
00402   if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
00403   {
00404     bitstatus = GPIO_PIN_SET;
00405   }
00406   else
00407   {
00408     bitstatus = GPIO_PIN_RESET;
00409   }
00410   return bitstatus;
00411 }
00412
00413 /**
00414   * @brief  Set or clear the selected data port bit.
00415   *
00416   * @note   This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
00417   *         accesses. In this way, there is no risk of an IRQ occurring between
00418   *         the read and the modify access.
00419   *
00420   * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
00421   * @param  GPIO_Pin specifies the port bit to be written.
00422   *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
00423   * @param  PinState specifies the value to be written to the selected bit.
00424   *         This parameter can be one of the GPIO_PinState enum values:
00425   *            @arg GPIO_PIN_RESET: to clear the port pin
00426   *            @arg GPIO_PIN_SET: to set the port pin
00427   * @retval None
00428   */
00429 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
00430 {
00431   /* Check the parameters */
00432   assert_param(IS_GPIO_PIN(GPIO_Pin));
00433   assert_param(IS_GPIO_PIN_ACTION(PinState));
00434
00435   if(PinState != GPIO_PIN_RESET)
00436   {
00437     GPIOx->BSRR = (uint32_t)GPIO_Pin;
00438   }
00439   else
00440   {
00441     GPIOx->BRR = (uint32_t)GPIO_Pin;
00442   }
00443 }
00444
00445 /**
00446   * @brief  Toggle the specified GPIO pin.
00447   * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
00448   * @param  GPIO_Pin specifies the pin to be toggled.
00449   * @retval None
00450   */
00451 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00452 {
00453   /* Check the parameters */
00454   assert_param(IS_GPIO_PIN(GPIO_Pin));
00455
00456   GPIOx->ODR ^= GPIO_Pin;
00457 }
00458
00459 /**
00460 * @brief  Lock GPIO Pins configuration registers.
00461   * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
00462   *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
00463   * @note   The configuration of the locked GPIO pins can no longer be modified
00464   *         until the next reset.
00465   * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
00466   * @param  GPIO_Pin specifies the port bits to be locked.
00467   *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
00468   * @retval None
00469   */
00470 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00471 {
00472   __IO uint32_t tmp = GPIO_LCKR_LCKK;
00473
00474   /* Check the parameters */
00475   assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
00476   assert_param(IS_GPIO_PIN(GPIO_Pin));
00477
00478   /* Apply lock key write sequence */
00479   tmp |= GPIO_Pin;
00480   /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */
00481   GPIOx->LCKR = tmp;
00482   /* Reset LCKx bit(s): LCKK='0' + LCK[15U-0] */
00483   GPIOx->LCKR = GPIO_Pin;
00484   /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */
00485   GPIOx->LCKR = tmp;
00486   /* Read LCKK bit*/
00487   tmp = GPIOx->LCKR;
00488
00489   if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
00490   {
00491     return HAL_OK;
00492   }
00493   else
00494   {
00495     return HAL_ERROR;
00496   }
00497 }
00498
00499 /**
00500   * @brief  Handle EXTI interrupt request.
00501   * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
00502   * @retval None
00503   */
00504 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
00505 {
00506   /* EXTI line interrupt detected */
00507   if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
00508   {
00509     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
00510     HAL_GPIO_EXTI_Callback(GPIO_Pin);
00511   }
00512 }
00513
00514 /**
00515   * @brief  EXTI line detection callback.
00516   * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
00517   * @retval None
00518   */
00519 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
00520 {
00521   /* Prevent unused argument(s) compilation warning */
00522   UNUSED(GPIO_Pin);
00523
00524   /* NOTE: This function should not be modified, when the callback is needed,
00525            the HAL_GPIO_EXTI_Callback could be implemented in the user file
00526    */
00527 }
00528
00529 /**
00530   * @}
00531   */
00532
00533
00534 /**
00535   * @}
00536   */
00537
00538 #endif /* HAL_GPIO_MODULE_ENABLED */
00539 /**
00540   * @}
00541   */
00542
00543 /**
00544   * @}
00545   */
00546
00547 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_gpio.h Source File

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stm32f3xx_hal_gpio.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_gpio.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of GPIO HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_GPIO_H
00038 #define __STM32F3xx_HAL_GPIO_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup GPIO
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056
00057 /** @defgroup GPIO_Exported_Types GPIO Exported Types
00058   * @{
00059   */
00060 /**
00061   * @brief   GPIO Init structure definition
00062   */
00063 typedef struct
00064 {
00065   uint32_t Pin;        /*!< Specifies the GPIO pins to be configured.
00066                            This parameter can be any value of @ref GPIO_pins */
00067
00068   uint32_t Mode;       /*!< Specifies the operating mode for the selected pins.
00069                            This parameter can be a value of @ref GPIO_mode */
00070
00071   uint32_t Pull;       /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
00072                            This parameter can be a value of @ref GPIO_pull */
00073
00074   uint32_t Speed;      /*!< Specifies the speed for the selected pins.
00075                            This parameter can be a value of @ref GPIO_speed */
00076
00077   uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins
00078                             This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
00079 }GPIO_InitTypeDef;
00080
00081 /**
00082   * @brief  GPIO Bit SET and Bit RESET enumeration
00083   */
00084 typedef enum
00085 {
00086   GPIO_PIN_RESET = 0U,
00087   GPIO_PIN_SET
00088 }GPIO_PinState;
00089 /**
00090   * @}
00091   */
00092
00093 /* Exported constants --------------------------------------------------------*/
00094 /** @defgroup GPIO_Exported_Constants GPIO Exported Constants
00095   * @{
00096   */
00097 /** @defgroup GPIO_pins GPIO pins
00098   * @{
00099   */
00100 #define GPIO_PIN_0                 ((uint16_t)0x0001U)  /* Pin 0 selected    */
00101 #define GPIO_PIN_1                 ((uint16_t)0x0002U)  /* Pin 1 selected    */
00102 #define GPIO_PIN_2                 ((uint16_t)0x0004U)  /* Pin 2 selected    */
00103 #define GPIO_PIN_3                 ((uint16_t)0x0008U)  /* Pin 3 selected    */
00104 #define GPIO_PIN_4                 ((uint16_t)0x0010U)  /* Pin 4 selected    */
00105 #define GPIO_PIN_5                 ((uint16_t)0x0020U)  /* Pin 5 selected    */
00106 #define GPIO_PIN_6                 ((uint16_t)0x0040U)  /* Pin 6 selected    */
00107 #define GPIO_PIN_7                 ((uint16_t)0x0080U)  /* Pin 7 selected    */
00108 #define GPIO_PIN_8                 ((uint16_t)0x0100U)  /* Pin 8 selected    */
00109 #define GPIO_PIN_9                 ((uint16_t)0x0200U)  /* Pin 9 selected    */
00110 #define GPIO_PIN_10                ((uint16_t)0x0400U)  /* Pin 10 selected   */
00111 #define GPIO_PIN_11                ((uint16_t)0x0800U)  /* Pin 11 selected   */
00112 #define GPIO_PIN_12                ((uint16_t)0x1000U)  /* Pin 12 selected   */
00113 #define GPIO_PIN_13                ((uint16_t)0x2000U)  /* Pin 13 selected   */
00114 #define GPIO_PIN_14                ((uint16_t)0x4000U)  /* Pin 14 selected   */
00115 #define GPIO_PIN_15                ((uint16_t)0x8000U)  /* Pin 15 selected   */
00116 #define GPIO_PIN_All               ((uint16_t)0xFFFFU)  /* All pins selected */
00117
00118 #define GPIO_PIN_MASK              (0x0000FFFFU) /* PIN mask for assert test */
00119 /**
00120   * @}
00121   */
00122
00123 /** @defgroup GPIO_mode GPIO mode
00124   * @brief GPIO Configuration Mode
00125   *        Elements values convention: 0xX0yz00YZ
00126   *           - X  : GPIO mode or EXTI Mode
00127   *           - y  : External IT or Event trigger detection
00128   *           - z  : IO configuration on External IT or Event
00129   *           - Y  : Output type (Push Pull or Open Drain)
00130   *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
00131   * @{
00132   */
00133 #define  GPIO_MODE_INPUT                        (0x00000000U)   /*!< Input Floating Mode                   */
00134 #define  GPIO_MODE_OUTPUT_PP                    (0x00000001U)   /*!< Output Push Pull Mode                 */
00135 #define  GPIO_MODE_OUTPUT_OD                    (0x00000011U)   /*!< Output Open Drain Mode                */
00136 #define  GPIO_MODE_AF_PP                        (0x00000002U)   /*!< Alternate Function Push Pull Mode     */
00137 #define  GPIO_MODE_AF_OD                        (0x00000012U)   /*!< Alternate Function Open Drain Mode    */
00138 #define  GPIO_MODE_ANALOG                       (0x00000003U)   /*!< Analog Mode  */
00139 #define  GPIO_MODE_IT_RISING                    (0x10110000U)   /*!< External Interrupt Mode with Rising edge trigger detection          */
00140 #define  GPIO_MODE_IT_FALLING                   (0x10210000U)   /*!< External Interrupt Mode with Falling edge trigger detection         */
00141 #define  GPIO_MODE_IT_RISING_FALLING            (0x10310000U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
00142 #define  GPIO_MODE_EVT_RISING                   (0x10120000U)   /*!< External Event Mode with Rising edge trigger detection               */
00143 #define  GPIO_MODE_EVT_FALLING                  (0x10220000U)   /*!< External Event Mode with Falling edge trigger detection              */
00144 #define  GPIO_MODE_EVT_RISING_FALLING           (0x10320000U)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
00145 /**
00146   * @}
00147   */
00148
00149 /** @defgroup GPIO_speed GPIO speed
00150   * @brief GPIO Output Maximum frequency
00151   * @{
00152   */
00153 #define  GPIO_SPEED_FREQ_LOW      (0x00000000U)  /*!< range up to 2 MHz, please refer to the product datasheet */
00154 #define  GPIO_SPEED_FREQ_MEDIUM   (0x00000001U)  /*!< range  4 MHz to 10 MHz, please refer to the product datasheet */
00155 #define  GPIO_SPEED_FREQ_HIGH     (0x00000003U)  /*!< range 10 MHz to 50 MHz, please refer to the product datasheet */
00156 /**
00157   * @}
00158   */
00159
00160  /** @defgroup GPIO_pull GPIO pull
00161    * @brief GPIO Pull-Up or Pull-Down Activation
00162    * @{
00163    */
00164 #define  GPIO_NOPULL        (0x00000000U)   /*!< No Pull-up or Pull-down activation  */
00165 #define  GPIO_PULLUP        (0x00000001U)   /*!< Pull-up activation                  */
00166 #define  GPIO_PULLDOWN      (0x00000002U)   /*!< Pull-down activation                */
00167 /**
00168   * @}
00169   */
00170
00171 /**
00172   * @}
00173   */
00174
00175 /* Exported macro ------------------------------------------------------------*/
00176 /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
00177   * @{
00178   */
00179
00180 /**
00181   * @brief  Check whether the specified EXTI line flag is set or not.
00182   * @param  __EXTI_LINE__ specifies the EXTI line flag to check.
00183   *         This parameter can be GPIO_PIN_x where x can be(0..15)
00184   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00185   */
00186 #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__)       (EXTI->PR & (__EXTI_LINE__))
00187
00188 /**
00189   * @brief  Clear the EXTI's line pending flags.
00190   * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.
00191   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00192   * @retval None
00193   */
00194 #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__)     (EXTI->PR = (__EXTI_LINE__))
00195
00196 /**
00197   * @brief  Check whether the specified EXTI line is asserted or not.
00198   * @param  __EXTI_LINE__ specifies the EXTI line to check.
00199   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00200   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00201   */
00202 #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)         (EXTI->PR & (__EXTI_LINE__))
00203
00204 /**
00205   * @brief  Clear the EXTI's line pending bits.
00206   * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
00207   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00208   * @retval None
00209   */
00210 #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)       (EXTI->PR = (__EXTI_LINE__))
00211
00212 /**
00213   * @brief  Generate a Software interrupt on selected EXTI line.
00214   * @param  __EXTI_LINE__ specifies the EXTI line to check.
00215   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00216   * @retval None
00217   */
00218 #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__)  (EXTI->SWIER |= (__EXTI_LINE__))
00219
00220 /**
00221   * @}
00222   */
00223
00224 /* Private macros ------------------------------------------------------------*/
00225 /** @addtogroup GPIO_Private_Macros GPIO Private Macros
00226   * @{
00227   */
00228 #define IS_GPIO_PIN_ACTION(ACTION)  (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
00229
00230 #define IS_GPIO_PIN(__PIN__)        ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
00231                                      (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
00232
00233 #define IS_GPIO_MODE(__MODE__)      (((__MODE__) == GPIO_MODE_INPUT)              ||\
00234                                      ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
00235                                      ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
00236                                      ((__MODE__) == GPIO_MODE_AF_PP)              ||\
00237                                      ((__MODE__) == GPIO_MODE_AF_OD)              ||\
00238                                      ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
00239                                      ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
00240                                      ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
00241                                      ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
00242                                      ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
00243                                      ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
00244                                      ((__MODE__) == GPIO_MODE_ANALOG))
00245
00246 #define IS_GPIO_SPEED(__SPEED__)    (((__SPEED__) == GPIO_SPEED_FREQ_LOW)    ||\
00247                                      ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
00248                                      ((__SPEED__) == GPIO_SPEED_FREQ_HIGH))
00249
00250 #define IS_GPIO_PULL(__PULL__)      (((__PULL__) == GPIO_NOPULL)   ||\
00251                                      ((__PULL__) == GPIO_PULLUP)   || \
00252                                      ((__PULL__) == GPIO_PULLDOWN))
00253 /**
00254   * @}
00255   */
00256
00257 /* Include GPIO HAL Extended module */
00258 #include "stm32f3xx_hal_gpio_ex.h"
00259
00260 /* Exported functions --------------------------------------------------------*/
00261 /** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
00262   * @{
00263   */
00264
00265 /** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
00266  *  @brief    Initialization and Configuration functions
00267  * @{
00268  */
00269
00270 /* Initialization and de-initialization functions *****************************/
00271 void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
00272 void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
00273
00274 /**
00275   * @}
00276   */
00277
00278 /** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions
00279  * @{
00280  */
00281
00282 /* IO operation functions *****************************************************/
00283 GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00284 void              HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
00285 void              HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00286 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00287 void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
00288 void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
00289
00290 /**
00291   * @}
00292   */
00293
00294 /**
00295   * @}
00296   */
00297
00298 /**
00299   * @}
00300   */
00301
00302 /**
00303   * @}
00304   */
00305
00306 #ifdef __cplusplus
00307 }
00308 #endif
00309
00310 #endif /* __STM32F3xx_HAL_GPIO_H */
00311
00312
00313 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_gpio_ex.h Source File

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stm32f3xx_hal_gpio_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_gpio_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of GPIO HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_GPIO_EX_H
00038 #define __STM32F3xx_HAL_GPIO_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @defgroup GPIOEx GPIOEx
00052   * @brief GPIO Extended HAL module driver
00053   * @{
00054   */
00055
00056 /* Exported types ------------------------------------------------------------*/
00057 /* Exported constants --------------------------------------------------------*/
00058 /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
00059   * @{
00060   */
00061
00062 /** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
00063   * @{
00064   */
00065
00066 #if defined (STM32F302xC)
00067 /*---------------------------------- STM32F302xC ------------------------------*/
00068 /**
00069   * @brief   AF 0 selection
00070   */
00071 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
00072 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00073 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
00074 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00075 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
00076
00077 /**
00078   * @brief   AF 1 selection
00079   */
00080 #define GPIO_AF1_TIM2           ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
00081 #define GPIO_AF1_TIM15          ((uint8_t)0x01U)  /* TIM15 Alternate Function mapping */
00082 #define GPIO_AF1_TIM16          ((uint8_t)0x01U)  /* TIM16 Alternate Function mapping */
00083 #define GPIO_AF1_TIM17          ((uint8_t)0x01U)  /* TIM17 Alternate Function mapping */
00084 #define GPIO_AF1_EVENTOUT       ((uint8_t)0x01U)  /* EVENTOUT Alternate Function mapping */
00085 /**
00086   * @brief   AF 2 selection
00087   */
00088 #define GPIO_AF2_TIM1           ((uint8_t)0x02U)  /* TIM1 Alternate Function mapping */
00089 #define GPIO_AF2_TIM2           ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping */
00090 #define GPIO_AF2_TIM3           ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
00091 #define GPIO_AF2_TIM4           ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
00092 #define GPIO_AF2_TIM15          ((uint8_t)0x02U)  /* TIM15 Alternate Function mapping */
00093 #define GPIO_AF2_COMP1          ((uint8_t)0x02U)  /* COMP1 Alternate Function mapping */
00094 /**
00095   * @brief   AF 3 selection
00096   */
00097 #define GPIO_AF3_TSC           ((uint8_t)0x03U)  /* TSC Alternate Function mapping  */
00098 #define GPIO_AF3_TIM15         ((uint8_t)0x03U)  /* TIM15 Alternate Function mapping */
00099
00100 /**
00101   * @brief   AF 4 selection
00102   */
00103 #define GPIO_AF4_TIM1          ((uint8_t)0x04U)  /* TIM1 Alternate Function mapping */
00104 #define GPIO_AF4_TIM16         ((uint8_t)0x04U)  /* TIM16 Alternate Function mapping */
00105 #define GPIO_AF4_TIM17         ((uint8_t)0x04U)  /* TIM17 Alternate Function mapping */
00106 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
00107 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
00108
00109 /**
00110   * @brief   AF 5 selection
00111   */
00112 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping */
00113 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping */
00114 #define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping */
00115 #define GPIO_AF5_I2S           ((uint8_t)0x05U)  /* I2S Alternate Function mapping */
00116 #define GPIO_AF5_I2S2ext       ((uint8_t)0x05U)  /* I2S2ext Alternate Function mapping */
00117 #define GPIO_AF5_IR            ((uint8_t)0x05U)  /* IR Alternate Function mapping */
00118 #define GPIO_AF5_UART4         ((uint8_t)0x05U)  /* UART4 Alternate Function mapping */
00119 #define GPIO_AF5_UART5         ((uint8_t)0x05U)  /* UART5 Alternate Function mapping */
00120 /**
00121   * @brief   AF 6 selection
00122   */
00123 #define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* SPI2/I2S2 Alternate Function mapping */
00124 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping */
00125 #define GPIO_AF6_I2S3ext       ((uint8_t)0x06U)  /* I2S3ext Alternate Function mapping */
00126 #define GPIO_AF6_TIM1          ((uint8_t)0x06U)  /* TIM1 Alternate Function mapping */
00127 #define GPIO_AF6_IR            ((uint8_t)0x06U)  /* IR Alternate Function mapping */
00128
00129 /**
00130   * @brief   AF 7 selection
00131   */
00132 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping  */
00133 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping  */
00134 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping  */
00135 #define GPIO_AF7_COMP6         ((uint8_t)0x07U)  /* COMP6 Alternate Function mapping  */
00136 #define GPIO_AF7_CAN           ((uint8_t)0x07U)  /* CAN Alternate Function mapping  */
00137
00138 /**
00139   * @brief   AF 8 selection
00140   */
00141 #define GPIO_AF8_COMP1         ((uint8_t)0x08U)  /* COMP1 Alternate Function mapping  */
00142 #define GPIO_AF8_COMP2         ((uint8_t)0x08U)  /* COMP2 Alternate Function mapping  */
00143 #define GPIO_AF8_COMP4         ((uint8_t)0x08U)  /* COMP4 Alternate Function mapping  */
00144 #define GPIO_AF8_COMP6         ((uint8_t)0x08U)  /* COMP6 Alternate Function mapping  */
00145
00146 /**
00147   * @brief   AF 9 selection
00148   */
00149 #define GPIO_AF9_CAN           ((uint8_t)0x09U)  /* CAN Alternate Function mapping  */
00150 #define GPIO_AF9_TIM1          ((uint8_t)0x09U)  /* TIM1 Alternate Function mapping */
00151 #define GPIO_AF9_TIM15         ((uint8_t)0x09U)  /* TIM15 Alternate Function mapping */
00152
00153 /**
00154   * @brief   AF 10 selection
00155   */
00156 #define GPIO_AF10_TIM2           ((uint8_t)0xAU)  /* TIM2 Alternate Function mapping */
00157 #define GPIO_AF10_TIM3           ((uint8_t)0xAU)  /* TIM3 Alternate Function mapping */
00158 #define GPIO_AF10_TIM4           ((uint8_t)0xAU)  /* TIM4 Alternate Function mapping */
00159 #define GPIO_AF10_TIM17          ((uint8_t)0xAU)  /* TIM17 Alternate Function mapping */
00160 /**
00161   * @brief   AF 11 selection
00162   */
00163 #define GPIO_AF11_TIM1           ((uint8_t)0x0BU)  /* TIM1 Alternate Function mapping */
00164
00165 /**
00166   * @brief   AF 12 selection
00167   */
00168 #define GPIO_AF12_TIM1            ((uint8_t)0xCU)  /* TIM1 Alternate Function mapping */
00169
00170 /**
00171   * @brief   AF 14 selection
00172   */
00173
00174 #define GPIO_AF14_USB           ((uint8_t)0x0EU)  /* USB Alternate Function mapping */
00175 /**
00176   * @brief   AF 15 selection
00177   */
00178 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
00179
00180 #define IS_GPIO_AF(AF)          (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
00181 /*------------------------------------------------------------------------------------------*/
00182 #endif /* STM32F302xC */
00183
00184 #if defined (STM32F303xC)
00185 /*---------------------------------- STM32F303xC ------------------------------*/
00186 /**
00187   * @brief   AF 0 selection
00188   */
00189 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
00190 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00191 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
00192 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00193 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
00194
00195 /**
00196   * @brief   AF 1 selection
00197   */
00198 #define GPIO_AF1_TIM2           ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
00199 #define GPIO_AF1_TIM15          ((uint8_t)0x01U)  /* TIM15 Alternate Function mapping */
00200 #define GPIO_AF1_TIM16          ((uint8_t)0x01U)  /* TIM16 Alternate Function mapping */
00201 #define GPIO_AF1_TIM17          ((uint8_t)0x01U)  /* TIM17 Alternate Function mapping */
00202 #define GPIO_AF1_EVENTOUT       ((uint8_t)0x01U)  /* EVENTOUT Alternate Function mapping */
00203 /**
00204   * @brief   AF 2 selection
00205   */
00206 #define GPIO_AF2_TIM1           ((uint8_t)0x02U)  /* TIM1 Alternate Function mapping */
00207 #define GPIO_AF2_TIM2           ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping */
00208 #define GPIO_AF2_TIM3           ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
00209 #define GPIO_AF2_TIM4           ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
00210 #define GPIO_AF2_TIM8           ((uint8_t)0x02U)  /* TIM8 Alternate Function mapping */
00211 #define GPIO_AF2_TIM15          ((uint8_t)0x02U)  /* TIM15 Alternate Function mapping */
00212 #define GPIO_AF2_COMP1          ((uint8_t)0x02U)  /* COMP1 Alternate Function mapping */
00213 /**
00214   * @brief   AF 3 selection
00215   */
00216 #define GPIO_AF3_TSC           ((uint8_t)0x03U)  /* TSC Alternate Function mapping  */
00217 #define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
00218 #define GPIO_AF3_COMP7         ((uint8_t)0x03U)  /* COMP7 Alternate Function mapping */
00219 #define GPIO_AF3_TIM15         ((uint8_t)0x03U)  /* TIM15 Alternate Function mapping */
00220
00221 /**
00222   * @brief   AF 4 selection
00223   */
00224 #define GPIO_AF4_TIM1          ((uint8_t)0x04U)  /* TIM1 Alternate Function mapping */
00225 #define GPIO_AF4_TIM8          ((uint8_t)0x04U)  /* TIM8 Alternate Function mapping */
00226 #define GPIO_AF4_TIM16         ((uint8_t)0x04U)  /* TIM16 Alternate Function mapping */
00227 #define GPIO_AF4_TIM17         ((uint8_t)0x04U)  /* TIM17 Alternate Function mapping */
00228 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
00229 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
00230
00231 /**
00232   * @brief   AF 5 selection
00233   */
00234 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping */
00235 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping */
00236 #define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping */
00237 #define GPIO_AF5_I2S           ((uint8_t)0x05U)  /* I2S Alternate Function mapping */
00238 #define GPIO_AF5_I2S2ext       ((uint8_t)0x05U)  /* I2S2ext Alternate Function mapping */
00239 #define GPIO_AF5_TIM8          ((uint8_t)0x05U)  /* TIM8 Alternate Function mapping */
00240 #define GPIO_AF5_IR            ((uint8_t)0x05U)  /* IR Alternate Function mapping */
00241 #define GPIO_AF5_UART4         ((uint8_t)0x05U)  /* UART4 Alternate Function mapping */
00242 #define GPIO_AF5_UART5         ((uint8_t)0x05U)  /* UART5 Alternate Function mapping */
00243 /**
00244   * @brief   AF 6 selection
00245   */
00246 #define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* SPI2/I2S2 Alternate Function mapping */
00247 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping */
00248 #define GPIO_AF6_I2S3ext       ((uint8_t)0x06U)  /* I2S3ext Alternate Function mapping */
00249 #define GPIO_AF6_TIM1          ((uint8_t)0x06U)  /* TIM1 Alternate Function mapping */
00250 #define GPIO_AF6_TIM8          ((uint8_t)0x06U)  /* TIM8 Alternate Function mapping */
00251 #define GPIO_AF6_IR            ((uint8_t)0x06U)  /* IR Alternate Function mapping */
00252
00253 /**
00254   * @brief   AF 7 selection
00255   */
00256 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping  */
00257 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping  */
00258 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping  */
00259 #define GPIO_AF7_COMP3         ((uint8_t)0x07U)  /* COMP3 Alternate Function mapping  */
00260 #define GPIO_AF7_COMP5         ((uint8_t)0x07U)  /* COMP5 Alternate Function mapping  */
00261 #define GPIO_AF7_COMP6         ((uint8_t)0x07U)  /* COMP6 Alternate Function mapping  */
00262 #define GPIO_AF7_CAN           ((uint8_t)0x07U)  /* CAN Alternate Function mapping  */
00263
00264 /**
00265   * @brief   AF 8 selection
00266   */
00267 #define GPIO_AF8_COMP1         ((uint8_t)0x08U)  /* COMP1 Alternate Function mapping  */
00268 #define GPIO_AF8_COMP2         ((uint8_t)0x08U)  /* COMP2 Alternate Function mapping  */
00269 #define GPIO_AF8_COMP3         ((uint8_t)0x08U)  /* COMP3 Alternate Function mapping  */
00270 #define GPIO_AF8_COMP4         ((uint8_t)0x08U)  /* COMP4 Alternate Function mapping  */
00271 #define GPIO_AF8_COMP5         ((uint8_t)0x08U)  /* COMP5 Alternate Function mapping  */
00272 #define GPIO_AF8_COMP6         ((uint8_t)0x08U)  /* COMP6 Alternate Function mapping  */
00273
00274 /**
00275   * @brief   AF 9 selection
00276   */
00277 #define GPIO_AF9_CAN           ((uint8_t)0x09U)  /* CAN Alternate Function mapping  */
00278 #define GPIO_AF9_TIM1          ((uint8_t)0x09U)  /* TIM1 Alternate Function mapping */
00279 #define GPIO_AF9_TIM8          ((uint8_t)0x09U)  /* TIM8 Alternate Function mapping */
00280 #define GPIO_AF9_TIM15         ((uint8_t)0x09U)  /* TIM15 Alternate Function mapping */
00281
00282 /**
00283   * @brief   AF 10 selection
00284   */
00285 #define GPIO_AF10_TIM2           ((uint8_t)0xAU)  /* TIM2 Alternate Function mapping */
00286 #define GPIO_AF10_TIM3           ((uint8_t)0xAU)  /* TIM3 Alternate Function mapping */
00287 #define GPIO_AF10_TIM4           ((uint8_t)0xAU)  /* TIM4 Alternate Function mapping */
00288 #define GPIO_AF10_TIM8           ((uint8_t)0xAU)  /* TIM8 Alternate Function mapping */
00289 #define GPIO_AF10_TIM17          ((uint8_t)0xAU)  /* TIM17 Alternate Function mapping */
00290 /**
00291   * @brief   AF 11 selection
00292   */
00293 #define GPIO_AF11_TIM1           ((uint8_t)0x0BU)  /* TIM1 Alternate Function mapping */
00294 #define GPIO_AF11_TIM8           ((uint8_t)0x0BU)  /* TIM8 Alternate Function mapping */
00295
00296 /**
00297   * @brief   AF 12 selection
00298   */
00299 #define GPIO_AF12_TIM1            ((uint8_t)0xCU)  /* TIM1 Alternate Function mapping */
00300
00301 /**
00302   * @brief   AF 14 selection
00303   */
00304
00305 #define GPIO_AF14_USB           ((uint8_t)0x0EU)  /* USB Alternate Function mapping */
00306 /**
00307   * @brief   AF 15 selection
00308   */
00309 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
00310
00311 #define IS_GPIO_AF(AF)          (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
00312 /*------------------------------------------------------------------------------------------*/
00313 #endif /* STM32F303xC */
00314
00315 #if defined (STM32F303xE)
00316 /*---------------------------------- STM32F303xE ------------------------------*/
00317 /**
00318   * @brief   AF 0 selection
00319   */
00320 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
00321 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00322 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
00323 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00324 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
00325
00326 /**
00327   * @brief   AF 1 selection
00328   */
00329 #define GPIO_AF1_TIM2           ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
00330 #define GPIO_AF1_TIM15          ((uint8_t)0x01U)  /* TIM15 Alternate Function mapping */
00331 #define GPIO_AF1_TIM16          ((uint8_t)0x01U)  /* TIM16 Alternate Function mapping */
00332 #define GPIO_AF1_TIM17          ((uint8_t)0x01U)  /* TIM17 Alternate Function mapping */
00333 #define GPIO_AF1_EVENTOUT       ((uint8_t)0x01U)  /* EVENTOUT Alternate Function mapping */
00334
00335 /**
00336   * @brief   AF 2 selection
00337   */
00338 #define GPIO_AF2_TIM1           ((uint8_t)0x02U)  /* TIM1 Alternate Function mapping */
00339 #define GPIO_AF2_TIM2           ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping */
00340 #define GPIO_AF2_TIM3           ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
00341 #define GPIO_AF2_TIM4           ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
00342 #define GPIO_AF2_TIM8           ((uint8_t)0x02U)  /* TIM8 Alternate Function mapping */
00343 #define GPIO_AF2_TIM15          ((uint8_t)0x02U)  /* TIM15 Alternate Function mapping */
00344 #define GPIO_AF2_COMP1          ((uint8_t)0x02U)  /* COMP1 Alternate Function mapping */
00345 #define GPIO_AF2_I2C3           ((uint8_t)0x02U)  /* I2C3 Alternate Function mapping */
00346 #define GPIO_AF2_TIM20          ((uint8_t)0x02U)  /* TIM20 Alternate Function mapping */
00347
00348 /**
00349   * @brief   AF 3 selection
00350   */
00351 #define GPIO_AF3_TSC           ((uint8_t)0x03U)  /* TSC Alternate Function mapping  */
00352 #define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
00353 #define GPIO_AF3_COMP7         ((uint8_t)0x03U)  /* COMP7 Alternate Function mapping */
00354 #define GPIO_AF3_TIM15         ((uint8_t)0x03U)  /* TIM15 Alternate Function mapping */
00355 #define GPIO_AF3_I2C3          ((uint8_t)0x03U)  /* I2C3 Alternate Function mapping */
00356 #define GPIO_AF3_TIM20         ((uint8_t)0x03U)  /* TIM20 Alternate Function mapping */
00357
00358 /**
00359   * @brief   AF 4 selection
00360   */
00361 #define GPIO_AF4_TIM1          ((uint8_t)0x04U)  /* TIM1 Alternate Function mapping */
00362 #define GPIO_AF4_TIM8          ((uint8_t)0x04U)  /* TIM8 Alternate Function mapping */
00363 #define GPIO_AF4_TIM16         ((uint8_t)0x04U)  /* TIM16 Alternate Function mapping */
00364 #define GPIO_AF4_TIM17         ((uint8_t)0x04U)  /* TIM17 Alternate Function mapping */
00365 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
00366 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
00367
00368 /**
00369   * @brief   AF 5 selection
00370   */
00371 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping */
00372 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping */
00373 #define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping */
00374 #define GPIO_AF5_I2S           ((uint8_t)0x05U)  /* I2S Alternate Function mapping */
00375 #define GPIO_AF5_I2S2ext       ((uint8_t)0x05U)  /* I2S2ext Alternate Function mapping */
00376 #define GPIO_AF5_TIM8          ((uint8_t)0x05U)  /* TIM8 Alternate Function mapping */
00377 #define GPIO_AF5_IR            ((uint8_t)0x05U)  /* IR Alternate Function mapping */
00378 #define GPIO_AF5_UART4         ((uint8_t)0x05U)  /* UART4 Alternate Function mapping */
00379 #define GPIO_AF5_UART5         ((uint8_t)0x05U)  /* UART5 Alternate Function mapping */
00380 #define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping */
00381
00382 /**
00383   * @brief   AF 6 selection
00384   */
00385 #define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* SPI2/I2S2 Alternate Function mapping */
00386 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping */
00387 #define GPIO_AF6_I2S3ext       ((uint8_t)0x06U)  /* I2S3ext Alternate Function mapping */
00388 #define GPIO_AF6_TIM1          ((uint8_t)0x06U)  /* TIM1 Alternate Function mapping */
00389 #define GPIO_AF6_TIM8          ((uint8_t)0x06U)  /* TIM8 Alternate Function mapping */
00390 #define GPIO_AF6_IR            ((uint8_t)0x06U)  /* IR Alternate Function mapping */
00391 #define GPIO_AF6_TIM20         ((uint8_t)0x06U)  /* TIM20 Alternate Function mapping */
00392
00393 /**
00394   * @brief   AF 7 selection
00395   */
00396 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping  */
00397 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping  */
00398 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping  */
00399 #define GPIO_AF7_COMP3         ((uint8_t)0x07U)  /* COMP3 Alternate Function mapping  */
00400 #define GPIO_AF7_COMP5         ((uint8_t)0x07U)  /* COMP5 Alternate Function mapping  */
00401 #define GPIO_AF7_COMP6         ((uint8_t)0x07U)  /* COMP6 Alternate Function mapping  */
00402 #define GPIO_AF7_CAN           ((uint8_t)0x07U)  /* CAN Alternate Function mapping  */
00403
00404 /**
00405   * @brief   AF 8 selection
00406   */
00407 #define GPIO_AF8_COMP1         ((uint8_t)0x08U)  /* COMP1 Alternate Function mapping  */
00408 #define GPIO_AF8_COMP2         ((uint8_t)0x08U)  /* COMP2 Alternate Function mapping  */
00409 #define GPIO_AF8_COMP3         ((uint8_t)0x08U)  /* COMP3 Alternate Function mapping  */
00410 #define GPIO_AF8_COMP4         ((uint8_t)0x08U)  /* COMP4 Alternate Function mapping  */
00411 #define GPIO_AF8_COMP5         ((uint8_t)0x08U)  /* COMP5 Alternate Function mapping  */
00412 #define GPIO_AF8_COMP6         ((uint8_t)0x08U)  /* COMP6 Alternate Function mapping  */
00413 #define GPIO_AF8_I2C3          ((uint8_t)0x08U)  /* I2C3 Alternate Function mapping */
00414
00415 /**
00416   * @brief   AF 9 selection
00417   */
00418 #define GPIO_AF9_CAN           ((uint8_t)0x09U)  /* CAN Alternate Function mapping  */
00419 #define GPIO_AF9_TIM1          ((uint8_t)0x09U)  /* TIM1 Alternate Function mapping */
00420 #define GPIO_AF9_TIM8          ((uint8_t)0x09U)  /* TIM8 Alternate Function mapping */
00421 #define GPIO_AF9_TIM15         ((uint8_t)0x09U)  /* TIM15 Alternate Function mapping */
00422
00423 /**
00424   * @brief   AF 10 selection
00425   */
00426 #define GPIO_AF10_TIM2           ((uint8_t)0xAU)  /* TIM2 Alternate Function mapping */
00427 #define GPIO_AF10_TIM3           ((uint8_t)0xAU)  /* TIM3 Alternate Function mapping */
00428 #define GPIO_AF10_TIM4           ((uint8_t)0xAU)  /* TIM4 Alternate Function mapping */
00429 #define GPIO_AF10_TIM8           ((uint8_t)0xAU)  /* TIM8 Alternate Function mapping */
00430 #define GPIO_AF10_TIM17          ((uint8_t)0xAU)  /* TIM17 Alternate Function mapping */
00431 /**
00432   * @brief   AF 11 selection
00433   */
00434 #define GPIO_AF11_TIM1           ((uint8_t)0x0BU)  /* TIM1 Alternate Function mapping */
00435 #define GPIO_AF11_TIM8           ((uint8_t)0x0BU)  /* TIM8 Alternate Function mapping */
00436
00437 /**
00438   * @brief   AF 12 selection
00439   */
00440 #define GPIO_AF12_TIM1            ((uint8_t)0xCU)  /* TIM1 Alternate Function mapping */
00441 #define GPIO_AF12_FMC             ((uint8_t)0xCU)  /* FMC Alternate Function mapping                      */
00442 #define GPIO_AF12_SDIO            ((uint8_t)0xCU)  /* SDIO Alternate Function mapping                     */
00443
00444 /**
00445   * @brief   AF 14 selection
00446   */
00447 #define GPIO_AF14_USB           ((uint8_t)0x0EU)  /* USB Alternate Function mapping */
00448
00449 /**
00450   * @brief   AF 15 selection
00451   */
00452 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
00453
00454 #define IS_GPIO_AF(AF)          (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
00455 /*------------------------------------------------------------------------------------------*/
00456 #endif /* STM32F303xE */
00457
00458 #if defined (STM32F302xE)
00459 /*---------------------------------- STM32F302xE ------------------------------*/
00460 /**
00461   * @brief   AF 0 selection
00462   */
00463 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
00464 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00465 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
00466 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00467 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
00468
00469 /**
00470   * @brief   AF 1 selection
00471   */
00472 #define GPIO_AF1_TIM2           ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
00473 #define GPIO_AF1_TIM15          ((uint8_t)0x01U)  /* TIM15 Alternate Function mapping */
00474 #define GPIO_AF1_TIM16          ((uint8_t)0x01U)  /* TIM16 Alternate Function mapping */
00475 #define GPIO_AF1_TIM17          ((uint8_t)0x01U)  /* TIM17 Alternate Function mapping */
00476 #define GPIO_AF1_EVENTOUT       ((uint8_t)0x01U)  /* EVENTOUT Alternate Function mapping */
00477
00478 /**
00479   * @brief   AF 2 selection
00480   */
00481 #define GPIO_AF2_TIM1           ((uint8_t)0x02U)  /* TIM1 Alternate Function mapping */
00482 #define GPIO_AF2_TIM2           ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping */
00483 #define GPIO_AF2_TIM3           ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
00484 #define GPIO_AF2_TIM4           ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
00485 #define GPIO_AF2_TIM15          ((uint8_t)0x02U)  /* TIM15 Alternate Function mapping */
00486 #define GPIO_AF2_COMP1          ((uint8_t)0x02U)  /* COMP1 Alternate Function mapping */
00487 #define GPIO_AF2_I2C3           ((uint8_t)0x02U)  /* I2C3 Alternate Function mapping */
00488
00489 /**
00490   * @brief   AF 3 selection
00491   */
00492 #define GPIO_AF3_TSC           ((uint8_t)0x03U)  /* TSC Alternate Function mapping  */
00493 #define GPIO_AF3_TIM15         ((uint8_t)0x03U)  /* TIM15 Alternate Function mapping */
00494 #define GPIO_AF3_I2C3          ((uint8_t)0x03U)  /* I2C3 Alternate Function mapping */
00495
00496 /**
00497   * @brief   AF 4 selection
00498   */
00499 #define GPIO_AF4_TIM1          ((uint8_t)0x04U)  /* TIM1 Alternate Function mapping */
00500 #define GPIO_AF4_TIM16         ((uint8_t)0x04U)  /* TIM16 Alternate Function mapping */
00501 #define GPIO_AF4_TIM17         ((uint8_t)0x04U)  /* TIM17 Alternate Function mapping */
00502 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
00503 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
00504
00505 /**
00506   * @brief   AF 5 selection
00507   */
00508 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping */
00509 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping */
00510 #define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping */
00511 #define GPIO_AF5_I2S           ((uint8_t)0x05U)  /* I2S Alternate Function mapping */
00512 #define GPIO_AF5_I2S2ext       ((uint8_t)0x05U)  /* I2S2ext Alternate Function mapping */
00513 #define GPIO_AF5_IR            ((uint8_t)0x05U)  /* IR Alternate Function mapping */
00514 #define GPIO_AF5_UART4         ((uint8_t)0x05U)  /* UART4 Alternate Function mapping */
00515 #define GPIO_AF5_UART5         ((uint8_t)0x05U)  /* UART5 Alternate Function mapping */
00516 #define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping */
00517
00518 /**
00519   * @brief   AF 6 selection
00520   */
00521 #define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* SPI2/I2S2 Alternate Function mapping */
00522 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping */
00523 #define GPIO_AF6_I2S3ext       ((uint8_t)0x06U)  /* I2S3ext Alternate Function mapping */
00524 #define GPIO_AF6_TIM1          ((uint8_t)0x06U)  /* TIM1 Alternate Function mapping */
00525 #define GPIO_AF6_IR            ((uint8_t)0x06U)  /* IR Alternate Function mapping */
00526
00527 /**
00528   * @brief   AF 7 selection
00529   */
00530 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping  */
00531 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping  */
00532 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping  */
00533 #define GPIO_AF7_COMP6         ((uint8_t)0x07U)  /* COMP6 Alternate Function mapping  */
00534 #define GPIO_AF7_CAN           ((uint8_t)0x07U)  /* CAN Alternate Function mapping  */
00535
00536 /**
00537   * @brief   AF 8 selection
00538   */
00539 #define GPIO_AF8_COMP1         ((uint8_t)0x08U)  /* COMP1 Alternate Function mapping  */
00540 #define GPIO_AF8_COMP2         ((uint8_t)0x08U)  /* COMP2 Alternate Function mapping  */
00541 #define GPIO_AF8_COMP4         ((uint8_t)0x08U)  /* COMP4 Alternate Function mapping  */
00542 #define GPIO_AF8_COMP6         ((uint8_t)0x08U)  /* COMP6 Alternate Function mapping  */
00543 #define GPIO_AF8_I2C3          ((uint8_t)0x08U)  /* I2C3 Alternate Function mapping */
00544
00545 /**
00546   * @brief   AF 9 selection
00547   */
00548 #define GPIO_AF9_CAN           ((uint8_t)0x09U)  /* CAN Alternate Function mapping  */
00549 #define GPIO_AF9_TIM1          ((uint8_t)0x09U)  /* TIM1 Alternate Function mapping */
00550 #define GPIO_AF9_TIM15         ((uint8_t)0x09U)  /* TIM15 Alternate Function mapping */
00551
00552 /**
00553   * @brief   AF 10 selection
00554   */
00555 #define GPIO_AF10_TIM2           ((uint8_t)0xAU)  /* TIM2 Alternate Function mapping */
00556 #define GPIO_AF10_TIM3           ((uint8_t)0xAU)  /* TIM3 Alternate Function mapping */
00557 #define GPIO_AF10_TIM4           ((uint8_t)0xAU)  /* TIM4 Alternate Function mapping */
00558 #define GPIO_AF10_TIM17          ((uint8_t)0xAU)  /* TIM17 Alternate Function mapping */
00559 /**
00560   * @brief   AF 11 selection
00561   */
00562 #define GPIO_AF11_TIM1           ((uint8_t)0x0BU)  /* TIM1 Alternate Function mapping */
00563
00564 /**
00565   * @brief   AF 12 selection
00566   */
00567 #define GPIO_AF12_TIM1            ((uint8_t)0xCU)  /* TIM1 Alternate Function mapping */
00568 #define GPIO_AF12_FMC             ((uint8_t)0xCU)  /* FMC Alternate Function mapping                      */
00569 #define GPIO_AF12_SDIO            ((uint8_t)0xCU)  /* SDIO Alternate Function mapping                     */
00570
00571 /**
00572   * @brief   AF 14 selection
00573   */
00574 #define GPIO_AF14_USB           ((uint8_t)0x0EU)  /* USB Alternate Function mapping */
00575
00576 /**
00577   * @brief   AF 15 selection
00578   */
00579 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
00580
00581 #define IS_GPIO_AF(AF)          (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
00582 /*------------------------------------------------------------------------------------------*/
00583 #endif /* STM32F302xE */
00584
00585 #if defined (STM32F398xx)
00586 /*---------------------------------- STM32F398xx ------------------------------*/
00587 /**
00588   * @brief   AF 0 selection
00589   */
00590 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
00591 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00592 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
00593 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00594 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
00595
00596 /**
00597   * @brief   AF 1 selection
00598   */
00599 #define GPIO_AF1_TIM2           ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
00600 #define GPIO_AF1_TIM15          ((uint8_t)0x01U)  /* TIM15 Alternate Function mapping */
00601 #define GPIO_AF1_TIM16          ((uint8_t)0x01U)  /* TIM16 Alternate Function mapping */
00602 #define GPIO_AF1_TIM17          ((uint8_t)0x01U)  /* TIM17 Alternate Function mapping */
00603 #define GPIO_AF1_EVENTOUT       ((uint8_t)0x01U)  /* EVENTOUT Alternate Function mapping */
00604
00605 /**
00606   * @brief   AF 2 selection
00607   */
00608 #define GPIO_AF2_TIM1           ((uint8_t)0x02U)  /* TIM1 Alternate Function mapping */
00609 #define GPIO_AF2_TIM2           ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping */
00610 #define GPIO_AF2_TIM3           ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
00611 #define GPIO_AF2_TIM4           ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
00612 #define GPIO_AF2_TIM8           ((uint8_t)0x02U)  /* TIM8 Alternate Function mapping */
00613 #define GPIO_AF2_TIM15          ((uint8_t)0x02U)  /* TIM15 Alternate Function mapping */
00614 #define GPIO_AF2_COMP1          ((uint8_t)0x02U)  /* COMP1 Alternate Function mapping */
00615 #define GPIO_AF2_I2C3           ((uint8_t)0x02U)  /* I2C3 Alternate Function mapping */
00616 #define GPIO_AF2_TIM20          ((uint8_t)0x02U)  /* TIM20 Alternate Function mapping */
00617
00618 /**
00619   * @brief   AF 3 selection
00620   */
00621 #define GPIO_AF3_TSC           ((uint8_t)0x03U)  /* TSC Alternate Function mapping  */
00622 #define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
00623 #define GPIO_AF3_COMP7         ((uint8_t)0x03U)  /* COMP7 Alternate Function mapping */
00624 #define GPIO_AF3_TIM15         ((uint8_t)0x03U)  /* TIM15 Alternate Function mapping */
00625 #define GPIO_AF3_I2C3          ((uint8_t)0x03U)  /* I2C3 Alternate Function mapping */
00626 #define GPIO_AF3_TIM20         ((uint8_t)0x03U)  /* TIM20 Alternate Function mapping */
00627
00628 /**
00629   * @brief   AF 4 selection
00630   */
00631 #define GPIO_AF4_TIM1          ((uint8_t)0x04U)  /* TIM1 Alternate Function mapping */
00632 #define GPIO_AF4_TIM8          ((uint8_t)0x04U)  /* TIM8 Alternate Function mapping */
00633 #define GPIO_AF4_TIM16         ((uint8_t)0x04U)  /* TIM16 Alternate Function mapping */
00634 #define GPIO_AF4_TIM17         ((uint8_t)0x04U)  /* TIM17 Alternate Function mapping */
00635 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
00636 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
00637
00638 /**
00639   * @brief   AF 5 selection
00640   */
00641 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping */
00642 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping */
00643 #define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping */
00644 #define GPIO_AF5_I2S           ((uint8_t)0x05U)  /* I2S Alternate Function mapping */
00645 #define GPIO_AF5_I2S2ext       ((uint8_t)0x05U)  /* I2S2ext Alternate Function mapping */
00646 #define GPIO_AF5_TIM8          ((uint8_t)0x05U)  /* TIM8 Alternate Function mapping */
00647 #define GPIO_AF5_IR            ((uint8_t)0x05U)  /* IR Alternate Function mapping */
00648 #define GPIO_AF5_UART4         ((uint8_t)0x05U)  /* UART4 Alternate Function mapping */
00649 #define GPIO_AF5_UART5         ((uint8_t)0x05U)  /* UART5 Alternate Function mapping */
00650 #define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping */
00651
00652 /**
00653   * @brief   AF 6 selection
00654   */
00655 #define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* SPI2/I2S2 Alternate Function mapping */
00656 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping */
00657 #define GPIO_AF6_I2S3ext       ((uint8_t)0x06U)  /* I2S3ext Alternate Function mapping */
00658 #define GPIO_AF6_TIM1          ((uint8_t)0x06U)  /* TIM1 Alternate Function mapping */
00659 #define GPIO_AF6_TIM8          ((uint8_t)0x06U)  /* TIM8 Alternate Function mapping */
00660 #define GPIO_AF6_IR            ((uint8_t)0x06U)  /* IR Alternate Function mapping */
00661 #define GPIO_AF6_TIM20         ((uint8_t)0x06U)  /* TIM20 Alternate Function mapping */
00662
00663 /**
00664   * @brief   AF 7 selection
00665   */
00666 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping  */
00667 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping  */
00668 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping  */
00669 #define GPIO_AF7_COMP3         ((uint8_t)0x07U)  /* COMP3 Alternate Function mapping  */
00670 #define GPIO_AF7_COMP5         ((uint8_t)0x07U)  /* COMP5 Alternate Function mapping  */
00671 #define GPIO_AF7_COMP6         ((uint8_t)0x07U)  /* COMP6 Alternate Function mapping  */
00672 #define GPIO_AF7_CAN           ((uint8_t)0x07U)  /* CAN Alternate Function mapping  */
00673
00674 /**
00675   * @brief   AF 8 selection
00676   */
00677 #define GPIO_AF8_COMP1         ((uint8_t)0x08U)  /* COMP1 Alternate Function mapping  */
00678 #define GPIO_AF8_COMP2         ((uint8_t)0x08U)  /* COMP2 Alternate Function mapping  */
00679 #define GPIO_AF8_COMP3         ((uint8_t)0x08U)  /* COMP3 Alternate Function mapping  */
00680 #define GPIO_AF8_COMP4         ((uint8_t)0x08U)  /* COMP4 Alternate Function mapping  */
00681 #define GPIO_AF8_COMP5         ((uint8_t)0x08U)  /* COMP5 Alternate Function mapping  */
00682 #define GPIO_AF8_COMP6         ((uint8_t)0x08U)  /* COMP6 Alternate Function mapping  */
00683 #define GPIO_AF8_I2C3          ((uint8_t)0x08U)  /* I2C3 Alternate Function mapping */
00684
00685 /**
00686   * @brief   AF 9 selection
00687   */
00688 #define GPIO_AF9_CAN           ((uint8_t)0x09U)  /* CAN Alternate Function mapping  */
00689 #define GPIO_AF9_TIM1          ((uint8_t)0x09U)  /* TIM1 Alternate Function mapping */
00690 #define GPIO_AF9_TIM8          ((uint8_t)0x09U)  /* TIM8 Alternate Function mapping */
00691 #define GPIO_AF9_TIM15         ((uint8_t)0x09U)  /* TIM15 Alternate Function mapping */
00692
00693 /**
00694   * @brief   AF 10 selection
00695   */
00696 #define GPIO_AF10_TIM2           ((uint8_t)0xAU)  /* TIM2 Alternate Function mapping */
00697 #define GPIO_AF10_TIM3           ((uint8_t)0xAU)  /* TIM3 Alternate Function mapping */
00698 #define GPIO_AF10_TIM4           ((uint8_t)0xAU)  /* TIM4 Alternate Function mapping */
00699 #define GPIO_AF10_TIM8           ((uint8_t)0xAU)  /* TIM8 Alternate Function mapping */
00700 #define GPIO_AF10_TIM17          ((uint8_t)0xAU)  /* TIM17 Alternate Function mapping */
00701 /**
00702   * @brief   AF 11 selection
00703   */
00704 #define GPIO_AF11_TIM1           ((uint8_t)0x0BU)  /* TIM1 Alternate Function mapping */
00705 #define GPIO_AF11_TIM8           ((uint8_t)0x0BU)  /* TIM8 Alternate Function mapping */
00706
00707 /**
00708   * @brief   AF 12 selection
00709   */
00710 #define GPIO_AF12_TIM1            ((uint8_t)0xCU)  /* TIM1 Alternate Function mapping */
00711 #define GPIO_AF12_FMC             ((uint8_t)0xCU)  /* FMC Alternate Function mapping                      */
00712 #define GPIO_AF12_SDIO            ((uint8_t)0xCU)  /* SDIO Alternate Function mapping                     */
00713
00714 /**
00715   * @brief   AF 15 selection
00716   */
00717 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
00718
00719 #define IS_GPIO_AF(AF)          (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU))
00720 /*------------------------------------------------------------------------------------------*/
00721 #endif /* STM32F398xx */
00722
00723 #if defined (STM32F358xx)
00724 /*---------------------------------- STM32F358xx -------------------------------------------*/
00725 /**
00726   * @brief   AF 0 selection
00727   */
00728 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
00729 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00730 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
00731 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00732 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
00733
00734 /**
00735   * @brief   AF 1 selection
00736   */
00737 #define GPIO_AF1_TIM2           ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
00738 #define GPIO_AF1_TIM15          ((uint8_t)0x01U)  /* TIM15 Alternate Function mapping */
00739 #define GPIO_AF1_TIM16          ((uint8_t)0x01U)  /* TIM16 Alternate Function mapping */
00740 #define GPIO_AF1_TIM17          ((uint8_t)0x01U)  /* TIM17 Alternate Function mapping */
00741 #define GPIO_AF1_EVENTOUT       ((uint8_t)0x01U)  /* EVENTOUT Alternate Function mapping */
00742 /**
00743   * @brief   AF 2 selection
00744   */
00745 #define GPIO_AF2_TIM1           ((uint8_t)0x02U)  /* TIM1 Alternate Function mapping */
00746 #define GPIO_AF2_TIM2           ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping */
00747 #define GPIO_AF2_TIM3           ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
00748 #define GPIO_AF2_TIM4           ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
00749 #define GPIO_AF2_TIM8           ((uint8_t)0x02U)  /* TIM8 Alternate Function mapping */
00750 #define GPIO_AF2_TIM15          ((uint8_t)0x02U)  /* TIM15 Alternate Function mapping */
00751 #define GPIO_AF2_COMP1          ((uint8_t)0x02U)  /* COMP1 Alternate Function mapping */
00752 /**
00753   * @brief   AF 3 selection
00754   */
00755 #define GPIO_AF3_TSC           ((uint8_t)0x03U)  /* TSC Alternate Function mapping  */
00756 #define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
00757 #define GPIO_AF3_COMP7         ((uint8_t)0x03U)  /* COMP7 Alternate Function mapping */
00758 #define GPIO_AF3_TIM15         ((uint8_t)0x03U)  /* TIM15 Alternate Function mapping */
00759
00760 /**
00761   * @brief   AF 4 selection
00762   */
00763 #define GPIO_AF4_TIM1          ((uint8_t)0x04U)  /* TIM1 Alternate Function mapping */
00764 #define GPIO_AF4_TIM8          ((uint8_t)0x04U)  /* TIM8 Alternate Function mapping */
00765 #define GPIO_AF4_TIM16         ((uint8_t)0x04U)  /* TIM16 Alternate Function mapping */
00766 #define GPIO_AF4_TIM17         ((uint8_t)0x04U)  /* TIM17 Alternate Function mapping */
00767 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
00768 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
00769
00770 /**
00771   * @brief   AF 5 selection
00772   */
00773 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping      */
00774 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping */
00775 #define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping */
00776 #define GPIO_AF5_I2S           ((uint8_t)0x05U)  /* I2S Alternate Function mapping */
00777 #define GPIO_AF5_I2S2ext       ((uint8_t)0x05U)  /* I2S2ext Alternate Function mapping */
00778 #define GPIO_AF5_TIM8          ((uint8_t)0x05U)  /* TIM8 Alternate Function mapping */
00779 #define GPIO_AF5_IR            ((uint8_t)0x05U)  /* IR Alternate Function mapping */
00780 #define GPIO_AF5_UART4         ((uint8_t)0x05U)  /* UART4 Alternate Function mapping */
00781 #define GPIO_AF5_UART5         ((uint8_t)0x05U)  /* UART5 Alternate Function mapping */
00782 /**
00783   * @brief   AF 6 selection
00784   */
00785 #define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* SPI2/I2S2 Alternate Function mapping */
00786 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping */
00787 #define GPIO_AF6_I2S3ext       ((uint8_t)0x06U)  /* I2S3ext Alternate Function mapping */
00788 #define GPIO_AF6_TIM1          ((uint8_t)0x06U)  /* TIM1 Alternate Function mapping */
00789 #define GPIO_AF6_TIM8          ((uint8_t)0x06U)  /* TIM8 Alternate Function mapping */
00790 #define GPIO_AF6_IR            ((uint8_t)0x06U)  /* IR Alternate Function mapping */
00791
00792 /**
00793   * @brief   AF 7 selection
00794   */
00795 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping  */
00796 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping  */
00797 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping  */
00798 #define GPIO_AF7_COMP3         ((uint8_t)0x07U)  /* COMP3 Alternate Function mapping  */
00799 #define GPIO_AF7_COMP5         ((uint8_t)0x07U)  /* COMP5 Alternate Function mapping  */
00800 #define GPIO_AF7_COMP6         ((uint8_t)0x07U)  /* COMP6 Alternate Function mapping  */
00801 #define GPIO_AF7_CAN           ((uint8_t)0x07U)  /* CAN Alternate Function mapping  */
00802
00803 /**
00804   * @brief   AF 8 selection
00805   */
00806 #define GPIO_AF8_COMP1         ((uint8_t)0x08U)  /* COMP1 Alternate Function mapping  */
00807 #define GPIO_AF8_COMP2         ((uint8_t)0x08U)  /* COMP2 Alternate Function mapping  */
00808 #define GPIO_AF8_COMP3         ((uint8_t)0x08U)  /* COMP3 Alternate Function mapping  */
00809 #define GPIO_AF8_COMP4         ((uint8_t)0x08U)  /* COMP4 Alternate Function mapping  */
00810 #define GPIO_AF8_COMP5         ((uint8_t)0x08U)  /* COMP5 Alternate Function mapping  */
00811 #define GPIO_AF8_COMP6         ((uint8_t)0x08U)  /* COMP6 Alternate Function mapping  */
00812
00813 /**
00814   * @brief   AF 9 selection
00815   */
00816 #define GPIO_AF9_CAN           ((uint8_t)0x09U)  /* CAN Alternate Function mapping  */
00817 #define GPIO_AF9_TIM1          ((uint8_t)0x09U)  /* TIM1 Alternate Function mapping */
00818 #define GPIO_AF9_TIM8          ((uint8_t)0x09U)  /* TIM8 Alternate Function mapping */
00819 #define GPIO_AF9_TIM15         ((uint8_t)0x09U)  /* TIM15 Alternate Function mapping */
00820
00821 /**
00822   * @brief   AF 10 selection
00823   */
00824 #define GPIO_AF10_TIM2           ((uint8_t)0xAU)  /* TIM2 Alternate Function mapping */
00825 #define GPIO_AF10_TIM3           ((uint8_t)0xAU)  /* TIM3 Alternate Function mapping */
00826 #define GPIO_AF10_TIM4           ((uint8_t)0xAU)  /* TIM4 Alternate Function mapping */
00827 #define GPIO_AF10_TIM8           ((uint8_t)0xAU)  /* TIM8 Alternate Function mapping */
00828 #define GPIO_AF10_TIM17          ((uint8_t)0xAU)  /* TIM17 Alternate Function mapping */
00829 /**
00830   * @brief   AF 11 selection
00831   */
00832 #define GPIO_AF11_TIM1           ((uint8_t)0x0BU)  /* TIM1 Alternate Function mapping */
00833 #define GPIO_AF11_TIM8           ((uint8_t)0x0BU)  /* TIM8 Alternate Function mapping */
00834
00835 /**
00836   * @brief   AF 12 selection
00837   */
00838 #define GPIO_AF12_TIM1            ((uint8_t)0xCU)  /* TIM1 Alternate Function mapping */
00839
00840 /**
00841   * @brief   AF 15 selection
00842   */
00843 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
00844
00845 #define IS_GPIO_AF(AF)          (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU))
00846 /*------------------------------------------------------------------------------------------*/
00847 #endif /* STM32F358xx */
00848
00849 #if  defined (STM32F373xC)
00850 /*---------------------------------- STM32F373xC--------------------------------*/
00851 /**
00852   * @brief   AF 0 selection
00853   */
00854 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
00855 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00856 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
00857 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00858 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
00859
00860 /**
00861   * @brief   AF 1 selection
00862   */
00863 #define GPIO_AF1_TIM2           ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
00864 #define GPIO_AF1_TIM15          ((uint8_t)0x01U)  /* TIM15 Alternate Function mapping */
00865 #define GPIO_AF1_TIM16          ((uint8_t)0x01U)  /* TIM16 Alternate Function mapping */
00866 #define GPIO_AF1_TIM17          ((uint8_t)0x01U)  /* TIM17 Alternate Function mapping */
00867 #define GPIO_AF1_EVENTOUT       ((uint8_t)0x01U)  /* EVENTOUT Alternate Function mapping */
00868 /**
00869   * @brief   AF 2 selection
00870   */
00871 #define GPIO_AF2_TIM3           ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
00872 #define GPIO_AF2_TIM4           ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
00873 #define GPIO_AF2_TIM5           ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
00874 #define GPIO_AF2_TIM13          ((uint8_t)0x02U)  /* TIM13 Alternate Function mapping */
00875 #define GPIO_AF2_TIM14          ((uint8_t)0x02U)  /* TIM14 Alternate Function mapping */
00876 #define GPIO_AF2_TIM15          ((uint8_t)0x02U)  /* TIM15 Alternate Function mapping */
00877 #define GPIO_AF2_TIM19          ((uint8_t)0x02U)  /* TIM19 Alternate Function mapping */
00878
00879 /**
00880   * @brief   AF 3 selection
00881   */
00882 #define GPIO_AF3_TSC           ((uint8_t)0x03U)  /* TSC Alternate Function mapping  */
00883 /**
00884   * @brief   AF 4 selection
00885   */
00886 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
00887 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
00888
00889 /**
00890   * @brief   AF 5 selection
00891   */
00892 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping */
00893 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping */
00894 #define GPIO_AF5_IR            ((uint8_t)0x05U)  /* IR Alternate Function mapping */
00895 /**
00896   * @brief   AF 6 selection
00897   */
00898 #define GPIO_AF6_SPI1          ((uint8_t)0x06U)  /* SPI1/I2S1 Alternate Function mapping */
00899 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping */
00900 #define GPIO_AF6_IR            ((uint8_t)0x06U)  /* IR Alternate Function mapping */
00901 #define GPIO_AF6_CEC           ((uint8_t)0x06U)  /* CEC Alternate Function mapping */
00902 /**
00903   * @brief   AF 7 selection
00904   */
00905 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping  */
00906 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping  */
00907 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping  */
00908 #define GPIO_AF7_CAN           ((uint8_t)0x07U)  /* CAN Alternate Function mapping  */
00909 #define GPIO_AF7_CEC           ((uint8_t)0x07U)  /* CEC Alternate Function mapping  */
00910
00911 /**
00912   * @brief   AF 8 selection
00913   */
00914 #define GPIO_AF8_COMP1         ((uint8_t)0x08U)  /* COMP1 Alternate Function mapping  */
00915 #define GPIO_AF8_COMP2         ((uint8_t)0x08U)  /* COMP2 Alternate Function mapping  */
00916
00917 /**
00918   * @brief   AF 9 selection
00919   */
00920 #define GPIO_AF9_CAN           ((uint8_t)0x09U)  /* CAN Alternate Function mapping  */
00921 #define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping */
00922 #define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping */
00923 #define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */
00924 #define GPIO_AF9_TIM15         ((uint8_t)0x09U)  /* TIM15 Alternate Function mapping */
00925 /**
00926   * @brief   AF 10 selection
00927   */
00928 #define GPIO_AF10_TIM2           ((uint8_t)0xAU)  /* TIM2 Alternate Function mapping */
00929 #define GPIO_AF10_TIM3           ((uint8_t)0xAU)  /* TIM3 Alternate Function mapping */
00930 #define GPIO_AF10_TIM4           ((uint8_t)0xAU)  /* TIM4 Alternate Function mapping */
00931 #define GPIO_AF10_TIM12          ((uint8_t)0xAU)  /* TIM12 Alternate Function mapping */
00932 #define GPIO_AF10_TIM17          ((uint8_t)0xAU)  /* TIM17 Alternate Function mapping */
00933 /**
00934   * @brief   AF 11 selection
00935   */
00936 #define GPIO_AF11_TIM19          ((uint8_t)0x0BU)  /* TIM19 Alternate Function mapping */
00937
00938
00939 /**
00940   * @brief   AF 14 selection
00941   */
00942 #define GPIO_AF14_USB           ((uint8_t)0x0EU)  /* USB Alternate Function mapping */
00943
00944 /**
00945   * @brief   AF 15 selection
00946   */
00947 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
00948
00949 #define IS_GPIO_AF(AF)          (((AF) <= (uint8_t)0x0BU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
00950 /*------------------------------------------------------------------------------------------*/
00951 #endif /* STM32F373xC */
00952
00953
00954 #if defined (STM32F378xx)
00955 /*---------------------------------------- STM32F378xx--------------------------------------*/
00956 /**
00957   * @brief   AF 0 selection
00958   */
00959 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
00960 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00961 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
00962 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00963 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
00964
00965 /**
00966   * @brief   AF 1 selection
00967   */
00968 #define GPIO_AF1_TIM2           ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
00969 #define GPIO_AF1_TIM15          ((uint8_t)0x01U)  /* TIM15 Alternate Function mapping */
00970 #define GPIO_AF1_TIM16          ((uint8_t)0x01U)  /* TIM16 Alternate Function mapping */
00971 #define GPIO_AF1_TIM17          ((uint8_t)0x01U)  /* TIM17 Alternate Function mapping */
00972 #define GPIO_AF1_EVENTOUT       ((uint8_t)0x01U)  /* EVENTOUT Alternate Function mapping */
00973 /**
00974   * @brief   AF 2 selection
00975   */
00976 #define GPIO_AF2_TIM3           ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
00977 #define GPIO_AF2_TIM4           ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
00978 #define GPIO_AF2_TIM5           ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
00979 #define GPIO_AF2_TIM13          ((uint8_t)0x02U)  /* TIM13 Alternate Function mapping */
00980 #define GPIO_AF2_TIM14          ((uint8_t)0x02U)  /* TIM14 Alternate Function mapping */
00981 #define GPIO_AF2_TIM15          ((uint8_t)0x02U)  /* TIM15 Alternate Function mapping */
00982 #define GPIO_AF2_TIM19          ((uint8_t)0x02U)  /* TIM19 Alternate Function mapping */
00983
00984 /**
00985   * @brief   AF 3 selection
00986   */
00987 #define GPIO_AF3_TSC           ((uint8_t)0x03U)  /* TSC Alternate Function mapping  */
00988 /**
00989   * @brief   AF 4 selection
00990   */
00991 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
00992 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
00993
00994 /**
00995   * @brief   AF 5 selection
00996   */
00997 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping */
00998 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping */
00999 #define GPIO_AF5_IR            ((uint8_t)0x05U)  /* IR Alternate Function mapping */
01000
01001 /**
01002   * @brief   AF 6 selection
01003   */
01004 #define GPIO_AF6_SPI1          ((uint8_t)0x06U)  /* SPI1/I2S1 Alternate Function mapping */
01005 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping */
01006 #define GPIO_AF6_IR            ((uint8_t)0x06U)  /* IR Alternate Function mapping */
01007 #define GPIO_AF6_CEC           ((uint8_t)0x06U)  /* CEC Alternate Function mapping */
01008
01009 /**
01010   * @brief   AF 7 selection
01011   */
01012 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping  */
01013 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping  */
01014 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping  */
01015 #define GPIO_AF7_CAN           ((uint8_t)0x07U)  /* CAN Alternate Function mapping  */
01016 #define GPIO_AF7_CEC           ((uint8_t)0x07U)  /* CEC Alternate Function mapping  */
01017
01018 /**
01019   * @brief   AF 8 selection
01020   */
01021 #define GPIO_AF8_COMP1         ((uint8_t)0x08U)  /* COMP1 Alternate Function mapping  */
01022 #define GPIO_AF8_COMP2         ((uint8_t)0x08U)  /* COMP2 Alternate Function mapping  */
01023
01024 /**
01025   * @brief   AF 9 selection
01026   */
01027 #define GPIO_AF9_CAN           ((uint8_t)0x09U)  /* CAN Alternate Function mapping  */
01028 #define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping */
01029 #define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping */
01030 #define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */
01031 #define GPIO_AF9_TIM15         ((uint8_t)0x09U)  /* TIM15 Alternate Function mapping */
01032
01033 /**
01034   * @brief   AF 10 selection
01035   */
01036 #define GPIO_AF10_TIM2           ((uint8_t)0xAU)  /* TIM2 Alternate Function mapping */
01037 #define GPIO_AF10_TIM3           ((uint8_t)0xAU)  /* TIM3 Alternate Function mapping */
01038 #define GPIO_AF10_TIM4           ((uint8_t)0xAU)  /* TIM4 Alternate Function mapping */
01039 #define GPIO_AF10_TIM12          ((uint8_t)0xAU)  /* TIM12 Alternate Function mapping */
01040 #define GPIO_AF10_TIM17          ((uint8_t)0xAU)  /* TIM17 Alternate Function mapping */
01041
01042 /**
01043   * @brief   AF 11 selection
01044   */
01045 #define GPIO_AF11_TIM19          ((uint8_t)0x0BU)  /* TIM19 Alternate Function mapping */
01046
01047 /**
01048   * @brief   AF 15 selection
01049   */
01050 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
01051
01052 #define IS_GPIO_AF(AF)          (((AF) <= (uint8_t)0x0BU) || ((AF) == (uint8_t)0x0FU))
01053 /*------------------------------------------------------------------------------------------*/
01054 #endif /* STM32F378xx */
01055
01056 #if defined (STM32F303x8)
01057 /*---------------------------------- STM32F303x8--------------------------------*/
01058 /**
01059   * @brief   AF 0 selection
01060   */
01061 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
01062 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
01063 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
01064 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
01065
01066 /**
01067   * @brief   AF 1 selection
01068   */
01069 #define GPIO_AF1_TIM2           ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
01070 #define GPIO_AF1_TIM15          ((uint8_t)0x01U)  /* TIM15 Alternate Function mapping */
01071 #define GPIO_AF1_TIM16          ((uint8_t)0x01U)  /* TIM16 Alternate Function mapping */
01072 #define GPIO_AF1_TIM17          ((uint8_t)0x01U)  /* TIM17 Alternate Function mapping */
01073 #define GPIO_AF1_EVENTOUT       ((uint8_t)0x01U)  /* EVENTOUT Alternate Function mapping */
01074 /**
01075   * @brief   AF 2 selection
01076   */
01077 #define GPIO_AF2_TIM3           ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
01078 #define GPIO_AF2_TIM1           ((uint8_t)0x02U)  /* TIM1 Alternate Function mapping */
01079 #define GPIO_AF2_TIM15          ((uint8_t)0x02U)  /* TIM15 Alternate Function mapping */
01080 #define GPIO_AF2_TIM16          ((uint8_t)0x02U)  /* TIM16 Alternate Function mapping */
01081
01082 /**
01083   * @brief   AF 3 selection
01084   */
01085 #define GPIO_AF3_TSC           ((uint8_t)0x03U)  /* TSC Alternate Function mapping  */
01086
01087 /**
01088   * @brief   AF 4 selection
01089   */
01090 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
01091 #define GPIO_AF4_TIM1          ((uint8_t)0x04U)  /* TIM1 Alternate Function mapping */
01092
01093 /**
01094   * @brief   AF 5 selection
01095   */
01096 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping */
01097 #define GPIO_AF5_IR            ((uint8_t)0x05U)  /* IR Alternate Function mapping */
01098 /**
01099   * @brief   AF 6 selection
01100   */
01101 #define GPIO_AF6_TIM1          ((uint8_t)0x06U)  /* TIM1 Alternate Function mapping */
01102 #define GPIO_AF6_IR            ((uint8_t)0x06U)  /* IR Alternate Function mapping */
01103
01104 /**
01105   * @brief   AF 7 selection
01106   */
01107 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping  */
01108 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping  */
01109 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping  */
01110 #define GPIO_AF7_GPCOMP6       ((uint8_t)0x07U)  /* GPCOMP6 Alternate Function mapping  */
01111
01112 /**
01113   * @brief   AF 8 selection
01114   */
01115 #define GPIO_AF8_GPCOMP2         ((uint8_t)0x08U)  /* GPCOMP2 Alternate Function mapping  */
01116 #define GPIO_AF8_GPCOMP4         ((uint8_t)0x08U)  /* GPCOMP4 Alternate Function mapping  */
01117 #define GPIO_AF8_GPCOMP6         ((uint8_t)0x08U)  /* GPCOMP6 Alternate Function mapping  */
01118
01119 /**
01120   * @brief   AF 9 selection
01121   */
01122 #define GPIO_AF9_CAN           ((uint8_t)0x09U)  /* CAN Alternate Function mapping  */
01123 #define GPIO_AF9_TIM1          ((uint8_t)0x09U)  /* TIM1 Alternate Function mapping */
01124 #define GPIO_AF9_TIM15         ((uint8_t)0x09U)  /* TIM15 Alternate Function mapping */
01125 /**
01126   * @brief   AF 10 selection
01127   */
01128 #define GPIO_AF10_TIM2           ((uint8_t)0xAU)  /* TIM2 Alternate Function mapping */
01129 #define GPIO_AF10_TIM3           ((uint8_t)0xAU)  /* TIM3 Alternate Function mapping */
01130 #define GPIO_AF10_TIM17          ((uint8_t)0xAU)  /* TIM17 Alternate Function mapping */
01131
01132 /**
01133   * @brief   AF 11 selection
01134   */
01135 #define GPIO_AF11_TIM1          ((uint8_t)0x0BU)  /* TIM1 Alternate Function mapping */
01136
01137 /**
01138   * @brief   AF 12 selection
01139   */
01140 #define GPIO_AF12_TIM1          ((uint8_t)0x0CU)  /* TIM1 Alternate Function mapping */
01141
01142 /**
01143   * @brief   AF 13 selection
01144   */
01145 #define GPIO_AF13_OPAMP2        ((uint8_t)0x0DU)  /* OPAMP2 Alternate Function mapping */
01146
01147 /**
01148   * @brief   AF 15 selection
01149   */
01150 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
01151
01152 #define IS_GPIO_AF(AF)          (((AF) <= (uint8_t)0x0DU) || ((AF) == (uint8_t)0x0FU))
01153 /*------------------------------------------------------------------------------------------*/
01154 #endif /* STM32F303x8 */
01155
01156 #if defined (STM32F334x8) || defined (STM32F328xx)
01157 /*---------------------------------- STM32F334x8/STM32F328xx -------------------------------*/
01158 /**
01159   * @brief   AF 0 selection
01160   */
01161 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
01162 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
01163 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
01164 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
01165
01166 /**
01167   * @brief   AF 1 selection
01168   */
01169 #define GPIO_AF1_TIM2           ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
01170 #define GPIO_AF1_TIM15          ((uint8_t)0x01U)  /* TIM15 Alternate Function mapping */
01171 #define GPIO_AF1_TIM16          ((uint8_t)0x01U)  /* TIM16 Alternate Function mapping */
01172 #define GPIO_AF1_TIM17          ((uint8_t)0x01U)  /* TIM17 Alternate Function mapping */
01173 #define GPIO_AF1_EVENTOUT       ((uint8_t)0x01U)  /* EVENTOUT Alternate Function mapping */
01174 /**
01175   * @brief   AF 2 selection
01176   */
01177 #define GPIO_AF2_TIM3           ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
01178 #define GPIO_AF2_TIM1           ((uint8_t)0x02U)  /* TIM1 Alternate Function mapping */
01179 #define GPIO_AF2_TIM15          ((uint8_t)0x02U)  /* TIM15 Alternate Function mapping */
01180 #define GPIO_AF2_TIM16          ((uint8_t)0x02U)  /* TIM16 Alternate Function mapping */
01181
01182 /**
01183   * @brief   AF 3 selection
01184   */
01185 #define GPIO_AF3_TSC           ((uint8_t)0x03U)  /* TSC Alternate Function mapping  */
01186 #define GPIO_AF3_HRTIM1        ((uint8_t)0x03U)  /* HRTIM1 Alternate Function mapping  */
01187
01188 /**
01189   * @brief   AF 4 selection
01190   */
01191 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
01192 #define GPIO_AF4_TIM1          ((uint8_t)0x04U)  /* TIM1 Alternate Function mapping */
01193
01194 /**
01195   * @brief   AF 5 selection
01196   */
01197 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping */
01198 #define GPIO_AF5_IR            ((uint8_t)0x05U)  /* IR Alternate Function mapping */
01199 /**
01200   * @brief   AF 6 selection
01201   */
01202 #define GPIO_AF6_TIM1          ((uint8_t)0x06U)  /* TIM1 Alternate Function mapping */
01203 #define GPIO_AF6_IR            ((uint8_t)0x06U)  /* IR Alternate Function mapping */
01204
01205 /**
01206   * @brief   AF 7 selection
01207   */
01208 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping  */
01209 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping  */
01210 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping  */
01211 #define GPIO_AF7_GPCOMP6       ((uint8_t)0x07U)  /* GPCOMP6 Alternate Function mapping  */
01212
01213 /**
01214   * @brief   AF 8 selection
01215   */
01216 #define GPIO_AF8_GPCOMP2         ((uint8_t)0x08U)  /* GPCOMP2 Alternate Function mapping  */
01217 #define GPIO_AF8_GPCOMP4         ((uint8_t)0x08U)  /* GPCOMP4 Alternate Function mapping  */
01218 #define GPIO_AF8_GPCOMP6         ((uint8_t)0x08U)  /* GPCOMP6 Alternate Function mapping  */
01219
01220 /**
01221   * @brief   AF 9 selection
01222   */
01223 #define GPIO_AF9_CAN           ((uint8_t)0x09U)  /* CAN Alternate Function mapping  */
01224 #define GPIO_AF9_TIM1          ((uint8_t)0x09U)  /* TIM1 Alternate Function mapping */
01225 #define GPIO_AF9_TIM15         ((uint8_t)0x09U)  /* TIM15 Alternate Function mapping */
01226 /**
01227   * @brief   AF 10 selection
01228   */
01229 #define GPIO_AF10_TIM2           ((uint8_t)0xAU)  /* TIM2 Alternate Function mapping */
01230 #define GPIO_AF10_TIM3           ((uint8_t)0xAU)  /* TIM3 Alternate Function mapping */
01231 #define GPIO_AF10_TIM17          ((uint8_t)0xAU)  /* TIM17 Alternate Function mapping */
01232
01233 /**
01234   * @brief   AF 11 selection
01235   */
01236 #define GPIO_AF11_TIM1          ((uint8_t)0x0BU)  /* TIM1 Alternate Function mapping */
01237
01238 /**
01239   * @brief   AF 12 selection
01240   */
01241 #define GPIO_AF12_TIM1          ((uint8_t)0x0CU)  /* TIM1 Alternate Function mapping */
01242 #define GPIO_AF12_HRTIM1        ((uint8_t)0x0CU)  /* HRTIM1 Alternate Function mapping  */
01243
01244 /**
01245   * @brief   AF 13 selection
01246   */
01247 #define GPIO_AF13_OPAMP2        ((uint8_t)0x0DU)  /* OPAMP2 Alternate Function mapping */
01248 #define GPIO_AF13_HRTIM1        ((uint8_t)0x0DU)  /* HRTIM1 Alternate Function mapping  */
01249
01250 /**
01251   * @brief   AF 15 selection
01252   */
01253 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
01254
01255 #define IS_GPIO_AF(AF)          (((AF) <= (uint8_t)0x0DU) || ((AF) == (uint8_t)0x0FU))
01256 /*------------------------------------------------------------------------------------------*/
01257 #endif /* STM32F334x8 || STM32F328xx */
01258
01259 #if defined (STM32F301x8) || defined (STM32F318xx)
01260 /*---------------------------------- STM32F301x8 / STM32F318xx ------------------------------------------*/
01261 /**
01262   * @brief   AF 0 selection
01263   */
01264 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
01265 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC Alternate Function mapping                                                                     */
01266 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
01267 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
01268 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
01269
01270 /**
01271   * @brief   AF 1 selection
01272   */
01273 #define GPIO_AF1_TIM2           ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
01274 #define GPIO_AF1_TIM15          ((uint8_t)0x01U)  /* TIM15 Alternate Function mapping */
01275 #define GPIO_AF1_TIM16          ((uint8_t)0x01U)  /* TIM16 Alternate Function mapping */
01276 #define GPIO_AF1_TIM17          ((uint8_t)0x01U)  /* TIM17 Alternate Function mapping */
01277 #define GPIO_AF1_EVENTOUT       ((uint8_t)0x01U)  /* EVENTOUT Alternate Function mapping */
01278 /**
01279   * @brief   AF 2 selection
01280   */
01281 #define GPIO_AF2_I2C3           ((uint8_t)0x02U)  /* I2C3 Alternate Function mapping */
01282 #define GPIO_AF2_TIM1           ((uint8_t)0x02U)  /* TIM1 Alternate Function mapping */
01283 #define GPIO_AF2_TIM15          ((uint8_t)0x02U)  /* TIM15 Alternate Function mapping */
01284 #define GPIO_AF2_TIM2           ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping */
01285
01286 /**
01287   * @brief   AF 3 selection
01288   */
01289 #define GPIO_AF3_TSC           ((uint8_t)0x03U)  /* TSC Alternate Function mapping  */
01290 #define GPIO_AF3_I2C3          ((uint8_t)0x03U)  /* I2C3 Alternate Function mapping  */
01291 #define GPIO_AF3_TIM15         ((uint8_t)0x03U)  /* TIM15 Alternate Function mapping  */
01292
01293 /**
01294   * @brief   AF 4 selection
01295   */
01296 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
01297 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
01298 #define GPIO_AF4_TIM1          ((uint8_t)0x04U)  /* TIM1 Alternate Function mapping */
01299 #define GPIO_AF4_TIM16         ((uint8_t)0x04U)  /* TIM16 Alternate Function mapping */
01300 #define GPIO_AF4_TIM17         ((uint8_t)0x04U)  /* TIM17 Alternate Function mapping */
01301
01302 /**
01303   * @brief   AF 5 selection
01304   */
01305 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping */
01306 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping */
01307 #define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping */
01308 #define GPIO_AF5_IR            ((uint8_t)0x05U)  /* IR Alternate Function mapping */
01309 /**
01310   * @brief   AF 6 selection
01311   */
01312 #define GPIO_AF6_TIM1          ((uint8_t)0x06U)  /* TIM1 Alternate Function mapping */
01313 #define GPIO_AF6_IR            ((uint8_t)0x06U)  /* IR Alternate Function mapping */
01314 #define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* SPI2/I2S2 Alternate Function mapping */
01315 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping */
01316
01317 /**
01318   * @brief   AF 7 selection
01319   */
01320 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping  */
01321 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping  */
01322 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping  */
01323 #define GPIO_AF7_GPCOMP6       ((uint8_t)0x07U)  /* GPCOMP6 Alternate Function mapping  */
01324
01325 /**
01326   * @brief   AF 8 selection
01327   */
01328 #define GPIO_AF8_I2C3            ((uint8_t)0x08U)  /* I2C3 Alternate Function mapping  */
01329 #define GPIO_AF8_GPCOMP2         ((uint8_t)0x08U)  /* GPCOMP2 Alternate Function mapping  */
01330 #define GPIO_AF8_GPCOMP4         ((uint8_t)0x08U)  /* GPCOMP4 Alternate Function mapping  */
01331 #define GPIO_AF8_GPCOMP6         ((uint8_t)0x08U)  /* GPCOMP6 Alternate Function mapping  */
01332
01333 /**
01334   * @brief   AF 9 selection
01335   */
01336 #define GPIO_AF9_TIM1          ((uint8_t)0x09U)  /* TIM1 Alternate Function mapping */
01337 #define GPIO_AF9_TIM15         ((uint8_t)0x09U)  /* TIM15 Alternate Function mapping */
01338
01339 /**
01340   * @brief   AF 10 selection
01341   */
01342 #define GPIO_AF10_TIM2           ((uint8_t)0xAU)  /* TIM2 Alternate Function mapping */
01343 #define GPIO_AF10_TIM17          ((uint8_t)0xAU)  /* TIM17 Alternate Function mapping */
01344
01345 /**
01346   * @brief   AF 11 selection
01347   */
01348 #define GPIO_AF11_TIM1          ((uint8_t)0x0BU)  /* TIM1 Alternate Function mapping */
01349
01350 /**
01351   * @brief   AF 12 selection
01352   */
01353 #define GPIO_AF12_TIM1          ((uint8_t)0x0CU)  /* TIM1 Alternate Function mapping */
01354
01355 /**
01356   * @brief   AF 15 selection
01357   */
01358 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
01359
01360 #define IS_GPIO_AF(AF)          (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU))
01361 /*------------------------------------------------------------------------------------------*/
01362 #endif /* STM32F301x8 || STM32F318xx */
01363
01364 #if defined (STM32F302x8)
01365 /*---------------------------------- STM32F302x8------------------------------------------*/
01366 /**
01367   * @brief   AF 0 selection
01368   */
01369 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
01370 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC Alternate Function mapping                                                                     */
01371 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
01372 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
01373 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
01374
01375 /**
01376   * @brief   AF 1 selection
01377   */
01378 #define GPIO_AF1_TIM2           ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
01379 #define GPIO_AF1_TIM15          ((uint8_t)0x01U)  /* TIM15 Alternate Function mapping */
01380 #define GPIO_AF1_TIM16          ((uint8_t)0x01U)  /* TIM16 Alternate Function mapping */
01381 #define GPIO_AF1_TIM17          ((uint8_t)0x01U)  /* TIM17 Alternate Function mapping */
01382 #define GPIO_AF1_EVENTOUT       ((uint8_t)0x01U)  /* EVENTOUT Alternate Function mapping */
01383 /**
01384   * @brief   AF 2 selection
01385   */
01386 #define GPIO_AF2_I2C3           ((uint8_t)0x02U)  /* I2C3 Alternate Function mapping */
01387 #define GPIO_AF2_TIM1           ((uint8_t)0x02U)  /* TIM1 Alternate Function mapping */
01388 #define GPIO_AF2_TIM15          ((uint8_t)0x02U)  /* TIM15 Alternate Function mapping */
01389 #define GPIO_AF2_TIM2           ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping */
01390
01391 /**
01392   * @brief   AF 3 selection
01393   */
01394 #define GPIO_AF3_TSC           ((uint8_t)0x03U)  /* TSC Alternate Function mapping  */
01395 #define GPIO_AF3_I2C3          ((uint8_t)0x03U)  /* I2C3 Alternate Function mapping  */
01396 #define GPIO_AF3_TIM15         ((uint8_t)0x03U)  /* TIM15 Alternate Function mapping  */
01397
01398 /**
01399   * @brief   AF 4 selection
01400   */
01401 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
01402 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
01403 #define GPIO_AF4_TIM1          ((uint8_t)0x04U)  /* TIM1 Alternate Function mapping */
01404 #define GPIO_AF4_TIM16         ((uint8_t)0x04U)  /* TIM16 Alternate Function mapping */
01405 #define GPIO_AF4_TIM17         ((uint8_t)0x04U)  /* TIM17 Alternate Function mapping */
01406
01407 /**
01408   * @brief   AF 5 selection
01409   */
01410 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping */
01411 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping */
01412 #define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping */
01413 #define GPIO_AF5_IR            ((uint8_t)0x05U)  /* IR Alternate Function mapping */
01414 /**
01415   * @brief   AF 6 selection
01416   */
01417 #define GPIO_AF6_TIM1          ((uint8_t)0x06U)  /* TIM1 Alternate Function mapping */
01418 #define GPIO_AF6_IR            ((uint8_t)0x06U)  /* IR Alternate Function mapping */
01419 #define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* SPI2/I2S2 Alternate Function mapping */
01420 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping */
01421
01422 /**
01423   * @brief   AF 7 selection
01424   */
01425 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping  */
01426 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping  */
01427 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping  */
01428 #define GPIO_AF7_GPCOMP6       ((uint8_t)0x07U)  /* GPCOMP6 Alternate Function mapping */
01429 #define GPIO_AF7_CAN           ((uint8_t)0x07U)  /* CAN Alternate Function mapping */
01430
01431 /**
01432   * @brief   AF 8 selection
01433   */
01434 #define GPIO_AF8_I2C3            ((uint8_t)0x08U)  /* I2C3 Alternate Function mapping  */
01435 #define GPIO_AF8_GPCOMP2         ((uint8_t)0x08U)  /* GPCOMP2 Alternate Function mapping  */
01436 #define GPIO_AF8_GPCOMP4         ((uint8_t)0x08U)  /* GPCOMP4 Alternate Function mapping  */
01437 #define GPIO_AF8_GPCOMP6         ((uint8_t)0x08U)  /* GPCOMP6 Alternate Function mapping  */
01438
01439 /**
01440   * @brief   AF 9 selection
01441   */
01442 #define GPIO_AF9_TIM1          ((uint8_t)0x09U)  /* TIM1 Alternate Function mapping */
01443 #define GPIO_AF9_TIM15         ((uint8_t)0x09U)  /* TIM15 Alternate Function mapping */
01444 #define GPIO_AF9_CAN           ((uint8_t)0x09U)  /* CAN Alternate Function mapping */
01445
01446 /**
01447   * @brief   AF 10 selection
01448   */
01449 #define GPIO_AF10_TIM2           ((uint8_t)0xAU)  /* TIM2 Alternate Function mapping */
01450 #define GPIO_AF10_TIM17          ((uint8_t)0xAU)  /* TIM17 Alternate Function mapping */
01451
01452 /**
01453   * @brief   AF 11 selection
01454   */
01455 #define GPIO_AF11_TIM1          ((uint8_t)0x0BU)  /* TIM1 Alternate Function mapping */
01456
01457 /**
01458   * @brief   AF 12 selection
01459   */
01460 #define GPIO_AF12_TIM1          ((uint8_t)0x0CU)  /* TIM1 Alternate Function mapping */
01461
01462 /**
01463   * @brief   AF 15 selection
01464   */
01465 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
01466
01467 #define IS_GPIO_AF(AF)          (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU))
01468 /*------------------------------------------------------------------------------------------*/
01469 #endif /* STM32F302x8 */
01470 /**
01471   * @}
01472   */
01473
01474 /**
01475   * @}
01476   */
01477
01478 /* Exported macro ------------------------------------------------------------*/
01479 /** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
01480   * @{
01481   */
01482
01483 /** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index
01484 * @{
01485   */
01486 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
01487     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01488 #define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
01489                                       ((__GPIOx__) == (GPIOB))? 1U :\
01490                                       ((__GPIOx__) == (GPIOC))? 2U :\
01491                                       ((__GPIOx__) == (GPIOD))? 3U : 5U)
01492 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
01493        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
01494
01495 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
01496     defined(STM32F373xC) || defined(STM32F378xx)
01497 #define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
01498                                       ((__GPIOx__) == (GPIOB))? 1U :\
01499                                       ((__GPIOx__) == (GPIOC))? 2U :\
01500                                       ((__GPIOx__) == (GPIOD))? 3U :\
01501                                       ((__GPIOx__) == (GPIOE))? 4U : 5U)
01502 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
01503        /* STM32F373xC || STM32F378xx                   */
01504
01505 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
01506 #define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
01507                                       ((__GPIOx__) == (GPIOB))? 1U :\
01508                                       ((__GPIOx__) == (GPIOC))? 2U :\
01509                                       ((__GPIOx__) == (GPIOD))? 3U :\
01510                                       ((__GPIOx__) == (GPIOE))? 4U :\
01511                                       ((__GPIOx__) == (GPIOF))? 5U :\
01512                                       ((__GPIOx__) == (GPIOG))? 6U : 7U)
01513 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
01514
01515 /**
01516   * @}
01517   */
01518
01519 /**
01520   * @}
01521   */
01522
01523 /* Exported functions --------------------------------------------------------*/
01524 /**
01525   * @}
01526   */
01527
01528 /**
01529   * @}
01530   */
01531
01532 #ifdef __cplusplus
01533 }
01534 #endif
01535
01536 #endif /* __STM32F3xx_HAL_GPIO_EX_H */
01537
01538 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_hrtim.c Source File

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stm32f3xx_hal_hrtim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_hrtim.c
00004   * @author  MCD Application Team
00005   * @brief   TIM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the High Resolution Timer (HRTIM) peripheral:
00008   *           + HRTIM Initialization
00009   *           + DLL Calibration Start
00010   *           + Timer Time Base Unit Configuration
00011   *           + Simple Time Base Start/Stop
00012   *           + Simple Time Base Start/Stop Interrupt
00013   *           + Simple Time Base Start/Stop DMA Request
00014   *           + Simple Output Compare/PWM Channel Configuration
00015   *           + Simple Output Compare/PWM Channel Start/Stop Interrupt
00016   *           + Simple Output Compare/PWM Channel Start/Stop DMA Request
00017   *           + Simple Input Capture Channel Configuration
00018   *           + Simple Input Capture Channel Start/Stop Interrupt
00019   *           + Simple Input Capture Channel Start/Stop DMA Request
00020   *           + Simple One Pulse Channel Configuration
00021   *           + Simple One Pulse Channel Start/Stop Interrupt
00022   *           + HRTIM External Synchronization Configuration
00023   *           + HRTIM Burst Mode Controller Configuration
00024   *           + HRTIM Burst Mode Controller Enabling
00025   *           + HRTIM External Events Conditioning Configuration
00026   *           + HRTIM Faults Conditioning Configuration
00027   *           + HRTIM Faults Enabling
00028   *           + HRTIM ADC trigger Configuration
00029   *           + Waveform Timer Configuration
00030   *           + Waveform Event Filtering Configuration
00031   *           + Waveform Dead Time Insertion Configuration
00032   *           + Waveform Chopper Mode Configuration
00033   *           + Waveform Compare Unit Configuration
00034   *           + Waveform Capture Unit Configuration
00035   *           + Waveform Output Configuration
00036   *           + Waveform Counter Start/Stop
00037   *           + Waveform Counter Start/Stop Interrupt
00038   *           + Waveform Counter Start/Stop DMA Request
00039   *           + Waveform Output Enabling
00040   *           + Waveform Output Level Set/Get
00041   *           + Waveform Output State Get
00042   *           + Waveform Burst DMA Operation Configuration
00043   *           + Waveform Burst DMA Operation Start
00044   *           + Waveform Timer Counter Software Reset
00045   *           + Waveform Capture Software Trigger
00046   *           + Waveform Burst Mode Controller Software Trigger
00047   *           + Waveform Timer Pre-loadable Registers Update Enabling
00048   *           + Waveform Timer Pre-loadable Registers Software Update
00049   *           + Waveform Timer Delayed Protection Status Get
00050   *           + Waveform Timer Burst Status Get
00051   *           + Waveform Timer Push-Pull Status Get
00052   *           + Peripheral State Get
00053   @verbatim
00054 ==============================================================================
00055                       ##### Simple mode v.s. waveform mode #####
00056 ==============================================================================
00057   [..] The HRTIM HAL API is split into 2 categories:
00058     (#)Simple functions: these functions allow for using a HRTIM timer as a
00059        general purpose timer with high resolution capabilities.
00060        HRTIM simple modes are managed through the set of functions named
00061        HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
00062        to the one defined for the TIM peripheral. When a HRTIM timer operates in
00063        simple mode, only a very limited set of HRTIM features are used.
00064        Following simple modes are proposed:
00065          (++)Output compare mode,
00066          (++)PWM output mode,
00067          (++)Input capture mode,
00068          (++)One pulse mode.
00069     (#)Waveform functions: These functions allow taking advantage of the HRTIM
00070        flexibility to produce numerous types of control signal. When a HRTIM timer
00071        operates in waveform mode, all the HRTIM features are accessible without
00072        any restriction.  HRTIM waveform modes are managed through the set of
00073        functions named HAL_HRTIM_Waveform<Function>
00074                       ##### How to use this driver #####
00075 ==============================================================================
00076     [..]
00077      (#)Initialize the HRTIM low level resources by implementing the
00078         HAL_HRTIM_MspInit() function:
00079         (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
00080         (##)Connect HRTIM pins to MCU I/Os
00081             (+++) Enable the clock for the HRTIM GPIOs using the following
00082                   function: __HAL_RCC_GPIOx_CLK_ENABLE()
00083             (+++) Configure these GPIO pins in Alternate Function mode using
00084                   HAL_GPIO_Init()
00085         (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
00086             (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
00087             (+++)Initialize the DMA handle
00088             (+++)Associate the initialized DMA handle to the appropriate DMA
00089                  handle of the HRTIM handle using  __HAL_LINKDMA()
00090             (+++)Initialize the DMA channel using HAL_DMA_Init()
00091             (+++)Configure the priority and enable the NVIC for the transfer
00092                  complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
00093                  and HAL_NVIC_EnableIRQ()
00094         (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
00095             (+++)Configure the priority and enable the NVIC for the concerned
00096                  HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
00097
00098     (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
00099        structure (field of the HRTIM handle) specifies which global interrupt of
00100        whole HRTIM must be enabled (Burst mode period, System fault, Faults).
00101        It also contains the HRTIM external synchronization configuration. HRTIM
00102        can act as a master (generating a synchronization signal) or as a slave
00103        (waiting for a trigger to be synchronized).
00104
00105     (#)Start the high resolution unit using HAL_HRTIM_DLLCalibrationStart(). DLL
00106        calibration is executed periodically and compensate for potential voltage
00107        and temperature drifts. DLL calibration period is specified by the
00108        CalibrationRate argument.
00109
00110     (#)HRTIM timers cannot be used until the high resolution unit is ready. This
00111        can be checked using HAL_HRTIM_PollForDLLCalibration(): this function returns
00112        HAL_OK if DLL calibration is completed or HAL_TIMEOUT if the DLL calibration
00113        is still going on when timeout given as argument expires. DLL calibration
00114        can also be started in interrupt mode using HAL_HRTIM_DLLCalibrationStart_IT().
00115        In that case an interrupt is generated when the DLL calibration is completed.
00116        Note that as DLL calibration is executed on a periodic basis an interrupt
00117        will be generated at the end of every DLL calibration operation
00118       (worst case: one interrupt every 14  micro seconds !).
00119
00120      (#) Configure HRTIM resources shared by all HRTIM timers
00121         (##)Burst Mode Controller:
00122                 (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
00123                      controller: operating mode (continuous or one-shot mode), clock
00124                      (source, prescaler) , trigger(s), period, idle duration.
00125         (##)External Events Conditionning:
00126                 (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
00127                      external event channel: source, polarity, edge-sensitivity.
00128                      External event can be used as triggers (timer reset, input
00129                      capture, burst mode, ADC triggers, delayed protection)
00130                      They can also be used to set or reset timer outputs. Up to
00131                      10 event channels are available.
00132                 (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
00133                      event sampling clock (used for digital filtering).
00134         (##)Fault Conditionning:
00135                 (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
00136                      fault channel: source, polarity, edge-sensitivity.  Fault
00137                      channels are used to disable the outputs in case of an
00138                      abnormal operation. Up to 5 fault channels are available.
00139                 (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
00140                      sampling clock (used for digital filtering).
00141                 (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
00142                      circuitry. By default all fault inputs are disabled.
00143         (##)ADC trigger:
00144                 (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
00145                      the update of the ADC trigger register and the ADC trigger.
00146                      4 independent triggers are available to start both the regular
00147                      and the injected sequencers of the 2 ADCs
00148
00149      (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
00150          function must be called whatever the HRTIM timer operating mode is
00151          (simple v.s. waveform). It  configures mainly:
00152         (##)The HRTIM  timer counter operating mode (continuous v.s. one shot)
00153         (##)The HRTIM  timer clock prescaler
00154         (##)The HRTIM  timer period
00155         (##)The HRTIM  timer repetition counter
00156
00157      *** If the HRTIM timer operates in simple mode ***
00158      ===================================================
00159      [..]
00160      (#) Start or Stop simple timers
00161                   (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
00162                   HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
00163                   HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
00164                   (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
00165                   HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
00166                   HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
00167                   HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
00168                   (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
00169                   HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
00170                   HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
00171                   HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
00172                   (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
00173                   HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
00174                   HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
00175                   HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
00176                   (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
00177                   HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
00178                   HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
00179
00180      *** If the HRTIM timer operates in waveform mode ***
00181      ====================================================
00182      [..]
00183      (#) Completes waveform timer configuration
00184                   (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
00185                               operating in wave form mode mainly consists in:
00186                 (+++)Enabling the HRTIM timer interrupts and DMA requests.
00187                 (+++)Enabling the half mode for the HRTIM timer.
00188                 (+++)Defining how the HRTIM timer reacts to external synchronization input.
00189                 (+++)Enabling the push-pull mode for the HRTIM timer.
00190                 (+++)Enabling the fault channels for the HRTIM timer.
00191                 (+++)Enabling the dead-time insertion for the HRTIM timer.
00192                 (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
00193                                      on which the delayed protection are applied).
00194                 (+++)Specifying the HRTIM timer update and reset triggers.
00195                 (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
00196                   (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
00197                   event blanking and windowing circuitry of a HRTIM timer:
00198                 (+++)Blanking:  to mask external events during a defined  time period a defined time period
00199                                 (+++)Windowing, to enable external events only during a defined time period
00200                   (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
00201                   unit for a HRTIM timer. Allows to generate a couple of
00202                   complementary signals from a single reference waveform,
00203                   with programmable delays between active state.
00204                   (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
00205                   the high-frequency carrier signal added on top of the timing
00206                   unit output. Chopper mode can be enabled or disabled for each
00207                    timer output separately (see  HAL_HRTIM_WaveformOutputConfig()).
00208                   (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
00209                   controller. Allows having multiple HRTIM registers updated
00210                   with a single DMA request. The burst DMA operation is started
00211                   by calling HAL_HRTIM_BurstDMATransfer().
00212                   (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
00213                   of a HRTIM timer. This operation consists in setting the
00214                   compare value and possibly specifying the auto delayed mode
00215                   for compare units 2 and 4 (allows to have compare events
00216                   generated relatively to capture events). Note that when auto
00217                   delayed mode is needed, the capture unit associated to the
00218                   compare unit must be configured separately.
00219                   (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
00220                   of a HRTIM timer. This operation consists in specifying the
00221                   source(s)  triggering the capture (timer register update event,
00222                   external event, timer output set/reset event, other HRTIM
00223                   timer related events).
00224                   (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
00225                   output mainly consists in:
00226                 (+++)Setting the output polarity (active high or active low),
00227                 (+++)Defining the set/reset crossbar for the output,
00228                 (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,
00229
00230      (#) Set waveform timer output(s) level
00231                   (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
00232                   active or inactive level. For example, when deadtime insertion
00233                   is enabled it is necessary to force the output level by software
00234                   to have the outputs in a complementary state as soon as the RUN mode is entered.
00235
00236      (#) Enable or Disable waveform timer output(s)
00237                   (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
00238
00239      (#) Start or Stop waveform HRTIM timer(s).
00240                   (++)HAL_HRTIM_WaveformCounterStart(),HAL_HRTIM_WaveformCounterStop(),
00241                   (++)HAL_HRTIM_WaveformCounterStart_IT(),HAL_HRTIM_WaveformCounterStop_IT(),
00242                   (++)HAL_HRTIM_WaveformCounterStart()_DMA,HAL_HRTIM_WaveformCounterStop_DMA(),
00243      (#) Burst mode controller enabling:
00244                   (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
00245                   burst mode controller.
00246
00247      (#) Some HRTIM operations can be triggered by software:
00248                   (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
00249                   trigs the burst operation.
00250                   (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
00251                   capture of the HRTIM timer counter.
00252                   (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
00253                   update of the pre-loadable registers of the HRTIM timer
00254                   (++)HAL_HRTIM_SoftwareReset():calling this function resets the
00255                   HRTIM timer counter.
00256
00257      (#) Some functions can be used any time to retrieve HRTIM timer related
00258             information
00259                   (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
00260                   capture register of the designated capture unit.
00261                   (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
00262                  (ACTIVE/INACTIVE) of the designated timer output.
00263                   (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
00264                  (IDLE/RUN/FAULT) of the designated timer output.
00265                   (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
00266                  (ACTIVE/INACTIVE) of the designated output when the delayed
00267                   protection was triggered.
00268                   (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
00269                  (ACTIVE/INACTIVE) of the burst mode controller.
00270                   (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
00271                  is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
00272                  the push-pull status indicates on which output the signal is currently
00273                  active (e.g signal applied on output 1 and output 2 forced
00274                  inactive or vice versa).
00275                  (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
00276                  is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
00277                  the idle push-pull status indicates during which period the
00278                  delayed protection request occurred (e.g. protection occurred
00279                  when the output 1 was active and output 2 forced inactive or
00280                  vice versa).
00281
00282      (#) Some functions can be used any time to retrieve actual HRTIM status
00283                  (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
00284
00285   @endverbatim
00286
00287   ******************************************************************************
00288   * @attention
00289   *
00290   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00291   *
00292   * Redistribution and use in source and binary forms, with or without modification,
00293   * are permitted provided that the following conditions are met:
00294   *   1. Redistributions of source code must retain the above copyright notice,
00295   *      this list of conditions and the following disclaimer.
00296   *   2. Redistributions in binary form must reproduce the above copyright notice,
00297   *      this list of conditions and the following disclaimer in the documentation
00298   *      and/or other materials provided with the distribution.
00299   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00300   *      may be used to endorse or promote products derived from this software
00301   *      without specific prior written permission.
00302   *
00303   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00304   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00305   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00306   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00307   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00308   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00309   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00310   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00311   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00312   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00313   *
00314   ******************************************************************************
00315   */
00316
00317 /* Includes ------------------------------------------------------------------*/
00318 #include "stm32f3xx_hal.h"
00319
00320 /** @addtogroup STM32F3xx_HAL_Driver
00321   * @{
00322   */
00323
00324 #ifdef HAL_HRTIM_MODULE_ENABLED
00325
00326 #if defined(STM32F334x8)
00327
00328 /** @defgroup HRTIM HRTIM
00329   * @brief HRTIM HAL module driver
00330   * @{
00331   */
00332
00333 /* Private typedef -----------------------------------------------------------*/
00334 /* Private define ------------------------------------------------------------*/
00335 /** @defgroup HRTIM_Private_Defines HRTIM Private Define
00336   * @{
00337   */
00338 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
00339                            HRTIM_FLTR_FLT2EN |\
00340                            HRTIM_FLTR_FLT3EN |\
00341                            HRTIM_FLTR_FLT4EN | \
00342                            HRTIM_FLTR_FLT5EN)
00343
00344 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER  |\
00345                                       HRTIM_TIMUPDATETRIGGER_TIMER_A |\
00346                                       HRTIM_TIMUPDATETRIGGER_TIMER_B |\
00347                                       HRTIM_TIMUPDATETRIGGER_TIMER_C |\
00348                                       HRTIM_TIMUPDATETRIGGER_TIMER_D |\
00349                                       HRTIM_TIMUPDATETRIGGER_TIMER_E)
00350 /**
00351   * @}
00352   */
00353
00354 /* Private macro -------------------------------------------------------------*/
00355 /* Private variables ---------------------------------------------------------*/
00356 /** @defgroup HRTIM_Private_Variables HRTIM Private Variables
00357   * @{
00358   */
00359 static uint32_t TimerIdxToTimerId[] =
00360 {
00361   HRTIM_TIMERID_TIMER_A,
00362   HRTIM_TIMERID_TIMER_B,
00363   HRTIM_TIMERID_TIMER_C,
00364   HRTIM_TIMERID_TIMER_D,
00365   HRTIM_TIMERID_TIMER_E,
00366   HRTIM_TIMERID_MASTER,
00367 };
00368 /**
00369   * @}
00370   */
00371
00372 /* Private function prototypes -----------------------------------------------*/
00373 /** @defgroup HRTIM_Private_Functions HRTIM Private Functions
00374   * @{
00375   */
00376 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
00377                                     HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
00378
00379 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
00380                                         uint32_t TimerIdx,
00381                                         HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
00382
00383 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
00384                                         HRTIM_TimerCfgTypeDef * pTimerCfg);
00385
00386 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
00387                                             uint32_t TimerIdx,
00388                                             HRTIM_TimerCfgTypeDef * pTimerCfg);
00389
00390 static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
00391                                     uint32_t TimerIdx,
00392                                     uint32_t CompareUnit,
00393                                     HRTIM_CompareCfgTypeDef * pCompareCfg);
00394
00395 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
00396                                     uint32_t TimerIdx,
00397                                     uint32_t CaptureUnit,
00398                                     uint32_t Event);
00399
00400 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
00401                                 uint32_t TimerIdx,
00402                                 uint32_t Output,
00403                                 HRTIM_OutputCfgTypeDef * pOutputCfg);
00404
00405 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
00406                               uint32_t Event,
00407                               HRTIM_EventCfgTypeDef * pEventCfg);
00408
00409 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
00410                                   uint32_t TimerIdx,
00411                                   uint32_t Event);
00412
00413 static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
00414                                       uint32_t TimerIdx,
00415                                       uint32_t OCChannel);
00416
00417 static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
00418                                        uint32_t TimerIdx,
00419                                        uint32_t OCChannel);
00420
00421 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
00422                                                           uint32_t TimerIdx);
00423
00424 static uint32_t GetTimerIdxFromDMAHandle(DMA_HandleTypeDef *hdma);
00425
00426 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
00427                                       uint32_t TimerIdx);
00428
00429 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim);
00430
00431 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim);
00432
00433 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
00434                                        uint32_t TimerIdx);
00435
00436 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
00437
00438 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
00439
00440 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
00441
00442 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
00443 /**
00444   * @}
00445   */
00446
00447 /* Exported functions ---------------------------------------------------------*/
00448 /** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
00449   * @{
00450   */
00451
00452 /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
00453  *  @brief    Initialization and Configuration functions
00454 @verbatim
00455  ===============================================================================
00456               ##### Initialization and Time Base Configuration functions #####
00457  ===============================================================================
00458     [..]  This section provides functions allowing to:
00459       (+) Initialize a HRTIM instance
00460       (+) De-initialize a HRTIM instance
00461       (+) Initialize the HRTIM MSP
00462       (+) De-initialize the HRTIM MSP
00463       (+) Start the high-resolution unit (start DLL calibration)
00464       (+) Check that the high resolution unit is ready (DLL calibration done)
00465       (+) Configure the time base unit of a HRTIM timer
00466
00467 @endverbatim
00468   * @{
00469   */
00470
00471 /**
00472   * @brief  Initializes a HRTIM instance
00473   * @param  hhrtim pointer to HAL HRTIM handle
00474   * @retval HAL status
00475   */
00476 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
00477 {
00478   uint8_t timer_idx;
00479   uint32_t hrtim_mcr;
00480
00481   /* Check the HRTIM handle allocation */
00482   if(hhrtim == NULL)
00483   {
00484     return HAL_ERROR;
00485   }
00486
00487   /* Check the parameters */
00488   assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
00489   assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests));
00490
00491   /* Set the HRTIM state */
00492   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00493
00494   /* Initialize the DMA handles */
00495   hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
00496   hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
00497   hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
00498   hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
00499   hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
00500   hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
00501
00502   /* HRTIM output synchronization configuration (if required) */
00503   if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != RESET)
00504   {
00505     /* Check parameters */
00506     assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
00507     assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
00508
00509     /* The synchronization output initialization procedure must be done prior
00510        to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
00511     */
00512     if (hhrtim->Instance == HRTIM1)
00513     {
00514       /* Enable the HRTIM peripheral clock */
00515       __HAL_RCC_HRTIM1_CLK_ENABLE();
00516     }
00517
00518     hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
00519
00520     /* Set the event to be sent on the synchronization output */
00521     hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
00522     hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
00523
00524     /* Set the polarity of the synchronization output */
00525     hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
00526     hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
00527
00528     /* Update the HRTIM registers */
00529     hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
00530   }
00531
00532   /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00533   HAL_HRTIM_MspInit(hhrtim);
00534
00535   /* HRTIM input synchronization configuration (if required) */
00536   if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != RESET)
00537   {
00538     /* Check parameters */
00539     assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
00540
00541     hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
00542
00543     /* Set the synchronization input source */
00544     hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
00545     hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
00546
00547     /* Update the HRTIM registers */
00548     hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
00549   }
00550
00551   /* Initialize the HRTIM state*/
00552   hhrtim->State = HAL_HRTIM_STATE_READY;
00553
00554   /* Initialize the lock status of the HRTIM HAL API */
00555   __HAL_UNLOCK(hhrtim);
00556
00557   /* Tnitialize timer related parameters */
00558   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
00559        timer_idx <= HRTIM_TIMERINDEX_MASTER ;
00560        timer_idx++)
00561   {
00562     hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
00563     hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
00564     hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
00565     hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
00566     hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
00567     hhrtim->TimerParam[timer_idx].DMASize = 0U;
00568   }
00569
00570   return HAL_OK;
00571 }
00572
00573 /**
00574   * @brief  De-initializes a HRTIM instance
00575   * @param  hhrtim pointer to HAL HRTIM handle
00576   * @retval HAL status
00577   */
00578 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
00579 {
00580   /* Check the HRTIM handle allocation */
00581   if(hhrtim == NULL)
00582   {
00583     return HAL_ERROR;
00584   }
00585
00586   /* Check the parameters */
00587   assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
00588
00589   /* Set the HRTIM state */
00590   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00591
00592   /* DeInit the low level hardware */
00593   HAL_HRTIM_MspDeInit(hhrtim);
00594
00595   hhrtim->State = HAL_HRTIM_STATE_READY;
00596
00597   return HAL_OK;
00598 }
00599
00600 /**
00601   * @brief  MSP initialization for a HRTIM instance
00602   * @param  hhrtim pointer to HAL HRTIM handle
00603   * @retval None
00604   */
00605 __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
00606 {
00607   /* Prevent unused argument(s) compilation warning */
00608   UNUSED(hhrtim);
00609
00610   /* NOTE: This function should not be modified, when the callback is needed,
00611            the HAL_HRTIM_MspInit could be implemented in the user file
00612    */
00613 }
00614
00615 /**
00616   * @brief  MSP de-initialization for a for a HRTIM instance
00617   * @param  hhrtim pointer to HAL HRTIM handle
00618   * @retval None
00619   */
00620 __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
00621 {
00622   /* Prevent unused argument(s) compilation warning */
00623   UNUSED(hhrtim);
00624
00625   /* NOTE: This function should not be modified, when the callback is needed,
00626            the HAL_HRTIM_MspDeInit could be implemented in the user file
00627    */
00628 }
00629
00630 /**
00631   * @brief  Starts the DLL calibration
00632   * @param  hhrtim pointer to HAL HRTIM handle
00633   * @param  CalibrationRate DLL calibration period
00634   *                    This parameter can be one of the following values:
00635   *                    @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
00636   *                    @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.3 ms
00637   *                    @arg HRTIM_CALIBRATIONRATE_910: Periodic DLL calibration. T=910 us
00638   *                    @arg HRTIM_CALIBRATIONRATE_114: Periodic DLL calibration. T=114 us
00639   *                    @arg HRTIM_CALIBRATIONRATE_14: Periodic DLL calibration. T=14 us
00640   * @retval HAL status
00641   * @note This function locks the HRTIM instance. HRTIM instance is unlocked
00642   *       within the HAL_HRTIM_PollForDLLCalibration function, just before
00643   *       exiting the function.
00644   */
00645 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim,
00646                                                 uint32_t CalibrationRate)
00647 {
00648   uint32_t hrtim_dllcr;
00649
00650    /* Check the parameters */
00651   assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
00652
00653   /* Process Locked */
00654   __HAL_LOCK(hhrtim);
00655
00656   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00657
00658   /* Configure DLL Calibration */
00659   hrtim_dllcr = hhrtim->Instance->sCommonRegs.DLLCR;
00660
00661   if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
00662   {
00663     /* One shot DLL calibration */
00664     hrtim_dllcr &= ~(HRTIM_DLLCR_CALEN);
00665     hrtim_dllcr |= HRTIM_DLLCR_CAL;
00666   }
00667   else
00668   {
00669     /* Periodic DLL calibration */
00670     hrtim_dllcr &= ~(HRTIM_DLLCR_CALRTE | HRTIM_DLLCR_CAL);
00671     hrtim_dllcr |= (CalibrationRate | HRTIM_DLLCR_CALEN);
00672   }
00673
00674   /* Update HRTIM register */
00675   hhrtim->Instance->sCommonRegs.DLLCR = hrtim_dllcr;
00676
00677   return HAL_OK;
00678 }
00679
00680 /**
00681   * @brief  Starts the DLL calibration.
00682   *         DLL ready interrupt is enabled
00683   * @param  hhrtim pointer to HAL HRTIM handle
00684   * @param  CalibrationRate DLL calibration period
00685   *                    This parameter can be one of the following values:
00686   *                    @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
00687   *                    @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.3 ms
00688   *                    @arg HRTIM_CALIBRATIONRATE_910: Periodic DLL calibration. T=910 us
00689   *                    @arg HRTIM_CALIBRATIONRATE_114: Periodic DLL calibration. T=114 us
00690   *                    @arg HRTIM_CALIBRATIONRATE_14: Periodic DLL calibration. T=14 us
00691   * @retval HAL status
00692   * @note This function locks the HRTIM instance. HRTIM instance is unlocked
00693   *       within the IRQ processing function when processing the DLL ready
00694   *       interrupt.
00695   * @note If this function is called for periodic calibration, the DLLRDY
00696   *       interrupt is generated every time the calibration completes which
00697   *       will significantly increases the overall interrupt rate.
00698   */
00699 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim,
00700                                                    uint32_t CalibrationRate)
00701 {
00702   uint32_t hrtim_dllcr;
00703
00704    /* Check the parameters */
00705   assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
00706
00707   /* Process Locked */
00708   __HAL_LOCK(hhrtim);
00709
00710   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00711
00712   /* Enable DLL Ready interrupt flag */
00713   __HAL_HRTIM_ENABLE_IT(hhrtim, HRTIM_IT_DLLRDY);
00714
00715   /* Configure DLL Calibration */
00716   hrtim_dllcr = hhrtim->Instance->sCommonRegs.DLLCR;
00717
00718   if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
00719   {
00720     /* One shot DLL calibration */
00721     hrtim_dllcr &= ~(HRTIM_DLLCR_CALEN);
00722     hrtim_dllcr |= HRTIM_DLLCR_CAL;
00723   }
00724   else
00725   {
00726     /* Periodic DLL calibration */
00727     hrtim_dllcr &= ~(HRTIM_DLLCR_CALRTE | HRTIM_DLLCR_CAL);
00728     hrtim_dllcr |= (CalibrationRate | HRTIM_DLLCR_CALEN);
00729   }
00730
00731   /* Update HRTIM register */
00732   hhrtim->Instance->sCommonRegs.DLLCR = hrtim_dllcr;
00733
00734   return HAL_OK;
00735 }
00736
00737 /**
00738   * @brief  Polls the DLL calibration ready flag and returns when the flag is
00739   *         set (DLL calibration completed) or upon timeout expiration
00740   * @param  hhrtim pointer to HAL HRTIM handle
00741   * @param  Timeout Timeout duration in millisecond
00742   * @retval HAL status
00743   */
00744 HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,
00745                                                   uint32_t Timeout)
00746 {
00747   uint32_t tickstart=0U;
00748
00749   tickstart = HAL_GetTick();
00750
00751   /* Check End of conversion flag */
00752   while(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == RESET)
00753   {
00754     if (Timeout != HAL_MAX_DELAY)
00755     {
00756       if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
00757       {
00758         hhrtim->State = HAL_HRTIM_STATE_ERROR;
00759         return HAL_TIMEOUT;
00760       }
00761     }
00762   }
00763
00764   /* Set HRTIM State */
00765   hhrtim->State = HAL_HRTIM_STATE_READY;
00766
00767   /* Process unlocked */
00768   __HAL_UNLOCK(hhrtim);
00769
00770   return HAL_OK;
00771 }
00772
00773 /**
00774   * @brief  Configures the time base unit of a timer
00775   * @param  hhrtim pointer to HAL HRTIM handle
00776   * @param  TimerIdx Timer index
00777   *                   This parameter can be one of the following values:
00778   *                   @arg HRTIM_TIMERINDEX_MASTER for master timer
00779   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00780   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00781   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00782   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00783   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00784   * @param  pTimeBaseCfg pointer to the time base configuration structure
00785   * @note This function must be called prior starting the timer
00786   * @note   The time-base unit initialization parameters specify:
00787   *           The timer counter operating mode (continuous, one shot),
00788   *           The timer clock prescaler,
00789   *           The timer period ,
00790   *           The timer repetition counter.
00791   * @retval HAL status
00792   */
00793 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
00794                                            uint32_t TimerIdx,
00795                                            HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
00796 {
00797   /* Check the parameters */
00798   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00799   assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
00800   assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
00801
00802   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
00803   {
00804      return HAL_BUSY;
00805   }
00806
00807   /* Set the HRTIM state */
00808   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00809
00810   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
00811   {
00812     /* Configure master timer time base unit */
00813     HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
00814   }
00815   else
00816   {
00817     /* Configure timing unit time base unit */
00818     HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
00819   }
00820
00821   /* Set HRTIM state */
00822   hhrtim->State = HAL_HRTIM_STATE_READY;
00823
00824   return HAL_OK;
00825 }
00826
00827 /**
00828   * @}
00829   */
00830
00831 /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
00832  *  @brief    Simple time base mode functions.
00833 @verbatim
00834  ===============================================================================
00835               ##### Simple time base mode functions #####
00836  ===============================================================================
00837     [..]  This section provides functions allowing to:
00838       (+) Start simple time base
00839       (+) Stop simple time base
00840       (+) Start simple time base and enable interrupt
00841       (+) Stop simple time base and disable interrupt
00842       (+) Start simple time base and enable DMA transfer
00843       (+) Stop simple time base and disable DMA transfer
00844       -@-  When a HRTIM timer operates in simple time base mode, the timer
00845                counter counts from 0 to the period value.
00846
00847 @endverbatim
00848   * @{
00849   */
00850
00851 /**
00852   * @brief  Starts the counter of a timer operating in simple time base mode.
00853   * @param  hhrtim pointer to HAL HRTIM handle
00854   * @param  TimerIdx Timer index.
00855   *                   This parameter can be one of the following values:
00856   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
00857   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00858   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00859   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00860   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00861   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00862   * @retval HAL status
00863   */
00864 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
00865                                            uint32_t TimerIdx)
00866 {
00867    /* Check the parameters */
00868   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00869
00870   /* Process Locked */
00871   __HAL_LOCK(hhrtim);
00872
00873   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00874
00875   /* Enable the timer counter */
00876   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
00877
00878   hhrtim->State = HAL_HRTIM_STATE_READY;
00879
00880   /* Process Unlocked */
00881   __HAL_UNLOCK(hhrtim);
00882
00883   return HAL_OK;
00884 }
00885
00886 /**
00887   * @brief  Stops the counter of a timer operating in simple time base mode.
00888   * @param  hhrtim pointer to HAL HRTIM handle
00889   * @param  TimerIdx Timer index.
00890   *                   This parameter can be one of the following values:
00891   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
00892   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00893   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00894   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00895   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00896   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00897   * @retval HAL status
00898   */
00899 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
00900                                           uint32_t TimerIdx)
00901 {
00902    /* Check the parameters */
00903   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00904
00905   /* Process Locked */
00906   __HAL_LOCK(hhrtim);
00907
00908   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00909
00910   /* Disable the timer counter */
00911   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
00912
00913   hhrtim->State = HAL_HRTIM_STATE_READY;
00914
00915   /* Process Unlocked */
00916   __HAL_UNLOCK(hhrtim);
00917
00918   return HAL_OK;
00919 }
00920
00921 /**
00922   * @brief  Starts the counter of a timer operating in simple time base mode
00923   *         (Timer repetition interrupt is enabled).
00924   * @param  hhrtim pointer to HAL HRTIM handle
00925   * @param  TimerIdx Timer index.
00926   *                   This parameter can be one of the following values:
00927   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
00928   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00929   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00930   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00931   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00932   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00933   * @retval HAL status
00934   */
00935 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
00936                                               uint32_t TimerIdx)
00937 {
00938    /* Check the parameters */
00939   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00940
00941   /* Process Locked */
00942   __HAL_LOCK(hhrtim);
00943
00944   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00945
00946   /* Enable the repetition interrupt */
00947   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
00948   {
00949     __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
00950   }
00951   else
00952   {
00953     __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
00954   }
00955
00956   /* Enable the timer counter */
00957   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
00958
00959   hhrtim->State = HAL_HRTIM_STATE_READY;
00960
00961   /* Process Unlocked */
00962   __HAL_UNLOCK(hhrtim);
00963
00964   return HAL_OK;
00965 }
00966
00967 /**
00968   * @brief  Stops the counter of a timer operating in simple time base mode
00969   *         (Timer repetition interrupt is disabled).
00970   * @param  hhrtim pointer to HAL HRTIM handle
00971   * @param  TimerIdx Timer index.
00972   *                   This parameter can be one of the following values:
00973   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
00974   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00975   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00976   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00977   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00978   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00979   * @retval HAL status
00980   */
00981 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
00982                                              uint32_t TimerIdx)
00983 {
00984    /* Check the parameters */
00985   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00986
00987   /* Process Locked */
00988   __HAL_LOCK(hhrtim);
00989
00990   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00991
00992   /* Disable the repetition interrupt */
00993   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
00994   {
00995     __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
00996   }
00997   else
00998   {
00999     __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
01000   }
01001
01002   /* Disable the timer counter */
01003   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01004
01005   hhrtim->State = HAL_HRTIM_STATE_READY;
01006
01007   /* Process Unlocked */
01008   __HAL_UNLOCK(hhrtim);
01009
01010   return HAL_OK;
01011 }
01012
01013 /**
01014   * @brief  Starts the counter of a timer operating in simple time base mode
01015   *         (Timer repetition DMA request is enabled).
01016   * @param  hhrtim pointer to HAL HRTIM handle
01017   * @param  TimerIdx Timer index.
01018   *                   This parameter can be one of the following values:
01019   *                    @arg HRTIM_TIMERINDEX_MASTER  for master timer
01020   *                    @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01021   *                    @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01022   *                    @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01023   *                    @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01024   *                    @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01025   * @param  SrcAddr DMA transfer source address
01026   * @param  DestAddr DMA transfer destination address
01027   * @param  Length The length of data items (data size) to be transferred
01028   *                     from source to destination
01029   */
01030 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
01031                                                uint32_t TimerIdx,
01032                                                uint32_t SrcAddr,
01033                                                uint32_t DestAddr,
01034                                                uint32_t Length)
01035 {
01036   DMA_HandleTypeDef * hdma;
01037
01038   /* Check the parameters */
01039   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
01040
01041   if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
01042   {
01043      return HAL_BUSY;
01044   }
01045   if((hhrtim->State == HAL_HRTIM_STATE_READY))
01046   {
01047     if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
01048     {
01049       return HAL_ERROR;
01050     }
01051     else
01052     {
01053       hhrtim->State = HAL_HRTIM_STATE_BUSY;
01054     }
01055   }
01056
01057   /* Process Locked */
01058   __HAL_LOCK(hhrtim);
01059
01060   /* Get the timer DMA handler */
01061   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
01062   if (hdma == NULL)
01063   {
01064    hhrtim->State = HAL_HRTIM_STATE_ERROR;
01065
01066    /* Process Unlocked */
01067    __HAL_UNLOCK(hhrtim);
01068
01069    return HAL_ERROR;
01070   }
01071   /* Set the DMA transfer completed callback */
01072   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
01073   {
01074     hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
01075   }
01076   else
01077   {
01078     hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
01079   }
01080
01081   /* Set the DMA error callback */
01082   hdma->XferErrorCallback = HRTIM_DMAError ;
01083
01084   /* Enable the DMA channel */
01085   HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
01086
01087   /* Enable the timer repetition DMA request */
01088   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
01089   {
01090     __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
01091   }
01092   else
01093   {
01094     __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
01095   }
01096
01097   /* Enable the timer counter */
01098   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01099
01100   hhrtim->State = HAL_HRTIM_STATE_READY;
01101
01102   /* Process Unlocked */
01103   __HAL_UNLOCK(hhrtim);
01104
01105   return HAL_OK;
01106 }
01107
01108 /**
01109   * @brief  Stops the counter of a timer operating in simple time base mode
01110   *         (Timer repetition DMA request is disabled).
01111   * @param  hhrtim pointer to HAL HRTIM handle
01112   * @param  TimerIdx Timer index.
01113   *                   This parameter can be one of the following values:
01114   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
01115   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01116   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01117   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01118   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01119   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01120   * @retval HAL status
01121   */
01122 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
01123                                               uint32_t TimerIdx)
01124 {
01125   DMA_HandleTypeDef * hdma;
01126
01127   /* Check the parameters */
01128   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
01129
01130   /* Process Locked */
01131   __HAL_LOCK(hhrtim);
01132
01133   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
01134   {
01135     /* Disable the DMA */
01136     HAL_DMA_Abort(hhrtim->hdmaMaster);
01137
01138     /* Disable the timer repetition DMA request */
01139     __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
01140   }
01141   else
01142   {
01143     /* Get the timer DMA handler */
01144     hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
01145
01146     if (hdma == NULL)
01147     {
01148       /* Disable the timer repetition DMA request */
01149       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
01150
01151       /* Disable the timer counter */
01152       __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01153
01154       hhrtim->State = HAL_HRTIM_STATE_ERROR;
01155
01156       /* Process Unlocked */
01157       __HAL_UNLOCK(hhrtim);
01158
01159       return HAL_ERROR;
01160     }
01161     else
01162     {
01163       /* Disable the DMA */
01164       HAL_DMA_Abort(hdma);
01165
01166       /* Disable the timer repetition DMA request */
01167       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
01168     }
01169   }
01170
01171   /* Disable the timer counter */
01172   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01173
01174   hhrtim->State = HAL_HRTIM_STATE_READY;
01175
01176   /* Process Unlocked */
01177   __HAL_UNLOCK(hhrtim);
01178
01179   return HAL_OK;
01180 }
01181
01182 /**
01183   * @}
01184   */
01185
01186 /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
01187  *  @brief    Simple output compare functions
01188 @verbatim
01189  ===============================================================================
01190               ##### Simple output compare functions #####
01191  ===============================================================================
01192     [..]  This section provides functions allowing to:
01193       (+) Configure simple output channel
01194       (+) Start simple output compare
01195       (+) Stop simple output compare
01196       (+) Start simple output compare and enable interrupt
01197       (+) Stop simple output compare and disable interrupt
01198       (+) Start simple output compare and enable DMA transfer
01199       (+) Stop simple output compare and disable DMA transfer
01200        -@- When a HRTIM timer operates in simple output compare mode
01201            the output level is set to a programmable value when a match
01202            is found between the compare register and the counter.
01203            Compare unit 1 is automatically associated to output 1
01204            Compare unit 2 is automatically associated to output 2
01205 @endverbatim
01206   * @{
01207   */
01208
01209 /**
01210   * @brief  Configures an output in simple output compare mode
01211   * @param  hhrtim pointer to HAL HRTIM handle
01212   * @param  TimerIdx Timer index
01213   *                   This parameter can be one of the following values:
01214   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01215   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01216   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01217   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01218   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01219   * @param  OCChannel Timer output
01220   *                    This parameter can be one of the following values:
01221   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01222   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01223   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01224   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01225   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01226   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01227   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01228   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01229   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01230   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01231   * @param  pSimpleOCChannelCfg pointer to the simple output compare output configuration structure
01232   * @note When the timer operates in simple output compare mode:
01233   *         Output 1 is implicitly controlled by the compare unit 1
01234   *         Output 2 is implicitly controlled by the compare unit 2
01235   *       Output Set/Reset crossbar is set according to the selected output compare mode:
01236   *         Toggle: SETxyR = RSTxyR = CMPy
01237   *         Active: SETxyR = CMPy, RSTxyR = 0
01238   *         Inactive: SETxy =0, RSTxy = CMPy
01239   * @retval HAL status
01240   */
01241 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
01242                                                  uint32_t TimerIdx,
01243                                                  uint32_t OCChannel,
01244                                                  HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
01245 {
01246   uint32_t CompareUnit = 0xFFFFFFFFU;
01247   HRTIM_CompareCfgTypeDef CompareCfg = {0};
01248   HRTIM_OutputCfgTypeDef OutputCfg = {0};
01249
01250   /* Check parameters */
01251   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01252   assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
01253   assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
01254   assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
01255
01256   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
01257   {
01258      return HAL_BUSY;
01259   }
01260
01261   /* Set HRTIM state */
01262   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01263
01264   /* Configure timer compare unit */
01265   switch (OCChannel)
01266   {
01267   case HRTIM_OUTPUT_TA1:
01268   case HRTIM_OUTPUT_TB1:
01269   case HRTIM_OUTPUT_TC1:
01270   case HRTIM_OUTPUT_TD1:
01271   case HRTIM_OUTPUT_TE1:
01272     {
01273       CompareUnit = HRTIM_COMPAREUNIT_1;
01274     }
01275     break;
01276   case HRTIM_OUTPUT_TA2:
01277   case HRTIM_OUTPUT_TB2:
01278   case HRTIM_OUTPUT_TC2:
01279   case HRTIM_OUTPUT_TD2:
01280   case HRTIM_OUTPUT_TE2:
01281     {
01282       CompareUnit = HRTIM_COMPAREUNIT_2;
01283     }
01284     break;
01285   default:
01286     break;
01287   }
01288
01289   CompareCfg.CompareValue = pSimpleOCChannelCfg->Pulse;
01290   CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
01291   CompareCfg.AutoDelayedTimeout = 0U;
01292
01293   HRTIM_CompareUnitConfig(hhrtim,
01294                           TimerIdx,
01295                           CompareUnit,
01296                           &CompareCfg);
01297
01298   /* Configure timer output */
01299   OutputCfg.Polarity = pSimpleOCChannelCfg->Polarity;
01300   OutputCfg.IdleLevel = pSimpleOCChannelCfg->IdleLevel;
01301   OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
01302   OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
01303   OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
01304   OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
01305
01306   switch (pSimpleOCChannelCfg->Mode)
01307   {
01308   case HRTIM_BASICOCMODE_TOGGLE:
01309     {
01310       if (CompareUnit == HRTIM_COMPAREUNIT_1)
01311       {
01312         OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
01313       }
01314       else
01315       {
01316         OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
01317       }
01318       OutputCfg.ResetSource = OutputCfg.SetSource;
01319     }
01320     break;
01321   case HRTIM_BASICOCMODE_ACTIVE:
01322     {
01323       if (CompareUnit == HRTIM_COMPAREUNIT_1)
01324       {
01325         OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
01326       }
01327       else
01328       {
01329         OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
01330       }
01331       OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
01332     }
01333     break;
01334   case HRTIM_BASICOCMODE_INACTIVE:
01335     {
01336       if (CompareUnit == HRTIM_COMPAREUNIT_1)
01337       {
01338         OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
01339       }
01340       else
01341       {
01342         OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
01343       }
01344       OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
01345     }
01346     break;
01347   default:
01348     break;
01349   }
01350
01351   HRTIM_OutputConfig(hhrtim,
01352                      TimerIdx,
01353                      OCChannel,
01354                      &OutputCfg);
01355
01356   /* Set HRTIM state */
01357   hhrtim->State = HAL_HRTIM_STATE_READY;
01358
01359   return HAL_OK;
01360 }
01361
01362 /**
01363   * @brief  Starts the output compare signal generation on the designed timer output
01364   * @param  hhrtim pointer to HAL HRTIM handle
01365   * @param  TimerIdx Timer index
01366   *                   This parameter can be one of the following values:
01367   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01368   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01369   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01370   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01371   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01372   * @param  OCChannel Timer output
01373   *                    This parameter can be one of the following values:
01374   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01375   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01376   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01377   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01378   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01379   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01380   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01381   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01382   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01383   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01384   * @retval HAL status
01385   */
01386 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
01387                                          uint32_t TimerIdx,
01388                                          uint32_t OCChannel)
01389 {
01390    /* Check the parameters */
01391   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01392
01393   /* Process Locked */
01394   __HAL_LOCK(hhrtim);
01395
01396   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01397
01398   /* Enable the timer output */
01399   hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
01400
01401   /* Enable the timer counter */
01402   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01403
01404   hhrtim->State = HAL_HRTIM_STATE_READY;
01405
01406   /* Process Unlocked */
01407   __HAL_UNLOCK(hhrtim);
01408
01409   return HAL_OK;
01410 }
01411
01412 /**
01413   * @brief  Stops the output compare signal generation on the designed timer output
01414   * @param  hhrtim pointer to HAL HRTIM handle
01415   * @param  TimerIdx Timer index
01416   *                   This parameter can be one of the following values:
01417   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01418   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01419   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01420   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01421   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01422   * @param  OCChannel Timer output
01423   *                    This parameter can be one of the following values:
01424   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01425   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01426   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01427   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01428   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01429   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01430   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01431   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01432   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01433   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01434   * @retval HAL status
01435   */
01436 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
01437                                         uint32_t TimerIdx,
01438                                         uint32_t OCChannel)
01439 {
01440    /* Check the parameters */
01441   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01442
01443   /* Process Locked */
01444   __HAL_LOCK(hhrtim);
01445
01446   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01447
01448   /* Disable the timer output */
01449   hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
01450
01451   /* Disable the timer counter */
01452   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01453
01454   hhrtim->State = HAL_HRTIM_STATE_READY;
01455
01456   /* Process Unlocked */
01457   __HAL_UNLOCK(hhrtim);
01458
01459   return HAL_OK;
01460 }
01461
01462 /**
01463   * @brief  Starts the output compare signal generation on the designed timer output
01464   *         (Interrupt is enabled (see note note below)).
01465   * @param  hhrtim pointer to HAL HRTIM handle
01466   * @param  TimerIdx Timer index
01467   *                   This parameter can be one of the following values:
01468   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01469   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01470   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01471   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01472   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01473   * @param  OCChannel Timer output
01474   *                    This parameter can be one of the following values:
01475   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01476   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01477   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01478   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01479   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01480   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01481   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01482   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01483   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01484   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01485   * @note Interrupt enabling depends on the chosen output compare mode
01486   *          Output toggle: compare match interrupt is enabled
01487   *          Output set active:  output set interrupt is enabled
01488   *          Output set inactive:  output reset interrupt is enabled
01489   * @retval HAL status
01490   */
01491 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
01492                                             uint32_t TimerIdx,
01493                                             uint32_t OCChannel)
01494 {
01495   uint32_t interrupt;
01496
01497    /* Check the parameters */
01498   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01499
01500   /* Process Locked */
01501   __HAL_LOCK(hhrtim);
01502
01503   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01504
01505   /* Get the interrupt to enable (depends on the output compare mode) */
01506   interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
01507
01508   /* Enable the timer output */
01509   hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
01510
01511   /* Enable the timer interrupt (depends on the output compare mode) */
01512   __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
01513
01514   /* Enable the timer counter */
01515   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01516
01517   hhrtim->State = HAL_HRTIM_STATE_READY;
01518
01519   /* Process Unlocked */
01520   __HAL_UNLOCK(hhrtim);
01521
01522   return HAL_OK;
01523 }
01524
01525 /**
01526   * @brief  Stops the output compare signal generation on the designed timer output
01527   *         (Interrupt is disabled).
01528   * @param  hhrtim pointer to HAL HRTIM handle
01529   * @param  TimerIdx Timer index
01530   *                   This parameter can be one of the following values:
01531   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01532   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01533   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01534   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01535   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01536   * @param  OCChannel Timer output
01537   *                    This parameter can be one of the following values:
01538   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01539   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01540   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01541   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01542   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01543   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01544   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01545   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01546   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01547   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01548   * @retval HAL status
01549   */
01550 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
01551                                            uint32_t TimerIdx,
01552                                            uint32_t OCChannel)
01553 {
01554   uint32_t interrupt;
01555
01556    /* Check the parameters */
01557   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01558
01559   /* Process Locked */
01560   __HAL_LOCK(hhrtim);
01561
01562   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01563
01564   /* Disable the timer output */
01565   hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
01566
01567   /* Get the interrupt to disable (depends on the output compare mode) */
01568   interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
01569
01570   /* Disable the timer interrupt */
01571   __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
01572
01573   /* Disable the timer counter */
01574   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01575
01576   hhrtim->State = HAL_HRTIM_STATE_READY;
01577
01578   /* Process Unlocked */
01579   __HAL_UNLOCK(hhrtim);
01580
01581   return HAL_OK;
01582 }
01583
01584 /**
01585   * @brief  Starts the output compare signal generation on the designed timer output
01586   *         (DMA request is enabled (see note below)).
01587   * @param  hhrtim pointer to HAL HRTIM handle
01588   * @param  TimerIdx Timer index
01589   *                   This parameter can be one of the following values:
01590   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01591   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01592   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01593   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01594   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01595   * @param  OCChannel Timer output
01596   *                    This parameter can be one of the following values:
01597   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01598   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01599   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01600   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01601   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01602   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01603   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01604   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01605   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01606   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01607   * @param  SrcAddr DMA transfer source address
01608   * @param  DestAddr DMA transfer destination address
01609   * @param  Length The length of data items (data size) to be transferred
01610   *                     from source to destination
01611   * @note  DMA request enabling depends on the chosen output compare mode
01612   *          Output toggle: compare match DMA request is enabled
01613   *          Output set active:  output set DMA request is enabled
01614   *          Output set inactive:  output reset DMA request is enabled
01615   * @retval HAL status
01616   */
01617 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
01618                                              uint32_t TimerIdx,
01619                                              uint32_t OCChannel,
01620                                              uint32_t SrcAddr,
01621                                              uint32_t DestAddr,
01622                                              uint32_t Length)
01623 {
01624   DMA_HandleTypeDef * hdma;
01625   uint32_t dma_request;
01626
01627   /* Check the parameters */
01628   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01629
01630   if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
01631   {
01632      return HAL_BUSY;
01633   }
01634   if((hhrtim->State == HAL_HRTIM_STATE_READY))
01635   {
01636     if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
01637     {
01638       return HAL_ERROR;
01639     }
01640     else
01641     {
01642       hhrtim->State = HAL_HRTIM_STATE_BUSY;
01643     }
01644   }
01645
01646   /* Process Locked */
01647   __HAL_LOCK(hhrtim);
01648
01649    /* Enable the timer output */
01650   hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
01651
01652   /* Get the DMA request to enable */
01653   dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
01654
01655   /* Get the timer DMA handler */
01656   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
01657   if (hdma == NULL)
01658   {
01659    hhrtim->State = HAL_HRTIM_STATE_ERROR;
01660
01661    /* Process Unlocked */
01662    __HAL_UNLOCK(hhrtim);
01663
01664    return HAL_ERROR;
01665   }
01666
01667   /* Set the DMA error callback */
01668   hdma->XferErrorCallback = HRTIM_DMAError ;
01669
01670   /* Set the DMA transfer completed callback */
01671   hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
01672
01673   /* Enable the DMA channel */
01674   HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
01675
01676   /* Enable the timer DMA request */
01677   __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
01678
01679   /* Enable the timer counter */
01680   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01681
01682   hhrtim->State = HAL_HRTIM_STATE_READY;
01683
01684   /* Process Unlocked */
01685   __HAL_UNLOCK(hhrtim);
01686
01687   return HAL_OK;
01688 }
01689
01690 /**
01691   * @brief  Stops the output compare signal generation on the designed timer output
01692   *         (DMA request is disabled).
01693   * @param  hhrtim pointer to HAL HRTIM handle
01694   * @param  TimerIdx Timer index
01695   *                   This parameter can be one of the following values:
01696   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01697   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01698   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01699   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01700   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01701   * @param  OCChannel Timer output
01702   *                    This parameter can be one of the following values:
01703   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01704   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01705   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01706   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01707   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01708   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01709   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01710   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01711   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01712   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01713   * @retval HAL status
01714   */
01715 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
01716                                             uint32_t TimerIdx,
01717                                             uint32_t OCChannel)
01718 {
01719   DMA_HandleTypeDef * hdma;
01720   uint32_t dma_request;
01721
01722   /* Check the parameters */
01723   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01724
01725   /* Process Locked */
01726   __HAL_LOCK(hhrtim);
01727
01728   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01729
01730   /* Disable the timer output */
01731   hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
01732
01733   /* Get the timer DMA handler */
01734   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
01735   if (hdma == NULL)
01736   {
01737    hhrtim->State = HAL_HRTIM_STATE_ERROR;
01738
01739    /* Process Unlocked */
01740    __HAL_UNLOCK(hhrtim);
01741
01742    return HAL_ERROR;
01743   }
01744
01745   /* Disable the DMA */
01746   HAL_DMA_Abort(hdma);
01747
01748   /* Get the DMA request to disable */
01749   dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
01750
01751   /* Disable the timer DMA request */
01752   __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
01753
01754   /* Disable the timer counter */
01755   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01756
01757   hhrtim->State = HAL_HRTIM_STATE_READY;
01758
01759   /* Process Unlocked */
01760   __HAL_UNLOCK(hhrtim);
01761
01762   return HAL_OK;
01763 }
01764
01765 /**
01766   * @}
01767   */
01768
01769 /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
01770  *  @brief    Simple PWM output functions
01771 @verbatim
01772  ===============================================================================
01773               ##### Simple PWM output functions #####
01774  ===============================================================================
01775     [..]  This section provides functions allowing to:
01776       (+) Configure simple PWM output channel
01777       (+) Start simple PWM output
01778       (+) Stop simple PWM output
01779       (+) Start simple PWM output and enable interrupt
01780       (+) Stop simple PWM output and disable interrupt
01781       (+) Start simple PWM output and enable DMA transfer
01782       (+) Stop simple PWM output and disable DMA transfer
01783           -@- When a HRTIM timer operates in simple PWM output mode
01784           the output level is set to a programmable value when a match is
01785           found between the compare register and the counter and reset when
01786           the timer period is reached. Duty cycle is determined by the
01787           comparison value.
01788           Compare unit 1 is automatically associated to output 1
01789           Compare unit 2 is automatically associated to output 2
01790 @endverbatim
01791   * @{
01792   */
01793
01794 /**
01795   * @brief  Configures an output in simple PWM mode
01796   * @param  hhrtim pointer to HAL HRTIM handle
01797   * @param  TimerIdx Timer index
01798   *                   This parameter can be one of the following values:
01799   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01800   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01801   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01802   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01803   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01804   * @param  PWMChannel Timer output
01805   *                    This parameter can be one of the following values:
01806   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01807   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01808   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01809   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01810   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01811   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01812   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01813   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01814   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01815   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01816   * @param  pSimplePWMChannelCfg pointer to the simple PWM output configuration structure
01817   * @note When the timer operates in simple PWM output mode:
01818   *         Output 1 is implicitly controlled by the compare unit 1
01819   *         Output 2 is implicitly controlled by the compare unit 2
01820   *       Output Set/Reset crossbar is set as follows:
01821   *         Output 1: SETx1R = CMP1, RSTx1R = PER
01822   *         Output 2: SETx2R = CMP2, RST2R = PER
01823   * @note When Simple PWM mode is used the registers preload mechanism is
01824   *       enabled (otherwise the behavior is not guaranteed).
01825   * @retval HAL status
01826   */
01827 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
01828                                                   uint32_t TimerIdx,
01829                                                   uint32_t PWMChannel,
01830                                                   HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
01831 {
01832   uint32_t CompareUnit = 0xFFFFFFFFU;
01833   HRTIM_CompareCfgTypeDef CompareCfg;
01834   HRTIM_OutputCfgTypeDef OutputCfg;
01835   uint32_t hrtim_timcr;
01836
01837   /* Check parameters */
01838   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
01839   assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
01840   assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
01841
01842   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
01843   {
01844      return HAL_BUSY;
01845   }
01846
01847   /* Process Locked */
01848   __HAL_LOCK(hhrtim);  hhrtim->State = HAL_HRTIM_STATE_BUSY;
01849
01850   /* Configure timer compare unit */
01851   switch (PWMChannel)
01852   {
01853   case HRTIM_OUTPUT_TA1:
01854   case HRTIM_OUTPUT_TB1:
01855   case HRTIM_OUTPUT_TC1:
01856   case HRTIM_OUTPUT_TD1:
01857   case HRTIM_OUTPUT_TE1:
01858     {
01859       CompareUnit = HRTIM_COMPAREUNIT_1;
01860     }
01861     break;
01862   case HRTIM_OUTPUT_TA2:
01863   case HRTIM_OUTPUT_TB2:
01864   case HRTIM_OUTPUT_TC2:
01865   case HRTIM_OUTPUT_TD2:
01866   case HRTIM_OUTPUT_TE2:
01867     {
01868       CompareUnit = HRTIM_COMPAREUNIT_2;
01869     }
01870     break;
01871   default:
01872     break;
01873   }
01874
01875   CompareCfg.CompareValue = pSimplePWMChannelCfg->Pulse;
01876   CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
01877   CompareCfg.AutoDelayedTimeout = 0U;
01878
01879   HRTIM_CompareUnitConfig(hhrtim,
01880                           TimerIdx,
01881                           CompareUnit,
01882                           &CompareCfg);
01883
01884   /* Configure timer output */
01885   OutputCfg.Polarity = pSimplePWMChannelCfg->Polarity;
01886   OutputCfg.IdleLevel = pSimplePWMChannelCfg->IdleLevel;
01887   OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
01888   OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
01889   OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
01890   OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
01891
01892   if (CompareUnit == HRTIM_COMPAREUNIT_1)
01893   {
01894     OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
01895   }
01896   else
01897   {
01898     OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
01899   }
01900   OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
01901
01902   HRTIM_OutputConfig(hhrtim,
01903                      TimerIdx,
01904                      PWMChannel,
01905                      &OutputCfg);
01906
01907   /* Enable the registers preload mechanism */
01908   hrtim_timcr   = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
01909   hrtim_timcr |= HRTIM_TIMCR_PREEN;
01910   hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR  = hrtim_timcr;
01911
01912   hhrtim->State = HAL_HRTIM_STATE_READY;
01913
01914   /* Process Unlocked */
01915   __HAL_UNLOCK(hhrtim);
01916
01917   return HAL_OK;
01918 }
01919
01920 /**
01921   * @brief  Starts the PWM output signal generation on the designed timer output
01922   * @param  hhrtim pointer to HAL HRTIM handle
01923   * @param  TimerIdx Timer index
01924   *                   This parameter can be one of the following values:
01925   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01926   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01927   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01928   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01929   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01930   * @param  PWMChannel Timer output
01931   *                    This parameter can be one of the following values:
01932   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01933   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01934   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01935   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01936   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01937   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01938   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01939   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01940   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01941   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01942   * @retval HAL status
01943   */
01944 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
01945                                           uint32_t TimerIdx,
01946                                           uint32_t PWMChannel)
01947 {
01948    /* Check the parameters */
01949   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
01950
01951   /* Process Locked */
01952   __HAL_LOCK(hhrtim);
01953
01954   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01955
01956   /* Enable the timer output */
01957   hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
01958
01959   /* Enable the timer counter */
01960   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01961
01962   hhrtim->State = HAL_HRTIM_STATE_READY;
01963
01964   /* Process Unlocked */
01965   __HAL_UNLOCK(hhrtim);
01966
01967   return HAL_OK;
01968 }
01969
01970 /**
01971   * @brief  Stops the PWM output signal generation on the designed timer output
01972   * @param  hhrtim pointer to HAL HRTIM handle
01973   * @param  TimerIdx Timer index
01974   *                   This parameter can be one of the following values:
01975   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01976   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01977   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01978   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01979   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01980   * @param  PWMChannel Timer output
01981   *                    This parameter can be one of the following values:
01982   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01983   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01984   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01985   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01986   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01987   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01988   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01989   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01990   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01991   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01992   * @retval HAL status
01993   */
01994 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
01995                                          uint32_t TimerIdx,
01996                                          uint32_t PWMChannel)
01997 {
01998    /* Check the parameters */
01999   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
02000
02001   /* Process Locked */
02002   __HAL_LOCK(hhrtim);
02003
02004   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02005
02006   /* Disable the timer output */
02007   hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
02008
02009   /* Disable the timer counter */
02010   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02011
02012   hhrtim->State = HAL_HRTIM_STATE_READY;
02013
02014   /* Process Unlocked */
02015   __HAL_UNLOCK(hhrtim);
02016
02017   return HAL_OK;
02018 }
02019
02020 /**
02021   * @brief  Starts the PWM output signal generation on the designed timer output
02022   *         (The compare interrupt is enabled).
02023   * @param  hhrtim pointer to HAL HRTIM handle
02024   * @param  TimerIdx Timer index
02025   *                   This parameter can be one of the following values:
02026   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02027   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02028   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02029   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02030   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02031   * @param  PWMChannel Timer output
02032   *                    This parameter can be one of the following values:
02033   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02034   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02035   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02036   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02037   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02038   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02039   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02040   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02041   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02042   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02043   * @retval HAL status
02044   */
02045 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
02046                                              uint32_t TimerIdx,
02047                                              uint32_t PWMChannel)
02048 {
02049    /* Check the parameters */
02050   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
02051
02052   /* Process Locked */
02053   __HAL_LOCK(hhrtim);
02054
02055   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02056
02057   /* Enable the timer output */
02058   hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
02059
02060   /* Enable the timer interrupt (depends on the PWM output) */
02061   switch (PWMChannel)
02062   {
02063   case HRTIM_OUTPUT_TA1:
02064   case HRTIM_OUTPUT_TB1:
02065   case HRTIM_OUTPUT_TC1:
02066   case HRTIM_OUTPUT_TD1:
02067   case HRTIM_OUTPUT_TE1:
02068     {
02069       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
02070     }
02071     break;
02072   case HRTIM_OUTPUT_TA2:
02073   case HRTIM_OUTPUT_TB2:
02074   case HRTIM_OUTPUT_TC2:
02075   case HRTIM_OUTPUT_TD2:
02076   case HRTIM_OUTPUT_TE2:
02077     {
02078       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
02079     }
02080     break;
02081   default:
02082     break;
02083   }
02084
02085   /* Enable the timer counter */
02086   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02087
02088   hhrtim->State = HAL_HRTIM_STATE_READY;
02089
02090   /* Process Unlocked */
02091   __HAL_UNLOCK(hhrtim);
02092
02093   return HAL_OK;
02094 }
02095
02096 /**
02097   * @brief  Stops the PWM output signal generation on the designed timer output
02098   *         (The compare interrupt is disabled).
02099   * @param  hhrtim pointer to HAL HRTIM handle
02100   * @param  TimerIdx Timer index
02101   *                   This parameter can be one of the following values:
02102   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02103   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02104   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02105   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02106   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02107   * @param  PWMChannel Timer output
02108   *                    This parameter can be one of the following values:
02109   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02110   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02111   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02112   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02113   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02114   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02115   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02116   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02117   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02118   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02119   * @retval HAL status
02120   */
02121 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
02122                                             uint32_t TimerIdx,
02123                                             uint32_t PWMChannel)
02124 {
02125    /* Check the parameters */
02126   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
02127
02128   /* Process Locked */
02129   __HAL_LOCK(hhrtim);
02130
02131   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02132
02133   /* Disable the timer output */
02134   hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
02135
02136   /* Disable the timer interrupt (depends on the PWM output) */
02137   switch (PWMChannel)
02138   {
02139   case HRTIM_OUTPUT_TA1:
02140   case HRTIM_OUTPUT_TB1:
02141   case HRTIM_OUTPUT_TC1:
02142   case HRTIM_OUTPUT_TD1:
02143   case HRTIM_OUTPUT_TE1:
02144     {
02145       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
02146     }
02147     break;
02148   case HRTIM_OUTPUT_TA2:
02149   case HRTIM_OUTPUT_TB2:
02150   case HRTIM_OUTPUT_TC2:
02151   case HRTIM_OUTPUT_TD2:
02152   case HRTIM_OUTPUT_TE2:
02153     {
02154       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
02155     }
02156     break;
02157   default:
02158     break;
02159   }
02160
02161   /* Disable the timer counter */
02162   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02163
02164   hhrtim->State = HAL_HRTIM_STATE_READY;
02165
02166   /* Process Unlocked */
02167   __HAL_UNLOCK(hhrtim);
02168
02169   return HAL_OK;
02170 }
02171
02172 /**
02173   * @brief  Starts the PWM output signal generation on the designed timer output
02174   *         (The compare DMA request is enabled).
02175   * @param  hhrtim pointer to HAL HRTIM handle
02176   * @param  TimerIdx Timer index
02177   *                   This parameter can be one of the following values:
02178   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02179   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02180   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02181   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02182   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02183   * @param  PWMChannel Timer output
02184   *                    This parameter can be one of the following values:
02185   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02186   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02187   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02188   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02189   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02190   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02191   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02192   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02193   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02194   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02195   * @param  SrcAddr DMA transfer source address
02196   * @param  DestAddr DMA transfer destination address
02197   * @param  Length The length of data items (data size) to be transferred
02198   *                     from source to destination
02199   * @retval HAL status
02200   */
02201 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
02202                                               uint32_t TimerIdx,
02203                                               uint32_t PWMChannel,
02204                                               uint32_t SrcAddr,
02205                                               uint32_t DestAddr,
02206                                               uint32_t Length)
02207 {
02208   DMA_HandleTypeDef * hdma;
02209
02210   /* Check the parameters */
02211   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
02212
02213   if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
02214   {
02215      return HAL_BUSY;
02216   }
02217   if((hhrtim->State == HAL_HRTIM_STATE_READY))
02218   {
02219     if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
02220     {
02221       return HAL_ERROR;
02222     }
02223     else
02224     {
02225       hhrtim->State = HAL_HRTIM_STATE_BUSY;
02226     }
02227   }
02228
02229   /* Process Locked */
02230   __HAL_LOCK(hhrtim);
02231
02232   /* Enable the timer output */
02233   hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
02234
02235   /* Get the timer DMA handler */
02236   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
02237   if (hdma == NULL)
02238   {
02239    hhrtim->State = HAL_HRTIM_STATE_ERROR;
02240
02241    /* Process Unlocked */
02242    __HAL_UNLOCK(hhrtim);
02243
02244    return HAL_ERROR;
02245   }
02246
02247   /* Set the DMA error callback */
02248   hdma->XferErrorCallback = HRTIM_DMAError ;
02249
02250   /* Set the DMA transfer completed callback */
02251   hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
02252
02253   /* Enable the DMA channel */
02254   HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
02255
02256   /* Enable the timer DMA request */
02257   switch (PWMChannel)
02258   {
02259   case HRTIM_OUTPUT_TA1:
02260   case HRTIM_OUTPUT_TB1:
02261   case HRTIM_OUTPUT_TC1:
02262   case HRTIM_OUTPUT_TD1:
02263   case HRTIM_OUTPUT_TE1:
02264     {
02265       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
02266     }
02267     break;
02268   case HRTIM_OUTPUT_TA2:
02269   case HRTIM_OUTPUT_TB2:
02270   case HRTIM_OUTPUT_TC2:
02271   case HRTIM_OUTPUT_TD2:
02272   case HRTIM_OUTPUT_TE2:
02273     {
02274       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
02275     }
02276     break;
02277   default:
02278     break;
02279   }
02280
02281   /* Enable the timer counter */
02282   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02283
02284   hhrtim->State = HAL_HRTIM_STATE_READY;
02285
02286   /* Process Unlocked */
02287   __HAL_UNLOCK(hhrtim);
02288
02289   return HAL_OK;
02290 }
02291
02292 /**
02293   * @brief  Stops the PWM output signal generation on the designed timer output
02294   *         (The compare DMA request is disabled).
02295   * @param  hhrtim pointer to HAL HRTIM handle
02296   * @param  TimerIdx Timer index
02297   *                   This parameter can be one of the following values:
02298   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02299   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02300   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02301   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02302   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02303   * @param  PWMChannel Timer output
02304   *                    This parameter can be one of the following values:
02305   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02306   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02307   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02308   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02309   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02310   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02311   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02312   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02313   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02314   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02315   * @retval HAL status
02316   */
02317 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
02318                                              uint32_t TimerIdx,
02319                                              uint32_t PWMChannel)
02320 {
02321   DMA_HandleTypeDef * hdma;
02322
02323   /* Check the parameters */
02324   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
02325
02326   /* Process Locked */
02327   __HAL_LOCK(hhrtim);
02328
02329   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02330
02331   /* Disable the timer output */
02332   hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
02333
02334   /* Get the timer DMA handler */
02335   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
02336   if (hdma == NULL)
02337   {
02338    hhrtim->State = HAL_HRTIM_STATE_ERROR;
02339
02340    /* Process Unlocked */
02341    __HAL_UNLOCK(hhrtim);
02342
02343    return HAL_ERROR;
02344   }
02345
02346   /* Disable the DMA */
02347   HAL_DMA_Abort(hdma);
02348
02349   /* Disable the timer DMA request */
02350   switch (PWMChannel)
02351   {
02352   case HRTIM_OUTPUT_TA1:
02353   case HRTIM_OUTPUT_TB1:
02354   case HRTIM_OUTPUT_TC1:
02355   case HRTIM_OUTPUT_TD1:
02356   case HRTIM_OUTPUT_TE1:
02357     {
02358       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
02359     }
02360     break;
02361   case HRTIM_OUTPUT_TA2:
02362   case HRTIM_OUTPUT_TB2:
02363   case HRTIM_OUTPUT_TC2:
02364   case HRTIM_OUTPUT_TD2:
02365   case HRTIM_OUTPUT_TE2:
02366     {
02367       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
02368     }
02369     break;
02370   default:
02371     break;
02372   }
02373
02374   /* Disable the timer counter */
02375   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02376
02377   hhrtim->State = HAL_HRTIM_STATE_READY;
02378
02379   /* Process Unlocked */
02380   __HAL_UNLOCK(hhrtim);
02381
02382   return HAL_OK;
02383 }
02384
02385 /**
02386   * @}
02387   */
02388
02389 /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
02390  *  @brief    Simple input capture functions
02391 @verbatim
02392  ===============================================================================
02393               ##### Simple input capture functions #####
02394  ===============================================================================
02395     [..]  This section provides functions allowing to:
02396       (+) Configure simple input capture channel
02397       (+) Start simple input capture
02398       (+) Stop simple input capture
02399       (+) Start simple input capture and enable interrupt
02400       (+) Stop simple input capture and disable interrupt
02401       (+) Start simple input capture and enable DMA transfer
02402       (+) Stop simple input capture and disable DMA transfer
02403       -@- When a HRTIM timer operates in simple input capture mode
02404           the Capture Register (HRTIM_CPT1/2xR) is used to latch the
02405          value of the timer counter counter after a transition detected
02406          on a given external event input.
02407 @endverbatim
02408   * @{
02409   */
02410
02411 /**
02412   * @brief  Configures a simple capture
02413   * @param  hhrtim pointer to HAL HRTIM handle
02414   * @param  TimerIdx Timer index
02415   *                   This parameter can be one of the following values:
02416   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02417   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02418   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02419   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02420   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02421   * @param  CaptureChannel Capture unit
02422   *                    This parameter can be one of the following values:
02423   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02424   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02425   * @param  pSimpleCaptureChannelCfg pointer to the simple capture configuration structure
02426   * @note When the timer operates in simple capture mode the capture is trigerred
02427   *       by the designated external event and GPIO input is implicitly used as event source.
02428   *       The cature can be triggered by a rising edge, a falling edge or both
02429   *       edges on event channel.
02430   * @retval HAL status
02431   */
02432 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
02433                                                       uint32_t TimerIdx,
02434                                                       uint32_t CaptureChannel,
02435                                                       HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
02436 {
02437   HRTIM_EventCfgTypeDef EventCfg;
02438
02439   /* Check parameters */
02440   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02441   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02442   assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
02443   assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
02444                                       pSimpleCaptureChannelCfg->EventPolarity));
02445   assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
02446   assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
02447                                     pSimpleCaptureChannelCfg->EventFilter));
02448
02449   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
02450   {
02451      return HAL_BUSY;
02452   }
02453
02454   /* Process Locked */
02455   __HAL_LOCK(hhrtim);
02456
02457   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02458
02459   /* Configure external event channel */
02460   EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
02461   EventCfg.Filter = pSimpleCaptureChannelCfg->EventFilter;
02462   EventCfg.Polarity = pSimpleCaptureChannelCfg->EventPolarity;
02463   EventCfg.Sensitivity = pSimpleCaptureChannelCfg->EventSensitivity;
02464   EventCfg.Source = HRTIM_EVENTSRC_1;
02465
02466   HRTIM_EventConfig(hhrtim,
02467                     pSimpleCaptureChannelCfg->Event,
02468                     &EventCfg);
02469
02470   /* Memorize capture trigger (will be configured when the capture is started */
02471   HRTIM_CaptureUnitConfig(hhrtim,
02472                           TimerIdx,
02473                           CaptureChannel,
02474                           pSimpleCaptureChannelCfg->Event);
02475
02476   hhrtim->State = HAL_HRTIM_STATE_READY;
02477
02478   /* Process Unlocked */
02479   __HAL_UNLOCK(hhrtim);
02480
02481   return HAL_OK;
02482 }
02483
02484 /**
02485   * @brief  Enables a simple capture on the designed capture unit
02486   * @param  hhrtim pointer to HAL HRTIM handle
02487   * @param  TimerIdx Timer index
02488   *                   This parameter can be one of the following values:
02489   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02490   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02491   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02492   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02493   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02494   * @param  CaptureChannel Timer output
02495   *                    This parameter can be one of the following values:
02496   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02497   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02498   * @retval HAL status
02499   * @note  The external event triggering the capture is available for all timing
02500   *        units. It can be used directly and is active as soon as the timing
02501   *        unit counter is enabled.
02502   */
02503 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
02504                                               uint32_t TimerIdx,
02505                                               uint32_t CaptureChannel)
02506 {
02507    /* Check the parameters */
02508   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02509   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02510
02511   /* Process Locked */
02512   __HAL_LOCK(hhrtim);
02513
02514   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02515
02516   /* Set the capture unit trigger */
02517   switch (CaptureChannel)
02518   {
02519   case HRTIM_CAPTUREUNIT_1:
02520     {
02521       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
02522     }
02523     break;
02524   case HRTIM_CAPTUREUNIT_2:
02525     {
02526       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
02527     }
02528     break;
02529   default:
02530     break;
02531   }
02532
02533   /* Enable the timer counter */
02534   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02535
02536   hhrtim->State = HAL_HRTIM_STATE_READY;
02537
02538   /* Process Unlocked */
02539   __HAL_UNLOCK(hhrtim);
02540
02541   return HAL_OK;
02542 }
02543
02544 /**
02545   * @brief  Disables a simple capture on the designed capture unit
02546   * @param  hhrtim pointer to HAL HRTIM handle
02547   * @param  TimerIdx Timer index
02548   *                   This parameter can be one of the following values:
02549   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02550   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02551   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02552   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02553   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02554   * @param  CaptureChannel Timer output
02555   *                    This parameter can be one of the following values:
02556   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02557   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02558   * @retval HAL status
02559   */
02560 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
02561                                              uint32_t TimerIdx,
02562                                              uint32_t CaptureChannel)
02563 {
02564    /* Check the parameters */
02565   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02566   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02567
02568   /* Process Locked */
02569   __HAL_LOCK(hhrtim);
02570
02571   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02572
02573   /* Set the capture unit trigger */
02574   switch (CaptureChannel)
02575   {
02576   case HRTIM_CAPTUREUNIT_1:
02577     {
02578       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
02579     }
02580     break;
02581   case HRTIM_CAPTUREUNIT_2:
02582     {
02583       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
02584     }
02585     break;
02586   default:
02587     break;
02588   }
02589
02590   /* Disable the timer counter */
02591   if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
02592       (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
02593   {
02594     __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02595   }
02596
02597   hhrtim->State = HAL_HRTIM_STATE_READY;
02598
02599   /* Process Unlocked */
02600   __HAL_UNLOCK(hhrtim);
02601
02602   return HAL_OK;
02603 }
02604
02605 /**
02606   * @brief  Enables a simple capture on the designed capture unit
02607   *         (Capture interrupt is enabled).
02608   * @param  hhrtim pointer to HAL HRTIM handle
02609   * @param  TimerIdx Timer index
02610   *                   This parameter can be one of the following values:
02611   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02612   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02613   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02614   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02615   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02616   * @param  CaptureChannel Timer output
02617   *                    This parameter can be one of the following values:
02618   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02619   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02620   * @retval HAL status
02621   */
02622 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
02623                                                  uint32_t TimerIdx,
02624                                                  uint32_t CaptureChannel)
02625 {
02626    /* Check the parameters */
02627   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02628   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02629
02630   /* Process Locked */
02631   __HAL_LOCK(hhrtim);
02632
02633   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02634
02635   /* Set the capture unit trigger */
02636   switch (CaptureChannel)
02637   {
02638   case HRTIM_CAPTUREUNIT_1:
02639     {
02640       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
02641
02642       /* Enable the capture unit 1 interrupt */
02643       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
02644     }
02645     break;
02646   case HRTIM_CAPTUREUNIT_2:
02647     {
02648       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
02649
02650       /* Enable the capture unit 2 interrupt */
02651       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
02652     }
02653     break;
02654   default:
02655     break;
02656   }
02657
02658   /* Enable the timer counter */
02659   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02660
02661   hhrtim->State = HAL_HRTIM_STATE_READY;
02662
02663   /* Process Unlocked */
02664   __HAL_UNLOCK(hhrtim);
02665
02666   return HAL_OK;
02667 }
02668
02669 /**
02670   * @brief  Disables a simple capture on the designed capture unit
02671   *         (Capture interrupt is disabled).
02672   * @param  hhrtim pointer to HAL HRTIM handle
02673   * @param  TimerIdx Timer index
02674   *                   This parameter can be one of the following values:
02675   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02676   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02677   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02678   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02679   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02680   * @param  CaptureChannel Timer output
02681   *                    This parameter can be one of the following values:
02682   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02683   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02684   * @retval HAL status
02685   */
02686 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
02687                                                 uint32_t TimerIdx,
02688                                                 uint32_t CaptureChannel)
02689 {
02690    /* Check the parameters */
02691   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02692   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02693
02694   /* Process Locked */
02695   __HAL_LOCK(hhrtim);
02696
02697   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02698
02699   /* Set the capture unit trigger */
02700   switch (CaptureChannel)
02701   {
02702   case HRTIM_CAPTUREUNIT_1:
02703     {
02704       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
02705
02706       /* Disable the capture unit 1 interrupt */
02707       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
02708     }
02709     break;
02710   case HRTIM_CAPTUREUNIT_2:
02711     {
02712       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
02713
02714       /* Disable the capture unit 2 interrupt */
02715       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
02716     }
02717     break;
02718   default:
02719     break;
02720   }
02721
02722   /* Disable the timer counter */
02723   if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
02724       (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
02725   {
02726     __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02727   }
02728
02729   hhrtim->State = HAL_HRTIM_STATE_READY;
02730
02731   /* Process Unlocked */
02732   __HAL_UNLOCK(hhrtim);
02733
02734   return HAL_OK;
02735 }
02736
02737 /**
02738   * @brief  Enables a simple capture on the designed capture unit
02739   *         (Capture DMA request is enabled).
02740   * @param  hhrtim pointer to HAL HRTIM handle
02741   * @param  TimerIdx Timer index
02742   *                   This parameter can be one of the following values:
02743   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02744   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02745   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02746   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02747   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02748   * @param  CaptureChannel Timer output
02749   *                    This parameter can be one of the following values:
02750   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02751   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02752   * @param  SrcAddr DMA transfer source address
02753   * @param  DestAddr DMA transfer destination address
02754   * @param  Length The length of data items (data size) to be transferred
02755   *                     from source to destination
02756   * @retval HAL status
02757   */
02758 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
02759                                                   uint32_t TimerIdx,
02760                                                   uint32_t CaptureChannel,
02761                                                   uint32_t SrcAddr,
02762                                                   uint32_t DestAddr,
02763                                                   uint32_t Length)
02764 {
02765   DMA_HandleTypeDef * hdma;
02766
02767    /* Check the parameters */
02768   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02769   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02770
02771   /* Process Locked */
02772   __HAL_LOCK(hhrtim);
02773
02774   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02775
02776   /* Get the timer DMA handler */
02777   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
02778   if (hdma == NULL)
02779   {
02780    hhrtim->State = HAL_HRTIM_STATE_ERROR;
02781
02782    /* Process Unlocked */
02783    __HAL_UNLOCK(hhrtim);
02784
02785    return HAL_ERROR;
02786   }
02787
02788   /* Set the DMA error callback */
02789   hdma->XferErrorCallback = HRTIM_DMAError ;
02790
02791   /* Set the DMA transfer completed callback */
02792   hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
02793
02794   /* Enable the DMA channel */
02795   HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
02796
02797   switch (CaptureChannel)
02798   {
02799   case HRTIM_CAPTUREUNIT_1:
02800     {
02801       /* Set the capture unit trigger */
02802       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
02803
02804       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
02805     }
02806     break;
02807   case HRTIM_CAPTUREUNIT_2:
02808     {
02809       /* Set the capture unit trigger */
02810       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
02811
02812       /* Enable the timer DMA request */
02813       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
02814     }
02815     break;
02816    default:
02817     break;
02818  }
02819
02820   /* Enable the timer counter */
02821   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02822
02823   hhrtim->State = HAL_HRTIM_STATE_READY;
02824
02825   /* Process Unlocked */
02826   __HAL_UNLOCK(hhrtim);
02827
02828   return HAL_OK;
02829 }
02830
02831 /**
02832   * @brief  Disables a simple capture on the designed capture unit
02833   *         (Capture DMA request is disabled).
02834   * @param  hhrtim pointer to HAL HRTIM handle
02835   * @param  TimerIdx Timer index
02836   *                   This parameter can be one of the following values:
02837   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02838   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02839   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02840   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02841   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02842   * @param  CaptureChannel Timer output
02843   *                    This parameter can be one of the following values:
02844   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02845   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02846   * @retval HAL status
02847   */
02848 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
02849                                                  uint32_t TimerIdx,
02850                                                  uint32_t CaptureChannel)
02851 {
02852   DMA_HandleTypeDef * hdma;
02853
02854   /* Check the parameters */
02855   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02856   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02857
02858   /* Process Locked */
02859   __HAL_LOCK(hhrtim);
02860
02861   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02862
02863   /* Get the timer DMA handler */
02864   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
02865   if (hdma == NULL)
02866   {
02867    hhrtim->State = HAL_HRTIM_STATE_ERROR;
02868
02869    /* Process Unlocked */
02870    __HAL_UNLOCK(hhrtim);
02871
02872    return HAL_ERROR;
02873   }
02874
02875   /* Disable the DMA */
02876   HAL_DMA_Abort(hdma);
02877
02878   switch (CaptureChannel)
02879   {
02880   case HRTIM_CAPTUREUNIT_1:
02881     {
02882       /* Reset the capture unit trigger */
02883       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
02884
02885       /* Disable the capture unit 1 DMA request */
02886       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
02887     }
02888     break;
02889   case HRTIM_CAPTUREUNIT_2:
02890     {
02891       /* Reset the capture unit trigger */
02892       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
02893
02894       /* Disable the capture unit 2 DMA request */
02895       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
02896     }
02897     break;
02898   default:
02899     break;
02900   }
02901
02902   /* Disable the timer counter */
02903   if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
02904       (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
02905   {
02906     __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02907   }
02908
02909   hhrtim->State = HAL_HRTIM_STATE_READY;
02910
02911   /* Process Unlocked */
02912   __HAL_UNLOCK(hhrtim);
02913
02914   return HAL_OK;
02915 }
02916
02917 /**
02918   * @}
02919   */
02920
02921 /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
02922  *  @brief    Simple one pulse functions
02923 @verbatim
02924  ===============================================================================
02925               ##### Simple one pulse functions #####
02926  ===============================================================================
02927     [..]  This section provides functions allowing to:
02928       (+) Configure one pulse channel
02929       (+) Start one pulse generation
02930       (+) Stop one pulse generation
02931       (+) Start one pulse generation and enable interrupt
02932       (+) Stop one pulse generation and disable interrupt
02933       -@- When a HRTIM timer operates in simple one pulse mode
02934           the timer counter is started in response to transition detected
02935           on a given external event input to generate a pulse with a
02936           programmable length after a programmable delay.
02937 @endverbatim
02938   * @{
02939   */
02940
02941 /**
02942   * @brief  Configures an output simple one pulse mode
02943   * @param  hhrtim pointer to HAL HRTIM handle
02944   * @param  TimerIdx Timer index
02945   *                   This parameter can be one of the following values:
02946   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02947   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02948   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02949   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02950   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02951   * @param  OnePulseChannel Timer output
02952   *                    This parameter can be one of the following values:
02953   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02954   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02955   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02956   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02957   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02958   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02959   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02960   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02961   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02962   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02963   * @param  pSimpleOnePulseChannelCfg pointer to the simple one pulse output configuration structure
02964   * @note When the timer operates in simple one pulse mode:
02965   *         the timer counter is implicitly started by the reset event,
02966   *         the reset of the timer counter is triggered by the designated external event
02967   *         GPIO input is implicitly used as event source,
02968   *         Output 1 is implicitly controlled by the compare unit 1,
02969   *         Output 2 is implicitly controlled by the compare unit 2.
02970   *       Output Set/Reset crossbar is set as follows:
02971   *         Output 1: SETx1R = CMP1, RSTx1R = PER
02972   *         Output 2: SETx2R = CMP2, RST2R = PER
02973   * @retval HAL status
02974   * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
02975   *       outputs, the reset event related configuration data provided in the
02976   *       second call will override the reset event related configuration data
02977   *       provided in the first call.
02978   */
02979 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
02980                                                        uint32_t TimerIdx,
02981                                                        uint32_t OnePulseChannel,
02982                                                        HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
02983 {
02984   uint32_t CompareUnit = 0xFFFFFFFFU;
02985   HRTIM_CompareCfgTypeDef CompareCfg;
02986   HRTIM_OutputCfgTypeDef OutputCfg;
02987   HRTIM_EventCfgTypeDef EventCfg;
02988
02989   /* Check parameters */
02990   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
02991   assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
02992   assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
02993   assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
02994   assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
02995                                       pSimpleOnePulseChannelCfg->EventPolarity));
02996   assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
02997   assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
02998                                     pSimpleOnePulseChannelCfg->EventFilter));
02999
03000   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03001   {
03002      return HAL_BUSY;
03003   }
03004
03005   /* Process Locked */
03006   __HAL_LOCK(hhrtim);
03007
03008   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03009
03010   /* Configure timer compare unit */
03011   switch (OnePulseChannel)
03012   {
03013   case HRTIM_OUTPUT_TA1:
03014   case HRTIM_OUTPUT_TB1:
03015   case HRTIM_OUTPUT_TC1:
03016   case HRTIM_OUTPUT_TD1:
03017   case HRTIM_OUTPUT_TE1:
03018     {
03019       CompareUnit = HRTIM_COMPAREUNIT_1;
03020     }
03021     break;
03022   case HRTIM_OUTPUT_TA2:
03023   case HRTIM_OUTPUT_TB2:
03024   case HRTIM_OUTPUT_TC2:
03025   case HRTIM_OUTPUT_TD2:
03026   case HRTIM_OUTPUT_TE2:
03027     {
03028       CompareUnit = HRTIM_COMPAREUNIT_2;
03029     }
03030     break;
03031   default:
03032     break;
03033   }
03034
03035   CompareCfg.CompareValue = pSimpleOnePulseChannelCfg->Pulse;
03036   CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
03037   CompareCfg.AutoDelayedTimeout = 0U;
03038
03039   HRTIM_CompareUnitConfig(hhrtim,
03040                           TimerIdx,
03041                           CompareUnit,
03042                           &CompareCfg);
03043
03044   /* Configure timer output */
03045   OutputCfg.Polarity = pSimpleOnePulseChannelCfg->OutputPolarity;
03046   OutputCfg.IdleLevel = pSimpleOnePulseChannelCfg->OutputIdleLevel;
03047   OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
03048   OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
03049   OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
03050   OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
03051
03052   if (CompareUnit == HRTIM_COMPAREUNIT_1)
03053   {
03054     OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
03055   }
03056   else
03057   {
03058     OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
03059   }
03060   OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
03061
03062   HRTIM_OutputConfig(hhrtim,
03063                      TimerIdx,
03064                      OnePulseChannel,
03065                      &OutputCfg);
03066
03067   /* Configure external event channel */
03068   EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
03069   EventCfg.Filter = pSimpleOnePulseChannelCfg->EventFilter;
03070   EventCfg.Polarity = pSimpleOnePulseChannelCfg->EventPolarity;
03071   EventCfg.Sensitivity = pSimpleOnePulseChannelCfg->EventSensitivity;
03072   EventCfg.Source = HRTIM_EVENTSRC_1;
03073
03074   HRTIM_EventConfig(hhrtim,
03075                     pSimpleOnePulseChannelCfg->Event,
03076                     &EventCfg);
03077
03078   /* Configure the timer reset register */
03079   HRTIM_TIM_ResetConfig(hhrtim,
03080                         TimerIdx,
03081                         pSimpleOnePulseChannelCfg->Event);
03082
03083   hhrtim->State = HAL_HRTIM_STATE_READY;
03084
03085   /* Process Unlocked */
03086   __HAL_UNLOCK(hhrtim);
03087
03088   return HAL_OK;
03089 }
03090
03091 /**
03092   * @brief  Enables the simple one pulse signal generation on the designed output
03093   * @param  hhrtim pointer to HAL HRTIM handle
03094   * @param  TimerIdx Timer index
03095   *                   This parameter can be one of the following values:
03096   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03097   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03098   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03099   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03100   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03101   * @param  OnePulseChannel Timer output
03102   *                    This parameter can be one of the following values:
03103   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
03104   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
03105   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
03106   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
03107   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
03108   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
03109   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
03110   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
03111   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
03112   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
03113   * @retval HAL status
03114   */
03115 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
03116                                                 uint32_t TimerIdx,
03117                                                 uint32_t OnePulseChannel)
03118 {
03119    /* Check the parameters */
03120   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
03121
03122   /* Process Locked */
03123   __HAL_LOCK(hhrtim);
03124
03125   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03126
03127   /* Enable the timer output */
03128   hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
03129
03130   /* Enable the timer counter */
03131   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03132
03133   hhrtim->State = HAL_HRTIM_STATE_READY;
03134
03135   /* Process Unlocked */
03136   __HAL_UNLOCK(hhrtim);
03137
03138   return HAL_OK;
03139 }
03140
03141 /**
03142   * @brief  Disables the simple one pulse signal generation on the designed output
03143   * @param  hhrtim pointer to HAL HRTIM handle
03144   * @param  TimerIdx Timer index
03145   *                   This parameter can be one of the following values:
03146   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03147   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03148   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03149   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03150   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03151   * @param  OnePulseChannel Timer output
03152   *                    This parameter can be one of the following values:
03153   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
03154   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
03155   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
03156   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
03157   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
03158   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
03159   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
03160   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
03161   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
03162   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
03163   * @retval HAL status
03164   */
03165 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
03166                                               uint32_t TimerIdx,
03167                                               uint32_t OnePulseChannel)
03168 {
03169    /* Check the parameters */
03170   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
03171
03172   /* Process Locked */
03173   __HAL_LOCK(hhrtim);
03174
03175   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03176
03177   /* Disable the timer output */
03178   hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
03179
03180   /* Disable the timer counter */
03181   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03182
03183   hhrtim->State = HAL_HRTIM_STATE_READY;
03184
03185   /* Process Unlocked */
03186   __HAL_UNLOCK(hhrtim);
03187
03188   return HAL_OK;
03189 }
03190
03191 /**
03192   * @brief  Enables the simple one pulse signal generation on the designed output
03193   *         (The compare interrupt is enabled (pulse start)).
03194   * @param  hhrtim pointer to HAL HRTIM handle
03195   * @param  TimerIdx Timer index
03196   *                   This parameter can be one of the following values:
03197   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03198   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03199   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03200   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03201   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03202   * @param  OnePulseChannel Timer output
03203   *                    This parameter can be one of the following values:
03204   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
03205   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
03206   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
03207   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
03208   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
03209   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
03210   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
03211   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
03212   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
03213   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
03214   * @retval HAL status
03215   */
03216 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
03217                                                   uint32_t TimerIdx,
03218                                                   uint32_t OnePulseChannel)
03219 {
03220    /* Check the parameters */
03221   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
03222
03223   /* Process Locked */
03224   __HAL_LOCK(hhrtim);
03225
03226   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03227
03228   /* Enable the timer output */
03229   hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
03230
03231   /* Enable the timer interrupt (depends on the OnePulse output) */
03232   switch (OnePulseChannel)
03233   {
03234   case HRTIM_OUTPUT_TA1:
03235   case HRTIM_OUTPUT_TB1:
03236   case HRTIM_OUTPUT_TC1:
03237   case HRTIM_OUTPUT_TD1:
03238   case HRTIM_OUTPUT_TE1:
03239     {
03240       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
03241     }
03242     break;
03243   case HRTIM_OUTPUT_TA2:
03244   case HRTIM_OUTPUT_TB2:
03245   case HRTIM_OUTPUT_TC2:
03246   case HRTIM_OUTPUT_TD2:
03247   case HRTIM_OUTPUT_TE2:
03248     {
03249       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
03250     }
03251     break;
03252   default:
03253     break;
03254   }
03255
03256   /* Enable the timer counter */
03257   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03258
03259   hhrtim->State = HAL_HRTIM_STATE_READY;
03260
03261   /* Process Unlocked */
03262   __HAL_UNLOCK(hhrtim);
03263
03264   return HAL_OK;
03265 }
03266
03267 /**
03268   * @brief  Disables the simple one pulse signal generation on the designed output
03269   *         (The compare interrupt is disabled).
03270   * @param  hhrtim pointer to HAL HRTIM handle
03271   * @param  TimerIdx Timer index
03272   *                   This parameter can be one of the following values:
03273   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03274   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03275   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03276   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03277   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03278   * @param  OnePulseChannel Timer output
03279   *                    This parameter can be one of the following values:
03280   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
03281   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
03282   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
03283   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
03284   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
03285   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
03286   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
03287   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
03288   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
03289   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
03290   * @retval HAL status
03291   */
03292 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
03293                                                  uint32_t TimerIdx,
03294                                                  uint32_t OnePulseChannel)
03295 {
03296      /* Check the parameters */
03297   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
03298
03299   /* Process Locked */
03300   __HAL_LOCK(hhrtim);
03301
03302   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03303
03304   /* Disable the timer output */
03305   hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
03306
03307   /* Disable the timer interrupt (depends on the OnePulse output) */
03308   switch (OnePulseChannel)
03309   {
03310   case HRTIM_OUTPUT_TA1:
03311   case HRTIM_OUTPUT_TB1:
03312   case HRTIM_OUTPUT_TC1:
03313   case HRTIM_OUTPUT_TD1:
03314   case HRTIM_OUTPUT_TE1:
03315     {
03316       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
03317     }
03318     break;
03319   case HRTIM_OUTPUT_TA2:
03320   case HRTIM_OUTPUT_TB2:
03321   case HRTIM_OUTPUT_TC2:
03322   case HRTIM_OUTPUT_TD2:
03323   case HRTIM_OUTPUT_TE2:
03324     {
03325       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
03326     }
03327     break;
03328   default:
03329     break;
03330   }
03331
03332   /* Disable the timer counter */
03333   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03334
03335   hhrtim->State = HAL_HRTIM_STATE_READY;
03336
03337   /* Process Unlocked */
03338   __HAL_UNLOCK(hhrtim);
03339
03340   return HAL_OK;
03341 }
03342
03343 /**
03344   * @}
03345   */
03346
03347 /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
03348  *  @brief    HRTIM configuration functions
03349 @verbatim
03350  ===============================================================================
03351               ##### HRTIM configuration functions #####
03352  ===============================================================================
03353     [..]  This section provides functions allowing to configure the HRTIM
03354               resources shared by all the HRTIM timers operating in waveform mode:
03355       (+) Configure the burst mode controller
03356       (+) Configure an external event conditionning
03357       (+) Configure the external events sampling clock
03358       (+) Configure a fault conditionning
03359       (+) Enable or disable fault inputs
03360       (+) Configure the faults sampling clock
03361       (+) Configure an ADC trigger
03362
03363 @endverbatim
03364   * @{
03365   */
03366
03367 /**
03368   * @brief  Configures the burst mode feature of the HRTIM
03369   * @param  hhrtim pointer to HAL HRTIM handle
03370   * @param  pBurstModeCfg pointer to the burst mode configuration structure
03371   * @retval HAL status
03372   * @note This function must be called before starting the burst mode
03373   *       controller
03374   */
03375 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
03376                                             HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
03377 {
03378   uint32_t hrtim_bmcr;
03379
03380   /* Check parameters */
03381   assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
03382   assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
03383   assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
03384   assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
03385   assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
03386
03387   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03388   {
03389      return HAL_BUSY;
03390   }
03391
03392   /* Process Locked */
03393   __HAL_LOCK(hhrtim);
03394
03395   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03396
03397   hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
03398
03399   /* Set the burst mode operating mode */
03400   hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
03401   hrtim_bmcr |= pBurstModeCfg->Mode;
03402
03403   /* Set the burst mode clock source */
03404   hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
03405   hrtim_bmcr |= pBurstModeCfg->ClockSource;
03406
03407   /* Set the burst mode prescaler */
03408   hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
03409   hrtim_bmcr |= pBurstModeCfg->Prescaler;
03410
03411   /* Enable/disable burst mode registers preload */
03412   hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
03413   hrtim_bmcr |= pBurstModeCfg->PreloadEnable;
03414
03415   /* Set the burst mode trigger */
03416   hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
03417
03418   /* Set the burst mode compare value */
03419   hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
03420
03421   /* Set the burst mode period */
03422   hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
03423
03424   /* Update the HRTIM registers */
03425   hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
03426
03427   hhrtim->State = HAL_HRTIM_STATE_READY;
03428
03429   /* Process Unlocked */
03430   __HAL_UNLOCK(hhrtim);
03431
03432   return HAL_OK;
03433 }
03434
03435 /**
03436   * @brief  Configures the conditioning of an external event
03437   * @param  hhrtim pointer to HAL HRTIM handle
03438   * @param  Event external event to configure
03439   *                    This parameter can be one of the following values:
03440   *                    @arg HRTIM_EVENT_1: External event 1
03441   *                    @arg HRTIM_EVENT_2: External event 2
03442   *                    @arg HRTIM_EVENT_3: External event 3
03443   *                    @arg HRTIM_EVENT_4: External event 4
03444   *                    @arg HRTIM_EVENT_5: External event 5
03445   *                    @arg HRTIM_EVENT_6: External event 6
03446   *                    @arg HRTIM_EVENT_7: External event 7
03447   *                    @arg HRTIM_EVENT_8: External event 8
03448   *                    @arg HRTIM_EVENT_9: External event 9
03449   *                    @arg HRTIM_EVENT_10: External event 10
03450   * @param  pEventCfg pointer to the event conditioning configuration structure
03451   * @note This function must be called before starting the timer
03452   * @retval HAL status
03453   */
03454 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
03455                                         uint32_t Event,
03456                                         HRTIM_EventCfgTypeDef* pEventCfg)
03457 {
03458   /* Check parameters */
03459   assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
03460   assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
03461   assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
03462   assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
03463   assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
03464
03465   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03466   {
03467      return HAL_BUSY;
03468   }
03469
03470   /* Process Locked */
03471   __HAL_LOCK(hhrtim);
03472
03473   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03474
03475   /* Configure the event channel */
03476   HRTIM_EventConfig(hhrtim, Event, pEventCfg);
03477
03478   hhrtim->State = HAL_HRTIM_STATE_READY;
03479
03480   /* Process Unlocked */
03481   __HAL_UNLOCK(hhrtim);
03482
03483   return HAL_OK;
03484 }
03485
03486 /**
03487   * @brief  Configures the external event conditioning block prescaler
03488   * @param  hhrtim pointer to HAL HRTIM handle
03489   * @param  Prescaler Prescaler value
03490   *                    This parameter can be one of the following values:
03491   *                    @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
03492   *                    @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
03493   *                    @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
03494   *                    @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
03495   * @note This function must be called before starting the timer
03496   * @retval HAL status
03497   */
03498 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
03499                                                  uint32_t Prescaler)
03500 {
03501   uint32_t hrtim_eecr3;
03502
03503   /* Check parameters */
03504   assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
03505
03506   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03507   {
03508      return HAL_BUSY;
03509   }
03510
03511   /* Process Locked */
03512   __HAL_LOCK(hhrtim);
03513
03514   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03515
03516   /* Set the external event prescaler */
03517   hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
03518   hrtim_eecr3 &= ~(HRTIM_EECR3_EEVSD);
03519   hrtim_eecr3 |= Prescaler;
03520
03521   /* Update the HRTIM registers */
03522   hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
03523
03524   hhrtim->State = HAL_HRTIM_STATE_READY;
03525
03526   /* Process Unlocked */
03527   __HAL_UNLOCK(hhrtim);
03528
03529   return HAL_OK;
03530 }
03531
03532 /**
03533   * @brief  Configures the conditioning of fault input
03534   * @param  hhrtim pointer to HAL HRTIM handle
03535   * @param  Fault fault input to configure
03536   *                    This parameter can be one of the following values:
03537   *                    @arg HRTIM_FAULT_1: Fault input 1
03538   *                    @arg HRTIM_FAULT_2: Fault input 2
03539   *                    @arg HRTIM_FAULT_3: Fault input 3
03540   *                    @arg HRTIM_FAULT_4: Fault input 4
03541   *                    @arg HRTIM_FAULT_5: Fault input 5
03542   * @param  pFaultCfg pointer to the fault conditioning configuration structure
03543   * @note This function must be called before starting the timer and before
03544   *       enabling faults inputs
03545   * @retval HAL status
03546   */
03547 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
03548                                         uint32_t Fault,
03549                                         HRTIM_FaultCfgTypeDef* pFaultCfg)
03550 {
03551   uint32_t hrtim_fltinr1;
03552   uint32_t hrtim_fltinr2;
03553
03554   /* Check parameters */
03555   assert_param(IS_HRTIM_FAULT(Fault));
03556   assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
03557   assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
03558   assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
03559   assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
03560
03561   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03562   {
03563      return HAL_BUSY;
03564   }
03565
03566   /* Process Locked */
03567   __HAL_LOCK(hhrtim);
03568
03569   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03570
03571   /* Configure fault channel */
03572   hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
03573   hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
03574
03575   switch (Fault)
03576   {
03577   case HRTIM_FAULT_1:
03578     {
03579       hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
03580       hrtim_fltinr1 |= pFaultCfg->Polarity;
03581       hrtim_fltinr1 |= pFaultCfg->Source;
03582       hrtim_fltinr1 |= pFaultCfg->Filter;
03583       hrtim_fltinr1 |= pFaultCfg->Lock;
03584     }
03585     break;
03586   case HRTIM_FAULT_2:
03587     {
03588       hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
03589       hrtim_fltinr1 |= (pFaultCfg->Polarity << 8U);
03590       hrtim_fltinr1 |= (pFaultCfg->Source << 8U);
03591       hrtim_fltinr1 |= (pFaultCfg->Filter << 8U);
03592       hrtim_fltinr1 |= (pFaultCfg->Lock << 8U);
03593     }
03594     break;
03595   case HRTIM_FAULT_3:
03596     {
03597       hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
03598       hrtim_fltinr1 |= (pFaultCfg->Polarity << 16U);
03599       hrtim_fltinr1 |= (pFaultCfg->Source << 16U);
03600       hrtim_fltinr1 |= (pFaultCfg->Filter << 16U);
03601       hrtim_fltinr1 |= (pFaultCfg->Lock << 16U);
03602     }
03603     break;
03604   case HRTIM_FAULT_4:
03605     {
03606       hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
03607       hrtim_fltinr1 |= (pFaultCfg->Polarity << 24U);
03608       hrtim_fltinr1 |= (pFaultCfg->Source << 24U);
03609       hrtim_fltinr1 |= (pFaultCfg->Filter << 24U);
03610       hrtim_fltinr1 |= (pFaultCfg->Lock << 24U);
03611     }
03612     break;
03613   case HRTIM_FAULT_5:
03614     {
03615       hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
03616       hrtim_fltinr2 |= pFaultCfg->Polarity;
03617       hrtim_fltinr2 |= pFaultCfg->Source;
03618       hrtim_fltinr2 |= pFaultCfg->Filter;
03619       hrtim_fltinr2 |= pFaultCfg->Lock;
03620     }
03621     break;
03622   default:
03623     break;
03624   }
03625
03626   /* Update the HRTIM registers */
03627   hhrtim->Instance->sCommonRegs.FLTINR1 = hrtim_fltinr1;
03628   hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
03629
03630   hhrtim->State = HAL_HRTIM_STATE_READY;
03631
03632   /* Process Unlocked */
03633   __HAL_UNLOCK(hhrtim);
03634
03635   return HAL_OK;
03636 }
03637
03638 /**
03639   * @brief  Configures the fault conditioning block prescaler
03640   * @param  hhrtim pointer to HAL HRTIM handle
03641   * @param  Prescaler Prescaler value
03642   *                    This parameter can be one of the following values:
03643   *                    @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
03644   *                    @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
03645   *                    @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
03646   *                    @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
03647   * @retval HAL status
03648   * @note This function must be called before starting the timer and before
03649   *       enabling faults inputs
03650   */
03651 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
03652                                                  uint32_t Prescaler)
03653 {
03654   uint32_t hrtim_fltinr2;
03655
03656   /* Check parameters */
03657   assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
03658
03659   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03660   {
03661      return HAL_BUSY;
03662   }
03663
03664   /* Process Locked */
03665   __HAL_LOCK(hhrtim);
03666
03667   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03668
03669   /* Set the external event prescaler */
03670   hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
03671   hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLTSD);
03672   hrtim_fltinr2 |= Prescaler;
03673
03674   /* Update the HRTIM registers */
03675   hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
03676
03677   hhrtim->State = HAL_HRTIM_STATE_READY;
03678
03679   /* Process Unlocked */
03680   __HAL_UNLOCK(hhrtim);
03681
03682   return HAL_OK;
03683 }
03684
03685 /**
03686   * @brief  Enables or disables the HRTIMx Fault mode.
03687   * @param  hhrtim pointer to HAL HRTIM handle
03688   * @param  Faults fault input(s) to enable or disable
03689   *                   This parameter can be any combination of the following values:
03690   *                    @arg HRTIM_FAULT_1: Fault input 1
03691   *                    @arg HRTIM_FAULT_2: Fault input 2
03692   *                    @arg HRTIM_FAULT_3: Fault input 3
03693   *                    @arg HRTIM_FAULT_4: Fault input 4
03694   *                    @arg HRTIM_FAULT_5: Fault input 5
03695   * @param  Enable Fault(s) enabling
03696   *                    This parameter can be one of the following values:
03697   *                    @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
03698   *                    @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
03699   * @retval None
03700   */
03701 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
03702                         uint32_t Faults,
03703                         uint32_t Enable)
03704 {
03705   uint32_t hrtim_fltinr1;
03706   uint32_t hrtim_fltinr2;
03707
03708   /* Check parameters */
03709   assert_param(IS_HRTIM_FAULT(Faults));
03710   assert_param(IS_HRTIM_FAULTMODECTL(Enable));
03711
03712   /* Configure fault channel */
03713   hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
03714   hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
03715
03716   if ((Faults & HRTIM_FAULT_1) != RESET)
03717   {
03718     hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT1E;
03719     hrtim_fltinr1 |= Enable;
03720   }
03721   if ((Faults & HRTIM_FAULT_2) != RESET)
03722   {
03723     hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT2E;
03724     hrtim_fltinr1 |= (Enable << 8U);
03725   }
03726   if ((Faults & HRTIM_FAULT_3) != RESET)
03727   {
03728     hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT3E;
03729     hrtim_fltinr1 |= (Enable << 16U);
03730   }
03731   if ((Faults & HRTIM_FAULT_4) != RESET)
03732   {
03733     hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT4E;
03734     hrtim_fltinr1 |= (Enable << 24U);
03735   }
03736   if ((Faults & HRTIM_FAULT_5) != RESET)
03737   {
03738     hrtim_fltinr2 &= ~HRTIM_FLTINR2_FLT5E;
03739     hrtim_fltinr2 |= Enable;
03740   }
03741
03742   /* Update the HRTIMx registers */
03743   hhrtim->Instance->sCommonRegs.FLTINR1 = hrtim_fltinr1;
03744   hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
03745 }
03746
03747 /**
03748   * @brief  Configures both the ADC trigger register update source and the ADC
03749   *         trigger source.
03750   * @param  hhrtim pointer to HAL HRTIM handle
03751   * @param  ADCTrigger ADC trigger to configure
03752   *                    This parameter can be one of the following values:
03753   *                    @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
03754   *                    @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
03755   *                    @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
03756   *                    @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
03757   * @param  pADCTriggerCfg pointer to the ADC trigger configuration structure
03758   * @retval HAL status
03759   * @note This function must be called before starting the timer
03760   */
03761 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
03762                                              uint32_t ADCTrigger,
03763                                              HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
03764 {
03765   uint32_t hrtim_cr1;
03766
03767   /* Check parameters */
03768   assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
03769   assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
03770
03771   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03772   {
03773      return HAL_BUSY;
03774   }
03775
03776   /* Process Locked */
03777   __HAL_LOCK(hhrtim);
03778
03779   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03780
03781   /* Set the ADC trigger update source */
03782   hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
03783
03784   switch (ADCTrigger)
03785   {
03786   case HRTIM_ADCTRIGGER_1:
03787     {
03788       hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
03789       hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
03790
03791       /* Set the ADC trigger 1 source */
03792       hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
03793     }
03794     break;
03795   case HRTIM_ADCTRIGGER_2:
03796     {
03797       hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
03798       hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC);
03799
03800       /* Set the ADC trigger 2 source */
03801       hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
03802     }
03803     break;
03804   case HRTIM_ADCTRIGGER_3:
03805     {
03806       hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
03807       hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC);
03808
03809       /* Set the ADC trigger 3 source */
03810       hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
03811     }
03812     break;
03813   case HRTIM_ADCTRIGGER_4:
03814     {
03815       hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
03816       hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC);
03817
03818       /* Set the ADC trigger 4 source */
03819       hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
03820     }
03821     break;
03822   default:
03823     break;
03824   }
03825
03826   /* Update the HRTIM registers */
03827   hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
03828
03829   hhrtim->State = HAL_HRTIM_STATE_READY;
03830
03831   /* Process Unlocked */
03832   __HAL_UNLOCK(hhrtim);
03833
03834   return HAL_OK;
03835 }
03836
03837 /**
03838   * @}
03839   */
03840
03841 /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
03842  *  @brief    HRTIM timer configuration and control functions
03843 @verbatim
03844  ===============================================================================
03845               ##### HRTIM timer configuration and control functions #####
03846  ===============================================================================
03847     [..]  This section provides functions used to configure and control a
03848               HRTIM timer operating in waveform mode:
03849       (+) Configure HRTIM timer general behavior
03850       (+) Configure HRTIM timer event filtering
03851       (+) Configure HRTIM timer deadtime insertion
03852       (+) Configure HRTIM timer chopper mode
03853       (+) Configure HRTIM timer burst DMA
03854       (+) Configure HRTIM timer compare unit
03855       (+) Configure HRTIM timer capture unit
03856       (+) Configure HRTIM timer output
03857       (+) Set HRTIM timer output level
03858       (+) Enable HRTIM timer output
03859       (+) Disable HRTIM timer output
03860       (+) Start HRTIM timer
03861       (+) Stop HRTIM timer
03862       (+) Start HRTIM timer and enable interrupt
03863       (+) Stop HRTIM timer and disable interrupt
03864       (+) Start HRTIM timer and enable DMA transfer
03865       (+) Stop HRTIM timer and disable DMA transfer
03866       (+) Enable or disable the burst mode controller
03867       (+) Start the burst mode controller (by software)
03868       (+) Trigger a Capture (by software)
03869       (+) Update the HRTIM timer preloadable registers (by software)
03870       (+) Reset the HRTIM timer counter (by software)
03871       (+) Start a burst DMA transfer
03872       (+) Enable timer register update
03873       (+) Disable timer register update
03874
03875 @endverbatim
03876   * @{
03877   */
03878
03879 /**
03880   * @brief  Configures the general behavior of a timer operating in waveform mode
03881   * @param  hhrtim pointer to HAL HRTIM handle
03882   * @param  TimerIdx Timer index
03883   *                   This parameter can be one of the following values:
03884   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
03885   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03886   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03887   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03888   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03889   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03890   * @param  pTimerCfg pointer to the timer configuration structure
03891   * @note When the timer operates in waveform mode, all the features supported by
03892   *       the HRTIM are available without any limitation.
03893   * @retval HAL status
03894   * @note This function must be called before starting the timer
03895   */
03896 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
03897                                                 uint32_t TimerIdx,
03898                                                 HRTIM_TimerCfgTypeDef * pTimerCfg)
03899 {
03900   /* Check parameters */
03901   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
03902
03903   /* Relevant for all HRTIM timers, including the master */
03904   assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
03905   assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
03906   assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
03907   assert_param(IS_HHRTIM_DACSYNC(pTimerCfg->DACSynchro));
03908   assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
03909   assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
03910   assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
03911
03912   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03913   {
03914      return HAL_BUSY;
03915   }
03916
03917   /* Process Locked */
03918   __HAL_LOCK(hhrtim);
03919
03920   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03921
03922   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
03923   {
03924     /* Check parameters */
03925     assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
03926     assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
03927     assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
03928
03929     /* Configure master timer */
03930     HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
03931   }
03932   else
03933   {
03934     /* Check parameters */
03935     assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
03936     assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
03937     assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
03938     assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
03939     assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
03940     assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
03941     assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
03942                                                pTimerCfg->DeadTimeInsertion));
03943     assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
03944                                                pTimerCfg->DelayedProtectionMode));
03945     assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
03946     assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
03947     assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
03948
03949     /* Configure timing unit */
03950     HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
03951   }
03952
03953   /* Update timer parameters */
03954   hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
03955   hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
03956   hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
03957   hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
03958   hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
03959
03960   /* Force a software update */
03961   HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
03962
03963   hhrtim->State = HAL_HRTIM_STATE_READY;
03964
03965   /* Process Unlocked */
03966   __HAL_UNLOCK(hhrtim);
03967
03968   return HAL_OK;
03969 }
03970
03971 /**
03972   * @brief  Configures the event filtering capabilities of a timer (blanking, windowing)
03973   * @param  hhrtim pointer to HAL HRTIM handle
03974   * @param  TimerIdx Timer index
03975   *                   This parameter can be one of the following values:
03976   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03977   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03978   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03979   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03980   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03981   * @param  Event external event for which timer event filtering must be configured
03982   *                    This parameter can be one of the following values:
03983   *                    @arg HRTIM_EVENT_NONE: Reset timer event filtering configuration
03984   *                    @arg HRTIM_EVENT_1: External event 1
03985   *                    @arg HRTIM_EVENT_2: External event 2
03986   *                    @arg HRTIM_EVENT_3: External event 3
03987   *                    @arg HRTIM_EVENT_4: External event 4
03988   *                    @arg HRTIM_EVENT_5: External event 5
03989   *                    @arg HRTIM_EVENT_6: External event 6
03990   *                    @arg HRTIM_EVENT_7: External event 7
03991   *                    @arg HRTIM_EVENT_8: External event 8
03992   *                    @arg HRTIM_EVENT_9: External event 9
03993   *                    @arg HRTIM_EVENT_10: External event 10
03994   * @param  pTimerEventFilteringCfg pointer to the timer event filtering configuration structure
03995   * @note This function must be called before starting the timer
03996   * @retval HAL status
03997   */
03998 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
03999                                                       uint32_t TimerIdx,
04000                                                       uint32_t Event,
04001                                                       HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
04002 {
04003   uint32_t hrtim_eefr;
04004
04005   /* Check parameters */
04006   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
04007   assert_param(IS_HRTIM_EVENT(Event));
04008   assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
04009   assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
04010
04011   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04012   {
04013      return HAL_BUSY;
04014   }
04015
04016   /* Process Locked */
04017   __HAL_LOCK(hhrtim);
04018
04019   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04020
04021   /* Configure timer event filtering capabilities */
04022   switch (Event)
04023   {
04024   case HRTIM_EVENT_NONE:
04025     {
04026       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = 0U;
04027       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = 0U;
04028     }
04029     break;
04030   case HRTIM_EVENT_1:
04031     {
04032       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
04033       hrtim_eefr &= ~(HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH);
04034       hrtim_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
04035       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
04036     }
04037     break;
04038   case HRTIM_EVENT_2:
04039     {
04040       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
04041       hrtim_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH);
04042       hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U);
04043       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
04044     }
04045     break;
04046   case HRTIM_EVENT_3:
04047     {
04048       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
04049       hrtim_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH);
04050       hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U);
04051       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
04052     }
04053     break;
04054   case HRTIM_EVENT_4:
04055     {
04056       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
04057       hrtim_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH);
04058       hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U);
04059       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
04060     }
04061     break;
04062   case HRTIM_EVENT_5:
04063     {
04064       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
04065       hrtim_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH);
04066       hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U);
04067       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
04068     }
04069     break;
04070   case HRTIM_EVENT_6:
04071     {
04072       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
04073       hrtim_eefr &= ~(HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH);
04074       hrtim_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
04075       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
04076     }
04077     break;
04078   case HRTIM_EVENT_7:
04079     {
04080       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
04081       hrtim_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH);
04082       hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U);
04083       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
04084     }
04085     break;
04086   case HRTIM_EVENT_8:
04087     {
04088       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
04089       hrtim_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH);
04090       hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U);
04091       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
04092     }
04093     break;
04094   case HRTIM_EVENT_9:
04095     {
04096       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
04097       hrtim_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH);
04098       hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U);
04099       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
04100     }
04101     break;
04102   case HRTIM_EVENT_10:
04103     {
04104       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
04105       hrtim_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH);
04106       hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U);
04107       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
04108     }
04109     break;
04110   default:
04111     break;
04112   }
04113
04114   hhrtim->State = HAL_HRTIM_STATE_READY;
04115
04116   /* Process Unlocked */
04117   __HAL_UNLOCK(hhrtim);
04118
04119   return HAL_OK;
04120 }
04121
04122 /**
04123   * @brief  Configures the deadtime insertion feature for a timer
04124   * @param  hhrtim pointer to HAL HRTIM handle
04125   * @param  TimerIdx Timer index
04126   *                   This parameter can be one of the following values:
04127   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04128   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04129   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04130   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04131   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04132   * @param  pDeadTimeCfg pointer to the deadtime insertion configuration structure
04133   * @retval HAL status
04134   * @note This function must be called before starting the timer
04135   */
04136 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
04137                                            uint32_t TimerIdx,
04138                                            HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
04139 {
04140   uint32_t hrtim_dtr;
04141
04142   /* Check parameters */
04143   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
04144   assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
04145   assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
04146   assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
04147   assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
04148   assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
04149   assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
04150   assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
04151
04152   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04153   {
04154      return HAL_BUSY;
04155   }
04156
04157   /* Process Locked */
04158   __HAL_LOCK(hhrtim);
04159
04160   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04161
04162   hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
04163
04164   /* Clear timer deadtime configuration */
04165   hrtim_dtr &= ~(HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
04166                  HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
04167                  HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK);
04168
04169   /* Set timer deadtime configuration */
04170   hrtim_dtr |= pDeadTimeCfg->Prescaler;
04171   hrtim_dtr |= pDeadTimeCfg->RisingValue;
04172   hrtim_dtr |= pDeadTimeCfg->RisingSign;
04173   hrtim_dtr |= pDeadTimeCfg->RisingSignLock;
04174   hrtim_dtr |= pDeadTimeCfg->RisingLock;
04175   hrtim_dtr |= (pDeadTimeCfg->FallingValue << 16U);
04176   hrtim_dtr |= pDeadTimeCfg->FallingSign;
04177   hrtim_dtr |= pDeadTimeCfg->FallingSignLock;
04178   hrtim_dtr |= pDeadTimeCfg->FallingLock;
04179
04180   /* Update the HRTIM registers */
04181   hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR = hrtim_dtr;
04182
04183   hhrtim->State = HAL_HRTIM_STATE_READY;
04184
04185   /* Process Unlocked */
04186   __HAL_UNLOCK(hhrtim);
04187
04188   return HAL_OK;
04189 }
04190
04191 /**
04192   * @brief  Configures the chopper mode feature for a timer
04193   * @param  hhrtim pointer to HAL HRTIM handle
04194   * @param  TimerIdx Timer index
04195   *                   This parameter can be one of the following values:
04196   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04197   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04198   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04199   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04200   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04201   * @param  pChopperModeCfg pointer to the chopper mode configuration structure
04202   * @retval HAL status
04203   * @note This function must be called before configuring the timer output(s)
04204   */
04205 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
04206                                               uint32_t TimerIdx,
04207                                               HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
04208 {
04209   uint32_t hrtim_chpr;
04210
04211   /* Check parameters */
04212   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
04213   assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
04214   assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
04215   assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
04216
04217   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04218   {
04219      return HAL_BUSY;
04220   }
04221
04222   /* Process Locked */
04223   __HAL_LOCK(hhrtim);
04224
04225   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04226
04227   hrtim_chpr = hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR;
04228
04229   /* Clear timer chopper mode configuration */
04230   hrtim_chpr &= ~(HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW);
04231
04232   /* Set timer choppe mode configuration */
04233   hrtim_chpr |= pChopperModeCfg->CarrierFreq;
04234   hrtim_chpr |= (pChopperModeCfg->DutyCycle);
04235   hrtim_chpr |= (pChopperModeCfg->StartPulse);
04236
04237   /* Update the HRTIM registers */
04238   hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR = hrtim_chpr;
04239
04240   hhrtim->State = HAL_HRTIM_STATE_READY;
04241
04242   /* Process Unlocked */
04243   __HAL_UNLOCK(hhrtim);
04244
04245   return HAL_OK;
04246 }
04247
04248 /**
04249   * @brief  Configures the burst DMA controller for a timer
04250   * @param  hhrtim pointer to HAL HRTIM handle
04251   * @param  TimerIdx Timer index
04252   *                  This parameter can be one of the following values:
04253   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
04254   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04255   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04256   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04257   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04258   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04259   * @param  RegistersToUpdate registers to be written by DMA
04260   *                    This parameter can be any combination of the following values:
04261   *                    @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
04262   *                    @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
04263   *                    @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
04264   *                    @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
04265   *                    @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
04266   *                    @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
04267   *                    @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
04268   *                    @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
04269   *                    @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
04270   *                    @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
04271   *                    @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
04272   *                    @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
04273   *                    @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
04274   *                    @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
04275   *                    @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
04276   *                    @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
04277   *                    @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
04278   *                    @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
04279   *                    @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
04280   *                    @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
04281   *                    @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
04282   * @retval HAL status
04283   * @note This function must be called before starting the timer
04284   */
04285 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
04286                                            uint32_t TimerIdx,
04287                                            uint32_t RegistersToUpdate)
04288 {
04289   /* Check parameters */
04290   assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
04291
04292   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04293   {
04294      return HAL_BUSY;
04295   }
04296
04297   /* Process Locked */
04298   __HAL_LOCK(hhrtim);
04299
04300   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04301
04302   /* Set the burst DMA timer update register */
04303   switch (TimerIdx)
04304   {
04305   case HRTIM_TIMERINDEX_TIMER_A:
04306     {
04307       hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
04308     }
04309     break;
04310   case HRTIM_TIMERINDEX_TIMER_B:
04311     {
04312       hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
04313     }
04314     break;
04315   case HRTIM_TIMERINDEX_TIMER_C:
04316     {
04317       hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
04318     }
04319     break;
04320   case HRTIM_TIMERINDEX_TIMER_D:
04321     {
04322       hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
04323     }
04324     break;
04325   case HRTIM_TIMERINDEX_TIMER_E:
04326     {
04327       hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
04328     }
04329     break;
04330   case HRTIM_TIMERINDEX_MASTER:
04331     {
04332       hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
04333     }
04334     break;
04335   default:
04336     break;
04337   }
04338
04339   hhrtim->State = HAL_HRTIM_STATE_READY;
04340
04341   /* Process Unlocked */
04342   __HAL_UNLOCK(hhrtim);
04343
04344   return HAL_OK;
04345 }
04346
04347 /**
04348   * @brief  Configures the compare unit of a timer operating in waveform mode
04349   * @param  hhrtim pointer to HAL HRTIM handle
04350   * @param  TimerIdx Timer index
04351   *                   This parameter can be one of the following values:
04352   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
04353   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04354   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04355   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04356   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04357   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04358   * @param  CompareUnit Compare unit to configure
04359   *                    This parameter can be one of the following values:
04360   *                    @arg HRTIM_COMPAREUNIT_1: Compare unit 1
04361   *                    @arg HRTIM_COMPAREUNIT_2: Compare unit 2
04362   *                    @arg HRTIM_COMPAREUNIT_3: Compare unit 3
04363   *                    @arg HRTIM_COMPAREUNIT_4: Compare unit 4
04364   * @param  pCompareCfg pointer to the compare unit configuration structure
04365   * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
04366   *       application has to configure separately the capture unit. Capture unit
04367   *       to configure in that case depends on the compare unit auto delayed mode
04368   *       is applied to (see below):
04369   *         Auto delayed on output compare 2: capture unit 1 must be configured
04370   *         Auto delayed on output compare 4: capture unit 2 must be configured
04371   * @retval HAL status
04372   * @note This function must be called before starting the timer
04373   */
04374 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
04375                                                   uint32_t TimerIdx,
04376                                                   uint32_t CompareUnit,
04377                                                   HRTIM_CompareCfgTypeDef* pCompareCfg)
04378 {
04379   /* Check parameters */
04380   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
04381
04382   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04383   {
04384      return HAL_BUSY;
04385   }
04386
04387   /* Process Locked */
04388   __HAL_LOCK(hhrtim);
04389
04390   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04391
04392   /* Configure the compare unit */
04393   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
04394   {
04395     switch (CompareUnit)
04396     {
04397       case HRTIM_COMPAREUNIT_1:
04398         {
04399         hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
04400         }
04401         break;
04402       case HRTIM_COMPAREUNIT_2:
04403         {
04404         hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
04405         }
04406         break;
04407       case HRTIM_COMPAREUNIT_3:
04408         {
04409         hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
04410         }
04411         break;
04412       case HRTIM_COMPAREUNIT_4:
04413         {
04414         hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
04415         }
04416         break;
04417     default:
04418       break;
04419     }
04420   }
04421   else
04422   {
04423     switch (CompareUnit)
04424     {
04425     case HRTIM_COMPAREUNIT_1:
04426       {
04427         /* Set the compare value */
04428         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
04429       }
04430       break;
04431     case HRTIM_COMPAREUNIT_2:
04432       {
04433         /* Check parameters */
04434         assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
04435
04436         /* Set the compare value */
04437         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
04438
04439         if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
04440         {
04441           /* Configure auto-delayed mode */
04442           /* DELCMP2 bitfield must be reset when reprogrammed from one value */
04443           /* to the other to reinitialize properly the auto-delayed mechanism */
04444           hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
04445           hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
04446
04447           /* Set the compare value for timeout compare unit (if any) */
04448           if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
04449           {
04450             hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
04451           }
04452           else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
04453           {
04454             hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
04455           }
04456         }
04457       }
04458       break;
04459     case HRTIM_COMPAREUNIT_3:
04460       {
04461         /* Set the compare value */
04462         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
04463       }
04464       break;
04465     case HRTIM_COMPAREUNIT_4:
04466       {
04467         /* Check parameters */
04468         assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
04469
04470         /* Set the compare value */
04471         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
04472
04473         if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
04474         {
04475           /* Configure auto-delayed mode */
04476           /* DELCMP4 bitfield must be reset when reprogrammed from one value */
04477           /* to the other to reinitialize properly the auto-delayed mechanism */
04478           hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
04479           hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
04480
04481           /* Set the compare value for timeout compare unit (if any) */
04482           if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
04483           {
04484             hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
04485           }
04486           else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
04487           {
04488             hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
04489           }
04490         }
04491       }
04492       break;
04493     default:
04494       break;
04495     }
04496   }
04497   hhrtim->State = HAL_HRTIM_STATE_READY;
04498
04499   /* Process Unlocked */
04500   __HAL_UNLOCK(hhrtim);
04501
04502   return HAL_OK;
04503 }
04504
04505 /**
04506   * @brief  Configures the capture unit of a timer operating in waveform mode
04507   * @param  hhrtim pointer to HAL HRTIM handle
04508   * @param  TimerIdx Timer index
04509   *                   This parameter can be one of the following values:
04510   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04511   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04512   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04513   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04514   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04515   * @param  CaptureUnit Capture unit to configure
04516   *                    This parameter can be one of the following values:
04517   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
04518   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
04519   * @param  pCaptureCfg pointer to the compare unit configuration structure
04520   * @retval HAL status
04521   * @note This function must be called before starting the timer
04522   */
04523 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
04524                                                   uint32_t TimerIdx,
04525                                                   uint32_t CaptureUnit,
04526                                                   HRTIM_CaptureCfgTypeDef* pCaptureCfg)
04527 {
04528   /* Check parameters */
04529   assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger));
04530
04531   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04532   {
04533      return HAL_BUSY;
04534   }
04535
04536   /* Process Locked */
04537   __HAL_LOCK(hhrtim);
04538
04539   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04540
04541   /* Configure the capture unit */
04542   switch (CaptureUnit)
04543   {
04544   case HRTIM_CAPTUREUNIT_1:
04545     {
04546       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = pCaptureCfg->Trigger;
04547     }
04548     break;
04549   case HRTIM_CAPTUREUNIT_2:
04550     {
04551       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = pCaptureCfg->Trigger;
04552     }
04553     break;
04554   default:
04555     break;
04556   }
04557
04558   hhrtim->State = HAL_HRTIM_STATE_READY;
04559
04560   /* Process Unlocked */
04561   __HAL_UNLOCK(hhrtim);
04562
04563   return HAL_OK;
04564 }
04565
04566 /**
04567   * @brief  Configures the output of a timer operating in waveform mode
04568   * @param  hhrtim pointer to HAL HRTIM handle
04569   * @param  TimerIdx Timer index
04570   *                   This parameter can be one of the following values:
04571   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04572   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04573   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04574   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04575   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04576   * @param  Output Timer output
04577   *                    This parameter can be one of the following values:
04578   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
04579   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
04580   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
04581   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
04582   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
04583   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
04584   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
04585   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
04586   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
04587   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
04588   * @param  pOutputCfg pointer to the timer output configuration structure
04589   * @retval HAL status
04590   * @note This function must be called before configuring the timer and after
04591   *       configuring the deadtime insertion feature (if required).
04592   */
04593 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
04594                                                 uint32_t TimerIdx,
04595                                                 uint32_t Output,
04596                                                 HRTIM_OutputCfgTypeDef * pOutputCfg)
04597 {
04598   /* Check parameters */
04599   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
04600   assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
04601   assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
04602   assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
04603   assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
04604   assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
04605   assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
04606
04607   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04608   {
04609      return HAL_BUSY;
04610   }
04611
04612   /* Process Locked */
04613   __HAL_LOCK(hhrtim);
04614
04615   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04616
04617   /* Configure the timer output */
04618   HRTIM_OutputConfig(hhrtim,
04619                      TimerIdx,
04620                      Output,
04621                      pOutputCfg);
04622
04623   hhrtim->State = HAL_HRTIM_STATE_READY;
04624
04625   /* Process Unlocked */
04626   __HAL_UNLOCK(hhrtim);
04627
04628   return HAL_OK;
04629 }
04630
04631 /**
04632   * @brief  Forces the timer output to its active or inactive state
04633   * @param  hhrtim pointer to HAL HRTIM handle
04634   * @param  TimerIdx Timer index
04635   *                   This parameter can be one of the following values:
04636   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04637   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04638   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04639   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04640   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04641   * @param  Output Timer output
04642   *                    This parameter can be one of the following values:
04643   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
04644   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
04645   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
04646   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
04647   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
04648   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
04649   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
04650   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
04651   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
04652   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
04653   * @param OutputLevel indicates whether the output is forced to its active or inactive level
04654   *                    This parameter can be one of the following values:
04655   *                    @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
04656   *                    @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
04657   * @retval HAL status
04658   * @note The 'software set/reset trigger' bit in the output set/reset registers
04659   *       is automatically reset by hardware
04660   */
04661 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
04662                                                    uint32_t TimerIdx,
04663                                                    uint32_t Output,
04664                                                    uint32_t OutputLevel)
04665 {
04666   /* Check parameters */
04667   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
04668   assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
04669
04670   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04671   {
04672      return HAL_BUSY;
04673   }
04674
04675   /* Process Locked */
04676   __HAL_LOCK(hhrtim);
04677
04678   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04679
04680   /* Force timer output level */
04681   switch (Output)
04682   {
04683   case HRTIM_OUTPUT_TA1:
04684   case HRTIM_OUTPUT_TB1:
04685   case HRTIM_OUTPUT_TC1:
04686   case HRTIM_OUTPUT_TD1:
04687   case HRTIM_OUTPUT_TE1:
04688     {
04689       if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
04690       {
04691         /* Force output to its active state */
04692         hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R |= HRTIM_SET1R_SST;
04693       }
04694       else
04695       {
04696         /* Force output to its inactive state */
04697         hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R |= HRTIM_RST1R_SRT;
04698       }
04699     }
04700     break;
04701   case HRTIM_OUTPUT_TA2:
04702   case HRTIM_OUTPUT_TB2:
04703   case HRTIM_OUTPUT_TC2:
04704   case HRTIM_OUTPUT_TD2:
04705   case HRTIM_OUTPUT_TE2:
04706     {
04707       if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
04708       {
04709         /* Force output to its active state */
04710         hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R |= HRTIM_SET2R_SST;
04711       }
04712       else
04713       {
04714         /* Force output to its inactive state */
04715         hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R |= HRTIM_RST2R_SRT;
04716       }
04717     }
04718     break;
04719   default:
04720     break;
04721   }
04722
04723   hhrtim->State = HAL_HRTIM_STATE_READY;
04724
04725   /* Process Unlocked */
04726   __HAL_UNLOCK(hhrtim);
04727
04728   return HAL_OK;
04729 }
04730
04731 /**
04732   * @brief  Enables the generation of the waveform signal on the designated output(s)
04733   *         Outputs can be combined (ORed) to allow for simultaneous output enabling.
04734   * @param  hhrtim pointer to HAL HRTIM handle
04735   * @param  OutputsToStart Timer output(s) to enable
04736   *                    This parameter can be any combination of the following values:
04737   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
04738   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
04739   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
04740   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
04741   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
04742   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
04743   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
04744   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
04745   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
04746   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
04747   * @retval HAL status
04748   */
04749 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
04750                                                 uint32_t OutputsToStart)
04751 {
04752    /* Check the parameters */
04753   assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
04754
04755   /* Process Locked */
04756   __HAL_LOCK(hhrtim);
04757
04758   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04759
04760   /* Enable the HRTIM outputs */
04761   hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
04762
04763   hhrtim->State = HAL_HRTIM_STATE_READY;
04764
04765   /* Process Unlocked */
04766   __HAL_UNLOCK(hhrtim);
04767
04768   return HAL_OK;
04769 }
04770
04771 /**
04772   * @brief  Disables the generation of the waveform signal on the designated output(s)
04773   *         Outputs can be combined (ORed) to allow for simultaneous output disabling.
04774   * @param  hhrtim pointer to HAL HRTIM handle
04775   * @param  OutputsToStop Timer output(s) to disable
04776   *                    This parameter can be any combination of the following values:
04777   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
04778   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
04779   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
04780   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
04781   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
04782   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
04783   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
04784   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
04785   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
04786   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
04787   * @retval HAL status
04788   */
04789 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
04790                                                uint32_t OutputsToStop)
04791 {
04792    /* Check the parameters */
04793   assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
04794
04795   /* Process Locked */
04796   __HAL_LOCK(hhrtim);
04797
04798   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04799
04800   /* Enable the HRTIM outputs */
04801   hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
04802
04803   hhrtim->State = HAL_HRTIM_STATE_READY;
04804
04805   /* Process Unlocked */
04806   __HAL_UNLOCK(hhrtim);
04807
04808   return HAL_OK;
04809 }
04810
04811 /**
04812   * @brief  Starts the counter of the designated timer(s) operating in waveform mode
04813   *         Timers can be combined (ORed) to allow for simultaneous counter start.
04814   * @param  hhrtim pointer to HAL HRTIM handle
04815   * @param  Timers Timer counter(s) to start
04816   *                   This parameter can be any combination of the following values:
04817   *                   @arg HRTIM_TIMERID_MASTER
04818   *                   @arg HRTIM_TIMERID_TIMER_A
04819   *                   @arg HRTIM_TIMERID_TIMER_B
04820   *                   @arg HRTIM_TIMERID_TIMER_C
04821   *                   @arg HRTIM_TIMERID_TIMER_D
04822   *                   @arg HRTIM_TIMERID_TIMER_E
04823   * @retval HAL status
04824   */
04825 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef * hhrtim,
04826                                                  uint32_t Timers)
04827 {
04828    /* Check the parameters */
04829   assert_param(IS_HRTIM_TIMERID(Timers));
04830
04831   /* Process Locked */
04832   __HAL_LOCK(hhrtim);
04833
04834   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04835
04836   /* Enable timer(s) counter */
04837   hhrtim->Instance->sMasterRegs.MCR |= (Timers);
04838
04839   hhrtim->State = HAL_HRTIM_STATE_READY;
04840
04841   /* Process Unlocked */
04842   __HAL_UNLOCK(hhrtim);
04843
04844   return HAL_OK;
04845 }
04846
04847 /**
04848   * @brief  Stops the counter of the designated timer(s) operating in waveform mode
04849   *         Timers can be combined (ORed) to allow for simultaneous counter stop.
04850   * @param  hhrtim pointer to HAL HRTIM handle
04851   * @param  Timers Timer counter(s) to stop
04852   *                   This parameter can be any combination of the following values:
04853   *                   @arg HRTIM_TIMERID_MASTER
04854   *                   @arg HRTIM_TIMERID_A
04855   *                   @arg HRTIM_TIMERID_B
04856   *                   @arg HRTIM_TIMERID_C
04857   *                   @arg HRTIM_TIMERID_D
04858   *                   @arg HRTIM_TIMERID_E
04859   * @retval HAL status
04860   * @note The counter of a timer is stopped only if all timer outputs are disabled
04861   */
04862 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef * hhrtim,
04863                                                 uint32_t Timers)
04864 {
04865    /* Check the parameters */
04866   assert_param(IS_HRTIM_TIMERID(Timers));
04867
04868   /* Process Locked */
04869   __HAL_LOCK(hhrtim);
04870
04871   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04872
04873   /* Disable timer(s) counter */
04874   hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
04875
04876   hhrtim->State = HAL_HRTIM_STATE_READY;
04877
04878   /* Process Unlocked */
04879   __HAL_UNLOCK(hhrtim);
04880
04881   return HAL_OK;
04882 }
04883
04884 /**
04885   * @brief  Starts the counter of the designated timer(s) operating in waveform mode
04886   *         Timers can be combined (ORed) to allow for simultaneous counter start.
04887   * @param  hhrtim pointer to HAL HRTIM handle
04888   * @param  Timers Timer counter(s) to start
04889   *                   This parameter can be any combination of the following values:
04890   *                   @arg HRTIM_TIMERID_MASTER
04891   *                   @arg HRTIM_TIMERID_A
04892   *                   @arg HRTIM_TIMERID_B
04893   *                   @arg HRTIM_TIMERID_C
04894   *                   @arg HRTIM_TIMERID_D
04895   *                   @arg HRTIM_TIMERID_E
04896   * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
04897   *       to the timers to start are enabled within this function.
04898   *       Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
04899   *       function.
04900   * @retval HAL status
04901   */
04902 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef * hhrtim,
04903                                                     uint32_t Timers)
04904 {
04905   uint8_t timer_idx;
04906
04907    /* Check the parameters */
04908   assert_param(IS_HRTIM_TIMERID(Timers));
04909
04910   /* Process Locked */
04911   __HAL_LOCK(hhrtim);
04912
04913   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04914
04915   /* Enable HRTIM interrupts (if required) */
04916   __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
04917
04918   /* Enable master timer related interrupts (if required) */
04919   if ((Timers & HRTIM_TIMERID_MASTER) != RESET)
04920   {
04921     __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
04922                                  hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
04923   }
04924
04925   /* Enable timing unit related interrupts (if required) */
04926   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
04927        timer_idx < HRTIM_TIMERINDEX_MASTER ;
04928        timer_idx++)
04929   {
04930     if ((Timers & TimerIdxToTimerId[timer_idx]) != RESET)
04931     {
04932       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
04933                                   timer_idx,
04934                                   hhrtim->TimerParam[timer_idx].InterruptRequests);
04935     }
04936   }
04937
04938   /* Enable timer(s) counter */
04939   hhrtim->Instance->sMasterRegs.MCR |= (Timers);
04940
04941   hhrtim->State = HAL_HRTIM_STATE_READY;
04942
04943   /* Process Unlocked */
04944   __HAL_UNLOCK(hhrtim);
04945
04946   return HAL_OK;}
04947
04948 /**
04949   * @brief  Stops the counter of the designated timer(s) operating in waveform mode
04950   *         Timers can be combined (ORed) to allow for simultaneous counter stop.
04951   * @param  hhrtim pointer to HAL HRTIM handle
04952   * @param  Timers Timer counter(s) to stop
04953   *                   This parameter can be any combination of the following values:
04954   *                   @arg HRTIM_TIMERID_MASTER
04955   *                   @arg HRTIM_TIMERID_A
04956   *                   @arg HRTIM_TIMERID_B
04957   *                   @arg HRTIM_TIMERID_C
04958   *                   @arg HRTIM_TIMERID_D
04959   *                   @arg HRTIM_TIMERID_E
04960   * @retval HAL status
04961   * @note The counter of a timer is stopped only if all timer outputs are disabled
04962   * @note All enabled timer related interrupts are disabled.
04963   */
04964 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef * hhrtim,
04965                                                    uint32_t Timers)
04966 {
04967   /* ++ WA */
04968   __IO uint32_t delai = (uint32_t)(0x17FU);
04969   /* -- WA */
04970
04971   uint8_t timer_idx;
04972
04973   /* Check the parameters */
04974   assert_param(IS_HRTIM_TIMERID(Timers));
04975
04976   /* Process Locked */
04977   __HAL_LOCK(hhrtim);
04978
04979   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04980
04981   /* Disable HRTIM interrupts (if required) */
04982   __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
04983
04984   /* Disable master timer related interrupts (if required) */
04985   if ((Timers & HRTIM_TIMERID_MASTER) != RESET)
04986   {
04987     /* Interrupts enable flag must be cleared one by one */
04988     __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
04989   }
04990
04991   /* Disable timing unit related interrupts (if required) */
04992   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
04993        timer_idx < HRTIM_TIMERINDEX_MASTER ;
04994        timer_idx++)
04995   {
04996     if ((Timers & TimerIdxToTimerId[timer_idx]) != RESET)
04997     {
04998       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
04999     }
05000   }
05001
05002   /* ++ WA */
05003   do { delai--; } while (delai != 0U);
05004   /* -- WA */
05005
05006   /* Disable timer(s) counter */
05007   hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
05008
05009   hhrtim->State = HAL_HRTIM_STATE_READY;
05010
05011   /* Process Unlocked */
05012   __HAL_UNLOCK(hhrtim);
05013
05014   return HAL_OK;
05015 }
05016
05017 /**
05018   * @brief  Starts the counter of the designated timer(s) operating in waveform mode
05019   *         Timers can be combined (ORed) to allow for simultaneous counter start.
05020   * @param  hhrtim pointer to HAL HRTIM handle
05021   * @param  Timers Timer counter(s) to start
05022   *                   This parameter can be any combination of the following values:
05023   *                   HRTIM_TIMERID_MASTER
05024   *                   @arg HRTIM_TIMERID_A
05025   *                   @arg HRTIM_TIMERID_B
05026   *                   @arg HRTIM_TIMERID_C
05027   *                   @arg HRTIM_TIMERID_D
05028   *                   @arg HRTIM_TIMERID_E
05029   * @retval HAL status
05030   * @note This function enables the dma request(s) mentionned in the timer
05031   *       configuration data structure for every timers to start.
05032   * @note The source memory address, the destination memory address and the
05033   *       size of each DMA transfer are specified at timer configuration time
05034   *       (see HAL_HRTIM_WaveformTimerConfig)
05035   */
05036 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef * hhrtim,
05037                                                      uint32_t Timers)
05038 {
05039   uint8_t timer_idx;
05040   DMA_HandleTypeDef * hdma;
05041
05042    /* Check the parameters */
05043   assert_param(IS_HRTIM_TIMERID(Timers));
05044
05045   if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
05046   {
05047      return HAL_BUSY;
05048   }
05049
05050   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05051
05052   /* Process Locked */
05053   __HAL_LOCK(hhrtim);
05054
05055   if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
05056       (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
05057   {
05058       /* Set the DMA error callback */
05059       hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
05060
05061       /* Set the DMA transfer completed callback */
05062       hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
05063
05064       /* Enable the DMA channel */
05065       HAL_DMA_Start_IT(hhrtim->hdmaMaster,
05066                        hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
05067                        hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
05068                        hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize);
05069
05070       /* Enable the timer DMA request */
05071       __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
05072                                    hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
05073   }
05074
05075   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
05076        timer_idx < HRTIM_TIMERINDEX_MASTER ;
05077        timer_idx++)
05078   {
05079     if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
05080          (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
05081     {
05082       /* Get the timer DMA handler */
05083       hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
05084      if (hdma == NULL)
05085      {
05086       hhrtim->State = HAL_HRTIM_STATE_ERROR;
05087
05088       /* Process Unlocked */
05089       __HAL_UNLOCK(hhrtim);
05090
05091       return HAL_ERROR;
05092      }
05093
05094       /* Set the DMA error callback */
05095       hdma->XferErrorCallback = HRTIM_DMAError ;
05096
05097       /* Set the DMA transfer completed callback */
05098       hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
05099
05100       /* Enable the DMA channel */
05101       HAL_DMA_Start_IT(hdma,
05102                        hhrtim->TimerParam[timer_idx].DMASrcAddress,
05103                        hhrtim->TimerParam[timer_idx].DMADstAddress,
05104                        hhrtim->TimerParam[timer_idx].DMASize);
05105
05106       /* Enable the timer DMA request */
05107       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
05108                                    timer_idx,
05109                                    hhrtim->TimerParam[timer_idx].DMARequests);
05110     }
05111   }
05112
05113   /* Enable the timer counter */
05114   __HAL_HRTIM_ENABLE(hhrtim, Timers);
05115
05116   hhrtim->State = HAL_HRTIM_STATE_READY;
05117
05118   /* Process Unlocked */
05119   __HAL_UNLOCK(hhrtim);
05120
05121   return HAL_OK;
05122 }
05123
05124 /**
05125   * @brief  Stops the counter of the designated timer(s) operating in waveform mode
05126   *         Timers can be combined (ORed) to allow for simultaneous counter stop.
05127   * @param  hhrtim pointer to HAL HRTIM handle
05128   * @param  Timers Timer counter(s) to stop
05129   *                   This parameter can be any combination of the following values:
05130   *                   @arg HRTIM_TIMERID_MASTER
05131   *                   @arg HRTIM_TIMERID_A
05132   *                   @arg HRTIM_TIMERID_B
05133   *                   @arg HRTIM_TIMERID_C
05134   *                   @arg HRTIM_TIMERID_D
05135   *                   @arg HRTIM_TIMERID_E
05136   * @retval HAL status
05137   * @note  The counter of a timer is stopped only if all timer outputs are disabled
05138   * @note  All enabled timer related DMA requests are disabled.
05139   */
05140 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef * hhrtim,
05141                                                     uint32_t Timers)
05142 {
05143   uint8_t timer_idx;
05144   DMA_HandleTypeDef * hdma;
05145
05146   /* Check the parameters */
05147   assert_param(IS_HRTIM_TIMERID(Timers));
05148
05149   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05150
05151   if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
05152       (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
05153   {
05154     /* Disable the DMA */
05155     HAL_DMA_Abort(hhrtim->hdmaMaster);
05156
05157     /* Disable the DMA request(s) */
05158     __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
05159                                    hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
05160   }
05161
05162   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
05163        timer_idx < HRTIM_TIMERINDEX_MASTER ;
05164        timer_idx++)
05165   {
05166     if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
05167         (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
05168     {
05169       /* Get the timer DMA handler */
05170       hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
05171       if (hdma == NULL)
05172       {
05173         /* Disable the DMA request(s) */
05174         __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
05175                                     timer_idx,
05176                                     hhrtim->TimerParam[timer_idx].DMARequests);
05177
05178         /* Disable the timer counter */
05179         __HAL_HRTIM_DISABLE(hhrtim, Timers);
05180
05181         hhrtim->State = HAL_HRTIM_STATE_ERROR;
05182
05183         return HAL_ERROR;
05184        }
05185
05186       /* Disable the DMA */
05187       HAL_DMA_Abort(hdma);
05188
05189     /* Disable the DMA request(s) */
05190       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
05191                                     timer_idx,
05192                                     hhrtim->TimerParam[timer_idx].DMARequests);
05193     }
05194   }
05195
05196   /* Disable the timer counter */
05197   __HAL_HRTIM_DISABLE(hhrtim, Timers);
05198
05199   hhrtim->State = HAL_HRTIM_STATE_READY;
05200
05201   return HAL_OK;
05202 }
05203
05204 /**
05205   * @brief  Enables or disables the HRTIM burst mode controller.
05206   * @param  hhrtim pointer to HAL HRTIM handle
05207   * @param  Enable Burst mode controller enabling
05208   *                    This parameter can be one of the following values:
05209   *                    @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
05210   *                    @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
05211   * @retval HAL status
05212   * @note This function must be called after starting the timer(s)
05213   */
05214 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
05215                                          uint32_t Enable)
05216 {
05217   uint32_t hrtim_bmcr;
05218
05219   /* Check parameters */
05220   assert_param(IS_HRTIM_BURSTMODECTL(Enable));
05221
05222   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05223   {
05224      return HAL_BUSY;
05225   }
05226
05227   /* Process Locked */
05228   __HAL_LOCK(hhrtim);
05229
05230   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05231
05232   /* Enable/Disable the burst mode controller */
05233   hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
05234   hrtim_bmcr &= ~(HRTIM_BMCR_BME);
05235   hrtim_bmcr |= Enable;
05236
05237   /* Update the HRTIM registers */
05238   hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
05239
05240   hhrtim->State = HAL_HRTIM_STATE_READY;
05241
05242   /* Process Unlocked */
05243   __HAL_UNLOCK(hhrtim);
05244
05245   return HAL_OK;
05246 }
05247
05248 /**
05249   * @brief  Triggers the burst mode operation.
05250   * @param  hhrtim pointer to HAL HRTIM handle
05251   * @retval HAL status
05252   */
05253 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
05254 {
05255   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05256   {
05257      return HAL_BUSY;
05258   }
05259
05260   /* Process Locked */
05261   __HAL_LOCK(hhrtim);
05262
05263   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05264
05265   /* Software trigger of the burst mode controller */
05266   hhrtim->Instance->sCommonRegs.BMTRGR |= HRTIM_BMTRGR_SW;
05267
05268   hhrtim->State = HAL_HRTIM_STATE_READY;
05269
05270   /* Process Unlocked */
05271   __HAL_UNLOCK(hhrtim);
05272
05273   return HAL_OK;
05274 }
05275
05276 /**
05277   * @brief  Triggers a software capture on the designed capture unit
05278   * @param  hhrtim pointer to HAL HRTIM handle
05279   * @param  TimerIdx Timer index
05280   *                   This parameter can be one of the following values:
05281   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05282   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05283   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05284   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05285   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05286   * @param  CaptureUnit Capture unit to trig
05287   *                    This parameter can be one of the following values:
05288   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
05289   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
05290   * @retval HAL status
05291   * @note The 'software capture' bit in the capure configuration register is
05292   *       automatically reset by hardware
05293   */
05294 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
05295                                             uint32_t TimerIdx,
05296                                             uint32_t CaptureUnit)
05297 {
05298   /* Check parameters */
05299   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
05300   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
05301
05302   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05303   {
05304      return HAL_BUSY;
05305   }
05306
05307   /* Process Locked */
05308   __HAL_LOCK(hhrtim);
05309
05310   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05311
05312   /* Force a software capture on concerned capture unit */
05313   switch (CaptureUnit)
05314   {
05315   case HRTIM_CAPTUREUNIT_1:
05316     {
05317       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR |= HRTIM_CPT1CR_SWCPT;
05318     }
05319     break;
05320   case HRTIM_CAPTUREUNIT_2:
05321     {
05322       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT;
05323     }
05324     break;
05325   default:
05326     break;
05327   }
05328
05329   hhrtim->State = HAL_HRTIM_STATE_READY;
05330
05331   /* Process Unlocked */
05332   __HAL_UNLOCK(hhrtim);
05333
05334   return HAL_OK;
05335 }
05336
05337 /**
05338   * @brief  Triggers the update of the registers of one or several timers
05339   * @param  hhrtim pointer to HAL HRTIM handle
05340   * @param  Timers timers concerned with the software register update
05341   *                   This parameter can be any combination of the following values:
05342   *                   @arg HRTIM_TIMERUPDATE_MASTER
05343   *                   @arg HRTIM_TIMERUPDATE_A
05344   *                   @arg HRTIM_TIMERUPDATE_B
05345   *                   @arg HRTIM_TIMERUPDATE_C
05346   *                   @arg HRTIM_TIMERUPDATE_D
05347   *                   @arg HRTIM_TIMERUPDATE_E
05348   * @retval HAL status
05349   * @note The 'software update' bits in the HRTIM conrol register 2 register are
05350   *       automatically reset by hardware
05351   */
05352 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
05353                                            uint32_t Timers)
05354 {
05355   /* Check parameters */
05356   assert_param(IS_HRTIM_TIMERUPDATE(Timers));
05357
05358   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05359   {
05360      return HAL_BUSY;
05361   }
05362
05363   /* Process Locked */
05364   __HAL_LOCK(hhrtim);
05365
05366   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05367
05368   /* Force timer(s) registers update */
05369   hhrtim->Instance->sCommonRegs.CR2 |= Timers;
05370
05371   hhrtim->State = HAL_HRTIM_STATE_READY;
05372
05373   /* Process Unlocked */
05374   __HAL_UNLOCK(hhrtim);
05375
05376   return HAL_OK;
05377 }
05378
05379 /**
05380   * @brief  Triggers the reset of one or several timers
05381   * @param  hhrtim pointer to HAL HRTIM handle
05382   * @param  Timers timers concerned with the software counter reset
05383   *                   This parameter can be any combination of the following values:
05384   *                   @arg HRTIM_TIMERRESET_MASTER
05385   *                   @arg HRTIM_TIMERRESET_TIMER_A
05386   *                   @arg HRTIM_TIMERRESET_TIMER_B
05387   *                   @arg HRTIM_TIMERRESET_TIMER_C
05388   *                   @arg HRTIM_TIMERRESET_TIMER_D
05389   *                   @arg HRTIM_TIMERRESET_TIMER_E
05390   * @retval HAL status
05391   * @note The 'software reset' bits in the HRTIM conrol register 2  are
05392   *       automatically reset by hardware
05393   */
05394 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
05395                                           uint32_t Timers)
05396 {
05397   /* Check parameters */
05398   assert_param(IS_HRTIM_TIMERRESET(Timers));
05399
05400   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05401   {
05402      return HAL_BUSY;
05403   }
05404
05405   /* Process Locked */
05406   __HAL_LOCK(hhrtim);
05407
05408   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05409
05410   /* Force timer(s) registers reset */
05411   hhrtim->Instance->sCommonRegs.CR2 = Timers;
05412
05413   hhrtim->State = HAL_HRTIM_STATE_READY;
05414
05415   /* Process Unlocked */
05416   __HAL_UNLOCK(hhrtim);
05417
05418   return HAL_OK;
05419 }
05420
05421 /**
05422   * @brief  Starts a burst DMA operation to update HRTIM control registers content
05423   * @param  hhrtim pointer to HAL HRTIM handle
05424   * @param  TimerIdx Timer index
05425   *                   This parameter can be one of the following values:
05426   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
05427   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05428   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05429   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05430   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05431   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05432   * @param  BurstBufferAddress address of the buffer the HRTIM control registers
05433   *                             content will be updated from.
05434   * @param  BurstBufferLength size (in WORDS) of the burst buffer.
05435   * @retval HAL status
05436   * @note The TimerIdx parameter determines the dma channel to be used by the
05437   *       DMA burst controller (see below)
05438   *       HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
05439   *       HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
05440   *       HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
05441   *       HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
05442   *       HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
05443   *       HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
05444   */
05445 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
05446                                              uint32_t TimerIdx,
05447                                              uint32_t BurstBufferAddress,
05448                                              uint32_t BurstBufferLength)
05449 {
05450   DMA_HandleTypeDef * hdma;
05451
05452   /* Check the parameters */
05453   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
05454
05455   if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
05456   {
05457      return HAL_BUSY;
05458   }
05459   if((hhrtim->State == HAL_HRTIM_STATE_READY))
05460   {
05461     if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
05462     {
05463       return HAL_ERROR;
05464     }
05465     else
05466     {
05467       hhrtim->State = HAL_HRTIM_STATE_BUSY;
05468     }
05469   }
05470
05471   /* Process Locked */
05472   __HAL_LOCK(hhrtim);
05473
05474   /* Get the timer DMA handler */
05475   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
05476   if (hdma == NULL)
05477   {
05478     hhrtim->State = HAL_HRTIM_STATE_ERROR;
05479
05480     /* Process Unlocked */
05481     __HAL_UNLOCK(hhrtim);
05482
05483     return HAL_ERROR;
05484   }
05485
05486   /* Set the DMA transfer completed callback */
05487   hdma->XferCpltCallback = HRTIM_BurstDMACplt;
05488
05489   /* Set the DMA error callback */
05490   hdma->XferErrorCallback = HRTIM_DMAError ;
05491
05492   /* Enable the DMA channel */
05493   HAL_DMA_Start_IT(hdma,
05494                    BurstBufferAddress,
05495                    (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR),
05496                    BurstBufferLength);
05497
05498   hhrtim->State = HAL_HRTIM_STATE_READY;
05499
05500   /* Process Unlocked */
05501   __HAL_UNLOCK(hhrtim);
05502
05503   return HAL_OK;
05504 }
05505
05506 /**
05507   * @brief  Enables the transfer from preload to active registers for one
05508   *         or several timing units (including master timer).
05509   * @param  hhrtim pointer to HAL HRTIM handle
05510   * @param  Timers Timer(s) concerned by the register preload enabling command
05511   *                   This parameter can be any combination of the following values:
05512   *                   @arg HRTIM_TIMERUPDATE_MASTER
05513   *                   @arg HRTIM_TIMERUPDATE_A
05514   *                   @arg HRTIM_TIMERUPDATE_B
05515   *                   @arg HRTIM_TIMERUPDATE_C
05516   *                   @arg HRTIM_TIMERUPDATE_D
05517   *                   @arg HRTIM_TIMERUPDATE_E
05518   * @retval HAL status
05519   */
05520 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
05521                                           uint32_t Timers)
05522 {
05523    /* Check the parameters */
05524   assert_param(IS_HRTIM_TIMERUPDATE(Timers));
05525
05526   /* Process Locked */
05527   __HAL_LOCK(hhrtim);
05528
05529   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05530
05531   /* Enable timer(s) registers update */
05532   hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
05533
05534   hhrtim->State = HAL_HRTIM_STATE_READY;
05535
05536   /* Process Unlocked */
05537   __HAL_UNLOCK(hhrtim);
05538
05539   return HAL_OK;
05540   }
05541
05542 /**
05543   * @brief  Disables the transfer from preload to active registers for one
05544   *         or several timing units (including master timer).
05545   * @param  hhrtim pointer to HAL HRTIM handle
05546   * @param  Timers Timer(s) concerned by the register preload disabling command
05547   *                   This parameter can be any combination of the following values:
05548   *                   @arg HRTIM_TIMERUPDATE_MASTER
05549   *                   @arg HRTIM_TIMERUPDATE_A
05550   *                   @arg HRTIM_TIMERUPDATE_B
05551   *                   @arg HRTIM_TIMERUPDATE_C
05552   *                   @arg HRTIM_TIMERUPDATE_D
05553   *                   @arg HRTIM_TIMERUPDATE_E
05554   * @retval HAL status
05555   */
05556 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
05557                                           uint32_t Timers)
05558 {
05559    /* Check the parameters */
05560   assert_param(IS_HRTIM_TIMERUPDATE(Timers));
05561
05562   /* Process Locked */
05563   __HAL_LOCK(hhrtim);
05564
05565   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05566
05567   /* Enable timer(s) registers update */
05568   hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
05569
05570   hhrtim->State = HAL_HRTIM_STATE_READY;
05571
05572   /* Process Unlocked */
05573   __HAL_UNLOCK(hhrtim);
05574
05575   return HAL_OK;
05576   }
05577
05578 /**
05579   * @}
05580   */
05581
05582 /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
05583  *  @brief    Peripheral State functions
05584 @verbatim
05585  ===============================================================================
05586               ##### Peripheral State functions #####
05587  ===============================================================================
05588     [..]  This section provides functions used to get HRTIM or HRTIM timer
05589           specific information:
05590       (+) Get HRTIM HAL state
05591       (+) Get captured value
05592       (+) Get HRTIM timer output level
05593       (+) Get HRTIM timer output state
05594       (+) Get delayed protection status
05595       (+) Get burst status
05596       (+) Get current push-pull status
05597       (+) Get idle push-pull status
05598
05599 @endverbatim
05600   * @{
05601   */
05602
05603 /**
05604   * @brief  return the HRTIM HAL state
05605   * @param  hhrtim pointer to HAL HRTIM handle
05606   * @retval HAL state
05607   */
05608 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim)
05609 {
05610   /* Return ADC state */
05611   return hhrtim->State;
05612 }
05613
05614 /**
05615   * @brief  Returns actual value of the capture register of the designated capture unit
05616   * @param  hhrtim pointer to HAL HRTIM handle
05617   * @param  TimerIdx Timer index
05618   *                   This parameter can be one of the following values:
05619   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05620   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05621   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05622   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05623   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05624   * @param  CaptureUnit Capture unit to trig
05625   *                    This parameter can be one of the following values:
05626   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
05627   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
05628   * @retval Captured value
05629   */
05630 uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
05631                                     uint32_t TimerIdx,
05632                                     uint32_t CaptureUnit)
05633 {
05634   uint32_t captured_value = 0U;
05635
05636   /* Check parameters */
05637   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
05638   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
05639
05640   /* Read captured value */
05641   switch (CaptureUnit)
05642   {
05643   case HRTIM_CAPTUREUNIT_1:
05644     {
05645       captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
05646     }
05647     break;
05648   case HRTIM_CAPTUREUNIT_2:
05649     {
05650       captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
05651     }
05652     break;
05653   default:
05654     break;
05655   }
05656
05657   return captured_value;
05658 }
05659
05660 /**
05661   * @brief  Returns actual level (active or inactive) of the designated output
05662   * @param  hhrtim pointer to HAL HRTIM handle
05663   * @param  TimerIdx Timer index
05664   *                   This parameter can be one of the following values:
05665   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05666   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05667   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05668   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05669   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05670   * @param  Output Timer output
05671   *                    This parameter can be one of the following values:
05672   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
05673   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
05674   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
05675   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
05676   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
05677   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
05678   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
05679   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
05680   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
05681   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
05682   * @retval Output level
05683   * @note Returned output level is taken before the output stage (chopper,
05684   *        polarity).
05685   */
05686 uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
05687                                           uint32_t TimerIdx,
05688                                           uint32_t Output)
05689 {
05690   uint32_t output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
05691
05692   /* Check parameters */
05693   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
05694
05695   /* Read the output level */
05696   switch (Output)
05697   {
05698   case HRTIM_OUTPUT_TA1:
05699   case HRTIM_OUTPUT_TB1:
05700   case HRTIM_OUTPUT_TC1:
05701   case HRTIM_OUTPUT_TD1:
05702   case HRTIM_OUTPUT_TE1:
05703     {
05704       if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != RESET)
05705       {
05706         output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
05707       }
05708       else
05709       {
05710         output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
05711       }
05712     }
05713     break;
05714   case HRTIM_OUTPUT_TA2:
05715   case HRTIM_OUTPUT_TB2:
05716   case HRTIM_OUTPUT_TC2:
05717   case HRTIM_OUTPUT_TD2:
05718   case HRTIM_OUTPUT_TE2:
05719     {
05720       if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != RESET)
05721       {
05722         output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
05723       }
05724       else
05725       {
05726         output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
05727       }
05728     }
05729     break;
05730   default:
05731     break;
05732   }
05733
05734   return output_level;
05735 }
05736
05737 /**
05738   * @brief  Returns actual state (RUN, IDLE, FAULT) of the designated output
05739   * @param  hhrtim pointer to HAL HRTIM handle
05740   * @param  TimerIdx Timer index
05741   *                   This parameter can be one of the following values:
05742   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05743   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05744   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05745   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05746   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05747   * @param  Output Timer output
05748   *                    This parameter can be one of the following values:
05749   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
05750   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
05751   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
05752   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
05753   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
05754   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
05755   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
05756   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
05757   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
05758   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
05759   * @retval Output state
05760   */
05761 uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
05762                                           uint32_t TimerIdx,
05763                                           uint32_t Output)
05764 {
05765   uint32_t output_bit = 0U;
05766   uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE;
05767
05768   /* Check parameters */
05769   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
05770
05771   /* Set output state according to output control status and output disable status */
05772   switch (Output)
05773   {
05774   case HRTIM_OUTPUT_TA1:
05775     {
05776       output_bit = HRTIM_OENR_TA1OEN;
05777     }
05778     break;
05779   case HRTIM_OUTPUT_TA2:
05780     {
05781       output_bit = HRTIM_OENR_TA2OEN;
05782     }
05783     break;
05784   case HRTIM_OUTPUT_TB1:
05785     {
05786       output_bit = HRTIM_OENR_TB1OEN;
05787     }
05788     break;
05789   case HRTIM_OUTPUT_TB2:
05790     {
05791       output_bit = HRTIM_OENR_TB2OEN;
05792     }
05793     break;
05794   case HRTIM_OUTPUT_TC1:
05795     {
05796       output_bit = HRTIM_OENR_TC1OEN;
05797     }
05798     break;
05799   case HRTIM_OUTPUT_TC2:
05800     {
05801       output_bit = HRTIM_OENR_TC2OEN;
05802     }
05803     break;
05804   case HRTIM_OUTPUT_TD1:
05805     {
05806       output_bit = HRTIM_OENR_TD1OEN;
05807     }
05808     break;
05809   case HRTIM_OUTPUT_TD2:
05810     {
05811       output_bit = HRTIM_OENR_TD2OEN;
05812     }
05813     break;
05814   case HRTIM_OUTPUT_TE1:
05815     {
05816       output_bit = HRTIM_OENR_TE1OEN;
05817     }
05818     break;
05819   case HRTIM_OUTPUT_TE2:
05820     {
05821       output_bit = HRTIM_OENR_TE2OEN;
05822     }
05823     break;
05824   default:
05825     break;
05826   }
05827
05828   if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != RESET)
05829   {
05830     /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
05831     output_state = HRTIM_OUTPUTSTATE_RUN;
05832   }
05833   else
05834   {
05835     if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != RESET)
05836     {
05837     /* Output is disabled: output in FAULT state */
05838       output_state = HRTIM_OUTPUTSTATE_FAULT;
05839     }
05840     else
05841     {
05842       /* Output is disabled: output in IDLE state */
05843       output_state = HRTIM_OUTPUTSTATE_IDLE;
05844     }
05845   }
05846
05847   return(output_state);
05848 }
05849
05850 /**
05851   * @brief  Returns the level (active or inactive) of the designated output
05852   *         when the delayed protection was triggered.
05853   * @param  hhrtim pointer to HAL HRTIM handle
05854   * @param  TimerIdx Timer index
05855   *                   This parameter can be one of the following values:
05856   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05857   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05858   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05859   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05860   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05861   * @param  Output Timer output
05862   *                    This parameter can be one of the following values:
05863   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
05864   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
05865   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
05866   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
05867   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
05868   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
05869   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
05870   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
05871   *                    @arg HRTIM_OUTPUT_TD1: Timer E - Output 1
05872   *                    @arg HRTIM_OUTPUT_TD2: Timer E - Output 2
05873   * @retval Delayed protection status
05874   */
05875 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,
05876                                               uint32_t TimerIdx,
05877                                               uint32_t Output)
05878 {
05879   uint32_t delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
05880
05881   /* Check parameters */
05882   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
05883
05884   /* Read the delayed protection status */
05885   switch (Output)
05886   {
05887   case HRTIM_OUTPUT_TA1:
05888   case HRTIM_OUTPUT_TB1:
05889   case HRTIM_OUTPUT_TC1:
05890   case HRTIM_OUTPUT_TD1:
05891   case HRTIM_OUTPUT_TE1:
05892     {
05893       if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != RESET)
05894       {
05895         /* Output 1 was active when the delayed idle protection was triggered */
05896         delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
05897       }
05898       else
05899       {
05900         /* Output 1 was inactive when the delayed idle protection was triggered */
05901         delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
05902       }
05903     }
05904     break;
05905   case HRTIM_OUTPUT_TA2:
05906   case HRTIM_OUTPUT_TB2:
05907   case HRTIM_OUTPUT_TC2:
05908   case HRTIM_OUTPUT_TD2:
05909   case HRTIM_OUTPUT_TE2:
05910     {
05911       if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != RESET)
05912       {
05913         /* Output 2 was active when the delayed idle protection was triggered */
05914         delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
05915       }
05916       else
05917       {
05918         /* Output 2 was inactive when the delayed idle protection was triggered */
05919         delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
05920       }
05921     }
05922     break;
05923   default:
05924     break;
05925   }
05926
05927   return delayed_protection_status;
05928 }
05929
05930 /**
05931   * @brief  Returns the actual status (active or inactive) of the burst mode controller
05932   * @param  hhrtim pointer to HAL HRTIM handle
05933   * @retval Burst mode controller status
05934   */
05935 uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim)
05936 {
05937   uint32_t burst_mode_status;
05938
05939   /* Read burst mode status */
05940   burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
05941
05942   return burst_mode_status;
05943 }
05944
05945 /**
05946   * @brief  Indicates on which output the signal is currently active (when the
05947   *         push pull mode is enabled).
05948   * @param  hhrtim pointer to HAL HRTIM handle
05949   * @param  TimerIdx Timer index
05950   *                   This parameter can be one of the following values:
05951   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05952   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05953   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05954   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05955   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05956   * @retval Burst mode controller status
05957   */
05958 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim,
05959                                             uint32_t TimerIdx)
05960 {
05961   uint32_t current_pushpull_status;
05962
05963    /* Check the parameters */
05964   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
05965
05966   /* Read current push pull status */
05967   current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
05968
05969   return current_pushpull_status;
05970 }
05971
05972
05973 /**
05974   * @brief  Indicates on which output the signal was applied, in push-pull mode,
05975             balanced fault mode or delayed idle mode, when the protection was triggered.
05976   * @param  hhrtim pointer to HAL HRTIM handle
05977   * @param  TimerIdx Timer index
05978   *                   This parameter can be one of the following values:
05979   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05980   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05981   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05982   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05983   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05984   * @retval Idle Push Pull Status
05985   */
05986 uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim,
05987                                          uint32_t TimerIdx)
05988 {
05989   uint32_t idle_pushpull_status;
05990
05991    /* Check the parameters */
05992   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
05993
05994   /* Read current push pull status */
05995   idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
05996
05997   return idle_pushpull_status;
05998 }
05999
06000 /**
06001   * @}
06002   */
06003
06004 /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
06005  *  @brief  Functions called when HRTIM generates an interrupt
06006  *          7 interrupts can be generated by the master timer:
06007  *            - Master timer registers update
06008  *            - Synchronization event received
06009  *            - Master timer repetition event
06010  *            - Master Compare 1 to 4 event
06011  *          14 interrupts can be generated by each timing unit:
06012  *            - Delayed protection triggered
06013  *            - Counter reset or roll-over event
06014  *            - Output 1 and output 2 reset (transition active to inactive)
06015  *            - Output 1 and output 2 set (transition inactive to active)
06016  *            - Capture 1 and 2 events
06017  *            - Timing unit registers update
06018  *            - Repetition event
06019  *            - Compare 1 to 4 event
06020  *          8 global interrupts are generated for the whole HRTIM:
06021  *            - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
06022  *            - DLL calibration done
06023  *            - Burst mode period completed
06024 @verbatim
06025  ===============================================================================
06026                       ##### HRTIM interrupts handling #####
06027  ===============================================================================
06028     [..]
06029     This subsection provides a set of functions allowing to manage the HRTIM
06030     interrupts:
06031       (+)  HRTIM interrupt handler
06032       (+)  Callback function called when Fault1 interrupt occurs
06033       (+)  Callback function called when Fault2 interrupt occurs
06034       (+)  Callback function called when Fault3 interrupt occurs
06035       (+)  Callback function called when Fault4 interrupt occurs
06036       (+)  Callback function called when Fault5 interrupt occurs
06037       (+)  Callback function called when system Fault interrupt occurs
06038       (+)  Callback function called when DLL ready interrupt occurs
06039       (+)  Callback function called when burst mode period interrupt occurs
06040       (+)  Callback function called when synchronization input interrupt occurs
06041       (+)  Callback function called when a timer register update interrupt occurs
06042       (+)  Callback function called when a timer repetition interrupt occurs
06043       (+)  Callback function called when a compare 1 match interrupt occurs
06044       (+)  Callback function called when a compare 2 match interrupt occurs
06045       (+)  Callback function called when a compare 3 match interrupt occurs
06046       (+)  Callback function called when a compare 4 match interrupt occurs
06047       (+)  Callback function called when a capture 1 interrupt occurs
06048       (+)  Callback function called when a capture 2 interrupt occurs
06049       (+)  Callback function called when a delayed protection interrupt occurs
06050       (+)  Callback function called when a timer counter reset interrupt occurs
06051       (+)  Callback function called when a timer output 1 set interrupt occurs
06052       (+)  Callback function called when a timer output 1 reset interrupt occurs
06053       (+)  Callback function called when a timer output 2 set interrupt occurs
06054       (+)  Callback function called when a timer output 2 reset interrupt occurs
06055       (+)  Callback function called when a timer output 2 reset interrupt occurs
06056       (+)  Callback function called upon completion of a burst DMA transfer
06057
06058 @endverbatim
06059   * @{
06060   */
06061
06062 /**
06063   * @brief  This function handles HRTIM interrupt request.
06064   * @param  hhrtim pointer to HAL HRTIM handle
06065   * @param  TimerIdx Timer index
06066   *                   This parameter can be any value of @ref HRTIM_Timer_Index
06067   * @retval None
06068   */
06069 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
06070                           uint32_t TimerIdx)
06071 {
06072   /* HRTIM interrupts handling */
06073   if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
06074   {
06075     HRTIM_HRTIM_ISR(hhrtim);
06076   }
06077   else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
06078   {
06079     /* Master related interrupts handling */
06080       HRTIM_Master_ISR(hhrtim);
06081   }
06082   else
06083   {
06084     /* Timing unit related interrupts handling */
06085     HRTIM_Timer_ISR(hhrtim, TimerIdx);
06086   }
06087
06088 }
06089
06090 /**
06091   * @brief  Callback function invoked when a fault 1 interrupt occured
06092   * @param  hhrtim pointer to HAL HRTIM handle  * @retval None
06093   * @retval None
06094   */
06095 __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
06096 {
06097   /* Prevent unused argument(s) compilation warning */
06098   UNUSED(hhrtim);
06099
06100   /* NOTE : This function should not be modified, when the callback is needed,
06101             the HAL_HRTIM_Fault1Callback could be implenetd in the user file
06102    */
06103 }
06104
06105 /**
06106   * @brief  Callback function invoked when a fault 2 interrupt occured
06107   * @param  hhrtim pointer to HAL HRTIM handle
06108   * @retval None
06109   */
06110 __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
06111 {
06112   /* Prevent unused argument(s) compilation warning */
06113   UNUSED(hhrtim);
06114
06115   /* NOTE : This function should not be modified, when the callback is needed,
06116             the HAL_HRTIM_Fault2Callback could be implenetd in the user file
06117    */
06118 }
06119
06120 /**
06121   * @brief  Callback function invoked when a fault 3 interrupt occured
06122   * @param  hhrtim pointer to HAL HRTIM handle
06123   * @retval None
06124   */
06125 __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
06126 {
06127   /* Prevent unused argument(s) compilation warning */
06128   UNUSED(hhrtim);
06129
06130   /* NOTE : This function should not be modified, when the callback is needed,
06131             the HAL_HRTIM_Fault3Callback could be implenetd in the user file
06132    */
06133 }
06134
06135 /**
06136   * @brief  Callback function invoked when a fault 4 interrupt occured
06137   * @param  hhrtim pointer to HAL HRTIM handle
06138   * @retval None
06139   */
06140 __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
06141 {
06142   /* Prevent unused argument(s) compilation warning */
06143   UNUSED(hhrtim);
06144
06145   /* NOTE : This function should not be modified, when the callback is needed,
06146             the HAL_HRTIM_Fault4Callback could be implenetd in the user file
06147    */
06148 }
06149
06150 /**
06151   * @brief  Callback function invoked when a fault 5 interrupt occured
06152   * @param  hhrtim pointer to HAL HRTIM handle
06153   * @retval None
06154   */
06155 __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
06156 {
06157   /* Prevent unused argument(s) compilation warning */
06158   UNUSED(hhrtim);
06159
06160   /* NOTE : This function should not be modified, when the callback is needed,
06161             the HAL_HRTIM_Fault5Callback could be implenetd in the user file
06162    */
06163 }
06164
06165 /**
06166   * @brief  Callback function invoked when a system fault interrupt occured
06167   * @param  hhrtim pointer to HAL HRTIM handle
06168   * @retval None
06169   */
06170 __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
06171 {
06172   /* Prevent unused argument(s) compilation warning */
06173   UNUSED(hhrtim);
06174
06175   /* NOTE : This function should not be modified, when the callback is needed,
06176             the HAL_HRTIM_SystemFaultCallback could be implenetd in the user file
06177    */
06178 }
06179
06180 /**
06181   * @brief  Callback function invoked when the DLL calibration is completed
06182   * @param  hhrtim pointer to HAL HRTIM handle
06183   * @retval None
06184   */
06185 __weak void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef * hhrtim)
06186 {
06187   /* Prevent unused argument(s) compilation warning */
06188   UNUSED(hhrtim);
06189
06190   /* NOTE : This function should not be modified, when the callback is needed,
06191             the HAL_HRTIM_DLLCalbrationCallback could be implenetd in the user file
06192    */
06193 }
06194
06195 /**
06196   * @brief  Callback function invoked when the end of the burst mode period is reached
06197   * @param  hhrtim pointer to HAL HRTIM handle
06198   * @retval None
06199   */
06200 __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
06201 {
06202   /* Prevent unused argument(s) compilation warning */
06203   UNUSED(hhrtim);
06204
06205   /* NOTE : This function should not be modified, when the callback is needed,
06206             the HAL_HRTIM_BurstModeCallback could be implenetd in the user file
06207    */
06208 }
06209
06210 /**
06211   * @brief  Callback function invoked when a synchronization input event is received
06212   * @param  hhrtim pointer to HAL HRTIM handle
06213   * @retval None
06214   */
06215 __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
06216 {
06217   /* Prevent unused argument(s) compilation warning */
06218   UNUSED(hhrtim);
06219
06220   /* NOTE : This function should not be modified, when the callback is needed,
06221             the HAL_HRTIM_Master_SynchronizationEventCallback could be implenetd in the user file
06222    */
06223 }
06224
06225 /**
06226   * @brief  Callback function invoked when timer registers are updated
06227   * @param  hhrtim pointer to HAL HRTIM handle
06228   * @param  TimerIdx Timer index
06229   *                   This parameter can be one of the following values:
06230   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
06231   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06232   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06233   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06234   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06235   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06236   * @retval None
06237   */
06238 __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
06239                                               uint32_t TimerIdx)
06240 {
06241   /* Prevent unused argument(s) compilation warning */
06242   UNUSED(hhrtim);
06243   UNUSED(TimerIdx);
06244
06245   /* NOTE : This function should not be modified, when the callback is needed,
06246             the HAL_HRTIM_Master_RegistersUpdateCallback could be implenetd in the user file
06247    */
06248 }
06249
06250 /**
06251   * @brief  Callback function invoked when timer repetition period has elapsed
06252   * @param  hhrtim pointer to HAL HRTIM handle
06253   * @param  TimerIdx Timer index
06254   *                   This parameter can be one of the following values:
06255   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
06256   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06257   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06258   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06259   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06260   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06261   * @retval None
06262   */
06263 __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
06264                                               uint32_t TimerIdx)
06265 {
06266   /* Prevent unused argument(s) compilation warning */
06267   UNUSED(hhrtim);
06268   UNUSED(TimerIdx);
06269
06270   /* NOTE : This function should not be modified, when the callback is needed,
06271             the HAL_HRTIM_Master_RepetitionEventCallback could be implenetd in the user file
06272    */
06273 }
06274
06275 /**
06276   * @brief  Callback function invoked when the timer counter matches the value
06277   *         programmed in the compare 1 register
06278   * @param  hhrtim pointer to HAL HRTIM handle
06279   * @param  TimerIdx Timer index
06280   *                   This parameter can be one of the following values:
06281   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
06282   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06283   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06284   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06285   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06286   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06287   * @retval None
06288   */
06289 __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
06290                                               uint32_t TimerIdx)
06291 {
06292   /* Prevent unused argument(s) compilation warning */
06293   UNUSED(hhrtim);
06294   UNUSED(TimerIdx);
06295
06296   /* NOTE : This function should not be modified, when the callback is needed,
06297             the HAL_HRTIM_Master_Compare1EventCallback could be implenetd in the user file
06298    */
06299 }
06300
06301 /**
06302   * @brief  Callback function invoked when the timer counter matches the value
06303   *         programmed in the compare 2 register
06304   * @param  hhrtim pointer to HAL HRTIM handle
06305   * @retval None
06306   * @param  TimerIdx Timer index
06307   *                   This parameter can be one of the following values:
06308   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
06309   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06310   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06311   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06312   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06313   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06314   */
06315 __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
06316                                               uint32_t TimerIdx)
06317 {
06318   /* Prevent unused argument(s) compilation warning */
06319   UNUSED(hhrtim);
06320   UNUSED(TimerIdx);
06321
06322   /* NOTE : This function should not be modified, when the callback is needed,
06323             the HAL_HRTIM_Master_Compare2EventCallback could be implenetd in the user file
06324    */
06325 }
06326
06327 /**
06328   * @brief  Callback function invoked when the timer counter matches the value
06329   *         programmed in the compare 3 register
06330   * @param  hhrtim pointer to HAL HRTIM handle
06331   * @param  TimerIdx Timer index
06332   *                   This parameter can be one of the following values:
06333   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
06334   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06335   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06336   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06337   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06338   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06339   * @retval None
06340   */
06341 __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
06342                                               uint32_t TimerIdx)
06343 {
06344   /* Prevent unused argument(s) compilation warning */
06345   UNUSED(hhrtim);
06346   UNUSED(TimerIdx);
06347
06348   /* NOTE : This function should not be modified, when the callback is needed,
06349             the HAL_HRTIM_Master_Compare3EventCallback could be implenetd in the user file
06350    */
06351 }
06352
06353 /**
06354   * @brief  Callback function invoked when the timer counter matches the value
06355   *         programmed in the compare 4 register.
06356   * @param  hhrtim pointer to HAL HRTIM handle
06357   * @param  TimerIdx Timer index
06358   *                   This parameter can be one of the following values:
06359   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
06360   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06361   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06362   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06363   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06364   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06365   * @retval None
06366   */
06367 __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
06368                                               uint32_t TimerIdx)
06369 {
06370   /* Prevent unused argument(s) compilation warning */
06371   UNUSED(hhrtim);
06372   UNUSED(TimerIdx);
06373
06374   /* NOTE : This function should not be modified, when the callback is needed,
06375             the HAL_HRTIM_Master_Compare4EventCallback could be implenetd in the user file
06376    */
06377 }
06378
06379 /**
06380   * @brief  Callback function invoked when the timer x capture 1 event occurs
06381   * @param  hhrtim pointer to HAL HRTIM handle
06382   * @param  TimerIdx Timer index
06383   *                   This parameter can be one of the following values:
06384   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06385   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06386   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06387   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06388   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06389   * @retval None
06390   */
06391 __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
06392                                               uint32_t TimerIdx)
06393 {
06394   /* Prevent unused argument(s) compilation warning */
06395   UNUSED(hhrtim);
06396   UNUSED(TimerIdx);
06397
06398   /* NOTE : This function should not be modified, when the callback is needed,
06399             the HAL_HRTIM_Timer_Capture1EventCallback could be implenetd in the user file
06400    */
06401 }
06402
06403 /**
06404   * @brief  Callback function invoked when the timer x capture 2 event occurs
06405   * @param  hhrtim pointer to HAL HRTIM handle
06406   * @param  TimerIdx Timer index
06407   *                   This parameter can be one of the following values:
06408   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06409   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06410   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06411   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06412   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06413   * @retval None
06414   */
06415 __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
06416                                               uint32_t TimerIdx)
06417 {
06418   /* Prevent unused argument(s) compilation warning */
06419   UNUSED(hhrtim);
06420   UNUSED(TimerIdx);
06421
06422   /* NOTE : This function should not be modified, when the callback is needed,
06423             the HAL_HRTIM_Timer_Capture2EventCallback could be implenetd in the user file
06424    */
06425 }
06426
06427 /**
06428   * @brief  Callback function invoked when the delayed idle or balanced idle mode is
06429   *         entered.
06430   * @param  hhrtim pointer to HAL HRTIM handle
06431   * @param  TimerIdx Timer index
06432   *                   This parameter can be one of the following values:
06433   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06434   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06435   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06436   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06437   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06438   * @retval None
06439   */
06440 __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
06441                                               uint32_t TimerIdx)
06442 {
06443   /* Prevent unused argument(s) compilation warning */
06444   UNUSED(hhrtim);
06445   UNUSED(TimerIdx);
06446
06447   /* NOTE : This function should not be modified, when the callback is needed,
06448             the HAL_HRTIM_Timer_DelayedProtectionCallback could be implenetd in the user file
06449    */
06450 }
06451
06452 /**
06453   * @brief  Callback function invoked when the timer x counter reset/roll-over
06454   *         event occurs.
06455   * @param  hhrtim pointer to HAL HRTIM handle
06456   * @param  TimerIdx Timer index
06457   *                   This parameter can be one of the following values:
06458   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06459   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06460   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06461   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06462   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06463   * @retval None
06464   */
06465 __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
06466                                               uint32_t TimerIdx)
06467 {
06468   /* Prevent unused argument(s) compilation warning */
06469   UNUSED(hhrtim);
06470   UNUSED(TimerIdx);
06471
06472   /* NOTE : This function should not be modified, when the callback is needed,
06473             the HAL_HRTIM_Timer_CounterResetCallback could be implenetd in the user file
06474    */
06475 }
06476
06477 /**
06478   * @brief  Callback function invoked when the timer x output 1 is set
06479   * @param  hhrtim pointer to HAL HRTIM handle
06480   * @param  TimerIdx Timer index
06481   *                   This parameter can be one of the following values:
06482   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06483   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06484   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06485   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06486   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06487   * @retval None
06488   */
06489 __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
06490                                               uint32_t TimerIdx)
06491 {
06492   /* Prevent unused argument(s) compilation warning */
06493   UNUSED(hhrtim);
06494   UNUSED(TimerIdx);
06495
06496   /* NOTE : This function should not be modified, when the callback is needed,
06497             the HAL_HRTIM_Timer_Output1SetCallback could be implenetd in the user file
06498    */
06499 }
06500
06501 /**
06502   * @brief  Callback function invoked when the timer x output 1 is reset
06503   * @param  hhrtim pointer to HAL HRTIM handle
06504   * @param  TimerIdx Timer index
06505   *                   This parameter can be one of the following values:
06506   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06507   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06508   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06509   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06510   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06511   * @retval None
06512   */
06513 __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
06514                                               uint32_t TimerIdx)
06515 {
06516   /* Prevent unused argument(s) compilation warning */
06517   UNUSED(hhrtim);
06518   UNUSED(TimerIdx);
06519
06520   /* NOTE : This function should not be modified, when the callback is needed,
06521             the HAL_HRTIM_Timer_Output1ResetCallback could be implenetd in the user file
06522    */
06523 }
06524
06525 /**
06526   * @brief  Callback function invoked when the timer x output 2 is set
06527   * @param  hhrtim pointer to HAL HRTIM handle
06528   * @param  TimerIdx Timer index
06529   *                   This parameter can be one of the following values:
06530   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06531   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06532   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06533   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06534   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06535   * @retval None
06536   */
06537 __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
06538                                               uint32_t TimerIdx)
06539 {
06540   /* Prevent unused argument(s) compilation warning */
06541   UNUSED(hhrtim);
06542   UNUSED(TimerIdx);
06543
06544   /* NOTE : This function should not be modified, when the callback is needed,
06545             the HAL_HRTIM_Timer_Output2SetCallback could be implenetd in the user file
06546    */
06547 }
06548
06549 /**
06550   * @brief  Callback function invoked when the timer x output 2 is reset
06551   * @param  hhrtim pointer to HAL HRTIM handle
06552   * @param  TimerIdx Timer index
06553   *                   This parameter can be one of the following values:
06554   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06555   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06556   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06557   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06558   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06559  * @retval None
06560   */
06561 __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
06562                                               uint32_t TimerIdx)
06563 {
06564   /* Prevent unused argument(s) compilation warning */
06565   UNUSED(hhrtim);
06566   UNUSED(TimerIdx);
06567
06568   /* NOTE : This function should not be modified, when the callback is needed,
06569             the HAL_HRTIM_Timer_Output2ResetCallback could be implenetd in the user file
06570    */
06571 }
06572
06573 /**
06574   * @brief  Callback function invoked when a DMA burst transfer is completed
06575   * @param  hhrtim pointer to HAL HRTIM handle
06576   * @param  TimerIdx Timer index
06577   *                   This parameter can be one of the following values:
06578   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
06579   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06580   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06581   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06582   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06583   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06584   * @retval None
06585   */
06586 __weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
06587                                                uint32_t TimerIdx)
06588 {
06589   /* Prevent unused argument(s) compilation warning */
06590   UNUSED(hhrtim);
06591   UNUSED(TimerIdx);
06592
06593   /* NOTE : This function should not be modified, when the callback is needed,
06594             the HAL_HRTIM_BurstDMATransferCallback could be implenetd in the user file
06595    */
06596 }
06597
06598 /**
06599   * @brief  Callback function invoked when a DMA error occurs
06600   * @param  hhrtim pointer to HAL HRTIM handle
06601   * @retval None
06602   */
06603 __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
06604 {
06605   /* Prevent unused argument(s) compilation warning */
06606   UNUSED(hhrtim);
06607
06608   /* NOTE : This function should not be modified, when the callback is needed,
06609             the HAL_HRTIM_ErrorCallback could be implenetd in the user file
06610    */
06611 }
06612
06613 /**
06614   * @}
06615   */
06616
06617 /**
06618   * @}
06619   */
06620
06621 /** @addtogroup HRTIM_Private_Functions HRTIM Private Functions
06622   * @{
06623   */
06624
06625 /**
06626   * @brief  Configures the master timer time base
06627   * @param  hhrtim pointer to HAL HRTIM handle
06628   * @param  pTimeBaseCfg pointer to the time base configuration structure
06629   * @retval None
06630   */
06631 static void  HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
06632                                      HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
06633 {
06634   uint32_t hrtim_mcr;
06635
06636   /* Configure master timer */
06637   hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
06638
06639   /* Set the prescaler ratio */
06640   hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
06641   hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
06642
06643   /* Set the operating mode */
06644   hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
06645   hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
06646
06647   /* Update the HRTIM registers */
06648   hhrtim->Instance->sMasterRegs.MCR  = hrtim_mcr;
06649   hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
06650   hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
06651 }
06652
06653 /**
06654   * @brief  Configures timing unit (timer A to timer E) time base
06655   * @param  hhrtim pointer to HAL HRTIM handle
06656   * @param  TimerIdx Timer index
06657   * @param  pTimeBaseCfg pointer to the time base configuration structure
06658   * @retval None
06659   */
06660 static void  HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
06661                                          uint32_t TimerIdx ,
06662                                          HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
06663 {
06664   uint32_t hrtim_timcr;
06665
06666   /* Configure master timing unit */
06667   hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
06668
06669   /* Set the prescaler ratio */
06670   hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
06671   hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
06672
06673   /* Set the operating mode */
06674   hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
06675   hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
06676
06677   /* Update the HRTIM registers */
06678   hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR  = hrtim_timcr;
06679   hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
06680   hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
06681 }
06682
06683 /**
06684   * @brief  Configures the master timer in waveform mode
06685   * @param  hhrtim pointer to HAL HRTIM handle
06686   * @param  pTimerCfg pointer to the timer configuration data structure
06687   * @retval None
06688   */
06689 static void  HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
06690                                          HRTIM_TimerCfgTypeDef * pTimerCfg)
06691 {
06692   uint32_t hrtim_mcr;
06693   uint32_t hrtim_bmcr;
06694
06695   /* Configure master timer */
06696   hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
06697   hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
06698
06699   /* Enable/Disable the half mode */
06700   hrtim_mcr &= ~(HRTIM_MCR_HALF);
06701   hrtim_mcr |= pTimerCfg->HalfModeEnable;
06702
06703   /* Enable/Disable the timer start upon synchronization event reception */
06704   hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
06705   hrtim_mcr |= pTimerCfg->StartOnSync;
06706
06707   /* Enable/Disable the timer reset upon synchronization event reception */
06708   hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
06709   hrtim_mcr |= pTimerCfg->ResetOnSync;
06710
06711   /* Enable/Disable the DAC synchronization event generation */
06712   hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
06713   hrtim_mcr |= pTimerCfg->DACSynchro;
06714
06715   /* Enable/Disable preload meachanism for timer registers */
06716   hrtim_mcr &= ~(HRTIM_MCR_PREEN);
06717   hrtim_mcr |= pTimerCfg->PreloadEnable;
06718
06719   /* Master timer registers update handling */
06720   hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
06721   hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
06722
06723   /* Enable/Disable registers update on repetition */
06724   hrtim_mcr &= ~(HRTIM_MCR_MREPU);
06725   hrtim_mcr |= pTimerCfg->RepetitionUpdate;
06726
06727   /* Set the timer burst mode */
06728   hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
06729   hrtim_bmcr |= pTimerCfg->BurstMode;
06730
06731   /* Update the HRTIM registers */
06732   hhrtim->Instance->sMasterRegs.MCR  = hrtim_mcr;
06733   hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
06734 }
06735
06736 /**
06737   * @brief  Configures timing unit (timer A to timer E) in waveform mode
06738   * @param  hhrtim pointer to HAL HRTIM handle
06739   * @param  TimerIdx Timer index
06740   * @param  pTimerCfg pointer to the timer configuration data structure
06741   * @retval None
06742   */
06743 static void  HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
06744                                              uint32_t TimerIdx,
06745                                              HRTIM_TimerCfgTypeDef * pTimerCfg)
06746 {
06747   uint32_t hrtim_timcr;
06748   uint32_t hrtim_timfltr;
06749   uint32_t hrtim_timoutr;
06750   uint32_t hrtim_timrstr;
06751   uint32_t hrtim_bmcr;
06752
06753   /* UPDGAT bitfield must be reset before programming a new value */
06754   hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
06755
06756   /* Configure timing unit (Timer A to Timer E) */
06757   hrtim_timcr   = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
06758   hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
06759   hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
06760   hrtim_timrstr = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR;
06761   hrtim_bmcr    = hhrtim->Instance->sCommonRegs.BMCR;
06762
06763   /* Enable/Disable the half mode */
06764   hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
06765   hrtim_timcr |= pTimerCfg->HalfModeEnable;
06766
06767   /* Enable/Disable the timer start upon synchronization event reception */
06768   hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
06769   hrtim_timcr |= pTimerCfg->StartOnSync;
06770
06771   /* Enable/Disable the timer reset upon synchronization event reception */
06772   hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
06773   hrtim_timcr |= pTimerCfg->ResetOnSync;
06774
06775   /* Enable/Disable the DAC synchronization event generation */
06776   hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
06777   hrtim_timcr |= pTimerCfg->DACSynchro;
06778
06779   /* Enable/Disable preload meachanism for timer registers */
06780   hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
06781   hrtim_timcr |= pTimerCfg->PreloadEnable;
06782
06783   /* Timing unit registers update handling */
06784   hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
06785   hrtim_timcr |= pTimerCfg->UpdateGating;
06786
06787   /* Enable/Disable registers update on repetition */
06788   hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
06789   if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
06790   {
06791     hrtim_timcr |= HRTIM_TIMCR_TREPU;
06792   }
06793
06794   /* Set the push-pull mode */
06795   hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
06796   hrtim_timcr |= pTimerCfg->PushPull;
06797
06798   /* Enable/Disable registers update on timer counter reset */
06799   hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
06800   hrtim_timcr |= pTimerCfg->ResetUpdate;
06801
06802   /* Set the timer update trigger */
06803   hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
06804   hrtim_timcr |= pTimerCfg->UpdateTrigger;
06805
06806
06807   /* Enable/Disable the fault channel at timer level */
06808   hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
06809   hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
06810
06811   /* Lock/Unlock fault sources at timer level */
06812   hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
06813   hrtim_timfltr |= pTimerCfg->FaultLock;
06814
06815   /* The deadtime cannot be used simultaneously with the push-pull mode */
06816   if (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_DISABLED)
06817   {
06818     /* Enable/Disable dead time insertion at timer level */
06819     hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
06820     hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
06821   }
06822
06823   /* Enable/Disable delayed protection at timer level
06824      Delayed Idle is available whatever the timer operating mode (regular, push-pull)
06825      Balanced Idle is only available in push-pull mode
06826   */
06827   if (   ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
06828        && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
06829        || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
06830   {
06831     hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
06832     hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
06833   }
06834
06835   /* Set the timer counter reset trigger */
06836   hrtim_timrstr = pTimerCfg->ResetTrigger;
06837
06838   /* Set the timer burst mode */
06839   switch (TimerIdx)
06840   {
06841   case HRTIM_TIMERINDEX_TIMER_A:
06842     {
06843       hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
06844       hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U);
06845     }
06846     break;
06847   case HRTIM_TIMERINDEX_TIMER_B:
06848     {
06849       hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
06850       hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U);
06851     }
06852     break;
06853   case HRTIM_TIMERINDEX_TIMER_C:
06854     {
06855       hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
06856       hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U);
06857     }
06858     break;
06859   case HRTIM_TIMERINDEX_TIMER_D:
06860     {
06861       hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
06862       hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U);
06863     }
06864     break;
06865   case HRTIM_TIMERINDEX_TIMER_E:
06866     {
06867       hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
06868       hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U);
06869     }
06870     break;
06871   default:
06872     break;
06873   }
06874
06875   /* Update the HRTIM registers */
06876   hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR  = hrtim_timcr;
06877   hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
06878   hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
06879   hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
06880   hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
06881 }
06882
06883 /**
06884   * @brief  Configures a compare unit
06885   * @param  hhrtim pointer to HAL HRTIM handle
06886   * @param  TimerIdx Timer index
06887   * @param  CompareUnit Compare unit identifier
06888   * @param  pCompareCfg pointer to the compare unit configuration data structure
06889   * @retval None
06890   */
06891 static void  HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
06892                                      uint32_t TimerIdx,
06893                                      uint32_t CompareUnit,
06894                                      HRTIM_CompareCfgTypeDef * pCompareCfg)
06895 {
06896   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
06897   {
06898     /* Configure the compare unit of the master timer */
06899     switch (CompareUnit)
06900     {
06901     case HRTIM_COMPAREUNIT_1:
06902       {
06903         hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
06904       }
06905       break;
06906     case HRTIM_COMPAREUNIT_2:
06907       {
06908         hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
06909       }
06910       break;
06911     case HRTIM_COMPAREUNIT_3:
06912       {
06913         hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
06914       }
06915       break;
06916     case HRTIM_COMPAREUNIT_4:
06917       {
06918         hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
06919       }
06920       break;
06921     default:
06922       break;
06923     }
06924   }
06925   else
06926   {
06927     /* Configure the compare unit of the timing unit */
06928     switch (CompareUnit)
06929     {
06930     case HRTIM_COMPAREUNIT_1:
06931       {
06932         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
06933       }
06934       break;
06935     case HRTIM_COMPAREUNIT_2:
06936       {
06937         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
06938       }
06939       break;
06940     case HRTIM_COMPAREUNIT_3:
06941       {
06942         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
06943       }
06944       break;
06945     case HRTIM_COMPAREUNIT_4:
06946       {
06947         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
06948       }
06949       break;
06950     default:
06951       break;
06952     }
06953   }
06954 }
06955
06956 /**
06957   * @brief  Configures a capture unit
06958   * @param  hhrtim pointer to HAL HRTIM handle
06959   * @param  TimerIdx Timer index
06960   * @param  CaptureUnit Capture unit identifier
06961   * @param  Event Event reference
06962   * @retval None
06963   */
06964 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
06965                                     uint32_t TimerIdx,
06966                                     uint32_t CaptureUnit,
06967                                     uint32_t Event)
06968 {
06969   uint32_t CaptureTrigger = 0xFFFFFFFFU;
06970
06971   switch (Event)
06972   {
06973   case HRTIM_EVENT_1:
06974     {
06975       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
06976     }
06977     break;
06978   case HRTIM_EVENT_2:
06979     {
06980       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
06981     }
06982     break;
06983   case HRTIM_EVENT_3:
06984     {
06985       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
06986     }
06987     break;
06988   case HRTIM_EVENT_4:
06989     {
06990       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
06991     }
06992     break;
06993   case HRTIM_EVENT_5:
06994     {
06995       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
06996     }
06997     break;
06998   case HRTIM_EVENT_6:
06999     {
07000       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
07001     }
07002     break;
07003   case HRTIM_EVENT_7:
07004     {
07005       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
07006     }
07007     break;
07008   case HRTIM_EVENT_8:
07009     {
07010       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
07011     }
07012     break;
07013   case HRTIM_EVENT_9:
07014     {
07015       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
07016     }
07017     break;
07018   case HRTIM_EVENT_10:
07019     {
07020       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
07021     }
07022     break;
07023   default:
07024     break;
07025   }
07026
07027   switch (CaptureUnit)
07028   {
07029   case HRTIM_CAPTUREUNIT_1:
07030     {
07031       hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
07032     }
07033     break;
07034   case HRTIM_CAPTUREUNIT_2:
07035     {
07036       hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
07037     }
07038     break;
07039   default:
07040     break;
07041   }
07042 }
07043
07044 /**
07045   * @brief  Configures the output of a timing unit
07046   * @param  hhrtim pointer to HAL HRTIM handle
07047   * @param  TimerIdx Timer index
07048   * @param  Output timing unit output identifier
07049   * @param  pOutputCfg pointer to the output configuration data structure
07050   * @retval None
07051   */
07052 static void  HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
07053                                 uint32_t TimerIdx,
07054                                 uint32_t Output,
07055                                 HRTIM_OutputCfgTypeDef * pOutputCfg)
07056 {
07057   uint32_t hrtim_outr;
07058   uint32_t hrtim_dtr;
07059
07060   uint32_t shift = 0xFFFFFFFFU;
07061
07062   hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
07063   hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
07064
07065   switch (Output)
07066   {
07067   case HRTIM_OUTPUT_TA1:
07068   case HRTIM_OUTPUT_TB1:
07069   case HRTIM_OUTPUT_TC1:
07070   case HRTIM_OUTPUT_TD1:
07071   case HRTIM_OUTPUT_TE1:
07072     {
07073       /* Set the output set/reset crossbar */
07074       hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
07075       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
07076
07077       shift = 0U;
07078     }
07079     break;
07080   case HRTIM_OUTPUT_TA2:
07081   case HRTIM_OUTPUT_TB2:
07082   case HRTIM_OUTPUT_TC2:
07083   case HRTIM_OUTPUT_TD2:
07084   case HRTIM_OUTPUT_TE2:
07085     {
07086       /* Set the output set/reset crossbar */
07087       hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
07088       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
07089
07090       shift = 16U;
07091     }
07092     break;
07093   default:
07094     break;
07095   }
07096
07097   /* Clear output config */
07098   hrtim_outr &= ~((HRTIM_OUTR_POL1 |
07099                    HRTIM_OUTR_IDLM1 |
07100                    HRTIM_OUTR_IDLES1|
07101                    HRTIM_OUTR_FAULT1|
07102                    HRTIM_OUTR_CHP1 |
07103                    HRTIM_OUTR_DIDL1)  << shift);
07104
07105   /* Set the polarity */
07106   hrtim_outr |= (pOutputCfg->Polarity << shift);
07107
07108   /* Set the IDLE mode */
07109   hrtim_outr |= (pOutputCfg->IdleMode << shift);
07110
07111   /* Set the IDLE state */
07112   hrtim_outr |= (pOutputCfg->IdleLevel << shift);
07113
07114   /* Set the FAULT state */
07115   hrtim_outr |= (pOutputCfg->FaultLevel << shift);
07116
07117   /* Set the chopper mode */
07118   hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
07119
07120   /* Set the burst mode entry mode : deadtime insertion when entering the idle
07121      state during a burst mode operation is allowed only under the following
07122      conditions:
07123      - the outputs is active during the burst mode (IDLES=1U)
07124      - positive deadtimes (SDTR/SDTF set to 0U)
07125   */
07126   if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
07127       ((hrtim_dtr & HRTIM_DTR_SDTR) == RESET) &&
07128       ((hrtim_dtr & HRTIM_DTR_SDTF) == RESET))
07129   {
07130     hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
07131   }
07132
07133   /* Update HRTIM register */
07134   hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
07135 }
07136
07137 /**
07138   * @brief  Configures an external event channel
07139   * @param  hhrtim pointer to HAL HRTIM handle
07140   * @param  Event Event channel identifier
07141   * @param  pEventCfg pointer to the event channel configuration data structure
07142   * @retval None
07143   */
07144 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
07145                               uint32_t Event,
07146                               HRTIM_EventCfgTypeDef *pEventCfg)
07147 {
07148   uint32_t hrtim_eecr1;
07149   uint32_t hrtim_eecr2;
07150   uint32_t hrtim_eecr3;
07151
07152   /* Configure external event channel */
07153   hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
07154   hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
07155   hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
07156
07157   switch (Event)
07158   {
07159   case HRTIM_EVENT_1:
07160     {
07161       hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
07162       hrtim_eecr1 |= pEventCfg->Source;
07163       hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
07164       hrtim_eecr1 |= pEventCfg->Sensitivity;
07165       /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
07166       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
07167       /* Update the HRTIM registers (EE1FAST bit) */
07168       hrtim_eecr1 |= pEventCfg->FastMode;
07169       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
07170     }
07171     break;
07172   case HRTIM_EVENT_2:
07173     {
07174       hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
07175       hrtim_eecr1 |= (pEventCfg->Source << 6U);
07176       hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & (HRTIM_EECR1_EE2POL));
07177       hrtim_eecr1 |= (pEventCfg->Sensitivity << 6U);
07178       /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
07179       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
07180       /* Update the HRTIM registers (EE2FAST bit) */
07181       hrtim_eecr1 |= (pEventCfg->FastMode << 6U);
07182       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
07183     }
07184     break;
07185   case HRTIM_EVENT_3:
07186     {
07187       hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
07188       hrtim_eecr1 |= (pEventCfg->Source << 12U);
07189       hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & (HRTIM_EECR1_EE3POL));
07190       hrtim_eecr1 |= (pEventCfg->Sensitivity << 12U);
07191       /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
07192       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
07193       /* Update the HRTIM registers (EE3FAST bit) */
07194       hrtim_eecr1 |= (pEventCfg->FastMode << 12U);
07195       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
07196     }
07197     break;
07198   case HRTIM_EVENT_4:
07199     {
07200       hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
07201       hrtim_eecr1 |= (pEventCfg->Source << 18U);
07202       hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & (HRTIM_EECR1_EE4POL));
07203       hrtim_eecr1 |= (pEventCfg->Sensitivity << 18U);
07204       /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
07205       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
07206       /* Update the HRTIM registers (EE4FAST bit) */
07207       hrtim_eecr1 |= (pEventCfg->FastMode << 18U);
07208       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
07209     }
07210     break;
07211   case HRTIM_EVENT_5:
07212     {
07213       hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
07214       hrtim_eecr1 |= (pEventCfg->Source << 24U);
07215       hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & (HRTIM_EECR1_EE5POL));
07216       hrtim_eecr1 |= (pEventCfg->Sensitivity << 24U);
07217       /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
07218       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
07219       /* Update the HRTIM registers (EE5FAST bit) */
07220       hrtim_eecr1 |= (pEventCfg->FastMode << 24U);
07221       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
07222     }
07223     break;
07224   case HRTIM_EVENT_6:
07225     {
07226       hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
07227       hrtim_eecr2 |= pEventCfg->Source;
07228       hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
07229       hrtim_eecr2 |= pEventCfg->Sensitivity;
07230       hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
07231       hrtim_eecr3 |= pEventCfg->Filter;
07232       /* Update the HRTIM registers */
07233       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
07234       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
07235     }
07236     break;
07237   case HRTIM_EVENT_7:
07238     {
07239       hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
07240       hrtim_eecr2 |= (pEventCfg->Source << 6U);
07241       hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & (HRTIM_EECR2_EE7POL));
07242       hrtim_eecr2 |= (pEventCfg->Sensitivity << 6U);
07243       hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
07244       hrtim_eecr3 |= (pEventCfg->Filter << 6U);
07245       /* Update the HRTIM registers */
07246       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
07247       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
07248     }
07249     break;
07250   case HRTIM_EVENT_8:
07251     {
07252       hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
07253       hrtim_eecr2 |= (pEventCfg->Source << 12U);
07254       hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & (HRTIM_EECR2_EE8POL));
07255       hrtim_eecr2 |= (pEventCfg->Sensitivity << 12U);
07256       hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
07257       hrtim_eecr3 |= (pEventCfg->Filter << 12U);
07258       /* Update the HRTIM registers */
07259       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
07260       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
07261     }
07262     break;
07263   case HRTIM_EVENT_9:
07264     {
07265       hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
07266       hrtim_eecr2 |= (pEventCfg->Source << 18U);
07267       hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & (HRTIM_EECR2_EE9POL));
07268       hrtim_eecr2 |= (pEventCfg->Sensitivity << 18U);
07269       hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
07270       hrtim_eecr3 |= (pEventCfg->Filter << 18U);
07271       /* Update the HRTIM registers */
07272       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
07273       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
07274     }
07275     break;
07276   case HRTIM_EVENT_10:
07277     {
07278       hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
07279       hrtim_eecr2 |= (pEventCfg->Source << 24U);
07280       hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & (HRTIM_EECR2_EE10POL));
07281       hrtim_eecr2 |= (pEventCfg->Sensitivity << 24U);
07282       hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
07283       hrtim_eecr3 |= (pEventCfg->Filter << 24U);
07284       /* Update the HRTIM registers */
07285       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
07286       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
07287     }
07288     break;
07289   default:
07290     break;
07291   }
07292 }
07293
07294 /**
07295   * @brief  Configures the timer counter reset
07296   * @param  hhrtim pointer to HAL HRTIM handle
07297   * @param  TimerIdx Timer index
07298   * @param  Event Event channel identifier
07299   * @retval None
07300   */
07301 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
07302                                   uint32_t TimerIdx,
07303                                   uint32_t Event)
07304 {
07305   switch (Event)
07306   {
07307   case HRTIM_EVENT_1:
07308     {
07309       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
07310     }
07311     break;
07312   case HRTIM_EVENT_2:
07313     {
07314       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
07315     }
07316     break;
07317   case HRTIM_EVENT_3:
07318     {
07319       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
07320     }
07321     break;
07322   case HRTIM_EVENT_4:
07323     {
07324       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
07325     }
07326     break;
07327   case HRTIM_EVENT_5:
07328     {
07329       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
07330     }
07331     break;
07332   case HRTIM_EVENT_6:
07333     {
07334       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
07335     }
07336     break;
07337   case HRTIM_EVENT_7:
07338     {
07339       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
07340     }
07341     break;
07342   case HRTIM_EVENT_8:
07343     {
07344       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
07345     }
07346     break;
07347   case HRTIM_EVENT_9:
07348     {
07349       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
07350     }
07351     break;
07352   case HRTIM_EVENT_10:
07353     {
07354       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
07355     }
07356     break;
07357   default:
07358     break;
07359   }
07360 }
07361
07362 /**
07363   * @brief  Returns the interrupt to enable or disable according to the
07364   *         OC mode.
07365   * @param  hhrtim pointer to HAL HRTIM handle
07366   * @param  TimerIdx Timer index
07367   * @param  OCChannel Timer output
07368   *                    This parameter can be one of the following values:
07369   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
07370   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
07371   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
07372   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
07373   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
07374   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
07375   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
07376   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
07377   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
07378   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
07379   * @retval Interrupt to enable or disable
07380   */
07381 static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
07382                                       uint32_t TimerIdx,
07383                                       uint32_t OCChannel)
07384 {
07385   uint32_t hrtim_set;
07386   uint32_t hrtim_reset;
07387   uint32_t interrupt = 0U;
07388
07389   switch (OCChannel)
07390   {
07391   case HRTIM_OUTPUT_TA1:
07392   case HRTIM_OUTPUT_TB1:
07393   case HRTIM_OUTPUT_TC1:
07394   case HRTIM_OUTPUT_TD1:
07395   case HRTIM_OUTPUT_TE1:
07396     {
07397       /* Retreives actual OC mode and set interrupt accordingly */
07398       hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
07399       hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
07400
07401       if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
07402           ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
07403       {
07404         /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
07405         interrupt = HRTIM_TIM_IT_CMP1;
07406       }
07407       else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
07408                (hrtim_reset  == 0U))
07409       {
07410          /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
07411         interrupt = HRTIM_TIM_IT_SET1;
07412       }
07413       else if ((hrtim_set == 0U) &&
07414                ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
07415       {
07416          /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
07417         interrupt = HRTIM_TIM_IT_RST1;
07418       }
07419     }
07420     break;
07421   case HRTIM_OUTPUT_TA2:
07422   case HRTIM_OUTPUT_TB2:
07423   case HRTIM_OUTPUT_TC2:
07424   case HRTIM_OUTPUT_TD2:
07425   case HRTIM_OUTPUT_TE2:
07426     {
07427       /* Retreives actual OC mode and set interrupt accordingly */
07428       hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
07429       hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
07430
07431       if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
07432           ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
07433       {
07434         /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
07435         interrupt = HRTIM_TIM_IT_CMP2;
07436       }
07437       else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
07438                (hrtim_reset  == 0U))
07439       {
07440          /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
07441         interrupt = HRTIM_TIM_IT_SET2;
07442       }
07443       else if ((hrtim_set == 0U) &&
07444                ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
07445       {
07446          /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
07447         interrupt = HRTIM_TIM_IT_RST2;
07448       }
07449     }
07450     break;
07451   default:
07452     break;
07453   }
07454
07455   return interrupt;
07456 }
07457
07458 /**
07459   * @brief  Returns the DMA request to enable or disable according to the
07460   *         OC mode.
07461   * @param  hhrtim pointer to HAL HRTIM handle
07462   * @param  TimerIdx Timer index
07463   * @param  OCChannel Timer output
07464   *                    This parameter can be one of the following values:
07465   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
07466   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
07467   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
07468   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
07469   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
07470   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
07471   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
07472   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
07473   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
07474   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
07475   * @retval DMA request to enable or disable
07476   */
07477 static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
07478                                        uint32_t TimerIdx,
07479                                        uint32_t OCChannel)
07480 {
07481   uint32_t hrtim_set;
07482   uint32_t hrtim_reset;
07483   uint32_t dma_request = 0U;
07484
07485   switch (OCChannel)
07486   {
07487   case HRTIM_OUTPUT_TA1:
07488   case HRTIM_OUTPUT_TB1:
07489   case HRTIM_OUTPUT_TC1:
07490   case HRTIM_OUTPUT_TD1:
07491   case HRTIM_OUTPUT_TE1:
07492     {
07493       /* Retreives actual OC mode and set dma_request accordingly */
07494       hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
07495       hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
07496
07497       if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
07498           ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
07499       {
07500         /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
07501         dma_request = HRTIM_TIM_DMA_CMP1;
07502       }
07503       else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
07504                (hrtim_reset  == 0U))
07505       {
07506          /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
07507         dma_request = HRTIM_TIM_DMA_SET1;
07508       }
07509       else if ((hrtim_set == 0U) &&
07510                ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
07511       {
07512          /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
07513         dma_request = HRTIM_TIM_DMA_RST1;
07514       }
07515     }
07516     break;
07517   case HRTIM_OUTPUT_TA2:
07518   case HRTIM_OUTPUT_TB2:
07519   case HRTIM_OUTPUT_TC2:
07520   case HRTIM_OUTPUT_TD2:
07521   case HRTIM_OUTPUT_TE2:
07522     {
07523       /* Retreives actual OC mode and set dma_request accordingly */
07524       hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
07525       hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
07526
07527       if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
07528           ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
07529       {
07530         /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
07531         dma_request = HRTIM_TIM_DMA_CMP2;
07532       }
07533       else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
07534                (hrtim_reset  == 0U))
07535       {
07536          /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
07537         dma_request = HRTIM_TIM_DMA_SET2;
07538       }
07539       else if ((hrtim_set == 0U) &&
07540                ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
07541       {
07542          /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
07543         dma_request = HRTIM_TIM_DMA_RST2;
07544       }
07545     }
07546     break;
07547   default:
07548     break;
07549   }
07550
07551   return dma_request;
07552 }
07553
07554 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
07555                                                           uint32_t TimerIdx)
07556 {
07557   DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL;
07558
07559   switch (TimerIdx)
07560   {
07561   case HRTIM_TIMERINDEX_MASTER:
07562     {
07563       hdma = hhrtim->hdmaMaster;
07564     }
07565     break;
07566   case HRTIM_TIMERINDEX_TIMER_A:
07567     {
07568       hdma = hhrtim->hdmaTimerA;
07569     }
07570     break;
07571   case HRTIM_TIMERINDEX_TIMER_B:
07572     {
07573       hdma = hhrtim->hdmaTimerB;
07574     }
07575     break;
07576   case HRTIM_TIMERINDEX_TIMER_C:
07577     {
07578       hdma = hhrtim->hdmaTimerC;
07579     }
07580     break;
07581   case HRTIM_TIMERINDEX_TIMER_D:
07582     {
07583       hdma = hhrtim->hdmaTimerD;
07584     }
07585     break;
07586   case HRTIM_TIMERINDEX_TIMER_E:
07587     {
07588       hdma = hhrtim->hdmaTimerE;
07589     }
07590     break;
07591   default:
07592     break;
07593   }
07594
07595   return hdma;
07596 }
07597
07598 static uint32_t GetTimerIdxFromDMAHandle(DMA_HandleTypeDef *hdma)
07599 {
07600   uint32_t timed_idx = 0xFFFFFFFFU;
07601
07602   if (hdma->Instance ==  DMA1_Channel2)
07603   {
07604     timed_idx = HRTIM_TIMERINDEX_MASTER;
07605   }
07606   else if (hdma->Instance ==  DMA1_Channel3)
07607   {
07608     timed_idx = HRTIM_TIMERINDEX_TIMER_A;
07609   }
07610   else if (hdma->Instance ==  DMA1_Channel4)
07611   {
07612     timed_idx = HRTIM_TIMERINDEX_TIMER_B;
07613   }
07614   else if (hdma->Instance ==  DMA1_Channel5)
07615   {
07616     timed_idx = HRTIM_TIMERINDEX_TIMER_C;
07617   }
07618   else if (hdma->Instance ==  DMA1_Channel6)
07619   {
07620     timed_idx = HRTIM_TIMERINDEX_TIMER_D;
07621   }
07622   else if (hdma->Instance ==  DMA1_Channel7)
07623   {
07624     timed_idx = HRTIM_TIMERINDEX_TIMER_E;
07625   }
07626
07627   return timed_idx;
07628 }
07629
07630 /**
07631   * @brief  Forces an immediate transfer from the preload to the active
07632   *         registers.
07633   * @param  hhrtim pointer to HAL HRTIM handle
07634   * @param  TimerIdx Timer index
07635   * @retval None
07636   */
07637 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
07638                                        uint32_t TimerIdx)
07639 {
07640   switch (TimerIdx)
07641   {
07642   case HRTIM_TIMERINDEX_MASTER:
07643     {
07644       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
07645     }
07646     break;
07647   case HRTIM_TIMERINDEX_TIMER_A:
07648     {
07649       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
07650     }
07651     break;
07652   case HRTIM_TIMERINDEX_TIMER_B:
07653     {
07654       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
07655     }
07656     break;
07657   case HRTIM_TIMERINDEX_TIMER_C:
07658     {
07659       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
07660     }
07661     break;
07662   case HRTIM_TIMERINDEX_TIMER_D:
07663     {
07664       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
07665     }
07666     break;
07667   case HRTIM_TIMERINDEX_TIMER_E:
07668     {
07669       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
07670     }
07671     break;
07672   default:
07673     break;
07674   }
07675 }
07676
07677
07678 /**
07679   * @brief  HRTIM interrupts service routine
07680   * @param  hhrtim pointer to HAL HRTIM handle
07681   * @retval None
07682   */
07683 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
07684 {
07685   /* Fault 1 event */
07686   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT1) != RESET)
07687   {
07688     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT1) != RESET)
07689     {
07690       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
07691
07692       /* Invoke Fault 1 event callback */
07693       HAL_HRTIM_Fault1Callback(hhrtim);
07694     }
07695   }
07696
07697   /* Fault 2 event */
07698   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT2) != RESET)
07699   {
07700     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT2) != RESET)
07701     {
07702       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
07703
07704       /* Invoke Fault 2 event callback */
07705       HAL_HRTIM_Fault2Callback(hhrtim);
07706     }
07707   }
07708
07709   /* Fault 3 event */
07710   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT3) != RESET)
07711   {
07712     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT3) != RESET)
07713     {
07714       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
07715
07716       /* Invoke Fault 3 event callback */
07717       HAL_HRTIM_Fault3Callback(hhrtim);
07718     }
07719   }
07720
07721   /* Fault 4 event */
07722   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT4) != RESET)
07723   {
07724     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT4) != RESET)
07725     {
07726       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
07727
07728       /* Invoke Fault 4 event callback */
07729       HAL_HRTIM_Fault4Callback(hhrtim);
07730     }
07731   }
07732
07733   /* Fault 5 event */
07734   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT5) != RESET)
07735   {
07736     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT5) != RESET)
07737     {
07738       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
07739
07740       /* Invoke Fault 5 event callback */
07741       HAL_HRTIM_Fault5Callback(hhrtim);
07742     }
07743   }
07744
07745   /* System fault event */
07746   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_SYSFLT) != RESET)
07747   {
07748     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_SYSFLT) != RESET)
07749     {
07750       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
07751
07752       /* Invoke System fault event callback */
07753       HAL_HRTIM_SystemFaultCallback(hhrtim);
07754     }
07755   }
07756 }
07757
07758 /**
07759 * @brief  Master timer interrupts service routine
07760 * @param  hhrtim pointer to HAL HRTIM handle
07761 * @retval None
07762 */
07763 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
07764 {
07765   /* DLL calibration ready event */
07766   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_DLLRDY) != RESET)
07767   {
07768     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_DLLRDY) != RESET)
07769     {
07770       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_DLLRDY);
07771
07772       /* Set HRTIM State */
07773       hhrtim->State = HAL_HRTIM_STATE_READY;
07774
07775       /* Process unlocked */
07776       __HAL_UNLOCK(hhrtim);
07777
07778       /* Invoke System fault event callback */
07779       HAL_HRTIM_DLLCalbrationReadyCallback(hhrtim);
07780     }
07781   }
07782
07783   /* Burst mode period event */
07784   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_BMPER) != RESET)
07785   {
07786     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_BMPER) != RESET)
07787     {
07788       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
07789
07790       /* Invoke Burst mode period event callback */
07791       HAL_HRTIM_BurstModePeriodCallback(hhrtim);
07792     }
07793   }
07794
07795   /* Master timer compare 1 event */
07796   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP1) != RESET)
07797   {
07798     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP1) != RESET)
07799     {
07800       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
07801
07802       /* Invoke compare 1 event callback */
07803       HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
07804     }
07805   }
07806
07807   /* Master timer compare 2 event */
07808   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP2) != RESET)
07809   {
07810     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP2) != RESET)
07811     {
07812       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
07813
07814       /* Invoke compare 2 event callback */
07815       HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
07816     }
07817   }
07818
07819   /* Master timer compare 3 event */
07820   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP3) != RESET)
07821   {
07822     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP3) != RESET)
07823     {
07824       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
07825
07826       /* Invoke compare 3 event callback */
07827       HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
07828     }
07829   }
07830
07831   /* Master timer compare 4 event */
07832   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP4) != RESET)
07833   {
07834     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP4) != RESET)
07835     {
07836       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
07837
07838       /* Invoke compare 4 event callback */
07839       HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
07840     }
07841   }
07842
07843   /* Master timer repetition event */
07844   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MREP) != RESET)
07845   {
07846     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MREP) != RESET)
07847     {
07848       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
07849
07850       /* Invoke repetition event callback */
07851       HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
07852     }
07853   }
07854
07855   /* Synchronization input event */
07856   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_SYNC) != RESET)
07857   {
07858     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_SYNC) != RESET)
07859     {
07860       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
07861
07862       /* Invoke synchronization event callback */
07863       HAL_HRTIM_SynchronizationEventCallback(hhrtim);
07864     }
07865   }
07866
07867   /* Master timer registers update event */
07868   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MUPD) != RESET)
07869   {
07870     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MUPD) != RESET)
07871     {
07872       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
07873
07874       /* Invoke registers update event callback */
07875       HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
07876     }
07877   }
07878 }
07879
07880 /**
07881   * @brief  Timer interrupts service routine
07882   * @param  hhrtim pointer to HAL HRTIM handle
07883   * @param  TimerIdx Timer index
07884   *                   This parameter can be one of the following values:
07885   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
07886   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
07887   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
07888   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
07889   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
07890   * @retval None
07891 */
07892 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
07893                      uint32_t TimerIdx)
07894 {
07895   /* Timer compare 1 event */
07896   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP1) != RESET)
07897   {
07898     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1) != RESET)
07899     {
07900       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
07901
07902       /* Invoke compare 1 event callback */
07903       HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
07904     }
07905   }
07906
07907   /* Timer compare 2 event */
07908   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP2) != RESET)
07909   {
07910     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2) != RESET)
07911     {
07912       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
07913
07914       /* Invoke compare 2 event callback */
07915       HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
07916     }
07917   }
07918
07919   /* Timer compare 3 event */
07920   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP3) != RESET)
07921   {
07922     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3) != RESET)
07923     {
07924       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
07925
07926       /* Invoke compare 3 event callback */
07927       HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
07928     }
07929   }
07930
07931   /* Timer compare 4 event */
07932   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP4) != RESET)
07933   {
07934     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4) != RESET)
07935     {
07936       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
07937
07938       /* Invoke compare 4 event callback */
07939       HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
07940     }
07941   }
07942
07943   /* Timer repetition event */
07944   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_REP) != RESET)
07945   {
07946     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_REP) != RESET)
07947     {
07948       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
07949
07950       /* Invoke repetition event callback */
07951       HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
07952     }
07953   }
07954
07955   /* Timer registers update event */
07956   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_UPD) != RESET)
07957   {
07958     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD) != RESET)
07959     {
07960       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
07961
07962       /* Invoke registers update event callback */
07963       HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
07964     }
07965   }
07966
07967   /* Timer capture 1 event */
07968   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT1) != RESET)
07969   {
07970     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1) != RESET)
07971     {
07972       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
07973
07974       /* Invoke capture 1 event callback */
07975       HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
07976     }
07977   }
07978
07979   /* Timer capture 2 event */
07980   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT2) != RESET)
07981   {
07982     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2) != RESET)
07983     {
07984       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
07985
07986       /* Invoke capture 2 event callback */
07987       HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
07988     }
07989   }
07990
07991   /* Timer ouput 1 set event */
07992   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET1) != RESET)
07993   {
07994     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1) != RESET)
07995     {
07996       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
07997
07998       /* Invoke ouput 1 set event callback */
07999       HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
08000     }
08001   }
08002
08003   /* Timer ouput 1 reset event */
08004   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST1) != RESET)
08005   {
08006     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1) != RESET)
08007     {
08008       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
08009
08010       /* Invoke ouput 1 reset event callback */
08011       HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
08012     }
08013   }
08014
08015   /* Timer ouput 2 set event */
08016   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET2) != RESET)
08017   {
08018     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2) != RESET)
08019     {
08020       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
08021
08022       /* Invoke ouput 2 set event callback */
08023       HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
08024     }
08025   }
08026
08027   /* Timer ouput 2 reset event */
08028   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST2) != RESET)
08029   {
08030     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2) != RESET)
08031     {
08032       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
08033
08034       /* Invoke ouput 2 reset event callback */
08035       HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
08036     }
08037   }
08038
08039   /* Timer reset event */
08040   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST) != RESET)
08041   {
08042     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST) != RESET)
08043     {
08044       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
08045
08046       /* Invoke timer reset callback */
08047       HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
08048     }
08049   }
08050
08051   /* Delayed protection event */
08052   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_DLYPRT) != RESET)
08053   {
08054     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT) != RESET)
08055     {
08056       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
08057
08058       /* Invoke delayed protection callback */
08059       HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
08060     }
08061   }
08062 }
08063
08064 /**
08065   * @brief  DMA callback invoked upon master timer related DMA request completion
08066   * @param  hdma pointer to DMA handle.
08067   * @retval None
08068   */
08069 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
08070 {
08071   HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
08072
08073   if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != RESET)
08074   {
08075     HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
08076   }
08077   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != RESET)
08078   {
08079     HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
08080   }
08081   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != RESET)
08082   {
08083     HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
08084   }
08085   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != RESET)
08086   {
08087     HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
08088   }
08089   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != RESET)
08090   {
08091     HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
08092   }
08093   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != RESET)
08094   {
08095     HAL_HRTIM_SynchronizationEventCallback(hrtim);
08096   }
08097   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != RESET)
08098   {
08099     HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
08100   }
08101 }
08102
08103 /**
08104   * @brief  DMA callback invoked upon timer A..E related DMA request completion
08105   * @param  hdma pointer to DMA handle.
08106   * @retval None
08107   */
08108 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
08109 {
08110   uint8_t timer_idx;
08111
08112   HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
08113
08114   timer_idx = GetTimerIdxFromDMAHandle(hdma);
08115
08116   if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != RESET)
08117   {
08118     HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
08119   }
08120   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != RESET)
08121   {
08122     HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
08123   }
08124   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != RESET)
08125   {
08126     HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
08127   }
08128   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != RESET)
08129   {
08130     HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
08131   }
08132   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != RESET)
08133   {
08134     HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
08135   }
08136   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != RESET)
08137   {
08138     HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
08139   }
08140   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != RESET)
08141   {
08142     HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
08143   }
08144   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != RESET)
08145   {
08146     HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
08147   }
08148   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != RESET)
08149   {
08150     HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
08151   }
08152   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != RESET)
08153   {
08154     HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
08155   }
08156   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != RESET)
08157   {
08158     HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
08159   }
08160   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != RESET)
08161   {
08162     HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
08163   }
08164   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != RESET)
08165   {
08166     HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
08167   }
08168   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != RESET)
08169   {
08170     HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
08171   }
08172   else
08173           return;
08174 }
08175
08176 /**
08177 * @brief  DMA error callback
08178 * @param  hdma pointer to DMA handle.
08179 * @retval None
08180 */
08181 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
08182 {
08183   HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
08184
08185   HAL_HRTIM_ErrorCallback(hrtim);
08186 }
08187
08188 /**
08189   * @brief  DMA callback invoked upon burst DMA transfer completion
08190   * @param  hdma pointer to DMA handle.
08191   * @retval None
08192   */
08193 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
08194 {
08195   HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
08196
08197   HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hdma));
08198 }
08199
08200 /**
08201   * @}
08202   */
08203
08204 /**
08205   * @}
08206   */
08207 #endif /* STM32F334x8 */
08208
08209 #endif /* HAL_HRTIM_MODULE_ENABLED */
08210
08211 /**
08212   * @}
08213   */
08214
08215 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
08216
08217
08218
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_hrtim.h Source File

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stm32f3xx_hal_hrtim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_hrtim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of HRTIM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_HRTIM_H
00038 #define __STM32F3xx_HAL_HRTIM_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 #if defined(STM32F334x8)
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f3xx_hal_def.h"
00048
00049 /** @addtogroup STM32F3xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup HRTIM HRTIM
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants
00059   * @{
00060   */
00061 /** @defgroup HRTIM_Max_Timer HRTIM Max Timer
00062   * @{
00063   */
00064 #define MAX_HRTIM_TIMER 6U
00065 /**
00066   * @}
00067   */
00068 /**
00069   * @}
00070   */
00071
00072 /** @defgroup HRTIM_Exported_Types HRTIM Exported Types
00073   * @{
00074   */
00075
00076 /**
00077   * @brief  HRTIM Configuration Structure definition - Time base related parameters
00078   */
00079 typedef struct
00080 {
00081   uint32_t HRTIMInterruptResquests;  /*!< Specifies which interrupts requests must enabled for the HRTIM instance.
00082                                           This parameter can be any combination of  @ref HRTIM_Common_Interrupt_Enable */
00083   uint32_t SyncOptions;              /*!< Specifies how the HRTIM instance handles the external synchronization signals.
00084                                           The HRTIM instance can be configured to act as a slave (waiting for a trigger
00085                                                                                   to be synchronized) or a master (generating a synchronization signal) or both.
00086                                           This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/
00087   uint32_t SyncInputSource;          /*!< Specifies the external synchronization input source (significant only when
00088                                           the HRTIM instance is configured as a slave).
00089                                           This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */
00090   uint32_t SyncOutputSource;         /*!< Specifies the source and event to be sent on the external synchronization outputs
00091                                          (significant only when the HRTIM instance is configured as a master).
00092                                           This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
00093   uint32_t SyncOutputPolarity;       /*!< Specifies the conditioning of the event to be sent on the external synchronization
00094                                           outputs (significant only when the HRTIM instance is configured as a master).
00095                                           This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
00096 } HRTIM_InitTypeDef;
00097
00098 /**
00099   * @brief  HAL State structures definition
00100   */
00101 typedef enum
00102 {
00103   HAL_HRTIM_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
00104   HAL_HRTIM_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
00105   HAL_HRTIM_STATE_TIMEOUT    = 0x06U,    /*!< Timeout state                                      */
00106   HAL_HRTIM_STATE_ERROR      = 0x07U,    /*!< Error state                                        */
00107 } HAL_HRTIM_StateTypeDef;
00108
00109 /**
00110   * @brief HRTIM Timer Structure definition
00111   */
00112 typedef struct
00113 {
00114   uint32_t CaptureTrigger1;       /*!< Event(s) triggering capture unit 1.
00115                                        When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
00116                                        When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
00117   uint32_t CaptureTrigger2;       /*!< Event(s) triggering capture unit 2.
00118                                        When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
00119                                        When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
00120   uint32_t InterruptRequests;     /*!< Interrupts requests enabled for the timer. */
00121   uint32_t DMARequests;           /*!< DMA requests enabled for the timer. */
00122   uint32_t DMASrcAddress;          /*!< Address of the source address of the DMA transfer. */
00123   uint32_t DMADstAddress;          /*!< Address of the destination address of the DMA transfer. */
00124   uint32_t DMASize;                /*!< Size of the DMA transfer */
00125 } HRTIM_TimerParamTypeDef;
00126
00127 /**
00128   * @brief  HRTIM Handle Structure definition
00129   */
00130 typedef struct __HRTIM_HandleTypeDef
00131 {
00132   HRTIM_TypeDef *              Instance;                     /*!< Register base address */
00133
00134   HRTIM_InitTypeDef            Init;                         /*!< HRTIM required parameters */
00135
00136   HRTIM_TimerParamTypeDef      TimerParam[MAX_HRTIM_TIMER];  /*!< HRTIM timers - including the master - parameters */
00137
00138   HAL_LockTypeDef              Lock;                         /*!< Locking object          */
00139
00140   __IO HAL_HRTIM_StateTypeDef  State;                        /*!< HRTIM communication state */
00141
00142   DMA_HandleTypeDef *          hdmaMaster;                   /*!< Master timer DMA handle parameters */
00143   DMA_HandleTypeDef *          hdmaTimerA;                   /*!< Timer A DMA handle parameters */
00144   DMA_HandleTypeDef *          hdmaTimerB;                   /*!< Timer B DMA handle parameters */
00145   DMA_HandleTypeDef *          hdmaTimerC;                   /*!< Timer C DMA handle parameters */
00146   DMA_HandleTypeDef *          hdmaTimerD;                   /*!< Timer D DMA handle parameters */
00147   DMA_HandleTypeDef *          hdmaTimerE;                   /*!< Timer E DMA handle parameters */
00148 } HRTIM_HandleTypeDef;
00149
00150 /**
00151   * @brief  Simple output compare mode configuration definition
00152   */
00153 typedef struct {
00154   uint32_t Period;                   /*!< Specifies the timer period.
00155                                           The period value must be above 3 periods of the fHRTIM clock.
00156                                           Maximum value is = 0xFFDFU */
00157   uint32_t RepetitionCounter;        /*!< Specifies the timer repetition period.
00158                                           This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00159   uint32_t PrescalerRatio;           /*!< Specifies the timer clock prescaler ratio.
00160                                           This parameter can be any value of @ref HRTIM_Prescaler_Ratio   */
00161   uint32_t Mode;                     /*!< Specifies the counter operating mode.
00162                                           This parameter can be any value of @ref HRTIM_Counter_Operating_Mode   */
00163 } HRTIM_TimeBaseCfgTypeDef;
00164
00165 /**
00166   * @brief  Simple output compare mode configuration definition
00167   */
00168 typedef struct {
00169   uint32_t Mode;       /*!< Specifies the output compare mode (toggle, active, inactive).
00170                             This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
00171   uint32_t Pulse;      /*!< Specifies the compare value to be loaded into the Compare Register.
00172                             The compare value must be above or equal to 3 periods of the fHRTIM clock */
00173   uint32_t Polarity;   /*!< Specifies the output polarity.
00174                             This parameter can be any value of @ref HRTIM_Output_Polarity */
00175   uint32_t IdleLevel;  /*!< Specifies whether the output level is active or inactive when in IDLE state.
00176                             This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
00177 } HRTIM_SimpleOCChannelCfgTypeDef;
00178
00179 /**
00180   * @brief  Simple PWM output mode configuration definition
00181   */
00182 typedef struct {
00183   uint32_t Pulse;            /*!< Specifies the compare value to be loaded into the Compare Register.
00184                                   The compare value must be above or equal to 3 periods of the fHRTIM clock */
00185   uint32_t Polarity;        /*!< Specifies the output polarity.
00186                                  This parameter can be any value of @ref HRTIM_Output_Polarity */
00187   uint32_t IdleLevel;       /*!< Specifies whether the output level is active or inactive when in IDLE state.
00188                                  This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
00189 } HRTIM_SimplePWMChannelCfgTypeDef;
00190
00191 /**
00192   * @brief  Simple capture mode configuration definition
00193   */
00194 typedef struct {
00195   uint32_t Event;             /*!< Specifies the external event triggering the capture.
00196                                    This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
00197   uint32_t EventPolarity;     /*!< Specifies the polarity of the external event (in case of level sensitivity).
00198                                    This parameter can be a value of @ref HRTIM_External_Event_Polarity */
00199   uint32_t EventSensitivity;  /*!< Specifies the sensitivity of the external event.
00200                                    This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
00201   uint32_t EventFilter;       /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
00202                                    This parameter can be a value of @ref HRTIM_External_Event_Filter */
00203 } HRTIM_SimpleCaptureChannelCfgTypeDef;
00204
00205 /**
00206   * @brief  Simple One Pulse mode configuration definition
00207   */
00208 typedef struct {
00209   uint32_t Pulse;             /*!< Specifies the compare value to be loaded into the Compare Register.
00210                                    The compare value must be above or equal to 3 periods of the fHRTIM clock */
00211   uint32_t OutputPolarity;    /*!< Specifies the output polarity.
00212                                    This parameter can be any value of @ref HRTIM_Output_Polarity */
00213   uint32_t OutputIdleLevel;   /*!< Specifies whether the output level is active or inactive when in IDLE state.
00214                                    This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
00215   uint32_t Event;             /*!< Specifies the external event triggering the pulse generation.
00216                                    This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
00217   uint32_t EventPolarity;     /*!< Specifies the polarity of the external event (in case of level sensitivity).
00218                                    This parameter can be a value of @ref HRTIM_External_Event_Polarity */
00219   uint32_t EventSensitivity;  /*!< Specifies the sensitivity of the external event.
00220                                    This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */
00221   uint32_t EventFilter;       /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
00222                                    This parameter can be a value of @ref HRTIM_External_Event_Filter */
00223 } HRTIM_SimpleOnePulseChannelCfgTypeDef;
00224
00225 /**
00226   * @brief  Timer configuration definition
00227   */
00228 typedef struct {
00229   uint32_t InterruptRequests;      /*!< Relevant for all HRTIM timers, including the master.
00230                                        Specifies which interrupts requests must enabled for the timer.
00231                                        This parameter can be any combination of  @ref HRTIM_Master_Interrupt_Enable
00232                                        or @ref HRTIM_Timing_Unit_Interrupt_Enable */
00233   uint32_t DMARequests;            /*!< Relevant for all HRTIM timers, including the master.
00234                                        Specifies which DMA requests must be enabled for the timer.
00235                                        This parameter can be any combination of  @ref HRTIM_Master_DMA_Request_Enable
00236                                        or @ref HRTIM_Timing_Unit_DMA_Request_Enable */
00237   uint32_t DMASrcAddress;          /*!< Relevant for all HRTIM timers, including the master.
00238                                        Specifies the address of the source address of the DMA transfer */
00239   uint32_t DMADstAddress;          /*!< Relevant for all HRTIM timers, including the master.
00240                                        Specifies the address of the destination address of the DMA transfer */
00241   uint32_t DMASize;                /*!< Relevant for all HRTIM timers, including the master.
00242                                        Specifies the size of the DMA transfer */
00243   uint32_t HalfModeEnable;         /*!< Relevant for all HRTIM timers, including the master.
00244                                         Specifies whether or not hald mode is enabled
00245                                         This parameter can be any value of @ref HRTIM_Half_Mode_Enable  */
00246   uint32_t StartOnSync;            /*!< Relevant for all HRTIM timers, including the master.
00247                                        Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
00248                                         This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event  */
00249   uint32_t ResetOnSync;            /*!< Relevant for all HRTIM timers, including the master.
00250                                         Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
00251                                         This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event  */
00252   uint32_t DACSynchro;             /*!< Relevant for all HRTIM timers, including the master.
00253                                         Indicates whether or not the a DAC synchronization event is generated.
00254                                         This parameter can be any value of @ref HRTIM_DAC_Synchronization   */
00255   uint32_t PreloadEnable;          /*!< Relevant for all HRTIM timers, including the master.
00256                                         Specifies whether or not register preload is enabled.
00257                                         This parameter can be any value of @ref HRTIM_Register_Preload_Enable  */
00258   uint32_t UpdateGating;           /*!< Relevant for all HRTIM timers, including the master.
00259                                         Specifies how the update occurs with respect to a burst DMA transaction or
00260                                         update enable inputs (Slave timers only).
00261                                         This parameter can be any value of @ref HRTIM_Update_Gating   */
00262   uint32_t BurstMode;              /*!< Relevant for all HRTIM timers, including the master.
00263                                         Specifies how the timer behaves during a burst mode operation.
00264                                         This parameter can be any value of @ref HRTIM_Timer_Burst_Mode  */
00265   uint32_t RepetitionUpdate;       /*!< Relevant for all HRTIM timers, including the master.
00266                                         Specifies whether or not registers update is triggered by the repetition event.
00267                                         This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */
00268   uint32_t PushPull;               /*!< Relevant for Timer A to Timer E.
00269                                         Specifies whether or not the push-pull mode is enabled.
00270                                         This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
00271   uint32_t FaultEnable;            /*!< Relevant for Timer A to Timer E.
00272                                         Specifies which fault channels are enabled for the timer.
00273                                         This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling  */
00274   uint32_t FaultLock;              /*!< Relevant for Timer A to Timer E.
00275                                         Specifies whether or not fault enabling status is write protected.
00276                                         This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
00277   uint32_t DeadTimeInsertion;      /*!< Relevant for Timer A to Timer E.
00278                                         Specifies whether or not dead-time insertion is enabled for the timer.
00279                                         This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
00280   uint32_t DelayedProtectionMode;  /*!< Relevant for Timer A to Timer E.
00281                                         Specifies the delayed protection mode.
00282                                         This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
00283   uint32_t UpdateTrigger;          /*!< Relevant for Timer A to Timer E.
00284                                         Specifies source(s) triggering the timer registers update.
00285                                         This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
00286   uint32_t ResetTrigger;           /*!< Relevant for Timer A to Timer E.
00287                                         Specifies source(s) triggering the timer counter reset.
00288                                         This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
00289   uint32_t ResetUpdate;           /*!<  Relevant for Timer A to Timer E.
00290                                         Specifies whether or not registers update is triggered when the timer counter is reset.
00291                                         This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
00292 } HRTIM_TimerCfgTypeDef;
00293
00294 /**
00295   * @brief  Compare unit configuration definition
00296   */
00297 typedef struct {
00298   uint32_t CompareValue;         /*!< Specifies the compare value of the timer compare unit.
00299                                       The minimum value must be greater than or equal to 3 periods of the fHRTIM clock.
00300                                       The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */
00301   uint32_t AutoDelayedMode;      /*!< Specifies the auto delayed mode for compare unit 2 or 4.
00302                                       This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
00303   uint32_t AutoDelayedTimeout;   /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected.
00304                                       CompareValue +  AutoDelayedTimeout must be less than 0xFFFFU */
00305 } HRTIM_CompareCfgTypeDef;
00306
00307 /**
00308   * @brief  Capture unit configuration definition
00309   */
00310 typedef struct {
00311   uint32_t Trigger;   /*!< Specifies source(s) triggering the capture.
00312                            This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
00313 } HRTIM_CaptureCfgTypeDef;
00314
00315 /**
00316   * @brief  Output configuration definition
00317   */
00318 typedef struct {
00319   uint32_t Polarity;              /*!< Specifies the output polarity.
00320                                        This parameter can be any value of @ref HRTIM_Output_Polarity */
00321   uint32_t SetSource;             /*!< Specifies the event(s) transitioning the output from its inactive level to its active level.
00322                                        This parameter can be a combination of @ref HRTIM_Output_Set_Source */
00323   uint32_t ResetSource;           /*!< Specifies the event(s) transitioning the output from its active level to its inactive level.
00324                                        This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
00325   uint32_t IdleMode;              /*!< Specifies whether or not the output is affected by a burst mode operation.
00326                                        This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
00327   uint32_t IdleLevel;             /*!< Specifies whether the output level is active or inactive when in IDLE state.
00328                                        This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
00329   uint32_t FaultLevel;            /*!< Specifies whether the output level is active or inactive when in FAULT state.
00330                                        This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
00331   uint32_t ChopperModeEnable;     /*!< Indicates whether or not the chopper mode is enabled
00332                                        This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
00333   uint32_t BurstModeEntryDelayed;  /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation.
00334                                         This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */
00335 } HRTIM_OutputCfgTypeDef;
00336
00337 /**
00338   * @brief  External event filtering in timing units configuration definition
00339   */
00340 typedef struct {
00341   uint32_t Filter;       /*!< Specifies the type of event filtering within the timing unit.
00342                              This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
00343   uint32_t Latch;       /*!< Specifies whether or not the signal is latched.
00344                              This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */
00345 } HRTIM_TimerEventFilteringCfgTypeDef;
00346
00347 /**
00348   * @brief  Dead time feature configuration definition
00349   */
00350 typedef struct {
00351   uint32_t Prescaler;        /*!< Specifies the Deadtime Prescaler.
00352                                   This parameter can be a value of @ref  HRTIM_Deadtime_Prescaler_Ratio */
00353   uint32_t RisingValue;      /*!< Specifies the Deadtime following a rising edge.
00354                                   This parameter can be a number between 0x0 and 0x1FFU */
00355   uint32_t RisingSign;       /*!< Specifies whether the deadtime is positive or negative on rising edge.
00356                                   This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
00357   uint32_t RisingLock;       /*!< Specifies whether or not deadtime rising settings (value and sign) are write protected.
00358                                   This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */
00359   uint32_t RisingSignLock;   /*!< Specifies whether or not deadtime rising sign is write protected.
00360                                   This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
00361   uint32_t FallingValue;     /*!< Specifies the Deadtime following a falling edge.
00362                                  This parameter can be a number between 0x0 and 0x1FFU */
00363   uint32_t FallingSign;      /*!< Specifies whether the deadtime is positive or negative on falling edge.
00364                                  This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
00365   uint32_t FallingLock;      /*!< Specifies whether or not deadtime falling settings (value and sign) are write protected.
00366                                  This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
00367   uint32_t FallingSignLock;  /*!< Specifies whether or not deadtime falling sign is write protected.
00368                                  This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
00369 } HRTIM_DeadTimeCfgTypeDef ;
00370
00371 /**
00372   * @brief  Chopper mode configuration definition
00373   */
00374 typedef struct {
00375   uint32_t CarrierFreq;  /*!< Specifies the Timer carrier frequency value.
00376                               This parameter can be a value of @ref HRTIM_Chopper_Frequency */
00377   uint32_t DutyCycle;   /*!< Specifies the Timer chopper duty cycle value.
00378                              This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */
00379   uint32_t StartPulse;  /*!< Specifies the Timer pulse width value.
00380                              This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */
00381 } HRTIM_ChopperModeCfgTypeDef;
00382
00383 /**
00384   * @brief  External event channel configuration definition
00385   */
00386 typedef struct {
00387   uint32_t Source;        /*!< Identifies the source of the external event.
00388                                This parameter can be a value of @ref HRTIM_External_Event_Sources */
00389   uint32_t Polarity;      /*!< Specifies the polarity of the external event (in case of level sensitivity).
00390                                This parameter can be a value of @ref HRTIM_External_Event_Polarity */
00391   uint32_t Sensitivity;   /*!< Specifies the sensitivity of the external event.
00392                                This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
00393   uint32_t Filter;        /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
00394                                This parameter can be a value of @ref HRTIM_External_Event_Filter */
00395   uint32_t FastMode;     /*!< Indicates whether or not low latency mode is enabled for the external event.
00396                               This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */
00397 } HRTIM_EventCfgTypeDef;
00398
00399 /**
00400   * @brief  Fault channel configuration definition
00401   */
00402 typedef struct {
00403   uint32_t Source;        /*!< Identifies the source of the fault.
00404                                This parameter can be a value of @ref HRTIM_Fault_Sources */
00405   uint32_t Polarity;      /*!< Specifies the polarity of the fault event.
00406                                This parameter can be a value of @ref HRTIM_Fault_Polarity */
00407   uint32_t Filter;        /*!< Defines the frequency used to sample the Fault input and the length of the digital filter.
00408                                This parameter can be a value of @ref HRTIM_Fault_Filter */
00409   uint32_t Lock;          /*!< Indicates whether or not fault programming bits are write protected.
00410                               This parameter can be a value of @ref HRTIM_Fault_Lock */
00411 } HRTIM_FaultCfgTypeDef;
00412
00413 /**
00414   * @brief  Burst mode configuration definition
00415   */
00416 typedef struct {
00417   uint32_t Mode;           /*!< Specifies the burst mode operating mode.
00418                                 This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */
00419   uint32_t ClockSource;    /*!< Specifies the burst mode clock source.
00420                                 This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */
00421   uint32_t Prescaler;      /*!< Specifies the burst mode prescaler.
00422                                 This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */
00423   uint32_t PreloadEnable;  /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER).
00424                                 This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable  */
00425   uint32_t Trigger;        /*!< Specifies the event(s) triggering the burst operation.
00426                                 This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger  */
00427   uint32_t IdleDuration;   /*!< Specifies number of periods during which the selected timers are in idle state.
00428                                 This parameter can be a number between 0x0 and 0xFFFF  */
00429   uint32_t Period;        /*!< Specifies burst mode repetition period.
00430                                 This parameter can be a number between 0x1 and 0xFFFF  */
00431 } HRTIM_BurstModeCfgTypeDef;
00432
00433 /**
00434   * @brief  ADC trigger configuration definition
00435   */
00436 typedef struct {
00437   uint32_t UpdateSource;  /*!< Specifies the ADC trigger update source.
00438                                This parameter can be a combination of @ref HRTIM_ADC_Trigger_Update_Source  */
00439   uint32_t Trigger;      /*!< Specifies the event(s) triggering the ADC conversion.
00440                               This parameter can be a value of @ref HRTIM_ADC_Trigger_Event  */
00441 } HRTIM_ADCTriggerCfgTypeDef;
00442
00443 /**
00444   * @}
00445   */
00446
00447 /* Exported constants --------------------------------------------------------*/
00448 /** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants
00449   * @{
00450   */
00451
00452 /** @defgroup HRTIM_Timer_Index HRTIM Timer Index
00453   * @{
00454   * @brief Constants defining the timer indexes
00455   */
00456 #define HRTIM_TIMERINDEX_TIMER_A 0x0U   /*!< Index used to access timer A registers */
00457 #define HRTIM_TIMERINDEX_TIMER_B 0x1U   /*!< Index used to access timer B registers */
00458 #define HRTIM_TIMERINDEX_TIMER_C 0x2U   /*!< Index used to access timer C registers */
00459 #define HRTIM_TIMERINDEX_TIMER_D 0x3U   /*!< Index used to access timer D registers */
00460 #define HRTIM_TIMERINDEX_TIMER_E 0x4U   /*!< Index used to access timer E registers */
00461 #define HRTIM_TIMERINDEX_MASTER  0x5U   /*!< Index used to access master registers */
00462 #define HRTIM_TIMERINDEX_COMMON  0xFFU  /*!< Index used to access HRTIM common registers */
00463 /**
00464   * @}
00465   */
00466
00467 /** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier
00468   * @{
00469   * @brief Constants defining timer identifiers
00470   */
00471 #define HRTIM_TIMERID_MASTER  (HRTIM_MCR_MCEN)   /*!< Master identifier*/
00472 #define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN)  /*!< Timer A identifier */
00473 #define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN)  /*!< Timer B identifier */
00474 #define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN)  /*!< Timer C identifier */
00475 #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN)  /*!< Timer D identifier */
00476 #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN)  /*!< Timer E identifier */
00477 /**
00478  * @}
00479  */
00480
00481 /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit
00482   * @{
00483   * @brief Constants defining compare unit identifiers
00484   */
00485 #define HRTIM_COMPAREUNIT_1 0x00000001U  /*!< Compare unit 1 identifier */
00486 #define HRTIM_COMPAREUNIT_2 0x00000002U  /*!< Compare unit 2 identifier */
00487 #define HRTIM_COMPAREUNIT_3 0x00000004U  /*!< Compare unit 3 identifier */
00488 #define HRTIM_COMPAREUNIT_4 0x00000008U  /*!< Compare unit 4 identifier */
00489  /**
00490   * @}
00491   */
00492
00493 /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit
00494   * @{
00495   * @brief Constants defining capture unit identifiers
00496   */
00497 #define HRTIM_CAPTUREUNIT_1 0x00000001U  /*!< Capture unit 1 identifier */
00498 #define HRTIM_CAPTUREUNIT_2 0x00000002U  /*!< Capture unit 2 identifier */
00499 /**
00500   * @}
00501   */
00502
00503 /** @defgroup HRTIM_Timer_Output HRTIM Timer Output
00504   * @{
00505   * @brief Constants defining timer output identifiers
00506   */
00507 #define HRTIM_OUTPUT_TA1  0x00000001U  /*!< Timer A - Output 1 identifier */
00508 #define HRTIM_OUTPUT_TA2  0x00000002U  /*!< Timer A - Output 2 identifier */
00509 #define HRTIM_OUTPUT_TB1  0x00000004U  /*!< Timer B - Output 1 identifier */
00510 #define HRTIM_OUTPUT_TB2  0x00000008U  /*!< Timer B - Output 2 identifier */
00511 #define HRTIM_OUTPUT_TC1  0x00000010U  /*!< Timer C - Output 1 identifier */
00512 #define HRTIM_OUTPUT_TC2  0x00000020U  /*!< Timer C - Output 2 identifier */
00513 #define HRTIM_OUTPUT_TD1  0x00000040U  /*!< Timer D - Output 1 identifier */
00514 #define HRTIM_OUTPUT_TD2  0x00000080U  /*!< Timer D - Output 2 identifier */
00515 #define HRTIM_OUTPUT_TE1  0x00000100U  /*!< Timer E - Output 1 identifier */
00516 #define HRTIM_OUTPUT_TE2  0x00000200U  /*!< Timer E - Output 2 identifier */
00517 /**
00518   * @}
00519   */
00520
00521 /** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger
00522   * @{
00523   * @brief Constants defining ADC triggers identifiers
00524   */
00525 #define HRTIM_ADCTRIGGER_1  0x00000001U  /*!< ADC trigger 1 identifier */
00526 #define HRTIM_ADCTRIGGER_2  0x00000002U  /*!< ADC trigger 2 identifier */
00527 #define HRTIM_ADCTRIGGER_3  0x00000004U  /*!< ADC trigger 3 identifier */
00528 #define HRTIM_ADCTRIGGER_4  0x00000008U  /*!< ADC trigger 4 identifier */
00529
00530 #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
00531     (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1)   || \
00532      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2)   || \
00533      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3)   || \
00534      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
00535 /**
00536   * @}
00537   */
00538
00539 /** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels
00540   * @{
00541   * @brief Constants defining external event channel identifiers
00542   */
00543 #define HRTIM_EVENT_NONE     (0x00000000U)     /*!< Undefined event channel */
00544 #define HRTIM_EVENT_1        (0x00000001U)     /*!< External event channel 1 identifier */
00545 #define HRTIM_EVENT_2        (0x00000002U)     /*!< External event channel 2 identifier */
00546 #define HRTIM_EVENT_3        (0x00000004U)     /*!< External event channel 3 identifier */
00547 #define HRTIM_EVENT_4        (0x00000008U)     /*!< External event channel 4 identifier */
00548 #define HRTIM_EVENT_5        (0x00000010U)     /*!< External event channel 5 identifier */
00549 #define HRTIM_EVENT_6        (0x00000020U)     /*!< External event channel 6 identifier */
00550 #define HRTIM_EVENT_7        (0x00000040U)     /*!< External event channel 7 identifier */
00551 #define HRTIM_EVENT_8        (0x00000080U)     /*!< External event channel 8 identifier */
00552 #define HRTIM_EVENT_9        (0x00000100U)     /*!< External event channel 9 identifier */
00553 #define HRTIM_EVENT_10       (0x00000200U)     /*!< External event channel 10 identifier */
00554 /**
00555   * @}
00556   */
00557
00558 /** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel
00559   * @{
00560   * @brief Constants defining fault channel identifiers
00561   */
00562 #define HRTIM_FAULT_1      (0x01U)     /*!< Fault channel 1 identifier */
00563 #define HRTIM_FAULT_2      (0x02U)     /*!< Fault channel 2 identifier */
00564 #define HRTIM_FAULT_3      (0x04U)     /*!< Fault channel 3 identifier */
00565 #define HRTIM_FAULT_4      (0x08U)     /*!< Fault channel 4 identifier */
00566 #define HRTIM_FAULT_5      (0x10U)     /*!< Fault channel 5 identifier */
00567 /**
00568   * @}
00569   */
00570
00571
00572  /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio
00573   * @{
00574   * @brief Constants defining timer high-resolution clock prescaler ratio.
00575   */
00576 #define HRTIM_PRESCALERRATIO_MUL32    (0x00000000U)  /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)      */
00577 #define HRTIM_PRESCALERRATIO_MUL16    (0x00000001U)  /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)      */
00578 #define HRTIM_PRESCALERRATIO_MUL8     (0x00000002U)  /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)      */
00579 #define HRTIM_PRESCALERRATIO_MUL4     (0x00000003U)  /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)      */
00580 #define HRTIM_PRESCALERRATIO_MUL2     (0x00000004U)  /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)      */
00581 #define HRTIM_PRESCALERRATIO_DIV1     (0x00000005U)  /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)      */
00582 #define HRTIM_PRESCALERRATIO_DIV2     (0x00000006U)  /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)      */
00583 #define HRTIM_PRESCALERRATIO_DIV4     (0x00000007U)  /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)      */
00584 /**
00585   * @}
00586   */
00587
00588 /** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode
00589   * @{
00590   * @brief Constants defining timer counter operating mode.
00591   */
00592 #define HRTIM_MODE_CONTINUOUS               (0x00000008U)  /*!< The timer operates in continuous (free-running) mode */
00593 #define HRTIM_MODE_SINGLESHOT               (0x00000000U)  /*!< The timer operates in non retriggerable single-shot mode */
00594 #define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U)  /*!< The timer operates in retriggerable single-shot mode */
00595 /**
00596   * @}
00597   */
00598
00599 /** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable
00600   * @{
00601   * @brief Constants defining half mode enabling status.
00602   */
00603 #define HRTIM_HALFMODE_DISABLED (0x00000000U)  /*!< Half mode is disabled */
00604 #define HRTIM_HALFMODE_ENABLED  (0x00000020U)  /*!< Half mode is enabled */
00605 /**
00606   * @}
00607   */
00608
00609 /** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event
00610   * @{
00611   * @brief Constants defining the timer behavior following the synchronization event
00612   */
00613 #define HRTIM_SYNCSTART_DISABLED (0x00000000U)  /*!< Synchronization input event has effect on the timer */
00614 #define HRTIM_SYNCSTART_ENABLED  (HRTIM_MCR_SYNCSTRTM)   /*!< Synchronization input event starts the timer */
00615 /**
00616   * @}
00617   */
00618
00619 /** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event
00620   * @{
00621   * @brief Constants defining the timer behavior following the synchronization event
00622   */
00623 #define HRTIM_SYNCRESET_DISABLED (0x00000000U)  /*!< Synchronization input event has effect on the timer */
00624 #define HRTIM_SYNCRESET_ENABLED  (HRTIM_MCR_SYNCRSTM)    /*!< Synchronization input event resets the timer */
00625 /**
00626   * @}
00627   */
00628
00629 /** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization
00630   * @{
00631   * @brief Constants defining on which output the DAC synchronization event is sent
00632   */
00633 #define HRTIM_DACSYNC_NONE          0x00000000U                                  /*!< No DAC synchronization event generated */
00634 #define HRTIM_DACSYNC_DACTRIGOUT_1  (HRTIM_MCR_DACSYNC_0)                       /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
00635 #define HRTIM_DACSYNC_DACTRIGOUT_2  (HRTIM_MCR_DACSYNC_1)                       /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
00636 #define HRTIM_DACSYNC_DACTRIGOUT_3  (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */
00637 /**
00638   * @}
00639   */
00640
00641 /** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable
00642   * @{
00643   * @brief Constants defining whether a write access into a preloadable
00644   *        register is done into the active or the preload register.
00645   */
00646 #define HRTIM_PRELOAD_DISABLED (0x00000000U)           /*!< Preload disabled: the write access is directly done into the active register */
00647 #define HRTIM_PRELOAD_ENABLED  (HRTIM_MCR_PREEN)       /*!< Preload enabled: the write access is done into the preload register */
00648 /**
00649   * @}
00650   */
00651
00652 /** @defgroup HRTIM_Update_Gating HRTIM Update Gating
00653   * @{
00654   * @brief Constants defining how the update occurs relatively to the burst DMA
00655   *        transaction and the external update request on update enable inputs 1 to 3.
00656   */
00657 #define HRTIM_UPDATEGATING_INDEPENDENT     0x00000000U                                                            /*!< Update done independently from the DMA burst transfer completion */
00658 #define HRTIM_UPDATEGATING_DMABURST        (HRTIM_TIMCR_UPDGAT_0)                                                /*!< Update done when the DMA burst transfer is completed */
00659 #define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1)                                                /*!< Update done on timer roll-over following a DMA burst transfer completion*/
00660 #define HRTIM_UPDATEGATING_UPDEN1          (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U */
00661 #define HRTIM_UPDATEGATING_UPDEN2          (HRTIM_TIMCR_UPDGAT_2)                                                /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U */
00662 #define HRTIM_UPDATEGATING_UPDEN3          (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U */
00663 #define HRTIM_UPDATEGATING_UPDEN1_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1)                         /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 1U */
00664 #define HRTIM_UPDATEGATING_UPDEN2_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)  /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 2U */
00665 #define HRTIM_UPDATEGATING_UPDEN3_UPDATE   (HRTIM_TIMCR_UPDGAT_3)                                                /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 3U */
00666 /**
00667   * @}
00668   */
00669
00670 /** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode
00671   * @{
00672   * @brief Constants defining how the timer behaves during a burst
00673             mode operation.
00674   */
00675 #define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x000000U          /*!< Timer counter clock is maintained and the timer operates normally */
00676 #define HRTIM_TIMERBURSTMODE_RESETCOUNTER  (HRTIM_BMCR_MTBM)  /*!< Timer counter clock is stopped and the counter is reset */
00677 /**
00678   * @}
00679   */
00680
00681 /** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update
00682   * @{
00683   * @brief Constants defining whether registers are updated when the timer
00684   *        repetition period is completed (either due to roll-over or
00685   *        reset events)
00686   */
00687 #define HRTIM_UPDATEONREPETITION_DISABLED 0x00000000U          /*!< Update on repetition disabled */
00688 #define HRTIM_UPDATEONREPETITION_ENABLED  (HRTIM_MCR_MREPU)    /*!< Update on repetition enabled */
00689 /**
00690   * @}
00691   */
00692
00693
00694 /** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode
00695   * @{
00696   * @brief Constants defining whether or not the puhs-pull mode is enabled for
00697   *        a timer.
00698   */
00699 #define HRTIM_TIMPUSHPULLMODE_DISABLED   (0x00000000U)                   /*!< Push-Pull mode disabled */
00700 #define HRTIM_TIMPUSHPULLMODE_ENABLED    ((uint32_t)HRTIM_TIMCR_PSHPLL)  /*!< Push-Pull mode enabled */
00701 /**
00702   * @}
00703   */
00704
00705 /** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling
00706   * @{
00707   * @brief Constants defining whether a faut channel is enabled for a timer
00708   */
00709 #define HRTIM_TIMFAULTENABLE_NONE     0x00000000U            /*!< No fault enabled */
00710 #define HRTIM_TIMFAULTENABLE_FAULT1   (HRTIM_FLTR_FLT1EN)   /*!< Fault 1 enabled */
00711 #define HRTIM_TIMFAULTENABLE_FAULT2   (HRTIM_FLTR_FLT2EN)   /*!< Fault 2 enabled */
00712 #define HRTIM_TIMFAULTENABLE_FAULT3   (HRTIM_FLTR_FLT3EN)   /*!< Fault 3 enabled */
00713 #define HRTIM_TIMFAULTENABLE_FAULT4   (HRTIM_FLTR_FLT4EN)   /*!< Fault 4 enabled */
00714 #define HRTIM_TIMFAULTENABLE_FAULT5   (HRTIM_FLTR_FLT5EN)   /*!< Fault 5 enabled */
00715 /**
00716   * @}
00717   */
00718
00719 /** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock
00720   * @{
00721   * @brief Constants defining whether or not fault enabling bits are write
00722   *        protected for a timer
00723   */
00724 #define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U)           /*!< Timer fault enabling bits are read/write */
00725 #define HRTIM_TIMFAULTLOCK_READONLY  (HRTIM_FLTR_FLTLCK)     /*!< Timer fault enabling bits are read only */
00726 /**
00727   * @}
00728   */
00729
00730 /** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Deadtime Insertion
00731   * @{
00732   * @brief Constants defining whether or not fault the dead time insertion
00733   *        feature is enabled for a timer
00734   */
00735 #define HRTIM_TIMDEADTIMEINSERTION_DISABLED   (0x00000000U)           /*!< Output 1 and output 2 signals are independent */
00736 #define HRTIM_TIMDEADTIMEINSERTION_ENABLED    HRTIM_OUTR_DTEN         /*!< Deadtime is inserted between output 1 and output 2U */
00737 /**
00738   * @}
00739   */
00740
00741 /** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode
00742   * @{
00743   * @brief Constants defining all possible delayed protection modes
00744   *        for a timer. Also definethe source and outputs on which the delayed
00745   *        protection schemes are applied
00746   */
00747 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED          (0x00000000U)                                                                           /*!< No action */
00748 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6  (HRTIM_OUTR_DLYPRTEN)                                                                   /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6U */
00749 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6  (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6U */
00750 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6  (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U */
00751 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6     (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Balanced Idle on external Event 6U */
00752 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7U */
00753 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7U */
00754 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */
00755 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7     (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */
00756
00757 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED          (0x00000000U)                                                                             /*!< No action */
00758 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8  (HRTIM_OUTR_DLYPRTEN)                                                                     /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */
00759 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8  (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */
00760 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8  (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */
00761 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8     (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Balanced Idle on external Event 6U */
00762 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */
00763 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */
00764 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */
00765 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9     (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)   /*!< Timers D, E: Balanced Idle on external Event 7U */
00766 /**
00767   * @}
00768   */
00769
00770 /** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger
00771   * @{
00772   * @brief Constants defining whether the registers update is done synchronously
00773   *        with any other timer or master update
00774   */
00775 #define HRTIM_TIMUPDATETRIGGER_NONE     0x00000000U          /*!< Register update is disabled */
00776 #define HRTIM_TIMUPDATETRIGGER_MASTER   (HRTIM_TIMCR_MSTU)   /*!< Register update is triggered by the master timer update */
00777 #define HRTIM_TIMUPDATETRIGGER_TIMER_A  (HRTIM_TIMCR_TAU)    /*!< Register update is triggered by the timer A update */
00778 #define HRTIM_TIMUPDATETRIGGER_TIMER_B  (HRTIM_TIMCR_TBU)    /*!< Register update is triggered by the timer B update */
00779 #define HRTIM_TIMUPDATETRIGGER_TIMER_C  (HRTIM_TIMCR_TCU)    /*!< Register update is triggered by the timer C update*/
00780 #define HRTIM_TIMUPDATETRIGGER_TIMER_D  (HRTIM_TIMCR_TDU)    /*!< Register update is triggered by the timer D update */
00781 #define HRTIM_TIMUPDATETRIGGER_TIMER_E  (HRTIM_TIMCR_TEU)    /*!< Register update is triggered by the timer E update */
00782 /**
00783   * @}
00784   */
00785
00786 /** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger
00787   * @{
00788   * @brief Constants defining the events that can be selected to trigger the reset
00789   *        of the timer counter
00790   */
00791 #define HRTIM_TIMRESETTRIGGER_NONE        0x00000000U            /*!< No counter reset trigger */
00792 #define HRTIM_TIMRESETTRIGGER_UPDATE      (HRTIM_RSTR_UPDATE)    /*!< The timer counter is reset upon update event */
00793 #define HRTIM_TIMRESETTRIGGER_CMP2        (HRTIM_RSTR_CMP2)      /*!< The timer counter is reset upon Timer Compare 2 event */
00794 #define HRTIM_TIMRESETTRIGGER_CMP4        (HRTIM_RSTR_CMP4)      /*!< The timer counter is reset upon Timer Compare 4 event */
00795 #define HRTIM_TIMRESETTRIGGER_MASTER_PER  (HRTIM_RSTR_MSTPER)    /*!< The timer counter is reset upon master timer period event */
00796 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1)   /*!< The timer counter is reset upon master timer Compare 1 event */
00797 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2)   /*!< The timer counter is reset upon master timer Compare 2 event */
00798 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3)   /*!< The timer counter is reset upon master timer Compare 3 event */
00799 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4)   /*!< The timer counter is reset upon master timer Compare 4 event */
00800 #define HRTIM_TIMRESETTRIGGER_EEV_1       (HRTIM_RSTR_EXTEVNT1)  /*!< The timer counter is reset upon external event 1U */
00801 #define HRTIM_TIMRESETTRIGGER_EEV_2       (HRTIM_RSTR_EXTEVNT2)  /*!< The timer counter is reset upon external event 2U */
00802 #define HRTIM_TIMRESETTRIGGER_EEV_3       (HRTIM_RSTR_EXTEVNT3)  /*!< The timer counter is reset upon external event 3U */
00803 #define HRTIM_TIMRESETTRIGGER_EEV_4       (HRTIM_RSTR_EXTEVNT4)  /*!< The timer counter is reset upon external event 4U */
00804 #define HRTIM_TIMRESETTRIGGER_EEV_5       (HRTIM_RSTR_EXTEVNT5)  /*!< The timer counter is reset upon external event 5U */
00805 #define HRTIM_TIMRESETTRIGGER_EEV_6       (HRTIM_RSTR_EXTEVNT6)  /*!< The timer counter is reset upon external event 6U */
00806 #define HRTIM_TIMRESETTRIGGER_EEV_7       (HRTIM_RSTR_EXTEVNT7)  /*!< The timer counter is reset upon external event 7U */
00807 #define HRTIM_TIMRESETTRIGGER_EEV_8       (HRTIM_RSTR_EXTEVNT8)  /*!< The timer counter is reset upon external event 8U */
00808 #define HRTIM_TIMRESETTRIGGER_EEV_9       (HRTIM_RSTR_EXTEVNT9)  /*!< The timer counter is reset upon external event 9U */
00809 #define HRTIM_TIMRESETTRIGGER_EEV_10      (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10U */
00810 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
00811 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
00812 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
00813 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
00814 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
00815 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
00816 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
00817 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
00818 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
00819 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
00820 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
00821 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
00822 /**
00823   * @}
00824   */
00825
00826 /** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update
00827   * @{
00828   * @brief Constants defining whether the register are updated upon Timerx
00829   *        counter reset or roll-over to 0 after reaching the period value
00830   *        in continuous mode
00831   */
00832 #define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U            /*!< Update by timer x reset / roll-over disabled */
00833 #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU)    /*!< Update by timer x reset / roll-over enabled */
00834 /**
00835   * @}
00836   */
00837
00838 /** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode
00839   * @{
00840   * @brief Constants defining whether the compare register is behaving in
00841   *        regular mode (compare match issued as soon as counter equal compare),
00842   *        or in auto-delayed mode
00843   */
00844 #define HRTIM_AUTODELAYEDMODE_REGULAR                 (0x00000000U)                                   /*!< standard compare mode */
00845 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT   (HRTIM_TIMCR_DELCMP2_0)                         /*!< Compare event generated only if a capture has occurred */
00846 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1)                         /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
00847 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
00848 /**
00849   * @}
00850   */
00851
00852 /** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode
00853   * @{
00854   * @brief Constants defining the behavior of the output signal when the timer
00855            operates in basic output compare mode
00856   */
00857 #define HRTIM_BASICOCMODE_TOGGLE    (0x00000001U)  /*!< Output toggles when the timer counter reaches the compare value */
00858 #define HRTIM_BASICOCMODE_INACTIVE  (0x00000002U)  /*!< Output forced to active level when the timer counter reaches the compare value */
00859 #define HRTIM_BASICOCMODE_ACTIVE    (0x00000003U)  /*!< Output forced to inactive level when the timer counter reaches the compare value */
00860
00861 #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
00862               (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE)   || \
00863                ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
00864                ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
00865 /**
00866   * @}
00867   */
00868
00869 /** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity
00870   * @{
00871   * @brief Constants defining the polarity of a timer output
00872   */
00873 #define HRTIM_OUTPUTPOLARITY_HIGH    (0x00000000U)           /*!< Output is acitve HIGH */
00874 #define HRTIM_OUTPUTPOLARITY_LOW     (HRTIM_OUTR_POL1)       /*!< Output is active LOW */
00875 /**
00876   * @}
00877   */
00878
00879 /** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source
00880   * @{
00881   * @brief Constants defining the events that can be selected to configure the
00882   *        set crossbar of a timer output
00883   */
00884 #define HRTIM_OUTPUTSET_NONE       0x00000000U              /*!< Reset the output set crossbar */
00885 #define HRTIM_OUTPUTSET_RESYNC     (HRTIM_SET1R_RESYNC)    /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
00886 #define HRTIM_OUTPUTSET_TIMPER     (HRTIM_SET1R_PER)       /*!< Timer period event forces the output to its active state */
00887 #define HRTIM_OUTPUTSET_TIMCMP1    (HRTIM_SET1R_CMP1)      /*!< Timer compare 1 event forces the output to its active state */
00888 #define HRTIM_OUTPUTSET_TIMCMP2    (HRTIM_SET1R_CMP2)      /*!< Timer compare 2 event forces the output to its active state */
00889 #define HRTIM_OUTPUTSET_TIMCMP3    (HRTIM_SET1R_CMP3)      /*!< Timer compare 3 event forces the output to its active state */
00890 #define HRTIM_OUTPUTSET_TIMCMP4    (HRTIM_SET1R_CMP4)      /*!< Timer compare 4 event forces the output to its active state */
00891 #define HRTIM_OUTPUTSET_MASTERPER  (HRTIM_SET1R_MSTPER)    /*!< The master timer period event forces the output to its active state */
00892 #define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1)   /*!< Master Timer compare 1 event forces the output to its active state */
00893 #define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2)   /*!< Master Timer compare 2 event forces the output to its active state */
00894 #define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3)   /*!< Master Timer compare 3 event forces the output to its active state */
00895 #define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4)   /*!< Master Timer compare 4 event forces the output to its active state */
00896 #define HRTIM_OUTPUTSET_TIMEV_1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
00897 #define HRTIM_OUTPUTSET_TIMEV_2    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
00898 #define HRTIM_OUTPUTSET_TIMEV_3    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
00899 #define HRTIM_OUTPUTSET_TIMEV_4    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
00900 #define HRTIM_OUTPUTSET_TIMEV_5    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
00901 #define HRTIM_OUTPUTSET_TIMEV_6    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
00902 #define HRTIM_OUTPUTSET_TIMEV_7    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
00903 #define HRTIM_OUTPUTSET_TIMEV_8    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
00904 #define HRTIM_OUTPUTSET_TIMEV_9    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
00905 #define HRTIM_OUTPUTSET_EEV_1      (HRTIM_SET1R_EXTVNT1)   /*!< External event 1 forces the output to its active state */
00906 #define HRTIM_OUTPUTSET_EEV_2      (HRTIM_SET1R_EXTVNT2)   /*!< External event 2 forces the output to its active state */
00907 #define HRTIM_OUTPUTSET_EEV_3      (HRTIM_SET1R_EXTVNT3)   /*!< External event 3 forces the output to its active state */
00908 #define HRTIM_OUTPUTSET_EEV_4      (HRTIM_SET1R_EXTVNT4)   /*!< External event 4 forces the output to its active state */
00909 #define HRTIM_OUTPUTSET_EEV_5      (HRTIM_SET1R_EXTVNT5)   /*!< External event 5 forces the output to its active state */
00910 #define HRTIM_OUTPUTSET_EEV_6      (HRTIM_SET1R_EXTVNT6)   /*!< External event 6 forces the output to its active state */
00911 #define HRTIM_OUTPUTSET_EEV_7      (HRTIM_SET1R_EXTVNT7)   /*!< External event 7 forces the output to its active state */
00912 #define HRTIM_OUTPUTSET_EEV_8      (HRTIM_SET1R_EXTVNT8)   /*!< External event 8 forces the output to its active state */
00913 #define HRTIM_OUTPUTSET_EEV_9      (HRTIM_SET1R_EXTVNT9)   /*!< External event 9 forces the output to its active state */
00914 #define HRTIM_OUTPUTSET_EEV_10     (HRTIM_SET1R_EXTVNT10)  /*!< External event 10 forces the output to its active state */
00915 #define HRTIM_OUTPUTSET_UPDATE     (HRTIM_SET1R_UPDATE)    /*!< Timer register update event forces the output to its active state */
00916 /**
00917   * @}
00918   */
00919
00920 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
00921   * @{
00922   * @brief Constants defining the events that can be selected to configure the
00923   *        set crossbar of a timer output
00924   */
00925 #define HRTIM_OUTPUTRESET_NONE       0x00000000U              /*!< Reset the output reset crossbar */
00926 #define HRTIM_OUTPUTRESET_RESYNC     (HRTIM_RST1R_RESYNC)    /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
00927 #define HRTIM_OUTPUTRESET_TIMPER     (HRTIM_RST1R_PER)       /*!< Timer period event forces the output to its inactive state */
00928 #define HRTIM_OUTPUTRESET_TIMCMP1    (HRTIM_RST1R_CMP1)      /*!< Timer compare 1 event forces the output to its inactive state */
00929 #define HRTIM_OUTPUTRESET_TIMCMP2    (HRTIM_RST1R_CMP2)      /*!< Timer compare 2 event forces the output to its inactive state */
00930 #define HRTIM_OUTPUTRESET_TIMCMP3    (HRTIM_RST1R_CMP3)      /*!< Timer compare 3 event forces the output to its inactive state */
00931 #define HRTIM_OUTPUTRESET_TIMCMP4    (HRTIM_RST1R_CMP4)      /*!< Timer compare 4 event forces the output to its inactive state */
00932 #define HRTIM_OUTPUTRESET_MASTERPER  (HRTIM_RST1R_MSTPER)    /*!< The master timer period event forces the output to its inactive state */
00933 #define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1)   /*!< Master Timer compare 1 event forces the output to its inactive state */
00934 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2)   /*!< Master Timer compare 2 event forces the output to its inactive state */
00935 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3)   /*!< Master Timer compare 3 event forces the output to its inactive state */
00936 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4)   /*!< Master Timer compare 4 event forces the output to its inactive state */
00937 #define HRTIM_OUTPUTRESET_TIMEV_1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
00938 #define HRTIM_OUTPUTRESET_TIMEV_2    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
00939 #define HRTIM_OUTPUTRESET_TIMEV_3    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
00940 #define HRTIM_OUTPUTRESET_TIMEV_4    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
00941 #define HRTIM_OUTPUTRESET_TIMEV_5    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
00942 #define HRTIM_OUTPUTRESET_TIMEV_6    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
00943 #define HRTIM_OUTPUTRESET_TIMEV_7    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
00944 #define HRTIM_OUTPUTRESET_TIMEV_8    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
00945 #define HRTIM_OUTPUTRESET_TIMEV_9    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
00946 #define HRTIM_OUTPUTRESET_EEV_1      (HRTIM_RST1R_EXTVNT1)   /*!< External event 1 forces the output to its inactive state */
00947 #define HRTIM_OUTPUTRESET_EEV_2      (HRTIM_RST1R_EXTVNT2)   /*!< External event 2 forces the output to its inactive state */
00948 #define HRTIM_OUTPUTRESET_EEV_3      (HRTIM_RST1R_EXTVNT3)   /*!< External event 3 forces the output to its inactive state */
00949 #define HRTIM_OUTPUTRESET_EEV_4      (HRTIM_RST1R_EXTVNT4)   /*!< External event 4 forces the output to its inactive state */
00950 #define HRTIM_OUTPUTRESET_EEV_5      (HRTIM_RST1R_EXTVNT5)   /*!< External event 5 forces the output to its inactive state */
00951 #define HRTIM_OUTPUTRESET_EEV_6      (HRTIM_RST1R_EXTVNT6)   /*!< External event 6 forces the output to its inactive state */
00952 #define HRTIM_OUTPUTRESET_EEV_7      (HRTIM_RST1R_EXTVNT7)   /*!< External event 7 forces the output to its inactive state */
00953 #define HRTIM_OUTPUTRESET_EEV_8      (HRTIM_RST1R_EXTVNT8)   /*!< External event 8 forces the output to its inactive state */
00954 #define HRTIM_OUTPUTRESET_EEV_9      (HRTIM_RST1R_EXTVNT9)   /*!< External event 9 forces the output to its inactive state */
00955 #define HRTIM_OUTPUTRESET_EEV_10     (HRTIM_RST1R_EXTVNT10)  /*!< External event 10 forces the output to its inactive state */
00956 #define HRTIM_OUTPUTRESET_UPDATE     (HRTIM_RST1R_UPDATE)    /*!< Timer register update event forces the output to its inactive state */
00957 /**
00958   * @}
00959   */
00960
00961 /** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode
00962   * @{
00963   * @brief Constants defining whether or not the timer output transition to its
00964            IDLE state when burst mode is entered
00965   */
00966 #define HRTIM_OUTPUTIDLEMODE_NONE     0x00000000U            /*!< The output is not affected by the burst mode operation */
00967 #define HRTIM_OUTPUTIDLEMODE_IDLE     (HRTIM_OUTR_IDLM1)    /*!< The output is in idle state when requested by the burst mode controller */
00968  /**
00969   * @}
00970   */
00971
00972 /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level
00973   * @{
00974   * @brief Constants defining the output level when output is in IDLE state
00975   */
00976 #define HRTIM_OUTPUTIDLELEVEL_INACTIVE   0x00000000U            /*!< Output at inactive level when in IDLE state */
00977 #define HRTIM_OUTPUTIDLELEVEL_ACTIVE     (HRTIM_OUTR_IDLES1)   /*!< Output at active level when in IDLE state */
00978 /**
00979   * @}
00980   */
00981
00982 /** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level
00983   * @{
00984   * @brief Constants defining the output level when output is in FAULT state
00985   */
00986 #define HRTIM_OUTPUTFAULTLEVEL_NONE      0x00000000U                                   /*!< The output is not affected by the fault input */
00987 #define HRTIM_OUTPUTFAULTLEVEL_ACTIVE    (HRTIM_OUTR_FAULT1_0)                        /*!< Output at active level when in FAULT state */
00988 #define HRTIM_OUTPUTFAULTLEVEL_INACTIVE  (HRTIM_OUTR_FAULT1_1)                        /*!< Output at inactive level when in FAULT state */
00989 #define HRTIM_OUTPUTFAULTLEVEL_HIGHZ     (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0)  /*!< Output is tri-stated when in FAULT state */
00990 /**
00991   * @}
00992   */
00993
00994 /** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable
00995   * @{
00996   * @brief Constants defining whether or not chopper mode is enabled for a timer
00997            output
00998   */
00999 #define HRTIM_OUTPUTCHOPPERMODE_DISABLED   0x00000000U            /*!< Output signal is not altered  */
01000 #define HRTIM_OUTPUTCHOPPERMODE_ENABLED    (HRTIM_OUTR_CHP1)     /*!< Output signal is chopped by a carrier signal  */
01001 /**
01002   * @}
01003   */
01004
01005 /** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed
01006   * @{
01007   * @brief Constants defining the idle mode entry is delayed by forcing a
01008            deadtime insertion before switching the outputs to their idle state
01009   */
01010 #define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR   0x00000000U            /*!< The programmed Idle state is applied immediately to the Output */
01011 #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED   (HRTIM_OUTR_DIDL1)    /*!< Deadtime is inserted on output before entering the idle mode */
01012 /**
01013   * @}
01014   */
01015
01016 /** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger
01017   * @{
01018   * @brief Constants defining the events that can be selected to trigger the
01019   *        capture of the timing unit counter
01020   */
01021 #define HRTIM_CAPTURETRIGGER_NONE         0x00000000U               /*!< Capture trigger is disabled */
01022 #define HRTIM_CAPTURETRIGGER_UPDATE       (HRTIM_CPT1CR_UPDCPT)    /*!< The update event triggers the Capture */
01023 #define HRTIM_CAPTURETRIGGER_EEV_1        (HRTIM_CPT1CR_EXEV1CPT)  /*!< The External event 1 triggers the Capture */
01024 #define HRTIM_CAPTURETRIGGER_EEV_2        (HRTIM_CPT1CR_EXEV2CPT)  /*!< The External event 2 triggers the Capture */
01025 #define HRTIM_CAPTURETRIGGER_EEV_3        (HRTIM_CPT1CR_EXEV3CPT)  /*!< The External event 3 triggers the Capture */
01026 #define HRTIM_CAPTURETRIGGER_EEV_4        (HRTIM_CPT1CR_EXEV4CPT)  /*!< The External event 4 triggers the Capture */
01027 #define HRTIM_CAPTURETRIGGER_EEV_5        (HRTIM_CPT1CR_EXEV5CPT)  /*!< The External event 5 triggers the Capture */
01028 #define HRTIM_CAPTURETRIGGER_EEV_6        (HRTIM_CPT1CR_EXEV6CPT)  /*!< The External event 6 triggers the Capture */
01029 #define HRTIM_CAPTURETRIGGER_EEV_7        (HRTIM_CPT1CR_EXEV7CPT)  /*!< The External event 7 triggers the Capture */
01030 #define HRTIM_CAPTURETRIGGER_EEV_8        (HRTIM_CPT1CR_EXEV8CPT)  /*!< The External event 8 triggers the Capture */
01031 #define HRTIM_CAPTURETRIGGER_EEV_9        (HRTIM_CPT1CR_EXEV9CPT)  /*!< The External event 9 triggers the Capture */
01032 #define HRTIM_CAPTURETRIGGER_EEV_10       (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */
01033 #define HRTIM_CAPTURETRIGGER_TA1_SET      (HRTIM_CPT1CR_TA1SET)    /*!< Capture is triggered by TA1 output inactive to active transition */
01034 #define HRTIM_CAPTURETRIGGER_TA1_RESET    (HRTIM_CPT1CR_TA1RST)    /*!< Capture is triggered by TA1 output active to inactive transition */
01035 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP1  (HRTIM_CPT1CR_TIMACMP1)  /*!< Timer A Compare 1 triggers Capture */
01036 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP2  (HRTIM_CPT1CR_TIMACMP2)  /*!< Timer A Compare 2 triggers Capture */
01037 #define HRTIM_CAPTURETRIGGER_TB1_SET      (HRTIM_CPT1CR_TB1SET)    /*!< Capture is triggered by TB1 output inactive to active transition */
01038 #define HRTIM_CAPTURETRIGGER_TB1_RESET    (HRTIM_CPT1CR_TB1RST)    /*!< Capture is triggered by TB1 output active to inactive transition */
01039 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP1  (HRTIM_CPT1CR_TIMBCMP1)  /*!< Timer B Compare 1 triggers Capture */
01040 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP2  (HRTIM_CPT1CR_TIMBCMP2)  /*!< Timer B Compare 2 triggers Capture */
01041 #define HRTIM_CAPTURETRIGGER_TC1_SET      (HRTIM_CPT1CR_TC1SET)    /*!< Capture is triggered by TC1 output inactive to active transition */
01042 #define HRTIM_CAPTURETRIGGER_TC1_RESET    (HRTIM_CPT1CR_TC1RST)    /*!< Capture is triggered by TC1 output active to inactive transition */
01043 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP1  (HRTIM_CPT1CR_TIMCCMP1)  /*!< Timer C Compare 1 triggers Capture */
01044 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP2  (HRTIM_CPT1CR_TIMCCMP2)  /*!< Timer C Compare 2 triggers Capture */
01045 #define HRTIM_CAPTURETRIGGER_TD1_SET      (HRTIM_CPT1CR_TD1SET)    /*!< Capture is triggered by TD1 output inactive to active transition */
01046 #define HRTIM_CAPTURETRIGGER_TD1_RESET    (HRTIM_CPT1CR_TD1RST)    /*!< Capture is triggered by TD1 output active to inactive transition */
01047 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP1  (HRTIM_CPT1CR_TIMDCMP1)  /*!< Timer D Compare 1 triggers Capture */
01048 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP2  (HRTIM_CPT1CR_TIMDCMP2)  /*!< Timer D Compare 2 triggers Capture */
01049 #define HRTIM_CAPTURETRIGGER_TE1_SET      (HRTIM_CPT1CR_TE1SET)    /*!< Capture is triggered by TE1 output inactive to active transition */
01050 #define HRTIM_CAPTURETRIGGER_TE1_RESET    (HRTIM_CPT1CR_TE1RST)    /*!< Capture is triggered by TE1 output active to inactive transition */
01051 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP1  (HRTIM_CPT1CR_TIMECMP1)  /*!< Timer E Compare 1 triggers Capture */
01052 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP2  (HRTIM_CPT1CR_TIMECMP2)  /*!< Timer E Compare 2 triggers Capture */
01053 /**
01054   * @}
01055   */
01056
01057 /** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
01058   * @{
01059   * @brief Constants defining the event filtering apploed to external events
01060   *        by a timer
01061   */
01062 #define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)
01063 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 1U */
01064 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 2U */
01065 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from counter reset/roll-over to Compare 3U */
01066 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 4U */
01067 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR1 source */
01068 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR2 source */
01069 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Blanking from another timing unit: TIMFLTR3 source */
01070 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)                                                                                                                           /*!< Blanking from another timing unit: TIMFLTR4 source */
01071 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR5 source */
01072 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR6 source */
01073 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Blanking from another timing unit: TIMFLTR7 source */
01074 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR8 source */
01075 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Windowing from counter reset/roll-over to Compare 2U */
01076 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                                                                           /*!< Windowing from counter reset/roll-over to Compare 3U */
01077 #define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)  /*!< Windowing from another timing unit: TIMWIN source */
01078 /**
01079   * @}
01080   */
01081
01082 /** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch
01083   * @{
01084   * @brief Constants defining whether or not the external event is
01085   *        memorized (latched) and generated as soon as the blanking period
01086   *        is completed or the window ends
01087   */
01088 #define HRTIM_TIMEVENTLATCH_DISABLED    (0x00000000U)           /*!< Event is ignored if it happens during a blank, or passed through during a window */
01089 #define HRTIM_TIMEVENTLATCH_ENABLED     HRTIM_EEFR1_EE1LTCH     /*!< Event is latched and delayed till the end of the blanking or windowing period */
01090 /**
01091   * @}
01092   */
01093
01094 /** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Deadtime Prescaler Ratio
01095   * @{
01096   * @brief Constants defining division ratio between the timer clock frequency
01097   *        (fHRTIM) and the deadtime generator clock (fDTG)
01098   */
01099 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8    (0x00000000U)                                                   /*!< fDTG = fHRTIM * 8U */
01100 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4    (HRTIM_DTR_DTPRSC_0)                                            /*!< fDTG = fHRTIM * 4U */
01101 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2    (HRTIM_DTR_DTPRSC_1)                                            /*!< fDTG = fHRTIM * 2U */
01102 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1    (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM */
01103 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2    (HRTIM_DTR_DTPRSC_2)                                            /*!< fDTG = fHRTIM / 2U */
01104 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM / 4U */
01105 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1)                       /*!< fDTG = fHRTIM / 8U */
01106 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16   (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)  /*!< fDTG = fHRTIM / 16U */
01107 /**
01108   * @}
01109   */
01110
01111 /** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Deadtime Rising Sign
01112   * @{
01113   * @brief Constants defining whether the deadtime is positive or negative
01114   *        (overlapping signal) on rising edge
01115   */
01116 #define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE    (0x00000000U)           /*!< Positive deadtime on rising edge */
01117 #define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE    (HRTIM_DTR_SDTR)        /*!< Negative deadtime on rising edge */
01118 /**
01119   * @}
01120   */
01121
01122 /** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Deadtime Rising Lock
01123   * @{
01124   * @brief Constants defining whether or not the deadtime (rising sign and
01125   *        value) is write protected
01126   */
01127 #define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE    (0x00000000U)           /*!< Deadtime rising value and sign is writeable */
01128 #define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK)       /*!< Deadtime rising value and sign is read-only */
01129 /**
01130   * @}
01131   */
01132
01133 /** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Deadtime Rising Sign Lock
01134   * @{
01135   * @brief Constants defining whether or not the deadtime rising sign is write
01136   *        protected
01137   */
01138 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE    (0x00000000U)           /*!< Deadtime rising sign is writeable */
01139 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK)      /*!< Deadtime rising sign is read-only */
01140 /**
01141   * @}
01142   */
01143
01144 /** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Deadtime Falling Sign
01145   * @{
01146   * @brief Constants defining whether the deadtime is positive or negative
01147   *        (overlapping signal) on falling edge
01148   */
01149 #define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE    (0x00000000U)  /*!< Positive deadtime on falling edge */
01150 #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE    (HRTIM_DTR_SDTF)        /*!< Negative deadtime on falling edge */
01151 /**
01152   * @}
01153   */
01154
01155 /** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Deadtime Falling Lock
01156   * @{
01157   * @brief Constants defining whether or not the deadtime (falling sign and
01158   *        value) is write protected
01159   */
01160 #define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE    (0x00000000U)  /*!< Deadtime falling value and sign is writeable */
01161 #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK)       /*!< Deadtime falling value and sign is read-only */
01162 /**
01163   * @}
01164   */
01165
01166 /** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Deadtime Falling Sign Lock
01167   * @{
01168   * @brief Constants defining whether or not the deadtime falling sign is write
01169   *        protected
01170   */
01171 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE    (0x00000000U)  /*!< Deadtime falling sign is writeable */
01172 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK)      /*!< Deadtime falling sign is read-only */
01173 /**
01174   * @}
01175   */
01176
01177 /** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency
01178   * @{
01179   * @brief Constants defining the frequency of the generated high frequency carrier
01180   */
01181 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV16  (0x000000U)                                                                     /*!< fCHPFRQ = fHRTIM / 16  */
01182 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV32  (HRTIM_CHPR_CARFRQ_0)                                                                    /*!< fCHPFRQ = fHRTIM / 32  */
01183 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV48  (HRTIM_CHPR_CARFRQ_1)                                                                    /*!< fCHPFRQ = fHRTIM / 48  */
01184 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV64  (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 64  */
01185 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV80  (HRTIM_CHPR_CARFRQ_2)                                                                    /*!< fCHPFRQ = fHRTIM / 80  */
01186 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV96  (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 96  */
01187 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 112  */
01188 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 128  */
01189 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3)                                                                    /*!< fCHPFRQ = fHRTIM / 144  */
01190 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 160  */
01191 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 176  */
01192 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 192  */
01193 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2)                                              /*!< fCHPFRQ = fHRTIM / 208  */
01194 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 224  */
01195 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                        /*!< fCHPFRQ = fHRTIM / 240  */
01196 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)  /*!< fCHPFRQ = fHRTIM / 256  */
01197  /**
01198   * @}
01199   */
01200
01201 /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle
01202   * @{
01203   * @brief Constants defining the duty cycle of the generated high frequency carrier
01204   *        Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
01205   */
01206 #define HRTIM_CHOPPER_DUTYCYCLE_0    (0x000000U)                                              /*!< Only 1st pulse is present */
01207 #define HRTIM_CHOPPER_DUTYCYCLE_125  (HRTIM_CHPR_CARDTY_0)                                             /*!< Duty cycle of the carrier signal is 12.5U % */
01208 #define HRTIM_CHOPPER_DUTYCYCLE_250  (HRTIM_CHPR_CARDTY_1)                                             /*!< Duty cycle of the carrier signal is 25U % */
01209 #define HRTIM_CHOPPER_DUTYCYCLE_375  (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 37.5U % */
01210 #define HRTIM_CHOPPER_DUTYCYCLE_500  (HRTIM_CHPR_CARDTY_2)                                             /*!< Duty cycle of the carrier signal is 50U % */
01211 #define HRTIM_CHOPPER_DUTYCYCLE_625  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 62.5U % */
01212 #define HRTIM_CHOPPER_DUTYCYCLE_750  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1)                       /*!< Duty cycle of the carrier signal is 75U % */
01213 #define HRTIM_CHOPPER_DUTYCYCLE_875  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5U % */
01214 /**
01215   * @}
01216   */
01217
01218 /** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width
01219   * @{
01220   * @brief Constants defining the pulse width of the first pulse of the generated
01221   *        high frequency carrier
01222   */
01223 #define HRTIM_CHOPPER_PULSEWIDTH_16   (0x000000U)                                                                 /*!< tSTPW = tHRTIM x 16  */
01224 #define HRTIM_CHOPPER_PULSEWIDTH_32   (HRTIM_CHPR_STRPW_0)                                                                 /*!< tSTPW = tHRTIM x 32  */
01225 #define HRTIM_CHOPPER_PULSEWIDTH_48   (HRTIM_CHPR_STRPW_1)                                                                 /*!< tSTPW = tHRTIM x 48  */
01226 #define HRTIM_CHOPPER_PULSEWIDTH_64   (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 64  */
01227 #define HRTIM_CHOPPER_PULSEWIDTH_80   (HRTIM_CHPR_STRPW_2)                                                                 /*!< tSTPW = tHRTIM x 80  */
01228 #define HRTIM_CHOPPER_PULSEWIDTH_96   (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 96  */
01229 #define HRTIM_CHOPPER_PULSEWIDTH_112  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 112  */
01230 #define HRTIM_CHOPPER_PULSEWIDTH_128  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 128  */
01231 #define HRTIM_CHOPPER_PULSEWIDTH_144  (HRTIM_CHPR_STRPW_3)                                                                 /*!< tSTPW = tHRTIM x 144  */
01232 #define HRTIM_CHOPPER_PULSEWIDTH_160  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 160  */
01233 #define HRTIM_CHOPPER_PULSEWIDTH_176  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 176  */
01234 #define HRTIM_CHOPPER_PULSEWIDTH_192  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 192  */
01235 #define HRTIM_CHOPPER_PULSEWIDTH_208  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2)                                            /*!< tSTPW = tHRTIM x 208  */
01236 #define HRTIM_CHOPPER_PULSEWIDTH_224  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 224  */
01237 #define HRTIM_CHOPPER_PULSEWIDTH_240  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                       /*!< tSTPW = tHRTIM x 240  */
01238 #define HRTIM_CHOPPER_PULSEWIDTH_256  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)  /*!< tSTPW = tHRTIM x 256  */
01239 /**
01240   * @}
01241   */
01242
01243 /** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options
01244   * @{
01245   * @brief Constants defining the options for synchronizing multiple HRTIM
01246   *        instances, as a master unit (generating a synchronization signal)
01247   *        or as a slave (waiting for a trigger to be synchronized)
01248   */
01249 #define HRTIM_SYNCOPTION_NONE   0x00000000U   /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */
01250 #define HRTIM_SYNCOPTION_MASTER 0x00000001U   /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/
01251 #define HRTIM_SYNCOPTION_SLAVE  0x00000002U   /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */
01252 /**
01253   * @}
01254   */
01255
01256 /** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source
01257   * @{
01258   * @brief Constants defining defining the synchronization input source
01259   */
01260 #define HRTIM_SYNCINPUTSOURCE_NONE           0x00000000U                         /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
01261 #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT  HRTIM_MCR_SYNC_IN_1                          /*!< The HRTIM is synchronized with the on-chip timer */
01262 #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT  (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0)  /*!< A positive pulse on SYNCIN input triggers the HRTIM */
01263 /**
01264   * @}
01265   */
01266
01267 /** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source
01268   * @{
01269   * @brief Constants defining the source and event to be sent on the
01270   *        synchronization outputs
01271   */
01272 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U                                     /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
01273 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1  (HRTIM_MCR_SYNC_SRC_0)                         /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
01274 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START   (HRTIM_MCR_SYNC_SRC_1)                         /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
01275 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1    (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)  /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
01276 /**
01277   * @}
01278   */
01279
01280 /** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity
01281   * @{
01282   * @brief Constants defining the routing and conditioning of the synchronization output event
01283   */
01284 #define HRTIM_SYNCOUTPUTPOLARITY_NONE      0x00000000U                                    /*!< Synchronization output event is disabled */
01285 #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE  (HRTIM_MCR_SYNC_OUT_1)                        /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
01286 #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE  (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
01287 /**
01288   * @}
01289   */
01290
01291 /** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources
01292   * @{
01293   * @brief Constants defining available sources associated to external events
01294   */
01295 #define HRTIM_EVENTSRC_1         (0x00000000U)                                  /*!< External event source 1U */
01296 #define HRTIM_EVENTSRC_2         (HRTIM_EECR1_EE1SRC_0)                         /*!< External event source 2U */
01297 #define HRTIM_EVENTSRC_3         (HRTIM_EECR1_EE1SRC_1)                         /*!< External event source 3U */
01298 #define HRTIM_EVENTSRC_4         (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)  /*!< External event source 4U */
01299 /**
01300   * @}
01301   */
01302
01303 /** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity
01304   * @{
01305   * @brief Constants defining the polarity of an external event
01306   */
01307 #define HRTIM_EVENTPOLARITY_HIGH    (0x00000000U)           /*!< External event is active high */
01308 #define HRTIM_EVENTPOLARITY_LOW     (HRTIM_EECR1_EE1POL)    /*!< External event is active low */
01309 /**
01310   * @}
01311   */
01312
01313 /** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity
01314   * @{
01315   * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
01316   *        of an external event
01317   */
01318 #define HRTIM_EVENTSENSITIVITY_LEVEL          (0x00000000U)                                  /*!< External event is active on level */
01319 #define HRTIM_EVENTSENSITIVITY_RISINGEDGE     (HRTIM_EECR1_EE1SNS_0)                         /*!< External event is active on Rising edge */
01320 #define HRTIM_EVENTSENSITIVITY_FALLINGEDGE    (HRTIM_EECR1_EE1SNS_1)                         /*!< External event is active on Falling edge */
01321 #define HRTIM_EVENTSENSITIVITY_BOTHEDGES      (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0)  /*!< External event is active on Rising and Falling edges */
01322 /**
01323   * @}
01324   */
01325
01326 /** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode
01327   * @{
01328   * @brief Constants defining whether or not an external event is programmed in
01329            fast mode
01330   */
01331
01332 #define HRTIM_EVENTFASTMODE_ENABLE      (0x00000000U)           /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
01333 #define HRTIM_EVENTFASTMODE_DISABLE     (HRTIM_EECR1_EE1FAST)   /*!< External Event is acting asynchronously on outputs (low latency mode) */
01334 /**
01335   * @}
01336   */
01337
01338 /** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter
01339   * @{
01340   * @brief Constants defining the frequency used to sample an external event 6
01341   *        input and the length (N) of the digital filter applied
01342   */
01343 #define HRTIM_EVENTFILTER_NONE      (0x00000000U)                                                                         /*!< Filter disabled */
01344 #define HRTIM_EVENTFILTER_1         (HRTIM_EECR3_EE6F_0)                                                                  /*!< fSAMPLING= fHRTIM, N=2U */
01345 #define HRTIM_EVENTFILTER_2         (HRTIM_EECR3_EE6F_1)                                                                  /*!< fSAMPLING= fHRTIM, N=4U */
01346 #define HRTIM_EVENTFILTER_3         (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fHRTIM, N=8U */
01347 #define HRTIM_EVENTFILTER_4         (HRTIM_EECR3_EE6F_2)                                                                  /*!< fSAMPLING= fEEVS/2U, N=6U */
01348 #define HRTIM_EVENTFILTER_5         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fEEVS/2U, N=8U */
01349 #define HRTIM_EVENTFILTER_6         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING= fEEVS/4U, N=6U */
01350 #define HRTIM_EVENTFILTER_7         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING= fEEVS/4U, N=8U */
01351 #define HRTIM_EVENTFILTER_8         (HRTIM_EECR3_EE6F_3)                                                                  /*!< fSAMPLING= fEEVS/8U, N=6U */
01352 #define HRTIM_EVENTFILTER_9         (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fEEVS/8U, N=8U */
01353 #define HRTIM_EVENTFILTER_10        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING= fEEVS/16U, N=5U */
01354 #define HRTIM_EVENTFILTER_11        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING= fEEVS/16U, N=6U */
01355 #define HRTIM_EVENTFILTER_12        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2)                                             /*!< fSAMPLING= fEEVS/16U, N=8U */
01356 #define HRTIM_EVENTFILTER_13        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_0)                       /*!< fSAMPLING= fEEVS/32U, N=5U */
01357 #define HRTIM_EVENTFILTER_14        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1)                       /*!< fSAMPLING= fEEVS/32U, N=6U */
01358 #define HRTIM_EVENTFILTER_15        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)  /*!< fSAMPLING= fEEVS/32U, N=8U */
01359 /**
01360   * @}
01361   */
01362
01363 /** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler
01364   * @{
01365   * @brief Constants defining division ratio between the timer clock frequency
01366   *        fHRTIM) and the external event signal sampling clock (fEEVS)
01367   *        used by the digital filters
01368   */
01369 #define HRTIM_EVENTPRESCALER_DIV1    (0x00000000U)                                   /*!< fEEVS=fHRTIM */
01370 #define HRTIM_EVENTPRESCALER_DIV2    (HRTIM_EECR3_EEVSD_0)                           /*!< fEEVS=fHRTIM / 2U */
01371 #define HRTIM_EVENTPRESCALER_DIV4    (HRTIM_EECR3_EEVSD_1)                           /*!< fEEVS=fHRTIM / 4U */
01372 #define HRTIM_EVENTPRESCALER_DIV8    (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0)     /*!< fEEVS=fHRTIM / 8U */
01373 /**
01374   * @}
01375   */
01376
01377 /** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources
01378   * @{
01379   * @brief Constants defining whether a faults is be triggered by any external
01380   *        or internal fault source
01381   */
01382 #define HRTIM_FAULTSOURCE_DIGITALINPUT      (0x00000000U)     /*!< Fault input is FLT input pin */
01383 #define HRTIM_FAULTSOURCE_INTERNAL          (HRTIM_FLTINR1_FLT1SRC)    /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
01384 /**
01385   * @}
01386   */
01387
01388 /** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity
01389   * @{
01390   * @brief Constants defining the polarity of a fault event
01391   */
01392 #define HRTIM_FAULTPOLARITY_LOW     (0x00000000U)   /*!< Fault input is active low */
01393 #define HRTIM_FAULTPOLARITY_HIGH    (HRTIM_FLTINR1_FLT1P)    /*!< Fault input is active high */
01394 /**
01395   * @}
01396   */
01397
01398 /** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter
01399   * @{
01400   * @ brief Constants defining the frequency used to sample the fault input and
01401   *         the length (N) of the digital filter applied
01402   */
01403 #define HRTIM_FAULTFILTER_NONE      (0x00000000U)                                                                                    /*!< Filter disabled */
01404 #define HRTIM_FAULTFILTER_1         (HRTIM_FLTINR1_FLT1F_0)                                                                          /*!< fSAMPLING= fHRTIM, N=2U */
01405 #define HRTIM_FAULTFILTER_2         (HRTIM_FLTINR1_FLT1F_1)                                                                          /*!< fSAMPLING= fHRTIM, N=4U */
01406 #define HRTIM_FAULTFILTER_3         (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fHRTIM, N=8U */
01407 #define HRTIM_FAULTFILTER_4         (HRTIM_FLTINR1_FLT1F_2)                                                                          /*!< fSAMPLING= fFLTS/2U, N=6U */
01408 #define HRTIM_FAULTFILTER_5         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/2U, N=8U */
01409 #define HRTIM_FAULTFILTER_6         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/4U, N=6U */
01410 #define HRTIM_FAULTFILTER_7         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/4U, N=8U */
01411 #define HRTIM_FAULTFILTER_8         (HRTIM_FLTINR1_FLT1F_3)                                                                          /*!< fSAMPLING= fFLTS/8U, N=6U */
01412 #define HRTIM_FAULTFILTER_9         (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/8U, N=8U */
01413 #define HRTIM_FAULTFILTER_10        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/16U, N=5U */
01414 #define HRTIM_FAULTFILTER_11        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/16U, N=6U */
01415 #define HRTIM_FAULTFILTER_12        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2)                                                  /*!< fSAMPLING= fFLTS/16U, N=8U */
01416 #define HRTIM_FAULTFILTER_13        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/32U, N=5U */
01417 #define HRTIM_FAULTFILTER_14        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                          /*!< fSAMPLING= fFLTS/32U, N=6U */
01418 #define HRTIM_FAULTFILTER_15        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)  /*!< fSAMPLING= fFLTS/32U, N=8U */
01419 /**
01420   * @}
01421   */
01422
01423 /** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock
01424   * @{
01425   * @brief Constants defining whether or not the fault programming bits are
01426            write protected
01427   */
01428 #define HRTIM_FAULTLOCK_READWRITE       (0x00000000U)                /*!< Fault settings bits are read/write */
01429 #define HRTIM_FAULTLOCK_READONLY        (HRTIM_FLTINR1_FLT1LCK)     /*!< Fault settings bits are read only */
01430 /**
01431   * @}
01432   */
01433
01434 /** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler
01435   * @{
01436   * @brief Constants defining the division ratio between the timer clock
01437   *        frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
01438   *        by the digital filters.
01439   */
01440 #define HRTIM_FAULTPRESCALER_DIV1    (0x00000000U)                                     /*!< fFLTS=fHRTIM */
01441 #define HRTIM_FAULTPRESCALER_DIV2    (HRTIM_FLTINR2_FLTSD_0)                           /*!< fFLTS=fHRTIM / 2U */
01442 #define HRTIM_FAULTPRESCALER_DIV4    (HRTIM_FLTINR2_FLTSD_1)                           /*!< fFLTS=fHRTIM / 4U */
01443 #define HRTIM_FAULTPRESCALER_DIV8    (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0)   /*!< fFLTS=fHRTIM / 8U */
01444 /**
01445   * @}
01446   */
01447
01448 /** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode
01449   * @{
01450   * @brief Constants defining if the burst mode is entered once or if it is
01451   *        continuously operating
01452   */
01453 #define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U)  /*!< Burst mode operates in single shot mode */
01454 #define HRTIM_BURSTMODE_CONTINOUS   (HRTIM_BMCR_BMOM)      /*!< Burst mode operates in continuous mode */
01455 /**
01456   * @}
01457   */
01458
01459 /** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source
01460   * @{
01461   * @brief Constants defining the clock source for the burst mode counter
01462   */
01463 #define HRTIM_BURSTMODECLOCKSOURCE_MASTER     (0x00000000U)                                                   /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
01464 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A    (HRTIM_BMCR_BMCLK_0)                                            /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
01465 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B    (HRTIM_BMCR_BMCLK_1)                                            /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
01466 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C    (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
01467 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D    (HRTIM_BMCR_BMCLK_2)                                            /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
01468 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E    (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
01469 #define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1)                       /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
01470 #define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)  /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
01471 #define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO  (HRTIM_BMCR_BMCLK_3)                                            /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
01472 #define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM     (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1)                       /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
01473 /**
01474   * @}
01475   */
01476
01477 /** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler
01478   * @{
01479   * @brief Constants defining the prescaling ratio of the fHRTIM clock
01480   *        for the burst mode controller
01481   */
01482 #define HRTIM_BURSTMODEPRESCALER_DIV1     (0x00000000U)                                                                           /*!< fBRST = fHRTIM */
01483 #define HRTIM_BURSTMODEPRESCALER_DIV2     (HRTIM_BMCR_BMPRSC_0)                                                                   /*!< fBRST = fHRTIM/2U */
01484 #define HRTIM_BURSTMODEPRESCALER_DIV4     (HRTIM_BMCR_BMPRSC_1)                                                                   /*!< fBRST = fHRTIM/4U */
01485 #define HRTIM_BURSTMODEPRESCALER_DIV8     (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/8U */
01486 #define HRTIM_BURSTMODEPRESCALER_DIV16    (HRTIM_BMCR_BMPRSC_2)                                                                   /*!< fBRST = fHRTIM/16U */
01487 #define HRTIM_BURSTMODEPRESCALER_DIV32    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/32U */
01488 #define HRTIM_BURSTMODEPRESCALER_DIV64    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/64U */
01489 #define HRTIM_BURSTMODEPRESCALER_DIV128   (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/128U */
01490 #define HRTIM_BURSTMODEPRESCALER_DIV256   (HRTIM_BMCR_BMPRSC_3)                                                                   /*!< fBRST = fHRTIM/256U */
01491 #define HRTIM_BURSTMODEPRESCALER_DIV512   (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/512U */
01492 #define HRTIM_BURSTMODEPRESCALER_DIV1024  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/1024U */
01493 #define HRTIM_BURSTMODEPRESCALER_DIV2048  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/2048U*/
01494 #define HRTIM_BURSTMODEPRESCALER_DIV4096  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2)                                             /*!< fBRST = fHRTIM/4096U */
01495 #define HRTIM_BURSTMODEPRESCALER_DIV8192  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/8192U */
01496 #define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                       /*!< fBRST = fHRTIM/16384U */
01497 #define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768U */
01498 /**
01499   * @}
01500   */
01501
01502 /** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable
01503   * @{
01504   * @brief Constants defining whether or not burst mode registers preload
01505            mechanism is enabled, i.e. a write access into a preloadable register
01506           (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
01507   */
01508 #define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U)  /*!< Preload disabled: the write access is directly done into active registers */
01509 #define HRIM_BURSTMODEPRELOAD_ENABLED  (HRTIM_BMCR_BMPREN)     /*!< Preload enabled: the write access is done into preload registers */
01510 /**
01511   * @}
01512   */
01513
01514 /** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger
01515   * @{
01516   * @brief Constants defining the events that can be used tor trig the burst
01517   *        mode operation
01518   */
01519 #define HRTIM_BURSTMODETRIGGER_NONE               0x00000000U              /*!<  No trigger */
01520 #define HRTIM_BURSTMODETRIGGER_MASTER_RESET       (HRTIM_BMTRGR_MSTRST)   /*!<  Master reset */
01521 #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION  (HRTIM_BMTRGR_MSTREP)   /*!<  Master repetition */
01522 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP1        (HRTIM_BMTRGR_MSTCMP1)  /*!<  Master compare 1U */
01523 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP2        (HRTIM_BMTRGR_MSTCMP2)  /*!<  Master compare 2U */
01524 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP3        (HRTIM_BMTRGR_MSTCMP3)  /*!<  Master compare 3U */
01525 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP4        (HRTIM_BMTRGR_MSTCMP4)  /*!<  Master compare 4U */
01526 #define HRTIM_BURSTMODETRIGGER_TIMERA_RESET       (HRTIM_BMTRGR_TARST)    /*!< Timer A reset  */
01527 #define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION  (HRTIM_BMTRGR_TAREP)    /*!< Timer A repetition  */
01528 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1        (HRTIM_BMTRGR_TACMP1)   /*!< Timer A compare 1  */
01529 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2        (HRTIM_BMTRGR_TACMP2)   /*!< Timer A compare 2  */
01530 #define HRTIM_BURSTMODETRIGGER_TIMERB_RESET       (HRTIM_BMTRGR_TBRST)    /*!< Timer B reset  */
01531 #define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION  (HRTIM_BMTRGR_TBREP)    /*!< Timer B repetition  */
01532 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1        (HRTIM_BMTRGR_TBCMP1)   /*!< Timer B compare 1  */
01533 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2        (HRTIM_BMTRGR_TBCMP2)   /*!< Timer B compare 2  */
01534 #define HRTIM_BURSTMODETRIGGER_TIMERC_RESET       (HRTIM_BMTRGR_TCRST)    /*!< Timer C reset  */
01535 #define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION  (HRTIM_BMTRGR_TCREP)    /*!< Timer C repetition  */
01536 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1        (HRTIM_BMTRGR_TCCMP1)   /*!< Timer C compare 1  */
01537 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2        (HRTIM_BMTRGR_TCCMP2)   /*!< Timer C compare 2  */
01538 #define HRTIM_BURSTMODETRIGGER_TIMERD_RESET       (HRTIM_BMTRGR_TDRST)    /*!< Timer D reset  */
01539 #define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION  (HRTIM_BMTRGR_TDREP)    /*!< Timer D repetition  */
01540 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1        (HRTIM_BMTRGR_TDCMP1)   /*!< Timer D compare 1  */
01541 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2        (HRTIM_BMTRGR_TDCMP2)   /*!< Timer D compare 2  */
01542 #define HRTIM_BURSTMODETRIGGER_TIMERE_RESET       (HRTIM_BMTRGR_TERST)    /*!< Timer E reset  */
01543 #define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION  (HRTIM_BMTRGR_TEREP)    /*!< Timer E repetition  */
01544 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1        (HRTIM_BMTRGR_TECMP1)   /*!< Timer E compare 1  */
01545 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2        (HRTIM_BMTRGR_TECMP2)   /*!< Timer E compare 2  */
01546 #define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7      (HRTIM_BMTRGR_TAEEV7)   /*!< Timer A period following External Event 7  */
01547 #define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8      (HRTIM_BMTRGR_TDEEV8)   /*!< Timer D period following External Event 8  */
01548 #define HRTIM_BURSTMODETRIGGER_EVENT_7            (HRTIM_BMTRGR_EEV7)     /*!< External Event 7 (timer A filters applied) */
01549 #define HRTIM_BURSTMODETRIGGER_EVENT_8            (HRTIM_BMTRGR_EEV8)     /*!< External Event 8 (timer D filters applied)*/
01550 #define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP       (HRTIM_BMTRGR_OCHPEV)   /*!< On-chip Event */
01551 /**
01552   * @}
01553   */
01554
01555 /** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source
01556   * @{
01557   * @brief constants defining the source triggering the update of the
01558      HRTIM_ADCxR register (transfer from preload to active register).
01559   */
01560 #define HRTIM_ADCTRIGGERUPDATE_MASTER  0x00000000U                                    /*!< Master timer */
01561 #define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0)                        /*!< Timer A */
01562 #define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1)                        /*!< Timer B */
01563 #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */
01564 #define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2)                        /*!< Timer D */
01565 #define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */
01566 /**
01567   * @}
01568   */
01569
01570 /** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event
01571   * @{
01572   * @brief constants defining the events triggering ADC conversion.
01573   *        HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
01574   *        HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
01575   */
01576 #define HRTIM_ADCTRIGGEREVENT13_NONE           0x00000000U               /*!< No ADC trigger event */
01577 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1    (HRTIM_ADC1R_AD1MC1)     /*!< ADC Trigger on master compare 1U */
01578 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2    (HRTIM_ADC1R_AD1MC2)     /*!< ADC Trigger on master compare 2U */
01579 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3    (HRTIM_ADC1R_AD1MC3)     /*!< ADC Trigger on master compare 3U */
01580 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4    (HRTIM_ADC1R_AD1MC4)     /*!< ADC Trigger on master compare 4U */
01581 #define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD  (HRTIM_ADC1R_AD1MPER)    /*!< ADC Trigger on master period */
01582 #define HRTIM_ADCTRIGGEREVENT13_EVENT_1        (HRTIM_ADC1R_AD1EEV1)    /*!< ADC Trigger on external event 1U */
01583 #define HRTIM_ADCTRIGGEREVENT13_EVENT_2        (HRTIM_ADC1R_AD1EEV2)    /*!< ADC Trigger on external event 2U */
01584 #define HRTIM_ADCTRIGGEREVENT13_EVENT_3        (HRTIM_ADC1R_AD1EEV3)    /*!< ADC Trigger on external event 3U */
01585 #define HRTIM_ADCTRIGGEREVENT13_EVENT_4        (HRTIM_ADC1R_AD1EEV4)    /*!< ADC Trigger on external event 4U */
01586 #define HRTIM_ADCTRIGGEREVENT13_EVENT_5        (HRTIM_ADC1R_AD1EEV5)    /*!< ADC Trigger on external event 5U */
01587 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2    (HRTIM_ADC1R_AD1TAC2)    /*!< ADC Trigger on Timer A compare 2U */
01588 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3    (HRTIM_ADC1R_AD1TAC3)    /*!< ADC Trigger on Timer A compare 3U */
01589 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4    (HRTIM_ADC1R_AD1TAC4)    /*!< ADC Trigger on Timer A compare 4U */
01590 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD  (HRTIM_ADC1R_AD1TAPER)   /*!< ADC Trigger on Timer A period */
01591 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET   (HRTIM_ADC1R_AD1TARST)   /*!< ADC Trigger on Timer A reset */
01592 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2    (HRTIM_ADC1R_AD1TBC2)    /*!< ADC Trigger on Timer B compare 2U */
01593 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3    (HRTIM_ADC1R_AD1TBC3)    /*!< ADC Trigger on Timer B compare 3U */
01594 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4    (HRTIM_ADC1R_AD1TBC4)    /*!< ADC Trigger on Timer B compare 4U */
01595 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD  (HRTIM_ADC1R_AD1TBPER)   /*!< ADC Trigger on Timer B period */
01596 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET   (HRTIM_ADC1R_AD1TBRST)   /*!< ADC Trigger on Timer B reset */
01597 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2    (HRTIM_ADC1R_AD1TCC2)    /*!< ADC Trigger on Timer C compare 2U */
01598 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3    (HRTIM_ADC1R_AD1TCC3)    /*!< ADC Trigger on Timer C compare 3U */
01599 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4    (HRTIM_ADC1R_AD1TCC4)    /*!< ADC Trigger on Timer C compare 4U */
01600 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD  (HRTIM_ADC1R_AD1TCPER)   /*!< ADC Trigger on Timer C period */
01601 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2    (HRTIM_ADC1R_AD1TDC2)    /*!< ADC Trigger on Timer D compare 2U */
01602 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3    (HRTIM_ADC1R_AD1TDC3)    /*!< ADC Trigger on Timer D compare 3U */
01603 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4    (HRTIM_ADC1R_AD1TDC4)    /*!< ADC Trigger on Timer D compare 4U */
01604 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD  (HRTIM_ADC1R_AD1TDPER)   /*!< ADC Trigger on Timer D period */
01605 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2    (HRTIM_ADC1R_AD1TEC2)    /*!< ADC Trigger on Timer E compare 2U */
01606 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3    (HRTIM_ADC1R_AD1TEC3)    /*!< ADC Trigger on Timer E compare 3U */
01607 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4    (HRTIM_ADC1R_AD1TEC4)    /*!< ADC Trigger on Timer E compare 4U */
01608 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD  (HRTIM_ADC1R_AD1TEPER)   /*!< ADC Trigger on Timer E period */
01609
01610 #define HRTIM_ADCTRIGGEREVENT24_NONE           0x00000000U               /*!< No ADC trigger event */
01611 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1    (HRTIM_ADC2R_AD2MC1)     /*!< ADC Trigger on master compare 1U */
01612 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2    (HRTIM_ADC2R_AD2MC2)     /*!< ADC Trigger on master compare 2U */
01613 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3    (HRTIM_ADC2R_AD2MC3)     /*!< ADC Trigger on master compare 3U */
01614 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4    (HRTIM_ADC2R_AD2MC4)     /*!< ADC Trigger on master compare 4U */
01615 #define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD  (HRTIM_ADC2R_AD2MPER)    /*!< ADC Trigger on master period */
01616 #define HRTIM_ADCTRIGGEREVENT24_EVENT_6        (HRTIM_ADC2R_AD2EEV6)    /*!< ADC Trigger on external event 6U */
01617 #define HRTIM_ADCTRIGGEREVENT24_EVENT_7        (HRTIM_ADC2R_AD2EEV7)    /*!< ADC Trigger on external event 7U */
01618 #define HRTIM_ADCTRIGGEREVENT24_EVENT_8        (HRTIM_ADC2R_AD2EEV8)    /*!< ADC Trigger on external event 8U */
01619 #define HRTIM_ADCTRIGGEREVENT24_EVENT_9        (HRTIM_ADC2R_AD2EEV9)    /*!< ADC Trigger on external event 9U */
01620 #define HRTIM_ADCTRIGGEREVENT24_EVENT_10       (HRTIM_ADC2R_AD2EEV10)   /*!< ADC Trigger on external event 10U */
01621 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2    (HRTIM_ADC2R_AD2TAC2)    /*!< ADC Trigger on Timer A compare 2U */
01622 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3    (HRTIM_ADC2R_AD2TAC3)    /*!< ADC Trigger on Timer A compare 3U */
01623 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4    (HRTIM_ADC2R_AD2TAC4)    /*!< ADC Trigger on Timer A compare 4U */
01624 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD  (HRTIM_ADC2R_AD2TAPER)   /*!< ADC Trigger on Timer A period */
01625 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2    (HRTIM_ADC2R_AD2TBC2)    /*!< ADC Trigger on Timer B compare 2U */
01626 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3    (HRTIM_ADC2R_AD2TBC3)    /*!< ADC Trigger on Timer B compare 3U */
01627 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4    (HRTIM_ADC2R_AD2TBC4)    /*!< ADC Trigger on Timer B compare 4U */
01628 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD  (HRTIM_ADC2R_AD2TBPER)   /*!< ADC Trigger on Timer B period */
01629 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2    (HRTIM_ADC2R_AD2TCC2)    /*!< ADC Trigger on Timer C compare 2U */
01630 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3    (HRTIM_ADC2R_AD2TCC3)    /*!< ADC Trigger on Timer C compare 3U */
01631 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4    (HRTIM_ADC2R_AD2TCC4)    /*!< ADC Trigger on Timer C compare 4U */
01632 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD  (HRTIM_ADC2R_AD2TCPER)   /*!< ADC Trigger on Timer C period */
01633 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET   (HRTIM_ADC2R_AD2TCRST)   /*!< ADC Trigger on Timer C reset */
01634 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2    (HRTIM_ADC2R_AD2TDC2)    /*!< ADC Trigger on Timer D compare 2U */
01635 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3    (HRTIM_ADC2R_AD2TDC3)    /*!< ADC Trigger on Timer D compare 3U */
01636 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4    (HRTIM_ADC2R_AD2TDC4)    /*!< ADC Trigger on Timer D compare 4U */
01637 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD  (HRTIM_ADC2R_AD2TDPER)   /*!< ADC Trigger on Timer D period */
01638 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET   (HRTIM_ADC2R_AD2TDRST)   /*!< ADC Trigger on Timer D reset */
01639 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2    (HRTIM_ADC2R_AD2TEC2)    /*!< ADC Trigger on Timer E compare 2U */
01640 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3    (HRTIM_ADC2R_AD2TEC3)    /*!< ADC Trigger on Timer E compare 3U */
01641 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4    (HRTIM_ADC2R_AD2TEC4)    /*!< ADC Trigger on Timer E compare 4U */
01642 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET   (HRTIM_ADC2R_AD2TERST)   /*!< ADC Trigger on Timer E reset */
01643
01644 /**
01645   * @}
01646   */
01647
01648 /** @defgroup HRTIM_DLL_Calibration_Rate HRTIM DLL Calibration Rate
01649   * @{
01650   * @brief Constants defining the DLL calibration periods (in micro seconds)
01651   */
01652 #define HRTIM_SINGLE_CALIBRATION    0xFFFFFFFFU                           /*!< Non periodic DLL calibration */
01653 #define HRTIM_CALIBRATIONRATE_7300  0x00000000U                           /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (7.3 ms) */
01654 #define HRTIM_CALIBRATIONRATE_910   (HRTIM_DLLCR_CALRTE_0)                         /*!< Periodic DLL calibration: T = 131072U * tHRTIM (910 ms) */
01655 #define HRTIM_CALIBRATIONRATE_114   (HRTIM_DLLCR_CALRTE_1)                         /*!< Periodic DLL calibration: T = 16384U * tHRTIM (114 ms) */
01656 #define HRTIM_CALIBRATIONRATE_14    (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)  /*!< Periodic DLL calibration: T = 2048U * tHRTIM (14 ms) */
01657 /**
01658   * @}
01659   */
01660
01661 /** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update
01662   * @{
01663   * @brief Constants defining the registers that can be written during a burst
01664   *        DMA operation
01665   */
01666 #define HRTIM_BURSTDMA_NONE  0x00000000U      /*!< No register is updated by Burst DMA accesses */
01667 #define HRTIM_BURSTDMA_CR    (HRTIM_BDTUPR_TIMCR)      /*!< MCR or TIMxCR register is updated by Burst DMA accesses */
01668 #define HRTIM_BURSTDMA_ICR   (HRTIM_BDTUPR_TIMICR)     /*!< MICR or TIMxICR register is updated by Burst DMA accesses */
01669 #define HRTIM_BURSTDMA_DIER  (HRTIM_BDTUPR_TIMDIER)    /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */
01670 #define HRTIM_BURSTDMA_CNT   (HRTIM_BDTUPR_TIMCNT)     /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */
01671 #define HRTIM_BURSTDMA_PER   (HRTIM_BDTUPR_TIMPER)     /*!< MPER or PERxR register is updated by Burst DMA accesses */
01672 #define HRTIM_BURSTDMA_REP   (HRTIM_BDTUPR_TIMREP)     /*!< MREPR or REPxR register is updated by Burst DMA accesses */
01673 #define HRTIM_BURSTDMA_CMP1  (HRTIM_BDTUPR_TIMCMP1)    /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */
01674 #define HRTIM_BURSTDMA_CMP2  (HRTIM_BDTUPR_TIMCMP2)    /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */
01675 #define HRTIM_BURSTDMA_CMP3  (HRTIM_BDTUPR_TIMCMP3)    /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */
01676 #define HRTIM_BURSTDMA_CMP4  (HRTIM_BDTUPR_TIMCMP4)    /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */
01677 #define HRTIM_BURSTDMA_DTR   (HRTIM_BDTUPR_TIMDTR)     /*!< TDxR register is updated by Burst DMA accesses */
01678 #define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R)   /*!< SET1R register is updated by Burst DMA accesses */
01679 #define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R)   /*!< RST1R register is updated by Burst DMA accesses */
01680 #define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R)   /*!< SET2R register is updated by Burst DMA accesses */
01681 #define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R)   /*!< RST1R register is updated by Burst DMA accesses */
01682 #define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1)   /*!< EEFxR1 register is updated by Burst DMA accesses */
01683 #define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2)   /*!< EEFxR2 register is updated by Burst DMA accesses */
01684 #define HRTIM_BURSTDMA_RSTR  (HRTIM_BDTUPR_TIMRSTR)    /*!< RSTxR register is updated by Burst DMA accesses */
01685 #define HRTIM_BURSTDMA_CHPR  (HRTIM_BDTUPR_TIMCHPR)    /*!< CHPxR register is updated by Burst DMA accesses */
01686 #define HRTIM_BURSTDMA_OUTR  (HRTIM_BDTUPR_TIMOUTR)    /*!< OUTxR register is updated by Burst DMA accesses */
01687 #define HRTIM_BURSTDMA_FLTR  (HRTIM_BDTUPR_TIMFLTR)    /*!< FLTxR register is updated by Burst DMA accesses */
01688 /**
01689   * @}
01690   */
01691
01692 /** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control
01693   * @{
01694   * @brief Constants used to enable or disable the burst mode controller
01695   */
01696 #define HRTIM_BURSTMODECTL_DISABLED 0x00000000U /*!< Burst mode disabled */
01697 #define HRTIM_BURSTMODECTL_ENABLED  (HRTIM_BMCR_BME)     /*!< Burst mode enabled */
01698 /**
01699   * @}
01700   */
01701
01702 /** @defgroup HRTIM_Fault_Mode_Control  HRTIM Fault Mode Control
01703   * @{
01704   * @brief Constants used to enable or disable a fault channel
01705   */
01706 #define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /*!< Fault channel is disabled */
01707 #define HRTIM_FAULTMODECTL_ENABLED  0x00000001U /*!< Fault channel is  enabled */
01708
01709 #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
01710     (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED)  || \
01711      ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))
01712 /**
01713   * @}
01714   */
01715
01716 /** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update
01717   * @{
01718   * @brief Constants used to force timer registers update
01719   */
01720 #define HRTIM_TIMERUPDATE_MASTER    (HRTIM_CR2_MSWU)     /*!< Forces an immediate transfer from the preload to the active register in the master timer */
01721 #define HRTIM_TIMERUPDATE_A         (HRTIM_CR2_TASWU)    /*!< Forces an immediate transfer from the preload to the active register in the timer A */
01722 #define HRTIM_TIMERUPDATE_B         (HRTIM_CR2_TBSWU)    /*!< Forces an immediate transfer from the preload to the active register in the timer B */
01723 #define HRTIM_TIMERUPDATE_C         (HRTIM_CR2_TCSWU)    /*!< Forces an immediate transfer from the preload to the active register in the timer C */
01724 #define HRTIM_TIMERUPDATE_D         (HRTIM_CR2_TDSWU)    /*!< Forces an immediate transfer from the preload to the active register in the timer D */
01725 #define HRTIM_TIMERUPDATE_E         (HRTIM_CR2_TESWU)    /*!< Forces an immediate transfer from the preload to the active register in the timer E */
01726 /**
01727   * @}
01728   */
01729
01730 /** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset
01731   * @{
01732   * @brief Constants used to force timer counter reset
01733   */
01734 #define HRTIM_TIMERRESET_MASTER    (HRTIM_CR2_MRST)     /*!< Resets the master timer counter */
01735 #define HRTIM_TIMERRESET_TIMER_A   (HRTIM_CR2_TARST)    /*!< Resets the timer A counter */
01736 #define HRTIM_TIMERRESET_TIMER_B   (HRTIM_CR2_TBRST)    /*!< Resets the timer B counter */
01737 #define HRTIM_TIMERRESET_TIMER_C   (HRTIM_CR2_TCRST)    /*!< Resets the timer C counter */
01738 #define HRTIM_TIMERRESET_TIMER_D   (HRTIM_CR2_TDRST)    /*!< Resets the timer D counter */
01739 #define HRTIM_TIMERRESET_TIMER_E   (HRTIM_CR2_TERST)    /*!< Resets the timer E counter */
01740 /**
01741   * @}
01742   */
01743
01744 /** @defgroup HRTIM_Output_Level HRTIM Output Level
01745   * @{
01746   * @brief Constants defining the level of a timer output
01747   */
01748 #define HRTIM_OUTPUTLEVEL_ACTIVE     (0x00000001U) /*!< Forces the output to its active state */
01749 #define HRTIM_OUTPUTLEVEL_INACTIVE   (0x00000002U) /*!< Forces the output to its inactive state */
01750
01751 #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
01752     (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE)  || \
01753      ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
01754 /**
01755   * @}
01756   */
01757
01758 /** @defgroup HRTIM_Output_State HRTIM Output State
01759   * @{
01760   * @brief Constants defining the state of a timer output
01761   */
01762 #define HRTIM_OUTPUTSTATE_IDLE     (0x00000001U)  /*!< Main operating mode, where the output can take the active or
01763                                                               inactive level as programmed in the crossbar unit */
01764 #define HRTIM_OUTPUTSTATE_RUN      (0x00000002U)  /*!< Default operating state (e.g. after an HRTIM reset, when the
01765                                                               outputs are disabled by software or during a burst mode operation */
01766 #define HRTIM_OUTPUTSTATE_FAULT    (0x00000003U)  /*!< Safety state, entered in case of a shut-down request on
01767                                                               FAULTx inputs */
01768 /**
01769   * @}
01770   */
01771
01772 /** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status
01773   * @{
01774   * @brief Constants defining the operating state of the burst mode controller
01775   */
01776 #define HRTIM_BURSTMODESTATUS_NORMAL   0x00000000U /*!< Normal operation */
01777 #define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT)   /*!< Burst operation on-going */
01778 /**
01779   * @}
01780   */
01781
01782 /** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status
01783   * @{
01784   * @brief Constants defining on which output the signal is currently applied
01785   *        in push-pull mode
01786   */
01787 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1    0x00000000U   /*!< Signal applied on output 1 and output 2 forced inactive */
01788 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2   (HRTIM_TIMISR_CPPSTAT)  /*!< Signal applied on output 2 and output 1 forced inactive */
01789 /**
01790   * @}
01791   */
01792
01793 /** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status
01794   * @{
01795   * @brief Constants defining on which output the signal was applied, in
01796   *        push-pull mode balanced fault mode or delayed idle mode, when the
01797   *        protection was triggered
01798   */
01799 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1    0x00000000U      /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
01800 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2   (HRTIM_TIMISR_IPPSTAT)     /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
01801 /**
01802   * @}
01803   */
01804
01805 /** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable
01806   * @{
01807   */
01808 #define HRTIM_IT_NONE           0x00000000U  /*!< No interrupt enabled */
01809 #define HRTIM_IT_FLT1           HRTIM_IER_FLT1        /*!< Fault 1 interrupt enable */
01810 #define HRTIM_IT_FLT2           HRTIM_IER_FLT2        /*!< Fault 2 interrupt enable */
01811 #define HRTIM_IT_FLT3           HRTIM_IER_FLT3        /*!< Fault 3 interrupt enable */
01812 #define HRTIM_IT_FLT4           HRTIM_IER_FLT4        /*!< Fault 4 interrupt enable */
01813 #define HRTIM_IT_FLT5           HRTIM_IER_FLT5        /*!< Fault 5 interrupt enable */
01814 #define HRTIM_IT_SYSFLT         HRTIM_IER_SYSFLT      /*!< System Fault interrupt enable */
01815 #define HRTIM_IT_DLLRDY         HRTIM_IER_DLLRDY      /*!< DLL ready interrupt enable */
01816 #define HRTIM_IT_BMPER          HRTIM_IER_BMPER       /*!<  Burst mode period interrupt enable */
01817 /**
01818   * @}
01819   */
01820
01821 /** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable
01822   * @{
01823   */
01824 #define HRTIM_MASTER_IT_NONE         0x00000000U  /*!< No interrupt enabled */
01825 #define HRTIM_MASTER_IT_MCMP1        HRTIM_MDIER_MCMP1IE   /*!< Master compare 1 interrupt enable */
01826 #define HRTIM_MASTER_IT_MCMP2        HRTIM_MDIER_MCMP2IE   /*!< Master compare 2 interrupt enable */
01827 #define HRTIM_MASTER_IT_MCMP3        HRTIM_MDIER_MCMP3IE   /*!< Master compare 3 interrupt enable */
01828 #define HRTIM_MASTER_IT_MCMP4        HRTIM_MDIER_MCMP4IE   /*!< Master compare 4 interrupt enable */
01829 #define HRTIM_MASTER_IT_MREP         HRTIM_MDIER_MREPIE    /*!< Master Repetition interrupt enable */
01830 #define HRTIM_MASTER_IT_SYNC         HRTIM_MDIER_SYNCIE    /*!< Synchronization input interrupt enable */
01831 #define HRTIM_MASTER_IT_MUPD         HRTIM_MDIER_MUPDIE    /*!< Master update interrupt enable */
01832 /**
01833   * @}
01834   */
01835
01836 /** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable
01837   * @{
01838   */
01839 #define HRTIM_TIM_IT_NONE       0x00000000U      /*!< No interrupt enabled */
01840 #define HRTIM_TIM_IT_CMP1       HRTIM_TIMDIER_CMP1IE      /*!< Timer compare 1 interrupt enable */
01841 #define HRTIM_TIM_IT_CMP2       HRTIM_TIMDIER_CMP2IE      /*!< Timer compare 2 interrupt enable */
01842 #define HRTIM_TIM_IT_CMP3       HRTIM_TIMDIER_CMP3IE      /*!< Timer compare 3 interrupt enable */
01843 #define HRTIM_TIM_IT_CMP4       HRTIM_TIMDIER_CMP4IE      /*!< Timer compare 4 interrupt enable */
01844 #define HRTIM_TIM_IT_REP        HRTIM_TIMDIER_REPIE       /*!< Timer repetition interrupt enable */
01845 #define HRTIM_TIM_IT_UPD        HRTIM_TIMDIER_UPDIE       /*!< Timer update interrupt enable */
01846 #define HRTIM_TIM_IT_CPT1       HRTIM_TIMDIER_CPT1IE      /*!< Timer capture 1 interrupt enable */
01847 #define HRTIM_TIM_IT_CPT2       HRTIM_TIMDIER_CPT2IE      /*!< Timer capture 2 interrupt enable */
01848 #define HRTIM_TIM_IT_SET1       HRTIM_TIMDIER_SET1IE      /*!< Timer output 1 set interrupt enable */
01849 #define HRTIM_TIM_IT_RST1       HRTIM_TIMDIER_RST1IE      /*!< Timer output 1 reset interrupt enable */
01850 #define HRTIM_TIM_IT_SET2       HRTIM_TIMDIER_SET2IE      /*!< Timer output 2 set interrupt enable */
01851 #define HRTIM_TIM_IT_RST2       HRTIM_TIMDIER_RST2IE      /*!< Timer output 2 reset interrupt enable */
01852 #define HRTIM_TIM_IT_RST        HRTIM_TIMDIER_RSTIE       /*!< Timer reset interrupt enable */
01853 #define HRTIM_TIM_IT_DLYPRT     HRTIM_TIMDIER_DLYPRTIE    /*!< Timer delay protection interrupt enable */
01854 /**
01855   * @}
01856   */
01857
01858 /** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag
01859   * @{
01860   */
01861 #define HRTIM_FLAG_FLT1           HRTIM_ISR_FLT1    /*!< Fault 1 interrupt flag */
01862 #define HRTIM_FLAG_FLT2           HRTIM_ISR_FLT2    /*!< Fault 2 interrupt flag */
01863 #define HRTIM_FLAG_FLT3           HRTIM_ISR_FLT3    /*!< Fault 3 interrupt flag */
01864 #define HRTIM_FLAG_FLT4           HRTIM_ISR_FLT4    /*!< Fault 4 interrupt flag */
01865 #define HRTIM_FLAG_FLT5           HRTIM_ISR_FLT5    /*!< Fault 5 interrupt flag */
01866 #define HRTIM_FLAG_SYSFLT         HRTIM_ISR_SYSFLT  /*!< System Fault interrupt flag */
01867 #define HRTIM_FLAG_DLLRDY         HRTIM_ISR_DLLRDY  /*!< DLL ready interrupt flag */
01868 #define HRTIM_FLAG_BMPER          HRTIM_ISR_BMPER   /*!< Burst mode period interrupt flag */
01869 /**
01870   * @}
01871   */
01872
01873 /** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag
01874   * @{
01875   */
01876 #define HRTIM_MASTER_FLAG_MCMP1        HRTIM_MISR_MCMP1    /*!< Master compare 1 interrupt flag */
01877 #define HRTIM_MASTER_FLAG_MCMP2        HRTIM_MISR_MCMP2    /*!< Master compare 2 interrupt flag */
01878 #define HRTIM_MASTER_FLAG_MCMP3        HRTIM_MISR_MCMP3    /*!< Master compare 3 interrupt flag */
01879 #define HRTIM_MASTER_FLAG_MCMP4        HRTIM_MISR_MCMP4   /*!< Master compare 4 interrupt flag */
01880 #define HRTIM_MASTER_FLAG_MREP         HRTIM_MISR_MREP    /*!< Master Repetition interrupt flag */
01881 #define HRTIM_MASTER_FLAG_SYNC         HRTIM_MISR_SYNC    /*!< Synchronization input interrupt flag */
01882 #define HRTIM_MASTER_FLAG_MUPD         HRTIM_MISR_MUPD    /*!< Master update interrupt flag */
01883 /**
01884   * @}
01885   */
01886
01887 /** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag
01888   * @{
01889   */
01890 #define HRTIM_TIM_FLAG_CMP1       HRTIM_TIMISR_CMP1      /*!< Timer compare 1 interrupt flag */
01891 #define HRTIM_TIM_FLAG_CMP2       HRTIM_TIMISR_CMP2      /*!< Timer compare 2 interrupt flag */
01892 #define HRTIM_TIM_FLAG_CMP3       HRTIM_TIMISR_CMP3      /*!< Timer compare 3 interrupt flag */
01893 #define HRTIM_TIM_FLAG_CMP4       HRTIM_TIMISR_CMP4      /*!< Timer compare 4 interrupt flag */
01894 #define HRTIM_TIM_FLAG_REP        HRTIM_TIMISR_REP       /*!< Timer repetition interrupt flag */
01895 #define HRTIM_TIM_FLAG_UPD        HRTIM_TIMISR_UPD       /*!< Timer update interrupt flag */
01896 #define HRTIM_TIM_FLAG_CPT1       HRTIM_TIMISR_CPT1      /*!< Timer capture 1 interrupt flag */
01897 #define HRTIM_TIM_FLAG_CPT2       HRTIM_TIMISR_CPT2      /*!< Timer capture 2 interrupt flag */
01898 #define HRTIM_TIM_FLAG_SET1       HRTIM_TIMISR_SET1      /*!< Timer output 1 set interrupt flag */
01899 #define HRTIM_TIM_FLAG_RST1       HRTIM_TIMISR_RST1      /*!< Timer output 1 reset interrupt flag */
01900 #define HRTIM_TIM_FLAG_SET2       HRTIM_TIMISR_SET2      /*!< Timer output 2 set interrupt flag */
01901 #define HRTIM_TIM_FLAG_RST2       HRTIM_TIMISR_RST2      /*!< Timer output 2 reset interrupt flag */
01902 #define HRTIM_TIM_FLAG_RST        HRTIM_TIMISR_RST       /*!< Timer reset interrupt flag */
01903 #define HRTIM_TIM_FLAG_DLYPRT     HRTIM_TIMISR_DLYPRT    /*!< Timer delay protection interrupt flag */
01904 /**
01905   * @}
01906   */
01907
01908 /** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable
01909   * @{
01910   */
01911 #define HRTIM_MASTER_DMA_NONE         0x00000000U   /*!< No DMA request enable */
01912 #define HRTIM_MASTER_DMA_MCMP1        HRTIM_MDIER_MCMP1DE    /*!< Master compare 1 DMA request enable */
01913 #define HRTIM_MASTER_DMA_MCMP2        HRTIM_MDIER_MCMP2DE    /*!< Master compare 2 DMA request enable */
01914 #define HRTIM_MASTER_DMA_MCMP3        HRTIM_MDIER_MCMP3DE    /*!< Master compare 3 DMA request enable */
01915 #define HRTIM_MASTER_DMA_MCMP4        HRTIM_MDIER_MCMP4DE    /*!< Master compare 4 DMA request enable */
01916 #define HRTIM_MASTER_DMA_MREP         HRTIM_MDIER_MREPDE     /*!< Master Repetition DMA request enable */
01917 #define HRTIM_MASTER_DMA_SYNC         HRTIM_MDIER_SYNCDE     /*!< Synchronization input DMA request enable */
01918 #define HRTIM_MASTER_DMA_MUPD         HRTIM_MDIER_MUPDDE     /*!< Master update DMA request enable */
01919 /**
01920   * @}
01921   */
01922
01923 /** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable
01924   * @{
01925   */
01926 #define HRTIM_TIM_DMA_NONE       0x00000000U       /*!< No DMA request enable */
01927 #define HRTIM_TIM_DMA_CMP1       HRTIM_TIMDIER_CMP1DE      /*!< Timer compare 1 DMA request enable */
01928 #define HRTIM_TIM_DMA_CMP2       HRTIM_TIMDIER_CMP2DE      /*!< Timer compare 2 DMA request enable */
01929 #define HRTIM_TIM_DMA_CMP3       HRTIM_TIMDIER_CMP3DE      /*!< Timer compare 3 DMA request enable */
01930 #define HRTIM_TIM_DMA_CMP4       HRTIM_TIMDIER_CMP4DE      /*!< Timer compare 4 DMA request enable */
01931 #define HRTIM_TIM_DMA_REP        HRTIM_TIMDIER_REPDE       /*!< Timer repetition DMA request enable */
01932 #define HRTIM_TIM_DMA_UPD        HRTIM_TIMDIER_UPDDE       /*!< Timer update DMA request enable */
01933 #define HRTIM_TIM_DMA_CPT1       HRTIM_TIMDIER_CPT1DE      /*!< Timer capture 1 DMA request enable */
01934 #define HRTIM_TIM_DMA_CPT2       HRTIM_TIMDIER_CPT2DE      /*!< Timer capture 2 DMA request enable */
01935 #define HRTIM_TIM_DMA_SET1       HRTIM_TIMDIER_SET1DE      /*!< Timer output 1 set DMA request enable */
01936 #define HRTIM_TIM_DMA_RST1       HRTIM_TIMDIER_RST1DE      /*!< Timer output 1 reset DMA request enable */
01937 #define HRTIM_TIM_DMA_SET2       HRTIM_TIMDIER_SET2DE      /*!< Timer output 2 set DMA request enable */
01938 #define HRTIM_TIM_DMA_RST2       HRTIM_TIMDIER_RST2DE      /*!< Timer output 2 reset DMA request enable */
01939 #define HRTIM_TIM_DMA_RST        HRTIM_TIMDIER_RSTDE       /*!< Timer reset DMA request enable */
01940 #define HRTIM_TIM_DMA_DLYPRT     HRTIM_TIMDIER_DLYPRTDE    /*!< Timer delay protection DMA request enable */
01941 /**
01942   * @}
01943   */
01944
01945 /**
01946   * @}
01947   */
01948
01949 /* Private macros --------------------------------------------------------*/
01950 /** @addtogroup HRTIM_Private_Macros HRTIM Private Macros
01951   * @{
01952   */
01953
01954 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
01955     (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER)   || \
01956      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A)  || \
01957      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B)  || \
01958      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C)  || \
01959      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D)  || \
01960      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
01961
01962 #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
01963      (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A)  || \
01964       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B)  || \
01965       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C)  || \
01966       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D)  || \
01967       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
01968
01969 #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U)
01970
01971 #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
01972     (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1)  || \
01973      ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2)  || \
01974      ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3)  || \
01975      ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
01976
01977 #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
01978     (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1)   || \
01979      ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
01980
01981 #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U)
01982
01983 #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
01984     ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) &&   \
01985      (((OUTPUT) == HRTIM_OUTPUT_TA1) ||          \
01986       ((OUTPUT) == HRTIM_OUTPUT_TA2)))           \
01987     ||                                           \
01988     (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) &&    \
01989      (((OUTPUT) == HRTIM_OUTPUT_TB1) ||          \
01990       ((OUTPUT) == HRTIM_OUTPUT_TB2)))           \
01991     ||                                           \
01992     (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) &&    \
01993      (((OUTPUT) == HRTIM_OUTPUT_TC1) ||          \
01994       ((OUTPUT) == HRTIM_OUTPUT_TC2)))           \
01995     ||                                           \
01996     (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) &&    \
01997      (((OUTPUT) == HRTIM_OUTPUT_TD1) ||          \
01998       ((OUTPUT) == HRTIM_OUTPUT_TD2)))           \
01999     ||                                           \
02000     (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) &&    \
02001      (((OUTPUT) == HRTIM_OUTPUT_TE1) ||          \
02002       ((OUTPUT) == HRTIM_OUTPUT_TE2))))
02003
02004 #define IS_HRTIM_EVENT(EVENT)\
02005       (((EVENT) == HRTIM_EVENT_1)   || \
02006        ((EVENT) == HRTIM_EVENT_2)   || \
02007        ((EVENT) == HRTIM_EVENT_3)   || \
02008        ((EVENT) == HRTIM_EVENT_4)   || \
02009        ((EVENT) == HRTIM_EVENT_5)   || \
02010        ((EVENT) == HRTIM_EVENT_6)   || \
02011        ((EVENT) == HRTIM_EVENT_7)   || \
02012        ((EVENT) == HRTIM_EVENT_8)   || \
02013        ((EVENT) == HRTIM_EVENT_9)   || \
02014        ((EVENT) == HRTIM_EVENT_10))
02015
02016 #define IS_HRTIM_FAULT(FAULT)\
02017       (((FAULT) == HRTIM_FAULT_1)   || \
02018        ((FAULT) == HRTIM_FAULT_2)   || \
02019        ((FAULT) == HRTIM_FAULT_3)   || \
02020        ((FAULT) == HRTIM_FAULT_4)   || \
02021        ((FAULT) == HRTIM_FAULT_5))
02022
02023 #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
02024         (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
02025          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
02026          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8)  || \
02027          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4)  || \
02028          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2)  || \
02029          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1)  || \
02030          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2)  || \
02031          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
02032
02033 #define IS_HRTIM_MODE(MODE)\
02034           (((MODE) == HRTIM_MODE_CONTINUOUS)  ||  \
02035            ((MODE) == HRTIM_MODE_SINGLESHOT) || \
02036            ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
02037
02038 #define IS_HRTIM_MODE_ONEPULSE(MODE)\
02039           (((MODE) == HRTIM_MODE_SINGLESHOT) || \
02040            ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
02041
02042
02043 #define IS_HRTIM_HALFMODE(HALFMODE)\
02044             (((HALFMODE) == HRTIM_HALFMODE_DISABLED)  ||  \
02045              ((HALFMODE) == HRTIM_HALFMODE_ENABLED))
02046
02047 #define IS_HRTIM_SYNCSTART(SYNCSTART)\
02048               (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED)  ||  \
02049                ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
02050
02051 #define IS_HRTIM_SYNCRESET(SYNCRESET)\
02052                 (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED)  ||  \
02053                  ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
02054
02055 #define IS_HHRTIM_DACSYNC(DACSYNC)\
02056                 (((DACSYNC) == HRTIM_DACSYNC_NONE)          ||  \
02057                  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1)  ||  \
02058                  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2)  ||  \
02059                  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
02060
02061 #define IS_HRTIM_PRELOAD(PRELOAD)\
02062                 (((PRELOAD) == HRTIM_PRELOAD_DISABLED)  ||  \
02063                  ((PRELOAD) == HRTIM_PRELOAD_ENABLED))
02064
02065 #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
02066                 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT)      ||  \
02067                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST)         ||  \
02068                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
02069
02070 #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
02071                 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT)      ||  \
02072                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST)         ||  \
02073                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)  ||  \
02074                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1)           ||  \
02075                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2)           ||  \
02076                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3)           ||  \
02077                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE)    ||  \
02078                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE)    ||  \
02079                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
02080
02081 #define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE)                               \
02082                 (((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK)  || \
02083                  ((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
02084
02085 #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION)                               \
02086                 (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED)  || \
02087                  ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
02088
02089 #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
02090                   (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
02091                    ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
02092
02093 #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U)
02094
02095
02096 #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
02097       (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
02098        ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
02099
02100 #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\
02101     ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) &&               \
02102         ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
02103           ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED))))  \
02104       ||                                                                     \
02105         (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) &&             \
02106          ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED)))
02107
02108 #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\
02109           ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED)          || \
02110             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6)  || \
02111             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6)  || \
02112             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6)  || \
02113             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \
02114             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \
02115             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7))    \
02116             ||                                                                           \
02117             (((TIMPUSHPULLMODE) ==  HRTIM_TIMPUSHPULLMODE_ENABLED) &&                    \
02118              (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)     || \
02119              ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))))
02120
02121 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)
02122
02123 #define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001U) == 0x00000000U)
02124
02125
02126 #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET)                       \
02127               (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
02128                ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
02129
02130 #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
02131               (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                  || \
02132                ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)    || \
02133                ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)  || \
02134                ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
02135
02136 /* Auto delayed mode is only available for compare units 2 and 4U */
02137 #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE)     \
02138     ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) &&                                 \
02139      (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                 ||  \
02140       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)   ||  \
02141       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) ||  \
02142       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))   \
02143     ||                                                                         \
02144     (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) &&                                 \
02145      (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                 ||  \
02146       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)   ||  \
02147       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) ||  \
02148       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
02149
02150 #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
02151               (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
02152                ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
02153
02154 #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
02155               (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE)       || \
02156                ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC)     || \
02157                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER)     || \
02158                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1)    || \
02159                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2)    || \
02160                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3)    || \
02161                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4)    || \
02162                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER)  || \
02163                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
02164                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
02165                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
02166                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
02167                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1)    || \
02168                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2)    || \
02169                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3)    || \
02170                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4)    || \
02171                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5)    || \
02172                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6)    || \
02173                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7)    || \
02174                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8)    || \
02175                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9)    || \
02176                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1)      || \
02177                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2)      || \
02178                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3)      || \
02179                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4)      || \
02180                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5)      || \
02181                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6)      || \
02182                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7)      || \
02183                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8)      || \
02184                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9)      || \
02185                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10)     || \
02186                ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
02187
02188 #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
02189               (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE)       || \
02190                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC)     || \
02191                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER)     || \
02192                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1)    || \
02193                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2)    || \
02194                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3)    || \
02195                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4)    || \
02196                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER)  || \
02197                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
02198                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
02199                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
02200                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
02201                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1)    || \
02202                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2)    || \
02203                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3)    || \
02204                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4)    || \
02205                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5)    || \
02206                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6)    || \
02207                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7)    || \
02208                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8)    || \
02209                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9)    || \
02210                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1)      || \
02211                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2)      || \
02212                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3)      || \
02213                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4)      || \
02214                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5)      || \
02215                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6)      || \
02216                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7)      || \
02217                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8)      || \
02218                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9)      || \
02219                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10)     || \
02220                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
02221
02222 #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
02223               (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
02224                ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
02225
02226 #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\
02227               (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \
02228                ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))
02229
02230 #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\
02231               (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE)     || \
02232                ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE)   || \
02233                ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \
02234                ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))
02235
02236 #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
02237               (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED)  || \
02238                ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
02239
02240 #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
02241               (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR)  || \
02242                ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
02243
02244 #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER)    \
02245    (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE)          || \
02246    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE)         || \
02247    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1)          || \
02248    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2)          || \
02249    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3)          || \
02250    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4)          || \
02251    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5)          || \
02252    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6)          || \
02253    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7)          || \
02254    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8)          || \
02255    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9)          || \
02256    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10)            \
02257    ||                                                           \
02258    (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) &&                    \
02259      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
02260       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
02261       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
02262       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
02263       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
02264       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
02265       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
02266       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
02267       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
02268       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
02269       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
02270       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
02271       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
02272       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
02273       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
02274       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
02275     ||                                                          \
02276    (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) &&                    \
02277      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
02278       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
02279       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
02280       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
02281       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
02282       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
02283       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
02284       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
02285       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
02286       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
02287       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
02288       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
02289       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
02290       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
02291       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
02292       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
02293     ||                                                          \
02294    (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) &&                    \
02295      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
02296       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
02297       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
02298       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
02299       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
02300       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
02301       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
02302       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
02303       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
02304       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
02305       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
02306       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
02307       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
02308       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
02309       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
02310       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
02311     ||                                                          \
02312    (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) &&                    \
02313      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
02314       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
02315       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
02316       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
02317       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
02318       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
02319       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
02320       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
02321       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
02322       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
02323       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
02324       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
02325       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
02326       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
02327       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
02328       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
02329     ||                                                          \
02330    (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) &&                    \
02331      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
02332       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
02333       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
02334       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
02335       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
02336       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
02337       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
02338       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
02339       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
02340       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
02341       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
02342       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
02343       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
02344       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
02345       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
02346       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))))
02347
02348 #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
02349                 (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE)           || \
02350                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1)   || \
02351                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2)   || \
02352                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3)   || \
02353                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4)   || \
02354                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1)  || \
02355                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2)  || \
02356                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3)  || \
02357                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4)  || \
02358                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5)  || \
02359                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6)  || \
02360                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7)  || \
02361                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8)  || \
02362                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2)  || \
02363                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3)  || \
02364                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
02365
02366 #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
02367               (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
02368                ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
02369
02370 #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
02371                 (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \
02372                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \
02373                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \
02374                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \
02375                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \
02376                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \
02377                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \
02378                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))
02379
02380 #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
02381                 (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE)    || \
02382                  ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
02383
02384 #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
02385                     (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE)    || \
02386                      ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
02387
02388 #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
02389                   (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE)    || \
02390                    ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
02391
02392 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
02393                       (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE)    || \
02394                        ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
02395
02396 #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
02397                           (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE)    || \
02398                            ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
02399
02400 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
02401                         (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE)    || \
02402                          ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
02403
02404 #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\
02405                         (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16)    || \
02406                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32)    || \
02407                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48)    || \
02408                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64)    || \
02409                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80)    || \
02410                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96)    || \
02411                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112)   || \
02412                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128)   || \
02413                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144)   || \
02414                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160)   || \
02415                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176)   || \
02416                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192)   || \
02417                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208)   || \
02418                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224)   || \
02419                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240)   || \
02420                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))
02421
02422 #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\
02423                         (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0)    || \
02424                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125)  || \
02425                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250)  || \
02426                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375)  || \
02427                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500)  || \
02428                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625)  || \
02429                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750)  || \
02430                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))
02431
02432 #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\
02433                         (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16)   || \
02434                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32)   || \
02435                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48)   || \
02436                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64)   || \
02437                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80)   || \
02438                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96)   || \
02439                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112)  || \
02440                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128)  || \
02441                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144)  || \
02442                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160)  || \
02443                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176)  || \
02444                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192)  || \
02445                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208)  || \
02446                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224)  || \
02447                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240)  || \
02448                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))
02449
02450 #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
02451               (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE)             || \
02452                ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT)    || \
02453                ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
02454
02455 #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
02456               (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START)  || \
02457                ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1)   || \
02458                ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START)    || \
02459                ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
02460
02461 #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
02462               (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE)  || \
02463                ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE)  || \
02464                ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
02465
02466 #define IS_HRTIM_EVENTSRC(EVENTSRC)\
02467                 (((EVENTSRC) == HRTIM_EVENTSRC_1)   || \
02468                  ((EVENTSRC) == HRTIM_EVENTSRC_2)   || \
02469                  ((EVENTSRC) == HRTIM_EVENTSRC_3)   || \
02470                  ((EVENTSRC) == HRTIM_EVENTSRC_4))
02471
02472 #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
02473     ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL)  &&      \
02474        (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH)  ||           \
02475         ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW)))              \
02476       ||                                                            \
02477       (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
02478        ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \
02479        ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))
02480
02481 #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
02482                     (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL)       || \
02483                      ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE)  || \
02484                      ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
02485                      ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
02486
02487 #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\
02488     (((((EVENT) == HRTIM_EVENT_1) ||                 \
02489        ((EVENT) == HRTIM_EVENT_2) ||                 \
02490        ((EVENT) == HRTIM_EVENT_3) ||                 \
02491        ((EVENT) == HRTIM_EVENT_4) ||                 \
02492        ((EVENT) == HRTIM_EVENT_5)) &&                \
02493       (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
02494        ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
02495     ||                                               \
02496     (((EVENT) == HRTIM_EVENT_6) ||                   \
02497      ((EVENT) == HRTIM_EVENT_7) ||                   \
02498      ((EVENT) == HRTIM_EVENT_8) ||                   \
02499      ((EVENT) == HRTIM_EVENT_9) ||                   \
02500      ((EVENT) == HRTIM_EVENT_10)))
02501
02502
02503 #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\
02504       ((((EVENT) == HRTIM_EVENT_1) ||            \
02505         ((EVENT) == HRTIM_EVENT_2) ||            \
02506         ((EVENT) == HRTIM_EVENT_3) ||            \
02507         ((EVENT) == HRTIM_EVENT_4) ||            \
02508         ((EVENT) == HRTIM_EVENT_5))              \
02509        ||                                        \
02510       ((((EVENT) == HRTIM_EVENT_6) ||            \
02511         ((EVENT) == HRTIM_EVENT_7) ||            \
02512         ((EVENT) == HRTIM_EVENT_8) ||            \
02513         ((EVENT) == HRTIM_EVENT_9) ||            \
02514         ((EVENT) == HRTIM_EVENT_10)) &&          \
02515         (((FILTER) == HRTIM_EVENTFILTER_NONE) || \
02516         ((FILTER) == HRTIM_EVENTFILTER_1)     || \
02517         ((FILTER) == HRTIM_EVENTFILTER_2)     || \
02518         ((FILTER) == HRTIM_EVENTFILTER_3)     || \
02519         ((FILTER) == HRTIM_EVENTFILTER_4)     || \
02520         ((FILTER) == HRTIM_EVENTFILTER_5)     || \
02521         ((FILTER) == HRTIM_EVENTFILTER_6)     || \
02522         ((FILTER) == HRTIM_EVENTFILTER_7)     || \
02523         ((FILTER) == HRTIM_EVENTFILTER_8)     || \
02524         ((FILTER) == HRTIM_EVENTFILTER_9)     || \
02525         ((FILTER) == HRTIM_EVENTFILTER_10)    || \
02526         ((FILTER) == HRTIM_EVENTFILTER_11)    || \
02527         ((FILTER) == HRTIM_EVENTFILTER_12)    || \
02528         ((FILTER) == HRTIM_EVENTFILTER_13)    || \
02529         ((FILTER) == HRTIM_EVENTFILTER_14)    || \
02530         ((FILTER) == HRTIM_EVENTFILTER_15))))
02531
02532 #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
02533              (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1)  || \
02534               ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2)   || \
02535               ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4)   || \
02536               ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
02537 #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
02538               (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
02539                ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
02540
02541 #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
02542               (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
02543                ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
02544
02545 #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
02546                 (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
02547                  ((FAULTFILTER) == HRTIM_FAULTFILTER_1)    || \
02548                  ((FAULTFILTER) == HRTIM_FAULTFILTER_2)    || \
02549                  ((FAULTFILTER) == HRTIM_FAULTFILTER_3)    || \
02550                  ((FAULTFILTER) == HRTIM_FAULTFILTER_4)    || \
02551                  ((FAULTFILTER) == HRTIM_FAULTFILTER_5)    || \
02552                  ((FAULTFILTER) == HRTIM_FAULTFILTER_6)    || \
02553                  ((FAULTFILTER) == HRTIM_FAULTFILTER_7)    || \
02554                  ((FAULTFILTER) == HRTIM_FAULTFILTER_8)    || \
02555                  ((FAULTFILTER) == HRTIM_FAULTFILTER_9)    || \
02556                  ((FAULTFILTER) == HRTIM_FAULTFILTER_10)   || \
02557                  ((FAULTFILTER) == HRTIM_FAULTFILTER_11)   || \
02558                  ((FAULTFILTER) == HRTIM_FAULTFILTER_12)   || \
02559                  ((FAULTFILTER) == HRTIM_FAULTFILTER_13)   || \
02560                  ((FAULTFILTER) == HRTIM_FAULTFILTER_14)   || \
02561                  ((FAULTFILTER) == HRTIM_FAULTFILTER_15))
02562
02563 #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
02564               (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
02565                ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
02566
02567 #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
02568              (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1)  || \
02569               ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2)   || \
02570               ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4)   || \
02571               ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
02572
02573 #define IS_HRTIM_BURSTMODE(BURSTMODE)\
02574               (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT)  || \
02575                ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
02576
02577 #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
02578               (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER)      || \
02579                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A)     || \
02580                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B)     || \
02581                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C)     || \
02582                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D)     || \
02583                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E)     || \
02584                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC)    || \
02585                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC)    || \
02586                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO)   || \
02587                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
02588
02589 #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
02590               (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1)     || \
02591                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2)     || \
02592                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4)     || \
02593                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8)     || \
02594                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16)    || \
02595                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32)    || \
02596                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64)    || \
02597                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128)   || \
02598                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256)   || \
02599                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512)   || \
02600                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024)  || \
02601                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048)  || \
02602                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096)  || \
02603                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192)  || \
02604                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
02605                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
02606
02607 #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
02608               (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED)  || \
02609                ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
02610
02611 #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
02612               (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE)               || \
02613                ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET)       || \
02614                ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION)  || \
02615                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP1)       || \
02616                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP2)       || \
02617                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP3)       || \
02618                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP4)       || \
02619                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_RESET)      || \
02620                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
02621                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_CMP1)       || \
02622                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_CMP2)       || \
02623                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_RESET)      || \
02624                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
02625                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_CMP1)       || \
02626                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_CMP2)       || \
02627                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_RESET)      || \
02628                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
02629                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_CMP1)       || \
02630                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_CMP2)       || \
02631                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_RESET)      || \
02632                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
02633                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_CMP1)       || \
02634                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_CMP2)       || \
02635                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_RESET)      || \
02636                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
02637                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_CMP1)       || \
02638                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_CMP2)       || \
02639                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7)     || \
02640                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8)     || \
02641                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_7)           || \
02642                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_8)           || \
02643                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
02644
02645 #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
02646              (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER)   || \
02647               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A)  || \
02648               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B)  || \
02649               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C)  || \
02650               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D)  || \
02651               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
02652
02653 #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
02654     (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION)   || \
02655      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \
02656      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910)  || \
02657      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114)  || \
02658      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
02659
02660 #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA)                                       \
02661    ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000U) == 0x00000000U)) \
02662     ||                                                                                 \
02663     (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
02664     ||                                                                                 \
02665     (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
02666     ||                                                                                 \
02667     (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
02668     ||                                                                                 \
02669     (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
02670     ||                                                                                 \
02671     (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)))
02672
02673 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
02674     (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED)  || \
02675      ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
02676
02677 #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U)
02678
02679 #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U)
02680
02681 #define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000U)
02682
02683
02684 #define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U)
02685
02686
02687 #define IS_HRTIM_TIM_IT(IS_HRTIM_TIM_IT) (((IS_HRTIM_TIM_IT) & 0xFFFF8020U) == 0x00000000U)
02688
02689
02690 #define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U)
02691
02692 #define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U)
02693 /**
02694   * @}
02695   */
02696
02697 /* Exported macros -----------------------------------------------------------*/
02698 /** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros
02699   * @{
02700   */
02701
02702 /** @brief Reset HRTIM handle state
02703   * @param  __HANDLE__ HRTIM handle.
02704   * @retval None
02705   */
02706 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
02707
02708 /** @brief  Enables or disables the timer counter(s)
02709   * @param  __HANDLE__ specifies the HRTIM Handle.
02710   * @param  __TIMERS__ timers to enable/disable
02711   *        This parameter can be any combinations of the following values:
02712   *            @arg HRTIM_TIMERID_MASTER: Master timer identifier
02713   *            @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
02714   *            @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
02715   *            @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
02716   *            @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
02717   *            @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
02718   * @retval None
02719   */
02720 #define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__)   ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))
02721
02722 /* The counter of a timing unit is disabled only if all the timer outputs */
02723 /* are disabled and no capture is configured                              */
02724 #define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
02725 #define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
02726 #define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
02727 #define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
02728 #define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
02729 #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
02730   do {\
02731     if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
02732       {\
02733         ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
02734       }\
02735     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
02736       {\
02737         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == RESET)\
02738           {\
02739             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
02740           }\
02741       }\
02742     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
02743       {\
02744         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == RESET)\
02745           {\
02746             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
02747           }\
02748       }\
02749     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
02750       {\
02751         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == RESET)\
02752           {\
02753             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
02754           }\
02755       }\
02756     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
02757       {\
02758         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == RESET)\
02759           {\
02760             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
02761           }\
02762       }\
02763     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
02764       {\
02765         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == RESET)\
02766           {\
02767             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
02768           }\
02769       }\
02770   } while(0U)
02771
02772 /** @brief  Enables or disables the specified HRTIM common interrupts.
02773   * @param  __HANDLE__ specifies the HRTIM Handle.
02774   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
02775   *        This parameter can be one of the following values:
02776   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
02777   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
02778   *            @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
02779   *            @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
02780   *            @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
02781   *            @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
02782   *            @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
02783   *            @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
02784   * @retval None
02785   */
02786 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
02787 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
02788
02789 /** @brief  Enables or disables the specified HRTIM Master timer interrupts.
02790   * @param  __HANDLE__ specifies the HRTIM Handle.
02791   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
02792   *        This parameter can be one of the following values:
02793   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
02794   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
02795   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
02796   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
02797   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
02798   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
02799   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
02800   * @retval None
02801   */
02802 #define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))
02803 #define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
02804
02805 /** @brief  Enables or disables the specified HRTIM Timerx interrupts.
02806   * @param  __HANDLE__ specifies the HRTIM Handle.
02807   * @param  __TIMER__ specified the timing unit (Timer A to E)
02808   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
02809   *        This parameter can be one of the following values:
02810   *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
02811   *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
02812   *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
02813   *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
02814   *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
02815   *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
02816   *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
02817   *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
02818   *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
02819   *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
02820   *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
02821   *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
02822   *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
02823   *            @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
02824   * @retval None
02825   */
02826 #define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))
02827 #define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
02828
02829 /** @brief  Checks if the specified HRTIM common interrupt  source  is enabled or disabled.
02830   * @param  __HANDLE__ specifies the HRTIM Handle.
02831   * @param  __INTERRUPT__ specifies the interrupt source to check.
02832   *        This parameter can be one of the following values:
02833   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
02834   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
02835   *            @arg HRTIM_IT_FLT3: Fault 3 enable
02836   *            @arg HRTIM_IT_FLT4: Fault 4 enable
02837   *            @arg HRTIM_IT_FLT5: Fault 5 enable
02838   *            @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
02839   *            @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
02840   *            @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
02841   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
02842   */
02843 #define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
02844
02845 /** @brief  Checks if the specified HRTIM Master interrupt source  is enabled or disabled.
02846   * @param  __HANDLE__ specifies the HRTIM Handle.
02847   * @param  __INTERRUPT__ specifies the interrupt source to check.
02848   *        This parameter can be one of the following values:
02849   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
02850   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
02851   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
02852   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
02853   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
02854   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
02855   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
02856   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
02857   */
02858 #define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
02859
02860 /** @brief  Checks if the specified HRTIM Timerx interrupt source  is enabled or disabled.
02861   * @param  __HANDLE__ specifies the HRTIM Handle.
02862   * @param  __TIMER__ specified the timing unit (Timer A to E)
02863   * @param  __INTERRUPT__ specifies the interrupt source to check.
02864   *        This parameter can be one of the following values:
02865   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
02866   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
02867   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
02868   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
02869   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
02870   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
02871   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
02872   *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
02873   *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
02874   *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
02875   *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
02876   *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
02877   *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
02878   *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
02879   *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
02880   *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
02881   *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
02882   *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
02883   *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
02884   *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
02885   *            @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
02886   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
02887   */
02888 #define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
02889
02890 /** @brief  Clears the specified HRTIM common pending flag.
02891   * @param  __HANDLE__ specifies the HRTIM Handle.
02892   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
02893   *        This parameter can be one of the following values:
02894   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
02895   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
02896   *            @arg HRTIM_IT_FLT3: Fault 3 clear flag
02897   *            @arg HRTIM_IT_FLT4: Fault 4 clear flag
02898   *            @arg HRTIM_IT_FLT5: Fault 5 clear flag
02899   *            @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
02900   *            @arg HRTIM_IT_DLLRDY: DLL ready interrupt clear flag
02901   *            @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
02902   * @retval None
02903   */
02904 #define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
02905
02906 /** @brief  Clears the specified HRTIM Master pending flag.
02907   * @param  __HANDLE__ specifies the HRTIM Handle.
02908   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
02909   *        This parameter can be one of the following values:
02910   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
02911   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
02912   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
02913   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
02914   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
02915   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
02916   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
02917   * @retval None
02918   */
02919 #define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
02920
02921 /** @brief  Clears the specified HRTIM Timerx pending flag.
02922   * @param  __HANDLE__ specifies the HRTIM Handle.
02923   * @param  __TIMER__ specified the timing unit (Timer A to E)
02924   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
02925   *        This parameter can be one of the following values:
02926   *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
02927   *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
02928   *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
02929   *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
02930   *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
02931   *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
02932   *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
02933   *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
02934   *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
02935   *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
02936   *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
02937   *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
02938   *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
02939   *            @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
02940   * @retval None
02941   */
02942 #define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
02943
02944 /* DMA HANDLING */
02945 /** @brief  Enables or disables the specified HRTIM common interrupts.
02946   * @param  __HANDLE__ specifies the HRTIM Handle.
02947   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
02948   *        This parameter can be one of the following values:
02949   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
02950   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
02951   *            @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
02952   *            @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
02953   *            @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
02954   *            @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
02955   *            @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
02956   *            @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
02957   * @retval None
02958   */
02959 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
02960 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
02961
02962 /** @brief  Enables or disables the specified HRTIM Master timer DMA requets.
02963   * @param  __HANDLE__ specifies the HRTIM Handle.
02964   * @param  __DMA__ specifies the DMA request to enable or disable.
02965   *        This parameter can be one of the following values:
02966   *            @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA resquest enable
02967   *            @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA resquest enable
02968   *            @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA resquest enable
02969   *            @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA resquest enable
02970   *            @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA resquest enable
02971   *            @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA resquest enable
02972   *            @arg HRTIM_MASTER_DMA_MUPD: Master update DMA resquest enable
02973   * @retval None
02974   */
02975 #define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__)   ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
02976 #define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
02977
02978 /** @brief  Enables or disables the specified HRTIM Timerx DMA requests.
02979   * @param  __HANDLE__ specifies the HRTIM Handle.
02980   * @param  __TIMER__ specified the timing unit (Timer A to E)
02981   * @param  __DMA__ specifies the DMA request to enable or disable.
02982   *        This parameter can be one of the following values:
02983   *            @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA resquest enable
02984   *            @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA resquest enable
02985   *            @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA resquest enable
02986   *            @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA resquest enable
02987   *            @arg HRTIM_TIM_DMA_REP: Timer repetition DMA resquest enable
02988   *            @arg HRTIM_TIM_DMA_UPD: Timer update DMA resquest enable
02989   *            @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA resquest enable
02990   *            @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA resquest enable
02991   *            @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA resquest enable
02992   *            @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA resquest enable
02993   *            @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA resquest enable
02994   *            @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA resquest enable
02995   *            @arg HRTIM_TIM_DMA_RST: Timer reset DMA resquest enable
02996   *            @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA resquest enable
02997   * @retval None
02998   */
02999 #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))
03000 #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
03001
03002 #define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__)        (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
03003 #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
03004
03005 #define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__)        (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
03006 #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
03007
03008 #define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__,  __TIMER__, __FLAG__)        (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
03009 #define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__,  __TIMER__, __FLAG__)      ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
03010
03011 /** @brief  Sets the HRTIM timer Counter Register value on runtime
03012   * @param  __HANDLE__ HRTIM Handle.
03013   * @param  __TIMER__ HRTIM timer
03014   *                   This parameter can be one of the following values:
03015   *                   @arg 0x5 for master timer
03016   *                   @arg 0x0 to 0x4 for timers A to E
03017   * @param  __COUNTER__ specifies the Counter Register new value.
03018   * @retval None
03019   */
03020 #define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \
03021   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
03022    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
03023
03024 /** @brief  Gets the HRTIM timer Counter Register value on runtime
03025   * @param  __HANDLE__ HRTIM Handle.
03026   * @param  __TIMER__ HRTIM timer
03027   *                   This parameter can be one of the following values:
03028   *                   @arg 0x5 for master timer
03029   *                   @arg 0x0 to 0x4 for timers A to E
03030   * @retval HRTIM timer Counter Register value
03031   */
03032 #define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \
03033   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
03034    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
03035
03036 /** @brief  Sets the HRTIM timer Period value on runtime
03037   * @param  __HANDLE__ HRTIM Handle.
03038   * @param  __TIMER__ HRTIM timer
03039   *                   This parameter can be one of the following values:
03040   *                   @arg 0x5 for master timer
03041   *                   @arg 0x0 to 0x4 for timers A to E
03042   * @param  __PERIOD__ specifies the Period Register new value.
03043   * @retval None
03044   */
03045 #define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \
03046   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
03047    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
03048
03049 /** @brief  Gets the HRTIM timer Period Register value on runtime
03050   * @param  __HANDLE__ HRTIM Handle.
03051   * @param  __TIMER__ HRTIM timer
03052   *                   This parameter can be one of the following values:
03053   *                   @arg 0x5 for master timer
03054   *                   @arg 0x0 to 0x4 for timers A to E
03055   * @retval timer Period Register
03056   */
03057 #define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \
03058   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
03059    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
03060
03061 /** @brief  Sets the HRTIM timer clock prescaler value on runtime
03062   * @param  __HANDLE__ HRTIM Handle.
03063   * @param  __TIMER__ HRTIM timer
03064   *                   This parameter can be one of the following values:
03065   *                   @arg 0x5 for master timer
03066   *                   @arg 0x0 to 0x4 for timers A to E
03067   * @param  __PRESCALER__ specifies the clock prescaler new value.
03068   *                   This parameter can be one of the following values:
03069   *                   @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
03070   *                   @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
03071   *                   @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
03072   *                   @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
03073   *                   @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
03074   *                   @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
03075   *                   @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
03076   *                   @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
03077   * @retval None
03078   */
03079 #define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \
03080   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\
03081    (MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__))))
03082
03083 /** @brief  Gets the HRTIM timer clock prescaler value on runtime
03084   * @param  __HANDLE__ HRTIM Handle.
03085   * @param  __TIMER__ HRTIM timer
03086   *                   This parameter can be one of the following values:
03087   *                   @arg 0x5 for master timer
03088   *                   @arg 0x0 to 0x4 for timers A to E
03089   * @retval timer clock prescaler value
03090   */
03091 #define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \
03092   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
03093    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR  & HRTIM_TIMCR_CK_PSC))
03094
03095 /** @brief  Sets the HRTIM timer Compare Register value on runtime
03096   * @param  __HANDLE__ HRTIM Handle.
03097   * @param  __TIMER__ HRTIM timer
03098   *                   This parameter can be one of the following values:
03099   *                   @arg 0x0 to 0x4 for timers A to E
03100   * @param  __COMPAREUNIT__ timer compare unit
03101   *                   This parameter can be one of the following values:
03102   *                   @arg HRTIM_COMPAREUNIT_1: Compare unit 1
03103   *                   @arg HRTIM_COMPAREUNIT_2: Compare unit 2
03104   *                   @arg HRTIM_COMPAREUNIT_3: Compare unit 3
03105   *                   @arg HRTIM_COMPAREUNIT_4: Compare unit 4
03106   * @param  __COMPARE__ specifies the Compare new value.
03107   * @retval None
03108   */
03109 #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
03110       (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
03111         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
03112          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
03113          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
03114          ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
03115          : \
03116         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
03117          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
03118          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
03119          ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
03120
03121 /** @brief  Gets the HRTIM timer Compare Register value on runtime
03122   * @param  __HANDLE__ HRTIM Handle.
03123   * @param  __TIMER__ HRTIM timer
03124   *                   This parameter can be one of the following values:
03125   *                   @arg 0x0 to 0x4 for timers A to E
03126   * @param  __COMPAREUNIT__ timer compare unit
03127   *                   This parameter can be one of the following values:
03128   *                   @arg HRTIM_COMPAREUNIT_1: Compare unit 1
03129   *                   @arg HRTIM_COMPAREUNIT_2: Compare unit 2
03130   *                   @arg HRTIM_COMPAREUNIT_3: Compare unit 3
03131   *                   @arg HRTIM_COMPAREUNIT_4: Compare unit 4
03132   * @retval Compare value
03133   */
03134 #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
03135       (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
03136         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
03137          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
03138          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
03139          ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
03140          : \
03141         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
03142          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
03143          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
03144          ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
03145
03146 /**
03147   * @}
03148   */
03149
03150 /* Exported functions --------------------------------------------------------*/
03151 /** @addtogroup HRTIM_Exported_Functions
03152 * @{
03153 */
03154
03155 /** @addtogroup HRTIM_Exported_Functions_Group1
03156 * @{
03157 */
03158
03159 /* Initialization and Configuration functions  ********************************/
03160 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);
03161
03162 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim);
03163
03164 void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);
03165
03166 void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
03167
03168 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
03169                                            uint32_t TimerIdx,
03170                                            HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
03171
03172 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim,
03173                                                 uint32_t CalibrationRate);
03174
03175 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim,
03176                                                    uint32_t CalibrationRate);
03177
03178 HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim,
03179                                                   uint32_t Timeout);
03180
03181 /**
03182   * @}
03183   */
03184
03185 /** @addtogroup HRTIM_Exported_Functions_Group2
03186 * @{
03187 */
03188
03189 /* Simple time base related functions  *****************************************/
03190 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
03191                                            uint32_t TimerIdx);
03192
03193 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
03194                                           uint32_t TimerIdx);
03195
03196 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
03197                                               uint32_t TimerIdx);
03198
03199 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
03200                                              uint32_t TimerIdx);
03201
03202 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
03203                                                uint32_t TimerIdx,
03204                                                uint32_t SrcAddr,
03205                                                uint32_t DestAddr,
03206                                                uint32_t Length);
03207
03208 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
03209                                               uint32_t TimerIdx);
03210
03211 /**
03212   * @}
03213   */
03214
03215 /** @addtogroup HRTIM_Exported_Functions_Group3
03216 * @{
03217 */
03218 /* Simple output compare related functions  ************************************/
03219 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
03220                                                  uint32_t TimerIdx,
03221                                                  uint32_t OCChannel,
03222                                                  HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
03223
03224 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
03225                                          uint32_t TimerIdx,
03226                                          uint32_t OCChannel);
03227
03228 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
03229                                         uint32_t TimerIdx,
03230                                         uint32_t OCChannel);
03231
03232 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
03233                                             uint32_t TimerIdx,
03234                                             uint32_t OCChannel);
03235
03236 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
03237                                            uint32_t TimerIdx,
03238                                            uint32_t OCChannel);
03239
03240 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
03241                                              uint32_t TimerIdx,
03242                                              uint32_t OCChannel,
03243                                              uint32_t SrcAddr,
03244                                              uint32_t DestAddr,
03245                                              uint32_t Length);
03246
03247 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
03248                                             uint32_t TimerIdx,
03249                                             uint32_t OCChannel);
03250
03251 /**
03252   * @}
03253   */
03254
03255 /** @addtogroup HRTIM_Exported_Functions_Group4
03256 * @{
03257 */
03258 /* Simple PWM output related functions  ****************************************/
03259 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
03260                                                   uint32_t TimerIdx,
03261                                                   uint32_t PWMChannel,
03262                                                   HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
03263
03264 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
03265                                           uint32_t TimerIdx,
03266                                           uint32_t PWMChannel);
03267
03268 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
03269                                          uint32_t TimerIdx,
03270                                          uint32_t PWMChannel);
03271
03272 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
03273                                              uint32_t TimerIdx,
03274                                              uint32_t PWMChannel);
03275
03276 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
03277                                             uint32_t TimerIdx,
03278                                             uint32_t PWMChannel);
03279
03280 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
03281                                               uint32_t TimerIdx,
03282                                               uint32_t PWMChannel,
03283                                               uint32_t SrcAddr,
03284                                               uint32_t DestAddr,
03285                                               uint32_t Length);
03286
03287 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
03288                                              uint32_t TimerIdx,
03289                                              uint32_t PWMChannel);
03290
03291 /**
03292   * @}
03293   */
03294
03295 /** @addtogroup HRTIM_Exported_Functions_Group5
03296 * @{
03297 */
03298 /* Simple capture related functions  *******************************************/
03299 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
03300                                                       uint32_t TimerIdx,
03301                                                       uint32_t CaptureChannel,
03302                                                       HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
03303
03304 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
03305                                               uint32_t TimerIdx,
03306                                               uint32_t CaptureChannel);
03307
03308 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
03309                                              uint32_t TimerIdx,
03310                                              uint32_t CaptureChannel);
03311
03312 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
03313                                                  uint32_t TimerIdx,
03314                                                  uint32_t CaptureChannel);
03315
03316 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
03317                                                 uint32_t TimerIdx,
03318                                                 uint32_t CaptureChannel);
03319
03320 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
03321                                                   uint32_t TimerIdx,
03322                                                   uint32_t CaptureChannel,
03323                                                   uint32_t SrcAddr,
03324                                                   uint32_t DestAddr,
03325                                                   uint32_t Length);
03326
03327 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
03328                                                  uint32_t TimerIdx,
03329                                                  uint32_t CaptureChannel);
03330
03331 /**
03332   * @}
03333   */
03334
03335 /** @addtogroup HRTIM_Exported_Functions_Group6
03336 * @{
03337 */
03338 /* Simple one pulse related functions  *****************************************/
03339 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
03340                                                        uint32_t TimerIdx,
03341                                                        uint32_t OnePulseChannel,
03342                                                        HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
03343
03344 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
03345                                                uint32_t TimerIdx,
03346                                                uint32_t OnePulseChannel);
03347
03348 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
03349                                               uint32_t TimerIdx,
03350                                              uint32_t OnePulseChannel);
03351
03352 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
03353                                                   uint32_t TimerIdx,
03354                                                   uint32_t OnePulseChannel);
03355
03356 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
03357                                                  uint32_t TimerIdx,
03358                                                  uint32_t OnePulseChannel);
03359
03360 /**
03361   * @}
03362   */
03363
03364 /** @addtogroup HRTIM_Exported_Functions_Group7
03365 * @{
03366 */
03367 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
03368                                             HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
03369
03370 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
03371                                         uint32_t Event,
03372                                         HRTIM_EventCfgTypeDef* pEventCfg);
03373
03374 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
03375                                                  uint32_t Prescaler);
03376
03377 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
03378                                         uint32_t Fault,
03379                                         HRTIM_FaultCfgTypeDef* pFaultCfg);
03380
03381 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
03382                                                  uint32_t Prescaler);
03383
03384 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
03385                             uint32_t Faults,
03386                             uint32_t Enable);
03387
03388 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
03389                                              uint32_t ADCTrigger,
03390                                              HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
03391
03392 /**
03393   * @}
03394   */
03395
03396 /** @addtogroup HRTIM_Exported_Functions_Group8
03397 * @{
03398 */
03399 /* Waveform related functions *************************************************/
03400 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
03401                                                 uint32_t TimerIdx,
03402                                                 HRTIM_TimerCfgTypeDef * pTimerCfg);
03403
03404 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
03405                                                   uint32_t TimerIdx,
03406                                                   uint32_t CompareUnit,
03407                                                   HRTIM_CompareCfgTypeDef* pCompareCfg);
03408
03409 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
03410                                                   uint32_t TimerIdx,
03411                                                   uint32_t CaptureUnit,
03412                                                   HRTIM_CaptureCfgTypeDef* pCaptureCfg);
03413
03414 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
03415                                                  uint32_t TimerIdx,
03416                                                  uint32_t Output,
03417                                                  HRTIM_OutputCfgTypeDef * pOutputCfg);
03418
03419 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
03420                                                    uint32_t TimerIdx,
03421                                                    uint32_t Output,
03422                                                    uint32_t OutputLevel);
03423
03424 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
03425                                                       uint32_t TimerIdx,
03426                                                       uint32_t Event,
03427                                                       HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
03428
03429 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
03430                                            uint32_t TimerIdx,
03431                                            HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
03432
03433 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
03434                                               uint32_t TimerIdx,
03435                                               HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
03436
03437 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
03438                                            uint32_t TimerIdx,
03439                                            uint32_t RegistersToUpdate);
03440
03441
03442 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef *hhrtim,
03443                                                  uint32_t Timers);
03444
03445 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef *hhrtim,
03446                                                  uint32_t Timers);
03447
03448
03449 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef *hhrtim,
03450                                                  uint32_t Timers);
03451
03452 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef *hhrtim,
03453                                                  uint32_t Timers);
03454
03455
03456 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef *hhrtim,
03457                                                      uint32_t Timers);
03458
03459 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef *hhrtim,
03460                                                     uint32_t Timers);
03461
03462 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
03463                                                 uint32_t OutputsToStart);
03464
03465 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
03466                                                uint32_t OutputsToStop);
03467
03468 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
03469                                          uint32_t Enable);
03470
03471 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);
03472
03473 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
03474                                             uint32_t TimerIdx,
03475                                             uint32_t CaptureUnit);
03476
03477 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
03478                                            uint32_t Timers);
03479
03480 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
03481                                           uint32_t Timers);
03482
03483 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
03484                                              uint32_t TimerIdx,
03485                                              uint32_t BurstBufferAddress,
03486                                              uint32_t BurstBufferLength);
03487
03488 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
03489                                           uint32_t Timers);
03490
03491 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
03492                                           uint32_t Timers);
03493
03494 /**
03495   * @}
03496   */
03497
03498 /** @addtogroup HRTIM_Exported_Functions_Group9
03499 * @{
03500 */
03501 /* HRTIM peripheral state functions */
03502 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim);
03503
03504 uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef *hhrtim,
03505                                     uint32_t TimerIdx,
03506                                     uint32_t CaptureUnit);
03507
03508 uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
03509                                           uint32_t TimerIdx,
03510                                           uint32_t Output);
03511
03512 uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
03513                                           uint32_t TimerIdx,
03514                                           uint32_t Output);
03515
03516 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim,
03517                                               uint32_t TimerIdx,
03518                                               uint32_t Output);
03519
03520 uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim);
03521
03522 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim,
03523                                             uint32_t TimerIdx);
03524
03525 uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim,
03526                                          uint32_t TimerIdx);
03527
03528 /**
03529   * @}
03530   */
03531
03532 /** @addtogroup HRTIM_Exported_Functions_Group10
03533 * @{
03534 */
03535 /* IRQ handler */
03536 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
03537                           uint32_t TimerIdx);
03538
03539 /* HRTIM events related callback functions */
03540 void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);
03541 void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);
03542 void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);
03543 void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);
03544 void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);
03545 void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);
03546 void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef *hhrtim);
03547 void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);
03548 void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);
03549
03550 /* Timer events related callback functions */
03551 void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
03552                                               uint32_t TimerIdx);
03553 void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
03554                                               uint32_t TimerIdx);
03555 void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
03556                                             uint32_t TimerIdx);
03557 void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
03558                                             uint32_t TimerIdx);
03559 void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
03560                                             uint32_t TimerIdx);
03561 void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
03562                                             uint32_t TimerIdx);
03563 void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
03564                                             uint32_t TimerIdx);
03565 void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
03566                                             uint32_t TimerIdx);
03567 void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
03568                                                 uint32_t TimerIdx);
03569 void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
03570                                            uint32_t TimerIdx);
03571 void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
03572                                          uint32_t TimerIdx);
03573 void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
03574                                            uint32_t TimerIdx);
03575 void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
03576                                          uint32_t TimerIdx);
03577 void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
03578                                            uint32_t TimerIdx);
03579 void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
03580                                                uint32_t TimerIdx);
03581 void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);
03582
03583 /**
03584   * @}
03585   */
03586
03587 /**
03588   * @}
03589   */
03590
03591 /**
03592   * @}
03593   */
03594
03595 /**
03596   * @}
03597   */
03598
03599 #endif /* defined(STM32F334x8) */
03600
03601 #ifdef __cplusplus
03602 }
03603 #endif
03604
03605 #endif /* __STM32F3xx_HAL_HRTIM_H */
03606
03607 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_i2c.c Source File

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stm32f3xx_hal_i2c.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_i2c.c
00004   * @author  MCD Application Team
00005   * @brief   I2C HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral State and Errors functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                         ##### How to use this driver #####
00015   ==============================================================================
00016     [..]
00017     The I2C HAL driver can be used as follows:
00018
00019     (#) Declare a I2C_HandleTypeDef handle structure, for example:
00020         I2C_HandleTypeDef  hi2c;
00021
00022     (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
00023         (##) Enable the I2Cx interface clock
00024         (##) I2C pins configuration
00025             (+++) Enable the clock for the I2C GPIOs
00026             (+++) Configure I2C pins as alternate function open-drain
00027         (##) NVIC configuration if you need to use interrupt process
00028             (+++) Configure the I2Cx interrupt priority
00029             (+++) Enable the NVIC I2C IRQ Channel
00030         (##) DMA Configuration if you need to use DMA process
00031             (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
00032             (+++) Enable the DMAx interface clock using
00033             (+++) Configure the DMA handle parameters
00034             (+++) Configure the DMA Tx or Rx channel
00035             (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
00036             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
00037                   the DMA Tx or Rx channel
00038
00039     (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
00040         Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
00041
00042     (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
00043         (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
00044
00045     (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
00046
00047     (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
00048
00049     *** Polling mode IO operation ***
00050     =================================
00051     [..]
00052       (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
00053       (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
00054       (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
00055       (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
00056
00057     *** Polling mode IO MEM operation ***
00058     =====================================
00059     [..]
00060       (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
00061       (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
00062
00063
00064     *** Interrupt mode IO operation ***
00065     ===================================
00066     [..]
00067       (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
00068       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
00069            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00070       (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
00071       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
00072            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00073       (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
00074       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
00075            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00076       (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
00077       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
00078            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00079       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00080            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00081       (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00082       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00083            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00084       (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00085            This action will inform Master to generate a Stop condition to discard the communication.
00086
00087
00088     *** Interrupt mode IO sequential operation ***
00089     ==============================================
00090     [..]
00091       (@) These interfaces allow to manage a sequential transfer with a repeated start condition
00092           when a direction change during transfer
00093     [..]
00094       (+) A specific option field manage the different steps of a sequential transfer
00095       (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
00096       (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
00097       (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
00098                             and data to transfer without a final stop condition
00099       (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
00100                             and data to transfer without a final stop condition, an then permit a call the same master sequential interface
00101                             several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT())
00102       (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
00103                             and with new data to transfer if the direction change or manage only the new data to transfer
00104                             if no direction change and without a final stop condition in both cases
00105       (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
00106                             and with new data to transfer if the direction change or manage only the new data to transfer
00107                             if no direction change and with a final stop condition in both cases
00108
00109       (+) Differents sequential I2C interfaces are listed below:
00110       (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
00111       (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
00112            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00113       (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
00114       (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
00115            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00116       (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00117       (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00118            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00119       (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
00120       (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
00121            add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
00122       (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
00123            add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
00124       (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
00125       (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
00126            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00127       (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
00128       (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
00129            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00130       (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00131            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00132       (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00133       (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00134            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00135       (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00136            This action will inform Master to generate a Stop condition to discard the communication.
00137
00138     *** Interrupt mode IO MEM operation ***
00139     =======================================
00140     [..]
00141       (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
00142           HAL_I2C_Mem_Write_IT()
00143       (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
00144            add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
00145       (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
00146           HAL_I2C_Mem_Read_IT()
00147       (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
00148            add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
00149       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00150            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00151
00152     *** DMA mode IO operation ***
00153     ==============================
00154     [..]
00155       (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
00156           HAL_I2C_Master_Transmit_DMA()
00157       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
00158            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00159       (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
00160           HAL_I2C_Master_Receive_DMA()
00161       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
00162            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00163       (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
00164           HAL_I2C_Slave_Transmit_DMA()
00165       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
00166            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00167       (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
00168           HAL_I2C_Slave_Receive_DMA()
00169       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
00170            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00171       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00172            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00173       (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00174       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00175            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00176       (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00177            This action will inform Master to generate a Stop condition to discard the communication.
00178
00179     *** DMA mode IO MEM operation ***
00180     =================================
00181     [..]
00182       (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
00183           HAL_I2C_Mem_Write_DMA()
00184       (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
00185            add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
00186       (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
00187           HAL_I2C_Mem_Read_DMA()
00188       (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
00189            add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
00190       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00191            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00192
00193
00194      *** I2C HAL driver macros list ***
00195      ==================================
00196      [..]
00197        Below the list of most used macros in I2C HAL driver.
00198
00199       (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
00200       (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
00201       (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
00202       (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
00203       (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
00204       (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
00205       (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
00206
00207      [..]
00208        (@) You can refer to the I2C HAL driver header file for more useful macros
00209
00210   @endverbatim
00211   ******************************************************************************
00212   * @attention
00213   *
00214   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00215   *
00216   * Redistribution and use in source and binary forms, with or without modification,
00217   * are permitted provided that the following conditions are met:
00218   *   1. Redistributions of source code must retain the above copyright notice,
00219   *      this list of conditions and the following disclaimer.
00220   *   2. Redistributions in binary form must reproduce the above copyright notice,
00221   *      this list of conditions and the following disclaimer in the documentation
00222   *      and/or other materials provided with the distribution.
00223   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00224   *      may be used to endorse or promote products derived from this software
00225   *      without specific prior written permission.
00226   *
00227   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00228   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00229   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00230   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00231   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00232   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00233   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00234   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00235   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00236   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00237   *
00238   ******************************************************************************
00239   */
00240
00241 /* Includes ------------------------------------------------------------------*/
00242 #include "stm32f3xx_hal.h"
00243
00244 /** @addtogroup STM32F3xx_HAL_Driver
00245   * @{
00246   */
00247
00248 /** @defgroup I2C I2C
00249   * @brief I2C HAL module driver
00250   * @{
00251   */
00252
00253 #ifdef HAL_I2C_MODULE_ENABLED
00254
00255 /* Private typedef -----------------------------------------------------------*/
00256 /* Private define ------------------------------------------------------------*/
00257
00258 /** @defgroup I2C_Private_Define I2C Private Define
00259   * @{
00260   */
00261 #define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
00262 #define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
00263 #define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
00264 #define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
00265 #define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
00266 #define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
00267 #define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
00268 #define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
00269 #define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
00270 #define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
00271
00272 #define MAX_NBYTE_SIZE      255U
00273 #define SlaveAddr_SHIFT     7U
00274 #define SlaveAddr_MSK       0x06U
00275
00276 /* Private define for @ref PreviousState usage */
00277 #define I2C_STATE_MSK             ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */
00278 #define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
00279 #define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
00280 #define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
00281 #define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
00282 #define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
00283 #define I2C_STATE_MEM_BUSY_TX     ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
00284 #define I2C_STATE_MEM_BUSY_RX     ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
00285
00286
00287 /* Private define to centralize the enable/disable of Interrupts */
00288 #define I2C_XFER_TX_IT          (0x00000001U)
00289 #define I2C_XFER_RX_IT          (0x00000002U)
00290 #define I2C_XFER_LISTEN_IT      (0x00000004U)
00291
00292 #define I2C_XFER_ERROR_IT       (0x00000011U)
00293 #define I2C_XFER_CPLT_IT        (0x00000012U)
00294 #define I2C_XFER_RELOAD_IT      (0x00000012U)
00295
00296 /* Private define Sequential Transfer Options default/reset value */
00297 #define I2C_NO_OPTION_FRAME     (0xFFFF0000U)
00298 /**
00299   * @}
00300   */
00301
00302 /* Private macro -------------------------------------------------------------*/
00303 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX)   ? \
00304                                             ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \
00305                                             ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR)))
00306
00307 /* Private variables ---------------------------------------------------------*/
00308 /* Private function prototypes -----------------------------------------------*/
00309
00310 /** @defgroup I2C_Private_Functions I2C Private Functions
00311   * @{
00312   */
00313 /* Private functions to handle DMA transfer */
00314 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
00315 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
00316 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
00317 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
00318 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
00319 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
00320
00321 /* Private functions to handle IT transfer */
00322 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00323 static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);
00324 static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);
00325 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00326 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00327 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00328 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
00329
00330 /* Private functions to handle IT transfer */
00331 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
00332 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
00333
00334 /* Private functions for I2C transfer IRQ handler */
00335 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00336 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00337 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00338 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00339
00340 /* Private functions to handle flags during polling transfer */
00341 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
00342 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00343 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00344 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00345 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00346
00347 /* Private functions to centralize the enable/disable of Interrupts */
00348 static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
00349 static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
00350
00351 /* Private functions to flush TXDR register */
00352 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
00353
00354 /* Private functions to handle  start, restart or stop a transfer */
00355 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
00356 /**
00357   * @}
00358   */
00359
00360 /* Exported functions --------------------------------------------------------*/
00361
00362 /** @defgroup I2C_Exported_Functions I2C Exported Functions
00363   * @{
00364   */
00365
00366 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00367  *  @brief    Initialization and Configuration functions
00368  *
00369 @verbatim
00370  ===============================================================================
00371               ##### Initialization and de-initialization functions #####
00372  ===============================================================================
00373     [..]  This subsection provides a set of functions allowing to initialize and
00374           deinitialize the I2Cx peripheral:
00375
00376       (+) User must Implement HAL_I2C_MspInit() function in which he configures
00377           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00378
00379       (+) Call the function HAL_I2C_Init() to configure the selected device with
00380           the selected configuration:
00381         (++) Clock Timing
00382         (++) Own Address 1
00383         (++) Addressing mode (Master, Slave)
00384         (++) Dual Addressing mode
00385         (++) Own Address 2
00386         (++) Own Address 2 Mask
00387         (++) General call mode
00388         (++) Nostretch mode
00389
00390       (+) Call the function HAL_I2C_DeInit() to restore the default configuration
00391           of the selected I2Cx peripheral.
00392
00393 @endverbatim
00394   * @{
00395   */
00396
00397 /**
00398   * @brief  Initializes the I2C according to the specified parameters
00399   *         in the I2C_InitTypeDef and initialize the associated handle.
00400   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00401   *                the configuration information for the specified I2C.
00402   * @retval HAL status
00403   */
00404 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
00405 {
00406   /* Check the I2C handle allocation */
00407   if (hi2c == NULL)
00408   {
00409     return HAL_ERROR;
00410   }
00411
00412   /* Check the parameters */
00413   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00414   assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
00415   assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
00416   assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
00417   assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
00418   assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
00419   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
00420   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
00421
00422   if (hi2c->State == HAL_I2C_STATE_RESET)
00423   {
00424     /* Allocate lock resource and initialize it */
00425     hi2c->Lock = HAL_UNLOCKED;
00426
00427     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00428     HAL_I2C_MspInit(hi2c);
00429   }
00430
00431   hi2c->State = HAL_I2C_STATE_BUSY;
00432
00433   /* Disable the selected I2C peripheral */
00434   __HAL_I2C_DISABLE(hi2c);
00435
00436   /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
00437   /* Configure I2Cx: Frequency range */
00438   hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
00439
00440   /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
00441   /* Disable Own Address1 before set the Own Address1 configuration */
00442   hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
00443
00444   /* Configure I2Cx: Own Address1 and ack own address1 mode */
00445   if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
00446   {
00447     hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
00448   }
00449   else /* I2C_ADDRESSINGMODE_10BIT */
00450   {
00451     hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
00452   }
00453
00454   /*---------------------------- I2Cx CR2 Configuration ----------------------*/
00455   /* Configure I2Cx: Addressing Master mode */
00456   if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
00457   {
00458     hi2c->Instance->CR2 = (I2C_CR2_ADD10);
00459   }
00460   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
00461   hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
00462
00463   /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
00464   /* Disable Own Address2 before set the Own Address2 configuration */
00465   hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
00466
00467   /* Configure I2Cx: Dual mode and Own Address2 */
00468   hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
00469
00470   /*---------------------------- I2Cx CR1 Configuration ----------------------*/
00471   /* Configure I2Cx: Generalcall and NoStretch mode */
00472   hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
00473
00474   /* Enable the selected I2C peripheral */
00475   __HAL_I2C_ENABLE(hi2c);
00476
00477   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00478   hi2c->State = HAL_I2C_STATE_READY;
00479   hi2c->PreviousState = I2C_STATE_NONE;
00480   hi2c->Mode = HAL_I2C_MODE_NONE;
00481
00482   return HAL_OK;
00483 }
00484
00485 /**
00486   * @brief  DeInitialize the I2C peripheral.
00487   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00488   *                the configuration information for the specified I2C.
00489   * @retval HAL status
00490   */
00491 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
00492 {
00493   /* Check the I2C handle allocation */
00494   if (hi2c == NULL)
00495   {
00496     return HAL_ERROR;
00497   }
00498
00499   /* Check the parameters */
00500   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00501
00502   hi2c->State = HAL_I2C_STATE_BUSY;
00503
00504   /* Disable the I2C Peripheral Clock */
00505   __HAL_I2C_DISABLE(hi2c);
00506
00507   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00508   HAL_I2C_MspDeInit(hi2c);
00509
00510   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00511   hi2c->State = HAL_I2C_STATE_RESET;
00512   hi2c->PreviousState = I2C_STATE_NONE;
00513   hi2c->Mode = HAL_I2C_MODE_NONE;
00514
00515   /* Release Lock */
00516   __HAL_UNLOCK(hi2c);
00517
00518   return HAL_OK;
00519 }
00520
00521 /**
00522   * @brief Initialize the I2C MSP.
00523   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00524   *                the configuration information for the specified I2C.
00525   * @retval None
00526   */
00527 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
00528 {
00529   /* Prevent unused argument(s) compilation warning */
00530   UNUSED(hi2c);
00531
00532   /* NOTE : This function should not be modified, when the callback is needed,
00533             the HAL_I2C_MspInit could be implemented in the user file
00534    */
00535 }
00536
00537 /**
00538   * @brief DeInitialize the I2C MSP.
00539   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00540   *                the configuration information for the specified I2C.
00541   * @retval None
00542   */
00543 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
00544 {
00545   /* Prevent unused argument(s) compilation warning */
00546   UNUSED(hi2c);
00547
00548   /* NOTE : This function should not be modified, when the callback is needed,
00549             the HAL_I2C_MspDeInit could be implemented in the user file
00550    */
00551 }
00552
00553 /**
00554   * @}
00555   */
00556
00557 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
00558  *  @brief   Data transfers functions
00559  *
00560 @verbatim
00561  ===============================================================================
00562                       ##### IO operation functions #####
00563  ===============================================================================
00564     [..]
00565     This subsection provides a set of functions allowing to manage the I2C data
00566     transfers.
00567
00568     (#) There are two modes of transfer:
00569        (++) Blocking mode : The communication is performed in the polling mode.
00570             The status of all data processing is returned by the same function
00571             after finishing transfer.
00572        (++) No-Blocking mode : The communication is performed using Interrupts
00573             or DMA. These functions return the status of the transfer startup.
00574             The end of the data processing will be indicated through the
00575             dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
00576             using DMA mode.
00577
00578     (#) Blocking mode functions are :
00579         (++) HAL_I2C_Master_Transmit()
00580         (++) HAL_I2C_Master_Receive()
00581         (++) HAL_I2C_Slave_Transmit()
00582         (++) HAL_I2C_Slave_Receive()
00583         (++) HAL_I2C_Mem_Write()
00584         (++) HAL_I2C_Mem_Read()
00585         (++) HAL_I2C_IsDeviceReady()
00586
00587     (#) No-Blocking mode functions with Interrupt are :
00588         (++) HAL_I2C_Master_Transmit_IT()
00589         (++) HAL_I2C_Master_Receive_IT()
00590         (++) HAL_I2C_Slave_Transmit_IT()
00591         (++) HAL_I2C_Slave_Receive_IT()
00592         (++) HAL_I2C_Mem_Write_IT()
00593         (++) HAL_I2C_Mem_Read_IT()
00594
00595     (#) No-Blocking mode functions with DMA are :
00596         (++) HAL_I2C_Master_Transmit_DMA()
00597         (++) HAL_I2C_Master_Receive_DMA()
00598         (++) HAL_I2C_Slave_Transmit_DMA()
00599         (++) HAL_I2C_Slave_Receive_DMA()
00600         (++) HAL_I2C_Mem_Write_DMA()
00601         (++) HAL_I2C_Mem_Read_DMA()
00602
00603     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00604         (++) HAL_I2C_MemTxCpltCallback()
00605         (++) HAL_I2C_MemRxCpltCallback()
00606         (++) HAL_I2C_MasterTxCpltCallback()
00607         (++) HAL_I2C_MasterRxCpltCallback()
00608         (++) HAL_I2C_SlaveTxCpltCallback()
00609         (++) HAL_I2C_SlaveRxCpltCallback()
00610         (++) HAL_I2C_ErrorCallback()
00611
00612 @endverbatim
00613   * @{
00614   */
00615
00616 /**
00617   * @brief  Transmits in master mode an amount of data in blocking mode.
00618   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00619   *                the configuration information for the specified I2C.
00620   * @param  DevAddress Target device address: The device 7 bits address value
00621   *         in datasheet must be shift at right before call interface
00622   * @param  pData Pointer to data buffer
00623   * @param  Size Amount of data to be sent
00624   * @param  Timeout Timeout duration
00625   * @retval HAL status
00626   */
00627 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00628 {
00629   uint32_t tickstart = 0U;
00630
00631   if (hi2c->State == HAL_I2C_STATE_READY)
00632   {
00633     /* Process Locked */
00634     __HAL_LOCK(hi2c);
00635
00636     /* Init tickstart for timeout management*/
00637     tickstart = HAL_GetTick();
00638
00639     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
00640     {
00641       return HAL_TIMEOUT;
00642     }
00643
00644     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
00645     hi2c->Mode      = HAL_I2C_MODE_MASTER;
00646     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00647
00648     /* Prepare transfer parameters */
00649     hi2c->pBuffPtr  = pData;
00650     hi2c->XferCount = Size;
00651     hi2c->XferISR   = NULL;
00652
00653     /* Send Slave Address */
00654     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
00655     if (hi2c->XferCount > MAX_NBYTE_SIZE)
00656     {
00657       hi2c->XferSize = MAX_NBYTE_SIZE;
00658       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
00659     }
00660     else
00661     {
00662       hi2c->XferSize = hi2c->XferCount;
00663       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
00664     }
00665
00666     while (hi2c->XferCount > 0U)
00667     {
00668       /* Wait until TXIS flag is set */
00669       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00670       {
00671         if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00672         {
00673           return HAL_ERROR;
00674         }
00675         else
00676         {
00677           return HAL_TIMEOUT;
00678         }
00679       }
00680       /* Write data to TXDR */
00681       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
00682       hi2c->XferCount--;
00683       hi2c->XferSize--;
00684
00685       if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
00686       {
00687         /* Wait until TCR flag is set */
00688         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
00689         {
00690           return HAL_TIMEOUT;
00691         }
00692
00693         if (hi2c->XferCount > MAX_NBYTE_SIZE)
00694         {
00695           hi2c->XferSize = MAX_NBYTE_SIZE;
00696           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
00697         }
00698         else
00699         {
00700           hi2c->XferSize = hi2c->XferCount;
00701           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
00702         }
00703       }
00704     }
00705
00706     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
00707     /* Wait until STOPF flag is set */
00708     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00709     {
00710       if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00711       {
00712         return HAL_ERROR;
00713       }
00714       else
00715       {
00716         return HAL_TIMEOUT;
00717       }
00718     }
00719
00720     /* Clear STOP Flag */
00721     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
00722
00723     /* Clear Configuration Register 2 */
00724     I2C_RESET_CR2(hi2c);
00725
00726     hi2c->State = HAL_I2C_STATE_READY;
00727     hi2c->Mode  = HAL_I2C_MODE_NONE;
00728
00729     /* Process Unlocked */
00730     __HAL_UNLOCK(hi2c);
00731
00732     return HAL_OK;
00733   }
00734   else
00735   {
00736     return HAL_BUSY;
00737   }
00738 }
00739
00740 /**
00741   * @brief  Receives in master mode an amount of data in blocking mode.
00742   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00743   *                the configuration information for the specified I2C.
00744   * @param  DevAddress Target device address: The device 7 bits address value
00745   *         in datasheet must be shift at right before call interface
00746   * @param  pData Pointer to data buffer
00747   * @param  Size Amount of data to be sent
00748   * @param  Timeout Timeout duration
00749   * @retval HAL status
00750   */
00751 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00752 {
00753   uint32_t tickstart = 0U;
00754
00755   if (hi2c->State == HAL_I2C_STATE_READY)
00756   {
00757     /* Process Locked */
00758     __HAL_LOCK(hi2c);
00759
00760     /* Init tickstart for timeout management*/
00761     tickstart = HAL_GetTick();
00762
00763     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
00764     {
00765       return HAL_TIMEOUT;
00766     }
00767
00768     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
00769     hi2c->Mode      = HAL_I2C_MODE_MASTER;
00770     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00771
00772     /* Prepare transfer parameters */
00773     hi2c->pBuffPtr  = pData;
00774     hi2c->XferCount = Size;
00775     hi2c->XferISR   = NULL;
00776
00777     /* Send Slave Address */
00778     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
00779     if (hi2c->XferCount > MAX_NBYTE_SIZE)
00780     {
00781       hi2c->XferSize = MAX_NBYTE_SIZE;
00782       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
00783     }
00784     else
00785     {
00786       hi2c->XferSize = hi2c->XferCount;
00787       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
00788     }
00789
00790     while (hi2c->XferCount > 0U)
00791     {
00792       /* Wait until RXNE flag is set */
00793       if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00794       {
00795         if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00796         {
00797           return HAL_ERROR;
00798         }
00799         else
00800         {
00801           return HAL_TIMEOUT;
00802         }
00803       }
00804
00805       /* Read data from RXDR */
00806       (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
00807       hi2c->XferSize--;
00808       hi2c->XferCount--;
00809
00810       if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
00811       {
00812         /* Wait until TCR flag is set */
00813         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
00814         {
00815           return HAL_TIMEOUT;
00816         }
00817
00818         if (hi2c->XferCount > MAX_NBYTE_SIZE)
00819         {
00820           hi2c->XferSize = MAX_NBYTE_SIZE;
00821           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
00822         }
00823         else
00824         {
00825           hi2c->XferSize = hi2c->XferCount;
00826           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
00827         }
00828       }
00829     }
00830
00831     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
00832     /* Wait until STOPF flag is set */
00833     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00834     {
00835       if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00836       {
00837         return HAL_ERROR;
00838       }
00839       else
00840       {
00841         return HAL_TIMEOUT;
00842       }
00843     }
00844
00845     /* Clear STOP Flag */
00846     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
00847
00848     /* Clear Configuration Register 2 */
00849     I2C_RESET_CR2(hi2c);
00850
00851     hi2c->State = HAL_I2C_STATE_READY;
00852     hi2c->Mode  = HAL_I2C_MODE_NONE;
00853
00854     /* Process Unlocked */
00855     __HAL_UNLOCK(hi2c);
00856
00857     return HAL_OK;
00858   }
00859   else
00860   {
00861     return HAL_BUSY;
00862   }
00863 }
00864
00865 /**
00866   * @brief  Transmits in slave mode an amount of data in blocking mode.
00867   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00868   *                the configuration information for the specified I2C.
00869   * @param  pData Pointer to data buffer
00870   * @param  Size Amount of data to be sent
00871   * @param  Timeout Timeout duration
00872   * @retval HAL status
00873   */
00874 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00875 {
00876   uint32_t tickstart = 0U;
00877
00878   if (hi2c->State == HAL_I2C_STATE_READY)
00879   {
00880     if ((pData == NULL) || (Size == 0U))
00881     {
00882       return  HAL_ERROR;
00883     }
00884     /* Process Locked */
00885     __HAL_LOCK(hi2c);
00886
00887     /* Init tickstart for timeout management*/
00888     tickstart = HAL_GetTick();
00889
00890     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
00891     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
00892     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00893
00894     /* Prepare transfer parameters */
00895     hi2c->pBuffPtr  = pData;
00896     hi2c->XferCount = Size;
00897     hi2c->XferISR   = NULL;
00898
00899     /* Enable Address Acknowledge */
00900     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
00901
00902     /* Wait until ADDR flag is set */
00903     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
00904     {
00905       /* Disable Address Acknowledge */
00906       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00907       return HAL_TIMEOUT;
00908     }
00909
00910     /* Clear ADDR flag */
00911     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
00912
00913     /* If 10bit addressing mode is selected */
00914     if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
00915     {
00916       /* Wait until ADDR flag is set */
00917       if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
00918       {
00919         /* Disable Address Acknowledge */
00920         hi2c->Instance->CR2 |= I2C_CR2_NACK;
00921         return HAL_TIMEOUT;
00922       }
00923
00924       /* Clear ADDR flag */
00925       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
00926     }
00927
00928     /* Wait until DIR flag is set Transmitter mode */
00929     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
00930     {
00931       /* Disable Address Acknowledge */
00932       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00933       return HAL_TIMEOUT;
00934     }
00935
00936     while (hi2c->XferCount > 0U)
00937     {
00938       /* Wait until TXIS flag is set */
00939       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00940       {
00941         /* Disable Address Acknowledge */
00942         hi2c->Instance->CR2 |= I2C_CR2_NACK;
00943
00944         if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00945         {
00946           return HAL_ERROR;
00947         }
00948         else
00949         {
00950           return HAL_TIMEOUT;
00951         }
00952       }
00953
00954       /* Write data to TXDR */
00955       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
00956       hi2c->XferCount--;
00957     }
00958
00959     /* Wait until STOP flag is set */
00960     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00961     {
00962       /* Disable Address Acknowledge */
00963       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00964
00965       if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00966       {
00967         /* Normal use case for Transmitter mode */
00968         /* A NACK is generated to confirm the end of transfer */
00969         hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00970       }
00971       else
00972       {
00973         return HAL_TIMEOUT;
00974       }
00975     }
00976
00977     /* Clear STOP flag */
00978     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
00979
00980     /* Wait until BUSY flag is reset */
00981     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
00982     {
00983       /* Disable Address Acknowledge */
00984       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00985       return HAL_TIMEOUT;
00986     }
00987
00988     /* Disable Address Acknowledge */
00989     hi2c->Instance->CR2 |= I2C_CR2_NACK;
00990
00991     hi2c->State = HAL_I2C_STATE_READY;
00992     hi2c->Mode  = HAL_I2C_MODE_NONE;
00993
00994     /* Process Unlocked */
00995     __HAL_UNLOCK(hi2c);
00996
00997     return HAL_OK;
00998   }
00999   else
01000   {
01001     return HAL_BUSY;
01002   }
01003 }
01004
01005 /**
01006   * @brief  Receive in slave mode an amount of data in blocking mode
01007   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01008   *                the configuration information for the specified I2C.
01009   * @param  pData Pointer to data buffer
01010   * @param  Size Amount of data to be sent
01011   * @param  Timeout Timeout duration
01012   * @retval HAL status
01013   */
01014 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01015 {
01016   uint32_t tickstart = 0U;
01017
01018   if (hi2c->State == HAL_I2C_STATE_READY)
01019   {
01020     if ((pData == NULL) || (Size == 0U))
01021     {
01022       return  HAL_ERROR;
01023     }
01024     /* Process Locked */
01025     __HAL_LOCK(hi2c);
01026
01027     /* Init tickstart for timeout management*/
01028     tickstart = HAL_GetTick();
01029
01030     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01031     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
01032     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01033
01034     /* Prepare transfer parameters */
01035     hi2c->pBuffPtr  = pData;
01036     hi2c->XferCount = Size;
01037     hi2c->XferISR   = NULL;
01038
01039     /* Enable Address Acknowledge */
01040     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01041
01042     /* Wait until ADDR flag is set */
01043     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01044     {
01045       /* Disable Address Acknowledge */
01046       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01047       return HAL_TIMEOUT;
01048     }
01049
01050     /* Clear ADDR flag */
01051     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
01052
01053     /* Wait until DIR flag is reset Receiver mode */
01054     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
01055     {
01056       /* Disable Address Acknowledge */
01057       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01058       return HAL_TIMEOUT;
01059     }
01060
01061     while (hi2c->XferCount > 0U)
01062     {
01063       /* Wait until RXNE flag is set */
01064       if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01065       {
01066         /* Disable Address Acknowledge */
01067         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01068
01069         /* Store Last receive data if any */
01070         if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
01071         {
01072           /* Read data from RXDR */
01073           (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
01074           hi2c->XferCount--;
01075         }
01076
01077         if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
01078         {
01079           return HAL_TIMEOUT;
01080         }
01081         else
01082         {
01083           return HAL_ERROR;
01084         }
01085       }
01086
01087       /* Read data from RXDR */
01088       (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
01089       hi2c->XferCount--;
01090     }
01091
01092     /* Wait until STOP flag is set */
01093     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01094     {
01095       /* Disable Address Acknowledge */
01096       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01097
01098       if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01099       {
01100         return HAL_ERROR;
01101       }
01102       else
01103       {
01104         return HAL_TIMEOUT;
01105       }
01106     }
01107
01108     /* Clear STOP flag */
01109     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01110
01111     /* Wait until BUSY flag is reset */
01112     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
01113     {
01114       /* Disable Address Acknowledge */
01115       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01116       return HAL_TIMEOUT;
01117     }
01118
01119     /* Disable Address Acknowledge */
01120     hi2c->Instance->CR2 |= I2C_CR2_NACK;
01121
01122     hi2c->State = HAL_I2C_STATE_READY;
01123     hi2c->Mode  = HAL_I2C_MODE_NONE;
01124
01125     /* Process Unlocked */
01126     __HAL_UNLOCK(hi2c);
01127
01128     return HAL_OK;
01129   }
01130   else
01131   {
01132     return HAL_BUSY;
01133   }
01134 }
01135
01136 /**
01137   * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
01138   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01139   *                the configuration information for the specified I2C.
01140   * @param  DevAddress Target device address: The device 7 bits address value
01141   *         in datasheet must be shift at right before call interface
01142   * @param  pData Pointer to data buffer
01143   * @param  Size Amount of data to be sent
01144   * @retval HAL status
01145   */
01146 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01147 {
01148   uint32_t xfermode = 0U;
01149
01150   if (hi2c->State == HAL_I2C_STATE_READY)
01151   {
01152     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01153     {
01154       return HAL_BUSY;
01155     }
01156
01157     /* Process Locked */
01158     __HAL_LOCK(hi2c);
01159
01160     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01161     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01162     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01163
01164     /* Prepare transfer parameters */
01165     hi2c->pBuffPtr    = pData;
01166     hi2c->XferCount   = Size;
01167     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01168     hi2c->XferISR     = I2C_Master_ISR_IT;
01169
01170     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01171     {
01172       hi2c->XferSize = MAX_NBYTE_SIZE;
01173       xfermode = I2C_RELOAD_MODE;
01174     }
01175     else
01176     {
01177       hi2c->XferSize = hi2c->XferCount;
01178       xfermode = I2C_AUTOEND_MODE;
01179     }
01180
01181     /* Send Slave Address */
01182     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01183     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
01184
01185     /* Process Unlocked */
01186     __HAL_UNLOCK(hi2c);
01187
01188     /* Note : The I2C interrupts must be enabled after unlocking current process
01189               to avoid the risk of I2C interrupt handle execution before current
01190               process unlock */
01191
01192     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01193     /* possible to enable all of these */
01194     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01195     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01196
01197     return HAL_OK;
01198   }
01199   else
01200   {
01201     return HAL_BUSY;
01202   }
01203 }
01204
01205 /**
01206   * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
01207   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01208   *                the configuration information for the specified I2C.
01209   * @param  DevAddress Target device address: The device 7 bits address value
01210   *         in datasheet must be shift at right before call interface
01211   * @param  pData Pointer to data buffer
01212   * @param  Size Amount of data to be sent
01213   * @retval HAL status
01214   */
01215 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01216 {
01217   uint32_t xfermode = 0U;
01218
01219   if (hi2c->State == HAL_I2C_STATE_READY)
01220   {
01221     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01222     {
01223       return HAL_BUSY;
01224     }
01225
01226     /* Process Locked */
01227     __HAL_LOCK(hi2c);
01228
01229     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01230     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01231     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01232
01233     /* Prepare transfer parameters */
01234     hi2c->pBuffPtr    = pData;
01235     hi2c->XferCount   = Size;
01236     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01237     hi2c->XferISR     = I2C_Master_ISR_IT;
01238
01239     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01240     {
01241       hi2c->XferSize = MAX_NBYTE_SIZE;
01242       xfermode = I2C_RELOAD_MODE;
01243     }
01244     else
01245     {
01246       hi2c->XferSize = hi2c->XferCount;
01247       xfermode = I2C_AUTOEND_MODE;
01248     }
01249
01250     /* Send Slave Address */
01251     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01252     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
01253
01254     /* Process Unlocked */
01255     __HAL_UNLOCK(hi2c);
01256
01257     /* Note : The I2C interrupts must be enabled after unlocking current process
01258               to avoid the risk of I2C interrupt handle execution before current
01259               process unlock */
01260
01261     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01262     /* possible to enable all of these */
01263     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01264     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
01265
01266     return HAL_OK;
01267   }
01268   else
01269   {
01270     return HAL_BUSY;
01271   }
01272 }
01273
01274 /**
01275   * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
01276   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01277   *                the configuration information for the specified I2C.
01278   * @param  pData Pointer to data buffer
01279   * @param  Size Amount of data to be sent
01280   * @retval HAL status
01281   */
01282 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01283 {
01284   if (hi2c->State == HAL_I2C_STATE_READY)
01285   {
01286     /* Process Locked */
01287     __HAL_LOCK(hi2c);
01288
01289     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01290     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01291     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01292
01293     /* Enable Address Acknowledge */
01294     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01295
01296     /* Prepare transfer parameters */
01297     hi2c->pBuffPtr    = pData;
01298     hi2c->XferCount   = Size;
01299     hi2c->XferSize    = hi2c->XferCount;
01300     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01301     hi2c->XferISR     = I2C_Slave_ISR_IT;
01302
01303     /* Process Unlocked */
01304     __HAL_UNLOCK(hi2c);
01305
01306     /* Note : The I2C interrupts must be enabled after unlocking current process
01307               to avoid the risk of I2C interrupt handle execution before current
01308               process unlock */
01309
01310     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01311     /* possible to enable all of these */
01312     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01313     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
01314
01315     return HAL_OK;
01316   }
01317   else
01318   {
01319     return HAL_BUSY;
01320   }
01321 }
01322
01323 /**
01324   * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
01325   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01326   *                the configuration information for the specified I2C.
01327   * @param  pData Pointer to data buffer
01328   * @param  Size Amount of data to be sent
01329   * @retval HAL status
01330   */
01331 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01332 {
01333   if (hi2c->State == HAL_I2C_STATE_READY)
01334   {
01335     /* Process Locked */
01336     __HAL_LOCK(hi2c);
01337
01338     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01339     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01340     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01341
01342     /* Enable Address Acknowledge */
01343     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01344
01345     /* Prepare transfer parameters */
01346     hi2c->pBuffPtr    = pData;
01347     hi2c->XferCount   = Size;
01348     hi2c->XferSize    = hi2c->XferCount;
01349     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01350     hi2c->XferISR     = I2C_Slave_ISR_IT;
01351
01352     /* Process Unlocked */
01353     __HAL_UNLOCK(hi2c);
01354
01355     /* Note : The I2C interrupts must be enabled after unlocking current process
01356               to avoid the risk of I2C interrupt handle execution before current
01357               process unlock */
01358
01359     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01360     /* possible to enable all of these */
01361     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01362     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
01363
01364     return HAL_OK;
01365   }
01366   else
01367   {
01368     return HAL_BUSY;
01369   }
01370 }
01371
01372 /**
01373   * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
01374   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01375   *                the configuration information for the specified I2C.
01376   * @param  DevAddress Target device address: The device 7 bits address value
01377   *         in datasheet must be shift at right before call interface
01378   * @param  pData Pointer to data buffer
01379   * @param  Size Amount of data to be sent
01380   * @retval HAL status
01381   */
01382 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01383 {
01384   uint32_t xfermode = 0U;
01385
01386   if (hi2c->State == HAL_I2C_STATE_READY)
01387   {
01388     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01389     {
01390       return HAL_BUSY;
01391     }
01392
01393     /* Process Locked */
01394     __HAL_LOCK(hi2c);
01395
01396     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01397     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01398     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01399
01400     /* Prepare transfer parameters */
01401     hi2c->pBuffPtr    = pData;
01402     hi2c->XferCount   = Size;
01403     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01404     hi2c->XferISR     = I2C_Master_ISR_DMA;
01405
01406     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01407     {
01408       hi2c->XferSize = MAX_NBYTE_SIZE;
01409       xfermode = I2C_RELOAD_MODE;
01410     }
01411     else
01412     {
01413       hi2c->XferSize = hi2c->XferCount;
01414       xfermode = I2C_AUTOEND_MODE;
01415     }
01416
01417     if (hi2c->XferSize > 0U)
01418     {
01419       /* Set the I2C DMA transfer complete callback */
01420       hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
01421
01422       /* Set the DMA error callback */
01423       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
01424
01425       /* Set the unused DMA callbacks to NULL */
01426       hi2c->hdmatx->XferHalfCpltCallback = NULL;
01427       hi2c->hdmatx->XferAbortCallback = NULL;
01428
01429       /* Enable the DMA channel */
01430       HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
01431
01432       /* Send Slave Address */
01433       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01434       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
01435
01436       /* Update XferCount value */
01437       hi2c->XferCount -= hi2c->XferSize;
01438
01439       /* Process Unlocked */
01440       __HAL_UNLOCK(hi2c);
01441
01442       /* Note : The I2C interrupts must be enabled after unlocking current process
01443                 to avoid the risk of I2C interrupt handle execution before current
01444                 process unlock */
01445       /* Enable ERR and NACK interrupts */
01446       I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
01447
01448       /* Enable DMA Request */
01449       hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
01450     }
01451     else
01452     {
01453       /* Update Transfer ISR function pointer */
01454       hi2c->XferISR = I2C_Master_ISR_IT;
01455
01456       /* Send Slave Address */
01457       /* Set NBYTES to write and generate START condition */
01458       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
01459
01460       /* Process Unlocked */
01461       __HAL_UNLOCK(hi2c);
01462
01463       /* Note : The I2C interrupts must be enabled after unlocking current process
01464                 to avoid the risk of I2C interrupt handle execution before current
01465                 process unlock */
01466       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01467       /* possible to enable all of these */
01468       /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01469       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01470     }
01471
01472     return HAL_OK;
01473   }
01474   else
01475   {
01476     return HAL_BUSY;
01477   }
01478 }
01479
01480 /**
01481   * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
01482   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01483   *                the configuration information for the specified I2C.
01484   * @param  DevAddress Target device address: The device 7 bits address value
01485   *         in datasheet must be shift at right before call interface
01486   * @param  pData Pointer to data buffer
01487   * @param  Size Amount of data to be sent
01488   * @retval HAL status
01489   */
01490 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01491 {
01492   uint32_t xfermode = 0U;
01493
01494   if (hi2c->State == HAL_I2C_STATE_READY)
01495   {
01496     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01497     {
01498       return HAL_BUSY;
01499     }
01500
01501     /* Process Locked */
01502     __HAL_LOCK(hi2c);
01503
01504     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01505     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01506     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01507
01508     /* Prepare transfer parameters */
01509     hi2c->pBuffPtr    = pData;
01510     hi2c->XferCount   = Size;
01511     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01512     hi2c->XferISR     = I2C_Master_ISR_DMA;
01513
01514     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01515     {
01516       hi2c->XferSize = MAX_NBYTE_SIZE;
01517       xfermode = I2C_RELOAD_MODE;
01518     }
01519     else
01520     {
01521       hi2c->XferSize = hi2c->XferCount;
01522       xfermode = I2C_AUTOEND_MODE;
01523     }
01524
01525     if (hi2c->XferSize > 0U)
01526     {
01527       /* Set the I2C DMA transfer complete callback */
01528       hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
01529
01530       /* Set the DMA error callback */
01531       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
01532
01533       /* Set the unused DMA callbacks to NULL */
01534       hi2c->hdmarx->XferHalfCpltCallback = NULL;
01535       hi2c->hdmarx->XferAbortCallback = NULL;
01536
01537       /* Enable the DMA channel */
01538       HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
01539
01540       /* Send Slave Address */
01541       /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01542       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
01543
01544       /* Update XferCount value */
01545       hi2c->XferCount -= hi2c->XferSize;
01546
01547       /* Process Unlocked */
01548       __HAL_UNLOCK(hi2c);
01549
01550       /* Note : The I2C interrupts must be enabled after unlocking current process
01551                 to avoid the risk of I2C interrupt handle execution before current
01552                 process unlock */
01553       /* Enable ERR and NACK interrupts */
01554       I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
01555
01556       /* Enable DMA Request */
01557       hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
01558     }
01559     else
01560     {
01561       /* Update Transfer ISR function pointer */
01562       hi2c->XferISR = I2C_Master_ISR_IT;
01563
01564       /* Send Slave Address */
01565       /* Set NBYTES to read and generate START condition */
01566       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
01567
01568       /* Process Unlocked */
01569       __HAL_UNLOCK(hi2c);
01570
01571       /* Note : The I2C interrupts must be enabled after unlocking current process
01572                 to avoid the risk of I2C interrupt handle execution before current
01573                 process unlock */
01574       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01575       /* possible to enable all of these */
01576       /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01577       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01578     }
01579     return HAL_OK;
01580   }
01581   else
01582   {
01583     return HAL_BUSY;
01584   }
01585 }
01586
01587 /**
01588   * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
01589   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01590   *                the configuration information for the specified I2C.
01591   * @param  pData Pointer to data buffer
01592   * @param  Size Amount of data to be sent
01593   * @retval HAL status
01594   */
01595 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01596 {
01597   if (hi2c->State == HAL_I2C_STATE_READY)
01598   {
01599     if ((pData == NULL) || (Size == 0U))
01600     {
01601       return  HAL_ERROR;
01602     }
01603     /* Process Locked */
01604     __HAL_LOCK(hi2c);
01605
01606     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01607     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01608     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01609
01610     /* Prepare transfer parameters */
01611     hi2c->pBuffPtr    = pData;
01612     hi2c->XferCount   = Size;
01613     hi2c->XferSize    = hi2c->XferCount;
01614     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01615     hi2c->XferISR     = I2C_Slave_ISR_DMA;
01616
01617     /* Set the I2C DMA transfer complete callback */
01618     hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
01619
01620     /* Set the DMA error callback */
01621     hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
01622
01623     /* Set the unused DMA callbacks to NULL */
01624     hi2c->hdmatx->XferHalfCpltCallback = NULL;
01625     hi2c->hdmatx->XferAbortCallback = NULL;
01626
01627     /* Enable the DMA channel */
01628     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
01629
01630     /* Enable Address Acknowledge */
01631     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01632
01633     /* Process Unlocked */
01634     __HAL_UNLOCK(hi2c);
01635
01636     /* Note : The I2C interrupts must be enabled after unlocking current process
01637               to avoid the risk of I2C interrupt handle execution before current
01638               process unlock */
01639     /* Enable ERR, STOP, NACK, ADDR interrupts */
01640     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
01641
01642     /* Enable DMA Request */
01643     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
01644
01645     return HAL_OK;
01646   }
01647   else
01648   {
01649     return HAL_BUSY;
01650   }
01651 }
01652
01653 /**
01654   * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
01655   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01656   *                the configuration information for the specified I2C.
01657   * @param  pData Pointer to data buffer
01658   * @param  Size Amount of data to be sent
01659   * @retval HAL status
01660   */
01661 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01662 {
01663   if (hi2c->State == HAL_I2C_STATE_READY)
01664   {
01665     if ((pData == NULL) || (Size == 0U))
01666     {
01667       return  HAL_ERROR;
01668     }
01669     /* Process Locked */
01670     __HAL_LOCK(hi2c);
01671
01672     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01673     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01674     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01675
01676     /* Prepare transfer parameters */
01677     hi2c->pBuffPtr    = pData;
01678     hi2c->XferCount   = Size;
01679     hi2c->XferSize    = hi2c->XferCount;
01680     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01681     hi2c->XferISR     = I2C_Slave_ISR_DMA;
01682
01683     /* Set the I2C DMA transfer complete callback */
01684     hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
01685
01686     /* Set the DMA error callback */
01687     hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
01688
01689     /* Set the unused DMA callbacks to NULL */
01690     hi2c->hdmarx->XferHalfCpltCallback = NULL;
01691     hi2c->hdmarx->XferAbortCallback = NULL;
01692
01693     /* Enable the DMA channel */
01694     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
01695
01696     /* Enable Address Acknowledge */
01697     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01698
01699     /* Process Unlocked */
01700     __HAL_UNLOCK(hi2c);
01701
01702     /* Note : The I2C interrupts must be enabled after unlocking current process
01703               to avoid the risk of I2C interrupt handle execution before current
01704               process unlock */
01705     /* Enable ERR, STOP, NACK, ADDR interrupts */
01706     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
01707
01708     /* Enable DMA Request */
01709     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
01710
01711     return HAL_OK;
01712   }
01713   else
01714   {
01715     return HAL_BUSY;
01716   }
01717 }
01718 /**
01719   * @brief  Write an amount of data in blocking mode to a specific memory address
01720   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01721   *                the configuration information for the specified I2C.
01722   * @param  DevAddress Target device address: The device 7 bits address value
01723   *         in datasheet must be shift at right before call interface
01724   * @param  MemAddress Internal memory address
01725   * @param  MemAddSize Size of internal memory address
01726   * @param  pData Pointer to data buffer
01727   * @param  Size Amount of data to be sent
01728   * @param  Timeout Timeout duration
01729   * @retval HAL status
01730   */
01731 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01732 {
01733   uint32_t tickstart = 0U;
01734
01735   /* Check the parameters */
01736   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
01737
01738   if (hi2c->State == HAL_I2C_STATE_READY)
01739   {
01740     if ((pData == NULL) || (Size == 0U))
01741     {
01742       return  HAL_ERROR;
01743     }
01744
01745     /* Process Locked */
01746     __HAL_LOCK(hi2c);
01747
01748     /* Init tickstart for timeout management*/
01749     tickstart = HAL_GetTick();
01750
01751     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
01752     {
01753       return HAL_TIMEOUT;
01754     }
01755
01756     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
01757     hi2c->Mode      = HAL_I2C_MODE_MEM;
01758     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01759
01760     /* Prepare transfer parameters */
01761     hi2c->pBuffPtr  = pData;
01762     hi2c->XferCount = Size;
01763     hi2c->XferISR   = NULL;
01764
01765     /* Send Slave Address and Memory Address */
01766     if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
01767     {
01768       if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01769       {
01770         /* Process Unlocked */
01771         __HAL_UNLOCK(hi2c);
01772         return HAL_ERROR;
01773       }
01774       else
01775       {
01776         /* Process Unlocked */
01777         __HAL_UNLOCK(hi2c);
01778         return HAL_TIMEOUT;
01779       }
01780     }
01781
01782     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01783     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01784     {
01785       hi2c->XferSize = MAX_NBYTE_SIZE;
01786       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01787     }
01788     else
01789     {
01790       hi2c->XferSize = hi2c->XferCount;
01791       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01792     }
01793
01794     do
01795     {
01796       /* Wait until TXIS flag is set */
01797       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01798       {
01799         if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01800         {
01801           return HAL_ERROR;
01802         }
01803         else
01804         {
01805           return HAL_TIMEOUT;
01806         }
01807       }
01808
01809       /* Write data to TXDR */
01810       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
01811       hi2c->XferCount--;
01812       hi2c->XferSize--;
01813
01814       if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
01815       {
01816         /* Wait until TCR flag is set */
01817         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
01818         {
01819           return HAL_TIMEOUT;
01820         }
01821
01822         if (hi2c->XferCount > MAX_NBYTE_SIZE)
01823         {
01824           hi2c->XferSize = MAX_NBYTE_SIZE;
01825           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01826         }
01827         else
01828         {
01829           hi2c->XferSize = hi2c->XferCount;
01830           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01831         }
01832       }
01833
01834     }
01835     while (hi2c->XferCount > 0U);
01836
01837     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01838     /* Wait until STOPF flag is reset */
01839     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01840     {
01841       if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01842       {
01843         return HAL_ERROR;
01844       }
01845       else
01846       {
01847         return HAL_TIMEOUT;
01848       }
01849     }
01850
01851     /* Clear STOP Flag */
01852     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01853
01854     /* Clear Configuration Register 2 */
01855     I2C_RESET_CR2(hi2c);
01856
01857     hi2c->State = HAL_I2C_STATE_READY;
01858     hi2c->Mode  = HAL_I2C_MODE_NONE;
01859
01860     /* Process Unlocked */
01861     __HAL_UNLOCK(hi2c);
01862
01863     return HAL_OK;
01864   }
01865   else
01866   {
01867     return HAL_BUSY;
01868   }
01869 }
01870
01871 /**
01872   * @brief  Read an amount of data in blocking mode from a specific memory address
01873   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01874   *                the configuration information for the specified I2C.
01875   * @param  DevAddress Target device address: The device 7 bits address value
01876   *         in datasheet must be shift at right before call interface
01877   * @param  MemAddress Internal memory address
01878   * @param  MemAddSize Size of internal memory address
01879   * @param  pData Pointer to data buffer
01880   * @param  Size Amount of data to be sent
01881   * @param  Timeout Timeout duration
01882   * @retval HAL status
01883   */
01884 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01885 {
01886   uint32_t tickstart = 0U;
01887
01888   /* Check the parameters */
01889   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
01890
01891   if (hi2c->State == HAL_I2C_STATE_READY)
01892   {
01893     if ((pData == NULL) || (Size == 0U))
01894     {
01895       return  HAL_ERROR;
01896     }
01897
01898     /* Process Locked */
01899     __HAL_LOCK(hi2c);
01900
01901     /* Init tickstart for timeout management*/
01902     tickstart = HAL_GetTick();
01903
01904     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
01905     {
01906       return HAL_TIMEOUT;
01907     }
01908
01909     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01910     hi2c->Mode      = HAL_I2C_MODE_MEM;
01911     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01912
01913     /* Prepare transfer parameters */
01914     hi2c->pBuffPtr  = pData;
01915     hi2c->XferCount = Size;
01916     hi2c->XferISR   = NULL;
01917
01918     /* Send Slave Address and Memory Address */
01919     if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
01920     {
01921       if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01922       {
01923         /* Process Unlocked */
01924         __HAL_UNLOCK(hi2c);
01925         return HAL_ERROR;
01926       }
01927       else
01928       {
01929         /* Process Unlocked */
01930         __HAL_UNLOCK(hi2c);
01931         return HAL_TIMEOUT;
01932       }
01933     }
01934
01935     /* Send Slave Address */
01936     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01937     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01938     {
01939       hi2c->XferSize = MAX_NBYTE_SIZE;
01940       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
01941     }
01942     else
01943     {
01944       hi2c->XferSize = hi2c->XferCount;
01945       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
01946     }
01947
01948     do
01949     {
01950       /* Wait until RXNE flag is set */
01951       if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
01952       {
01953         return HAL_TIMEOUT;
01954       }
01955
01956       /* Read data from RXDR */
01957       (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
01958       hi2c->XferSize--;
01959       hi2c->XferCount--;
01960
01961       if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
01962       {
01963         /* Wait until TCR flag is set */
01964         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
01965         {
01966           return HAL_TIMEOUT;
01967         }
01968
01969         if (hi2c->XferCount > MAX_NBYTE_SIZE)
01970         {
01971           hi2c->XferSize = MAX_NBYTE_SIZE;
01972           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01973         }
01974         else
01975         {
01976           hi2c->XferSize = hi2c->XferCount;
01977           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01978         }
01979       }
01980     }
01981     while (hi2c->XferCount > 0U);
01982
01983     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01984     /* Wait until STOPF flag is reset */
01985     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01986     {
01987       if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01988       {
01989         return HAL_ERROR;
01990       }
01991       else
01992       {
01993         return HAL_TIMEOUT;
01994       }
01995     }
01996
01997     /* Clear STOP Flag */
01998     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01999
02000     /* Clear Configuration Register 2 */
02001     I2C_RESET_CR2(hi2c);
02002
02003     hi2c->State = HAL_I2C_STATE_READY;
02004     hi2c->Mode  = HAL_I2C_MODE_NONE;
02005
02006     /* Process Unlocked */
02007     __HAL_UNLOCK(hi2c);
02008
02009     return HAL_OK;
02010   }
02011   else
02012   {
02013     return HAL_BUSY;
02014   }
02015 }
02016 /**
02017   * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
02018   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02019   *                the configuration information for the specified I2C.
02020   * @param  DevAddress Target device address: The device 7 bits address value
02021   *         in datasheet must be shift at right before call interface
02022   * @param  MemAddress Internal memory address
02023   * @param  MemAddSize Size of internal memory address
02024   * @param  pData Pointer to data buffer
02025   * @param  Size Amount of data to be sent
02026   * @retval HAL status
02027   */
02028 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02029 {
02030   uint32_t tickstart = 0U;
02031   uint32_t xfermode = 0U;
02032
02033   /* Check the parameters */
02034   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02035
02036   if (hi2c->State == HAL_I2C_STATE_READY)
02037   {
02038     if ((pData == NULL) || (Size == 0U))
02039     {
02040       return  HAL_ERROR;
02041     }
02042
02043     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02044     {
02045       return HAL_BUSY;
02046     }
02047
02048     /* Process Locked */
02049     __HAL_LOCK(hi2c);
02050
02051     /* Init tickstart for timeout management*/
02052     tickstart = HAL_GetTick();
02053
02054     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02055     hi2c->Mode        = HAL_I2C_MODE_MEM;
02056     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02057
02058     /* Prepare transfer parameters */
02059     hi2c->pBuffPtr    = pData;
02060     hi2c->XferCount   = Size;
02061     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02062     hi2c->XferISR     = I2C_Master_ISR_IT;
02063
02064     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02065     {
02066       hi2c->XferSize = MAX_NBYTE_SIZE;
02067       xfermode = I2C_RELOAD_MODE;
02068     }
02069     else
02070     {
02071       hi2c->XferSize = hi2c->XferCount;
02072       xfermode = I2C_AUTOEND_MODE;
02073     }
02074
02075     /* Send Slave Address and Memory Address */
02076     if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02077     {
02078       if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02079       {
02080         /* Process Unlocked */
02081         __HAL_UNLOCK(hi2c);
02082         return HAL_ERROR;
02083       }
02084       else
02085       {
02086         /* Process Unlocked */
02087         __HAL_UNLOCK(hi2c);
02088         return HAL_TIMEOUT;
02089       }
02090     }
02091
02092     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02093     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
02094
02095     /* Process Unlocked */
02096     __HAL_UNLOCK(hi2c);
02097
02098     /* Note : The I2C interrupts must be enabled after unlocking current process
02099               to avoid the risk of I2C interrupt handle execution before current
02100               process unlock */
02101
02102     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02103     /* possible to enable all of these */
02104     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02105     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02106
02107     return HAL_OK;
02108   }
02109   else
02110   {
02111     return HAL_BUSY;
02112   }
02113 }
02114
02115 /**
02116   * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
02117   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02118   *                the configuration information for the specified I2C.
02119   * @param  DevAddress Target device address: The device 7 bits address value
02120   *         in datasheet must be shift at right before call interface
02121   * @param  MemAddress Internal memory address
02122   * @param  MemAddSize Size of internal memory address
02123   * @param  pData Pointer to data buffer
02124   * @param  Size Amount of data to be sent
02125   * @retval HAL status
02126   */
02127 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02128 {
02129   uint32_t tickstart = 0U;
02130   uint32_t xfermode = 0U;
02131
02132   /* Check the parameters */
02133   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02134
02135   if (hi2c->State == HAL_I2C_STATE_READY)
02136   {
02137     if ((pData == NULL) || (Size == 0U))
02138     {
02139       return  HAL_ERROR;
02140     }
02141
02142     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02143     {
02144       return HAL_BUSY;
02145     }
02146
02147     /* Process Locked */
02148     __HAL_LOCK(hi2c);
02149
02150     /* Init tickstart for timeout management*/
02151     tickstart = HAL_GetTick();
02152
02153     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02154     hi2c->Mode        = HAL_I2C_MODE_MEM;
02155     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02156
02157     /* Prepare transfer parameters */
02158     hi2c->pBuffPtr    = pData;
02159     hi2c->XferCount   = Size;
02160     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02161     hi2c->XferISR     = I2C_Master_ISR_IT;
02162
02163     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02164     {
02165       hi2c->XferSize = MAX_NBYTE_SIZE;
02166       xfermode = I2C_RELOAD_MODE;
02167     }
02168     else
02169     {
02170       hi2c->XferSize = hi2c->XferCount;
02171       xfermode = I2C_AUTOEND_MODE;
02172     }
02173
02174     /* Send Slave Address and Memory Address */
02175     if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02176     {
02177       if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02178       {
02179         /* Process Unlocked */
02180         __HAL_UNLOCK(hi2c);
02181         return HAL_ERROR;
02182       }
02183       else
02184       {
02185         /* Process Unlocked */
02186         __HAL_UNLOCK(hi2c);
02187         return HAL_TIMEOUT;
02188       }
02189     }
02190
02191     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02192     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
02193
02194     /* Process Unlocked */
02195     __HAL_UNLOCK(hi2c);
02196
02197     /* Note : The I2C interrupts must be enabled after unlocking current process
02198               to avoid the risk of I2C interrupt handle execution before current
02199               process unlock */
02200
02201     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
02202     /* possible to enable all of these */
02203     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02204     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
02205
02206     return HAL_OK;
02207   }
02208   else
02209   {
02210     return HAL_BUSY;
02211   }
02212 }
02213 /**
02214   * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
02215   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02216   *                the configuration information for the specified I2C.
02217   * @param  DevAddress Target device address: The device 7 bits address value
02218   *         in datasheet must be shift at right before call interface
02219   * @param  MemAddress Internal memory address
02220   * @param  MemAddSize Size of internal memory address
02221   * @param  pData Pointer to data buffer
02222   * @param  Size Amount of data to be sent
02223   * @retval HAL status
02224   */
02225 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02226 {
02227   uint32_t tickstart = 0U;
02228   uint32_t xfermode = 0U;
02229
02230   /* Check the parameters */
02231   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02232
02233   if (hi2c->State == HAL_I2C_STATE_READY)
02234   {
02235     if ((pData == NULL) || (Size == 0U))
02236     {
02237       return  HAL_ERROR;
02238     }
02239
02240     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02241     {
02242       return HAL_BUSY;
02243     }
02244
02245     /* Process Locked */
02246     __HAL_LOCK(hi2c);
02247
02248     /* Init tickstart for timeout management*/
02249     tickstart = HAL_GetTick();
02250
02251     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02252     hi2c->Mode        = HAL_I2C_MODE_MEM;
02253     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02254
02255     /* Prepare transfer parameters */
02256     hi2c->pBuffPtr    = pData;
02257     hi2c->XferCount   = Size;
02258     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02259     hi2c->XferISR     = I2C_Master_ISR_DMA;
02260
02261     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02262     {
02263       hi2c->XferSize = MAX_NBYTE_SIZE;
02264       xfermode = I2C_RELOAD_MODE;
02265     }
02266     else
02267     {
02268       hi2c->XferSize = hi2c->XferCount;
02269       xfermode = I2C_AUTOEND_MODE;
02270     }
02271
02272     /* Send Slave Address and Memory Address */
02273     if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02274     {
02275       if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02276       {
02277         /* Process Unlocked */
02278         __HAL_UNLOCK(hi2c);
02279         return HAL_ERROR;
02280       }
02281       else
02282       {
02283         /* Process Unlocked */
02284         __HAL_UNLOCK(hi2c);
02285         return HAL_TIMEOUT;
02286       }
02287     }
02288
02289     /* Set the I2C DMA transfer complete callback */
02290     hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
02291
02292     /* Set the DMA error callback */
02293     hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
02294
02295     /* Set the unused DMA callbacks to NULL */
02296     hi2c->hdmatx->XferHalfCpltCallback = NULL;
02297     hi2c->hdmatx->XferAbortCallback = NULL;
02298
02299     /* Enable the DMA channel */
02300     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
02301
02302     /* Send Slave Address */
02303     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02304     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
02305
02306     /* Update XferCount value */
02307     hi2c->XferCount -= hi2c->XferSize;
02308
02309     /* Process Unlocked */
02310     __HAL_UNLOCK(hi2c);
02311
02312     /* Note : The I2C interrupts must be enabled after unlocking current process
02313               to avoid the risk of I2C interrupt handle execution before current
02314               process unlock */
02315     /* Enable ERR and NACK interrupts */
02316     I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
02317
02318     /* Enable DMA Request */
02319     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
02320
02321     return HAL_OK;
02322   }
02323   else
02324   {
02325     return HAL_BUSY;
02326   }
02327 }
02328
02329 /**
02330   * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
02331   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02332   *                the configuration information for the specified I2C.
02333   * @param  DevAddress Target device address: The device 7 bits address value
02334   *         in datasheet must be shift at right before call interface
02335   * @param  MemAddress Internal memory address
02336   * @param  MemAddSize Size of internal memory address
02337   * @param  pData Pointer to data buffer
02338   * @param  Size Amount of data to be read
02339   * @retval HAL status
02340   */
02341 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02342 {
02343   uint32_t tickstart = 0U;
02344   uint32_t xfermode = 0U;
02345
02346   /* Check the parameters */
02347   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02348
02349   if (hi2c->State == HAL_I2C_STATE_READY)
02350   {
02351     if ((pData == NULL) || (Size == 0U))
02352     {
02353       return  HAL_ERROR;
02354     }
02355
02356     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02357     {
02358       return HAL_BUSY;
02359     }
02360
02361     /* Process Locked */
02362     __HAL_LOCK(hi2c);
02363
02364     /* Init tickstart for timeout management*/
02365     tickstart = HAL_GetTick();
02366
02367     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02368     hi2c->Mode        = HAL_I2C_MODE_MEM;
02369     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02370
02371     /* Prepare transfer parameters */
02372     hi2c->pBuffPtr    = pData;
02373     hi2c->XferCount   = Size;
02374     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02375     hi2c->XferISR     = I2C_Master_ISR_DMA;
02376
02377     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02378     {
02379       hi2c->XferSize = MAX_NBYTE_SIZE;
02380       xfermode = I2C_RELOAD_MODE;
02381     }
02382     else
02383     {
02384       hi2c->XferSize = hi2c->XferCount;
02385       xfermode = I2C_AUTOEND_MODE;
02386     }
02387
02388     /* Send Slave Address and Memory Address */
02389     if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02390     {
02391       if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02392       {
02393         /* Process Unlocked */
02394         __HAL_UNLOCK(hi2c);
02395         return HAL_ERROR;
02396       }
02397       else
02398       {
02399         /* Process Unlocked */
02400         __HAL_UNLOCK(hi2c);
02401         return HAL_TIMEOUT;
02402       }
02403     }
02404
02405     /* Set the I2C DMA transfer complete callback */
02406     hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
02407
02408     /* Set the DMA error callback */
02409     hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
02410
02411     /* Set the unused DMA callbacks to NULL */
02412     hi2c->hdmarx->XferHalfCpltCallback = NULL;
02413     hi2c->hdmarx->XferAbortCallback = NULL;
02414
02415     /* Enable the DMA channel */
02416     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
02417
02418     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02419     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
02420
02421     /* Update XferCount value */
02422     hi2c->XferCount -= hi2c->XferSize;
02423
02424     /* Process Unlocked */
02425     __HAL_UNLOCK(hi2c);
02426
02427     /* Enable DMA Request */
02428     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
02429
02430     /* Note : The I2C interrupts must be enabled after unlocking current process
02431               to avoid the risk of I2C interrupt handle execution before current
02432               process unlock */
02433     /* Enable ERR and NACK interrupts */
02434     I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
02435
02436     return HAL_OK;
02437   }
02438   else
02439   {
02440     return HAL_BUSY;
02441   }
02442 }
02443
02444 /**
02445   * @brief  Checks if target device is ready for communication.
02446   * @note   This function is used with Memory devices
02447   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02448   *                the configuration information for the specified I2C.
02449   * @param  DevAddress Target device address: The device 7 bits address value
02450   *         in datasheet must be shift at right before call interface
02451   * @param  Trials Number of trials
02452   * @param  Timeout Timeout duration
02453   * @retval HAL status
02454   */
02455 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
02456 {
02457   uint32_t tickstart = 0U;
02458
02459   __IO uint32_t I2C_Trials = 0U;
02460
02461   if (hi2c->State == HAL_I2C_STATE_READY)
02462   {
02463     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02464     {
02465       return HAL_BUSY;
02466     }
02467
02468     /* Process Locked */
02469     __HAL_LOCK(hi2c);
02470
02471     hi2c->State = HAL_I2C_STATE_BUSY;
02472     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02473
02474     do
02475     {
02476       /* Generate Start */
02477       hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
02478
02479       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
02480       /* Wait until STOPF flag is set or a NACK flag is set*/
02481       tickstart = HAL_GetTick();
02482       while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
02483       {
02484         if (Timeout != HAL_MAX_DELAY)
02485         {
02486           if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
02487           {
02488             /* Device is ready */
02489             hi2c->State = HAL_I2C_STATE_READY;
02490             /* Process Unlocked */
02491             __HAL_UNLOCK(hi2c);
02492             return HAL_TIMEOUT;
02493           }
02494         }
02495       }
02496
02497       /* Check if the NACKF flag has not been set */
02498       if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
02499       {
02500         /* Wait until STOPF flag is reset */
02501         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
02502         {
02503           return HAL_TIMEOUT;
02504         }
02505
02506         /* Clear STOP Flag */
02507         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02508
02509         /* Device is ready */
02510         hi2c->State = HAL_I2C_STATE_READY;
02511
02512         /* Process Unlocked */
02513         __HAL_UNLOCK(hi2c);
02514
02515         return HAL_OK;
02516       }
02517       else
02518       {
02519         /* Wait until STOPF flag is reset */
02520         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
02521         {
02522           return HAL_TIMEOUT;
02523         }
02524
02525         /* Clear NACK Flag */
02526         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
02527
02528         /* Clear STOP Flag, auto generated with autoend*/
02529         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02530       }
02531
02532       /* Check if the maximum allowed number of trials has been reached */
02533       if (I2C_Trials++ == Trials)
02534       {
02535         /* Generate Stop */
02536         hi2c->Instance->CR2 |= I2C_CR2_STOP;
02537
02538         /* Wait until STOPF flag is reset */
02539         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
02540         {
02541           return HAL_TIMEOUT;
02542         }
02543
02544         /* Clear STOP Flag */
02545         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02546       }
02547     }
02548     while (I2C_Trials < Trials);
02549
02550     hi2c->State = HAL_I2C_STATE_READY;
02551
02552     /* Process Unlocked */
02553     __HAL_UNLOCK(hi2c);
02554
02555     return HAL_TIMEOUT;
02556   }
02557   else
02558   {
02559     return HAL_BUSY;
02560   }
02561 }
02562
02563 /**
02564   * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
02565   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02566   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02567   *                the configuration information for the specified I2C.
02568   * @param  DevAddress Target device address: The device 7 bits address value
02569   *         in datasheet must be shift at right before call interface
02570   * @param  pData Pointer to data buffer
02571   * @param  Size Amount of data to be sent
02572   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
02573   * @retval HAL status
02574   */
02575 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02576 {
02577   uint32_t xfermode = 0U;
02578   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
02579
02580   /* Check the parameters */
02581   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02582
02583   if (hi2c->State == HAL_I2C_STATE_READY)
02584   {
02585     /* Process Locked */
02586     __HAL_LOCK(hi2c);
02587
02588     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
02589     hi2c->Mode      = HAL_I2C_MODE_MASTER;
02590     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02591
02592     /* Prepare transfer parameters */
02593     hi2c->pBuffPtr    = pData;
02594     hi2c->XferCount   = Size;
02595     hi2c->XferOptions = XferOptions;
02596     hi2c->XferISR     = I2C_Master_ISR_IT;
02597
02598     /* If size > MAX_NBYTE_SIZE, use reload mode */
02599     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02600     {
02601       hi2c->XferSize = MAX_NBYTE_SIZE;
02602       xfermode = I2C_RELOAD_MODE;
02603     }
02604     else
02605     {
02606       hi2c->XferSize = hi2c->XferCount;
02607       xfermode = hi2c->XferOptions;
02608     }
02609
02610     /* If transfer direction not change, do not generate Restart Condition */
02611     /* Mean Previous state is same as current state */
02612     if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
02613     {
02614       xferrequest = I2C_NO_STARTSTOP;
02615     }
02616
02617     /* Send Slave Address and set NBYTES to write */
02618     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
02619
02620     /* Process Unlocked */
02621     __HAL_UNLOCK(hi2c);
02622
02623     /* Note : The I2C interrupts must be enabled after unlocking current process
02624               to avoid the risk of I2C interrupt handle execution before current
02625               process unlock */
02626     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02627
02628     return HAL_OK;
02629   }
02630   else
02631   {
02632     return HAL_BUSY;
02633   }
02634 }
02635
02636 /**
02637   * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
02638   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02639   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02640   *                the configuration information for the specified I2C.
02641   * @param  DevAddress Target device address: The device 7 bits address value
02642   *         in datasheet must be shift at right before call interface
02643   * @param  pData Pointer to data buffer
02644   * @param  Size Amount of data to be sent
02645   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
02646   * @retval HAL status
02647   */
02648 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02649 {
02650   uint32_t xfermode = 0U;
02651   uint32_t xferrequest = I2C_GENERATE_START_READ;
02652
02653   /* Check the parameters */
02654   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02655
02656   if (hi2c->State == HAL_I2C_STATE_READY)
02657   {
02658     /* Process Locked */
02659     __HAL_LOCK(hi2c);
02660
02661     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
02662     hi2c->Mode      = HAL_I2C_MODE_MASTER;
02663     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02664
02665     /* Prepare transfer parameters */
02666     hi2c->pBuffPtr    = pData;
02667     hi2c->XferCount   = Size;
02668     hi2c->XferOptions = XferOptions;
02669     hi2c->XferISR     = I2C_Master_ISR_IT;
02670
02671     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
02672     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02673     {
02674       hi2c->XferSize = MAX_NBYTE_SIZE;
02675       xfermode = I2C_RELOAD_MODE;
02676     }
02677     else
02678     {
02679       hi2c->XferSize = hi2c->XferCount;
02680       xfermode = hi2c->XferOptions;
02681     }
02682
02683     /* If transfer direction not change, do not generate Restart Condition */
02684     /* Mean Previous state is same as current state */
02685     if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
02686     {
02687       xferrequest = I2C_NO_STARTSTOP;
02688     }
02689
02690     /* Send Slave Address and set NBYTES to read */
02691     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
02692
02693     /* Process Unlocked */
02694     __HAL_UNLOCK(hi2c);
02695
02696     /* Note : The I2C interrupts must be enabled after unlocking current process
02697               to avoid the risk of I2C interrupt handle execution before current
02698               process unlock */
02699     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
02700
02701     return HAL_OK;
02702   }
02703   else
02704   {
02705     return HAL_BUSY;
02706   }
02707 }
02708
02709 /**
02710   * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
02711   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02712   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02713   *                the configuration information for the specified I2C.
02714   * @param  pData Pointer to data buffer
02715   * @param  Size Amount of data to be sent
02716   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
02717   * @retval HAL status
02718   */
02719 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02720 {
02721   /* Check the parameters */
02722   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02723
02724   if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
02725   {
02726     if ((pData == NULL) || (Size == 0U))
02727     {
02728       return  HAL_ERROR;
02729     }
02730
02731     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
02732     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
02733
02734     /* Process Locked */
02735     __HAL_LOCK(hi2c);
02736
02737     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
02738     /* and then toggle the HAL slave RX state to TX state */
02739     if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
02740     {
02741       /* Disable associated Interrupts */
02742       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
02743     }
02744
02745     hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
02746     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
02747     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02748
02749     /* Enable Address Acknowledge */
02750     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
02751
02752     /* Prepare transfer parameters */
02753     hi2c->pBuffPtr    = pData;
02754     hi2c->XferCount   = Size;
02755     hi2c->XferSize    = hi2c->XferCount;
02756     hi2c->XferOptions = XferOptions;
02757     hi2c->XferISR     = I2C_Slave_ISR_IT;
02758
02759     if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
02760     {
02761       /* Clear ADDR flag after prepare the transfer parameters */
02762       /* This action will generate an acknowledge to the Master */
02763       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
02764     }
02765
02766     /* Process Unlocked */
02767     __HAL_UNLOCK(hi2c);
02768
02769     /* Note : The I2C interrupts must be enabled after unlocking current process
02770     to avoid the risk of I2C interrupt handle execution before current
02771     process unlock */
02772     /* REnable ADDR interrupt */
02773     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
02774
02775     return HAL_OK;
02776   }
02777   else
02778   {
02779     return HAL_ERROR;
02780   }
02781 }
02782
02783 /**
02784   * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
02785   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02786   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02787   *                the configuration information for the specified I2C.
02788   * @param  pData Pointer to data buffer
02789   * @param  Size Amount of data to be sent
02790   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
02791   * @retval HAL status
02792   */
02793 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02794 {
02795   /* Check the parameters */
02796   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02797
02798   if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
02799   {
02800     if ((pData == NULL) || (Size == 0U))
02801     {
02802       return  HAL_ERROR;
02803     }
02804
02805     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
02806     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
02807
02808     /* Process Locked */
02809     __HAL_LOCK(hi2c);
02810
02811     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
02812     /* and then toggle the HAL slave TX state to RX state */
02813     if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
02814     {
02815       /* Disable associated Interrupts */
02816       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
02817     }
02818
02819     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
02820     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
02821     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02822
02823     /* Enable Address Acknowledge */
02824     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
02825
02826     /* Prepare transfer parameters */
02827     hi2c->pBuffPtr    = pData;
02828     hi2c->XferCount   = Size;
02829     hi2c->XferSize    = hi2c->XferCount;
02830     hi2c->XferOptions = XferOptions;
02831     hi2c->XferISR     = I2C_Slave_ISR_IT;
02832
02833     if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
02834     {
02835       /* Clear ADDR flag after prepare the transfer parameters */
02836       /* This action will generate an acknowledge to the Master */
02837       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
02838     }
02839
02840     /* Process Unlocked */
02841     __HAL_UNLOCK(hi2c);
02842
02843     /* Note : The I2C interrupts must be enabled after unlocking current process
02844     to avoid the risk of I2C interrupt handle execution before current
02845     process unlock */
02846     /* REnable ADDR interrupt */
02847     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
02848
02849     return HAL_OK;
02850   }
02851   else
02852   {
02853     return HAL_ERROR;
02854   }
02855 }
02856
02857 /**
02858   * @brief  Enable the Address listen mode with Interrupt.
02859   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02860   *                the configuration information for the specified I2C.
02861   * @retval HAL status
02862   */
02863 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
02864 {
02865   if (hi2c->State == HAL_I2C_STATE_READY)
02866   {
02867     hi2c->State = HAL_I2C_STATE_LISTEN;
02868     hi2c->XferISR = I2C_Slave_ISR_IT;
02869
02870     /* Enable the Address Match interrupt */
02871     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
02872
02873     return HAL_OK;
02874   }
02875   else
02876   {
02877     return HAL_BUSY;
02878   }
02879 }
02880
02881 /**
02882   * @brief  Disable the Address listen mode with Interrupt.
02883   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02884   *                the configuration information for the specified I2C
02885   * @retval HAL status
02886   */
02887 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
02888 {
02889   /* Declaration of tmp to prevent undefined behavior of volatile usage */
02890   uint32_t tmp;
02891
02892   /* Disable Address listen mode only if a transfer is not ongoing */
02893   if (hi2c->State == HAL_I2C_STATE_LISTEN)
02894   {
02895     tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
02896     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
02897     hi2c->State = HAL_I2C_STATE_READY;
02898     hi2c->Mode = HAL_I2C_MODE_NONE;
02899     hi2c->XferISR = NULL;
02900
02901     /* Disable the Address Match interrupt */
02902     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
02903
02904     return HAL_OK;
02905   }
02906   else
02907   {
02908     return HAL_BUSY;
02909   }
02910 }
02911
02912 /**
02913   * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
02914   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02915   *                the configuration information for the specified I2C.
02916   * @param  DevAddress Target device address: The device 7 bits address value
02917   *         in datasheet must be shift at right before call interface
02918   * @retval HAL status
02919   */
02920 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
02921 {
02922   if (hi2c->Mode == HAL_I2C_MODE_MASTER)
02923   {
02924     /* Process Locked */
02925     __HAL_LOCK(hi2c);
02926
02927     /* Disable Interrupts */
02928     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
02929     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
02930
02931     /* Set State at HAL_I2C_STATE_ABORT */
02932     hi2c->State = HAL_I2C_STATE_ABORT;
02933
02934     /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
02935     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
02936     I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
02937
02938     /* Process Unlocked */
02939     __HAL_UNLOCK(hi2c);
02940
02941     /* Note : The I2C interrupts must be enabled after unlocking current process
02942               to avoid the risk of I2C interrupt handle execution before current
02943               process unlock */
02944     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
02945
02946     return HAL_OK;
02947   }
02948   else
02949   {
02950     /* Wrong usage of abort function */
02951     /* This function should be used only in case of abort monitored by master device */
02952     return HAL_ERROR;
02953   }
02954 }
02955
02956 /**
02957   * @}
02958   */
02959
02960 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
02961  * @{
02962  */
02963
02964 /**
02965   * @brief  This function handles I2C event interrupt request.
02966   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02967   *                the configuration information for the specified I2C.
02968   * @retval None
02969   */
02970 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
02971 {
02972   /* Get current IT Flags and IT sources value */
02973   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
02974   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
02975
02976   /* I2C events treatment -------------------------------------*/
02977   if (hi2c->XferISR != NULL)
02978   {
02979     hi2c->XferISR(hi2c, itflags, itsources);
02980   }
02981 }
02982
02983 /**
02984   * @brief  This function handles I2C error interrupt request.
02985   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02986   *                the configuration information for the specified I2C.
02987   * @retval None
02988   */
02989 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
02990 {
02991   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
02992   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
02993
02994   /* I2C Bus error interrupt occurred ------------------------------------*/
02995   if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
02996   {
02997     hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
02998
02999     /* Clear BERR flag */
03000     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
03001   }
03002
03003   /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
03004   if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
03005   {
03006     hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
03007
03008     /* Clear OVR flag */
03009     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
03010   }
03011
03012   /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
03013   if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
03014   {
03015     hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
03016
03017     /* Clear ARLO flag */
03018     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
03019   }
03020
03021   /* Call the Error Callback in case of Error detected */
03022   if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
03023   {
03024     I2C_ITError(hi2c, hi2c->ErrorCode);
03025   }
03026 }
03027
03028 /**
03029   * @brief  Master Tx Transfer completed callback.
03030   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03031   *                the configuration information for the specified I2C.
03032   * @retval None
03033   */
03034 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
03035 {
03036   /* Prevent unused argument(s) compilation warning */
03037   UNUSED(hi2c);
03038
03039   /* NOTE : This function should not be modified, when the callback is needed,
03040             the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
03041    */
03042 }
03043
03044 /**
03045   * @brief  Master Rx Transfer completed callback.
03046   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03047   *                the configuration information for the specified I2C.
03048   * @retval None
03049   */
03050 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
03051 {
03052   /* Prevent unused argument(s) compilation warning */
03053   UNUSED(hi2c);
03054
03055   /* NOTE : This function should not be modified, when the callback is needed,
03056             the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
03057    */
03058 }
03059
03060 /** @brief  Slave Tx Transfer completed callback.
03061   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03062   *                the configuration information for the specified I2C.
03063   * @retval None
03064   */
03065 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
03066 {
03067   /* Prevent unused argument(s) compilation warning */
03068   UNUSED(hi2c);
03069
03070   /* NOTE : This function should not be modified, when the callback is needed,
03071             the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
03072    */
03073 }
03074
03075 /**
03076   * @brief  Slave Rx Transfer completed callback.
03077   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03078   *                the configuration information for the specified I2C.
03079   * @retval None
03080   */
03081 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
03082 {
03083   /* Prevent unused argument(s) compilation warning */
03084   UNUSED(hi2c);
03085
03086   /* NOTE : This function should not be modified, when the callback is needed,
03087             the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
03088    */
03089 }
03090
03091 /**
03092   * @brief  Slave Address Match callback.
03093   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03094   *                the configuration information for the specified I2C.
03095   * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
03096   * @param  AddrMatchCode Address Match Code
03097   * @retval None
03098   */
03099 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
03100 {
03101   /* Prevent unused argument(s) compilation warning */
03102   UNUSED(hi2c);
03103   UNUSED(TransferDirection);
03104   UNUSED(AddrMatchCode);
03105
03106   /* NOTE : This function should not be modified, when the callback is needed,
03107             the HAL_I2C_AddrCallback() could be implemented in the user file
03108    */
03109 }
03110
03111 /**
03112   * @brief  Listen Complete callback.
03113   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03114   *                the configuration information for the specified I2C.
03115   * @retval None
03116   */
03117 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
03118 {
03119   /* Prevent unused argument(s) compilation warning */
03120   UNUSED(hi2c);
03121
03122   /* NOTE : This function should not be modified, when the callback is needed,
03123             the HAL_I2C_ListenCpltCallback() could be implemented in the user file
03124    */
03125 }
03126
03127 /**
03128   * @brief  Memory Tx Transfer completed callback.
03129   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03130   *                the configuration information for the specified I2C.
03131   * @retval None
03132   */
03133 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
03134 {
03135   /* Prevent unused argument(s) compilation warning */
03136   UNUSED(hi2c);
03137
03138   /* NOTE : This function should not be modified, when the callback is needed,
03139             the HAL_I2C_MemTxCpltCallback could be implemented in the user file
03140    */
03141 }
03142
03143 /**
03144   * @brief  Memory Rx Transfer completed callback.
03145   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03146   *                the configuration information for the specified I2C.
03147   * @retval None
03148   */
03149 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
03150 {
03151   /* Prevent unused argument(s) compilation warning */
03152   UNUSED(hi2c);
03153
03154   /* NOTE : This function should not be modified, when the callback is needed,
03155             the HAL_I2C_MemRxCpltCallback could be implemented in the user file
03156    */
03157 }
03158
03159 /**
03160   * @brief  I2C error callback.
03161   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03162   *                the configuration information for the specified I2C.
03163   * @retval None
03164   */
03165 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
03166 {
03167   /* Prevent unused argument(s) compilation warning */
03168   UNUSED(hi2c);
03169
03170   /* NOTE : This function should not be modified, when the callback is needed,
03171             the HAL_I2C_ErrorCallback could be implemented in the user file
03172    */
03173 }
03174
03175 /**
03176   * @brief  I2C abort callback.
03177   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03178   *                the configuration information for the specified I2C.
03179   * @retval None
03180   */
03181 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
03182 {
03183   /* Prevent unused argument(s) compilation warning */
03184   UNUSED(hi2c);
03185
03186   /* NOTE : This function should not be modified, when the callback is needed,
03187             the HAL_I2C_AbortCpltCallback could be implemented in the user file
03188    */
03189 }
03190
03191 /**
03192   * @}
03193   */
03194
03195 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
03196  *  @brief   Peripheral State, Mode and Error functions
03197  *
03198 @verbatim
03199  ===============================================================================
03200             ##### Peripheral State, Mode and Error functions #####
03201  ===============================================================================
03202     [..]
03203     This subsection permit to get in run-time the status of the peripheral
03204     and the data flow.
03205
03206 @endverbatim
03207   * @{
03208   */
03209
03210 /**
03211   * @brief  Return the I2C handle state.
03212   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03213   *                the configuration information for the specified I2C.
03214   * @retval HAL state
03215   */
03216 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
03217 {
03218   /* Return I2C handle state */
03219   return hi2c->State;
03220 }
03221
03222 /**
03223   * @brief  Returns the I2C Master, Slave, Memory or no mode.
03224   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03225   *         the configuration information for I2C module
03226   * @retval HAL mode
03227   */
03228 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
03229 {
03230   return hi2c->Mode;
03231 }
03232
03233 /**
03234 * @brief  Return the I2C error code.
03235   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03236   *              the configuration information for the specified I2C.
03237 * @retval I2C Error Code
03238 */
03239 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
03240 {
03241   return hi2c->ErrorCode;
03242 }
03243
03244 /**
03245   * @}
03246   */
03247
03248 /**
03249   * @}
03250   */
03251
03252 /** @addtogroup I2C_Private_Functions
03253   * @{
03254   */
03255
03256 /**
03257   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
03258   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03259   *                the configuration information for the specified I2C.
03260   * @param  ITFlags Interrupt flags to handle.
03261   * @param  ITSources Interrupt sources enabled.
03262   * @retval HAL status
03263   */
03264 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
03265 {
03266   uint16_t devaddress = 0U;
03267
03268   /* Process Locked */
03269   __HAL_LOCK(hi2c);
03270
03271   if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
03272   {
03273     /* Clear NACK Flag */
03274     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03275
03276     /* Set corresponding Error Code */
03277     /* No need to generate STOP, it is automatically done */
03278     /* Error callback will be send during stop flag treatment */
03279     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03280
03281     /* Flush TX register */
03282     I2C_Flush_TXDR(hi2c);
03283   }
03284   else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
03285   {
03286     /* Read data from RXDR */
03287     (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
03288     hi2c->XferSize--;
03289     hi2c->XferCount--;
03290   }
03291   else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
03292   {
03293     /* Write data to TXDR */
03294     hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
03295     hi2c->XferSize--;
03296     hi2c->XferCount--;
03297   }
03298   else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
03299   {
03300     if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
03301     {
03302       devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
03303
03304       if (hi2c->XferCount > MAX_NBYTE_SIZE)
03305       {
03306         hi2c->XferSize = MAX_NBYTE_SIZE;
03307         I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
03308       }
03309       else
03310       {
03311         hi2c->XferSize = hi2c->XferCount;
03312         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
03313         {
03314           I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
03315         }
03316         else
03317         {
03318           I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
03319         }
03320       }
03321     }
03322     else
03323     {
03324       /* Call TxCpltCallback() if no stop mode is set */
03325       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
03326       {
03327         /* Call I2C Master Sequential complete process */
03328         I2C_ITMasterSequentialCplt(hi2c);
03329       }
03330       else
03331       {
03332         /* Wrong size Status regarding TCR flag event */
03333         /* Call the corresponding callback to inform upper layer of End of Transfer */
03334         I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
03335       }
03336     }
03337   }
03338   else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
03339   {
03340     if (hi2c->XferCount == 0U)
03341     {
03342       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
03343       {
03344         /* Generate a stop condition in case of no transfer option */
03345         if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
03346         {
03347           /* Generate Stop */
03348           hi2c->Instance->CR2 |= I2C_CR2_STOP;
03349         }
03350         else
03351         {
03352           /* Call I2C Master Sequential complete process */
03353           I2C_ITMasterSequentialCplt(hi2c);
03354         }
03355       }
03356     }
03357     else
03358     {
03359       /* Wrong size Status regarding TC flag event */
03360       /* Call the corresponding callback to inform upper layer of End of Transfer */
03361       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
03362     }
03363   }
03364
03365   if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
03366   {
03367     /* Call I2C Master complete process */
03368     I2C_ITMasterCplt(hi2c, ITFlags);
03369   }
03370
03371   /* Process Unlocked */
03372   __HAL_UNLOCK(hi2c);
03373
03374   return HAL_OK;
03375 }
03376
03377 /**
03378   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
03379   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03380   *                the configuration information for the specified I2C.
03381   * @param  ITFlags Interrupt flags to handle.
03382   * @param  ITSources Interrupt sources enabled.
03383   * @retval HAL status
03384   */
03385 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
03386 {
03387   /* Process locked */
03388   __HAL_LOCK(hi2c);
03389
03390   if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
03391   {
03392     /* Check that I2C transfer finished */
03393     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
03394     /* Mean XferCount == 0*/
03395     /* So clear Flag NACKF only */
03396     if (hi2c->XferCount == 0U)
03397     {
03398       if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
03399           (hi2c->State == HAL_I2C_STATE_LISTEN))
03400       {
03401         /* Call I2C Listen complete process */
03402         I2C_ITListenCplt(hi2c, ITFlags);
03403       }
03404       else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
03405       {
03406         /* Clear NACK Flag */
03407         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03408
03409         /* Flush TX register */
03410         I2C_Flush_TXDR(hi2c);
03411
03412         /* Last Byte is Transmitted */
03413         /* Call I2C Slave Sequential complete process */
03414         I2C_ITSlaveSequentialCplt(hi2c);
03415       }
03416       else
03417       {
03418         /* Clear NACK Flag */
03419         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03420       }
03421     }
03422     else
03423     {
03424       /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
03425       /* Clear NACK Flag */
03426       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03427
03428       /* Set ErrorCode corresponding to a Non-Acknowledge */
03429       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03430     }
03431   }
03432   else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
03433   {
03434     if (hi2c->XferCount > 0U)
03435     {
03436       /* Read data from RXDR */
03437       (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
03438       hi2c->XferSize--;
03439       hi2c->XferCount--;
03440     }
03441
03442     if ((hi2c->XferCount == 0U) && \
03443         (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
03444     {
03445       /* Call I2C Slave Sequential complete process */
03446       I2C_ITSlaveSequentialCplt(hi2c);
03447     }
03448   }
03449   else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
03450   {
03451     I2C_ITAddrCplt(hi2c, ITFlags);
03452   }
03453   else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
03454   {
03455     /* Write data to TXDR only if XferCount not reach "0" */
03456     /* A TXIS flag can be set, during STOP treatment      */
03457     /* Check if all Datas have already been sent */
03458     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
03459     if (hi2c->XferCount > 0U)
03460     {
03461       /* Write data to TXDR */
03462       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
03463       hi2c->XferCount--;
03464       hi2c->XferSize--;
03465     }
03466     else
03467     {
03468       if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
03469       {
03470         /* Last Byte is Transmitted */
03471         /* Call I2C Slave Sequential complete process */
03472         I2C_ITSlaveSequentialCplt(hi2c);
03473       }
03474     }
03475   }
03476
03477   /* Check if STOPF is set */
03478   if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
03479   {
03480     /* Call I2C Slave complete process */
03481     I2C_ITSlaveCplt(hi2c, ITFlags);
03482   }
03483
03484   /* Process Unlocked */
03485   __HAL_UNLOCK(hi2c);
03486
03487   return HAL_OK;
03488 }
03489
03490 /**
03491   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
03492   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03493   *                the configuration information for the specified I2C.
03494   * @param  ITFlags Interrupt flags to handle.
03495   * @param  ITSources Interrupt sources enabled.
03496   * @retval HAL status
03497   */
03498 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
03499 {
03500   uint16_t devaddress = 0U;
03501   uint32_t xfermode = 0U;
03502
03503   /* Process Locked */
03504   __HAL_LOCK(hi2c);
03505
03506   if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
03507   {
03508     /* Clear NACK Flag */
03509     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03510
03511     /* Set corresponding Error Code */
03512     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03513
03514     /* No need to generate STOP, it is automatically done */
03515     /* But enable STOP interrupt, to treat it */
03516     /* Error callback will be send during stop flag treatment */
03517     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
03518
03519     /* Flush TX register */
03520     I2C_Flush_TXDR(hi2c);
03521   }
03522   else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
03523   {
03524     /* Disable TC interrupt */
03525     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
03526
03527     if (hi2c->XferCount != 0U)
03528     {
03529       /* Recover Slave address */
03530       devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
03531
03532       /* Prepare the new XferSize to transfer */
03533       if (hi2c->XferCount > MAX_NBYTE_SIZE)
03534       {
03535         hi2c->XferSize = MAX_NBYTE_SIZE;
03536         xfermode = I2C_RELOAD_MODE;
03537       }
03538       else
03539       {
03540         hi2c->XferSize = hi2c->XferCount;
03541         xfermode = I2C_AUTOEND_MODE;
03542       }
03543
03544       /* Set the new XferSize in Nbytes register */
03545       I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
03546
03547       /* Update XferCount value */
03548       hi2c->XferCount -= hi2c->XferSize;
03549
03550       /* Enable DMA Request */
03551       if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
03552       {
03553         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
03554       }
03555       else
03556       {
03557         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
03558       }
03559     }
03560     else
03561     {
03562       /* Wrong size Status regarding TCR flag event */
03563       /* Call the corresponding callback to inform upper layer of End of Transfer */
03564       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
03565     }
03566   }
03567   else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
03568   {
03569     /* Call I2C Master complete process */
03570     I2C_ITMasterCplt(hi2c, ITFlags);
03571   }
03572
03573   /* Process Unlocked */
03574   __HAL_UNLOCK(hi2c);
03575
03576   return HAL_OK;
03577 }
03578
03579 /**
03580   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
03581   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03582   *                the configuration information for the specified I2C.
03583   * @param  ITFlags Interrupt flags to handle.
03584   * @param  ITSources Interrupt sources enabled.
03585   * @retval HAL status
03586   */
03587 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
03588 {
03589   /* Process locked */
03590   __HAL_LOCK(hi2c);
03591
03592   if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
03593   {
03594     /* Check that I2C transfer finished */
03595     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
03596     /* Mean XferCount == 0 */
03597     /* So clear Flag NACKF only */
03598     if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
03599     {
03600       /* Clear NACK Flag */
03601       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03602     }
03603     else
03604     {
03605       /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
03606       /* Clear NACK Flag */
03607       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03608
03609       /* Set ErrorCode corresponding to a Non-Acknowledge */
03610       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03611     }
03612   }
03613   else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
03614   {
03615     /* Clear ADDR flag */
03616     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
03617   }
03618   else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
03619   {
03620     /* Call I2C Slave complete process */
03621     I2C_ITSlaveCplt(hi2c, ITFlags);
03622   }
03623
03624   /* Process Unlocked */
03625   __HAL_UNLOCK(hi2c);
03626
03627   return HAL_OK;
03628 }
03629
03630 /**
03631   * @brief  Master sends target device address followed by internal memory address for write request.
03632   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03633   *                the configuration information for the specified I2C.
03634   * @param  DevAddress Target device address: The device 7 bits address value
03635   *         in datasheet must be shift at right before call interface
03636   * @param  MemAddress Internal memory address
03637   * @param  MemAddSize Size of internal memory address
03638   * @param  Timeout Timeout duration
03639   * @param  Tickstart Tick start value
03640   * @retval HAL status
03641   */
03642 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
03643 {
03644   I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
03645
03646   /* Wait until TXIS flag is set */
03647   if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
03648   {
03649     if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03650     {
03651       return HAL_ERROR;
03652     }
03653     else
03654     {
03655       return HAL_TIMEOUT;
03656     }
03657   }
03658
03659   /* If Memory address size is 8Bit */
03660   if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
03661   {
03662     /* Send Memory Address */
03663     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03664   }
03665   /* If Memory address size is 16Bit */
03666   else
03667   {
03668     /* Send MSB of Memory Address */
03669     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
03670
03671     /* Wait until TXIS flag is set */
03672     if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
03673     {
03674       if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03675       {
03676         return HAL_ERROR;
03677       }
03678       else
03679       {
03680         return HAL_TIMEOUT;
03681       }
03682     }
03683
03684     /* Send LSB of Memory Address */
03685     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03686   }
03687
03688   /* Wait until TCR flag is set */
03689   if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
03690   {
03691     return HAL_TIMEOUT;
03692   }
03693
03694   return HAL_OK;
03695 }
03696
03697 /**
03698   * @brief  Master sends target device address followed by internal memory address for read request.
03699   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03700   *                the configuration information for the specified I2C.
03701   * @param  DevAddress Target device address: The device 7 bits address value
03702   *         in datasheet must be shift at right before call interface
03703   * @param  MemAddress Internal memory address
03704   * @param  MemAddSize Size of internal memory address
03705   * @param  Timeout Timeout duration
03706   * @param  Tickstart Tick start value
03707   * @retval HAL status
03708   */
03709 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
03710 {
03711   I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
03712
03713   /* Wait until TXIS flag is set */
03714   if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
03715   {
03716     if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03717     {
03718       return HAL_ERROR;
03719     }
03720     else
03721     {
03722       return HAL_TIMEOUT;
03723     }
03724   }
03725
03726   /* If Memory address size is 8Bit */
03727   if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
03728   {
03729     /* Send Memory Address */
03730     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03731   }
03732   /* If Memory address size is 16Bit */
03733   else
03734   {
03735     /* Send MSB of Memory Address */
03736     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
03737
03738     /* Wait until TXIS flag is set */
03739     if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
03740     {
03741       if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03742       {
03743         return HAL_ERROR;
03744       }
03745       else
03746       {
03747         return HAL_TIMEOUT;
03748       }
03749     }
03750
03751     /* Send LSB of Memory Address */
03752     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03753   }
03754
03755   /* Wait until TC flag is set */
03756   if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
03757   {
03758     return HAL_TIMEOUT;
03759   }
03760
03761   return HAL_OK;
03762 }
03763
03764 /**
03765   * @brief  I2C Address complete process callback.
03766   * @param  hi2c I2C handle.
03767   * @param  ITFlags Interrupt flags to handle.
03768   * @retval None
03769   */
03770 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
03771 {
03772   uint8_t transferdirection = 0U;
03773   uint16_t slaveaddrcode = 0U;
03774   uint16_t ownadd1code = 0U;
03775   uint16_t ownadd2code = 0U;
03776
03777   /* Prevent unused argument(s) compilation warning */
03778   UNUSED(ITFlags);
03779
03780   /* In case of Listen state, need to inform upper layer of address match code event */
03781   if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
03782   {
03783     transferdirection = I2C_GET_DIR(hi2c);
03784     slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
03785     ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
03786     ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
03787
03788     /* If 10bits addressing mode is selected */
03789     if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
03790     {
03791       if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
03792       {
03793         slaveaddrcode = ownadd1code;
03794         hi2c->AddrEventCount++;
03795         if (hi2c->AddrEventCount == 2U)
03796         {
03797           /* Reset Address Event counter */
03798           hi2c->AddrEventCount = 0U;
03799
03800           /* Clear ADDR flag */
03801           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
03802
03803           /* Process Unlocked */
03804           __HAL_UNLOCK(hi2c);
03805
03806           /* Call Slave Addr callback */
03807           HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
03808         }
03809       }
03810       else
03811       {
03812         slaveaddrcode = ownadd2code;
03813
03814         /* Disable ADDR Interrupts */
03815         I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
03816
03817         /* Process Unlocked */
03818         __HAL_UNLOCK(hi2c);
03819
03820         /* Call Slave Addr callback */
03821         HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
03822       }
03823     }
03824     /* else 7 bits addressing mode is selected */
03825     else
03826     {
03827       /* Disable ADDR Interrupts */
03828       I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
03829
03830       /* Process Unlocked */
03831       __HAL_UNLOCK(hi2c);
03832
03833       /* Call Slave Addr callback */
03834       HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
03835     }
03836   }
03837   /* Else clear address flag only */
03838   else
03839   {
03840     /* Clear ADDR flag */
03841     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
03842
03843     /* Process Unlocked */
03844     __HAL_UNLOCK(hi2c);
03845   }
03846 }
03847
03848 /**
03849   * @brief  I2C Master sequential complete process.
03850   * @param  hi2c I2C handle.
03851   * @retval None
03852   */
03853 static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
03854 {
03855   /* Reset I2C handle mode */
03856   hi2c->Mode = HAL_I2C_MODE_NONE;
03857
03858   /* No Generate Stop, to permit restart mode */
03859   /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
03860   if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
03861   {
03862     hi2c->State         = HAL_I2C_STATE_READY;
03863     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
03864     hi2c->XferISR       = NULL;
03865
03866     /* Disable Interrupts */
03867     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
03868
03869     /* Process Unlocked */
03870     __HAL_UNLOCK(hi2c);
03871
03872     /* Call the corresponding callback to inform upper layer of End of Transfer */
03873     HAL_I2C_MasterTxCpltCallback(hi2c);
03874   }
03875   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
03876   else
03877   {
03878     hi2c->State         = HAL_I2C_STATE_READY;
03879     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
03880     hi2c->XferISR       = NULL;
03881
03882     /* Disable Interrupts */
03883     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
03884
03885     /* Process Unlocked */
03886     __HAL_UNLOCK(hi2c);
03887
03888     /* Call the corresponding callback to inform upper layer of End of Transfer */
03889     HAL_I2C_MasterRxCpltCallback(hi2c);
03890   }
03891 }
03892
03893 /**
03894   * @brief  I2C Slave sequential complete process.
03895   * @param  hi2c I2C handle.
03896   * @retval None
03897   */
03898 static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
03899 {
03900   /* Reset I2C handle mode */
03901   hi2c->Mode = HAL_I2C_MODE_NONE;
03902
03903   if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
03904   {
03905     /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
03906     hi2c->State         = HAL_I2C_STATE_LISTEN;
03907     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
03908
03909     /* Disable Interrupts */
03910     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
03911
03912     /* Process Unlocked */
03913     __HAL_UNLOCK(hi2c);
03914
03915     /* Call the Tx complete callback to inform upper layer of the end of transmit process */
03916     HAL_I2C_SlaveTxCpltCallback(hi2c);
03917   }
03918
03919   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
03920   {
03921     /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
03922     hi2c->State         = HAL_I2C_STATE_LISTEN;
03923     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
03924
03925     /* Disable Interrupts */
03926     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
03927
03928     /* Process Unlocked */
03929     __HAL_UNLOCK(hi2c);
03930
03931     /* Call the Rx complete callback to inform upper layer of the end of receive process */
03932     HAL_I2C_SlaveRxCpltCallback(hi2c);
03933   }
03934 }
03935
03936 /**
03937   * @brief  I2C Master complete process.
03938   * @param  hi2c I2C handle.
03939   * @param  ITFlags Interrupt flags to handle.
03940   * @retval None
03941   */
03942 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
03943 {
03944   /* Clear STOP Flag */
03945   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03946
03947   /* Clear Configuration Register 2 */
03948   I2C_RESET_CR2(hi2c);
03949
03950   /* Reset handle parameters */
03951   hi2c->PreviousState = I2C_STATE_NONE;
03952   hi2c->XferISR       = NULL;
03953   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
03954
03955   if ((ITFlags & I2C_FLAG_AF) != RESET)
03956   {
03957     /* Clear NACK Flag */
03958     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03959
03960     /* Set acknowledge error code */
03961     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03962   }
03963
03964   /* Flush TX register */
03965   I2C_Flush_TXDR(hi2c);
03966
03967   /* Disable Interrupts */
03968   I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
03969
03970   /* Call the corresponding callback to inform upper layer of End of Transfer */
03971   if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))
03972   {
03973     /* Call the corresponding callback to inform upper layer of End of Transfer */
03974     I2C_ITError(hi2c, hi2c->ErrorCode);
03975   }
03976   /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
03977   else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
03978   {
03979     hi2c->State = HAL_I2C_STATE_READY;
03980
03981     if (hi2c->Mode == HAL_I2C_MODE_MEM)
03982     {
03983       hi2c->Mode = HAL_I2C_MODE_NONE;
03984
03985       /* Process Unlocked */
03986       __HAL_UNLOCK(hi2c);
03987
03988       /* Call the corresponding callback to inform upper layer of End of Transfer */
03989       HAL_I2C_MemTxCpltCallback(hi2c);
03990     }
03991     else
03992     {
03993       hi2c->Mode = HAL_I2C_MODE_NONE;
03994
03995       /* Process Unlocked */
03996       __HAL_UNLOCK(hi2c);
03997
03998       /* Call the corresponding callback to inform upper layer of End of Transfer */
03999       HAL_I2C_MasterTxCpltCallback(hi2c);
04000     }
04001   }
04002   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
04003   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
04004   {
04005     hi2c->State = HAL_I2C_STATE_READY;
04006
04007     if (hi2c->Mode == HAL_I2C_MODE_MEM)
04008     {
04009       hi2c->Mode = HAL_I2C_MODE_NONE;
04010
04011       /* Process Unlocked */
04012       __HAL_UNLOCK(hi2c);
04013
04014       HAL_I2C_MemRxCpltCallback(hi2c);
04015     }
04016     else
04017     {
04018       hi2c->Mode = HAL_I2C_MODE_NONE;
04019
04020       /* Process Unlocked */
04021       __HAL_UNLOCK(hi2c);
04022
04023       HAL_I2C_MasterRxCpltCallback(hi2c);
04024     }
04025   }
04026 }
04027
04028 /**
04029   * @brief  I2C Slave complete process.
04030   * @param  hi2c I2C handle.
04031   * @param  ITFlags Interrupt flags to handle.
04032   * @retval None
04033   */
04034 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
04035 {
04036   /* Clear STOP Flag */
04037   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
04038
04039   /* Clear ADDR flag */
04040   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
04041
04042   /* Disable all interrupts */
04043   I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
04044
04045   /* Disable Address Acknowledge */
04046   hi2c->Instance->CR2 |= I2C_CR2_NACK;
04047
04048   /* Clear Configuration Register 2 */
04049   I2C_RESET_CR2(hi2c);
04050
04051   /* Flush TX register */
04052   I2C_Flush_TXDR(hi2c);
04053
04054   /* If a DMA is ongoing, Update handle size context */
04055   if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
04056       ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
04057   {
04058     hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c);
04059   }
04060
04061   /* All data are not transferred, so set error code accordingly */
04062   if (hi2c->XferCount != 0U)
04063   {
04064     /* Set ErrorCode corresponding to a Non-Acknowledge */
04065     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04066   }
04067
04068   /* Store Last receive data if any */
04069   if (((ITFlags & I2C_FLAG_RXNE) != RESET))
04070   {
04071     /* Read data from RXDR */
04072     (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
04073
04074     if ((hi2c->XferSize > 0U))
04075     {
04076       hi2c->XferSize--;
04077       hi2c->XferCount--;
04078
04079       /* Set ErrorCode corresponding to a Non-Acknowledge */
04080       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04081     }
04082   }
04083
04084   hi2c->PreviousState = I2C_STATE_NONE;
04085   hi2c->Mode = HAL_I2C_MODE_NONE;
04086   hi2c->XferISR = NULL;
04087
04088   if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
04089   {
04090     /* Call the corresponding callback to inform upper layer of End of Transfer */
04091     I2C_ITError(hi2c, hi2c->ErrorCode);
04092
04093     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
04094     if (hi2c->State == HAL_I2C_STATE_LISTEN)
04095     {
04096       /* Call I2C Listen complete process */
04097       I2C_ITListenCplt(hi2c, ITFlags);
04098     }
04099   }
04100   else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
04101   {
04102     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
04103     hi2c->State = HAL_I2C_STATE_READY;
04104
04105     /* Process Unlocked */
04106     __HAL_UNLOCK(hi2c);
04107
04108     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
04109     HAL_I2C_ListenCpltCallback(hi2c);
04110   }
04111   /* Call the corresponding callback to inform upper layer of End of Transfer */
04112   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
04113   {
04114     hi2c->State = HAL_I2C_STATE_READY;
04115
04116     /* Process Unlocked */
04117     __HAL_UNLOCK(hi2c);
04118
04119     /* Call the Slave Rx Complete callback */
04120     HAL_I2C_SlaveRxCpltCallback(hi2c);
04121   }
04122   else
04123   {
04124     hi2c->State = HAL_I2C_STATE_READY;
04125
04126     /* Process Unlocked */
04127     __HAL_UNLOCK(hi2c);
04128
04129     /* Call the Slave Tx Complete callback */
04130     HAL_I2C_SlaveTxCpltCallback(hi2c);
04131   }
04132 }
04133
04134 /**
04135   * @brief  I2C Listen complete process.
04136   * @param  hi2c I2C handle.
04137   * @param  ITFlags Interrupt flags to handle.
04138   * @retval None
04139   */
04140 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
04141 {
04142   /* Reset handle parameters */
04143   hi2c->XferOptions = I2C_NO_OPTION_FRAME;
04144   hi2c->PreviousState = I2C_STATE_NONE;
04145   hi2c->State = HAL_I2C_STATE_READY;
04146   hi2c->Mode = HAL_I2C_MODE_NONE;
04147   hi2c->XferISR = NULL;
04148
04149   /* Store Last receive data if any */
04150   if (((ITFlags & I2C_FLAG_RXNE) != RESET))
04151   {
04152     /* Read data from RXDR */
04153     (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
04154
04155     if ((hi2c->XferSize > 0U))
04156     {
04157       hi2c->XferSize--;
04158       hi2c->XferCount--;
04159
04160       /* Set ErrorCode corresponding to a Non-Acknowledge */
04161       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04162     }
04163   }
04164
04165   /* Disable all Interrupts*/
04166   I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
04167
04168   /* Clear NACK Flag */
04169   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04170
04171   /* Process Unlocked */
04172   __HAL_UNLOCK(hi2c);
04173
04174   /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
04175   HAL_I2C_ListenCpltCallback(hi2c);
04176 }
04177
04178 /**
04179   * @brief  I2C interrupts error process.
04180   * @param  hi2c I2C handle.
04181   * @param  ErrorCode Error code to handle.
04182   * @retval None
04183   */
04184 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
04185 {
04186   /* Reset handle parameters */
04187   hi2c->Mode          = HAL_I2C_MODE_NONE;
04188   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
04189   hi2c->XferCount     = 0U;
04190
04191   /* Set new error code */
04192   hi2c->ErrorCode |= ErrorCode;
04193
04194   /* Disable Interrupts */
04195   if ((hi2c->State == HAL_I2C_STATE_LISTEN)         ||
04196       (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
04197       (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
04198   {
04199     /* Disable all interrupts, except interrupts related to LISTEN state */
04200     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
04201
04202     /* keep HAL_I2C_STATE_LISTEN if set */
04203     hi2c->State         = HAL_I2C_STATE_LISTEN;
04204     hi2c->PreviousState = I2C_STATE_NONE;
04205     hi2c->XferISR       = I2C_Slave_ISR_IT;
04206   }
04207   else
04208   {
04209     /* Disable all interrupts */
04210     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
04211
04212     /* If state is an abort treatment on goind, don't change state */
04213     /* This change will be do later */
04214     if (hi2c->State != HAL_I2C_STATE_ABORT)
04215     {
04216       /* Set HAL_I2C_STATE_READY */
04217       hi2c->State         = HAL_I2C_STATE_READY;
04218     }
04219     hi2c->PreviousState = I2C_STATE_NONE;
04220     hi2c->XferISR       = NULL;
04221   }
04222
04223   /* Abort DMA TX transfer if any */
04224   if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
04225   {
04226     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
04227
04228     /* Set the I2C DMA Abort callback :
04229        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04230     hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
04231
04232     /* Process Unlocked */
04233     __HAL_UNLOCK(hi2c);
04234
04235     /* Abort DMA TX */
04236     if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
04237     {
04238       /* Call Directly XferAbortCallback function in case of error */
04239       hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
04240     }
04241   }
04242   /* Abort DMA RX transfer if any */
04243   else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
04244   {
04245     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
04246
04247     /* Set the I2C DMA Abort callback :
04248        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04249     hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
04250
04251     /* Process Unlocked */
04252     __HAL_UNLOCK(hi2c);
04253
04254     /* Abort DMA RX */
04255     if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
04256     {
04257       /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
04258       hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
04259     }
04260   }
04261   else if (hi2c->State == HAL_I2C_STATE_ABORT)
04262   {
04263     hi2c->State = HAL_I2C_STATE_READY;
04264
04265     /* Process Unlocked */
04266     __HAL_UNLOCK(hi2c);
04267
04268     /* Call the corresponding callback to inform upper layer of End of Transfer */
04269     HAL_I2C_AbortCpltCallback(hi2c);
04270   }
04271   else
04272   {
04273     /* Process Unlocked */
04274     __HAL_UNLOCK(hi2c);
04275
04276     /* Call the corresponding callback to inform upper layer of End of Transfer */
04277     HAL_I2C_ErrorCallback(hi2c);
04278   }
04279 }
04280
04281 /**
04282   * @brief  I2C Tx data register flush process.
04283   * @param  hi2c I2C handle.
04284   * @retval None
04285   */
04286 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
04287 {
04288   /* If a pending TXIS flag is set */
04289   /* Write a dummy data in TXDR to clear it */
04290   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
04291   {
04292     hi2c->Instance->TXDR = 0x00U;
04293   }
04294
04295   /* Flush TX register if not empty */
04296   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
04297   {
04298     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
04299   }
04300 }
04301
04302 /**
04303   * @brief  DMA I2C master transmit process complete callback.
04304   * @param  hdma DMA handle
04305   * @retval None
04306   */
04307 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
04308 {
04309   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
04310
04311   /* Disable DMA Request */
04312   hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
04313
04314   /* If last transfer, enable STOP interrupt */
04315   if (hi2c->XferCount == 0U)
04316   {
04317     /* Enable STOP interrupt */
04318     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
04319   }
04320   /* else prepare a new DMA transfer and enable TCReload interrupt */
04321   else
04322   {
04323     /* Update Buffer pointer */
04324     hi2c->pBuffPtr += hi2c->XferSize;
04325
04326     /* Set the XferSize to transfer */
04327     if (hi2c->XferCount > MAX_NBYTE_SIZE)
04328     {
04329       hi2c->XferSize = MAX_NBYTE_SIZE;
04330     }
04331     else
04332     {
04333       hi2c->XferSize = hi2c->XferCount;
04334     }
04335
04336     /* Enable the DMA channel */
04337     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
04338
04339     /* Enable TC interrupts */
04340     I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
04341   }
04342 }
04343
04344 /**
04345   * @brief  DMA I2C slave transmit process complete callback.
04346   * @param  hdma DMA handle
04347   * @retval None
04348   */
04349 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
04350 {
04351   /* Prevent unused argument(s) compilation warning */
04352   UNUSED(hdma);
04353
04354   /* No specific action, Master fully manage the generation of STOP condition */
04355   /* Mean that this generation can arrive at any time, at the end or during DMA process */
04356   /* So STOP condition should be manage through Interrupt treatment */
04357 }
04358
04359 /**
04360   * @brief DMA I2C master receive process complete callback.
04361   * @param  hdma DMA handle
04362   * @retval None
04363   */
04364 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
04365 {
04366   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
04367
04368   /* Disable DMA Request */
04369   hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
04370
04371   /* If last transfer, enable STOP interrupt */
04372   if (hi2c->XferCount == 0U)
04373   {
04374     /* Enable STOP interrupt */
04375     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
04376   }
04377   /* else prepare a new DMA transfer and enable TCReload interrupt */
04378   else
04379   {
04380     /* Update Buffer pointer */
04381     hi2c->pBuffPtr += hi2c->XferSize;
04382
04383     /* Set the XferSize to transfer */
04384     if (hi2c->XferCount > MAX_NBYTE_SIZE)
04385     {
04386       hi2c->XferSize = MAX_NBYTE_SIZE;
04387     }
04388     else
04389     {
04390       hi2c->XferSize = hi2c->XferCount;
04391     }
04392
04393     /* Enable the DMA channel */
04394     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
04395
04396     /* Enable TC interrupts */
04397     I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
04398   }
04399 }
04400
04401 /**
04402   * @brief  DMA I2C slave receive process complete callback.
04403   * @param  hdma DMA handle
04404   * @retval None
04405   */
04406 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
04407 {
04408   /* Prevent unused argument(s) compilation warning */
04409   UNUSED(hdma);
04410
04411   /* No specific action, Master fully manage the generation of STOP condition */
04412   /* Mean that this generation can arrive at any time, at the end or during DMA process */
04413   /* So STOP condition should be manage through Interrupt treatment */
04414 }
04415
04416 /**
04417   * @brief  DMA I2C communication error callback.
04418   * @param hdma DMA handle
04419   * @retval None
04420   */
04421 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
04422 {
04423   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
04424
04425   /* Disable Acknowledge */
04426   hi2c->Instance->CR2 |= I2C_CR2_NACK;
04427
04428   /* Call the corresponding callback to inform upper layer of End of Transfer */
04429   I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
04430 }
04431
04432 /**
04433   * @brief DMA I2C communication abort callback
04434   *        (To be called at end of DMA Abort procedure).
04435   * @param hdma DMA handle.
04436   * @retval None
04437   */
04438 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
04439 {
04440   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
04441
04442   /* Disable Acknowledge */
04443   hi2c->Instance->CR2 |= I2C_CR2_NACK;
04444
04445   /* Reset AbortCpltCallback */
04446   hi2c->hdmatx->XferAbortCallback = NULL;
04447   hi2c->hdmarx->XferAbortCallback = NULL;
04448
04449   /* Check if come from abort from user */
04450   if (hi2c->State == HAL_I2C_STATE_ABORT)
04451   {
04452     hi2c->State = HAL_I2C_STATE_READY;
04453
04454     /* Call the corresponding callback to inform upper layer of End of Transfer */
04455     HAL_I2C_AbortCpltCallback(hi2c);
04456   }
04457   else
04458   {
04459     /* Call the corresponding callback to inform upper layer of End of Transfer */
04460     HAL_I2C_ErrorCallback(hi2c);
04461   }
04462 }
04463
04464 /**
04465   * @brief  This function handles I2C Communication Timeout.
04466   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04467   *                the configuration information for the specified I2C.
04468   * @param  Flag Specifies the I2C flag to check.
04469   * @param  Status The new Flag status (SET or RESET).
04470   * @param  Timeout Timeout duration
04471   * @param  Tickstart Tick start value
04472   * @retval HAL status
04473   */
04474 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
04475 {
04476   while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
04477   {
04478     /* Check for the Timeout */
04479     if (Timeout != HAL_MAX_DELAY)
04480     {
04481       if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
04482       {
04483         hi2c->State = HAL_I2C_STATE_READY;
04484         hi2c->Mode = HAL_I2C_MODE_NONE;
04485
04486         /* Process Unlocked */
04487         __HAL_UNLOCK(hi2c);
04488         return HAL_TIMEOUT;
04489       }
04490     }
04491   }
04492   return HAL_OK;
04493 }
04494
04495 /**
04496   * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
04497   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04498   *                the configuration information for the specified I2C.
04499   * @param  Timeout Timeout duration
04500   * @param  Tickstart Tick start value
04501   * @retval HAL status
04502   */
04503 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
04504 {
04505   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
04506   {
04507     /* Check if a NACK is detected */
04508     if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
04509     {
04510       return HAL_ERROR;
04511     }
04512
04513     /* Check for the Timeout */
04514     if (Timeout != HAL_MAX_DELAY)
04515     {
04516       if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
04517       {
04518         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04519         hi2c->State = HAL_I2C_STATE_READY;
04520         hi2c->Mode = HAL_I2C_MODE_NONE;
04521
04522         /* Process Unlocked */
04523         __HAL_UNLOCK(hi2c);
04524
04525         return HAL_TIMEOUT;
04526       }
04527     }
04528   }
04529   return HAL_OK;
04530 }
04531
04532 /**
04533   * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
04534   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04535   *                the configuration information for the specified I2C.
04536   * @param  Timeout Timeout duration
04537   * @param  Tickstart Tick start value
04538   * @retval HAL status
04539   */
04540 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
04541 {
04542   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
04543   {
04544     /* Check if a NACK is detected */
04545     if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
04546     {
04547       return HAL_ERROR;
04548     }
04549
04550     /* Check for the Timeout */
04551     if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
04552     {
04553       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04554       hi2c->State = HAL_I2C_STATE_READY;
04555       hi2c->Mode = HAL_I2C_MODE_NONE;
04556
04557       /* Process Unlocked */
04558       __HAL_UNLOCK(hi2c);
04559
04560       return HAL_TIMEOUT;
04561     }
04562   }
04563   return HAL_OK;
04564 }
04565
04566 /**
04567   * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
04568   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04569   *                the configuration information for the specified I2C.
04570   * @param  Timeout Timeout duration
04571   * @param  Tickstart Tick start value
04572   * @retval HAL status
04573   */
04574 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
04575 {
04576   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
04577   {
04578     /* Check if a NACK is detected */
04579     if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
04580     {
04581       return HAL_ERROR;
04582     }
04583
04584     /* Check if a STOPF is detected */
04585     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
04586     {
04587       /* Clear STOP Flag */
04588       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
04589
04590       /* Clear Configuration Register 2 */
04591       I2C_RESET_CR2(hi2c);
04592
04593       hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
04594       hi2c->State = HAL_I2C_STATE_READY;
04595       hi2c->Mode = HAL_I2C_MODE_NONE;
04596
04597       /* Process Unlocked */
04598       __HAL_UNLOCK(hi2c);
04599
04600       return HAL_ERROR;
04601     }
04602
04603     /* Check for the Timeout */
04604     if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
04605     {
04606       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04607       hi2c->State = HAL_I2C_STATE_READY;
04608
04609       /* Process Unlocked */
04610       __HAL_UNLOCK(hi2c);
04611
04612       return HAL_TIMEOUT;
04613     }
04614   }
04615   return HAL_OK;
04616 }
04617
04618 /**
04619   * @brief  This function handles Acknowledge failed detection during an I2C Communication.
04620   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04621   *                the configuration information for the specified I2C.
04622   * @param  Timeout Timeout duration
04623   * @param  Tickstart Tick start value
04624   * @retval HAL status
04625   */
04626 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
04627 {
04628   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
04629   {
04630     /* Wait until STOP Flag is reset */
04631     /* AutoEnd should be initiate after AF */
04632     while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
04633     {
04634       /* Check for the Timeout */
04635       if (Timeout != HAL_MAX_DELAY)
04636       {
04637         if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
04638         {
04639           hi2c->State = HAL_I2C_STATE_READY;
04640           hi2c->Mode = HAL_I2C_MODE_NONE;
04641
04642           /* Process Unlocked */
04643           __HAL_UNLOCK(hi2c);
04644           return HAL_TIMEOUT;
04645         }
04646       }
04647     }
04648
04649     /* Clear NACKF Flag */
04650     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04651
04652     /* Clear STOP Flag */
04653     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
04654
04655     /* Flush TX register */
04656     I2C_Flush_TXDR(hi2c);
04657
04658     /* Clear Configuration Register 2 */
04659     I2C_RESET_CR2(hi2c);
04660
04661     hi2c->ErrorCode = HAL_I2C_ERROR_AF;
04662     hi2c->State = HAL_I2C_STATE_READY;
04663     hi2c->Mode = HAL_I2C_MODE_NONE;
04664
04665     /* Process Unlocked */
04666     __HAL_UNLOCK(hi2c);
04667
04668     return HAL_ERROR;
04669   }
04670   return HAL_OK;
04671 }
04672
04673 /**
04674   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
04675   * @param  hi2c I2C handle.
04676   * @param  DevAddress Specifies the slave address to be programmed.
04677   * @param  Size Specifies the number of bytes to be programmed.
04678   *   This parameter must be a value between 0 and 255.
04679   * @param  Mode New state of the I2C START condition generation.
04680   *   This parameter can be one of the following values:
04681   *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
04682   *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
04683   *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
04684   * @param  Request New state of the I2C START condition generation.
04685   *   This parameter can be one of the following values:
04686   *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
04687   *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
04688   *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
04689   *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
04690   * @retval None
04691   */
04692 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
04693 {
04694   uint32_t tmpreg = 0U;
04695
04696   /* Check the parameters */
04697   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
04698   assert_param(IS_TRANSFER_MODE(Mode));
04699   assert_param(IS_TRANSFER_REQUEST(Request));
04700
04701   /* Get the CR2 register value */
04702   tmpreg = hi2c->Instance->CR2;
04703
04704   /* clear tmpreg specific bits */
04705   tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
04706
04707   /* update tmpreg */
04708   tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16) & I2C_CR2_NBYTES) | \
04709                        (uint32_t)Mode | (uint32_t)Request);
04710
04711   /* update CR2 register */
04712   hi2c->Instance->CR2 = tmpreg;
04713 }
04714
04715 /**
04716   * @brief  Manage the enabling of Interrupts.
04717   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04718   *                the configuration information for the specified I2C.
04719   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
04720   * @retval HAL status
04721   */
04722 static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
04723 {
04724   uint32_t tmpisr = 0U;
04725
04726   if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
04727       (hi2c->XferISR == I2C_Slave_ISR_DMA))
04728   {
04729     if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
04730     {
04731       /* Enable ERR, STOP, NACK and ADDR interrupts */
04732       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04733     }
04734
04735     if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
04736     {
04737       /* Enable ERR and NACK interrupts */
04738       tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
04739     }
04740
04741     if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
04742     {
04743       /* Enable STOP interrupts */
04744       tmpisr |= I2C_IT_STOPI;
04745     }
04746
04747     if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
04748     {
04749       /* Enable TC interrupts */
04750       tmpisr |= I2C_IT_TCI;
04751     }
04752   }
04753   else
04754   {
04755     if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
04756     {
04757       /* Enable ERR, STOP, NACK, and ADDR interrupts */
04758       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04759     }
04760
04761     if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
04762     {
04763       /* Enable ERR, TC, STOP, NACK and RXI interrupts */
04764       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
04765     }
04766
04767     if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
04768     {
04769       /* Enable ERR, TC, STOP, NACK and TXI interrupts */
04770       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
04771     }
04772
04773     if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
04774     {
04775       /* Enable STOP interrupts */
04776       tmpisr |= I2C_IT_STOPI;
04777     }
04778   }
04779
04780   /* Enable interrupts only at the end */
04781   /* to avoid the risk of I2C interrupt handle execution before */
04782   /* all interrupts requested done */
04783   __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
04784
04785   return HAL_OK;
04786 }
04787
04788 /**
04789   * @brief  Manage the disabling of Interrupts.
04790   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04791   *                the configuration information for the specified I2C.
04792   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
04793   * @retval HAL status
04794   */
04795 static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
04796 {
04797   uint32_t tmpisr = 0U;
04798
04799   if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
04800   {
04801     /* Disable TC and TXI interrupts */
04802     tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
04803
04804     if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
04805     {
04806       /* Disable NACK and STOP interrupts */
04807       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04808     }
04809   }
04810
04811   if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
04812   {
04813     /* Disable TC and RXI interrupts */
04814     tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
04815
04816     if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
04817     {
04818       /* Disable NACK and STOP interrupts */
04819       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04820     }
04821   }
04822
04823   if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
04824   {
04825     /* Disable ADDR, NACK and STOP interrupts */
04826     tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04827   }
04828
04829   if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
04830   {
04831     /* Enable ERR and NACK interrupts */
04832     tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
04833   }
04834
04835   if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
04836   {
04837     /* Enable STOP interrupts */
04838     tmpisr |= I2C_IT_STOPI;
04839   }
04840
04841   if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
04842   {
04843     /* Enable TC interrupts */
04844     tmpisr |= I2C_IT_TCI;
04845   }
04846
04847   /* Disable interrupts only at the end */
04848   /* to avoid a breaking situation like at "t" time */
04849   /* all disable interrupts request are not done */
04850   __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
04851
04852   return HAL_OK;
04853 }
04854
04855 /**
04856   * @}
04857   */
04858
04859 #endif /* HAL_I2C_MODULE_ENABLED */
04860 /**
04861   * @}
04862   */
04863
04864 /**
04865   * @}
04866   */
04867
04868 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_i2c.h Source File

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stm32f3xx_hal_i2c.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_i2c.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2C HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_I2C_H
00038 #define __STM32F3xx_HAL_I2C_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup I2C
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /** @defgroup I2C_Exported_Types I2C Exported Types
00057   * @{
00058   */
00059
00060 /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
00061   * @brief  I2C Configuration Structure definition
00062   * @{
00063   */
00064 typedef struct
00065 {
00066   uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
00067                                   This parameter calculated by referring to I2C initialization
00068                                          section in Reference manual */
00069
00070   uint32_t OwnAddress1;         /*!< Specifies the first device own address.
00071                                   This parameter can be a 7-bit or 10-bit address. */
00072
00073   uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
00074                                   This parameter can be a value of @ref I2C_ADDRESSING_MODE */
00075
00076   uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
00077                                   This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
00078
00079   uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
00080                                   This parameter can be a 7-bit address. */
00081
00082   uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
00083                                   This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
00084
00085   uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
00086                                   This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
00087
00088   uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
00089                                   This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
00090
00091 } I2C_InitTypeDef;
00092
00093 /**
00094   * @}
00095   */
00096
00097 /** @defgroup HAL_state_structure_definition HAL state structure definition
00098   * @brief  HAL State structure definition
00099   * @note  HAL I2C State value coding follow below described bitmap :\n
00100   *          b7-b6  Error information\n
00101   *             00 : No Error\n
00102   *             01 : Abort (Abort user request on going)\n
00103   *             10 : Timeout\n
00104   *             11 : Error\n
00105   *          b5     IP initilisation status\n
00106   *             0  : Reset (IP not initialized)\n
00107   *             1  : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
00108   *          b4     (not used)\n
00109   *             x  : Should be set to 0\n
00110   *          b3\n
00111   *             0  : Ready or Busy (No Listen mode ongoing)\n
00112   *             1  : Listen (IP in Address Listen Mode)\n
00113   *          b2     Intrinsic process state\n
00114   *             0  : Ready\n
00115   *             1  : Busy (IP busy with some configuration or internal operations)\n
00116   *          b1     Rx state\n
00117   *             0  : Ready (no Rx operation ongoing)\n
00118   *             1  : Busy (Rx operation ongoing)\n
00119   *          b0     Tx state\n
00120   *             0  : Ready (no Tx operation ongoing)\n
00121   *             1  : Busy (Tx operation ongoing)
00122   * @{
00123   */
00124 typedef enum
00125 {
00126   HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
00127   HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
00128   HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
00129   HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
00130   HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
00131   HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
00132   HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
00133                                                  process is ongoing                         */
00134   HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
00135                                                  process is ongoing                         */
00136   HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
00137   HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
00138   HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
00139
00140 } HAL_I2C_StateTypeDef;
00141
00142 /**
00143   * @}
00144   */
00145
00146 /** @defgroup HAL_mode_structure_definition HAL mode structure definition
00147   * @brief  HAL Mode structure definition
00148   * @note  HAL I2C Mode value coding follow below described bitmap :\n
00149   *          b7     (not used)\n
00150   *             x  : Should be set to 0\n
00151   *          b6\n
00152   *             0  : None\n
00153   *             1  : Memory (HAL I2C communication is in Memory Mode)\n
00154   *          b5\n
00155   *             0  : None\n
00156   *             1  : Slave (HAL I2C communication is in Slave Mode)\n
00157   *          b4\n
00158   *             0  : None\n
00159   *             1  : Master (HAL I2C communication is in Master Mode)\n
00160   *          b3-b2-b1-b0  (not used)\n
00161   *             xxxx : Should be set to 0000
00162   * @{
00163   */
00164 typedef enum
00165 {
00166   HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
00167   HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
00168   HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
00169   HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
00170
00171 } HAL_I2C_ModeTypeDef;
00172
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup I2C_Error_Code_definition I2C Error Code definition
00178   * @brief  I2C Error Code definition
00179   * @{
00180   */
00181 #define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
00182 #define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
00183 #define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
00184 #define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
00185 #define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
00186 #define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
00187 #define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
00188 #define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
00189 /**
00190   * @}
00191   */
00192
00193 /** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
00194   * @brief  I2C handle Structure definition
00195   * @{
00196   */
00197 typedef struct __I2C_HandleTypeDef
00198 {
00199   I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
00200
00201   I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
00202
00203   uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
00204
00205   uint16_t                   XferSize;       /*!< I2C transfer size                         */
00206
00207   __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
00208
00209   __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
00210                                                   be a value of @ref I2C_XFEROPTIONS */
00211
00212   __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
00213
00214   HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);  /*!< I2C transfer IRQ handler function pointer */
00215
00216   DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
00217
00218   DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
00219
00220   HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
00221
00222   __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
00223
00224   __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
00225
00226   __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
00227
00228   __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
00229 } I2C_HandleTypeDef;
00230 /**
00231   * @}
00232   */
00233
00234 /**
00235   * @}
00236   */
00237 /* Exported constants --------------------------------------------------------*/
00238
00239 /** @defgroup I2C_Exported_Constants I2C Exported Constants
00240   * @{
00241   */
00242
00243 /** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
00244   * @{
00245   */
00246 #define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
00247 #define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
00248 #define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
00249 #define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
00250 #define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
00256   * @{
00257   */
00258 #define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
00259 #define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
00265   * @{
00266   */
00267 #define I2C_DUALADDRESS_DISABLE         (0x00000000U)
00268 #define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
00274   * @{
00275   */
00276 #define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
00277 #define I2C_OA2_MASK01                  ((uint8_t)0x01U)
00278 #define I2C_OA2_MASK02                  ((uint8_t)0x02U)
00279 #define I2C_OA2_MASK03                  ((uint8_t)0x03U)
00280 #define I2C_OA2_MASK04                  ((uint8_t)0x04U)
00281 #define I2C_OA2_MASK05                  ((uint8_t)0x05U)
00282 #define I2C_OA2_MASK06                  ((uint8_t)0x06U)
00283 #define I2C_OA2_MASK07                  ((uint8_t)0x07U)
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
00289   * @{
00290   */
00291 #define I2C_GENERALCALL_DISABLE         (0x00000000U)
00292 #define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
00298   * @{
00299   */
00300 #define I2C_NOSTRETCH_DISABLE           (0x00000000U)
00301 #define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
00307   * @{
00308   */
00309 #define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
00310 #define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
00316   * @{
00317   */
00318 #define I2C_DIRECTION_TRANSMIT          (0x00000000U)
00319 #define I2C_DIRECTION_RECEIVE           (0x00000001U)
00320 /**
00321   * @}
00322   */
00323
00324 /** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
00325   * @{
00326   */
00327 #define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
00328 #define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
00329 #define  I2C_SOFTEND_MODE               (0x00000000U)
00330 /**
00331   * @}
00332   */
00333
00334 /** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
00335   * @{
00336   */
00337 #define  I2C_NO_STARTSTOP               (0x00000000U)
00338 #define  I2C_GENERATE_STOP              I2C_CR2_STOP
00339 #define  I2C_GENERATE_START_READ        (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
00340 #define  I2C_GENERATE_START_WRITE       I2C_CR2_START
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
00346   * @brief I2C Interrupt definition
00347   *        Elements values convention: 0xXXXXXXXX
00348   *           - XXXXXXXX  : Interrupt control mask
00349   * @{
00350   */
00351 #define I2C_IT_ERRI                     I2C_CR1_ERRIE
00352 #define I2C_IT_TCI                      I2C_CR1_TCIE
00353 #define I2C_IT_STOPI                    I2C_CR1_STOPIE
00354 #define I2C_IT_NACKI                    I2C_CR1_NACKIE
00355 #define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
00356 #define I2C_IT_RXI                      I2C_CR1_RXIE
00357 #define I2C_IT_TXI                      I2C_CR1_TXIE
00358 /**
00359   * @}
00360   */
00361
00362 /** @defgroup I2C_Flag_definition I2C Flag definition
00363   * @{
00364   */
00365 #define I2C_FLAG_TXE                    I2C_ISR_TXE
00366 #define I2C_FLAG_TXIS                   I2C_ISR_TXIS
00367 #define I2C_FLAG_RXNE                   I2C_ISR_RXNE
00368 #define I2C_FLAG_ADDR                   I2C_ISR_ADDR
00369 #define I2C_FLAG_AF                     I2C_ISR_NACKF
00370 #define I2C_FLAG_STOPF                  I2C_ISR_STOPF
00371 #define I2C_FLAG_TC                     I2C_ISR_TC
00372 #define I2C_FLAG_TCR                    I2C_ISR_TCR
00373 #define I2C_FLAG_BERR                   I2C_ISR_BERR
00374 #define I2C_FLAG_ARLO                   I2C_ISR_ARLO
00375 #define I2C_FLAG_OVR                    I2C_ISR_OVR
00376 #define I2C_FLAG_PECERR                 I2C_ISR_PECERR
00377 #define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
00378 #define I2C_FLAG_ALERT                  I2C_ISR_ALERT
00379 #define I2C_FLAG_BUSY                   I2C_ISR_BUSY
00380 #define I2C_FLAG_DIR                    I2C_ISR_DIR
00381 /**
00382   * @}
00383   */
00384
00385 /**
00386   * @}
00387   */
00388
00389 /* Exported macros -----------------------------------------------------------*/
00390
00391 /** @defgroup I2C_Exported_Macros I2C Exported Macros
00392   * @{
00393   */
00394
00395 /** @brief Reset I2C handle state.
00396   * @param  __HANDLE__ specifies the I2C Handle.
00397   * @retval None
00398   */
00399 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
00400
00401 /** @brief  Enable the specified I2C interrupt.
00402   * @param  __HANDLE__ specifies the I2C Handle.
00403   * @param  __INTERRUPT__ specifies the interrupt source to enable.
00404   *        This parameter can be one of the following values:
00405   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00406   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00407   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00408   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00409   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00410   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00411   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00412   *
00413   * @retval None
00414   */
00415 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
00416
00417 /** @brief  Disable the specified I2C interrupt.
00418   * @param  __HANDLE__ specifies the I2C Handle.
00419   * @param  __INTERRUPT__ specifies the interrupt source to disable.
00420   *        This parameter can be one of the following values:
00421   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00422   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00423   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00424   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00425   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00426   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00427   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00428   *
00429   * @retval None
00430   */
00431 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
00432
00433 /** @brief  Check whether the specified I2C interrupt source is enabled or not.
00434   * @param  __HANDLE__ specifies the I2C Handle.
00435   * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
00436   *          This parameter can be one of the following values:
00437   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00438   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00439   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00440   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00441   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00442   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00443   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00444   *
00445   * @retval The new state of __INTERRUPT__ (SET or RESET).
00446   */
00447 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00448
00449 /** @brief  Check whether the specified I2C flag is set or not.
00450   * @param  __HANDLE__ specifies the I2C Handle.
00451   * @param  __FLAG__ specifies the flag to check.
00452   *        This parameter can be one of the following values:
00453   *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
00454   *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
00455   *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
00456   *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
00457   *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
00458   *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
00459   *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
00460   *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
00461   *            @arg @ref I2C_FLAG_BERR    Bus error
00462   *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
00463   *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
00464   *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
00465   *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
00466   *            @arg @ref I2C_FLAG_ALERT   SMBus alert
00467   *            @arg @ref I2C_FLAG_BUSY    Bus busy
00468   *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
00469   *
00470   * @retval The new state of __FLAG__ (SET or RESET).
00471   */
00472 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
00473
00474 /** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
00475   * @param  __HANDLE__ specifies the I2C Handle.
00476   * @param  __FLAG__ specifies the flag to clear.
00477   *          This parameter can be any combination of the following values:
00478   *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
00479   *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
00480   *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
00481   *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
00482   *            @arg @ref I2C_FLAG_BERR    Bus error
00483   *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
00484   *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
00485   *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
00486   *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
00487   *            @arg @ref I2C_FLAG_ALERT   SMBus alert
00488   *
00489   * @retval None
00490   */
00491 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
00492                                                                                  : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
00493
00494 /** @brief  Enable the specified I2C peripheral.
00495   * @param  __HANDLE__ specifies the I2C Handle.
00496   * @retval None
00497   */
00498 #define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))
00499
00500 /** @brief  Disable the specified I2C peripheral.
00501   * @param  __HANDLE__ specifies the I2C Handle.
00502   * @retval None
00503   */
00504 #define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00505
00506 /** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
00507   * @param  __HANDLE__ specifies the I2C Handle.
00508   * @retval None
00509   */
00510 #define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
00511 /**
00512   * @}
00513   */
00514
00515 /* Include I2C HAL Extended module */
00516 #include "stm32f3xx_hal_i2c_ex.h"
00517
00518 /* Exported functions --------------------------------------------------------*/
00519 /** @addtogroup I2C_Exported_Functions
00520   * @{
00521   */
00522
00523 /** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00524   * @{
00525   */
00526 /* Initialization and de-initialization functions******************************/
00527 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
00528 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
00529 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
00530 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
00531 /**
00532   * @}
00533   */
00534
00535 /** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
00536   * @{
00537   */
00538 /* IO operation functions  ****************************************************/
00539 /******* Blocking mode: Polling */
00540 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00541 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00542 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00543 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00544 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00545 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00546 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
00547
00548 /******* Non-Blocking mode: Interrupt */
00549 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00550 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00551 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00552 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00553 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00554 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00555
00556 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00557 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00558 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00559 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00560 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
00561 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
00562 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
00563
00564 /******* Non-Blocking mode: DMA */
00565 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00566 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00567 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00568 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00569 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00570 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00571 /**
00572   * @}
00573   */
00574
00575 /** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00576  * @{
00577  */
00578 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00579 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
00580 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
00581 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
00582 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
00583 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
00584 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
00585 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
00586 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
00587 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
00588 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
00589 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
00590 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
00591 /**
00592   * @}
00593   */
00594
00595 /** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
00596   * @{
00597   */
00598 /* Peripheral State, Mode and Error functions  *********************************/
00599 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
00600 HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
00601 uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
00602
00603 /**
00604   * @}
00605   */
00606
00607 /**
00608   * @}
00609   */
00610
00611 /* Private constants ---------------------------------------------------------*/
00612 /** @defgroup I2C_Private_Constants I2C Private Constants
00613   * @{
00614   */
00615
00616 /**
00617   * @}
00618   */
00619
00620 /* Private macros ------------------------------------------------------------*/
00621 /** @defgroup I2C_Private_Macro I2C Private Macros
00622   * @{
00623   */
00624
00625 #define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
00626                                          ((MODE) == I2C_ADDRESSINGMODE_10BIT))
00627
00628 #define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
00629                                          ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
00630
00631 #define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
00632                                          ((MASK) == I2C_OA2_MASK01) || \
00633                                          ((MASK) == I2C_OA2_MASK02) || \
00634                                          ((MASK) == I2C_OA2_MASK03) || \
00635                                          ((MASK) == I2C_OA2_MASK04) || \
00636                                          ((MASK) == I2C_OA2_MASK05) || \
00637                                          ((MASK) == I2C_OA2_MASK06) || \
00638                                          ((MASK) == I2C_OA2_MASK07))
00639
00640 #define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
00641                                          ((CALL) == I2C_GENERALCALL_ENABLE))
00642
00643 #define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
00644                                          ((STRETCH) == I2C_NOSTRETCH_ENABLE))
00645
00646 #define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
00647                                          ((SIZE) == I2C_MEMADD_SIZE_16BIT))
00648
00649 #define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
00650                                          ((MODE) == I2C_AUTOEND_MODE) || \
00651                                          ((MODE) == I2C_SOFTEND_MODE))
00652
00653 #define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
00654                                          ((REQUEST) == I2C_GENERATE_START_READ)  || \
00655                                          ((REQUEST) == I2C_GENERATE_START_WRITE) || \
00656                                          ((REQUEST) == I2C_NO_STARTSTOP))
00657
00658 #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
00659                                                    ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
00660                                                    ((REQUEST) == I2C_NEXT_FRAME)           || \
00661                                                    ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
00662                                                    ((REQUEST) == I2C_LAST_FRAME))
00663
00664 #define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
00665
00666 #define I2C_GET_ADDR_MATCH(__HANDLE__)            (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
00667 #define I2C_GET_DIR(__HANDLE__)                   (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
00668 #define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
00669 #define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
00670 #define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
00671
00672 #define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
00673 #define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
00674
00675 #define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
00676 #define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
00677
00678 #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
00679                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
00680 /**
00681   * @}
00682   */
00683
00684 /* Private Functions ---------------------------------------------------------*/
00685 /** @defgroup I2C_Private_Functions I2C Private Functions
00686   * @{
00687   */
00688 /* Private functions are defined in stm32f3xx_hal_i2c.c file */
00689 /**
00690   * @}
00691   */
00692
00693 /**
00694   * @}
00695   */
00696
00697 /**
00698   * @}
00699   */
00700
00701 #ifdef __cplusplus
00702 }
00703 #endif
00704
00705
00706 #endif /* __STM32F3xx_HAL_I2C_H */
00707
00708 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_i2c_ex.c Source File

  • File List
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  • Firmware
  • Drivers
  • STM32F3xx_HAL_Driver
  • Src
stm32f3xx_hal_i2c_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_i2c_ex.c
00004   * @author  MCD Application Team
00005   * @brief   I2C Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of I2C Extended peripheral:
00008   *           + Extended features functions
00009   *
00010   @verbatim
00011   ==============================================================================
00012                ##### I2C peripheral Extended features  #####
00013   ==============================================================================
00014
00015   [..] Comparing to other previous devices, the I2C interface for STM32F3xx
00016        devices contains the following additional features
00017
00018        (+) Possibility to disable or enable Analog Noise Filter
00019        (+) Use of a configured Digital Noise Filter
00020        (+) Disable or enable wakeup from Stop mode
00021
00022                      ##### How to use this driver #####
00023   ==============================================================================
00024   [..] This driver provides functions to configure Noise Filter and Wake Up Feature
00025     (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
00026     (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
00027     (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
00028           (++) HAL_I2CEx_EnableWakeUp()
00029           (++) HAL_I2CEx_DisableWakeUp()
00030     (#) Configure the enable or disable of fast mode plus driving capability using the functions :
00031           (++) HAL_I2CEx_EnableFastModePlus()
00032           (++) HAL_I2CEx_DisableFastModePlus()
00033   @endverbatim
00034   ******************************************************************************
00035   * @attention
00036   *
00037   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00038   *
00039   * Redistribution and use in source and binary forms, with or without modification,
00040   * are permitted provided that the following conditions are met:
00041   *   1. Redistributions of source code must retain the above copyright notice,
00042   *      this list of conditions and the following disclaimer.
00043   *   2. Redistributions in binary form must reproduce the above copyright notice,
00044   *      this list of conditions and the following disclaimer in the documentation
00045   *      and/or other materials provided with the distribution.
00046   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00047   *      may be used to endorse or promote products derived from this software
00048   *      without specific prior written permission.
00049   *
00050   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00051   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00052   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00053   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00054   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00055   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00056   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00057   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00058   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00059   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00060   *
00061   ******************************************************************************
00062   */
00063
00064 /* Includes ------------------------------------------------------------------*/
00065 #include "stm32f3xx_hal.h"
00066
00067 /** @addtogroup STM32F3xx_HAL_Driver
00068   * @{
00069   */
00070
00071 /** @defgroup I2CEx I2CEx
00072   * @brief I2C Extended HAL module driver
00073   * @{
00074   */
00075
00076 #ifdef HAL_I2C_MODULE_ENABLED
00077
00078 /* Private typedef -----------------------------------------------------------*/
00079 /* Private define ------------------------------------------------------------*/
00080 /* Private macro -------------------------------------------------------------*/
00081 /* Private variables ---------------------------------------------------------*/
00082 /* Private function prototypes -----------------------------------------------*/
00083 /* Private functions ---------------------------------------------------------*/
00084
00085 /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
00086   * @{
00087   */
00088
00089 /** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
00090   * @brief    Extended features functions
00091  *
00092 @verbatim
00093  ===============================================================================
00094                       ##### Extended features functions #####
00095  ===============================================================================
00096     [..] This section provides functions allowing to:
00097       (+) Configure Noise Filters
00098       (+) Configure Wake Up Feature
00099
00100 @endverbatim
00101   * @{
00102   */
00103
00104 /**
00105   * @brief  Configure I2C Analog noise filter.
00106   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00107   *                the configuration information for the specified I2Cx peripheral.
00108   * @param  AnalogFilter New state of the Analog filter.
00109   * @retval HAL status
00110   */
00111 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
00112 {
00113   /* Check the parameters */
00114   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00115   assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
00116
00117   if (hi2c->State == HAL_I2C_STATE_READY)
00118   {
00119     /* Process Locked */
00120     __HAL_LOCK(hi2c);
00121
00122     hi2c->State = HAL_I2C_STATE_BUSY;
00123
00124     /* Disable the selected I2C peripheral */
00125     __HAL_I2C_DISABLE(hi2c);
00126
00127     /* Reset I2Cx ANOFF bit */
00128     hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
00129
00130     /* Set analog filter bit*/
00131     hi2c->Instance->CR1 |= AnalogFilter;
00132
00133     __HAL_I2C_ENABLE(hi2c);
00134
00135     hi2c->State = HAL_I2C_STATE_READY;
00136
00137     /* Process Unlocked */
00138     __HAL_UNLOCK(hi2c);
00139
00140     return HAL_OK;
00141   }
00142   else
00143   {
00144     return HAL_BUSY;
00145   }
00146 }
00147
00148 /**
00149   * @brief  Configure I2C Digital noise filter.
00150   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00151   *                the configuration information for the specified I2Cx peripheral.
00152   * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
00153   * @retval HAL status
00154   */
00155 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
00156 {
00157   uint32_t tmpreg = 0U;
00158
00159   /* Check the parameters */
00160   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00161   assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
00162
00163   if (hi2c->State == HAL_I2C_STATE_READY)
00164   {
00165     /* Process Locked */
00166     __HAL_LOCK(hi2c);
00167
00168     hi2c->State = HAL_I2C_STATE_BUSY;
00169
00170     /* Disable the selected I2C peripheral */
00171     __HAL_I2C_DISABLE(hi2c);
00172
00173     /* Get the old register value */
00174     tmpreg = hi2c->Instance->CR1;
00175
00176     /* Reset I2Cx DNF bits [11:8] */
00177     tmpreg &= ~(I2C_CR1_DNF);
00178
00179     /* Set I2Cx DNF coefficient */
00180     tmpreg |= DigitalFilter << 8U;
00181
00182     /* Store the new register value */
00183     hi2c->Instance->CR1 = tmpreg;
00184
00185     __HAL_I2C_ENABLE(hi2c);
00186
00187     hi2c->State = HAL_I2C_STATE_READY;
00188
00189     /* Process Unlocked */
00190     __HAL_UNLOCK(hi2c);
00191
00192     return HAL_OK;
00193   }
00194   else
00195   {
00196     return HAL_BUSY;
00197   }
00198 }
00199
00200 /**
00201   * @brief  Enable I2C wakeup from stop mode.
00202   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00203   *                the configuration information for the specified I2Cx peripheral.
00204   * @retval HAL status
00205   */
00206 HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
00207 {
00208   /* Check the parameters */
00209   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
00210
00211   if (hi2c->State == HAL_I2C_STATE_READY)
00212   {
00213     /* Process Locked */
00214     __HAL_LOCK(hi2c);
00215
00216     hi2c->State = HAL_I2C_STATE_BUSY;
00217
00218     /* Disable the selected I2C peripheral */
00219     __HAL_I2C_DISABLE(hi2c);
00220
00221     /* Enable wakeup from stop mode */
00222     hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
00223
00224     __HAL_I2C_ENABLE(hi2c);
00225
00226     hi2c->State = HAL_I2C_STATE_READY;
00227
00228     /* Process Unlocked */
00229     __HAL_UNLOCK(hi2c);
00230
00231     return HAL_OK;
00232   }
00233   else
00234   {
00235     return HAL_BUSY;
00236   }
00237 }
00238
00239 /**
00240   * @brief  Disable I2C wakeup from stop mode.
00241   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00242   *                the configuration information for the specified I2Cx peripheral.
00243   * @retval HAL status
00244   */
00245 HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
00246 {
00247   /* Check the parameters */
00248   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
00249
00250   if (hi2c->State == HAL_I2C_STATE_READY)
00251   {
00252     /* Process Locked */
00253     __HAL_LOCK(hi2c);
00254
00255     hi2c->State = HAL_I2C_STATE_BUSY;
00256
00257     /* Disable the selected I2C peripheral */
00258     __HAL_I2C_DISABLE(hi2c);
00259
00260     /* Enable wakeup from stop mode */
00261     hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
00262
00263     __HAL_I2C_ENABLE(hi2c);
00264
00265     hi2c->State = HAL_I2C_STATE_READY;
00266
00267     /* Process Unlocked */
00268     __HAL_UNLOCK(hi2c);
00269
00270     return HAL_OK;
00271   }
00272   else
00273   {
00274     return HAL_BUSY;
00275   }
00276 }
00277
00278 /**
00279   * @brief Enable the I2C fast mode plus driving capability.
00280   * @param ConfigFastModePlus Selects the pin.
00281   *   This parameter can be one of the @ref I2CEx_FastModePlus values
00282   * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
00283   *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
00284   *        on each one of the following pins PB6, PB7, PB8 and PB9.
00285   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
00286   *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
00287   * @note  For all I2C2 pins fast mode plus driving capability can be enabled
00288   *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
00289   * @note  For all I2C3 pins fast mode plus driving capability can be enabled
00290   *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
00291   * @retval None
00292   */
00293 void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
00294 {
00295   /* Check the parameter */
00296   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
00297
00298   /* Enable SYSCFG clock */
00299   __HAL_RCC_SYSCFG_CLK_ENABLE();
00300
00301   /* Enable fast mode plus driving capability for selected pin */
00302   SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
00303 }
00304
00305 /**
00306   * @brief Disable the I2C fast mode plus driving capability.
00307   * @param ConfigFastModePlus Selects the pin.
00308   *   This parameter can be one of the @ref I2CEx_FastModePlus values
00309   * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
00310   *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
00311   *        on each one of the following pins PB6, PB7, PB8 and PB9.
00312   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
00313   *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
00314   * @note  For all I2C2 pins fast mode plus driving capability can be disabled
00315   *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
00316   * @note  For all I2C3 pins fast mode plus driving capability can be disabled
00317   *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
00318   * @retval None
00319   */
00320 void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
00321 {
00322   /* Check the parameter */
00323   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
00324
00325   /* Enable SYSCFG clock */
00326   __HAL_RCC_SYSCFG_CLK_ENABLE();
00327
00328   /* Disable fast mode plus driving capability for selected pin */
00329   CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
00330 }
00331
00332 /**
00333   * @}
00334   */
00335
00336 /**
00337   * @}
00338   */
00339
00340 #endif /* HAL_I2C_MODULE_ENABLED */
00341 /**
00342   * @}
00343   */
00344
00345 /**
00346   * @}
00347   */
00348
00349 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_i2c_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32F3xx_HAL_Driver
  • Inc
stm32f3xx_hal_i2c_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_i2c_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2C HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_I2C_EX_H
00038 #define __STM32F3xx_HAL_I2C_EX_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup I2CEx
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /* Exported constants --------------------------------------------------------*/
00057
00058 /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
00059   * @{
00060   */
00061
00062 /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
00063   * @{
00064   */
00065 #define I2C_ANALOGFILTER_ENABLE         0x00000000U
00066 #define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
00067 /**
00068   * @}
00069   */
00070
00071 /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
00072   * @{
00073   */
00074 #define I2C_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */
00075 #define I2C_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
00076 #define I2C_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
00077 #define I2C_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
00078 #define I2C_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
00079 #define I2C_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
00080 #if defined(SYSCFG_CFGR1_I2C2_FMP)
00081 #define I2C_FASTMODEPLUS_I2C2           SYSCFG_CFGR1_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
00082 #else
00083 #define I2C_FASTMODEPLUS_I2C2           (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported  */
00084 #endif
00085 #if defined(SYSCFG_CFGR1_I2C3_FMP)
00086 #define I2C_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
00087 #else
00088 #define I2C_FASTMODEPLUS_I2C3           (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported  */
00089 #endif
00090 /**
00091   * @}
00092   */
00093
00094 /**
00095   * @}
00096   */
00097
00098 /* Exported macro ------------------------------------------------------------*/
00099 /* Exported functions --------------------------------------------------------*/
00100
00101 /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
00102   * @{
00103   */
00104
00105 /** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
00106   * @brief    Extended features functions
00107   * @{
00108   */
00109
00110 /* Peripheral Control functions  ************************************************/
00111 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
00112 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
00113 HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
00114 HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
00115 void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
00116 void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
00117
00118 /* Private constants ---------------------------------------------------------*/
00119 /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
00120   * @{
00121   */
00122
00123 /**
00124   * @}
00125   */
00126
00127 /* Private macros ------------------------------------------------------------*/
00128 /** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
00129   * @{
00130   */
00131 #define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
00132                                           ((FILTER) == I2C_ANALOGFILTER_DISABLE))
00133
00134 #define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
00135
00136 #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
00137                                          ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6))  == I2C_FASTMODEPLUS_PB6)     || \
00138                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7))  == I2C_FASTMODEPLUS_PB7)     || \
00139                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8))  == I2C_FASTMODEPLUS_PB8)     || \
00140                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9))  == I2C_FASTMODEPLUS_PB9)     || \
00141                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)    || \
00142                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)    || \
00143                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)))
00144 /**
00145   * @}
00146   */
00147
00148 /* Private Functions ---------------------------------------------------------*/
00149 /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
00150   * @{
00151   */
00152 /* Private functions are defined in stm32f3xx_hal_i2c_ex.c file */
00153 /**
00154   * @}
00155   */
00156
00157 /**
00158   * @}
00159   */
00160
00161 /**
00162   * @}
00163   */
00164
00165 /**
00166   * @}
00167   */
00168
00169 /**
00170   * @}
00171   */
00172
00173 #ifdef __cplusplus
00174 }
00175 #endif
00176
00177 #endif /* __STM32F3xx_HAL_I2C_EX_H */
00178
00179 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_i2s.c Source File

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stm32f3xx_hal_i2s.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_i2s.c
00004   * @author  MCD Application Team
00005   * @brief   I2S HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral State and Errors functions
00011   @verbatim
00012  ===============================================================================
00013                   ##### How to use this driver #####
00014  ===============================================================================
00015  [..]
00016     The I2S HAL driver can be used as follows:
00017
00018     (#) Declare a I2S_HandleTypeDef handle structure.
00019     (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
00020         (##) Enable the SPIx interface clock.
00021         (##) I2S pins configuration:
00022             (+++) Enable the clock for the I2S GPIOs.
00023             (+++) Configure these I2S pins as alternate function pull-up.
00024         (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
00025              and HAL_I2S_Receive_IT() APIs).
00026             (+++) Configure the I2Sx interrupt priority.
00027             (+++) Enable the NVIC I2S IRQ handle.
00028         (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
00029              and HAL_I2S_Receive_DMA() APIs:
00030             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00031             (+++) Enable the DMAx interface clock.
00032             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00033             (+++) Configure the DMA Tx/Rx Channel.
00034             (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
00035             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00036                 DMA Tx/Rx Channel.
00037
00038    (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
00039        using HAL_I2S_Init() function.
00040
00041    -@- The specific I2S interrupts (Transmission complete interrupt,
00042        RXNE interrupt and Error Interrupts) will be managed using the macros
00043        __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
00044    -@- Make sure that either:
00045        (+@) I2S clock is configured based on SYSCLK or
00046        (+@) External clock source is configured after setting correctly
00047             the define constant EXTERNAL_CLOCK_VALUE in the stm32f3xx_hal_conf.h file.
00048
00049    (#) Three mode of operations are available within this driver :
00050
00051    *** Polling mode IO operation ***
00052    =================================
00053    [..]
00054      (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
00055      (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
00056
00057    *** Interrupt mode IO operation ***
00058    ===================================
00059    [..]
00060      (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
00061      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00062          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00063      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00064          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00065      (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
00066      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00067          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00068      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00069          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00070      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00071          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00072
00073    *** DMA mode IO operation ***
00074    ==============================
00075    [..]
00076      (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
00077      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00078          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00079      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00080          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00081      (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
00082      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00083          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00084      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00085          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00086      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00087          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00088      (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
00089      (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
00090      (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
00091
00092    *** I2S HAL driver macros list ***
00093    =============================================
00094    [..]
00095      Below the list of most used macros in I2S HAL driver.
00096
00097       (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
00098       (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
00099       (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
00100       (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
00101       (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
00102
00103     [..]
00104       (@) You can refer to the I2S HAL driver header file for more useful macros
00105
00106   @endverbatim
00107   ******************************************************************************
00108   * @attention
00109   *
00110   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00111   *
00112   * Redistribution and use in source and binary forms, with or without modification,
00113   * are permitted provided that the following conditions are met:
00114   *   1. Redistributions of source code must retain the above copyright notice,
00115   *      this list of conditions and the following disclaimer.
00116   *   2. Redistributions in binary form must reproduce the above copyright notice,
00117   *      this list of conditions and the following disclaimer in the documentation
00118   *      and/or other materials provided with the distribution.
00119   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00120   *      may be used to endorse or promote products derived from this software
00121   *      without specific prior written permission.
00122   *
00123   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00124   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00125   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00126   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00127   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00128   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00129   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00130   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00131   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00132   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00133   *
00134   ******************************************************************************
00135   */
00136
00137 /* Includes ------------------------------------------------------------------*/
00138 #include "stm32f3xx_hal.h"
00139
00140 #ifdef HAL_I2S_MODULE_ENABLED
00141
00142 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00143     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00144     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
00145     defined(STM32F373xC) || defined(STM32F378xx)
00146
00147 /** @addtogroup STM32F3xx_HAL_Driver
00148   * @{
00149   */
00150
00151 /** @defgroup I2S I2S
00152   * @brief I2S HAL module driver
00153   * @{
00154   */
00155
00156 /* Private typedef -----------------------------------------------------------*/
00157 /* Private define ------------------------------------------------------------*/
00158 /* Private macro -------------------------------------------------------------*/
00159 /* Private variables ---------------------------------------------------------*/
00160 /* Private function prototypes -----------------------------------------------*/
00161 /** @defgroup I2S_Private_Functions I2S Private Functions
00162   * @{
00163   */
00164 static void               I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
00165 static void               I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00166 static void               I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
00167 static void               I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00168 static void               I2S_DMAError(DMA_HandleTypeDef *hdma);
00169 static void               I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
00170 static void               I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
00171 static HAL_StatusTypeDef  I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
00172 /**
00173   * @}
00174   */
00175
00176 /* Exported functions ---------------------------------------------------------*/
00177
00178 /** @defgroup I2S_Exported_Functions I2S Exported Functions
00179   * @{
00180   */
00181
00182 /** @defgroup  I2S_Exported_Functions_Group1 Initialization and de-initialization functions
00183   *  @brief    Initialization and Configuration functions
00184   *
00185 @verbatim
00186  ===============================================================================
00187               ##### Initialization and de-initialization functions #####
00188  ===============================================================================
00189     [..]  This subsection provides a set of functions allowing to initialize and
00190           de-initialiaze the I2Sx peripheral in simplex mode:
00191
00192       (+) User must Implement HAL_I2S_MspInit() function in which he configures
00193           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00194
00195       (+) Call the function HAL_I2S_Init() to configure the selected device with
00196           the selected configuration:
00197         (++) Mode
00198         (++) Standard
00199         (++) Data Format
00200         (++) MCLK Output
00201         (++) Audio frequency
00202         (++) Polarity
00203         (++) Full duplex mode
00204
00205       (+) Call the function HAL_I2S_DeInit() to restore the default configuration
00206           of the selected I2Sx periperal.
00207 @endverbatim
00208   * @{
00209   */
00210
00211 /**
00212   * @brief Initializes the I2S according to the specified parameters
00213   *         in the I2S_InitTypeDef and create the associated handle.
00214   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00215   *         the configuration information for I2S module
00216   * @retval HAL status
00217   */
00218 __weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
00219 {
00220   /* Prevent unused argument(s) compilation warning */
00221   UNUSED(hi2s);
00222
00223   /* Note : This function is defined into this file for library reference.  */
00224   /*        Function content is located into file stm32f3xx_hal_i2s_ex.c to */
00225   /*        handle the possible I2S interfaces defined in STM32F3xx devices */
00226
00227   /* Return error status as not implemented here */
00228   return HAL_ERROR;
00229 }
00230
00231 /**
00232   * @brief DeInitializes the I2S peripheral
00233   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00234   *         the configuration information for I2S module
00235   * @retval HAL status
00236   */
00237 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
00238 {
00239   /* Check the I2S handle allocation */
00240   if(hi2s == NULL)
00241   {
00242     return HAL_ERROR;
00243   }
00244
00245   /* Check the parameters */
00246   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
00247
00248   hi2s->State = HAL_I2S_STATE_BUSY;
00249
00250   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00251   HAL_I2S_MspDeInit(hi2s);
00252
00253   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00254   hi2s->State = HAL_I2S_STATE_RESET;
00255
00256   /* Release Lock */
00257   __HAL_UNLOCK(hi2s);
00258
00259   return HAL_OK;
00260 }
00261
00262 /**
00263   * @brief I2S MSP Init
00264   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00265   *         the configuration information for I2S module
00266   * @retval None
00267   */
00268  __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
00269 {
00270   /* Prevent unused argument(s) compilation warning */
00271   UNUSED(hi2s);
00272
00273   /* NOTE : This function Should not be modified, when the callback is needed,
00274             the HAL_I2S_MspInit could be implemented in the user file
00275    */
00276 }
00277
00278 /**
00279   * @brief I2S MSP DeInit
00280   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00281   *         the configuration information for I2S module
00282   * @retval None
00283   */
00284  __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
00285 {
00286   /* Prevent unused argument(s) compilation warning */
00287   UNUSED(hi2s);
00288
00289   /* NOTE : This function Should not be modified, when the callback is needed,
00290             the HAL_I2S_MspDeInit could be implemented in the user file
00291    */
00292 }
00293
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
00299   *  @brief Data transfers functions
00300   *
00301 @verbatim
00302  ===============================================================================
00303                       ##### IO operation functions #####
00304  ===============================================================================
00305     [..]
00306     This subsection provides a set of functions allowing to manage the I2S data
00307     transfers.
00308
00309     (#) There are two modes of transfer:
00310        (++) Blocking mode : The communication is performed in the polling mode.
00311             The status of all data processing is returned by the same function
00312             after finishing transfer.
00313        (++) No-Blocking mode : The communication is performed using Interrupts
00314             or DMA. These functions return the status of the transfer startup.
00315             The end of the data processing will be indicated through the
00316             dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
00317             using DMA mode.
00318
00319     (#) Blocking mode functions are :
00320         (++) HAL_I2S_Transmit()
00321         (++) HAL_I2S_Receive()
00322
00323     (#) No-Blocking mode functions with Interrupt are :
00324         (++) HAL_I2S_Transmit_IT()
00325         (++) HAL_I2S_Receive_IT()
00326
00327     (#) No-Blocking mode functions with DMA are :
00328         (++) HAL_I2S_Transmit_DMA()
00329         (++) HAL_I2S_Receive_DMA()
00330
00331     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00332         (++) HAL_I2S_TxCpltCallback()
00333         (++) HAL_I2S_RxCpltCallback()
00334         (++) HAL_I2S_ErrorCallback()
00335
00336 @endverbatim
00337   * @{
00338   */
00339
00340 /**
00341   * @brief Transmit an amount of data in blocking mode
00342   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00343   *         the configuration information for I2S module
00344   * @param pData a 16-bit pointer to data buffer.
00345   * @param Size number of data sample to be sent:
00346   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00347   *       configuration phase, the Size parameter means the number of 16-bit data length
00348   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00349   *       the Size parameter means the number of 16-bit data length.
00350   * @param  Timeout Timeout duration
00351   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00352   *       between Master and Slave(example: audio streaming).
00353   * @retval HAL status
00354   */
00355 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
00356 {
00357   if((pData == NULL ) || (Size == 0U))
00358   {
00359     return  HAL_ERROR;
00360   }
00361
00362   if(hi2s->State == HAL_I2S_STATE_READY)
00363   {
00364     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
00365        ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
00366     {
00367       hi2s->TxXferSize = (Size << 1U);
00368       hi2s->TxXferCount = (Size << 1U);
00369     }
00370     else
00371     {
00372       hi2s->TxXferSize = Size;
00373       hi2s->TxXferCount = Size;
00374     }
00375
00376     /* Process Locked */
00377     __HAL_LOCK(hi2s);
00378
00379     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00380     hi2s->State = HAL_I2S_STATE_BUSY_TX;
00381
00382     /* Check if the I2S is already enabled */
00383     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00384     {
00385       /* Enable I2S peripheral */
00386       __HAL_I2S_ENABLE(hi2s);
00387     }
00388
00389     while(hi2s->TxXferCount > 0U)
00390     {
00391       hi2s->Instance->DR = (*pData++);
00392       hi2s->TxXferCount--;
00393       /* Wait until TXE flag is set */
00394       if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
00395       {
00396         /* Set the error code and execute error callback*/
00397         hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
00398         HAL_I2S_ErrorCallback(hi2s);
00399         return HAL_TIMEOUT;
00400       }
00401
00402       /* Check if an underrun occurs */
00403       if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
00404       {
00405         /* Set the I2S State ready */
00406         hi2s->State = HAL_I2S_STATE_READY;
00407
00408         /* Process Unlocked */
00409         __HAL_UNLOCK(hi2s);
00410
00411         /* Set the error code and execute error callback*/
00412         hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
00413         HAL_I2S_ErrorCallback(hi2s);
00414
00415         return HAL_ERROR;
00416       }
00417     }
00418     hi2s->State = HAL_I2S_STATE_READY;
00419
00420     /* Process Unlocked */
00421     __HAL_UNLOCK(hi2s);
00422
00423     return HAL_OK;
00424   }
00425   else
00426   {
00427     return HAL_BUSY;
00428   }
00429 }
00430
00431 /**
00432   * @brief Receive an amount of data in blocking mode
00433   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00434   *         the configuration information for I2S module
00435   * @param pData a 16-bit pointer to data buffer.
00436   * @param Size number of data sample to be sent:
00437   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00438   *       configuration phase, the Size parameter means the number of 16-bit data length
00439   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00440   *       the Size parameter means the number of 16-bit data length.
00441   * @param Timeout Timeout duration
00442   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00443   *       between Master and Slave(example: audio streaming).
00444   * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
00445   *       in continouse way and as the I2S is not disabled at the end of the I2S transaction.
00446   * @retval HAL status
00447   */
00448 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
00449 {
00450   if((pData == NULL ) || (Size == 0U))
00451   {
00452     return  HAL_ERROR;
00453   }
00454
00455   if(hi2s->State == HAL_I2S_STATE_READY)
00456   {
00457     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
00458        ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
00459     {
00460       hi2s->RxXferSize = (Size << 1U);
00461       hi2s->RxXferCount = (Size << 1U);
00462     }
00463     else
00464     {
00465       hi2s->RxXferSize = Size;
00466       hi2s->RxXferCount = Size;
00467     }
00468     /* Process Locked */
00469     __HAL_LOCK(hi2s);
00470
00471     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00472     hi2s->State = HAL_I2S_STATE_BUSY_RX;
00473
00474     /* Check if the I2S is already enabled */
00475     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00476     {
00477       /* Enable I2S peripheral */
00478       __HAL_I2S_ENABLE(hi2s);
00479     }
00480
00481     /* Check if Master Receiver mode is selected */
00482     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
00483     {
00484       /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
00485       access to the SPI_SR register. */
00486       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00487     }
00488
00489     /* Receive data */
00490     while(hi2s->RxXferCount > 0U)
00491     {
00492       /* Wait until RXNE flag is set */
00493       if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00494       {
00495         /* Set the error code and execute error callback*/
00496         hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
00497         HAL_I2S_ErrorCallback(hi2s);
00498         return HAL_TIMEOUT;
00499       }
00500
00501       /* Check if an overrun occurs */
00502       if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
00503       {
00504         /* Set the I2S State ready */
00505         hi2s->State = HAL_I2S_STATE_READY;
00506
00507         /* Process Unlocked */
00508         __HAL_UNLOCK(hi2s);
00509
00510         /* Set the error code and execute error callback*/
00511         hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
00512         HAL_I2S_ErrorCallback(hi2s);
00513
00514         return HAL_ERROR;
00515       }
00516
00517       (*pData++) = hi2s->Instance->DR;
00518       hi2s->RxXferCount--;
00519     }
00520
00521     hi2s->State = HAL_I2S_STATE_READY;
00522
00523     /* Process Unlocked */
00524     __HAL_UNLOCK(hi2s);
00525
00526     return HAL_OK;
00527   }
00528   else
00529   {
00530     return HAL_BUSY;
00531   }
00532 }
00533
00534 /**
00535   * @brief Transmit an amount of data in non-blocking mode with Interrupt
00536   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00537   *         the configuration information for I2S module
00538   * @param pData a 16-bit pointer to data buffer.
00539   * @param Size number of data sample to be sent:
00540   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00541   *       configuration phase, the Size parameter means the number of 16-bit data length
00542   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00543   *       the Size parameter means the number of 16-bit data length.
00544   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00545   *       between Master and Slave(example: audio streaming).
00546   * @retval HAL status
00547   */
00548 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00549 {
00550   if(hi2s->State == HAL_I2S_STATE_READY)
00551   {
00552     if((pData == NULL) || (Size == 0U))
00553     {
00554       return  HAL_ERROR;
00555     }
00556
00557     hi2s->pTxBuffPtr = pData;
00558     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
00559       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
00560     {
00561       hi2s->TxXferSize = (Size << 1U);
00562       hi2s->TxXferCount = (Size << 1U);
00563     }
00564     else
00565     {
00566       hi2s->TxXferSize = Size;
00567       hi2s->TxXferCount = Size;
00568     }
00569
00570     /* Process Locked */
00571     __HAL_LOCK(hi2s);
00572
00573     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00574     hi2s->State = HAL_I2S_STATE_BUSY_TX;
00575
00576     /* Enable TXE and ERR interrupt */
00577     __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00578
00579     /* Check if the I2S is already enabled */
00580     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00581     {
00582       /* Enable I2S peripheral */
00583       __HAL_I2S_ENABLE(hi2s);
00584     }
00585
00586     /* Process Unlocked */
00587     __HAL_UNLOCK(hi2s);
00588
00589     return HAL_OK;
00590   }
00591   else
00592   {
00593     return HAL_BUSY;
00594   }
00595 }
00596
00597 /**
00598   * @brief Receive an amount of data in non-blocking mode with Interrupt
00599   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00600   *         the configuration information for I2S module
00601   * @param pData a 16-bit pointer to the Receive data buffer.
00602   * @param Size number of data sample to be sent:
00603   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00604   *       configuration phase, the Size parameter means the number of 16-bit data length
00605   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00606   *       the Size parameter means the number of 16-bit data length.
00607   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00608   *       between Master and Slave(example: audio streaming).
00609   * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
00610   * between Master and Slave otherwise the I2S interrupt should be optimized.
00611   * @retval HAL status
00612   */
00613 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00614 {
00615   if(hi2s->State == HAL_I2S_STATE_READY)
00616   {
00617     if((pData == NULL) || (Size == 0U))
00618     {
00619       return  HAL_ERROR;
00620     }
00621
00622     hi2s->pRxBuffPtr = pData;
00623     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
00624       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
00625     {
00626       hi2s->RxXferSize = (Size << 1U);
00627       hi2s->RxXferCount = (Size << 1U);
00628     }
00629     else
00630     {
00631       hi2s->RxXferSize = Size;
00632       hi2s->RxXferCount = Size;
00633     }
00634     /* Process Locked */
00635     __HAL_LOCK(hi2s);
00636
00637     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00638     hi2s->State = HAL_I2S_STATE_BUSY_RX;
00639
00640     /* Enable TXE and ERR interrupt */
00641     __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
00642
00643     /* Check if the I2S is already enabled */
00644     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00645     {
00646       /* Enable I2S peripheral */
00647       __HAL_I2S_ENABLE(hi2s);
00648     }
00649
00650     /* Process Unlocked */
00651     __HAL_UNLOCK(hi2s);
00652
00653     return HAL_OK;
00654   }
00655   else
00656   {
00657     return HAL_BUSY;
00658   }
00659 }
00660
00661 /**
00662   * @brief Transmit an amount of data in non-blocking mode with DMA
00663   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00664   *         the configuration information for I2S module
00665   * @param pData a 16-bit pointer to the Transmit data buffer.
00666   * @param Size number of data sample to be sent:
00667   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00668   *       configuration phase, the Size parameter means the number of 16-bit data length
00669   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00670   *       the Size parameter means the number of 16-bit data length.
00671   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00672   *       between Master and Slave(example: audio streaming).
00673   * @retval HAL status
00674   */
00675 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00676 {
00677   uint32_t *tmp;
00678
00679   if((pData == NULL) || (Size == 0U))
00680   {
00681     return  HAL_ERROR;
00682   }
00683
00684   if(hi2s->State == HAL_I2S_STATE_READY)
00685   {
00686     hi2s->pTxBuffPtr = pData;
00687     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
00688       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
00689     {
00690       hi2s->TxXferSize = (Size << 1U);
00691       hi2s->TxXferCount = (Size << 1U);
00692     }
00693     else
00694     {
00695       hi2s->TxXferSize = Size;
00696       hi2s->TxXferCount = Size;
00697     }
00698
00699     /* Process Locked */
00700     __HAL_LOCK(hi2s);
00701
00702     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00703     hi2s->State = HAL_I2S_STATE_BUSY_TX;
00704
00705     /* Set the I2S Tx DMA Half transfer complete callback */
00706     hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
00707
00708     /* Set the I2S Tx DMA transfer complete callback */
00709     hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
00710
00711     /* Set the DMA error callback */
00712     hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
00713
00714     /* Enable the Tx DMA Channel */
00715     tmp = (uint32_t*)&pData;
00716     HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
00717
00718     /* Check if the I2S is already enabled */
00719     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00720     {
00721       /* Enable I2S peripheral */
00722       __HAL_I2S_ENABLE(hi2s);
00723     }
00724
00725     /* Enable Tx DMA Request */
00726     hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
00727
00728     /* Process Unlocked */
00729     __HAL_UNLOCK(hi2s);
00730
00731     return HAL_OK;
00732   }
00733   else
00734   {
00735     return HAL_BUSY;
00736   }
00737 }
00738
00739 /**
00740   * @brief Receive an amount of data in non-blocking mode with DMA
00741   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00742   *         the configuration information for I2S module
00743   * @param pData a 16-bit pointer to the Receive data buffer.
00744   * @param Size number of data sample to be sent:
00745   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00746   *       configuration phase, the Size parameter means the number of 16-bit data length
00747   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00748   *       the Size parameter means the number of 16-bit data length.
00749   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00750   *       between Master and Slave(example: audio streaming).
00751   * @retval HAL status
00752   */
00753 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00754 {
00755   uint32_t *tmp;
00756
00757   if((pData == NULL) || (Size == 0U))
00758   {
00759     return  HAL_ERROR;
00760   }
00761
00762   if(hi2s->State == HAL_I2S_STATE_READY)
00763   {
00764     hi2s->pRxBuffPtr = pData;
00765     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
00766       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
00767     {
00768       hi2s->RxXferSize = (Size << 1U);
00769       hi2s->RxXferCount = (Size << 1U);
00770     }
00771     else
00772     {
00773       hi2s->RxXferSize = Size;
00774       hi2s->RxXferCount = Size;
00775     }
00776     /* Process Locked */
00777     __HAL_LOCK(hi2s);
00778
00779     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00780     hi2s->State = HAL_I2S_STATE_BUSY_RX;
00781
00782     /* Set the I2S Rx DMA Half transfer complete callback */
00783     hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
00784
00785     /* Set the I2S Rx DMA transfer complete callback */
00786     hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
00787
00788     /* Set the DMA error callback */
00789     hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
00790
00791     /* Check if Master Receiver mode is selected */
00792     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
00793     {
00794       /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
00795       access to the SPI_SR register. */
00796       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00797     }
00798
00799     /* Enable the Rx DMA Channel */
00800     tmp = (uint32_t*)&pData;
00801     HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
00802
00803     /* Check if the I2S is already enabled */
00804     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00805     {
00806       /* Enable I2S peripheral */
00807       __HAL_I2S_ENABLE(hi2s);
00808     }
00809
00810     /* Enable Rx DMA Request */
00811     hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
00812
00813     /* Process Unlocked */
00814     __HAL_UNLOCK(hi2s);
00815
00816     return HAL_OK;
00817   }
00818   else
00819   {
00820     return HAL_BUSY;
00821   }
00822 }
00823
00824 /**
00825   * @brief Pauses the audio stream playing from the Media.
00826   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00827   *         the configuration information for I2S module
00828   * @retval HAL status
00829   */
00830 __weak HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
00831 {
00832   /* Process Locked */
00833   __HAL_LOCK(hi2s);
00834
00835   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
00836   {
00837     /* Disable the I2S DMA Tx request */
00838     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
00839   }
00840   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
00841   {
00842     /* Disable the I2S DMA Rx request */
00843     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
00844   }
00845
00846   /* Process Unlocked */
00847   __HAL_UNLOCK(hi2s);
00848
00849   return HAL_OK;
00850 }
00851
00852 /**
00853   * @brief Resumes the audio stream playing from the Media.
00854   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00855   *         the configuration information for I2S module
00856   * @retval HAL status
00857   */
00858 __weak HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
00859 {
00860   /* Process Locked */
00861   __HAL_LOCK(hi2s);
00862
00863   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
00864   {
00865     /* Enable the I2S DMA Tx request */
00866     hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
00867   }
00868   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
00869   {
00870     /* Enable the I2S DMA Rx request */
00871     hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
00872   }
00873
00874   /* If the I2S peripheral is still not enabled, enable it */
00875   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
00876   {
00877     /* Enable I2S peripheral */
00878     __HAL_I2S_ENABLE(hi2s);
00879   }
00880
00881   /* Process Unlocked */
00882   __HAL_UNLOCK(hi2s);
00883
00884   return HAL_OK;
00885 }
00886
00887 /**
00888   * @brief Resumes the audio stream playing from the Media.
00889   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00890   *         the configuration information for I2S module
00891   * @retval HAL status
00892   */
00893 __weak HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
00894 {
00895   /* Process Locked */
00896   __HAL_LOCK(hi2s);
00897
00898   /* Disable the I2S Tx/Rx DMA requests */
00899   hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
00900   hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
00901
00902   /* Abort the I2S DMA tx channel */
00903   if(hi2s->hdmatx != NULL)
00904   {
00905     /* Disable the I2S DMA channel */
00906     __HAL_DMA_DISABLE(hi2s->hdmatx);
00907     HAL_DMA_Abort(hi2s->hdmatx);
00908   }
00909   /* Abort the I2S DMA rx channel */
00910   if(hi2s->hdmarx != NULL)
00911   {
00912     /* Disable the I2S DMA channel */
00913     __HAL_DMA_DISABLE(hi2s->hdmarx);
00914     HAL_DMA_Abort(hi2s->hdmarx);
00915   }
00916
00917   /* Disable I2S peripheral */
00918   __HAL_I2S_DISABLE(hi2s);
00919
00920   hi2s->State = HAL_I2S_STATE_READY;
00921
00922   /* Process Unlocked */
00923   __HAL_UNLOCK(hi2s);
00924
00925   return HAL_OK;
00926 }
00927
00928 /**
00929   * @brief  This function handles I2S interrupt request.
00930   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00931   *         the configuration information for I2S module
00932   * @retval None
00933   */
00934 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
00935 {
00936   __IO uint32_t i2ssr = hi2s->Instance->SR;
00937
00938   if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
00939   {
00940     /* I2S in mode Receiver ----------------------------------------------------*/
00941     if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
00942     {
00943       I2S_Receive_IT(hi2s);
00944     }
00945
00946     /* I2S Overrun error interrupt occured -------------------------------------*/
00947     if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
00948     {
00949       /* Disable RXNE and ERR interrupt */
00950       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
00951
00952       /* Set the I2S State ready */
00953       hi2s->State = HAL_I2S_STATE_READY;
00954
00955       /* Set the error code and execute error callback*/
00956       hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
00957       HAL_I2S_ErrorCallback(hi2s);
00958     }
00959   }
00960   else if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
00961   {
00962     /* I2S in mode Tramitter ---------------------------------------------------*/
00963     if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
00964     {
00965       I2S_Transmit_IT(hi2s);
00966     }
00967
00968     /* I2S Underrun error interrupt occured ------------------------------------*/
00969     if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
00970     {
00971       /* Disable TXE and ERR interrupt */
00972       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00973
00974       /* Set the I2S State ready */
00975       hi2s->State = HAL_I2S_STATE_READY;
00976
00977       /* Set the error code and execute error callback*/
00978       hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
00979       HAL_I2S_ErrorCallback(hi2s);
00980     }
00981   }
00982 }
00983
00984 /**
00985   * @}
00986   */
00987
00988 /**
00989   * @}
00990   */
00991
00992
00993
00994 /** @addtogroup I2S_Exported_Functions I2S Exported Functions
00995   * @{
00996   */
00997
00998 /** @addtogroup  I2S_Exported_Functions_Group2 IO operation functions
00999   * @{
01000   */
01001 /**
01002   * @brief Tx Transfer Half completed callbacks
01003   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01004   *         the configuration information for I2S module
01005   * @retval None
01006   */
01007  __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
01008 {
01009   /* Prevent unused argument(s) compilation warning */
01010   UNUSED(hi2s);
01011
01012   /* NOTE : This function Should not be modified, when the callback is needed,
01013             the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
01014    */
01015 }
01016
01017 /**
01018   * @brief Tx Transfer completed callbacks
01019   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01020   *         the configuration information for I2S module
01021   * @retval None
01022   */
01023  __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
01024 {
01025   /* Prevent unused argument(s) compilation warning */
01026   UNUSED(hi2s);
01027
01028   /* NOTE : This function Should not be modified, when the callback is needed,
01029             the HAL_I2S_TxCpltCallback could be implemented in the user file
01030    */
01031 }
01032
01033 /**
01034   * @brief Rx Transfer half completed callbacks
01035   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01036   *         the configuration information for I2S module
01037   * @retval None
01038   */
01039 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
01040 {
01041   /* Prevent unused argument(s) compilation warning */
01042   UNUSED(hi2s);
01043
01044   /* NOTE : This function Should not be modified, when the callback is needed,
01045             the HAL_I2S_RxCpltCallback could be implemented in the user file
01046    */
01047 }
01048
01049 /**
01050   * @brief Rx Transfer completed callbacks
01051   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01052   *         the configuration information for I2S module
01053   * @retval None
01054   */
01055 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
01056 {
01057   /* Prevent unused argument(s) compilation warning */
01058   UNUSED(hi2s);
01059
01060   /* NOTE : This function Should not be modified, when the callback is needed,
01061             the HAL_I2S_RxCpltCallback could be implemented in the user file
01062    */
01063 }
01064
01065 /**
01066   * @brief I2S error callbacks
01067   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01068   *         the configuration information for I2S module
01069   * @retval None
01070   */
01071  __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
01072 {
01073   /* Prevent unused argument(s) compilation warning */
01074   UNUSED(hi2s);
01075
01076   /* NOTE : This function Should not be modified, when the callback is needed,
01077             the HAL_I2S_ErrorCallback could be implemented in the user file
01078    */
01079 }
01080
01081 /**
01082   * @}
01083   */
01084
01085 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
01086   *  @brief   Peripheral State functions
01087   *
01088 @verbatim
01089  ===============================================================================
01090                       ##### Peripheral State and Errors functions #####
01091  ===============================================================================
01092     [..]
01093     This subsection permits to get in run-time the status of the peripheral
01094     and the data flow.
01095
01096 @endverbatim
01097   * @{
01098   */
01099
01100 /**
01101   * @brief  Return the I2S state
01102   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01103   *         the configuration information for I2S module
01104   * @retval HAL state
01105   */
01106 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
01107 {
01108   return hi2s->State;
01109 }
01110
01111 /**
01112   * @brief  Return the I2S error code
01113   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01114   *         the configuration information for I2S module
01115   * @retval I2S Error Code
01116   */
01117 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
01118 {
01119   return hi2s->ErrorCode;
01120 }
01121 /**
01122   * @}
01123   */
01124
01125 /**
01126   * @}
01127   */
01128
01129 /** @addtogroup I2S_Private_Functions I2S Private Functions
01130   * @{
01131   */
01132 /**
01133   * @brief DMA I2S transmit process complete callback
01134   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01135   *                the configuration information for the specified DMA module.
01136   * @retval None
01137   */
01138 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
01139 {
01140   I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01141
01142   if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
01143   {
01144     /* Disable Tx DMA Request */
01145     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
01146
01147     hi2s->TxXferCount = 0U;
01148     hi2s->State = HAL_I2S_STATE_READY;
01149   }
01150   HAL_I2S_TxCpltCallback(hi2s);
01151 }
01152
01153 /**
01154   * @brief DMA I2S transmit process half complete callback
01155   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01156   *                the configuration information for the specified DMA module.
01157   * @retval None
01158   */
01159 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01160 {
01161   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01162
01163   HAL_I2S_TxHalfCpltCallback(hi2s);
01164 }
01165
01166 /**
01167   * @brief DMA I2S receive process complete callback
01168   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01169   *                the configuration information for the specified DMA module.
01170   * @retval None
01171   */
01172 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
01173 {
01174   I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01175
01176   if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
01177   {
01178     /* Disable Rx DMA Request */
01179     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
01180     hi2s->RxXferCount = 0U;
01181     hi2s->State = HAL_I2S_STATE_READY;
01182   }
01183   HAL_I2S_RxCpltCallback(hi2s);
01184 }
01185
01186 /**
01187   * @brief DMA I2S receive process half complete callback
01188   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01189   *                the configuration information for the specified DMA module.
01190   * @retval None
01191   */
01192 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01193 {
01194   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01195
01196   HAL_I2S_RxHalfCpltCallback(hi2s);
01197 }
01198
01199 /**
01200   * @brief DMA I2S communication error callback
01201   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01202   *                the configuration information for the specified DMA module.
01203   * @retval None
01204   */
01205 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
01206 {
01207   I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01208
01209   /* Disable Rx and Tx DMA Request */
01210   hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
01211   hi2s->TxXferCount = 0U;
01212   hi2s->RxXferCount = 0U;
01213
01214   hi2s->State= HAL_I2S_STATE_READY;
01215
01216   /* Set the error code and execute error callback*/
01217   hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
01218   HAL_I2S_ErrorCallback(hi2s);
01219 }
01220
01221 /**
01222   * @brief Transmit an amount of data in non-blocking mode with Interrupt
01223   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01224   *         the configuration information for I2S module
01225   * @retval None
01226   */
01227 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
01228 {
01229   /* Transmit data */
01230   hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
01231   hi2s->TxXferCount--;
01232
01233   if(hi2s->TxXferCount == 0U)
01234   {
01235     /* Disable TXE and ERR interrupt */
01236     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01237
01238     hi2s->State = HAL_I2S_STATE_READY;
01239     HAL_I2S_TxCpltCallback(hi2s);
01240   }
01241 }
01242
01243 /**
01244   * @brief Receive an amount of data in non-blocking mode with Interrupt
01245   * @param hi2s: I2S handle
01246   * @retval None
01247   */
01248 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
01249 {
01250   /* Receive data */
01251   (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
01252   hi2s->RxXferCount--;
01253
01254   if(hi2s->RxXferCount == 0U)
01255   {
01256     /* Disable RXNE and ERR interrupt */
01257     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01258
01259     hi2s->State = HAL_I2S_STATE_READY;
01260     HAL_I2S_RxCpltCallback(hi2s);
01261   }
01262 }
01263
01264 /**
01265   * @brief This function handles I2S Communication Timeout.
01266   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01267   *         the configuration information for I2S module
01268   * @param Flag Flag checked
01269   * @param State Value of the flag expected
01270   * @param Timeout Duration of the timeout
01271   * @retval HAL status
01272   */
01273 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
01274 {
01275   uint32_t tickstart = HAL_GetTick();
01276
01277   /* Wait until flag is set */
01278   if(State == RESET)
01279   {
01280     while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
01281     {
01282       if(Timeout != HAL_MAX_DELAY)
01283       {
01284         if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
01285         {
01286           /* Set the I2S State ready */
01287           hi2s->State= HAL_I2S_STATE_READY;
01288
01289           /* Process Unlocked */
01290           __HAL_UNLOCK(hi2s);
01291
01292           return HAL_TIMEOUT;
01293         }
01294       }
01295     }
01296   }
01297   else
01298   {
01299     while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
01300     {
01301       if(Timeout != HAL_MAX_DELAY)
01302       {
01303         if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
01304         {
01305           /* Set the I2S State ready */
01306           hi2s->State= HAL_I2S_STATE_READY;
01307
01308           /* Process Unlocked */
01309           __HAL_UNLOCK(hi2s);
01310
01311           return HAL_TIMEOUT;
01312         }
01313       }
01314     }
01315   }
01316   return HAL_OK;
01317 }
01318
01319 /**
01320   * @}
01321   */
01322
01323 /**
01324   * @}
01325   */
01326
01327 /**
01328   * @}
01329   */
01330 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
01331        /* STM32F302xC || STM32F303xC || STM32F358xx || */
01332        /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
01333        /* STM32F373xC || STM32F378xx                   */
01334
01335 #endif /* HAL_I2S_MODULE_ENABLED */
01336
01337 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_i2s.h Source File

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stm32f3xx_hal_i2s.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_i2s.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2S HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_I2S_H
00038 #define __STM32F3xx_HAL_I2S_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00045     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00046     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
00047     defined(STM32F373xC) || defined(STM32F378xx)
00048
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f3xx_hal_def.h"
00051
00052 /** @addtogroup STM32F3xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @addtogroup I2S
00057   * @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /** @defgroup I2S_Exported_Types I2S Exported Types
00062   * @{
00063   */
00064
00065 /**
00066   * @brief I2S Init structure definition
00067   */
00068 typedef struct
00069 {
00070   uint32_t Mode;                /*!< Specifies the I2S operating mode.
00071                                      This parameter can be a value of @ref I2S_Mode */
00072
00073   uint32_t Standard;            /*!< Specifies the standard used for the I2S communication.
00074                                      This parameter can be a value of @ref I2S_Standard */
00075
00076   uint32_t DataFormat;          /*!< Specifies the data format for the I2S communication.
00077                                      This parameter can be a value of @ref I2S_Data_Format */
00078
00079   uint32_t MCLKOutput;          /*!< Specifies whether the I2S MCLK output is enabled or not.
00080                                      This parameter can be a value of @ref I2S_MCLK_Output */
00081
00082   uint32_t AudioFreq;           /*!< Specifies the frequency selected for the I2S communication.
00083                                      This parameter can be a value of @ref I2S_Audio_Frequency */
00084
00085   uint32_t CPOL;                /*!< Specifies the idle state of the I2S clock.
00086                                      This parameter can be a value of @ref I2S_Clock_Polarity */
00087
00088   uint32_t ClockSource;         /*!< Specifies the I2S Clock Source.
00089                                      This parameter can be a value of @ref I2S_Clock_Source */
00090
00091   uint32_t FullDuplexMode;  /*!< Specifies the I2S FullDuplex mode.
00092                                  This parameter can be a value of @ref I2S_FullDuplex_Mode */
00093
00094 }I2S_InitTypeDef;
00095
00096 /**
00097   * @brief  HAL State structures definition
00098   */
00099 typedef enum
00100 {
00101   HAL_I2S_STATE_RESET      = 0x00U,  /*!< I2S not yet initialized or disabled                */
00102   HAL_I2S_STATE_READY      = 0x01U,  /*!< I2S initialized and ready for use                  */
00103   HAL_I2S_STATE_BUSY       = 0x02U,  /*!< I2S internal process is ongoing                    */
00104   HAL_I2S_STATE_BUSY_TX    = 0x03U,  /*!< Data Transmission process is ongoing               */
00105   HAL_I2S_STATE_BUSY_RX    = 0x04U,  /*!< Data Reception process is ongoing                  */
00106   HAL_I2S_STATE_BUSY_TX_RX = 0x05U,  /*!< Data Transmission and Reception process is ongoing */
00107   HAL_I2S_STATE_TIMEOUT    = 0x06U,  /*!< I2S timeout state                                  */
00108   HAL_I2S_STATE_ERROR      = 0x07   /*!< I2S error state                                    */
00109 }HAL_I2S_StateTypeDef;
00110
00111 /**
00112   * @brief I2S handle Structure definition
00113   */
00114 typedef struct
00115 {
00116   SPI_TypeDef                *Instance;    /*!< I2S registers base address */
00117
00118   I2S_InitTypeDef            Init;         /*!< I2S communication parameters */
00119
00120   uint16_t                   *pTxBuffPtr;  /*!< Pointer to I2S Tx transfer buffer */
00121
00122   __IO uint16_t              TxXferSize;   /*!< I2S Tx transfer size */
00123
00124   __IO uint16_t              TxXferCount;  /*!< I2S Tx transfer Counter */
00125
00126   uint16_t                   *pRxBuffPtr;  /*!< Pointer to I2S Rx transfer buffer */
00127
00128   __IO uint16_t              RxXferSize;   /*!< I2S Rx transfer size */
00129
00130   __IO uint16_t              RxXferCount;  /*!< I2S Rx transfer counter
00131                                               (This field is initialized at the
00132                                                same value as transfer size at the
00133                                                beginning of the transfer and
00134                                                decremented when a sample is received.
00135                                                NbSamplesReceived = RxBufferSize-RxBufferCount) */
00136
00137   DMA_HandleTypeDef          *hdmatx;      /*!< I2S Tx DMA handle parameters */
00138
00139   DMA_HandleTypeDef          *hdmarx;      /*!< I2S Rx DMA handle parameters */
00140
00141   __IO HAL_LockTypeDef       Lock;         /*!< I2S locking object */
00142
00143   __IO HAL_I2S_StateTypeDef  State;        /*!< I2S communication state */
00144
00145   __IO uint32_t              ErrorCode;    /*!< I2S Error code
00146                                                 This parameter can be a value of @ref I2S_Error */
00147
00148 }I2S_HandleTypeDef;
00149 /**
00150   * @}
00151   */
00152
00153 /* Exported constants --------------------------------------------------------*/
00154 /** @defgroup I2S_Exported_Constants I2S Exported Constants
00155   * @{
00156   */
00157 /** @defgroup I2S_Error I2S Error
00158   * @{
00159   */
00160 #define HAL_I2S_ERROR_NONE               (0x00000000U)  /*!< No error           */
00161 #define HAL_I2S_ERROR_TIMEOUT            (0x00000001U)  /*!< Timeout error      */
00162 #define HAL_I2S_ERROR_OVR                (0x00000002U)  /*!< OVR error          */
00163 #define HAL_I2S_ERROR_UDR                (0x00000004U)  /*!< UDR error          */
00164 #define HAL_I2S_ERROR_DMA                (0x00000008U)  /*!< DMA transfer error */
00165 #define HAL_I2S_ERROR_UNKNOW             (0x00000010U)  /*!< Unknow Error error */
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup I2S_Clock_Source I2S Clock Source
00171   * @{
00172   */
00173 #define I2S_CLOCK_EXTERNAL                (0x00000001U)
00174 #define I2S_CLOCK_SYSCLK                  (0x00000002U)
00175
00176 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
00177                                    ((CLOCK) == I2S_CLOCK_SYSCLK))
00178 /**
00179   * @}
00180   */
00181
00182 /** @defgroup I2S_Mode I2S Mode
00183   * @{
00184   */
00185 #define I2S_MODE_SLAVE_TX                (0x00000000U)
00186 #define I2S_MODE_SLAVE_RX                (0x00000100U)
00187 #define I2S_MODE_MASTER_TX               (0x00000200U)
00188 #define I2S_MODE_MASTER_RX               (0x00000300U)
00189
00190 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
00191                            ((MODE) == I2S_MODE_SLAVE_RX) || \
00192                            ((MODE) == I2S_MODE_MASTER_TX)|| \
00193                            ((MODE) == I2S_MODE_MASTER_RX))
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup I2S_Standard I2S Standard
00199   * @{
00200   */
00201 #define I2S_STANDARD_PHILIPS             (0x00000000U)
00202 #define I2S_STANDARD_MSB                 (0x00000010U)
00203 #define I2S_STANDARD_LSB                 (0x00000020U)
00204 #define I2S_STANDARD_PCM_SHORT           (0x00000030U)
00205 #define I2S_STANDARD_PCM_LONG            (0x000000B0U)
00206
00207 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
00208                                    ((STANDARD) == I2S_STANDARD_MSB) || \
00209                                    ((STANDARD) == I2S_STANDARD_LSB) || \
00210                                    ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
00211                                    ((STANDARD) == I2S_STANDARD_PCM_LONG))
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup I2S_Data_Format I2S Data Format
00217   * @{
00218   */
00219 #define I2S_DATAFORMAT_16B               (0x00000000U)
00220 #define I2S_DATAFORMAT_16B_EXTENDED      (0x00000001U)
00221 #define I2S_DATAFORMAT_24B               (0x00000003U)
00222 #define I2S_DATAFORMAT_32B               (0x00000005U)
00223
00224 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
00225                                     ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
00226                                     ((FORMAT) == I2S_DATAFORMAT_24B) || \
00227                                     ((FORMAT) == I2S_DATAFORMAT_32B))
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup I2S_MCLK_Output I2S MCLK Output
00233   * @{
00234   */
00235 #define I2S_MCLKOUTPUT_ENABLE           ((uint32_t)SPI_I2SPR_MCKOE)
00236 #define I2S_MCLKOUTPUT_DISABLE          (0x00000000U)
00237
00238 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
00239                                     ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
00245   * @{
00246   */
00247 #define I2S_AUDIOFREQ_192K               (192000U)
00248 #define I2S_AUDIOFREQ_96K                (96000U)
00249 #define I2S_AUDIOFREQ_48K                (48000U)
00250 #define I2S_AUDIOFREQ_44K                (44100U)
00251 #define I2S_AUDIOFREQ_32K                (32000U)
00252 #define I2S_AUDIOFREQ_22K                (22050U)
00253 #define I2S_AUDIOFREQ_16K                (16000U)
00254 #define I2S_AUDIOFREQ_11K                (11025U)
00255 #define I2S_AUDIOFREQ_8K                 (8000U)
00256 #define I2S_AUDIOFREQ_DEFAULT            (2U)
00257
00258 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
00259                                  ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
00260                                  ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup I2S_FullDuplex_Mode I2S Full Duplex Mode
00266   * @{
00267   */
00268 #define I2S_FULLDUPLEXMODE_DISABLE                   (0x00000000U)
00269 #define I2S_FULLDUPLEXMODE_ENABLE                    (0x00000001U)
00270
00271 #define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
00272                                       ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity
00278   * @{
00279   */
00280 #define I2S_CPOL_LOW                    (0x00000000U)
00281 #define I2S_CPOL_HIGH                   ((uint32_t)SPI_I2SCFGR_CKPOL)
00282
00283 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
00284                            ((CPOL) == I2S_CPOL_HIGH))
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
00290   * @{
00291   */
00292 #define I2S_IT_TXE                      SPI_CR2_TXEIE
00293 #define I2S_IT_RXNE                     SPI_CR2_RXNEIE
00294 #define I2S_IT_ERR                      SPI_CR2_ERRIE
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup I2S_Flag_definition I2S Flag definition
00300   * @{
00301   */
00302 #define I2S_FLAG_TXE                    SPI_SR_TXE
00303 #define I2S_FLAG_RXNE                   SPI_SR_RXNE
00304
00305 #define I2S_FLAG_UDR                    SPI_SR_UDR
00306 #define I2S_FLAG_OVR                    SPI_SR_OVR
00307 #define I2S_FLAG_FRE                    SPI_SR_FRE
00308
00309 #define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE
00310 #define I2S_FLAG_BSY                    SPI_SR_BSY
00311 /**
00312   * @}
00313   */
00314
00315 /**
00316   * @}
00317   */
00318
00319 /* Exported macros -----------------------------------------------------------*/
00320 /** @defgroup I2S_Exported_Macros I2S Exported Macros
00321   * @{
00322   */
00323
00324 /** @brief  Reset I2S handle state
00325   * @param  __HANDLE__ I2S handle.
00326   * @retval None
00327   */
00328 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
00329
00330 /** @brief  Enable or disable the specified SPI peripheral (in I2S mode).
00331   * @param  __HANDLE__ specifies the I2S Handle.
00332   * @retval None
00333   */
00334 #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
00335 #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SE))
00336
00337 /** @brief  Enable or disable the specified I2S interrupts.
00338   * @param  __HANDLE__ specifies the I2S Handle.
00339   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
00340   *        This parameter can be one of the following values:
00341   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00342   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00343   *            @arg I2S_IT_ERR: Error interrupt enable
00344   * @retval None
00345   */
00346 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
00347 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__)))
00348
00349 /** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
00350   * @param  __HANDLE__ specifies the I2S Handle.
00351   *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
00352   * @param  __INTERRUPT__ specifies the I2S interrupt source to check.
00353   *          This parameter can be one of the following values:
00354   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00355   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00356   *            @arg I2S_IT_ERR: Error interrupt enable
00357   * @retval The new state of __IT__ (TRUE or FALSE).
00358   */
00359 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00360
00361 /** @brief  Checks whether the specified I2S flag is set or not.
00362   * @param  __HANDLE__ specifies the I2S Handle.
00363   * @param  __FLAG__ specifies the flag to check.
00364   *        This parameter can be one of the following values:
00365   *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
00366   *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
00367   *            @arg I2S_FLAG_UDR: Underrun flag
00368   *            @arg I2S_FLAG_OVR: Overrun flag
00369   *            @arg I2S_FLAG_FRE: Frame error flag
00370   *            @arg I2S_FLAG_CHSIDE: Channel Side flag
00371   *            @arg I2S_FLAG_BSY: Busy flag
00372   * @retval The new state of __FLAG__ (TRUE or FALSE).
00373   */
00374 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00375
00376 /** @brief Clears the I2S OVR pending flag.
00377   * @param  __HANDLE__ specifies the I2S Handle.
00378   * @retval None
00379   */
00380 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
00381                                                __IO uint32_t tmpreg; \
00382                                                tmpreg = (__HANDLE__)->Instance->DR; \
00383                                                tmpreg = (__HANDLE__)->Instance->SR; \
00384                                                UNUSED(tmpreg); \
00385                                               }while(0U)
00386 /** @brief Clears the I2S UDR pending flag.
00387   * @param  __HANDLE__ specifies the I2S Handle.
00388   * @retval None
00389   */
00390 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
00391                                                __IO uint32_t tmpreg;\
00392                                                tmpreg = ((__HANDLE__)->Instance->SR);\
00393                                                UNUSED(tmpreg); \
00394                                               }while(0U)
00395 /**
00396   * @}
00397   */
00398
00399 /* Include I2S HAL Extended module */
00400 #include "stm32f3xx_hal_i2s_ex.h"
00401
00402 /* Exported functions --------------------------------------------------------*/
00403 /** @addtogroup I2S_Exported_Functions
00404   * @{
00405   */
00406
00407 /** @addtogroup I2S_Exported_Functions_Group1
00408   * @{
00409   */
00410
00411 /* Initialization and de-initialization functions *****************************/
00412 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
00413 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
00414 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
00415 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
00416 /**
00417   * @}
00418   */
00419
00420 /** @addtogroup I2S_Exported_Functions_Group2
00421   * @{
00422   */
00423 /* I/O operation functions  ***************************************************/
00424  /* Blocking mode: Polling */
00425 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
00426 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
00427
00428  /* Non-Blocking mode: Interrupt */
00429 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00430 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00431 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
00432
00433 /* Non-Blocking mode: DMA */
00434 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00435 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00436
00437 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
00438 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
00439 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
00440
00441 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
00442 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00443 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
00444 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00445 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
00446 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
00447 /**
00448   * @}
00449   */
00450
00451 /** @addtogroup I2S_Exported_Functions_Group3
00452   * @{
00453   */
00454 /* Peripheral Control and State functions  ************************************/
00455 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
00456 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
00457 /**
00458   * @}
00459   */
00460
00461 /**
00462   * @}
00463   */
00464
00465
00466 /**
00467   * @}
00468   */
00469
00470 /**
00471   * @}
00472   */
00473
00474 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00475        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00476        /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
00477        /* STM32F373xC || STM32F378xx                   */
00478
00479 #ifdef __cplusplus
00480 }
00481 #endif
00482
00483
00484 #endif /* __STM32F3xx_HAL_I2S_H */
00485
00486 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:08 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_i2s_ex.c Source File

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stm32f3xx_hal_i2s_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_i2s_ex.c
00004   * @author  MCD Application Team
00005   * @brief   I2S Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of I2S Extended peripheral:
00008   *           + Extended features Functions
00009   *
00010   @verbatim
00011   ==============================================================================
00012                     ##### I2S Extended features #####
00013   ==============================================================================
00014  [..]
00015     (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
00016         data simultaneously using two data lines. Each SPI peripheral has an extended block
00017         called I2Sxext ie. I2S2ext for SPI2 and I2S3ext for SPI3).
00018     (#) The Extended block is not a full SPI IP, it is used only as I2S slave to
00019         implement full duplex mode. The Extended block uses the same clock sources
00020         as its master.
00021
00022     (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
00023
00024      -@- Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
00025          I2Sx can be I2S2 or I2S3.
00026
00027  ===============================================================================
00028                   ##### How to use this driver #####
00029  ===============================================================================
00030  [..]
00031    Three mode of operations are available within this driver :
00032
00033    *** Polling mode IO operation ***
00034    =================================
00035    [..]
00036      (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive()
00037
00038    *** Interrupt mode IO operation ***
00039    ===================================
00040    [..]
00041      (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT()
00042      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00043          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00044      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00045          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00046      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00047          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00048      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00049          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00050      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00051          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00052
00053    *** DMA mode IO operation ***
00054    ==============================
00055    [..]
00056      (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA()
00057      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00058          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00059      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00060          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00061      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00062          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00063      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00064          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00065      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00066          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00067      (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
00068      (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
00069      (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
00070
00071   @endverbatim
00072   ******************************************************************************
00073   * @attention
00074   *
00075   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00076   *
00077   * Redistribution and use in source and binary forms, with or without modification,
00078   * are permitted provided that the following conditions are met:
00079   *   1. Redistributions of source code must retain the above copyright notice,
00080   *      this list of conditions and the following disclaimer.
00081   *   2. Redistributions in binary form must reproduce the above copyright notice,
00082   *      this list of conditions and the following disclaimer in the documentation
00083   *      and/or other materials provided with the distribution.
00084   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00085   *      may be used to endorse or promote products derived from this software
00086   *      without specific prior written permission.
00087   *
00088   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00089   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00090   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00091   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00092   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00093   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00094   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00095   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00096   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00097   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00098   *
00099   ******************************************************************************
00100   */
00101 /*
00102   Additional Figure: The Extended block uses the same clock sources as its master.
00103
00104                 +-----------------------+
00105     I2Sx_SCK    |                       |
00106   ----------+-->|          I2Sx         |------------------->I2Sx_SD(in/out)
00107          +--|-->|                       |
00108         |   |   +-----------------------+
00109         |   |
00110  I2S_WS |   |
00111  ------>|   |
00112         |   |   +-----------------------+
00113         |   +-->|                       |
00114         |       |       I2Sx_ext        |------------------->I2Sx_extSD(in/out)
00115          +----->|                       |
00116                 +-----------------------+
00117 */
00118
00119 /* Includes ------------------------------------------------------------------*/
00120 #include "stm32f3xx_hal.h"
00121
00122 #ifdef HAL_I2S_MODULE_ENABLED
00123
00124 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00125     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00126     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
00127     defined(STM32F373xC) || defined(STM32F378xx)
00128
00129 /** @addtogroup STM32F3xx_HAL_Driver
00130   * @{
00131   */
00132
00133 /** @defgroup I2SEx I2SEx
00134   * @brief I2S Extended HAL module driver
00135   * @{
00136   */
00137
00138 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
00139
00140 /* Private typedef -----------------------------------------------------------*/
00141 /** @defgroup I2SEx_Private_Typedef I2S Extended Private Typedef
00142   * @{
00143   */
00144 typedef enum
00145 {
00146   I2S_USE_I2S      = 0x00U,   /*!< I2Sx should be used           */
00147   I2S_USE_I2SEXT   = 0x01    /*!< I2Sx_ext should be used       */
00148 }I2S_UseTypeDef;
00149 /**
00150   * @}
00151   */
00152
00153 /* Private define ------------------------------------------------------------*/
00154 /* Private macro -------------------------------------------------------------*/
00155 /* Private variables ---------------------------------------------------------*/
00156 /* Private function prototypes -----------------------------------------------*/
00157 /** @defgroup I2SEx_Private_Functions I2S Extended Private Functions
00158   * @{
00159   */
00160 static void I2S_TxRxDMACplt(DMA_HandleTypeDef *hdma);
00161 static void I2S_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma);
00162 static void I2S_TxRxDMAError(DMA_HandleTypeDef *hdma);
00163 static void I2S_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
00164 static void I2S_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
00165 static HAL_StatusTypeDef I2S_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
00166                                                                  uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed);
00167 /**
00168   * @}
00169   */
00170
00171 /**
00172   * @}
00173   */
00174 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
00175
00176 /* Exported functions ---------------------------------------------------------*/
00177
00178 /** @addtogroup I2S I2S
00179   * @{
00180   */
00181
00182 /** @addtogroup I2S_Exported_Functions I2S Exported Functions
00183   * @{
00184   */
00185
00186 /** @addtogroup  I2S_Exported_Functions_Group1 Initialization and de-initialization functions
00187   *  @brief    Initialization and Configuration functions
00188   *
00189 @verbatim
00190  ===============================================================================
00191               ##### Initialization and de-initialization functions #####
00192  ===============================================================================
00193     [..]  This subsection provides a set of functions allowing to initialize and
00194           de-initialiaze the I2Sx peripheral in simplex mode:
00195
00196       (+) User must Implement HAL_I2S_MspInit() function in which he configures
00197           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00198
00199       (+) Call the function HAL_I2S_Init() to configure the selected device with
00200           the selected configuration:
00201         (++) Mode
00202         (++) Standard
00203         (++) Data Format
00204         (++) MCLK Output
00205         (++) Audio frequency
00206         (++) Polarity
00207
00208       (+) Call the function HAL_I2S_DeInit() to restore the default configuration
00209           of the selected I2Sx periperal.
00210 @endverbatim
00211   * @{
00212   */
00213
00214 /**
00215   * @brief Initializes the I2S according to the specified parameters
00216   *         in the I2S_InitTypeDef and create the associated handle.
00217   * @param hi2s: I2S handle
00218   * @retval HAL status
00219   */
00220 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
00221 {
00222   uint16_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
00223   uint32_t tmp = 0U, i2sclk = 0U;
00224 #if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
00225   RCC_PeriphCLKInitTypeDef rccperiphclkinit;
00226 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
00227
00228   /* Check the I2S handle allocation */
00229   if(hi2s == NULL)
00230   {
00231     return HAL_ERROR;
00232   }
00233
00234   /* Check the parameters */
00235   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
00236   assert_param(IS_I2S_MODE(hi2s->Init.Mode));
00237   assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
00238   assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
00239   assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
00240   assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
00241   assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
00242   assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
00243   assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
00244
00245   hi2s->State = HAL_I2S_STATE_BUSY;
00246
00247   /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00248   HAL_I2S_MspInit(hi2s);
00249
00250   /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
00251   /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
00252   hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
00253                                SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
00254                                SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
00255   hi2s->Instance->I2SPR = 0x0002U;
00256
00257   /* Get the I2SCFGR register value */
00258   tmpreg = hi2s->Instance->I2SCFGR;
00259
00260   /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
00261   if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
00262   {
00263     i2sodd = (uint16_t)0U;
00264     i2sdiv = (uint16_t)2U;
00265   }
00266   /* If the requested audio frequency is not the default, compute the prescaler */
00267   else
00268   {
00269     /* Check the frame length (For the Prescaler computing) *******************/
00270     if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
00271     {
00272       /* Packet length is 16 bits */
00273       packetlength = 1U;
00274     }
00275     else
00276     {
00277       /* Packet length is 32 bits */
00278       packetlength = 2U;
00279     }
00280
00281     /* Get I2S source Clock frequency  ****************************************/
00282 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
00283     rccperiphclkinit.PeriphClockSelection = RCC_PERIPHCLK_I2S;
00284
00285     /* If an external I2S clock has to be used, the specific define should be set
00286     in the project configuration or in the stm32f3xx_conf.h file */
00287     if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
00288     {
00289       /* Set external clock as I2S clock source */
00290       rccperiphclkinit.I2sClockSelection = RCC_I2SCLKSOURCE_EXT;
00291       HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit);
00292
00293       /* Set the I2S clock to the external clock  value */
00294       i2sclk = EXTERNAL_CLOCK_VALUE;
00295     }
00296     else
00297     {
00298       /* Set SYSCLK as I2S clock source */
00299       rccperiphclkinit.I2sClockSelection = RCC_I2SCLKSOURCE_SYSCLK;
00300       HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit);
00301
00302       /* Get the I2S source clock value */
00303       i2sclk = HAL_RCC_GetSysClockFreq();
00304     }
00305 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
00306
00307 #if defined (STM32F373xC) || defined (STM32F378xx)
00308     if(hi2s->Instance == SPI1)
00309     {
00310       i2sclk = HAL_RCC_GetPCLK2Freq();
00311     }
00312     else if((hi2s->Instance == SPI2) || (hi2s->Instance == SPI3))
00313     {
00314       i2sclk = HAL_RCC_GetPCLK1Freq();
00315     }
00316 #endif /* STM32F373xC || STM32F378xx */
00317
00318     /* Compute the Real divider depending on the MCLK output state, with a floating point */
00319     if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
00320     {
00321       /* MCLK output is enabled */
00322       tmp = (uint16_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
00323     }
00324     else
00325     {
00326       /* MCLK output is disabled */
00327       tmp = (uint16_t)(((((i2sclk / (32U * packetlength)) *10U ) / hi2s->Init.AudioFreq)) + 5U);
00328     }
00329
00330     /* Remove the flatting point */
00331     tmp = tmp / 10U;
00332
00333     /* Check the parity of the divider */
00334     i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
00335
00336     /* Compute the i2sdiv prescaler */
00337     i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
00338
00339     /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
00340     i2sodd = (uint16_t) (i2sodd << 8U);
00341   }
00342
00343   /* Test if the divider is 1 or 0 or greater than 0xFFU */
00344   if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
00345   {
00346     /* Set the default values */
00347     i2sdiv = 2U;
00348     i2sodd = 0U;
00349   }
00350
00351   /* Write to SPIx I2SPR register the computed value */
00352   hi2s->Instance->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)hi2s->Init.MCLKOutput));
00353
00354   /* Configure the I2S with the I2S_InitStruct values */
00355   tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \
00356                        (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
00357                        (uint16_t)hi2s->Init.CPOL))));
00358
00359   /* Write to SPIx I2SCFGR */
00360   hi2s->Instance->I2SCFGR = tmpreg;
00361
00362 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
00363   if (hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
00364   {
00365     /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
00366     I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
00367                                           SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
00368                                           SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
00369     I2SxEXT(hi2s->Instance)->I2SPR = 0x0002U;
00370
00371     /* Get the I2SCFGR register value */
00372     tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
00373
00374     /* Get the mode to be configured for the extended I2S */
00375     if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
00376     {
00377       tmp = I2S_MODE_SLAVE_RX;
00378     }
00379     else
00380     {
00381       if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
00382       {
00383         tmp = I2S_MODE_SLAVE_TX;
00384       }
00385     }
00386
00387     /* Configure the I2S Slave with the I2S Master parameter values */
00388     tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
00389                          (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
00390                          (uint16_t)hi2s->Init.CPOL))));
00391
00392     /* Write to SPIx I2SCFGR */
00393     I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg;
00394   }
00395 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
00396
00397   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00398   hi2s->State= HAL_I2S_STATE_READY;
00399
00400   return HAL_OK;
00401 }
00402 /**
00403   * @}
00404   */
00405
00406 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
00407 /** @addtogroup  I2S_Exported_Functions_Group2 IO operation functions
00408   * @{
00409   */
00410
00411 /**
00412   * @brief  This function handles I2S/I2Sext interrupt requests in full-duplex mode.
00413   * @param  hi2s: I2S handle
00414   * @retval HAL status
00415   */
00416 void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s)
00417 {
00418   __IO uint32_t i2ssr = hi2s->Instance->SR ;
00419   __IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR;
00420
00421   /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
00422   if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
00423   {
00424     /* I2S in mode Transmitter -------------------------------------------------*/
00425     if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
00426     {
00427       /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
00428       the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
00429       I2S_FullDuplexTx_IT(hi2s, I2S_USE_I2S);
00430     }
00431
00432     /* I2Sext in mode Receiver -----------------------------------------------*/
00433     if(((i2sextsr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
00434     {
00435       /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
00436       the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
00437       I2S_FullDuplexRx_IT(hi2s, I2S_USE_I2SEXT);
00438     }
00439
00440     /* I2Sext Overrun error interrupt occured --------------------------------*/
00441     if(((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
00442     {
00443       /* Disable RXNE and ERR interrupt */
00444       __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
00445
00446       /* Disable TXE and ERR interrupt */
00447       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00448
00449       /* Set the I2S State ready */
00450       hi2s->State = HAL_I2S_STATE_READY;
00451
00452       /* Set the error code and execute error callback*/
00453       hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
00454       HAL_I2S_ErrorCallback(hi2s);
00455     }
00456
00457     /* I2S Underrun error interrupt occured ----------------------------------*/
00458     if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
00459     {
00460       /* Disable TXE and ERR interrupt */
00461       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00462
00463       /* Disable RXNE and ERR interrupt */
00464       __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
00465
00466       /* Set the I2S State ready */
00467       hi2s->State = HAL_I2S_STATE_READY;
00468
00469       /* Set the error code and execute error callback*/
00470       hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
00471       HAL_I2S_ErrorCallback(hi2s);
00472     }
00473   }
00474   /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
00475   else
00476   {
00477     /* I2Sext in mode Transmitter ----------------------------------------------*/
00478     if(((i2sextsr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
00479     {
00480       /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
00481       the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
00482       I2S_FullDuplexTx_IT(hi2s, I2S_USE_I2SEXT);
00483     }
00484
00485     /* I2S in mode Receiver --------------------------------------------------*/
00486     if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
00487     {
00488       /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
00489       the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
00490       I2S_FullDuplexRx_IT(hi2s, I2S_USE_I2S);
00491     }
00492
00493     /* I2S Overrun error interrupt occured -------------------------------------*/
00494     if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
00495     {
00496       /* Disable RXNE and ERR interrupt */
00497       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
00498
00499       /* Disable TXE and ERR interrupt */
00500       __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00501
00502       /* Set the I2S State ready */
00503       hi2s->State = HAL_I2S_STATE_READY;
00504
00505       /* Set the error code and execute error callback*/
00506       hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
00507       HAL_I2S_ErrorCallback(hi2s);
00508     }
00509
00510     /* I2Sext Underrun error interrupt occured -------------------------------*/
00511     if(((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
00512     {
00513       /* Disable TXE and ERR interrupt */
00514       __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00515
00516       /* Disable RXNE and ERR interrupt */
00517       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
00518
00519       /* Set the I2S State ready */
00520       hi2s->State = HAL_I2S_STATE_READY;
00521
00522       /* Set the error code and execute error callback*/
00523       hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
00524       HAL_I2S_ErrorCallback(hi2s);
00525     }
00526   }
00527 }
00528
00529 /**
00530   * @brief Tx and Rx Transfer completed callbacks
00531   * @param hi2s: I2S handle
00532   * @retval None
00533   */
00534 __weak void HAL_I2S_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
00535 {
00536   /* Prevent unused argument(s) compilation warning */
00537   UNUSED(hi2s);
00538
00539   /* NOTE : This function Should not be modified, when the callback is needed,
00540             the HAL_I2S_TxRxCpltCallback could be implemented in the user file
00541    */
00542 }
00543
00544 /**
00545   * @brief Tx and Rx Transfer half completed callbacks
00546   * @param hi2s: I2S handle
00547   * @retval None
00548   */
00549 __weak void HAL_I2S_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
00550 {
00551   /* Prevent unused argument(s) compilation warning */
00552   UNUSED(hi2s);
00553
00554   /* NOTE : This function Should not be modified, when the callback is needed,
00555             the HAL_I2S_TxRxHalfCpltCallback could be implemented in the user file
00556    */
00557 }
00558
00559 /**
00560   * @}
00561   */
00562
00563 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
00564
00565 /** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
00566   *  @brief   Peripheral State functions
00567   *
00568   *
00569 @verbatim
00570  ===============================================================================
00571                       ##### Peripheral State functions #####
00572  ===============================================================================
00573     [..]
00574     This subsection permit to get in run-time the status of the peripheral
00575     and the data flow.
00576
00577 @endverbatim
00578   * @{
00579   */
00580 /**
00581   * @brief Pauses the audio stream playing from the Media.
00582   * @param  hi2s : I2S handle
00583   * @retval None
00584   */
00585 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
00586 {
00587   /* Process Locked */
00588   __HAL_LOCK(hi2s);
00589
00590   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
00591   {
00592     /* Pause the audio file playing by disabling the I2S DMA request */
00593     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
00594   }
00595   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
00596   {
00597     /* Pause the audio file playing by disabling the I2S DMA request */
00598     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
00599   }
00600 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
00601   else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
00602   {
00603     /* Pause the audio file playing by disabling the I2S DMA request */
00604     hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
00605     I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
00606   }
00607 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
00608
00609   /* Process Unlocked */
00610   __HAL_UNLOCK(hi2s);
00611
00612   return HAL_OK;
00613 }
00614
00615 /**
00616   * @brief Resumes the audio stream playing from the Media.
00617   * @param  hi2s : I2S handle
00618   * @retval None
00619   */
00620 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
00621 {
00622   /* Process Locked */
00623   __HAL_LOCK(hi2s);
00624
00625   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
00626   {
00627     /* Enable the I2S DMA request */
00628     hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
00629   }
00630   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
00631   {
00632     /* Enable the I2S DMA request */
00633     hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
00634   }
00635 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
00636   else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
00637   {
00638     /* Pause the audio file playing by disabling the I2S DMA request */
00639     hi2s->Instance->CR2 |= (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
00640     I2SxEXT(hi2s->Instance)->CR2 |= (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
00641
00642     /* If the I2Sext peripheral is still not enabled, enable it */
00643     if ((I2SxEXT(hi2s->Instance)->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
00644     {
00645       /* Enable I2Sext peripheral */
00646       __HAL_I2SEXT_ENABLE(hi2s);
00647     }
00648   }
00649 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
00650
00651   /* If the I2S peripheral is still not enabled, enable it */
00652   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
00653   {
00654     /* Enable I2S peripheral */
00655     __HAL_I2S_ENABLE(hi2s);
00656   }
00657
00658   /* Process Unlocked */
00659   __HAL_UNLOCK(hi2s);
00660
00661   return HAL_OK;
00662 }
00663
00664 /**
00665   * @brief Resumes the audio stream playing from the Media.
00666   * @param hi2s: I2S handle
00667   * @retval None
00668   */
00669 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
00670 {
00671   /* Process Locked */
00672   __HAL_LOCK(hi2s);
00673
00674   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
00675   {
00676     /* Disable the I2S DMA requests */
00677     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
00678
00679     /* Disable the I2S DMA Channel */
00680     HAL_DMA_Abort(hi2s->hdmatx);
00681   }
00682   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
00683   {
00684     /* Disable the I2S DMA requests */
00685     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
00686
00687     /* Disable the I2S DMA Channel */
00688     HAL_DMA_Abort(hi2s->hdmarx);
00689   }
00690 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
00691   else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
00692   {
00693     /* Disable the I2S DMA requests */
00694     hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
00695     I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
00696
00697     /* Disable the I2S DMA Channels */
00698     HAL_DMA_Abort(hi2s->hdmatx);
00699     HAL_DMA_Abort(hi2s->hdmarx);
00700
00701     /* Disable I2Sext peripheral */
00702     __HAL_I2SEXT_DISABLE(hi2s);
00703   }
00704 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
00705
00706   /* Disable I2S peripheral */
00707   __HAL_I2S_DISABLE(hi2s);
00708
00709   hi2s->State = HAL_I2S_STATE_READY;
00710
00711   /* Process Unlocked */
00712   __HAL_UNLOCK(hi2s);
00713
00714   return HAL_OK;
00715 }
00716
00717 /**
00718   * @}
00719   */
00720
00721 /**
00722   * @}
00723   */
00724
00725 /**
00726   * @}
00727   */
00728
00729 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
00730 /** @addtogroup I2SEx
00731   * @brief I2S Extended HAL module driver
00732   * @{
00733   */
00734
00735 /** @defgroup I2SEx_Exported_Functions I2S Extended Exported Functions
00736   * @{
00737   */
00738
00739 /** @defgroup I2SEx_Exported_Functions_Group1 I2S Extended Features Functions
00740   *  @brief   Extended features functions
00741   *
00742 @verbatim
00743  ===============================================================================
00744                        ##### Extended features Functions #####
00745  ===============================================================================
00746     [..]
00747     This subsection provides a set of functions allowing to manage the I2S data
00748     transfers.
00749
00750     (#) There is two mode of transfer:
00751        (++) Blocking mode: The communication is performed in the polling mode.
00752             The status of all data processing is returned by the same function
00753             after finishing transfer.
00754        (++) No-Blocking mode: The communication is performed using Interrupts
00755             or DMA. These functions return the status of the transfer startup.
00756             The end of the data processing will be indicated through the
00757             dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
00758             using DMA mode.
00759
00760     (#) Blocking mode functions are :
00761         (++) HAL_I2S_TransmitReceive()
00762
00763     (#) No-Blocking mode functions with Interrupt are:
00764         (++) HAL_I2S_TransmitReceive_IT()
00765         (++) HAL_I2SFullDuplex_IRQHandler()
00766
00767     (#) No-Blocking mode functions with DMA are:
00768         (++) HAL_I2S_TransmitReceive_DMA()
00769
00770     (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
00771         (++) HAL_I2S_TxRxCpltCallback()
00772         (++) HAL_I2S_TxRxHalfCpltCallback()
00773         (++) HAL_I2S_TxRxErrorCallback()
00774
00775 @endverbatim
00776   * @{
00777   */
00778
00779 /**
00780   * @brief Full-Duplex Transmit/Receive data in blocking mode.
00781   * @param hi2s: I2S handle
00782   * @param pTxData a 16-bit pointer to the Transmit data buffer.
00783   * @param pRxData a 16-bit pointer to the Receive data buffer.
00784   * @param Size number of data sample to be sent:
00785   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00786   *       configuration phase, the Size parameter means the number of 16-bit data length
00787   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00788   *       the Size parameter means the number of 16-bit data length.
00789   * @param Timeout Timeout duration
00790   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00791   *       between Master and Slave(example: audio streaming).
00792   * @retval HAL status
00793   */
00794 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
00795 {
00796   if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
00797   {
00798     return  HAL_ERROR;
00799   }
00800
00801   /* Check the I2S State */
00802   if(hi2s->State == HAL_I2S_STATE_READY)
00803   {
00804     /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
00805        is selected during the I2S configuration phase, the Size parameter means the number
00806        of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
00807        frame is selected the Size parameter means the number of 16-bit data length. */
00808     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
00809       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
00810     {
00811       hi2s->TxXferSize = (Size << 1U);
00812       hi2s->TxXferCount = (Size << 1U);
00813       hi2s->RxXferSize = (Size << 1U);
00814       hi2s->RxXferCount = (Size << 1U);
00815     }
00816     else
00817     {
00818       hi2s->TxXferSize = Size;
00819       hi2s->TxXferCount = Size;
00820       hi2s->RxXferSize = Size;
00821       hi2s->RxXferCount = Size;
00822     }
00823
00824     /* Process Locked */
00825     __HAL_LOCK(hi2s);
00826
00827     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00828
00829     /* Set the I2S State busy TX/RX */
00830     hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
00831
00832     /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
00833     if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
00834     {
00835       /* Prepare the First Data before enabling the I2S */
00836       if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
00837       {
00838         hi2s->Instance->DR = (*pTxData++);
00839         hi2s->TxXferCount--;
00840       }
00841
00842       /* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction
00843       to avoid the clock de-synchronization between Master and Slave. */
00844       if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00845       {
00846         /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
00847         __HAL_I2SEXT_ENABLE(hi2s);
00848
00849         /* Enable I2Sx peripheral */
00850         __HAL_I2S_ENABLE(hi2s);
00851       }
00852
00853       while(hi2s->RxXferCount > 0U)
00854       {
00855         /* Wait until TXE flag is set */
00856         if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
00857         {
00858           /* Set the error code and execute error callback*/
00859           hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
00860           HAL_I2S_ErrorCallback(hi2s);
00861           return HAL_TIMEOUT;
00862         }
00863
00864         if (hi2s->TxXferCount > 0U)
00865         {
00866           /* Check if an underrun occurs */
00867           if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
00868           {
00869             /* Set the I2S State ready */
00870             hi2s->State = HAL_I2S_STATE_READY;
00871
00872             /* Process Unlocked */
00873             __HAL_UNLOCK(hi2s);
00874
00875             /* Set the error code and execute error callback*/
00876             hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
00877             HAL_I2S_ErrorCallback(hi2s);
00878
00879             return HAL_ERROR;
00880           }
00881
00882           hi2s->Instance->DR = (*pTxData++);
00883           hi2s->TxXferCount--;
00884         }
00885
00886         /* Wait until RXNE flag is set */
00887         if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
00888         {
00889           /* Set the error code and execute error callback*/
00890           hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
00891           HAL_I2S_ErrorCallback(hi2s);
00892           return HAL_TIMEOUT;
00893         }
00894
00895         /* Check if an overrun occurs */
00896         if(__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
00897         {
00898           /* Set the I2S State ready */
00899           hi2s->State = HAL_I2S_STATE_READY;
00900
00901           /* Process Unlocked */
00902           __HAL_UNLOCK(hi2s);
00903
00904           /* Set the error code and execute error callback*/
00905           hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
00906           HAL_I2S_ErrorCallback(hi2s);
00907
00908           return HAL_ERROR;
00909         }
00910
00911         (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
00912         hi2s->RxXferCount--;
00913       }
00914     }
00915     /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
00916     else
00917     {
00918       /* Prepare the First Data before enabling the I2S */
00919       I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
00920       hi2s->TxXferCount--;
00921
00922       /* Check if the I2S is already enabled */
00923       if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00924       {
00925         /* Enable I2S peripheral before the I2Sext*/
00926         __HAL_I2S_ENABLE(hi2s);
00927
00928         /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
00929         __HAL_I2SEXT_ENABLE(hi2s);
00930       }
00931
00932       /* Check if Master Receiver mode is selected */
00933       if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
00934       {
00935         /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
00936         access to the SPI_SR register. */
00937         __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00938       }
00939
00940       while(hi2s->RxXferCount > 0U)
00941       {
00942         /* Wait until TXE flag is set */
00943         if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
00944         {
00945           /* Set the error code and execute error callback*/
00946           hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
00947           HAL_I2S_ErrorCallback(hi2s);
00948           return HAL_TIMEOUT;
00949         }
00950
00951         if (hi2s->TxXferCount > 0U)
00952         {
00953           /* Check if an underrun occurs */
00954           if(__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
00955           {
00956             /* Set the I2S State ready */
00957             hi2s->State = HAL_I2S_STATE_READY;
00958
00959             /* Process Unlocked */
00960             __HAL_UNLOCK(hi2s);
00961
00962             /* Set the error code and execute error callback*/
00963             hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
00964             HAL_I2S_ErrorCallback(hi2s);
00965
00966             return HAL_ERROR;
00967           }
00968
00969           I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
00970           hi2s->TxXferCount--;
00971         }
00972
00973         /* Wait until RXNE flag is set */
00974         if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
00975         {
00976           /* Set the error code and execute error callback*/
00977           hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
00978           HAL_I2S_ErrorCallback(hi2s);
00979           return HAL_TIMEOUT;
00980         }
00981
00982         /* Check if an overrun occurs */
00983         if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
00984         {
00985           /* Set the I2S State ready */
00986           hi2s->State = HAL_I2S_STATE_READY;
00987
00988           /* Process Unlocked */
00989           __HAL_UNLOCK(hi2s);
00990
00991           /* Set the error code and execute error callback*/
00992           hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
00993           HAL_I2S_ErrorCallback(hi2s);
00994
00995           return HAL_ERROR;
00996         }
00997
00998         (*pRxData++) = hi2s->Instance->DR;
00999         hi2s->RxXferCount--;
01000       }
01001     }
01002
01003     /* Set the I2S State ready */
01004     hi2s->State = HAL_I2S_STATE_READY;
01005
01006     /* Process Unlocked */
01007     __HAL_UNLOCK(hi2s);
01008
01009     return HAL_OK;
01010   }
01011   else
01012   {
01013     return HAL_BUSY;
01014   }
01015 }
01016
01017 /**
01018   * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
01019   * @param hi2s: I2S handle
01020   * @param pTxData a 16-bit pointer to the Transmit data buffer.
01021   * @param pRxData a 16-bit pointer to the Receive data buffer.
01022   * @param Size number of data sample to be sent:
01023   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
01024   *       configuration phase, the Size parameter means the number of 16-bit data length
01025   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
01026   *       the Size parameter means the number of 16-bit data length.
01027   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
01028   *       between Master and Slave(example: audio streaming).
01029   * @retval HAL status
01030   */
01031 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
01032 {
01033   if(hi2s->State == HAL_I2S_STATE_READY)
01034   {
01035     if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
01036     {
01037       return  HAL_ERROR;
01038     }
01039
01040     hi2s->pTxBuffPtr = pTxData;
01041     hi2s->pRxBuffPtr = pRxData;
01042
01043     /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
01044        is selected during the I2S configuration phase, the Size parameter means the number
01045        of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
01046        frame is selected the Size parameter means the number of 16-bit data length. */
01047     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
01048       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
01049     {
01050       hi2s->TxXferSize = (Size << 1U);
01051       hi2s->TxXferCount = (Size << 1U);
01052       hi2s->RxXferSize = (Size << 1U);
01053       hi2s->RxXferCount = (Size << 1U);
01054     }
01055     else
01056     {
01057       hi2s->TxXferSize = Size;
01058       hi2s->TxXferCount = Size;
01059       hi2s->RxXferSize = Size;
01060       hi2s->RxXferCount = Size;
01061     }
01062
01063     /* Process Locked */
01064     __HAL_LOCK(hi2s);
01065
01066     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
01067     hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
01068
01069     /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
01070     if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
01071     {
01072       /* Enable I2Sext RXNE and ERR interrupts */
01073       __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01074
01075       /* Enable I2Sx TXE and ERR interrupts */
01076       __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01077
01078       /* Check if the I2S is already enabled */
01079       if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
01080       {
01081         if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
01082         {
01083           /* Prepare the First Data before enabling the I2S */
01084           if(hi2s->TxXferCount != 0U)
01085           {
01086             /* Transmit First data */
01087             hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
01088             hi2s->TxXferCount--;
01089
01090             if(hi2s->TxXferCount == 0U)
01091             {
01092               /* Disable TXE and ERR interrupt */
01093               __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01094
01095               if(hi2s->RxXferCount == 0U)
01096               {
01097                 /* Disable I2Sext RXNE and ERR interrupt */
01098                 __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR));
01099
01100                 hi2s->State = HAL_I2S_STATE_READY;
01101                 HAL_I2S_TxRxCpltCallback(hi2s);
01102               }
01103             }
01104           }
01105         }
01106         /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
01107         __HAL_I2SEXT_ENABLE(hi2s);
01108
01109         /* Enable I2Sx peripheral */
01110         __HAL_I2S_ENABLE(hi2s);
01111       }
01112     }
01113     /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
01114     else
01115     {
01116       /* Enable I2Sext TXE and ERR interrupts */
01117       __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01118
01119       /* Enable I2Sext RXNE and ERR interrupts */
01120       __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01121
01122       /* Check if the I2S is already enabled */
01123       if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
01124       {
01125         /* Prepare the First Data before enabling the I2S */
01126         if(hi2s->TxXferCount != 0U)
01127         {
01128           /* Transmit First data */
01129           I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
01130           hi2s->TxXferCount--;
01131
01132           if(hi2s->TxXferCount == 0U)
01133           {
01134             /* Disable I2Sext TXE and ERR interrupt */
01135             __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01136
01137             if(hi2s->RxXferCount == 0U)
01138             {
01139               /* Disable RXNE and ERR interrupt */
01140               __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR));
01141
01142               hi2s->State = HAL_I2S_STATE_READY;
01143               HAL_I2S_TxRxCpltCallback(hi2s);
01144             }
01145           }
01146         }
01147         /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
01148         __HAL_I2SEXT_ENABLE(hi2s);
01149
01150         /* Enable I2S peripheral */
01151         __HAL_I2S_ENABLE(hi2s);
01152       }
01153     }
01154     /* Process Unlocked */
01155     __HAL_UNLOCK(hi2s);
01156
01157     return HAL_OK;
01158   }
01159   else
01160   {
01161     return HAL_BUSY;
01162   }
01163 }
01164
01165 /**
01166   * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
01167   * @param hi2s: I2S handle
01168   * @param pTxData a 16-bit pointer to the Transmit data buffer.
01169   * @param pRxData a 16-bit pointer to the Receive data buffer.
01170   * @param Size number of data sample to be sent:
01171   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
01172   *       configuration phase, the Size parameter means the number of 16-bit data length
01173   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
01174   *       the Size parameter means the number of 16-bit data length.
01175   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
01176   *       between Master and Slave(example: audio streaming).
01177   * @retval HAL status
01178   */
01179 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
01180 {
01181   uint32_t *tmp;
01182
01183   if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
01184   {
01185     return  HAL_ERROR;
01186   }
01187
01188   if(hi2s->State == HAL_I2S_STATE_READY)
01189   {
01190     hi2s->pTxBuffPtr = pTxData;
01191     hi2s->pRxBuffPtr = pRxData;
01192
01193     /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
01194        is selected during the I2S configuration phase, the Size parameter means the number
01195        of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
01196        frame is selected the Size parameter means the number of 16-bit data length. */
01197     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
01198       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
01199     {
01200       hi2s->TxXferSize = (Size << 1U);
01201       hi2s->TxXferCount = (Size << 1U);
01202       hi2s->RxXferSize = (Size << 1U);
01203       hi2s->RxXferCount = (Size << 1U);
01204     }
01205     else
01206     {
01207       hi2s->TxXferSize = Size;
01208       hi2s->TxXferCount = Size;
01209       hi2s->RxXferSize = Size;
01210       hi2s->RxXferCount = Size;
01211     }
01212
01213     /* Process Locked */
01214     __HAL_LOCK(hi2s);
01215
01216     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
01217     hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
01218
01219     /* Set the I2S Rx DMA transfer complete callback */
01220     hi2s->hdmarx->XferCpltCallback = I2S_TxRxDMACplt;
01221
01222     /* Set the I2S Rx DMA Half transfer complete callback */
01223     hi2s->hdmarx->XferHalfCpltCallback = I2S_TxRxDMAHalfCplt;
01224
01225     /* Set the I2S Rx DMA error callback */
01226     hi2s->hdmarx->XferErrorCallback = I2S_TxRxDMAError;
01227
01228     /* Set the I2S Tx DMA transfer callbacks as NULL because the
01229     communication closing is performed in DMA reception callbacks */
01230     hi2s->hdmatx->XferCpltCallback = NULL;
01231     hi2s->hdmatx->XferHalfCpltCallback = NULL;
01232
01233     /* Set the I2S Tx DMA error callback */
01234     hi2s->hdmatx->XferErrorCallback = I2S_TxRxDMAError;
01235
01236     /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
01237     if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
01238     {
01239       /* Enable the Rx DMA Channel */
01240       tmp = (uint32_t*)&pRxData;
01241       HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
01242
01243       /* Enable Rx DMA Request */
01244       I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
01245
01246       /* Enable the Tx DMA Channel */
01247       tmp = (uint32_t*)&pTxData;
01248       HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
01249
01250       /* Enable Tx DMA Request */
01251       hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
01252
01253       /* Check if the I2S is already enabled */
01254       if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
01255       {
01256         /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
01257         __HAL_I2SEXT_ENABLE(hi2s);
01258
01259         /* Enable I2S peripheral after the I2Sext*/
01260         __HAL_I2S_ENABLE(hi2s);
01261       }
01262     }
01263     else
01264     {
01265       /* Check if Master Receiver mode is selected */
01266       if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
01267       {
01268         /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
01269         access to the SPI_SR register. */
01270         __HAL_I2S_CLEAR_OVRFLAG(hi2s);
01271       }
01272
01273       /* Enable the Tx DMA Channel */
01274       tmp = (uint32_t*)&pTxData;
01275       HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
01276
01277       /* Enable Tx DMA Request */
01278       I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
01279
01280       /* Enable the Rx DMA Channel */
01281       tmp = (uint32_t*)&pRxData;
01282       HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
01283
01284       /* Enable Rx DMA Request */
01285       hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
01286
01287       /* Check if the I2S is already enabled */
01288       if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
01289       {
01290         /* Enable I2Sext(transmitter) before enabling I2Sx peripheral */
01291         __HAL_I2SEXT_ENABLE(hi2s);
01292
01293         /* Enable I2S peripheral after the I2Sext*/
01294         __HAL_I2S_ENABLE(hi2s);
01295       }
01296     }
01297
01298     /* Process Unlocked */
01299     __HAL_UNLOCK(hi2s);
01300
01301     return HAL_OK;
01302   }
01303   else
01304   {
01305     return HAL_BUSY;
01306   }
01307 }
01308
01309 /**
01310   * @}
01311   */
01312
01313 /**
01314   * @}
01315   */
01316
01317 /** @addtogroup I2SEx_Private_Functions I2S Extended Private Functions
01318   * @{
01319   */
01320
01321 /**
01322   * @brief DMA I2S transmit receive process complete callback
01323   * @param hdma DMA handle
01324   * @retval None
01325   */
01326 static void I2S_TxRxDMACplt(DMA_HandleTypeDef *hdma)
01327 {
01328   I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01329
01330   /* DMA Normal Mode */
01331   if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
01332   {
01333     /* Disable Rx/Tx DMA Request */
01334     if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
01335     {
01336       hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
01337       I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
01338     }
01339     else
01340     {
01341       hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
01342       I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
01343     }
01344
01345     hi2s->RxXferCount = 0U;
01346     hi2s->TxXferCount = 0U;
01347
01348     hi2s->State = HAL_I2S_STATE_READY;
01349   }
01350
01351   HAL_I2S_TxRxCpltCallback(hi2s);
01352 }
01353
01354 static void I2S_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma)
01355 {
01356   I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01357
01358   HAL_I2S_TxRxHalfCpltCallback(hi2s);
01359 }
01360
01361 /**
01362   * @brief DMA I2S communication error callback
01363   * @param hdma : DMA handle
01364   * @retval None
01365   */
01366 static void I2S_TxRxDMAError(DMA_HandleTypeDef *hdma)
01367 {
01368   I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01369
01370   /* Disable Rx and Tx DMA Request */
01371   hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
01372   I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
01373
01374   hi2s->TxXferCount = 0U;
01375   hi2s->RxXferCount = 0U;
01376
01377   hi2s->State= HAL_I2S_STATE_READY;
01378
01379   /* Set the error code and execute error callback*/
01380   hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
01381   HAL_I2S_ErrorCallback(hi2s);
01382 }
01383
01384 /**
01385   * @brief Full-Duplex IT handler transmit function
01386   * @param hi2s: I2S handle
01387   * @param i2sUsed: indicate if I2Sx or I2Sx_ext is concerned
01388   * @retval None
01389   */
01390 static void I2S_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
01391 {
01392   if(i2sUsed == I2S_USE_I2S)
01393   {
01394     /* Transmit data */
01395     hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
01396     hi2s->TxXferCount--;
01397
01398     if(hi2s->TxXferCount == 0U)
01399     {
01400       /* Disable TXE and ERR interrupt */
01401       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01402
01403       if(hi2s->RxXferCount == 0U)
01404       {
01405         hi2s->State = HAL_I2S_STATE_READY;
01406         HAL_I2S_TxRxCpltCallback(hi2s);
01407       }
01408     }
01409   }
01410   else
01411   {
01412     /* Transmit data */
01413     I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
01414     hi2s->TxXferCount--;
01415
01416     if(hi2s->TxXferCount == 0U)
01417     {
01418       /* Disable I2Sext TXE and ERR interrupt */
01419       __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01420
01421       if(hi2s->RxXferCount == 0U)
01422       {
01423         hi2s->State = HAL_I2S_STATE_READY;
01424         HAL_I2S_TxRxCpltCallback(hi2s);
01425       }
01426     }
01427   }
01428 }
01429
01430 /**
01431   * @brief Full-Duplex IT handler receive function
01432   * @param hi2s: I2S handle
01433   * @param i2sUsed: indicate if I2Sx or I2Sx_ext is concerned
01434   * @retval None
01435   */
01436 static void I2S_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
01437 {
01438   if(i2sUsed == I2S_USE_I2S)
01439   {
01440     /* Receive data */
01441     (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
01442     hi2s->RxXferCount--;
01443
01444     if(hi2s->RxXferCount == 0U)
01445     {
01446       /* Disable RXNE and ERR interrupt */
01447       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01448
01449       if(hi2s->TxXferCount == 0U)
01450       {
01451         hi2s->State = HAL_I2S_STATE_READY;
01452         HAL_I2S_TxRxCpltCallback(hi2s);
01453       }
01454     }
01455   }
01456   else
01457   {
01458     /* Receive data */
01459     (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
01460     hi2s->RxXferCount--;
01461
01462     if(hi2s->RxXferCount == 0U)
01463     {
01464       /* Disable I2Sext RXNE and ERR interrupt */
01465       __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01466
01467       if(hi2s->TxXferCount == 0U)
01468       {
01469         hi2s->State = HAL_I2S_STATE_READY;
01470         HAL_I2S_TxRxCpltCallback(hi2s);
01471       }
01472     }
01473   }
01474 }
01475
01476 /**
01477   * @brief This function handles I2S Communication Timeout.
01478   * @param hi2s: I2S handle
01479   * @param Flag Flag checked
01480   * @param State Value of the flag expected
01481   * @param Timeout Duration of the timeout
01482   * @param i2sUsed: I2S instance reference
01483   * @retval HAL status
01484   */
01485 static HAL_StatusTypeDef I2S_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
01486                                                                  uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed)
01487 {
01488   uint32_t tickstart = HAL_GetTick();
01489
01490   if(i2sUsed == I2S_USE_I2S)
01491   {
01492     if(State == RESET)
01493     {
01494       /* Wait until flag is reset */
01495       while((__HAL_I2S_GET_FLAG(hi2s, Flag)) != RESET)
01496       {
01497         if(Timeout != HAL_MAX_DELAY)
01498         {
01499           if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
01500           {
01501             /* Set the I2S State ready */
01502             hi2s->State= HAL_I2S_STATE_READY;
01503
01504             /* Process Unlocked */
01505             __HAL_UNLOCK(hi2s);
01506
01507             return HAL_TIMEOUT;
01508           }
01509         }
01510       }
01511     }
01512     else /* State == SET */
01513     {
01514       /* Wait until flag is set */
01515       while((__HAL_I2S_GET_FLAG(hi2s, Flag)) != SET)
01516       {
01517         if(Timeout != HAL_MAX_DELAY)
01518         {
01519           if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
01520           {
01521             /* Set the I2S State ready */
01522             hi2s->State= HAL_I2S_STATE_READY;
01523
01524             /* Process Unlocked */
01525             __HAL_UNLOCK(hi2s);
01526
01527             return HAL_TIMEOUT;
01528           }
01529         }
01530       }
01531     }
01532   }
01533   else /* i2sUsed == I2S_USE_I2SEXT */
01534   {
01535     if(State == RESET)
01536     {
01537       /* Wait until flag is reset */
01538       while((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) != RESET)
01539       {
01540         if(Timeout != HAL_MAX_DELAY)
01541         {
01542           if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
01543           {
01544             /* Set the I2S State ready */
01545             hi2s->State= HAL_I2S_STATE_READY;
01546
01547             /* Process Unlocked */
01548             __HAL_UNLOCK(hi2s);
01549
01550             return HAL_TIMEOUT;
01551           }
01552         }
01553       }
01554     }
01555     else /* State == SET */
01556     {
01557       /* Wait until flag is set */
01558       while((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) != SET)
01559       {
01560         if(Timeout != HAL_MAX_DELAY)
01561         {
01562           if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
01563           {
01564             /* Set the I2S State ready */
01565             hi2s->State= HAL_I2S_STATE_READY;
01566
01567             /* Process Unlocked */
01568             __HAL_UNLOCK(hi2s);
01569
01570             return HAL_TIMEOUT;
01571           }
01572         }
01573       }
01574     }
01575   }
01576
01577   return HAL_OK;
01578 }
01579 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
01580
01581 /**
01582   * @}
01583   */
01584
01585 /**
01586   * @}
01587   */
01588
01589 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
01590        /* STM32F302xC || STM32F303xC || STM32F358xx || */
01591        /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
01592        /* STM32F373xC || STM32F378xx                   */
01593
01594 #endif /* HAL_I2S_MODULE_ENABLED */
01595
01596 /**
01597   * @}
01598   */
01599
01600 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_i2s_ex.h Source File

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stm32f3xx_hal_i2s_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_i2s_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2S HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_I2S_EX_H
00038 #define __STM32F3xx_HAL_I2S_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00045     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00046     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
00047     defined(STM32F373xC) || defined(STM32F378xx)
00048
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f3xx_hal_def.h"
00051
00052 /** @addtogroup STM32F3xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @addtogroup I2SEx I2SEx
00057   * @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /* Exported constants --------------------------------------------------------*/
00062 /* Exported macros ------------------------------------------------------------*/
00063 /** @defgroup I2SEx_Exported_Macros I2S Extended Exported Macros
00064   * @{
00065   */
00066 #if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
00067 #define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
00068
00069 /** @brief  Enable or disable the specified I2SExt peripheral.
00070   * @param  __HANDLE__ specifies the I2S Handle.
00071   * @retval None
00072   */
00073 #define __HAL_I2SEXT_ENABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE)
00074 #define __HAL_I2SEXT_DISABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
00075
00076 /** @brief  Enable or disable the specified I2SExt interrupts.
00077   * @param  __HANDLE__ specifies the I2S Handle.
00078   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
00079   *        This parameter can be one of the following values:
00080   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00081   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00082   *            @arg I2S_IT_ERR: Error interrupt enable
00083   * @retval None
00084   */
00085 #define __HAL_I2SEXT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 |= (__INTERRUPT__))
00086 #define __HAL_I2SEXT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 &= ~(__INTERRUPT__))
00087
00088 /** @brief  Checks if the specified I2SExt interrupt source is enabled or disabled.
00089   * @param  __HANDLE__ specifies the I2S Handle.
00090   *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
00091   * @param  __INTERRUPT__ specifies the I2S interrupt source to check.
00092   *          This parameter can be one of the following values:
00093   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00094   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00095   *            @arg I2S_IT_ERR: Error interrupt enable
00096   * @retval The new state of __IT__ (TRUE or FALSE).
00097   */
00098 #define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00099
00100 /** @brief  Checks whether the specified I2SExt flag is set or not.
00101   * @param  __HANDLE__ specifies the I2S Handle.
00102   * @param  __FLAG__ specifies the flag to check.
00103   *        This parameter can be one of the following values:
00104   *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
00105   *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
00106   *            @arg I2S_FLAG_UDR: Underrun flag
00107   *            @arg I2S_FLAG_OVR: Overrun flag
00108   *            @arg I2S_FLAG_FRE: Frame error flag
00109   *            @arg I2S_FLAG_CHSIDE: Channel Side flag
00110   *            @arg I2S_FLAG_BSY: Busy flag
00111   * @retval The new state of __FLAG__ (TRUE or FALSE).
00112   */
00113 #define __HAL_I2SEXT_GET_FLAG(__HANDLE__, __FLAG__) (((I2SxEXT((__HANDLE__)->Instance)->SR) & (__FLAG__)) == (__FLAG__))
00114
00115 /** @brief Clears the I2SExt OVR pending flag.
00116   * @param  __HANDLE__ specifies the I2S Handle.
00117   * @retval None
00118   */
00119 #define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{(I2SxEXT((__HANDLE__)->Instance)->DR;\
00120                                                   (I2SxEXT((__HANDLE__)->Instance)->SR;}while(0U)
00121 /** @brief Clears the I2SExt UDR pending flag.
00122   * @param  __HANDLE__ specifies the I2S Handle.
00123   * @retval None
00124   */
00125 #define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__)(I2SxEXT((__HANDLE__)->Instance)->SR)
00126 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
00127  /**
00128   * @}
00129   */
00130
00131
00132 /* Exported functions --------------------------------------------------------*/
00133 /* Initialization/de-initialization functions  ********************************/
00134 /** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
00135   * @{
00136   */
00137
00138 #if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
00139 /** @addtogroup I2SEx_Exported_Functions_Group1 I2S Extended Features Functions
00140   * @{
00141   */
00142
00143 /* Extended features functions ************************************************/
00144  /* Blocking mode: Polling */
00145 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout);
00146 /* Non-Blocking mode: Interrupt */
00147 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
00148 /* Non-Blocking mode: DMA */
00149 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
00150 /**
00151   * @}
00152   */
00153 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /**
00160   * @}
00161   */
00162
00163 /** @addtogroup I2S I2S
00164   * @{
00165   */
00166
00167 /** @addtogroup I2S_Exported_Functions I2S Exported Functions
00168   * @{
00169   */
00170 #if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
00171 /** @addtogroup  I2S_Exported_Functions_Group2 IO operation functions
00172   * @{
00173   */
00174 /* I2S IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00175 void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s);
00176 void HAL_I2S_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
00177 /* Callback used in non blocking modes (DMA only) */
00178 void HAL_I2S_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00179 /**
00180   * @}
00181   */
00182 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
00183
00184 /** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
00185   * @{
00186   */
00187 /* Peripheral Control and State functions  ************************************/
00188 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
00189 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
00190 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
00191
00192 /**
00193   * @}
00194   */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /**
00201   * @}
00202   */
00203
00204 /**
00205   * @}
00206   */
00207 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00208        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00209        /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
00210        /* STM32F373xC || STM32F378xx                   */
00211
00212 #ifdef __cplusplus
00213 }
00214 #endif
00215
00216
00217 #endif /* __STM32F3xx_HAL_I2S_EX_H */
00218
00219 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_irda.c Source File

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stm32f3xx_hal_irda.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_irda.c
00004   * @author  MCD Application Team
00005   * @brief   IRDA HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the IrDA (Infrared Data Association) Peripheral
00008   *          (IRDA)
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral State and Errors functions
00012   *           + Peripheral Control functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019     The IRDA HAL driver can be used as follows:
00020
00021     (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
00022     (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
00023         in setting the associated USART or UART in IRDA mode:
00024         (++) Enable the USARTx/UARTx interface clock.
00025         (++) USARTx/UARTx pins configuration:
00026             (+++) Enable the clock for the USARTx/UARTx GPIOs.
00027             (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
00028         (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
00029              and HAL_IRDA_Receive_IT() APIs):
00030             (+++) Configure the USARTx/UARTx interrupt priority.
00031             (+++) Enable the NVIC USARTx/UARTx IRQ handle.
00032             (+++) The specific IRDA interrupts (Transmission complete interrupt,
00033                   RXNE interrupt and Error Interrupts) will be managed using the macros
00034                   __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
00035
00036         (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
00037              and HAL_IRDA_Receive_DMA() APIs):
00038             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00039             (+++) Enable the DMAx interface clock.
00040             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00041             (+++) Configure the DMA Tx/Rx channel.
00042             (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
00043             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00044
00045     (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
00046         the normal or low power mode and the clock prescaler in the hirda handle Init structure.
00047
00048     (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
00049         (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
00050              by calling the customized HAL_IRDA_MspInit() API.
00051
00052          -@@- The specific IRDA interrupts (Transmission complete interrupt,
00053              RXNE interrupt and Error Interrupts) will be managed using the macros
00054              __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
00055
00056     (#) Three operation modes are available within this driver :
00057
00058      *** Polling mode IO operation ***
00059      =================================
00060      [..]
00061        (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
00062        (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
00063
00064      *** Interrupt mode IO operation ***
00065      ===================================
00066      [..]
00067        (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
00068        (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
00069             add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
00070        (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
00071        (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
00072             add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
00073        (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00074             add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
00075
00076      *** DMA mode IO operation ***
00077      ==============================
00078      [..]
00079        (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
00080        (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
00081             add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
00082        (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
00083             add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
00084        (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
00085        (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
00086             add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
00087        (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
00088             add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
00089        (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00090             add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
00091
00092      *** IRDA HAL driver macros list ***
00093      ====================================
00094      [..]
00095        Below the list of most used macros in IRDA HAL driver.
00096
00097        (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
00098        (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
00099        (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
00100        (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
00101        (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
00102        (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
00103        (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
00104
00105      [..]
00106        (@) You can refer to the IRDA HAL driver header file for more useful macros
00107
00108   @endverbatim
00109   ******************************************************************************
00110   * @attention
00111   *
00112   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00113   *
00114   * Redistribution and use in source and binary forms, with or without modification,
00115   * are permitted provided that the following conditions are met:
00116   *   1. Redistributions of source code must retain the above copyright notice,
00117   *      this list of conditions and the following disclaimer.
00118   *   2. Redistributions in binary form must reproduce the above copyright notice,
00119   *      this list of conditions and the following disclaimer in the documentation
00120   *      and/or other materials provided with the distribution.
00121   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00122   *      may be used to endorse or promote products derived from this software
00123   *      without specific prior written permission.
00124   *
00125   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00126   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00127   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00128   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00129   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00130   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00131   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00132   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00133   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00134   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00135   *
00136   ******************************************************************************
00137   */
00138
00139 /* Includes ------------------------------------------------------------------*/
00140 #include "stm32f3xx_hal.h"
00141
00142 /** @addtogroup STM32F3xx_HAL_Driver
00143   * @{
00144   */
00145
00146 /** @defgroup IRDA IRDA
00147   * @brief IRDA HAL module driver
00148   * @{
00149   */
00150
00151 #ifdef HAL_IRDA_MODULE_ENABLED
00152
00153 /* Private typedef -----------------------------------------------------------*/
00154 /* Private define ------------------------------------------------------------*/
00155 /** @defgroup IRDA_Private_Constants IRDA Private Constants
00156   * @{
00157   */
00158 #define IRDA_TEACK_REACK_TIMEOUT            1000                                   /*!< IRDA TX or RX enable acknowledge time-out value  */
00159 #define IRDA_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
00160                                    | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))  /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
00161 /**
00162   * @}
00163   */
00164
00165 /* Private macros ------------------------------------------------------------*/
00166 /* Private variables ---------------------------------------------------------*/
00167 /* Private function prototypes -----------------------------------------------*/
00168 /** @addtogroup IRDA_Private_Functions
00169   * @{
00170   */
00171 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
00172 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
00173 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00174 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
00175 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
00176 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00177 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
00178 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00179 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
00180 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
00181 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00182 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00183 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00184 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00185 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00186 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
00187 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
00188 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
00189 /**
00190   * @}
00191   */
00192
00193 /* Exported functions --------------------------------------------------------*/
00194
00195 /** @defgroup IRDA_Exported_Functions IRDA Exported Functions
00196   * @{
00197   */
00198
00199 /** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
00200   *  @brief    Initialization and Configuration functions
00201   *
00202 @verbatim
00203   ==============================================================================
00204               ##### Initialization and Configuration functions #####
00205   ==============================================================================
00206   [..]
00207   This subsection provides a set of functions allowing to initialize the USARTx
00208   in asynchronous IRDA mode.
00209   (+) For the asynchronous mode only these parameters can be configured:
00210       (++) Baud Rate
00211       (++) Word Length
00212       (++) Parity
00213       (++) Power mode
00214       (++) Prescaler setting
00215       (++) Receiver/transmitter modes
00216
00217   [..]
00218   The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
00219   (details for the procedures are available in reference manual).
00220
00221 @endverbatim
00222   * @{
00223   */
00224
00225 /*
00226   Additional remark:  If the parity is enabled, then the MSB bit of the data written
00227                       in the data register is transmitted but is changed by the parity bit.
00228                       According to device capability (support or not of 7-bit word length),
00229                       frame length is either defined by the M bit (8-bits or 9-bits)
00230                       or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
00231                       Possible IRDA frame formats are as listed in the following table:
00232
00233     Table 1. IRDA frame format.
00234     +-----------------------------------------------------------------------+
00235     |       M bit       |  PCE bit  |             IRDA frame                |
00236     |-------------------|-----------|---------------------------------------|
00237     |         0         |     0     |    | SB |    8-bit data   | STB |     |
00238     |-------------------|-----------|---------------------------------------|
00239     |         0         |     1     |    | SB | 7-bit data | PB | STB |     |
00240     |-------------------|-----------|---------------------------------------|
00241     |         1         |     0     |    | SB |    9-bit data   | STB |     |
00242     |-------------------|-----------|---------------------------------------|
00243     |         1         |     1     |    | SB | 8-bit data | PB | STB |     |
00244     +-----------------------------------------------------------------------+
00245     |  M1 bit |  M0 bit |  PCE bit  |             IRDA frame                |
00246     |---------|---------|-----------|---------------------------------------|
00247     |    0    |    0    |     0     |    | SB |    8 bit data   | STB |     |
00248     |---------|---------|-----------|---------------------------------------|
00249     |    0    |    0    |     1     |    | SB | 7 bit data | PB | STB |     |
00250     |---------|---------|-----------|---------------------------------------|
00251     |    0    |    1    |     0     |    | SB |    9 bit data   | STB |     |
00252     |---------|---------|-----------|---------------------------------------|
00253     |    0    |    1    |     1     |    | SB | 8 bit data | PB | STB |     |
00254     |---------|---------|-----------|---------------------------------------|
00255     |    1    |    0    |     0     |    | SB |    7 bit data   | STB |     |
00256     |---------|---------|-----------|---------------------------------------|
00257     |    1    |    0    |     1     |    | SB | 6 bit data | PB | STB |     |
00258     +-----------------------------------------------------------------------+
00259
00260 */
00261
00262 /**
00263   * @brief  Initialize the IRDA mode according to the specified
00264   *         parameters in the IRDA_InitTypeDef and initialize the associated handle.
00265   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00266   *               the configuration information for the specified IRDA module.
00267   * @retval HAL status
00268   */
00269 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
00270 {
00271   /* Check the IRDA handle allocation */
00272   if(hirda == NULL)
00273   {
00274     return HAL_ERROR;
00275   }
00276
00277   /* Check the USART/UART associated to the IRDA handle */
00278   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00279
00280   if(hirda->gState == HAL_IRDA_STATE_RESET)
00281   {
00282     /* Allocate lock resource and initialize it */
00283     hirda->Lock = HAL_UNLOCKED;
00284
00285     /* Init the low level hardware : GPIO, CLOCK */
00286     HAL_IRDA_MspInit(hirda);
00287   }
00288
00289   hirda->gState = HAL_IRDA_STATE_BUSY;
00290
00291   /* Disable the Peripheral to update the configuration registers */
00292   __HAL_IRDA_DISABLE(hirda);
00293
00294   /* Set the IRDA Communication parameters */
00295   if (IRDA_SetConfig(hirda) == HAL_ERROR)
00296   {
00297     return HAL_ERROR;
00298   }
00299
00300   /* In IRDA mode, the following bits must be kept cleared:
00301   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
00302   - SCEN and HDSEL bits in the USART_CR3 register.*/
00303   CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
00304   CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
00305
00306   /* set the UART/USART in IRDA mode */
00307   hirda->Instance->CR3 |= USART_CR3_IREN;
00308
00309   /* Enable the Peripheral */
00310   __HAL_IRDA_ENABLE(hirda);
00311
00312   /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
00313   return (IRDA_CheckIdleState(hirda));
00314 }
00315
00316 /**
00317   * @brief  DeInitialize the IRDA peripheral.
00318   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00319   *               the configuration information for the specified IRDA module.
00320   * @retval HAL status
00321   */
00322 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
00323 {
00324   /* Check the IRDA handle allocation */
00325   if(hirda == NULL)
00326   {
00327     return HAL_ERROR;
00328   }
00329
00330   /* Check the USART/UART associated to the IRDA handle */
00331   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00332
00333   hirda->gState = HAL_IRDA_STATE_BUSY;
00334
00335   /* DeInit the low level hardware */
00336   HAL_IRDA_MspDeInit(hirda);
00337   /* Disable the Peripheral */
00338   __HAL_IRDA_DISABLE(hirda);
00339
00340   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00341   hirda->gState    = HAL_IRDA_STATE_RESET;
00342   hirda->RxState   = HAL_IRDA_STATE_RESET;
00343
00344   /* Process Unlock */
00345   __HAL_UNLOCK(hirda);
00346
00347   return HAL_OK;
00348 }
00349
00350 /**
00351   * @brief  Initialize the IRDA MSP.
00352   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00353   *               the configuration information for the specified IRDA module.
00354   * @retval None
00355   */
00356 __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
00357 {
00358   /* Prevent unused argument(s) compilation warning */
00359   UNUSED(hirda);
00360
00361   /* NOTE: This function should not be modified, when the callback is needed,
00362            the HAL_IRDA_MspInit can be implemented in the user file
00363    */
00364 }
00365
00366 /**
00367   * @brief  DeInitialize the IRDA MSP.
00368   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00369   *               the configuration information for the specified IRDA module.
00370   * @retval None
00371   */
00372 __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
00373 {
00374   /* Prevent unused argument(s) compilation warning */
00375   UNUSED(hirda);
00376
00377   /* NOTE: This function should not be modified, when the callback is needed,
00378            the HAL_IRDA_MspDeInit can be implemented in the user file
00379    */
00380 }
00381
00382 /**
00383   * @}
00384   */
00385
00386 /** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
00387   *  @brief   IRDA Transmit and Receive functions
00388   *
00389 @verbatim
00390  ===============================================================================
00391                       ##### IO operation functions #####
00392  ===============================================================================
00393   [..]
00394     This subsection provides a set of functions allowing to manage the IRDA data transfers.
00395
00396   [..]
00397     IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
00398     on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
00399     is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
00400     While receiving data, transmission should be avoided as the data to be transmitted
00401     could be corrupted.
00402
00403     (#) There are two mode of transfer:
00404         (++) Blocking mode: the communication is performed in polling mode.
00405              The HAL status of all data processing is returned by the same function
00406              after finishing transfer.
00407         (++) Non-Blocking mode: the communication is performed using Interrupts
00408              or DMA, these API's return the HAL status.
00409              The end of the data processing will be indicated through the
00410              dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
00411              using DMA mode.
00412              The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
00413              will be executed respectively at the end of the Transmit or Receive process
00414              The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
00415
00416     (#) Blocking mode APIs are :
00417         (++) HAL_IRDA_Transmit()
00418         (++) HAL_IRDA_Receive()
00419
00420     (#) Non Blocking mode APIs with Interrupt are :
00421         (++) HAL_IRDA_Transmit_IT()
00422         (++) HAL_IRDA_Receive_IT()
00423         (++) HAL_IRDA_IRQHandler()
00424
00425     (#) Non Blocking mode functions with DMA are :
00426         (++) HAL_IRDA_Transmit_DMA()
00427         (++) HAL_IRDA_Receive_DMA()
00428         (++) HAL_IRDA_DMAPause()
00429         (++) HAL_IRDA_DMAResume()
00430         (++) HAL_IRDA_DMAStop()
00431
00432     (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
00433         (++) HAL_IRDA_TxHalfCpltCallback()
00434         (++) HAL_IRDA_TxCpltCallback()
00435         (++) HAL_IRDA_RxHalfCpltCallback()
00436         (++) HAL_IRDA_RxCpltCallback()
00437         (++) HAL_IRDA_ErrorCallback()
00438
00439     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00440         (++) HAL_IRDA_Abort()
00441         (++) HAL_IRDA_AbortTransmit()
00442         (++) HAL_IRDA_AbortReceive()
00443         (++) HAL_IRDA_Abort_IT()
00444         (++) HAL_IRDA_AbortTransmit_IT()
00445         (++) HAL_IRDA_AbortReceive_IT()
00446
00447     (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
00448         (++) HAL_IRDA_AbortCpltCallback()
00449         (++) HAL_IRDA_AbortTransmitCpltCallback()
00450         (++) HAL_IRDA_AbortReceiveCpltCallback()
00451
00452     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00453         Errors are handled as follows :
00454        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00455             to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
00456             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
00457             and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
00458             If user wants to abort it, Abort services should be called by user.
00459        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00460             This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
00461             Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
00462
00463 @endverbatim
00464   * @{
00465   */
00466
00467 /**
00468   * @brief  Send an amount of data in blocking mode.
00469   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00470   *               the configuration information for the specified IRDA module.
00471   * @param  pData Pointer to data buffer.
00472   * @param  Size Amount of data to be sent.
00473   * @param  Timeout Specify timeout value.
00474   * @retval HAL status
00475   */
00476 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00477 {
00478   uint16_t* tmp;
00479   uint32_t tickstart = 0U;
00480
00481   /* Check that a Tx process is not already ongoing */
00482   if(hirda->gState == HAL_IRDA_STATE_READY)
00483   {
00484     if((pData == NULL) || (Size == 0U))
00485     {
00486       return  HAL_ERROR;
00487     }
00488
00489     /* Process Locked */
00490     __HAL_LOCK(hirda);
00491
00492     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00493     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00494
00495     /* Init tickstart for timeout managment*/
00496     tickstart = HAL_GetTick();
00497
00498     hirda->TxXferSize = Size;
00499     hirda->TxXferCount = Size;
00500     while(hirda->TxXferCount > 0U)
00501     {
00502       hirda->TxXferCount--;
00503
00504       if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00505       {
00506         return HAL_TIMEOUT;
00507       }
00508       if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00509       {
00510         tmp = (uint16_t*) pData;
00511         hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
00512         pData += 2U;
00513       }
00514       else
00515       {
00516         hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
00517       }
00518     }
00519
00520     if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00521     {
00522       return HAL_TIMEOUT;
00523     }
00524
00525     /* At end of Tx process, restore hirda->gState to Ready */
00526     hirda->gState = HAL_IRDA_STATE_READY;
00527
00528     /* Process Unlocked */
00529     __HAL_UNLOCK(hirda);
00530
00531     return HAL_OK;
00532   }
00533   else
00534   {
00535     return HAL_BUSY;
00536   }
00537 }
00538
00539 /**
00540   * @brief  Receive an amount of data in blocking mode.
00541   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00542   *               the configuration information for the specified IRDA module.
00543   * @param  pData Pointer to data buffer.
00544   * @param  Size Amount of data to be received.
00545   * @param  Timeout Specify timeout value.
00546   * @retval HAL status
00547   */
00548 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00549 {
00550   uint16_t* tmp;
00551   uint16_t uhMask;
00552   uint32_t tickstart = 0U;
00553
00554   /* Check that a Rx process is not already ongoing */
00555   if(hirda->RxState == HAL_IRDA_STATE_READY)
00556   {
00557     if((pData == NULL) || (Size == 0U))
00558     {
00559       return  HAL_ERROR;
00560     }
00561
00562     /* Process Locked */
00563     __HAL_LOCK(hirda);
00564
00565     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00566     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00567
00568     /* Init tickstart for timeout managment*/
00569     tickstart = HAL_GetTick();
00570
00571     hirda->RxXferSize = Size;
00572     hirda->RxXferCount = Size;
00573
00574     /* Computation of the mask to apply to RDR register
00575        of the UART associated to the IRDA */
00576     IRDA_MASK_COMPUTATION(hirda);
00577     uhMask = hirda->Mask;
00578
00579     /* Check data remaining to be received */
00580     while(hirda->RxXferCount > 0U)
00581     {
00582       hirda->RxXferCount--;
00583
00584       if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00585       {
00586         return HAL_TIMEOUT;
00587       }
00588       if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00589       {
00590         tmp = (uint16_t*) pData ;
00591         *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
00592         pData +=2U;
00593       }
00594       else
00595       {
00596         *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
00597       }
00598     }
00599
00600     /* At end of Rx process, restore hirda->RxState to Ready */
00601     hirda->RxState = HAL_IRDA_STATE_READY;
00602
00603     /* Process Unlocked */
00604     __HAL_UNLOCK(hirda);
00605
00606     return HAL_OK;
00607   }
00608   else
00609   {
00610     return HAL_BUSY;
00611   }
00612 }
00613
00614 /**
00615   * @brief  Send an amount of data in interrupt mode.
00616   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00617   *               the configuration information for the specified IRDA module.
00618   * @param  pData Pointer to data buffer.
00619   * @param  Size Amount of data to be sent.
00620   * @retval HAL status
00621   */
00622 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00623 {
00624   /* Check that a Tx process is not already ongoing */
00625   if(hirda->gState == HAL_IRDA_STATE_READY)
00626   {
00627     if((pData == NULL) || (Size == 0U))
00628     {
00629       return HAL_ERROR;
00630     }
00631
00632     /* Process Locked */
00633     __HAL_LOCK(hirda);
00634
00635     hirda->pTxBuffPtr = pData;
00636     hirda->TxXferSize = Size;
00637     hirda->TxXferCount = Size;
00638
00639     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00640     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00641
00642     /* Process Unlocked */
00643     __HAL_UNLOCK(hirda);
00644
00645     /* Enable the IRDA Transmit Data Register Empty Interrupt */
00646     SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
00647
00648     return HAL_OK;
00649   }
00650   else
00651   {
00652     return HAL_BUSY;
00653   }
00654 }
00655
00656 /**
00657   * @brief  Receive an amount of data in interrupt mode.
00658   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00659   *               the configuration information for the specified IRDA module.
00660   * @param  pData Pointer to data buffer.
00661   * @param  Size Amount of data to be received.
00662   * @retval HAL status
00663   */
00664 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00665 {
00666   /* Check that a Rx process is not already ongoing */
00667   if(hirda->RxState == HAL_IRDA_STATE_READY)
00668   {
00669     if((pData == NULL) || (Size == 0U))
00670     {
00671       return HAL_ERROR;
00672     }
00673
00674     /* Process Locked */
00675     __HAL_LOCK(hirda);
00676
00677     hirda->pRxBuffPtr = pData;
00678     hirda->RxXferSize = Size;
00679     hirda->RxXferCount = Size;
00680
00681     /* Computation of the mask to apply to the RDR register
00682        of the UART associated to the IRDA */
00683     IRDA_MASK_COMPUTATION(hirda);
00684
00685     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00686     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00687
00688     /* Process Unlocked */
00689     __HAL_UNLOCK(hirda);
00690
00691     /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
00692     SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
00693
00694     /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
00695     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
00696
00697     return HAL_OK;
00698   }
00699   else
00700   {
00701     return HAL_BUSY;
00702   }
00703 }
00704
00705 /**
00706   * @brief  Send an amount of data in DMA mode.
00707   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00708   *               the configuration information for the specified IRDA module.
00709   * @param  pData pointer to data buffer.
00710   * @param  Size amount of data to be sent.
00711   * @retval HAL status
00712   */
00713 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00714 {
00715   /* Check if USART/UART instance associated to the IRDA handle supports continuous communication using DMA */
00716   assert_param(IS_UART_DMA_INSTANCE(hirda->Instance));
00717
00718   /* Check that a Tx process is not already ongoing */
00719   if(hirda->gState == HAL_IRDA_STATE_READY)
00720   {
00721     if((pData == NULL) || (Size == 0U))
00722     {
00723       return HAL_ERROR;
00724     }
00725
00726     /* Process Locked */
00727     __HAL_LOCK(hirda);
00728
00729     hirda->pTxBuffPtr = pData;
00730     hirda->TxXferSize = Size;
00731     hirda->TxXferCount = Size;
00732
00733     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00734     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00735
00736     /* Set the IRDA DMA transfer complete callback */
00737     hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
00738
00739     /* Set the IRDA DMA half transfer complete callback */
00740     hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
00741
00742     /* Set the DMA error callback */
00743     hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
00744
00745     /* Set the DMA abort callback */
00746     hirda->hdmatx->XferAbortCallback = NULL;
00747
00748     /* Enable the IRDA transmit DMA channel */
00749     HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size);
00750
00751     /* Clear the TC flag in the ICR register */
00752     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
00753
00754     /* Process Unlocked */
00755     __HAL_UNLOCK(hirda);
00756
00757     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00758        in the USART CR3 register */
00759     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00760
00761     return HAL_OK;
00762   }
00763   else
00764   {
00765     return HAL_BUSY;
00766   }
00767 }
00768
00769 /**
00770   * @brief  Receive an amount of data in DMA mode.
00771   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00772   *               the configuration information for the specified IRDA module.
00773   * @param  pData Pointer to data buffer.
00774   * @param  Size Amount of data to be received.
00775   * @note   When the IRDA parity is enabled (PCE = 1), the received data contains
00776   *         the parity bit (MSB position).
00777   * @retval HAL status
00778   */
00779 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00780 {
00781   /* Check if USART/UART instance associated to the IRDA handle supports continuous communication using DMA */
00782   assert_param(IS_UART_DMA_INSTANCE(hirda->Instance));
00783
00784   /* Check that a Rx process is not already ongoing */
00785   if(hirda->RxState == HAL_IRDA_STATE_READY)
00786   {
00787     if((pData == NULL) || (Size == 0U))
00788     {
00789       return HAL_ERROR;
00790     }
00791
00792     /* Process Locked */
00793     __HAL_LOCK(hirda);
00794
00795     hirda->pRxBuffPtr = pData;
00796     hirda->RxXferSize = Size;
00797
00798     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00799     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00800
00801     /* Set the IRDA DMA transfer complete callback */
00802     hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
00803
00804     /* Set the IRDA DMA half transfer complete callback */
00805     hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
00806
00807     /* Set the DMA error callback */
00808     hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
00809
00810     /* Set the DMA abort callback */
00811     hirda->hdmarx->XferAbortCallback = NULL;
00812
00813     /* Enable the DMA channel */
00814     HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size);
00815
00816     /* Process Unlocked */
00817     __HAL_UNLOCK(hirda);
00818
00819     /* Enable the UART Parity Error Interrupt */
00820     SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
00821
00822     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
00823     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
00824
00825     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00826        in the USART CR3 register */
00827     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00828
00829     return HAL_OK;
00830   }
00831   else
00832   {
00833     return HAL_BUSY;
00834   }
00835 }
00836
00837
00838 /**
00839   * @brief  Pause the DMA Transfer.
00840   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00841   *               the configuration information for the specified IRDA module.
00842   * @retval HAL status
00843   */
00844 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
00845 {
00846   /* Process Locked */
00847   __HAL_LOCK(hirda);
00848
00849   if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
00850       (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
00851   {
00852     /* Disable the IRDA DMA Tx request */
00853     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00854   }
00855   if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
00856       (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
00857   {
00858     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
00859     CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
00860     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
00861
00862     /* Disable the IRDA DMA Rx request */
00863     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00864   }
00865
00866   /* Process Unlocked */
00867   __HAL_UNLOCK(hirda);
00868
00869   return HAL_OK;
00870 }
00871
00872 /**
00873   * @brief  Resume the DMA Transfer.
00874   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00875   *               the configuration information for the specified UART module.
00876   * @retval HAL status
00877   */
00878 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
00879 {
00880   /* Process Locked */
00881   __HAL_LOCK(hirda);
00882
00883   if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
00884   {
00885     /* Enable the IRDA DMA Tx request */
00886     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00887   }
00888   if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
00889   {
00890     /* Clear the Overrun flag before resuming the Rx transfer*/
00891     __HAL_IRDA_CLEAR_OREFLAG(hirda);
00892
00893     /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
00894     SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
00895     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
00896
00897     /* Enable the IRDA DMA Rx request */
00898     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00899   }
00900
00901   /* Process Unlocked */
00902   __HAL_UNLOCK(hirda);
00903
00904   return HAL_OK;
00905 }
00906
00907 /**
00908   * @brief  Stop the DMA Transfer.
00909   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00910   *               the configuration information for the specified UART module.
00911   * @retval HAL status
00912   */
00913 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
00914 {
00915   /* The Lock is not implemented on this API to allow the user application
00916      to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
00917      HAL_IRDA_TxHalfCpltCallback() / HAL_IRDA_RxHalfCpltCallback():
00918      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
00919      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
00920      the stream and the corresponding call back is executed. */
00921
00922   /* Stop IRDA DMA Tx request if ongoing */
00923   if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
00924       (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
00925   {
00926     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00927
00928     /* Abort the IRDA DMA Tx channel */
00929     if(hirda->hdmatx != NULL)
00930     {
00931       HAL_DMA_Abort(hirda->hdmatx);
00932     }
00933
00934     IRDA_EndTxTransfer(hirda);
00935   }
00936
00937   /* Stop IRDA DMA Rx request if ongoing */
00938   if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
00939       (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
00940   {
00941     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00942
00943     /* Abort the IRDA DMA Rx channel */
00944     if(hirda->hdmarx != NULL)
00945     {
00946       HAL_DMA_Abort(hirda->hdmarx);
00947     }
00948
00949     IRDA_EndRxTransfer(hirda);
00950   }
00951
00952   return HAL_OK;
00953 }
00954
00955 /**
00956   * @brief  Abort ongoing transfers (blocking mode).
00957   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00958   *               the configuration information for the specified UART module.
00959   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
00960   *         This procedure performs following operations :
00961   *           - Disable IRDA Interrupts (Tx and Rx)
00962   *           - Disable the DMA transfer in the peripheral register (if enabled)
00963   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
00964   *           - Set handle State to READY
00965   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
00966   * @retval HAL status
00967 */
00968 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
00969 {
00970   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
00971   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
00972   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
00973
00974   /* Disable the IRDA DMA Tx request if enabled */
00975   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
00976   {
00977     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00978
00979     /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
00980     if(hirda->hdmatx != NULL)
00981     {
00982       /* Set the IRDA DMA Abort callback to Null.
00983          No call back execution at end of DMA abort procedure */
00984       hirda->hdmatx->XferAbortCallback = NULL;
00985
00986       HAL_DMA_Abort(hirda->hdmatx);
00987     }
00988   }
00989
00990   /* Disable the IRDA DMA Rx request if enabled */
00991   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
00992   {
00993     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00994
00995     /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
00996     if(hirda->hdmarx != NULL)
00997     {
00998       /* Set the IRDA DMA Abort callback to Null.
00999          No call back execution at end of DMA abort procedure */
01000       hirda->hdmarx->XferAbortCallback = NULL;
01001
01002       HAL_DMA_Abort(hirda->hdmarx);
01003     }
01004   }
01005
01006   /* Reset Tx and Rx transfer counters */
01007   hirda->TxXferCount = 0U;
01008   hirda->RxXferCount = 0U;
01009
01010   /* Clear the Error flags in the ICR register */
01011   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01012
01013   /* Restore hirda->gState and hirda->RxState to Ready */
01014   hirda->gState  = HAL_IRDA_STATE_READY;
01015   hirda->RxState = HAL_IRDA_STATE_READY;
01016
01017   /* Reset Handle ErrorCode to No Error */
01018   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01019
01020   return HAL_OK;
01021 }
01022
01023 /**
01024   * @brief  Abort ongoing Transmit transfer (blocking mode).
01025   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01026   *               the configuration information for the specified UART module.
01027   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01028   *         This procedure performs following operations :
01029   *           - Disable IRDA Interrupts (Tx)
01030   *           - Disable the DMA transfer in the peripheral register (if enabled)
01031   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01032   *           - Set handle State to READY
01033   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01034   * @retval HAL status
01035 */
01036 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
01037 {
01038   /* Disable TXEIE and TCIE interrupts */
01039   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01040
01041   /* Disable the IRDA DMA Tx request if enabled */
01042   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01043   {
01044     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01045
01046     /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
01047     if(hirda->hdmatx != NULL)
01048     {
01049       /* Set the IRDA DMA Abort callback to Null.
01050          No call back execution at end of DMA abort procedure */
01051       hirda->hdmatx->XferAbortCallback = NULL;
01052
01053       HAL_DMA_Abort(hirda->hdmatx);
01054     }
01055   }
01056
01057   /* Reset Tx transfer counter */
01058   hirda->TxXferCount = 0U;
01059
01060   /* Restore hirda->gState to Ready */
01061   hirda->gState = HAL_IRDA_STATE_READY;
01062
01063   return HAL_OK;
01064 }
01065
01066 /**
01067   * @brief  Abort ongoing Receive transfer (blocking mode).
01068   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01069   *               the configuration information for the specified UART module.
01070   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01071   *         This procedure performs following operations :
01072   *           - Disable IRDA Interrupts (Rx)
01073   *           - Disable the DMA transfer in the peripheral register (if enabled)
01074   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01075   *           - Set handle State to READY
01076   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01077   * @retval HAL status
01078 */
01079 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
01080 {
01081   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01082   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01083   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01084
01085   /* Disable the IRDA DMA Rx request if enabled */
01086   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01087   {
01088     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01089
01090     /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
01091     if(hirda->hdmarx != NULL)
01092     {
01093       /* Set the IRDA DMA Abort callback to Null.
01094          No call back execution at end of DMA abort procedure */
01095       hirda->hdmarx->XferAbortCallback = NULL;
01096
01097       HAL_DMA_Abort(hirda->hdmarx);
01098     }
01099   }
01100
01101   /* Reset Rx transfer counter */
01102   hirda->RxXferCount = 0U;
01103
01104   /* Clear the Error flags in the ICR register */
01105   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01106
01107   /* Restore hirda->RxState to Ready */
01108   hirda->RxState = HAL_IRDA_STATE_READY;
01109
01110   return HAL_OK;
01111 }
01112
01113 /**
01114   * @brief  Abort ongoing transfers (Interrupt mode).
01115   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01116   *               the configuration information for the specified UART module.
01117   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01118   *         This procedure performs following operations :
01119   *           - Disable IRDA Interrupts (Tx and Rx)
01120   *           - Disable the DMA transfer in the peripheral register (if enabled)
01121   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01122   *           - Set handle State to READY
01123   *           - At abort completion, call user abort complete callback
01124   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01125   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01126   * @retval HAL status
01127 */
01128 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
01129 {
01130   uint32_t abortcplt = 1U;
01131
01132   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01133   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
01134   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01135
01136   /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
01137      before any call to DMA Abort functions */
01138   /* DMA Tx Handle is valid */
01139   if(hirda->hdmatx != NULL)
01140   {
01141     /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
01142        Otherwise, set it to NULL */
01143     if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01144     {
01145       hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
01146     }
01147     else
01148     {
01149       hirda->hdmatx->XferAbortCallback = NULL;
01150     }
01151   }
01152   /* DMA Rx Handle is valid */
01153   if(hirda->hdmarx != NULL)
01154   {
01155     /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
01156        Otherwise, set it to NULL */
01157     if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01158     {
01159       hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
01160     }
01161     else
01162     {
01163       hirda->hdmarx->XferAbortCallback = NULL;
01164     }
01165   }
01166
01167   /* Disable the IRDA DMA Tx request if enabled */
01168   if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01169   {
01170     /* Disable DMA Tx at UART level */
01171     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01172
01173     /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
01174     if(hirda->hdmatx != NULL)
01175     {
01176       /* IRDA Tx DMA Abort callback has already been initialised :
01177          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01178
01179       /* Abort DMA TX */
01180       if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
01181       {
01182         hirda->hdmatx->XferAbortCallback = NULL;
01183       }
01184       else
01185       {
01186         abortcplt = 0U;
01187       }
01188     }
01189   }
01190
01191   /* Disable the IRDA DMA Rx request if enabled */
01192   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01193   {
01194     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01195
01196     /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
01197     if(hirda->hdmarx != NULL)
01198     {
01199       /* IRDA Rx DMA Abort callback has already been initialised :
01200          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01201
01202       /* Abort DMA RX */
01203       if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01204       {
01205         hirda->hdmarx->XferAbortCallback = NULL;
01206         abortcplt = 1U;
01207       }
01208       else
01209       {
01210         abortcplt = 0U;
01211       }
01212     }
01213   }
01214
01215   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01216   if (abortcplt == 1U)
01217   {
01218     /* Reset Tx and Rx transfer counters */
01219     hirda->TxXferCount = 0U;
01220     hirda->RxXferCount = 0U;
01221
01222     /* Reset errorCode */
01223     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01224
01225     /* Clear the Error flags in the ICR register */
01226     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01227
01228     /* Restore hirda->gState and hirda->RxState to Ready */
01229     hirda->gState  = HAL_IRDA_STATE_READY;
01230     hirda->RxState = HAL_IRDA_STATE_READY;
01231
01232     /* As no DMA to be aborted, call directly user Abort complete callback */
01233     HAL_IRDA_AbortCpltCallback(hirda);
01234   }
01235
01236   return HAL_OK;
01237 }
01238
01239 /**
01240   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01241   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01242   *               the configuration information for the specified UART module.
01243   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01244   *         This procedure performs following operations :
01245   *           - Disable IRDA Interrupts (Tx)
01246   *           - Disable the DMA transfer in the peripheral register (if enabled)
01247   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01248   *           - Set handle State to READY
01249   *           - At abort completion, call user abort complete callback
01250   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01251   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01252   * @retval HAL status
01253 */
01254 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
01255 {
01256   /* Disable TXEIE and TCIE interrupts */
01257   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01258
01259   /* Disable the IRDA DMA Tx request if enabled */
01260   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01261   {
01262     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01263
01264     /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
01265     if(hirda->hdmatx != NULL)
01266     {
01267       /* Set the IRDA DMA Abort callback :
01268          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01269       hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
01270
01271       /* Abort DMA TX */
01272       if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
01273       {
01274         /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
01275         hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
01276       }
01277     }
01278     else
01279     {
01280       /* Reset Tx transfer counter */
01281       hirda->TxXferCount = 0U;
01282
01283       /* Restore hirda->gState to Ready */
01284       hirda->gState = HAL_IRDA_STATE_READY;
01285
01286       /* As no DMA to be aborted, call directly user Abort complete callback */
01287       HAL_IRDA_AbortTransmitCpltCallback(hirda);
01288     }
01289   }
01290   else
01291   {
01292     /* Reset Tx transfer counter */
01293     hirda->TxXferCount = 0U;
01294
01295     /* Restore hirda->gState to Ready */
01296     hirda->gState = HAL_IRDA_STATE_READY;
01297
01298     /* As no DMA to be aborted, call directly user Abort complete callback */
01299     HAL_IRDA_AbortTransmitCpltCallback(hirda);
01300   }
01301
01302   return HAL_OK;
01303 }
01304
01305 /**
01306   * @brief  Abort ongoing Receive transfer (Interrupt mode).
01307   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01308   *               the configuration information for the specified UART module.
01309   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01310   *         This procedure performs following operations :
01311   *           - Disable IRDA Interrupts (Rx)
01312   *           - Disable the DMA transfer in the peripheral register (if enabled)
01313   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01314   *           - Set handle State to READY
01315   *           - At abort completion, call user abort complete callback
01316   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01317   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01318   * @retval HAL status
01319 */
01320 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
01321 {
01322   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01323   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01324   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01325
01326   /* Disable the IRDA DMA Rx request if enabled */
01327   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01328   {
01329     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01330
01331     /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
01332     if(hirda->hdmarx != NULL)
01333     {
01334       /* Set the IRDA DMA Abort callback :
01335          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01336       hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
01337
01338       /* Abort DMA RX */
01339       if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01340       {
01341         /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
01342         hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
01343       }
01344     }
01345     else
01346     {
01347       /* Reset Rx transfer counter */
01348       hirda->RxXferCount = 0U;
01349
01350       /* Clear the Error flags in the ICR register */
01351       __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01352
01353       /* Restore hirda->RxState to Ready */
01354       hirda->RxState = HAL_IRDA_STATE_READY;
01355
01356       /* As no DMA to be aborted, call directly user Abort complete callback */
01357       HAL_IRDA_AbortReceiveCpltCallback(hirda);
01358     }
01359   }
01360   else
01361   {
01362     /* Reset Rx transfer counter */
01363     hirda->RxXferCount = 0U;
01364
01365     /* Clear the Error flags in the ICR register */
01366     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01367
01368     /* Restore hirda->RxState to Ready */
01369     hirda->RxState = HAL_IRDA_STATE_READY;
01370
01371     /* As no DMA to be aborted, call directly user Abort complete callback */
01372     HAL_IRDA_AbortReceiveCpltCallback(hirda);
01373   }
01374
01375   return HAL_OK;
01376 }
01377
01378 /**
01379   * @brief  Handle IRDA interrupt request.
01380   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01381   *               the configuration information for the specified IRDA module.
01382   * @retval None
01383   */
01384 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
01385 {
01386   uint32_t isrflags   = READ_REG(hirda->Instance->ISR);
01387   uint32_t cr1its     = READ_REG(hirda->Instance->CR1);
01388   uint32_t cr3its;
01389   uint32_t errorflags;
01390
01391   /* If no error occurs */
01392   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
01393   if (errorflags == RESET)
01394   {
01395     /* IRDA in mode Receiver ---------------------------------------------------*/
01396     if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01397     {
01398       IRDA_Receive_IT(hirda);
01399       return;
01400     }
01401   }
01402
01403   /* If some errors occur */
01404   cr3its = READ_REG(hirda->Instance->CR3);
01405   if(   (errorflags != RESET)
01406      && (    ((cr3its & USART_CR3_EIE) != RESET)
01407           || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
01408   {
01409     /* IRDA parity error interrupt occurred -------------------------------------*/
01410     if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
01411     {
01412       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
01413
01414       hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
01415     }
01416
01417     /* IRDA frame error interrupt occurred --------------------------------------*/
01418     if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01419     {
01420       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
01421
01422       hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
01423     }
01424
01425     /* IRDA noise error interrupt occurred --------------------------------------*/
01426     if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01427     {
01428       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
01429
01430       hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
01431     }
01432
01433     /* IRDA Over-Run interrupt occurred -----------------------------------------*/
01434     if(((isrflags & USART_ISR_ORE) != RESET) &&
01435        (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
01436     {
01437       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
01438
01439       hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
01440     }
01441
01442     /* Call IRDA Error Call back function if need be --------------------------*/
01443     if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
01444     {
01445       /* IRDA in mode Receiver ---------------------------------------------------*/
01446       if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01447       {
01448         IRDA_Receive_IT(hirda);
01449       }
01450
01451       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
01452          consider error as blocking */
01453       if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) ||
01454           (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
01455       {
01456         /* Blocking error : transfer is aborted
01457            Set the IRDA state ready to be able to start again the process,
01458            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01459         IRDA_EndRxTransfer(hirda);
01460
01461         /* Disable the IRDA DMA Rx request if enabled */
01462         if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01463         {
01464           CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01465
01466           /* Abort the IRDA DMA Rx channel */
01467           if(hirda->hdmarx != NULL)
01468           {
01469             /* Set the IRDA DMA Abort callback :
01470                will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
01471             hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
01472
01473             /* Abort DMA RX */
01474             if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01475             {
01476               /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
01477               hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
01478             }
01479           }
01480           else
01481           {
01482             /* Call user error callback */
01483             HAL_IRDA_ErrorCallback(hirda);
01484           }
01485         }
01486         else
01487         {
01488           /* Call user error callback */
01489           HAL_IRDA_ErrorCallback(hirda);
01490         }
01491       }
01492       else
01493       {
01494         /* Non Blocking error : transfer could go on.
01495            Error is notified to user through user error callback */
01496         HAL_IRDA_ErrorCallback(hirda);
01497         hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01498       }
01499     }
01500     return;
01501
01502   } /* End if some error occurs */
01503
01504   /* IRDA in mode Transmitter ------------------------------------------------*/
01505   if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
01506   {
01507     IRDA_Transmit_IT(hirda);
01508     return;
01509   }
01510
01511   /* IRDA in mode Transmitter (transmission end) -----------------------------*/
01512   if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
01513   {
01514     IRDA_EndTransmit_IT(hirda);
01515     return;
01516   }
01517
01518 }
01519
01520 /**
01521   * @brief  Tx Transfer completed callback.
01522   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01523   *               the configuration information for the specified IRDA module.
01524   * @retval None
01525   */
01526 __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
01527 {
01528   /* Prevent unused argument(s) compilation warning */
01529   UNUSED(hirda);
01530
01531   /* NOTE : This function should not be modified, when the callback is needed,
01532             the HAL_IRDA_TxCpltCallback can be implemented in the user file.
01533    */
01534 }
01535
01536 /**
01537   * @brief  Tx Half Transfer completed callback.
01538   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01539   *               the configuration information for the specified USART module.
01540   * @retval None
01541   */
01542 __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
01543 {
01544   /* Prevent unused argument(s) compilation warning */
01545   UNUSED(hirda);
01546
01547   /* NOTE : This function should not be modified, when the callback is needed,
01548             the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
01549    */
01550 }
01551
01552 /**
01553   * @brief  Rx Transfer completed callback.
01554   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01555   *               the configuration information for the specified IRDA module.
01556   * @retval None
01557   */
01558 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
01559 {
01560   /* Prevent unused argument(s) compilation warning */
01561   UNUSED(hirda);
01562
01563   /* NOTE : This function should not be modified, when the callback is needed,
01564             the HAL_IRDA_RxCpltCallback can be implemented in the user file.
01565    */
01566 }
01567
01568 /**
01569   * @brief  Rx Half Transfer complete callback.
01570   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01571   *                the configuration information for the specified IRDA module.
01572   * @retval None
01573   */
01574 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
01575 {
01576   /* Prevent unused argument(s) compilation warning */
01577   UNUSED(hirda);
01578
01579   /* NOTE : This function should not be modified, when the callback is needed,
01580             the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
01581    */
01582 }
01583
01584 /**
01585   * @brief  IRDA error callback.
01586   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01587   *               the configuration information for the specified IRDA module.
01588   * @retval None
01589   */
01590 __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
01591 {
01592   /* Prevent unused argument(s) compilation warning */
01593   UNUSED(hirda);
01594
01595   /* NOTE : This function should not be modified, when the callback is needed,
01596             the HAL_IRDA_ErrorCallback can be implemented in the user file.
01597    */
01598 }
01599
01600 /**
01601   * @brief  IRDA Abort Complete callback.
01602   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01603   *               the configuration information for the specified IRDA module.
01604   * @retval None
01605   */
01606 __weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
01607 {
01608   /* Prevent unused argument(s) compilation warning */
01609   UNUSED(hirda);
01610
01611   /* NOTE : This function should not be modified, when the callback is needed,
01612             the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
01613    */
01614 }
01615
01616 /**
01617   * @brief  IRDA Abort Complete callback.
01618   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01619   *               the configuration information for the specified IRDA module.
01620   * @retval None
01621   */
01622 __weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
01623 {
01624   /* Prevent unused argument(s) compilation warning */
01625   UNUSED(hirda);
01626
01627   /* NOTE : This function should not be modified, when the callback is needed,
01628             the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
01629    */
01630 }
01631
01632 /**
01633   * @brief  IRDA Abort Receive Complete callback.
01634   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01635   *               the configuration information for the specified IRDA module.
01636   * @retval None
01637   */
01638 __weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
01639 {
01640   /* Prevent unused argument(s) compilation warning */
01641   UNUSED(hirda);
01642
01643   /* NOTE : This function should not be modified, when the callback is needed,
01644             the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
01645    */
01646 }
01647
01648 /**
01649   * @}
01650   */
01651
01652 /** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions
01653   *  @brief   IRDA State and Errors functions
01654   *
01655 @verbatim
01656   ==============================================================================
01657             ##### Peripheral State and Error functions #####
01658   ==============================================================================
01659   [..]
01660     This subsection provides a set of functions allowing to return the State of IrDA
01661     communication process and also return Peripheral Errors occurred during communication process
01662      (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
01663          of the IRDA peripheral handle.
01664      (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
01665          communication.
01666
01667 @endverbatim
01668   * @{
01669   */
01670
01671 /**
01672   * @brief  Return the IRDA handle state.
01673   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01674   *               the configuration information for the specified IRDA module.
01675   * @retval HAL state
01676   */
01677 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
01678 {
01679   /* Return IRDA handle state */
01680   uint32_t temp1= 0x00U, temp2 = 0x00U;
01681   temp1 = hirda->gState;
01682   temp2 = hirda->RxState;
01683
01684   return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
01685 }
01686
01687 /**
01688   * @brief  Return the IRDA handle error code.
01689   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01690   *               the configuration information for the specified IRDA module.
01691   * @retval IRDA Error Code
01692   */
01693 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
01694 {
01695   return hirda->ErrorCode;
01696 }
01697
01698 /**
01699   * @}
01700   */
01701
01702 /**
01703   * @}
01704   */
01705
01706 /** @defgroup IRDA_Private_Functions IRDA Private Functions
01707   * @{
01708   */
01709
01710 /**
01711   * @brief  Configure the IRDA peripheral.
01712   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01713   *               the configuration information for the specified IRDA module.
01714   * @retval HAL status
01715   */
01716 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
01717 {
01718   uint32_t tmpreg                     = 0x00000000U;
01719   IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
01720   HAL_StatusTypeDef ret               = HAL_OK;
01721
01722   /* Check the communication parameters */
01723   assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
01724   assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
01725   assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
01726   assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
01727   assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
01728   assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
01729
01730   /*-------------------------- USART CR1 Configuration -----------------------*/
01731   /* Configure the IRDA Word Length, Parity and transfer Mode:
01732      Set the M bits according to hirda->Init.WordLength value
01733      Set PCE and PS bits according to hirda->Init.Parity value
01734      Set TE and RE bits according to hirda->Init.Mode value */
01735   tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
01736
01737   MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
01738
01739   /*-------------------------- USART CR3 Configuration -----------------------*/
01740   MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
01741
01742   /*-------------------------- USART GTPR Configuration ----------------------*/
01743   MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
01744
01745   /*-------------------------- USART BRR Configuration -----------------------*/
01746   IRDA_GETCLOCKSOURCE(hirda, clocksource);
01747   switch (clocksource)
01748   {
01749     case IRDA_CLOCKSOURCE_PCLK1:
01750       hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
01751       break;
01752     case IRDA_CLOCKSOURCE_PCLK2:
01753       hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
01754       break;
01755     case IRDA_CLOCKSOURCE_HSI:
01756       hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
01757       break;
01758     case IRDA_CLOCKSOURCE_SYSCLK:
01759       hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
01760       break;
01761     case IRDA_CLOCKSOURCE_LSE:
01762       hirda->Instance->BRR = (uint16_t)((LSE_VALUE  + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
01763       break;
01764     case IRDA_CLOCKSOURCE_UNDEFINED:
01765     default:
01766       ret = HAL_ERROR;
01767       break;
01768   }
01769
01770   return ret;
01771 }
01772
01773 /**
01774   * @brief  Check the IRDA Idle State.
01775   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01776   *               the configuration information for the specified IRDA module.
01777   * @retval HAL status
01778   */
01779 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
01780 {
01781   uint32_t tickstart = 0U;
01782
01783   /* Initialize the IRDA ErrorCode */
01784   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01785
01786   /* Init tickstart for timeout managment*/
01787   tickstart = HAL_GetTick();
01788
01789   /* TEACK bits in ISR is checked only when available.
01790      Bit is defined and available only for UART instances supporting WakeUp from Stop Mode feature.
01791   */
01792   if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(hirda->Instance))
01793   {
01794     /* Check if the Transmitter is enabled */
01795     if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
01796     {
01797       /* Wait until TEACK flag is set */
01798       if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
01799       {
01800         /* Timeout occurred */
01801         return HAL_TIMEOUT;
01802       }
01803     }
01804   }
01805
01806   /* Check if the Receiver is enabled */
01807   if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
01808   {
01809     /* Wait until REACK flag is set */
01810     if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
01811     {
01812       /* Timeout Occured */
01813       return HAL_TIMEOUT;
01814     }
01815   }
01816
01817   /* Initialize the IRDA state*/
01818   hirda->gState  = HAL_IRDA_STATE_READY;
01819   hirda->RxState = HAL_IRDA_STATE_READY;
01820
01821   /* Process Unlocked */
01822   __HAL_UNLOCK(hirda);
01823
01824   return HAL_OK;
01825 }
01826
01827 /**
01828   * @brief  Handle IRDA Communication Timeout.
01829   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01830   *               the configuration information for the specified IRDA module.
01831   * @param  Flag Specifies the IRDA flag to check.
01832   * @param  Status the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
01833   * @param  Tickstart Tick start value
01834   * @param  Timeout Timeout duration
01835   * @retval HAL status
01836   */
01837 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
01838 {
01839   /* Wait until flag is set */
01840   while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
01841   {
01842     /* Check for the Timeout */
01843     if(Timeout != HAL_MAX_DELAY)
01844     {
01845       if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
01846       {
01847         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01848         CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
01849         CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01850
01851         hirda->gState  = HAL_IRDA_STATE_READY;
01852         hirda->RxState = HAL_IRDA_STATE_READY;
01853
01854         /* Process Unlocked */
01855         __HAL_UNLOCK(hirda);
01856
01857         return HAL_TIMEOUT;
01858       }
01859     }
01860   }
01861   return HAL_OK;
01862 }
01863
01864
01865 /**
01866   * @brief  End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
01867   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01868   *               the configuration information for the specified IRDA module.
01869   * @retval None
01870   */
01871 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
01872 {
01873   /* Disable TXEIE and TCIE interrupts */
01874   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01875
01876   /* At end of Tx process, restore hirda->gState to Ready */
01877   hirda->gState = HAL_IRDA_STATE_READY;
01878 }
01879
01880
01881 /**
01882   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
01883   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01884   *               the configuration information for the specified IRDA module.
01885   * @retval None
01886   */
01887 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
01888 {
01889   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01890   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01891   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01892
01893   /* At end of Rx process, restore hirda->RxState to Ready */
01894   hirda->RxState = HAL_IRDA_STATE_READY;
01895 }
01896
01897
01898 /**
01899   * @brief  DMA IRDA transmit process complete callback.
01900   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
01901   *              the configuration information for the specified DMA module.
01902   * @retval None
01903   */
01904 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01905 {
01906   IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
01907
01908   /* DMA Normal mode */
01909   if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
01910   {
01911     hirda->TxXferCount = 0U;
01912
01913     /* Disable the DMA transfer for transmit request by resetting the DMAT bit
01914        in the IRDA CR3 register */
01915     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01916
01917     /* Enable the IRDA Transmit Complete Interrupt */
01918     SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
01919   }
01920   /* DMA Circular mode */
01921   else
01922   {
01923     HAL_IRDA_TxCpltCallback(hirda);
01924   }
01925
01926 }
01927
01928 /**
01929   * @brief  DMA IRDA transmit process half complete callback.
01930   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
01931   *              the configuration information for the specified DMA module.
01932   * @retval None
01933   */
01934 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
01935 {
01936   IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
01937
01938   HAL_IRDA_TxHalfCpltCallback(hirda);
01939 }
01940
01941 /**
01942   * @brief  DMA IRDA receive process complete callback.
01943   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
01944   *               the configuration information for the specified DMA module.
01945   * @retval None
01946   */
01947 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01948 {
01949   IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
01950
01951   /* DMA Normal mode */
01952   if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
01953   {
01954     hirda->RxXferCount = 0U;
01955
01956     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01957     CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
01958     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01959
01960     /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
01961        in the IRDA CR3 register */
01962     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01963
01964     /* At end of Rx process, restore hirda->RxState to Ready */
01965     hirda->RxState = HAL_IRDA_STATE_READY;
01966   }
01967
01968   HAL_IRDA_RxCpltCallback(hirda);
01969 }
01970
01971 /**
01972   * @brief DMA IRDA receive process half complete callback.
01973   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
01974   *              the configuration information for the specified DMA module.
01975   * @retval None
01976   */
01977 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
01978 {
01979   IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
01980
01981   HAL_IRDA_RxHalfCpltCallback(hirda);
01982 }
01983
01984 /**
01985   * @brief  DMA IRDA communication error callback.
01986   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
01987   *              the configuration information for the specified DMA module.
01988   * @retval None
01989   */
01990 static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
01991 {
01992   IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
01993
01994   /* Stop IRDA DMA Tx request if ongoing */
01995   if (  (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
01996       &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) )
01997   {
01998     hirda->TxXferCount = 0U;
01999     IRDA_EndTxTransfer(hirda);
02000   }
02001
02002   /* Stop IRDA DMA Rx request if ongoing */
02003   if (  (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
02004       &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) )
02005   {
02006     hirda->RxXferCount = 0U;
02007     IRDA_EndRxTransfer(hirda);
02008   }
02009
02010   hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
02011   HAL_IRDA_ErrorCallback(hirda);
02012 }
02013
02014 /**
02015   * @brief  DMA IRDA communication abort callback, when initiated by HAL services on Error
02016   *         (To be called at end of DMA Abort procedure following error occurrence).
02017   * @param  hdma DMA handle.
02018   * @retval None
02019   */
02020 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02021 {
02022   IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
02023   hirda->RxXferCount = 0U;
02024   hirda->TxXferCount = 0U;
02025
02026   HAL_IRDA_ErrorCallback(hirda);
02027 }
02028
02029 /**
02030   * @brief  DMA IRDA Tx communication abort callback, when initiated by user
02031   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02032   * @note   When this callback is executed, User Abort complete call back is called only if no
02033   *         Abort still ongoing for Rx DMA Handle.
02034   * @param  hdma DMA handle.
02035   * @retval None
02036   */
02037 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02038 {
02039   IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
02040
02041   hirda->hdmatx->XferAbortCallback = NULL;
02042
02043   /* Check if an Abort process is still ongoing */
02044   if(hirda->hdmarx != NULL)
02045   {
02046     if(hirda->hdmarx->XferAbortCallback != NULL)
02047     {
02048       return;
02049     }
02050   }
02051
02052   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02053   hirda->TxXferCount = 0U;
02054   hirda->RxXferCount = 0U;
02055
02056   /* Reset errorCode */
02057   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02058
02059   /* Clear the Error flags in the ICR register */
02060   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02061
02062   /* Restore hirda->gState and hirda->RxState to Ready */
02063   hirda->gState  = HAL_IRDA_STATE_READY;
02064   hirda->RxState = HAL_IRDA_STATE_READY;
02065
02066   /* Call user Abort complete callback */
02067   HAL_IRDA_AbortCpltCallback(hirda);
02068 }
02069
02070
02071 /**
02072   * @brief  DMA IRDA Rx communication abort callback, when initiated by user
02073   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02074   * @note   When this callback is executed, User Abort complete call back is called only if no
02075   *         Abort still ongoing for Tx DMA Handle.
02076   * @param  hdma DMA handle.
02077   * @retval None
02078   */
02079 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02080 {
02081   IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
02082
02083   hirda->hdmarx->XferAbortCallback = NULL;
02084
02085   /* Check if an Abort process is still ongoing */
02086   if(hirda->hdmatx != NULL)
02087   {
02088     if(hirda->hdmatx->XferAbortCallback != NULL)
02089     {
02090       return;
02091     }
02092   }
02093
02094   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02095   hirda->TxXferCount = 0U;
02096   hirda->RxXferCount = 0U;
02097
02098   /* Reset errorCode */
02099   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02100
02101   /* Clear the Error flags in the ICR register */
02102   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02103
02104   /* Restore hirda->gState and hirda->RxState to Ready */
02105   hirda->gState  = HAL_IRDA_STATE_READY;
02106   hirda->RxState = HAL_IRDA_STATE_READY;
02107
02108   /* Call user Abort complete callback */
02109   HAL_IRDA_AbortCpltCallback(hirda);
02110 }
02111
02112
02113 /**
02114   * @brief  DMA IRDA Tx communication abort callback, when initiated by user by a call to
02115   *         HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
02116   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
02117   *         and leads to user Tx Abort Complete callback execution).
02118   * @param  hdma DMA handle.
02119   * @retval None
02120   */
02121 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02122 {
02123   IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
02124
02125   hirda->TxXferCount = 0U;
02126
02127   /* Restore hirda->gState to Ready */
02128   hirda->gState = HAL_IRDA_STATE_READY;
02129
02130   /* Call user Abort complete callback */
02131   HAL_IRDA_AbortTransmitCpltCallback(hirda);
02132 }
02133
02134 /**
02135   * @brief  DMA IRDA Rx communication abort callback, when initiated by user by a call to
02136   *         HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
02137   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
02138   *         and leads to user Rx Abort Complete callback execution).
02139   * @param  hdma DMA handle.
02140   * @retval None
02141   */
02142 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02143 {
02144   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02145
02146   hirda->RxXferCount = 0U;
02147
02148   /* Clear the Error flags in the ICR register */
02149   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02150
02151   /* Restore hirda->RxState to Ready */
02152   hirda->RxState = HAL_IRDA_STATE_READY;
02153
02154   /* Call user Abort complete callback */
02155   HAL_IRDA_AbortReceiveCpltCallback(hirda);
02156 }
02157
02158 /**
02159   * @brief  Send an amount of data in interrupt mode.
02160   * @note   Function is called under interruption only, once
02161   *         interruptions have been enabled by HAL_IRDA_Transmit_IT().
02162   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02163   *               the configuration information for the specified IRDA module.
02164   * @retval HAL status
02165   */
02166 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
02167 {
02168   uint16_t* tmp;
02169
02170   /* Check that a Tx process is ongoing */
02171   if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
02172   {
02173     if(hirda->TxXferCount == 0U)
02174     {
02175       /* Disable the IRDA Transmit Data Register Empty Interrupt */
02176       CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
02177
02178       /* Enable the IRDA Transmit Complete Interrupt */
02179       SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
02180
02181       return HAL_OK;
02182     }
02183     else
02184     {
02185       if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
02186       {
02187         tmp = (uint16_t*) hirda->pTxBuffPtr;
02188         hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
02189         hirda->pTxBuffPtr += 2U;
02190       }
02191       else
02192       {
02193         hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFFU);
02194       }
02195       hirda->TxXferCount--;
02196
02197       return HAL_OK;
02198     }
02199   }
02200   else
02201   {
02202     return HAL_BUSY;
02203   }
02204 }
02205
02206 /**
02207   * @brief  Wrap up transmission in non-blocking mode.
02208   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02209   *               the configuration information for the specified IRDA module.
02210   * @retval HAL status
02211   */
02212 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
02213 {
02214   /* Disable the IRDA Transmit Complete Interrupt */
02215   CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
02216
02217   /* Tx process is ended, restore hirda->gState to Ready */
02218   hirda->gState = HAL_IRDA_STATE_READY;
02219
02220   HAL_IRDA_TxCpltCallback(hirda);
02221
02222   return HAL_OK;
02223 }
02224
02225 /**
02226   * @brief  Receive an amount of data in interrupt mode.
02227   * @note   Function is called under interruption only, once
02228   *         interruptions have been enabled by HAL_IRDA_Receive_IT()
02229   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02230   *               the configuration information for the specified IRDA module.
02231   * @retval HAL status
02232   */
02233 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
02234 {
02235   uint16_t* tmp;
02236   uint16_t  uhMask = hirda->Mask;
02237   uint16_t  uhdata;
02238
02239   /* Check that a Rx process is ongoing */
02240   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
02241   {
02242     uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
02243     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
02244     {
02245       tmp = (uint16_t*) hirda->pRxBuffPtr ;
02246       *tmp = (uint16_t)(uhdata & uhMask);
02247       hirda->pRxBuffPtr +=2U;
02248     }
02249     else
02250     {
02251       *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
02252     }
02253
02254     if(--hirda->RxXferCount == 0U)
02255     {
02256       /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
02257       CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
02258
02259       /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
02260       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02261
02262       /* Rx process is completed, restore hirda->RxState to Ready */
02263       hirda->RxState = HAL_IRDA_STATE_READY;
02264
02265       HAL_IRDA_RxCpltCallback(hirda);
02266
02267       return HAL_OK;
02268     }
02269
02270     return HAL_OK;
02271   }
02272   else
02273   {
02274     /* Clear RXNE interrupt flag */
02275     __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
02276
02277     return HAL_BUSY;
02278   }
02279 }
02280
02281 /**
02282   * @}
02283   */
02284
02285 #endif /* HAL_IRDA_MODULE_ENABLED */
02286 /**
02287   * @}
02288   */
02289
02290 /**
02291   * @}
02292   */
02293
02294 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_irda.h Source File

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stm32f3xx_hal_irda.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_irda.h
00004   * @author  MCD Application Team
00005   * @brief   This file contains all the functions prototypes for the IRDA
00006   *          firmware library.
00007   ******************************************************************************
00008   * @attention
00009   *
00010   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00011   *
00012   * Redistribution and use in source and binary forms, with or without modification,
00013   * are permitted provided that the following conditions are met:
00014   *   1. Redistributions of source code must retain the above copyright notice,
00015   *      this list of conditions and the following disclaimer.
00016   *   2. Redistributions in binary form must reproduce the above copyright notice,
00017   *      this list of conditions and the following disclaimer in the documentation
00018   *      and/or other materials provided with the distribution.
00019   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00020   *      may be used to endorse or promote products derived from this software
00021   *      without specific prior written permission.
00022   *
00023   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00024   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00025   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00026   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00027   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00028   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00029   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00030   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00031   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00032   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00033   *
00034   ******************************************************************************
00035   */
00036
00037 /* Define to prevent recursive inclusion -------------------------------------*/
00038 #ifndef __STM32F3xx_HAL_IRDA_H
00039 #define __STM32F3xx_HAL_IRDA_H
00040
00041 #ifdef __cplusplus
00042  extern "C" {
00043 #endif
00044
00045 /* Includes ------------------------------------------------------------------*/
00046 #include "stm32f3xx_hal_def.h"
00047
00048 /** @addtogroup STM32F3xx_HAL_Driver
00049   * @{
00050   */
00051
00052 /** @addtogroup IRDA
00053   * @{
00054   */
00055
00056 /* Exported types ------------------------------------------------------------*/
00057 /** @defgroup IRDA_Exported_Types IRDA Exported Types
00058   * @{
00059   */
00060
00061 /**
00062   * @brief IRDA Init Structure definition
00063   */
00064 typedef struct
00065 {
00066   uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
00067                                            The baud rate register is computed using the following formula:
00068                                               Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
00069
00070   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00071                                            This parameter can be a value of @ref IRDAEx_Word_Length */
00072
00073   uint32_t Parity;                    /*!< Specifies the parity mode.
00074                                            This parameter can be a value of @ref IRDA_Parity
00075                                            @note When parity is enabled, the computed parity is inserted
00076                                                  at the MSB position of the transmitted data (9th bit when
00077                                                  the word length is set to 9 data bits; 8th bit when the
00078                                                  word length is set to 8 data bits). */
00079
00080   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00081                                            This parameter can be a value of @ref IRDA_Transfer_Mode */
00082
00083   uint8_t  Prescaler;                 /*!< Specifies the Prescaler value for dividing the UART/USART source clock
00084                                            to achieve low-power frequency.
00085                                            @note Prescaler value 0 is forbidden */
00086
00087   uint16_t PowerMode;                 /*!< Specifies the IRDA power mode.
00088                                            This parameter can be a value of @ref IRDA_Low_Power */
00089 }IRDA_InitTypeDef;
00090
00091 /**
00092   * @brief HAL IRDA State structures definition
00093   * @note  HAL IRDA State value is a combination of 2 different substates: gState and RxState.
00094   *        - gState contains IRDA state information related to global Handle management
00095   *          and also information related to Tx operations.
00096   *          gState value coding follow below described bitmap :
00097   *          b7-b6  Error information
00098   *             00 : No Error
00099   *             01 : (Not Used)
00100   *             10 : Timeout
00101   *             11 : Error
00102   *          b5     IP initilisation status
00103   *             0  : Reset (IP not initialized)
00104   *             1  : Init done (IP not initialized. HAL IRDA Init function already called)
00105   *          b4-b3  (not used)
00106   *             xx : Should be set to 00
00107   *          b2     Intrinsic process state
00108   *             0  : Ready
00109   *             1  : Busy (IP busy with some configuration or internal operations)
00110   *          b1     (not used)
00111   *             x  : Should be set to 0
00112   *          b0     Tx state
00113   *             0  : Ready (no Tx operation ongoing)
00114   *             1  : Busy (Tx operation ongoing)
00115   *        - RxState contains information related to Rx operations.
00116   *          RxState value coding follow below described bitmap :
00117   *          b7-b6  (not used)
00118   *             xx : Should be set to 00
00119   *          b5     IP initilisation status
00120   *             0  : Reset (IP not initialized)
00121   *             1  : Init done (IP not initialized)
00122   *          b4-b2  (not used)
00123   *            xxx : Should be set to 000
00124   *          b1     Rx state
00125   *             0  : Ready (no Rx operation ongoing)
00126   *             1  : Busy (Rx operation ongoing)
00127   *          b0     (not used)
00128   *             x  : Should be set to 0.
00129   */
00130 typedef enum
00131 {
00132   HAL_IRDA_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
00133                                                    Value is allowed for gState and RxState */
00134   HAL_IRDA_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
00135                                                    Value is allowed for gState and RxState */
00136   HAL_IRDA_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing
00137                                                    Value is allowed for gState only */
00138   HAL_IRDA_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
00139                                                    Value is allowed for gState only */
00140   HAL_IRDA_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
00141                                                    Value is allowed for RxState only */
00142   HAL_IRDA_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
00143                                                    Not to be used for neither gState nor RxState.
00144                                                    Value is result of combination (Or) between gState and RxState values */
00145   HAL_IRDA_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
00146                                                    Value is allowed for gState only */
00147   HAL_IRDA_STATE_ERROR             = 0xE0U    /*!< Error
00148                                                    Value is allowed for gState only */
00149 }HAL_IRDA_StateTypeDef;
00150
00151 /**
00152   * @brief IRDA clock sources definition
00153   */
00154 typedef enum
00155 {
00156   IRDA_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source     */
00157   IRDA_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source     */
00158   IRDA_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source       */
00159   IRDA_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source    */
00160   IRDA_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */
00161   IRDA_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */
00162 }IRDA_ClockSourceTypeDef;
00163
00164 /**
00165   * @brief  IRDA handle Structure definition
00166   */
00167 typedef struct
00168 {
00169   USART_TypeDef            *Instance;        /*!< IRDA registers base address        */
00170
00171   IRDA_InitTypeDef         Init;             /*!< IRDA communication parameters      */
00172
00173   uint8_t                  *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */
00174
00175   uint16_t                 TxXferSize;       /*!< IRDA Tx Transfer size              */
00176
00177   __IO uint16_t            TxXferCount;      /*!< IRDA Tx Transfer Counter           */
00178
00179   uint8_t                  *pRxBuffPtr;      /*!< Pointer to IRDA Rx transfer Buffer */
00180
00181   uint16_t                 RxXferSize;       /*!< IRDA Rx Transfer size              */
00182
00183   __IO uint16_t            RxXferCount;      /*!< IRDA Rx Transfer Counter           */
00184
00185   uint16_t                 Mask;             /*!< IRDA RX RDR register mask          */
00186
00187   DMA_HandleTypeDef        *hdmatx;          /*!< IRDA Tx DMA Handle parameters      */
00188
00189   DMA_HandleTypeDef        *hdmarx;          /*!< IRDA Rx DMA Handle parameters      */
00190
00191   HAL_LockTypeDef          Lock;             /*!< Locking object                     */
00192
00193   __IO HAL_IRDA_StateTypeDef    gState;      /*!< IRDA state information related to global Handle management
00194                                                   and also related to Tx operations.
00195                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00196
00197   __IO HAL_IRDA_StateTypeDef    RxState;     /*!< IRDA state information related to Rx operations.
00198                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00199
00200   __IO uint32_t            ErrorCode;        /*!< IRDA Error code
00201                                                   This parameter can be a value of @ref IRDA_Error */
00202
00203 }IRDA_HandleTypeDef;
00204
00205 /**
00206   * @brief  IRDA Configuration enumeration values definition
00207   */
00208 typedef enum
00209 {
00210   IRDA_BAUDRATE        = 0x00U,     /*!< IRDA Baud rate          */
00211   IRDA_PARITY          = 0x01U,     /*!< IRDA frame parity       */
00212   IRDA_WORDLENGTH      = 0x02U,     /*!< IRDA frame length       */
00213   IRDA_MODE            = 0x03U,     /*!< IRDA communication mode */
00214   IRDA_PRESCALER       = 0x04U,     /*!< IRDA prescaling         */
00215   IRDA_POWERMODE       = 0x05U      /*!< IRDA power mode         */
00216 }IRDA_ControlTypeDef;
00217
00218 /**
00219   * @}
00220   */
00221
00222 /* Exported constants --------------------------------------------------------*/
00223 /** @defgroup IRDA_Exported_Constants IRDA Exported Constants
00224   * @{
00225   */
00226
00227 /** @defgroup IRDA_Error IRDA Error
00228   * @{
00229   */
00230 #define HAL_IRDA_ERROR_NONE      (0x00000000U)    /*!< No error            */
00231 #define HAL_IRDA_ERROR_PE        (0x00000001U)    /*!< Parity error        */
00232 #define HAL_IRDA_ERROR_NE        (0x00000002U)    /*!< Noise error         */
00233 #define HAL_IRDA_ERROR_FE        (0x00000004U)    /*!< frame error         */
00234 #define HAL_IRDA_ERROR_ORE       (0x00000008U)    /*!< Overrun error       */
00235 #define HAL_IRDA_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error  */
00236 #define HAL_IRDA_ERROR_BUSY      (0x00000020U)    /*!< Busy Error          */
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup IRDA_Parity IRDA Parity
00242   * @{
00243   */
00244 #define IRDA_PARITY_NONE                    (0x00000000U)                               /*!< No parity   */
00245 #define IRDA_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)                   /*!< Even parity */
00246 #define IRDA_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))  /*!< Odd parity  */
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
00252   * @{
00253   */
00254 #define IRDA_MODE_RX                        ((uint32_t)USART_CR1_RE)                   /*!< RX mode        */
00255 #define IRDA_MODE_TX                        ((uint32_t)USART_CR1_TE)                   /*!< TX mode        */
00256 #define IRDA_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))   /*!< RX and TX mode */
00257 /**
00258   * @}
00259   */
00260
00261 /** @defgroup IRDA_Low_Power IRDA Low Power
00262   * @{
00263   */
00264 #define IRDA_POWERMODE_NORMAL               (0x00000000U)                /*!< IRDA normal power mode */
00265 #define IRDA_POWERMODE_LOWPOWER             ((uint32_t)USART_CR3_IRLP)   /*!< IRDA low power mode    */
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup IRDA_State IRDA State
00271   * @{
00272   */
00273 #define IRDA_STATE_DISABLE                  (0x00000000U)              /*!< IRDA disabled  */
00274 #define IRDA_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)   /*!< IRDA enabled   */
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup IRDA_Mode  IRDA Mode
00280   * @{
00281   */
00282 #define IRDA_MODE_DISABLE                   (0x00000000U)               /*!< Associated UART disabled in IRDA mode */
00283 #define IRDA_MODE_ENABLE                    ((uint32_t)USART_CR3_IREN)  /*!< Associated UART enabled in IRDA mode  */
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup IRDA_One_Bit  IRDA One Bit Sampling
00289   * @{
00290   */
00291 #define IRDA_ONE_BIT_SAMPLE_DISABLE         (0x00000000U)                /*!< One-bit sampling disabled */
00292 #define IRDA_ONE_BIT_SAMPLE_ENABLE          ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled  */
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup IRDA_DMA_Tx IRDA DMA Tx
00298   * @{
00299   */
00300 #define IRDA_DMA_TX_DISABLE                 (0x00000000U)                /*!< IRDA DMA TX disabled */
00301 #define IRDA_DMA_TX_ENABLE                  ((uint32_t)USART_CR3_DMAT)   /*!< IRDA DMA TX enabled  */
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup IRDA_DMA_Rx  IRDA DMA Rx
00307   * @{
00308   */
00309 #define IRDA_DMA_RX_DISABLE                 (0x00000000U)                /*!< IRDA DMA RX disabled */
00310 #define IRDA_DMA_RX_ENABLE                  ((uint32_t)USART_CR3_DMAR)   /*!< IRDA DMA RX enabled  */
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup IRDA_Request_Parameters IRDA Request Parameters
00316   * @{
00317   */
00318 #define IRDA_AUTOBAUD_REQUEST            ((uint32_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request      */
00319 #define IRDA_RXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request  */
00320 #define IRDA_TXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup IRDA_Flags IRDA Flags
00326   *        Elements values convention: 0xXXXX
00327   *           - 0xXXXX  : Flag mask in the ISR register
00328   * @{
00329   */
00330 #define IRDA_FLAG_REACK                     (0x00400000U)    /*!< IRDA Receive enable acknowledge flag  */
00331 #define IRDA_FLAG_TEACK                     (0x00200000U)    /*!< IRDA Transmit enable acknowledge flag */
00332 #define IRDA_FLAG_BUSY                      (0x00010000U)    /*!< IRDA Busy flag                        */
00333 #define IRDA_FLAG_ABRF                      (0x00008000U)    /*!< IRDA Auto baud rate flag              */
00334 #define IRDA_FLAG_ABRE                      (0x00004000U)    /*!< IRDA Auto baud rate error             */
00335 #define IRDA_FLAG_TXE                       (0x00000080U)    /*!< IRDA Transmit data register empty     */
00336 #define IRDA_FLAG_TC                        (0x00000040U)    /*!< IRDA Transmission complete            */
00337 #define IRDA_FLAG_RXNE                      (0x00000020U)    /*!< IRDA Read data register not empty     */
00338 #define IRDA_FLAG_ORE                       (0x00000008U)    /*!< IRDA Overrun error                    */
00339 #define IRDA_FLAG_NE                        (0x00000004U)    /*!< IRDA Noise error                      */
00340 #define IRDA_FLAG_FE                        (0x00000002U)    /*!< IRDA Framing error                    */
00341 #define IRDA_FLAG_PE                        (0x00000001U)    /*!< IRDA Parity error                     */
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
00347   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00348   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00349   *           - XX  : Interrupt source register (2bits)
00350   *                 - 01: CR1 register
00351   *                 - 10: CR2 register
00352   *                 - 11: CR3 register
00353   *           - ZZZZ  : Flag position in the ISR register(4bits)
00354   * @{
00355   */
00356 #define IRDA_IT_PE                          ((uint16_t)0x0028U)     /*!< IRDA Parity error interruption                 */
00357 #define IRDA_IT_TXE                         ((uint16_t)0x0727U)     /*!< IRDA Transmit data register empty interruption */
00358 #define IRDA_IT_TC                          ((uint16_t)0x0626U)     /*!< IRDA Transmission complete interruption        */
00359 #define IRDA_IT_RXNE                        ((uint16_t)0x0525U)     /*!< IRDA Read data register not empty interruption */
00360 #define IRDA_IT_IDLE                        ((uint16_t)0x0424U)     /*!< IRDA Idle interruption                         */
00361 #define IRDA_IT_ERR                         ((uint16_t)0x0060U)     /*!< IRDA Error interruption                        */
00362 #define IRDA_IT_ORE                         ((uint16_t)0x0300U)     /*!< IRDA Overrun error interruption                */
00363 #define IRDA_IT_NE                          ((uint16_t)0x0200U)     /*!< IRDA Noise error interruption                  */
00364 #define IRDA_IT_FE                          ((uint16_t)0x0100U)     /*!< IRDA Frame error interruption                  */
00365 /**
00366   * @}
00367   */
00368
00369 /** @defgroup IRDA_IT_CLEAR_Flags   IRDA Interruption Clear Flags
00370   * @{
00371   */
00372 #define IRDA_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
00373 #define IRDA_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
00374 #define IRDA_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag        */
00375 #define IRDA_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
00376 #define IRDA_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
00377 #define IRDA_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup IRDA_Interruption_Mask    IRDA interruptions flags mask
00383   * @{
00384   */
00385 #define IRDA_IT_MASK  ((uint16_t)0x001FU)                             /*!< IRDA Interruptions flags mask */
00386 /**
00387   * @}
00388   */
00389
00390 /**
00391  * @}
00392  */
00393
00394
00395 /* Exported macros -----------------------------------------------------------*/
00396 /** @defgroup IRDA_Exported_Macros IRDA Exported Macros
00397   * @{
00398   */
00399
00400 /** @brief  Reset IRDA handle state.
00401   * @param  __HANDLE__ IRDA handle.
00402   * @retval None
00403   */
00404 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00405                                                        (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
00406                                                        (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
00407                                                      } while(0U)
00408
00409 /** @brief  Flush the IRDA DR register.
00410   * @param  __HANDLE__ specifies the IRDA Handle.
00411   * @retval None
00412   */
00413 #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \
00414     do{                                                                    \
00415          SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
00416          SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
00417       } while(0U)
00418
00419 /** @brief  Clear the specified IRDA pending flag.
00420   * @param  __HANDLE__ specifies the IRDA Handle.
00421   * @param  __FLAG__ specifies the flag to check.
00422   *          This parameter can be any combination of the following values:
00423   *            @arg @ref IRDA_CLEAR_PEF
00424   *            @arg @ref IRDA_CLEAR_FEF
00425   *            @arg @ref IRDA_CLEAR_NEF
00426   *            @arg @ref IRDA_CLEAR_OREF
00427   *            @arg @ref IRDA_CLEAR_TCF
00428   *            @arg @ref IRDA_CLEAR_IDLEF
00429   * @retval None
00430   */
00431 #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00432
00433 /** @brief  Clear the IRDA PE pending flag.
00434   * @param  __HANDLE__ specifies the IRDA Handle.
00435   * @retval None
00436   */
00437 #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
00438
00439
00440 /** @brief  Clear the IRDA FE pending flag.
00441   * @param  __HANDLE__ specifies the IRDA Handle.
00442   * @retval None
00443   */
00444 #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
00445
00446 /** @brief  Clear the IRDA NE pending flag.
00447   * @param  __HANDLE__ specifies the IRDA Handle.
00448   * @retval None
00449   */
00450 #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
00451
00452 /** @brief  Clear the IRDA ORE pending flag.
00453   * @param  __HANDLE__ specifies the IRDA Handle.
00454   * @retval None
00455   */
00456 #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
00457
00458 /** @brief  Clear the IRDA IDLE pending flag.
00459   * @param  __HANDLE__ specifies the IRDA Handle.
00460   * @retval None
00461   */
00462 #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
00463
00464 /** @brief  Check whether the specified IRDA flag is set or not.
00465   * @param  __HANDLE__ specifies the IRDA Handle.
00466   * @param  __FLAG__ specifies the flag to check.
00467   *        This parameter can be one of the following values:
00468   *            @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
00469   *            @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
00470   *            @arg @ref IRDA_FLAG_BUSY  Busy flag
00471   *            @arg @ref IRDA_FLAG_ABRF  Auto Baud rate detection flag
00472   *            @arg @ref IRDA_FLAG_ABRE  Auto Baud rate detection error flag
00473   *            @arg @ref IRDA_FLAG_TXE   Transmit data register empty flag
00474   *            @arg @ref IRDA_FLAG_TC    Transmission Complete flag
00475   *            @arg @ref IRDA_FLAG_RXNE  Receive data register not empty flag
00476   *            @arg @ref IRDA_FLAG_ORE   OverRun Error flag
00477   *            @arg @ref IRDA_FLAG_NE    Noise Error flag
00478   *            @arg @ref IRDA_FLAG_FE    Framing Error flag
00479   *            @arg @ref IRDA_FLAG_PE    Parity Error flag
00480   * @retval The new state of __FLAG__ (TRUE or FALSE).
00481   */
00482 #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00483
00484
00485 /** @brief  Enable the specified IRDA interrupt.
00486   * @param  __HANDLE__ specifies the IRDA Handle.
00487   * @param  __INTERRUPT__ specifies the IRDA interrupt source to enable.
00488   *          This parameter can be one of the following values:
00489   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
00490   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
00491   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00492   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00493   *            @arg @ref IRDA_IT_PE   Parity Error interrupt
00494   *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00495   * @retval None
00496   */
00497 #define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00498                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00499                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
00500
00501 /** @brief  Disable the specified IRDA interrupt.
00502   * @param  __HANDLE__ specifies the IRDA Handle.
00503   * @param  __INTERRUPT__ specifies the IRDA interrupt source to disable.
00504   *          This parameter can be one of the following values:
00505   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
00506   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
00507   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00508   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00509   *            @arg @ref IRDA_IT_PE   Parity Error interrupt
00510   *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00511   * @retval None
00512   */
00513 #define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00514                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00515                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
00516
00517
00518 /** @brief  Check whether the specified IRDA interrupt has occurred or not.
00519   * @param  __HANDLE__ specifies the IRDA Handle.
00520   * @param  __IT__ specifies the IRDA interrupt source to check.
00521   *          This parameter can be one of the following values:
00522   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
00523   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
00524   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00525   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00526   *            @arg @ref IRDA_IT_ORE OverRun Error interrupt
00527   *            @arg @ref IRDA_IT_NE Noise Error interrupt
00528   *            @arg @ref IRDA_IT_FE Framing Error interrupt
00529   *            @arg @ref IRDA_IT_PE Parity Error interrupt
00530   * @retval The new state of __IT__ (TRUE or FALSE).
00531   */
00532 #define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
00533
00534 /** @brief  Check whether the specified IRDA interrupt source is enabled or not.
00535   * @param  __HANDLE__ specifies the IRDA Handle.
00536   * @param  __IT__ specifies the IRDA interrupt source to check.
00537   *          This parameter can be one of the following values:
00538   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
00539   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
00540   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00541   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00542   *            @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
00543   *            @arg @ref IRDA_IT_PE Parity Error interrupt
00544   * @retval The new state of __IT__ (TRUE or FALSE).
00545   */
00546 #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
00547                                                        (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
00548
00549
00550 /** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
00551   * @param  __HANDLE__ specifies the IRDA Handle.
00552   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
00553   *                       to clear the corresponding interrupt
00554   *          This parameter can be one of the following values:
00555   *            @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
00556   *            @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
00557   *            @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
00558   *            @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
00559   *            @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
00560   * @retval None
00561   */
00562 #define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00563
00564
00565 /** @brief  Set a specific IRDA request flag.
00566   * @param  __HANDLE__ specifies the IRDA Handle.
00567   * @param  __REQ__ specifies the request flag to set
00568   *          This parameter can be one of the following values:
00569   *            @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
00570   *            @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
00571   *            @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
00572   *
00573   * @retval None
00574   */
00575 #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00576
00577 /** @brief  Enable the IRDA one bit sample method.
00578   * @param  __HANDLE__ specifies the IRDA Handle.
00579   * @retval None
00580   */
00581 #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00582
00583 /** @brief  Disable the IRDA one bit sample method.
00584   * @param  __HANDLE__ specifies the IRDA Handle.
00585   * @retval None
00586   */
00587 #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00588
00589 /** @brief  Enable UART/USART associated to IRDA Handle.
00590   * @param  __HANDLE__ specifies the IRDA Handle.
00591   * @retval None
00592   */
00593 #define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00594
00595 /** @brief  Disable UART/USART associated to IRDA Handle.
00596   * @param  __HANDLE__ specifies the IRDA Handle.
00597   * @retval None
00598   */
00599 #define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00600
00601 /**
00602   * @}
00603   */
00604
00605 /* Private macros --------------------------------------------------------*/
00606 /** @defgroup IRDA_Private_Macros   IRDA Private Macros
00607   * @{
00608   */
00609
00610 /** @brief  Ensure that IRDA Baud rate is less or equal to maximum value.
00611   * @param  __BAUDRATE__ specifies the IRDA Baudrate set by the user.
00612   * @retval True or False
00613   */
00614 #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
00615
00616 /** @brief  Ensure that IRDA prescaler value is strictly larger than 0.
00617   * @param  __PRESCALER__ specifies the IRDA prescaler value set by the user.
00618   * @retval True or False
00619   */
00620 #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
00621
00622 /**
00623   * @brief Ensure that IRDA frame parity is valid.
00624   * @param __PARITY__ IRDA frame parity.
00625   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00626   */
00627 #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
00628                                     ((__PARITY__) == IRDA_PARITY_EVEN) || \
00629                                     ((__PARITY__) == IRDA_PARITY_ODD))
00630
00631 /**
00632   * @brief Ensure that IRDA communication mode is valid.
00633   * @param __MODE__ IRDA communication mode.
00634   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00635   */
00636 #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
00637
00638 /**
00639   * @brief Ensure that IRDA power mode is valid.
00640   * @param __MODE__ IRDA power mode.
00641   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00642   */
00643 #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
00644                                      ((__MODE__) == IRDA_POWERMODE_NORMAL))
00645
00646 /**
00647   * @brief Ensure that IRDA state is valid.
00648   * @param __STATE__ IRDA state mode.
00649   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00650   */
00651 #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
00652                                   ((__STATE__) == IRDA_STATE_ENABLE))
00653
00654 /**
00655   * @brief Ensure that IRDA associated UART/USART mode is valid.
00656   * @param __MODE__ IRDA associated UART/USART mode.
00657   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00658   */
00659 #define IS_IRDA_MODE(__MODE__)  (((__MODE__) == IRDA_MODE_DISABLE) || \
00660                                  ((__MODE__) == IRDA_MODE_ENABLE))
00661
00662 /**
00663   * @brief Ensure that IRDA sampling rate is valid.
00664   * @param __ONEBIT__ IRDA sampling rate.
00665   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
00666   */
00667 #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)      (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
00668                                                  ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
00669
00670 /**
00671   * @brief Ensure that IRDA DMA TX mode is valid.
00672   * @param __DMATX__ IRDA DMA TX mode.
00673   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
00674   */
00675 #define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
00676                                        ((__DMATX__) == IRDA_DMA_TX_ENABLE))
00677
00678 /**
00679   * @brief Ensure that IRDA DMA RX mode is valid.
00680   * @param __DMARX__ IRDA DMA RX mode.
00681   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
00682   */
00683 #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
00684                                    ((__DMARX__) == IRDA_DMA_RX_ENABLE))
00685
00686 /**
00687   * @brief Ensure that IRDA request is valid.
00688   * @param __PARAM__ IRDA request.
00689   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
00690   */
00691 #define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
00692                                               ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
00693                                               ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
00694 /**
00695  * @}
00696  */
00697
00698 /* Include IRDA HAL Extended module */
00699 #include "stm32f3xx_hal_irda_ex.h"
00700
00701 /* Exported functions --------------------------------------------------------*/
00702 /** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
00703   * @{
00704   */
00705
00706 /** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
00707   * @{
00708   */
00709
00710 /* Initialization and de-initialization functions  ****************************/
00711 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
00712 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
00713 void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
00714 void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
00715
00716 /**
00717   * @}
00718   */
00719
00720 /** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
00721   * @{
00722   */
00723
00724 /* IO operation functions *****************************************************/
00725 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00726 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00727 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00728 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00729 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00730 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00731 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
00732 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
00733 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
00734 /* Transfer Abort functions */
00735 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
00736 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
00737 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
00738 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
00739 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
00740 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
00741
00742 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
00743 void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
00744 void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
00745 void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00746 void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00747 void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
00748 void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda);
00749 void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda);
00750 void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda);
00751
00752 /**
00753   * @}
00754   */
00755
00756 /* Peripheral Control functions  ************************************************/
00757
00758 /** @addtogroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions
00759   * @{
00760   */
00761
00762 /* Peripheral State and Error functions ***************************************/
00763 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
00764 uint32_t              HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
00765
00766 /**
00767   * @}
00768   */
00769
00770 /**
00771   * @}
00772   */
00773
00774 /**
00775   * @}
00776   */
00777
00778 /**
00779   * @}
00780   */
00781
00782 #ifdef __cplusplus
00783 }
00784 #endif
00785
00786 #endif /* __STM32F3xx_HAL_IRDA_H */
00787
00788 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_irda_ex.h Source File

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stm32f3xx_hal_irda_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_irda_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IRDA HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_IRDA_EX_H
00038 #define __STM32F3xx_HAL_IRDA_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup IRDAEx
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /* Exported constants --------------------------------------------------------*/
00057 /** @defgroup IRDAEx_Exported_Constants IRDAEx Exported Constants
00058   * @{
00059   */
00060
00061 /** @defgroup IRDAEx_Word_Length IRDA Word Length
00062   * @{
00063   */
00064 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00065     defined(STM32F334x8)                                                 || \
00066     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00067 #define IRDA_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long frame */
00068 #define IRDA_WORDLENGTH_8B                  (0x00000000U)              /*!< 8-bit long frame */
00069 #define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long frame */
00070 #else
00071 #define IRDA_WORDLENGTH_8B                  (0x00000000U)              /*!< 8-bit long frame */
00072 #define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)    /*!< 9-bit long frame */
00073 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00074        /* STM32F334x8                               || */
00075        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00076 /**
00077   * @}
00078   */
00079
00080 /**
00081   * @}
00082   */
00083
00084 /* Exported macros -----------------------------------------------------------*/
00085 /* Exported functions --------------------------------------------------------*/
00086
00087 /* Private macros ------------------------------------------------------------*/
00088
00089 /** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
00090   * @{
00091   */
00092
00093 /** @brief  Report the IRDA clock source.
00094   * @param  __HANDLE__ specifies the IRDA Handle.
00095   * @param  __CLOCKSOURCE__ output variable.
00096   * @retval IRDA clocking source, written in __CLOCKSOURCE__.
00097   */
00098 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00099     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
00100 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00101   do {                                                        \
00102     if((__HANDLE__)->Instance == USART1)                      \
00103     {                                                         \
00104        switch(__HAL_RCC_GET_USART1_SOURCE())                  \
00105        {                                                      \
00106         case RCC_USART1CLKSOURCE_PCLK2:                       \
00107           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \
00108           break;                                              \
00109         case RCC_USART1CLKSOURCE_HSI:                         \
00110           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00111           break;                                              \
00112         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00113           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00114           break;                                              \
00115         case RCC_USART1CLKSOURCE_LSE:                         \
00116           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00117           break;                                              \
00118         default:                                              \
00119           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00120           break;                                              \
00121        }                                                      \
00122     }                                                         \
00123     else if((__HANDLE__)->Instance == USART2)                 \
00124     {                                                         \
00125        switch(__HAL_RCC_GET_USART2_SOURCE())                  \
00126        {                                                      \
00127         case RCC_USART2CLKSOURCE_PCLK1:                       \
00128           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00129           break;                                              \
00130         case RCC_USART2CLKSOURCE_HSI:                         \
00131           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00132           break;                                              \
00133         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00134           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00135           break;                                              \
00136         case RCC_USART2CLKSOURCE_LSE:                         \
00137           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00138           break;                                              \
00139         default:                                              \
00140           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00141           break;                                              \
00142        }                                                      \
00143     }                                                         \
00144     else if((__HANDLE__)->Instance == USART3)                 \
00145     {                                                         \
00146        switch(__HAL_RCC_GET_USART3_SOURCE())                  \
00147        {                                                      \
00148         case RCC_USART3CLKSOURCE_PCLK1:                       \
00149           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00150           break;                                              \
00151         case RCC_USART3CLKSOURCE_HSI:                         \
00152           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00153           break;                                              \
00154         case RCC_USART3CLKSOURCE_SYSCLK:                      \
00155           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00156           break;                                              \
00157         case RCC_USART3CLKSOURCE_LSE:                         \
00158           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00159           break;                                              \
00160         default:                                              \
00161           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00162           break;                                              \
00163        }                                                      \
00164     }                                                         \
00165     else if((__HANDLE__)->Instance == UART4)                  \
00166     {                                                         \
00167        switch(__HAL_RCC_GET_UART4_SOURCE())                   \
00168        {                                                      \
00169         case RCC_UART4CLKSOURCE_PCLK1:                        \
00170           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00171           break;                                              \
00172         case RCC_UART4CLKSOURCE_HSI:                          \
00173           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00174           break;                                              \
00175         case RCC_UART4CLKSOURCE_SYSCLK:                       \
00176           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00177           break;                                              \
00178         case RCC_UART4CLKSOURCE_LSE:                          \
00179           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00180           break;                                              \
00181         default:                                              \
00182           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00183           break;                                              \
00184        }                                                      \
00185     }                                                         \
00186     else if ((__HANDLE__)->Instance == UART5)                 \
00187     {                                                         \
00188        switch(__HAL_RCC_GET_UART5_SOURCE())                   \
00189        {                                                      \
00190         case RCC_UART5CLKSOURCE_PCLK1:                        \
00191           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00192           break;                                              \
00193         case RCC_UART5CLKSOURCE_HSI:                          \
00194           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00195           break;                                              \
00196         case RCC_UART5CLKSOURCE_SYSCLK:                       \
00197           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00198           break;                                              \
00199         case RCC_UART5CLKSOURCE_LSE:                          \
00200           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00201           break;                                              \
00202         default:                                              \
00203           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00204           break;                                              \
00205        }                                                      \
00206     }                                                         \
00207     else                                                      \
00208     {                                                         \
00209       (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;         \
00210     }                                                         \
00211   } while(0U)
00212 #elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00213       defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00214 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00215   do {                                                        \
00216     if((__HANDLE__)->Instance == USART1)                      \
00217     {                                                         \
00218        switch(__HAL_RCC_GET_USART1_SOURCE())                  \
00219        {                                                      \
00220         case RCC_USART1CLKSOURCE_PCLK1:                       \
00221           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00222           break;                                              \
00223         case RCC_USART1CLKSOURCE_HSI:                         \
00224           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00225           break;                                              \
00226         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00227           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00228           break;                                              \
00229         case RCC_USART1CLKSOURCE_LSE:                         \
00230           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00231           break;                                              \
00232         default:                                              \
00233           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00234           break;                                              \
00235        }                                                      \
00236     }                                                         \
00237     else if((__HANDLE__)->Instance == USART2)                 \
00238     {                                                         \
00239       (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;             \
00240     }                                                         \
00241     else if((__HANDLE__)->Instance == USART3)                 \
00242     {                                                         \
00243       (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;             \
00244     }                                                         \
00245     else                                                      \
00246     {                                                         \
00247       (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;         \
00248     }                                                         \
00249   } while(0U)
00250 #else
00251 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00252   do {                                                        \
00253     if((__HANDLE__)->Instance == USART1)                      \
00254     {                                                         \
00255        switch(__HAL_RCC_GET_USART1_SOURCE())                  \
00256        {                                                      \
00257         case RCC_USART1CLKSOURCE_PCLK2:                       \
00258           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \
00259           break;                                              \
00260         case RCC_USART1CLKSOURCE_HSI:                         \
00261           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00262           break;                                              \
00263         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00264           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00265           break;                                              \
00266         case RCC_USART1CLKSOURCE_LSE:                         \
00267           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00268           break;                                              \
00269         default:                                              \
00270           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00271           break;                                              \
00272        }                                                      \
00273     }                                                         \
00274     else if((__HANDLE__)->Instance == USART2)                 \
00275     {                                                         \
00276        switch(__HAL_RCC_GET_USART2_SOURCE())                  \
00277        {                                                      \
00278         case RCC_USART2CLKSOURCE_PCLK1:                       \
00279           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00280           break;                                              \
00281         case RCC_USART2CLKSOURCE_HSI:                         \
00282           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00283           break;                                              \
00284         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00285           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00286           break;                                              \
00287         case RCC_USART2CLKSOURCE_LSE:                         \
00288           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00289           break;                                              \
00290         default:                                              \
00291           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00292           break;                                              \
00293        }                                                      \
00294     }                                                         \
00295     else if((__HANDLE__)->Instance == USART3)                 \
00296     {                                                         \
00297        switch(__HAL_RCC_GET_USART3_SOURCE())                  \
00298        {                                                      \
00299         case RCC_USART3CLKSOURCE_PCLK1:                       \
00300           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00301           break;                                              \
00302         case RCC_USART3CLKSOURCE_HSI:                         \
00303           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00304           break;                                              \
00305         case RCC_USART3CLKSOURCE_SYSCLK:                      \
00306           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00307           break;                                              \
00308         case RCC_USART3CLKSOURCE_LSE:                         \
00309           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00310           break;                                              \
00311         default:                                              \
00312           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00313           break;                                              \
00314        }                                                      \
00315     }                                                         \
00316     else                                                      \
00317     {                                                         \
00318       (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;         \
00319     }                                                         \
00320   } while(0U)
00321 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00322        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00323
00324
00325 /** @brief  Compute the mask to apply to retrieve the received data
00326   *         according to the word length and to the parity bits activation.
00327   * @note   If PCE = 1, the parity bit is not included in the data extracted
00328   *         by the reception API().
00329   *         This masking operation is not carried out in the case of
00330   *         DMA transfers.
00331   * @param  __HANDLE__ specifies the IRDA Handle.
00332   * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
00333   */
00334 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00335     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
00336     defined(STM32F334x8)
00337 #define IRDA_MASK_COMPUTATION(__HANDLE__)                             \
00338   do {                                                                \
00339   if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)            \
00340   {                                                                   \
00341      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
00342      {                                                                \
00343         (__HANDLE__)->Mask = 0x01FFU ;                                \
00344      }                                                                \
00345      else                                                             \
00346      {                                                                \
00347         (__HANDLE__)->Mask = 0x00FFU ;                                \
00348      }                                                                \
00349   }                                                                   \
00350   else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)       \
00351   {                                                                   \
00352      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
00353      {                                                                \
00354         (__HANDLE__)->Mask = 0x00FFU ;                                \
00355      }                                                                \
00356      else                                                             \
00357      {                                                                \
00358         (__HANDLE__)->Mask = 0x007FU ;                                \
00359      }                                                                \
00360   }                                                                   \
00361   else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)       \
00362   {                                                                   \
00363      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
00364      {                                                                \
00365         (__HANDLE__)->Mask = 0x007FU ;                                \
00366      }                                                                \
00367      else                                                             \
00368      {                                                                \
00369         (__HANDLE__)->Mask = 0x003FU ;                                \
00370      }                                                                \
00371   }                                                                   \
00372 } while(0U)
00373 #else
00374 #define IRDA_MASK_COMPUTATION(__HANDLE__)                             \
00375   do {                                                                \
00376   if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)            \
00377   {                                                                   \
00378      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
00379      {                                                                \
00380         (__HANDLE__)->Mask = 0x01FFU ;                                \
00381      }                                                                \
00382      else                                                             \
00383      {                                                                \
00384         (__HANDLE__)->Mask = 0x00FFU ;                                \
00385      }                                                                \
00386   }                                                                   \
00387   else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)       \
00388   {                                                                   \
00389      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
00390      {                                                                \
00391         (__HANDLE__)->Mask = 0x00FFU ;                                \
00392      }                                                                \
00393      else                                                             \
00394      {                                                                \
00395         (__HANDLE__)->Mask = 0x007FU ;                                \
00396      }                                                                \
00397   }                                                                   \
00398 } while(0U)
00399 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00400        /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
00401        /* STM32F334x8                                  */
00402 /**
00403   * @brief Ensure that IRDA frame length is valid.
00404   * @param __LENGTH__ IRDA frame length.
00405   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00406   */
00407 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00408     defined(STM32F334x8)                                                 || \
00409     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00410 #define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
00411                                          ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
00412                                          ((__LENGTH__) == IRDA_WORDLENGTH_9B))
00413 #else
00414 #define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
00415                                          ((__LENGTH__) == IRDA_WORDLENGTH_9B))
00416 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00417        /* STM32F334x8                               || */
00418        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00419 /**
00420   * @}
00421   */
00422
00423 /* Exported functions --------------------------------------------------------*/
00424
00425 /**
00426   * @}
00427   */
00428
00429 /**
00430   * @}
00431   */
00432
00433 #ifdef __cplusplus
00434 }
00435 #endif
00436
00437 #endif /* __STM32F3xx_HAL_IRDA_EX_H */
00438
00439 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00440
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_iwdg.c Source File

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  • Src
stm32f3xx_hal_iwdg.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_iwdg.c
00004   * @author  MCD Application Team
00005   * @brief   IWDG HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Independent Watchdog (IWDG) peripheral:
00008   *           + Initialization and Start functions
00009   *           + IO operation functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                     ##### IWDG Generic features #####
00014   ==============================================================================
00015   [..]
00016     (+) The IWDG can be started by either software or hardware (configurable
00017         through option byte).
00018
00019     (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
00020         if the main clock fails.
00021
00022     (+) Once the IWDG is started, the LSI is forced ON and both can not be
00023         disabled. The counter starts counting down from the reset value (0xFFFU).
00024         When it reaches the end of count value (0x000U) a reset signal is
00025         generated (IWDG reset).
00026
00027     (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
00028         the IWDG_RLR value is reloaded in the counter and the watchdog reset is
00029         prevented.
00030
00031     (+) The IWDG is implemented in the VDD voltage domain that is still functional
00032         in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
00033         IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
00034         reset occurs.
00035
00036     (+) Debug mode : When the microcontroller enters debug mode (core halted),
00037         the IWDG counter either continues to work normally or stops, depending
00038         on DBG_IWDG_STOP configuration bit in DBG module, accessible through
00039         __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
00040
00041     [..] Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s
00042          The IWDG timeout may vary due to LSI frequency dispersion. STM32F3xx
00043          devices provide the capability to measure the LSI frequency (LSI clock
00044          connected internally to TIM16 CH1 input capture). The measured value
00045          can be used to have an IWDG timeout with an acceptable accuracy.
00046
00047                      ##### How to use this driver #####
00048   ==============================================================================
00049   [..]
00050     (#) Use IWDG using HAL_IWDG_Init() function to :
00051       (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
00052            clock is forced ON and IWDG counter starts downcounting.
00053       (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
00054            IWDG_WINR.
00055       (++) Configure the IWDG prescaler and counter reload value. This reload
00056            value will be loaded in the IWDG counter each time the watchdog is
00057            reloaded, then the IWDG will start counting down from this value.
00058       (++) wait for status flags to be reset"
00059       (++) Depending on window parameter:
00060         (+++) If Window Init parameter is same as Window register value,
00061              nothing more is done but reload counter value in order to exit
00062              function withy exact time base.
00063         (+++) Else modify Window register. This will automatically reload
00064              watchdog counter.
00065
00066     (#) Then the application program must refresh the IWDG counter at regular
00067         intervals during normal operation to prevent an MCU reset, using
00068         HAL_IWDG_Refresh() function.
00069
00070      *** IWDG HAL driver macros list ***
00071      ====================================
00072      [..]
00073        Below the list of most used macros in IWDG HAL driver:
00074       (+) __HAL_IWDG_START: Enable the IWDG peripheral
00075       (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
00076           the reload register
00077
00078   @endverbatim
00079   ******************************************************************************
00080   * @attention
00081   *
00082   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00083   *
00084   * Redistribution and use in source and binary forms, with or without modification,
00085   * are permitted provided that the following conditions are met:
00086   *   1. Redistributions of source code must retain the above copyright notice,
00087   *      this list of conditions and the following disclaimer.
00088   *   2. Redistributions in binary form must reproduce the above copyright notice,
00089   *      this list of conditions and the following disclaimer in the documentation
00090   *      and/or other materials provided with the distribution.
00091   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00092   *      may be used to endorse or promote products derived from this software
00093   *      without specific prior written permission.
00094   *
00095   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00096   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00097   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00098   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00099   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00100   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00101   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00102   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00103   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00104   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00105   *
00106   ******************************************************************************
00107   */
00108
00109 /* Includes ------------------------------------------------------------------*/
00110 #include "stm32f3xx_hal.h"
00111
00112 /** @addtogroup STM32F3xx_HAL_Driver
00113   * @{
00114   */
00115
00116 #ifdef HAL_IWDG_MODULE_ENABLED
00117 /** @addtogroup IWDG
00118   * @brief IWDG HAL module driver.
00119   * @{
00120   */
00121
00122 /* Private typedef -----------------------------------------------------------*/
00123 /* Private define ------------------------------------------------------------*/
00124 /** @defgroup IWDG_Private_Defines IWDG Private Defines
00125   * @{
00126   */
00127 /* Status register need 5 RC LSI divided by prescaler clock to be updated. With
00128    higher prescaler (256U), and according to HSI variation, we need to wait at
00129    least 6 cycles so 48 ms. */
00130 #define HAL_IWDG_DEFAULT_TIMEOUT            48u
00131 /**
00132   * @}
00133   */
00134
00135 /* Private macro -------------------------------------------------------------*/
00136 /* Private variables ---------------------------------------------------------*/
00137 /* Private function prototypes -----------------------------------------------*/
00138 /* Exported functions --------------------------------------------------------*/
00139
00140 /** @addtogroup IWDG_Exported_Functions
00141   * @{
00142   */
00143
00144 /** @addtogroup IWDG_Exported_Functions_Group1
00145  *  @brief    Initialization and Start functions.
00146  *
00147 @verbatim
00148  ===============================================================================
00149           ##### Initialization and Start functions #####
00150  ===============================================================================
00151  [..]  This section provides functions allowing to:
00152       (+) Initialize the IWDG according to the specified parameters in the
00153           IWDG_InitTypeDef of associated handle.
00154       (+) Manage Window option.
00155       (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
00156           is reloaded in order to exit function with correct time base.
00157
00158 @endverbatim
00159   * @{
00160   */
00161
00162 /**
00163   * @brief  Initialize the IWDG according to the specified parameters in the
00164   *         IWDG_InitTypeDef and start watchdog. Before exiting function,
00165   *         watchdog is refreshed in order to have correct time base.
00166   * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
00167   *                the configuration information for the specified IWDG module.
00168   * @retval HAL status
00169   */
00170 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
00171 {
00172   uint32_t tickstart;
00173
00174   /* Check the IWDG handle allocation */
00175   if(hiwdg == NULL)
00176   {
00177     return HAL_ERROR;
00178   }
00179
00180   /* Check the parameters */
00181   assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
00182   assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
00183   assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
00184   assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
00185
00186   /* Enable IWDG. LSI is turned on automaticaly */
00187   __HAL_IWDG_START(hiwdg);
00188
00189   /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
00190   0x5555 in KR */
00191   IWDG_ENABLE_WRITE_ACCESS(hiwdg);
00192
00193   /* Write to IWDG registers the Prescaler & Reload values to work with */
00194   hiwdg->Instance->PR = hiwdg->Init.Prescaler;
00195   hiwdg->Instance->RLR = hiwdg->Init.Reload;
00196
00197   /* Check pending flag, if previous update not done, return timeout */
00198   tickstart = HAL_GetTick();
00199
00200    /* Wait for register to be updated */
00201   while(hiwdg->Instance->SR != RESET)
00202   {
00203     if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
00204     {
00205       return HAL_TIMEOUT;
00206     }
00207   }
00208
00209   /* If window parameter is different than current value, modify window
00210   register */
00211   if(hiwdg->Instance->WINR != hiwdg->Init.Window)
00212   {
00213     /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
00214     even if window feature is disabled, Watchdog will be reloaded by writing
00215     windows register */
00216     hiwdg->Instance->WINR = hiwdg->Init.Window;
00217   }
00218   else
00219   {
00220     /* Reload IWDG counter with value defined in the reload register */
00221     __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00222   }
00223
00224   /* Return function status */
00225   return HAL_OK;
00226 }
00227
00228 /**
00229   * @}
00230   */
00231
00232
00233 /** @addtogroup IWDG_Exported_Functions_Group2
00234  *  @brief   IO operation functions
00235  *
00236 @verbatim
00237  ===============================================================================
00238                       ##### IO operation functions #####
00239  ===============================================================================
00240  [..]  This section provides functions allowing to:
00241       (+) Refresh the IWDG.
00242
00243 @endverbatim
00244   * @{
00245   */
00246
00247
00248 /**
00249   * @brief  Refresh the IWDG.
00250   * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
00251   *                the configuration information for the specified IWDG module.
00252   * @retval HAL status
00253   */
00254 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
00255 {
00256   /* Reload IWDG counter with value defined in the reload register */
00257   __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00258
00259   /* Return function status */
00260   return HAL_OK;
00261 }
00262
00263 /**
00264   * @}
00265   */
00266
00267 /**
00268   * @}
00269   */
00270
00271 #endif /* HAL_IWDG_MODULE_ENABLED */
00272 /**
00273   * @}
00274   */
00275
00276 /**
00277   * @}
00278   */
00279
00280 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_iwdg.h Source File

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stm32f3xx_hal_iwdg.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_iwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IWDG HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_IWDG_H
00038 #define __STM32F3xx_HAL_IWDG_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @defgroup IWDG IWDG
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /** @defgroup IWDG_Exported_Types IWDG Exported Types
00057   * @{
00058   */
00059
00060 /**
00061   * @brief  IWDG Init structure definition
00062   */
00063 typedef struct
00064 {
00065   uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
00066                             This parameter can be a value of @ref IWDG_Prescaler */
00067
00068   uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
00069                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFFU */
00070
00071   uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.
00072                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFFU */
00073
00074 } IWDG_InitTypeDef;
00075
00076 /**
00077   * @brief  IWDG Handle Structure definition
00078   */
00079 typedef struct
00080 {
00081   IWDG_TypeDef                 *Instance;  /*!< Register base address    */
00082
00083   IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
00084
00085 }IWDG_HandleTypeDef;
00086
00087 /**
00088   * @}
00089   */
00090
00091 /* Exported constants --------------------------------------------------------*/
00092 /** @defgroup IWDG_Exported_Constants IWDG Exported Constants
00093   * @{
00094   */
00095
00096 /** @defgroup IWDG_Prescaler IWDG Prescaler
00097   * @{
00098   */
00099 #define IWDG_PRESCALER_4                0x00000000u                   /*!< IWDG prescaler set to 4   */
00100 #define IWDG_PRESCALER_8                IWDG_PR_PR_0                  /*!< IWDG prescaler set to 8   */
00101 #define IWDG_PRESCALER_16               IWDG_PR_PR_1                  /*!< IWDG prescaler set to 16  */
00102 #define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32  */
00103 #define IWDG_PRESCALER_64               IWDG_PR_PR_2                  /*!< IWDG prescaler set to 64  */
00104 #define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)   /*!< IWDG prescaler set to 128U */
00105 #define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)   /*!< IWDG prescaler set to 256U */
00106 /**
00107   * @}
00108   */
00109
00110 /** @defgroup IWDG_Window_option IWDG Window option
00111   * @{
00112   */
00113 #define IWDG_WINDOW_DISABLE             IWDG_WINR_WIN
00114 /**
00115   * @}
00116   */
00117
00118 /**
00119   * @}
00120   */
00121
00122 /* Exported macros -----------------------------------------------------------*/
00123 /** @defgroup IWDG_Exported_Macros IWDG Exported Macros
00124   * @{
00125   */
00126
00127 /**
00128   * @brief  Enable the IWDG peripheral.
00129   * @param  __HANDLE__  IWDG handle
00130   * @retval None
00131   */
00132 #define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
00133
00134 /**
00135   * @brief  Reload IWDG counter with value defined in the reload register
00136   *         (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
00137   * @param  __HANDLE__  IWDG handle
00138   * @retval None
00139   */
00140 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
00141
00142 /**
00143   * @}
00144   */
00145
00146 /* Exported functions --------------------------------------------------------*/
00147 /** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
00148   * @{
00149   */
00150
00151 /** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
00152   * @{
00153   */
00154 /* Initialization/Start functions  ********************************************/
00155 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
00156 /**
00157   * @}
00158   */
00159
00160 /** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
00161   * @{
00162   */
00163 /* I/O operation functions ****************************************************/
00164 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
00165 /**
00166   * @}
00167   */
00168
00169 /**
00170   * @}
00171   */
00172
00173 /* Private constants ---------------------------------------------------------*/
00174 /** @defgroup IWDG_Private_Constants IWDG Private Constants
00175   * @{
00176   */
00177 /**
00178   * @brief  IWDG Key Register BitMask
00179   */
00180 #define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */
00181 #define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */
00182 #define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */
00183 #define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000u  /*!< IWDG KR Write Access Disable */
00184
00185 /**
00186   * @}
00187   */
00188
00189 /* Private macros ------------------------------------------------------------*/
00190 /** @defgroup IWDG_Private_Macros IWDG Private Macros
00191   * @{
00192   */
00193 /**
00194   * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00195   * @param  __HANDLE__  IWDG handle
00196   * @retval None
00197   */
00198 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
00199
00200 /**
00201   * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00202   * @param  __HANDLE__  IWDG handle
00203   * @retval None
00204   */
00205 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
00206
00207 /**
00208   * @brief  Check IWDG prescaler value.
00209   * @param  __PRESCALER__  IWDG prescaler value
00210   * @retval None
00211   */
00212 #define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
00213                                                ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
00214                                                ((__PRESCALER__) == IWDG_PRESCALER_16) || \
00215                                                ((__PRESCALER__) == IWDG_PRESCALER_32) || \
00216                                                ((__PRESCALER__) == IWDG_PRESCALER_64) || \
00217                                                ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
00218                                                ((__PRESCALER__) == IWDG_PRESCALER_256))
00219
00220 /**
00221   * @brief  Check IWDG reload value.
00222   * @param  __RELOAD__  IWDG reload value
00223   * @retval None
00224   */
00225 #define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
00226
00227 /**
00228   * @brief  Check IWDG window value.
00229   * @param  __WINDOW__  IWDG window value
00230   * @retval None
00231   */
00232 #define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= IWDG_WINR_WIN)
00233
00234 /**
00235   * @}
00236   */
00237
00238 /**
00239   * @}
00240   */
00241
00242 /**
00243   * @}
00244   */
00245
00246
00247 #ifdef __cplusplus
00248 }
00249 #endif
00250
00251 #endif /* __STM32F3xx_HAL_IWDG_H */
00252
00253 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_nand.c Source File

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stm32f3xx_hal_nand.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_nand.c
00004   * @author  MCD Application Team
00005   * @brief   NAND HAL module driver.
00006   *          This file provides a generic firmware to drive NAND memories mounted
00007   *          as external device.
00008   *
00009   @verbatim
00010   ==============================================================================
00011                          ##### How to use this driver #####
00012   ==============================================================================
00013     [..]
00014       This driver is a generic layered driver which contains a set of APIs used to
00015       control NAND flash memories. It uses the FMC layer functions to interface
00016       with NAND devices. This driver is used as follows:
00017
00018       (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
00019           with control and timing parameters for both common and attribute spaces.
00020
00021       (+) Read NAND flash memory maker and device IDs using the function
00022           HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
00023           structure declared by the function caller.
00024
00025       (+) Access NAND flash memory by read/write operations using the functions
00026           HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
00027           HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
00028           HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
00029           HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
00030           to read/write page(s)/spare area(s). These functions use specific device
00031           information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
00032           structure. The read/write address information is contained by the Nand_Address_Typedef
00033           structure passed as parameter.
00034
00035       (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
00036
00037       (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
00038           The erase block address information is contained in the Nand_Address_Typedef
00039           structure passed as parameter.
00040
00041       (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
00042
00043       (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
00044           HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
00045           feature or the function HAL_NAND_GetECC() to get the ECC correction code.
00046
00047       (+) You can monitor the NAND device HAL state by calling the function
00048           HAL_NAND_GetState()
00049
00050     [..]
00051       (@) This driver is a set of generic APIs which handle standard NAND flash operations.
00052           If a NAND flash device contains different operations and/or implementations,
00053           it should be implemented separately.
00054
00055   @endverbatim
00056   ******************************************************************************
00057   * @attention
00058   *
00059   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00060   *
00061   * Redistribution and use in source and binary forms, with or without modification,
00062   * are permitted provided that the following conditions are met:
00063   *   1. Redistributions of source code must retain the above copyright notice,
00064   *      this list of conditions and the following disclaimer.
00065   *   2. Redistributions in binary form must reproduce the above copyright notice,
00066   *      this list of conditions and the following disclaimer in the documentation
00067   *      and/or other materials provided with the distribution.
00068   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00069   *      may be used to endorse or promote products derived from this software
00070   *      without specific prior written permission.
00071   *
00072   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00073   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00074   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00075   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00076   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00077   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00078   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00079   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00080   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00081   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00082   *
00083   ******************************************************************************
00084   */
00085
00086 /* Includes ------------------------------------------------------------------*/
00087 #include "stm32f3xx_hal.h"
00088
00089 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
00090
00091 /** @addtogroup STM32F3xx_HAL_Driver
00092   * @{
00093   */
00094
00095 #ifdef HAL_NAND_MODULE_ENABLED
00096
00097 /** @defgroup NAND NAND
00098   * @brief NAND HAL module driver
00099   * @{
00100   */
00101
00102 /* Private typedef -----------------------------------------------------------*/
00103 /* Private define ------------------------------------------------------------*/
00104 /** @defgroup NAND_Private_Constants NAND Private Constants
00105   * @{
00106   */
00107
00108 /**
00109   * @}
00110   */
00111
00112 /* Private macro -------------------------------------------------------------*/
00113 /** @defgroup NAND_Private_Macros NAND Private Macros
00114   * @{
00115   */
00116
00117 /**
00118   * @}
00119   */
00120 /* Private variables ---------------------------------------------------------*/
00121 /* Private function prototypes -----------------------------------------------*/
00122 /* Exported functions --------------------------------------------------------*/
00123 /** @defgroup NAND_Exported_Functions NAND Exported Functions
00124   * @{
00125   */
00126
00127 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
00128   * @brief    Initialization and Configuration functions
00129   *
00130   @verbatim
00131   ==============================================================================
00132             ##### NAND Initialization and de-initialization functions #####
00133   ==============================================================================
00134   [..]
00135     This section provides functions allowing to initialize/de-initialize
00136     the NAND memory
00137
00138 @endverbatim
00139   * @{
00140   */
00141
00142 /**
00143   * @brief  Perform NAND memory Initialization sequence
00144   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00145   *                the configuration information for NAND module.
00146   * @param  ComSpace_Timing pointer to Common space timing structure
00147   * @param  AttSpace_Timing pointer to Attribute space timing structure
00148   * @retval HAL status
00149   */
00150 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
00151 {
00152   /* Check the NAND handle state */
00153   if(hnand == NULL)
00154   {
00155      return HAL_ERROR;
00156   }
00157
00158   if(hnand->State == HAL_NAND_STATE_RESET)
00159   {
00160     /* Allocate lock resource and initialize it */
00161     hnand->Lock = HAL_UNLOCKED;
00162     /* Initialize the low level hardware (MSP) */
00163     HAL_NAND_MspInit(hnand);
00164   }
00165
00166   /* Initialize NAND control Interface */
00167   FMC_NAND_Init(hnand->Instance, &(hnand->Init));
00168
00169   /* Initialize NAND common space timing Interface */
00170   FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
00171
00172   /* Initialize NAND attribute space timing Interface */
00173   FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
00174
00175   /* Enable the NAND device */
00176   __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
00177
00178   /* Update the NAND controller state */
00179   hnand->State = HAL_NAND_STATE_READY;
00180
00181   return HAL_OK;
00182 }
00183
00184 /**
00185   * @brief  Perform NAND memory De-Initialization sequence
00186   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00187   *                the configuration information for NAND module.
00188   * @retval HAL status
00189   */
00190 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
00191 {
00192   /* Initialize the low level hardware (MSP) */
00193   HAL_NAND_MspDeInit(hnand);
00194
00195   /* Configure the NAND registers with their reset values */
00196   FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
00197
00198   /* Reset the NAND controller state */
00199   hnand->State = HAL_NAND_STATE_RESET;
00200
00201   /* Release Lock */
00202   __HAL_UNLOCK(hnand);
00203
00204   return HAL_OK;
00205 }
00206
00207 /**
00208   * @brief  NAND MSP Init
00209   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00210   *                the configuration information for NAND module.
00211   * @retval None
00212   */
00213 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
00214 {
00215   /* Prevent unused argument(s) compilation warning */
00216   UNUSED(hnand);
00217   /* NOTE : This function Should not be modified, when the callback is needed,
00218             the HAL_NAND_MspInit could be implemented in the user file
00219    */
00220 }
00221
00222 /**
00223   * @brief  NAND MSP DeInit
00224   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00225   *                the configuration information for NAND module.
00226   * @retval None
00227   */
00228 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
00229 {
00230   /* Prevent unused argument(s) compilation warning */
00231   UNUSED(hnand);
00232   /* NOTE : This function Should not be modified, when the callback is needed,
00233             the HAL_NAND_MspDeInit could be implemented in the user file
00234    */
00235 }
00236
00237
00238 /**
00239   * @brief  This function handles NAND device interrupt request.
00240   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00241   *                the configuration information for NAND module.
00242   * @retval HAL status
00243 */
00244 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
00245 {
00246   /* Check NAND interrupt Rising edge flag */
00247   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
00248   {
00249     /* NAND interrupt callback*/
00250     HAL_NAND_ITCallback(hnand);
00251
00252     /* Clear NAND interrupt Rising edge pending bit */
00253     __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
00254   }
00255
00256   /* Check NAND interrupt Level flag */
00257   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
00258   {
00259     /* NAND interrupt callback*/
00260     HAL_NAND_ITCallback(hnand);
00261
00262     /* Clear NAND interrupt Level pending bit */
00263     __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
00264   }
00265
00266   /* Check NAND interrupt Falling edge flag */
00267   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
00268   {
00269     /* NAND interrupt callback*/
00270     HAL_NAND_ITCallback(hnand);
00271
00272     /* Clear NAND interrupt Falling edge pending bit */
00273     __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
00274   }
00275
00276   /* Check NAND interrupt FIFO empty flag */
00277   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
00278   {
00279     /* NAND interrupt callback*/
00280     HAL_NAND_ITCallback(hnand);
00281
00282     /* Clear NAND interrupt FIFO empty pending bit */
00283     __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
00284   }
00285 }
00286
00287 /**
00288   * @brief  NAND interrupt feature callback
00289   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00290   *                the configuration information for NAND module.
00291   * @retval None
00292   */
00293 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
00294 {
00295   /* Prevent unused argument(s) compilation warning */
00296   UNUSED(hnand);
00297   /* NOTE : This function Should not be modified, when the callback is needed,
00298             the HAL_NAND_ITCallback could be implemented in the user file
00299    */
00300 }
00301
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
00307   * @brief    Input Output and memory control functions
00308   *
00309   @verbatim
00310   ==============================================================================
00311                     ##### NAND Input and Output functions #####
00312   ==============================================================================
00313   [..]
00314     This section provides functions allowing to use and control the NAND
00315     memory
00316
00317 @endverbatim
00318   * @{
00319   */
00320
00321 /**
00322   * @brief  Read the NAND memory electronic signature
00323   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00324   *                the configuration information for NAND module.
00325   * @param  pNAND_ID NAND ID structure
00326   * @retval HAL status
00327   */
00328 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
00329 {
00330   __IO uint32_t data = 0U;
00331   __IO uint32_t data1 = 0U;
00332   uint32_t deviceaddress = 0U;
00333
00334   /* Process Locked */
00335   __HAL_LOCK(hnand);
00336
00337   /* Check the NAND controller state */
00338   if(hnand->State == HAL_NAND_STATE_BUSY)
00339   {
00340      return HAL_BUSY;
00341   }
00342
00343   /* Identify the device address */
00344   if(hnand->Init.NandBank == FMC_NAND_BANK2)
00345   {
00346     deviceaddress = NAND_DEVICE1;
00347   }
00348   else
00349   {
00350     deviceaddress = NAND_DEVICE2;
00351   }
00352
00353   /* Update the NAND controller state */
00354   hnand->State = HAL_NAND_STATE_BUSY;
00355
00356   /* Send Read ID command sequence */
00357   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_READID;
00358   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00359
00360   /* Read the electronic signature from NAND flash */
00361   if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
00362   {
00363     data = *(__IO uint32_t *)deviceaddress;
00364
00365     /* Return the data read */
00366     pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
00367     pNAND_ID->Device_Id  = ADDR_2ND_CYCLE(data);
00368     pNAND_ID->Third_Id   = ADDR_3RD_CYCLE(data);
00369     pNAND_ID->Fourth_Id  = ADDR_4TH_CYCLE(data);
00370   }
00371   else
00372   {
00373     data = *(__IO uint32_t *)deviceaddress;
00374     data1 = *((__IO uint32_t *)deviceaddress + 4U);
00375
00376     /* Return the data read */
00377     pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
00378     pNAND_ID->Device_Id  = ADDR_3RD_CYCLE(data);
00379     pNAND_ID->Third_Id   = ADDR_1ST_CYCLE(data1);
00380     pNAND_ID->Fourth_Id  = ADDR_3RD_CYCLE(data1);
00381   }
00382
00383   /* Update the NAND controller state */
00384   hnand->State = HAL_NAND_STATE_READY;
00385
00386   /* Process unlocked */
00387   __HAL_UNLOCK(hnand);
00388
00389   return HAL_OK;
00390 }
00391
00392 /**
00393   * @brief  NAND memory reset
00394   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00395   *                the configuration information for NAND module.
00396   * @retval HAL status
00397   */
00398 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
00399 {
00400   uint32_t deviceaddress = 0U;
00401
00402   /* Process Locked */
00403   __HAL_LOCK(hnand);
00404
00405   /* Check the NAND controller state */
00406   if(hnand->State == HAL_NAND_STATE_BUSY)
00407   {
00408      return HAL_BUSY;
00409   }
00410
00411   /* Identify the device address */
00412   if(hnand->Init.NandBank == FMC_NAND_BANK2)
00413   {
00414     deviceaddress = NAND_DEVICE1;
00415   }
00416   else
00417   {
00418     deviceaddress = NAND_DEVICE2;
00419   }
00420
00421   /* Update the NAND controller state */
00422   hnand->State = HAL_NAND_STATE_BUSY;
00423
00424   /* Send NAND reset command */
00425   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
00426
00427
00428   /* Update the NAND controller state */
00429   hnand->State = HAL_NAND_STATE_READY;
00430
00431   /* Process unlocked */
00432   __HAL_UNLOCK(hnand);
00433
00434   return HAL_OK;
00435
00436 }
00437
00438 /**
00439   * @brief  Configure the device: Enter the physical parameters of the device
00440   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00441   *                the configuration information for NAND module.
00442   * @param  pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
00443   * @retval HAL status
00444   */
00445 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
00446 {
00447   hnand->Config.PageSize           = pDeviceConfig->PageSize;
00448   hnand->Config.SpareAreaSize      = pDeviceConfig->SpareAreaSize;
00449   hnand->Config.BlockSize          = pDeviceConfig->BlockSize;
00450   hnand->Config.BlockNbr           = pDeviceConfig->BlockNbr;
00451   hnand->Config.PlaneSize          = pDeviceConfig->PlaneSize;
00452   hnand->Config.PlaneNbr           = pDeviceConfig->PlaneNbr;
00453   hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
00454
00455   return HAL_OK;
00456 }
00457
00458 /**
00459   * @brief  Read Page(s) from NAND memory block (8-bits addressing)
00460   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00461   *                the configuration information for NAND module.
00462   * @param  pAddress pointer to NAND address structure
00463   * @param  pBuffer pointer to destination read buffer
00464   * @param  NumPageToRead number of pages to read from block
00465   * @retval HAL status
00466   */
00467 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
00468 {
00469   __IO uint32_t index  = 0U;
00470   uint32_t tickstart = 0U;
00471   uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
00472
00473   /* Process Locked */
00474   __HAL_LOCK(hnand);
00475
00476   /* Check the NAND controller state */
00477   if(hnand->State == HAL_NAND_STATE_BUSY)
00478   {
00479      return HAL_BUSY;
00480   }
00481
00482   /* Identify the device address */
00483   if(hnand->Init.NandBank == FMC_NAND_BANK2)
00484   {
00485     deviceaddress = NAND_DEVICE1;
00486   }
00487   else
00488   {
00489     deviceaddress = NAND_DEVICE2;
00490   }
00491
00492   /* Update the NAND controller state */
00493   hnand->State = HAL_NAND_STATE_BUSY;
00494
00495   /* NAND raw address calculation */
00496   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
00497
00498   /* Page(s) read loop */
00499   while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00500   {
00501     /* update the buffer size */
00502     size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
00503
00504     /* Send read page command sequence */
00505     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
00506
00507     /* Cards with page size <= 512 bytes */
00508     if((hnand->Config.PageSize) <= 512U)
00509     {
00510       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
00511       {
00512         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00513         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00514         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00515       }
00516       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00517       {
00518         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00519         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00520         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00521         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00522       }
00523     }
00524     else /* (hnand->Config.PageSize) > 512 */
00525     {
00526       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
00527       {
00528         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00529         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00530         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00531         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00532       }
00533       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00534       {
00535         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00536         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00537         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00538         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00539         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00540       }
00541     }
00542
00543     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
00544
00545     /* Check if an extra command is needed for reading pages  */
00546     if(hnand->Config.ExtraCommandEnable == ENABLE)
00547     {
00548       /* Get tick */
00549       tickstart = HAL_GetTick();
00550
00551       /* Read status until NAND is ready */
00552       while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00553       {
00554         if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00555         {
00556           return HAL_TIMEOUT;
00557         }
00558       }
00559
00560       /* Go back to read mode */
00561       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
00562       __DSB();
00563     }
00564
00565     /* Get Data into Buffer */
00566     for(; index < size; index++)
00567     {
00568       *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
00569     }
00570
00571     /* Increment read pages number */
00572     numPagesRead++;
00573
00574     /* Decrement pages to read */
00575     NumPageToRead--;
00576
00577     /* Increment the NAND address */
00578     nandaddress = (uint32_t)(nandaddress + 1U);
00579   }
00580
00581   /* Update the NAND controller state */
00582   hnand->State = HAL_NAND_STATE_READY;
00583
00584   /* Process unlocked */
00585   __HAL_UNLOCK(hnand);
00586
00587   return HAL_OK;
00588 }
00589
00590 /**
00591   * @brief  Read Page(s) from NAND memory block (16-bits addressing)
00592   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00593   *                the configuration information for NAND module.
00594   * @param  pAddress pointer to NAND address structure
00595   * @param  pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned
00596   * @param  NumPageToRead number of pages to read from block
00597   * @retval HAL status
00598   */
00599 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
00600 {
00601   __IO uint32_t index  = 0U;
00602   uint32_t tickstart = 0U;
00603   uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
00604
00605   /* Process Locked */
00606   __HAL_LOCK(hnand);
00607
00608   /* Check the NAND controller state */
00609   if(hnand->State == HAL_NAND_STATE_BUSY)
00610   {
00611      return HAL_BUSY;
00612   }
00613
00614   /* Identify the device address */
00615   if(hnand->Init.NandBank == FMC_NAND_BANK2)
00616   {
00617     deviceaddress = NAND_DEVICE1;
00618   }
00619   else
00620   {
00621     deviceaddress = NAND_DEVICE2;
00622   }
00623
00624   /* Update the NAND controller state */
00625   hnand->State = HAL_NAND_STATE_BUSY;
00626
00627   /* NAND raw address calculation */
00628   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
00629
00630   /* Page(s) read loop */
00631   while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00632   {
00633     /* update the buffer size */
00634     size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
00635
00636     /* Send read page command sequence */
00637     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
00638     __DSB();
00639
00640     /* Cards with page size <= 512 bytes */
00641     if((hnand->Config.PageSize) <= 512U)
00642     {
00643       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
00644       {
00645         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00646         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00647         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00648       }
00649       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00650       {
00651         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00652         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00653         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00654         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00655       }
00656     }
00657     else /* (hnand->Config.PageSize) > 512 */
00658     {
00659       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
00660       {
00661         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00662         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00663         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00664         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00665       }
00666       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00667       {
00668         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00669         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00670         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00671         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00672         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00673       }
00674     }
00675
00676     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
00677
00678     if(hnand->Config.ExtraCommandEnable == ENABLE)
00679     {
00680       /* Get tick */
00681       tickstart = HAL_GetTick();
00682
00683       /* Read status until NAND is ready */
00684       while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00685       {
00686         if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00687         {
00688           return HAL_TIMEOUT;
00689         }
00690       }
00691
00692       /* Go back to read mode */
00693       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
00694     }
00695
00696     /* Get Data into Buffer */
00697     for(; index < size; index++)
00698     {
00699       *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
00700     }
00701
00702     /* Increment read pages number */
00703     numPagesRead++;
00704
00705     /* Decrement pages to read */
00706     NumPageToRead--;
00707
00708     /* Increment the NAND address */
00709     nandaddress = (uint32_t)(nandaddress + 1U);
00710   }
00711
00712   /* Update the NAND controller state */
00713   hnand->State = HAL_NAND_STATE_READY;
00714
00715   /* Process unlocked */
00716   __HAL_UNLOCK(hnand);
00717
00718   return HAL_OK;
00719 }
00720
00721 /**
00722   * @brief  Write Page(s) to NAND memory block (8-bits addressing)
00723   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00724   *                the configuration information for NAND module.
00725   * @param  pAddress pointer to NAND address structure
00726   * @param  pBuffer pointer to source buffer to write
00727   * @param  NumPageToWrite  : number of pages to write to block
00728   * @retval HAL status
00729   */
00730 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
00731 {
00732   __IO uint32_t index = 0U;
00733   uint32_t tickstart = 0U;
00734   uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
00735
00736   /* Process Locked */
00737   __HAL_LOCK(hnand);
00738
00739   /* Check the NAND controller state */
00740   if(hnand->State == HAL_NAND_STATE_BUSY)
00741   {
00742      return HAL_BUSY;
00743   }
00744
00745   /* Identify the device address */
00746   if(hnand->Init.NandBank == FMC_NAND_BANK2)
00747   {
00748     deviceaddress = NAND_DEVICE1;
00749   }
00750   else
00751   {
00752     deviceaddress = NAND_DEVICE2;
00753   }
00754
00755   /* Update the NAND controller state */
00756   hnand->State = HAL_NAND_STATE_BUSY;
00757
00758   /* NAND raw address calculation */
00759   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
00760
00761   /* Page(s) write loop */
00762   while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00763   {
00764     /* update the buffer size */
00765     size = hnand->Config.PageSize + ((hnand->Config.PageSize) * numPagesWritten);
00766
00767     /* Send write page command sequence */
00768     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
00769     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
00770
00771     /* Cards with page size <= 512 bytes */
00772     if((hnand->Config.PageSize) <= 512U)
00773     {
00774       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
00775       {
00776         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00777         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00778         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00779       }
00780       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00781       {
00782         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00783         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00784         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00785         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00786       }
00787     }
00788     else /* (hnand->Config.PageSize) > 512 */
00789     {
00790       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
00791       {
00792         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00793         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00794         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00795         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00796       }
00797       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00798       {
00799         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00800         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00801         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00802         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00803         __DSB();
00804         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00805         __DSB();
00806       }
00807     }
00808
00809
00810     /* Write data to memory */
00811     for(; index < size; index++)
00812     {
00813       *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
00814     }
00815
00816     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
00817
00818     /* Read status until NAND is ready */
00819     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00820     {
00821       /* Get tick */
00822       tickstart = HAL_GetTick();
00823
00824       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00825       {
00826         return HAL_TIMEOUT;
00827       }
00828     }
00829
00830     /* Increment written pages number */
00831     numPagesWritten++;
00832
00833     /* Decrement pages to write */
00834     NumPageToWrite--;
00835
00836     /* Increment the NAND address */
00837     nandaddress = (uint32_t)(nandaddress + 1U);
00838   }
00839
00840   /* Update the NAND controller state */
00841   hnand->State = HAL_NAND_STATE_READY;
00842
00843   /* Process unlocked */
00844   __HAL_UNLOCK(hnand);
00845
00846   return HAL_OK;
00847 }
00848
00849 /**
00850   * @brief  Write Page(s) to NAND memory block (16-bits addressing)
00851   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00852   *                the configuration information for NAND module.
00853   * @param  pAddress pointer to NAND address structure
00854   * @param  pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned
00855   * @param  NumPageToWrite  : number of pages to write to block
00856   * @retval HAL status
00857   */
00858 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
00859 {
00860   __IO uint32_t index = 0U;
00861   uint32_t tickstart = 0U;
00862   uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
00863
00864   /* Process Locked */
00865   __HAL_LOCK(hnand);
00866
00867   /* Check the NAND controller state */
00868   if(hnand->State == HAL_NAND_STATE_BUSY)
00869   {
00870      return HAL_BUSY;
00871   }
00872
00873   /* Identify the device address */
00874   if(hnand->Init.NandBank == FMC_NAND_BANK2)
00875   {
00876     deviceaddress = NAND_DEVICE1;
00877   }
00878   else
00879   {
00880     deviceaddress = NAND_DEVICE2;
00881   }
00882
00883   /* Update the NAND controller state */
00884   hnand->State = HAL_NAND_STATE_BUSY;
00885
00886   /* NAND raw address calculation */
00887   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
00888
00889   /* Page(s) write loop */
00890   while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00891   {
00892     /* update the buffer size */
00893     size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
00894
00895     /* Send write page command sequence */
00896     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
00897     __DSB();
00898     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
00899     __DSB();
00900
00901     /* Cards with page size <= 512 bytes */
00902     if((hnand->Config.PageSize) <= 512U)
00903     {
00904       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
00905       {
00906         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00907         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00908         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00909       }
00910       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00911       {
00912         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00913         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00914         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00915         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00916       }
00917     }
00918     else /* (hnand->Config.PageSize) > 512 */
00919     {
00920       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
00921       {
00922         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00923         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00924         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00925         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00926       }
00927       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00928       {
00929         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00930         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00931         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00932         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00933         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00934       }
00935     }
00936
00937     /* Write data to memory */
00938     for(; index < size; index++)
00939     {
00940       *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
00941     }
00942
00943     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
00944
00945     /* Read status until NAND is ready */
00946     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00947     {
00948       /* Get tick */
00949       tickstart = HAL_GetTick();
00950
00951       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00952       {
00953         return HAL_TIMEOUT;
00954       }
00955     }
00956
00957     /* Increment written pages number */
00958     numPagesWritten++;
00959
00960     /* Decrement pages to write */
00961     NumPageToWrite--;
00962
00963     /* Increment the NAND address */
00964     nandaddress = (uint32_t)(nandaddress + 1U);
00965   }
00966
00967   /* Update the NAND controller state */
00968   hnand->State = HAL_NAND_STATE_READY;
00969
00970   /* Process unlocked */
00971   __HAL_UNLOCK(hnand);
00972
00973   return HAL_OK;
00974 }
00975
00976 /**
00977   * @brief  Read Spare area(s) from NAND memory
00978   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00979   *                the configuration information for NAND module.
00980   * @param  pAddress pointer to NAND address structure
00981   * @param  pBuffer pointer to source buffer to write
00982   * @param  NumSpareAreaToRead Number of spare area to read
00983   * @retval HAL status
00984 */
00985 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
00986 {
00987   __IO uint32_t index = 0U;
00988   uint32_t tickstart = 0U;
00989   uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
00990
00991   /* Process Locked */
00992   __HAL_LOCK(hnand);
00993
00994   /* Check the NAND controller state */
00995   if(hnand->State == HAL_NAND_STATE_BUSY)
00996   {
00997      return HAL_BUSY;
00998   }
00999
01000   /* Identify the device address */
01001   if(hnand->Init.NandBank == FMC_NAND_BANK2)
01002   {
01003     deviceaddress = NAND_DEVICE1;
01004   }
01005   else
01006   {
01007     deviceaddress = NAND_DEVICE2;
01008   }
01009
01010   /* Update the NAND controller state */
01011   hnand->State = HAL_NAND_STATE_BUSY;
01012
01013   /* NAND raw address calculation */
01014   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
01015
01016   /* Column in page address */
01017   columnaddress = COLUMN_ADDRESS(hnand);
01018
01019   /* Spare area(s) read loop */
01020   while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01021   {
01022     /* update the buffer size */
01023     size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
01024
01025     /* Cards with page size <= 512 bytes */
01026     if((hnand->Config.PageSize) <= 512U)
01027     {
01028       /* Send read spare area command sequence */
01029       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
01030
01031       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
01032       {
01033         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
01034         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01035         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01036       }
01037       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01038       {
01039         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
01040         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01041         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01042         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01043       }
01044     }
01045     else /* (hnand->Config.PageSize) > 512 */
01046     {
01047       /* Send read spare area command sequence */
01048       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
01049
01050       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
01051       {
01052         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01053         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01054         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01055         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01056       }
01057       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01058       {
01059         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01060         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01061         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01062         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01063         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01064       }
01065     }
01066
01067     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
01068
01069     if(hnand->Config.ExtraCommandEnable == ENABLE)
01070     {
01071       /* Get tick */
01072       tickstart = HAL_GetTick();
01073
01074       /* Read status until NAND is ready */
01075       while(HAL_NAND_Read_Status(hnand) != NAND_READY)
01076       {
01077         if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
01078         {
01079           return HAL_TIMEOUT;
01080         }
01081       }
01082
01083       /* Go back to read mode */
01084       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
01085     }
01086
01087     /* Get Data into Buffer */
01088     for(; index < size; index++)
01089     {
01090       *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
01091     }
01092
01093     /* Increment read spare areas number */
01094     numSpareAreaRead++;
01095
01096     /* Decrement spare areas to read */
01097     NumSpareAreaToRead--;
01098
01099     /* Increment the NAND address */
01100     nandaddress = (uint32_t)(nandaddress + 1U);
01101   }
01102
01103   /* Update the NAND controller state */
01104   hnand->State = HAL_NAND_STATE_READY;
01105
01106   /* Process unlocked */
01107   __HAL_UNLOCK(hnand);
01108
01109   return HAL_OK;
01110 }
01111
01112 /**
01113   * @brief  Read Spare area(s) from NAND memory (16-bits addressing)
01114   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01115   *                the configuration information for NAND module.
01116   * @param  pAddress pointer to NAND address structure
01117   * @param  pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
01118   * @param  NumSpareAreaToRead Number of spare area to read
01119   * @retval HAL status
01120 */
01121 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
01122 {
01123   __IO uint32_t index = 0U;
01124   uint32_t tickstart = 0U;
01125   uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
01126
01127   /* Process Locked */
01128   __HAL_LOCK(hnand);
01129
01130   /* Check the NAND controller state */
01131   if(hnand->State == HAL_NAND_STATE_BUSY)
01132   {
01133      return HAL_BUSY;
01134   }
01135
01136   /* Identify the device address */
01137   if(hnand->Init.NandBank == FMC_NAND_BANK2)
01138   {
01139     deviceaddress = NAND_DEVICE1;
01140   }
01141   else
01142   {
01143     deviceaddress = NAND_DEVICE2;
01144   }
01145
01146   /* Update the NAND controller state */
01147   hnand->State = HAL_NAND_STATE_BUSY;
01148
01149   /* NAND raw address calculation */
01150   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
01151
01152   /* Column in page address */
01153   columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
01154
01155   /* Spare area(s) read loop */
01156   while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01157   {
01158     /* update the buffer size */
01159     size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
01160
01161     /* Cards with page size <= 512 bytes */
01162     if((hnand->Config.PageSize) <= 512U)
01163     {
01164       /* Send read spare area command sequence */
01165       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
01166
01167       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
01168       {
01169         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
01170         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01171         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01172       }
01173       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01174       {
01175         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
01176         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01177         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01178         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01179       }
01180     }
01181     else /* (hnand->Config.PageSize) > 512 */
01182     {
01183       /* Send read spare area command sequence */
01184       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
01185
01186       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
01187       {
01188         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01189         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01190         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01191         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01192       }
01193       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01194       {
01195         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01196         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01197         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01198         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01199         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01200       }
01201     }
01202
01203     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
01204
01205     if(hnand->Config.ExtraCommandEnable == ENABLE)
01206     {
01207       /* Get tick */
01208       tickstart = HAL_GetTick();
01209
01210       /* Read status until NAND is ready */
01211       while(HAL_NAND_Read_Status(hnand) != NAND_READY)
01212       {
01213         if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
01214         {
01215           return HAL_TIMEOUT;
01216         }
01217       }
01218
01219       /* Go back to read mode */
01220       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
01221     }
01222
01223     /* Get Data into Buffer */
01224     for(; index < size; index++)
01225     {
01226       *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
01227     }
01228
01229     /* Increment read spare areas number */
01230     numSpareAreaRead++;
01231
01232     /* Decrement spare areas to read */
01233     NumSpareAreaToRead--;
01234
01235     /* Increment the NAND address */
01236     nandaddress = (uint32_t)(nandaddress + 1U);
01237   }
01238
01239   /* Update the NAND controller state */
01240   hnand->State = HAL_NAND_STATE_READY;
01241
01242   /* Process unlocked */
01243   __HAL_UNLOCK(hnand);
01244
01245   return HAL_OK;
01246 }
01247
01248 /**
01249   * @brief  Write Spare area(s) to NAND memory
01250   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01251   *                the configuration information for NAND module.
01252   * @param  pAddress pointer to NAND address structure
01253   * @param  pBuffer pointer to source buffer to write
01254   * @param  NumSpareAreaTowrite  : number of spare areas to write to block
01255   * @retval HAL status
01256   */
01257 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
01258 {
01259   __IO uint32_t index = 0U;
01260   uint32_t tickstart = 0U;
01261   uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
01262
01263   /* Process Locked */
01264   __HAL_LOCK(hnand);
01265
01266   /* Check the NAND controller state */
01267   if(hnand->State == HAL_NAND_STATE_BUSY)
01268   {
01269      return HAL_BUSY;
01270   }
01271
01272   /* Identify the device address */
01273   if(hnand->Init.NandBank == FMC_NAND_BANK2)
01274   {
01275     deviceaddress = NAND_DEVICE1;
01276   }
01277   else
01278   {
01279     deviceaddress = NAND_DEVICE2;
01280   }
01281
01282   /* Update the FMC_NAND controller state */
01283   hnand->State = HAL_NAND_STATE_BUSY;
01284
01285   /* Page address calculation */
01286   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
01287
01288   /* Column in page address */
01289   columnaddress = COLUMN_ADDRESS(hnand);
01290
01291   /* Spare area(s) write loop */
01292   while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01293   {
01294     /* update the buffer size */
01295     size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
01296
01297     /* Cards with page size <= 512 bytes */
01298     if((hnand->Config.PageSize) <= 512U)
01299     {
01300       /* Send write Spare area command sequence */
01301       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
01302       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
01303
01304       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
01305       {
01306         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
01307         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01308         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01309       }
01310       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01311       {
01312         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
01313         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01314         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01315         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01316       }
01317     }
01318     else /* (hnand->Config.PageSize) > 512 */
01319     {
01320       /* Send write Spare area command sequence */
01321       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
01322       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
01323
01324       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
01325       {
01326         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01327         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01328         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01329         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01330       }
01331       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01332       {
01333         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01334         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01335         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01336         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01337         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01338       }
01339     }
01340
01341     /* Write data to memory */
01342     for(; index < size; index++)
01343     {
01344       *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
01345     }
01346
01347     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
01348
01349     /* Get tick */
01350     tickstart = HAL_GetTick();
01351
01352     /* Read status until NAND is ready */
01353     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
01354     {
01355       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
01356       {
01357         return HAL_TIMEOUT;
01358       }
01359     }
01360
01361     /* Increment written spare areas number */
01362     numSpareAreaWritten++;
01363
01364     /* Decrement spare areas to write */
01365     NumSpareAreaTowrite--;
01366
01367     /* Increment the NAND address */
01368     nandaddress = (uint32_t)(nandaddress + 1U);
01369   }
01370
01371   /* Update the NAND controller state */
01372   hnand->State = HAL_NAND_STATE_READY;
01373
01374   /* Process unlocked */
01375   __HAL_UNLOCK(hnand);
01376
01377   return HAL_OK;
01378 }
01379
01380 /**
01381   * @brief  Write Spare area(s) to NAND memory (16-bits addressing)
01382   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01383   *                the configuration information for NAND module.
01384   * @param  pAddress pointer to NAND address structure
01385   * @param  pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
01386   * @param  NumSpareAreaTowrite  : number of spare areas to write to block
01387   * @retval HAL status
01388   */
01389 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
01390 {
01391   __IO uint32_t index = 0U;
01392   uint32_t tickstart = 0U;
01393   uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
01394
01395   /* Process Locked */
01396   __HAL_LOCK(hnand);
01397
01398   /* Check the NAND controller state */
01399   if(hnand->State == HAL_NAND_STATE_BUSY)
01400   {
01401      return HAL_BUSY;
01402   }
01403
01404   /* Identify the device address */
01405   if(hnand->Init.NandBank == FMC_NAND_BANK2)
01406   {
01407     deviceaddress = NAND_DEVICE1;
01408   }
01409   else
01410   {
01411     deviceaddress = NAND_DEVICE2;
01412   }
01413
01414   /* Update the FMC_NAND controller state */
01415   hnand->State = HAL_NAND_STATE_BUSY;
01416
01417   /* NAND raw address calculation */
01418   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
01419
01420   /* Column in page address */
01421   columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
01422
01423   /* Spare area(s) write loop */
01424   while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01425   {
01426     /* update the buffer size */
01427     size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
01428
01429     /* Cards with page size <= 512 bytes */
01430     if((hnand->Config.PageSize) <= 512U)
01431     {
01432       /* Send write Spare area command sequence */
01433       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
01434       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
01435
01436       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
01437       {
01438         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
01439         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01440         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01441       }
01442       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01443       {
01444         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
01445         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01446         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01447         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01448       }
01449     }
01450     else /* (hnand->Config.PageSize) > 512 */
01451     {
01452       /* Send write Spare area command sequence */
01453       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
01454       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
01455
01456       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
01457       {
01458         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01459         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01460         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01461         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01462       }
01463       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01464       {
01465         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01466         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01467         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01468         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01469         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01470       }
01471     }
01472
01473     /* Write data to memory */
01474     for(; index < size; index++)
01475     {
01476       *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
01477     }
01478
01479     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
01480
01481     /* Read status until NAND is ready */
01482     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
01483     {
01484       /* Get tick */
01485       tickstart = HAL_GetTick();
01486
01487       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
01488       {
01489         return HAL_TIMEOUT;
01490       }
01491     }
01492
01493     /* Increment written spare areas number */
01494     numSpareAreaWritten++;
01495
01496     /* Decrement spare areas to write */
01497     NumSpareAreaTowrite--;
01498
01499     /* Increment the NAND address */
01500     nandaddress = (uint32_t)(nandaddress + 1U);
01501   }
01502
01503   /* Update the NAND controller state */
01504   hnand->State = HAL_NAND_STATE_READY;
01505
01506   /* Process unlocked */
01507   __HAL_UNLOCK(hnand);
01508
01509   return HAL_OK;
01510 }
01511
01512 /**
01513   * @brief  NAND memory Block erase
01514   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01515   *                the configuration information for NAND module.
01516   * @param  pAddress pointer to NAND address structure
01517   * @retval HAL status
01518   */
01519 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
01520 {
01521   uint32_t deviceaddress = 0U;
01522   uint32_t tickstart = 0U;
01523
01524   /* Process Locked */
01525   __HAL_LOCK(hnand);
01526
01527   /* Check the NAND controller state */
01528   if(hnand->State == HAL_NAND_STATE_BUSY)
01529   {
01530      return HAL_BUSY;
01531   }
01532
01533   /* Identify the device address */
01534   if(hnand->Init.NandBank == FMC_NAND_BANK2)
01535   {
01536     deviceaddress = NAND_DEVICE1;
01537   }
01538   else
01539   {
01540     deviceaddress = NAND_DEVICE2;
01541   }
01542
01543   /* Update the NAND controller state */
01544   hnand->State = HAL_NAND_STATE_BUSY;
01545
01546   /* Send Erase block command sequence */
01547   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
01548
01549   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
01550   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
01551   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
01552
01553   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
01554
01555   /* Update the NAND controller state */
01556   hnand->State = HAL_NAND_STATE_READY;
01557
01558   /* Get tick */
01559   tickstart = HAL_GetTick();
01560
01561   /* Read status until NAND is ready */
01562   while(HAL_NAND_Read_Status(hnand) != NAND_READY)
01563   {
01564     if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
01565     {
01566       /* Process unlocked */
01567       __HAL_UNLOCK(hnand);
01568
01569       return HAL_TIMEOUT;
01570     }
01571   }
01572
01573   /* Process unlocked */
01574   __HAL_UNLOCK(hnand);
01575
01576   return HAL_OK;
01577 }
01578
01579 /**
01580   * @brief  NAND memory read status
01581   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01582   *                the configuration information for NAND module.
01583   * @retval NAND status
01584   */
01585 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
01586 {
01587   uint32_t data = 0U;
01588   uint32_t deviceaddress = 0U;
01589
01590   /* Identify the device address */
01591   if(hnand->Init.NandBank == FMC_NAND_BANK2)
01592   {
01593     deviceaddress = NAND_DEVICE1;
01594   }
01595   else
01596   {
01597     deviceaddress = NAND_DEVICE2;
01598   }
01599
01600   /* Send Read status operation command */
01601   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
01602
01603   /* Read status register data */
01604   data = *(__IO uint8_t *)deviceaddress;
01605
01606   /* Return the status */
01607   if((data & NAND_ERROR) == NAND_ERROR)
01608   {
01609     return NAND_ERROR;
01610   }
01611   else if((data & NAND_READY) == NAND_READY)
01612   {
01613     return NAND_READY;
01614   }
01615
01616   return NAND_BUSY;
01617 }
01618
01619 /**
01620   * @brief  Increment the NAND memory address
01621   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01622   *                the configuration information for NAND module.
01623   * @param pAddress pointer to NAND address structure
01624   * @retval The new status of the increment address operation. It can be:
01625   *           - NAND_VALID_ADDRESS: When the new address is valid address
01626   *           - NAND_INVALID_ADDRESS: When the new address is invalid address
01627   */
01628 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
01629 {
01630   uint32_t status = NAND_VALID_ADDRESS;
01631
01632   /* Increment page address */
01633   pAddress->Page++;
01634
01635   /* Check NAND address is valid */
01636   if(pAddress->Page == hnand->Config.BlockSize)
01637   {
01638     pAddress->Page = 0U;
01639     pAddress->Block++;
01640
01641     if(pAddress->Block == hnand->Config.PlaneSize)
01642     {
01643       pAddress->Block = 0U;
01644       pAddress->Plane++;
01645
01646       if(pAddress->Plane == (hnand->Config.PlaneNbr))
01647       {
01648         status = NAND_INVALID_ADDRESS;
01649       }
01650     }
01651   }
01652
01653   return (status);
01654 }
01655 /**
01656   * @}
01657   */
01658
01659 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
01660  *  @brief   management functions
01661  *
01662 @verbatim
01663   ==============================================================================
01664                          ##### NAND Control functions #####
01665   ==============================================================================
01666   [..]
01667     This subsection provides a set of functions allowing to control dynamically
01668     the NAND interface.
01669
01670 @endverbatim
01671   * @{
01672   */
01673
01674
01675 /**
01676   * @brief  Enables dynamically NAND ECC feature.
01677   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01678   *                the configuration information for NAND module.
01679   * @retval HAL status
01680   */
01681 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
01682 {
01683   /* Check the NAND controller state */
01684   if(hnand->State == HAL_NAND_STATE_BUSY)
01685   {
01686      return HAL_BUSY;
01687   }
01688
01689   /* Update the NAND state */
01690   hnand->State = HAL_NAND_STATE_BUSY;
01691
01692   /* Enable ECC feature */
01693   FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
01694
01695   /* Update the NAND state */
01696   hnand->State = HAL_NAND_STATE_READY;
01697
01698   return HAL_OK;
01699 }
01700
01701 /**
01702   * @brief  Disables dynamically FMC_NAND ECC feature.
01703   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01704   *                the configuration information for NAND module.
01705   * @retval HAL status
01706   */
01707 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
01708 {
01709   /* Check the NAND controller state */
01710   if(hnand->State == HAL_NAND_STATE_BUSY)
01711   {
01712      return HAL_BUSY;
01713   }
01714
01715   /* Update the NAND state */
01716   hnand->State = HAL_NAND_STATE_BUSY;
01717
01718   /* Disable ECC feature */
01719   FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
01720
01721   /* Update the NAND state */
01722   hnand->State = HAL_NAND_STATE_READY;
01723
01724   return HAL_OK;
01725 }
01726
01727 /**
01728   * @brief  Disables dynamically NAND ECC feature.
01729   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01730   *                the configuration information for NAND module.
01731   * @param  ECCval pointer to ECC value
01732   * @param  Timeout maximum timeout to wait
01733   * @retval HAL status
01734   */
01735 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
01736 {
01737   HAL_StatusTypeDef status = HAL_OK;
01738
01739   /* Check the NAND controller state */
01740   if(hnand->State == HAL_NAND_STATE_BUSY)
01741   {
01742      return HAL_BUSY;
01743   }
01744
01745   /* Update the NAND state */
01746   hnand->State = HAL_NAND_STATE_BUSY;
01747
01748   /* Get NAND ECC value */
01749   status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
01750
01751   /* Update the NAND state */
01752   hnand->State = HAL_NAND_STATE_READY;
01753
01754   return status;
01755 }
01756
01757 /**
01758   * @}
01759   */
01760
01761
01762 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
01763  *  @brief   Peripheral State functions
01764  *
01765 @verbatim
01766   ==============================================================================
01767                          ##### NAND State functions #####
01768   ==============================================================================
01769   [..]
01770     This subsection permits to get in run-time the status of the NAND controller
01771     and the data flow.
01772
01773 @endverbatim
01774   * @{
01775   */
01776
01777 /**
01778   * @brief  return the NAND state
01779   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01780   *                the configuration information for NAND module.
01781   * @retval HAL state
01782   */
01783 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
01784 {
01785   return hnand->State;
01786 }
01787
01788 /**
01789   * @}
01790   */
01791
01792 /**
01793   * @}
01794   */
01795
01796 /**
01797   * @}
01798   */
01799
01800 #endif /* HAL_NAND_MODULE_ENABLED  */
01801
01802 /**
01803   * @}
01804   */
01805 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
01806
01807 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_nand.h Source File

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stm32f3xx_hal_nand.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_nand.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of NAND HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_NAND_H
00038 #define __STM32F3xx_HAL_NAND_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
00046 #include "stm32f3xx_ll_fmc.h"
00047
00048 /** @addtogroup STM32F3xx_HAL_Driver
00049   * @{
00050   */
00051
00052 /** @addtogroup NAND
00053   * @{
00054   */
00055
00056 /* Exported typedef ----------------------------------------------------------*/
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup NAND_Exported_Types NAND Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  HAL NAND State structures definition
00064   */
00065 typedef enum
00066 {
00067   HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
00068   HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
00069   HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
00070   HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
00071 }HAL_NAND_StateTypeDef;
00072
00073 /**
00074   * @brief  NAND Memory electronic signature Structure definition
00075   */
00076 typedef struct
00077 {
00078   /*<! NAND memory electronic signature maker and device IDs */
00079
00080   uint8_t Maker_Id;
00081
00082   uint8_t Device_Id;
00083
00084   uint8_t Third_Id;
00085
00086   uint8_t Fourth_Id;
00087 }NAND_IDTypeDef;
00088
00089 /**
00090   * @brief  NAND Memory address Structure definition
00091   */
00092 typedef struct
00093 {
00094   uint16_t Page;   /*!< NAND memory Page address    */
00095
00096   uint16_t Plane;   /*!< NAND memory Plane address  */
00097
00098   uint16_t Block;  /*!< NAND memory Block address   */
00099
00100 }NAND_AddressTypeDef;
00101
00102 /**
00103   * @brief  NAND Memory info Structure definition
00104   */
00105 typedef struct
00106 {
00107   uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes
00108                                               for 8 bits adressing or words for 16 bits addressing             */
00109
00110   uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes
00111                                               for 8 bits adressing or words for 16 bits addressing             */
00112
00113   uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
00114
00115   uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
00116
00117   uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
00118
00119   uint32_t        PlaneSize;             /*!< NAND memory plane size measured in number of blocks               */
00120
00121   FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This
00122                                               parameter is mandatory for some NAND parts after the read
00123                                               command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
00124                                               Example: Toshiba THTH58BYG3S0HBAI6.
00125                                               This parameter could be ENABLE or DISABLE
00126                                               Please check the Read Mode sequnece in the NAND device datasheet */
00127 }NAND_DeviceConfigTypeDef;
00128
00129 /**
00130   * @brief  NAND handle Structure definition
00131   */
00132 typedef struct
00133 {
00134   FMC_NAND_TypeDef               *Instance;  /*!< Register base address                                 */
00135
00136   FMC_NAND_InitTypeDef           Init;       /*!< NAND device control configuration parameters          */
00137
00138   HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */
00139
00140   __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
00141
00142   NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */
00143
00144 }NAND_HandleTypeDef;
00145 /**
00146   * @}
00147   */
00148
00149 /* Exported constants --------------------------------------------------------*/
00150 /* Exported macros ------------------------------------------------------------*/
00151 /** @defgroup NAND_Exported_Macros NAND Exported Macros
00152  * @{
00153  */
00154
00155 /** @brief Reset NAND handle state
00156   * @param  __HANDLE__ specifies the NAND handle.
00157   * @retval None
00158   */
00159 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
00160
00161 /**
00162   * @}
00163   */
00164
00165 /* Exported functions --------------------------------------------------------*/
00166 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
00167   * @{
00168   */
00169
00170 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
00171   * @{
00172   */
00173
00174 /* Initialization/de-initialization functions  ********************************/
00175 /* Initialization/de-initialization functions  ********************************/
00176 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
00177 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
00178
00179 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
00180
00181 HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
00182
00183 void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
00184 void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
00185 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
00186 void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
00187
00188 /**
00189   * @}
00190   */
00191
00192 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
00193   * @{
00194   */
00195
00196 /* IO operation functions  ****************************************************/
00197 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
00198
00199 HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
00200 HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
00201 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
00202 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
00203
00204 HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
00205 HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
00206 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
00207 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
00208
00209 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
00210
00211 uint32_t           HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
00212 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
00213
00214 /**
00215   * @}
00216   */
00217
00218 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
00219   * @{
00220   */
00221
00222 /* NAND Control functions  ****************************************************/
00223 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
00224 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
00225 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
00226
00227 /**
00228   * @}
00229   */
00230
00231 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
00232   * @{
00233   */
00234 /* NAND State functions *******************************************************/
00235 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
00236 /**
00237   * @}
00238   */
00239
00240 /**
00241   * @}
00242   */
00243
00244 /* Private types -------------------------------------------------------------*/
00245 /* Private variables ---------------------------------------------------------*/
00246 /* Private constants ---------------------------------------------------------*/
00247 /** @defgroup NAND_Private_Constants NAND Private Constants
00248   * @{
00249   */
00250 #define NAND_DEVICE1               FMC_BANK2
00251 #define NAND_DEVICE2               FMC_BANK3
00252 #define NAND_WRITE_TIMEOUT         0x01000000U
00253
00254 #define CMD_AREA                   ((uint32_t)(1U<<16U))  /* A16 = CLE high */
00255 #define ADDR_AREA                  ((uint32_t)(1U<<17U))  /* A17 = ALE high */
00256
00257 #define NAND_CMD_AREA_A            ((uint8_t)0x00)
00258 #define NAND_CMD_AREA_B            ((uint8_t)0x01)
00259 #define NAND_CMD_AREA_C            ((uint8_t)0x50)
00260 #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
00261
00262 #define NAND_CMD_WRITE0            ((uint8_t)0x80)
00263 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
00264 #define NAND_CMD_ERASE0            ((uint8_t)0x60)
00265 #define NAND_CMD_ERASE1            ((uint8_t)0xD0)
00266 #define NAND_CMD_READID            ((uint8_t)0x90)
00267 #define NAND_CMD_STATUS            ((uint8_t)0x70)
00268 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
00269 #define NAND_CMD_RESET             ((uint8_t)0xFF)
00270
00271 /* NAND memory status */
00272 #define NAND_VALID_ADDRESS         0x00000100U
00273 #define NAND_INVALID_ADDRESS       0x00000200U
00274 #define NAND_TIMEOUT_ERROR         0x00000400U
00275 #define NAND_BUSY                  0x00000000U
00276 #define NAND_ERROR                 0x00000001U
00277 #define NAND_READY                 0x00000040U
00278 /**
00279   * @}
00280   */
00281
00282 /* Private macros ------------------------------------------------------------*/
00283 /** @defgroup NAND_Private_Macros NAND Private Macros
00284   * @{
00285   */
00286
00287 /**
00288   * @brief  NAND memory address computation.
00289   * @param  __ADDRESS__ NAND memory address.
00290   * @param  __HANDLE__ NAND handle.
00291   * @retval NAND Raw address value
00292   */
00293 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
00294                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
00295
00296 /**
00297   * @brief  NAND memory Column address computation.
00298   * @param  __HANDLE__ NAND handle.
00299   * @retval NAND Raw address value
00300   */
00301 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
00302
00303 /**
00304   * @brief  NAND memory address cycling.
00305   * @param  __ADDRESS__ NAND memory address.
00306   * @retval NAND address cycling value.
00307   */
00308 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
00309 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
00310 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
00311 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
00312
00313 /**
00314   * @brief  NAND memory Columns cycling.
00315   * @param  __ADDRESS__ NAND memory address.
00316   * @retval NAND Column address cycling value.
00317   */
00318 #define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st Column addressing cycle */
00319 #define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */
00320
00321 /**
00322   * @}
00323   */
00324
00325 /**
00326   * @}
00327   */
00328 /**
00329   * @}
00330   */
00331
00332 /**
00333   * @}
00334   */
00335
00336 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
00337
00338 #ifdef __cplusplus
00339 }
00340 #endif
00341
00342 #endif /* __STM32F3xx_HAL_NAND_H */
00343
00344 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_nor.c Source File

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stm32f3xx_hal_nor.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_nor.c
00004   * @author  MCD Application Team
00005   * @brief   NOR HAL module driver.
00006   *          This file provides a generic firmware to drive NOR memories mounted
00007   *          as external device.
00008   *
00009   @verbatim
00010   ==============================================================================
00011                      ##### How to use this driver #####
00012   ==============================================================================
00013     [..]
00014       This driver is a generic layered driver which contains a set of APIs used to
00015       control NOR flash memories. It uses the FMC layer functions to interface
00016       with NOR devices. This driver is used as follows:
00017
00018       (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
00019           with control and timing parameters for both normal and extended mode.
00020
00021       (+) Read NOR flash memory manufacturer code and device IDs using the function
00022           HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
00023           structure declared by the function caller.
00024
00025       (+) Access NOR flash memory by read/write data unit operations using the functions
00026           HAL_NOR_Read(), HAL_NOR_Program().
00027
00028       (+) Perform NOR flash erase block/chip operations using the functions
00029           HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
00030
00031       (+) Read the NOR flash CFI (common flash interface) IDs using the function
00032           HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
00033           structure declared by the function caller.
00034
00035       (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
00036           HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
00037
00038       (+) You can monitor the NOR device HAL state by calling the function
00039           HAL_NOR_GetState()
00040     [..]
00041      (@) This driver is a set of generic APIs which handle standard NOR flash operations.
00042          If a NOR flash device contains different operations and/or implementations,
00043          it should be implemented separately.
00044
00045      *** NOR HAL driver macros list ***
00046      =============================================
00047      [..]
00048        Below the list of most used macros in NOR HAL driver.
00049
00050       (+) NOR_WRITE: NOR memory write data to specified address
00051
00052   @endverbatim
00053   ******************************************************************************
00054   * @attention
00055   *
00056   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00057   *
00058   * Redistribution and use in source and binary forms, with or without modification,
00059   * are permitted provided that the following conditions are met:
00060   *   1. Redistributions of source code must retain the above copyright notice,
00061   *      this list of conditions and the following disclaimer.
00062   *   2. Redistributions in binary form must reproduce the above copyright notice,
00063   *      this list of conditions and the following disclaimer in the documentation
00064   *      and/or other materials provided with the distribution.
00065   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00066   *      may be used to endorse or promote products derived from this software
00067   *      without specific prior written permission.
00068   *
00069   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00070   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00071   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00072   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00073   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00074   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00075   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00076   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00077   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00078   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00079   *
00080   ******************************************************************************
00081   */
00082
00083 /* Includes ------------------------------------------------------------------*/
00084 #include "stm32f3xx_hal.h"
00085
00086 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
00087
00088 /** @addtogroup STM32F3xx_HAL_Driver
00089   * @{
00090   */
00091
00092 #ifdef HAL_NOR_MODULE_ENABLED
00093 /** @defgroup NOR NOR
00094   * @brief NOR HAL module driver
00095   * @{
00096   */
00097 /* Private typedef -----------------------------------------------------------*/
00098 /* Private define ------------------------------------------------------------*/
00099 /** @defgroup NOR_Private_Constants NOR Private Constants
00100   * @{
00101   */
00102
00103 /* Constants to define address to set to write a command */
00104 #define NOR_CMD_ADDRESS_FIRST                 (uint16_t)0x0555
00105 #define NOR_CMD_ADDRESS_FIRST_CFI             (uint16_t)0x0055
00106 #define NOR_CMD_ADDRESS_SECOND                (uint16_t)0x02AA
00107 #define NOR_CMD_ADDRESS_THIRD                 (uint16_t)0x0555
00108 #define NOR_CMD_ADDRESS_FOURTH                (uint16_t)0x0555
00109 #define NOR_CMD_ADDRESS_FIFTH                 (uint16_t)0x02AA
00110 #define NOR_CMD_ADDRESS_SIXTH                 (uint16_t)0x0555
00111
00112 /* Constants to define data to program a command */
00113 #define NOR_CMD_DATA_READ_RESET               (uint16_t)0x00F0
00114 #define NOR_CMD_DATA_FIRST                    (uint16_t)0x00AA
00115 #define NOR_CMD_DATA_SECOND                   (uint16_t)0x0055
00116 #define NOR_CMD_DATA_AUTO_SELECT              (uint16_t)0x0090
00117 #define NOR_CMD_DATA_PROGRAM                  (uint16_t)0x00A0
00118 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD   (uint16_t)0x0080
00119 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH  (uint16_t)0x00AA
00120 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH   (uint16_t)0x0055
00121 #define NOR_CMD_DATA_CHIP_ERASE               (uint16_t)0x0010
00122 #define NOR_CMD_DATA_CFI                      (uint16_t)0x0098
00123
00124 #define NOR_CMD_DATA_BUFFER_AND_PROG          (uint8_t)0x25
00125 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM  (uint8_t)0x29
00126 #define NOR_CMD_DATA_BLOCK_ERASE              (uint8_t)0x30
00127
00128 /* Mask on NOR STATUS REGISTER */
00129 #define NOR_MASK_STATUS_DQ5                   (uint16_t)0x0020
00130 #define NOR_MASK_STATUS_DQ6                   (uint16_t)0x0040
00131
00132 /**
00133   * @}
00134   */
00135
00136 /* Private macro -------------------------------------------------------------*/
00137 /** @defgroup NOR_Private_Macros NOR Private Macros
00138   * @{
00139   */
00140
00141 /**
00142   * @}
00143   */
00144
00145 /* Private variables ---------------------------------------------------------*/
00146
00147 /** @defgroup NOR_Private_Variables NOR Private Variables
00148  * @{
00149  */
00150
00151 static uint32_t uwNORMemoryDataWidth  = NOR_MEMORY_8B;
00152
00153 /**
00154   * @}
00155   */
00156
00157 /* Exported functions ---------------------------------------------------------*/
00158
00159 /** @defgroup NOR_Exported_Functions NOR Exported Functions
00160   * @{
00161   */
00162
00163 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
00164   * @brief    Initialization and Configuration functions
00165   *
00166   @verbatim
00167   ==============================================================================
00168            ##### NOR Initialization and de_initialization functions #####
00169   ==============================================================================
00170   [..]
00171     This section provides functions allowing to initialize/de-initialize
00172     the NOR memory
00173
00174 @endverbatim
00175   * @{
00176   */
00177
00178 /**
00179   * @brief  Perform the NOR memory Initialization sequence
00180   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00181   *                the configuration information for NOR module.
00182   * @param  Timing pointer to NOR control timing structure
00183   * @param  ExtTiming pointer to NOR extended mode timing structure
00184   * @retval HAL status
00185   */
00186 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
00187 {
00188   /* Check the NOR handle parameter */
00189   if(hnor == NULL)
00190   {
00191      return HAL_ERROR;
00192   }
00193
00194   if(hnor->State == HAL_NOR_STATE_RESET)
00195   {
00196     /* Allocate lock resource and initialize it */
00197     hnor->Lock = HAL_UNLOCKED;
00198
00199     /* Initialize the low level hardware (MSP) */
00200     HAL_NOR_MspInit(hnor);
00201   }
00202
00203   /* Initialize NOR control Interface */
00204   FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
00205
00206   /* Initialize NOR timing Interface */
00207   FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
00208
00209   /* Initialize NOR extended mode timing Interface */
00210   FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
00211
00212   /* Enable the NORSRAM device */
00213   __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
00214
00215   /* Initialize NOR Memory Data Width*/
00216   if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
00217   {
00218     uwNORMemoryDataWidth = NOR_MEMORY_8B;
00219   }
00220   else
00221   {
00222     uwNORMemoryDataWidth = NOR_MEMORY_16B;
00223   }
00224
00225   /* Check the NOR controller state */
00226   hnor->State = HAL_NOR_STATE_READY;
00227
00228   return HAL_OK;
00229 }
00230
00231 /**
00232   * @brief  Perform NOR memory De-Initialization sequence
00233   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00234   *                the configuration information for NOR module.
00235   * @retval HAL status
00236   */
00237 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
00238 {
00239   /* De-Initialize the low level hardware (MSP) */
00240   HAL_NOR_MspDeInit(hnor);
00241
00242   /* Configure the NOR registers with their reset values */
00243   FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
00244
00245   /* Update the NOR controller state */
00246   hnor->State = HAL_NOR_STATE_RESET;
00247
00248   /* Release Lock */
00249   __HAL_UNLOCK(hnor);
00250
00251   return HAL_OK;
00252 }
00253
00254 /**
00255   * @brief  NOR MSP Init
00256   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00257   *                the configuration information for NOR module.
00258   * @retval None
00259   */
00260 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
00261 {
00262   /* Prevent unused argument(s) compilation warning */
00263   UNUSED(hnor);
00264
00265   /* NOTE : This function Should not be modified, when the callback is needed,
00266             the HAL_NOR_MspInit could be implemented in the user file
00267    */
00268 }
00269
00270 /**
00271   * @brief  NOR MSP DeInit
00272   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00273   *                the configuration information for NOR module.
00274   * @retval None
00275   */
00276 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
00277 {
00278   /* Prevent unused argument(s) compilation warning */
00279   UNUSED(hnor);
00280
00281   /* NOTE : This function Should not be modified, when the callback is needed,
00282             the HAL_NOR_MspDeInit could be implemented in the user file
00283    */
00284 }
00285
00286 /**
00287   * @brief  NOR MSP Wait fro Ready/Busy signal
00288   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00289   *                the configuration information for NOR module.
00290   * @param  Timeout Maximum timeout value
00291   * @retval None
00292   */
00293 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
00294 {
00295   /* Prevent unused argument(s) compilation warning */
00296   UNUSED(hnor);
00297   UNUSED(Timeout);
00298
00299   /* NOTE : This function Should not be modified, when the callback is needed,
00300             the HAL_NOR_MspWait could be implemented in the user file
00301    */
00302 }
00303
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
00309   * @brief    Input Output and memory control functions
00310   *
00311   @verbatim
00312   ==============================================================================
00313                 ##### NOR Input and Output functions #####
00314   ==============================================================================
00315   [..]
00316     This section provides functions allowing to use and control the NOR memory
00317
00318 @endverbatim
00319   * @{
00320   */
00321
00322 /**
00323   * @brief  Read NOR flash IDs
00324   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00325   *                the configuration information for NOR module.
00326   * @param  pNOR_ID pointer to NOR ID structure
00327   * @retval HAL status
00328   */
00329 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
00330 {
00331   uint32_t deviceaddress = 0U;
00332
00333   /* Process Locked */
00334   __HAL_LOCK(hnor);
00335
00336   /* Check the NOR controller state */
00337   if(hnor->State == HAL_NOR_STATE_BUSY)
00338   {
00339      return HAL_BUSY;
00340   }
00341
00342   /* Select the NOR device address */
00343   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00344   {
00345     deviceaddress = NOR_MEMORY_ADRESS1;
00346   }
00347   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00348   {
00349     deviceaddress = NOR_MEMORY_ADRESS2;
00350   }
00351   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00352   {
00353     deviceaddress = NOR_MEMORY_ADRESS3;
00354   }
00355   else /* FMC_NORSRAM_BANK4 */
00356   {
00357     deviceaddress = NOR_MEMORY_ADRESS4;
00358   }
00359
00360   /* Update the NOR controller state */
00361   hnor->State = HAL_NOR_STATE_BUSY;
00362
00363   /* Send read ID command */
00364   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00365   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00366   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
00367
00368   /* Read the NOR IDs */
00369   pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
00370   pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
00371   pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
00372   pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
00373
00374   /* Check the NOR controller state */
00375   hnor->State = HAL_NOR_STATE_READY;
00376
00377   /* Process unlocked */
00378   __HAL_UNLOCK(hnor);
00379
00380   return HAL_OK;
00381 }
00382
00383 /**
00384   * @brief  Returns the NOR memory to Read mode.
00385   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00386   *                the configuration information for NOR module.
00387   * @retval HAL status
00388   */
00389 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
00390 {
00391   uint32_t deviceaddress = 0U;
00392
00393   /* Process Locked */
00394   __HAL_LOCK(hnor);
00395
00396   /* Check the NOR controller state */
00397   if(hnor->State == HAL_NOR_STATE_BUSY)
00398   {
00399      return HAL_BUSY;
00400   }
00401
00402   /* Select the NOR device address */
00403   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00404   {
00405     deviceaddress = NOR_MEMORY_ADRESS1;
00406   }
00407   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00408   {
00409     deviceaddress = NOR_MEMORY_ADRESS2;
00410   }
00411   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00412   {
00413     deviceaddress = NOR_MEMORY_ADRESS3;
00414   }
00415   else /* FMC_NORSRAM_BANK4 */
00416   {
00417     deviceaddress = NOR_MEMORY_ADRESS4;
00418   }
00419
00420   NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
00421
00422   /* Check the NOR controller state */
00423   hnor->State = HAL_NOR_STATE_READY;
00424
00425   /* Process unlocked */
00426   __HAL_UNLOCK(hnor);
00427
00428   return HAL_OK;
00429 }
00430
00431 /**
00432   * @brief  Read data from NOR memory
00433   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00434   *                the configuration information for NOR module.
00435   * @param  pAddress pointer to Device address
00436   * @param  pData pointer to read data
00437   * @retval HAL status
00438   */
00439 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
00440 {
00441   uint32_t deviceaddress = 0U;
00442
00443   /* Process Locked */
00444   __HAL_LOCK(hnor);
00445
00446   /* Check the NOR controller state */
00447   if(hnor->State == HAL_NOR_STATE_BUSY)
00448   {
00449      return HAL_BUSY;
00450   }
00451
00452   /* Select the NOR device address */
00453   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00454   {
00455     deviceaddress = NOR_MEMORY_ADRESS1;
00456   }
00457   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00458   {
00459     deviceaddress = NOR_MEMORY_ADRESS2;
00460   }
00461   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00462   {
00463     deviceaddress = NOR_MEMORY_ADRESS3;
00464   }
00465   else /* FMC_NORSRAM_BANK4 */
00466   {
00467     deviceaddress = NOR_MEMORY_ADRESS4;
00468   }
00469
00470   /* Update the NOR controller state */
00471   hnor->State = HAL_NOR_STATE_BUSY;
00472
00473   /* Send read data command */
00474   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00475   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00476   NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
00477
00478   /* Read the data */
00479   *pData = *(__IO uint32_t *)(uint32_t)pAddress;
00480
00481   /* Check the NOR controller state */
00482   hnor->State = HAL_NOR_STATE_READY;
00483
00484   /* Process unlocked */
00485   __HAL_UNLOCK(hnor);
00486
00487   return HAL_OK;
00488 }
00489
00490 /**
00491   * @brief  Program data to NOR memory
00492   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00493   *                the configuration information for NOR module.
00494   * @param  pAddress Device address
00495   * @param  pData pointer to the data to write
00496   * @retval HAL status
00497   */
00498 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
00499 {
00500   uint32_t deviceaddress = 0U;
00501
00502   /* Process Locked */
00503   __HAL_LOCK(hnor);
00504
00505   /* Check the NOR controller state */
00506   if(hnor->State == HAL_NOR_STATE_BUSY)
00507   {
00508      return HAL_BUSY;
00509   }
00510
00511   /* Select the NOR device address */
00512   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00513   {
00514     deviceaddress = NOR_MEMORY_ADRESS1;
00515   }
00516   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00517   {
00518     deviceaddress = NOR_MEMORY_ADRESS2;
00519   }
00520   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00521   {
00522     deviceaddress = NOR_MEMORY_ADRESS3;
00523   }
00524   else /* FMC_NORSRAM_BANK4 */
00525   {
00526     deviceaddress = NOR_MEMORY_ADRESS4;
00527   }
00528
00529   /* Update the NOR controller state */
00530   hnor->State = HAL_NOR_STATE_BUSY;
00531
00532   /* Send program data command */
00533   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00534   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00535   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
00536
00537   /* Write the data */
00538  NOR_WRITE(pAddress, *pData);
00539
00540   /* Check the NOR controller state */
00541   hnor->State = HAL_NOR_STATE_READY;
00542
00543   /* Process unlocked */
00544   __HAL_UNLOCK(hnor);
00545
00546   return HAL_OK;
00547 }
00548
00549 /**
00550   * @brief  Reads a block of data from the FMC NOR memory.
00551   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00552   *                the configuration information for NOR module.
00553   * @param  uwAddress NOR memory internal address to read from.
00554   * @param  pData pointer to the buffer that receives the data read from the
00555   *         NOR memory.
00556   * @param  uwBufferSize number of Half word to read.
00557   * @retval HAL status
00558   */
00559 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
00560 {
00561   uint32_t deviceaddress = 0U;
00562
00563   /* Process Locked */
00564   __HAL_LOCK(hnor);
00565
00566   /* Check the NOR controller state */
00567   if(hnor->State == HAL_NOR_STATE_BUSY)
00568   {
00569      return HAL_BUSY;
00570   }
00571
00572   /* Select the NOR device address */
00573   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00574   {
00575     deviceaddress = NOR_MEMORY_ADRESS1;
00576   }
00577   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00578   {
00579     deviceaddress = NOR_MEMORY_ADRESS2;
00580   }
00581   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00582   {
00583     deviceaddress = NOR_MEMORY_ADRESS3;
00584   }
00585   else /* FMC_NORSRAM_BANK4 */
00586   {
00587     deviceaddress = NOR_MEMORY_ADRESS4;
00588   }
00589
00590   /* Update the NOR controller state */
00591   hnor->State = HAL_NOR_STATE_BUSY;
00592
00593   /* Send read data command */
00594   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00595   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00596   NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
00597
00598   /* Read buffer */
00599   while( uwBufferSize > 0U)
00600   {
00601     *pData++ = *(__IO uint16_t *)uwAddress;
00602     uwAddress += 2U;
00603     uwBufferSize--;
00604   }
00605
00606   /* Check the NOR controller state */
00607   hnor->State = HAL_NOR_STATE_READY;
00608
00609   /* Process unlocked */
00610   __HAL_UNLOCK(hnor);
00611
00612   return HAL_OK;
00613 }
00614
00615 /**
00616   * @brief  Writes a half-word buffer to the FMC NOR memory. This function
00617   *         must be used only with S29GL128P NOR memory.
00618   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00619   *                the configuration information for NOR module.
00620   * @param  uwAddress NOR memory internal address from which the data
00621   * @note   Some NOR memory need Address aligned to xx bytes (can be aligned to
00622   *          64 bytes boundary for example).
00623   * @param  pData pointer to source data buffer.
00624   * @param  uwBufferSize number of Half words to write.
00625   * @note   The maximum buffer size allowed is NOR memory dependent
00626   *         (can be 64 Bytes max for example).
00627   * @retval HAL status
00628   */
00629 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
00630 {
00631   uint16_t * p_currentaddress = (uint16_t *)NULL;
00632   uint16_t * p_endaddress = (uint16_t *)NULL;
00633   uint32_t lastloadedaddress = 0U, deviceaddress = 0U;
00634
00635   /* Process Locked */
00636   __HAL_LOCK(hnor);
00637
00638   /* Check the NOR controller state */
00639   if(hnor->State == HAL_NOR_STATE_BUSY)
00640   {
00641     return HAL_BUSY;
00642   }
00643
00644   /* Select the NOR device address */
00645   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00646   {
00647     deviceaddress = NOR_MEMORY_ADRESS1;
00648   }
00649   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00650   {
00651     deviceaddress = NOR_MEMORY_ADRESS2;
00652   }
00653   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00654   {
00655     deviceaddress = NOR_MEMORY_ADRESS3;
00656   }
00657   else /* FMC_NORSRAM_BANK4 */
00658   {
00659     deviceaddress = NOR_MEMORY_ADRESS4;
00660   }
00661
00662   /* Update the NOR controller state */
00663   hnor->State = HAL_NOR_STATE_BUSY;
00664
00665   /* Initialize variables */
00666   p_currentaddress  = (uint16_t*)((uint32_t)(uwAddress));
00667   p_endaddress      = p_currentaddress + (uwBufferSize-1U);
00668   lastloadedaddress = (uint32_t)(uwAddress);
00669
00670   /* Issue unlock command sequence */
00671   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00672   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00673
00674   /* Write Buffer Load Command */
00675   NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
00676   NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1U));
00677
00678   /* Load Data into NOR Buffer */
00679   while(p_currentaddress <= p_endaddress)
00680   {
00681     /* Store last loaded address & data value (for polling) */
00682     lastloadedaddress = (uint32_t)p_currentaddress;
00683
00684     NOR_WRITE(p_currentaddress, *pData++);
00685
00686     p_currentaddress++;
00687   }
00688
00689   NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
00690
00691   /* Check the NOR controller state */
00692   hnor->State = HAL_NOR_STATE_READY;
00693
00694   /* Process unlocked */
00695   __HAL_UNLOCK(hnor);
00696
00697   return HAL_OK;
00698
00699 }
00700
00701 /**
00702   * @brief  Erase the specified block of the NOR memory
00703   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00704   *                the configuration information for NOR module.
00705   * @param  BlockAddress Block to erase address
00706   * @param  Address Device address
00707   * @retval HAL status
00708   */
00709 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
00710 {
00711   uint32_t deviceaddress = 0U;
00712
00713   /* Process Locked */
00714   __HAL_LOCK(hnor);
00715
00716   /* Check the NOR controller state */
00717   if(hnor->State == HAL_NOR_STATE_BUSY)
00718   {
00719      return HAL_BUSY;
00720   }
00721
00722   /* Select the NOR device address */
00723   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00724   {
00725     deviceaddress = NOR_MEMORY_ADRESS1;
00726   }
00727   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00728   {
00729     deviceaddress = NOR_MEMORY_ADRESS2;
00730   }
00731   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00732   {
00733     deviceaddress = NOR_MEMORY_ADRESS3;
00734   }
00735   else /* FMC_NORSRAM_BANK4 */
00736   {
00737     deviceaddress = NOR_MEMORY_ADRESS4;
00738   }
00739
00740   /* Update the NOR controller state */
00741   hnor->State = HAL_NOR_STATE_BUSY;
00742
00743   /* Send block erase command sequence */
00744   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00745   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00746   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
00747   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
00748   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
00749   NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
00750
00751   /* Check the NOR memory status and update the controller state */
00752   hnor->State = HAL_NOR_STATE_READY;
00753
00754   /* Process unlocked */
00755   __HAL_UNLOCK(hnor);
00756
00757   return HAL_OK;
00758
00759 }
00760
00761 /**
00762   * @brief  Erase the entire NOR chip.
00763   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00764   *                the configuration information for NOR module.
00765   * @param  Address Device address
00766   * @retval HAL status
00767   */
00768 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
00769 {
00770   uint32_t deviceaddress = 0U;
00771
00772   /* Process Locked */
00773   __HAL_LOCK(hnor);
00774
00775   /* Check the NOR controller state */
00776   if(hnor->State == HAL_NOR_STATE_BUSY)
00777   {
00778      return HAL_BUSY;
00779   }
00780
00781   /* Select the NOR device address */
00782   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00783   {
00784     deviceaddress = NOR_MEMORY_ADRESS1;
00785   }
00786   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00787   {
00788     deviceaddress = NOR_MEMORY_ADRESS2;
00789   }
00790   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00791   {
00792     deviceaddress = NOR_MEMORY_ADRESS3;
00793   }
00794   else /* FMC_NORSRAM_BANK4 */
00795   {
00796     deviceaddress = NOR_MEMORY_ADRESS4;
00797   }
00798
00799   /* Update the NOR controller state */
00800   hnor->State = HAL_NOR_STATE_BUSY;
00801
00802   /* Send NOR chip erase command sequence */
00803   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00804   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00805   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
00806   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
00807   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
00808   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
00809
00810   /* Check the NOR memory status and update the controller state */
00811   hnor->State = HAL_NOR_STATE_READY;
00812
00813   /* Process unlocked */
00814   __HAL_UNLOCK(hnor);
00815
00816   return HAL_OK;
00817 }
00818
00819 /**
00820   * @brief  Read NOR flash CFI IDs
00821   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00822   *                the configuration information for NOR module.
00823   * @param  pNOR_CFI pointer to NOR CFI IDs structure
00824   * @retval HAL status
00825   */
00826 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
00827 {
00828   uint32_t deviceaddress = 0U;
00829
00830   /* Process Locked */
00831   __HAL_LOCK(hnor);
00832
00833   /* Check the NOR controller state */
00834   if(hnor->State == HAL_NOR_STATE_BUSY)
00835   {
00836      return HAL_BUSY;
00837   }
00838
00839   /* Select the NOR device address */
00840   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00841   {
00842     deviceaddress = NOR_MEMORY_ADRESS1;
00843   }
00844   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00845   {
00846     deviceaddress = NOR_MEMORY_ADRESS2;
00847   }
00848   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00849   {
00850     deviceaddress = NOR_MEMORY_ADRESS3;
00851   }
00852   else /* FMC_NORSRAM_BANK4 */
00853   {
00854     deviceaddress = NOR_MEMORY_ADRESS4;
00855   }
00856
00857   /* Update the NOR controller state */
00858   hnor->State = HAL_NOR_STATE_BUSY;
00859
00860   /* Send read CFI query command */
00861   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
00862
00863   /* read the NOR CFI information */
00864   pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
00865   pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
00866   pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
00867   pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
00868
00869   /* Check the NOR controller state */
00870   hnor->State = HAL_NOR_STATE_READY;
00871
00872   /* Process unlocked */
00873   __HAL_UNLOCK(hnor);
00874
00875   return HAL_OK;
00876 }
00877
00878 /**
00879   * @}
00880   */
00881
00882 /** @defgroup NOR_Exported_Functions_Group3 Peripheral Control functions
00883  *  @brief   management functions
00884  *
00885 @verbatim
00886   ==============================================================================
00887                         ##### NOR Control functions #####
00888   ==============================================================================
00889   [..]
00890     This subsection provides a set of functions allowing to control dynamically
00891     the NOR interface.
00892
00893 @endverbatim
00894   * @{
00895   */
00896
00897 /**
00898   * @brief  Enables dynamically NOR write operation.
00899   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00900   *                the configuration information for NOR module.
00901   * @retval HAL status
00902   */
00903 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
00904 {
00905   /* Process Locked */
00906   __HAL_LOCK(hnor);
00907
00908   /* Enable write operation */
00909   FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
00910
00911   /* Update the NOR controller state */
00912   hnor->State = HAL_NOR_STATE_READY;
00913
00914   /* Process unlocked */
00915   __HAL_UNLOCK(hnor);
00916
00917   return HAL_OK;
00918 }
00919
00920 /**
00921   * @brief  Disables dynamically NOR write operation.
00922   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00923   *                the configuration information for NOR module.
00924   * @retval HAL status
00925   */
00926 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
00927 {
00928   /* Process Locked */
00929   __HAL_LOCK(hnor);
00930
00931   /* Update the SRAM controller state */
00932   hnor->State = HAL_NOR_STATE_BUSY;
00933
00934   /* Disable write operation */
00935   FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
00936
00937   /* Update the NOR controller state */
00938   hnor->State = HAL_NOR_STATE_PROTECTED;
00939
00940   /* Process unlocked */
00941   __HAL_UNLOCK(hnor);
00942
00943   return HAL_OK;
00944 }
00945
00946 /**
00947   * @}
00948   */
00949
00950 /** @defgroup NOR_Exported_Functions_Group4 Peripheral State functions
00951  *  @brief   Peripheral State functions
00952  *
00953 @verbatim
00954   ==============================================================================
00955                       ##### NOR State functions #####
00956   ==============================================================================
00957   [..]
00958     This subsection permits to get in run-time the status of the NOR controller
00959     and the data flow.
00960
00961 @endverbatim
00962   * @{
00963   */
00964
00965 /**
00966   * @brief  return the NOR controller state
00967   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00968   *                the configuration information for NOR module.
00969   * @retval NOR controller state
00970   */
00971 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
00972 {
00973   return hnor->State;
00974 }
00975
00976 /**
00977   * @brief  Returns the NOR operation status.
00978   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00979   *                the configuration information for NOR module.
00980   * @param  Address Device address
00981   * @param  Timeout NOR progamming Timeout
00982   * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
00983   *         or HAL_NOR_STATUS_TIMEOUT
00984   */
00985 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
00986 {
00987   HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
00988   uint16_t tmp_sr1 = 0U, tmp_sr2 = 0U;
00989   uint32_t tickstart = 0U;
00990
00991   /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
00992   HAL_NOR_MspWait(hnor, Timeout);
00993
00994   /* Get tick */
00995   tickstart = HAL_GetTick();
00996   while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
00997   {
00998     /* Check for the Timeout */
00999     if(Timeout != HAL_MAX_DELAY)
01000     {
01001       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01002     {
01003       status = HAL_NOR_STATUS_TIMEOUT;
01004     }
01005     }
01006
01007     /* Read NOR status register (DQ6 and DQ5) */
01008     tmp_sr1 = *(__IO uint16_t *)Address;
01009     tmp_sr2 = *(__IO uint16_t *)Address;
01010
01011     /* If DQ6 did not toggle between the two reads then return NOR_Success */
01012     if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
01013     {
01014       return HAL_NOR_STATUS_SUCCESS;
01015     }
01016
01017     if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
01018     {
01019       status = HAL_NOR_STATUS_ONGOING;
01020     }
01021
01022     tmp_sr1 = *(__IO uint16_t *)Address;
01023     tmp_sr2 = *(__IO uint16_t *)Address;
01024
01025     /* If DQ6 did not toggle between the two reads then return NOR_Success */
01026     if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
01027     {
01028       return HAL_NOR_STATUS_SUCCESS;
01029     }
01030     else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
01031     {
01032       return HAL_NOR_STATUS_ERROR;
01033     }
01034   }
01035
01036   /* Return the operation status */
01037   return status;
01038 }
01039
01040 /**
01041   * @}
01042   */
01043
01044 /**
01045   * @}
01046   */
01047 /**
01048   * @}
01049   */
01050 #endif /* HAL_NOR_MODULE_ENABLED */
01051
01052 /**
01053   * @}
01054   */
01055 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
01056
01057 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_nor.h Source File

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stm32f3xx_hal_nor.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_nor.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of NOR HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_NOR_H
00038 #define __STM32F3xx_HAL_NOR_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
00046 #include "stm32f3xx_ll_fmc.h"
00047
00048 /** @addtogroup STM32F3xx_HAL_Driver
00049   * @{
00050   */
00051
00052 /** @addtogroup NOR
00053   * @{
00054   */
00055
00056
00057 /** @addtogroup NOR_Private_Constants
00058   * @{
00059   */
00060
00061 /* NOR device IDs addresses */
00062 #define MC_ADDRESS               ((uint16_t)0x0000U)
00063 #define DEVICE_CODE1_ADDR        ((uint16_t)0x0001U)
00064 #define DEVICE_CODE2_ADDR        ((uint16_t)0x000EU)
00065 #define DEVICE_CODE3_ADDR        ((uint16_t)0x000FU)
00066
00067 /* NOR CFI IDs addresses */
00068 #define CFI1_ADDRESS             ((uint16_t)0x10U)
00069 #define CFI2_ADDRESS             ((uint16_t)0x11U)
00070 #define CFI3_ADDRESS             ((uint16_t)0x12U)
00071 #define CFI4_ADDRESS             ((uint16_t)0x13U)
00072
00073 /* NOR memory data width */
00074 #define NOR_MEMORY_8B            ((uint8_t)0x0U)
00075 #define NOR_MEMORY_16B           ((uint8_t)0x1U)
00076
00077 /* NOR memory device read/write start address */
00078 #define NOR_MEMORY_ADRESS1       FMC_BANK1_1
00079 #define NOR_MEMORY_ADRESS2       FMC_BANK1_2
00080 #define NOR_MEMORY_ADRESS3       FMC_BANK1_3
00081 #define NOR_MEMORY_ADRESS4       FMC_BANK1_4
00082
00083 /**
00084   * @}
00085   */
00086
00087 /** @addtogroup NOR_Private_Macros
00088   * @{
00089   */
00090
00091 /**
00092   * @brief  NOR memory address shifting.
00093   * @param  __NOR_ADDRESS NOR base address
00094   * @param  __NOR_MEMORY_WIDTH_ NOR memory width
00095   * @param  __ADDRESS__ NOR memory address
00096   * @retval NOR shifted address value
00097   */
00098 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)       \
00099             ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?              \
00100               ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))):              \
00101               ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
00102
00103 /**
00104   * @brief  NOR memory write data to specified address.
00105   * @param  __ADDRESS__ NOR memory address
00106   * @param  __DATA__ Data to write
00107   * @retval None
00108   */
00109 #define NOR_WRITE(__ADDRESS__, __DATA__)  (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
00110
00111 /**
00112   * @}
00113   */
00114
00115 /* Exported typedef ----------------------------------------------------------*/
00116 /** @defgroup NOR_Exported_Types NOR Exported Types
00117   * @{
00118   */
00119
00120 /**
00121   * @brief  HAL SRAM State structures definition
00122   */
00123 typedef enum
00124 {
00125   HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */
00126   HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */
00127   HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */
00128   HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */
00129   HAL_NOR_STATE_PROTECTED         = 0x04   /*!< NOR NORSRAM device write protected  */
00130 }HAL_NOR_StateTypeDef;
00131
00132 /**
00133   * @brief  FMC NOR Status typedef
00134   */
00135 typedef enum
00136 {
00137   HAL_NOR_STATUS_SUCCESS = 0U,
00138   HAL_NOR_STATUS_ONGOING,
00139   HAL_NOR_STATUS_ERROR,
00140   HAL_NOR_STATUS_TIMEOUT
00141 }HAL_NOR_StatusTypeDef;
00142
00143 /**
00144   * @brief  FMC NOR ID typedef
00145   */
00146 typedef struct
00147 {
00148   uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
00149
00150   uint16_t Device_Code1;
00151
00152   uint16_t Device_Code2;
00153
00154   uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
00155                                     These codes can be accessed by performing read operations with specific
00156                                     control signals and addresses set.They can also be accessed by issuing
00157                                     an Auto Select command.                                                   */
00158 }NOR_IDTypeDef;
00159
00160 /**
00161   * @brief  FMC NOR CFI typedef
00162   */
00163 typedef struct
00164 {
00165   uint16_t CFI_1;
00166
00167   uint16_t CFI_2;
00168
00169   uint16_t CFI_3;
00170
00171   uint16_t CFI_4;  /*!< Defines the information stored in the memory's Common flash interface
00172                         which contains a description of various electrical and timing parameters,
00173                         density information and functions supported by the memory.                   */
00174 }NOR_CFITypeDef;
00175
00176 /**
00177   * @brief  NOR handle Structure definition
00178   */
00179 typedef struct
00180 {
00181   FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
00182
00183   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
00184
00185   FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
00186
00187   HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
00188
00189   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
00190
00191 }NOR_HandleTypeDef;
00192
00193 /**
00194   * @}
00195   */
00196
00197 /* Exported constants --------------------------------------------------------*/
00198 /* Exported macro ------------------------------------------------------------*/
00199 /** @defgroup NOR_Exported_Macros NOR Exported Macros
00200   * @{
00201   */
00202
00203 /** @brief Reset NOR handle state
00204   * @param  __HANDLE__ NOR handle
00205   * @retval None
00206   */
00207 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
00208
00209 /**
00210   * @}
00211   */
00212
00213 /* Exported functions --------------------------------------------------------*/
00214 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
00215   * @{
00216   */
00217
00218 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
00219   * @{
00220   */
00221
00222 /* Initialization/de-initialization functions  ********************************/
00223 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
00224 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
00225 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
00226 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
00227 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
00228
00229 /**
00230   * @}
00231   */
00232
00233 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
00234   * @{
00235   */
00236
00237 /* I/O operation functions  ***************************************************/
00238 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
00239 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
00240 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00241 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00242
00243 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
00244 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
00245
00246 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
00247 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
00248 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
00249
00250 /**
00251   * @}
00252   */
00253
00254 /** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions
00255   * @{
00256   */
00257
00258 /* NOR Control functions  *****************************************************/
00259 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
00260 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
00261
00262 /**
00263   * @}
00264   */
00265
00266 /** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions
00267   * @{
00268   */
00269
00270 /* NOR State functions ********************************************************/
00271 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
00272 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
00273
00274 /**
00275   * @}
00276   */
00277
00278 /**
00279   * @}
00280   */
00281
00282 /**
00283   * @}
00284   */
00285
00286 /**
00287   * @}
00288   */
00289
00290 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
00291
00292 #ifdef __cplusplus
00293 }
00294 #endif
00295
00296 #endif /* __STM32F3xx_HAL_NOR_H */
00297
00298 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_opamp.c Source File

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stm32f3xx_hal_opamp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_opamp.c
00004   * @author  MCD Application Team
00005   * @brief   OPAMP HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the operational amplifiers (OPAMP1,...OPAMP4)
00008   *          peripheral:
00009   *           + OPAMP Configuration
00010   *           + OPAMP calibration
00011   *          Thanks to
00012   *           + Initialization/de-initialization functions
00013   *           + I/O operation functions
00014   *           + Peripheral Control functions
00015   *           + Peripheral State functions
00016   *
00017   @verbatim
00018 ================================================================================
00019           ##### OPAMP Peripheral Features #####
00020 ================================================================================
00021
00022   [..] The device integrates up to 4 operational amplifiers OPAMP1, OPAMP2,
00023        OPAMP3 and OPAMP4:
00024
00025        (#) The OPAMP(s) provides several exclusive running modes.
00026        (++) Standalone mode
00027        (++) Programmable Gain Amplifier (PGA) mode (Resistor feedback output)
00028        (++) Follower mode
00029
00030        (#) The OPAMP(s) provide(s) calibration capabilities.
00031        (++) Calibration aims at correcting some offset for running mode.
00032        (++) The OPAMP uses either factory calibration settings OR user defined
00033            calibration (trimming) settings (i.e. trimming mode).
00034        (++) The user defined settings can be figured out using self calibration
00035            handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
00036        (++) HAL_OPAMP_SelfCalibrate:
00037        (++) Runs automatically the calibration in 2 steps.
00038             (90U% of VDDA for NMOS transistors, 10U% of VDDA for PMOS transistors).
00039             (As OPAMP is Rail-to-rail input/output, these 2 steps calibration is
00040             appropriate and enough in most cases).
00041        (++) Enables the user trimming mode
00042        (++) Updates the init structure with trimming values with fresh calibration
00043             results.
00044             The user may store the calibration results for larger
00045             (ex monitoring the trimming as a function of temperature
00046             for instance)
00047        (++) for STM32F3 devices having 2 or 4 OPAMPs
00048             HAL_OPAMPEx_SelfCalibrateAll
00049             runs calibration of 2 or 4 OPAMPs in parallel.
00050
00051        (#) For any running mode, an additional Timer-controlled Mux (multiplexer)
00052            mode can be set on top.
00053        (++) Timer-controlled Mux mode allows Automatic switching between inverting
00054            and non-inverting input.
00055        (++) Hence on top of defaults (primary) inverting and non-inverting inputs,
00056            the user shall select secondary inverting and non inverting inputs.
00057        (++) TIM1 CC6 provides the alternate switching tempo between defaults
00058            (primary) and secondary inputs.
00059
00060        (#) Running mode: Standalone mode
00061        (++) Gain is set externally (gain depends on external loads).
00062        (++) Follower mode also possible externally by connecting the inverting input to
00063            the output.
00064
00065        (#) Running mode: Follower mode
00066        (++) No Inverting Input is connected.
00067
00068        (#) Running mode: Programmable Gain Amplifier (PGA) mode
00069            (Resistor feedback output)
00070        (++) The OPAMP(s) output(s) can be internally connected to resistor feedback
00071            output.
00072        (++) OPAMP gain is either 2U, 4U, 8 or 16.
00073
00074
00075             ##### How to use this driver #####
00076 ================================================================================
00077   [..]
00078     *** Calibration ***
00079     ============================================
00080     [..]
00081   To run the opamp calibration self calibration:
00082
00083       (#) Start calibration using HAL_OPAMP_SelfCalibrate.
00084            Store the calibration results.
00085
00086     *** Running mode ***
00087     ============================================
00088     [..]
00089   To use the opamp, perform the following steps:
00090
00091       (#) Fill in the HAL_OPAMP_MspInit() to
00092       (++) Configure the opamp input AND output in analog mode using
00093           HAL_GPIO_Init() to map the opamp output to the GPIO pin.
00094
00095       (#) Configure the opamp using HAL_OPAMP_Init() function:
00096       (++) Select the mode
00097       (++) Select the inverting input
00098       (++) Select the non-inverting input
00099       (++) Select if the Timer controlled Mux mode is enabled/disabled
00100       (++) If the Timer controlled Mux mode is enabled, select the secondary inverting input
00101       (++) If the Timer controlled Mux mode is enabled, Select the secondary non-inverting input
00102       (++) If PGA mode is enabled, Select if inverting input is connected.
00103       (++) Select either factory or user defined trimming mode.
00104       (++) If the user defined trimming mode is enabled, select PMOS & NMOS trimming values
00105           (typ. settings returned by HAL_OPAMP_SelfCalibrate function).
00106
00107       (#) Enable the opamp using HAL_OPAMP_Start() function.
00108
00109       (#) Disable the opamp using HAL_OPAMP_Stop() function.
00110
00111       (#) Lock the opamp in running mode using HAL_OPAMP_Lock() function. From then The configuration
00112           can  be modified
00113       (++) After HW reset
00114       (++) OR thanks to HAL_OPAMP_MspDeInit called (user defined) from HAL_OPAMP_DeInit.
00115
00116     *** Running mode: change of configuration while OPAMP ON  ***
00117     ============================================
00118     [..]
00119     To Re-configure OPAMP when OPAMP is ON (change on the fly)
00120       (#) If needed, Fill in the HAL_OPAMP_MspInit()
00121       (++) This is the case for instance if you wish to use new OPAMP I/O
00122
00123       (#) Configure the opamp using HAL_OPAMP_Init() function:
00124       (++) As in configure case, selects first the parameters you wish to modify.
00125
00126   @endverbatim
00127   ******************************************************************************
00128   * @attention
00129   *
00130   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00131   *
00132   * Redistribution and use in source and binary forms, with or without modification,
00133   * are permitted provided that the following conditions are met:
00134   *   1. Redistributions of source code must retain the above copyright notice,
00135   *      this list of conditions and the following disclaimer.
00136   *   2. Redistributions in binary form must reproduce the above copyright notice,
00137   *      this list of conditions and the following disclaimer in the documentation
00138   *      and/or other materials provided with the distribution.
00139   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00140   *      may be used to endorse or promote products derived from this software
00141   *      without specific prior written permission.
00142   *
00143   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00144   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00145   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00146   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00147   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00148   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00149   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00150   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00151   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00152   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00153   *
00154   ******************************************************************************
00155   */
00156
00157 /*
00158   Additional Tables:
00159     The OPAMPs non inverting input (both default and secondary) can be
00160     selected among the list shown by table below.
00161
00162     The OPAMPs non inverting input (both default and secondary) can be
00163     selected among the list shown by table below.
00164
00165     Table 1.  OPAMPs inverting/non-inverting inputs for the STM32F3 devices:
00166     +--------------------------------------------------------------+
00167     |                 |        | OPAMP1 | OPAMP2 | OPAMP3 | OPAMP4 |
00168     |-----------------|--------|--------|--------|--------|--------|
00169     |                 | No conn|   X    |   X    |   X    |   X    |
00170     | Inverting Input | VM0    |  PC5   |  PC5   |  PB10  |  PB10  |
00171     | (1)             | VM1    |  PA3   |  PA5   |  PB2   |  PD8   |
00172     |-----------------|--------|--------|--------|--------|--------|
00173     |                 | VP0    |  PA1   |  PA7   |  PB0   |  PB13  |
00174     |  Non Inverting  | VP1    |  PA7   |  PD14  |  PB13  |  PD11  |
00175     |    Input        | VP2    |  PA3   |  PB0   |  PA1   |  PA4   |
00176     |                 | VP3    |  PA5   |  PB14  |  PA5   |  PB11  |
00177     +--------------------------------------------------------------+
00178     (1): NA in follower mode.
00179
00180     Table 2.  OPAMPs outputs for the STM32F3 devices:
00181     +--------------------------------------------------------------+
00182     |                 |        | OPAMP1 | OPAMP2 | OPAMP3 | OPAMP4 |
00183     |-----------------|--------|--------|--------|--------|--------|
00184     | Output          |        |  PA2   |  PA6   |  PB1   |  PB12  |
00185     |-----------------|--------|--------|--------|--------|--------|
00186
00187 */
00188
00189 /* Includes ------------------------------------------------------------------*/
00190 #include "stm32f3xx_hal.h"
00191
00192 /** @addtogroup STM32F3xx_HAL_Driver
00193   * @{
00194   */
00195
00196 #ifdef HAL_OPAMP_MODULE_ENABLED
00197
00198 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00199     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00200     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00201     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00202
00203 /** @defgroup OPAMP OPAMP
00204   * @brief OPAMP HAL module driver
00205   * @{
00206   */
00207
00208 /* Private typedef -----------------------------------------------------------*/
00209 /* Private define ------------------------------------------------------------*/
00210 /** @defgroup OPAMP_Private_Define OPAMP Private Define
00211  * @{
00212  */
00213 /* CSR register reset value */
00214 #define OPAMP_CSR_RESET_VALUE             (0x00000000U)
00215 /**
00216   * @}
00217   */
00218
00219 /* Private macro -------------------------------------------------------------*/
00220 /* Private variables ---------------------------------------------------------*/
00221 /* Private function prototypes -----------------------------------------------*/
00222 /* Exported functions ---------------------------------------------------------*/
00223
00224 /** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
00225   * @{
00226   */
00227
00228 /** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
00229  *  @brief    Initialization and Configuration functions
00230  *
00231 @verbatim
00232  ===============================================================================
00233               ##### Initialization and de-initialization  functions #####
00234  ===============================================================================
00235     [..]  This section provides functions allowing to:
00236
00237 @endverbatim
00238   * @{
00239   */
00240
00241 /**
00242   * @brief  Initializes the OPAMP according to the specified
00243   *         parameters in the OPAMP_InitTypeDef and create the associated handle.
00244   * @note   If the selected opamp is locked, initialization can't be performed.
00245   *         To unlock the configuration, perform a system reset.
00246   * @param  hopamp OPAMP handle
00247   * @retval HAL status
00248   */
00249 HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
00250
00251 {
00252   HAL_StatusTypeDef status = HAL_OK;
00253
00254   /* Check the OPAMP handle allocation and lock status */
00255   /* Init not allowed if calibration is ongoing */
00256   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \
00257                       || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
00258   {
00259     return HAL_ERROR;
00260   }
00261   else
00262   {
00263
00264     /* Check the parameter */
00265     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00266
00267     /* Set OPAMP parameters */
00268     assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
00269     assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));
00270     if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
00271     {
00272       assert_param(IS_OPAMP_INVERTING_INPUT(hopamp->Init.InvertingInput));
00273     }
00274
00275     assert_param(IS_OPAMP_TIMERCONTROLLED_MUXMODE(hopamp->Init.TimerControlledMuxmode));
00276
00277     if ((hopamp->Init.TimerControlledMuxmode) == OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE)
00278     {
00279       assert_param(IS_OPAMP_SEC_NONINVERTINGINPUT(hopamp->Init.NonInvertingInputSecondary));
00280       if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
00281       {
00282         assert_param(IS_OPAMP_SEC_INVERTINGINPUT(hopamp->Init.InvertingInputSecondary));
00283       }
00284     }
00285
00286     if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
00287     {
00288       assert_param(IS_OPAMP_PGACONNECT(hopamp->Init.PgaConnect));
00289       assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain));
00290     }
00291
00292     assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
00293     if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER)
00294     {
00295       assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP));
00296       assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN));
00297     }
00298
00299     /* Init SYSCFG and the low level hardware to access opamp */
00300     __HAL_RCC_SYSCFG_CLK_ENABLE();
00301
00302     if(hopamp->State == HAL_OPAMP_STATE_RESET)
00303     {
00304       /* Allocate lock resource and initialize it */
00305       hopamp->Lock = HAL_UNLOCKED;
00306     }
00307
00308     /* Call MSP init function */
00309     HAL_OPAMP_MspInit(hopamp);
00310
00311     /* Set OPAMP parameters */
00312     /*     Set  bits according to hopamp->hopamp->Init.Mode value                                 */
00313     /*     Set  bits according to hopamp->hopamp->Init.InvertingInput value                       */
00314     /*     Set  bits according to hopamp->hopamp->Init.NonInvertingInput value                    */
00315     /*     Set  bits according to hopamp->hopamp->Init.TimerControlledMuxmode value               */
00316     /*     Set  bits according to hopamp->hopamp->Init.InvertingInputSecondary  value             */
00317     /*     Set  bits according to hopamp->hopamp->Init.NonInvertingInputSecondary value           */
00318     /*     Set  bits according to hopamp->hopamp->Init.PgaConnect value                           */
00319     /*     Set  bits according to hopamp->hopamp->Init.PgaGain value                              */
00320     /*     Set  bits according to hopamp->hopamp->Init.UserTrimming value                         */
00321     /*     Set  bits according to hopamp->hopamp->Init.TrimmingValueP value                       */
00322     /*     Set  bits according to hopamp->hopamp->Init.TrimmingValueN value                       */
00323
00324
00325     /* check if OPAMP_PGA_MODE & in Follower mode */
00326     /*   - InvertingInput                         */
00327     /*   - InvertingInputSecondary                */
00328     /* are Not Applicable                         */
00329
00330     if ((hopamp->Init.Mode == OPAMP_PGA_MODE) || (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE))
00331     {
00332       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK, \
00333                                         hopamp->Init.Mode | \
00334                                         hopamp->Init.NonInvertingInput | \
00335                                         hopamp->Init.TimerControlledMuxmode | \
00336                                         hopamp->Init.NonInvertingInputSecondary  | \
00337                                         hopamp->Init.PgaConnect | \
00338                                         hopamp->Init.PgaGain | \
00339                                         hopamp->Init.UserTrimming | \
00340                                         (hopamp->Init.TrimmingValueP << OPAMP_INPUT_NONINVERTING) | \
00341                                         (hopamp->Init.TrimmingValueN << OPAMP_INPUT_INVERTING));
00342
00343     }
00344     else /* OPAMP_STANDALONE_MODE */
00345     {
00346       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK, \
00347                                         hopamp->Init.Mode | \
00348                                         hopamp->Init.InvertingInput    | \
00349                                         hopamp->Init.NonInvertingInput | \
00350                                         hopamp->Init.TimerControlledMuxmode | \
00351                                         hopamp->Init.InvertingInputSecondary  | \
00352                                         hopamp->Init.NonInvertingInputSecondary  | \
00353                                         hopamp->Init.PgaConnect | \
00354                                         hopamp->Init.PgaGain | \
00355                                         hopamp->Init.UserTrimming | \
00356                                         (hopamp->Init.TrimmingValueP << OPAMP_INPUT_NONINVERTING) | \
00357                                         (hopamp->Init.TrimmingValueN << OPAMP_INPUT_INVERTING));
00358     }
00359
00360     /* Update the OPAMP state*/
00361     if (hopamp->State == HAL_OPAMP_STATE_RESET)
00362     {
00363       /* From RESET state to READY State */
00364     hopamp->State = HAL_OPAMP_STATE_READY;
00365     }
00366     /* else: remain in READY or BUSY state (no update) */
00367
00368     return status;
00369     }
00370 }
00371
00372
00373 /**
00374   * @brief  DeInitializes the OPAMP peripheral
00375   * @note   Deinitialization can't be performed if the OPAMP configuration is locked.
00376   *         To unlock the configuration, perform a system reset.
00377   * @param  hopamp OPAMP handle
00378   * @retval HAL status
00379   */
00380 HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
00381 {
00382   HAL_StatusTypeDef status = HAL_OK;
00383
00384   /* Check the OPAMP handle allocation */
00385   /* DeInit not allowed if calibration is ongoing */
00386   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
00387   {
00388     status = HAL_ERROR;
00389   }
00390   else
00391   {
00392     /* Check the parameter */
00393     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00394
00395     /* Set OPAMP_CSR register to reset value */
00396     WRITE_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_VALUE);
00397
00398     /* DeInit the low level hardware: GPIO, CLOCK and NVIC */
00399     /* When OPAMP is locked, unlocking can be achieved thanks to */
00400     /* __HAL_RCC_SYSCFG_CLK_DISABLE() call within HAL_OPAMP_MspDeInit */
00401     /* Note that __HAL_RCC_SYSCFG_CLK_DISABLE() also disables comparator */
00402     HAL_OPAMP_MspDeInit(hopamp);
00403
00404     if (OPAMP_CSR_RESET_VALUE == hopamp->Instance->CSR)
00405     {
00406       /* Update the OPAMP state */
00407       hopamp->State = HAL_OPAMP_STATE_RESET;
00408     }
00409     else /* RESET STATE */
00410     {
00411       /* DeInit not complete */
00412       /* It can be the case if OPAMP was formerly locked */
00413       status = HAL_ERROR;
00414
00415       /* The OPAMP state is NOT updated */
00416     }
00417
00418     /* Process unlocked */
00419     __HAL_UNLOCK(hopamp);
00420   }
00421
00422   return status;
00423 }
00424
00425 /**
00426   * @brief  Initializes the OPAMP MSP.
00427   * @param  hopamp OPAMP handle
00428   * @retval None
00429   */
00430 __weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
00431 {
00432   /* Prevent unused argument(s) compilation warning */
00433   UNUSED(hopamp);
00434
00435   /* NOTE : This function should not be modified, when the callback is needed,
00436             the HAL_OPAMP_MspInit could be implemented in the user file
00437    */
00438
00439    /* Example */
00440 }
00441
00442 /**
00443   * @brief  DeInitializes OPAMP MSP.
00444   * @param  hopamp OPAMP handle
00445   * @retval None
00446   */
00447 __weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
00448 {
00449   /* Prevent unused argument(s) compilation warning */
00450   UNUSED(hopamp);
00451
00452   /* NOTE : This function should not be modified, when the callback is needed,
00453             the HAL_OPAMP_MspDeInit could be implemented in the user file
00454    */
00455
00456 }
00457
00458 /**
00459   * @}
00460   */
00461
00462
00463 /** @defgroup OPAMP_Exported_Functions_Group2 Input and Output operation functions
00464  *  @brief   Data transfers functions
00465  *
00466 @verbatim
00467  ===============================================================================
00468                       ##### IO operation functions #####
00469  ===============================================================================
00470     [..]
00471     This subsection provides a set of functions allowing to manage the OPAMP data
00472     transfers.
00473
00474 @endverbatim
00475   * @{
00476   */
00477
00478 /**
00479   * @brief  Start the opamp
00480   * @param  hopamp OPAMP handle
00481   * @retval HAL status
00482   */
00483
00484 HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
00485 {
00486   HAL_StatusTypeDef status = HAL_OK;
00487
00488   /* Check the OPAMP handle allocation */
00489   /* Check if OPAMP locked */
00490   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
00491
00492   {
00493     status = HAL_ERROR;
00494   }
00495   else
00496   {
00497     /* Check the parameter */
00498     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00499
00500     if(hopamp->State == HAL_OPAMP_STATE_READY)
00501     {
00502       /* Enable the selected opamp */
00503       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00504
00505       /* Update the OPAMP state*/
00506       /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */
00507       hopamp->State = HAL_OPAMP_STATE_BUSY;
00508     }
00509     else
00510     {
00511       status = HAL_ERROR;
00512     }
00513
00514
00515    }
00516   return status;
00517 }
00518
00519 /**
00520   * @brief  Stop the opamp
00521   * @param  hopamp OPAMP handle
00522   * @retval HAL status
00523   */
00524 HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
00525 {
00526   HAL_StatusTypeDef status = HAL_OK;
00527
00528   /* Check the OPAMP handle allocation */
00529   /* Check if OPAMP locked */
00530   /* Check if OPAMP calibration ongoing */
00531   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \
00532                       || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
00533   {
00534     status = HAL_ERROR;
00535   }
00536   else
00537   {
00538     /* Check the parameter */
00539     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00540
00541     if(hopamp->State == HAL_OPAMP_STATE_BUSY)
00542     {
00543       /* Disable the selected opamp */
00544       CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00545
00546       /* Update the OPAMP state*/
00547       /* From  HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/
00548       hopamp->State = HAL_OPAMP_STATE_READY;
00549     }
00550     else
00551     {
00552       status = HAL_ERROR;
00553     }
00554   }
00555   return status;
00556 }
00557
00558 /**
00559   * @brief  Run the self calibration of one OPAMP
00560   * @param  hopamp handle
00561   * @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled
00562   * @retval HAL status
00563   * @note   Calibration runs about 25 ms.
00564   */
00565
00566 HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
00567 {
00568
00569   HAL_StatusTypeDef status = HAL_OK;
00570
00571   uint32_t trimmingvaluen = 0U;
00572   uint32_t trimmingvaluep = 0U;
00573   uint32_t delta;
00574
00575   /* Check the OPAMP handle allocation */
00576   /* Check if OPAMP locked */
00577   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
00578   {
00579     status = HAL_ERROR;
00580   }
00581   else
00582   {
00583
00584     /* Check if OPAMP in calibration mode and calibration not yet enable */
00585     if(hopamp->State ==  HAL_OPAMP_STATE_READY)
00586     {
00587       /* Check the parameter */
00588       assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00589
00590       /* Set Calibration mode */
00591       /* Non-inverting input connected to calibration reference voltage. */
00592       SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
00593
00594       /*  user trimming values are used for offset calibration */
00595       SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
00596
00597       /* Enable calibration */
00598       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
00599
00600       /* 1st calibration - N */
00601       /* Select 90U% VREF */
00602       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00603
00604       /* Enable the selected opamp */
00605       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00606
00607       /* Init trimming counter */
00608       /* Medium value */
00609       trimmingvaluen = 16U;
00610       delta = 8U;
00611
00612       while (delta != 0U)
00613       {
00614         /* Set candidate trimming */
00615         MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<<OPAMP_INPUT_INVERTING);
00616
00617         /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00618         /* Offset trim time: during calibration, minimum time needed between */
00619         /* two steps to have 1 mV accuracy */
00620         HAL_Delay(2U);
00621
00622         if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00623         {
00624           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00625           trimmingvaluen += delta;
00626         }
00627         else
00628         {
00629           /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
00630           trimmingvaluen -= delta;
00631         }
00632
00633         delta >>= 1U;
00634       }
00635
00636       /* Still need to check if righ calibration is current value or un step below */
00637       /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0  */
00638       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<<OPAMP_INPUT_INVERTING);
00639
00640        /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00641        /* Offset trim time: during calibration, minimum time needed between */
00642        /* two steps to have 1 mV accuracy */
00643        HAL_Delay(2U);
00644
00645       if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00646       {
00647         /* OPAMP_CSR_OUTCAL is actually one value more */
00648         trimmingvaluen++;
00649         /* Set right trimming */
00650         MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<<OPAMP_INPUT_INVERTING);
00651       }
00652
00653       /* 2nd calibration - P */
00654       /* Select 10U% VREF */
00655       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00656
00657       /* Init trimming counter */
00658       /* Medium value */
00659       trimmingvaluep = 16U;
00660       delta = 8U;
00661
00662       while (delta != 0U)
00663       {
00664         /* Set candidate trimming */
00665         MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<<OPAMP_INPUT_NONINVERTING);
00666
00667         /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00668         /* Offset trim time: during calibration, minimum time needed between */
00669         /* two steps to have 1 mV accuracy */
00670         HAL_Delay(2U);
00671
00672         if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00673         {
00674           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00675           trimmingvaluep += delta;
00676         }
00677         else
00678         {
00679           trimmingvaluep -= delta;
00680         }
00681
00682         delta >>= 1U;
00683       }
00684
00685       /* Still need to check if righ calibration is current value or un step below */
00686       /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */
00687       /* Set candidate trimming */
00688       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<<OPAMP_INPUT_NONINVERTING);
00689
00690        /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00691        /* Offset trim time: during calibration, minimum time needed between */
00692        /* two steps to have 1 mV accuracy */
00693        HAL_Delay(2U);
00694
00695       if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00696       {
00697         /* OPAMP_CSR_OUTCAL is actually one value more */
00698         trimmingvaluep++;
00699         /* Set right trimming */
00700         MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<<OPAMP_INPUT_NONINVERTING);
00701       }
00702
00703       /* Disable calibration */
00704       CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
00705
00706       /* Disable the OPAMP */
00707       CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00708
00709       /* Set operating mode  */
00710       /* Non-inverting input connected to calibration reference voltage. */
00711       CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
00712
00713       /* Self calibration is successful  */
00714       /* Store calibration(user timming) results in init structure. */
00715
00716       /* Write calibration result N */
00717       hopamp->Init.TrimmingValueN = trimmingvaluen;
00718
00719       /* Write calibration result P */
00720       hopamp->Init.TrimmingValueP = trimmingvaluep;
00721
00722       /* Select user timming mode */
00723       /* And updated with calibrated settings */
00724       hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER;
00725       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<<OPAMP_INPUT_NONINVERTING);
00726       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<<OPAMP_INPUT_INVERTING);
00727     }
00728
00729     else
00730     {
00731       /* OPAMP can not be calibrated from this mode */
00732       status = HAL_ERROR;
00733     }
00734   }
00735   return status;
00736 }
00737
00738 /**
00739   * @}
00740   */
00741
00742 /** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
00743  *  @brief   management functions
00744  *
00745 @verbatim
00746  ===============================================================================
00747                       ##### Peripheral Control functions #####
00748  ===============================================================================
00749     [..]
00750     This subsection provides a set of functions allowing to control the OPAMP data
00751     transfers.
00752
00753
00754
00755 @endverbatim
00756   * @{
00757   */
00758
00759 /**
00760   * @brief  Lock the selected opamp configuration.
00761   * @param  hopamp OPAMP handle
00762   * @retval HAL status
00763   */
00764 HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
00765 {
00766   HAL_StatusTypeDef status = HAL_OK;
00767
00768   /* Check the OPAMP handle allocation */
00769   /* Check if OPAMP locked */
00770   /* OPAMP can be locked when enabled and running in normal mode */
00771   /*   It is meaningless otherwise */
00772   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \
00773                       || (hopamp->State == HAL_OPAMP_STATE_READY) \
00774                       || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\
00775                       || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
00776
00777   {
00778     status = HAL_ERROR;
00779   }
00780
00781   else
00782   {
00783     /* Check the parameter */
00784     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00785
00786    /* Lock OPAMP */
00787     SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_LOCK);
00788
00789    /* OPAMP state changed to locked */
00790     hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED;
00791   }
00792   return status;
00793 }
00794
00795 /**
00796   * @}
00797   */
00798
00799 /** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
00800  *  @brief   Peripheral State functions
00801  *
00802 @verbatim
00803  ===============================================================================
00804                       ##### Peripheral State functions #####
00805  ===============================================================================
00806     [..]
00807     This subsection permit to get in run-time the status of the peripheral
00808     and the data flow.
00809
00810 @endverbatim
00811   * @{
00812   */
00813
00814 /**
00815   * @brief  Return the OPAMP state
00816   * @param  hopamp OPAMP handle
00817   * @retval HAL state
00818   */
00819 HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
00820 {
00821   /* Check the OPAMP handle allocation */
00822   if(hopamp == NULL)
00823   {
00824     return HAL_OPAMP_STATE_RESET;
00825   }
00826
00827   /* Check the parameter */
00828   assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00829
00830   return hopamp->State;
00831 }
00832
00833 /**
00834   * @brief  Return the OPAMP factory trimming value
00835   * @param  hopamp OPAMP handle
00836   * @param  trimmingoffset Trimming offset (P or N)
00837   * @retval Trimming value (P or N): range: 0->31
00838   *         or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
00839  */
00840
00841 OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
00842 {
00843   uint32_t oldusertrimming = 0U;
00844   OPAMP_TrimmingValueTypeDef  oldtrimmingvaluep = 0U, oldtrimmingvaluen = 0U, trimmingvalue = 0U;
00845
00846   /* Check the OPAMP handle allocation */
00847   /* Value can be retrieved in HAL_OPAMP_STATE_READY state */
00848   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \
00849                       || (hopamp->State == HAL_OPAMP_STATE_BUSY) \
00850                       || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\
00851                       || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
00852   {
00853     return OPAMP_FACTORYTRIMMING_DUMMY;
00854   }
00855   else
00856   {
00857     /* Check the parameter */
00858     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00859     assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset));
00860
00861     /* Check the trimming mode */
00862     if ((READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM)) != RESET)
00863     {
00864       /* User trimming is used */
00865       oldusertrimming = OPAMP_TRIMMING_USER;
00866       /* Store the TrimmingValueP & TrimmingValueN */
00867       oldtrimmingvaluep = (hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETP) >> OPAMP_INPUT_NONINVERTING;
00868       oldtrimmingvaluen = (hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETN) >> OPAMP_INPUT_INVERTING;
00869     }
00870
00871     /* Set factory timming mode */
00872     CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
00873
00874     /* Get factory trimming  */
00875     if (trimmingoffset == OPAMP_FACTORYTRIMMING_P)
00876     {
00877       /* Return TrimOffsetP */
00878      trimmingvalue = ((hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETP) >> OPAMP_INPUT_NONINVERTING);
00879     }
00880     else
00881     {
00882       /* Return TrimOffsetN */
00883       trimmingvalue = ((hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETN) >> OPAMP_INPUT_INVERTING);
00884     }
00885
00886     /* Restore user trimming configuration if it was formerly set */
00887     /* Check if user trimming was used */
00888     if (oldusertrimming == OPAMP_TRIMMING_USER)
00889     {
00890       /* Restore user trimming */
00891       SET_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM);
00892       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, oldtrimmingvaluep<<OPAMP_INPUT_NONINVERTING);
00893       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, oldtrimmingvaluen<<OPAMP_INPUT_INVERTING);
00894     }
00895   }
00896   return trimmingvalue;
00897 }
00898 /**
00899   * @}
00900   */
00901
00902 /**
00903   * @}
00904   */
00905
00906 /**
00907   * @}
00908   */
00909
00910 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00911        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00912        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00913        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00914
00915 #endif /* HAL_OPAMP_MODULE_ENABLED */
00916 /**
00917   * @}
00918   */
00919
00920
00921
00922 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_opamp.h Source File

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stm32f3xx_hal_opamp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_opamp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of OPAMP HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_OPAMP_H
00038 #define __STM32F3xx_HAL_OPAMP_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00045     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00046     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00047     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00048
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f3xx_hal_def.h"
00051
00052 /** @addtogroup STM32F3xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @addtogroup OPAMP
00057   * @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /** @defgroup OPAMP_Exported_Types OPAMP Exported Types
00062   * @{
00063   */
00064
00065 /**
00066   * @brief  OPAMP Init structure definition
00067   */
00068
00069 typedef struct
00070 {
00071   uint32_t Mode;                        /*!< Specifies the OPAMP mode
00072                                              This parameter must be a value of @ref OPAMP_Mode
00073                                              mode is either Standalone, - Follower or PGA */
00074
00075   uint32_t InvertingInput;              /*!< Specifies the inverting input in Standalone & Pga modes
00076                                                - In Standalone mode:   i.e when mode is OPAMP_STANDALONE_MODE
00077                                                  This parameter must be a value of @ref OPAMP_InvertingInput
00078                                                  InvertingInput is either VM0 or VM1
00079                                                - In PGA mode:          i.e when mode is OPAMP_PGA_MODE
00080                                                  & in Follower mode    i.e when mode is OPAMP_FOLLOWER_MODE
00081                                                  This parameter is Not Applicable */
00082
00083   uint32_t NonInvertingInput;           /*!< Specifies the non inverting input of the opamp:
00084                                              This parameter must be a value of @ref OPAMP_NonInvertingInput
00085                                              NonInvertingInput is either VP0, VP1, VP2 or VP3 */
00086
00087   uint32_t TimerControlledMuxmode;      /*!< Specifies if the Timer controlled Mux mode is enabled or disabled
00088                                              This parameter must be a value of @ref OPAMP_TimerControlledMuxmode */
00089
00090   uint32_t InvertingInputSecondary;     /*!< Specifies the inverting input (secondary) of the opamp when
00091                                              TimerControlledMuxmode is enabled
00092                                              i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
00093                                                - In Standalone mode:   i.e when mode is OPAMP_STANDALONE_MODE
00094                                                  This parameter must be a value of @ref OPAMP_InvertingInputSecondary
00095                                                  InvertingInputSecondary is either VM0 or VM1
00096                                                - In PGA mode:          i.e when mode is OPAMP_PGA_MODE
00097                                                  & in Follower mode    i.e when mode is OPAMP_FOLLOWER_MODE
00098                                                  This parameter is Not Applicable */
00099
00100   uint32_t NonInvertingInputSecondary;  /*!< Specifies the non inverting input (secondary) of the opamp when
00101                                              TimerControlledMuxmode is enabled
00102                                              i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
00103                                              This parameter must be a value of @ref OPAMP_NonInvertingInputSecondary
00104                                              NonInvertingInput is either VP0, VP1, VP2 or VP3 */
00105
00106   uint32_t PgaConnect;                  /*!< Specifies the inverting pin in PGA mode
00107                                              i.e. when mode is OPAMP_PGA_MODE
00108                                              This parameter must be a value of @ref OPAMP_PgaConnect
00109                                              Either: not connected, connected to VM0, connected to VM1
00110                                              (VM0 or VM1 are typically used for external filtering) */
00111
00112   uint32_t PgaGain;                     /*!< Specifies the gain in PGA mode
00113                                              i.e. when mode is OPAMP_PGA_MODE.
00114                                              This parameter must be a value of @ref OPAMP_PgaGain (2U, 4U, 8 or 16U ) */
00115
00116   uint32_t UserTrimming;                /*!< Specifies the trimming mode
00117                                              This parameter must be a value of @ref OPAMP_UserTrimming
00118                                              UserTrimming is either factory or user trimming */
00119
00120   uint32_t TrimmingValueP;              /*!< Specifies the offset trimming value (PMOS)
00121                                              i.e. when UserTrimming is OPAMP_TRIMMING_USER.
00122                                              This parameter must be a number between Min_Data = 1 and Max_Data = 31U */
00123
00124   uint32_t TrimmingValueN;              /*!< Specifies the offset trimming value (NMOS)
00125                                              i.e. when UserTrimming is OPAMP_TRIMMING_USER.
00126                                              This parameter must be a number between Min_Data = 1 and Max_Data = 31U */
00127
00128 }OPAMP_InitTypeDef;
00129
00130 /**
00131   * @brief  HAL State structures definition
00132   */
00133
00134 typedef enum
00135 {
00136   HAL_OPAMP_STATE_RESET               = 0x00000000U, /*!< OPMAP is not yet Initialized          */
00137
00138   HAL_OPAMP_STATE_READY               = 0x00000001U, /*!< OPAMP is initialized and ready for use */
00139   HAL_OPAMP_STATE_CALIBBUSY           = 0x00000002U, /*!< OPAMP is enabled in auto calibration mode */
00140
00141   HAL_OPAMP_STATE_BUSY                = 0x00000004U, /*!< OPAMP is enabled and running in normal mode */
00142   HAL_OPAMP_STATE_BUSYLOCKED          = 0x00000005U, /*!< OPAMP is locked
00143                                                          only system reset allows reconfiguring the opamp. */
00144
00145 }HAL_OPAMP_StateTypeDef;
00146
00147 /**
00148   * @brief OPAMP Handle Structure definition to @brief  OPAMP Handle Structure definition
00149   */
00150 typedef struct
00151 {
00152   OPAMP_TypeDef       *Instance;                    /*!< OPAMP instance's registers base address   */
00153   OPAMP_InitTypeDef   Init;                         /*!< OPAMP required parameters */
00154   HAL_StatusTypeDef Status;                         /*!< OPAMP peripheral status   */
00155   HAL_LockTypeDef   Lock;                           /*!< Locking object          */
00156   __IO HAL_OPAMP_StateTypeDef  State;               /*!< OPAMP communication state */
00157
00158 } OPAMP_HandleTypeDef;
00159
00160 /**
00161   * @brief OPAMP_TrimmingValueTypeDef @brief   definition
00162   */
00163
00164 typedef  uint32_t OPAMP_TrimmingValueTypeDef;
00165 /**
00166   * @}
00167   */
00168
00169 /* Exported constants --------------------------------------------------------*/
00170 /** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
00171   * @{
00172   */
00173
00174 /** @defgroup OPAMP_CSR_INIT OPAMP CSR init register Mask
00175   * @{
00176   */
00177 /* Used for Init phase */
00178 #define OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP \
00179                                           | OPAMP_CSR_USERTRIM | OPAMP_CSR_PGGAIN | OPAMP_CSR_VPSSEL \
00180                                           | OPAMP_CSR_VMSSEL | OPAMP_CSR_TCMEN | OPAMP_CSR_VPSEL \
00181                                           | OPAMP_CSR_VMSEL | OPAMP_CSR_FORCEVP)
00182
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup OPAMP_Mode OPAMP Mode
00188   * @{
00189   */
00190 #define OPAMP_STANDALONE_MODE            (0x00000000U) /*!< standalone mode */
00191 #define OPAMP_PGA_MODE                   OPAMP_CSR_VMSEL_1      /*!< PGA mode */
00192 #define OPAMP_FOLLOWER_MODE              OPAMP_CSR_VMSEL        /*!< follower mode */
00193
00194
00195 #define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
00196                                                ((INPUT) == OPAMP_PGA_MODE) || \
00197                                                ((INPUT) == OPAMP_FOLLOWER_MODE))
00198
00199 /**
00200   * @}
00201   */
00202
00203 /** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input
00204   * @{
00205   */
00206
00207 #define OPAMP_NONINVERTINGINPUT_IO0         OPAMP_CSR_VPSEL         /*!< VP0 (PA1 for OPAMP1, VP0 PA7  for OPAMP2, VP0 PB0  for OPAMP3, VP0 PB13 for OPAMP4)
00208                                                                                   connected to OPAMPx non inverting input */
00209 #define OPAMP_NONINVERTINGINPUT_IO1         (0x00000000U)  /*!< VP1 (PA7 for OPAMP1, VP3 PD14 for OPAMP2, VP1 PB13 for OPAMP3, VP1 PD11 for OPAMP4)
00210                                                                                   connected to OPAMPx non inverting input */
00211 #define OPAMP_NONINVERTINGINPUT_IO2         OPAMP_CSR_VPSEL_1       /*!< VP2 (PA3 for OPAMP1, VP2 PB0  for OPAMP2, VP2 PA1  for OPAMP3, VP3 PA4  for OPAMP4)
00212                                                                                   connected to OPAMPx non inverting input */
00213 #define OPAMP_NONINVERTINGINPUT_IO3         OPAMP_CSR_VPSEL_0       /*!< VP3 (PA5 for OPAMP1, VP1 PB14 for OPAMP2, VP3 PA5  for OPAMP3, VP2 PB11 for OPAMP4)
00214                                                                                   connected to OPAMPx non inverting input */
00215
00216 #define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
00217                                             ((INPUT) == OPAMP_NONINVERTINGINPUT_IO1) || \
00218                                             ((INPUT) == OPAMP_NONINVERTINGINPUT_IO2) || \
00219                                             ((INPUT) == OPAMP_NONINVERTINGINPUT_IO3))
00220
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup OPAMP_InvertingInput OPAMP Inverting Input
00226   * @{
00227   */
00228
00229 #define OPAMP_INVERTINGINPUT_IO0       (0x00000000U)            /*!< inverting input connected to VM0 */
00230 #define OPAMP_INVERTINGINPUT_IO1         OPAMP_CSR_VMSEL_0           /*!< inverting input connected to VM1 */
00231
00232 #define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
00233                                          ((INPUT) == OPAMP_INVERTINGINPUT_IO1))
00234
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup OPAMP_TimerControlledMuxmode OPAMP Timer Controlled Mux mode
00240   * @{
00241   */
00242  #define OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE (0x00000000U)    /*!< Timer controlled Mux mode disabled */
00243  #define OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE  OPAMP_CSR_TCMEN           /*!< Timer controlled Mux mode enabled */
00244
00245  #define IS_OPAMP_TIMERCONTROLLED_MUXMODE(MUXMODE) (((MUXMODE) == OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE) || \
00246                                                     ((MUXMODE) == OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE))
00247 /**
00248   * @}
00249   */
00250
00251  /** @defgroup OPAMP_NonInvertingInputSecondary OPAMP Non Inverting Input Secondary
00252   * @{
00253   */
00254
00255 #define OPAMP_SEC_NONINVERTINGINPUT_IO0          OPAMP_CSR_VPSSEL       /*!< VP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
00256                                                                               connected to OPAMPx non inverting input */
00257 #define OPAMP_SEC_NONINVERTINGINPUT_IO1          (0x00000000U) /*!< VP1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
00258                                                                              connected to OPAMPx non inverting input */
00259 #define OPAMP_SEC_NONINVERTINGINPUT_IO2          OPAMP_CSR_VPSSEL_1     /*!< VP2 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
00260                                                                               connected to OPAMPx non inverting input */
00261 #define OPAMP_SEC_NONINVERTINGINPUT_IO3          OPAMP_CSR_VPSSEL_0     /*!< VP3 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
00262                                                                               connected to OPAMPx non inverting input */
00263
00264 #define IS_OPAMP_SEC_NONINVERTINGINPUT(INPUT) (((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO0) || \
00265                                                ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO1) || \
00266                                                ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO2) || \
00267                                                ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO3))
00268
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup OPAMP_InvertingInputSecondary OPAMP Inverting Input Secondary
00274   * @{
00275   */
00276
00277 #define OPAMP_SEC_INVERTINGINPUT_IO0          (0x00000000U)    /*!< VM0 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
00278                                                                           connected to OPAMPx inverting input */
00279 #define OPAMP_SEC_INVERTINGINPUT_IO1          OPAMP_CSR_VMSSEL         /*!< VM1 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4)
00280                                                                          connected to OPAMPx inverting input */
00281
00282 #define IS_OPAMP_SEC_INVERTINGINPUT(INPUT) (((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO0) || \
00283                                              ((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO1))
00284
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup OPAMP_PgaConnect OPAMP Pga Connect
00290   * @{
00291   */
00292
00293 #define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO               (0x00000000U)                    /*!< In PGA mode, the non inverting input is not connected */
00294 #define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0               OPAMP_CSR_PGGAIN_3                       /*!< In PGA mode, the non inverting input is connected to VM0 */
00295 #define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1              (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3) /*!< In PGA mode, the non inverting input is connected to VM1 */
00296
00297 #define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO)  || \
00298                                       ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0) || \
00299                                       ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1))
00300 /**
00301   * @}
00302   */
00303
00304
00305 /** @defgroup OPAMP_PgaGain OPAMP Pga Gain
00306   * @{
00307   */
00308
00309 #define OPAMP_PGA_GAIN_2                (0x00000000U)                        /*!< PGA gain =  2 */
00310 #define OPAMP_PGA_GAIN_4                OPAMP_CSR_PGGAIN_0                            /*!< PGA gain =  4 */
00311 #define OPAMP_PGA_GAIN_8                OPAMP_CSR_PGGAIN_1                            /*!< PGA gain =  8 */
00312 #define OPAMP_PGA_GAIN_16              (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)      /*!< PGA gain = 16 */
00313
00314 #define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \
00315                                  ((GAIN) == OPAMP_PGA_GAIN_4) || \
00316                                  ((GAIN) == OPAMP_PGA_GAIN_8) || \
00317                                  ((GAIN) == OPAMP_PGA_GAIN_16))
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup OPAMP_UserTrimming OPAMP User Trimming
00323   * @{
00324   */
00325
00326 #define OPAMP_TRIMMING_FACTORY        (0x00000000U)                          /*!< Factory trimming */
00327 #define OPAMP_TRIMMING_USER           OPAMP_CSR_USERTRIM                              /*!< User trimming */
00328
00329 #define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
00330                                      ((TRIMMING) == OPAMP_TRIMMING_USER))
00331
00332 /** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming
00333   * @{
00334   */
00335
00336 #define OPAMP_FACTORYTRIMMING_DUMMY    (0xFFFFFFFFU)                          /*!< Dummy trimming value */
00337
00338 #define OPAMP_FACTORYTRIMMING_N        (0x00000000U)                          /*!< Offset trimming N */
00339 #define OPAMP_FACTORYTRIMMING_P        (0x00000001U)                          /*!< Offset trimming P */
00340
00341 #define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
00342                                              ((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
00343
00344 /**
00345   * @}
00346   */
00347
00348
00349 /** @defgroup OPAMP_TrimmingValue OPAMP Trimming Value
00350   * @{
00351   */
00352
00353 #define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
00354
00355
00356 /**
00357   * @}
00358   */
00359
00360
00361 /** @defgroup OPAMP_Input OPAMP Input
00362   * @{
00363   */
00364
00365 #define OPAMP_INPUT_INVERTING                 ( 24U) /*!< Inverting input */
00366 #define OPAMP_INPUT_NONINVERTING              ( 19U) /*!< Non inverting input */
00367
00368 #define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_INPUT_INVERTING) || \
00369                                ((INPUT) == OPAMP_INPUT_NONINVERTING))
00370 /**
00371   * @}
00372   */
00373
00374
00375 /** @defgroup OPAMP_VREF OPAMP VREF
00376   * @{
00377   */
00378
00379 #define OPAMP_VREF_3VDDA                    (0x00000000U)  /*!< OPMAP Vref = 3.3U% VDDA */
00380 #define OPAMP_VREF_10VDDA                    OPAMP_CSR_CALSEL_0     /*!< OPMAP Vref = 10U% VDDA  */
00381 #define OPAMP_VREF_50VDDA                    OPAMP_CSR_CALSEL_1     /*!< OPMAP Vref = 50U% VDDA  */
00382 #define OPAMP_VREF_90VDDA                    OPAMP_CSR_CALSEL       /*!< OPMAP Vref = 90U% VDDA  */
00383
00384 #define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_VREF_3VDDA)  || \
00385                              ((VREF) == OPAMP_VREF_10VDDA) || \
00386                              ((VREF) == OPAMP_VREF_50VDDA) || \
00387                              ((VREF) == OPAMP_VREF_90VDDA))
00388
00389 /**
00390   * @}
00391   */
00392
00393  /** @defgroup OPAMP_Vref2ADCforCalib OPAMP Vref2ADCforCalib
00394   */
00395
00396 #define OPAMP_VREF_NOTCONNECTEDTO_ADC          (0x00000000U) /*!< VREF not connected to ADC */
00397 #define OPAMP_VREF_CONNECTEDTO_ADC             (0x00000001U) /*!< VREF not connected to ADC */
00398
00399 #define IS_OPAMP_ALLOPAMPVREF_CONNECT(CONNECT) (((CONNECT) == OPAMP_VREF_NOTCONNECTEDTO_ADC) || \
00400                                                 ((CONNECT) == OPAMP_VREF_CONNECTEDTO_ADC))
00401
00402
00403  /**
00404   * @}
00405   */
00406
00407  /**
00408   * @}
00409   */
00410
00411 /* Exported macros -----------------------------------------------------------*/
00412 /** @defgroup OPAMP_Exported_Macros OPAMP Exported Macros
00413   * @{
00414   */
00415
00416 /** @brief Reset OPAMP handle state
00417   * @param  __HANDLE__ OPAMP handle.
00418   * @retval None
00419   */
00420 #define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
00421
00422 /**
00423   * @}
00424   */
00425
00426 /* Include OPAMP HAL Extended module */
00427 #include "stm32f3xx_hal_opamp_ex.h"
00428
00429 /* Exported functions --------------------------------------------------------*/
00430 /** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
00431   * @{
00432   */
00433
00434 /** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
00435   * @{
00436   */
00437
00438 /* Initialization/de-initialization functions  **********************************/
00439 HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
00440 HAL_StatusTypeDef HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp);
00441 void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
00442 void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
00443 /**
00444   * @}
00445   */
00446
00447
00448 /** @defgroup OPAMP_Exported_Functions_Group2 Input and Output operation functions
00449   * @{
00450   */
00451
00452 /* I/O operation functions  *****************************************************/
00453 HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
00454 HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
00455 HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
00456
00457 /**
00458   * @}
00459   */
00460
00461 /** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
00462   * @{
00463   */
00464
00465 /* Peripheral Control functions  ************************************************/
00466 HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
00467
00468 /**
00469   * @}
00470   */
00471
00472 /** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
00473   * @{
00474   */
00475
00476 /* Peripheral State functions  **************************************************/
00477 HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
00478 OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
00479
00480 /**
00481   * @}
00482   */
00483
00484 /**
00485   * @}
00486   */
00487
00488 /**
00489   * @}
00490   */
00491
00492 /**
00493   * @}
00494   */
00495
00496 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00497        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00498        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00499        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00500
00501 #ifdef __cplusplus
00502 }
00503 #endif
00504
00505 #endif /* __STM32F3xx_HAL_OPAMP_H */
00506
00507 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_opamp_ex.c Source File

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stm32f3xx_hal_opamp_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_opamp_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended OPAMP HAL module driver.
00006   *
00007   *          This file provides firmware functions to manage the following
00008   *          functionalities of the Power Controller (OPAMP) peripheral:
00009   *           + Extended Initialization and de-initialization  functions
00010   *           + Extended Peripheral Control  functions
00011   *
00012   @verbatim
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00017   *
00018   * Redistribution and use in source and binary forms, with or without modification,
00019   * are permitted provided that the following conditions are met:
00020   *   1. Redistributions of source code must retain the above copyright notice,
00021   *      this list of conditions and the following disclaimer.
00022   *   2. Redistributions in binary form must reproduce the above copyright notice,
00023   *      this list of conditions and the following disclaimer in the documentation
00024   *      and/or other materials provided with the distribution.
00025   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00026   *      may be used to endorse or promote products derived from this software
00027   *      without specific prior written permission.
00028   *
00029   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00030   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00031   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00032   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00033   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00034   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00035   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00036   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00037   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00038   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00039   *
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32f3xx_hal.h"
00045
00046 /** @addtogroup STM32F3xx_HAL_Driver
00047   * @{
00048   */
00049
00050 #ifdef HAL_OPAMP_MODULE_ENABLED
00051
00052 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00053     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00054     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00055     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00056
00057 /** @defgroup OPAMPEx OPAMPEx
00058   * @brief OPAMP Extended HAL module driver.
00059   * @{
00060   */
00061
00062
00063 /* Private typedef -----------------------------------------------------------*/
00064 /* Private define ------------------------------------------------------------*/
00065 /* Private macro -------------------------------------------------------------*/
00066 /* Private variables ---------------------------------------------------------*/
00067 /* Private function prototypes -----------------------------------------------*/
00068 /* Exported functions ---------------------------------------------------------*/
00069
00070 /** @defgroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
00071   * @{
00072   */
00073
00074
00075 /** @defgroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
00076   * @brief    Extended Self calibration functions
00077   *
00078 @verbatim
00079  ===============================================================================
00080               ##### Extended IO operation functions #####
00081  ===============================================================================
00082   [..]
00083
00084 @endverbatim
00085   * @{
00086   */
00087
00088 #if defined(STM32F302xE) || \
00089     defined(STM32F302xC)
00090 /*  2 OPAMPS available */
00091 /*  2 OPAMPS can be calibrated in parallel */
00092
00093 /**
00094   * @brief  Run the self calibration of 2 OPAMPs in parallel.
00095   * @param  hopamp1 handle
00096   * @param  hopamp2 handle
00097   * @retval HAL status
00098   * @note   Updated offset trimming values (PMOS & NMOS), user trimming is enabled
00099   * @note   Calibration runs about 25 ms.
00100   */
00101
00102 HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
00103 {
00104   HAL_StatusTypeDef status = HAL_OK;
00105
00106   uint32_t trimmingvaluen1 = 0U;
00107   uint32_t trimmingvaluep1 = 0U;
00108   uint32_t trimmingvaluen2 = 0U;
00109   uint32_t trimmingvaluep2 = 0U;
00110
00111   uint32_t delta;
00112
00113   if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
00114      (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED))
00115   {
00116     status = HAL_ERROR;
00117   }
00118
00119   if(status == HAL_OK)
00120   {
00121     /* Check if OPAMP in calibration mode and calibration not yet enable */
00122     if((hopamp1->State ==  HAL_OPAMP_STATE_READY) && (hopamp2->State ==  HAL_OPAMP_STATE_READY))
00123     {
00124       /* Check the parameter */
00125       assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
00126       assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
00127
00128       /* Set Calibration mode */
00129       /* Non-inverting input connected to calibration reference voltage. */
00130       SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
00131       SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
00132
00133       /*  user trimming values are used for offset calibration */
00134       SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
00135       SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
00136
00137       /* Enable calibration */
00138       SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
00139       SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
00140
00141       /* 1st calibration - N */
00142       /* Select 90U% VREF */
00143       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00144       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00145
00146       /* Enable the opamps */
00147       SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00148       SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00149
00150       /* Init trimming counter */
00151       /* Medium value */
00152       trimmingvaluen1 = 16U;
00153       trimmingvaluen2 = 16U;
00154       delta = 8U;
00155
00156       while (delta != 0U)
00157       {
00158         /* Set candidate trimming */
00159         MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
00160         MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
00161
00162         /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00163         /* Offset trim time: during calibration, minimum time needed between */
00164         /* two steps to have 1 mV accuracy */
00165         HAL_Delay(2U);
00166
00167         if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)
00168         {
00169           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00170           trimmingvaluen1 += delta;
00171         }
00172         else
00173         {
00174           /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
00175           trimmingvaluen1 -= delta;
00176         }
00177
00178         if (hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL)
00179         {
00180           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00181           trimmingvaluen2 += delta;
00182         }
00183         else
00184         {
00185           /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
00186           trimmingvaluen2 -= delta;
00187         }
00188
00189         delta >>= 1U;
00190       }
00191
00192       // Still need to check if righ calibration is current value or un step below
00193       // Indeed the first value that causes the OUTCAL bit to change from 1 to 0
00194       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
00195       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
00196
00197       /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00198       /* Offset trim time: during calibration, minimum time needed between */
00199       /* two steps to have 1 mV accuracy */
00200       HAL_Delay(2U);
00201
00202       if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)
00203         {
00204           /* OPAMP_CSR_OUTCAL is actually one value more */
00205           trimmingvaluen1++;
00206           /* Set right trimming */
00207           MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
00208         }
00209
00210       if (hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL)
00211         {
00212           /* OPAMP_CSR_OUTCAL is actually one value more */
00213           trimmingvaluen2++;
00214           /* Set right trimming */
00215           MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
00216         }
00217
00218       /* 2nd calibration - P */
00219       /* Select 10U% VREF */
00220       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00221       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00222
00223       /* Init trimming counter */
00224       /* Medium value */
00225       trimmingvaluep1 = 16U;
00226       trimmingvaluep2 = 16U;
00227       delta = 8U;
00228
00229       while (delta != 0U)
00230       {
00231         /* Set candidate trimming */
00232         MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
00233         MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
00234
00235         /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00236         /* Offset trim time: during calibration, minimum time needed between */
00237         /* two steps to have 1 mV accuracy */
00238         HAL_Delay(2U);
00239
00240         if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)
00241         {
00242           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00243           trimmingvaluep1 += delta;
00244         }
00245         else
00246         {
00247           trimmingvaluep1 -= delta;
00248         }
00249
00250         if (hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL)
00251         {
00252           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00253           trimmingvaluep2 += delta;
00254         }
00255         else
00256         {
00257           trimmingvaluep2 -= delta;
00258         }
00259
00260         delta >>= 1U;
00261       }
00262
00263       // Still need to check if righ calibration is current value or un step below
00264       // Indeed the first value that causes the OUTCAL bit to change from 1 to 0
00265       /* Set candidate trimming */
00266       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
00267       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
00268
00269        /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00270        /* Offset trim time: during calibration, minimum time needed between */
00271        /* two steps to have 1 mV accuracy */
00272        HAL_Delay(2U);
00273
00274       if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)
00275         {
00276           /* OPAMP_CSR_OUTCAL is actually one value more */
00277           trimmingvaluep1++;
00278           /* Set right trimming */
00279           MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
00280         }
00281
00282       if (hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL)
00283         {
00284           /* OPAMP_CSR_OUTCAL is actually one value more */
00285           trimmingvaluep2++;
00286           /* Set right trimming */
00287           MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
00288         }
00289
00290       /* Disable calibration */
00291       CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
00292       CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
00293
00294       /* Disable the OPAMPs */
00295       CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00296       CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00297
00298       /* Set operating mode back */
00299       CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
00300       CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
00301
00302       /* Self calibration is successful  */
00303       /* Store calibration(user timming) results in init structure. */
00304       /* Select user timming mode */
00305
00306       /* Write calibration result N */
00307       hopamp1->Init.TrimmingValueN = trimmingvaluen1;
00308       hopamp2->Init.TrimmingValueN = trimmingvaluen2;
00309
00310       /* Write calibration result P */
00311       hopamp1->Init.TrimmingValueP = trimmingvaluep1;
00312       hopamp2->Init.TrimmingValueP = trimmingvaluep2;
00313
00314       /* Calibration */
00315       hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
00316       hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
00317
00318       /* Select user timming mode */
00319       /* And updated with calibrated settings */
00320       hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
00321       hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
00322
00323       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
00324       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
00325
00326       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
00327       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
00328
00329     }
00330
00331     else
00332     {
00333       /* At least one OPAMP can not be calibrated */
00334       status = HAL_ERROR;
00335     }
00336   }
00337
00338   return status;
00339 }
00340 #endif /* STM32F302xE || */
00341        /* STM32F302xC    */
00342
00343 #if defined(STM32F303xE) || defined(STM32F398xx) || \
00344     defined(STM32F303xC) || defined(STM32F358xx)
00345 /*  4 OPAMPS available */
00346 /*  4 OPAMPS can be calibrated in parallel */
00347
00348 /**
00349   * @brief  Run the self calibration of 4 OPAMPs in parallel.
00350   * @param  hopamp1 handle
00351   * @param  hopamp2 handle
00352   * @param  hopamp3 handle
00353   * @param  hopamp4 handle
00354   * @retval HAL status
00355   * @note   Updated offset trimming values (PMOS & NMOS), user trimming is enabled
00356   * @note   Calibration runs about 25 ms.
00357   */
00358
00359 HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4)
00360 {
00361   HAL_StatusTypeDef status = HAL_OK;
00362
00363   uint32_t trimmingvaluen1 = 0U;
00364   uint32_t trimmingvaluep1 = 0U;
00365   uint32_t trimmingvaluen2 = 0U;
00366   uint32_t trimmingvaluep2 = 0U;
00367   uint32_t trimmingvaluen3 = 0U;
00368   uint32_t trimmingvaluep3 = 0U;
00369   uint32_t trimmingvaluen4 = 0U;
00370   uint32_t trimmingvaluep4 = 0U;
00371
00372   uint32_t delta;
00373
00374   if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
00375      (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
00376      (hopamp3 == NULL) || (hopamp3->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
00377      (hopamp4 == NULL) || (hopamp4->State == HAL_OPAMP_STATE_BUSYLOCKED))
00378   {
00379     status = HAL_ERROR;
00380   }
00381
00382   if(status == HAL_OK)
00383   {
00384     /* Check if OPAMP in calibration mode and calibration not yet enable */
00385     if((hopamp1->State ==  HAL_OPAMP_STATE_READY) && (hopamp2->State ==  HAL_OPAMP_STATE_READY) && \
00386        (hopamp3->State ==  HAL_OPAMP_STATE_READY) && (hopamp4->State ==  HAL_OPAMP_STATE_READY))
00387     {
00388       /* Check the parameter */
00389       assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
00390       assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
00391       assert_param(IS_OPAMP_ALL_INSTANCE(hopamp3->Instance));
00392       assert_param(IS_OPAMP_ALL_INSTANCE(hopamp4->Instance));
00393
00394       /* Set Calibration mode */
00395       /* Non-inverting input connected to calibration reference voltage. */
00396       SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
00397       SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
00398       SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_FORCEVP);
00399       SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_FORCEVP);
00400
00401       /*  user trimming values are used for offset calibration */
00402       SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
00403       SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
00404       SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_USERTRIM);
00405       SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_USERTRIM);
00406
00407       /* Enable calibration */
00408       SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
00409       SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
00410       SET_BIT (hopamp3->Instance->CSR, OPAMP_CSR_CALON);
00411       SET_BIT (hopamp4->Instance->CSR, OPAMP_CSR_CALON);
00412
00413       /* 1st calibration - N */
00414       /* Select 90U% VREF */
00415       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00416       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00417       MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00418       MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00419
00420       /* Enable the opamps */
00421       SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00422       SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00423       SET_BIT (hopamp3->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00424       SET_BIT (hopamp4->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00425
00426       /* Init trimming counter */
00427       /* Medium value */
00428       trimmingvaluen1 = 16U;
00429       trimmingvaluen2 = 16U;
00430       trimmingvaluen3 = 16U;
00431       trimmingvaluen4 = 16U;
00432       delta = 8U;
00433
00434       while (delta != 0U)
00435       {
00436         /* Set candidate trimming */
00437         MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
00438         MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
00439         MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<<OPAMP_INPUT_INVERTING);
00440         MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4<<OPAMP_INPUT_INVERTING);
00441
00442         /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00443         /* Offset trim time: during calibration, minimum time needed between */
00444         /* two steps to have 1 mV accuracy */
00445         HAL_Delay(2U);
00446
00447         if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00448         {
00449           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00450           trimmingvaluen1 += delta;
00451         }
00452         else
00453         {
00454           /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
00455           trimmingvaluen1 -= delta;
00456         }
00457
00458         if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00459         {
00460           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00461           trimmingvaluen2 += delta;
00462         }
00463         else
00464         {
00465           /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
00466           trimmingvaluen2 -= delta;
00467         }
00468
00469         if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00470         {
00471           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00472           trimmingvaluen3 += delta;
00473         }
00474         else
00475         {
00476           /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
00477           trimmingvaluen3 -= delta;
00478         }
00479
00480         if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00481         {
00482           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00483           trimmingvaluen4 += delta;
00484         }
00485         else
00486         {
00487           /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
00488           trimmingvaluen4 -= delta;
00489         }
00490
00491         delta >>= 1U;
00492       }
00493
00494       /* Still need to check if righ calibration is current value or un step below */
00495       /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */
00496       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
00497       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
00498       MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<<OPAMP_INPUT_INVERTING);
00499       MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4<<OPAMP_INPUT_INVERTING);
00500
00501       /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00502       /* Offset trim time: during calibration, minimum time needed between */
00503       /* two steps to have 1 mV accuracy */
00504       HAL_Delay(2U);
00505
00506       if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00507       {
00508         /* OPAMP_CSR_OUTCAL is actually one value more */
00509         trimmingvaluen1++;
00510         /* Set right trimming */
00511         MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
00512       }
00513
00514       if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00515       {
00516         /* OPAMP_CSR_OUTCAL is actually one value more */
00517         trimmingvaluen2++;
00518         /* Set right trimming */
00519         MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
00520       }
00521
00522       if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00523       {
00524         /* OPAMP_CSR_OUTCAL is actually one value more */
00525         trimmingvaluen3++;
00526         /* Set right trimming */
00527         MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<<OPAMP_INPUT_INVERTING);
00528       }
00529
00530       if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00531       {
00532         /* OPAMP_CSR_OUTCAL is actually one value more */
00533         trimmingvaluen4++;
00534         /* Set right trimming */
00535         MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4<<OPAMP_INPUT_INVERTING);
00536       }
00537
00538       /* 2nd calibration - P */
00539       /* Select 10U% VREF */
00540       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00541       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00542       MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00543       MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00544
00545       /* Init trimming counter */
00546       /* Medium value */
00547       trimmingvaluep1 = 16U;
00548       trimmingvaluep2 = 16U;
00549       trimmingvaluep3 = 16U;
00550       trimmingvaluep4 = 16U;
00551
00552       delta = 8U;
00553
00554       while (delta != 0U)
00555       {
00556         /* Set candidate trimming */
00557         MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
00558         MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
00559         MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3<<OPAMP_INPUT_NONINVERTING);
00560         MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4<<OPAMP_INPUT_NONINVERTING);
00561
00562         /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00563         /* Offset trim time: during calibration, minimum time needed between */
00564         /* two steps to have 1 mV accuracy */
00565         HAL_Delay(2U);
00566
00567         if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00568         {
00569           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00570           trimmingvaluep1 += delta;
00571         }
00572         else
00573         {
00574           trimmingvaluep1 -= delta;
00575         }
00576
00577         if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00578         {
00579           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00580           trimmingvaluep2 += delta;
00581         }
00582         else
00583         {
00584           trimmingvaluep2 -= delta;
00585         }
00586
00587         if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00588         {
00589           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00590           trimmingvaluep3 += delta;
00591         }
00592         else
00593         {
00594           trimmingvaluep3 -= delta;
00595         }
00596
00597         if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00598         {
00599           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00600           trimmingvaluep4 += delta;
00601         }
00602         else
00603         {
00604           trimmingvaluep4 -= delta;
00605         }
00606
00607         delta >>= 1U;
00608       }
00609
00610       /* Still need to check if righ calibration is current value or un step below */
00611       /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */
00612       /* Set candidate trimming */
00613       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
00614       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
00615       MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3<<OPAMP_INPUT_NONINVERTING);
00616       MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4<<OPAMP_INPUT_NONINVERTING);
00617
00618       /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00619       /* Offset trim time: during calibration, minimum time needed between */
00620       /* two steps to have 1 mV accuracy */
00621       HAL_Delay(2U);
00622
00623       if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00624       {
00625         /* Trimming value is actually one value more */
00626         trimmingvaluep1++;
00627         /* Set right trimming */
00628         MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
00629       }
00630
00631       if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00632       {
00633         /* Trimming value is actually one value more */
00634         trimmingvaluep2++;
00635         /* Set right trimming */
00636         MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
00637       }
00638
00639       if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00640       {
00641         /* Trimming value is actually one value more */
00642         trimmingvaluep3++;
00643         /* Set right trimming */
00644         MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3<<OPAMP_INPUT_NONINVERTING);
00645       }
00646
00647       if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
00648       {
00649         /* Trimming value is actually one value more */
00650         trimmingvaluep4++;
00651         /* Set right trimming */
00652         MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4<<OPAMP_INPUT_NONINVERTING);
00653       }
00654
00655       /* Disable calibration */
00656       CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
00657       CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
00658       CLEAR_BIT (hopamp3->Instance->CSR, OPAMP_CSR_CALON);
00659       CLEAR_BIT (hopamp4->Instance->CSR, OPAMP_CSR_CALON);
00660
00661       /* Disable the OPAMPs */
00662       CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00663       CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00664       CLEAR_BIT (hopamp3->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00665       CLEAR_BIT (hopamp4->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00666
00667       /* Set normal operating mode back */
00668       CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
00669       CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
00670       CLEAR_BIT(hopamp3->Instance->CSR, OPAMP_CSR_FORCEVP);
00671       CLEAR_BIT(hopamp4->Instance->CSR, OPAMP_CSR_FORCEVP);
00672
00673       /* Self calibration is successful  */
00674       /* Store calibration(user timming) results in init structure. */
00675       /* Select user timming mode */
00676
00677       /* Write calibration result N */
00678       hopamp1->Init.TrimmingValueN = trimmingvaluen1;
00679       hopamp2->Init.TrimmingValueN = trimmingvaluen2;
00680       hopamp3->Init.TrimmingValueN = trimmingvaluen3;
00681       hopamp4->Init.TrimmingValueN = trimmingvaluen4;
00682
00683       /* Write calibration result P */
00684       hopamp1->Init.TrimmingValueP = trimmingvaluep1;
00685       hopamp2->Init.TrimmingValueP = trimmingvaluep2;
00686       hopamp3->Init.TrimmingValueP = trimmingvaluep3;
00687       hopamp4->Init.TrimmingValueP = trimmingvaluep4;
00688
00689       /* Select user timming mode */
00690       /* And updated with calibrated settings */
00691       hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
00692       hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
00693       hopamp3->Init.UserTrimming = OPAMP_TRIMMING_USER;
00694       hopamp4->Init.UserTrimming = OPAMP_TRIMMING_USER;
00695
00696       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
00697       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
00698       MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<<OPAMP_INPUT_INVERTING);
00699       MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4<<OPAMP_INPUT_INVERTING);
00700
00701       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
00702       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
00703       MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3<<OPAMP_INPUT_NONINVERTING);
00704       MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4<<OPAMP_INPUT_NONINVERTING);
00705
00706     }
00707
00708     else
00709     {
00710       /* At least one OPAMP can not be calibrated */
00711       status = HAL_ERROR;
00712     }
00713   }
00714
00715   return status;
00716 }
00717 #endif /* STM32F303xE || STM32F398xx  || */
00718        /* STM32F303xC || STM32F358xx     */
00719
00720 /**
00721   * @}
00722   */
00723
00724 /**
00725   * @}
00726   */
00727
00728 /**
00729   * @}
00730   */
00731
00732 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00733        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00734        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00735        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00736
00737 #endif /* HAL_OPAMP_MODULE_ENABLED */
00738
00739 /**
00740   * @}
00741   */
00742
00743 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32F373xC HAL User Manual: stm32f3xx_hal_opamp_ex.h Source File

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stm32f3xx_hal_opamp_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_opamp_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of OPAMP HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_OPAMP_EX_H
00038 #define __STM32F3xx_HAL_OPAMP_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00045     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00046     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00047     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00048
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f3xx_hal_def.h"
00051
00052 /** @addtogroup STM32F3xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @addtogroup OPAMPEx OPAMPEx
00057   * @{
00058   */
00059 /* Exported types ------------------------------------------------------------*/
00060 /* Exported constants --------------------------------------------------------*/
00061 /* Exported macro ------------------------------------------------------------*/
00062 /* Exported functions --------------------------------------------------------*/
00063 /** @addtogroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
00064   * @{
00065   */
00066
00067 /** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
00068   * @{
00069   */
00070
00071 /* I/O operation functions  *****************************************************/
00072
00073 #if defined(STM32F302xE) || \
00074     defined(STM32F302xC)
00075
00076 HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2);
00077
00078 #endif /* STM32F302xE || */
00079        /* STM32F302xC    */
00080
00081 #if defined(STM32F303xE) || defined(STM32F398xx) || \
00082     defined(STM32F303xC) || defined(STM32F358xx)
00083 HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4);
00084 #endif /* STM32F303xE || STM32F398xx || */
00085        /* STM32F303xC || STM32F358xx    */
00086
00087 /**
00088   * @}
00089   */
00090
00091 /**
00092   * @}
00093   */
00094
00095 /**
00096   * @}
00097   */
00098
00099 /**
00100   * @}
00101   */
00102
00103 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00104        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00105        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00106        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00107
00108 #ifdef __cplusplus
00109 }
00110 #endif
00111
00112
00113 #endif /* __STM32F3xx_HAL_OPAMP_EX_H */
00114
00115 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pccard.c Source File

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stm32f3xx_hal_pccard.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_pccard.c
00004   * @author  MCD Application Team
00005   * @brief   PCCARD HAL module driver.
00006   *          This file provides a generic firmware to drive PCCARD memories mounted
00007   *          as external device.
00008   *
00009   @verbatim
00010  ===============================================================================
00011                         ##### How to use this driver #####
00012  ===============================================================================
00013    [..]
00014      This driver is a generic layered driver which contains a set of APIs used to
00015      control PCCARD/compact flash memories. It uses the FMC layer functions
00016      to interface with PCCARD devices. This driver is used for:
00017
00018     (+) PCCARD/compact flash memory configuration sequence using the function
00019         HAL_PCCARD_Init() with control and timing parameters for both common and
00020         attribute spaces.
00021
00022     (+) Read PCCARD/compact flash memory maker and device IDs using the function
00023         HAL_PCCARD_Read_ID(). The read information is stored in the CompactFlash_ID
00024         structure declared by the function caller.
00025
00026     (+) Access PCCARD/compact flash memory by read/write operations using the functions
00027         HAL_PCCARD_Read_Sector()/HAL_PCCARD_Write_Sector(), to read/write sector.
00028
00029     (+) Perform PCCARD/compact flash Reset chip operation using the function HAL_PCCARD_Reset().
00030
00031     (+) Perform PCCARD/compact flash erase sector operation using the function
00032         HAL_PCCARD_Erase_Sector().
00033
00034     (+) Read the PCCARD/compact flash status operation using the function HAL_PCCARD_ReadStatus().
00035
00036     (+) You can monitor the PCCARD/compact flash  device HAL state by calling the function
00037         HAL_PCCARD_GetState()
00038
00039    [..]
00040      (@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
00041          operations. If a PCCARD/compact flash device contains different operations
00042          and/or implementations, it should be implemented separately.
00043
00044   @endverbatim
00045   ******************************************************************************
00046   * @attention
00047   *
00048   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00049   *
00050   * Redistribution and use in source and binary forms, with or without modification,
00051   * are permitted provided that the following conditions are met:
00052   *   1. Redistributions of source code must retain the above copyright notice,
00053   *      this list of conditions and the following disclaimer.
00054   *   2. Redistributions in binary form must reproduce the above copyright notice,
00055   *      this list of conditions and the following disclaimer in the documentation
00056   *      and/or other materials provided with the distribution.
00057   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00058   *      may be used to endorse or promote products derived from this software
00059   *      without specific prior written permission.
00060   *
00061   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00062   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00063   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00064   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00065   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00066   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00067   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00068   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00069   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00070   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00071   *
00072   ******************************************************************************
00073   */
00074
00075 /* Includes ------------------------------------------------------------------*/
00076 #include "stm32f3xx_hal.h"
00077
00078 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
00079 /** @addtogroup STM32F3xx_HAL_Driver
00080   * @{
00081   */
00082
00083 #ifdef HAL_PCCARD_MODULE_ENABLED
00084
00085 /** @defgroup PCCARD PCCARD
00086   * @brief PCCARD HAL module driver
00087   * @{
00088   */
00089
00090 /* Private typedef -----------------------------------------------------------*/
00091 /* Private define ------------------------------------------------------------*/
00092 /** @defgroup PCCARD_Private_Constants PCCARD Private Constants
00093   * @{
00094   */
00095
00096 #define PCCARD_TIMEOUT_READ_ID      0x0000FFFF
00097 #define PCCARD_TIMEOUT_SECTOR       0x0000FFFF
00098 #define PCCARD_TIMEOUT_STATUS       0x01000000
00099
00100 #define PCCARD_STATUS_OK            (uint8_t)0x58
00101 #define PCCARD_STATUS_WRITE_OK      (uint8_t)0x50
00102 /**
00103   * @}
00104   */
00105
00106 /* Private macro -------------------------------------------------------------*/
00107 /* Private variables ---------------------------------------------------------*/
00108 /* Private function prototypes -----------------------------------------------*/
00109 /* Exported functions ---------------------------------------------------------*/
00110
00111 /** @defgroup PCCARD_Exported_Functions PCCARD Exported Functions
00112   * @{
00113   */
00114
00115 /** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
00116   * @brief    Initialization and Configuration functions
00117   *
00118   @verbatim
00119   ==============================================================================
00120           ##### PCCARD Initialization and de-initialization functions #####
00121   ==============================================================================
00122   [..]
00123     This section provides functions allowing to initialize/de-initialize
00124     the PCCARD memory
00125
00126 @endverbatim
00127   * @{
00128   */
00129
00130 /**
00131   * @brief  Perform the PCCARD memory Initialization sequence
00132   * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
00133   *                the configuration information for PCCARD module.
00134   * @param  ComSpaceTiming Common space timing structure
00135   * @param  AttSpaceTiming Attribute space timing structure
00136   * @param  IOSpaceTiming IO space timing structure
00137   * @retval HAL status
00138   */
00139 HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
00140 {
00141   /* Check the PCCARD controller state */
00142   if(hpccard == NULL)
00143   {
00144      return HAL_ERROR;
00145   }
00146
00147   if(hpccard->State == HAL_PCCARD_STATE_RESET)
00148   {
00149     /* Allocate lock resource and initialize it */
00150     hpccard->Lock = HAL_UNLOCKED;
00151
00152     /* Initialize the low level hardware (MSP) */
00153     HAL_PCCARD_MspInit(hpccard);
00154   }
00155
00156   /* Initialize the PCCARD state */
00157   hpccard->State = HAL_PCCARD_STATE_BUSY;
00158
00159   /* Initialize PCCARD control Interface */
00160   FMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init));
00161
00162   /* Init PCCARD common space timing Interface */
00163   FMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming);
00164
00165   /* Init PCCARD attribute space timing Interface */
00166   FMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming);
00167
00168   /* Init PCCARD IO space timing Interface */
00169   FMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming);
00170
00171   /* Enable the PCCARD device */
00172   __FMC_PCCARD_ENABLE(hpccard->Instance);
00173
00174   /* Update the PCCARD state */
00175   hpccard->State = HAL_PCCARD_STATE_READY;
00176
00177   return HAL_OK;
00178
00179 }
00180
00181 /**
00182   * @brief  Perform the PCCARD memory De-initialization sequence
00183   * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
00184   *                the configuration information for PCCARD module.
00185   * @retval HAL status
00186   */
00187 HAL_StatusTypeDef  HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
00188 {
00189   /* De-Initialize the low level hardware (MSP) */
00190   HAL_PCCARD_MspDeInit(hpccard);
00191
00192   /* Configure the PCCARD registers with their reset values */
00193   FMC_PCCARD_DeInit(hpccard->Instance);
00194
00195   /* Update the PCCARD controller state */
00196   hpccard->State = HAL_PCCARD_STATE_RESET;
00197
00198   /* Release Lock */
00199   __HAL_UNLOCK(hpccard);
00200
00201   return HAL_OK;
00202 }
00203
00204 /**
00205   * @brief  PCCARD MSP Init
00206   * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
00207   *                the configuration information for PCCARD module.
00208   * @retval None
00209   */
00210 __weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
00211 {
00212   /* Prevent unused argument(s) compilation warning */
00213   UNUSED(hpccard);
00214
00215   /* NOTE : This function Should not be modified, when the callback is needed,
00216             the HAL_PCCARD_MspInit could be implemented in the user file
00217    */
00218 }
00219
00220 /**
00221   * @brief  PCCARD MSP DeInit
00222   * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
00223   *                the configuration information for PCCARD module.
00224   * @retval None
00225   */
00226 __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
00227 {
00228   /* Prevent unused argument(s) compilation warning */
00229   UNUSED(hpccard);
00230
00231   /* NOTE : This function Should not be modified, when the callback is needed,
00232             the HAL_PCCARD_MspDeInit could be implemented in the user file
00233    */
00234 }
00235
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup PCCARD_Exported_Functions_Group2 Input Output and memory functions
00241   * @brief    Input Output and memory control functions
00242   *
00243   @verbatim
00244   ==============================================================================
00245                 ##### PCCARD Input Output and memory functions #####
00246   ==============================================================================
00247   [..]
00248     This section provides functions allowing to use and control the PCCARD memory
00249
00250 @endverbatim
00251   * @{
00252   */
00253
00254 /**
00255   * @brief  Read Compact Flash's ID.
00256   * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
00257   *                the configuration information for PCCARD module.
00258   * @param  CompactFlash_ID Compact flash ID structure.
00259   * @param  pStatus pointer to compact flash status
00260   * @retval HAL status
00261   *
00262   */
00263 HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
00264 {
00265   uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U;
00266   uint8_t status = 0U;
00267
00268   /* Process Locked */
00269   __HAL_LOCK(hpccard);
00270
00271   /* Check the PCCARD controller state */
00272   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00273   {
00274      return HAL_BUSY;
00275   }
00276
00277   /* Update the PCCARD controller state */
00278   hpccard->State = HAL_PCCARD_STATE_BUSY;
00279
00280   /* Initialize the CF status */
00281   *pStatus = PCCARD_READY;
00282
00283   /* Send the Identify Command */
00284   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)  = 0xECEC;
00285
00286   /* Read CF IDs and timeout treatment */
00287   do
00288   {
00289      /* Read the CF status */
00290      status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00291
00292      timeout--;
00293   }while((status != PCCARD_STATUS_OK) && timeout);
00294
00295   if(timeout == 0U)
00296   {
00297     *pStatus = PCCARD_TIMEOUT_ERROR;
00298   }
00299   else
00300   {
00301      /* Read CF ID bytes */
00302     for(index = 0U; index < 16U; index++)
00303     {
00304       CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
00305     }
00306   }
00307
00308   /* Update the PCCARD controller state */
00309   hpccard->State = HAL_PCCARD_STATE_READY;
00310
00311   /* Process unlocked */
00312   __HAL_UNLOCK(hpccard);
00313
00314   return HAL_OK;
00315 }
00316
00317 /**
00318   * @brief  Read sector from PCCARD memory
00319   * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
00320   *                the configuration information for PCCARD module.
00321   * @param  pBuffer pointer to destination read buffer
00322   * @param  SectorAddress Sector address to read
00323   * @param  pStatus pointer to CF status
00324   * @retval HAL status
00325   */
00326 HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
00327 {
00328   uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U;
00329   uint8_t status = 0U;
00330
00331   /* Process Locked */
00332   __HAL_LOCK(hpccard);
00333
00334   /* Check the PCCARD controller state */
00335   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00336   {
00337      return HAL_BUSY;
00338   }
00339
00340   /* Update the PCCARD controller state */
00341   hpccard->State = HAL_PCCARD_STATE_BUSY;
00342
00343   /* Initialize CF status */
00344   *pStatus = PCCARD_READY;
00345
00346   /* Set the parameters to write a sector */
00347   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
00348   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT)  = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
00349   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)    = (uint16_t)0xE4A0;
00350
00351   do
00352   {
00353     /* wait till the Status = 0x80U */
00354     status =  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00355     timeout--;
00356   }while((status == 0x80U) && timeout);
00357
00358   if(timeout == 0U)
00359   {
00360     *pStatus = PCCARD_TIMEOUT_ERROR;
00361   }
00362
00363   timeout = 0xFFFFU;
00364
00365   do
00366   {
00367     /* wait till the Status = PCCARD_STATUS_OK */
00368     status =  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00369     timeout--;
00370   }while((status != PCCARD_STATUS_OK) && timeout);
00371
00372   if(timeout == 0U)
00373   {
00374     *pStatus = PCCARD_TIMEOUT_ERROR;
00375   }
00376
00377   /* Read bytes */
00378   for(; index < PCCARD_SECTOR_SIZE; index++)
00379   {
00380     *(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR);
00381   }
00382
00383   /* Update the PCCARD controller state */
00384   hpccard->State = HAL_PCCARD_STATE_READY;
00385
00386   /* Process unlocked */
00387   __HAL_UNLOCK(hpccard);
00388
00389   return HAL_OK;
00390 }
00391
00392
00393 /**
00394   * @brief  Write sector to PCCARD memory
00395   * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
00396   *                the configuration information for PCCARD module.
00397   * @param  pBuffer pointer to source write buffer
00398   * @param  SectorAddress Sector address to write
00399   * @param  pStatus pointer to CF status
00400   * @retval HAL status
00401   */
00402 HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,  uint8_t *pStatus)
00403 {
00404   uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U;
00405   uint8_t status = 0U;
00406
00407   /* Process Locked */
00408   __HAL_LOCK(hpccard);
00409
00410   /* Check the PCCARD controller state */
00411   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00412   {
00413      return HAL_BUSY;
00414   }
00415
00416   /* Update the PCCARD controller state */
00417   hpccard->State = HAL_PCCARD_STATE_BUSY;
00418
00419   /* Initialize CF status */
00420   *pStatus = PCCARD_READY;
00421
00422   /* Set the parameters to write a sector */
00423   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
00424   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT)  = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
00425   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)    = (uint16_t)0x30A0;
00426
00427   do
00428   {
00429     /* Wait till the Status = PCCARD_STATUS_OK */
00430     status =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00431     timeout--;
00432   }while((status != PCCARD_STATUS_OK) && timeout);
00433
00434   if(timeout == 0U)
00435   {
00436     *pStatus = PCCARD_TIMEOUT_ERROR;
00437   }
00438
00439   /* Write bytes */
00440   for(; index < PCCARD_SECTOR_SIZE; index++)
00441   {
00442     *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
00443   }
00444
00445   do
00446   {
00447     /* Wait till the Status = PCCARD_STATUS_WRITE_OK */
00448     status =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00449     timeout--;
00450   }while((status != PCCARD_STATUS_WRITE_OK) && timeout);
00451
00452   if(timeout == 0U)
00453   {
00454     *pStatus = PCCARD_TIMEOUT_ERROR;
00455   }
00456
00457   /* Update the PCCARD controller state */
00458   hpccard->State = HAL_PCCARD_STATE_READY;
00459
00460   /* Process unlocked */
00461   __HAL_UNLOCK(hpccard);
00462
00463   return HAL_OK;
00464 }
00465
00466
00467 /**
00468   * @brief  Erase sector from PCCARD memory
00469   * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
00470   *                the configuration information for PCCARD module.
00471   * @param  SectorAddress Sector address to erase
00472   * @param  pStatus pointer to CF status
00473   * @retval HAL status
00474   */
00475 HAL_StatusTypeDef  HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
00476 {
00477   uint32_t timeout = 0x400U;
00478   uint8_t status = 0U;
00479
00480   /* Process Locked */
00481   __HAL_LOCK(hpccard);
00482
00483   /* Check the PCCARD controller state */
00484   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00485   {
00486      return HAL_BUSY;
00487   }
00488
00489   /* Update the PCCARD controller state */
00490   hpccard->State = HAL_PCCARD_STATE_BUSY;
00491
00492   /* Initialize CF status */
00493   *pStatus = PCCARD_READY;
00494
00495   /* Set the parameters to write a sector */
00496   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW)  = 0x00;
00497   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00;
00498   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_NUMBER) = SectorAddress;
00499   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT)  = 0x01;
00500   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD)     = 0xA0;
00501   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)    = ATA_ERASE_SECTOR_CMD;
00502
00503   /* wait till the CF is ready */
00504   status =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00505
00506   while((status != PCCARD_STATUS_WRITE_OK) && timeout)
00507   {
00508     status =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00509     timeout--;
00510   }
00511
00512   if(timeout == 0U)
00513   {
00514     *pStatus = PCCARD_TIMEOUT_ERROR;
00515   }
00516
00517   /* Check the PCCARD controller state */
00518   hpccard->State = HAL_PCCARD_STATE_READY;
00519
00520   /* Process unlocked */
00521   __HAL_UNLOCK(hpccard);
00522
00523   return HAL_OK;
00524 }
00525
00526 /**
00527   * @brief  Reset the PCCARD memory
00528   * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
00529   *                the configuration information for PCCARD module.
00530   * @retval HAL status
00531   */
00532 HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
00533 {
00534   /* Process Locked */
00535   __HAL_LOCK(hpccard);
00536
00537   /* Check the PCCARD controller state */
00538   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00539   {
00540      return HAL_BUSY;
00541   }
00542
00543   /* Provide an SW reset and Read and verify the:
00544    - CF Configuration Option Register at address 0x98000200U --> 0x80
00545    - Card Configuration and Status Register     at address 0x98000202U --> 0x00
00546    - Pin Replacement Register  at address 0x98000204U --> 0x0C
00547    - Socket and Copy Register at address 0x98000206U --> 0x00
00548   */
00549
00550   /* Check the PCCARD controller state */
00551   hpccard->State = HAL_PCCARD_STATE_BUSY;
00552
00553   *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION) = 0x01;
00554
00555   /* Check the PCCARD controller state */
00556   hpccard->State = HAL_PCCARD_STATE_READY;
00557
00558   /* Process unlocked */
00559   __HAL_UNLOCK(hpccard);
00560
00561   return HAL_OK;
00562 }
00563
00564 /**
00565   * @brief  This function handles PCCARD device interrupt request.
00566   * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
00567   *                the configuration information for PCCARD module.
00568   * @retval HAL status
00569 */
00570 void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
00571 {
00572   /* Check PCCARD interrupt Rising edge flag */
00573   if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE))
00574   {
00575     /* PCCARD interrupt callback*/
00576     HAL_PCCARD_ITCallback(hpccard);
00577
00578     /* Clear PCCARD interrupt Rising edge pending bit */
00579     __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE);
00580   }
00581
00582   /* Check PCCARD interrupt Level flag */
00583   if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_LEVEL))
00584   {
00585     /* PCCARD interrupt callback*/
00586     HAL_PCCARD_ITCallback(hpccard);
00587
00588     /* Clear PCCARD interrupt Level pending bit */
00589     __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_LEVEL);
00590   }
00591
00592   /* Check PCCARD interrupt Falling edge flag */
00593   if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE))
00594   {
00595     /* PCCARD interrupt callback*/
00596     HAL_PCCARD_ITCallback(hpccard);
00597
00598     /* Clear PCCARD interrupt Falling edge pending bit */
00599     __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE);
00600   }
00601
00602   /* Check PCCARD interrupt FIFO empty flag */
00603   if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FEMPT))
00604   {
00605     /* PCCARD interrupt callback*/
00606     HAL_PCCARD_ITCallback(hpccard);
00607
00608     /* Clear PCCARD interrupt FIFO empty pending bit */
00609     __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FEMPT);
00610   }
00611
00612 }
00613
00614 /**
00615   * @brief  PCCARD interrupt feature callback
00616   * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
00617   *                the configuration information for PCCARD module.
00618   * @retval None
00619   */
00620 __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
00621 {
00622   /* Prevent unused argument(s) compilation warning */
00623   UNUSED(hpccard);
00624
00625   /* NOTE : This function Should not be modified, when the callback is needed,
00626             the HAL_PCCARD_ITCallback could be implemented in the user file
00627    */
00628 }
00629
00630 /**
00631   * @}
00632   */
00633
00634 /** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions
00635  *  @brief   Peripheral State functions
00636  *
00637 @verbatim
00638   ==============================================================================
00639                    ##### PCCARD Peripheral State functions #####
00640   ==============================================================================
00641   [..]
00642     This subsection permits to get in run-time the status of the PCCARD controller
00643     and the data flow.
00644
00645 @endverbatim
00646   * @{
00647   */
00648
00649 /**
00650   * @brief  return the PCCARD controller state
00651   * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
00652   *                the configuration information for PCCARD module.
00653   * @retval HAL state
00654   */
00655 HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
00656 {
00657   return hpccard->State;
00658 }
00659
00660 /**
00661   * @brief  Get the compact flash memory status
00662   * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
00663   *                the configuration information for PCCARD module.
00664   * @retval New status of the CF operation. This parameter can be:
00665   *          - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
00666   *            a Timeout error
00667   *          - CompactFlash_READY: when memory is ready for the next operation
00668   *
00669   */
00670 HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
00671 {
00672   uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_cf = 0U;
00673
00674   /* Check the PCCARD controller state */
00675   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00676   {
00677      return HAL_PCCARD_STATUS_ONGOING;
00678   }
00679
00680   status_cf =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00681
00682   while((status_cf == PCCARD_BUSY) && timeout)
00683   {
00684     status_cf =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00685     timeout--;
00686   }
00687
00688   if(timeout == 0U)
00689   {
00690     status_cf =  PCCARD_TIMEOUT_ERROR;
00691   }
00692
00693   /* Return the operation status */
00694   return (HAL_PCCARD_StatusTypeDef) status_cf;
00695 }
00696
00697 /**
00698   * @brief  Reads the Compact Flash memory status using the Read status command
00699   * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
00700   *                the configuration information for PCCARD module.
00701   * @retval The status of the Compact Flash memory. This parameter can be:
00702   *          - CompactFlash_BUSY: when memory is busy
00703   *          - CompactFlash_READY: when memory is ready for the next operation
00704   *          - CompactFlash_ERROR: when the previous operation gererates error
00705   */
00706 HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
00707 {
00708   uint8_t data = 0U, status_cf = PCCARD_BUSY;
00709
00710   /* Check the PCCARD controller state */
00711   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00712   {
00713      return HAL_PCCARD_STATUS_ONGOING;
00714   }
00715
00716   /* Read status operation */
00717   data =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00718
00719   if((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR)
00720   {
00721     status_cf = PCCARD_TIMEOUT_ERROR;
00722   }
00723   else if((data & PCCARD_READY) == PCCARD_READY)
00724   {
00725     status_cf = PCCARD_READY;
00726   }
00727
00728   return (HAL_PCCARD_StatusTypeDef) status_cf;
00729 }
00730
00731 /**
00732   * @}
00733   */
00734
00735 /**
00736   * @}
00737   */
00738 /**
00739   * @}
00740   */
00741
00742 #endif /* HAL_PCCARD_MODULE_ENABLED */
00743
00744 /**
00745   * @}
00746   */
00747 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
00748
00749 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pccard.h Source File

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stm32f3xx_hal_pccard.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_pccard.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PCCARD HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_PCCARD_H
00038 #define __STM32F3xx_HAL_PCCARD_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
00046 #include "stm32f3xx_ll_fmc.h"
00047
00048 /** @addtogroup STM32F3xx_HAL_Driver
00049   * @{
00050   */
00051
00052 /** @addtogroup PCCARD
00053   * @{
00054   */
00055
00056 /** @addtogroup PCCARD_Private_Constants
00057   * @{
00058   */
00059
00060 #define PCCARD_DEVICE_ADDRESS           FMC_BANK4
00061 #define PCCARD_ATTRIBUTE_SPACE_ADDRESS  ((uint32_t)(FMC_BANK4 + 0x08000000U))  /* Attribute space size to @0x9BFF FFFF */
00062 #define PCCARD_COMMON_SPACE_ADDRESS     PCCARD_DEVICE_ADDRESS                           /* Common space size to @0x93FF FFFF    */
00063 #define PCCARD_IO_SPACE_ADDRESS         ((uint32_t)(FMC_BANK4 + 0x0C000000U))  /* IO space size to @0x9FFF FFFF        */
00064 #define PCCARD_IO_SPACE_PRIMARY_ADDR    ((uint32_t)(FMC_BANK4 + 0x0C0001F0U))  /* IO space size to @0x9FFF FFFF        */
00065
00066 /* Compact Flash-ATA registers description */
00067 #define ATA_DATA                        ((uint8_t)0x00U)    /* Data register */
00068 #define ATA_SECTOR_COUNT                ((uint8_t)0x02U)    /* Sector Count register */
00069 #define ATA_SECTOR_NUMBER               ((uint8_t)0x03U)    /* Sector Number register */
00070 #define ATA_CYLINDER_LOW                ((uint8_t)0x04U)    /* Cylinder low register */
00071 #define ATA_CYLINDER_HIGH               ((uint8_t)0x05U)    /* Cylinder high register */
00072 #define ATA_CARD_HEAD                   ((uint8_t)0x06U)    /* Card/Head register */
00073 #define ATA_STATUS_CMD                  ((uint8_t)0x07U)    /* Status(read)/Command(write) register */
00074 #define ATA_STATUS_CMD_ALTERNATE        ((uint8_t)0x0EU)    /* Alternate Status(read)/Command(write) register */
00075 #define ATA_COMMON_DATA_AREA            ((uint16_t)0x0400U) /* Start of data area (for Common access only!) */
00076 #define ATA_CARD_CONFIGURATION          ((uint16_t)0x0202U) /* Card Configuration and Status Register */
00077
00078 /* Compact Flash-ATA commands */
00079 #define ATA_READ_SECTOR_CMD             ((uint8_t)0x20U)
00080 #define ATA_WRITE_SECTOR_CMD            ((uint8_t)0x30U)
00081 #define ATA_ERASE_SECTOR_CMD            ((uint8_t)0xC0U)
00082 #define ATA_IDENTIFY_CMD                ((uint8_t)0xECU)
00083
00084 /* Compact Flash status */
00085 #define PCCARD_TIMEOUT_ERROR            ((uint8_t)0x60U)
00086 #define PCCARD_BUSY                     ((uint8_t)0x80U)
00087 #define PCCARD_PROGR                    ((uint8_t)0x01U)
00088 #define PCCARD_READY                    ((uint8_t)0x40U)
00089
00090 #define PCCARD_SECTOR_SIZE              (255U)    /* In half words */
00091
00092
00093 /* Compact Flash redefinition */
00094 #define HAL_CF_Read_ID              HAL_PCCARD_Read_ID
00095 #define HAL_CF_Write_Sector         HAL_PCCARD_Write_Sector
00096 #define HAL_CF_Read_Sector          HAL_PCCARD_Read_Sector
00097 #define HAL_CF_Erase_Sector         HAL_PCCARD_Erase_Sector
00098 #define HAL_CF_Reset                HAL_PCCARD_Reset
00099
00100 #define HAL_CF_GetStatus            HAL_PCCARD_GetStatus
00101 #define HAL_CF_ReadStatus           HAL_PCCARD_ReadStatus
00102
00103 #define CF_SUCCESS                  HAL_PCCARD_STATUS_SUCCESS
00104 #define CF_ONGOING                  HAL_PCCARD_STATUS_ONGOING
00105 #define CF_ERROR                    HAL_PCCARD_STATUS_ERROR
00106 #define CF_TIMEOUT                  HAL_PCCARD_STATUS_TIMEOUT
00107 #define HAL_PCCARD_StatusTypeDef            HAL_PCCARD_StatusTypeDef
00108
00109
00110 #define CF_DEVICE_ADDRESS           PCCARD_DEVICE_ADDRESS
00111 #define CF_ATTRIBUTE_SPACE_ADDRESS  PCCARD_ATTRIBUTE_SPACE_ADDRESS
00112 #define CF_COMMON_SPACE_ADDRESS     PCCARD_COMMON_SPACE_ADDRESS
00113 #define CF_IO_SPACE_ADDRESS         PCCARD_IO_SPACE_ADDRESS
00114 #define CF_IO_SPACE_PRIMARY_ADDR    PCCARD_IO_SPACE_PRIMARY_ADDR
00115
00116 #define CF_TIMEOUT_ERROR            PCCARD_TIMEOUT_ERROR
00117 #define CF_BUSY                     PCCARD_BUSY
00118 #define CF_PROGR                    PCCARD_PROGR
00119 #define CF_READY                    PCCARD_READY
00120
00121 #define CF_SECTOR_SIZE              PCCARD_SECTOR_SIZE
00122
00123 /**
00124   * @}
00125   */
00126
00127 /* Exported typedef ----------------------------------------------------------*/
00128 /** @defgroup PCCARD_Exported_Types PCCARD Exported Types
00129   * @{
00130   */
00131
00132 /**
00133   * @brief  HAL PCCARD State structures definition
00134   */
00135 typedef enum
00136 {
00137   HAL_PCCARD_STATE_RESET     = 0x00U,    /*!< PCCARD peripheral not yet initialized or disabled */
00138   HAL_PCCARD_STATE_READY     = 0x01U,    /*!< PCCARD peripheral ready                           */
00139   HAL_PCCARD_STATE_BUSY      = 0x02U,    /*!< PCCARD peripheral busy                            */
00140   HAL_PCCARD_STATE_ERROR     = 0x04     /*!< PCCARD peripheral error                           */
00141 }HAL_PCCARD_StateTypeDef;
00142
00143 typedef enum
00144 {
00145   HAL_PCCARD_STATUS_SUCCESS = 0U,
00146   HAL_PCCARD_STATUS_ONGOING,
00147   HAL_PCCARD_STATUS_ERROR,
00148   HAL_PCCARD_STATUS_TIMEOUT
00149 }HAL_PCCARD_StatusTypeDef;
00150
00151 /**
00152   * @brief  FMC_PCCARD handle Structure definition
00153   */
00154 typedef struct
00155 {
00156   FMC_PCCARD_TypeDef           *Instance;              /*!< Register base address for PCCARD device          */
00157
00158   FMC_PCCARD_InitTypeDef       Init;                   /*!< PCCARD device control configuration parameters   */
00159
00160   __IO HAL_PCCARD_StateTypeDef State;                  /*!< PCCARD device access state                       */
00161
00162   HAL_LockTypeDef              Lock;                   /*!< PCCARD Lock                                      */
00163
00164 }PCCARD_HandleTypeDef;
00165 /**
00166   * @}
00167   */
00168
00169 /* Exported constants --------------------------------------------------------*/
00170 /* Exported macro ------------------------------------------------------------*/
00171 /** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
00172   * @{
00173   */
00174
00175 /** @brief Reset PCCARD handle state
00176   * @param  __HANDLE__ specifies the PCCARD handle.
00177   * @retval None
00178   */
00179 #define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
00180 /**
00181   * @}
00182   */
00183
00184 /* Exported functions --------------------------------------------------------*/
00185 /** @addtogroup PCCARD_Exported_Functions PCCARD Exported Functions
00186   * @{
00187   */
00188
00189 /** @addtogroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
00190   * @{
00191   */
00192 /* Initialization/de-initialization functions  **********************************/
00193 HAL_StatusTypeDef  HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
00194 HAL_StatusTypeDef  HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
00195 void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
00196 void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
00197 /**
00198   * @}
00199   */
00200
00201 /** @addtogroup PCCARD_Exported_Functions_Group2 Input Output and memory functions
00202   * @{
00203   */
00204 /* IO operation functions  *****************************************************/
00205 HAL_StatusTypeDef  HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
00206 HAL_StatusTypeDef  HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,  uint8_t *pStatus);
00207 HAL_StatusTypeDef  HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
00208 HAL_StatusTypeDef  HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
00209 HAL_StatusTypeDef  HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
00210 void               HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
00211 void               HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
00212
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions
00218   * @{
00219   */
00220 /* PCCARD State functions *******************************************************/
00221 HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
00222 HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
00223 HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
00224 /**
00225   * @}
00226   */
00227
00228 /**
00229   * @}
00230   */
00231 /**
00232   * @}
00233   */
00234
00235 /**
00236   * @}
00237   */
00238
00239 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
00240
00241 #ifdef __cplusplus
00242 }
00243 #endif
00244
00245 #endif /* __STM32F3xx_HAL_PCCARD_H */
00246
00247 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pcd.c Source File

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stm32f3xx_hal_pcd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_pcd.c
00004   * @author  MCD Application Team
00005   * @brief   PCD HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the USB Peripheral Controller:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                     ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018       The PCD HAL driver can be used as follows:
00019
00020      (#) Declare a PCD_HandleTypeDef handle structure, for example:
00021          PCD_HandleTypeDef  hpcd;
00022
00023      (#) Fill parameters of Init structure in HCD handle
00024
00025      (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...)
00026
00027      (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
00028          (##) Enable the PCD/USB Low Level interface clock using
00029               (+++) __HAL_RCC_USB_CLK_ENABLE();
00030
00031          (##) Initialize the related GPIO clocks
00032          (##) Configure PCD pin-out
00033          (##) Configure PCD NVIC interrupt
00034
00035      (#)Associate the Upper USB device stack to the HAL PCD Driver:
00036          (##) hpcd.pData = pdev;
00037
00038      (#)Enable HCD transmission and reception:
00039          (##) HAL_PCD_Start();
00040
00041   @endverbatim
00042   ******************************************************************************
00043   * @attention
00044   *
00045   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00046   *
00047   * Redistribution and use in source and binary forms, with or without modification,
00048   * are permitted provided that the following conditions are met:
00049   *   1. Redistributions of source code must retain the above copyright notice,
00050   *      this list of conditions and the following disclaimer.
00051   *   2. Redistributions in binary form must reproduce the above copyright notice,
00052   *      this list of conditions and the following disclaimer in the documentation
00053   *      and/or other materials provided with the distribution.
00054   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00055   *      may be used to endorse or promote products derived from this software
00056   *      without specific prior written permission.
00057   *
00058   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00059   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00060   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00061   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00062   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00063   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00064   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00065   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00066   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00067   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00068   *
00069   ******************************************************************************
00070   */
00071
00072 /* Includes ------------------------------------------------------------------*/
00073 #include "stm32f3xx_hal.h"
00074
00075 #ifdef HAL_PCD_MODULE_ENABLED
00076
00077 #if defined(STM32F302xE) || defined(STM32F303xE) || \
00078     defined(STM32F302xC) || defined(STM32F303xC) || \
00079     defined(STM32F302x8)                         || \
00080     defined(STM32F373xC)
00081
00082 /** @addtogroup STM32F3xx_HAL_Driver
00083   * @{
00084   */
00085
00086 /** @defgroup PCD PCD
00087   * @brief PCD HAL module driver
00088   * @{
00089   */
00090
00091 /* Private typedef -----------------------------------------------------------*/
00092 /* Private define ------------------------------------------------------------*/
00093
00094 /** @defgroup PCD_Private_Define PCD Private Define
00095   * @{
00096   */
00097 #define BTABLE_ADDRESS                  (0x000U)
00098 /**
00099   * @}
00100   */
00101
00102 /* Private macro -------------------------------------------------------------*/
00103 /* Private variables ---------------------------------------------------------*/
00104 /* Private function prototypes -----------------------------------------------*/
00105 /** @defgroup PCD_Private_Functions PCD Private Functions
00106   * @{
00107   */
00108 static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
00109 /**
00110   * @}
00111   */
00112
00113 /* Exported functions ---------------------------------------------------------*/
00114
00115 /** @defgroup PCD_Exported_Functions PCD Exported Functions
00116   * @{
00117   */
00118
00119 /** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00120  *  @brief    Initialization and Configuration functions
00121  *
00122 @verbatim
00123  ===============================================================================
00124             ##### Initialization and de-initialization functions #####
00125  ===============================================================================
00126     [..]  This section provides functions allowing to:
00127
00128 @endverbatim
00129   * @{
00130   */
00131
00132 /**
00133   * @brief  Initializes the PCD according to the specified
00134   *         parameters in the PCD_InitTypeDef and create the associated handle.
00135   * @param  hpcd PCD handle
00136   * @retval HAL status
00137   */
00138 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
00139 {
00140   uint32_t i = 0U;
00141
00142   uint32_t wInterrupt_Mask = 0U;
00143
00144   /* Check the PCD handle allocation */
00145   if(hpcd == NULL)
00146   {
00147     return HAL_ERROR;
00148   }
00149
00150   /* Check the parameters */
00151   assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
00152
00153   if(hpcd->State == HAL_PCD_STATE_RESET)
00154   {
00155     /* Allocate lock resource and initialize it */
00156     hpcd->Lock = HAL_UNLOCKED;
00157
00158     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00159     HAL_PCD_MspInit(hpcd);
00160   }
00161
00162   hpcd->State = HAL_PCD_STATE_BUSY;
00163
00164  /* Init endpoints structures */
00165  for (i = 0U; i < hpcd->Init.dev_endpoints ; i++)
00166  {
00167    /* Init ep structure */
00168    hpcd->IN_ep[i].is_in = 1U;
00169    hpcd->IN_ep[i].num = i;
00170    /* Control until ep is actvated */
00171    hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL;
00172    hpcd->IN_ep[i].maxpacket =  0U;
00173    hpcd->IN_ep[i].xfer_buff = 0U;
00174    hpcd->IN_ep[i].xfer_len = 0U;
00175  }
00176
00177  for (i = 0U; i < hpcd->Init.dev_endpoints ; i++)
00178  {
00179    hpcd->OUT_ep[i].is_in = 0U;
00180    hpcd->OUT_ep[i].num = i;
00181    /* Control until ep is activated */
00182    hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL;
00183    hpcd->OUT_ep[i].maxpacket = 0U;
00184    hpcd->OUT_ep[i].xfer_buff = 0U;
00185    hpcd->OUT_ep[i].xfer_len = 0U;
00186  }
00187
00188  /* Init Device */
00189  /*CNTR_FRES = 1U*/
00190  hpcd->Instance->CNTR = USB_CNTR_FRES;
00191
00192  /*CNTR_FRES = 0U*/
00193  hpcd->Instance->CNTR = 0U;
00194
00195  /*Clear pending interrupts*/
00196  hpcd->Instance->ISTR = 0U;
00197
00198   /*Set Btable Adress*/
00199  hpcd->Instance->BTABLE = BTABLE_ADDRESS;
00200
00201   /*set wInterrupt_Mask global variable*/
00202   wInterrupt_Mask = USB_CNTR_CTRM  | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
00203   | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM;
00204
00205   /*Set interrupt mask*/
00206   hpcd->Instance->CNTR = wInterrupt_Mask;
00207
00208   hpcd->USB_Address = 0U;
00209   hpcd->State= HAL_PCD_STATE_READY;
00210
00211  return HAL_OK;
00212 }
00213
00214 /**
00215   * @brief  DeInitializes the PCD peripheral
00216   * @param  hpcd PCD handle
00217   * @retval HAL status
00218   */
00219 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
00220 {
00221   /* Check the PCD handle allocation */
00222   if(hpcd == NULL)
00223   {
00224     return HAL_ERROR;
00225   }
00226
00227   hpcd->State = HAL_PCD_STATE_BUSY;
00228
00229   /* Stop Device */
00230   HAL_PCD_Stop(hpcd);
00231
00232   /* DeInit the low level hardware */
00233   HAL_PCD_MspDeInit(hpcd);
00234
00235   hpcd->State = HAL_PCD_STATE_RESET;
00236
00237   return HAL_OK;
00238 }
00239
00240 /**
00241   * @brief  Initializes the PCD MSP.
00242   * @param  hpcd PCD handle
00243   * @retval None
00244   */
00245 __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
00246 {
00247   /* Prevent unused argument(s) compilation warning */
00248   UNUSED(hpcd);
00249
00250   /* NOTE : This function should not be modified, when the callback is needed,
00251             the HAL_PCD_MspInit could be implemented in the user file
00252    */
00253 }
00254
00255 /**
00256   * @brief  DeInitializes PCD MSP.
00257   * @param  hpcd PCD handle
00258   * @retval None
00259   */
00260 __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
00261 {
00262   /* Prevent unused argument(s) compilation warning */
00263   UNUSED(hpcd);
00264
00265   /* NOTE : This function should not be modified, when the callback is needed,
00266             the HAL_PCD_MspDeInit could be implemented in the user file
00267    */
00268 }
00269
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup PCD_Exported_Functions_Group2 IO operation functions
00275  *  @brief   Data transfers functions
00276  *
00277 @verbatim
00278  ===============================================================================
00279                       ##### IO operation functions #####
00280  ===============================================================================
00281     [..]
00282     This subsection provides a set of functions allowing to manage the PCD data
00283     transfers.
00284
00285 @endverbatim
00286   * @{
00287   */
00288
00289 /**
00290   * @brief  Start the USB device.
00291   * @param  hpcd PCD handle
00292   * @retval HAL status
00293   */
00294 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
00295 {
00296   /*  DP Pull-Down is external */
00297   HAL_PCDEx_SetConnectionState (hpcd, 1U);
00298
00299   return HAL_OK;
00300 }
00301
00302 /**
00303   * @brief  Stop the USB device.
00304   * @param  hpcd PCD handle
00305   * @retval HAL status
00306   */
00307 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
00308 {
00309   __HAL_LOCK(hpcd);
00310
00311     /* disable all interrupts and force USB reset */
00312   hpcd->Instance->CNTR = USB_CNTR_FRES;
00313
00314   /* clear interrupt status register */
00315   hpcd->Instance->ISTR = 0U;
00316
00317   /* switch-off device */
00318   hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);
00319
00320   __HAL_UNLOCK(hpcd);
00321   return HAL_OK;
00322 }
00323 /**
00324   * @}
00325   */
00326
00327 /**
00328   * @}
00329   */
00330
00331 /** @addtogroup PCD_Private_Functions PCD Private Functions
00332   * @{
00333   */
00334 /**
00335   * @brief  This function handles PCD Endpoint interrupt request.
00336   * @param  hpcd PCD handle
00337   * @retval HAL status
00338   */
00339 static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
00340 {
00341   PCD_EPTypeDef *ep;
00342   uint16_t count=0U;
00343   uint8_t EPindex;
00344   __IO uint16_t wIstr;
00345   __IO uint16_t wEPVal = 0U;
00346
00347   /* stay in loop while pending interrupts */
00348   while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0U)
00349   {
00350     /* extract highest priority endpoint number */
00351     EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
00352
00353     if (EPindex == 0U)
00354     {
00355       /* Decode and service control endpoint interrupt */
00356
00357       /* DIR bit = origin of the interrupt */
00358       if ((wIstr & USB_ISTR_DIR) == 0U)
00359       {
00360         /* DIR = 0U */
00361
00362         /* DIR = 0      => IN  int */
00363         /* DIR = 0 implies that (EP_CTR_TX = 1U) always  */
00364         PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
00365         ep = &hpcd->IN_ep[0];
00366
00367         ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
00368         ep->xfer_buff += ep->xfer_count;
00369
00370         /* TX COMPLETE */
00371         HAL_PCD_DataInStageCallback(hpcd, 0U);
00372
00373
00374         if((hpcd->USB_Address > 0U)&& ( ep->xfer_len == 0U))
00375         {
00376           hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
00377           hpcd->USB_Address = 0U;
00378         }
00379
00380       }
00381       else
00382       {
00383         /* DIR = 1U */
00384
00385         /* DIR = 1U & CTR_RX       => SETUP or OUT int */
00386         /* DIR = 1U & (CTR_TX | CTR_RX) => 2 int pending */
00387         ep = &hpcd->OUT_ep[0];
00388         wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
00389
00390         if ((wEPVal & USB_EP_SETUP) != 0U)
00391         {
00392           /* Get SETUP Packet*/
00393           ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
00394           PCD_ReadPMA(hpcd->Instance, (uint8_t*)(void*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);
00395           /* SETUP bit kept frozen while CTR_RX = 1U*/
00396           PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
00397
00398           /* Process SETUP Packet*/
00399           HAL_PCD_SetupStageCallback(hpcd);
00400         }
00401
00402         else if ((wEPVal & USB_EP_CTR_RX) != 0U)
00403         {
00404           PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
00405           /* Get Control Data OUT Packet*/
00406           ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
00407
00408           if (ep->xfer_count != 0U)
00409           {
00410             PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
00411             ep->xfer_buff+=ep->xfer_count;
00412           }
00413
00414           /* Process Control Data OUT Packet*/
00415            HAL_PCD_DataOutStageCallback(hpcd, 0U);
00416
00417           PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket)
00418           PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID)
00419         }
00420       }
00421     }
00422     else
00423     {
00424
00425       /* Decode and service non control endpoints interrupt  */
00426
00427       /* process related endpoint register */
00428       wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex);
00429       if ((wEPVal & USB_EP_CTR_RX) != 0U)
00430       {
00431         /* clear int flag */
00432         PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex);
00433         ep = &hpcd->OUT_ep[EPindex];
00434
00435         /* OUT double Buffering*/
00436         if (ep->doublebuffer == 0U)
00437         {
00438           count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
00439           if (count != 0U)
00440           {
00441             PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
00442           }
00443         }
00444         else
00445         {
00446           if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_RX) == USB_EP_DTOG_RX)
00447           {
00448             /*read from endpoint BUF0Addr buffer*/
00449             count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
00450             if (count != 0U)
00451             {
00452               PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
00453             }
00454           }
00455           else
00456           {
00457             /*read from endpoint BUF1Addr buffer*/
00458             count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
00459             if (count != 0U)
00460             {
00461               PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
00462             }
00463           }
00464           PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT)
00465         }
00466         /*multi-packet on the NON control OUT endpoint*/
00467         ep->xfer_count+=count;
00468         ep->xfer_buff+=count;
00469
00470         if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
00471         {
00472           /* RX COMPLETE */
00473           HAL_PCD_DataOutStageCallback(hpcd, ep->num);
00474         }
00475         else
00476         {
00477           HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
00478         }
00479
00480       } /* if((wEPVal & EP_CTR_RX) */
00481
00482       if ((wEPVal & USB_EP_CTR_TX) != 0U)
00483       {
00484         ep = &hpcd->IN_ep[EPindex];
00485
00486         /* clear int flag */
00487         PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex);
00488
00489         /* IN double Buffering*/
00490         if (ep->doublebuffer == 0U)
00491         {
00492           ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
00493           if (ep->xfer_count != 0U)
00494           {
00495             PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
00496           }
00497         }
00498         else
00499         {
00500           if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
00501           {
00502             /*read from endpoint BUF0Addr buffer*/
00503             ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
00504             if (ep->xfer_count != 0U)
00505             {
00506               PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
00507             }
00508           }
00509           else
00510           {
00511             /*read from endpoint BUF1Addr buffer*/
00512             ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
00513             if (ep->xfer_count != 0U)
00514             {
00515               PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
00516             }
00517           }
00518           PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN)
00519         }
00520         /*multi-packet on the NON control IN endpoint*/
00521         ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
00522         ep->xfer_buff+=ep->xfer_count;
00523
00524         /* Zero Length Packet? */
00525         if (ep->xfer_len == 0U)
00526         {
00527           /* TX COMPLETE */
00528           HAL_PCD_DataInStageCallback(hpcd, ep->num);
00529         }
00530         else
00531         {
00532           HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
00533         }
00534       }
00535     }
00536   }
00537   return HAL_OK;
00538 }
00539 /**
00540   * @}
00541   */
00542
00543 /** @addtogroup PCD_Exported_Functions
00544   * @{
00545   */
00546
00547 /** @defgroup PCD_Exported_Functions_Group2 IO operation functions
00548  * @{
00549  */
00550
00551 /**
00552   * @brief  This function handles PCD interrupt request.
00553   * @param  hpcd PCD handle
00554   * @retval HAL status
00555   */
00556 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
00557 {
00558
00559   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR))
00560   {
00561     /* servicing of the endpoint correct transfer interrupt */
00562     /* clear of the CTR flag into the sub */
00563     PCD_EP_ISR_Handler(hpcd);
00564   }
00565
00566   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET))
00567   {
00568     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
00569     HAL_PCD_ResetCallback(hpcd);
00570     HAL_PCD_SetAddress(hpcd, 0U);
00571   }
00572
00573   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR))
00574   {
00575     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
00576   }
00577   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR))
00578   {
00579     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
00580   }
00581
00582   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
00583   {
00584     hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
00585     hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
00586
00587     HAL_PCD_ResumeCallback(hpcd);
00588
00589     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
00590   }
00591
00592   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP))
00593   {
00594     /* Force low-power mode in the macrocell */
00595     hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
00596
00597     /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
00598     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
00599
00600     hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
00601     if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0U)
00602     {
00603       HAL_PCD_SuspendCallback(hpcd);
00604     }
00605   }
00606
00607   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF))
00608   {
00609     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
00610     HAL_PCD_SOFCallback(hpcd);
00611   }
00612
00613   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF))
00614   {
00615     /* clear ESOF flag in ISTR */
00616     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
00617   }
00618 }
00619
00620 /**
00621   * @brief  Data out stage callbacks
00622   * @param  hpcd PCD handle
00623   * @param  epnum endpoint number
00624   * @retval None
00625   */
00626  __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00627 {
00628   /* Prevent unused argument(s) compilation warning */
00629   UNUSED(hpcd);
00630   UNUSED(epnum);
00631
00632   /* NOTE : This function should not be modified, when the callback is needed,
00633             the HAL_PCD_DataOutStageCallback could be implemented in the user file
00634    */
00635 }
00636
00637 /**
00638   * @brief  Data IN stage callbacks
00639   * @param  hpcd PCD handle
00640   * @param  epnum endpoint number
00641   * @retval None
00642   */
00643  __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00644 {
00645   /* Prevent unused argument(s) compilation warning */
00646   UNUSED(hpcd);
00647   UNUSED(epnum);
00648
00649   /* NOTE : This function should not be modified, when the callback is needed,
00650             the HAL_PCD_DataInStageCallback could be implemented in the user file
00651    */
00652 }
00653 /**
00654   * @brief  Setup stage callback
00655   * @param  hpcd PCD handle
00656   * @retval None
00657   */
00658  __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
00659 {
00660   /* Prevent unused argument(s) compilation warning */
00661   UNUSED(hpcd);
00662
00663   /* NOTE : This function should not be modified, when the callback is needed,
00664             the HAL_PCD_SetupStageCallback could be implemented in the user file
00665    */
00666 }
00667
00668 /**
00669   * @brief  USB Start Of Frame callbacks
00670   * @param  hpcd PCD handle
00671   * @retval None
00672   */
00673  __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
00674 {
00675   /* Prevent unused argument(s) compilation warning */
00676   UNUSED(hpcd);
00677
00678   /* NOTE : This function should not be modified, when the callback is needed,
00679             the HAL_PCD_SOFCallback could be implemented in the user file
00680    */
00681 }
00682
00683 /**
00684   * @brief  USB Reset callbacks
00685   * @param  hpcd PCD handle
00686   * @retval None
00687   */
00688  __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
00689 {
00690   /* Prevent unused argument(s) compilation warning */
00691   UNUSED(hpcd);
00692
00693   /* NOTE : This function should not be modified, when the callback is needed,
00694             the HAL_PCD_ResetCallback could be implemented in the user file
00695    */
00696 }
00697
00698 /**
00699   * @brief  Suspend event callbacks
00700   * @param  hpcd PCD handle
00701   * @retval None
00702   */
00703  __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
00704 {
00705   /* Prevent unused argument(s) compilation warning */
00706   UNUSED(hpcd);
00707
00708   /* NOTE : This function should not be modified, when the callback is needed,
00709             the HAL_PCD_SuspendCallback could be implemented in the user file
00710    */
00711 }
00712
00713 /**
00714   * @brief  Resume event callbacks
00715   * @param  hpcd PCD handle
00716   * @retval None
00717   */
00718  __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
00719 {
00720   /* Prevent unused argument(s) compilation warning */
00721   UNUSED(hpcd);
00722
00723   /* NOTE : This function should not be modified, when the callback is needed,
00724             the HAL_PCD_ResumeCallback could be implemented in the user file
00725    */
00726 }
00727
00728 /**
00729   * @brief  Incomplete ISO OUT callbacks
00730   * @param  hpcd PCD handle
00731   * @param  epnum endpoint number
00732   * @retval None
00733   */
00734  __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00735 {
00736   /* Prevent unused argument(s) compilation warning */
00737   UNUSED(hpcd);
00738   UNUSED(epnum);
00739
00740   /* NOTE : This function should not be modified, when the callback is needed,
00741             the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
00742    */
00743 }
00744
00745 /**
00746   * @brief  Incomplete ISO IN  callbacks
00747   * @param  hpcd PCD handle
00748   * @param  epnum endpoint number
00749   * @retval None
00750   */
00751  __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00752 {
00753   /* Prevent unused argument(s) compilation warning */
00754   UNUSED(hpcd);
00755   UNUSED(epnum);
00756
00757   /* NOTE : This function should not be modified, when the callback is needed,
00758             the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
00759    */
00760 }
00761
00762 /**
00763   * @brief  Connection event callbacks
00764   * @param  hpcd PCD handle
00765   * @retval None
00766   */
00767  __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
00768 {
00769   /* Prevent unused argument(s) compilation warning */
00770   UNUSED(hpcd);
00771
00772   /* NOTE : This function should not be modified, when the callback is needed,
00773             the HAL_PCD_ConnectCallback could be implemented in the user file
00774    */
00775 }
00776
00777 /**
00778   * @brief  Disconnection event callbacks
00779   * @param  hpcd PCD handle
00780   * @retval None
00781   */
00782  __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
00783 {
00784   /* Prevent unused argument(s) compilation warning */
00785   UNUSED(hpcd);
00786
00787   /* NOTE : This function should not be modified, when the callback is needed,
00788             the HAL_PCD_DisconnectCallback could be implemented in the user file
00789    */
00790 }
00791 /**
00792   * @}
00793   */
00794
00795 /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
00796  *  @brief   management functions
00797  *
00798 @verbatim
00799  ===============================================================================
00800                       ##### Peripheral Control functions #####
00801  ===============================================================================
00802     [..]
00803     This subsection provides a set of functions allowing to control the PCD data
00804     transfers.
00805
00806 @endverbatim
00807   * @{
00808   */
00809
00810 /**
00811   * @brief  Connect the USB device
00812   * @param  hpcd PCD handle
00813   * @retval HAL status
00814   */
00815 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
00816 {
00817   __HAL_LOCK(hpcd);
00818
00819   /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */
00820    HAL_PCDEx_SetConnectionState(hpcd, 1U);
00821
00822   __HAL_UNLOCK(hpcd);
00823   return HAL_OK;
00824 }
00825
00826 /**
00827   * @brief  Disconnect the USB device
00828   * @param  hpcd PCD handle
00829   * @retval HAL status
00830   */
00831 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
00832 {
00833   __HAL_LOCK(hpcd);
00834
00835   /* Disable DP Pull-Down bit*/
00836   HAL_PCDEx_SetConnectionState(hpcd, 0U);
00837
00838   __HAL_UNLOCK(hpcd);
00839   return HAL_OK;
00840 }
00841
00842 /**
00843   * @brief  Set the USB Device address
00844   * @param  hpcd PCD handle
00845   * @param  address new device address
00846   * @retval HAL status
00847   */
00848 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
00849 {
00850    __HAL_LOCK(hpcd);
00851
00852    if(address == 0U)
00853    {
00854      /* set device address and enable function */
00855      hpcd->Instance->DADDR = USB_DADDR_EF;
00856    }
00857    else /* USB Address will be applied later */
00858    {
00859      hpcd->USB_Address = address;
00860    }
00861
00862   __HAL_UNLOCK(hpcd);
00863   return HAL_OK;
00864 }
00865 /**
00866   * @brief  Open and configure an endpoint
00867   * @param  hpcd PCD handle
00868   * @param  ep_addr endpoint address
00869   * @param  ep_mps endpoint max packet size
00870   * @param  ep_type endpoint type
00871   * @retval HAL status
00872   */
00873 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
00874 {
00875   HAL_StatusTypeDef  ret = HAL_OK;
00876   PCD_EPTypeDef *ep;
00877
00878   if ((ep_addr & 0x80U) == 0x80U)
00879   {
00880     ep = &hpcd->IN_ep[ep_addr & 0x7FU];
00881   }
00882   else
00883   {
00884     ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
00885   }
00886   ep->num   = ep_addr & 0x7FU;
00887
00888   ep->is_in = (0x80U & ep_addr) != 0U;
00889   ep->maxpacket = ep_mps;
00890   ep->type = ep_type;
00891
00892   __HAL_LOCK(hpcd);
00893
00894   /* initialize Endpoint */
00895   switch (ep->type)
00896   {
00897   case PCD_EP_TYPE_CTRL:
00898     PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_CONTROL);
00899     break;
00900   case PCD_EP_TYPE_BULK:
00901     PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_BULK);
00902     break;
00903   case PCD_EP_TYPE_INTR:
00904     PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_INTERRUPT);
00905     break;
00906   case PCD_EP_TYPE_ISOC:
00907     PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS);
00908     break;
00909   default:
00910     break;
00911   }
00912
00913   PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num);
00914
00915   if (ep->doublebuffer == 0U)
00916   {
00917     if (ep->is_in)
00918     {
00919       /*Set the endpoint Transmit buffer address */
00920       PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
00921       PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
00922       /* Configure NAK status for the Endpoint*/
00923       PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK)
00924     }
00925     else
00926     {
00927       /*Set the endpoint Receive buffer address */
00928       PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
00929       /*Set the endpoint Receive buffer counter*/
00930       PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket)
00931       PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
00932       /* Configure VALID status for the Endpoint*/
00933       PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
00934     }
00935   }
00936   /*Double Buffer*/
00937   else
00938   {
00939     /*Set the endpoint as double buffered*/
00940     PCD_SET_EP_DBUF(hpcd->Instance, ep->num);
00941     /*Set buffer address for double buffered mode*/
00942     PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1)
00943
00944     if (ep->is_in==0U)
00945     {
00946       /* Clear the data toggle bits for the endpoint IN/OUT*/
00947       PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
00948       PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
00949
00950       /* Reset value of the data toggle bits for the endpoint out*/
00951       PCD_TX_DTOG(hpcd->Instance, ep->num);
00952
00953       PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
00954       PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
00955     }
00956     else
00957     {
00958       /* Clear the data toggle bits for the endpoint IN/OUT*/
00959       PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
00960       PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
00961       PCD_RX_DTOG(hpcd->Instance, ep->num);
00962       /* Configure DISABLE status for the Endpoint*/
00963       PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
00964       PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
00965     }
00966   }
00967
00968   __HAL_UNLOCK(hpcd);
00969   return ret;
00970 }
00971
00972
00973 /**
00974   * @brief  Deactivate an endpoint
00975   * @param  hpcd PCD handle
00976   * @param  ep_addr endpoint address
00977   * @retval HAL status
00978   */
00979 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
00980 {
00981   PCD_EPTypeDef *ep;
00982
00983   if ((ep_addr & 0x80U) == 0x80U)
00984   {
00985     ep = &hpcd->IN_ep[ep_addr & 0x7F];
00986   }
00987   else
00988   {
00989     ep = &hpcd->OUT_ep[ep_addr & 0x7F];
00990   }
00991   ep->num   = ep_addr & 0x7FU;
00992
00993   ep->is_in = (0x80U & ep_addr) != 0U;
00994
00995   __HAL_LOCK(hpcd);
00996
00997   if (ep->doublebuffer == 0U)
00998   {
00999     if (ep->is_in)
01000     {
01001       PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
01002       /* Configure DISABLE status for the Endpoint*/
01003       PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
01004     }
01005     else
01006     {
01007       PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
01008       /* Configure DISABLE status for the Endpoint*/
01009       PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
01010     }
01011   }
01012   /*Double Buffer*/
01013   else
01014   {
01015     if (ep->is_in==0U)
01016     {
01017       /* Clear the data toggle bits for the endpoint IN/OUT*/
01018       PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
01019       PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
01020
01021       /* Reset value of the data toggle bits for the endpoint out*/
01022       PCD_TX_DTOG(hpcd->Instance, ep->num);
01023
01024       PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
01025       PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
01026     }
01027     else
01028     {
01029       /* Clear the data toggle bits for the endpoint IN/OUT*/
01030       PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
01031       PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
01032       PCD_RX_DTOG(hpcd->Instance, ep->num);
01033       /* Configure DISABLE status for the Endpoint*/
01034       PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
01035       PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
01036     }
01037   }
01038
01039   __HAL_UNLOCK(hpcd);
01040   return HAL_OK;
01041 }
01042
01043
01044 /**
01045   * @brief  Receive an amount of data
01046   * @param  hpcd PCD handle
01047   * @param  ep_addr endpoint address
01048   * @param  pBuf pointer to the reception buffer
01049   * @param  len amount of data to be received
01050   * @retval HAL status
01051   */
01052 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
01053 {
01054
01055  PCD_EPTypeDef *ep;
01056
01057   ep = &hpcd->OUT_ep[ep_addr & 0x7F];
01058
01059   /*setup and start the Xfer */
01060   ep->xfer_buff = pBuf;
01061   ep->xfer_len = len;
01062   ep->xfer_count = 0U;
01063   ep->is_in = 0U;
01064   ep->num = ep_addr & 0x7FU;
01065
01066   /* Multi packet transfer*/
01067   if (ep->xfer_len > ep->maxpacket)
01068   {
01069     len=ep->maxpacket;
01070     ep->xfer_len-=len;
01071   }
01072   else
01073   {
01074     len=ep->xfer_len;
01075     ep->xfer_len =0U;
01076   }
01077
01078   /* configure and validate Rx endpoint */
01079   if (ep->doublebuffer == 0U)
01080   {
01081     /*Set RX buffer count*/
01082     PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len)
01083   }
01084   else
01085   {
01086     /*Set the Double buffer counter*/
01087     PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len)
01088   }
01089
01090   PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
01091
01092   return HAL_OK;
01093 }
01094
01095 /**
01096   * @brief  Get Received Data Size
01097   * @param  hpcd PCD handle
01098   * @param  ep_addr endpoint address
01099   * @retval Data Size
01100   */
01101 uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01102 {
01103   return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
01104 }
01105 /**
01106   * @brief  Send an amount of data
01107   * @param  hpcd PCD handle
01108   * @param  ep_addr endpoint address
01109   * @param  pBuf pointer to the transmission buffer
01110   * @param  len amount of data to be sent
01111   * @retval HAL status
01112   */
01113 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
01114 {
01115   PCD_EPTypeDef *ep;
01116   uint16_t pmabuffer = 0U;
01117
01118   ep = &hpcd->IN_ep[ep_addr & 0x7F];
01119
01120   /*setup and start the Xfer */
01121   ep->xfer_buff = pBuf;
01122   ep->xfer_len = len;
01123   ep->xfer_count = 0U;
01124   ep->is_in = 1U;
01125   ep->num = ep_addr & 0x7FU;
01126
01127   /*Multi packet transfer*/
01128   if (ep->xfer_len > ep->maxpacket)
01129   {
01130     len=ep->maxpacket;
01131     ep->xfer_len-=len;
01132   }
01133   else
01134   {
01135     len=ep->xfer_len;
01136     ep->xfer_len =0U;
01137   }
01138
01139   /* configure and validate Tx endpoint */
01140   if (ep->doublebuffer == 0U)
01141   {
01142     PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len);
01143     PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len);
01144   }
01145   else
01146   {
01147     /*Write the data to the USB endpoint*/
01148     if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
01149     {
01150       pmabuffer = ep->pmaaddr1;
01151     }
01152     else
01153     {
01154       pmabuffer = ep->pmaaddr0;
01155     }
01156     PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len);
01157     PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in)
01158   }
01159
01160   PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
01161
01162   return HAL_OK;
01163 }
01164
01165 /**
01166   * @brief  Set a STALL condition over an endpoint
01167   * @param  hpcd PCD handle
01168   * @param  ep_addr endpoint address
01169   * @retval HAL status
01170   */
01171 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01172 {
01173   PCD_EPTypeDef *ep;
01174
01175   __HAL_LOCK(hpcd);
01176
01177   if ((0x80U & ep_addr) == 0x80U)
01178   {
01179     ep = &hpcd->IN_ep[ep_addr & 0x7F];
01180   }
01181   else
01182   {
01183     ep = &hpcd->OUT_ep[ep_addr];
01184   }
01185
01186   ep->is_stall = 1U;
01187   ep->num   = ep_addr & 0x7FU;
01188   ep->is_in = ((ep_addr & 0x80U) == 0x80U);
01189
01190   if (ep->num == 0U)
01191   {
01192     /* This macro sets STALL status for RX & TX*/
01193     PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL)
01194   }
01195   else
01196   {
01197     if (ep->is_in)
01198     {
01199       PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL)
01200     }
01201     else
01202     {
01203       PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL)
01204     }
01205   }
01206   __HAL_UNLOCK(hpcd);
01207
01208   return HAL_OK;
01209 }
01210
01211 /**
01212   * @brief  Clear a STALL condition over in an endpoint
01213   * @param  hpcd PCD handle
01214   * @param  ep_addr endpoint address
01215   * @retval HAL status
01216   */
01217 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01218 {
01219   PCD_EPTypeDef *ep;
01220
01221   if ((0x80U & ep_addr) == 0x80U)
01222   {
01223     ep = &hpcd->IN_ep[ep_addr & 0x7F];
01224   }
01225   else
01226   {
01227     ep = &hpcd->OUT_ep[ep_addr];
01228   }
01229
01230   ep->is_stall = 0U;
01231   ep->num   = ep_addr & 0x7FU;
01232   ep->is_in = ((ep_addr & 0x80U) == 0x80U);
01233
01234   __HAL_LOCK(hpcd);
01235
01236   if (ep->is_in)
01237   {
01238     PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
01239     PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
01240   }
01241   else
01242   {
01243     PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
01244     PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
01245   }
01246   __HAL_UNLOCK(hpcd);
01247
01248   return HAL_OK;
01249 }
01250
01251 /**
01252   * @brief  Flush an endpoint
01253   * @param  hpcd PCD handle
01254   * @param  ep_addr endpoint address
01255   * @retval HAL status
01256   */
01257 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01258 {
01259   return HAL_OK;
01260 }
01261
01262 /**
01263   * @brief  HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling
01264   * @param  hpcd PCD handle
01265   * @retval HAL status
01266   */
01267 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01268 {
01269   hpcd->Instance->CNTR |= USB_CNTR_RESUME;
01270   return HAL_OK;
01271 }
01272
01273 /**
01274   * @brief  HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling
01275   * @param  hpcd PCD handle
01276   * @retval HAL status
01277   */
01278 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01279 {
01280   hpcd->Instance->CNTR &=~((uint32_t)USB_CNTR_RESUME);
01281   return HAL_OK;
01282 }
01283
01284 /**
01285   * @}
01286   */
01287
01288 /** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
01289  *  @brief   Peripheral State functions
01290  *
01291 @verbatim
01292  ===============================================================================
01293                       ##### Peripheral State functions #####
01294  ===============================================================================
01295     [..]
01296     This subsection permits to get in run-time the status of the peripheral
01297     and the data flow.
01298
01299 @endverbatim
01300   * @{
01301   */
01302
01303 /**
01304   * @brief  Return the PCD state
01305   * @param  hpcd PCD handle
01306   * @retval HAL state
01307   */
01308 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
01309 {
01310   return hpcd->State;
01311 }
01312 /**
01313   * @}
01314   */
01315
01316
01317 /**
01318   * @}
01319   */
01320
01321 /**
01322   * @}
01323   */
01324
01325 /**
01326   * @}
01327   */
01328
01329 #endif /* STM32F302xE || STM32F303xE || */
01330        /* STM32F302xC || STM32F303xC || */
01331        /* STM32F302x8                || */
01332        /* STM32F373xC                   */
01333
01334 #endif /* HAL_PCD_MODULE_ENABLED */
01335
01336 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pcd.h Source File

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stm32f3xx_hal_pcd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_pcd.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PCD HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_PCD_H
00038 #define __STM32F3xx_HAL_PCD_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 #if defined(STM32F302xE) || defined(STM32F303xE) || \
00045     defined(STM32F302xC) || defined(STM32F303xC) || \
00046     defined(STM32F302x8)                         || \
00047     defined(STM32F373xC)
00048
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f3xx_hal_def.h"
00051
00052 /** @addtogroup STM32F3xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @addtogroup PCD
00057   * @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /** @defgroup PCD_Exported_Types PCD Exported Types
00062   * @{
00063   */
00064
00065 /**
00066   * @brief  PCD State structure definition
00067   */
00068 typedef enum
00069 {
00070   HAL_PCD_STATE_RESET   = 0x00U,
00071   HAL_PCD_STATE_READY   = 0x01U,
00072   HAL_PCD_STATE_ERROR   = 0x02U,
00073   HAL_PCD_STATE_BUSY    = 0x03U,
00074   HAL_PCD_STATE_TIMEOUT = 0x04U
00075 } PCD_StateTypeDef;
00076
00077 /**
00078   * @brief  PCD double buffered endpoint direction
00079   */
00080 typedef enum
00081 {
00082   PCD_EP_DBUF_OUT,
00083   PCD_EP_DBUF_IN,
00084   PCD_EP_DBUF_ERR,
00085 }PCD_EP_DBUF_DIR;
00086
00087 /**
00088   * @brief  PCD endpoint buffer number
00089   */
00090 typedef enum
00091 {
00092   PCD_EP_NOBUF,
00093   PCD_EP_BUF0,
00094   PCD_EP_BUF1
00095 }PCD_EP_BUF_NUM;
00096
00097 /**
00098   * @brief  PCD Initialization Structure definition
00099   */
00100 typedef struct
00101 {
00102   uint32_t dev_endpoints;        /*!< Device Endpoints number.
00103                                       This parameter depends on the used USB core.
00104                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
00105
00106   uint32_t speed;                /*!< USB Core speed.
00107                                       This parameter can be any value of @ref PCD_Core_Speed                 */
00108
00109   uint32_t ep0_mps;              /*!< Set the Endpoint 0 Max Packet size.
00110                                       This parameter can be any value of @ref PCD_EP0_MPS                    */
00111
00112   uint32_t phy_itface;           /*!< Select the used PHY interface.
00113                                       This parameter can be any value of @ref PCD_Core_PHY                   */
00114
00115   uint32_t Sof_enable;           /*!< Enable or disable the output of the SOF signal.
00116                                       This parameter can be set to ENABLE or DISABLE                      */
00117
00118   uint32_t low_power_enable;     /*!< Enable or disable Low Power mode
00119                                       This parameter can be set to ENABLE or DISABLE                      */
00120
00121   uint32_t lpm_enable;           /*!< Enable or disable the Link Power Management .
00122                                       This parameter can be set to ENABLE or DISABLE                      */
00123
00124   uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.
00125                                       This parameter can be set to ENABLE or DISABLE                      */
00126
00127 }PCD_InitTypeDef;
00128
00129 typedef struct
00130 {
00131   uint8_t   num;            /*!< Endpoint number
00132                                 This parameter must be a number between Min_Data = 1 and Max_Data = 15    */
00133
00134   uint8_t   is_in;          /*!< Endpoint direction
00135                                 This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
00136
00137   uint8_t   is_stall;       /*!< Endpoint stall condition
00138                                 This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
00139
00140   uint8_t   type;           /*!< Endpoint type
00141                                  This parameter can be any value of @ref PCD_EP_Type                      */
00142
00143   uint16_t  pmaadress;      /*!< PMA Address
00144                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */
00145
00146
00147   uint16_t  pmaaddr0;       /*!< PMA Address0
00148                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */
00149
00150
00151   uint16_t  pmaaddr1;        /*!< PMA Address1
00152                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */
00153
00154
00155   uint8_t   doublebuffer;    /*!< Double buffer enable
00156                                  This parameter can be 0 or 1                                             */
00157
00158   uint32_t  maxpacket;      /*!< Endpoint Max packet size
00159                                  This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
00160
00161   uint8_t   *xfer_buff;     /*!< Pointer to transfer buffer                                               */
00162
00163
00164   uint32_t  xfer_len;       /*!< Current transfer length                                                  */
00165
00166   uint32_t  xfer_count;     /*!< Partial transfer length in case of multi packet transfer                 */
00167
00168 }PCD_EPTypeDef;
00169
00170 typedef   USB_TypeDef PCD_TypeDef;
00171
00172 /**
00173   * @brief  PCD Handle Structure definition
00174   */
00175 typedef struct
00176 {
00177   PCD_TypeDef             *Instance;   /*!< Register base address              */
00178   PCD_InitTypeDef         Init;       /*!< PCD required parameters            */
00179   __IO uint8_t            USB_Address; /*!< USB Address            */
00180   PCD_EPTypeDef           IN_ep[15];  /*!< IN endpoint parameters             */
00181   PCD_EPTypeDef           OUT_ep[15]; /*!< OUT endpoint parameters            */
00182   HAL_LockTypeDef         Lock;       /*!< PCD peripheral status              */
00183   __IO PCD_StateTypeDef   State;      /*!< PCD communication state            */
00184   uint32_t                Setup[12];  /*!< Setup packet buffer                */
00185   void                    *pData;      /*!< Pointer to upper stack Handler     */
00186
00187 } PCD_HandleTypeDef;
00188
00189 /**
00190   * @}
00191   */
00192
00193 /* Include PCD HAL Extension module */
00194 #include "stm32f3xx_hal_pcd_ex.h"
00195
00196 /* Exported constants --------------------------------------------------------*/
00197 /** @defgroup PCD_Exported_Constants PCD Exported Constants
00198   * @{
00199   */
00200
00201 /** @defgroup PCD_Core_Speed PCD Core Speed
00202   * @{
00203   */
00204 #define PCD_SPEED_HIGH               0U /* Not Supported */
00205 #define PCD_SPEED_FULL               2U
00206 /**
00207   * @}
00208   */
00209
00210   /** @defgroup PCD_Core_PHY PCD Core PHY
00211   * @{
00212   */
00213 #define PCD_PHY_EMBEDDED             2U
00214 /**
00215   * @}
00216   */
00217 /**
00218   * @}
00219   */
00220
00221 /* Exported macros -----------------------------------------------------------*/
00222 /** @defgroup PCD_Exported_Macros PCD Exported Macros
00223  *  @brief macros to handle interrupts and specific clock configurations
00224   * @{
00225   */
00226 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
00227 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    ((((__HANDLE__)->Instance->ISTR) = (uint16_t)(~(__INTERRUPT__))))
00228
00229 #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT()                 EXTI->IMR |= USB_WAKEUP_EXTI_LINE
00230 #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT()                EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
00231 #define __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__))
00232
00233 #define __HAL_USB_WAKEUP_EXTI_GET_FLAG()                  EXTI->PR & (USB_WAKEUP_EXTI_LINE)
00234 #define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG()                EXTI->PR = USB_WAKEUP_EXTI_LINE
00235
00236 #define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE()   do {\
00237                                                      EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE);\
00238                                                      EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;\
00239                                                    } while(0U)
00240
00241 #define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE()  do {\
00242                                                      EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE);\
00243                                                      EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE);\
00244                                                    } while(0U)
00245
00246 #define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\
00247                                                      EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE);\
00248                                                      EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE);\
00249                                                      EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;\
00250                                                      EXTI->FTSR |= USB_WAKEUP_EXTI_LINE;\
00251                                                    } while(0U)
00252 /**
00253   * @}
00254   */
00255
00256 /* Exported functions --------------------------------------------------------*/
00257 /** @addtogroup PCD_Exported_Functions PCD Exported Functions
00258   * @{
00259   */
00260
00261 /* Initialization/de-initialization functions  ********************************/
00262 /** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00263   * @{
00264   */
00265 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
00266 HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
00267 void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
00268 void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
00269 /**
00270   * @}
00271   */
00272
00273 /* I/O operation functions  ***************************************************/
00274 /* Non-Blocking mode: Interrupt */
00275 /** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
00276   * @{
00277   */
00278 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
00279 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
00280 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
00281
00282 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00283 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00284 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
00285 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
00286 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
00287 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
00288 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
00289 void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00290 void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00291 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
00292 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
00293 /**
00294   * @}
00295   */
00296
00297 /* Peripheral Control functions  **********************************************/
00298 /** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
00299   * @{
00300   */
00301 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
00302 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
00303 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
00304 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
00305 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00306 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00307 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00308 uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00309 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00310 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00311 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00312 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00313 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00314 /**
00315   * @}
00316   */
00317
00318 /* Peripheral State functions  ************************************************/
00319 /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
00320   * @{
00321   */
00322 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
00323 /**
00324   * @}
00325   */
00326
00327 /**
00328   * @}
00329   */
00330
00331 /* Private constants ---------------------------------------------------------*/
00332 /** @defgroup PCD_Private_Constants PCD Private Constants
00333   * @{
00334   */
00335 /** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
00336   * @{
00337   */
00338 #define  USB_WAKEUP_EXTI_LINE              ((uint32_t)EXTI_IMR_MR18)  /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup PCD_EP0_MPS PCD EP0 MPS
00344   * @{
00345   */
00346 #define DEP0CTL_MPS_64                         0U
00347 #define DEP0CTL_MPS_32                         1U
00348 #define DEP0CTL_MPS_16                         2U
00349 #define DEP0CTL_MPS_8                          3U
00350
00351 #define PCD_EP0MPS_64                          DEP0CTL_MPS_64
00352 #define PCD_EP0MPS_32                          DEP0CTL_MPS_32
00353 #define PCD_EP0MPS_16                          DEP0CTL_MPS_16
00354 #define PCD_EP0MPS_08                          DEP0CTL_MPS_8
00355 /**
00356   * @}
00357   */
00358
00359 /** @defgroup PCD_EP_Type PCD EP Type
00360   * @{
00361   */
00362 #define PCD_EP_TYPE_CTRL                       0U
00363 #define PCD_EP_TYPE_ISOC                       1U
00364 #define PCD_EP_TYPE_BULK                       2U
00365 #define PCD_EP_TYPE_INTR                       3U
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup PCD_ENDP PCD ENDP
00371   * @{
00372   */
00373 #define PCD_ENDP0                              ((uint8_t)0U)
00374 #define PCD_ENDP1                              ((uint8_t)1U)
00375 #define PCD_ENDP2                              ((uint8_t)2U)
00376 #define PCD_ENDP3                              ((uint8_t)3U)
00377 #define PCD_ENDP4                              ((uint8_t)4U)
00378 #define PCD_ENDP5                              ((uint8_t)5U)
00379 #define PCD_ENDP6                              ((uint8_t)6U)
00380 #define PCD_ENDP7                              ((uint8_t)7U)
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
00386   * @{
00387   */
00388 #define PCD_SNG_BUF                            0U
00389 #define PCD_DBL_BUF                            1U
00390 /**
00391   * @}
00392   */
00393
00394 /**
00395   * @}
00396   */
00397 /* Internal macros -----------------------------------------------------------*/
00398
00399 /* Private macros ------------------------------------------------------------*/
00400 /** @addtogroup PCD_Private_Macros PCD Private Macros
00401   * @{
00402   */
00403
00404 /* SetENDPOINT */
00405 #define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue)  (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue))
00406
00407 /* GetENDPOINT */
00408 #define PCD_GET_ENDPOINT(USBx, bEpNum)            (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U)))))
00409
00410
00411
00412 /**
00413   * @brief  sets the type in the endpoint register(bits EP_TYPE[1:0])
00414   * @param  USBx USB peripheral instance register address.
00415   * @param  bEpNum Endpoint Number.
00416   * @param  wType Endpoint Type.
00417   * @retval None
00418   */
00419 #define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
00420                                   ((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & ((uint32_t)(USB_EP_T_MASK))) | ((uint32_t)(wType)) )))
00421
00422 /**
00423   * @brief  gets the type in the endpoint register(bits EP_TYPE[1:0])
00424   * @param  USBx USB peripheral instance register address.
00425   * @param  bEpNum Endpoint Number.
00426   * @retval Endpoint Type
00427   */
00428 #define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD)
00429
00430
00431 /**
00432   * @brief free buffer used from the application realizing it to the line
00433           toggles bit SW_BUF in the double buffered endpoint register
00434   * @param  USBx USB peripheral instance register address.
00435   * @param  bEpNum Endpoint Number.
00436   * @param  bDir Direction
00437   * @retval None
00438   */
00439 #define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
00440 {\
00441   if ((bDir) == PCD_EP_DBUF_OUT)\
00442   { /* OUT double buffered endpoint */\
00443     PCD_TX_DTOG((USBx), (bEpNum));\
00444   }\
00445   else if ((bDir) == PCD_EP_DBUF_IN)\
00446   { /* IN double buffered endpoint */\
00447     PCD_RX_DTOG((USBx), (bEpNum));\
00448   }\
00449 }
00450
00451 /**
00452   * @brief gets direction of the double buffered endpoint
00453   * @param   USBx: USB peripheral instance register address.
00454   * @param   bEpNum: Endpoint Number.
00455   * @retval EP_DBUF_OUT, EP_DBUF_IN,
00456   *         EP_DBUF_ERR if the endpoint counter not yet programmed.
00457   */
00458 #define PCD_GET_DB_DIR(USBx, bEpNum)\
00459 {\
00460   if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00U) != 0U)\
00461     return(PCD_EP_DBUF_OUT);\
00462   else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FFU) != 0U)\
00463     return(PCD_EP_DBUF_IN);\
00464   else\
00465     return(PCD_EP_DBUF_ERR);\
00466 }
00467
00468 /**
00469   * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
00470   * @param  USBx USB peripheral instance register address.
00471   * @param  bEpNum Endpoint Number.
00472   * @param  wState new state
00473   * @retval None
00474   */
00475 #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
00476    \
00477     _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_DTOGMASK);\
00478    /* toggle first bit ? */     \
00479    if((USB_EPTX_DTOG1 & (wState))!= 0U)\
00480    {                                                                            \
00481      _wRegVal ^=(uint16_t) USB_EPTX_DTOG1;        \
00482    }                                                                            \
00483    /* toggle second bit ?  */         \
00484    if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U)      \
00485    {                                                                            \
00486      _wRegVal ^=(uint16_t) USB_EPTX_DTOG2;        \
00487    }                                                                            \
00488    PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX));\
00489   } /* PCD_SET_EP_TX_STATUS */
00490
00491 /**
00492   * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
00493   * @param  USBx USB peripheral instance register address.
00494   * @param  bEpNum Endpoint Number.
00495   * @param  wState new state
00496   * @retval None
00497   */
00498 #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
00499     register uint16_t _wRegVal;   \
00500     \
00501     _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_DTOGMASK);\
00502     /* toggle first bit ? */  \
00503     if((USB_EPRX_DTOG1 & (wState))!= 0U) \
00504     {                                                                             \
00505       _wRegVal ^= (uint16_t) USB_EPRX_DTOG1;  \
00506     }                                                                             \
00507     /* toggle second bit ? */  \
00508     if((USB_EPRX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
00509     {                                                                             \
00510       _wRegVal ^= (uint16_t) USB_EPRX_DTOG2;  \
00511     }                                                                             \
00512     PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
00513   } /* PCD_SET_EP_RX_STATUS */
00514
00515 /**
00516   * @brief  sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
00517   * @param  USBx USB peripheral instance register address.
00518   * @param  bEpNum Endpoint Number.
00519   * @param  wStaterx new state.
00520   * @param  wStatetx new state.
00521   * @retval None
00522   */
00523 #define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
00524     register uint32_t _wRegVal;   \
00525     \
00526     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
00527     /* toggle first bit ? */  \
00528     if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0U) \
00529     {                                                                                    \
00530       _wRegVal ^= USB_EPRX_DTOG1;  \
00531     }                                                                                    \
00532     /* toggle second bit ? */  \
00533     if((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
00534     {                                                                                    \
00535       _wRegVal ^= USB_EPRX_DTOG2;  \
00536     }                                                                                    \
00537     /* toggle first bit ? */     \
00538     if((USB_EPTX_DTOG1 & (wStatetx))!= 0U)      \
00539     {                                                                                    \
00540       _wRegVal ^= USB_EPTX_DTOG1;        \
00541     }                                                                                    \
00542     /* toggle second bit ?  */         \
00543     if((USB_EPTX_DTOG2 & (wStatetx))!= 0U)      \
00544     {                                                                                    \
00545       _wRegVal ^= USB_EPTX_DTOG2;        \
00546     }                                                                                    \
00547     PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX);    \
00548   } /* PCD_SET_EP_TXRX_STATUS */
00549
00550 /**
00551   * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]
00552   *         /STAT_RX[1:0])
00553   * @param  USBx USB peripheral instance register address.
00554   * @param  bEpNum Endpoint Number.
00555   * @retval status
00556   */
00557 #define PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT)
00558 #define PCD_GET_EP_RX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_STAT)
00559
00560 /**
00561   * @brief  sets directly the VALID tx/rx-status into the endpoint register
00562   * @param  USBx USB peripheral instance register address.
00563   * @param  bEpNum Endpoint Number.
00564   * @retval None
00565   */
00566 #define PCD_SET_EP_TX_VALID(USBx, bEpNum)     (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
00567
00568 #define PCD_SET_EP_RX_VALID(USBx, bEpNum)     (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
00569
00570 /**
00571   * @brief  checks stall condition in an endpoint.
00572   * @param  USBx USB peripheral instance register address.
00573   * @param  bEpNum Endpoint Number.
00574   * @retval TRUE = endpoint in stall condition.
00575   */
00576 #define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
00577                                    == USB_EP_TX_STALL)
00578 #define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
00579                                    == USB_EP_RX_STALL)
00580
00581 /**
00582   * @brief  set & clear EP_KIND bit.
00583   * @param  USBx USB peripheral instance register address.
00584   * @param  bEpNum Endpoint Number.
00585   * @retval None
00586   */
00587 #define PCD_SET_EP_KIND(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
00588                                 (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) | USB_EP_KIND) & USB_EPREG_MASK))))
00589 #define PCD_CLEAR_EP_KIND(USBx, bEpNum)  (PCD_SET_ENDPOINT((USBx), (bEpNum), \
00590                                 (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPKIND_MASK))))
00591
00592 /**
00593   * @brief  Sets/clears directly STATUS_OUT bit in the endpoint register.
00594   * @param  USBx USB peripheral instance register address.
00595   * @param  bEpNum Endpoint Number.
00596   * @retval None
00597   */
00598 #define PCD_SET_OUT_STATUS(USBx, bEpNum)    PCD_SET_EP_KIND((USBx), (bEpNum))
00599 #define PCD_CLEAR_OUT_STATUS(USBx, bEpNum)  PCD_CLEAR_EP_KIND((USBx), (bEpNum))
00600
00601 /**
00602   * @brief  Sets/clears directly EP_KIND bit in the endpoint register.
00603   * @param  USBx USB peripheral instance register address.
00604   * @param  bEpNum Endpoint Number.
00605   * @retval None
00606   */
00607 #define PCD_SET_EP_DBUF(USBx, bEpNum)   PCD_SET_EP_KIND((USBx), (bEpNum))
00608 #define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
00609
00610 /**
00611   * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
00612   * @param  USBx USB peripheral instance register address.
00613   * @param  bEpNum Endpoint Number.
00614   * @retval None
00615   */
00616 #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT((USBx), (bEpNum),\
00617                                    PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))
00618 #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT((USBx), (bEpNum),\
00619                                    PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))
00620
00621 /**
00622   * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
00623   * @param  USBx USB peripheral instance register address.
00624   * @param  bEpNum Endpoint Number.
00625   * @retval None
00626   */
00627 #define PCD_RX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
00628                                    USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
00629 #define PCD_TX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
00630                                    USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
00631
00632 /**
00633   * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
00634   * @param  USBx USB peripheral instance register address.
00635   * @param  bEpNum Endpoint Number.
00636   * @retval None
00637   */
00638 #define PCD_CLEAR_RX_DTOG(USBx, bEpNum)  if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\
00639                                          {                                                              \
00640                                            PCD_RX_DTOG((USBx),(bEpNum));\
00641                                          }
00642 #define PCD_CLEAR_TX_DTOG(USBx, bEpNum)  if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_TX) != 0)\
00643                                          {\
00644                                            PCD_TX_DTOG((USBx),(bEpNum));\
00645                                          }
00646
00647 /**
00648   * @brief  Sets address in an endpoint register.
00649   * @param  USBx USB peripheral instance register address.
00650   * @param  bEpNum Endpoint Number.
00651   * @param  bAddr Address.
00652   * @retval None
00653   */
00654 #define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
00655     USB_EP_CTR_RX|USB_EP_CTR_TX|(((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK) | (bAddr))
00656
00657 /**
00658   * @brief  Gets address in an endpoint register.
00659   * @param  USBx USB peripheral instance register address.
00660   * @param  bEpNum Endpoint Number.
00661   * @retval None
00662   */
00663 #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
00664
00665 /**
00666   * @brief  sets address of the tx/rx buffer.
00667   * @param  USBx USB peripheral instance register address.
00668   * @param  bEpNum Endpoint Number.
00669   * @param  wAddr address to be set (must be word aligned).
00670   * @retval None
00671   */
00672 #define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
00673 #define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
00674
00675 /**
00676   * @brief  Gets address of the tx/rx buffer.
00677   * @param  USBx USB peripheral instance register address.
00678   * @param  bEpNum Endpoint Number.
00679   * @retval address of the buffer.
00680   */
00681 #define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
00682 #define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
00683
00684 /**
00685   * @brief  Sets counter of rx buffer with no. of blocks.
00686   * @param  dwReg Register
00687   * @param  wCount Counter.
00688   * @param  wNBlocks no. of Blocks.
00689   * @retval None
00690   */
00691 #define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
00692     (wNBlocks) = (wCount) >> 5U;\
00693     if(((wCount) & 0x1fU) == 0U)\
00694     {                                                  \
00695       (wNBlocks)--;\
00696     }                                                  \
00697     *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | (uint16_t)0x8000U); \
00698   }/* PCD_CALC_BLK32 */
00699
00700
00701 #define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
00702     (wNBlocks) = (wCount) >> 1U;\
00703     if(((wCount) & 0x1U) != 0U)\
00704     {                                                  \
00705       (wNBlocks)++;\
00706     }                                                  \
00707     *pdwReg = (uint16_t)((wNBlocks) << 10U);\
00708   }/* PCD_CALC_BLK2 */
00709
00710 #define PCD_SET_EP_CNT_RX_REG(dwReg,wCount)  {\
00711     uint16_t wNBlocks;\
00712     if((wCount) > 62U)                                \
00713     {                                                \
00714       PCD_CALC_BLK32((dwReg),(wCount),wNBlocks)     \
00715     }                                                \
00716     else                                             \
00717     {                                                \
00718       PCD_CALC_BLK2((dwReg),(wCount),wNBlocks)     \
00719     }                                                \
00720   }/* PCD_SET_EP_CNT_RX_REG */
00721
00722 #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
00723     uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
00724     PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount))\
00725   }
00726
00727 /**
00728   * @brief  sets counter for the tx/rx buffer.
00729   * @param  USBx USB peripheral instance register address.
00730   * @param  bEpNum Endpoint Number.
00731   * @param  wCount Counter value.
00732   * @retval None
00733   */
00734 #define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
00735
00736 /**
00737   * @brief  gets counter of the tx buffer.
00738   * @param  USBx USB peripheral instance register address.
00739   * @param  bEpNum Endpoint Number.
00740   * @retval Counter value
00741   */
00742 #define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
00743 #define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
00744
00745 /**
00746   * @brief  Sets buffer 0/1 address in a double buffer endpoint.
00747   * @param  USBx USB peripheral instance register address.
00748   * @param  bEpNum Endpoint Number.
00749   * @param  wBuf0Addr: buffer 0 address.
00750   * @retval Counter value
00751   */
00752 #define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)))
00753 #define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) (PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)))
00754
00755 /**
00756   * @brief  Sets addresses in a double buffer endpoint.
00757   * @param  USBx USB peripheral instance register address.
00758   * @param  bEpNum Endpoint Number.
00759   * @param  wBuf0Addr: buffer 0 address.
00760   * @param  wBuf1Addr = buffer 1 address.
00761   * @retval None
00762   */
00763 #define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
00764     PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
00765     PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
00766   } /* PCD_SET_EP_DBUF_ADDR */
00767
00768 /**
00769   * @brief  Gets buffer 0/1 address of a double buffer endpoint.
00770   * @param  USBx USB peripheral instance register address.
00771   * @param  bEpNum Endpoint Number.
00772   * @retval None
00773   */
00774 #define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
00775 #define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
00776
00777 /**
00778   * @brief  Gets buffer 0/1 address of a double buffer endpoint.
00779   * @param  USBx USB peripheral instance register address.
00780   * @param  bEpNum Endpoint Number.
00781   * @param  bDir endpoint dir  EP_DBUF_OUT = OUT
00782   *         EP_DBUF_IN  = IN
00783   * @param  wCount Counter value
00784   * @retval None
00785   */
00786 #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)  { \
00787     if((bDir) == PCD_EP_DBUF_OUT)\
00788       /* OUT endpoint */ \
00789     {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount))} \
00790     else if((bDir) == PCD_EP_DBUF_IN)\
00791       {                                                       \
00792       *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount);  \
00793       }                                                       \
00794   } /* SetEPDblBuf0Count*/
00795
00796 #define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount)  { \
00797     if((bDir) == PCD_EP_DBUF_OUT)\
00798     {/* OUT endpoint */                                       \
00799       PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount))           \
00800     }                                                         \
00801     else if((bDir) == PCD_EP_DBUF_IN)\
00802     {/* IN endpoint */                                        \
00803       *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
00804     }                                                         \
00805   } /* SetEPDblBuf1Count */
00806
00807 #define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
00808     PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)) \
00809     PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)) \
00810   } /
00811
00812 /**
00813   * @brief  Gets buffer 0/1 rx/tx counter for double buffering.
00814   * @param  USBx USB peripheral instance register address.
00815   * @param  bEpNum Endpoint Number.
00816   * @retval None
00817   */
00818 #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
00819 #define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
00820 /**
00821   * @}
00822   */
00823
00824 /** @defgroup PCD_Instance_definition PCD Instance definition
00825   * @{
00826   */
00827 #define IS_PCD_ALL_INSTANCE                    IS_USB_ALL_INSTANCE
00828 /**
00829   * @}
00830   */
00831
00832 /** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
00833   * @{
00834   */
00835 /* Peripheral Control functions  ************************************************/
00836 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
00837 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
00838 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
00839 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
00840 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00841 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00842 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00843 uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00844 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00845 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00846 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00847 HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
00848 HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
00849 /**
00850   * @}
00851   */
00852
00853 /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
00854   * @{
00855   */
00856 /* Peripheral State functions  **************************************************/
00857 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
00858 /**
00859   * @}
00860   */
00861
00862 /** @addtogroup PCDEx_Private_Functions PCD Extended Private Functions
00863   * @{
00864   */
00865 void PCD_WritePMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
00866 void PCD_ReadPMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
00867 /**
00868   * @}
00869   */
00870
00871 /**
00872   * @}
00873   */
00874
00875 /**
00876   * @}
00877   */
00878
00879 #endif /* STM32F302xE || STM32F303xE || */
00880        /* STM32F302xC || STM32F303xC || */
00881        /* STM32F302x8                || */
00882        /* STM32F373xC                   */
00883
00884 #ifdef __cplusplus
00885 }
00886 #endif
00887
00888
00889 #endif /* __STM32F3xx_HAL_PCD_H */
00890
00891 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pcd_ex.c Source File

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stm32f3xx_hal_pcd_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_pcd_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended PCD HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the USB Peripheral Controller:
00008   *           + Configuration of the PMA for EP
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00014   *
00015   * Redistribution and use in source and binary forms, with or without modification,
00016   * are permitted provided that the following conditions are met:
00017   *   1. Redistributions of source code must retain the above copyright notice,
00018   *      this list of conditions and the following disclaimer.
00019   *   2. Redistributions in binary form must reproduce the above copyright notice,
00020   *      this list of conditions and the following disclaimer in the documentation
00021   *      and/or other materials provided with the distribution.
00022   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00023   *      may be used to endorse or promote products derived from this software
00024   *      without specific prior written permission.
00025   *
00026   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00027   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00028   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00029   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00030   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00031   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00032   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00033   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00034   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00035   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00036   *
00037   ******************************************************************************
00038   */
00039
00040 /* Includes ------------------------------------------------------------------*/
00041 #include "stm32f3xx_hal.h"
00042
00043 #ifdef HAL_PCD_MODULE_ENABLED
00044
00045 #if defined(STM32F302xE) || defined(STM32F303xE) || \
00046     defined(STM32F302xC) || defined(STM32F303xC) || \
00047     defined(STM32F302x8)                         || \
00048     defined(STM32F373xC)
00049
00050 /** @addtogroup STM32F3xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @defgroup PCDEx PCDEx
00055   * @brief PCD Extended HAL module driver
00056   * @{
00057   */
00058
00059 /* Private typedef -----------------------------------------------------------*/
00060 /* Private define ------------------------------------------------------------*/
00061 /* Private macro -------------------------------------------------------------*/
00062 /* Private variables ---------------------------------------------------------*/
00063 /* Private function prototypes -----------------------------------------------*/
00064 /* Exported functions ---------------------------------------------------------*/
00065
00066 /** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
00067   * @{
00068   */
00069
00070 /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00071   * @brief    PCDEx control functions
00072   *
00073 @verbatim
00074  ===============================================================================
00075               ##### Extended Peripheral Control functions #####
00076  ===============================================================================
00077     [..]  This section provides functions allowing to:
00078       (+) Update PMA configuration
00079
00080 @endverbatim
00081   * @{
00082   */
00083
00084 /**
00085   * @brief Configure PMA for EP
00086   * @param  hpcd PCD handle
00087   * @param  ep_addr endpoint address
00088   * @param  ep_kind endpoint Kind
00089   *                @arg USB_SNG_BUF: Single Buffer used
00090   *                @arg USB_DBL_BUF: Double Buffer used
00091   * @param  pmaadress EP address in The PMA: In case of single buffer endpoint
00092   *                   this parameter is 16-bit value providing the address
00093   *                   in PMA allocated to endpoint.
00094   *                   In case of double buffer endpoint this parameter
00095   *                   is a 32-bit value providing the endpoint buffer 0 address
00096   *                   in the LSB part of 32-bit value and endpoint buffer 1 address
00097   *                   in the MSB part of 32-bit value.
00098   * @retval : status
00099   */
00100
00101 HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
00102                         uint16_t ep_addr,
00103                         uint16_t ep_kind,
00104                         uint32_t pmaadress)
00105
00106 {
00107   PCD_EPTypeDef *ep;
00108
00109   /* initialize ep structure*/
00110   if ((0x80U & ep_addr) == 0x80U)
00111   {
00112     ep = &hpcd->IN_ep[ep_addr & 0x7FU];
00113   }
00114   else
00115   {
00116     ep = &hpcd->OUT_ep[ep_addr];
00117   }
00118
00119   /* Here we check if the endpoint is single or double Buffer*/
00120   if (ep_kind == PCD_SNG_BUF)
00121   {
00122     /*Single Buffer*/
00123     ep->doublebuffer = 0U;
00124     /*Configure the PMA*/
00125     ep->pmaadress = (uint16_t)pmaadress;
00126   }
00127   else /*USB_DBL_BUF*/
00128   {
00129     /*Double Buffer Endpoint*/
00130     ep->doublebuffer = 1;
00131     /*Configure the PMA*/
00132     ep->pmaaddr0 =  pmaadress & 0xFFFFU;
00133     ep->pmaaddr1 =  (pmaadress & 0xFFFF0000U) >> 16U;
00134   }
00135
00136   return HAL_OK;
00137 }
00138 /**
00139   * @}
00140   */
00141
00142 /**
00143   * @}
00144   */
00145
00146 /** @defgroup PCDEx_Private_Functions PCD Extended Private Functions
00147   * @{
00148   */
00149 #if defined(STM32F303xC)                         || \
00150     defined(STM32F303x8) || defined(STM32F334x8) || \
00151     defined(STM32F301x8)                         || \
00152     defined(STM32F373xC) || defined(STM32F378xx) || \
00153     defined(STM32F302xC)
00154
00155 /**
00156   * @brief Copy a buffer from user memory area to packet memory area (PMA)
00157   * @param   USBx: USB peripheral instance register address.
00158   * @param   pbUsrBuf: pointer to user memory area.
00159   * @param   wPMABufAddr: address into PMA.
00160   * @param   wNBytes: no. of bytes to be copied.
00161   * @retval None
00162   */
00163 void PCD_WritePMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
00164 {
00165   uint32_t n =  ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
00166
00167   uint32_t i, temp1, temp2;
00168   uint16_t *pdwVal;
00169   pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U));
00170
00171   for (i = n; i != 0; i--)
00172   {
00173     temp1 = (uint16_t) * pbUsrBuf;
00174     pbUsrBuf++;
00175     temp2 = temp1 | ((uint16_t)((uint16_t)  * pbUsrBuf << 8U)) ;
00176     *pdwVal++ = temp2;
00177     pdwVal++;
00178     pbUsrBuf++;
00179   }
00180 }
00181
00182 /**
00183   * @brief Copy a buffer from user memory area to packet memory area (PMA)
00184   * @param   USBx: USB peripheral instance register address.
00185   * @param   pbUsrBuf: pointer to user memory area.
00186   * @param   wPMABufAddr: address into PMA.
00187   * @param   wNBytes: no. of bytes to be copied.
00188   * @retval None
00189   */
00190 void PCD_ReadPMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
00191 {
00192   uint32_t n = (uint32_t)wNBytes >> 1U;
00193   uint32_t i;
00194   uint16_t *pdwVal;
00195   uint32_t temp;
00196   pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U));
00197
00198   for (i = n; i != 0U; i--)
00199   {
00200     temp = *pdwVal++;
00201     *pbUsrBuf++ = ((temp >> 0) & 0xFF);
00202     *pbUsrBuf++ = ((temp >> 8) & 0xFF);
00203     pdwVal++;
00204   }
00205
00206   if (wNBytes % 2)
00207   {
00208     temp = *pdwVal++;
00209     *pbUsrBuf++ = ((temp >> 0) & 0xFF);
00210   }
00211 }
00212 #endif /* STM32F303xC                || */
00213        /* STM32F303x8 || STM32F334x8 || */
00214        /* STM32F301x8                || */
00215        /* STM32F373xC || STM32F378xx    */
00216
00217 #if defined(STM32F302xE) || defined(STM32F303xE) || \
00218     defined(STM32F302x8)
00219 /**
00220   * @brief Copy a buffer from user memory area to packet memory area (PMA)
00221   * @param   USBx: USB peripheral instance register address.
00222   * @param   pbUsrBuf: pointer to user memory area.
00223   * @param   wPMABufAddr: address into PMA.
00224   * @param   wNBytes: no. of bytes to be copied.
00225   * @retval None
00226   */
00227 void PCD_WritePMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
00228 {
00229   uint32_t n =  ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
00230   uint32_t i;
00231   uint16_t temp1, temp2;
00232   uint16_t *pdwVal;
00233   pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U));
00234   for (i = n; i != 0U; i--)
00235   {
00236     temp1 = (uint16_t) * pbUsrBuf;
00237     pbUsrBuf++;
00238     temp2 = temp1 | ((uint16_t)((uint16_t)  * pbUsrBuf << 8U)) ;
00239     *pdwVal++ = temp2;
00240     pbUsrBuf++;
00241   }
00242 }
00243
00244 /**
00245   * @brief Copy a buffer from user memory area to packet memory area (PMA)
00246   * @param   USBx: USB peripheral instance register address.
00247   * @param   pbUsrBuf: pointer to user memory area.
00248   * @param   wPMABufAddr: address into PMA.
00249   * @param   wNBytes: no. of bytes to be copied.
00250   * @retval None
00251   */
00252 void PCD_ReadPMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
00253 {
00254   uint32_t n = (uint32_t)wNBytes >> 1U;
00255   uint32_t i;
00256   uint16_t *pdwVal;
00257   uint32_t temp;
00258   pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U));
00259
00260   for (i = n; i != 0U; i--)
00261   {
00262     temp = *pdwVal++;
00263     *pbUsrBuf++ = ((temp >> 0) & 0xFF);
00264     *pbUsrBuf++ = ((temp >> 8) & 0xFF);
00265   }
00266
00267   if (wNBytes % 2)
00268   {
00269     temp = *pdwVal++;
00270     *pbUsrBuf++ = ((temp >> 0) & 0xFF);
00271   }
00272 }
00273 #endif /* STM32F302xE || STM32F303xE || */
00274        /* STM32F302xC                || */
00275        /* STM32F302x8                   */
00276
00277 /**
00278   * @}
00279   */
00280
00281 /** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
00282   * @{
00283   */
00284
00285 /** @addtogroup PCDEx_Exported_Functions_Group2 Extended Initialization and de-initialization functions
00286   * @{
00287   */
00288 /**
00289   * @brief  Software Device Connection
00290   * @param  hpcd PCD handle
00291   * @param  state Device state
00292   * @retval None
00293   */
00294  __weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
00295 {
00296   /* Prevent unused argument(s) compilation warning */
00297   UNUSED(hpcd);
00298   UNUSED(state);
00299
00300   /* NOTE : This function Should not be modified, when the callback is needed,
00301             the HAL_PCDEx_SetConnectionState could be implenetd in the user file
00302    */
00303 }
00304 /**
00305   * @}
00306   */
00307
00308 /**
00309   * @}
00310   */
00311
00312 /**
00313   * @}
00314   */
00315
00316 /**
00317   * @}
00318   */
00319
00320 #endif /* STM32F302xE || STM32F303xE || */
00321        /* STM32F302xC || STM32F303xC || */
00322        /* STM32F302x8                || */
00323        /* STM32F373xC                   */
00324
00325 #endif /* HAL_PCD_MODULE_ENABLED */
00326
00327 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pcd_ex.h Source File

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stm32f3xx_hal_pcd_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_pcd_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PCD HAL Extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_PCD_EX_H
00038 #define __STM32F3xx_HAL_PCD_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 #if defined(STM32F302xE) || defined(STM32F303xE) || \
00045     defined(STM32F302xC) || defined(STM32F303xC) || \
00046     defined(STM32F302x8)                         || \
00047     defined(STM32F373xC)
00048
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f3xx_hal_def.h"
00051
00052 /** @addtogroup STM32F3xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @addtogroup PCDEx
00057   * @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /* Exported constants --------------------------------------------------------*/
00062 /* Exported macros -----------------------------------------------------------*/
00063 /** @defgroup PCDEx_Exported_Macros PCD Extended Exported Macros
00064   * @{
00065   */
00066 /**
00067   * @brief  Gets address in an endpoint register.
00068   * @param  USBx USB peripheral instance register address.
00069   * @param  bEpNum Endpoint Number.
00070   * @retval None
00071   */
00072
00073 #if defined(STM32F302xC) || defined(STM32F303xC) || \
00074     defined(STM32F373xC)
00075
00076 #define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)*2+     ((uint32_t)(USBx) + 0x400U)))))
00077 #define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)*2+  ((uint32_t)(USBx) + 0x400U)))))
00078 #define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400U)))))
00079 #define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)*2+  ((uint32_t)(USBx) + 0x400U)))))
00080
00081
00082 #define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
00083     uint16_t *pdwReg =PCD_EP_RX_CNT((USBx),(bEpNum)); \
00084     PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
00085   }
00086
00087 #endif /* STM32F302xC || STM32F303xC || */
00088        /* STM32F373xC                   */
00089
00090
00091 #if defined(STM32F302xE) || defined(STM32F303xE) || \
00092     defined(STM32F302x8)
00093
00094 #define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)+     ((uint32_t)(USBx) + 0x400U)))))
00095 #define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)+  ((uint32_t)(USBx) + 0x400U)))))
00096 #define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400U)))))
00097 #define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)+  ((uint32_t)(USBx) + 0x400U)))))
00098
00099 #define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
00100     uint16_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum));\
00101     PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
00102   }
00103
00104 #endif /* STM32F302xE || STM32F303xE || */
00105        /* STM32F302x8                   */
00106 /**
00107   * @}
00108   */
00109
00110 /* Exported functions --------------------------------------------------------*/
00111 /** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
00112   * @{
00113   */
00114 /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00115   * @{
00116   */
00117 HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
00118                                      uint16_t ep_addr,
00119                                      uint16_t ep_kind,
00120                                      uint32_t pmaadress);
00121
00122 void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
00123
00124 /**
00125   * @}
00126   */
00127
00128 /**
00129   * @}
00130   */
00131
00132 /**
00133   * @}
00134   */
00135
00136 /**
00137   * @}
00138   */
00139
00140 #endif /* STM32F302xE || STM32F303xE || */
00141        /* STM32F302xC || STM32F303xC || */
00142        /* STM32F302x8                || */
00143        /* STM32F373xC                   */
00144
00145 #ifdef __cplusplus
00146 }
00147 #endif
00148
00149
00150 #endif /* __STM32F3xx_HAL_PCD_EX_H */
00151
00152 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pwr.c Source File

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stm32f3xx_hal_pwr.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_pwr.c
00004   * @author  MCD Application Team
00005   * @brief   PWR HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Power Controller (PWR) peripheral:
00008   *           + Initialization/de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   @verbatim
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00016   *
00017   * Redistribution and use in source and binary forms, with or without modification,
00018   * are permitted provided that the following conditions are met:
00019   *   1. Redistributions of source code must retain the above copyright notice,
00020   *      this list of conditions and the following disclaimer.
00021   *   2. Redistributions in binary form must reproduce the above copyright notice,
00022   *      this list of conditions and the following disclaimer in the documentation
00023   *      and/or other materials provided with the distribution.
00024   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00025   *      may be used to endorse or promote products derived from this software
00026   *      without specific prior written permission.
00027   *
00028   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00029   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00030   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00031   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00032   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00033   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00034   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00036   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00037   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00038   *
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32f3xx_hal.h"
00044
00045 /** @addtogroup STM32F3xx_HAL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup PWR PWR
00050   * @brief PWR HAL module driver
00051   * @{
00052   */
00053
00054 #ifdef HAL_PWR_MODULE_ENABLED
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /* Private define ------------------------------------------------------------*/
00058 /* Private macro -------------------------------------------------------------*/
00059 /* Private variables ---------------------------------------------------------*/
00060 /* Private function prototypes -----------------------------------------------*/
00061 /* Private functions ---------------------------------------------------------*/
00062
00063 /** @defgroup PWR_Exported_Functions PWR Exported Functions
00064   * @{
00065   */
00066
00067 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
00068   *  @brief    Initialization and de-initialization functions
00069   *
00070 @verbatim
00071  ===============================================================================
00072               ##### Initialization and de-initialization functions #####
00073  ===============================================================================
00074     [..]
00075       After reset, the backup domain (RTC registers, RTC backup data
00076       registers and backup SRAM) is protected against possible unwanted
00077       write accesses.
00078       To enable access to the RTC Domain and RTC registers, proceed as follows:
00079         (+) Enable the Power Controller (PWR) APB1 interface clock using the
00080             __HAL_RCC_PWR_CLK_ENABLE() macro.
00081         (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
00082
00083 @endverbatim
00084   * @{
00085   */
00086
00087 /**
00088   * @brief Deinitializes the PWR peripheral registers to their default reset values.
00089   * @retval None
00090   */
00091 void HAL_PWR_DeInit(void)
00092 {
00093   __HAL_RCC_PWR_FORCE_RESET();
00094   __HAL_RCC_PWR_RELEASE_RESET();
00095 }
00096
00097 /**
00098   * @brief Enables access to the backup domain (RTC registers, RTC
00099   *         backup data registers and backup SRAM).
00100   * @note  If the HSE divided by 32 is used as the RTC clock, the
00101   *         Backup Domain Access should be kept enabled.
00102   * @retval None
00103   */
00104 void HAL_PWR_EnableBkUpAccess(void)
00105 {
00106   SET_BIT(PWR->CR, PWR_CR_DBP);
00107 }
00108
00109 /**
00110   * @brief Disables access to the backup domain (RTC registers, RTC
00111   *         backup data registers and backup SRAM).
00112   * @note  If the HSE divided by 32 is used as the RTC clock, the
00113   *         Backup Domain Access should be kept enabled.
00114   * @retval None
00115   */
00116 void HAL_PWR_DisableBkUpAccess(void)
00117 {
00118   CLEAR_BIT(PWR->CR, PWR_CR_DBP);
00119 }
00120
00121 /**
00122   * @}
00123   */
00124
00125 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
00126   *  @brief Low Power modes configuration functions
00127   *
00128 @verbatim
00129
00130  ===============================================================================
00131                  ##### Peripheral Control functions #####
00132  ===============================================================================
00133
00134     *** WakeUp pin configuration ***
00135     ================================
00136     [..]
00137       (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
00138           forced in input pull down configuration and is active on rising edges.
00139       (+) There are up to three WakeUp pins:
00140           (++)WakeUp Pin 1 on PA.00.
00141           (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only).
00142           (++)WakeUp Pin 3 on PE.06.
00143
00144     *** Main and Backup Regulators configuration ***
00145     ================================================
00146     [..]
00147       (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
00148           the backup SRAM is powered from VDD which replaces the VBAT power supply to
00149           save battery life.
00150
00151       (+) The backup SRAM is not mass erased by a tamper event. It is read
00152           protected to prevent confidential data, such as cryptographic private
00153           key, from being accessed. The backup SRAM can be erased only through
00154           the Flash interface when a protection level change from level 1 to
00155           level 0 is requested.
00156       -@- Refer to the description of Read protection (RDP) in the Flash
00157           programming manual.
00158
00159         Refer to the datasheets for more details.
00160
00161     *** Low Power modes configuration ***
00162     =====================================
00163     [..]
00164       The devices feature 3 low-power modes:
00165       (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
00166       (+) Stop mode: all clocks are stopped, regulator running, regulator
00167           in low power mode
00168       (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices).
00169
00170    *** Sleep mode ***
00171    ==================
00172     [..]
00173       (+) Entry:
00174           The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
00175               functions with
00176           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
00177           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
00178
00179       (+) Exit:
00180         (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
00181               controller (NVIC) can wake up the device from Sleep mode.
00182
00183    *** Stop mode ***
00184    =================
00185     [..]
00186       In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
00187       and the HSE RC oscillators are disabled. Internal SRAM and register contents
00188       are preserved.
00189       The voltage regulator can be configured either in normal or low-power mode to minimize the consumption.
00190
00191       (+) Entry:
00192           The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI )
00193              function with:
00194           (++) Main regulator ON or
00195           (++) Low Power regulator ON.
00196           (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or
00197           (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
00198       (+) Exit:
00199           (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
00200           (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
00201                when programmed in wakeup mode (the peripheral must be
00202                programmed in wakeup mode and the corresponding interrupt vector
00203                must be enabled in the NVIC).
00204
00205    *** Standby mode ***
00206    ====================
00207      [..]
00208       The Standby mode allows to achieve the lowest power consumption. It is based
00209       on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
00210       The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
00211       the HSE oscillator are also switched off. SRAM and register contents are lost
00212       except for the RTC registers, RTC backup registers, backup SRAM and Standby
00213       circuitry.
00214       The voltage regulator is OFF.
00215
00216       (+) Entry:
00217           (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
00218       (+) Exit:
00219           (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
00220                tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
00221
00222    *** Auto-wakeup (AWU) from low-power mode ***
00223    =============================================
00224     [..]
00225       The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
00226       Wakeup event, a tamper event, a time-stamp event, or a comparator event,
00227       without depending on an external interrupt (Auto-wakeup mode).
00228
00229     (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
00230
00231       (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
00232             configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
00233
00234       (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
00235            is necessary to configure the RTC to detect the tamper or time stamp event using the
00236            HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
00237
00238       (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
00239            configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function.
00240
00241     (+) Comparator auto-wakeup (AWU) from the Stop mode
00242
00243       (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
00244            (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2U)
00245                  to be sensitive to to the selected edges (falling, rising or falling
00246                  and rising) (Interrupt or Event modes) using the EXTI_Init() function.
00247            (+++) Configure the comparator to generate the event.
00248 @endverbatim
00249   * @{
00250   */
00251
00252 /**
00253   * @brief Enables the WakeUp PINx functionality.
00254   * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
00255   *         This parameter can be value of :
00256   *           @ref PWR_WakeUp_Pins
00257   * @retval None
00258   */
00259 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
00260 {
00261   /* Check the parameters */
00262   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
00263   /* Enable the EWUPx pin */
00264   SET_BIT(PWR->CSR, WakeUpPinx);
00265 }
00266
00267 /**
00268   * @brief Disables the WakeUp PINx functionality.
00269   * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
00270   *         This parameter can be values of :
00271   *           @ref PWR_WakeUp_Pins
00272   * @retval None
00273   */
00274 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
00275 {
00276   /* Check the parameters */
00277   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
00278   /* Disable the EWUPx pin */
00279   CLEAR_BIT(PWR->CSR, WakeUpPinx);
00280 }
00281
00282 /**
00283   * @brief Enters Sleep mode.
00284   * @note  In Sleep mode, all I/O pins keep the same state as in Run mode.
00285   * @param Regulator Specifies the regulator state in SLEEP mode.
00286   *          This parameter can be one of the following values:
00287   *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
00288   *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
00289   * @note This parameter has no effect in F3 family and is just maintained to
00290   *       offer full portability of other STM32 families softwares.
00291   * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
00292   *           When WFI entry is used, tick interrupt have to be disabled if not desired as
00293   *           the interrupt wake up source.
00294   *           This parameter can be one of the following values:
00295   *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
00296   *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
00297   * @retval None
00298   */
00299 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
00300 {
00301   /* Check the parameters */
00302   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
00303
00304   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00305   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
00306
00307   /* Select SLEEP mode entry -------------------------------------------------*/
00308   if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
00309   {
00310     /* Request Wait For Interrupt */
00311     __WFI();
00312   }
00313   else
00314   {
00315     /* Request Wait For Event */
00316     __SEV();
00317     __WFE();
00318     __WFE();
00319   }
00320 }
00321
00322 /**
00323   * @brief Enters STOP mode.
00324   * @note  In Stop mode, all I/O pins keep the same state as in Run mode.
00325   * @note  When exiting Stop mode by issuing an interrupt or a wakeup event,
00326   *         the HSI RC oscillator is selected as system clock.
00327   * @note  When the voltage regulator operates in low power mode, an additional
00328   *         startup delay is incurred when waking up from Stop mode.
00329   *         By keeping the internal regulator ON during Stop mode, the consumption
00330   *         is higher although the startup time is reduced.
00331   * @param Regulator Specifies the regulator state in STOP mode.
00332   *          This parameter can be one of the following values:
00333   *            @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
00334   *            @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
00335   * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
00336   *          This parameter can be one of the following values:
00337   *            @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
00338   *            @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
00339   * @retval None
00340   */
00341 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
00342 {
00343   uint32_t tmpreg = 0U;
00344
00345   /* Check the parameters */
00346   assert_param(IS_PWR_REGULATOR(Regulator));
00347   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
00348
00349   /* Select the regulator state in STOP mode ---------------------------------*/
00350   tmpreg = PWR->CR;
00351
00352   /* Clear PDDS and LPDS bits */
00353   tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
00354
00355   /* Set LPDS bit according to Regulator value */
00356   tmpreg |= Regulator;
00357
00358   /* Store the new value */
00359   PWR->CR = tmpreg;
00360
00361   /* Set SLEEPDEEP bit of Cortex System Control Register */
00362   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
00363
00364   /* Select STOP mode entry --------------------------------------------------*/
00365   if(STOPEntry == PWR_STOPENTRY_WFI)
00366   {
00367     /* Request Wait For Interrupt */
00368     __WFI();
00369   }
00370   else
00371   {
00372     /* Request Wait For Event */
00373     __SEV();
00374     __WFE();
00375     __WFE();
00376   }
00377
00378   /* Reset SLEEPDEEP bit of Cortex System Control Register */
00379   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
00380 }
00381
00382 /**
00383   * @brief Enters STANDBY mode.
00384   * @note  In Standby mode, all I/O pins are high impedance except for:
00385   *          - Reset pad (still available),
00386   *          - RTC alternate function pins if configured for tamper, time-stamp, RTC
00387   *            Alarm out, or RTC clock calibration out,
00388   *          - WKUP pins if enabled.
00389   * @retval None
00390   */
00391 void HAL_PWR_EnterSTANDBYMode(void)
00392 {
00393   /* Select STANDBY mode */
00394   PWR->CR |= PWR_CR_PDDS;
00395
00396   /* Set SLEEPDEEP bit of Cortex System Control Register */
00397   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
00398
00399   /* This option is used to ensure that store operations are completed */
00400 #if defined ( __CC_ARM)
00401   __force_stores();
00402 #endif
00403   /* Request Wait For Interrupt */
00404   __WFI();
00405 }
00406
00407 /**
00408   * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
00409   * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00410   *       re-enters SLEEP mode when an interruption handling is over.
00411   *       Setting this bit is useful when the processor is expected to run only on
00412   *       interruptions handling.
00413   * @retval None
00414   */
00415 void HAL_PWR_EnableSleepOnExit(void)
00416 {
00417   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00418   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00419 }
00420
00421
00422 /**
00423   * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
00424   * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00425   *       re-enters SLEEP mode when an interruption handling is over.
00426   * @retval None
00427   */
00428 void HAL_PWR_DisableSleepOnExit(void)
00429 {
00430   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00431   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00432 }
00433
00434
00435
00436 /**
00437   * @brief Enables CORTEX M4 SEVONPEND bit.
00438   * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
00439   *       WFE to wake up when an interrupt moves from inactive to pended.
00440   * @retval None
00441   */
00442 void HAL_PWR_EnableSEVOnPend(void)
00443 {
00444   /* Set SEVONPEND bit of Cortex System Control Register */
00445   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00446 }
00447
00448
00449 /**
00450   * @brief Disables CORTEX M4 SEVONPEND bit.
00451   * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
00452   *       WFE to wake up when an interrupt moves from inactive to pended.
00453   * @retval None
00454   */
00455 void HAL_PWR_DisableSEVOnPend(void)
00456 {
00457   /* Clear SEVONPEND bit of Cortex System Control Register */
00458   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00459 }
00460 /**
00461   * @}
00462   */
00463
00464 /**
00465   * @}
00466   */
00467
00468 #endif /* HAL_PWR_MODULE_ENABLED */
00469 /**
00470   * @}
00471   */
00472
00473 /**
00474   * @}
00475   */
00476
00477 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pwr.h Source File

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stm32f3xx_hal_pwr.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_pwr.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PWR HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_PWR_H
00038 #define __STM32F3xx_HAL_PWR_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup PWR PWR
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /* Exported constants --------------------------------------------------------*/
00057 /** @defgroup PWR_Exported_Constants PWR Exported Constants
00058   * @{
00059   */
00060
00061 /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
00062   * @{
00063   */
00064
00065 #define PWR_WAKEUP_PIN1                 ((uint32_t)PWR_CSR_EWUP1)   /*!< Wakeup pin 1U */
00066 #define PWR_WAKEUP_PIN2                 ((uint32_t)PWR_CSR_EWUP2)   /*!< Wakeup pin 2U */
00067 #define PWR_WAKEUP_PIN3                 ((uint32_t)PWR_CSR_EWUP3)   /*!< Wakeup pin 3U */
00068 /**
00069   * @}
00070   */
00071
00072 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode
00073   * @{
00074   */
00075 #define PWR_MAINREGULATOR_ON         (0x00000000U) /*!< Voltage regulator on during STOP mode                */
00076 #define PWR_LOWPOWERREGULATOR_ON     PWR_CR_LPDS            /*!< Voltage regulator in low-power mode during STOP mode */
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
00082   * @{
00083   */
00084 #define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01U)   /*!< Wait For Interruption instruction to enter SLEEP mode */
00085 #define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02U)   /*!< Wait For Event instruction to enter SLEEP mode        */
00086 /**
00087   * @}
00088   */
00089
00090 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
00091   * @{
00092   */
00093 #define PWR_STOPENTRY_WFI               ((uint8_t)0x01U)   /*!< Wait For Interruption instruction to enter STOP mode */
00094 #define PWR_STOPENTRY_WFE               ((uint8_t)0x02U)   /*!< Wait For Event instruction to enter STOP mode        */
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup PWR_Flag PWR Flag
00100   * @{
00101   */
00102 #define PWR_FLAG_WU                     PWR_CSR_WUF             /*!< Wakeup event from wakeup pin or RTC alarm */
00103 #define PWR_FLAG_SB                     PWR_CSR_SBF             /*!< Standby flag                              */
00104 #define PWR_FLAG_PVDO                   PWR_CSR_PVDO            /*!< Power Voltage Detector output flag        */
00105 #define PWR_FLAG_VREFINTRDY             PWR_CSR_VREFINTRDYF     /*!< VREFINT reference voltage ready           */
00106 /**
00107   * @}
00108   */
00109
00110 /**
00111   * @}
00112   */
00113
00114 /* Exported macro ------------------------------------------------------------*/
00115 /** @defgroup PWR_Exported_Macro PWR Exported Macro
00116   * @{
00117   */
00118
00119 /** @brief  Check PWR flag is set or not.
00120   * @param  __FLAG__ specifies the flag to check.
00121   *           This parameter can be one of the following values:
00122   *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
00123   *                  was received from the WKUP pin or from the RTC alarm (Alarm A
00124   *                  or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
00125   *                  An additional wakeup event is detected if the WKUP pin is enabled
00126   *                  (by setting the EWUP bit) when the WKUP pin level is already high.
00127   *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
00128   *                  resumed from StandBy mode.
00129   *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
00130   *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
00131   *                  For this reason, this bit is equal to 0 after Standby or reset
00132   *                  until the PVDE bit is set.
00133   *            @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference
00134   *                  voltage VREFINT is ready.
00135   * @retval The new state of __FLAG__ (TRUE or FALSE).
00136   */
00137 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
00138
00139 /** @brief  Clear the PWR's pending flags.
00140   * @param  __FLAG__ specifies the flag to clear.
00141   *          This parameter can be one of the following values:
00142   *            @arg PWR_FLAG_WU: Wake Up flag
00143   *            @arg PWR_FLAG_SB: StandBy flag
00144   */
00145 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |=  (__FLAG__) << 2U)
00146
00147 /**
00148   * @}
00149   */
00150
00151 /* Private macros --------------------------------------------------------*/
00152 /** @addtogroup  PWR_Private_Macros   PWR Private Macros
00153   * @{
00154   */
00155
00156 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
00157                                 ((PIN) == PWR_WAKEUP_PIN2) || \
00158                                 ((PIN) == PWR_WAKEUP_PIN3))
00159
00160 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
00161                                      ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
00162
00163 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
00164
00165 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
00166
00167 /**
00168   * @}
00169   */
00170
00171 /* Include PWR HAL Extended module */
00172 #include "stm32f3xx_hal_pwr_ex.h"
00173
00174 /* Exported functions --------------------------------------------------------*/
00175
00176 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
00177   * @{
00178   */
00179
00180 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
00181   * @{
00182   */
00183
00184 /* Initialization and de-initialization functions *****************************/
00185 void HAL_PWR_DeInit(void);
00186
00187 /**
00188   * @}
00189   */
00190
00191 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
00192   * @{
00193   */
00194
00195 /* Peripheral Control functions  **********************************************/
00196 void HAL_PWR_EnableBkUpAccess(void);
00197 void HAL_PWR_DisableBkUpAccess(void);
00198
00199 /* WakeUp pins configuration functions ****************************************/
00200 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
00201 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
00202
00203 /* Low Power modes configuration functions ************************************/
00204 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
00205 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
00206 void HAL_PWR_EnterSTANDBYMode(void);
00207
00208 void HAL_PWR_EnableSleepOnExit(void);
00209 void HAL_PWR_DisableSleepOnExit(void);
00210 void HAL_PWR_EnableSEVOnPend(void);
00211 void HAL_PWR_DisableSEVOnPend(void);
00212 /**
00213   * @}
00214   */
00215
00216 /**
00217   * @}
00218   */
00219
00220 /**
00221   * @}
00222   */
00223
00224 /**
00225   * @}
00226   */
00227
00228 #ifdef __cplusplus
00229 }
00230 #endif
00231
00232
00233 #endif /* __STM32F3xx_HAL_PWR_H */
00234
00235 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pwr_ex.c Source File

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stm32f3xx_hal_pwr_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_pwr_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended PWR HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Power Controller (PWR) peripheral:
00008   *           + Extended Initialization and de-initialization functions
00009   *           + Extended Peripheral Control functions
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00015   *
00016   * Redistribution and use in source and binary forms, with or without modification,
00017   * are permitted provided that the following conditions are met:
00018   *   1. Redistributions of source code must retain the above copyright notice,
00019   *      this list of conditions and the following disclaimer.
00020   *   2. Redistributions in binary form must reproduce the above copyright notice,
00021   *      this list of conditions and the following disclaimer in the documentation
00022   *      and/or other materials provided with the distribution.
00023   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00024   *      may be used to endorse or promote products derived from this software
00025   *      without specific prior written permission.
00026   *
00027   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00028   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00029   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00030   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00031   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00032   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00033   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00034   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00035   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00036   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00037   *
00038   ******************************************************************************
00039   */
00040
00041 /* Includes ------------------------------------------------------------------*/
00042 #include "stm32f3xx_hal.h"
00043
00044 /** @addtogroup STM32F3xx_HAL_Driver
00045   * @{
00046   */
00047
00048 /** @defgroup PWREx PWREx
00049   * @brief    PWREx HAL module driver
00050   * @{
00051   */
00052
00053 #ifdef HAL_PWR_MODULE_ENABLED
00054
00055 /* Private typedef -----------------------------------------------------------*/
00056 /* Private define ------------------------------------------------------------*/
00057 /** @defgroup PWREx_Private_Constants PWR Extended Private Constants
00058   * @{
00059   */
00060 #define PVD_MODE_IT               (0x00010000U)
00061 #define PVD_MODE_EVT              (0x00020000U)
00062 #define PVD_RISING_EDGE           (0x00000001U)
00063 #define PVD_FALLING_EDGE          (0x00000002U)
00064 /**
00065   * @}
00066   */
00067
00068 /* Private macro -------------------------------------------------------------*/
00069 /* Private variables ---------------------------------------------------------*/
00070 /* Private function prototypes -----------------------------------------------*/
00071 /* Exported functions ---------------------------------------------------------*/
00072
00073 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
00074   * @{
00075   */
00076
00077 /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions
00078   *  @brief   Extended Peripheral Control functions
00079   *
00080 @verbatim
00081
00082  ===============================================================================
00083                  ##### Peripheral Extended control functions #####
00084  ===============================================================================
00085     *** PVD configuration (present on all other devices than STM32F3x8 devices) ***
00086     =========================
00087     [..]
00088       (+) The PVD is used to monitor the VDD power supply by comparing it to a
00089           threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
00090       (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
00091           than the PVD threshold. This event is internally connected to the EXTI
00092           line16 and can generate an interrupt if enabled. This is done through
00093           __HAL_PWR_PVD_EXTI_ENABLE_IT() macro
00094       (+) The PVD is stopped in Standby mode.
00095       -@- PVD is not available on STM32F3x8 Product Line
00096
00097
00098     *** Voltage regulator ***
00099     =========================
00100     [..]
00101       (+) The voltage regulator is always enabled after Reset. It works in three different
00102           modes.
00103           In Run mode, the regulator supplies full power to the 1.8V domain (core, memories
00104           and digital peripherals).
00105           In Stop mode, the regulator supplies low power to the 1.8V domain, preserving
00106           contents of registers and SRAM.
00107           In Stop mode, the regulator is powered off. The contents of the registers and SRAM
00108           are lost except for the Standby circuitry and the Backup Domain.
00109           Note: in the STM32F3x8xx devices, the voltage regulator is bypassed and the
00110           microcontroller must be powered from a nominal VDD = 1.8V +/-8U% voltage.
00111
00112
00113       (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
00114           than the PVD threshold. This event is internally connected to the EXTI
00115           line16 and can generate an interrupt if enabled. This is done through
00116           __HAL_PWR_PVD_EXTI_ENABLE_IT() macro
00117       (+) The PVD is stopped in Standby mode.
00118
00119
00120     *** SDADC power configuration ***
00121     ================================
00122     [..]
00123       (+) On STM32F373xC/STM32F378xx devices, there are up to
00124           3 SDADC instances that can be enabled/disabled.
00125
00126 @endverbatim
00127   * @{
00128   */
00129
00130 #if defined(STM32F302xE) || defined(STM32F303xE) || \
00131     defined(STM32F302xC) || defined(STM32F303xC) || \
00132     defined(STM32F303x8) || defined(STM32F334x8) || \
00133     defined(STM32F301x8) || defined(STM32F302x8) || \
00134     defined(STM32F373xC)
00135
00136 /**
00137   * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
00138   * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
00139   *        information for the PVD.
00140   * @note Refer to the electrical characteristics of your device datasheet for
00141   *         more details about the voltage threshold corresponding to each
00142   *         detection level.
00143   * @retval None
00144   */
00145 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
00146 {
00147   /* Check the parameters */
00148   assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
00149   assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
00150
00151   /* Set PLS[7:5] bits according to PVDLevel value */
00152   MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
00153
00154   /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00155   __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
00156   __HAL_PWR_PVD_EXTI_DISABLE_IT();
00157   __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
00158
00159   /* Configure interrupt mode */
00160   if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
00161   {
00162     __HAL_PWR_PVD_EXTI_ENABLE_IT();
00163   }
00164
00165   /* Configure event mode */
00166   if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
00167   {
00168     __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
00169   }
00170
00171   /* Configure the edge */
00172   if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
00173   {
00174     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
00175   }
00176
00177   if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
00178   {
00179     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
00180   }
00181 }
00182
00183 /**
00184   * @brief Enables the Power Voltage Detector(PVD).
00185   * @retval None
00186   */
00187 void HAL_PWR_EnablePVD(void)
00188 {
00189   SET_BIT(PWR->CR, PWR_CR_PVDE);
00190 }
00191
00192 /**
00193   * @brief Disables the Power Voltage Detector(PVD).
00194   * @retval None
00195   */
00196 void HAL_PWR_DisablePVD(void)
00197 {
00198   CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
00199 }
00200
00201 /**
00202   * @brief This function handles the PWR PVD interrupt request.
00203   * @note This API should be called under the PVD_IRQHandler().
00204   * @retval None
00205   */
00206 void HAL_PWR_PVD_IRQHandler(void)
00207 {
00208   /* Check PWR exti flag */
00209   if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
00210   {
00211     /* PWR PVD interrupt user callback */
00212     HAL_PWR_PVDCallback();
00213
00214     /* Clear PWR Exti pending bit */
00215     __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
00216   }
00217 }
00218
00219 /**
00220   * @brief PWR PVD interrupt callback
00221   * @retval None
00222   */
00223 __weak void HAL_PWR_PVDCallback(void)
00224 {
00225   /* NOTE : This function Should not be modified, when the callback is needed,
00226             the HAL_PWR_PVDCallback could be implemented in the user file
00227    */
00228 }
00229
00230 #endif /* STM32F302xE || STM32F303xE || */
00231        /* STM32F302xC || STM32F303xC || */
00232        /* STM32F303x8 || STM32F334x8 || */
00233        /* STM32F301x8 || STM32F302x8 || */
00234        /* STM32F373xC                   */
00235
00236 #if defined(STM32F373xC) || defined(STM32F378xx)
00237
00238 /**
00239   * @brief  Enables the SDADC peripheral functionaliy
00240   * @param  Analogx specifies the SDADC peripheral instance.
00241   *   This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3.
00242   * @retval None
00243   */
00244 void HAL_PWREx_EnableSDADC(uint32_t Analogx)
00245 {
00246   /* Check the parameters */
00247   assert_param(IS_PWR_SDADC_ANALOG(Analogx));
00248
00249   /* Enable PWR clock interface for SDADC use */
00250   __HAL_RCC_PWR_CLK_ENABLE();
00251
00252   PWR->CR |= Analogx;
00253 }
00254
00255 /**
00256   * @brief  Disables the SDADC peripheral functionaliy
00257   * @param  Analogx specifies the SDADC peripheral instance.
00258   *   This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3.
00259   * @retval None
00260   */
00261 void HAL_PWREx_DisableSDADC(uint32_t Analogx)
00262 {
00263   /* Check the parameters */
00264   assert_param(IS_PWR_SDADC_ANALOG(Analogx));
00265
00266   PWR->CR &= ~Analogx;
00267 }
00268
00269 #endif /* STM32F373xC || STM32F378xx */
00270
00271 /**
00272   * @}
00273   */
00274
00275 /**
00276   * @}
00277   */
00278
00279 #endif /* HAL_PWR_MODULE_ENABLED */
00280 /**
00281   * @}
00282   */
00283
00284 /**
00285   * @}
00286   */
00287
00288 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_pwr_ex.h Source File

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stm32f3xx_hal_pwr_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_pwr_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PWR HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_PWR_EX_H
00038 #define __STM32F3xx_HAL_PWR_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup PWREx
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056
00057 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types
00058  *  @{
00059  */
00060 #if defined(STM32F302xE) || defined(STM32F303xE) || \
00061     defined(STM32F302xC) || defined(STM32F303xC) || \
00062     defined(STM32F303x8) || defined(STM32F334x8) || \
00063     defined(STM32F301x8) || defined(STM32F302x8) || \
00064     defined(STM32F373xC)
00065 /**
00066   * @brief  PWR PVD configuration structure definition
00067   */
00068 typedef struct
00069 {
00070   uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level
00071                             This parameter can be a value of @ref PWREx_PVD_detection_level */
00072
00073   uint32_t Mode;       /*!< Mode: Specifies the operating mode for the selected pins.
00074                             This parameter can be a value of @ref PWREx_PVD_Mode */
00075 }PWR_PVDTypeDef;
00076 #endif /* STM32F302xE || STM32F303xE || */
00077        /* STM32F302xC || STM32F303xC || */
00078        /* STM32F303x8 || STM32F334x8 || */
00079        /* STM32F301x8 || STM32F302x8 || */
00080        /* STM32F373xC                   */
00081
00082 /**
00083   * @}
00084   */
00085
00086 /* Exported constants --------------------------------------------------------*/
00087 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
00088   * @{
00089   */
00090
00091 #if defined(STM32F302xE) || defined(STM32F303xE) || \
00092     defined(STM32F302xC) || defined(STM32F303xC) || \
00093     defined(STM32F303x8) || defined(STM32F334x8) || \
00094     defined(STM32F301x8) || defined(STM32F302x8) || \
00095     defined(STM32F373xC)
00096
00097 /** @defgroup PWREx_PVD_detection_level PWR Extended PVD detection level
00098   * @{
00099   */
00100 #define PWR_PVDLEVEL_0                  PWR_CR_PLS_LEV0    /*!< PVD threshold around 2.2 V */
00101 #define PWR_PVDLEVEL_1                  PWR_CR_PLS_LEV1    /*!< PVD threshold around 2.3 V */
00102 #define PWR_PVDLEVEL_2                  PWR_CR_PLS_LEV2    /*!< PVD threshold around 2.4 V */
00103 #define PWR_PVDLEVEL_3                  PWR_CR_PLS_LEV3    /*!< PVD threshold around 2.5 V */
00104 #define PWR_PVDLEVEL_4                  PWR_CR_PLS_LEV4    /*!< PVD threshold around 2.6 V */
00105 #define PWR_PVDLEVEL_5                  PWR_CR_PLS_LEV5    /*!< PVD threshold around 2.7 V */
00106 #define PWR_PVDLEVEL_6                  PWR_CR_PLS_LEV6    /*!< PVD threshold around 2.8 V */
00107 #define PWR_PVDLEVEL_7                  PWR_CR_PLS_LEV7    /*!< PVD threshold around 2.9 V */
00108 /**
00109   * @}
00110   */
00111
00112 /** @defgroup PWREx_PVD_Mode PWR Extended PVD Mode
00113   * @{
00114   */
00115 #define PWR_PVD_MODE_NORMAL                 (0x00000000U)   /*!< Basic mode is used */
00116 #define PWR_PVD_MODE_IT_RISING              (0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection */
00117 #define PWR_PVD_MODE_IT_FALLING             (0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection */
00118 #define PWR_PVD_MODE_IT_RISING_FALLING      (0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00119 #define PWR_PVD_MODE_EVENT_RISING           (0x00020001U)   /*!< Event Mode with Rising edge trigger detection */
00120 #define PWR_PVD_MODE_EVENT_FALLING          (0x00020002U)   /*!< Event Mode with Falling edge trigger detection */
00121 #define PWR_PVD_MODE_EVENT_RISING_FALLING   (0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection */
00122 /**
00123   * @}
00124   */
00125
00126 #define PWR_EXTI_LINE_PVD  EXTI_IMR_MR16  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
00127
00128 #endif /* STM32F302xE || STM32F303xE || */
00129        /* STM32F302xC || STM32F303xC || */
00130        /* STM32F303x8 || STM32F334x8 || */
00131        /* STM32F301x8 || STM32F302x8 || */
00132        /* STM32F373xC                   */
00133
00134 #if defined(STM32F373xC) || defined(STM32F378xx)
00135 /** @defgroup PWREx_SDADC_ANALOGx PWR Extended SDADC ANALOGx
00136   * @{
00137   */
00138 #define PWR_SDADC_ANALOG1              ((uint32_t)PWR_CR_ENSD1)   /*!< Enable SDADC1 */
00139 #define PWR_SDADC_ANALOG2              ((uint32_t)PWR_CR_ENSD2)   /*!< Enable SDADC2 */
00140 #define PWR_SDADC_ANALOG3              ((uint32_t)PWR_CR_ENSD3)   /*!< Enable SDADC3 */
00141 /**
00142   * @}
00143   */
00144 #endif /* STM32F373xC || STM32F378xx */
00145
00146 /**
00147   * @}
00148   */
00149
00150 /* Exported macro ------------------------------------------------------------*/
00151 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
00152   * @{
00153   */
00154
00155 #if defined(STM32F302xE) || defined(STM32F303xE) || \
00156     defined(STM32F302xC) || defined(STM32F303xC) || \
00157     defined(STM32F303x8) || defined(STM32F334x8) || \
00158     defined(STM32F301x8) || defined(STM32F302x8) || \
00159     defined(STM32F373xC)
00160
00161 /**
00162   * @brief Enable interrupt on PVD Exti Line 16.
00163   * @retval None.
00164   */
00165 #define __HAL_PWR_PVD_EXTI_ENABLE_IT()      (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
00166
00167 /**
00168   * @brief Disable interrupt on PVD Exti Line 16.
00169   * @retval None.
00170   */
00171 #define __HAL_PWR_PVD_EXTI_DISABLE_IT()     (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
00172
00173 /**
00174   * @brief Generate a Software interrupt on selected EXTI line.
00175   * @retval None.
00176   */
00177 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT()  (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
00178
00179 /**
00180   * @brief Enable event on PVD Exti Line 16.
00181   * @retval None.
00182   */
00183 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
00184
00185 /**
00186   * @brief Disable event on PVD Exti Line 16.
00187   * @retval None.
00188   */
00189 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
00190
00191 /**
00192   * @brief Disable the PVD Extended Interrupt Rising Trigger.
00193   * @retval None.
00194   */
00195 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
00196
00197 /**
00198   * @brief Disable the PVD Extended Interrupt Falling Trigger.
00199   * @retval None.
00200   */
00201 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
00202
00203 /**
00204   * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
00205   * @retval None
00206   */
00207 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
00208
00209 /**
00210   * @brief  PVD EXTI line configuration: set falling edge trigger.
00211   * @retval None.
00212   */
00213 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()  EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
00214
00215 /**
00216   * @brief  PVD EXTI line configuration: set rising edge trigger.
00217   * @retval None.
00218   */
00219 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
00220
00221 /**
00222   * @brief  Enable the PVD Extended Interrupt Rising & Falling Trigger.
00223   * @retval None
00224   */
00225 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
00226
00227 /**
00228   * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
00229   * @retval EXTI PVD Line Status.
00230   */
00231 #define __HAL_PWR_PVD_EXTI_GET_FLAG()       (EXTI->PR & (PWR_EXTI_LINE_PVD))
00232
00233 /**
00234   * @brief Clear the PVD EXTI flag.
00235   * @retval None.
00236   */
00237 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()     (EXTI->PR = (PWR_EXTI_LINE_PVD))
00238
00239 #endif /* STM32F302xE || STM32F303xE || */
00240        /* STM32F302xC || STM32F303xC || */
00241        /* STM32F303x8 || STM32F334x8 || */
00242        /* STM32F301x8 || STM32F302x8 || */
00243        /* STM32F373xC                   */
00244
00245 /**
00246   * @}
00247   */
00248
00249 /* Private macros --------------------------------------------------------*/
00250 /** @addtogroup  PWREx_Private_Macros   PWR Extended Private Macros
00251   * @{
00252   */
00253
00254 #if defined(STM32F302xE) || defined(STM32F303xE) || \
00255     defined(STM32F302xC) || defined(STM32F303xC) || \
00256     defined(STM32F303x8) || defined(STM32F334x8) || \
00257     defined(STM32F301x8) || defined(STM32F302x8) || \
00258     defined(STM32F373xC)
00259 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
00260                                  ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
00261                                  ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
00262                                  ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
00263
00264 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
00265                               ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
00266                               ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
00267                               ((MODE) == PWR_PVD_MODE_NORMAL))
00268 #endif /* STM32F302xE || STM32F303xE || */
00269        /* STM32F302xC || STM32F303xC || */
00270        /* STM32F303x8 || STM32F334x8 || */
00271        /* STM32F301x8 || STM32F302x8 || */
00272        /* STM32F373xC                   */
00273
00274 #if defined(STM32F373xC) || defined(STM32F378xx)
00275 #define IS_PWR_SDADC_ANALOG(SDADC) (((SDADC) == PWR_SDADC_ANALOG1) || \
00276                                     ((SDADC) == PWR_SDADC_ANALOG2) || \
00277                                     ((SDADC) == PWR_SDADC_ANALOG3))
00278 #endif /* STM32F373xC || STM32F378xx */
00279
00280
00281 /**
00282   * @}
00283   */
00284
00285 /* Exported functions --------------------------------------------------------*/
00286
00287 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
00288  *  @{
00289  */
00290
00291 /** @addtogroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions
00292   * @{
00293   */
00294 /* Peripheral Extended control functions **************************************/
00295 #if defined(STM32F302xE) || defined(STM32F303xE) || \
00296     defined(STM32F302xC) || defined(STM32F303xC) || \
00297     defined(STM32F303x8) || defined(STM32F334x8) || \
00298     defined(STM32F301x8) || defined(STM32F302x8) || \
00299     defined(STM32F373xC)
00300 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
00301 void HAL_PWR_EnablePVD(void);
00302 void HAL_PWR_DisablePVD(void);
00303 void HAL_PWR_PVD_IRQHandler(void);
00304 void HAL_PWR_PVDCallback(void);
00305 #endif /* STM32F302xE || STM32F303xE || */
00306        /* STM32F302xC || STM32F303xC || */
00307        /* STM32F303x8 || STM32F334x8 || */
00308        /* STM32F301x8 || STM32F302x8 || */
00309        /* STM32F373xC                   */
00310
00311 #if defined(STM32F373xC) || defined(STM32F378xx)
00312 void HAL_PWREx_EnableSDADC(uint32_t Analogx);
00313 void HAL_PWREx_DisableSDADC(uint32_t Analogx);
00314 #endif /* STM32F373xC || STM32F378xx */
00315
00316 /**
00317   * @}
00318   */
00319
00320 /**
00321   * @}
00322   */
00323
00324 /**
00325   * @}
00326   */
00327
00328 /**
00329   * @}
00330   */
00331
00332 #ifdef __cplusplus
00333 }
00334 #endif
00335
00336 #endif /* __STM32F3xx_HAL_PWR_EX_H */
00337
00338 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_rcc.c Source File

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stm32f3xx_hal_rcc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_rcc.c
00004   * @author  MCD Application Team
00005   * @brief   RCC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Reset and Clock Control (RCC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                       ##### RCC specific features #####
00014   ==============================================================================
00015     [..]
00016       After reset the device is running from Internal High Speed oscillator
00017       (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
00018       and all peripherals are off except internal SRAM, Flash and JTAG.
00019       (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
00020           all peripherals mapped on these buses are running at HSI speed.
00021       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
00022       (+) All GPIOs are in input floating state, except the JTAG pins which
00023           are assigned to be used for debug purpose.
00024     [..] Once the device started from reset, the user application has to:
00025       (+) Configure the clock source to be used to drive the System clock
00026           (if the application needs higher frequency/performance)
00027       (+) Configure the System clock frequency and Flash settings
00028       (+) Configure the AHB and APB buses prescalers
00029       (+) Enable the clock for the peripheral(s) to be used
00030       (+) Configure the clock source(s) for peripherals whose clocks are not
00031           derived from the System clock (RTC, ADC, I2C, I2S, TIM, USB FS)
00032
00033                       ##### RCC Limitations #####
00034   ==============================================================================
00035     [..]
00036       A delay between an RCC peripheral clock enable and the effective peripheral
00037       enabling should be taken into account in order to manage the peripheral read/write
00038       from/to registers.
00039       (+) This delay depends on the peripheral mapping.
00040         (++) AHB & APB peripherals, 1 dummy read is necessary
00041
00042     [..]
00043       Workarounds:
00044       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
00045           inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
00046
00047   @endverbatim
00048   ******************************************************************************
00049   * @attention
00050   *
00051   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00052   *
00053   * Redistribution and use in source and binary forms, with or without modification,
00054   * are permitted provided that the following conditions are met:
00055   *   1. Redistributions of source code must retain the above copyright notice,
00056   *      this list of conditions and the following disclaimer.
00057   *   2. Redistributions in binary form must reproduce the above copyright notice,
00058   *      this list of conditions and the following disclaimer in the documentation
00059   *      and/or other materials provided with the distribution.
00060   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00061   *      may be used to endorse or promote products derived from this software
00062   *      without specific prior written permission.
00063   *
00064   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00065   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00066   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00067   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00068   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00069   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00070   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00071   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00072   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00073   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00074   *
00075   ******************************************************************************
00076 */
00077
00078 /* Includes ------------------------------------------------------------------*/
00079 #include "stm32f3xx_hal.h"
00080
00081 /** @addtogroup STM32F3xx_HAL_Driver
00082   * @{
00083   */
00084
00085 /** @defgroup RCC RCC
00086 * @brief RCC HAL module driver
00087   * @{
00088   */
00089
00090 #ifdef HAL_RCC_MODULE_ENABLED
00091
00092 /* Private typedef -----------------------------------------------------------*/
00093 /* Private define ------------------------------------------------------------*/
00094 /** @defgroup RCC_Private_Constants RCC Private Constants
00095  * @{
00096  */
00097 /* Bits position in  in the CFGR register */
00098 #define RCC_CFGR_HPRE_BITNUMBER           POSITION_VAL(RCC_CFGR_HPRE)
00099 #define RCC_CFGR_PPRE1_BITNUMBER          POSITION_VAL(RCC_CFGR_PPRE1)
00100 #define RCC_CFGR_PPRE2_BITNUMBER          POSITION_VAL(RCC_CFGR_PPRE2)
00101 /**
00102   * @}
00103   */
00104 /* Private macro -------------------------------------------------------------*/
00105 /** @defgroup RCC_Private_Macros RCC Private Macros
00106   * @{
00107   */
00108
00109 #define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
00110 #define MCO1_GPIO_PORT        GPIOA
00111 #define MCO1_PIN              GPIO_PIN_8
00112
00113 /**
00114   * @}
00115   */
00116
00117 /* Private variables ---------------------------------------------------------*/
00118 /** @defgroup RCC_Private_Variables RCC Private Variables
00119   * @{
00120   */
00121 const uint8_t aPLLMULFactorTable[16] = { 2U,  3U,  4U,  5U,  6U,  7U,  8U,  9U,
00122                                        10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
00123 const uint8_t aPredivFactorTable[16] = { 1U, 2U,  3U,  4U,  5U,  6U,  7U,  8U,
00124                                          9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
00125 /**
00126   * @}
00127   */
00128
00129 /* Private function prototypes -----------------------------------------------*/
00130 /* Exported functions ---------------------------------------------------------*/
00131
00132 /** @defgroup RCC_Exported_Functions RCC Exported Functions
00133   * @{
00134   */
00135
00136 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
00137   *  @brief    Initialization and Configuration functions
00138   *
00139   @verbatim
00140   ===============================================================================
00141            ##### Initialization and de-initialization functions #####
00142   ===============================================================================
00143     [..]
00144       This section provides functions allowing to configure the internal/external oscillators
00145       (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
00146       and APB2).
00147
00148     [..] Internal/external clock and PLL configuration
00149       (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
00150           the PLL as System clock source.
00151           The HSI clock can be used also to clock the USART and I2C peripherals.
00152
00153       (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
00154           clock source.
00155
00156       (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
00157           through the PLL as System clock source. Can be used also as RTC clock source.
00158
00159       (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
00160
00161       (#) PLL (clocked by HSI or HSE), featuring different output clocks:
00162         (++) The first output is used to generate the high speed system clock (up to 72 MHz)
00163         (++) The second output is used to generate the clock for the USB FS (48 MHz)
00164         (++) The third output may be used to generate the clock for the ADC peripherals (up to 72 MHz)
00165         (++) The fourth output may be used to generate the clock for the TIM peripherals (144 MHz)
00166
00167       (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
00168           and if a HSE clock failure occurs(HSE used directly or through PLL as System
00169           clock source), the System clocks automatically switched to HSI and an interrupt
00170           is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
00171           (Non-Maskable Interrupt) exception vector.
00172
00173       (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
00174           clock (divided by 2) output on pin (such as PA8 pin).
00175
00176     [..] System, AHB and APB buses clocks configuration
00177       (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
00178           HSE and PLL.
00179           The AHB clock (HCLK) is derived from System clock through configurable
00180           prescaler and used to clock the CPU, memory and peripherals mapped
00181           on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
00182           from AHB clock through configurable prescalers and used to clock
00183           the peripherals mapped on these buses. You can use
00184           "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
00185
00186       (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
00187         (++) The FLASH program/erase clock  which is always HSI 8MHz clock.
00188         (++) The USB 48 MHz clock which is derived from the PLL VCO clock.
00189         (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
00190         (++) The I2C clock which can be derived as well from HSI 8MHz clock.
00191         (++) The ADC clock which is derived from PLL output.
00192         (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
00193              (HSE divided by a programmable prescaler). The System clock (SYSCLK)
00194              frequency must be higher or equal to the RTC clock frequency.
00195         (++) IWDG clock which is always the LSI clock.
00196
00197          (#) For the STM32F3xx devices, the maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz,
00198              Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
00199
00200          (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
00201              prefetch is disabled.
00202   @endverbatim
00203   * @{
00204   */
00205
00206 /*
00207   Additional consideration on the SYSCLK based on Latency settings:
00208         +-----------------------------------------------+
00209         | Latency       | SYSCLK clock frequency (MHz)  |
00210         |---------------|-------------------------------|
00211         |0WS(1CPU cycle)|       0 < SYSCLK <= 24        |
00212         |---------------|-------------------------------|
00213         |1WS(2CPU cycle)|      24 < SYSCLK <= 48        |
00214         |---------------|-------------------------------|
00215         |2WS(3CPU cycle)|      48 < SYSCLK <= 72        |
00216         +-----------------------------------------------+
00217   */
00218
00219 /**
00220   * @brief  Resets the RCC clock configuration to the default reset state.
00221   * @note   The default reset state of the clock configuration is given below:
00222   *            - HSI ON and used as system clock source
00223   *            - HSE and PLL OFF
00224   *            - AHB, APB1 and APB2 prescaler set to 1.
00225   *            - CSS and MCO1 OFF
00226   *            - All interrupts disabled
00227   * @note   This function does not modify the configuration of the
00228   *            - Peripheral clocks
00229   *            - LSI, LSE and RTC clocks
00230   * @retval None
00231   */
00232 void HAL_RCC_DeInit(void)
00233 {
00234   /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/
00235   SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
00236
00237   /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0] and MCOSEL[2:0] bits */
00238   CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCO);
00239
00240   /* Reset HSEON, CSSON, PLLON bits */
00241   CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON);
00242
00243   /* Reset HSEBYP bit */
00244   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
00245
00246   /* Reset CFGR register */
00247   CLEAR_REG(RCC->CFGR);
00248
00249   /* Reset CFGR2 register */
00250   CLEAR_REG(RCC->CFGR2);
00251
00252   /* Reset CFGR3 register */
00253   CLEAR_REG(RCC->CFGR3);
00254
00255   /* Disable all interrupts */
00256   CLEAR_REG(RCC->CIR);
00257
00258   /* Update the SystemCoreClock global variable */
00259   SystemCoreClock = HSI_VALUE;
00260 }
00261
00262 /**
00263   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
00264   *         RCC_OscInitTypeDef.
00265   * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
00266   *         contains the configuration information for the RCC Oscillators.
00267   * @note   The PLL is not disabled when used as system clock.
00268   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
00269   *         supported by this macro. User should request a transition to LSE Off
00270   *         first and then LSE On or LSE Bypass.
00271   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
00272   *         supported by this macro. User should request a transition to HSE Off
00273   *         first and then HSE On or HSE Bypass.
00274   * @retval HAL status
00275   */
00276 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
00277 {
00278    uint32_t tickstart = 0U;
00279
00280   /* Check the parameters */
00281   assert_param(RCC_OscInitStruct != NULL);
00282   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
00283
00284   /*------------------------------- HSE Configuration ------------------------*/
00285   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
00286   {
00287     /* Check the parameters */
00288     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
00289
00290     /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
00291     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
00292        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
00293     {
00294       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
00295       {
00296         return HAL_ERROR;
00297       }
00298     }
00299     else
00300     {
00301       /* Set the new HSE configuration ---------------------------------------*/
00302       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
00303
00304 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
00305       /* Configure the HSE predivision factor --------------------------------*/
00306       __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
00307 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
00308
00309        /* Check the HSE State */
00310       if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
00311       {
00312         /* Get Start Tick */
00313         tickstart = HAL_GetTick();
00314
00315         /* Wait till HSE is ready */
00316         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
00317         {
00318           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
00319           {
00320             return HAL_TIMEOUT;
00321           }
00322         }
00323       }
00324       else
00325       {
00326         /* Get Start Tick */
00327         tickstart = HAL_GetTick();
00328
00329         /* Wait till HSE is disabled */
00330         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
00331         {
00332            if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
00333           {
00334             return HAL_TIMEOUT;
00335           }
00336         }
00337       }
00338     }
00339   }
00340   /*----------------------------- HSI Configuration --------------------------*/
00341   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
00342   {
00343     /* Check the parameters */
00344     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
00345     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
00346
00347     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
00348     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
00349        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
00350     {
00351       /* When HSI is used as system clock it will not disabled */
00352       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
00353       {
00354         return HAL_ERROR;
00355       }
00356       /* Otherwise, just the calibration is allowed */
00357       else
00358       {
00359         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00360         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00361       }
00362     }
00363     else
00364     {
00365       /* Check the HSI State */
00366       if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
00367       {
00368        /* Enable the Internal High Speed oscillator (HSI). */
00369         __HAL_RCC_HSI_ENABLE();
00370
00371         /* Get Start Tick */
00372         tickstart = HAL_GetTick();
00373
00374         /* Wait till HSI is ready */
00375         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
00376         {
00377           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
00378           {
00379             return HAL_TIMEOUT;
00380           }
00381         }
00382
00383         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00384         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00385       }
00386       else
00387       {
00388         /* Disable the Internal High Speed oscillator (HSI). */
00389         __HAL_RCC_HSI_DISABLE();
00390
00391         /* Get Start Tick */
00392         tickstart = HAL_GetTick();
00393
00394         /* Wait till HSI is disabled */
00395         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
00396         {
00397           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
00398           {
00399             return HAL_TIMEOUT;
00400           }
00401         }
00402       }
00403     }
00404   }
00405   /*------------------------------ LSI Configuration -------------------------*/
00406   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
00407   {
00408     /* Check the parameters */
00409     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
00410
00411     /* Check the LSI State */
00412     if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
00413     {
00414       /* Enable the Internal Low Speed oscillator (LSI). */
00415       __HAL_RCC_LSI_ENABLE();
00416
00417       /* Get Start Tick */
00418       tickstart = HAL_GetTick();
00419
00420       /* Wait till LSI is ready */
00421       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
00422       {
00423         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
00424         {
00425           return HAL_TIMEOUT;
00426         }
00427       }
00428     }
00429     else
00430     {
00431       /* Disable the Internal Low Speed oscillator (LSI). */
00432       __HAL_RCC_LSI_DISABLE();
00433
00434       /* Get Start Tick */
00435       tickstart = HAL_GetTick();
00436
00437       /* Wait till LSI is disabled */
00438       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
00439       {
00440         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
00441         {
00442           return HAL_TIMEOUT;
00443         }
00444       }
00445     }
00446   }
00447   /*------------------------------ LSE Configuration -------------------------*/
00448   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
00449   {
00450     FlagStatus       pwrclkchanged = RESET;
00451
00452     /* Check the parameters */
00453     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
00454
00455     /* Update LSE configuration in Backup Domain control register    */
00456     /* Requires to enable write access to Backup Domain of necessary */
00457     if(__HAL_RCC_PWR_IS_CLK_DISABLED())
00458     {
00459       __HAL_RCC_PWR_CLK_ENABLE();
00460       pwrclkchanged = SET;
00461     }
00462
00463     if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
00464     {
00465       /* Enable write access to Backup domain */
00466       SET_BIT(PWR->CR, PWR_CR_DBP);
00467
00468       /* Wait for Backup domain Write protection disable */
00469       tickstart = HAL_GetTick();
00470
00471       while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
00472       {
00473         if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
00474         {
00475           return HAL_TIMEOUT;
00476         }
00477       }
00478     }
00479
00480     /* Set the new LSE configuration -----------------------------------------*/
00481     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
00482     /* Check the LSE State */
00483     if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
00484     {
00485       /* Get Start Tick */
00486       tickstart = HAL_GetTick();
00487
00488       /* Wait till LSE is ready */
00489       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
00490       {
00491         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
00492         {
00493           return HAL_TIMEOUT;
00494         }
00495       }
00496     }
00497     else
00498     {
00499       /* Get Start Tick */
00500       tickstart = HAL_GetTick();
00501
00502       /* Wait till LSE is disabled */
00503       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
00504       {
00505         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
00506         {
00507           return HAL_TIMEOUT;
00508         }
00509       }
00510     }
00511
00512     /* Require to disable power clock if necessary */
00513     if(pwrclkchanged == SET)
00514     {
00515       __HAL_RCC_PWR_CLK_DISABLE();
00516     }
00517   }
00518
00519   /*-------------------------------- PLL Configuration -----------------------*/
00520   /* Check the parameters */
00521   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
00522   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
00523   {
00524     /* Check if the PLL is used as system clock or not */
00525     if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
00526     {
00527       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
00528       {
00529         /* Check the parameters */
00530         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
00531         assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
00532 #if   defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
00533         assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
00534 #endif
00535
00536         /* Disable the main PLL. */
00537         __HAL_RCC_PLL_DISABLE();
00538
00539         /* Get Start Tick */
00540         tickstart = HAL_GetTick();
00541
00542         /* Wait till PLL is disabled */
00543         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
00544         {
00545           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00546           {
00547             return HAL_TIMEOUT;
00548           }
00549         }
00550
00551 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
00552         /* Configure the main PLL clock source, predivider and multiplication factor. */
00553         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
00554                              RCC_OscInitStruct->PLL.PREDIV,
00555                              RCC_OscInitStruct->PLL.PLLMUL);
00556 #else
00557       /* Configure the main PLL clock source and multiplication factor. */
00558       __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
00559                            RCC_OscInitStruct->PLL.PLLMUL);
00560 #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
00561         /* Enable the main PLL. */
00562         __HAL_RCC_PLL_ENABLE();
00563
00564         /* Get Start Tick */
00565         tickstart = HAL_GetTick();
00566
00567         /* Wait till PLL is ready */
00568         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
00569         {
00570           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00571           {
00572             return HAL_TIMEOUT;
00573           }
00574         }
00575       }
00576       else
00577       {
00578         /* Disable the main PLL. */
00579         __HAL_RCC_PLL_DISABLE();
00580
00581         /* Get Start Tick */
00582         tickstart = HAL_GetTick();
00583
00584         /* Wait till PLL is disabled */
00585         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
00586         {
00587           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00588           {
00589             return HAL_TIMEOUT;
00590           }
00591         }
00592       }
00593     }
00594     else
00595     {
00596       return HAL_ERROR;
00597     }
00598   }
00599
00600   return HAL_OK;
00601 }
00602
00603 /**
00604   * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
00605   *         parameters in the RCC_ClkInitStruct.
00606   * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
00607   *         contains the configuration information for the RCC peripheral.
00608   * @param  FLatency FLASH Latency
00609   *          The value of this parameter depend on device used within the same series
00610   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
00611   *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
00612   *
00613   * @note   The HSI is used (enabled by hardware) as system clock source after
00614   *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
00615   *         of failure of the HSE used directly or indirectly as system clock
00616   *         (if the Clock Security System CSS is enabled).
00617   *
00618   * @note   A switch from one clock source to another occurs only if the target
00619   *         clock source is ready (clock stable after start-up delay or PLL locked).
00620   *         If a clock source which is not yet ready is selected, the switch will
00621   *         occur when the clock source will be ready.
00622   *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
00623   *         currently used as system clock source.
00624   * @retval HAL status
00625   */
00626 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
00627 {
00628   uint32_t tickstart = 0U;
00629
00630   /* Check the parameters */
00631   assert_param(RCC_ClkInitStruct != NULL);
00632   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
00633   assert_param(IS_FLASH_LATENCY(FLatency));
00634
00635   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
00636   must be correctly programmed according to the frequency of the CPU clock
00637     (HCLK) of the device. */
00638
00639   /* Increasing the number of wait states because of higher CPU frequency */
00640   if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
00641   {
00642     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00643     __HAL_FLASH_SET_LATENCY(FLatency);
00644
00645     /* Check that the new number of wait states is taken into account to access the Flash
00646     memory by reading the FLASH_ACR register */
00647     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
00648     {
00649       return HAL_ERROR;
00650     }
00651   }
00652
00653   /*-------------------------- HCLK Configuration --------------------------*/
00654   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
00655   {
00656     assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
00657     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
00658   }
00659
00660   /*------------------------- SYSCLK Configuration ---------------------------*/
00661   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
00662   {
00663     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
00664
00665     /* HSE is selected as System Clock Source */
00666     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
00667     {
00668       /* Check the HSE ready flag */
00669       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
00670       {
00671         return HAL_ERROR;
00672       }
00673     }
00674     /* PLL is selected as System Clock Source */
00675     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
00676     {
00677       /* Check the PLL ready flag */
00678       if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
00679       {
00680         return HAL_ERROR;
00681       }
00682     }
00683     /* HSI is selected as System Clock Source */
00684     else
00685     {
00686       /* Check the HSI ready flag */
00687       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
00688       {
00689         return HAL_ERROR;
00690       }
00691     }
00692     __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
00693
00694     /* Get Start Tick */
00695     tickstart = HAL_GetTick();
00696
00697     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
00698     {
00699       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
00700       {
00701         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00702         {
00703           return HAL_TIMEOUT;
00704         }
00705       }
00706     }
00707     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
00708     {
00709       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
00710       {
00711         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00712         {
00713           return HAL_TIMEOUT;
00714         }
00715       }
00716     }
00717     else
00718     {
00719       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
00720       {
00721         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00722         {
00723           return HAL_TIMEOUT;
00724         }
00725       }
00726     }
00727   }
00728   /* Decreasing the number of wait states because of lower CPU frequency */
00729   if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
00730   {
00731     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00732     __HAL_FLASH_SET_LATENCY(FLatency);
00733
00734     /* Check that the new number of wait states is taken into account to access the Flash
00735     memory by reading the FLASH_ACR register */
00736     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
00737     {
00738       return HAL_ERROR;
00739     }
00740   }
00741
00742   /*-------------------------- PCLK1 Configuration ---------------------------*/
00743   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
00744   {
00745     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
00746     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
00747   }
00748
00749   /*-------------------------- PCLK2 Configuration ---------------------------*/
00750   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
00751   {
00752     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
00753     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
00754   }
00755
00756   /* Update the SystemCoreClock global variable */
00757   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
00758
00759   /* Configure the source of time base considering new system clocks settings*/
00760   HAL_InitTick (TICK_INT_PRIORITY);
00761
00762   return HAL_OK;
00763 }
00764
00765 /**
00766   * @}
00767   */
00768
00769 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
00770   *  @brief   RCC clocks control functions
00771   *
00772   @verbatim
00773   ===============================================================================
00774                   ##### Peripheral Control functions #####
00775   ===============================================================================
00776     [..]
00777     This subsection provides a set of functions allowing to control the RCC Clocks
00778     frequencies.
00779
00780   @endverbatim
00781   * @{
00782   */
00783
00784 #if defined(RCC_CFGR_MCOPRE)
00785 /**
00786   * @brief  Selects the clock source to output on MCO pin.
00787   * @note   MCO pin should be configured in alternate function mode.
00788   * @param  RCC_MCOx specifies the output direction for the clock source.
00789   *          This parameter can be one of the following values:
00790   *            @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
00791   * @param  RCC_MCOSource specifies the clock source to output.
00792   *          This parameter can be one of the following values:
00793   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK     No clock selected
00794   *            @arg @ref RCC_MCO1SOURCE_SYSCLK      System Clock selected as MCO clock
00795   *            @arg @ref RCC_MCO1SOURCE_HSI         HSI selected as MCO clock
00796   *            @arg @ref RCC_MCO1SOURCE_HSE         HSE selected as MCO clock
00797   *            @arg @ref RCC_MCO1SOURCE_LSI         LSI selected as MCO clock
00798   *            @arg @ref RCC_MCO1SOURCE_LSE         LSE selected as MCO clock
00799   *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
00800   *            @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
00801   * @param  RCC_MCODiv specifies the MCO DIV.
00802   *          This parameter can be one of the following values:
00803   *            @arg @ref RCC_MCODIV_1   no division applied to MCO clock
00804   *            @arg @ref RCC_MCODIV_2   division by 2 applied to MCO clock
00805   *            @arg @ref RCC_MCODIV_4   division by 4 applied to MCO clock
00806   *            @arg @ref RCC_MCODIV_8   division by 8 applied to MCO clock
00807   *            @arg @ref RCC_MCODIV_16  division by 16 applied to MCO clock
00808   *            @arg @ref RCC_MCODIV_32  division by 32 applied to MCO clock
00809   *            @arg @ref RCC_MCODIV_64  division by 64 applied to MCO clock
00810   *            @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock
00811   * @retval None
00812   */
00813 #else
00814 /**
00815   * @brief  Selects the clock source to output on MCO pin.
00816   * @note   MCO pin should be configured in alternate function mode.
00817   * @param  RCC_MCOx specifies the output direction for the clock source.
00818   *          This parameter can be one of the following values:
00819   *            @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
00820   * @param  RCC_MCOSource specifies the clock source to output.
00821   *          This parameter can be one of the following values:
00822   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK     No clock selected as MCO clock
00823   *            @arg @ref RCC_MCO1SOURCE_SYSCLK      System clock selected as MCO clock
00824   *            @arg @ref RCC_MCO1SOURCE_HSI         HSI selected as MCO clock
00825   *            @arg @ref RCC_MCO1SOURCE_HSE         HSE selected as MCO clock
00826   *            @arg @ref RCC_MCO1SOURCE_LSI         LSI selected as MCO clock
00827   *            @arg @ref RCC_MCO1SOURCE_LSE         LSE selected as MCO clock
00828   *            @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
00829   * @param  RCC_MCODiv specifies the MCO DIV.
00830   *          This parameter can be one of the following values:
00831   *            @arg @ref RCC_MCODIV_1 no division applied to MCO clock
00832   * @retval None
00833   */
00834 #endif
00835 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
00836 {
00837   GPIO_InitTypeDef gpio;
00838
00839   /* Check the parameters */
00840   assert_param(IS_RCC_MCO(RCC_MCOx));
00841   assert_param(IS_RCC_MCODIV(RCC_MCODiv));
00842   assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
00843
00844   /* Configure the MCO1 pin in alternate function mode */
00845   gpio.Mode      = GPIO_MODE_AF_PP;
00846   gpio.Speed     = GPIO_SPEED_FREQ_HIGH;
00847   gpio.Pull      = GPIO_NOPULL;
00848   gpio.Pin       = MCO1_PIN;
00849   gpio.Alternate = GPIO_AF0_MCO;
00850
00851   /* MCO1 Clock Enable */
00852   MCO1_CLK_ENABLE();
00853
00854   HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
00855
00856   /* Configure the MCO clock source */
00857   __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
00858 }
00859
00860 /**
00861   * @brief  Enables the Clock Security System.
00862   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
00863   *         is automatically disabled and an interrupt is generated to inform the
00864   *         software about the failure (Clock Security System Interrupt, CSSI),
00865   *         allowing the MCU to perform rescue operations. The CSSI is linked to
00866   *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
00867   * @retval None
00868   */
00869 void HAL_RCC_EnableCSS(void)
00870 {
00871   *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
00872 }
00873
00874 /**
00875   * @brief  Disables the Clock Security System.
00876   * @retval None
00877   */
00878 void HAL_RCC_DisableCSS(void)
00879 {
00880   *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
00881 }
00882
00883 /**
00884   * @brief  Returns the SYSCLK frequency
00885   * @note   The system frequency computed by this function is not the real
00886   *         frequency in the chip. It is calculated based on the predefined
00887   *         constant and the selected clock source:
00888   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
00889   * @note     If SYSCLK source is HSE, function returns a value based on HSE_VALUE
00890   *           divided by PREDIV factor(**)
00891   * @note     If SYSCLK source is PLL, function returns a value based on HSE_VALUE
00892   *           divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
00893   * @note     (*) HSI_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value
00894   *               8 MHz) but the real value may vary depending on the variations
00895   *               in voltage and temperature.
00896   * @note     (**) HSE_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value
00897   *                8 MHz), user has to ensure that HSE_VALUE is same as the real
00898   *                frequency of the crystal used. Otherwise, this function may
00899   *                have wrong result.
00900   *
00901   * @note   The result of this function could be not correct when using fractional
00902   *         value for HSE crystal.
00903   *
00904   * @note   This function can be used by the user application to compute the
00905   *         baud-rate for the communication peripherals or configure other parameters.
00906   *
00907   * @note   Each time SYSCLK changes, this function must be called to update the
00908   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
00909   *
00910   * @retval SYSCLK frequency
00911   */
00912 uint32_t HAL_RCC_GetSysClockFreq(void)
00913 {
00914   uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
00915   uint32_t sysclockfreq = 0U;
00916
00917   tmpreg = RCC->CFGR;
00918
00919   /* Get SYSCLK source -------------------------------------------------------*/
00920   switch (tmpreg & RCC_CFGR_SWS)
00921   {
00922     case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
00923     {
00924       sysclockfreq = HSE_VALUE;
00925       break;
00926     }
00927     case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
00928     {
00929       pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)];
00930       prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFGR2_PREDIV)];
00931 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
00932       if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI)
00933       {
00934         /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
00935         pllclk = (HSE_VALUE / prediv) * pllmul;
00936       }
00937       else
00938       {
00939         /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
00940         pllclk = (HSI_VALUE >> 1U) * pllmul;
00941       }
00942 #else
00943       if ((tmpreg & RCC_CFGR_PLLSRC_HSE_PREDIV) == RCC_CFGR_PLLSRC_HSE_PREDIV)
00944       {
00945         /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
00946         pllclk = (HSE_VALUE / prediv) * pllmul;
00947       }
00948       else
00949       {
00950         /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
00951         pllclk = (HSI_VALUE / prediv) * pllmul;
00952       }
00953 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
00954       sysclockfreq = pllclk;
00955       break;
00956     }
00957     case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
00958     default: /* HSI used as system clock */
00959     {
00960       sysclockfreq = HSI_VALUE;
00961       break;
00962     }
00963   }
00964   return sysclockfreq;
00965 }
00966
00967 /**
00968   * @brief  Returns the HCLK frequency
00969   * @note   Each time HCLK changes, this function must be called to update the
00970   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
00971   *
00972   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
00973   *         and updated within this function
00974   * @retval HCLK frequency
00975   */
00976 uint32_t HAL_RCC_GetHCLKFreq(void)
00977 {
00978   return SystemCoreClock;
00979 }
00980
00981 /**
00982   * @brief  Returns the PCLK1 frequency
00983   * @note   Each time PCLK1 changes, this function must be called to update the
00984   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
00985   * @retval PCLK1 frequency
00986   */
00987 uint32_t HAL_RCC_GetPCLK1Freq(void)
00988 {
00989   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
00990   return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]);
00991 }
00992
00993 /**
00994   * @brief  Returns the PCLK2 frequency
00995   * @note   Each time PCLK2 changes, this function must be called to update the
00996   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
00997   * @retval PCLK2 frequency
00998   */
00999 uint32_t HAL_RCC_GetPCLK2Freq(void)
01000 {
01001   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
01002   return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]);
01003 }
01004
01005 /**
01006   * @brief  Configures the RCC_OscInitStruct according to the internal
01007   * RCC configuration registers.
01008   * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
01009   * will be configured.
01010   * @retval None
01011   */
01012 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
01013 {
01014   /* Check the parameters */
01015   assert_param(RCC_OscInitStruct != NULL);
01016
01017   /* Set all possible values for the Oscillator type parameter ---------------*/
01018   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI  \
01019                   | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
01020
01021
01022   /* Get the HSE configuration -----------------------------------------------*/
01023   if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
01024   {
01025     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
01026   }
01027   else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
01028   {
01029     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
01030   }
01031   else
01032   {
01033     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
01034   }
01035 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
01036   RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
01037 #endif
01038
01039   /* Get the HSI configuration -----------------------------------------------*/
01040   if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
01041   {
01042     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
01043   }
01044   else
01045   {
01046     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
01047   }
01048
01049   RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
01050
01051   /* Get the LSE configuration -----------------------------------------------*/
01052   if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
01053   {
01054     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
01055   }
01056   else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
01057   {
01058     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
01059   }
01060   else
01061   {
01062     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
01063   }
01064
01065   /* Get the LSI configuration -----------------------------------------------*/
01066   if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
01067   {
01068     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
01069   }
01070   else
01071   {
01072     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
01073   }
01074
01075
01076   /* Get the PLL configuration -----------------------------------------------*/
01077   if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
01078   {
01079     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
01080   }
01081   else
01082   {
01083     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
01084   }
01085   RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
01086   RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
01087 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
01088   RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV);
01089 #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
01090 }
01091
01092 /**
01093   * @brief  Get the RCC_ClkInitStruct according to the internal
01094   * RCC configuration registers.
01095   * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
01096   * contains the current clock configuration.
01097   * @param  pFLatency Pointer on the Flash Latency.
01098   * @retval None
01099   */
01100 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
01101 {
01102   /* Check the parameters */
01103   assert_param(RCC_ClkInitStruct != NULL);
01104   assert_param(pFLatency != NULL);
01105
01106   /* Set all possible values for the Clock type parameter --------------------*/
01107   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
01108
01109   /* Get the SYSCLK configuration --------------------------------------------*/
01110   RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
01111
01112   /* Get the HCLK configuration ----------------------------------------------*/
01113   RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
01114
01115   /* Get the APB1 configuration ----------------------------------------------*/
01116   RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
01117
01118   /* Get the APB2 configuration ----------------------------------------------*/
01119   RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
01120
01121   /* Get the Flash Wait State (Latency) configuration ------------------------*/
01122   *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
01123 }
01124
01125 /**
01126   * @brief This function handles the RCC CSS interrupt request.
01127   * @note This API should be called under the NMI_Handler().
01128   * @retval None
01129   */
01130 void HAL_RCC_NMI_IRQHandler(void)
01131 {
01132   /* Check RCC CSSF flag  */
01133   if(__HAL_RCC_GET_IT(RCC_IT_CSS))
01134   {
01135     /* RCC Clock Security System interrupt user callback */
01136     HAL_RCC_CSSCallback();
01137
01138     /* Clear RCC CSS pending bit */
01139     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
01140   }
01141 }
01142
01143 /**
01144   * @brief  RCC Clock Security System interrupt callback
01145   * @retval none
01146   */
01147 __weak void HAL_RCC_CSSCallback(void)
01148 {
01149   /* NOTE : This function Should not be modified, when the callback is needed,
01150     the HAL_RCC_CSSCallback could be implemented in the user file
01151     */
01152 }
01153
01154 /**
01155   * @}
01156   */
01157
01158 /**
01159   * @}
01160   */
01161
01162 #endif /* HAL_RCC_MODULE_ENABLED */
01163 /**
01164   * @}
01165   */
01166
01167 /**
01168   * @}
01169   */
01170
01171 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_rcc.h Source File

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stm32f3xx_hal_rcc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_rcc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RCC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_RCC_H
00038 #define __STM32F3xx_HAL_RCC_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup RCC
00052   * @{
00053   */
00054
00055 /** @addtogroup RCC_Private_Constants
00056   * @{
00057   */
00058
00059 /** @defgroup RCC_Timeout RCC Timeout
00060   * @{
00061   */
00062
00063 /* Disable Backup domain write protection state change timeout */
00064 #define RCC_DBP_TIMEOUT_VALUE      (100U)       /* 100 ms */
00065 /* LSE state change timeout */
00066 #define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
00067 #define CLOCKSWITCH_TIMEOUT_VALUE  (5000U)  /* 5 s    */
00068 #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
00069 #define HSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
00070 #define LSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
00071 #define PLL_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
00072 /**
00073   * @}
00074   */
00075
00076 /** @defgroup RCC_Register_Offset Register offsets
00077   * @{
00078   */
00079 #define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
00080 #define RCC_CR_OFFSET             0x00
00081 #define RCC_CFGR_OFFSET           0x04
00082 #define RCC_CIR_OFFSET            0x08
00083 #define RCC_BDCR_OFFSET           0x20
00084 #define RCC_CSR_OFFSET            0x24
00085
00086 /**
00087   * @}
00088   */
00089
00090 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
00091   * @brief RCC registers bit address in the alias region
00092   * @{
00093   */
00094 #define RCC_CR_OFFSET_BB          (RCC_OFFSET + RCC_CR_OFFSET)
00095 #define RCC_CFGR_OFFSET_BB        (RCC_OFFSET + RCC_CFGR_OFFSET)
00096 #define RCC_CIR_OFFSET_BB         (RCC_OFFSET + RCC_CIR_OFFSET)
00097 #define RCC_BDCR_OFFSET_BB        (RCC_OFFSET + RCC_BDCR_OFFSET)
00098 #define RCC_CSR_OFFSET_BB         (RCC_OFFSET + RCC_CSR_OFFSET)
00099
00100 /* --- CR Register ---*/
00101 /* Alias word address of HSION bit */
00102 #define RCC_HSION_BIT_NUMBER      POSITION_VAL(RCC_CR_HSION)
00103 #define RCC_CR_HSION_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
00104 /* Alias word address of HSEON bit */
00105 #define RCC_HSEON_BIT_NUMBER      POSITION_VAL(RCC_CR_HSEON)
00106 #define RCC_CR_HSEON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
00107 /* Alias word address of CSSON bit */
00108 #define RCC_CSSON_BIT_NUMBER      POSITION_VAL(RCC_CR_CSSON)
00109 #define RCC_CR_CSSON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
00110 /* Alias word address of PLLON bit */
00111 #define RCC_PLLON_BIT_NUMBER      POSITION_VAL(RCC_CR_PLLON)
00112 #define RCC_CR_PLLON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
00113
00114 /* --- CSR Register ---*/
00115 /* Alias word address of LSION bit */
00116 #define RCC_LSION_BIT_NUMBER      POSITION_VAL(RCC_CSR_LSION)
00117 #define RCC_CSR_LSION_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
00118
00119 /* Alias word address of RMVF bit */
00120 #define RCC_RMVF_BIT_NUMBER       POSITION_VAL(RCC_CSR_RMVF)
00121 #define RCC_CSR_RMVF_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
00122
00123 /* --- BDCR Registers ---*/
00124 /* Alias word address of LSEON bit */
00125 #define RCC_LSEON_BIT_NUMBER      POSITION_VAL(RCC_BDCR_LSEON)
00126 #define RCC_BDCR_LSEON_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
00127
00128 /* Alias word address of LSEON bit */
00129 #define RCC_LSEBYP_BIT_NUMBER     POSITION_VAL(RCC_BDCR_LSEBYP)
00130 #define RCC_BDCR_LSEBYP_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
00131
00132 /* Alias word address of RTCEN bit */
00133 #define RCC_RTCEN_BIT_NUMBER      POSITION_VAL(RCC_BDCR_RTCEN)
00134 #define RCC_BDCR_RTCEN_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
00135
00136 /* Alias word address of BDRST bit */
00137 #define RCC_BDRST_BIT_NUMBER          POSITION_VAL(RCC_BDCR_BDRST)
00138 #define RCC_BDCR_BDRST_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
00139
00140 /**
00141   * @}
00142   */
00143
00144 /* CR register byte 2 (Bits[23:16]) base address */
00145 #define RCC_CR_BYTE2_ADDRESS          ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
00146
00147 /* CIR register byte 1 (Bits[15:8]) base address */
00148 #define RCC_CIR_BYTE1_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
00149
00150 /* CIR register byte 2 (Bits[23:16]) base address */
00151 #define RCC_CIR_BYTE2_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
00152
00153 /* Defines used for Flags */
00154 #define CR_REG_INDEX                     ((uint8_t)1U)
00155 #define BDCR_REG_INDEX                   ((uint8_t)2U)
00156 #define CSR_REG_INDEX                    ((uint8_t)3U)
00157 #define CFGR_REG_INDEX                   ((uint8_t)4U)
00158
00159 #define RCC_FLAG_MASK                    ((uint8_t)0x1FU)
00160
00161 /**
00162   * @}
00163   */
00164
00165 /** @addtogroup RCC_Private_Macros
00166   * @{
00167   */
00168 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
00169                                       ((__SOURCE__) == RCC_PLLSOURCE_HSE))
00170 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
00171                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
00172                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
00173                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
00174                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
00175 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
00176                              ((__HSE__) == RCC_HSE_BYPASS))
00177 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
00178                              ((__LSE__) == RCC_LSE_BYPASS))
00179 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
00180 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
00181 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
00182 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
00183                              ((__PLL__) == RCC_PLL_ON))
00184 #if   defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
00185 #define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1)  || ((__PREDIV__) == RCC_PREDIV_DIV2)   || \
00186                                   ((__PREDIV__) == RCC_PREDIV_DIV3)  || ((__PREDIV__) == RCC_PREDIV_DIV4)   || \
00187                                   ((__PREDIV__) == RCC_PREDIV_DIV5)  || ((__PREDIV__) == RCC_PREDIV_DIV6)   || \
00188                                   ((__PREDIV__) == RCC_PREDIV_DIV7)  || ((__PREDIV__) == RCC_PREDIV_DIV8)   || \
00189                                   ((__PREDIV__) == RCC_PREDIV_DIV9)  || ((__PREDIV__) == RCC_PREDIV_DIV10)  || \
00190                                   ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12)  || \
00191                                   ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14)  || \
00192                                   ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16))
00193 #else
00194 #define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \
00195                                  ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))
00196 #endif
00197 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
00198 #define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1)  || ((DIV) == RCC_HSE_PREDIV_DIV2)  || \
00199                                 ((DIV) == RCC_HSE_PREDIV_DIV3)  || ((DIV) == RCC_HSE_PREDIV_DIV4)  || \
00200                                 ((DIV) == RCC_HSE_PREDIV_DIV5)  || ((DIV) == RCC_HSE_PREDIV_DIV6)  || \
00201                                 ((DIV) == RCC_HSE_PREDIV_DIV7)  || ((DIV) == RCC_HSE_PREDIV_DIV8)  || \
00202                                 ((DIV) == RCC_HSE_PREDIV_DIV9)  || ((DIV) == RCC_HSE_PREDIV_DIV10) || \
00203                                 ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \
00204                                 ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \
00205                                 ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16))
00206 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
00207
00208 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2)  || ((__MUL__) == RCC_PLL_MUL3)   || \
00209                                  ((__MUL__) == RCC_PLL_MUL4)  || ((__MUL__) == RCC_PLL_MUL5)   || \
00210                                  ((__MUL__) == RCC_PLL_MUL6)  || ((__MUL__) == RCC_PLL_MUL7)   || \
00211                                  ((__MUL__) == RCC_PLL_MUL8)  || ((__MUL__) == RCC_PLL_MUL9)   || \
00212                                  ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11)  || \
00213                                  ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13)  || \
00214                                  ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15)  || \
00215                                  ((__MUL__) == RCC_PLL_MUL16))
00216 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
00217                                (((CLK) & RCC_CLOCKTYPE_HCLK)   == RCC_CLOCKTYPE_HCLK)   || \
00218                                (((CLK) & RCC_CLOCKTYPE_PCLK1)  == RCC_CLOCKTYPE_PCLK1)  || \
00219                                (((CLK) & RCC_CLOCKTYPE_PCLK2)  == RCC_CLOCKTYPE_PCLK2))
00220 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
00221                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
00222                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
00223 #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
00224                                                 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
00225                                                 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
00226 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
00227                                ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
00228                                ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
00229                                ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
00230                                ((__HCLK__) == RCC_SYSCLK_DIV512))
00231 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
00232                                ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
00233                                ((__PCLK__) == RCC_HCLK_DIV16))
00234 #define IS_RCC_MCO(__MCO__)  ((__MCO__) == RCC_MCO)
00235 #define IS_RCC_RTCCLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
00236                                           ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)  || \
00237                                           ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)  || \
00238                                           ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
00239 #if defined(RCC_CFGR3_USART2SW)
00240 #define IS_RCC_USART2CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \
00241                                              ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
00242                                              ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \
00243                                              ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
00244 #endif /* RCC_CFGR3_USART2SW */
00245 #if defined(RCC_CFGR3_USART3SW)
00246 #define IS_RCC_USART3CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1)  || \
00247                                              ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
00248                                              ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)    || \
00249                                              ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
00250 #endif /* RCC_CFGR3_USART3SW */
00251 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \
00252                                            ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
00253
00254 /**
00255   * @}
00256   */
00257
00258 /* Exported types ------------------------------------------------------------*/
00259
00260 /** @defgroup RCC_Exported_Types RCC Exported Types
00261   * @{
00262   */
00263
00264 /**
00265   * @brief  RCC PLL configuration structure definition
00266   */
00267 typedef struct
00268 {
00269   uint32_t PLLState;      /*!< PLLState: The new state of the PLL.
00270                               This parameter can be a value of @ref RCC_PLL_Config */
00271
00272   uint32_t PLLSource;     /*!< PLLSource: PLL entry clock source.
00273                               This parameter must be a value of @ref RCC_PLL_Clock_Source */
00274
00275   uint32_t PLLMUL;        /*!< PLLMUL: Multiplication factor for PLL VCO input clock
00276                               This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
00277
00278 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
00279   uint32_t PREDIV;        /*!< PREDIV: Predivision factor for PLL VCO input clock
00280                               This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
00281
00282 #endif
00283 } RCC_PLLInitTypeDef;
00284
00285 /**
00286   * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
00287   */
00288 typedef struct
00289 {
00290   uint32_t OscillatorType;        /*!< The oscillators to be configured.
00291                                        This parameter can be a value of @ref RCC_Oscillator_Type */
00292
00293   uint32_t HSEState;              /*!< The new state of the HSE.
00294                                        This parameter can be a value of @ref RCC_HSE_Config */
00295
00296 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
00297   uint32_t HSEPredivValue;       /*!<  The HSE predivision factor value.
00298                                        This parameter can be a value of @ref RCC_PLL_HSE_Prediv_Factor */
00299
00300 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
00301   uint32_t LSEState;              /*!< The new state of the LSE.
00302                                        This parameter can be a value of @ref RCC_LSE_Config */
00303
00304   uint32_t HSIState;              /*!< The new state of the HSI.
00305                                        This parameter can be a value of @ref RCC_HSI_Config */
00306
00307   uint32_t HSICalibrationValue;   /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
00308                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
00309
00310   uint32_t LSIState;              /*!< The new state of the LSI.
00311                                        This parameter can be a value of @ref RCC_LSI_Config */
00312
00313   RCC_PLLInitTypeDef PLL;         /*!< PLL structure parameters */
00314
00315 } RCC_OscInitTypeDef;
00316
00317 /**
00318   * @brief  RCC System, AHB and APB busses clock configuration structure definition
00319   */
00320 typedef struct
00321 {
00322   uint32_t ClockType;             /*!< The clock to be configured.
00323                                        This parameter can be a value of @ref RCC_System_Clock_Type */
00324
00325   uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
00326                                        This parameter can be a value of @ref RCC_System_Clock_Source */
00327
00328   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
00329                                        This parameter can be a value of @ref RCC_AHB_Clock_Source */
00330
00331   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00332                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
00333
00334   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
00335                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
00336 } RCC_ClkInitTypeDef;
00337
00338 /**
00339   * @}
00340   */
00341
00342 /* Exported constants --------------------------------------------------------*/
00343 /** @defgroup RCC_Exported_Constants RCC Exported Constants
00344   * @{
00345   */
00346
00347 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
00348   * @{
00349   */
00350
00351 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
00352 #define RCC_PLLSOURCE_HSI           RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI clock selected as PLL entry clock source */
00353 #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
00354 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
00355 #define RCC_PLLSOURCE_HSI           RCC_CFGR_PLLSRC_HSI_DIV2   /*!< HSI clock divided by 2 selected as PLL entry clock source */
00356 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
00357 #define RCC_PLLSOURCE_HSE           RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */
00358
00359 /**
00360   * @}
00361   */
00362
00363 /** @defgroup RCC_Oscillator_Type Oscillator Type
00364   * @{
00365   */
00366 #define RCC_OSCILLATORTYPE_NONE            (0x00000000U)
00367 #define RCC_OSCILLATORTYPE_HSE             (0x00000001U)
00368 #define RCC_OSCILLATORTYPE_HSI             (0x00000002U)
00369 #define RCC_OSCILLATORTYPE_LSE             (0x00000004U)
00370 #define RCC_OSCILLATORTYPE_LSI             (0x00000008U)
00371 /**
00372   * @}
00373   */
00374
00375 /** @defgroup RCC_HSE_Config HSE Config
00376   * @{
00377   */
00378 #define RCC_HSE_OFF                      (0x00000000U)                     /*!< HSE clock deactivation */
00379 #define RCC_HSE_ON                       RCC_CR_HSEON                               /*!< HSE clock activation */
00380 #define RCC_HSE_BYPASS                   ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup RCC_LSE_Config LSE Config
00386   * @{
00387   */
00388 #define RCC_LSE_OFF                      (0x00000000U)                       /*!< LSE clock deactivation */
00389 #define RCC_LSE_ON                       RCC_BDCR_LSEON                                /*!< LSE clock activation */
00390 #define RCC_LSE_BYPASS                   ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
00391
00392 /**
00393   * @}
00394   */
00395
00396 /** @defgroup RCC_HSI_Config HSI Config
00397   * @{
00398   */
00399 #define RCC_HSI_OFF                      (0x00000000U)           /*!< HSI clock deactivation */
00400 #define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
00401
00402 #define RCC_HSICALIBRATION_DEFAULT       (0x10U)         /* Default HSI calibration trimming value */
00403
00404 /**
00405   * @}
00406   */
00407
00408 /** @defgroup RCC_LSI_Config LSI Config
00409   * @{
00410   */
00411 #define RCC_LSI_OFF                      (0x00000000U)   /*!< LSI clock deactivation */
00412 #define RCC_LSI_ON                       RCC_CSR_LSION            /*!< LSI clock activation */
00413
00414 /**
00415   * @}
00416   */
00417
00418 /** @defgroup RCC_PLL_Config PLL Config
00419   * @{
00420   */
00421 #define RCC_PLL_NONE                      (0x00000000U)  /*!< PLL is not configured */
00422 #define RCC_PLL_OFF                       (0x00000001U)  /*!< PLL deactivation */
00423 #define RCC_PLL_ON                        (0x00000002U)  /*!< PLL activation */
00424
00425 /**
00426   * @}
00427   */
00428
00429 /** @defgroup RCC_System_Clock_Type System Clock Type
00430   * @{
00431   */
00432 #define RCC_CLOCKTYPE_SYSCLK             (0x00000001U) /*!< SYSCLK to configure */
00433 #define RCC_CLOCKTYPE_HCLK               (0x00000002U) /*!< HCLK to configure */
00434 #define RCC_CLOCKTYPE_PCLK1              (0x00000004U) /*!< PCLK1 to configure */
00435 #define RCC_CLOCKTYPE_PCLK2              (0x00000008U) /*!< PCLK2 to configure */
00436
00437 /**
00438   * @}
00439   */
00440
00441 /** @defgroup RCC_System_Clock_Source System Clock Source
00442   * @{
00443   */
00444 #define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
00445 #define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
00446 #define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
00447
00448 /**
00449   * @}
00450   */
00451
00452 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
00453   * @{
00454   */
00455 #define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI            /*!< HSI used as system clock */
00456 #define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE            /*!< HSE used as system clock */
00457 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL            /*!< PLL used as system clock */
00458
00459 /**
00460   * @}
00461   */
00462
00463 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
00464   * @{
00465   */
00466 #define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
00467 #define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
00468 #define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
00469 #define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
00470 #define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
00471 #define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
00472 #define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
00473 #define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
00474 #define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
00475
00476 /**
00477   * @}
00478   */
00479
00480 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
00481   * @{
00482   */
00483 #define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
00484 #define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
00485 #define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
00486 #define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
00487 #define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
00488
00489 /**
00490   * @}
00491   */
00492
00493 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
00494   * @{
00495   */
00496 #define RCC_RTCCLKSOURCE_NO_CLK          RCC_BDCR_RTCSEL_NOCLOCK                /*!< No clock */
00497 #define RCC_RTCCLKSOURCE_LSE             RCC_BDCR_RTCSEL_LSE                  /*!< LSE oscillator clock used as RTC clock */
00498 #define RCC_RTCCLKSOURCE_LSI             RCC_BDCR_RTCSEL_LSI                  /*!< LSI oscillator clock used as RTC clock */
00499 #define RCC_RTCCLKSOURCE_HSE_DIV32       RCC_BDCR_RTCSEL_HSE                    /*!< HSE oscillator clock divided by 32 used as RTC clock */
00500 /**
00501   * @}
00502   */
00503
00504 /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
00505   * @{
00506   */
00507 #define RCC_PLL_MUL2                     RCC_CFGR_PLLMUL2
00508 #define RCC_PLL_MUL3                     RCC_CFGR_PLLMUL3
00509 #define RCC_PLL_MUL4                     RCC_CFGR_PLLMUL4
00510 #define RCC_PLL_MUL5                     RCC_CFGR_PLLMUL5
00511 #define RCC_PLL_MUL6                     RCC_CFGR_PLLMUL6
00512 #define RCC_PLL_MUL7                     RCC_CFGR_PLLMUL7
00513 #define RCC_PLL_MUL8                     RCC_CFGR_PLLMUL8
00514 #define RCC_PLL_MUL9                     RCC_CFGR_PLLMUL9
00515 #define RCC_PLL_MUL10                    RCC_CFGR_PLLMUL10
00516 #define RCC_PLL_MUL11                    RCC_CFGR_PLLMUL11
00517 #define RCC_PLL_MUL12                    RCC_CFGR_PLLMUL12
00518 #define RCC_PLL_MUL13                    RCC_CFGR_PLLMUL13
00519 #define RCC_PLL_MUL14                    RCC_CFGR_PLLMUL14
00520 #define RCC_PLL_MUL15                    RCC_CFGR_PLLMUL15
00521 #define RCC_PLL_MUL16                    RCC_CFGR_PLLMUL16
00522
00523 /**
00524   * @}
00525   */
00526
00527 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
00528 /** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
00529   * @{
00530   */
00531
00532 #define RCC_PREDIV_DIV1                  RCC_CFGR2_PREDIV_DIV1
00533 #define RCC_PREDIV_DIV2                  RCC_CFGR2_PREDIV_DIV2
00534 #define RCC_PREDIV_DIV3                  RCC_CFGR2_PREDIV_DIV3
00535 #define RCC_PREDIV_DIV4                  RCC_CFGR2_PREDIV_DIV4
00536 #define RCC_PREDIV_DIV5                  RCC_CFGR2_PREDIV_DIV5
00537 #define RCC_PREDIV_DIV6                  RCC_CFGR2_PREDIV_DIV6
00538 #define RCC_PREDIV_DIV7                  RCC_CFGR2_PREDIV_DIV7
00539 #define RCC_PREDIV_DIV8                  RCC_CFGR2_PREDIV_DIV8
00540 #define RCC_PREDIV_DIV9                  RCC_CFGR2_PREDIV_DIV9
00541 #define RCC_PREDIV_DIV10                 RCC_CFGR2_PREDIV_DIV10
00542 #define RCC_PREDIV_DIV11                 RCC_CFGR2_PREDIV_DIV11
00543 #define RCC_PREDIV_DIV12                 RCC_CFGR2_PREDIV_DIV12
00544 #define RCC_PREDIV_DIV13                 RCC_CFGR2_PREDIV_DIV13
00545 #define RCC_PREDIV_DIV14                 RCC_CFGR2_PREDIV_DIV14
00546 #define RCC_PREDIV_DIV15                 RCC_CFGR2_PREDIV_DIV15
00547 #define RCC_PREDIV_DIV16                 RCC_CFGR2_PREDIV_DIV16
00548
00549 /**
00550   * @}
00551   */
00552
00553 #endif
00554 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
00555 /** @defgroup RCC_PLL_HSE_Prediv_Factor RCC PLL HSE Prediv Factor
00556   * @{
00557   */
00558
00559 #define RCC_HSE_PREDIV_DIV1              RCC_CFGR2_PREDIV_DIV1
00560 #define RCC_HSE_PREDIV_DIV2              RCC_CFGR2_PREDIV_DIV2
00561 #define RCC_HSE_PREDIV_DIV3              RCC_CFGR2_PREDIV_DIV3
00562 #define RCC_HSE_PREDIV_DIV4              RCC_CFGR2_PREDIV_DIV4
00563 #define RCC_HSE_PREDIV_DIV5              RCC_CFGR2_PREDIV_DIV5
00564 #define RCC_HSE_PREDIV_DIV6              RCC_CFGR2_PREDIV_DIV6
00565 #define RCC_HSE_PREDIV_DIV7              RCC_CFGR2_PREDIV_DIV7
00566 #define RCC_HSE_PREDIV_DIV8              RCC_CFGR2_PREDIV_DIV8
00567 #define RCC_HSE_PREDIV_DIV9              RCC_CFGR2_PREDIV_DIV9
00568 #define RCC_HSE_PREDIV_DIV10             RCC_CFGR2_PREDIV_DIV10
00569 #define RCC_HSE_PREDIV_DIV11             RCC_CFGR2_PREDIV_DIV11
00570 #define RCC_HSE_PREDIV_DIV12             RCC_CFGR2_PREDIV_DIV12
00571 #define RCC_HSE_PREDIV_DIV13             RCC_CFGR2_PREDIV_DIV13
00572 #define RCC_HSE_PREDIV_DIV14             RCC_CFGR2_PREDIV_DIV14
00573 #define RCC_HSE_PREDIV_DIV15             RCC_CFGR2_PREDIV_DIV15
00574 #define RCC_HSE_PREDIV_DIV16             RCC_CFGR2_PREDIV_DIV16
00575
00576 /**
00577   * @}
00578   */
00579 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
00580
00581 #if defined(RCC_CFGR3_USART2SW)
00582 /** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source
00583   * @{
00584   */
00585 #define RCC_USART2CLKSOURCE_PCLK1        RCC_CFGR3_USART2SW_PCLK
00586 #define RCC_USART2CLKSOURCE_SYSCLK       RCC_CFGR3_USART2SW_SYSCLK
00587 #define RCC_USART2CLKSOURCE_LSE          RCC_CFGR3_USART2SW_LSE
00588 #define RCC_USART2CLKSOURCE_HSI          RCC_CFGR3_USART2SW_HSI
00589
00590 /**
00591   * @}
00592   */
00593 #endif /* RCC_CFGR3_USART2SW */
00594
00595 #if defined(RCC_CFGR3_USART3SW)
00596 /** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source
00597   * @{
00598   */
00599 #define RCC_USART3CLKSOURCE_PCLK1        RCC_CFGR3_USART3SW_PCLK
00600 #define RCC_USART3CLKSOURCE_SYSCLK       RCC_CFGR3_USART3SW_SYSCLK
00601 #define RCC_USART3CLKSOURCE_LSE          RCC_CFGR3_USART3SW_LSE
00602 #define RCC_USART3CLKSOURCE_HSI          RCC_CFGR3_USART3SW_HSI
00603
00604 /**
00605   * @}
00606   */
00607 #endif /* RCC_CFGR3_USART3SW */
00608
00609 /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
00610   * @{
00611   */
00612 #define RCC_I2C1CLKSOURCE_HSI            RCC_CFGR3_I2C1SW_HSI
00613 #define RCC_I2C1CLKSOURCE_SYSCLK         RCC_CFGR3_I2C1SW_SYSCLK
00614
00615 /**
00616   * @}
00617   */
00618 /** @defgroup RCC_MCO_Index MCO Index
00619   * @{
00620   */
00621 #define RCC_MCO1                         (0x00000000U)
00622 #define RCC_MCO                          RCC_MCO1               /*!< MCO1 to be compliant with other families with 2 MCOs*/
00623
00624 /**
00625   * @}
00626   */
00627
00628 /** @defgroup RCC_Interrupt Interrupts
00629   * @{
00630   */
00631 #define RCC_IT_LSIRDY                    ((uint8_t)RCC_CIR_LSIRDYF)   /*!< LSI Ready Interrupt flag */
00632 #define RCC_IT_LSERDY                    ((uint8_t)RCC_CIR_LSERDYF)   /*!< LSE Ready Interrupt flag */
00633 #define RCC_IT_HSIRDY                    ((uint8_t)RCC_CIR_HSIRDYF)   /*!< HSI Ready Interrupt flag */
00634 #define RCC_IT_HSERDY                    ((uint8_t)RCC_CIR_HSERDYF)   /*!< HSE Ready Interrupt flag */
00635 #define RCC_IT_PLLRDY                    ((uint8_t)RCC_CIR_PLLRDYF)   /*!< PLL Ready Interrupt flag */
00636 #define RCC_IT_CSS                       ((uint8_t)RCC_CIR_CSSF)      /*!< Clock Security System Interrupt flag */
00637 /**
00638   * @}
00639   */
00640
00641 /** @defgroup RCC_Flag Flags
00642   *        Elements values convention: XXXYYYYYb
00643   *           - YYYYY  : Flag position in the register
00644   *           - XXX  : Register index
00645   *                 - 001: CR register
00646   *                 - 010: BDCR register
00647   *                 - 011: CSR register
00648   *                 - 100: CFGR register
00649   * @{
00650   */
00651 /* Flags in the CR register */
00652 #define RCC_FLAG_HSIRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
00653 #define RCC_FLAG_HSERDY                  ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
00654 #define RCC_FLAG_PLLRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
00655
00656 /* Flags in the CSR register */
00657 #define RCC_FLAG_LSIRDY                  ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY)))   /*!< Internal Low Speed oscillator Ready */
00658 #if   defined(RCC_CSR_V18PWRRSTF)
00659 #define RCC_FLAG_V18PWRRST               ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_V18PWRRSTF)))
00660 #endif
00661 #define RCC_FLAG_OBLRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF)))  /*!< Options bytes loading reset flag */
00662 #define RCC_FLAG_PINRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF)))  /*!< PIN reset flag */
00663 #define RCC_FLAG_PORRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF)))  /*!< POR/PDR reset flag */
00664 #define RCC_FLAG_SFTRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF)))  /*!< Software Reset flag */
00665 #define RCC_FLAG_IWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
00666 #define RCC_FLAG_WWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
00667 #define RCC_FLAG_LPWRRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
00668
00669 /* Flags in the BDCR register */
00670 #define RCC_FLAG_LSERDY                  ((uint8_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */
00671
00672 /* Flags in the CFGR register */
00673 #if defined(RCC_CFGR_MCOF)
00674 #define RCC_FLAG_MCO                     ((uint8_t)((CFGR_REG_INDEX << 5U) | POSITION_VAL(RCC_CFGR_MCOF)))   /*!< Microcontroller Clock Output Flag */
00675 #endif /* RCC_CFGR_MCOF */
00676
00677 /**
00678   * @}
00679   */
00680
00681 /**
00682   * @}
00683   */
00684
00685 /* Exported macro ------------------------------------------------------------*/
00686
00687 /** @defgroup RCC_Exported_Macros RCC Exported Macros
00688   * @{
00689   */
00690
00691 /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
00692   * @brief  Enable or disable the AHB peripheral clock.
00693   * @note   After reset, the peripheral clock (used for registers read/write access)
00694   *         is disabled and the application software has to enable this clock before
00695   *         using it.
00696   * @{
00697   */
00698 #define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
00699                                         __IO uint32_t tmpreg; \
00700                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
00701                                         /* Delay after an RCC peripheral clock enabling */ \
00702                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
00703                                         UNUSED(tmpreg); \
00704                                       } while(0U)
00705 #define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
00706                                         __IO uint32_t tmpreg; \
00707                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
00708                                         /* Delay after an RCC peripheral clock enabling */ \
00709                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
00710                                         UNUSED(tmpreg); \
00711                                       } while(0U)
00712 #define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
00713                                         __IO uint32_t tmpreg; \
00714                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
00715                                         /* Delay after an RCC peripheral clock enabling */ \
00716                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
00717                                         UNUSED(tmpreg); \
00718                                       } while(0U)
00719 #define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
00720                                         __IO uint32_t tmpreg; \
00721                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
00722                                         /* Delay after an RCC peripheral clock enabling */ \
00723                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
00724                                         UNUSED(tmpreg); \
00725                                       } while(0U)
00726 #define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
00727                                         __IO uint32_t tmpreg; \
00728                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
00729                                         /* Delay after an RCC peripheral clock enabling */ \
00730                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
00731                                         UNUSED(tmpreg); \
00732                                       } while(0U)
00733 #define __HAL_RCC_CRC_CLK_ENABLE()   do { \
00734                                         __IO uint32_t tmpreg; \
00735                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
00736                                         /* Delay after an RCC peripheral clock enabling */ \
00737                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
00738                                         UNUSED(tmpreg); \
00739                                       } while(0U)
00740 #define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
00741                                         __IO uint32_t tmpreg; \
00742                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
00743                                         /* Delay after an RCC peripheral clock enabling */ \
00744                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
00745                                         UNUSED(tmpreg); \
00746                                       } while(0U)
00747 #define __HAL_RCC_SRAM_CLK_ENABLE()   do { \
00748                                         __IO uint32_t tmpreg; \
00749                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
00750                                         /* Delay after an RCC peripheral clock enabling */ \
00751                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
00752                                         UNUSED(tmpreg); \
00753                                       } while(0U)
00754 #define __HAL_RCC_FLITF_CLK_ENABLE()   do { \
00755                                         __IO uint32_t tmpreg; \
00756                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
00757                                         /* Delay after an RCC peripheral clock enabling */ \
00758                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
00759                                         UNUSED(tmpreg); \
00760                                       } while(0U)
00761 #define __HAL_RCC_TSC_CLK_ENABLE()   do { \
00762                                         __IO uint32_t tmpreg; \
00763                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
00764                                         /* Delay after an RCC peripheral clock enabling */ \
00765                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
00766                                         UNUSED(tmpreg); \
00767                                       } while(0U)
00768
00769 #define __HAL_RCC_GPIOA_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
00770 #define __HAL_RCC_GPIOB_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
00771 #define __HAL_RCC_GPIOC_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
00772 #define __HAL_RCC_GPIOD_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
00773 #define __HAL_RCC_GPIOF_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
00774 #define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
00775 #define __HAL_RCC_DMA1_CLK_DISABLE()         (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
00776 #define __HAL_RCC_SRAM_CLK_DISABLE()         (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
00777 #define __HAL_RCC_FLITF_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
00778 #define __HAL_RCC_TSC_CLK_DISABLE()          (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
00779 /**
00780   * @}
00781   */
00782
00783 /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
00784   * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
00785   * @note   After reset, the peripheral clock (used for registers read/write access)
00786   *         is disabled and the application software has to enable this clock before
00787   *         using it.
00788   * @{
00789   */
00790 #define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
00791                                         __IO uint32_t tmpreg; \
00792                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
00793                                         /* Delay after an RCC peripheral clock enabling */ \
00794                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
00795                                         UNUSED(tmpreg); \
00796                                       } while(0U)
00797 #define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
00798                                         __IO uint32_t tmpreg; \
00799                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
00800                                         /* Delay after an RCC peripheral clock enabling */ \
00801                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
00802                                         UNUSED(tmpreg); \
00803                                       } while(0U)
00804 #define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
00805                                         __IO uint32_t tmpreg; \
00806                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
00807                                         /* Delay after an RCC peripheral clock enabling */ \
00808                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
00809                                         UNUSED(tmpreg); \
00810                                       } while(0U)
00811 #define __HAL_RCC_USART2_CLK_ENABLE()   do { \
00812                                         __IO uint32_t tmpreg; \
00813                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
00814                                         /* Delay after an RCC peripheral clock enabling */ \
00815                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
00816                                         UNUSED(tmpreg); \
00817                                       } while(0U)
00818 #define __HAL_RCC_USART3_CLK_ENABLE()   do { \
00819                                         __IO uint32_t tmpreg; \
00820                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
00821                                         /* Delay after an RCC peripheral clock enabling */ \
00822                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
00823                                         UNUSED(tmpreg); \
00824                                       } while(0U)
00825 #define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
00826                                         __IO uint32_t tmpreg; \
00827                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
00828                                         /* Delay after an RCC peripheral clock enabling */ \
00829                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
00830                                         UNUSED(tmpreg); \
00831                                       } while(0U)
00832 #define __HAL_RCC_PWR_CLK_ENABLE()   do { \
00833                                         __IO uint32_t tmpreg; \
00834                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
00835                                         /* Delay after an RCC peripheral clock enabling */ \
00836                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
00837                                         UNUSED(tmpreg); \
00838                                       } while(0U)
00839 #define __HAL_RCC_DAC1_CLK_ENABLE()   do { \
00840                                         __IO uint32_t tmpreg; \
00841                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
00842                                         /* Delay after an RCC peripheral clock enabling */ \
00843                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
00844                                         UNUSED(tmpreg); \
00845                                       } while(0U)
00846
00847 #define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
00848 #define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
00849 #define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
00850 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
00851 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
00852 #define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
00853 #define __HAL_RCC_PWR_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
00854 #define __HAL_RCC_DAC1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))
00855 /**
00856   * @}
00857   */
00858
00859 /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
00860   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
00861   * @note   After reset, the peripheral clock (used for registers read/write access)
00862   *         is disabled and the application software has to enable this clock before
00863   *         using it.
00864   * @{
00865   */
00866 #define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
00867                                         __IO uint32_t tmpreg; \
00868                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
00869                                         /* Delay after an RCC peripheral clock enabling */ \
00870                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
00871                                         UNUSED(tmpreg); \
00872                                       } while(0U)
00873 #define __HAL_RCC_TIM15_CLK_ENABLE()   do { \
00874                                         __IO uint32_t tmpreg; \
00875                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
00876                                         /* Delay after an RCC peripheral clock enabling */ \
00877                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
00878                                         UNUSED(tmpreg); \
00879                                       } while(0U)
00880 #define __HAL_RCC_TIM16_CLK_ENABLE()   do { \
00881                                         __IO uint32_t tmpreg; \
00882                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
00883                                         /* Delay after an RCC peripheral clock enabling */ \
00884                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
00885                                         UNUSED(tmpreg); \
00886                                       } while(0U)
00887 #define __HAL_RCC_TIM17_CLK_ENABLE()   do { \
00888                                         __IO uint32_t tmpreg; \
00889                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
00890                                         /* Delay after an RCC peripheral clock enabling */ \
00891                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
00892                                         UNUSED(tmpreg); \
00893                                       } while(0U)
00894 #define __HAL_RCC_USART1_CLK_ENABLE()   do { \
00895                                         __IO uint32_t tmpreg; \
00896                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
00897                                         /* Delay after an RCC peripheral clock enabling */ \
00898                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
00899                                         UNUSED(tmpreg); \
00900                                       } while(0U)
00901
00902 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
00903 #define __HAL_RCC_TIM15_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
00904 #define __HAL_RCC_TIM16_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
00905 #define __HAL_RCC_TIM17_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
00906 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
00907 /**
00908   * @}
00909   */
00910
00911 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
00912   * @brief  Get the enable or disable status of the AHB peripheral clock.
00913   * @note   After reset, the peripheral clock (used for registers read/write access)
00914   *         is disabled and the application software has to enable this clock before
00915   *         using it.
00916   * @{
00917   */
00918 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED()         ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
00919 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED()         ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
00920 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED()         ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
00921 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()         ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
00922 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED()         ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
00923 #define __HAL_RCC_CRC_IS_CLK_ENABLED()           ((RCC->AHBENR & (RCC_AHBENR_CRCEN))   != RESET)
00924 #define __HAL_RCC_DMA1_IS_CLK_ENABLED()          ((RCC->AHBENR & (RCC_AHBENR_DMA1EN))  != RESET)
00925 #define __HAL_RCC_SRAM_IS_CLK_ENABLED()          ((RCC->AHBENR & (RCC_AHBENR_SRAMEN))  != RESET)
00926 #define __HAL_RCC_FLITF_IS_CLK_ENABLED()         ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
00927 #define __HAL_RCC_TSC_IS_CLK_ENABLED()           ((RCC->AHBENR & (RCC_AHBENR_TSCEN))   != RESET)
00928
00929 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED()        ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
00930 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED()        ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
00931 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED()        ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
00932 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED()        ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
00933 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED()        ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
00934 #define __HAL_RCC_CRC_IS_CLK_DISABLED()          ((RCC->AHBENR & (RCC_AHBENR_CRCEN))   == RESET)
00935 #define __HAL_RCC_DMA1_IS_CLK_DISABLED()         ((RCC->AHBENR & (RCC_AHBENR_DMA1EN))  == RESET)
00936 #define __HAL_RCC_SRAM_IS_CLK_DISABLED()         ((RCC->AHBENR & (RCC_AHBENR_SRAMEN))  == RESET)
00937 #define __HAL_RCC_FLITF_IS_CLK_DISABLED()        ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
00938 #define __HAL_RCC_TSC_IS_CLK_DISABLED()          ((RCC->AHBENR & (RCC_AHBENR_TSCEN))   == RESET)
00939 /**
00940   * @}
00941   */
00942
00943 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable  Status
00944   * @brief  Get the enable or disable status of the APB1 peripheral clock.
00945   * @note   After reset, the peripheral clock (used for registers read/write access)
00946   *         is disabled and the application software has to enable this clock before
00947   *         using it.
00948   * @{
00949   */
00950 #define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN))   != RESET)
00951 #define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN))   != RESET)
00952 #define __HAL_RCC_WWDG_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN))   != RESET)
00953 #define __HAL_RCC_USART2_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
00954 #define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
00955 #define __HAL_RCC_I2C1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN))   != RESET)
00956 #define __HAL_RCC_PWR_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_PWREN))    != RESET)
00957 #define __HAL_RCC_DAC1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN))   != RESET)
00958
00959 #define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN))   == RESET)
00960 #define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN))   == RESET)
00961 #define __HAL_RCC_WWDG_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN))   == RESET)
00962 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
00963 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
00964 #define __HAL_RCC_I2C1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN))   == RESET)
00965 #define __HAL_RCC_PWR_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_PWREN))    == RESET)
00966 #define __HAL_RCC_DAC1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN))   == RESET)
00967 /**
00968   * @}
00969   */
00970
00971 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
00972   * @brief  EGet the enable or disable status of the APB2 peripheral clock.
00973   * @note   After reset, the peripheral clock (used for registers read/write access)
00974   *         is disabled and the application software has to enable this clock before
00975   *         using it.
00976   * @{
00977   */
00978 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN))  != RESET)
00979 #define __HAL_RCC_TIM15_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN))   != RESET)
00980 #define __HAL_RCC_TIM16_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN))   != RESET)
00981 #define __HAL_RCC_TIM17_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN))   != RESET)
00982 #define __HAL_RCC_USART1_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN))  != RESET)
00983
00984 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN))  == RESET)
00985 #define __HAL_RCC_TIM15_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN))   == RESET)
00986 #define __HAL_RCC_TIM16_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN))   == RESET)
00987 #define __HAL_RCC_TIM17_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN))   == RESET)
00988 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN))  == RESET)
00989 /**
00990   * @}
00991   */
00992
00993 /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
00994   * @brief  Force or release AHB peripheral reset.
00995   * @{
00996   */
00997 #define __HAL_RCC_AHB_FORCE_RESET()     (RCC->AHBRSTR = 0xFFFFFFFFU)
00998 #define __HAL_RCC_GPIOA_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
00999 #define __HAL_RCC_GPIOB_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
01000 #define __HAL_RCC_GPIOC_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
01001 #define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
01002 #define __HAL_RCC_GPIOF_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
01003 #define __HAL_RCC_TSC_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
01004
01005 #define __HAL_RCC_AHB_RELEASE_RESET()   (RCC->AHBRSTR = 0x00000000U)
01006 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
01007 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
01008 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
01009 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
01010 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
01011 #define __HAL_RCC_TSC_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
01012 /**
01013   * @}
01014   */
01015
01016 /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
01017   * @brief  Force or release APB1 peripheral reset.
01018   * @{
01019   */
01020 #define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)
01021 #define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
01022 #define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
01023 #define __HAL_RCC_WWDG_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
01024 #define __HAL_RCC_USART2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
01025 #define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
01026 #define __HAL_RCC_I2C1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
01027 #define __HAL_RCC_PWR_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
01028 #define __HAL_RCC_DAC1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST))
01029
01030 #define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00000000U)
01031 #define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
01032 #define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
01033 #define __HAL_RCC_WWDG_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
01034 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
01035 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
01036 #define __HAL_RCC_I2C1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
01037 #define __HAL_RCC_PWR_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
01038 #define __HAL_RCC_DAC1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))
01039 /**
01040   * @}
01041   */
01042
01043 /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
01044   * @brief  Force or release APB2 peripheral reset.
01045   * @{
01046   */
01047 #define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)
01048 #define __HAL_RCC_SYSCFG_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
01049 #define __HAL_RCC_TIM15_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
01050 #define __HAL_RCC_TIM16_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
01051 #define __HAL_RCC_TIM17_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
01052 #define __HAL_RCC_USART1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
01053
01054 #define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00000000U)
01055 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
01056 #define __HAL_RCC_TIM15_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
01057 #define __HAL_RCC_TIM16_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
01058 #define __HAL_RCC_TIM17_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
01059 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
01060 /**
01061   * @}
01062   */
01063
01064 /** @defgroup RCC_HSI_Configuration HSI Configuration
01065   * @{
01066   */
01067
01068 /** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
01069   * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
01070   *         It is used (enabled by hardware) as system clock source after startup
01071   *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
01072   *         of the HSE used directly or indirectly as system clock (if the Clock
01073   *         Security System CSS is enabled).
01074   * @note   HSI can not be stopped if it is used as system clock source. In this case,
01075   *         you have to select another source of the system clock then stop the HSI.
01076   * @note   After enabling the HSI, the application software should wait on HSIRDY
01077   *         flag to be set indicating that HSI clock is stable and can be used as
01078   *         system clock source.
01079   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
01080   *         clock cycles.
01081   */
01082 #define __HAL_RCC_HSI_ENABLE()  (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
01083 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
01084
01085 /** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
01086   * @note   The calibration is used to compensate for the variations in voltage
01087   *         and temperature that influence the frequency of the internal HSI RC.
01088   * @param  _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
01089   *         (default is RCC_HSICALIBRATION_DEFAULT).
01090   *         This parameter must be a number between 0 and 0x1F.
01091   */
01092 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
01093           (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
01094
01095 /**
01096   * @}
01097   */
01098
01099 /** @defgroup RCC_LSI_Configuration  LSI Configuration
01100   * @{
01101   */
01102
01103 /** @brief Macro to enable the Internal Low Speed oscillator (LSI).
01104   * @note   After enabling the LSI, the application software should wait on
01105   *         LSIRDY flag to be set indicating that LSI clock is stable and can
01106   *         be used to clock the IWDG and/or the RTC.
01107   */
01108 #define __HAL_RCC_LSI_ENABLE()  (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
01109
01110 /** @brief Macro to disable the Internal Low Speed oscillator (LSI).
01111   * @note   LSI can not be disabled if the IWDG is running.
01112   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
01113   *         clock cycles.
01114   */
01115 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
01116
01117 /**
01118   * @}
01119   */
01120
01121 /** @defgroup RCC_HSE_Configuration HSE Configuration
01122   * @{
01123   */
01124
01125 /**
01126   * @brief  Macro to configure the External High Speed oscillator (HSE).
01127   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
01128   *         supported by this macro. User should request a transition to HSE Off
01129   *         first and then HSE On or HSE Bypass.
01130   * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
01131   *         software should wait on HSERDY flag to be set indicating that HSE clock
01132   *         is stable and can be used to clock the PLL and/or system clock.
01133   * @note   HSE state can not be changed if it is used directly or through the
01134   *         PLL as system clock. In this case, you have to select another source
01135   *         of the system clock then change the HSE state (ex. disable it).
01136   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
01137   * @note   This function reset the CSSON bit, so if the clock security system(CSS)
01138   *         was previously enabled you have to enable it again after calling this
01139   *         function.
01140   * @param  __STATE__ specifies the new state of the HSE.
01141   *          This parameter can be one of the following values:
01142   *            @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
01143   *                              6 HSE oscillator clock cycles.
01144   *            @arg @ref RCC_HSE_ON turn ON the HSE oscillator
01145   *            @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
01146   */
01147 #define __HAL_RCC_HSE_CONFIG(__STATE__)                                     \
01148                     do{                                                     \
01149                       if ((__STATE__) == RCC_HSE_ON)                        \
01150                       {                                                     \
01151                         SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
01152                       }                                                     \
01153                       else if ((__STATE__) == RCC_HSE_OFF)                  \
01154                       {                                                     \
01155                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
01156                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
01157                       }                                                     \
01158                       else if ((__STATE__) == RCC_HSE_BYPASS)               \
01159                       {                                                     \
01160                         SET_BIT(RCC->CR, RCC_CR_HSEBYP);                    \
01161                         SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
01162                       }                                                     \
01163                       else                                                  \
01164                       {                                                     \
01165                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
01166                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
01167                       }                                                     \
01168                     }while(0U)
01169
01170 /**
01171   * @}
01172   */
01173
01174 /** @defgroup RCC_LSE_Configuration LSE Configuration
01175   * @{
01176   */
01177
01178 /**
01179   * @brief  Macro to configure the External Low Speed oscillator (LSE).
01180   * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
01181   * @note   As the LSE is in the Backup domain and write access is denied to
01182   *         this domain after reset, you have to enable write access using
01183   *         @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
01184   *         (to be done once after reset).
01185   * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
01186   *         software should wait on LSERDY flag to be set indicating that LSE clock
01187   *         is stable and can be used to clock the RTC.
01188   * @param  __STATE__ specifies the new state of the LSE.
01189   *         This parameter can be one of the following values:
01190   *            @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
01191   *                              6 LSE oscillator clock cycles.
01192   *            @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
01193   *            @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
01194   */
01195 #define __HAL_RCC_LSE_CONFIG(__STATE__)                                     \
01196                     do{                                                     \
01197                       if ((__STATE__) == RCC_LSE_ON)                        \
01198                       {                                                     \
01199                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
01200                       }                                                     \
01201                       else if ((__STATE__) == RCC_LSE_OFF)                  \
01202                       {                                                     \
01203                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
01204                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
01205                       }                                                     \
01206                       else if ((__STATE__) == RCC_LSE_BYPASS)               \
01207                       {                                                     \
01208                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                  \
01209                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
01210                       }                                                     \
01211                       else                                                  \
01212                       {                                                     \
01213                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
01214                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
01215                       }                                                     \
01216                     }while(0U)
01217
01218 /**
01219   * @}
01220   */
01221
01222 /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
01223   * @{
01224   */
01225
01226 /** @brief  Macro to configure the USART1 clock (USART1CLK).
01227   * @param  __USART1CLKSOURCE__ specifies the USART1 clock source.
01228   *         This parameter can be one of the following values:
01229   @if STM32F302xC
01230   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
01231   @endif
01232   @if STM32F303xC
01233   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
01234   @endif
01235   @if STM32F358xx
01236   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
01237   @endif
01238   @if STM32F302xE
01239   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
01240   @endif
01241   @if STM32F303xE
01242   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
01243   @endif
01244   @if STM32F398xx
01245   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
01246   @endif
01247   @if STM32F373xC
01248   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
01249   @endif
01250   @if STM32F378xx
01251   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
01252   @endif
01253   @if STM32F301x8
01254   *            @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
01255   @endif
01256   @if STM32F302x8
01257   *            @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
01258   @endif
01259   @if STM32F318xx
01260   *            @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
01261   @endif
01262   @if STM32F303x8
01263   *            @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
01264   @endif
01265   @if STM32F334x8
01266   *            @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
01267   @endif
01268   @if STM32F328xx
01269   *            @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
01270   @endif
01271   *            @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
01272   *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
01273   *            @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
01274   */
01275 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \
01276                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__))
01277
01278 /** @brief  Macro to get the USART1 clock source.
01279   * @retval The clock source can be one of the following values:
01280   @if STM32F302xC
01281   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
01282   @endif
01283   @if STM32F303xC
01284   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
01285   @endif
01286   @if STM32F358xx
01287   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
01288   @endif
01289   @if STM32F302xE
01290   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
01291   @endif
01292   @if STM32F303xE
01293   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
01294   @endif
01295   @if STM32F398xx
01296   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
01297   @endif
01298   @if STM32F373xC
01299   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
01300   @endif
01301   @if STM32F378xx
01302   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
01303   @endif
01304   @if STM32F301x8
01305   *            @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
01306   @endif
01307   @if STM32F302x8
01308   *            @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
01309   @endif
01310   @if STM32F318xx
01311   *            @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
01312   @endif
01313   @if STM32F303x8
01314   *            @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
01315   @endif
01316   @if STM32F334x8
01317   *            @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
01318   @endif
01319   @if STM32F328xx
01320   *            @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
01321   @endif
01322   *            @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
01323   *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
01324   *            @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
01325   */
01326 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
01327
01328 #if defined(RCC_CFGR3_USART2SW)
01329 /** @brief  Macro to configure the USART2 clock (USART2CLK).
01330   * @param  __USART2CLKSOURCE__ specifies the USART2 clock source.
01331   *         This parameter can be one of the following values:
01332   *            @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
01333   *            @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
01334   *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
01335   *            @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
01336   */
01337 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \
01338                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__))
01339
01340 /** @brief  Macro to get the USART2 clock source.
01341   * @retval The clock source can be one of the following values:
01342   *            @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
01343   *            @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
01344   *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
01345   *            @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
01346   */
01347 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
01348 #endif /* RCC_CFGR3_USART2SW */
01349
01350 #if defined(RCC_CFGR3_USART3SW)
01351 /** @brief  Macro to configure the USART3 clock (USART3CLK).
01352   * @param  __USART3CLKSOURCE__ specifies the USART3 clock source.
01353   *         This parameter can be one of the following values:
01354   *            @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
01355   *            @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
01356   *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
01357   *            @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
01358   */
01359 #define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \
01360                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__))
01361
01362 /** @brief  Macro to get the USART3 clock source.
01363   * @retval The clock source can be one of the following values:
01364   *            @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
01365   *            @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
01366   *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
01367   *            @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
01368   */
01369 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
01370 #endif /* RCC_CFGR3_USART2SW */
01371 /**
01372   * @}
01373   */
01374
01375 /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
01376   * @{
01377   */
01378
01379 /** @brief  Macro to configure the I2C1 clock (I2C1CLK).
01380   * @param  __I2C1CLKSOURCE__ specifies the I2C1 clock source.
01381   *         This parameter can be one of the following values:
01382   *            @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
01383   *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
01384   */
01385 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \
01386                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__))
01387
01388 /** @brief  Macro to get the I2C1 clock source.
01389   * @retval The clock source can be one of the following values:
01390   *            @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
01391   *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
01392   */
01393 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
01394 /**
01395   * @}
01396   */
01397
01398 /** @defgroup RCC_PLL_Configuration PLL Configuration
01399   * @{
01400   */
01401
01402 /** @brief Macro to enable the main PLL.
01403   * @note   After enabling the main PLL, the application software should wait on
01404   *         PLLRDY flag to be set indicating that PLL clock is stable and can
01405   *         be used as system clock source.
01406   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
01407   */
01408 #define __HAL_RCC_PLL_ENABLE()          (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
01409
01410 /** @brief Macro to disable the main PLL.
01411   * @note   The main PLL can not be disabled if it is used as system clock source
01412   */
01413 #define __HAL_RCC_PLL_DISABLE()         (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
01414
01415
01416 /** @brief  Get oscillator clock selected as PLL input clock
01417   * @retval The clock source used for PLL entry. The returned value can be one
01418   *         of the following:
01419   *             @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
01420   *             @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
01421   */
01422 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
01423
01424 /**
01425   * @}
01426   */
01427
01428 /** @defgroup RCC_Get_Clock_source Get Clock source
01429   * @{
01430   */
01431
01432 /**
01433   * @brief  Macro to configure the system clock source.
01434   * @param  __SYSCLKSOURCE__ specifies the system clock source.
01435   *          This parameter can be one of the following values:
01436   *              @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
01437   *              @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
01438   *              @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
01439   */
01440 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
01441                   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
01442
01443 /** @brief  Macro to get the clock source used as system clock.
01444   * @retval The clock source used as system clock. The returned value can be one
01445   *         of the following:
01446   *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
01447   *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
01448   *             @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
01449   */
01450 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
01451
01452 /**
01453   * @}
01454   */
01455
01456 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
01457   * @{
01458   */
01459
01460 #if defined(RCC_CFGR_MCOPRE)
01461 /** @brief  Macro to configure the MCO clock.
01462   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
01463   *          This parameter can be one of the following values:
01464   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK      No clock selected as MCO clock
01465   *            @arg @ref RCC_MCO1SOURCE_SYSCLK       System Clock selected as MCO clock
01466   *            @arg @ref RCC_MCO1SOURCE_HSI          HSI oscillator clock selected as MCO clock
01467   *            @arg @ref RCC_MCO1SOURCE_HSE          HSE selected as MCO clock
01468   *            @arg @ref RCC_MCO1SOURCE_LSI          LSI selected as MCO clock
01469   *            @arg @ref RCC_MCO1SOURCE_LSE          LSE selected as MCO clock
01470   *            @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2  PLLCLK Divided by 2 selected as MCO clock
01471   * @param  __MCODIV__ specifies the MCO clock prescaler.
01472   *          This parameter can be one of the following values:
01473   *            @arg @ref RCC_MCODIV_1   MCO clock source is divided by 1
01474   *            @arg @ref RCC_MCODIV_2   MCO clock source is divided by 2
01475   *            @arg @ref RCC_MCODIV_4   MCO clock source is divided by 4
01476   *            @arg @ref RCC_MCODIV_8   MCO clock source is divided by 8
01477   *            @arg @ref RCC_MCODIV_16  MCO clock source is divided by 16
01478   *            @arg @ref RCC_MCODIV_32  MCO clock source is divided by 32
01479   *            @arg @ref RCC_MCODIV_64  MCO clock source is divided by 64
01480   *            @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128
01481   */
01482 #else
01483 /** @brief  Macro to configure the MCO clock.
01484   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
01485   *         This parameter can be one of the following values:
01486   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK     No clock selected as MCO clock
01487   *            @arg @ref RCC_MCO1SOURCE_SYSCLK      System Clock selected as MCO clock
01488   *            @arg @ref RCC_MCO1SOURCE_HSI         HSI selected as MCO clock
01489   *            @arg @ref RCC_MCO1SOURCE_HSE         HSE selected as MCO clock
01490   *            @arg @ref RCC_MCO1SOURCE_LSI         LSI selected as MCO clock
01491   *            @arg @ref RCC_MCO1SOURCE_LSE         LSE selected as MCO clock
01492   *            @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
01493   * @param  __MCODIV__ specifies the MCO clock prescaler.
01494   *         This parameter can be one of the following values:
01495   *            @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
01496   */
01497 #endif
01498 #if   defined(RCC_CFGR_MCOPRE)
01499 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
01500                  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
01501 #else
01502
01503 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
01504                  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
01505
01506 #endif
01507
01508 /**
01509   * @}
01510   */
01511
01512   /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
01513   * @{
01514   */
01515
01516 /** @brief Macro to configure the RTC clock (RTCCLK).
01517   * @note   As the RTC clock configuration bits are in the Backup domain and write
01518   *         access is denied to this domain after reset, you have to enable write
01519   *         access using the Power Backup Access macro before to configure
01520   *         the RTC clock source (to be done once after reset).
01521   * @note   Once the RTC clock is configured it cannot be changed unless the
01522   *         Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
01523   *         a Power On Reset (POR).
01524   *
01525   * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.
01526   *          This parameter can be one of the following values:
01527   *             @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
01528   *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
01529   *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
01530   *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
01531   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
01532   *         work in STOP and STANDBY modes, and can be used as wakeup source.
01533   *         However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
01534   *         the RTC cannot be used in STOP and STANDBY modes.
01535   * @note   The system must always be configured so as to get a PCLK frequency greater than or
01536   *             equal to the RTCCLK frequency for a proper operation of the RTC.
01537   */
01538 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
01539
01540 /** @brief Macro to get the RTC clock source.
01541   * @retval The clock source can be one of the following values:
01542   *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
01543   *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
01544   *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
01545   *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
01546   */
01547 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
01548
01549 /** @brief Macro to enable the the RTC clock.
01550   * @note   These macros must be used only after the RTC clock source was selected.
01551   */
01552 #define __HAL_RCC_RTC_ENABLE()          (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
01553
01554 /** @brief Macro to disable the the RTC clock.
01555   * @note  These macros must be used only after the RTC clock source was selected.
01556   */
01557 #define __HAL_RCC_RTC_DISABLE()         (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
01558
01559 /** @brief  Macro to force the Backup domain reset.
01560   * @note   This function resets the RTC peripheral (including the backup registers)
01561   *         and the RTC clock source selection in RCC_BDCR register.
01562   */
01563 #define __HAL_RCC_BACKUPRESET_FORCE()   (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
01564
01565 /** @brief  Macros to release the Backup domain reset.
01566   */
01567 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
01568
01569 /**
01570   * @}
01571   */
01572
01573 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
01574   * @brief macros to manage the specified RCC Flags and interrupts.
01575   * @{
01576   */
01577
01578 /** @brief Enable RCC interrupt.
01579   * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
01580   *          This parameter can be any combination of the following values:
01581   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
01582   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
01583   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
01584   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
01585   *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
01586   */
01587 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
01588
01589 /** @brief Disable RCC interrupt.
01590   * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
01591   *          This parameter can be any combination of the following values:
01592   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
01593   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
01594   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
01595   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
01596   *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
01597   */
01598 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
01599
01600 /** @brief Clear the RCC's interrupt pending bits.
01601   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
01602   *          This parameter can be any combination of the following values:
01603   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
01604   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
01605   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
01606   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
01607   *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
01608   *            @arg @ref RCC_IT_CSS Clock Security System interrupt
01609   */
01610 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
01611
01612 /** @brief Check the RCC's interrupt has occurred or not.
01613   * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
01614   *          This parameter can be one of the following values:
01615   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
01616   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
01617   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
01618   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
01619   *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
01620   *            @arg @ref RCC_IT_CSS Clock Security System interrupt
01621   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
01622   */
01623 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
01624
01625 /** @brief Set RMVF bit to clear the reset flags.
01626   *         The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
01627   *         RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
01628   */
01629 #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
01630
01631 /** @brief  Check RCC flag is set or not.
01632   * @param  __FLAG__ specifies the flag to check.
01633   *          This parameter can be one of the following values:
01634   *            @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
01635   *            @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
01636   *            @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
01637   *            @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
01638   *            @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
01639   *            @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
01640   *            @arg @ref RCC_FLAG_PINRST  Pin reset.
01641   *            @arg @ref RCC_FLAG_PORRST  POR/PDR reset.
01642   *            @arg @ref RCC_FLAG_SFTRST  Software reset.
01643   *            @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
01644   *            @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
01645   *            @arg @ref RCC_FLAG_LPWRRST Low Power reset.
01646   @if defined(STM32F301x8)
01647   *            @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
01648   @endif
01649   @if defined(STM32F302x8)
01650   *            @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
01651   @endif
01652   @if defined(STM32F302xC)
01653   *            @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
01654   *            @arg @ref RCC_FLAG_MCO       Microcontroller Clock Output
01655   @endif
01656   @if defined(STM32F302xE)
01657   *            @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
01658   @endif
01659   @if defined(STM32F303x8)
01660   *            @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
01661   @endif
01662   @if defined(STM32F303xC)
01663   *            @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
01664   *            @arg @ref RCC_FLAG_MCO       Microcontroller Clock Output
01665   @endif
01666   @if defined(STM32F303xE)
01667   *            @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
01668   @endif
01669   @if defined(STM32F334x8)
01670   *            @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
01671   @endif
01672   @if defined(STM32F358xx)
01673   *            @arg @ref RCC_FLAG_MCO       Microcontroller Clock Output
01674   @endif
01675   @if defined(STM32F373xC)
01676   *            @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
01677   @endif
01678   * @retval The new state of __FLAG__ (TRUE or FALSE).
01679   */
01680 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)  ? RCC->CR   : \
01681                                        (((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
01682                                        (((__FLAG__) >> 5U) == CFGR_REG_INDEX)? RCC->CFGR : \
01683                                                                               RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
01684
01685 /**
01686   * @}
01687   */
01688
01689 /**
01690   * @}
01691   */
01692
01693 /* Include RCC HAL Extension module */
01694 #include "stm32f3xx_hal_rcc_ex.h"
01695
01696 /* Exported functions --------------------------------------------------------*/
01697 /** @addtogroup RCC_Exported_Functions
01698   * @{
01699   */
01700
01701 /** @addtogroup RCC_Exported_Functions_Group1
01702   * @{
01703   */
01704
01705 /* Initialization and de-initialization functions  ******************************/
01706 void              HAL_RCC_DeInit(void);
01707 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
01708 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency);
01709
01710 /**
01711   * @}
01712   */
01713
01714 /** @addtogroup RCC_Exported_Functions_Group2
01715   * @{
01716   */
01717
01718 /* Peripheral Control functions  ************************************************/
01719 void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
01720 void              HAL_RCC_EnableCSS(void);
01721 /* CSS NMI IRQ handler */
01722 void              HAL_RCC_NMI_IRQHandler(void);
01723 /* User Callbacks in non blocking mode (IT mode) */
01724 void              HAL_RCC_CSSCallback(void);
01725 void              HAL_RCC_DisableCSS(void);
01726 uint32_t          HAL_RCC_GetSysClockFreq(void);
01727 uint32_t          HAL_RCC_GetHCLKFreq(void);
01728 uint32_t          HAL_RCC_GetPCLK1Freq(void);
01729 uint32_t          HAL_RCC_GetPCLK2Freq(void);
01730 void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
01731 void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency);
01732
01733 /**
01734   * @}
01735   */
01736
01737 /**
01738   * @}
01739   */
01740
01741 /**
01742   * @}
01743   */
01744
01745 /**
01746   * @}
01747   */
01748
01749 #ifdef __cplusplus
01750 }
01751 #endif
01752
01753 #endif /* __STM32F3xx_HAL_RCC_H */
01754
01755 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
01756
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_rcc_ex.c Source File

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stm32f3xx_hal_rcc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_rcc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended RCC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities RCC extension peripheral:
00008   *           + Extended Peripheral Control functions
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00014   *
00015   * Redistribution and use in source and binary forms, with or without modification,
00016   * are permitted provided that the following conditions are met:
00017   *   1. Redistributions of source code must retain the above copyright notice,
00018   *      this list of conditions and the following disclaimer.
00019   *   2. Redistributions in binary form must reproduce the above copyright notice,
00020   *      this list of conditions and the following disclaimer in the documentation
00021   *      and/or other materials provided with the distribution.
00022   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00023   *      may be used to endorse or promote products derived from this software
00024   *      without specific prior written permission.
00025   *
00026   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00027   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00028   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00029   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00030   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00031   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00032   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00033   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00034   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00035   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00036   *
00037   ******************************************************************************
00038   */
00039
00040 /* Includes ------------------------------------------------------------------*/
00041 #include "stm32f3xx_hal.h"
00042
00043 /** @addtogroup STM32F3xx_HAL_Driver
00044   * @{
00045   */
00046
00047 #ifdef HAL_RCC_MODULE_ENABLED
00048
00049 /** @defgroup RCCEx RCCEx
00050   * @brief RCC Extension HAL module driver.
00051   * @{
00052   */
00053
00054 /* Private typedef -----------------------------------------------------------*/
00055 /* Private define ------------------------------------------------------------*/
00056 /* Private macro -------------------------------------------------------------*/
00057 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
00058  * @{
00059  */
00060 /**
00061   * @}
00062   */
00063
00064 /* Private variables ---------------------------------------------------------*/
00065 /* Private function prototypes -----------------------------------------------*/
00066 /* Private functions ---------------------------------------------------------*/
00067 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \
00068  || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW)     \
00069  || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW)  \
00070  || defined(RCC_CFGR3_HRTIM1SW)
00071 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
00072   * @{
00073   */
00074 static uint32_t RCC_GetPLLCLKFreq(void);
00075
00076 /**
00077   * @}
00078   */
00079 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */
00080
00081 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
00082   * @{
00083   */
00084
00085 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
00086   * @brief    Extended Peripheral Control functions
00087   *
00088 @verbatim
00089  ===============================================================================
00090                 ##### Extended Peripheral Control functions  #####
00091  ===============================================================================
00092     [..]
00093     This subsection provides a set of functions allowing to control the RCC Clocks
00094     frequencies.
00095     [..]
00096     (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
00097         select the RTC clock source; in this case the Backup domain will be reset in
00098         order to modify the RTC Clock source, as consequence RTC registers (including
00099         the backup registers) are set to their reset values.
00100
00101 @endverbatim
00102   * @{
00103   */
00104
00105 /**
00106   * @brief  Initializes the RCC extended peripherals clocks according to the specified
00107   *         parameters in the RCC_PeriphCLKInitTypeDef.
00108   * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
00109   *         contains the configuration information for the Extended Peripherals clocks
00110   *         (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB).
00111   *
00112   * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
00113   *         the RTC clock source; in this case the Backup domain will be reset in
00114   *         order to modify the RTC Clock source, as consequence RTC registers (including
00115   *         the backup registers) and RCC_BDCR register are set to their reset values.
00116   *
00117   * @retval HAL status
00118   */
00119 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00120 {
00121   uint32_t tickstart = 0U;
00122   uint32_t temp_reg = 0U;
00123
00124   /* Check the parameters */
00125   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
00126
00127   /*---------------------------- RTC configuration -------------------------------*/
00128   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
00129   {
00130     /* check for RTC Parameters used to output RTCCLK */
00131     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
00132
00133     FlagStatus       pwrclkchanged = RESET;
00134
00135     /* As soon as function is called to change RTC clock source, activation of the
00136        power domain is done. */
00137     /* Requires to enable write access to Backup Domain of necessary */
00138     if(__HAL_RCC_PWR_IS_CLK_DISABLED())
00139     {
00140       __HAL_RCC_PWR_CLK_ENABLE();
00141       pwrclkchanged = SET;
00142     }
00143
00144     if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
00145     {
00146       /* Enable write access to Backup domain */
00147       SET_BIT(PWR->CR, PWR_CR_DBP);
00148
00149       /* Wait for Backup domain Write protection disable */
00150       tickstart = HAL_GetTick();
00151
00152       while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
00153       {
00154           if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
00155         {
00156           return HAL_TIMEOUT;
00157         }
00158       }
00159     }
00160
00161     /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
00162     temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
00163     if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
00164     {
00165       /* Store the content of BDCR register before the reset of Backup Domain */
00166       temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
00167       /* RTC Clock selection can be changed only if the Backup Domain is reset */
00168       __HAL_RCC_BACKUPRESET_FORCE();
00169       __HAL_RCC_BACKUPRESET_RELEASE();
00170       /* Restore the Content of BDCR register */
00171       RCC->BDCR = temp_reg;
00172
00173       /* Wait for LSERDY if LSE was enabled */
00174       if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
00175       {
00176         /* Get Start Tick */
00177         tickstart = HAL_GetTick();
00178
00179         /* Wait till LSE is ready */
00180         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
00181         {
00182             if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
00183           {
00184             return HAL_TIMEOUT;
00185           }
00186         }
00187       }
00188     }
00189     __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
00190
00191     /* Require to disable power clock if necessary */
00192     if(pwrclkchanged == SET)
00193     {
00194       __HAL_RCC_PWR_CLK_DISABLE();
00195     }
00196   }
00197
00198   /*------------------------------- USART1 Configuration ------------------------*/
00199   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
00200   {
00201     /* Check the parameters */
00202     assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
00203
00204     /* Configure the USART1 clock source */
00205     __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
00206   }
00207
00208 #if defined(RCC_CFGR3_USART2SW)
00209   /*----------------------------- USART2 Configuration --------------------------*/
00210   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
00211   {
00212     /* Check the parameters */
00213     assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
00214
00215     /* Configure the USART2 clock source */
00216     __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
00217   }
00218 #endif /* RCC_CFGR3_USART2SW */
00219
00220 #if defined(RCC_CFGR3_USART3SW)
00221   /*------------------------------ USART3 Configuration ------------------------*/
00222   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
00223   {
00224     /* Check the parameters */
00225     assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
00226
00227     /* Configure the USART3 clock source */
00228     __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
00229   }
00230 #endif /* RCC_CFGR3_USART3SW */
00231
00232   /*------------------------------ I2C1 Configuration ------------------------*/
00233   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
00234   {
00235     /* Check the parameters */
00236     assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
00237
00238     /* Configure the I2C1 clock source */
00239     __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
00240   }
00241
00242 #if defined(STM32F302xE) || defined(STM32F303xE)\
00243  || defined(STM32F302xC) || defined(STM32F303xC)\
00244  || defined(STM32F302x8)                        \
00245  || defined(STM32F373xC)
00246   /*------------------------------ USB Configuration ------------------------*/
00247   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
00248   {
00249     /* Check the parameters */
00250     assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection));
00251
00252     /* Configure the USB clock source */
00253     __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection);
00254   }
00255
00256 #endif /* STM32F302xE || STM32F303xE || */
00257        /* STM32F302xC || STM32F303xC || */
00258        /* STM32F302x8                || */
00259        /* STM32F373xC                   */
00260
00261 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
00262  || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
00263  || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
00264  || defined(STM32F373xC) || defined(STM32F378xx)
00265
00266   /*------------------------------ I2C2 Configuration ------------------------*/
00267   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
00268   {
00269     /* Check the parameters */
00270     assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
00271
00272     /* Configure the I2C2 clock source */
00273     __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
00274   }
00275
00276 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00277        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00278        /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
00279        /* STM32F373xC || STM32F378xx                   */
00280
00281 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
00282  || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00283
00284   /*------------------------------ I2C3 Configuration ------------------------*/
00285   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
00286   {
00287     /* Check the parameters */
00288     assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
00289
00290     /* Configure the I2C3 clock source */
00291     __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
00292   }
00293 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00294        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00295
00296 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
00297  || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
00298
00299   /*------------------------------ UART4 Configuration ------------------------*/
00300   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
00301   {
00302     /* Check the parameters */
00303     assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
00304
00305     /* Configure the UART4 clock source */
00306     __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
00307   }
00308
00309   /*------------------------------ UART5 Configuration ------------------------*/
00310   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
00311   {
00312     /* Check the parameters */
00313     assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
00314
00315     /* Configure the UART5 clock source */
00316     __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
00317   }
00318
00319 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00320        /* STM32F302xC || STM32F303xC || STM32F358xx    */
00321
00322 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
00323  || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
00324  || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00325   /*------------------------------ I2S Configuration ------------------------*/
00326   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
00327   {
00328     /* Check the parameters */
00329     assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
00330
00331     /* Configure the I2S clock source */
00332     __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
00333   }
00334
00335 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00336        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00337        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00338
00339 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00340
00341   /*------------------------------ ADC1 clock Configuration ------------------*/
00342   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
00343   {
00344     /* Check the parameters */
00345     assert_param(IS_RCC_ADC1PLLCLK_DIV(PeriphClkInit->Adc1ClockSelection));
00346
00347     /* Configure the ADC1 clock source */
00348     __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
00349   }
00350
00351 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
00352
00353 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
00354  || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
00355  || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
00356
00357   /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/
00358   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
00359   {
00360     /* Check the parameters */
00361     assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection));
00362
00363     /* Configure the ADC12 clock source */
00364     __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
00365   }
00366
00367 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00368        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00369        /* STM32F303x8 || STM32F334x8 || STM32F328xx    */
00370
00371 #if defined(STM32F303xE) || defined(STM32F398xx)\
00372  || defined(STM32F303xC) || defined(STM32F358xx)
00373
00374   /*------------------------------ ADC3 & ADC4 clock Configuration -------------*/
00375   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC34) == RCC_PERIPHCLK_ADC34)
00376   {
00377     /* Check the parameters */
00378     assert_param(IS_RCC_ADC34PLLCLK_DIV(PeriphClkInit->Adc34ClockSelection));
00379
00380     /* Configure the ADC34 clock source */
00381     __HAL_RCC_ADC34_CONFIG(PeriphClkInit->Adc34ClockSelection);
00382   }
00383
00384 #endif /* STM32F303xE || STM32F398xx || */
00385        /* STM32F303xC || STM32F358xx    */
00386
00387 #if defined(STM32F373xC) || defined(STM32F378xx)
00388
00389   /*------------------------------ ADC1 clock Configuration ------------------*/
00390   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
00391   {
00392     /* Check the parameters */
00393     assert_param(IS_RCC_ADC1PCLK2_DIV(PeriphClkInit->Adc1ClockSelection));
00394
00395     /* Configure the ADC1 clock source */
00396     __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
00397   }
00398
00399 #endif /* STM32F373xC || STM32F378xx */
00400
00401 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
00402  || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
00403  || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
00404  || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00405
00406   /*------------------------------ TIM1 clock Configuration ----------------*/
00407   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
00408   {
00409     /* Check the parameters */
00410     assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
00411
00412     /* Configure the TIM1 clock source */
00413     __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
00414   }
00415
00416 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00417        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00418        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00419        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00420
00421 #if defined(STM32F303xE) || defined(STM32F398xx)\
00422  || defined(STM32F303xC) || defined(STM32F358xx)
00423
00424   /*------------------------------ TIM8 clock Configuration ----------------*/
00425   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM8) == RCC_PERIPHCLK_TIM8)
00426   {
00427     /* Check the parameters */
00428     assert_param(IS_RCC_TIM8CLKSOURCE(PeriphClkInit->Tim8ClockSelection));
00429
00430     /* Configure the TIM8 clock source */
00431     __HAL_RCC_TIM8_CONFIG(PeriphClkInit->Tim8ClockSelection);
00432   }
00433
00434 #endif /* STM32F303xE || STM32F398xx || */
00435        /* STM32F303xC || STM32F358xx    */
00436
00437 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00438
00439   /*------------------------------ TIM15 clock Configuration ----------------*/
00440   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
00441   {
00442     /* Check the parameters */
00443     assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
00444
00445     /* Configure the TIM15 clock source */
00446     __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
00447   }
00448
00449   /*------------------------------ TIM16 clock Configuration ----------------*/
00450   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
00451   {
00452     /* Check the parameters */
00453     assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
00454
00455     /* Configure the TIM16 clock source */
00456     __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
00457   }
00458
00459   /*------------------------------ TIM17 clock Configuration ----------------*/
00460   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
00461   {
00462     /* Check the parameters */
00463     assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
00464
00465     /* Configure the TIM17 clock source */
00466     __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
00467   }
00468
00469 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
00470
00471 #if defined(STM32F334x8)
00472
00473   /*------------------------------ HRTIM1 clock Configuration ----------------*/
00474   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
00475   {
00476     /* Check the parameters */
00477     assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
00478
00479     /* Configure the HRTIM1 clock source */
00480     __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
00481   }
00482
00483 #endif /* STM32F334x8 */
00484
00485 #if defined(STM32F373xC) || defined(STM32F378xx)
00486
00487   /*------------------------------ SDADC clock Configuration -------------------*/
00488   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDADC) == RCC_PERIPHCLK_SDADC)
00489   {
00490     /* Check the parameters */
00491     assert_param(IS_RCC_SDADCSYSCLK_DIV(PeriphClkInit->SdadcClockSelection));
00492
00493     /* Configure the SDADC clock prescaler */
00494     __HAL_RCC_SDADC_CONFIG(PeriphClkInit->SdadcClockSelection);
00495   }
00496
00497   /*------------------------------ CEC clock Configuration -------------------*/
00498   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
00499   {
00500     /* Check the parameters */
00501     assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
00502
00503     /* Configure the CEC clock source */
00504     __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
00505   }
00506
00507 #endif /* STM32F373xC || STM32F378xx */
00508
00509 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
00510
00511   /*------------------------------ TIM2 clock Configuration -------------------*/
00512   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM2) == RCC_PERIPHCLK_TIM2)
00513   {
00514     /* Check the parameters */
00515     assert_param(IS_RCC_TIM2CLKSOURCE(PeriphClkInit->Tim2ClockSelection));
00516
00517     /* Configure the CEC clock source */
00518     __HAL_RCC_TIM2_CONFIG(PeriphClkInit->Tim2ClockSelection);
00519   }
00520
00521   /*------------------------------ TIM3 clock Configuration -------------------*/
00522   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM34) == RCC_PERIPHCLK_TIM34)
00523   {
00524     /* Check the parameters */
00525     assert_param(IS_RCC_TIM3CLKSOURCE(PeriphClkInit->Tim34ClockSelection));
00526
00527     /* Configure the CEC clock source */
00528     __HAL_RCC_TIM34_CONFIG(PeriphClkInit->Tim34ClockSelection);
00529   }
00530
00531   /*------------------------------ TIM15 clock Configuration ------------------*/
00532   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
00533   {
00534     /* Check the parameters */
00535     assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
00536
00537     /* Configure the CEC clock source */
00538     __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
00539   }
00540
00541   /*------------------------------ TIM16 clock Configuration ------------------*/
00542   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
00543   {
00544     /* Check the parameters */
00545     assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
00546
00547     /* Configure the CEC clock source */
00548     __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
00549   }
00550
00551   /*------------------------------ TIM17 clock Configuration ------------------*/
00552   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
00553   {
00554     /* Check the parameters */
00555     assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
00556
00557     /* Configure the CEC clock source */
00558     __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
00559   }
00560
00561 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
00562
00563 #if defined(STM32F303xE) || defined(STM32F398xx)
00564   /*------------------------------ TIM20 clock Configuration ------------------*/
00565   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM20) == RCC_PERIPHCLK_TIM20)
00566   {
00567     /* Check the parameters */
00568     assert_param(IS_RCC_TIM20CLKSOURCE(PeriphClkInit->Tim20ClockSelection));
00569
00570     /* Configure the CEC clock source */
00571     __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection);
00572   }
00573 #endif /* STM32F303xE || STM32F398xx */
00574
00575
00576   return HAL_OK;
00577 }
00578
00579 /**
00580   * @brief  Get the RCC_ClkInitStruct according to the internal
00581   * RCC configuration registers.
00582   * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
00583   *         returns the configuration information for the Extended Peripherals clocks
00584   *         (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB clocks).
00585   * @retval None
00586   */
00587 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00588 {
00589   /* Set all possible values for the extended clock type parameter------------*/
00590   /* Common part first */
00591 #if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW)
00592   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
00593                                         RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_RTC;
00594 #else
00595   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | \
00596                                         RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_RTC;
00597 #endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
00598
00599   /* Get the RTC configuration --------------------------------------------*/
00600   PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
00601   /* Get the USART1 clock configuration --------------------------------------------*/
00602   PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
00603 #if defined(RCC_CFGR3_USART2SW)
00604   /* Get the USART2 clock configuration -----------------------------------------*/
00605   PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
00606 #endif /* RCC_CFGR3_USART2SW */
00607 #if defined(RCC_CFGR3_USART3SW)
00608    /* Get the USART3 clock configuration -----------------------------------------*/
00609   PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
00610 #endif /* RCC_CFGR3_USART3SW */
00611   /* Get the I2C1 clock configuration -----------------------------------------*/
00612   PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
00613
00614 #if defined(STM32F302xE) || defined(STM32F303xE)\
00615     || defined(STM32F302xC) || defined(STM32F303xC)\
00616     || defined(STM32F302x8)                        \
00617     || defined(STM32F373xC)
00618
00619   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
00620   /* Get the USB clock configuration -----------------------------------------*/
00621   PeriphClkInit->USBClockSelection = __HAL_RCC_GET_USB_SOURCE();
00622
00623 #endif /* STM32F302xE || STM32F303xE || */
00624        /* STM32F302xC || STM32F303xC || */
00625        /* STM32F302x8                || */
00626        /* STM32F373xC                   */
00627
00628 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
00629     || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
00630     || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
00631     || defined(STM32F373xC) || defined(STM32F378xx)
00632
00633   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C2;
00634   /* Get the I2C2 clock configuration -----------------------------------------*/
00635   PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
00636
00637 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00638        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00639        /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
00640        /* STM32F373xC || STM32F378xx                   */
00641
00642 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
00643     || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00644
00645   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3;
00646   /* Get the I2C3 clock configuration -----------------------------------------*/
00647   PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
00648
00649 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00650        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00651
00652 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
00653     || defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx)
00654
00655   PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5);
00656   /* Get the UART4 clock configuration -----------------------------------------*/
00657   PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
00658   /* Get the UART5 clock configuration -----------------------------------------*/
00659   PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
00660
00661 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00662        /* STM32F302xC || STM32F303xC || STM32F358xx */
00663
00664 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
00665     || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
00666     || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00667
00668   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S;
00669   /* Get the I2S clock configuration -----------------------------------------*/
00670   PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE();
00671
00672 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00673        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00674        /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
00675
00676 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
00677     || defined(STM32F373xC) || defined(STM32F378xx)
00678
00679   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC1;
00680   /* Get the ADC1 clock configuration -----------------------------------------*/
00681   PeriphClkInit->Adc1ClockSelection = __HAL_RCC_GET_ADC1_SOURCE();
00682
00683 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
00684        /* STM32F373xC || STM32F378xx                   */
00685
00686 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
00687     || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
00688     || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
00689
00690   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC12;
00691   /* Get the ADC1 & ADC2 clock configuration -----------------------------------------*/
00692   PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE();
00693
00694 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00695        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00696        /* STM32F303x8 || STM32F334x8 || STM32F328xx    */
00697
00698 #if defined(STM32F303xE) || defined(STM32F398xx)\
00699     || defined(STM32F303xC) || defined(STM32F358xx)
00700
00701   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC34;
00702    /* Get the ADC3 & ADC4 clock configuration -----------------------------------------*/
00703   PeriphClkInit->Adc34ClockSelection = __HAL_RCC_GET_ADC34_SOURCE();
00704
00705 #endif /* STM32F303xE || STM32F398xx || */
00706        /* STM32F303xC || STM32F358xx    */
00707
00708 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
00709     || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
00710     || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
00711     || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00712
00713   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM1;
00714   /* Get the TIM1 clock configuration -----------------------------------------*/
00715   PeriphClkInit->Tim1ClockSelection = __HAL_RCC_GET_TIM1_SOURCE();
00716
00717 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00718        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00719        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00720        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00721
00722 #if defined(STM32F303xE) || defined(STM32F398xx)\
00723     || defined(STM32F303xC) || defined(STM32F358xx)
00724
00725   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM8;
00726   /* Get the TIM8 clock configuration -----------------------------------------*/
00727   PeriphClkInit->Tim8ClockSelection = __HAL_RCC_GET_TIM8_SOURCE();
00728
00729 #endif /* STM32F303xE || STM32F398xx || */
00730        /* STM32F303xC || STM32F358xx    */
00731
00732 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00733
00734   PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17);
00735   /* Get the TIM15 clock configuration -----------------------------------------*/
00736   PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
00737   /* Get the TIM16 clock configuration -----------------------------------------*/
00738   PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE();
00739   /* Get the TIM17 clock configuration -----------------------------------------*/
00740   PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
00741
00742 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
00743
00744 #if defined(STM32F334x8)
00745
00746   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
00747   /* Get the HRTIM1 clock configuration -----------------------------------------*/
00748   PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE();
00749
00750 #endif /* STM32F334x8 */
00751
00752 #if defined(STM32F373xC) || defined(STM32F378xx)
00753
00754   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDADC;
00755   /* Get the SDADC clock configuration -----------------------------------------*/
00756   PeriphClkInit->SdadcClockSelection = __HAL_RCC_GET_SDADC_SOURCE();
00757
00758   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
00759   /* Get the CEC clock configuration -----------------------------------------*/
00760   PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
00761
00762 #endif /* STM32F373xC || STM32F378xx */
00763
00764 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
00765
00766   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM2;
00767   /* Get the TIM2 clock configuration -----------------------------------------*/
00768   PeriphClkInit->Tim2ClockSelection = __HAL_RCC_GET_TIM2_SOURCE();
00769
00770   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM34;
00771   /* Get the TIM3 clock configuration -----------------------------------------*/
00772   PeriphClkInit->Tim34ClockSelection = __HAL_RCC_GET_TIM34_SOURCE();
00773
00774   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM15;
00775   /* Get the TIM15 clock configuration -----------------------------------------*/
00776   PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
00777
00778   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM16;
00779   /* Get the TIM16 clock configuration -----------------------------------------*/
00780   PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE();
00781
00782   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM17;
00783   /* Get the TIM17 clock configuration -----------------------------------------*/
00784   PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
00785
00786 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
00787
00788 #if defined (STM32F303xE) || defined(STM32F398xx)
00789   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM20;
00790   /* Get the TIM20 clock configuration -----------------------------------------*/
00791   PeriphClkInit->Tim20ClockSelection = __HAL_RCC_GET_TIM20_SOURCE();
00792 #endif /* STM32F303xE || STM32F398xx */
00793 }
00794
00795 /**
00796   * @brief  Returns the peripheral clock frequency
00797   * @note   Returns 0 if peripheral clock is unknown or 0xDEADDEAD if not applicable.
00798   * @param  PeriphClk Peripheral clock identifier
00799   *         This parameter can be one of the following values:
00800   *            @arg @ref RCC_PERIPHCLK_RTC     RTC peripheral clock
00801   *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock
00802   *            @arg @ref RCC_PERIPHCLK_I2C1    I2C1 peripheral clock
00803   @if STM32F301x8
00804   *            @arg @ref RCC_PERIPHCLK_I2C2    I2C2 peripheral clock
00805   *            @arg @ref RCC_PERIPHCLK_I2C3    I2C3 peripheral clock
00806   *            @arg @ref RCC_PERIPHCLK_I2S     I2S peripheral clock
00807   *            @arg @ref RCC_PERIPHCLK_ADC1    ADC1 peripheral clock
00808   *            @arg @ref RCC_PERIPHCLK_TIM1    TIM1 peripheral clock
00809   *            @arg @ref RCC_PERIPHCLK_TIM15   TIM15 peripheral clock
00810   *            @arg @ref RCC_PERIPHCLK_TIM16   TIM16 peripheral clock
00811   *            @arg @ref RCC_PERIPHCLK_TIM17   TIM17 peripheral clock
00812   @endif
00813   @if STM32F302x8
00814   *            @arg @ref RCC_PERIPHCLK_I2C2    I2C2 peripheral clock
00815   *            @arg @ref RCC_PERIPHCLK_I2C3    I2C3 peripheral clock
00816   *            @arg @ref RCC_PERIPHCLK_I2S     I2S peripheral clock
00817   *            @arg @ref RCC_PERIPHCLK_USB     USB peripheral clock
00818   *            @arg @ref RCC_PERIPHCLK_ADC1    ADC1 peripheral clock
00819   *            @arg @ref RCC_PERIPHCLK_TIM1    TIM1 peripheral clock
00820   *            @arg @ref RCC_PERIPHCLK_TIM15   TIM15 peripheral clock
00821   *            @arg @ref RCC_PERIPHCLK_TIM16   TIM16 peripheral clock
00822   *            @arg @ref RCC_PERIPHCLK_TIM17   TIM17 peripheral clock
00823   @endif
00824   @if STM32F302xC
00825   *            @arg @ref RCC_PERIPHCLK_USART2  USART2 peripheral clock
00826   *            @arg @ref RCC_PERIPHCLK_USART3  USART3 peripheral clock
00827   *            @arg @ref RCC_PERIPHCLK_UART4   UART4 peripheral clock
00828   *            @arg @ref RCC_PERIPHCLK_UART5   UART5 peripheral clock
00829   *            @arg @ref RCC_PERIPHCLK_I2C2    I2C2 peripheral clock
00830   *            @arg @ref RCC_PERIPHCLK_I2S     I2S peripheral clock
00831   *            @arg @ref RCC_PERIPHCLK_USB     USB peripheral clock
00832   *            @arg @ref RCC_PERIPHCLK_ADC12   ADC12 peripheral clock
00833   *            @arg @ref RCC_PERIPHCLK_TIM1    TIM1 peripheral clock
00834   @endif
00835   @if STM32F302xE
00836   *            @arg @ref RCC_PERIPHCLK_USART2  USART2 peripheral clock
00837   *            @arg @ref RCC_PERIPHCLK_USART3  USART3 peripheral clock
00838   *            @arg @ref RCC_PERIPHCLK_UART4   UART4 peripheral clock
00839   *            @arg @ref RCC_PERIPHCLK_UART5   UART5 peripheral clock
00840   *            @arg @ref RCC_PERIPHCLK_I2C2    I2C2 peripheral clock
00841   *            @arg @ref RCC_PERIPHCLK_I2C3    I2C3 peripheral clock
00842   *            @arg @ref RCC_PERIPHCLK_I2S     I2S peripheral clock
00843   *            @arg @ref RCC_PERIPHCLK_USB     USB peripheral clock
00844   *            @arg @ref RCC_PERIPHCLK_ADC12   ADC12 peripheral clock
00845   *            @arg @ref RCC_PERIPHCLK_TIM1    TIM1 peripheral clock
00846   *            @arg @ref RCC_PERIPHCLK_TIM2    TIM2 peripheral clock
00847   *            @arg @ref RCC_PERIPHCLK_TIM15   TIM15 peripheral clock
00848   *            @arg @ref RCC_PERIPHCLK_TIM16   TIM16 peripheral clock
00849   *            @arg @ref RCC_PERIPHCLK_TIM17   TIM17 peripheral clock
00850   *            @arg @ref RCC_PERIPHCLK_TIM34   TIM34 peripheral clock
00851   @endif
00852   @if STM32F303x8
00853   *            @arg @ref RCC_PERIPHCLK_ADC12   ADC12 peripheral clock
00854   *            @arg @ref RCC_PERIPHCLK_TIM1    TIM1 peripheral clock
00855   @endif
00856   @if STM32F303xC
00857   *            @arg @ref RCC_PERIPHCLK_USART2  USART2 peripheral clock
00858   *            @arg @ref RCC_PERIPHCLK_USART3  USART3 peripheral clock
00859   *            @arg @ref RCC_PERIPHCLK_UART4   UART4 peripheral clock
00860   *            @arg @ref RCC_PERIPHCLK_UART5   UART5 peripheral clock
00861   *            @arg @ref RCC_PERIPHCLK_I2C2    I2C2 peripheral clock
00862   *            @arg @ref RCC_PERIPHCLK_I2S     I2S peripheral clock
00863   *            @arg @ref RCC_PERIPHCLK_USB     USB peripheral clock
00864   *            @arg @ref RCC_PERIPHCLK_ADC12   ADC12 peripheral clock
00865   *            @arg @ref RCC_PERIPHCLK_ADC34   ADC34 peripheral clock
00866   *            @arg @ref RCC_PERIPHCLK_TIM1    TIM1 peripheral clock
00867   *            @arg @ref RCC_PERIPHCLK_TIM8    TIM8 peripheral clock
00868   @endif
00869   @if STM32F303xE
00870   *            @arg @ref RCC_PERIPHCLK_USART2  USART2 peripheral clock
00871   *            @arg @ref RCC_PERIPHCLK_USART3  USART3 peripheral clock
00872   *            @arg @ref RCC_PERIPHCLK_UART4   UART4 peripheral clock
00873   *            @arg @ref RCC_PERIPHCLK_UART5   UART5 peripheral clock
00874   *            @arg @ref RCC_PERIPHCLK_I2C2    I2C2 peripheral clock
00875   *            @arg @ref RCC_PERIPHCLK_I2C3    I2C3 peripheral clock
00876   *            @arg @ref RCC_PERIPHCLK_I2S     I2S peripheral clock
00877   *            @arg @ref RCC_PERIPHCLK_USB     USB peripheral clock
00878   *            @arg @ref RCC_PERIPHCLK_ADC12   ADC12 peripheral clock
00879   *            @arg @ref RCC_PERIPHCLK_ADC34   ADC34 peripheral clock
00880   *            @arg @ref RCC_PERIPHCLK_TIM1    TIM1 peripheral clock
00881   *            @arg @ref RCC_PERIPHCLK_TIM2    TIM2 peripheral clock
00882   *            @arg @ref RCC_PERIPHCLK_TIM8    TIM8 peripheral clock
00883   *            @arg @ref RCC_PERIPHCLK_TIM15   TIM15 peripheral clock
00884   *            @arg @ref RCC_PERIPHCLK_TIM16   TIM16 peripheral clock
00885   *            @arg @ref RCC_PERIPHCLK_TIM17   TIM17 peripheral clock
00886   *            @arg @ref RCC_PERIPHCLK_TIM20   TIM20 peripheral clock
00887   *            @arg @ref RCC_PERIPHCLK_TIM34   TIM34 peripheral clock
00888   @endif
00889   @if STM32F318xx
00890   *            @arg @ref RCC_PERIPHCLK_I2C2    I2C2 peripheral clock
00891   *            @arg @ref RCC_PERIPHCLK_I2C3    I2C3 peripheral clock
00892   *            @arg @ref RCC_PERIPHCLK_I2S     I2S peripheral clock
00893   *            @arg @ref RCC_PERIPHCLK_ADC1    ADC1 peripheral clock
00894   *            @arg @ref RCC_PERIPHCLK_TIM1    TIM1 peripheral clock
00895   *            @arg @ref RCC_PERIPHCLK_TIM15   TIM15 peripheral clock
00896   *            @arg @ref RCC_PERIPHCLK_TIM16   TIM16 peripheral clock
00897   *            @arg @ref RCC_PERIPHCLK_TIM17   TIM17 peripheral clock
00898   @endif
00899   @if STM32F328xx
00900   *            @arg @ref RCC_PERIPHCLK_I2C2    I2C2 peripheral clock
00901   *            @arg @ref RCC_PERIPHCLK_ADC12   ADC12 peripheral clock
00902   *            @arg @ref RCC_PERIPHCLK_TIM1    TIM1 peripheral clock
00903   @endif
00904   @if STM32F334x8
00905   *            @arg @ref RCC_PERIPHCLK_ADC12   ADC12 peripheral clock
00906   *            @arg @ref RCC_PERIPHCLK_TIM1    TIM1 peripheral clock
00907   *            @arg @ref RCC_PERIPHCLK_HRTIM1  HRTIM1 peripheral clock
00908   @endif
00909   @if STM32F358xx
00910   *            @arg @ref RCC_PERIPHCLK_USART2  USART2 peripheral clock
00911   *            @arg @ref RCC_PERIPHCLK_USART3  USART3 peripheral clock
00912   *            @arg @ref RCC_PERIPHCLK_UART4   UART4 peripheral clock
00913   *            @arg @ref RCC_PERIPHCLK_UART5   UART5 peripheral clock
00914   *            @arg @ref RCC_PERIPHCLK_I2S     I2S peripheral clock
00915   *            @arg @ref RCC_PERIPHCLK_ADC12   ADC12 peripheral clock
00916   *            @arg @ref RCC_PERIPHCLK_ADC34   ADC34 peripheral clock
00917   *            @arg @ref RCC_PERIPHCLK_TIM1    TIM1 peripheral clock
00918   *            @arg @ref RCC_PERIPHCLK_TIM8    TIM8 peripheral clock
00919   @endif
00920   @if STM32F373xC
00921   *            @arg @ref RCC_PERIPHCLK_USART2  USART2 peripheral clock
00922   *            @arg @ref RCC_PERIPHCLK_USART3  USART3 peripheral clock
00923   *            @arg @ref RCC_PERIPHCLK_I2C2    I2C2 peripheral clock
00924   *            @arg @ref RCC_PERIPHCLK_USB     USB peripheral clock
00925   *            @arg @ref RCC_PERIPHCLK_ADC1    ADC1 peripheral clock
00926   *            @arg @ref RCC_PERIPHCLK_SDADC   SDADC peripheral clock
00927   *            @arg @ref RCC_PERIPHCLK_CEC     CEC peripheral clock
00928   @endif
00929   @if STM32F378xx
00930   *            @arg @ref RCC_PERIPHCLK_USART2  USART2 peripheral clock
00931   *            @arg @ref RCC_PERIPHCLK_USART3  USART3 peripheral clock
00932   *            @arg @ref RCC_PERIPHCLK_I2C2    I2C2 peripheral clock
00933   *            @arg @ref RCC_PERIPHCLK_ADC1    ADC1 peripheral clock
00934   *            @arg @ref RCC_PERIPHCLK_SDADC   SDADC peripheral clock
00935   *            @arg @ref RCC_PERIPHCLK_CEC     CEC peripheral clock
00936   @endif
00937   @if STM32F398xx
00938   *            @arg @ref RCC_PERIPHCLK_USART2  USART2 peripheral clock
00939   *            @arg @ref RCC_PERIPHCLK_USART3  USART3 peripheral clock
00940   *            @arg @ref RCC_PERIPHCLK_UART4   UART4 peripheral clock
00941   *            @arg @ref RCC_PERIPHCLK_UART5   UART5 peripheral clock
00942   *            @arg @ref RCC_PERIPHCLK_I2C2    I2C2 peripheral clock
00943   *            @arg @ref RCC_PERIPHCLK_I2C3    I2C3 peripheral clock
00944   *            @arg @ref RCC_PERIPHCLK_I2S     I2S peripheral clock
00945   *            @arg @ref RCC_PERIPHCLK_ADC12   ADC12 peripheral clock
00946   *            @arg @ref RCC_PERIPHCLK_ADC34   ADC34 peripheral clock
00947   *            @arg @ref RCC_PERIPHCLK_TIM1    TIM1 peripheral clock
00948   *            @arg @ref RCC_PERIPHCLK_TIM2    TIM2 peripheral clock
00949   *            @arg @ref RCC_PERIPHCLK_TIM8    TIM8 peripheral clock
00950   *            @arg @ref RCC_PERIPHCLK_TIM15   TIM15 peripheral clock
00951   *            @arg @ref RCC_PERIPHCLK_TIM16   TIM16 peripheral clock
00952   *            @arg @ref RCC_PERIPHCLK_TIM17   TIM17 peripheral clock
00953   *            @arg @ref RCC_PERIPHCLK_TIM20   TIM20 peripheral clock
00954   *            @arg @ref RCC_PERIPHCLK_TIM34   TIM34 peripheral clock
00955   @endif
00956   * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
00957   */
00958 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
00959 {
00960   /* frequency == 0 : means that no available frequency for the peripheral */
00961   uint32_t frequency = 0U;
00962
00963   uint32_t srcclk = 0U;
00964 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
00965   uint16_t adc_pll_prediv_table[16] = { 1U,  2U,  4U,  6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U, 256U, 256U, 256U, 256U};
00966 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
00967 #if defined(RCC_CFGR_SDPRE)
00968   uint8_t sdadc_prescaler_table[16] = { 2U,  4U,  6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U};
00969 #endif /* RCC_CFGR_SDPRE */
00970
00971   /* Check the parameters */
00972   assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
00973
00974   switch (PeriphClk)
00975   {
00976   case RCC_PERIPHCLK_RTC:
00977     {
00978       /* Get the current RTC source */
00979       srcclk = __HAL_RCC_GET_RTC_SOURCE();
00980
00981       /* Check if LSE is ready and if RTC clock selection is LSE */
00982       if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
00983       {
00984         frequency = LSE_VALUE;
00985       }
00986       /* Check if LSI is ready and if RTC clock selection is LSI */
00987       else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
00988       {
00989         frequency = LSI_VALUE;
00990       }
00991       /* Check if HSE is ready  and if RTC clock selection is HSI_DIV32*/
00992       else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
00993       {
00994         frequency = HSE_VALUE / 32U;
00995       }
00996       break;
00997     }
00998   case RCC_PERIPHCLK_USART1:
00999     {
01000       /* Get the current USART1 source */
01001       srcclk = __HAL_RCC_GET_USART1_SOURCE();
01002
01003       /* Check if USART1 clock selection is PCLK1 */
01004 #if defined(RCC_USART1CLKSOURCE_PCLK2)
01005       if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
01006       {
01007         frequency = HAL_RCC_GetPCLK2Freq();
01008       }
01009 #else
01010       if (srcclk == RCC_USART1CLKSOURCE_PCLK1)
01011       {
01012         frequency = HAL_RCC_GetPCLK1Freq();
01013       }
01014 #endif /* RCC_USART1CLKSOURCE_PCLK2 */
01015       /* Check if HSI is ready and if USART1 clock selection is HSI */
01016       else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01017       {
01018         frequency = HSI_VALUE;
01019       }
01020       /* Check if USART1 clock selection is SYSCLK */
01021       else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
01022       {
01023         frequency = HAL_RCC_GetSysClockFreq();
01024       }
01025       /* Check if LSE is ready  and if USART1 clock selection is LSE */
01026       else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
01027       {
01028         frequency = LSE_VALUE;
01029       }
01030       break;
01031     }
01032 #if defined(RCC_CFGR3_USART2SW)
01033   case RCC_PERIPHCLK_USART2:
01034     {
01035       /* Get the current USART2 source */
01036       srcclk = __HAL_RCC_GET_USART2_SOURCE();
01037
01038       /* Check if USART2 clock selection is PCLK1 */
01039       if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
01040       {
01041         frequency = HAL_RCC_GetPCLK1Freq();
01042       }
01043       /* Check if HSI is ready and if USART2 clock selection is HSI */
01044       else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01045       {
01046         frequency = HSI_VALUE;
01047       }
01048       /* Check if USART2 clock selection is SYSCLK */
01049       else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
01050       {
01051         frequency = HAL_RCC_GetSysClockFreq();
01052       }
01053       /* Check if LSE is ready  and if USART2 clock selection is LSE */
01054       else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
01055       {
01056         frequency = LSE_VALUE;
01057       }
01058       break;
01059     }
01060 #endif /* RCC_CFGR3_USART2SW */
01061 #if defined(RCC_CFGR3_USART3SW)
01062   case RCC_PERIPHCLK_USART3:
01063     {
01064       /* Get the current USART3 source */
01065       srcclk = __HAL_RCC_GET_USART3_SOURCE();
01066
01067       /* Check if USART3 clock selection is PCLK1 */
01068       if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
01069       {
01070         frequency = HAL_RCC_GetPCLK1Freq();
01071       }
01072       /* Check if HSI is ready and if USART3 clock selection is HSI */
01073       else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01074       {
01075         frequency = HSI_VALUE;
01076       }
01077       /* Check if USART3 clock selection is SYSCLK */
01078       else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
01079       {
01080         frequency = HAL_RCC_GetSysClockFreq();
01081       }
01082       /* Check if LSE is ready  and if USART3 clock selection is LSE */
01083       else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
01084       {
01085         frequency = LSE_VALUE;
01086       }
01087      break;
01088     }
01089 #endif /* RCC_CFGR3_USART3SW */
01090 #if defined(RCC_CFGR3_UART4SW)
01091   case RCC_PERIPHCLK_UART4:
01092     {
01093       /* Get the current UART4 source */
01094       srcclk = __HAL_RCC_GET_UART4_SOURCE();
01095
01096       /* Check if UART4 clock selection is PCLK1 */
01097       if (srcclk == RCC_UART4CLKSOURCE_PCLK1)
01098       {
01099         frequency = HAL_RCC_GetPCLK1Freq();
01100       }
01101       /* Check if HSI is ready and if UART4 clock selection is HSI */
01102       else if ((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01103       {
01104         frequency = HSI_VALUE;
01105       }
01106       /* Check if UART4 clock selection is SYSCLK */
01107       else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK)
01108       {
01109         frequency = HAL_RCC_GetSysClockFreq();
01110       }
01111       /* Check if LSE is ready  and if UART4 clock selection is LSE */
01112       else if ((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
01113       {
01114         frequency = LSE_VALUE;
01115       }
01116       break;
01117     }
01118 #endif /* RCC_CFGR3_UART4SW */
01119 #if defined(RCC_CFGR3_UART5SW)
01120   case RCC_PERIPHCLK_UART5:
01121     {
01122       /* Get the current UART5 source */
01123       srcclk = __HAL_RCC_GET_UART5_SOURCE();
01124
01125       /* Check if UART5 clock selection is PCLK1 */
01126       if (srcclk == RCC_UART5CLKSOURCE_PCLK1)
01127       {
01128         frequency = HAL_RCC_GetPCLK1Freq();
01129       }
01130       /* Check if HSI is ready and if UART5 clock selection is HSI */
01131       else if ((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01132       {
01133         frequency = HSI_VALUE;
01134       }
01135       /* Check if UART5 clock selection is SYSCLK */
01136       else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK)
01137       {
01138         frequency = HAL_RCC_GetSysClockFreq();
01139       }
01140       /* Check if LSE is ready  and if UART5 clock selection is LSE */
01141       else if ((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
01142       {
01143         frequency = LSE_VALUE;
01144       }
01145       break;
01146     }
01147 #endif /* RCC_CFGR3_UART5SW */
01148   case RCC_PERIPHCLK_I2C1:
01149     {
01150       /* Get the current I2C1 source */
01151       srcclk = __HAL_RCC_GET_I2C1_SOURCE();
01152
01153       /* Check if HSI is ready and if I2C1 clock selection is HSI */
01154       if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01155       {
01156         frequency = HSI_VALUE;
01157       }
01158       /* Check if I2C1 clock selection is SYSCLK */
01159       else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
01160       {
01161         frequency = HAL_RCC_GetSysClockFreq();
01162       }
01163       break;
01164     }
01165 #if defined(RCC_CFGR3_I2C2SW)
01166   case RCC_PERIPHCLK_I2C2:
01167     {
01168       /* Get the current I2C2 source */
01169       srcclk = __HAL_RCC_GET_I2C2_SOURCE();
01170
01171       /* Check if HSI is ready and if I2C2 clock selection is HSI */
01172       if ((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01173       {
01174         frequency = HSI_VALUE;
01175       }
01176       /* Check if I2C2 clock selection is SYSCLK */
01177       else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
01178       {
01179         frequency = HAL_RCC_GetSysClockFreq();
01180       }
01181       break;
01182     }
01183 #endif /* RCC_CFGR3_I2C2SW */
01184 #if defined(RCC_CFGR3_I2C3SW)
01185   case RCC_PERIPHCLK_I2C3:
01186     {
01187       /* Get the current I2C3 source */
01188       srcclk = __HAL_RCC_GET_I2C3_SOURCE();
01189
01190       /* Check if HSI is ready and if I2C3 clock selection is HSI */
01191       if ((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01192       {
01193         frequency = HSI_VALUE;
01194       }
01195       /* Check if I2C3 clock selection is SYSCLK */
01196       else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
01197       {
01198         frequency = HAL_RCC_GetSysClockFreq();
01199       }
01200       break;
01201     }
01202 #endif /* RCC_CFGR3_I2C3SW */
01203 #if defined(RCC_CFGR_I2SSRC)
01204   case RCC_PERIPHCLK_I2S:
01205     {
01206       /* Get the current I2S source */
01207       srcclk = __HAL_RCC_GET_I2S_SOURCE();
01208
01209       /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin */
01210       if (srcclk == RCC_I2SCLKSOURCE_EXT)
01211       {
01212         /* External clock used. Frequency cannot be returned.*/
01213         frequency = 0xDEADDEADU;
01214       }
01215       /* Check if I2S clock selection is SYSCLK */
01216       else if (srcclk == RCC_I2SCLKSOURCE_SYSCLK)
01217       {
01218         frequency = HAL_RCC_GetSysClockFreq();
01219       }
01220       break;
01221     }
01222 #endif /* RCC_CFGR_I2SSRC */
01223 #if defined(RCC_CFGR_USBPRE)
01224   case RCC_PERIPHCLK_USB:
01225     {
01226       /* Check if PLL is ready */
01227       if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
01228       {
01229         /* Get the current USB source */
01230         srcclk = __HAL_RCC_GET_USB_SOURCE();
01231
01232         /* Check if USB clock selection is not divided */
01233         if (srcclk == RCC_USBCLKSOURCE_PLL)
01234         {
01235           frequency = RCC_GetPLLCLKFreq();
01236         }
01237         /* Check if USB clock selection is divided by 1.5 */
01238         else /* RCC_USBCLKSOURCE_PLL_DIV1_5 */
01239         {
01240           frequency = (RCC_GetPLLCLKFreq() * 3U) / 2U;
01241         }
01242       }
01243       break;
01244     }
01245 #endif /* RCC_CFGR_USBPRE */
01246 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR_ADCPRE)
01247   case RCC_PERIPHCLK_ADC1:
01248     {
01249       /* Get the current ADC1 source */
01250       srcclk = __HAL_RCC_GET_ADC1_SOURCE();
01251 #if defined(RCC_CFGR2_ADC1PRES)
01252       /* Check if ADC1 clock selection is AHB */
01253       if (srcclk == RCC_ADC1PLLCLK_OFF)
01254       {
01255           frequency = SystemCoreClock;
01256       }
01257       /* PLL clock has been selected */
01258       else
01259       {
01260         /* Check if PLL is ready */
01261         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
01262         {
01263           /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
01264           frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADC1PRES)) & 0xFU];
01265         }
01266       }
01267 #else /* RCC_CFGR_ADCPRE */
01268       /* ADC1 is set to PLCK2 frequency divided by 2U/4U/6U/8U */
01269       frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk  >> POSITION_VAL(RCC_CFGR_ADCPRE)) + 1U) * 2U);
01270 #endif /* RCC_CFGR2_ADC1PRES */
01271       break;
01272     }
01273 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR_ADCPRE */
01274 #if defined(RCC_CFGR2_ADCPRE12)
01275   case RCC_PERIPHCLK_ADC12:
01276     {
01277       /* Get the current ADC12 source */
01278       srcclk = __HAL_RCC_GET_ADC12_SOURCE();
01279       /* Check if ADC12 clock selection is AHB */
01280       if (srcclk == RCC_ADC12PLLCLK_OFF)
01281       {
01282           frequency = SystemCoreClock;
01283       }
01284       /* PLL clock has been selected */
01285       else
01286       {
01287         /* Check if PLL is ready */
01288         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
01289         {
01290           /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6/8U/10U/12U/16U/32U/64U/128U/256U) */
01291           frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE12)) & 0xF];
01292         }
01293       }
01294       break;
01295     }
01296 #endif /* RCC_CFGR2_ADCPRE12 */
01297 #if defined(RCC_CFGR2_ADCPRE34)
01298   case RCC_PERIPHCLK_ADC34:
01299     {
01300       /* Get the current ADC34 source */
01301       srcclk = __HAL_RCC_GET_ADC34_SOURCE();
01302       /* Check if ADC34 clock selection is AHB */
01303       if (srcclk == RCC_ADC34PLLCLK_OFF)
01304       {
01305           frequency = SystemCoreClock;
01306       }
01307       /* PLL clock has been selected */
01308       else
01309       {
01310         /* Check if PLL is ready */
01311         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
01312         {
01313           /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
01314           frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE34)) & 0xF];
01315         }
01316       }
01317       break;
01318     }
01319 #endif /* RCC_CFGR2_ADCPRE34 */
01320 #if defined(RCC_CFGR3_TIM1SW)
01321   case RCC_PERIPHCLK_TIM1:
01322     {
01323       /* Get the current TIM1 source */
01324       srcclk = __HAL_RCC_GET_TIM1_SOURCE();
01325
01326       /* Check if PLL is ready and if TIM1 clock selection is PLL */
01327       if ((srcclk == RCC_TIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
01328       {
01329         frequency = RCC_GetPLLCLKFreq();
01330       }
01331       /* Check if TIM1 clock selection is SYSCLK */
01332       else if (srcclk == RCC_TIM1CLK_HCLK)
01333       {
01334         frequency = SystemCoreClock;
01335       }
01336       break;
01337     }
01338 #endif /* RCC_CFGR3_TIM1SW */
01339 #if defined(RCC_CFGR3_TIM2SW)
01340   case RCC_PERIPHCLK_TIM2:
01341     {
01342       /* Get the current TIM2 source */
01343       srcclk = __HAL_RCC_GET_TIM2_SOURCE();
01344
01345       /* Check if PLL is ready and if TIM2 clock selection is PLL */
01346       if ((srcclk == RCC_TIM2CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
01347       {
01348         frequency = RCC_GetPLLCLKFreq();
01349       }
01350       /* Check if TIM2 clock selection is SYSCLK */
01351       else if (srcclk == RCC_TIM2CLK_HCLK)
01352       {
01353         frequency = SystemCoreClock;
01354       }
01355       break;
01356     }
01357 #endif /* RCC_CFGR3_TIM2SW */
01358 #if defined(RCC_CFGR3_TIM8SW)
01359   case RCC_PERIPHCLK_TIM8:
01360     {
01361       /* Get the current TIM8 source */
01362       srcclk = __HAL_RCC_GET_TIM8_SOURCE();
01363
01364       /* Check if PLL is ready and if TIM8 clock selection is PLL */
01365       if ((srcclk == RCC_TIM8CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
01366       {
01367         frequency = RCC_GetPLLCLKFreq();
01368       }
01369       /* Check if TIM8 clock selection is SYSCLK */
01370       else if (srcclk == RCC_TIM8CLK_HCLK)
01371       {
01372         frequency = SystemCoreClock;
01373       }
01374       break;
01375     }
01376 #endif /* RCC_CFGR3_TIM8SW */
01377 #if defined(RCC_CFGR3_TIM15SW)
01378   case RCC_PERIPHCLK_TIM15:
01379     {
01380       /* Get the current TIM15 source */
01381       srcclk = __HAL_RCC_GET_TIM15_SOURCE();
01382
01383       /* Check if PLL is ready and if TIM15 clock selection is PLL */
01384       if ((srcclk == RCC_TIM15CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
01385       {
01386         frequency = RCC_GetPLLCLKFreq();
01387       }
01388       /* Check if TIM15 clock selection is SYSCLK */
01389       else if (srcclk == RCC_TIM15CLK_HCLK)
01390       {
01391         frequency = SystemCoreClock;
01392       }
01393       break;
01394     }
01395 #endif /* RCC_CFGR3_TIM15SW */
01396 #if defined(RCC_CFGR3_TIM16SW)
01397   case RCC_PERIPHCLK_TIM16:
01398     {
01399       /* Get the current TIM16 source */
01400       srcclk = __HAL_RCC_GET_TIM16_SOURCE();
01401
01402       /* Check if PLL is ready and if TIM16 clock selection is PLL */
01403       if ((srcclk == RCC_TIM16CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
01404       {
01405         frequency = RCC_GetPLLCLKFreq();
01406       }
01407       /* Check if TIM16 clock selection is SYSCLK */
01408       else if (srcclk == RCC_TIM16CLK_HCLK)
01409       {
01410         frequency = SystemCoreClock;
01411       }
01412       break;
01413     }
01414 #endif /* RCC_CFGR3_TIM16SW */
01415 #if defined(RCC_CFGR3_TIM17SW)
01416   case RCC_PERIPHCLK_TIM17:
01417     {
01418       /* Get the current TIM17 source */
01419       srcclk = __HAL_RCC_GET_TIM17_SOURCE();
01420
01421       /* Check if PLL is ready and if TIM17 clock selection is PLL */
01422       if ((srcclk == RCC_TIM17CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
01423       {
01424         frequency = RCC_GetPLLCLKFreq();
01425       }
01426       /* Check if TIM17 clock selection is SYSCLK */
01427       else if (srcclk == RCC_TIM17CLK_HCLK)
01428       {
01429         frequency = SystemCoreClock;
01430       }
01431       break;
01432     }
01433 #endif /* RCC_CFGR3_TIM17SW */
01434 #if defined(RCC_CFGR3_TIM20SW)
01435   case RCC_PERIPHCLK_TIM20:
01436     {
01437       /* Get the current TIM20 source */
01438       srcclk = __HAL_RCC_GET_TIM20_SOURCE();
01439
01440       /* Check if PLL is ready and if TIM20 clock selection is PLL */
01441       if ((srcclk == RCC_TIM20CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
01442       {
01443         frequency = RCC_GetPLLCLKFreq();
01444       }
01445       /* Check if TIM20 clock selection is SYSCLK */
01446       else if (srcclk == RCC_TIM20CLK_HCLK)
01447       {
01448         frequency = SystemCoreClock;
01449       }
01450       break;
01451     }
01452 #endif /* RCC_CFGR3_TIM20SW */
01453 #if defined(RCC_CFGR3_TIM34SW)
01454   case RCC_PERIPHCLK_TIM34:
01455     {
01456       /* Get the current TIM34 source */
01457       srcclk = __HAL_RCC_GET_TIM34_SOURCE();
01458
01459       /* Check if PLL is ready and if TIM34 clock selection is PLL */
01460       if ((srcclk == RCC_TIM34CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
01461       {
01462         frequency = RCC_GetPLLCLKFreq();
01463       }
01464       /* Check if TIM34 clock selection is SYSCLK */
01465       else if (srcclk == RCC_TIM34CLK_HCLK)
01466       {
01467         frequency = SystemCoreClock;
01468       }
01469       break;
01470     }
01471 #endif /* RCC_CFGR3_TIM34SW */
01472 #if defined(RCC_CFGR3_HRTIM1SW)
01473   case RCC_PERIPHCLK_HRTIM1:
01474     {
01475       /* Get the current HRTIM1 source */
01476       srcclk = __HAL_RCC_GET_HRTIM1_SOURCE();
01477
01478       /* Check if PLL is ready and if HRTIM1 clock selection is PLL */
01479       if ((srcclk == RCC_HRTIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
01480       {
01481         frequency = RCC_GetPLLCLKFreq();
01482       }
01483       /* Check if HRTIM1 clock selection is SYSCLK */
01484       else if (srcclk == RCC_HRTIM1CLK_HCLK)
01485       {
01486         frequency = SystemCoreClock;
01487       }
01488      break;
01489     }
01490 #endif /* RCC_CFGR3_HRTIM1SW */
01491 #if defined(RCC_CFGR_SDPRE)
01492   case RCC_PERIPHCLK_SDADC:
01493     {
01494       /* Get the current SDADC source */
01495       srcclk = __HAL_RCC_GET_SDADC_SOURCE();
01496       /* Frequency is the system frequency divided by SDADC prescaler (2U/4U/6U/8U/10U/12U/14U/16U/20U/24U/28U/32U/36U/40U/44U/48U) */
01497       frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> POSITION_VAL(RCC_CFGR_SDPRE)) & 0xF];
01498       break;
01499     }
01500 #endif /* RCC_CFGR_SDPRE */
01501 #if defined(RCC_CFGR3_CECSW)
01502   case RCC_PERIPHCLK_CEC:
01503     {
01504       /* Get the current CEC source */
01505       srcclk = __HAL_RCC_GET_CEC_SOURCE();
01506
01507       /* Check if HSI is ready and if CEC clock selection is HSI */
01508       if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01509       {
01510         frequency = HSI_VALUE;
01511       }
01512       /* Check if LSE is ready  and if CEC clock selection is LSE */
01513       else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
01514       {
01515         frequency = LSE_VALUE;
01516       }
01517       break;
01518     }
01519 #endif /* RCC_CFGR3_CECSW */
01520   default:
01521     {
01522       break;
01523     }
01524   }
01525   return(frequency);
01526 }
01527
01528 /**
01529   * @}
01530   */
01531
01532 /**
01533   * @}
01534   */
01535
01536
01537 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \
01538  || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW)     \
01539  || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW)  \
01540  || defined(RCC_CFGR3_HRTIM1SW)
01541
01542 /** @addtogroup RCCEx_Private_Functions
01543   * @{
01544   */
01545 static uint32_t RCC_GetPLLCLKFreq(void)
01546 {
01547   uint32_t pllmul = 0U, pllsource = 0U, prediv = 0U, pllclk = 0U;
01548
01549   pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
01550   pllmul = ( pllmul >> 18U) + 2U;
01551   pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
01552 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
01553   if (pllsource != RCC_PLLSOURCE_HSI)
01554   {
01555     prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U;
01556     /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
01557     pllclk = (HSE_VALUE/prediv) * pllmul;
01558   }
01559   else
01560   {
01561     /* HSI used as PLL clock source : PLLCLK = HSI/2U * PLLMUL */
01562     pllclk = (HSI_VALUE >> 1U) * pllmul;
01563   }
01564 #else
01565   prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U;
01566   if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
01567   {
01568     /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
01569     pllclk = (HSE_VALUE/prediv) * pllmul;
01570   }
01571   else
01572   {
01573     /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
01574     pllclk = (HSI_VALUE/prediv) * pllmul;
01575   }
01576 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
01577
01578   return pllclk;
01579 }
01580 /**
01581   * @}
01582   */
01583
01584 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */
01585
01586 /**
01587   * @}
01588   */
01589
01590 #endif /* HAL_RCC_MODULE_ENABLED */
01591
01592 /**
01593   * @}
01594   */
01595
01596 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_rcc_ex.h Source File

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stm32f3xx_hal_rcc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_rcc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RCC HAL Extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_RCC_EX_H
00038 #define __STM32F3xx_HAL_RCC_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup RCCEx
00052   * @{
00053   */
00054
00055 /** @addtogroup RCCEx_Private_Macros
00056  * @{
00057  */
00058
00059 #if defined(RCC_CFGR_PLLNODIV)
00060 #define IS_RCC_MCO1SOURCE(SOURCE)  (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK)        || \
00061                                    ((SOURCE) == RCC_MCO1SOURCE_LSI)         || \
00062                                    ((SOURCE) == RCC_MCO1SOURCE_LSE)         || \
00063                                    ((SOURCE) == RCC_MCO1SOURCE_SYSCLK)      || \
00064                                    ((SOURCE) == RCC_MCO1SOURCE_HSI)         || \
00065                                    ((SOURCE) == RCC_MCO1SOURCE_HSE)         || \
00066                                    ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \
00067                                    ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2))
00068 #else
00069 #define IS_RCC_MCO1SOURCE(SOURCE)  (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK)    || \
00070                                    ((SOURCE) == RCC_MCO1SOURCE_LSI)     || \
00071                                    ((SOURCE) == RCC_MCO1SOURCE_LSE)     || \
00072                                    ((SOURCE) == RCC_MCO1SOURCE_SYSCLK)  || \
00073                                    ((SOURCE) == RCC_MCO1SOURCE_HSI)     || \
00074                                    ((SOURCE) == RCC_MCO1SOURCE_HSE)     || \
00075                                    ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2))
00076 #endif /* RCC_CFGR_PLLNODIV */
00077
00078 #if defined(STM32F301x8) || defined(STM32F318xx)
00079 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
00080                                                        RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | \
00081                                                        RCC_PERIPHCLK_ADC1   | RCC_PERIPHCLK_I2S    | \
00082                                                        RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_TIM1   | \
00083                                                        RCC_PERIPHCLK_TIM15  | RCC_PERIPHCLK_TIM16  | \
00084                                                        RCC_PERIPHCLK_TIM17  | RCC_PERIPHCLK_RTC))
00085 #endif /* STM32F301x8 || STM32F318xx */
00086 #if defined(STM32F302x8)
00087 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
00088                                                        RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | \
00089                                                        RCC_PERIPHCLK_ADC1   | RCC_PERIPHCLK_I2S    | \
00090                                                        RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_TIM1   | \
00091                                                        RCC_PERIPHCLK_RTC    | RCC_PERIPHCLK_USB    |  \
00092                                                        RCC_PERIPHCLK_TIM15  | RCC_PERIPHCLK_TIM16  |  \
00093                                                        RCC_PERIPHCLK_TIM17))
00094 #endif /* STM32F302x8 */
00095 #if defined(STM32F302xC)
00096 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
00097                                                      RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \
00098                                                      RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | \
00099                                                      RCC_PERIPHCLK_ADC12  | RCC_PERIPHCLK_I2S    | \
00100                                                      RCC_PERIPHCLK_TIM1   | RCC_PERIPHCLK_RTC    | \
00101                                                      RCC_PERIPHCLK_USB))
00102 #endif /* STM32F302xC */
00103 #if defined(STM32F303xC)
00104 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
00105                                                      RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \
00106                                                      RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | \
00107                                                      RCC_PERIPHCLK_ADC12  | RCC_PERIPHCLK_ADC34  | \
00108                                                      RCC_PERIPHCLK_I2S    | RCC_PERIPHCLK_TIM1   | \
00109                                                      RCC_PERIPHCLK_TIM8   | RCC_PERIPHCLK_RTC    | \
00110                                                      RCC_PERIPHCLK_USB))
00111 #endif /* STM32F303xC */
00112 #if defined(STM32F302xE)
00113 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
00114                                                      RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \
00115                                                      RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | \
00116                                                      RCC_PERIPHCLK_ADC12  | RCC_PERIPHCLK_I2S    | \
00117                                                      RCC_PERIPHCLK_TIM1   | RCC_PERIPHCLK_RTC    | \
00118                                                      RCC_PERIPHCLK_USB    | RCC_PERIPHCLK_I2C3   | \
00119                                                      RCC_PERIPHCLK_TIM2   | RCC_PERIPHCLK_TIM34  | \
00120                                                      RCC_PERIPHCLK_TIM15  | RCC_PERIPHCLK_TIM16  | \
00121                                                      RCC_PERIPHCLK_TIM17))
00122 #endif /* STM32F302xE */
00123 #if defined(STM32F303xE)
00124 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
00125                                                      RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \
00126                                                      RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | \
00127                                                      RCC_PERIPHCLK_ADC12  | RCC_PERIPHCLK_ADC34  | \
00128                                                      RCC_PERIPHCLK_I2S    | RCC_PERIPHCLK_TIM1   | \
00129                                                      RCC_PERIPHCLK_TIM8   | RCC_PERIPHCLK_RTC    | \
00130                                                      RCC_PERIPHCLK_USB    | RCC_PERIPHCLK_I2C3   | \
00131                                                      RCC_PERIPHCLK_TIM2   | RCC_PERIPHCLK_TIM34  | \
00132                                                      RCC_PERIPHCLK_TIM15  | RCC_PERIPHCLK_TIM16  | \
00133                                                      RCC_PERIPHCLK_TIM17  | RCC_PERIPHCLK_TIM20))
00134 #endif /* STM32F303xE */
00135 #if defined(STM32F398xx)
00136 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
00137                                                      RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \
00138                                                      RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | \
00139                                                      RCC_PERIPHCLK_ADC12  | RCC_PERIPHCLK_ADC34  | \
00140                                                      RCC_PERIPHCLK_I2S    | RCC_PERIPHCLK_TIM1   | \
00141                                                      RCC_PERIPHCLK_TIM8   | RCC_PERIPHCLK_RTC    | \
00142                                                      RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_TIM2   | \
00143                                                      RCC_PERIPHCLK_TIM34  | RCC_PERIPHCLK_TIM15  | \
00144                                                      RCC_PERIPHCLK_TIM16  | RCC_PERIPHCLK_TIM17  | \
00145                                                      RCC_PERIPHCLK_TIM20))
00146 #endif /* STM32F398xx */
00147 #if defined(STM32F358xx)
00148 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
00149                                                      RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \
00150                                                      RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | \
00151                                                      RCC_PERIPHCLK_ADC12  | RCC_PERIPHCLK_ADC34  | \
00152                                                      RCC_PERIPHCLK_I2S    | RCC_PERIPHCLK_TIM1   | \
00153                                                      RCC_PERIPHCLK_TIM8   | RCC_PERIPHCLK_RTC))
00154 #endif /* STM32F358xx */
00155 #if defined(STM32F303x8)
00156 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
00157                                                        RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_ADC12  | \
00158                                                        RCC_PERIPHCLK_TIM1   | RCC_PERIPHCLK_RTC))
00159 #endif /* STM32F303x8 */
00160 #if defined(STM32F334x8)
00161 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
00162                                                        RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_ADC12  | \
00163                                                        RCC_PERIPHCLK_TIM1   | RCC_PERIPHCLK_HRTIM1 | \
00164                                                        RCC_PERIPHCLK_RTC))
00165 #endif /* STM32F334x8 */
00166 #if defined(STM32F328xx)
00167 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
00168                                                        RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_ADC12  | \
00169                                                        RCC_PERIPHCLK_TIM1   | RCC_PERIPHCLK_RTC))
00170 #endif /* STM32F328xx */
00171 #if defined(STM32F373xC)
00172 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
00173                                                      RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | \
00174                                                      RCC_PERIPHCLK_ADC1   | RCC_PERIPHCLK_SDADC  | \
00175                                                      RCC_PERIPHCLK_CEC    | RCC_PERIPHCLK_RTC    | \
00176                                                      RCC_PERIPHCLK_USB))
00177 #endif /* STM32F373xC */
00178 #if defined(STM32F378xx)
00179 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
00180                                                      RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | \
00181                                                      RCC_PERIPHCLK_ADC1   | RCC_PERIPHCLK_SDADC  | \
00182                                                      RCC_PERIPHCLK_CEC    | RCC_PERIPHCLK_RTC))
00183 #endif /* STM32F378xx */
00184
00185 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00186 #define IS_RCC_USART1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1)  || \
00187                                          ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
00188                                          ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
00189                                          ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
00190 #define IS_RCC_I2C2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
00191                                        ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
00192 #define IS_RCC_I2C3CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
00193                                        ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
00194 #define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF)   || ((ADCCLK) == RCC_ADC1PLLCLK_DIV1)   || \
00195                                        ((ADCCLK) == RCC_ADC1PLLCLK_DIV2)  || ((ADCCLK) == RCC_ADC1PLLCLK_DIV4)   || \
00196                                        ((ADCCLK) == RCC_ADC1PLLCLK_DIV6)  || ((ADCCLK) == RCC_ADC1PLLCLK_DIV8)   || \
00197                                        ((ADCCLK) == RCC_ADC1PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV12)  || \
00198                                        ((ADCCLK) == RCC_ADC1PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV32)  || \
00199                                        ((ADCCLK) == RCC_ADC1PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) || \
00200                                        ((ADCCLK) == RCC_ADC1PLLCLK_DIV256))
00201 #define IS_RCC_I2SCLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
00202                                       ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
00203 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
00204                                       ((SOURCE) == RCC_TIM1CLK_PLLCLK))
00205 #define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
00206                                        ((SOURCE) == RCC_TIM15CLK_PLLCLK))
00207 #define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
00208                                        ((SOURCE) == RCC_TIM16CLK_PLLCLK))
00209 #define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
00210                                        ((SOURCE) == RCC_TIM17CLK_PLLCLK))
00211 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
00212 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
00213 #define IS_RCC_USART1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2)  || \
00214                                          ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
00215                                          ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
00216                                          ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
00217 #define IS_RCC_I2C2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
00218                                        ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
00219 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF)   || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1)   || \
00220                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV2)  || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4)   || \
00221                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV6)  || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8)   || \
00222                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12)  || \
00223                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32)  || \
00224                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
00225                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
00226 #define IS_RCC_I2SCLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
00227                                       ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
00228 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
00229                                       ((SOURCE) == RCC_TIM1CLK_PLLCLK))
00230 #define IS_RCC_UART4CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1)  || \
00231                                         ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
00232                                         ((SOURCE) == RCC_UART4CLKSOURCE_LSE)    || \
00233                                         ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
00234 #define IS_RCC_UART5CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1)  || \
00235                                         ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
00236                                         ((SOURCE) == RCC_UART5CLKSOURCE_LSE)    || \
00237                                         ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
00238 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
00239 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
00240 #define IS_RCC_USART1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2)  || \
00241                                          ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
00242                                          ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
00243                                          ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
00244 #define IS_RCC_I2C2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
00245                                        ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
00246 #define IS_RCC_I2C3CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
00247                                        ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
00248 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF)   || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1)   || \
00249                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV2)  || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4)   || \
00250                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV6)  || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8)   || \
00251                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12)  || \
00252                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32)  || \
00253                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
00254                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
00255 #define IS_RCC_I2SCLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
00256                                       ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
00257 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
00258                                       ((SOURCE) == RCC_TIM1CLK_PLLCLK))
00259 #define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) || \
00260                                       ((SOURCE) == RCC_TIM2CLK_PLLCLK))
00261 #define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) || \
00262                                       ((SOURCE) == RCC_TIM34CLK_PLLCLK))
00263 #define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
00264                                       ((SOURCE) == RCC_TIM15CLK_PLLCLK))
00265 #define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
00266                                       ((SOURCE) == RCC_TIM16CLK_PLLCLK))
00267 #define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
00268                                       ((SOURCE) == RCC_TIM17CLK_PLLCLK))
00269 #define IS_RCC_UART4CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1)  || \
00270                                         ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
00271                                         ((SOURCE) == RCC_UART4CLKSOURCE_LSE)    || \
00272                                         ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
00273 #define IS_RCC_UART5CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1)  || \
00274                                         ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
00275                                         ((SOURCE) == RCC_UART5CLKSOURCE_LSE)    || \
00276                                         ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
00277 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
00278 #if defined(STM32F303xE) ||  defined(STM32F398xx)
00279 #define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) || \
00280                                       ((SOURCE) == RCC_TIM20CLK_PLLCLK))
00281 #endif /* STM32F303xE || STM32F398xx */
00282 #if defined(STM32F303xE) || defined(STM32F398xx)\
00283   || defined(STM32F303xC) || defined(STM32F358xx)
00284 #define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF)   || ((ADCCLK) == RCC_ADC34PLLCLK_DIV1)   || \
00285                                         ((ADCCLK) == RCC_ADC34PLLCLK_DIV2)  || ((ADCCLK) == RCC_ADC34PLLCLK_DIV4)   || \
00286                                         ((ADCCLK) == RCC_ADC34PLLCLK_DIV6)  || ((ADCCLK) == RCC_ADC34PLLCLK_DIV8)   || \
00287                                         ((ADCCLK) == RCC_ADC34PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV12)  || \
00288                                         ((ADCCLK) == RCC_ADC34PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV32)  || \
00289                                         ((ADCCLK) == RCC_ADC34PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) || \
00290                                         ((ADCCLK) == RCC_ADC34PLLCLK_DIV256))
00291 #define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) || \
00292                                       ((SOURCE) == RCC_TIM8CLK_PLLCLK))
00293 #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
00294 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
00295 #define IS_RCC_USART1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1)  || \
00296                                          ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
00297                                          ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
00298                                          ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
00299 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF)   || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1)   || \
00300                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV2)  || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4)   || \
00301                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV6)  || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8)   || \
00302                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12)  || \
00303                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32)  || \
00304                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
00305                                         ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
00306 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
00307                                       ((SOURCE) == RCC_TIM1CLK_PLLCLK))
00308 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
00309 #if defined(STM32F334x8)
00310 #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) || \
00311                                         ((SOURCE) == RCC_HRTIM1CLK_PLLCLK))
00312 #endif /* STM32F334x8 */
00313 #if defined(STM32F373xC) || defined(STM32F378xx)
00314 #define IS_RCC_USART1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2)  || \
00315                                          ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
00316                                          ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
00317                                          ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
00318 #define IS_RCC_I2C2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
00319                                        ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
00320 #define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) || ((ADCCLK) == RCC_ADC1PCLK2_DIV4) || \
00321                                       ((ADCCLK) == RCC_ADC1PCLK2_DIV6) || ((ADCCLK) == RCC_ADC1PCLK2_DIV8))
00322 #define IS_RCC_CECCLKSOURCE(SOURCE)  (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
00323                                       ((SOURCE) == RCC_CECCLKSOURCE_LSE))
00324 #define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1)  || ((DIV) == RCC_SDADCSYSCLK_DIV2)   || \
00325                                      ((DIV) == RCC_SDADCSYSCLK_DIV4)  || ((DIV) == RCC_SDADCSYSCLK_DIV6)   || \
00326                                      ((DIV) == RCC_SDADCSYSCLK_DIV8)  || ((DIV) == RCC_SDADCSYSCLK_DIV10)  || \
00327                                      ((DIV) == RCC_SDADCSYSCLK_DIV12) || ((DIV) == RCC_SDADCSYSCLK_DIV14)  || \
00328                                      ((DIV) == RCC_SDADCSYSCLK_DIV16) || ((DIV) == RCC_SDADCSYSCLK_DIV20)  || \
00329                                      ((DIV) == RCC_SDADCSYSCLK_DIV24) || ((DIV) == RCC_SDADCSYSCLK_DIV28)  || \
00330                                      ((DIV) == RCC_SDADCSYSCLK_DIV32) || ((DIV) == RCC_SDADCSYSCLK_DIV36)  || \
00331                                      ((DIV) == RCC_SDADCSYSCLK_DIV40) || ((DIV) == RCC_SDADCSYSCLK_DIV44)  || \
00332                                      ((DIV) == RCC_SDADCSYSCLK_DIV48))
00333 #endif /* STM32F373xC || STM32F378xx */
00334 #if defined(STM32F302xE) || defined(STM32F303xE)\
00335   || defined(STM32F302xC) || defined(STM32F303xC)\
00336   || defined(STM32F302x8)                        \
00337   || defined(STM32F373xC)
00338 #define IS_RCC_USBCLKSOURCE(SOURCE)  (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \
00339                                       ((SOURCE) == RCC_USBCLKSOURCE_PLL_DIV1_5))
00340 #endif /* STM32F302xE || STM32F303xE || */
00341        /* STM32F302xC || STM32F303xC || */
00342        /* STM32F302x8                || */
00343        /* STM32F373xC                   */
00344 #if defined(RCC_CFGR_MCOPRE)
00345 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2)   || \
00346                             ((DIV) == RCC_MCODIV_4)  || ((DIV) == RCC_MCODIV_8)   || \
00347                             ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32)  || \
00348                             ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128))
00349 #else
00350 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
00351 #endif /* RCC_CFGR_MCOPRE */
00352
00353 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW)        || \
00354                                      ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW)  || \
00355                                      ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
00356                                      ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
00357
00358 /**
00359   * @}
00360   */
00361
00362 /* Exported types ------------------------------------------------------------*/
00363 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
00364   * @{
00365   */
00366
00367 /**
00368   * @brief  RCC extended clocks structure definition
00369   */
00370 #if defined(STM32F301x8) || defined(STM32F318xx)
00371 typedef struct
00372 {
00373   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
00374                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00375
00376   uint32_t RTCClockSelection;    /*!< Specifies RTC Clock Prescalers Selection
00377                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
00378
00379   uint32_t Usart1ClockSelection; /*!< USART1 clock source
00380                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00381
00382   uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
00383                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
00384
00385   uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
00386                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
00387
00388   uint32_t I2c3ClockSelection;   /*!< I2C3 clock source
00389                                       This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
00390
00391   uint32_t Adc1ClockSelection;   /*!< ADC1 clock source
00392                                       This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
00393
00394   uint32_t I2sClockSelection;    /*!< I2S clock source
00395                                       This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
00396
00397   uint32_t Tim1ClockSelection;   /*!< TIM1 clock source
00398                                       This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
00399
00400   uint32_t Tim15ClockSelection;  /*!< TIM15 clock source
00401                                       This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
00402
00403   uint32_t Tim16ClockSelection;  /*!< TIM16 clock source
00404                                       This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
00405
00406   uint32_t Tim17ClockSelection;  /*!< TIM17 clock source
00407                                       This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
00408 }RCC_PeriphCLKInitTypeDef;
00409 #endif /* STM32F301x8 || STM32F318xx */
00410
00411 #if defined(STM32F302x8)
00412 typedef struct
00413 {
00414   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
00415                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00416
00417   uint32_t RTCClockSelection;    /*!< Specifies RTC Clock Prescalers Selection
00418                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
00419
00420   uint32_t Usart1ClockSelection; /*!< USART1 clock source
00421                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00422
00423   uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
00424                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
00425
00426   uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
00427                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
00428
00429   uint32_t I2c3ClockSelection;   /*!< I2C3 clock source
00430                                       This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
00431
00432   uint32_t Adc1ClockSelection;   /*!< ADC1 clock source
00433                                       This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
00434
00435   uint32_t I2sClockSelection;    /*!< I2S clock source
00436                                       This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
00437
00438   uint32_t Tim1ClockSelection;   /*!< TIM1 clock source
00439                                       This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
00440
00441   uint32_t Tim15ClockSelection;  /*!< TIM15 clock source
00442                                       This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
00443
00444   uint32_t Tim16ClockSelection;  /*!< TIM16 clock source
00445                                       This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
00446
00447   uint32_t Tim17ClockSelection;  /*!< TIM17 clock source
00448                                       This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
00449
00450   uint32_t USBClockSelection;    /*!< USB clock source
00451                                       This parameter can be a value of @ref RCCEx_USB_Clock_Source */
00452
00453 }RCC_PeriphCLKInitTypeDef;
00454 #endif /* STM32F302x8 */
00455
00456 #if defined(STM32F302xC)
00457 typedef struct
00458 {
00459   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
00460                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00461
00462   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
00463                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
00464
00465   uint32_t Usart1ClockSelection; /*!< USART1 clock source
00466                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00467
00468   uint32_t Usart2ClockSelection; /*!< USART2 clock source
00469                                       This parameter can be a value of @ref RCC_USART2_Clock_Source */
00470
00471   uint32_t Usart3ClockSelection; /*!< USART3 clock source
00472                                       This parameter can be a value of @ref RCC_USART3_Clock_Source */
00473
00474   uint32_t Uart4ClockSelection;  /*!< UART4 clock source
00475                                       This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
00476
00477   uint32_t Uart5ClockSelection;  /*!< UART5 clock source
00478                                       This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
00479
00480   uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
00481                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
00482
00483   uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
00484                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
00485
00486   uint32_t Adc12ClockSelection;  /*!< ADC1 & ADC2 clock source
00487                                       This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
00488
00489   uint32_t I2sClockSelection;    /*!< I2S clock source
00490                                       This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
00491
00492   uint32_t Tim1ClockSelection;   /*!< TIM1 clock source
00493                                       This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
00494
00495   uint32_t USBClockSelection;    /*!< USB clock source
00496                                       This parameter can be a value of @ref RCCEx_USB_Clock_Source */
00497
00498 }RCC_PeriphCLKInitTypeDef;
00499 #endif /* STM32F302xC */
00500
00501 #if defined(STM32F303xC)
00502 typedef struct
00503 {
00504   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
00505                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00506
00507   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
00508                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
00509
00510   uint32_t Usart1ClockSelection; /*!< USART1 clock source
00511                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00512
00513   uint32_t Usart2ClockSelection; /*!< USART2 clock source
00514                                       This parameter can be a value of @ref RCC_USART2_Clock_Source */
00515
00516   uint32_t Usart3ClockSelection; /*!< USART3 clock source
00517                                       This parameter can be a value of @ref RCC_USART3_Clock_Source */
00518
00519   uint32_t Uart4ClockSelection;  /*!< UART4 clock source
00520                                       This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
00521
00522   uint32_t Uart5ClockSelection;  /*!< UART5 clock source
00523                                       This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
00524
00525   uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
00526                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
00527
00528   uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
00529                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
00530
00531   uint32_t Adc12ClockSelection;  /*!< ADC1 & ADC2 clock source
00532                                       This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
00533
00534   uint32_t Adc34ClockSelection;  /*!< ADC3 & ADC4 clock source
00535                                       This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
00536
00537   uint32_t I2sClockSelection;    /*!< I2S clock source
00538                                       This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
00539
00540   uint32_t Tim1ClockSelection;   /*!< TIM1 clock source
00541                                       This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
00542
00543   uint32_t Tim8ClockSelection;   /*!< TIM8 clock source
00544                                       This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
00545
00546   uint32_t USBClockSelection;    /*!< USB clock source
00547                                       This parameter can be a value of @ref RCCEx_USB_Clock_Source */
00548
00549 }RCC_PeriphCLKInitTypeDef;
00550 #endif /* STM32F303xC */
00551
00552 #if defined(STM32F302xE)
00553 typedef struct
00554 {
00555   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
00556                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00557
00558   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
00559                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
00560
00561   uint32_t Usart1ClockSelection; /*!< USART1 clock source
00562                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00563
00564   uint32_t Usart2ClockSelection; /*!< USART2 clock source
00565                                       This parameter can be a value of @ref RCC_USART2_Clock_Source */
00566
00567   uint32_t Usart3ClockSelection; /*!< USART3 clock source
00568                                       This parameter can be a value of @ref RCC_USART3_Clock_Source */
00569
00570   uint32_t Uart4ClockSelection;  /*!< UART4 clock source
00571                                       This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
00572
00573   uint32_t Uart5ClockSelection;  /*!< UART5 clock source
00574                                       This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
00575
00576   uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
00577                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
00578
00579   uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
00580                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
00581
00582   uint32_t I2c3ClockSelection;   /*!< I2C3 clock source
00583                                       This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
00584
00585   uint32_t Adc12ClockSelection;  /*!< ADC1 & ADC2 clock source
00586                                       This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
00587
00588   uint32_t I2sClockSelection;    /*!< I2S clock source
00589                                       This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
00590
00591   uint32_t Tim1ClockSelection;   /*!< TIM1 clock source
00592                                       This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
00593
00594   uint32_t Tim2ClockSelection;   /*!< TIM2 clock source
00595                                       This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
00596
00597   uint32_t Tim34ClockSelection;   /*!< TIM3 & TIM4 clock source
00598                                        This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
00599
00600   uint32_t Tim15ClockSelection;  /*!< TIM15 clock source
00601                                       This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
00602
00603   uint32_t Tim16ClockSelection;  /*!< TIM16 clock source
00604                                       This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
00605
00606   uint32_t Tim17ClockSelection;  /*!< TIM17 clock source
00607                                       This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
00608
00609   uint32_t USBClockSelection;    /*!< USB clock source
00610                                       This parameter can be a value of @ref RCCEx_USB_Clock_Source */
00611
00612 }RCC_PeriphCLKInitTypeDef;
00613 #endif /* STM32F302xE */
00614
00615 #if defined(STM32F303xE)
00616 typedef struct
00617 {
00618   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
00619                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00620
00621   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
00622                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
00623
00624   uint32_t Usart1ClockSelection; /*!< USART1 clock source
00625                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00626
00627   uint32_t Usart2ClockSelection; /*!< USART2 clock source
00628                                       This parameter can be a value of @ref RCC_USART2_Clock_Source */
00629
00630   uint32_t Usart3ClockSelection; /*!< USART3 clock source
00631                                       This parameter can be a value of @ref RCC_USART3_Clock_Source */
00632
00633   uint32_t Uart4ClockSelection;  /*!< UART4 clock source
00634                                       This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
00635
00636   uint32_t Uart5ClockSelection;  /*!< UART5 clock source
00637                                       This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
00638
00639   uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
00640                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
00641
00642   uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
00643                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
00644
00645   uint32_t I2c3ClockSelection;   /*!< I2C3 clock source
00646                                       This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
00647
00648   uint32_t Adc12ClockSelection;  /*!< ADC1 & ADC2 clock source
00649                                       This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
00650
00651   uint32_t Adc34ClockSelection;  /*!< ADC3 & ADC4 clock source
00652                                       This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
00653
00654   uint32_t I2sClockSelection;    /*!< I2S clock source
00655                                       This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
00656
00657   uint32_t Tim1ClockSelection;   /*!< TIM1 clock source
00658                                       This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
00659
00660   uint32_t Tim2ClockSelection;   /*!< TIM2 clock source
00661                                       This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
00662
00663   uint32_t Tim34ClockSelection;   /*!< TIM3 & TIM4 clock source
00664                                        This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
00665
00666   uint32_t Tim8ClockSelection;   /*!< TIM8 clock source
00667                                       This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
00668
00669   uint32_t Tim15ClockSelection;  /*!< TIM15 clock source
00670                                       This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
00671
00672   uint32_t Tim16ClockSelection;  /*!< TIM16 clock source
00673                                       This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
00674
00675   uint32_t Tim17ClockSelection;  /*!< TIM17 clock source
00676                                       This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
00677
00678   uint32_t Tim20ClockSelection;  /*!< TIM20 clock source
00679                                       This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
00680
00681   uint32_t USBClockSelection;    /*!< USB clock source
00682                                       This parameter can be a value of @ref RCCEx_USB_Clock_Source */
00683
00684 }RCC_PeriphCLKInitTypeDef;
00685 #endif /* STM32F303xE */
00686
00687 #if defined(STM32F398xx)
00688 typedef struct
00689 {
00690   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
00691                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00692
00693   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
00694                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
00695
00696   uint32_t Usart1ClockSelection; /*!< USART1 clock source
00697                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00698
00699   uint32_t Usart2ClockSelection; /*!< USART2 clock source
00700                                       This parameter can be a value of @ref RCC_USART2_Clock_Source */
00701
00702   uint32_t Usart3ClockSelection; /*!< USART3 clock source
00703                                       This parameter can be a value of @ref RCC_USART3_Clock_Source */
00704
00705   uint32_t Uart4ClockSelection;  /*!< UART4 clock source
00706                                       This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
00707
00708   uint32_t Uart5ClockSelection;  /*!< UART5 clock source
00709                                       This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
00710
00711   uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
00712                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
00713
00714   uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
00715                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
00716
00717   uint32_t I2c3ClockSelection;   /*!< I2C3 clock source
00718                                       This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
00719
00720   uint32_t Adc12ClockSelection;  /*!< ADC1 & ADC2 clock source
00721                                       This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
00722
00723   uint32_t Adc34ClockSelection;  /*!< ADC3 & ADC4 clock source
00724                                       This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
00725
00726   uint32_t I2sClockSelection;    /*!< I2S clock source
00727                                       This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
00728
00729   uint32_t Tim1ClockSelection;   /*!< TIM1 clock source
00730                                       This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
00731
00732   uint32_t Tim2ClockSelection;   /*!< TIM2 clock source
00733                                       This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
00734
00735   uint32_t Tim34ClockSelection;   /*!< TIM3 & TIM4 clock source
00736                                        This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
00737
00738   uint32_t Tim8ClockSelection;   /*!< TIM8 clock source
00739                                       This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
00740
00741   uint32_t Tim15ClockSelection;  /*!< TIM15 clock source
00742                                       This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
00743
00744   uint32_t Tim16ClockSelection;  /*!< TIM16 clock source
00745                                       This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
00746
00747   uint32_t Tim17ClockSelection;  /*!< TIM17 clock source
00748                                       This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
00749
00750   uint32_t Tim20ClockSelection;  /*!< TIM20 clock source
00751                                       This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
00752
00753 }RCC_PeriphCLKInitTypeDef;
00754 #endif /* STM32F398xx */
00755
00756 #if defined(STM32F358xx)
00757 typedef struct
00758 {
00759   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
00760                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00761
00762   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
00763                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
00764
00765   uint32_t Usart1ClockSelection; /*!< USART1 clock source
00766                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00767
00768   uint32_t Usart2ClockSelection; /*!< USART2 clock source
00769                                       This parameter can be a value of @ref RCC_USART2_Clock_Source */
00770
00771   uint32_t Usart3ClockSelection; /*!< USART3 clock source
00772                                       This parameter can be a value of @ref RCC_USART3_Clock_Source */
00773
00774   uint32_t Uart4ClockSelection;  /*!< UART4 clock source
00775                                       This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
00776
00777   uint32_t Uart5ClockSelection;  /*!< UART5 clock source
00778                                       This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
00779
00780   uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
00781                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
00782
00783   uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
00784                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
00785
00786   uint32_t Adc12ClockSelection;  /*!< ADC1 & ADC2 clock source
00787                                       This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
00788
00789   uint32_t Adc34ClockSelection;  /*!< ADC3 & ADC4 clock source
00790                                       This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
00791
00792   uint32_t I2sClockSelection;    /*!< I2S clock source
00793                                       This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
00794
00795   uint32_t Tim1ClockSelection;   /*!< TIM1 clock source
00796                                       This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
00797
00798   uint32_t Tim8ClockSelection;   /*!< TIM8 clock source
00799                                       This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
00800
00801 }RCC_PeriphCLKInitTypeDef;
00802 #endif /* STM32F358xx */
00803
00804 #if defined(STM32F303x8)
00805 typedef struct
00806 {
00807   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
00808                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00809
00810   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
00811                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
00812
00813   uint32_t Usart1ClockSelection; /*!< USART1 clock source
00814                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00815
00816   uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
00817                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
00818
00819   uint32_t Adc12ClockSelection;  /*!< ADC1 & ADC2 clock source
00820                                       This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
00821
00822   uint32_t Tim1ClockSelection;   /*!< TIM1 clock source
00823                                       This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
00824
00825 }RCC_PeriphCLKInitTypeDef;
00826 #endif /* STM32F303x8 */
00827
00828 #if defined(STM32F334x8)
00829 typedef struct
00830 {
00831   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
00832                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00833
00834   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
00835                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
00836
00837   uint32_t Usart1ClockSelection; /*!< USART1 clock source
00838                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00839
00840   uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
00841                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
00842
00843   uint32_t Adc12ClockSelection;  /*!< ADC1 & ADC2 clock source
00844                                       This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
00845
00846   uint32_t Tim1ClockSelection;   /*!< TIM1 clock source
00847                                       This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
00848
00849   uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source
00850                                       This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */
00851
00852 }RCC_PeriphCLKInitTypeDef;
00853 #endif /* STM32F334x8 */
00854
00855 #if defined(STM32F328xx)
00856 typedef struct
00857 {
00858   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
00859                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00860
00861   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
00862                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
00863
00864   uint32_t Usart1ClockSelection; /*!< USART1 clock source
00865                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00866
00867   uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
00868                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
00869
00870   uint32_t Adc12ClockSelection;  /*!< ADC1 & ADC2 clock source
00871                                       This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
00872
00873   uint32_t Tim1ClockSelection;   /*!< TIM1 clock source
00874                                       This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
00875
00876 }RCC_PeriphCLKInitTypeDef;
00877 #endif /* STM32F328xx */
00878
00879 #if defined(STM32F373xC)
00880 typedef struct
00881 {
00882   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
00883                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00884
00885   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
00886                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
00887
00888   uint32_t Usart1ClockSelection; /*!< USART1 clock source
00889                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00890
00891   uint32_t Usart2ClockSelection; /*!< USART2 clock source
00892                                       This parameter can be a value of @ref RCC_USART2_Clock_Source */
00893
00894   uint32_t Usart3ClockSelection; /*!< USART3 clock source
00895                                       This parameter can be a value of @ref RCC_USART3_Clock_Source */
00896
00897   uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
00898                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
00899
00900   uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
00901                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
00902
00903   uint32_t Adc1ClockSelection;   /*!< ADC1 clock source
00904                                       This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
00905
00906   uint32_t SdadcClockSelection;   /*!< SDADC clock prescaler
00907                                       This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
00908
00909   uint32_t CecClockSelection;    /*!< HDMI CEC clock source
00910                                        This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
00911
00912   uint32_t USBClockSelection;    /*!< USB clock source
00913                                       This parameter can be a value of @ref RCCEx_USB_Clock_Source */
00914
00915 }RCC_PeriphCLKInitTypeDef;
00916 #endif /* STM32F373xC */
00917
00918 #if defined(STM32F378xx)
00919 typedef struct
00920 {
00921   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
00922                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00923
00924   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
00925                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
00926
00927   uint32_t Usart1ClockSelection; /*!< USART1 clock source
00928                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00929
00930   uint32_t Usart2ClockSelection; /*!< USART2 clock source
00931                                       This parameter can be a value of @ref RCC_USART2_Clock_Source */
00932
00933   uint32_t Usart3ClockSelection; /*!< USART3 clock source
00934                                       This parameter can be a value of @ref RCC_USART3_Clock_Source */
00935
00936   uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
00937                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
00938
00939   uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
00940                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
00941
00942   uint32_t Adc1ClockSelection;   /*!< ADC1 clock source
00943                                       This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
00944
00945   uint32_t SdadcClockSelection;   /*!< SDADC clock prescaler
00946                                       This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
00947
00948   uint32_t CecClockSelection;    /*!< HDMI CEC clock source
00949                                        This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
00950
00951 }RCC_PeriphCLKInitTypeDef;
00952 #endif /* STM32F378xx */
00953
00954 /**
00955   * @}
00956   */
00957
00958 /* Exported constants --------------------------------------------------------*/
00959 /** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants
00960   * @{
00961   */
00962 /** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
00963   * @{
00964   */
00965 #define RCC_MCO1SOURCE_NOCLOCK            RCC_CFGR_MCO_NOCLOCK
00966 #define RCC_MCO1SOURCE_LSI                RCC_CFGR_MCO_LSI
00967 #define RCC_MCO1SOURCE_LSE                RCC_CFGR_MCO_LSE
00968 #define RCC_MCO1SOURCE_SYSCLK             RCC_CFGR_MCO_SYSCLK
00969 #define RCC_MCO1SOURCE_HSI                RCC_CFGR_MCO_HSI
00970 #define RCC_MCO1SOURCE_HSE                RCC_CFGR_MCO_HSE
00971 #if defined(RCC_CFGR_PLLNODIV)
00972 #define RCC_MCO1SOURCE_PLLCLK             (RCC_CFGR_PLLNODIV | RCC_CFGR_MCO_PLL)
00973 #endif /* RCC_CFGR_PLLNODIV */
00974 #define RCC_MCO1SOURCE_PLLCLK_DIV2        RCC_CFGR_MCO_PLL
00975
00976 /**
00977   * @}
00978   */
00979
00980 /** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection
00981   * @{
00982   */
00983 #if defined(STM32F301x8) || defined(STM32F318xx)
00984 #define RCC_PERIPHCLK_USART1           (0x00000001U)
00985 #define RCC_PERIPHCLK_I2C1             (0x00000020U)
00986 #define RCC_PERIPHCLK_I2C2             (0x00000040U)
00987 #define RCC_PERIPHCLK_ADC1             (0x00000080U)
00988 #define RCC_PERIPHCLK_I2S              (0x00000200U)
00989 #define RCC_PERIPHCLK_TIM1             (0x00001000U)
00990 #define RCC_PERIPHCLK_I2C3             (0x00008000U)
00991 #define RCC_PERIPHCLK_RTC              (0x00010000U)
00992 #define RCC_PERIPHCLK_TIM15            (0x00040000U)
00993 #define RCC_PERIPHCLK_TIM16            (0x00080000U)
00994 #define RCC_PERIPHCLK_TIM17            (0x00100000U)
00995
00996 #endif /* STM32F301x8 || STM32F318xx */
00997
00998 #if defined(STM32F302x8)
00999 #define RCC_PERIPHCLK_USART1           (0x00000001U)
01000 #define RCC_PERIPHCLK_I2C1             (0x00000020U)
01001 #define RCC_PERIPHCLK_I2C2             (0x00000040U)
01002 #define RCC_PERIPHCLK_ADC1             (0x00000080U)
01003 #define RCC_PERIPHCLK_I2S              (0x00000200U)
01004 #define RCC_PERIPHCLK_TIM1             (0x00001000U)
01005 #define RCC_PERIPHCLK_I2C3             (0x00008000U)
01006 #define RCC_PERIPHCLK_RTC              (0x00010000U)
01007 #define RCC_PERIPHCLK_USB              (0x00020000U)
01008 #define RCC_PERIPHCLK_TIM15            (0x00040000U)
01009 #define RCC_PERIPHCLK_TIM16            (0x00080000U)
01010 #define RCC_PERIPHCLK_TIM17            (0x00100000U)
01011
01012
01013 #endif /* STM32F302x8 */
01014
01015 #if defined(STM32F302xC)
01016 #define RCC_PERIPHCLK_USART1           (0x00000001U)
01017 #define RCC_PERIPHCLK_USART2           (0x00000002U)
01018 #define RCC_PERIPHCLK_USART3           (0x00000004U)
01019 #define RCC_PERIPHCLK_UART4            (0x00000008U)
01020 #define RCC_PERIPHCLK_UART5            (0x00000010U)
01021 #define RCC_PERIPHCLK_I2C1             (0x00000020U)
01022 #define RCC_PERIPHCLK_I2C2             (0x00000040U)
01023 #define RCC_PERIPHCLK_ADC12            (0x00000080U)
01024 #define RCC_PERIPHCLK_I2S              (0x00000200U)
01025 #define RCC_PERIPHCLK_TIM1             (0x00001000U)
01026 #define RCC_PERIPHCLK_RTC              (0x00010000U)
01027 #define RCC_PERIPHCLK_USB              (0x00020000U)
01028
01029 #endif /* STM32F302xC */
01030
01031 #if defined(STM32F303xC)
01032 #define RCC_PERIPHCLK_USART1           (0x00000001U)
01033 #define RCC_PERIPHCLK_USART2           (0x00000002U)
01034 #define RCC_PERIPHCLK_USART3           (0x00000004U)
01035 #define RCC_PERIPHCLK_UART4            (0x00000008U)
01036 #define RCC_PERIPHCLK_UART5            (0x00000010U)
01037 #define RCC_PERIPHCLK_I2C1             (0x00000020U)
01038 #define RCC_PERIPHCLK_I2C2             (0x00000040U)
01039 #define RCC_PERIPHCLK_ADC12            (0x00000080U)
01040 #define RCC_PERIPHCLK_ADC34            (0x00000100U)
01041 #define RCC_PERIPHCLK_I2S              (0x00000200U)
01042 #define RCC_PERIPHCLK_TIM1             (0x00001000U)
01043 #define RCC_PERIPHCLK_TIM8             (0x00002000U)
01044 #define RCC_PERIPHCLK_RTC              (0x00010000U)
01045 #define RCC_PERIPHCLK_USB              (0x00020000U)
01046
01047 #endif /* STM32F303xC */
01048
01049 #if defined(STM32F302xE)
01050 #define RCC_PERIPHCLK_USART1           (0x00000001U)
01051 #define RCC_PERIPHCLK_USART2           (0x00000002U)
01052 #define RCC_PERIPHCLK_USART3           (0x00000004U)
01053 #define RCC_PERIPHCLK_UART4            (0x00000008U)
01054 #define RCC_PERIPHCLK_UART5            (0x00000010U)
01055 #define RCC_PERIPHCLK_I2C1             (0x00000020U)
01056 #define RCC_PERIPHCLK_I2C2             (0x00000040U)
01057 #define RCC_PERIPHCLK_ADC12            (0x00000080U)
01058 #define RCC_PERIPHCLK_I2S              (0x00000200U)
01059 #define RCC_PERIPHCLK_TIM1             (0x00001000U)
01060 #define RCC_PERIPHCLK_RTC              (0x00010000U)
01061 #define RCC_PERIPHCLK_USB              (0x00020000U)
01062 #define RCC_PERIPHCLK_I2C3             (0x00040000U)
01063 #define RCC_PERIPHCLK_TIM2             (0x00100000U)
01064 #define RCC_PERIPHCLK_TIM34            (0x00200000U)
01065 #define RCC_PERIPHCLK_TIM15            (0x00400000U)
01066 #define RCC_PERIPHCLK_TIM16            (0x00800000U)
01067 #define RCC_PERIPHCLK_TIM17            (0x01000000U)
01068
01069 #endif /* STM32F302xE */
01070
01071 #if defined(STM32F303xE)
01072 #define RCC_PERIPHCLK_USART1           (0x00000001U)
01073 #define RCC_PERIPHCLK_USART2           (0x00000002U)
01074 #define RCC_PERIPHCLK_USART3           (0x00000004U)
01075 #define RCC_PERIPHCLK_UART4            (0x00000008U)
01076 #define RCC_PERIPHCLK_UART5            (0x00000010U)
01077 #define RCC_PERIPHCLK_I2C1             (0x00000020U)
01078 #define RCC_PERIPHCLK_I2C2             (0x00000040U)
01079 #define RCC_PERIPHCLK_ADC12            (0x00000080U)
01080 #define RCC_PERIPHCLK_ADC34            (0x00000100U)
01081 #define RCC_PERIPHCLK_I2S              (0x00000200U)
01082 #define RCC_PERIPHCLK_TIM1             (0x00001000U)
01083 #define RCC_PERIPHCLK_TIM8             (0x00002000U)
01084 #define RCC_PERIPHCLK_RTC              (0x00010000U)
01085 #define RCC_PERIPHCLK_USB              (0x00020000U)
01086 #define RCC_PERIPHCLK_I2C3             (0x00040000U)
01087 #define RCC_PERIPHCLK_TIM2             (0x00100000U)
01088 #define RCC_PERIPHCLK_TIM34            (0x00200000U)
01089 #define RCC_PERIPHCLK_TIM15            (0x00400000U)
01090 #define RCC_PERIPHCLK_TIM16            (0x00800000U)
01091 #define RCC_PERIPHCLK_TIM17            (0x01000000U)
01092 #define RCC_PERIPHCLK_TIM20            (0x02000000U)
01093
01094 #endif /* STM32F303xE */
01095
01096 #if defined(STM32F398xx)
01097 #define RCC_PERIPHCLK_USART1           (0x00000001U)
01098 #define RCC_PERIPHCLK_USART2           (0x00000002U)
01099 #define RCC_PERIPHCLK_USART3           (0x00000004U)
01100 #define RCC_PERIPHCLK_UART4            (0x00000008U)
01101 #define RCC_PERIPHCLK_UART5            (0x00000010U)
01102 #define RCC_PERIPHCLK_I2C1             (0x00000020U)
01103 #define RCC_PERIPHCLK_I2C2             (0x00000040U)
01104 #define RCC_PERIPHCLK_ADC12            (0x00000080U)
01105 #define RCC_PERIPHCLK_ADC34            (0x00000100U)
01106 #define RCC_PERIPHCLK_I2S              (0x00000200U)
01107 #define RCC_PERIPHCLK_TIM1             (0x00001000U)
01108 #define RCC_PERIPHCLK_TIM8             (0x00002000U)
01109 #define RCC_PERIPHCLK_RTC              (0x00010000U)
01110 #define RCC_PERIPHCLK_I2C3             (0x00040000U)
01111 #define RCC_PERIPHCLK_TIM2             (0x00100000U)
01112 #define RCC_PERIPHCLK_TIM34            (0x00200000U)
01113 #define RCC_PERIPHCLK_TIM15            (0x00400000U)
01114 #define RCC_PERIPHCLK_TIM16            (0x00800000U)
01115 #define RCC_PERIPHCLK_TIM17            (0x01000000U)
01116 #define RCC_PERIPHCLK_TIM20            (0x02000000U)
01117
01118
01119 #endif /* STM32F398xx */
01120
01121 #if defined(STM32F358xx)
01122 #define RCC_PERIPHCLK_USART1           (0x00000001U)
01123 #define RCC_PERIPHCLK_USART2           (0x00000002U)
01124 #define RCC_PERIPHCLK_USART3           (0x00000004U)
01125 #define RCC_PERIPHCLK_UART4            (0x00000008U)
01126 #define RCC_PERIPHCLK_UART5            (0x00000010U)
01127 #define RCC_PERIPHCLK_I2C1             (0x00000020U)
01128 #define RCC_PERIPHCLK_I2C2             (0x00000040U)
01129 #define RCC_PERIPHCLK_ADC12            (0x00000080U)
01130 #define RCC_PERIPHCLK_ADC34            (0x00000100U)
01131 #define RCC_PERIPHCLK_I2S              (0x00000200U)
01132 #define RCC_PERIPHCLK_TIM1             (0x00001000U)
01133 #define RCC_PERIPHCLK_TIM8             (0x00002000U)
01134 #define RCC_PERIPHCLK_RTC              (0x00010000U)
01135
01136 #endif /* STM32F358xx */
01137
01138 #if defined(STM32F303x8)
01139 #define RCC_PERIPHCLK_USART1           (0x00000001U)
01140 #define RCC_PERIPHCLK_I2C1             (0x00000020U)
01141 #define RCC_PERIPHCLK_ADC12            (0x00000080U)
01142 #define RCC_PERIPHCLK_TIM1             (0x00001000U)
01143 #define RCC_PERIPHCLK_RTC              (0x00010000U)
01144
01145 #endif /* STM32F303x8 */
01146
01147 #if defined(STM32F334x8)
01148 #define RCC_PERIPHCLK_USART1           (0x00000001U)
01149 #define RCC_PERIPHCLK_I2C1             (0x00000020U)
01150 #define RCC_PERIPHCLK_ADC12            (0x00000080U)
01151 #define RCC_PERIPHCLK_TIM1             (0x00001000U)
01152 #define RCC_PERIPHCLK_HRTIM1           (0x00004000U)
01153 #define RCC_PERIPHCLK_RTC              (0x00010000U)
01154
01155
01156 #endif /* STM32F334x8 */
01157
01158 #if defined(STM32F328xx)
01159 #define RCC_PERIPHCLK_USART1           (0x00000001U)
01160 #define RCC_PERIPHCLK_I2C1             (0x00000020U)
01161 #define RCC_PERIPHCLK_ADC12            (0x00000080U)
01162 #define RCC_PERIPHCLK_TIM1             (0x00001000U)
01163 #define RCC_PERIPHCLK_RTC              (0x00010000U)
01164
01165 #endif /* STM32F328xx */
01166
01167 #if defined(STM32F373xC)
01168 #define RCC_PERIPHCLK_USART1           (0x00000001U)
01169 #define RCC_PERIPHCLK_USART2           (0x00000002U)
01170 #define RCC_PERIPHCLK_USART3           (0x00000004U)
01171 #define RCC_PERIPHCLK_I2C1             (0x00000020U)
01172 #define RCC_PERIPHCLK_I2C2             (0x00000040U)
01173 #define RCC_PERIPHCLK_ADC1             (0x00000080U)
01174 #define RCC_PERIPHCLK_CEC              (0x00000400U)
01175 #define RCC_PERIPHCLK_SDADC            (0x00000800U)
01176 #define RCC_PERIPHCLK_RTC              (0x00010000U)
01177 #define RCC_PERIPHCLK_USB              (0x00020000U)
01178
01179 #endif /* STM32F373xC */
01180
01181 #if defined(STM32F378xx)
01182 #define RCC_PERIPHCLK_USART1           (0x00000001U)
01183 #define RCC_PERIPHCLK_USART2           (0x00000002U)
01184 #define RCC_PERIPHCLK_USART3           (0x00000004U)
01185 #define RCC_PERIPHCLK_I2C1             (0x00000020U)
01186 #define RCC_PERIPHCLK_I2C2             (0x00000040U)
01187 #define RCC_PERIPHCLK_ADC1             (0x00000080U)
01188 #define RCC_PERIPHCLK_CEC              (0x00000400U)
01189 #define RCC_PERIPHCLK_SDADC            (0x00000800U)
01190 #define RCC_PERIPHCLK_RTC              (0x00010000U)
01191
01192 #endif /* STM32F378xx */
01193 /**
01194   * @}
01195   */
01196
01197 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01198
01199 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
01200   * @{
01201   */
01202 #define RCC_USART1CLKSOURCE_PCLK1        RCC_CFGR3_USART1SW_PCLK1
01203 #define RCC_USART1CLKSOURCE_SYSCLK       RCC_CFGR3_USART1SW_SYSCLK
01204 #define RCC_USART1CLKSOURCE_LSE          RCC_CFGR3_USART1SW_LSE
01205 #define RCC_USART1CLKSOURCE_HSI          RCC_CFGR3_USART1SW_HSI
01206
01207 /**
01208   * @}
01209   */
01210
01211 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
01212   * @{
01213   */
01214 #define RCC_I2C2CLKSOURCE_HSI            RCC_CFGR3_I2C2SW_HSI
01215 #define RCC_I2C2CLKSOURCE_SYSCLK         RCC_CFGR3_I2C2SW_SYSCLK
01216
01217 /**
01218   * @}
01219   */
01220
01221 /** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
01222   * @{
01223   */
01224 #define RCC_I2C3CLKSOURCE_HSI            RCC_CFGR3_I2C3SW_HSI
01225 #define RCC_I2C3CLKSOURCE_SYSCLK         RCC_CFGR3_I2C3SW_SYSCLK
01226
01227 /**
01228   * @}
01229   */
01230
01231 /** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
01232   * @{
01233   */
01234 #define RCC_ADC1PLLCLK_OFF               RCC_CFGR2_ADC1PRES_NO
01235 #define RCC_ADC1PLLCLK_DIV1              RCC_CFGR2_ADC1PRES_DIV1
01236 #define RCC_ADC1PLLCLK_DIV2              RCC_CFGR2_ADC1PRES_DIV2
01237 #define RCC_ADC1PLLCLK_DIV4              RCC_CFGR2_ADC1PRES_DIV4
01238 #define RCC_ADC1PLLCLK_DIV6              RCC_CFGR2_ADC1PRES_DIV6
01239 #define RCC_ADC1PLLCLK_DIV8              RCC_CFGR2_ADC1PRES_DIV8
01240 #define RCC_ADC1PLLCLK_DIV10             RCC_CFGR2_ADC1PRES_DIV10
01241 #define RCC_ADC1PLLCLK_DIV12             RCC_CFGR2_ADC1PRES_DIV12
01242 #define RCC_ADC1PLLCLK_DIV16             RCC_CFGR2_ADC1PRES_DIV16
01243 #define RCC_ADC1PLLCLK_DIV32             RCC_CFGR2_ADC1PRES_DIV32
01244 #define RCC_ADC1PLLCLK_DIV64             RCC_CFGR2_ADC1PRES_DIV64
01245 #define RCC_ADC1PLLCLK_DIV128            RCC_CFGR2_ADC1PRES_DIV128
01246 #define RCC_ADC1PLLCLK_DIV256            RCC_CFGR2_ADC1PRES_DIV256
01247
01248 /**
01249   * @}
01250   */
01251
01252 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
01253   * @{
01254   */
01255 #define RCC_I2SCLKSOURCE_SYSCLK          RCC_CFGR_I2SSRC_SYSCLK
01256 #define RCC_I2SCLKSOURCE_EXT             RCC_CFGR_I2SSRC_EXT
01257
01258 /**
01259   * @}
01260   */
01261
01262 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
01263   * @{
01264   */
01265 #define RCC_TIM1CLK_HCLK                  RCC_CFGR3_TIM1SW_HCLK
01266 #define RCC_TIM1CLK_PLLCLK                RCC_CFGR3_TIM1SW_PLL
01267
01268 /**
01269   * @}
01270   */
01271
01272 /** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
01273   * @{
01274   */
01275 #define RCC_TIM15CLK_HCLK                 RCC_CFGR3_TIM15SW_HCLK
01276 #define RCC_TIM15CLK_PLLCLK               RCC_CFGR3_TIM15SW_PLL
01277
01278 /**
01279   * @}
01280   */
01281
01282 /** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
01283   * @{
01284   */
01285 #define RCC_TIM16CLK_HCLK                 RCC_CFGR3_TIM16SW_HCLK
01286 #define RCC_TIM16CLK_PLLCLK               RCC_CFGR3_TIM16SW_PLL
01287
01288 /**
01289   * @}
01290   */
01291
01292 /** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
01293   * @{
01294   */
01295 #define RCC_TIM17CLK_HCLK                 RCC_CFGR3_TIM17SW_HCLK
01296 #define RCC_TIM17CLK_PLLCLK               RCC_CFGR3_TIM17SW_PLL
01297
01298 /**
01299   * @}
01300   */
01301
01302 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
01303
01304 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
01305
01306 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
01307   * @{
01308   */
01309 #define RCC_USART1CLKSOURCE_PCLK2        RCC_CFGR3_USART1SW_PCLK2
01310 #define RCC_USART1CLKSOURCE_SYSCLK       RCC_CFGR3_USART1SW_SYSCLK
01311 #define RCC_USART1CLKSOURCE_LSE          RCC_CFGR3_USART1SW_LSE
01312 #define RCC_USART1CLKSOURCE_HSI          RCC_CFGR3_USART1SW_HSI
01313
01314 /**
01315   * @}
01316   */
01317
01318 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
01319   * @{
01320   */
01321 #define RCC_I2C2CLKSOURCE_HSI            RCC_CFGR3_I2C2SW_HSI
01322 #define RCC_I2C2CLKSOURCE_SYSCLK         RCC_CFGR3_I2C2SW_SYSCLK
01323
01324 /**
01325   * @}
01326   */
01327
01328 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
01329   * @{
01330   */
01331
01332 /* ADC1 & ADC2 */
01333 #define RCC_ADC12PLLCLK_OFF              RCC_CFGR2_ADCPRE12_NO
01334 #define RCC_ADC12PLLCLK_DIV1             RCC_CFGR2_ADCPRE12_DIV1
01335 #define RCC_ADC12PLLCLK_DIV2             RCC_CFGR2_ADCPRE12_DIV2
01336 #define RCC_ADC12PLLCLK_DIV4             RCC_CFGR2_ADCPRE12_DIV4
01337 #define RCC_ADC12PLLCLK_DIV6             RCC_CFGR2_ADCPRE12_DIV6
01338 #define RCC_ADC12PLLCLK_DIV8             RCC_CFGR2_ADCPRE12_DIV8
01339 #define RCC_ADC12PLLCLK_DIV10            RCC_CFGR2_ADCPRE12_DIV10
01340 #define RCC_ADC12PLLCLK_DIV12            RCC_CFGR2_ADCPRE12_DIV12
01341 #define RCC_ADC12PLLCLK_DIV16            RCC_CFGR2_ADCPRE12_DIV16
01342 #define RCC_ADC12PLLCLK_DIV32            RCC_CFGR2_ADCPRE12_DIV32
01343 #define RCC_ADC12PLLCLK_DIV64            RCC_CFGR2_ADCPRE12_DIV64
01344 #define RCC_ADC12PLLCLK_DIV128           RCC_CFGR2_ADCPRE12_DIV128
01345 #define RCC_ADC12PLLCLK_DIV256           RCC_CFGR2_ADCPRE12_DIV256
01346
01347 /**
01348   * @}
01349   */
01350
01351 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
01352   * @{
01353   */
01354 #define RCC_I2SCLKSOURCE_SYSCLK          RCC_CFGR_I2SSRC_SYSCLK
01355 #define RCC_I2SCLKSOURCE_EXT             RCC_CFGR_I2SSRC_EXT
01356
01357 /**
01358   * @}
01359   */
01360 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
01361   * @{
01362   */
01363 #define RCC_TIM1CLK_HCLK                  RCC_CFGR3_TIM1SW_HCLK
01364 #define RCC_TIM1CLK_PLLCLK                RCC_CFGR3_TIM1SW_PLL
01365
01366 /**
01367   * @}
01368   */
01369
01370 /** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
01371   * @{
01372   */
01373 #define RCC_UART4CLKSOURCE_PCLK1         RCC_CFGR3_UART4SW_PCLK
01374 #define RCC_UART4CLKSOURCE_SYSCLK        RCC_CFGR3_UART4SW_SYSCLK
01375 #define RCC_UART4CLKSOURCE_LSE           RCC_CFGR3_UART4SW_LSE
01376 #define RCC_UART4CLKSOURCE_HSI           RCC_CFGR3_UART4SW_HSI
01377
01378 /**
01379   * @}
01380   */
01381
01382 /** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
01383   * @{
01384   */
01385 #define RCC_UART5CLKSOURCE_PCLK1         RCC_CFGR3_UART5SW_PCLK
01386 #define RCC_UART5CLKSOURCE_SYSCLK        RCC_CFGR3_UART5SW_SYSCLK
01387 #define RCC_UART5CLKSOURCE_LSE           RCC_CFGR3_UART5SW_LSE
01388 #define RCC_UART5CLKSOURCE_HSI           RCC_CFGR3_UART5SW_HSI
01389
01390 /**
01391   * @}
01392   */
01393
01394 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
01395
01396 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
01397
01398 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
01399   * @{
01400   */
01401 #define RCC_USART1CLKSOURCE_PCLK2        RCC_CFGR3_USART1SW_PCLK2
01402 #define RCC_USART1CLKSOURCE_SYSCLK       RCC_CFGR3_USART1SW_SYSCLK
01403 #define RCC_USART1CLKSOURCE_LSE          RCC_CFGR3_USART1SW_LSE
01404 #define RCC_USART1CLKSOURCE_HSI          RCC_CFGR3_USART1SW_HSI
01405
01406 /**
01407   * @}
01408   */
01409
01410 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
01411   * @{
01412   */
01413 #define RCC_I2C2CLKSOURCE_HSI            RCC_CFGR3_I2C2SW_HSI
01414 #define RCC_I2C2CLKSOURCE_SYSCLK         RCC_CFGR3_I2C2SW_SYSCLK
01415
01416 /**
01417   * @}
01418   */
01419
01420 /** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
01421   * @{
01422   */
01423 #define RCC_I2C3CLKSOURCE_HSI            RCC_CFGR3_I2C3SW_HSI
01424 #define RCC_I2C3CLKSOURCE_SYSCLK         RCC_CFGR3_I2C3SW_SYSCLK
01425
01426 /**
01427   * @}
01428   */
01429
01430 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
01431   * @{
01432   */
01433
01434 /* ADC1 & ADC2 */
01435 #define RCC_ADC12PLLCLK_OFF              RCC_CFGR2_ADCPRE12_NO
01436 #define RCC_ADC12PLLCLK_DIV1             RCC_CFGR2_ADCPRE12_DIV1
01437 #define RCC_ADC12PLLCLK_DIV2             RCC_CFGR2_ADCPRE12_DIV2
01438 #define RCC_ADC12PLLCLK_DIV4             RCC_CFGR2_ADCPRE12_DIV4
01439 #define RCC_ADC12PLLCLK_DIV6             RCC_CFGR2_ADCPRE12_DIV6
01440 #define RCC_ADC12PLLCLK_DIV8             RCC_CFGR2_ADCPRE12_DIV8
01441 #define RCC_ADC12PLLCLK_DIV10            RCC_CFGR2_ADCPRE12_DIV10
01442 #define RCC_ADC12PLLCLK_DIV12            RCC_CFGR2_ADCPRE12_DIV12
01443 #define RCC_ADC12PLLCLK_DIV16            RCC_CFGR2_ADCPRE12_DIV16
01444 #define RCC_ADC12PLLCLK_DIV32            RCC_CFGR2_ADCPRE12_DIV32
01445 #define RCC_ADC12PLLCLK_DIV64            RCC_CFGR2_ADCPRE12_DIV64
01446 #define RCC_ADC12PLLCLK_DIV128           RCC_CFGR2_ADCPRE12_DIV128
01447 #define RCC_ADC12PLLCLK_DIV256           RCC_CFGR2_ADCPRE12_DIV256
01448
01449 /**
01450   * @}
01451   */
01452
01453 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
01454   * @{
01455   */
01456 #define RCC_I2SCLKSOURCE_SYSCLK          RCC_CFGR_I2SSRC_SYSCLK
01457 #define RCC_I2SCLKSOURCE_EXT             RCC_CFGR_I2SSRC_EXT
01458
01459 /**
01460   * @}
01461   */
01462
01463 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
01464   * @{
01465   */
01466 #define RCC_TIM1CLK_HCLK                  RCC_CFGR3_TIM1SW_HCLK
01467 #define RCC_TIM1CLK_PLLCLK                RCC_CFGR3_TIM1SW_PLL
01468
01469 /**
01470   * @}
01471   */
01472
01473 /** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source
01474   * @{
01475   */
01476 #define RCC_TIM2CLK_HCLK                  RCC_CFGR3_TIM2SW_HCLK
01477 #define RCC_TIM2CLK_PLLCLK                RCC_CFGR3_TIM2SW_PLL
01478
01479 /**
01480   * @}
01481   */
01482
01483 /** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source
01484   * @{
01485   */
01486 #define RCC_TIM34CLK_HCLK                  RCC_CFGR3_TIM34SW_HCLK
01487 #define RCC_TIM34CLK_PLLCLK                RCC_CFGR3_TIM34SW_PLL
01488
01489 /**
01490   * @}
01491   */
01492
01493 /** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
01494   * @{
01495   */
01496 #define RCC_TIM15CLK_HCLK                  RCC_CFGR3_TIM15SW_HCLK
01497 #define RCC_TIM15CLK_PLLCLK                RCC_CFGR3_TIM15SW_PLL
01498
01499 /**
01500   * @}
01501   */
01502
01503 /** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
01504   * @{
01505   */
01506 #define RCC_TIM16CLK_HCLK                  RCC_CFGR3_TIM16SW_HCLK
01507 #define RCC_TIM16CLK_PLLCLK                RCC_CFGR3_TIM16SW_PLL
01508
01509 /**
01510   * @}
01511   */
01512
01513 /** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
01514   * @{
01515   */
01516 #define RCC_TIM17CLK_HCLK                  RCC_CFGR3_TIM17SW_HCLK
01517 #define RCC_TIM17CLK_PLLCLK                RCC_CFGR3_TIM17SW_PLL
01518
01519 /**
01520   * @}
01521   */
01522
01523 /** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
01524   * @{
01525   */
01526 #define RCC_UART4CLKSOURCE_PCLK1         RCC_CFGR3_UART4SW_PCLK
01527 #define RCC_UART4CLKSOURCE_SYSCLK        RCC_CFGR3_UART4SW_SYSCLK
01528 #define RCC_UART4CLKSOURCE_LSE           RCC_CFGR3_UART4SW_LSE
01529 #define RCC_UART4CLKSOURCE_HSI           RCC_CFGR3_UART4SW_HSI
01530
01531 /**
01532   * @}
01533   */
01534
01535 /** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
01536   * @{
01537   */
01538 #define RCC_UART5CLKSOURCE_PCLK1         RCC_CFGR3_UART5SW_PCLK
01539 #define RCC_UART5CLKSOURCE_SYSCLK        RCC_CFGR3_UART5SW_SYSCLK
01540 #define RCC_UART5CLKSOURCE_LSE           RCC_CFGR3_UART5SW_LSE
01541 #define RCC_UART5CLKSOURCE_HSI           RCC_CFGR3_UART5SW_HSI
01542
01543 /**
01544   * @}
01545   */
01546
01547 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
01548
01549 #if defined(STM32F303xE) ||  defined(STM32F398xx)
01550 /** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source
01551   * @{
01552   */
01553 #define RCC_TIM20CLK_HCLK                  RCC_CFGR3_TIM20SW_HCLK
01554 #define RCC_TIM20CLK_PLLCLK                RCC_CFGR3_TIM20SW_PLL
01555
01556 /**
01557   * @}
01558   */
01559 #endif /* STM32F303xE || STM32F398xx */
01560
01561 #if defined(STM32F303xE) || defined(STM32F398xx)\
01562   || defined(STM32F303xC) || defined(STM32F358xx)
01563
01564 /** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source
01565   * @{
01566   */
01567
01568 /* ADC3 & ADC4 */
01569 #define RCC_ADC34PLLCLK_OFF              RCC_CFGR2_ADCPRE34_NO
01570 #define RCC_ADC34PLLCLK_DIV1             RCC_CFGR2_ADCPRE34_DIV1
01571 #define RCC_ADC34PLLCLK_DIV2             RCC_CFGR2_ADCPRE34_DIV2
01572 #define RCC_ADC34PLLCLK_DIV4             RCC_CFGR2_ADCPRE34_DIV4
01573 #define RCC_ADC34PLLCLK_DIV6             RCC_CFGR2_ADCPRE34_DIV6
01574 #define RCC_ADC34PLLCLK_DIV8             RCC_CFGR2_ADCPRE34_DIV8
01575 #define RCC_ADC34PLLCLK_DIV10            RCC_CFGR2_ADCPRE34_DIV10
01576 #define RCC_ADC34PLLCLK_DIV12            RCC_CFGR2_ADCPRE34_DIV12
01577 #define RCC_ADC34PLLCLK_DIV16            RCC_CFGR2_ADCPRE34_DIV16
01578 #define RCC_ADC34PLLCLK_DIV32            RCC_CFGR2_ADCPRE34_DIV32
01579 #define RCC_ADC34PLLCLK_DIV64            RCC_CFGR2_ADCPRE34_DIV64
01580 #define RCC_ADC34PLLCLK_DIV128           RCC_CFGR2_ADCPRE34_DIV128
01581 #define RCC_ADC34PLLCLK_DIV256           RCC_CFGR2_ADCPRE34_DIV256
01582
01583 /**
01584   * @}
01585   */
01586
01587 /** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source
01588   * @{
01589   */
01590 #define RCC_TIM8CLK_HCLK                  RCC_CFGR3_TIM8SW_HCLK
01591 #define RCC_TIM8CLK_PLLCLK                RCC_CFGR3_TIM8SW_PLL
01592
01593 /**
01594   * @}
01595   */
01596
01597 #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
01598
01599 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
01600
01601 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
01602   * @{
01603   */
01604 #define RCC_USART1CLKSOURCE_PCLK1        RCC_CFGR3_USART1SW_PCLK1
01605 #define RCC_USART1CLKSOURCE_SYSCLK       RCC_CFGR3_USART1SW_SYSCLK
01606 #define RCC_USART1CLKSOURCE_LSE          RCC_CFGR3_USART1SW_LSE
01607 #define RCC_USART1CLKSOURCE_HSI          RCC_CFGR3_USART1SW_HSI
01608
01609 /**
01610   * @}
01611   */
01612
01613 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
01614   * @{
01615   */
01616 /* ADC1 & ADC2 */
01617 #define RCC_ADC12PLLCLK_OFF              RCC_CFGR2_ADCPRE12_NO
01618 #define RCC_ADC12PLLCLK_DIV1             RCC_CFGR2_ADCPRE12_DIV1
01619 #define RCC_ADC12PLLCLK_DIV2             RCC_CFGR2_ADCPRE12_DIV2
01620 #define RCC_ADC12PLLCLK_DIV4             RCC_CFGR2_ADCPRE12_DIV4
01621 #define RCC_ADC12PLLCLK_DIV6             RCC_CFGR2_ADCPRE12_DIV6
01622 #define RCC_ADC12PLLCLK_DIV8             RCC_CFGR2_ADCPRE12_DIV8
01623 #define RCC_ADC12PLLCLK_DIV10            RCC_CFGR2_ADCPRE12_DIV10
01624 #define RCC_ADC12PLLCLK_DIV12            RCC_CFGR2_ADCPRE12_DIV12
01625 #define RCC_ADC12PLLCLK_DIV16            RCC_CFGR2_ADCPRE12_DIV16
01626 #define RCC_ADC12PLLCLK_DIV32            RCC_CFGR2_ADCPRE12_DIV32
01627 #define RCC_ADC12PLLCLK_DIV64            RCC_CFGR2_ADCPRE12_DIV64
01628 #define RCC_ADC12PLLCLK_DIV128           RCC_CFGR2_ADCPRE12_DIV128
01629 #define RCC_ADC12PLLCLK_DIV256           RCC_CFGR2_ADCPRE12_DIV256
01630
01631 /**
01632   * @}
01633   */
01634
01635 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
01636   * @{
01637   */
01638 #define RCC_TIM1CLK_HCLK                  RCC_CFGR3_TIM1SW_HCLK
01639 #define RCC_TIM1CLK_PLLCLK                RCC_CFGR3_TIM1SW_PLL
01640
01641 /**
01642   * @}
01643   */
01644
01645 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
01646
01647 #if defined(STM32F334x8)
01648
01649 /** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
01650   * @{
01651   */
01652 #define RCC_HRTIM1CLK_HCLK                RCC_CFGR3_HRTIM1SW_HCLK
01653 #define RCC_HRTIM1CLK_PLLCLK              RCC_CFGR3_HRTIM1SW_PLL
01654
01655 /**
01656   * @}
01657   */
01658
01659 #endif /* STM32F334x8 */
01660
01661 #if defined(STM32F373xC) || defined(STM32F378xx)
01662
01663 /** @defgroup RCCEx_USART1_Clock_Source  RCC Extended USART1 Clock Source
01664   * @{
01665   */
01666 #define RCC_USART1CLKSOURCE_PCLK2        RCC_CFGR3_USART1SW_PCLK2
01667 #define RCC_USART1CLKSOURCE_SYSCLK       RCC_CFGR3_USART1SW_SYSCLK
01668 #define RCC_USART1CLKSOURCE_LSE          RCC_CFGR3_USART1SW_LSE
01669 #define RCC_USART1CLKSOURCE_HSI          RCC_CFGR3_USART1SW_HSI
01670
01671 /**
01672   * @}
01673   */
01674
01675 /** @defgroup RCCEx_I2C2_Clock_Source  RCC Extended I2C2 Clock Source
01676   * @{
01677   */
01678 #define RCC_I2C2CLKSOURCE_HSI            RCC_CFGR3_I2C2SW_HSI
01679 #define RCC_I2C2CLKSOURCE_SYSCLK         RCC_CFGR3_I2C2SW_SYSCLK
01680
01681 /**
01682   * @}
01683   */
01684
01685 /** @defgroup RCCEx_ADC1_Clock_Source  RCC Extended ADC1 Clock Source
01686   * @{
01687   */
01688
01689 /* ADC1 */
01690 #define RCC_ADC1PCLK2_DIV2               RCC_CFGR_ADCPRE_DIV2
01691 #define RCC_ADC1PCLK2_DIV4               RCC_CFGR_ADCPRE_DIV4
01692 #define RCC_ADC1PCLK2_DIV6               RCC_CFGR_ADCPRE_DIV6
01693 #define RCC_ADC1PCLK2_DIV8               RCC_CFGR_ADCPRE_DIV8
01694
01695 /**
01696   * @}
01697   */
01698
01699 /** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source
01700   * @{
01701   */
01702 #define RCC_CECCLKSOURCE_HSI             RCC_CFGR3_CECSW_HSI_DIV244
01703 #define RCC_CECCLKSOURCE_LSE             RCC_CFGR3_CECSW_LSE
01704
01705 /**
01706   * @}
01707   */
01708
01709 /** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler
01710   * @{
01711   */
01712 #define RCC_SDADCSYSCLK_DIV1             RCC_CFGR_SDPRE_DIV1
01713 #define RCC_SDADCSYSCLK_DIV2             RCC_CFGR_SDPRE_DIV2
01714 #define RCC_SDADCSYSCLK_DIV4             RCC_CFGR_SDPRE_DIV4
01715 #define RCC_SDADCSYSCLK_DIV6             RCC_CFGR_SDPRE_DIV6
01716 #define RCC_SDADCSYSCLK_DIV8             RCC_CFGR_SDPRE_DIV8
01717 #define RCC_SDADCSYSCLK_DIV10            RCC_CFGR_SDPRE_DIV10
01718 #define RCC_SDADCSYSCLK_DIV12            RCC_CFGR_SDPRE_DIV12
01719 #define RCC_SDADCSYSCLK_DIV14            RCC_CFGR_SDPRE_DIV14
01720 #define RCC_SDADCSYSCLK_DIV16            RCC_CFGR_SDPRE_DIV16
01721 #define RCC_SDADCSYSCLK_DIV20            RCC_CFGR_SDPRE_DIV20
01722 #define RCC_SDADCSYSCLK_DIV24            RCC_CFGR_SDPRE_DIV24
01723 #define RCC_SDADCSYSCLK_DIV28            RCC_CFGR_SDPRE_DIV28
01724 #define RCC_SDADCSYSCLK_DIV32            RCC_CFGR_SDPRE_DIV32
01725 #define RCC_SDADCSYSCLK_DIV36            RCC_CFGR_SDPRE_DIV36
01726 #define RCC_SDADCSYSCLK_DIV40            RCC_CFGR_SDPRE_DIV40
01727 #define RCC_SDADCSYSCLK_DIV44            RCC_CFGR_SDPRE_DIV44
01728 #define RCC_SDADCSYSCLK_DIV48            RCC_CFGR_SDPRE_DIV48
01729
01730 /**
01731   * @}
01732   */
01733
01734 #endif /* STM32F373xC || STM32F378xx */
01735
01736 #if defined(STM32F302xE) || defined(STM32F303xE)\
01737   || defined(STM32F302xC) || defined(STM32F303xC)\
01738   || defined(STM32F302x8)                        \
01739   || defined(STM32F373xC)
01740 /** @defgroup RCCEx_USB_Clock_Source  RCC Extended USB Clock Source
01741   * @{
01742   */
01743
01744 #define RCC_USBCLKSOURCE_PLL               RCC_CFGR_USBPRE_DIV1
01745 #define RCC_USBCLKSOURCE_PLL_DIV1_5             RCC_CFGR_USBPRE_DIV1_5
01746
01747 /**
01748   * @}
01749   */
01750
01751 #endif /* STM32F302xE || STM32F303xE || */
01752        /* STM32F302xC || STM32F303xC || */
01753        /* STM32F302x8                || */
01754        /* STM32F373xC                   */
01755
01756
01757 /** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
01758   * @{
01759   */
01760 #if defined(RCC_CFGR_MCOPRE)
01761
01762 #define RCC_MCODIV_1                     (0x00000000U)
01763 #define RCC_MCODIV_2                     (0x10000000U)
01764 #define RCC_MCODIV_4                     (0x20000000U)
01765 #define RCC_MCODIV_8                     (0x30000000U)
01766 #define RCC_MCODIV_16                    (0x40000000U)
01767 #define RCC_MCODIV_32                    (0x50000000U)
01768 #define RCC_MCODIV_64                    (0x60000000U)
01769 #define RCC_MCODIV_128                   (0x70000000U)
01770
01771 #else
01772
01773 #define RCC_MCODIV_1                    (0x00000000U)
01774
01775 #endif /* RCC_CFGR_MCOPRE */
01776
01777 /**
01778   * @}
01779   */
01780
01781 /** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration
01782   * @{
01783   */
01784
01785 #define RCC_LSEDRIVE_LOW                 (0x00000000U) /*!< Xtal mode lower driving capability */
01786 #define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_1      /*!< Xtal mode medium low driving capability */
01787 #define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_0      /*!< Xtal mode medium high driving capability */
01788 #define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV        /*!< Xtal mode higher driving capability */
01789
01790 /**
01791   * @}
01792   */
01793
01794 /**
01795   * @}
01796   */
01797
01798 /* Exported macro ------------------------------------------------------------*/
01799 /** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros
01800  * @{
01801  */
01802
01803 /** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration
01804   * @{
01805   */
01806 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
01807 /** @brief  Macro to configure the PLL clock source, multiplication and division factors.
01808   * @note   This macro must be used only when the PLL is disabled.
01809   *
01810   * @param  __RCC_PLLSource__ specifies the PLL entry clock source.
01811   *         This parameter can be one of the following values:
01812   *            @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
01813   *            @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
01814   * @param  __PREDIV__ specifies the predivider factor for PLL VCO input clock
01815   *         This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
01816   * @param  __PLLMUL__ specifies the multiplication factor for PLL VCO input clock
01817   *         This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
01818   *
01819   */
01820 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
01821                   do { \
01822                     MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
01823                     MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
01824                   } while(0U)
01825 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
01826
01827 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
01828   || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
01829   || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
01830   || defined(STM32F373xC) || defined(STM32F378xx)
01831 /** @brief  Macro to configure the PLL clock source and multiplication factor.
01832   * @note   This macro must be used only when the PLL is disabled.
01833   *
01834   * @param  __RCC_PLLSource__ specifies the PLL entry clock source.
01835   *         This parameter can be one of the following values:
01836   *            @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
01837   *            @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
01838   * @param  __PLLMUL__ specifies the multiplication factor for PLL VCO input clock
01839   *         This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
01840   *
01841   */
01842 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \
01843                   MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__)))
01844 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
01845        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
01846        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
01847        /* STM32F373xC || STM32F378xx                   */
01848 /**
01849   * @}
01850   */
01851
01852 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
01853   || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
01854   || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
01855   || defined(STM32F373xC) || defined(STM32F378xx)
01856 /** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration
01857   * @{
01858   */
01859
01860 /**
01861   * @brief  Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
01862   * @note   Predivision factor can not be changed if PLL is used as system clock
01863   *         In this case, you have to select another source of the system clock, disable the PLL and
01864   *         then change the HSE predivision factor.
01865   * @param  __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
01866   *         This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
01867   */
01868 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
01869                   MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
01870
01871 /**
01872   * @brief  Macro to get prediv1 factor for PLL.
01873   */
01874 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)
01875
01876 /**
01877   * @}
01878   */
01879 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
01880        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
01881        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
01882        /* STM32F373xC || STM32F378xx                   */
01883
01884 /** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable
01885   * @brief  Enable or disable the AHB peripheral clock.
01886   * @note   After reset, the peripheral clock (used for registers read/write access)
01887   *         is disabled and the application software has to enable this clock before
01888   *         using it.
01889   * @{
01890   */
01891 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01892 #define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
01893                                         __IO uint32_t tmpreg; \
01894                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
01895                                         /* Delay after an RCC peripheral clock enabling */ \
01896                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
01897                                         UNUSED(tmpreg); \
01898                                       } while(0U)
01899
01900 #define __HAL_RCC_ADC1_CLK_DISABLE()         (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
01901 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
01902
01903 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
01904   || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
01905 #define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
01906                                         __IO uint32_t tmpreg; \
01907                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
01908                                         /* Delay after an RCC peripheral clock enabling */ \
01909                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
01910                                         UNUSED(tmpreg); \
01911                                       } while(0U)
01912 #define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
01913                                         __IO uint32_t tmpreg; \
01914                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
01915                                         /* Delay after an RCC peripheral clock enabling */ \
01916                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
01917                                         UNUSED(tmpreg); \
01918                                       } while(0U)
01919 #define __HAL_RCC_ADC12_CLK_ENABLE()   do { \
01920                                         __IO uint32_t tmpreg; \
01921                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
01922                                         /* Delay after an RCC peripheral clock enabling */ \
01923                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
01924                                         UNUSED(tmpreg); \
01925                                       } while(0U)
01926 /* Aliases for STM32 F3 compatibility */
01927 #define __HAL_RCC_ADC1_CLK_ENABLE()          __HAL_RCC_ADC12_CLK_ENABLE()
01928 #define __HAL_RCC_ADC2_CLK_ENABLE()          __HAL_RCC_ADC12_CLK_ENABLE()
01929
01930 #define __HAL_RCC_DMA2_CLK_DISABLE()         (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
01931 #define __HAL_RCC_GPIOE_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
01932 #define __HAL_RCC_ADC12_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
01933 /* Aliases for STM32 F3 compatibility */
01934 #define __HAL_RCC_ADC1_CLK_DISABLE()          __HAL_RCC_ADC12_CLK_DISABLE()
01935 #define __HAL_RCC_ADC2_CLK_DISABLE()          __HAL_RCC_ADC12_CLK_DISABLE()
01936 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
01937        /* STM32F302xC || STM32F303xC || STM32F358xx    */
01938
01939 #if defined(STM32F303xE) || defined(STM32F398xx)\
01940   || defined(STM32F303xC) || defined(STM32F358xx)
01941 #define __HAL_RCC_ADC34_CLK_ENABLE()   do { \
01942                                         __IO uint32_t tmpreg; \
01943                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\
01944                                         /* Delay after an RCC peripheral clock enabling */ \
01945                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\
01946                                         UNUSED(tmpreg); \
01947                                       } while(0U)
01948 #define __HAL_RCC_ADC34_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
01949 #endif /* STM32F303xE || STM32F398xx || */
01950        /* STM32F303xC || STM32F358xx    */
01951
01952 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
01953 #define __HAL_RCC_ADC12_CLK_ENABLE()   do { \
01954                                         __IO uint32_t tmpreg; \
01955                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
01956                                         /* Delay after an RCC peripheral clock enabling */ \
01957                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
01958                                         UNUSED(tmpreg); \
01959                                       } while(0U)
01960 /* Aliases for STM32 F3 compatibility */
01961 #define __HAL_RCC_ADC1_CLK_ENABLE()          __HAL_RCC_ADC12_CLK_ENABLE()
01962 #define __HAL_RCC_ADC2_CLK_ENABLE()          __HAL_RCC_ADC12_CLK_ENABLE()
01963
01964 #define __HAL_RCC_ADC12_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
01965 /* Aliases for STM32 F3 compatibility */
01966 #define __HAL_RCC_ADC1_CLK_DISABLE()          __HAL_RCC_ADC12_CLK_DISABLE()
01967 #define __HAL_RCC_ADC2_CLK_DISABLE()          __HAL_RCC_ADC12_CLK_DISABLE()
01968 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
01969
01970 #if defined(STM32F373xC) || defined(STM32F378xx)
01971 #define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
01972                                         __IO uint32_t tmpreg; \
01973                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
01974                                         /* Delay after an RCC peripheral clock enabling */ \
01975                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
01976                                         UNUSED(tmpreg); \
01977                                       } while(0U)
01978 #define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
01979                                         __IO uint32_t tmpreg; \
01980                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
01981                                         /* Delay after an RCC peripheral clock enabling */ \
01982                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
01983                                         UNUSED(tmpreg); \
01984                                       } while(0U)
01985
01986 #define __HAL_RCC_DMA2_CLK_DISABLE()         (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
01987 #define __HAL_RCC_GPIOE_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
01988 #endif /* STM32F373xC || STM32F378xx */
01989
01990 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
01991 #define __HAL_RCC_FMC_CLK_ENABLE()   do { \
01992                                         __IO uint32_t tmpreg; \
01993                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\
01994                                         /* Delay after an RCC peripheral clock enabling */ \
01995                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\
01996                                         UNUSED(tmpreg); \
01997                                       } while(0U)
01998 #define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
01999                                         __IO uint32_t tmpreg; \
02000                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
02001                                         /* Delay after an RCC peripheral clock enabling */ \
02002                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
02003                                         UNUSED(tmpreg); \
02004                                       } while(0U)
02005 #define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
02006                                         __IO uint32_t tmpreg; \
02007                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
02008                                         /* Delay after an RCC peripheral clock enabling */ \
02009                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
02010                                         UNUSED(tmpreg); \
02011                                       } while(0U)
02012
02013 #define __HAL_RCC_FMC_CLK_DISABLE()           (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN))
02014 #define __HAL_RCC_GPIOG_CLK_DISABLE()         (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
02015 #define __HAL_RCC_GPIOH_CLK_DISABLE()         (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
02016 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
02017 /**
02018   * @}
02019   */
02020
02021 /** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable
02022   * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
02023   * @note   After reset, the peripheral clock (used for registers read/write access)
02024   *         is disabled and the application software has to enable this clock before
02025   *         using it.
02026   * @{
02027   */
02028 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02029 #define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
02030                                         __IO uint32_t tmpreg; \
02031                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
02032                                         /* Delay after an RCC peripheral clock enabling */ \
02033                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
02034                                         UNUSED(tmpreg); \
02035                                       } while(0U)
02036 #define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
02037                                         __IO uint32_t tmpreg; \
02038                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
02039                                         /* Delay after an RCC peripheral clock enabling */ \
02040                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
02041                                         UNUSED(tmpreg); \
02042                                       } while(0U)
02043 #define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
02044                                         __IO uint32_t tmpreg; \
02045                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
02046                                         /* Delay after an RCC peripheral clock enabling */ \
02047                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
02048                                         UNUSED(tmpreg); \
02049                                       } while(0U)
02050 #define __HAL_RCC_I2C3_CLK_ENABLE()   do { \
02051                                         __IO uint32_t tmpreg; \
02052                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
02053                                         /* Delay after an RCC peripheral clock enabling */ \
02054                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
02055                                         UNUSED(tmpreg); \
02056                                       } while(0U)
02057
02058 #define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
02059 #define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
02060 #define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
02061 #define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
02062 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
02063
02064 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
02065   || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
02066 #define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
02067                                         __IO uint32_t tmpreg; \
02068                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
02069                                         /* Delay after an RCC peripheral clock enabling */ \
02070                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
02071                                         UNUSED(tmpreg); \
02072                                       } while(0U)
02073 #define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
02074                                         __IO uint32_t tmpreg; \
02075                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
02076                                         /* Delay after an RCC peripheral clock enabling */ \
02077                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
02078                                         UNUSED(tmpreg); \
02079                                       } while(0U)
02080 #define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
02081                                         __IO uint32_t tmpreg; \
02082                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
02083                                         /* Delay after an RCC peripheral clock enabling */ \
02084                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
02085                                         UNUSED(tmpreg); \
02086                                       } while(0U)
02087 #define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
02088                                         __IO uint32_t tmpreg; \
02089                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
02090                                         /* Delay after an RCC peripheral clock enabling */ \
02091                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
02092                                         UNUSED(tmpreg); \
02093                                       } while(0U)
02094 #define __HAL_RCC_UART4_CLK_ENABLE()   do { \
02095                                         __IO uint32_t tmpreg; \
02096                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
02097                                         /* Delay after an RCC peripheral clock enabling */ \
02098                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
02099                                         UNUSED(tmpreg); \
02100                                       } while(0U)
02101 #define __HAL_RCC_UART5_CLK_ENABLE()   do { \
02102                                         __IO uint32_t tmpreg; \
02103                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
02104                                         /* Delay after an RCC peripheral clock enabling */ \
02105                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
02106                                         UNUSED(tmpreg); \
02107                                       } while(0U)
02108 #define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
02109                                         __IO uint32_t tmpreg; \
02110                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
02111                                         /* Delay after an RCC peripheral clock enabling */ \
02112                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
02113                                         UNUSED(tmpreg); \
02114                                       } while(0U)
02115
02116 #define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
02117 #define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
02118 #define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
02119 #define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
02120 #define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
02121 #define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
02122 #define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
02123 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02124        /* STM32F302xC || STM32F303xC || STM32F358xx    */
02125
02126 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
02127 #define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
02128                                         __IO uint32_t tmpreg; \
02129                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
02130                                         /* Delay after an RCC peripheral clock enabling */ \
02131                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
02132                                         UNUSED(tmpreg); \
02133                                       } while(0U)
02134 #define __HAL_RCC_DAC2_CLK_ENABLE()   do { \
02135                                         __IO uint32_t tmpreg; \
02136                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
02137                                         /* Delay after an RCC peripheral clock enabling */ \
02138                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
02139                                         UNUSED(tmpreg); \
02140                                       } while(0U)
02141
02142 #define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
02143 #define __HAL_RCC_DAC2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
02144 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
02145
02146 #if defined(STM32F373xC) || defined(STM32F378xx)
02147 #define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
02148                                         __IO uint32_t tmpreg; \
02149                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
02150                                         /* Delay after an RCC peripheral clock enabling */ \
02151                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
02152                                         UNUSED(tmpreg); \
02153                                       } while(0U)
02154 #define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
02155                                         __IO uint32_t tmpreg; \
02156                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
02157                                         /* Delay after an RCC peripheral clock enabling */ \
02158                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
02159                                         UNUSED(tmpreg); \
02160                                       } while(0U)
02161 #define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
02162                                         __IO uint32_t tmpreg; \
02163                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
02164                                         /* Delay after an RCC peripheral clock enabling */ \
02165                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
02166                                         UNUSED(tmpreg); \
02167                                       } while(0U)
02168 #define __HAL_RCC_TIM12_CLK_ENABLE()   do { \
02169                                         __IO uint32_t tmpreg; \
02170                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
02171                                         /* Delay after an RCC peripheral clock enabling */ \
02172                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
02173                                         UNUSED(tmpreg); \
02174                                       } while(0U)
02175 #define __HAL_RCC_TIM13_CLK_ENABLE()   do { \
02176                                         __IO uint32_t tmpreg; \
02177                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
02178                                         /* Delay after an RCC peripheral clock enabling */ \
02179                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
02180                                         UNUSED(tmpreg); \
02181                                       } while(0U)
02182 #define __HAL_RCC_TIM14_CLK_ENABLE()   do { \
02183                                         __IO uint32_t tmpreg; \
02184                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
02185                                         /* Delay after an RCC peripheral clock enabling */ \
02186                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
02187                                         UNUSED(tmpreg); \
02188                                       } while(0U)
02189 #define __HAL_RCC_TIM18_CLK_ENABLE()   do { \
02190                                         __IO uint32_t tmpreg; \
02191                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
02192                                         /* Delay after an RCC peripheral clock enabling */ \
02193                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
02194                                         UNUSED(tmpreg); \
02195                                       } while(0U)
02196 #define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
02197                                         __IO uint32_t tmpreg; \
02198                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
02199                                         /* Delay after an RCC peripheral clock enabling */ \
02200                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
02201                                         UNUSED(tmpreg); \
02202                                       } while(0U)
02203 #define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
02204                                         __IO uint32_t tmpreg; \
02205                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
02206                                         /* Delay after an RCC peripheral clock enabling */ \
02207                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
02208                                         UNUSED(tmpreg); \
02209                                       } while(0U)
02210 #define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
02211                                         __IO uint32_t tmpreg; \
02212                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
02213                                         /* Delay after an RCC peripheral clock enabling */ \
02214                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
02215                                         UNUSED(tmpreg); \
02216                                       } while(0U)
02217 #define __HAL_RCC_DAC2_CLK_ENABLE()   do { \
02218                                         __IO uint32_t tmpreg; \
02219                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
02220                                         /* Delay after an RCC peripheral clock enabling */ \
02221                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
02222                                         UNUSED(tmpreg); \
02223                                       } while(0U)
02224 #define __HAL_RCC_CEC_CLK_ENABLE()   do { \
02225                                         __IO uint32_t tmpreg; \
02226                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
02227                                         /* Delay after an RCC peripheral clock enabling */ \
02228                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
02229                                         UNUSED(tmpreg); \
02230                                       } while(0U)
02231
02232 #define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
02233 #define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
02234 #define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
02235 #define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
02236 #define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
02237 #define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
02238 #define __HAL_RCC_TIM18_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
02239 #define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
02240 #define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
02241 #define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
02242 #define __HAL_RCC_DAC2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
02243 #define __HAL_RCC_CEC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
02244 #endif /* STM32F373xC || STM32F378xx */
02245
02246 #if defined(STM32F303xE) || defined(STM32F398xx)                        \
02247   || defined(STM32F303xC) || defined(STM32F358xx)                        \
02248   || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
02249   || defined(STM32F373xC) || defined(STM32F378xx)
02250 #define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
02251                                         __IO uint32_t tmpreg; \
02252                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
02253                                         /* Delay after an RCC peripheral clock enabling */ \
02254                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
02255                                         UNUSED(tmpreg); \
02256                                       } while(0U)
02257
02258 #define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
02259 #endif /* STM32F303xE || STM32F398xx                || */
02260        /* STM32F303xC || STM32F358xx                || */
02261        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02262        /* STM32F373xC || STM32F378xx                   */
02263
02264 #if defined(STM32F302xE) || defined(STM32F303xE)\
02265   || defined(STM32F302xC) || defined(STM32F303xC)\
02266   || defined(STM32F302x8)                        \
02267   || defined(STM32F373xC)
02268 #define __HAL_RCC_USB_CLK_ENABLE()   do { \
02269                                         __IO uint32_t tmpreg; \
02270                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
02271                                         /* Delay after an RCC peripheral clock enabling */ \
02272                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
02273                                         UNUSED(tmpreg); \
02274                                       } while(0U)
02275
02276 #define __HAL_RCC_USB_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
02277 #endif /* STM32F302xE || STM32F303xE || */
02278        /* STM32F302xC || STM32F303xC || */
02279        /* STM32F302x8                || */
02280        /* STM32F373xC                   */
02281
02282 #if !defined(STM32F301x8)
02283 #define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
02284                                         __IO uint32_t tmpreg; \
02285                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
02286                                         /* Delay after an RCC peripheral clock enabling */ \
02287                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
02288                                         UNUSED(tmpreg); \
02289                                       } while(0U)
02290
02291 #define __HAL_RCC_CAN1_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
02292 #endif /* STM32F301x8*/
02293
02294 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
02295 #define __HAL_RCC_I2C3_CLK_ENABLE()   do { \
02296                                         __IO uint32_t tmpreg; \
02297                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
02298                                         /* Delay after an RCC peripheral clock enabling */ \
02299                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
02300                                         UNUSED(tmpreg); \
02301                                       } while(0U)
02302
02303 #define __HAL_RCC_I2C3_CLK_DISABLE()         (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
02304 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
02305 /**
02306   * @}
02307   */
02308
02309 /** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable
02310   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
02311   * @note   After reset, the peripheral clock (used for registers read/write access)
02312   *         is disabled and the application software has to enable this clock before
02313   *         using it.
02314   * @{
02315   */
02316 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
02317   || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
02318 #define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
02319                                         __IO uint32_t tmpreg; \
02320                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
02321                                         /* Delay after an RCC peripheral clock enabling */ \
02322                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
02323                                         UNUSED(tmpreg); \
02324                                       } while(0U)
02325
02326 #define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
02327 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02328        /* STM32F302xC || STM32F303xC || STM32F358xx    */
02329
02330 #if defined(STM32F303xE) || defined(STM32F398xx)\
02331   || defined(STM32F303xC) || defined(STM32F358xx)
02332 #define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
02333                                         __IO uint32_t tmpreg; \
02334                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
02335                                         /* Delay after an RCC peripheral clock enabling */ \
02336                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
02337                                         UNUSED(tmpreg); \
02338                                       } while(0U)
02339
02340 #define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
02341 #endif /* STM32F303xE || STM32F398xx || */
02342        /* STM32F303xC || STM32F358xx    */
02343
02344 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
02345 #define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
02346                                         __IO uint32_t tmpreg; \
02347                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
02348                                         /* Delay after an RCC peripheral clock enabling */ \
02349                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
02350                                         UNUSED(tmpreg); \
02351                                       } while(0U)
02352
02353 #define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
02354 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
02355
02356 #if defined(STM32F334x8)
02357 #define __HAL_RCC_HRTIM1_CLK_ENABLE()   do { \
02358                                         __IO uint32_t tmpreg; \
02359                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\
02360                                         /* Delay after an RCC peripheral clock enabling */ \
02361                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\
02362                                         UNUSED(tmpreg); \
02363                                       } while(0U)
02364
02365 #define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN))
02366 #endif /* STM32F334x8 */
02367
02368 #if defined(STM32F373xC) || defined(STM32F378xx)
02369 #define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
02370                                         __IO uint32_t tmpreg; \
02371                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
02372                                         /* Delay after an RCC peripheral clock enabling */ \
02373                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
02374                                         UNUSED(tmpreg); \
02375                                       } while(0U)
02376 #define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
02377                                         __IO uint32_t tmpreg; \
02378                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
02379                                         /* Delay after an RCC peripheral clock enabling */ \
02380                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
02381                                         UNUSED(tmpreg); \
02382                                       } while(0U)
02383 #define __HAL_RCC_TIM19_CLK_ENABLE()   do { \
02384                                         __IO uint32_t tmpreg; \
02385                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
02386                                         /* Delay after an RCC peripheral clock enabling */ \
02387                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
02388                                         UNUSED(tmpreg); \
02389                                       } while(0U)
02390 #define __HAL_RCC_SDADC1_CLK_ENABLE()   do { \
02391                                         __IO uint32_t tmpreg; \
02392                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
02393                                         /* Delay after an RCC peripheral clock enabling */ \
02394                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
02395                                         UNUSED(tmpreg); \
02396                                       } while(0U)
02397 #define __HAL_RCC_SDADC2_CLK_ENABLE()   do { \
02398                                         __IO uint32_t tmpreg; \
02399                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
02400                                         /* Delay after an RCC peripheral clock enabling */ \
02401                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
02402                                         UNUSED(tmpreg); \
02403                                       } while(0U)
02404 #define __HAL_RCC_SDADC3_CLK_ENABLE()   do { \
02405                                         __IO uint32_t tmpreg; \
02406                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
02407                                         /* Delay after an RCC peripheral clock enabling */ \
02408                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
02409                                         UNUSED(tmpreg); \
02410                                       } while(0U)
02411
02412 #define __HAL_RCC_ADC1_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
02413 #define __HAL_RCC_SPI1_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
02414 #define __HAL_RCC_TIM19_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
02415 #define __HAL_RCC_SDADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
02416 #define __HAL_RCC_SDADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
02417 #define __HAL_RCC_SDADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
02418 #endif /* STM32F373xC || STM32F378xx */
02419
02420 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
02421   || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
02422   || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
02423   || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02424 #define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
02425                                         __IO uint32_t tmpreg; \
02426                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
02427                                         /* Delay after an RCC peripheral clock enabling */ \
02428                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
02429                                         UNUSED(tmpreg); \
02430                                       } while(0U)
02431
02432 #define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
02433 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02434        /* STM32F302xC || STM32F303xC || STM32F358xx || */
02435        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02436        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
02437
02438 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
02439 #define __HAL_RCC_SPI4_CLK_ENABLE()   do { \
02440                                         __IO uint32_t tmpreg; \
02441                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
02442                                         /* Delay after an RCC peripheral clock enabling */ \
02443                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
02444                                         UNUSED(tmpreg); \
02445                                       } while(0U)
02446
02447 #define __HAL_RCC_SPI4_CLK_DISABLE()         (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
02448 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
02449
02450 #if defined(STM32F303xE) || defined(STM32F398xx)
02451 #define __HAL_RCC_TIM20_CLK_ENABLE()   do { \
02452                                         __IO uint32_t tmpreg; \
02453                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\
02454                                         /* Delay after an RCC peripheral clock enabling */ \
02455                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\
02456                                         UNUSED(tmpreg); \
02457                                       } while(0U)
02458 #define __HAL_RCC_TIM20_CLK_DISABLE()        (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN))
02459 #endif /* STM32F303xE || STM32F398xx */
02460
02461 /**
02462   * @}
02463   */
02464
02465 /** @defgroup RCCEx_AHB_Peripheral_Clock_Enable_Disable_Status RCC Extended AHB Peripheral Clock Enable Disable Status
02466   * @brief  Get the enable or disable status of the AHB peripheral clock.
02467   * @note   After reset, the peripheral clock (used for registers read/write access)
02468   *         is disabled and the application software has to enable this clock before
02469   *         using it.
02470   * @{
02471   */
02472 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02473 #define __HAL_RCC_ADC1_IS_CLK_ENABLED()          ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) != RESET)
02474
02475 #define __HAL_RCC_ADC1_IS_CLK_DISABLED()         ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) == RESET)
02476 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
02477
02478 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
02479   || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
02480 #define __HAL_RCC_DMA2_IS_CLK_ENABLED()          ((RCC->AHBENR & (RCC_AHBENR_DMA2EN))  != RESET)
02481 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()         ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
02482 #define __HAL_RCC_ADC12_IS_CLK_ENABLED()         ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET)
02483
02484 #define __HAL_RCC_DMA2_IS_CLK_DISABLED()         ((RCC->AHBENR & (RCC_AHBENR_DMA2EN))  == RESET)
02485 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED()        ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
02486 #define __HAL_RCC_ADC12_IS_CLK_DISABLED()        ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET)
02487 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02488        /* STM32F302xC || STM32F303xC || STM32F358xx    */
02489
02490 #if defined(STM32F303xE) || defined(STM32F398xx)\
02491   || defined(STM32F303xC) || defined(STM32F358xx)
02492 #define __HAL_RCC_ADC34_IS_CLK_ENABLED()         ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) != RESET)
02493
02494 #define __HAL_RCC_ADC34_IS_CLK_DISABLED()        ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) == RESET)
02495 #endif /* STM32F303xE || STM32F398xx || */
02496        /* STM32F303xC || STM32F358xx    */
02497
02498 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
02499 #define __HAL_RCC_ADC12_IS_CLK_ENABLED()         ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET)
02500
02501 #define __HAL_RCC_ADC12_IS_CLK_DISABLED()        ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET)
02502 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
02503
02504 #if defined(STM32F373xC) || defined(STM32F378xx)
02505 #define __HAL_RCC_DMA2_IS_CLK_ENABLED()          ((RCC->AHBENR & (RCC_AHBENR_DMA2EN))  != RESET)
02506 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()         ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
02507
02508 #define __HAL_RCC_DMA2_IS_CLK_DISABLED()         ((RCC->AHBENR & (RCC_AHBENR_DMA2EN))  == RESET)
02509 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED()        ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
02510 #endif /* STM32F373xC || STM32F378xx */
02511
02512 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
02513 #define __HAL_RCC_FMC_IS_CLK_ENABLED()           ((RCC->AHBENR & (RCC_AHBENR_FMCEN))   != RESET)
02514 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED()         ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != RESET)
02515 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED()         ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != RESET)
02516
02517 #define __HAL_RCC_FMC_IS_CLK_DISABLED()           ((RCC->AHBENR & (RCC_AHBENR_FMCEN))   == RESET)
02518 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED()         ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == RESET)
02519 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED()         ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == RESET)
02520 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
02521 /**
02522   * @}
02523   */
02524
02525 /** @defgroup RCCEx_APB1_Clock_Enable_Disable_Status RCC Extended APB1 Peripheral Clock Enable Disable  Status
02526   * @brief  Get the enable or disable status of the APB1 peripheral clock.
02527   * @note   After reset, the peripheral clock (used for registers read/write access)
02528   *         is disabled and the application software has to enable this clock before
02529   *         using it.
02530   * @{
02531   */
02532 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02533 #define __HAL_RCC_SPI2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
02534 #define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
02535 #define __HAL_RCC_I2C2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
02536 #define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
02537
02538 #define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
02539 #define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
02540 #define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
02541 #define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
02542 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
02543
02544 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
02545   || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
02546 #define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN))  != RESET)
02547 #define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN))  != RESET)
02548 #define __HAL_RCC_SPI2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN))  != RESET)
02549 #define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN))  != RESET)
02550 #define __HAL_RCC_UART4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
02551 #define __HAL_RCC_UART5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
02552 #define __HAL_RCC_I2C2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN))  != RESET)
02553
02554 #define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN))  == RESET)
02555 #define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN))  == RESET)
02556 #define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN))  == RESET)
02557 #define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN))  == RESET)
02558 #define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
02559 #define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
02560 #define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN))  == RESET)
02561 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02562        /* STM32F302xC || STM32F303xC || STM32F358xx    */
02563
02564 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
02565 #define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
02566 #define __HAL_RCC_DAC2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)
02567
02568 #define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
02569 #define __HAL_RCC_DAC2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)
02570 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
02571
02572 #if defined(STM32F373xC) || defined(STM32F378xx)
02573 #define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN))  != RESET)
02574 #define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN))  != RESET)
02575 #define __HAL_RCC_TIM5_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN))  != RESET)
02576 #define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
02577 #define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
02578 #define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
02579 #define __HAL_RCC_TIM18_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) != RESET)
02580 #define __HAL_RCC_SPI2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN))  != RESET)
02581 #define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN))  != RESET)
02582 #define __HAL_RCC_I2C2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN))  != RESET)
02583 #define __HAL_RCC_DAC2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN))  != RESET)
02584 #define __HAL_RCC_CEC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN))   != RESET)
02585
02586 #define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN))  == RESET)
02587 #define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN))  == RESET)
02588 #define __HAL_RCC_TIM5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN))  == RESET)
02589 #define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
02590 #define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
02591 #define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
02592 #define __HAL_RCC_TIM18_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) == RESET)
02593 #define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN))  == RESET)
02594 #define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN))  == RESET)
02595 #define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN))  == RESET)
02596 #define __HAL_RCC_DAC2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN))  == RESET)
02597 #define __HAL_RCC_CEC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CECEN))   == RESET)
02598 #endif /* STM32F373xC || STM32F378xx */
02599
02600 #if defined(STM32F303xE) || defined(STM32F398xx)                        \
02601   || defined(STM32F303xC) || defined(STM32F358xx)                        \
02602   || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
02603   || defined(STM32F373xC) || defined(STM32F378xx)
02604 #define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
02605
02606 #define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
02607 #endif /* STM32F303xE || STM32F398xx                || */
02608        /* STM32F303xC || STM32F358xx                || */
02609        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02610        /* STM32F373xC || STM32F378xx                   */
02611
02612 #if defined(STM32F302xE) || defined(STM32F303xE)\
02613   || defined(STM32F302xC) || defined(STM32F303xC)\
02614   || defined(STM32F302x8)                        \
02615   || defined(STM32F373xC)
02616 #define __HAL_RCC_USB_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
02617
02618 #define __HAL_RCC_USB_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
02619 #endif /* STM32F302xE || STM32F303xE || */
02620        /* STM32F302xC || STM32F303xC || */
02621        /* STM32F302x8                || */
02622        /* STM32F373xC                   */
02623
02624 #if !defined(STM32F301x8)
02625 #define __HAL_RCC_CAN1_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) != RESET)
02626
02627 #define __HAL_RCC_CAN1_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) == RESET)
02628 #endif /* STM32F301x8*/
02629
02630 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
02631 #define __HAL_RCC_I2C3_IS_CLK_ENABLED()          ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
02632
02633 #define __HAL_RCC_I2C3_IS_CLK_DISABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
02634 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
02635 /**
02636   * @}
02637   */
02638
02639 /** @defgroup RCCEx_APB2_Clock_Enable_Disable_Status RCC Extended APB2 Peripheral Clock Enable Disable  Status
02640   * @brief  Get the enable or disable status of the APB2 peripheral clock.
02641   * @note   After reset, the peripheral clock (used for registers read/write access)
02642   *         is disabled and the application software has to enable this clock before
02643   *         using it.
02644   * @{
02645   */
02646 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
02647   || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
02648 #define __HAL_RCC_SPI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
02649
02650 #define __HAL_RCC_SPI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
02651 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02652        /* STM32F302xC || STM32F303xC || STM32F358xx    */
02653
02654 #if defined(STM32F303xE) || defined(STM32F398xx)\
02655   || defined(STM32F303xC) || defined(STM32F358xx)
02656 #define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
02657
02658 #define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
02659 #endif /* STM32F303xE || STM32F398xx || */
02660        /* STM32F303xC || STM32F358xx    */
02661
02662 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
02663 #define __HAL_RCC_SPI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
02664
02665 #define __HAL_RCC_SPI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
02666 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
02667
02668 #if defined(STM32F334x8)
02669 #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) != RESET)
02670
02671 #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) == RESET)
02672 #endif /* STM32F334x8 */
02673
02674 #if defined(STM32F373xC) || defined(STM32F378xx)
02675 #define __HAL_RCC_ADC1_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN))   != RESET)
02676 #define __HAL_RCC_SPI1_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN))   != RESET)
02677 #define __HAL_RCC_TIM19_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN))  != RESET)
02678 #define __HAL_RCC_SDADC1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) != RESET)
02679 #define __HAL_RCC_SDADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) != RESET)
02680 #define __HAL_RCC_SDADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) != RESET)
02681
02682 #define __HAL_RCC_ADC1_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN))   == RESET)
02683 #define __HAL_RCC_SPI1_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN))   == RESET)
02684 #define __HAL_RCC_TIM19_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN))  == RESET)
02685 #define __HAL_RCC_SDADC1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) == RESET)
02686 #define __HAL_RCC_SDADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) == RESET)
02687 #define __HAL_RCC_SDADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) == RESET)
02688 #endif /* STM32F373xC || STM32F378xx */
02689
02690 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
02691   || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
02692   || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
02693   || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02694 #define __HAL_RCC_TIM1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
02695
02696 #define __HAL_RCC_TIM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
02697 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02698        /* STM32F302xC || STM32F303xC || STM32F358xx || */
02699        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02700        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
02701
02702 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
02703 #define __HAL_RCC_SPI4_IS_CLK_ENABLED()          ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
02704
02705 #define __HAL_RCC_SPI4_IS_CLK_DISABLED()         ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
02706 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
02707
02708 #if defined(STM32F303xE) || defined(STM32F398xx)
02709 #define __HAL_RCC_TIM20_IS_CLK_ENABLED()         ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) != RESET)
02710
02711 #define __HAL_RCC_TIM20_IS_CLK_DISABLED()        ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) == RESET)
02712 #endif /* STM32F303xE || STM32F398xx */
02713 /**
02714   * @}
02715   */
02716
02717 /** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset
02718   * @brief  Force or release AHB peripheral reset.
02719   * @{
02720   */
02721 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02722 #define __HAL_RCC_ADC1_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC1RST))
02723
02724 #define __HAL_RCC_ADC1_RELEASE_RESET()  (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST))
02725 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
02726
02727 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
02728   || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
02729 #define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
02730 #define __HAL_RCC_ADC12_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
02731 /* Aliases for STM32 F3 compatibility */
02732 #define __HAL_RCC_ADC1_FORCE_RESET()     __HAL_RCC_ADC12_FORCE_RESET()
02733 #define __HAL_RCC_ADC2_FORCE_RESET()     __HAL_RCC_ADC12_FORCE_RESET()
02734
02735 #define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
02736 #define __HAL_RCC_ADC12_RELEASE_RESET()  (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
02737 /* Aliases for STM32 F3 compatibility */
02738 #define __HAL_RCC_ADC1_RELEASE_RESET()    __HAL_RCC_ADC12_RELEASE_RESET()
02739 #define __HAL_RCC_ADC2_RELEASE_RESET()    __HAL_RCC_ADC12_RELEASE_RESET()
02740 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02741        /* STM32F302xC || STM32F303xC || STM32F358xx    */
02742
02743 #if defined(STM32F303xE) || defined(STM32F398xx)\
02744   || defined(STM32F303xC) || defined(STM32F358xx)
02745 #define __HAL_RCC_ADC34_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC34RST))
02746
02747 #define __HAL_RCC_ADC34_RELEASE_RESET()  (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST))
02748 #endif /* STM32F303xE || STM32F398xx || */
02749        /* STM32F303xC || STM32F358xx    */
02750
02751 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
02752 #define __HAL_RCC_ADC12_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
02753 /* Aliases for STM32 F3 compatibility */
02754 #define __HAL_RCC_ADC1_FORCE_RESET()     __HAL_RCC_ADC12_FORCE_RESET()
02755 #define __HAL_RCC_ADC2_FORCE_RESET()     __HAL_RCC_ADC12_FORCE_RESET()
02756
02757 #define __HAL_RCC_ADC12_RELEASE_RESET()  (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
02758 /* Aliases for STM32 F3 compatibility */
02759 #define __HAL_RCC_ADC1_RELEASE_RESET()    __HAL_RCC_ADC12_RELEASE_RESET()
02760 #define __HAL_RCC_ADC2_RELEASE_RESET()    __HAL_RCC_ADC12_RELEASE_RESET()
02761 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
02762
02763 #if defined(STM32F373xC) || defined(STM32F378xx)
02764 #define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
02765
02766 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
02767 #endif /* STM32F373xC || STM32F378xx */
02768
02769 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
02770 #define __HAL_RCC_FMC_FORCE_RESET()            (RCC->AHBRSTR |= (RCC_AHBRSTR_FMCRST))
02771 #define __HAL_RCC_GPIOG_FORCE_RESET()          (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
02772 #define __HAL_RCC_GPIOH_FORCE_RESET()          (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST))
02773
02774 #define __HAL_RCC_FMC_RELEASE_RESET()            (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST))
02775 #define __HAL_RCC_GPIOG_RELEASE_RESET()          (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
02776 #define __HAL_RCC_GPIOH_RELEASE_RESET()          (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
02777 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
02778 /**
02779   * @}
02780   */
02781
02782 /** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset
02783   * @brief  Force or release APB1 peripheral reset.
02784   * @{
02785   */
02786 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02787 #define __HAL_RCC_SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
02788 #define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
02789 #define __HAL_RCC_I2C2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
02790 #define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
02791
02792 #define __HAL_RCC_SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
02793 #define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
02794 #define __HAL_RCC_I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
02795 #define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
02796 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
02797
02798 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
02799   || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
02800 #define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
02801 #define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
02802 #define __HAL_RCC_SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
02803 #define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
02804 #define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
02805 #define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
02806 #define __HAL_RCC_I2C2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
02807
02808 #define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
02809 #define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
02810 #define __HAL_RCC_SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
02811 #define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
02812 #define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
02813 #define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
02814 #define __HAL_RCC_I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
02815 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02816        /* STM32F302xC || STM32F303xC || STM32F358xx */
02817
02818 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
02819 #define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
02820 #define __HAL_RCC_DAC2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
02821
02822 #define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
02823 #define __HAL_RCC_DAC2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
02824 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
02825
02826 #if defined(STM32F373xC) || defined(STM32F378xx)
02827 #define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
02828 #define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
02829 #define __HAL_RCC_TIM5_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
02830 #define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
02831 #define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
02832 #define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
02833 #define __HAL_RCC_TIM18_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM18RST))
02834 #define __HAL_RCC_SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
02835 #define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
02836 #define __HAL_RCC_I2C2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
02837 #define __HAL_RCC_DAC2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
02838 #define __HAL_RCC_CEC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
02839
02840 #define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
02841 #define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
02842 #define __HAL_RCC_TIM5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
02843 #define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
02844 #define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
02845 #define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
02846 #define __HAL_RCC_TIM18_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
02847 #define __HAL_RCC_SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
02848 #define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
02849 #define __HAL_RCC_I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
02850 #define __HAL_RCC_DAC2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
02851 #define __HAL_RCC_CEC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
02852 #endif /* STM32F373xC || STM32F378xx */
02853
02854 #if defined(STM32F303xE) || defined(STM32F398xx)\
02855   || defined(STM32F303xC) || defined(STM32F358xx)\
02856   || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
02857   || defined(STM32F373xC) || defined(STM32F378xx)
02858 #define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
02859
02860 #define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
02861 #endif /* STM32F303xE || STM32F398xx                || */
02862        /* STM32F303xC || STM32F358xx                || */
02863        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02864        /* STM32F373xC || STM32F378xx                   */
02865
02866 #if defined(STM32F302xE) || defined(STM32F303xE)\
02867   || defined(STM32F302xC) || defined(STM32F303xC)\
02868   || defined(STM32F302x8)                        \
02869   || defined(STM32F373xC)
02870 #define __HAL_RCC_USB_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
02871
02872 #define __HAL_RCC_USB_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
02873 #endif /* STM32F302xE || STM32F303xE || */
02874        /* STM32F302xC || STM32F303xC || */
02875        /* STM32F302x8                || */
02876        /* STM32F373xC                   */
02877
02878 #if !defined(STM32F301x8)
02879 #define __HAL_RCC_CAN1_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
02880
02881 #define __HAL_RCC_CAN1_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
02882 #endif /* STM32F301x8*/
02883
02884 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
02885 #define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
02886
02887 #define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
02888 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
02889 /**
02890   * @}
02891   */
02892
02893 /** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset
02894   * @brief  Force or release APB2 peripheral reset.
02895   * @{
02896   */
02897 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
02898   || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
02899 #define __HAL_RCC_SPI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
02900
02901 #define __HAL_RCC_SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
02902 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02903        /* STM32F302xC || STM32F303xC || STM32F358xx */
02904
02905 #if defined(STM32F303xE) || defined(STM32F398xx)\
02906   || defined(STM32F303xC) || defined(STM32F358xx)
02907 #define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
02908
02909 #define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
02910 #endif /* STM32F303xE || STM32F398xx || */
02911        /* STM32F303xC || STM32F358xx    */
02912
02913 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
02914 #define __HAL_RCC_SPI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
02915
02916 #define __HAL_RCC_SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
02917 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
02918
02919 #if defined(STM32F334x8)
02920 #define __HAL_RCC_HRTIM1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_HRTIM1RST))
02921
02922 #define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST))
02923 #endif /* STM32F334x8 */
02924
02925 #if defined(STM32F373xC) || defined(STM32F378xx)
02926 #define __HAL_RCC_ADC1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
02927 #define __HAL_RCC_SPI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
02928 #define __HAL_RCC_TIM19_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM19RST))
02929 #define __HAL_RCC_SDADC1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC1RST))
02930 #define __HAL_RCC_SDADC2_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC2RST))
02931 #define __HAL_RCC_SDADC3_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC3RST))
02932
02933 #define __HAL_RCC_ADC1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
02934 #define __HAL_RCC_SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
02935 #define __HAL_RCC_TIM19_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
02936 #define __HAL_RCC_SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
02937 #define __HAL_RCC_SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
02938 #define __HAL_RCC_SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
02939 #endif /* STM32F373xC || STM32F378xx */
02940
02941 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
02942   || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
02943   || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
02944   || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02945 #define __HAL_RCC_TIM1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
02946
02947 #define __HAL_RCC_TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
02948 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02949        /* STM32F302xC || STM32F303xC || STM32F358xx || */
02950        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02951        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
02952
02953 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
02954 #define __HAL_RCC_SPI4_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
02955
02956 #define __HAL_RCC_SPI4_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
02957 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
02958
02959 #if defined(STM32F303xE) || defined(STM32F398xx)
02960 #define __HAL_RCC_TIM20_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM20RST))
02961
02962 #define __HAL_RCC_TIM20_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST))
02963 #endif /* STM32F303xE || STM32F398xx */
02964
02965 /**
02966   * @}
02967   */
02968
02969 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02970 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
02971   * @{
02972   */
02973
02974 /** @brief  Macro to configure the I2C2 clock (I2C2CLK).
02975   * @param  __I2C2CLKSource__ specifies the I2C2 clock source.
02976   *         This parameter can be one of the following values:
02977   *            @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
02978   *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
02979   */
02980 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
02981                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
02982
02983 /** @brief  Macro to get the I2C2 clock source.
02984   * @retval The clock source can be one of the following values:
02985   *            @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
02986   *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
02987   */
02988 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
02989
02990 /** @brief  Macro to configure the I2C3 clock (I2C3CLK).
02991   * @param  __I2C3CLKSource__ specifies the I2C3 clock source.
02992   *         This parameter can be one of the following values:
02993   *            @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
02994   *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
02995   */
02996 #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
02997                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
02998
02999 /** @brief  Macro to get the I2C3 clock source.
03000   * @retval The clock source can be one of the following values:
03001   *            @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
03002   *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
03003   */
03004 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
03005
03006 /**
03007   * @}
03008   */
03009
03010 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
03011   * @{
03012   */
03013 /** @brief  Macro to configure the TIM1 clock (TIM1CLK).
03014   * @param  __TIM1CLKSource__ specifies the TIM1 clock source.
03015   *         This parameter can be one of the following values:
03016   *            @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
03017   *            @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
03018   */
03019 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
03020                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
03021
03022 /** @brief  Macro to get the TIM1 clock (TIM1CLK).
03023   * @retval The clock source can be one of the following values:
03024   *            @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
03025   *            @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
03026   */
03027 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
03028
03029 /** @brief  Macro to configure the TIM15 clock (TIM15CLK).
03030   * @param  __TIM15CLKSource__ specifies the TIM15 clock source.
03031   *         This parameter can be one of the following values:
03032   *            @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
03033   *            @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
03034   */
03035 #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
03036                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
03037
03038 /** @brief  Macro to get the TIM15 clock (TIM15CLK).
03039   * @retval The clock source can be one of the following values:
03040   *            @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
03041   *            @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
03042   */
03043 #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
03044
03045 /** @brief  Macro to configure the TIM16 clock (TIM16CLK).
03046   * @param  __TIM16CLKSource__ specifies the TIM16 clock source.
03047   *         This parameter can be one of the following values:
03048   *            @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
03049   *            @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
03050   */
03051 #define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
03052                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
03053
03054 /** @brief  Macro to get the TIM16 clock (TIM16CLK).
03055   * @retval The clock source can be one of the following values:
03056   *            @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
03057   *            @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
03058   */
03059 #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
03060
03061 /** @brief  Macro to configure the TIM17 clock (TIM17CLK).
03062   * @param  __TIM17CLKSource__ specifies the TIM17 clock source.
03063   *         This parameter can be one of the following values:
03064   *            @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
03065   *            @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
03066   */
03067 #define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
03068                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
03069
03070 /** @brief  Macro to get the TIM17 clock (TIM17CLK).
03071   * @retval The clock source can be one of the following values:
03072   *            @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
03073   *            @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
03074   */
03075 #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
03076
03077 /**
03078   * @}
03079   */
03080
03081 /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
03082   * @{
03083   */
03084 /** @brief  Macro to configure the I2S clock source (I2SCLK).
03085   * @note   This function must be called before enabling the I2S APB clock.
03086   * @param  __I2SCLKSource__ specifies the I2S clock source.
03087   *         This parameter can be one of the following values:
03088   *            @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
03089   *            @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
03090   *                                        used as I2S clock source
03091   */
03092 #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
03093                   MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
03094
03095 /** @brief  Macro to get the I2S clock source (I2SCLK).
03096   * @retval The clock source can be one of the following values:
03097   *            @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
03098   *            @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
03099   *                                        used as I2S clock source
03100   */
03101 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
03102 /**
03103   * @}
03104   */
03105
03106 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
03107   * @{
03108   */
03109
03110 /** @brief  Macro to configure the ADC1 clock (ADC1CLK).
03111   * @param  __ADC1CLKSource__ specifies the ADC1 clock source.
03112   *         This parameter can be one of the following values:
03113   *            @arg @ref RCC_ADC1PLLCLK_OFF  ADC1 PLL clock disabled, ADC1 can use AHB clock
03114   *            @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock
03115   *            @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock
03116   *            @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock
03117   *            @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock
03118   *            @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock
03119   *            @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock
03120   *            @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock
03121   *            @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock
03122   *            @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock
03123   *            @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock
03124   *            @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock
03125   *            @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock
03126   */
03127 #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
03128                   MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__))
03129
03130 /** @brief  Macro to get the ADC1 clock
03131   * @retval The clock source can be one of the following values:
03132   *            @arg @ref RCC_ADC1PLLCLK_OFF  ADC1 PLL clock disabled, ADC1 can use AHB clock
03133   *            @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock
03134   *            @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock
03135   *            @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock
03136   *            @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock
03137   *            @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock
03138   *            @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock
03139   *            @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock
03140   *            @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock
03141   *            @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock
03142   *            @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock
03143   *            @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock
03144   *            @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock
03145   */
03146 #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES)))
03147 /**
03148   * @}
03149   */
03150
03151 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
03152
03153 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
03154   || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
03155 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
03156   * @{
03157   */
03158
03159 /** @brief  Macro to configure the I2C2 clock (I2C2CLK).
03160   * @param  __I2C2CLKSource__ specifies the I2C2 clock source.
03161   *         This parameter can be one of the following values:
03162   *            @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
03163   *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
03164   */
03165 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
03166                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
03167
03168 /** @brief  Macro to get the I2C2 clock source.
03169   * @retval The clock source can be one of the following values:
03170   *            @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
03171   *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
03172   */
03173 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
03174 /**
03175   * @}
03176   */
03177
03178 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
03179   * @{
03180   */
03181
03182 /** @brief  Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
03183   * @param  __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source.
03184   *         This parameter can be one of the following values:
03185   *            @arg @ref RCC_ADC12PLLCLK_OFF  ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
03186   *            @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
03187   *            @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
03188   *            @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
03189   *            @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
03190   *            @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
03191   *            @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
03192   *            @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
03193   *            @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
03194   *            @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
03195   *            @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
03196   *            @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
03197   *            @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
03198   */
03199 #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
03200                   MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
03201
03202 /** @brief  Macro to get the ADC1 & ADC2 clock
03203   * @retval The clock source can be one of the following values:
03204   *            @arg @ref RCC_ADC12PLLCLK_OFF  ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
03205   *            @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
03206   *            @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
03207   *            @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
03208   *            @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
03209   *            @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
03210   *            @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
03211   *            @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
03212   *            @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
03213   *            @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
03214   *            @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
03215   *            @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
03216   *            @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
03217   */
03218 #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
03219 /**
03220   * @}
03221   */
03222
03223 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
03224   * @{
03225   */
03226
03227 /** @brief  Macro to configure the TIM1 clock (TIM1CLK).
03228   * @param  __TIM1CLKSource__ specifies the TIM1 clock source.
03229   *         This parameter can be one of the following values:
03230   *            @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
03231   *            @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
03232   */
03233 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
03234                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
03235
03236 /** @brief  Macro to get the TIM1 clock (TIM1CLK).
03237   * @retval The clock source can be one of the following values:
03238   *            @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
03239   *            @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
03240   */
03241 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
03242 /**
03243   * @}
03244   */
03245
03246 /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
03247   * @{
03248   */
03249
03250 /** @brief  Macro to configure the I2S clock source (I2SCLK).
03251   * @note   This function must be called before enabling the I2S APB clock.
03252   * @param  __I2SCLKSource__ specifies the I2S clock source.
03253   *         This parameter can be one of the following values:
03254   *            @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
03255   *            @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
03256   *                                        used as I2S clock source
03257   */
03258 #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
03259                   MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
03260
03261 /** @brief  Macro to get the I2S clock source (I2SCLK).
03262   * @retval The clock source can be one of the following values:
03263   *            @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
03264   *            @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
03265   *                                        used as I2S clock source
03266   */
03267 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
03268 /**
03269   * @}
03270   */
03271
03272 /** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config
03273   * @{
03274   */
03275
03276 /** @brief  Macro to configure the UART4 clock (UART4CLK).
03277   * @param  __UART4CLKSource__ specifies the UART4 clock source.
03278   *         This parameter can be one of the following values:
03279   *            @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
03280   *            @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
03281   *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
03282   *            @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
03283   */
03284 #define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
03285                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__))
03286
03287 /** @brief  Macro to get the UART4 clock source.
03288   * @retval The clock source can be one of the following values:
03289   *            @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
03290   *            @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
03291   *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
03292   *            @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
03293   */
03294 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW)))
03295
03296 /** @brief  Macro to configure the UART5 clock (UART5CLK).
03297   * @param  __UART5CLKSource__ specifies the UART5 clock source.
03298   *         This parameter can be one of the following values:
03299   *            @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
03300   *            @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
03301   *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
03302   *            @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
03303   */
03304 #define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
03305                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__))
03306
03307 /** @brief  Macro to get the UART5 clock source.
03308   * @retval The clock source can be one of the following values:
03309   *            @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
03310   *            @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
03311   *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
03312   *            @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
03313   */
03314 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW)))
03315 /**
03316   * @}
03317   */
03318 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
03319        /* STM32F302xC || STM32F303xC || STM32F358xx    */
03320
03321 #if defined(STM32F303xE) || defined(STM32F398xx)\
03322   || defined(STM32F303xC) || defined(STM32F358xx)
03323 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
03324   * @{
03325   */
03326
03327 /** @brief  Macro to configure the ADC3 & ADC4 clock (ADC34CLK).
03328   * @param  __ADC34CLKSource__ specifies the ADC3 & ADC4 clock source.
03329   *         This parameter can be one of the following values:
03330   *            @arg @ref RCC_ADC34PLLCLK_OFF  ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
03331   *            @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock
03332   *            @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock
03333   *            @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock
03334   *            @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock
03335   *            @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock
03336   *            @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock
03337   *            @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock
03338   *            @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock
03339   *            @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock
03340   *            @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock
03341   *            @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock
03342   *            @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock
03343   */
03344 #define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \
03345                   MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__))
03346
03347 /** @brief  Macro to get the ADC3 & ADC4 clock
03348   * @retval The clock source can be one of the following values:
03349   *            @arg @ref RCC_ADC34PLLCLK_OFF  ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
03350   *            @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock
03351   *            @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock
03352   *            @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock
03353   *            @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock
03354   *            @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock
03355   *            @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock
03356   *            @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock
03357   *            @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock
03358   *            @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock
03359   *            @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock
03360   *            @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock
03361   *            @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock
03362   */
03363 #define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34)))
03364 /**
03365   * @}
03366   */
03367
03368 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
03369   * @{
03370   */
03371
03372 /** @brief  Macro to configure the TIM8 clock (TIM8CLK).
03373   * @param  __TIM8CLKSource__ specifies the TIM8 clock source.
03374   *         This parameter can be one of the following values:
03375   *            @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock
03376   *            @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock
03377   */
03378 #define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \
03379                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__))
03380
03381 /** @brief  Macro to get the TIM8 clock (TIM8CLK).
03382   * @retval The clock source can be one of the following values:
03383   *            @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock
03384   *            @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock
03385   */
03386 #define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW)))
03387
03388 /**
03389   * @}
03390   */
03391 #endif /* STM32F303xE || STM32F398xx || */
03392        /* STM32F303xC || STM32F358xx    */
03393
03394 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
03395 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
03396   * @{
03397   */
03398
03399 /** @brief  Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
03400   * @param  __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source.
03401   *         This parameter can be one of the following values:
03402   *            @arg @ref RCC_ADC12PLLCLK_OFF  ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
03403   *            @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
03404   *            @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
03405   *            @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
03406   *            @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
03407   *            @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
03408   *            @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
03409   *            @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
03410   *            @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
03411   *            @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
03412   *            @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
03413   *            @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
03414   *            @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
03415   */
03416 #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
03417                   MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
03418
03419 /** @brief  Macro to get the ADC1 & ADC2 clock
03420   * @retval The clock source can be one of the following values:
03421   *            @arg @ref RCC_ADC12PLLCLK_OFF  ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
03422   *            @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
03423   *            @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
03424   *            @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
03425   *            @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
03426   *            @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
03427   *            @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
03428   *            @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
03429   *            @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
03430   *            @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
03431   *            @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
03432   *            @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
03433   *            @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
03434   */
03435 #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
03436 /**
03437   * @}
03438   */
03439
03440 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
03441   * @{
03442   */
03443 /** @brief  Macro to configure the TIM1 clock (TIM1CLK).
03444   * @param  __TIM1CLKSource__ specifies the TIM1 clock source.
03445   *         This parameter can be one of the following values:
03446   *            @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
03447   *            @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
03448   */
03449 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
03450                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
03451
03452 /** @brief  Macro to get the TIM1 clock (TIM1CLK).
03453   * @retval The clock source can be one of the following values:
03454   *            @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
03455   *            @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
03456   */
03457 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
03458 /**
03459   * @}
03460   */
03461 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
03462
03463 #if defined(STM32F334x8)
03464 /** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
03465   * @{
03466   */
03467 /** @brief  Macro to configure the HRTIM1 clock.
03468   * @param  __HRTIM1CLKSource__ specifies the HRTIM1 clock source.
03469   *         This parameter can be one of the following values:
03470   *            @arg @ref RCC_HRTIM1CLK_HCLK   HCLK selected as HRTIM1 clock
03471   *            @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock
03472   */
03473 #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
03474                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__))
03475
03476 /** @brief  Macro to get the HRTIM1 clock source.
03477   * @retval The clock source can be one of the following values:
03478   *            @arg @ref RCC_HRTIM1CLK_HCLK   HCLK selected as HRTIM1 clock
03479   *            @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock
03480   */
03481 #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW)))
03482 /**
03483   * @}
03484   */
03485 #endif /* STM32F334x8 */
03486
03487 #if defined(STM32F373xC) || defined(STM32F378xx)
03488 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
03489   * @{
03490   */
03491 /** @brief  Macro to configure the I2C2 clock (I2C2CLK).
03492   * @param  __I2C2CLKSource__ specifies the I2C2 clock source.
03493   *         This parameter can be one of the following values:
03494   *            @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
03495   *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
03496   */
03497 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
03498                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
03499
03500 /** @brief  Macro to get the I2C2 clock source.
03501   * @retval The clock source can be one of the following values:
03502   *            @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
03503   *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
03504   */
03505 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
03506 /**
03507   * @}
03508   */
03509
03510 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
03511   * @{
03512   */
03513 /** @brief  Macro to configure the ADC1 clock (ADC1CLK).
03514   * @param  __ADC1CLKSource__ specifies the ADC1 clock source.
03515   *          This parameter can be one of the following values:
03516   *            @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock
03517   *            @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock
03518   *            @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock
03519   *            @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock
03520   */
03521 #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
03522                   MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
03523
03524 /** @brief  Macro to get the ADC1 clock (ADC1CLK).
03525   * @retval The clock source can be one of the following values:
03526   *            @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock
03527   *            @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock
03528   *            @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock
03529   *            @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock
03530   */
03531 #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
03532 /**
03533   * @}
03534   */
03535
03536 /** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config
03537   * @{
03538   */
03539 /** @brief  Macro to configure the SDADCx clock (SDADCxCLK).
03540   * @param  __SDADCPrescaler__ specifies the SDADCx system clock prescaler.
03541   *         This parameter can be one of the following values:
03542   *            @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock
03543   *            @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock
03544   *            @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock
03545   *            @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock
03546   *            @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock
03547   *            @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock
03548   *            @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock
03549   *            @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock
03550   *            @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock
03551   *            @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock
03552   *            @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock
03553   *            @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock
03554   *            @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock
03555   *            @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock
03556   *            @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock
03557   *            @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock
03558   *            @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock
03559   */
03560 #define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \
03561                   MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, (uint32_t)(__SDADCPrescaler__))
03562
03563 /** @brief  Macro to get the SDADCx clock prescaler.
03564   * @retval The clock source can be one of the following values:
03565   *            @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock
03566   *            @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock
03567   *            @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock
03568   *            @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock
03569   *            @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock
03570   *            @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock
03571   *            @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock
03572   *            @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock
03573   *            @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock
03574   *            @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock
03575   *            @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock
03576   *            @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock
03577   *            @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock
03578   *            @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock
03579   *            @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock
03580   *            @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock
03581   *            @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock
03582   */
03583 #define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDPRE)))
03584 /**
03585   * @}
03586   */
03587
03588 /** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config
03589   * @{
03590   */
03591 /** @brief  Macro to configure the CEC clock.
03592   * @param  __CECCLKSource__ specifies the CEC clock source.
03593   *         This parameter can be one of the following values:
03594   *            @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
03595   *            @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
03596   */
03597 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
03598                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
03599
03600 /** @brief  Macro to get the HDMI CEC clock source.
03601   * @retval The clock source can be one of the following values:
03602   *            @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
03603   *            @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
03604   */
03605 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
03606 /**
03607   * @}
03608   */
03609
03610 #endif /* STM32F373xC || STM32F378xx */
03611
03612 #if defined(STM32F302xE) || defined(STM32F303xE)\
03613   || defined(STM32F302xC) || defined(STM32F303xC)\
03614   || defined(STM32F302x8)                        \
03615   || defined(STM32F373xC)
03616
03617 /** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config
03618   * @{
03619   */
03620 /** @brief  Macro to configure the USB clock (USBCLK).
03621   * @param  __USBCLKSource__ specifies the USB clock source.
03622   *         This parameter can be one of the following values:
03623   *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL Clock divided by 1 selected as USB clock
03624   *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock
03625   */
03626 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
03627                   MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
03628
03629 /** @brief  Macro to get the USB clock source.
03630   * @retval The clock source can be one of the following values:
03631   *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL Clock divided by 1 selected as USB clock
03632   *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock
03633   */
03634 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
03635 /**
03636   * @}
03637   */
03638
03639 #endif /* STM32F302xE || STM32F303xE || */
03640        /* STM32F302xC || STM32F303xC || */
03641        /* STM32F302x8                || */
03642        /* STM32F373xC                   */
03643
03644 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
03645
03646 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
03647   * @{
03648   */
03649 /** @brief  Macro to configure the I2C3 clock (I2C3CLK).
03650   * @param  __I2C3CLKSource__ specifies the I2C3 clock source.
03651   *         This parameter can be one of the following values:
03652   *            @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
03653   *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
03654   */
03655 #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
03656                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
03657
03658 /** @brief  Macro to get the I2C3 clock source.
03659   * @retval The clock source can be one of the following values:
03660   *            @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
03661   *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
03662   */
03663 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
03664 /**
03665   * @}
03666   */
03667
03668 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
03669   * @{
03670   */
03671 /** @brief  Macro to configure the TIM2 clock (TIM2CLK).
03672   * @param  __TIM2CLKSource__ specifies the TIM2 clock source.
03673   *         This parameter can be one of the following values:
03674   *            @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock
03675   *            @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock
03676   */
03677 #define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \
03678                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__))
03679
03680 /** @brief  Macro to get the TIM2 clock (TIM2CLK).
03681   * @retval The clock source can be one of the following values:
03682   *            @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock
03683   *            @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock
03684   */
03685 #define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW)))
03686
03687 /** @brief  Macro to configure the TIM3 & TIM4 clock (TIM34CLK).
03688   * @param  __TIM34CLKSource__ specifies the TIM3 & TIM4 clock source.
03689   *         This parameter can be one of the following values:
03690   *            @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock
03691   *            @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock
03692   */
03693 #define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \
03694                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__))
03695
03696 /** @brief  Macro to get the TIM3 & TIM4 clock (TIM34CLK).
03697   * @retval The clock source can be one of the following values:
03698   *            @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock
03699   *            @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock
03700   */
03701 #define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW)))
03702
03703 /** @brief  Macro to configure the TIM15 clock (TIM15CLK).
03704   * @param  __TIM15CLKSource__ specifies the TIM15 clock source.
03705   *         This parameter can be one of the following values:
03706   *            @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
03707   *            @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
03708   */
03709 #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
03710                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
03711
03712 /** @brief  Macro to get the TIM15 clock (TIM15CLK).
03713   * @retval The clock source can be one of the following values:
03714   *            @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
03715   *            @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
03716   */
03717 #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
03718
03719 /** @brief  Macro to configure the TIM16 clock (TIM16CLK).
03720   * @param  __TIM16CLKSource__ specifies the TIM16 clock source.
03721   *         This parameter can be one of the following values:
03722   *            @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
03723   *            @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
03724   */
03725 #define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
03726                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
03727
03728 /** @brief  Macro to get the TIM16 clock (TIM16CLK).
03729   * @retval The clock source can be one of the following values:
03730   *            @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
03731   *            @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
03732   */
03733 #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
03734
03735 /** @brief  Macro to configure the TIM17 clock (TIM17CLK).
03736   * @param  __TIM17CLKSource__ specifies the TIM17 clock source.
03737   *         This parameter can be one of the following values:
03738   *            @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
03739   *            @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
03740   */
03741 #define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
03742                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
03743
03744 /** @brief  Macro to get the TIM17 clock (TIM17CLK).
03745   * @retval The clock source can be one of the following values:
03746   *            @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
03747   *            @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
03748   */
03749 #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
03750
03751 /**
03752   * @}
03753   */
03754
03755 #endif /* STM32f302xE || STM32f303xE || STM32F398xx */
03756
03757 #if defined(STM32F303xE) || defined(STM32F398xx)
03758 /** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
03759   * @{
03760   */
03761 /** @brief  Macro to configure the TIM20 clock (TIM20CLK).
03762   * @param  __TIM20CLKSource__ specifies the TIM20 clock source.
03763   *         This parameter can be one of the following values:
03764   *            @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock
03765   *            @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock
03766   */
03767 #define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \
03768                   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__))
03769
03770 /** @brief  Macro to get the TIM20 clock (TIM20CLK).
03771   * @retval The clock source can be one of the following values:
03772   *            @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock
03773   *            @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock
03774   */
03775 #define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW)))
03776
03777 /**
03778   * @}
03779   */
03780 #endif /* STM32f303xE || STM32F398xx */
03781
03782 /** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration
03783   * @{
03784   */
03785
03786 /**
03787   * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.
03788   * @param  __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
03789   *          This parameter can be one of the following values:
03790   *            @arg @ref RCC_LSEDRIVE_LOW        LSE oscillator low drive capability.
03791   *            @arg @ref RCC_LSEDRIVE_MEDIUMLOW  LSE oscillator medium low drive capability.
03792   *            @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
03793   *            @arg @ref RCC_LSEDRIVE_HIGH       LSE oscillator high drive capability.
03794   * @retval None
03795   */
03796 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\
03797         RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
03798
03799 /**
03800   * @}
03801   */
03802
03803 /**
03804   * @}
03805   */
03806
03807 /* Exported functions --------------------------------------------------------*/
03808 /** @addtogroup RCCEx_Exported_Functions
03809   * @{
03810   */
03811
03812 /** @addtogroup RCCEx_Exported_Functions_Group1
03813   * @{
03814   */
03815
03816 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
03817 void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
03818 uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
03819
03820 /**
03821   * @}
03822   */
03823
03824 /**
03825   * @}
03826   */
03827
03828 /**
03829   * @}
03830   */
03831
03832 /**
03833   * @}
03834   */
03835
03836 #ifdef __cplusplus
03837 }
03838 #endif
03839
03840 #endif /* __STM32F3xx_HAL_RCC_EX_H */
03841
03842 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
03843
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_rtc.c Source File

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stm32f3xx_hal_rtc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_rtc.c
00004   * @author  MCD Application Team
00005   * @brief   RTC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Real-Time Clock (RTC) peripheral:
00008   *           + Initialization
00009   *           + Calendar (Time and Date) configuration
00010   *           + Alarms (Alarm A and Alarm B) configuration
00011   *           + WakeUp Timer configuration
00012   *           + TimeStamp configuration
00013   *           + Tampers configuration
00014   *           + Backup Data Registers configuration
00015   *           + RTC Tamper and TimeStamp Pins Selection
00016   *           + Interrupts and flags management
00017   *
00018   @verbatim
00019
00020  ===============================================================================
00021                           ##### RTC Operating Condition #####
00022  ===============================================================================
00023     [..] The real-time clock (RTC) and the RTC backup registers can be powered
00024          from the VBAT voltage when the main VDD supply is powered off.
00025          To retain the content of the RTC backup registers and supply the RTC
00026          when VDD is turned off, VBAT pin can be connected to an optional
00027          standby voltage supplied by a battery or by another source.
00028
00029     [..] To allow the RTC to operate even when the main digital supply (VDD)
00030          is turned off, the VBAT pin powers the following blocks:
00031            (#) The RTC
00032            (#) The LSE oscillator
00033            (#) PC13 to PC15 I/Os (when available)
00034
00035     [..] When the backup domain is supplied by VDD (analog switch connected
00036          to VDD), the following functions are available:
00037            (#) PC14 and PC15 can be used as either GPIO or LSE pins
00038            (#) PC13 can be used as a GPIO or as the RTC_OUT pin
00039
00040     [..] When the backup domain is supplied by VBAT (analog switch connected
00041          to VBAT because VDD is not present), the following functions are available:
00042            (#) PC14 and PC15 can be used as LSE pins only
00043            (#) PC13 can be used as the RTC_OUT pin
00044
00045                         ##### Backup Domain Reset #####
00046  ===============================================================================
00047     [..] The backup domain reset sets all RTC registers and the RCC_BDCR
00048          register to their reset values.
00049          A backup domain reset is generated when one of the following events
00050          occurs:
00051            (#) Software reset, triggered by setting the BDRST bit in the
00052                RCC Backup domain control register (RCC_BDCR).
00053            (#) VDD or VBAT power on, if both supplies have previously been
00054                powered off.
00055
00056                    ##### Backup Domain Access #####
00057  ===================================================================
00058     [..] After reset, the backup domain (RTC registers, RTC backup data
00059          registers and backup SRAM) is protected against possible unwanted write
00060          accesses.
00061
00062     [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
00063            (#) Enable the Power Controller (PWR) APB1 interface clock using the
00064                __HAL_RCC_PWR_CLK_ENABLE() function.
00065            (#) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
00066            (#) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
00067            (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
00068
00069
00070                   ##### How to use RTC Driver #####
00071  ===================================================================
00072     [..]
00073         (+) Enable the RTC domain access (see description in the section above).
00074         (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00075             format using the HAL_RTC_Init() function.
00076
00077     *** Time and Date configuration ***
00078     ===================================
00079     [..]
00080         (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
00081             and HAL_RTC_SetDate() functions.
00082         (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
00083
00084     *** Alarm configuration ***
00085     ===========================
00086     [..]
00087         (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
00088             You can also configure the RTC Alarm with interrupt mode using the
00089             HAL_RTC_SetAlarm_IT() function.
00090         (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
00091
00092     *** RTC Wakeup configuration ***
00093     ================================
00094     [..]
00095         (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
00096             function. You can also configure the RTC Wakeup timer with interrupt mode
00097             using the HAL_RTC_SetWakeUpTimer_IT() function.
00098         (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer()
00099             function.
00100
00101     *** TimeStamp configuration ***
00102     ===============================
00103     [..]
00104         (+) Configure the RTC_AF trigger and enables the RTC TimeStamp using the
00105             HAL_RTC_SetTimeStamp() function. You can also configure the RTC TimeStamp with
00106             interrupt mode using the HAL_RTC_SetTimeStamp_IT() function.
00107         (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
00108             function.
00109
00110     *** Tamper configuration ***
00111     ============================
00112     [..]
00113         (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge
00114             or Level according to the Tamper filter (if equal to 0 Edge else Level)
00115             value, sampling frequency, precharge or discharge and Pull-UP using the
00116             HAL_RTC_SetTamper() function. You can configure RTC Tamper with interrupt
00117             mode using HAL_RTC_SetTamper_IT() function.
00118
00119     *** Backup Data Registers configuration ***
00120     ===========================================
00121     [..]
00122         (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
00123             function.
00124         (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
00125             function.
00126
00127
00128                   ##### RTC and low power modes #####
00129  ===================================================================
00130     [..] The MCU can be woken up from a low power mode by an RTC alternate
00131          function.
00132     [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
00133          RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
00134          These RTC alternate functions can wake up the system from the Stop and
00135          Standby low power modes.
00136     [..] The system can also wake up from low power modes without depending
00137          on an external interrupt (Auto-wakeup mode), by using the RTC alarm
00138          or the RTC wakeup events.
00139     [..] The RTC provides a programmable time base for waking up from the
00140          Stop or Standby mode at regular intervals.
00141          Wakeup from STOP and Standby modes is possible only when the RTC clock source
00142          is LSE or LSI.
00143
00144   @endverbatim
00145
00146   ******************************************************************************
00147   * @attention
00148   *
00149   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00150   *
00151   * Redistribution and use in source and binary forms, with or without modification,
00152   * are permitted provided that the following conditions are met:
00153   *   1. Redistributions of source code must retain the above copyright notice,
00154   *      this list of conditions and the following disclaimer.
00155   *   2. Redistributions in binary form must reproduce the above copyright notice,
00156   *      this list of conditions and the following disclaimer in the documentation
00157   *      and/or other materials provided with the distribution.
00158   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00159   *      may be used to endorse or promote products derived from this software
00160   *      without specific prior written permission.
00161   *
00162   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00163   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00164   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00165   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00166   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00167   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00168   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00169   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00170   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00171   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00172   *
00173   ******************************************************************************
00174   */
00175
00176 /* Includes ------------------------------------------------------------------*/
00177 #include "stm32f3xx_hal.h"
00178
00179 /** @addtogroup STM32F3xx_HAL_Driver
00180   * @{
00181   */
00182
00183 /** @addtogroup RTC
00184   * @brief RTC HAL module driver
00185   * @{
00186   */
00187
00188 #ifdef HAL_RTC_MODULE_ENABLED
00189
00190 /* Private typedef -----------------------------------------------------------*/
00191 /* Private define ------------------------------------------------------------*/
00192 /* Private macro -------------------------------------------------------------*/
00193 /* Private variables ---------------------------------------------------------*/
00194 /* Private function prototypes -----------------------------------------------*/
00195 /* Exported functions ---------------------------------------------------------*/
00196
00197 /** @addtogroup RTC_Exported_Functions
00198   * @{
00199   */
00200
00201 /** @addtogroup RTC_Exported_Functions_Group1
00202  *  @brief    Initialization and Configuration functions
00203  *
00204 @verbatim
00205  ===============================================================================
00206               ##### Initialization and de-initialization functions #####
00207  ===============================================================================
00208    [..] This section provides functions allowing to initialize and configure the
00209          RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
00210          RTC registers Write protection, enter and exit the RTC initialization mode,
00211          RTC registers synchronization check and reference clock detection enable.
00212          (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
00213              It is split into 2 programmable prescalers to minimize power consumption.
00214              (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
00215              (++) When both prescalers are used, it is recommended to configure the
00216                  asynchronous prescaler to a high value to minimize power consumption.
00217          (#) All RTC registers are Write protected. Writing to the RTC registers
00218              is enabled by writing a key into the Write Protection register, RTC_WPR.
00219          (#) To configure the RTC Calendar, user application should enter
00220              initialization mode. In this mode, the calendar counter is stopped
00221              and its value can be updated. When the initialization sequence is
00222              complete, the calendar restarts counting after 4 RTCCLK cycles.
00223          (#) To read the calendar through the shadow registers after Calendar
00224              initialization, calendar update or after wakeup from low power modes
00225              the software must first clear the RSF flag. The software must then
00226              wait until it is set again before reading the calendar, which means
00227              that the calendar registers have been correctly copied into the
00228              RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
00229              implements the above software sequence (RSF clear and RSF check).
00230
00231 @endverbatim
00232   * @{
00233   */
00234
00235 /**
00236   * @brief  Initialize the RTC according to the specified parameters
00237   *         in the RTC_InitTypeDef structure and initialize the associated handle.
00238   * @param  hrtc RTC handle
00239   * @retval HAL status
00240   */
00241 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
00242 {
00243   /* Check the RTC peripheral state */
00244   if(hrtc == NULL)
00245   {
00246      return HAL_ERROR;
00247   }
00248
00249   /* Check the parameters */
00250   assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
00251   assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
00252   assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
00253   assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
00254   assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
00255   assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
00256   assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
00257
00258   if(hrtc->State == HAL_RTC_STATE_RESET)
00259   {
00260     /* Allocate lock resource and initialize it */
00261     hrtc->Lock = HAL_UNLOCKED;
00262
00263     /* Initialize RTC MSP */
00264     HAL_RTC_MspInit(hrtc);
00265   }
00266
00267   /* Set RTC state */
00268   hrtc->State = HAL_RTC_STATE_BUSY;
00269
00270   /* Disable the write protection for RTC registers */
00271   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00272
00273   /* Set Initialization mode */
00274   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00275   {
00276     /* Enable the write protection for RTC registers */
00277     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00278
00279     /* Set RTC state */
00280     hrtc->State = HAL_RTC_STATE_ERROR;
00281
00282     return HAL_ERROR;
00283   }
00284   else
00285   {
00286     /* Clear RTC_CR FMT, OSEL and POL Bits */
00287     hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
00288     /* Set RTC_CR register */
00289     hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
00290
00291     /* Configure the RTC PRER */
00292     hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
00293     hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
00294
00295     /* Exit Initialization mode */
00296     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
00297
00298     /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00299     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
00300     {
00301       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00302       {
00303         /* Enable the write protection for RTC registers */
00304         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00305
00306         hrtc->State = HAL_RTC_STATE_ERROR;
00307
00308         return HAL_ERROR;
00309       }
00310     }
00311
00312     hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
00313     hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
00314
00315     /* Enable the write protection for RTC registers */
00316     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00317
00318     /* Set RTC state */
00319     hrtc->State = HAL_RTC_STATE_READY;
00320
00321     return HAL_OK;
00322   }
00323 }
00324
00325 /**
00326   * @brief  DeInitialize the RTC peripheral.
00327   * @param  hrtc RTC handle
00328   * @note   This function doesn't reset the RTC Backup Data registers.
00329   * @retval HAL status
00330   */
00331 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
00332 {
00333   uint32_t tickstart = 0U;
00334
00335   /* Check the parameters */
00336   assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
00337
00338   /* Set RTC state */
00339   hrtc->State = HAL_RTC_STATE_BUSY;
00340
00341   /* Disable the write protection for RTC registers */
00342   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00343
00344   /* Set Initialization mode */
00345   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00346   {
00347     /* Enable the write protection for RTC registers */
00348     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00349
00350     /* Set RTC state */
00351     hrtc->State = HAL_RTC_STATE_ERROR;
00352
00353     return HAL_ERROR;
00354   }
00355   else
00356   {
00357     /* Reset TR, DR and CR registers */
00358     hrtc->Instance->TR = 0x00000000U;
00359     hrtc->Instance->DR = (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0);
00360     /* Reset All CR bits except CR[2:0] */
00361     hrtc->Instance->CR &= RTC_CR_WUCKSEL;
00362
00363     tickstart = HAL_GetTick();
00364
00365     /* Wait till WUTWF flag is set and if Time out is reached exit */
00366     while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
00367     {
00368       if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
00369       {
00370         /* Enable the write protection for RTC registers */
00371         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00372
00373         /* Set RTC state */
00374         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00375
00376         return HAL_TIMEOUT;
00377       }
00378     }
00379
00380     /* Reset all RTC CR register bits */
00381     hrtc->Instance->CR &= 0x00000000U;
00382     hrtc->Instance->WUTR = RTC_WUTR_WUT;
00383     hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU));
00384     hrtc->Instance->ALRMAR = 0x00000000U;
00385     hrtc->Instance->ALRMBR = 0x00000000U;
00386     hrtc->Instance->SHIFTR = 0x00000000U;
00387     hrtc->Instance->CALR = 0x00000000U;
00388     hrtc->Instance->ALRMASSR = 0x00000000U;
00389     hrtc->Instance->ALRMBSSR = 0x00000000U;
00390
00391     /* Reset ISR register and exit initialization mode */
00392     hrtc->Instance->ISR = 0x00000000U;
00393
00394     /* Reset Tamper and alternate functions configuration register */
00395     hrtc->Instance->TAFCR = 0x00000000U;
00396
00397     /* If  RTC_CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
00398     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
00399     {
00400       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00401       {
00402         /* Enable the write protection for RTC registers */
00403         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00404
00405         hrtc->State = HAL_RTC_STATE_ERROR;
00406
00407         return HAL_ERROR;
00408       }
00409     }
00410   }
00411
00412   /* Enable the write protection for RTC registers */
00413   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00414
00415   /* De-Initialize RTC MSP */
00416   HAL_RTC_MspDeInit(hrtc);
00417
00418   hrtc->State = HAL_RTC_STATE_RESET;
00419
00420   /* Release Lock */
00421   __HAL_UNLOCK(hrtc);
00422
00423   return HAL_OK;
00424 }
00425
00426 /**
00427   * @brief  Initialize the RTC MSP.
00428   * @param  hrtc RTC handle
00429   * @retval None
00430   */
00431 __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
00432 {
00433   /* Prevent unused argument(s) compilation warning */
00434   UNUSED(hrtc);
00435
00436   /* NOTE : This function should not be modified, when the callback is needed,
00437             the HAL_RTC_MspInit could be implemented in the user file
00438    */
00439 }
00440
00441 /**
00442   * @brief  DeInitialize the RTC MSP.
00443   * @param  hrtc RTC handle
00444   * @retval None
00445   */
00446 __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
00447 {
00448   /* Prevent unused argument(s) compilation warning */
00449   UNUSED(hrtc);
00450
00451   /* NOTE : This function should not be modified, when the callback is needed,
00452             the HAL_RTC_MspDeInit could be implemented in the user file
00453    */
00454 }
00455
00456 /**
00457   * @}
00458   */
00459
00460 /** @addtogroup RTC_Exported_Functions_Group2
00461  *  @brief   RTC Time and Date functions
00462  *
00463 @verbatim
00464  ===============================================================================
00465                  ##### RTC Time and Date functions #####
00466  ===============================================================================
00467
00468  [..] This section provides functions allowing to configure Time and Date features
00469
00470 @endverbatim
00471   * @{
00472   */
00473
00474 /**
00475   * @brief  Set RTC current time.
00476   * @param  hrtc RTC handle
00477   * @param  sTime Pointer to Time structure
00478   * @param  Format Specifies the format of the entered parameters.
00479   *          This parameter can be one of the following values:
00480   *            @arg RTC_FORMAT_BIN: Binary data format
00481   *            @arg RTC_FORMAT_BCD: BCD data format
00482   * @retval HAL status
00483   */
00484 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00485 {
00486   uint32_t tmpreg = 0U;
00487
00488  /* Check the parameters */
00489   assert_param(IS_RTC_FORMAT(Format));
00490   assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
00491   assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
00492
00493   /* Process Locked */
00494   __HAL_LOCK(hrtc);
00495
00496   hrtc->State = HAL_RTC_STATE_BUSY;
00497
00498   if(Format == RTC_FORMAT_BIN)
00499   {
00500     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00501     {
00502       assert_param(IS_RTC_HOUR12(sTime->Hours));
00503       assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00504     }
00505     else
00506     {
00507       sTime->TimeFormat = 0x00U;
00508       assert_param(IS_RTC_HOUR24(sTime->Hours));
00509     }
00510     assert_param(IS_RTC_MINUTES(sTime->Minutes));
00511     assert_param(IS_RTC_SECONDS(sTime->Seconds));
00512
00513     tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
00514                         ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
00515                         ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
00516                         (((uint32_t)sTime->TimeFormat) << 16U));
00517   }
00518   else
00519   {
00520     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00521     {
00522       tmpreg = RTC_Bcd2ToByte(sTime->Hours);
00523       assert_param(IS_RTC_HOUR12(tmpreg));
00524       assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00525     }
00526     else
00527     {
00528       sTime->TimeFormat = 0x00U;
00529       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
00530     }
00531     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
00532     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
00533     tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
00534               ((uint32_t)(sTime->Minutes) << 8U) | \
00535               ((uint32_t)sTime->Seconds) | \
00536               ((uint32_t)(sTime->TimeFormat) << 16U));
00537   }
00538
00539   /* Disable the write protection for RTC registers */
00540   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00541
00542   /* Set Initialization mode */
00543   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00544   {
00545     /* Enable the write protection for RTC registers */
00546     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00547
00548     /* Set RTC state */
00549     hrtc->State = HAL_RTC_STATE_ERROR;
00550
00551     /* Process Unlocked */
00552     __HAL_UNLOCK(hrtc);
00553
00554     return HAL_ERROR;
00555   }
00556   else
00557   {
00558     /* Set the RTC_TR register */
00559     hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
00560
00561     /* Clear the bits to be configured */
00562     hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK);
00563
00564     /* Configure the RTC_CR register */
00565     hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
00566
00567     /* Exit Initialization mode */
00568     hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
00569
00570     /* If  CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
00571     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
00572     {
00573       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00574       {
00575         /* Enable the write protection for RTC registers */
00576         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00577
00578         hrtc->State = HAL_RTC_STATE_ERROR;
00579
00580         /* Process Unlocked */
00581         __HAL_UNLOCK(hrtc);
00582
00583         return HAL_ERROR;
00584       }
00585     }
00586
00587     /* Enable the write protection for RTC registers */
00588     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00589
00590    hrtc->State = HAL_RTC_STATE_READY;
00591
00592    __HAL_UNLOCK(hrtc);
00593
00594    return HAL_OK;
00595   }
00596 }
00597
00598 /**
00599   * @brief  Get RTC current time.
00600   * @param  hrtc RTC handle
00601   * @param  sTime Pointer to Time structure
00602   * @param  Format Specifies the format of the entered parameters.
00603   *          This parameter can be one of the following values:
00604   *            @arg RTC_FORMAT_BIN: Binary data format
00605   *            @arg RTC_FORMAT_BCD: BCD data format
00606   * @note  You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
00607   *        value in second fraction ratio with time unit following generic formula:
00608   *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
00609   *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
00610   * @note   Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
00611   *         in the higher-order calendar shadow registers.
00612   * @retval HAL status
00613   */
00614 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00615 {
00616   uint32_t tmpreg = 0U;
00617
00618   /* Check the parameters */
00619   assert_param(IS_RTC_FORMAT(Format));
00620
00621   /* Get subseconds structure field from the corresponding register*/
00622   sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
00623
00624   /* Get SecondFraction structure field from the corresponding register field*/
00625   sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
00626
00627   /* Get the TR register */
00628   tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
00629
00630   /* Fill the structure fields with the read parameters */
00631   sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
00632   sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8U);
00633   sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
00634   sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U);
00635
00636   /* Check the input parameters format */
00637   if(Format == RTC_FORMAT_BIN)
00638   {
00639     /* Convert the time structure parameters to Binary format */
00640     sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
00641     sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
00642     sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
00643   }
00644
00645   return HAL_OK;
00646 }
00647
00648 /**
00649   * @brief  Set RTC current date.
00650   * @param  hrtc RTC handle
00651   * @param  sDate Pointer to date structure
00652   * @param  Format specifies the format of the entered parameters.
00653   *          This parameter can be one of the following values:
00654   *            @arg RTC_FORMAT_BIN: Binary data format
00655   *            @arg RTC_FORMAT_BCD: BCD data format
00656   * @retval HAL status
00657   */
00658 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
00659 {
00660   uint32_t datetmpreg = 0U;
00661
00662  /* Check the parameters */
00663   assert_param(IS_RTC_FORMAT(Format));
00664
00665  /* Process Locked */
00666  __HAL_LOCK(hrtc);
00667
00668   hrtc->State = HAL_RTC_STATE_BUSY;
00669
00670   if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
00671   {
00672     sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
00673   }
00674
00675   assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
00676
00677   if(Format == RTC_FORMAT_BIN)
00678   {
00679     assert_param(IS_RTC_YEAR(sDate->Year));
00680     assert_param(IS_RTC_MONTH(sDate->Month));
00681     assert_param(IS_RTC_DATE(sDate->Date));
00682
00683    datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
00684                  ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
00685                  ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
00686                  ((uint32_t)sDate->WeekDay << 13U));
00687   }
00688   else
00689   {
00690     assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
00691     datetmpreg = RTC_Bcd2ToByte(sDate->Month);
00692     assert_param(IS_RTC_MONTH(datetmpreg));
00693     datetmpreg = RTC_Bcd2ToByte(sDate->Date);
00694     assert_param(IS_RTC_DATE(datetmpreg));
00695
00696     datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
00697                   (((uint32_t)sDate->Month) << 8U) | \
00698                   ((uint32_t)sDate->Date) | \
00699                   (((uint32_t)sDate->WeekDay) << 13U));
00700   }
00701
00702   /* Disable the write protection for RTC registers */
00703   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00704
00705   /* Set Initialization mode */
00706   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00707   {
00708     /* Enable the write protection for RTC registers */
00709     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00710
00711     /* Set RTC state*/
00712     hrtc->State = HAL_RTC_STATE_ERROR;
00713
00714     /* Process Unlocked */
00715     __HAL_UNLOCK(hrtc);
00716
00717     return HAL_ERROR;
00718   }
00719   else
00720   {
00721     /* Set the RTC_DR register */
00722     hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
00723
00724     /* Exit Initialization mode */
00725     hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
00726
00727     /* If  CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
00728     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
00729     {
00730       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00731       {
00732         /* Enable the write protection for RTC registers */
00733         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00734
00735         hrtc->State = HAL_RTC_STATE_ERROR;
00736
00737         /* Process Unlocked */
00738         __HAL_UNLOCK(hrtc);
00739
00740         return HAL_ERROR;
00741       }
00742     }
00743
00744     /* Enable the write protection for RTC registers */
00745     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00746
00747     hrtc->State = HAL_RTC_STATE_READY ;
00748
00749     /* Process Unlocked */
00750     __HAL_UNLOCK(hrtc);
00751
00752     return HAL_OK;
00753   }
00754 }
00755
00756 /**
00757   * @brief  Get RTC current date.
00758   * @param  hrtc RTC handle
00759   * @param  sDate Pointer to Date structure
00760   * @param  Format Specifies the format of the entered parameters.
00761   *          This parameter can be one of the following values:
00762   *            @arg RTC_FORMAT_BIN :  Binary data format
00763   *            @arg RTC_FORMAT_BCD :  BCD data format
00764   * @retval HAL status
00765   */
00766 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
00767 {
00768   uint32_t datetmpreg = 0U;
00769
00770   /* Check the parameters */
00771   assert_param(IS_RTC_FORMAT(Format));
00772
00773   /* Get the DR register */
00774   datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
00775
00776   /* Fill the structure fields with the read parameters */
00777   sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
00778   sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
00779   sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
00780   sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U);
00781
00782   /* Check the input parameters format */
00783   if(Format == RTC_FORMAT_BIN)
00784   {
00785     /* Convert the date structure parameters to Binary format */
00786     sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
00787     sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
00788     sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
00789   }
00790   return HAL_OK;
00791 }
00792
00793 /**
00794   * @}
00795   */
00796
00797 /** @addtogroup RTC_Exported_Functions_Group3
00798  *  @brief   RTC Alarm functions
00799  *
00800 @verbatim
00801  ===============================================================================
00802                  ##### RTC Alarm functions #####
00803  ===============================================================================
00804
00805  [..] This section provides functions allowing to configure Alarm feature
00806
00807 @endverbatim
00808   * @{
00809   */
00810 /**
00811   * @brief  Set the specified RTC Alarm.
00812   * @param  hrtc RTC handle
00813   * @param  sAlarm Pointer to Alarm structure
00814   * @param  Format Specifies the format of the entered parameters.
00815   *          This parameter can be one of the following values:
00816   *             @arg RTC_FORMAT_BIN: Binary data format
00817   *             @arg RTC_FORMAT_BCD: BCD data format
00818   * @retval HAL status
00819   */
00820 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
00821 {
00822   uint32_t tickstart = 0U;
00823   uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
00824
00825   /* Check the parameters */
00826   assert_param(IS_RTC_FORMAT(Format));
00827   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
00828   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
00829   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
00830   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
00831   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
00832
00833   /* Process Locked */
00834   __HAL_LOCK(hrtc);
00835
00836   hrtc->State = HAL_RTC_STATE_BUSY;
00837
00838   if(Format == RTC_FORMAT_BIN)
00839   {
00840     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00841     {
00842       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
00843       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
00844     }
00845     else
00846     {
00847       sAlarm->AlarmTime.TimeFormat = 0x00U;
00848       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
00849     }
00850     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
00851     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
00852
00853     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
00854     {
00855       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
00856     }
00857     else
00858     {
00859       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
00860     }
00861
00862     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
00863               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
00864               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
00865               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
00866               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
00867               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
00868               ((uint32_t)sAlarm->AlarmMask));
00869   }
00870   else
00871   {
00872     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00873     {
00874       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
00875       assert_param(IS_RTC_HOUR12(tmpreg));
00876       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
00877     }
00878     else
00879     {
00880       sAlarm->AlarmTime.TimeFormat = 0x00U;
00881       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
00882     }
00883
00884     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
00885     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
00886
00887     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
00888     {
00889       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
00890       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
00891     }
00892     else
00893     {
00894       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
00895       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
00896     }
00897
00898     tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
00899               ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
00900               ((uint32_t) sAlarm->AlarmTime.Seconds) | \
00901               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
00902               ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
00903               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
00904               ((uint32_t)sAlarm->AlarmMask));
00905   }
00906
00907   /* Configure the Alarm A or Alarm B Sub Second registers */
00908   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
00909
00910   /* Disable the write protection for RTC registers */
00911   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00912
00913   /* Configure the Alarm register */
00914   if(sAlarm->Alarm == RTC_ALARM_A)
00915   {
00916     /* Disable the Alarm A interrupt */
00917     __HAL_RTC_ALARMA_DISABLE(hrtc);
00918
00919     /* In case of interrupt mode is used, the interrupt source must disabled */
00920     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
00921
00922     tickstart = HAL_GetTick();
00923     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
00924     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
00925     {
00926       if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
00927       {
00928         /* Enable the write protection for RTC registers */
00929         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00930
00931         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00932
00933         /* Process Unlocked */
00934         __HAL_UNLOCK(hrtc);
00935
00936         return HAL_TIMEOUT;
00937       }
00938     }
00939
00940     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
00941     /* Configure the Alarm A Sub Second register */
00942     hrtc->Instance->ALRMASSR = subsecondtmpreg;
00943     /* Configure the Alarm state: Enable Alarm */
00944     __HAL_RTC_ALARMA_ENABLE(hrtc);
00945   }
00946   else
00947   {
00948     /* Disable the Alarm B interrupt */
00949     __HAL_RTC_ALARMB_DISABLE(hrtc);
00950
00951     /* In case of interrupt mode is used, the interrupt source must disabled */
00952     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
00953
00954     tickstart = HAL_GetTick();
00955     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
00956     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
00957     {
00958       if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
00959       {
00960         /* Enable the write protection for RTC registers */
00961         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00962
00963         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00964
00965         /* Process Unlocked */
00966         __HAL_UNLOCK(hrtc);
00967
00968         return HAL_TIMEOUT;
00969       }
00970     }
00971
00972     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
00973     /* Configure the Alarm B Sub Second register */
00974     hrtc->Instance->ALRMBSSR = subsecondtmpreg;
00975     /* Configure the Alarm state: Enable Alarm */
00976     __HAL_RTC_ALARMB_ENABLE(hrtc);
00977   }
00978
00979   /* Enable the write protection for RTC registers */
00980   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00981
00982   /* Change RTC state */
00983   hrtc->State = HAL_RTC_STATE_READY;
00984
00985   /* Process Unlocked */
00986   __HAL_UNLOCK(hrtc);
00987
00988   return HAL_OK;
00989 }
00990
00991 /**
00992   * @brief  Set the specified RTC Alarm with Interrupt.
00993   * @param  hrtc RTC handle
00994   * @param  sAlarm Pointer to Alarm structure
00995   * @param  Format Specifies the format of the entered parameters.
00996   *          This parameter can be one of the following values:
00997   *             @arg RTC_FORMAT_BIN: Binary data format
00998   *             @arg RTC_FORMAT_BCD: BCD data format
00999   * @note   The Alarm register can only be written when the corresponding Alarm
01000   *         is disabled (Use the HAL_RTC_DeactivateAlarm()).
01001   * @note   The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
01002   * @retval HAL status
01003   */
01004 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
01005 {
01006   uint32_t tickstart = 0U;
01007   uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
01008
01009   /* Check the parameters */
01010   assert_param(IS_RTC_FORMAT(Format));
01011   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
01012   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
01013   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
01014   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
01015   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
01016
01017   /* Process Locked */
01018   __HAL_LOCK(hrtc);
01019
01020   hrtc->State = HAL_RTC_STATE_BUSY;
01021
01022   if(Format == RTC_FORMAT_BIN)
01023   {
01024     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
01025     {
01026       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
01027       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01028     }
01029     else
01030     {
01031       sAlarm->AlarmTime.TimeFormat = 0x00U;
01032       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
01033     }
01034     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
01035     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
01036
01037     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01038     {
01039       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
01040     }
01041     else
01042     {
01043       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
01044     }
01045     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
01046               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
01047               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
01048               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
01049               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
01050               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01051               ((uint32_t)sAlarm->AlarmMask));
01052   }
01053   else
01054   {
01055     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
01056     {
01057       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
01058       assert_param(IS_RTC_HOUR12(tmpreg));
01059       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01060     }
01061     else
01062     {
01063       sAlarm->AlarmTime.TimeFormat = 0x00U;
01064       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01065     }
01066
01067     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
01068     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
01069
01070     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01071     {
01072       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01073       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
01074     }
01075     else
01076     {
01077       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01078       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
01079     }
01080     tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
01081               ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
01082               ((uint32_t) sAlarm->AlarmTime.Seconds) | \
01083               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
01084               ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
01085               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01086               ((uint32_t)sAlarm->AlarmMask));
01087   }
01088   /* Configure the Alarm A or Alarm B Sub Second registers */
01089   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
01090
01091   /* Disable the write protection for RTC registers */
01092   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01093
01094   /* Configure the Alarm register */
01095   if(sAlarm->Alarm == RTC_ALARM_A)
01096   {
01097     /* Disable the Alarm A interrupt */
01098     __HAL_RTC_ALARMA_DISABLE(hrtc);
01099
01100     /* Clear flag alarm A */
01101     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01102
01103     tickstart = HAL_GetTick();
01104     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
01105     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
01106     {
01107       if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
01108       {
01109         /* Enable the write protection for RTC registers */
01110         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01111
01112         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01113
01114         /* Process Unlocked */
01115         __HAL_UNLOCK(hrtc);
01116
01117         return HAL_TIMEOUT;
01118       }
01119     }
01120
01121     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
01122     /* Configure the Alarm A Sub Second register */
01123     hrtc->Instance->ALRMASSR = subsecondtmpreg;
01124     /* Configure the Alarm state: Enable Alarm */
01125     __HAL_RTC_ALARMA_ENABLE(hrtc);
01126     /* Configure the Alarm interrupt */
01127     __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
01128   }
01129   else
01130   {
01131     /* Disable the Alarm B interrupt */
01132     __HAL_RTC_ALARMB_DISABLE(hrtc);
01133
01134     /* Clear flag alarm B */
01135     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01136
01137     tickstart = HAL_GetTick();
01138     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
01139     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
01140     {
01141       if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
01142       {
01143         /* Enable the write protection for RTC registers */
01144         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01145
01146         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01147
01148         /* Process Unlocked */
01149         __HAL_UNLOCK(hrtc);
01150
01151         return HAL_TIMEOUT;
01152       }
01153     }
01154
01155     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
01156     /* Configure the Alarm B Sub Second register */
01157     hrtc->Instance->ALRMBSSR = subsecondtmpreg;
01158     /* Configure the Alarm state: Enable Alarm */
01159     __HAL_RTC_ALARMB_ENABLE(hrtc);
01160     /* Configure the Alarm interrupt */
01161     __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
01162   }
01163
01164   /* RTC Alarm Interrupt Configuration: EXTI configuration */
01165   __HAL_RTC_ALARM_EXTI_ENABLE_IT();
01166
01167   __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
01168
01169   /* Enable the write protection for RTC registers */
01170   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01171
01172   hrtc->State = HAL_RTC_STATE_READY;
01173
01174   /* Process Unlocked */
01175   __HAL_UNLOCK(hrtc);
01176
01177   return HAL_OK;
01178 }
01179
01180 /**
01181   * @brief  Deactivate the specified RTC Alarm.
01182   * @param  hrtc RTC handle
01183   * @param  Alarm Specifies the Alarm.
01184   *          This parameter can be one of the following values:
01185   *            @arg RTC_ALARM_A :  AlarmA
01186   *            @arg RTC_ALARM_B :  AlarmB
01187   * @retval HAL status
01188   */
01189 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
01190 {
01191   uint32_t tickstart = 0U;
01192
01193   /* Check the parameters */
01194   assert_param(IS_RTC_ALARM(Alarm));
01195
01196   /* Process Locked */
01197   __HAL_LOCK(hrtc);
01198
01199   hrtc->State = HAL_RTC_STATE_BUSY;
01200
01201   /* Disable the write protection for RTC registers */
01202   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01203
01204   if(Alarm == RTC_ALARM_A)
01205   {
01206     /* AlarmA */
01207     __HAL_RTC_ALARMA_DISABLE(hrtc);
01208
01209     /* In case of interrupt mode is used, the interrupt source must disabled */
01210     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
01211
01212     tickstart = HAL_GetTick();
01213
01214     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01215     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
01216     {
01217       if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
01218       {
01219         /* Enable the write protection for RTC registers */
01220         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01221
01222         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01223
01224         /* Process Unlocked */
01225         __HAL_UNLOCK(hrtc);
01226
01227         return HAL_TIMEOUT;
01228       }
01229     }
01230   }
01231   else
01232   {
01233     /* AlarmB */
01234     __HAL_RTC_ALARMB_DISABLE(hrtc);
01235
01236     /* In case of interrupt mode is used, the interrupt source must disabled */
01237     __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
01238
01239     tickstart = HAL_GetTick();
01240
01241     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01242     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
01243     {
01244       if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
01245       {
01246         /* Enable the write protection for RTC registers */
01247         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01248
01249         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01250
01251         /* Process Unlocked */
01252         __HAL_UNLOCK(hrtc);
01253
01254         return HAL_TIMEOUT;
01255       }
01256     }
01257   }
01258   /* Enable the write protection for RTC registers */
01259   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01260
01261   hrtc->State = HAL_RTC_STATE_READY;
01262
01263   /* Process Unlocked */
01264   __HAL_UNLOCK(hrtc);
01265
01266   return HAL_OK;
01267 }
01268
01269 /**
01270   * @brief  Get the RTC Alarm value and masks.
01271   * @param  hrtc RTC handle
01272   * @param  sAlarm Pointer to Date structure
01273   * @param  Alarm Specifies the Alarm.
01274   *          This parameter can be one of the following values:
01275   *             @arg RTC_ALARM_A: AlarmA
01276   *             @arg RTC_ALARM_B: AlarmB
01277   * @param  Format Specifies the format of the entered parameters.
01278   *          This parameter can be one of the following values:
01279   *             @arg RTC_FORMAT_BIN: Binary data format
01280   *             @arg RTC_FORMAT_BCD: BCD data format
01281   * @retval HAL status
01282   */
01283 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
01284 {
01285   uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
01286
01287   /* Check the parameters */
01288   assert_param(IS_RTC_FORMAT(Format));
01289   assert_param(IS_RTC_ALARM(Alarm));
01290
01291   if(Alarm == RTC_ALARM_A)
01292   {
01293     /* AlarmA */
01294     sAlarm->Alarm = RTC_ALARM_A;
01295
01296     tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
01297     subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
01298   }
01299   else
01300   {
01301     sAlarm->Alarm = RTC_ALARM_B;
01302
01303     tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
01304     subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
01305   }
01306
01307   /* Fill the structure with the read parameters */
01308   sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U);
01309   sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U);
01310   sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
01311   sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U);
01312   sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
01313   sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U);
01314   sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
01315   sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
01316
01317   if(Format == RTC_FORMAT_BIN)
01318   {
01319     sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
01320     sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
01321     sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
01322     sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01323   }
01324
01325   return HAL_OK;
01326 }
01327
01328 /**
01329   * @brief  Handle Alarm interrupt request.
01330   * @param  hrtc RTC handle
01331   * @retval None
01332   */
01333 void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
01334 {
01335   /* Get the AlarmA interrupt source enable status */
01336   if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET)
01337   {
01338     /* Get the pending status of the AlarmA Interrupt */
01339     if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)
01340     {
01341       /* AlarmA callback */
01342       HAL_RTC_AlarmAEventCallback(hrtc);
01343
01344       /* Clear the AlarmA interrupt pending bit */
01345       __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
01346     }
01347   }
01348
01349   /* Get the AlarmB interrupt source enable status */
01350   if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET)
01351   {
01352     /* Get the pending status of the AlarmB Interrupt */
01353     if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET)
01354     {
01355       /* AlarmB callback */
01356       HAL_RTCEx_AlarmBEventCallback(hrtc);
01357
01358       /* Clear the AlarmB interrupt pending bit */
01359       __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
01360     }
01361   }
01362
01363   /* Clear the EXTI's line Flag for RTC Alarm */
01364   __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
01365
01366   /* Change RTC state */
01367   hrtc->State = HAL_RTC_STATE_READY;
01368 }
01369
01370 /**
01371   * @brief  Alarm A callback.
01372   * @param  hrtc RTC handle
01373   * @retval None
01374   */
01375 __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
01376 {
01377   /* Prevent unused argument(s) compilation warning */
01378   UNUSED(hrtc);
01379
01380   /* NOTE : This function should not be modified, when the callback is needed,
01381             the HAL_RTC_AlarmAEventCallback could be implemented in the user file
01382    */
01383 }
01384
01385 /**
01386   * @brief  Handle AlarmA Polling request.
01387   * @param  hrtc RTC handle
01388   * @param  Timeout Timeout duration
01389   * @retval HAL status
01390   */
01391 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01392 {
01393
01394   uint32_t tickstart = HAL_GetTick();
01395
01396   while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
01397   {
01398     if(Timeout != HAL_MAX_DELAY)
01399     {
01400       if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
01401       {
01402         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01403         return HAL_TIMEOUT;
01404       }
01405     }
01406   }
01407
01408   /* Clear the Alarm interrupt pending bit */
01409   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01410
01411   /* Change RTC state */
01412   hrtc->State = HAL_RTC_STATE_READY;
01413
01414   return HAL_OK;
01415 }
01416
01417 /**
01418   * @}
01419   */
01420
01421 /** @@addtogroup RTC_Exported_Functions_Group4 Peripheral Control functions
01422  *  @brief   Peripheral Control functions
01423  *
01424 @verbatim
01425  ===============================================================================
01426                      ##### Peripheral Control functions #####
01427  ===============================================================================
01428     [..]
01429     This subsection provides functions allowing to
01430       (+) Wait for RTC Time and Date Synchronization
01431
01432 @endverbatim
01433   * @{
01434   */
01435
01436 /**
01437   * @brief  Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
01438   *         synchronized with RTC APB clock.
01439   * @note   The RTC Resynchronization mode is write protected, use the
01440   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
01441   * @note   To read the calendar through the shadow registers after Calendar
01442   *         initialization, calendar update or after wakeup from low power modes
01443   *         the software must first clear the RSF flag.
01444   *         The software must then wait until it is set again before reading
01445   *         the calendar, which means that the calendar registers have been
01446   *         correctly copied into the RTC_TR and RTC_DR shadow registers.
01447   * @param  hrtc RTC handle
01448   * @retval HAL status
01449   */
01450 HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
01451 {
01452   uint32_t tickstart = 0U;
01453
01454   /* Clear RSF flag */
01455   hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
01456
01457   tickstart = HAL_GetTick();
01458
01459   /* Wait the registers to be synchronised */
01460   while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
01461   {
01462     if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
01463     {
01464       return HAL_TIMEOUT;
01465     }
01466   }
01467
01468   return HAL_OK;
01469 }
01470
01471 /**
01472   * @}
01473   */
01474
01475 /** @@addtogroup RTC_Exported_Functions_Group5 Peripheral State functions
01476  *  @brief   Peripheral State functions
01477  *
01478 @verbatim
01479  ===============================================================================
01480                      ##### Peripheral State functions #####
01481  ===============================================================================
01482     [..]
01483     This subsection provides functions allowing to
01484       (+) Get RTC state
01485
01486 @endverbatim
01487   * @{
01488   */
01489 /**
01490   * @brief  Return the RTC handle state.
01491   * @param  hrtc RTC handle
01492   * @retval HAL state
01493   */
01494 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
01495 {
01496   /* Return RTC handle state */
01497   return hrtc->State;
01498 }
01499
01500 /**
01501   * @}
01502   */
01503
01504 /**
01505   * @}
01506   */
01507
01508 /** @@addtogroup RTC_Private_Functions RTC Private Functions
01509   * @{
01510   */
01511
01512 /**
01513   * @brief  Enter the RTC Initialization mode.
01514   * @note   The RTC Initialization mode is write protected, use the
01515   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
01516   * @param  hrtc RTC handle
01517   * @retval An ErrorStatus enumeration value:
01518   *          - HAL_OK : RTC is in Init mode
01519   *          - HAL_TIMEOUT : RTC is not in Init mode and in Timeout
01520   */
01521 HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
01522 {
01523   uint32_t tickstart = 0U;
01524
01525   /* Check if the Initialization mode is set */
01526   if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
01527   {
01528     /* Set the Initialization mode */
01529     hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
01530
01531     tickstart = HAL_GetTick();
01532     /* Wait till RTC is in INIT state and if Time out is reached exit */
01533     while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
01534     {
01535       if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
01536       {
01537         return HAL_TIMEOUT;
01538       }
01539     }
01540   }
01541
01542   return HAL_OK;
01543 }
01544
01545
01546 /**
01547   * @brief  Convert a 2 digit decimal to BCD format.
01548   * @param  Value Byte to be converted
01549   * @retval Converted byte
01550   */
01551 uint8_t RTC_ByteToBcd2(uint8_t Value)
01552 {
01553   uint32_t bcdhigh = 0U;
01554
01555   while(Value >= 10U)
01556   {
01557     bcdhigh++;
01558     Value -= 10U;
01559   }
01560
01561   return  ((uint8_t)(bcdhigh << 4U) | Value);
01562 }
01563
01564 /**
01565   * @brief  Convert from 2 digit BCD to Binary.
01566   * @param  Value BCD value to be converted
01567   * @retval Converted word
01568   */
01569 uint8_t RTC_Bcd2ToByte(uint8_t Value)
01570 {
01571   uint32_t tmp = 0U;
01572   tmp = ((uint8_t)(Value & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U;
01573   return (tmp + (Value & (uint8_t)0x0FU));
01574 }
01575 /**
01576   * @}
01577   */
01578
01579 #endif /* HAL_RTC_MODULE_ENABLED */
01580
01581 /**
01582   * @}
01583   */
01584
01585
01586 /**
01587   * @}
01588   */
01589
01590 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_rtc.h Source File

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stm32f3xx_hal_rtc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_rtc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RTC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_RTC_H
00038 #define __STM32F3xx_HAL_RTC_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @defgroup RTC RTC
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /** @defgroup RTC_Exported_Types RTC Exported Types
00057   * @{
00058   */
00059
00060 /**
00061   * @brief  HAL State structures definition
00062   */
00063 typedef enum
00064 {
00065   HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */
00066   HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */
00067   HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */
00068   HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */
00069   HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */
00070
00071 }HAL_RTCStateTypeDef;
00072
00073 /**
00074   * @brief  RTC Configuration Structure definition
00075   */
00076 typedef struct
00077 {
00078   uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
00079                                  This parameter can be a value of @ref RTC_Hour_Formats */
00080
00081   uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
00082                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
00083
00084   uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
00085                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
00086
00087   uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.
00088                                  This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
00089
00090   uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.
00091                                  This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
00092
00093   uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
00094                                  This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
00095 }RTC_InitTypeDef;
00096
00097 /**
00098   * @brief  RTC Time structure definition
00099   */
00100 typedef struct
00101 {
00102   uint8_t Hours;            /*!< Specifies the RTC Time Hour.
00103                                  This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
00104                                  This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
00105
00106   uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
00107                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00108
00109   uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
00110                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00111
00112   uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
00113                                  This parameter can be a value of @ref RTC_AM_PM_Definitions */
00114
00115   uint32_t SubSeconds;     /*!< Specifies the RTC_SSR RTC Sub Second register content.
00116                                  This parameter corresponds to a time unit range between [0-1] Second
00117                                  with [1 Sec / SecondFraction +1] granularity */
00118
00119   uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
00120                                  corresponding to Synchronous pre-scaler factor value (PREDIV_S)
00121                                  This parameter corresponds to a time unit range between [0-1] Second
00122                                  with [1 Sec / SecondFraction +1] granularity.
00123                                  This field will be used only by HAL_RTC_GetTime function */
00124
00125   uint32_t DayLightSaving;  /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
00126                                  This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
00127
00128   uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
00129                                  in CR register to store the operation.
00130                                  This parameter can be a value of @ref RTC_StoreOperation_Definitions */
00131 }RTC_TimeTypeDef;
00132
00133 /**
00134   * @brief  RTC Date structure definition
00135   */
00136 typedef struct
00137 {
00138   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
00139                          This parameter can be a value of @ref RTC_WeekDay_Definitions */
00140
00141   uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
00142                          This parameter can be a value of @ref RTC_Month_Date_Definitions */
00143
00144   uint8_t Date;     /*!< Specifies the RTC Date.
00145                          This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
00146
00147   uint8_t Year;     /*!< Specifies the RTC Date Year.
00148                          This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
00149
00150 }RTC_DateTypeDef;
00151
00152 /**
00153   * @brief  RTC Alarm structure definition
00154   */
00155 typedef struct
00156 {
00157   RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
00158
00159   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
00160                                       This parameter can be a value of @ref RTC_AlarmMask_Definitions */
00161
00162   uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
00163                                       This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
00164
00165   uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
00166                                       This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
00167
00168   uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
00169                                       If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
00170                                       If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
00171
00172   uint32_t Alarm;                /*!< Specifies the alarm .
00173                                       This parameter can be a value of @ref RTC_Alarms_Definitions */
00174 }RTC_AlarmTypeDef;
00175
00176 /**
00177   * @brief  RTC Handle Structure definition
00178   */
00179 typedef struct
00180 {
00181   RTC_TypeDef               *Instance;  /*!< Register base address    */
00182
00183   RTC_InitTypeDef           Init;       /*!< RTC required parameters  */
00184
00185   HAL_LockTypeDef           Lock;       /*!< RTC locking object       */
00186
00187   __IO HAL_RTCStateTypeDef  State;      /*!< Time communication state */
00188
00189 }RTC_HandleTypeDef;
00190 /**
00191   * @}
00192   */
00193
00194 /* Exported constants --------------------------------------------------------*/
00195 /** @defgroup RTC_Exported_Constants RTC Exported Constants
00196   * @{
00197   */
00198
00199 /** @defgroup RTC_Hour_Formats RTC Hour Formats
00200   * @{
00201   */
00202 #define RTC_HOURFORMAT_24              0x00000000U
00203 #define RTC_HOURFORMAT_12              RTC_CR_FMT
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
00209   * @{
00210   */
00211 #define RTC_OUTPUT_POLARITY_HIGH       0x00000000U
00212 #define RTC_OUTPUT_POLARITY_LOW        RTC_CR_POL
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
00218   * @{
00219   */
00220 #define RTC_OUTPUT_TYPE_OPENDRAIN      0x00000000U
00221 #define RTC_OUTPUT_TYPE_PUSHPULL       RTC_TAFCR_ALARMOUTTYPE
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
00227   * @{
00228   */
00229 #define RTC_HOURFORMAT12_AM            ((uint8_t)0x00)
00230 #define RTC_HOURFORMAT12_PM            ((uint8_t)0x40)
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
00236   * @{
00237   */
00238 #define RTC_DAYLIGHTSAVING_NONE        0x00000000U
00239 #define RTC_DAYLIGHTSAVING_SUB1H       RTC_CR_SUB1H
00240 #define RTC_DAYLIGHTSAVING_ADD1H       RTC_CR_ADD1H
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
00246   * @{
00247   */
00248 #define RTC_STOREOPERATION_RESET        0x00000000U
00249 #define RTC_STOREOPERATION_SET          RTC_CR_BCK
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions
00255   * @{
00256   */
00257 #define RTC_FORMAT_BIN                      0x000000000U
00258 #define RTC_FORMAT_BCD                      0x000000001U
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
00264   * @{
00265   */
00266 /* Coded in BCD format */
00267 #define RTC_MONTH_JANUARY              ((uint8_t)0x01)
00268 #define RTC_MONTH_FEBRUARY             ((uint8_t)0x02)
00269 #define RTC_MONTH_MARCH                ((uint8_t)0x03)
00270 #define RTC_MONTH_APRIL                ((uint8_t)0x04)
00271 #define RTC_MONTH_MAY                  ((uint8_t)0x05)
00272 #define RTC_MONTH_JUNE                 ((uint8_t)0x06)
00273 #define RTC_MONTH_JULY                 ((uint8_t)0x07)
00274 #define RTC_MONTH_AUGUST               ((uint8_t)0x08)
00275 #define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09)
00276 #define RTC_MONTH_OCTOBER              ((uint8_t)0x10)
00277 #define RTC_MONTH_NOVEMBER             ((uint8_t)0x11)
00278 #define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
00284   * @{
00285   */
00286 #define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01)
00287 #define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02)
00288 #define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03)
00289 #define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04)
00290 #define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05)
00291 #define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06)
00292 #define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07)
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
00298   * @{
00299   */
00300 #define RTC_ALARMDATEWEEKDAYSEL_DATE      0x00000000U
00301 #define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   RTC_ALRMAR_WDSEL
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
00307   * @{
00308   */
00309 #define RTC_ALARMMASK_NONE                0x00000000U
00310 #define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4
00311 #define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3
00312 #define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2
00313 #define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1
00314 #define RTC_ALARMMASK_ALL                 (RTC_ALARMMASK_NONE        | \
00315                                            RTC_ALARMMASK_DATEWEEKDAY | \
00316                                            RTC_ALARMMASK_HOURS       | \
00317                                            RTC_ALARMMASK_MINUTES     | \
00318                                            RTC_ALARMMASK_SECONDS)
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
00324   * @{
00325   */
00326 #define RTC_ALARM_A                       RTC_CR_ALRAE
00327 #define RTC_ALARM_B                       RTC_CR_ALRBE
00328 /**
00329   * @}
00330   */
00331
00332   /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
00333   * @{
00334   */
00335 #define RTC_ALARMSUBSECONDMASK_ALL         0x00000000U            /*!< All Alarm SS fields are masked.
00336                                                                         There is no comparison on sub seconds
00337                                                                         for Alarm */
00338 #define RTC_ALARMSUBSECONDMASK_SS14_1      RTC_ALRMASSR_MASKSS_0  /*!< SS[14:1] are ignored in Alarm
00339                                                                         comparison. Only SS[0] is compared.    */
00340 #define RTC_ALARMSUBSECONDMASK_SS14_2      RTC_ALRMASSR_MASKSS_1  /*!< SS[14:2] are ignored in Alarm
00341                                                                         comparison. Only SS[1:0] are compared  */
00342 #define RTC_ALARMSUBSECONDMASK_SS14_3      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)  /*!< SS[14:3] are ignored in Alarm
00343                                                                         comparison. Only SS[2:0] are compared  */
00344 #define RTC_ALARMSUBSECONDMASK_SS14_4      RTC_ALRMASSR_MASKSS_2  /*!< SS[14:4] are ignored in Alarm
00345                                                                         comparison. Only SS[3:0] are compared  */
00346 #define RTC_ALARMSUBSECONDMASK_SS14_5      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)  /*!< SS[14:5] are ignored in Alarm
00347                                                                         comparison. Only SS[4:0] are compared  */
00348 #define RTC_ALARMSUBSECONDMASK_SS14_6      (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)  /*!< SS[14:6] are ignored in Alarm
00349                                                                         comparison. Only SS[5:0] are compared  */
00350 #define RTC_ALARMSUBSECONDMASK_SS14_7      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)  /*!< SS[14:7] are ignored in Alarm
00351                                                                         comparison. Only SS[6:0] are compared  */
00352 #define RTC_ALARMSUBSECONDMASK_SS14_8      RTC_ALRMASSR_MASKSS_3  /*!< SS[14:8] are ignored in Alarm
00353                                                                         comparison. Only SS[7:0] are compared  */
00354 #define RTC_ALARMSUBSECONDMASK_SS14_9      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14:9] are ignored in Alarm
00355                                                                         comparison. Only SS[8:0] are compared  */
00356 #define RTC_ALARMSUBSECONDMASK_SS14_10     (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14:10] are ignored in Alarm
00357                                                                         comparison. Only SS[9:0] are compared  */
00358 #define RTC_ALARMSUBSECONDMASK_SS14_11     (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14:11] are ignored in Alarm
00359                                                                         comparison. Only SS[10:0] are compared */
00360 #define RTC_ALARMSUBSECONDMASK_SS14_12     (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14:12] are ignored in Alarm
00361                                                                         comparison.Only SS[11:0] are compared  */
00362 #define RTC_ALARMSUBSECONDMASK_SS14_13     (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14:13] are ignored in Alarm
00363                                                                         comparison. Only SS[12:0] are compared */
00364 #define RTC_ALARMSUBSECONDMASK_SS14        (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14] is don't care in Alarm
00365                                                                         comparison.Only SS[13:0] are compared  */
00366 #define RTC_ALARMSUBSECONDMASK_NONE        RTC_ALRMASSR_MASKSS    /*!< SS[14:0] are compared and must match
00367                                                                         to activate alarm. */
00368 /**
00369   * @}
00370   */
00371
00372 /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
00373   * @{
00374   */
00375 #define RTC_IT_TS                         RTC_CR_TSIE
00376 #define RTC_IT_WUT                        RTC_CR_WUTIE
00377 #define RTC_IT_ALRB                       RTC_CR_ALRBIE
00378 #define RTC_IT_ALRA                       RTC_CR_ALRAIE
00379 #define RTC_IT_TAMP                       RTC_TAFCR_TAMPIE       /* Used only to Enable the Tamper Interrupt */
00380 #define RTC_IT_TAMP1                      0x00020000U            /*only for RTC_ISR flag check*/
00381 #define RTC_IT_TAMP2                      0x00040000U            /*only for RTC_ISR flag check*/
00382 #if defined(RTC_TAMPER3_SUPPORT)
00383 #define RTC_IT_TAMP3                      0x00080000U            /*only for RTC_ISR flag check*/
00384 #endif /* RTC_TAMPER3_SUPPORT */
00385 /**
00386   * @}
00387   */
00388
00389 /** @defgroup RTC_Flags_Definitions RTC Flags Definitions
00390   * @{
00391   */
00392 #define RTC_FLAG_RECALPF                  RTC_ISR_RECALPF
00393 #if defined(RTC_TAMPER3_SUPPORT)
00394 #define RTC_FLAG_TAMP3F                   RTC_ISR_TAMP3F
00395 #endif /* RTC_TAMPER3_SUPPORT */
00396 #define RTC_FLAG_TAMP2F                   RTC_ISR_TAMP2F
00397 #define RTC_FLAG_TAMP1F                   RTC_ISR_TAMP1F
00398 #define RTC_FLAG_TSOVF                    RTC_ISR_TSOVF
00399 #define RTC_FLAG_TSF                      RTC_ISR_TSF
00400 #define RTC_FLAG_WUTF                     RTC_ISR_WUTF
00401 #define RTC_FLAG_ALRBF                    RTC_ISR_ALRBF
00402 #define RTC_FLAG_ALRAF                    RTC_ISR_ALRAF
00403 #define RTC_FLAG_INITF                    RTC_ISR_INITF
00404 #define RTC_FLAG_RSF                      RTC_ISR_RSF
00405 #define RTC_FLAG_INITS                    RTC_ISR_INITS
00406 #define RTC_FLAG_SHPF                     RTC_ISR_SHPF
00407 #define RTC_FLAG_WUTWF                    RTC_ISR_WUTWF
00408 #define RTC_FLAG_ALRBWF                   RTC_ISR_ALRBWF
00409 #define RTC_FLAG_ALRAWF                   RTC_ISR_ALRAWF
00410 /**
00411   * @}
00412   */
00413
00414 /**
00415   * @}
00416   */
00417
00418 /* Exported macros -----------------------------------------------------------*/
00419 /** @defgroup RTC_Exported_Macros RTC Exported Macros
00420   * @{
00421   */
00422
00423 /** @brief  Reset RTC handle state
00424   * @param  __HANDLE__ RTC handle.
00425   * @retval None
00426   */
00427 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
00428
00429 /**
00430   * @brief  Disable the write protection for RTC registers.
00431   * @param  __HANDLE__ specifies the RTC handle.
00432   * @retval None
00433   */
00434 #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
00435                         do{                                       \
00436                             (__HANDLE__)->Instance->WPR = 0xCAU;   \
00437                             (__HANDLE__)->Instance->WPR = 0x53U;   \
00438                           } while(0U)
00439
00440 /**
00441   * @brief  Enable the write protection for RTC registers.
00442   * @param  __HANDLE__ specifies the RTC handle.
00443   * @retval None
00444   */
00445 #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
00446                         do{                                       \
00447                             (__HANDLE__)->Instance->WPR = 0xFFU;   \
00448                           } while(0U)
00449
00450 /**
00451   * @brief  Enable the RTC ALARMA peripheral.
00452   * @param  __HANDLE__ specifies the RTC handle.
00453   * @retval None
00454   */
00455 #define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
00456
00457 /**
00458   * @brief  Disable the RTC ALARMA peripheral.
00459   * @param  __HANDLE__ specifies the RTC handle.
00460   * @retval None
00461   */
00462 #define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
00463
00464 /**
00465   * @brief  Enable the RTC ALARMB peripheral.
00466   * @param  __HANDLE__ specifies the RTC handle.
00467   * @retval None
00468   */
00469 #define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
00470
00471 /**
00472   * @brief  Disable the RTC ALARMB peripheral.
00473   * @param  __HANDLE__ specifies the RTC handle.
00474   * @retval None
00475   */
00476 #define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
00477
00478 /**
00479   * @brief  Enable the RTC Alarm interrupt.
00480   * @param  __HANDLE__ specifies the RTC handle.
00481   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
00482   *          This parameter can be any combination of the following values:
00483   *             @arg RTC_IT_ALRA: Alarm A interrupt
00484   *             @arg RTC_IT_ALRB: Alarm B interrupt
00485   * @retval None
00486   */
00487 #define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00488
00489 /**
00490   * @brief  Disable the RTC Alarm interrupt.
00491   * @param  __HANDLE__ specifies the RTC handle.
00492   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
00493   *         This parameter can be any combination of the following values:
00494   *            @arg RTC_IT_ALRA: Alarm A interrupt
00495   *            @arg RTC_IT_ALRB: Alarm B interrupt
00496   * @retval None
00497   */
00498 #define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00499
00500 /**
00501   * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
00502   * @param  __HANDLE__ specifies the RTC handle.
00503   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt to check.
00504   *         This parameter can be:
00505   *            @arg RTC_IT_ALRA: Alarm A interrupt
00506   *            @arg RTC_IT_ALRB: Alarm B interrupt
00507   * @retval None
00508   */
00509 #define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)  (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
00510
00511 /**
00512   * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
00513   * @param  __HANDLE__ specifies the RTC handle.
00514   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
00515   *         This parameter can be:
00516   *            @arg RTC_IT_ALRA: Alarm A interrupt
00517   *            @arg RTC_IT_ALRB: Alarm B interrupt
00518   * @retval None
00519   */
00520 #define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00521
00522 /**
00523   * @brief  Get the selected RTC Alarm's flag status.
00524   * @param  __HANDLE__ specifies the RTC handle.
00525   * @param  __FLAG__ specifies the RTC Alarm Flag sources to check.
00526   *         This parameter can be:
00527   *            @arg RTC_FLAG_ALRAF
00528   *            @arg RTC_FLAG_ALRBF
00529   *            @arg RTC_FLAG_ALRAWF
00530   *            @arg RTC_FLAG_ALRBWF
00531   * @retval None
00532   */
00533 #define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
00534
00535 /**
00536   * @brief  Clear the RTC Alarm's pending flags.
00537   * @param  __HANDLE__ specifies the RTC handle.
00538   * @param  __FLAG__ specifies the RTC Alarm Flag sources to clear.
00539   *         This parameter can be:
00540   *            @arg RTC_FLAG_ALRAF
00541   *            @arg RTC_FLAG_ALRBF
00542   * @retval None
00543   */
00544 #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00545
00546 /**
00547   * @brief  Enable interrupt on the RTC Alarm associated Exti line.
00548   * @retval None
00549   */
00550 #define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
00551
00552 /**
00553   * @brief  Disable interrupt on the RTC Alarm associated Exti line.
00554   * @retval None
00555   */
00556 #define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00557
00558 /**
00559   * @brief  Enable event on the RTC Alarm associated Exti line.
00560   * @retval None.
00561   */
00562 #define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
00563
00564 /**
00565   * @brief  Disable event on the RTC Alarm associated Exti line.
00566   * @retval None.
00567   */
00568 #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00569
00570 /**
00571   * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.
00572   * @retval None.
00573   */
00574 #define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
00575
00576 /**
00577   * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.
00578   * @retval None.
00579   */
00580 #define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00581
00582 /**
00583   * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.
00584   * @retval None.
00585   */
00586 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
00587
00588 /**
00589   * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.
00590   * @retval None.
00591   */
00592 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00593
00594 /**
00595   * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
00596   * @retval None.
00597   */
00598 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
00599
00600 /**
00601   * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
00602   * @retval None.
00603   */
00604 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
00605
00606 /**
00607   * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
00608   * @retval Line Status.
00609   */
00610 #define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
00611
00612 /**
00613   * @brief Clear the RTC Alarm associated Exti line flag.
00614   * @retval None.
00615   */
00616 #define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
00617
00618 /**
00619   * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
00620   * @retval None.
00621   */
00622 #define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
00623 /**
00624   * @}
00625   */
00626
00627 /* Include RTC HAL Extended module */
00628 #include "stm32f3xx_hal_rtc_ex.h"
00629
00630 /* Exported functions --------------------------------------------------------*/
00631 /** @defgroup RTC_Exported_Functions RTC Exported Functions
00632   * @{
00633   */
00634
00635 /** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
00636   * @{
00637   */
00638
00639 /* Initialization and de-initialization functions  ****************************/
00640 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
00641 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
00642 void              HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
00643 void              HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
00644 /**
00645   * @}
00646   */
00647
00648 /** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
00649   * @{
00650   */
00651
00652 /* RTC Time and Date functions ************************************************/
00653 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00654 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00655 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00656 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00657 /**
00658   * @}
00659   */
00660
00661 /** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
00662   * @{
00663   */
00664 /* RTC Alarm functions ********************************************************/
00665 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00666 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00667 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
00668 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
00669 void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
00670 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00671 void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
00672 /**
00673   * @}
00674   */
00675
00676 /** @defgroup  RTC_Exported_Functions_Group4 Peripheral Control functions
00677   * @{
00678   */
00679 /* Peripheral Control functions ***********************************************/
00680 HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
00681 /**
00682   * @}
00683   */
00684
00685 /** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
00686   * @{
00687   */
00688 /* Peripheral State functions *************************************************/
00689 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
00690 /**
00691   * @}
00692   */
00693
00694 /**
00695   * @}
00696   */
00697
00698 /* Private types -------------------------------------------------------------*/
00699 /* Private variables ---------------------------------------------------------*/
00700 /* Private constants ---------------------------------------------------------*/
00701 /** @defgroup RTC_Private_Constants RTC Private Constants
00702   * @{
00703   */
00704 /* Masks Definition */
00705 #define RTC_TR_RESERVED_MASK    0x007F7F7FU
00706 #define RTC_DR_RESERVED_MASK    0x00FFFF3FU
00707 #define RTC_INIT_MASK           0xFFFFFFFFU
00708 #define RTC_RSF_MASK            0xFFFFFF5FU
00709 #define RTC_FLAGS_MASK          ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
00710                                              RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF       | \
00711                                              RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF      | \
00712                                              RTC_FLAG_INITF | RTC_FLAG_RSF                        | \
00713                                              RTC_FLAG_INITS | RTC_FLAG_SHPF | RTC_FLAG_WUTWF      | \
00714                                              RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF))
00715
00716 #define RTC_TIMEOUT_VALUE  1000
00717
00718 #define RTC_EXTI_LINE_ALARM_EVENT             EXTI_IMR_MR17  /*!< External interrupt line 17 Connected to the RTC Alarm event */
00719 #define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  EXTI_IMR_MR19  /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
00720 #define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       EXTI_IMR_MR20  /*!< External interrupt line 20 Connected to the RTC Wakeup event */
00721 /**
00722   * @}
00723   */
00724 /* Private macros  -----------------------------------------------------------*/
00725 /** @defgroup RTC_Private_Macros RTC Private Macros
00726   * @{
00727   */
00728
00729 /** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
00730   * @{
00731   */
00732
00733 #define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
00734                                         ((FORMAT) == RTC_HOURFORMAT_24))
00735
00736 #define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
00737                                 ((POL) == RTC_OUTPUT_POLARITY_LOW))
00738
00739 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
00740                                   ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
00741 #define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0U) && ((HOUR) <= 12U))
00742 #define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23U)
00743 #define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7FU)
00744 #define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x7FFFU)
00745 #define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59U)
00746 #define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59U)
00747
00748 #define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || \
00749                                   ((PM) == RTC_HOURFORMAT12_PM))
00750
00751 #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
00752                                       ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
00753                                       ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
00754
00755 #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
00756                                            ((OPERATION) == RTC_STOREOPERATION_SET))
00757
00758 #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
00759
00760 #define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99U)
00761
00762 #define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1U) && ((MONTH) <= 12U))
00763
00764 #define IS_RTC_DATE(DATE)              (((DATE) >= 1U) && ((DATE) <= 31U))
00765
00766 #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
00767                                  ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
00768                                  ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
00769                                  ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
00770                                  ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
00771                                  ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
00772                                  ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
00773
00774 #define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
00775
00776 #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
00777                                                     ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
00778                                                     ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
00779                                                     ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
00780                                                     ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
00781                                                     ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
00782                                                     ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
00783
00784 #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
00785                                             ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
00786
00787 #define IS_RTC_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
00788
00789 #define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
00790
00791 #define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU)
00792
00793 #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
00794                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
00795                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
00796                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
00797                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
00798                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
00799                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
00800                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
00801                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
00802                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
00803                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
00804                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
00805                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
00806                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
00807                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
00808                                               ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
00809 /**
00810   * @}
00811   */
00812
00813 /**
00814   * @}
00815   */
00816
00817 /* Private functions -------------------------------------------------------------*/
00818 /** @defgroup RTC_Private_Functions RTC Private Functions
00819   * @{
00820   */
00821 HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
00822 uint8_t            RTC_ByteToBcd2(uint8_t Value);
00823 uint8_t            RTC_Bcd2ToByte(uint8_t Value);
00824 /**
00825   * @}
00826   */
00827
00828 /**
00829   * @}
00830   */
00831
00832 /**
00833   * @}
00834   */
00835
00836 #ifdef __cplusplus
00837 }
00838 #endif
00839
00840 #endif /* __STM32F3xx_HAL_RTC_H */
00841
00842 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_rtc_ex.c Source File

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stm32f3xx_hal_rtc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_rtc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended RTC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Real Time Clock (RTC) Extended peripheral:
00008   *           + RTC Time Stamp functions
00009   *           + RTC Tamper functions
00010   *           + RTC Wake-up functions
00011   *           + Extended Control functions
00012   *           + Extended RTC features functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                   ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019     (+) Enable the RTC domain access.
00020     (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00021         format using the HAL_RTC_Init() function.
00022
00023   *** RTC Wakeup configuration ***
00024   ================================
00025   [..]
00026     (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
00027         function. You can also configure the RTC Wakeup timer with interrupt mode
00028         using the HAL_RTCEx_SetWakeUpTimer_IT() function.
00029     (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
00030         function.
00031
00032   *** TimeStamp configuration ***
00033   ===============================
00034   [..]
00035         (+) Configure the RTC_AF trigger and enable the RTC TimeStamp using the
00036         HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with
00037         interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function.
00038     (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
00039         function.
00040     (+) The TIMESTAMP alternate function is mapped to RTC_AF1 (PC13U).
00041
00042   *** Tamper configuration ***
00043   ============================
00044   [..]
00045         (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
00046         or Level according to the Tamper filter (if equal to 0 Edge else Level)
00047         value, sampling frequency, precharge or discharge and Pull-UP using the
00048         HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt
00049         mode using HAL_RTCEx_SetTamper_IT() function.
00050     (+) The TAMPER1 alternate function is mapped to RTC_AF1 (PC13U).
00051
00052   *** Backup Data Registers configuration ***
00053   ===========================================
00054   [..]
00055     (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
00056         function.
00057     (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
00058         function.
00059
00060    @endverbatim
00061   ******************************************************************************
00062   * @attention
00063   *
00064   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00065   *
00066   * Redistribution and use in source and binary forms, with or without modification,
00067   * are permitted provided that the following conditions are met:
00068   *   1. Redistributions of source code must retain the above copyright notice,
00069   *      this list of conditions and the following disclaimer.
00070   *   2. Redistributions in binary form must reproduce the above copyright notice,
00071   *      this list of conditions and the following disclaimer in the documentation
00072   *      and/or other materials provided with the distribution.
00073   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00074   *      may be used to endorse or promote products derived from this software
00075   *      without specific prior written permission.
00076   *
00077   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00078   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00079   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00080   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00081   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00082   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00083   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00084   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00085   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00086   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00087   *
00088   ******************************************************************************
00089   */
00090
00091 /* Includes ------------------------------------------------------------------*/
00092 #include "stm32f3xx_hal.h"
00093
00094 /** @addtogroup STM32F3xx_HAL_Driver
00095   * @{
00096   */
00097
00098
00099
00100 /** @addtogroup RTCEx
00101   * @brief RTC Extended HAL module driver
00102   * @{
00103   */
00104
00105 #ifdef HAL_RTC_MODULE_ENABLED
00106
00107 /* Private typedef -----------------------------------------------------------*/
00108 /* Private define ------------------------------------------------------------*/
00109 /* Private macro -------------------------------------------------------------*/
00110 /* Private variables ---------------------------------------------------------*/
00111 /* Private function prototypes -----------------------------------------------*/
00112 /* Exported functions ---------------------------------------------------------*/
00113
00114 /** @addtogroup RTCEx_Exported_Functions
00115   * @{
00116   */
00117
00118
00119 /** @addtogroup RTCEx_Exported_Functions_Group1
00120  *  @brief   RTC TimeStamp and Tamper functions
00121  *
00122 @verbatim
00123  ===============================================================================
00124                  ##### RTC TimeStamp and Tamper functions #####
00125  ===============================================================================
00126
00127  [..] This section provides functions allowing to configure TimeStamp feature
00128
00129 @endverbatim
00130   * @{
00131   */
00132
00133 /**
00134   * @brief  Set TimeStamp.
00135   * @note   This API must be called before enabling the TimeStamp feature.
00136   * @param  hrtc RTC handle
00137   * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is
00138   *         activated.
00139   *          This parameter can be one of the following values:
00140   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00141   *                                        rising edge of the related pin.
00142   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00143   *                                         falling edge of the related pin.
00144   * @param  RTC_TimeStampPin specifies the RTC TimeStamp Pin.
00145   *          This parameter can be one of the following values:
00146   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
00147   * @retval HAL status
00148   */
00149 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00150 {
00151   uint32_t tmpreg = 0U;
00152
00153   /* Check the parameters */
00154   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00155   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00156
00157   /* Process Locked */
00158   __HAL_LOCK(hrtc);
00159
00160   hrtc->State = HAL_RTC_STATE_BUSY;
00161
00162   /* Get the RTC_CR register and clear the bits to be configured */
00163   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00164
00165   tmpreg|= TimeStampEdge;
00166
00167   /* Disable the write protection for RTC registers */
00168   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00169
00170   /* Configure the Time Stamp TSEDGE and Enable bits */
00171   hrtc->Instance->CR = (uint32_t)tmpreg;
00172
00173   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
00174
00175   /* Enable the write protection for RTC registers */
00176   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00177
00178   /* Change RTC state */
00179   hrtc->State = HAL_RTC_STATE_READY;
00180
00181   /* Process Unlocked */
00182   __HAL_UNLOCK(hrtc);
00183
00184   return HAL_OK;
00185 }
00186
00187 /**
00188   * @brief  Set TimeStamp with Interrupt.
00189   * @param  hrtc RTC handle
00190   * @note   This API must be called before enabling the TimeStamp feature.
00191   * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is
00192   *         activated.
00193   *          This parameter can be one of the following values:
00194   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00195   *                                        rising edge of the related pin.
00196   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00197   *                                         falling edge of the related pin.
00198   * @param  RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
00199   *          This parameter can be one of the following values:
00200   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
00201   * @retval HAL status
00202   */
00203 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00204 {
00205   uint32_t tmpreg = 0U;
00206
00207   /* Check the parameters */
00208   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00209   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00210
00211   /* Process Locked */
00212   __HAL_LOCK(hrtc);
00213
00214   hrtc->State = HAL_RTC_STATE_BUSY;
00215
00216   /* Get the RTC_CR register and clear the bits to be configured */
00217   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00218
00219   tmpreg |= TimeStampEdge;
00220
00221   /* Disable the write protection for RTC registers */
00222   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00223
00224   /* Configure the Time Stamp TSEDGE and Enable bits */
00225   hrtc->Instance->CR = (uint32_t)tmpreg;
00226
00227   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
00228
00229   /* Enable IT timestamp */
00230   __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
00231
00232   /* RTC timestamp Interrupt Configuration: EXTI configuration */
00233   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
00234
00235   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
00236
00237   /* Enable the write protection for RTC registers */
00238   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00239
00240   hrtc->State = HAL_RTC_STATE_READY;
00241
00242   /* Process Unlocked */
00243   __HAL_UNLOCK(hrtc);
00244
00245   return HAL_OK;
00246 }
00247
00248 /**
00249   * @brief  Deactivate TimeStamp.
00250   * @param  hrtc RTC handle
00251   * @retval HAL status
00252   */
00253 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
00254 {
00255   uint32_t tmpreg = 0U;
00256
00257   /* Process Locked */
00258   __HAL_LOCK(hrtc);
00259
00260   hrtc->State = HAL_RTC_STATE_BUSY;
00261
00262   /* Disable the write protection for RTC registers */
00263   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00264
00265   /* In case of interrupt mode is used, the interrupt source must disabled */
00266   __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
00267
00268   /* Get the RTC_CR register and clear the bits to be configured */
00269   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00270
00271   /* Configure the Time Stamp TSEDGE and Enable bits */
00272   hrtc->Instance->CR = (uint32_t)tmpreg;
00273
00274   /* Enable the write protection for RTC registers */
00275   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00276
00277   hrtc->State = HAL_RTC_STATE_READY;
00278
00279   /* Process Unlocked */
00280   __HAL_UNLOCK(hrtc);
00281
00282   return HAL_OK;
00283 }
00284
00285 /**
00286   * @brief  Get the RTC TimeStamp value.
00287   * @param  hrtc RTC handle
00288   * @param  sTimeStamp Pointer to Time structure
00289   * @param  sTimeStampDate Pointer to Date structure
00290   * @param  Format specifies the format of the entered parameters.
00291   *          This parameter can be one of the following values:
00292   *             @arg RTC_FORMAT_BIN: Binary data format
00293   *             @arg RTC_FORMAT_BCD: BCD data format
00294   * @retval HAL status
00295   */
00296 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
00297 {
00298   uint32_t tmptime = 0U, tmpdate = 0U;
00299
00300   /* Check the parameters */
00301   assert_param(IS_RTC_FORMAT(Format));
00302
00303   /* Get the TimeStamp time and date registers values */
00304   tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
00305   tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
00306
00307   /* Fill the Time structure fields with the read parameters */
00308   sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
00309   sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
00310   sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
00311   sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U);
00312   sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
00313
00314   /* Fill the Date structure fields with the read parameters */
00315   sTimeStampDate->Year = 0U;
00316   sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
00317   sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
00318   sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);
00319
00320   /* Check the input parameters format */
00321   if(Format == RTC_FORMAT_BIN)
00322   {
00323     /* Convert the TimeStamp structure parameters to Binary format */
00324     sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
00325     sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
00326     sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
00327
00328     /* Convert the DateTimeStamp structure parameters to Binary format */
00329     sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
00330     sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
00331     sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
00332   }
00333
00334   /* Clear the TIMESTAMP Flag */
00335   __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
00336
00337   return HAL_OK;
00338 }
00339
00340 /**
00341   * @brief  Set Tamper
00342   * @note   By calling this API we disable the tamper interrupt for all tampers.
00343   * @param  hrtc RTC handle
00344   * @param  sTamper Pointer to Tamper Structure.
00345   * @retval HAL status
00346   */
00347 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
00348 {
00349   uint32_t tmpreg = 0U;
00350
00351   /* Check the parameters */
00352   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
00353   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00354   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
00355   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
00356   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
00357   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
00358   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
00359
00360   /* Process Locked */
00361   __HAL_LOCK(hrtc);
00362
00363   hrtc->State = HAL_RTC_STATE_BUSY;
00364
00365   if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
00366   {
00367     sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
00368   }
00369
00370   tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\
00371             (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
00372             (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
00373
00374   hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\
00375                                        (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
00376                                        (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPIE);
00377
00378   hrtc->Instance->TAFCR |= tmpreg;
00379
00380   hrtc->State = HAL_RTC_STATE_READY;
00381
00382   /* Process Unlocked */
00383   __HAL_UNLOCK(hrtc);
00384
00385   return HAL_OK;
00386 }
00387
00388 /**
00389   * @brief  Set Tamper with interrupt.
00390   * @note   By calling this API we force the tamper interrupt for all tampers.
00391   * @param  hrtc RTC handle
00392   * @param  sTamper Pointer to RTC Tamper.
00393   * @retval HAL status
00394   */
00395 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
00396 {
00397   uint32_t tmpreg = 0U;
00398
00399   /* Check the parameters */
00400   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
00401   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00402   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
00403   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
00404   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
00405   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
00406   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
00407
00408   /* Process Locked */
00409   __HAL_LOCK(hrtc);
00410
00411   hrtc->State = HAL_RTC_STATE_BUSY;
00412
00413   /* Configure the tamper trigger */
00414   if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
00415   {
00416     sTamper->Trigger = (uint32_t) (sTamper->Tamper<<1U);
00417   }
00418
00419   tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\
00420             (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
00421             (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
00422
00423   hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\
00424                                        (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
00425                                        (uint32_t)RTC_TAFCR_TAMPPUDIS);
00426
00427   hrtc->Instance->TAFCR |= tmpreg;
00428
00429   /* Configure the Tamper Interrupt in the RTC_TAFCR */
00430   hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
00431
00432   /* RTC Tamper Interrupt Configuration: EXTI configuration */
00433   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
00434
00435   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
00436
00437   hrtc->State = HAL_RTC_STATE_READY;
00438
00439   /* Process Unlocked */
00440   __HAL_UNLOCK(hrtc);
00441
00442   return HAL_OK;
00443 }
00444
00445 /**
00446   * @brief  Deactivate Tamper.
00447   * @param  hrtc RTC handle
00448   * @param  Tamper Selected tamper pin.
00449   *          This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3 (*)
00450   * @note   (*) RTC_TAMPER_3 not present on all the devices
00451   * @retval HAL status
00452   */
00453 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
00454 {
00455   assert_param(IS_RTC_TAMPER(Tamper));
00456
00457   /* Process Locked */
00458   __HAL_LOCK(hrtc);
00459
00460   hrtc->State = HAL_RTC_STATE_BUSY;
00461
00462   /* Disable the selected Tamper pin */
00463   hrtc->Instance->TAFCR &= (uint32_t)~Tamper;
00464
00465   hrtc->State = HAL_RTC_STATE_READY;
00466
00467   /* Process Unlocked */
00468   __HAL_UNLOCK(hrtc);
00469
00470   return HAL_OK;
00471 }
00472
00473 /**
00474   * @brief  Handle TimeStamp interrupt request.
00475   * @param  hrtc RTC handle
00476   * @retval None
00477   */
00478 void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
00479 {
00480   /* Get the TimeStamp interrupt source enable status */
00481   if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET)
00482   {
00483     /* Get the pending status of the TIMESTAMP Interrupt */
00484     if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)
00485     {
00486       /* TIMESTAMP callback */
00487       HAL_RTCEx_TimeStampEventCallback(hrtc);
00488
00489       /* Clear the TIMESTAMP interrupt pending bit */
00490       __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
00491     }
00492   }
00493
00494   /* Get the Tamper interrupts source enable status */
00495   if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
00496   {
00497    /* Get the pending status of the Tamper1 Interrupt */
00498     if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)
00499     {
00500       /* Tamper1 callback */
00501       HAL_RTCEx_Tamper1EventCallback(hrtc);
00502
00503       /* Clear the Tamper1 interrupt pending bit */
00504       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
00505     }
00506   }
00507
00508   /* Get the Tamper interrupts source enable status */
00509   if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
00510   {
00511    /* Get the pending status of the Tamper2 Interrupt */
00512     if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)
00513     {
00514       /* Tamper2 callback */
00515       HAL_RTCEx_Tamper2EventCallback(hrtc);
00516
00517       /* Clear the Tamper2 interrupt pending bit */
00518       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
00519     }
00520   }
00521
00522 #if defined(RTC_TAMPER3_SUPPORT)
00523   /* Get the Tamper interrupts source enable status */
00524   if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
00525   {
00526    /* Get the pending status of the Tamper3 Interrupt */
00527     if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)
00528     {
00529       /* Tamper3 callback */
00530       HAL_RTCEx_Tamper3EventCallback(hrtc);
00531
00532       /* Clear the Tamper3 interrupt pending bit */
00533       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
00534     }
00535   }
00536 #endif /* RTC_TAMPER3_SUPPORT */
00537
00538   /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
00539   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
00540
00541   /* Change RTC state */
00542   hrtc->State = HAL_RTC_STATE_READY;
00543 }
00544
00545 /**
00546   * @brief  TimeStamp callback.
00547   * @param  hrtc RTC handle
00548   * @retval None
00549   */
00550 __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
00551 {
00552   /* Prevent unused argument(s) compilation warning */
00553   UNUSED(hrtc);
00554
00555   /* NOTE : This function should not be modified, when the callback is needed,
00556             the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
00557   */
00558 }
00559
00560 /**
00561   * @brief  Tamper 1 callback.
00562   * @param  hrtc RTC handle
00563   * @retval None
00564   */
00565 __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
00566 {
00567   /* Prevent unused argument(s) compilation warning */
00568   UNUSED(hrtc);
00569
00570   /* NOTE : This function should not be modified, when the callback is needed,
00571             the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
00572    */
00573 }
00574
00575 /**
00576   * @brief  Tamper 2 callback.
00577   * @param  hrtc RTC handle
00578   * @retval None
00579   */
00580 __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
00581 {
00582   /* Prevent unused argument(s) compilation warning */
00583   UNUSED(hrtc);
00584
00585   /* NOTE : This function should not be modified, when the callback is needed,
00586             the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
00587    */
00588 }
00589
00590 #if defined(RTC_TAMPER3_SUPPORT)
00591 /**
00592   * @brief  Tamper 3 callback.
00593   * @param  hrtc RTC handle
00594   * @retval None
00595   */
00596 __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
00597 {
00598   /* Prevent unused argument(s) compilation warning */
00599   UNUSED(hrtc);
00600
00601   /* NOTE : This function should not be modified, when the callback is needed,
00602             the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
00603    */
00604 }
00605 #endif /* RTC_TAMPER3_SUPPORT */
00606
00607 /**
00608   * @brief  Handle TimeStamp polling request.
00609   * @param  hrtc RTC handle
00610   * @param  Timeout Timeout duration
00611   * @retval HAL status
00612   */
00613 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00614 {
00615   uint32_t tickstart = HAL_GetTick();
00616
00617   while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
00618   {
00619     if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
00620     {
00621       /* Clear the TIMESTAMP OverRun Flag */
00622       __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
00623
00624       /* Change TIMESTAMP state */
00625       hrtc->State = HAL_RTC_STATE_ERROR;
00626
00627       return HAL_ERROR;
00628     }
00629
00630     if(Timeout != HAL_MAX_DELAY)
00631     {
00632       if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
00633       {
00634         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00635         return HAL_TIMEOUT;
00636       }
00637     }
00638   }
00639
00640   /* Change RTC state */
00641   hrtc->State = HAL_RTC_STATE_READY;
00642
00643   return HAL_OK;
00644 }
00645
00646 /**
00647   * @brief  Handle Tamper 1 Polling.
00648   * @param  hrtc RTC handle
00649   * @param  Timeout Timeout duration
00650   * @retval HAL status
00651   */
00652 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00653 {
00654   uint32_t tickstart = HAL_GetTick();
00655
00656   /* Get the status of the Interrupt */
00657   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP1F)== RESET)
00658   {
00659     if(Timeout != HAL_MAX_DELAY)
00660     {
00661       if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
00662       {
00663         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00664         return HAL_TIMEOUT;
00665       }
00666     }
00667   }
00668
00669   /* Clear the Tamper Flag */
00670   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
00671
00672   /* Change RTC state */
00673   hrtc->State = HAL_RTC_STATE_READY;
00674
00675   return HAL_OK;
00676 }
00677
00678 /**
00679   * @brief  Handle Tamper 2 Polling.
00680   * @param  hrtc RTC handle
00681   * @param  Timeout Timeout duration
00682   * @retval HAL status
00683   */
00684 HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00685 {
00686   uint32_t tickstart = HAL_GetTick();
00687
00688   /* Get the status of the Interrupt */
00689   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP2F) == RESET)
00690   {
00691     if(Timeout != HAL_MAX_DELAY)
00692     {
00693       if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
00694       {
00695         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00696         return HAL_TIMEOUT;
00697       }
00698     }
00699   }
00700
00701   /* Clear the Tamper Flag */
00702   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);
00703
00704   /* Change RTC state */
00705   hrtc->State = HAL_RTC_STATE_READY;
00706
00707   return HAL_OK;
00708 }
00709
00710 #if defined(RTC_TAMPER3_SUPPORT)
00711 /**
00712   * @brief  Handle Tamper 3 Polling.
00713   * @param  hrtc RTC handle
00714   * @param  Timeout Timeout duration
00715   * @retval HAL status
00716   */
00717 HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00718 {
00719   uint32_t tickstart = HAL_GetTick();
00720
00721   /* Get the status of the Interrupt */
00722   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP3F) == RESET)
00723   {
00724     if(Timeout != HAL_MAX_DELAY)
00725     {
00726       if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
00727       {
00728         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00729         return HAL_TIMEOUT;
00730       }
00731     }
00732   }
00733
00734   /* Clear the Tamper Flag */
00735   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F);
00736
00737   /* Change RTC state */
00738   hrtc->State = HAL_RTC_STATE_READY;
00739
00740   return HAL_OK;
00741 }
00742 #endif /* RTC_TAMPER3_SUPPORT */
00743
00744 /**
00745   * @}
00746   */
00747
00748 /** @addtogroup RTCEx_Exported_Functions_Group2
00749   * @brief    RTC Wake-up functions
00750   *
00751 @verbatim
00752  ===============================================================================
00753                         ##### RTC Wake-up functions #####
00754  ===============================================================================
00755
00756  [..] This section provides functions allowing to configure Wake-up feature
00757
00758 @endverbatim
00759   * @{
00760   */
00761
00762 /**
00763   * @brief  Set wake up timer.
00764   * @param  hrtc RTC handle
00765   * @param  WakeUpCounter Wake up counter
00766   * @param  WakeUpClock Wake up clock
00767   * @retval HAL status
00768   */
00769 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
00770 {
00771   uint32_t tickstart = 0U;
00772
00773   /* Check the parameters */
00774   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
00775   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
00776
00777   /* Process Locked */
00778   __HAL_LOCK(hrtc);
00779
00780   hrtc->State = HAL_RTC_STATE_BUSY;
00781
00782   /* Disable the write protection for RTC registers */
00783   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00784
00785   /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
00786   if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET){
00787     tickstart = HAL_GetTick();
00788
00789    /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
00790    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
00791    {
00792     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00793       {
00794        /* Enable the write protection for RTC registers */
00795        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00796
00797        hrtc->State = HAL_RTC_STATE_TIMEOUT;
00798
00799        /* Process Unlocked */
00800        __HAL_UNLOCK(hrtc);
00801
00802        return HAL_TIMEOUT;
00803       }
00804     }
00805   }
00806
00807   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
00808
00809   tickstart = HAL_GetTick();
00810
00811   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
00812   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
00813   {
00814     if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
00815     {
00816       /* Enable the write protection for RTC registers */
00817       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00818
00819       hrtc->State = HAL_RTC_STATE_TIMEOUT;
00820
00821       /* Process Unlocked */
00822       __HAL_UNLOCK(hrtc);
00823
00824       return HAL_TIMEOUT;
00825     }
00826   }
00827
00828   /* Clear the Wakeup Timer clock source bits in CR register */
00829   hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
00830
00831   /* Configure the clock source */
00832   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
00833
00834   /* Configure the Wakeup Timer counter */
00835   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
00836
00837    /* Enable the Wakeup Timer */
00838   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
00839
00840   /* Enable the write protection for RTC registers */
00841   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00842
00843   hrtc->State = HAL_RTC_STATE_READY;
00844
00845   /* Process Unlocked */
00846   __HAL_UNLOCK(hrtc);
00847
00848   return HAL_OK;
00849 }
00850
00851 /**
00852   * @brief  Set wake up timer with interrupt.
00853   * @param  hrtc RTC handle
00854   * @param  WakeUpCounter Wake up counter
00855   * @param  WakeUpClock Wake up clock
00856   * @retval HAL status
00857   */
00858 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
00859 {
00860   uint32_t tickstart = 0U;
00861
00862   /* Check the parameters */
00863   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
00864   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
00865
00866   /* Process Locked */
00867   __HAL_LOCK(hrtc);
00868
00869   hrtc->State = HAL_RTC_STATE_BUSY;
00870
00871   /* Disable the write protection for RTC registers */
00872   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00873
00874   /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
00875   if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET){
00876     tickstart = HAL_GetTick();
00877
00878    /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
00879    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
00880    {
00881     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00882       {
00883        /* Enable the write protection for RTC registers */
00884        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00885
00886        hrtc->State = HAL_RTC_STATE_TIMEOUT;
00887
00888        /* Process Unlocked */
00889        __HAL_UNLOCK(hrtc);
00890
00891        return HAL_TIMEOUT;
00892       }
00893     }
00894   }
00895
00896   /* Disable the Wake-Up timer */
00897   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
00898
00899   /* Clear flag Wake-Up */
00900   __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
00901
00902   tickstart = HAL_GetTick();
00903
00904   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
00905   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
00906   {
00907     if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
00908     {
00909       /* Enable the write protection for RTC registers */
00910       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00911
00912       hrtc->State = HAL_RTC_STATE_TIMEOUT;
00913
00914       /* Process Unlocked */
00915       __HAL_UNLOCK(hrtc);
00916
00917       return HAL_TIMEOUT;
00918     }
00919   }
00920
00921   /* Configure the Wakeup Timer counter */
00922   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
00923
00924   /* Clear the Wakeup Timer clock source bits in CR register */
00925   hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
00926
00927   /* Configure the clock source */
00928   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
00929
00930   /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
00931   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
00932
00933   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
00934
00935   /* Configure the Interrupt in the RTC_CR register */
00936   __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
00937
00938   /* Enable the Wakeup Timer */
00939   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
00940
00941   /* Enable the write protection for RTC registers */
00942   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00943
00944   hrtc->State = HAL_RTC_STATE_READY;
00945
00946   /* Process Unlocked */
00947   __HAL_UNLOCK(hrtc);
00948
00949   return HAL_OK;
00950 }
00951
00952 /**
00953   * @brief  Deactivate wake up timer counter.
00954   * @param  hrtc RTC handle
00955   * @retval HAL status
00956   */
00957 uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
00958 {
00959   uint32_t tickstart = 0U;
00960
00961   /* Process Locked */
00962   __HAL_LOCK(hrtc);
00963
00964   hrtc->State = HAL_RTC_STATE_BUSY;
00965
00966   /* Disable the write protection for RTC registers */
00967   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00968
00969   /* Disable the Wakeup Timer */
00970   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
00971
00972   /* In case of interrupt mode is used, the interrupt source must disabled */
00973   __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
00974
00975   tickstart = HAL_GetTick();
00976   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
00977   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
00978   {
00979     if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
00980     {
00981       /* Enable the write protection for RTC registers */
00982       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00983
00984       hrtc->State = HAL_RTC_STATE_TIMEOUT;
00985
00986       /* Process Unlocked */
00987       __HAL_UNLOCK(hrtc);
00988
00989       return HAL_TIMEOUT;
00990     }
00991   }
00992
00993   /* Enable the write protection for RTC registers */
00994   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00995
00996   hrtc->State = HAL_RTC_STATE_READY;
00997
00998   /* Process Unlocked */
00999   __HAL_UNLOCK(hrtc);
01000
01001   return HAL_OK;
01002 }
01003
01004 /**
01005   * @brief  Get wake up timer counter.
01006   * @param  hrtc RTC handle
01007   * @retval Counter value
01008   */
01009 uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
01010 {
01011   /* Get the counter value */
01012   return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
01013 }
01014
01015 /**
01016   * @brief  Handle Wake Up Timer interrupt request.
01017   * @param  hrtc RTC handle
01018   * @retval None
01019   */
01020 void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
01021 {
01022   /* Get the pending status of the WAKEUPTIMER Interrupt */
01023   if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET)
01024   {
01025     /* WAKEUPTIMER callback */
01026     HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
01027
01028     /* Clear the WAKEUPTIMER interrupt pending bit */
01029     __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
01030   }
01031
01032   /* Clear the EXTI's line Flag for RTC WakeUpTimer */
01033   __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
01034
01035   /* Change RTC state */
01036   hrtc->State = HAL_RTC_STATE_READY;
01037 }
01038
01039 /**
01040   * @brief  Wake Up Timer callback.
01041   * @param  hrtc RTC handle
01042   * @retval None
01043   */
01044 __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
01045 {
01046   /* Prevent unused argument(s) compilation warning */
01047   UNUSED(hrtc);
01048
01049   /* NOTE : This function should not be modified, when the callback is needed,
01050             the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
01051    */
01052 }
01053
01054 /**
01055  * @brief  Handle Wake Up Timer Polling.
01056   * @param  hrtc RTC handle
01057   * @param  Timeout Timeout duration
01058   * @retval HAL status
01059   */
01060 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01061 {
01062   uint32_t tickstart = HAL_GetTick();
01063
01064   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
01065   {
01066     if(Timeout != HAL_MAX_DELAY)
01067     {
01068       if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
01069       {
01070         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01071
01072         return HAL_TIMEOUT;
01073       }
01074     }
01075   }
01076
01077   /* Clear the WAKEUPTIMER Flag */
01078   __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
01079
01080   /* Change RTC state */
01081   hrtc->State = HAL_RTC_STATE_READY;
01082
01083   return HAL_OK;
01084 }
01085
01086 /**
01087   * @}
01088   */
01089
01090
01091 /** @addtogroup RTCEx_Exported_Functions_Group3
01092   * @brief    Extended Peripheral Control functions
01093   *
01094 @verbatim
01095  ===============================================================================
01096               ##### Extended Peripheral Control functions #####
01097  ===============================================================================
01098     [..]
01099     This subsection provides functions allowing to
01100       (+) Write a data in a specified RTC Backup data register
01101       (+) Read a data in a specified RTC Backup data register
01102       (+) Set the Coarse calibration parameters.
01103       (+) Deactivate the Coarse calibration parameters
01104       (+) Set the Smooth calibration parameters.
01105       (+) Configure the Synchronization Shift Control Settings.
01106       (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01107       (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01108       (+) Enable the RTC reference clock detection.
01109       (+) Disable the RTC reference clock detection.
01110       (+) Enable the Bypass Shadow feature.
01111       (+) Disable the Bypass Shadow feature.
01112
01113 @endverbatim
01114   * @{
01115   */
01116
01117 /**
01118   * @brief  Write a data in a specified RTC Backup data register.
01119   * @param  hrtc RTC handle
01120   * @param  BackupRegister RTC Backup data Register number.
01121   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
01122   *                                 specify the register.
01123   * @param  Data Data to be written in the specified RTC Backup data register.
01124   * @retval None
01125   */
01126 void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
01127 {
01128   uint32_t tmp = 0U;
01129
01130   /* Check the parameters */
01131   assert_param(IS_RTC_BKP(BackupRegister));
01132
01133   tmp = (uint32_t)&(hrtc->Instance->BKP0R);
01134   tmp += (BackupRegister * 4U);
01135
01136   /* Write the specified register */
01137   *(__IO uint32_t *)tmp = (uint32_t)Data;
01138 }
01139
01140 /**
01141   * @brief  Reads data from the specified RTC Backup data Register.
01142   * @param  hrtc RTC handle
01143   * @param  BackupRegister RTC Backup data Register number.
01144   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
01145   *                                 specify the register.
01146   * @retval Read value
01147   */
01148 uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
01149 {
01150   uint32_t tmp = 0U;
01151
01152   /* Check the parameters */
01153   assert_param(IS_RTC_BKP(BackupRegister));
01154
01155   tmp = (uint32_t)&(hrtc->Instance->BKP0R);
01156   tmp += (BackupRegister * 4U);
01157
01158   /* Read the specified register */
01159   return (*(__IO uint32_t *)tmp);
01160 }
01161
01162 /**
01163   * @brief  Set the Smooth calibration parameters.
01164   * @param  hrtc RTC handle
01165   * @param  SmoothCalibPeriod Select the Smooth Calibration Period.
01166   *          This parameter can be can be one of the following values :
01167   *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
01168   *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
01169   *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
01170   * @param  SmoothCalibPlusPulses Select to Set or reset the CALP bit.
01171   *          This parameter can be one of the following values:
01172   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
01173   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
01174   * @param  SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits.
01175   *          This parameter can be one any value from 0 to 0x000001FF.
01176   * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses
01177   *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
01178   *         SmoothCalibMinusPulsesValue mut be equal to 0.
01179   * @retval HAL status
01180   */
01181 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
01182 {
01183   uint32_t tickstart = 0U;
01184
01185   /* Check the parameters */
01186   assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
01187   assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
01188   assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
01189
01190   /* Process Locked */
01191   __HAL_LOCK(hrtc);
01192
01193   hrtc->State = HAL_RTC_STATE_BUSY;
01194
01195   /* Disable the write protection for RTC registers */
01196   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01197
01198   /* check if a calibration is pending*/
01199   if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
01200   {
01201     tickstart = HAL_GetTick();
01202
01203     /* check if a calibration is pending*/
01204     while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
01205     {
01206       if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
01207       {
01208         /* Enable the write protection for RTC registers */
01209         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01210
01211         /* Change RTC state */
01212         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01213
01214         /* Process Unlocked */
01215         __HAL_UNLOCK(hrtc);
01216
01217         return HAL_TIMEOUT;
01218       }
01219     }
01220   }
01221
01222   /* Configure the Smooth calibration settings */
01223   hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
01224
01225   /* Enable the write protection for RTC registers */
01226   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01227
01228   /* Change RTC state */
01229   hrtc->State = HAL_RTC_STATE_READY;
01230
01231   /* Process Unlocked */
01232   __HAL_UNLOCK(hrtc);
01233
01234   return HAL_OK;
01235 }
01236
01237 /**
01238   * @brief  Configure the Synchronization Shift Control Settings.
01239   * @note   When REFCKON is set, firmware must not write to Shift control register.
01240   * @param  hrtc RTC handle
01241   * @param  ShiftAdd1S: Select to add or not 1 second to the time calendar.
01242   *          This parameter can be one of the following values :
01243   *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
01244   *             @arg RTC_SHIFTADD1S_RESET: No effect.
01245   * @param  ShiftSubFS Select the number of Second Fractions to substitute.
01246   *          This parameter can be one any value from 0 to 0x7FFF.
01247   * @retval HAL status
01248   */
01249 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
01250 {
01251   uint32_t tickstart = 0U;
01252
01253   /* Check the parameters */
01254   assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
01255   assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
01256
01257   /* Process Locked */
01258   __HAL_LOCK(hrtc);
01259
01260   hrtc->State = HAL_RTC_STATE_BUSY;
01261
01262   /* Disable the write protection for RTC registers */
01263   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01264
01265     tickstart = HAL_GetTick();
01266
01267     /* Wait until the shift is completed*/
01268     while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
01269     {
01270       if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
01271       {
01272         /* Enable the write protection for RTC registers */
01273         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01274
01275         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01276
01277         /* Process Unlocked */
01278         __HAL_UNLOCK(hrtc);
01279
01280         return HAL_TIMEOUT;
01281       }
01282     }
01283
01284     /* Check if the reference clock detection is disabled */
01285     if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
01286     {
01287       /* Configure the Shift settings */
01288       hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
01289
01290       /* If  RTC_CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
01291       if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
01292       {
01293         if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
01294         {
01295           /* Enable the write protection for RTC registers */
01296           __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01297
01298           hrtc->State = HAL_RTC_STATE_ERROR;
01299
01300           /* Process Unlocked */
01301           __HAL_UNLOCK(hrtc);
01302
01303           return HAL_ERROR;
01304         }
01305       }
01306     }
01307     else
01308     {
01309       /* Enable the write protection for RTC registers */
01310       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01311
01312       /* Change RTC state */
01313       hrtc->State = HAL_RTC_STATE_ERROR;
01314
01315       /* Process Unlocked */
01316       __HAL_UNLOCK(hrtc);
01317
01318       return HAL_ERROR;
01319     }
01320
01321   /* Enable the write protection for RTC registers */
01322   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01323
01324   /* Change RTC state */
01325   hrtc->State = HAL_RTC_STATE_READY;
01326
01327   /* Process Unlocked */
01328   __HAL_UNLOCK(hrtc);
01329
01330   return HAL_OK;
01331 }
01332
01333 /**
01334   * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01335   * @param  hrtc RTC handle
01336   * @param  CalibOutput Select the Calibration output Selection .
01337   *          This parameter can be one of the following values:
01338   *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
01339   *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
01340   * @retval HAL status
01341   */
01342 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
01343 {
01344   /* Check the parameters */
01345   assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
01346
01347   /* Process Locked */
01348   __HAL_LOCK(hrtc);
01349
01350   hrtc->State = HAL_RTC_STATE_BUSY;
01351
01352   /* Disable the write protection for RTC registers */
01353   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01354
01355   /* Clear flags before config */
01356   hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
01357
01358   /* Configure the RTC_CR register */
01359   hrtc->Instance->CR |= (uint32_t)CalibOutput;
01360
01361   __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
01362
01363   /* Enable the write protection for RTC registers */
01364   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01365
01366   /* Change RTC state */
01367   hrtc->State = HAL_RTC_STATE_READY;
01368
01369   /* Process Unlocked */
01370   __HAL_UNLOCK(hrtc);
01371
01372   return HAL_OK;
01373 }
01374
01375 /**
01376   * @brief  Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01377   * @param  hrtc RTC handle
01378   * @retval HAL status
01379   */
01380 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
01381 {
01382   /* Process Locked */
01383   __HAL_LOCK(hrtc);
01384
01385   hrtc->State = HAL_RTC_STATE_BUSY;
01386
01387   /* Disable the write protection for RTC registers */
01388   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01389
01390   __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
01391
01392   /* Enable the write protection for RTC registers */
01393   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01394
01395   /* Change RTC state */
01396   hrtc->State = HAL_RTC_STATE_READY;
01397
01398   /* Process Unlocked */
01399   __HAL_UNLOCK(hrtc);
01400
01401   return HAL_OK;
01402 }
01403
01404 /**
01405   * @brief  Enable the RTC reference clock detection.
01406   * @param  hrtc RTC handle
01407   * @retval HAL status
01408   */
01409 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
01410 {
01411   /* Process Locked */
01412   __HAL_LOCK(hrtc);
01413
01414   hrtc->State = HAL_RTC_STATE_BUSY;
01415
01416   /* Disable the write protection for RTC registers */
01417   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01418
01419   /* Set Initialization mode */
01420   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01421   {
01422     /* Enable the write protection for RTC registers */
01423     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01424
01425     /* Set RTC state*/
01426     hrtc->State = HAL_RTC_STATE_ERROR;
01427
01428     /* Process Unlocked */
01429     __HAL_UNLOCK(hrtc);
01430
01431     return HAL_ERROR;
01432   }
01433   else
01434   {
01435     __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
01436
01437     /* Exit Initialization mode */
01438     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
01439   }
01440
01441   /* Enable the write protection for RTC registers */
01442   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01443
01444    /* Change RTC state */
01445   hrtc->State = HAL_RTC_STATE_READY;
01446
01447   /* Process Unlocked */
01448   __HAL_UNLOCK(hrtc);
01449
01450   return HAL_OK;
01451 }
01452
01453 /**
01454   * @brief  Disable the RTC reference clock detection.
01455   * @param  hrtc RTC handle
01456   * @retval HAL status
01457   */
01458 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
01459 {
01460   /* Process Locked */
01461   __HAL_LOCK(hrtc);
01462
01463   hrtc->State = HAL_RTC_STATE_BUSY;
01464
01465   /* Disable the write protection for RTC registers */
01466   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01467
01468   /* Set Initialization mode */
01469   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01470   {
01471     /* Enable the write protection for RTC registers */
01472     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01473
01474     /* Set RTC state*/
01475     hrtc->State = HAL_RTC_STATE_ERROR;
01476
01477     /* Process Unlocked */
01478     __HAL_UNLOCK(hrtc);
01479
01480     return HAL_ERROR;
01481   }
01482   else
01483   {
01484     __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
01485
01486     /* Exit Initialization mode */
01487     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
01488   }
01489
01490   /* Enable the write protection for RTC registers */
01491   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01492
01493   /* Change RTC state */
01494   hrtc->State = HAL_RTC_STATE_READY;
01495
01496   /* Process Unlocked */
01497   __HAL_UNLOCK(hrtc);
01498
01499   return HAL_OK;
01500 }
01501
01502 /**
01503   * @brief  Enable the Bypass Shadow feature.
01504   * @param  hrtc RTC handle
01505   * @note   When the Bypass Shadow is enabled the calendar value are taken
01506   *         directly from the Calendar counter.
01507   * @retval HAL status
01508   */
01509 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
01510 {
01511   /* Process Locked */
01512   __HAL_LOCK(hrtc);
01513
01514   hrtc->State = HAL_RTC_STATE_BUSY;
01515
01516   /* Disable the write protection for RTC registers */
01517   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01518
01519   /* Set the BYPSHAD bit */
01520   hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
01521
01522   /* Enable the write protection for RTC registers */
01523   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01524
01525   /* Change RTC state */
01526   hrtc->State = HAL_RTC_STATE_READY;
01527
01528   /* Process Unlocked */
01529   __HAL_UNLOCK(hrtc);
01530
01531   return HAL_OK;
01532 }
01533
01534 /**
01535   * @brief  Disable the Bypass Shadow feature.
01536   * @param  hrtc RTC handle
01537   * @note   When the Bypass Shadow is enabled the calendar value are taken
01538   *         directly from the Calendar counter.
01539   * @retval HAL status
01540   */
01541 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
01542 {
01543   /* Process Locked */
01544   __HAL_LOCK(hrtc);
01545
01546   hrtc->State = HAL_RTC_STATE_BUSY;
01547
01548   /* Disable the write protection for RTC registers */
01549   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01550
01551   /* Reset the BYPSHAD bit */
01552   hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
01553
01554   /* Enable the write protection for RTC registers */
01555   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01556
01557   /* Change RTC state */
01558   hrtc->State = HAL_RTC_STATE_READY;
01559
01560   /* Process Unlocked */
01561   __HAL_UNLOCK(hrtc);
01562
01563   return HAL_OK;
01564 }
01565
01566 /**
01567   * @}
01568   */
01569
01570 /** @addtogroup RTCEx_Exported_Functions_Group4 Extended features functions
01571   * @brief    Extended features functions
01572   *
01573 @verbatim
01574  ===============================================================================
01575                  ##### Extended features functions #####
01576  ===============================================================================
01577     [..]  This section provides functions allowing to:
01578       (+) RTC Alram B callback
01579       (+) RTC Poll for Alarm B request
01580
01581 @endverbatim
01582   * @{
01583   */
01584
01585 /**
01586   * @brief  Alarm B callback.
01587   * @param  hrtc RTC handle
01588   * @retval None
01589   */
01590 __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
01591 {
01592   /* Prevent unused argument(s) compilation warning */
01593   UNUSED(hrtc);
01594
01595   /* NOTE : This function should not be modified, when the callback is needed,
01596             the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
01597    */
01598 }
01599
01600 /**
01601   * @brief  This function handles AlarmB Polling request.
01602   * @param  hrtc RTC handle
01603   * @param  Timeout Timeout duration
01604   * @retval HAL status
01605   */
01606 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01607 {
01608   uint32_t tickstart = HAL_GetTick();
01609
01610   while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
01611   {
01612     if(Timeout != HAL_MAX_DELAY)
01613     {
01614       if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
01615       {
01616         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01617         return HAL_TIMEOUT;
01618       }
01619     }
01620   }
01621
01622   /* Clear the Alarm Flag */
01623   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01624
01625   /* Change RTC state */
01626   hrtc->State = HAL_RTC_STATE_READY;
01627
01628   return HAL_OK;
01629 }
01630
01631 /**
01632   * @}
01633   */
01634
01635 /**
01636   * @}
01637   */
01638
01639 #endif /* HAL_RTC_MODULE_ENABLED */
01640 /**
01641   * @}
01642   */
01643
01644 /**
01645   * @}
01646   */
01647
01648 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_rtc_ex.h Source File

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stm32f3xx_hal_rtc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_rtc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RTC HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_RTC_EX_H
00038 #define __STM32F3xx_HAL_RTC_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @defgroup RTCEx RTCEx
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056
00057 /** @defgroup RTCEx_Exported_Types RTC Extended Exported Types
00058   * @{
00059   */
00060
00061 /**
00062   * @brief  RTC Tamper structure definition
00063   */
00064 typedef struct
00065 {
00066   uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
00067                                              This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
00068
00069   uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
00070                                              This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
00071
00072   uint32_t Filter;                      /*!< Specifies the RTC Filter Tamper.
00073                                              This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
00074
00075   uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
00076                                              This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
00077
00078   uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
00079                                              This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
00080
00081   uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
00082                                              This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
00083
00084   uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
00085                                              This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
00086 }RTC_TamperTypeDef;
00087 /**
00088   * @}
00089   */
00090
00091 /* Exported constants --------------------------------------------------------*/
00092 /** @defgroup RTCEx_Exported_Constants RTC Extended Exported Constants
00093   * @{
00094   */
00095
00096 /** @defgroup RTCEx_Output_selection_Definitions RTC Extended Output Selection Definition
00097   * @{
00098   */
00099 #define RTC_OUTPUT_DISABLE             0x00000000U
00100 #define RTC_OUTPUT_ALARMA              RTC_CR_OSEL_0
00101 #define RTC_OUTPUT_ALARMB              RTC_CR_OSEL_1
00102 #define RTC_OUTPUT_WAKEUP              RTC_CR_OSEL
00103 /**
00104   * @}
00105   */
00106
00107 /** @defgroup RTCEx_Backup_Registers_Definitions RTC Extended Backup Registers Definition
00108   * @{
00109   */
00110 #if RTC_BKP_NUMBER > 0U
00111 #define RTC_BKP_DR0  0x00000000U
00112 #define RTC_BKP_DR1  0x00000001U
00113 #define RTC_BKP_DR2  0x00000002U
00114 #define RTC_BKP_DR3  0x00000003U
00115 #define RTC_BKP_DR4  0x00000004U
00116 #endif /* RTC_BKP_NUMBER > 0U */
00117
00118 #if RTC_BKP_NUMBER > 5U
00119 #define RTC_BKP_DR5  0x00000005U
00120 #define RTC_BKP_DR6  0x00000006U
00121 #define RTC_BKP_DR7  0x00000007U
00122 #define RTC_BKP_DR8  0x00000008U
00123 #define RTC_BKP_DR9  0x00000009U
00124 #define RTC_BKP_DR10 0x0000000AU
00125 #define RTC_BKP_DR11 0x0000000BU
00126 #define RTC_BKP_DR12 0x0000000CU
00127 #define RTC_BKP_DR13 0x0000000DU
00128 #define RTC_BKP_DR14 0x0000000EU
00129 #define RTC_BKP_DR15 0x0000000FU
00130 #endif /* RTC_BKP_NUMBER > 5U */
00131
00132 #if RTC_BKP_NUMBER > 16U
00133 #define RTC_BKP_DR16 0x00000010U
00134 #define RTC_BKP_DR17 0x00000011U
00135 #define RTC_BKP_DR18 0x00000012U
00136 #define RTC_BKP_DR19 0x00000013U
00137 #endif /* RTC_BKP_NUMBER > 16U */
00138
00139 #if RTC_BKP_NUMBER > 20U
00140 #define RTC_BKP_DR20 0x00000014U
00141 #define RTC_BKP_DR21 0x00000015U
00142 #define RTC_BKP_DR22 0x00000016U
00143 #define RTC_BKP_DR23 0x00000017U
00144 #define RTC_BKP_DR24 0x00000018U
00145 #define RTC_BKP_DR25 0x00000019U
00146 #define RTC_BKP_DR26 0x0000001AU
00147 #define RTC_BKP_DR27 0x0000001BU
00148 #define RTC_BKP_DR28 0x0000001CU
00149 #define RTC_BKP_DR29 0x0000001DU
00150 #define RTC_BKP_DR30 0x0000001EU
00151 #define RTC_BKP_DR31 0x0000001FU
00152 #endif /* RTC_BKP_NUMBER > 20U */
00153 /**
00154   * @}
00155   */
00156
00157 /** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC Extended Time Stamp Edges definition
00158   * @{
00159   */
00160 #define RTC_TIMESTAMPEDGE_RISING          0x00000000U
00161 #define RTC_TIMESTAMPEDGE_FALLING         RTC_CR_TSEDGE
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup RTCEx_TimeStamp_Pin_Selections RTC Extended TimeStamp Pin Selection
00167   * @{
00168   */
00169 #define RTC_TIMESTAMPPIN_DEFAULT              0x00000000U
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup RTCEx_Tamper_Pins_Definitions RTC Extended Tamper Pins Definition
00175   * @{
00176   */
00177 #define RTC_TAMPER_1                    RTC_TAFCR_TAMP1E
00178 #define RTC_TAMPER_2                    RTC_TAFCR_TAMP2E
00179 #if defined(RTC_TAMPER3_SUPPORT)
00180 #define RTC_TAMPER_3                    RTC_TAFCR_TAMP3E
00181 #endif /* RTC_TAMPER3_SUPPORT */
00182 /**
00183   * @}
00184   */
00185
00186
00187 /** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Extended Tamper Trigger Definition
00188   * @{
00189   */
00190 #define RTC_TAMPERTRIGGER_RISINGEDGE       0x00000000U
00191 #define RTC_TAMPERTRIGGER_FALLINGEDGE      RTC_TAFCR_TAMP1TRG
00192 #define RTC_TAMPERTRIGGER_LOWLEVEL         RTC_TAMPERTRIGGER_RISINGEDGE
00193 #define RTC_TAMPERTRIGGER_HIGHLEVEL        RTC_TAMPERTRIGGER_FALLINGEDGE
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup RTCEx_Tamper_Filter_Definitions RTC Extended Tamper Filter Definition
00199   * @{
00200   */
00201 #define RTC_TAMPERFILTER_DISABLE   0x00000000U             /*!< Tamper filter is disabled */
00202
00203 #define RTC_TAMPERFILTER_2SAMPLE   RTC_TAFCR_TAMPFLT_0     /*!< Tamper is activated after 2
00204                                                                 consecutive samples at the active level */
00205 #define RTC_TAMPERFILTER_4SAMPLE   RTC_TAFCR_TAMPFLT_1     /*!< Tamper is activated after 4
00206                                                                 consecutive samples at the active level */
00207 #define RTC_TAMPERFILTER_8SAMPLE   RTC_TAFCR_TAMPFLT       /*!< Tamper is activated after 8
00208                                                                 consecutive samples at the active level. */
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Extended Tamper Sampling Frequencies Definition
00214   * @{
00215   */
00216 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  0x00000000U           /*!< Each of the tamper inputs are sampled
00217                                                                              with a frequency =  RTCCLK / 32768U */
00218 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  RTC_TAFCR_TAMPFREQ_0  /*!< Each of the tamper inputs are sampled
00219                                                                              with a frequency =  RTCCLK / 16384U */
00220 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   RTC_TAFCR_TAMPFREQ_1  /*!< Each of the tamper inputs are sampled
00221                                                                              with a frequency =  RTCCLK / 8192  */
00222 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1)  /*!< Each of the tamper inputs are sampled
00223                                                                              with a frequency =  RTCCLK / 4096  */
00224 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   RTC_TAFCR_TAMPFREQ_2  /*!< Each of the tamper inputs are sampled
00225                                                                              with a frequency =  RTCCLK / 2048  */
00226 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_2)  /*!< Each of the tamper inputs are sampled
00227                                                                              with a frequency =  RTCCLK / 1024  */
00228 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2)  /*!< Each of the tamper inputs are sampled
00229                                                                              with a frequency =  RTCCLK / 512   */
00230 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2)  /*!< Each of the tamper inputs are sampled
00231                                                                              with a frequency =  RTCCLK / 256   */
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Extended Tamper Pin Precharge Duration Definition
00237   * @{
00238   */
00239 #define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U           /*!< Tamper pins are pre-charged before
00240                                                                          sampling during 1 RTCCLK cycle */
00241 #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0  /*!< Tamper pins are pre-charged before
00242                                                                          sampling during 2 RTCCLK cycles */
00243 #define RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1  /*!< Tamper pins are pre-charged before
00244                                                                          sampling during 4 RTCCLK cycles */
00245 #define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (RTC_TAFCR_TAMPPRCH_0 | RTC_TAFCR_TAMPPRCH_1)  /*!< Tamper pins are pre-charged before
00246                                                                          sampling during 8 RTCCLK cycles */
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Extended Tamper TimeStampOnTamperDetection Definition
00252   * @{
00253   */
00254 #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE  ((uint32_t)RTC_TAFCR_TAMPTS)  /*!< TimeStamp on Tamper Detection event saved */
00255 #define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U       /*!< TimeStamp on Tamper Detection event is not saved */
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Extended Tamper Pull UP Definition
00261   * @{
00262   */
00263 #define RTC_TAMPER_PULLUP_ENABLE  0x00000000U                       /*!< Tamper pins are pre-charged before sampling  */
00264 #define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS)   /*!< Tamper pins are not pre-charged before sampling */
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Extended Wakeup Timer Definition
00270   * @{
00271   */
00272 #define RTC_WAKEUPCLOCK_RTCCLK_DIV16        0x00000000U
00273 #define RTC_WAKEUPCLOCK_RTCCLK_DIV8         RTC_CR_WUCKSEL_0
00274 #define RTC_WAKEUPCLOCK_RTCCLK_DIV4         RTC_CR_WUCKSEL_1
00275 #define RTC_WAKEUPCLOCK_RTCCLK_DIV2         (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
00276 #define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      (RTC_CR_WUCKSEL_2)
00277 #define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Extended Smooth calib period Definition
00283   * @{
00284   */
00285 #define RTC_SMOOTHCALIB_PERIOD_32SEC   0x00000000U            /*!<  If RTCCLK = 32768 Hz, Smooth calibation
00286                                                                     period is 32s,  else 2exp20 RTCCLK seconds */
00287 #define RTC_SMOOTHCALIB_PERIOD_16SEC   RTC_CALR_CALW16        /*!<  If RTCCLK = 32768 Hz, Smooth calibation
00288                                                                     period is 16s, else 2exp19 RTCCLK seconds */
00289 #define RTC_SMOOTHCALIB_PERIOD_8SEC    RTC_CALR_CALW8         /*!<  If RTCCLK = 32768 Hz, Smooth calibation
00290                                                                     period is 8s, else 2exp18 RTCCLK seconds */
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Extended Smooth calib Plus pulses Definition
00296   * @{
00297   */
00298 #define RTC_SMOOTHCALIB_PLUSPULSES_RESET  0x00000000U         /*!<  The number of RTCCLK pulses subbstited
00299                                                                     during a 32-second window =   CALM[8:0] */
00300 #define RTC_SMOOTHCALIB_PLUSPULSES_SET    RTC_CALR_CALP       /*!<  The number of RTCCLK pulses added
00301                                                                     during a X -second window = Y - CALM[8:0]
00302                                                                     with Y = 512U, 256U, 128 when X = 32U, 16U, 8U */
00303 /**
00304   * @}
00305   */
00306
00307  /** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Extended Calib Output selection Definition
00308   * @{
00309   */
00310 #define RTC_CALIBOUTPUT_512HZ            0x00000000U
00311 #define RTC_CALIBOUTPUT_1HZ              RTC_CR_COSEL
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTC Extended Add 1 Second Parameter Definition
00317   * @{
00318   */
00319 #define RTC_SHIFTADD1S_RESET      0x00000000U
00320 #define RTC_SHIFTADD1S_SET        RTC_SHIFTR_ADD1S
00321 /**
00322   * @}
00323   */
00324
00325 /**
00326   * @}
00327   */
00328
00329 /* Exported macro ------------------------------------------------------------*/
00330 /** @defgroup RTCEx_Exported_Macros RTC Extended Exported Macros
00331   * @{
00332   */
00333
00334 /* ---------------------------------WAKEUPTIMER---------------------------------*/
00335 /** @defgroup RTCEx_WakeUp_Timer RTC Extended WakeUp Timer
00336   * @{
00337   */
00338 /**
00339   * @brief  Enable the RTC WakeUp Timer peripheral.
00340   * @param  __HANDLE__ specifies the RTC handle.
00341   * @retval None
00342   */
00343 #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
00344
00345 /**
00346   * @brief  Disable the RTC WakeUp Timer peripheral.
00347   * @param  __HANDLE__ specifies the RTC handle.
00348   * @retval None
00349   */
00350 #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
00351
00352 /**
00353   * @brief  Enable the RTC WakeUpTimer interrupt.
00354   * @param  __HANDLE__ specifies the RTC handle.
00355   * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled.
00356   *         This parameter can be:
00357   *            @arg RTC_IT_WUT: WakeUpTimer interrupt
00358   * @retval None
00359   */
00360 #define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00361
00362 /**
00363   * @brief  Disable the RTC WakeUpTimer interrupt.
00364   * @param  __HANDLE__ specifies the RTC handle.
00365   * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled.
00366   *         This parameter can be:
00367   *            @arg RTC_IT_WUT: WakeUpTimer interrupt
00368   * @retval None
00369   */
00370 #define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00371
00372 /**
00373   * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
00374   * @param  __HANDLE__ specifies the RTC handle.
00375   * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
00376   *         This parameter can be:
00377   *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
00378   * @retval None
00379   */
00380 #define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET) ? SET : RESET)
00381
00382 /**
00383   * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
00384   * @param  __HANDLE__ specifies the RTC handle.
00385   * @param  __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
00386   *         This parameter can be:
00387   *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
00388   * @retval None
00389   */
00390 #define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00391
00392 /**
00393   * @brief  Get the selected RTC WakeUpTimer's flag status.
00394   * @param  __HANDLE__ specifies the RTC handle.
00395   * @param  __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not.
00396   *          This parameter can be:
00397   *             @arg RTC_FLAG_WUTF
00398   *             @arg RTC_FLAG_WUTWF
00399   * @retval None
00400   */
00401 #define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00402
00403 /**
00404   * @brief  Clear the RTC Wake Up timer's pending flags.
00405   * @param  __HANDLE__ specifies the RTC handle.
00406   * @param  __FLAG__ specifies the RTC WakeUpTimer Flag to clear.
00407   *         This parameter can be:
00408   *            @arg RTC_FLAG_WUTF
00409   * @retval None
00410   */
00411 #define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00412
00413 /* WAKE-UP TIMER EXTI */
00414 /* ------------------ */
00415 /**
00416   * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line.
00417   * @retval None
00418   */
00419 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00420
00421 /**
00422   * @brief  Disable interrupt on the RTC WakeUp Timer associated Exti line.
00423   * @retval None
00424   */
00425 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00426
00427 /**
00428   * @brief  Enable event on the RTC WakeUp Timer associated Exti line.
00429   * @retval None.
00430   */
00431 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00432
00433 /**
00434   * @brief  Disable event on the RTC WakeUp Timer associated Exti line.
00435   * @retval None.
00436   */
00437 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00438
00439 /**
00440   * @brief  Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
00441   * @retval None.
00442   */
00443 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00444
00445 /**
00446   * @brief  Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
00447   * @retval None.
00448   */
00449 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00450
00451 /**
00452   * @brief  Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
00453   * @retval None.
00454   */
00455 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00456
00457 /**
00458   * @brief  Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
00459   * @retval None.
00460   */
00461 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00462
00463 /**
00464   * @brief  Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
00465   * @retval None.
00466   */
00467 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
00468
00469 /**
00470   * @brief  Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
00471   * This parameter can be:
00472   * @retval None.
00473   */
00474 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
00475
00476 /**
00477   * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
00478   * @retval Line Status.
00479   */
00480 #define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00481
00482 /**
00483   * @brief Clear the RTC WakeUp Timer associated Exti line flag.
00484   * @retval None.
00485   */
00486 #define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00487
00488 /**
00489   * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
00490   * @retval None.
00491   */
00492 #define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00493 /**
00494   * @}
00495   */
00496
00497 /* ---------------------------------TIMESTAMP---------------------------------*/
00498 /** @defgroup RTCEx_Timestamp RTC Extended Timestamp
00499   * @{
00500   */
00501 /**
00502   * @brief  Enable the RTC TimeStamp peripheral.
00503   * @param  __HANDLE__ specifies the RTC handle.
00504   * @retval None
00505   */
00506 #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                        ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
00507
00508 /**
00509   * @brief  Disable the RTC TimeStamp peripheral.
00510   * @param  __HANDLE__ specifies the RTC handle.
00511   * @retval None
00512   */
00513 #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
00514
00515 /**
00516   * @brief  Enable the RTC TimeStamp interrupt.
00517   * @param  __HANDLE__ specifies the RTC handle.
00518   * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled.
00519   *         This parameter can be:
00520   *            @arg RTC_IT_TS: TimeStamp interrupt
00521   * @retval None
00522   */
00523 #define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00524
00525 /**
00526   * @brief  Disable the RTC TimeStamp interrupt.
00527   * @param  __HANDLE__ specifies the RTC handle.
00528   * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.
00529   *         This parameter can be:
00530   *            @arg RTC_IT_TS: TimeStamp interrupt
00531   * @retval None
00532   */
00533 #define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00534
00535 /**
00536   * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
00537   * @param  __HANDLE__ specifies the RTC handle.
00538   * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
00539   *         This parameter can be:
00540   *            @arg RTC_IT_TS: TimeStamp interrupt
00541   * @retval None
00542   */
00543 #define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)         (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
00544
00545 /**
00546   * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.
00547   * @param  __HANDLE__ specifies the RTC handle.
00548   * @param  __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
00549   *         This parameter can be:
00550   *            @arg RTC_IT_TS: TimeStamp interrupt
00551   * @retval None
00552   */
00553 #define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00554
00555 /**
00556   * @brief  Get the selected RTC TimeStamp's flag status.
00557   * @param  __HANDLE__ specifies the RTC handle.
00558   * @param  __FLAG__ specifies the RTC TimeStamp Flag is pending or not.
00559   *         This parameter can be:
00560   *            @arg RTC_FLAG_TSF
00561   *            @arg RTC_FLAG_TSOVF
00562   * @retval None
00563   */
00564 #define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)            (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
00565
00566 /**
00567   * @brief  Clear the RTC Time Stamp's pending flags.
00568   * @param  __HANDLE__ specifies the RTC handle.
00569   * @param  __FLAG__ specifies the RTC Alarm Flag to clear.
00570   *          This parameter can be:
00571   *             @arg RTC_FLAG_TSF
00572   * @retval None
00573   */
00574 #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)          ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00575
00576 /**
00577   * @}
00578   */
00579
00580 /* ---------------------------------TAMPER------------------------------------*/
00581 /** @defgroup RTCEx_Tamper RTC Extended Tamper
00582   * @{
00583   */
00584
00585 /**
00586   * @brief  Enable the RTC Tamper1 input detection.
00587   * @param  __HANDLE__ specifies the RTC handle.
00588   * @retval None
00589   */
00590 #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
00591
00592 /**
00593   * @brief  Disable the RTC Tamper1 input detection.
00594   * @param  __HANDLE__ specifies the RTC handle.
00595   * @retval None
00596   */
00597 #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
00598
00599 /**
00600   * @brief  Enable the RTC Tamper2 input detection.
00601   * @param  __HANDLE__ specifies the RTC handle.
00602   * @retval None
00603   */
00604 #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E))
00605
00606 /**
00607   * @brief  Disable the RTC Tamper2 input detection.
00608   * @param  __HANDLE__ specifies the RTC handle.
00609   * @retval None
00610   */
00611 #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))
00612
00613 #if defined(RTC_TAMPER3_SUPPORT)
00614 /**
00615   * @brief  Enable the RTC Tamper3 input detection.
00616   * @param  __HANDLE__ specifies the RTC handle.
00617   * @retval None
00618   */
00619 #define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP3E))
00620
00621 /**
00622   * @brief  Disable the RTC Tamper3 input detection.
00623   * @param  __HANDLE__ specifies the RTC handle.
00624   * @retval None
00625   */
00626 #define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP3E))
00627 #endif /* RTC_TAMPER3_SUPPORT */
00628
00629 /**
00630   * @brief  Enable the RTC Tamper interrupt.
00631   * @param  __HANDLE__ specifies the RTC handle.
00632   * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
00633   *          This parameter can be any combination of the following values:
00634   *            @arg RTC_IT_TAMP: Tamper interrupt
00635   * @retval None
00636   */
00637 #define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->TAFCR |= (__INTERRUPT__))
00638
00639 /**
00640   * @brief  Disable the RTC Tamper interrupt.
00641   * @param  __HANDLE__ specifies the RTC handle.
00642   * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
00643   *         This parameter can be any combination of the following values:
00644   *            @arg RTC_IT_TAMP: Tamper interrupt
00645   * @retval None
00646   */
00647 #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__))
00648
00649 /**
00650   * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
00651   * @param  __HANDLE__ specifies the RTC handle.
00652   * @param  __INTERRUPT__ specifies the RTC Tamper interrupt to check.
00653   *         This parameter can be:
00654   *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
00655   *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
00656   *            @arg  RTC_IT_TAMP3: Tamper3 interrupt (*)
00657   * @note   (*) RTC_IT_TAMP3 not present on all the devices
00658   * @retval None
00659   */
00660 #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
00661
00662 /**
00663   * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
00664   * @param  __HANDLE__ specifies the RTC handle.
00665   * @param  __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
00666   *         This parameter can be:
00667   *            @arg RTC_IT_TAMP: Tamper interrupt
00668   * @retval None
00669   */
00670 #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00671
00672  /**
00673   * @brief  Get the selected RTC Tamper's flag status.
00674   * @param  __HANDLE__ specifies the RTC handle.
00675   * @param  __FLAG__ specifies the RTC Tamper Flag is pending or not.
00676   *          This parameter can be:
00677   *             @arg RTC_FLAG_TAMP1F
00678   *             @arg RTC_FLAG_TAMP2F
00679   *             @arg RTC_FLAG_TAMP3F (*)
00680   * @note   (*) RTC_FLAG_TAMP3F not present on all the devices
00681   * @retval None
00682   */
00683 #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
00684
00685
00686 /**
00687   * @brief  Clear the RTC Tamper's pending flags.
00688   * @param  __HANDLE__ specifies the RTC handle.
00689   * @param  __FLAG__ specifies the RTC Tamper Flag to clear.
00690   *          This parameter can be:
00691   *             @arg RTC_FLAG_TAMP1F
00692   *             @arg RTC_FLAG_TAMP2F
00693   *             @arg RTC_FLAG_TAMP3F (*)
00694   * @note   (*) RTC_FLAG_TAMP3F not present on all the devices
00695   * @retval None
00696   */
00697 #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00698
00699
00700 /**
00701   * @}
00702   */
00703
00704 /* --------------------------TAMPER/TIMESTAMP---------------------------------*/
00705 /** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Extended Tamper Timestamp EXTI
00706   * @{
00707   */
00708
00709 /* TAMPER TIMESTAMP EXTI */
00710 /* --------------------- */
00711 /**
00712   * @brief  Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
00713   * @retval None
00714   */
00715 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00716
00717 /**
00718   * @brief  Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
00719   * @retval None
00720   */
00721 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00722
00723 /**
00724   * @brief  Enable event on the RTC Tamper and Timestamp associated Exti line.
00725   * @retval None.
00726   */
00727 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00728
00729 /**
00730   * @brief  Disable event on the RTC Tamper and Timestamp associated Exti line.
00731   * @retval None.
00732   */
00733 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00734
00735 /**
00736   * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00737   * @retval None.
00738   */
00739 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00740
00741 /**
00742   * @brief  Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00743   * @retval None.
00744   */
00745 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00746
00747 /**
00748   * @brief  Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
00749   * @retval None.
00750   */
00751 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00752
00753 /**
00754   * @brief  Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
00755   * @retval None.
00756   */
00757 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00758
00759 /**
00760   * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00761   * @retval None.
00762   */
00763 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
00764
00765 /**
00766   * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00767   * This parameter can be:
00768   * @retval None.
00769   */
00770 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
00771
00772 /**
00773   * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
00774   * @retval Line Status.
00775   */
00776 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00777
00778 /**
00779   * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
00780   * @retval None.
00781   */
00782 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00783
00784 /**
00785   * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
00786   * @retval None.
00787   */
00788 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()    (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00789 /**
00790   * @}
00791   */
00792
00793 /* ------------------------------Calibration----------------------------------*/
00794 /** @defgroup RTCEx_Calibration RTC Extended Calibration
00795   * @{
00796   */
00797
00798 /**
00799   * @brief  Enable the RTC calibration output.
00800   * @param  __HANDLE__ specifies the RTC handle.
00801   * @retval None
00802   */
00803 #define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
00804
00805 /**
00806   * @brief  Disable the calibration output.
00807   * @param  __HANDLE__ specifies the RTC handle.
00808   * @retval None
00809   */
00810 #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
00811
00812 /**
00813   * @brief  Enable the clock reference detection.
00814   * @param  __HANDLE__ specifies the RTC handle.
00815   * @retval None
00816   */
00817 #define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
00818
00819 /**
00820   * @brief  Disable the clock reference detection.
00821   * @param  __HANDLE__ specifies the RTC handle.
00822   * @retval None
00823   */
00824 #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
00825
00826 /**
00827   * @brief  Get the selected RTC shift operation's flag status.
00828   * @param  __HANDLE__ specifies the RTC handle.
00829   * @param  __FLAG__ specifies the RTC shift operation Flag is pending or not.
00830   *          This parameter can be:
00831   *             @arg RTC_FLAG_SHPF
00832   * @retval None
00833   */
00834 #define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
00835 /**
00836   * @}
00837   */
00838
00839 /**
00840   * @}
00841   */
00842
00843 /* Exported functions --------------------------------------------------------*/
00844 /** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
00845   * @{
00846   */
00847
00848 /* RTC TimeStamp and Tamper functions *****************************************/
00849 /** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp and Tamper functions
00850  * @{
00851  */
00852
00853 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
00854 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
00855 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
00856 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
00857
00858 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
00859 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
00860 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
00861 void              HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
00862
00863 void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
00864 void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
00865 void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
00866 void              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
00867 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00868 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00869 HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00870 HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00871 /**
00872   * @}
00873   */
00874
00875 /* RTC Wake-up functions ******************************************************/
00876 /** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
00877  * @{
00878  */
00879
00880 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
00881 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
00882 uint32_t          HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
00883 uint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
00884 void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
00885 void              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
00886 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00887 /**
00888   * @}
00889   */
00890
00891 /* Extended Control functions ************************************************/
00892 /** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
00893  * @{
00894  */
00895
00896 void              HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
00897 uint32_t          HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
00898
00899 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
00900 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
00901 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
00902 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
00903 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
00904 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
00905 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
00906 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
00907 /**
00908   * @}
00909   */
00910
00911 /* Extended RTC features functions *******************************************/
00912 /** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
00913  * @{
00914  */
00915 void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
00916 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00917
00918 /**
00919   * @}
00920   */
00921
00922 /**
00923   * @}
00924   */
00925
00926 /* Private types -------------------------------------------------------------*/
00927 /* Private variables ---------------------------------------------------------*/
00928 /* Private constants ---------------------------------------------------------*/
00929 /* Private macros ------------------------------------------------------------*/
00930 /** @defgroup RTCEx_Private_Macros RTCEx Private Macros
00931   * @{
00932   */
00933
00934 /** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
00935   * @{
00936   */
00937 #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
00938                                ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
00939                                ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
00940                                ((OUTPUT) == RTC_OUTPUT_WAKEUP))
00941
00942 #define IS_RTC_BKP(BKP)                   ((BKP) < (uint32_t) RTC_BKP_NUMBER)
00943
00944 #define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
00945                                  ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
00946
00947 #define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & 0xFFFFFFD6U) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
00948
00949
00950 #define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
00951
00952
00953 #define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
00954                                         ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
00955                                         ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
00956                                         ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
00957 #define IS_RTC_TAMPER_FILTER(FILTER)  (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
00958                                        ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
00959                                        ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
00960                                        ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
00961 #define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
00962                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
00963                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
00964                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
00965                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
00966                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
00967                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
00968                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
00969 #define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
00970                                                     ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
00971                                                     ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
00972                                                     ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
00973 #define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
00974                                                               ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
00975 #define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
00976                                            ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
00977 #define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)   || \
00978                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
00979                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
00980                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
00981                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
00982                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
00983
00984 #define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFFU)
00985
00986
00987 #define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
00988                                             ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
00989                                             ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
00990 #define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
00991                                         ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
00992
00993
00994 #define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU)
00995 #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
00996                                  ((SEL) == RTC_SHIFTADD1S_SET))
00997 #define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU)
00998 #define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
00999                                       ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
01000 /**
01001   * @}
01002   */
01003
01004 /**
01005   * @}
01006   */
01007
01008 /**
01009   * @}
01010   */
01011
01012 /**
01013   * @}
01014   */
01015
01016 #ifdef __cplusplus
01017 }
01018 #endif
01019
01020 #endif /* __STM32F3xx_HAL_RTC_EX_H */
01021
01022 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_sdadc.c Source File

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stm32f3xx_hal_sdadc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_sdadc.c
00004   * @author  MCD Application Team
00005   * @brief   This file provides firmware functions to manage the following
00006   *          functionalities of the Sigma-Delta Analog to Digital Converter
00007   *          (SDADC) peripherals:
00008   *           + Initialization and Configuration
00009   *           + Regular Channels Configuration
00010   *           + Injected channels Configuration
00011   *           + Power saving
00012   *           + Regular/Injected Channels DMA Configuration
00013   *           + Interrupts and flags management
00014   @verbatim
00015   ==============================================================================
00016                     ##### SDADC specific features #####
00017   ==============================================================================
00018   [..]
00019   (#) 16-bit sigma delta architecture.
00020   (#) Self calibration.
00021   (#) Interrupt generation at the end of calibration, regular/injected conversion
00022       and in case of overrun events.
00023   (#) Single and continuous conversion modes.
00024   (#) External trigger option with configurable polarity for injected conversion.
00025   (#) Multi mode (synchronized another SDADC with SDADC1).
00026   (#) DMA request generation during regular or injected channel conversion.
00027
00028                      ##### How to use this driver #####
00029   ==============================================================================
00030   [..]
00031     *** Initialization ***
00032     ======================
00033     [..]
00034       (#) As prerequisite, fill in the HAL_SDADC_MspInit() :
00035         (++) Enable SDADCx clock interface with __SDADCx_CLK_ENABLE().
00036         (++) Configure SDADCx clock divider with HAL_RCCEx_PeriphCLKConfig.
00037         (++) Enable power on SDADC with HAL_PWREx_EnableSDADC().
00038         (++) Enable the clocks for the SDADC GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
00039         (++) Configure these SDADC pins in analog mode using HAL_GPIO_Init().
00040         (++) If interrupt mode is used, enable and configure SDADC global
00041             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00042         (++) If DMA mode is used, configure DMA with HAL_DMA_Init and link it
00043             with SDADC handle using __HAL_LINKDMA.
00044       (#) Configure the SDADC low power mode, fast conversion mode, slow clock
00045           mode and SDADC1 reference voltage using the HAL_ADC_Init() function.
00046           Note: Common reference voltage. is common to all SDADC instances.
00047       (#) Prepare channel configurations (input mode, common mode, gain and
00048           offset) using HAL_SDADC_PrepareChannelConfig and associate channel
00049           with one configuration using HAL_SDADC_AssociateChannelConfig.
00050
00051     *** Calibration ***
00052     ============================================
00053     [..]
00054       (#) Start calibration using HAL_SDADC_StartCalibration or
00055           HAL_SDADC_CalibrationStart_IT.
00056       (#) In polling mode, use HAL_SDADC_PollForCalibEvent to detect the end of
00057           calibration.
00058       (#) In interrupt mode, HAL_SDADC_CalibrationCpltCallback will be called at
00059           the end of calibration.
00060
00061     *** Regular channel conversion ***
00062     ============================================
00063     [..]
00064       (#) Select trigger for regular conversion using
00065           HAL_SDADC_SelectRegularTrigger.
00066       (#) Select regular channel and enable/disable continuous mode using
00067           HAL_SDADC_ConfigChannel.
00068       (#) Start regular conversion using HAL_SDADC_Start, HAL_SDADC_Start_IT
00069           or HAL_SDADC_Start_DMA.
00070       (#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
00071           regular conversion.
00072       (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
00073           end of regular conversion.
00074       (#) Get value of regular conversion using HAL_SDADC_GetValue.
00075       (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
00076           HAL_SDADC_ConvCpltCallback will be called respectively at the half
00077           transfer and at the transfer complete.
00078       (#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
00079           or HAL_SDADC_Stop_DMA.
00080
00081     *** Injected channels conversion ***
00082     ============================================
00083     [..]
00084       (#) Enable/disable delay on injected conversion using
00085           HAL_SDADC_SelectInjectedDelay.
00086       (#) If external trigger is used for injected conversion, configure this
00087           trigger using HAL_SDADC_SelectInjectedExtTrigger.
00088       (#) Select trigger for injected conversion using
00089           HAL_SDADC_SelectInjectedTrigger.
00090       (#) Select injected channels and enable/disable continuous mode using
00091           HAL_SDADC_InjectedConfigChannel.
00092       (#) Start injected conversion using HAL_SDADC_InjectedStart,
00093           HAL_SDADC_InjectedStart_IT or HAL_SDADC_InjectedStart_DMA.
00094       (#) In polling mode, use HAL_SDADC_PollForInjectedConversion to detect the
00095           end of injected conversion.
00096       (#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
00097           at the end of injected conversion.
00098       (#) Get value of injected conversion and corresponding channel using
00099           HAL_SDADC_InjectedGetValue.
00100       (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
00101           HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
00102           half transfer and at the transfer complete.
00103       (#) Stop injected conversion using HAL_SDADC_InjectedStop,
00104           HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjectedStop_DMA.
00105
00106     *** Multi mode regular channels conversions ***
00107     ======================================================
00108     [..]
00109       (#) Select type of multimode (SDADC1/SDADC2 or SDADC1/SDADC3) using
00110           HAL_SDADC_MultiModeConfigChannel.
00111       (#) Select software trigger for SDADC1 and synchronized trigger for
00112           SDADC2 (or SDADC3) using HAL_SDADC_SelectRegularTrigger.
00113       (#) Select regular channel for SDADC1 and SDADC2 (or SDADC3) using
00114           HAL_SDADC_ConfigChannel.
00115       (#) Start regular conversion for SDADC2 (or SDADC3) with HAL_SDADC_Start.
00116       (#) Start regular conversion for SDADC1 using HAL_SDADC_Start,
00117           HAL_SDADC_Start_IT or HAL_SDADC_MultiModeStart_DMA.
00118       (#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
00119           regular conversion for SDADC1.
00120       (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
00121           end of regular conversion for SDADC1.
00122       (#) Get value of regular conversions using HAL_SDADC_MultiModeGetValue.
00123       (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
00124           HAL_SDADC_ConvCpltCallback will be called respectively at the half
00125           transfer and at the transfer complete for SDADC1.
00126       (#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
00127           or HAL_SDADC_MultiModeStop_DMA for SDADC1.
00128       (#) Stop regular conversion using HAL_SDADC_Stop for SDADC2 (or SDADC3).
00129
00130     *** Multi mode injected channels conversions ***
00131     ======================================================
00132     [..]
00133       (#) Select type of multimode (SDADC1/SDADC2 or SDADC1/SDADC3) using
00134           HAL_SDADC_InjectedMultiModeConfigChannel.
00135       (#) Select software or external trigger for SDADC1 and synchronized
00136           trigger for SDADC2 (or SDADC3) using HAL_SDADC_SelectInjectedTrigger.
00137       (#) Select injected channels for SDADC1 and SDADC2 (or SDADC3) using
00138           HAL_SDADC_InjectedConfigChannel.
00139       (#) Start injected conversion for SDADC2 (or SDADC3) with
00140           HAL_SDADC_InjectedStart.
00141       (#) Start injected conversion for SDADC1 using HAL_SDADC_InjectedStart,
00142           HAL_SDADC_InjectedStart_IT or HAL_SDADC_InjectedMultiModeStart_DMA.
00143       (#) In polling mode, use HAL_SDADC_InjectedPollForConversion to detect
00144           the end of injected conversion for SDADC1.
00145       (#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
00146           at the end of injected conversion for SDADC1.
00147       (#) Get value of injected conversions using
00148           HAL_SDADC_InjectedMultiModeGetValue.
00149       (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
00150           HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
00151           half transfer and at the transfer complete for SDADC1.
00152       (#) Stop injected conversion using HAL_SDADC_InjectedStop,
00153           HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjecteddMultiModeStop_DMA
00154           for SDADC1.
00155       (#) Stop injected conversion using HAL_SDADC_InjectedStop for SDADC2
00156           (or SDADC3).
00157
00158     @endverbatim
00159   ******************************************************************************
00160   * @attention
00161   *
00162   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00163   *
00164   * Redistribution and use in source and binary forms, with or without modification,
00165   * are permitted provided that the following conditions are met:
00166   *   1. Redistributions of source code must retain the above copyright notice,
00167   *      this list of conditions and the following disclaimer.
00168   *   2. Redistributions in binary form must reproduce the above copyright notice,
00169   *      this list of conditions and the following disclaimer in the documentation
00170   *      and/or other materials provided with the distribution.
00171   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00172   *      may be used to endorse or promote products derived from this software
00173   *      without specific prior written permission.
00174   *
00175   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00176   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00177   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00178   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00179   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00180   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00181   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00182   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00183   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00184   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00185   *
00186   ******************************************************************************
00187   */
00188
00189 /* Includes ------------------------------------------------------------------*/
00190 #include "stm32f3xx_hal.h"
00191
00192 /** @addtogroup STM32F3xx_HAL_Driver
00193   * @{
00194   */
00195
00196 #ifdef HAL_SDADC_MODULE_ENABLED
00197 #if defined(STM32F373xC) || defined(STM32F378xx)
00198 /** @defgroup SDADC SDADC
00199   * @brief SDADC HAL driver modules
00200   * @{
00201   */
00202
00203 /* Private typedef -----------------------------------------------------------*/
00204 /* Private define ------------------------------------------------------------*/
00205 /** @defgroup SDADC_Private_Define SDADC Private Define
00206  * @{
00207  */
00208 #define SDADC_TIMEOUT          200
00209 #define SDADC_CONFREG_OFFSET   0x00000020
00210 #define SDADC_JDATAR_CH_OFFSET 24
00211 #define SDADC_MSB_MASK         0xFFFF0000U
00212 #define SDADC_LSB_MASK         0x0000FFFFU
00213 /**
00214   * @}
00215   */
00216
00217 /* Private macro -------------------------------------------------------------*/
00218 /* Private variables ---------------------------------------------------------*/
00219 /* Private function prototypes -----------------------------------------------*/
00220 /** @defgroup SDADC_Private_Functions SDADC Private Functions
00221   * @{
00222   */
00223
00224 static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc);
00225 static void              SDADC_ExitInitMode(SDADC_HandleTypeDef* hsdadc);
00226 static uint32_t          SDADC_GetInjChannelsNbr(uint32_t Channels);
00227 static HAL_StatusTypeDef SDADC_RegConvStart(SDADC_HandleTypeDef* hsdadc);
00228 static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc);
00229 static HAL_StatusTypeDef SDADC_InjConvStart(SDADC_HandleTypeDef* hsdadc);
00230 static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc);
00231 static void              SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
00232 static void              SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
00233 static void              SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
00234 static void              SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
00235 static void              SDADC_DMAError(DMA_HandleTypeDef *hdma);
00236 /**
00237   * @}
00238   */
00239
00240 /* Exported functions ---------------------------------------------------------*/
00241
00242 /** @defgroup SDADC_Exported_Functions SDADC Exported Functions
00243   * @{
00244   */
00245
00246 /** @defgroup SDADC_Exported_Functions_Group1 Initialization and de-initialization functions
00247  *  @brief    Initialization and de-initialization functions
00248  *
00249 @verbatim
00250   ===============================================================================
00251               ##### Initialization and de-initialization functions #####
00252   ===============================================================================
00253     [..]  This section provides functions allowing to:
00254       (+) Initialize the SDADC.
00255       (+) De-initialize the SDADC.
00256
00257 @endverbatim
00258   * @{
00259   */
00260
00261 /**
00262   * @brief  Initializes the SDADC according to the specified
00263   *         parameters in the SDADC_InitTypeDef structure.
00264   * @note   If multiple SDADC are used, please configure first SDADC1 to set
00265   *         the common reference voltage.
00266   * @param  hsdadc SDADC handle.
00267   * @retval HAL status.
00268   */
00269 HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc)
00270 {
00271   /* Check SDADC handle */
00272   if(hsdadc == NULL)
00273   {
00274     return HAL_ERROR;
00275   }
00276
00277   /* Check parameters */
00278   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
00279   assert_param(IS_SDADC_LOWPOWER_MODE(hsdadc->Init.IdleLowPowerMode));
00280   assert_param(IS_SDADC_FAST_CONV_MODE(hsdadc->Init.FastConversionMode));
00281   assert_param(IS_SDADC_SLOW_CLOCK_MODE(hsdadc->Init.SlowClockMode));
00282   assert_param(IS_SDADC_VREF(hsdadc->Init.ReferenceVoltage));
00283
00284   /* Initialize SDADC variables with default values */
00285   hsdadc->RegularContMode     = SDADC_CONTINUOUS_CONV_OFF;
00286   hsdadc->InjectedContMode    = SDADC_CONTINUOUS_CONV_OFF;
00287   hsdadc->InjectedChannelsNbr = 1U;
00288   hsdadc->InjConvRemaining    = 1U;
00289   hsdadc->RegularTrigger      = SDADC_SOFTWARE_TRIGGER;
00290   hsdadc->InjectedTrigger     = SDADC_SOFTWARE_TRIGGER;
00291   hsdadc->ExtTriggerEdge      = SDADC_EXT_TRIG_RISING_EDGE;
00292   hsdadc->RegularMultimode    = SDADC_MULTIMODE_SDADC1_SDADC2;
00293   hsdadc->InjectedMultimode   = SDADC_MULTIMODE_SDADC1_SDADC2;
00294   hsdadc->ErrorCode           = SDADC_ERROR_NONE;
00295
00296   /* Call MSP init function */
00297   HAL_SDADC_MspInit(hsdadc);
00298
00299   /* Set idle low power and slow clock modes */
00300   hsdadc->Instance->CR1 &= ~(SDADC_CR1_SBI|SDADC_CR1_PDI|SDADC_CR1_SLOWCK);
00301   hsdadc->Instance->CR1 |= (hsdadc->Init.IdleLowPowerMode | \
00302                             hsdadc->Init.SlowClockMode);
00303
00304   /* Set fast conversion mode */
00305   hsdadc->Instance->CR2 &= ~(SDADC_CR2_FAST);
00306   hsdadc->Instance->CR2 |= hsdadc->Init.FastConversionMode;
00307
00308   /* Set reference voltage common to all SDADC instances */
00309   /* Update this parameter only if needed to avoid unnecessary settling time */
00310   if((SDADC1->CR1 & SDADC_CR1_REFV) != hsdadc->Init.ReferenceVoltage)
00311   {
00312     /* Voltage reference bits are common to all SADC instances but are        */
00313     /* present in SDADC1 register.                                            */
00314     SDADC1->CR1 &= ~(SDADC_CR1_REFV);
00315     SDADC1->CR1 |= hsdadc->Init.ReferenceVoltage;
00316
00317     /* Wait at least 2ms before setting ADON */
00318     HAL_Delay(2U);
00319   }
00320
00321   /* Enable SDADC */
00322   hsdadc->Instance->CR2 |= SDADC_CR2_ADON;
00323
00324   /* Wait end of stabilization */
00325   while((hsdadc->Instance->ISR & SDADC_ISR_STABIP) != 0U)
00326   {
00327   }
00328
00329   /* Set SDADC to ready state */
00330   hsdadc->State = HAL_SDADC_STATE_READY;
00331
00332   /* Return HAL status */
00333   return HAL_OK;
00334 }
00335
00336 /**
00337   * @brief  De-initializes the SDADC.
00338   * @param  hsdadc SDADC handle.
00339   * @retval HAL status.
00340   */
00341 HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef* hsdadc)
00342 {
00343   /* Check SDADC handle */
00344   if(hsdadc == NULL)
00345   {
00346     return HAL_ERROR;
00347   }
00348
00349   /* Check parameters */
00350   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
00351
00352   /* Disable the SDADC */
00353   hsdadc->Instance->CR2 &= ~(SDADC_CR2_ADON);
00354
00355   /* Reset all registers */
00356   hsdadc->Instance->CR1      = 0x00000000U;
00357   hsdadc->Instance->CR2      = 0x00000000U;
00358   hsdadc->Instance->JCHGR    = 0x00000001U;
00359   hsdadc->Instance->CONF0R   = 0x00000000U;
00360   hsdadc->Instance->CONF1R   = 0x00000000U;
00361   hsdadc->Instance->CONF2R   = 0x00000000U;
00362   hsdadc->Instance->CONFCHR1 = 0x00000000U;
00363   hsdadc->Instance->CONFCHR2 = 0x00000000U;
00364
00365   /* Call MSP deinit function */
00366   HAL_SDADC_MspDeInit(hsdadc);
00367
00368   /* Set SDADC in reset state */
00369   hsdadc->State = HAL_SDADC_STATE_RESET;
00370
00371   /* Return function status */
00372   return HAL_OK;
00373 }
00374
00375 /**
00376   * @brief  Initializes the SDADC MSP.
00377   * @param  hsdadc SDADC handle
00378   * @retval None
00379   */
00380 __weak void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc)
00381 {
00382   /* Prevent unused argument(s) compilation warning */
00383   UNUSED(hsdadc);
00384
00385   /* NOTE : This function should not be modified, when the callback is needed,
00386             the HAL_SDADC_MspInit could be implemented in the user file.
00387    */
00388 }
00389
00390 /**
00391   * @brief  De-initializes the SDADC MSP.
00392   * @param  hsdadc SDADC handle
00393   * @retval None
00394   */
00395 __weak void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc)
00396 {
00397   /* Prevent unused argument(s) compilation warning */
00398   UNUSED(hsdadc);
00399
00400   /* NOTE : This function should not be modified, when the callback is needed,
00401             the HAL_SDADC_MspDeInit could be implemented in the user file.
00402    */
00403 }
00404
00405 /**
00406   * @}
00407   */
00408
00409 /** @defgroup SDADC_Exported_Functions_Group2 peripheral control functions
00410  *  @brief    Peripheral control functions
00411  *
00412 @verbatim
00413   ===============================================================================
00414               ##### Peripheral control functions #####
00415   ===============================================================================
00416     [..]  This section provides functions allowing to:
00417       (+) Program one of the three different configurations for channels.
00418       (+) Associate channel to one of configurations.
00419       (+) Select regular and injected channels.
00420       (+) Enable/disable continuous mode for regular and injected conversions.
00421       (+) Select regular and injected triggers.
00422       (+) Select and configure injected external trigger.
00423       (+) Enable/disable delay addition for injected conversions.
00424       (+) Configure multimode.
00425
00426 @endverbatim
00427   * @{
00428   */
00429
00430 /**
00431   * @brief  This function allows the user to set parameters for a configuration.
00432   *         Parameters are input mode, common mode, gain and offset.
00433   * @note   This function should be called only when SDADC instance is in idle state
00434   *         (neither calibration nor regular or injected conversion ongoing)
00435   * @param  hsdadc SDADC handle.
00436   * @param  ConfIndex Index of configuration to modify.
00437   *         This parameter can be a value of @ref SDADC_ConfIndex.
00438   * @param  ConfParamStruct Parameters to apply for this configuration.
00439   * @retval HAL status
00440   */
00441 HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
00442                                                  uint32_t ConfIndex,
00443                                                  SDADC_ConfParamTypeDef* ConfParamStruct)
00444 {
00445   HAL_StatusTypeDef status = HAL_OK;
00446   uint32_t          tmp = 0U;
00447
00448   /* Check parameters */
00449   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
00450   assert_param(IS_SDADC_CONF_INDEX(ConfIndex));
00451   assert_param(ConfParamStruct != NULL);
00452   assert_param(IS_SDADC_INPUT_MODE(ConfParamStruct->InputMode));
00453   assert_param(IS_SDADC_GAIN(ConfParamStruct->Gain));
00454   assert_param(IS_SDADC_COMMON_MODE(ConfParamStruct->CommonMode));
00455   assert_param(IS_SDADC_OFFSET_VALUE(ConfParamStruct->Offset));
00456
00457   /* Check SDADC state is ready */
00458   if(hsdadc->State != HAL_SDADC_STATE_READY)
00459   {
00460     status = HAL_ERROR;
00461   }
00462   else
00463   {
00464     /* Enter init mode */
00465     if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
00466     {
00467       /* Set SDADC in error state */
00468       hsdadc->State = HAL_SDADC_STATE_ERROR;
00469       status = HAL_TIMEOUT;
00470     }
00471     else
00472     {
00473       /* Program configuration register with parameters */
00474       tmp = (uint32_t)((uint32_t)(hsdadc->Instance) + \
00475                        SDADC_CONFREG_OFFSET + \
00476                        (uint32_t)(ConfIndex << 2U));
00477       *(__IO uint32_t *) (tmp) = (uint32_t) (ConfParamStruct->InputMode | \
00478                                              ConfParamStruct->Gain | \
00479                                              ConfParamStruct->CommonMode | \
00480                                              ConfParamStruct->Offset);
00481       /* Exit init mode */
00482       SDADC_ExitInitMode(hsdadc);
00483     }
00484   }
00485   /* Return function status */
00486   return status;
00487 }
00488
00489 /**
00490   * @brief  This function allows the user to associate a channel with one of the
00491   *         available configurations.
00492   * @note   This function should be called only when SDADC instance is in idle state
00493   *         (neither calibration nor regular or injected conversion ongoing)
00494   * @param  hsdadc SDADC handle.
00495   * @param  Channel Channel to associate with configuration.
00496   *         This parameter can be a value of @ref SDADC_Channel_Selection.
00497   * @param  ConfIndex Index of configuration to associate with channel.
00498   *         This parameter can be a value of @ref SDADC_ConfIndex.
00499   * @retval HAL status
00500   */
00501 HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
00502                                                    uint32_t Channel,
00503                                                    uint32_t ConfIndex)
00504 {
00505   HAL_StatusTypeDef status = HAL_OK;
00506   uint32_t          channelnum = 0U;
00507
00508   /* Check parameters */
00509   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
00510   assert_param(IS_SDADC_REGULAR_CHANNEL(Channel));
00511   assert_param(IS_SDADC_CONF_INDEX(ConfIndex));
00512
00513   /* Check SDADC state is ready */
00514   if(hsdadc->State != HAL_SDADC_STATE_READY)
00515   {
00516     status = HAL_ERROR;
00517   }
00518   else
00519   {
00520     /* Enter init mode */
00521     if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
00522     {
00523       /* Set SDADC in error state */
00524       hsdadc->State = HAL_SDADC_STATE_ERROR;
00525       status = HAL_TIMEOUT;
00526     }
00527     else
00528     {
00529       /* Program channel configuration register according parameters */
00530       if(Channel != SDADC_CHANNEL_8)
00531       {
00532         /* Get channel number */
00533         channelnum = (uint32_t)(Channel>>16U);
00534
00535         /* Set the channel configuration */
00536         hsdadc->Instance->CONFCHR1 &= (uint32_t) ~((uint32_t)SDADC_CONFCHR1_CONFCH0 << (channelnum << 2U));
00537         hsdadc->Instance->CONFCHR1 |= (uint32_t) (ConfIndex << (channelnum << 2U));
00538       }
00539       else
00540       {
00541         hsdadc->Instance->CONFCHR2 = (uint32_t) (ConfIndex);
00542       }
00543       /* Exit init mode */
00544       SDADC_ExitInitMode(hsdadc);
00545     }
00546   }
00547   /* Return function status */
00548   return status;
00549 }
00550
00551 /**
00552   * @brief  This function allows to select channel for regular conversion and
00553   *         to enable/disable continuous mode for regular conversion.
00554   * @param  hsdadc SDADC handle.
00555   * @param  Channel Channel for regular conversion.
00556   *         This parameter can be a value of @ref SDADC_Channel_Selection.
00557   * @param  ContinuousMode Enable/disable continuous mode for regular conversion.
00558   *         This parameter can be a value of @ref SDADC_ContinuousMode.
00559   * @retval HAL status
00560   */
00561 HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc,
00562                                           uint32_t Channel,
00563                                           uint32_t ContinuousMode)
00564 {
00565   HAL_StatusTypeDef status = HAL_OK;
00566
00567   /* Check parameters */
00568   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
00569   assert_param(IS_SDADC_REGULAR_CHANNEL(Channel));
00570   assert_param(IS_SDADC_CONTINUOUS_MODE(ContinuousMode));
00571
00572   /* Check SDADC state */
00573   if((hsdadc->State != HAL_SDADC_STATE_RESET) && (hsdadc->State != HAL_SDADC_STATE_ERROR))
00574   {
00575     /* Set RCH[3:0] and RCONT bits in SDADC_CR2 */
00576     hsdadc->Instance->CR2 &= (uint32_t) ~(SDADC_CR2_RCH | SDADC_CR2_RCONT);
00577     if(ContinuousMode == SDADC_CONTINUOUS_CONV_ON)
00578     {
00579       hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK) | SDADC_CR2_RCONT);
00580     }
00581     else
00582     {
00583       hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK));
00584     }
00585     /* Store continuous mode information */
00586     hsdadc->RegularContMode = ContinuousMode;
00587   }
00588   else
00589   {
00590     status = HAL_ERROR;
00591   }
00592   /* Return function status */
00593   return status;
00594 }
00595
00596 /**
00597   * @brief  This function allows to select channels for injected conversion and
00598   *         to enable/disable continuous mode for injected conversion.
00599   * @param  hsdadc SDADC handle.
00600   * @param  Channel Channels for injected conversion.
00601   *         This parameter can be a values combination of @ref SDADC_Channel_Selection.
00602   * @param  ContinuousMode Enable/disable continuous mode for injected conversion.
00603   *         This parameter can be a value of @ref SDADC_ContinuousMode.
00604   * @retval HAL status
00605   */
00606 HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc,
00607                                                   uint32_t Channel,
00608                                                   uint32_t ContinuousMode)
00609 {
00610   HAL_StatusTypeDef status = HAL_OK;
00611
00612   /* Check parameters */
00613   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
00614   assert_param(IS_SDADC_INJECTED_CHANNEL(Channel));
00615   assert_param(IS_SDADC_CONTINUOUS_MODE(ContinuousMode));
00616
00617   /* Check SDADC state */
00618   if((hsdadc->State != HAL_SDADC_STATE_RESET) && (hsdadc->State != HAL_SDADC_STATE_ERROR))
00619   {
00620     /* Set JCHG[8:0] bits in SDADC_JCHG */
00621     hsdadc->Instance->JCHGR = (uint32_t) (Channel & SDADC_LSB_MASK);
00622     /* Set or clear JCONT bit in SDADC_CR2 */
00623     if(ContinuousMode == SDADC_CONTINUOUS_CONV_ON)
00624     {
00625       hsdadc->Instance->CR2 |= SDADC_CR2_JCONT;
00626     }
00627     else
00628     {
00629       hsdadc->Instance->CR2 &= ~(SDADC_CR2_JCONT);
00630     }
00631     /* Store continuous mode information */
00632     hsdadc->InjectedContMode = ContinuousMode;
00633     /* Store number of injected channels */
00634     hsdadc->InjectedChannelsNbr = SDADC_GetInjChannelsNbr(Channel);
00635   }
00636   else
00637   {
00638     status = HAL_ERROR;
00639   }
00640   /* Return function status */
00641   return status;
00642 }
00643
00644 /**
00645   * @brief  This function allows to select trigger for regular conversions.
00646   * @note   This function should not be called if regular conversion is ongoing.
00647   * @param  hsdadc SDADC handle.
00648   * @param  Trigger Trigger for regular conversions.
00649   *         This parameter can be one of the following value :
00650   *            @arg SDADC_SOFTWARE_TRIGGER : Software trigger.
00651   *            @arg SDADC_SYNCHRONOUS_TRIGGER : Synchronous with SDADC1 (only for SDADC2 and SDADC3).
00652   * @retval HAL status
00653   */
00654 HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
00655 {
00656   HAL_StatusTypeDef status = HAL_OK;
00657
00658   /* Check parameters */
00659   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
00660   assert_param(IS_SDADC_REGULAR_TRIGGER(Trigger));
00661
00662   /* Check parameters compatibility */
00663   if((hsdadc->Instance == SDADC1) && (Trigger == SDADC_SYNCHRONOUS_TRIGGER))
00664   {
00665     status = HAL_ERROR;
00666   }
00667   /* Check SDADC state */
00668   else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
00669           (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
00670           (hsdadc->State == HAL_SDADC_STATE_INJ))
00671   {
00672     /* Store regular trigger information */
00673     hsdadc->RegularTrigger = Trigger;
00674   }
00675   else
00676   {
00677     status = HAL_ERROR;
00678   }
00679   /* Return function status */
00680   return status;
00681 }
00682
00683 /**
00684   * @brief  This function allows to select trigger for injected conversions.
00685   * @note   This function should not be called if injected conversion is ongoing.
00686   * @param  hsdadc SDADC handle.
00687   * @param  Trigger Trigger for injected conversions.
00688   *         This parameter can be one of the following value :
00689   *            @arg SDADC_SOFTWARE_TRIGGER : Software trigger.
00690   *            @arg SDADC_SYNCHRONOUS_TRIGGER : Synchronous with SDADC1 (only for SDADC2 and SDADC3).
00691   *            @arg SDADC_EXTERNAL_TRIGGER : External trigger.
00692   * @retval HAL status
00693   */
00694 HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
00695 {
00696   HAL_StatusTypeDef status = HAL_OK;
00697
00698   /* Check parameters */
00699   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
00700   assert_param(IS_SDADC_INJECTED_TRIGGER(Trigger));
00701
00702   /* Check parameters compatibility */
00703   if((hsdadc->Instance == SDADC1) && (Trigger == SDADC_SYNCHRONOUS_TRIGGER))
00704   {
00705     status = HAL_ERROR;
00706   }
00707   /* Check SDADC state */
00708   else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
00709           (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
00710           (hsdadc->State == HAL_SDADC_STATE_REG))
00711   {
00712     /* Store regular trigger information */
00713     hsdadc->InjectedTrigger = Trigger;
00714   }
00715   else
00716   {
00717     status = HAL_ERROR;
00718   }
00719   /* Return function status */
00720   return status;
00721 }
00722
00723 /**
00724   * @brief  This function allows to select and configure injected external trigger.
00725   * @note   This function should be called only when SDADC instance is in idle state
00726   *         (neither calibration nor regular or injected conversion ongoing)
00727   * @param  hsdadc SDADC handle.
00728   * @param  InjectedExtTrigger External trigger for injected conversions.
00729   *         This parameter can be a value of @ref SDADC_InjectedExtTrigger.
00730   * @param  ExtTriggerEdge Edge of external injected trigger.
00731   *         This parameter can be a value of @ref SDADC_ExtTriggerEdge.
00732   * @retval HAL status
00733   */
00734 HAL_StatusTypeDef HAL_SDADC_SelectInjectedExtTrigger(SDADC_HandleTypeDef *hsdadc,
00735                                                      uint32_t InjectedExtTrigger,
00736                                                      uint32_t ExtTriggerEdge)
00737 {
00738   HAL_StatusTypeDef status = HAL_OK;
00739
00740   /* Check parameters */
00741   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
00742   assert_param(IS_SDADC_EXT_INJEC_TRIG(InjectedExtTrigger));
00743   assert_param(IS_SDADC_EXT_TRIG_EDGE(ExtTriggerEdge));
00744
00745   /* Check SDADC state */
00746   if(hsdadc->State == HAL_SDADC_STATE_READY)
00747   {
00748     /* Enter init mode */
00749     if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
00750     {
00751       /* Set SDADC in error state */
00752       hsdadc->State = HAL_SDADC_STATE_ERROR;
00753       status = HAL_TIMEOUT;
00754     }
00755     else
00756     {
00757       /* Set JEXTSEL[2:0] bits in SDADC_CR2 register */
00758       hsdadc->Instance->CR2 &= ~(SDADC_CR2_JEXTSEL);
00759       hsdadc->Instance->CR2 |= InjectedExtTrigger;
00760
00761       /* Store external trigger edge information */
00762       hsdadc->ExtTriggerEdge = ExtTriggerEdge;
00763
00764       /* Exit init mode */
00765       SDADC_ExitInitMode(hsdadc);
00766     }
00767   }
00768   else
00769   {
00770     status = HAL_ERROR;
00771   }
00772   /* Return function status */
00773   return status;
00774 }
00775
00776 /**
00777   * @brief  This function allows to enable/disable delay addition for injected conversions.
00778   * @note   This function should be called only when SDADC instance is in idle state
00779   *         (neither calibration nor regular or injected conversion ongoing)
00780   * @param  hsdadc SDADC handle.
00781   * @param  InjectedDelay Enable/disable delay for injected conversions.
00782   *         This parameter can be a value of @ref SDADC_InjectedDelay.
00783   * @retval HAL status
00784   */
00785 HAL_StatusTypeDef HAL_SDADC_SelectInjectedDelay(SDADC_HandleTypeDef *hsdadc,
00786                                                 uint32_t InjectedDelay)
00787 {
00788   HAL_StatusTypeDef status = HAL_OK;
00789
00790   /* Check parameters */
00791   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
00792   assert_param(IS_SDADC_INJECTED_DELAY(InjectedDelay));
00793
00794   /* Check SDADC state */
00795   if(hsdadc->State == HAL_SDADC_STATE_READY)
00796   {
00797     /* Enter init mode */
00798     if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
00799     {
00800       /* Set SDADC in error state */
00801       hsdadc->State = HAL_SDADC_STATE_ERROR;
00802       status = HAL_TIMEOUT;
00803     }
00804     else
00805     {
00806       /* Set JDS bit in SDADC_CR2 register */
00807       hsdadc->Instance->CR2 &= ~(SDADC_CR2_JDS);
00808       hsdadc->Instance->CR2 |= InjectedDelay;
00809
00810       /* Exit init mode */
00811       SDADC_ExitInitMode(hsdadc);
00812     }
00813   }
00814   else
00815   {
00816     status = HAL_ERROR;
00817   }
00818   /* Return function status */
00819   return status;
00820 }
00821
00822 /**
00823   * @brief  This function allows to configure multimode for regular conversions.
00824   * @note   This function should not be called if regular conversion is ongoing
00825   *         and should be could only for SDADC1.
00826   * @param  hsdadc SDADC handle.
00827   * @param  MultimodeType Type of multimode for regular conversions.
00828   *         This parameter can be a value of @ref SDADC_MultimodeType.
00829   * @retval HAL status
00830   */
00831 HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc,
00832                                                    uint32_t MultimodeType)
00833 {
00834   HAL_StatusTypeDef status = HAL_OK;
00835
00836   /* Check parameters */
00837   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
00838   assert_param(IS_SDADC_MULTIMODE_TYPE(MultimodeType));
00839
00840   /* Check instance is SDADC1 */
00841   if(hsdadc->Instance != SDADC1)
00842   {
00843     status = HAL_ERROR;
00844   }
00845   /* Check SDADC state */
00846   else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
00847           (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
00848           (hsdadc->State == HAL_SDADC_STATE_INJ))
00849   {
00850     /* Store regular trigger information */
00851     hsdadc->RegularMultimode = MultimodeType;
00852   }
00853   else
00854   {
00855     status = HAL_ERROR;
00856   }
00857   /* Return function status */
00858   return status;
00859 }
00860
00861 /**
00862   * @brief  This function allows to configure multimode for injected conversions.
00863   * @note   This function should not be called if injected conversion is ongoing
00864   *         and should be could only for SDADC1.
00865   * @param  hsdadc SDADC handle.
00866   * @param  MultimodeType Type of multimode for injected conversions.
00867   *         This parameter can be a value of @ref SDADC_MultimodeType.
00868   * @retval HAL status
00869   */
00870 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc,
00871                                                            uint32_t MultimodeType)
00872 {
00873   HAL_StatusTypeDef status = HAL_OK;
00874
00875   /* Check parameters */
00876   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
00877   assert_param(IS_SDADC_MULTIMODE_TYPE(MultimodeType));
00878
00879   /* Check instance is SDADC1 */
00880   if(hsdadc->Instance != SDADC1)
00881   {
00882     status = HAL_ERROR;
00883   }
00884   /* Check SDADC state */
00885   else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
00886           (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
00887           (hsdadc->State == HAL_SDADC_STATE_REG))
00888   {
00889     /* Store regular trigger information */
00890     hsdadc->InjectedMultimode = MultimodeType;
00891   }
00892   else
00893   {
00894     status = HAL_ERROR;
00895   }
00896   /* Return function status */
00897   return status;
00898 }
00899
00900 /**
00901   * @}
00902   */
00903
00904 /** @defgroup SDADC_Exported_Functions_Group3 Input and Output operation functions
00905  *  @brief    IO operation Control functions
00906  *
00907 @verbatim
00908   ===============================================================================
00909               ##### IO operation functions #####
00910   ===============================================================================
00911     [..]  This section provides functions allowing to:
00912       (+) Start calibration.
00913       (+) Poll for the end of calibration.
00914       (+) Start calibration and enable interrupt.
00915       (+) Start conversion of regular/injected channel.
00916       (+) Poll for the end of regular/injected conversion.
00917       (+) Stop conversion of regular/injected channel.
00918       (+) Start conversion of regular/injected channel and enable interrupt.
00919       (+) Stop conversion of regular/injected channel and disable interrupt.
00920       (+) Start conversion of regular/injected channel and enable DMA transfer.
00921       (+) Stop conversion of regular/injected channel and disable DMA transfer.
00922       (+) Start multimode and enable DMA transfer for regular/injected conversion.
00923       (+) Stop multimode and disable DMA transfer for regular/injected conversion..
00924       (+) Get result of regular channel conversion.
00925       (+) Get result of injected channel conversion.
00926       (+) Get result of multimode conversion.
00927       (+) Handle SDADC interrupt request.
00928       (+) Callbacks for calibration and regular/injected conversions.
00929
00930 @endverbatim
00931   * @{
00932   */
00933
00934 /**
00935   * @brief  This function allows to start calibration in polling mode.
00936   * @note   This function should be called only when SDADC instance is in idle state
00937   *         (neither calibration nor regular or injected conversion ongoing).
00938   * @param  hsdadc SDADC handle.
00939   * @param  CalibrationSequence Calibration sequence.
00940   *         This parameter can be a value of @ref SDADC_CalibrationSequence.
00941   * @retval HAL status
00942   */
00943 HAL_StatusTypeDef HAL_SDADC_CalibrationStart(SDADC_HandleTypeDef *hsdadc,
00944                                              uint32_t CalibrationSequence)
00945 {
00946   HAL_StatusTypeDef status = HAL_OK;
00947
00948   /* Check parameters */
00949   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
00950   assert_param(IS_SDADC_CALIB_SEQUENCE(CalibrationSequence));
00951
00952   /* Check SDADC state */
00953   if(hsdadc->State == HAL_SDADC_STATE_READY)
00954   {
00955     /* Enter init mode */
00956     if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
00957     {
00958       /* Set SDADC in error state */
00959       hsdadc->State = HAL_SDADC_STATE_ERROR;
00960       status = HAL_TIMEOUT;
00961     }
00962     else
00963     {
00964       /* Set CALIBCNT[1:0] bits in SDADC_CR2 register */
00965       hsdadc->Instance->CR2 &= ~(SDADC_CR2_CALIBCNT);
00966       hsdadc->Instance->CR2 |= CalibrationSequence;
00967
00968       /* Exit init mode */
00969       SDADC_ExitInitMode(hsdadc);
00970
00971       /* Set STARTCALIB in SDADC_CR2 */
00972       hsdadc->Instance->CR2 |= SDADC_CR2_STARTCALIB;
00973
00974       /* Set SDADC in calibration state */
00975       hsdadc->State = HAL_SDADC_STATE_CALIB;
00976     }
00977   }
00978   else
00979   {
00980     status = HAL_ERROR;
00981   }
00982   /* Return function status */
00983   return status;
00984 }
00985
00986 /**
00987   * @brief  This function allows to poll for the end of calibration.
00988   * @note   This function should be called only if calibration is ongoing.
00989   * @param  hsdadc SDADC handle.
00990   * @param  Timeout Timeout value in milliseconds.
00991   * @retval HAL status
00992   */
00993 HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout)
00994 {
00995   uint32_t tickstart;
00996
00997   /* Check parameters */
00998   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
00999
01000   /* Check SDADC state */
01001   if(hsdadc->State != HAL_SDADC_STATE_CALIB)
01002   {
01003     /* Return error status */
01004     return HAL_ERROR;
01005   }
01006   else
01007   {
01008     /* Get timeout */
01009     tickstart = HAL_GetTick();
01010
01011     /* Wait EOCALF bit in SDADC_ISR register */
01012     while((hsdadc->Instance->ISR & SDADC_ISR_EOCALF) != SDADC_ISR_EOCALF)
01013     {
01014       /* Check the Timeout */
01015       if(Timeout != HAL_MAX_DELAY)
01016       {
01017         if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
01018         {
01019           /* Return timeout status */
01020           return HAL_TIMEOUT;
01021         }
01022       }
01023     }
01024     /* Set CLREOCALF bit in SDADC_CLRISR register */
01025     hsdadc->Instance->CLRISR |= SDADC_ISR_CLREOCALF;
01026
01027     /* Set SDADC in ready state */
01028     hsdadc->State = HAL_SDADC_STATE_READY;
01029
01030     /* Return function status */
01031     return HAL_OK;
01032   }
01033 }
01034
01035 /**
01036   * @brief  This function allows to start calibration in interrupt mode.
01037   * @note   This function should be called only when SDADC instance is in idle state
01038   *         (neither calibration nor regular or injected conversion ongoing).
01039   * @param  hsdadc SDADC handle.
01040   * @param  CalibrationSequence Calibration sequence.
01041   *         This parameter can be a value of @ref SDADC_CalibrationSequence.
01042   * @retval HAL status
01043   */
01044 HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT(SDADC_HandleTypeDef *hsdadc,
01045                                                 uint32_t CalibrationSequence)
01046 {
01047   HAL_StatusTypeDef status = HAL_OK;
01048
01049   /* Check parameters */
01050   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01051   assert_param(IS_SDADC_CALIB_SEQUENCE(CalibrationSequence));
01052
01053   /* Check SDADC state */
01054   if(hsdadc->State == HAL_SDADC_STATE_READY)
01055   {
01056     /* Enter init mode */
01057     if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
01058     {
01059       /* Set SDADC in error state */
01060       hsdadc->State = HAL_SDADC_STATE_ERROR;
01061       status = HAL_TIMEOUT;
01062     }
01063     else
01064     {
01065       /* Set CALIBCNT[1:0] bits in SDADC_CR2 register */
01066       hsdadc->Instance->CR2 &= ~(SDADC_CR2_CALIBCNT);
01067       hsdadc->Instance->CR2 |= CalibrationSequence;
01068
01069       /* Exit init mode */
01070       SDADC_ExitInitMode(hsdadc);
01071
01072       /* Set EOCALIE bit in SDADC_CR1 register */
01073       hsdadc->Instance->CR1 |= SDADC_CR1_EOCALIE;
01074
01075       /* Set STARTCALIB in SDADC_CR2 */
01076       hsdadc->Instance->CR2 |= SDADC_CR2_STARTCALIB;
01077
01078       /* Set SDADC in calibration state */
01079       hsdadc->State = HAL_SDADC_STATE_CALIB;
01080     }
01081   }
01082   else
01083   {
01084     status = HAL_ERROR;
01085   }
01086   /* Return function status */
01087   return status;
01088 }
01089
01090 /**
01091   * @brief  This function allows to start regular conversion in polling mode.
01092   * @note   This function should be called only when SDADC instance is in idle state
01093   *         or if injected conversion is ongoing.
01094   * @param  hsdadc SDADC handle.
01095   * @retval HAL status
01096   */
01097 HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc)
01098 {
01099   HAL_StatusTypeDef status = HAL_OK;
01100
01101   /* Check parameters */
01102   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01103
01104   /* Check SDADC state */
01105   if((hsdadc->State == HAL_SDADC_STATE_READY) || \
01106      (hsdadc->State == HAL_SDADC_STATE_INJ))
01107   {
01108     /* Start regular conversion */
01109     status = SDADC_RegConvStart(hsdadc);
01110   }
01111   else
01112   {
01113     status = HAL_ERROR;
01114   }
01115   /* Return function status */
01116   return status;
01117 }
01118
01119 /**
01120   * @brief  This function allows to poll for the end of regular conversion.
01121   * @note   This function should be called only if regular conversion is ongoing.
01122   * @param  hsdadc SDADC handle.
01123   * @param  Timeout Timeout value in milliseconds.
01124   * @retval HAL status
01125   */
01126 HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout)
01127 {
01128   uint32_t tickstart;
01129
01130   /* Check parameters */
01131   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01132
01133   /* Check SDADC state */
01134   if((hsdadc->State != HAL_SDADC_STATE_REG) && \
01135      (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
01136   {
01137     /* Return error status */
01138     return HAL_ERROR;
01139   }
01140   else
01141   {
01142     /* Get timeout */
01143     tickstart = HAL_GetTick();
01144
01145     /* Wait REOCF bit in SDADC_ISR register */
01146     while((hsdadc->Instance->ISR & SDADC_ISR_REOCF) != SDADC_ISR_REOCF)
01147     {
01148       /* Check the Timeout */
01149       if(Timeout != HAL_MAX_DELAY)
01150       {
01151         if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
01152         {
01153           /* Return timeout status */
01154           return HAL_TIMEOUT;
01155         }
01156       }
01157     }
01158     /* Check if overrun occurs */
01159     if((hsdadc->Instance->ISR & SDADC_ISR_ROVRF) == SDADC_ISR_ROVRF)
01160     {
01161       /* Update error code and call error callback */
01162       hsdadc->ErrorCode = SDADC_ERROR_REGULAR_OVERRUN;
01163       HAL_SDADC_ErrorCallback(hsdadc);
01164
01165       /* Set CLRROVRF bit in SDADC_CLRISR register */
01166       hsdadc->Instance->CLRISR |= SDADC_ISR_CLRROVRF;
01167     }
01168     /* Update SDADC state only if not continuous conversion and SW trigger */
01169     if((hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
01170        (hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER))
01171     {
01172       hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
01173                       HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
01174     }
01175     /* Return function status */
01176     return HAL_OK;
01177   }
01178 }
01179
01180 /**
01181   * @brief  This function allows to stop regular conversion in polling mode.
01182   * @note   This function should be called only if regular conversion is ongoing.
01183   * @param  hsdadc SDADC handle.
01184   * @retval HAL status
01185   */
01186 HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc)
01187 {
01188   HAL_StatusTypeDef status = HAL_OK;
01189
01190   /* Check parameters */
01191   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01192
01193   /* Check SDADC state */
01194   if((hsdadc->State != HAL_SDADC_STATE_REG) && \
01195      (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
01196   {
01197     /* Return error status */
01198     status = HAL_ERROR;
01199   }
01200   else
01201   {
01202     /* Stop regular conversion */
01203     status = SDADC_RegConvStop(hsdadc);
01204   }
01205   /* Return function status */
01206   return status;
01207 }
01208
01209 /**
01210   * @brief  This function allows to start regular conversion in interrupt mode.
01211   * @note   This function should be called only when SDADC instance is in idle state
01212   *         or if injected conversion is ongoing.
01213   * @param  hsdadc SDADC handle.
01214   * @retval HAL status
01215   */
01216 HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc)
01217 {
01218   HAL_StatusTypeDef status = HAL_OK;
01219
01220   /* Check parameters */
01221   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01222
01223   /* Check SDADC state */
01224   if((hsdadc->State == HAL_SDADC_STATE_READY) || \
01225      (hsdadc->State == HAL_SDADC_STATE_INJ))
01226   {
01227     /* Set REOCIE and ROVRIE bits in SDADC_CR1 register */
01228     hsdadc->Instance->CR1 |= (uint32_t) (SDADC_CR1_REOCIE | SDADC_CR1_ROVRIE);
01229
01230     /* Start regular conversion */
01231     status = SDADC_RegConvStart(hsdadc);
01232   }
01233   else
01234   {
01235     status = HAL_ERROR;
01236   }
01237   /* Return function status */
01238   return status;
01239 }
01240
01241 /**
01242   * @brief  This function allows to stop regular conversion in interrupt mode.
01243   * @note   This function should be called only if regular conversion is ongoing.
01244   * @param  hsdadc SDADC handle.
01245   * @retval HAL status
01246   */
01247 HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc)
01248 {
01249   HAL_StatusTypeDef status = HAL_OK;
01250
01251   /* Check parameters */
01252   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01253
01254   /* Check SDADC state */
01255   if((hsdadc->State != HAL_SDADC_STATE_REG) && \
01256      (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
01257   {
01258     /* Return error status */
01259     status = HAL_ERROR;
01260   }
01261   else
01262   {
01263     /* Clear REOCIE and ROVRIE bits in SDADC_CR1 register */
01264     hsdadc->Instance->CR1 &= (uint32_t) ~(SDADC_CR1_REOCIE | SDADC_CR1_ROVRIE);
01265
01266     /* Stop regular conversion */
01267     status = SDADC_RegConvStop(hsdadc);
01268   }
01269   /* Return function status */
01270   return status;
01271 }
01272
01273 /**
01274   * @brief  This function allows to start regular conversion in DMA mode.
01275   * @note   This function should be called only when SDADC instance is in idle state
01276   *         or if injected conversion is ongoing.
01277   * @param  hsdadc SDADC handle.
01278   * @param  pData The destination buffer address.
01279   * @param  Length The length of data to be transferred from SDADC peripheral to memory.
01280   * @retval HAL status
01281   */
01282 HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData,
01283                                       uint32_t Length)
01284 {
01285   HAL_StatusTypeDef status = HAL_OK;
01286
01287   /* Check parameters */
01288   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01289   assert_param(pData != NULL);
01290   assert_param(Length != 0U);
01291
01292   /* Check that DMA is not enabled for injected conversion */
01293   if((hsdadc->Instance->CR1 & SDADC_CR1_JDMAEN) == SDADC_CR1_JDMAEN)
01294   {
01295     status = HAL_ERROR;
01296   }
01297   /* Check parameters compatibility */
01298   else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
01299           (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
01300           (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
01301           (Length != 1U))
01302   {
01303     status = HAL_ERROR;
01304   }
01305   else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
01306           (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
01307           (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
01308   {
01309     status = HAL_ERROR;
01310   }
01311   /* Check SDADC state */
01312   else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
01313           (hsdadc->State == HAL_SDADC_STATE_INJ))
01314   {
01315     /* Set callbacks on DMA handler */
01316     hsdadc->hdma->XferCpltCallback = SDADC_DMARegularConvCplt;
01317     hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
01318     if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
01319     {
01320       hsdadc->hdma->XferHalfCpltCallback = SDADC_DMARegularHalfConvCplt;
01321     }
01322
01323     /* Set RDMAEN bit in SDADC_CR1 register */
01324     hsdadc->Instance->CR1 |= SDADC_CR1_RDMAEN;
01325
01326     /* Start DMA in interrupt mode */
01327     if(HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATAR, \
01328                         (uint32_t) pData, Length) != HAL_OK)
01329     {
01330       /* Set SDADC in error state */
01331       hsdadc->State = HAL_SDADC_STATE_ERROR;
01332       status = HAL_ERROR;
01333     }
01334     else
01335     {
01336       /* Start regular conversion */
01337       status = SDADC_RegConvStart(hsdadc);
01338     }
01339   }
01340   else
01341   {
01342     status = HAL_ERROR;
01343   }
01344   /* Return function status */
01345   return status;
01346 }
01347
01348 /**
01349   * @brief  This function allows to stop regular conversion in DMA mode.
01350   * @note   This function should be called only if regular conversion is ongoing.
01351   * @param  hsdadc SDADC handle.
01352   * @retval HAL status
01353   */
01354 HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc)
01355 {
01356   HAL_StatusTypeDef status = HAL_OK;
01357
01358   /* Check parameters */
01359   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01360
01361   /* Check SDADC state */
01362   if((hsdadc->State != HAL_SDADC_STATE_REG) && \
01363      (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
01364   {
01365     /* Return error status */
01366     status = HAL_ERROR;
01367   }
01368   else
01369   {
01370     /* Clear RDMAEN bit in SDADC_CR1 register */
01371     hsdadc->Instance->CR1 &= ~(SDADC_CR1_RDMAEN);
01372
01373     /* Stop current DMA transfer */
01374     if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
01375     {
01376       /* Set SDADC in error state */
01377       hsdadc->State = HAL_SDADC_STATE_ERROR;
01378       status = HAL_ERROR;
01379     }
01380     else
01381     {
01382       /* Stop regular conversion */
01383       status = SDADC_RegConvStop(hsdadc);
01384     }
01385   }
01386   /* Return function status */
01387   return status;
01388 }
01389
01390 /**
01391   * @brief  This function allows to get regular conversion value.
01392   * @param  hsdadc SDADC handle.
01393   * @retval Regular conversion value
01394   */
01395 uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc)
01396 {
01397   /* Check parameters */
01398   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01399
01400   /* Return regular conversion value */
01401   return hsdadc->Instance->RDATAR;
01402 }
01403
01404 /**
01405   * @brief  This function allows to start injected conversion in polling mode.
01406   * @note   This function should be called only when SDADC instance is in idle state
01407   *         or if regular conversion is ongoing.
01408   * @param  hsdadc SDADC handle.
01409   * @retval HAL status
01410   */
01411 HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc)
01412 {
01413   HAL_StatusTypeDef status = HAL_OK;
01414
01415   /* Check parameters */
01416   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01417
01418   /* Check SDADC state */
01419   if((hsdadc->State == HAL_SDADC_STATE_READY) || \
01420      (hsdadc->State == HAL_SDADC_STATE_REG))
01421   {
01422     /* Start injected conversion */
01423     status = SDADC_InjConvStart(hsdadc);
01424   }
01425   else
01426   {
01427     status = HAL_ERROR;
01428   }
01429   /* Return function status */
01430   return status;
01431 }
01432
01433 /**
01434   * @brief  This function allows to poll for the end of injected conversion.
01435   * @note   This function should be called only if injected conversion is ongoing.
01436   * @param  hsdadc SDADC handle.
01437   * @param  Timeout Timeout value in milliseconds.
01438   * @retval HAL status
01439   */
01440 HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdadc,
01441                                                       uint32_t Timeout)
01442 {
01443   uint32_t tickstart;
01444
01445   /* Check parameters */
01446   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01447
01448   /* Check SDADC state */
01449   if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
01450      (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
01451   {
01452     /* Return error status */
01453     return HAL_ERROR;
01454   }
01455   else
01456   {
01457     /* Get timeout */
01458     tickstart = HAL_GetTick();
01459
01460     /* Wait JEOCF bit in SDADC_ISR register */
01461     while((hsdadc->Instance->ISR & SDADC_ISR_JEOCF) != SDADC_ISR_JEOCF)
01462     {
01463       /* Check the Timeout */
01464       if(Timeout != HAL_MAX_DELAY)
01465       {
01466         if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
01467         {
01468           /* Return timeout status */
01469           return HAL_TIMEOUT;
01470         }
01471       }
01472     }
01473     /* Check if overrun occurs */
01474     if((hsdadc->Instance->ISR & SDADC_ISR_JOVRF) == SDADC_ISR_JOVRF)
01475     {
01476       /* Update error code and call error callback */
01477       hsdadc->ErrorCode = SDADC_ERROR_INJECTED_OVERRUN;
01478       HAL_SDADC_ErrorCallback(hsdadc);
01479
01480       /* Set CLRJOVRF bit in SDADC_CLRISR register */
01481       hsdadc->Instance->CLRISR |= SDADC_ISR_CLRJOVRF;
01482     }
01483     /* Update remaining injected conversions */
01484     hsdadc->InjConvRemaining--;
01485     if(hsdadc->InjConvRemaining == 0U)
01486     {
01487       /* end of injected sequence, reset the value */
01488       hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
01489     }
01490
01491     /* Update SDADC state only if not continuous conversion, SW trigger */
01492     /* and end of injected sequence */
01493     if((hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
01494        (hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
01495        (hsdadc->InjConvRemaining == hsdadc->InjectedChannelsNbr))
01496     {
01497       hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
01498                       HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
01499     }
01500     /* Return function status */
01501     return HAL_OK;
01502   }
01503 }
01504
01505 /**
01506   * @brief  This function allows to stop injected conversion in polling mode.
01507   * @note   This function should be called only if injected conversion is ongoing.
01508   * @param  hsdadc SDADC handle.
01509   * @retval HAL status
01510   */
01511 HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc)
01512 {
01513   HAL_StatusTypeDef status = HAL_OK;
01514
01515   /* Check parameters */
01516   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01517
01518   /* Check SDADC state */
01519   if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
01520      (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
01521   {
01522     /* Return error status */
01523     status = HAL_ERROR;
01524   }
01525   else
01526   {
01527     /* Stop injected conversion */
01528     status = SDADC_InjConvStop(hsdadc);
01529   }
01530   /* Return function status */
01531   return status;
01532 }
01533
01534 /**
01535   * @brief  This function allows to start injected conversion in interrupt mode.
01536   * @note   This function should be called only when SDADC instance is in idle state
01537   *         or if regular conversion is ongoing.
01538   * @param  hsdadc SDADC handle.
01539   * @retval HAL status
01540   */
01541 HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc)
01542 {
01543   HAL_StatusTypeDef status = HAL_OK;
01544
01545   /* Check parameters */
01546   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01547
01548   /* Check SDADC state */
01549   if((hsdadc->State == HAL_SDADC_STATE_READY) || \
01550      (hsdadc->State == HAL_SDADC_STATE_REG))
01551   {
01552     /* Set JEOCIE and JOVRIE bits in SDADC_CR1 register */
01553     hsdadc->Instance->CR1 |= (uint32_t) (SDADC_CR1_JEOCIE | SDADC_CR1_JOVRIE);
01554
01555     /* Start injected conversion */
01556     status = SDADC_InjConvStart(hsdadc);
01557   }
01558   else
01559   {
01560     status = HAL_ERROR;
01561   }
01562   /* Return function status */
01563   return status;
01564 }
01565
01566 /**
01567   * @brief  This function allows to stop injected conversion in interrupt mode.
01568   * @note   This function should be called only if injected conversion is ongoing.
01569   * @param  hsdadc SDADC handle.
01570   * @retval HAL status
01571   */
01572 HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc)
01573 {
01574   HAL_StatusTypeDef status = HAL_OK;
01575
01576   /* Check parameters */
01577   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01578
01579   /* Check SDADC state */
01580   if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
01581      (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
01582   {
01583     /* Return error status */
01584     status = HAL_ERROR;
01585   }
01586   else
01587   {
01588     /* Clear JEOCIE and JOVRIE bits in SDADC_CR1 register */
01589     hsdadc->Instance->CR1 &= (uint32_t) ~(SDADC_CR1_JEOCIE | SDADC_CR1_JOVRIE);
01590
01591     /* Stop injected conversion */
01592     status = SDADC_InjConvStop(hsdadc);
01593   }
01594   /* Return function status */
01595   return status;
01596 }
01597
01598 /**
01599   * @brief  This function allows to start injected conversion in DMA mode.
01600   * @note   This function should be called only when SDADC instance is in idle state
01601   *         or if regular conversion is ongoing.
01602   * @param  hsdadc SDADC handle.
01603   * @param  pData The destination buffer address.
01604   * @param  Length The length of data to be transferred from SDADC peripheral to memory.
01605   * @retval HAL status
01606   */
01607 HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData,
01608                                               uint32_t Length)
01609 {
01610   HAL_StatusTypeDef status = HAL_OK;
01611
01612   /* Check parameters */
01613   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01614   assert_param(pData != NULL);
01615   assert_param(Length != 0U);
01616
01617   /* Check that DMA is not enabled for regular conversion */
01618   if((hsdadc->Instance->CR1 & SDADC_CR1_RDMAEN) == SDADC_CR1_RDMAEN)
01619   {
01620     status = HAL_ERROR;
01621   }
01622   /* Check parameters compatibility */
01623   else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
01624           (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
01625           (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
01626           (Length > hsdadc->InjectedChannelsNbr))
01627   {
01628     status = HAL_ERROR;
01629   }
01630   else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
01631           (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
01632           (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
01633   {
01634     status = HAL_ERROR;
01635   }
01636   /* Check SDADC state */
01637   else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
01638           (hsdadc->State == HAL_SDADC_STATE_REG))
01639   {
01640     /* Set callbacks on DMA handler */
01641     hsdadc->hdma->XferCpltCallback = SDADC_DMAInjectedConvCplt;
01642     hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
01643     if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
01644     {
01645       hsdadc->hdma->XferHalfCpltCallback = SDADC_DMAInjectedHalfConvCplt;
01646     }
01647
01648     /* Set JDMAEN bit in SDADC_CR1 register */
01649     hsdadc->Instance->CR1 |= SDADC_CR1_JDMAEN;
01650
01651     /* Start DMA in interrupt mode */
01652     if(HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATAR, \
01653                         (uint32_t) pData, Length) != HAL_OK)
01654     {
01655       /* Set SDADC in error state */
01656       hsdadc->State = HAL_SDADC_STATE_ERROR;
01657       status = HAL_ERROR;
01658     }
01659     else
01660     {
01661       /* Start injected conversion */
01662       status = SDADC_InjConvStart(hsdadc);
01663     }
01664   }
01665   else
01666   {
01667     status = HAL_ERROR;
01668   }
01669   /* Return function status */
01670   return status;
01671 }
01672
01673 /**
01674   * @brief  This function allows to stop injected conversion in DMA mode.
01675   * @note   This function should be called only if injected conversion is ongoing.
01676   * @param  hsdadc SDADC handle.
01677   * @retval HAL status
01678   */
01679 HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc)
01680 {
01681   HAL_StatusTypeDef status = HAL_OK;
01682
01683   /* Check parameters */
01684   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01685
01686   /* Check SDADC state */
01687   if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
01688      (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
01689   {
01690     /* Return error status */
01691     status = HAL_ERROR;
01692   }
01693   else
01694   {
01695     /* Clear JDMAEN bit in SDADC_CR1 register */
01696     hsdadc->Instance->CR1 &= ~(SDADC_CR1_JDMAEN);
01697
01698     /* Stop current DMA transfer */
01699     if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
01700     {
01701       /* Set SDADC in error state */
01702       hsdadc->State = HAL_SDADC_STATE_ERROR;
01703       status = HAL_ERROR;
01704     }
01705     else
01706     {
01707       /* Stop injected conversion */
01708       status = SDADC_InjConvStop(hsdadc);
01709     }
01710   }
01711   /* Return function status */
01712   return status;
01713 }
01714
01715 /**
01716   * @brief  This function allows to get injected conversion value.
01717   * @param  hsdadc SDADC handle.
01718   * @param  Channel Corresponding channel of injected conversion.
01719   * @retval Injected conversion value
01720   */
01721 uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel)
01722 {
01723   uint32_t value = 0U;
01724
01725   /* Check parameters */
01726   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01727   assert_param(Channel != NULL);
01728
01729   /* Read SDADC_JDATAR register and extract channel and conversion value */
01730   value = hsdadc->Instance->JDATAR;
01731   *Channel = ((value & SDADC_JDATAR_JDATACH) >> SDADC_JDATAR_CH_OFFSET);
01732   value &= SDADC_JDATAR_JDATA;
01733
01734   /* Return injected conversion value */
01735   return value;
01736 }
01737
01738 /**
01739   * @brief  This function allows to start multimode regular conversions in DMA mode.
01740   * @note   This function should be called only when SDADC instance is in idle state
01741   *         or if injected conversion is ongoing.
01742   * @param  hsdadc SDADC handle.
01743   * @param  pData The destination buffer address.
01744   * @param  Length The length of data to be transferred from SDADC peripheral to memory.
01745   * @retval HAL status
01746   */
01747 HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData,
01748                                                uint32_t Length)
01749 {
01750   HAL_StatusTypeDef status = HAL_OK;
01751
01752   /* Check parameters */
01753   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01754   assert_param(pData != NULL);
01755   assert_param(Length != 0U);
01756
01757   /* Check instance is SDADC1 */
01758   if(hsdadc->Instance != SDADC1)
01759   {
01760     status = HAL_ERROR;
01761   }
01762   /* Check that DMA is not enabled for injected conversion */
01763   else if((hsdadc->Instance->CR1 & SDADC_CR1_JDMAEN) == SDADC_CR1_JDMAEN)
01764   {
01765     status = HAL_ERROR;
01766   }
01767   /* Check parameters compatibility */
01768   else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
01769           (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
01770           (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
01771           (Length != 1U))
01772   {
01773     status = HAL_ERROR;
01774   }
01775   else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
01776           (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
01777           (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
01778   {
01779     status = HAL_ERROR;
01780   }
01781   /* Check SDADC state */
01782   else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
01783           (hsdadc->State == HAL_SDADC_STATE_INJ))
01784   {
01785     /* Set callbacks on DMA handler */
01786     hsdadc->hdma->XferCpltCallback = SDADC_DMARegularConvCplt;
01787     hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
01788     if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
01789     {
01790       hsdadc->hdma->XferHalfCpltCallback = SDADC_DMARegularHalfConvCplt;
01791     }
01792     /* Set RDMAEN bit in SDADC_CR1 register */
01793     hsdadc->Instance->CR1 |= SDADC_CR1_RDMAEN;
01794
01795     /* Start DMA in interrupt mode */
01796     if(hsdadc->RegularMultimode == SDADC_MULTIMODE_SDADC1_SDADC2)
01797     {
01798       status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATA12R, \
01799                                 (uint32_t) pData, Length);
01800     }
01801     else
01802     {
01803       status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATA13R, \
01804                                 (uint32_t) pData, Length);
01805     }
01806     if(status != HAL_OK)
01807     {
01808       /* Set SDADC in error state */
01809       hsdadc->State = HAL_SDADC_STATE_ERROR;
01810       status = HAL_ERROR;
01811     }
01812     else
01813     {
01814       /* Start regular conversion */
01815       status = SDADC_RegConvStart(hsdadc);
01816     }
01817   }
01818   else
01819   {
01820     status = HAL_ERROR;
01821   }
01822   /* Return function status */
01823   return status;
01824 }
01825
01826 /**
01827   * @brief  This function allows to stop multimode regular conversions in DMA mode.
01828   * @note   This function should be called only if regular conversion is ongoing.
01829   * @param  hsdadc SDADC handle.
01830   * @retval HAL status
01831   */
01832 HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc)
01833 {
01834   HAL_StatusTypeDef status = HAL_OK;
01835
01836   /* Check parameters */
01837   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01838
01839   /* Check instance is SDADC1 */
01840   if(hsdadc->Instance != SDADC1)
01841   {
01842     status = HAL_ERROR;
01843   }
01844   /* Check SDADC state */
01845   else if((hsdadc->State != HAL_SDADC_STATE_REG) && \
01846           (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
01847   {
01848     /* Return error status */
01849     status = HAL_ERROR;
01850   }
01851   else
01852   {
01853     /* Clear RDMAEN bit in SDADC_CR1 register */
01854     hsdadc->Instance->CR1 &= ~(SDADC_CR1_RDMAEN);
01855
01856     /* Stop current DMA transfer */
01857     if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
01858     {
01859       /* Set SDADC in error state */
01860       hsdadc->State = HAL_SDADC_STATE_ERROR;
01861       status = HAL_ERROR;
01862     }
01863     else
01864     {
01865       /* Stop regular conversion */
01866       status = SDADC_RegConvStop(hsdadc);
01867     }
01868   }
01869   /* Return function status */
01870   return status;
01871 }
01872
01873 /**
01874   * @brief  This function allows to get multimode regular conversion value.
01875   * @param  hsdadc SDADC handle.
01876   * @retval Multimode regular conversion value
01877   */
01878 uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
01879 {
01880   uint32_t value = 0U;
01881
01882   /* Check parameters and check instance is SDADC1 */
01883   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01884   assert_param(hsdadc->Instance == SDADC1);
01885
01886   /* read multimode regular value */
01887   value = (hsdadc->RegularMultimode == SDADC_MULTIMODE_SDADC1_SDADC2) ? \
01888           hsdadc->Instance->RDATA12R : hsdadc->Instance->RDATA13R;
01889
01890   /* Return multimode regular conversions value */
01891   return value;
01892 }
01893
01894 /**
01895   * @brief  This function allows to start multimode injected conversions in DMA mode.
01896   * @note   This function should be called only when SDADC instance is in idle state
01897   *         or if regular conversion is ongoing.
01898   * @param  hsdadc SDADC handle.
01899   * @param  pData The destination buffer address.
01900   * @param  Length The length of data to be transferred from SDADC peripheral to memory.
01901   * @retval HAL status
01902   */
01903 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc,
01904                                                        uint32_t* pData, uint32_t Length)
01905 {
01906   HAL_StatusTypeDef status = HAL_OK;
01907
01908   /* Check parameters */
01909   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01910   assert_param(pData != NULL);
01911   assert_param(Length != 0U);
01912
01913   /* Check instance is SDADC1 */
01914   if(hsdadc->Instance != SDADC1)
01915   {
01916     status = HAL_ERROR;
01917   }
01918   /* Check that DMA is not enabled for regular conversion */
01919   else if((hsdadc->Instance->CR1 & SDADC_CR1_RDMAEN) == SDADC_CR1_RDMAEN)
01920   {
01921     status = HAL_ERROR;
01922   }
01923   /* Check parameters compatibility */
01924   else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
01925           (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
01926           (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
01927           (Length > (hsdadc->InjectedChannelsNbr << 1U)))
01928   {
01929     status = HAL_ERROR;
01930   }
01931   else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
01932           (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
01933           (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
01934   {
01935     status = HAL_ERROR;
01936   }
01937   /* Check SDADC state */
01938   else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
01939           (hsdadc->State == HAL_SDADC_STATE_REG))
01940   {
01941     /* Set callbacks on DMA handler */
01942     hsdadc->hdma->XferCpltCallback = SDADC_DMAInjectedConvCplt;
01943     hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
01944     if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
01945     {
01946       hsdadc->hdma->XferHalfCpltCallback = SDADC_DMAInjectedHalfConvCplt;
01947     }
01948     /* Set JDMAEN bit in SDADC_CR1 register */
01949     hsdadc->Instance->CR1 |= SDADC_CR1_JDMAEN;
01950
01951     /* Start DMA in interrupt mode */
01952     if(hsdadc->InjectedMultimode == SDADC_MULTIMODE_SDADC1_SDADC2)
01953     {
01954       status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATA12R, \
01955                                 (uint32_t) pData, Length);
01956     }
01957     else
01958     {
01959       status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATA13R, \
01960                                 (uint32_t) pData, Length);
01961     }
01962     if(status != HAL_OK)
01963     {
01964       /* Set SDADC in error state */
01965       hsdadc->State = HAL_SDADC_STATE_ERROR;
01966       status = HAL_ERROR;
01967     }
01968     else
01969     {
01970       /* Start injected conversion */
01971       status = SDADC_InjConvStart(hsdadc);
01972     }
01973   }
01974   else
01975   {
01976     status = HAL_ERROR;
01977   }
01978   /* Return function status */
01979   return status;
01980 }
01981
01982 /**
01983   * @brief  This function allows to stop multimode injected conversions in DMA mode.
01984   * @note   This function should be called only if injected conversion is ongoing.
01985   * @param  hsdadc SDADC handle.
01986   * @retval HAL status
01987   */
01988 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc)
01989 {
01990   HAL_StatusTypeDef status = HAL_OK;
01991
01992   /* Check parameters */
01993   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
01994
01995   /* Check instance is SDADC1 */
01996   if(hsdadc->Instance != SDADC1)
01997   {
01998     status = HAL_ERROR;
01999   }
02000   /* Check SDADC state */
02001   else if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
02002           (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
02003   {
02004     /* Return error status */
02005     status = HAL_ERROR;
02006   }
02007   else
02008   {
02009     /* Clear JDMAEN bit in SDADC_CR1 register */
02010     hsdadc->Instance->CR1 &= ~(SDADC_CR1_JDMAEN);
02011
02012     /* Stop current DMA transfer */
02013     if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
02014     {
02015       /* Set SDADC in error state */
02016       hsdadc->State = HAL_SDADC_STATE_ERROR;
02017       status = HAL_ERROR;
02018     }
02019     else
02020     {
02021       /* Stop injected conversion */
02022       status = SDADC_InjConvStop(hsdadc);
02023     }
02024   }
02025   /* Return function status */
02026   return status;
02027 }
02028
02029 /**
02030   * @brief  This function allows to get multimode injected conversion value.
02031   * @param  hsdadc SDADC handle.
02032   * @retval Multimode injected conversion value
02033   */
02034 uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
02035 {
02036   uint32_t value = 0U;
02037
02038   /* Check parameters and check instance is SDADC1 */
02039   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
02040   assert_param(hsdadc->Instance == SDADC1);
02041
02042   /* read multimode injected value */
02043   value = (hsdadc->InjectedMultimode == SDADC_MULTIMODE_SDADC1_SDADC2) ? \
02044           hsdadc->Instance->JDATA12R : hsdadc->Instance->JDATA13R;
02045
02046   /* Return multimode injected conversions value */
02047   return value;
02048 }
02049
02050 /**
02051   * @brief  This function handles the SDADC interrupts.
02052   * @param  hsdadc SDADC handle.
02053   * @retval None
02054   */
02055 void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc)
02056 {
02057   /* Check if end of regular conversion */
02058   if(((hsdadc->Instance->ISR & SDADC_ISR_REOCF) == SDADC_ISR_REOCF) && \
02059           ((hsdadc->Instance->CR1 & SDADC_CR1_REOCIE) == SDADC_CR1_REOCIE))
02060   {
02061     /* Call regular conversion complete callback */
02062     HAL_SDADC_ConvCpltCallback(hsdadc);
02063
02064     /* End of conversion if mode is not continuous and software trigger */
02065     if((hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
02066        (hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER))
02067     {
02068       /* Clear REOCIE and ROVRIE bits in SDADC_CR1 register */
02069       hsdadc->Instance->CR1 &= ~(SDADC_CR1_REOCIE | SDADC_CR1_ROVRIE);
02070
02071       /* Update SDADC state */
02072       hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
02073                       HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
02074     }
02075   }
02076   /* Check if end of injected conversion */
02077   else if(((hsdadc->Instance->ISR & SDADC_ISR_JEOCF) == SDADC_ISR_JEOCF) && \
02078           ((hsdadc->Instance->CR1 & SDADC_CR1_JEOCIE) == SDADC_CR1_JEOCIE))
02079   {
02080     /* Call injected conversion complete callback */
02081     HAL_SDADC_InjectedConvCpltCallback(hsdadc);
02082
02083     /* Update remaining injected conversions */
02084     hsdadc->InjConvRemaining--;
02085     if(hsdadc->InjConvRemaining ==0U)
02086     {
02087       /* end of injected sequence, reset the value */
02088       hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
02089     }
02090     /* End of conversion if mode is not continuous, software trigger */
02091     /* and end of injected sequence */
02092     if((hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
02093        (hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
02094        (hsdadc->InjConvRemaining == hsdadc->InjectedChannelsNbr))
02095     {
02096       /* Clear JEOCIE and JOVRIE bits in SDADC_CR1 register */
02097       hsdadc->Instance->CR1 &= ~(SDADC_CR1_JEOCIE | SDADC_CR1_JOVRIE);
02098
02099       /* Update SDADC state */
02100       hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
02101                       HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
02102     }
02103   }
02104   /* Check if end of calibration */
02105   else if(((hsdadc->Instance->ISR & SDADC_ISR_EOCALF) == SDADC_ISR_EOCALF) && \
02106           ((hsdadc->Instance->CR1 & SDADC_CR1_EOCALIE) == SDADC_CR1_EOCALIE))
02107   {
02108     /* Clear EOCALIE bit in SDADC_CR1 register */
02109     hsdadc->Instance->CR1 &= ~(SDADC_CR1_EOCALIE);
02110
02111     /* Set CLREOCALF bit in SDADC_CLRISR register */
02112     hsdadc->Instance->CLRISR |= SDADC_ISR_CLREOCALF;
02113
02114     /* Call calibration callback */
02115     HAL_SDADC_CalibrationCpltCallback(hsdadc);
02116
02117     /* Update SDADC state */
02118     hsdadc->State = HAL_SDADC_STATE_READY;
02119   }
02120   /* Check if overrun occurs during regular conversion */
02121   else if(((hsdadc->Instance->ISR & SDADC_ISR_ROVRF) == SDADC_ISR_ROVRF) && \
02122           ((hsdadc->Instance->CR1 & SDADC_CR1_ROVRIE) == SDADC_CR1_ROVRIE))
02123   {
02124     /* Set CLRROVRF bit in SDADC_CLRISR register */
02125     hsdadc->Instance->CLRISR |= SDADC_ISR_CLRROVRF;
02126
02127     /* Update error code */
02128     hsdadc->ErrorCode = SDADC_ERROR_REGULAR_OVERRUN;
02129
02130     /* Call error callback */
02131     HAL_SDADC_ErrorCallback(hsdadc);
02132   }
02133   /* Check if overrun occurs during injected conversion */
02134   else if(((hsdadc->Instance->ISR & SDADC_ISR_JOVRF) == SDADC_ISR_JOVRF) && \
02135           ((hsdadc->Instance->CR1 & SDADC_CR1_JOVRIE) == SDADC_CR1_JOVRIE))
02136   {
02137     /* Set CLRJOVRF bit in SDADC_CLRISR register */
02138     hsdadc->Instance->CLRISR |= SDADC_ISR_CLRJOVRF;
02139
02140     /* Update error code */
02141     hsdadc->ErrorCode = SDADC_ERROR_INJECTED_OVERRUN;
02142
02143     /* Call error callback */
02144     HAL_SDADC_ErrorCallback(hsdadc);
02145   }
02146   else
02147   {
02148     /* No additional IRQ source */
02149   }
02150
02151   return;
02152 }
02153
02154 /**
02155   * @brief  Calibration complete callback.
02156   * @param  hsdadc SDADC handle.
02157   * @retval None
02158   */
02159 __weak void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc)
02160 {
02161   /* Prevent unused argument(s) compilation warning */
02162   UNUSED(hsdadc);
02163
02164   /* NOTE : This function should not be modified, when the callback is needed,
02165             the HAL_SDADC_CalibrationCpltCallback could be implemented in the user file
02166    */
02167 }
02168
02169 /**
02170   * @brief  Half regular conversion complete callback.
02171   * @param  hsdadc SDADC handle.
02172   * @retval None
02173   */
02174 __weak void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
02175 {
02176   /* Prevent unused argument(s) compilation warning */
02177   UNUSED(hsdadc);
02178
02179   /* NOTE : This function should not be modified, when the callback is needed,
02180             the HAL_SDADC_ConvHalfCpltCallback could be implemented in the user file
02181    */
02182 }
02183
02184 /**
02185   * @brief  Regular conversion complete callback.
02186   * @note   In interrupt mode, user has to read conversion value in this function
02187             using HAL_SDADC_GetValue or HAL_SDADC_MultiModeGetValue.
02188   * @param  hsdadc SDADC handle.
02189   * @retval None
02190   */
02191 __weak void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
02192 {
02193   /* Prevent unused argument(s) compilation warning */
02194   UNUSED(hsdadc);
02195
02196   /* NOTE : This function should not be modified, when the callback is needed,
02197             the HAL_SDADC_ConvCpltCallback could be implemented in the user file.
02198    */
02199 }
02200
02201 /**
02202   * @brief  Half injected conversion complete callback.
02203   * @param  hsdadc SDADC handle.
02204   * @retval None
02205   */
02206 __weak void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
02207 {
02208   /* Prevent unused argument(s) compilation warning */
02209   UNUSED(hsdadc);
02210
02211   /* NOTE : This function should not be modified, when the callback is needed,
02212             the HAL_SDADC_InjectedConvHalfCpltCallback could be implemented in the user file.
02213    */
02214 }
02215
02216 /**
02217   * @brief  Injected conversion complete callback.
02218   * @note   In interrupt mode, user has to read conversion value in this function
02219             using HAL_SDADC_InjectedGetValue or HAL_SDADC_InjectedMultiModeGetValue.
02220   * @param  hsdadc SDADC handle.
02221   * @retval None
02222   */
02223 __weak void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
02224 {
02225   /* Prevent unused argument(s) compilation warning */
02226   UNUSED(hsdadc);
02227
02228   /* NOTE : This function should not be modified, when the callback is needed,
02229             the HAL_SDADC_InjectedConvCpltCallback could be implemented in the user file.
02230    */
02231 }
02232
02233 /**
02234   * @brief  Error callback.
02235   * @param  hsdadc SDADC handle.
02236   * @retval None
02237   */
02238 __weak void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc)
02239 {
02240   /* Prevent unused argument(s) compilation warning */
02241   UNUSED(hsdadc);
02242
02243   /* NOTE : This function should not be modified, when the callback is needed,
02244             the HAL_SDADC_ErrorCallback could be implemented in the user file.
02245    */
02246 }
02247
02248 /**
02249   * @brief  DMA half transfer complete callback for regular conversion.
02250   * @param  hdma DMA handle.
02251   * @retval None
02252   */
02253 static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
02254 {
02255   /* Get SDADC handle */
02256   SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
02257
02258   /* Call regular half conversion complete callback */
02259   HAL_SDADC_ConvHalfCpltCallback(hsdadc);
02260 }
02261
02262 /**
02263   * @brief  DMA transfer complete callback for regular conversion.
02264   * @param  hdma DMA handle.
02265   * @retval None
02266   */
02267 static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
02268 {
02269   /* Get SDADC handle */
02270   SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
02271
02272   /* Call regular conversion complete callback */
02273   HAL_SDADC_ConvCpltCallback(hsdadc);
02274 }
02275
02276 /**
02277   * @brief  DMA half transfer complete callback for injected conversion.
02278   * @param  hdma DMA handle.
02279   * @retval None
02280   */
02281 static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
02282 {
02283   /* Get SDADC handle */
02284   SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
02285
02286   /* Call injected half conversion complete callback */
02287   HAL_SDADC_InjectedConvHalfCpltCallback(hsdadc);
02288 }
02289
02290 /**
02291   * @brief  DMA transfer complete callback for injected conversion.
02292   * @param  hdma DMA handle.
02293   * @retval None
02294   */
02295 static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
02296 {
02297   /* Get SDADC handle */
02298   SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
02299
02300   /* Call injected conversion complete callback */
02301   HAL_SDADC_InjectedConvCpltCallback(hsdadc);
02302 }
02303
02304 /**
02305   * @brief  DMA error callback.
02306   * @param  hdma DMA handle.
02307   * @retval None
02308   */
02309 static void SDADC_DMAError(DMA_HandleTypeDef *hdma)
02310 {
02311   /* Get SDADC handle */
02312   SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
02313
02314   /* Update error code */
02315   hsdadc->ErrorCode = SDADC_ERROR_DMA;
02316
02317   /* Call error callback */
02318   HAL_SDADC_ErrorCallback(hsdadc);
02319 }
02320
02321 /**
02322   * @}
02323   */
02324
02325 /** @defgroup SDADC_Exported_Functions_Group4 Peripheral State functions
02326  *  @brief   SDADC Peripheral State functions
02327  *
02328 @verbatim
02329   ===============================================================================
02330              ##### ADC Peripheral State functions #####
02331   ===============================================================================
02332     [..] This subsection provides functions allowing to
02333       (+) Get the SDADC state
02334       (+) Get the SDADC Error
02335
02336 @endverbatim
02337   * @{
02338   */
02339
02340 /**
02341   * @brief  This function allows to get the current SDADC state.
02342   * @param  hsdadc SDADC handle.
02343   * @retval SDADC state.
02344   */
02345 HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc)
02346 {
02347   return hsdadc->State;
02348 }
02349
02350 /**
02351   * @brief  This function allows to get the current SDADC error code.
02352   * @param  hsdadc SDADC handle.
02353   * @retval SDADC error code.
02354   */
02355 uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc)
02356 {
02357   return hsdadc->ErrorCode;
02358 }
02359
02360 /**
02361   * @}
02362   */
02363
02364 /** @addtogroup SDADC_Private_Functions SDADC Private Functions
02365   * @{
02366   */
02367
02368 /**
02369   * @brief  This function allows to enter in init mode for SDADC instance.
02370   * @param  hsdadc SDADC handle.
02371   * @retval HAL status.
02372   */
02373 static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc)
02374 {
02375   uint32_t tickstart = 0U;
02376
02377   /* Set INIT bit on SDADC_CR1 register */
02378   hsdadc->Instance->CR1 |= SDADC_CR1_INIT;
02379
02380   /* Wait INITRDY bit on SDADC_ISR */
02381   tickstart = HAL_GetTick();
02382   while((hsdadc->Instance->ISR & SDADC_ISR_INITRDY) == (uint32_t)RESET)
02383   {
02384     if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
02385     {
02386       return HAL_TIMEOUT;
02387     }
02388   }
02389
02390   /* Return HAL status */
02391   return HAL_OK;
02392 }
02393
02394 /**
02395   * @brief  This function allows to exit from init mode for SDADC instance.
02396   * @param  hsdadc SDADC handle.
02397   * @retval None.
02398   */
02399 static void SDADC_ExitInitMode(SDADC_HandleTypeDef* hsdadc)
02400 {
02401   /* Reset INIT bit in SDADC_CR1 register */
02402   hsdadc->Instance->CR1 &= ~(SDADC_CR1_INIT);
02403 }
02404
02405 /**
02406   * @brief  This function allows to get the number of injected channels.
02407   * @param  Channels bitfield of injected channels.
02408   * @retval Number of injected channels.
02409   */
02410 static uint32_t SDADC_GetInjChannelsNbr(uint32_t Channels)
02411 {
02412   uint32_t nbChannels = 0U;
02413   uint32_t tmp,i;
02414
02415   /* Get the number of channels from bitfield */
02416   tmp = (uint32_t) (Channels & SDADC_LSB_MASK);
02417   for(i = 0U ; i < 9U ; i++)
02418   {
02419     if((tmp & 0x00000001U) != 0U)
02420     {
02421       nbChannels++;
02422     }
02423     tmp = (uint32_t) (tmp >> 1U);
02424   }
02425   return nbChannels;
02426 }
02427
02428 /**
02429   * @brief  This function allows to really start regular conversion.
02430   * @param  hsdadc SDADC handle.
02431   * @retval HAL status.
02432   */
02433 static HAL_StatusTypeDef SDADC_RegConvStart(SDADC_HandleTypeDef* hsdadc)
02434 {
02435   HAL_StatusTypeDef status = HAL_OK;
02436
02437   /* Check regular trigger */
02438   if(hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER)
02439   {
02440     /* Set RSWSTART bit in SDADC_CR2 register */
02441     hsdadc->Instance->CR2 |= SDADC_CR2_RSWSTART;
02442   }
02443   else /* synchronuous trigger */
02444   {
02445     /* Enter init mode */
02446     if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
02447     {
02448       /* Set SDADC in error state */
02449       hsdadc->State = HAL_SDADC_STATE_ERROR;
02450       status = HAL_TIMEOUT;
02451     }
02452     else
02453     {
02454       /* Set RSYNC bit in SDADC_CR1 register */
02455       hsdadc->Instance->CR1 |= SDADC_CR1_RSYNC;
02456
02457       /* Exit init mode */
02458       SDADC_ExitInitMode(hsdadc);
02459     }
02460   }
02461   /* Update SDADC state only if status is OK */
02462   if(status == HAL_OK)
02463   {
02464     hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_READY) ? \
02465                     HAL_SDADC_STATE_REG : HAL_SDADC_STATE_REG_INJ;
02466   }
02467   /* Return function status */
02468   return status;
02469 }
02470
02471 /**
02472   * @brief  This function allows to really stop regular conversion.
02473   * @param  hsdadc SDADC handle.
02474   * @retval HAL status.
02475   */
02476 static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc)
02477 {
02478   uint32_t tickstart;
02479   __IO uint32_t dummy_read_for_register_reset;
02480
02481   /* Check continuous mode */
02482   if(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_ON)
02483   {
02484     /* Clear REOCF by reading SDADC_RDATAR register */
02485     dummy_read_for_register_reset = hsdadc->Instance->RDATAR;
02486     UNUSED(dummy_read_for_register_reset);
02487
02488     /* Clear RCONT bit in SDADC_CR2 register */
02489     hsdadc->Instance->CR2 &= ~(SDADC_CR2_RCONT);
02490   }
02491   /* Wait for the end of regular conversion */
02492   tickstart = HAL_GetTick();
02493   while((hsdadc->Instance->ISR & SDADC_ISR_RCIP) != 0U)
02494   {
02495     if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
02496     {
02497       /* Set SDADC in error state and return timeout status */
02498       hsdadc->State = HAL_SDADC_STATE_ERROR;
02499       return HAL_TIMEOUT;
02500     }
02501   }
02502   /* Check if trigger is synchronuous */
02503   if(hsdadc->RegularTrigger == SDADC_SYNCHRONOUS_TRIGGER)
02504   {
02505     /* Enter init mode */
02506     if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
02507     {
02508       /* Set SDADC in error state and return timeout status */
02509       hsdadc->State = HAL_SDADC_STATE_ERROR;
02510       return HAL_TIMEOUT;
02511     }
02512     else
02513     {
02514       /* Clear RSYNC bit in SDADC_CR1 register */
02515       hsdadc->Instance->CR1 &= ~(SDADC_CR1_RSYNC);
02516
02517       /* Exit init mode */
02518       SDADC_ExitInitMode(hsdadc);
02519     }
02520   }
02521   /* Check if continuous mode */
02522   if(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_ON)
02523   {
02524     /* Restore RCONT bit in SDADC_CR2 register */
02525     hsdadc->Instance->CR2 |= SDADC_CR2_RCONT;
02526   }
02527   /* Clear REOCF by reading SDADC_RDATAR register */
02528   dummy_read_for_register_reset = hsdadc->Instance->RDATAR;
02529   UNUSED(dummy_read_for_register_reset);
02530
02531   /* Set CLRROVRF bit in SDADC_CLRISR register */
02532   hsdadc->Instance->CLRISR |= SDADC_ISR_CLRROVRF;
02533
02534   /* Update SDADC state */
02535   hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
02536                   HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
02537
02538   /* Return function status */
02539   return HAL_OK;
02540 }
02541
02542 /**
02543   * @brief  This function allows to really start injected conversion.
02544   * @param  hsdadc SDADC handle.
02545   * @retval HAL status.
02546   */
02547 static HAL_StatusTypeDef SDADC_InjConvStart(SDADC_HandleTypeDef* hsdadc)
02548 {
02549   HAL_StatusTypeDef status = HAL_OK;
02550
02551   /* Initialize number of injected conversions remaining */
02552   hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
02553
02554   /* Check injected trigger */
02555   if(hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER)
02556   {
02557     /* Set JSWSTART bit in SDADC_CR2 register */
02558     hsdadc->Instance->CR2 |= SDADC_CR2_JSWSTART;
02559   }
02560   else /* external or synchronuous trigger */
02561   {
02562     /* Enter init mode */
02563     if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
02564     {
02565       /* Set SDADC in error state */
02566       hsdadc->State = HAL_SDADC_STATE_ERROR;
02567       status = HAL_TIMEOUT;
02568     }
02569     else
02570     {
02571       if(hsdadc->InjectedTrigger == SDADC_SYNCHRONOUS_TRIGGER)
02572       {
02573         /* Set JSYNC bit in SDADC_CR1 register */
02574         hsdadc->Instance->CR1 |= SDADC_CR1_JSYNC;
02575       }
02576       else /* external trigger */
02577       {
02578         /* Set JEXTEN[1:0] bits in SDADC_CR2 register */
02579         hsdadc->Instance->CR2 |= hsdadc->ExtTriggerEdge;
02580       }
02581       /* Exit init mode */
02582       SDADC_ExitInitMode(hsdadc);
02583     }
02584   }
02585   /* Update SDADC state only if status is OK */
02586   if(status == HAL_OK)
02587   {
02588     hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_READY) ? \
02589                     HAL_SDADC_STATE_INJ : HAL_SDADC_STATE_REG_INJ;
02590   }
02591   /* Return function status */
02592   return status;
02593 }
02594
02595 /**
02596   * @brief  This function allows to really stop injected conversion.
02597   * @param  hsdadc SDADC handle.
02598   * @retval HAL status.
02599   */
02600 static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc)
02601 {
02602   uint32_t tickstart;
02603   __IO uint32_t dummy_read_for_register_reset;
02604
02605   /* Check continuous mode */
02606   if(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_ON)
02607   {
02608     /* Clear JEOCF by reading SDADC_JDATAR register */
02609     dummy_read_for_register_reset =  hsdadc->Instance->JDATAR;
02610     UNUSED(dummy_read_for_register_reset);
02611
02612     /* Clear JCONT bit in SDADC_CR2 register */
02613     hsdadc->Instance->CR2 &= ~(SDADC_CR2_JCONT);
02614   }
02615   /* Wait for the end of injected conversion */
02616   tickstart = HAL_GetTick();
02617   while((hsdadc->Instance->ISR & SDADC_ISR_JCIP) != 0U)
02618   {
02619     if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
02620     {
02621       /* Set SDADC in error state and return timeout status */
02622       hsdadc->State = HAL_SDADC_STATE_ERROR;
02623       return HAL_TIMEOUT;
02624     }
02625   }
02626   /* Check if trigger is not software */
02627   if(hsdadc->InjectedTrigger != SDADC_SOFTWARE_TRIGGER)
02628   {
02629     /* Enter init mode */
02630     if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
02631     {
02632       /* Set SDADC in error state and return timeout status */
02633       hsdadc->State = HAL_SDADC_STATE_ERROR;
02634       return HAL_TIMEOUT;
02635     }
02636     else
02637     {
02638       /* Check if trigger is synchronuous */
02639       if(hsdadc->InjectedTrigger == SDADC_SYNCHRONOUS_TRIGGER)
02640       {
02641         /* Clear JSYNC bit in SDADC_CR1 register */
02642         hsdadc->Instance->CR1 &= ~(SDADC_CR1_JSYNC);
02643       }
02644       else /* external trigger */
02645       {
02646         /* Clear JEXTEN[1:0] bits in SDADC_CR2 register */
02647         hsdadc->Instance->CR2 &= ~(SDADC_CR2_JEXTEN);
02648       }
02649       /* Exit init mode */
02650       SDADC_ExitInitMode(hsdadc);
02651     }
02652   }
02653   /* Check if continuous mode */
02654   if(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_ON)
02655   {
02656     /* Restore JCONT bit in SDADC_CR2 register */
02657     hsdadc->Instance->CR2 |= SDADC_CR2_JCONT;
02658   }
02659   /* Clear JEOCF by reading SDADC_JDATAR register */
02660   dummy_read_for_register_reset = hsdadc->Instance->JDATAR;
02661   UNUSED(dummy_read_for_register_reset);
02662
02663   /* Set CLRJOVRF bit in SDADC_CLRISR register */
02664   hsdadc->Instance->CLRISR |= SDADC_ISR_CLRJOVRF;
02665
02666   /* Update SDADC state */
02667   hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
02668                   HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
02669
02670   /* Return function status */
02671   return HAL_OK;
02672 }
02673
02674 /**
02675   * @}
02676   */
02677
02678 /**
02679   * @}
02680   */
02681
02682 /**
02683   * @}
02684   */
02685
02686 #endif /* defined(STM32F373xC) || defined(STM32F378xx) */
02687 #endif /* HAL_SDADC_MODULE_ENABLED */
02688 /**
02689   * @}
02690   */
02691
02692 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_sdadc.h Source File

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stm32f3xx_hal_sdadc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_sdadc.h
00004   * @author  MCD Application Team
00005   * @brief   This file contains all the functions prototypes for the SDADC
00006   *          firmware library.
00007   ******************************************************************************
00008   * @attention
00009   *
00010   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00011   *
00012   * Redistribution and use in source and binary forms, with or without modification,
00013   * are permitted provided that the following conditions are met:
00014   *   1. Redistributions of source code must retain the above copyright notice,
00015   *      this list of conditions and the following disclaimer.
00016   *   2. Redistributions in binary form must reproduce the above copyright notice,
00017   *      this list of conditions and the following disclaimer in the documentation
00018   *      and/or other materials provided with the distribution.
00019   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00020   *      may be used to endorse or promote products derived from this software
00021   *      without specific prior written permission.
00022   *
00023   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00024   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00025   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00026   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00027   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00028   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00029   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00030   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00031   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00032   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00033   *
00034   ******************************************************************************
00035   */
00036
00037 /* Define to prevent recursive inclusion -------------------------------------*/
00038 #ifndef __STM32F3xx_SDADC_H
00039 #define __STM32F3xx_SDADC_H
00040
00041 #ifdef __cplusplus
00042  extern "C" {
00043 #endif
00044
00045 #if defined(STM32F373xC) || defined(STM32F378xx)
00046
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f3xx_hal_def.h"
00049
00050 /** @addtogroup STM32F3xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup SDADC
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup SDADC_Exported_Types SDADC Exported Types
00060   * @{
00061   */
00062
00063
00064 /**
00065   * @brief  HAL SDADC States definition
00066   */
00067 typedef enum
00068 {
00069   HAL_SDADC_STATE_RESET                   = 0x00U,    /*!< SDADC not initialized */
00070   HAL_SDADC_STATE_READY                   = 0x01U,    /*!< SDADC initialized and ready for use */
00071   HAL_SDADC_STATE_CALIB                   = 0x02U,    /*!< SDADC calibration in progress */
00072   HAL_SDADC_STATE_REG                     = 0x03U,    /*!< SDADC regular conversion in progress */
00073   HAL_SDADC_STATE_INJ                     = 0x04U,    /*!< SDADC injected conversion in progress */
00074   HAL_SDADC_STATE_REG_INJ                 = 0x05U,    /*!< SDADC regular and injected conversions in progress */
00075   HAL_SDADC_STATE_ERROR                   = 0xFFU,    /*!< SDADC state error */
00076 }HAL_SDADC_StateTypeDef;
00077
00078 /**
00079   * @brief SDADC Init Structure definition
00080   */
00081 typedef struct
00082 {
00083   uint32_t IdleLowPowerMode;        /*!< Specifies if SDADC can enter in power down or standby when idle.
00084                                          This parameter can be a value of @ref SDADC_Idle_Low_Power_Mode */
00085   uint32_t FastConversionMode;      /*!< Specifies if Fast conversion mode is enabled or not.
00086                                          This parameter can be a value of @ref SDADC_Fast_Conv_Mode */
00087   uint32_t SlowClockMode;           /*!< Specifies if slow clock mode is enabled or not.
00088                                          This parameter can be a value of @ref SDADC_Slow_Clock_Mode */
00089   uint32_t ReferenceVoltage;        /*!< Specifies the reference voltage.
00090                                          Note: This parameter is common to all SDADC instances.
00091                                          This parameter can be a value of @ref SDADC_Reference_Voltage */
00092 }SDADC_InitTypeDef;
00093
00094 /**
00095   * @brief  SDADC handle Structure definition
00096   */
00097 typedef struct
00098 {
00099   SDADC_TypeDef            *Instance;           /*!< SDADC registers base address */
00100   SDADC_InitTypeDef        Init;                /*!< SDADC init parameters        */
00101   DMA_HandleTypeDef        *hdma;               /*!< SDADC DMA Handle parameters  */
00102   uint32_t                 RegularContMode;     /*!< Regular conversion continuous mode */
00103   uint32_t                 InjectedContMode;    /*!< Injected conversion continuous mode */
00104   uint32_t                 InjectedChannelsNbr; /*!< Number of channels in injected sequence */
00105   uint32_t                 InjConvRemaining;    /*!< Injected conversion remaining */
00106   uint32_t                 RegularTrigger;      /*!< Current trigger used for regular conversion */
00107   uint32_t                 InjectedTrigger;     /*!< Current trigger used for injected conversion */
00108   uint32_t                 ExtTriggerEdge;      /*!< Rising, falling or both edges selected */
00109   uint32_t                 RegularMultimode;    /*!< current type of regular multimode */
00110   uint32_t                 InjectedMultimode;   /*!< Current type of injected multimode */
00111   HAL_SDADC_StateTypeDef   State;               /*!< SDADC state */
00112   uint32_t                 ErrorCode;           /*!< SDADC Error code */
00113 }SDADC_HandleTypeDef;
00114
00115 /**
00116   * @brief  SDADC Configuration Register Parameter Structure
00117   */
00118 typedef struct
00119 {
00120   uint32_t InputMode;      /*!< Specifies the input mode (single ended, differential...)
00121                                 This parameter can be any value of @ref SDADC_InputMode */
00122   uint32_t Gain;           /*!< Specifies the gain setting.
00123                                 This parameter can be any value of @ref SDADC_Gain */
00124   uint32_t CommonMode;     /*!< Specifies the common mode setting (VSSA, VDDA, VDDA/2U).
00125                                 This parameter can be any value of @ref SDADC_CommonMode */
00126   uint32_t Offset;         /*!< Specifies the 12-bit offset value.
00127                                 This parameter can be any value lower or equal to 0x00000FFFU */
00128 }SDADC_ConfParamTypeDef;
00129
00130 /**
00131   * @}
00132   */
00133
00134 /* Exported constants --------------------------------------------------------*/
00135
00136 /** @defgroup SDADC_Exported_Constants SDADC Exported Constants
00137   * @{
00138   */
00139
00140 /** @defgroup SDADC_Idle_Low_Power_Mode SDADC Idle Low Power Mode
00141   * @{
00142   */
00143 #define SDADC_LOWPOWER_NONE                  (0x00000000U)
00144 #define SDADC_LOWPOWER_POWERDOWN             SDADC_CR1_PDI
00145 #define SDADC_LOWPOWER_STANDBY               SDADC_CR1_SBI
00146 /**
00147   * @}
00148   */
00149
00150 /** @defgroup SDADC_Fast_Conv_Mode SDADC Fast Conversion Mode
00151   * @{
00152   */
00153 #define SDADC_FAST_CONV_DISABLE              (0x00000000U)
00154 #define SDADC_FAST_CONV_ENABLE               SDADC_CR2_FAST
00155 /**
00156   * @}
00157   */
00158
00159 /** @defgroup SDADC_Slow_Clock_Mode SDADC Slow Clock Mode
00160   * @{
00161   */
00162 #define SDADC_SLOW_CLOCK_DISABLE             (0x00000000U)
00163 #define SDADC_SLOW_CLOCK_ENABLE              SDADC_CR1_SLOWCK
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup SDADC_Reference_Voltage SDADC Reference Voltage
00169   * @{
00170   */
00171 #define SDADC_VREF_EXT                       (0x00000000U) /*!< The reference voltage is forced externally using VREF pin */
00172 #define SDADC_VREF_VREFINT1                  SDADC_CR1_REFV_0       /*!< The reference voltage is forced internally to 1.22V VREFINT */
00173 #define SDADC_VREF_VREFINT2                  SDADC_CR1_REFV_1       /*!< The reference voltage is forced internally to 1.8V VREFINT */
00174 #define SDADC_VREF_VDDA                      SDADC_CR1_REFV         /*!< The reference voltage is forced internally to VDDA */
00175 /**
00176   * @}
00177   */
00178
00179 /** @defgroup SDADC_ConfIndex SDADC Configuration Index
00180   * @{
00181   */
00182
00183 #define SDADC_CONF_INDEX_0                     (0x00000000U) /*!< Configuration 0 Register selected */
00184 #define SDADC_CONF_INDEX_1                     (0x00000001U) /*!< Configuration 1 Register selected */
00185 #define SDADC_CONF_INDEX_2                     (0x00000002U) /*!< Configuration 2 Register selected */
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup SDADC_InputMode SDADC Input Mode
00191   * @{
00192   */
00193 #define SDADC_INPUT_MODE_DIFF                (0x00000000U) /*!< Conversions are executed in differential mode */
00194 #define SDADC_INPUT_MODE_SE_OFFSET           SDADC_CONF0R_SE0_0     /*!< Conversions are executed in single ended offset mode */
00195 #define SDADC_INPUT_MODE_SE_ZERO_REFERENCE   SDADC_CONF0R_SE0       /*!< Conversions are executed in single ended zero-volt reference mode */
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup SDADC_Gain SDADC Gain
00201   * @{
00202   */
00203 #define SDADC_GAIN_1                         (0x00000000U)  /*!< Gain equal to 1U */
00204 #define SDADC_GAIN_2                         SDADC_CONF0R_GAIN0_0    /*!< Gain equal to 2U */
00205 #define SDADC_GAIN_4                         SDADC_CONF0R_GAIN0_1    /*!< Gain equal to 4U */
00206 #define SDADC_GAIN_8                         (0x00300000U)  /*!< Gain equal to 8U */
00207 #define SDADC_GAIN_16                        SDADC_CONF0R_GAIN0_2    /*!< Gain equal to 16U */
00208 #define SDADC_GAIN_32                        (0x00500000U)  /*!< Gain equal to 32U */
00209 #define SDADC_GAIN_1_2                       SDADC_CONF0R_GAIN0      /*!< Gain equal to 1U/2U */
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup SDADC_CommonMode SDADC Common Mode
00215   * @{
00216   */
00217 #define SDADC_COMMON_MODE_VSSA               (0x00000000U) /*!< Select SDADC VSSA as common mode */
00218 #define SDADC_COMMON_MODE_VDDA_2             SDADC_CONF0R_COMMON0_0 /*!< Select SDADC VDDA/2 as common mode */
00219 #define SDADC_COMMON_MODE_VDDA               SDADC_CONF0R_COMMON0_1 /*!< Select SDADC VDDA as common mode */
00220 /**
00221   * @}
00222   */
00223
00224
00225
00226 /** @defgroup SDADC_Channel_Selection SDADC Channel Selection
00227   * @{
00228   */
00229
00230 /* SDADC Channels ------------------------------------------------------------*/
00231 /* The SDADC channels are defined as follows:
00232    - in 16-bit LSB the channel mask is set
00233    - in 16-bit MSB the channel number is set
00234    e.g. for channel 5 definition:
00235         - the channel mask is 0x00000020 (bit 5 is set)
00236         - the channel number 5 is 0x00050000
00237         --> Consequently, channel 5 definition is 0x00000020U | 0x00050000U = 0x00050020U */
00238 #define SDADC_CHANNEL_0                              (0x00000001U)
00239 #define SDADC_CHANNEL_1                              (0x00010002U)
00240 #define SDADC_CHANNEL_2                              (0x00020004U)
00241 #define SDADC_CHANNEL_3                              (0x00030008U)
00242 #define SDADC_CHANNEL_4                              (0x00040010U)
00243 #define SDADC_CHANNEL_5                              (0x00050020U)
00244 #define SDADC_CHANNEL_6                              (0x00060040U)
00245 #define SDADC_CHANNEL_7                              (0x00070080U)
00246 #define SDADC_CHANNEL_8                              (0x00080100U)
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup SDADC_CalibrationSequence SDADC Calibration Sequence
00252   * @{
00253   */
00254 #define SDADC_CALIBRATION_SEQ_1                   (0x00000000U) /*!< One calibration sequence to calculate offset of conf0 (OFFSET0[11:0]) */
00255 #define SDADC_CALIBRATION_SEQ_2                   SDADC_CR2_CALIBCNT_0   /*!< Two calibration sequences to calculate offset of conf0 and conf1 (OFFSET0[11:0] and OFFSET1[11:0]) */
00256 #define SDADC_CALIBRATION_SEQ_3                   SDADC_CR2_CALIBCNT_1   /*!< Three calibration sequences to calculate offset of conf0, conf1 and conf2 (OFFSET0[11:0], OFFSET1[11:0], and OFFSET2[11:0]) */
00257 /**
00258   * @}
00259   */
00260
00261 /** @defgroup SDADC_ContinuousMode SDADC Continuous Mode
00262   * @{
00263   */
00264 #define SDADC_CONTINUOUS_CONV_OFF            (0x00000000U) /*!< Conversion are not continuous */
00265 #define SDADC_CONTINUOUS_CONV_ON             (0x00000001U) /*!< Conversion are continuous */
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup SDADC_Trigger SDADC Trigger
00271   * @{
00272   */
00273 #define SDADC_SOFTWARE_TRIGGER               (0x00000000U) /*!< Software trigger */
00274 #define SDADC_SYNCHRONOUS_TRIGGER            (0x00000001U) /*!< Synchronous with SDADC1 (only for SDADC2 and SDADC3) */
00275 #define SDADC_EXTERNAL_TRIGGER               (0x00000002U) /*!< External trigger */
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup SDADC_InjectedExtTrigger SDADC Injected External Trigger
00281   * @{
00282   */
00283 #define SDADC_EXT_TRIG_TIM13_CC1             (0x00000000U) /*!< Trigger source for SDADC1 */
00284 #define SDADC_EXT_TRIG_TIM14_CC1             (0x00000100U) /*!< Trigger source for SDADC1 */
00285 #define SDADC_EXT_TRIG_TIM16_CC1             (0x00000000U) /*!< Trigger source for SDADC3 */
00286 #define SDADC_EXT_TRIG_TIM17_CC1             (0x00000000U) /*!< Trigger source for SDADC2 */
00287 #define SDADC_EXT_TRIG_TIM12_CC1             (0x00000100U) /*!< Trigger source for SDADC2 */
00288 #define SDADC_EXT_TRIG_TIM12_CC2             (0x00000100U) /*!< Trigger source for SDADC3 */
00289 #define SDADC_EXT_TRIG_TIM15_CC2             (0x00000200U) /*!< Trigger source for SDADC1 */
00290 #define SDADC_EXT_TRIG_TIM2_CC3              (0x00000200U) /*!< Trigger source for SDADC2 */
00291 #define SDADC_EXT_TRIG_TIM2_CC4              (0x00000200U) /*!< Trigger source for SDADC3 */
00292 #define SDADC_EXT_TRIG_TIM3_CC1              (0x00000300U) /*!< Trigger source for SDADC1 */
00293 #define SDADC_EXT_TRIG_TIM3_CC2              (0x00000300U) /*!< Trigger source for SDADC2 */
00294 #define SDADC_EXT_TRIG_TIM3_CC3              (0x00000300U) /*!< Trigger source for SDADC3 */
00295 #define SDADC_EXT_TRIG_TIM4_CC1              (0x00000400U) /*!< Trigger source for SDADC1 */
00296 #define SDADC_EXT_TRIG_TIM4_CC2              (0x00000400U) /*!< Trigger source for SDADC2 */
00297 #define SDADC_EXT_TRIG_TIM4_CC3              (0x00000400U) /*!< Trigger source for SDADC3 */
00298 #define SDADC_EXT_TRIG_TIM19_CC2             (0x00000500U) /*!< Trigger source for SDADC1 */
00299 #define SDADC_EXT_TRIG_TIM19_CC3             (0x00000500U) /*!< Trigger source for SDADC2 */
00300 #define SDADC_EXT_TRIG_TIM19_CC4             (0x00000500U) /*!< Trigger source for SDADC3 */
00301 #define SDADC_EXT_TRIG_EXTI11                (0x00000700U) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
00302 #define SDADC_EXT_TRIG_EXTI15                (0x00000600U) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup SDADC_ExtTriggerEdge SDADC External Trigger Edge
00308   * @{
00309   */
00310 #define SDADC_EXT_TRIG_RISING_EDGE           SDADC_CR2_JEXTEN_0     /*!< External rising edge */
00311 #define SDADC_EXT_TRIG_FALLING_EDGE          SDADC_CR2_JEXTEN_1     /*!< External falling edge */
00312 #define SDADC_EXT_TRIG_BOTH_EDGES            SDADC_CR2_JEXTEN       /*!< External rising and falling edges */
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup SDADC_InjectedDelay SDADC Injected Conversion Delay
00318   * @{
00319   */
00320 #define SDADC_INJECTED_DELAY_NONE            (0x00000000U) /*!< No delay on injected conversion */
00321 #define SDADC_INJECTED_DELAY                 SDADC_CR2_JDS          /*!< Delay on injected conversion */
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup SDADC_MultimodeType SDADC Multimode Type
00327   * @{
00328   */
00329 #define SDADC_MULTIMODE_SDADC1_SDADC2        (0x00000000U) /*!< Get conversion values for SDADC1 and SDADC2 */
00330 #define SDADC_MULTIMODE_SDADC1_SDADC3        (0x00000001U) /*!< Get conversion values for SDADC1 and SDADC3 */
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup SDADC_ErrorCode SDADC Error Code
00336   * @{
00337   */
00338 #define SDADC_ERROR_NONE                     (0x00000000U) /*!< No error */
00339 #define SDADC_ERROR_REGULAR_OVERRUN          (0x00000001U) /*!< Overrun occurs during regular conversion */
00340 #define SDADC_ERROR_INJECTED_OVERRUN         (0x00000002U) /*!< Overrun occurs during injected conversion */
00341 #define SDADC_ERROR_DMA                      (0x00000003U) /*!< DMA error occurs */
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup SDADC_interrupts_definition SDADC interrupts definition
00347   * @{
00348   */
00349 #define  SDADC_IT_EOCAL     SDADC_CR1_EOCALIE   /*!< End of calibration interrupt enable */
00350 #define  SDADC_IT_JEOC      SDADC_CR1_JEOCIE    /*!< Injected end of conversion interrupt enable */
00351 #define  SDADC_IT_JOVR      SDADC_CR1_JOVRIE    /*!< Injected data overrun interrupt enable */
00352 #define  SDADC_IT_REOC      SDADC_CR1_REOCIE    /*!< Regular end of conversion interrupt enable */
00353 #define  SDADC_IT_ROVR      SDADC_CR1_ROVRIE    /*!< Regular data overrun interrupt enable */
00354 /**
00355   * @}
00356   */
00357
00358 /** @defgroup SDADC_flags_definition SDADC flags definition
00359   * @{
00360   */
00361 #define SDADC_FLAG_EOCAL    SDADC_ISR_EOCALF    /*!< End of calibration flag */
00362 #define SDADC_FLAG_JEOC     SDADC_ISR_JEOCF     /*!< End of injected conversion flag */
00363 #define SDADC_FLAG_JOVR     SDADC_ISR_JOVRF     /*!< Injected conversion overrun flag */
00364 #define SDADC_FLAG_REOC     SDADC_ISR_REOCF     /*!< End of regular conversion flag */
00365 #define SDADC_FLAG_ROVR     SDADC_ISR_ROVRF     /*!< Regular conversion overrun flag */
00366 /**
00367   * @}
00368   */
00369
00370 /**
00371   * @}
00372   */
00373
00374 /* Exported macros -----------------------------------------------------------*/
00375 /** @defgroup SDADC_Exported_Macros SDADC Exported Macros
00376  * @{
00377  */
00378
00379 /* Macro for internal HAL driver usage, and possibly can be used into code of */
00380 /* final user.                                                                */
00381
00382 /** @brief Enable the ADC end of conversion interrupt.
00383   * @param __HANDLE__ ADC handle
00384   * @param __INTERRUPT__ ADC Interrupt
00385   *          This parameter can be any combination of the following values:
00386   *            @arg SDADC_IT_EOCAL: End of calibration interrupt enable
00387   *            @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
00388   *            @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
00389   *            @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
00390   *            @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
00391   * @retval None
00392   */
00393 #define __HAL_SDADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                       \
00394   (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
00395
00396 /** @brief Disable the ADC end of conversion interrupt.
00397   * @param __HANDLE__ ADC handle
00398   * @param __INTERRUPT__ ADC Interrupt
00399   *          This parameter can be any combination of the following values:
00400   *            @arg SDADC_IT_EOCAL: End of calibration interrupt enable
00401   *            @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
00402   *            @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
00403   *            @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
00404   *            @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
00405   * @retval None
00406   */
00407 #define __HAL_SDADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                      \
00408   (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
00409
00410 /** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
00411   * @param __HANDLE__ ADC handle
00412   * @param __INTERRUPT__ ADC interrupt source to check
00413   *          This parameter can be any combination of the following values:
00414   *            @arg SDADC_IT_EOCAL: End of calibration interrupt enable
00415   *            @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
00416   *            @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
00417   *            @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
00418   *            @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
00419   * @retval State of interruption (SET or RESET)
00420   */
00421 #define __HAL_SDADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                   \
00422   (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
00423
00424 /** @brief Get the selected ADC's flag status.
00425   * @param __HANDLE__ ADC handle
00426   * @param __FLAG__ ADC flag
00427   *          This parameter can be any combination of the following values:
00428   *            @arg SDADC_FLAG_EOCAL: End of calibration flag
00429   *            @arg SDADC_FLAG_JEOC: End of injected conversion flag
00430   *            @arg SDADC_FLAG_JOVR: Injected conversion overrun flag
00431   *            @arg SDADC_FLAG_REOC: End of regular conversion flag
00432   *            @arg SDADC_FLAG_ROVR: Regular conversion overrun flag
00433   * @retval None
00434   */
00435 #define __HAL_SDADC_GET_FLAG(__HANDLE__, __FLAG__)                             \
00436   ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
00437
00438 /** @brief Clear the ADC's pending flags
00439   * @param __HANDLE__ ADC handle
00440   * @param __FLAG__ ADC flag
00441   *          This parameter can be any combination of the following values:
00442   *            @arg SDADC_FLAG_EOCAL: End of calibration flag
00443   *            @arg SDADC_FLAG_JEOC: End of injected conversion flag
00444   *            @arg SDADC_FLAG_JOVR: Injected conversion overrun flag
00445   *            @arg SDADC_FLAG_REOC: End of regular conversion flag
00446   *            @arg SDADC_FLAG_ROVR: Regular conversion overrun flag
00447   * @retval None
00448   */
00449 #define __HAL_SDADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                           \
00450   (CLEAR_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)))
00451
00452 /** @brief  Reset SDADC handle state
00453   * @param  __HANDLE__ SDADC handle.
00454   * @retval None
00455   */
00456 #define __HAL_SDADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDADC_STATE_RESET)
00457
00458 /**
00459   * @}
00460   */
00461
00462 /* Private macros ------------------------------------------------------------*/
00463 /** @defgroup SDADC_Private_Macros SDADC Private Macros
00464  * @{
00465  */
00466
00467 #define IS_SDADC_LOWPOWER_MODE(LOWPOWER)     (((LOWPOWER) == SDADC_LOWPOWER_NONE)      || \
00468                                               ((LOWPOWER) == SDADC_LOWPOWER_POWERDOWN) || \
00469                                               ((LOWPOWER) == SDADC_LOWPOWER_STANDBY))
00470
00471 #define IS_SDADC_FAST_CONV_MODE(FAST)        (((FAST) == SDADC_FAST_CONV_DISABLE) || \
00472                                               ((FAST) == SDADC_FAST_CONV_ENABLE))
00473
00474 #define IS_SDADC_SLOW_CLOCK_MODE(MODE)       (((MODE) == SDADC_SLOW_CLOCK_DISABLE) || \
00475                                               ((MODE) == SDADC_SLOW_CLOCK_ENABLE))
00476
00477 #define IS_SDADC_VREF(VREF)                  (((VREF) == SDADC_VREF_EXT)      || \
00478                                               ((VREF) == SDADC_VREF_VREFINT1) || \
00479                                               ((VREF) == SDADC_VREF_VREFINT2) || \
00480                                               ((VREF) == SDADC_VREF_VDDA))
00481
00482 #define IS_SDADC_CONF_INDEX(CONF) (((CONF) == SDADC_CONF_INDEX_0)  || \
00483                                    ((CONF) == SDADC_CONF_INDEX_1)  || \
00484                                    ((CONF) == SDADC_CONF_INDEX_2))
00485
00486 #define IS_SDADC_INPUT_MODE(MODE) (((MODE) == SDADC_INPUT_MODE_DIFF)     || \
00487                                    ((MODE) == SDADC_INPUT_MODE_SE_OFFSET) || \
00488                                    ((MODE) == SDADC_INPUT_MODE_SE_ZERO_REFERENCE))
00489
00490 #define IS_SDADC_GAIN(GAIN) (((GAIN) == SDADC_GAIN_1)  || \
00491                              ((GAIN) == SDADC_GAIN_2)  || \
00492                              ((GAIN) == SDADC_GAIN_4)  || \
00493                              ((GAIN) == SDADC_GAIN_8)  || \
00494                              ((GAIN) == SDADC_GAIN_16)  || \
00495                              ((GAIN) == SDADC_GAIN_32)  || \
00496                              ((GAIN) == SDADC_GAIN_1_2))
00497
00498 #define IS_SDADC_COMMON_MODE(MODE) (((MODE) == SDADC_COMMON_MODE_VSSA)   || \
00499                                     ((MODE) == SDADC_COMMON_MODE_VDDA_2) || \
00500                                     ((MODE) == SDADC_COMMON_MODE_VDDA))
00501
00502 #define IS_SDADC_OFFSET_VALUE(VALUE) ((VALUE) <= 0x00000FFFU)
00503
00504 /* Just one channel of the 9 channels can be selected for regular conversion */
00505 #define IS_SDADC_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == SDADC_CHANNEL_0)  || \
00506                                            ((CHANNEL) == SDADC_CHANNEL_1)  || \
00507                                            ((CHANNEL) == SDADC_CHANNEL_2)  || \
00508                                            ((CHANNEL) == SDADC_CHANNEL_3)  || \
00509                                            ((CHANNEL) == SDADC_CHANNEL_4)  || \
00510                                            ((CHANNEL) == SDADC_CHANNEL_5)  || \
00511                                            ((CHANNEL) == SDADC_CHANNEL_6)  || \
00512                                            ((CHANNEL) == SDADC_CHANNEL_7)  || \
00513                                            ((CHANNEL) == SDADC_CHANNEL_8))
00514
00515 /* Any or all of the 9 channels can be selected for injected conversion */
00516 #define IS_SDADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F01FFU))
00517
00518
00519 #define IS_SDADC_CALIB_SEQUENCE(SEQUENCE)  (((SEQUENCE) == SDADC_CALIBRATION_SEQ_1)  || \
00520                                             ((SEQUENCE) == SDADC_CALIBRATION_SEQ_2)  || \
00521                                             ((SEQUENCE) == SDADC_CALIBRATION_SEQ_3))
00522
00523 #define IS_SDADC_CONTINUOUS_MODE(MODE)       (((MODE) == SDADC_CONTINUOUS_CONV_OFF)  || \
00524                                              ((MODE) == SDADC_CONTINUOUS_CONV_ON))
00525
00526
00527 #define IS_SDADC_REGULAR_TRIGGER(TRIGGER)    (((TRIGGER) == SDADC_SOFTWARE_TRIGGER)  || \
00528                                              ((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER))
00529
00530 #define IS_SDADC_INJECTED_TRIGGER(TRIGGER)   (((TRIGGER) == SDADC_SOFTWARE_TRIGGER)  || \
00531                                              ((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER)  || \
00532                                              ((TRIGGER) == SDADC_EXTERNAL_TRIGGER))
00533
00534
00535 #define IS_SDADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == SDADC_EXT_TRIG_TIM13_CC1) || \
00536                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM14_CC1) || \
00537                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM16_CC1) || \
00538                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM17_CC1) || \
00539                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC1) || \
00540                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC2)  || \
00541                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM15_CC2)  || \
00542                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC3)  || \
00543                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC4)  || \
00544                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC1)  || \
00545                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC2)  || \
00546                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC3) || \
00547                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC1) || \
00548                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC2) || \
00549                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC3) || \
00550                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC2) || \
00551                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC3) || \
00552                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC4) || \
00553                                           ((INJTRIG) == SDADC_EXT_TRIG_EXTI11) || \
00554                                           ((INJTRIG) == SDADC_EXT_TRIG_EXTI15))
00555
00556 #define IS_SDADC_EXT_TRIG_EDGE(TRIGGER)      (((TRIGGER) == SDADC_EXT_TRIG_RISING_EDGE)  || \
00557                                              ((TRIGGER) == SDADC_EXT_TRIG_FALLING_EDGE)  || \
00558                                              ((TRIGGER) == SDADC_EXT_TRIG_BOTH_EDGES))
00559
00560
00561 #define IS_SDADC_INJECTED_DELAY(DELAY)       (((DELAY) == SDADC_INJECTED_DELAY_NONE) || \
00562                                              ((DELAY) == SDADC_INJECTED_DELAY))
00563
00564 #define IS_SDADC_MULTIMODE_TYPE(TYPE)        (((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC2) || \
00565                                              ((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC3))
00566 /**
00567   * @}
00568   */
00569
00570 /* Exported functions --------------------------------------------------------*/
00571 /** @addtogroup SDADC_Exported_Functions SDADC Exported Functions
00572   * @{
00573   */
00574
00575 /** @addtogroup SDADC_Exported_Functions_Group1 Initialization and de-initialization functions
00576   * @{
00577   */
00578
00579 /* Initialization and de-initialization functions *****************************/
00580 HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef *hsdadc);
00581 HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef *hsdadc);
00582 void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc);
00583 void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc);
00584
00585 /**
00586   * @}
00587   */
00588
00589 /** @addtogroup SDADC_Exported_Functions_Group2 peripheral control functions
00590   * @{
00591   */
00592
00593 /* Peripheral Control functions ***********************************************/
00594 HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
00595                                                  uint32_t ConfIndex,
00596                                                  SDADC_ConfParamTypeDef* ConfParamStruct);
00597 HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
00598                                                    uint32_t Channel,
00599                                                    uint32_t ConfIndex);
00600 HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc,
00601                                           uint32_t Channel,
00602                                           uint32_t ContinuousMode);
00603 HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc,
00604                                                   uint32_t Channel,
00605                                                   uint32_t ContinuousMode);
00606 HAL_StatusTypeDef HAL_SDADC_SelectInjectedExtTrigger(SDADC_HandleTypeDef *hsdadc,
00607                                                      uint32_t InjectedExtTrigger,
00608                                                      uint32_t ExtTriggerEdge);
00609 HAL_StatusTypeDef HAL_SDADC_SelectInjectedDelay(SDADC_HandleTypeDef *hsdadc,
00610                                                 uint32_t InjectedDelay);
00611 HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger);
00612 HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger);
00613 HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType);
00614 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType);
00615
00616 /**
00617   * @}
00618   */
00619
00620 /** @addtogroup SDADC_Exported_Functions_Group3 Input and Output operation functions
00621   * @{
00622   */
00623
00624 /* IO operation functions *****************************************************/
00625 HAL_StatusTypeDef HAL_SDADC_CalibrationStart(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence);
00626 HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence);
00627
00628 HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc);
00629 HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc);
00630 HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length);
00631 HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc);
00632 HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc);
00633 HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc);
00634
00635 HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc);
00636 HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc);
00637 HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length);
00638 HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc);
00639 HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc);
00640 HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc);
00641
00642 HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length);
00643 HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc);
00644 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length);
00645 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc);
00646
00647 uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc);
00648 uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel);
00649 uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
00650 uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
00651
00652 void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc);
00653
00654 HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
00655 HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
00656 HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
00657
00658 void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc);
00659 void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc);
00660 void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc);
00661 void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc);
00662 void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc);
00663 void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc);
00664
00665 /**
00666   * @}
00667   */
00668
00669 /** @defgroup SDADC_Exported_Functions_Group4 Peripheral State functions
00670   * @{
00671   */
00672
00673 /* Peripheral State and Error functions ***************************************/
00674 HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc);
00675 uint32_t               HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc);
00676
00677 /* Private functions ---------------------------------------------------------*/
00678
00679 /**
00680   * @}
00681   */
00682
00683 /**
00684   * @}
00685   */
00686
00687 /**
00688   * @}
00689   */
00690
00691 /**
00692   * @}
00693   */
00694
00695 #endif /* defined(STM32F373xC) || defined(STM32F378xx) */
00696
00697 #ifdef __cplusplus
00698 }
00699 #endif
00700
00701 #endif /*__STM32F3xx_SDADC_H */
00702
00703
00704 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_smartcard.c Source File

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stm32f3xx_hal_smartcard.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_smartcard.c
00004   * @author  MCD Application Team
00005   * @brief   SMARTCARD HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the SMARTCARD peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State and Error functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017   [..]
00018     The SMARTCARD HAL driver can be used as follows:
00019
00020     (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
00021     (#) Associate a USART to the SMARTCARD handle hsmartcard.
00022     (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
00023         (++) Enable the USARTx interface clock.
00024         (++) USART pins configuration:
00025             (+++) Enable the clock for the USART GPIOs.
00026             (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
00027         (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
00028              and HAL_SMARTCARD_Receive_IT() APIs):
00029             (+++) Configure the USARTx interrupt priority.
00030             (+++) Enable the NVIC USART IRQ handle.
00031         (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
00032              and HAL_SMARTCARD_Receive_DMA() APIs):
00033             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00034             (+++) Enable the DMAx interface clock.
00035             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00036             (+++) Configure the DMA Tx/Rx channel.
00037             (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
00038             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00039
00040     (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
00041         the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
00042         error enabling or disabling in the hsmartcard handle Init structure.
00043
00044     (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
00045         in the hsmartcard handle AdvancedInit structure.
00046
00047     (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
00048         (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
00049              by calling the customized HAL_SMARTCARD_MspInit() API.
00050         [..]
00051         (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
00052              RXNE interrupt and Error Interrupts) will be managed using the macros
00053              __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
00054
00055     [..]
00056     [..] Three operation modes are available within this driver :
00057
00058      *** Polling mode IO operation ***
00059      =================================
00060      [..]
00061        (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
00062        (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
00063
00064      *** Interrupt mode IO operation ***
00065      ===================================
00066      [..]
00067        (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
00068        (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
00069             add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
00070        (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
00071        (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
00072             add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
00073        (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00074             add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
00075
00076      *** DMA mode IO operation ***
00077      ==============================
00078      [..]
00079        (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
00080        (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
00081             add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
00082        (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
00083        (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
00084             add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
00085        (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00086             add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
00087
00088      *** SMARTCARD HAL driver macros list ***
00089      ========================================
00090      [..]
00091        Below the list of most used macros in SMARTCARD HAL driver.
00092
00093        (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
00094        (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
00095        (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
00096        (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
00097        (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
00098
00099      [..]
00100        (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
00101
00102   @endverbatim
00103   ******************************************************************************
00104   * @attention
00105   *
00106   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00107   *
00108   * Redistribution and use in source and binary forms, with or without modification,
00109   * are permitted provided that the following conditions are met:
00110   *   1. Redistributions of source code must retain the above copyright notice,
00111   *      this list of conditions and the following disclaimer.
00112   *   2. Redistributions in binary form must reproduce the above copyright notice,
00113   *      this list of conditions and the following disclaimer in the documentation
00114   *      and/or other materials provided with the distribution.
00115   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00116   *      may be used to endorse or promote products derived from this software
00117   *      without specific prior written permission.
00118   *
00119   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00120   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00121   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00122   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00123   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00124   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00125   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00126   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00127   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00128   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00129   *
00130   ******************************************************************************
00131   */
00132
00133 /* Includes ------------------------------------------------------------------*/
00134 #include "stm32f3xx_hal.h"
00135
00136 /** @addtogroup STM32F3xx_HAL_Driver
00137   * @{
00138   */
00139
00140 /** @defgroup SMARTCARD SMARTCARD
00141   * @brief SMARTCARD HAL module driver
00142   * @{
00143   */
00144
00145 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00146
00147 /* Private typedef -----------------------------------------------------------*/
00148 /* Private define ------------------------------------------------------------*/
00149 /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
00150  * @{
00151  */
00152 #define SMARTCARD_TEACK_REACK_TIMEOUT               1000      /*!< SMARTCARD TX or RX enable acknowledge time-out value  */
00153
00154 #define USART_CR1_FIELDS      ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
00155                                           USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))       /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
00156 #define USART_CR2_CLK_FIELDS  ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
00157 #define USART_CR2_FIELDS      ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
00158 #define USART_CR3_FIELDS      ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))   /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
00159 /**
00160   * @}
00161   */
00162
00163 /* Private macros ------------------------------------------------------------*/
00164 /* Private variables ---------------------------------------------------------*/
00165 /* Private function prototypes -----------------------------------------------*/
00166 /** @addtogroup SMARTCARD_Private_Functions
00167   * @{
00168   */
00169 static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
00170 static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
00171 static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
00172 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00173 static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
00174 static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
00175 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00176 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00177 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
00178 static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00179 static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00180 static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00181 static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00182 static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00183 static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
00184 static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
00185 static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
00186 /**
00187   * @}
00188   */
00189
00190 /* Exported functions --------------------------------------------------------*/
00191
00192 /** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
00193   * @{
00194   */
00195
00196 /** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
00197   *  @brief    Initialization and Configuration functions
00198   *
00199 @verbatim
00200   ==============================================================================
00201               ##### Initialization and Configuration functions #####
00202   ==============================================================================
00203   [..]
00204   This subsection provides a set of functions allowing to initialize the USARTx
00205   associated to the SmartCard.
00206   [..]
00207   The Smartcard interface is designed to support asynchronous protocol Smartcards as
00208   defined in the ISO 7816-3 standard.
00209   [..]
00210   The USART can provide a clock to the smartcard through the SCLK output.
00211   In smartcard mode, SCLK is not associated to the communication but is simply derived
00212   from the internal peripheral input clock through a 5-bit prescaler.
00213   [..]
00214   (+) These parameters can be configured:
00215       (++) Baud Rate
00216       (++) Parity: should be enabled
00217       (++) Receiver/transmitter modes
00218       (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
00219       (++) Prescaler value
00220       (++) Guard bit time
00221       (++) NACK enabling or disabling on transmission error
00222
00223   (+) The following advanced features can be configured as well:
00224       (++) TX and/or RX pin level inversion
00225       (++) data logical level inversion
00226       (++) RX and TX pins swap
00227       (++) RX overrun detection disabling
00228       (++) DMA disabling on RX error
00229       (++) MSB first on communication line
00230       (++) Time out enabling (and if activated, timeout value)
00231       (++) Block length
00232       (++) Auto-retry counter
00233   [..]
00234   The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
00235   (details for the procedures are available in reference manual).
00236
00237 @endverbatim
00238   * @{
00239   */
00240
00241 /*
00242   Additional Table:
00243     Frame Length is fixed to 8 bits plus parity:
00244     SMARTCARD frame format is given in the following table:
00245     +---------------------------------------------------------------+
00246     | M1M0 bits |  PCE bit  |          SMARTCARD frame              |
00247     |-----------------------|---------------------------------------|
00248     |     01    |    1      |    | SB | 8 bit data | PB | STB |     |
00249     +---------------------------------------------------------------+
00250
00251 */
00252
00253 /**
00254   * @brief  Initialize the SMARTCARD mode according to the specified
00255   *         parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
00256   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00257   *                    the configuration information for the specified SMARTCARD module.
00258   * @retval HAL status
00259   */
00260 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
00261 {
00262   /* Check the SMARTCARD handle allocation */
00263   if(hsmartcard == NULL)
00264   {
00265     return HAL_ERROR;
00266   }
00267
00268   /* Check the USART associated to the SMARTCARD handle */
00269   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
00270
00271   if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
00272   {
00273     /* Allocate lock resource and initialize it */
00274     hsmartcard->Lock = HAL_UNLOCKED;
00275
00276     /* Init the low level hardware : GPIO, CLOCK */
00277     HAL_SMARTCARD_MspInit(hsmartcard);
00278   }
00279
00280   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00281
00282   /* Disable the Peripheral to set smartcard mode */
00283   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00284
00285   /* In SmartCard mode, the following bits must be kept cleared:
00286   - LINEN in the USART_CR2 register,
00287   - HDSEL and IREN  bits in the USART_CR3 register.*/
00288   CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
00289   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
00290
00291   /* set the USART in SMARTCARD mode */
00292   SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
00293
00294   /* Set the SMARTCARD Communication parameters */
00295   if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
00296   {
00297     return HAL_ERROR;
00298   }
00299
00300   if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
00301   {
00302     SMARTCARD_AdvFeatureConfig(hsmartcard);
00303   }
00304
00305   /* Enable the Peripheral */
00306   SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00307
00308   /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
00309   return (SMARTCARD_CheckIdleState(hsmartcard));
00310 }
00311
00312 /**
00313   * @brief  DeInitialize the SMARTCARD peripheral.
00314   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00315   *                    the configuration information for the specified SMARTCARD module.
00316   * @retval HAL status
00317   */
00318 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
00319 {
00320   /* Check the SMARTCARD handle allocation */
00321   if(hsmartcard == NULL)
00322   {
00323     return HAL_ERROR;
00324   }
00325
00326   /* Check the USART/UART associated to the SMARTCARD handle */
00327   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
00328
00329   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00330
00331   /* Disable the Peripheral */
00332   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00333
00334   WRITE_REG(hsmartcard->Instance->CR1, 0x0U);
00335   WRITE_REG(hsmartcard->Instance->CR2, 0x0U);
00336   WRITE_REG(hsmartcard->Instance->CR3, 0x0U);
00337   WRITE_REG(hsmartcard->Instance->RTOR, 0x0U);
00338   WRITE_REG(hsmartcard->Instance->GTPR, 0x0U);
00339
00340   /* DeInit the low level hardware */
00341   HAL_SMARTCARD_MspDeInit(hsmartcard);
00342
00343   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00344   hsmartcard->gState    = HAL_SMARTCARD_STATE_RESET;
00345   hsmartcard->RxState   = HAL_SMARTCARD_STATE_RESET;
00346
00347   /* Process Unlock */
00348   __HAL_UNLOCK(hsmartcard);
00349
00350   return HAL_OK;
00351 }
00352
00353 /**
00354   * @brief  Initialize the SMARTCARD MSP.
00355   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00356   *                    the configuration information for the specified SMARTCARD module.
00357   * @retval None
00358   */
00359 __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
00360 {
00361   /* Prevent unused argument(s) compilation warning */
00362   UNUSED(hsmartcard);
00363
00364   /* NOTE : This function should not be modified, when the callback is needed,
00365             the HAL_SMARTCARD_MspInit can be implemented in the user file
00366    */
00367 }
00368
00369 /**
00370   * @brief  DeInitialize the SMARTCARD MSP.
00371   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00372   *                    the configuration information for the specified SMARTCARD module.
00373   * @retval None
00374   */
00375 __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
00376 {
00377   /* Prevent unused argument(s) compilation warning */
00378   UNUSED(hsmartcard);
00379
00380   /* NOTE : This function should not be modified, when the callback is needed,
00381             the HAL_SMARTCARD_MspDeInit can be implemented in the user file
00382    */
00383 }
00384
00385 /**
00386   * @}
00387   */
00388
00389 /** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
00390   * @brief    SMARTCARD Transmit and Receive functions
00391   *
00392 @verbatim
00393   ==============================================================================
00394                          ##### IO operation functions #####
00395   ==============================================================================
00396   [..]
00397     This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
00398
00399   [..]
00400     Smartcard is a single wire half duplex communication protocol.
00401     The Smartcard interface is designed to support asynchronous protocol Smartcards as
00402     defined in the ISO 7816-3 standard. The USART should be configured as:
00403     (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
00404     (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
00405
00406   [..]
00407     (#) There are two modes of transfer:
00408         (++) Blocking mode: The communication is performed in polling mode.
00409              The HAL status of all data processing is returned by the same function
00410              after finishing transfer.
00411         (++) Non-Blocking mode: The communication is performed using Interrupts
00412              or DMA, the relevant API's return the HAL status.
00413              The end of the data processing will be indicated through the
00414              dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
00415              using DMA mode.
00416         (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
00417              will be executed respectively at the end of the Transmit or Receive process
00418              The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
00419              error is detected.
00420
00421     (#) Blocking mode APIs are :
00422         (++) HAL_SMARTCARD_Transmit()
00423         (++) HAL_SMARTCARD_Receive()
00424
00425     (#) Non Blocking mode APIs with Interrupt are :
00426         (++) HAL_SMARTCARD_Transmit_IT()
00427         (++) HAL_SMARTCARD_Receive_IT()
00428         (++) HAL_SMARTCARD_IRQHandler()
00429
00430     (#) Non Blocking mode functions with DMA are :
00431         (++) HAL_SMARTCARD_Transmit_DMA()
00432         (++) HAL_SMARTCARD_Receive_DMA()
00433
00434     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00435         (++) HAL_SMARTCARD_TxCpltCallback()
00436         (++) HAL_SMARTCARD_RxCpltCallback()
00437         (++) HAL_SMARTCARD_ErrorCallback()
00438
00439     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00440         (++) HAL_SMARTCARD_Abort()
00441         (++) HAL_SMARTCARD_AbortTransmit()
00442         (++) HAL_SMARTCARD_AbortReceive()
00443         (++) HAL_SMARTCARD_Abort_IT()
00444         (++) HAL_SMARTCARD_AbortTransmit_IT()
00445         (++) HAL_SMARTCARD_AbortReceive_IT()
00446
00447     (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
00448         (++) HAL_SMARTCARD_AbortCpltCallback()
00449         (++) HAL_SMARTCARD_AbortTransmitCpltCallback()
00450         (++) HAL_SMARTCARD_AbortReceiveCpltCallback()
00451
00452     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00453         Errors are handled as follows :
00454         (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00455              to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
00456              Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
00457              and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
00458              If user wants to abort it, Abort services should be called by user.
00459         (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00460              This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
00461              Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
00462
00463 @endverbatim
00464   * @{
00465   */
00466
00467 /**
00468   * @brief  Send an amount of data in blocking mode.
00469   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00470   *                    the configuration information for the specified SMARTCARD module.
00471   * @param  pData pointer to data buffer.
00472   * @param  Size amount of data to be sent.
00473   * @param  Timeout  Timeout duration.
00474   * @retval HAL status
00475   */
00476 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00477 {
00478   uint32_t tickstart = 0U;
00479
00480   /* Check that a Tx process is not already ongoing */
00481   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00482   {
00483     if((pData == NULL) || (Size == 0U))
00484     {
00485       return  HAL_ERROR;
00486     }
00487
00488     /* Process Locked */
00489     __HAL_LOCK(hsmartcard);
00490
00491     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00492
00493     /* Init tickstart for timeout managment*/
00494     tickstart = HAL_GetTick();
00495
00496     /* Disable the Peripheral first to update mode for TX master */
00497     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00498
00499     /* Disable Rx, enable Tx */
00500     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00501     SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
00502     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
00503
00504     /* Enable the Peripheral */
00505     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00506
00507     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00508     hsmartcard->TxXferSize = Size;
00509     hsmartcard->TxXferCount = Size;
00510
00511     while(hsmartcard->TxXferCount > 0U)
00512     {
00513       hsmartcard->TxXferCount--;
00514       if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00515       {
00516         return HAL_TIMEOUT;
00517       }
00518       hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
00519     }
00520     if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00521     {
00522       return HAL_TIMEOUT;
00523     }
00524     /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
00525     if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
00526     {
00527       /* Disable the Peripheral first to update modes */
00528       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00529       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00530       /* Enable the Peripheral */
00531       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00532     }
00533
00534     /* At end of Tx process, restore hsmartcard->gState to Ready */
00535     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00536
00537     /* Process Unlocked */
00538     __HAL_UNLOCK(hsmartcard);
00539
00540     return HAL_OK;
00541   }
00542   else
00543   {
00544     return HAL_BUSY;
00545   }
00546 }
00547
00548 /**
00549   * @brief  Receive an amount of data in blocking mode.
00550   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00551   *                    the configuration information for the specified SMARTCARD module.
00552   * @param  pData pointer to data buffer.
00553   * @param  Size amount of data to be received.
00554   * @param  Timeout Timeout duration.
00555   * @retval HAL status
00556   */
00557 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00558 {
00559   uint32_t tickstart = 0U;
00560
00561   /* Check that a Rx process is not already ongoing */
00562   if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
00563   {
00564     if((pData == NULL) || (Size == 0U))
00565     {
00566       return  HAL_ERROR;
00567     }
00568
00569     /* Process Locked */
00570     __HAL_LOCK(hsmartcard);
00571
00572     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00573     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
00574
00575     /* Init tickstart for timeout managment*/
00576     tickstart = HAL_GetTick();
00577
00578     hsmartcard->RxXferSize = Size;
00579     hsmartcard->RxXferCount = Size;
00580
00581     /* Check the remain data to be received */
00582     while(hsmartcard->RxXferCount > 0U)
00583     {
00584       hsmartcard->RxXferCount--;
00585
00586       if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00587       {
00588         return HAL_TIMEOUT;
00589       }
00590       *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
00591     }
00592
00593     /* At end of Rx process, restore hsmartcard->RxState to Ready */
00594     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
00595
00596     /* Process Unlocked */
00597     __HAL_UNLOCK(hsmartcard);
00598
00599     return HAL_OK;
00600   }
00601   else
00602   {
00603     return HAL_BUSY;
00604   }
00605 }
00606
00607 /**
00608   * @brief  Send an amount of data in interrupt mode.
00609   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00610   *                    the configuration information for the specified SMARTCARD module.
00611   * @param  pData pointer to data buffer.
00612   * @param  Size amount of data to be sent.
00613   * @retval HAL status
00614   */
00615 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
00616 {
00617   /* Check that a Tx process is not already ongoing */
00618   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00619   {
00620     if((pData == NULL) || (Size == 0U))
00621     {
00622       return HAL_ERROR;
00623     }
00624
00625     /* Process Locked */
00626     __HAL_LOCK(hsmartcard);
00627
00628     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00629     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00630
00631     hsmartcard->pTxBuffPtr = pData;
00632     hsmartcard->TxXferSize = Size;
00633     hsmartcard->TxXferCount = Size;
00634
00635     /* Disable the Peripheral first to update mode for TX master */
00636     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00637
00638     /* Disable Rx, enable Tx */
00639     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00640     SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
00641     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
00642
00643     /* Enable the Peripheral */
00644     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00645
00646     /* Process Unlocked */
00647     __HAL_UNLOCK(hsmartcard);
00648
00649     /* Enable the SMARTCARD Error Interrupt: (Frame error) */
00650     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
00651
00652     /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
00653     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
00654
00655     return HAL_OK;
00656   }
00657   else
00658   {
00659     return HAL_BUSY;
00660   }
00661 }
00662
00663 /**
00664   * @brief  Receive an amount of data in interrupt mode.
00665   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00666   *                    the configuration information for the specified SMARTCARD module.
00667   * @param  pData pointer to data buffer.
00668   * @param  Size amount of data to be received.
00669   * @retval HAL status
00670   */
00671 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
00672 {
00673   /* Check that a Rx process is not already ongoing */
00674   if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
00675   {
00676     if((pData == NULL) || (Size == 0U))
00677     {
00678       return HAL_ERROR;
00679     }
00680
00681     /* Process Locked */
00682     __HAL_LOCK(hsmartcard);
00683
00684     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00685     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
00686
00687     hsmartcard->pRxBuffPtr = pData;
00688     hsmartcard->RxXferSize = Size;
00689     hsmartcard->RxXferCount = Size;
00690
00691     /* Process Unlocked */
00692     __HAL_UNLOCK(hsmartcard);
00693
00694     /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
00695     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
00696
00697     /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
00698     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
00699
00700     return HAL_OK;
00701   }
00702   else
00703   {
00704     return HAL_BUSY;
00705   }
00706 }
00707
00708 /**
00709   * @brief  Send an amount of data in DMA mode.
00710   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00711   *                    the configuration information for the specified SMARTCARD module.
00712   * @param  pData pointer to data buffer.
00713   * @param  Size amount of data to be sent.
00714   * @retval HAL status
00715   */
00716 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
00717 {
00718   /* Check that a Tx process is not already ongoing */
00719   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00720   {
00721     if((pData == NULL) || (Size == 0U))
00722     {
00723       return HAL_ERROR;
00724     }
00725
00726     /* Process Locked */
00727     __HAL_LOCK(hsmartcard);
00728
00729     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00730
00731     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00732     hsmartcard->pTxBuffPtr = pData;
00733     hsmartcard->TxXferSize = Size;
00734     hsmartcard->TxXferCount = Size;
00735
00736     /* Disable the Peripheral first to update mode for TX master */
00737     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00738
00739     /* Disable Rx, enable Tx */
00740     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00741     SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
00742     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
00743
00744     /* Enable the Peripheral */
00745     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00746
00747     /* Set the SMARTCARD DMA transfer complete callback */
00748     hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
00749
00750     /* Set the SMARTCARD error callback */
00751     hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
00752
00753     /* Set the DMA abort callback */
00754     hsmartcard->hdmatx->XferAbortCallback = NULL;
00755
00756     /* Enable the SMARTCARD transmit DMA channel */
00757     HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size);
00758
00759     /* Clear the TC flag in the ICR register */
00760     CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
00761
00762     /* Process Unlocked */
00763     __HAL_UNLOCK(hsmartcard);
00764
00765     /* Enable the UART Error Interrupt: (Frame error) */
00766     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
00767
00768     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00769        in the SMARTCARD associated USART CR3 register */
00770     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
00771
00772     return HAL_OK;
00773   }
00774   else
00775   {
00776     return HAL_BUSY;
00777   }
00778 }
00779
00780 /**
00781   * @brief  Receive an amount of data in DMA mode.
00782   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00783   *                    the configuration information for the specified SMARTCARD module.
00784   * @param  pData pointer to data buffer.
00785   * @param  Size amount of data to be received.
00786   * @note   The SMARTCARD-associated USART parity is enabled (PCE = 1),
00787   *         the received data contain the parity bit (MSB position).
00788   * @retval HAL status
00789   */
00790 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
00791 {
00792   /* Check that a Rx process is not already ongoing */
00793   if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
00794   {
00795     if((pData == NULL) || (Size == 0U))
00796     {
00797       return HAL_ERROR;
00798     }
00799
00800     /* Process Locked */
00801     __HAL_LOCK(hsmartcard);
00802
00803     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00804     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
00805
00806     hsmartcard->pRxBuffPtr = pData;
00807     hsmartcard->RxXferSize = Size;
00808
00809     /* Set the SMARTCARD DMA transfer complete callback */
00810     hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
00811
00812     /* Set the SMARTCARD DMA error callback */
00813     hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
00814
00815     /* Set the DMA abort callback */
00816     hsmartcard->hdmarx->XferAbortCallback = NULL;
00817
00818     /* Enable the DMA channel */
00819     HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size);
00820
00821     /* Process Unlocked */
00822     __HAL_UNLOCK(hsmartcard);
00823
00824     /* Enable the UART Parity Error Interrupt */
00825     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
00826
00827     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
00828     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
00829
00830     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00831        in the SMARTCARD associated USART CR3 register */
00832     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
00833
00834     return HAL_OK;
00835   }
00836   else
00837   {
00838     return HAL_BUSY;
00839   }
00840 }
00841
00842 /**
00843   * @brief  Abort ongoing transfers (blocking mode).
00844   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00845   *                    the configuration information for the specified SMARTCARD module.
00846   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
00847   *         This procedure performs following operations :
00848   *           - Disable SMARTCARD Interrupts (Tx and Rx)
00849   *           - Disable the DMA transfer in the peripheral register (if enabled)
00850   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
00851   *           - Set handle State to READY
00852   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
00853   * @retval HAL status
00854 */
00855 HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
00856 {
00857   /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
00858   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
00859   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
00860
00861   /* Disable the SMARTCARD DMA Tx request if enabled */
00862   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
00863   {
00864     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
00865
00866     /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
00867     if(hsmartcard->hdmatx != NULL)
00868     {
00869       /* Set the SMARTCARD DMA Abort callback to Null.
00870          No call back execution at end of DMA abort procedure */
00871       hsmartcard->hdmatx->XferAbortCallback = NULL;
00872
00873       HAL_DMA_Abort(hsmartcard->hdmatx);
00874     }
00875   }
00876
00877   /* Disable the SMARTCARD DMA Rx request if enabled */
00878   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
00879   {
00880     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
00881
00882     /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
00883     if(hsmartcard->hdmarx != NULL)
00884     {
00885       /* Set the SMARTCARD DMA Abort callback to Null.
00886          No call back execution at end of DMA abort procedure */
00887       hsmartcard->hdmarx->XferAbortCallback = NULL;
00888
00889       HAL_DMA_Abort(hsmartcard->hdmarx);
00890     }
00891   }
00892
00893   /* Reset Tx and Rx transfer counters */
00894   hsmartcard->TxXferCount = 0U;
00895   hsmartcard->RxXferCount = 0U;
00896
00897   /* Clear the Error flags in the ICR register */
00898   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
00899
00900   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
00901   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
00902   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
00903
00904   /* Reset Handle ErrorCode to No Error */
00905   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00906
00907   return HAL_OK;
00908 }
00909
00910 /**
00911   * @brief  Abort ongoing Transmit transfer (blocking mode).
00912   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00913   *                    the configuration information for the specified SMARTCARD module.
00914   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
00915   *         This procedure performs following operations :
00916   *           - Disable SMARTCARD Interrupts (Tx)
00917   *           - Disable the DMA transfer in the peripheral register (if enabled)
00918   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
00919   *           - Set handle State to READY
00920   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
00921   * @retval HAL status
00922 */
00923 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
00924 {
00925   /* Disable TXEIE and TCIE interrupts */
00926   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
00927
00928   /* Check if a receive process is ongoing or not. If not disable ERR IT */
00929   if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
00930   {
00931     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
00932     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
00933   }
00934
00935   /* Disable the SMARTCARD DMA Tx request if enabled */
00936   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
00937   {
00938     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
00939
00940     /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
00941     if(hsmartcard->hdmatx != NULL)
00942     {
00943       /* Set the SMARTCARD DMA Abort callback to Null.
00944          No call back execution at end of DMA abort procedure */
00945       hsmartcard->hdmatx->XferAbortCallback = NULL;
00946
00947       HAL_DMA_Abort(hsmartcard->hdmatx);
00948     }
00949   }
00950
00951   /* Reset Tx transfer counter */
00952   hsmartcard->TxXferCount = 0U;
00953
00954   /* Clear the Error flags in the ICR register */
00955   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
00956
00957   /* Restore hsmartcard->gState to Ready */
00958   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00959
00960   return HAL_OK;
00961 }
00962
00963 /**
00964   * @brief  Abort ongoing Receive transfer (blocking mode).
00965   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00966   *                    the configuration information for the specified SMARTCARD module.
00967   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
00968   *         This procedure performs following operations :
00969   *           - Disable SMARTCARD Interrupts (Rx)
00970   *           - Disable the DMA transfer in the peripheral register (if enabled)
00971   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
00972   *           - Set handle State to READY
00973   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
00974   * @retval HAL status
00975 */
00976 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
00977 {
00978   /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
00979   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
00980
00981   /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
00982   if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00983   {
00984     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
00985     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
00986   }
00987
00988   /* Disable the SMARTCARD DMA Rx request if enabled */
00989   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
00990   {
00991     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
00992
00993     /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
00994     if(hsmartcard->hdmarx != NULL)
00995     {
00996       /* Set the SMARTCARD DMA Abort callback to Null.
00997          No call back execution at end of DMA abort procedure */
00998       hsmartcard->hdmarx->XferAbortCallback = NULL;
00999
01000       HAL_DMA_Abort(hsmartcard->hdmarx);
01001     }
01002   }
01003
01004   /* Reset Rx transfer counter */
01005   hsmartcard->RxXferCount = 0U;
01006
01007   /* Clear the Error flags in the ICR register */
01008   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01009
01010   /* Restore hsmartcard->RxState to Ready */
01011   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01012
01013   return HAL_OK;
01014 }
01015
01016 /**
01017   * @brief  Abort ongoing transfers (Interrupt mode).
01018   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01019   *                    the configuration information for the specified SMARTCARD module.
01020   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01021   *         This procedure performs following operations :
01022   *           - Disable SMARTCARD Interrupts (Tx and Rx)
01023   *           - Disable the DMA transfer in the peripheral register (if enabled)
01024   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01025   *           - Set handle State to READY
01026   *           - At abort completion, call user abort complete callback
01027   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01028   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01029   * @retval HAL status
01030 */
01031 HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01032 {
01033   uint32_t abortcplt = 1U;
01034
01035   /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01036   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
01037   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01038
01039   /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
01040      before any call to DMA Abort functions */
01041   /* DMA Tx Handle is valid */
01042   if(hsmartcard->hdmatx != NULL)
01043   {
01044     /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
01045        Otherwise, set it to NULL */
01046     if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01047     {
01048       hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
01049     }
01050     else
01051     {
01052       hsmartcard->hdmatx->XferAbortCallback = NULL;
01053     }
01054   }
01055   /* DMA Rx Handle is valid */
01056   if(hsmartcard->hdmarx != NULL)
01057   {
01058     /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
01059        Otherwise, set it to NULL */
01060     if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01061     {
01062       hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
01063     }
01064     else
01065     {
01066       hsmartcard->hdmarx->XferAbortCallback = NULL;
01067     }
01068   }
01069
01070   /* Disable the SMARTCARD DMA Tx request if enabled */
01071   if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01072   {
01073     /* Disable DMA Tx at UART level */
01074     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01075
01076     /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
01077     if(hsmartcard->hdmatx != NULL)
01078     {
01079       /* SMARTCARD Tx DMA Abort callback has already been initialised :
01080          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01081
01082       /* Abort DMA TX */
01083       if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
01084       {
01085         hsmartcard->hdmatx->XferAbortCallback = NULL;
01086       }
01087       else
01088       {
01089         abortcplt = 0U;
01090       }
01091     }
01092   }
01093
01094   /* Disable the SMARTCARD DMA Rx request if enabled */
01095   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01096   {
01097     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01098
01099     /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
01100     if(hsmartcard->hdmarx != NULL)
01101     {
01102       /* SMARTCARD Rx DMA Abort callback has already been initialised :
01103          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01104
01105       /* Abort DMA RX */
01106       if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01107       {
01108         hsmartcard->hdmarx->XferAbortCallback = NULL;
01109         abortcplt = 1U;
01110       }
01111       else
01112       {
01113         abortcplt = 0U;
01114       }
01115     }
01116   }
01117
01118   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01119   if (abortcplt == 1U)
01120   {
01121     /* Reset Tx and Rx transfer counters */
01122     hsmartcard->TxXferCount = 0U;
01123     hsmartcard->RxXferCount = 0U;
01124
01125     /* Reset errorCode */
01126     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01127
01128     /* Clear the Error flags in the ICR register */
01129     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01130
01131     /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
01132     hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
01133     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01134
01135     /* As no DMA to be aborted, call directly user Abort complete callback */
01136     HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
01137   }
01138
01139   return HAL_OK;
01140 }
01141
01142 /**
01143   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01144   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01145   *                    the configuration information for the specified SMARTCARD module.
01146   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01147   *         This procedure performs following operations :
01148   *           - Disable SMARTCARD Interrupts (Tx)
01149   *           - Disable the DMA transfer in the peripheral register (if enabled)
01150   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01151   *           - Set handle State to READY
01152   *           - At abort completion, call user abort complete callback
01153   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01154   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01155   * @retval HAL status
01156 */
01157 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01158 {
01159   /* Disable TXEIE and TCIE interrupts */
01160   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01161
01162   /* Check if a receive process is ongoing or not. If not disable ERR IT */
01163   if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01164   {
01165     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01166     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01167   }
01168
01169   /* Disable the SMARTCARD DMA Tx request if enabled */
01170   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01171   {
01172     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01173
01174     /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
01175     if(hsmartcard->hdmatx != NULL)
01176     {
01177       /* Set the SMARTCARD DMA Abort callback :
01178          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01179       hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
01180
01181       /* Abort DMA TX */
01182       if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
01183       {
01184         /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
01185         hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
01186       }
01187     }
01188     else
01189     {
01190       /* Reset Tx transfer counter */
01191       hsmartcard->TxXferCount = 0U;
01192
01193       /* Restore hsmartcard->gState to Ready */
01194       hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01195
01196       /* As no DMA to be aborted, call directly user Abort complete callback */
01197       HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
01198     }
01199   }
01200   else
01201   {
01202     /* Reset Tx transfer counter */
01203     hsmartcard->TxXferCount = 0U;
01204
01205     /* Clear the Error flags in the ICR register */
01206     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
01207
01208     /* Restore hsmartcard->gState to Ready */
01209     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01210
01211     /* As no DMA to be aborted, call directly user Abort complete callback */
01212     HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
01213   }
01214
01215   return HAL_OK;
01216 }
01217
01218 /**
01219   * @brief  Abort ongoing Receive transfer (Interrupt mode).
01220   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01221   *                    the configuration information for the specified SMARTCARD module.
01222   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01223   *         This procedure performs following operations :
01224   *           - Disable SMARTCARD Interrupts (Rx)
01225   *           - Disable the DMA transfer in the peripheral register (if enabled)
01226   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01227   *           - Set handle State to READY
01228   *           - At abort completion, call user abort complete callback
01229   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01230   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01231   * @retval HAL status
01232 */
01233 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01234 {
01235   /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01236   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
01237
01238   /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
01239   if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
01240   {
01241     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01242     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01243   }
01244
01245   /* Disable the SMARTCARD DMA Rx request if enabled */
01246   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01247   {
01248     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01249
01250     /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
01251     if(hsmartcard->hdmarx != NULL)
01252     {
01253       /* Set the SMARTCARD DMA Abort callback :
01254          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01255       hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
01256
01257       /* Abort DMA RX */
01258       if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01259       {
01260         /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
01261         hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
01262       }
01263     }
01264     else
01265     {
01266       /* Reset Rx transfer counter */
01267       hsmartcard->RxXferCount = 0U;
01268
01269       /* Clear the Error flags in the ICR register */
01270       __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01271
01272       /* Restore hsmartcard->RxState to Ready */
01273       hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01274
01275       /* As no DMA to be aborted, call directly user Abort complete callback */
01276       HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
01277     }
01278   }
01279   else
01280   {
01281     /* Reset Rx transfer counter */
01282     hsmartcard->RxXferCount = 0U;
01283
01284     /* Clear the Error flags in the ICR register */
01285     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01286
01287     /* Restore hsmartcard->RxState to Ready */
01288     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01289
01290     /* As no DMA to be aborted, call directly user Abort complete callback */
01291     HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
01292   }
01293
01294   return HAL_OK;
01295 }
01296
01297 /**
01298   * @brief Handle SMARTCARD interrupt requests.
01299   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01300   *                    the configuration information for the specified SMARTCARD module.
01301   * @retval None
01302   */
01303 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
01304 {
01305   uint32_t isrflags   = READ_REG(hsmartcard->Instance->ISR);
01306   uint32_t cr1its     = READ_REG(hsmartcard->Instance->CR1);
01307   uint32_t cr3its;
01308   uint32_t errorflags;
01309
01310   /* If no error occurs */
01311   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
01312   if (errorflags == RESET)
01313   {
01314     /* SMARTCARD in mode Receiver ---------------------------------------------------*/
01315     if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01316     {
01317       SMARTCARD_Receive_IT(hsmartcard);
01318       /* Clear RXNE interrupt flag done by reading RDR in SMARTCARD_Receive_IT() */
01319       return;
01320     }
01321   }
01322
01323   /* If some errors occur */
01324   cr3its = READ_REG(hsmartcard->Instance->CR3);
01325   if(   (errorflags != RESET)
01326      && (    ((cr3its & USART_CR3_EIE) != RESET)
01327           || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != RESET)) )
01328   {
01329     /* SMARTCARD parity error interrupt occurred -------------------------------------*/
01330     if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
01331     {
01332       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
01333
01334       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
01335     }
01336
01337     /* SMARTCARD frame error interrupt occurred --------------------------------------*/
01338     if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01339     {
01340       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
01341
01342       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
01343     }
01344
01345     /* SMARTCARD noise error interrupt occurred --------------------------------------*/
01346     if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01347     {
01348       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
01349
01350       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
01351     }
01352
01353     /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
01354     if(((isrflags & USART_ISR_ORE) != RESET) &&
01355        (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
01356     {
01357       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
01358
01359       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
01360     }
01361
01362     /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
01363     if(((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET))
01364     {
01365       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
01366
01367       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
01368     }
01369
01370     /* Call SMARTCARD Error Call back function if need be --------------------------*/
01371     if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
01372     {
01373       /* SMARTCARD in mode Receiver ---------------------------------------------------*/
01374       if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01375       {
01376         SMARTCARD_Receive_IT(hsmartcard);
01377       }
01378
01379       /* If Error is to be considered as blocking :
01380           - Receiver Timeout error in Reception
01381           - Overrun error in Reception
01382           - any error occurs in DMA mode reception
01383       */
01384       if (   ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET)
01385           || (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)))
01386       {
01387         /* Blocking error : transfer is aborted
01388            Set the SMARTCARD state ready to be able to start again the process,
01389            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01390         SMARTCARD_EndRxTransfer(hsmartcard);
01391
01392         /* Disable the SMARTCARD DMA Rx request if enabled */
01393         if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01394         {
01395           CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01396
01397           /* Abort the SMARTCARD DMA Rx channel */
01398           if(hsmartcard->hdmarx != NULL)
01399           {
01400             /* Set the SMARTCARD DMA Abort callback :
01401                will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
01402             hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
01403
01404             /* Abort DMA RX */
01405             if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01406             {
01407               /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
01408               hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
01409             }
01410           }
01411           else
01412           {
01413             /* Call user error callback */
01414             HAL_SMARTCARD_ErrorCallback(hsmartcard);
01415           }
01416         }
01417         else
01418         {
01419           /* Call user error callback */
01420           HAL_SMARTCARD_ErrorCallback(hsmartcard);
01421         }
01422       }
01423       /* other error type to be considered as blocking :
01424           - Frame error in Transmission
01425       */
01426       else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET))
01427       {
01428         /* Blocking error : transfer is aborted
01429            Set the SMARTCARD state ready to be able to start again the process,
01430            Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
01431         SMARTCARD_EndTxTransfer(hsmartcard);
01432
01433         /* Disable the SMARTCARD DMA Tx request if enabled */
01434         if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01435         {
01436           CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01437
01438           /* Abort the SMARTCARD DMA Tx channel */
01439           if(hsmartcard->hdmatx != NULL)
01440           {
01441             /* Set the SMARTCARD DMA Abort callback :
01442                will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
01443             hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
01444
01445             /* Abort DMA TX */
01446             if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
01447             {
01448               /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
01449               hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
01450             }
01451           }
01452           else
01453           {
01454             /* Call user error callback */
01455             HAL_SMARTCARD_ErrorCallback(hsmartcard);
01456           }
01457         }
01458         else
01459         {
01460           /* Call user error callback */
01461           HAL_SMARTCARD_ErrorCallback(hsmartcard);
01462         }
01463       }
01464       else
01465       {
01466         /* Non Blocking error : transfer could go on.
01467            Error is notified to user through user error callback */
01468         HAL_SMARTCARD_ErrorCallback(hsmartcard);
01469         hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01470       }
01471     }
01472     return;
01473
01474   } /* End if some error occurs */
01475
01476   /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
01477   if(((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET))
01478   {
01479     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01480     __HAL_UNLOCK(hsmartcard);
01481     HAL_SMARTCARD_RxCpltCallback(hsmartcard);
01482     /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
01483      * to be available during HAL_SMARTCARD_RxCpltCallback() processing */
01484     __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
01485     return;
01486   }
01487
01488   /* SMARTCARD in mode Transmitter ------------------------------------------------*/
01489   if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
01490   {
01491     SMARTCARD_Transmit_IT(hsmartcard);
01492     return;
01493   }
01494
01495   /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
01496   if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET))
01497   {
01498     SMARTCARD_EndTransmit_IT(hsmartcard);
01499     return;
01500   }
01501 }
01502
01503 /**
01504   * @brief  Tx Transfer completed callback.
01505   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01506   *                    the configuration information for the specified SMARTCARD module.
01507   * @retval None
01508   */
01509 __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
01510 {
01511   /* Prevent unused argument(s) compilation warning */
01512   UNUSED(hsmartcard);
01513
01514   /* NOTE : This function should not be modified, when the callback is needed,
01515             the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
01516    */
01517 }
01518
01519 /**
01520   * @brief  Rx Transfer completed callback.
01521   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01522   *                    the configuration information for the specified SMARTCARD module.
01523   * @retval None
01524   */
01525 __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
01526 {
01527   /* Prevent unused argument(s) compilation warning */
01528   UNUSED(hsmartcard);
01529
01530   /* NOTE : This function should not be modified, when the callback is needed,
01531             the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
01532    */
01533 }
01534
01535 /**
01536   * @brief  SMARTCARD error callback.
01537   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01538   *                    the configuration information for the specified SMARTCARD module.
01539   * @retval None
01540   */
01541 __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
01542 {
01543   /* Prevent unused argument(s) compilation warning */
01544   UNUSED(hsmartcard);
01545
01546   /* NOTE : This function should not be modified, when the callback is needed,
01547             the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
01548    */
01549 }
01550
01551 /**
01552   * @brief  SMARTCARD Abort Complete callback.
01553   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01554   *                    the configuration information for the specified SMARTCARD module.
01555   * @retval None
01556   */
01557 __weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
01558 {
01559   /* Prevent unused argument(s) compilation warning */
01560   UNUSED(hsmartcard);
01561
01562   /* NOTE : This function should not be modified, when the callback is needed,
01563             the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
01564    */
01565 }
01566
01567 /**
01568   * @brief  SMARTCARD Abort Complete callback.
01569   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01570   *                    the configuration information for the specified SMARTCARD module.
01571   * @retval None
01572   */
01573 __weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
01574 {
01575   /* Prevent unused argument(s) compilation warning */
01576   UNUSED(hsmartcard);
01577
01578   /* NOTE : This function should not be modified, when the callback is needed,
01579             the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
01580    */
01581 }
01582
01583 /**
01584   * @brief  SMARTCARD Abort Receive Complete callback.
01585   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01586   *                    the configuration information for the specified SMARTCARD module.
01587   * @retval None
01588   */
01589 __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
01590 {
01591   /* Prevent unused argument(s) compilation warning */
01592   UNUSED(hsmartcard);
01593
01594   /* NOTE : This function should not be modified, when the callback is needed,
01595             the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
01596    */
01597 }
01598
01599 /**
01600   * @}
01601   */
01602
01603 /** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
01604   *  @brief   SMARTCARD State and Errors functions
01605   *
01606 @verbatim
01607   ==============================================================================
01608                   ##### Peripheral State and Errors functions #####
01609   ==============================================================================
01610   [..]
01611     This subsection provides a set of functions allowing to return the State of SmartCard
01612     handle and also return Peripheral Errors occurred during communication process
01613      (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
01614          of the SMARTCARD peripheral.
01615      (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
01616          communication.
01617
01618 @endverbatim
01619   * @{
01620   */
01621
01622 /**
01623   * @brief  Return the SMARTCARD handle state.
01624   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01625   *                    the configuration information for the specified SMARTCARD module.
01626   * @retval SMARTCARD handle state
01627   */
01628 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
01629 {
01630   /* Return SMARTCARD handle state */
01631   uint32_t temp1= 0x00U, temp2 = 0x00U;
01632   temp1 = hsmartcard->gState;
01633   temp2 = hsmartcard->RxState;
01634
01635   return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
01636 }
01637
01638 /**
01639   * @brief  Return the SMARTCARD handle error code.
01640   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01641   *                    the configuration information for the specified SMARTCARD module.
01642   * @retval SMARTCARD handle Error Code
01643 */
01644 uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
01645 {
01646   return hsmartcard->ErrorCode;
01647 }
01648
01649 /**
01650   * @}
01651   */
01652
01653 /**
01654   * @}
01655   */
01656
01657 /** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
01658   * @{
01659   */
01660
01661 /**
01662   * @brief  Configure the SMARTCARD associated USART peripheral.
01663   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01664   *                     the configuration information for the specified SMARTCARD module.
01665   * @retval HAL status
01666   */
01667 static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
01668 {
01669   uint32_t tmpreg                          = 0x00000000U;
01670   SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED;
01671   HAL_StatusTypeDef ret                    = HAL_OK;
01672
01673   /* Check the parameters */
01674   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
01675   assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
01676   assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
01677   assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
01678   assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
01679   assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
01680   assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
01681   assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
01682   assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
01683   assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
01684   assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
01685   assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
01686   assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
01687
01688   /*-------------------------- USART CR1 Configuration -----------------------*/
01689   /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
01690    * Oversampling is forced to 16 (OVER8 = 0).
01691    * Configure the Parity and Mode:
01692    *  set PS bit according to hsmartcard->Init.Parity value
01693    *  set TE and RE bits according to hsmartcard->Init.Mode value */
01694   tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
01695   tmpreg |= (uint32_t) hsmartcard->Init.WordLength;
01696   MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
01697
01698   /*-------------------------- USART CR2 Configuration -----------------------*/
01699   tmpreg = hsmartcard->Init.StopBits;
01700   /* Synchronous mode is activated by default */
01701   tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
01702   tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
01703   tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
01704   MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
01705
01706   /*-------------------------- USART CR3 Configuration -----------------------*/
01707   /* Configure
01708    * - one-bit sampling method versus three samples' majority rule
01709    *   according to hsmartcard->Init.OneBitSampling
01710    * - NACK transmission in case of parity error according
01711    *   to hsmartcard->Init.NACKEnable
01712    * - autoretry counter according to hsmartcard->Init.AutoRetryCount     */
01713   tmpreg =  (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
01714   tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
01715   MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
01716
01717   /*-------------------------- USART GTPR Configuration ----------------------*/
01718   tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
01719   MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
01720
01721   /*-------------------------- USART RTOR Configuration ----------------------*/
01722   tmpreg =   ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
01723   if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
01724   {
01725     assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
01726     tmpreg |=  (uint32_t) hsmartcard->Init.TimeOutValue;
01727   }
01728   MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
01729
01730   /*-------------------------- USART BRR Configuration -----------------------*/
01731   SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
01732   switch (clocksource)
01733   {
01734     case SMARTCARD_CLOCKSOURCE_PCLK1:
01735       hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
01736       break;
01737     case SMARTCARD_CLOCKSOURCE_PCLK2:
01738       hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
01739       break;
01740     case SMARTCARD_CLOCKSOURCE_HSI:
01741       hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
01742       break;
01743     case SMARTCARD_CLOCKSOURCE_SYSCLK:
01744       hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
01745       break;
01746     case SMARTCARD_CLOCKSOURCE_LSE:
01747       hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
01748       break;
01749     case SMARTCARD_CLOCKSOURCE_UNDEFINED:
01750     default:
01751       ret = HAL_ERROR;
01752       break;
01753   }
01754
01755   return ret;
01756 }
01757
01758
01759 /**
01760   * @brief  Configure the SMARTCARD associated USART peripheral advanced features.
01761   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01762   *                     the configuration information for the specified SMARTCARD module.
01763   * @retval None
01764   */
01765 static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
01766 {
01767   /* Check whether the set of advanced features to configure is properly set */
01768   assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
01769
01770   /* if required, configure TX pin active level inversion */
01771   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
01772   {
01773     assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
01774     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
01775   }
01776
01777   /* if required, configure RX pin active level inversion */
01778   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
01779   {
01780     assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
01781     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
01782   }
01783
01784   /* if required, configure data inversion */
01785   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
01786   {
01787     assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
01788     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
01789   }
01790
01791   /* if required, configure RX/TX pins swap */
01792   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
01793   {
01794     assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
01795     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
01796   }
01797
01798   /* if required, configure RX overrun detection disabling */
01799   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
01800   {
01801     assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
01802     MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
01803   }
01804
01805   /* if required, configure DMA disabling on reception error */
01806   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
01807   {
01808     assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
01809     MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
01810   }
01811
01812   /* if required, configure MSB first on communication line */
01813   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
01814   {
01815     assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
01816     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
01817   }
01818
01819 }
01820
01821 /**
01822   * @brief  Check the SMARTCARD Idle State.
01823   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01824   *                     the configuration information for the specified SMARTCARD module.
01825   * @retval HAL status
01826   */
01827 static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
01828 {
01829   uint32_t tickstart = 0U;
01830
01831   /* Initialize the SMARTCARD ErrorCode */
01832   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01833
01834   /* Init tickstart for timeout managment*/
01835   tickstart = HAL_GetTick();
01836
01837   /* Check if the Transmitter is enabled */
01838   if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
01839   {
01840     /* Wait until TEACK flag is set */
01841     if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
01842     {
01843       /* Timeout occurred */
01844       return HAL_TIMEOUT;
01845     }
01846   }
01847
01848   /* Check if the Receiver is enabled */
01849   if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
01850   {
01851     /* Wait until REACK flag is set */
01852     if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
01853     {
01854       /* Timeout occurred */
01855       return HAL_TIMEOUT;
01856     }
01857   }
01858
01859   /* Initialize the SMARTCARD states */
01860   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
01861   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01862
01863   /* Process Unlocked */
01864   __HAL_UNLOCK(hsmartcard);
01865
01866   return HAL_OK;
01867 }
01868
01869 /**
01870   * @brief  Handle SMARTCARD Communication Timeout.
01871   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01872   *                    the configuration information for the specified SMARTCARD module.
01873   * @param  Flag Specifies the SMARTCARD flag to check.
01874   * @param  Status The new Flag status (SET or RESET).
01875   * @param  Tickstart Tick start value
01876   * @param  Timeout Timeout duration.
01877   * @retval HAL status
01878   */
01879 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
01880 {
01881   /* Wait until flag is set */
01882   while((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
01883   {
01884     /* Check for the Timeout */
01885     if(Timeout != HAL_MAX_DELAY)
01886     {
01887       if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
01888       {
01889         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01890         CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
01891         CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01892
01893         hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
01894         hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01895
01896         /* Process Unlocked */
01897         __HAL_UNLOCK(hsmartcard);
01898         return HAL_TIMEOUT;
01899       }
01900     }
01901   }
01902   return HAL_OK;
01903 }
01904
01905
01906 /**
01907   * @brief  End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
01908   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01909   *               the configuration information for the specified SMARTCARD module.
01910   * @retval None
01911   */
01912 static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
01913 {
01914   /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
01915   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01916   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01917
01918   /* At end of Tx process, restore hsmartcard->gState to Ready */
01919   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01920 }
01921
01922
01923 /**
01924   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
01925   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01926   *               the configuration information for the specified SMARTCARD module.
01927   * @retval None
01928   */
01929 static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
01930 {
01931   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01932   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01933   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01934
01935   /* At end of Rx process, restore hsmartcard->RxState to Ready */
01936   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01937 }
01938
01939
01940 /**
01941   * @brief  DMA SMARTCARD transmit process complete callback.
01942   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
01943   *              the configuration information for the specified DMA module.
01944   * @retval None
01945   */
01946 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01947 {
01948   SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
01949   hsmartcard->TxXferCount = 0U;
01950
01951   /* Disable the DMA transfer for transmit request by resetting the DMAT bit
01952   in the SMARTCARD associated USART CR3 register */
01953   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01954
01955   /* Enable the SMARTCARD Transmit Complete Interrupt */
01956   __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
01957 }
01958
01959 /**
01960   * @brief  DMA SMARTCARD receive process complete callback.
01961   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
01962   *              the configuration information for the specified DMA module.
01963   * @retval None
01964   */
01965 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01966 {
01967   SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
01968   hsmartcard->RxXferCount = 0U;
01969
01970   /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01971   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
01972   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01973
01974   /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
01975      in the SMARTCARD associated USART CR3 register */
01976   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01977
01978   /* At end of Rx process, restore hsmartcard->RxState to Ready */
01979   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01980
01981   HAL_SMARTCARD_RxCpltCallback(hsmartcard);
01982 }
01983
01984 /**
01985   * @brief  DMA SMARTCARD communication error callback.
01986   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
01987   *              the configuration information for the specified DMA module.
01988   * @retval None
01989   */
01990 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
01991 {
01992   SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
01993
01994   /* Stop SMARTCARD DMA Tx request if ongoing */
01995   if (  (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
01996       &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) )
01997   {
01998     hsmartcard->TxXferCount = 0U;
01999     SMARTCARD_EndTxTransfer(hsmartcard);
02000   }
02001
02002   /* Stop SMARTCARD DMA Rx request if ongoing */
02003   if (  (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
02004       &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) )
02005   {
02006     hsmartcard->RxXferCount = 0U;
02007     SMARTCARD_EndRxTransfer(hsmartcard);
02008   }
02009
02010   hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
02011   HAL_SMARTCARD_ErrorCallback(hsmartcard);
02012 }
02013
02014 /**
02015   * @brief  DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
02016   *         (To be called at end of DMA Abort procedure following error occurrence).
02017   * @param  hdma DMA handle.
02018   * @retval None
02019   */
02020 static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02021 {
02022   SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
02023   hsmartcard->RxXferCount = 0U;
02024   hsmartcard->TxXferCount = 0U;
02025
02026   HAL_SMARTCARD_ErrorCallback(hsmartcard);
02027 }
02028
02029 /**
02030   * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user
02031   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02032   * @note   When this callback is executed, User Abort complete call back is called only if no
02033   *         Abort still ongoing for Rx DMA Handle.
02034   * @param  hdma DMA handle.
02035   * @retval None
02036   */
02037 static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02038 {
02039   SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
02040
02041   hsmartcard->hdmatx->XferAbortCallback = NULL;
02042
02043   /* Check if an Abort process is still ongoing */
02044   if(hsmartcard->hdmarx != NULL)
02045   {
02046     if(hsmartcard->hdmarx->XferAbortCallback != NULL)
02047     {
02048       return;
02049     }
02050   }
02051
02052   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02053   hsmartcard->TxXferCount = 0U;
02054   hsmartcard->RxXferCount = 0U;
02055
02056   /* Reset errorCode */
02057   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02058
02059   /* Clear the Error flags in the ICR register */
02060   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
02061
02062   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
02063   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02064   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02065
02066   /* Call user Abort complete callback */
02067   HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
02068 }
02069
02070
02071 /**
02072   * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user
02073   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02074   * @note   When this callback is executed, User Abort complete call back is called only if no
02075   *         Abort still ongoing for Tx DMA Handle.
02076   * @param  hdma DMA handle.
02077   * @retval None
02078   */
02079 static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02080 {
02081   SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
02082
02083   hsmartcard->hdmarx->XferAbortCallback = NULL;
02084
02085   /* Check if an Abort process is still ongoing */
02086   if(hsmartcard->hdmatx != NULL)
02087   {
02088     if(hsmartcard->hdmatx->XferAbortCallback != NULL)
02089     {
02090       return;
02091     }
02092   }
02093
02094   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02095   hsmartcard->TxXferCount = 0U;
02096   hsmartcard->RxXferCount = 0U;
02097
02098   /* Reset errorCode */
02099   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02100
02101   /* Clear the Error flags in the ICR register */
02102   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
02103
02104   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
02105   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02106   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02107
02108   /* Call user Abort complete callback */
02109   HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
02110 }
02111
02112
02113 /**
02114   * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
02115   *         HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
02116   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
02117   *         and leads to user Tx Abort Complete callback execution).
02118   * @param  hdma DMA handle.
02119   * @retval None
02120   */
02121 static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02122 {
02123   SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
02124
02125   hsmartcard->TxXferCount = 0U;
02126
02127   /* Clear the Error flags in the ICR register */
02128   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
02129
02130   /* Restore hsmartcard->gState to Ready */
02131   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
02132
02133   /* Call user Abort complete callback */
02134   HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
02135 }
02136
02137 /**
02138   * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
02139   *         HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
02140   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
02141   *         and leads to user Rx Abort Complete callback execution).
02142   * @param  hdma DMA handle.
02143   * @retval None
02144   */
02145 static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02146 {
02147   SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )(hdma->Parent);
02148
02149   hsmartcard->RxXferCount = 0U;
02150
02151   /* Clear the Error flags in the ICR register */
02152   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
02153
02154   /* Restore hsmartcard->RxState to Ready */
02155   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02156
02157   /* Call user Abort complete callback */
02158   HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
02159 }
02160
02161 /**
02162   * @brief Send an amount of data in non-blocking mode.
02163   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02164   *                the configuration information for the specified SMARTCARD module.
02165   *         Function called under interruption only, once
02166   *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
02167   * @retval HAL status
02168   */
02169 static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
02170 {
02171   /* Check that a Tx process is ongoing */
02172   if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
02173   {
02174     if(hsmartcard->TxXferCount == 0U)
02175     {
02176       /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
02177       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
02178
02179       /* Enable the SMARTCARD Transmit Complete Interrupt */
02180       __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
02181
02182       return HAL_OK;
02183     }
02184     else
02185     {
02186       hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFFU);
02187       hsmartcard->TxXferCount--;
02188
02189       return HAL_OK;
02190     }
02191   }
02192   else
02193   {
02194     return HAL_BUSY;
02195   }
02196 }
02197
02198 /**
02199   * @brief  Wrap up transmission in non-blocking mode.
02200   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02201   *                    the configuration information for the specified SMARTCARD module.
02202   * @retval HAL status
02203   */
02204 static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
02205 {
02206   /* Disable the SMARTCARD Transmit Complete Interrupt */
02207   __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
02208
02209   /* Check if a receive process is ongoing or not. If not disable ERR IT */
02210   if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
02211   {
02212     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
02213     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02214   }
02215
02216   /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
02217   if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
02218   {
02219     /* Disable the Peripheral first to update modes */
02220     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
02221     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
02222     /* Enable the Peripheral */
02223     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
02224   }
02225
02226   /* Tx process is ended, restore hsmartcard->gState to Ready */
02227   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
02228
02229   HAL_SMARTCARD_TxCpltCallback(hsmartcard);
02230
02231   return HAL_OK;
02232 }
02233
02234 /**
02235   * @brief Receive an amount of data in non-blocking mode.
02236   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02237   *                the configuration information for the specified SMARTCARD module.
02238   *         Function called under interruption only, once
02239   *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
02240   * @retval HAL status
02241   */
02242 static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
02243 {
02244   /* Check that a Rx process is ongoing */
02245   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
02246   {
02247     *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
02248
02249     if(--hsmartcard->RxXferCount == 0U)
02250     {
02251       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE);
02252
02253       /* Check if a transmit process is ongoing or not. If not disable ERR IT */
02254       if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
02255       {
02256         /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
02257         CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02258       }
02259
02260       /* Disable the SMARTCARD Parity Error Interrupt */
02261       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
02262
02263       hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02264
02265       HAL_SMARTCARD_RxCpltCallback(hsmartcard);
02266
02267       return HAL_OK;
02268     }
02269
02270     return HAL_OK;
02271   }
02272   else
02273   {
02274     /* Clear RXNE interrupt flag */
02275     __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
02276
02277     return HAL_BUSY;
02278   }
02279 }
02280
02281 /**
02282   * @}
02283   */
02284
02285 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
02286 /**
02287   * @}
02288   */
02289
02290 /**
02291   * @}
02292   */
02293
02294 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_smartcard.h Source File

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stm32f3xx_hal_smartcard.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_smartcard.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SMARTCARD HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_SMARTCARD_H
00038 #define __STM32F3xx_HAL_SMARTCARD_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup SMARTCARD
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
00057   * @{
00058   */
00059
00060 /**
00061   * @brief SMARTCARD Init Structure definition
00062   */
00063 typedef struct
00064 {
00065   uint32_t BaudRate;                  /*!< Configures the SmartCard communication baud rate.
00066                                            The baud rate register is computed using the following formula:
00067                                               Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */
00068
00069   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00070                                            This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
00071
00072   uint32_t StopBits;                  /*!< Specifies the number of stop bits.
00073                                            This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
00074
00075   uint16_t Parity;                    /*!< Specifies the parity mode.
00076                                            This parameter can be a value of @ref SMARTCARD_Parity
00077                                            @note The parity is enabled by default (PCE is forced to 1U).
00078                                                  Since the WordLength is forced to 8 bits + parity, M is
00079                                                  forced to 1 and the parity bit is the 9th bit. */
00080
00081   uint16_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00082                                            This parameter can be a value of @ref SMARTCARD_Mode */
00083
00084   uint16_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00085                                            This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
00086
00087   uint16_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00088                                            This parameter can be a value of @ref SMARTCARD_Clock_Phase */
00089
00090   uint16_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00091                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00092                                            This parameter can be a value of @ref SMARTCARD_Last_Bit */
00093
00094   uint16_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
00095                                            Selecting the single sample method increases the receiver tolerance to clock
00096                                            deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
00097
00098   uint8_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler. */
00099
00100   uint8_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time applied after stop bits. */
00101
00102   uint16_t NACKEnable;                /*!< Specifies whether the SmartCard NACK transmission is enabled
00103                                            in case of parity error.
00104                                            This parameter can be a value of @ref SMARTCARD_NACK_Enable */
00105
00106   uint32_t TimeOutEnable;             /*!< Specifies whether the receiver timeout is enabled.
00107                                             This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
00108
00109   uint32_t TimeOutValue;              /*!< Specifies the receiver time out value in number of baud blocks:
00110                                            it is used to implement the Character Wait Time (CWT) and
00111                                            Block Wait Time (BWT). It is coded over 24 bits. */
00112
00113   uint8_t BlockLength;                /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
00114                                            This parameter can be any value from 0x0 to 0xFFU */
00115
00116   uint8_t AutoRetryCount;             /*!< Specifies the SmartCard auto-retry count (number of retries in
00117                                             receive and transmit mode). When set to 0U, retransmission is
00118                                             disabled. Otherwise, its maximum value is 7 (before signalling
00119                                             an error) */
00120
00121 }SMARTCARD_InitTypeDef;
00122
00123 /**
00124   * @brief  SMARTCARD advanced features initalization structure definition
00125   */
00126 typedef struct
00127 {
00128   uint32_t AdvFeatureInit;            /*!< Specifies which advanced SMARTCARD features is initialized. Several
00129                                            advanced features may be initialized at the same time. This parameter
00130                                            can be a value of @ref SMARTCARD_Advanced_Features_Initialization_Type */
00131
00132   uint32_t TxPinLevelInvert;          /*!< Specifies whether the TX pin active level is inverted.
00133                                            This parameter can be a value of @ref SMARTCARD_Tx_Inv  */
00134
00135   uint32_t RxPinLevelInvert;          /*!< Specifies whether the RX pin active level is inverted.
00136                                            This parameter can be a value of @ref SMARTCARD_Rx_Inv  */
00137
00138   uint32_t DataInvert;                /*!< Specifies whether data are inverted (positive/direct logic
00139                                            vs negative/inverted logic).
00140                                            This parameter can be a value of @ref SMARTCARD_Data_Inv */
00141
00142   uint32_t Swap;                      /*!< Specifies whether TX and RX pins are swapped.
00143                                            This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
00144
00145   uint32_t OverrunDisable;            /*!< Specifies whether the reception overrun detection is disabled.
00146                                            This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
00147
00148   uint32_t DMADisableonRxError;       /*!< Specifies whether the DMA is disabled in case of reception error.
00149                                            This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
00150
00151   uint32_t MSBFirst;                  /*!< Specifies whether MSB is sent first on UART line.
00152                                            This parameter can be a value of @ref SMARTCARD_MSB_First */
00153 }SMARTCARD_AdvFeatureInitTypeDef;
00154
00155 /**
00156   * @brief HAL SMARTCARD State structures definition
00157   * @note  HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
00158   *        - gState contains SMARTCARD state information related to global Handle management
00159   *          and also information related to Tx operations.
00160   *          gState value coding follow below described bitmap :
00161   *          b7-b6  Error information
00162   *             00 : No Error
00163   *             01 : (Not Used)
00164   *             10 : Timeout
00165   *             11 : Error
00166   *          b5     IP initilisation status
00167   *             0  : Reset (IP not initialized)
00168   *             1  : Init done (IP not initialized. HAL SMARTCARD Init function already called)
00169   *          b4-b3  (not used)
00170   *             xx : Should be set to 00
00171   *          b2     Intrinsic process state
00172   *             0  : Ready
00173   *             1  : Busy (IP busy with some configuration or internal operations)
00174   *          b1     (not used)
00175   *             x  : Should be set to 0
00176   *          b0     Tx state
00177   *             0  : Ready (no Tx operation ongoing)
00178   *             1  : Busy (Tx operation ongoing)
00179   *        - RxState contains information related to Rx operations.
00180   *          RxState value coding follow below described bitmap :
00181   *          b7-b6  (not used)
00182   *             xx : Should be set to 00
00183   *          b5     IP initilisation status
00184   *             0  : Reset (IP not initialized)
00185   *             1  : Init done (IP not initialized)
00186   *          b4-b2  (not used)
00187   *            xxx : Should be set to 000
00188   *          b1     Rx state
00189   *             0  : Ready (no Rx operation ongoing)
00190   *             1  : Busy (Rx operation ongoing)
00191   *          b0     (not used)
00192   *             x  : Should be set to 0.
00193   */
00194 typedef enum
00195 {
00196   HAL_SMARTCARD_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
00197                                                         Value is allowed for gState and RxState */
00198   HAL_SMARTCARD_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
00199                                                         Value is allowed for gState and RxState */
00200   HAL_SMARTCARD_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing
00201                                                         Value is allowed for gState only */
00202   HAL_SMARTCARD_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
00203                                                         Value is allowed for gState only */
00204   HAL_SMARTCARD_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
00205                                                         Value is allowed for RxState only */
00206   HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
00207                                                         Not to be used for neither gState nor RxState.
00208                                                         Value is result of combination (Or) between gState and RxState values */
00209   HAL_SMARTCARD_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
00210                                                         Value is allowed for gState only */
00211   HAL_SMARTCARD_STATE_ERROR             = 0xE0U    /*!< Error
00212                                                         Value is allowed for gState only */
00213 }HAL_SMARTCARD_StateTypeDef;
00214
00215 /**
00216   * @brief  SMARTCARD handle Structure definition
00217   */
00218 typedef struct
00219 {
00220   USART_TypeDef                   *Instance;        /*!< USART registers base address                          */
00221
00222   SMARTCARD_InitTypeDef           Init;             /*!< SmartCard communication parameters                    */
00223
00224   SMARTCARD_AdvFeatureInitTypeDef AdvancedInit;     /*!< SmartCard advanced features initialization parameters */
00225
00226   uint8_t                         *pTxBuffPtr;      /*!< Pointer to SmartCard Tx transfer Buffer               */
00227
00228   uint16_t                        TxXferSize;       /*!< SmartCard Tx Transfer size                            */
00229
00230   __IO uint16_t                   TxXferCount;      /*!< SmartCard Tx Transfer Counter                         */
00231
00232   uint8_t                         *pRxBuffPtr;      /*!< Pointer to SmartCard Rx transfer Buffer               */
00233
00234   uint16_t                        RxXferSize;       /*!< SmartCard Rx Transfer size                            */
00235
00236   __IO uint16_t                   RxXferCount;      /*!< SmartCard Rx Transfer Counter                         */
00237
00238   DMA_HandleTypeDef               *hdmatx;          /*!< SmartCard Tx DMA Handle parameters                    */
00239
00240   DMA_HandleTypeDef               *hdmarx;          /*!< SmartCard Rx DMA Handle parameters                    */
00241
00242   HAL_LockTypeDef                 Lock;             /*!< Locking object                                        */
00243
00244   __IO HAL_SMARTCARD_StateTypeDef    gState;        /*!< SmartCard state information related to global Handle management
00245                                                          and also related to Tx operations.
00246                                                          This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
00247
00248   __IO HAL_SMARTCARD_StateTypeDef    RxState;       /*!< SmartCard state information related to Rx operations.
00249                                                          This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
00250
00251   __IO uint32_t                   ErrorCode;        /*!< SmartCard Error code
00252                                                          This parameter can be a value of @ref SMARTCARD_Error */
00253
00254 }SMARTCARD_HandleTypeDef;
00255
00256 /**
00257   * @brief  SMARTCARD clock sources
00258   */
00259 typedef enum
00260 {
00261   SMARTCARD_CLOCKSOURCE_PCLK1     = 0x00U, /*!< PCLK1 clock source     */
00262   SMARTCARD_CLOCKSOURCE_PCLK2     = 0x01U, /*!< PCLK2 clock source     */
00263   SMARTCARD_CLOCKSOURCE_HSI       = 0x02U, /*!< HSI clock source       */
00264   SMARTCARD_CLOCKSOURCE_SYSCLK    = 0x04U, /*!< SYSCLK clock source    */
00265   SMARTCARD_CLOCKSOURCE_LSE       = 0x08U, /*!< LSE clock source       */
00266   SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U  /*!< undefined clock source */
00267 }SMARTCARD_ClockSourceTypeDef;
00268
00269 /**
00270   * @}
00271   */
00272
00273 /* Exported constants --------------------------------------------------------*/
00274 /** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported Constants
00275   * @{
00276   */
00277
00278 /** @defgroup SMARTCARD_Error SMARTCARD Error
00279   * @{
00280   */
00281 #define HAL_SMARTCARD_ERROR_NONE      (0x00000000U)    /*!< No error                */
00282 #define HAL_SMARTCARD_ERROR_PE        (0x00000001U)    /*!< Parity error            */
00283 #define HAL_SMARTCARD_ERROR_NE        (0x00000002U)    /*!< Noise error             */
00284 #define HAL_SMARTCARD_ERROR_FE        (0x00000004U)    /*!< frame error             */
00285 #define HAL_SMARTCARD_ERROR_ORE       (0x00000008U)    /*!< Overrun error           */
00286 #define HAL_SMARTCARD_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error      */
00287 #define HAL_SMARTCARD_ERROR_RTO       (0x00000020U)    /*!< Receiver TimeOut error  */
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
00293   * @{
00294   */
00295 #define SMARTCARD_WORDLENGTH_9B             ((uint32_t)USART_CR1_M0)              /*!< SMARTCARD frame length */
00296 /**
00297   * @}
00298   */
00299
00300 /** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
00301   * @{
00302   */
00303 #define SMARTCARD_STOPBITS_0_5              ((uint32_t)USART_CR2_STOP_0)                      /*!< SMARTCARD frame with 0.5 stop bit  */
00304 #define SMARTCARD_STOPBITS_1_5              ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< SMARTCARD frame with 1.5 stop bits */
00305 /**
00306   * @}
00307   */
00308
00309 /** @defgroup SMARTCARD_Parity SMARTCARD Parity
00310   * @{
00311   */
00312 #define SMARTCARD_PARITY_EVEN               ((uint32_t)USART_CR1_PCE)                  /*!< SMARTCARD frame even parity */
00313 #define SMARTCARD_PARITY_ODD                ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< SMARTCARD frame odd parity  */
00314 /**
00315   * @}
00316   */
00317
00318 /** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
00319   * @{
00320   */
00321 #define SMARTCARD_MODE_RX                   ((uint32_t)USART_CR1_RE)                  /*!< SMARTCARD RX mode        */
00322 #define SMARTCARD_MODE_TX                   ((uint32_t)USART_CR1_TE)                  /*!< SMARTCARD TX mode        */
00323 #define SMARTCARD_MODE_TX_RX                ((uint32_t)(USART_CR1_TE |USART_CR1_RE))  /*!< SMARTCARD RX and TX mode */
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
00329   * @{
00330   */
00331 #define SMARTCARD_POLARITY_LOW              (0x00000000U)                            /*!< SMARTCARD frame low polarity  */
00332 #define SMARTCARD_POLARITY_HIGH             ((uint32_t)USART_CR2_CPOL)               /*!< SMARTCARD frame high polarity */
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
00338   * @{
00339   */
00340 #define SMARTCARD_PHASE_1EDGE               (0x00000000U)                           /*!< SMARTCARD frame phase on first clock transition  */
00341 #define SMARTCARD_PHASE_2EDGE               ((uint32_t)USART_CR2_CPHA)              /*!< SMARTCARD frame phase on second clock transition */
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
00347   * @{
00348   */
00349 #define SMARTCARD_LASTBIT_DISABLE           (0x00000000U)                          /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
00350 #define SMARTCARD_LASTBIT_ENABLE            ((uint32_t)USART_CR2_LBCL)             /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin     */
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
00356   * @{
00357   */
00358 #define SMARTCARD_ONE_BIT_SAMPLE_DISABLE    (0x00000000U)                          /*!< SMARTCARD frame one-bit sample disabled */
00359 #define SMARTCARD_ONE_BIT_SAMPLE_ENABLE     ((uint32_t)USART_CR3_ONEBIT)           /*!< SMARTCARD frame one-bit sample enabled  */
00360 /**
00361   * @}
00362   */
00363
00364
00365 /** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
00366   * @{
00367   */
00368 #define SMARTCARD_NACK_ENABLE               ((uint32_t)USART_CR3_NACK)            /*!< SMARTCARD NACK transmission disabled */
00369 #define SMARTCARD_NACK_DISABLE              (0x00000000U)                         /*!< SMARTCARD NACK transmission enabled  */
00370 /**
00371   * @}
00372   */
00373
00374 /** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
00375   * @{
00376   */
00377 #define SMARTCARD_TIMEOUT_DISABLE           (0x00000000U)                         /*!< SMARTCARD receiver timeout disabled */
00378 #define SMARTCARD_TIMEOUT_ENABLE            ((uint32_t)USART_CR2_RTOEN)           /*!< SMARTCARD receiver timeout enabled  */
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
00384   * @{
00385   */
00386 #define SMARTCARD_ADVFEATURE_NO_INIT                 (0x00000000U)    /*!< No advanced feature initialization                  */
00387 #define SMARTCARD_ADVFEATURE_TXINVERT_INIT           (0x00000001U)    /*!< TX pin active level inversion                       */
00388 #define SMARTCARD_ADVFEATURE_RXINVERT_INIT           (0x00000002U)    /*!< RX pin active level inversion                       */
00389 #define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         (0x00000004U)    /*!< Binary data inversion                               */
00390 #define SMARTCARD_ADVFEATURE_SWAP_INIT               (0x00000008U)    /*!< TX/RX pins swap                                     */
00391 #define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   (0x00000010U)    /*!< RX overrun disable                                  */
00392 #define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  (0x00000020U)    /*!< DMA disable on Reception Error                      */
00393 #define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           (0x00000080U)    /*!< Most significant bit sent/received first            */
00394 /**
00395   * @}
00396   */
00397
00398 /** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
00399   * @{
00400   */
00401 #define SMARTCARD_ADVFEATURE_TXINV_DISABLE  (0x00000000U)                         /*!< TX pin active level inversion disable */
00402 #define SMARTCARD_ADVFEATURE_TXINV_ENABLE   ((uint32_t)USART_CR2_TXINV)           /*!< TX pin active level inversion enable  */
00403 /**
00404   * @}
00405   */
00406
00407 /** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
00408   * @{
00409   */
00410 #define SMARTCARD_ADVFEATURE_RXINV_DISABLE  (0x00000000U)                         /*!< RX pin active level inversion disable */
00411 #define SMARTCARD_ADVFEATURE_RXINV_ENABLE   ((uint32_t)USART_CR2_RXINV)           /*!< RX pin active level inversion enable  */
00412 /**
00413   * @}
00414   */
00415
00416 /** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
00417   * @{
00418   */
00419 #define SMARTCARD_ADVFEATURE_DATAINV_DISABLE  (0x00000000U)                       /*!< Binary data inversion disable */
00420 #define SMARTCARD_ADVFEATURE_DATAINV_ENABLE   ((uint32_t)USART_CR2_DATAINV)       /*!< Binary data inversion enable  */
00421 /**
00422   * @}
00423   */
00424
00425 /** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
00426   * @{
00427   */
00428 #define SMARTCARD_ADVFEATURE_SWAP_DISABLE   (0x00000000U)                         /*!< TX/RX pins swap disable */
00429 #define SMARTCARD_ADVFEATURE_SWAP_ENABLE    ((uint32_t)USART_CR2_SWAP)            /*!< TX/RX pins swap enable  */
00430 /**
00431   * @}
00432   */
00433
00434 /** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
00435   * @{
00436   */
00437 #define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE   (0x00000000U)                       /*!< RX overrun enable  */
00438 #define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE  ((uint32_t)USART_CR3_OVRDIS)        /*!< RX overrun disable */
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
00444   * @{
00445   */
00446 #define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR   (0x00000000U)                  /*!< DMA enable on Reception Error  */
00447 #define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR  ((uint32_t)USART_CR3_DDRE)     /*!< DMA disable on Reception Error */
00448 /**
00449   * @}
00450   */
00451
00452 /** @defgroup SMARTCARD_MSB_First   SMARTCARD advanced feature MSB first
00453   * @{
00454   */
00455 #define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE      (0x00000000U)                    /*!< Most significant bit sent/received first disable */
00456 #define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE       ((uint32_t)USART_CR2_MSBFIRST)   /*!< Most significant bit sent/received first enable  */
00457 /**
00458   * @}
00459   */
00460
00461 /** @defgroup SMARTCARD_Flags SMARTCARD Flags
00462   *        Elements values convention: 0xXXXX
00463   *           - 0xXXXX  : Flag mask in the ISR register
00464   * @{
00465   */
00466 #define SMARTCARD_FLAG_REACK          USART_ISR_REACK      /*!< SMARTCARD receive enable acknowledge flag  */
00467 #define SMARTCARD_FLAG_TEACK          USART_ISR_TEACK      /*!< SMARTCARD transmit enable acknowledge flag */
00468 #define SMARTCARD_FLAG_BUSY           USART_ISR_BUSY       /*!< SMARTCARD busy flag                        */
00469 #define SMARTCARD_FLAG_EOBF           USART_ISR_EOBF       /*!< SMARTCARD end of block flag                */
00470 #define SMARTCARD_FLAG_RTOF           USART_ISR_RTOF       /*!< SMARTCARD receiver timeout flag            */
00471 #define SMARTCARD_FLAG_TXE            USART_ISR_TXE        /*!< SMARTCARD transmit data register empty     */
00472 #define SMARTCARD_FLAG_TC             USART_ISR_TC         /*!< SMARTCARD transmission complete            */
00473 #define SMARTCARD_FLAG_RXNE           USART_ISR_RXNE       /*!< SMARTCARD read data register not empty     */
00474 #define SMARTCARD_FLAG_IDLE           USART_ISR_IDLE       /*!< SMARTCARD idle line detection              */
00475 #define SMARTCARD_FLAG_ORE            USART_ISR_ORE        /*!< SMARTCARD overrun error                    */
00476 #define SMARTCARD_FLAG_NE             USART_ISR_NE         /*!< SMARTCARD noise error                      */
00477 #define SMARTCARD_FLAG_FE             USART_ISR_FE         /*!< SMARTCARD frame error                      */
00478 #define SMARTCARD_FLAG_PE             USART_ISR_PE         /*!< SMARTCARD parity error                     */
00479 /**
00480   * @}
00481   */
00482
00483 /** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition
00484   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00485   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00486   *           - XX  : Interrupt source register (2bits)
00487   *                 - 01: CR1 register
00488   *                 - 10: CR2 register
00489   *                 - 11: CR3 register
00490   *           - ZZZZ  : Flag position in the ISR register(4bits)
00491   * @{
00492   */
00493
00494 #define SMARTCARD_IT_PE                     ((uint16_t)0x0028U)        /*!< SMARTCARD parity error interruption                 */
00495 #define SMARTCARD_IT_TXE                    ((uint16_t)0x0727U)        /*!< SMARTCARD transmit data register empty interruption */
00496 #define SMARTCARD_IT_TC                     ((uint16_t)0x0626U)        /*!< SMARTCARD transmission complete interruption        */
00497 #define SMARTCARD_IT_RXNE                   ((uint16_t)0x0525U)        /*!< SMARTCARD read data register not empty interruption */
00498 #define SMARTCARD_IT_IDLE                   ((uint16_t)0x0424U)        /*!< SMARTCARD idle line detection interruption          */
00499
00500 #define SMARTCARD_IT_ERR                    ((uint16_t)0x0060U)        /*!< SMARTCARD error interruption                        */
00501 #define SMARTCARD_IT_ORE                    ((uint16_t)0x0300U)        /*!< SMARTCARD overrun error interruption                */
00502 #define SMARTCARD_IT_NE                     ((uint16_t)0x0200U)        /*!< SMARTCARD noise error interruption                  */
00503 #define SMARTCARD_IT_FE                     ((uint16_t)0x0100U)        /*!< SMARTCARD frame error interruption                  */
00504
00505 #define SMARTCARD_IT_EOB                    ((uint16_t)0x0C3BU)        /*!< SMARTCARD end of block interruption                 */
00506 #define SMARTCARD_IT_RTO                    ((uint16_t)0x0B3AU)        /*!< SMARTCARD receiver timeout interruption             */
00507 /**
00508   * @}
00509   */
00510
00511 /** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
00512   * @{
00513   */
00514 #define SMARTCARD_CLEAR_PEF                 USART_ICR_PECF    /*!< SMARTCARD parity error clear flag          */
00515 #define SMARTCARD_CLEAR_FEF                 USART_ICR_FECF    /*!< SMARTCARD framing error clear flag         */
00516 #define SMARTCARD_CLEAR_NEF                 USART_ICR_NCF     /*!< SMARTCARD noise detected clear flag        */
00517 #define SMARTCARD_CLEAR_OREF                USART_ICR_ORECF   /*!< SMARTCARD overrun error clear flag         */
00518 #define SMARTCARD_CLEAR_IDLEF               USART_ICR_IDLECF  /*!< SMARTCARD idle line detected clear flag    */
00519 #define SMARTCARD_CLEAR_TCF                 USART_ICR_TCCF    /*!< SMARTCARD transmission complete clear flag */
00520 #define SMARTCARD_CLEAR_RTOF                USART_ICR_RTOCF   /*!< SMARTCARD receiver time out clear flag     */
00521 #define SMARTCARD_CLEAR_EOBF                USART_ICR_EOBCF   /*!< SMARTCARD end of block clear flag          */
00522 /**
00523   * @}
00524   */
00525
00526 /** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register
00527   * @{
00528   */
00529 #define SMARTCARD_CR3_SCARCNT_LSB_POS       ( 17U)                /*!< SMARTCARD auto retry counter LSB position in CR3 register */
00530 /**
00531   * @}
00532   */
00533
00534 /** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register
00535   * @{
00536   */
00537 #define SMARTCARD_GTPR_GT_LSB_POS           ( 8U)                 /*!<  SMARTCARD guard time value LSB position in GTPR register */
00538 /**
00539   * @}
00540   */
00541
00542 /** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register
00543   * @{
00544   */
00545 #define SMARTCARD_RTOR_BLEN_LSB_POS         ( 24U)                /*!< SMARTCARD block length LSB position in RTOR register */
00546 /**
00547   * @}
00548   */
00549
00550 /** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
00551   * @{
00552   */
00553 #define SMARTCARD_IT_MASK                   ((uint16_t)0x001FU)   /*!< SMARTCARD interruptions flags mask */
00554 /**
00555   * @}
00556   */
00557
00558 /** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
00559   * @{
00560   */
00561 #define SMARTCARD_RXDATA_FLUSH_REQUEST      ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive data flush request */
00562 #define SMARTCARD_TXDATA_FLUSH_REQUEST      ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush request */
00563 /**
00564   * @}
00565   */
00566
00567 /**
00568   * @}
00569   */
00570
00571 /* Exported macros -----------------------------------------------------------*/
00572 /** @defgroup SMARTCARD_Exported_Macros  SMARTCARD Exported Macros
00573   * @{
00574   */
00575
00576 /** @brief  Reset SMARTCARD handle states.
00577   * @param  __HANDLE__ SMARTCARD handle.
00578   * @retval None
00579   */
00580 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
00581                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
00582                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
00583                                                           } while(0U)
00584
00585 /** @brief  Flush the Smartcard Data registers.
00586   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00587   * @retval None
00588   */
00589 #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)                        \
00590     do{                                                                     \
00591       SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
00592       SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
00593       } while(0U)
00594
00595 /** @brief  Clear the specified SMARTCARD pending flag.
00596   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00597   * @param  __FLAG__ specifies the flag to check.
00598   *          This parameter can be any combination of the following values:
00599   *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
00600   *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
00601   *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
00602   *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
00603   *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detected clear flag
00604   *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
00605   *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
00606   *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
00607   * @retval None
00608   */
00609 #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00610
00611 /** @brief  Clear the SMARTCARD PE pending flag.
00612   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00613   * @retval None
00614   */
00615 #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
00616
00617
00618 /** @brief  Clear the SMARTCARD FE pending flag.
00619   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00620   * @retval None
00621   */
00622 #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
00623
00624 /** @brief  Clear the SMARTCARD NE pending flag.
00625   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00626   * @retval None
00627   */
00628 #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
00629
00630 /** @brief  Clear the SMARTCARD ORE pending flag.
00631   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00632   * @retval None
00633   */
00634 #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
00635
00636 /** @brief  Clear the SMARTCARD IDLE pending flag.
00637   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00638   * @retval None
00639   */
00640 #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
00641
00642 /** @brief  Check whether the specified Smartcard flag is set or not.
00643   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00644   * @param  __FLAG__ specifies the flag to check.
00645   *        This parameter can be one of the following values:
00646   *            @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
00647   *            @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
00648   *            @arg @ref SMARTCARD_FLAG_BUSY  Busy flag
00649   *            @arg @ref SMARTCARD_FLAG_EOBF  End of block flag
00650   *            @arg @ref SMARTCARD_FLAG_RTOF  Receiver timeout flag
00651   *            @arg @ref SMARTCARD_FLAG_TXE   Transmit data register empty flag
00652   *            @arg @ref SMARTCARD_FLAG_TC    Transmission complete flag
00653   *            @arg @ref SMARTCARD_FLAG_RXNE  Receive data register not empty flag
00654   *            @arg @ref SMARTCARD_FLAG_IDLE  Idle line detection flag
00655   *            @arg @ref SMARTCARD_FLAG_ORE   Overrun error flag
00656   *            @arg @ref SMARTCARD_FLAG_NE    Noise error flag
00657   *            @arg @ref SMARTCARD_FLAG_FE    Framing error flag
00658   *            @arg @ref SMARTCARD_FLAG_PE    Parity error flag
00659   * @retval The new state of __FLAG__ (TRUE or FALSE).
00660   */
00661 #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00662
00663
00664 /** @brief  Enable the specified SmartCard interrupt.
00665   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00666   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
00667   *          This parameter can be one of the following values:
00668   *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
00669   *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
00670   *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
00671   *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
00672   *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
00673   *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt
00674   *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
00675   *            @arg @ref SMARTCARD_IT_ERR   Error interrupt(frame error, noise error, overrun error)
00676   * @retval None
00677   */
00678 #define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00679                                                                 ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00680                                                                 ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
00681
00682 /** @brief  Disable the specified SmartCard interrupt.
00683   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00684   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
00685   *          This parameter can be one of the following values:
00686   *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
00687   *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
00688   *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
00689   *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
00690   *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
00691   *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt
00692   *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
00693   *            @arg @ref SMARTCARD_IT_ERR   Error interrupt(frame error, noise error, overrun error)
00694   * @retval None
00695   */
00696 #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00697                                                                 ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00698                                                                 ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
00699
00700
00701 /** @brief  Check whether the specified SmartCard interrupt has occurred or not.
00702   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00703   * @param  __IT__ specifies the SMARTCARD interrupt to check.
00704   *          This parameter can be one of the following values:
00705   *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
00706   *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
00707   *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
00708   *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
00709   *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
00710   *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt
00711   *            @arg @ref SMARTCARD_IT_ORE   Overrun error interrupt
00712   *            @arg @ref SMARTCARD_IT_NE    Noise error interrupt
00713   *            @arg @ref SMARTCARD_IT_FE    Framing error interrupt
00714   *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
00715   * @retval The new state of __IT__ (TRUE or FALSE).
00716   */
00717 #define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
00718
00719 /** @brief  Check whether the specified SmartCard interrupt source is enabled or not.
00720   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00721   * @param  __IT__ specifies the SMARTCARD interrupt source to check.
00722   *          This parameter can be one of the following values:
00723   *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
00724   *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
00725   *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
00726   *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
00727   *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
00728   *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt
00729   *            @arg @ref SMARTCARD_IT_ERR   Framing, overrun or noise error interrupt
00730   *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
00731   * @retval The new state of __IT__ (TRUE or FALSE).
00732   */
00733 #define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((__IT__) & 0xFFU) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1 : \
00734                                                            (((((__IT__) & 0xFFU) >> 5U) == 2U)? (__HANDLE__)->Instance->CR2 : \
00735                                                            (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
00736
00737
00738 /** @brief  Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
00739   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00740   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
00741   *                       to clear the corresponding interrupt.
00742   *          This parameter can be one of the following values:
00743   *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
00744   *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
00745   *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
00746   *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
00747   *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detection clear flag
00748   *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
00749   *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
00750   *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
00751   * @retval None
00752   */
00753 #define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00754
00755 /** @brief  Set a specific SMARTCARD request flag.
00756   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00757   * @param  __REQ__ specifies the request flag to set
00758   *          This parameter can be one of the following values:
00759   *            @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
00760   *            @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
00761   *
00762   * @retval None
00763   */
00764 #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00765
00766 /** @brief  Enable the SMARTCARD one bit sample method.
00767   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00768   * @retval None
00769   */
00770 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00771
00772 /** @brief  Disable the SMARTCARD one bit sample method.
00773   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00774   * @retval None
00775   */
00776 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00777
00778 /** @brief  Enable the USART associated to the SMARTCARD Handle.
00779   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00780   * @retval None
00781   */
00782 #define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00783
00784 /** @brief  Disable the USART associated to the SMARTCARD Handle
00785   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00786   * @retval None
00787   */
00788 #define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00789
00790 /**
00791   * @}
00792   */
00793
00794 /* Private macros -------------------------------------------------------------*/
00795 /** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
00796   * @{
00797   */
00798
00799 /** @brief  Check the Baud rate range.
00800   * @note   The maximum Baud Rate is derived from the maximum clock on F3 (72 MHz)
00801   *         divided by the oversampling used on the SMARTCARD (i.e. 16).
00802   * @param  __BAUDRATE__ Baud rate set by the configuration function.
00803   * @retval Test result (TRUE or FALSE)
00804   */
00805 #define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001U)
00806
00807 /** @brief  Check the block length range.
00808   * @note   The maximum SMARTCARD block length is 0xFF.
00809   * @param  __LENGTH__ block length.
00810   * @retval Test result (TRUE or FALSE)
00811   */
00812 #define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
00813
00814 /** @brief  Check the receiver timeout value.
00815   * @note   The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
00816   * @param  __TIMEOUTVALUE__ receiver timeout value.
00817   * @retval Test result (TRUE or FALSE)
00818   */
00819 #define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
00820
00821 /** @brief  Check the SMARTCARD autoretry counter value.
00822   * @note   The maximum number of retransmissions is 0x7.
00823   * @param  __COUNT__ number of retransmissions.
00824   * @retval Test result (TRUE or FALSE)
00825   */
00826 #define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7U)
00827
00828 /**
00829   * @brief Ensure that SMARTCARD frame length is valid.
00830   * @param __LENGTH__ SMARTCARD frame length.
00831   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00832   */
00833 #define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
00834
00835 /**
00836   * @brief Ensure that SMARTCARD frame number of stop bits is valid.
00837   * @param __STOPBITS__ SMARTCARD frame number of stop bits.
00838   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
00839   */
00840 #define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
00841                                              ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
00842
00843 /**
00844   * @brief Ensure that SMARTCARD frame parity is valid.
00845   * @param __PARITY__ SMARTCARD frame parity.
00846   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00847   */
00848 #define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
00849                                          ((__PARITY__) == SMARTCARD_PARITY_ODD))
00850
00851 /**
00852   * @brief Ensure that SMARTCARD communication mode is valid.
00853   * @param __MODE__ SMARTCARD communication mode.
00854   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00855   */
00856 #define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3U) == 0x00U) && ((__MODE__) != (uint16_t)0x00U))
00857
00858 /**
00859   * @brief Ensure that SMARTCARD frame polarity is valid.
00860   * @param __CPOL__ SMARTCARD frame polarity.
00861   * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
00862   */
00863 #define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
00864
00865 /**
00866   * @brief Ensure that SMARTCARD frame phase is valid.
00867   * @param __CPHA__ SMARTCARD frame phase.
00868   * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
00869   */
00870 #define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
00871
00872 /**
00873   * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
00874   * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting.
00875   * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
00876   */
00877 #define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
00878                                            ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
00879
00880 /**
00881   * @brief Ensure that SMARTCARD frame sampling is valid.
00882   * @param __ONEBIT__ SMARTCARD frame sampling.
00883   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
00884   */
00885 #define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
00886                                                  ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
00887
00888 /**
00889   * @brief Ensure that SMARTCARD NACK transmission setting is valid.
00890   * @param __NACK__ SMARTCARD NACK transmission setting.
00891   * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
00892   */
00893 #define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
00894                                      ((__NACK__) == SMARTCARD_NACK_DISABLE))
00895
00896 /**
00897   * @brief Ensure that SMARTCARD receiver timeout setting is valid.
00898   * @param __TIMEOUT__ SMARTCARD receiver timeout setting.
00899   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
00900   */
00901 #define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
00902                                            ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
00903
00904 /**
00905   * @brief Ensure that SMARTCARD advanced features initialization is valid.
00906   * @param __INIT__ SMARTCARD advanced features initialization.
00907   * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
00908   */
00909 #define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
00910                                                                SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
00911                                                                SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
00912                                                                SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
00913                                                                SMARTCARD_ADVFEATURE_SWAP_INIT              | \
00914                                                                SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
00915                                                                SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
00916                                                                SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
00917
00918 /**
00919   * @brief Ensure that SMARTCARD frame TX inversion setting is valid.
00920   * @param __TXINV__ SMARTCARD frame TX inversion setting.
00921   * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
00922   */
00923 #define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
00924                                                   ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
00925
00926 /**
00927   * @brief Ensure that SMARTCARD frame RX inversion setting is valid.
00928   * @param __RXINV__ SMARTCARD frame RX inversion setting.
00929   * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
00930   */
00931 #define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
00932                                                   ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
00933
00934 /**
00935   * @brief Ensure that SMARTCARD frame data inversion setting is valid.
00936   * @param __DATAINV__ SMARTCARD frame data inversion setting.
00937   * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
00938   */
00939 #define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
00940                                                       ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
00941
00942 /**
00943   * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
00944   * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting.
00945   * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
00946   */
00947 #define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
00948                                                 ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
00949
00950 /**
00951   * @brief Ensure that SMARTCARD frame overrun setting is valid.
00952   * @param __OVERRUN__ SMARTCARD frame overrun setting.
00953   * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
00954   */
00955 #define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
00956                                            ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
00957
00958 /**
00959   * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
00960   * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting.
00961   * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
00962   */
00963 #define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
00964                                                        ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
00965
00966 /**
00967   * @brief Ensure that SMARTCARD frame MSB first setting is valid.
00968   * @param __MSBFIRST__ SMARTCARD frame MSB first setting.
00969   * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
00970   */
00971 #define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
00972                                                         ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
00973
00974 /**
00975   * @brief Ensure that SMARTCARD request parameter is valid.
00976   * @param __PARAM__ SMARTCARD request parameter.
00977   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
00978   */
00979 #define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
00980                                                    ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
00981
00982 /**
00983   * @}
00984   */
00985
00986 /* Include SMARTCARD HAL Extended module */
00987 #include "stm32f3xx_hal_smartcard_ex.h"
00988
00989 /* Exported functions --------------------------------------------------------*/
00990 /** @addtogroup SMARTCARD_Exported_Functions
00991   * @{
00992   */
00993
00994 /* Initialization and de-initialization functions  ****************************/
00995
00996 /** @addtogroup SMARTCARD_Exported_Functions_Group1
00997   * @{
00998   */
00999
01000 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
01001 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
01002 void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
01003 void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
01004
01005 /**
01006   * @}
01007   */
01008
01009 /* IO operation functions *****************************************************/
01010 /** @addtogroup SMARTCARD_Exported_Functions_Group2
01011   * @{
01012   */
01013
01014 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01015 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01016 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01017 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01018 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01019 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01020 /* Transfer Abort functions */
01021 HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
01022 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
01023 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
01024 HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01025 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01026 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01027
01028 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
01029 void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01030 void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01031 void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01032 void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
01033 void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
01034 void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
01035
01036 /**
01037   * @}
01038   */
01039
01040 /* Peripheral State and Error functions ***************************************/
01041 /** @addtogroup SMARTCARD_Exported_Functions_Group3
01042   * @{
01043   */
01044
01045 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
01046 uint32_t                   HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
01047
01048 /**
01049   * @}
01050   */
01051
01052 /**
01053   * @}
01054   */
01055
01056 /**
01057   * @}
01058   */
01059
01060 /**
01061   * @}
01062   */
01063
01064 #ifdef __cplusplus
01065 }
01066 #endif
01067
01068 #endif /* __STM32F3xx_HAL_SMARTCARD_H */
01069
01070 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_smartcard_ex.c Source File

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stm32f3xx_hal_smartcard_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_smartcard_ex.c
00004   * @author  MCD Application Team
00005   * @brief   SMARTCARD HAL module driver.
00006   *          This file provides extended firmware functions to manage the following
00007   *          functionalities of the SmartCard.
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   *
00012   @verbatim
00013   =============================================================================
00014                ##### SMARTCARD peripheral extended features  #####
00015   =============================================================================
00016   [..]
00017   The Extended SMARTCARD HAL driver can be used as follows:
00018
00019     (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
00020         then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
00021         auto-retry counter,...) in the hsmartcard AdvancedInit structure.
00022
00023
00024
00025   @endverbatim
00026   ******************************************************************************
00027   * @attention
00028   *
00029   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00030   *
00031   * Redistribution and use in source and binary forms, with or without modification,
00032   * are permitted provided that the following conditions are met:
00033   *   1. Redistributions of source code must retain the above copyright notice,
00034   *      this list of conditions and the following disclaimer.
00035   *   2. Redistributions in binary form must reproduce the above copyright notice,
00036   *      this list of conditions and the following disclaimer in the documentation
00037   *      and/or other materials provided with the distribution.
00038   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00039   *      may be used to endorse or promote products derived from this software
00040   *      without specific prior written permission.
00041   *
00042   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00043   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00044   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00045   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00046   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00047   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00048   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00049   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00050   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00051   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00052   *
00053   ******************************************************************************
00054   */
00055
00056 /* Includes ------------------------------------------------------------------*/
00057 #include "stm32f3xx_hal.h"
00058
00059 /** @addtogroup STM32F3xx_HAL_Driver
00060   * @{
00061   */
00062
00063 /** @defgroup SMARTCARDEx SMARTCARDEx
00064   * @brief SMARTCARD Extension HAL module driver
00065   * @{
00066   */
00067 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00068
00069 /* Private typedef -----------------------------------------------------------*/
00070 /* Private define ------------------------------------------------------------*/
00071 /* Private macros ------------------------------------------------------------*/
00072 /* Private variables ---------------------------------------------------------*/
00073 /* Private function prototypes -----------------------------------------------*/
00074
00075 /* Exported functions --------------------------------------------------------*/
00076 /** @defgroup SMARTCARDEx_Exported_Functions  SMARTCARD Extended Exported Functions
00077   * @{
00078   */
00079
00080 /** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
00081   * @brief    Extended control functions
00082   *
00083 @verbatim
00084   ===============================================================================
00085                       ##### Peripheral Control functions #####
00086   ===============================================================================
00087   [..]
00088   This subsection provides a set of functions allowing to initialize the SMARTCARD.
00089      (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
00090      (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
00091      (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
00092      (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
00093
00094 @endverbatim
00095   * @{
00096   */
00097
00098 /**
00099   * @brief Update on the fly the SMARTCARD block length in RTOR register.
00100   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00101   *                    the configuration information for the specified SMARTCARD module.
00102   * @param BlockLength SMARTCARD block length (8-bit long at most)
00103   * @retval None
00104   */
00105 void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
00106 {
00107   MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));
00108 }
00109
00110 /**
00111   * @brief Update on the fly the receiver timeout value in RTOR register.
00112   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00113   *                    the configuration information for the specified SMARTCARD module.
00114   * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
00115   *                     value must be less or equal to 0x0FFFFFFFF.
00116   * @retval None
00117   */
00118 void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
00119 {
00120   assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
00121   MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
00122 }
00123
00124 /**
00125   * @brief Enable the SMARTCARD receiver timeout feature.
00126   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00127   *                    the configuration information for the specified SMARTCARD module.
00128   * @retval HAL status
00129   */
00130 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
00131 {
00132
00133   if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00134   {
00135     /* Process Locked */
00136     __HAL_LOCK(hsmartcard);
00137
00138     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00139
00140     /* Set the USART RTOEN bit */
00141     SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
00142
00143     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00144
00145     /* Process Unlocked */
00146     __HAL_UNLOCK(hsmartcard);
00147
00148     return HAL_OK;
00149   }
00150   else
00151   {
00152     return HAL_BUSY;
00153   }
00154 }
00155
00156 /**
00157   * @brief Disable the SMARTCARD receiver timeout feature.
00158   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00159   *                    the configuration information for the specified SMARTCARD module.
00160   * @retval HAL status
00161   */
00162 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
00163 {
00164
00165   if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00166   {
00167     /* Process Locked */
00168     __HAL_LOCK(hsmartcard);
00169
00170     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00171
00172     /* Clear the USART RTOEN bit */
00173     CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
00174
00175     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00176
00177     /* Process Unlocked */
00178     __HAL_UNLOCK(hsmartcard);
00179
00180     return HAL_OK;
00181   }
00182   else
00183   {
00184     return HAL_BUSY;
00185   }
00186 }
00187
00188 /**
00189   * @}
00190   */
00191
00192 /**
00193   * @}
00194   */
00195
00196 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00197
00198 /**
00199   * @}
00200   */
00201
00202 /**
00203   * @}
00204   */
00205
00206 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_smartcard_ex.h Source File

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stm32f3xx_hal_smartcard_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_smartcard_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SMARTCARD HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_SMARTCARD_EX_H
00038 #define __STM32F3xx_HAL_SMARTCARD_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup SMARTCARDEx
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /* Exported constants --------------------------------------------------------*/
00057 /* Exported macros -----------------------------------------------------------*/
00058 /* Private macros ------------------------------------------------------------*/
00059 /** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
00060   * @{
00061   */
00062
00063 /** @brief  Report the SMARTCARD clock source.
00064   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00065   * @param  __CLOCKSOURCE__ output variable.
00066   * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
00067   */
00068 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00069     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00070 #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
00071   do {                                                         \
00072     if((__HANDLE__)->Instance == USART1)                       \
00073     {                                                          \
00074        switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00075        {                                                       \
00076         case RCC_USART1CLKSOURCE_PCLK1:                        \
00077           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
00078           break;                                               \
00079         case RCC_USART1CLKSOURCE_HSI:                          \
00080           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00081           break;                                               \
00082         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00083           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00084           break;                                               \
00085         case RCC_USART1CLKSOURCE_LSE:                          \
00086           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00087           break;                                               \
00088         default:                                               \
00089           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00090           break;                                               \
00091        }                                                       \
00092     }                                                          \
00093     else if((__HANDLE__)->Instance == USART2)                  \
00094     {                                                          \
00095       (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;         \
00096     }                                                          \
00097     else if((__HANDLE__)->Instance == USART3)                  \
00098     {                                                          \
00099       (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;         \
00100     }                                                          \
00101     else                                                       \
00102     {                                                          \
00103       (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;     \
00104     }                                                          \
00105   } while(0U)
00106 #else
00107 #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
00108   do {                                                         \
00109     if((__HANDLE__)->Instance == USART1)                       \
00110     {                                                          \
00111        switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00112        {                                                       \
00113         case RCC_USART1CLKSOURCE_PCLK2:                        \
00114           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;     \
00115           break;                                               \
00116         case RCC_USART1CLKSOURCE_HSI:                          \
00117           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00118           break;                                               \
00119         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00120           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00121           break;                                               \
00122         case RCC_USART1CLKSOURCE_LSE:                          \
00123           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00124           break;                                               \
00125         default:                                               \
00126           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00127           break;                                               \
00128        }                                                       \
00129     }                                                          \
00130     else if((__HANDLE__)->Instance == USART2)                  \
00131     {                                                          \
00132        switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00133        {                                                       \
00134         case RCC_USART2CLKSOURCE_PCLK1:                        \
00135           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
00136           break;                                               \
00137         case RCC_USART2CLKSOURCE_HSI:                          \
00138           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00139           break;                                               \
00140         case RCC_USART2CLKSOURCE_SYSCLK:                       \
00141           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00142           break;                                               \
00143         case RCC_USART2CLKSOURCE_LSE:                          \
00144           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00145           break;                                               \
00146         default:                                               \
00147           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00148           break;                                               \
00149        }                                                       \
00150     }                                                          \
00151     else if((__HANDLE__)->Instance == USART3)                  \
00152     {                                                          \
00153        switch(__HAL_RCC_GET_USART3_SOURCE())                   \
00154        {                                                       \
00155         case RCC_USART3CLKSOURCE_PCLK1:                        \
00156           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
00157           break;                                               \
00158         case RCC_USART3CLKSOURCE_HSI:                          \
00159           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00160           break;                                               \
00161         case RCC_USART3CLKSOURCE_SYSCLK:                       \
00162           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00163           break;                                               \
00164         case RCC_USART3CLKSOURCE_LSE:                          \
00165           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00166           break;                                               \
00167         default:                                               \
00168           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00169           break;                                               \
00170        }                                                       \
00171     }                                                          \
00172     else                                                       \
00173     {                                                          \
00174       (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;     \
00175     }                                                          \
00176   } while(0U)
00177 #endif
00178
00179 /**
00180   * @}
00181   */
00182
00183 /* Exported functions --------------------------------------------------------*/
00184 /** @addtogroup SMARTCARDEx_Exported_Functions
00185   * @{
00186   */
00187
00188 /* Initialization and de-initialization functions  ****************************/
00189 /* IO operation methods *******************************************************/
00190
00191 /** @addtogroup SMARTCARDEx_Exported_Functions_Group1
00192   * @{
00193   */
00194
00195 /* Peripheral Control functions ***********************************************/
00196 void              HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
00197 void              HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
00198 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
00199 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
00200
00201 /**
00202   * @}
00203   */
00204
00205 /**
00206   * @}
00207   */
00208
00209 /**
00210   * @}
00211   */
00212
00213 /**
00214   * @}
00215   */
00216
00217 #ifdef __cplusplus
00218 }
00219 #endif
00220
00221 #endif /* __STM32F3xx_HAL_SMARTCARD_EX_H */
00222
00223 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_smbus.c Source File

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stm32f3xx_hal_smbus.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_smbus.c
00004   * @author  MCD Application Team
00005   * @brief   SMBUS HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the System Management Bus (SMBus) peripheral,
00008   *          based on I2C principles of operation :
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral State and Errors functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018     The SMBUS HAL driver can be used as follows:
00019
00020     (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
00021         SMBUS_HandleTypeDef  hsmbus;
00022
00023     (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
00024         (##) Enable the SMBUSx interface clock
00025         (##) SMBUS pins configuration
00026             (+++) Enable the clock for the SMBUS GPIOs
00027             (+++) Configure SMBUS pins as alternate function open-drain
00028         (##) NVIC configuration if you need to use interrupt process
00029             (+++) Configure the SMBUSx interrupt priority
00030             (+++) Enable the NVIC SMBUS IRQ Channel
00031
00032     (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
00033         Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
00034         Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
00035
00036     (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
00037         (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00038              by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
00039
00040     (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
00041
00042     (#) For SMBUS IO operations, only one mode of operations is available within this driver
00043
00044     *** Interrupt mode IO operation ***
00045     ===================================
00046     [..]
00047       (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
00048       (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
00049            add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
00050       (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
00051       (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
00052            add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
00053       (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
00054       (++) The associated previous transfer callback is called at the end of abort process
00055       (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
00056       (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
00057       (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
00058            using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
00059       (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
00060            add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
00061       (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
00062            add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
00063       (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
00064       (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
00065            add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
00066       (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
00067       (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
00068            add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
00069       (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
00070       (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
00071            add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
00072            to check the Alert Error Code using function HAL_SMBUS_GetError()
00073       (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
00074       (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
00075            add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
00076            to check the Error Code using function HAL_SMBUS_GetError()
00077
00078      *** SMBUS HAL driver macros list ***
00079      ==================================
00080      [..]
00081        Below the list of most used macros in SMBUS HAL driver.
00082
00083       (+) __HAL_SMBUS_ENABLE:      Enable the SMBUS peripheral
00084       (+) __HAL_SMBUS_DISABLE:     Disable the SMBUS peripheral
00085       (+) __HAL_SMBUS_GET_FLAG:    Check whether the specified SMBUS flag is set or not
00086       (+) __HAL_SMBUS_CLEAR_FLAG:  Clear the specified SMBUS pending flag
00087       (+) __HAL_SMBUS_ENABLE_IT:   Enable the specified SMBUS interrupt
00088       (+) __HAL_SMBUS_DISABLE_IT:  Disable the specified SMBUS interrupt
00089
00090      [..]
00091        (@) You can refer to the SMBUS HAL driver header file for more useful macros
00092
00093
00094   @endverbatim
00095   ******************************************************************************
00096   * @attention
00097   *
00098   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00099   *
00100   * Redistribution and use in source and binary forms, with or without modification,
00101   * are permitted provided that the following conditions are met:
00102   *   1. Redistributions of source code must retain the above copyright notice,
00103   *      this list of conditions and the following disclaimer.
00104   *   2. Redistributions in binary form must reproduce the above copyright notice,
00105   *      this list of conditions and the following disclaimer in the documentation
00106   *      and/or other materials provided with the distribution.
00107   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00108   *      may be used to endorse or promote products derived from this software
00109   *      without specific prior written permission.
00110   *
00111   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00112   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00113   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00114   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00115   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00116   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00117   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00118   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00119   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00120   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00121   *
00122   ******************************************************************************
00123   */
00124
00125 /* Includes ------------------------------------------------------------------*/
00126 #include "stm32f3xx_hal.h"
00127
00128 /** @addtogroup STM32F3xx_HAL_Driver
00129   * @{
00130   */
00131
00132 /** @defgroup SMBUS SMBUS
00133   * @brief SMBUS HAL module driver
00134   * @{
00135   */
00136
00137 #ifdef HAL_SMBUS_MODULE_ENABLED
00138
00139 /* Private typedef -----------------------------------------------------------*/
00140 /* Private constants ---------------------------------------------------------*/
00141 /** @defgroup SMBUS_Private_Define SMBUS Private Constants
00142   * @{
00143   */
00144 #define TIMING_CLEAR_MASK   (0xF0FFFFFFU)      /*!< SMBUS TIMING clear register Mask */
00145 #define HAL_TIMEOUT_ADDR    (10000U)           /*!< 10 s  */
00146 #define HAL_TIMEOUT_BUSY    (25U)              /*!< 25 ms */
00147 #define HAL_TIMEOUT_DIR     (25U)              /*!< 25 ms */
00148 #define HAL_TIMEOUT_RXNE    (25U)              /*!< 25 ms */
00149 #define HAL_TIMEOUT_STOPF   (25U)              /*!< 25 ms */
00150 #define HAL_TIMEOUT_TC      (25U)              /*!< 25 ms */
00151 #define HAL_TIMEOUT_TCR     (25U)              /*!< 25 ms */
00152 #define HAL_TIMEOUT_TXIS    (25U)              /*!< 25 ms */
00153 #define MAX_NBYTE_SIZE      255U
00154 /**
00155   * @}
00156   */
00157
00158 /* Private macro -------------------------------------------------------------*/
00159 /* Private variables ---------------------------------------------------------*/
00160 /* Private function prototypes -----------------------------------------------*/
00161 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
00162   * @{
00163   */
00164 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00165
00166 static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
00167 static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
00168 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
00169 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
00170
00171 static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
00172
00173 static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
00174
00175 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
00176 /**
00177   * @}
00178   */
00179
00180 /* Exported functions --------------------------------------------------------*/
00181
00182 /** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
00183   * @{
00184   */
00185
00186 /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
00187  *  @brief    Initialization and Configuration functions
00188  *
00189 @verbatim
00190  ===============================================================================
00191               ##### Initialization and de-initialization functions #####
00192  ===============================================================================
00193     [..]  This subsection provides a set of functions allowing to initialize and
00194           deinitialize the SMBUSx peripheral:
00195
00196       (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
00197           all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
00198
00199       (+) Call the function HAL_SMBUS_Init() to configure the selected device with
00200           the selected configuration:
00201         (++) Clock Timing
00202         (++) Bus Timeout
00203         (++) Analog Filer mode
00204         (++) Own Address 1
00205         (++) Addressing mode (Master, Slave)
00206         (++) Dual Addressing mode
00207         (++) Own Address 2
00208         (++) Own Address 2 Mask
00209         (++) General call mode
00210         (++) Nostretch mode
00211         (++) Packet Error Check mode
00212         (++) Peripheral mode
00213
00214
00215       (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
00216           of the selected SMBUSx peripheral.
00217
00218       (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
00219           HAL_SMBUS_ConfigDigitalFilter().
00220
00221 @endverbatim
00222   * @{
00223   */
00224
00225 /**
00226   * @brief  Initialize the SMBUS according to the specified parameters
00227   *         in the SMBUS_InitTypeDef and initialize the associated handle.
00228   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00229   *                the configuration information for the specified SMBUS.
00230   * @retval HAL status
00231   */
00232 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
00233 {
00234   /* Check the SMBUS handle allocation */
00235   if (hsmbus == NULL)
00236   {
00237     return HAL_ERROR;
00238   }
00239
00240   /* Check the parameters */
00241   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00242   assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
00243   assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
00244   assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
00245   assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
00246   assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
00247   assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
00248   assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
00249   assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
00250   assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
00251   assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
00252
00253   if (hsmbus->State == HAL_SMBUS_STATE_RESET)
00254   {
00255     /* Allocate lock resource and initialize it */
00256     hsmbus->Lock = HAL_UNLOCKED;
00257
00258     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00259     HAL_SMBUS_MspInit(hsmbus);
00260   }
00261
00262   hsmbus->State = HAL_SMBUS_STATE_BUSY;
00263
00264   /* Disable the selected SMBUS peripheral */
00265   __HAL_SMBUS_DISABLE(hsmbus);
00266
00267   /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
00268   /* Configure SMBUSx: Frequency range */
00269   hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
00270
00271   /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
00272   /* Configure SMBUSx: Bus Timeout  */
00273   hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
00274   hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
00275   hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
00276
00277   /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
00278   /* Configure SMBUSx: Own Address1 and ack own address1 mode */
00279   hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
00280
00281   if (hsmbus->Init.OwnAddress1 != 0U)
00282   {
00283     if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
00284     {
00285       hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
00286     }
00287     else /* SMBUS_ADDRESSINGMODE_10BIT */
00288     {
00289       hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
00290     }
00291   }
00292
00293   /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
00294   /* Configure SMBUSx: Addressing Master mode */
00295   if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
00296   {
00297     hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
00298   }
00299   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
00300   /* AUTOEND and NACK bit will be manage during Transfer process */
00301   hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
00302
00303   /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
00304   /* Configure SMBUSx: Dual mode and Own Address2 */
00305   hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
00306
00307   /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
00308   /* Configure SMBUSx: Generalcall and NoStretch mode */
00309   hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
00310
00311   /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
00312   if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
00313       && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
00314   {
00315     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
00316   }
00317
00318   /* Enable the selected SMBUS peripheral */
00319   __HAL_SMBUS_ENABLE(hsmbus);
00320
00321   hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00322   hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
00323   hsmbus->State = HAL_SMBUS_STATE_READY;
00324
00325   return HAL_OK;
00326 }
00327
00328 /**
00329   * @brief  DeInitialize the SMBUS peripheral.
00330   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00331   *                the configuration information for the specified SMBUS.
00332   * @retval HAL status
00333   */
00334 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
00335 {
00336   /* Check the SMBUS handle allocation */
00337   if (hsmbus == NULL)
00338   {
00339     return HAL_ERROR;
00340   }
00341
00342   /* Check the parameters */
00343   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00344
00345   hsmbus->State = HAL_SMBUS_STATE_BUSY;
00346
00347   /* Disable the SMBUS Peripheral Clock */
00348   __HAL_SMBUS_DISABLE(hsmbus);
00349
00350   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00351   HAL_SMBUS_MspDeInit(hsmbus);
00352
00353   hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00354   hsmbus->PreviousState =  HAL_SMBUS_STATE_RESET;
00355   hsmbus->State = HAL_SMBUS_STATE_RESET;
00356
00357   /* Release Lock */
00358   __HAL_UNLOCK(hsmbus);
00359
00360   return HAL_OK;
00361 }
00362
00363 /**
00364   * @brief Initialize the SMBUS MSP.
00365   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00366   *                the configuration information for the specified SMBUS.
00367   * @retval None
00368   */
00369 __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
00370 {
00371   /* Prevent unused argument(s) compilation warning */
00372   UNUSED(hsmbus);
00373
00374   /* NOTE : This function should not be modified, when the callback is needed,
00375             the HAL_SMBUS_MspInit could be implemented in the user file
00376    */
00377 }
00378
00379 /**
00380   * @brief DeInitialize the SMBUS MSP.
00381   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00382   *                the configuration information for the specified SMBUS.
00383   * @retval None
00384   */
00385 __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
00386 {
00387   /* Prevent unused argument(s) compilation warning */
00388   UNUSED(hsmbus);
00389
00390   /* NOTE : This function should not be modified, when the callback is needed,
00391             the HAL_SMBUS_MspDeInit could be implemented in the user file
00392    */
00393 }
00394
00395 /**
00396   * @brief  Configure Analog noise filter.
00397   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00398   *                the configuration information for the specified SMBUS.
00399   * @param  AnalogFilter This parameter can be one of the following values:
00400   *         @arg @ref SMBUS_ANALOGFILTER_ENABLE
00401   *         @arg @ref SMBUS_ANALOGFILTER_DISABLE
00402   * @retval HAL status
00403   */
00404 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
00405 {
00406   /* Check the parameters */
00407   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00408   assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
00409
00410   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00411   {
00412     /* Process Locked */
00413     __HAL_LOCK(hsmbus);
00414
00415     hsmbus->State = HAL_SMBUS_STATE_BUSY;
00416
00417     /* Disable the selected SMBUS peripheral */
00418     __HAL_SMBUS_DISABLE(hsmbus);
00419
00420     /* Reset ANOFF bit */
00421     hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
00422
00423     /* Set analog filter bit*/
00424     hsmbus->Instance->CR1 |= AnalogFilter;
00425
00426     __HAL_SMBUS_ENABLE(hsmbus);
00427
00428     hsmbus->State = HAL_SMBUS_STATE_READY;
00429
00430     /* Process Unlocked */
00431     __HAL_UNLOCK(hsmbus);
00432
00433     return HAL_OK;
00434   }
00435   else
00436   {
00437     return HAL_BUSY;
00438   }
00439 }
00440
00441 /**
00442   * @brief  Configure Digital noise filter.
00443   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00444   *                the configuration information for the specified SMBUS.
00445   * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
00446   * @retval HAL status
00447   */
00448 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
00449 {
00450   uint32_t tmpreg = 0U;
00451
00452   /* Check the parameters */
00453   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00454   assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
00455
00456   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00457   {
00458     /* Process Locked */
00459     __HAL_LOCK(hsmbus);
00460
00461     hsmbus->State = HAL_SMBUS_STATE_BUSY;
00462
00463     /* Disable the selected SMBUS peripheral */
00464     __HAL_SMBUS_DISABLE(hsmbus);
00465
00466     /* Get the old register value */
00467     tmpreg = hsmbus->Instance->CR1;
00468
00469     /* Reset I2C DNF bits [11:8] */
00470     tmpreg &= ~(I2C_CR1_DNF);
00471
00472     /* Set I2Cx DNF coefficient */
00473     tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
00474
00475     /* Store the new register value */
00476     hsmbus->Instance->CR1 = tmpreg;
00477
00478     __HAL_SMBUS_ENABLE(hsmbus);
00479
00480     hsmbus->State = HAL_SMBUS_STATE_READY;
00481
00482     /* Process Unlocked */
00483     __HAL_UNLOCK(hsmbus);
00484
00485     return HAL_OK;
00486   }
00487   else
00488   {
00489     return HAL_BUSY;
00490   }
00491 }
00492
00493 /**
00494   * @}
00495   */
00496
00497 /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
00498  *  @brief   Data transfers functions
00499  *
00500 @verbatim
00501  ===============================================================================
00502                       ##### IO operation functions #####
00503  ===============================================================================
00504     [..]
00505     This subsection provides a set of functions allowing to manage the SMBUS data
00506     transfers.
00507
00508     (#) Blocking mode function to check if device is ready for usage is :
00509         (++) HAL_SMBUS_IsDeviceReady()
00510
00511     (#) There is only one mode of transfer:
00512        (++) Non-Blocking mode : The communication is performed using Interrupts.
00513             These functions return the status of the transfer startup.
00514             The end of the data processing will be indicated through the
00515             dedicated SMBUS IRQ when using Interrupt mode.
00516
00517     (#) Non-Blocking mode functions with Interrupt are :
00518         (++) HAL_SMBUS_Master_Transmit_IT()
00519         (++) HAL_SMBUS_Master_Receive_IT()
00520         (++) HAL_SMBUS_Slave_Transmit_IT()
00521         (++) HAL_SMBUS_Slave_Receive_IT()
00522         (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
00523         (++) HAL_SMBUS_DisableListen_IT()
00524         (++) HAL_SMBUS_EnableAlert_IT()
00525         (++) HAL_SMBUS_DisableAlert_IT()
00526
00527     (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
00528         (++) HAL_SMBUS_MasterTxCpltCallback()
00529         (++) HAL_SMBUS_MasterRxCpltCallback()
00530         (++) HAL_SMBUS_SlaveTxCpltCallback()
00531         (++) HAL_SMBUS_SlaveRxCpltCallback()
00532         (++) HAL_SMBUS_AddrCallback()
00533         (++) HAL_SMBUS_ListenCpltCallback()
00534         (++) HAL_SMBUS_ErrorCallback()
00535
00536 @endverbatim
00537   * @{
00538   */
00539
00540 /**
00541   * @brief  Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
00542   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00543   *                the configuration information for the specified SMBUS.
00544   * @param  DevAddress Target device address: The device 7 bits address value
00545   *         in datasheet must be shift at right before call interface
00546   * @param  pData Pointer to data buffer
00547   * @param  Size Amount of data to be sent
00548   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
00549   * @retval HAL status
00550   */
00551 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
00552 {
00553   /* Check the parameters */
00554   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
00555
00556   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00557   {
00558     /* Process Locked */
00559     __HAL_LOCK(hsmbus);
00560
00561     hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
00562     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00563     /* Prepare transfer parameters */
00564     hsmbus->pBuffPtr = pData;
00565     hsmbus->XferCount = Size;
00566     hsmbus->XferOptions = XferOptions;
00567
00568     /* In case of Quick command, remove autoend mode */
00569     /* Manage the stop generation by software */
00570     if (hsmbus->pBuffPtr == NULL)
00571     {
00572       hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
00573     }
00574
00575     if (Size > MAX_NBYTE_SIZE)
00576     {
00577       hsmbus->XferSize = MAX_NBYTE_SIZE;
00578     }
00579     else
00580     {
00581       hsmbus->XferSize = Size;
00582     }
00583
00584     /* Send Slave Address */
00585     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
00586     if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
00587     {
00588       SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
00589     }
00590     else
00591     {
00592       /* If transfer direction not change, do not generate Restart Condition */
00593       /* Mean Previous state is same as current state */
00594       if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
00595       {
00596         SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
00597       }
00598       /* Else transfer direction change, so generate Restart with new transfer direction */
00599       else
00600       {
00601         /* Convert OTHER_xxx XferOptions if any */
00602         SMBUS_ConvertOtherXferOptions(hsmbus);
00603
00604         /* Handle Transfer */
00605         SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
00606       }
00607
00608       /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
00609       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
00610       if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
00611       {
00612         hsmbus->XferSize--;
00613         hsmbus->XferCount--;
00614       }
00615     }
00616
00617     /* Process Unlocked */
00618     __HAL_UNLOCK(hsmbus);
00619
00620     /* Note : The SMBUS interrupts must be enabled after unlocking current process
00621               to avoid the risk of SMBUS interrupt handle execution before current
00622               process unlock */
00623     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
00624
00625     return HAL_OK;
00626   }
00627   else
00628   {
00629     return HAL_BUSY;
00630   }
00631 }
00632
00633 /**
00634   * @brief  Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
00635   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00636   *                the configuration information for the specified SMBUS.
00637   * @param  DevAddress Target device address: The device 7 bits address value
00638   *         in datasheet must be shift at right before call interface
00639   * @param  pData Pointer to data buffer
00640   * @param  Size Amount of data to be sent
00641   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
00642   * @retval HAL status
00643   */
00644 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
00645 {
00646   /* Check the parameters */
00647   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
00648
00649   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00650   {
00651     /* Process Locked */
00652     __HAL_LOCK(hsmbus);
00653
00654     hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
00655     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00656
00657     /* Prepare transfer parameters */
00658     hsmbus->pBuffPtr = pData;
00659     hsmbus->XferCount = Size;
00660     hsmbus->XferOptions = XferOptions;
00661
00662     /* In case of Quick command, remove autoend mode */
00663     /* Manage the stop generation by software */
00664     if (hsmbus->pBuffPtr == NULL)
00665     {
00666       hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
00667     }
00668
00669     if (Size > MAX_NBYTE_SIZE)
00670     {
00671       hsmbus->XferSize = MAX_NBYTE_SIZE;
00672     }
00673     else
00674     {
00675       hsmbus->XferSize = Size;
00676     }
00677
00678     /* Send Slave Address */
00679     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
00680     if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
00681     {
00682       SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
00683     }
00684     else
00685     {
00686       /* If transfer direction not change, do not generate Restart Condition */
00687       /* Mean Previous state is same as current state */
00688       if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
00689       {
00690         SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
00691       }
00692       /* Else transfer direction change, so generate Restart with new transfer direction */
00693       else
00694       {
00695         /* Convert OTHER_xxx XferOptions if any */
00696         SMBUS_ConvertOtherXferOptions(hsmbus);
00697
00698         /* Handle Transfer */
00699         SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
00700       }
00701     }
00702
00703     /* Process Unlocked */
00704     __HAL_UNLOCK(hsmbus);
00705
00706     /* Note : The SMBUS interrupts must be enabled after unlocking current process
00707               to avoid the risk of SMBUS interrupt handle execution before current
00708               process unlock */
00709     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
00710
00711     return HAL_OK;
00712   }
00713   else
00714   {
00715     return HAL_BUSY;
00716   }
00717 }
00718
00719 /**
00720   * @brief  Abort a master/host SMBUS process communication with Interrupt.
00721   * @note   This abort can be called only if state is ready
00722   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00723   *                the configuration information for the specified SMBUS.
00724   * @param  DevAddress Target device address: The device 7 bits address value
00725   *         in datasheet must be shift at right before call interface
00726   * @retval HAL status
00727   */
00728 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
00729 {
00730   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00731   {
00732     /* Process Locked */
00733     __HAL_LOCK(hsmbus);
00734
00735     /* Keep the same state as previous */
00736     /* to perform as well the call of the corresponding end of transfer callback */
00737     if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
00738     {
00739       hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
00740     }
00741     else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
00742     {
00743       hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
00744     }
00745     else
00746     {
00747       /* Wrong usage of abort function */
00748       /* This function should be used only in case of abort monitored by master device */
00749       return HAL_ERROR;
00750     }
00751     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00752
00753     /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
00754     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
00755     SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
00756
00757     /* Process Unlocked */
00758     __HAL_UNLOCK(hsmbus);
00759
00760     /* Note : The SMBUS interrupts must be enabled after unlocking current process
00761               to avoid the risk of SMBUS interrupt handle execution before current
00762               process unlock */
00763     if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
00764     {
00765       SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
00766     }
00767     else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
00768     {
00769       SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
00770     }
00771
00772     return HAL_OK;
00773   }
00774   else
00775   {
00776     return HAL_BUSY;
00777   }
00778 }
00779
00780 /**
00781   * @brief  Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
00782   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00783   *                the configuration information for the specified SMBUS.
00784   * @param  pData Pointer to data buffer
00785   * @param  Size Amount of data to be sent
00786   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
00787   * @retval HAL status
00788   */
00789 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
00790 {
00791   /* Check the parameters */
00792   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
00793
00794   if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
00795   {
00796     if ((pData == NULL) || (Size == 0U))
00797     {
00798       return  HAL_ERROR;
00799     }
00800
00801     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
00802     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
00803
00804     /* Process Locked */
00805     __HAL_LOCK(hsmbus);
00806
00807     hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
00808     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00809
00810     /* Set SBC bit to manage Acknowledge at each bit */
00811     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
00812
00813     /* Enable Address Acknowledge */
00814     hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
00815
00816     /* Prepare transfer parameters */
00817     hsmbus->pBuffPtr = pData;
00818     hsmbus->XferCount = Size;
00819     hsmbus->XferOptions = XferOptions;
00820
00821     /* Convert OTHER_xxx XferOptions if any */
00822     SMBUS_ConvertOtherXferOptions(hsmbus);
00823
00824     if (Size > MAX_NBYTE_SIZE)
00825     {
00826       hsmbus->XferSize = MAX_NBYTE_SIZE;
00827     }
00828     else
00829     {
00830       hsmbus->XferSize = Size;
00831     }
00832
00833     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
00834     if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
00835     {
00836       SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
00837     }
00838     else
00839     {
00840       /* Set NBYTE to transmit */
00841       SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
00842
00843       /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
00844       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
00845       if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
00846       {
00847         hsmbus->XferSize--;
00848         hsmbus->XferCount--;
00849       }
00850     }
00851
00852     /* Clear ADDR flag after prepare the transfer parameters */
00853     /* This action will generate an acknowledge to the HOST */
00854     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
00855
00856     /* Process Unlocked */
00857     __HAL_UNLOCK(hsmbus);
00858
00859     /* Note : The SMBUS interrupts must be enabled after unlocking current process
00860               to avoid the risk of SMBUS interrupt handle execution before current
00861               process unlock */
00862     /* REnable ADDR interrupt */
00863     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
00864
00865     return HAL_OK;
00866   }
00867   else
00868   {
00869     return HAL_ERROR;
00870   }
00871 }
00872
00873 /**
00874   * @brief  Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
00875   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00876   *                the configuration information for the specified SMBUS.
00877   * @param  pData Pointer to data buffer
00878   * @param  Size Amount of data to be sent
00879   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
00880   * @retval HAL status
00881   */
00882 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
00883 {
00884   /* Check the parameters */
00885   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
00886
00887   if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
00888   {
00889     if ((pData == NULL) || (Size == 0U))
00890     {
00891       return  HAL_ERROR;
00892     }
00893
00894     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
00895     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
00896
00897     /* Process Locked */
00898     __HAL_LOCK(hsmbus);
00899
00900     hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
00901     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00902
00903     /* Set SBC bit to manage Acknowledge at each bit */
00904     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
00905
00906     /* Enable Address Acknowledge */
00907     hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
00908
00909     /* Prepare transfer parameters */
00910     hsmbus->pBuffPtr = pData;
00911     hsmbus->XferSize = Size;
00912     hsmbus->XferCount = Size;
00913     hsmbus->XferOptions = XferOptions;
00914
00915     /* Convert OTHER_xxx XferOptions if any */
00916     SMBUS_ConvertOtherXferOptions(hsmbus);
00917
00918     /* Set NBYTE to receive */
00919     /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
00920     /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
00921     /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
00922     /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
00923     if ((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
00924     {
00925       SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
00926     }
00927     else
00928     {
00929       SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
00930     }
00931
00932     /* Clear ADDR flag after prepare the transfer parameters */
00933     /* This action will generate an acknowledge to the HOST */
00934     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
00935
00936     /* Process Unlocked */
00937     __HAL_UNLOCK(hsmbus);
00938
00939     /* Note : The SMBUS interrupts must be enabled after unlocking current process
00940               to avoid the risk of SMBUS interrupt handle execution before current
00941               process unlock */
00942     /* REnable ADDR interrupt */
00943     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
00944
00945     return HAL_OK;
00946   }
00947   else
00948   {
00949     return HAL_ERROR;
00950   }
00951 }
00952
00953 /**
00954   * @brief  Enable the Address listen mode with Interrupt.
00955   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00956   *                the configuration information for the specified SMBUS.
00957   * @retval HAL status
00958   */
00959 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
00960 {
00961   hsmbus->State = HAL_SMBUS_STATE_LISTEN;
00962
00963   /* Enable the Address Match interrupt */
00964   SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
00965
00966   return HAL_OK;
00967 }
00968
00969 /**
00970   * @brief  Disable the Address listen mode with Interrupt.
00971   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00972   *                the configuration information for the specified SMBUS.
00973   * @retval HAL status
00974   */
00975 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
00976 {
00977   /* Disable Address listen mode only if a transfer is not ongoing */
00978   if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
00979   {
00980     hsmbus->State = HAL_SMBUS_STATE_READY;
00981
00982     /* Disable the Address Match interrupt */
00983     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
00984
00985     return HAL_OK;
00986   }
00987   else
00988   {
00989     return HAL_BUSY;
00990   }
00991 }
00992
00993 /**
00994   * @brief  Enable the SMBUS alert mode with Interrupt.
00995   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00996   *                the configuration information for the specified SMBUSx peripheral.
00997   * @retval HAL status
00998   */
00999 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
01000 {
01001   /* Enable SMBus alert */
01002   hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
01003
01004   /* Clear ALERT flag */
01005   __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
01006
01007   /* Enable Alert Interrupt */
01008   SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
01009
01010   return HAL_OK;
01011 }
01012 /**
01013   * @brief  Disable the SMBUS alert mode with Interrupt.
01014   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01015   *                the configuration information for the specified SMBUSx peripheral.
01016   * @retval HAL status
01017   */
01018 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
01019 {
01020   /* Enable SMBus alert */
01021   hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
01022
01023   /* Disable Alert Interrupt */
01024   SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
01025
01026   return HAL_OK;
01027 }
01028
01029 /**
01030   * @brief  Check if target device is ready for communication.
01031   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01032   *                the configuration information for the specified SMBUS.
01033   * @param  DevAddress Target device address: The device 7 bits address value
01034   *         in datasheet must be shift at right before call interface
01035   * @param  Trials Number of trials
01036   * @param  Timeout Timeout duration
01037   * @retval HAL status
01038   */
01039 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
01040 {
01041   uint32_t tickstart = 0U;
01042
01043   __IO uint32_t SMBUS_Trials = 0U;
01044
01045   if (hsmbus->State == HAL_SMBUS_STATE_READY)
01046   {
01047     if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
01048     {
01049       return HAL_BUSY;
01050     }
01051
01052     /* Process Locked */
01053     __HAL_LOCK(hsmbus);
01054
01055     hsmbus->State = HAL_SMBUS_STATE_BUSY;
01056     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01057
01058     do
01059     {
01060       /* Generate Start */
01061       hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress);
01062
01063       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01064       /* Wait until STOPF flag is set or a NACK flag is set*/
01065       tickstart = HAL_GetTick();
01066       while ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
01067       {
01068         if (Timeout != HAL_MAX_DELAY)
01069         {
01070           if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
01071           {
01072             /* Device is ready */
01073             hsmbus->State = HAL_SMBUS_STATE_READY;
01074
01075             /* Process Unlocked */
01076             __HAL_UNLOCK(hsmbus);
01077             return HAL_TIMEOUT;
01078           }
01079         }
01080       }
01081
01082       /* Check if the NACKF flag has not been set */
01083       if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
01084       {
01085         /* Wait until STOPF flag is reset */
01086         if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01087         {
01088           return HAL_TIMEOUT;
01089         }
01090
01091         /* Clear STOP Flag */
01092         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01093
01094         /* Device is ready */
01095         hsmbus->State = HAL_SMBUS_STATE_READY;
01096
01097         /* Process Unlocked */
01098         __HAL_UNLOCK(hsmbus);
01099
01100         return HAL_OK;
01101       }
01102       else
01103       {
01104         /* Wait until STOPF flag is reset */
01105         if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01106         {
01107           return HAL_TIMEOUT;
01108         }
01109
01110         /* Clear NACK Flag */
01111         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01112
01113         /* Clear STOP Flag, auto generated with autoend*/
01114         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01115       }
01116
01117       /* Check if the maximum allowed number of trials has been reached */
01118       if (SMBUS_Trials++ == Trials)
01119       {
01120         /* Generate Stop */
01121         hsmbus->Instance->CR2 |= I2C_CR2_STOP;
01122
01123         /* Wait until STOPF flag is reset */
01124         if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01125         {
01126           return HAL_TIMEOUT;
01127         }
01128
01129         /* Clear STOP Flag */
01130         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01131       }
01132     }
01133     while (SMBUS_Trials < Trials);
01134
01135     hsmbus->State = HAL_SMBUS_STATE_READY;
01136
01137     /* Process Unlocked */
01138     __HAL_UNLOCK(hsmbus);
01139
01140     return HAL_TIMEOUT;
01141   }
01142   else
01143   {
01144     return HAL_BUSY;
01145   }
01146 }
01147 /**
01148   * @}
01149   */
01150
01151 /** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
01152  * @{
01153  */
01154
01155 /**
01156   * @brief  Handle SMBUS event interrupt request.
01157   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01158   *                the configuration information for the specified SMBUS.
01159   * @retval None
01160   */
01161 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
01162 {
01163   uint32_t tmpisrvalue = 0U;
01164
01165   /* Use a local variable to store the current ISR flags */
01166   /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
01167   tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
01168
01169   /* SMBUS in mode Transmitter ---------------------------------------------------*/
01170   if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
01171   {
01172     /* Slave mode selected */
01173     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
01174     {
01175       SMBUS_Slave_ISR(hsmbus);
01176     }
01177     /* Master mode selected */
01178     else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01179     {
01180       SMBUS_Master_ISR(hsmbus);
01181     }
01182   }
01183
01184   /* SMBUS in mode Receiver ----------------------------------------------------*/
01185   if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
01186   {
01187     /* Slave mode selected */
01188     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
01189     {
01190       SMBUS_Slave_ISR(hsmbus);
01191     }
01192     /* Master mode selected */
01193     else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01194     {
01195       SMBUS_Master_ISR(hsmbus);
01196     }
01197   }
01198
01199   /* SMBUS in mode Listener Only --------------------------------------------------*/
01200   if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
01201       && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
01202   {
01203     if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
01204     {
01205       SMBUS_Slave_ISR(hsmbus);
01206     }
01207   }
01208 }
01209
01210 /**
01211   * @brief  Handle SMBUS error interrupt request.
01212   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01213   *                the configuration information for the specified SMBUS.
01214   * @retval None
01215   */
01216 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
01217 {
01218   SMBUS_ITErrorHandler(hsmbus);
01219 }
01220
01221 /**
01222   * @brief  Master Tx Transfer completed callback.
01223   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01224   *                the configuration information for the specified SMBUS.
01225   * @retval None
01226   */
01227 __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01228 {
01229   /* Prevent unused argument(s) compilation warning */
01230   UNUSED(hsmbus);
01231
01232   /* NOTE : This function should not be modified, when the callback is needed,
01233             the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
01234    */
01235 }
01236
01237 /**
01238   * @brief  Master Rx Transfer completed callback.
01239   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01240   *                the configuration information for the specified SMBUS.
01241   * @retval None
01242   */
01243 __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01244 {
01245   /* Prevent unused argument(s) compilation warning */
01246   UNUSED(hsmbus);
01247
01248   /* NOTE : This function should not be modified, when the callback is needed,
01249             the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
01250    */
01251 }
01252
01253 /** @brief  Slave Tx Transfer completed callback.
01254   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01255   *                the configuration information for the specified SMBUS.
01256   * @retval None
01257   */
01258 __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01259 {
01260   /* Prevent unused argument(s) compilation warning */
01261   UNUSED(hsmbus);
01262
01263   /* NOTE : This function should not be modified, when the callback is needed,
01264             the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
01265    */
01266 }
01267
01268 /**
01269   * @brief  Slave Rx Transfer completed callback.
01270   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01271   *                the configuration information for the specified SMBUS.
01272   * @retval None
01273   */
01274 __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01275 {
01276   /* Prevent unused argument(s) compilation warning */
01277   UNUSED(hsmbus);
01278
01279   /* NOTE : This function should not be modified, when the callback is needed,
01280             the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
01281    */
01282 }
01283
01284 /**
01285   * @brief  Slave Address Match callback.
01286   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01287   *                the configuration information for the specified SMBUS.
01288   * @param  TransferDirection Master request Transfer Direction (Write/Read)
01289   * @param  AddrMatchCode Address Match Code
01290   * @retval None
01291   */
01292 __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
01293 {
01294   /* Prevent unused argument(s) compilation warning */
01295   UNUSED(hsmbus);
01296   UNUSED(TransferDirection);
01297   UNUSED(AddrMatchCode);
01298
01299   /* NOTE : This function should not be modified, when the callback is needed,
01300             the HAL_SMBUS_AddrCallback() could be implemented in the user file
01301    */
01302 }
01303
01304 /**
01305   * @brief  Listen Complete callback.
01306   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01307   *                the configuration information for the specified SMBUS.
01308   * @retval None
01309   */
01310 __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01311 {
01312   /* Prevent unused argument(s) compilation warning */
01313   UNUSED(hsmbus);
01314
01315   /* NOTE : This function should not be modified, when the callback is needed,
01316             the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
01317    */
01318 }
01319
01320 /**
01321   * @brief  SMBUS error callback.
01322   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01323   *                the configuration information for the specified SMBUS.
01324   * @retval None
01325   */
01326 __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
01327 {
01328   /* Prevent unused argument(s) compilation warning */
01329   UNUSED(hsmbus);
01330
01331   /* NOTE : This function should not be modified, when the callback is needed,
01332             the HAL_SMBUS_ErrorCallback() could be implemented in the user file
01333    */
01334 }
01335
01336 /**
01337   * @}
01338   */
01339
01340 /** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
01341  *  @brief   Peripheral State and Errors functions
01342  *
01343 @verbatim
01344  ===============================================================================
01345             ##### Peripheral State and Errors functions #####
01346  ===============================================================================
01347     [..]
01348     This subsection permits to get in run-time the status of the peripheral
01349     and the data flow.
01350
01351 @endverbatim
01352   * @{
01353   */
01354
01355 /**
01356   * @brief  Return the SMBUS handle state.
01357   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01358   *                the configuration information for the specified SMBUS.
01359   * @retval HAL state
01360   */
01361 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
01362 {
01363   /* Return SMBUS handle state */
01364   return hsmbus->State;
01365 }
01366
01367 /**
01368 * @brief  Return the SMBUS error code.
01369   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01370   *              the configuration information for the specified SMBUS.
01371 * @retval SMBUS Error Code
01372 */
01373 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
01374 {
01375   return hsmbus->ErrorCode;
01376 }
01377
01378 /**
01379   * @}
01380   */
01381
01382 /**
01383   * @}
01384   */
01385
01386 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
01387  *  @brief   Data transfers Private functions
01388   * @{
01389   */
01390
01391 /**
01392   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
01393   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01394   *                the configuration information for the specified SMBUS.
01395   * @retval HAL status
01396   */
01397 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
01398 {
01399   uint16_t DevAddress;
01400
01401   /* Process Locked */
01402   __HAL_LOCK(hsmbus);
01403
01404   if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
01405   {
01406     /* Clear NACK Flag */
01407     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01408
01409     /* Set corresponding Error Code */
01410     /* No need to generate STOP, it is automatically done */
01411     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
01412
01413     /* Process Unlocked */
01414     __HAL_UNLOCK(hsmbus);
01415
01416     /* Call the Error callback to inform upper layer */
01417     HAL_SMBUS_ErrorCallback(hsmbus);
01418   }
01419   else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
01420   {
01421     /* Check and treat errors if errors occurs during STOP process */
01422     SMBUS_ITErrorHandler(hsmbus);
01423
01424     /* Call the corresponding callback to inform upper layer of End of Transfer */
01425     if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01426     {
01427       /* Disable Interrupt */
01428       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01429
01430       /* Clear STOP Flag */
01431       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01432
01433       /* Clear Configuration Register 2 */
01434       SMBUS_RESET_CR2(hsmbus);
01435
01436       /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
01437       /* Disable the selected SMBUS peripheral */
01438       __HAL_SMBUS_DISABLE(hsmbus);
01439
01440       hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
01441       hsmbus->State = HAL_SMBUS_STATE_READY;
01442
01443       /* Process Unlocked */
01444       __HAL_UNLOCK(hsmbus);
01445
01446       /* REenable the selected SMBUS peripheral */
01447       __HAL_SMBUS_ENABLE(hsmbus);
01448
01449       HAL_SMBUS_MasterTxCpltCallback(hsmbus);
01450     }
01451     else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01452     {
01453       /* Store Last receive data if any */
01454       if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
01455       {
01456         /* Read data from RXDR */
01457         (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
01458
01459         if ((hsmbus->XferSize > 0U))
01460         {
01461           hsmbus->XferSize--;
01462           hsmbus->XferCount--;
01463         }
01464       }
01465
01466       /* Disable Interrupt */
01467       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01468
01469       /* Clear STOP Flag */
01470       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01471
01472       /* Clear Configuration Register 2 */
01473       SMBUS_RESET_CR2(hsmbus);
01474
01475       hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
01476       hsmbus->State = HAL_SMBUS_STATE_READY;
01477
01478       /* Process Unlocked */
01479       __HAL_UNLOCK(hsmbus);
01480
01481       HAL_SMBUS_MasterRxCpltCallback(hsmbus);
01482     }
01483   }
01484   else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
01485   {
01486     /* Read data from RXDR */
01487     (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
01488     hsmbus->XferSize--;
01489     hsmbus->XferCount--;
01490   }
01491   else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
01492   {
01493     /* Write data to TXDR */
01494     hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
01495     hsmbus->XferSize--;
01496     hsmbus->XferCount--;
01497   }
01498   else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
01499   {
01500     if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
01501     {
01502       DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
01503
01504       if (hsmbus->XferCount > MAX_NBYTE_SIZE)
01505       {
01506         SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
01507         hsmbus->XferSize = MAX_NBYTE_SIZE;
01508       }
01509       else
01510       {
01511         hsmbus->XferSize = hsmbus->XferCount;
01512         SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
01513         /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
01514         /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
01515         if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
01516         {
01517           hsmbus->XferSize--;
01518           hsmbus->XferCount--;
01519         }
01520       }
01521     }
01522     else if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount == 0U))
01523     {
01524       /* Call TxCpltCallback() if no stop mode is set */
01525       if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
01526       {
01527         /* Call the corresponding callback to inform upper layer of End of Transfer */
01528         if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01529         {
01530           /* Disable Interrupt */
01531           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01532           hsmbus->PreviousState = hsmbus->State;
01533           hsmbus->State = HAL_SMBUS_STATE_READY;
01534
01535           /* Process Unlocked */
01536           __HAL_UNLOCK(hsmbus);
01537
01538           HAL_SMBUS_MasterTxCpltCallback(hsmbus);
01539         }
01540         else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01541         {
01542           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01543           hsmbus->PreviousState = hsmbus->State;
01544           hsmbus->State = HAL_SMBUS_STATE_READY;
01545
01546           /* Process Unlocked */
01547           __HAL_UNLOCK(hsmbus);
01548
01549           HAL_SMBUS_MasterRxCpltCallback(hsmbus);
01550         }
01551       }
01552     }
01553   }
01554   else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
01555   {
01556     if (hsmbus->XferCount == 0U)
01557     {
01558       /* Specific use case for Quick command */
01559       if (hsmbus->pBuffPtr == NULL)
01560       {
01561         /* Generate a Stop command */
01562         hsmbus->Instance->CR2 |= I2C_CR2_STOP;
01563       }
01564       /* Call TxCpltCallback() if no stop mode is set */
01565       else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
01566       {
01567         /* No Generate Stop, to permit restart mode */
01568         /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
01569
01570         /* Call the corresponding callback to inform upper layer of End of Transfer */
01571         if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01572         {
01573           /* Disable Interrupt */
01574           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01575           hsmbus->PreviousState = hsmbus->State;
01576           hsmbus->State = HAL_SMBUS_STATE_READY;
01577
01578           /* Process Unlocked */
01579           __HAL_UNLOCK(hsmbus);
01580
01581           HAL_SMBUS_MasterTxCpltCallback(hsmbus);
01582         }
01583         else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01584         {
01585           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01586           hsmbus->PreviousState = hsmbus->State;
01587           hsmbus->State = HAL_SMBUS_STATE_READY;
01588
01589           /* Process Unlocked */
01590           __HAL_UNLOCK(hsmbus);
01591
01592           HAL_SMBUS_MasterRxCpltCallback(hsmbus);
01593         }
01594       }
01595     }
01596   }
01597
01598   /* Process Unlocked */
01599   __HAL_UNLOCK(hsmbus);
01600
01601   return HAL_OK;
01602 }
01603 /**
01604   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
01605   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01606   *                the configuration information for the specified SMBUS.
01607   * @retval HAL status
01608   */
01609 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
01610 {
01611   uint8_t TransferDirection = 0U;
01612   uint16_t SlaveAddrCode = 0U;
01613
01614   /* Process Locked */
01615   __HAL_LOCK(hsmbus);
01616
01617   if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
01618   {
01619     /* Check that SMBUS transfer finished */
01620     /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
01621     /* Mean XferCount == 0*/
01622     /* So clear Flag NACKF only */
01623     if (hsmbus->XferCount == 0U)
01624     {
01625       /* Clear NACK Flag */
01626       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01627
01628       /* Process Unlocked */
01629       __HAL_UNLOCK(hsmbus);
01630     }
01631     else
01632     {
01633       /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
01634       /* Clear NACK Flag */
01635       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01636
01637       /* Set HAL State to "Idle" State, mean to LISTEN state */
01638       /* So reset Slave Busy state */
01639       hsmbus->PreviousState = hsmbus->State;
01640       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
01641       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
01642
01643       /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
01644       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
01645
01646       /* Set ErrorCode corresponding to a Non-Acknowledge */
01647       hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
01648
01649       /* Process Unlocked */
01650       __HAL_UNLOCK(hsmbus);
01651
01652       /* Call the Error callback to inform upper layer */
01653       HAL_SMBUS_ErrorCallback(hsmbus);
01654     }
01655   }
01656   else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
01657   {
01658     TransferDirection = SMBUS_GET_DIR(hsmbus);
01659     SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
01660
01661     /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
01662     /* Other ADDRInterrupt will be treat in next Listen usecase */
01663     __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
01664
01665     /* Process Unlocked */
01666     __HAL_UNLOCK(hsmbus);
01667
01668     /* Call Slave Addr callback */
01669     HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
01670   }
01671   else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
01672   {
01673     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
01674     {
01675       /* Read data from RXDR */
01676       (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
01677       hsmbus->XferSize--;
01678       hsmbus->XferCount--;
01679
01680       if (hsmbus->XferCount == 1U)
01681       {
01682         /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
01683         /* or only the last Byte of Transfer */
01684         /* So reset the RELOAD bit mode */
01685         hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
01686         SMBUS_TransferConfig(hsmbus, 0U , 1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
01687       }
01688       else if (hsmbus->XferCount == 0U)
01689       {
01690         /* Last Byte is received, disable Interrupt */
01691         SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01692
01693         /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
01694         hsmbus->PreviousState = hsmbus->State;
01695         hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
01696
01697         /* Process Unlocked */
01698         __HAL_UNLOCK(hsmbus);
01699
01700         /* Call the Rx complete callback to inform upper layer of the end of receive process */
01701         HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
01702       }
01703       else
01704       {
01705         /* Set Reload for next Bytes */
01706         SMBUS_TransferConfig(hsmbus, 0U, 1U, SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
01707
01708         /* Ack last Byte Read */
01709         hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
01710       }
01711     }
01712     else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
01713     {
01714       if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
01715       {
01716         if (hsmbus->XferCount > MAX_NBYTE_SIZE)
01717         {
01718           SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
01719           hsmbus->XferSize = MAX_NBYTE_SIZE;
01720         }
01721         else
01722         {
01723           hsmbus->XferSize = hsmbus->XferCount;
01724           SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
01725           /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
01726           /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
01727           if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
01728           {
01729             hsmbus->XferSize--;
01730             hsmbus->XferCount--;
01731           }
01732         }
01733       }
01734     }
01735   }
01736   else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
01737   {
01738     /* Write data to TXDR only if XferCount not reach "0" */
01739     /* A TXIS flag can be set, during STOP treatment      */
01740     /* Check if all Data have already been sent */
01741     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
01742     if (hsmbus->XferCount > 0U)
01743     {
01744       /* Write data to TXDR */
01745       hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
01746       hsmbus->XferCount--;
01747       hsmbus->XferSize--;
01748     }
01749
01750     if (hsmbus->XferCount == 0U)
01751     {
01752       /* Last Byte is Transmitted */
01753       /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
01754       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01755       hsmbus->PreviousState = hsmbus->State;
01756       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
01757
01758       /* Process Unlocked */
01759       __HAL_UNLOCK(hsmbus);
01760
01761       /* Call the Tx complete callback to inform upper layer of the end of transmit process */
01762       HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
01763     }
01764   }
01765
01766   /* Check if STOPF is set */
01767   if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
01768   {
01769     if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
01770     {
01771       /* Store Last receive data if any */
01772       if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
01773       {
01774         /* Read data from RXDR */
01775         (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
01776
01777         if ((hsmbus->XferSize > 0U))
01778         {
01779           hsmbus->XferSize--;
01780           hsmbus->XferCount--;
01781         }
01782       }
01783
01784       /* Disable RX and TX Interrupts */
01785       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
01786
01787       /* Disable ADDR Interrupt */
01788       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
01789
01790       /* Disable Address Acknowledge */
01791       hsmbus->Instance->CR2 |= I2C_CR2_NACK;
01792
01793       /* Clear Configuration Register 2 */
01794       SMBUS_RESET_CR2(hsmbus);
01795
01796       /* Clear STOP Flag */
01797       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01798
01799       /* Clear ADDR flag */
01800       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
01801
01802       hsmbus->XferOptions = 0U;
01803       hsmbus->PreviousState = hsmbus->State;
01804       hsmbus->State = HAL_SMBUS_STATE_READY;
01805
01806       /* Process Unlocked */
01807       __HAL_UNLOCK(hsmbus);
01808
01809       /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
01810       HAL_SMBUS_ListenCpltCallback(hsmbus);
01811     }
01812   }
01813
01814   /* Process Unlocked */
01815   __HAL_UNLOCK(hsmbus);
01816
01817   return HAL_OK;
01818 }
01819 /**
01820   * @brief  Manage the enabling of Interrupts.
01821   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01822   *                the configuration information for the specified SMBUS.
01823   * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
01824   * @retval HAL status
01825   */
01826 static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
01827 {
01828   uint32_t tmpisr = 0U;
01829
01830   if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
01831   {
01832     /* Enable ERR interrupt */
01833     tmpisr |= SMBUS_IT_ERRI;
01834   }
01835
01836   if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
01837   {
01838     /* Enable ADDR, STOP interrupt */
01839     tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
01840   }
01841
01842   if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
01843   {
01844     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01845     tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
01846   }
01847
01848   if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
01849   {
01850     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01851     tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
01852   }
01853
01854   /* Enable interrupts only at the end */
01855   /* to avoid the risk of SMBUS interrupt handle execution before */
01856   /* all interrupts requested done */
01857   __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
01858
01859   return HAL_OK;
01860 }
01861 /**
01862   * @brief  Manage the disabling of Interrupts.
01863   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01864   *                the configuration information for the specified SMBUS.
01865   * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
01866   * @retval HAL status
01867   */
01868 static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
01869 {
01870   uint32_t tmpisr = 0U;
01871
01872   if (((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY))
01873   {
01874     /* Disable ERR interrupt */
01875     tmpisr |= SMBUS_IT_ERRI;
01876   }
01877
01878   if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
01879   {
01880     /* Disable TC, STOP, NACK, TXI interrupt */
01881     tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
01882
01883     if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
01884         && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
01885     {
01886       /* Disable ERR interrupt */
01887       tmpisr |= SMBUS_IT_ERRI;
01888     }
01889
01890     if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
01891     {
01892       /* Disable STOPI, NACKI */
01893       tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
01894     }
01895   }
01896
01897   if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
01898   {
01899     /* Disable TC, STOP, NACK, RXI interrupt */
01900     tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
01901
01902     if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
01903         && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
01904     {
01905       /* Disable ERR interrupt */
01906       tmpisr |= SMBUS_IT_ERRI;
01907     }
01908
01909     if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
01910     {
01911       /* Disable STOPI, NACKI */
01912       tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
01913     }
01914   }
01915
01916   if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
01917   {
01918     /* Enable ADDR, STOP interrupt */
01919     tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
01920
01921     if (SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
01922     {
01923       /* Disable ERR interrupt */
01924       tmpisr |= SMBUS_IT_ERRI;
01925     }
01926   }
01927
01928   /* Disable interrupts only at the end */
01929   /* to avoid a breaking situation like at "t" time */
01930   /* all disable interrupts request are not done */
01931   __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
01932
01933   return HAL_OK;
01934 }
01935
01936 /**
01937   * @brief  SMBUS interrupts error handler.
01938   * @param  hsmbus SMBUS handle.
01939   * @retval None
01940   */
01941 static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
01942 {
01943   uint32_t itflags   = READ_REG(hsmbus->Instance->ISR);
01944   uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
01945
01946   /* SMBUS Bus error interrupt occurred ------------------------------------*/
01947   if (((itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
01948   {
01949     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
01950
01951     /* Clear BERR flag */
01952     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
01953   }
01954
01955   /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
01956   if (((itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
01957   {
01958     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
01959
01960     /* Clear OVR flag */
01961     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
01962   }
01963
01964   /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
01965   if (((itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
01966   {
01967     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
01968
01969     /* Clear ARLO flag */
01970     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
01971   }
01972
01973   /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
01974   if (((itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
01975   {
01976     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
01977
01978     /* Clear TIMEOUT flag */
01979     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
01980   }
01981
01982   /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
01983   if (((itflags & SMBUS_FLAG_ALERT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
01984   {
01985     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
01986
01987     /* Clear ALERT flag */
01988     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
01989   }
01990
01991   /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
01992   if (((itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
01993   {
01994     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
01995
01996     /* Clear PEC error flag */
01997     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
01998   }
01999
02000   /* Call the Error Callback in case of Error detected */
02001   if ((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) && (hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
02002   {
02003     /* Do not Reset the HAL state in case of ALERT error */
02004     if ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
02005     {
02006       if (((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
02007           || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
02008       {
02009         /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
02010         /* keep HAL_SMBUS_STATE_LISTEN if set */
02011         hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
02012         hsmbus->State = HAL_SMBUS_STATE_LISTEN;
02013       }
02014     }
02015
02016     /* Call the Error callback to inform upper layer */
02017     HAL_SMBUS_ErrorCallback(hsmbus);
02018   }
02019 }
02020
02021 /**
02022   * @brief  Handle SMBUS Communication Timeout.
02023   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
02024   *                the configuration information for the specified SMBUS.
02025   * @param  Flag Specifies the SMBUS flag to check.
02026   * @param  Status The new Flag status (SET or RESET).
02027   * @param  Timeout Timeout duration
02028   * @retval HAL status
02029   */
02030 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
02031 {
02032   uint32_t tickstart = HAL_GetTick();
02033
02034   /* Wait until flag is set */
02035   if (Status == RESET)
02036   {
02037     while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
02038     {
02039       /* Check for the Timeout */
02040       if (Timeout != HAL_MAX_DELAY)
02041       {
02042         if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
02043         {
02044           hsmbus->PreviousState = hsmbus->State;
02045           hsmbus->State = HAL_SMBUS_STATE_READY;
02046
02047           /* Process Unlocked */
02048           __HAL_UNLOCK(hsmbus);
02049
02050           return HAL_TIMEOUT;
02051         }
02052       }
02053     }
02054   }
02055   else
02056   {
02057     while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
02058     {
02059       /* Check for the Timeout */
02060       if (Timeout != HAL_MAX_DELAY)
02061       {
02062         if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
02063         {
02064           hsmbus->PreviousState = hsmbus->State;
02065           hsmbus->State = HAL_SMBUS_STATE_READY;
02066
02067           /* Process Unlocked */
02068           __HAL_UNLOCK(hsmbus);
02069
02070           return HAL_TIMEOUT;
02071         }
02072       }
02073     }
02074   }
02075   return HAL_OK;
02076 }
02077
02078 /**
02079   * @brief  Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
02080   * @param  hsmbus SMBUS handle.
02081   * @param  DevAddress specifies the slave address to be programmed.
02082   * @param  Size specifies the number of bytes to be programmed.
02083   *   This parameter must be a value between 0 and 255.
02084   * @param  Mode New state of the SMBUS START condition generation.
02085   *   This parameter can be one or a combination  of the following values:
02086   *     @arg @ref SMBUS_RELOAD_MODE Enable Reload mode.
02087   *     @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode.
02088   *     @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
02089   *     @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
02090   * @param  Request New state of the SMBUS START condition generation.
02091   *   This parameter can be one of the following values:
02092   *     @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
02093   *     @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
02094   *     @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request.
02095   *     @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
02096   * @retval None
02097   */
02098 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
02099 {
02100   uint32_t tmpreg = 0U;
02101
02102   /* Check the parameters */
02103   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
02104   assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
02105   assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
02106
02107   /* Get the CR2 register value */
02108   tmpreg = hsmbus->Instance->CR2;
02109
02110   /* clear tmpreg specific bits */
02111   tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE));
02112
02113   /* update tmpreg */
02114   tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U) & I2C_CR2_NBYTES) | \
02115                        (uint32_t)Mode | (uint32_t)Request);
02116
02117   /* update CR2 register */
02118   hsmbus->Instance->CR2 = tmpreg;
02119 }
02120
02121 /**
02122   * @brief  Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
02123   * @param  hsmbus SMBUS handle.
02124   * @retval None
02125   */
02126 static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
02127 {
02128   /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC   */
02129   /* it request implicitly to generate a restart condition */
02130   /* set XferOptions to SMBUS_FIRST_FRAME                  */
02131   if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
02132   {
02133     hsmbus->XferOptions = SMBUS_FIRST_FRAME;
02134   }
02135   /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
02136   /* it request implicitly to generate a restart condition      */
02137   /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE  */
02138   else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
02139   {
02140     hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
02141   }
02142   /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
02143   /* it request implicitly to generate a restart condition             */
02144   /* then generate a stop condition at the end of transfer             */
02145   /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC              */
02146   else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
02147   {
02148     hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
02149   }
02150   /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
02151   /* it request implicitly to generate a restart condition               */
02152   /* then generate a stop condition at the end of transfer               */
02153   /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC              */
02154   else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
02155   {
02156     hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
02157   }
02158 }
02159 /**
02160   * @}
02161   */
02162
02163 #endif /* HAL_SMBUS_MODULE_ENABLED */
02164 /**
02165   * @}
02166   */
02167
02168 /**
02169   * @}
02170   */
02171
02172 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_smbus.h Source File

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stm32f3xx_hal_smbus.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_smbus.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SMBUS HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_SMBUS_H
00038 #define __STM32F3xx_HAL_SMBUS_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup SMBUS
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types
00057   * @{
00058   */
00059
00060 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
00061   * @brief  SMBUS Configuration Structure definition
00062   * @{
00063   */
00064 typedef struct
00065 {
00066   uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
00067                                      This parameter calculated by referring to SMBUS initialization
00068                                             section in Reference manual */
00069   uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
00070                                      This parameter can be a value of @ref SMBUS_Analog_Filter */
00071
00072   uint32_t OwnAddress1;            /*!< Specifies the first device own address.
00073                                      This parameter can be a 7-bit or 10-bit address. */
00074
00075   uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
00076                                      This parameter can be a value of @ref SMBUS_addressing_mode */
00077
00078   uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
00079                                      This parameter can be a value of @ref SMBUS_dual_addressing_mode */
00080
00081   uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
00082                                      This parameter can be a 7-bit address. */
00083
00084   uint32_t OwnAddress2Masks;       /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
00085                                      This parameter can be a value of @ref SMBUS_own_address2_masks. */
00086
00087   uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
00088                                      This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
00089
00090   uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
00091                                      This parameter can be a value of @ref SMBUS_nostretch_mode */
00092
00093   uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
00094                                      This parameter can be a value of @ref SMBUS_packet_error_check_mode */
00095
00096   uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
00097                                      This parameter can be a value of @ref SMBUS_peripheral_mode */
00098
00099   uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
00100                                       (Enable bits and different timeout values)
00101                                      This parameter calculated by referring to SMBUS initialization
00102                                          section in Reference manual */
00103 } SMBUS_InitTypeDef;
00104 /**
00105   * @}
00106   */
00107
00108 /** @defgroup HAL_state_definition HAL state definition
00109   * @brief  HAL State definition
00110   * @{
00111   */
00112 #define HAL_SMBUS_STATE_RESET           (0x00000000U)  /*!< SMBUS not yet initialized or disabled         */
00113 #define HAL_SMBUS_STATE_READY           (0x00000001U)  /*!< SMBUS initialized and ready for use           */
00114 #define HAL_SMBUS_STATE_BUSY            (0x00000002U)  /*!< SMBUS internal process is ongoing             */
00115 #define HAL_SMBUS_STATE_MASTER_BUSY_TX  (0x00000012U)  /*!< Master Data Transmission process is ongoing   */
00116 #define HAL_SMBUS_STATE_MASTER_BUSY_RX  (0x00000022U)  /*!< Master Data Reception process is ongoing      */
00117 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */
00118 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX   (0x00000042U)  /*!< Slave Data Reception process is ongoing       */
00119 #define HAL_SMBUS_STATE_TIMEOUT         (0x00000003U)  /*!< Timeout state                                 */
00120 #define HAL_SMBUS_STATE_ERROR           (0x00000004U)  /*!< Reception process is ongoing                  */
00121 #define HAL_SMBUS_STATE_LISTEN          (0x00000008U)   /*!< Address Listen Mode is ongoing                */
00122 /**
00123   * @}
00124   */
00125
00126 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
00127   * @brief  SMBUS Error Code definition
00128   * @{
00129   */
00130 #define HAL_SMBUS_ERROR_NONE            (0x00000000U)    /*!< No error             */
00131 #define HAL_SMBUS_ERROR_BERR            (0x00000001U)    /*!< BERR error           */
00132 #define HAL_SMBUS_ERROR_ARLO            (0x00000002U)    /*!< ARLO error           */
00133 #define HAL_SMBUS_ERROR_ACKF            (0x00000004U)    /*!< ACKF error           */
00134 #define HAL_SMBUS_ERROR_OVR             (0x00000008U)    /*!< OVR error            */
00135 #define HAL_SMBUS_ERROR_HALTIMEOUT      (0x00000010U)    /*!< Timeout error        */
00136 #define HAL_SMBUS_ERROR_BUSTIMEOUT      (0x00000020U)    /*!< Bus Timeout error    */
00137 #define HAL_SMBUS_ERROR_ALERT           (0x00000040U)    /*!< Alert error          */
00138 #define HAL_SMBUS_ERROR_PECERR          (0x00000080U)    /*!< PEC error            */
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
00144   * @brief  SMBUS handle Structure definition
00145   * @{
00146   */
00147 typedef struct
00148 {
00149   I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address       */
00150
00151   SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters     */
00152
00153   uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer   */
00154
00155   uint16_t                     XferSize;        /*!< SMBUS transfer size                */
00156
00157   __IO uint16_t                XferCount;       /*!< SMBUS transfer counter             */
00158
00159   __IO uint32_t                XferOptions;     /*!< SMBUS transfer options             */
00160
00161   __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous state */
00162
00163   HAL_LockTypeDef              Lock;            /*!< SMBUS locking object               */
00164
00165   __IO uint32_t                State;           /*!< SMBUS communication state          */
00166
00167   __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */
00168
00169 } SMBUS_HandleTypeDef;
00170 /**
00171   * @}
00172   */
00173
00174 /**
00175   * @}
00176   */
00177 /* Exported constants --------------------------------------------------------*/
00178
00179 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
00180   * @{
00181   */
00182
00183 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
00184   * @{
00185   */
00186 #define SMBUS_ANALOGFILTER_ENABLE               (0x00000000U)
00187 #define SMBUS_ANALOGFILTER_DISABLE              I2C_CR1_ANFOFF
00188 /**
00189   * @}
00190   */
00191
00192 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode
00193   * @{
00194   */
00195 #define SMBUS_ADDRESSINGMODE_7BIT               (0x00000001U)
00196 #define SMBUS_ADDRESSINGMODE_10BIT              (0x00000002U)
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
00202   * @{
00203   */
00204
00205 #define SMBUS_DUALADDRESS_DISABLE               (0x00000000U)
00206 #define SMBUS_DUALADDRESS_ENABLE                I2C_OAR2_OA2EN
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
00212   * @{
00213   */
00214
00215 #define SMBUS_OA2_NOMASK                        ((uint8_t)0x00U)
00216 #define SMBUS_OA2_MASK01                        ((uint8_t)0x01U)
00217 #define SMBUS_OA2_MASK02                        ((uint8_t)0x02U)
00218 #define SMBUS_OA2_MASK03                        ((uint8_t)0x03U)
00219 #define SMBUS_OA2_MASK04                        ((uint8_t)0x04U)
00220 #define SMBUS_OA2_MASK05                        ((uint8_t)0x05U)
00221 #define SMBUS_OA2_MASK06                        ((uint8_t)0x06U)
00222 #define SMBUS_OA2_MASK07                        ((uint8_t)0x07U)
00223 /**
00224   * @}
00225   */
00226
00227
00228 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
00229   * @{
00230   */
00231 #define SMBUS_GENERALCALL_DISABLE               (0x00000000U)
00232 #define SMBUS_GENERALCALL_ENABLE                I2C_CR1_GCEN
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup SMBUS_nostretch_mode  SMBUS nostretch mode
00238   * @{
00239   */
00240 #define SMBUS_NOSTRETCH_DISABLE                 (0x00000000U)
00241 #define SMBUS_NOSTRETCH_ENABLE                  I2C_CR1_NOSTRETCH
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
00247   * @{
00248   */
00249 #define SMBUS_PEC_DISABLE                       (0x00000000U)
00250 #define SMBUS_PEC_ENABLE                        I2C_CR1_PECEN
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
00256   * @{
00257   */
00258 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        I2C_CR1_SMBHEN
00259 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (0x00000000U)
00260 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   I2C_CR1_SMBDEN
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
00266   * @{
00267   */
00268
00269 #define  SMBUS_SOFTEND_MODE                     (0x00000000U)
00270 #define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD
00271 #define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND
00272 #define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
00278   * @{
00279   */
00280
00281 #define  SMBUS_NO_STARTSTOP                     (0x00000000U)
00282 #define  SMBUS_GENERATE_STOP                    I2C_CR2_STOP
00283 #define  SMBUS_GENERATE_START_READ              (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
00284 #define  SMBUS_GENERATE_START_WRITE             I2C_CR2_START
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
00290   * @{
00291   */
00292
00293 /* List of XferOptions in usage of :
00294  * 1- Restart condition when direction change
00295  * 2- No Restart condition in other use cases
00296  */
00297 #define  SMBUS_FIRST_FRAME                      SMBUS_SOFTEND_MODE
00298 #define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
00299 #define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE
00300 #define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
00301 #define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
00302 #define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
00303
00304 /* List of XferOptions in usage of :
00305  * 1- Restart condition in all use cases (direction change or not)
00306  */
00307 #define  SMBUS_OTHER_FRAME_NO_PEC               (0x000000AAU)
00308 #define  SMBUS_OTHER_FRAME_WITH_PEC             (0x0000AA00U)
00309 #define  SMBUS_OTHER_AND_LAST_FRAME_NO_PEC      (0x00AA0000U)
00310 #define  SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC    (0xAA000000U)
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
00316   * @brief SMBUS Interrupt definition
00317   *        Elements values convention: 0xXXXXXXXX
00318   *           - XXXXXXXX  : Interrupt control mask
00319   * @{
00320   */
00321 #define SMBUS_IT_ERRI                           I2C_CR1_ERRIE
00322 #define SMBUS_IT_TCI                            I2C_CR1_TCIE
00323 #define SMBUS_IT_STOPI                          I2C_CR1_STOPIE
00324 #define SMBUS_IT_NACKI                          I2C_CR1_NACKIE
00325 #define SMBUS_IT_ADDRI                          I2C_CR1_ADDRIE
00326 #define SMBUS_IT_RXI                            I2C_CR1_RXIE
00327 #define SMBUS_IT_TXI                            I2C_CR1_TXIE
00328 #define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
00329 #define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
00330 #define SMBUS_IT_ALERT                          (SMBUS_IT_ERRI)
00331 #define SMBUS_IT_ADDR                           (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition
00337   * @brief Flag definition
00338   *        Elements values convention: 0xXXXXYYYY
00339   *           - XXXXXXXX  : Flag mask
00340   * @{
00341   */
00342
00343 #define  SMBUS_FLAG_TXE                         I2C_ISR_TXE
00344 #define  SMBUS_FLAG_TXIS                        I2C_ISR_TXIS
00345 #define  SMBUS_FLAG_RXNE                        I2C_ISR_RXNE
00346 #define  SMBUS_FLAG_ADDR                        I2C_ISR_ADDR
00347 #define  SMBUS_FLAG_AF                          I2C_ISR_NACKF
00348 #define  SMBUS_FLAG_STOPF                       I2C_ISR_STOPF
00349 #define  SMBUS_FLAG_TC                          I2C_ISR_TC
00350 #define  SMBUS_FLAG_TCR                         I2C_ISR_TCR
00351 #define  SMBUS_FLAG_BERR                        I2C_ISR_BERR
00352 #define  SMBUS_FLAG_ARLO                        I2C_ISR_ARLO
00353 #define  SMBUS_FLAG_OVR                         I2C_ISR_OVR
00354 #define  SMBUS_FLAG_PECERR                      I2C_ISR_PECERR
00355 #define  SMBUS_FLAG_TIMEOUT                     I2C_ISR_TIMEOUT
00356 #define  SMBUS_FLAG_ALERT                       I2C_ISR_ALERT
00357 #define  SMBUS_FLAG_BUSY                        I2C_ISR_BUSY
00358 #define  SMBUS_FLAG_DIR                         I2C_ISR_DIR
00359 /**
00360   * @}
00361   */
00362
00363 /**
00364   * @}
00365   */
00366
00367 /* Exported macros ------------------------------------------------------------*/
00368 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
00369   * @{
00370   */
00371
00372 /** @brief  Reset SMBUS handle state.
00373   * @param  __HANDLE__ specifies the SMBUS Handle.
00374   * @retval None
00375   */
00376 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
00377
00378 /** @brief  Enable the specified SMBUS interrupts.
00379   * @param  __HANDLE__ specifies the SMBUS Handle.
00380   * @param  __INTERRUPT__ specifies the interrupt source to enable.
00381   *        This parameter can be one of the following values:
00382   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
00383   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
00384   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
00385   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
00386   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
00387   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
00388   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
00389   *
00390   * @retval None
00391   */
00392 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
00393
00394 /** @brief  Disable the specified SMBUS interrupts.
00395   * @param  __HANDLE__ specifies the SMBUS Handle.
00396   * @param  __INTERRUPT__ specifies the interrupt source to disable.
00397   *        This parameter can be one of the following values:
00398   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
00399   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
00400   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
00401   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
00402   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
00403   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
00404   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
00405   *
00406   * @retval None
00407   */
00408 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
00409
00410 /** @brief  Check whether the specified SMBUS interrupt source is enabled or not.
00411   * @param  __HANDLE__ specifies the SMBUS Handle.
00412   * @param  __INTERRUPT__ specifies the SMBUS interrupt source to check.
00413   *          This parameter can be one of the following values:
00414   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
00415   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
00416   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
00417   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
00418   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
00419   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
00420   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
00421   *
00422   * @retval The new state of __IT__ (TRUE or FALSE).
00423   */
00424 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00425
00426 /** @brief  Check whether the specified SMBUS flag is set or not.
00427   * @param  __HANDLE__ specifies the SMBUS Handle.
00428   * @param  __FLAG__ specifies the flag to check.
00429   *        This parameter can be one of the following values:
00430   *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
00431   *            @arg @ref SMBUS_FLAG_TXIS    Transmit interrupt status
00432   *            @arg @ref SMBUS_FLAG_RXNE    Receive data register not empty
00433   *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
00434   *            @arg @ref SMBUS_FLAG_AF      NACK received flag
00435   *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
00436   *            @arg @ref SMBUS_FLAG_TC      Transfer complete (master mode)
00437   *            @arg @ref SMBUS_FLAG_TCR     Transfer complete reload
00438   *            @arg @ref SMBUS_FLAG_BERR    Bus error
00439   *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
00440   *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
00441   *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
00442   *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
00443   *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
00444   *            @arg @ref SMBUS_FLAG_BUSY    Bus busy
00445   *            @arg @ref SMBUS_FLAG_DIR     Transfer direction (slave mode)
00446   *
00447   * @retval The new state of __FLAG__ (TRUE or FALSE).
00448   */
00449 #define SMBUS_FLAG_MASK  (0x0001FFFFU)
00450 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
00451
00452 /** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
00453   * @param  __HANDLE__ specifies the SMBUS Handle.
00454   * @param  __FLAG__ specifies the flag to clear.
00455   *          This parameter can be any combination of the following values:
00456   *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
00457   *            @arg @ref SMBUS_FLAG_AF      NACK received flag
00458   *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
00459   *            @arg @ref SMBUS_FLAG_BERR    Bus error
00460   *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
00461   *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
00462   *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
00463   *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
00464   *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
00465   *
00466   * @retval None
00467   */
00468 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00469
00470 /** @brief  Enable the specified SMBUS peripheral.
00471   * @param  __HANDLE__ specifies the SMBUS Handle.
00472   * @retval None
00473   */
00474 #define __HAL_SMBUS_ENABLE(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00475
00476 /** @brief  Disable the specified SMBUS peripheral.
00477   * @param  __HANDLE__ specifies the SMBUS Handle.
00478   * @retval None
00479   */
00480 #define __HAL_SMBUS_DISABLE(__HANDLE__)                 (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00481
00482 /** @brief  Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
00483   * @param  __HANDLE__ specifies the SMBUS Handle.
00484   * @retval None
00485   */
00486 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)           (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
00487
00488 /**
00489   * @}
00490   */
00491
00492
00493 /* Private constants ---------------------------------------------------------*/
00494
00495 /* Private macros ------------------------------------------------------------*/
00496 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros
00497   * @{
00498   */
00499
00500 #define IS_SMBUS_ANALOG_FILTER(FILTER)                  (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
00501                                                           ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
00502
00503 #define IS_SMBUS_DIGITAL_FILTER(FILTER)                 ((FILTER) <= 0x0000000FU)
00504
00505 #define IS_SMBUS_ADDRESSING_MODE(MODE)                  (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
00506                                                           ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
00507
00508 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS)                  (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
00509                                                           ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
00510
00511 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)                (((MASK) == SMBUS_OA2_NOMASK)    || \
00512                                                          ((MASK) == SMBUS_OA2_MASK01)    || \
00513                                                          ((MASK) == SMBUS_OA2_MASK02)    || \
00514                                                          ((MASK) == SMBUS_OA2_MASK03)    || \
00515                                                          ((MASK) == SMBUS_OA2_MASK04)    || \
00516                                                          ((MASK) == SMBUS_OA2_MASK05)    || \
00517                                                          ((MASK) == SMBUS_OA2_MASK06)    || \
00518                                                          ((MASK) == SMBUS_OA2_MASK07))
00519
00520 #define IS_SMBUS_GENERAL_CALL(CALL)                     (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
00521                                                          ((CALL) == SMBUS_GENERALCALL_ENABLE))
00522
00523 #define IS_SMBUS_NO_STRETCH(STRETCH)                    (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
00524                                                          ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
00525
00526 #define IS_SMBUS_PEC(PEC)                               (((PEC) == SMBUS_PEC_DISABLE) || \
00527                                                           ((PEC) == SMBUS_PEC_ENABLE))
00528
00529 #define IS_SMBUS_PERIPHERAL_MODE(MODE)                  (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)    || \
00530                                                           ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
00531                                                           ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
00532
00533 #define IS_SMBUS_TRANSFER_MODE(MODE)                    (((MODE) == SMBUS_RELOAD_MODE)                           || \
00534                                                           ((MODE) == SMBUS_AUTOEND_MODE)                         || \
00535                                                           ((MODE) == SMBUS_SOFTEND_MODE)                         || \
00536                                                           ((MODE) == SMBUS_SENDPEC_MODE)                         || \
00537                                                           ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
00538                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
00539                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
00540                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
00541
00542
00543 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \
00544                                                           ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
00545                                                           ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
00546                                                           ((REQUEST) == SMBUS_NO_STARTSTOP))
00547
00548
00549 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == SMBUS_FIRST_FRAME)                        || \
00550                                                           ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
00551                                                           ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
00552                                                           ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
00553                                                           ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
00554                                                           ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)               || \
00555                                                           IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
00556
00557 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)                || \
00558                                                           ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)       || \
00559                                                           ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)              || \
00560                                                           ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
00561
00562 #define SMBUS_RESET_CR1(__HANDLE__)                       ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
00563 #define SMBUS_RESET_CR2(__HANDLE__)                       ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
00564
00565 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
00566                                                                   (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
00567
00568 #define SMBUS_GET_ADDR_MATCH(__HANDLE__)                  (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
00569 #define SMBUS_GET_DIR(__HANDLE__)                         (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
00570 #define SMBUS_GET_STOP_MODE(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
00571 #define SMBUS_GET_PEC_MODE(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
00572 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__)                ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
00573
00574 #define SMBUS_GET_ISR_REG(__HANDLE__)                   ((__HANDLE__)->Instance->ISR)
00575 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
00576
00577 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                         ((ADDRESS1) <= 0x000003FFU)
00578 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                         ((ADDRESS2) <= (uint16_t)0x00FFU)
00579
00580 /**
00581   * @}
00582   */
00583
00584 /* Exported functions --------------------------------------------------------*/
00585 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
00586   * @{
00587   */
00588
00589 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
00590  * @{
00591  */
00592
00593 /* Initialization and de-initialization functions  **********************************/
00594 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
00595 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
00596 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
00597 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
00598 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
00599 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
00600
00601 /**
00602   * @}
00603   */
00604
00605 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
00606  * @{
00607  */
00608
00609 /* IO operation functions  *****************************************************/
00610 /** @addtogroup Blocking_mode_Polling Blocking mode Polling
00611  * @{
00612  */
00613 /******* Blocking mode: Polling */
00614 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
00615 /**
00616   * @}
00617   */
00618
00619 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
00620  * @{
00621  */
00622 /******* Non-Blocking mode: Interrupt */
00623 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00624 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00625 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
00626 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00627 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00628
00629 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
00630 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
00631 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
00632 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
00633 /**
00634   * @}
00635   */
00636
00637 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00638  * @{
00639  */
00640 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
00641 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
00642 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
00643 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00644 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00645 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00646 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00647 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
00648 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00649 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
00650
00651 /**
00652   * @}
00653   */
00654
00655 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
00656  *  @{
00657  */
00658
00659 /* Peripheral State and Errors functions  **************************************************/
00660 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
00661 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
00662
00663 /**
00664   * @}
00665   */
00666
00667 /**
00668   * @}
00669   */
00670
00671 /* Private Functions ---------------------------------------------------------*/
00672 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions
00673   * @{
00674   */
00675 /* Private functions are defined in stm32f3xx_hal_smbus.c file */
00676 /**
00677   * @}
00678   */
00679
00680 /**
00681   * @}
00682   */
00683
00684 /**
00685   * @}
00686   */
00687
00688 /**
00689   * @}
00690   */
00691
00692 #ifdef __cplusplus
00693 }
00694 #endif
00695
00696
00697 #endif /* __STM32F3xx_HAL_SMBUS_H */
00698
00699 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_spi.c Source File

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stm32f3xx_hal_spi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_spi.c
00004   * @author  MCD Application Team
00005   * @brief   SPI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018       The SPI HAL driver can be used as follows:
00019
00020       (#) Declare a SPI_HandleTypeDef handle structure, for example:
00021           SPI_HandleTypeDef  hspi;
00022
00023       (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
00024           (##) Enable the SPIx interface clock
00025           (##) SPI pins configuration
00026               (+++) Enable the clock for the SPI GPIOs
00027               (+++) Configure these SPI pins as alternate function push-pull
00028           (##) NVIC configuration if you need to use interrupt process
00029               (+++) Configure the SPIx interrupt priority
00030               (+++) Enable the NVIC SPI IRQ handle
00031           (##) DMA Configuration if you need to use DMA process
00032               (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
00033               (+++) Enable the DMAx clock
00034               (+++) Configure the DMA handle parameters
00035               (+++) Configure the DMA Tx or Rx Stream/Channel
00036               (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
00037               (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
00038
00039       (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
00040           management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
00041
00042       (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
00043           (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00044               by calling the customized HAL_SPI_MspInit() API.
00045      [..]
00046        Circular mode restriction:
00047       (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
00048           (##) Master 2Lines RxOnly
00049           (##) Master 1Line Rx
00050       (#) The CRC feature is not managed when the DMA circular mode is enabled
00051       (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
00052           the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
00053      [..]
00054        Master Receive mode restriction:
00055       (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
00056           bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
00057           does not initiate a new transfer the following procedure has to be respected:
00058           (##) HAL_SPI_DeInit()
00059           (##) HAL_SPI_Init()
00060      [..]
00061        The HAL drivers do not allow reaching all supported SPI frequencies in the different SPI
00062        modes. Refer to the source code (stm32xxxx_hal_spi.c header) to get a summary of the
00063        maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on
00064        the APBx peripheral clock frequency (fPCLK) used by the SPI instance.
00065
00066
00067   @endverbatim
00068
00069   Additional table :
00070
00071        DataSize = SPI_DATASIZE_8BIT:
00072        +----------------------------------------------------------------------------------------------+
00073        |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
00074        | Process | Tranfert mode  |---------------------|----------------------|----------------------|
00075        |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
00076        |==============================================================================================|
00077        |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
00078        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00079        |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |
00080        |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
00081        |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
00082        |=========|================|==========|==========|===========|==========|===========|==========|
00083        |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |
00084        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00085        |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |
00086        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00087        |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |
00088        |=========|================|==========|==========|===========|==========|===========|==========|
00089        |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |
00090        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00091        |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |
00092        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00093        |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |
00094        +----------------------------------------------------------------------------------------------+
00095
00096        DataSize = SPI_DATASIZE_16BIT:
00097        +----------------------------------------------------------------------------------------------+
00098        |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
00099        | Process | Tranfert mode  |---------------------|----------------------|----------------------|
00100        |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
00101        |==============================================================================================|
00102        |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
00103        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00104        |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |
00105        |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
00106        |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
00107        |=========|================|==========|==========|===========|==========|===========|==========|
00108        |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |
00109        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00110        |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |
00111        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00112        |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |
00113        |=========|================|==========|==========|===========|==========|===========|==========|
00114        |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |
00115        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00116        |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |
00117        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00118        |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |
00119        +----------------------------------------------------------------------------------------------+
00120        @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
00121              SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
00122        @note
00123             (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
00124             (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
00125             (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
00126
00127   ******************************************************************************
00128   * @attention
00129   *
00130   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00131   *
00132   * Redistribution and use in source and binary forms, with or without modification,
00133   * are permitted provided that the following conditions are met:
00134   *   1. Redistributions of source code must retain the above copyright notice,
00135   *      this list of conditions and the following disclaimer.
00136   *   2. Redistributions in binary form must reproduce the above copyright notice,
00137   *      this list of conditions and the following disclaimer in the documentation
00138   *      and/or other materials provided with the distribution.
00139   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00140   *      may be used to endorse or promote products derived from this software
00141   *      without specific prior written permission.
00142   *
00143   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00144   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00145   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00146   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00147   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00148   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00149   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00150   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00151   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00152   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00153   *
00154   ******************************************************************************
00155   */
00156
00157 /* Includes ------------------------------------------------------------------*/
00158 #include "stm32f3xx_hal.h"
00159
00160 /** @addtogroup STM32F3xx_HAL_Driver
00161   * @{
00162   */
00163
00164 /** @defgroup SPI SPI
00165   * @brief SPI HAL module driver
00166   * @{
00167   */
00168 #ifdef HAL_SPI_MODULE_ENABLED
00169
00170 /* Private typedef -----------------------------------------------------------*/
00171 /* Private defines -----------------------------------------------------------*/
00172 /** @defgroup SPI_Private_Constants SPI Private Constants
00173   * @{
00174   */
00175 #define SPI_DEFAULT_TIMEOUT 100U
00176 /**
00177   * @}
00178   */
00179
00180 /* Private macros ------------------------------------------------------------*/
00181 /* Private variables ---------------------------------------------------------*/
00182 /* Private function prototypes -----------------------------------------------*/
00183 /** @defgroup SPI_Private_Functions SPI Private Functions
00184   * @{
00185   */
00186 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00187 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00188 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00189 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
00190 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
00191 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00192 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
00193 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00194 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00195 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00196 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
00197                                                        uint32_t Timeout, uint32_t Tickstart);
00198 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
00199                                                        uint32_t Timeout, uint32_t Tickstart);
00200 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00201 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00202 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00203 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00204 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00205 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00206 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00207 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00208 #if (USE_SPI_CRC != 0U)
00209 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
00210 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
00211 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
00212 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
00213 #endif /* USE_SPI_CRC */
00214 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
00215 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
00216 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
00217 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
00218 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
00219 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
00220 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
00221 /**
00222   * @}
00223   */
00224
00225 /* Exported functions --------------------------------------------------------*/
00226 /** @defgroup SPI_Exported_Functions SPI Exported Functions
00227   * @{
00228   */
00229
00230 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
00231  *  @brief    Initialization and Configuration functions
00232  *
00233 @verbatim
00234  ===============================================================================
00235               ##### Initialization and de-initialization functions #####
00236  ===============================================================================
00237     [..]  This subsection provides a set of functions allowing to initialize and
00238           de-initialize the SPIx peripheral:
00239
00240       (+) User must implement HAL_SPI_MspInit() function in which he configures
00241           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00242
00243       (+) Call the function HAL_SPI_Init() to configure the selected device with
00244           the selected configuration:
00245         (++) Mode
00246         (++) Direction
00247         (++) Data Size
00248         (++) Clock Polarity and Phase
00249         (++) NSS Management
00250         (++) BaudRate Prescaler
00251         (++) FirstBit
00252         (++) TIMode
00253         (++) CRC Calculation
00254         (++) CRC Polynomial if CRC enabled
00255         (++) CRC Length, used only with Data8 and Data16
00256         (++) FIFO reception threshold
00257
00258       (+) Call the function HAL_SPI_DeInit() to restore the default configuration
00259           of the selected SPIx peripheral.
00260
00261 @endverbatim
00262   * @{
00263   */
00264
00265 /**
00266   * @brief  Initialize the SPI according to the specified parameters
00267   *         in the SPI_InitTypeDef and initialize the associated handle.
00268   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00269   *               the configuration information for SPI module.
00270   * @retval HAL status
00271   */
00272 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
00273 {
00274   uint32_t frxth;
00275
00276   /* Check the SPI handle allocation */
00277   if (hspi == NULL)
00278   {
00279     return HAL_ERROR;
00280   }
00281
00282   /* Check the parameters */
00283   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00284   assert_param(IS_SPI_MODE(hspi->Init.Mode));
00285   assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
00286   assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
00287   assert_param(IS_SPI_NSS(hspi->Init.NSS));
00288   assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
00289   assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
00290   assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
00291   assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
00292   if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
00293   {
00294     assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
00295     assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
00296   }
00297 #if (USE_SPI_CRC != 0U)
00298   assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
00299   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00300   {
00301     assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
00302     assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
00303   }
00304 #else
00305   hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
00306 #endif /* USE_SPI_CRC */
00307
00308   if (hspi->State == HAL_SPI_STATE_RESET)
00309   {
00310     /* Allocate lock resource and initialize it */
00311     hspi->Lock = HAL_UNLOCKED;
00312
00313     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00314     HAL_SPI_MspInit(hspi);
00315   }
00316
00317   hspi->State = HAL_SPI_STATE_BUSY;
00318
00319   /* Disable the selected SPI peripheral */
00320   __HAL_SPI_DISABLE(hspi);
00321
00322   /* Align by default the rs fifo threshold on the data size */
00323   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00324   {
00325     frxth = SPI_RXFIFO_THRESHOLD_HF;
00326   }
00327   else
00328   {
00329     frxth = SPI_RXFIFO_THRESHOLD_QF;
00330   }
00331
00332   /* CRC calculation is valid only for 16Bit and 8 Bit */
00333   if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
00334   {
00335     /* CRC must be disabled */
00336     hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
00337   }
00338
00339   /* Align the CRC Length on the data size */
00340   if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
00341   {
00342     /* CRC Length aligned on the data size : value set by default */
00343     if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00344     {
00345       hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
00346     }
00347     else
00348     {
00349       hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
00350     }
00351   }
00352
00353   /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
00354   /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
00355   Communication speed, First bit and CRC calculation state */
00356   WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
00357                                   hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
00358                                   hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation));
00359 #if (USE_SPI_CRC != 0U)
00360   /* Configure : CRC Length */
00361   if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
00362   {
00363     hspi->Instance->CR1 |= SPI_CR1_CRCL;
00364   }
00365 #endif /* USE_SPI_CRC */
00366
00367   /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo Threshold */
00368   WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
00369                                   hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
00370
00371 #if (USE_SPI_CRC != 0U)
00372   /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
00373   /* Configure : CRC Polynomial */
00374   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00375   {
00376     WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
00377   }
00378 #endif /* USE_SPI_CRC */
00379
00380 #if defined(SPI_I2SCFGR_I2SMOD)
00381   /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
00382   CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
00383 #endif /* SPI_I2SCFGR_I2SMOD */
00384
00385   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00386   hspi->State     = HAL_SPI_STATE_READY;
00387
00388   return HAL_OK;
00389 }
00390
00391 /**
00392   * @brief  De-Initialize the SPI peripheral.
00393   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00394   *               the configuration information for SPI module.
00395   * @retval HAL status
00396   */
00397 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
00398 {
00399   /* Check the SPI handle allocation */
00400   if (hspi == NULL)
00401   {
00402     return HAL_ERROR;
00403   }
00404
00405   /* Check SPI Instance parameter */
00406   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00407
00408   hspi->State = HAL_SPI_STATE_BUSY;
00409
00410   /* Disable the SPI Peripheral Clock */
00411   __HAL_SPI_DISABLE(hspi);
00412
00413   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00414   HAL_SPI_MspDeInit(hspi);
00415
00416   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00417   hspi->State = HAL_SPI_STATE_RESET;
00418
00419   /* Release Lock */
00420   __HAL_UNLOCK(hspi);
00421
00422   return HAL_OK;
00423 }
00424
00425 /**
00426   * @brief  Initialize the SPI MSP.
00427   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00428   *               the configuration information for SPI module.
00429   * @retval None
00430   */
00431 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
00432 {
00433   /* Prevent unused argument(s) compilation warning */
00434   UNUSED(hspi);
00435
00436   /* NOTE : This function should not be modified, when the callback is needed,
00437             the HAL_SPI_MspInit should be implemented in the user file
00438    */
00439 }
00440
00441 /**
00442   * @brief  De-Initialize the SPI MSP.
00443   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00444   *               the configuration information for SPI module.
00445   * @retval None
00446   */
00447 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
00448 {
00449   /* Prevent unused argument(s) compilation warning */
00450   UNUSED(hspi);
00451
00452   /* NOTE : This function should not be modified, when the callback is needed,
00453             the HAL_SPI_MspDeInit should be implemented in the user file
00454    */
00455 }
00456
00457 /**
00458   * @}
00459   */
00460
00461 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
00462  *  @brief   Data transfers functions
00463  *
00464 @verbatim
00465   ==============================================================================
00466                       ##### IO operation functions #####
00467  ===============================================================================
00468  [..]
00469     This subsection provides a set of functions allowing to manage the SPI
00470     data transfers.
00471
00472     [..] The SPI supports master and slave mode :
00473
00474     (#) There are two modes of transfer:
00475        (++) Blocking mode: The communication is performed in polling mode.
00476             The HAL status of all data processing is returned by the same function
00477             after finishing transfer.
00478        (++) No-Blocking mode: The communication is performed using Interrupts
00479             or DMA, These APIs return the HAL status.
00480             The end of the data processing will be indicated through the
00481             dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
00482             using DMA mode.
00483             The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
00484             will be executed respectively at the end of the transmit or Receive process
00485             The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
00486
00487     (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
00488         exist for 1Line (simplex) and 2Lines (full duplex) modes.
00489
00490 @endverbatim
00491   * @{
00492   */
00493
00494 /**
00495   * @brief  Transmit an amount of data in blocking mode.
00496   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00497   *               the configuration information for SPI module.
00498   * @param  pData pointer to data buffer
00499   * @param  Size amount of data to be sent
00500   * @param  Timeout Timeout duration
00501   * @retval HAL status
00502   */
00503 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00504 {
00505   uint32_t tickstart = 0U;
00506   HAL_StatusTypeDef errorcode = HAL_OK;
00507
00508
00509   /* Check Direction parameter */
00510   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
00511
00512   /* Process Locked */
00513   __HAL_LOCK(hspi);
00514
00515   /* Init tickstart for timeout management*/
00516   tickstart = HAL_GetTick();
00517
00518   if (hspi->State != HAL_SPI_STATE_READY)
00519   {
00520     errorcode = HAL_BUSY;
00521     goto error;
00522   }
00523
00524   if ((pData == NULL) || (Size == 0U))
00525   {
00526     errorcode = HAL_ERROR;
00527     goto error;
00528   }
00529
00530   /* Set the transaction information */
00531   hspi->State       = HAL_SPI_STATE_BUSY_TX;
00532   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00533   hspi->pTxBuffPtr  = (uint8_t *)pData;
00534   hspi->TxXferSize  = Size;
00535   hspi->TxXferCount = Size;
00536
00537   /*Init field not used in handle to zero */
00538   hspi->pRxBuffPtr  = (uint8_t *)NULL;
00539   hspi->RxXferSize  = 0U;
00540   hspi->RxXferCount = 0U;
00541   hspi->TxISR       = NULL;
00542   hspi->RxISR       = NULL;
00543
00544   /* Configure communication direction : 1Line */
00545   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
00546   {
00547     SPI_1LINE_TX(hspi);
00548   }
00549
00550 #if (USE_SPI_CRC != 0U)
00551   /* Reset CRC Calculation */
00552   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00553   {
00554     SPI_RESET_CRC(hspi);
00555   }
00556 #endif /* USE_SPI_CRC */
00557
00558   /* Check if the SPI is already enabled */
00559   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00560   {
00561     /* Enable SPI peripheral */
00562     __HAL_SPI_ENABLE(hspi);
00563   }
00564
00565   /* Transmit data in 16 Bit mode */
00566   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00567   {
00568     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
00569     {
00570       hspi->Instance->DR = *((uint16_t *)pData);
00571       pData += sizeof(uint16_t);
00572       hspi->TxXferCount--;
00573     }
00574     /* Transmit data in 16 Bit mode */
00575     while (hspi->TxXferCount > 0U)
00576     {
00577       /* Wait until TXE flag is set to send data */
00578       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
00579       {
00580         hspi->Instance->DR = *((uint16_t *)pData);
00581         pData += sizeof(uint16_t);
00582         hspi->TxXferCount--;
00583       }
00584       else
00585       {
00586         /* Timeout management */
00587         if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
00588         {
00589           errorcode = HAL_TIMEOUT;
00590           goto error;
00591         }
00592       }
00593     }
00594   }
00595   /* Transmit data in 8 Bit mode */
00596   else
00597   {
00598     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
00599     {
00600       if (hspi->TxXferCount > 1U)
00601       {
00602         /* write on the data register in packing mode */
00603         hspi->Instance->DR = *((uint16_t *)pData);
00604         pData += sizeof(uint16_t);
00605         hspi->TxXferCount -= 2U;
00606       }
00607       else
00608       {
00609         *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
00610         hspi->TxXferCount--;
00611       }
00612     }
00613     while (hspi->TxXferCount > 0U)
00614     {
00615       /* Wait until TXE flag is set to send data */
00616       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
00617       {
00618         if (hspi->TxXferCount > 1U)
00619         {
00620           /* write on the data register in packing mode */
00621           hspi->Instance->DR = *((uint16_t *)pData);
00622           pData += sizeof(uint16_t);
00623           hspi->TxXferCount -= 2U;
00624         }
00625         else
00626         {
00627           *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
00628           hspi->TxXferCount--;
00629         }
00630       }
00631       else
00632       {
00633         /* Timeout management */
00634         if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
00635         {
00636           errorcode = HAL_TIMEOUT;
00637           goto error;
00638         }
00639       }
00640     }
00641   }
00642 #if (USE_SPI_CRC != 0U)
00643   /* Enable CRC Transmission */
00644   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00645   {
00646     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
00647   }
00648 #endif /* USE_SPI_CRC */
00649
00650   /* Check the end of the transaction */
00651   if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
00652   {
00653     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
00654   }
00655
00656   /* Clear overrun flag in 2 Lines communication mode because received is not read */
00657   if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
00658   {
00659     __HAL_SPI_CLEAR_OVRFLAG(hspi);
00660   }
00661
00662   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00663   {
00664     errorcode = HAL_ERROR;
00665   }
00666
00667 error:
00668   hspi->State = HAL_SPI_STATE_READY;
00669   /* Process Unlocked */
00670   __HAL_UNLOCK(hspi);
00671   return errorcode;
00672 }
00673
00674 /**
00675   * @brief  Receive an amount of data in blocking mode.
00676   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00677   *               the configuration information for SPI module.
00678   * @param  pData pointer to data buffer
00679   * @param  Size amount of data to be received
00680   * @param  Timeout Timeout duration
00681   * @retval HAL status
00682   */
00683 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00684 {
00685 #if (USE_SPI_CRC != 0U)
00686   __IO uint16_t tmpreg = 0U;
00687 #endif /* USE_SPI_CRC */
00688   uint32_t tickstart = 0U;
00689   HAL_StatusTypeDef errorcode = HAL_OK;
00690
00691
00692   if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
00693   {
00694     hspi->State = HAL_SPI_STATE_BUSY_RX;
00695     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
00696     return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
00697   }
00698
00699   /* Process Locked */
00700   __HAL_LOCK(hspi);
00701
00702   /* Init tickstart for timeout management*/
00703   tickstart = HAL_GetTick();
00704
00705   if (hspi->State != HAL_SPI_STATE_READY)
00706   {
00707     errorcode = HAL_BUSY;
00708     goto error;
00709   }
00710
00711   if ((pData == NULL) || (Size == 0U))
00712   {
00713     errorcode = HAL_ERROR;
00714     goto error;
00715   }
00716
00717   /* Set the transaction information */
00718   hspi->State       = HAL_SPI_STATE_BUSY_RX;
00719   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00720   hspi->pRxBuffPtr  = (uint8_t *)pData;
00721   hspi->RxXferSize  = Size;
00722   hspi->RxXferCount = Size;
00723
00724   /*Init field not used in handle to zero */
00725   hspi->pTxBuffPtr  = (uint8_t *)NULL;
00726   hspi->TxXferSize  = 0U;
00727   hspi->TxXferCount = 0U;
00728   hspi->RxISR       = NULL;
00729   hspi->TxISR       = NULL;
00730
00731 #if (USE_SPI_CRC != 0U)
00732   /* Reset CRC Calculation */
00733   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00734   {
00735     SPI_RESET_CRC(hspi);
00736     /* this is done to handle the CRCNEXT before the latest data */
00737     hspi->RxXferCount--;
00738   }
00739 #endif /* USE_SPI_CRC */
00740
00741   /* Set the Rx FiFo threshold */
00742   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00743   {
00744     /* set fiforxthresold according the reception data length: 16bit */
00745     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
00746   }
00747   else
00748   {
00749     /* set fiforxthresold according the reception data length: 8bit */
00750     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
00751   }
00752
00753   /* Configure communication direction: 1Line */
00754   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
00755   {
00756     SPI_1LINE_RX(hspi);
00757   }
00758
00759   /* Check if the SPI is already enabled */
00760   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00761   {
00762     /* Enable SPI peripheral */
00763     __HAL_SPI_ENABLE(hspi);
00764   }
00765
00766   /* Receive data in 8 Bit mode */
00767   if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
00768   {
00769     /* Transfer loop */
00770     while (hspi->RxXferCount > 0U)
00771     {
00772       /* Check the RXNE flag */
00773       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
00774       {
00775         /* read the received data */
00776         (* (uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
00777         pData += sizeof(uint8_t);
00778         hspi->RxXferCount--;
00779       }
00780       else
00781       {
00782         /* Timeout management */
00783         if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
00784         {
00785           errorcode = HAL_TIMEOUT;
00786           goto error;
00787         }
00788       }
00789     }
00790   }
00791   else
00792   {
00793     /* Transfer loop */
00794     while (hspi->RxXferCount > 0U)
00795     {
00796       /* Check the RXNE flag */
00797       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
00798       {
00799         *((uint16_t *)pData) = hspi->Instance->DR;
00800         pData += sizeof(uint16_t);
00801         hspi->RxXferCount--;
00802       }
00803       else
00804       {
00805         /* Timeout management */
00806         if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
00807         {
00808           errorcode = HAL_TIMEOUT;
00809           goto error;
00810         }
00811       }
00812     }
00813   }
00814
00815 #if (USE_SPI_CRC != 0U)
00816   /* Handle the CRC Transmission */
00817   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00818   {
00819     /* freeze the CRC before the latest data */
00820     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
00821
00822     /* Read the latest data */
00823     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
00824     {
00825       /* the latest data has not been received */
00826       errorcode = HAL_TIMEOUT;
00827       goto error;
00828     }
00829
00830     /* Receive last data in 16 Bit mode */
00831     if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00832     {
00833       *((uint16_t *)pData) = hspi->Instance->DR;
00834     }
00835     /* Receive last data in 8 Bit mode */
00836     else
00837     {
00838       (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
00839     }
00840
00841     /* Wait the CRC data */
00842     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
00843     {
00844       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
00845       errorcode = HAL_TIMEOUT;
00846       goto error;
00847     }
00848
00849     /* Read CRC to Flush DR and RXNE flag */
00850     if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
00851     {
00852       tmpreg = hspi->Instance->DR;
00853       /* To avoid GCC warning */
00854       UNUSED(tmpreg);
00855     }
00856     else
00857     {
00858       tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
00859       /* To avoid GCC warning */
00860       UNUSED(tmpreg);
00861
00862       if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
00863       {
00864         if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)
00865         {
00866           /* Error on the CRC reception */
00867           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
00868           errorcode = HAL_TIMEOUT;
00869           goto error;
00870         }
00871         tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
00872         /* To avoid GCC warning */
00873         UNUSED(tmpreg);
00874       }
00875     }
00876   }
00877 #endif /* USE_SPI_CRC */
00878
00879   /* Check the end of the transaction */
00880   if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
00881   {
00882     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
00883   }
00884
00885 #if (USE_SPI_CRC != 0U)
00886   /* Check if CRC error occurred */
00887   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
00888   {
00889     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
00890     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
00891   }
00892 #endif /* USE_SPI_CRC */
00893
00894   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00895   {
00896     errorcode = HAL_ERROR;
00897   }
00898
00899 error :
00900   hspi->State = HAL_SPI_STATE_READY;
00901   __HAL_UNLOCK(hspi);
00902   return errorcode;
00903 }
00904
00905 /**
00906   * @brief  Transmit and Receive an amount of data in blocking mode.
00907   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00908   *               the configuration information for SPI module.
00909   * @param  pTxData pointer to transmission data buffer
00910   * @param  pRxData pointer to reception data buffer
00911   * @param  Size amount of data to be sent and received
00912   * @param  Timeout Timeout duration
00913   * @retval HAL status
00914   */
00915 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
00916                                           uint32_t Timeout)
00917 {
00918   uint32_t tmp = 0U, tmp1 = 0U;
00919 #if (USE_SPI_CRC != 0U)
00920   __IO uint16_t tmpreg = 0U;
00921 #endif /* USE_SPI_CRC */
00922   uint32_t tickstart = 0U;
00923   /* Variable used to alternate Rx and Tx during transfer */
00924   uint32_t txallowed = 1U;
00925   HAL_StatusTypeDef errorcode = HAL_OK;
00926
00927
00928   /* Check Direction parameter */
00929   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
00930
00931   /* Process Locked */
00932   __HAL_LOCK(hspi);
00933
00934   /* Init tickstart for timeout management*/
00935   tickstart = HAL_GetTick();
00936
00937   tmp  = hspi->State;
00938   tmp1 = hspi->Init.Mode;
00939
00940   if (!((tmp == HAL_SPI_STATE_READY) || \
00941         ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
00942   {
00943     errorcode = HAL_BUSY;
00944     goto error;
00945   }
00946
00947   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00948   {
00949     errorcode = HAL_ERROR;
00950     goto error;
00951   }
00952
00953   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
00954   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
00955   {
00956     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
00957   }
00958
00959   /* Set the transaction information */
00960   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00961   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
00962   hspi->RxXferCount = Size;
00963   hspi->RxXferSize  = Size;
00964   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
00965   hspi->TxXferCount = Size;
00966   hspi->TxXferSize  = Size;
00967
00968   /*Init field not used in handle to zero */
00969   hspi->RxISR       = NULL;
00970   hspi->TxISR       = NULL;
00971
00972 #if (USE_SPI_CRC != 0U)
00973   /* Reset CRC Calculation */
00974   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00975   {
00976     SPI_RESET_CRC(hspi);
00977   }
00978 #endif /* USE_SPI_CRC */
00979
00980   /* Set the Rx Fifo threshold */
00981   if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U))
00982   {
00983     /* set fiforxthreshold according the reception data length: 16bit */
00984     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
00985   }
00986   else
00987   {
00988     /* set fiforxthreshold according the reception data length: 8bit */
00989     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
00990   }
00991
00992   /* Check if the SPI is already enabled */
00993   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00994   {
00995     /* Enable SPI peripheral */
00996     __HAL_SPI_ENABLE(hspi);
00997   }
00998
00999   /* Transmit and Receive data in 16 Bit mode */
01000   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01001   {
01002     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
01003     {
01004       hspi->Instance->DR = *((uint16_t *)pTxData);
01005       pTxData += sizeof(uint16_t);
01006       hspi->TxXferCount--;
01007     }
01008     while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
01009     {
01010       /* Check TXE flag */
01011       if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
01012       {
01013         hspi->Instance->DR = *((uint16_t *)pTxData);
01014         pTxData += sizeof(uint16_t);
01015         hspi->TxXferCount--;
01016         /* Next Data is a reception (Rx). Tx not allowed */
01017         txallowed = 0U;
01018
01019 #if (USE_SPI_CRC != 0U)
01020         /* Enable CRC Transmission */
01021         if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
01022         {
01023           /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
01024           if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
01025           {
01026             SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
01027           }
01028           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
01029         }
01030 #endif /* USE_SPI_CRC */
01031       }
01032
01033       /* Check RXNE flag */
01034       if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
01035       {
01036         *((uint16_t *)pRxData) = hspi->Instance->DR;
01037         pRxData += sizeof(uint16_t);
01038         hspi->RxXferCount--;
01039         /* Next Data is a Transmission (Tx). Tx is allowed */
01040         txallowed = 1U;
01041       }
01042       if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout))
01043       {
01044         errorcode = HAL_TIMEOUT;
01045         goto error;
01046       }
01047     }
01048   }
01049   /* Transmit and Receive data in 8 Bit mode */
01050   else
01051   {
01052     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
01053     {
01054       if (hspi->TxXferCount > 1U)
01055       {
01056         hspi->Instance->DR = *((uint16_t *)pTxData);
01057         pTxData += sizeof(uint16_t);
01058         hspi->TxXferCount -= 2U;
01059       }
01060       else
01061       {
01062         *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
01063         hspi->TxXferCount--;
01064       }
01065     }
01066     while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
01067     {
01068       /* check TXE flag */
01069       if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
01070       {
01071         if (hspi->TxXferCount > 1U)
01072         {
01073           hspi->Instance->DR = *((uint16_t *)pTxData);
01074           pTxData += sizeof(uint16_t);
01075           hspi->TxXferCount -= 2U;
01076         }
01077         else
01078         {
01079           *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
01080           hspi->TxXferCount--;
01081         }
01082         /* Next Data is a reception (Rx). Tx not allowed */
01083         txallowed = 0U;
01084
01085 #if (USE_SPI_CRC != 0U)
01086         /* Enable CRC Transmission */
01087         if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
01088         {
01089           /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
01090           if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
01091           {
01092             SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
01093           }
01094           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
01095         }
01096 #endif /* USE_SPI_CRC */
01097       }
01098
01099       /* Wait until RXNE flag is reset */
01100       if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
01101       {
01102         if (hspi->RxXferCount > 1U)
01103         {
01104           *((uint16_t *)pRxData) = hspi->Instance->DR;
01105           pRxData += sizeof(uint16_t);
01106           hspi->RxXferCount -= 2U;
01107           if (hspi->RxXferCount <= 1U)
01108           {
01109             /* set fiforxthresold before to switch on 8 bit data size */
01110             SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01111           }
01112         }
01113         else
01114         {
01115           (*(uint8_t *)pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR;
01116           hspi->RxXferCount--;
01117         }
01118         /* Next Data is a Transmission (Tx). Tx is allowed */
01119         txallowed = 1U;
01120       }
01121       if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout))
01122       {
01123         errorcode = HAL_TIMEOUT;
01124         goto error;
01125       }
01126     }
01127   }
01128
01129 #if (USE_SPI_CRC != 0U)
01130   /* Read CRC from DR to close CRC calculation process */
01131   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01132   {
01133     /* Wait until TXE flag */
01134     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
01135     {
01136       /* Error on the CRC reception */
01137       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01138       errorcode = HAL_TIMEOUT;
01139       goto error;
01140     }
01141     /* Read CRC */
01142     if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
01143     {
01144       tmpreg = hspi->Instance->DR;
01145       /* To avoid GCC warning */
01146       UNUSED(tmpreg);
01147     }
01148     else
01149     {
01150       tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
01151       /* To avoid GCC warning */
01152       UNUSED(tmpreg);
01153
01154       if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
01155       {
01156         if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
01157         {
01158           /* Error on the CRC reception */
01159           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01160           errorcode = HAL_TIMEOUT;
01161           goto error;
01162         }
01163         tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
01164         /* To avoid GCC warning */
01165         UNUSED(tmpreg);
01166       }
01167     }
01168   }
01169
01170   /* Check if CRC error occurred */
01171   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
01172   {
01173     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01174     /* Clear CRC Flag */
01175     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
01176
01177     errorcode = HAL_ERROR;
01178   }
01179 #endif /* USE_SPI_CRC */
01180
01181   /* Check the end of the transaction */
01182   if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
01183   {
01184     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
01185   }
01186
01187   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
01188   {
01189     errorcode = HAL_ERROR;
01190   }
01191
01192 error :
01193   hspi->State = HAL_SPI_STATE_READY;
01194   __HAL_UNLOCK(hspi);
01195   return errorcode;
01196 }
01197
01198 /**
01199   * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
01200   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01201   *               the configuration information for SPI module.
01202   * @param  pData pointer to data buffer
01203   * @param  Size amount of data to be sent
01204   * @retval HAL status
01205   */
01206 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01207 {
01208   HAL_StatusTypeDef errorcode = HAL_OK;
01209
01210
01211   /* Check Direction parameter */
01212   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
01213
01214   /* Process Locked */
01215   __HAL_LOCK(hspi);
01216
01217   if ((pData == NULL) || (Size == 0U))
01218   {
01219     errorcode = HAL_ERROR;
01220     goto error;
01221   }
01222
01223   if (hspi->State != HAL_SPI_STATE_READY)
01224   {
01225     errorcode = HAL_BUSY;
01226     goto error;
01227   }
01228
01229   /* Set the transaction information */
01230   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01231   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01232   hspi->pTxBuffPtr  = (uint8_t *)pData;
01233   hspi->TxXferSize  = Size;
01234   hspi->TxXferCount = Size;
01235
01236   /* Init field not used in handle to zero */
01237   hspi->pRxBuffPtr  = (uint8_t *)NULL;
01238   hspi->RxXferSize  = 0U;
01239   hspi->RxXferCount = 0U;
01240   hspi->RxISR       = NULL;
01241
01242   /* Set the function for IT treatment */
01243   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01244   {
01245     hspi->TxISR = SPI_TxISR_16BIT;
01246   }
01247   else
01248   {
01249     hspi->TxISR = SPI_TxISR_8BIT;
01250   }
01251
01252   /* Configure communication direction : 1Line */
01253   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01254   {
01255     SPI_1LINE_TX(hspi);
01256   }
01257
01258 #if (USE_SPI_CRC != 0U)
01259   /* Reset CRC Calculation */
01260   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01261   {
01262     SPI_RESET_CRC(hspi);
01263   }
01264 #endif /* USE_SPI_CRC */
01265
01266   /* Enable TXE and ERR interrupt */
01267   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
01268
01269
01270   /* Check if the SPI is already enabled */
01271   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01272   {
01273     /* Enable SPI peripheral */
01274     __HAL_SPI_ENABLE(hspi);
01275   }
01276
01277 error :
01278   __HAL_UNLOCK(hspi);
01279   return errorcode;
01280 }
01281
01282 /**
01283   * @brief  Receive an amount of data in non-blocking mode with Interrupt.
01284   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01285   *               the configuration information for SPI module.
01286   * @param  pData pointer to data buffer
01287   * @param  Size amount of data to be sent
01288   * @retval HAL status
01289   */
01290 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01291 {
01292   HAL_StatusTypeDef errorcode = HAL_OK;
01293
01294
01295   if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
01296   {
01297     hspi->State = HAL_SPI_STATE_BUSY_RX;
01298     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
01299     return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
01300   }
01301
01302   /* Process Locked */
01303   __HAL_LOCK(hspi);
01304
01305   if (hspi->State != HAL_SPI_STATE_READY)
01306   {
01307     errorcode = HAL_BUSY;
01308     goto error;
01309   }
01310
01311   if ((pData == NULL) || (Size == 0U))
01312   {
01313     errorcode = HAL_ERROR;
01314     goto error;
01315   }
01316
01317   /* Set the transaction information */
01318   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01319   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01320   hspi->pRxBuffPtr  = (uint8_t *)pData;
01321   hspi->RxXferSize  = Size;
01322   hspi->RxXferCount = Size;
01323
01324   /* Init field not used in handle to zero */
01325   hspi->pTxBuffPtr  = (uint8_t *)NULL;
01326   hspi->TxXferSize  = 0U;
01327   hspi->TxXferCount = 0U;
01328   hspi->TxISR       = NULL;
01329
01330   /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
01331   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01332   {
01333     /* Set fiforxthresold according the reception data length: 16 bit */
01334     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01335     hspi->RxISR = SPI_RxISR_16BIT;
01336   }
01337   else
01338   {
01339     /* Set fiforxthresold according the reception data length: 8 bit */
01340     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01341     hspi->RxISR = SPI_RxISR_8BIT;
01342   }
01343
01344   /* Configure communication direction : 1Line */
01345   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01346   {
01347     SPI_1LINE_RX(hspi);
01348   }
01349
01350 #if (USE_SPI_CRC != 0U)
01351   /* Reset CRC Calculation */
01352   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01353   {
01354     hspi->CRCSize = 1U;
01355     if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
01356     {
01357       hspi->CRCSize = 2U;
01358     }
01359     SPI_RESET_CRC(hspi);
01360   }
01361   else
01362   {
01363     hspi->CRCSize = 0U;
01364   }
01365 #endif /* USE_SPI_CRC */
01366
01367   /* Enable TXE and ERR interrupt */
01368   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
01369
01370   /* Note : The SPI must be enabled after unlocking current process
01371             to avoid the risk of SPI interrupt handle execution before current
01372             process unlock */
01373
01374   /* Check if the SPI is already enabled */
01375   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01376   {
01377     /* Enable SPI peripheral */
01378     __HAL_SPI_ENABLE(hspi);
01379   }
01380
01381 error :
01382   /* Process Unlocked */
01383   __HAL_UNLOCK(hspi);
01384   return errorcode;
01385 }
01386
01387 /**
01388   * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
01389   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01390   *               the configuration information for SPI module.
01391   * @param  pTxData pointer to transmission data buffer
01392   * @param  pRxData pointer to reception data buffer
01393   * @param  Size amount of data to be sent and received
01394   * @retval HAL status
01395   */
01396 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01397 {
01398   uint32_t tmp = 0U, tmp1 = 0U;
01399   HAL_StatusTypeDef errorcode = HAL_OK;
01400
01401
01402   /* Check Direction parameter */
01403   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01404
01405   /* Process locked */
01406   __HAL_LOCK(hspi);
01407
01408   tmp  = hspi->State;
01409   tmp1 = hspi->Init.Mode;
01410
01411   if (!((tmp == HAL_SPI_STATE_READY) || \
01412         ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
01413   {
01414     errorcode = HAL_BUSY;
01415     goto error;
01416   }
01417
01418   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01419   {
01420     errorcode = HAL_ERROR;
01421     goto error;
01422   }
01423
01424   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
01425   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
01426   {
01427     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01428   }
01429
01430   /* Set the transaction information */
01431   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01432   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
01433   hspi->TxXferSize  = Size;
01434   hspi->TxXferCount = Size;
01435   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
01436   hspi->RxXferSize  = Size;
01437   hspi->RxXferCount = Size;
01438
01439   /* Set the function for IT treatment */
01440   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01441   {
01442     hspi->RxISR     = SPI_2linesRxISR_16BIT;
01443     hspi->TxISR     = SPI_2linesTxISR_16BIT;
01444   }
01445   else
01446   {
01447     hspi->RxISR     = SPI_2linesRxISR_8BIT;
01448     hspi->TxISR     = SPI_2linesTxISR_8BIT;
01449   }
01450
01451 #if (USE_SPI_CRC != 0U)
01452   /* Reset CRC Calculation */
01453   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01454   {
01455     hspi->CRCSize = 1U;
01456     if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
01457     {
01458       hspi->CRCSize = 2U;
01459     }
01460     SPI_RESET_CRC(hspi);
01461   }
01462   else
01463   {
01464     hspi->CRCSize = 0U;
01465   }
01466 #endif /* USE_SPI_CRC */
01467
01468   /* Check if packing mode is enabled and if there is more than 2 data to receive */
01469   if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U))
01470   {
01471     /* Set fiforxthresold according the reception data length: 16 bit */
01472     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01473   }
01474   else
01475   {
01476     /* Set fiforxthresold according the reception data length: 8 bit */
01477     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01478   }
01479
01480   /* Enable TXE, RXNE and ERR interrupt */
01481   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
01482
01483   /* Check if the SPI is already enabled */
01484   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01485   {
01486     /* Enable SPI peripheral */
01487     __HAL_SPI_ENABLE(hspi);
01488   }
01489
01490 error :
01491   /* Process Unlocked */
01492   __HAL_UNLOCK(hspi);
01493   return errorcode;
01494 }
01495
01496 /**
01497   * @brief  Transmit an amount of data in non-blocking mode with DMA.
01498   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01499   *               the configuration information for SPI module.
01500   * @param  pData pointer to data buffer
01501   * @param  Size amount of data to be sent
01502   * @retval HAL status
01503   */
01504 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01505 {
01506   HAL_StatusTypeDef errorcode = HAL_OK;
01507
01508   /* check tx dma handle */
01509   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
01510
01511   /* Check Direction parameter */
01512   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
01513
01514   /* Process Locked */
01515   __HAL_LOCK(hspi);
01516
01517   if (hspi->State != HAL_SPI_STATE_READY)
01518   {
01519     errorcode = HAL_BUSY;
01520     goto error;
01521   }
01522
01523   if ((pData == NULL) || (Size == 0U))
01524   {
01525     errorcode = HAL_ERROR;
01526     goto error;
01527   }
01528
01529   /* Set the transaction information */
01530   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01531   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01532   hspi->pTxBuffPtr  = (uint8_t *)pData;
01533   hspi->TxXferSize  = Size;
01534   hspi->TxXferCount = Size;
01535
01536   /* Init field not used in handle to zero */
01537   hspi->pRxBuffPtr  = (uint8_t *)NULL;
01538   hspi->TxISR       = NULL;
01539   hspi->RxISR       = NULL;
01540   hspi->RxXferSize  = 0U;
01541   hspi->RxXferCount = 0U;
01542
01543   /* Configure communication direction : 1Line */
01544   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01545   {
01546     SPI_1LINE_TX(hspi);
01547   }
01548
01549 #if (USE_SPI_CRC != 0U)
01550   /* Reset CRC Calculation */
01551   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01552   {
01553     SPI_RESET_CRC(hspi);
01554   }
01555 #endif /* USE_SPI_CRC */
01556
01557   /* Set the SPI TxDMA Half transfer complete callback */
01558   hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
01559
01560   /* Set the SPI TxDMA transfer complete callback */
01561   hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
01562
01563   /* Set the DMA error callback */
01564   hspi->hdmatx->XferErrorCallback = SPI_DMAError;
01565
01566   /* Set the DMA AbortCpltCallback */
01567   hspi->hdmatx->XferAbortCallback = NULL;
01568
01569   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01570   /* Packing mode is enabled only if the DMA setting is HALWORD */
01571   if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
01572   {
01573     /* Check the even/odd of the data size + crc if enabled */
01574     if ((hspi->TxXferCount & 0x1U) == 0U)
01575     {
01576       CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01577       hspi->TxXferCount = (hspi->TxXferCount >> 1U);
01578     }
01579     else
01580     {
01581       SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01582       hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
01583     }
01584   }
01585
01586   /* Enable the Tx DMA Stream/Channel */
01587   HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
01588
01589   /* Check if the SPI is already enabled */
01590   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01591   {
01592     /* Enable SPI peripheral */
01593     __HAL_SPI_ENABLE(hspi);
01594   }
01595
01596   /* Enable the SPI Error Interrupt Bit */
01597   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
01598
01599   /* Enable Tx DMA Request */
01600   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
01601
01602 error :
01603   /* Process Unlocked */
01604   __HAL_UNLOCK(hspi);
01605   return errorcode;
01606 }
01607
01608 /**
01609   * @brief  Receive an amount of data in non-blocking mode with DMA.
01610   * @note   In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
01611   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01612   *               the configuration information for SPI module.
01613   * @param  pData pointer to data buffer
01614   * @note   When the CRC feature is enabled the pData Length must be Size + 1.
01615   * @param  Size amount of data to be sent
01616   * @retval HAL status
01617   */
01618 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01619 {
01620   HAL_StatusTypeDef errorcode = HAL_OK;
01621
01622   /* check rx dma handle */
01623   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
01624
01625   if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
01626   {
01627     hspi->State = HAL_SPI_STATE_BUSY_RX;
01628
01629     /* check tx dma handle */
01630     assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
01631
01632     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
01633     return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
01634   }
01635
01636   /* Process Locked */
01637   __HAL_LOCK(hspi);
01638
01639   if (hspi->State != HAL_SPI_STATE_READY)
01640   {
01641     errorcode = HAL_BUSY;
01642     goto error;
01643   }
01644
01645   if ((pData == NULL) || (Size == 0U))
01646   {
01647     errorcode = HAL_ERROR;
01648     goto error;
01649   }
01650
01651   /* Set the transaction information */
01652   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01653   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01654   hspi->pRxBuffPtr  = (uint8_t *)pData;
01655   hspi->RxXferSize  = Size;
01656   hspi->RxXferCount = Size;
01657
01658   /*Init field not used in handle to zero */
01659   hspi->RxISR       = NULL;
01660   hspi->TxISR       = NULL;
01661   hspi->TxXferSize  = 0U;
01662   hspi->TxXferCount = 0U;
01663
01664   /* Configure communication direction : 1Line */
01665   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01666   {
01667     SPI_1LINE_RX(hspi);
01668   }
01669
01670 #if (USE_SPI_CRC != 0U)
01671   /* Reset CRC Calculation */
01672   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01673   {
01674     SPI_RESET_CRC(hspi);
01675   }
01676 #endif /* USE_SPI_CRC */
01677
01678 #if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx) || defined (STM32F378xx)
01679   /* Packing mode management is enabled by the DMA settings */
01680   if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
01681   {
01682     /* Restriction the DMA data received is not allowed in this mode */
01683     errorcode = HAL_ERROR;
01684     goto error;
01685   }
01686 #endif
01687
01688   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
01689   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01690   {
01691     /* Set fiforxthresold according the reception data length: 16bit */
01692     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01693   }
01694   else
01695   {
01696     /* Set fiforxthresold according the reception data length: 8bit */
01697     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01698
01699     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
01700     {
01701       /* set fiforxthresold according the reception data length: 16bit */
01702       CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01703
01704       if ((hspi->RxXferCount & 0x1U) == 0x0U)
01705       {
01706         CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
01707         hspi->RxXferCount = hspi->RxXferCount >> 1U;
01708       }
01709       else
01710       {
01711         SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
01712         hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
01713       }
01714     }
01715   }
01716
01717   /* Set the SPI RxDMA Half transfer complete callback */
01718   hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
01719
01720   /* Set the SPI Rx DMA transfer complete callback */
01721   hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
01722
01723   /* Set the DMA error callback */
01724   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
01725
01726   /* Set the DMA AbortCpltCallback */
01727   hspi->hdmarx->XferAbortCallback = NULL;
01728
01729   /* Enable the Rx DMA Stream/Channel  */
01730   HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
01731
01732   /* Check if the SPI is already enabled */
01733   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01734   {
01735     /* Enable SPI peripheral */
01736     __HAL_SPI_ENABLE(hspi);
01737   }
01738
01739   /* Enable the SPI Error Interrupt Bit */
01740   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
01741
01742   /* Enable Rx DMA Request */
01743   SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
01744
01745 error:
01746   /* Process Unlocked */
01747   __HAL_UNLOCK(hspi);
01748   return errorcode;
01749 }
01750
01751 /**
01752   * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
01753   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01754   *               the configuration information for SPI module.
01755   * @param  pTxData pointer to transmission data buffer
01756   * @param  pRxData pointer to reception data buffer
01757   * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
01758   * @param  Size amount of data to be sent
01759   * @retval HAL status
01760   */
01761 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
01762                                               uint16_t Size)
01763 {
01764   uint32_t tmp = 0U, tmp1 = 0U;
01765   HAL_StatusTypeDef errorcode = HAL_OK;
01766
01767   /* check rx & tx dma handles */
01768   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
01769   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
01770
01771   /* Check Direction parameter */
01772   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01773
01774   /* Process locked */
01775   __HAL_LOCK(hspi);
01776
01777   tmp  = hspi->State;
01778   tmp1 = hspi->Init.Mode;
01779   if (!((tmp == HAL_SPI_STATE_READY) ||
01780         ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
01781   {
01782     errorcode = HAL_BUSY;
01783     goto error;
01784   }
01785
01786   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01787   {
01788     errorcode = HAL_ERROR;
01789     goto error;
01790   }
01791
01792   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
01793   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
01794   {
01795     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01796   }
01797
01798   /* Set the transaction information */
01799   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01800   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
01801   hspi->TxXferSize  = Size;
01802   hspi->TxXferCount = Size;
01803   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
01804   hspi->RxXferSize  = Size;
01805   hspi->RxXferCount = Size;
01806
01807   /* Init field not used in handle to zero */
01808   hspi->RxISR       = NULL;
01809   hspi->TxISR       = NULL;
01810
01811 #if (USE_SPI_CRC != 0U)
01812   /* Reset CRC Calculation */
01813   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01814   {
01815     SPI_RESET_CRC(hspi);
01816   }
01817 #endif /* USE_SPI_CRC */
01818
01819
01820 #if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx) || defined (STM32F378xx)
01821   /* packing mode management is enabled by the DMA settings */
01822   if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
01823   {
01824     /* Restriction the DMA data received is not allowed in this mode */
01825     errorcode = HAL_ERROR;
01826     goto error;
01827   }
01828 #endif
01829
01830   /* Reset the threshold bit */
01831   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
01832
01833   /* The packing mode management is enabled by the DMA settings according the spi data size */
01834   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01835   {
01836     /* Set fiforxthreshold according the reception data length: 16bit */
01837     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01838   }
01839   else
01840   {
01841     /* Set fiforxthresold according the reception data length: 8bit */
01842     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01843
01844     if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
01845     {
01846       if ((hspi->TxXferSize & 0x1U) == 0x0U)
01847       {
01848         CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01849         hspi->TxXferCount = hspi->TxXferCount >> 1U;
01850       }
01851       else
01852       {
01853         SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01854         hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
01855       }
01856     }
01857
01858     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
01859     {
01860       /* Set fiforxthresold according the reception data length: 16bit */
01861       CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01862
01863       if ((hspi->RxXferCount & 0x1U) == 0x0U)
01864       {
01865         CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
01866         hspi->RxXferCount = hspi->RxXferCount >> 1U;
01867       }
01868       else
01869       {
01870         SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
01871         hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
01872       }
01873     }
01874   }
01875
01876   /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
01877   if (hspi->State == HAL_SPI_STATE_BUSY_RX)
01878   {
01879     /* Set the SPI Rx DMA Half transfer complete callback */
01880     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
01881     hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
01882   }
01883   else
01884   {
01885     /* Set the SPI Tx/Rx DMA Half transfer complete callback */
01886     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
01887     hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
01888   }
01889
01890   /* Set the DMA error callback */
01891   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
01892
01893   /* Set the DMA AbortCpltCallback */
01894   hspi->hdmarx->XferAbortCallback = NULL;
01895
01896   /* Enable the Rx DMA Stream/Channel  */
01897   HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
01898
01899   /* Enable Rx DMA Request */
01900   SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
01901
01902   /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
01903   is performed in DMA reception complete callback  */
01904   hspi->hdmatx->XferHalfCpltCallback = NULL;
01905   hspi->hdmatx->XferCpltCallback     = NULL;
01906   hspi->hdmatx->XferErrorCallback    = NULL;
01907   hspi->hdmatx->XferAbortCallback    = NULL;
01908
01909   /* Enable the Tx DMA Stream/Channel  */
01910   HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
01911
01912   /* Check if the SPI is already enabled */
01913   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01914   {
01915     /* Enable SPI peripheral */
01916     __HAL_SPI_ENABLE(hspi);
01917   }
01918   /* Enable the SPI Error Interrupt Bit */
01919   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
01920
01921   /* Enable Tx DMA Request */
01922   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
01923
01924 error :
01925   /* Process Unlocked */
01926   __HAL_UNLOCK(hspi);
01927   return errorcode;
01928 }
01929
01930 /**
01931   * @brief  Abort ongoing transfer (blocking mode).
01932   * @param  hspi SPI handle.
01933   * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
01934   *         started in Interrupt or DMA mode.
01935   *         This procedure performs following operations :
01936   *           - Disable SPI Interrupts (depending of transfer direction)
01937   *           - Disable the DMA transfer in the peripheral register (if enabled)
01938   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01939   *           - Set handle State to READY
01940   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01941   * @retval HAL status
01942 */
01943 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
01944 {
01945   HAL_StatusTypeDef errorcode;
01946   __IO uint32_t count, resetcount;
01947
01948   /* Initialized local variable  */
01949   errorcode = HAL_OK;
01950   resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
01951   count = resetcount;
01952
01953   /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
01954   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
01955   {
01956     hspi->TxISR = SPI_AbortTx_ISR;
01957     /* Wait HAL_SPI_STATE_ABORT state */
01958     do
01959     {
01960       if (count-- == 0U)
01961       {
01962         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
01963         break;
01964       }
01965     }
01966     while (hspi->State != HAL_SPI_STATE_ABORT);
01967     /* Reset Timeout Counter */
01968     count = resetcount;
01969   }
01970
01971   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
01972   {
01973     hspi->RxISR = SPI_AbortRx_ISR;
01974     /* Wait HAL_SPI_STATE_ABORT state */
01975     do
01976     {
01977       if (count-- == 0U)
01978       {
01979         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
01980         break;
01981       }
01982     }
01983     while (hspi->State != HAL_SPI_STATE_ABORT);
01984     /* Reset Timeout Counter */
01985     count = resetcount;
01986   }
01987
01988   /* Clear ERRIE interrupts in case of DMA Mode */
01989   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
01990
01991   /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
01992   if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
01993   {
01994     /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
01995     if (hspi->hdmatx != NULL)
01996     {
01997       /* Set the SPI DMA Abort callback :
01998       will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
01999       hspi->hdmatx->XferAbortCallback = NULL;
02000
02001       /* Abort DMA Tx Handle linked to SPI Peripheral */
02002       if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
02003       {
02004         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02005       }
02006
02007       /* Disable Tx DMA Request */
02008       CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
02009
02010       if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02011       {
02012         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02013       }
02014
02015       /* Disable SPI Peripheral */
02016       __HAL_SPI_DISABLE(hspi);
02017
02018       /* Empty the FRLVL fifo */
02019       if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02020       {
02021         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02022       }
02023     }
02024     /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
02025     if (hspi->hdmarx != NULL)
02026     {
02027       /* Set the SPI DMA Abort callback :
02028       will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
02029       hspi->hdmarx->XferAbortCallback = NULL;
02030
02031       /* Abort DMA Rx Handle linked to SPI Peripheral */
02032       if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
02033       {
02034         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02035       }
02036
02037       /* Disable peripheral */
02038       __HAL_SPI_DISABLE(hspi);
02039
02040       /* Control the BSY flag */
02041       if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02042       {
02043         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02044       }
02045
02046       /* Empty the FRLVL fifo */
02047       if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02048       {
02049         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02050       }
02051
02052       /* Disable Rx DMA Request */
02053       CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
02054     }
02055   }
02056   /* Reset Tx and Rx transfer counters */
02057   hspi->RxXferCount = 0U;
02058   hspi->TxXferCount = 0U;
02059
02060   /* Check error during Abort procedure */
02061   if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
02062   {
02063     /* return HAL_Error in case of error during Abort procedure */
02064     errorcode = HAL_ERROR;
02065   }
02066   else
02067   {
02068     /* Reset errorCode */
02069     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
02070   }
02071
02072   /* Clear the Error flags in the SR register */
02073   __HAL_SPI_CLEAR_OVRFLAG(hspi);
02074   __HAL_SPI_CLEAR_FREFLAG(hspi);
02075
02076   /* Restore hspi->state to ready */
02077   hspi->State = HAL_SPI_STATE_READY;
02078
02079   return errorcode;
02080 }
02081
02082 /**
02083   * @brief  Abort ongoing transfer (Interrupt mode).
02084   * @param  hspi SPI handle.
02085   * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
02086   *         started in Interrupt or DMA mode.
02087   *         This procedure performs following operations :
02088   *           - Disable SPI Interrupts (depending of transfer direction)
02089   *           - Disable the DMA transfer in the peripheral register (if enabled)
02090   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
02091   *           - Set handle State to READY
02092   *           - At abort completion, call user abort complete callback
02093   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
02094   *         considered as completed only when user abort complete callback is executed (not when exiting function).
02095   * @retval HAL status
02096 */
02097 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
02098 {
02099   HAL_StatusTypeDef errorcode;
02100   uint32_t abortcplt ;
02101   __IO uint32_t count, resetcount;
02102
02103   /* Initialized local variable  */
02104   errorcode = HAL_OK;
02105   abortcplt = 1U;
02106   resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
02107   count = resetcount;
02108
02109   /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
02110   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
02111   {
02112     hspi->TxISR = SPI_AbortTx_ISR;
02113     /* Wait HAL_SPI_STATE_ABORT state */
02114     do
02115     {
02116       if (count-- == 0U)
02117       {
02118         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02119         break;
02120       }
02121     }
02122     while (hspi->State != HAL_SPI_STATE_ABORT);
02123     /* Reset Timeout Counter */
02124     count = resetcount;
02125   }
02126
02127   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
02128   {
02129     hspi->RxISR = SPI_AbortRx_ISR;
02130     /* Wait HAL_SPI_STATE_ABORT state */
02131     do
02132     {
02133       if (count-- == 0U)
02134       {
02135         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02136         break;
02137       }
02138     }
02139     while (hspi->State != HAL_SPI_STATE_ABORT);
02140     /* Reset Timeout Counter */
02141     count = resetcount;
02142   }
02143
02144   /* Clear ERRIE interrupts in case of DMA Mode */
02145   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
02146
02147   /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
02148      before any call to DMA Abort functions */
02149   /* DMA Tx Handle is valid */
02150   if (hspi->hdmatx != NULL)
02151   {
02152     /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
02153        Otherwise, set it to NULL */
02154     if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
02155     {
02156       hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
02157     }
02158     else
02159     {
02160       hspi->hdmatx->XferAbortCallback = NULL;
02161     }
02162   }
02163   /* DMA Rx Handle is valid */
02164   if (hspi->hdmarx != NULL)
02165   {
02166     /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
02167        Otherwise, set it to NULL */
02168     if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
02169     {
02170       hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
02171     }
02172     else
02173     {
02174       hspi->hdmarx->XferAbortCallback = NULL;
02175     }
02176   }
02177
02178   /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
02179   if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
02180   {
02181     /* Abort the SPI DMA Tx Stream/Channel */
02182     if (hspi->hdmatx != NULL)
02183     {
02184       /* Abort DMA Tx Handle linked to SPI Peripheral */
02185       if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
02186       {
02187         hspi->hdmatx->XferAbortCallback = NULL;
02188         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02189       }
02190       else
02191       {
02192         abortcplt = 0U;
02193       }
02194     }
02195     /* Abort the SPI DMA Rx Stream/Channel */
02196     if (hspi->hdmarx != NULL)
02197     {
02198       /* Abort DMA Rx Handle linked to SPI Peripheral */
02199       if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
02200       {
02201         hspi->hdmarx->XferAbortCallback = NULL;
02202         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02203         abortcplt = 1U;
02204       }
02205       else
02206       {
02207         abortcplt = 0U;
02208       }
02209     }
02210   }
02211
02212   /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
02213   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
02214   {
02215     /* Abort the SPI DMA Tx Stream/Channel */
02216     if (hspi->hdmatx != NULL)
02217     {
02218       /* Abort DMA Tx Handle linked to SPI Peripheral */
02219       if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
02220       {
02221         hspi->hdmatx->XferAbortCallback = NULL;
02222         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02223       }
02224       else
02225       {
02226         abortcplt = 0U;
02227       }
02228     }
02229   }
02230   /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
02231   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
02232   {
02233     /* Abort the SPI DMA Rx Stream/Channel */
02234     if (hspi->hdmarx != NULL)
02235     {
02236       /* Abort DMA Rx Handle linked to SPI Peripheral */
02237       if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
02238       {
02239         hspi->hdmarx->XferAbortCallback = NULL;
02240         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02241       }
02242       else
02243       {
02244         abortcplt = 0U;
02245       }
02246     }
02247   }
02248
02249   if (abortcplt == 1U)
02250   {
02251     /* Reset Tx and Rx transfer counters */
02252     hspi->RxXferCount = 0U;
02253     hspi->TxXferCount = 0U;
02254
02255     /* Check error during Abort procedure */
02256     if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
02257     {
02258       /* return HAL_Error in case of error during Abort procedure */
02259       errorcode = HAL_ERROR;
02260     }
02261     else
02262     {
02263       /* Reset errorCode */
02264       hspi->ErrorCode = HAL_SPI_ERROR_NONE;
02265     }
02266
02267     /* Clear the Error flags in the SR register */
02268     __HAL_SPI_CLEAR_OVRFLAG(hspi);
02269     __HAL_SPI_CLEAR_FREFLAG(hspi);
02270
02271     /* Restore hspi->State to Ready */
02272     hspi->State = HAL_SPI_STATE_READY;
02273
02274     /* As no DMA to be aborted, call directly user Abort complete callback */
02275     HAL_SPI_AbortCpltCallback(hspi);
02276   }
02277
02278   return errorcode;
02279 }
02280
02281 /**
02282   * @brief  Pause the DMA Transfer.
02283   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02284   *               the configuration information for the specified SPI module.
02285   * @retval HAL status
02286   */
02287 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
02288 {
02289   /* Process Locked */
02290   __HAL_LOCK(hspi);
02291
02292   /* Disable the SPI DMA Tx & Rx requests */
02293   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02294
02295   /* Process Unlocked */
02296   __HAL_UNLOCK(hspi);
02297
02298   return HAL_OK;
02299 }
02300
02301 /**
02302   * @brief  Resume the DMA Transfer.
02303   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02304   *               the configuration information for the specified SPI module.
02305   * @retval HAL status
02306   */
02307 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
02308 {
02309   /* Process Locked */
02310   __HAL_LOCK(hspi);
02311
02312   /* Enable the SPI DMA Tx & Rx requests */
02313   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02314
02315   /* Process Unlocked */
02316   __HAL_UNLOCK(hspi);
02317
02318   return HAL_OK;
02319 }
02320
02321 /**
02322   * @brief Stop the DMA Transfer.
02323   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02324   *               the configuration information for the specified SPI module.
02325   * @retval HAL status
02326   */
02327 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
02328 {
02329   /* The Lock is not implemented on this API to allow the user application
02330      to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
02331      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
02332      and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
02333      */
02334
02335   /* Abort the SPI DMA tx Stream/Channel  */
02336   if (hspi->hdmatx != NULL)
02337   {
02338     HAL_DMA_Abort(hspi->hdmatx);
02339   }
02340   /* Abort the SPI DMA rx Stream/Channel  */
02341   if (hspi->hdmarx != NULL)
02342   {
02343     HAL_DMA_Abort(hspi->hdmarx);
02344   }
02345
02346   /* Disable the SPI DMA Tx & Rx requests */
02347   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02348   hspi->State = HAL_SPI_STATE_READY;
02349   return HAL_OK;
02350 }
02351
02352 /**
02353   * @brief  Handle SPI interrupt request.
02354   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02355   *               the configuration information for the specified SPI module.
02356   * @retval None
02357   */
02358 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
02359 {
02360   uint32_t itsource = hspi->Instance->CR2;
02361   uint32_t itflag   = hspi->Instance->SR;
02362
02363   /* SPI in mode Receiver ----------------------------------------------------*/
02364   if (((itflag & SPI_FLAG_OVR) == RESET) &&
02365       ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
02366   {
02367     hspi->RxISR(hspi);
02368     return;
02369   }
02370
02371   /* SPI in mode Transmitter -------------------------------------------------*/
02372   if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
02373   {
02374     hspi->TxISR(hspi);
02375     return;
02376   }
02377
02378   /* SPI in Error Treatment --------------------------------------------------*/
02379   if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
02380   {
02381     /* SPI Overrun error interrupt occurred ----------------------------------*/
02382     if ((itflag & SPI_FLAG_OVR) != RESET)
02383     {
02384       if (hspi->State != HAL_SPI_STATE_BUSY_TX)
02385       {
02386         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
02387         __HAL_SPI_CLEAR_OVRFLAG(hspi);
02388       }
02389       else
02390       {
02391         __HAL_SPI_CLEAR_OVRFLAG(hspi);
02392         return;
02393       }
02394     }
02395
02396     /* SPI Mode Fault error interrupt occurred -------------------------------*/
02397     if ((itflag & SPI_FLAG_MODF) != RESET)
02398     {
02399       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
02400       __HAL_SPI_CLEAR_MODFFLAG(hspi);
02401     }
02402
02403     /* SPI Frame error interrupt occurred ------------------------------------*/
02404     if ((itflag & SPI_FLAG_FRE) != RESET)
02405     {
02406       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
02407       __HAL_SPI_CLEAR_FREFLAG(hspi);
02408     }
02409
02410     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02411     {
02412       /* Disable all interrupts */
02413       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
02414
02415       hspi->State = HAL_SPI_STATE_READY;
02416       /* Disable the SPI DMA requests if enabled */
02417       if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
02418       {
02419         CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
02420
02421         /* Abort the SPI DMA Rx channel */
02422         if (hspi->hdmarx != NULL)
02423         {
02424           /* Set the SPI DMA Abort callback :
02425           will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
02426           hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
02427           HAL_DMA_Abort_IT(hspi->hdmarx);
02428         }
02429         /* Abort the SPI DMA Tx channel */
02430         if (hspi->hdmatx != NULL)
02431         {
02432           /* Set the SPI DMA Abort callback :
02433           will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
02434           hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
02435           HAL_DMA_Abort_IT(hspi->hdmatx);
02436         }
02437       }
02438       else
02439       {
02440         /* Call user error callback */
02441         HAL_SPI_ErrorCallback(hspi);
02442       }
02443     }
02444     return;
02445   }
02446 }
02447
02448 /**
02449   * @brief Tx Transfer completed callback.
02450   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02451   *               the configuration information for SPI module.
02452   * @retval None
02453   */
02454 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
02455 {
02456   /* Prevent unused argument(s) compilation warning */
02457   UNUSED(hspi);
02458
02459   /* NOTE : This function should not be modified, when the callback is needed,
02460             the HAL_SPI_TxCpltCallback should be implemented in the user file
02461    */
02462 }
02463
02464 /**
02465   * @brief Rx Transfer completed callback.
02466   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02467   *               the configuration information for SPI module.
02468   * @retval None
02469   */
02470 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
02471 {
02472   /* Prevent unused argument(s) compilation warning */
02473   UNUSED(hspi);
02474
02475   /* NOTE : This function should not be modified, when the callback is needed,
02476             the HAL_SPI_RxCpltCallback should be implemented in the user file
02477    */
02478 }
02479
02480 /**
02481   * @brief Tx and Rx Transfer completed callback.
02482   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02483   *               the configuration information for SPI module.
02484   * @retval None
02485   */
02486 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
02487 {
02488   /* Prevent unused argument(s) compilation warning */
02489   UNUSED(hspi);
02490
02491   /* NOTE : This function should not be modified, when the callback is needed,
02492             the HAL_SPI_TxRxCpltCallback should be implemented in the user file
02493    */
02494 }
02495
02496 /**
02497   * @brief Tx Half Transfer completed callback.
02498   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02499   *               the configuration information for SPI module.
02500   * @retval None
02501   */
02502 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02503 {
02504   /* Prevent unused argument(s) compilation warning */
02505   UNUSED(hspi);
02506
02507   /* NOTE : This function should not be modified, when the callback is needed,
02508             the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
02509    */
02510 }
02511
02512 /**
02513   * @brief Rx Half Transfer completed callback.
02514   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02515   *               the configuration information for SPI module.
02516   * @retval None
02517   */
02518 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02519 {
02520   /* Prevent unused argument(s) compilation warning */
02521   UNUSED(hspi);
02522
02523   /* NOTE : This function should not be modified, when the callback is needed,
02524             the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
02525    */
02526 }
02527
02528 /**
02529   * @brief Tx and Rx Half Transfer callback.
02530   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02531   *               the configuration information for SPI module.
02532   * @retval None
02533   */
02534 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02535 {
02536   /* Prevent unused argument(s) compilation warning */
02537   UNUSED(hspi);
02538
02539   /* NOTE : This function should not be modified, when the callback is needed,
02540             the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
02541    */
02542 }
02543
02544 /**
02545   * @brief SPI error callback.
02546   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02547   *               the configuration information for SPI module.
02548   * @retval None
02549   */
02550 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
02551 {
02552   /* Prevent unused argument(s) compilation warning */
02553   UNUSED(hspi);
02554
02555   /* NOTE : This function should not be modified, when the callback is needed,
02556             the HAL_SPI_ErrorCallback should be implemented in the user file
02557    */
02558   /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
02559             and user can use HAL_SPI_GetError() API to check the latest error occurred
02560    */
02561 }
02562
02563 /**
02564   * @brief  SPI Abort Complete callback.
02565   * @param  hspi SPI handle.
02566   * @retval None
02567   */
02568 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
02569 {
02570   /* Prevent unused argument(s) compilation warning */
02571   UNUSED(hspi);
02572
02573   /* NOTE : This function should not be modified, when the callback is needed,
02574             the HAL_SPI_AbortCpltCallback can be implemented in the user file.
02575    */
02576 }
02577
02578 /**
02579   * @}
02580   */
02581
02582 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
02583   * @brief   SPI control functions
02584   *
02585 @verbatim
02586  ===============================================================================
02587                       ##### Peripheral State and Errors functions #####
02588  ===============================================================================
02589     [..]
02590     This subsection provides a set of functions allowing to control the SPI.
02591      (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
02592      (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
02593 @endverbatim
02594   * @{
02595   */
02596
02597 /**
02598   * @brief  Return the SPI handle state.
02599   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02600   *               the configuration information for SPI module.
02601   * @retval SPI state
02602   */
02603 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
02604 {
02605   /* Return SPI handle state */
02606   return hspi->State;
02607 }
02608
02609 /**
02610   * @brief  Return the SPI error code.
02611   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02612   *               the configuration information for SPI module.
02613   * @retval SPI error code in bitmap format
02614   */
02615 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
02616 {
02617   /* Return SPI ErrorCode */
02618   return hspi->ErrorCode;
02619 }
02620
02621 /**
02622   * @}
02623   */
02624
02625 /**
02626   * @}
02627   */
02628
02629 /** @addtogroup SPI_Private_Functions
02630   * @brief   Private functions
02631   * @{
02632   */
02633
02634 /**
02635   * @brief DMA SPI transmit process complete callback.
02636   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02637   *               the configuration information for the specified DMA module.
02638   * @retval None
02639   */
02640 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02641 {
02642   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02643   uint32_t tickstart = 0U;
02644
02645   /* Init tickstart for timeout managment*/
02646   tickstart = HAL_GetTick();
02647
02648   /* DMA Normal Mode */
02649   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
02650   {
02651     /* Disable ERR interrupt */
02652     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
02653
02654     /* Disable Tx DMA Request */
02655     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
02656
02657     /* Check the end of the transaction */
02658     if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
02659     {
02660       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
02661     }
02662
02663     /* Clear overrun flag in 2 Lines communication mode because received data is not read */
02664     if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
02665     {
02666       __HAL_SPI_CLEAR_OVRFLAG(hspi);
02667     }
02668
02669     hspi->TxXferCount = 0U;
02670     hspi->State = HAL_SPI_STATE_READY;
02671
02672     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02673     {
02674       HAL_SPI_ErrorCallback(hspi);
02675       return;
02676     }
02677   }
02678   HAL_SPI_TxCpltCallback(hspi);
02679 }
02680
02681 /**
02682   * @brief DMA SPI receive process complete callback.
02683   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02684   *               the configuration information for the specified DMA module.
02685   * @retval None
02686   */
02687 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02688 {
02689   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02690   uint32_t tickstart = 0U;
02691 #if (USE_SPI_CRC != 0U)
02692   __IO uint16_t tmpreg = 0U;
02693 #endif /* USE_SPI_CRC */
02694
02695   /* Init tickstart for timeout management*/
02696   tickstart = HAL_GetTick();
02697
02698   /* DMA Normal Mode */
02699   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
02700   {
02701     /* Disable ERR interrupt */
02702     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
02703
02704 #if (USE_SPI_CRC != 0U)
02705     /* CRC handling */
02706     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02707     {
02708       /* Wait until RXNE flag */
02709       if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
02710       {
02711         /* Error on the CRC reception */
02712         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
02713       }
02714       /* Read CRC */
02715       if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
02716       {
02717         tmpreg = hspi->Instance->DR;
02718         /* To avoid GCC warning */
02719         UNUSED(tmpreg);
02720       }
02721       else
02722       {
02723         tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
02724         /* To avoid GCC warning */
02725         UNUSED(tmpreg);
02726
02727         if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
02728         {
02729           if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
02730           {
02731             /* Error on the CRC reception */
02732             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
02733           }
02734           tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
02735           /* To avoid GCC warning */
02736           UNUSED(tmpreg);
02737         }
02738       }
02739     }
02740 #endif /* USE_SPI_CRC */
02741
02742     /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
02743     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02744
02745     /* Check the end of the transaction */
02746     if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
02747     {
02748       hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
02749     }
02750
02751     hspi->RxXferCount = 0U;
02752     hspi->State = HAL_SPI_STATE_READY;
02753
02754 #if (USE_SPI_CRC != 0U)
02755     /* Check if CRC error occurred */
02756     if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
02757     {
02758       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
02759       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
02760     }
02761 #endif /* USE_SPI_CRC */
02762
02763     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02764     {
02765       HAL_SPI_ErrorCallback(hspi);
02766       return;
02767     }
02768   }
02769   HAL_SPI_RxCpltCallback(hspi);
02770 }
02771
02772 /**
02773   * @brief  DMA SPI transmit receive process complete callback.
02774   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02775   *               the configuration information for the specified DMA module.
02776   * @retval None
02777   */
02778 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
02779 {
02780   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02781   uint32_t tickstart = 0U;
02782 #if (USE_SPI_CRC != 0U)
02783   __IO int16_t tmpreg = 0U;
02784 #endif /* USE_SPI_CRC */
02785   /* Init tickstart for timeout management*/
02786   tickstart = HAL_GetTick();
02787
02788   /* DMA Normal Mode */
02789   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
02790   {
02791     /* Disable ERR interrupt */
02792     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
02793
02794 #if (USE_SPI_CRC != 0U)
02795     /* CRC handling */
02796     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02797     {
02798       if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
02799       {
02800         if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
02801                                           tickstart) != HAL_OK)
02802         {
02803           /* Error on the CRC reception */
02804           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
02805         }
02806         /* Read CRC to Flush DR and RXNE flag */
02807         tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
02808         /* To avoid GCC warning */
02809         UNUSED(tmpreg);
02810       }
02811       else
02812       {
02813         if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
02814         {
02815           /* Error on the CRC reception */
02816           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
02817         }
02818         /* Read CRC to Flush DR and RXNE flag */
02819         tmpreg = hspi->Instance->DR;
02820         /* To avoid GCC warning */
02821         UNUSED(tmpreg);
02822       }
02823     }
02824 #endif /* USE_SPI_CRC */
02825
02826     /* Check the end of the transaction */
02827     if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
02828     {
02829       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
02830     }
02831
02832     /* Disable Rx/Tx DMA Request */
02833     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02834
02835     hspi->TxXferCount = 0U;
02836     hspi->RxXferCount = 0U;
02837     hspi->State = HAL_SPI_STATE_READY;
02838
02839 #if (USE_SPI_CRC != 0U)
02840     /* Check if CRC error occurred */
02841     if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
02842     {
02843       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
02844       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
02845     }
02846 #endif /* USE_SPI_CRC */
02847
02848     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02849     {
02850       HAL_SPI_ErrorCallback(hspi);
02851       return;
02852     }
02853   }
02854   HAL_SPI_TxRxCpltCallback(hspi);
02855 }
02856
02857 /**
02858   * @brief  DMA SPI half transmit process complete callback.
02859   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02860   *               the configuration information for the specified DMA module.
02861   * @retval None
02862   */
02863 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
02864 {
02865   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02866
02867   HAL_SPI_TxHalfCpltCallback(hspi);
02868 }
02869
02870 /**
02871   * @brief  DMA SPI half receive process complete callback
02872   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02873   *               the configuration information for the specified DMA module.
02874   * @retval None
02875   */
02876 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
02877 {
02878   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02879
02880   HAL_SPI_RxHalfCpltCallback(hspi);
02881 }
02882
02883 /**
02884   * @brief  DMA SPI half transmit receive process complete callback.
02885   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02886   *               the configuration information for the specified DMA module.
02887   * @retval None
02888   */
02889 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
02890 {
02891   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02892
02893   HAL_SPI_TxRxHalfCpltCallback(hspi);
02894 }
02895
02896 /**
02897   * @brief  DMA SPI communication error callback.
02898   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02899   *               the configuration information for the specified DMA module.
02900   * @retval None
02901   */
02902 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
02903 {
02904   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02905
02906   /* Stop the disable DMA transfer on SPI side */
02907   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02908
02909   SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02910   hspi->State = HAL_SPI_STATE_READY;
02911   HAL_SPI_ErrorCallback(hspi);
02912 }
02913
02914 /**
02915   * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
02916   *         (To be called at end of DMA Abort procedure following error occurrence).
02917   * @param  hdma DMA handle.
02918   * @retval None
02919   */
02920 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02921 {
02922   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02923   hspi->RxXferCount = 0U;
02924   hspi->TxXferCount = 0U;
02925
02926   HAL_SPI_ErrorCallback(hspi);
02927 }
02928
02929 /**
02930   * @brief  DMA SPI Tx communication abort callback, when initiated by user
02931   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02932   * @note   When this callback is executed, User Abort complete call back is called only if no
02933   *         Abort still ongoing for Rx DMA Handle.
02934   * @param  hdma DMA handle.
02935   * @retval None
02936   */
02937 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02938 {
02939   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02940
02941   hspi->hdmatx->XferAbortCallback = NULL;
02942
02943   /* Disable Tx DMA Request */
02944   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
02945
02946   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02947   {
02948     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02949   }
02950
02951   /* Disable SPI Peripheral */
02952   __HAL_SPI_DISABLE(hspi);
02953
02954   /* Empty the FRLVL fifo */
02955   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02956   {
02957     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02958   }
02959
02960   /* Check if an Abort process is still ongoing */
02961   if (hspi->hdmarx != NULL)
02962   {
02963     if (hspi->hdmarx->XferAbortCallback != NULL)
02964     {
02965       return;
02966     }
02967   }
02968
02969   /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
02970   hspi->RxXferCount = 0U;
02971   hspi->TxXferCount = 0U;
02972
02973   /* Check no error during Abort procedure */
02974   if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
02975   {
02976     /* Reset errorCode */
02977     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
02978   }
02979
02980   /* Clear the Error flags in the SR register */
02981   __HAL_SPI_CLEAR_OVRFLAG(hspi);
02982   __HAL_SPI_CLEAR_FREFLAG(hspi);
02983
02984   /* Restore hspi->State to Ready */
02985   hspi->State  = HAL_SPI_STATE_READY;
02986
02987   /* Call user Abort complete callback */
02988   HAL_SPI_AbortCpltCallback(hspi);
02989 }
02990
02991 /**
02992   * @brief  DMA SPI Rx communication abort callback, when initiated by user
02993   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02994   * @note   When this callback is executed, User Abort complete call back is called only if no
02995   *         Abort still ongoing for Tx DMA Handle.
02996   * @param  hdma DMA handle.
02997   * @retval None
02998   */
02999 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
03000 {
03001   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03002
03003   /* Disable SPI Peripheral */
03004   __HAL_SPI_DISABLE(hspi);
03005
03006   hspi->hdmarx->XferAbortCallback = NULL;
03007
03008   /* Disable Rx DMA Request */
03009   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
03010
03011   /* Control the BSY flag */
03012   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03013   {
03014     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03015   }
03016
03017   /* Empty the FRLVL fifo */
03018   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03019   {
03020     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03021   }
03022
03023   /* Check if an Abort process is still ongoing */
03024   if (hspi->hdmatx != NULL)
03025   {
03026     if (hspi->hdmatx->XferAbortCallback != NULL)
03027     {
03028       return;
03029     }
03030   }
03031
03032   /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
03033   hspi->RxXferCount = 0U;
03034   hspi->TxXferCount = 0U;
03035
03036   /* Check no error during Abort procedure */
03037   if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
03038   {
03039     /* Reset errorCode */
03040     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
03041   }
03042
03043   /* Clear the Error flags in the SR register */
03044   __HAL_SPI_CLEAR_OVRFLAG(hspi);
03045   __HAL_SPI_CLEAR_FREFLAG(hspi);
03046
03047   /* Restore hspi->State to Ready */
03048   hspi->State  = HAL_SPI_STATE_READY;
03049
03050   /* Call user Abort complete callback */
03051   HAL_SPI_AbortCpltCallback(hspi);
03052 }
03053
03054 /**
03055   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
03056   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03057   *               the configuration information for SPI module.
03058   * @retval None
03059   */
03060 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03061 {
03062   /* Receive data in packing mode */
03063   if (hspi->RxXferCount > 1U)
03064   {
03065     *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
03066     hspi->pRxBuffPtr += sizeof(uint16_t);
03067     hspi->RxXferCount -= 2U;
03068     if (hspi->RxXferCount == 1U)
03069     {
03070       /* set fiforxthresold according the reception data length: 8bit */
03071       SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
03072     }
03073   }
03074   /* Receive data in 8 Bit mode */
03075   else
03076   {
03077     *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
03078     hspi->RxXferCount--;
03079   }
03080
03081   /* check end of the reception */
03082   if (hspi->RxXferCount == 0U)
03083   {
03084 #if (USE_SPI_CRC != 0U)
03085     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03086     {
03087       SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
03088       hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
03089       return;
03090     }
03091 #endif /* USE_SPI_CRC */
03092
03093     /* Disable RXNE  and ERR interrupt */
03094     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
03095
03096     if (hspi->TxXferCount == 0U)
03097     {
03098       SPI_CloseRxTx_ISR(hspi);
03099     }
03100   }
03101 }
03102
03103 #if (USE_SPI_CRC != 0U)
03104 /**
03105   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
03106   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03107   *               the configuration information for SPI module.
03108   * @retval None
03109   */
03110 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
03111 {
03112   __IO uint8_t tmpreg = 0U;
03113
03114   /* Read data register to flush CRC */
03115   tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
03116
03117   /* To avoid GCC warning */
03118   UNUSED(tmpreg);
03119
03120   hspi->CRCSize--;
03121
03122   /* check end of the reception */
03123   if (hspi->CRCSize == 0U)
03124   {
03125     /* Disable RXNE and ERR interrupt */
03126     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
03127
03128     if (hspi->TxXferCount == 0U)
03129     {
03130       SPI_CloseRxTx_ISR(hspi);
03131     }
03132   }
03133 }
03134 #endif /* USE_SPI_CRC */
03135
03136 /**
03137   * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
03138   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03139   *               the configuration information for SPI module.
03140   * @retval None
03141   */
03142 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03143 {
03144   /* Transmit data in packing Bit mode */
03145   if (hspi->TxXferCount >= 2U)
03146   {
03147     hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
03148     hspi->pTxBuffPtr += sizeof(uint16_t);
03149     hspi->TxXferCount -= 2U;
03150   }
03151   /* Transmit data in 8 Bit mode */
03152   else
03153   {
03154     *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
03155     hspi->TxXferCount--;
03156   }
03157
03158   /* check the end of the transmission */
03159   if (hspi->TxXferCount == 0U)
03160   {
03161 #if (USE_SPI_CRC != 0U)
03162     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03163     {
03164       /* Set CRC Next Bit to send CRC */
03165       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03166       /* Disable TXE interrupt */
03167       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03168       return;
03169     }
03170 #endif /* USE_SPI_CRC */
03171
03172     /* Disable TXE interrupt */
03173     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03174
03175     if (hspi->RxXferCount == 0U)
03176     {
03177       SPI_CloseRxTx_ISR(hspi);
03178     }
03179   }
03180 }
03181
03182 /**
03183   * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
03184   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03185   *               the configuration information for SPI module.
03186   * @retval None
03187   */
03188 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03189 {
03190   /* Receive data in 16 Bit mode */
03191   *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
03192   hspi->pRxBuffPtr += sizeof(uint16_t);
03193   hspi->RxXferCount--;
03194
03195   if (hspi->RxXferCount == 0U)
03196   {
03197 #if (USE_SPI_CRC != 0U)
03198     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03199     {
03200       hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
03201       return;
03202     }
03203 #endif /* USE_SPI_CRC */
03204
03205     /* Disable RXNE interrupt */
03206     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
03207
03208     if (hspi->TxXferCount == 0U)
03209     {
03210       SPI_CloseRxTx_ISR(hspi);
03211     }
03212   }
03213 }
03214
03215 #if (USE_SPI_CRC != 0U)
03216 /**
03217   * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
03218   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03219   *               the configuration information for SPI module.
03220   * @retval None
03221   */
03222 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
03223 {
03224   /* Receive data in 16 Bit mode */
03225   __IO uint16_t tmpreg = 0U;
03226
03227   /* Read data register to flush CRC */
03228   tmpreg = hspi->Instance->DR;
03229
03230   /* To avoid GCC warning */
03231   UNUSED(tmpreg);
03232
03233   /* Disable RXNE interrupt */
03234   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
03235
03236   SPI_CloseRxTx_ISR(hspi);
03237 }
03238 #endif /* USE_SPI_CRC */
03239
03240 /**
03241   * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
03242   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03243   *               the configuration information for SPI module.
03244   * @retval None
03245   */
03246 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03247 {
03248   /* Transmit data in 16 Bit mode */
03249   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
03250   hspi->pTxBuffPtr += sizeof(uint16_t);
03251   hspi->TxXferCount--;
03252
03253   /* Enable CRC Transmission */
03254   if (hspi->TxXferCount == 0U)
03255   {
03256 #if (USE_SPI_CRC != 0U)
03257     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03258     {
03259       /* Set CRC Next Bit to send CRC */
03260       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03261       /* Disable TXE interrupt */
03262       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03263       return;
03264     }
03265 #endif /* USE_SPI_CRC */
03266
03267     /* Disable TXE interrupt */
03268     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03269
03270     if (hspi->RxXferCount == 0U)
03271     {
03272       SPI_CloseRxTx_ISR(hspi);
03273     }
03274   }
03275 }
03276
03277 #if (USE_SPI_CRC != 0U)
03278 /**
03279   * @brief  Manage the CRC 8-bit receive in Interrupt context.
03280   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03281   *               the configuration information for SPI module.
03282   * @retval None
03283   */
03284 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
03285 {
03286   __IO uint8_t tmpreg = 0U;
03287
03288   /* Read data register to flush CRC */
03289   tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
03290
03291   /* To avoid GCC warning */
03292   UNUSED(tmpreg);
03293
03294   hspi->CRCSize--;
03295
03296   if (hspi->CRCSize == 0U)
03297   {
03298     SPI_CloseRx_ISR(hspi);
03299   }
03300 }
03301 #endif /* USE_SPI_CRC */
03302
03303 /**
03304   * @brief  Manage the receive 8-bit in Interrupt context.
03305   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03306   *               the configuration information for SPI module.
03307   * @retval None
03308   */
03309 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03310 {
03311   *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
03312   hspi->RxXferCount--;
03313
03314 #if (USE_SPI_CRC != 0U)
03315   /* Enable CRC Transmission */
03316   if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
03317   {
03318     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03319   }
03320 #endif /* USE_SPI_CRC */
03321
03322   if (hspi->RxXferCount == 0U)
03323   {
03324 #if (USE_SPI_CRC != 0U)
03325     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03326     {
03327       hspi->RxISR =  SPI_RxISR_8BITCRC;
03328       return;
03329     }
03330 #endif /* USE_SPI_CRC */
03331     SPI_CloseRx_ISR(hspi);
03332   }
03333 }
03334
03335 #if (USE_SPI_CRC != 0U)
03336 /**
03337   * @brief  Manage the CRC 16-bit receive in Interrupt context.
03338   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03339   *               the configuration information for SPI module.
03340   * @retval None
03341   */
03342 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
03343 {
03344   __IO uint16_t tmpreg = 0U;
03345
03346   /* Read data register to flush CRC */
03347   tmpreg = hspi->Instance->DR;
03348
03349   /* To avoid GCC warning */
03350   UNUSED(tmpreg);
03351
03352   /* Disable RXNE and ERR interrupt */
03353   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
03354
03355   SPI_CloseRx_ISR(hspi);
03356 }
03357 #endif /* USE_SPI_CRC */
03358
03359 /**
03360   * @brief  Manage the 16-bit receive in Interrupt context.
03361   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03362   *               the configuration information for SPI module.
03363   * @retval None
03364   */
03365 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03366 {
03367   *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
03368   hspi->pRxBuffPtr += sizeof(uint16_t);
03369   hspi->RxXferCount--;
03370
03371 #if (USE_SPI_CRC != 0U)
03372   /* Enable CRC Transmission */
03373   if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
03374   {
03375     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03376   }
03377 #endif /* USE_SPI_CRC */
03378
03379   if (hspi->RxXferCount == 0U)
03380   {
03381 #if (USE_SPI_CRC != 0U)
03382     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03383     {
03384       hspi->RxISR = SPI_RxISR_16BITCRC;
03385       return;
03386     }
03387 #endif /* USE_SPI_CRC */
03388     SPI_CloseRx_ISR(hspi);
03389   }
03390 }
03391
03392 /**
03393   * @brief  Handle the data 8-bit transmit in Interrupt mode.
03394   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03395   *               the configuration information for SPI module.
03396   * @retval None
03397   */
03398 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03399 {
03400   *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
03401   hspi->TxXferCount--;
03402
03403   if (hspi->TxXferCount == 0U)
03404   {
03405 #if (USE_SPI_CRC != 0U)
03406     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03407     {
03408       /* Enable CRC Transmission */
03409       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03410     }
03411 #endif /* USE_SPI_CRC */
03412     SPI_CloseTx_ISR(hspi);
03413   }
03414 }
03415
03416 /**
03417   * @brief  Handle the data 16-bit transmit in Interrupt mode.
03418   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03419   *               the configuration information for SPI module.
03420   * @retval None
03421   */
03422 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03423 {
03424   /* Transmit data in 16 Bit mode */
03425   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
03426   hspi->pTxBuffPtr += sizeof(uint16_t);
03427   hspi->TxXferCount--;
03428
03429   if (hspi->TxXferCount == 0U)
03430   {
03431 #if (USE_SPI_CRC != 0U)
03432     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03433     {
03434       /* Enable CRC Transmission */
03435       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03436     }
03437 #endif /* USE_SPI_CRC */
03438     SPI_CloseTx_ISR(hspi);
03439   }
03440 }
03441
03442 /**
03443   * @brief Handle SPI Communication Timeout.
03444   * @param hspi pointer to a SPI_HandleTypeDef structure that contains
03445   *              the configuration information for SPI module.
03446   * @param Flag SPI flag to check
03447   * @param State flag state to check
03448   * @param Timeout Timeout duration
03449   * @param Tickstart tick start value
03450   * @retval HAL status
03451   */
03452 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
03453                                                        uint32_t Timeout, uint32_t Tickstart)
03454 {
03455   while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
03456   {
03457     if (Timeout != HAL_MAX_DELAY)
03458     {
03459       if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
03460       {
03461         /* Disable the SPI and reset the CRC: the CRC value should be cleared
03462         on both master and slave sides in order to resynchronize the master
03463         and slave for their respective CRC calculation */
03464
03465         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
03466         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
03467
03468         if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
03469                                                      || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
03470         {
03471           /* Disable SPI peripheral */
03472           __HAL_SPI_DISABLE(hspi);
03473         }
03474
03475         /* Reset CRC Calculation */
03476         if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03477         {
03478           SPI_RESET_CRC(hspi);
03479         }
03480
03481         hspi->State = HAL_SPI_STATE_READY;
03482
03483         /* Process Unlocked */
03484         __HAL_UNLOCK(hspi);
03485
03486         return HAL_TIMEOUT;
03487       }
03488     }
03489   }
03490
03491   return HAL_OK;
03492 }
03493
03494 /**
03495   * @brief Handle SPI FIFO Communication Timeout.
03496   * @param hspi pointer to a SPI_HandleTypeDef structure that contains
03497   *              the configuration information for SPI module.
03498   * @param Fifo Fifo to check
03499   * @param State Fifo state to check
03500   * @param Timeout Timeout duration
03501   * @param Tickstart tick start value
03502   * @retval HAL status
03503   */
03504 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
03505                                                        uint32_t Timeout, uint32_t Tickstart)
03506 {
03507   __IO uint8_t tmpreg;
03508
03509   while ((hspi->Instance->SR & Fifo) != State)
03510   {
03511     if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
03512     {
03513       tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
03514       /* To avoid GCC warning */
03515       UNUSED(tmpreg);
03516     }
03517
03518     if (Timeout != HAL_MAX_DELAY)
03519     {
03520       if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
03521       {
03522         /* Disable the SPI and reset the CRC: the CRC value should be cleared
03523            on both master and slave sides in order to resynchronize the master
03524            and slave for their respective CRC calculation */
03525
03526         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
03527         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
03528
03529         if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
03530                                                      || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
03531         {
03532           /* Disable SPI peripheral */
03533           __HAL_SPI_DISABLE(hspi);
03534         }
03535
03536         /* Reset CRC Calculation */
03537         if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03538         {
03539           SPI_RESET_CRC(hspi);
03540         }
03541
03542         hspi->State = HAL_SPI_STATE_READY;
03543
03544         /* Process Unlocked */
03545         __HAL_UNLOCK(hspi);
03546
03547         return HAL_TIMEOUT;
03548       }
03549     }
03550   }
03551
03552   return HAL_OK;
03553 }
03554
03555 /**
03556   * @brief  Handle the check of the RX transaction complete.
03557   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03558   *               the configuration information for SPI module.
03559   * @param  Timeout Timeout duration
03560   * @param  Tickstart tick start value
03561   * @retval HAL status
03562   */
03563 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)
03564 {
03565   if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
03566                                                || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
03567   {
03568     /* Disable SPI peripheral */
03569     __HAL_SPI_DISABLE(hspi);
03570   }
03571
03572   /* Control the BSY flag */
03573   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
03574   {
03575     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03576     return HAL_TIMEOUT;
03577   }
03578
03579   if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
03580                                                || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
03581   {
03582     /* Empty the FRLVL fifo */
03583     if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
03584     {
03585       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03586       return HAL_TIMEOUT;
03587     }
03588   }
03589   return HAL_OK;
03590 }
03591
03592 /**
03593   * @brief  Handle the check of the RXTX or TX transaction complete.
03594   * @param  hspi SPI handle
03595   * @param  Timeout Timeout duration
03596   * @param  Tickstart tick start value
03597   * @retval HAL status
03598   */
03599 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
03600 {
03601   /* Control if the TX fifo is empty */
03602   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
03603   {
03604     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03605     return HAL_TIMEOUT;
03606   }
03607
03608   /* Control the BSY flag */
03609   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
03610   {
03611     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03612     return HAL_TIMEOUT;
03613   }
03614
03615   /* Control if the RX fifo is empty */
03616   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
03617   {
03618     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03619     return HAL_TIMEOUT;
03620   }
03621   return HAL_OK;
03622 }
03623
03624 /**
03625   * @brief  Handle the end of the RXTX transaction.
03626   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03627   *               the configuration information for SPI module.
03628   * @retval None
03629   */
03630 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
03631 {
03632   uint32_t tickstart = 0U;
03633
03634   /* Init tickstart for timeout managment*/
03635   tickstart = HAL_GetTick();
03636
03637   /* Disable ERR interrupt */
03638   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
03639
03640   /* Check the end of the transaction */
03641   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03642   {
03643     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03644   }
03645
03646 #if (USE_SPI_CRC != 0U)
03647   /* Check if CRC error occurred */
03648   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
03649   {
03650     hspi->State = HAL_SPI_STATE_READY;
03651     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03652     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
03653     HAL_SPI_ErrorCallback(hspi);
03654   }
03655   else
03656   {
03657 #endif /* USE_SPI_CRC */
03658     if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
03659     {
03660       if (hspi->State == HAL_SPI_STATE_BUSY_RX)
03661       {
03662         hspi->State = HAL_SPI_STATE_READY;
03663         HAL_SPI_RxCpltCallback(hspi);
03664       }
03665       else
03666       {
03667         hspi->State = HAL_SPI_STATE_READY;
03668         HAL_SPI_TxRxCpltCallback(hspi);
03669       }
03670     }
03671     else
03672     {
03673       hspi->State = HAL_SPI_STATE_READY;
03674       HAL_SPI_ErrorCallback(hspi);
03675     }
03676 #if (USE_SPI_CRC != 0U)
03677   }
03678 #endif /* USE_SPI_CRC */
03679 }
03680
03681 /**
03682   * @brief  Handle the end of the RX transaction.
03683   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03684   *               the configuration information for SPI module.
03685   * @retval None
03686   */
03687 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
03688 {
03689   /* Disable RXNE and ERR interrupt */
03690   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
03691
03692   /* Check the end of the transaction */
03693   if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03694   {
03695     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03696   }
03697   hspi->State = HAL_SPI_STATE_READY;
03698
03699 #if (USE_SPI_CRC != 0U)
03700   /* Check if CRC error occurred */
03701   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
03702   {
03703     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03704     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
03705     HAL_SPI_ErrorCallback(hspi);
03706   }
03707   else
03708   {
03709 #endif /* USE_SPI_CRC */
03710     if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
03711     {
03712       HAL_SPI_RxCpltCallback(hspi);
03713     }
03714     else
03715     {
03716       HAL_SPI_ErrorCallback(hspi);
03717     }
03718 #if (USE_SPI_CRC != 0U)
03719   }
03720 #endif /* USE_SPI_CRC */
03721 }
03722
03723 /**
03724   * @brief  Handle the end of the TX transaction.
03725   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03726   *               the configuration information for SPI module.
03727   * @retval None
03728   */
03729 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
03730 {
03731   uint32_t tickstart = 0U;
03732
03733   /* Init tickstart for timeout management*/
03734   tickstart = HAL_GetTick();
03735
03736   /* Disable TXE and ERR interrupt */
03737   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
03738
03739   /* Check the end of the transaction */
03740   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03741   {
03742     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03743   }
03744
03745   /* Clear overrun flag in 2 Lines communication mode because received is not read */
03746   if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
03747   {
03748     __HAL_SPI_CLEAR_OVRFLAG(hspi);
03749   }
03750
03751   hspi->State = HAL_SPI_STATE_READY;
03752   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
03753   {
03754     HAL_SPI_ErrorCallback(hspi);
03755   }
03756   else
03757   {
03758     HAL_SPI_TxCpltCallback(hspi);
03759   }
03760 }
03761
03762 /**
03763   * @brief  Handle abort a Rx transaction.
03764   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03765   *               the configuration information for SPI module.
03766   * @retval None
03767   */
03768 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
03769 {
03770   __IO uint32_t count;
03771
03772   /* Disable SPI Peripheral */
03773   __HAL_SPI_DISABLE(hspi);
03774
03775   count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
03776
03777   /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
03778   CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
03779
03780   /* Check RXNEIE is disabled */
03781   do
03782   {
03783     if (count-- == 0U)
03784     {
03785       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
03786       break;
03787     }
03788   }
03789   while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
03790
03791   /* Control the BSY flag */
03792   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03793   {
03794     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03795   }
03796
03797   /* Empty the FRLVL fifo */
03798   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03799   {
03800     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03801   }
03802
03803   hspi->State = HAL_SPI_STATE_ABORT;
03804 }
03805
03806 /**
03807   * @brief  Handle abort a Tx or Rx/Tx transaction.
03808   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03809   *               the configuration information for SPI module.
03810   * @retval None
03811   */
03812 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
03813 {
03814   __IO uint32_t count;
03815
03816   count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
03817
03818   /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
03819   CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
03820
03821   /* Check TXEIE is disabled */
03822   do
03823   {
03824     if (count-- == 0U)
03825     {
03826       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
03827       break;
03828     }
03829   }
03830   while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
03831
03832   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03833   {
03834     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03835   }
03836
03837   /* Disable SPI Peripheral */
03838   __HAL_SPI_DISABLE(hspi);
03839
03840   /* Empty the FRLVL fifo */
03841   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03842   {
03843     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03844   }
03845
03846   hspi->State = HAL_SPI_STATE_ABORT;
03847 }
03848
03849 /**
03850   * @}
03851   */
03852
03853 #endif /* HAL_SPI_MODULE_ENABLED */
03854
03855 /**
03856   * @}
03857   */
03858
03859 /**
03860   * @}
03861   */
03862
03863 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_spi.h Source File

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stm32f3xx_hal_spi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_spi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SPI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_SPI_H
00038 #define __STM32F3xx_HAL_SPI_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup SPI
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /** @defgroup SPI_Exported_Types SPI Exported Types
00057   * @{
00058   */
00059
00060 /**
00061   * @brief  SPI Configuration Structure definition
00062   */
00063 typedef struct
00064 {
00065   uint32_t Mode;                /*!< Specifies the SPI operating mode.
00066                                      This parameter can be a value of @ref SPI_Mode */
00067
00068   uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
00069                                      This parameter can be a value of @ref SPI_Direction */
00070
00071   uint32_t DataSize;            /*!< Specifies the SPI data size.
00072                                      This parameter can be a value of @ref SPI_Data_Size */
00073
00074   uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
00075                                      This parameter can be a value of @ref SPI_Clock_Polarity */
00076
00077   uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
00078                                      This parameter can be a value of @ref SPI_Clock_Phase */
00079
00080   uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
00081                                      hardware (NSS pin) or by software using the SSI bit.
00082                                      This parameter can be a value of @ref SPI_Slave_Select_management */
00083
00084   uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
00085                                      used to configure the transmit and receive SCK clock.
00086                                      This parameter can be a value of @ref SPI_BaudRate_Prescaler
00087                                      @note The communication clock is derived from the master
00088                                      clock. The slave clock does not need to be set. */
00089
00090   uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
00091                                      This parameter can be a value of @ref SPI_MSB_LSB_transmission */
00092
00093   uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.
00094                                      This parameter can be a value of @ref SPI_TI_mode */
00095
00096   uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
00097                                      This parameter can be a value of @ref SPI_CRC_Calculation */
00098
00099   uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
00100                                      This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
00101
00102   uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.
00103                                      CRC Length is only used with Data8 and Data16, not other data size
00104                                      This parameter can be a value of @ref SPI_CRC_length */
00105
00106   uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .
00107                                      This parameter can be a value of @ref SPI_NSSP_Mode
00108                                      This mode is activated by the NSSP bit in the SPIx_CR2 register and
00109                                      it takes effect only if the SPI interface is configured as Motorola SPI
00110                                      master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
00111                                      CPOL setting is ignored).. */
00112 } SPI_InitTypeDef;
00113
00114 /**
00115   * @brief  HAL SPI State structure definition
00116   */
00117 typedef enum
00118 {
00119   HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
00120   HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
00121   HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
00122   HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
00123   HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
00124   HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
00125   HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */
00126   HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */
00127 } HAL_SPI_StateTypeDef;
00128
00129 /**
00130   * @brief  SPI handle Structure definition
00131   */
00132 typedef struct __SPI_HandleTypeDef
00133 {
00134   SPI_TypeDef                *Instance;      /*!< SPI registers base address               */
00135
00136   SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */
00137
00138   uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */
00139
00140   uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */
00141
00142   __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */
00143
00144   uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */
00145
00146   uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */
00147
00148   __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */
00149
00150   uint32_t                   CRCSize;        /*!< SPI CRC size used for the transfer       */
00151
00152   void (*RxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Rx ISR       */
00153
00154   void (*TxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Tx ISR       */
00155
00156   DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */
00157
00158   DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */
00159
00160   HAL_LockTypeDef            Lock;           /*!< Locking object                           */
00161
00162   __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */
00163
00164   __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */
00165
00166 } SPI_HandleTypeDef;
00167
00168 /**
00169   * @}
00170   */
00171
00172 /* Exported constants --------------------------------------------------------*/
00173 /** @defgroup SPI_Exported_Constants SPI Exported Constants
00174   * @{
00175   */
00176
00177 /** @defgroup SPI_Error_Code SPI Error Code
00178   * @{
00179   */
00180 #define HAL_SPI_ERROR_NONE              (0x00000000U)   /*!< No error                               */
00181 #define HAL_SPI_ERROR_MODF              (0x00000001U)   /*!< MODF error                             */
00182 #define HAL_SPI_ERROR_CRC               (0x00000002U)   /*!< CRC error                              */
00183 #define HAL_SPI_ERROR_OVR               (0x00000004U)   /*!< OVR error                              */
00184 #define HAL_SPI_ERROR_FRE               (0x00000008U)   /*!< FRE error                              */
00185 #define HAL_SPI_ERROR_DMA               (0x00000010U)   /*!< DMA transfer error                     */
00186 #define HAL_SPI_ERROR_FLAG              (0x00000020U)   /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
00187 #define HAL_SPI_ERROR_ABORT             (0x00000040U)   /*!< Error during SPI Abort procedure       */
00188 /**
00189   * @}
00190   */
00191
00192 /** @defgroup SPI_Mode SPI Mode
00193   * @{
00194   */
00195 #define SPI_MODE_SLAVE                  (0x00000000U)
00196 #define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup SPI_Direction SPI Direction Mode
00202   * @{
00203   */
00204 #define SPI_DIRECTION_2LINES            (0x00000000U)
00205 #define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
00206 #define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup SPI_Data_Size SPI Data Size
00212   * @{
00213   */
00214 #define SPI_DATASIZE_4BIT               (0x00000300U)
00215 #define SPI_DATASIZE_5BIT               (0x00000400U)
00216 #define SPI_DATASIZE_6BIT               (0x00000500U)
00217 #define SPI_DATASIZE_7BIT               (0x00000600U)
00218 #define SPI_DATASIZE_8BIT               (0x00000700U)
00219 #define SPI_DATASIZE_9BIT               (0x00000800U)
00220 #define SPI_DATASIZE_10BIT              (0x00000900U)
00221 #define SPI_DATASIZE_11BIT              (0x00000A00U)
00222 #define SPI_DATASIZE_12BIT              (0x00000B00U)
00223 #define SPI_DATASIZE_13BIT              (0x00000C00U)
00224 #define SPI_DATASIZE_14BIT              (0x00000D00U)
00225 #define SPI_DATASIZE_15BIT              (0x00000E00U)
00226 #define SPI_DATASIZE_16BIT              (0x00000F00U)
00227 /**
00228   * @}
00229   */
00230
00231 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
00232   * @{
00233   */
00234 #define SPI_POLARITY_LOW                (0x00000000U)
00235 #define SPI_POLARITY_HIGH               SPI_CR1_CPOL
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup SPI_Clock_Phase SPI Clock Phase
00241   * @{
00242   */
00243 #define SPI_PHASE_1EDGE                 (0x00000000U)
00244 #define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
00250   * @{
00251   */
00252 #define SPI_NSS_SOFT                    SPI_CR1_SSM
00253 #define SPI_NSS_HARD_INPUT              (0x00000000U)
00254 #define SPI_NSS_HARD_OUTPUT             (SPI_CR2_SSOE << 16U)
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
00260   * @{
00261   */
00262 #define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP
00263 #define SPI_NSS_PULSE_DISABLE           (0x00000000U)
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
00269   * @{
00270   */
00271 #define SPI_BAUDRATEPRESCALER_2         (0x00000000U)
00272 #define SPI_BAUDRATEPRESCALER_4         (SPI_CR1_BR_0)
00273 #define SPI_BAUDRATEPRESCALER_8         (SPI_CR1_BR_1)
00274 #define SPI_BAUDRATEPRESCALER_16        (SPI_CR1_BR_1 | SPI_CR1_BR_0)
00275 #define SPI_BAUDRATEPRESCALER_32        (SPI_CR1_BR_2)
00276 #define SPI_BAUDRATEPRESCALER_64        (SPI_CR1_BR_2 | SPI_CR1_BR_0)
00277 #define SPI_BAUDRATEPRESCALER_128       (SPI_CR1_BR_2 | SPI_CR1_BR_1)
00278 #define SPI_BAUDRATEPRESCALER_256       (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
00284   * @{
00285   */
00286 #define SPI_FIRSTBIT_MSB                (0x00000000U)
00287 #define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup SPI_TI_mode SPI TI Mode
00293   * @{
00294   */
00295 #define SPI_TIMODE_DISABLE              (0x00000000U)
00296 #define SPI_TIMODE_ENABLE               SPI_CR2_FRF
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
00302   * @{
00303   */
00304 #define SPI_CRCCALCULATION_DISABLE      (0x00000000U)
00305 #define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
00306 /**
00307   * @}
00308   */
00309
00310 /** @defgroup SPI_CRC_length SPI CRC Length
00311   * @{
00312   * This parameter can be one of the following values:
00313   *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size
00314   *     SPI_CRC_LENGTH_8BIT    : CRC 8bit
00315   *     SPI_CRC_LENGTH_16BIT   : CRC 16bit
00316   */
00317 #define SPI_CRC_LENGTH_DATASIZE         (0x00000000U)
00318 #define SPI_CRC_LENGTH_8BIT             (0x00000001U)
00319 #define SPI_CRC_LENGTH_16BIT            (0x00000002U)
00320 /**
00321   * @}
00322   */
00323
00324 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
00325   * @{
00326   * This parameter can be one of the following values:
00327   *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
00328   *          RXNE event is generated if the FIFO
00329   *          level is greater or equal to 1/2(16-bits).
00330   *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
00331   *          level is greater or equal to 1/4(8 bits). */
00332 #define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH
00333 #define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH
00334 #define SPI_RXFIFO_THRESHOLD_HF         (0x00000000U)
00335
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
00341   * @{
00342   */
00343 #define SPI_IT_TXE                      SPI_CR2_TXEIE
00344 #define SPI_IT_RXNE                     SPI_CR2_RXNEIE
00345 #define SPI_IT_ERR                      SPI_CR2_ERRIE
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup SPI_Flags_definition SPI Flags Definition
00351   * @{
00352   */
00353 #define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */
00354 #define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */
00355 #define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */
00356 #define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */
00357 #define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */
00358 #define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */
00359 #define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
00360 #define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level                     */
00361 #define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level                        */
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
00367   * @{
00368   */
00369 #define SPI_FTLVL_EMPTY                 (0x00000000U)
00370 #define SPI_FTLVL_QUARTER_FULL          (0x00000800U)
00371 #define SPI_FTLVL_HALF_FULL             (0x00001000U)
00372 #define SPI_FTLVL_FULL                  (0x00001800U)
00373
00374 /**
00375   * @}
00376   */
00377
00378 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
00379   * @{
00380   */
00381 #define SPI_FRLVL_EMPTY                 (0x00000000U)
00382 #define SPI_FRLVL_QUARTER_FULL          (0x00000200U)
00383 #define SPI_FRLVL_HALF_FULL             (0x00000400U)
00384 #define SPI_FRLVL_FULL                  (0x00000600U)
00385 /**
00386   * @}
00387   */
00388
00389 /**
00390   * @}
00391   */
00392
00393 /* Exported macros -----------------------------------------------------------*/
00394 /** @defgroup SPI_Exported_Macros SPI Exported Macros
00395   * @{
00396   */
00397
00398 /** @brief  Reset SPI handle state.
00399   * @param  __HANDLE__ specifies the SPI Handle.
00400   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00401   * @retval None
00402   */
00403 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
00404
00405 /** @brief  Enable the specified SPI interrupts.
00406   * @param  __HANDLE__ specifies the SPI Handle.
00407   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00408   * @param  __INTERRUPT__ specifies the interrupt source to enable.
00409   *         This parameter can be one of the following values:
00410   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00411   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00412   *            @arg SPI_IT_ERR: Error interrupt enable
00413   * @retval None
00414   */
00415 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
00416
00417 /** @brief  Disable the specified SPI interrupts.
00418   * @param  __HANDLE__ specifies the SPI handle.
00419   *         This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
00420   * @param  __INTERRUPT__ specifies the interrupt source to disable.
00421   *         This parameter can be one of the following values:
00422   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00423   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00424   *            @arg SPI_IT_ERR: Error interrupt enable
00425   * @retval None
00426   */
00427 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
00428
00429 /** @brief  Check whether the specified SPI interrupt source is enabled or not.
00430   * @param  __HANDLE__ specifies the SPI Handle.
00431   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00432   * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
00433   *          This parameter can be one of the following values:
00434   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00435   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00436   *            @arg SPI_IT_ERR: Error interrupt enable
00437   * @retval The new state of __IT__ (TRUE or FALSE).
00438   */
00439 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00440
00441 /** @brief  Check whether the specified SPI flag is set or not.
00442   * @param  __HANDLE__ specifies the SPI Handle.
00443   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00444   * @param  __FLAG__ specifies the flag to check.
00445   *         This parameter can be one of the following values:
00446   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
00447   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
00448   *            @arg SPI_FLAG_CRCERR: CRC error flag
00449   *            @arg SPI_FLAG_MODF: Mode fault flag
00450   *            @arg SPI_FLAG_OVR: Overrun flag
00451   *            @arg SPI_FLAG_BSY: Busy flag
00452   *            @arg SPI_FLAG_FRE: Frame format error flag
00453   *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
00454   *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
00455   * @retval The new state of __FLAG__ (TRUE or FALSE).
00456   */
00457 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00458
00459 /** @brief  Clear the SPI CRCERR pending flag.
00460   * @param  __HANDLE__ specifies the SPI Handle.
00461   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00462   * @retval None
00463   */
00464 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
00465
00466 /** @brief  Clear the SPI MODF pending flag.
00467   * @param  __HANDLE__ specifies the SPI Handle.
00468   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00469   * @retval None
00470   */
00471 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)             \
00472   do{                                                    \
00473     __IO uint32_t tmpreg_modf = 0x00U;                   \
00474     tmpreg_modf = (__HANDLE__)->Instance->SR;            \
00475     CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
00476     UNUSED(tmpreg_modf);                                 \
00477   } while(0U)
00478
00479 /** @brief  Clear the SPI OVR pending flag.
00480   * @param  __HANDLE__ specifies the SPI Handle.
00481   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00482   * @retval None
00483   */
00484 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
00485   do{                                              \
00486     __IO uint32_t tmpreg_ovr = 0x00U;              \
00487     tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
00488     tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
00489     UNUSED(tmpreg_ovr);                            \
00490   } while(0U)
00491
00492 /** @brief  Clear the SPI FRE pending flag.
00493   * @param  __HANDLE__ specifies the SPI Handle.
00494   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00495   * @retval None
00496   */
00497 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \
00498   do{                                              \
00499   __IO uint32_t tmpreg_fre = 0x00U;                \
00500   tmpreg_fre = (__HANDLE__)->Instance->SR;         \
00501   UNUSED(tmpreg_fre);                              \
00502   }while(0U)
00503
00504 /** @brief  Enable the SPI peripheral.
00505   * @param  __HANDLE__ specifies the SPI Handle.
00506   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00507   * @retval None
00508   */
00509 #define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
00510
00511 /** @brief  Disable the SPI peripheral.
00512   * @param  __HANDLE__ specifies the SPI Handle.
00513   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00514   * @retval None
00515   */
00516 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
00517
00518 /**
00519   * @}
00520   */
00521
00522 /* Private macros ------------------------------------------------------------*/
00523 /** @defgroup SPI_Private_Macros SPI Private Macros
00524   * @{
00525   */
00526
00527 /** @brief  Set the SPI transmit-only mode.
00528   * @param  __HANDLE__ specifies the SPI Handle.
00529   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00530   * @retval None
00531   */
00532 #define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
00533
00534 /** @brief  Set the SPI receive-only mode.
00535   * @param  __HANDLE__ specifies the SPI Handle.
00536   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00537   * @retval None
00538   */
00539 #define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
00540
00541 /** @brief  Reset the CRC calculation of the SPI.
00542   * @param  __HANDLE__ specifies the SPI Handle.
00543   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00544   * @retval None
00545   */
00546 #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
00547                                        SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
00548
00549 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
00550                            ((MODE) == SPI_MODE_MASTER))
00551
00552 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES)        || \
00553                                 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
00554                                 ((MODE) == SPI_DIRECTION_1LINE))
00555
00556 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
00557
00558 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
00559                                                 ((MODE) == SPI_DIRECTION_1LINE))
00560
00561 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
00562                                    ((DATASIZE) == SPI_DATASIZE_15BIT) || \
00563                                    ((DATASIZE) == SPI_DATASIZE_14BIT) || \
00564                                    ((DATASIZE) == SPI_DATASIZE_13BIT) || \
00565                                    ((DATASIZE) == SPI_DATASIZE_12BIT) || \
00566                                    ((DATASIZE) == SPI_DATASIZE_11BIT) || \
00567                                    ((DATASIZE) == SPI_DATASIZE_10BIT) || \
00568                                    ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
00569                                    ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
00570                                    ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
00571                                    ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
00572                                    ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
00573                                    ((DATASIZE) == SPI_DATASIZE_4BIT))
00574
00575 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
00576                            ((CPOL) == SPI_POLARITY_HIGH))
00577
00578 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
00579                            ((CPHA) == SPI_PHASE_2EDGE))
00580
00581 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \
00582                          ((NSS) == SPI_NSS_HARD_INPUT) || \
00583                          ((NSS) == SPI_NSS_HARD_OUTPUT))
00584
00585 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
00586                            ((NSSP) == SPI_NSS_PULSE_DISABLE))
00587
00588 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
00589                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
00590                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
00591                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
00592                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
00593                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
00594                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
00595                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
00596
00597 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
00598                                ((BIT) == SPI_FIRSTBIT_LSB))
00599
00600 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
00601                              ((MODE) == SPI_TIMODE_ENABLE))
00602
00603 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
00604                                              ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
00605
00606 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
00607                                    ((LENGTH) == SPI_CRC_LENGTH_8BIT)  ||   \
00608                                    ((LENGTH) == SPI_CRC_LENGTH_16BIT))
00609
00610 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
00611
00612 #define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL)
00613
00614
00615 /**
00616   * @}
00617   */
00618
00619 /* Include SPI HAL Extended module */
00620 #include "stm32f3xx_hal_spi_ex.h"
00621
00622 /* Exported functions --------------------------------------------------------*/
00623 /** @addtogroup SPI_Exported_Functions
00624   * @{
00625   */
00626
00627 /** @addtogroup SPI_Exported_Functions_Group1
00628   * @{
00629   */
00630 /* Initialization/de-initialization functions  ********************************/
00631 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
00632 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
00633 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
00634 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
00635 /**
00636   * @}
00637   */
00638
00639 /** @addtogroup SPI_Exported_Functions_Group2
00640   * @{
00641   */
00642 /* I/O operation functions  ***************************************************/
00643 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00644 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00645 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
00646                                           uint32_t Timeout);
00647 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00648 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00649 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
00650                                              uint16_t Size);
00651 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00652 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00653 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
00654                                               uint16_t Size);
00655 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
00656 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
00657 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
00658 /* Transfer Abort functions */
00659 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
00660 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
00661
00662 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
00663 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
00664 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
00665 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
00666 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00667 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00668 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00669 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
00670 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
00671 /**
00672   * @}
00673   */
00674
00675 /** @addtogroup SPI_Exported_Functions_Group3
00676   * @{
00677   */
00678 /* Peripheral State and Error functions ***************************************/
00679 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
00680 uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
00681 /**
00682   * @}
00683   */
00684
00685 /**
00686   * @}
00687   */
00688
00689 /**
00690   * @}
00691   */
00692
00693 /**
00694   * @}
00695   */
00696
00697 #ifdef __cplusplus
00698 }
00699 #endif
00700
00701 #endif /* __STM32F3xx_HAL_SPI_H */
00702
00703 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_spi_ex.c Source File

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stm32f3xx_hal_spi_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_spi_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended SPI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          SPI peripheral extended functionalities :
00008   *           + IO operation functions
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00014   *
00015   * Redistribution and use in source and binary forms, with or without modification,
00016   * are permitted provided that the following conditions are met:
00017   *   1. Redistributions of source code must retain the above copyright notice,
00018   *      this list of conditions and the following disclaimer.
00019   *   2. Redistributions in binary form must reproduce the above copyright notice,
00020   *      this list of conditions and the following disclaimer in the documentation
00021   *      and/or other materials provided with the distribution.
00022   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00023   *      may be used to endorse or promote products derived from this software
00024   *      without specific prior written permission.
00025   *
00026   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00027   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00028   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00029   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00030   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00031   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00032   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00033   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00034   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00035   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00036   *
00037   ******************************************************************************
00038   */
00039
00040 /* Includes ------------------------------------------------------------------*/
00041 #include "stm32f3xx_hal.h"
00042
00043 /** @addtogroup STM32F3xx_HAL_Driver
00044   * @{
00045   */
00046
00047 /** @defgroup SPIEx SPIEx
00048   * @brief SPI Extended HAL module driver
00049   * @{
00050   */
00051 #ifdef HAL_SPI_MODULE_ENABLED
00052
00053 /* Private typedef -----------------------------------------------------------*/
00054 /* Private defines -----------------------------------------------------------*/
00055 /** @defgroup SPIEx_Private_Constants SPIEx Private Constants
00056   * @{
00057   */
00058 #define SPI_FIFO_SIZE       4
00059 /**
00060   * @}
00061   */
00062
00063 /* Private macros ------------------------------------------------------------*/
00064 /* Private variables ---------------------------------------------------------*/
00065 /* Private function prototypes -----------------------------------------------*/
00066 /* Exported functions ---------------------------------------------------------*/
00067
00068 /** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
00069   * @{
00070   */
00071
00072 /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
00073   *  @brief   Data transfers functions
00074   *
00075 @verbatim
00076   ==============================================================================
00077                       ##### IO operation functions #####
00078  ===============================================================================
00079  [..]
00080     This subsection provides a set of extended functions to manage the SPI
00081     data transfers.
00082
00083     (#) Rx data flush function:
00084         (++) HAL_SPIEx_FlushRxFifo()
00085
00086 @endverbatim
00087   * @{
00088   */
00089
00090 /**
00091   * @brief Flush the RX fifo.
00092   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00093   *               the configuration information for the specified SPI module.
00094   * @retval HAL status
00095   */
00096 HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
00097 {
00098   __IO uint32_t tmpreg;
00099   uint8_t  count = 0U;
00100   while ((hspi->Instance->SR & SPI_FLAG_FRLVL) !=  SPI_FRLVL_EMPTY)
00101   {
00102     count++;
00103     tmpreg = hspi->Instance->DR;
00104     UNUSED(tmpreg); /* To avoid GCC warning */
00105     if (count == SPI_FIFO_SIZE)
00106     {
00107       return HAL_TIMEOUT;
00108     }
00109   }
00110   return HAL_OK;
00111 }
00112
00113 /**
00114   * @}
00115   */
00116
00117 /**
00118   * @}
00119   */
00120
00121 #endif /* HAL_SPI_MODULE_ENABLED */
00122
00123 /**
00124   * @}
00125   */
00126
00127 /**
00128   * @}
00129   */
00130
00131 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_spi_ex.h Source File

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stm32f3xx_hal_spi_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_spi_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SPI HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_SPI_EX_H
00038 #define __STM32F3xx_HAL_SPI_EX_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup SPIEx
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /* Exported constants --------------------------------------------------------*/
00057 /* Exported macros -----------------------------------------------------------*/
00058 /* Exported functions --------------------------------------------------------*/
00059 /** @addtogroup SPIEx_Exported_Functions
00060   * @{
00061   */
00062
00063 /* Initialization and de-initialization functions  ****************************/
00064 /* IO operation functions *****************************************************/
00065 /** @addtogroup SPIEx_Exported_Functions_Group1
00066   * @{
00067   */
00068 HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
00069 /**
00070   * @}
00071   */
00072
00073 /**
00074   * @}
00075   */
00076
00077 /**
00078   * @}
00079   */
00080
00081 /**
00082   * @}
00083   */
00084
00085 #ifdef __cplusplus
00086 }
00087 #endif
00088
00089 #endif /* __STM32F3xx_HAL_SPI_EX_H */
00090
00091 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_sram.c Source File

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stm32f3xx_hal_sram.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_sram.c
00004   * @author  MCD Application Team
00005   * @brief   SRAM HAL module driver.
00006   *          This file provides a generic firmware to drive SRAM memories
00007   *          mounted as external device.
00008   *
00009   @verbatim
00010   ==============================================================================
00011                           ##### How to use this driver #####
00012   ==============================================================================
00013   [..]
00014     This driver is a generic layered driver which contains a set of APIs used to
00015     control SRAM memories. It uses the FMC layer functions to interface
00016     with SRAM devices.
00017     The following sequence should be followed to configure the FMC to interface
00018     with SRAM/PSRAM memories:
00019
00020    (#) Declare a SRAM_HandleTypeDef handle structure, for example:
00021           SRAM_HandleTypeDef  hsram; and:
00022
00023        (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
00024             values of the structure member.
00025
00026        (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
00027             base register instance for NOR or SRAM device
00028
00029        (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
00030             base register instance for NOR or SRAM extended mode
00031
00032    (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
00033        mode timings; for example:
00034           FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
00035       and fill its fields with the allowed values of the structure member.
00036
00037    (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
00038        performs the following sequence:
00039
00040        (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
00041        (##) Control register configuration using the FMC NORSRAM interface function
00042             FMC_NORSRAM_Init()
00043        (##) Timing register configuration using the FMC NORSRAM interface function
00044             FMC_NORSRAM_Timing_Init()
00045        (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
00046             FMC_NORSRAM_Extended_Timing_Init()
00047        (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
00048
00049    (#) At this stage you can perform read/write accesses from/to the memory connected
00050        to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
00051        following APIs:
00052        (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
00053        (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
00054
00055    (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
00056        HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
00057
00058    (#) You can continuously monitor the SRAM device HAL state by calling the function
00059        HAL_SRAM_GetState()
00060
00061   @endverbatim
00062   ******************************************************************************
00063   * @attention
00064   *
00065   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00066   *
00067   * Redistribution and use in source and binary forms, with or without modification,
00068   * are permitted provided that the following conditions are met:
00069   *   1. Redistributions of source code must retain the above copyright notice,
00070   *      this list of conditions and the following disclaimer.
00071   *   2. Redistributions in binary form must reproduce the above copyright notice,
00072   *      this list of conditions and the following disclaimer in the documentation
00073   *      and/or other materials provided with the distribution.
00074   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00075   *      may be used to endorse or promote products derived from this software
00076   *      without specific prior written permission.
00077   *
00078   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00079   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00080   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00081   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00082   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00083   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00084   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00085   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00086   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00087   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00088   *
00089   ******************************************************************************
00090   */
00091
00092 /* Includes ------------------------------------------------------------------*/
00093 #include "stm32f3xx_hal.h"
00094
00095 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
00096
00097 /** @addtogroup STM32F3xx_HAL_Driver
00098   * @{
00099   */
00100
00101 #ifdef HAL_SRAM_MODULE_ENABLED
00102
00103 /** @defgroup SRAM SRAM
00104   * @brief SRAM HAL module driver
00105   * @{
00106   */
00107 /* Private typedef -----------------------------------------------------------*/
00108 /* Private define ------------------------------------------------------------*/
00109 /* Private macro -------------------------------------------------------------*/
00110 /* Private variables ---------------------------------------------------------*/
00111 /* Private function prototypes -----------------------------------------------*/
00112 /* Exported functions --------------------------------------------------------*/
00113
00114 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
00115   * @{
00116   */
00117
00118 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00119   * @brief    Initialization and Configuration functions.
00120   *
00121   @verbatim
00122   ==============================================================================
00123            ##### SRAM Initialization and de_initialization functions #####
00124   ==============================================================================
00125     [..]  This section provides functions allowing to initialize/de-initialize
00126           the SRAM memory
00127
00128 @endverbatim
00129   * @{
00130   */
00131
00132 /**
00133   * @brief  Performs the SRAM device initialization sequence
00134   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00135   *                the configuration information for SRAM module.
00136   * @param  Timing Pointer to SRAM control timing structure
00137   * @param  ExtTiming Pointer to SRAM extended mode timing structure
00138   * @retval HAL status
00139   */
00140 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
00141 {
00142   /* Check the SRAM handle parameter */
00143   if(hsram == NULL)
00144   {
00145      return HAL_ERROR;
00146   }
00147
00148   if(hsram->State == HAL_SRAM_STATE_RESET)
00149   {
00150     /* Allocate lock resource and initialize it */
00151     hsram->Lock = HAL_UNLOCKED;
00152
00153     /* Initialize the low level hardware (MSP) */
00154     HAL_SRAM_MspInit(hsram);
00155   }
00156
00157   /* Initialize SRAM control Interface */
00158   FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
00159
00160   /* Initialize SRAM timing Interface */
00161   FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
00162
00163   /* Initialize SRAM extended mode timing Interface */
00164   FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,  hsram->Init.ExtendedMode);
00165
00166   /* Enable the NORSRAM device */
00167   __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
00168
00169   return HAL_OK;
00170 }
00171
00172 /**
00173   * @brief  Performs the SRAM device De-initialization sequence.
00174   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00175   *                the configuration information for SRAM module.
00176   * @retval HAL status
00177   */
00178 HAL_StatusTypeDef  HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
00179 {
00180   /* De-Initialize the low level hardware (MSP) */
00181   HAL_SRAM_MspDeInit(hsram);
00182
00183   /* Configure the SRAM registers with their reset values */
00184   FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
00185
00186   hsram->State = HAL_SRAM_STATE_RESET;
00187
00188   /* Release Lock */
00189   __HAL_UNLOCK(hsram);
00190
00191   return HAL_OK;
00192 }
00193
00194 /**
00195   * @brief  SRAM MSP Init.
00196   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00197   *                the configuration information for SRAM module.
00198   * @retval None
00199   */
00200 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
00201 {
00202   /* Prevent unused argument(s) compilation warning */
00203   UNUSED(hsram);
00204
00205   /* NOTE : This function Should not be modified, when the callback is needed,
00206             the HAL_SRAM_MspInit could be implemented in the user file
00207    */
00208 }
00209
00210 /**
00211   * @brief  SRAM MSP DeInit.
00212   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00213   *                the configuration information for SRAM module.
00214   * @retval None
00215   */
00216 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
00217 {
00218   /* Prevent unused argument(s) compilation warning */
00219   UNUSED(hsram);
00220
00221   /* NOTE : This function Should not be modified, when the callback is needed,
00222             the HAL_SRAM_MspDeInit could be implemented in the user file
00223    */
00224 }
00225
00226 /**
00227   * @brief  DMA transfer complete callback.
00228   * @param  hdma pointer to a SRAM_HandleTypeDef structure that contains
00229   *                the configuration information for SRAM module.
00230   * @retval None
00231   */
00232 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
00233 {
00234   /* Prevent unused argument(s) compilation warning */
00235   UNUSED(hdma);
00236
00237   /* NOTE : This function Should not be modified, when the callback is needed,
00238             the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
00239    */
00240 }
00241
00242 /**
00243   * @brief  DMA transfer complete error callback.
00244   * @param  hdma pointer to a SRAM_HandleTypeDef structure that contains
00245   *                the configuration information for SRAM module.
00246   * @retval None
00247   */
00248 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
00249 {
00250   /* Prevent unused argument(s) compilation warning */
00251   UNUSED(hdma);
00252
00253   /* NOTE : This function Should not be modified, when the callback is needed,
00254             the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
00255    */
00256 }
00257
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
00263   * @brief    Input Output and memory control functions
00264   *
00265   @verbatim
00266   ==============================================================================
00267                   ##### SRAM Input and Output functions #####
00268   ==============================================================================
00269   [..]
00270     This section provides functions allowing to use and control the SRAM memory
00271
00272 @endverbatim
00273   * @{
00274   */
00275
00276 /**
00277   * @brief  Reads 8-bit buffer from SRAM memory.
00278   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00279   *                the configuration information for SRAM module.
00280   * @param  pAddress Pointer to read start address
00281   * @param  pDstBuffer Pointer to destination buffer
00282   * @param  BufferSize Size of the buffer to read from memory
00283   * @retval HAL status
00284   */
00285 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
00286 {
00287   __IO uint8_t * psramaddress = (uint8_t *)pAddress;
00288
00289   /* Process Locked */
00290   __HAL_LOCK(hsram);
00291
00292   /* Update the SRAM controller state */
00293   hsram->State = HAL_SRAM_STATE_BUSY;
00294
00295   /* Read data from memory */
00296   for(; BufferSize != 0U; BufferSize--)
00297   {
00298     *pDstBuffer = *(__IO uint8_t *)psramaddress;
00299     pDstBuffer++;
00300     psramaddress++;
00301   }
00302
00303   /* Update the SRAM controller state */
00304   hsram->State = HAL_SRAM_STATE_READY;
00305
00306   /* Process unlocked */
00307   __HAL_UNLOCK(hsram);
00308
00309   return HAL_OK;
00310 }
00311
00312 /**
00313   * @brief  Writes 8-bit buffer to SRAM memory.
00314   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00315   *                the configuration information for SRAM module.
00316   * @param  pAddress Pointer to write start address
00317   * @param  pSrcBuffer Pointer to source buffer to write
00318   * @param  BufferSize Size of the buffer to write to memory
00319   * @retval HAL status
00320   */
00321 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
00322 {
00323   __IO uint8_t * psramaddress = (uint8_t *)pAddress;
00324
00325   /* Check the SRAM controller state */
00326   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00327   {
00328     return  HAL_ERROR;
00329   }
00330
00331   /* Process Locked */
00332   __HAL_LOCK(hsram);
00333
00334   /* Update the SRAM controller state */
00335   hsram->State = HAL_SRAM_STATE_BUSY;
00336
00337   /* Write data to memory */
00338   for(; BufferSize != 0U; BufferSize--)
00339   {
00340     *(__IO uint8_t *)psramaddress = *pSrcBuffer;
00341     pSrcBuffer++;
00342     psramaddress++;
00343   }
00344
00345   /* Update the SRAM controller state */
00346   hsram->State = HAL_SRAM_STATE_READY;
00347
00348   /* Process unlocked */
00349   __HAL_UNLOCK(hsram);
00350
00351   return HAL_OK;
00352 }
00353
00354 /**
00355   * @brief  Reads 16-bit buffer from SRAM memory.
00356   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00357   *                the configuration information for SRAM module.
00358   * @param  pAddress Pointer to read start address
00359   * @param  pDstBuffer Pointer to destination buffer
00360   * @param  BufferSize Size of the buffer to read from memory
00361   * @retval HAL status
00362   */
00363 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
00364 {
00365   __IO uint16_t * psramaddress = (uint16_t *)pAddress;
00366
00367   /* Process Locked */
00368   __HAL_LOCK(hsram);
00369
00370   /* Update the SRAM controller state */
00371   hsram->State = HAL_SRAM_STATE_BUSY;
00372
00373   /* Read data from memory */
00374   for(; BufferSize != 0U; BufferSize--)
00375   {
00376     *pDstBuffer = *(__IO uint16_t *)psramaddress;
00377     pDstBuffer++;
00378     psramaddress++;
00379   }
00380
00381   /* Update the SRAM controller state */
00382   hsram->State = HAL_SRAM_STATE_READY;
00383
00384   /* Process unlocked */
00385   __HAL_UNLOCK(hsram);
00386
00387   return HAL_OK;
00388 }
00389
00390 /**
00391   * @brief  Writes 16-bit buffer to SRAM memory.
00392   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00393   *                the configuration information for SRAM module.
00394   * @param  pAddress Pointer to write start address
00395   * @param  pSrcBuffer Pointer to source buffer to write
00396   * @param  BufferSize Size of the buffer to write to memory
00397   * @retval HAL status
00398   */
00399 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
00400 {
00401   __IO uint16_t * psramaddress = (uint16_t *)pAddress;
00402
00403   /* Check the SRAM controller state */
00404   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00405   {
00406     return  HAL_ERROR;
00407   }
00408
00409   /* Process Locked */
00410   __HAL_LOCK(hsram);
00411
00412   /* Update the SRAM controller state */
00413   hsram->State = HAL_SRAM_STATE_BUSY;
00414
00415   /* Write data to memory */
00416   for(; BufferSize != 0U; BufferSize--)
00417   {
00418     *(__IO uint16_t *)psramaddress = *pSrcBuffer;
00419     pSrcBuffer++;
00420     psramaddress++;
00421   }
00422
00423   /* Update the SRAM controller state */
00424   hsram->State = HAL_SRAM_STATE_READY;
00425
00426   /* Process unlocked */
00427   __HAL_UNLOCK(hsram);
00428
00429   return HAL_OK;
00430 }
00431
00432 /**
00433   * @brief  Reads 32-bit buffer from SRAM memory.
00434   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00435   *                the configuration information for SRAM module.
00436   * @param  pAddress Pointer to read start address
00437   * @param  pDstBuffer Pointer to destination buffer
00438   * @param  BufferSize Size of the buffer to read from memory
00439   * @retval HAL status
00440   */
00441 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00442 {
00443   /* Process Locked */
00444   __HAL_LOCK(hsram);
00445
00446   /* Update the SRAM controller state */
00447   hsram->State = HAL_SRAM_STATE_BUSY;
00448
00449   /* Read data from memory */
00450   for(; BufferSize != 0U; BufferSize--)
00451   {
00452     *pDstBuffer = *(__IO uint32_t *)pAddress;
00453     pDstBuffer++;
00454     pAddress++;
00455   }
00456
00457   /* Update the SRAM controller state */
00458   hsram->State = HAL_SRAM_STATE_READY;
00459
00460   /* Process unlocked */
00461   __HAL_UNLOCK(hsram);
00462
00463   return HAL_OK;
00464 }
00465
00466 /**
00467   * @brief  Writes 32-bit buffer to SRAM memory.
00468   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00469   *                the configuration information for SRAM module.
00470   * @param  pAddress Pointer to write start address
00471   * @param  pSrcBuffer Pointer to source buffer to write
00472   * @param  BufferSize Size of the buffer to write to memory
00473   * @retval HAL status
00474   */
00475 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00476 {
00477   /* Check the SRAM controller state */
00478   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00479   {
00480     return  HAL_ERROR;
00481   }
00482
00483   /* Process Locked */
00484   __HAL_LOCK(hsram);
00485
00486   /* Update the SRAM controller state */
00487   hsram->State = HAL_SRAM_STATE_BUSY;
00488
00489   /* Write data to memory */
00490   for(; BufferSize != 0U; BufferSize--)
00491   {
00492     *(__IO uint32_t *)pAddress = *pSrcBuffer;
00493     pSrcBuffer++;
00494     pAddress++;
00495   }
00496
00497   /* Update the SRAM controller state */
00498   hsram->State = HAL_SRAM_STATE_READY;
00499
00500   /* Process unlocked */
00501   __HAL_UNLOCK(hsram);
00502
00503   return HAL_OK;
00504 }
00505
00506 /**
00507   * @brief  Reads a Words data from the SRAM memory using DMA transfer.
00508   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00509   *                the configuration information for SRAM module.
00510   * @param  pAddress Pointer to read start address
00511   * @param  pDstBuffer Pointer to destination buffer
00512   * @param  BufferSize Size of the buffer to read from memory
00513   * @retval HAL status
00514   */
00515 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00516 {
00517   /* Process Locked */
00518   __HAL_LOCK(hsram);
00519
00520   /* Update the SRAM controller state */
00521   hsram->State = HAL_SRAM_STATE_BUSY;
00522
00523   /* Configure DMA user callbacks */
00524   hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
00525   hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00526
00527   /* Enable the DMA Channel */
00528   HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
00529
00530   /* Update the SRAM controller state */
00531   hsram->State = HAL_SRAM_STATE_READY;
00532
00533   /* Process unlocked */
00534   __HAL_UNLOCK(hsram);
00535
00536   return HAL_OK;
00537 }
00538
00539 /**
00540   * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.
00541   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00542   *                the configuration information for SRAM module.
00543   * @param  pAddress Pointer to write start address
00544   * @param  pSrcBuffer Pointer to source buffer to write
00545   * @param  BufferSize Size of the buffer to write to memory
00546   * @retval HAL status
00547   */
00548 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00549 {
00550   /* Check the SRAM controller state */
00551   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00552   {
00553     return  HAL_ERROR;
00554   }
00555
00556   /* Process Locked */
00557   __HAL_LOCK(hsram);
00558
00559   /* Update the SRAM controller state */
00560   hsram->State = HAL_SRAM_STATE_BUSY;
00561
00562   /* Configure DMA user callbacks */
00563   hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
00564   hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00565
00566   /* Enable the DMA Channel */
00567   HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
00568
00569   /* Update the SRAM controller state */
00570   hsram->State = HAL_SRAM_STATE_READY;
00571
00572   /* Process unlocked */
00573   __HAL_UNLOCK(hsram);
00574
00575   return HAL_OK;
00576 }
00577
00578 /**
00579   * @}
00580   */
00581
00582 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
00583  *  @brief   Control functions
00584  *
00585 @verbatim
00586   ==============================================================================
00587                         ##### SRAM Control functions #####
00588   ==============================================================================
00589   [..]
00590     This subsection provides a set of functions allowing to control dynamically
00591     the SRAM interface.
00592
00593 @endverbatim
00594   * @{
00595   */
00596
00597 /**
00598   * @brief  Enables dynamically SRAM write operation.
00599   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00600   *                the configuration information for SRAM module.
00601   * @retval HAL status
00602   */
00603 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
00604 {
00605   /* Process Locked */
00606   __HAL_LOCK(hsram);
00607
00608   /* Enable write operation */
00609   FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
00610
00611   /* Update the SRAM controller state */
00612   hsram->State = HAL_SRAM_STATE_READY;
00613
00614   /* Process unlocked */
00615   __HAL_UNLOCK(hsram);
00616
00617   return HAL_OK;
00618 }
00619
00620 /**
00621   * @brief  Disables dynamically SRAM write operation.
00622   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00623   *                the configuration information for SRAM module.
00624   * @retval HAL status
00625   */
00626 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
00627 {
00628   /* Process Locked */
00629   __HAL_LOCK(hsram);
00630
00631   /* Update the SRAM controller state */
00632   hsram->State = HAL_SRAM_STATE_BUSY;
00633
00634   /* Disable write operation */
00635   FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
00636
00637   /* Update the SRAM controller state */
00638   hsram->State = HAL_SRAM_STATE_PROTECTED;
00639
00640   /* Process unlocked */
00641   __HAL_UNLOCK(hsram);
00642
00643   return HAL_OK;
00644 }
00645
00646 /**
00647   * @}
00648   */
00649
00650 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
00651  *  @brief   Peripheral State functions
00652  *
00653 @verbatim
00654   ==============================================================================
00655                       ##### SRAM State functions #####
00656   ==============================================================================
00657   [..]
00658     This subsection permits to get in run-time the status of the SRAM controller
00659     and the data flow.
00660
00661 @endverbatim
00662   * @{
00663   */
00664
00665 /**
00666   * @brief  Returns the SRAM controller state
00667   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00668   *                the configuration information for SRAM module.
00669   * @retval HAL state
00670   */
00671 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
00672 {
00673   return hsram->State;
00674 }
00675
00676 /**
00677   * @}
00678   */
00679
00680 /**
00681   * @}
00682   */
00683 /**
00684   * @}
00685   */
00686 #endif /* HAL_SRAM_MODULE_ENABLED */
00687
00688 /**
00689   * @}
00690   */
00691 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
00692
00693 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_sram.h Source File

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stm32f3xx_hal_sram.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_sram.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SRAM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_SRAM_H
00038 #define __STM32F3xx_HAL_SRAM_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
00046 #include "stm32f3xx_ll_fmc.h"
00047
00048 /** @addtogroup STM32F3xx_HAL_Driver
00049   * @{
00050   */
00051
00052 /** @addtogroup SRAM
00053   * @{
00054   */
00055
00056 /* Exported typedef ----------------------------------------------------------*/
00057
00058 /** @defgroup SRAM_Exported_Types SRAM Exported Types
00059   * @{
00060   */
00061 /**
00062   * @brief  HAL SRAM State structures definition
00063   */
00064 typedef enum
00065 {
00066   HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */
00067   HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */
00068   HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */
00069   HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */
00070   HAL_SRAM_STATE_PROTECTED = 0x04   /*!< SRAM peripheral NORSRAM device write protected */
00071
00072 }HAL_SRAM_StateTypeDef;
00073
00074 /**
00075   * @brief  SRAM handle Structure definition
00076   */
00077 typedef struct
00078 {
00079   FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
00080
00081   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
00082
00083   FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
00084
00085   HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
00086
00087   __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
00088
00089   DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
00090
00091 }SRAM_HandleTypeDef;
00092
00093 /**
00094   * @}
00095   */
00096
00097 /* Exported constants --------------------------------------------------------*/
00098 /* Exported macro ------------------------------------------------------------*/
00099
00100 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
00101  * @{
00102  */
00103
00104 /** @brief Reset SRAM handle state
00105   * @param  __HANDLE__ SRAM handle
00106   * @retval None
00107   */
00108 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
00109
00110 /**
00111   * @}
00112   */
00113
00114 /* Exported functions --------------------------------------------------------*/
00115 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
00116   * @{
00117   */
00118
00119 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00120  * @{
00121  */
00122
00123 /* Initialization/de-initialization functions  ********************************/
00124 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
00125 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
00126 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
00127 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
00128
00129 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
00130 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
00137  * @{
00138  */
00139
00140 /* I/O operation functions  ***************************************************/
00141 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
00142 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
00143 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
00144 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
00145 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00146 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00147 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00148 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00149
00150 /**
00151   * @}
00152   */
00153
00154 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions
00155  * @{
00156  */
00157
00158 /* SRAM Control functions  ****************************************************/
00159 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
00160 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
00161
00162 /**
00163   * @}
00164   */
00165
00166 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
00167  * @{
00168  */
00169
00170 /* SRAM Peripheral State functions ********************************************/
00171 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
00172
00173 /**
00174   * @}
00175   */
00176
00177 /**
00178   * @}
00179   */
00180
00181 /**
00182   * @}
00183   */
00184
00185 /**
00186   * @}
00187   */
00188
00189 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
00190
00191 #ifdef __cplusplus
00192 }
00193 #endif
00194
00195 #endif /* __STM32F3xx_HAL_SRAM_H */
00196
00197 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_tim.c Source File

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stm32f3xx_hal_tim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_tim.c
00004   * @author  MCD Application Team
00005   * @brief   TIM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Timer (TIM) peripheral:
00008   *           + Time Base Initialization
00009   *           + Time Base Start
00010   *           + Time Base Start Interruption
00011   *           + Time Base Start DMA
00012   *           + Time Output Compare/PWM Initialization
00013   *           + Time Output Compare/PWM Channel Configuration
00014   *           + Time Output Compare/PWM  Start
00015   *           + Time Output Compare/PWM  Start Interruption
00016   *           + Time Output Compare/PWM Start DMA
00017   *           + Time Input Capture Initialization
00018   *           + Time Input Capture Channel Configuration
00019   *           + Time Input Capture Start
00020   *           + Time Input Capture Start Interruption
00021   *           + Time Input Capture Start DMA
00022   *           + Time One Pulse Initialization
00023   *           + Time One Pulse Channel Configuration
00024   *           + Time One Pulse Start
00025   *           + Time Encoder Interface Initialization
00026   *           + Time Encoder Interface Start
00027   *           + Time Encoder Interface Start Interruption
00028   *           + Time Encoder Interface Start DMA
00029   *           + Commutation Event configuration with Interruption and DMA
00030   *           + Time OCRef clear configuration
00031   *           + Time External Clock configuration
00032   @verbatim
00033   ==============================================================================
00034                       ##### TIMER Generic features #####
00035   ==============================================================================
00036   [..] The Timer features include:
00037        (#) 16-bit up, down, up/down auto-reload counter.
00038        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
00039            counter clock frequency either by any factor between 1 and 65536.
00040        (#) Up to 4 independent channels for:
00041            (++) Input Capture
00042            (++) Output Compare
00043            (++) PWM generation (Edge and Center-aligned Mode)
00044            (++) One-pulse mode output
00045
00046             ##### How to use this driver #####
00047   ==============================================================================
00048     [..]
00049      (#) Initialize the TIM low level resources by implementing the following functions
00050          depending from feature used :
00051            (++) Time Base : HAL_TIM_Base_MspInit()
00052            (++) Input Capture : HAL_TIM_IC_MspInit()
00053            (++) Output Compare : HAL_TIM_OC_MspInit()
00054            (++) PWM generation : HAL_TIM_PWM_MspInit()
00055            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
00056            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
00057
00058      (#) Initialize the TIM low level resources :
00059         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE  ();
00060         (##) TIM pins configuration
00061             (+++) Enable the clock for the TIM GPIOs using the following function:
00062              __HAL_RCC_GPIOx_CLK_ENABLE();
00063             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00064
00065      (#) The external Clock can be configured, if needed (the default clock is the
00066          internal clock from the APBx), using the following function:
00067          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00068          any start function.
00069
00070      (#) Configure the TIM in the desired functioning mode using one of the
00071        Initialization function of this driver:
00072        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
00073        (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
00074             Output Compare signal.
00075        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
00076             PWM signal.
00077        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
00078             external signal.
00079          (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
00080               in One Pulse Mode.
00081        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
00082
00083      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
00084            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
00085            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
00086            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
00087            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
00088            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
00089            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
00090
00091      (#) The DMA Burst is managed with the two following functions:
00092          HAL_TIM_DMABurst_WriteStart()
00093          HAL_TIM_DMABurst_ReadStart()
00094
00095   @endverbatim
00096   ******************************************************************************
00097   * @attention
00098   *
00099   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00100   *
00101   * Redistribution and use in source and binary forms, with or without modification,
00102   * are permitted provided that the following conditions are met:
00103   *   1. Redistributions of source code must retain the above copyright notice,
00104   *      this list of conditions and the following disclaimer.
00105   *   2. Redistributions in binary form must reproduce the above copyright notice,
00106   *      this list of conditions and the following disclaimer in the documentation
00107   *      and/or other materials provided with the distribution.
00108   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00109   *      may be used to endorse or promote products derived from this software
00110   *      without specific prior written permission.
00111   *
00112   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00113   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00114   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00115   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00116   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00117   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00118   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00119   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00120   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00121   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00122   *
00123   ******************************************************************************
00124   */
00125
00126 /* Includes ------------------------------------------------------------------*/
00127 #include "stm32f3xx_hal.h"
00128
00129 /** @addtogroup STM32F3xx_HAL_Driver
00130   * @{
00131   */
00132
00133 /** @defgroup TIM TIM
00134   * @brief TIM HAL module driver
00135   * @{
00136   */
00137
00138 #ifdef HAL_TIM_MODULE_ENABLED
00139
00140 /* Private typedef -----------------------------------------------------------*/
00141 /* Private define ------------------------------------------------------------*/
00142 /* Private macro -------------------------------------------------------------*/
00143 /* Private variables ---------------------------------------------------------*/
00144 /* Private function prototypes -----------------------------------------------*/
00145
00146 /** @defgroup TIM_Private_Functions TIM Private Functions
00147   * @{
00148   */
00149 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00150 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00151                        uint32_t TIM_ICFilter);
00152 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00153 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00154                        uint32_t TIM_ICFilter);
00155 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00156                        uint32_t TIM_ICFilter);
00157 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
00158 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
00159 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
00160 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
00161                                      TIM_SlaveConfigTypeDef * sSlaveConfig);
00162
00163 /**
00164   * @}
00165   */
00166
00167 /* Exported functions ---------------------------------------------------------*/
00168
00169 /** @defgroup TIM_Exported_Functions TIM Exported Functions
00170   * @{
00171   */
00172
00173 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
00174  *  @brief    Time Base functions
00175  *
00176 @verbatim
00177   ==============================================================================
00178               ##### Time Base functions #####
00179   ==============================================================================
00180   [..]
00181     This section provides functions allowing to:
00182     (+) Initialize and configure the TIM base.
00183     (+) De-initialize the TIM base.
00184     (+) Start the Time Base.
00185     (+) Stop the Time Base.
00186     (+) Start the Time Base and enable interrupt.
00187     (+) Stop the Time Base and disable interrupt.
00188     (+) Start the Time Base and enable DMA transfer.
00189     (+) Stop the Time Base and disable DMA transfer.
00190
00191 @endverbatim
00192   * @{
00193   */
00194 /**
00195   * @brief  Initializes the TIM Time base Unit according to the specified
00196   *         parameters in the TIM_HandleTypeDef and create the associated handle.
00197   * @param  htim TIM Base handle
00198   * @retval HAL status
00199   */
00200 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
00201 {
00202   /* Check the TIM handle allocation */
00203   if(htim == NULL)
00204   {
00205     return HAL_ERROR;
00206   }
00207
00208   /* Check the parameters */
00209   assert_param(IS_TIM_INSTANCE(htim->Instance));
00210   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00211   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00212   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00213
00214   if(htim->State == HAL_TIM_STATE_RESET)
00215   {
00216     /* Allocate lock resource and initialize it */
00217     htim->Lock = HAL_UNLOCKED;
00218
00219     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00220     HAL_TIM_Base_MspInit(htim);
00221   }
00222
00223   /* Set the TIM state */
00224   htim->State= HAL_TIM_STATE_BUSY;
00225
00226   /* Set the Time Base configuration */
00227   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00228
00229   /* Initialize the TIM state*/
00230   htim->State= HAL_TIM_STATE_READY;
00231
00232   return HAL_OK;
00233 }
00234
00235 /**
00236   * @brief  DeInitializes the TIM Base peripheral
00237   * @param  htim TIM Base handle
00238   * @retval HAL status
00239   */
00240 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
00241 {
00242   /* Check the parameters */
00243   assert_param(IS_TIM_INSTANCE(htim->Instance));
00244
00245   htim->State = HAL_TIM_STATE_BUSY;
00246
00247   /* Disable the TIM Peripheral Clock */
00248   __HAL_TIM_DISABLE(htim);
00249
00250   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00251   HAL_TIM_Base_MspDeInit(htim);
00252
00253   /* Change TIM state */
00254   htim->State = HAL_TIM_STATE_RESET;
00255
00256   /* Release Lock */
00257   __HAL_UNLOCK(htim);
00258
00259   return HAL_OK;
00260 }
00261
00262 /**
00263   * @brief  Initializes the TIM Base MSP.
00264   * @param  htim TIM handle
00265   * @retval None
00266   */
00267 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
00268 {
00269   /* Prevent unused argument(s) compilation warning */
00270   UNUSED(htim);
00271
00272   /* NOTE : This function Should not be modified, when the callback is needed,
00273             the HAL_TIM_Base_MspInit could be implemented in the user file
00274    */
00275 }
00276
00277 /**
00278   * @brief  DeInitializes TIM Base MSP.
00279   * @param  htim TIM handle
00280   * @retval None
00281   */
00282 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
00283 {
00284   /* Prevent unused argument(s) compilation warning */
00285   UNUSED(htim);
00286
00287   /* NOTE : This function Should not be modified, when the callback is needed,
00288             the HAL_TIM_Base_MspDeInit could be implemented in the user file
00289    */
00290 }
00291
00292
00293 /**
00294   * @brief  Starts the TIM Base generation.
00295   * @param  htim TIM handle
00296   * @retval HAL status
00297 */
00298 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
00299 {
00300   /* Check the parameters */
00301   assert_param(IS_TIM_INSTANCE(htim->Instance));
00302
00303   /* Set the TIM state */
00304   htim->State= HAL_TIM_STATE_BUSY;
00305
00306   /* Enable the Peripheral */
00307   __HAL_TIM_ENABLE(htim);
00308
00309   /* Change the TIM state*/
00310   htim->State= HAL_TIM_STATE_READY;
00311
00312   /* Return function status */
00313   return HAL_OK;
00314 }
00315
00316 /**
00317   * @brief  Stops the TIM Base generation.
00318   * @param  htim TIM handle
00319   * @retval HAL status
00320 */
00321 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
00322 {
00323   /* Check the parameters */
00324   assert_param(IS_TIM_INSTANCE(htim->Instance));
00325
00326   /* Set the TIM state */
00327   htim->State= HAL_TIM_STATE_BUSY;
00328
00329   /* Disable the Peripheral */
00330   __HAL_TIM_DISABLE(htim);
00331
00332   /* Change the TIM state*/
00333   htim->State= HAL_TIM_STATE_READY;
00334
00335   /* Return function status */
00336   return HAL_OK;
00337 }
00338
00339 /**
00340   * @brief  Starts the TIM Base generation in interrupt mode.
00341   * @param  htim TIM handle
00342   * @retval HAL status
00343 */
00344 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
00345 {
00346   /* Check the parameters */
00347   assert_param(IS_TIM_INSTANCE(htim->Instance));
00348
00349    /* Enable the TIM Update interrupt */
00350    __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
00351
00352    /* Enable the Peripheral */
00353   __HAL_TIM_ENABLE(htim);
00354
00355   /* Return function status */
00356   return HAL_OK;
00357 }
00358
00359 /**
00360   * @brief  Stops the TIM Base generation in interrupt mode.
00361   * @param  htim TIM handle
00362   * @retval HAL status
00363 */
00364 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
00365 {
00366   /* Check the parameters */
00367   assert_param(IS_TIM_INSTANCE(htim->Instance));
00368   /* Disable the TIM Update interrupt */
00369   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
00370
00371   /* Disable the Peripheral */
00372   __HAL_TIM_DISABLE(htim);
00373
00374   /* Return function status */
00375   return HAL_OK;
00376 }
00377
00378 /**
00379   * @brief  Starts the TIM Base generation in DMA mode.
00380   * @param  htim TIM handle
00381   * @param  pData The source Buffer address.
00382   * @param  Length The length of data to be transferred from memory to peripheral.
00383   * @retval HAL status
00384 */
00385 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00386 {
00387   /* Check the parameters */
00388   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00389
00390   if((htim->State == HAL_TIM_STATE_BUSY))
00391   {
00392      return HAL_BUSY;
00393   }
00394   else if((htim->State == HAL_TIM_STATE_READY))
00395   {
00396     if((pData == 0U ) && (Length > 0U))
00397     {
00398       return HAL_ERROR;
00399     }
00400     else
00401     {
00402       htim->State = HAL_TIM_STATE_BUSY;
00403     }
00404   }
00405   /* Set the DMA Period elapsed callback */
00406   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
00407
00408   /* Set the DMA error callback */
00409   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
00410
00411   /* Enable the DMA channel */
00412   HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
00413
00414   /* Enable the TIM Update DMA request */
00415   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
00416
00417   /* Enable the Peripheral */
00418   __HAL_TIM_ENABLE(htim);
00419
00420   /* Return function status */
00421   return HAL_OK;
00422 }
00423
00424 /**
00425   * @brief  Stops the TIM Base generation in DMA mode.
00426   * @param  htim TIM handle
00427   * @retval HAL status
00428 */
00429 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
00430 {
00431   /* Check the parameters */
00432   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00433
00434   /* Disable the TIM Update DMA request */
00435   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
00436
00437   /* Disable the Peripheral */
00438   __HAL_TIM_DISABLE(htim);
00439
00440   /* Change the htim state */
00441   htim->State = HAL_TIM_STATE_READY;
00442
00443   /* Return function status */
00444   return HAL_OK;
00445 }
00446
00447 /**
00448   * @}
00449   */
00450
00451 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
00452  *  @brief    Time Output Compare functions
00453  *
00454 @verbatim
00455   ==============================================================================
00456                   ##### Time Output Compare functions #####
00457   ==============================================================================
00458   [..]
00459     This section provides functions allowing to:
00460     (+) Initialize and configure the TIM Output Compare.
00461     (+) De-initialize the TIM Output Compare.
00462     (+) Start the Time Output Compare.
00463     (+) Stop the Time Output Compare.
00464     (+) Start the Time Output Compare and enable interrupt.
00465     (+) Stop the Time Output Compare and disable interrupt.
00466     (+) Start the Time Output Compare and enable DMA transfer.
00467     (+) Stop the Time Output Compare and disable DMA transfer.
00468
00469 @endverbatim
00470   * @{
00471   */
00472 /**
00473   * @brief  Initializes the TIM Output Compare according to the specified
00474   *         parameters in the TIM_HandleTypeDef and create the associated handle.
00475   * @param  htim TIM Output Compare handle
00476   * @retval HAL status
00477   */
00478 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
00479 {
00480   /* Check the TIM handle allocation */
00481   if(htim == NULL)
00482   {
00483     return HAL_ERROR;
00484   }
00485
00486   /* Check the parameters */
00487   assert_param(IS_TIM_INSTANCE(htim->Instance));
00488   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00489   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00490   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00491
00492   if(htim->State == HAL_TIM_STATE_RESET)
00493   {
00494     /* Allocate lock resource and initialize it */
00495     htim->Lock = HAL_UNLOCKED;
00496
00497     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00498     HAL_TIM_OC_MspInit(htim);
00499   }
00500
00501   /* Set the TIM state */
00502   htim->State= HAL_TIM_STATE_BUSY;
00503
00504   /* Init the base time for the Output Compare */
00505   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
00506
00507   /* Initialize the TIM state*/
00508   htim->State= HAL_TIM_STATE_READY;
00509
00510   return HAL_OK;
00511 }
00512
00513 /**
00514   * @brief  DeInitializes the TIM peripheral
00515   * @param  htim TIM Output Compare handle
00516   * @retval HAL status
00517   */
00518 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
00519 {
00520   /* Check the parameters */
00521   assert_param(IS_TIM_INSTANCE(htim->Instance));
00522
00523    htim->State = HAL_TIM_STATE_BUSY;
00524
00525   /* Disable the TIM Peripheral Clock */
00526   __HAL_TIM_DISABLE(htim);
00527
00528   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00529   HAL_TIM_OC_MspDeInit(htim);
00530
00531   /* Change TIM state */
00532   htim->State = HAL_TIM_STATE_RESET;
00533
00534   /* Release Lock */
00535   __HAL_UNLOCK(htim);
00536
00537   return HAL_OK;
00538 }
00539
00540 /**
00541   * @brief  Initializes the TIM Output Compare MSP.
00542   * @param  htim TIM handle
00543   * @retval None
00544   */
00545 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
00546 {
00547   /* Prevent unused argument(s) compilation warning */
00548   UNUSED(htim);
00549
00550   /* NOTE : This function Should not be modified, when the callback is needed,
00551             the HAL_TIM_OC_MspInit could be implemented in the user file
00552    */
00553 }
00554
00555 /**
00556   * @brief  DeInitializes TIM Output Compare MSP.
00557   * @param  htim TIM handle
00558   * @retval None
00559   */
00560 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
00561 {
00562   /* Prevent unused argument(s) compilation warning */
00563   UNUSED(htim);
00564
00565   /* NOTE : This function Should not be modified, when the callback is needed,
00566             the HAL_TIM_OC_MspDeInit could be implemented in the user file
00567    */
00568 }
00569
00570 /**
00571   * @brief  Starts the TIM Output Compare signal generation.
00572   * @param  htim TIM Output Compare handle
00573   * @param  Channel TIM Channel to be enabled
00574   *          This parameter can be one of the following values:
00575   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00576   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00577   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00578   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00579   * @retval HAL status
00580 */
00581 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00582 {
00583   /* Check the parameters */
00584   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00585
00586   /* Enable the Output compare channel */
00587   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00588
00589   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00590   {
00591     /* Enable the main output */
00592     __HAL_TIM_MOE_ENABLE(htim);
00593   }
00594
00595   /* Enable the Peripheral */
00596   __HAL_TIM_ENABLE(htim);
00597
00598   /* Return function status */
00599   return HAL_OK;
00600 }
00601
00602 /**
00603   * @brief  Stops the TIM Output Compare signal generation.
00604   * @param  htim TIM handle
00605   * @param  Channel TIM Channel to be disabled
00606   *          This parameter can be one of the following values:
00607   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00608   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00609   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00610   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00611   * @retval HAL status
00612 */
00613 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00614 {
00615   /* Check the parameters */
00616   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00617
00618   /* Disable the Output compare channel */
00619   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00620
00621   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00622   {
00623     /* Disable the Main Ouput */
00624     __HAL_TIM_MOE_DISABLE(htim);
00625   }
00626
00627   /* Disable the Peripheral */
00628   __HAL_TIM_DISABLE(htim);
00629
00630   /* Return function status */
00631   return HAL_OK;
00632 }
00633
00634 /**
00635   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
00636   * @param  htim TIM OC handle
00637   * @param  Channel TIM Channel to be enabled
00638   *          This parameter can be one of the following values:
00639   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00640   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00641   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00642   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00643   * @retval HAL status
00644 */
00645 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00646 {
00647   /* Check the parameters */
00648   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00649
00650   switch (Channel)
00651   {
00652     case TIM_CHANNEL_1:
00653     {
00654       /* Enable the TIM Capture/Compare 1 interrupt */
00655       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00656     }
00657     break;
00658
00659     case TIM_CHANNEL_2:
00660     {
00661       /* Enable the TIM Capture/Compare 2 interrupt */
00662       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00663     }
00664     break;
00665
00666     case TIM_CHANNEL_3:
00667     {
00668       /* Enable the TIM Capture/Compare 3 interrupt */
00669       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00670     }
00671     break;
00672
00673     case TIM_CHANNEL_4:
00674     {
00675       /* Enable the TIM Capture/Compare 4 interrupt */
00676       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00677     }
00678     break;
00679
00680     default:
00681     break;
00682   }
00683
00684   /* Enable the Output compare channel */
00685   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00686
00687   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00688   {
00689     /* Enable the main output */
00690     __HAL_TIM_MOE_ENABLE(htim);
00691   }
00692
00693   /* Enable the Peripheral */
00694   __HAL_TIM_ENABLE(htim);
00695
00696   /* Return function status */
00697   return HAL_OK;
00698 }
00699
00700 /**
00701   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
00702   * @param  htim TIM Output Compare handle
00703   * @param  Channel TIM Channel to be disabled
00704   *          This parameter can be one of the following values:
00705   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00706   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00707   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00708   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00709   * @retval HAL status
00710 */
00711 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00712 {
00713   /* Check the parameters */
00714   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00715
00716   switch (Channel)
00717   {
00718     case TIM_CHANNEL_1:
00719     {
00720       /* Disable the TIM Capture/Compare 1 interrupt */
00721       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00722     }
00723     break;
00724
00725     case TIM_CHANNEL_2:
00726     {
00727       /* Disable the TIM Capture/Compare 2 interrupt */
00728       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00729     }
00730     break;
00731
00732     case TIM_CHANNEL_3:
00733     {
00734       /* Disable the TIM Capture/Compare 3 interrupt */
00735       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00736     }
00737     break;
00738
00739     case TIM_CHANNEL_4:
00740     {
00741       /* Disable the TIM Capture/Compare 4 interrupt */
00742       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
00743     }
00744     break;
00745
00746     default:
00747     break;
00748   }
00749
00750   /* Disable the Output compare channel */
00751   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00752
00753   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00754   {
00755     /* Disable the Main Ouput */
00756     __HAL_TIM_MOE_DISABLE(htim);
00757   }
00758
00759   /* Disable the Peripheral */
00760   __HAL_TIM_DISABLE(htim);
00761
00762   /* Return function status */
00763   return HAL_OK;
00764 }
00765
00766 /**
00767   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
00768   * @param  htim TIM Output Compare handle
00769   * @param  Channel TIM Channel to be enabled
00770   *          This parameter can be one of the following values:
00771   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00772   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00773   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00774   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00775   * @param  pData The source Buffer address.
00776   * @param  Length The length of data to be transferred from memory to TIM peripheral
00777   * @retval HAL status
00778 */
00779 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00780 {
00781   /* Check the parameters */
00782   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00783
00784   if((htim->State == HAL_TIM_STATE_BUSY))
00785   {
00786      return HAL_BUSY;
00787   }
00788   else if((htim->State == HAL_TIM_STATE_READY))
00789   {
00790     if(((uint32_t)pData == 0U ) && (Length > 0U))
00791     {
00792       return HAL_ERROR;
00793     }
00794     else
00795     {
00796       htim->State = HAL_TIM_STATE_BUSY;
00797     }
00798   }
00799   switch (Channel)
00800   {
00801     case TIM_CHANNEL_1:
00802     {
00803       /* Set the DMA Period elapsed callback */
00804       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
00805
00806       /* Set the DMA error callback */
00807       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00808
00809       /* Enable the DMA channel */
00810       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
00811
00812       /* Enable the TIM Capture/Compare 1 DMA request */
00813       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00814     }
00815     break;
00816
00817     case TIM_CHANNEL_2:
00818     {
00819       /* Set the DMA Period elapsed callback */
00820       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
00821
00822       /* Set the DMA error callback */
00823       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
00824
00825       /* Enable the DMA channel */
00826       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
00827
00828       /* Enable the TIM Capture/Compare 2 DMA request */
00829       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00830     }
00831     break;
00832
00833     case TIM_CHANNEL_3:
00834     {
00835       /* Set the DMA Period elapsed callback */
00836       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
00837
00838       /* Set the DMA error callback */
00839       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
00840
00841       /* Enable the DMA channel */
00842       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
00843
00844       /* Enable the TIM Capture/Compare 3 DMA request */
00845       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
00846     }
00847     break;
00848
00849     case TIM_CHANNEL_4:
00850     {
00851      /* Set the DMA Period elapsed callback */
00852       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
00853
00854       /* Set the DMA error callback */
00855       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
00856
00857       /* Enable the DMA channel */
00858       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
00859
00860       /* Enable the TIM Capture/Compare 4 DMA request */
00861       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
00862     }
00863     break;
00864
00865     default:
00866     break;
00867   }
00868
00869   /* Enable the Output compare channel */
00870   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00871
00872   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00873   {
00874     /* Enable the main output */
00875     __HAL_TIM_MOE_ENABLE(htim);
00876   }
00877
00878   /* Enable the Peripheral */
00879   __HAL_TIM_ENABLE(htim);
00880
00881   /* Return function status */
00882   return HAL_OK;
00883 }
00884
00885 /**
00886   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
00887   * @param  htim TIM Output Compare handle
00888   * @param  Channel TIM Channel to be disabled
00889   *          This parameter can be one of the following values:
00890   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00891   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00892   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00893   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00894   * @retval HAL status
00895 */
00896 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
00897 {
00898   /* Check the parameters */
00899   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00900
00901   switch (Channel)
00902   {
00903     case TIM_CHANNEL_1:
00904     {
00905       /* Disable the TIM Capture/Compare 1 DMA request */
00906       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00907     }
00908     break;
00909
00910     case TIM_CHANNEL_2:
00911     {
00912       /* Disable the TIM Capture/Compare 2 DMA request */
00913       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
00914     }
00915     break;
00916
00917     case TIM_CHANNEL_3:
00918     {
00919       /* Disable the TIM Capture/Compare 3 DMA request */
00920       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
00921     }
00922     break;
00923
00924     case TIM_CHANNEL_4:
00925     {
00926       /* Disable the TIM Capture/Compare 4 interrupt */
00927       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
00928     }
00929     break;
00930
00931     default:
00932     break;
00933   }
00934
00935   /* Disable the Output compare channel */
00936   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00937
00938   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00939   {
00940     /* Disable the Main Ouput */
00941     __HAL_TIM_MOE_DISABLE(htim);
00942   }
00943
00944   /* Disable the Peripheral */
00945   __HAL_TIM_DISABLE(htim);
00946
00947   /* Change the htim state */
00948   htim->State = HAL_TIM_STATE_READY;
00949
00950   /* Return function status */
00951   return HAL_OK;
00952 }
00953
00954 /**
00955   * @}
00956   */
00957
00958 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
00959  *  @brief    Time PWM functions
00960  *
00961 @verbatim
00962   ==============================================================================
00963                           ##### Time PWM functions #####
00964   ==============================================================================
00965   [..]
00966     This section provides functions allowing to:
00967     (+) Initialize and configure the TIM OPWM.
00968     (+) De-initialize the TIM PWM.
00969     (+) Start the Time PWM.
00970     (+) Stop the Time PWM.
00971     (+) Start the Time PWM and enable interrupt.
00972     (+) Stop the Time PWM and disable interrupt.
00973     (+) Start the Time PWM and enable DMA transfer.
00974     (+) Stop the Time PWM and disable DMA transfer.
00975
00976 @endverbatim
00977   * @{
00978   */
00979 /**
00980   * @brief  Initializes the TIM PWM Time Base according to the specified
00981   *         parameters in the TIM_HandleTypeDef and create the associated handle.
00982   * @param  htim TIM handle
00983   * @retval HAL status
00984   */
00985 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
00986 {
00987   /* Check the TIM handle allocation */
00988   if(htim == NULL)
00989   {
00990     return HAL_ERROR;
00991   }
00992
00993   /* Check the parameters */
00994   assert_param(IS_TIM_INSTANCE(htim->Instance));
00995   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00996   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00997   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00998
00999   if(htim->State == HAL_TIM_STATE_RESET)
01000   {
01001     /* Allocate lock resource and initialize it */
01002     htim->Lock = HAL_UNLOCKED;
01003
01004     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01005     HAL_TIM_PWM_MspInit(htim);
01006   }
01007
01008   /* Set the TIM state */
01009   htim->State= HAL_TIM_STATE_BUSY;
01010
01011   /* Init the base time for the PWM */
01012   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01013
01014   /* Initialize the TIM state*/
01015   htim->State= HAL_TIM_STATE_READY;
01016
01017   return HAL_OK;
01018 }
01019
01020 /**
01021   * @brief  DeInitializes the TIM peripheral
01022   * @param  htim TIM handle
01023   * @retval HAL status
01024   */
01025 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
01026 {
01027   /* Check the parameters */
01028   assert_param(IS_TIM_INSTANCE(htim->Instance));
01029
01030   htim->State = HAL_TIM_STATE_BUSY;
01031
01032   /* Disable the TIM Peripheral Clock */
01033   __HAL_TIM_DISABLE(htim);
01034
01035   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01036   HAL_TIM_PWM_MspDeInit(htim);
01037
01038   /* Change TIM state */
01039   htim->State = HAL_TIM_STATE_RESET;
01040
01041   /* Release Lock */
01042   __HAL_UNLOCK(htim);
01043
01044   return HAL_OK;
01045 }
01046
01047 /**
01048   * @brief  Initializes the TIM PWM MSP.
01049   * @param  htim TIM handle
01050   * @retval None
01051   */
01052 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
01053 {
01054   /* Prevent unused argument(s) compilation warning */
01055   UNUSED(htim);
01056
01057   /* NOTE : This function Should not be modified, when the callback is needed,
01058             the HAL_TIM_PWM_MspInit could be implemented in the user file
01059    */
01060 }
01061
01062 /**
01063   * @brief  DeInitializes TIM PWM MSP.
01064   * @param  htim TIM handle
01065   * @retval None
01066   */
01067 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
01068 {
01069   /* Prevent unused argument(s) compilation warning */
01070   UNUSED(htim);
01071
01072   /* NOTE : This function Should not be modified, when the callback is needed,
01073             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
01074    */
01075 }
01076
01077 /**
01078   * @brief  Starts the PWM signal generation.
01079   * @param  htim TIM handle
01080   * @param  Channel TIM Channels to be enabled
01081   *          This parameter can be one of the following values:
01082   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01083   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01084   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01085   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01086   * @retval HAL status
01087 */
01088 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
01089 {
01090   /* Check the parameters */
01091   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01092
01093   /* Enable the Capture compare channel */
01094   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01095
01096   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01097   {
01098     /* Enable the main output */
01099     __HAL_TIM_MOE_ENABLE(htim);
01100   }
01101
01102   /* Enable the Peripheral */
01103   __HAL_TIM_ENABLE(htim);
01104
01105   /* Return function status */
01106   return HAL_OK;
01107 }
01108
01109 /**
01110   * @brief  Stops the PWM signal generation.
01111   * @param  htim TIM handle
01112   * @param  Channel TIM Channels to be disabled
01113   *          This parameter can be one of the following values:
01114   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01115   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01116   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01117   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01118   * @retval HAL status
01119 */
01120 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01121 {
01122   /* Check the parameters */
01123   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01124
01125   /* Disable the Capture compare channel */
01126   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01127
01128   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01129   {
01130     /* Disable the Main Ouput */
01131     __HAL_TIM_MOE_DISABLE(htim);
01132   }
01133
01134   /* Disable the Peripheral */
01135   __HAL_TIM_DISABLE(htim);
01136
01137   /* Change the htim state */
01138   htim->State = HAL_TIM_STATE_READY;
01139
01140   /* Return function status */
01141   return HAL_OK;
01142 }
01143
01144 /**
01145   * @brief  Starts the PWM signal generation in interrupt mode.
01146   * @param  htim TIM handle
01147   * @param  Channel TIM Channels to be enabled
01148   *          This parameter can be one of the following values:
01149   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01150   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01151   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01152   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01153   * @retval HAL status
01154 */
01155 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01156 {
01157   /* Check the parameters */
01158   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01159
01160   switch (Channel)
01161   {
01162     case TIM_CHANNEL_1:
01163     {
01164       /* Enable the TIM Capture/Compare 1 interrupt */
01165       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01166     }
01167     break;
01168
01169     case TIM_CHANNEL_2:
01170     {
01171       /* Enable the TIM Capture/Compare 2 interrupt */
01172       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01173     }
01174     break;
01175
01176     case TIM_CHANNEL_3:
01177     {
01178       /* Enable the TIM Capture/Compare 3 interrupt */
01179       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01180     }
01181     break;
01182
01183     case TIM_CHANNEL_4:
01184     {
01185       /* Enable the TIM Capture/Compare 4 interrupt */
01186       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01187     }
01188     break;
01189
01190     default:
01191     break;
01192   }
01193
01194   /* Enable the Capture compare channel */
01195   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01196
01197   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01198   {
01199     /* Enable the main output */
01200     __HAL_TIM_MOE_ENABLE(htim);
01201   }
01202
01203   /* Enable the Peripheral */
01204   __HAL_TIM_ENABLE(htim);
01205
01206   /* Return function status */
01207   return HAL_OK;
01208 }
01209
01210 /**
01211   * @brief  Stops the PWM signal generation in interrupt mode.
01212   * @param  htim TIM handle
01213   * @param  Channel TIM Channels to be disabled
01214   *          This parameter can be one of the following values:
01215   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01216   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01217   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01218   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01219   * @retval HAL status
01220 */
01221 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01222 {
01223   /* Check the parameters */
01224   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01225
01226   switch (Channel)
01227   {
01228     case TIM_CHANNEL_1:
01229     {
01230       /* Disable the TIM Capture/Compare 1 interrupt */
01231       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01232     }
01233     break;
01234
01235     case TIM_CHANNEL_2:
01236     {
01237       /* Disable the TIM Capture/Compare 2 interrupt */
01238       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01239     }
01240     break;
01241
01242     case TIM_CHANNEL_3:
01243     {
01244       /* Disable the TIM Capture/Compare 3 interrupt */
01245       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01246     }
01247     break;
01248
01249     case TIM_CHANNEL_4:
01250     {
01251       /* Disable the TIM Capture/Compare 4 interrupt */
01252       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01253     }
01254     break;
01255
01256     default:
01257     break;
01258   }
01259
01260   /* Disable the Capture compare channel */
01261   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01262
01263   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01264   {
01265     /* Disable the Main Ouput */
01266     __HAL_TIM_MOE_DISABLE(htim);
01267   }
01268
01269   /* Disable the Peripheral */
01270   __HAL_TIM_DISABLE(htim);
01271
01272   /* Return function status */
01273   return HAL_OK;
01274 }
01275
01276 /**
01277   * @brief  Starts the TIM PWM signal generation in DMA mode.
01278   * @param  htim TIM handle
01279   * @param  Channel TIM Channels to be enabled
01280   *          This parameter can be one of the following values:
01281   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01282   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01283   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01284   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01285   * @param  pData The source Buffer address.
01286   * @param  Length The length of data to be transferred from memory to TIM peripheral
01287   * @retval HAL status
01288 */
01289 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01290 {
01291   /* Check the parameters */
01292   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01293
01294   if((htim->State == HAL_TIM_STATE_BUSY))
01295   {
01296      return HAL_BUSY;
01297   }
01298   else if((htim->State == HAL_TIM_STATE_READY))
01299   {
01300     if(((uint32_t)pData == 0U ) && (Length > 0U))
01301     {
01302       return HAL_ERROR;
01303     }
01304     else
01305     {
01306       htim->State = HAL_TIM_STATE_BUSY;
01307     }
01308   }
01309   switch (Channel)
01310   {
01311     case TIM_CHANNEL_1:
01312     {
01313       /* Set the DMA Period elapsed callback */
01314       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01315
01316       /* Set the DMA error callback */
01317       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01318
01319       /* Enable the DMA channel */
01320       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
01321
01322       /* Enable the TIM Capture/Compare 1 DMA request */
01323       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01324     }
01325     break;
01326
01327     case TIM_CHANNEL_2:
01328     {
01329       /* Set the DMA Period elapsed callback */
01330       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01331
01332       /* Set the DMA error callback */
01333       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01334
01335       /* Enable the DMA channel */
01336       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
01337
01338       /* Enable the TIM Capture/Compare 2 DMA request */
01339       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01340     }
01341     break;
01342
01343     case TIM_CHANNEL_3:
01344     {
01345       /* Set the DMA Period elapsed callback */
01346       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01347
01348       /* Set the DMA error callback */
01349       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01350
01351       /* Enable the DMA channel */
01352       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
01353
01354       /* Enable the TIM Output Capture/Compare 3 request */
01355       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01356     }
01357     break;
01358
01359     case TIM_CHANNEL_4:
01360     {
01361      /* Set the DMA Period elapsed callback */
01362       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01363
01364       /* Set the DMA error callback */
01365       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01366
01367       /* Enable the DMA channel */
01368       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
01369
01370       /* Enable the TIM Capture/Compare 4 DMA request */
01371       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01372     }
01373     break;
01374
01375     default:
01376     break;
01377   }
01378
01379   /* Enable the Capture compare channel */
01380   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01381
01382   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01383   {
01384     /* Enable the main output */
01385     __HAL_TIM_MOE_ENABLE(htim);
01386   }
01387
01388   /* Enable the Peripheral */
01389   __HAL_TIM_ENABLE(htim);
01390
01391   /* Return function status */
01392   return HAL_OK;
01393 }
01394
01395 /**
01396   * @brief  Stops the TIM PWM signal generation in DMA mode.
01397   * @param  htim TIM handle
01398   * @param  Channel TIM Channels to be disabled
01399   *          This parameter can be one of the following values:
01400   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01401   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01402   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01403   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01404   * @retval HAL status
01405 */
01406 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01407 {
01408   /* Check the parameters */
01409   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01410
01411   switch (Channel)
01412   {
01413     case TIM_CHANNEL_1:
01414     {
01415       /* Disable the TIM Capture/Compare 1 DMA request */
01416       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01417     }
01418     break;
01419
01420     case TIM_CHANNEL_2:
01421     {
01422       /* Disable the TIM Capture/Compare 2 DMA request */
01423       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01424     }
01425     break;
01426
01427     case TIM_CHANNEL_3:
01428     {
01429       /* Disable the TIM Capture/Compare 3 DMA request */
01430       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01431     }
01432     break;
01433
01434     case TIM_CHANNEL_4:
01435     {
01436       /* Disable the TIM Capture/Compare 4 interrupt */
01437       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01438     }
01439     break;
01440
01441     default:
01442     break;
01443   }
01444
01445   /* Disable the Capture compare channel */
01446   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01447
01448   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01449   {
01450     /* Disable the Main Ouput */
01451     __HAL_TIM_MOE_DISABLE(htim);
01452   }
01453
01454   /* Disable the Peripheral */
01455   __HAL_TIM_DISABLE(htim);
01456
01457   /* Change the htim state */
01458   htim->State = HAL_TIM_STATE_READY;
01459
01460   /* Return function status */
01461   return HAL_OK;
01462 }
01463
01464 /**
01465   * @}
01466   */
01467
01468 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
01469  *  @brief    Time Input Capture functions
01470  *
01471 @verbatim
01472   ==============================================================================
01473               ##### Time Input Capture functions #####
01474   ==============================================================================
01475  [..]
01476    This section provides functions allowing to:
01477    (+) Initialize and configure the TIM Input Capture.
01478    (+) De-initialize the TIM Input Capture.
01479    (+) Start the Time Input Capture.
01480    (+) Stop the Time Input Capture.
01481    (+) Start the Time Input Capture and enable interrupt.
01482    (+) Stop the Time Input Capture and disable interrupt.
01483    (+) Start the Time Input Capture and enable DMA transfer.
01484    (+) Stop the Time Input Capture and disable DMA transfer.
01485
01486 @endverbatim
01487   * @{
01488   */
01489 /**
01490   * @brief  Initializes the TIM Input Capture Time base according to the specified
01491   *         parameters in the TIM_HandleTypeDef and create the associated handle.
01492   * @param  htim TIM Input Capture handle
01493   * @retval HAL status
01494   */
01495 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
01496 {
01497   /* Check the TIM handle allocation */
01498   if(htim == NULL)
01499   {
01500     return HAL_ERROR;
01501   }
01502
01503   /* Check the parameters */
01504   assert_param(IS_TIM_INSTANCE(htim->Instance));
01505   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01506   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01507   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
01508
01509   if(htim->State == HAL_TIM_STATE_RESET)
01510   {
01511     /* Allocate lock resource and initialize it */
01512     htim->Lock = HAL_UNLOCKED;
01513
01514     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01515     HAL_TIM_IC_MspInit(htim);
01516   }
01517
01518   /* Set the TIM state */
01519   htim->State= HAL_TIM_STATE_BUSY;
01520
01521   /* Init the base time for the input capture */
01522   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01523
01524   /* Initialize the TIM state*/
01525   htim->State= HAL_TIM_STATE_READY;
01526
01527   return HAL_OK;
01528 }
01529
01530 /**
01531   * @brief  DeInitializes the TIM peripheral
01532   * @param  htim TIM Input Capture handle
01533   * @retval HAL status
01534   */
01535 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
01536 {
01537   /* Check the parameters */
01538   assert_param(IS_TIM_INSTANCE(htim->Instance));
01539
01540   htim->State = HAL_TIM_STATE_BUSY;
01541
01542   /* Disable the TIM Peripheral Clock */
01543   __HAL_TIM_DISABLE(htim);
01544
01545   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01546   HAL_TIM_IC_MspDeInit(htim);
01547
01548   /* Change TIM state */
01549   htim->State = HAL_TIM_STATE_RESET;
01550
01551   /* Release Lock */
01552   __HAL_UNLOCK(htim);
01553
01554   return HAL_OK;
01555 }
01556
01557 /**
01558   * @brief  Initializes the TIM Input Capture MSP.
01559   * @param  htim TIM handle
01560   * @retval None
01561   */
01562 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
01563 {
01564   /* Prevent unused argument(s) compilation warning */
01565   UNUSED(htim);
01566
01567   /* NOTE : This function Should not be modified, when the callback is needed,
01568             the HAL_TIM_IC_MspInit could be implemented in the user file
01569    */
01570 }
01571
01572 /**
01573   * @brief  DeInitializes TIM Input Capture MSP.
01574   * @param  htim TIM handle
01575   * @retval None
01576   */
01577 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
01578 {
01579   /* Prevent unused argument(s) compilation warning */
01580   UNUSED(htim);
01581
01582   /* NOTE : This function Should not be modified, when the callback is needed,
01583             the HAL_TIM_IC_MspDeInit could be implemented in the user file
01584    */
01585 }
01586
01587 /**
01588   * @brief  Starts the TIM Input Capture measurement.
01589   * @param  htim TIM Input Capture handle
01590   * @param  Channel TIM Channels to be enabled
01591   *          This parameter can be one of the following values:
01592   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01593   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01594   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01595   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01596   * @retval HAL status
01597 */
01598 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
01599 {
01600   /* Check the parameters */
01601   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01602
01603   /* Enable the Input Capture channel */
01604   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01605
01606   /* Enable the Peripheral */
01607   __HAL_TIM_ENABLE(htim);
01608
01609   /* Return function status */
01610   return HAL_OK;
01611 }
01612
01613 /**
01614   * @brief  Stops the TIM Input Capture measurement.
01615   * @param  htim TIM handle
01616   * @param  Channel TIM Channels to be disabled
01617   *          This parameter can be one of the following values:
01618   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01619   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01620   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01621   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01622   * @retval HAL status
01623 */
01624 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01625 {
01626   /* Check the parameters */
01627   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01628
01629   /* Disable the Input Capture channel */
01630   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01631
01632   /* Disable the Peripheral */
01633   __HAL_TIM_DISABLE(htim);
01634
01635   /* Return function status */
01636   return HAL_OK;
01637 }
01638
01639 /**
01640   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
01641   * @param  htim TIM Input Capture handle
01642   * @param  Channel TIM Channels to be enabled
01643   *          This parameter can be one of the following values:
01644   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01645   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01646   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01647   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01648   * @retval HAL status
01649 */
01650 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01651 {
01652   /* Check the parameters */
01653   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01654
01655   switch (Channel)
01656   {
01657     case TIM_CHANNEL_1:
01658     {
01659       /* Enable the TIM Capture/Compare 1 interrupt */
01660       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01661     }
01662     break;
01663
01664     case TIM_CHANNEL_2:
01665     {
01666       /* Enable the TIM Capture/Compare 2 interrupt */
01667       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01668     }
01669     break;
01670
01671     case TIM_CHANNEL_3:
01672     {
01673       /* Enable the TIM Capture/Compare 3 interrupt */
01674       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01675     }
01676     break;
01677
01678     case TIM_CHANNEL_4:
01679     {
01680       /* Enable the TIM Capture/Compare 4 interrupt */
01681       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01682     }
01683     break;
01684
01685     default:
01686     break;
01687   }
01688   /* Enable the Input Capture channel */
01689   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01690
01691   /* Enable the Peripheral */
01692   __HAL_TIM_ENABLE(htim);
01693
01694   /* Return function status */
01695   return HAL_OK;
01696 }
01697
01698 /**
01699   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
01700   * @param  htim TIM handle
01701   * @param  Channel TIM Channels to be disabled
01702   *          This parameter can be one of the following values:
01703   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01704   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01705   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01706   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01707   * @retval HAL status
01708 */
01709 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01710 {
01711   /* Check the parameters */
01712   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01713
01714   switch (Channel)
01715   {
01716     case TIM_CHANNEL_1:
01717     {
01718       /* Disable the TIM Capture/Compare 1 interrupt */
01719       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01720     }
01721     break;
01722
01723     case TIM_CHANNEL_2:
01724     {
01725       /* Disable the TIM Capture/Compare 2 interrupt */
01726       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01727     }
01728     break;
01729
01730     case TIM_CHANNEL_3:
01731     {
01732       /* Disable the TIM Capture/Compare 3 interrupt */
01733       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01734     }
01735     break;
01736
01737     case TIM_CHANNEL_4:
01738     {
01739       /* Disable the TIM Capture/Compare 4 interrupt */
01740       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01741     }
01742     break;
01743
01744     default:
01745     break;
01746   }
01747
01748   /* Disable the Input Capture channel */
01749   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01750
01751   /* Disable the Peripheral */
01752   __HAL_TIM_DISABLE(htim);
01753
01754   /* Return function status */
01755   return HAL_OK;
01756 }
01757
01758 /**
01759   * @brief  Starts the TIM Input Capture measurement in DMA mode.
01760   * @param  htim TIM Input Capture handle
01761   * @param  Channel TIM Channels to be enabled
01762   *          This parameter can be one of the following values:
01763   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01764   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01765   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01766   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01767   * @param  pData The destination Buffer address.
01768   * @param  Length The length of data to be transferred from TIM peripheral to memory.
01769   * @retval HAL status
01770 */
01771 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01772 {
01773   /* Check the parameters */
01774   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01775   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
01776
01777   if((htim->State == HAL_TIM_STATE_BUSY))
01778   {
01779      return HAL_BUSY;
01780   }
01781   else if((htim->State == HAL_TIM_STATE_READY))
01782   {
01783     if((pData == 0U ) && (Length > 0U))
01784     {
01785       return HAL_ERROR;
01786     }
01787     else
01788     {
01789       htim->State = HAL_TIM_STATE_BUSY;
01790     }
01791   }
01792
01793   switch (Channel)
01794   {
01795     case TIM_CHANNEL_1:
01796     {
01797       /* Set the DMA Period elapsed callback */
01798       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
01799
01800       /* Set the DMA error callback */
01801       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01802
01803       /* Enable the DMA channel */
01804       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
01805
01806       /* Enable the TIM Capture/Compare 1 DMA request */
01807       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01808     }
01809     break;
01810
01811     case TIM_CHANNEL_2:
01812     {
01813       /* Set the DMA Period elapsed callback */
01814       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
01815
01816       /* Set the DMA error callback */
01817       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01818
01819       /* Enable the DMA channel */
01820       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
01821
01822       /* Enable the TIM Capture/Compare 2  DMA request */
01823       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01824     }
01825     break;
01826
01827     case TIM_CHANNEL_3:
01828     {
01829       /* Set the DMA Period elapsed callback */
01830       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
01831
01832       /* Set the DMA error callback */
01833       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01834
01835       /* Enable the DMA channel */
01836       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
01837
01838       /* Enable the TIM Capture/Compare 3  DMA request */
01839       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01840     }
01841     break;
01842
01843     case TIM_CHANNEL_4:
01844     {
01845       /* Set the DMA Period elapsed callback */
01846       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
01847
01848       /* Set the DMA error callback */
01849       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01850
01851       /* Enable the DMA channel */
01852       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
01853
01854       /* Enable the TIM Capture/Compare 4  DMA request */
01855       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01856     }
01857     break;
01858
01859     default:
01860     break;
01861   }
01862
01863   /* Enable the Input Capture channel */
01864   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01865
01866   /* Enable the Peripheral */
01867   __HAL_TIM_ENABLE(htim);
01868
01869   /* Return function status */
01870   return HAL_OK;
01871 }
01872
01873 /**
01874   * @brief  Stops the TIM Input Capture measurement in DMA mode.
01875   * @param  htim TIM Input Capture handle
01876   * @param  Channel TIM Channels to be disabled
01877   *          This parameter can be one of the following values:
01878   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01879   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01880   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01881   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01882   * @retval HAL status
01883 */
01884 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01885 {
01886   /* Check the parameters */
01887   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01888   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
01889
01890   switch (Channel)
01891   {
01892     case TIM_CHANNEL_1:
01893     {
01894       /* Disable the TIM Capture/Compare 1 DMA request */
01895       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01896     }
01897     break;
01898
01899     case TIM_CHANNEL_2:
01900     {
01901       /* Disable the TIM Capture/Compare 2 DMA request */
01902       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01903     }
01904     break;
01905
01906     case TIM_CHANNEL_3:
01907     {
01908       /* Disable the TIM Capture/Compare 3  DMA request */
01909       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01910     }
01911     break;
01912
01913     case TIM_CHANNEL_4:
01914     {
01915       /* Disable the TIM Capture/Compare 4  DMA request */
01916       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01917     }
01918     break;
01919
01920     default:
01921     break;
01922   }
01923
01924   /* Disable the Input Capture channel */
01925   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01926
01927   /* Disable the Peripheral */
01928   __HAL_TIM_DISABLE(htim);
01929
01930   /* Change the htim state */
01931   htim->State = HAL_TIM_STATE_READY;
01932
01933   /* Return function status */
01934   return HAL_OK;
01935 }
01936 /**
01937   * @}
01938   */
01939
01940 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
01941  *  @brief    Time One Pulse functions
01942  *
01943 @verbatim
01944   ==============================================================================
01945                         ##### Time One Pulse functions #####
01946   ==============================================================================
01947   [..]
01948     This section provides functions allowing to:
01949     (+) Initialize and configure the TIM One Pulse.
01950     (+) De-initialize the TIM One Pulse.
01951     (+) Start the Time One Pulse.
01952     (+) Stop the Time One Pulse.
01953     (+) Start the Time One Pulse and enable interrupt.
01954     (+) Stop the Time One Pulse and disable interrupt.
01955     (+) Start the Time One Pulse and enable DMA transfer.
01956     (+) Stop the Time One Pulse and disable DMA transfer.
01957
01958 @endverbatim
01959   * @{
01960   */
01961 /**
01962   * @brief  Initializes the TIM One Pulse Time Base according to the specified
01963   *         parameters in the TIM_HandleTypeDef and create the associated handle.
01964   * @param  htim TIM OnePulse handle
01965   * @param  OnePulseMode Select the One pulse mode.
01966   *         This parameter can be one of the following values:
01967   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
01968   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
01969   * @retval HAL status
01970   */
01971 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
01972 {
01973   /* Check the TIM handle allocation */
01974   if(htim == NULL)
01975   {
01976     return HAL_ERROR;
01977   }
01978
01979   /* Check the parameters */
01980   assert_param(IS_TIM_INSTANCE(htim->Instance));
01981   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01982   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01983   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
01984   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
01985
01986   if(htim->State == HAL_TIM_STATE_RESET)
01987   {
01988     /* Allocate lock resource and initialize it */
01989     htim->Lock = HAL_UNLOCKED;
01990
01991     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01992     HAL_TIM_OnePulse_MspInit(htim);
01993   }
01994
01995   /* Set the TIM state */
01996   htim->State= HAL_TIM_STATE_BUSY;
01997
01998   /* Configure the Time base in the One Pulse Mode */
01999   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02000
02001   /* Reset the OPM Bit */
02002   htim->Instance->CR1 &= ~TIM_CR1_OPM;
02003
02004   /* Configure the OPM Mode */
02005   htim->Instance->CR1 |= OnePulseMode;
02006
02007   /* Initialize the TIM state*/
02008   htim->State= HAL_TIM_STATE_READY;
02009
02010   return HAL_OK;
02011 }
02012
02013 /**
02014   * @brief  DeInitializes the TIM One Pulse
02015   * @param  htim TIM One Pulse handle
02016   * @retval HAL status
02017   */
02018 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
02019 {
02020   /* Check the parameters */
02021   assert_param(IS_TIM_INSTANCE(htim->Instance));
02022
02023   htim->State = HAL_TIM_STATE_BUSY;
02024
02025   /* Disable the TIM Peripheral Clock */
02026   __HAL_TIM_DISABLE(htim);
02027
02028   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02029   HAL_TIM_OnePulse_MspDeInit(htim);
02030
02031   /* Change TIM state */
02032   htim->State = HAL_TIM_STATE_RESET;
02033
02034   /* Release Lock */
02035   __HAL_UNLOCK(htim);
02036
02037   return HAL_OK;
02038 }
02039
02040 /**
02041   * @brief  Initializes the TIM One Pulse MSP.
02042   * @param  htim TIM handle
02043   * @retval None
02044   */
02045 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
02046 {
02047   /* Prevent unused argument(s) compilation warning */
02048   UNUSED(htim);
02049
02050   /* NOTE : This function Should not be modified, when the callback is needed,
02051             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
02052    */
02053 }
02054
02055 /**
02056   * @brief  DeInitializes TIM One Pulse MSP.
02057   * @param  htim TIM handle
02058   * @retval None
02059   */
02060 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
02061 {
02062   /* Prevent unused argument(s) compilation warning */
02063   UNUSED(htim);
02064
02065   /* NOTE : This function Should not be modified, when the callback is needed,
02066             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
02067    */
02068 }
02069
02070 /**
02071   * @brief  Starts the TIM One Pulse signal generation.
02072   * @param  htim TIM One Pulse handle
02073   * @param  OutputChannel TIM Channels to be enabled
02074   *          This parameter can be one of the following values:
02075   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02076   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02077   * @retval HAL status
02078 */
02079 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02080 {
02081   /* Enable the Capture compare and the Input Capture channels
02082     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02083     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02084     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02085     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02086
02087     No need to enable the counter, it's enabled automatically by hardware
02088     (the counter starts in response to a stimulus and generate a pulse */
02089
02090   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02091   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02092
02093   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02094   {
02095     /* Enable the main output */
02096     __HAL_TIM_MOE_ENABLE(htim);
02097   }
02098
02099   /* Return function status */
02100   return HAL_OK;
02101 }
02102
02103 /**
02104   * @brief  Stops the TIM One Pulse signal generation.
02105   * @param  htim TIM One Pulse handle
02106   * @param  OutputChannel TIM Channels to be disable
02107   *          This parameter can be one of the following values:
02108   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02109   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02110   * @retval HAL status
02111 */
02112 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02113 {
02114   /* Disable the Capture compare and the Input Capture channels
02115   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02116   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02117   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02118   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02119
02120   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02121   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02122
02123   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02124   {
02125     /* Disable the Main Ouput */
02126     __HAL_TIM_MOE_DISABLE(htim);
02127   }
02128
02129   /* Disable the Peripheral */
02130   __HAL_TIM_DISABLE(htim);
02131
02132   /* Return function status */
02133   return HAL_OK;
02134 }
02135
02136 /**
02137   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
02138   * @param  htim TIM One Pulse handle
02139   * @param  OutputChannel TIM Channels to be enabled
02140   *          This parameter can be one of the following values:
02141   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02142   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02143   * @retval HAL status
02144 */
02145 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02146 {
02147   /* Enable the Capture compare and the Input Capture channels
02148     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02149     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02150     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02151     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02152
02153     No need to enable the counter, it's enabled automatically by hardware
02154     (the counter starts in response to a stimulus and generate a pulse */
02155
02156   /* Enable the TIM Capture/Compare 1 interrupt */
02157   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02158
02159   /* Enable the TIM Capture/Compare 2 interrupt */
02160   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02161
02162   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02163   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02164
02165   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02166   {
02167     /* Enable the main output */
02168     __HAL_TIM_MOE_ENABLE(htim);
02169   }
02170
02171   /* Return function status */
02172   return HAL_OK;
02173 }
02174
02175 /**
02176   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
02177   * @param  htim TIM One Pulse handle
02178   * @param  OutputChannel TIM Channels to be enabled
02179   *          This parameter can be one of the following values:
02180   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02181   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02182   * @retval HAL status
02183 */
02184 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02185 {
02186   /* Disable the TIM Capture/Compare 1 interrupt */
02187   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02188
02189   /* Disable the TIM Capture/Compare 2 interrupt */
02190   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02191
02192   /* Disable the Capture compare and the Input Capture channels
02193   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02194   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02195   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02196   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02197   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02198   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02199
02200   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02201   {
02202     /* Disable the Main Ouput */
02203     __HAL_TIM_MOE_DISABLE(htim);
02204   }
02205
02206   /* Disable the Peripheral */
02207    __HAL_TIM_DISABLE(htim);
02208
02209   /* Return function status */
02210   return HAL_OK;
02211 }
02212
02213 /**
02214   * @}
02215   */
02216
02217 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
02218  *  @brief    Time Encoder functions
02219  *
02220 @verbatim
02221   ==============================================================================
02222                           ##### Time Encoder functions #####
02223   ==============================================================================
02224   [..]
02225     This section provides functions allowing to:
02226     (+) Initialize and configure the TIM Encoder.
02227     (+) De-initialize the TIM Encoder.
02228     (+) Start the Time Encoder.
02229     (+) Stop the Time Encoder.
02230     (+) Start the Time Encoder and enable interrupt.
02231     (+) Stop the Time Encoder and disable interrupt.
02232     (+) Start the Time Encoder and enable DMA transfer.
02233     (+) Stop the Time Encoder and disable DMA transfer.
02234
02235 @endverbatim
02236   * @{
02237   */
02238 /**
02239   * @brief  Initializes the TIM Encoder Interface and create the associated handle.
02240   * @param  htim TIM Encoder Interface handle
02241   * @param  sConfig TIM Encoder Interface configuration structure
02242   * @retval HAL status
02243   */
02244 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)
02245 {
02246   uint32_t tmpsmcr = 0U;
02247   uint32_t tmpccmr1 = 0U;
02248   uint32_t tmpccer = 0U;
02249
02250   /* Check the TIM handle allocation */
02251   if(htim == NULL)
02252   {
02253     return HAL_ERROR;
02254   }
02255
02256   /* Check the parameters */
02257   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02258   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
02259   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
02260   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
02261   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
02262   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
02263   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
02264   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
02265   assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
02266   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
02267   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
02268   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
02269   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
02270
02271   if(htim->State == HAL_TIM_STATE_RESET)
02272   {
02273     /* Allocate lock resource and initialize it */
02274     htim->Lock = HAL_UNLOCKED;
02275
02276     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02277     HAL_TIM_Encoder_MspInit(htim);
02278   }
02279
02280   /* Set the TIM state */
02281   htim->State= HAL_TIM_STATE_BUSY;
02282
02283   /* Reset the SMS bits */
02284   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
02285
02286   /* Configure the Time base in the Encoder Mode */
02287   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02288
02289   /* Get the TIMx SMCR register value */
02290   tmpsmcr = htim->Instance->SMCR;
02291
02292   /* Get the TIMx CCMR1 register value */
02293   tmpccmr1 = htim->Instance->CCMR1;
02294
02295   /* Get the TIMx CCER register value */
02296   tmpccer = htim->Instance->CCER;
02297
02298   /* Set the encoder Mode */
02299   tmpsmcr |= sConfig->EncoderMode;
02300
02301   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
02302   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
02303   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
02304
02305   /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
02306   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
02307   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
02308   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
02309   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
02310
02311   /* Set the TI1 and the TI2 Polarities */
02312   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
02313   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
02314   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
02315
02316   /* Write to TIMx SMCR */
02317   htim->Instance->SMCR = tmpsmcr;
02318
02319   /* Write to TIMx CCMR1 */
02320   htim->Instance->CCMR1 = tmpccmr1;
02321
02322   /* Write to TIMx CCER */
02323   htim->Instance->CCER = tmpccer;
02324
02325   /* Initialize the TIM state*/
02326   htim->State= HAL_TIM_STATE_READY;
02327
02328   return HAL_OK;
02329 }
02330
02331
02332 /**
02333   * @brief  DeInitializes the TIM Encoder interface
02334   * @param  htim TIM Encoder handle
02335   * @retval HAL status
02336   */
02337 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
02338 {
02339   /* Check the parameters */
02340   assert_param(IS_TIM_INSTANCE(htim->Instance));
02341
02342   htim->State = HAL_TIM_STATE_BUSY;
02343
02344   /* Disable the TIM Peripheral Clock */
02345   __HAL_TIM_DISABLE(htim);
02346
02347   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02348   HAL_TIM_Encoder_MspDeInit(htim);
02349
02350   /* Change TIM state */
02351   htim->State = HAL_TIM_STATE_RESET;
02352
02353   /* Release Lock */
02354   __HAL_UNLOCK(htim);
02355
02356   return HAL_OK;
02357 }
02358
02359 /**
02360   * @brief  Initializes the TIM Encoder Interface MSP.
02361   * @param  htim TIM handle
02362   * @retval None
02363   */
02364 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
02365 {
02366   /* Prevent unused argument(s) compilation warning */
02367   UNUSED(htim);
02368
02369   /* NOTE : This function Should not be modified, when the callback is needed,
02370             the HAL_TIM_Encoder_MspInit could be implemented in the user file
02371    */
02372 }
02373
02374 /**
02375   * @brief  DeInitializes TIM Encoder Interface MSP.
02376   * @param  htim TIM handle
02377   * @retval None
02378   */
02379 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
02380 {
02381   /* Prevent unused argument(s) compilation warning */
02382   UNUSED(htim);
02383
02384   /* NOTE : This function Should not be modified, when the callback is needed,
02385             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
02386    */
02387 }
02388
02389 /**
02390   * @brief  Starts the TIM Encoder Interface.
02391   * @param  htim TIM Encoder Interface handle
02392   * @param  Channel TIM Channels to be enabled
02393   *          This parameter can be one of the following values:
02394   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02395   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02396   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02397   * @retval HAL status
02398 */
02399 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
02400 {
02401   /* Check the parameters */
02402   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02403
02404   /* Enable the encoder interface channels */
02405   switch (Channel)
02406   {
02407   case TIM_CHANNEL_1:
02408     {
02409       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02410       break;
02411     }
02412   case TIM_CHANNEL_2:
02413     {
02414       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02415       break;
02416     }
02417   default :
02418     {
02419       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02420       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02421       break;
02422     }
02423   }
02424   /* Enable the Peripheral */
02425   __HAL_TIM_ENABLE(htim);
02426
02427   /* Return function status */
02428   return HAL_OK;
02429 }
02430
02431 /**
02432   * @brief  Stops the TIM Encoder Interface.
02433   * @param  htim TIM Encoder Interface handle
02434   * @param  Channel TIM Channels to be disabled
02435   *          This parameter can be one of the following values:
02436   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02437   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02438   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02439   * @retval HAL status
02440 */
02441 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
02442 {
02443   /* Check the parameters */
02444   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02445
02446   /* Disable the Input Capture channels 1 and 2
02447   (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02448   switch (Channel)
02449   {
02450   case TIM_CHANNEL_1:
02451     {
02452       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02453       break;
02454     }
02455   case TIM_CHANNEL_2:
02456     {
02457       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02458       break;
02459     }
02460   default :
02461     {
02462       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02463       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02464       break;
02465     }
02466   }
02467
02468   /* Disable the Peripheral */
02469   __HAL_TIM_DISABLE(htim);
02470
02471   /* Return function status */
02472   return HAL_OK;
02473 }
02474
02475 /**
02476   * @brief  Starts the TIM Encoder Interface in interrupt mode.
02477   * @param  htim TIM Encoder Interface handle
02478   * @param  Channel TIM Channels to be enabled
02479   *          This parameter can be one of the following values:
02480   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02481   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02482   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02483   * @retval HAL status
02484 */
02485 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02486 {
02487   /* Check the parameters */
02488   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02489
02490   /* Enable the encoder interface channels */
02491   /* Enable the capture compare Interrupts 1 and/or 2U */
02492   switch (Channel)
02493   {
02494   case TIM_CHANNEL_1:
02495     {
02496       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02497       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02498       break;
02499     }
02500   case TIM_CHANNEL_2:
02501     {
02502       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02503       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02504       break;
02505     }
02506   default :
02507     {
02508       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02509       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02510       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02511       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02512       break;
02513     }
02514   }
02515
02516   /* Enable the Peripheral */
02517   __HAL_TIM_ENABLE(htim);
02518
02519   /* Return function status */
02520   return HAL_OK;
02521 }
02522
02523 /**
02524   * @brief  Stops the TIM Encoder Interface in interrupt mode.
02525   * @param  htim TIM Encoder Interface handle
02526   * @param  Channel TIM Channels to be disabled
02527   *          This parameter can be one of the following values:
02528   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02529   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02530   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02531   * @retval HAL status
02532 */
02533 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02534 {
02535   /* Check the parameters */
02536   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02537
02538   /* Disable the Input Capture channels 1 and 2
02539   (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02540   if(Channel == TIM_CHANNEL_1)
02541   {
02542     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02543
02544     /* Disable the capture compare Interrupts 1U */
02545     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02546   }
02547   else if(Channel == TIM_CHANNEL_2)
02548   {
02549     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02550
02551     /* Disable the capture compare Interrupts 2U */
02552     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02553   }
02554   else
02555   {
02556     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02557     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02558
02559     /* Disable the capture compare Interrupts 1 and 2U */
02560     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02561     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02562   }
02563
02564   /* Disable the Peripheral */
02565   __HAL_TIM_DISABLE(htim);
02566
02567   /* Change the htim state */
02568   htim->State = HAL_TIM_STATE_READY;
02569
02570   /* Return function status */
02571   return HAL_OK;
02572 }
02573
02574 /**
02575   * @brief  Starts the TIM Encoder Interface in DMA mode.
02576   * @param  htim TIM Encoder Interface handle
02577   * @param  Channel TIM Channels to be enabled
02578   *          This parameter can be one of the following values:
02579   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02580   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02581   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02582   * @param  pData1: The destination Buffer address for IC1.
02583   * @param  pData2: The destination Buffer address for IC2.
02584   * @param  Length The length of data to be transferred from TIM peripheral to memory.
02585   * @retval HAL status
02586 */
02587 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
02588 {
02589   /* Check the parameters */
02590   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02591
02592   if((htim->State == HAL_TIM_STATE_BUSY))
02593   {
02594     return HAL_BUSY;
02595   }
02596   else if((htim->State == HAL_TIM_STATE_READY))
02597   {
02598     if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
02599     {
02600       return HAL_ERROR;
02601     }
02602     else
02603     {
02604       htim->State = HAL_TIM_STATE_BUSY;
02605     }
02606   }
02607
02608   switch (Channel)
02609   {
02610   case TIM_CHANNEL_1:
02611     {
02612       /* Set the DMA Period elapsed callback */
02613       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
02614
02615       /* Set the DMA error callback */
02616       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
02617
02618       /* Enable the DMA channel */
02619       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
02620
02621       /* Enable the TIM Input Capture DMA request */
02622       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02623
02624       /* Enable the Peripheral */
02625       __HAL_TIM_ENABLE(htim);
02626
02627       /* Enable the Capture compare channel */
02628       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02629     }
02630     break;
02631
02632   case TIM_CHANNEL_2:
02633     {
02634       /* Set the DMA Period elapsed callback */
02635       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
02636
02637       /* Set the DMA error callback */
02638       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
02639       /* Enable the DMA channel */
02640       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
02641
02642       /* Enable the TIM Input Capture  DMA request */
02643       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02644
02645       /* Enable the Peripheral */
02646       __HAL_TIM_ENABLE(htim);
02647
02648       /* Enable the Capture compare channel */
02649       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02650     }
02651     break;
02652
02653   case TIM_CHANNEL_ALL:
02654     {
02655       /* Set the DMA Period elapsed callback */
02656       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
02657
02658       /* Set the DMA error callback */
02659       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
02660
02661       /* Enable the DMA channel */
02662       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
02663
02664       /* Set the DMA Period elapsed callback */
02665       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
02666
02667       /* Set the DMA error callback */
02668       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
02669
02670       /* Enable the DMA channel */
02671       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
02672
02673       /* Enable the Peripheral */
02674       __HAL_TIM_ENABLE(htim);
02675
02676       /* Enable the Capture compare channel */
02677       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02678       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02679
02680       /* Enable the TIM Input Capture  DMA request */
02681       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02682       /* Enable the TIM Input Capture  DMA request */
02683       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02684     }
02685     break;
02686
02687   default:
02688     break;
02689   }
02690   /* Return function status */
02691   return HAL_OK;
02692 }
02693
02694 /**
02695   * @brief  Stops the TIM Encoder Interface in DMA mode.
02696   * @param  htim TIM Encoder Interface handle
02697   * @param  Channel TIM Channels to be enabled
02698   *          This parameter can be one of the following values:
02699   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02700   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02701   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02702   * @retval HAL status
02703 */
02704 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
02705 {
02706   /* Check the parameters */
02707   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02708
02709   /* Disable the Input Capture channels 1 and 2
02710   (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02711   if(Channel == TIM_CHANNEL_1)
02712   {
02713     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02714
02715     /* Disable the capture compare DMA Request 1U */
02716     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02717   }
02718   else if(Channel == TIM_CHANNEL_2)
02719   {
02720     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02721
02722     /* Disable the capture compare DMA Request 2U */
02723     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02724   }
02725   else
02726   {
02727     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02728     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02729
02730     /* Disable the capture compare DMA Request 1 and 2U */
02731     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02732     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02733   }
02734
02735   /* Disable the Peripheral */
02736   __HAL_TIM_DISABLE(htim);
02737
02738   /* Change the htim state */
02739   htim->State = HAL_TIM_STATE_READY;
02740
02741   /* Return function status */
02742   return HAL_OK;
02743 }
02744
02745 /**
02746   * @}
02747   */
02748 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
02749  *  @brief    IRQ handler management
02750  *
02751 @verbatim
02752   ==============================================================================
02753                         ##### IRQ handler management #####
02754   ==============================================================================
02755   [..]
02756     This section provides Timer IRQ handler function.
02757
02758 @endverbatim
02759   * @{
02760   */
02761 /**
02762   * @brief  This function handles TIM interrupts requests.
02763   * @param  htim TIM  handle
02764   * @retval None
02765   */
02766 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
02767 {
02768   /* Capture compare 1 event */
02769   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
02770   {
02771     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
02772     {
02773       {
02774         __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
02775         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
02776
02777         /* Input capture event */
02778         if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
02779         {
02780           HAL_TIM_IC_CaptureCallback(htim);
02781         }
02782         /* Output compare event */
02783         else
02784         {
02785           HAL_TIM_OC_DelayElapsedCallback(htim);
02786           HAL_TIM_PWM_PulseFinishedCallback(htim);
02787         }
02788         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02789       }
02790     }
02791   }
02792   /* Capture compare 2 event */
02793   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
02794   {
02795     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
02796     {
02797       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
02798       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
02799       /* Input capture event */
02800       if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
02801       {
02802         HAL_TIM_IC_CaptureCallback(htim);
02803       }
02804       /* Output compare event */
02805       else
02806       {
02807         HAL_TIM_OC_DelayElapsedCallback(htim);
02808         HAL_TIM_PWM_PulseFinishedCallback(htim);
02809       }
02810       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02811     }
02812   }
02813   /* Capture compare 3 event */
02814   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
02815   {
02816     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
02817     {
02818       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
02819       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
02820       /* Input capture event */
02821       if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
02822       {
02823         HAL_TIM_IC_CaptureCallback(htim);
02824       }
02825       /* Output compare event */
02826       else
02827       {
02828         HAL_TIM_OC_DelayElapsedCallback(htim);
02829         HAL_TIM_PWM_PulseFinishedCallback(htim);
02830       }
02831       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02832     }
02833   }
02834   /* Capture compare 4 event */
02835   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
02836   {
02837     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
02838     {
02839       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
02840       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
02841       /* Input capture event */
02842       if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
02843       {
02844         HAL_TIM_IC_CaptureCallback(htim);
02845       }
02846       /* Output compare event */
02847       else
02848       {
02849         HAL_TIM_OC_DelayElapsedCallback(htim);
02850         HAL_TIM_PWM_PulseFinishedCallback(htim);
02851       }
02852       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02853     }
02854   }
02855   /* TIM Update event */
02856   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
02857   {
02858     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
02859     {
02860       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
02861       HAL_TIM_PeriodElapsedCallback(htim);
02862     }
02863   }
02864   /* TIM Break input event */
02865   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
02866   {
02867     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
02868     {
02869       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
02870       HAL_TIMEx_BreakCallback(htim);
02871     }
02872   }
02873
02874 #if defined(TIM_FLAG_BREAK2)
02875   /* TIM Break input 2 event */
02876   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
02877   {
02878     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
02879     {
02880       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
02881       HAL_TIMEx_Break2Callback(htim);
02882     }
02883   }
02884 #endif
02885
02886   /* TIM Trigger detection event */
02887   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
02888   {
02889     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
02890     {
02891       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
02892       HAL_TIM_TriggerCallback(htim);
02893     }
02894   }
02895   /* TIM commutation event */
02896   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
02897   {
02898     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
02899     {
02900       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
02901       HAL_TIMEx_CommutationCallback(htim);
02902     }
02903   }
02904 }
02905
02906 /**
02907   * @}
02908   */
02909
02910 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
02911  *  @brief      Peripheral Control functions
02912  *
02913 @verbatim
02914   ==============================================================================
02915                    ##### Peripheral Control functions #####
02916   ==============================================================================
02917  [..]
02918    This section provides functions allowing to:
02919       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
02920       (+) Configure External Clock source.
02921       (+) Configure Complementary channels, break features and dead time.
02922       (+) Configure Master and the Slave synchronization.
02923       (+) Configure the DMA Burst Mode.
02924
02925 @endverbatim
02926   * @{
02927   */
02928
02929 /**
02930   * @brief  Initializes the TIM Output Compare Channels according to the specified
02931   *         parameters in the TIM_OC_InitTypeDef.
02932   * @param  htim TIM Output Compare handle
02933   * @param  sConfig TIM Output Compare configuration structure
02934   * @param  Channel TIM Channels to be enabled
02935   *          This parameter can be one of the following values:
02936   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02937   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02938   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02939   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02940   * @retval HAL status
02941   */
02942 __weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
02943 {
02944   /* Check the parameters */
02945   assert_param(IS_TIM_CHANNELS(Channel));
02946   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
02947   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
02948
02949   /* Check input state */
02950   __HAL_LOCK(htim);
02951
02952   htim->State = HAL_TIM_STATE_BUSY;
02953
02954   switch (Channel)
02955   {
02956     case TIM_CHANNEL_1:
02957     {
02958       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
02959       /* Configure the TIM Channel 1 in Output Compare */
02960       TIM_OC1_SetConfig(htim->Instance, sConfig);
02961     }
02962     break;
02963
02964     case TIM_CHANNEL_2:
02965     {
02966       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02967       /* Configure the TIM Channel 2 in Output Compare */
02968       TIM_OC2_SetConfig(htim->Instance, sConfig);
02969     }
02970     break;
02971
02972     case TIM_CHANNEL_3:
02973     {
02974        assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
02975       /* Configure the TIM Channel 3 in Output Compare */
02976       TIM_OC3_SetConfig(htim->Instance, sConfig);
02977     }
02978     break;
02979
02980     case TIM_CHANNEL_4:
02981     {
02982       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
02983        /* Configure the TIM Channel 4 in Output Compare */
02984        TIM_OC4_SetConfig(htim->Instance, sConfig);
02985     }
02986     break;
02987
02988     default:
02989     break;
02990   }
02991   htim->State = HAL_TIM_STATE_READY;
02992
02993   __HAL_UNLOCK(htim);
02994
02995   return HAL_OK;
02996 }
02997
02998 /**
02999   * @brief  Initializes the TIM Input Capture Channels according to the specified
03000   *         parameters in the TIM_IC_InitTypeDef.
03001   * @param  htim TIM IC handle
03002   * @param  sConfig TIM Input Capture configuration structure
03003   * @param  Channel TIM Channels to be enabled
03004   *          This parameter can be one of the following values:
03005   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03006   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03007   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03008   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03009   * @retval HAL status
03010   */
03011 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
03012 {
03013   /* Check the parameters */
03014   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03015   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
03016   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
03017   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
03018   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
03019
03020   __HAL_LOCK(htim);
03021
03022   htim->State = HAL_TIM_STATE_BUSY;
03023
03024   if (Channel == TIM_CHANNEL_1)
03025   {
03026     /* TI1 Configuration */
03027     TIM_TI1_SetConfig(htim->Instance,
03028                sConfig->ICPolarity,
03029                sConfig->ICSelection,
03030                sConfig->ICFilter);
03031
03032     /* Reset the IC1PSC Bits */
03033     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03034
03035     /* Set the IC1PSC value */
03036     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
03037   }
03038   else if (Channel == TIM_CHANNEL_2)
03039   {
03040     /* TI2 Configuration */
03041     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03042
03043     TIM_TI2_SetConfig(htim->Instance,
03044                       sConfig->ICPolarity,
03045                       sConfig->ICSelection,
03046                       sConfig->ICFilter);
03047
03048     /* Reset the IC2PSC Bits */
03049     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03050
03051     /* Set the IC2PSC value */
03052     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
03053   }
03054   else if (Channel == TIM_CHANNEL_3)
03055   {
03056     /* TI3 Configuration */
03057     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03058
03059     TIM_TI3_SetConfig(htim->Instance,
03060                sConfig->ICPolarity,
03061                sConfig->ICSelection,
03062                sConfig->ICFilter);
03063
03064     /* Reset the IC3PSC Bits */
03065     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
03066
03067     /* Set the IC3PSC value */
03068     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
03069   }
03070   else
03071   {
03072     /* TI4 Configuration */
03073     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03074
03075     TIM_TI4_SetConfig(htim->Instance,
03076                sConfig->ICPolarity,
03077                sConfig->ICSelection,
03078                sConfig->ICFilter);
03079
03080     /* Reset the IC4PSC Bits */
03081     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
03082
03083     /* Set the IC4PSC value */
03084     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
03085   }
03086
03087   htim->State = HAL_TIM_STATE_READY;
03088
03089   __HAL_UNLOCK(htim);
03090
03091   return HAL_OK;
03092 }
03093
03094 /**
03095   * @brief  Initializes the TIM PWM  channels according to the specified
03096   *         parameters in the TIM_OC_InitTypeDef.
03097   * @param  htim TIM handle
03098   * @param  sConfig TIM PWM configuration structure
03099   * @param  Channel TIM Channels to be enabled
03100   *          This parameter can be one of the following values:
03101   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03102   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03103   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03104   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03105   * @retval HAL status
03106   */
03107 __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
03108 {
03109   __HAL_LOCK(htim);
03110
03111   /* Check the parameters */
03112   assert_param(IS_TIM_CHANNELS(Channel));
03113   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
03114   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
03115   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
03116
03117   htim->State = HAL_TIM_STATE_BUSY;
03118
03119   switch (Channel)
03120   {
03121     case TIM_CHANNEL_1:
03122     {
03123       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03124       /* Configure the Channel 1 in PWM mode */
03125       TIM_OC1_SetConfig(htim->Instance, sConfig);
03126
03127       /* Set the Preload enable bit for channel1 */
03128       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
03129
03130       /* Configure the Output Fast mode */
03131       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
03132       htim->Instance->CCMR1 |= sConfig->OCFastMode;
03133     }
03134     break;
03135
03136     case TIM_CHANNEL_2:
03137     {
03138       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03139       /* Configure the Channel 2 in PWM mode */
03140       TIM_OC2_SetConfig(htim->Instance, sConfig);
03141
03142       /* Set the Preload enable bit for channel2 */
03143       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
03144
03145       /* Configure the Output Fast mode */
03146       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
03147       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
03148     }
03149     break;
03150
03151     case TIM_CHANNEL_3:
03152     {
03153       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03154       /* Configure the Channel 3 in PWM mode */
03155       TIM_OC3_SetConfig(htim->Instance, sConfig);
03156
03157       /* Set the Preload enable bit for channel3 */
03158       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
03159
03160      /* Configure the Output Fast mode */
03161       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
03162       htim->Instance->CCMR2 |= sConfig->OCFastMode;
03163     }
03164     break;
03165
03166     case TIM_CHANNEL_4:
03167     {
03168       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03169       /* Configure the Channel 4 in PWM mode */
03170       TIM_OC4_SetConfig(htim->Instance, sConfig);
03171
03172       /* Set the Preload enable bit for channel4 */
03173       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
03174
03175      /* Configure the Output Fast mode */
03176       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
03177       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
03178     }
03179     break;
03180
03181     default:
03182     break;
03183   }
03184
03185   htim->State = HAL_TIM_STATE_READY;
03186
03187   __HAL_UNLOCK(htim);
03188
03189   return HAL_OK;
03190 }
03191
03192 /**
03193   * @brief  Initializes the TIM One Pulse Channels according to the specified
03194   *         parameters in the TIM_OnePulse_InitTypeDef.
03195   * @param  htim TIM One Pulse handle
03196   * @param  sConfig TIM One Pulse configuration structure
03197   * @param  OutputChannel TIM Channels to be enabled
03198   *          This parameter can be one of the following values:
03199   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03200   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03201   * @param  InputChannel TIM Channels to be enabled
03202   *          This parameter can be one of the following values:
03203   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03204   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03205   * @retval HAL status
03206   */
03207 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel)
03208 {
03209   TIM_OC_InitTypeDef temp1;
03210
03211   /* Check the parameters */
03212   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
03213   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
03214
03215   if(OutputChannel != InputChannel)
03216   {
03217   __HAL_LOCK(htim);
03218
03219   htim->State = HAL_TIM_STATE_BUSY;
03220
03221   /* Extract the Ouput compare configuration from sConfig structure */
03222   temp1.OCMode = sConfig->OCMode;
03223   temp1.Pulse = sConfig->Pulse;
03224   temp1.OCPolarity = sConfig->OCPolarity;
03225   temp1.OCNPolarity = sConfig->OCNPolarity;
03226   temp1.OCIdleState = sConfig->OCIdleState;
03227   temp1.OCNIdleState = sConfig->OCNIdleState;
03228
03229     switch (OutputChannel)
03230   {
03231     case TIM_CHANNEL_1:
03232     {
03233         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03234
03235       TIM_OC1_SetConfig(htim->Instance, &temp1);
03236     }
03237     break;
03238     case TIM_CHANNEL_2:
03239     {
03240         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03241
03242       TIM_OC2_SetConfig(htim->Instance, &temp1);
03243     }
03244     break;
03245     default:
03246     break;
03247   }
03248     switch (InputChannel)
03249   {
03250     case TIM_CHANNEL_1:
03251     {
03252         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03253
03254       TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
03255                         sConfig->ICSelection, sConfig->ICFilter);
03256
03257     /* Reset the IC1PSC Bits */
03258     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03259
03260     /* Select the Trigger source */
03261         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03262     htim->Instance->SMCR |= TIM_TS_TI1FP1;
03263
03264     /* Select the Slave Mode */
03265         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03266     htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03267     }
03268     break;
03269     case TIM_CHANNEL_2:
03270     {
03271         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03272
03273       TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
03274                  sConfig->ICSelection, sConfig->ICFilter);
03275
03276       /* Reset the IC2PSC Bits */
03277         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03278
03279       /* Select the Trigger source */
03280         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03281       htim->Instance->SMCR |= TIM_TS_TI2FP2;
03282
03283       /* Select the Slave Mode */
03284         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03285       htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03286     }
03287     break;
03288
03289     default:
03290     break;
03291   }
03292
03293   htim->State = HAL_TIM_STATE_READY;
03294
03295   __HAL_UNLOCK(htim);
03296
03297   return HAL_OK;
03298 }
03299   else
03300   {
03301     return HAL_ERROR;
03302   }
03303 }
03304
03305 /**
03306   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
03307   * @param  htim TIM handle
03308   * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
03309   *         This parameter can be one of the following values:
03310   *            @arg TIM_DMABASE_CR1
03311   *            @arg TIM_DMABASE_CR2
03312   *            @arg TIM_DMABASE_SMCR
03313   *            @arg TIM_DMABASE_DIER
03314   *            @arg TIM_DMABASE_SR
03315   *            @arg TIM_DMABASE_EGR
03316   *            @arg TIM_DMABASE_CCMR1
03317   *            @arg TIM_DMABASE_CCMR2
03318   *            @arg TIM_DMABASE_CCER
03319   *            @arg TIM_DMABASE_CNT
03320   *            @arg TIM_DMABASE_PSC
03321   *            @arg TIM_DMABASE_ARR
03322   *            @arg TIM_DMABASE_RCR
03323   *            @arg TIM_DMABASE_CCR1
03324   *            @arg TIM_DMABASE_CCR2
03325   *            @arg TIM_DMABASE_CCR3
03326   *            @arg TIM_DMABASE_CCR4
03327   *            @arg TIM_DMABASE_BDTR
03328   *            @arg TIM_DMABASE_DCR
03329   * @param  BurstRequestSrc TIM DMA Request sources
03330   *         This parameter can be one of the following values:
03331   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03332   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03333   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03334   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03335   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03336   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03337   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03338   * @param  BurstBuffer The Buffer address.
03339   * @param  BurstLength DMA Burst length. This parameter can be one value
03340   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
03341   * @retval HAL status
03342   */
03343 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
03344                                               uint32_t  *BurstBuffer, uint32_t  BurstLength)
03345 {
03346 return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
03347 }
03348
03349 /**
03350   * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
03351   * @param  htim TIM handle
03352   * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
03353   *         This parameter can be one of the following values:
03354   *            @arg TIM_DMABASE_CR1
03355   *            @arg TIM_DMABASE_CR2
03356   *            @arg TIM_DMABASE_SMCR
03357   *            @arg TIM_DMABASE_DIER
03358   *            @arg TIM_DMABASE_SR
03359   *            @arg TIM_DMABASE_EGR
03360   *            @arg TIM_DMABASE_CCMR1
03361   *            @arg TIM_DMABASE_CCMR2
03362   *            @arg TIM_DMABASE_CCER
03363   *            @arg TIM_DMABASE_CNT
03364   *            @arg TIM_DMABASE_PSC
03365   *            @arg TIM_DMABASE_ARR
03366   *            @arg TIM_DMABASE_RCR
03367   *            @arg TIM_DMABASE_CCR1
03368   *            @arg TIM_DMABASE_CCR2
03369   *            @arg TIM_DMABASE_CCR3
03370   *            @arg TIM_DMABASE_CCR4
03371   *            @arg TIM_DMABASE_BDTR
03372   *            @arg TIM_DMABASE_DCR
03373   * @param  BurstRequestSrc TIM DMA Request sources
03374   *         This parameter can be one of the following values:
03375   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03376   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03377   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03378   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03379   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03380   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03381   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03382   * @param  BurstBuffer The Buffer address.
03383   * @param  BurstLength DMA Burst length. This parameter can be one value
03384   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
03385   * @param  DataLength Data length. This parameter can be one value
03386   *         between 1 and 0xFFFF.
03387   * @retval HAL status
03388   */
03389 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
03390                                                    uint32_t* BurstBuffer, uint32_t  BurstLength,  uint32_t  DataLength)
03391 {
03392   /* Check the parameters */
03393   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
03394   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
03395   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03396   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
03397   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
03398
03399   if((htim->State == HAL_TIM_STATE_BUSY))
03400   {
03401      return HAL_BUSY;
03402   }
03403   else if((htim->State == HAL_TIM_STATE_READY))
03404   {
03405     if((BurstBuffer == 0U ) && (BurstLength > 0U))
03406     {
03407       return HAL_ERROR;
03408     }
03409     else
03410     {
03411       htim->State = HAL_TIM_STATE_BUSY;
03412     }
03413   }
03414   switch(BurstRequestSrc)
03415   {
03416     case TIM_DMA_UPDATE:
03417     {
03418       /* Set the DMA Period elapsed callback */
03419       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
03420
03421       /* Set the DMA error callback */
03422       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
03423
03424       /* Enable the DMA channel */
03425       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
03426     }
03427     break;
03428     case TIM_DMA_CC1:
03429     {
03430       /* Set the DMA Period elapsed callback */
03431       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  TIM_DMADelayPulseCplt;
03432
03433       /* Set the DMA error callback */
03434       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03435
03436       /* Enable the DMA channel */
03437       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
03438     }
03439     break;
03440     case TIM_DMA_CC2:
03441     {
03442       /* Set the DMA Period elapsed callback */
03443       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  TIM_DMADelayPulseCplt;
03444
03445       /* Set the DMA error callback */
03446       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
03447
03448       /* Enable the DMA channel */
03449       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
03450     }
03451     break;
03452     case TIM_DMA_CC3:
03453     {
03454       /* Set the DMA Period elapsed callback */
03455       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  TIM_DMADelayPulseCplt;
03456
03457       /* Set the DMA error callback */
03458       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
03459
03460       /* Enable the DMA channel */
03461       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
03462     }
03463     break;
03464     case TIM_DMA_CC4:
03465     {
03466       /* Set the DMA Period elapsed callback */
03467       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  TIM_DMADelayPulseCplt;
03468
03469       /* Set the DMA error callback */
03470       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
03471
03472       /* Enable the DMA channel */
03473       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
03474     }
03475     break;
03476     case TIM_DMA_COM:
03477     {
03478       /* Set the DMA Period elapsed callback */
03479       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
03480
03481       /* Set the DMA error callback */
03482       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
03483
03484       /* Enable the DMA channel */
03485       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
03486     }
03487     break;
03488     case TIM_DMA_TRIGGER:
03489     {
03490       /* Set the DMA Period elapsed callback */
03491       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
03492
03493       /* Set the DMA error callback */
03494       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
03495
03496       /* Enable the DMA channel */
03497       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
03498     }
03499     break;
03500     default:
03501     break;
03502   }
03503    /* configure the DMA Burst Mode */
03504    htim->Instance->DCR = BurstBaseAddress | BurstLength;
03505
03506    /* Enable the TIM DMA Request */
03507    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
03508
03509    htim->State = HAL_TIM_STATE_READY;
03510
03511   /* Return function status */
03512   return HAL_OK;
03513 }
03514
03515 /**
03516   * @brief  Stops the TIM DMA Burst mode
03517   * @param  htim TIM handle
03518   * @param  BurstRequestSrc TIM DMA Request sources to disable
03519   * @retval HAL status
03520   */
03521 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
03522 {
03523   /* Check the parameters */
03524   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03525
03526   /* Abort the DMA transfer (at least disable the DMA channel) */
03527   switch(BurstRequestSrc)
03528   {
03529     case TIM_DMA_UPDATE:
03530     {
03531       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
03532     }
03533     break;
03534     case TIM_DMA_CC1:
03535     {
03536       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
03537     }
03538     break;
03539     case TIM_DMA_CC2:
03540     {
03541       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
03542     }
03543     break;
03544     case TIM_DMA_CC3:
03545     {
03546       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
03547     }
03548     break;
03549     case TIM_DMA_CC4:
03550     {
03551       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
03552     }
03553     break;
03554     case TIM_DMA_COM:
03555     {
03556       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
03557     }
03558     break;
03559     case TIM_DMA_TRIGGER:
03560     {
03561       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
03562     }
03563     break;
03564     default:
03565     break;
03566   }
03567
03568   /* Disable the TIM Update DMA request */
03569   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
03570
03571   /* Return function status */
03572   return HAL_OK;
03573 }
03574
03575 /**
03576   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
03577   * @param  htim TIM handle
03578   * @param  BurstBaseAddress TIM Base address from where the DMA will starts the Data read
03579   *         This parameter can be one of the following values:
03580   *            @arg TIM_DMABASE_CR1
03581   *            @arg TIM_DMABASE_CR2
03582   *            @arg TIM_DMABASE_SMCR
03583   *            @arg TIM_DMABASE_DIER
03584   *            @arg TIM_DMABASE_SR
03585   *            @arg TIM_DMABASE_EGR
03586   *            @arg TIM_DMABASE_CCMR1
03587   *            @arg TIM_DMABASE_CCMR2
03588   *            @arg TIM_DMABASE_CCER
03589   *            @arg TIM_DMABASE_CNT
03590   *            @arg TIM_DMABASE_PSC
03591   *            @arg TIM_DMABASE_ARR
03592   *            @arg TIM_DMABASE_RCR
03593   *            @arg TIM_DMABASE_CCR1
03594   *            @arg TIM_DMABASE_CCR2
03595   *            @arg TIM_DMABASE_CCR3
03596   *            @arg TIM_DMABASE_CCR4
03597   *            @arg TIM_DMABASE_BDTR
03598   *            @arg TIM_DMABASE_DCR
03599   * @param  BurstRequestSrc TIM DMA Request sources
03600   *         This parameter can be one of the following values:
03601   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03602   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03603   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03604   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03605   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03606   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03607   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03608   * @param  BurstBuffer The Buffer address.
03609   * @param  BurstLength DMA Burst length. This parameter can be one value
03610   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
03611   * @retval HAL status
03612   */
03613 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
03614                                              uint32_t  *BurstBuffer, uint32_t  BurstLength)
03615 {
03616 return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
03617 }
03618
03619 /**
03620   * @brief  Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory
03621   * @param  htim TIM handle
03622   * @param  BurstBaseAddress TIM Base address from where the DMA will starts the Data read
03623   *         This parameter can be one of the following values:
03624   *            @arg TIM_DMABASE_CR1
03625   *            @arg TIM_DMABASE_CR2
03626   *            @arg TIM_DMABASE_SMCR
03627   *            @arg TIM_DMABASE_DIER
03628   *            @arg TIM_DMABASE_SR
03629   *            @arg TIM_DMABASE_EGR
03630   *            @arg TIM_DMABASE_CCMR1
03631   *            @arg TIM_DMABASE_CCMR2
03632   *            @arg TIM_DMABASE_CCER
03633   *            @arg TIM_DMABASE_CNT
03634   *            @arg TIM_DMABASE_PSC
03635   *            @arg TIM_DMABASE_ARR
03636   *            @arg TIM_DMABASE_RCR
03637   *            @arg TIM_DMABASE_CCR1
03638   *            @arg TIM_DMABASE_CCR2
03639   *            @arg TIM_DMABASE_CCR3
03640   *            @arg TIM_DMABASE_CCR4
03641   *            @arg TIM_DMABASE_BDTR
03642   *            @arg TIM_DMABASE_DCR
03643   * @param  BurstRequestSrc TIM DMA Request sources
03644   *         This parameter can be one of the following values:
03645   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03646   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03647   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03648   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03649   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03650   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03651   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03652   * @param  BurstBuffer The Buffer address.
03653   * @param  BurstLength DMA Burst length. This parameter can be one value
03654   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
03655   * @param  DataLength Data length. This parameter can be one value
03656   *         between 1 and 0xFFFF.
03657   * @retval HAL status
03658   */
03659 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
03660                                                   uint32_t  *BurstBuffer, uint32_t  BurstLength, uint32_t  DataLength)
03661 {
03662   /* Check the parameters */
03663   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
03664   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
03665   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03666   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
03667   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
03668
03669   if((htim->State == HAL_TIM_STATE_BUSY))
03670   {
03671      return HAL_BUSY;
03672   }
03673   else if((htim->State == HAL_TIM_STATE_READY))
03674   {
03675     if((BurstBuffer == 0U ) && (BurstLength > 0U))
03676     {
03677       return HAL_ERROR;
03678     }
03679     else
03680     {
03681       htim->State = HAL_TIM_STATE_BUSY;
03682     }
03683   }
03684   switch(BurstRequestSrc)
03685   {
03686     case TIM_DMA_UPDATE:
03687     {
03688       /* Set the DMA Period elapsed callback */
03689       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
03690
03691       /* Set the DMA error callback */
03692       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
03693
03694       /* Enable the DMA channel */
03695        HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
03696     }
03697     break;
03698     case TIM_DMA_CC1:
03699     {
03700       /* Set the DMA Period elapsed callback */
03701       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  TIM_DMACaptureCplt;
03702
03703       /* Set the DMA error callback */
03704       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03705
03706       /* Enable the DMA channel */
03707       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
03708     }
03709     break;
03710     case TIM_DMA_CC2:
03711     {
03712       /* Set the DMA Period elapsed callback */
03713       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  TIM_DMACaptureCplt;
03714
03715       /* Set the DMA error callback */
03716       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
03717
03718       /* Enable the DMA channel */
03719       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
03720     }
03721     break;
03722     case TIM_DMA_CC3:
03723     {
03724       /* Set the DMA Period elapsed callback */
03725       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  TIM_DMACaptureCplt;
03726
03727       /* Set the DMA error callback */
03728       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
03729
03730       /* Enable the DMA channel */
03731       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
03732     }
03733     break;
03734     case TIM_DMA_CC4:
03735     {
03736       /* Set the DMA Period elapsed callback */
03737       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  TIM_DMACaptureCplt;
03738
03739       /* Set the DMA error callback */
03740       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
03741
03742       /* Enable the DMA channel */
03743       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
03744     }
03745     break;
03746     case TIM_DMA_COM:
03747     {
03748       /* Set the DMA Period elapsed callback */
03749       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
03750
03751       /* Set the DMA error callback */
03752       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
03753
03754       /* Enable the DMA channel */
03755       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
03756     }
03757     break;
03758     case TIM_DMA_TRIGGER:
03759     {
03760       /* Set the DMA Period elapsed callback */
03761       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
03762
03763       /* Set the DMA error callback */
03764       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
03765
03766       /* Enable the DMA channel */
03767       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
03768     }
03769     break;
03770     default:
03771     break;
03772   }
03773
03774   /* configure the DMA Burst Mode */
03775   htim->Instance->DCR = BurstBaseAddress | BurstLength;
03776
03777   /* Enable the TIM DMA Request */
03778   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
03779
03780   htim->State = HAL_TIM_STATE_READY;
03781
03782   /* Return function status */
03783   return HAL_OK;
03784 }
03785
03786 /**
03787   * @brief  Stop the DMA burst reading
03788   * @param  htim TIM handle
03789   * @param  BurstRequestSrc TIM DMA Request sources to disable.
03790   * @retval HAL status
03791   */
03792 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
03793 {
03794   /* Check the parameters */
03795   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03796
03797   /* Abort the DMA transfer (at least disable the DMA channel) */
03798   switch(BurstRequestSrc)
03799   {
03800     case TIM_DMA_UPDATE:
03801     {
03802       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
03803     }
03804     break;
03805     case TIM_DMA_CC1:
03806     {
03807       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
03808     }
03809     break;
03810     case TIM_DMA_CC2:
03811     {
03812       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
03813     }
03814     break;
03815     case TIM_DMA_CC3:
03816     {
03817       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
03818     }
03819     break;
03820     case TIM_DMA_CC4:
03821     {
03822       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
03823     }
03824     break;
03825     case TIM_DMA_COM:
03826     {
03827       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
03828     }
03829     break;
03830     case TIM_DMA_TRIGGER:
03831     {
03832       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
03833     }
03834     break;
03835     default:
03836     break;
03837   }
03838
03839   /* Disable the TIM Update DMA request */
03840   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
03841
03842   /* Return function status */
03843   return HAL_OK;
03844 }
03845
03846 /**
03847   * @brief  Generate a software event
03848   * @param  htim TIM handle
03849   * @param  EventSource specifies the event source.
03850   *          This parameter can be one of the following values:
03851   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
03852   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
03853   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
03854   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
03855   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
03856   *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
03857   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
03858   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
03859   *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
03860   * @retval HAL status
03861   * @note TIM_EVENTSOURCE_BREAK2 isn't relevant for STM32F37xx and STM32F38xx
03862   *       devices
03863   */
03864
03865 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
03866 {
03867   /* Check the parameters */
03868   assert_param(IS_TIM_INSTANCE(htim->Instance));
03869   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
03870
03871   /* Process Locked */
03872   __HAL_LOCK(htim);
03873
03874   /* Change the TIM state */
03875   htim->State = HAL_TIM_STATE_BUSY;
03876
03877   /* Set the event sources */
03878   htim->Instance->EGR = EventSource;
03879
03880   /* Change the TIM state */
03881   htim->State = HAL_TIM_STATE_READY;
03882
03883   __HAL_UNLOCK(htim);
03884
03885   /* Return function status */
03886   return HAL_OK;
03887 }
03888
03889 /**
03890   * @brief  Configures the OCRef clear feature
03891   * @param  htim TIM handle
03892   * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
03893   *         contains the OCREF clear feature and parameters for the TIM peripheral.
03894   * @param  Channel specifies the TIM Channel
03895   *          This parameter can be one of the following values:
03896   *            @arg TIM_CHANNEL_1: TIM Channel 1
03897   *            @arg TIM_CHANNEL_2: TIM Channel 2
03898   *            @arg TIM_CHANNEL_3: TIM Channel 3
03899   *            @arg TIM_CHANNEL_4: TIM Channel 4
03900   * @retval HAL status
03901   */
03902 __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
03903 {
03904   /* Check the parameters */
03905   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03906   assert_param(IS_TIM_CHANNELS(Channel));
03907   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
03908
03909   /* Process Locked */
03910   __HAL_LOCK(htim);
03911
03912   htim->State = HAL_TIM_STATE_BUSY;
03913
03914   if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
03915   {
03916     /* Check the parameters */
03917     assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
03918     assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
03919     assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
03920
03921     TIM_ETR_SetConfig(htim->Instance,
03922                       sClearInputConfig->ClearInputPrescaler,
03923                       sClearInputConfig->ClearInputPolarity,
03924                       sClearInputConfig->ClearInputFilter);
03925   }
03926
03927   switch (Channel)
03928   {
03929     case TIM_CHANNEL_1:
03930     {
03931       if(sClearInputConfig->ClearInputState != RESET)
03932       {
03933       /* Enable the Ocref clear feature for Channel 1U */
03934       htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
03935       }
03936       else
03937       {
03938         /* Disable the Ocref clear feature for Channel 1U */
03939         htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
03940       }
03941     }
03942     break;
03943     case TIM_CHANNEL_2:
03944     {
03945       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03946       if(sClearInputConfig->ClearInputState != RESET)
03947       {
03948       /* Enable the Ocref clear feature for Channel 2U */
03949       htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
03950       }
03951       else
03952       {
03953         /* Disable the Ocref clear feature for Channel 2U */
03954         htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
03955       }
03956     }
03957     break;
03958     case TIM_CHANNEL_3:
03959     {
03960       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03961       if(sClearInputConfig->ClearInputState != RESET)
03962       {
03963       /* Enable the Ocref clear feature for Channel 3U */
03964       htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
03965       }
03966       else
03967       {
03968         /* Disable the Ocref clear feature for Channel 3U */
03969         htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
03970       }
03971     }
03972     break;
03973     case TIM_CHANNEL_4:
03974     {
03975       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03976       if(sClearInputConfig->ClearInputState != RESET)
03977       {
03978       /* Enable the Ocref clear feature for Channel 4U */
03979       htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
03980       }
03981       else
03982       {
03983         /* Disable the Ocref clear feature for Channel 4U */
03984         htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
03985       }
03986     }
03987     break;
03988     default:
03989     break;
03990   }
03991
03992   htim->State = HAL_TIM_STATE_READY;
03993
03994   __HAL_UNLOCK(htim);
03995
03996   return HAL_OK;
03997 }
03998
03999 /**
04000   * @brief   Configures the clock source to be used
04001   * @param  htim TIM handle
04002   * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
04003   *         contains the clock source information for the TIM peripheral.
04004   * @retval HAL status
04005   */
04006 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
04007 {
04008   uint32_t tmpsmcr = 0U;
04009
04010   /* Process Locked */
04011   __HAL_LOCK(htim);
04012
04013   htim->State = HAL_TIM_STATE_BUSY;
04014
04015   /* Check the parameters */
04016   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
04017
04018   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
04019   tmpsmcr = htim->Instance->SMCR;
04020   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
04021   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
04022   htim->Instance->SMCR = tmpsmcr;
04023
04024   switch (sClockSourceConfig->ClockSource)
04025   {
04026   case TIM_CLOCKSOURCE_INTERNAL:
04027     {
04028       assert_param(IS_TIM_INSTANCE(htim->Instance));
04029       /* Disable slave mode to clock the prescaler directly with the internal clock */
04030       htim->Instance->SMCR &= ~TIM_SMCR_SMS;
04031     }
04032     break;
04033
04034   case TIM_CLOCKSOURCE_ETRMODE1:
04035     {
04036       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
04037       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
04038
04039       /* Check ETR input conditioning related parameters */
04040       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
04041       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04042       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04043
04044       /* Configure the ETR Clock source */
04045       TIM_ETR_SetConfig(htim->Instance,
04046                         sClockSourceConfig->ClockPrescaler,
04047                         sClockSourceConfig->ClockPolarity,
04048                         sClockSourceConfig->ClockFilter);
04049       /* Get the TIMx SMCR register value */
04050       tmpsmcr = htim->Instance->SMCR;
04051       /* Reset the SMS and TS Bits */
04052       tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
04053       /* Select the External clock mode1 and the ETRF trigger */
04054       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
04055       /* Write to TIMx SMCR */
04056       htim->Instance->SMCR = tmpsmcr;
04057     }
04058     break;
04059
04060   case TIM_CLOCKSOURCE_ETRMODE2:
04061     {
04062       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
04063       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
04064
04065       /* Check ETR input conditioning related parameters */
04066       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
04067       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04068       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04069
04070       /* Configure the ETR Clock source */
04071       TIM_ETR_SetConfig(htim->Instance,
04072                         sClockSourceConfig->ClockPrescaler,
04073                         sClockSourceConfig->ClockPolarity,
04074                         sClockSourceConfig->ClockFilter);
04075       /* Enable the External clock mode2 */
04076       htim->Instance->SMCR |= TIM_SMCR_ECE;
04077     }
04078     break;
04079
04080   case TIM_CLOCKSOURCE_TI1:
04081     {
04082       /* Check whether or not the timer instance supports external clock mode 1U */
04083       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04084
04085       /* Check TI1 input conditioning related parameters */
04086       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04087       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04088
04089       TIM_TI1_ConfigInputStage(htim->Instance,
04090                                sClockSourceConfig->ClockPolarity,
04091                                sClockSourceConfig->ClockFilter);
04092       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
04093     }
04094     break;
04095   case TIM_CLOCKSOURCE_TI2:
04096     {
04097       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
04098       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04099
04100        /* Check TI2 input conditioning related parameters */
04101       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04102       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04103
04104       TIM_TI2_ConfigInputStage(htim->Instance,
04105                                sClockSourceConfig->ClockPolarity,
04106                                sClockSourceConfig->ClockFilter);
04107       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
04108     }
04109     break;
04110   case TIM_CLOCKSOURCE_TI1ED:
04111     {
04112       /* Check whether or not the timer instance supports external clock mode 1U */
04113       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04114
04115       /* Check TI1 input conditioning related parameters */
04116       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04117       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04118
04119       TIM_TI1_ConfigInputStage(htim->Instance,
04120                                sClockSourceConfig->ClockPolarity,
04121                                sClockSourceConfig->ClockFilter);
04122       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
04123     }
04124     break;
04125   case TIM_CLOCKSOURCE_ITR0:
04126     {
04127       /* Check whether or not the timer instance supports external clock mode 1U */
04128       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04129
04130       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
04131     }
04132     break;
04133   case TIM_CLOCKSOURCE_ITR1:
04134     {
04135       /* Check whether or not the timer instance supports external clock mode 1U */
04136       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04137
04138       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
04139     }
04140     break;
04141   case TIM_CLOCKSOURCE_ITR2:
04142     {
04143       /* Check whether or not the timer instance supports external clock mode 1U */
04144       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04145
04146       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
04147     }
04148     break;
04149   case TIM_CLOCKSOURCE_ITR3:
04150     {
04151       /* Check whether or not the timer instance supports external clock mode 1U */
04152       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04153
04154       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
04155     }
04156     break;
04157
04158   default:
04159     break;
04160   }
04161   htim->State = HAL_TIM_STATE_READY;
04162
04163   __HAL_UNLOCK(htim);
04164
04165   return HAL_OK;
04166 }
04167
04168 /**
04169   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
04170   *         or a XOR combination between CH1_input, CH2_input & CH3_input
04171   * @param  htim TIM handle.
04172   * @param  TI1_Selection: Indicate whether or not channel 1 is connected to the
04173   *         output of a XOR gate.
04174   *          This parameter can be one of the following values:
04175   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
04176   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
04177   *            pins are connected to the TI1 input (XOR combination)
04178   * @retval HAL status
04179   */
04180 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
04181 {
04182   uint32_t tmpcr2 = 0U;
04183
04184   /* Check the parameters */
04185   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
04186   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
04187
04188   /* Get the TIMx CR2 register value */
04189   tmpcr2 = htim->Instance->CR2;
04190
04191   /* Reset the TI1 selection */
04192   tmpcr2 &= ~TIM_CR2_TI1S;
04193
04194   /* Set the the TI1 selection */
04195   tmpcr2 |= TI1_Selection;
04196
04197   /* Write to TIMxCR2 */
04198   htim->Instance->CR2 = tmpcr2;
04199
04200   return HAL_OK;
04201 }
04202
04203 /**
04204   * @brief  Configures the TIM in Slave mode
04205   * @param  htim TIM handle.
04206   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
04207   *         contains the selected trigger (internal trigger input, filtered
04208   *         timer input or external trigger input) and the ) and the Slave
04209   *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
04210   * @retval HAL status
04211   */
04212 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
04213 {
04214   /* Check the parameters */
04215   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04216   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04217   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04218
04219   __HAL_LOCK(htim);
04220
04221   htim->State = HAL_TIM_STATE_BUSY;
04222
04223   TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
04224
04225   /* Disable Trigger Interrupt */
04226   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
04227
04228   /* Disable Trigger DMA request */
04229   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
04230
04231   htim->State = HAL_TIM_STATE_READY;
04232
04233   __HAL_UNLOCK(htim);
04234
04235   return HAL_OK;
04236 }
04237
04238 /**
04239   * @brief  Configures the TIM in Slave mode in interrupt mode
04240   * @param  htim TIM handle.
04241   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
04242   *         contains the selected trigger (internal trigger input, filtered
04243   *         timer input or external trigger input) and the ) and the Slave
04244   *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
04245   * @retval HAL status
04246   */
04247 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
04248                                                         TIM_SlaveConfigTypeDef * sSlaveConfig)
04249 {
04250   /* Check the parameters */
04251   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04252   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04253   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04254
04255   __HAL_LOCK(htim);
04256
04257   htim->State = HAL_TIM_STATE_BUSY;
04258
04259   TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
04260
04261   /* Enable Trigger Interrupt */
04262   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
04263
04264   /* Disable Trigger DMA request */
04265   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
04266
04267   htim->State = HAL_TIM_STATE_READY;
04268
04269   __HAL_UNLOCK(htim);
04270
04271   return HAL_OK;
04272 }
04273
04274 /**
04275   * @brief  Read the captured value from Capture Compare unit
04276   * @param  htim TIM handle.
04277   * @param  Channel TIM Channels to be enabled
04278   *          This parameter can be one of the following values:
04279   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
04280   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
04281   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
04282   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
04283   * @retval Captured value
04284   */
04285 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
04286 {
04287   uint32_t tmpreg = 0U;
04288
04289   __HAL_LOCK(htim);
04290
04291   switch (Channel)
04292   {
04293   case TIM_CHANNEL_1:
04294     {
04295       /* Check the parameters */
04296       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04297
04298       /* Return the capture 1 value */
04299       tmpreg =  htim->Instance->CCR1;
04300
04301       break;
04302     }
04303   case TIM_CHANNEL_2:
04304     {
04305       /* Check the parameters */
04306       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04307
04308       /* Return the capture 2 value */
04309       tmpreg =   htim->Instance->CCR2;
04310
04311       break;
04312     }
04313
04314   case TIM_CHANNEL_3:
04315     {
04316       /* Check the parameters */
04317       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
04318
04319       /* Return the capture 3 value */
04320       tmpreg =   htim->Instance->CCR3;
04321
04322       break;
04323     }
04324
04325   case TIM_CHANNEL_4:
04326     {
04327       /* Check the parameters */
04328       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
04329
04330       /* Return the capture 4 value */
04331       tmpreg =   htim->Instance->CCR4;
04332
04333       break;
04334     }
04335
04336   default:
04337     break;
04338   }
04339
04340   __HAL_UNLOCK(htim);
04341   return tmpreg;
04342 }
04343
04344 /**
04345   * @}
04346   */
04347
04348 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
04349  *  @brief    TIM Callbacks functions
04350  *
04351 @verbatim
04352   ==============================================================================
04353                         ##### TIM Callbacks functions #####
04354   ==============================================================================
04355  [..]
04356    This section provides TIM callback functions:
04357    (+) Timer Period elapsed callback
04358    (+) Timer Output Compare callback
04359    (+) Timer Input capture callback
04360    (+) Timer Trigger callback
04361    (+) Timer Error callback
04362
04363 @endverbatim
04364   * @{
04365   */
04366
04367 /**
04368   * @brief  Period elapsed callback in non blocking mode
04369   * @param  htim TIM handle
04370   * @retval None
04371   */
04372 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
04373 {
04374   /* Prevent unused argument(s) compilation warning */
04375   UNUSED(htim);
04376
04377   /* NOTE : This function Should not be modified, when the callback is needed,
04378             the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
04379    */
04380
04381 }
04382 /**
04383   * @brief  Output Compare callback in non blocking mode
04384   * @param  htim TIM OC handle
04385   * @retval None
04386   */
04387 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
04388 {
04389   /* Prevent unused argument(s) compilation warning */
04390   UNUSED(htim);
04391
04392   /* NOTE : This function Should not be modified, when the callback is needed,
04393             the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
04394    */
04395 }
04396 /**
04397   * @brief  Input Capture callback in non blocking mode
04398   * @param  htim TIM IC handle
04399   * @retval None
04400   */
04401 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
04402 {
04403   /* Prevent unused argument(s) compilation warning */
04404   UNUSED(htim);
04405
04406   /* NOTE : This function Should not be modified, when the callback is needed,
04407             the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
04408    */
04409 }
04410
04411 /**
04412   * @brief  PWM Pulse finished callback in non blocking mode
04413   * @param  htim TIM handle
04414   * @retval None
04415   */
04416 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
04417 {
04418   /* Prevent unused argument(s) compilation warning */
04419   UNUSED(htim);
04420
04421   /* NOTE : This function Should not be modified, when the callback is needed,
04422             the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
04423    */
04424 }
04425
04426 /**
04427   * @brief  Hall Trigger detection callback in non blocking mode
04428   * @param  htim TIM handle
04429   * @retval None
04430   */
04431 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
04432 {
04433   /* Prevent unused argument(s) compilation warning */
04434   UNUSED(htim);
04435
04436   /* NOTE : This function Should not be modified, when the callback is needed,
04437             the HAL_TIM_TriggerCallback could be implemented in the user file
04438    */
04439 }
04440
04441 /**
04442   * @brief  Timer error callback in non blocking mode
04443   * @param  htim TIM handle
04444   * @retval None
04445   */
04446 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
04447 {
04448   /* Prevent unused argument(s) compilation warning */
04449   UNUSED(htim);
04450
04451   /* NOTE : This function Should not be modified, when the callback is needed,
04452             the HAL_TIM_ErrorCallback could be implemented in the user file
04453    */
04454 }
04455
04456 /**
04457   * @}
04458   */
04459
04460 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
04461  *  @brief   Peripheral State functions
04462  *
04463 @verbatim
04464   ==============================================================================
04465                         ##### Peripheral State functions #####
04466   ==============================================================================
04467     [..]
04468     This subsection permit to get in run-time the status of the peripheral
04469     and the data flow.
04470
04471 @endverbatim
04472   * @{
04473   */
04474
04475 /**
04476   * @brief  Return the TIM Base state
04477   * @param  htim TIM Base handle
04478   * @retval HAL state
04479   */
04480 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
04481 {
04482   return htim->State;
04483 }
04484
04485 /**
04486   * @brief  Return the TIM OC state
04487   * @param  htim TIM Ouput Compare handle
04488   * @retval HAL state
04489   */
04490 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
04491 {
04492   return htim->State;
04493 }
04494
04495 /**
04496   * @brief  Return the TIM PWM state
04497   * @param  htim TIM handle
04498   * @retval HAL state
04499   */
04500 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
04501 {
04502   return htim->State;
04503 }
04504
04505 /**
04506   * @brief  Return the TIM Input Capture state
04507   * @param  htim TIM IC handle
04508   * @retval HAL state
04509   */
04510 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
04511 {
04512   return htim->State;
04513 }
04514
04515 /**
04516   * @brief  Return the TIM One Pulse Mode state
04517   * @param  htim TIM OPM handle
04518   * @retval HAL state
04519   */
04520 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
04521 {
04522   return htim->State;
04523 }
04524
04525 /**
04526   * @brief  Return the TIM Encoder Mode state
04527   * @param  htim TIM Encoder handle
04528   * @retval HAL state
04529   */
04530 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
04531 {
04532   return htim->State;
04533 }
04534
04535 /**
04536   * @}
04537   */
04538
04539 /**
04540   * @}
04541   */
04542
04543 /** @addtogroup TIM_Private_Functions TIM_Private_Functions
04544   * @{
04545   */
04546
04547 /**
04548   * @brief  TIM DMA error callback
04549   * @param  hdma pointer to DMA handle.
04550   * @retval None
04551   */
04552 void TIM_DMAError(DMA_HandleTypeDef *hdma)
04553 {
04554   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04555
04556   htim->State= HAL_TIM_STATE_READY;
04557
04558   HAL_TIM_ErrorCallback(htim);
04559 }
04560
04561 /**
04562   * @brief  TIM DMA Delay Pulse complete callback.
04563   * @param  hdma pointer to DMA handle.
04564   * @retval None
04565   */
04566 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
04567 {
04568   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04569
04570   htim->State= HAL_TIM_STATE_READY;
04571
04572   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
04573   {
04574     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
04575   }
04576   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
04577   {
04578     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
04579   }
04580   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
04581   {
04582     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
04583   }
04584   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
04585   {
04586     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
04587   }
04588
04589   HAL_TIM_PWM_PulseFinishedCallback(htim);
04590
04591   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
04592 }
04593 /**
04594   * @brief  TIM DMA Capture complete callback.
04595   * @param  hdma pointer to DMA handle.
04596   * @retval None
04597   */
04598 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
04599 {
04600   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04601
04602   htim->State= HAL_TIM_STATE_READY;
04603
04604   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
04605   {
04606     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
04607   }
04608   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
04609   {
04610     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
04611   }
04612   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
04613   {
04614     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
04615   }
04616   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
04617   {
04618     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
04619   }
04620
04621   HAL_TIM_IC_CaptureCallback(htim);
04622
04623   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
04624 }
04625
04626 /**
04627   * @brief  TIM DMA Period Elapse complete callback.
04628   * @param  hdma pointer to DMA handle.
04629   * @retval None
04630   */
04631 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
04632 {
04633   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04634
04635   htim->State= HAL_TIM_STATE_READY;
04636
04637   HAL_TIM_PeriodElapsedCallback(htim);
04638 }
04639
04640 /**
04641   * @brief  TIM DMA Trigger callback.
04642   * @param  hdma pointer to DMA handle.
04643   * @retval None
04644   */
04645 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
04646 {
04647   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04648
04649   htim->State= HAL_TIM_STATE_READY;
04650
04651   HAL_TIM_TriggerCallback(htim);
04652 }
04653
04654 /**
04655   * @brief  Time Base configuration
04656   * @param  TIMx TIM periheral
04657   * @param  Structure TIM Base configuration structure
04658   * @retval None
04659   */
04660 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
04661 {
04662   uint32_t tmpcr1 = 0U;
04663   tmpcr1 = TIMx->CR1;
04664
04665   /* Set TIM Time Base Unit parameters ---------------------------------------*/
04666   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
04667   {
04668     /* Select the Counter Mode */
04669     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
04670     tmpcr1 |= Structure->CounterMode;
04671   }
04672
04673   if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
04674   {
04675     /* Set the clock division */
04676     tmpcr1 &= ~TIM_CR1_CKD;
04677     tmpcr1 |= (uint32_t)Structure->ClockDivision;
04678   }
04679
04680   /* Set the auto-reload preload */
04681   MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
04682
04683   TIMx->CR1 = tmpcr1;
04684
04685   /* Set the Autoreload value */
04686   TIMx->ARR = (uint32_t)Structure->Period ;
04687
04688   /* Set the Prescaler value */
04689   TIMx->PSC = (uint32_t)Structure->Prescaler;
04690
04691   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
04692   {
04693     /* Set the Repetition Counter value */
04694     TIMx->RCR = Structure->RepetitionCounter;
04695   }
04696
04697   /* Generate an update event to reload the Prescaler
04698      and the repetition counter(only for TIM1 and TIM8) value immediatly */
04699   TIMx->EGR = TIM_EGR_UG;
04700 }
04701
04702 /**
04703   * @brief  Time Ouput Compare 1 configuration
04704   * @param  TIMx to select the TIM peripheral
04705   * @param  OC_Config The ouput configuration structure
04706   * @retval None
04707   */
04708 void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04709 {
04710   uint32_t tmpccmrx = 0U;
04711   uint32_t tmpccer = 0U;
04712   uint32_t tmpcr2 = 0U;
04713
04714    /* Disable the Channel 1: Reset the CC1E Bit */
04715   TIMx->CCER &= ~TIM_CCER_CC1E;
04716
04717   /* Get the TIMx CCER register value */
04718   tmpccer = TIMx->CCER;
04719   /* Get the TIMx CR2 register value */
04720   tmpcr2 =  TIMx->CR2;
04721
04722   /* Get the TIMx CCMR1 register value */
04723   tmpccmrx = TIMx->CCMR1;
04724
04725   /* Reset the Output Compare Mode Bits */
04726   tmpccmrx &= ~TIM_CCMR1_OC1M;
04727   tmpccmrx &= ~TIM_CCMR1_CC1S;
04728   /* Select the Output Compare Mode */
04729   tmpccmrx |= OC_Config->OCMode;
04730
04731   /* Reset the Output Polarity level */
04732   tmpccer &= ~TIM_CCER_CC1P;
04733   /* Set the Output Compare Polarity */
04734   tmpccer |= OC_Config->OCPolarity;
04735
04736   if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
04737   {
04738     /* Check parameters */
04739     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04740
04741     /* Reset the Output N Polarity level */
04742     tmpccer &= ~TIM_CCER_CC1NP;
04743     /* Set the Output N Polarity */
04744     tmpccer |= OC_Config->OCNPolarity;
04745     /* Reset the Output N State */
04746     tmpccer &= ~TIM_CCER_CC1NE;
04747   }
04748
04749   if(IS_TIM_BREAK_INSTANCE(TIMx))
04750   {
04751     /* Check parameters */
04752     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
04753     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04754
04755     /* Reset the Output Compare and Output Compare N IDLE State */
04756     tmpcr2 &= ~TIM_CR2_OIS1;
04757     tmpcr2 &= ~TIM_CR2_OIS1N;
04758     /* Set the Output Idle state */
04759     tmpcr2 |= OC_Config->OCIdleState;
04760     /* Set the Output N Idle state */
04761     tmpcr2 |= OC_Config->OCNIdleState;
04762   }
04763   /* Write to TIMx CR2 */
04764   TIMx->CR2 = tmpcr2;
04765
04766   /* Write to TIMx CCMR1 */
04767   TIMx->CCMR1 = tmpccmrx;
04768
04769   /* Set the Capture Compare Register value */
04770   TIMx->CCR1 = OC_Config->Pulse;
04771
04772   /* Write to TIMx CCER */
04773   TIMx->CCER = tmpccer;
04774 }
04775
04776 /**
04777   * @brief  Time Ouput Compare 2 configuration
04778   * @param  TIMx to select the TIM peripheral
04779   * @param  OC_Config The ouput configuration structure
04780   * @retval None
04781   */
04782 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04783 {
04784   uint32_t tmpccmrx = 0U;
04785   uint32_t tmpccer = 0U;
04786   uint32_t tmpcr2 = 0U;
04787
04788   /* Disable the Channel 2: Reset the CC2E Bit */
04789   TIMx->CCER &= ~TIM_CCER_CC2E;
04790
04791   /* Get the TIMx CCER register value */
04792   tmpccer = TIMx->CCER;
04793   /* Get the TIMx CR2 register value */
04794   tmpcr2 =  TIMx->CR2;
04795
04796   /* Get the TIMx CCMR1 register value */
04797   tmpccmrx = TIMx->CCMR1;
04798
04799   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04800   tmpccmrx &= ~TIM_CCMR1_OC2M;
04801   tmpccmrx &= ~TIM_CCMR1_CC2S;
04802
04803   /* Select the Output Compare Mode */
04804   tmpccmrx |= (OC_Config->OCMode << 8U);
04805
04806   /* Reset the Output Polarity level */
04807   tmpccer &= ~TIM_CCER_CC2P;
04808   /* Set the Output Compare Polarity */
04809   tmpccer |= (OC_Config->OCPolarity << 4U);
04810
04811   if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
04812   {
04813     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04814
04815     /* Reset the Output N Polarity level */
04816     tmpccer &= ~TIM_CCER_CC2NP;
04817     /* Set the Output N Polarity */
04818     tmpccer |= (OC_Config->OCNPolarity << 4U);
04819     /* Reset the Output N State */
04820     tmpccer &= ~TIM_CCER_CC2NE;
04821
04822   }
04823
04824   if(IS_TIM_BREAK_INSTANCE(TIMx))
04825   {
04826     /* Check parameters */
04827     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
04828     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04829
04830     /* Reset the Output Compare IDLE State */
04831     tmpcr2 &= ~TIM_CR2_OIS2;
04832 #if defined(STM32F373xC) || defined(STM32F378xx)
04833 #else
04834     /* Reset the Output Compare N IDLE State */
04835     tmpcr2 &= ~TIM_CR2_OIS2N;
04836 #endif
04837     /* Set the Output Idle state */
04838     tmpcr2 |= (OC_Config->OCIdleState << 2U);
04839     /* Set the Output N Idle state */
04840     tmpcr2 |= (OC_Config->OCNIdleState << 2U);
04841   }
04842
04843   /* Write to TIMx CR2 */
04844   TIMx->CR2 = tmpcr2;
04845
04846   /* Write to TIMx CCMR1 */
04847   TIMx->CCMR1 = tmpccmrx;
04848
04849   /* Set the Capture Compare Register value */
04850   TIMx->CCR2 = OC_Config->Pulse;
04851
04852   /* Write to TIMx CCER */
04853   TIMx->CCER = tmpccer;
04854 }
04855
04856 /**
04857   * @brief  Time Ouput Compare 3 configuration
04858   * @param  TIMx to select the TIM peripheral
04859   * @param  OC_Config The ouput configuration structure
04860   * @retval None
04861   */
04862 void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04863 {
04864   uint32_t tmpccmrx = 0U;
04865   uint32_t tmpccer = 0U;
04866   uint32_t tmpcr2 = 0U;
04867
04868   /* Disable the Channel 3: Reset the CC2E Bit */
04869   TIMx->CCER &= ~TIM_CCER_CC3E;
04870
04871   /* Get the TIMx CCER register value */
04872   tmpccer = TIMx->CCER;
04873   /* Get the TIMx CR2 register value */
04874   tmpcr2 =  TIMx->CR2;
04875
04876   /* Get the TIMx CCMR2 register value */
04877   tmpccmrx = TIMx->CCMR2;
04878
04879   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04880   tmpccmrx &= ~TIM_CCMR2_OC3M;
04881   tmpccmrx &= ~TIM_CCMR2_CC3S;
04882   /* Select the Output Compare Mode */
04883   tmpccmrx |= OC_Config->OCMode;
04884
04885   /* Reset the Output Polarity level */
04886   tmpccer &= ~TIM_CCER_CC3P;
04887   /* Set the Output Compare Polarity */
04888   tmpccer |= (OC_Config->OCPolarity << 8U);
04889
04890   if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
04891   {
04892     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04893
04894     /* Reset the Output N Polarity level */
04895     tmpccer &= ~TIM_CCER_CC3NP;
04896     /* Set the Output N Polarity */
04897     tmpccer |= (OC_Config->OCNPolarity << 8U);
04898     /* Reset the Output N State */
04899     tmpccer &= ~TIM_CCER_CC3NE;
04900   }
04901
04902   if(IS_TIM_BREAK_INSTANCE(TIMx))
04903   {
04904     /* Check parameters */
04905     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
04906     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04907
04908 #if defined(STM32F373xC) || defined(STM32F378xx)
04909 #else
04910     /* Reset the Output Compare and Output Compare N IDLE State */
04911     tmpcr2 &= ~TIM_CR2_OIS3;
04912     tmpcr2 &= ~TIM_CR2_OIS3N;
04913 #endif
04914     /* Set the Output Idle state */
04915     tmpcr2 |= (OC_Config->OCIdleState << 4U);
04916     /* Set the Output N Idle state */
04917     tmpcr2 |= (OC_Config->OCNIdleState << 4U);
04918   }
04919
04920   /* Write to TIMx CR2 */
04921   TIMx->CR2 = tmpcr2;
04922
04923   /* Write to TIMx CCMR2 */
04924   TIMx->CCMR2 = tmpccmrx;
04925
04926   /* Set the Capture Compare Register value */
04927   TIMx->CCR3 = OC_Config->Pulse;
04928
04929   /* Write to TIMx CCER */
04930   TIMx->CCER = tmpccer;
04931 }
04932
04933 /**
04934   * @brief  Time Ouput Compare 4 configuration
04935   * @param  TIMx to select the TIM peripheral
04936   * @param  OC_Config The ouput configuration structure
04937   * @retval None
04938   */
04939 void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04940 {
04941   uint32_t tmpccmrx = 0U;
04942   uint32_t tmpccer = 0U;
04943   uint32_t tmpcr2 = 0U;
04944
04945   /* Disable the Channel 4: Reset the CC4E Bit */
04946   TIMx->CCER &= ~TIM_CCER_CC4E;
04947
04948   /* Get the TIMx CCER register value */
04949   tmpccer = TIMx->CCER;
04950   /* Get the TIMx CR2 register value */
04951   tmpcr2 =  TIMx->CR2;
04952
04953   /* Get the TIMx CCMR2 register value */
04954   tmpccmrx = TIMx->CCMR2;
04955
04956   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04957   tmpccmrx &= ~TIM_CCMR2_OC4M;
04958   tmpccmrx &= ~TIM_CCMR2_CC4S;
04959
04960   /* Select the Output Compare Mode */
04961   tmpccmrx |= (OC_Config->OCMode << 8U);
04962
04963   /* Reset the Output Polarity level */
04964   tmpccer &= ~TIM_CCER_CC4P;
04965   /* Set the Output Compare Polarity */
04966   tmpccer |= (OC_Config->OCPolarity << 12U);
04967
04968   if(IS_TIM_BREAK_INSTANCE(TIMx))
04969   {
04970     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04971
04972 #if defined(STM32F373xC) || defined(STM32F378xx)
04973 #else
04974    /* Reset the Output Compare IDLE State */
04975     tmpcr2 &= ~TIM_CR2_OIS4;
04976 #endif
04977     /* Set the Output Idle state */
04978     tmpcr2 |= (OC_Config->OCIdleState << 6U);
04979   }
04980
04981   /* Write to TIMx CR2 */
04982   TIMx->CR2 = tmpcr2;
04983
04984   /* Write to TIMx CCMR2 */
04985   TIMx->CCMR2 = tmpccmrx;
04986
04987   /* Set the Capture Compare Register value */
04988   TIMx->CCR4 = OC_Config->Pulse;
04989
04990   /* Write to TIMx CCER */
04991   TIMx->CCER = tmpccer;
04992 }
04993
04994 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
04995                               TIM_SlaveConfigTypeDef * sSlaveConfig)
04996 {
04997   uint32_t tmpsmcr = 0U;
04998   uint32_t tmpccmr1 = 0U;
04999   uint32_t tmpccer = 0U;
05000
05001   /* Get the TIMx SMCR register value */
05002   tmpsmcr = htim->Instance->SMCR;
05003
05004   /* Reset the Trigger Selection Bits */
05005   tmpsmcr &= ~TIM_SMCR_TS;
05006   /* Set the Input Trigger source */
05007   tmpsmcr |= sSlaveConfig->InputTrigger;
05008
05009   /* Reset the slave mode Bits */
05010   tmpsmcr &= ~TIM_SMCR_SMS;
05011   /* Set the slave mode */
05012   tmpsmcr |= sSlaveConfig->SlaveMode;
05013
05014   /* Write to TIMx SMCR */
05015   htim->Instance->SMCR = tmpsmcr;
05016
05017   /* Configure the trigger prescaler, filter, and polarity */
05018   switch (sSlaveConfig->InputTrigger)
05019   {
05020   case TIM_TS_ETRF:
05021     {
05022       /* Check the parameters */
05023       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
05024       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
05025       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
05026       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05027       /* Configure the ETR Trigger source */
05028       TIM_ETR_SetConfig(htim->Instance,
05029                         sSlaveConfig->TriggerPrescaler,
05030                         sSlaveConfig->TriggerPolarity,
05031                         sSlaveConfig->TriggerFilter);
05032     }
05033     break;
05034
05035   case TIM_TS_TI1F_ED:
05036     {
05037       /* Check the parameters */
05038       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
05039       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05040
05041       /* Disable the Channel 1: Reset the CC1E Bit */
05042       tmpccer = htim->Instance->CCER;
05043       htim->Instance->CCER &= ~TIM_CCER_CC1E;
05044       tmpccmr1 = htim->Instance->CCMR1;
05045
05046       /* Set the filter */
05047       tmpccmr1 &= ~TIM_CCMR1_IC1F;
05048       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
05049
05050       /* Write to TIMx CCMR1 and CCER registers */
05051       htim->Instance->CCMR1 = tmpccmr1;
05052       htim->Instance->CCER = tmpccer;
05053
05054     }
05055     break;
05056
05057   case TIM_TS_TI1FP1:
05058     {
05059       /* Check the parameters */
05060       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
05061       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
05062       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05063
05064       /* Configure TI1 Filter and Polarity */
05065       TIM_TI1_ConfigInputStage(htim->Instance,
05066                                sSlaveConfig->TriggerPolarity,
05067                                sSlaveConfig->TriggerFilter);
05068     }
05069     break;
05070
05071   case TIM_TS_TI2FP2:
05072     {
05073       /* Check the parameters */
05074       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05075       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
05076       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05077
05078       /* Configure TI2 Filter and Polarity */
05079       TIM_TI2_ConfigInputStage(htim->Instance,
05080                                 sSlaveConfig->TriggerPolarity,
05081                                 sSlaveConfig->TriggerFilter);
05082     }
05083     break;
05084
05085   case TIM_TS_ITR0:
05086     {
05087       /* Check the parameter */
05088       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05089     }
05090     break;
05091
05092   case TIM_TS_ITR1:
05093     {
05094       /* Check the parameter */
05095       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05096     }
05097     break;
05098
05099   case TIM_TS_ITR2:
05100     {
05101       /* Check the parameter */
05102       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05103     }
05104     break;
05105
05106   case TIM_TS_ITR3:
05107     {
05108       /* Check the parameter */
05109       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05110     }
05111     break;
05112
05113   default:
05114     break;
05115   }
05116 }
05117
05118 /**
05119   * @brief  Configure the TI1 as Input.
05120   * @param  TIMx to select the TIM peripheral.
05121   * @param  TIM_ICPolarity The Input Polarity.
05122   *          This parameter can be one of the following values:
05123   *            @arg TIM_ICPOLARITY_RISING
05124   *            @arg TIM_ICPOLARITY_FALLING
05125   *            @arg TIM_ICPOLARITY_BOTHEDGE
05126   * @param  TIM_ICSelection specifies the input to be used.
05127   *          This parameter can be one of the following values:
05128   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
05129   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
05130   *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
05131   * @param  TIM_ICFilter Specifies the Input Capture Filter.
05132   *          This parameter must be a value between 0x00 and 0x0F.
05133   * @retval None
05134   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
05135   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
05136   *        protected against un-initialized filter and polarity values.
05137   */
05138 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05139                        uint32_t TIM_ICFilter)
05140 {
05141   uint32_t tmpccmr1 = 0U;
05142   uint32_t tmpccer = 0U;
05143
05144   /* Disable the Channel 1: Reset the CC1E Bit */
05145   TIMx->CCER &= ~TIM_CCER_CC1E;
05146   tmpccmr1 = TIMx->CCMR1;
05147   tmpccer = TIMx->CCER;
05148
05149   /* Select the Input */
05150   if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
05151   {
05152     tmpccmr1 &= ~TIM_CCMR1_CC1S;
05153     tmpccmr1 |= TIM_ICSelection;
05154   }
05155   else
05156   {
05157     tmpccmr1 |= TIM_CCMR1_CC1S_0;
05158   }
05159
05160   /* Set the filter */
05161   tmpccmr1 &= ~TIM_CCMR1_IC1F;
05162   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
05163
05164   /* Select the Polarity and set the CC1E Bit */
05165   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
05166   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
05167
05168   /* Write to TIMx CCMR1 and CCER registers */
05169   TIMx->CCMR1 = tmpccmr1;
05170   TIMx->CCER = tmpccer;
05171 }
05172
05173 /**
05174   * @brief  Configure the Polarity and Filter for TI1.
05175   * @param  TIMx to select the TIM peripheral.
05176   * @param  TIM_ICPolarity The Input Polarity.
05177   *          This parameter can be one of the following values:
05178   *            @arg TIM_ICPOLARITY_RISING
05179   *            @arg TIM_ICPOLARITY_FALLING
05180   *            @arg TIM_ICPOLARITY_BOTHEDGE
05181   * @param  TIM_ICFilter Specifies the Input Capture Filter.
05182   *          This parameter must be a value between 0x00 and 0x0F.
05183   * @retval None
05184   */
05185 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
05186 {
05187   uint32_t tmpccmr1 = 0U;
05188   uint32_t tmpccer = 0U;
05189
05190   /* Disable the Channel 1: Reset the CC1E Bit */
05191   tmpccer = TIMx->CCER;
05192   TIMx->CCER &= ~TIM_CCER_CC1E;
05193   tmpccmr1 = TIMx->CCMR1;
05194
05195   /* Set the filter */
05196   tmpccmr1 &= ~TIM_CCMR1_IC1F;
05197   tmpccmr1 |= (TIM_ICFilter << 4U);
05198
05199   /* Select the Polarity and set the CC1E Bit */
05200   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
05201   tmpccer |= TIM_ICPolarity;
05202
05203   /* Write to TIMx CCMR1 and CCER registers */
05204   TIMx->CCMR1 = tmpccmr1;
05205   TIMx->CCER = tmpccer;
05206 }
05207
05208 /**
05209   * @brief  Configure the TI2 as Input.
05210   * @param  TIMx to select the TIM peripheral
05211   * @param  TIM_ICPolarity The Input Polarity.
05212   *          This parameter can be one of the following values:
05213   *            @arg TIM_ICPOLARITY_RISING
05214   *            @arg TIM_ICPOLARITY_FALLING
05215   *            @arg TIM_ICPOLARITY_BOTHEDGE
05216   * @param  TIM_ICSelection specifies the input to be used.
05217   *          This parameter can be one of the following values:
05218   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
05219   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
05220   *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
05221   * @param  TIM_ICFilter Specifies the Input Capture Filter.
05222   *          This parameter must be a value between 0x00 and 0x0F.
05223   * @retval None
05224   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
05225   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
05226   *        protected against un-initialized filter and polarity values.
05227   */
05228 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05229                        uint32_t TIM_ICFilter)
05230 {
05231   uint32_t tmpccmr1 = 0U;
05232   uint32_t tmpccer = 0U;
05233
05234   /* Disable the Channel 2: Reset the CC2E Bit */
05235   TIMx->CCER &= ~TIM_CCER_CC2E;
05236   tmpccmr1 = TIMx->CCMR1;
05237   tmpccer = TIMx->CCER;
05238
05239   /* Select the Input */
05240   tmpccmr1 &= ~TIM_CCMR1_CC2S;
05241   tmpccmr1 |= (TIM_ICSelection << 8U);
05242
05243   /* Set the filter */
05244   tmpccmr1 &= ~TIM_CCMR1_IC2F;
05245   tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
05246
05247   /* Select the Polarity and set the CC2E Bit */
05248   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
05249   tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
05250
05251   /* Write to TIMx CCMR1 and CCER registers */
05252   TIMx->CCMR1 = tmpccmr1 ;
05253   TIMx->CCER = tmpccer;
05254 }
05255
05256 /**
05257   * @brief  Configure the Polarity and Filter for TI2.
05258   * @param  TIMx to select the TIM peripheral.
05259   * @param  TIM_ICPolarity The Input Polarity.
05260   *          This parameter can be one of the following values:
05261   *            @arg TIM_ICPOLARITY_RISING
05262   *            @arg TIM_ICPOLARITY_FALLING
05263   *            @arg TIM_ICPOLARITY_BOTHEDGE
05264   * @param  TIM_ICFilter Specifies the Input Capture Filter.
05265   *          This parameter must be a value between 0x00 and 0x0F.
05266   * @retval None
05267   */
05268 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
05269 {
05270   uint32_t tmpccmr1 = 0U;
05271   uint32_t tmpccer = 0U;
05272
05273   /* Disable the Channel 2: Reset the CC2E Bit */
05274   TIMx->CCER &= ~TIM_CCER_CC2E;
05275   tmpccmr1 = TIMx->CCMR1;
05276   tmpccer = TIMx->CCER;
05277
05278   /* Set the filter */
05279   tmpccmr1 &= ~TIM_CCMR1_IC2F;
05280   tmpccmr1 |= (TIM_ICFilter << 12U);
05281
05282   /* Select the Polarity and set the CC2E Bit */
05283   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
05284   tmpccer |= (TIM_ICPolarity << 4U);
05285
05286   /* Write to TIMx CCMR1 and CCER registers */
05287   TIMx->CCMR1 = tmpccmr1 ;
05288   TIMx->CCER = tmpccer;
05289 }
05290
05291 /**
05292   * @brief  Configure the TI3 as Input.
05293   * @param  TIMx to select the TIM peripheral
05294   * @param  TIM_ICPolarity The Input Polarity.
05295   *          This parameter can be one of the following values:
05296   *            @arg TIM_ICPOLARITY_RISING
05297   *            @arg TIM_ICPOLARITY_FALLING
05298   *            @arg TIM_ICPOLARITY_BOTHEDGE
05299   * @param  TIM_ICSelection specifies the input to be used.
05300   *          This parameter can be one of the following values:
05301   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
05302   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
05303   *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
05304   * @param  TIM_ICFilter Specifies the Input Capture Filter.
05305   *          This parameter must be a value between 0x00 and 0x0F.
05306   * @retval None
05307   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
05308   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
05309   *        protected against un-initialized filter and polarity values.
05310   */
05311 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05312                        uint32_t TIM_ICFilter)
05313 {
05314   uint32_t tmpccmr2 = 0U;
05315   uint32_t tmpccer = 0U;
05316
05317   /* Disable the Channel 3: Reset the CC3E Bit */
05318   TIMx->CCER &= ~TIM_CCER_CC3E;
05319   tmpccmr2 = TIMx->CCMR2;
05320   tmpccer = TIMx->CCER;
05321
05322   /* Select the Input */
05323   tmpccmr2 &= ~TIM_CCMR2_CC3S;
05324   tmpccmr2 |= TIM_ICSelection;
05325
05326   /* Set the filter */
05327   tmpccmr2 &= ~TIM_CCMR2_IC3F;
05328   tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
05329
05330   /* Select the Polarity and set the CC3E Bit */
05331   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
05332   tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
05333
05334   /* Write to TIMx CCMR2 and CCER registers */
05335   TIMx->CCMR2 = tmpccmr2;
05336   TIMx->CCER = tmpccer;
05337 }
05338
05339 /**
05340   * @brief  Configure the TI4 as Input.
05341   * @param  TIMx to select the TIM peripheral
05342   * @param  TIM_ICPolarity The Input Polarity.
05343   *          This parameter can be one of the following values:
05344   *            @arg TIM_ICPOLARITY_RISING
05345   *            @arg TIM_ICPOLARITY_FALLING
05346   *            @arg TIM_ICPOLARITY_BOTHEDGE
05347   * @param  TIM_ICSelection specifies the input to be used.
05348   *          This parameter can be one of the following values:
05349   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
05350   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
05351   *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
05352   * @param  TIM_ICFilter Specifies the Input Capture Filter.
05353   *          This parameter must be a value between 0x00 and 0x0F.
05354   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
05355   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
05356   *        protected against un-initialized filter and polarity values.
05357   * @retval None
05358   */
05359 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05360                        uint32_t TIM_ICFilter)
05361 {
05362   uint32_t tmpccmr2 = 0U;
05363   uint32_t tmpccer = 0U;
05364
05365   /* Disable the Channel 4: Reset the CC4E Bit */
05366   TIMx->CCER &= ~TIM_CCER_CC4E;
05367   tmpccmr2 = TIMx->CCMR2;
05368   tmpccer = TIMx->CCER;
05369
05370   /* Select the Input */
05371   tmpccmr2 &= ~TIM_CCMR2_CC4S;
05372   tmpccmr2 |= (TIM_ICSelection << 8U);
05373
05374   /* Set the filter */
05375   tmpccmr2 &= ~TIM_CCMR2_IC4F;
05376   tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
05377
05378   /* Select the Polarity and set the CC4E Bit */
05379   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
05380   tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
05381
05382   /* Write to TIMx CCMR2 and CCER registers */
05383   TIMx->CCMR2 = tmpccmr2;
05384   TIMx->CCER = tmpccer ;
05385 }
05386
05387 /**
05388   * @brief  Selects the Input Trigger source
05389   * @param  TIMx to select the TIM peripheral
05390   * @param  InputTriggerSource The Input Trigger source.
05391   *          This parameter can be one of the following values:
05392   *            @arg TIM_TS_ITR0: Internal Trigger 0
05393   *            @arg TIM_TS_ITR1: Internal Trigger 1
05394   *            @arg TIM_TS_ITR2: Internal Trigger 2
05395   *            @arg TIM_TS_ITR3: Internal Trigger 3
05396   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
05397   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
05398   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
05399   *            @arg TIM_TS_ETRF: External Trigger input
05400   * @retval None
05401   */
05402 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
05403 {
05404   uint32_t tmpsmcr = 0U;
05405
05406    /* Get the TIMx SMCR register value */
05407    tmpsmcr = TIMx->SMCR;
05408    /* Reset the TS Bits */
05409    tmpsmcr &= ~TIM_SMCR_TS;
05410    /* Set the Input Trigger source and the slave mode*/
05411    tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
05412    /* Write to TIMx SMCR */
05413    TIMx->SMCR = tmpsmcr;
05414 }
05415 /**
05416   * @brief  Configures the TIMx External Trigger (ETR).
05417   * @param  TIMx to select the TIM peripheral
05418   * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
05419   *          This parameter can be one of the following values:
05420   *            @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
05421   *            @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
05422   *            @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
05423   *            @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
05424   * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
05425   *          This parameter can be one of the following values:
05426   *            @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
05427   *            @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
05428   * @param  ExtTRGFilter External Trigger Filter.
05429   *          This parameter must be a value between 0x00 and 0x0F
05430   * @retval None
05431   */
05432 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
05433                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
05434 {
05435   uint32_t tmpsmcr = 0U;
05436
05437   tmpsmcr = TIMx->SMCR;
05438
05439   /* Reset the ETR Bits */
05440   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
05441
05442   /* Set the Prescaler, the Filter value and the Polarity */
05443   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
05444
05445   /* Write to TIMx SMCR */
05446   TIMx->SMCR = tmpsmcr;
05447 }
05448
05449 /**
05450   * @brief  Enables or disables the TIM Capture Compare Channel x.
05451   * @param  TIMx to select the TIM peripheral
05452   * @param  Channel specifies the TIM Channel
05453   *          This parameter can be one of the following values:
05454   *            @arg TIM_CHANNEL_1: TIM Channel 1
05455   *            @arg TIM_CHANNEL_2: TIM Channel 2
05456   *            @arg TIM_CHANNEL_3: TIM Channel 3
05457   *            @arg TIM_CHANNEL_4: TIM Channel 4
05458   * @param  ChannelState specifies the TIM Channel CCxE bit new state.
05459   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
05460   * @retval None
05461   */
05462 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
05463 {
05464   uint32_t tmp = 0U;
05465
05466   /* Check the parameters */
05467   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
05468   assert_param(IS_TIM_CHANNELS(Channel));
05469
05470   tmp = TIM_CCER_CC1E << Channel;
05471
05472   /* Reset the CCxE Bit */
05473   TIMx->CCER &= ~tmp;
05474
05475   /* Set or reset the CCxE Bit */
05476   TIMx->CCER |=  (uint32_t)(ChannelState << Channel);
05477 }
05478
05479
05480 /**
05481   * @}
05482   */
05483
05484 #endif /* HAL_TIM_MODULE_ENABLED */
05485 /**
05486   * @}
05487   */
05488
05489 /**
05490   * @}
05491   */
05492 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_tim.h Source File

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stm32f3xx_hal_tim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_tim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TIM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_TIM_H
00038 #define __STM32F3xx_HAL_TIM_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup TIM
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /** @defgroup TIM_Exported_Types TIM Exported Types
00057   * @{
00058   */
00059 /**
00060   * @brief  TIM Time base Configuration Structure definition
00061   */
00062 typedef struct
00063 {
00064   uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00065                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
00066
00067   uint32_t CounterMode;       /*!< Specifies the counter mode.
00068                                    This parameter can be a value of @ref TIM_Counter_Mode */
00069
00070   uint32_t Period;            /*!< Specifies the period value to be loaded into the active
00071                                    Auto-Reload Register at the next update event.
00072                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
00073
00074   uint32_t ClockDivision;     /*!< Specifies the clock division.
00075                                    This parameter can be a value of @ref TIM_ClockDivision */
00076
00077   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00078                                     reaches zero, an update event is generated and counting restarts
00079                                     from the RCR value (N).
00080                                     This means in PWM mode that (N+1U) corresponds to:
00081                                         - the number of PWM periods in edge-aligned mode
00082                                         - the number of half PWM period in center-aligned mode
00083                                      GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00084                                      Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
00085
00086   uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
00087                                    This parameter can be a value of @ref TIM_AutoReloadPreload */
00088 } TIM_Base_InitTypeDef;
00089
00090 /**
00091   * @brief  TIM Output Compare Configuration Structure definition
00092   */
00093 typedef struct
00094 {
00095   uint32_t OCMode;        /*!< Specifies the TIM mode.
00096                                This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
00097
00098   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00099                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
00100
00101   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00102                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00103
00104   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00105                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00106                                @note This parameter is valid only for TIM1 and TIM8. */
00107
00108   uint32_t OCFastMode;   /*!< Specifies the Fast mode state.
00109                                This parameter can be a value of @ref TIM_Output_Fast_State
00110                                @note This parameter is valid only in PWM1 and PWM2 mode. */
00111
00112
00113   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00114                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00115                                @note This parameter is valid only for TIM1 and TIM8. */
00116
00117   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00118                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00119                                @note This parameter is valid only for TIM1 and TIM8. */
00120 } TIM_OC_InitTypeDef;
00121
00122 /**
00123   * @brief  TIM One Pulse Mode Configuration Structure definition
00124   */
00125 typedef struct
00126 {
00127   uint32_t OCMode;        /*!< Specifies the TIM mode.
00128                                This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
00129
00130   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00131                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
00132
00133   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00134                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00135
00136   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00137                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00138                                @note This parameter is valid only for TIM1 and TIM8. */
00139
00140   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00141                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00142                                @note This parameter is valid only for TIM1 and TIM8. */
00143
00144   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00145                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00146                                @note This parameter is valid only for TIM1 and TIM8. */
00147
00148   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00149                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00150
00151   uint32_t ICSelection;   /*!< Specifies the input.
00152                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00153
00154   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00155                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
00156 } TIM_OnePulse_InitTypeDef;
00157
00158
00159 /**
00160   * @brief  TIM Input Capture Configuration Structure definition
00161   */
00162 typedef struct
00163 {
00164   uint32_t  ICPolarity;   /*!< Specifies the active edge of the input signal.
00165                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00166
00167   uint32_t ICSelection;  /*!< Specifies the input.
00168                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00169
00170   uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
00171                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00172
00173   uint32_t ICFilter;     /*!< Specifies the input capture filter.
00174                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
00175 } TIM_IC_InitTypeDef;
00176
00177 /**
00178   * @brief  TIM Encoder Configuration Structure definition
00179   */
00180 typedef struct
00181 {
00182   uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
00183                                This parameter can be a value of @ref TIM_Encoder_Mode */
00184
00185   uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
00186                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00187
00188   uint32_t IC1Selection;  /*!< Specifies the input.
00189                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
00190
00191   uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
00192                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00193
00194   uint32_t IC1Filter;     /*!< Specifies the input capture filter.
00195                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
00196
00197   uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
00198                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00199
00200   uint32_t IC2Selection;  /*!< Specifies the input.
00201                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00202
00203   uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
00204                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00205
00206   uint32_t IC2Filter;     /*!< Specifies the input capture filter.
00207                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
00208 } TIM_Encoder_InitTypeDef;
00209
00210
00211 /**
00212   * @brief  TIM Clock Configuration Handle Structure definition
00213   */
00214 typedef struct
00215 {
00216   uint32_t ClockSource;     /*!< TIM clock sources
00217                                  This parameter can be a value of @ref TIM_Clock_Source */
00218   uint32_t ClockPolarity;   /*!< TIM clock polarity
00219                                  This parameter can be a value of @ref TIM_Clock_Polarity */
00220   uint32_t ClockPrescaler;  /*!< TIM clock prescaler
00221                                  This parameter can be a value of @ref TIM_Clock_Prescaler */
00222   uint32_t ClockFilter;    /*!< TIM clock filter
00223                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
00224 }TIM_ClockConfigTypeDef;
00225
00226 /**
00227   * @brief  TIM Clear Input Configuration Handle Structure definition
00228   */
00229 typedef struct
00230 {
00231   uint32_t ClearInputState;      /*!< TIM clear Input state
00232                                       This parameter can be ENABLE or DISABLE */
00233   uint32_t ClearInputSource;     /*!< TIM clear Input sources
00234                                       This parameter can be a value of @ref TIMEx_ClearInput_Source */
00235   uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
00236                                       This parameter can be a value of @ref TIM_ClearInput_Polarity */
00237   uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
00238                                       This parameter can be a value of @ref TIM_ClearInput_Prescaler */
00239   uint32_t ClearInputFilter;    /*!< TIM Clear Input filter
00240                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
00241 }TIM_ClearInputConfigTypeDef;
00242
00243 /**
00244   * @brief  TIM Slave configuration Structure definition
00245   */
00246 typedef struct {
00247   uint32_t  SlaveMode;      /*!< Slave mode selection
00248                                This parameter can be a value of @ref TIMEx_Slave_Mode */
00249   uint32_t  InputTrigger;      /*!< Input Trigger source
00250                                   This parameter can be a value of @ref TIM_Trigger_Selection */
00251   uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
00252                                   This parameter can be a value of @ref TIM_Trigger_Polarity */
00253   uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
00254                                   This parameter can be a value of @ref TIM_Trigger_Prescaler */
00255   uint32_t  TriggerFilter;     /*!< Input trigger filter
00256                                   This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
00257
00258 }TIM_SlaveConfigTypeDef;
00259
00260 /**
00261   * @brief  HAL State structures definition
00262   */
00263 typedef enum
00264 {
00265   HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
00266   HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
00267   HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
00268   HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
00269   HAL_TIM_STATE_ERROR             = 0x04     /*!< Reception process is ongoing                */
00270 }HAL_TIM_StateTypeDef;
00271
00272 /**
00273   * @brief  HAL Active channel structures definition
00274   */
00275 typedef enum
00276 {
00277   HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
00278   HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
00279   HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
00280   HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
00281   HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00    /*!< All active channels cleared */
00282 }HAL_TIM_ActiveChannel;
00283
00284 /**
00285   * @brief  TIM Time Base Handle Structure definition
00286   */
00287 typedef struct
00288 {
00289   TIM_TypeDef              *Instance;     /*!< Register base address             */
00290   TIM_Base_InitTypeDef     Init;          /*!< TIM Time Base required parameters */
00291   HAL_TIM_ActiveChannel    Channel;       /*!< Active channel                    */
00292   DMA_HandleTypeDef        *hdma[7];      /*!< DMA Handlers array
00293                                              This array is accessed by a @ref TIM_DMA_Handle_index */
00294   HAL_LockTypeDef          Lock;          /*!< Locking object                    */
00295   __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
00296 }TIM_HandleTypeDef;
00297
00298 /**
00299   * @}
00300   */
00301 /* End of exported types -----------------------------------------------------*/
00302
00303 /* Exported constants --------------------------------------------------------*/
00304 /** @defgroup TIM_Exported_Constants TIM Exported Constants
00305   * @{
00306   */
00307
00308 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
00309   * @{
00310   */
00311 #define  TIM_INPUTCHANNELPOLARITY_RISING      (0x00000000U)            /*!< Polarity for TIx source */
00312 #define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */
00313 #define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
00314 /**
00315   * @}
00316   */
00317
00318 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
00319   * @{
00320   */
00321 #define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */
00322 #define TIM_ETRPOLARITY_NONINVERTED           (0x0000U)                /*!< Polarity for ETR source */
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
00328   * @{
00329   */
00330 #define TIM_ETRPRESCALER_DIV1                 (0x0000U)                /*!< No prescaler is used */
00331 #define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2U */
00332 #define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4U */
00333 #define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8U */
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup TIM_Counter_Mode TIM Counter Mode
00339   * @{
00340   */
00341 #define TIM_COUNTERMODE_UP                 (0x0000U)
00342 #define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR
00343 #define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0
00344 #define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1
00345 #define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup TIM_ClockDivision TIM Clock Division
00351   * @{
00352   */
00353 #define TIM_CLOCKDIVISION_DIV1                       (0x0000U)
00354 #define TIM_CLOCKDIVISION_DIV2                       (TIM_CR1_CKD_0)
00355 #define TIM_CLOCKDIVISION_DIV4                       (TIM_CR1_CKD_1)
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
00361   * @{
00362   */
00363 #define TIM_AUTORELOAD_PRELOAD_DISABLE                (0x0000U)   /*!< TIMx_ARR register is not buffered */
00364 #define TIM_AUTORELOAD_PRELOAD_ENABLE                 (TIM_CR1_ARPE)       /*!< TIMx_ARR register is buffered */
00365
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
00371   * @{
00372   */
00373 #define TIM_OCFAST_DISABLE                (0x0000U)
00374 #define TIM_OCFAST_ENABLE                 (TIM_CCMR1_OC1FE)
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
00380   * @{
00381   */
00382 #define TIM_OCPOLARITY_HIGH                (0x0000U)
00383 #define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)
00384 /**
00385   * @}
00386   */
00387
00388 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
00389   * @{
00390   */
00391 #define TIM_OCNPOLARITY_HIGH               (0x0000U)
00392 #define TIM_OCNPOLARITY_LOW                (TIM_CCER_CC1NP)
00393 /**
00394   * @}
00395   */
00396
00397 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
00398   * @{
00399   */
00400 #define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)
00401 #define TIM_OCIDLESTATE_RESET              (0x0000U)
00402 /**
00403   * @}
00404   */
00405
00406 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
00407   * @{
00408   */
00409 #define TIM_OCNIDLESTATE_SET               (TIM_CR2_OIS1N)
00410 #define TIM_OCNIDLESTATE_RESET             (0x0000U)
00411 /**
00412   * @}
00413   */
00414
00415 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
00416   * @{
00417   */
00418 #define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING
00419 #define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING
00420 #define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE
00421 /**
00422   * @}
00423   */
00424
00425 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
00426   * @{
00427   */
00428 #define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1U, 2U, 3 or 4 is selected to be
00429                                                                                connected to IC1, IC2, IC3 or IC4, respectively */
00430 #define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1U, 2U, 3 or 4 is selected to be
00431                                                                                connected to IC2, IC1, IC4 or IC3, respectively */
00432 #define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1U, 2U, 3 or 4 is selected to be connected to TRC */
00433 /**
00434   * @}
00435   */
00436
00437 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
00438   * @{
00439   */
00440 #define TIM_ICPSC_DIV1                     (0x0000U)                 /*!< Capture performed each time an edge is detected on the capture input */
00441 #define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */
00442 #define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */
00443 #define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */
00444 /**
00445   * @}
00446   */
00447
00448 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
00449   * @{
00450   */
00451 #define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)
00452 #define TIM_OPMODE_REPETITIVE              (0x0000U)
00453 /**
00454   * @}
00455   */
00456
00457 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
00458   * @{
00459   */
00460 #define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)
00461 #define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)
00462 #define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
00463 /**
00464   * @}
00465   */
00466
00467 /** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
00468   * @{
00469   */
00470 #define TIM_IT_UPDATE           (TIM_DIER_UIE)
00471 #define TIM_IT_CC1              (TIM_DIER_CC1IE)
00472 #define TIM_IT_CC2              (TIM_DIER_CC2IE)
00473 #define TIM_IT_CC3              (TIM_DIER_CC3IE)
00474 #define TIM_IT_CC4              (TIM_DIER_CC4IE)
00475 #define TIM_IT_COM              (TIM_DIER_COMIE)
00476 #define TIM_IT_TRIGGER          (TIM_DIER_TIE)
00477 #define TIM_IT_BREAK            (TIM_DIER_BIE)
00478 /**
00479   * @}
00480   */
00481
00482 /** @defgroup TIM_Commutation_Source  TIM Commutation Source
00483   * @{
00484   */
00485 #define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)
00486 #define TIM_COMMUTATION_SOFTWARE          (0x0000U)
00487
00488 /**
00489   * @}
00490   */
00491
00492 /** @defgroup TIM_DMA_sources TIM DMA Sources
00493   * @{
00494   */
00495 #define TIM_DMA_UPDATE                     (TIM_DIER_UDE)
00496 #define TIM_DMA_CC1                        (TIM_DIER_CC1DE)
00497 #define TIM_DMA_CC2                        (TIM_DIER_CC2DE)
00498 #define TIM_DMA_CC3                        (TIM_DIER_CC3DE)
00499 #define TIM_DMA_CC4                        (TIM_DIER_CC4DE)
00500 #define TIM_DMA_COM                        (TIM_DIER_COMDE)
00501 #define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)
00502 /**
00503   * @}
00504   */
00505
00506 /** @defgroup TIM_Flag_definition TIM Flag Definition
00507   * @{
00508   */
00509 #define TIM_FLAG_UPDATE                    (TIM_SR_UIF)
00510 #define TIM_FLAG_CC1                       (TIM_SR_CC1IF)
00511 #define TIM_FLAG_CC2                       (TIM_SR_CC2IF)
00512 #define TIM_FLAG_CC3                       (TIM_SR_CC3IF)
00513 #define TIM_FLAG_CC4                       (TIM_SR_CC4IF)
00514 #define TIM_FLAG_COM                       (TIM_SR_COMIF)
00515 #define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)
00516 #define TIM_FLAG_BREAK                     (TIM_SR_BIF)
00517 #if defined(TIM_SR_B2IF)
00518 #define TIM_FLAG_BREAK2                    (TIM_SR_B2IF)
00519 #endif
00520 #define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)
00521 #define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)
00522 #define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)
00523 #define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)
00524 /**
00525   * @}
00526   */
00527
00528 /** @defgroup TIM_Clock_Source TIM Clock Source
00529   * @{
00530   */
00531 #define TIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1)
00532 #define TIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0)
00533 #define TIM_CLOCKSOURCE_ITR0        (0x0000U)
00534 #define TIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)
00535 #define TIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)
00536 #define TIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
00537 #define TIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)
00538 #define TIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
00539 #define TIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
00540 #define TIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS)
00541 /**
00542   * @}
00543   */
00544
00545 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
00546   * @{
00547   */
00548 #define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx clock sources */
00549 #define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx clock sources */
00550 #define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIx clock sources */
00551 #define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
00552 #define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
00553 /**
00554   * @}
00555   */
00556
00557 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
00558   * @{
00559   */
00560 #define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
00561 #define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
00562 #define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
00563 #define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
00564 /**
00565   * @}
00566   */
00567
00568 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
00569   * @{
00570   */
00571 #define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED                    /*!< Polarity for ETRx pin */
00572 #define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED                          /*!< Polarity for ETRx pin */
00573 /**
00574   * @}
00575   */
00576
00577 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
00578   * @{
00579   */
00580 #define TIM_CLEARINPUTPRESCALER_DIV1                    TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */
00581 #define TIM_CLEARINPUTPRESCALER_DIV2                    TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
00582 #define TIM_CLEARINPUTPRESCALER_DIV4                    TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
00583 #define TIM_CLEARINPUTPRESCALER_DIV8                    TIM_ETRPRESCALER_DIV8        /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
00584 /**
00585   * @}
00586   */
00587
00588 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
00589   * @{
00590   */
00591 #define TIM_OSSR_ENABLE        (TIM_BDTR_OSSR)
00592 #define TIM_OSSR_DISABLE              (0x0000U)
00593 /**
00594   * @}
00595   */
00596
00597 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
00598   * @{
00599   */
00600 #define TIM_OSSI_ENABLE       (TIM_BDTR_OSSI)
00601 #define TIM_OSSI_DISABLE            (0x0000U)
00602 /**
00603   * @}
00604   */
00605
00606 /** @defgroup TIM_Lock_level TIM Lock level
00607   * @{
00608   */
00609 #define TIM_LOCKLEVEL_OFF    (0x0000U)
00610 #define TIM_LOCKLEVEL_1            (TIM_BDTR_LOCK_0)
00611 #define TIM_LOCKLEVEL_2            (TIM_BDTR_LOCK_1)
00612 #define TIM_LOCKLEVEL_3            (TIM_BDTR_LOCK)
00613 /**
00614   * @}
00615   */
00616
00617 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
00618   * @{
00619   */
00620 #define TIM_BREAK_ENABLE          (TIM_BDTR_BKE)
00621 #define TIM_BREAK_DISABLE         (0x0000U)
00622 /**
00623   * @}
00624   */
00625
00626 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
00627   * @{
00628   */
00629 #define TIM_BREAKPOLARITY_LOW        (0x0000U)
00630 #define TIM_BREAKPOLARITY_HIGH       (TIM_BDTR_BKP)
00631 /**
00632   * @}
00633   */
00634 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
00635   * @{
00636   */
00637 #define TIM_AUTOMATICOUTPUT_ENABLE           (TIM_BDTR_AOE)
00638 #define TIM_AUTOMATICOUTPUT_DISABLE          (0x0000U)
00639 /**
00640   * @}
00641   */
00642
00643 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
00644   * @{
00645   */
00646 #define TIM_TRGO_RESET            (0x0000U)
00647 #define TIM_TRGO_ENABLE           (TIM_CR2_MMS_0)
00648 #define TIM_TRGO_UPDATE           (TIM_CR2_MMS_1)
00649 #define TIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
00650 #define TIM_TRGO_OC1REF           (TIM_CR2_MMS_2)
00651 #define TIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
00652 #define TIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
00653 #define TIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
00654 /**
00655   * @}
00656   */
00657
00658 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
00659   * @{
00660   */
00661 #define TIM_MASTERSLAVEMODE_ENABLE          (0x0080U)
00662 #define TIM_MASTERSLAVEMODE_DISABLE         (0x0000U)
00663 /**
00664   * @}
00665   */
00666
00667 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
00668   * @{
00669   */
00670 #define TIM_TS_ITR0                        (0x0000U)
00671 #define TIM_TS_ITR1                        (0x0010U)
00672 #define TIM_TS_ITR2                        (0x0020U)
00673 #define TIM_TS_ITR3                        (0x0030U)
00674 #define TIM_TS_TI1F_ED                     (0x0040U)
00675 #define TIM_TS_TI1FP1                      (0x0050U)
00676 #define TIM_TS_TI2FP2                      (0x0060U)
00677 #define TIM_TS_ETRF                        (0x0070U)
00678 #define TIM_TS_NONE                        (0xFFFFU)
00679 /**
00680   * @}
00681   */
00682
00683 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
00684   * @{
00685   */
00686 #define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx trigger sources */
00687 #define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx trigger sources */
00688 #define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00689 #define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00690 #define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00691 /**
00692   * @}
00693   */
00694
00695 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
00696   * @{
00697   */
00698 #define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
00699 #define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
00700 #define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
00701 #define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
00702 /**
00703   * @}
00704   */
00705
00706   /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
00707   * @{
00708   */
00709 #define TIM_TI1SELECTION_CH1                (0x0000U)
00710 #define TIM_TI1SELECTION_XORCOMBINATION     (TIM_CR2_TI1S)
00711 /**
00712   * @}
00713   */
00714
00715 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
00716   * @{
00717   */
00718 #define TIM_DMABURSTLENGTH_1TRANSFER           (0x00000000U)
00719 #define TIM_DMABURSTLENGTH_2TRANSFERS          (0x00000100U)
00720 #define TIM_DMABURSTLENGTH_3TRANSFERS          (0x00000200U)
00721 #define TIM_DMABURSTLENGTH_4TRANSFERS          (0x00000300U)
00722 #define TIM_DMABURSTLENGTH_5TRANSFERS          (0x00000400U)
00723 #define TIM_DMABURSTLENGTH_6TRANSFERS          (0x00000500U)
00724 #define TIM_DMABURSTLENGTH_7TRANSFERS          (0x00000600U)
00725 #define TIM_DMABURSTLENGTH_8TRANSFERS          (0x00000700U)
00726 #define TIM_DMABURSTLENGTH_9TRANSFERS          (0x00000800U)
00727 #define TIM_DMABURSTLENGTH_10TRANSFERS         (0x00000900U)
00728 #define TIM_DMABURSTLENGTH_11TRANSFERS         (0x00000A00U)
00729 #define TIM_DMABURSTLENGTH_12TRANSFERS         (0x00000B00U)
00730 #define TIM_DMABURSTLENGTH_13TRANSFERS         (0x00000C00U)
00731 #define TIM_DMABURSTLENGTH_14TRANSFERS         (0x00000D00U)
00732 #define TIM_DMABURSTLENGTH_15TRANSFERS         (0x00000E00U)
00733 #define TIM_DMABURSTLENGTH_16TRANSFERS         (0x00000F00U)
00734 #define TIM_DMABURSTLENGTH_17TRANSFERS         (0x00001000U)
00735 #define TIM_DMABURSTLENGTH_18TRANSFERS         (0x00001100U)
00736 /**
00737   * @}
00738   */
00739
00740 /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
00741   * @{
00742   */
00743 #define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0U)       /*!< Index of the DMA handle used for Update DMA requests */
00744 #define TIM_DMA_ID_CC1                   ((uint16_t) 0x1U)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
00745 #define TIM_DMA_ID_CC2                   ((uint16_t) 0x2U)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
00746 #define TIM_DMA_ID_CC3                   ((uint16_t) 0x3U)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
00747 #define TIM_DMA_ID_CC4                   ((uint16_t) 0x4U)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
00748 #define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x5U)       /*!< Index of the DMA handle used for Commutation DMA requests */
00749 #define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x6U)       /*!< Index of the DMA handle used for Trigger DMA requests */
00750 /**
00751   * @}
00752   */
00753
00754 /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
00755   * @{
00756   */
00757 #define TIM_CCx_ENABLE                   (0x0001U)
00758 #define TIM_CCx_DISABLE                  (0x0000U)
00759 #define TIM_CCxN_ENABLE                  (0x0004U)
00760 #define TIM_CCxN_DISABLE                 (0x0000U)
00761 /**
00762   * @}
00763   */
00764
00765 /**
00766   * @}
00767   */
00768 /* End of exported constants -------------------------------------------------*/
00769
00770 /* Exported macros -----------------------------------------------------------*/
00771 /** @defgroup TIM_Exported_Macros TIM Exported Macros
00772   * @{
00773   */
00774
00775 /** @brief  Reset TIM handle state
00776   * @param  __HANDLE__ TIM handle.
00777   * @retval None
00778   */
00779 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
00780
00781 /**
00782   * @brief  Enable the TIM peripheral.
00783   * @param  __HANDLE__ TIM handle
00784   * @retval None
00785  */
00786 #define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
00787
00788 /**
00789   * @brief  Enable the TIM main Output.
00790   * @param  __HANDLE__ TIM handle
00791   * @retval None
00792   */
00793 #define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
00794
00795 /**
00796   * @brief  Disable the TIM peripheral.
00797   * @param  __HANDLE__ TIM handle
00798   * @retval None
00799   */
00800 #define __HAL_TIM_DISABLE(__HANDLE__) \
00801                         do { \
00802                           if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
00803                             { \
00804                             if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
00805                             { \
00806                               (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
00807                             } \
00808                           } \
00809                         } while(0U)
00810 /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
00811    channels have been disabled */
00812 /**
00813   * @brief  Disable the TIM main Output.
00814   * @param  __HANDLE__ TIM handle
00815   * @retval None
00816   * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
00817   */
00818 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
00819                         do { \
00820                           if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
00821                           { \
00822                             if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
00823                             { \
00824                               (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
00825                             } \
00826                             } \
00827                         } while(0U)
00828
00829 /* The Main Output Enable of a timer instance is disabled unconditionally */
00830 /**
00831   * @brief  Disable the TIM main Output.
00832   * @param  __HANDLE__ TIM handle
00833   * @retval None
00834   * @note The Main Output Enable of a timer instance is disabled uncondiotionally
00835   */
00836 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
00837
00838 /**
00839   * @brief  Enables the specified TIM interrupt.
00840   * @param  __HANDLE__ specifies the TIM Handle.
00841   * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
00842   *          This parameter can be one of the following values:
00843   *            @arg TIM_IT_UPDATE: Update interrupt
00844   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
00845   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
00846   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
00847   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
00848   *            @arg TIM_IT_COM:   Commutation interrupt
00849   *            @arg TIM_IT_TRIGGER: Trigger interrupt
00850   *            @arg TIM_IT_BREAK: Break interrupt
00851   * @retval None
00852   */
00853 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
00854
00855 /**
00856   * @brief  Disables the specified TIM interrupt.
00857   * @param  __HANDLE__ specifies the TIM Handle.
00858   * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
00859   *          This parameter can be one of the following values:
00860   *            @arg TIM_IT_UPDATE: Update interrupt
00861   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
00862   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
00863   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
00864   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
00865   *            @arg TIM_IT_COM:   Commutation interrupt
00866   *            @arg TIM_IT_TRIGGER: Trigger interrupt
00867   *            @arg TIM_IT_BREAK: Break interrupt
00868   * @retval None
00869   */
00870 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
00871
00872 /**
00873   * @brief  Enables the specified DMA request.
00874   * @param  __HANDLE__ specifies the TIM Handle.
00875   * @param  __DMA__ specifies the TIM DMA request to enable.
00876   *          This parameter can be one of the following values:
00877   *            @arg TIM_DMA_UPDATE: Update DMA request
00878   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
00879   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
00880   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
00881   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
00882   *            @arg TIM_DMA_COM:   Commutation DMA request
00883   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
00884   * @retval None
00885   */
00886 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)  ((__HANDLE__)->Instance->DIER |= (__DMA__))
00887
00888 /**
00889   * @brief  Disables the specified DMA request.
00890   * @param  __HANDLE__ specifies the TIM Handle.
00891   * @param  __DMA__ specifies the TIM DMA request to disable.
00892   *          This parameter can be one of the following values:
00893   *            @arg TIM_DMA_UPDATE: Update DMA request
00894   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
00895   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
00896   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
00897   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
00898   *            @arg TIM_DMA_COM:   Commutation DMA request
00899   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
00900   * @retval None
00901   */
00902 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)  ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
00903
00904 /**
00905   * @brief  Checks whether the specified TIM interrupt flag is set or not.
00906   * @param  __HANDLE__ specifies the TIM Handle.
00907   * @param  __FLAG__ specifies the TIM interrupt flag to check.
00908   *        This parameter can be one of the following values:
00909   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
00910   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
00911   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
00912   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
00913   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
00914   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
00915   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
00916   *            @arg TIM_FLAG_BREAK: Break interrupt flag
00917   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
00918   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
00919   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
00920   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
00921   * @retval The new state of __FLAG__ (TRUE or FALSE).
00922   */
00923 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)       (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
00924
00925 /**
00926   * @brief  Clears the specified TIM interrupt flag.
00927   * @param  __HANDLE__ specifies the TIM Handle.
00928   * @param  __FLAG__ specifies the TIM interrupt flag to clear.
00929   *        This parameter can be one of the following values:
00930   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
00931   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
00932   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
00933   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
00934   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
00935   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
00936   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
00937   *            @arg TIM_FLAG_BREAK: Break interrupt flag
00938   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
00939   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
00940   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
00941   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
00942   * @retval The new state of __FLAG__ (TRUE or FALSE).
00943   */
00944 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)       ((__HANDLE__)->Instance->SR = ~(__FLAG__))
00945
00946 /**
00947   * @brief  Checks whether the specified TIM interrupt has occurred or not.
00948   * @param  __HANDLE__ TIM handle
00949   * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
00950   * @retval The state of TIM_IT (SET or RESET).
00951   */
00952 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00953
00954 /**
00955   * @brief Clear the TIM interrupt pending bits
00956   * @param  __HANDLE__ TIM handle
00957   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
00958   * @retval None
00959   */
00960 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
00961
00962 /**
00963   * @brief  Indicates whether or not the TIM Counter is used as downcounter
00964   * @param  __HANDLE__ TIM handle.
00965   * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
00966   * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder mode.
00967   */
00968 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)       (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
00969
00970 /**
00971   * @brief  Sets the TIM active prescaler register value on update event.
00972   * @param  __HANDLE__ TIM handle.
00973   * @param  __PRESC__ specifies the active prescaler register new value.
00974   * @retval None
00975   */
00976 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)  ((__HANDLE__)->Instance->PSC = (__PRESC__))
00977
00978 /**
00979   * @brief  Sets the TIM Counter Register value on runtime.
00980   * @param  __HANDLE__ TIM handle.
00981   * @param  __COUNTER__ specifies the Counter register new value.
00982   * @retval None
00983   */
00984 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
00985
00986 /**
00987   * @brief  Gets the TIM Counter Register value on runtime.
00988   * @param  __HANDLE__ TIM handle.
00989   * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
00990   */
00991 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
00992    ((__HANDLE__)->Instance->CNT)
00993
00994 /**
00995   * @brief  Sets the TIM Autoreload Register value on runtime without calling
00996   *         another time any Init function.
00997   * @param  __HANDLE__ TIM handle.
00998   * @param  __AUTORELOAD__ specifies the Counter register new value.
00999   * @retval None
01000   */
01001 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
01002                         do{                                                    \
01003                               (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
01004                               (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
01005                           } while(0U)
01006
01007 /**
01008   * @brief  Gets the TIM Autoreload Register value on runtime
01009   * @param  __HANDLE__ TIM handle.
01010   * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
01011   */
01012 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
01013    ((__HANDLE__)->Instance->ARR)
01014
01015 /**
01016   * @brief  Sets the TIM Clock Division value on runtime without calling
01017   *         another time any Init function.
01018   * @param  __HANDLE__ TIM handle.
01019   * @param  __CKD__ specifies the clock division value.
01020   *          This parameter can be one of the following value:
01021   *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
01022   *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
01023   *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
01024   * @retval None
01025   */
01026 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
01027                         do{                                                    \
01028                               (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
01029                               (__HANDLE__)->Instance->CR1 |= (__CKD__);                   \
01030                               (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
01031                           } while(0U)
01032
01033 /**
01034   * @brief  Gets the TIM Clock Division value on runtime
01035   * @param  __HANDLE__ TIM handle.
01036   * @retval The clock division can be one of the following values:
01037   *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
01038   *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
01039   *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
01040   */
01041 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  \
01042    ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
01043
01044 /**
01045   * @brief  Sets the TIM Input Capture prescaler on runtime without calling
01046   *         another time HAL_TIM_IC_ConfigChannel() function.
01047   * @param  __HANDLE__ TIM handle.
01048   * @param  __CHANNEL__ TIM Channels to be configured.
01049   *          This parameter can be one of the following values:
01050   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01051   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01052   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01053   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01054   * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
01055   *          This parameter can be one of the following values:
01056   *            @arg TIM_ICPSC_DIV1: no prescaler
01057   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01058   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01059   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01060   * @retval None
01061   */
01062 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
01063                         do{                                                    \
01064                               TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
01065                               TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
01066                           } while(0U)
01067
01068 /**
01069   * @brief  Gets the TIM Input Capture prescaler on runtime
01070   * @param  __HANDLE__ TIM handle.
01071   * @param  __CHANNEL__ TIM Channels to be configured.
01072   *          This parameter can be one of the following values:
01073   *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
01074   *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
01075   *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
01076   *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
01077   * @retval The input capture prescaler can be one of the following values:
01078   *            @arg TIM_ICPSC_DIV1: no prescaler
01079   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01080   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01081   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01082   */
01083 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
01084   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
01085    ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
01086    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
01087    (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
01088
01089 /**
01090   * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register
01091   * @param  __HANDLE__ TIM handle.
01092   * @note  When the USR bit of the TIMx_CR1 register is set, only counter
01093   *        overflow/underflow generates an update interrupt or DMA request (if
01094   *        enabled)
01095   * @retval None
01096   */
01097 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
01098     ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
01099
01100 /**
01101   * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register
01102   * @param  __HANDLE__ TIM handle.
01103   * @note  When the USR bit of the TIMx_CR1 register is reset, any of the
01104   *        following events generate an update interrupt or DMA request (if
01105   *        enabled):
01106   *          (+) Counter overflow/underflow
01107   *          (+) Setting the UG bit
01108   *          (+) Update generation through the slave mode controller
01109   * @retval None
01110   */
01111 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
01112       ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
01113
01114 /**
01115   * @brief  Sets the TIM Capture x input polarity on runtime.
01116   * @param  __HANDLE__ TIM handle.
01117   * @param  __CHANNEL__ TIM Channels to be configured.
01118   *          This parameter can be one of the following values:
01119   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01120   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01121   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01122   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01123   * @param  __POLARITY__ Polarity for TIx source
01124   *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
01125   *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
01126   *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
01127   * @retval None
01128   */
01129 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
01130         do{                                                                     \
01131           TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
01132           TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
01133         }while(0U)
01134
01135 /**
01136   * @}
01137   */
01138 /* End of exported macros ----------------------------------------------------*/
01139
01140 /* Private Constants -----------------------------------------------------------*/
01141 /** @defgroup TIM_Private_Constants TIM Private Constants
01142   * @{
01143   */
01144
01145 /* The counter of a timer instance is disabled only if all the CCx and CCxN
01146    channels have been disabled */
01147 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
01148 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
01149
01150 /**
01151   * @}
01152   */
01153 /* End of private constants --------------------------------------------------*/
01154
01155 /* Private Macros -----------------------------------------------------------*/
01156 /** @defgroup TIM_Private_Macros TIM Private Macros
01157   * @{
01158   */
01159
01160 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP)              || \
01161                                    ((MODE) == TIM_COUNTERMODE_DOWN)            || \
01162                                    ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
01163                                    ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
01164                                    ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
01165
01166 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
01167                                        ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
01168                                        ((DIV) == TIM_CLOCKDIVISION_DIV4))
01169
01170 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
01171                                             ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
01172
01173 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
01174                                   ((STATE) == TIM_OCFAST_ENABLE))
01175
01176 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
01177                                       ((POLARITY) == TIM_OCPOLARITY_LOW))
01178
01179 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
01180                                        ((POLARITY) == TIM_OCNPOLARITY_LOW))
01181
01182 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
01183                                     ((STATE) == TIM_OCIDLESTATE_RESET))
01184
01185 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
01186                                      ((STATE) == TIM_OCNIDLESTATE_RESET))
01187
01188
01189 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING)   || \
01190                                       ((POLARITY) == TIM_ICPOLARITY_FALLING)  || \
01191                                       ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
01192
01193 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
01194                                         ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
01195                                         ((SELECTION) == TIM_ICSELECTION_TRC))
01196
01197 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
01198                                         ((PRESCALER) == TIM_ICPSC_DIV2) || \
01199                                         ((PRESCALER) == TIM_ICPSC_DIV4) || \
01200                                         ((PRESCALER) == TIM_ICPSC_DIV8))
01201
01202 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
01203                               ((MODE) == TIM_OPMODE_REPETITIVE))
01204
01205 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
01206                                    ((MODE) == TIM_ENCODERMODE_TI2) || \
01207                                    ((MODE) == TIM_ENCODERMODE_TI12))
01208
01209 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
01210
01211
01212 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
01213                                    ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
01214                                    ((CLOCK) == TIM_CLOCKSOURCE_ITR0)     || \
01215                                    ((CLOCK) == TIM_CLOCKSOURCE_ITR1)     || \
01216                                    ((CLOCK) == TIM_CLOCKSOURCE_ITR2)     || \
01217                                    ((CLOCK) == TIM_CLOCKSOURCE_ITR3)     || \
01218                                    ((CLOCK) == TIM_CLOCKSOURCE_TI1ED)    || \
01219                                    ((CLOCK) == TIM_CLOCKSOURCE_TI1)      || \
01220                                    ((CLOCK) == TIM_CLOCKSOURCE_TI2)      || \
01221                                    ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
01222
01223 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED)    || \
01224                                         ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
01225                                         ((POLARITY) == TIM_CLOCKPOLARITY_RISING)      || \
01226                                         ((POLARITY) == TIM_CLOCKPOLARITY_FALLING)     || \
01227                                         ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
01228
01229 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
01230                                           ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
01231                                           ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
01232                                           ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
01233
01234 #define IS_TIM_CLOCKFILTER(ICFILTER)      ((ICFILTER) <= 0xFU)
01235
01236 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
01237                                              ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
01238
01239 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER)   (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
01240                                                 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
01241                                                 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
01242                                                 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
01243
01244 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
01245
01246 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
01247                                   ((STATE) == TIM_OSSR_DISABLE))
01248
01249 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
01250                                   ((STATE) == TIM_OSSI_DISABLE))
01251
01252 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
01253                                   ((LEVEL) == TIM_LOCKLEVEL_1) || \
01254                                   ((LEVEL) == TIM_LOCKLEVEL_2) || \
01255                                   ((LEVEL) == TIM_LOCKLEVEL_3))
01256
01257 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
01258                                    ((STATE) == TIM_BREAK_DISABLE))
01259
01260 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
01261                                          ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
01262
01263 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
01264                                               ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
01265
01266 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
01267                                     ((SOURCE) == TIM_TRGO_ENABLE) || \
01268                                     ((SOURCE) == TIM_TRGO_UPDATE) || \
01269                                     ((SOURCE) == TIM_TRGO_OC1) || \
01270                                     ((SOURCE) == TIM_TRGO_OC1REF) || \
01271                                     ((SOURCE) == TIM_TRGO_OC2REF) || \
01272                                     ((SOURCE) == TIM_TRGO_OC3REF) || \
01273                                     ((SOURCE) == TIM_TRGO_OC4REF))
01274
01275 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
01276                                  ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
01277
01278 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
01279                                              ((SELECTION) == TIM_TS_ITR1) || \
01280                                              ((SELECTION) == TIM_TS_ITR2) || \
01281                                              ((SELECTION) == TIM_TS_ITR3) || \
01282                                              ((SELECTION) == TIM_TS_TI1F_ED) || \
01283                                              ((SELECTION) == TIM_TS_TI1FP1) || \
01284                                              ((SELECTION) == TIM_TS_TI2FP2) || \
01285                                              ((SELECTION) == TIM_TS_ETRF))
01286
01287 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
01288                                                            ((SELECTION) == TIM_TS_ITR1) || \
01289                                                            ((SELECTION) == TIM_TS_ITR2) || \
01290                                                            ((SELECTION) == TIM_TS_ITR3) || \
01291                                                            ((SELECTION) == TIM_TS_NONE))
01292
01293 #define IS_TIM_TRIGGERPOLARITY(POLARITY)     (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
01294                                               ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
01295                                               ((POLARITY) == TIM_TRIGGERPOLARITY_RISING     ) || \
01296                                               ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING    ) || \
01297                                               ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
01298
01299 #define IS_TIM_TRIGGERPRESCALER(PRESCALER)  (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
01300                                              ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
01301                                              ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
01302                                              ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
01303
01304 #define IS_TIM_TRIGGERFILTER(ICFILTER)     ((ICFILTER) <= 0xFU)
01305
01306 #define IS_TIM_TI1SELECTION(TI1SELECTION)   (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
01307                                              ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
01308
01309 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
01310                                    ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
01311                                    ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
01312                                    ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
01313                                    ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
01314                                    ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
01315                                    ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
01316                                    ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
01317                                    ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
01318                                    ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
01319                                    ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
01320                                    ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
01321                                    ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
01322                                    ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
01323                                    ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
01324                                    ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
01325                                    ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
01326                                    ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
01327
01328 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
01329
01330 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
01331
01332 /** @brief Set TIM IC prescaler
01333   * @param  __HANDLE__ TIM handle
01334   * @param  __CHANNEL__ specifies TIM Channel
01335   * @param  __ICPSC__ specifies the prescaler value.
01336   * @retval None
01337   */
01338 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
01339 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
01340  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
01341  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
01342  ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
01343
01344 /** @brief Reset TIM IC prescaler
01345   * @param  __HANDLE__ TIM handle
01346   * @param  __CHANNEL__ specifies TIM Channel
01347   * @retval None
01348   */
01349 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
01350 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
01351  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
01352  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
01353  ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
01354
01355 /** @brief Set TIM IC polarity
01356   * @param  __HANDLE__ TIM handle
01357   * @param  __CHANNEL__ specifies TIM Channel
01358   * @param  __POLARITY__ specifies TIM Channel Polarity
01359   * @retval None
01360   */
01361 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
01362 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
01363  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
01364  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
01365  ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
01366
01367 /** @brief Reset TIM IC polarity
01368   * @param  __HANDLE__ TIM handle
01369   * @param  __CHANNEL__ specifies TIM Channel
01370   * @retval None
01371   */
01372 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
01373 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
01374  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
01375  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
01376  ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
01377 /**
01378   * @}
01379   */
01380 /* End of private macros -----------------------------------------------------*/
01381
01382 /* Include TIM HAL Extended module */
01383 #include "stm32f3xx_hal_tim_ex.h"
01384
01385 /* Exported functions --------------------------------------------------------*/
01386 /** @addtogroup TIM_Exported_Functions
01387   * @{
01388   */
01389
01390 /** @addtogroup TIM_Exported_Functions_Group1
01391  * @{
01392  */
01393 /* Time Base functions ********************************************************/
01394 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
01395 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
01396 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
01397 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
01398 /* Blocking mode: Polling */
01399 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
01400 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
01401 /* Non-Blocking mode: Interrupt */
01402 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
01403 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
01404 /* Non-Blocking mode: DMA */
01405 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
01406 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
01407 /**
01408   * @}
01409   */
01410
01411 /** @addtogroup TIM_Exported_Functions_Group2
01412  * @{
01413  */
01414 /* Timer Output Compare functions **********************************************/
01415 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
01416 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
01417 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
01418 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
01419 /* Blocking mode: Polling */
01420 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01421 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01422 /* Non-Blocking mode: Interrupt */
01423 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01424 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01425 /* Non-Blocking mode: DMA */
01426 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01427 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01428
01429 /**
01430   * @}
01431   */
01432
01433 /** @addtogroup TIM_Exported_Functions_Group3
01434  * @{
01435  */
01436 /* Timer PWM functions *********************************************************/
01437 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
01438 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
01439 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
01440 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
01441 /* Blocking mode: Polling */
01442 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01443 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01444 /* Non-Blocking mode: Interrupt */
01445 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01446 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01447 /* Non-Blocking mode: DMA */
01448 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01449 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01450 /**
01451   * @}
01452   */
01453
01454 /** @addtogroup TIM_Exported_Functions_Group4
01455  * @{
01456  */
01457 /* Timer Input Capture functions ***********************************************/
01458 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
01459 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
01460 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
01461 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
01462 /* Blocking mode: Polling */
01463 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01464 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01465 /* Non-Blocking mode: Interrupt */
01466 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01467 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01468 /* Non-Blocking mode: DMA */
01469 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01470 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01471 /**
01472   * @}
01473   */
01474
01475 /** @addtogroup TIM_Exported_Functions_Group5
01476  * @{
01477  */
01478 /* Timer One Pulse functions ***************************************************/
01479 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
01480 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
01481 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
01482 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
01483 /* Blocking mode: Polling */
01484 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01485 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01486 /* Non-Blocking mode: Interrupt */
01487 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01488 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01489 /**
01490   * @}
01491   */
01492
01493 /** @addtogroup TIM_Exported_Functions_Group6
01494  * @{
01495  */
01496 /* Timer Encoder functions *****************************************************/
01497 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);
01498 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
01499 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
01500 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
01501  /* Blocking mode: Polling */
01502 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01503 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01504 /* Non-Blocking mode: Interrupt */
01505 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01506 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01507 /* Non-Blocking mode: DMA */
01508 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
01509 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01510
01511 /**
01512   * @}
01513   */
01514
01515 /** @addtogroup TIM_Exported_Functions_Group7
01516   * @{
01517   */
01518 /* Interrupt Handler functions  **********************************************/
01519 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
01520 /**
01521   * @}
01522   */
01523
01524 /** @addtogroup TIM_Exported_Functions_Group8
01525   * @{
01526   */
01527 /* Control functions  *********************************************************/
01528 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
01529 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
01530 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
01531 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);
01532 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
01533 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
01534 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
01535 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
01536 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
01537 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
01538                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
01539 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
01540                                                    uint32_t  *BurstBuffer, uint32_t  BurstLength, uint32_t  DataLength);
01541 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
01542 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
01543                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
01544 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
01545                                                   uint32_t  *BurstBuffer, uint32_t  BurstLength, uint32_t  DataLength);
01546 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
01547 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
01548 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
01549
01550 /**
01551   * @}
01552   */
01553
01554 /** @addtogroup TIM_Exported_Functions_Group9
01555   * @{
01556   */
01557 /* Callback in non blocking modes (Interrupt and DMA) *************************/
01558 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
01559 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
01560 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
01561 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
01562 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
01563 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
01564 /**
01565   * @}
01566   */
01567
01568 /** @addtogroup TIM_Exported_Functions_Group10
01569  * @{
01570  */
01571 /* Peripheral State functions  **************************************************/
01572 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
01573 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
01574 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
01575 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
01576 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
01577 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
01578
01579 /**
01580   * @}
01581   */
01582
01583 /**
01584   * @}
01585   */
01586 /* End of exported functions -------------------------------------------------*/
01587
01588 /* Private Functions --------------------------------------------------------*/
01589 /** @addtogroup TIM_Private_Functions
01590  * @{
01591  */
01592 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
01593 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
01594 void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
01595 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
01596 void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
01597 void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
01598 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
01599                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
01600 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
01601 void TIM_DMAError(DMA_HandleTypeDef *hdma);
01602 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
01603 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
01604 /**
01605   * @}
01606   */
01607 /* End of private functions --------------------------------------------------*/
01608
01609 /**
01610   * @}
01611   */
01612
01613 /**
01614   * @}
01615   */
01616
01617 #ifdef __cplusplus
01618 }
01619 #endif
01620
01621 #endif /* __STM32F3xx_HAL_TIM_H */
01622
01623 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_tim_ex.c Source File

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stm32f3xx_hal_tim_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_tim_ex.c
00004   * @author  MCD Application Team
00005   * @brief   TIM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Timer Extended peripheral:
00008   *           + Time Hall Sensor Interface Initialization
00009   *           + Time Hall Sensor Interface Start
00010   *           + Time Complementary signal bread and dead time configuration
00011   *           + Time Master and Slave synchronization configuration
00012   *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
00013   *           + Time OCRef clear configuration
00014   *           + Timer remapping capabilities configuration
00015   @verbatim
00016   ==============================================================================
00017                       ##### TIMER Extended features #####
00018   ==============================================================================
00019   [..]
00020     The Timer Extended features include:
00021     (#) Complementary outputs with programmable dead-time for :
00022         (++) Output Compare
00023         (++) PWM generation (Edge and Center-aligned Mode)
00024         (++) One-pulse mode output
00025     (#) Synchronization circuit to control the timer with external signals and to
00026         interconnect several timers together.
00027     (#) Break input to put the timer output signals in reset state or in a known state.
00028     (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
00029         positioning purposes
00030
00031             ##### How to use this driver #####
00032   ==============================================================================
00033     [..]
00034      (#) Initialize the TIM low level resources by implementing the following functions
00035          depending from feature used :
00036            (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
00037            (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
00038            (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
00039            (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
00040
00041      (#) Initialize the TIM low level resources :
00042         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE  ();
00043         (##) TIM pins configuration
00044             (+++) Enable the clock for the TIM GPIOs using the following function:
00045               __HAL_RCC_GPIOx_CLK_ENABLE();
00046             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00047
00048      (#) The external Clock can be configured, if needed (the default clock is the
00049          internal clock from the APBx), using the following function:
00050          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00051          any start function.
00052
00053      (#) Configure the TIM in the desired functioning mode using one of the
00054          initialization function of this driver:
00055           (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
00056               Timer Hall Sensor Interface and the commutation event with the corresponding
00057               Interrupt and DMA request if needed (Note that One Timer is used to interface
00058              with the Hall sensor Interface and another Timer should be used to use
00059              the commutation event).
00060
00061      (#) Activate the TIM peripheral using one of the start functions:
00062            (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
00063            (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
00064            (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
00065            (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
00066
00067
00068   @endverbatim
00069   ******************************************************************************
00070   * @attention
00071   *
00072   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00073   *
00074   * Redistribution and use in source and binary forms, with or without modification,
00075   * are permitted provided that the following conditions are met:
00076   *   1. Redistributions of source code must retain the above copyright notice,
00077   *      this list of conditions and the following disclaimer.
00078   *   2. Redistributions in binary form must reproduce the above copyright notice,
00079   *      this list of conditions and the following disclaimer in the documentation
00080   *      and/or other materials provided with the distribution.
00081   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00082   *      may be used to endorse or promote products derived from this software
00083   *      without specific prior written permission.
00084   *
00085   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00086   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00087   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00088   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00089   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00090   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00091   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00092   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00093   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00094   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00095   *
00096   ******************************************************************************
00097 */
00098
00099 /* Includes ------------------------------------------------------------------*/
00100 #include "stm32f3xx_hal.h"
00101
00102 /** @addtogroup STM32F3xx_HAL_Driver
00103   * @{
00104   */
00105
00106 /** @defgroup TIMEx TIMEx
00107   * @brief TIM Extended HAL module driver
00108   * @{
00109   */
00110
00111 #ifdef HAL_TIM_MODULE_ENABLED
00112
00113 /* Private typedef -----------------------------------------------------------*/
00114 /* Private define ------------------------------------------------------------*/
00115 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00116     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00117     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00118     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00119
00120 #define BDTR_BKF_SHIFT (16U)
00121 #define BDTR_BK2F_SHIFT (20U)
00122 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00123        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00124        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00125        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00126
00127 /* Private macro -------------------------------------------------------------*/
00128 /* Private variables ---------------------------------------------------------*/
00129 /* Private function prototypes -----------------------------------------------*/
00130
00131 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
00132   * @{
00133   */
00134 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
00135
00136 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00137     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00138     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00139     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00140 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
00141                               TIM_OC_InitTypeDef *OC_Config);
00142
00143 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
00144                               TIM_OC_InitTypeDef *OC_Config);
00145 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00146        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00147        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00148        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00149
00150 /**
00151   * @}
00152   */
00153
00154 /* Exported functions ---------------------------------------------------------*/
00155
00156 /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
00157   * @{
00158   */
00159
00160 /** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
00161   * @brief    Timer Hall Sensor functions
00162   *
00163 @verbatim
00164   ==============================================================================
00165                       ##### Timer Hall Sensor functions #####
00166   ==============================================================================
00167   [..]
00168     This section provides functions allowing to:
00169     (+) Initialize and configure TIM HAL Sensor.
00170     (+) De-initialize TIM HAL Sensor.
00171     (+) Start the Hall Sensor Interface.
00172     (+) Stop the Hall Sensor Interface.
00173     (+) Start the Hall Sensor Interface and enable interrupts.
00174     (+) Stop the Hall Sensor Interface and disable interrupts.
00175     (+) Start the Hall Sensor Interface and enable DMA transfers.
00176     (+) Stop the Hall Sensor Interface and disable DMA transfers.
00177
00178 @endverbatim
00179   * @{
00180   */
00181 /**
00182   * @brief  Initializes the TIM Hall Sensor Interface and create the associated handle.
00183   * @param  htim TIM Encoder Interface handle
00184   * @param  sConfig TIM Hall Sensor configuration structure
00185   * @retval HAL status
00186   */
00187 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
00188 {
00189   TIM_OC_InitTypeDef OC_Config;
00190
00191   /* Check the TIM handle allocation */
00192   if(htim == NULL)
00193   {
00194     return HAL_ERROR;
00195   }
00196
00197   assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
00198   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00199   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00200   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00201   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
00202   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
00203   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
00204
00205   if(htim->State == HAL_TIM_STATE_RESET)
00206   {
00207     /* Allocate lock resource and initialize it */
00208     htim->Lock = HAL_UNLOCKED;
00209
00210     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00211     HAL_TIMEx_HallSensor_MspInit(htim);
00212   }
00213
00214   /* Set the TIM state */
00215   htim->State = HAL_TIM_STATE_BUSY;
00216
00217   /* Configure the Time base in the Encoder Mode */
00218   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00219
00220   /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
00221   TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
00222
00223   /* Reset the IC1PSC Bits */
00224   htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
00225   /* Set the IC1PSC value */
00226   htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
00227
00228   /* Enable the Hall sensor interface (XOR function of the three inputs) */
00229   htim->Instance->CR2 |= TIM_CR2_TI1S;
00230
00231   /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
00232   htim->Instance->SMCR &= ~TIM_SMCR_TS;
00233   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
00234
00235   /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
00236   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
00237   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
00238
00239   /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
00240   OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
00241   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
00242   OC_Config.OCMode = TIM_OCMODE_PWM2;
00243   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
00244   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
00245   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
00246   OC_Config.Pulse = sConfig->Commutation_Delay;
00247
00248   TIM_OC2_SetConfig(htim->Instance, &OC_Config);
00249
00250   /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
00251     register to 101U */
00252   htim->Instance->CR2 &= ~TIM_CR2_MMS;
00253   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
00254
00255   /* Initialize the TIM state*/
00256   htim->State= HAL_TIM_STATE_READY;
00257
00258   return HAL_OK;
00259 }
00260
00261 /**
00262   * @brief  DeInitializes the TIM Hall Sensor interface
00263   * @param  htim TIM Hall Sensor handle
00264   * @retval HAL status
00265   */
00266 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
00267 {
00268   /* Check the parameters */
00269   assert_param(IS_TIM_INSTANCE(htim->Instance));
00270
00271   htim->State = HAL_TIM_STATE_BUSY;
00272
00273   /* Disable the TIM Peripheral Clock */
00274   __HAL_TIM_DISABLE(htim);
00275
00276   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00277   HAL_TIMEx_HallSensor_MspDeInit(htim);
00278
00279   /* Change TIM state */
00280   htim->State = HAL_TIM_STATE_RESET;
00281
00282   /* Release Lock */
00283   __HAL_UNLOCK(htim);
00284
00285   return HAL_OK;
00286 }
00287
00288 /**
00289   * @brief  Initializes the TIM Hall Sensor MSP.
00290   * @param  htim TIM handle
00291   * @retval None
00292   */
00293 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
00294 {
00295   /* Prevent unused argument(s) compilation warning */
00296   UNUSED(htim);
00297
00298   /* NOTE : This function Should not be modified, when the callback is needed,
00299             the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
00300    */
00301 }
00302
00303 /**
00304   * @brief  DeInitializes TIM Hall Sensor MSP.
00305   * @param  htim TIM handle
00306   * @retval None
00307   */
00308 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
00309 {
00310   /* Prevent unused argument(s) compilation warning */
00311   UNUSED(htim);
00312
00313   /* NOTE : This function Should not be modified, when the callback is needed,
00314             the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
00315    */
00316 }
00317
00318 /**
00319   * @brief  Starts the TIM Hall Sensor Interface.
00320   * @param  htim TIM Hall Sensor handle
00321   * @retval HAL status
00322   */
00323 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
00324 {
00325   /* Check the parameters */
00326   assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
00327
00328   /* Enable the Input Capture channel 1
00329     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00330   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00331
00332   /* Enable the Peripheral */
00333   __HAL_TIM_ENABLE(htim);
00334
00335   /* Return function status */
00336   return HAL_OK;
00337 }
00338
00339 /**
00340   * @brief  Stops the TIM Hall sensor Interface.
00341   * @param  htim TIM Hall Sensor handle
00342   * @retval HAL status
00343   */
00344 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
00345 {
00346   /* Check the parameters */
00347   assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
00348
00349   /* Disable the Input Capture channels 1U, 2 and 3
00350     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00351   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00352
00353   /* Disable the Peripheral */
00354   __HAL_TIM_DISABLE(htim);
00355
00356   /* Return function status */
00357   return HAL_OK;
00358 }
00359
00360 /**
00361   * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
00362   * @param  htim TIM Hall Sensor handle
00363   * @retval HAL status
00364   */
00365 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
00366 {
00367   /* Check the parameters */
00368   assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
00369
00370   /* Enable the capture compare Interrupts 1 event */
00371   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00372
00373   /* Enable the Input Capture channel 1
00374     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00375   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00376
00377   /* Enable the Peripheral */
00378   __HAL_TIM_ENABLE(htim);
00379
00380   /* Return function status */
00381   return HAL_OK;
00382 }
00383
00384 /**
00385   * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
00386   * @param  htim TIM handle
00387   * @retval HAL status
00388   */
00389 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
00390 {
00391   /* Check the parameters */
00392   assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
00393
00394   /* Disable the Input Capture channel 1
00395     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00396   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00397
00398   /* Disable the capture compare Interrupts event */
00399   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00400
00401   /* Disable the Peripheral */
00402   __HAL_TIM_DISABLE(htim);
00403
00404   /* Return function status */
00405   return HAL_OK;
00406 }
00407
00408 /**
00409   * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
00410   * @param  htim TIM Hall Sensor handle
00411   * @param  pData The destination Buffer address.
00412   * @param  Length The length of data to be transferred from TIM peripheral to memory.
00413   * @retval HAL status
00414   */
00415 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00416 {
00417   /* Check the parameters */
00418   assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
00419
00420    if((htim->State == HAL_TIM_STATE_BUSY))
00421   {
00422      return HAL_BUSY;
00423   }
00424   else if((htim->State == HAL_TIM_STATE_READY))
00425   {
00426     if(((uint32_t)pData == 0U ) && (Length > 0U))
00427     {
00428       return HAL_ERROR;
00429     }
00430     else
00431     {
00432       htim->State = HAL_TIM_STATE_BUSY;
00433     }
00434   }
00435   /* Enable the Input Capture channel 1
00436     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00437   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00438
00439   /* Set the DMA Input Capture 1 Callback */
00440   htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
00441   /* Set the DMA error callback */
00442   htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00443
00444   /* Enable the DMA channel for Capture 1U*/
00445   HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
00446
00447   /* Enable the capture compare 1 Interrupt */
00448   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00449
00450   /* Enable the Peripheral */
00451   __HAL_TIM_ENABLE(htim);
00452
00453   /* Return function status */
00454   return HAL_OK;
00455 }
00456
00457 /**
00458   * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
00459   * @param  htim TIM handle
00460   * @retval HAL status
00461   */
00462 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
00463 {
00464   /* Check the parameters */
00465   assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
00466
00467   /* Disable the Input Capture channel 1
00468     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00469   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00470
00471
00472   /* Disable the capture compare Interrupts 1 event */
00473   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00474
00475   /* Disable the Peripheral */
00476   __HAL_TIM_DISABLE(htim);
00477
00478   /* Return function status */
00479   return HAL_OK;
00480 }
00481
00482 /**
00483   * @}
00484   */
00485
00486 /** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
00487   *  @brief   Timer Complementary Output Compare functions
00488   *
00489 @verbatim
00490   ==============================================================================
00491               ##### Timer Complementary Output Compare functions #####
00492   ==============================================================================
00493   [..]
00494     This section provides functions allowing to:
00495     (+) Start the Complementary Output Compare.
00496     (+) Stop the Complementary Output Compare.
00497     (+) Start the Complementary Output Compare and enable interrupts.
00498     (+) Stop the Complementary Output Compare and disable interrupts.
00499     (+) Start the Complementary Output Compare and enable DMA transfers.
00500     (+) Stop the Complementary Output Compare and disable DMA transfers.
00501
00502 @endverbatim
00503   * @{
00504   */
00505
00506 /**
00507   * @brief  Starts the TIM Output Compare signal generation on the complementary
00508   *         output.
00509   * @param  htim TIM Output Compare handle
00510   * @param  Channel TIM Channel to be enabled
00511   *          This parameter can be one of the following values:
00512   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00513   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00514   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00515   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00516   * @retval HAL status
00517   */
00518 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00519 {
00520   /* Check the parameters */
00521   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00522
00523      /* Enable the Capture compare channel N */
00524      TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00525
00526   /* Enable the Main Ouput */
00527     __HAL_TIM_MOE_ENABLE(htim);
00528
00529   /* Enable the Peripheral */
00530   __HAL_TIM_ENABLE(htim);
00531
00532   /* Return function status */
00533   return HAL_OK;
00534 }
00535
00536 /**
00537   * @brief  Stops the TIM Output Compare signal generation on the complementary
00538   *         output.
00539   * @param  htim TIM handle
00540   * @param  Channel TIM Channel to be disabled
00541   *          This parameter can be one of the following values:
00542   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00543   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00544   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00545   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00546   * @retval HAL status
00547   */
00548 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00549 {
00550   /* Check the parameters */
00551   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00552
00553     /* Disable the Capture compare channel N */
00554   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00555
00556   /* Disable the Main Ouput */
00557     __HAL_TIM_MOE_DISABLE(htim);
00558
00559   /* Disable the Peripheral */
00560   __HAL_TIM_DISABLE(htim);
00561
00562   /* Return function status */
00563   return HAL_OK;
00564 }
00565
00566 /**
00567   * @brief  Starts the TIM Output Compare signal generation in interrupt mode
00568   *         on the complementary output.
00569   * @param  htim TIM OC handle
00570   * @param  Channel TIM Channel to be enabled
00571   *          This parameter can be one of the following values:
00572   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00573   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00574   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00575   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00576   * @retval HAL status
00577   */
00578 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00579 {
00580   /* Check the parameters */
00581   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00582
00583   switch (Channel)
00584   {
00585     case TIM_CHANNEL_1:
00586     {
00587       /* Enable the TIM Output Compare interrupt */
00588       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00589     }
00590     break;
00591
00592     case TIM_CHANNEL_2:
00593     {
00594       /* Enable the TIM Output Compare interrupt */
00595       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00596     }
00597     break;
00598
00599     case TIM_CHANNEL_3:
00600     {
00601       /* Enable the TIM Output Compare interrupt */
00602       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00603     }
00604     break;
00605
00606     case TIM_CHANNEL_4:
00607     {
00608       /* Enable the TIM Output Compare interrupt */
00609       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00610     }
00611     break;
00612
00613     default:
00614     break;
00615   }
00616
00617   /* Enable the TIM Break interrupt */
00618   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
00619
00620   /* Enable the Capture compare channel N */
00621   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00622
00623   /* Enable the Main Ouput */
00624     __HAL_TIM_MOE_ENABLE(htim);
00625
00626   /* Enable the Peripheral */
00627   __HAL_TIM_ENABLE(htim);
00628
00629   /* Return function status */
00630   return HAL_OK;
00631 }
00632
00633 /**
00634   * @brief  Stops the TIM Output Compare signal generation in interrupt mode
00635   *         on the complementary output.
00636   * @param  htim TIM Output Compare handle
00637   * @param  Channel TIM Channel to be disabled
00638   *          This parameter can be one of the following values:
00639   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00640   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00641   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00642   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00643   * @retval HAL status
00644   */
00645 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00646 {
00647   uint32_t tmpccer = 0U;
00648
00649   /* Check the parameters */
00650   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00651
00652   switch (Channel)
00653   {
00654     case TIM_CHANNEL_1:
00655     {
00656       /* Disable the TIM Output Compare interrupt */
00657       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00658     }
00659     break;
00660
00661     case TIM_CHANNEL_2:
00662     {
00663       /* Disable the TIM Output Compare interrupt */
00664       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00665     }
00666     break;
00667
00668     case TIM_CHANNEL_3:
00669     {
00670       /* Disable the TIM Output Compare interrupt */
00671       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00672     }
00673     break;
00674
00675     case TIM_CHANNEL_4:
00676     {
00677       /* Disable the TIM Output Compare interrupt */
00678       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
00679     }
00680     break;
00681
00682     default:
00683     break;
00684   }
00685
00686   /* Disable the Capture compare channel N */
00687   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00688
00689   /* Disable the TIM Break interrupt (only if no more channel is active) */
00690   tmpccer = htim->Instance->CCER;
00691   if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
00692   {
00693     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
00694   }
00695
00696   /* Disable the Main Ouput */
00697   __HAL_TIM_MOE_DISABLE(htim);
00698
00699   /* Disable the Peripheral */
00700   __HAL_TIM_DISABLE(htim);
00701
00702   /* Return function status */
00703   return HAL_OK;
00704 }
00705
00706 /**
00707   * @brief  Starts the TIM Output Compare signal generation in DMA mode
00708   *         on the complementary output.
00709   * @param  htim TIM Output Compare handle
00710   * @param  Channel TIM Channel to be enabled
00711   *          This parameter can be one of the following values:
00712   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00713   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00714   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00715   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00716   * @param  pData The source Buffer address.
00717   * @param  Length The length of data to be transferred from memory to TIM peripheral
00718   * @retval HAL status
00719   */
00720 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00721 {
00722   /* Check the parameters */
00723   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00724
00725   if((htim->State == HAL_TIM_STATE_BUSY))
00726   {
00727      return HAL_BUSY;
00728   }
00729   else if((htim->State == HAL_TIM_STATE_READY))
00730   {
00731     if(((uint32_t)pData == 0U ) && (Length > 0U))
00732     {
00733       return HAL_ERROR;
00734     }
00735     else
00736     {
00737       htim->State = HAL_TIM_STATE_BUSY;
00738     }
00739   }
00740   switch (Channel)
00741   {
00742     case TIM_CHANNEL_1:
00743     {
00744       /* Set the DMA Period elapsed callback */
00745       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
00746
00747       /* Set the DMA error callback */
00748       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00749
00750       /* Enable the DMA channel */
00751       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
00752
00753       /* Enable the TIM Output Compare DMA request */
00754       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00755     }
00756     break;
00757
00758     case TIM_CHANNEL_2:
00759     {
00760       /* Set the DMA Period elapsed callback */
00761       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
00762
00763       /* Set the DMA error callback */
00764       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
00765
00766       /* Enable the DMA channel */
00767       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
00768
00769       /* Enable the TIM Output Compare DMA request */
00770       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00771     }
00772     break;
00773
00774     case TIM_CHANNEL_3:
00775 {
00776       /* Set the DMA Period elapsed callback */
00777       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
00778
00779       /* Set the DMA error callback */
00780       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
00781
00782       /* Enable the DMA channel */
00783       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
00784
00785       /* Enable the TIM Output Compare DMA request */
00786       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
00787     }
00788     break;
00789
00790     case TIM_CHANNEL_4:
00791     {
00792      /* Set the DMA Period elapsed callback */
00793       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
00794
00795       /* Set the DMA error callback */
00796       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
00797
00798       /* Enable the DMA channel */
00799       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
00800
00801       /* Enable the TIM Output Compare DMA request */
00802       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
00803     }
00804     break;
00805
00806     default:
00807     break;
00808   }
00809
00810   /* Enable the Capture compare channel N */
00811   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00812
00813   /* Enable the Main Ouput */
00814   __HAL_TIM_MOE_ENABLE(htim);
00815
00816   /* Enable the Peripheral */
00817   __HAL_TIM_ENABLE(htim);
00818
00819   /* Return function status */
00820   return HAL_OK;
00821 }
00822
00823 /**
00824   * @brief  Stops the TIM Output Compare signal generation in DMA mode
00825   *         on the complementary output.
00826   * @param  htim TIM Output Compare handle
00827   * @param  Channel TIM Channel to be disabled
00828   *          This parameter can be one of the following values:
00829   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00830   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00831   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00832   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00833   * @retval HAL status
00834   */
00835 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
00836 {
00837   /* Check the parameters */
00838   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00839
00840   switch (Channel)
00841   {
00842     case TIM_CHANNEL_1:
00843     {
00844       /* Disable the TIM Output Compare DMA request */
00845       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00846     }
00847     break;
00848
00849     case TIM_CHANNEL_2:
00850     {
00851       /* Disable the TIM Output Compare DMA request */
00852       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
00853     }
00854     break;
00855
00856     case TIM_CHANNEL_3:
00857     {
00858       /* Disable the TIM Output Compare DMA request */
00859       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
00860     }
00861     break;
00862
00863     case TIM_CHANNEL_4:
00864     {
00865       /* Disable the TIM Output Compare interrupt */
00866       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
00867     }
00868     break;
00869
00870     default:
00871     break;
00872   }
00873
00874   /* Disable the Capture compare channel N */
00875   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00876
00877   /* Disable the Main Ouput */
00878   __HAL_TIM_MOE_DISABLE(htim);
00879
00880   /* Disable the Peripheral */
00881   __HAL_TIM_DISABLE(htim);
00882
00883   /* Change the htim state */
00884   htim->State = HAL_TIM_STATE_READY;
00885
00886   /* Return function status */
00887   return HAL_OK;
00888 }
00889
00890 /**
00891   * @}
00892   */
00893
00894 /** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
00895   * @brief    Timer Complementary PWM functions
00896   *
00897 @verbatim
00898   ==============================================================================
00899                  ##### Timer Complementary PWM functions #####
00900   ==============================================================================
00901   [..]
00902     This section provides functions allowing to:
00903     (+) Start the Complementary PWM.
00904     (+) Stop the Complementary PWM.
00905     (+) Start the Complementary PWM and enable interrupts.
00906     (+) Stop the Complementary PWM and disable interrupts.
00907     (+) Start the Complementary PWM and enable DMA transfers.
00908     (+) Stop the Complementary PWM and disable DMA transfers.
00909     (+) Start the Complementary Input Capture measurement.
00910     (+) Stop the Complementary Input Capture.
00911     (+) Start the Complementary Input Capture and enable interrupts.
00912     (+) Stop the Complementary Input Capture and disable interrupts.
00913     (+) Start the Complementary Input Capture and enable DMA transfers.
00914     (+) Stop the Complementary Input Capture and disable DMA transfers.
00915     (+) Start the Complementary One Pulse generation.
00916     (+) Stop the Complementary One Pulse.
00917     (+) Start the Complementary One Pulse and enable interrupts.
00918     (+) Stop the Complementary One Pulse and disable interrupts.
00919
00920 @endverbatim
00921   * @{
00922   */
00923
00924 /**
00925   * @brief  Starts the PWM signal generation on the complementary output.
00926   * @param  htim TIM handle
00927   * @param  Channel TIM Channel to be enabled
00928   *          This parameter can be one of the following values:
00929   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00930   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00931   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00932   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00933   * @retval HAL status
00934   */
00935 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00936 {
00937   /* Check the parameters */
00938   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00939
00940   /* Enable the complementary PWM output  */
00941   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00942
00943   /* Enable the Main Ouput */
00944   __HAL_TIM_MOE_ENABLE(htim);
00945
00946   /* Enable the Peripheral */
00947   __HAL_TIM_ENABLE(htim);
00948
00949   /* Return function status */
00950   return HAL_OK;
00951 }
00952
00953 /**
00954   * @brief  Stops the PWM signal generation on the complementary output.
00955   * @param  htim TIM handle
00956   * @param  Channel TIM Channel to be disabled
00957   *          This parameter can be one of the following values:
00958   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00959   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00960   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00961   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00962   * @retval HAL status
00963   */
00964 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00965 {
00966   /* Check the parameters */
00967   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00968
00969   /* Disable the complementary PWM output  */
00970   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00971
00972   /* Disable the Main Ouput */
00973   __HAL_TIM_MOE_DISABLE(htim);
00974
00975   /* Disable the Peripheral */
00976   __HAL_TIM_DISABLE(htim);
00977
00978   /* Return function status */
00979   return HAL_OK;
00980 }
00981
00982 /**
00983   * @brief  Starts the PWM signal generation in interrupt mode on the
00984   *         complementary output.
00985   * @param  htim TIM handle
00986   * @param  Channel TIM Channel to be disabled
00987   *          This parameter can be one of the following values:
00988   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00989   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00990   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00991   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00992   * @retval HAL status
00993   */
00994 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00995 {
00996   /* Check the parameters */
00997   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00998
00999   switch (Channel)
01000   {
01001     case TIM_CHANNEL_1:
01002     {
01003       /* Enable the TIM Capture/Compare 1 interrupt */
01004       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01005     }
01006     break;
01007
01008     case TIM_CHANNEL_2:
01009     {
01010       /* Enable the TIM Capture/Compare 2 interrupt */
01011       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01012     }
01013     break;
01014
01015     case TIM_CHANNEL_3:
01016     {
01017       /* Enable the TIM Capture/Compare 3 interrupt */
01018       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01019     }
01020     break;
01021
01022     case TIM_CHANNEL_4:
01023     {
01024       /* Enable the TIM Capture/Compare 4 interrupt */
01025       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01026     }
01027     break;
01028
01029     default:
01030     break;
01031   }
01032
01033   /* Enable the TIM Break interrupt */
01034   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
01035
01036   /* Enable the complementary PWM output  */
01037   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01038
01039   /* Enable the Main Ouput */
01040   __HAL_TIM_MOE_ENABLE(htim);
01041
01042   /* Enable the Peripheral */
01043   __HAL_TIM_ENABLE(htim);
01044
01045   /* Return function status */
01046   return HAL_OK;
01047 }
01048
01049 /**
01050   * @brief  Stops the PWM signal generation in interrupt mode on the
01051   *         complementary output.
01052   * @param  htim TIM handle
01053   * @param  Channel TIM Channel to be disabled
01054   *          This parameter can be one of the following values:
01055   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01056   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01057   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01058   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01059   * @retval HAL status
01060   */
01061 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01062 {
01063   uint32_t tmpccer = 0U;
01064
01065   /* Check the parameters */
01066   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01067
01068   switch (Channel)
01069   {
01070     case TIM_CHANNEL_1:
01071     {
01072       /* Disable the TIM Capture/Compare 1 interrupt */
01073       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01074     }
01075     break;
01076
01077     case TIM_CHANNEL_2:
01078     {
01079       /* Disable the TIM Capture/Compare 2 interrupt */
01080       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01081     }
01082     break;
01083
01084     case TIM_CHANNEL_3:
01085     {
01086       /* Disable the TIM Capture/Compare 3 interrupt */
01087       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01088     }
01089     break;
01090
01091     case TIM_CHANNEL_4:
01092     {
01093       /* Disable the TIM Capture/Compare 3 interrupt */
01094       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01095     }
01096     break;
01097
01098     default:
01099     break;
01100   }
01101
01102   /* Disable the complementary PWM output  */
01103   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01104
01105   /* Disable the TIM Break interrupt (only if no more channel is active) */
01106   tmpccer = htim->Instance->CCER;
01107   if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
01108   {
01109     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
01110   }
01111
01112   /* Disable the Main Ouput */
01113   __HAL_TIM_MOE_DISABLE(htim);
01114
01115   /* Disable the Peripheral */
01116   __HAL_TIM_DISABLE(htim);
01117
01118   /* Return function status */
01119   return HAL_OK;
01120 }
01121
01122 /**
01123   * @brief  Starts the TIM PWM signal generation in DMA mode on the
01124   *         complementary output
01125   * @param  htim TIM handle
01126   * @param  Channel TIM Channel to be enabled
01127   *          This parameter can be one of the following values:
01128   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01129   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01130   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01131   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01132   * @param  pData The source Buffer address.
01133   * @param  Length The length of data to be transferred from memory to TIM peripheral
01134   * @retval HAL status
01135   */
01136 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01137 {
01138   /* Check the parameters */
01139   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01140
01141   if((htim->State == HAL_TIM_STATE_BUSY))
01142   {
01143      return HAL_BUSY;
01144   }
01145   else if((htim->State == HAL_TIM_STATE_READY))
01146   {
01147     if(((uint32_t)pData == 0U ) && (Length > 0U))
01148     {
01149       return HAL_ERROR;
01150     }
01151     else
01152     {
01153       htim->State = HAL_TIM_STATE_BUSY;
01154     }
01155   }
01156   switch (Channel)
01157   {
01158     case TIM_CHANNEL_1:
01159     {
01160       /* Set the DMA Period elapsed callback */
01161       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01162
01163       /* Set the DMA error callback */
01164       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01165
01166       /* Enable the DMA channel */
01167       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
01168
01169       /* Enable the TIM Capture/Compare 1 DMA request */
01170       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01171     }
01172     break;
01173
01174     case TIM_CHANNEL_2:
01175     {
01176       /* Set the DMA Period elapsed callback */
01177       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01178
01179       /* Set the DMA error callback */
01180       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01181
01182       /* Enable the DMA channel */
01183       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
01184
01185       /* Enable the TIM Capture/Compare 2 DMA request */
01186       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01187     }
01188     break;
01189
01190     case TIM_CHANNEL_3:
01191     {
01192       /* Set the DMA Period elapsed callback */
01193       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01194
01195       /* Set the DMA error callback */
01196       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01197
01198       /* Enable the DMA channel */
01199       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
01200
01201       /* Enable the TIM Capture/Compare 3 DMA request */
01202       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01203     }
01204     break;
01205
01206     case TIM_CHANNEL_4:
01207     {
01208      /* Set the DMA Period elapsed callback */
01209       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01210
01211       /* Set the DMA error callback */
01212       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01213
01214       /* Enable the DMA channel */
01215       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
01216
01217       /* Enable the TIM Capture/Compare 4 DMA request */
01218       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01219     }
01220     break;
01221
01222     default:
01223     break;
01224   }
01225
01226   /* Enable the complementary PWM output  */
01227   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01228
01229   /* Enable the Main Ouput */
01230   __HAL_TIM_MOE_ENABLE(htim);
01231
01232   /* Enable the Peripheral */
01233   __HAL_TIM_ENABLE(htim);
01234
01235   /* Return function status */
01236   return HAL_OK;
01237 }
01238
01239 /**
01240   * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
01241   *         output
01242   * @param  htim TIM handle
01243   * @param  Channel TIM Channel to be disabled
01244   *          This parameter can be one of the following values:
01245   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01246   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01247   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01248   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01249   * @retval HAL status
01250   */
01251 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01252 {
01253   /* Check the parameters */
01254   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01255
01256   switch (Channel)
01257   {
01258     case TIM_CHANNEL_1:
01259     {
01260       /* Disable the TIM Capture/Compare 1 DMA request */
01261       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01262     }
01263     break;
01264
01265     case TIM_CHANNEL_2:
01266     {
01267       /* Disable the TIM Capture/Compare 2 DMA request */
01268       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01269     }
01270     break;
01271
01272     case TIM_CHANNEL_3:
01273     {
01274       /* Disable the TIM Capture/Compare 3 DMA request */
01275       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01276     }
01277     break;
01278
01279     case TIM_CHANNEL_4:
01280     {
01281       /* Disable the TIM Capture/Compare 4 DMA request */
01282       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01283     }
01284     break;
01285
01286     default:
01287     break;
01288   }
01289
01290   /* Disable the complementary PWM output */
01291   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01292
01293   /* Disable the Main Ouput */
01294   __HAL_TIM_MOE_DISABLE(htim);
01295
01296   /* Disable the Peripheral */
01297   __HAL_TIM_DISABLE(htim);
01298
01299   /* Change the htim state */
01300   htim->State = HAL_TIM_STATE_READY;
01301
01302   /* Return function status */
01303   return HAL_OK;
01304 }
01305
01306 /**
01307   * @}
01308   */
01309
01310 /** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
01311   * @brief    Timer Complementary One Pulse functions
01312   *
01313 @verbatim
01314   ==============================================================================
01315                 ##### Timer Complementary One Pulse functions #####
01316   ==============================================================================
01317   [..]
01318     This section provides functions allowing to:
01319     (+) Start the Complementary One Pulse generation.
01320     (+) Stop the Complementary One Pulse.
01321     (+) Start the Complementary One Pulse and enable interrupts.
01322     (+) Stop the Complementary One Pulse and disable interrupts.
01323
01324 @endverbatim
01325   * @{
01326   */
01327
01328 /**
01329   * @brief  Starts the TIM One Pulse signal generation on the complemetary
01330   *         output.
01331   * @param  htim TIM One Pulse handle
01332   * @param  OutputChannel TIM Channel to be enabled
01333   *          This parameter can be one of the following values:
01334   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01335   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01336   * @retval HAL status
01337   */
01338 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01339   {
01340   /* Check the parameters */
01341   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01342
01343   /* Enable the complementary One Pulse output */
01344   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01345
01346   /* Enable the Main Ouput */
01347   __HAL_TIM_MOE_ENABLE(htim);
01348
01349   /* Return function status */
01350   return HAL_OK;
01351 }
01352
01353 /**
01354   * @brief  Stops the TIM One Pulse signal generation on the complementary
01355   *         output.
01356   * @param  htim TIM One Pulse handle
01357   * @param  OutputChannel TIM Channel to be disabled
01358   *          This parameter can be one of the following values:
01359   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01360   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01361   * @retval HAL status
01362   */
01363 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01364 {
01365
01366   /* Check the parameters */
01367   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01368
01369   /* Disable the complementary One Pulse output */
01370   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01371
01372   /* Disable the Main Ouput */
01373   __HAL_TIM_MOE_DISABLE(htim);
01374
01375   /* Disable the Peripheral */
01376   __HAL_TIM_DISABLE(htim);
01377
01378   /* Return function status */
01379   return HAL_OK;
01380 }
01381
01382 /**
01383   * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
01384   *         complementary channel.
01385   * @param  htim TIM One Pulse handle
01386   * @param  OutputChannel TIM Channel to be enabled
01387   *          This parameter can be one of the following values:
01388   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01389   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01390   * @retval HAL status
01391   */
01392 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01393 {
01394   /* Check the parameters */
01395   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01396
01397   /* Enable the TIM Capture/Compare 1 interrupt */
01398   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01399
01400   /* Enable the TIM Capture/Compare 2 interrupt */
01401   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01402
01403   /* Enable the complementary One Pulse output */
01404   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01405
01406   /* Enable the Main Ouput */
01407   __HAL_TIM_MOE_ENABLE(htim);
01408
01409   /* Return function status */
01410   return HAL_OK;
01411   }
01412
01413 /**
01414   * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
01415   *         complementary channel.
01416   * @param  htim TIM One Pulse handle
01417   * @param  OutputChannel TIM Channel to be disabled
01418   *          This parameter can be one of the following values:
01419   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01420   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01421   * @retval HAL status
01422   */
01423 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01424 {
01425   /* Check the parameters */
01426   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01427
01428   /* Disable the TIM Capture/Compare 1 interrupt */
01429   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01430
01431   /* Disable the TIM Capture/Compare 2 interrupt */
01432   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01433
01434   /* Disable the complementary One Pulse output */
01435   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01436
01437   /* Disable the Main Ouput */
01438   __HAL_TIM_MOE_DISABLE(htim);
01439
01440   /* Disable the Peripheral */
01441   __HAL_TIM_DISABLE(htim);
01442
01443   /* Return function status */
01444   return HAL_OK;
01445 }
01446
01447 /**
01448   * @}
01449   */
01450 /** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
01451   * @brief    Peripheral Control functions
01452   *
01453 @verbatim
01454   ==============================================================================
01455                     ##### Peripheral Control functions #####
01456   ==============================================================================
01457   [..]
01458     This section provides functions allowing to:
01459     (+) Configure the commutation event in case of use of the Hall sensor interface.
01460       (+) Configure Output channels for OC and PWM mode.
01461
01462       (+) Configure Complementary channels, break features and dead time.
01463       (+) Configure Master synchronization.
01464       (+) Configure timer remapping capabilities.
01465       (+) Enable or disable channel grouping
01466
01467 @endverbatim
01468   * @{
01469   */
01470 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
01471     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
01472     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
01473     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01474 /**
01475   * @brief  Configure the TIM commutation event sequence.
01476   * @note this function is mandatory to use the commutation event in order to
01477   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01478   *        the typical use of this feature is with the use of another Timer(interface Timer)
01479   *        configured in Hall sensor interface, this interface Timer will generate the
01480   *        commutation at its TRGO output (connected to Timer used in this function) each time
01481   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01482   * @param  htim TIM handle
01483   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01484   *          This parameter can be one of the following values:
01485   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01486   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01487   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01488   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01489   *            @arg TIM_TS_NONE: No trigger is needed
01490   * @param  CommutationSource the Commutation Event source
01491   *          This parameter can be one of the following values:
01492   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01493   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01494   * @retval HAL status
01495   */
01496 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01497 {
01498   /* Check the parameters */
01499   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01500   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01501
01502   __HAL_LOCK(htim);
01503
01504   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01505       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01506   {
01507     /* Select the Input trigger */
01508     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01509     htim->Instance->SMCR |= InputTrigger;
01510   }
01511
01512   /* Select the Capture Compare preload feature */
01513   htim->Instance->CR2 |= TIM_CR2_CCPC;
01514   /* Select the Commutation event source */
01515   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01516   htim->Instance->CR2 |= CommutationSource;
01517
01518   __HAL_UNLOCK(htim);
01519
01520   return HAL_OK;
01521 }
01522
01523 /**
01524   * @brief  Configure the TIM commutation event sequence with interrupt.
01525   * @note this function is mandatory to use the commutation event in order to
01526   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01527   *        the typical use of this feature is with the use of another Timer(interface Timer)
01528   *        configured in Hall sensor interface, this interface Timer will generate the
01529   *        commutation at its TRGO output (connected to Timer used in this function) each time
01530   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01531   * @param  htim TIM handle
01532   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01533   *          This parameter can be one of the following values:
01534   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01535   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01536   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01537   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01538   *            @arg TIM_TS_NONE: No trigger is needed
01539   * @param  CommutationSource the Commutation Event source
01540   *          This parameter can be one of the following values:
01541   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01542   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01543   * @retval HAL status
01544   */
01545 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01546 {
01547   /* Check the parameters */
01548   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01549   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01550
01551   __HAL_LOCK(htim);
01552
01553   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01554       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01555   {
01556     /* Select the Input trigger */
01557     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01558     htim->Instance->SMCR |= InputTrigger;
01559   }
01560
01561   /* Select the Capture Compare preload feature */
01562   htim->Instance->CR2 |= TIM_CR2_CCPC;
01563   /* Select the Commutation event source */
01564   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01565   htim->Instance->CR2 |= CommutationSource;
01566
01567   /* Enable the Commutation Interrupt Request */
01568   __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
01569
01570   __HAL_UNLOCK(htim);
01571
01572   return HAL_OK;
01573 }
01574
01575 /**
01576   * @brief  Configure the TIM commutation event sequence with DMA.
01577   * @note this function is mandatory to use the commutation event in order to
01578   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01579   *        the typical use of this feature is with the use of another Timer(interface Timer)
01580   *        configured in Hall sensor interface, this interface Timer will generate the
01581   *        commutation at its TRGO output (connected to Timer used in this function) each time
01582   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01583   * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
01584   * @param  htim TIM handle
01585   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01586   *          This parameter can be one of the following values:
01587   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01588   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01589   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01590   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01591   *            @arg TIM_TS_NONE: No trigger is needed
01592   * @param  CommutationSource the Commutation Event source
01593   *          This parameter can be one of the following values:
01594   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01595   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01596   * @retval HAL status
01597   */
01598 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01599 {
01600   /* Check the parameters */
01601   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01602   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01603
01604   __HAL_LOCK(htim);
01605
01606   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01607       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01608   {
01609     /* Select the Input trigger */
01610     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01611     htim->Instance->SMCR |= InputTrigger;
01612   }
01613
01614   /* Select the Capture Compare preload feature */
01615   htim->Instance->CR2 |= TIM_CR2_CCPC;
01616   /* Select the Commutation event source */
01617   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01618   htim->Instance->CR2 |= CommutationSource;
01619
01620   /* Enable the Commutation DMA Request */
01621   /* Set the DMA Commutation Callback */
01622   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
01623   /* Set the DMA error callback */
01624   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
01625
01626   /* Enable the Commutation DMA Request */
01627   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
01628
01629   __HAL_UNLOCK(htim);
01630
01631   return HAL_OK;
01632 }
01633
01634 /**
01635   * @brief  Initializes the TIM Output Compare Channels according to the specified
01636   *         parameters in the TIM_OC_InitTypeDef.
01637   * @param  htim TIM Output Compare handle
01638   * @param  sConfig TIM Output Compare configuration structure
01639   * @param  Channel TIM Channels to configure
01640   *          This parameter can be one of the following values:
01641   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01642   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01643   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01644   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01645   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01646   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01647   * @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
01648   *       STM32F398xx and STM32F303x8 up to 6 OC channels can be configured
01649   * @retval HAL status
01650   */
01651 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
01652                                            TIM_OC_InitTypeDef* sConfig,
01653                                            uint32_t Channel)
01654 {
01655   /* Check the parameters */
01656   assert_param(IS_TIM_CHANNELS(Channel));
01657   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
01658   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
01659
01660   /* Check input state */
01661   __HAL_LOCK(htim);
01662
01663   htim->State = HAL_TIM_STATE_BUSY;
01664
01665   switch (Channel)
01666   {
01667     case TIM_CHANNEL_1:
01668     {
01669       /* Check the parameters */
01670       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
01671
01672      /* Configure the TIM Channel 1 in Output Compare */
01673       TIM_OC1_SetConfig(htim->Instance, sConfig);
01674     }
01675     break;
01676
01677     case TIM_CHANNEL_2:
01678     {
01679       /* Check the parameters */
01680       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
01681
01682       /* Configure the TIM Channel 2 in Output Compare */
01683       TIM_OC2_SetConfig(htim->Instance, sConfig);
01684     }
01685     break;
01686
01687     case TIM_CHANNEL_3:
01688     {
01689       /* Check the parameters */
01690       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
01691
01692       /* Configure the TIM Channel 3 in Output Compare */
01693       TIM_OC3_SetConfig(htim->Instance, sConfig);
01694     }
01695     break;
01696
01697     case TIM_CHANNEL_4:
01698     {
01699       /* Check the parameters */
01700       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
01701
01702        /* Configure the TIM Channel 4 in Output Compare */
01703        TIM_OC4_SetConfig(htim->Instance, sConfig);
01704     }
01705     break;
01706
01707     case TIM_CHANNEL_5:
01708     {
01709       /* Check the parameters */
01710       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
01711
01712        /* Configure the TIM Channel 5 in Output Compare */
01713        TIM_OC5_SetConfig(htim->Instance, sConfig);
01714     }
01715     break;
01716
01717     case TIM_CHANNEL_6:
01718     {
01719       /* Check the parameters */
01720       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
01721
01722        /* Configure the TIM Channel 6 in Output Compare */
01723        TIM_OC6_SetConfig(htim->Instance, sConfig);
01724     }
01725     break;
01726
01727     default:
01728     break;
01729   }
01730
01731   htim->State = HAL_TIM_STATE_READY;
01732
01733   __HAL_UNLOCK(htim);
01734
01735   return HAL_OK;
01736 }
01737
01738 /**
01739   * @brief  Initializes the TIM PWM  channels according to the specified
01740   *         parameters in the TIM_OC_InitTypeDef.
01741   * @param  htim TIM PWM handle
01742   * @param  sConfig TIM PWM configuration structure
01743   * @param  Channel TIM Channels to be configured
01744   *          This parameter can be one of the following values:
01745   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01746   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01747   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01748   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01749   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01750   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01751   * @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
01752   *       STM32F398xx and STM32F303x8 up to 6 PWM channels can be configured
01753   * @retval HAL status
01754   */
01755 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
01756                                             TIM_OC_InitTypeDef* sConfig,
01757                                             uint32_t Channel)
01758 {
01759   /* Check the parameters */
01760   assert_param(IS_TIM_CHANNELS(Channel));
01761   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
01762   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
01763   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
01764
01765   /* Check input state */
01766   __HAL_LOCK(htim);
01767
01768   htim->State = HAL_TIM_STATE_BUSY;
01769
01770   switch (Channel)
01771   {
01772     case TIM_CHANNEL_1:
01773     {
01774       /* Check the parameters */
01775       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
01776
01777       /* Configure the Channel 1 in PWM mode */
01778       TIM_OC1_SetConfig(htim->Instance, sConfig);
01779
01780       /* Set the Preload enable bit for channel1 */
01781       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
01782
01783       /* Configure the Output Fast mode */
01784       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
01785       htim->Instance->CCMR1 |= sConfig->OCFastMode;
01786     }
01787     break;
01788
01789     case TIM_CHANNEL_2:
01790     {
01791       /* Check the parameters */
01792       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
01793
01794       /* Configure the Channel 2 in PWM mode */
01795       TIM_OC2_SetConfig(htim->Instance, sConfig);
01796
01797       /* Set the Preload enable bit for channel2 */
01798       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
01799
01800       /* Configure the Output Fast mode */
01801       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
01802       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
01803     }
01804     break;
01805
01806     case TIM_CHANNEL_3:
01807     {
01808       /* Check the parameters */
01809       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
01810
01811       /* Configure the Channel 3 in PWM mode */
01812       TIM_OC3_SetConfig(htim->Instance, sConfig);
01813
01814       /* Set the Preload enable bit for channel3 */
01815       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
01816
01817      /* Configure the Output Fast mode */
01818       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
01819       htim->Instance->CCMR2 |= sConfig->OCFastMode;
01820     }
01821     break;
01822
01823     case TIM_CHANNEL_4:
01824     {
01825       /* Check the parameters */
01826       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
01827
01828       /* Configure the Channel 4 in PWM mode */
01829       TIM_OC4_SetConfig(htim->Instance, sConfig);
01830
01831       /* Set the Preload enable bit for channel4 */
01832       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
01833
01834      /* Configure the Output Fast mode */
01835       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
01836       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
01837     }
01838     break;
01839
01840     case TIM_CHANNEL_5:
01841     {
01842        /* Check the parameters */
01843       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
01844
01845      /* Configure the Channel 5 in PWM mode */
01846       TIM_OC5_SetConfig(htim->Instance, sConfig);
01847
01848       /* Set the Preload enable bit for channel5*/
01849       htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
01850
01851      /* Configure the Output Fast mode */
01852       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
01853       htim->Instance->CCMR3 |= sConfig->OCFastMode;
01854     }
01855     break;
01856
01857     case TIM_CHANNEL_6:
01858     {
01859        /* Check the parameters */
01860       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
01861
01862      /* Configure the Channel 5 in PWM mode */
01863       TIM_OC6_SetConfig(htim->Instance, sConfig);
01864
01865       /* Set the Preload enable bit for channel6 */
01866       htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
01867
01868      /* Configure the Output Fast mode */
01869       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
01870       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
01871     }
01872     break;
01873
01874     default:
01875     break;
01876   }
01877
01878   htim->State = HAL_TIM_STATE_READY;
01879
01880   __HAL_UNLOCK(htim);
01881
01882   return HAL_OK;
01883 }
01884
01885
01886 /**
01887   * @brief  Configures the TIM in master mode.
01888   * @param  htim TIM handle.
01889   * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
01890   *         contains the selected trigger output (TRGO) and the Master/Slave
01891   *         mode.
01892   * @retval HAL status
01893   */
01894 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
01895                                                       TIM_MasterConfigTypeDef * sMasterConfig)
01896 {
01897   uint32_t tmpcr2;
01898   uint32_t tmpsmcr;
01899
01900   /* Check the parameters */
01901   assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
01902   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
01903   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
01904
01905   /* Check input state */
01906   __HAL_LOCK(htim);
01907
01908  /* Get the TIMx CR2 register value */
01909   tmpcr2 = htim->Instance->CR2;
01910
01911   /* Get the TIMx SMCR register value */
01912   tmpsmcr = htim->Instance->SMCR;
01913
01914   /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2U */
01915   if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
01916   {
01917     /* Check the parameters */
01918     assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
01919
01920     /* Clear the MMS2 bits */
01921     tmpcr2 &= ~TIM_CR2_MMS2;
01922     /* Select the TRGO2 source*/
01923     tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
01924   }
01925
01926   /* Reset the MMS Bits */
01927   tmpcr2 &= ~TIM_CR2_MMS;
01928   /* Select the TRGO source */
01929   tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
01930
01931   /* Reset the MSM Bit */
01932   tmpsmcr &= ~TIM_SMCR_MSM;
01933   /* Set master mode */
01934   tmpsmcr |= sMasterConfig->MasterSlaveMode;
01935
01936   /* Update TIMx CR2 */
01937   htim->Instance->CR2 = tmpcr2;
01938
01939   /* Update TIMx SMCR */
01940   htim->Instance->SMCR = tmpsmcr;
01941
01942   __HAL_UNLOCK(htim);
01943
01944   return HAL_OK;
01945 }
01946 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
01947        /* STM32F302xC || STM32F303xC || STM32F358xx || */
01948        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
01949        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
01950
01951 #if defined(STM32F373xC) || defined(STM32F378xx)
01952 /**
01953   * @brief  Configures the TIM in master mode.
01954   * @param  htim TIM handle.
01955   * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
01956   *         contains the selected trigger output (TRGO) and the Master/Slave
01957   *         mode.
01958   * @retval HAL status
01959   */
01960 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
01961 {
01962   /* Check the parameters */
01963   assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
01964   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
01965   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
01966
01967   __HAL_LOCK(htim);
01968
01969   htim->State = HAL_TIM_STATE_BUSY;
01970
01971   /* Reset the MMS Bits */
01972   htim->Instance->CR2 &= ~TIM_CR2_MMS;
01973   /* Select the TRGO source */
01974   htim->Instance->CR2 |=  sMasterConfig->MasterOutputTrigger;
01975
01976   /* Reset the MSM Bit */
01977   htim->Instance->SMCR &= ~TIM_SMCR_MSM;
01978   /* Set or Reset the MSM Bit */
01979   htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
01980
01981   htim->State = HAL_TIM_STATE_READY;
01982
01983   __HAL_UNLOCK(htim);
01984
01985   return HAL_OK;
01986 }
01987 #endif /* STM32F373xC || STM32F378xx */
01988
01989 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
01990     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
01991     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
01992     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01993 /**
01994   * @brief   Configures the Break feature, dead time, Lock level, OSSI/OSSR State
01995   *         and the AOE(automatic output enable).
01996   * @param  htim TIM handle
01997   * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef
01998             structure that contains the BDTR Register configuration information
01999             for the TIM peripheral.
02000   * @note   For STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE,
02001             STM32F398xx and STM32F303x8 two break inputs can be configured.
02002   * @retval HAL status
02003   */
02004 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
02005                                                 TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
02006 {
02007   uint32_t tmpbdtr = 0U;
02008
02009   /* Check the parameters */
02010   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
02011   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
02012   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
02013   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
02014   assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
02015   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
02016   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
02017   assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
02018   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
02019
02020   /* Check input state */
02021   __HAL_LOCK(htim);
02022
02023   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
02024   the OSSI State, the dead time value and the Automatic Output Enable Bit */
02025
02026   /* Set the BDTR bits */
02027   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
02028   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
02029   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
02030   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
02031   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
02032   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
02033   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
02034   MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
02035   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT));
02036
02037   if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
02038   {
02039     assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
02040     assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
02041     assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
02042
02043     /* Set the BREAK2 input related BDTR bits */
02044     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT));
02045     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
02046     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
02047   }
02048
02049   /* Set TIMx_BDTR */
02050   htim->Instance->BDTR = tmpbdtr;
02051
02052   __HAL_UNLOCK(htim);
02053
02054   return HAL_OK;
02055 }
02056 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02057        /* STM32F302xC || STM32F303xC || STM32F358xx || */
02058        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02059        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
02060
02061 #if defined(STM32F373xC) || defined(STM32F378xx)
02062 /**
02063   * @brief   Configures the Break feature, dead time, Lock level, OSSI/OSSR State
02064   *          and the AOE(automatic output enable).
02065   * @param  htim TIM handle
02066   * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
02067   *         contains the BDTR Register configuration  information for the TIM peripheral.
02068   * @retval HAL status
02069   */
02070 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
02071                                                 TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
02072 {
02073   uint32_t tmpbdtr = 0U;
02074
02075   /* Check the parameters */
02076   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
02077   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
02078   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
02079   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
02080   assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
02081   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
02082   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
02083   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
02084
02085   /* Process Locked */
02086   __HAL_LOCK(htim);
02087
02088   htim->State = HAL_TIM_STATE_BUSY;
02089
02090   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
02091      the OSSI State, the dead time value and the Automatic Output Enable Bit */
02092
02093   /* Set the BDTR bits */
02094   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
02095   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
02096   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
02097   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
02098   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
02099   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
02100   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
02101   MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
02102
02103   /* Set TIMx_BDTR */
02104   htim->Instance->BDTR = tmpbdtr;
02105
02106   htim->State = HAL_TIM_STATE_READY;
02107
02108   __HAL_UNLOCK(htim);
02109
02110   return HAL_OK;
02111 }
02112 #endif /* STM32F373xC || STM32F378xx */
02113
02114 #if defined(STM32F303xE) || defined(STM32F398xx) || \
02115     defined(STM32F303xC) || defined(STM32F358xx) || \
02116         defined(STM32F334x8)
02117 #if defined(STM32F303xE) || defined(STM32F398xx)
02118 /**
02119   * @brief  Configures the TIM1, TIM8, TIM16 and TIM20 Remapping input capabilities.
02120   * @param  htim TIM handle.
02121   * @param  Remap1: specifies the first TIM remapping source.
02122   *          This parameter can be one of the following values:
02123   *            @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
02124   *            @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
02125   *            @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
02126   *            @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
02127   *            @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD
02128   *            @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
02129   *            @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
02130   *            @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
02131   *            @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
02132   *            @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
02133   *            @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
02134   *            @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
02135   *            @arg TIM_TIM20_ADC3_NONE: TIM20_ETR is not connected to any AWD (analog watchdog)
02136   *            @arg TIM_TIM20_ADC3_AWD1: TIM20_ETR is connected to ADC3 AWD1
02137   *            @arg TIM_TIM20_ADC3_AWD2: TIM20_ETR is connected to ADC3 AWD2
02138   *            @arg TIM_TIM20_ADC3_AWD3: TIM20_ETR is connected to ADC3 AWD3
02139   * @param  Remap2: specifies the  second TIMremapping source (if any).
02140   *          This parameter can be one of the following values:
02141   *            @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any ADC4 AWD (analog watchdog)
02142   *            @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
02143   *            @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
02144   *            @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
02145   *            @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD
02146   *            @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
02147   *            @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
02148   *            @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
02149   *            @arg TIM_TIM16_NONE: Non significant value for TIM16
02150   *            @arg TIM_TIM20_ADC4_NONE: TIM20_ETR is not connected to any ADC4 AWD
02151   *            @arg TIM_TIM20_ADC4_AWD1: TIM20_ETR is connected to ADC4 AWD1
02152   *            @arg TIM_TIM20_ADC4_AWD2: TIM20_ETR is connected to ADC4 AWD2
02153   *            @arg TIM_TIM20_ADC4_AWD3: TIM20_ETR is connected to ADC4 AWD3
02154   * @retval HAL status
02155   */
02156 #elif defined(STM32F303xC) || defined(STM32F358xx)
02157 /**
02158   * @brief  Configures the TIM1, TIM8 and TIM16 Remapping input capabilities.
02159   * @param  htim TIM handle.
02160   * @param  Remap1: specifies the first TIM remapping source.
02161   *          This parameter can be one of the following values:
02162   *            @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
02163   *            @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
02164   *            @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
02165   *            @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
02166   *            @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any AWD
02167   *            @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
02168   *            @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
02169   *            @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
02170   *            @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
02171   *            @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
02172   *            @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
02173   *            @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
02174   * @param  Remap2: specifies the  second TIMremapping source (if any).
02175   *          This parameter can be one of the following values:
02176   *            @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
02177   *            @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
02178   *            @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
02179   *            @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
02180   *            @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any AWD
02181   *            @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
02182   *            @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
02183   *            @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
02184   * @retval HAL status
02185   */
02186 #else /* STM32F334x8 */
02187 /**
02188   * @brief  Configures the TIM1, TIM8 and TIM16 Remapping input capabilities.
02189   * @param  htim TIM handle.
02190   * @param  Remap1: specifies the first TIM remapping source.
02191   *          This parameter can be one of the following values:
02192   *            @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
02193   *            @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
02194   *            @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
02195   *            @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
02196   *            @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
02197   *            @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
02198   *            @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
02199   *            @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
02200   * @param  Remap2: specifies the  second TIMremapping source (if any).
02201   *          This parameter can be one of the following values:
02202   *            @arg TIM_TIM1_ADC2_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
02203   *            @arg TIM_TIM1_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1
02204   *            @arg TIM_TIM1_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2
02205   *            @arg TIM_TIM1_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD3
02206   * @retval HAL status
02207   */
02208 #endif /* STM32F303xE || STM32F398xx || */
02209 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2)
02210 {
02211   __HAL_LOCK(htim);
02212
02213   /* Check parameters */
02214   assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
02215   assert_param(IS_TIM_REMAP(Remap1));
02216   assert_param(IS_TIM_REMAP2(Remap2));
02217
02218   /* Set the Timer remapping configuration */
02219   htim->Instance->OR = Remap1 | Remap2;
02220
02221   htim->State = HAL_TIM_STATE_READY;
02222
02223   __HAL_UNLOCK(htim);
02224
02225   return HAL_OK;
02226 }
02227 #endif /* STM32F303xE || STM32F398xx || */
02228        /* STM32F303xC || STM32F358xx || STM32F334x8 */
02229
02230
02231 #if defined(STM32F302xE)                                                 || \
02232     defined(STM32F302xC)                                                 || \
02233     defined(STM32F303x8) || defined(STM32F328xx) || \
02234     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
02235     defined(STM32F373xC) || defined(STM32F378xx)
02236 #if defined(STM32F302xE)                                                 || \
02237     defined(STM32F302xC)                                                 || \
02238     defined(STM32F303x8) || defined(STM32F328xx) || \
02239     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02240 /**
02241   * @brief  Configures the TIM1 and TIM16 Remapping input capabilities.
02242   * @param  htim TIM handle.
02243   * @param  Remap specifies the TIM remapping source.
02244   *          This parameter can be one of the following values:
02245   *            @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
02246   *            @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
02247   *            @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
02248   *            @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
02249   *            @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
02250   *            @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC_clock
02251   *            @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
02252   *            @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
02253   * @retval HAL status
02254   */
02255 #else /* STM32F373xC || STM32F378xx */
02256 /**
02257   * @brief  Configures the TIM2 and TIM14 Remapping input capabilities.
02258   * @param  htim TIM handle.
02259   * @param  Remap specifies the TIM remapping source.
02260   *          This parameter can be one of the following values:
02261   *          STM32F373xC, STM32F378xx:
02262   *            @arg TIM_TIM2_TIM8_TRGO: TIM8 TRGOUT is connected to TIM2_ITR1
02263   *            @arg TIM_TIM2_ETH_PTP: PTP trigger output is connected to TIM2_ITR1
02264   *            @arg TIM_TIM2_USBFS_SOF: OTG FS SOF is connected to the TIM2_ITR1 input
02265   *            @arg TIM_TIM2_USBHS_SOF: OTG HS SOF is connected to the TIM2_ITR1 input
02266   *            @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
02267   *            @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
02268   *            @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
02269   *            @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
02270   * @retval HAL status
02271   */
02272 #endif /* STM32F302xE                               || */
02273        /* STM32F302xC                               || */
02274        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02275        /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
02276 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
02277 {
02278   __HAL_LOCK(htim);
02279
02280   /* Check parameters */
02281   assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
02282   assert_param(IS_TIM_REMAP(Remap));
02283
02284   /* Set the Timer remapping configuration */
02285   htim->Instance->OR = Remap;
02286
02287   htim->State = HAL_TIM_STATE_READY;
02288
02289   __HAL_UNLOCK(htim);
02290
02291   return HAL_OK;
02292 }
02293 #endif /* STM32F302xE                               || */
02294        /* STM32F302xC                               || */
02295        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02296        /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
02297        /* STM32F373xC || STM32F378xx                   */
02298
02299
02300 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
02301     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
02302     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
02303     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02304 /**
02305   * @brief  Group channel 5 and channel 1, 2 or 3
02306   * @param  htim TIM handle.
02307   * @param  Channels specifies the reference signal(s) the OC5REF is combined with.
02308   *         This parameter can be any combination of the following values:
02309   *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
02310   *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
02311   *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
02312   *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
02313   * @retval HAL status
02314   */
02315 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
02316 {
02317   /* Check parameters */
02318   assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
02319   assert_param(IS_TIM_GROUPCH5(Channels));
02320
02321   /* Process Locked */
02322   __HAL_LOCK(htim);
02323
02324   htim->State = HAL_TIM_STATE_BUSY;
02325
02326   /* Clear GC5Cx bit fields */
02327   htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
02328
02329   /* Set GC5Cx bit fields */
02330   htim->Instance->CCR5 |= Channels;
02331
02332   htim->State = HAL_TIM_STATE_READY;
02333
02334   __HAL_UNLOCK(htim);
02335
02336   return HAL_OK;
02337 }
02338 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02339        /* STM32F302xC || STM32F303xC || STM32F358xx || */
02340        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02341        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
02342
02343 /**
02344   * @}
02345   */
02346
02347 /** @addtogroup TIM_Exported_Functions_Group8
02348   * @{
02349   */
02350 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
02351     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
02352     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
02353     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02354 /**
02355   * @brief  Configures the OCRef clear feature
02356   * @param  htim TIM handle
02357   * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
02358   *         contains the OCREF clear feature and parameters for the TIM peripheral.
02359   * @param  Channel specifies the TIM Channel
02360   *          This parameter can be one of the following values:
02361   *            @arg TIM_CHANNEL_1: TIM Channel 1
02362   *            @arg TIM_CHANNEL_2: TIM Channel 2
02363   *            @arg TIM_CHANNEL_3: TIM Channel 3
02364   *            @arg TIM_CHANNEL_4: TIM Channel 4
02365   *            @arg TIM_Channel_5: TIM Channel 5
02366   *            @arg TIM_Channel_6: TIM Channel 6
02367   * @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
02368   *       STM32F398xx and STM32F303x8 up to 6 OC channels can be configured
02369   * @retval None
02370   */
02371 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
02372                                            TIM_ClearInputConfigTypeDef *sClearInputConfig,
02373                                            uint32_t Channel)
02374 {
02375   uint32_t tmpsmcr = 0U;
02376
02377   /* Check the parameters */
02378   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
02379   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
02380
02381   /* Check input state */
02382   __HAL_LOCK(htim);
02383
02384   htim->State = HAL_TIM_STATE_BUSY;
02385
02386   switch (sClearInputConfig->ClearInputSource)
02387   {
02388     case TIM_CLEARINPUTSOURCE_NONE:
02389     {
02390       /* Get the TIMx SMCR register value */
02391       tmpsmcr = htim->Instance->SMCR;
02392
02393       /* Clear the OCREF clear selection bit */
02394       tmpsmcr &= ~TIM_SMCR_OCCS;
02395
02396       /* Clear the ETR Bits */
02397       tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
02398
02399       /* Set TIMx_SMCR */
02400       htim->Instance->SMCR = tmpsmcr;
02401    }
02402     break;
02403
02404     case TIM_CLEARINPUTSOURCE_OCREFCLR:
02405     {
02406       /* Clear the OCREF clear selection bit */
02407       htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
02408     }
02409     break;
02410
02411     case TIM_CLEARINPUTSOURCE_ETR:
02412     {
02413       /* Check the parameters */
02414       assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
02415       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
02416       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
02417
02418       TIM_ETR_SetConfig(htim->Instance,
02419                         sClearInputConfig->ClearInputPrescaler,
02420                         sClearInputConfig->ClearInputPolarity,
02421                         sClearInputConfig->ClearInputFilter);
02422
02423       /* Set the OCREF clear selection bit */
02424       htim->Instance->SMCR |= TIM_SMCR_OCCS;
02425     }
02426     break;
02427     default:
02428     break;
02429   }
02430
02431   switch (Channel)
02432   {
02433     case TIM_CHANNEL_1:
02434       {
02435         if(sClearInputConfig->ClearInputState != RESET)
02436         {
02437           /* Enable the Ocref clear feature for Channel 1U */
02438           htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
02439         }
02440         else
02441         {
02442           /* Disable the Ocref clear feature for Channel 1U */
02443           htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
02444         }
02445       }
02446       break;
02447     case TIM_CHANNEL_2:
02448       {
02449         if(sClearInputConfig->ClearInputState != RESET)
02450         {
02451           /* Enable the Ocref clear feature for Channel 2U */
02452           htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
02453         }
02454         else
02455         {
02456           /* Disable the Ocref clear feature for Channel 2U */
02457           htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
02458         }
02459       }
02460     break;
02461     case TIM_CHANNEL_3:
02462       {
02463         if(sClearInputConfig->ClearInputState != RESET)
02464         {
02465           /* Enable the Ocref clear feature for Channel 3U */
02466           htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
02467         }
02468         else
02469         {
02470           /* Disable the Ocref clear feature for Channel 3U */
02471           htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
02472         }
02473       }
02474     break;
02475     case TIM_CHANNEL_4:
02476       {
02477         if(sClearInputConfig->ClearInputState != RESET)
02478         {
02479           /* Enable the Ocref clear feature for Channel 4U */
02480           htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
02481         }
02482         else
02483         {
02484           /* Disable the Ocref clear feature for Channel 4U */
02485           htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
02486         }
02487       }
02488     break;
02489     case TIM_CHANNEL_5:
02490       {
02491         if(sClearInputConfig->ClearInputState != RESET)
02492         {
02493           /* Enable the Ocref clear feature for Channel 1U */
02494           htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
02495         }
02496         else
02497         {
02498           /* Disable the Ocref clear feature for Channel 1U */
02499           htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
02500         }
02501       }
02502     break;
02503     case TIM_CHANNEL_6:
02504       {
02505         if(sClearInputConfig->ClearInputState != RESET)
02506         {
02507           /* Enable the Ocref clear feature for Channel 1U */
02508           htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
02509         }
02510         else
02511         {
02512           /* Disable the Ocref clear feature for Channel 1U */
02513           htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
02514         }
02515       }
02516     break;
02517     default:
02518     break;
02519   }
02520
02521   htim->State = HAL_TIM_STATE_READY;
02522
02523   __HAL_UNLOCK(htim);
02524
02525   return HAL_OK;
02526 }
02527 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02528        /* STM32F302xC || STM32F303xC || STM32F358xx || */
02529        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02530        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
02531 /**
02532   * @}
02533   */
02534
02535 /** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
02536  *  @brief   Extension Callbacks functions
02537   *
02538 @verbatim
02539   ==============================================================================
02540                     ##### Extended Callbacks functions #####
02541   ==============================================================================
02542   [..]
02543     This section provides Extended TIM callback functions:
02544     (+) Timer Commutation callback
02545     (+) Timer Break callback
02546
02547 @endverbatim
02548   * @{
02549   */
02550
02551 /**
02552   * @brief  Hall commutation changed callback in non blocking mode
02553   * @param  htim TIM handle
02554   * @retval None
02555   */
02556 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
02557 {
02558   /* Prevent unused argument(s) compilation warning */
02559   UNUSED(htim);
02560
02561   /* NOTE : This function Should not be modified, when the callback is needed,
02562             the HAL_TIMEx_CommutationCallback could be implemented in the user file
02563    */
02564 }
02565
02566 /**
02567   * @brief  Hall Break detection callback in non blocking mode
02568   * @param  htim TIM handle
02569   * @retval None
02570   */
02571 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
02572 {
02573   /* Prevent unused argument(s) compilation warning */
02574   UNUSED(htim);
02575
02576   /* NOTE : This function Should not be modified, when the callback is needed,
02577             the HAL_TIMEx_BreakCallback could be implemented in the user file
02578    */
02579 }
02580
02581 /**
02582   * @brief  Hall Break2 detection callback in non blocking mode
02583   * @param  htim: TIM handle
02584   * @retval None
02585   */
02586 __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
02587 {
02588   /* Prevent unused argument(s) compilation warning */
02589   UNUSED(htim);
02590
02591   /* NOTE : This function Should not be modified, when the callback is needed,
02592             the HAL_TIMEx_Break2Callback could be implemented in the user file
02593    */
02594 }
02595
02596 /**
02597   * @}
02598   */
02599
02600 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
02601   * @brief    Extended Peripheral State functions
02602   *
02603 @verbatim
02604   ==============================================================================
02605                 ##### Extended Peripheral State functions #####
02606   ==============================================================================
02607   [..]
02608     This subsection permit to get in run-time the status of the peripheral
02609     and the data flow.
02610
02611 @endverbatim
02612   * @{
02613   */
02614
02615 /**
02616   * @brief  Return the TIM Hall Sensor interface state
02617   * @param  htim TIM Hall Sensor handle
02618   * @retval HAL state
02619   */
02620 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
02621 {
02622   return htim->State;
02623 }
02624
02625 /**
02626   * @}
02627   */
02628
02629 /**
02630   * @}
02631   */
02632
02633 /** @addtogroup TIMEx_Private_Functions
02634   * @{
02635   */
02636 /**
02637   * @brief  TIM DMA Commutation callback.
02638   * @param  hdma pointer to DMA handle.
02639   * @retval None
02640   */
02641 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
02642 {
02643   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02644
02645   htim->State= HAL_TIM_STATE_READY;
02646
02647   HAL_TIMEx_CommutationCallback(htim);
02648 }
02649
02650 /**
02651   * @brief  Enables or disables the TIM Capture Compare Channel xN.
02652   * @param  TIMx to select the TIM peripheral
02653   * @param  Channel specifies the TIM Channel
02654   *          This parameter can be one of the following values:
02655   *            @arg TIM_CHANNEL_1: TIM Channel 1
02656   *            @arg TIM_CHANNEL_2: TIM Channel 2
02657   *            @arg TIM_CHANNEL_3: TIM Channel 3
02658   * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
02659   *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
02660   * @retval None
02661   */
02662 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
02663 {
02664   uint32_t tmp = 0U;
02665
02666   tmp = TIM_CCER_CC1NE << Channel;
02667
02668   /* Reset the CCxNE Bit */
02669   TIMx->CCER &=  ~tmp;
02670
02671   /* Set or reset the CCxNE Bit */
02672   TIMx->CCER |=  (uint32_t)(ChannelNState << Channel);
02673 }
02674
02675 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
02676     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
02677     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
02678     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
02679 /**
02680   * @brief  Timer Ouput Compare 5 configuration
02681   * @param  TIMx to select the TIM peripheral
02682   * @param  OC_Config The ouput configuration structure
02683   * @retval None
02684   */
02685 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
02686                               TIM_OC_InitTypeDef *OC_Config)
02687 {
02688   uint32_t tmpccmrx = 0U;
02689   uint32_t tmpccer = 0U;
02690   uint32_t tmpcr2 = 0U;
02691
02692   /* Disable the output: Reset the CCxE Bit */
02693   TIMx->CCER &= ~TIM_CCER_CC5E;
02694
02695   /* Get the TIMx CCER register value */
02696   tmpccer = TIMx->CCER;
02697   /* Get the TIMx CR2 register value */
02698   tmpcr2 =  TIMx->CR2;
02699   /* Get the TIMx CCMR1 register value */
02700   tmpccmrx = TIMx->CCMR3;
02701
02702   /* Reset the Output Compare Mode Bits */
02703   tmpccmrx &= ~(TIM_CCMR3_OC5M);
02704   /* Select the Output Compare Mode */
02705   tmpccmrx |= OC_Config->OCMode;
02706
02707   /* Reset the Output Polarity level */
02708   tmpccer &= ~TIM_CCER_CC5P;
02709   /* Set the Output Compare Polarity */
02710   tmpccer |= (OC_Config->OCPolarity << 16U);
02711
02712   if(IS_TIM_BREAK_INSTANCE(TIMx))
02713   {
02714     /* Reset the Output Compare IDLE State */
02715     tmpcr2 &= ~TIM_CR2_OIS5;
02716     /* Set the Output Idle state */
02717     tmpcr2 |= (OC_Config->OCIdleState << 8U);
02718   }
02719   /* Write to TIMx CR2 */
02720   TIMx->CR2 = tmpcr2;
02721
02722   /* Write to TIMx CCMR3 */
02723   TIMx->CCMR3 = tmpccmrx;
02724
02725   /* Set the Capture Compare Register value */
02726   TIMx->CCR5 = OC_Config->Pulse;
02727
02728   /* Write to TIMx CCER */
02729   TIMx->CCER = tmpccer;
02730 }
02731
02732 /**
02733   * @brief  Timer Ouput Compare 6 configuration
02734   * @param  TIMx to select the TIM peripheral
02735   * @param  OC_Config The ouput configuration structure
02736   * @retval None
02737   */
02738 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
02739                               TIM_OC_InitTypeDef *OC_Config)
02740 {
02741   uint32_t tmpccmrx = 0U;
02742   uint32_t tmpccer = 0U;
02743   uint32_t tmpcr2 = 0U;
02744
02745   /* Disable the output: Reset the CCxE Bit */
02746   TIMx->CCER &= ~TIM_CCER_CC6E;
02747
02748   /* Get the TIMx CCER register value */
02749   tmpccer = TIMx->CCER;
02750   /* Get the TIMx CR2 register value */
02751   tmpcr2 =  TIMx->CR2;
02752   /* Get the TIMx CCMR1 register value */
02753   tmpccmrx = TIMx->CCMR3;
02754
02755   /* Reset the Output Compare Mode Bits */
02756   tmpccmrx &= ~(TIM_CCMR3_OC6M);
02757   /* Select the Output Compare Mode */
02758   tmpccmrx |= (OC_Config->OCMode << 8U);
02759
02760   /* Reset the Output Polarity level */
02761   tmpccer &= (uint32_t)~TIM_CCER_CC6P;
02762   /* Set the Output Compare Polarity */
02763   tmpccer |= (OC_Config->OCPolarity << 20U);
02764
02765   if(IS_TIM_BREAK_INSTANCE(TIMx))
02766   {
02767     /* Reset the Output Compare IDLE State */
02768     tmpcr2 &= ~TIM_CR2_OIS6;
02769     /* Set the Output Idle state */
02770     tmpcr2 |= (OC_Config->OCIdleState << 10U);
02771   }
02772
02773   /* Write to TIMx CR2 */
02774   TIMx->CR2 = tmpcr2;
02775
02776   /* Write to TIMx CCMR3 */
02777   TIMx->CCMR3 = tmpccmrx;
02778
02779   /* Set the Capture Compare Register value */
02780   TIMx->CCR6 = OC_Config->Pulse;
02781
02782   /* Write to TIMx CCER */
02783   TIMx->CCER = tmpccer;
02784 }
02785 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
02786        /* STM32F302xC || STM32F303xC || STM32F358xx || */
02787        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
02788        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
02789 /**
02790   * @}
02791   */
02792
02793 #endif /* HAL_TIM_MODULE_ENABLED */
02794 /**
02795   * @}
02796   */
02797
02798 /**
02799   * @}
02800   */
02801
02802 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_tim_ex.h Source File

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stm32f3xx_hal_tim_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_tim_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TIM HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_TIM_EX_H
00038 #define __STM32F3xx_HAL_TIM_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup TIMEx
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /** @defgroup TIMEx_Exported_Types TIMEx Exported Types
00057   * @{
00058   */
00059
00060 /**
00061   * @brief  TIM Hall sensor Configuration Structure definition
00062   */
00063
00064 typedef struct
00065 {
00066
00067   uint32_t IC1Polarity;            /*!< Specifies the active edge of the input signal.
00068                                         This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00069
00070   uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
00071                                      This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00072
00073   uint32_t IC1Filter;           /*!< Specifies the input capture filter.
00074                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
00075   uint32_t Commutation_Delay;  /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00076                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
00077 } TIM_HallSensor_InitTypeDef;
00078
00079 #if defined(STM32F373xC) || defined(STM32F378xx)
00080 /**
00081   * @brief  TIM Master configuration Structure definition
00082   * @note   STM32F373xC and STM32F378xx: timer instances provide a single TRGO
00083   *         output
00084   */
00085 typedef struct {
00086   uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
00087                                       This parameter can be a value of @ref TIM_Master_Mode_Selection */
00088   uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
00089                                       This parameter can be a value of @ref TIM_Master_Slave_Mode */
00090 }TIM_MasterConfigTypeDef;
00091
00092 /**
00093   * @brief  TIM Break and Dead time configuration Structure definition
00094   * @note   STM32F373xC and STM32F378xx: single break input with configurable polarity.
00095   */
00096 typedef struct
00097 {
00098   uint32_t OffStateRunMode;        /*!< TIM off state in run mode
00099                                          This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
00100   uint32_t OffStateIDLEMode;        /*!< TIM off state in IDLE mode
00101                                          This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
00102   uint32_t LockLevel;           /*!< TIM Lock level
00103                                          This parameter can be a value of @ref TIM_Lock_level */
00104   uint32_t DeadTime;           /*!< TIM dead Time
00105                                          This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
00106   uint32_t BreakState;           /*!< TIM Break State
00107                                          This parameter can be a value of @ref TIM_Break_Input_enable_disable */
00108   uint32_t BreakPolarity;             /*!< TIM Break input polarity
00109                                          This parameter can be a value of @ref TIM_Break_Polarity */
00110   uint32_t AutomaticOutput;           /*!< TIM Automatic Output Enable state
00111                                          This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
00112 } TIM_BreakDeadTimeConfigTypeDef;
00113
00114 #endif /* STM32F373xC || STM32F378xx */
00115
00116 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00117     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00118     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00119     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00120 /**
00121   * @brief  TIM Break input(s) and Dead time configuration Structure definition
00122   * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
00123   *        filter and polarity.
00124   */
00125 typedef struct
00126 {
00127   uint32_t OffStateRunMode;        /*!< TIM off state in run mode
00128                                          This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
00129   uint32_t OffStateIDLEMode;        /*!< TIM off state in IDLE mode
00130                                          This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
00131   uint32_t LockLevel;           /*!< TIM Lock level
00132                                          This parameter can be a value of @ref TIM_Lock_level */
00133   uint32_t DeadTime;           /*!< TIM dead Time
00134                                          This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
00135   uint32_t BreakState;           /*!< TIM Break State
00136                                          This parameter can be a value of @ref TIM_Break_Input_enable_disable */
00137   uint32_t BreakPolarity;             /*!< TIM Break input polarity
00138                                          This parameter can be a value of @ref TIM_Break_Polarity */
00139   uint32_t BreakFilter;               /*!< Specifies the brek input filter.
00140                                          This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
00141   uint32_t Break2State;           /*!< TIM Break2 State
00142                                          This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
00143   uint32_t Break2Polarity;            /*!< TIM Break2 input polarity
00144                                          This parameter can be a value of @ref TIMEx_Break2_Polarity */
00145   uint32_t Break2Filter;              /*!< TIM break2 input filter.
00146                                          This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
00147   uint32_t AutomaticOutput;           /*!< TIM Automatic Output Enable state
00148                                          This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
00149 } TIM_BreakDeadTimeConfigTypeDef;
00150
00151 /**
00152   * @brief  TIM Master configuration Structure definition
00153   * @note   Advanced timers provide TRGO2 internal line which is redirected
00154   *         to the ADC
00155   */
00156 typedef struct {
00157   uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
00158                                       This parameter can be a value of @ref TIM_Master_Mode_Selection */
00159   uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
00160                                       This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
00161   uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
00162                                       This parameter can be a value of @ref TIM_Master_Slave_Mode */
00163 }TIM_MasterConfigTypeDef;
00164 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00165        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00166        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00167        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00168 /**
00169   * @}
00170   */
00171
00172 /* Exported constants --------------------------------------------------------*/
00173 /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
00174   * @{
00175   */
00176
00177 #if defined(STM32F373xC) || defined(STM32F378xx)
00178 /** @defgroup TIMEx_Channel TIMEx Channel
00179   * @{
00180   */
00181 #define TIM_CHANNEL_1                      (0x0000U)
00182 #define TIM_CHANNEL_2                      (0x0004U)
00183 #define TIM_CHANNEL_3                      (0x0008U)
00184 #define TIM_CHANNEL_4                      (0x000CU)
00185 #define TIM_CHANNEL_ALL                    (0x0018U)
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
00191   * @{
00192   */
00193 #define TIM_OCMODE_TIMING                   (0x0000U)
00194 #define TIM_OCMODE_ACTIVE                   ((uint32_t)TIM_CCMR1_OC1M_0)
00195 #define TIM_OCMODE_INACTIVE                 ((uint32_t)TIM_CCMR1_OC1M_1)
00196 #define TIM_OCMODE_TOGGLE                   ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
00197 #define TIM_OCMODE_PWM1                     ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
00198 #define TIM_OCMODE_PWM2                     ((uint32_t)TIM_CCMR1_OC1M)
00199 #define TIM_OCMODE_FORCED_ACTIVE            ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
00200 #define TIM_OCMODE_FORCED_INACTIVE          ((uint32_t)TIM_CCMR1_OC1M_2)
00201 /**
00202   * @}
00203   */
00204
00205 /** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
00206   * @{
00207   */
00208 #define TIM_CLEARINPUTSOURCE_ETR           (0x0001U)
00209 #define TIM_CLEARINPUTSOURCE_NONE          (0x0000U)
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup TIMEx_Slave_Mode TIMEx Slave Mode
00215   * @{
00216   */
00217 #define TIM_SLAVEMODE_DISABLE                (0x0000U)
00218 #define TIM_SLAVEMODE_RESET                  ((uint32_t)(TIM_SMCR_SMS_2))
00219 #define TIM_SLAVEMODE_GATED                  ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
00220 #define TIM_SLAVEMODE_TRIGGER                ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
00221 #define TIM_SLAVEMODE_EXTERNAL1              ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup TIMEx_Event_Source TIMEx Event Source
00227   * @{
00228   */
00229 #define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
00230 #define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1U */
00231 #define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2U */
00232 #define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3U */
00233 #define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4U */
00234 #define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
00235 #define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
00236 #define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup TIMEx_DMA_Base_address TIMEx DMA BAse Address
00242   * @{
00243   */
00244 #define TIM_DMABASE_CR1                    (0x00000000U)
00245 #define TIM_DMABASE_CR2                    (0x00000001U)
00246 #define TIM_DMABASE_SMCR                   (0x00000002U)
00247 #define TIM_DMABASE_DIER                   (0x00000003U)
00248 #define TIM_DMABASE_SR                     (0x00000004U)
00249 #define TIM_DMABASE_EGR                    (0x00000005U)
00250 #define TIM_DMABASE_CCMR1                  (0x00000006U)
00251 #define TIM_DMABASE_CCMR2                  (0x00000007U)
00252 #define TIM_DMABASE_CCER                   (0x00000008U)
00253 #define TIM_DMABASE_CNT                    (0x00000009U)
00254 #define TIM_DMABASE_PSC                    (0x0000000AU)
00255 #define TIM_DMABASE_ARR                    (0x0000000BU)
00256 #define TIM_DMABASE_RCR                    (0x0000000CU)
00257 #define TIM_DMABASE_CCR1                   (0x0000000DU)
00258 #define TIM_DMABASE_CCR2                   (0x0000000EU)
00259 #define TIM_DMABASE_CCR3                   (0x0000000FU)
00260 #define TIM_DMABASE_CCR4                   (0x00000010U)
00261 #define TIM_DMABASE_BDTR                   (0x00000011U)
00262 #define TIM_DMABASE_DCR                    (0x00000012U)
00263 #define TIM_DMABASE_OR                     (0x00000013U)
00264 /**
00265   * @}
00266   */
00267 #endif /* STM32F373xC || STM32F378xx */
00268
00269 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00270     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00271     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00272     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00273 /** @defgroup TIMEx_Channel TIMEx Channel
00274   * @{
00275   */
00276 #define TIM_CHANNEL_1                      (0x0000U)
00277 #define TIM_CHANNEL_2                      (0x0004U)
00278 #define TIM_CHANNEL_3                      (0x0008U)
00279 #define TIM_CHANNEL_4                      (0x000CU)
00280 #define TIM_CHANNEL_5                      (0x0010U)
00281 #define TIM_CHANNEL_6                      (0x0014U)
00282 #define TIM_CHANNEL_ALL                    (0x003CU)
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
00288   * @{
00289   */
00290 #define TIM_OCMODE_TIMING                   (0x0000U)
00291 #define TIM_OCMODE_ACTIVE                   ((uint32_t)TIM_CCMR1_OC1M_0)
00292 #define TIM_OCMODE_INACTIVE                 ((uint32_t)TIM_CCMR1_OC1M_1)
00293 #define TIM_OCMODE_TOGGLE                   ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
00294 #define TIM_OCMODE_PWM1                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
00295 #define TIM_OCMODE_PWM2                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
00296 #define TIM_OCMODE_FORCED_ACTIVE            ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
00297 #define TIM_OCMODE_FORCED_INACTIVE          ((uint32_t)TIM_CCMR1_OC1M_2)
00298
00299 #define TIM_OCMODE_RETRIGERRABLE_OPM1      ((uint32_t)TIM_CCMR1_OC1M_3)
00300 #define TIM_OCMODE_RETRIGERRABLE_OPM2      ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
00301 #define TIM_OCMODE_COMBINED_PWM1           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
00302 #define TIM_OCMODE_COMBINED_PWM2           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
00303 #define TIM_OCMODE_ASSYMETRIC_PWM1         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
00304 #define TIM_OCMODE_ASSYMETRIC_PWM2         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
00305
00306 /**
00307   * @}
00308   */
00309
00310 /** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
00311   * @{
00312   */
00313 #define TIM_CLEARINPUTSOURCE_ETR            (0x0001U)
00314 #define TIM_CLEARINPUTSOURCE_OCREFCLR       (0x0002U)
00315 #define TIM_CLEARINPUTSOURCE_NONE           (0x0000U)
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup TIMEx_Break2_Input_enable_disable  TIMEX Break input 2 Enable
00321   * @{
00322   */
00323 #define TIM_BREAK2_DISABLE         (0x00000000U)
00324 #define TIM_BREAK2_ENABLE          ((uint32_t)TIM_BDTR_BK2E)
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup TIMEx_Break2_Polarity TIMEx Break Input 2 Polarity
00330   * @{
00331   */
00332 #define TIM_BREAK2POLARITY_LOW        (0x00000000U)
00333 #define TIM_BREAK2POLARITY_HIGH       ((uint32_t)TIM_BDTR_BK2P)
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2)
00339   * @{
00340   */
00341 #define  TIM_TRGO2_RESET                          (0x00000000U)
00342 #define  TIM_TRGO2_ENABLE                         ((uint32_t)(TIM_CR2_MMS2_0))
00343 #define  TIM_TRGO2_UPDATE                         ((uint32_t)(TIM_CR2_MMS2_1))
00344 #define  TIM_TRGO2_OC1                            ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00345 #define  TIM_TRGO2_OC1REF                         ((uint32_t)(TIM_CR2_MMS2_2))
00346 #define  TIM_TRGO2_OC2REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
00347 #define  TIM_TRGO2_OC3REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
00348 #define  TIM_TRGO2_OC4REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00349 #define  TIM_TRGO2_OC5REF                         ((uint32_t)(TIM_CR2_MMS2_3))
00350 #define  TIM_TRGO2_OC6REF                         ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
00351 #define  TIM_TRGO2_OC4REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
00352 #define  TIM_TRGO2_OC6REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00353 #define  TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
00354 #define  TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
00355 #define  TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
00356 #define  TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup TIMEx_Slave_Mode TIMEx Slave mode
00362   * @{
00363   */
00364 #define TIM_SLAVEMODE_DISABLE                (0x0000U)
00365 #define TIM_SLAVEMODE_RESET                  ((uint32_t)(TIM_SMCR_SMS_2))
00366 #define TIM_SLAVEMODE_GATED                  ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
00367 #define TIM_SLAVEMODE_TRIGGER                ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
00368 #define TIM_SLAVEMODE_EXTERNAL1              ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
00369 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  ((uint32_t)(TIM_SMCR_SMS_3))
00370 /**
00371   * @}
00372   */
00373
00374 /** @defgroup TIM_Event_Source TIMEx Event Source
00375   * @{
00376   */
00377 #define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
00378 #define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1U */
00379 #define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2U */
00380 #define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3U */
00381 #define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4U */
00382 #define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
00383 #define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
00384 #define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
00385 #define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
00386 /**
00387   * @}
00388   */
00389
00390 /** @defgroup TIM_DMA_Base_address TIMEx DMA Base Address
00391   * @{
00392   */
00393 #define TIM_DMABASE_CR1                    (0x00000000U)
00394 #define TIM_DMABASE_CR2                    (0x00000001U)
00395 #define TIM_DMABASE_SMCR                   (0x00000002U)
00396 #define TIM_DMABASE_DIER                   (0x00000003U)
00397 #define TIM_DMABASE_SR                     (0x00000004U)
00398 #define TIM_DMABASE_EGR                    (0x00000005U)
00399 #define TIM_DMABASE_CCMR1                  (0x00000006U)
00400 #define TIM_DMABASE_CCMR2                  (0x00000007U)
00401 #define TIM_DMABASE_CCER                   (0x00000008U)
00402 #define TIM_DMABASE_CNT                    (0x00000009U)
00403 #define TIM_DMABASE_PSC                    (0x0000000AU)
00404 #define TIM_DMABASE_ARR                    (0x0000000BU)
00405 #define TIM_DMABASE_RCR                    (0x0000000CU)
00406 #define TIM_DMABASE_CCR1                   (0x0000000DU)
00407 #define TIM_DMABASE_CCR2                   (0x0000000EU)
00408 #define TIM_DMABASE_CCR3                   (0x0000000FU)
00409 #define TIM_DMABASE_CCR4                   (0x00000010U)
00410 #define TIM_DMABASE_BDTR                   (0x00000011U)
00411 #define TIM_DMABASE_DCR                    (0x00000012U)
00412 #define TIM_DMABASE_CCMR3                  (0x00000015U)
00413 #define TIM_DMABASE_CCR5                   (0x00000016U)
00414 #define TIM_DMABASE_CCR6                   (0x00000017U)
00415 #define TIM_DMABASE_OR                     (0x00000018U)
00416 /**
00417   * @}
00418   */
00419 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00420        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00421        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00422        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00423
00424 #if defined(STM32F302xE)                                                 || \
00425     defined(STM32F302xC)                                                 || \
00426     defined(STM32F303x8) || defined(STM32F328xx) || \
00427     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00428 /** @defgroup TIMEx_Remap TIMEx Remapping
00429   * @{
00430   */
00431 #define TIM_TIM1_ADC1_NONE                     (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
00432 #define TIM_TIM1_ADC1_AWD1                     (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
00433 #define TIM_TIM1_ADC1_AWD2                     (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
00434 #define TIM_TIM1_ADC1_AWD3                     (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
00435 #define TIM_TIM16_GPIO                         (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
00436 #define TIM_TIM16_RTC                          (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
00437 #define TIM_TIM16_HSE                          (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
00438 #define TIM_TIM16_MCO                          (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
00439 /**
00440   * @}
00441   */
00442 #endif /* STM32F302xE                               || */
00443        /* STM32F302xC                               || */
00444        /* STM32F303x8 || STM32F328xx || */
00445        /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
00446
00447
00448 #if defined(STM32F334x8)
00449 /** @defgroup TIMEx_Remap TIMEx Remapping 1
00450   * @{
00451   */
00452 #define TIM_TIM1_ADC1_NONE                     (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
00453 #define TIM_TIM1_ADC1_AWD1                     (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
00454 #define TIM_TIM1_ADC1_AWD2                     (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
00455 #define TIM_TIM1_ADC1_AWD3                     (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
00456 #define TIM_TIM16_GPIO                         (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
00457 #define TIM_TIM16_RTC                          (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
00458 #define TIM_TIM16_HSE                          (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
00459 #define TIM_TIM16_MCO                          (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
00460 /**
00461   * @}
00462   */
00463
00464 /** @defgroup TIMEx_Remap2 TIMEx Remapping 2
00465   * @{
00466   */
00467 #define TIM_TIM1_ADC2_NONE                     (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
00468 #define TIM_TIM1_ADC2_AWD1                     (0x00000004U) /*!< TIM1_ETR is connected to ADC2 AWD1 */
00469 #define TIM_TIM1_ADC2_AWD2                     (0x00000008U) /*!< TIM1_ETR is connected to ADC2 AWD2 */
00470 #define TIM_TIM1_ADC2_AWD3                     (0x0000000CU) /*!< TIM1_ETR is connected to ADC2 AWD3 */
00471 #define TIM_TIM16_NONE                         (0x00000000U) /*!< Non significant value for TIM16U */
00472 /**
00473   * @}
00474   */
00475 #endif /* STM32F334x8 */
00476
00477 #if defined(STM32F303xC) || defined(STM32F358xx)
00478 /** @defgroup TIMEx_Remap TIMEx Remapping 1
00479   * @{
00480   */
00481 #define TIM_TIM1_ADC1_NONE                     (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
00482 #define TIM_TIM1_ADC1_AWD1                     (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
00483 #define TIM_TIM1_ADC1_AWD2                     (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
00484 #define TIM_TIM1_ADC1_AWD3                     (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
00485 #define TIM_TIM8_ADC2_NONE                     (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
00486 #define TIM_TIM8_ADC2_AWD1                     (0x00000001U) /*!< TIM8_ETR is connected to ADC2 AWD1 */
00487 #define TIM_TIM8_ADC2_AWD2                     (0x00000002U) /*!< TIM8_ETR is connected to ADC2 AWD2 */
00488 #define TIM_TIM8_ADC2_AWD3                     (0x00000003U) /*!< TIM8_ETR is connected to ADC2 AWD3 */
00489 #define TIM_TIM16_GPIO                         (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
00490 #define TIM_TIM16_RTC                          (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
00491 #define TIM_TIM16_HSE                          (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
00492 #define TIM_TIM16_MCO                          (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
00493 /**
00494   * @}
00495   */
00496
00497 /** @defgroup TIMEx_Remap2 TIMEx Remapping 2
00498   * @{
00499   */
00500 #define TIM_TIM1_ADC4_NONE                     (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
00501 #define TIM_TIM1_ADC4_AWD1                     (0x00000004U) /*!< TIM1_ETR is connected to ADC4 AWD1 */
00502 #define TIM_TIM1_ADC4_AWD2                     (0x00000008U) /*!< TIM1_ETR is connected to ADC4 AWD2 */
00503 #define TIM_TIM1_ADC4_AWD3                     (0x0000000CU) /*!< TIM1_ETR is connected to ADC4 AWD3 */
00504 #define TIM_TIM8_ADC3_NONE                     (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
00505 #define TIM_TIM8_ADC3_AWD1                     (0x00000004U) /*!< TIM8_ETR is connected to ADC3 AWD1 */
00506 #define TIM_TIM8_ADC3_AWD2                     (0x00000008U) /*!< TIM8_ETR is connected to ADC3 AWD2 */
00507 #define TIM_TIM8_ADC3_AWD3                     (0x0000000CU) /*!< TIM8_ETR is connected to ADC3 AWD3 */
00508 #define TIM_TIM16_NONE                         (0x00000000U) /*!< Non significant value for TIM16U */
00509 /**
00510   * @}
00511   */
00512 #endif /* STM32F303xC || STM32F358xx */
00513
00514 #if defined(STM32F303xE) || defined(STM32F398xx)
00515 /** @defgroup TIMEx_Remap TIMEx Remapping 1
00516   * @{
00517   */
00518 #define TIM_TIM1_ADC1_NONE                     (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
00519 #define TIM_TIM1_ADC1_AWD1                     (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
00520 #define TIM_TIM1_ADC1_AWD2                     (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
00521 #define TIM_TIM1_ADC1_AWD3                     (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
00522 #define TIM_TIM8_ADC2_NONE                     (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
00523 #define TIM_TIM8_ADC2_AWD1                     (0x00000001U) /*!< TIM8_ETR is connected to ADC2 AWD1 */
00524 #define TIM_TIM8_ADC2_AWD2                     (0x00000002U) /*!< TIM8_ETR is connected to ADC2 AWD2 */
00525 #define TIM_TIM8_ADC2_AWD3                     (0x00000003U) /*!< TIM8_ETR is connected to ADC2 AWD3 */
00526 #define TIM_TIM16_GPIO                         (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
00527 #define TIM_TIM16_RTC                          (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
00528 #define TIM_TIM16_HSE                          (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
00529 #define TIM_TIM16_MCO                          (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
00530 #define TIM_TIM20_ADC3_NONE                    (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
00531 #define TIM_TIM20_ADC3_AWD1                    (0x00000001U) /*!< TIM20_ETR is connected to ADC3 AWD1 */
00532 #define TIM_TIM20_ADC3_AWD2                    (0x00000002U) /*!< TIM20_ETR is connected to ADC3 AWD2 */
00533 #define TIM_TIM20_ADC3_AWD3                    (0x00000003U) /*!< TIM20_ETR is connected to ADC3 AWD3 */
00534 /**
00535   * @}
00536   */
00537
00538 /** @defgroup TIMEx_Remap2 TIMEx Remapping 2
00539   * @{
00540   */
00541 #define TIM_TIM1_ADC4_NONE                     (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
00542 #define TIM_TIM1_ADC4_AWD1                     (0x00000004U) /*!< TIM1_ETR is connected to ADC4 AWD1 */
00543 #define TIM_TIM1_ADC4_AWD2                     (0x00000008U) /*!< TIM1_ETR is connected to ADC4 AWD2 */
00544 #define TIM_TIM1_ADC4_AWD3                     (0x0000000CU) /*!< TIM1_ETR is connected to ADC4 AWD3 */
00545 #define TIM_TIM8_ADC3_NONE                     (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
00546 #define TIM_TIM8_ADC3_AWD1                     (0x00000004U) /*!< TIM8_ETR is connected to ADC3 AWD1 */
00547 #define TIM_TIM8_ADC3_AWD2                     (0x00000008U) /*!< TIM8_ETR is connected to ADC3 AWD2 */
00548 #define TIM_TIM8_ADC3_AWD3                     (0x0000000CU) /*!< TIM8_ETR is connected to ADC3 AWD3 */
00549 #define TIM_TIM16_NONE                         (0x00000000U) /*!< Non significant value for TIM16U */
00550 #define TIM_TIM20_ADC4_NONE                    (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
00551 #define TIM_TIM20_ADC4_AWD1                    (0x00000004U) /*!< TIM20_ETR is connected to ADC4 AWD1 */
00552 #define TIM_TIM20_ADC4_AWD2                    (0x00000008U) /*!< TIM20_ETR is connected to ADC4 AWD2 */
00553 #define TIM_TIM20_ADC4_AWD3                    (0x0000000CU) /*!< TIM20_ETR is connected to ADC4 AWD3 */
00554 /**
00555   * @}
00556   */
00557 #endif /* STM32F303xE || STM32F398xx */
00558
00559
00560 #if defined(STM32F373xC) || defined(STM32F378xx)
00561 /** @defgroup TIMEx_Remap TIMEx remapping
00562   * @{
00563   */
00564 #define TIM_TIM2_TIM8_TRGO      (0x00000000U)  /*!< TIM8 TRGOUT is connected to TIM2_ITR1 */
00565 #define TIM_TIM2_ETH_PTP        (0x00000400U)  /*!< PTP trigger output is connected to TIM2_ITR1 */
00566 #define TIM_TIM2_USBFS_SOF      (0x00000800U)  /*!< OTG FS SOF is connected to the TIM2_ITR1 input */
00567 #define TIM_TIM2_USBHS_SOF      (0x00000C00U)  /*!< OTG HS SOF is connected to the TIM2_ITR1 input */
00568 #define TIM_TIM14_GPIO          (0x00000000U) /*!< TIM14 TI1 is connected to GPIO */
00569 #define TIM_TIM14_RTC           (0x00000001U) /*!< TIM14 TI1 is connected to RTC_clock */
00570 #define TIM_TIM14_HSE           (0x00000002U) /*!< TIM14 TI1 is connected to HSE/32U */
00571 #define TIM_TIM14_MCO           (0x00000003U) /*!< TIM14 TI1 is connected to MCO */
00572 /**
00573   * @}
00574   */
00575 #endif /* STM32F373xC || STM32F378xx */
00576
00577 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00578     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00579     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00580     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00581 /** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1U, 2 or 3
00582   * @{
00583   */
00584 #define TIM_GROUPCH5_NONE       0x00000000  /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
00585 #define TIM_GROUPCH5_OC1REFC    (TIM_CCR5_GC5C1)      /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
00586 #define TIM_GROUPCH5_OC2REFC    (TIM_CCR5_GC5C2)      /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
00587 #define TIM_GROUPCH5_OC3REFC    (TIM_CCR5_GC5C3)       /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
00588 /**
00589   * @}
00590   */
00591 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00592        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00593        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00594        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00595
00596 /**
00597   * @}
00598   */
00599
00600
00601 /* Private Macros -----------------------------------------------------------*/
00602 /** @defgroup TIM_Private_Macros TIM Private Macros
00603   * @{
00604   */
00605 #if defined(STM32F373xC) || defined(STM32F378xx)
00606
00607 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
00608                                   ((CHANNEL) == TIM_CHANNEL_2) || \
00609                                   ((CHANNEL) == TIM_CHANNEL_3) || \
00610                                   ((CHANNEL) == TIM_CHANNEL_4) || \
00611                                   ((CHANNEL) == TIM_CHANNEL_ALL))
00612
00613 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
00614                                       ((CHANNEL) == TIM_CHANNEL_2))
00615
00616 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
00617                                                 ((CHANNEL) == TIM_CHANNEL_2) || \
00618                                                 ((CHANNEL) == TIM_CHANNEL_3))
00619
00620 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
00621                                ((MODE) == TIM_OCMODE_PWM2))
00622
00623 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING)           || \
00624                               ((MODE) == TIM_OCMODE_ACTIVE)           || \
00625                               ((MODE) == TIM_OCMODE_INACTIVE)         || \
00626                               ((MODE) == TIM_OCMODE_TOGGLE)           || \
00627                               ((MODE) == TIM_OCMODE_FORCED_ACTIVE)    || \
00628                               ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
00629
00630 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE)  (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
00631                                            ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
00632
00633 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
00634                                  ((MODE) == TIM_SLAVEMODE_RESET) || \
00635                                  ((MODE) == TIM_SLAVEMODE_GATED) || \
00636                                  ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
00637                                  ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
00638
00639 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
00640
00641 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
00642                                ((BASE) == TIM_DMABASE_CR2) || \
00643                                ((BASE) == TIM_DMABASE_SMCR) || \
00644                                ((BASE) == TIM_DMABASE_DIER) || \
00645                                ((BASE) == TIM_DMABASE_SR) || \
00646                                ((BASE) == TIM_DMABASE_EGR) || \
00647                                ((BASE) == TIM_DMABASE_CCMR1) || \
00648                                ((BASE) == TIM_DMABASE_CCMR2) || \
00649                                ((BASE) == TIM_DMABASE_CCER) || \
00650                                ((BASE) == TIM_DMABASE_CNT) || \
00651                                ((BASE) == TIM_DMABASE_PSC) || \
00652                                ((BASE) == TIM_DMABASE_ARR) || \
00653                                ((BASE) == TIM_DMABASE_RCR) || \
00654                                ((BASE) == TIM_DMABASE_CCR1) || \
00655                                ((BASE) == TIM_DMABASE_CCR2) || \
00656                                ((BASE) == TIM_DMABASE_CCR3) || \
00657                                ((BASE) == TIM_DMABASE_CCR4) || \
00658                                ((BASE) == TIM_DMABASE_BDTR) || \
00659                                ((BASE) == TIM_DMABASE_DCR) || \
00660                                ((BASE) == TIM_DMABASE_OR))
00661
00662 #endif /* STM32F373xC || STM32F378xx */
00663
00664
00665
00666 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00667     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00668     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00669     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00670
00671 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
00672                                   ((CHANNEL) == TIM_CHANNEL_2) || \
00673                                   ((CHANNEL) == TIM_CHANNEL_3) || \
00674                                   ((CHANNEL) == TIM_CHANNEL_4) || \
00675                                   ((CHANNEL) == TIM_CHANNEL_5) || \
00676                                   ((CHANNEL) == TIM_CHANNEL_6) || \
00677                                   ((CHANNEL) == TIM_CHANNEL_ALL))
00678
00679 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
00680                                       ((CHANNEL) == TIM_CHANNEL_2))
00681
00682 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
00683                                                 ((CHANNEL) == TIM_CHANNEL_2) || \
00684                                                 ((CHANNEL) == TIM_CHANNEL_3))
00685
00686 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1)               || \
00687                                ((MODE) == TIM_OCMODE_PWM2)               || \
00688                                ((MODE) == TIM_OCMODE_COMBINED_PWM1)      || \
00689                                ((MODE) == TIM_OCMODE_COMBINED_PWM2)      || \
00690                                ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
00691                                ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
00692
00693 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING)             || \
00694                              ((MODE) == TIM_OCMODE_ACTIVE)             || \
00695                              ((MODE) == TIM_OCMODE_INACTIVE)           || \
00696                              ((MODE) == TIM_OCMODE_TOGGLE)             || \
00697                              ((MODE) == TIM_OCMODE_FORCED_ACTIVE)      || \
00698                              ((MODE) == TIM_OCMODE_FORCED_INACTIVE)    || \
00699                              ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
00700                              ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
00701
00702 #define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR)      || \
00703                                         ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR)  || \
00704                                         ((MODE) == TIM_CLEARINPUTSOURCE_NONE))
00705
00706 #define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xFU)
00707
00708 #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
00709                                     ((STATE) == TIM_BREAK2_DISABLE))
00710
00711 #define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_BREAK2POLARITY_LOW) || \
00712                                           ((POLARITY) == TIM_BREAK2POLARITY_HIGH))
00713
00714 #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET)                        || \
00715                                      ((SOURCE) == TIM_TRGO2_ENABLE)                       || \
00716                                      ((SOURCE) == TIM_TRGO2_UPDATE)                       || \
00717                                      ((SOURCE) == TIM_TRGO2_OC1)                          || \
00718                                      ((SOURCE) == TIM_TRGO2_OC1REF)                       || \
00719                                      ((SOURCE) == TIM_TRGO2_OC2REF)                       || \
00720                                      ((SOURCE) == TIM_TRGO2_OC3REF)                       || \
00721                                      ((SOURCE) == TIM_TRGO2_OC3REF)                       || \
00722                                      ((SOURCE) == TIM_TRGO2_OC4REF)                       || \
00723                                      ((SOURCE) == TIM_TRGO2_OC5REF)                       || \
00724                                      ((SOURCE) == TIM_TRGO2_OC6REF)                       || \
00725                                      ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
00726                                      ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
00727                                      ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
00728                                      ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
00729                                      ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
00730                                      ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
00731
00732 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE)   || \
00733                                  ((MODE) == TIM_SLAVEMODE_RESET)     || \
00734                                  ((MODE) == TIM_SLAVEMODE_GATED)     || \
00735                                  ((MODE) == TIM_SLAVEMODE_TRIGGER)   || \
00736                                  ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
00737                                  ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
00738
00739 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
00740
00741 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1)   || \
00742                                ((BASE) == TIM_DMABASE_CR2)   || \
00743                                ((BASE) == TIM_DMABASE_SMCR)  || \
00744                                ((BASE) == TIM_DMABASE_DIER)  || \
00745                                ((BASE) == TIM_DMABASE_SR)    || \
00746                                ((BASE) == TIM_DMABASE_EGR)   || \
00747                                ((BASE) == TIM_DMABASE_CCMR1) || \
00748                                ((BASE) == TIM_DMABASE_CCMR2) || \
00749                                ((BASE) == TIM_DMABASE_CCER)  || \
00750                                ((BASE) == TIM_DMABASE_CNT)   || \
00751                                ((BASE) == TIM_DMABASE_PSC)   || \
00752                                ((BASE) == TIM_DMABASE_ARR)   || \
00753                                ((BASE) == TIM_DMABASE_RCR)   || \
00754                                ((BASE) == TIM_DMABASE_CCR1)  || \
00755                                ((BASE) == TIM_DMABASE_CCR2)  || \
00756                                ((BASE) == TIM_DMABASE_CCR3)  || \
00757                                ((BASE) == TIM_DMABASE_CCR4)  || \
00758                                ((BASE) == TIM_DMABASE_BDTR)  || \
00759                                ((BASE) == TIM_DMABASE_CCMR3) || \
00760                                ((BASE) == TIM_DMABASE_CCR5)  || \
00761                                ((BASE) == TIM_DMABASE_CCR6)  || \
00762                                ((BASE) == TIM_DMABASE_OR))
00763
00764 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00765        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00766        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00767        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00768
00769 #if defined(STM32F302xE)                                                 || \
00770     defined(STM32F302xC)                                                 || \
00771     defined(STM32F303x8) || defined(STM32F328xx) || \
00772     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00773
00774 #define IS_TIM_REMAP(REMAP)    (((REMAP) == TIM_TIM1_ADC1_NONE) ||\
00775                                 ((REMAP) == TIM_TIM1_ADC1_AWD1) ||\
00776                                 ((REMAP) == TIM_TIM1_ADC1_AWD2) ||\
00777                                 ((REMAP) == TIM_TIM1_ADC1_AWD3) ||\
00778                                 ((REMAP) == TIM_TIM16_GPIO)     ||\
00779                                 ((REMAP) == TIM_TIM16_RTC)      ||\
00780                                 ((REMAP) == TIM_TIM16_HSE)      ||\
00781                                 ((REMAP) == TIM_TIM16_MCO))
00782
00783 #endif /* STM32F302xE                               || */
00784        /* STM32F302xC                               || */
00785        /* STM32F303x8 || STM32F328xx || */
00786        /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
00787
00788 #if defined(STM32F334x8)
00789 #define IS_TIM_REMAP(REMAP1)   (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
00790                                 ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
00791                                 ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
00792                                 ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
00793                                 ((REMAP1) == TIM_TIM16_GPIO)     ||\
00794                                 ((REMAP1) == TIM_TIM16_RTC)      ||\
00795                                 ((REMAP1) == TIM_TIM16_HSE)      ||\
00796                                 ((REMAP1) == TIM_TIM16_MCO))
00797
00798 #define IS_TIM_REMAP2(REMAP2)  (((REMAP2) == TIM_TIM1_ADC2_NONE) ||\
00799                                 ((REMAP2) == TIM_TIM1_ADC2_AWD1) ||\
00800                                 ((REMAP2) == TIM_TIM1_ADC2_AWD2) ||\
00801                                 ((REMAP2) == TIM_TIM1_ADC2_AWD3) ||\
00802                                 ((REMAP2) == TIM_TIM16_NONE))
00803
00804 #endif /* STM32F334x8 */
00805
00806 #if defined(STM32F303xC) || defined(STM32F358xx)
00807
00808 #define IS_TIM_REMAP(REMAP1)   (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
00809                                 ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
00810                                 ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
00811                                 ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
00812                                 ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
00813                                 ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
00814                                 ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
00815                                 ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
00816                                 ((REMAP1) == TIM_TIM16_GPIO)     ||\
00817                                 ((REMAP1) == TIM_TIM16_RTC)      ||\
00818                                 ((REMAP1) == TIM_TIM16_HSE)      ||\
00819                                 ((REMAP1) == TIM_TIM16_MCO))
00820
00821 #define IS_TIM_REMAP2(REMAP2)  (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
00822                                 ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
00823                                 ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
00824                                 ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
00825                                 ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
00826                                 ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
00827                                 ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
00828                                 ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
00829                                 ((REMAP2) == TIM_TIM16_NONE))
00830
00831 #endif /* STM32F303xC || STM32F358xx */
00832
00833 #if defined(STM32F303xE) || defined(STM32F398xx)
00834
00835 #define IS_TIM_REMAP(REMAP1)   (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
00836                                 ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
00837                                 ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
00838                                 ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
00839                                 ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
00840                                 ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
00841                                 ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
00842                                 ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
00843                                 ((REMAP1) == TIM_TIM16_GPIO)     ||\
00844                                 ((REMAP1) == TIM_TIM16_RTC)      ||\
00845                                 ((REMAP1) == TIM_TIM16_HSE)      ||\
00846                                 ((REMAP1) == TIM_TIM16_MCO)      ||\
00847                                 ((REMAP1) == TIM_TIM20_ADC3_NONE) ||\
00848                                 ((REMAP1) == TIM_TIM20_ADC3_AWD1) ||\
00849                                 ((REMAP1) == TIM_TIM20_ADC3_AWD2) ||\
00850                                 ((REMAP1) == TIM_TIM20_ADC3_AWD3))
00851
00852 #define IS_TIM_REMAP2(REMAP2)  (((REMAP2) == TIM_TIM1_ADC4_NONE)  ||\
00853                                 ((REMAP2) == TIM_TIM1_ADC4_AWD1)  ||\
00854                                 ((REMAP2) == TIM_TIM1_ADC4_AWD2)  ||\
00855                                 ((REMAP2) == TIM_TIM1_ADC4_AWD3)  ||\
00856                                 ((REMAP2) == TIM_TIM8_ADC3_NONE)  ||\
00857                                 ((REMAP2) == TIM_TIM8_ADC3_AWD1)  ||\
00858                                 ((REMAP2) == TIM_TIM8_ADC3_AWD2)  ||\
00859                                 ((REMAP2) == TIM_TIM8_ADC3_AWD3)  ||\
00860                                 ((REMAP2) == TIM_TIM16_NONE)      ||\
00861                                 ((REMAP2) == TIM_TIM20_ADC4_NONE) ||\
00862                                 ((REMAP2) == TIM_TIM20_ADC4_AWD1) ||\
00863                                 ((REMAP2) == TIM_TIM20_ADC4_AWD2) ||\
00864                                 ((REMAP2) == TIM_TIM20_ADC4_AWD3))
00865
00866 #endif /* STM32F303xE || STM32F398xx */
00867
00868 #if defined(STM32F373xC) || defined(STM32F378xx)
00869
00870 #define IS_TIM_REMAP(REMAP)    (((REMAP) == TIM_TIM2_TIM8_TRGO)  ||\
00871                                 ((REMAP) == TIM_TIM2_ETH_PTP)    ||\
00872                                 ((REMAP) == TIM_TIM2_USBFS_SOF)  ||\
00873                                 ((REMAP) == TIM_TIM2_USBHS_SOF)  ||\
00874                                 ((REMAP) == TIM_TIM14_GPIO)      ||\
00875                                 ((REMAP) == TIM_TIM14_RTC)       ||\
00876                                 ((REMAP) == TIM_TIM14_HSE)       ||\
00877                                 ((REMAP) == TIM_TIM14_MCO))
00878
00879 #endif /* STM32F373xC || STM32F378xx */
00880
00881
00882 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00883     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00884     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00885     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00886
00887 #define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFFU) == 0x00000000U))
00888
00889 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00890        /* STM32F302xC || STM32F303xC || STM32F358xx || */
00891        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00892        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00893
00894 #define IS_TIM_DEADTIME(DEADTIME)      ((DEADTIME) <= 0xFFU)
00895
00896 /**
00897   * @}
00898   */
00899 /* End of private macros -----------------------------------------------------*/
00900
00901
00902 /* Exported macro ------------------------------------------------------------*/
00903 /** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros
00904   * @{
00905   */
00906
00907 #if defined(STM32F373xC) || defined(STM32F378xx)
00908 /**
00909   * @brief  Sets the TIM Capture Compare Register value on runtime without
00910   *         calling another time ConfigChannel function.
00911   * @param  __HANDLE__ TIM handle.
00912   * @param  __CHANNEL__ TIM Channels to be configured.
00913   *          This parameter can be one of the following values:
00914   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00915   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00916   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00917   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00918   * @param  __COMPARE__ specifies the Capture Compare register new value.
00919   * @retval None
00920   */
00921 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
00922 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
00923
00924 /**
00925   * @brief  Gets the TIM Capture Compare Register value on runtime
00926   * @param  __HANDLE__ TIM handle.
00927   * @param  __CHANNEL__ TIM Channel associated with the capture compare register
00928   *          This parameter can be one of the following values:
00929   *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
00930   *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
00931   *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
00932   *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
00933   * @retval None
00934   */
00935 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
00936   (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
00937
00938 /**
00939   * @brief  Sets the TIM Output compare preload.
00940   * @param  __HANDLE__ TIM handle.
00941   * @param  __CHANNEL__ TIM Channels to be configured.
00942   *          This parameter can be one of the following values:
00943   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00944   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00945   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00946   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00947   * @retval None
00948   */
00949 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
00950         (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
00951          ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
00952          ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
00953          ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
00954
00955 /**
00956   * @brief  Resets the TIM Output compare preload.
00957   * @param  __HANDLE__ TIM handle.
00958   * @param  __CHANNEL__ TIM Channels to be configured.
00959   *          This parameter can be one of the following values:
00960   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00961   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00962   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00963   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00964   * @retval None
00965   */
00966 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
00967         (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
00968          ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
00969          ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
00970          ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
00971
00972 #endif /* STM32F373xC || STM32F378xx */
00973
00974 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00975     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
00976     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00977     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00978 /**
00979   * @brief  Sets the TIM Capture Compare Register value on runtime without
00980   *         calling another time ConfigChannel function.
00981   * @param  __HANDLE__ TIM handle.
00982   * @param  __CHANNEL__ TIM Channels to be configured.
00983   *          This parameter can be one of the following values:
00984   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00985   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00986   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00987   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00988   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
00989   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
00990   * @param  __COMPARE__ specifies the Capture Compare register new value.
00991   * @retval None
00992   */
00993 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
00994 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
00995  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
00996  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
00997  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
00998  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
00999  ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
01000
01001 /**
01002   * @brief  Gets the TIM Capture Compare Register value on runtime
01003   * @param  __HANDLE__ TIM handle.
01004   * @param  __CHANNEL__ TIM Channel associated with the capture compare register
01005   *          This parameter can be one of the following values:
01006   *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
01007   *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
01008   *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
01009   *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
01010   *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
01011   *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
01012   * @retval None
01013   */
01014 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
01015 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
01016  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
01017  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
01018  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
01019  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
01020  ((__HANDLE__)->Instance->CCR6))
01021
01022 /**
01023   * @brief  Sets the TIM Output compare preload.
01024   * @param  __HANDLE__ TIM handle.
01025   * @param  __CHANNEL__ TIM Channels to be configured.
01026   *          This parameter can be one of the following values:
01027   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01028   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01029   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01030   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01031   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01032   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01033   * @retval None
01034   */
01035 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
01036         (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
01037          ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
01038          ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
01039          ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
01040          ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
01041          ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
01042
01043 /**
01044   * @brief  Resets the TIM Output compare preload.
01045   * @param  __HANDLE__ TIM handle.
01046   * @param  __CHANNEL__ TIM Channels to be configured.
01047   *          This parameter can be one of the following values:
01048   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01049   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01050   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01051   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01052   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01053   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01054   * @retval None
01055   */
01056 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
01057         (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
01058          ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
01059          ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
01060          ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
01061          ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
01062          ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
01063
01064 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
01065        /* STM32F302xC || STM32F303xC || STM32F358xx || */
01066        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
01067        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
01068 /**
01069   * @}
01070   */
01071
01072 /* Exported functions --------------------------------------------------------*/
01073 /** @addtogroup TIMEx_Exported_Functions
01074   * @{
01075   */
01076
01077 /** @addtogroup TIMEx_Exported_Functions_Group1
01078  * @{
01079  */
01080 /*  Timer Hall Sensor functions  **********************************************/
01081 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
01082 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
01083
01084 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
01085 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
01086
01087  /* Blocking mode: Polling */
01088 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
01089 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
01090 /* Non-Blocking mode: Interrupt */
01091 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
01092 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
01093 /* Non-Blocking mode: DMA */
01094 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
01095 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
01096 /**
01097   * @}
01098   */
01099
01100 /** @addtogroup TIMEx_Exported_Functions_Group2
01101  * @{
01102  */
01103 /*  Timer Complementary Output Compare functions  *****************************/
01104 /* Blocking mode: Polling */
01105 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01106 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01107
01108 /* Non-Blocking mode: Interrupt */
01109 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01110 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01111
01112 /* Non-Blocking mode: DMA */
01113 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01114 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01115 /**
01116   * @}
01117   */
01118
01119 /** @addtogroup TIMEx_Exported_Functions_Group3
01120  * @{
01121  */
01122 /*  Timer Complementary PWM functions  ****************************************/
01123 /* Blocking mode: Polling */
01124 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01125 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01126
01127 /* Non-Blocking mode: Interrupt */
01128 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01129 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01130 /* Non-Blocking mode: DMA */
01131 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01132 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01133 /**
01134   * @}
01135   */
01136
01137 /** @addtogroup TIMEx_Exported_Functions_Group4
01138  * @{
01139  */
01140 /*  Timer Complementary One Pulse functions  **********************************/
01141 /* Blocking mode: Polling */
01142 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01143 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01144
01145 /* Non-Blocking mode: Interrupt */
01146 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01147 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01148 /**
01149   * @}
01150   */
01151
01152 /** @addtogroup TIMEx_Exported_Functions_Group5
01153  * @{
01154  */
01155 /* Extended Control functions  ************************************************/
01156 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
01157 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
01158 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
01159 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
01160 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
01161
01162 #if defined(STM32F303xE) || defined(STM32F398xx) || \
01163     defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F334x8)
01164 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2);
01165 #endif /* STM32F303xE || STM32F398xx || */
01166        /* STM32F303xC || STM32F358xx    */
01167
01168 #if defined(STM32F302xE)                                                 || \
01169     defined(STM32F302xC)                                                 || \
01170     defined(STM32F303x8)  || defined(STM32F328xx) || \
01171     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
01172     defined(STM32F373xC) || defined(STM32F378xx)
01173 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
01174 #endif /* STM32F302xE                               || */
01175        /* STM32F302xC                               || */
01176        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
01177        /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
01178        /* STM32F373xC || STM32F378xx                   */
01179
01180 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
01181     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
01182     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
01183     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01184 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
01185 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
01186        /* STM32F302xC || STM32F303xC || STM32F358xx || */
01187        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
01188        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
01189 /**
01190   * @}
01191   */
01192
01193 /** @addtogroup TIMEx_Exported_Functions_Group6
01194   * @{
01195   */
01196 /* Extended Callback *********************************************************/
01197 void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
01198 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
01199 void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
01200 /**
01201   * @}
01202   */
01203
01204 /** @addtogroup TIMEx_Exported_Functions_Group7
01205   * @{
01206   */
01207 /* Extended Peripheral State functions  **************************************/
01208 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
01209 /**
01210   * @}
01211   */
01212
01213 /**
01214   * @}
01215   */
01216 /* End of exported functions -------------------------------------------------*/
01217
01218 /* Private functions----------------------------------------------------------*/
01219 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
01220   * @{
01221   */
01222 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
01223 /**
01224   * @}
01225   */
01226 /* End of private functions --------------------------------------------------*/
01227
01228 /**
01229   * @}
01230   */
01231
01232 /**
01233   * @}
01234   */
01235
01236 #ifdef __cplusplus
01237 }
01238 #endif
01239
01240
01241 #endif /* __STM32F3xx_HAL_TIM_EX_H */
01242
01243 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_tsc.c Source File

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stm32f3xx_hal_tsc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_tsc.c
00004   * @author  MCD Application Team
00005   * @brief   This file provides firmware functions to manage the following
00006   *          functionalities of the Touch Sensing Controller (TSC) peripheral:
00007   *           + Initialization and De-initialization
00008   *           + Channel IOs, Shield IOs and Sampling IOs configuration
00009   *           + Start and Stop an acquisition
00010   *           + Read acquisition result
00011   *           + Interrupts and flags management
00012   *
00013   @verbatim
00014 ================================================================================
00015                        ##### TSC specific features #####
00016 ================================================================================
00017   [..]
00018   (#) Proven and robust surface charge transfer acquisition principle
00019
00020   (#) Supports up to 3 capacitive sensing channels per group
00021
00022   (#) Capacitive sensing channels can be acquired in parallel offering a very good
00023       response time
00024
00025   (#) Spread spectrum feature to improve system robustness in noisy environments
00026
00027   (#) Full hardware management of the charge transfer acquisition sequence
00028
00029   (#) Programmable charge transfer frequency
00030
00031   (#) Programmable sampling capacitor I/O pin
00032
00033   (#) Programmable channel I/O pin
00034
00035   (#) Programmable max count value to avoid long acquisition when a channel is faulty
00036
00037   (#) Dedicated end of acquisition and max count error flags with interrupt capability
00038
00039   (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
00040       components
00041
00042   (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation
00043
00044
00045                           ##### How to use this driver #####
00046 ================================================================================
00047   [..]
00048     (#) Enable the TSC interface clock using __HAL_RCC_TSC_CLK_ENABLE() macro.
00049
00050     (#) GPIO pins configuration
00051       (++) Enable the clock for the TSC GPIOs using __HAL_RCC_GPIOx_CLK_ENABLE() macro.
00052       (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode,
00053            and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode
00054            using HAL_GPIO_Init() function.
00055
00056     (#) Interrupts configuration
00057       (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority()
00058            and HAL_NVIC_EnableIRQ() and function.
00059
00060     (#) TSC configuration
00061       (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function.
00062
00063
00064    *** Acquisition sequence ***
00065   ===================================
00066   [..]
00067     (+) Discharge all IOs using HAL_TSC_IODischarge() function.
00068     (+) Wait a certain time allowing a good discharge of all capacitors. This delay depends
00069         of the sampling capacitor and electrodes design.
00070     (+) Select the channel IOs to be acquired using HAL_TSC_IOConfig() function.
00071     (+) Launch the acquisition using either HAL_TSC_Start() or HAL_TSC_Start_IT() function.
00072         If the synchronized mode is selected, the acquisition will start as soon as the signal
00073         is received on the synchro pin.
00074     (+) Wait the end of acquisition using either HAL_TSC_PollForAcquisition() or
00075         HAL_TSC_GetState() function or using WFI instruction for example.
00076     (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function.
00077     (+) Read the acquisition value using HAL_TSC_GroupGetValue() function.
00078
00079   @endverbatim
00080   ******************************************************************************
00081   * @attention
00082   *
00083   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00084   *
00085   * Redistribution and use in source and binary forms, with or without modification,
00086   * are permitted provided that the following conditions are met:
00087   *   1. Redistributions of source code must retain the above copyright notice,
00088   *      this list of conditions and the following disclaimer.
00089   *   2. Redistributions in binary form must reproduce the above copyright notice,
00090   *      this list of conditions and the following disclaimer in the documentation
00091   *      and/or other materials provided with the distribution.
00092   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00093   *      may be used to endorse or promote products derived from this software
00094   *      without specific prior written permission.
00095   *
00096   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00097   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00098   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00099   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00100   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00101   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00102   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00103   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00104   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00105   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00106   *
00107   ******************************************************************************
00108   */
00109
00110 /*
00111   Addition Table:
00112     Table 1. IOs for the STM32F3xx devices
00113     +--------------------------------+
00114     |       IOs    |   TSC functions |
00115     |--------------|-----------------|
00116     |   PA0  (AF)  |   TSC_G1_IO1    |
00117     |   PA1  (AF)  |   TSC_G1_IO2    |
00118     |   PA2  (AF)  |   TSC_G1_IO3    |
00119     |   PA3  (AF)  |   TSC_G1_IO4    |
00120     |--------------|-----------------|
00121     |   PA4 (AF)   |   TSC_G2_IO1    |
00122     |   PA5 (AF)   |   TSC_G2_IO2    |
00123     |   PA6 (AF)   |   TSC_G2_IO3    |
00124     |   PA7 (AF)   |   TSC_G2_IO4    |
00125     |--------------|-----------------|
00126     |   PC5  (AF)  |   TSC_G3_IO1    |
00127     |   PB0  (AF)  |   TSC_G3_IO2    |
00128     |   PB1  (AF)  |   TSC_G3_IO3    |
00129     |   PB2  (AF)  |   TSC_G3_IO4    |
00130     |--------------|-----------------|
00131     |   PA9  (AF)  |   TSC_G4_IO1    |
00132     |   PA10 (AF)  |   TSC_G4_IO2    |
00133     |   PA13 (AF)  |   TSC_G4_IO3    |
00134     |   PA14 (AF)  |   TSC_G4_IO4    |
00135     |--------------|-----------------|
00136     |   PB3  (AF)  |   TSC_G5_IO1    |
00137     |   PB4  (AF)  |   TSC_G5_IO2    |
00138     |   PB6  (AF)  |   TSC_G5_IO3    |
00139     |   PB7  (AF)  |   TSC_G5_IO4    |
00140     |--------------|-----------------|
00141     |   PB11 (AF)  |   TSC_G6_IO1    |
00142     |   PB12 (AF)  |   TSC_G6_IO2    |
00143     |   PB13 (AF)  |   TSC_G6_IO3    |
00144     |   PB14 (AF)  |   TSC_G6_IO4    |
00145     |--------------|-----------------|
00146     |   PE2  (AF)  |   TSC_G7_IO1    |
00147     |   PE3  (AF)  |   TSC_G7_IO2    |
00148     |   PE4  (AF)  |   TSC_G7_IO3    |
00149     |   PE5  (AF)  |   TSC_G7_IO4    |
00150     |--------------|-----------------|
00151     |   PD12 (AF)  |   TSC_G8_IO1    |
00152     |   PD13 (AF)  |   TSC_G8_IO2    |
00153     |   PD14 (AF)  |   TSC_G8_IO3    |
00154     |   PD15 (AF)  |   TSC_G8_IO4    |
00155     |--------------|-----------------|
00156     |   PB8  (AF)  |   TSC_SYNC      |
00157     |   PB10 (AF)  |                 |
00158     +--------------------------------+
00159     TSC peripheral alternate functions are mapped on AF3.
00160
00161 */
00162
00163
00164 /* Includes ------------------------------------------------------------------*/
00165 #include "stm32f3xx_hal.h"
00166
00167 /** @addtogroup STM32F3xx_HAL_Driver
00168   * @{
00169   */
00170
00171 /** @defgroup TSC TSC
00172   * @brief HAL TSC module driver
00173   * @{
00174   */
00175
00176 #ifdef HAL_TSC_MODULE_ENABLED
00177
00178 /* Private typedef -----------------------------------------------------------*/
00179 /* Private define ------------------------------------------------------------*/
00180 /* Private macro -------------------------------------------------------------*/
00181 /* Private variables ---------------------------------------------------------*/
00182 /* Private function prototypes -----------------------------------------------*/
00183 static uint32_t TSC_extract_groups(uint32_t iomask);
00184
00185 /* Exported functions --------------------------------------------------------*/
00186
00187 /** @defgroup TSC_Exported_Functions Exported Functions
00188   * @{
00189   */
00190
00191 /** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
00192  *  @brief    Initialization and Configuration functions
00193  *
00194 @verbatim
00195  ===============================================================================
00196               ##### Initialization and de-initialization functions #####
00197  ===============================================================================
00198     [..]  This section provides functions allowing to:
00199       (+) Initialize and configure the TSC.
00200       (+) De-initialize the TSC.
00201 @endverbatim
00202   * @{
00203   */
00204
00205 /**
00206   * @brief  Initialize the TSC peripheral according to the specified parameters
00207   *         in the TSC_InitTypeDef structure and initialize the associated handle.
00208   * @param  htsc TSC handle
00209   * @retval HAL status
00210   */
00211 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc)
00212 {
00213   /* Check TSC handle allocation */
00214   if (htsc == NULL)
00215   {
00216     return HAL_ERROR;
00217   }
00218
00219   /* Check the parameters */
00220   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00221   assert_param(IS_TSC_CTPH(htsc->Init.CTPulseHighLength));
00222   assert_param(IS_TSC_CTPL(htsc->Init.CTPulseLowLength));
00223   assert_param(IS_TSC_SS(htsc->Init.SpreadSpectrum));
00224   assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation));
00225   assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler));
00226   assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler));
00227   assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue));
00228   assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode));
00229   assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
00230   assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode));
00231   assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
00232
00233   if(htsc->State == HAL_TSC_STATE_RESET)
00234   {
00235     /* Allocate lock resource and initialize it */
00236     htsc->Lock = HAL_UNLOCKED;
00237   }
00238
00239   /* Initialize the TSC state */
00240   htsc->State = HAL_TSC_STATE_BUSY;
00241
00242   /* Init the low level hardware : GPIO, CLOCK, CORTEX */
00243   HAL_TSC_MspInit(htsc);
00244
00245   /*--------------------------------------------------------------------------*/
00246   /* Set TSC parameters */
00247
00248   /* Enable TSC */
00249   htsc->Instance->CR = TSC_CR_TSCE;
00250
00251   /* Set all functions */
00252   htsc->Instance->CR |= (htsc->Init.CTPulseHighLength |
00253                          htsc->Init.CTPulseLowLength |
00254                          (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17U) |
00255                          htsc->Init.SpreadSpectrumPrescaler |
00256                          htsc->Init.PulseGeneratorPrescaler |
00257                          htsc->Init.MaxCountValue |
00258                          htsc->Init.SynchroPinPolarity |
00259                          htsc->Init.AcquisitionMode);
00260
00261   /* Spread spectrum */
00262   if (htsc->Init.SpreadSpectrum == ENABLE)
00263   {
00264     htsc->Instance->CR |= TSC_CR_SSE;
00265   }
00266
00267   /* Disable Schmitt trigger hysteresis on all used TSC IOs */
00268   htsc->Instance->IOHCR = (uint32_t)(~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs));
00269
00270   /* Set channel and shield IOs */
00271   htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs);
00272
00273   /* Set sampling IOs */
00274   htsc->Instance->IOSCR = htsc->Init.SamplingIOs;
00275
00276   /* Set the groups to be acquired */
00277   htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs);
00278
00279   /* Disable interrupts */
00280   htsc->Instance->IER &= (uint32_t)(~(TSC_IT_EOA | TSC_IT_MCE));
00281
00282   /* Clear flags */
00283   htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE);
00284
00285   /*--------------------------------------------------------------------------*/
00286
00287   /* Initialize the TSC state */
00288   htsc->State = HAL_TSC_STATE_READY;
00289
00290   /* Return function status */
00291   return HAL_OK;
00292 }
00293
00294 /**
00295   * @brief  Deinitialize the TSC peripheral registers to their default reset values.
00296   * @param  htsc TSC handle
00297   * @retval HAL status
00298   */
00299 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc)
00300 {
00301   /* Check TSC handle allocation */
00302   if (htsc == NULL)
00303   {
00304     return HAL_ERROR;
00305   }
00306
00307   /* Check the parameters */
00308   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00309
00310   /* Change TSC state */
00311   htsc->State = HAL_TSC_STATE_BUSY;
00312
00313   /* DeInit the low level hardware */
00314   HAL_TSC_MspDeInit(htsc);
00315
00316   /* Change TSC state */
00317   htsc->State = HAL_TSC_STATE_RESET;
00318
00319   /* Process unlocked */
00320   __HAL_UNLOCK(htsc);
00321
00322   /* Return function status */
00323   return HAL_OK;
00324 }
00325
00326 /**
00327   * @brief  Initialize the TSC MSP.
00328   * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
00329   *         the configuration information for the specified TSC.
00330   * @retval None
00331   */
00332 __weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc)
00333 {
00334   /* Prevent unused argument(s) compilation warning */
00335   UNUSED(htsc);
00336
00337   /* NOTE : This function should not be modified, when the callback is needed,
00338             the HAL_TSC_MspInit could be implemented in the user file.
00339    */
00340 }
00341
00342 /**
00343   * @brief  DeInitialize the TSC MSP.
00344   * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
00345   *         the configuration information for the specified TSC.
00346   * @retval None
00347   */
00348 __weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc)
00349 {
00350   /* Prevent unused argument(s) compilation warning */
00351   UNUSED(htsc);
00352
00353   /* NOTE : This function should not be modified, when the callback is needed,
00354             the HAL_TSC_MspDeInit could be implemented in the user file.
00355    */
00356 }
00357
00358 /**
00359   * @}
00360   */
00361
00362 /** @defgroup TSC_Exported_Functions_Group2 Input and Output operation functions
00363  *  @brief    Input and Output operation functions
00364  *
00365 @verbatim
00366  ===============================================================================
00367              ##### IO Operation functions #####
00368  ===============================================================================
00369     [..]  This section provides functions allowing to:
00370       (+) Start acquisition in polling mode.
00371       (+) Start acquisition in interrupt mode.
00372       (+) Stop conversion in polling mode.
00373       (+) Stop conversion in interrupt mode.
00374       (+) Poll for acquisition completed.
00375       (+) Get group acquisition status.
00376       (+) Get group acquisition value.
00377 @endverbatim
00378   * @{
00379   */
00380
00381 /**
00382   * @brief  Start the acquisition.
00383   * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
00384   *         the configuration information for the specified TSC.
00385   * @retval HAL status
00386   */
00387 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc)
00388 {
00389   /* Check the parameters */
00390   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00391
00392   /* Process locked */
00393   __HAL_LOCK(htsc);
00394
00395   /* Change TSC state */
00396   htsc->State = HAL_TSC_STATE_BUSY;
00397
00398   /* Clear interrupts */
00399   __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
00400
00401   /* Clear flags */
00402   __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
00403
00404   /* Set touch sensing IOs not acquired to the specified IODefaultMode */
00405   if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
00406   {
00407     __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
00408   }
00409   else
00410   {
00411     __HAL_TSC_SET_IODEF_INFLOAT(htsc);
00412   }
00413
00414   /* Launch the acquisition */
00415   __HAL_TSC_START_ACQ(htsc);
00416
00417   /* Process unlocked */
00418   __HAL_UNLOCK(htsc);
00419
00420   /* Return function status */
00421   return HAL_OK;
00422 }
00423
00424 /**
00425   * @brief  Start the acquisition in interrupt mode.
00426   * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
00427   *         the configuration information for the specified TSC.
00428   * @retval HAL status.
00429   */
00430 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc)
00431 {
00432   /* Check the parameters */
00433   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00434   assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
00435
00436   /* Process locked */
00437   __HAL_LOCK(htsc);
00438
00439   /* Change TSC state */
00440   htsc->State = HAL_TSC_STATE_BUSY;
00441
00442   /* Enable end of acquisition interrupt */
00443   __HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA);
00444
00445   /* Enable max count error interrupt (optional) */
00446   if (htsc->Init.MaxCountInterrupt == ENABLE)
00447   {
00448     __HAL_TSC_ENABLE_IT(htsc, TSC_IT_MCE);
00449   }
00450   else
00451   {
00452     __HAL_TSC_DISABLE_IT(htsc, TSC_IT_MCE);
00453   }
00454
00455   /* Clear flags */
00456   __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
00457
00458   /* Set touch sensing IOs not acquired to the specified IODefaultMode */
00459   if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
00460   {
00461     __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
00462   }
00463   else
00464   {
00465     __HAL_TSC_SET_IODEF_INFLOAT(htsc);
00466   }
00467
00468   /* Launch the acquisition */
00469   __HAL_TSC_START_ACQ(htsc);
00470
00471   /* Process unlocked */
00472   __HAL_UNLOCK(htsc);
00473
00474   /* Return function status */
00475   return HAL_OK;
00476 }
00477
00478 /**
00479   * @brief  Stop the acquisition previously launched in polling mode.
00480   * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
00481   *         the configuration information for the specified TSC.
00482   * @retval HAL status
00483   */
00484 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc)
00485 {
00486   /* Check the parameters */
00487   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00488
00489   /* Process locked */
00490   __HAL_LOCK(htsc);
00491
00492   /* Stop the acquisition */
00493   __HAL_TSC_STOP_ACQ(htsc);
00494
00495   /* Set touch sensing IOs in low power mode (output push-pull) */
00496   __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
00497
00498   /* Clear flags */
00499   __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
00500
00501   /* Change TSC state */
00502   htsc->State = HAL_TSC_STATE_READY;
00503
00504   /* Process unlocked */
00505   __HAL_UNLOCK(htsc);
00506
00507   /* Return function status */
00508   return HAL_OK;
00509 }
00510
00511 /**
00512   * @brief  Stop the acquisition previously launched in interrupt mode.
00513   * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
00514   *         the configuration information for the specified TSC.
00515   * @retval HAL status
00516   */
00517 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc)
00518 {
00519   /* Check the parameters */
00520   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00521
00522   /* Process locked */
00523   __HAL_LOCK(htsc);
00524
00525   /* Stop the acquisition */
00526   __HAL_TSC_STOP_ACQ(htsc);
00527
00528   /* Set touch sensing IOs in low power mode (output push-pull) */
00529   __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
00530
00531   /* Disable interrupts */
00532   __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
00533
00534   /* Clear flags */
00535   __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
00536
00537   /* Change TSC state */
00538   htsc->State = HAL_TSC_STATE_READY;
00539
00540   /* Process unlocked */
00541   __HAL_UNLOCK(htsc);
00542
00543   /* Return function status */
00544   return HAL_OK;
00545 }
00546
00547 /**
00548   * @brief  Start acquisition and wait until completion.
00549   * @note   There is no need of a timeout parameter as the max count error is already
00550   *         managed by the TSC peripheral.
00551   * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
00552   *         the configuration information for the specified TSC.
00553   * @retval HAL state
00554   */
00555 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc)
00556 {
00557   /* Check the parameters */
00558   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00559
00560   /* Process locked */
00561   __HAL_LOCK(htsc);
00562
00563   /* Check end of acquisition */
00564   while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY)
00565   {
00566     /* The timeout (max count error) is managed by the TSC peripheral itself. */
00567   }
00568
00569   /* Process unlocked */
00570   __HAL_UNLOCK(htsc);
00571
00572   return HAL_OK;
00573 }
00574
00575 /**
00576   * @brief  Get the acquisition status for a group.
00577   * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
00578   *         the configuration information for the specified TSC.
00579   * @param  gx_index Index of the group
00580   * @retval Group status
00581   */
00582 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index)
00583 {
00584   /* Check the parameters */
00585   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00586   assert_param(IS_TSC_GROUP_INDEX(gx_index));
00587
00588   /* Return the group status */
00589   return(__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index));
00590 }
00591
00592 /**
00593   * @brief  Get the acquisition measure for a group.
00594   * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
00595   *         the configuration information for the specified TSC.
00596   * @param  gx_index Index of the group
00597   * @retval Acquisition measure
00598   */
00599 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index)
00600 {
00601   /* Check the parameters */
00602   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00603   assert_param(IS_TSC_GROUP_INDEX(gx_index));
00604
00605   /* Return the group acquisition counter */
00606   return htsc->Instance->IOGXCR[gx_index];
00607 }
00608
00609 /**
00610   * @}
00611   */
00612
00613 /** @defgroup TSC_Exported_Functions_Group3 Peripheral Control functions
00614  *  @brief    Peripheral Control functions
00615  *
00616 @verbatim
00617  ===============================================================================
00618              ##### Peripheral Control functions #####
00619  ===============================================================================
00620     [..]  This section provides functions allowing to:
00621       (+) Configure TSC IOs
00622       (+) Discharge TSC IOs
00623 @endverbatim
00624   * @{
00625   */
00626
00627 /**
00628   * @brief  Configure TSC IOs.
00629   * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
00630   *         the configuration information for the specified TSC.
00631   * @param  config pointer to the configuration structure.
00632   * @retval HAL status
00633   */
00634 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config)
00635 {
00636   /* Check the parameters */
00637   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00638
00639   /* Process locked */
00640   __HAL_LOCK(htsc);
00641
00642   /* Stop acquisition */
00643   __HAL_TSC_STOP_ACQ(htsc);
00644
00645   /* Disable Schmitt trigger hysteresis on all used TSC IOs */
00646   htsc->Instance->IOHCR = (uint32_t)(~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs));
00647
00648   /* Set channel and shield IOs */
00649   htsc->Instance->IOCCR = (config->ChannelIOs | config->ShieldIOs);
00650
00651   /* Set sampling IOs */
00652   htsc->Instance->IOSCR = config->SamplingIOs;
00653
00654   /* Set groups to be acquired */
00655   htsc->Instance->IOGCSR = TSC_extract_groups(config->ChannelIOs);
00656
00657   /* Process unlocked */
00658   __HAL_UNLOCK(htsc);
00659
00660   /* Return function status */
00661   return HAL_OK;
00662 }
00663
00664 /**
00665   * @brief  Discharge TSC IOs.
00666   * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
00667   *         the configuration information for the specified TSC.
00668   * @param  choice enable or disable
00669   * @retval HAL status
00670   */
00671 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice)
00672 {
00673   /* Check the parameters */
00674   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00675
00676   /* Process locked */
00677   __HAL_LOCK(htsc);
00678
00679   if (choice == ENABLE)
00680   {
00681     __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
00682   }
00683   else
00684   {
00685     __HAL_TSC_SET_IODEF_INFLOAT(htsc);
00686   }
00687
00688   /* Process unlocked */
00689   __HAL_UNLOCK(htsc);
00690
00691   /* Return the group acquisition counter */
00692   return HAL_OK;
00693 }
00694
00695 /**
00696   * @}
00697   */
00698
00699 /** @defgroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
00700  *  @brief   Peripheral State and Errors functions
00701  *
00702 @verbatim
00703  ===============================================================================
00704             ##### State and Errors functions #####
00705  ===============================================================================
00706     [..]
00707     This subsection provides functions allowing to
00708       (+) Get TSC state.
00709
00710 @endverbatim
00711   * @{
00712   */
00713
00714 /**
00715   * @brief  Return the TSC handle state.
00716   * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
00717   *         the configuration information for the specified TSC.
00718   * @retval HAL state
00719   */
00720 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc)
00721 {
00722   /* Check the parameters */
00723   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00724
00725   if (htsc->State == HAL_TSC_STATE_BUSY)
00726   {
00727     /* Check end of acquisition flag */
00728     if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
00729     {
00730       /* Check max count error flag */
00731       if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
00732       {
00733         /* Change TSC state */
00734         htsc->State = HAL_TSC_STATE_ERROR;
00735       }
00736       else
00737       {
00738         /* Change TSC state */
00739         htsc->State = HAL_TSC_STATE_READY;
00740       }
00741     }
00742   }
00743
00744   /* Return TSC state */
00745   return htsc->State;
00746 }
00747
00748 /**
00749   * @}
00750   */
00751
00752 /** @defgroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00753  * @{
00754  */
00755
00756 /**
00757   * @brief  Handle TSC interrupt request.
00758   * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
00759   *         the configuration information for the specified TSC.
00760   * @retval None
00761   */
00762 void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc)
00763 {
00764   /* Check the parameters */
00765   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00766
00767   /* Check if the end of acquisition occurred */
00768   if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
00769   {
00770     /* Clear EOA flag */
00771     __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA);
00772   }
00773
00774   /* Check if max count error occurred */
00775   if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
00776   {
00777     /* Clear MCE flag */
00778     __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE);
00779     /* Change TSC state */
00780     htsc->State = HAL_TSC_STATE_ERROR;
00781     /* Conversion completed callback */
00782     HAL_TSC_ErrorCallback(htsc);
00783   }
00784   else
00785   {
00786     /* Change TSC state */
00787     htsc->State = HAL_TSC_STATE_READY;
00788     /* Conversion completed callback */
00789     HAL_TSC_ConvCpltCallback(htsc);
00790   }
00791 }
00792
00793 /**
00794   * @brief  Acquisition completed callback in non-blocking mode.
00795   * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
00796   *         the configuration information for the specified TSC.
00797   * @retval None
00798   */
00799 __weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc)
00800 {
00801   /* Prevent unused argument(s) compilation warning */
00802   UNUSED(htsc);
00803
00804   /* NOTE : This function should not be modified, when the callback is needed,
00805             the HAL_TSC_ConvCpltCallback could be implemented in the user file.
00806    */
00807 }
00808
00809 /**
00810   * @brief  Error callback in non-blocking mode.
00811   * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
00812   *         the configuration information for the specified TSC.
00813   * @retval None
00814   */
00815 __weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc)
00816 {
00817   /* Prevent unused argument(s) compilation warning */
00818   UNUSED(htsc);
00819
00820   /* NOTE : This function should not be modified, when the callback is needed,
00821             the HAL_TSC_ErrorCallback could be implemented in the user file.
00822    */
00823 }
00824
00825 /**
00826   * @}
00827   */
00828
00829 /**
00830   * @}
00831   */
00832
00833 /* Private functions ---------------------------------------------------------*/
00834 /** @defgroup TSC_Private_Functions Private Functions
00835  *  @{
00836  */
00837
00838 /**
00839   * @brief  Utility function used to set the acquired groups mask.
00840   * @param  iomask Channels IOs mask
00841   * @retval Acquired groups mask
00842   */
00843 static uint32_t TSC_extract_groups(uint32_t iomask)
00844 {
00845   uint32_t groups = 0U;
00846   uint32_t idx;
00847
00848   for (idx = 0U; idx < TSC_NB_OF_GROUPS; idx++)
00849   {
00850     if ((iomask & (0x0FU << (idx * 4U))) != RESET)
00851     {
00852       groups |= (1U << idx);
00853     }
00854   }
00855
00856   return groups;
00857 }
00858
00859 /**
00860   * @}
00861   */
00862
00863 #endif /* HAL_TSC_MODULE_ENABLED */
00864
00865 /**
00866   * @}
00867   */
00868
00869 /**
00870   * @}
00871   */
00872
00873 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_tsc.h Source File

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stm32f3xx_hal_tsc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_tsc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TSC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_TSC_H
00038 #define __STM32F3xx_HAL_TSC_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup TSC
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /** @defgroup TSC_Exported_Types TSC Exported Types
00057   * @{
00058   */
00059
00060 /**
00061   * @brief TSC state structure definition
00062   */
00063 typedef enum
00064 {
00065   HAL_TSC_STATE_RESET  = 0x00U, /*!< TSC registers have their reset value */
00066   HAL_TSC_STATE_READY  = 0x01U, /*!< TSC registers are initialized or acquisition is completed with success */
00067   HAL_TSC_STATE_BUSY   = 0x02U, /*!< TSC initialization or acquisition is on-going */
00068   HAL_TSC_STATE_ERROR  = 0x03U  /*!< Acquisition is completed with max count error */
00069 } HAL_TSC_StateTypeDef;
00070
00071 /**
00072   * @brief TSC group status structure definition
00073   */
00074 typedef enum
00075 {
00076   TSC_GROUP_ONGOING   = 0x00U, /*!< Acquisition on group is on-going or not started */
00077   TSC_GROUP_COMPLETED = 0x01U  /*!< Acquisition on group is completed with success (no max count error) */
00078 } TSC_GroupStatusTypeDef;
00079
00080 /**
00081   * @brief TSC init structure definition
00082   */
00083 typedef struct
00084 {
00085   uint32_t CTPulseHighLength;       /*!< Charge-transfer high pulse length
00086                                          This parameter can be a value of @ref TSC_CTPulseHL_Config  */
00087   uint32_t CTPulseLowLength;        /*!< Charge-transfer low pulse length
00088                                          This parameter can be a value of @ref TSC_CTPulseLL_Config  */
00089   uint32_t SpreadSpectrum;          /*!< Spread spectrum activation
00090                                          This parameter can be a value of @ref TSC_CTPulseLL_Config  */
00091   uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation
00092                                          This parameter must be a number between Min_Data = 0 and Max_Data = 127U */
00093   uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler
00094                                          This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */
00095   uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler
00096                                          This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */
00097   uint32_t MaxCountValue;           /*!< Max count value
00098                                          This parameter can be a value of @ref TSC_MaxCount_Value  */
00099   uint32_t IODefaultMode;           /*!< IO default mode
00100                                          This parameter can be a value of @ref TSC_IO_Default_Mode  */
00101   uint32_t SynchroPinPolarity;      /*!< Synchro pin polarity
00102                                          This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */
00103   uint32_t AcquisitionMode;         /*!< Acquisition mode
00104                                          This parameter can be a value of @ref TSC_Acquisition_Mode  */
00105   uint32_t MaxCountInterrupt;       /*!< Max count interrupt activation
00106                                          This parameter can be set to ENABLE or DISABLE. */
00107   uint32_t ChannelIOs;              /*!< Channel IOs mask */
00108   uint32_t ShieldIOs;               /*!< Shield IOs mask */
00109   uint32_t SamplingIOs;             /*!< Sampling IOs mask */
00110 } TSC_InitTypeDef;
00111
00112 /**
00113   * @brief TSC IOs configuration structure definition
00114   */
00115 typedef struct
00116 {
00117   uint32_t ChannelIOs;  /*!< Channel IOs mask */
00118   uint32_t ShieldIOs;   /*!< Shield IOs mask */
00119   uint32_t SamplingIOs; /*!< Sampling IOs mask */
00120 } TSC_IOConfigTypeDef;
00121
00122 /**
00123   * @brief  TSC handle Structure definition
00124   */
00125 typedef struct
00126 {
00127   TSC_TypeDef               *Instance; /*!< Register base address */
00128   TSC_InitTypeDef           Init;      /*!< Initialization parameters */
00129   __IO HAL_TSC_StateTypeDef State;     /*!< Peripheral state */
00130   HAL_LockTypeDef           Lock;      /*!< Lock feature */
00131 } TSC_HandleTypeDef;
00132
00133 /**
00134   * @}
00135   */
00136
00137 /* Exported constants --------------------------------------------------------*/
00138 /** @defgroup TSC_Exported_Constants TSC Exported Constants
00139   * @{
00140   */
00141
00142 /** @defgroup TSC_CTPulseHL_Config CTPulse High Length
00143   * @{
00144   */
00145 #define TSC_CTPH_1CYCLE   ((uint32_t)( 0U << 28U))
00146 #define TSC_CTPH_2CYCLES  ((uint32_t)( 1U << 28U))
00147 #define TSC_CTPH_3CYCLES  ((uint32_t)( 2U << 28U))
00148 #define TSC_CTPH_4CYCLES  ((uint32_t)( 3U << 28U))
00149 #define TSC_CTPH_5CYCLES  ((uint32_t)( 4U << 28U))
00150 #define TSC_CTPH_6CYCLES  ((uint32_t)( 5U << 28U))
00151 #define TSC_CTPH_7CYCLES  ((uint32_t)( 6U << 28U))
00152 #define TSC_CTPH_8CYCLES  ((uint32_t)( 7U << 28U))
00153 #define TSC_CTPH_9CYCLES  ((uint32_t)( 8U << 28U))
00154 #define TSC_CTPH_10CYCLES ((uint32_t)( 9U << 28U))
00155 #define TSC_CTPH_11CYCLES ((uint32_t)(10U << 28U))
00156 #define TSC_CTPH_12CYCLES ((uint32_t)(11U << 28U))
00157 #define TSC_CTPH_13CYCLES ((uint32_t)(12U << 28U))
00158 #define TSC_CTPH_14CYCLES ((uint32_t)(13U << 28U))
00159 #define TSC_CTPH_15CYCLES ((uint32_t)(14U << 28U))
00160 #define TSC_CTPH_16CYCLES ((uint32_t)(15U << 28U))
00161 /**
00162   * @}
00163   */
00164
00165 /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
00166   * @{
00167   */
00168 #define TSC_CTPL_1CYCLE   ((uint32_t)( 0U << 24U))
00169 #define TSC_CTPL_2CYCLES  ((uint32_t)( 1U << 24U))
00170 #define TSC_CTPL_3CYCLES  ((uint32_t)( 2U << 24U))
00171 #define TSC_CTPL_4CYCLES  ((uint32_t)( 3U << 24U))
00172 #define TSC_CTPL_5CYCLES  ((uint32_t)( 4U << 24U))
00173 #define TSC_CTPL_6CYCLES  ((uint32_t)( 5U << 24U))
00174 #define TSC_CTPL_7CYCLES  ((uint32_t)( 6U << 24U))
00175 #define TSC_CTPL_8CYCLES  ((uint32_t)( 7U << 24U))
00176 #define TSC_CTPL_9CYCLES  ((uint32_t)( 8U << 24U))
00177 #define TSC_CTPL_10CYCLES ((uint32_t)( 9U << 24U))
00178 #define TSC_CTPL_11CYCLES ((uint32_t)(10U << 24U))
00179 #define TSC_CTPL_12CYCLES ((uint32_t)(11U << 24U))
00180 #define TSC_CTPL_13CYCLES ((uint32_t)(12U << 24U))
00181 #define TSC_CTPL_14CYCLES ((uint32_t)(13U << 24U))
00182 #define TSC_CTPL_15CYCLES ((uint32_t)(14U << 24U))
00183 #define TSC_CTPL_16CYCLES ((uint32_t)(15U << 24U))
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler
00189   * @{
00190   */
00191 #define TSC_SS_PRESC_DIV1 (0U)
00192 #define TSC_SS_PRESC_DIV2  (TSC_CR_SSPSC)
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler
00198   * @{
00199   */
00200 #define TSC_PG_PRESC_DIV1   ((uint32_t)(0U << 12U))
00201 #define TSC_PG_PRESC_DIV2   ((uint32_t)(1U << 12U))
00202 #define TSC_PG_PRESC_DIV4   ((uint32_t)(2U << 12U))
00203 #define TSC_PG_PRESC_DIV8   ((uint32_t)(3U << 12U))
00204 #define TSC_PG_PRESC_DIV16  ((uint32_t)(4U << 12U))
00205 #define TSC_PG_PRESC_DIV32  ((uint32_t)(5U << 12U))
00206 #define TSC_PG_PRESC_DIV64  ((uint32_t)(6U << 12U))
00207 #define TSC_PG_PRESC_DIV128 ((uint32_t)(7U << 12U))
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup TSC_MaxCount_Value Max Count Value
00213   * @{
00214   */
00215 #define TSC_MCV_255   ((uint32_t)(0U << 5U))
00216 #define TSC_MCV_511   ((uint32_t)(1U << 5U))
00217 #define TSC_MCV_1023  ((uint32_t)(2U << 5U))
00218 #define TSC_MCV_2047  ((uint32_t)(3U << 5U))
00219 #define TSC_MCV_4095  ((uint32_t)(4U << 5U))
00220 #define TSC_MCV_8191  ((uint32_t)(5U << 5U))
00221 #define TSC_MCV_16383 ((uint32_t)(6U << 5U))
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup TSC_IO_Default_Mode IO Default Mode
00227   * @{
00228   */
00229 #define TSC_IODEF_OUT_PP_LOW (0U)
00230 #define TSC_IODEF_IN_FLOAT   (TSC_CR_IODEF)
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity
00236   * @{
00237   */
00238 #define TSC_SYNC_POLARITY_FALLING      (0U)
00239 #define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup TSC_Acquisition_Mode Acquisition Mode
00245   * @{
00246   */
00247 #define TSC_ACQ_MODE_NORMAL  (0U)
00248 #define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup TSC_IO_Mode IO Mode
00254   * @{
00255   */
00256 #define TSC_IOMODE_UNUSED   (0U)
00257 #define TSC_IOMODE_CHANNEL  (1U)
00258 #define TSC_IOMODE_SHIELD   (2U)
00259 #define TSC_IOMODE_SAMPLING (3U)
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup TSC_interrupts_definition Interrupts definition
00265   * @{
00266   */
00267 #define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
00268 #define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup TSC_flags_definition Flags definition
00274   * @{
00275   */
00276 #define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
00277 #define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup TSC_Group_definition Group definition
00283   * @{
00284   */
00285 #define TSC_NB_OF_GROUPS (8U)
00286
00287 #define TSC_GROUP1 (0x00000001U)
00288 #define TSC_GROUP2 (0x00000002U)
00289 #define TSC_GROUP3 (0x00000004U)
00290 #define TSC_GROUP4 (0x00000008U)
00291 #define TSC_GROUP5 (0x00000010U)
00292 #define TSC_GROUP6 (0x00000020U)
00293 #define TSC_GROUP7 (0x00000040U)
00294 #define TSC_GROUP8 (0x00000080U)
00295 #define TSC_ALL_GROUPS (0x000000FFU)
00296
00297 #define TSC_GROUP1_IDX (0U)
00298 #define TSC_GROUP2_IDX (1U)
00299 #define TSC_GROUP3_IDX (2U)
00300 #define TSC_GROUP4_IDX (3U)
00301 #define TSC_GROUP5_IDX (4U)
00302 #define TSC_GROUP6_IDX (5U)
00303 #define TSC_GROUP7_IDX (6U)
00304 #define TSC_GROUP8_IDX (7U)
00305
00306 #define TSC_GROUP1_IO1 (0x00000001U)
00307 #define TSC_GROUP1_IO2 (0x00000002U)
00308 #define TSC_GROUP1_IO3 (0x00000004U)
00309 #define TSC_GROUP1_IO4 (0x00000008U)
00310 #define TSC_GROUP1_ALL_IOS (0x0000000FU)
00311
00312 #define TSC_GROUP2_IO1 (0x00000010U)
00313 #define TSC_GROUP2_IO2 (0x00000020U)
00314 #define TSC_GROUP2_IO3 (0x00000040U)
00315 #define TSC_GROUP2_IO4 (0x00000080U)
00316 #define TSC_GROUP2_ALL_IOS (0x000000F0U)
00317
00318 #define TSC_GROUP3_IO1 (0x00000100U)
00319 #define TSC_GROUP3_IO2 (0x00000200U)
00320 #define TSC_GROUP3_IO3 (0x00000400U)
00321 #define TSC_GROUP3_IO4 (0x00000800U)
00322 #define TSC_GROUP3_ALL_IOS (0x00000F00U)
00323
00324 #define TSC_GROUP4_IO1 (0x00001000U)
00325 #define TSC_GROUP4_IO2 (0x00002000U)
00326 #define TSC_GROUP4_IO3 (0x00004000U)
00327 #define TSC_GROUP4_IO4 (0x00008000U)
00328 #define TSC_GROUP4_ALL_IOS (0x0000F000U)
00329
00330 #define TSC_GROUP5_IO1 (0x00010000U)
00331 #define TSC_GROUP5_IO2 (0x00020000U)
00332 #define TSC_GROUP5_IO3 (0x00040000U)
00333 #define TSC_GROUP5_IO4 (0x00080000U)
00334 #define TSC_GROUP5_ALL_IOS (0x000F0000U)
00335
00336 #define TSC_GROUP6_IO1 (0x00100000U)
00337 #define TSC_GROUP6_IO2 (0x00200000U)
00338 #define TSC_GROUP6_IO3 (0x00400000U)
00339 #define TSC_GROUP6_IO4 (0x00800000U)
00340 #define TSC_GROUP6_ALL_IOS (0x00F00000U)
00341
00342 #define TSC_GROUP7_IO1 (0x01000000U)
00343 #define TSC_GROUP7_IO2 (0x02000000U)
00344 #define TSC_GROUP7_IO3 (0x04000000U)
00345 #define TSC_GROUP7_IO4 (0x08000000U)
00346 #define TSC_GROUP7_ALL_IOS (0x0F000000U)
00347
00348 #define TSC_GROUP8_IO1 (0x10000000U)
00349 #define TSC_GROUP8_IO2 (0x20000000U)
00350 #define TSC_GROUP8_IO3 (0x40000000U)
00351 #define TSC_GROUP8_IO4 (0x80000000U)
00352 #define TSC_GROUP8_ALL_IOS (0xF0000000U)
00353
00354 #define TSC_ALL_GROUPS_ALL_IOS (0xFFFFFFFFU)
00355 /**
00356   * @}
00357   */
00358
00359 /**
00360   * @}
00361   */
00362
00363 /* Exported macros -----------------------------------------------------------*/
00364
00365 /** @defgroup TSC_Exported_Macros TSC Exported Macros
00366  * @{
00367  */
00368
00369 /** @brief Reset TSC handle state.
00370   * @param  __HANDLE__ TSC handle
00371   * @retval None
00372   */
00373 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
00374
00375 /**
00376   * @brief Enable the TSC peripheral.
00377   * @param  __HANDLE__ TSC handle
00378   * @retval None
00379   */
00380 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
00381
00382 /**
00383   * @brief Disable the TSC peripheral.
00384   * @param  __HANDLE__ TSC handle
00385   * @retval None
00386   */
00387 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
00388
00389 /**
00390   * @brief Start acquisition.
00391   * @param  __HANDLE__ TSC handle
00392   * @retval None
00393   */
00394 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
00395
00396 /**
00397   * @brief Stop acquisition.
00398   * @param  __HANDLE__ TSC handle
00399   * @retval None
00400   */
00401 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
00402
00403 /**
00404   * @brief Set IO default mode to output push-pull low.
00405   * @param  __HANDLE__ TSC handle
00406   * @retval None
00407   */
00408 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
00409
00410 /**
00411   * @brief Set IO default mode to input floating.
00412   * @param  __HANDLE__ TSC handle
00413   * @retval None
00414   */
00415 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
00416
00417 /**
00418   * @brief Set synchronization polarity to falling edge.
00419   * @param  __HANDLE__ TSC handle
00420   * @retval None
00421   */
00422 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
00423
00424 /**
00425   * @brief Set synchronization polarity to rising edge and high level.
00426   * @param  __HANDLE__ TSC handle
00427   * @retval None
00428   */
00429 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
00430
00431 /**
00432   * @brief Enable TSC interrupt.
00433   * @param  __HANDLE__ TSC handle
00434   * @param  __INTERRUPT__ TSC interrupt
00435   * @retval None
00436   */
00437 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00438
00439 /**
00440   * @brief Disable TSC interrupt.
00441   * @param  __HANDLE__ TSC handle
00442   * @param  __INTERRUPT__ TSC interrupt
00443   * @retval None
00444   */
00445 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
00446
00447 /** @brief Check whether the specified TSC interrupt source is enabled or not.
00448   * @param  __HANDLE__ TSC Handle
00449   * @param  __INTERRUPT__ TSC interrupt
00450   * @retval SET or RESET
00451   */
00452 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00453
00454 /**
00455   * @brief Check whether the specified TSC flag is set or not.
00456   * @param  __HANDLE__ TSC handle
00457   * @param  __FLAG__ TSC flag
00458   * @retval SET or RESET
00459   */
00460 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
00461
00462 /**
00463   * @brief Clear the TSC's pending flag.
00464   * @param  __HANDLE__ TSC handle
00465   * @param  __FLAG__ TSC flag
00466   * @retval None
00467   */
00468 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00469
00470 /**
00471   * @brief Enable schmitt trigger hysteresis on a group of IOs.
00472   * @param  __HANDLE__ TSC handle
00473   * @param  __GX_IOY_MASK__ IOs mask
00474   * @retval None
00475   */
00476 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
00477
00478 /**
00479   * @brief Disable schmitt trigger hysteresis on a group of IOs.
00480   * @param  __HANDLE__ TSC handle
00481   * @param  __GX_IOY_MASK__ IOs mask
00482   * @retval None
00483   */
00484 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
00485
00486 /**
00487   * @brief Open analog switch on a group of IOs.
00488   * @param  __HANDLE__ TSC handle
00489   * @param  __GX_IOY_MASK__ IOs mask
00490   * @retval None
00491   */
00492 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
00493
00494 /**
00495   * @brief Close analog switch on a group of IOs.
00496   * @param  __HANDLE__ TSC handle
00497   * @param  __GX_IOY_MASK__ IOs mask
00498   * @retval None
00499   */
00500 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
00501
00502 /**
00503   * @brief Enable a group of IOs in channel mode.
00504   * @param  __HANDLE__ TSC handle
00505   * @param  __GX_IOY_MASK__ IOs mask
00506   * @retval None
00507   */
00508 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
00509
00510 /**
00511   * @brief Disable a group of channel IOs.
00512   * @param  __HANDLE__ TSC handle
00513   * @param  __GX_IOY_MASK__ IOs mask
00514   * @retval None
00515   */
00516 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
00517
00518 /**
00519   * @brief Enable a group of IOs in sampling mode.
00520   * @param  __HANDLE__ TSC handle
00521   * @param  __GX_IOY_MASK__ IOs mask
00522   * @retval None
00523   */
00524 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
00525
00526 /**
00527   * @brief Disable a group of sampling IOs.
00528   * @param  __HANDLE__ TSC handle
00529   * @param  __GX_IOY_MASK__ IOs mask
00530   * @retval None
00531   */
00532 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
00533
00534 /**
00535   * @brief Enable acquisition groups.
00536   * @param  __HANDLE__ TSC handle
00537   * @param  __GX_MASK__ Groups mask
00538   * @retval None
00539   */
00540 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
00541
00542 /**
00543   * @brief Disable acquisition groups.
00544   * @param  __HANDLE__ TSC handle
00545   * @param  __GX_MASK__ Groups mask
00546   * @retval None
00547   */
00548 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
00549
00550 /** @brief Gets acquisition group status.
00551   * @param  __HANDLE__ TSC Handle
00552   * @param  __GX_INDEX__ Group index
00553   * @retval SET or RESET
00554   */
00555 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
00556 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) == (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
00557
00558 /**
00559   * @}
00560   */
00561
00562 /* Private macros ------------------------------------------------------------*/
00563
00564 /** @defgroup TSC_Private_Macros TSC Private Macros
00565   * @{
00566   */
00567
00568 #define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
00569                           ((VAL) == TSC_CTPH_2CYCLES) || \
00570                           ((VAL) == TSC_CTPH_3CYCLES) || \
00571                           ((VAL) == TSC_CTPH_4CYCLES) || \
00572                           ((VAL) == TSC_CTPH_5CYCLES) || \
00573                           ((VAL) == TSC_CTPH_6CYCLES) || \
00574                           ((VAL) == TSC_CTPH_7CYCLES) || \
00575                           ((VAL) == TSC_CTPH_8CYCLES) || \
00576                           ((VAL) == TSC_CTPH_9CYCLES) || \
00577                           ((VAL) == TSC_CTPH_10CYCLES) || \
00578                           ((VAL) == TSC_CTPH_11CYCLES) || \
00579                           ((VAL) == TSC_CTPH_12CYCLES) || \
00580                           ((VAL) == TSC_CTPH_13CYCLES) || \
00581                           ((VAL) == TSC_CTPH_14CYCLES) || \
00582                           ((VAL) == TSC_CTPH_15CYCLES) || \
00583                           ((VAL) == TSC_CTPH_16CYCLES))
00584
00585 #define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
00586                           ((VAL) == TSC_CTPL_2CYCLES) || \
00587                           ((VAL) == TSC_CTPL_3CYCLES) || \
00588                           ((VAL) == TSC_CTPL_4CYCLES) || \
00589                           ((VAL) == TSC_CTPL_5CYCLES) || \
00590                           ((VAL) == TSC_CTPL_6CYCLES) || \
00591                           ((VAL) == TSC_CTPL_7CYCLES) || \
00592                           ((VAL) == TSC_CTPL_8CYCLES) || \
00593                           ((VAL) == TSC_CTPL_9CYCLES) || \
00594                           ((VAL) == TSC_CTPL_10CYCLES) || \
00595                           ((VAL) == TSC_CTPL_11CYCLES) || \
00596                           ((VAL) == TSC_CTPL_12CYCLES) || \
00597                           ((VAL) == TSC_CTPL_13CYCLES) || \
00598                           ((VAL) == TSC_CTPL_14CYCLES) || \
00599                           ((VAL) == TSC_CTPL_15CYCLES) || \
00600                           ((VAL) == TSC_CTPL_16CYCLES))
00601
00602 #define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
00603
00604 #define IS_TSC_SSD(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < 128U)))
00605
00606 #define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
00607
00608 #define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
00609                               ((VAL) == TSC_PG_PRESC_DIV2) || \
00610                               ((VAL) == TSC_PG_PRESC_DIV4) || \
00611                               ((VAL) == TSC_PG_PRESC_DIV8) || \
00612                               ((VAL) == TSC_PG_PRESC_DIV16) || \
00613                               ((VAL) == TSC_PG_PRESC_DIV32) || \
00614                               ((VAL) == TSC_PG_PRESC_DIV64) || \
00615                               ((VAL) == TSC_PG_PRESC_DIV128))
00616
00617 #define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
00618                          ((VAL) == TSC_MCV_511) || \
00619                          ((VAL) == TSC_MCV_1023) || \
00620                          ((VAL) == TSC_MCV_2047) || \
00621                          ((VAL) == TSC_MCV_4095) || \
00622                          ((VAL) == TSC_MCV_8191) || \
00623                          ((VAL) == TSC_MCV_16383))
00624
00625 #define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
00626
00627 #define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
00628
00629 #define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
00630
00631 #define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
00632                             ((VAL) == TSC_IOMODE_CHANNEL) || \
00633                             ((VAL) == TSC_IOMODE_SHIELD) || \
00634                             ((VAL) == TSC_IOMODE_SAMPLING))
00635
00636 #define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
00637
00638 #define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < TSC_NB_OF_GROUPS)))
00639
00640 /**
00641   * @}
00642   */
00643
00644 /* Exported functions --------------------------------------------------------*/
00645 /** @addtogroup TSC_Exported_Functions
00646   * @{
00647   */
00648
00649 /** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
00650  *  @{
00651  */
00652  /* Initialization and de-initialization functions *****************************/
00653 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
00654 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
00655 void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc);
00656 void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc);
00657 /**
00658   * @}
00659   */
00660
00661 /** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions
00662  *  @{
00663  */
00664 /* IO operation functions *****************************************************/
00665 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc);
00666 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc);
00667 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc);
00668 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc);
00669 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
00670 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index);
00671 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index);
00672 /**
00673   * @}
00674   */
00675
00676 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
00677  *  @{
00678  */
00679 /* Peripheral Control functions ***********************************************/
00680 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config);
00681 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice);
00682 /**
00683   * @}
00684   */
00685
00686 /** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
00687  *  @{
00688  */
00689 /* Peripheral State and Error functions ***************************************/
00690 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc);
00691 /**
00692   * @}
00693   */
00694
00695 /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00696  * @{
00697  */
00698 /******* TSC IRQHandler and Callbacks used in Interrupt mode */
00699 void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc);
00700 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc);
00701 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc);
00702 /**
00703   * @}
00704   */
00705
00706 /**
00707   * @}
00708   */
00709
00710 /**
00711   * @}
00712   */
00713
00714 /**
00715   * @}
00716   */
00717
00718 #ifdef __cplusplus
00719 }
00720 #endif
00721
00722 #endif /*__STM32F3xx_TSC_H */
00723
00724 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_uart.c Source File

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stm32f3xx_hal_uart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_uart.c
00004   * @author  MCD Application Team
00005   * @brief   UART HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State and Errors functions
00012   *
00013   @verbatim
00014  ===============================================================================
00015                         ##### How to use this driver #####
00016  ===============================================================================
00017   [..]
00018     The UART HAL driver can be used as follows:
00019
00020     (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
00021     (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
00022         (++) Enable the USARTx interface clock.
00023         (++) UART pins configuration:
00024             (+++) Enable the clock for the UART GPIOs.
00025             (+++) Configure these UART pins as alternate function pull-up.
00026         (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
00027              and HAL_UART_Receive_IT() APIs):
00028             (+++) Configure the USARTx interrupt priority.
00029             (+++) Enable the NVIC USART IRQ handle.
00030         (++) UART interrupts handling:
00031               -@@-  The specific UART interrupts (Transmission complete interrupt,
00032                 RXNE interrupt and Error Interrupts) are managed using the macros
00033                 __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
00034         (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
00035              and HAL_UART_Receive_DMA() APIs):
00036             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00037             (+++) Enable the DMAx interface clock.
00038             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00039             (+++) Configure the DMA Tx/Rx channel.
00040             (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
00041             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00042
00043     (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
00044         flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
00045
00046     (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
00047         in the huart handle AdvancedInit structure.
00048
00049     (#) For the UART asynchronous mode, initialize the UART registers by calling
00050         the HAL_UART_Init() API.
00051
00052     (#) For the UART Half duplex mode, initialize the UART registers by calling
00053         the HAL_HalfDuplex_Init() API.
00054
00055     (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
00056         by calling the HAL_LIN_Init() API.
00057
00058     (#) For the UART Multiprocessor mode, initialize the UART registers
00059         by calling the HAL_MultiProcessor_Init() API.
00060
00061     (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
00062         by calling the HAL_RS485Ex_Init() API.
00063
00064    [..]
00065     (@) These APIs (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(),
00066         also configure the low level Hardware (GPIO, CLOCK, CORTEX...etc) by
00067         calling the customized HAL_UART_MspInit() API.
00068
00069    [..]
00070    [..] Three operation modes are available within this driver :
00071
00072      *** Polling mode IO operation ***
00073      =================================
00074      [..]
00075        (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
00076        (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
00077
00078      *** Interrupt mode IO operation ***
00079      ===================================
00080      [..]
00081        (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
00082        (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
00083             add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
00084        (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
00085             add his own code by customization of function pointer HAL_UART_TxCpltCallback
00086        (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
00087        (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
00088             add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
00089        (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
00090             add his own code by customization of function pointer HAL_UART_RxCpltCallback
00091        (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
00092             add his own code by customization of function pointer HAL_UART_ErrorCallback
00093
00094      *** DMA mode IO operation ***
00095      ==============================
00096      [..]
00097        (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
00098        (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
00099             add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
00100        (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
00101             add his own code by customization of function pointer HAL_UART_TxCpltCallback
00102        (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
00103        (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
00104             add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
00105        (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
00106             add his own code by customization of function pointer HAL_UART_RxCpltCallback
00107        (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
00108             add his own code by customization of function pointer HAL_UART_ErrorCallback
00109        (+) Pause the DMA Transfer using HAL_UART_DMAPause()
00110        (+) Resume the DMA Transfer using HAL_UART_DMAResume()
00111        (+) Stop the DMA Transfer using HAL_UART_DMAStop()
00112
00113      *** UART HAL driver macros list ***
00114      =============================================
00115      [..]
00116        Below the list of most used macros in UART HAL driver.
00117
00118       (+) __HAL_UART_ENABLE: Enable the UART peripheral
00119       (+) __HAL_UART_DISABLE: Disable the UART peripheral
00120       (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
00121       (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
00122       (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
00123       (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
00124
00125      [..]
00126        (@) You can refer to the UART HAL driver header file for more useful macros
00127
00128   @endverbatim
00129   ******************************************************************************
00130   * @attention
00131   *
00132   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00133   *
00134   * Redistribution and use in source and binary forms, with or without modification,
00135   * are permitted provided that the following conditions are met:
00136   *   1. Redistributions of source code must retain the above copyright notice,
00137   *      this list of conditions and the following disclaimer.
00138   *   2. Redistributions in binary form must reproduce the above copyright notice,
00139   *      this list of conditions and the following disclaimer in the documentation
00140   *      and/or other materials provided with the distribution.
00141   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00142   *      may be used to endorse or promote products derived from this software
00143   *      without specific prior written permission.
00144   *
00145   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00146   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00147   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00148   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00149   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00150   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00151   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00152   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00153   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00154   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00155   *
00156   ******************************************************************************
00157   */
00158
00159 /* Includes ------------------------------------------------------------------*/
00160 #include "stm32f3xx_hal.h"
00161
00162 /** @addtogroup STM32F3xx_HAL_Driver
00163   * @{
00164   */
00165
00166 /** @defgroup UART UART
00167   * @brief UART HAL module driver
00168   * @{
00169   */
00170
00171 #ifdef HAL_UART_MODULE_ENABLED
00172
00173 /* Private typedef -----------------------------------------------------------*/
00174 /* Private define ------------------------------------------------------------*/
00175 /** @defgroup UART_Private_Constants UART Private Constants
00176   * @{
00177   */
00178 #define UART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
00179                                      USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
00180 /**
00181   * @}
00182   */
00183
00184 /* Private macros ------------------------------------------------------------*/
00185 /* Private variables ---------------------------------------------------------*/
00186 /* Private function prototypes -----------------------------------------------*/
00187 /** @addtogroup UART_Private_Functions
00188   * @{
00189   */
00190 static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
00191 static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
00192 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00193 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00194 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00195 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00196 static void UART_DMAError(DMA_HandleTypeDef *hdma);
00197 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00198 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00199 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00200 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00201 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00202 HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
00203 HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
00204 HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
00205 /**
00206   * @}
00207   */
00208
00209 /* Exported functions --------------------------------------------------------*/
00210
00211 /** @defgroup UART_Exported_Functions UART Exported Functions
00212   * @{
00213   */
00214
00215 /** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
00216   *  @brief    Initialization and Configuration functions
00217   *
00218 @verbatim
00219 ===============================================================================
00220             ##### Initialization and Configuration functions #####
00221  ===============================================================================
00222     [..]
00223     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00224     in asynchronous mode.
00225       (+) For the asynchronous mode the parameters below can be configured:
00226         (++) Baud Rate
00227         (++) Word Length
00228         (++) Stop Bit
00229         (++) Parity
00230         (++) Hardware flow control
00231         (++) Receiver/transmitter modes
00232         (++) Over Sampling Method
00233         (++) One-Bit Sampling Method
00234       (+) For the asynchronous mode, the following advanced features can be configured as well:
00235         (++) TX and/or RX pin level inversion
00236         (++) data logical level inversion
00237         (++) RX and TX pins swap
00238         (++) RX overrun detection disabling
00239         (++) DMA disabling on RX error
00240         (++) MSB first on communication line
00241         (++) auto Baud rate detection
00242     [..]
00243     The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init()
00244     API follow respectively the UART asynchronous, UART Half duplex, UART LIN mode and
00245     multiprocessor configuration procedures (details for the procedures are available in reference manual).
00246
00247 @endverbatim
00248   * @{
00249   */
00250
00251 /*
00252   Additional Table: If the parity is enabled, then the MSB bit of the data written
00253                     in the data register is transmitted but is changed by the parity bit.
00254                     According to device capability (support or not of 7-bit word length),
00255                     frame length is either defined by the M bit (8-bits or 9-bits)
00256                     or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
00257                     Possible UART frame formats are as listed in the following table:
00258
00259       Table 1. UART frame format.
00260       +-----------------------------------------------------------------------+
00261       |       M bit       |  PCE bit  |             UART frame                |
00262       |-------------------|-----------|---------------------------------------|
00263       |         0         |     0     |    | SB |    8-bit data   | STB |     |
00264       |-------------------|-----------|---------------------------------------|
00265       |         0         |     1     |    | SB | 7-bit data | PB | STB |     |
00266       |-------------------|-----------|---------------------------------------|
00267       |         1         |     0     |    | SB |    9-bit data   | STB |     |
00268       |-------------------|-----------|---------------------------------------|
00269       |         1         |     1     |    | SB | 8-bit data | PB | STB |     |
00270       +-----------------------------------------------------------------------+
00271       |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
00272       |---------|---------|-----------|---------------------------------------|
00273       |    0    |    0    |     0     |    | SB |    8 bit data   | STB |     |
00274       |---------|---------|-----------|---------------------------------------|
00275       |    0    |    0    |     1     |    | SB | 7 bit data | PB | STB |     |
00276       |---------|---------|-----------|---------------------------------------|
00277       |    0    |    1    |     0     |    | SB |    9 bit data   | STB |     |
00278       |---------|---------|-----------|---------------------------------------|
00279       |    0    |    1    |     1     |    | SB | 8 bit data | PB | STB |     |
00280       |---------|---------|-----------|---------------------------------------|
00281       |    1    |    0    |     0     |    | SB |    7 bit data   | STB |     |
00282       |---------|---------|-----------|---------------------------------------|
00283       |    1    |    0    |     1     |    | SB | 6 bit data | PB | STB |     |
00284       +-----------------------------------------------------------------------+
00285
00286 */
00287
00288 /**
00289   * @brief Initialize the UART mode according to the specified
00290   *        parameters in the UART_InitTypeDef and initialize the associated handle.
00291   * @param huart UART handle.
00292   * @retval HAL status
00293   */
00294 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
00295 {
00296   /* Check the UART handle allocation */
00297   if(huart == NULL)
00298   {
00299     return HAL_ERROR;
00300   }
00301
00302   if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
00303   {
00304     /* Check the parameters */
00305     assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
00306   }
00307   else
00308   {
00309     /* Check the parameters */
00310     assert_param(IS_UART_INSTANCE(huart->Instance));
00311   }
00312
00313   if(huart->gState == HAL_UART_STATE_RESET)
00314   {
00315     /* Allocate lock resource and initialize it */
00316     huart->Lock = HAL_UNLOCKED;
00317
00318     /* Init the low level hardware : GPIO, CLOCK */
00319     HAL_UART_MspInit(huart);
00320   }
00321
00322   huart->gState = HAL_UART_STATE_BUSY;
00323
00324   /* Disable the Peripheral */
00325   __HAL_UART_DISABLE(huart);
00326
00327   /* Set the UART Communication parameters */
00328   if (UART_SetConfig(huart) == HAL_ERROR)
00329   {
00330     return HAL_ERROR;
00331   }
00332
00333   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00334   {
00335     UART_AdvFeatureConfig(huart);
00336   }
00337
00338   /* In asynchronous mode, the following bits must be kept cleared:
00339   - LINEN and CLKEN bits in the USART_CR2 register,
00340   - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
00341   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00342   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00343
00344   /* Enable the Peripheral */
00345   __HAL_UART_ENABLE(huart);
00346
00347   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00348   return (UART_CheckIdleState(huart));
00349 }
00350
00351 /**
00352   * @brief Initialize the half-duplex mode according to the specified
00353   *        parameters in the UART_InitTypeDef and creates the associated handle.
00354   * @param huart UART handle.
00355   * @retval HAL status
00356   */
00357 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
00358 {
00359   /* Check the UART handle allocation */
00360   if(huart == NULL)
00361   {
00362     return HAL_ERROR;
00363   }
00364
00365   /* Check UART instance */
00366   assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
00367
00368   if(huart->gState == HAL_UART_STATE_RESET)
00369   {
00370     /* Allocate lock resource and initialize it */
00371     huart->Lock = HAL_UNLOCKED;
00372
00373     /* Init the low level hardware : GPIO, CLOCK */
00374     HAL_UART_MspInit(huart);
00375   }
00376
00377   huart->gState = HAL_UART_STATE_BUSY;
00378
00379   /* Disable the Peripheral */
00380   __HAL_UART_DISABLE(huart);
00381
00382   /* Set the UART Communication parameters */
00383   if (UART_SetConfig(huart) == HAL_ERROR)
00384   {
00385     return HAL_ERROR;
00386   }
00387
00388   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00389   {
00390     UART_AdvFeatureConfig(huart);
00391   }
00392
00393   /* In half-duplex mode, the following bits must be kept cleared:
00394   - LINEN and CLKEN bits in the USART_CR2 register,
00395   - SCEN and IREN bits in the USART_CR3 register.*/
00396   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00397   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
00398
00399   /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
00400   SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
00401
00402   /* Enable the Peripheral */
00403   __HAL_UART_ENABLE(huart);
00404
00405   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00406   return (UART_CheckIdleState(huart));
00407 }
00408
00409
00410 /**
00411   * @brief Initialize the LIN mode according to the specified
00412   *        parameters in the UART_InitTypeDef and creates the associated handle .
00413   * @param huart UART handle.
00414   * @param BreakDetectLength specifies the LIN break detection length.
00415   *        This parameter can be one of the following values:
00416   *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
00417   *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
00418   * @retval HAL status
00419   */
00420 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
00421 {
00422   /* Check the UART handle allocation */
00423   if(huart == NULL)
00424   {
00425     return HAL_ERROR;
00426   }
00427
00428   /* Check the LIN UART instance */
00429   assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
00430   /* Check the Break detection length parameter */
00431   assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
00432
00433   /* LIN mode limited to 16-bit oversampling only */
00434   if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
00435   {
00436     return HAL_ERROR;
00437   }
00438   /* LIN mode limited to 8-bit data length */
00439   if(huart->Init.WordLength != UART_WORDLENGTH_8B)
00440   {
00441     return HAL_ERROR;
00442   }
00443
00444   if(huart->gState == HAL_UART_STATE_RESET)
00445   {
00446     /* Allocate lock resource and initialize it */
00447     huart->Lock = HAL_UNLOCKED;
00448
00449     /* Init the low level hardware : GPIO, CLOCK */
00450     HAL_UART_MspInit(huart);
00451   }
00452
00453   huart->gState = HAL_UART_STATE_BUSY;
00454
00455   /* Disable the Peripheral */
00456   __HAL_UART_DISABLE(huart);
00457
00458   /* Set the UART Communication parameters */
00459   if (UART_SetConfig(huart) == HAL_ERROR)
00460   {
00461     return HAL_ERROR;
00462   }
00463
00464   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00465   {
00466     UART_AdvFeatureConfig(huart);
00467   }
00468
00469   /* In LIN mode, the following bits must be kept cleared:
00470   - LINEN and CLKEN bits in the USART_CR2 register,
00471   - SCEN and IREN bits in the USART_CR3 register.*/
00472   CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
00473   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
00474
00475   /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
00476   SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
00477
00478   /* Set the USART LIN Break detection length. */
00479   MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
00480
00481   /* Enable the Peripheral */
00482   __HAL_UART_ENABLE(huart);
00483
00484   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00485   return (UART_CheckIdleState(huart));
00486 }
00487
00488
00489 /**
00490   * @brief Initialize the multiprocessor mode according to the specified
00491   *        parameters in the UART_InitTypeDef and initialize the associated handle.
00492   * @param huart UART handle.
00493   * @param Address UART node address (4-, 6-, 7- or 8-bit long).
00494   * @param WakeUpMethod specifies the UART wakeup method.
00495   *        This parameter can be one of the following values:
00496   *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
00497   *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
00498   * @note  If the user resorts to idle line detection wake up, the Address parameter
00499   *        is useless and ignored by the initialization function.
00500   * @note  If the user resorts to address mark wake up, the address length detection
00501   *        is configured by default to 4 bits only. For the UART to be able to
00502   *        manage 6-, 7- or 8-bit long addresses detection, the API
00503   *        HAL_MultiProcessorEx_AddressLength_Set() must be called after
00504   *        HAL_MultiProcessor_Init().
00505   * @retval HAL status
00506   */
00507 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
00508 {
00509   /* Check the UART handle allocation */
00510   if(huart == NULL)
00511   {
00512     return HAL_ERROR;
00513   }
00514
00515   /* Check the wake up method parameter */
00516   assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
00517
00518   if(huart->gState == HAL_UART_STATE_RESET)
00519   {
00520     /* Allocate lock resource and initialize it */
00521     huart->Lock = HAL_UNLOCKED;
00522
00523     /* Init the low level hardware : GPIO, CLOCK */
00524     HAL_UART_MspInit(huart);
00525   }
00526
00527   huart->gState = HAL_UART_STATE_BUSY;
00528
00529   /* Disable the Peripheral */
00530   __HAL_UART_DISABLE(huart);
00531
00532   /* Set the UART Communication parameters */
00533   if (UART_SetConfig(huart) == HAL_ERROR)
00534   {
00535     return HAL_ERROR;
00536   }
00537
00538   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00539   {
00540     UART_AdvFeatureConfig(huart);
00541   }
00542
00543   /* In multiprocessor mode, the following bits must be kept cleared:
00544   - LINEN and CLKEN bits in the USART_CR2 register,
00545   - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
00546   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00547   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00548
00549   if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
00550   {
00551     /* If address mark wake up method is chosen, set the USART address node */
00552     MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
00553   }
00554
00555   /* Set the wake up method by setting the WAKE bit in the CR1 register */
00556   MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
00557
00558   /* Enable the Peripheral */
00559   __HAL_UART_ENABLE(huart);
00560
00561   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00562   return (UART_CheckIdleState(huart));
00563 }
00564
00565
00566 /**
00567   * @brief DeInitialize the UART peripheral.
00568   * @param huart UART handle.
00569   * @retval HAL status
00570   */
00571 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
00572 {
00573   /* Check the UART handle allocation */
00574   if(huart == NULL)
00575   {
00576     return HAL_ERROR;
00577   }
00578
00579   /* Check the parameters */
00580   assert_param(IS_UART_INSTANCE(huart->Instance));
00581
00582   huart->gState = HAL_UART_STATE_BUSY;
00583
00584   /* Disable the Peripheral */
00585   __HAL_UART_DISABLE(huart);
00586
00587   huart->Instance->CR1 = 0x0U;
00588   huart->Instance->CR2 = 0x0U;
00589   huart->Instance->CR3 = 0x0U;
00590
00591   /* DeInit the low level hardware */
00592   HAL_UART_MspDeInit(huart);
00593
00594   huart->ErrorCode = HAL_UART_ERROR_NONE;
00595   huart->gState    = HAL_UART_STATE_RESET;
00596   huart->RxState   = HAL_UART_STATE_RESET;
00597
00598   /* Process Unlock */
00599   __HAL_UNLOCK(huart);
00600
00601   return HAL_OK;
00602 }
00603
00604 /**
00605   * @brief Initialize the UART MSP.
00606   * @param huart UART handle.
00607   * @retval None
00608   */
00609 __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
00610 {
00611   /* Prevent unused argument(s) compilation warning */
00612   UNUSED(huart);
00613
00614   /* NOTE : This function should not be modified, when the callback is needed,
00615             the HAL_UART_MspInit can be implemented in the user file
00616    */
00617 }
00618
00619 /**
00620   * @brief DeInitialize the UART MSP.
00621   * @param huart UART handle.
00622   * @retval None
00623   */
00624 __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
00625 {
00626   /* Prevent unused argument(s) compilation warning */
00627   UNUSED(huart);
00628
00629   /* NOTE : This function should not be modified, when the callback is needed,
00630             the HAL_UART_MspDeInit can be implemented in the user file
00631    */
00632 }
00633
00634 /**
00635   * @}
00636   */
00637
00638 /** @defgroup UART_Exported_Functions_Group2 IO operation functions
00639   * @brief UART Transmit/Receive functions
00640   *
00641 @verbatim
00642  ===============================================================================
00643                       ##### IO operation functions #####
00644  ===============================================================================
00645     This subsection provides a set of functions allowing to manage the UART asynchronous
00646     and Half duplex data transfers.
00647
00648     (#) There are two mode of transfer:
00649        (++) Blocking mode: The communication is performed in polling mode.
00650            The HAL status of all data processing is returned by the same function
00651            after finishing transfer.
00652        (++) Non-Blocking mode: The communication is performed using Interrupts
00653            or DMA, These API's return the HAL status.
00654            The end of the data processing will be indicated through the
00655            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
00656            using DMA mode.
00657            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
00658            will be executed respectively at the end of the transmit or Receive process
00659            The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
00660
00661     (#) Blocking mode API's are :
00662         (++) HAL_UART_Transmit()
00663         (++) HAL_UART_Receive()
00664
00665     (#) Non-Blocking mode API's with Interrupt are :
00666         (++) HAL_UART_Transmit_IT()
00667         (++) HAL_UART_Receive_IT()
00668         (++) HAL_UART_IRQHandler()
00669
00670     (#) Non-Blocking mode API's with DMA are :
00671         (++) HAL_UART_Transmit_DMA()
00672         (++) HAL_UART_Receive_DMA()
00673         (++) HAL_UART_DMAPause()
00674         (++) HAL_UART_DMAResume()
00675         (++) HAL_UART_DMAStop()
00676
00677     (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
00678         (++) HAL_UART_TxHalfCpltCallback()
00679         (++) HAL_UART_TxCpltCallback()
00680         (++) HAL_UART_RxHalfCpltCallback()
00681         (++) HAL_UART_RxCpltCallback()
00682         (++) HAL_UART_ErrorCallback()
00683
00684     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00685         (++) HAL_UART_Abort()
00686         (++) HAL_UART_AbortTransmit()
00687         (++) HAL_UART_AbortReceive()
00688         (++) HAL_UART_Abort_IT()
00689         (++) HAL_UART_AbortTransmit_IT()
00690         (++) HAL_UART_AbortReceive_IT()
00691
00692     (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
00693         (++) HAL_UART_AbortCpltCallback()
00694         (++) HAL_UART_AbortTransmitCpltCallback()
00695         (++) HAL_UART_AbortReceiveCpltCallback()
00696
00697     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00698         Errors are handled as follows :
00699         (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00700              to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
00701              Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
00702              and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
00703              If user wants to abort it, Abort services should be called by user.
00704         (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00705              This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
00706              Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
00707
00708     -@- In the Half duplex communication, it is forbidden to run the transmit
00709         and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
00710
00711 @endverbatim
00712   * @{
00713   */
00714
00715 /**
00716   * @brief Send an amount of data in blocking mode.
00717   * @param huart UART handle.
00718   * @param pData Pointer to data buffer.
00719   * @param Size Amount of data to be sent.
00720   * @param Timeout Timeout duration.
00721   * @retval HAL status
00722   */
00723 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00724 {
00725   uint16_t* tmp;
00726   uint32_t tickstart = 0U;
00727
00728   /* Check that a Tx process is not already ongoing */
00729   if(huart->gState == HAL_UART_STATE_READY)
00730   {
00731     if((pData == NULL ) || (Size == 0U))
00732     {
00733       return  HAL_ERROR;
00734     }
00735
00736     /* Process Locked */
00737     __HAL_LOCK(huart);
00738
00739     huart->ErrorCode = HAL_UART_ERROR_NONE;
00740     huart->gState = HAL_UART_STATE_BUSY_TX;
00741
00742     /* Init tickstart for timeout managment*/
00743     tickstart = HAL_GetTick();
00744
00745     huart->TxXferSize = Size;
00746     huart->TxXferCount = Size;
00747     while(huart->TxXferCount > 0U)
00748     {
00749       huart->TxXferCount--;
00750       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00751       {
00752         return HAL_TIMEOUT;
00753       }
00754       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
00755       {
00756         tmp = (uint16_t*) pData;
00757         huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
00758         pData += 2U;
00759       }
00760       else
00761       {
00762         huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
00763       }
00764     }
00765     if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00766     {
00767       return HAL_TIMEOUT;
00768     }
00769
00770     /* At end of Tx process, restore huart->gState to Ready */
00771     huart->gState = HAL_UART_STATE_READY;
00772
00773     /* Process Unlocked */
00774     __HAL_UNLOCK(huart);
00775
00776     return HAL_OK;
00777   }
00778   else
00779   {
00780     return HAL_BUSY;
00781   }
00782 }
00783
00784 /**
00785   * @brief Receive an amount of data in blocking mode.
00786   * @param huart UART handle.
00787   * @param pData pointer to data buffer.
00788   * @param Size amount of data to be received.
00789   * @param Timeout Timeout duration.
00790   * @retval HAL status
00791   */
00792 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00793 {
00794   uint16_t* tmp;
00795   uint16_t uhMask;
00796   uint32_t tickstart = 0U;
00797
00798   /* Check that a Rx process is not already ongoing */
00799   if(huart->RxState == HAL_UART_STATE_READY)
00800   {
00801     if((pData == NULL ) || (Size == 0U))
00802     {
00803       return  HAL_ERROR;
00804     }
00805
00806     /* Process Locked */
00807     __HAL_LOCK(huart);
00808
00809     huart->ErrorCode = HAL_UART_ERROR_NONE;
00810     huart->RxState = HAL_UART_STATE_BUSY_RX;
00811
00812     /* Init tickstart for timeout managment*/
00813     tickstart = HAL_GetTick();
00814
00815     huart->RxXferSize = Size;
00816     huart->RxXferCount = Size;
00817
00818     /* Computation of UART mask to apply to RDR register */
00819     UART_MASK_COMPUTATION(huart);
00820     uhMask = huart->Mask;
00821
00822     /* as long as data have to be received */
00823     while(huart->RxXferCount > 0U)
00824     {
00825       huart->RxXferCount--;
00826       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00827       {
00828         return HAL_TIMEOUT;
00829       }
00830       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
00831       {
00832         tmp = (uint16_t*) pData ;
00833         *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
00834         pData +=2U;
00835       }
00836       else
00837       {
00838         *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
00839       }
00840     }
00841
00842     /* At end of Rx process, restore huart->RxState to Ready */
00843     huart->RxState = HAL_UART_STATE_READY;
00844
00845     /* Process Unlocked */
00846     __HAL_UNLOCK(huart);
00847
00848     return HAL_OK;
00849   }
00850   else
00851   {
00852     return HAL_BUSY;
00853   }
00854 }
00855
00856 /**
00857   * @brief Send an amount of data in interrupt mode.
00858   * @param huart UART handle.
00859   * @param pData pointer to data buffer.
00860   * @param Size amount of data to be sent.
00861   * @retval HAL status
00862   */
00863 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00864 {
00865   /* Check that a Tx process is not already ongoing */
00866   if(huart->gState == HAL_UART_STATE_READY)
00867   {
00868     if((pData == NULL ) || (Size == 0U))
00869     {
00870       return HAL_ERROR;
00871     }
00872
00873     /* Process Locked */
00874     __HAL_LOCK(huart);
00875
00876     huart->pTxBuffPtr = pData;
00877     huart->TxXferSize = Size;
00878     huart->TxXferCount = Size;
00879
00880     huart->ErrorCode = HAL_UART_ERROR_NONE;
00881     huart->gState = HAL_UART_STATE_BUSY_TX;
00882
00883     /* Process Unlocked */
00884     __HAL_UNLOCK(huart);
00885
00886     /* Enable the UART Transmit Data Register Empty Interrupt */
00887     SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
00888
00889     return HAL_OK;
00890   }
00891   else
00892   {
00893     return HAL_BUSY;
00894   }
00895 }
00896
00897 /**
00898   * @brief Receive an amount of data in interrupt mode.
00899   * @param huart UART handle.
00900   * @param pData pointer to data buffer.
00901   * @param Size amount of data to be received.
00902   * @retval HAL status
00903   */
00904 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00905 {
00906   /* Check that a Rx process is not already ongoing */
00907   if(huart->RxState == HAL_UART_STATE_READY)
00908   {
00909     if((pData == NULL ) || (Size == 0U))
00910     {
00911       return HAL_ERROR;
00912     }
00913
00914     /* Process Locked */
00915     __HAL_LOCK(huart);
00916
00917     huart->pRxBuffPtr = pData;
00918     huart->RxXferSize = Size;
00919     huart->RxXferCount = Size;
00920
00921     /* Computation of UART mask to apply to RDR register */
00922     UART_MASK_COMPUTATION(huart);
00923
00924     huart->ErrorCode = HAL_UART_ERROR_NONE;
00925     huart->RxState = HAL_UART_STATE_BUSY_RX;
00926
00927     /* Process Unlocked */
00928     __HAL_UNLOCK(huart);
00929
00930     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
00931     SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
00932
00933     /* Enable the UART Parity Error and Data Register not empty Interrupts */
00934     SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
00935
00936     return HAL_OK;
00937   }
00938   else
00939   {
00940     return HAL_BUSY;
00941   }
00942 }
00943
00944 /**
00945   * @brief Send an amount of data in DMA mode.
00946   * @param huart UART handle.
00947   * @param pData pointer to data buffer.
00948   * @param Size amount of data to be sent.
00949   * @note This function starts a DMA transfer in interrupt mode meaning that
00950   *       DMA half transfer complete, DMA transfer complete and DMA transfer
00951   *       error interrupts are enabled
00952   * @retval HAL status
00953   */
00954 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00955 {
00956   /* Check if UART instance supports continuous communication using DMA */
00957   assert_param(IS_UART_DMA_INSTANCE(huart->Instance));
00958
00959   /* Check that a Tx process is not already ongoing */
00960   if(huart->gState == HAL_UART_STATE_READY)
00961   {
00962     if((pData == NULL ) || (Size == 0U))
00963     {
00964       return HAL_ERROR;
00965     }
00966
00967     /* Process Locked */
00968     __HAL_LOCK(huart);
00969
00970     huart->pTxBuffPtr = pData;
00971     huart->TxXferSize = Size;
00972     huart->TxXferCount = Size;
00973
00974     huart->ErrorCode = HAL_UART_ERROR_NONE;
00975     huart->gState = HAL_UART_STATE_BUSY_TX;
00976
00977     /* Set the UART DMA transfer complete callback */
00978     huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
00979
00980     /* Set the UART DMA Half transfer complete callback */
00981     huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
00982
00983     /* Set the DMA error callback */
00984     huart->hdmatx->XferErrorCallback = UART_DMAError;
00985
00986     /* Set the DMA abort callback */
00987     huart->hdmatx->XferAbortCallback = NULL;
00988
00989     /* Enable the UART transmit DMA channel */
00990     HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size);
00991
00992     /* Clear the TC flag in the ICR register */
00993     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
00994
00995     /* Process Unlocked */
00996     __HAL_UNLOCK(huart);
00997
00998     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00999        in the UART CR3 register */
01000     SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01001
01002     return HAL_OK;
01003   }
01004   else
01005   {
01006     return HAL_BUSY;
01007   }
01008 }
01009
01010 /**
01011   * @brief Receive an amount of data in DMA mode.
01012   * @param huart UART handle.
01013   * @param pData pointer to data buffer.
01014   * @param Size amount of data to be received.
01015   * @note   When the UART parity is enabled (PCE = 1), the received data contain
01016   *         the parity bit (MSB position).
01017   * @note This function starts a DMA transfer in interrupt mode meaning that
01018   *       DMA half transfer complete, DMA transfer complete and DMA transfer
01019   *       error interrupts are enabled
01020   * @retval HAL status
01021   */
01022 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
01023 {
01024   /* Check if UART instance supports continuous communication using DMA */
01025   assert_param(IS_UART_DMA_INSTANCE(huart->Instance));
01026
01027   /* Check that a Rx process is not already ongoing */
01028   if(huart->RxState == HAL_UART_STATE_READY)
01029   {
01030     if((pData == NULL ) || (Size == 0U))
01031     {
01032       return HAL_ERROR;
01033     }
01034
01035     /* Process Locked */
01036     __HAL_LOCK(huart);
01037
01038     huart->pRxBuffPtr = pData;
01039     huart->RxXferSize = Size;
01040
01041     huart->ErrorCode = HAL_UART_ERROR_NONE;
01042     huart->RxState = HAL_UART_STATE_BUSY_RX;
01043
01044     /* Set the UART DMA transfer complete callback */
01045     huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
01046
01047     /* Set the UART DMA Half transfer complete callback */
01048     huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
01049
01050     /* Set the DMA error callback */
01051     huart->hdmarx->XferErrorCallback = UART_DMAError;
01052
01053     /* Set the DMA abort callback */
01054     huart->hdmarx->XferAbortCallback = NULL;
01055
01056     /* Enable the DMA channel */
01057     HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size);
01058
01059     /* Process Unlocked */
01060     __HAL_UNLOCK(huart);
01061
01062     /* Enable the UART Parity Error Interrupt */
01063     SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01064
01065     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
01066     SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
01067
01068     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01069        in the UART CR3 register */
01070     SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01071
01072     return HAL_OK;
01073   }
01074   else
01075   {
01076     return HAL_BUSY;
01077   }
01078 }
01079
01080 /**
01081   * @brief  Pause the DMA Transfer.
01082   * @param  huart UART handle.
01083   * @retval HAL status
01084   */
01085 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
01086 {
01087   /* Process Locked */
01088   __HAL_LOCK(huart);
01089
01090   if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
01091       (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
01092   {
01093     /* Disable the UART DMA Tx request */
01094     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01095   }
01096   if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
01097       (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
01098   {
01099     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01100     CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01101     CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01102
01103     /* Disable the UART DMA Rx request */
01104     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01105   }
01106
01107   /* Process Unlocked */
01108   __HAL_UNLOCK(huart);
01109
01110   return HAL_OK;
01111 }
01112
01113 /**
01114   * @brief  Resume the DMA Transfer.
01115   * @param  huart UART handle.
01116   * @retval HAL status
01117   */
01118 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
01119 {
01120   /* Process Locked */
01121   __HAL_LOCK(huart);
01122
01123   if(huart->gState == HAL_UART_STATE_BUSY_TX)
01124   {
01125     /* Enable the UART DMA Tx request */
01126     SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01127   }
01128   if(huart->RxState == HAL_UART_STATE_BUSY_RX)
01129   {
01130     /* Clear the Overrun flag before resuming the Rx transfer */
01131     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
01132
01133     /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
01134     SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01135     SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
01136
01137     /* Enable the UART DMA Rx request */
01138     SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01139   }
01140
01141   /* Process Unlocked */
01142   __HAL_UNLOCK(huart);
01143
01144   return HAL_OK;
01145 }
01146
01147 /**
01148   * @brief  Stop the DMA Transfer.
01149   * @param  huart UART handle.
01150   * @retval HAL status
01151   */
01152 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
01153 {
01154   /* The Lock is not implemented on this API to allow the user application
01155      to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
01156      HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
01157      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01158      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01159      the stream and the corresponding call back is executed. */
01160
01161   /* Stop UART DMA Tx request if ongoing */
01162   if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
01163       (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
01164   {
01165     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01166
01167     /* Abort the UART DMA Tx channel */
01168     if(huart->hdmatx != NULL)
01169     {
01170       HAL_DMA_Abort(huart->hdmatx);
01171     }
01172
01173     UART_EndTxTransfer(huart);
01174   }
01175
01176   /* Stop UART DMA Rx request if ongoing */
01177   if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
01178       (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
01179   {
01180     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01181
01182     /* Abort the UART DMA Rx channel */
01183     if(huart->hdmarx != NULL)
01184     {
01185       HAL_DMA_Abort(huart->hdmarx);
01186     }
01187
01188     UART_EndRxTransfer(huart);
01189   }
01190
01191   return HAL_OK;
01192 }
01193
01194 /**
01195   * @brief  Abort ongoing transfers (blocking mode).
01196   * @param  huart UART handle.
01197   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01198   *         This procedure performs following operations :
01199   *           - Disable UART Interrupts (Tx and Rx)
01200   *           - Disable the DMA transfer in the peripheral register (if enabled)
01201   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01202   *           - Set handle State to READY
01203   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01204   * @retval HAL status
01205 */
01206 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
01207 {
01208   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01209   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
01210   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01211
01212   /* Disable the UART DMA Tx request if enabled */
01213   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01214   {
01215     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01216
01217     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
01218     if(huart->hdmatx != NULL)
01219     {
01220       /* Set the UART DMA Abort callback to Null.
01221          No call back execution at end of DMA abort procedure */
01222       huart->hdmatx->XferAbortCallback = NULL;
01223
01224       HAL_DMA_Abort(huart->hdmatx);
01225     }
01226   }
01227
01228   /* Disable the UART DMA Rx request if enabled */
01229   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01230   {
01231     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01232
01233     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
01234     if(huart->hdmarx != NULL)
01235     {
01236       /* Set the UART DMA Abort callback to Null.
01237          No call back execution at end of DMA abort procedure */
01238       huart->hdmarx->XferAbortCallback = NULL;
01239
01240       HAL_DMA_Abort(huart->hdmarx);
01241     }
01242   }
01243
01244   /* Reset Tx and Rx transfer counters */
01245   huart->TxXferCount = 0U;
01246   huart->RxXferCount = 0U;
01247
01248   /* Clear the Error flags in the ICR register */
01249   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01250
01251   /* Restore huart->gState and huart->RxState to Ready */
01252   huart->gState  = HAL_UART_STATE_READY;
01253   huart->RxState = HAL_UART_STATE_READY;
01254
01255   /* Reset Handle ErrorCode to No Error */
01256   huart->ErrorCode = HAL_UART_ERROR_NONE;
01257
01258   return HAL_OK;
01259 }
01260
01261 /**
01262   * @brief  Abort ongoing Transmit transfer (blocking mode).
01263   * @param  huart UART handle.
01264   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01265   *         This procedure performs following operations :
01266   *           - Disable UART Interrupts (Tx)
01267   *           - Disable the DMA transfer in the peripheral register (if enabled)
01268   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01269   *           - Set handle State to READY
01270   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01271   * @retval HAL status
01272 */
01273 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
01274 {
01275   /* Disable TXEIE and TCIE interrupts */
01276   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01277
01278   /* Disable the UART DMA Tx request if enabled */
01279   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01280   {
01281     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01282
01283     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
01284     if(huart->hdmatx != NULL)
01285     {
01286       /* Set the UART DMA Abort callback to Null.
01287          No call back execution at end of DMA abort procedure */
01288       huart->hdmatx->XferAbortCallback = NULL;
01289
01290       HAL_DMA_Abort(huart->hdmatx);
01291     }
01292   }
01293
01294   /* Reset Tx transfer counter */
01295   huart->TxXferCount = 0U;
01296
01297   /* Restore huart->gState to Ready */
01298   huart->gState = HAL_UART_STATE_READY;
01299
01300   return HAL_OK;
01301 }
01302
01303 /**
01304   * @brief  Abort ongoing Receive transfer (blocking mode).
01305   * @param  huart UART handle.
01306   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01307   *         This procedure performs following operations :
01308   *           - Disable UART Interrupts (Rx)
01309   *           - Disable the DMA transfer in the peripheral register (if enabled)
01310   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01311   *           - Set handle State to READY
01312   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01313   * @retval HAL status
01314 */
01315 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
01316 {
01317   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01318   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01319   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01320
01321   /* Disable the UART DMA Rx request if enabled */
01322   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01323   {
01324     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01325
01326     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
01327     if(huart->hdmarx != NULL)
01328     {
01329       /* Set the UART DMA Abort callback to Null.
01330          No call back execution at end of DMA abort procedure */
01331       huart->hdmarx->XferAbortCallback = NULL;
01332
01333       HAL_DMA_Abort(huart->hdmarx);
01334     }
01335   }
01336
01337   /* Reset Rx transfer counter */
01338   huart->RxXferCount = 0U;
01339
01340   /* Clear the Error flags in the ICR register */
01341   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01342
01343   /* Restore huart->RxState to Ready */
01344   huart->RxState = HAL_UART_STATE_READY;
01345
01346   return HAL_OK;
01347 }
01348
01349 /**
01350   * @brief  Abort ongoing transfers (Interrupt mode).
01351   * @param  huart UART handle.
01352   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01353   *         This procedure performs following operations :
01354   *           - Disable UART Interrupts (Tx and Rx)
01355   *           - Disable the DMA transfer in the peripheral register (if enabled)
01356   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01357   *           - Set handle State to READY
01358   *           - At abort completion, call user abort complete callback
01359   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01360   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01361   * @retval HAL status
01362 */
01363 HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
01364 {
01365   uint32_t abortcplt = 1U;
01366
01367   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01368   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
01369   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01370
01371   /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
01372      before any call to DMA Abort functions */
01373   /* DMA Tx Handle is valid */
01374   if(huart->hdmatx != NULL)
01375   {
01376     /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
01377        Otherwise, set it to NULL */
01378     if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01379     {
01380       huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
01381     }
01382     else
01383     {
01384       huart->hdmatx->XferAbortCallback = NULL;
01385     }
01386   }
01387   /* DMA Rx Handle is valid */
01388   if(huart->hdmarx != NULL)
01389   {
01390     /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
01391        Otherwise, set it to NULL */
01392     if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01393     {
01394       huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
01395     }
01396     else
01397     {
01398       huart->hdmarx->XferAbortCallback = NULL;
01399     }
01400   }
01401
01402   /* Disable the UART DMA Tx request if enabled */
01403   if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01404   {
01405     /* Disable DMA Tx at UART level */
01406     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01407
01408     /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
01409     if(huart->hdmatx != NULL)
01410     {
01411       /* UART Tx DMA Abort callback has already been initialised :
01412          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01413
01414       /* Abort DMA TX */
01415       if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
01416       {
01417         huart->hdmatx->XferAbortCallback = NULL;
01418       }
01419       else
01420       {
01421         abortcplt = 0U;
01422       }
01423     }
01424   }
01425
01426   /* Disable the UART DMA Rx request if enabled */
01427   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01428   {
01429     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01430
01431     /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
01432     if(huart->hdmarx != NULL)
01433     {
01434       /* UART Rx DMA Abort callback has already been initialised :
01435          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01436
01437       /* Abort DMA RX */
01438       if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
01439       {
01440         huart->hdmarx->XferAbortCallback = NULL;
01441         abortcplt = 1U;
01442       }
01443       else
01444       {
01445         abortcplt = 0U;
01446       }
01447     }
01448   }
01449
01450   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01451   if (abortcplt == 1U)
01452   {
01453     /* Reset Tx and Rx transfer counters */
01454     huart->TxXferCount = 0U;
01455     huart->RxXferCount = 0U;
01456
01457     /* Reset errorCode */
01458     huart->ErrorCode = HAL_UART_ERROR_NONE;
01459
01460     /* Clear the Error flags in the ICR register */
01461     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01462
01463     /* Restore huart->gState and huart->RxState to Ready */
01464     huart->gState  = HAL_UART_STATE_READY;
01465     huart->RxState = HAL_UART_STATE_READY;
01466
01467     /* As no DMA to be aborted, call directly user Abort complete callback */
01468     HAL_UART_AbortCpltCallback(huart);
01469   }
01470
01471   return HAL_OK;
01472 }
01473
01474 /**
01475   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01476   * @param  huart UART handle.
01477   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01478   *         This procedure performs following operations :
01479   *           - Disable UART Interrupts (Tx)
01480   *           - Disable the DMA transfer in the peripheral register (if enabled)
01481   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01482   *           - Set handle State to READY
01483   *           - At abort completion, call user abort complete callback
01484   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01485   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01486   * @retval HAL status
01487 */
01488 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
01489 {
01490   /* Disable TXEIE and TCIE interrupts */
01491   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01492
01493   /* Disable the UART DMA Tx request if enabled */
01494   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01495   {
01496     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01497
01498     /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
01499     if(huart->hdmatx != NULL)
01500     {
01501       /* Set the UART DMA Abort callback :
01502          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01503       huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
01504
01505       /* Abort DMA TX */
01506       if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
01507       {
01508         /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
01509         huart->hdmatx->XferAbortCallback(huart->hdmatx);
01510       }
01511     }
01512     else
01513     {
01514       /* Reset Tx transfer counter */
01515       huart->TxXferCount = 0U;
01516
01517       /* Restore huart->gState to Ready */
01518       huart->gState = HAL_UART_STATE_READY;
01519
01520       /* As no DMA to be aborted, call directly user Abort complete callback */
01521       HAL_UART_AbortTransmitCpltCallback(huart);
01522     }
01523   }
01524   else
01525   {
01526     /* Reset Tx transfer counter */
01527     huart->TxXferCount = 0U;
01528
01529     /* Restore huart->gState to Ready */
01530     huart->gState = HAL_UART_STATE_READY;
01531
01532     /* As no DMA to be aborted, call directly user Abort complete callback */
01533     HAL_UART_AbortTransmitCpltCallback(huart);
01534   }
01535
01536   return HAL_OK;
01537 }
01538
01539 /**
01540   * @brief  Abort ongoing Receive transfer (Interrupt mode).
01541   * @param  huart UART handle.
01542   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01543   *         This procedure performs following operations :
01544   *           - Disable UART Interrupts (Rx)
01545   *           - Disable the DMA transfer in the peripheral register (if enabled)
01546   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01547   *           - Set handle State to READY
01548   *           - At abort completion, call user abort complete callback
01549   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01550   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01551   * @retval HAL status
01552 */
01553 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
01554 {
01555   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01556   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01557   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01558
01559   /* Disable the UART DMA Rx request if enabled */
01560   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01561   {
01562     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01563
01564     /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
01565     if(huart->hdmarx != NULL)
01566     {
01567       /* Set the UART DMA Abort callback :
01568          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01569       huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
01570
01571       /* Abort DMA RX */
01572       if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
01573       {
01574         /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
01575         huart->hdmarx->XferAbortCallback(huart->hdmarx);
01576       }
01577     }
01578     else
01579     {
01580       /* Reset Rx transfer counter */
01581       huart->RxXferCount = 0U;
01582
01583       /* Clear the Error flags in the ICR register */
01584       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01585
01586       /* Restore huart->RxState to Ready */
01587       huart->RxState = HAL_UART_STATE_READY;
01588
01589       /* As no DMA to be aborted, call directly user Abort complete callback */
01590       HAL_UART_AbortReceiveCpltCallback(huart);
01591     }
01592   }
01593   else
01594   {
01595     /* Reset Rx transfer counter */
01596     huart->RxXferCount = 0U;
01597
01598     /* Clear the Error flags in the ICR register */
01599     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01600
01601     /* Restore huart->RxState to Ready */
01602     huart->RxState = HAL_UART_STATE_READY;
01603
01604     /* As no DMA to be aborted, call directly user Abort complete callback */
01605     HAL_UART_AbortReceiveCpltCallback(huart);
01606   }
01607
01608   return HAL_OK;
01609 }
01610
01611 /**
01612   * @brief Handle UART interrupt request.
01613   * @param huart UART handle.
01614   * @retval None
01615   */
01616 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
01617 {
01618   uint32_t isrflags   = READ_REG(huart->Instance->ISR);
01619   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
01620   uint32_t cr3its;
01621   uint32_t errorflags;
01622
01623   /* If no error occurs */
01624   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
01625   if (errorflags == RESET)
01626   {
01627     /* UART in mode Receiver ---------------------------------------------------*/
01628     if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01629     {
01630       UART_Receive_IT(huart);
01631       return;
01632     }
01633   }
01634
01635   /* If some errors occur */
01636   cr3its = READ_REG(huart->Instance->CR3);
01637   if(   (errorflags != RESET)
01638      && (   ((cr3its & USART_CR3_EIE) != RESET)
01639          || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
01640   {
01641     /* UART parity error interrupt occurred -------------------------------------*/
01642     if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
01643     {
01644       __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
01645
01646       huart->ErrorCode |= HAL_UART_ERROR_PE;
01647     }
01648
01649     /* UART frame error interrupt occurred --------------------------------------*/
01650     if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01651     {
01652       __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
01653
01654       huart->ErrorCode |= HAL_UART_ERROR_FE;
01655     }
01656
01657     /* UART noise error interrupt occurred --------------------------------------*/
01658     if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01659     {
01660       __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
01661
01662       huart->ErrorCode |= HAL_UART_ERROR_NE;
01663     }
01664
01665     /* UART Over-Run interrupt occurred -----------------------------------------*/
01666     if(((isrflags & USART_ISR_ORE) != RESET) &&
01667        (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
01668     {
01669       __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
01670
01671       huart->ErrorCode |= HAL_UART_ERROR_ORE;
01672     }
01673
01674     /* Call UART Error Call back function if need be --------------------------*/
01675     if(huart->ErrorCode != HAL_UART_ERROR_NONE)
01676     {
01677       /* UART in mode Receiver ---------------------------------------------------*/
01678       if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01679       {
01680         UART_Receive_IT(huart);
01681       }
01682
01683       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
01684          consider error as blocking */
01685       if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||
01686           (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
01687       {
01688         /* Blocking error : transfer is aborted
01689            Set the UART state ready to be able to start again the process,
01690            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01691         UART_EndRxTransfer(huart);
01692
01693         /* Disable the UART DMA Rx request if enabled */
01694         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01695         {
01696           CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01697
01698           /* Abort the UART DMA Rx channel */
01699           if(huart->hdmarx != NULL)
01700           {
01701             /* Set the UART DMA Abort callback :
01702                will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
01703             huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
01704
01705             /* Abort DMA RX */
01706             if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
01707             {
01708               /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
01709               huart->hdmarx->XferAbortCallback(huart->hdmarx);
01710             }
01711           }
01712           else
01713           {
01714             /* Call user error callback */
01715             HAL_UART_ErrorCallback(huart);
01716           }
01717         }
01718         else
01719         {
01720           /* Call user error callback */
01721           HAL_UART_ErrorCallback(huart);
01722         }
01723       }
01724       else
01725       {
01726         /* Non Blocking error : transfer could go on.
01727            Error is notified to user through user error callback */
01728         HAL_UART_ErrorCallback(huart);
01729         huart->ErrorCode = HAL_UART_ERROR_NONE;
01730       }
01731     }
01732     return;
01733
01734   } /* End if some error occurs */
01735
01736   /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
01737   if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET))
01738   {
01739     __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF);
01740     /* Set the UART state ready to be able to start again the process */
01741     huart->gState  = HAL_UART_STATE_READY;
01742     huart->RxState = HAL_UART_STATE_READY;
01743     HAL_UARTEx_WakeupCallback(huart);
01744     return;
01745   }
01746
01747   /* UART in mode Transmitter ------------------------------------------------*/
01748   if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
01749   {
01750     UART_Transmit_IT(huart);
01751     return;
01752   }
01753
01754   /* UART in mode Transmitter (transmission end) -----------------------------*/
01755   if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
01756   {
01757     UART_EndTransmit_IT(huart);
01758     return;
01759   }
01760
01761 }
01762
01763 /**
01764   * @brief Tx Transfer completed callback.
01765   * @param huart UART handle.
01766   * @retval None
01767   */
01768 __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
01769 {
01770   /* Prevent unused argument(s) compilation warning */
01771   UNUSED(huart);
01772
01773   /* NOTE : This function should not be modified, when the callback is needed,
01774             the HAL_UART_TxCpltCallback can be implemented in the user file.
01775    */
01776 }
01777
01778 /**
01779   * @brief  Tx Half Transfer completed callback.
01780   * @param  huart UART handle.
01781   * @retval None
01782   */
01783 __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
01784 {
01785   /* Prevent unused argument(s) compilation warning */
01786   UNUSED(huart);
01787
01788   /* NOTE: This function should not be modified, when the callback is needed,
01789            the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
01790    */
01791 }
01792
01793 /**
01794   * @brief Rx Transfer completed callback.
01795   * @param huart UART handle.
01796   * @retval None
01797   */
01798 __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
01799 {
01800   /* Prevent unused argument(s) compilation warning */
01801   UNUSED(huart);
01802
01803   /* NOTE : This function should not be modified, when the callback is needed,
01804             the HAL_UART_RxCpltCallback can be implemented in the user file.
01805    */
01806 }
01807
01808 /**
01809   * @brief  Rx Half Transfer completed callback.
01810   * @param  huart UART handle.
01811   * @retval None
01812   */
01813 __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
01814 {
01815   /* Prevent unused argument(s) compilation warning */
01816   UNUSED(huart);
01817
01818   /* NOTE: This function should not be modified, when the callback is needed,
01819            the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
01820    */
01821 }
01822
01823 /**
01824   * @brief UART error callback.
01825   * @param huart UART handle.
01826   * @retval None
01827   */
01828 __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
01829 {
01830   /* Prevent unused argument(s) compilation warning */
01831   UNUSED(huart);
01832
01833   /* NOTE : This function should not be modified, when the callback is needed,
01834             the HAL_UART_ErrorCallback can be implemented in the user file.
01835    */
01836 }
01837
01838 /**
01839   * @brief  UART Abort Complete callback.
01840   * @param  huart UART handle.
01841   * @retval None
01842   */
01843 __weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
01844 {
01845   /* Prevent unused argument(s) compilation warning */
01846   UNUSED(huart);
01847
01848   /* NOTE : This function should not be modified, when the callback is needed,
01849             the HAL_UART_AbortCpltCallback can be implemented in the user file.
01850    */
01851 }
01852
01853 /**
01854   * @brief  UART Abort Complete callback.
01855   * @param  huart UART handle.
01856   * @retval None
01857   */
01858 __weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
01859 {
01860   /* Prevent unused argument(s) compilation warning */
01861   UNUSED(huart);
01862
01863   /* NOTE : This function should not be modified, when the callback is needed,
01864             the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
01865    */
01866 }
01867
01868 /**
01869   * @brief  UART Abort Receive Complete callback.
01870   * @param  huart UART handle.
01871   * @retval None
01872   */
01873 __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
01874 {
01875   /* Prevent unused argument(s) compilation warning */
01876   UNUSED(huart);
01877
01878   /* NOTE : This function should not be modified, when the callback is needed,
01879             the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
01880    */
01881 }
01882
01883 /**
01884   * @}
01885   */
01886
01887 /** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
01888   *  @brief   UART control functions
01889   *
01890 @verbatim
01891  ===============================================================================
01892                       ##### Peripheral Control functions #####
01893  ===============================================================================
01894     [..]
01895     This subsection provides a set of functions allowing to control the UART.
01896      (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
01897      (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
01898      (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
01899      (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
01900      (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
01901      (+) HAL_LIN_SendBreak() API transmits the break characters
01902 @endverbatim
01903   * @{
01904   */
01905
01906 /**
01907   * @brief Enable UART in mute mode (does not mean UART enters mute mode;
01908   * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
01909   * @param huart UART handle.
01910   * @retval HAL status
01911   */
01912 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
01913 {
01914   /* Process Locked */
01915   __HAL_LOCK(huart);
01916
01917   huart->gState = HAL_UART_STATE_BUSY;
01918
01919   /* Enable USART mute mode by setting the MME bit in the CR1 register */
01920   SET_BIT(huart->Instance->CR1, USART_CR1_MME);
01921
01922   huart->gState = HAL_UART_STATE_READY;
01923
01924   return (UART_CheckIdleState(huart));
01925 }
01926
01927 /**
01928   * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode
01929   *         as it may not have been in mute mode at this very moment).
01930   * @param  huart UART handle.
01931   * @retval HAL status
01932   */
01933 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
01934 {
01935   /* Process Locked */
01936   __HAL_LOCK(huart);
01937
01938   huart->gState = HAL_UART_STATE_BUSY;
01939
01940    /* Disable USART mute mode by clearing the MME bit in the CR1 register */
01941   CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
01942
01943   huart->gState = HAL_UART_STATE_READY;
01944
01945   return (UART_CheckIdleState(huart));
01946 }
01947
01948 /**
01949   * @brief Enter UART mute mode (means UART actually enters mute mode).
01950   * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
01951   * @param huart UART handle.
01952   * @retval None
01953   */
01954 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
01955 {
01956   __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
01957 }
01958
01959 /**
01960   * @brief  Enable the UART transmitter and disable the UART receiver.
01961   * @param  huart UART handle.
01962   * @retval HAL status
01963   */
01964 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
01965 {
01966   /* Process Locked */
01967   __HAL_LOCK(huart);
01968   huart->gState = HAL_UART_STATE_BUSY;
01969
01970   /* Clear TE and RE bits */
01971   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
01972   /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
01973   SET_BIT(huart->Instance->CR1, USART_CR1_TE);
01974
01975   huart->gState = HAL_UART_STATE_READY;
01976
01977   /* Process Unlocked */
01978   __HAL_UNLOCK(huart);
01979
01980   return HAL_OK;
01981 }
01982
01983 /**
01984   * @brief  Enable the UART receiver and disable the UART transmitter.
01985   * @param  huart UART handle.
01986   * @retval HAL status.
01987   */
01988 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
01989 {
01990   /* Process Locked */
01991   __HAL_LOCK(huart);
01992   huart->gState = HAL_UART_STATE_BUSY;
01993
01994   /* Clear TE and RE bits */
01995   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
01996   /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
01997   SET_BIT(huart->Instance->CR1, USART_CR1_RE);
01998
01999   huart->gState = HAL_UART_STATE_READY;
02000   /* Process Unlocked */
02001   __HAL_UNLOCK(huart);
02002
02003   return HAL_OK;
02004 }
02005
02006
02007 /**
02008   * @brief  Transmit break characters.
02009   * @param  huart UART handle.
02010   * @retval HAL status
02011   */
02012 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
02013 {
02014   /* Check the parameters */
02015   assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
02016
02017   /* Process Locked */
02018   __HAL_LOCK(huart);
02019
02020   huart->gState = HAL_UART_STATE_BUSY;
02021
02022   /* Send break characters */
02023   huart->Instance->RQR |= UART_SENDBREAK_REQUEST;
02024
02025   huart->gState = HAL_UART_STATE_READY;
02026
02027   /* Process Unlocked */
02028   __HAL_UNLOCK(huart);
02029
02030   return HAL_OK;
02031 }
02032
02033
02034 /**
02035   * @}
02036   */
02037
02038 /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
02039  *  @brief   UART Peripheral State functions
02040  *
02041 @verbatim
02042   ==============================================================================
02043             ##### Peripheral State and Error functions #####
02044   ==============================================================================
02045     [..]
02046     This subsection provides functions allowing to :
02047       (+) Return the UART handle state.
02048       (+) Return the UART handle error code
02049
02050 @endverbatim
02051   * @{
02052   */
02053
02054 /**
02055   * @brief  Return the UART handle state.
02056   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02057   *               the configuration information for the specified UART.
02058   * @retval HAL state
02059   */
02060 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
02061 {
02062   uint32_t temp1= 0x00U, temp2 = 0x00U;
02063   temp1 = huart->gState;
02064   temp2 = huart->RxState;
02065
02066   return (HAL_UART_StateTypeDef)(temp1 | temp2);
02067 }
02068
02069 /**
02070   * @brief  Return the UART handle error code.
02071   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02072   *               the configuration information for the specified UART.
02073   * @retval UART Error Code
02074   */
02075 uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
02076 {
02077   return huart->ErrorCode;
02078 }
02079 /**
02080   * @}
02081   */
02082
02083 /**
02084   * @}
02085   */
02086
02087 /** @defgroup UART_Private_Functions UART Private Functions
02088   * @{
02089   */
02090
02091 /**
02092   * @brief Configure the UART peripheral.
02093   * @param huart UART handle.
02094   * @retval HAL status
02095   */
02096 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
02097 {
02098   uint32_t tmpreg                     = 0x00000000U;
02099   UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
02100   uint16_t brrtemp                    = 0x0000U;
02101   uint16_t usartdiv                   = 0x0000U;
02102   HAL_StatusTypeDef ret               = HAL_OK;
02103
02104   /* Check the parameters */
02105   assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
02106   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
02107   assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
02108   assert_param(IS_UART_PARITY(huart->Init.Parity));
02109   assert_param(IS_UART_MODE(huart->Init.Mode));
02110   assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
02111   assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
02112   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
02113
02114
02115   /*-------------------------- USART CR1 Configuration -----------------------*/
02116   /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
02117    *  the UART Word Length, Parity, Mode and oversampling:
02118    *  set the M bits according to huart->Init.WordLength value
02119    *  set PCE and PS bits according to huart->Init.Parity value
02120    *  set TE and RE bits according to huart->Init.Mode value
02121    *  set OVER8 bit according to huart->Init.OverSampling value */
02122   tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
02123   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
02124
02125   /*-------------------------- USART CR2 Configuration -----------------------*/
02126   /* Configure the UART Stop Bits: Set STOP[13:12] bits according
02127    * to huart->Init.StopBits value */
02128   MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
02129
02130   /*-------------------------- USART CR3 Configuration -----------------------*/
02131   /* Configure
02132    * - UART HardWare Flow Control: set CTSE and RTSE bits according
02133    *   to huart->Init.HwFlowCtl value
02134    * - one-bit sampling method versus three samples' majority rule according
02135    *   to huart->Init.OneBitSampling */
02136   tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;
02137   MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
02138
02139   /*-------------------------- USART BRR Configuration -----------------------*/
02140   UART_GETCLOCKSOURCE(huart, clocksource);
02141
02142   /* Check UART Over Sampling to set Baud Rate Register */
02143   if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
02144   {
02145     switch (clocksource)
02146     {
02147       case UART_CLOCKSOURCE_PCLK1:
02148         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
02149         break;
02150       case UART_CLOCKSOURCE_PCLK2:
02151         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
02152         break;
02153       case UART_CLOCKSOURCE_HSI:
02154         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
02155         break;
02156       case UART_CLOCKSOURCE_SYSCLK:
02157         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
02158         break;
02159       case UART_CLOCKSOURCE_LSE:
02160         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
02161         break;
02162       case UART_CLOCKSOURCE_UNDEFINED:
02163       default:
02164         ret = HAL_ERROR;
02165         break;
02166     }
02167
02168     brrtemp = usartdiv & 0xFFF0U;
02169     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
02170     huart->Instance->BRR = brrtemp;
02171   }
02172   else
02173   {
02174     switch (clocksource)
02175     {
02176       case UART_CLOCKSOURCE_PCLK1:
02177         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
02178         break;
02179       case UART_CLOCKSOURCE_PCLK2:
02180         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
02181         break;
02182       case UART_CLOCKSOURCE_HSI:
02183         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
02184         break;
02185       case UART_CLOCKSOURCE_SYSCLK:
02186         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
02187         break;
02188       case UART_CLOCKSOURCE_LSE:
02189         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
02190         break;
02191       case UART_CLOCKSOURCE_UNDEFINED:
02192       default:
02193         ret = HAL_ERROR;
02194         break;
02195     }
02196   }
02197
02198   return ret;
02199
02200 }
02201
02202 /**
02203   * @brief Configure the UART peripheral advanced features.
02204   * @param huart UART handle.
02205   * @retval None
02206   */
02207 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
02208 {
02209   /* Check whether the set of advanced features to configure is properly set */
02210   assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
02211
02212   /* if required, configure TX pin active level inversion */
02213   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
02214   {
02215     assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
02216     MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
02217   }
02218
02219   /* if required, configure RX pin active level inversion */
02220   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
02221   {
02222     assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
02223     MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
02224   }
02225
02226   /* if required, configure data inversion */
02227   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
02228   {
02229     assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
02230     MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
02231   }
02232
02233   /* if required, configure RX/TX pins swap */
02234   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
02235   {
02236     assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
02237     MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
02238   }
02239
02240   /* if required, configure RX overrun detection disabling */
02241   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
02242   {
02243     assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
02244     MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
02245   }
02246
02247   /* if required, configure DMA disabling on reception error */
02248   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
02249   {
02250     assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
02251     MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
02252   }
02253
02254   /* if required, configure auto Baud rate detection scheme */
02255   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
02256   {
02257     assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
02258     assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
02259     MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
02260     /* set auto Baudrate detection parameters if detection is enabled */
02261     if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
02262     {
02263       assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
02264       MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
02265     }
02266   }
02267
02268   /* if required, configure MSB first on communication line */
02269   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
02270   {
02271     assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
02272     MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
02273   }
02274 }
02275
02276 /**
02277   * @brief Check the UART Idle State.
02278   * @param huart UART handle.
02279   * @retval HAL status
02280   */
02281 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
02282 {
02283   uint32_t tickstart = 0U;
02284
02285   /* Initialize the UART ErrorCode */
02286   huart->ErrorCode = HAL_UART_ERROR_NONE;
02287
02288   /* Init tickstart for timeout managment*/
02289   tickstart = HAL_GetTick();
02290
02291   /* Check if the Transmitter is enabled */
02292   if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
02293   {
02294     /* Wait until TEACK flag is set */
02295     if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
02296     {
02297       /* Timeout Occured */
02298       return HAL_TIMEOUT;
02299     }
02300   }
02301   /* Check if the Receiver is enabled */
02302   if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
02303   {
02304     /* Wait until REACK flag is set */
02305     if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
02306     {
02307       /* Timeout Occured */
02308       return HAL_TIMEOUT;
02309     }
02310   }
02311
02312   /* Initialize the UART State */
02313   huart->gState  = HAL_UART_STATE_READY;
02314   huart->RxState = HAL_UART_STATE_READY;
02315
02316   /* Process Unlocked */
02317   __HAL_UNLOCK(huart);
02318
02319   return HAL_OK;
02320 }
02321
02322 /**
02323   * @brief  Handle UART Communication Timeout.
02324   * @param  huart UART handle.
02325   * @param  Flag Specifies the UART flag to check
02326   * @param  Status Flag status (SET or RESET)
02327   * @param  Tickstart Tick start value
02328   * @param  Timeout Timeout duration
02329   * @retval HAL status
02330   */
02331 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
02332 {
02333   /* Wait until flag is set */
02334   while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
02335   {
02336     /* Check for the Timeout */
02337     if(Timeout != HAL_MAX_DELAY)
02338     {
02339       if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
02340       {
02341         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
02342         CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
02343         CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
02344
02345         huart->gState  = HAL_UART_STATE_READY;
02346         huart->RxState = HAL_UART_STATE_READY;
02347
02348         /* Process Unlocked */
02349         __HAL_UNLOCK(huart);
02350         return HAL_TIMEOUT;
02351       }
02352     }
02353   }
02354   return HAL_OK;
02355 }
02356
02357
02358 /**
02359   * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
02360   * @param  huart UART handle.
02361   * @retval None
02362   */
02363 static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
02364 {
02365   /* Disable TXEIE and TCIE interrupts */
02366   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
02367
02368   /* At end of Tx process, restore huart->gState to Ready */
02369   huart->gState = HAL_UART_STATE_READY;
02370 }
02371
02372
02373 /**
02374   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
02375   * @param  huart UART handle.
02376   * @retval None
02377   */
02378 static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
02379 {
02380   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
02381   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
02382   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
02383
02384   /* At end of Rx process, restore huart->RxState to Ready */
02385   huart->RxState = HAL_UART_STATE_READY;
02386 }
02387
02388
02389 /**
02390   * @brief DMA UART transmit process complete callback.
02391   * @param hdma DMA handle.
02392   * @retval None
02393   */
02394 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02395 {
02396   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
02397
02398   /* DMA Normal mode */
02399   if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
02400   {
02401     huart->TxXferCount = 0U;
02402
02403     /* Disable the DMA transfer for transmit request by resetting the DMAT bit
02404        in the UART CR3 register */
02405     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
02406
02407     /* Enable the UART Transmit Complete Interrupt */
02408     SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
02409   }
02410   /* DMA Circular mode */
02411   else
02412   {
02413     HAL_UART_TxCpltCallback(huart);
02414   }
02415
02416 }
02417
02418 /**
02419   * @brief DMA UART transmit process half complete callback.
02420   * @param hdma DMA handle.
02421   * @retval None
02422   */
02423 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
02424 {
02425   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
02426
02427   HAL_UART_TxHalfCpltCallback(huart);
02428 }
02429
02430 /**
02431   * @brief DMA UART receive process complete callback.
02432   * @param hdma DMA handle.
02433   * @retval None
02434   */
02435 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02436 {
02437   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
02438
02439   /* DMA Normal mode */
02440   if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
02441   {
02442     huart->RxXferCount = 0U;
02443
02444     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
02445     CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
02446     CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
02447
02448     /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
02449        in the UART CR3 register */
02450     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
02451
02452     /* At end of Rx process, restore huart->RxState to Ready */
02453     huart->RxState = HAL_UART_STATE_READY;
02454   }
02455
02456   HAL_UART_RxCpltCallback(huart);
02457 }
02458
02459 /**
02460   * @brief DMA UART receive process half complete callback.
02461   * @param hdma DMA handle.
02462   * @retval None
02463   */
02464 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
02465 {
02466   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
02467
02468   HAL_UART_RxHalfCpltCallback(huart);
02469 }
02470
02471 /**
02472   * @brief DMA UART communication error callback.
02473   * @param hdma DMA handle.
02474   * @retval None
02475   */
02476 static void UART_DMAError(DMA_HandleTypeDef *hdma)
02477 {
02478   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
02479
02480   /* Stop UART DMA Tx request if ongoing */
02481   if (  (huart->gState == HAL_UART_STATE_BUSY_TX)
02482       &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )
02483   {
02484     huart->TxXferCount = 0U;
02485     UART_EndTxTransfer(huart);
02486   }
02487
02488   /* Stop UART DMA Rx request if ongoing */
02489   if (  (huart->RxState == HAL_UART_STATE_BUSY_RX)
02490       &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )
02491   {
02492     huart->RxXferCount = 0U;
02493     UART_EndRxTransfer(huart);
02494   }
02495
02496   huart->ErrorCode |= HAL_UART_ERROR_DMA;
02497   HAL_UART_ErrorCallback(huart);
02498 }
02499
02500 /**
02501   * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
02502   *         (To be called at end of DMA Abort procedure following error occurrence).
02503   * @param  hdma DMA handle.
02504   * @retval None
02505   */
02506 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02507 {
02508   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
02509   huart->RxXferCount = 0U;
02510   huart->TxXferCount = 0U;
02511
02512   HAL_UART_ErrorCallback(huart);
02513 }
02514
02515 /**
02516   * @brief  DMA UART Tx communication abort callback, when initiated by user
02517   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02518   * @note   When this callback is executed, User Abort complete call back is called only if no
02519   *         Abort still ongoing for Rx DMA Handle.
02520   * @param  hdma DMA handle.
02521   * @retval None
02522   */
02523 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02524 {
02525   UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
02526
02527   huart->hdmatx->XferAbortCallback = NULL;
02528
02529   /* Check if an Abort process is still ongoing */
02530   if(huart->hdmarx != NULL)
02531   {
02532     if(huart->hdmarx->XferAbortCallback != NULL)
02533     {
02534       return;
02535     }
02536   }
02537
02538   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02539   huart->TxXferCount = 0U;
02540   huart->RxXferCount = 0U;
02541
02542   /* Reset errorCode */
02543   huart->ErrorCode = HAL_UART_ERROR_NONE;
02544
02545   /* Clear the Error flags in the ICR register */
02546   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
02547
02548   /* Restore huart->gState and huart->RxState to Ready */
02549   huart->gState  = HAL_UART_STATE_READY;
02550   huart->RxState = HAL_UART_STATE_READY;
02551
02552   /* Call user Abort complete callback */
02553   HAL_UART_AbortCpltCallback(huart);
02554 }
02555
02556
02557 /**
02558   * @brief  DMA UART Rx communication abort callback, when initiated by user
02559   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02560   * @note   When this callback is executed, User Abort complete call back is called only if no
02561   *         Abort still ongoing for Tx DMA Handle.
02562   * @param  hdma DMA handle.
02563   * @retval None
02564   */
02565 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02566 {
02567   UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
02568
02569   huart->hdmarx->XferAbortCallback = NULL;
02570
02571   /* Check if an Abort process is still ongoing */
02572   if(huart->hdmatx != NULL)
02573   {
02574     if(huart->hdmatx->XferAbortCallback != NULL)
02575     {
02576       return;
02577     }
02578   }
02579
02580   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02581   huart->TxXferCount = 0U;
02582   huart->RxXferCount = 0U;
02583
02584   /* Reset errorCode */
02585   huart->ErrorCode = HAL_UART_ERROR_NONE;
02586
02587   /* Clear the Error flags in the ICR register */
02588   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
02589
02590   /* Restore huart->gState and huart->RxState to Ready */
02591   huart->gState  = HAL_UART_STATE_READY;
02592   huart->RxState = HAL_UART_STATE_READY;
02593
02594   /* Call user Abort complete callback */
02595   HAL_UART_AbortCpltCallback(huart);
02596 }
02597
02598
02599 /**
02600   * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
02601   *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
02602   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
02603   *         and leads to user Tx Abort Complete callback execution).
02604   * @param  hdma DMA handle.
02605   * @retval None
02606   */
02607 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02608 {
02609   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
02610
02611   huart->TxXferCount = 0U;
02612
02613   /* Restore huart->gState to Ready */
02614   huart->gState = HAL_UART_STATE_READY;
02615
02616   /* Call user Abort complete callback */
02617   HAL_UART_AbortTransmitCpltCallback(huart);
02618 }
02619
02620 /**
02621   * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
02622   *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
02623   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
02624   *         and leads to user Rx Abort Complete callback execution).
02625   * @param  hdma DMA handle.
02626   * @retval None
02627   */
02628 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02629 {
02630   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02631
02632   huart->RxXferCount = 0U;
02633
02634   /* Clear the Error flags in the ICR register */
02635   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
02636
02637   /* Restore huart->RxState to Ready */
02638   huart->RxState = HAL_UART_STATE_READY;
02639
02640   /* Call user Abort complete callback */
02641   HAL_UART_AbortReceiveCpltCallback(huart);
02642 }
02643
02644 /**
02645   * @brief  Send an amount of data in interrupt mode.
02646   * @note   Function is called under interruption only, once
02647   *         interruptions have been enabled by HAL_UART_Transmit_IT().
02648   * @param  huart UART handle.
02649   * @retval HAL status
02650   */
02651 HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
02652 {
02653   uint16_t* tmp;
02654
02655   /* Check that a Tx process is ongoing */
02656   if (huart->gState == HAL_UART_STATE_BUSY_TX)
02657   {
02658     if(huart->TxXferCount == 0U)
02659     {
02660       /* Disable the UART Transmit Data Register Empty Interrupt */
02661       CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
02662
02663       /* Enable the UART Transmit Complete Interrupt */
02664       SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
02665
02666       return HAL_OK;
02667     }
02668     else
02669     {
02670       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
02671       {
02672         tmp = (uint16_t*) huart->pTxBuffPtr;
02673         huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
02674         huart->pTxBuffPtr += 2U;
02675       }
02676       else
02677       {
02678         huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU);
02679       }
02680       huart->TxXferCount--;
02681
02682       return HAL_OK;
02683     }
02684   }
02685   else
02686   {
02687     return HAL_BUSY;
02688   }
02689 }
02690
02691 /**
02692   * @brief  Wrap up transmission in non-blocking mode.
02693   * @param  huart pointer to a UART_HandleTypeDef structure that contains
02694   *               the configuration information for the specified UART module.
02695   * @retval HAL status
02696   */
02697 HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
02698 {
02699   /* Disable the UART Transmit Complete Interrupt */
02700   CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
02701
02702   /* Tx process is ended, restore huart->gState to Ready */
02703   huart->gState = HAL_UART_STATE_READY;
02704
02705   HAL_UART_TxCpltCallback(huart);
02706
02707   return HAL_OK;
02708 }
02709
02710 /**
02711   * @brief  Receive an amount of data in interrupt mode.
02712   * @note   Function is called under interruption only, once
02713   *         interruptions have been enabled by HAL_UART_Receive_IT()
02714   * @param  huart UART handle.
02715   * @retval HAL status
02716   */
02717 HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
02718 {
02719   uint16_t* tmp;
02720   uint16_t  uhMask = huart->Mask;
02721   uint16_t  uhdata;
02722
02723   /* Check that a Rx process is ongoing */
02724   if(huart->RxState == HAL_UART_STATE_BUSY_RX)
02725   {
02726     uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
02727     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
02728     {
02729       tmp = (uint16_t*) huart->pRxBuffPtr ;
02730       *tmp = (uint16_t)(uhdata & uhMask);
02731       huart->pRxBuffPtr +=2U;
02732     }
02733     else
02734     {
02735       *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
02736     }
02737
02738     if(--huart->RxXferCount == 0U)
02739     {
02740       /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
02741       CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
02742
02743       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
02744       CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
02745
02746       /* Rx process is completed, restore huart->RxState to Ready */
02747       huart->RxState = HAL_UART_STATE_READY;
02748
02749       HAL_UART_RxCpltCallback(huart);
02750
02751       return HAL_OK;
02752     }
02753
02754     return HAL_OK;
02755   }
02756   else
02757   {
02758     /* Clear RXNE interrupt flag */
02759     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
02760
02761     return HAL_BUSY;
02762   }
02763 }
02764
02765 /**
02766   * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
02767   * @param huart UART handle.
02768   * @param WakeUpSelection UART wake up from stop mode parameters.
02769   * @retval None
02770   */
02771 void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
02772 {
02773   assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
02774
02775   /* Set the USART address length */
02776   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
02777
02778   /* Set the USART address node */
02779   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
02780 }
02781
02782 /**
02783   * @}
02784   */
02785
02786 #endif /* HAL_UART_MODULE_ENABLED */
02787 /**
02788   * @}
02789   */
02790
02791 /**
02792   * @}
02793   */
02794
02795 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_uart.h Source File

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stm32f3xx_hal_uart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_uart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UART HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_UART_H
00038 #define __STM32F3xx_HAL_UART_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup UART
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /** @defgroup UART_Exported_Types UART Exported Types
00057   * @{
00058   */
00059
00060 /**
00061   * @brief UART Init Structure definition
00062   */
00063 typedef struct
00064 {
00065   uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
00066                                            The baud rate register is computed using the following formula:
00067                                            - If oversampling is 16 or in LIN mode,
00068                                               Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
00069                                            - If oversampling is 8U,
00070                                               Baud Rate Register[15:4] = ((2U * PCLKx) / ((huart->Init.BaudRate)))[15:4]
00071                                               Baud Rate Register[3] =  0
00072                                               Baud Rate Register[2:0] =  (((2U * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1      */
00073
00074   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00075                                            This parameter can be a value of @ref UARTEx_Word_Length. */
00076
00077   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00078                                            This parameter can be a value of @ref UART_Stop_Bits. */
00079
00080   uint32_t Parity;                    /*!< Specifies the parity mode.
00081                                            This parameter can be a value of @ref UART_Parity
00082                                            @note When parity is enabled, the computed parity is inserted
00083                                                  at the MSB position of the transmitted data (9th bit when
00084                                                  the word length is set to 9 data bits; 8th bit when the
00085                                                  word length is set to 8 data bits). */
00086
00087   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00088                                            This parameter can be a value of @ref UART_Mode. */
00089
00090   uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled
00091                                            or disabled.
00092                                            This parameter can be a value of @ref UART_Hardware_Flow_Control. */
00093
00094   uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8U).
00095                                            This parameter can be a value of @ref UART_Over_Sampling. */
00096
00097   uint32_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
00098                                            Selecting the single sample method increases the receiver tolerance to clock
00099                                            deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
00100 }UART_InitTypeDef;
00101
00102 /**
00103   * @brief  UART Advanced Features initalization structure definition
00104   */
00105 typedef struct
00106 {
00107   uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
00108                                        Advanced Features may be initialized at the same time .
00109                                        This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
00110
00111   uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
00112                                        This parameter can be a value of @ref UART_Tx_Inv.  */
00113
00114   uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
00115                                        This parameter can be a value of @ref UART_Rx_Inv.  */
00116
00117   uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
00118                                        vs negative/inverted logic).
00119                                        This parameter can be a value of @ref UART_Data_Inv. */
00120
00121   uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
00122                                        This parameter can be a value of @ref UART_Rx_Tx_Swap. */
00123
00124   uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
00125                                        This parameter can be a value of @ref UART_Overrun_Disable. */
00126
00127   uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
00128                                        This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
00129
00130   uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
00131                                        This parameter can be a value of @ref UART_AutoBaudRate_Enable */
00132
00133   uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
00134                                        detection is carried out.
00135                                        This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
00136
00137   uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
00138                                        This parameter can be a value of @ref UART_MSB_First. */
00139 } UART_AdvFeatureInitTypeDef;
00140
00141 /**
00142   * @brief  UART wake up from stop mode parameters
00143   */
00144 typedef struct
00145 {
00146   uint32_t WakeUpEvent;        /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
00147                                     This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
00148                                     If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
00149                                     be filled up. */
00150
00151   uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
00152                                     This parameter can be a value of @ref UART_WakeUp_Address_Length.  */
00153
00154   uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
00155 } UART_WakeUpTypeDef;
00156
00157 /**
00158   * @brief HAL UART State structures definition
00159   * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.
00160   *        - gState contains UART state information related to global Handle management
00161   *          and also information related to Tx operations.
00162   *          gState value coding follow below described bitmap :
00163   *          b7-b6  Error information
00164   *             00 : No Error
00165   *             01 : (Not Used)
00166   *             10 : Timeout
00167   *             11 : Error
00168   *          b5     IP initilisation status
00169   *             0  : Reset (IP not initialized)
00170   *             1  : Init done (IP not initialized. HAL UART Init function already called)
00171   *          b4-b3  (not used)
00172   *             xx : Should be set to 00
00173   *          b2     Intrinsic process state
00174   *             0  : Ready
00175   *             1  : Busy (IP busy with some configuration or internal operations)
00176   *          b1     (not used)
00177   *             x  : Should be set to 0
00178   *          b0     Tx state
00179   *             0  : Ready (no Tx operation ongoing)
00180   *             1  : Busy (Tx operation ongoing)
00181   *        - RxState contains information related to Rx operations.
00182   *          RxState value coding follow below described bitmap :
00183   *          b7-b6  (not used)
00184   *             xx : Should be set to 00
00185   *          b5     IP initilisation status
00186   *             0  : Reset (IP not initialized)
00187   *             1  : Init done (IP not initialized)
00188   *          b4-b2  (not used)
00189   *            xxx : Should be set to 000
00190   *          b1     Rx state
00191   *             0  : Ready (no Rx operation ongoing)
00192   *             1  : Busy (Rx operation ongoing)
00193   *          b0     (not used)
00194   *             x  : Should be set to 0.
00195   */
00196 typedef enum
00197 {
00198   HAL_UART_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
00199                                                    Value is allowed for gState and RxState */
00200   HAL_UART_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
00201                                                    Value is allowed for gState and RxState */
00202   HAL_UART_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing
00203                                                    Value is allowed for gState only */
00204   HAL_UART_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
00205                                                    Value is allowed for gState only */
00206   HAL_UART_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
00207                                                    Value is allowed for RxState only */
00208   HAL_UART_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
00209                                                    Not to be used for neither gState nor RxState.
00210                                                    Value is result of combination (Or) between gState and RxState values */
00211   HAL_UART_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
00212                                                    Value is allowed for gState only */
00213   HAL_UART_STATE_ERROR             = 0xE0U    /*!< Error
00214                                                    Value is allowed for gState only */
00215 }HAL_UART_StateTypeDef;
00216
00217 /**
00218   * @brief UART clock sources definition
00219   */
00220 typedef enum
00221 {
00222   UART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source     */
00223   UART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source     */
00224   UART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source       */
00225   UART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source    */
00226   UART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */
00227   UART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */
00228 }UART_ClockSourceTypeDef;
00229
00230 /**
00231   * @brief  UART handle Structure definition
00232   */
00233 typedef struct
00234 {
00235   USART_TypeDef            *Instance;        /*!< UART registers base address        */
00236
00237   UART_InitTypeDef         Init;             /*!< UART communication parameters      */
00238
00239   UART_AdvFeatureInitTypeDef AdvancedInit;   /*!< UART Advanced Features initialization parameters */
00240
00241   uint8_t                  *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */
00242
00243   uint16_t                 TxXferSize;       /*!< UART Tx Transfer size              */
00244
00245   __IO uint16_t            TxXferCount;      /*!< UART Tx Transfer Counter           */
00246
00247   uint8_t                  *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
00248
00249   uint16_t                 RxXferSize;       /*!< UART Rx Transfer size              */
00250
00251   __IO uint16_t            RxXferCount;      /*!< UART Rx Transfer Counter           */
00252
00253   uint16_t                 Mask;             /*!< UART Rx RDR register mask          */
00254
00255   DMA_HandleTypeDef        *hdmatx;          /*!< UART Tx DMA Handle parameters      */
00256
00257   DMA_HandleTypeDef        *hdmarx;          /*!< UART Rx DMA Handle parameters      */
00258
00259   HAL_LockTypeDef           Lock;            /*!< Locking object                     */
00260
00261   __IO HAL_UART_StateTypeDef    gState;      /*!< UART state information related to global Handle management
00262                                                   and also related to Tx operations.
00263                                                   This parameter can be a value of @ref HAL_UART_StateTypeDef */
00264
00265   __IO HAL_UART_StateTypeDef    RxState;     /*!< UART state information related to Rx operations.
00266                                                   This parameter can be a value of @ref HAL_UART_StateTypeDef */
00267
00268   __IO uint32_t             ErrorCode;       /*!< UART Error code                    */
00269
00270 }UART_HandleTypeDef;
00271
00272 /**
00273   * @}
00274   */
00275
00276 /* Exported constants --------------------------------------------------------*/
00277 /** @defgroup UART_Exported_Constants UART Exported Constants
00278   * @{
00279   */
00280
00281 /** @defgroup UART_Error UART Error
00282   * @{
00283   */
00284 #define HAL_UART_ERROR_NONE      (0x00000000U)    /*!< No error            */
00285 #define HAL_UART_ERROR_PE        (0x00000001U)    /*!< Parity error        */
00286 #define HAL_UART_ERROR_NE        (0x00000002U)    /*!< Noise error         */
00287 #define HAL_UART_ERROR_FE        (0x00000004U)    /*!< frame error         */
00288 #define HAL_UART_ERROR_ORE       (0x00000008U)    /*!< Overrun error       */
00289 #define HAL_UART_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error  */
00290 #define HAL_UART_ERROR_BUSY      (0x00000020U)    /*!< Busy Error          */
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup UART_Stop_Bits   UART Number of Stop Bits
00296   * @{
00297   */
00298 #define UART_STOPBITS_0_5                   USART_CR2_STOP_0                                  /*!< UART frame with 0.5 stop bit  */
00299 #define UART_STOPBITS_1                     (0x00000000U)                                     /*!< UART frame with 1 stop bit    */
00300 #define UART_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< UART frame with 1.5 stop bits */
00301 #define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)                      /*!< UART frame with 2 stop bits   */
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup UART_Parity  UART Parity
00307   * @{
00308   */
00309 #define UART_PARITY_NONE                    (0x00000000U)                                  /*!< No parity   */
00310 #define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)                      /*!< Even parity */
00311 #define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))     /*!< Odd parity  */
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
00317   * @{
00318   */
00319 #define UART_HWCONTROL_NONE                  (0x00000000U)                                    /*!< No hardware control       */
00320 #define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)                       /*!< Request To Send           */
00321 #define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)                       /*!< Clear To Send             */
00322 #define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))    /*!< Request and Clear To Send */
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup UART_Mode UART Transfer Mode
00328   * @{
00329   */
00330 #define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)                    /*!< RX mode        */
00331 #define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)                    /*!< TX mode        */
00332 #define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))    /*!< RX and TX mode */
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup UART_State  UART State
00338   * @{
00339   */
00340 #define UART_STATE_DISABLE                  (0x00000000U)                   /*!< UART disabled  */
00341 #define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)        /*!< UART enabled   */
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup UART_Over_Sampling UART Over Sampling
00347   * @{
00348   */
00349 #define UART_OVERSAMPLING_16                (0x00000000U)                   /*!< Oversampling by 16U */
00350 #define UART_OVERSAMPLING_8                 ((uint32_t)USART_CR1_OVER8)     /*!< Oversampling by 8  */
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
00356   * @{
00357   */
00358 #define UART_ONE_BIT_SAMPLE_DISABLE         (0x00000000U)                   /*!< One-bit sampling disable */
00359 #define UART_ONE_BIT_SAMPLE_ENABLE          ((uint32_t)USART_CR3_ONEBIT)    /*!< One-bit sampling enable  */
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
00365   * @{
00366   */
00367 #define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    (0x00000000U)                     /*!< Auto Baud rate detection on start bit            */
00368 #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)   /*!< Auto Baud rate detection on falling edge         */
00369 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   ((uint32_t)USART_CR2_ABRMODE_1)   /*!< Auto Baud rate detection on 0x7F frame detection */
00370 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   ((uint32_t)USART_CR2_ABRMODE)     /*!< Auto Baud rate detection on 0x55 frame detection */
00371 /**
00372   * @}
00373   */
00374
00375 /** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
00376   * @{
00377   */
00378 #define UART_RECEIVER_TIMEOUT_DISABLE       (0x00000000U)                           /*!< UART receiver timeout disable */
00379 #define UART_RECEIVER_TIMEOUT_ENABLE        ((uint32_t)USART_CR2_RTOEN)             /*!< UART receiver timeout enable  */
00380 /**
00381   * @}
00382   */
00383
00384 /** @defgroup UART_LIN    UART Local Interconnection Network mode
00385   * @{
00386   */
00387 #define UART_LIN_DISABLE                    (0x00000000U)                          /*!< Local Interconnect Network disable */
00388 #define UART_LIN_ENABLE                     ((uint32_t)USART_CR2_LINEN)            /*!< Local Interconnect Network enable  */
00389 /**
00390   * @}
00391   */
00392
00393 /** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
00394   * @{
00395   */
00396 #define UART_LINBREAKDETECTLENGTH_10B       (0x00000000U)                         /*!< LIN 10-bit break detection length */
00397 #define UART_LINBREAKDETECTLENGTH_11B       ((uint32_t)USART_CR2_LBDL)            /*!< LIN 11-bit break detection length  */
00398 /**
00399   * @}
00400   */
00401
00402 /** @defgroup UART_DMA_Tx    UART DMA Tx
00403   * @{
00404   */
00405 #define UART_DMA_TX_DISABLE                 (0x00000000U)                         /*!< UART DMA TX disabled */
00406 #define UART_DMA_TX_ENABLE                  ((uint32_t)USART_CR3_DMAT)            /*!< UART DMA TX enabled  */
00407 /**
00408   * @}
00409   */
00410
00411 /** @defgroup UART_DMA_Rx   UART DMA Rx
00412   * @{
00413   */
00414 #define UART_DMA_RX_DISABLE                 (0x00000000U)                           /*!< UART DMA RX disabled */
00415 #define UART_DMA_RX_ENABLE                  ((uint32_t)USART_CR3_DMAR)              /*!< UART DMA RX enabled  */
00416 /**
00417   * @}
00418   */
00419
00420 /** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
00421   * @{
00422   */
00423 #define UART_HALF_DUPLEX_DISABLE            (0x00000000U)                           /*!< UART half-duplex disabled */
00424 #define UART_HALF_DUPLEX_ENABLE             ((uint32_t)USART_CR3_HDSEL)             /*!< UART half-duplex enabled  */
00425 /**
00426   * @}
00427   */
00428
00429 /** @defgroup UART_WakeUp_Address_Length    UART WakeUp Address Length
00430   * @{
00431   */
00432 #define UART_ADDRESS_DETECT_4B              (0x00000000U)                /*!< 4-bit long wake-up address */
00433 #define UART_ADDRESS_DETECT_7B              ((uint32_t)USART_CR2_ADDM7)  /*!< 7-bit long wake-up address */
00434 /**
00435   * @}
00436   */
00437
00438 /** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
00439   * @{
00440   */
00441 #define UART_WAKEUPMETHOD_IDLELINE          (0x00000000U)                           /*!< UART wake-up on idle line    */
00442 #define UART_WAKEUPMETHOD_ADDRESSMARK       ((uint32_t)USART_CR1_WAKE)              /*!< UART wake-up on address mark */
00443 /**
00444   * @}
00445   */
00446
00447 /** @defgroup UART_Flags     UART Status Flags
00448   *        Elements values convention: 0xXXXX
00449   *           - 0xXXXX  : Flag mask in the ISR register
00450   * @{
00451   */
00452 #define UART_FLAG_REACK                     (0x00400000U)              /*!< UART receive enable acknowledge flag      */
00453 #define UART_FLAG_TEACK                     (0x00200000U)              /*!< UART transmit enable acknowledge flag     */
00454 #define UART_FLAG_WUF                       (0x00100000U)              /*!< UART wake-up from stop mode flag          */
00455 #define UART_FLAG_RWU                       (0x00080000U)              /*!< UART receiver wake-up from mute mode flag */
00456 #define UART_FLAG_SBKF                      (0x00040000U)              /*!< UART send break flag                      */
00457 #define UART_FLAG_CMF                       (0x00020000U)              /*!< UART character match flag                 */
00458 #define UART_FLAG_BUSY                      (0x00010000U)              /*!< UART busy flag                            */
00459 #define UART_FLAG_ABRF                      (0x00008000U)              /*!< UART auto Baud rate flag                  */
00460 #define UART_FLAG_ABRE                      (0x00004000U)              /*!< UART auto Baud rate error                 */
00461 #define UART_FLAG_EOBF                      (0x00001000U)              /*!< UART end of block flag                    */
00462 #define UART_FLAG_RTOF                      (0x00000800U)              /*!< UART receiver timeout flag                */
00463 #define UART_FLAG_CTS                       (0x00000400U)              /*!< UART clear to send flag                   */
00464 #define UART_FLAG_CTSIF                     (0x00000200U)              /*!< UART clear to send interrupt flag         */
00465 #define UART_FLAG_LBDF                      (0x00000100U)              /*!< UART LIN break detection flag             */
00466 #define UART_FLAG_TXE                       (0x00000080U)              /*!< UART transmit data register empty         */
00467 #define UART_FLAG_TC                        (0x00000040U)              /*!< UART transmission complete                */
00468 #define UART_FLAG_RXNE                      (0x00000020U)              /*!< UART read data register not empty         */
00469 #define UART_FLAG_IDLE                      (0x00000010U)              /*!< UART idle flag                            */
00470 #define UART_FLAG_ORE                       (0x00000008U)              /*!< UART overrun error                        */
00471 #define UART_FLAG_NE                        (0x00000004U)              /*!< UART noise error                          */
00472 #define UART_FLAG_FE                        (0x00000002U)              /*!< UART frame error                          */
00473 #define UART_FLAG_PE                        (0x00000001U)              /*!< UART parity error                         */
00474 /**
00475   * @}
00476   */
00477
00478 /** @defgroup UART_Interrupt_definition   UART Interrupts Definition
00479   *        Elements values convention: 000ZZZZZ0XXYYYYYb
00480   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00481   *           - XX  : Interrupt source register (2bits)
00482   *                 - 01: CR1 register
00483   *                 - 10: CR2 register
00484   *                 - 11: CR3 register
00485   *           - ZZZZZ  : Flag position in the ISR register(5bits)
00486   * @{
00487   */
00488 #define UART_IT_PE                          (0x0028U)                  /*!< UART parity error interruption                 */
00489 #define UART_IT_TXE                         (0x0727U)                  /*!< UART transmit data register empty interruption */
00490 #define UART_IT_TC                          (0x0626U)                  /*!< UART transmission complete interruption        */
00491 #define UART_IT_RXNE                        (0x0525U)                  /*!< UART read data register not empty interruption */
00492 #define UART_IT_IDLE                        (0x0424U)                  /*!< UART idle interruption                         */
00493 #define UART_IT_LBD                         (0x0846U)                  /*!< UART LIN break detection interruption          */
00494 #define UART_IT_CTS                         (0x096AU)                  /*!< UART CTS interruption                          */
00495 #define UART_IT_CM                          (0x112EU)                  /*!< UART character match interruption              */
00496 #define UART_IT_WUF                         (0x1476U)                  /*!< UART wake-up from stop mode interruption       */
00497 #define UART_IT_ERR                         (0x0060U)                  /*!< UART error interruption                        */
00498 #define UART_IT_ORE                         (0x0300U)                  /*!< UART overrun error interruption                */
00499 #define UART_IT_NE                          (0x0200U)                  /*!< UART noise error interruption                  */
00500 #define UART_IT_FE                          (0x0100U)                  /*!< UART frame error interruption                  */
00501 /**
00502   * @}
00503   */
00504
00505 /** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
00506   * @{
00507   */
00508 #define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */
00509 #define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */
00510 #define UART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag         */
00511 #define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */
00512 #define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */
00513 #define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */
00514 #define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */
00515 #define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */
00516 #define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< Receiver Time Out Clear Flag      */
00517 #define UART_CLEAR_EOBF                      USART_ICR_EOBCF           /*!< End Of Block Clear Flag           */
00518 #define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */
00519 #define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */
00520 /**
00521   * @}
00522   */
00523
00524 /** @defgroup UART_Request_Parameters UART Request Parameters
00525   * @{
00526   */
00527 #define UART_AUTOBAUD_REQUEST               ((uint32_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request      */
00528 #define UART_SENDBREAK_REQUEST              ((uint32_t)USART_RQR_SBKRQ)        /*!< Send Break Request          */
00529 #define UART_MUTE_MODE_REQUEST              ((uint32_t)USART_RQR_MMRQ)         /*!< Mute Mode Request           */
00530 #define UART_RXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request  */
00531 #define UART_TXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
00532 /**
00533   * @}
00534   */
00535
00536 /** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
00537   * @{
00538   */
00539 #define UART_ADVFEATURE_NO_INIT                 (0x00000000U)          /*!< No advanced feature initialization       */
00540 #define UART_ADVFEATURE_TXINVERT_INIT           (0x00000001U)          /*!< TX pin active level inversion            */
00541 #define UART_ADVFEATURE_RXINVERT_INIT           (0x00000002U)          /*!< RX pin active level inversion            */
00542 #define UART_ADVFEATURE_DATAINVERT_INIT         (0x00000004U)          /*!< Binary data inversion                    */
00543 #define UART_ADVFEATURE_SWAP_INIT               (0x00000008U)          /*!< TX/RX pins swap                          */
00544 #define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   (0x00000010U)          /*!< RX overrun disable                       */
00545 #define UART_ADVFEATURE_DMADISABLEONERROR_INIT  (0x00000020U)          /*!< DMA disable on Reception Error           */
00546 #define UART_ADVFEATURE_AUTOBAUDRATE_INIT       (0x00000040U)          /*!< Auto Baud rate detection initialization  */
00547 #define UART_ADVFEATURE_MSBFIRST_INIT           (0x00000080U)          /*!< Most significant bit sent/received first */
00548 /**
00549   * @}
00550   */
00551
00552 /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
00553   * @{
00554   */
00555 #define UART_ADVFEATURE_TXINV_DISABLE       (0x00000000U)                       /*!< TX pin active level inversion disable */
00556 #define UART_ADVFEATURE_TXINV_ENABLE        ((uint32_t)USART_CR2_TXINV)         /*!< TX pin active level inversion enable  */
00557 /**
00558   * @}
00559   */
00560
00561 /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
00562   * @{
00563   */
00564 #define UART_ADVFEATURE_RXINV_DISABLE       (0x00000000U)                       /*!< RX pin active level inversion disable */
00565 #define UART_ADVFEATURE_RXINV_ENABLE        ((uint32_t)USART_CR2_RXINV)         /*!< RX pin active level inversion enable  */
00566 /**
00567   * @}
00568   */
00569
00570 /** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
00571   * @{
00572   */
00573 #define UART_ADVFEATURE_DATAINV_DISABLE     (0x00000000U)                       /*!< Binary data inversion disable */
00574 #define UART_ADVFEATURE_DATAINV_ENABLE      ((uint32_t)USART_CR2_DATAINV)       /*!< Binary data inversion enable  */
00575 /**
00576   * @}
00577   */
00578
00579 /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
00580   * @{
00581   */
00582 #define UART_ADVFEATURE_SWAP_DISABLE        (0x00000000U)                       /*!< TX/RX pins swap disable */
00583 #define UART_ADVFEATURE_SWAP_ENABLE         ((uint32_t)USART_CR2_SWAP)          /*!< TX/RX pins swap enable  */
00584 /**
00585   * @}
00586   */
00587
00588 /** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
00589   * @{
00590   */
00591 #define UART_ADVFEATURE_OVERRUN_ENABLE      (0x00000000U)                       /*!< RX overrun enable  */
00592 #define UART_ADVFEATURE_OVERRUN_DISABLE     ((uint32_t)USART_CR3_OVRDIS)        /*!< RX overrun disable */
00593 /**
00594   * @}
00595   */
00596
00597 /** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
00598   * @{
00599   */
00600 #define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   (0x00000000U)                    /*!< RX Auto Baud rate detection enable  */
00601 #define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    ((uint32_t)USART_CR2_ABREN)      /*!< RX Auto Baud rate detection disable */
00602 /**
00603   * @}
00604   */
00605
00606 /** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
00607   * @{
00608   */
00609 #define UART_ADVFEATURE_DMA_ENABLEONRXERROR    (0x00000000U)                    /*!< DMA enable on Reception Error  */
00610 #define UART_ADVFEATURE_DMA_DISABLEONRXERROR   ((uint32_t)USART_CR3_DDRE)       /*!< DMA disable on Reception Error */
00611 /**
00612   * @}
00613   */
00614
00615 /** @defgroup UART_MSB_First   UART Advanced Feature MSB First
00616   * @{
00617   */
00618 #define UART_ADVFEATURE_MSBFIRST_DISABLE    (0x00000000U)                       /*!< Most significant bit sent/received first disable */
00619 #define UART_ADVFEATURE_MSBFIRST_ENABLE     ((uint32_t)USART_CR2_MSBFIRST)      /*!< Most significant bit sent/received first enable  */
00620 /**
00621   * @}
00622   */
00623
00624 /** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable
00625   * @{
00626   */
00627 #define UART_ADVFEATURE_STOPMODE_DISABLE    (0x00000000U)                       /*!< UART stop mode disable */
00628 #define UART_ADVFEATURE_STOPMODE_ENABLE     ((uint32_t)USART_CR1_UESM)          /*!< UART stop mode enable  */
00629 /**
00630   * @}
00631   */
00632
00633 /** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
00634   * @{
00635   */
00636 #define UART_ADVFEATURE_MUTEMODE_DISABLE    (0x00000000U)                       /*!< UART mute mode disable */
00637 #define UART_ADVFEATURE_MUTEMODE_ENABLE     ((uint32_t)USART_CR1_MME)           /*!< UART mute mode enable  */
00638 /**
00639   * @}
00640   */
00641
00642 /** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
00643   * @{
00644   */
00645 #define UART_CR2_ADDRESS_LSB_POS            ( 24U)                              /*!< UART address-matching LSB position in CR2 register */
00646 /**
00647   * @}
00648   */
00649
00650 /** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection
00651   * @{
00652   */
00653 #define UART_WAKEUP_ON_ADDRESS              (0x00000000U)                       /*!< UART wake-up on address                         */
00654 #define UART_WAKEUP_ON_STARTBIT             ((uint32_t)USART_CR3_WUS_1)         /*!< UART wake-up on start bit                       */
00655 #define UART_WAKEUP_ON_READDATA_NONEMPTY    ((uint32_t)USART_CR3_WUS)           /*!< UART wake-up on receive data register not empty */
00656 /**
00657   * @}
00658   */
00659
00660 /** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
00661   * @{
00662   */
00663 #define UART_DE_POLARITY_HIGH               (0x00000000U)                       /*!< Driver enable signal is active high */
00664 #define UART_DE_POLARITY_LOW                ((uint32_t)USART_CR3_DEP)           /*!< Driver enable signal is active low  */
00665 /**
00666   * @}
00667   */
00668
00669 /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
00670   * @{
00671   */
00672 #define UART_CR1_DEAT_ADDRESS_LSB_POS       ( 21U)                              /*!< UART Driver Enable assertion time LSB position in CR1 register */
00673 /**
00674   * @}
00675   */
00676
00677 /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
00678   * @{
00679   */
00680 #define UART_CR1_DEDT_ADDRESS_LSB_POS       ( 16U)                              /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
00681 /**
00682   * @}
00683   */
00684
00685 /** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
00686   * @{
00687   */
00688 #define UART_IT_MASK                        (0x001FU)                           /*!< UART interruptions flags mask */
00689 /**
00690   * @}
00691   */
00692
00693 /** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
00694   * @{
00695   */
00696 #define HAL_UART_TIMEOUT_VALUE              0x1FFFFFF                           /*!< UART polling-based communications time-out value */
00697 /**
00698   * @}
00699   */
00700
00701 /**
00702   * @}
00703   */
00704
00705 /* Exported macros -----------------------------------------------------------*/
00706 /** @defgroup UART_Exported_Macros UART Exported Macros
00707   * @{
00708   */
00709
00710 /** @brief  Reset UART handle states.
00711   * @param  __HANDLE__ UART handle.
00712   * @retval None
00713   */
00714 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00715                                                        (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
00716                                                        (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
00717                                                      } while(0U)
00718 /** @brief  Flush the UART Data registers.
00719   * @param  __HANDLE__ specifies the UART Handle.
00720   * @retval None
00721   */
00722 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
00723   do{                \
00724       SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
00725       SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
00726     }  while(0U)
00727
00728 /** @brief  Clear the specified UART pending flag.
00729   * @param  __HANDLE__ specifies the UART Handle.
00730   * @param  __FLAG__ specifies the flag to check.
00731   *          This parameter can be any combination of the following values:
00732   *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag
00733   *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag
00734   *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag
00735   *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag
00736   *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag
00737   *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag
00738   *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag  (not available on all devices)
00739   *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag
00740   *            @arg @ref UART_CLEAR_RTOF     Receiver Time Out Clear Flag
00741   *            @arg @ref UART_CLEAR_EOBF     End Of Block Clear Flag (not available on all devices)
00742   *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag
00743   *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag (not available on all devices)
00744   * @retval None
00745   */
00746 #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00747
00748 /** @brief  Clear the UART PE pending flag.
00749   * @param  __HANDLE__ specifies the UART Handle.
00750   * @retval None
00751   */
00752 #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
00753
00754 /** @brief  Clear the UART FE pending flag.
00755   * @param  __HANDLE__ specifies the UART Handle.
00756   * @retval None
00757   */
00758 #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
00759
00760 /** @brief  Clear the UART NE pending flag.
00761   * @param  __HANDLE__ specifies the UART Handle.
00762   * @retval None
00763   */
00764 #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
00765
00766 /** @brief  Clear the UART ORE pending flag.
00767   * @param  __HANDLE__ specifies the UART Handle.
00768   * @retval None
00769   */
00770 #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
00771
00772 /** @brief  Clear the UART IDLE pending flag.
00773   * @param  __HANDLE__ specifies the UART Handle.
00774   * @retval None
00775   */
00776 #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
00777
00778 /** @brief  Check whether the specified UART flag is set or not.
00779   * @param  __HANDLE__ specifies the UART Handle.
00780   * @param  __FLAG__ specifies the flag to check.
00781   *        This parameter can be one of the following values:
00782   *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
00783   *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
00784   *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag
00785   *            @arg @ref UART_FLAG_RWU   Receiver wake up flag
00786   *            @arg @ref UART_FLAG_SBKF  Send Break flag
00787   *            @arg @ref UART_FLAG_CMF   Character match flag
00788   *            @arg @ref UART_FLAG_BUSY  Busy flag
00789   *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag
00790   *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag
00791   *            @arg @ref UART_FLAG_EOBF  End of block flag
00792   *            @arg @ref UART_FLAG_RTOF  Receiver timeout flag
00793   *            @arg @ref UART_FLAG_CTS   CTS Change flag (not available for UART4 and UART5)
00794   *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag
00795   *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag
00796   *            @arg @ref UART_FLAG_TC    Transmission Complete flag
00797   *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag
00798   *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag
00799   *            @arg @ref UART_FLAG_ORE   Overrun Error flag
00800   *            @arg @ref UART_FLAG_NE    Noise Error flag
00801   *            @arg @ref UART_FLAG_FE    Framing Error flag
00802   *            @arg @ref UART_FLAG_PE    Parity Error flag
00803   * @retval The new state of __FLAG__ (TRUE or FALSE).
00804   */
00805 #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00806
00807 /** @brief  Enable the specified UART interrupt.
00808   * @param  __HANDLE__ specifies the UART Handle.
00809   * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
00810   *          This parameter can be one of the following values:
00811   *            @arg @ref UART_IT_WUF  Wakeup from stop mode interrupt
00812   *            @arg @ref UART_IT_CM   Character match interrupt
00813   *            @arg @ref UART_IT_CTS  CTS change interrupt
00814   *            @arg @ref UART_IT_LBD  LIN Break detection interrupt
00815   *            @arg @ref UART_IT_TXE  Transmit Data Register empty interrupt
00816   *            @arg @ref UART_IT_TC   Transmission complete interrupt
00817   *            @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
00818   *            @arg @ref UART_IT_IDLE Idle line detection interrupt
00819   *            @arg @ref UART_IT_PE   Parity Error interrupt
00820   *            @arg @ref UART_IT_ERR  Error interrupt (Frame error, noise error, overrun error)
00821   * @retval None
00822   */
00823 #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00824                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00825                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
00826
00827
00828 /** @brief  Disable the specified UART interrupt.
00829   * @param  __HANDLE__ specifies the UART Handle.
00830   * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
00831   *          This parameter can be one of the following values:
00832   *            @arg @ref UART_IT_WUF  Wakeup from stop mode interrupt
00833   *            @arg @ref UART_IT_CM   Character match interrupt
00834   *            @arg @ref UART_IT_CTS  CTS change interrupt
00835   *            @arg @ref UART_IT_LBD  LIN Break detection interrupt
00836   *            @arg @ref UART_IT_TXE  Transmit Data Register empty interrupt
00837   *            @arg @ref UART_IT_TC   Transmission complete interrupt
00838   *            @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
00839   *            @arg @ref UART_IT_IDLE Idle line detection interrupt
00840   *            @arg @ref UART_IT_PE   Parity Error interrupt
00841   *            @arg @ref UART_IT_ERR  Error interrupt (Frame error, noise error, overrun error)
00842   * @retval None
00843   */
00844 #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00845                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00846                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
00847
00848 /** @brief  Check whether the specified UART interrupt has occurred or not.
00849   * @param  __HANDLE__ specifies the UART Handle.
00850   * @param  __IT__ specifies the UART interrupt to check.
00851   *          This parameter can be one of the following values:
00852   *            @arg @ref UART_IT_WUF  Wakeup from stop mode interrupt
00853   *            @arg @ref UART_IT_CM   Character match interrupt
00854   *            @arg @ref UART_IT_CTS  CTS change interrupt (not available for UART4 and UART5)
00855   *            @arg @ref UART_IT_LBD  LIN Break detection interrupt
00856   *            @arg @ref UART_IT_TXE  Transmit Data Register empty interrupt
00857   *            @arg @ref UART_IT_TC   Transmission complete interrupt
00858   *            @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
00859   *            @arg @ref UART_IT_IDLE Idle line detection interrupt
00860   *            @arg @ref UART_IT_ORE  Overrun Error interrupt
00861   *            @arg @ref UART_IT_NE   Noise Error interrupt
00862   *            @arg @ref UART_IT_FE   Framing Error interrupt
00863   *            @arg @ref UART_IT_PE   Parity Error interrupt
00864   * @retval The new state of __IT__ (TRUE or FALSE).
00865   */
00866 #define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
00867
00868 /** @brief  Check whether the specified UART interrupt source is enabled or not.
00869   * @param  __HANDLE__ specifies the UART Handle.
00870   * @param  __IT__ specifies the UART interrupt source to check.
00871   *          This parameter can be one of the following values:
00872   *            @arg @ref UART_IT_WUF  Wakeup from stop mode interrupt
00873   *            @arg @ref UART_IT_CM   Character match interrupt
00874   *            @arg @ref UART_IT_CTS  CTS change interrupt (not available for UART4 and UART5)
00875   *            @arg @ref UART_IT_LBD  LIN Break detection interrupt
00876   *            @arg @ref UART_IT_TXE  Transmit Data Register empty interrupt
00877   *            @arg @ref UART_IT_TC   Transmission complete interrupt
00878   *            @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
00879   *            @arg @ref UART_IT_IDLE Idle line detection interrupt
00880   *            @arg @ref UART_IT_ERR  Error interrupt (Frame error, noise error, overrun error)
00881   *            @arg @ref UART_IT_PE   Parity Error interrupt
00882   * @retval The new state of __IT__ (TRUE or FALSE).
00883   */
00884 #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
00885                                                        (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & UART_IT_MASK)))
00886
00887 /** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
00888   * @param  __HANDLE__ specifies the UART Handle.
00889   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
00890   *                       to clear the corresponding interrupt
00891   *          This parameter can be one of the following values:
00892   *            @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
00893   *            @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
00894   *            @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
00895   *            @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
00896   *            @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
00897   *            @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
00898   *            @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
00899   *            @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
00900   *            @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag
00901   *            @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag
00902   *            @arg @ref UART_CLEAR_CMF Character Match Clear Flag
00903   *            @arg @ref UART_CLEAR_WUF  Wake Up from stop mode Clear Flag
00904   * @retval None
00905   */
00906 #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00907
00908 /** @brief  Set a specific UART request flag.
00909   * @param  __HANDLE__ specifies the UART Handle.
00910   * @param  __REQ__ specifies the request flag to set
00911   *          This parameter can be one of the following values:
00912   *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
00913   *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request
00914   *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
00915   *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
00916   *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
00917   * @retval None
00918   */
00919 #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
00920
00921 /** @brief  Enable the UART one bit sample method.
00922   * @param  __HANDLE__ specifies the UART Handle.
00923   * @retval None
00924   */
00925 #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00926
00927 /** @brief  Disable the UART one bit sample method.
00928   * @param  __HANDLE__ specifies the UART Handle.
00929   * @retval None
00930   */
00931 #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00932
00933 /** @brief  Enable UART.
00934   * @param  __HANDLE__ specifies the UART Handle.
00935   * @retval None
00936   */
00937 #define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00938
00939 /** @brief  Disable UART.
00940   * @param  __HANDLE__ specifies the UART Handle.
00941   * @retval None
00942   */
00943 #define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00944
00945 /** @brief  Enable CTS flow control.
00946   * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
00947   *         without need to call HAL_UART_Init() function.
00948   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00949   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
00950   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00951   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00952   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
00953   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
00954   * @param  __HANDLE__ specifies the UART Handle.
00955   * @retval None
00956   */
00957 #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
00958   do{                                                      \
00959     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
00960     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
00961   } while(0U)
00962
00963 /** @brief  Disable CTS flow control.
00964   * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
00965   *         without need to call HAL_UART_Init() function.
00966   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00967   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
00968   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00969   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00970   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
00971   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
00972   * @param  __HANDLE__ specifies the UART Handle.
00973   * @retval None
00974   */
00975 #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
00976   do{                                                       \
00977     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
00978     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
00979   } while(0U)
00980
00981 /** @brief  Enable RTS flow control.
00982   * @note   This macro allows to enable RTS hardware flow control for a given UART instance,
00983   *         without need to call HAL_UART_Init() function.
00984   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00985   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
00986   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00987   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00988   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
00989   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
00990   * @param  __HANDLE__ specifies the UART Handle.
00991   * @retval None
00992   */
00993 #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
00994   do{                                                     \
00995     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
00996     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
00997   } while(0U)
00998
00999 /** @brief  Disable RTS flow control.
01000   * @note   This macro allows to disable RTS hardware flow control for a given UART instance,
01001   *         without need to call HAL_UART_Init() function.
01002   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01003   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
01004   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01005   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01006   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
01007   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01008   * @param  __HANDLE__ specifies the UART Handle.
01009   * @retval None
01010   */
01011 #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
01012   do{                                                      \
01013     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
01014     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
01015   } while(0U)
01016
01017 /**
01018   * @}
01019   */
01020
01021 /* Private macros --------------------------------------------------------*/
01022 /** @defgroup UART_Private_Macros   UART Private Macros
01023   * @{
01024   */
01025 /** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
01026   * @param  __PCLK__ UART clock.
01027   * @param  __BAUD__ Baud rate set by the user.
01028   * @retval Division result
01029   */
01030 #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__)   ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
01031
01032 /** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
01033   * @param  __PCLK__ UART clock.
01034   * @param  __BAUD__ Baud rate set by the user.
01035   * @retval Division result
01036   */
01037 #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__)  (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))
01038
01039 /** @brief  Check UART Baud rate.
01040   * @param  __BAUDRATE__ Baudrate specified by the user.
01041   *         The maximum Baud Rate is derived from the maximum clock on F3 (i.e. 72 MHz)
01042   *         divided by the smallest oversampling used on the USART (i.e. 8)
01043   * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
01044   */
01045 #define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001U)
01046
01047 /** @brief  Check UART assertion time.
01048   * @param  __TIME__ 5-bit value assertion time.
01049   * @retval Test result (TRUE or FALSE).
01050   */
01051 #define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1FU)
01052
01053 /** @brief  Check UART deassertion time.
01054   * @param  __TIME__ 5-bit value deassertion time.
01055   * @retval Test result (TRUE or FALSE).
01056   */
01057 #define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
01058
01059 /**
01060   * @brief Ensure that UART frame number of stop bits is valid.
01061   * @param __STOPBITS__ UART frame number of stop bits.
01062   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
01063   */
01064 #define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
01065                                         ((__STOPBITS__) == UART_STOPBITS_1)   || \
01066                                         ((__STOPBITS__) == UART_STOPBITS_1_5) || \
01067                                         ((__STOPBITS__) == UART_STOPBITS_2))
01068
01069 /**
01070   * @brief Ensure that UART frame parity is valid.
01071   * @param __PARITY__ UART frame parity.
01072   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
01073   */
01074 #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
01075                                     ((__PARITY__) == UART_PARITY_EVEN) || \
01076                                     ((__PARITY__) == UART_PARITY_ODD))
01077
01078 /**
01079   * @brief Ensure that UART hardware flow control is valid.
01080   * @param __CONTROL__ UART hardware flow control.
01081   * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
01082   */
01083 #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
01084                                    (((__CONTROL__) == UART_HWCONTROL_NONE) || \
01085                                     ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
01086                                     ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
01087                                     ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
01088
01089 /**
01090   * @brief Ensure that UART communication mode is valid.
01091   * @param __MODE__ UART communication mode.
01092   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01093   */
01094 #define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
01095
01096 /**
01097   * @brief Ensure that UART state is valid.
01098   * @param __STATE__ UART state.
01099   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
01100   */
01101 #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
01102                                   ((__STATE__) == UART_STATE_ENABLE))
01103
01104 /**
01105   * @brief Ensure that UART oversampling is valid.
01106   * @param __SAMPLING__ UART oversampling.
01107   * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
01108   */
01109 #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
01110                                             ((__SAMPLING__) == UART_OVERSAMPLING_8))
01111
01112 /**
01113   * @brief Ensure that UART frame sampling is valid.
01114   * @param __ONEBIT__ UART frame sampling.
01115   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
01116   */
01117 #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
01118                                             ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
01119
01120 /**
01121   * @brief Ensure that Address Length detection parameter is valid.
01122   * @param __ADDRESS__ UART Adress length value.
01123   * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
01124   */
01125 #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
01126                                                    ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
01127
01128 /**
01129   * @brief Ensure that UART auto Baud rate detection mode is valid.
01130   * @param __MODE__ UART auto Baud rate detection mode.
01131   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01132   */
01133 #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
01134                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
01135                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
01136                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
01137
01138 /**
01139   * @brief Ensure that UART receiver timeout setting is valid.
01140   * @param __TIMEOUT__ UART receiver timeout setting.
01141   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
01142   */
01143 #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
01144                                                ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
01145
01146 /**
01147   * @brief Ensure that UART LIN state is valid.
01148   * @param __LIN__ UART LIN state.
01149   * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
01150   */
01151 #define IS_UART_LIN(__LIN__)            (((__LIN__) == UART_LIN_DISABLE) || \
01152                                          ((__LIN__) == UART_LIN_ENABLE))
01153
01154 /**
01155   * @brief Ensure that UART LIN break detection length is valid.
01156   * @param __LENGTH__ UART LIN break detection length.
01157   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
01158   */
01159 #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
01160                                                      ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
01161
01162 /**
01163   * @brief Ensure that UART DMA TX state is valid.
01164   * @param __DMATX__ UART DMA TX state.
01165   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
01166   */
01167 #define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
01168                                        ((__DMATX__) == UART_DMA_TX_ENABLE))
01169
01170 /**
01171   * @brief Ensure that UART DMA RX state is valid.
01172   * @param __DMARX__ UART DMA RX state.
01173   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
01174   */
01175 #define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
01176                                        ((__DMARX__) == UART_DMA_RX_ENABLE))
01177
01178 /**
01179   * @brief Ensure that UART half-duplex state is valid.
01180   * @param __HDSEL__ UART half-duplex state.
01181   * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
01182   */
01183 #define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
01184                                             ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
01185
01186 /**
01187   * @brief Ensure that UART wake-up method is valid.
01188   * @param __WAKEUP__ UART wake-up method .
01189   * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
01190   */
01191 #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
01192                                           ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
01193
01194 /**
01195   * @brief Ensure that UART advanced features initialization is valid.
01196   * @param __INIT__ UART advanced features initialization.
01197   * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
01198   */
01199 #define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
01200                                                             UART_ADVFEATURE_TXINVERT_INIT          | \
01201                                                             UART_ADVFEATURE_RXINVERT_INIT          | \
01202                                                             UART_ADVFEATURE_DATAINVERT_INIT        | \
01203                                                             UART_ADVFEATURE_SWAP_INIT              | \
01204                                                             UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
01205                                                             UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
01206                                                             UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
01207                                                             UART_ADVFEATURE_MSBFIRST_INIT))
01208
01209 /**
01210   * @brief Ensure that UART frame TX inversion setting is valid.
01211   * @param __TXINV__ UART frame TX inversion setting.
01212   * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
01213   */
01214 #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
01215                                              ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
01216
01217 /**
01218   * @brief Ensure that UART frame RX inversion setting is valid.
01219   * @param __RXINV__ UART frame RX inversion setting.
01220   * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
01221   */
01222 #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
01223                                              ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
01224
01225 /**
01226   * @brief Ensure that UART frame data inversion setting is valid.
01227   * @param __DATAINV__ UART frame data inversion setting.
01228   * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
01229   */
01230 #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
01231                                                  ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
01232
01233 /**
01234   * @brief Ensure that UART frame RX/TX pins swap setting is valid.
01235   * @param __SWAP__ UART frame RX/TX pins swap setting.
01236   * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
01237   */
01238 #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
01239                                            ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
01240
01241 /**
01242   * @brief Ensure that UART frame overrun setting is valid.
01243   * @param __OVERRUN__ UART frame overrun setting.
01244   * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
01245   */
01246 #define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
01247                                           ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
01248
01249 /**
01250   * @brief Ensure that UART auto Baud rate state is valid.
01251   * @param __AUTOBAUDRATE__ UART auto Baud rate state.
01252   * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
01253   */
01254 #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)  (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
01255                                                             ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
01256
01257 /**
01258   * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
01259   * @param __DMA__ UART DMA enabling or disabling on error setting.
01260   * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
01261   */
01262 #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
01263                                                    ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
01264
01265 /**
01266   * @brief Ensure that UART frame MSB first setting is valid.
01267   * @param __MSBFIRST__ UART frame MSB first setting.
01268   * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
01269   */
01270 #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
01271                                                    ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
01272
01273 /**
01274   * @brief Ensure that UART stop mode state is valid.
01275   * @param __STOPMODE__ UART stop mode state.
01276   * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
01277   */
01278 #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
01279                                                    ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
01280
01281 /**
01282   * @brief Ensure that UART mute mode state is valid.
01283   * @param __MUTE__ UART mute mode state.
01284   * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
01285   */
01286 #define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
01287                                            ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
01288
01289 /**
01290   * @brief Ensure that UART wake-up selection is valid.
01291   * @param __WAKE__ UART wake-up selection.
01292   * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
01293   */
01294 #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
01295                                             ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
01296                                             ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
01297
01298 /**
01299   * @brief Ensure that UART driver enable polarity is valid.
01300   * @param __POLARITY__ UART driver enable polarity.
01301   * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
01302   */
01303 #define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
01304                                               ((__POLARITY__) == UART_DE_POLARITY_LOW))
01305
01306 /**
01307   * @brief Ensure that UART request parameter is valid.
01308   * @param __PARAM__ UART request parameter.
01309   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
01310   */
01311 #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
01312                                               ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
01313                                               ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
01314                                               ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
01315                                               ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
01316
01317 /**
01318   * @}
01319   */
01320
01321 /* Include UART HAL Extended module */
01322 #include "stm32f3xx_hal_uart_ex.h"
01323
01324 /* Exported functions --------------------------------------------------------*/
01325 /** @addtogroup UART_Exported_Functions UART Exported Functions
01326   * @{
01327   */
01328
01329 /** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
01330   * @{
01331   */
01332
01333 /* Initialization and de-initialization functions  ****************************/
01334 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
01335 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
01336 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
01337 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
01338 HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
01339 void HAL_UART_MspInit(UART_HandleTypeDef *huart);
01340 void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
01341
01342 /**
01343   * @}
01344   */
01345
01346 /** @addtogroup UART_Exported_Functions_Group2 IO operation functions
01347   * @{
01348   */
01349
01350 /* IO operation functions *****************************************************/
01351 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01352 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01353 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01354 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01355 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01356 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01357 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
01358 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
01359 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
01360 /* Transfer Abort functions */
01361 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
01362 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
01363 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
01364 HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
01365 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
01366 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
01367
01368 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
01369 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
01370 void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
01371 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
01372 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
01373 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
01374 void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart);
01375 void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart);
01376 void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart);
01377
01378 /**
01379   * @}
01380   */
01381
01382 /** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
01383   * @{
01384   */
01385
01386 /* Peripheral Control functions  ************************************************/
01387 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
01388 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
01389 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
01390 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
01391 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
01392 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
01393
01394 /**
01395   * @}
01396   */
01397
01398 /** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
01399   * @{
01400   */
01401
01402 /* Peripheral State and Errors functions  **************************************************/
01403 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
01404 uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
01405
01406 /**
01407   * @}
01408   */
01409
01410 /**
01411   * @}
01412   */
01413
01414 /* Private functions -----------------------------------------------------------*/
01415 /** @addtogroup UART_Private_Functions UART Private Functions
01416   * @{
01417   */
01418 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
01419 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
01420 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
01421 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
01422 HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
01423 HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
01424 HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
01425 void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
01426
01427 /**
01428   * @}
01429   */
01430
01431 /**
01432   * @}
01433   */
01434
01435 /**
01436   * @}
01437   */
01438
01439 #ifdef __cplusplus
01440 }
01441 #endif
01442
01443 #endif /* __STM32F3xx_HAL_UART_H */
01444
01445 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
01446
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_uart_ex.c Source File

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stm32f3xx_hal_uart_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_uart_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended UART HAL module driver.
00006   *          This file provides firmware functions to manage the following extended
00007   *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   *
00012   @verbatim
00013   ==============================================================================
00014                ##### UART peripheral extended features  #####
00015   ==============================================================================
00016
00017     (#) Declare a UART_HandleTypeDef handle structure.
00018
00019     (#) For the UART RS485 Driver Enable mode, initialize the UART registers
00020         by calling the HAL_RS485Ex_Init() API.
00021
00022
00023   @endverbatim
00024   ******************************************************************************
00025   * @attention
00026   *
00027   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00028   *
00029   * Redistribution and use in source and binary forms, with or without modification,
00030   * are permitted provided that the following conditions are met:
00031   *   1. Redistributions of source code must retain the above copyright notice,
00032   *      this list of conditions and the following disclaimer.
00033   *   2. Redistributions in binary form must reproduce the above copyright notice,
00034   *      this list of conditions and the following disclaimer in the documentation
00035   *      and/or other materials provided with the distribution.
00036   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00037   *      may be used to endorse or promote products derived from this software
00038   *      without specific prior written permission.
00039   *
00040   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00041   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00042   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00043   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00044   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00045   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00046   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00047   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00048   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00049   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00050   *
00051   ******************************************************************************
00052   */
00053
00054 /* Includes ------------------------------------------------------------------*/
00055 #include "stm32f3xx_hal.h"
00056
00057 /** @addtogroup STM32F3xx_HAL_Driver
00058   * @{
00059   */
00060
00061 /** @defgroup UARTEx UARTEx
00062   * @brief UART Extension HAL module driver
00063   * @{
00064   */
00065
00066 #ifdef HAL_UART_MODULE_ENABLED
00067
00068 /* Private typedef -----------------------------------------------------------*/
00069 /* Private define ------------------------------------------------------------*/
00070 /* Private macros ------------------------------------------------------------*/
00071 /* Private variables ---------------------------------------------------------*/
00072 /* Private function prototypes -----------------------------------------------*/
00073 /* Exported functions --------------------------------------------------------*/
00074
00075 /** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
00076   * @{
00077   */
00078
00079 /** @defgroup UARTEx_Exported_Functions_Group1 Extended Initialization and de-initialization functions
00080   * @brief    Extended Initialization and Configuration Functions
00081   *
00082 @verbatim
00083 ===============================================================================
00084             ##### Initialization and Configuration functions #####
00085  ==============================================================================
00086     [..]
00087     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00088     in asynchronous mode.
00089       (+) For the asynchronous mode the parameters below can be configured:
00090         (++) Baud Rate
00091         (++) Word Length (Fixed to 8-bits only for LIN mode)
00092         (++) Stop Bit
00093         (++) Parity
00094         (++) Hardware flow control
00095         (++) Receiver/transmitter modes
00096         (++) Over Sampling Method
00097         (++) One-Bit Sampling Method
00098       (+) For the asynchronous mode, the following advanced features can be configured as well:
00099         (++) TX and/or RX pin level inversion
00100         (++) data logical level inversion
00101         (++) RX and TX pins swap
00102         (++) RX overrun detection disabling
00103         (++) DMA disabling on RX error
00104         (++) MSB first on communication line
00105         (++) auto Baud rate detection
00106     [..]
00107     The HAL_RS485Ex_Init() API follows respectively the UART RS485 mode
00108     configuration procedures (details for the procedures are available in reference manual).
00109
00110 @endverbatim
00111   * @{
00112   */
00113
00114 /*
00115   Additional Table:  If the parity is enabled, then the MSB bit of the data written
00116                      in the data register is transmitted but is changed by the parity bit.
00117                      According to device capability (support or not of 7-bit word length),
00118                      frame length is either defined by the M bit (8-bits or 9-bits)
00119                      or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
00120                      Possible UART frame formats are as listed in the following table:
00121
00122       Table 1. UART frame format.
00123       +-----------------------------------------------------------------------+
00124       |       M bit       |  PCE bit  |             UART frame                |
00125       |-------------------|-----------|---------------------------------------|
00126       |         0         |     0     |    | SB |    8-bit data   | STB |     |
00127       |-------------------|-----------|---------------------------------------|
00128       |         0         |     1     |    | SB | 7-bit data | PB | STB |     |
00129       |-------------------|-----------|---------------------------------------|
00130       |         1         |     0     |    | SB |    9-bit data   | STB |     |
00131       |-------------------|-----------|---------------------------------------|
00132       |         1         |     1     |    | SB | 8-bit data | PB | STB |     |
00133       +-----------------------------------------------------------------------+
00134       |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
00135       |---------|---------|-----------|---------------------------------------|
00136       |    0    |    0    |     0     |    | SB |    8 bit data   | STB |     |
00137       |---------|---------|-----------|---------------------------------------|
00138       |    0    |    0    |     1     |    | SB | 7 bit data | PB | STB |     |
00139       |---------|---------|-----------|---------------------------------------|
00140       |    0    |    1    |     0     |    | SB |    9 bit data   | STB |     |
00141       |---------|---------|-----------|---------------------------------------|
00142       |    0    |    1    |     1     |    | SB | 8 bit data | PB | STB |     |
00143       |---------|---------|-----------|---------------------------------------|
00144       |    1    |    0    |     0     |    | SB |    7 bit data   | STB |     |
00145       |---------|---------|-----------|---------------------------------------|
00146       |    1    |    0    |     1     |    | SB | 6 bit data | PB | STB |     |
00147       +-----------------------------------------------------------------------+
00148
00149 */
00150
00151 /**
00152   * @brief Initialize the RS485 Driver enable feature according to the specified
00153   *         parameters in the UART_InitTypeDef and creates the associated handle.
00154   * @param huart UART handle.
00155   * @param Polarity select the driver enable polarity.
00156   *        This parameter can be one of the following values:
00157   *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
00158   *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
00159   * @param AssertionTime Driver Enable assertion time:
00160   *                         5-bit value defining the time between the activation of the DE (Driver Enable)
00161   *                         signal and the beginning of the start bit. It is expressed in sample time
00162   *                         units (1/8 or 1/16 bit time, depending on the oversampling rate)
00163   * @param DeassertionTime Driver Enable deassertion time:
00164   *                         5-bit value defining the time between the end of the last stop bit, in a
00165   *                         transmitted message, and the de-activation of the DE (Driver Enable) signal.
00166   *                         It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
00167   *                         oversampling rate).
00168   * @retval HAL status
00169   */
00170 HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
00171 {
00172   uint32_t temp = 0x0U;
00173
00174   /* Check the UART handle allocation */
00175   if(huart == NULL)
00176   {
00177     return HAL_ERROR;
00178   }
00179   /* Check the Driver Enable UART instance */
00180   assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
00181
00182   /* Check the Driver Enable polarity */
00183   assert_param(IS_UART_DE_POLARITY(Polarity));
00184
00185   /* Check the Driver Enable assertion time */
00186   assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
00187
00188   /* Check the Driver Enable deassertion time */
00189   assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
00190
00191   if(huart->gState == HAL_UART_STATE_RESET)
00192   {
00193     /* Allocate lock resource and initialize it */
00194     huart->Lock = HAL_UNLOCKED;
00195
00196     /* Init the low level hardware : GPIO, CLOCK, CORTEX */
00197     HAL_UART_MspInit(huart);
00198   }
00199
00200   huart->gState = HAL_UART_STATE_BUSY;
00201
00202   /* Disable the Peripheral */
00203   __HAL_UART_DISABLE(huart);
00204
00205   /* Set the UART Communication parameters */
00206   if (UART_SetConfig(huart) == HAL_ERROR)
00207   {
00208     return HAL_ERROR;
00209   }
00210
00211   if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00212   {
00213     UART_AdvFeatureConfig(huart);
00214   }
00215
00216   /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
00217   SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
00218
00219   /* Set the Driver Enable polarity */
00220   MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
00221
00222   /* Set the Driver Enable assertion and deassertion times */
00223   temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
00224   temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
00225   MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);
00226
00227   /* Enable the Peripheral */
00228   __HAL_UART_ENABLE(huart);
00229
00230   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00231   return (UART_CheckIdleState(huart));
00232 }
00233
00234
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup UARTEx_Exported_Functions_Group2 Extended IO operation function
00240   * @brief    Extended UART Interrupt handling function
00241   *
00242 @verbatim
00243  ===============================================================================
00244                       ##### IO operation function #####
00245  ===============================================================================
00246     [..]
00247     This subsection provides functions allowing to manage the UART interrupts
00248     and to handle Wake up interrupt call-back.
00249
00250     (#) Callback provided in No_Blocking mode:
00251         (++) HAL_UARTEx_WakeupCallback()
00252
00253 @endverbatim
00254   * @{
00255   */
00256
00257
00258 /**
00259   * @brief  UART wakeup from Stop mode callback.
00260   * @param  huart UART handle.
00261   * @retval None
00262   */
00263 __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
00264 {
00265   /* Prevent unused argument(s) compilation warning */
00266   UNUSED(huart);
00267
00268   /* NOTE : This function should not be modified, when the callback is needed,
00269             the HAL_UARTEx_WakeupCallback can be implemented in the user file.
00270    */
00271 }
00272
00273 /**
00274   * @}
00275   */
00276
00277
00278 /** @defgroup UARTEx_Exported_Functions_Group3 Extended Peripheral Control functions
00279   * @brief    Extended Peripheral Control functions
00280   *
00281 @verbatim
00282  ===============================================================================
00283                       ##### Peripheral Control functions #####
00284  ===============================================================================
00285     [..]
00286     This subsection provides extended functions allowing to control the UART.
00287      (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API sets Wakeup from Stop mode interrupt flag selection
00288      (+) HAL_UARTEx_EnableStopMode() API allows the UART to wake up the MCU from Stop mode as
00289          long as UART clock is HSI or LSE
00290      (+) HAL_UARTEx_DisableStopMode() API disables the above feature
00291      (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
00292          detection length to more than 4 bits for multiprocessor address mark wake up.
00293 @endverbatim
00294   * @{
00295   */
00296
00297 /**
00298   * @brief Set Wakeup from Stop mode interrupt flag selection.
00299   * @param huart UART handle.
00300   * @param WakeUpSelection address match, Start Bit detection or RXNE bit status.
00301   * This parameter can be one of the following values:
00302   *      @arg @ref UART_WAKEUP_ON_ADDRESS
00303   *      @arg @ref UART_WAKEUP_ON_STARTBIT
00304   *      @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
00305   * @retval HAL status
00306   */
00307 HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
00308 {
00309   HAL_StatusTypeDef status = HAL_OK;
00310   uint32_t tickstart = 0U;
00311
00312   /* check the wake-up from stop mode UART instance */
00313   assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
00314   /* check the wake-up selection parameter */
00315   assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
00316
00317   /* Process Locked */
00318   __HAL_LOCK(huart);
00319
00320   huart->gState = HAL_UART_STATE_BUSY;
00321
00322   /* Disable the Peripheral */
00323   __HAL_UART_DISABLE(huart);
00324
00325   /* Set the wake-up selection scheme */
00326   MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
00327
00328   if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
00329   {
00330     UART_Wakeup_AddressConfig(huart, WakeUpSelection);
00331   }
00332
00333   /* Enable the Peripheral */
00334   __HAL_UART_ENABLE(huart);
00335
00336   /* Init tickstart for timeout managment*/
00337   tickstart = HAL_GetTick();
00338
00339   /* Wait until REACK flag is set */
00340   if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
00341   {
00342     status = HAL_TIMEOUT;
00343   }
00344   else
00345   {
00346     /* Initialize the UART State */
00347     huart->gState = HAL_UART_STATE_READY;
00348   }
00349
00350   /* Process Unlocked */
00351   __HAL_UNLOCK(huart);
00352
00353   return status;
00354 }
00355
00356
00357 /**
00358   * @brief Enable UART Stop Mode.
00359   * @note  The UART is able to wake up the MCU from Stop mode as long as UART clock is HSI or LSE.
00360   * @param huart UART handle.
00361   * @retval HAL status
00362   */
00363 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
00364 {
00365   /* Check parameter */
00366   assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
00367
00368   /* Process Locked */
00369   __HAL_LOCK(huart);
00370
00371   huart->gState = HAL_UART_STATE_BUSY;
00372
00373   /* Set UESM bit */
00374   SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
00375
00376   huart->gState = HAL_UART_STATE_READY;
00377
00378   /* Process Unlocked */
00379   __HAL_UNLOCK(huart);
00380
00381   return HAL_OK;
00382 }
00383
00384 /**
00385   * @brief Disable UART Stop Mode.
00386   * @param huart UART handle.
00387   * @retval HAL status
00388   */
00389 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
00390 {
00391   /* Check parameter */
00392   assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
00393
00394   /* Process Locked */
00395   __HAL_LOCK(huart);
00396
00397   huart->gState = HAL_UART_STATE_BUSY;
00398
00399   /* Clear UESM bit */
00400   CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
00401
00402   huart->gState = HAL_UART_STATE_READY;
00403
00404   /* Process Unlocked */
00405   __HAL_UNLOCK(huart);
00406
00407   return HAL_OK;
00408 }
00409
00410 /**
00411   * @brief By default in multiprocessor mode, when the wake up method is set
00412   *        to address mark, the UART handles only 4-bit long addresses detection;
00413   *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
00414   *        long).
00415   * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
00416   *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
00417   * @param huart UART handle.
00418   * @param AddressLength this parameter can be one of the following values:
00419   *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
00420   *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
00421   * @retval HAL status
00422   */
00423 HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
00424 {
00425   /* Check the UART handle allocation */
00426   if(huart == NULL)
00427   {
00428     return HAL_ERROR;
00429   }
00430
00431   /* Check the address length parameter */
00432   assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
00433
00434   huart->gState = HAL_UART_STATE_BUSY;
00435
00436   /* Disable the Peripheral */
00437   __HAL_UART_DISABLE(huart);
00438
00439   /* Set the address length */
00440   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
00441
00442   /* Enable the Peripheral */
00443   __HAL_UART_ENABLE(huart);
00444
00445   /* TEACK and/or REACK to check before moving huart->gState to Ready */
00446   return (UART_CheckIdleState(huart));
00447 }
00448
00449
00450
00451 /**
00452   * @}
00453   */
00454
00455 /**
00456   * @}
00457   */
00458
00459 #endif /* HAL_UART_MODULE_ENABLED */
00460
00461 /**
00462   * @}
00463   */
00464
00465 /**
00466   * @}
00467   */
00468
00469 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_uart_ex.h Source File

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stm32f3xx_hal_uart_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_uart_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UART HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_UART_EX_H
00038 #define __STM32F3xx_HAL_UART_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup UARTEx
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /* Exported constants --------------------------------------------------------*/
00057 /** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
00058   * @{
00059   */
00060
00061 /** @defgroup UARTEx_Word_Length UARTEx Word Length
00062   * @{
00063   */
00064 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00065     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00066     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00067 #define UART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long UART frame */
00068 #define UART_WORDLENGTH_8B                  (0x00000000U)              /*!< 8-bit long UART frame */
00069 #define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long UART frame */
00070 #else
00071 #define UART_WORDLENGTH_8B                  (0x00000000U)              /*!< 8-bit long UART frame */
00072 #define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)    /*!< 9-bit long UART frame */
00073 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00074        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00075        /* STM32F301x8 || STM32F302x8 || STM32F318xx   */
00076 /**
00077   * @}
00078   */
00079
00080 /**
00081   * @}
00082   */
00083
00084 /* Exported macros -----------------------------------------------------------*/
00085 /* Exported functions --------------------------------------------------------*/
00086 /** @addtogroup UARTEx_Exported_Functions
00087   * @{
00088   */
00089
00090 /** @addtogroup UARTEx_Exported_Functions_Group1
00091   * @{
00092   */
00093
00094 /* Initialization and de-initialization functions  ****************************/
00095 HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
00096
00097 /**
00098   * @}
00099   */
00100
00101 /* IO operation functions *****************************************************/
00102
00103 /** @addtogroup UARTEx_Exported_Functions_Group3
00104   * @{
00105   */
00106
00107 /* Peripheral Control functions  **********************************************/
00108 HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
00109 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
00110 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
00111 HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
00112 void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
00113
00114 /**
00115   * @}
00116   */
00117
00118 /**
00119   * @}
00120   */
00121
00122 /* Private macros ------------------------------------------------------------*/
00123 /** @defgroup UARTEx_Private_Macros UARTEx Private Macros
00124   * @{
00125   */
00126
00127 /** @brief  Report the UART clock source.
00128   * @param  __HANDLE__ specifies the UART Handle.
00129   * @param  __CLOCKSOURCE__ output variable.
00130   * @retval UART clocking source, written in __CLOCKSOURCE__.
00131   */
00132 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00133     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
00134 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00135   do {                                                        \
00136     if((__HANDLE__)->Instance == USART1)                      \
00137     {                                                         \
00138        switch(__HAL_RCC_GET_USART1_SOURCE())                  \
00139        {                                                      \
00140         case RCC_USART1CLKSOURCE_PCLK2:                       \
00141           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
00142           break;                                              \
00143         case RCC_USART1CLKSOURCE_HSI:                         \
00144           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00145           break;                                              \
00146         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00147           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00148           break;                                              \
00149         case RCC_USART1CLKSOURCE_LSE:                         \
00150           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00151           break;                                              \
00152         default:                                              \
00153           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00154           break;                                              \
00155        }                                                      \
00156     }                                                         \
00157     else if((__HANDLE__)->Instance == USART2)                 \
00158     {                                                         \
00159        switch(__HAL_RCC_GET_USART2_SOURCE())                  \
00160        {                                                      \
00161         case RCC_USART2CLKSOURCE_PCLK1:                       \
00162           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00163           break;                                              \
00164         case RCC_USART2CLKSOURCE_HSI:                         \
00165           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00166           break;                                              \
00167         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00168           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00169           break;                                              \
00170         case RCC_USART2CLKSOURCE_LSE:                         \
00171           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00172           break;                                              \
00173         default:                                              \
00174           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00175           break;                                              \
00176        }                                                      \
00177     }                                                         \
00178     else if((__HANDLE__)->Instance == USART3)                 \
00179     {                                                         \
00180        switch(__HAL_RCC_GET_USART3_SOURCE())                  \
00181        {                                                      \
00182         case RCC_USART3CLKSOURCE_PCLK1:                       \
00183           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00184           break;                                              \
00185         case RCC_USART3CLKSOURCE_HSI:                         \
00186           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00187           break;                                              \
00188         case RCC_USART3CLKSOURCE_SYSCLK:                      \
00189           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00190           break;                                              \
00191         case RCC_USART3CLKSOURCE_LSE:                         \
00192           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00193           break;                                              \
00194         default:                                              \
00195           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00196           break;                                              \
00197        }                                                      \
00198     }                                                         \
00199     else if((__HANDLE__)->Instance == UART4)                  \
00200     {                                                         \
00201        switch(__HAL_RCC_GET_UART4_SOURCE())                   \
00202        {                                                      \
00203         case RCC_UART4CLKSOURCE_PCLK1:                        \
00204           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00205           break;                                              \
00206         case RCC_UART4CLKSOURCE_HSI:                          \
00207           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00208           break;                                              \
00209         case RCC_UART4CLKSOURCE_SYSCLK:                       \
00210           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00211           break;                                              \
00212         case RCC_UART4CLKSOURCE_LSE:                          \
00213           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00214           break;                                              \
00215         default:                                              \
00216           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00217           break;                                              \
00218        }                                                      \
00219     }                                                         \
00220     else if ((__HANDLE__)->Instance == UART5)                 \
00221     {                                                         \
00222        switch(__HAL_RCC_GET_UART5_SOURCE())                   \
00223        {                                                      \
00224         case RCC_UART5CLKSOURCE_PCLK1:                        \
00225           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00226           break;                                              \
00227         case RCC_UART5CLKSOURCE_HSI:                          \
00228           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00229           break;                                              \
00230         case RCC_UART5CLKSOURCE_SYSCLK:                       \
00231           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00232           break;                                              \
00233         case RCC_UART5CLKSOURCE_LSE:                          \
00234           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00235           break;                                              \
00236         default:                                              \
00237           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00238           break;                                              \
00239        }                                                      \
00240     }                                                         \
00241     else                                                      \
00242     {                                                         \
00243       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
00244     }                                                         \
00245   } while(0U)
00246 #elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00247       defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00248 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00249   do {                                                        \
00250     if((__HANDLE__)->Instance == USART1)                      \
00251     {                                                         \
00252        switch(__HAL_RCC_GET_USART1_SOURCE())                  \
00253        {                                                      \
00254         case RCC_USART1CLKSOURCE_PCLK1:                       \
00255           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00256           break;                                              \
00257         case RCC_USART1CLKSOURCE_HSI:                         \
00258           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00259           break;                                              \
00260         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00261           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00262           break;                                              \
00263         case RCC_USART1CLKSOURCE_LSE:                         \
00264           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00265           break;                                              \
00266         default:                                              \
00267           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00268           break;                                              \
00269        }                                                      \
00270     }                                                         \
00271     else if((__HANDLE__)->Instance == USART2)                 \
00272     {                                                         \
00273       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
00274     }                                                         \
00275     else if((__HANDLE__)->Instance == USART3)                 \
00276     {                                                         \
00277       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
00278     }                                                         \
00279     else                                                      \
00280     {                                                         \
00281       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
00282     }                                                         \
00283   } while(0U)
00284 #else
00285 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00286   do {                                                        \
00287     if((__HANDLE__)->Instance == USART1)                      \
00288     {                                                         \
00289        switch(__HAL_RCC_GET_USART1_SOURCE())                  \
00290        {                                                      \
00291         case RCC_USART1CLKSOURCE_PCLK2:                       \
00292           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
00293           break;                                              \
00294         case RCC_USART1CLKSOURCE_HSI:                         \
00295           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00296           break;                                              \
00297         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00298           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00299           break;                                              \
00300         case RCC_USART1CLKSOURCE_LSE:                         \
00301           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00302           break;                                              \
00303         default:                                              \
00304           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00305           break;                                              \
00306        }                                                      \
00307     }                                                         \
00308     else if((__HANDLE__)->Instance == USART2)                 \
00309     {                                                         \
00310        switch(__HAL_RCC_GET_USART2_SOURCE())                  \
00311        {                                                      \
00312         case RCC_USART2CLKSOURCE_PCLK1:                       \
00313           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00314           break;                                              \
00315         case RCC_USART2CLKSOURCE_HSI:                         \
00316           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00317           break;                                              \
00318         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00319           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00320           break;                                              \
00321         case RCC_USART2CLKSOURCE_LSE:                         \
00322           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00323           break;                                              \
00324         default:                                              \
00325           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00326           break;                                              \
00327        }                                                      \
00328     }                                                         \
00329     else if((__HANDLE__)->Instance == USART3)                 \
00330     {                                                         \
00331        switch(__HAL_RCC_GET_USART3_SOURCE())                  \
00332        {                                                      \
00333         case RCC_USART3CLKSOURCE_PCLK1:                       \
00334           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00335           break;                                              \
00336         case RCC_USART3CLKSOURCE_HSI:                         \
00337           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00338           break;                                              \
00339         case RCC_USART3CLKSOURCE_SYSCLK:                      \
00340           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00341           break;                                              \
00342         case RCC_USART3CLKSOURCE_LSE:                         \
00343           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00344           break;                                              \
00345         default:                                              \
00346           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00347           break;                                              \
00348        }                                                      \
00349     }                                                         \
00350     else                                                      \
00351     {                                                         \
00352       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
00353     }                                                         \
00354   } while(0U)
00355 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00356        /* STM32F302xC || STM32F303xC || STM32F358xx    */
00357
00358
00359 /** @brief  Compute the UART mask to apply to retrieve the received data
00360   *         according to the word length and to the parity bits activation.
00361   * @note   If PCE = 1, the parity bit is not included in the data extracted
00362   *         by the reception API().
00363   *         This masking operation is not carried out in the case of
00364   *         DMA transfers.
00365   * @param  __HANDLE__ specifies the UART Handle.
00366   * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
00367   */
00368 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00369     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00370     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00371 #define UART_MASK_COMPUTATION(__HANDLE__)                             \
00372   do {                                                                \
00373   if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)            \
00374   {                                                                   \
00375      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
00376      {                                                                \
00377         (__HANDLE__)->Mask = 0x01FFU ;                                \
00378      }                                                                \
00379      else                                                             \
00380      {                                                                \
00381         (__HANDLE__)->Mask = 0x00FFU ;                                \
00382      }                                                                \
00383   }                                                                   \
00384   else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)       \
00385   {                                                                   \
00386      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
00387      {                                                                \
00388         (__HANDLE__)->Mask = 0x00FFU ;                                \
00389      }                                                                \
00390      else                                                             \
00391      {                                                                \
00392         (__HANDLE__)->Mask = 0x007FU ;                                \
00393      }                                                                \
00394   }                                                                   \
00395   else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)       \
00396   {                                                                   \
00397      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
00398      {                                                                \
00399         (__HANDLE__)->Mask = 0x007FU ;                                \
00400      }                                                                \
00401      else                                                             \
00402      {                                                                \
00403         (__HANDLE__)->Mask = 0x003FU ;                                \
00404      }                                                                \
00405   }                                                                   \
00406 } while(0U)
00407 #else
00408 #define UART_MASK_COMPUTATION(__HANDLE__)                             \
00409   do {                                                                \
00410   if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)            \
00411   {                                                                   \
00412      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
00413      {                                                                \
00414         (__HANDLE__)->Mask = 0x01FFU ;                                \
00415      }                                                                \
00416      else                                                             \
00417      {                                                                \
00418         (__HANDLE__)->Mask = 0x00FFU ;                                \
00419      }                                                                \
00420   }                                                                   \
00421   else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)       \
00422   {                                                                   \
00423      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
00424      {                                                                \
00425         (__HANDLE__)->Mask = 0x00FFU ;                                \
00426      }                                                                \
00427      else                                                             \
00428      {                                                                \
00429         (__HANDLE__)->Mask = 0x007FU ;                                \
00430      }                                                                \
00431   }                                                                   \
00432 } while(0U)
00433 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00434        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00435        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00436
00437 /**
00438   * @brief Ensure that UART frame length is valid.
00439   * @param __LENGTH__ UART frame length.
00440   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00441   */
00442 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00443     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00444     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00445 #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
00446                                          ((__LENGTH__) == UART_WORDLENGTH_8B) || \
00447                                          ((__LENGTH__) == UART_WORDLENGTH_9B))
00448 #else
00449 #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_8B) || \
00450                                          ((__LENGTH__) == UART_WORDLENGTH_9B))
00451 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00452        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
00453        /* STM32F301x8 || STM32F302x8 || STM32F318xx   */
00454 /**
00455   * @}
00456   */
00457
00458 /* Private functions ---------------------------------------------------------*/
00459
00460 /**
00461   * @}
00462   */
00463
00464 /**
00465   * @}
00466   */
00467
00468 #ifdef __cplusplus
00469 }
00470 #endif
00471
00472 #endif /* __STM32F3xx_HAL_UART_EX_H */
00473
00474 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00475
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_usart.c Source File

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stm32f3xx_hal_usart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_usart.c
00004   * @author  MCD Application Team
00005   * @brief   USART HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Universal Synchronous Asynchronous Receiver Transmitter
00008   *          Peripheral (USART).
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral Control functions
00012   *           + Peripheral State and Error functions
00013   *
00014   @verbatim
00015  ===============================================================================
00016                         ##### How to use this driver #####
00017  ===============================================================================
00018     [..]
00019       The USART HAL driver can be used as follows:
00020
00021       (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
00022       (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
00023           (++) Enable the USARTx interface clock.
00024           (++) USART pins configuration:
00025             (+++) Enable the clock for the USART GPIOs.
00026             (+++) Configure these USART pins as alternate function pull-up.
00027           (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
00028                 HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
00029             (+++) Configure the USARTx interrupt priority.
00030             (+++) Enable the NVIC USART IRQ handle.
00031             (++) USART interrupts handling:
00032               -@@-   The specific USART interrupts (Transmission complete interrupt,
00033                   RXNE interrupt and Error Interrupts) will be managed using the macros
00034                   __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
00035           (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
00036                HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
00037             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00038             (+++) Enable the DMAx interface clock.
00039             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00040             (+++) Configure the DMA Tx/Rx channel.
00041             (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
00042             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00043
00044       (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
00045           flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.
00046
00047       (#) Initialize the USART registers by calling the HAL_USART_Init() API:
00048           (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
00049                by calling the customized HAL_USART_MspInit(&husart) API.
00050
00051     (#) Three operation modes are available within this driver :
00052
00053      *** Polling mode IO operation ***
00054      =================================
00055      [..]
00056        (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
00057        (+) Receive an amount of data in blocking mode using HAL_USART_Receive()
00058
00059      *** Interrupt mode IO operation ***
00060      ===================================
00061      [..]
00062        (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
00063        (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
00064             add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
00065        (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
00066             add his own code by customization of function pointer HAL_USART_TxCpltCallback
00067        (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
00068        (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
00069             add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
00070        (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
00071             add his own code by customization of function pointer HAL_USART_RxCpltCallback
00072        (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
00073             add his own code by customization of function pointer HAL_USART_ErrorCallback
00074
00075      *** DMA mode IO operation ***
00076      ==============================
00077      [..]
00078        (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
00079        (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
00080             add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
00081        (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
00082             add his own code by customization of function pointer HAL_USART_TxCpltCallback
00083        (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
00084        (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
00085             add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
00086        (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
00087             add his own code by customization of function pointer HAL_USART_RxCpltCallback
00088        (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
00089             add his own code by customization of function pointer HAL_USART_ErrorCallback
00090        (+) Pause the DMA Transfer using HAL_USART_DMAPause()
00091        (+) Resume the DMA Transfer using HAL_USART_DMAResume()
00092        (+) Stop the DMA Transfer using HAL_USART_DMAStop()
00093
00094      *** USART HAL driver macros list ***
00095      =============================================
00096      [..]
00097        Below the list of most used macros in USART HAL driver.
00098
00099        (+) __HAL_USART_ENABLE: Enable the USART peripheral
00100        (+) __HAL_USART_DISABLE: Disable the USART peripheral
00101        (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
00102        (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
00103        (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
00104        (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
00105
00106      [..]
00107        (@) You can refer to the USART HAL driver header file for more useful macros
00108      [..]
00109        (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
00110            HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
00111            HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
00112
00113   @endverbatim
00114   ******************************************************************************
00115   * @attention
00116   *
00117   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00118   *
00119   * Redistribution and use in source and binary forms, with or without modification,
00120   * are permitted provided that the following conditions are met:
00121   *   1. Redistributions of source code must retain the above copyright notice,
00122   *      this list of conditions and the following disclaimer.
00123   *   2. Redistributions in binary form must reproduce the above copyright notice,
00124   *      this list of conditions and the following disclaimer in the documentation
00125   *      and/or other materials provided with the distribution.
00126   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00127   *      may be used to endorse or promote products derived from this software
00128   *      without specific prior written permission.
00129   *
00130   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00131   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00132   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00133   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00134   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00135   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00136   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00137   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00138   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00139   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00140   *
00141   ******************************************************************************
00142   */
00143
00144 /* Includes ------------------------------------------------------------------*/
00145 #include "stm32f3xx_hal.h"
00146
00147 /** @addtogroup STM32F3xx_HAL_Driver
00148   * @{
00149   */
00150
00151 /** @defgroup USART USART
00152   * @brief USART HAL module driver
00153   * @{
00154   */
00155
00156 #ifdef HAL_USART_MODULE_ENABLED
00157
00158 /* Private typedef -----------------------------------------------------------*/
00159 /* Private define ------------------------------------------------------------*/
00160 /** @defgroup USART_Private_Constants USART Private Constants
00161   * @{
00162   */
00163 #define USART_DUMMY_DATA          ((uint16_t) 0xFFFFU)           /*!< USART transmitted dummy data                     */
00164 #define USART_TEACK_REACK_TIMEOUT ( 1000U)                       /*!< USART TX or RX enable acknowledge time-out value */
00165 #define USART_CR1_FIELDS          ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
00166                                               USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8))    /*!< USART CR1 fields of parameters set by USART_SetConfig API */
00167 #define USART_CR2_FIELDS          ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
00168                                               USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */
00169 /**
00170   * @}
00171   */
00172
00173 /* Private macros ------------------------------------------------------------*/
00174 /* Private variables ---------------------------------------------------------*/
00175 /* Private function prototypes -----------------------------------------------*/
00176 /** @addtogroup USART_Private_Functions
00177   * @{
00178   */
00179 static void USART_EndTransfer(USART_HandleTypeDef *husart);
00180 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00181 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00182 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00183 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00184 static void USART_DMAError(DMA_HandleTypeDef *hdma);
00185 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00186 static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00187 static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00188 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00189 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
00190 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
00191 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
00192 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
00193 static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
00194 static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
00195 /**
00196   * @}
00197   */
00198
00199 /* Exported functions --------------------------------------------------------*/
00200
00201 /** @defgroup USART_Exported_Functions USART Exported Functions
00202   * @{
00203   */
00204
00205 /** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
00206   * @brief    Initialization and Configuration functions
00207   *
00208 @verbatim
00209  ===============================================================================
00210             ##### Initialization and Configuration functions #####
00211  ===============================================================================
00212     [..]
00213     This subsection provides a set of functions allowing to initialize the USART
00214     in asynchronous and in synchronous modes.
00215       (+) For the asynchronous mode only these parameters can be configured:
00216         (++) Baud Rate
00217         (++) Word Length
00218         (++) Stop Bit
00219         (++) Parity
00220         (++) USART polarity
00221         (++) USART phase
00222         (++) USART LastBit
00223         (++) Receiver/transmitter modes
00224
00225     [..]
00226     The HAL_USART_Init() function follows the USART  synchronous configuration
00227     procedure (details for the procedure are available in reference manual).
00228
00229 @endverbatim
00230   * @{
00231   */
00232
00233 /*
00234   Additional Table:  If the parity is enabled, then the MSB bit of the data written
00235                      in the data register is transmitted but is changed by the parity bit.
00236                      According to device capability (support or not of 7-bit word length),
00237                      frame length is either defined by the M bit (8-bits or 9-bits)
00238                      or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
00239                      Possible USART frame formats are as listed in the following table:
00240
00241       Table 1. USART frame format.
00242       +-----------------------------------------------------------------------+
00243       |       M bit       |  PCE bit  |             USART frame                |
00244       |-------------------|-----------|---------------------------------------|
00245       |         0         |     0     |    | SB |    8-bit data   | STB |     |
00246       |-------------------|-----------|---------------------------------------|
00247       |         0         |     1     |    | SB | 7-bit data | PB | STB |     |
00248       |-------------------|-----------|---------------------------------------|
00249       |         1         |     0     |    | SB |    9-bit data   | STB |     |
00250       |-------------------|-----------|---------------------------------------|
00251       |         1         |     1     |    | SB | 8-bit data | PB | STB |     |
00252       +-----------------------------------------------------------------------+
00253       |  M1 bit |  M0 bit |  PCE bit  |             USART frame                |
00254       |---------|---------|-----------|---------------------------------------|
00255       |    0    |    0    |     0     |    | SB |    8 bit data   | STB |     |
00256       |---------|---------|-----------|---------------------------------------|
00257       |    0    |    0    |     1     |    | SB | 7 bit data | PB | STB |     |
00258       |---------|---------|-----------|---------------------------------------|
00259       |    0    |    1    |     0     |    | SB |    9 bit data   | STB |     |
00260       |---------|---------|-----------|---------------------------------------|
00261       |    0    |    1    |     1     |    | SB | 8 bit data | PB | STB |     |
00262       |---------|---------|-----------|---------------------------------------|
00263       |    1    |    0    |     0     |    | SB |    7 bit data   | STB |     |
00264       |---------|---------|-----------|---------------------------------------|
00265       |    1    |    0    |     1     |    | SB | 6 bit data | PB | STB |     |
00266       +-----------------------------------------------------------------------+
00267
00268 */
00269
00270 /**
00271   * @brief  Initialize the USART mode according to the specified
00272   *         parameters in the USART_InitTypeDef and initialize the associated handle.
00273   * @param  husart USART handle.
00274   * @retval HAL status
00275   */
00276 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
00277 {
00278   /* Check the USART handle allocation */
00279   if(husart == NULL)
00280   {
00281     return HAL_ERROR;
00282   }
00283
00284   /* Check the parameters */
00285   assert_param(IS_USART_INSTANCE(husart->Instance));
00286
00287   if(husart->State == HAL_USART_STATE_RESET)
00288   {
00289     /* Allocate lock resource and initialize it */
00290     husart->Lock = HAL_UNLOCKED;
00291
00292     /* Init the low level hardware : GPIO, CLOCK */
00293     HAL_USART_MspInit(husart);
00294   }
00295
00296   husart->State = HAL_USART_STATE_BUSY;
00297
00298   /* Disable the Peripheral */
00299   __HAL_USART_DISABLE(husart);
00300
00301   /* Set the Usart Communication parameters */
00302   if (USART_SetConfig(husart) == HAL_ERROR)
00303   {
00304     return HAL_ERROR;
00305   }
00306
00307   /* In Synchronous mode, the following bits must be kept cleared:
00308   - LINEN bit in the USART_CR2 register
00309   - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
00310   husart->Instance->CR2 &= ~USART_CR2_LINEN;
00311   husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
00312
00313   /* Enable the Peripheral */
00314   __HAL_USART_ENABLE(husart);
00315
00316   /* TEACK and/or REACK to check before moving husart->State to Ready */
00317   return (USART_CheckIdleState(husart));
00318 }
00319
00320 /**
00321   * @brief  DeInitialize the USART peripheral.
00322   * @param  husart USART handle.
00323   * @retval HAL status
00324   */
00325 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
00326 {
00327   /* Check the USART handle allocation */
00328   if(husart == NULL)
00329   {
00330     return HAL_ERROR;
00331   }
00332
00333   /* Check the parameters */
00334   assert_param(IS_USART_INSTANCE(husart->Instance));
00335
00336   husart->State = HAL_USART_STATE_BUSY;
00337
00338   husart->Instance->CR1 = 0x0U;
00339   husart->Instance->CR2 = 0x0U;
00340   husart->Instance->CR3 = 0x0U;
00341
00342   /* DeInit the low level hardware */
00343   HAL_USART_MspDeInit(husart);
00344
00345   husart->ErrorCode = HAL_USART_ERROR_NONE;
00346   husart->State = HAL_USART_STATE_RESET;
00347
00348   /* Process Unlock */
00349   __HAL_UNLOCK(husart);
00350
00351   return HAL_OK;
00352 }
00353
00354 /**
00355   * @brief  Initialize the USART MSP.
00356   * @param  husart USART handle.
00357   * @retval None
00358   */
00359 __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
00360 {
00361   /* Prevent unused argument(s) compilation warning */
00362   UNUSED(husart);
00363
00364   /* NOTE : This function should not be modified, when the callback is needed,
00365             the HAL_USART_MspInit can be implemented in the user file
00366    */
00367 }
00368
00369 /**
00370   * @brief  DeInitialize the USART MSP.
00371   * @param  husart USART handle.
00372   * @retval None
00373   */
00374 __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
00375 {
00376   /* Prevent unused argument(s) compilation warning */
00377   UNUSED(husart);
00378
00379   /* NOTE : This function should not be modified, when the callback is needed,
00380             the HAL_USART_MspDeInit can be implemented in the user file
00381    */
00382 }
00383
00384 /**
00385   * @}
00386   */
00387
00388 /** @defgroup USART_Exported_Functions_Group2 IO operation functions
00389   * @brief    USART Transmit and Receive functions
00390   *
00391 @verbatim
00392  ===============================================================================
00393                       ##### IO operation functions #####
00394  ===============================================================================
00395     [..] This subsection provides a set of functions allowing to manage the USART synchronous
00396     data transfers.
00397
00398     [..] The USART supports master mode only: it cannot receive or send data related to an input
00399          clock (SCLK is always an output).
00400
00401     (#) There are two modes of transfer:
00402        (++) Blocking mode: The communication is performed in polling mode.
00403             The HAL status of all data processing is returned by the same function
00404             after finishing transfer.
00405        (++) No-Blocking mode: The communication is performed using Interrupts
00406            or DMA, These APIs return the HAL status.
00407            The end of the data processing will be indicated through the
00408            dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
00409            using DMA mode.
00410            The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
00411            will be executed respectively at the end of the transmit or Receive process
00412            The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
00413
00414     (#) Blocking mode APIs are :
00415         (++) HAL_USART_Transmit() in simplex mode
00416         (++) HAL_USART_Receive() in full duplex receive only
00417         (++) HAL_USART_TransmitReceive() in full duplex mode
00418
00419     (#) No-Blocking mode APIs with Interrupt are :
00420         (++) HAL_USART_Transmit_IT() in simplex mode
00421         (++) HAL_USART_Receive_IT() in full duplex receive only
00422         (++) HAL_USART_TransmitReceive_IT()in full duplex mode
00423         (++) HAL_USART_IRQHandler()
00424
00425     (#) No-Blocking mode APIs with DMA are :
00426         (++) HAL_USART_Transmit_DMA() in simplex mode
00427         (++) HAL_USART_Receive_DMA() in full duplex receive only
00428         (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
00429         (++) HAL_USART_DMAPause()
00430         (++) HAL_USART_DMAResume()
00431         (++) HAL_USART_DMAStop()
00432
00433     (#) A set of Transfer Complete Callbacks are provided in No-Blocking mode:
00434         (++) HAL_USART_TxCpltCallback()
00435         (++) HAL_USART_RxCpltCallback()
00436         (++) HAL_USART_TxHalfCpltCallback()
00437         (++) HAL_USART_RxHalfCpltCallback()
00438         (++) HAL_USART_ErrorCallback()
00439         (++) HAL_USART_TxRxCpltCallback()
00440
00441     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00442         (++) HAL_USART_Abort()
00443         (++) HAL_USART_Abort_IT()
00444
00445     (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
00446         (++) HAL_USART_AbortCpltCallback()
00447
00448     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00449         Errors are handled as follows :
00450         (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00451              to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
00452              Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
00453              and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
00454              If user wants to abort it, Abort services should be called by user.
00455         (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00456              This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
00457              Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
00458
00459 @endverbatim
00460   * @{
00461   */
00462
00463 /**
00464   * @brief  Simplex send an amount of data in blocking mode.
00465   * @param  husart USART handle.
00466   * @param  pTxData Pointer to data buffer.
00467   * @param  Size Amount of data to be sent.
00468   * @param  Timeout Timeout duration.
00469   * @retval HAL status
00470   */
00471 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
00472 {
00473   uint16_t* tmp=0U;
00474   uint32_t tickstart = 0U;
00475
00476   if(husart->State == HAL_USART_STATE_READY)
00477   {
00478     if((pTxData == NULL) || (Size == 0U))
00479     {
00480       return  HAL_ERROR;
00481     }
00482
00483     /* Process Locked */
00484     __HAL_LOCK(husart);
00485
00486     husart->ErrorCode = HAL_USART_ERROR_NONE;
00487     husart->State = HAL_USART_STATE_BUSY_TX;
00488
00489     /* Init tickstart for timeout managment*/
00490     tickstart = HAL_GetTick();
00491
00492     husart->TxXferSize = Size;
00493     husart->TxXferCount = Size;
00494
00495     /* Check the remaining data to be sent */
00496     while(husart->TxXferCount > 0U)
00497     {
00498       husart->TxXferCount--;
00499       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00500       {
00501         return HAL_TIMEOUT;
00502       }
00503       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00504       {
00505         tmp = (uint16_t*) pTxData;
00506         husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
00507         pTxData += 2U;
00508       }
00509       else
00510       {
00511         husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU);
00512       }
00513     }
00514
00515     if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00516     {
00517       return HAL_TIMEOUT;
00518     }
00519
00520     /* At end of Tx process, restore husart->State to Ready */
00521     husart->State = HAL_USART_STATE_READY;
00522
00523     /* Process Unlocked */
00524     __HAL_UNLOCK(husart);
00525
00526     return HAL_OK;
00527   }
00528   else
00529   {
00530     return HAL_BUSY;
00531   }
00532 }
00533
00534 /**
00535   * @brief  Receive an amount of data in blocking mode.
00536   * @note   To receive synchronous data, dummy data are simultaneously transmitted.
00537   * @param  husart USART handle.
00538   * @param  pRxData Pointer to data buffer.
00539   * @param  Size Amount of data to be received.
00540   * @param  Timeout Timeout duration.
00541   * @retval HAL status
00542   */
00543 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00544 {
00545   uint16_t* tmp=0U;
00546   uint16_t uhMask;
00547   uint32_t tickstart = 0U;
00548
00549   if(husart->State == HAL_USART_STATE_READY)
00550   {
00551     if((pRxData == NULL) || (Size == 0U))
00552     {
00553       return  HAL_ERROR;
00554     }
00555
00556     /* Process Locked */
00557     __HAL_LOCK(husart);
00558
00559     husart->ErrorCode = HAL_USART_ERROR_NONE;
00560     husart->State = HAL_USART_STATE_BUSY_RX;
00561
00562     /* Init tickstart for timeout managment*/
00563     tickstart = HAL_GetTick();
00564
00565     husart->RxXferSize = Size;
00566     husart->RxXferCount = Size;
00567
00568     /* Computation of USART mask to apply to RDR register */
00569     USART_MASK_COMPUTATION(husart);
00570     uhMask = husart->Mask;
00571
00572     /* as long as data have to be received */
00573     while(husart->RxXferCount > 0U)
00574     {
00575       husart->RxXferCount--;
00576
00577       /* Wait until TC flag is set to send dummy byte in order to generate the
00578       * clock for the slave to send data.
00579        * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
00580        * can be written for all the cases. */
00581       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00582       {
00583         return HAL_TIMEOUT;
00584       }
00585       husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FFU);
00586
00587       /* Wait for RXNE Flag */
00588       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00589       {
00590         return HAL_TIMEOUT;
00591       }
00592
00593       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00594       {
00595         tmp = (uint16_t*) pRxData ;
00596         *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
00597         pRxData +=2U;
00598       }
00599       else
00600       {
00601         *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
00602       }
00603     }
00604
00605     /* At end of Rx process, restore husart->State to Ready */
00606     husart->State = HAL_USART_STATE_READY;
00607
00608     /* Process Unlocked */
00609     __HAL_UNLOCK(husart);
00610
00611     return HAL_OK;
00612   }
00613   else
00614   {
00615     return HAL_BUSY;
00616   }
00617 }
00618
00619 /**
00620   * @brief  Full-Duplex Send and Receive an amount of data in blocking mode.
00621   * @param  husart USART handle.
00622   * @param  pTxData pointer to TX data buffer.
00623   * @param  pRxData pointer to RX data buffer.
00624   * @param  Size amount of data to be sent (same amount to be received).
00625   * @param  Timeout Timeout duration.
00626   * @retval HAL status
00627   */
00628 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00629 {
00630   uint16_t* tmp=0U;
00631   uint16_t uhMask;
00632   uint32_t tickstart = 0U;
00633
00634   if(husart->State == HAL_USART_STATE_READY)
00635   {
00636     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00637     {
00638       return  HAL_ERROR;
00639     }
00640
00641     /* Process Locked */
00642     __HAL_LOCK(husart);
00643
00644     husart->ErrorCode = HAL_USART_ERROR_NONE;
00645     husart->State = HAL_USART_STATE_BUSY_RX;
00646
00647     /* Init tickstart for timeout managment*/
00648     tickstart = HAL_GetTick();
00649
00650     husart->RxXferSize = Size;
00651     husart->TxXferSize = Size;
00652     husart->TxXferCount = Size;
00653     husart->RxXferCount = Size;
00654
00655     /* Computation of USART mask to apply to RDR register */
00656     USART_MASK_COMPUTATION(husart);
00657     uhMask = husart->Mask;
00658
00659     /* Check the remain data to be sent */
00660     while(husart->TxXferCount > 0U)
00661     {
00662       husart->TxXferCount--;
00663       husart->RxXferCount--;
00664
00665       /* Wait until TC flag is set to send data */
00666       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00667       {
00668         return HAL_TIMEOUT;
00669       }
00670       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00671       {
00672         tmp = (uint16_t*) pTxData;
00673         husart->Instance->TDR = (*tmp & uhMask);
00674         pTxData += 2U;
00675       }
00676       else
00677       {
00678         husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
00679       }
00680
00681       /* Wait for RXNE Flag */
00682       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00683       {
00684         return HAL_TIMEOUT;
00685       }
00686
00687       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00688       {
00689         tmp = (uint16_t*) pRxData ;
00690         *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
00691         pRxData +=2U;
00692       }
00693       else
00694       {
00695         *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
00696       }
00697     }
00698
00699     /* At end of TxRx process, restore husart->State to Ready */
00700     husart->State = HAL_USART_STATE_READY;
00701
00702     /* Process Unlocked */
00703     __HAL_UNLOCK(husart);
00704
00705     return HAL_OK;
00706   }
00707   else
00708   {
00709     return HAL_BUSY;
00710   }
00711 }
00712
00713 /**
00714   * @brief  Send an amount of data in interrupt mode.
00715   * @param  husart USART handle.
00716   * @param  pTxData pointer to data buffer.
00717   * @param  Size amount of data to be sent.
00718   * @retval HAL status
00719   */
00720 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
00721 {
00722   if(husart->State == HAL_USART_STATE_READY)
00723   {
00724     if((pTxData == NULL) || (Size == 0U))
00725     {
00726       return HAL_ERROR;
00727     }
00728
00729     /* Process Locked */
00730     __HAL_LOCK(husart);
00731
00732     husart->pTxBuffPtr = pTxData;
00733     husart->TxXferSize = Size;
00734     husart->TxXferCount = Size;
00735
00736     husart->ErrorCode = HAL_USART_ERROR_NONE;
00737     husart->State = HAL_USART_STATE_BUSY_TX;
00738
00739     /* The USART Error Interrupts: (Frame error, noise error, overrun error)
00740     are not managed by the USART Transmit Process to avoid the overrun interrupt
00741     when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
00742     to benefit for the frame error and noise interrupts the usart mode should be
00743     configured only for transmit "USART_MODE_TX" */
00744
00745     /* Process Unlocked */
00746     __HAL_UNLOCK(husart);
00747
00748     /* Enable the USART Transmit Data Register Empty Interrupt */
00749     __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
00750
00751     return HAL_OK;
00752   }
00753   else
00754   {
00755     return HAL_BUSY;
00756   }
00757 }
00758
00759 /**
00760   * @brief  Receive an amount of data in interrupt mode.
00761   * @note   To receive synchronous data, dummy data are simultaneously transmitted.
00762   * @param  husart USART handle.
00763   * @param  pRxData pointer to data buffer.
00764   * @param  Size amount of data to be received.
00765   * @retval HAL status
00766   */
00767 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
00768 {
00769   if(husart->State == HAL_USART_STATE_READY)
00770   {
00771     if((pRxData == NULL) || (Size == 0U))
00772     {
00773       return HAL_ERROR;
00774     }
00775
00776     /* Process Locked */
00777     __HAL_LOCK(husart);
00778
00779     husart->pRxBuffPtr = pRxData;
00780     husart->RxXferSize = Size;
00781     husart->RxXferCount = Size;
00782
00783     USART_MASK_COMPUTATION(husart);
00784
00785     husart->ErrorCode = HAL_USART_ERROR_NONE;
00786     husart->State = HAL_USART_STATE_BUSY_RX;
00787
00788     /* Process Unlocked */
00789     __HAL_UNLOCK(husart);
00790
00791     /* Enable the USART Parity Error and Data Register not empty Interrupts */
00792     SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
00793
00794     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
00795     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
00796
00797     /* Send dummy byte in order to generate the clock for the Slave to send the next data */
00798     if(husart->Init.WordLength == USART_WORDLENGTH_9B)
00799     {
00800       husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FFU);
00801     }
00802     else
00803     {
00804       husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
00805     }
00806
00807     return HAL_OK;
00808   }
00809   else
00810   {
00811     return HAL_BUSY;
00812   }
00813 }
00814
00815 /**
00816   * @brief  Full-Duplex Send and Receive an amount of data in interrupt mode.
00817   * @param  husart USART handle.
00818   * @param  pTxData pointer to TX data buffer.
00819   * @param  pRxData pointer to RX data buffer.
00820   * @param  Size amount of data to be sent (same amount to be received).
00821   * @retval HAL status
00822   */
00823 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size)
00824 {
00825
00826   if(husart->State == HAL_USART_STATE_READY)
00827   {
00828     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00829     {
00830       return HAL_ERROR;
00831     }
00832
00833     /* Process Locked */
00834     __HAL_LOCK(husart);
00835
00836     husart->pRxBuffPtr = pRxData;
00837     husart->RxXferSize = Size;
00838     husart->RxXferCount = Size;
00839     husart->pTxBuffPtr = pTxData;
00840     husart->TxXferSize = Size;
00841     husart->TxXferCount = Size;
00842
00843     /* Computation of USART mask to apply to RDR register */
00844     USART_MASK_COMPUTATION(husart);
00845
00846     husart->ErrorCode = HAL_USART_ERROR_NONE;
00847     husart->State = HAL_USART_STATE_BUSY_TX_RX;
00848
00849     /* Process Unlocked */
00850     __HAL_UNLOCK(husart);
00851
00852     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
00853     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
00854
00855     /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
00856     SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
00857
00858     /* Enable the USART Transmit Data Register Empty Interrupt */
00859     SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
00860
00861     return HAL_OK;
00862   }
00863   else
00864   {
00865     return HAL_BUSY;
00866   }
00867 }
00868
00869 /**
00870   * @brief  Send an amount of data in DMA mode.
00871   * @param  husart USART handle.
00872   * @param  pTxData pointer to data buffer.
00873   * @param  Size amount of data to be sent.
00874   * @note   This function starts a DMA transfer in interrupt mode meaning that
00875   *         DMA half transfer complete, DMA transfer complete and DMA transfer
00876   *         error interrupts are enabled
00877   * @retval HAL status
00878   */
00879 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
00880 {
00881   uint32_t *tmp=0U;
00882
00883   if(husart->State == HAL_USART_STATE_READY)
00884   {
00885     if((pTxData == NULL) || (Size == 0U))
00886     {
00887       return HAL_ERROR;
00888     }
00889
00890     /* Process Locked */
00891     __HAL_LOCK(husart);
00892
00893     husart->pTxBuffPtr = pTxData;
00894     husart->TxXferSize = Size;
00895     husart->TxXferCount = Size;
00896
00897     husart->ErrorCode = HAL_USART_ERROR_NONE;
00898     husart->State = HAL_USART_STATE_BUSY_TX;
00899
00900     /* Set the USART DMA transfer complete callback */
00901     husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
00902
00903     /* Set the USART DMA Half transfer complete callback */
00904     husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
00905
00906     /* Set the DMA error callback */
00907     husart->hdmatx->XferErrorCallback = USART_DMAError;
00908
00909     /* Enable the USART transmit DMA channel */
00910     tmp = (uint32_t*)&pTxData;
00911     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
00912
00913     /* Clear the TC flag in the ICR register */
00914     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
00915
00916     /* Process Unlocked */
00917     __HAL_UNLOCK(husart);
00918
00919     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00920        in the USART CR3 register */
00921     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
00922
00923     return HAL_OK;
00924   }
00925   else
00926   {
00927     return HAL_BUSY;
00928   }
00929 }
00930
00931 /**
00932   * @brief  Receive an amount of data in DMA mode.
00933   * @param  husart USART handle.
00934   * @param  pRxData pointer to data buffer.
00935   * @param  Size amount of data to be received.
00936   * @note   When the USART parity is enabled (PCE = 1), the received data contain
00937   *         the parity bit (MSB position).
00938   * @note   The USART DMA transmit channel must be configured in order to generate the clock for the slave.
00939   * @note   This function starts a DMA transfer in interrupt mode meaning that
00940   *         DMA half transfer complete, DMA transfer complete and DMA transfer
00941   *         error interrupts are enabled
00942   * @retval HAL status
00943   */
00944 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
00945 {
00946   uint32_t *tmp;
00947
00948   /* Check that a Rx process is not already ongoing */
00949   if(husart->State == HAL_USART_STATE_READY)
00950   {
00951     if((pRxData == NULL) || (Size == 0U))
00952     {
00953       return HAL_ERROR;
00954     }
00955
00956     /* Process Locked */
00957     __HAL_LOCK(husart);
00958
00959     husart->pRxBuffPtr = pRxData;
00960     husart->RxXferSize = Size;
00961     husart->pTxBuffPtr = pRxData;
00962     husart->TxXferSize = Size;
00963
00964     husart->ErrorCode = HAL_USART_ERROR_NONE;
00965     husart->State = HAL_USART_STATE_BUSY_RX;
00966
00967     /* Set the USART DMA Rx transfer complete callback */
00968     husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
00969
00970     /* Set the USART DMA Half transfer complete callback */
00971     husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
00972
00973     /* Set the USART DMA Rx transfer error callback */
00974     husart->hdmarx->XferErrorCallback = USART_DMAError;
00975
00976     /* Enable the USART receive DMA channel */
00977     tmp = (uint32_t*)&pRxData;
00978     HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
00979
00980     /* Enable the USART transmit DMA channel: the transmit channel is used in order
00981        to generate in the non-blocking mode the clock to the slave device,
00982        this mode isn't a simplex receive mode but a full-duplex receive mode */
00983     /* Set the USART DMA Tx Complete and Error callback to Null */
00984     husart->hdmatx->XferErrorCallback = NULL;
00985     husart->hdmatx->XferHalfCpltCallback = NULL;
00986     husart->hdmatx->XferCpltCallback = NULL;
00987     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
00988
00989     /* Process Unlocked */
00990     __HAL_UNLOCK(husart);
00991
00992     /* Enable the USART Parity Error Interrupt */
00993     SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
00994
00995     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
00996     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
00997
00998     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00999        in the USART CR3 register */
01000     SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01001
01002     /* Enable the DMA transfer for transmit request by setting the DMAT bit
01003        in the USART CR3 register */
01004     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01005
01006     return HAL_OK;
01007   }
01008   else
01009   {
01010     return HAL_BUSY;
01011   }
01012 }
01013
01014 /**
01015   * @brief  Full-Duplex Transmit Receive an amount of data in non-blocking mode.
01016   * @param  husart USART handle.
01017   * @param  pTxData pointer to TX data buffer.
01018   * @param  pRxData pointer to RX data buffer.
01019   * @param  Size amount of data to be received/sent.
01020   * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
01021   * @note   This function starts a 2 DMA transfers in interrupt mode meaning that
01022   *         DMA half transfer complete, DMA transfer complete and DMA transfer
01023   *         error interrupts are enabled
01024   * @retval HAL status
01025   */
01026 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01027 {
01028   uint32_t *tmp;
01029
01030   if(husart->State == HAL_USART_STATE_READY)
01031   {
01032     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01033     {
01034       return HAL_ERROR;
01035     }
01036
01037     /* Process Locked */
01038     __HAL_LOCK(husart);
01039
01040     husart->pRxBuffPtr = pRxData;
01041     husart->RxXferSize = Size;
01042     husart->pTxBuffPtr = pTxData;
01043     husart->TxXferSize = Size;
01044
01045     husart->ErrorCode = HAL_USART_ERROR_NONE;
01046     husart->State = HAL_USART_STATE_BUSY_TX_RX;
01047
01048     /* Set the USART DMA Rx transfer complete callback */
01049     husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
01050
01051     /* Set the USART DMA Half transfer complete callback */
01052     husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
01053
01054     /* Set the USART DMA Tx transfer complete callback */
01055     husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
01056
01057     /* Set the USART DMA Half transfer complete callback */
01058     husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
01059
01060     /* Set the USART DMA Tx transfer error callback */
01061     husart->hdmatx->XferErrorCallback = USART_DMAError;
01062
01063     /* Set the USART DMA Rx transfer error callback */
01064     husart->hdmarx->XferErrorCallback = USART_DMAError;
01065
01066     /* Enable the USART receive DMA channel */
01067     tmp = (uint32_t*)&pRxData;
01068     HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
01069
01070     /* Enable the USART transmit DMA channel */
01071     tmp = (uint32_t*)&pTxData;
01072     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
01073
01074     /* Process Unlocked */
01075     __HAL_UNLOCK(husart);
01076
01077     /* Enable the USART Parity Error Interrupt */
01078     SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01079
01080     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01081     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01082
01083     /* Clear the TC flag in the ICR register */
01084     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
01085
01086     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01087        in the USART CR3 register */
01088     SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01089
01090     /* Enable the DMA transfer for transmit request by setting the DMAT bit
01091        in the USART CR3 register */
01092     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01093
01094     return HAL_OK;
01095   }
01096   else
01097   {
01098     return HAL_BUSY;
01099   }
01100 }
01101
01102 /**
01103   * @brief  Pause the DMA Transfer.
01104   * @param  husart USART handle.
01105   * @retval HAL status
01106   */
01107 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
01108 {
01109   /* Process Locked */
01110   __HAL_LOCK(husart);
01111
01112   if( (husart->State == HAL_USART_STATE_BUSY_TX) &&
01113       (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))
01114   {
01115     /* Disable the USART DMA Tx request */
01116     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01117   }
01118   else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
01119            (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
01120   {
01121     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01122     {
01123       /* Disable the USART DMA Tx request */
01124       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01125     }
01126     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01127     {
01128       /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01129       CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01130       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01131
01132       /* Disable the USART DMA Rx request */
01133       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01134     }
01135   }
01136
01137   /* Process Unlocked */
01138   __HAL_UNLOCK(husart);
01139
01140   return HAL_OK;
01141 }
01142
01143 /**
01144   * @brief  Resume the DMA Transfer.
01145   * @param  husart USART handle.
01146   * @retval HAL status
01147   */
01148 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
01149 {
01150   /* Process Locked */
01151   __HAL_LOCK(husart);
01152
01153   if(husart->State == HAL_USART_STATE_BUSY_TX)
01154   {
01155     /* Enable the USART DMA Tx request */
01156     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01157   }
01158   else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
01159            (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
01160   {
01161     /* Clear the Overrun flag before resuming the Rx transfer*/
01162     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
01163
01164     /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
01165     SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01166     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01167
01168     /* Enable the USART DMA Rx request  before the DMA Tx request */
01169     SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01170
01171     /* Enable the USART DMA Tx request */
01172     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01173   }
01174
01175   /* Process Unlocked */
01176   __HAL_UNLOCK(husart);
01177
01178   return HAL_OK;
01179 }
01180
01181 /**
01182   * @brief  Stop the DMA Transfer.
01183   * @param  husart USART handle.
01184   * @retval HAL status
01185   */
01186 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
01187 {
01188   /* The Lock is not implemented on this API to allow the user application
01189      to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
01190      HAL_USART_TxHalfCpltCallback() / HAL_USART_RxHalfCpltCallback ():
01191      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is
01192      generated if the DMA transfer interruption occurs at the middle or at the end of the stream
01193      and the corresponding call back is executed.
01194      */
01195
01196   /* Disable the USART Tx/Rx DMA requests */
01197   CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01198   CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01199
01200   /* Abort the USART DMA tx channel */
01201   if(husart->hdmatx != NULL)
01202   {
01203     HAL_DMA_Abort(husart->hdmatx);
01204   }
01205   /* Abort the USART DMA rx channel */
01206   if(husart->hdmarx != NULL)
01207   {
01208     HAL_DMA_Abort(husart->hdmarx);
01209   }
01210
01211   USART_EndTransfer(husart);
01212   husart->State = HAL_USART_STATE_READY;
01213
01214   return HAL_OK;
01215 }
01216
01217 /**
01218   * @brief  Abort ongoing transfers (blocking mode).
01219   * @param  husart USART handle.
01220   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01221   *         This procedure performs following operations :
01222   *           - Disable USART Interrupts (Tx and Rx)
01223   *           - Disable the DMA transfer in the peripheral register (if enabled)
01224   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01225   *           - Set handle State to READY
01226   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01227   * @retval HAL status
01228 */
01229 HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
01230 {
01231   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01232   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
01233   CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01234
01235   /* Disable the USART DMA Tx request if enabled */
01236   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01237   {
01238     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01239
01240     /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
01241     if(husart->hdmatx != NULL)
01242     {
01243       /* Set the USART DMA Abort callback to Null.
01244          No call back execution at end of DMA abort procedure */
01245       husart->hdmatx->XferAbortCallback = NULL;
01246
01247       HAL_DMA_Abort(husart->hdmatx);
01248     }
01249   }
01250
01251   /* Disable the USART DMA Rx request if enabled */
01252   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01253   {
01254     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01255
01256     /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
01257     if(husart->hdmarx != NULL)
01258     {
01259       /* Set the USART DMA Abort callback to Null.
01260          No call back execution at end of DMA abort procedure */
01261       husart->hdmarx->XferAbortCallback = NULL;
01262
01263       HAL_DMA_Abort(husart->hdmarx);
01264     }
01265   }
01266
01267   /* Reset Tx and Rx transfer counters */
01268   husart->TxXferCount = 0U;
01269   husart->RxXferCount = 0U;
01270
01271   /* Clear the Error flags in the ICR register */
01272   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
01273
01274   /* Restore husart->State to Ready */
01275   husart->State  = HAL_USART_STATE_READY;
01276
01277   /* Reset Handle ErrorCode to No Error */
01278   husart->ErrorCode = HAL_USART_ERROR_NONE;
01279
01280   return HAL_OK;
01281 }
01282
01283 /**
01284   * @brief  Abort ongoing transfers (Interrupt mode).
01285   * @param  husart USART handle.
01286   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01287   *         This procedure performs following operations :
01288   *           - Disable USART Interrupts (Tx and Rx)
01289   *           - Disable the DMA transfer in the peripheral register (if enabled)
01290   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01291   *           - Set handle State to READY
01292   *           - At abort completion, call user abort complete callback
01293   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01294   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01295   * @retval HAL status
01296 */
01297 HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
01298 {
01299   uint32_t abortcplt = 1U;
01300
01301   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01302   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
01303   CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01304
01305   /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
01306      before any call to DMA Abort functions */
01307   /* DMA Tx Handle is valid */
01308   if(husart->hdmatx != NULL)
01309   {
01310     /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
01311        Otherwise, set it to NULL */
01312     if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01313     {
01314       husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
01315     }
01316     else
01317     {
01318       husart->hdmatx->XferAbortCallback = NULL;
01319     }
01320   }
01321   /* DMA Rx Handle is valid */
01322   if(husart->hdmarx != NULL)
01323   {
01324     /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
01325        Otherwise, set it to NULL */
01326     if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01327     {
01328       husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
01329     }
01330     else
01331     {
01332       husart->hdmarx->XferAbortCallback = NULL;
01333     }
01334   }
01335
01336   /* Disable the USART DMA Tx request if enabled */
01337   if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01338   {
01339     /* Disable DMA Tx at USART level */
01340     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01341
01342     /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
01343     if(husart->hdmatx != NULL)
01344     {
01345       /* USART Tx DMA Abort callback has already been initialised :
01346          will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
01347
01348       /* Abort DMA TX */
01349       if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
01350       {
01351         husart->hdmatx->XferAbortCallback = NULL;
01352       }
01353       else
01354       {
01355         abortcplt = 0U;
01356       }
01357     }
01358   }
01359
01360   /* Disable the USART DMA Rx request if enabled */
01361   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01362   {
01363     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01364
01365     /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
01366     if(husart->hdmarx != NULL)
01367     {
01368       /* USART Rx DMA Abort callback has already been initialised :
01369          will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
01370
01371       /* Abort DMA RX */
01372       if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
01373       {
01374         husart->hdmarx->XferAbortCallback = NULL;
01375         abortcplt = 1U;
01376       }
01377       else
01378       {
01379         abortcplt = 0U;
01380       }
01381     }
01382   }
01383
01384   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01385   if (abortcplt == 1U)
01386   {
01387     /* Reset Tx and Rx transfer counters */
01388     husart->TxXferCount = 0U;
01389     husart->RxXferCount = 0U;
01390
01391     /* Reset errorCode */
01392     husart->ErrorCode = HAL_USART_ERROR_NONE;
01393
01394     /* Clear the Error flags in the ICR register */
01395     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
01396
01397     /* Restore husart->State to Ready */
01398     husart->State  = HAL_USART_STATE_READY;
01399
01400     /* As no DMA to be aborted, call directly user Abort complete callback */
01401     HAL_USART_AbortCpltCallback(husart);
01402   }
01403
01404   return HAL_OK;
01405 }
01406
01407 /**
01408   * @brief  Handle USART interrupt request.
01409   * @param  husart USART handle.
01410   * @retval None
01411   */
01412 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
01413 {
01414   uint32_t isrflags   = READ_REG(husart->Instance->ISR);
01415   uint32_t cr1its     = READ_REG(husart->Instance->CR1);
01416   uint32_t cr3its;
01417   uint32_t errorflags;
01418
01419   /* If no error occurs */
01420   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
01421   if (errorflags == RESET)
01422   {
01423     /* USART in mode Receiver ---------------------------------------------------*/
01424     if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01425     {
01426       if(husart->State == HAL_USART_STATE_BUSY_RX)
01427       {
01428         USART_Receive_IT(husart);
01429       }
01430       else
01431       {
01432         USART_TransmitReceive_IT(husart);
01433       }
01434       return;
01435     }
01436   }
01437
01438   /* If some errors occur */
01439   cr3its = READ_REG(husart->Instance->CR3);
01440   if(   (errorflags != RESET)
01441      && (   ((cr3its & USART_CR3_EIE) != RESET)
01442          || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
01443   {
01444     /* USART parity error interrupt occurred -------------------------------------*/
01445     if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
01446     {
01447       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
01448
01449       husart->ErrorCode |= HAL_USART_ERROR_PE;
01450     }
01451
01452     /* USART frame error interrupt occurred --------------------------------------*/
01453     if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01454     {
01455       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
01456
01457       husart->ErrorCode |= HAL_USART_ERROR_FE;
01458     }
01459
01460     /* USART noise error interrupt occurred --------------------------------------*/
01461     if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01462     {
01463       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
01464
01465       husart->ErrorCode |= HAL_USART_ERROR_NE;
01466     }
01467
01468     /* USART Over-Run interrupt occurred -----------------------------------------*/
01469     if(((isrflags & USART_ISR_ORE) != RESET) &&
01470        (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
01471     {
01472       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
01473
01474       husart->ErrorCode |= HAL_USART_ERROR_ORE;
01475     }
01476
01477     /* Call USART Error Call back function if need be --------------------------*/
01478     if(husart->ErrorCode != HAL_USART_ERROR_NONE)
01479     {
01480       /* USART in mode Receiver ---------------------------------------------------*/
01481       if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01482       {
01483         if(husart->State == HAL_USART_STATE_BUSY_RX)
01484         {
01485           USART_Receive_IT(husart);
01486         }
01487         else
01488         {
01489           USART_TransmitReceive_IT(husart);
01490         }
01491       }
01492
01493       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
01494          consider error as blocking */
01495       if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) ||
01496           (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
01497       {
01498         /* Blocking error : transfer is aborted
01499            Set the USART state ready to be able to start again the process,
01500            Disable Interrupts, and disable DMA requests, if ongoing */
01501         USART_EndTransfer(husart);
01502
01503         /* Disable the USART DMA Rx request if enabled */
01504         if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01505         {
01506           CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
01507
01508           /* Abort the USART DMA Tx channel */
01509           if(husart->hdmatx != NULL)
01510           {
01511             /* Set the USART Tx DMA Abort callback to NULL : no callback
01512                executed at end of DMA abort procedure */
01513             husart->hdmatx->XferAbortCallback = NULL;
01514
01515             /* Abort DMA TX */
01516             HAL_DMA_Abort_IT(husart->hdmatx);
01517           }
01518
01519           /* Abort the USART DMA Rx channel */
01520           if(husart->hdmarx != NULL)
01521           {
01522             /* Set the USART Rx DMA Abort callback :
01523                will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
01524             husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
01525
01526             /* Abort DMA RX */
01527             if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
01528             {
01529               /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
01530               husart->hdmarx->XferAbortCallback(husart->hdmarx);
01531             }
01532           }
01533           else
01534           {
01535             /* Call user error callback */
01536             HAL_USART_ErrorCallback(husart);
01537           }
01538         }
01539         else
01540         {
01541           /* Call user error callback */
01542           HAL_USART_ErrorCallback(husart);
01543         }
01544       }
01545       else
01546       {
01547         /* Non Blocking error : transfer could go on.
01548            Error is notified to user through user error callback */
01549         HAL_USART_ErrorCallback(husart);
01550         husart->ErrorCode = HAL_USART_ERROR_NONE;
01551       }
01552     }
01553     return;
01554
01555   } /* End if some error occurs */
01556
01557
01558   /* USART in mode Transmitter ------------------------------------------------*/
01559   if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
01560   {
01561     if(husart->State == HAL_USART_STATE_BUSY_TX)
01562     {
01563       USART_Transmit_IT(husart);
01564     }
01565     else
01566     {
01567       USART_TransmitReceive_IT(husart);
01568     }
01569     return;
01570   }
01571
01572   /* USART in mode Transmitter (transmission end) -----------------------------*/
01573   if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
01574   {
01575     USART_EndTransmit_IT(husart);
01576     return;
01577   }
01578
01579 }
01580
01581 /**
01582   * @brief  Tx Transfer completed callback.
01583   * @param  husart USART handle.
01584   * @retval None
01585   */
01586 __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
01587 {
01588   /* Prevent unused argument(s) compilation warning */
01589   UNUSED(husart);
01590
01591   /* NOTE : This function should not be modified, when the callback is needed,
01592             the HAL_USART_TxCpltCallback can be implemented in the user file.
01593    */
01594 }
01595
01596 /**
01597   * @brief  Tx Half Transfer completed callback.
01598   * @param  husart USART handle.
01599   * @retval None
01600   */
01601 __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
01602 {
01603   /* Prevent unused argument(s) compilation warning */
01604   UNUSED(husart);
01605
01606   /* NOTE: This function should not be modified, when the callback is needed,
01607            the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
01608    */
01609 }
01610
01611 /**
01612   * @brief  Rx Transfer completed callback.
01613   * @param  husart USART handle.
01614   * @retval None
01615   */
01616 __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
01617 {
01618   /* Prevent unused argument(s) compilation warning */
01619   UNUSED(husart);
01620
01621   /* NOTE: This function should not be modified, when the callback is needed,
01622            the HAL_USART_RxCpltCallback can be implemented in the user file.
01623    */
01624 }
01625
01626 /**
01627   * @brief  Rx Half Transfer completed callback.
01628   * @param  husart USART handle.
01629   * @retval None
01630   */
01631 __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
01632 {
01633   /* Prevent unused argument(s) compilation warning */
01634   UNUSED(husart);
01635
01636   /* NOTE : This function should not be modified, when the callback is needed,
01637             the HAL_USART_RxHalfCpltCallback can be implemented in the user file
01638    */
01639 }
01640
01641 /**
01642   * @brief  Tx/Rx Transfers completed callback for the non-blocking process.
01643   * @param  husart USART handle.
01644   * @retval None
01645   */
01646 __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
01647 {
01648   /* Prevent unused argument(s) compilation warning */
01649   UNUSED(husart);
01650
01651   /* NOTE : This function should not be modified, when the callback is needed,
01652             the HAL_USART_TxRxCpltCallback can be implemented in the user file
01653    */
01654 }
01655
01656 /**
01657   * @brief  USART error callback.
01658   * @param  husart USART handle.
01659   * @retval None
01660   */
01661 __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
01662 {
01663   /* Prevent unused argument(s) compilation warning */
01664   UNUSED(husart);
01665
01666   /* NOTE : This function should not be modified, when the callback is needed,
01667             the HAL_USART_ErrorCallback can be implemented in the user file.
01668    */
01669 }
01670
01671 /**
01672   * @brief  USART Abort Complete callback.
01673   * @param  husart USART handle.
01674   * @retval None
01675   */
01676 __weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
01677 {
01678   /* Prevent unused argument(s) compilation warning */
01679   UNUSED(husart);
01680
01681   /* NOTE : This function should not be modified, when the callback is needed,
01682             the HAL_USART_AbortCpltCallback can be implemented in the user file.
01683    */
01684 }
01685
01686 /**
01687   * @}
01688   */
01689
01690 /** @defgroup USART_Exported_Functions_Group3 Peripheral State and Error functions
01691  *  @brief   USART Peripheral State and Error functions
01692  *
01693 @verbatim
01694   ==============================================================================
01695             ##### Peripheral State and Error functions #####
01696   ==============================================================================
01697     [..]
01698     This subsection provides functions allowing to :
01699       (+) Return the USART handle state
01700       (+) Return the USART handle error code
01701
01702 @endverbatim
01703   * @{
01704   */
01705
01706
01707 /**
01708   * @brief  Return the USART handle state.
01709   * @param  husart pointer to a USART_HandleTypeDef structure that contains
01710   *                  the configuration information for the specified USART.
01711   * @retval USART handle state
01712   */
01713 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
01714 {
01715   return husart->State;
01716 }
01717
01718 /**
01719   * @brief  Return the USART error code.
01720   * @param  husart pointer to a USART_HandleTypeDef structure that contains
01721   *                  the configuration information for the specified USART.
01722   * @retval USART handle Error Code
01723   */
01724 uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
01725 {
01726   return husart->ErrorCode;
01727 }
01728
01729 /**
01730   * @}
01731   */
01732
01733 /**
01734   * @}
01735   */
01736
01737 /** @defgroup USART_Private_Functions USART Private Functions
01738   * @brief   USART Private functions
01739   *
01740 @verbatim
01741     [..]
01742     This subsection provides a set of functions allowing to control the USART.
01743      (+) USART_SetConfig() API is used to set the USART communication parameters.
01744      (+) USART_CheckIdleState() APi ensures that TEACK and/or REACK bits are set after initialization
01745
01746 @endverbatim
01747   * @{
01748   */
01749 /**
01750   * @brief  End ongoing transfer on USART peripheral (following error detection or Transfer completion).
01751   * @param  husart USART handle.
01752   * @retval None
01753   */
01754 static void USART_EndTransfer(USART_HandleTypeDef *husart)
01755 {
01756   /* Disable TXEIE and TCIE interrupts */
01757   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01758   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | USART_CR1_PEIE));
01759   CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01760
01761   /* At end of process, restore husart->State to Ready */
01762   husart->State = HAL_USART_STATE_READY;
01763 }
01764
01765 /**
01766   * @brief  DMA USART transmit process complete callback.
01767   * @param  hdma DMA handle.
01768   * @retval None
01769   */
01770 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01771 {
01772   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01773
01774   /* DMA Normal mode */
01775   if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
01776   {
01777     husart->TxXferCount = 0U;
01778
01779     if(husart->State == HAL_USART_STATE_BUSY_TX)
01780     {
01781       /* Disable the DMA transfer for transmit request by resetting the DMAT bit
01782          in the USART CR3 register */
01783       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01784
01785       /* Enable the USART Transmit Complete Interrupt */
01786       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
01787     }
01788   }
01789   /* DMA Circular mode */
01790   else
01791   {
01792     if(husart->State == HAL_USART_STATE_BUSY_TX)
01793     {
01794       HAL_USART_TxCpltCallback(husart);
01795     }
01796   }
01797 }
01798
01799 /**
01800   * @brief  DMA USART transmit process half complete callback.
01801   * @param  hdma DMA handle.
01802   * @retval None
01803   */
01804 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01805 {
01806   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01807
01808   HAL_USART_TxHalfCpltCallback(husart);
01809 }
01810
01811 /**
01812   * @brief  DMA USART receive process complete callback.
01813   * @param  hdma DMA handle.
01814   * @retval None
01815   */
01816 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01817 {
01818   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01819
01820   /* DMA Normal mode */
01821   if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
01822   {
01823     husart->RxXferCount = 0U;
01824
01825     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01826     CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01827     CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01828
01829     /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
01830        in USART CR3 register */
01831     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01832     /* similarly, disable the DMA TX transfer that was started to provide the
01833        clock to the slave device */
01834     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01835
01836     if(husart->State == HAL_USART_STATE_BUSY_RX)
01837     {
01838       HAL_USART_RxCpltCallback(husart);
01839     }
01840     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
01841     else
01842     {
01843       HAL_USART_TxRxCpltCallback(husart);
01844     }
01845     husart->State= HAL_USART_STATE_READY;
01846   }
01847   /* DMA circular mode */
01848   else
01849   {
01850     if(husart->State == HAL_USART_STATE_BUSY_RX)
01851     {
01852       HAL_USART_RxCpltCallback(husart);
01853     }
01854     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
01855     else
01856     {
01857       HAL_USART_TxRxCpltCallback(husart);
01858     }
01859   }
01860
01861 }
01862
01863 /**
01864   * @brief  DMA USART receive process half complete callback.
01865   * @param  hdma DMA handle.
01866   * @retval None
01867   */
01868 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01869 {
01870   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01871
01872   HAL_USART_RxHalfCpltCallback(husart);
01873 }
01874
01875 /**
01876   * @brief  DMA USART communication error callback.
01877   * @param  hdma DMA handle.
01878   * @retval None
01879   */
01880 static void USART_DMAError(DMA_HandleTypeDef *hdma)
01881 {
01882   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01883
01884   husart->RxXferCount = 0U;
01885   husart->TxXferCount = 0U;
01886   USART_EndTransfer(husart);
01887
01888   husart->ErrorCode |= HAL_USART_ERROR_DMA;
01889   husart->State= HAL_USART_STATE_READY;
01890
01891   HAL_USART_ErrorCallback(husart);
01892 }
01893
01894 /**
01895   * @brief  DMA USART communication abort callback, when initiated by HAL services on Error
01896   *         (To be called at end of DMA Abort procedure following error occurrence).
01897   * @param  hdma DMA handle.
01898   * @retval None
01899   */
01900 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
01901 {
01902   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01903   husart->RxXferCount = 0U;
01904   husart->TxXferCount = 0U;
01905
01906   HAL_USART_ErrorCallback(husart);
01907 }
01908
01909 /**
01910   * @brief  DMA USART Tx communication abort callback, when initiated by user
01911   *         (To be called at end of DMA Tx Abort procedure following user abort request).
01912   * @note   When this callback is executed, User Abort complete call back is called only if no
01913   *         Abort still ongoing for Rx DMA Handle.
01914   * @param  hdma DMA handle.
01915   * @retval None
01916   */
01917 static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
01918 {
01919   USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
01920
01921   husart->hdmatx->XferAbortCallback = NULL;
01922
01923   /* Check if an Abort process is still ongoing */
01924   if(husart->hdmarx != NULL)
01925   {
01926     if(husart->hdmarx->XferAbortCallback != NULL)
01927     {
01928       return;
01929     }
01930   }
01931
01932   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
01933   husart->TxXferCount = 0U;
01934   husart->RxXferCount = 0U;
01935
01936   /* Reset errorCode */
01937   husart->ErrorCode = HAL_USART_ERROR_NONE;
01938
01939   /* Clear the Error flags in the ICR register */
01940   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
01941
01942   /* Restore husart->State to Ready */
01943   husart->State  = HAL_USART_STATE_READY;
01944
01945   /* Call user Abort complete callback */
01946   HAL_USART_AbortCpltCallback(husart);
01947 }
01948
01949
01950 /**
01951   * @brief  DMA USART Rx communication abort callback, when initiated by user
01952   *         (To be called at end of DMA Rx Abort procedure following user abort request).
01953   * @note   When this callback is executed, User Abort complete call back is called only if no
01954   *         Abort still ongoing for Tx DMA Handle.
01955   * @param  hdma DMA handle.
01956   * @retval None
01957   */
01958 static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
01959 {
01960   USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
01961
01962   husart->hdmarx->XferAbortCallback = NULL;
01963
01964   /* Check if an Abort process is still ongoing */
01965   if(husart->hdmatx != NULL)
01966   {
01967     if(husart->hdmatx->XferAbortCallback != NULL)
01968     {
01969       return;
01970     }
01971   }
01972
01973   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
01974   husart->TxXferCount = 0U;
01975   husart->RxXferCount = 0U;
01976
01977   /* Reset errorCode */
01978   husart->ErrorCode = HAL_USART_ERROR_NONE;
01979
01980   /* Clear the Error flags in the ICR register */
01981   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
01982
01983   /* Restore husart->State to Ready */
01984   husart->State  = HAL_USART_STATE_READY;
01985
01986   /* Call user Abort complete callback */
01987   HAL_USART_AbortCpltCallback(husart);
01988 }
01989
01990
01991 /**
01992   * @brief  Handle USART Communication Timeout.
01993   * @param  husart USART handle.
01994   * @param  Flag Specifies the USART flag to check.
01995   * @param  Status the Flag status (SET or RESET).
01996   * @param  Tickstart Tick start value
01997   * @param  Timeout timeout duration.
01998   * @retval HAL status
01999   */
02000 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
02001 {
02002   /* Wait until flag is set */
02003   while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
02004   {
02005     /* Check for the Timeout */
02006     if(Timeout != HAL_MAX_DELAY)
02007     {
02008       if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
02009       {
02010         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
02011         CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
02012         CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
02013
02014         husart->State= HAL_USART_STATE_READY;
02015
02016         /* Process Unlocked */
02017         __HAL_UNLOCK(husart);
02018
02019         return HAL_TIMEOUT;
02020       }
02021     }
02022   }
02023   return HAL_OK;
02024 }
02025
02026
02027 /**
02028   * @brief Configure the USART peripheral.
02029   * @param husart USART handle.
02030   * @retval HAL status
02031   */
02032 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
02033 {
02034   uint32_t tmpreg                      = 0x0U;
02035   USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
02036   HAL_StatusTypeDef ret                = HAL_OK;
02037   uint16_t brrtemp                     = 0x0000U;
02038   uint16_t usartdiv                    = 0x0000U;
02039
02040   /* Check the parameters */
02041   assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
02042   assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
02043   assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
02044   assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
02045   assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
02046   assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
02047   assert_param(IS_USART_PARITY(husart->Init.Parity));
02048   assert_param(IS_USART_MODE(husart->Init.Mode));
02049
02050
02051   /*-------------------------- USART CR1 Configuration -----------------------*/
02052    /* Clear M, PCE, PS, TE and RE bits and configure
02053    *  the USART Word Length, Parity and Mode:
02054    *  set the M bits according to husart->Init.WordLength value
02055    *  set PCE and PS bits according to husart->Init.Parity value
02056    *  set TE and RE bits according to husart->Init.Mode value
02057    *  force OVER8 to 1 to allow to reach the maximum speed (Fclock/8)  */
02058   tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
02059   MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
02060
02061   /*---------------------------- USART CR2 Configuration ---------------------*/
02062   /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
02063    * set CPOL bit according to husart->Init.CLKPolarity value
02064    * set CPHA bit according to husart->Init.CLKPhase value
02065    * set LBCL bit according to husart->Init.CLKLastBit value
02066    * set STOP[13:12] bits according to husart->Init.StopBits value */
02067   tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
02068   tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
02069   tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);
02070   MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
02071
02072   /*-------------------------- USART CR3 Configuration -----------------------*/
02073   /* no CR3 register configuration                                            */
02074
02075   /*-------------------------- USART BRR Configuration -----------------------*/
02076   /* BRR is filled-up according to OVER8 bit setting which is forced to 1     */
02077   USART_GETCLOCKSOURCE(husart, clocksource);
02078   switch (clocksource)
02079   {
02080     case USART_CLOCKSOURCE_PCLK1:
02081       usartdiv = (uint16_t)(((2U*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
02082       break;
02083     case USART_CLOCKSOURCE_PCLK2:
02084       usartdiv = (uint16_t)(((2U*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
02085       break;
02086     case USART_CLOCKSOURCE_HSI:
02087       usartdiv = (uint16_t)(((2U*HSI_VALUE) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
02088       break;
02089     case USART_CLOCKSOURCE_SYSCLK:
02090       usartdiv = (uint16_t)(((2U*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
02091       break;
02092     case USART_CLOCKSOURCE_LSE:
02093       usartdiv = (uint16_t)(((2U*LSE_VALUE) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
02094       break;
02095     case USART_CLOCKSOURCE_UNDEFINED:
02096     default:
02097       ret = HAL_ERROR;
02098       break;
02099   }
02100
02101   brrtemp = usartdiv & 0xFFF0U;
02102   brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
02103   husart->Instance->BRR = brrtemp;
02104
02105   return ret;
02106 }
02107
02108 /**
02109   * @brief Check the USART Idle State.
02110   * @param husart USART handle.
02111   * @retval HAL status
02112   */
02113 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
02114 {
02115   uint32_t tickstart = 0U;
02116
02117   /* Initialize the USART ErrorCode */
02118   husart->ErrorCode = HAL_USART_ERROR_NONE;
02119
02120   /* Init tickstart for timeout managment*/
02121   tickstart = HAL_GetTick();
02122
02123   /* Check if the Transmitter is enabled */
02124   if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
02125   {
02126     /* Wait until TEACK flag is set */
02127     if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
02128     {
02129       /* Timeout Occured */
02130       return HAL_TIMEOUT;
02131     }
02132   }
02133
02134   /* REACK bit in ISR is checked only when available (not to be checked on all instances).
02135      Bit is defined only for USART instances supporting WakeUp from Stop Mode feature.
02136   */
02137   if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(husart->Instance))
02138   {
02139     /* Check if the Receiver is enabled */
02140     if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
02141     {
02142       /* Wait until REACK flag is set */
02143       if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
02144       {
02145         /* Timeout occurred */
02146         return HAL_TIMEOUT;
02147       }
02148     }
02149   }
02150
02151   /* Initialize the USART state*/
02152   husart->State= HAL_USART_STATE_READY;
02153
02154   /* Process Unlocked */
02155   __HAL_UNLOCK(husart);
02156
02157   return HAL_OK;
02158 }
02159
02160
02161 /**
02162   * @brief  Simplex send an amount of data in non-blocking mode.
02163   * @note   Function called under interruption only, once
02164   *         interruptions have been enabled by HAL_USART_Transmit_IT().
02165   * @note   The USART errors are not managed to avoid the overrun error.
02166   * @param  husart USART handle.
02167   * @retval HAL status
02168   */
02169 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
02170 {
02171   uint16_t* tmp=0U;
02172
02173   /* Check that a Tx process is ongoing */
02174   if(husart->State == HAL_USART_STATE_BUSY_TX)
02175   {
02176
02177     if(husart->TxXferCount == 0U)
02178     {
02179       /* Disable the USART Transmit data register empty interrupt */
02180       __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
02181
02182       /* Enable the USART Transmit Complete Interrupt */
02183       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
02184
02185       return HAL_OK;
02186     }
02187     else
02188     {
02189       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
02190       {
02191         tmp = (uint16_t*) husart->pTxBuffPtr;
02192         husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
02193         husart->pTxBuffPtr += 2U;
02194       }
02195       else
02196       {
02197         husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFFU);
02198       }
02199
02200       husart->TxXferCount--;
02201
02202       return HAL_OK;
02203     }
02204   }
02205   else
02206   {
02207     return HAL_BUSY;
02208   }
02209 }
02210
02211
02212 /**
02213   * @brief  Wraps up transmission in non-blocking mode.
02214   * @param  husart Pointer to a USART_HandleTypeDef structure that contains
02215   *                the configuration information for the specified USART module.
02216   * @retval HAL status
02217   */
02218 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
02219 {
02220   /* Disable the USART Transmit Complete Interrupt */
02221   __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
02222
02223   /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
02224   __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
02225
02226   /* Tx process is ended, restore husart->State to Ready */
02227   husart->State = HAL_USART_STATE_READY;
02228
02229   HAL_USART_TxCpltCallback(husart);
02230
02231   return HAL_OK;
02232 }
02233
02234
02235 /**
02236   * @brief  Simplex receive an amount of data in non-blocking mode.
02237   * @note   Function called under interruption only, once
02238   *         interruptions have been enabled by HAL_USART_Receive_IT().
02239   * @param  husart USART handle
02240   * @retval HAL status
02241   */
02242 static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
02243 {
02244   uint16_t* tmp=0U;
02245   uint16_t uhMask = husart->Mask;
02246
02247   if(husart->State == HAL_USART_STATE_BUSY_RX)
02248   {
02249
02250     if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
02251     {
02252       tmp = (uint16_t*) husart->pRxBuffPtr;
02253       *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
02254       husart->pRxBuffPtr += 2U;
02255     }
02256     else
02257     {
02258       *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
02259     }
02260
02261     /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
02262     husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
02263
02264     if(--husart->RxXferCount == 0U)
02265     {
02266       /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
02267       CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
02268
02269       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
02270       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
02271
02272       /* Rx process is completed, restore husart->State to Ready */
02273       husart->State = HAL_USART_STATE_READY;
02274
02275       HAL_USART_RxCpltCallback(husart);
02276
02277       return HAL_OK;
02278     }
02279
02280     return HAL_OK;
02281   }
02282   else
02283   {
02284     return HAL_BUSY;
02285   }
02286 }
02287
02288 /**
02289   * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
02290   * @note   Function called under interruption only, once
02291   *         interruptions have been enabled by HAL_USART_TransmitReceive_IT().
02292   * @param  husart USART handle.
02293   * @retval HAL status
02294   */
02295 static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
02296 {
02297   uint16_t* tmp=0U;
02298   uint16_t uhMask = husart->Mask;
02299
02300   if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
02301   {
02302
02303     if(husart->TxXferCount != 0x00U)
02304     {
02305       if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
02306       {
02307         if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
02308         {
02309           tmp = (uint16_t*) husart->pTxBuffPtr;
02310           husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
02311           husart->pTxBuffPtr += 2U;
02312         }
02313         else
02314         {
02315           husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
02316         }
02317         husart->TxXferCount--;
02318
02319         /* Check the latest data transmitted */
02320         if(husart->TxXferCount == 0U)
02321         {
02322            __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
02323         }
02324       }
02325     }
02326
02327     if(husart->RxXferCount != 0x00U)
02328     {
02329       if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
02330       {
02331         if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
02332         {
02333           tmp = (uint16_t*) husart->pRxBuffPtr;
02334           *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
02335           husart->pRxBuffPtr += 2U;
02336         }
02337         else
02338         {
02339           *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
02340         }
02341         husart->RxXferCount--;
02342       }
02343     }
02344
02345     /* Check the latest data received */
02346     if(husart->RxXferCount == 0U)
02347     {
02348       /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
02349       CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
02350
02351       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
02352       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
02353
02354       /* Rx process is completed, restore husart->State to Ready */
02355       husart->State = HAL_USART_STATE_READY;
02356
02357       HAL_USART_TxRxCpltCallback(husart);
02358
02359       return HAL_OK;
02360     }
02361
02362     return HAL_OK;
02363   }
02364   else
02365   {
02366     return HAL_BUSY;
02367   }
02368 }
02369
02370 /**
02371   * @}
02372   */
02373
02374 #endif /* HAL_USART_MODULE_ENABLED */
02375 /**
02376   * @}
02377   */
02378
02379 /**
02380   * @}
02381   */
02382
02383 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_usart.h Source File

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stm32f3xx_hal_usart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_usart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of USART HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_USART_H
00038 #define __STM32F3xx_HAL_USART_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup USART
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /** @defgroup USART_Exported_Types USART Exported Types
00057   * @{
00058   */
00059
00060 /**
00061   * @brief USART Init Structure definition
00062   */
00063 typedef struct
00064 {
00065   uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
00066                                            The baud rate is computed using the following formula:
00067                                               Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))). */
00068
00069   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00070                                            This parameter can be a value of @ref USARTEx_Word_Length. */
00071
00072   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00073                                            This parameter can be a value of @ref USART_Stop_Bits. */
00074
00075   uint32_t Parity;                   /*!< Specifies the parity mode.
00076                                            This parameter can be a value of @ref USART_Parity
00077                                            @note When parity is enabled, the computed parity is inserted
00078                                                  at the MSB position of the transmitted data (9th bit when
00079                                                  the word length is set to 9 data bits; 8th bit when the
00080                                                  word length is set to 8 data bits). */
00081
00082   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00083                                            This parameter can be a value of @ref USART_Mode. */
00084
00085   uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00086                                            This parameter can be a value of @ref USART_Clock_Polarity. */
00087
00088   uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00089                                            This parameter can be a value of @ref USART_Clock_Phase. */
00090
00091   uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00092                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00093                                            This parameter can be a value of @ref USART_Last_Bit. */
00094 }USART_InitTypeDef;
00095
00096 /**
00097   * @brief HAL USART State structures definition
00098   */
00099 typedef enum
00100 {
00101   HAL_USART_STATE_RESET             = 0x00U,    /*!< Peripheral is not initialized                  */
00102   HAL_USART_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use       */
00103   HAL_USART_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                 */
00104   HAL_USART_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing           */
00105   HAL_USART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing              */
00106   HAL_USART_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission Reception process is ongoing */
00107   HAL_USART_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                                  */
00108   HAL_USART_STATE_ERROR             = 0x04U     /*!< Error                                          */
00109 }HAL_USART_StateTypeDef;
00110
00111 /**
00112   * @brief  USART clock sources definitions
00113   */
00114 typedef enum
00115 {
00116   USART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source     */
00117   USART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source     */
00118   USART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source       */
00119   USART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source    */
00120   USART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */
00121   USART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */
00122 }USART_ClockSourceTypeDef;
00123
00124
00125 /**
00126   * @brief  USART handle Structure definition
00127   */
00128 typedef struct
00129 {
00130   USART_TypeDef                 *Instance;        /*!< USART registers base address        */
00131
00132   USART_InitTypeDef             Init;             /*!< USART communication parameters      */
00133
00134   uint8_t                       *pTxBuffPtr;      /*!< Pointer to USART Tx transfer Buffer */
00135
00136   uint16_t                      TxXferSize;       /*!< USART Tx Transfer size              */
00137
00138   __IO uint16_t                 TxXferCount;      /*!< USART Tx Transfer Counter           */
00139
00140   uint8_t                       *pRxBuffPtr;      /*!< Pointer to USART Rx transfer Buffer */
00141
00142   uint16_t                      RxXferSize;       /*!< USART Rx Transfer size              */
00143
00144   __IO uint16_t                 RxXferCount;      /*!< USART Rx Transfer Counter           */
00145
00146   uint16_t                      Mask;             /*!< USART Rx RDR register mask          */
00147
00148   DMA_HandleTypeDef             *hdmatx;          /*!< USART Tx DMA Handle parameters      */
00149
00150   DMA_HandleTypeDef             *hdmarx;          /*!< USART Rx DMA Handle parameters      */
00151
00152   HAL_LockTypeDef               Lock;             /*!< Locking object                      */
00153
00154   __IO HAL_USART_StateTypeDef   State;            /*!< USART communication state           */
00155
00156   __IO uint32_t                 ErrorCode;        /*!< USART Error code                    */
00157
00158 }USART_HandleTypeDef;
00159
00160 /**
00161   * @}
00162   */
00163
00164 /* Exported constants --------------------------------------------------------*/
00165 /** @defgroup USART_Exported_Constants USART Exported Constants
00166   * @{
00167   */
00168
00169 /** @defgroup USART_Error USART Error
00170   * @{
00171   */
00172 #define HAL_USART_ERROR_NONE      (0x00000000U)    /*!< No error            */
00173 #define HAL_USART_ERROR_PE        (0x00000001U)    /*!< Parity error        */
00174 #define HAL_USART_ERROR_NE        (0x00000002U)    /*!< Noise error         */
00175 #define HAL_USART_ERROR_FE        (0x00000004U)    /*!< frame error         */
00176 #define HAL_USART_ERROR_ORE       (0x00000008U)    /*!< Overrun error       */
00177 #define HAL_USART_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error  */
00178 /**
00179   * @}
00180   */
00181
00182 /** @defgroup USART_Stop_Bits  USART Number of Stop Bits
00183   * @{
00184   */
00185 #define USART_STOPBITS_0_5                  ((uint32_t)USART_CR2_STOP_0)                      /*!< USART frame with 0.5 stop bit  */
00186 #define USART_STOPBITS_1                    (0x00000000U)                                     /*!< USART frame with 1 stop bit    */
00187 #define USART_STOPBITS_1_5                  ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< USART frame with 1.5 stop bits */
00188 #define USART_STOPBITS_2                    ((uint32_t)USART_CR2_STOP_1)                      /*!< USART frame with 2 stop bits   */
00189 /**
00190   * @}
00191   */
00192
00193 /** @defgroup USART_Parity    USART Parity
00194   * @{
00195   */
00196 #define USART_PARITY_NONE                   (0x00000000U)                               /*!< No parity   */
00197 #define USART_PARITY_EVEN                   ((uint32_t)USART_CR1_PCE)                   /*!< Even parity */
00198 #define USART_PARITY_ODD                    ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))  /*!< Odd parity  */
00199 /**
00200   * @}
00201   */
00202
00203 /** @defgroup USART_Mode   USART Mode
00204   * @{
00205   */
00206 #define USART_MODE_RX                       ((uint32_t)USART_CR1_RE)                   /*!< RX mode        */
00207 #define USART_MODE_TX                       ((uint32_t)USART_CR1_TE)                   /*!< TX mode        */
00208 #define USART_MODE_TX_RX                    ((uint32_t)(USART_CR1_TE |USART_CR1_RE))   /*!< RX and TX mode */
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup USART_Clock  USART Clock
00214   * @{
00215   */
00216 #define USART_CLOCK_DISABLE                 (0x00000000U)                 /*!< USART clock disable */
00217 #define USART_CLOCK_ENABLE                  ((uint32_t)USART_CR2_CLKEN)   /*!< USART clock enable  */
00218 /**
00219   * @}
00220   */
00221
00222 /** @defgroup USART_Clock_Polarity  USART Clock Polarity
00223   * @{
00224   */
00225 #define USART_POLARITY_LOW                  (0x00000000U)                /*!< USART Clock signal is steady Low  */
00226 #define USART_POLARITY_HIGH                 ((uint32_t)USART_CR2_CPOL)   /*!< USART Clock signal is steady High */
00227 /**
00228   * @}
00229   */
00230
00231 /** @defgroup USART_Clock_Phase   USART Clock Phase
00232   * @{
00233   */
00234 #define USART_PHASE_1EDGE                   (0x00000000U)                /*!< USART frame phase on first clock transition  */
00235 #define USART_PHASE_2EDGE                   ((uint32_t)USART_CR2_CPHA)   /*!< USART frame phase on second clock transition */
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup USART_Last_Bit  USART Last Bit
00241   * @{
00242   */
00243 #define USART_LASTBIT_DISABLE               (0x00000000U)                /*!< USART frame last data bit clock pulse not output to SCLK pin */
00244 #define USART_LASTBIT_ENABLE                ((uint32_t)USART_CR2_LBCL)   /*!< USART frame last data bit clock pulse output to SCLK pin     */
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup USART_Request_Parameters  USART Request Parameters
00250   * @{
00251   */
00252 #define USART_RXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_RXFRQ)    /*!< Receive Data flush Request  */
00253 #define USART_TXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_TXFRQ)    /*!< Transmit data flush Request */
00254 /**
00255   * @}
00256   */
00257
00258 /** @defgroup USART_Flags      USART Flags
00259   *        Elements values convention: 0xXXXX
00260   *           - 0xXXXX  : Flag mask in the ISR register
00261   * @{
00262   */
00263 #define USART_FLAG_REACK                     (0x00400000U)    /*!< USART receive enable acknowledge flag  */
00264 #define USART_FLAG_TEACK                     (0x00200000U)    /*!< USART transmit enable acknowledge flag */
00265 #define USART_FLAG_BUSY                      (0x00010000U)    /*!< USART busy flag                        */
00266 #define USART_FLAG_CTS                       (0x00000400U)    /*!< USART clear to send flag               */
00267 #define USART_FLAG_CTSIF                     (0x00000200U)    /*!< USART clear to send interrupt flag     */
00268 #define USART_FLAG_LBDF                      (0x00000100U)    /*!< USART LIN break detection flag         */
00269 #define USART_FLAG_TXE                       (0x00000080U)    /*!< USART transmit data register empty     */
00270 #define USART_FLAG_TC                        (0x00000040U)    /*!< USART transmission complete            */
00271 #define USART_FLAG_RXNE                      (0x00000020U)    /*!< USART read data register not empty     */
00272 #define USART_FLAG_IDLE                      (0x00000010U)    /*!< USART idle flag                        */
00273 #define USART_FLAG_ORE                       (0x00000008U)    /*!< USART overrun error                    */
00274 #define USART_FLAG_NE                        (0x00000004U)    /*!< USART noise error                      */
00275 #define USART_FLAG_FE                        (0x00000002U)    /*!< USART frame error                      */
00276 #define USART_FLAG_PE                        (0x00000001U)    /*!< USART parity error                     */
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup USART_Interrupt_definition USART Interrupts Definition
00282   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00283   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00284   *           - XX  : Interrupt source register (2bits)
00285   *                 - 01: CR1 register
00286   *                 - 10: CR2 register
00287   *                 - 11: CR3 register
00288   *           - ZZZZ  : Flag position in the ISR register(4bits)
00289   * @{
00290   */
00291
00292 #define USART_IT_PE                          ((uint16_t)0x0028U)     /*!< USART parity error interruption                 */
00293 #define USART_IT_TXE                         ((uint16_t)0x0727U)     /*!< USART transmit data register empty interruption */
00294 #define USART_IT_TC                          ((uint16_t)0x0626U)     /*!< USART transmission complete interruption        */
00295 #define USART_IT_RXNE                        ((uint16_t)0x0525U)     /*!< USART read data register not empty interruption */
00296 #define USART_IT_IDLE                        ((uint16_t)0x0424U)     /*!< USART idle interruption                         */
00297 #define USART_IT_ERR                         ((uint16_t)0x0060U)     /*!< USART error interruption                        */
00298 #define USART_IT_ORE                         ((uint16_t)0x0300U)     /*!< USART overrun error interruption                */
00299 #define USART_IT_NE                          ((uint16_t)0x0200U)     /*!< USART noise error interruption                  */
00300 #define USART_IT_FE                          ((uint16_t)0x0100U)     /*!< USART frame error interruption                  */
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup USART_IT_CLEAR_Flags    USART Interruption Clear Flags
00306   * @{
00307   */
00308 #define USART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
00309 #define USART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
00310 #define USART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag        */
00311 #define USART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
00312 #define USART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
00313 #define USART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
00314 #define USART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag         */
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup USART_Interruption_Mask    USART Interruption Flags Mask
00320   * @{
00321   */
00322 #define USART_IT_MASK                             ((uint16_t)0x001FU)     /*!< USART interruptions flags mask */
00323 /**
00324   * @}
00325   */
00326
00327 /**
00328   * @}
00329   */
00330
00331 /* Exported macros -----------------------------------------------------------*/
00332 /** @defgroup USART_Exported_Macros USART Exported Macros
00333   * @{
00334   */
00335
00336 /** @brief  Reset USART handle state.
00337   * @param  __HANDLE__ USART handle.
00338   * @retval None
00339   */
00340 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
00341
00342 /** @brief  Flush the USART Data registers.
00343   * @param  __HANDLE__ specifies the USART Handle.
00344   * @retval None
00345   */
00346 #define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__)  \
00347   do{                \
00348       SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
00349       SET_BIT((__HANDLE__)->Instance->RQR, USART_TXDATA_FLUSH_REQUEST); \
00350     }  while(0U)
00351
00352 /** @brief  Check whether the specified USART flag is set or not.
00353   * @param  __HANDLE__ specifies the USART Handle
00354   * @param  __FLAG__ specifies the flag to check.
00355   *        This parameter can be one of the following values:
00356   *            @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
00357   *            @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
00358   *            @arg @ref USART_FLAG_BUSY  Busy flag
00359   *            @arg @ref USART_FLAG_CTS   CTS Change flag
00360   *            @arg @ref USART_FLAG_TXE   Transmit data register empty flag
00361   *            @arg @ref USART_FLAG_TC    Transmission Complete flag
00362   *            @arg @ref USART_FLAG_RXNE  Receive data register not empty flag
00363   *            @arg @ref USART_FLAG_IDLE  Idle Line detection flag
00364   *            @arg @ref USART_FLAG_ORE   OverRun Error flag
00365   *            @arg @ref USART_FLAG_NE    Noise Error flag
00366   *            @arg @ref USART_FLAG_FE    Framing Error flag
00367   *            @arg @ref USART_FLAG_PE    Parity Error flag
00368   * @retval The new state of __FLAG__ (TRUE or FALSE).
00369   */
00370 #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00371
00372 /** @brief  Clear the specified USART pending flag.
00373   * @param  __HANDLE__ specifies the USART Handle.
00374   * @param  __FLAG__ specifies the flag to check.
00375   *          This parameter can be any combination of the following values:
00376   *            @arg @ref USART_CLEAR_PEF
00377   *            @arg @ref USART_CLEAR_FEF
00378   *            @arg @ref USART_CLEAR_NEF
00379   *            @arg @ref USART_CLEAR_OREF
00380   *            @arg @ref USART_CLEAR_IDLEF
00381   *            @arg @ref USART_CLEAR_TCF
00382   *            @arg @ref USART_CLEAR_CTSF
00383   * @retval None
00384   */
00385 #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00386
00387 /** @brief  Clear the USART PE pending flag.
00388   * @param  __HANDLE__ specifies the USART Handle.
00389   * @retval None
00390   */
00391 #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
00392
00393 /** @brief  Clear the USART FE pending flag.
00394   * @param  __HANDLE__ specifies the USART Handle.
00395   * @retval None
00396   */
00397 #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
00398
00399 /** @brief  Clear the USART NE pending flag.
00400   * @param  __HANDLE__ specifies the USART Handle.
00401   * @retval None
00402   */
00403 #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__)  __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
00404
00405 /** @brief  Clear the USART ORE pending flag.
00406   * @param  __HANDLE__ specifies the USART Handle.
00407   * @retval None
00408   */
00409 #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
00410
00411 /** @brief  Clear the USART IDLE pending flag.
00412   * @param  __HANDLE__ specifies the USART Handle.
00413   * @retval None
00414   */
00415 #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
00416
00417 /** @brief  Enable the specified USART interrupt.
00418   * @param  __HANDLE__ specifies the USART Handle.
00419   * @param  __INTERRUPT__ specifies the USART interrupt source to enable.
00420   *          This parameter can be one of the following values:
00421   *            @arg @ref USART_IT_TXE  Transmit Data Register empty interrupt
00422   *            @arg @ref USART_IT_TC   Transmission complete interrupt
00423   *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
00424   *            @arg @ref USART_IT_IDLE Idle line detection interrupt
00425   *            @arg @ref USART_IT_PE   Parity Error interrupt
00426   *            @arg @ref USART_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00427   * @retval None
00428   */
00429 #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00430                                                             ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00431                                                             ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
00432
00433 /** @brief  Disable the specified USART interrupt.
00434   * @param  __HANDLE__ specifies the USART Handle.
00435   * @param  __INTERRUPT__ specifies the USART interrupt source to disable.
00436   *          This parameter can be one of the following values:
00437   *            @arg @ref USART_IT_TXE  Transmit Data Register empty interrupt
00438   *            @arg @ref USART_IT_TC   Transmission complete interrupt
00439   *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
00440   *            @arg @ref USART_IT_IDLE Idle line detection interrupt
00441   *            @arg @ref USART_IT_PE   Parity Error interrupt
00442   *            @arg @ref USART_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00443   * @retval None
00444   */
00445 #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00446                                                             ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00447                                                             ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
00448
00449
00450 /** @brief  Check whether the specified USART interrupt has occurred or not.
00451   * @param  __HANDLE__ specifies the USART Handle.
00452   * @param  __IT__ specifies the USART interrupt source to check.
00453   *          This parameter can be one of the following values:
00454   *            @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
00455   *            @arg @ref USART_IT_TC  Transmission complete interrupt
00456   *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
00457   *            @arg @ref USART_IT_IDLE Idle line detection interrupt
00458   *            @arg @ref USART_IT_ORE OverRun Error interrupt
00459   *            @arg @ref USART_IT_NE Noise Error interrupt
00460   *            @arg @ref USART_IT_FE Framing Error interrupt
00461   *            @arg @ref USART_IT_PE Parity Error interrupt
00462   * @retval The new state of __IT__ (TRUE or FALSE).
00463   */
00464 #define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
00465
00466 /** @brief  Check whether the specified USART interrupt source is enabled or not.
00467   * @param  __HANDLE__ specifies the USART Handle.
00468   * @param  __IT__ specifies the USART interrupt source to check.
00469   *          This parameter can be one of the following values:
00470   *            @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
00471   *            @arg @ref USART_IT_TC  Transmission complete interrupt
00472   *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
00473   *            @arg @ref USART_IT_IDLE Idle line detection interrupt
00474   *            @arg @ref USART_IT_ORE OverRun Error interrupt
00475   *            @arg @ref USART_IT_NE Noise Error interrupt
00476   *            @arg @ref USART_IT_FE Framing Error interrupt
00477   *            @arg @ref USART_IT_PE Parity Error interrupt
00478   * @retval The new state of __IT__ (TRUE or FALSE).
00479   */
00480 #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
00481                                                    (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << \
00482                                                    (((uint16_t)(__IT__)) & USART_IT_MASK)))
00483
00484
00485 /** @brief  Clear the specified USART ISR flag, in setting the proper ICR register flag.
00486   * @param  __HANDLE__ specifies the USART Handle.
00487   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
00488   *                       to clear the corresponding interrupt.
00489   *          This parameter can be one of the following values:
00490   *            @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
00491   *            @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
00492   *            @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
00493   *            @arg @ref USART_CLEAR_OREF OverRun Error Clear Flag
00494   *            @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
00495   *            @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
00496   *            @arg @ref USART_CLEAR_CTSF CTS Interrupt Clear Flag
00497   * @retval None
00498   */
00499 #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00500
00501 /** @brief  Set a specific USART request flag.
00502   * @param  __HANDLE__ specifies the USART Handle.
00503   * @param  __REQ__ specifies the request flag to set.
00504   *          This parameter can be one of the following values:
00505   *            @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
00506   *            @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
00507   *
00508   * @retval None
00509   */
00510 #define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__)      ((__HANDLE__)->Instance->RQR |= (__REQ__))
00511
00512 /** @brief  Enable the USART one bit sample method.
00513   * @param  __HANDLE__ specifies the USART Handle.
00514   * @retval None
00515   */
00516 #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00517
00518 /** @brief  Disable the USART one bit sample method.
00519   * @param  __HANDLE__ specifies the USART Handle.
00520   * @retval None
00521   */
00522 #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00523
00524 /** @brief  Enable USART.
00525   * @param  __HANDLE__ specifies the USART Handle.
00526   * @retval None
00527   */
00528 #define __HAL_USART_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00529
00530 /** @brief  Disable USART.
00531   * @param  __HANDLE__ specifies the USART Handle.
00532   * @retval None
00533   */
00534 #define __HAL_USART_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00535
00536 /**
00537   * @}
00538   */
00539
00540 /* Private macros --------------------------------------------------------*/
00541 /** @defgroup USART_Private_Macros   USART Private Macros
00542   * @{
00543   */
00544
00545 /** @brief  Check USART Baud rate.
00546   * @param  __BAUDRATE__ Baudrate specified by the user.
00547   *         The maximum Baud Rate is derived from the maximum clock on F3 (i.e. 72 MHz)
00548   *         divided by the smallest oversampling used on the USART (i.e. 8).
00549   * @retval Test result (TRUE or FALSE).
00550   */
00551 #define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001U)
00552
00553 /**
00554   * @brief Ensure that USART frame number of stop bits is valid.
00555   * @param __STOPBITS__ USART frame number of stop bits.
00556   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
00557   */
00558 #define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
00559                                          ((__STOPBITS__) == USART_STOPBITS_1)   || \
00560                                          ((__STOPBITS__) == USART_STOPBITS_1_5) || \
00561                                          ((__STOPBITS__) == USART_STOPBITS_2))
00562
00563 /**
00564   * @brief Ensure that USART frame parity is valid.
00565   * @param __PARITY__ USART frame parity.
00566   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00567   */
00568 #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
00569                                      ((__PARITY__) == USART_PARITY_EVEN) || \
00570                                      ((__PARITY__) == USART_PARITY_ODD))
00571
00572 /**
00573   * @brief Ensure that USART communication mode is valid.
00574   * @param __MODE__ USART communication mode.
00575   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00576   */
00577 #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
00578
00579 /**
00580   * @brief Ensure that USART clock state is valid.
00581   * @param __CLOCK__ USART clock state.
00582   * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
00583   */
00584 #define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
00585                                    ((__CLOCK__) == USART_CLOCK_ENABLE))
00586
00587 /**
00588   * @brief Ensure that USART frame polarity is valid.
00589   * @param __CPOL__ USART frame polarity.
00590   * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
00591   */
00592 #define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
00593
00594 /**
00595   * @brief Ensure that USART frame phase is valid.
00596   * @param __CPHA__ USART frame phase.
00597   * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
00598   */
00599 #define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
00600
00601 /**
00602   * @brief Ensure that USART frame last bit clock pulse setting is valid.
00603   * @param __LASTBIT__ USART frame last bit clock pulse setting.
00604   * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
00605   */
00606 #define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
00607                                        ((__LASTBIT__) == USART_LASTBIT_ENABLE))
00608
00609 /**
00610   * @brief Ensure that USART request parameter is valid.
00611   * @param __PARAM__ USART request parameter.
00612   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
00613   */
00614 #define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
00615                                                ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
00616
00617 /**
00618   * @}
00619   */
00620
00621 /* Include USART HAL Extended module */
00622 #include "stm32f3xx_hal_usart_ex.h"
00623
00624 /* Exported functions --------------------------------------------------------*/
00625 /** @addtogroup USART_Exported_Functions USART Exported Functions
00626   * @{
00627   */
00628
00629 /** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
00630   * @{
00631   */
00632
00633 /* Initialization and de-initialization functions  ****************************/
00634 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
00635 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
00636 void HAL_USART_MspInit(USART_HandleTypeDef *husart);
00637 void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
00638
00639 /**
00640   * @}
00641   */
00642
00643 /** @addtogroup USART_Exported_Functions_Group2 IO operation functions
00644   * @{
00645   */
00646
00647 /* IO operation functions *****************************************************/
00648 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
00649 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00650 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00651 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
00652 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
00653 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size);
00654 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
00655 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
00656 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
00657 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
00658 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
00659 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
00660 /* Transfer Abort functions */
00661 HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
00662 HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
00663
00664 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
00665 void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
00666 void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
00667 void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
00668 void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
00669 void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
00670 void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
00671 void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
00672
00673 /**
00674   * @}
00675   */
00676
00677 /* Peripheral Control functions ***********************************************/
00678
00679 /** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Error functions
00680   * @{
00681   */
00682
00683 /* Peripheral State and Error functions ***************************************/
00684 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
00685 uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
00686
00687 /**
00688   * @}
00689   */
00690
00691 /**
00692   * @}
00693   */
00694
00695 /**
00696   * @}
00697   */
00698
00699 /**
00700   * @}
00701   */
00702
00703 #ifdef __cplusplus
00704 }
00705 #endif
00706
00707 #endif /* __STM32F3xx_HAL_USART_H */
00708
00709 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00710
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_usart_ex.h Source File

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stm32f3xx_hal_usart_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_usart_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of USART HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_USART_EX_H
00038 #define __STM32F3xx_HAL_USART_EX_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup USARTEx
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 /* Exported constants --------------------------------------------------------*/
00057 /** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
00058   * @{
00059   */
00060
00061 /** @defgroup USARTEx_Word_Length USARTEx Word Length
00062   * @{
00063   */
00064 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00065     defined(STM32F334x8)                                                 || \
00066     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00067 #define USART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long USART frame */
00068 #define USART_WORDLENGTH_8B                  (0x00000000U)              /*!< 8-bit long USART frame */
00069 #define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long USART frame */
00070 #else
00071 #define USART_WORDLENGTH_8B                  (0x00000000U)              /*!< 8-bit long USART frame */
00072 #define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)    /*!< 9-bit long USART frame */
00073 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00074        /* STM32F334x8                               || */
00075        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00076 /**
00077   * @}
00078   */
00079
00080 /**
00081   * @}
00082   */
00083
00084 /* Private macros ------------------------------------------------------------*/
00085 /** @defgroup USARTEx_Private_Macros USARTEx Private Macros
00086   * @{
00087   */
00088
00089 /** @brief  Report the USART clock source.
00090   * @param  __HANDLE__ specifies the USART Handle.
00091   * @param  __CLOCKSOURCE__ output variable.
00092   * @retval the USART clocking source, written in __CLOCKSOURCE__.
00093   */
00094 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
00095     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00096 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00097   do {                                                         \
00098     if((__HANDLE__)->Instance == USART1)                       \
00099     {                                                          \
00100        switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00101        {                                                       \
00102         case RCC_USART1CLKSOURCE_PCLK1:                        \
00103           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
00104           break;                                               \
00105         case RCC_USART1CLKSOURCE_HSI:                          \
00106           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00107           break;                                               \
00108         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00109           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00110           break;                                               \
00111         case RCC_USART1CLKSOURCE_LSE:                          \
00112           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00113           break;                                               \
00114         default:                                               \
00115           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00116           break;                                               \
00117        }                                                       \
00118     }                                                          \
00119     else if((__HANDLE__)->Instance == USART2)                  \
00120     {                                                          \
00121       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;             \
00122     }                                                          \
00123     else if((__HANDLE__)->Instance == USART3)                  \
00124     {                                                          \
00125       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;             \
00126     }                                                          \
00127     else                                                       \
00128     {                                                          \
00129       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;         \
00130     }                                                          \
00131   } while(0U)
00132 #else
00133 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00134   do {                                                         \
00135     if((__HANDLE__)->Instance == USART1)                       \
00136     {                                                          \
00137        switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00138        {                                                       \
00139         case RCC_USART1CLKSOURCE_PCLK2:                        \
00140           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \
00141           break;                                               \
00142         case RCC_USART1CLKSOURCE_HSI:                          \
00143           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00144           break;                                               \
00145         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00146           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00147           break;                                               \
00148         case RCC_USART1CLKSOURCE_LSE:                          \
00149           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00150           break;                                               \
00151         default:                                               \
00152           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00153           break;                                               \
00154        }                                                       \
00155     }                                                          \
00156     else if((__HANDLE__)->Instance == USART2)                  \
00157     {                                                          \
00158        switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00159        {                                                       \
00160         case RCC_USART2CLKSOURCE_PCLK1:                        \
00161           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
00162           break;                                               \
00163         case RCC_USART2CLKSOURCE_HSI:                          \
00164           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00165           break;                                               \
00166         case RCC_USART2CLKSOURCE_SYSCLK:                       \
00167           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00168           break;                                               \
00169         case RCC_USART2CLKSOURCE_LSE:                          \
00170           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00171           break;                                               \
00172         default:                                               \
00173           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00174           break;                                               \
00175        }                                                       \
00176     }                                                          \
00177     else if((__HANDLE__)->Instance == USART3)                  \
00178     {                                                          \
00179        switch(__HAL_RCC_GET_USART3_SOURCE())                   \
00180        {                                                       \
00181         case RCC_USART3CLKSOURCE_PCLK1:                        \
00182           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
00183           break;                                               \
00184         case RCC_USART3CLKSOURCE_HSI:                          \
00185           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00186           break;                                               \
00187         case RCC_USART3CLKSOURCE_SYSCLK:                       \
00188           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00189           break;                                               \
00190         case RCC_USART3CLKSOURCE_LSE:                          \
00191           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00192           break;                                               \
00193         default:                                               \
00194           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00195           break;                                               \
00196        }                                                       \
00197     }                                                          \
00198     else                                                       \
00199     {                                                          \
00200       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;         \
00201     }                                                          \
00202   } while(0U)
00203 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
00204
00205 /** @brief  Compute the USART mask to apply to retrieve the received data
00206   *         according to the word length and to the parity bits activation.
00207   * @note   If PCE = 1, the parity bit is not included in the data extracted
00208   *         by the reception API().
00209   *         This masking operation is not carried out in the case of
00210   *         DMA transfers.
00211   * @param  __HANDLE__ specifies the USART Handle.
00212   * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
00213   */
00214 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00215     defined(STM32F334x8)                                                 || \
00216     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00217 #define USART_MASK_COMPUTATION(__HANDLE__)                            \
00218   do {                                                                \
00219   if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)           \
00220   {                                                                   \
00221      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
00222      {                                                                \
00223         (__HANDLE__)->Mask = 0x01FFU ;                                \
00224      }                                                                \
00225      else                                                             \
00226      {                                                                \
00227         (__HANDLE__)->Mask = 0x00FFU ;                                \
00228      }                                                                \
00229   }                                                                   \
00230   else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)      \
00231   {                                                                   \
00232      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
00233      {                                                                \
00234         (__HANDLE__)->Mask = 0x00FFU ;                                \
00235      }                                                                \
00236      else                                                             \
00237      {                                                                \
00238         (__HANDLE__)->Mask = 0x007FU ;                                \
00239      }                                                                \
00240   }                                                                   \
00241   else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B)      \
00242   {                                                                   \
00243      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
00244      {                                                                \
00245         (__HANDLE__)->Mask = 0x007FU ;                                \
00246      }                                                                \
00247      else                                                             \
00248      {                                                                \
00249         (__HANDLE__)->Mask = 0x003FU ;                                \
00250      }                                                                \
00251   }                                                                   \
00252 } while(0U)
00253 #else
00254 #define USART_MASK_COMPUTATION(__HANDLE__)                            \
00255   do {                                                                \
00256   if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)           \
00257   {                                                                   \
00258      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
00259      {                                                                \
00260         (__HANDLE__)->Mask = 0x01FFU ;                                \
00261      }                                                                \
00262      else                                                             \
00263      {                                                                \
00264         (__HANDLE__)->Mask = 0x00FFU ;                                \
00265      }                                                                \
00266   }                                                                   \
00267   else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)      \
00268   {                                                                   \
00269      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
00270      {                                                                \
00271         (__HANDLE__)->Mask = 0x00FFU ;                                \
00272      }                                                                \
00273      else                                                             \
00274      {                                                                \
00275         (__HANDLE__)->Mask = 0x007FU ;                                \
00276      }                                                                \
00277   }                                                                   \
00278 } while(0U)
00279 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00280        /* STM32F334x8                               || */
00281        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00282
00283
00284 /**
00285   * @brief Ensure that USART frame length is valid.
00286   * @param __LENGTH__ USART frame length.
00287   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00288   */
00289 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
00290     defined(STM32F334x8)                                                 || \
00291     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00292 #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
00293                                           ((__LENGTH__) == USART_WORDLENGTH_8B) || \
00294                                           ((__LENGTH__) == USART_WORDLENGTH_9B))
00295 #else
00296 #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_8B) || \
00297                                           ((__LENGTH__) == USART_WORDLENGTH_9B))
00298 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
00299        /* STM32F334x8                               || */
00300        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
00301 /**
00302   * @}
00303   */
00304
00305 /* Exported functions --------------------------------------------------------*/
00306
00307 /**
00308   * @}
00309   */
00310
00311 /**
00312   * @}
00313   */
00314
00315 #ifdef __cplusplus
00316 }
00317 #endif
00318
00319 #endif /* __STM32F3xx_HAL_USART_EX_H */
00320
00321 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00322
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_wwdg.c Source File

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stm32f3xx_hal_wwdg.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_wwdg.c
00004   * @author  MCD Application Team
00005   * @brief   WWDG HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Window Watchdog (WWDG) peripheral:
00008   *           + Initialization and Configuration function
00009   *           + IO operation functions
00010   @verbatim
00011   ==============================================================================
00012                       ##### WWDG specific features #####
00013   ==============================================================================
00014   [..]
00015     Once enabled the WWDG generates a system reset on expiry of a programmed
00016     time period, unless the program refreshes the counter (T[6U;0] downcounter)
00017     before reaching 0x3F value (i.e. a reset is generated when the counter
00018     value rolls over from 0x40 to 0x3FU).
00019
00020     (+) An MCU reset is also generated if the counter value is refreshed
00021         before the counter has reached the refresh window value. This
00022         implies that the counter must be refreshed in a limited window.
00023
00024     (+) Once enabled the WWDG cannot be disabled except by a system reset.
00025
00026     (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has
00027         occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).
00028
00029     (+) The WWDG downcounter input clock is derived from the APB clock divided
00030         by a programmable prescaler.
00031
00032     (+) WWDG downcounter clock (Hz) = PCLK1 / (4096U * Prescaler)
00033
00034     (+) WWDG timeout (ms) = (1000U * (T[5U;0] + 1U)) / (WWDG downcounter clock)
00035         where T[5U;0] are the lowest 6 bits of downcounter.
00036
00037     (+) WWDG Counter refresh is allowed between the following limits :
00038         (++) min time (ms) = (1000U * (T[5U;0] - Window)) / (WWDG downcounter clock)
00039         (++) max time (ms) = (1000U * (T[5U;0] - 0x40U)) / (WWDG downcounter clock)
00040
00041     (+) Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms
00042
00043     (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
00044         operations or data logging must be performed before the actual reset is
00045         generated. When the downcounter reaches the value 0x40U, an EWI interrupt
00046         is generated and the corresponding interrupt service routine (ISR) can
00047         be used to trigger specific actions (such as communications or data
00048         logging), before resetting the device.
00049         In some applications, the EWI interrupt can be used to manage a software
00050         system check and/or system recovery/graceful degradation, without
00051         generating a WWDG reset. In this case, the corresponding interrupt
00052         service routine (ISR) should reload the WWDG counter to avoid the WWDG
00053         reset, then trigger the required actions.
00054         Note:When the EWI interrupt cannot be served, e.g. due to a system lock
00055         in a higher priority task, the WWDG reset will eventually be generated.
00056
00057     (+) Debug mode : When the microcontroller enters debug mode (core halted),
00058         the WWDG counter either continues to work normally or stops, depending
00059         on DBG_WWDG_STOP configuration bit in DBG module, accessible through
00060         __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
00061
00062                      ##### How to use this driver #####
00063   ==============================================================================
00064   [..]
00065     (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
00066
00067     (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
00068         Interrupt mode using using HAL_WWDG_Init() function.
00069         This enables WWDG peripheral and the downcounter starts downcounting
00070         from given counter value.
00071         Init function can be called again to modify all watchdog parameters,
00072         however if EWI mode has been set once, it can't be clear until next
00073         reset.
00074
00075     (+) The application program must refresh the WWDG counter at regular
00076         intervals during normal operation to prevent an MCU reset using
00077         HAL_WWDG_Refresh() function. This operation must occur only when
00078         the counter is lower than the window value already programmed.
00079
00080     (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
00081         the counter reaches 0x40. User can add his own code in weak function
00082         HAL_WWDG_EarlyWakeupCallback().
00083
00084      *** WWDG HAL driver macros list ***
00085      ==================================
00086      [..]
00087        Below the list of most used macros in WWDG HAL driver.
00088
00089       (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
00090       (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
00091       (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
00092
00093   @endverbatim
00094   ******************************************************************************
00095   * @attention
00096   *
00097   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00098   *
00099   * Redistribution and use in source and binary forms, with or without modification,
00100   * are permitted provided that the following conditions are met:
00101   *   1. Redistributions of source code must retain the above copyright notice,
00102   *      this list of conditions and the following disclaimer.
00103   *   2. Redistributions in binary form must reproduce the above copyright notice,
00104   *      this list of conditions and the following disclaimer in the documentation
00105   *      and/or other materials provided with the distribution.
00106   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00107   *      may be used to endorse or promote products derived from this software
00108   *      without specific prior written permission.
00109   *
00110   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00111   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00112   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00113   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00114   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00115   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00116   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00117   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00118   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00119   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00120   *
00121   ******************************************************************************
00122   */
00123
00124 /* Includes ------------------------------------------------------------------*/
00125 #include "stm32f3xx_hal.h"
00126
00127 /** @addtogroup STM32F3xx_HAL_Driver
00128   * @{
00129   */
00130
00131 #ifdef HAL_WWDG_MODULE_ENABLED
00132 /** @defgroup WWDG WWDG
00133   * @brief WWDG HAL module driver.
00134   * @{
00135   */
00136
00137 /* Private typedef -----------------------------------------------------------*/
00138 /* Private define ------------------------------------------------------------*/
00139 /* Private macro -------------------------------------------------------------*/
00140 /* Private variables ---------------------------------------------------------*/
00141 /* Private function prototypes -----------------------------------------------*/
00142 /* Exported functions --------------------------------------------------------*/
00143
00144 /** @defgroup WWDG_Exported_Functions WWDG Exported Functions
00145   * @{
00146   */
00147
00148 /** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
00149  *  @brief    Initialization and Configuration functions.
00150  *
00151 @verbatim
00152   ==============================================================================
00153           ##### Initialization and Configuration functions #####
00154   ==============================================================================
00155   [..]
00156     This section provides functions allowing to:
00157       (+) Initialize and start the WWDG according to the specified parameters
00158           in the WWDG_InitTypeDef of associated handle.
00159       (+) Initialize the WWDG MSP.
00160
00161 @endverbatim
00162   * @{
00163   */
00164
00165 /**
00166   * @brief  Initialize the WWDG according to the specified.
00167   *         parameters in the WWDG_InitTypeDef of  associated handle.
00168   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00169   *                the configuration information for the specified WWDG module.
00170   * @retval HAL status
00171   */
00172 HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
00173 {
00174   /* Check the WWDG handle allocation */
00175   if(hwwdg == NULL)
00176   {
00177     return HAL_ERROR;
00178   }
00179
00180   /* Check the parameters */
00181   assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
00182   assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
00183   assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
00184   assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
00185   assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
00186
00187   /* Init the low level hardware */
00188   HAL_WWDG_MspInit(hwwdg);
00189
00190   /* Set WWDG Counter */
00191   WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
00192
00193   /* Set WWDG Prescaler and Window */
00194   WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
00195
00196   /* Return function status */
00197   return HAL_OK;
00198 }
00199
00200
00201 /**
00202   * @brief  Initialize the WWDG MSP.
00203   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00204   *                the configuration information for the specified WWDG module.
00205   * @note   When rewriting this function in user file, mechanism may be added
00206   *         to avoid multiple initialize when HAL_WWDG_Init function is called
00207   *         again to change parameters.
00208   * @retval None
00209   */
00210 __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
00211 {
00212   /* Prevent unused argument(s) compilation warning */
00213   UNUSED(hwwdg);
00214
00215   /* NOTE: This function should not be modified, when the callback is needed,
00216            the HAL_WWDG_MspInit could be implemented in the user file
00217    */
00218 }
00219
00220 /**
00221   * @}
00222   */
00223
00224 /** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
00225  *  @brief    IO operation functions
00226  *
00227 @verbatim
00228   ==============================================================================
00229                       ##### IO operation functions #####
00230   ==============================================================================
00231   [..]
00232     This section provides functions allowing to:
00233     (+) Refresh the WWDG.
00234     (+) Handle WWDG interrupt request and associated function callback.
00235
00236 @endverbatim
00237   * @{
00238   */
00239
00240 /**
00241   * @brief  Refresh the WWDG.
00242   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00243   *                the configuration information for the specified WWDG module.
00244   * @retval HAL status
00245   */
00246 HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
00247 {
00248   /* Write to WWDG CR the WWDG Counter value to refresh with */
00249   WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
00250
00251   /* Return function status */
00252   return HAL_OK;
00253 }
00254
00255 /**
00256   * @brief  Handle WWDG interrupt request.
00257   * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
00258   *         or data logging must be performed before the actual reset is generated.
00259   *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with
00260   *         EWIMode set to WWDG_EWI_ENABLE.
00261   *         When the downcounter reaches the value 0x40, and EWI interrupt is
00262   *         generated and the corresponding Interrupt Service Routine (ISR) can
00263   *         be used to trigger specific actions (such as communications or data
00264   *         logging), before resetting the device.
00265   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00266   *                the configuration information for the specified WWDG module.
00267   * @retval None
00268   */
00269 void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
00270 {
00271   /* Check if Early Wakeup Interrupt is enable */
00272   if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
00273   {
00274     /* Check if WWDG Early Wakeup Interrupt occurred */
00275     if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
00276     {
00277       /* Clear the WWDG Early Wakeup flag */
00278       __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
00279
00280       /* Early Wakeup callback */
00281       HAL_WWDG_EarlyWakeupCallback(hwwdg);
00282     }
00283   }
00284 }
00285
00286 /**
00287   * @brief  WWDG Early Wakeup callback.
00288   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00289   *                the configuration information for the specified WWDG module.
00290   * @retval None
00291   */
00292 __weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
00293 {
00294   /* Prevent unused argument(s) compilation warning */
00295   UNUSED(hwwdg);
00296
00297   /* NOTE: This function should not be modified, when the callback is needed,
00298            the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
00299    */
00300 }
00301
00302 /**
00303   * @}
00304   */
00305
00306 /**
00307   * @}
00308   */
00309
00310 #endif /* HAL_WWDG_MODULE_ENABLED */
00311 /**
00312   * @}
00313   */
00314
00315 /**
00316   * @}
00317   */
00318
00319 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_hal_wwdg.h Source File

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stm32f3xx_hal_wwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_hal_wwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of WWDG HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_HAL_WWDG_H
00038 #define __STM32F3xx_HAL_WWDG_H
00039
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx_hal_def.h"
00046
00047 /** @addtogroup STM32F3xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup WWDG
00052   * @{
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056
00057 /** @defgroup WWDG_Exported_Types WWDG Exported Types
00058   * @{
00059   */
00060
00061 /**
00062   * @brief  WWDG Init structure definition
00063   */
00064 typedef struct
00065 {
00066   uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.
00067                                This parameter can be a value of @ref WWDG_Prescaler */
00068
00069   uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.
00070                                This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7FU */
00071
00072   uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.
00073                                This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7FU */
00074
00075   uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
00076                                This parameter can be a value of @ref WWDG_EWI_Mode */
00077
00078 }WWDG_InitTypeDef;
00079
00080 /**
00081   * @brief  WWDG handle Structure definition
00082   */
00083 typedef struct
00084 {
00085   WWDG_TypeDef                 *Instance;  /*!< Register base address    */
00086
00087   WWDG_InitTypeDef             Init;       /*!< WWDG required parameters */
00088
00089 }WWDG_HandleTypeDef;
00090 /**
00091   * @}
00092   */
00093
00094 /* Exported constants --------------------------------------------------------*/
00095
00096 /** @defgroup WWDG_Exported_Constants WWDG Exported Constants
00097   * @{
00098   */
00099
00100 /** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
00101   * @{
00102   */
00103 #define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */
00104 /**
00105   * @}
00106   */
00107
00108 /** @defgroup WWDG_Flag_definition WWDG Flag definition
00109   * @brief WWDG Flag definition
00110   * @{
00111   */
00112 #define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
00113 /**
00114   * @}
00115   */
00116
00117 /** @defgroup WWDG_Prescaler WWDG Prescaler
00118   * @{
00119   */
00120 #define WWDG_PRESCALER_1                    0x00000000u       /*!< WWDG counter clock = (PCLK1/4096U)/1U */
00121 #define WWDG_PRESCALER_2                    WWDG_CFR_WDGTB_0  /*!< WWDG counter clock = (PCLK1/4096U)/2U */
00122 #define WWDG_PRESCALER_4                    WWDG_CFR_WDGTB_1  /*!< WWDG counter clock = (PCLK1/4096U)/4U */
00123 #define WWDG_PRESCALER_8                    WWDG_CFR_WDGTB    /*!< WWDG counter clock = (PCLK1/4096U)/8U */
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
00129   * @{
00130   */
00131 #define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */
00132 #define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */
00133 /**
00134   * @}
00135   */
00136
00137 /**
00138   * @}
00139   */
00140
00141 /* Private macros ------------------------------------------------------------*/
00142
00143 /** @defgroup WWDG_Private_Macros WWDG Private Macros
00144   * @{
00145   */
00146 #define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1) || \
00147                                              ((__PRESCALER__) == WWDG_PRESCALER_2) || \
00148                                              ((__PRESCALER__) == WWDG_PRESCALER_4) || \
00149                                              ((__PRESCALER__) == WWDG_PRESCALER_8))
00150
00151 #define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
00152
00153 #define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
00154
00155 #define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \
00156                                              ((__MODE__) == WWDG_EWI_DISABLE))
00157 /**
00158   * @}
00159   */
00160
00161
00162 /* Exported macros ------------------------------------------------------------*/
00163
00164 /** @defgroup WWDG_Exported_Macros WWDG Exported Macros
00165   * @{
00166   */
00167
00168 /**
00169   * @brief  Enable the WWDG peripheral.
00170   * @param  __HANDLE__  WWDG handle
00171   * @retval None
00172   */
00173 #define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
00174
00175 /**
00176   * @brief  Enable the WWDG early wakeup interrupt.
00177   * @param  __HANDLE__ WWDG handle
00178   * @param  __INTERRUPT__  specifies the interrupt to enable.
00179   *         This parameter can be one of the following values:
00180   *            @arg WWDG_IT_EWI: Early wakeup interrupt
00181   * @note   Once enabled this interrupt cannot be disabled except by a system reset.
00182   * @retval None
00183   */
00184 #define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
00185
00186 /**
00187   * @brief  Check whether the selected WWDG interrupt has occurred or not.
00188   * @param  __HANDLE__  WWDG handle
00189   * @param  __INTERRUPT__  specifies the it to check.
00190   *        This parameter can be one of the following values:
00191   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
00192   * @retval The new state of WWDG_FLAG (SET or RESET).
00193   */
00194 #define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
00195
00196 /** @brief  Clear the WWDG interrupt pending bits.
00197   *         bits to clear the selected interrupt pending bits.
00198   * @param  __HANDLE__  WWDG handle
00199   * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
00200   *         This parameter can be one of the following values:
00201   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00202   */
00203 #define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
00204
00205 /**
00206   * @brief  Check whether the specified WWDG flag is set or not.
00207   * @param  __HANDLE__  WWDG handle
00208   * @param  __FLAG__  specifies the flag to check.
00209   *         This parameter can be one of the following values:
00210   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00211   * @retval The new state of WWDG_FLAG (SET or RESET).
00212   */
00213 #define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00214
00215 /**
00216   * @brief  Clear the WWDG's pending flags.
00217   * @param  __HANDLE__  WWDG handle
00218   * @param  __FLAG__  specifies the flag to clear.
00219   *         This parameter can be one of the following values:
00220   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00221   * @retval None
00222   */
00223 #define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))
00224
00225 /** @brief  Check whether the specified WWDG interrupt source is enabled or not.
00226   * @param  __HANDLE__  WWDG Handle.
00227   * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.
00228   *         This parameter can be one of the following values:
00229   *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
00230   * @retval state of __INTERRUPT__ (TRUE or FALSE).
00231   */
00232 #define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
00233
00234 /**
00235   * @}
00236   */
00237
00238 /* Exported functions --------------------------------------------------------*/
00239
00240 /** @addtogroup WWDG_Exported_Functions
00241   * @{
00242   */
00243
00244 /** @addtogroup WWDG_Exported_Functions_Group1
00245   * @{
00246   */
00247 /* Initialization/de-initialization functions  **********************************/
00248 HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
00249 void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
00250 /**
00251   * @}
00252   */
00253
00254 /** @addtogroup WWDG_Exported_Functions_Group2
00255   * @{
00256   */
00257 /* I/O operation functions ******************************************************/
00258 HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
00259 void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
00260 void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
00261 /**
00262   * @}
00263   */
00264
00265 /**
00266   * @}
00267   */
00268
00269 /**
00270   * @}
00271   */
00272
00273 /**
00274   * @}
00275   */
00276
00277 #ifdef __cplusplus
00278 }
00279 #endif
00280
00281 #endif /* __STM32F3xx_HAL_WWDG_H */
00282
00283 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_adc.c Source File

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stm32f3xx_ll_adc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_adc.c
00004   * @author  MCD Application Team
00005   * @brief   ADC LL module driver
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 #if defined(USE_FULL_LL_DRIVER)
00036
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f3xx_ll_adc.h"
00039 #include "stm32f3xx_ll_bus.h"
00040
00041 #ifdef  USE_FULL_ASSERT
00042   #include "stm32_assert.h"
00043 #else
00044   #define assert_param(expr) ((void)0U)
00045 #endif
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 /* Note: Devices of STM32F3 serie embed 1 out of 2 different ADC IP.   b      */
00052 /*       - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x:  */
00053 /*         ADC IP 5Msamples/sec, from 1 to 4 ADC instances and other specific */
00054 /*         features (refer to reference manual).                              */
00055 /*       - STM32F37x:                                                         */
00056 /*         ADC IP 1Msamples/sec, 1 ADC instance                               */
00057 /*       This file contains the drivers of these ADC IP, located in 2 area    */
00058 /*       delimited by compilation switches.                                   */
00059
00060 #if defined(ADC5_V1_1)
00061
00062 #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4)
00063
00064 /** @addtogroup ADC_LL ADC
00065   * @{
00066   */
00067
00068 /* Private types -------------------------------------------------------------*/
00069 /* Private variables ---------------------------------------------------------*/
00070 /* Private constants ---------------------------------------------------------*/
00071 /** @addtogroup ADC_LL_Private_Constants
00072   * @{
00073   */
00074
00075 /* Definitions of ADC hardware constraints delays */
00076 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */
00077 /*       not timeout values:                                                  */
00078 /*       Timeout values for ADC operations are dependent to device clock      */
00079 /*       configuration (system clock versus ADC clock),                       */
00080 /*       and therefore must be defined in user application.                   */
00081 /*       Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout     */
00082 /*       values definition.                                                   */
00083 /* Note: ADC timeout values are defined here in CPU cycles to be independent  */
00084 /*       of device clock setting.                                             */
00085 /*       In user application, ADC timeout values should be defined with       */
00086 /*       temporal values, in function of device clock settings.               */
00087 /*       Highest ratio CPU clock frequency vs ADC clock frequency:            */
00088 /*        - ADC clock from synchronous clock with AHB prescaler 512,          */
00089 /*          APB prescaler 16, ADC prescaler 4.                                */
00090 /*        - ADC clock from asynchronous clock (PLL) with prescaler 1,         */
00091 /*          with highest ratio CPU clock frequency vs HSI clock frequency:    */
00092 /*          CPU clock frequency max 72MHz, PLL frequency 72MHz: ratio 1.      */
00093 /* Unit: CPU cycles.                                                          */
00094 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST          ((uint32_t) 512U * 16U * 4U)
00095 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES          (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
00096 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES  (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
00097
00098 /**
00099   * @}
00100   */
00101
00102 /* Private macros ------------------------------------------------------------*/
00103
00104 /** @addtogroup ADC_LL_Private_Macros
00105   * @{
00106   */
00107
00108 /* Check of parameters for configuration of ADC hierarchical scope:           */
00109 /* common to several ADC instances.                                           */
00110 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__)                                      \
00111   (   ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                             \
00112    || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
00113    || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                             \
00114    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                 \
00115   )
00116
00117 /* Check of parameters for configuration of ADC hierarchical scope:           */
00118 /* ADC instance.                                                              */
00119 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__)                                   \
00120   (   ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                              \
00121    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
00122    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
00123    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \
00124   )
00125
00126 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)                                   \
00127   (   ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                            \
00128    || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
00129   )
00130
00131 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__)                                     \
00132   (   ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                 \
00133    || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
00134   )
00135
00136 /* Check of parameters for configuration of ADC hierarchical scope:           */
00137 /* ADC group regular                                                          */
00138 #if defined(STM32F303xE) || defined(STM32F398xx)
00139 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
00140   ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))              \
00141     ? (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                  \
00142        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12)        \
00143        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12)        \
00144        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)              \
00145        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12)        \
00146        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12)       \
00147        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12)        \
00148        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12)     \
00149        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12)       \
00150        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)            \
00151        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)             \
00152        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)            \
00153        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12)       \
00154        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)             \
00155        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12)       \
00156        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)            \
00157        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12)        \
00158        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12)      \
00159        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12)     \
00160        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12)       \
00161        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12)       \
00162        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12)       \
00163       )                                                                        \
00164       :                                                                        \
00165       (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                  \
00166        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34)        \
00167        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34)        \
00168        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)              \
00169        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34)        \
00170        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34)      \
00171        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34)      \
00172        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34)        \
00173        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34)      \
00174        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)            \
00175        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)             \
00176        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)            \
00177        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34)      \
00178        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)             \
00179        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34)       \
00180        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)            \
00181        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34)        \
00182        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC34)      \
00183        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34)     \
00184        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34)       \
00185       )                                                                        \
00186   )
00187 #elif defined(STM32F303xC) || defined(STM32F358xx)
00188 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
00189   ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))              \
00190     ? (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                  \
00191        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12)        \
00192        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12)        \
00193        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)              \
00194        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12)        \
00195        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12)       \
00196        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12)        \
00197        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12)     \
00198        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12)       \
00199        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)            \
00200        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)             \
00201        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)            \
00202        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12)       \
00203        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)             \
00204        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12)       \
00205        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)            \
00206        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12)        \
00207       )                                                                        \
00208       :                                                                        \
00209       (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                  \
00210        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34)        \
00211        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34)        \
00212        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)              \
00213        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34)        \
00214        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34)      \
00215        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34)      \
00216        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34)        \
00217        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34)      \
00218        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)            \
00219        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)             \
00220        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)            \
00221        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34)      \
00222        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)             \
00223        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34)       \
00224        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)            \
00225        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34)        \
00226       )                                                                        \
00227   )
00228 #elif defined(STM32F303x8) || defined(STM32F328xx)
00229 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
00230   (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
00231    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
00232    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
00233    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
00234    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
00235    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
00236    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)                  \
00237    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
00238    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
00239    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
00240    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
00241    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
00242    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
00243    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
00244    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
00245    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)                  \
00246   )
00247 #elif defined(STM32F334x8)
00248 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
00249   (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
00250    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
00251    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
00252    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
00253    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
00254    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
00255    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
00256    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)                \
00257    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)                \
00258    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
00259    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
00260    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
00261    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
00262    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
00263    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)                  \
00264   )
00265 #elif defined(STM32F302xC) || defined(STM32F302xE)
00266 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
00267   (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
00268    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
00269    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
00270    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
00271    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
00272    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
00273    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)                  \
00274    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
00275    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
00276    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
00277    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
00278    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
00279    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
00280    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
00281    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)                  \
00282   )
00283 #elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00284 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
00285   (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
00286    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
00287    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
00288    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
00289    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
00290    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
00291    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
00292    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
00293    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
00294    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
00295   )
00296 #endif
00297
00298 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \
00299   (   ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                    \
00300    || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
00301   )
00302
00303 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)                       \
00304   (   ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                 \
00305    || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)              \
00306    || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
00307   )
00308
00309 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)             \
00310   (   ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)           \
00311    || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
00312   )
00313
00314 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)                 \
00315   (   ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)               \
00316    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
00317    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
00318    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
00319    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
00320    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
00321    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
00322    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
00323    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
00324    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
00325    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
00326    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
00327    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
00328    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
00329    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
00330    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS)        \
00331   )
00332
00333 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \
00334   (   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \
00335    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
00336    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
00337    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
00338    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \
00339    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \
00340    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \
00341    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \
00342    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS)            \
00343   )
00344
00345 /* Check of parameters for configuration of ADC hierarchical scope:           */
00346 /* ADC group injected                                                         */
00347 #if defined(STM32F303xE) || defined(STM32F398xx)
00348 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
00349   ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))              \
00350     ? (   ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                  \
00351        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)             \
00352        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)              \
00353        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12)       \
00354        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12)        \
00355        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12)        \
00356        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12)       \
00357        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12)     \
00358        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12)        \
00359        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)            \
00360        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)             \
00361        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)            \
00362        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12)        \
00363        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)             \
00364        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12)        \
00365        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12)       \
00366        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)            \
00367        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12)      \
00368        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12)     \
00369        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12)       \
00370       )                                                                        \
00371       :                                                                        \
00372       (   ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                  \
00373        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)             \
00374        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)              \
00375        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34)        \
00376        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34)        \
00377        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34)       \
00378        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34)        \
00379        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34)      \
00380        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)            \
00381        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)             \
00382        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)            \
00383        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34)        \
00384        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)             \
00385        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34)      \
00386        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34)       \
00387        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)            \
00388        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34)       \
00389        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34)      \
00390        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2)             \
00391       )                                                                        \
00392   )
00393 #elif defined(STM32F303xC) || defined(STM32F358xx)
00394 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
00395   ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))              \
00396     ? (   ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                  \
00397        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)             \
00398        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)              \
00399        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12)       \
00400        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12)        \
00401        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12)        \
00402        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12)       \
00403        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12)     \
00404        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12)        \
00405        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)            \
00406        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)             \
00407        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)            \
00408        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12)        \
00409        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)             \
00410        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12)        \
00411        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12)       \
00412        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)            \
00413       )                                                                        \
00414       :                                                                        \
00415       (   ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                  \
00416        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)             \
00417        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)              \
00418        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34)        \
00419        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34)        \
00420        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34)       \
00421        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34)        \
00422        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34)      \
00423        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)            \
00424        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)             \
00425        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)            \
00426        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34)        \
00427        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)             \
00428        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34)      \
00429        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34)       \
00430        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)            \
00431       )                                                                        \
00432   )
00433
00434 #elif defined(STM32F303x8) || defined(STM32F328xx)
00435 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)                         \
00436   (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
00437    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
00438    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
00439    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
00440    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
00441    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
00442    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
00443    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
00444    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
00445    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
00446    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
00447    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
00448    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)                  \
00449    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
00450    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)                  \
00451    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
00452    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
00453   )
00454 #elif defined(STM32F334x8)
00455 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)                         \
00456   (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
00457    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
00458    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
00459    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
00460    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
00461    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
00462    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
00463    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
00464    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)                \
00465    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)                \
00466    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)                  \
00467    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
00468    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)                  \
00469    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
00470    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
00471   )
00472 #elif defined(STM32F302xC) || defined(STM32F302xE)
00473 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)                         \
00474   (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
00475    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
00476    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
00477    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
00478    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
00479    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
00480    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
00481    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
00482    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
00483    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)                  \
00484    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
00485    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)                  \
00486    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
00487    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
00488   )
00489 #elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00490 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)                         \
00491   (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
00492    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
00493    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
00494    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
00495    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
00496    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
00497    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
00498   )
00499 #endif
00500
00501 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)                     \
00502   (   ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                  \
00503    || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING)                 \
00504    || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING)           \
00505   )
00506
00507 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)                             \
00508   (   ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                     \
00509    || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \
00510   )
00511
00512 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)                 \
00513   (   ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)               \
00514    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
00515    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
00516    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
00517   )
00518
00519 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)          \
00520   (   ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)           \
00521    || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \
00522   )
00523
00524 #if defined(ADC_MULTIMODE_SUPPORT)
00525 /* Check of parameters for configuration of ADC hierarchical scope:           */
00526 /* multimode.                                                                 */
00527 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)                                   \
00528   (   ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT)                           \
00529    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT)                       \
00530    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL)                       \
00531    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT)                       \
00532    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN)                       \
00533    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)                  \
00534    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)                  \
00535    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)                  \
00536   )
00537
00538 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__)                   \
00539   (   ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC)              \
00540    || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B)       \
00541    || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B)         \
00542    || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B)       \
00543    || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B)         \
00544   )
00545
00546 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__)                   \
00547   (   ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)           \
00548    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)          \
00549    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)          \
00550    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)          \
00551    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)          \
00552    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)          \
00553    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)          \
00554    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)          \
00555    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)          \
00556    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)         \
00557    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)         \
00558    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)         \
00559   )
00560
00561 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)                   \
00562   (   ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER)                        \
00563    || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE)                         \
00564    || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE)                  \
00565   )
00566
00567 #endif /* ADC_MULTIMODE_SUPPORT */
00568 /**
00569   * @}
00570   */
00571
00572
00573 /* Private function prototypes -----------------------------------------------*/
00574
00575 /* Exported functions --------------------------------------------------------*/
00576 /** @addtogroup ADC_LL_Exported_Functions
00577   * @{
00578   */
00579
00580 /** @addtogroup ADC_LL_EF_Init
00581   * @{
00582   */
00583
00584 /**
00585   * @brief  De-initialize registers of all ADC instances belonging to
00586   *         the same ADC common instance to their default reset values.
00587   * @note   This function is performing a hard reset, using high level
00588   *         clock source RCC ADC reset.
00589   *         Caution: On this STM32 serie, if several ADC instances are available
00590   *         on the selected device, RCC ADC reset will reset
00591   *         all ADC instances belonging to the common ADC instance.
00592   *         To de-initialize only 1 ADC instance, use
00593   *         function @ref LL_ADC_DeInit().
00594   * @param  ADCxy_COMMON ADC common instance
00595   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
00596   * @retval An ErrorStatus enumeration value:
00597   *          - SUCCESS: ADC common registers are de-initialized
00598   *          - ERROR: not applicable
00599   */
00600 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
00601 {
00602   /* Check the parameters */
00603   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
00604
00605   /* Force reset of ADC clock (core clock) */
00606   #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
00607   if(ADCxy_COMMON == ADC12_COMMON)
00608   {
00609     LL_AHB1_GRP1_ForceReset  (LL_AHB1_GRP1_PERIPH_ADC12);
00610   }
00611   else
00612   {
00613     LL_AHB1_GRP1_ForceReset  (LL_AHB1_GRP1_PERIPH_ADC34);
00614   }
00615   #elif defined(ADC1) && defined(ADC2)
00616   LL_AHB1_GRP1_ForceReset  (LL_AHB1_GRP1_PERIPH_ADC12);
00617   #elif defined(ADC1)
00618   LL_AHB1_GRP1_ForceReset  (LL_AHB1_GRP1_PERIPH_ADC1);
00619   #endif
00620
00621   /* Release reset of ADC clock (core clock) */
00622   #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
00623   if(ADCxy_COMMON == ADC12_COMMON)
00624   {
00625     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
00626   }
00627   else
00628   {
00629     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC34);
00630   }
00631   #elif defined(ADC1) && defined(ADC2)
00632   LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
00633   #elif defined(ADC1)
00634   LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC1);
00635   #endif
00636
00637   return SUCCESS;
00638 }
00639
00640 /**
00641   * @brief  Initialize some features of ADC common parameters
00642   *         (all ADC instances belonging to the same ADC common instance)
00643   *         and multimode (for devices with several ADC instances available).
00644   * @note   The setting of ADC common parameters is conditioned to
00645   *         ADC instances state:
00646   *         All ADC instances belonging to the same ADC common instance
00647   *         must be disabled.
00648   * @param  ADCxy_COMMON ADC common instance
00649   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
00650   * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
00651   * @retval An ErrorStatus enumeration value:
00652   *          - SUCCESS: ADC common registers are initialized
00653   *          - ERROR: ADC common registers are not initialized
00654   */
00655 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
00656 {
00657   ErrorStatus status = SUCCESS;
00658
00659   /* Check the parameters */
00660   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
00661   assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
00662
00663 #if defined(ADC_MULTIMODE_SUPPORT)
00664   assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
00665   if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
00666   {
00667     assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
00668     assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
00669   }
00670 #endif /* ADC_MULTIMODE_SUPPORT */
00671
00672   /* Note: Hardware constraint (refer to description of functions             */
00673   /*       "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"):               */
00674   /*       On this STM32 serie, setting of these features is conditioned to   */
00675   /*       ADC state:                                                         */
00676   /*       All ADC instances of the ADC common group must be disabled.        */
00677   if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
00678   {
00679     /* Configuration of ADC hierarchical scope:                               */
00680     /*  - common to several ADC                                               */
00681     /*    (all ADC instances belonging to the same ADC common instance)       */
00682     /*    - Set ADC clock (conversion clock)                                  */
00683     /*  - multimode (if several ADC instances available on the                */
00684     /*    selected device)                                                    */
00685     /*    - Set ADC multimode configuration                                   */
00686     /*    - Set ADC multimode DMA transfer                                    */
00687     /*    - Set ADC multimode: delay between 2 sampling phases                */
00688 #if defined(ADC_MULTIMODE_SUPPORT)
00689     if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
00690     {
00691       MODIFY_REG(ADCxy_COMMON->CCR,
00692                    ADC_CCR_CKMODE
00693                  | ADC_CCR_DUAL
00694                  | ADC_CCR_MDMA
00695                  | ADC_CCR_DELAY
00696                 ,
00697                    ADC_CommonInitStruct->CommonClock
00698                  | ADC_CommonInitStruct->Multimode
00699                  | ADC_CommonInitStruct->MultiDMATransfer
00700                  | ADC_CommonInitStruct->MultiTwoSamplingDelay
00701                 );
00702     }
00703     else
00704     {
00705       MODIFY_REG(ADCxy_COMMON->CCR,
00706                    ADC_CCR_CKMODE
00707                  | ADC_CCR_DUAL
00708                  | ADC_CCR_MDMA
00709                  | ADC_CCR_DELAY
00710                 ,
00711                    ADC_CommonInitStruct->CommonClock
00712                  | LL_ADC_MULTI_INDEPENDENT
00713                 );
00714     }
00715 #else
00716     LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
00717 #endif
00718   }
00719   else
00720   {
00721     /* Initialization error: One or several ADC instances belonging to        */
00722     /* the same ADC common instance are not disabled.                         */
00723     status = ERROR;
00724   }
00725
00726   return status;
00727 }
00728
00729 /**
00730   * @brief  Set each @ref LL_ADC_CommonInitTypeDef field to default value.
00731   * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
00732   *                              whose fields will be set to default values.
00733   * @retval None
00734   */
00735 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
00736 {
00737   /* Set ADC_CommonInitStruct fields to default values */
00738   /* Set fields of ADC common */
00739   /* (all ADC instances belonging to the same ADC common instance) */
00740   ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
00741
00742 #if defined(ADC_MULTIMODE_SUPPORT)
00743   /* Set fields of ADC multimode */
00744   ADC_CommonInitStruct->Multimode             = LL_ADC_MULTI_INDEPENDENT;
00745   ADC_CommonInitStruct->MultiDMATransfer      = LL_ADC_MULTI_REG_DMA_EACH_ADC;
00746   ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
00747 #endif /* ADC_MULTIMODE_SUPPORT */
00748 }
00749
00750 /**
00751   * @brief  De-initialize registers of the selected ADC instance
00752   *         to their default reset values.
00753   * @note   To reset all ADC instances quickly (perform a hard reset),
00754   *         use function @ref LL_ADC_CommonDeInit().
00755   * @note   If this functions returns error status, it means that ADC instance
00756   *         is in an unknown state.
00757   *         In this case, perform a hard reset using high level
00758   *         clock source RCC ADC reset.
00759   *         Caution: On this STM32 serie, if several ADC instances are available
00760   *         on the selected device, RCC ADC reset will reset
00761   *         all ADC instances belonging to the common ADC instance.
00762   *         Refer to function @ref LL_ADC_CommonDeInit().
00763   * @param  ADCx ADC instance
00764   * @retval An ErrorStatus enumeration value:
00765   *          - SUCCESS: ADC registers are de-initialized
00766   *          - ERROR: ADC registers are not de-initialized
00767   */
00768 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
00769 {
00770   ErrorStatus status = SUCCESS;
00771
00772   __IO uint32_t timeout_cpu_cycles = 0U;
00773
00774   /* Check the parameters */
00775   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00776
00777   /* Disable ADC instance if not already disabled.                            */
00778   if(LL_ADC_IsEnabled(ADCx) == 1U)
00779   {
00780     /* Set ADC group regular trigger source to SW start to ensure to not      */
00781     /* have an external trigger event occurring during the conversion stop    */
00782     /* ADC disable process.                                                   */
00783     LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
00784
00785     /* Stop potential ADC conversion on going on ADC group regular.           */
00786     if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
00787     {
00788       if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
00789       {
00790         LL_ADC_REG_StopConversion(ADCx);
00791       }
00792     }
00793
00794     /* Set ADC group injected trigger source to SW start to ensure to not     */
00795     /* have an external trigger event occurring during the conversion stop    */
00796     /* ADC disable process.                                                   */
00797     LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
00798
00799     /* Stop potential ADC conversion on going on ADC group injected.          */
00800     if(LL_ADC_INJ_IsConversionOngoing(ADCx) != 0U)
00801     {
00802       if(LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0U)
00803       {
00804         LL_ADC_INJ_StopConversion(ADCx);
00805       }
00806     }
00807
00808     /* Wait for ADC conversions are effectively stopped                       */
00809     timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
00810     while ((  LL_ADC_REG_IsStopConversionOngoing(ADCx)
00811             | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1U)
00812     {
00813       if(timeout_cpu_cycles-- == 0U)
00814       {
00815         /* Time-out error */
00816         status = ERROR;
00817       }
00818     }
00819
00820     /* Flush group injected contexts queue (register JSQR):                   */
00821     /* Note: Bit JQM must be set to empty the contexts queue (otherwise       */
00822     /*       contexts queue is maintained with the last active context).      */
00823     LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
00824
00825     /* Disable the ADC instance */
00826     LL_ADC_Disable(ADCx);
00827
00828     /* Wait for ADC instance is effectively disabled */
00829     timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
00830     while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
00831     {
00832       if(timeout_cpu_cycles-- == 0U)
00833       {
00834         /* Time-out error */
00835         status = ERROR;
00836       }
00837     }
00838   }
00839
00840   /* Check whether ADC state is compliant with expected state */
00841   if(READ_BIT(ADCx->CR,
00842               (  ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
00843                | ADC_CR_ADDIS | ADC_CR_ADEN                                     )
00844              )
00845      == 0U)
00846   {
00847     /* ========== Reset ADC registers ========== */
00848     /* Reset register IER */
00849     CLEAR_BIT(ADCx->IER,
00850               (  LL_ADC_IT_ADRDY
00851                | LL_ADC_IT_EOC
00852                | LL_ADC_IT_EOS
00853                | LL_ADC_IT_OVR
00854                | LL_ADC_IT_EOSMP
00855                | LL_ADC_IT_JEOC
00856                | LL_ADC_IT_JEOS
00857                | LL_ADC_IT_JQOVF
00858                | LL_ADC_IT_AWD1
00859                | LL_ADC_IT_AWD2
00860                | LL_ADC_IT_AWD3 )
00861              );
00862
00863     /* Reset register ISR */
00864     SET_BIT(ADCx->ISR,
00865             (  LL_ADC_FLAG_ADRDY
00866              | LL_ADC_FLAG_EOC
00867              | LL_ADC_FLAG_EOS
00868              | LL_ADC_FLAG_OVR
00869              | LL_ADC_FLAG_EOSMP
00870              | LL_ADC_FLAG_JEOC
00871              | LL_ADC_FLAG_JEOS
00872              | LL_ADC_FLAG_JQOVF
00873              | LL_ADC_FLAG_AWD1
00874              | LL_ADC_FLAG_AWD2
00875              | LL_ADC_FLAG_AWD3 )
00876            );
00877
00878     /* Reset register CR */
00879     /*  - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,  */
00880     /*    ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in                      */
00881     /*    access mode "read-set": no direct reset applicable.                 */
00882     /*  - Reset Calibration mode to default setting (single ended).           */
00883     /*  - Disable ADC internal voltage regulator.                             */
00884     /*    Note: ADC internal voltage regulator disable is conditioned to      */
00885     /*          ADC state disabled: already done above.                       */
00886     /* Sequence to disable voltage regulator:                                 */
00887     /* 1. Set the intermediate state before moving the ADC voltage regulator  */
00888     /*    to disable state.                                                   */
00889     CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0 | ADC_CR_ADCALDIF);
00890     /* 2. Set ADVREGEN bits to 0x10 */
00891     SET_BIT(ADCx->CR, ADC_CR_ADVREGEN_1);
00892
00893     /* Reset register CFGR */
00894     CLEAR_BIT(ADCx->CFGR,
00895               (  ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN
00896                | ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
00897                | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
00898                | ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD
00899                | ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN
00900                | ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN  )
00901              );
00902
00903     /* Reset register SMPR1 */
00904     CLEAR_BIT(ADCx->SMPR1,
00905               (  ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
00906                | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
00907                | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
00908              );
00909
00910     /* Reset register SMPR2 */
00911     CLEAR_BIT(ADCx->SMPR2,
00912               (  ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
00913                | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
00914                | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
00915              );
00916
00917     /* Reset register TR1 */
00918     MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
00919
00920     /* Reset register TR2 */
00921     MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
00922
00923     /* Reset register TR3 */
00924     MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
00925
00926     /* Reset register SQR1 */
00927     CLEAR_BIT(ADCx->SQR1,
00928               (  ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
00929                | ADC_SQR1_SQ1 | ADC_SQR1_L)
00930              );
00931
00932     /* Reset register SQR2 */
00933     CLEAR_BIT(ADCx->SQR2,
00934               (  ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
00935                | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
00936              );
00937
00938     /* Reset register SQR3 */
00939     CLEAR_BIT(ADCx->SQR3,
00940               (  ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
00941                | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
00942              );
00943
00944     /* Reset register SQR4 */
00945     CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
00946
00947     /* Reset register JSQR */
00948     CLEAR_BIT(ADCx->JSQR,
00949               (  ADC_JSQR_JL
00950                | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
00951                | ADC_JSQR_JSQ4    | ADC_JSQR_JSQ3
00952                | ADC_JSQR_JSQ2    | ADC_JSQR_JSQ1  )
00953              );
00954
00955     /* Flush ADC group injected contexts queue */
00956     SET_BIT(ADCx->CFGR, ADC_CFGR_JQM);
00957     CLEAR_BIT(ADCx->CFGR, ADC_CFGR_JQM);
00958     /* Reset register ISR bit JQOVF (set by previous operation on JSQR) */
00959     SET_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF);
00960
00961     /* Reset register DR */
00962     /* Note: bits in access mode read only, no direct reset applicable */
00963
00964     /* Reset register OFR1 */
00965     CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
00966     /* Reset register OFR2 */
00967     CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
00968     /* Reset register OFR3 */
00969     CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
00970     /* Reset register OFR4 */
00971     CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
00972
00973     /* Reset registers JDR1, JDR2, JDR3, JDR4 */
00974     /* Note: bits in access mode read only, no direct reset applicable */
00975
00976     /* Reset register AWD2CR */
00977     CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
00978
00979     /* Reset register AWD3CR */
00980     CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
00981
00982     /* Reset register DIFSEL */
00983     CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
00984
00985     /* Reset register CALFACT */
00986     CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
00987   }
00988   else
00989   {
00990     /* ADC instance is in an unknown state */
00991     /* Need to performing a hard reset of ADC instance, using high level      */
00992     /* clock source RCC ADC reset.                                            */
00993     /* Caution: On this STM32 serie, if several ADC instances are available   */
00994     /*          on the selected device, RCC ADC reset will reset              */
00995     /*          all ADC instances belonging to the common ADC instance.       */
00996     /* Caution: On this STM32 serie, if several ADC instances are available   */
00997     /*          on the selected device, RCC ADC reset will reset              */
00998     /*          all ADC instances belonging to the common ADC instance.       */
00999     status = ERROR;
01000   }
01001
01002   return status;
01003 }
01004
01005 /**
01006   * @brief  Initialize some features of ADC instance.
01007   * @note   These parameters have an impact on ADC scope: ADC instance.
01008   *         Affects both group regular and group injected (availability
01009   *         of ADC group injected depends on STM32 families).
01010   *         Refer to corresponding unitary functions into
01011   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
01012   * @note   The setting of these parameters by function @ref LL_ADC_Init()
01013   *         is conditioned to ADC state:
01014   *         ADC instance must be disabled.
01015   *         This condition is applied to all ADC features, for efficiency
01016   *         and compatibility over all STM32 families. However, the different
01017   *         features can be set under different ADC state conditions
01018   *         (setting possible with ADC enabled without conversion on going,
01019   *         ADC enabled with conversion on going, ...)
01020   *         Each feature can be updated afterwards with a unitary function
01021   *         and potentially with ADC in a different state than disabled,
01022   *         refer to description of each function for setting
01023   *         conditioned to ADC state.
01024   * @note   After using this function, some other features must be configured
01025   *         using LL unitary functions.
01026   *         The minimum configuration remaining to be done is:
01027   *          - Set ADC group regular or group injected sequencer:
01028   *            map channel on the selected sequencer rank.
01029   *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
01030   *          - Set ADC channel sampling time
01031   *            Refer to function LL_ADC_SetChannelSamplingTime();
01032   * @param  ADCx ADC instance
01033   * @param  ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
01034   * @retval An ErrorStatus enumeration value:
01035   *          - SUCCESS: ADC registers are initialized
01036   *          - ERROR: ADC registers are not initialized
01037   */
01038 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
01039 {
01040   ErrorStatus status = SUCCESS;
01041
01042   /* Check the parameters */
01043   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
01044
01045   assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
01046   assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
01047   assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
01048
01049   /* Note: Hardware constraint (refer to description of this function):       */
01050   /*       ADC instance must be disabled.                                     */
01051   if(LL_ADC_IsEnabled(ADCx) == 0U)
01052   {
01053     /* Configuration of ADC hierarchical scope:                               */
01054     /*  - ADC instance                                                        */
01055     /*    - Set ADC data resolution                                           */
01056     /*    - Set ADC conversion data alignment                                 */
01057     /*    - Set ADC low power mode                                            */
01058     MODIFY_REG(ADCx->CFGR,
01059                  ADC_CFGR_RES
01060                | ADC_CFGR_ALIGN
01061                | ADC_CFGR_AUTDLY
01062               ,
01063                  ADC_InitStruct->Resolution
01064                | ADC_InitStruct->DataAlignment
01065                | ADC_InitStruct->LowPowerMode
01066               );
01067
01068   }
01069   else
01070   {
01071     /* Initialization error: ADC instance is not disabled. */
01072     status = ERROR;
01073   }
01074   return status;
01075 }
01076
01077 /**
01078   * @brief  Set each @ref LL_ADC_InitTypeDef field to default value.
01079   * @param  ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
01080   *                        whose fields will be set to default values.
01081   * @retval None
01082   */
01083 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
01084 {
01085   /* Set ADC_InitStruct fields to default values */
01086   /* Set fields of ADC instance */
01087   ADC_InitStruct->Resolution    = LL_ADC_RESOLUTION_12B;
01088   ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
01089   ADC_InitStruct->LowPowerMode  = LL_ADC_LP_MODE_NONE;
01090
01091 }
01092
01093 /**
01094   * @brief  Initialize some features of ADC group regular.
01095   * @note   These parameters have an impact on ADC scope: ADC group regular.
01096   *         Refer to corresponding unitary functions into
01097   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
01098   *         (functions with prefix "REG").
01099   * @note   The setting of these parameters by function @ref LL_ADC_Init()
01100   *         is conditioned to ADC state:
01101   *         ADC instance must be disabled.
01102   *         This condition is applied to all ADC features, for efficiency
01103   *         and compatibility over all STM32 families. However, the different
01104   *         features can be set under different ADC state conditions
01105   *         (setting possible with ADC enabled without conversion on going,
01106   *         ADC enabled with conversion on going, ...)
01107   *         Each feature can be updated afterwards with a unitary function
01108   *         and potentially with ADC in a different state than disabled,
01109   *         refer to description of each function for setting
01110   *         conditioned to ADC state.
01111   * @note   After using this function, other features must be configured
01112   *         using LL unitary functions.
01113   *         The minimum configuration remaining to be done is:
01114   *          - Set ADC group regular or group injected sequencer:
01115   *            map channel on the selected sequencer rank.
01116   *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
01117   *          - Set ADC channel sampling time
01118   *            Refer to function LL_ADC_SetChannelSamplingTime();
01119   * @param  ADCx ADC instance
01120   * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
01121   * @retval An ErrorStatus enumeration value:
01122   *          - SUCCESS: ADC registers are initialized
01123   *          - ERROR: ADC registers are not initialized
01124   */
01125 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
01126 {
01127   ErrorStatus status = SUCCESS;
01128
01129   /* Check the parameters */
01130   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
01131 #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
01132   assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource));
01133 #else
01134   assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
01135 #endif
01136   assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
01137   if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
01138   {
01139     assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
01140   }
01141   assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
01142   assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
01143   assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
01144
01145   /* Note: Hardware constraint (refer to description of this function):       */
01146   /*       ADC instance must be disabled.                                     */
01147   if(LL_ADC_IsEnabled(ADCx) == 0U)
01148   {
01149     /* Configuration of ADC hierarchical scope:                               */
01150     /*  - ADC group regular                                                   */
01151     /*    - Set ADC group regular trigger source                              */
01152     /*    - Set ADC group regular sequencer length                            */
01153     /*    - Set ADC group regular sequencer discontinuous mode                */
01154     /*    - Set ADC group regular continuous mode                             */
01155     /*    - Set ADC group regular conversion data transfer: no transfer or    */
01156     /*      transfer by DMA, and DMA requests mode                            */
01157     /*    - Set ADC group regular overrun behavior                            */
01158     /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by     */
01159     /*       setting of trigger source to SW start.                           */
01160     if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
01161     {
01162       MODIFY_REG(ADCx->CFGR,
01163                    ADC_CFGR_EXTSEL
01164                  | ADC_CFGR_EXTEN
01165                  | ADC_CFGR_DISCEN
01166                  | ADC_CFGR_DISCNUM
01167                  | ADC_CFGR_CONT
01168                  | ADC_CFGR_DMAEN
01169                  | ADC_CFGR_DMACFG
01170                  | ADC_CFGR_OVRMOD
01171                 ,
01172                    ADC_REG_InitStruct->TriggerSource
01173                  | ADC_REG_InitStruct->SequencerDiscont
01174                  | ADC_REG_InitStruct->ContinuousMode
01175                  | ADC_REG_InitStruct->DMATransfer
01176                  | ADC_REG_InitStruct->Overrun
01177                 );
01178     }
01179     else
01180     {
01181       MODIFY_REG(ADCx->CFGR,
01182                    ADC_CFGR_EXTSEL
01183                  | ADC_CFGR_EXTEN
01184                  | ADC_CFGR_DISCEN
01185                  | ADC_CFGR_DISCNUM
01186                  | ADC_CFGR_CONT
01187                  | ADC_CFGR_DMAEN
01188                  | ADC_CFGR_DMACFG
01189                  | ADC_CFGR_OVRMOD
01190                 ,
01191                    ADC_REG_InitStruct->TriggerSource
01192                  | LL_ADC_REG_SEQ_DISCONT_DISABLE
01193                  | ADC_REG_InitStruct->ContinuousMode
01194                  | ADC_REG_InitStruct->DMATransfer
01195                  | ADC_REG_InitStruct->Overrun
01196                 );
01197     }
01198
01199     /* Set ADC group regular sequencer length and scan direction */
01200     LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
01201   }
01202   else
01203   {
01204     /* Initialization error: ADC instance is not disabled. */
01205     status = ERROR;
01206   }
01207   return status;
01208 }
01209
01210 /**
01211   * @brief  Set each @ref LL_ADC_REG_InitTypeDef field to default value.
01212   * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
01213   *                            whose fields will be set to default values.
01214   * @retval None
01215   */
01216 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
01217 {
01218   /* Set ADC_REG_InitStruct fields to default values */
01219   /* Set fields of ADC group regular */
01220   /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by       */
01221   /*       setting of trigger source to SW start.                             */
01222   ADC_REG_InitStruct->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
01223   ADC_REG_InitStruct->SequencerLength  = LL_ADC_REG_SEQ_SCAN_DISABLE;
01224   ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
01225   ADC_REG_InitStruct->ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
01226   ADC_REG_InitStruct->DMATransfer      = LL_ADC_REG_DMA_TRANSFER_NONE;
01227   ADC_REG_InitStruct->Overrun          = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
01228 }
01229
01230 /**
01231   * @brief  Initialize some features of ADC group injected.
01232   * @note   These parameters have an impact on ADC scope: ADC group injected.
01233   *         Refer to corresponding unitary functions into
01234   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
01235   *         (functions with prefix "INJ").
01236   * @note   The setting of these parameters by function @ref LL_ADC_Init()
01237   *         is conditioned to ADC state:
01238   *         ADC instance must be disabled.
01239   *         This condition is applied to all ADC features, for efficiency
01240   *         and compatibility over all STM32 families. However, the different
01241   *         features can be set under different ADC state conditions
01242   *         (setting possible with ADC enabled without conversion on going,
01243   *         ADC enabled with conversion on going, ...)
01244   *         Each feature can be updated afterwards with a unitary function
01245   *         and potentially with ADC in a different state than disabled,
01246   *         refer to description of each function for setting
01247   *         conditioned to ADC state.
01248   * @note   After using this function, other features must be configured
01249   *         using LL unitary functions.
01250   *         The minimum configuration remaining to be done is:
01251   *          - Set ADC group injected sequencer:
01252   *            map channel on the selected sequencer rank.
01253   *            Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
01254   *          - Set ADC channel sampling time
01255   *            Refer to function LL_ADC_SetChannelSamplingTime();
01256   * @note   Caution to ADC group injected contexts queue: On this STM32 serie,
01257   *         using successively several times this function will appear has
01258   *         having no effect.
01259   *         This is due to ADC group injected contexts queue (this feature
01260   *         cannot be disabled on this STM32 serie).
01261   *         To set several features of ADC group injected, use
01262   *         function @ref LL_ADC_INJ_ConfigQueueContext().
01263   * @param  ADCx ADC instance
01264   * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
01265   * @retval An ErrorStatus enumeration value:
01266   *          - SUCCESS: ADC registers are initialized
01267   *          - ERROR: ADC registers are not initialized
01268   */
01269 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
01270 {
01271   ErrorStatus status = SUCCESS;
01272
01273   /* Check the parameters */
01274   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
01275 #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
01276   assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource));
01277 #else
01278   assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
01279 #endif
01280   assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
01281   if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
01282   {
01283     assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
01284   }
01285   assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
01286
01287   /* Note: Hardware constraint (refer to description of this function):       */
01288   /*       ADC instance must be disabled.                                     */
01289   if(LL_ADC_IsEnabled(ADCx) == 0U)
01290   {
01291     /* Configuration of ADC hierarchical scope:                               */
01292     /*  - ADC group injected                                                  */
01293     /*    - Set ADC group injected trigger source                             */
01294     /*    - Set ADC group injected sequencer length                           */
01295     /*    - Set ADC group injected sequencer discontinuous mode               */
01296     /*    - Set ADC group injected conversion trigger: independent or         */
01297     /*      from ADC group regular                                            */
01298     /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by     */
01299     /*       setting of trigger source to SW start.                           */
01300     if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
01301     {
01302       MODIFY_REG(ADCx->CFGR,
01303                    ADC_CFGR_JDISCEN
01304                  | ADC_CFGR_JAUTO
01305                 ,
01306                    ADC_INJ_InitStruct->SequencerDiscont
01307                  | ADC_INJ_InitStruct->TrigAuto
01308                 );
01309     }
01310     else
01311     {
01312       MODIFY_REG(ADCx->CFGR,
01313                    ADC_CFGR_JDISCEN
01314                  | ADC_CFGR_JAUTO
01315                 ,
01316                    LL_ADC_REG_SEQ_DISCONT_DISABLE
01317                  | ADC_INJ_InitStruct->TrigAuto
01318                 );
01319     }
01320
01321     MODIFY_REG(ADCx->JSQR,
01322                  ADC_JSQR_JEXTSEL
01323                | ADC_JSQR_JEXTEN
01324                | ADC_JSQR_JL
01325               ,
01326                  ADC_INJ_InitStruct->TriggerSource
01327                | ADC_INJ_InitStruct->SequencerLength
01328               );
01329   }
01330   else
01331   {
01332     /* Initialization error: ADC instance is not disabled. */
01333     status = ERROR;
01334   }
01335   return status;
01336 }
01337
01338 /**
01339   * @brief  Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
01340   * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
01341   *                            whose fields will be set to default values.
01342   * @retval None
01343   */
01344 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
01345 {
01346   /* Set ADC_INJ_InitStruct fields to default values */
01347   /* Set fields of ADC group injected */
01348   ADC_INJ_InitStruct->TriggerSource    = LL_ADC_INJ_TRIG_SOFTWARE;
01349   ADC_INJ_InitStruct->SequencerLength  = LL_ADC_INJ_SEQ_SCAN_DISABLE;
01350   ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
01351   ADC_INJ_InitStruct->TrigAuto         = LL_ADC_INJ_TRIG_INDEPENDENT;
01352 }
01353
01354 /**
01355   * @}
01356   */
01357
01358 /**
01359   * @}
01360   */
01361
01362 /**
01363   * @}
01364   */
01365
01366 #endif /* ADC1 || ADC2 || ADC3 || ADC4 */
01367
01368
01369 #endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
01370
01371 #if defined (ADC1_V2_5)
01372
01373 #if defined (ADC1)
01374
01375 /** @addtogroup ADC_LL ADC
01376   * @{
01377   */
01378
01379 /* Private types -------------------------------------------------------------*/
01380 /* Private variables ---------------------------------------------------------*/
01381 /* Private constants ---------------------------------------------------------*/
01382 /* Private macros ------------------------------------------------------------*/
01383
01384 /** @addtogroup ADC_LL_Private_Macros
01385   * @{
01386   */
01387
01388 /* Check of parameters for configuration of ADC hierarchical scope:           */
01389 /* common to several ADC instances.                                           */
01390 /* Check of parameters for configuration of ADC hierarchical scope:           */
01391 /* ADC instance.                                                              */
01392 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)                                   \
01393   (   ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                            \
01394    || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) )
01395
01396 #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__)                           \
01397   (   ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE)                        \
01398    || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) )
01399
01400 #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__)                             \
01401   (   ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE)                             \
01402    || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) )
01403
01404 /* Check of parameters for configuration of ADC hierarchical scope:           */
01405 /* ADC group regular                                                          */
01406 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
01407   (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
01408    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
01409    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
01410    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH2)                  \
01411    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_TRGO)                \
01412    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_CH3)                 \
01413    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_CH4)                 \
01414    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11))
01415
01416 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \
01417   (   ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                    \
01418    || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS))
01419
01420 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)                       \
01421   (   ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                 \
01422    || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED))
01423
01424 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)                 \
01425   (   ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)               \
01426    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
01427    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
01428    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
01429    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
01430    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
01431    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
01432    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
01433    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
01434    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
01435    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
01436    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
01437    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
01438    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
01439    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
01440    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS))
01441
01442 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \
01443   (   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \
01444    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
01445    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
01446    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
01447    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \
01448    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \
01449    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \
01450    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \
01451    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) )
01452
01453 /* Check of parameters for configuration of ADC hierarchical scope:           */
01454 /* ADC group injected                                                         */
01455 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)                         \
01456   (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
01457    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
01458    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
01459    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
01460    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                  \
01461    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM19_CH1)                 \
01462    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM19_CH2)                 \
01463    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15))
01464
01465 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)                             \
01466   (   ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                     \
01467    || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR))
01468
01469 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)                 \
01470   (   ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)               \
01471    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
01472    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
01473    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS))
01474
01475 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)          \
01476   (   ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)           \
01477    || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)  )
01478
01479 /**
01480   * @}
01481   */
01482
01483
01484 /* Private function prototypes -----------------------------------------------*/
01485
01486 /* Exported functions --------------------------------------------------------*/
01487 /** @addtogroup ADC_LL_Exported_Functions
01488   * @{
01489   */
01490
01491 /** @addtogroup ADC_LL_EF_Init
01492   * @{
01493   */
01494
01495 /**
01496   * @brief  De-initialize registers of all ADC instances belonging to
01497   *         the same ADC common instance to their default reset values.
01498   * @param  ADCxy_COMMON ADC common instance
01499   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01500   * @retval An ErrorStatus enumeration value:
01501   *          - SUCCESS: ADC common registers are de-initialized
01502   *          - ERROR: not applicable
01503   */
01504 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
01505 {
01506   /* Check the parameters */
01507   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
01508
01509   /* Force reset of ADC clock (core clock) */
01510   LL_APB2_GRP1_ForceReset  (LL_APB2_GRP1_PERIPH_ADC1);
01511
01512   /* Release reset of ADC clock (core clock) */
01513   LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
01514
01515   return SUCCESS;
01516 }
01517
01518 /**
01519   * @brief  De-initialize registers of the selected ADC instance
01520   *         to their default reset values.
01521   * @note   To reset all ADC instances quickly (perform a hard reset),
01522   *         use function @ref LL_ADC_CommonDeInit().
01523   * @param  ADCx ADC instance
01524   * @retval An ErrorStatus enumeration value:
01525   *          - SUCCESS: ADC registers are de-initialized
01526   *          - ERROR: ADC registers are not de-initialized
01527   */
01528 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
01529 {
01530   ErrorStatus status = SUCCESS;
01531
01532   /* Check the parameters */
01533   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
01534
01535   /* Disable ADC instance if not already disabled.                            */
01536   if(LL_ADC_IsEnabled(ADCx) == 1U)
01537   {
01538     /* Set ADC group regular trigger source to SW start to ensure to not      */
01539     /* have an external trigger event occurring during the conversion stop    */
01540     /* ADC disable process.                                                   */
01541     LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
01542
01543     /* Set ADC group injected trigger source to SW start to ensure to not     */
01544     /* have an external trigger event occurring during the conversion stop    */
01545     /* ADC disable process.                                                   */
01546     LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
01547
01548     /* Disable the ADC instance */
01549     LL_ADC_Disable(ADCx);
01550   }
01551
01552   /* Check whether ADC state is compliant with expected state */
01553   /* (hardware requirements of bits state to reset registers below) */
01554   if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
01555   {
01556     /* ========== Reset ADC registers ========== */
01557     /* Reset register SR */
01558     CLEAR_BIT(ADCx->SR,
01559               (  LL_ADC_FLAG_STRT
01560                | LL_ADC_FLAG_JSTRT
01561                | LL_ADC_FLAG_EOS
01562                | LL_ADC_FLAG_JEOS
01563                | LL_ADC_FLAG_AWD1 )
01564              );
01565
01566     /* Reset register CR1 */
01567     CLEAR_BIT(ADCx->CR1,
01568               (  ADC_CR1_AWDEN   | ADC_CR1_JAWDEN
01569                | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
01570                | ADC_CR1_JAUTO   | ADC_CR1_AWDSGL  | ADC_CR1_SCAN
01571                | ADC_CR1_JEOCIE  | ADC_CR1_AWDIE   | ADC_CR1_EOCIE
01572                | ADC_CR1_AWDCH                                     )
01573              );
01574
01575     /* Reset register CR2 */
01576     CLEAR_BIT(ADCx->CR2,
01577               (  ADC_CR2_TSVREFE
01578                | ADC_CR2_SWSTART  | ADC_CR2_EXTTRIG  | ADC_CR2_EXTSEL
01579                | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL
01580                | ADC_CR2_ALIGN    | ADC_CR2_DMA
01581                | ADC_CR2_RSTCAL   | ADC_CR2_CAL
01582                | ADC_CR2_CONT     | ADC_CR2_ADON                      )
01583              );
01584
01585     /* Reset register SMPR1 */
01586     CLEAR_BIT(ADCx->SMPR1,
01587               (  ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
01588                | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
01589                | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
01590              );
01591
01592     /* Reset register SMPR2 */
01593     CLEAR_BIT(ADCx->SMPR2,
01594               (  ADC_SMPR2_SMP9
01595                | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
01596                | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
01597                | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
01598              );
01599
01600     /* Reset register JOFR1 */
01601     CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
01602     /* Reset register JOFR2 */
01603     CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
01604     /* Reset register JOFR3 */
01605     CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
01606     /* Reset register JOFR4 */
01607     CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
01608
01609     /* Reset register HTR */
01610     SET_BIT(ADCx->HTR, ADC_HTR_HT);
01611     /* Reset register LTR */
01612     CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
01613
01614     /* Reset register SQR1 */
01615     CLEAR_BIT(ADCx->SQR1,
01616               (  ADC_SQR1_L
01617                | ADC_SQR1_SQ16
01618                | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
01619              );
01620
01621     /* Reset register SQR2 */
01622     CLEAR_BIT(ADCx->SQR2,
01623               (  ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
01624                | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
01625              );
01626
01627
01628     /* Reset register JSQR */
01629     CLEAR_BIT(ADCx->JSQR,
01630               (  ADC_JSQR_JL
01631                | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
01632                | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1  )
01633              );
01634
01635     /* Reset register DR */
01636     /* bits in access mode read only, no direct reset applicable */
01637
01638     /* Reset registers JDR1, JDR2, JDR3, JDR4 */
01639     /* bits in access mode read only, no direct reset applicable */
01640
01641   }
01642
01643   return status;
01644 }
01645
01646 /**
01647   * @brief  Initialize some features of ADC instance.
01648   * @note   These parameters have an impact on ADC scope: ADC instance.
01649   *         Affects both group regular and group injected (availability
01650   *         of ADC group injected depends on STM32 families).
01651   *         Refer to corresponding unitary functions into
01652   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
01653   * @note   The setting of these parameters by function @ref LL_ADC_Init()
01654   *         is conditioned to ADC state:
01655   *         ADC instance must be disabled.
01656   *         This condition is applied to all ADC features, for efficiency
01657   *         and compatibility over all STM32 families. However, the different
01658   *         features can be set under different ADC state conditions
01659   *         (setting possible with ADC enabled without conversion on going,
01660   *         ADC enabled with conversion on going, ...)
01661   *         Each feature can be updated afterwards with a unitary function
01662   *         and potentially with ADC in a different state than disabled,
01663   *         refer to description of each function for setting
01664   *         conditioned to ADC state.
01665   * @note   After using this function, some other features must be configured
01666   *         using LL unitary functions.
01667   *         The minimum configuration remaining to be done is:
01668   *          - Set ADC group regular or group injected sequencer:
01669   *            map channel on the selected sequencer rank.
01670   *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
01671   *          - Set ADC channel sampling time
01672   *            Refer to function LL_ADC_SetChannelSamplingTime();
01673   * @param  ADCx ADC instance
01674   * @param  ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
01675   * @retval An ErrorStatus enumeration value:
01676   *          - SUCCESS: ADC registers are initialized
01677   *          - ERROR: ADC registers are not initialized
01678   */
01679 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
01680 {
01681   ErrorStatus status = SUCCESS;
01682
01683   /* Check the parameters */
01684   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
01685
01686   assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
01687   assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
01688
01689   /* Note: Hardware constraint (refer to description of this function):       */
01690   /*       ADC instance must be disabled.                                     */
01691   if(LL_ADC_IsEnabled(ADCx) == 0U)
01692   {
01693     /* Configuration of ADC hierarchical scope:                               */
01694     /*  - ADC instance                                                        */
01695     /*    - Set ADC conversion data alignment                                 */
01696     MODIFY_REG(ADCx->CR1,
01697                  ADC_CR1_SCAN
01698               ,
01699                  ADC_InitStruct->SequencersScanMode
01700               );
01701
01702     MODIFY_REG(ADCx->CR2,
01703                  ADC_CR2_ALIGN
01704               ,
01705                  ADC_InitStruct->DataAlignment
01706               );
01707
01708   }
01709   else
01710   {
01711     /* Initialization error: ADC instance is not disabled. */
01712     status = ERROR;
01713   }
01714   return status;
01715 }
01716
01717 /**
01718   * @brief  Set each @ref LL_ADC_InitTypeDef field to default value.
01719   * @param  ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
01720   *                        whose fields will be set to default values.
01721   * @retval None
01722   */
01723 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
01724 {
01725   /* Set ADC_InitStruct fields to default values */
01726   /* Set fields of ADC instance */
01727   ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
01728
01729   /* Enable scan mode to have a generic behavior with ADC of other            */
01730   /* STM32 families, without this setting available:                          */
01731   /* ADC group regular sequencer and ADC group injected sequencer depend      */
01732   /* only of their own configuration.                                         */
01733   ADC_InitStruct->SequencersScanMode      = LL_ADC_SEQ_SCAN_ENABLE;
01734
01735 }
01736
01737 /**
01738   * @brief  Initialize some features of ADC group regular.
01739   * @note   These parameters have an impact on ADC scope: ADC group regular.
01740   *         Refer to corresponding unitary functions into
01741   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
01742   *         (functions with prefix "REG").
01743   * @note   The setting of these parameters by function @ref LL_ADC_Init()
01744   *         is conditioned to ADC state:
01745   *         ADC instance must be disabled.
01746   *         This condition is applied to all ADC features, for efficiency
01747   *         and compatibility over all STM32 families. However, the different
01748   *         features can be set under different ADC state conditions
01749   *         (setting possible with ADC enabled without conversion on going,
01750   *         ADC enabled with conversion on going, ...)
01751   *         Each feature can be updated afterwards with a unitary function
01752   *         and potentially with ADC in a different state than disabled,
01753   *         refer to description of each function for setting
01754   *         conditioned to ADC state.
01755   * @note   After using this function, other features must be configured
01756   *         using LL unitary functions.
01757   *         The minimum configuration remaining to be done is:
01758   *          - Set ADC group regular or group injected sequencer:
01759   *            map channel on the selected sequencer rank.
01760   *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
01761   *          - Set ADC channel sampling time
01762   *            Refer to function LL_ADC_SetChannelSamplingTime();
01763   * @param  ADCx ADC instance
01764   * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
01765   * @retval An ErrorStatus enumeration value:
01766   *          - SUCCESS: ADC registers are initialized
01767   *          - ERROR: ADC registers are not initialized
01768   */
01769 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
01770 {
01771   ErrorStatus status = SUCCESS;
01772
01773   /* Check the parameters */
01774   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
01775   assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
01776   assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
01777   if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
01778   {
01779     assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
01780   }
01781   assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
01782   assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
01783
01784   /* Note: Hardware constraint (refer to description of this function):       */
01785   /*       ADC instance must be disabled.                                     */
01786   if(LL_ADC_IsEnabled(ADCx) == 0U)
01787   {
01788     /* Configuration of ADC hierarchical scope:                               */
01789     /*  - ADC group regular                                                   */
01790     /*    - Set ADC group regular trigger source                              */
01791     /*    - Set ADC group regular sequencer length                            */
01792     /*    - Set ADC group regular sequencer discontinuous mode                */
01793     /*    - Set ADC group regular continuous mode                             */
01794     /*    - Set ADC group regular conversion data transfer: no transfer or    */
01795     /*      transfer by DMA, and DMA requests mode                            */
01796     /* Note: On this STM32 serie, ADC trigger edge is set when starting        */
01797     /*       ADC conversion.                                                  */
01798     /*       Refer to function @ref LL_ADC_REG_StartConversionExtTrig().      */
01799     if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
01800     {
01801       MODIFY_REG(ADCx->CR1,
01802                    ADC_CR1_DISCEN
01803                  | ADC_CR1_DISCNUM
01804                 ,
01805                    ADC_REG_InitStruct->SequencerLength
01806                  | ADC_REG_InitStruct->SequencerDiscont
01807                 );
01808     }
01809     else
01810     {
01811       MODIFY_REG(ADCx->CR1,
01812                    ADC_CR1_DISCEN
01813                  | ADC_CR1_DISCNUM
01814                 ,
01815                    ADC_REG_InitStruct->SequencerLength
01816                  | LL_ADC_REG_SEQ_DISCONT_DISABLE
01817                 );
01818     }
01819
01820     MODIFY_REG(ADCx->CR2,
01821                  ADC_CR2_EXTSEL
01822                | ADC_CR2_CONT
01823                | ADC_CR2_DMA
01824               ,
01825                  ADC_REG_InitStruct->TriggerSource
01826                | ADC_REG_InitStruct->ContinuousMode
01827                | ADC_REG_InitStruct->DMATransfer
01828               );
01829
01830     /* Set ADC group regular sequencer length and scan direction */
01831     /* Note: Hardware constraint (refer to description of this function):     */
01832     /* Note: If ADC instance feature scan mode is disabled                    */
01833     /*       (refer to  ADC instance initialization structure                 */
01834     /*       parameter @ref SequencersScanMode                                */
01835     /*       or function @ref LL_ADC_SetSequencersScanMode() ),               */
01836     /*       this parameter is discarded.                                     */
01837     LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
01838   }
01839   else
01840   {
01841     /* Initialization error: ADC instance is not disabled. */
01842     status = ERROR;
01843   }
01844   return status;
01845 }
01846
01847 /**
01848   * @brief  Set each @ref LL_ADC_REG_InitTypeDef field to default value.
01849   * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
01850   *                            whose fields will be set to default values.
01851   * @retval None
01852   */
01853 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
01854 {
01855   /* Set ADC_REG_InitStruct fields to default values */
01856   /* Set fields of ADC group regular */
01857   /* Note: On this STM32 serie, ADC trigger edge is set when starting         */
01858   /*       ADC conversion.                                                    */
01859   /*       Refer to function @ref LL_ADC_REG_StartConversionExtTrig().        */
01860   ADC_REG_InitStruct->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
01861   ADC_REG_InitStruct->SequencerLength  = LL_ADC_REG_SEQ_SCAN_DISABLE;
01862   ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
01863   ADC_REG_InitStruct->ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
01864   ADC_REG_InitStruct->DMATransfer      = LL_ADC_REG_DMA_TRANSFER_NONE;
01865 }
01866
01867 /**
01868   * @brief  Initialize some features of ADC group injected.
01869   * @note   These parameters have an impact on ADC scope: ADC group injected.
01870   *         Refer to corresponding unitary functions into
01871   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
01872   *         (functions with prefix "INJ").
01873   * @note   The setting of these parameters by function @ref LL_ADC_Init()
01874   *         is conditioned to ADC state:
01875   *         ADC instance must be disabled.
01876   *         This condition is applied to all ADC features, for efficiency
01877   *         and compatibility over all STM32 families. However, the different
01878   *         features can be set under different ADC state conditions
01879   *         (setting possible with ADC enabled without conversion on going,
01880   *         ADC enabled with conversion on going, ...)
01881   *         Each feature can be updated afterwards with a unitary function
01882   *         and potentially with ADC in a different state than disabled,
01883   *         refer to description of each function for setting
01884   *         conditioned to ADC state.
01885   * @note   After using this function, other features must be configured
01886   *         using LL unitary functions.
01887   *         The minimum configuration remaining to be done is:
01888   *          - Set ADC group injected sequencer:
01889   *            map channel on the selected sequencer rank.
01890   *            Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
01891   *          - Set ADC channel sampling time
01892   *            Refer to function LL_ADC_SetChannelSamplingTime();
01893   * @param  ADCx ADC instance
01894   * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
01895   * @retval An ErrorStatus enumeration value:
01896   *          - SUCCESS: ADC registers are initialized
01897   *          - ERROR: ADC registers are not initialized
01898   */
01899 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
01900 {
01901   ErrorStatus status = SUCCESS;
01902
01903   /* Check the parameters */
01904   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
01905   assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
01906   assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
01907   if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
01908   {
01909     assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
01910   }
01911   assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
01912
01913   /* Note: Hardware constraint (refer to description of this function):       */
01914   /*       ADC instance must be disabled.                                     */
01915   if(LL_ADC_IsEnabled(ADCx) == 0U)
01916   {
01917     /* Configuration of ADC hierarchical scope:                               */
01918     /*  - ADC group injected                                                  */
01919     /*    - Set ADC group injected trigger source                             */
01920     /*    - Set ADC group injected sequencer length                           */
01921     /*    - Set ADC group injected sequencer discontinuous mode               */
01922     /*    - Set ADC group injected conversion trigger: independent or         */
01923     /*      from ADC group regular                                            */
01924     /* Note: On this STM32 serie, ADC trigger edge is set when starting       */
01925     /*       ADC conversion.                                                  */
01926     /*       Refer to function @ref LL_ADC_INJ_StartConversionExtTrig().      */
01927     if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
01928     {
01929       MODIFY_REG(ADCx->CR1,
01930                    ADC_CR1_JDISCEN
01931                  | ADC_CR1_JAUTO
01932                 ,
01933                    ADC_INJ_InitStruct->SequencerDiscont
01934                  | ADC_INJ_InitStruct->TrigAuto
01935                 );
01936     }
01937     else
01938     {
01939       MODIFY_REG(ADCx->CR1,
01940                    ADC_CR1_JDISCEN
01941                  | ADC_CR1_JAUTO
01942                 ,
01943                    LL_ADC_REG_SEQ_DISCONT_DISABLE
01944                  | ADC_INJ_InitStruct->TrigAuto
01945                 );
01946     }
01947
01948     MODIFY_REG(ADCx->CR2,
01949                ADC_CR2_JEXTSEL
01950               ,
01951                ADC_INJ_InitStruct->TriggerSource
01952               );
01953
01954     /* Note: Hardware constraint (refer to description of this function):     */
01955     /* Note: If ADC instance feature scan mode is disabled                    */
01956     /*       (refer to  ADC instance initialization structure                 */
01957     /*       parameter @ref SequencersScanMode                                */
01958     /*       or function @ref LL_ADC_SetSequencersScanMode() ),               */
01959     /*       this parameter is discarded.                                     */
01960     LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
01961   }
01962   else
01963   {
01964     /* Initialization error: ADC instance is not disabled. */
01965     status = ERROR;
01966   }
01967   return status;
01968 }
01969
01970 /**
01971   * @brief  Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
01972   * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
01973   *                            whose fields will be set to default values.
01974   * @retval None
01975   */
01976 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
01977 {
01978   /* Set ADC_INJ_InitStruct fields to default values */
01979   /* Set fields of ADC group injected */
01980   ADC_INJ_InitStruct->TriggerSource    = LL_ADC_INJ_TRIG_SOFTWARE;
01981   ADC_INJ_InitStruct->SequencerLength  = LL_ADC_INJ_SEQ_SCAN_DISABLE;
01982   ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
01983   ADC_INJ_InitStruct->TrigAuto         = LL_ADC_INJ_TRIG_INDEPENDENT;
01984 }
01985
01986 /**
01987   * @}
01988   */
01989
01990 /**
01991   * @}
01992   */
01993
01994 /**
01995   * @}
01996   */
01997
01998 #endif /* ADC1 */
01999
02000
02001 #endif /* STM32F373xC || STM32F378xx */
02002
02003 /**
02004   * @}
02005   */
02006
02007 #endif /* USE_FULL_LL_DRIVER */
02008
02009 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:09 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_adc.h Source File

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stm32f3xx_ll_adc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_adc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of ADC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_ADC_H
00038 #define __STM32F3xx_LL_ADC_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 /* Note: Devices of STM32F3 serie embed 1 out of 2 different ADC IP.          */
00052 /*       - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x:  */
00053 /*         ADC IP 5Msamples/sec, from 1 to 4 ADC instances and other specific */
00054 /*         features (refer to reference manual).                              */
00055 /*       - STM32F37x:                                                         */
00056 /*         ADC IP 1Msamples/sec, 1 ADC instance                               */
00057 /*       This file contains the drivers of these ADC IP, located in 2 area    */
00058 /*       delimited by compilation switches.                                   */
00059
00060 #if defined(ADC5_V1_1)
00061
00062 #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4)
00063
00064 /** @defgroup ADC_LL ADC
00065   * @{
00066   */
00067
00068 /* Private types -------------------------------------------------------------*/
00069 /* Private variables ---------------------------------------------------------*/
00070
00071 /* Private constants ---------------------------------------------------------*/
00072 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
00073   * @{
00074   */
00075
00076 /* Internal mask for ADC group regular sequencer:                             */
00077 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
00078 /* - sequencer register offset                                                */
00079 /* - sequencer rank bits position into the selected register                  */
00080
00081 /* Internal register offset for ADC group regular sequencer configuration */
00082 /* (offset placed into a spare area of literal definition) */
00083 #define ADC_SQR1_REGOFFSET                 ((uint32_t)0x00000000U)
00084 #define ADC_SQR2_REGOFFSET                 ((uint32_t)0x00000100U)
00085 #define ADC_SQR3_REGOFFSET                 ((uint32_t)0x00000200U)
00086 #define ADC_SQR4_REGOFFSET                 ((uint32_t)0x00000300U)
00087
00088 #define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
00089 #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
00090
00091 /* Definition of ADC group regular sequencer bits information to be inserted  */
00092 /* into ADC group regular sequencer ranks literals definition.                */
00093 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */
00094 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */
00095 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */
00096 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */
00097 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */
00098 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */
00099 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
00100 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
00101 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
00102 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */
00103 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */
00104 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */
00105 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
00106 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
00107 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */
00108 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */
00109
00110
00111
00112 /* Internal mask for ADC group injected sequencer:                            */
00113 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */
00114 /* - data register offset                                                     */
00115 /* - sequencer rank bits position into the selected register                  */
00116
00117 /* Internal register offset for ADC group injected data register */
00118 /* (offset placed into a spare area of literal definition) */
00119 #define ADC_JDR1_REGOFFSET                 ((uint32_t)0x00000000U)
00120 #define ADC_JDR2_REGOFFSET                 ((uint32_t)0x00000100U)
00121 #define ADC_JDR3_REGOFFSET                 ((uint32_t)0x00000200U)
00122 #define ADC_JDR4_REGOFFSET                 ((uint32_t)0x00000300U)
00123
00124 #define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
00125 #define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
00126
00127 /* Definition of ADC group injected sequencer bits information to be inserted */
00128 /* into ADC group injected sequencer ranks literals definition.               */
00129 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
00130 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
00131 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
00132 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  ((uint32_t)26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
00133
00134
00135
00136 /* Internal mask for ADC group regular trigger:                               */
00137 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
00138 /* - regular trigger source                                                   */
00139 /* - regular trigger edge                                                     */
00140 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
00141
00142 /* Mask containing trigger source masks for each of possible                  */
00143 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00144 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00145 #define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0U)) | \
00146                                              ((ADC_CFGR_EXTSEL)                            << (4U * 1U)) | \
00147                                              ((ADC_CFGR_EXTSEL)                            << (4U * 2U)) | \
00148                                              ((ADC_CFGR_EXTSEL)                            << (4U * 3U))  )
00149
00150 /* Mask containing trigger edge masks for each of possible                    */
00151 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00152 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00153 #define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0U)) | \
00154                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1U)) | \
00155                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2U)) | \
00156                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3U))  )
00157
00158 /* Definition of ADC group regular trigger bits information.                  */
00159 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */
00160 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */
00161
00162
00163
00164 /* Internal definitions for ADC group regular trigger sources:                */
00165 /* To differentiate into literal LL_ADC_REG_TRIG_x the trigger sources        */
00166 /* depending on ADC instances ADC1, ADC2, ADC3, ADC4 (if ADC instance is      */
00167 /* available on the selected device).                                         */
00168
00169 #if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
00170 /* Internal mask offset for ADC group injected trigger sources                */
00171 /* available only on specific ADC instances.                                  */
00172 /* (offset placed into a spare area of literal definition) */
00173 #define ADC_REG_TRIG_EXT_INST_ADC12        ((uint32_t)0x00000001U) /* Marker for differentiation of ADC group regular external trigger available only on ADC instance: ADC1, ADC2 */
00174 #define ADC_REG_TRIG_EXT_INST_ADC34        ((uint32_t)0x00000002U) /* Marker for differentiation of ADC group regular external trigger available only on ADC instance: ADC3, ADC4 */
00175 #endif
00176
00177 /* Internal mask for ADC group injected trigger:                              */
00178 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */
00179 /* - injected trigger source                                                  */
00180 /* - injected trigger edge                                                    */
00181 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
00182
00183 /* Mask containing trigger source masks for each of possible                  */
00184 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00185 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00186 #define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0U)) | \
00187                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 1U)) | \
00188                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 2U)) | \
00189                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 3U))  )
00190
00191 /* Mask containing trigger edge masks for each of possible                    */
00192 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00193 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00194 #define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0U)) | \
00195                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1U)) | \
00196                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2U)) | \
00197                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3U))  )
00198
00199 /* Definition of ADC group injected trigger bits information.                 */
00200 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */
00201 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */
00202
00203
00204
00205 /* Internal definitions for ADC group injected trigger sources:               */
00206 /* To differentiate into literal LL_ADC_INJ_TRIG_x the trigger sources        */
00207 /* depending on ADC instances ADC1, ADC2, ADC3, ADC4 (if ADC instance is      */
00208 /* available on the selected device).                                         */
00209
00210 #if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
00211 /* Internal mask offset for ADC group injected trigger sources                */
00212 /* available only on specific ADC instances.                                  */
00213 /* (offset placed into a spare area of literal definition) */
00214 #define ADC_INJ_TRIG_EXT_INST_ADC12        ((uint32_t)0x00000001U) /* Marker for differentiation of ADC group injected external trigger available only on ADC instance: ADC1, ADC2 */
00215 #define ADC_INJ_TRIG_EXT_INST_ADC34        ((uint32_t)0x00000002U) /* Marker for differentiation of ADC group injected external trigger available only on ADC instance: ADC3, ADC4 */
00216 #endif
00217
00218
00219
00220
00221 /* Internal mask for ADC channel:                                             */
00222 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
00223 /* - channel identifier defined by number                                     */
00224 /* - channel identifier defined by bitfield                                   */
00225 /* - channel differentiation between external channels (connected to          */
00226 /*   GPIO pins) and internal channels (connected to internal paths)           */
00227 /* - channel sampling time defined by SMPRx register offset                   */
00228 /*   and SMPx bits positions into SMPRx register                              */
00229 #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR_AWD1CH)
00230 #define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_AWD2CR_AWD2CH)
00231 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
00232 #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
00233 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
00234 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
00235
00236 /* Channel differentiation between external and internal channels */
00237 #define ADC_CHANNEL_ID_INTERNAL_CH         ((uint32_t)0x80000000U) /* Marker of internal channel */
00238 #define ADC_CHANNEL_ID_INTERNAL_CH_2       ((uint32_t)0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
00239 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
00240
00241 /* Internal register offset for ADC channel sampling time configuration */
00242 /* (offset placed into a spare area of literal definition) */
00243 #define ADC_SMPR1_REGOFFSET                ((uint32_t)0x00000000U)
00244 #define ADC_SMPR2_REGOFFSET                ((uint32_t)0x02000000U)
00245 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
00246
00247 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK    ((uint32_t)0x01F00000U)
00248 #define ADC_CHANNEL_SMPx_BITOFFSET_POS     ((uint32_t)20U)           /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
00249
00250 /* Definition of channels ID number information to be inserted into           */
00251 /* channels literals definition.                                              */
00252 #define ADC_CHANNEL_0_NUMBER               ((uint32_t)0x00000000U)
00253 #define ADC_CHANNEL_1_NUMBER               (                                                                                ADC_CFGR_AWD1CH_0)
00254 #define ADC_CHANNEL_2_NUMBER               (                                                            ADC_CFGR_AWD1CH_1                    )
00255 #define ADC_CHANNEL_3_NUMBER               (                                                            ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00256 #define ADC_CHANNEL_4_NUMBER               (                                        ADC_CFGR_AWD1CH_2                                        )
00257 #define ADC_CHANNEL_5_NUMBER               (                                        ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)
00258 #define ADC_CHANNEL_6_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )
00259 #define ADC_CHANNEL_7_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00260 #define ADC_CHANNEL_8_NUMBER               (                    ADC_CFGR_AWD1CH_3                                                            )
00261 #define ADC_CHANNEL_9_NUMBER               (                    ADC_CFGR_AWD1CH_3                                         | ADC_CFGR_AWD1CH_0)
00262 #define ADC_CHANNEL_10_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1                    )
00263 #define ADC_CHANNEL_11_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00264 #define ADC_CHANNEL_12_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                                        )
00265 #define ADC_CHANNEL_13_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)
00266 #define ADC_CHANNEL_14_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )
00267 #define ADC_CHANNEL_15_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00268 #define ADC_CHANNEL_16_NUMBER              (ADC_CFGR_AWD1CH_4                                                                                )
00269 #define ADC_CHANNEL_17_NUMBER              (ADC_CFGR_AWD1CH_4                                                             | ADC_CFGR_AWD1CH_0)
00270 #define ADC_CHANNEL_18_NUMBER              (ADC_CFGR_AWD1CH_4                                         | ADC_CFGR_AWD1CH_1                    )
00271
00272 /* Definition of channels ID bitfield information to be inserted into         */
00273 /* channels literals definition.                                              */
00274 #define ADC_CHANNEL_0_BITFIELD             (ADC_AWD2CR_AWD2CH_0)
00275 #define ADC_CHANNEL_1_BITFIELD             (ADC_AWD2CR_AWD2CH_1)
00276 #define ADC_CHANNEL_2_BITFIELD             (ADC_AWD2CR_AWD2CH_2)
00277 #define ADC_CHANNEL_3_BITFIELD             (ADC_AWD2CR_AWD2CH_3)
00278 #define ADC_CHANNEL_4_BITFIELD             (ADC_AWD2CR_AWD2CH_4)
00279 #define ADC_CHANNEL_5_BITFIELD             (ADC_AWD2CR_AWD2CH_5)
00280 #define ADC_CHANNEL_6_BITFIELD             (ADC_AWD2CR_AWD2CH_6)
00281 #define ADC_CHANNEL_7_BITFIELD             (ADC_AWD2CR_AWD2CH_7)
00282 #define ADC_CHANNEL_8_BITFIELD             (ADC_AWD2CR_AWD2CH_8)
00283 #define ADC_CHANNEL_9_BITFIELD             (ADC_AWD2CR_AWD2CH_9)
00284 #define ADC_CHANNEL_10_BITFIELD            (ADC_AWD2CR_AWD2CH_10)
00285 #define ADC_CHANNEL_11_BITFIELD            (ADC_AWD2CR_AWD2CH_11)
00286 #define ADC_CHANNEL_12_BITFIELD            (ADC_AWD2CR_AWD2CH_12)
00287 #define ADC_CHANNEL_13_BITFIELD            (ADC_AWD2CR_AWD2CH_13)
00288 #define ADC_CHANNEL_14_BITFIELD            (ADC_AWD2CR_AWD2CH_14)
00289 #define ADC_CHANNEL_15_BITFIELD            (ADC_AWD2CR_AWD2CH_15)
00290 #define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)
00291 #define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)
00292 #define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)
00293
00294 /* Definition of channels sampling time information to be inserted into       */
00295 /* channels literals definition.                                              */
00296 #define ADC_CHANNEL_0_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */
00297 #define ADC_CHANNEL_1_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */
00298 #define ADC_CHANNEL_2_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */
00299 #define ADC_CHANNEL_3_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */
00300 #define ADC_CHANNEL_4_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */
00301 #define ADC_CHANNEL_5_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */
00302 #define ADC_CHANNEL_6_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */
00303 #define ADC_CHANNEL_7_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */
00304 #define ADC_CHANNEL_8_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */
00305 #define ADC_CHANNEL_9_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */
00306 #define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
00307 #define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
00308 #define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
00309 #define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
00310 #define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
00311 #define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
00312 #define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
00313 #define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
00314 #define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
00315
00316
00317 /* Internal mask for ADC mode single or differential ended:                   */
00318 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */
00319 /* the relevant bits for:                                                     */
00320 /* (concatenation of multiple bits used in different registers)               */
00321 /* - ADC calibration: calibration start, calibration factor get or set        */
00322 /* - ADC channels: set each ADC channel ending mode                           */
00323 #define ADC_SINGLEDIFF_CALIB_START_MASK    (ADC_CR_ADCALDIF)
00324 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK   (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
00325 #define ADC_SINGLEDIFF_CHANNEL_MASK        (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
00326 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK  (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
00327
00328
00329 /* Internal mask for ADC analog watchdog:                                     */
00330 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
00331 /* (concatenation of multiple bits used in different analog watchdogs,        */
00332 /* (feature of several watchdogs not available on all STM32 families)).       */
00333 /* - analog watchdog 1: monitored channel defined by number,                  */
00334 /*   selection of ADC group (ADC groups regular and-or injected).             */
00335 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */
00336 /*   selection on groups.                                                     */
00337
00338 /* Internal register offset for ADC analog watchdog channel configuration */
00339 #define ADC_AWD_CR1_REGOFFSET              ((uint32_t)0x00000000U)
00340 #define ADC_AWD_CR2_REGOFFSET              ((uint32_t)0x00100000U)
00341 #define ADC_AWD_CR3_REGOFFSET              ((uint32_t)0x00200000U)
00342
00343 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
00344 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
00345 #define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)
00346 #define ADC_AWD_CR12_REGOFFSETGAP_VAL      ((uint32_t)0x00000024U)
00347
00348 #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
00349
00350 #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
00351 #define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)
00352 #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
00353
00354 /* Internal register offset for ADC analog watchdog threshold configuration */
00355 #define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)
00356 #define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)
00357 #define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET)
00358 #define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
00359
00360
00361 /* Internal mask for ADC offset:                                              */
00362 /* Internal register offset for ADC offset number configuration */
00363 #define ADC_OFR1_REGOFFSET                 ((uint32_t)0x00000000U)
00364 #define ADC_OFR2_REGOFFSET                 ((uint32_t)0x00000001U)
00365 #define ADC_OFR3_REGOFFSET                 ((uint32_t)0x00000002U)
00366 #define ADC_OFR4_REGOFFSET                 ((uint32_t)0x00000003U)
00367 #define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
00368
00369
00370 /* ADC registers bits positions */
00371 #define ADC_CFGR_RES_BITOFFSET_POS         ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */
00372 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS     ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */
00373 #define ADC_CFGR_AWD1EN_BITOFFSET_POS      ((uint32_t)23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */
00374 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS     ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */
00375 #define ADC_TR1_HT1_BITOFFSET_POS          ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */
00376
00377
00378 /* ADC registers bits groups */
00379 #define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
00380
00381
00382 /* ADC internal channels related definitions */
00383 /* Internal voltage reference VrefInt */
00384 #define VREFINT_CAL_ADDR                   ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
00385 #define VREFINT_CAL_VREF                   ((uint32_t) 3300U)                    /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
00386 /* Temperature sensor */
00387 #define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F3, temperature sensor ADC raw data acquired at temperature  25 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
00388 #define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F3, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
00389 #define TEMPSENSOR_CAL1_TEMP               (( int32_t)   25)                     /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
00390 #define TEMPSENSOR_CAL2_TEMP               (( int32_t)  110)                     /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
00391 #define TEMPSENSOR_CAL_VREFANALOG          ((uint32_t) 3300U)                    /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
00392
00393
00394 /**
00395   * @}
00396   */
00397
00398
00399 /* Private macros ------------------------------------------------------------*/
00400 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
00401   * @{
00402   */
00403
00404 /**
00405   * @brief  Driver macro reserved for internal use: isolate bits with the
00406   *         selected mask and shift them to the register LSB
00407   *         (shift mask on register position bit 0).
00408   * @param  __BITS__ Bits in register 32 bits
00409   * @param  __MASK__ Mask in register 32 bits
00410   * @retval Bits in register 32 bits
00411   */
00412 #define __ADC_MASK_SHIFT(__BITS__, __MASK__)                                   \
00413   (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
00414
00415 /**
00416   * @brief  Driver macro reserved for internal use: set a pointer to
00417   *         a register from a register basis from which an offset
00418   *         is applied.
00419   * @param  __REG__ Register basis from which the offset is applied.
00420   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
00421   * @retval Pointer to register address
00422   */
00423 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
00424  ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
00425
00426 /**
00427   * @}
00428   */
00429
00430
00431 /* Exported types ------------------------------------------------------------*/
00432 #if defined(USE_FULL_LL_DRIVER)
00433 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
00434   * @{
00435   */
00436
00437 /**
00438   * @brief  Structure definition of some features of ADC common parameters
00439   *         and multimode
00440   *         (all ADC instances belonging to the same ADC common instance).
00441   * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
00442   *         is conditioned to ADC instances state (all ADC instances
00443   *         sharing the same ADC common instance):
00444   *         All ADC instances sharing the same ADC common instance must be
00445   *         disabled.
00446   */
00447 typedef struct
00448 {
00449   uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.
00450                                              This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
00451                                              @note On this STM32 serie, if ADC group injected is used, some
00452                                                    clock ratio constraints between ADC clock and AHB clock
00453                                                    must be respected. Refer to reference manual.
00454
00455                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
00456
00457 #if defined(ADC_MULTIMODE_SUPPORT)
00458   uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
00459                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
00460
00461                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
00462
00463   uint32_t MultiDMATransfer;            /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
00464                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
00465
00466                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
00467
00468   uint32_t MultiTwoSamplingDelay;       /*!< Set ADC multimode delay between 2 sampling phases.
00469                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
00470
00471                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
00472 #endif /* ADC_MULTIMODE_SUPPORT */
00473
00474 } LL_ADC_CommonInitTypeDef;
00475
00476 /**
00477   * @brief  Structure definition of some features of ADC instance.
00478   * @note   These parameters have an impact on ADC scope: ADC instance.
00479   *         Affects both group regular and group injected (availability
00480   *         of ADC group injected depends on STM32 families).
00481   *         Refer to corresponding unitary functions into
00482   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
00483   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00484   *         is conditioned to ADC state:
00485   *         ADC instance must be disabled.
00486   *         This condition is applied to all ADC features, for efficiency
00487   *         and compatibility over all STM32 families. However, the different
00488   *         features can be set under different ADC state conditions
00489   *         (setting possible with ADC enabled without conversion on going,
00490   *         ADC enabled with conversion on going, ...)
00491   *         Each feature can be updated afterwards with a unitary function
00492   *         and potentially with ADC in a different state than disabled,
00493   *         refer to description of each function for setting
00494   *         conditioned to ADC state.
00495   */
00496 typedef struct
00497 {
00498   uint32_t Resolution;                  /*!< Set ADC resolution.
00499                                              This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
00500
00501                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
00502
00503   uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.
00504                                              This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
00505
00506                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
00507
00508   uint32_t LowPowerMode;                /*!< Set ADC low power mode.
00509                                              This parameter can be a value of @ref ADC_LL_EC_LP_MODE
00510
00511                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
00512
00513 } LL_ADC_InitTypeDef;
00514
00515 /**
00516   * @brief  Structure definition of some features of ADC group regular.
00517   * @note   These parameters have an impact on ADC scope: ADC group regular.
00518   *         Refer to corresponding unitary functions into
00519   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00520   *         (functions with prefix "REG").
00521   * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
00522   *         is conditioned to ADC state:
00523   *         ADC instance must be disabled.
00524   *         This condition is applied to all ADC features, for efficiency
00525   *         and compatibility over all STM32 families. However, the different
00526   *         features can be set under different ADC state conditions
00527   *         (setting possible with ADC enabled without conversion on going,
00528   *         ADC enabled with conversion on going, ...)
00529   *         Each feature can be updated afterwards with a unitary function
00530   *         and potentially with ADC in a different state than disabled,
00531   *         refer to description of each function for setting
00532   *         conditioned to ADC state.
00533   */
00534 typedef struct
00535 {
00536   uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
00537                                              This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
00538                                              @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
00539                                                    (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
00540                                                    In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
00541
00542                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
00543
00544   uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.
00545                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
00546
00547                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
00548
00549   uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
00550                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
00551                                              @note This parameter has an effect only if group regular sequencer is enabled
00552                                                    (scan length of 2 ranks or more).
00553
00554                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
00555
00556   uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
00557                                              This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
00558                                              Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
00559
00560                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
00561
00562   uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
00563                                              This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
00564
00565                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
00566
00567   uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:
00568                                              data preserved or overwritten.
00569                                              This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
00570
00571                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
00572
00573 } LL_ADC_REG_InitTypeDef;
00574
00575 /**
00576   * @brief  Structure definition of some features of ADC group injected.
00577   * @note   These parameters have an impact on ADC scope: ADC group injected.
00578   *         Refer to corresponding unitary functions into
00579   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00580   *         (functions with prefix "INJ").
00581   * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()
00582   *         is conditioned to ADC state:
00583   *         ADC instance must be disabled.
00584   *         This condition is applied to all ADC features, for efficiency
00585   *         and compatibility over all STM32 families. However, the different
00586   *         features can be set under different ADC state conditions
00587   *         (setting possible with ADC enabled without conversion on going,
00588   *         ADC enabled with conversion on going, ...)
00589   *         Each feature can be updated afterwards with a unitary function
00590   *         and potentially with ADC in a different state than disabled,
00591   *         refer to description of each function for setting
00592   *         conditioned to ADC state.
00593   */
00594 typedef struct
00595 {
00596   uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
00597                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
00598                                              @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
00599                                                    (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
00600                                                    In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
00601
00602                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
00603
00604   uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.
00605                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
00606
00607                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
00608
00609   uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
00610                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
00611                                              @note This parameter has an effect only if group injected sequencer is enabled
00612                                                    (scan length of 2 ranks or more).
00613
00614                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
00615
00616   uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
00617                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
00618                                              Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
00619
00620                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
00621
00622 } LL_ADC_INJ_InitTypeDef;
00623
00624 /**
00625   * @}
00626   */
00627 #endif /* USE_FULL_LL_DRIVER */
00628
00629 /* Exported constants --------------------------------------------------------*/
00630 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
00631   * @{
00632   */
00633
00634 /** @defgroup ADC_LL_EC_FLAG ADC flags
00635   * @brief    Flags defines which can be used with LL_ADC_ReadReg function
00636   * @{
00637   */
00638 #define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */
00639 #define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary conversion */
00640 #define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence conversions */
00641 #define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */
00642 #define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */
00643 #define LL_ADC_FLAG_JEOC                   ADC_ISR_JEOC       /*!< ADC flag ADC group injected end of unitary conversion */
00644 #define LL_ADC_FLAG_JEOS                   ADC_ISR_JEOS       /*!< ADC flag ADC group injected end of sequence conversions */
00645 #define LL_ADC_FLAG_JQOVF                  ADC_ISR_JQOVF      /*!< ADC flag ADC group injected contexts queue overflow */
00646 #define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */
00647 #define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */
00648 #define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */
00649 #if defined(ADC_MULTIMODE_SUPPORT)
00650 #define LL_ADC_FLAG_ADRDY_MST              ADC_CSR_ADRDY_MST  /*!< ADC flag ADC multimode master instance ready */
00651 #define LL_ADC_FLAG_ADRDY_SLV              ADC_CSR_ADRDY_SLV  /*!< ADC flag ADC multimode slave instance ready */
00652 #define LL_ADC_FLAG_EOC_MST                ADC_CSR_EOC_MST    /*!< ADC flag ADC multimode master group regular end of unitary conversion */
00653 #define LL_ADC_FLAG_EOC_SLV                ADC_CSR_EOC_SLV    /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
00654 #define LL_ADC_FLAG_EOS_MST                ADC_CSR_EOS_MST    /*!< ADC flag ADC multimode master group regular end of sequence conversions */
00655 #define LL_ADC_FLAG_EOS_SLV                ADC_CSR_EOS_SLV    /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
00656 #define LL_ADC_FLAG_OVR_MST                ADC_CSR_OVR_MST    /*!< ADC flag ADC multimode master group regular overrun */
00657 #define LL_ADC_FLAG_OVR_SLV                ADC_CSR_OVR_SLV    /*!< ADC flag ADC multimode slave group regular overrun */
00658 #define LL_ADC_FLAG_EOSMP_MST              ADC_CSR_EOSMP_MST  /*!< ADC flag ADC multimode master group regular end of sampling phase */
00659 #define LL_ADC_FLAG_EOSMP_SLV              ADC_CSR_EOSMP_SLV  /*!< ADC flag ADC multimode slave group regular end of sampling phase */
00660 #define LL_ADC_FLAG_JEOC_MST               ADC_CSR_JEOC_MST   /*!< ADC flag ADC multimode master group injected end of unitary conversion */
00661 #define LL_ADC_FLAG_JEOC_SLV               ADC_CSR_JEOC_SLV   /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
00662 #define LL_ADC_FLAG_JEOS_MST               ADC_CSR_JEOS_MST   /*!< ADC flag ADC multimode master group injected end of sequence conversions */
00663 #define LL_ADC_FLAG_JEOS_SLV               ADC_CSR_JEOS_SLV   /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
00664 #define LL_ADC_FLAG_JQOVF_MST              ADC_CSR_JQOVF_MST  /*!< ADC flag ADC multimode master group injected contexts queue overflow */
00665 #define LL_ADC_FLAG_JQOVF_SLV              ADC_CSR_JQOVF_SLV  /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
00666 #define LL_ADC_FLAG_AWD1_MST               ADC_CSR_AWD1_MST   /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
00667 #define LL_ADC_FLAG_AWD1_SLV               ADC_CSR_AWD1_SLV   /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
00668 #define LL_ADC_FLAG_AWD2_MST               ADC_CSR_AWD2_MST   /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
00669 #define LL_ADC_FLAG_AWD2_SLV               ADC_CSR_AWD2_SLV   /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
00670 #define LL_ADC_FLAG_AWD3_MST               ADC_CSR_AWD3_MST   /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
00671 #define LL_ADC_FLAG_AWD3_SLV               ADC_CSR_AWD3_SLV   /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
00672 #endif
00673 /**
00674   * @}
00675   */
00676
00677 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
00678   * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
00679   * @{
00680   */
00681 #define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */
00682 #define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion */
00683 #define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence conversions */
00684 #define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */
00685 #define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling phase */
00686 #define LL_ADC_IT_JEOC                     ADC_IER_JEOCIE     /*!< ADC interruption ADC group injected end of unitary conversion */
00687 #define LL_ADC_IT_JEOS                     ADC_IER_JEOSIE     /*!< ADC interruption ADC group injected end of sequence conversions */
00688 #define LL_ADC_IT_JQOVF                    ADC_IER_JQOVFIE    /*!< ADC interruption ADC group injected contexts queue overflow */
00689 #define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watchdog 1 */
00690 #define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watchdog 2 */
00691 #define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watchdog 3 */
00692 /**
00693   * @}
00694   */
00695
00696 /** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
00697   * @{
00698   */
00699 /* List of ADC registers intended to be used (most commonly) with             */
00700 /* DMA transfer.                                                              */
00701 /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
00702 #define LL_ADC_DMA_REG_REGULAR_DATA          ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
00703 #if defined(ADC_MULTIMODE_SUPPORT)
00704 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI    ((uint32_t)0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
00705 #endif
00706 /**
00707   * @}
00708   */
00709
00710 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
00711   * @{
00712   */
00713 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CCR_CKMODE_0)                                    /*!< ADC synchronous clock derived from AHB clock without prescaler */
00714 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CCR_CKMODE_1                   )                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
00715 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
00716 #define LL_ADC_CLOCK_ASYNC_DIV1            ((uint32_t)0x00000000U)                               /*!< ADC asynchronous clock without prescaler */
00717 /**
00718   * @}
00719   */
00720
00721 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
00722   * @{
00723   */
00724 /* Note: Other measurement paths to internal channels may be available        */
00725 /*       (connections to other peripherals).                                  */
00726 /*       If they are not listed below, they do not require any specific       */
00727 /*       path enable. In this case, Access to measurement path is done        */
00728 /*       only by selecting the corresponding ADC internal channel.            */
00729 #define LL_ADC_PATH_INTERNAL_NONE          ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */
00730 #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to internal channel VrefInt */
00731 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSEN)         /*!< ADC measurement path to internal channel temperature sensor */
00732 #define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATEN)       /*!< ADC measurement path to internal channel Vbat */
00733 /**
00734   * @}
00735   */
00736
00737 /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
00738   * @{
00739   */
00740 #define LL_ADC_RESOLUTION_12B              ((uint32_t)0x00000000U)             /*!< ADC resolution 12 bits */
00741 #define LL_ADC_RESOLUTION_10B              (                 ADC_CFGR_RES_0)   /*!< ADC resolution 10 bits */
00742 #define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_1                 )   /*!< ADC resolution  8 bits */
00743 #define LL_ADC_RESOLUTION_6B               (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)   /*!< ADC resolution  6 bits */
00744 /**
00745   * @}
00746   */
00747
00748 /** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
00749   * @{
00750   */
00751 #define LL_ADC_DATA_ALIGN_RIGHT            ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
00752 #define LL_ADC_DATA_ALIGN_LEFT             (ADC_CFGR_ALIGN)       /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
00753 /**
00754   * @}
00755   */
00756
00757 /** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode
00758   * @{
00759   */
00760 #define LL_ADC_LP_MODE_NONE                ((uint32_t)0x00000000U)              /*!< No ADC low power mode activated */
00761 #define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR_AUTDLY)                   /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
00762 /**
00763   * @}
00764   */
00765
00766 /** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset number
00767   * @{
00768   */
00769 #define LL_ADC_OFFSET_1                    ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00770 #define LL_ADC_OFFSET_2                    ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00771 #define LL_ADC_OFFSET_3                    ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00772 #define LL_ADC_OFFSET_4                    ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00773 /**
00774   * @}
00775   */
00776
00777 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
00778   * @{
00779   */
00780 #define LL_ADC_OFFSET_DISABLE              ((uint32_t)0x00000000U)/*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
00781 #define LL_ADC_OFFSET_ENABLE               (ADC_OFR1_OFFSET1_EN)  /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
00782 /**
00783   * @}
00784   */
00785
00786 /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
00787   * @{
00788   */
00789 #define LL_ADC_GROUP_REGULAR               ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
00790 #define LL_ADC_GROUP_INJECTED              ((uint32_t)0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/
00791 #define LL_ADC_GROUP_REGULAR_INJECTED      ((uint32_t)0x00000003U) /*!< ADC both groups regular and injected */
00792 /**
00793   * @}
00794   */
00795
00796 /** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
00797   * @{
00798   */
00799 #define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP  | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
00800 #define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP  | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
00801 #define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP  | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
00802 #define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP  | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
00803 #define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP  | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
00804 #define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP  | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
00805 #define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP  | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
00806 #define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP  | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
00807 #define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP  | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
00808 #define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP  | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
00809 #define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
00810 #define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
00811 #define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
00812 #define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
00813 #define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
00814 #define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
00815 #define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
00816 #define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
00817 #define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
00818 #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F3, ADC channel available only on all ADC instances, but only one ADC instance is allowed to be connected to VrefInt at the same time. */
00819 #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F3, ADC channel available only on ADC instance: ADC1. */
00820 #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F3, ADC channel available only on ADC instance: ADC1. */
00821 #if defined(OPAMP1_CSR_OPAMP1EN)
00822 #define LL_ADC_CHANNEL_VOPAMP1             (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On STM32F3, ADC channel available only on ADC instance: ADC1. */
00823 #endif
00824 #if defined(OPAMP2_CSR_OPAMP2EN)
00825 #define LL_ADC_CHANNEL_VOPAMP2             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On STM32F3, ADC channel available only on ADC instance: ADC2. */
00826 #endif
00827 #if defined(OPAMP3_CSR_OPAMP3EN)
00828 #define LL_ADC_CHANNEL_VOPAMP3             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On STM32F3, ADC channel available only on ADC instance: ADC3. */
00829 #endif
00830 #if defined(OPAMP4_CSR_OPAMP4EN)
00831 #define LL_ADC_CHANNEL_VOPAMP4             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP4 output. On STM32F3, ADC channel available only on ADC instance: ADC4. */
00832 #endif
00833 /**
00834   * @}
00835   */
00836
00837 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
00838   * @{
00839   */
00840 #define LL_ADC_REG_TRIG_SOFTWARE              ((uint32_t)0x00000000U)                                                                      /*!< ADC group regular conversion trigger internal: SW start. */
00841 #if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
00842 /* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for     */
00843 /* ADC instances ADCx available on the selected device)                       */
00844 /* Note: Literal without suffix "ADCxy" means that external trigger           */
00845 /*       is available on all ADC instances.                                   */
00846 /* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set   */
00847 /*       register SYSCFG_CFGR4. Refer to reference manual.                    */
00848 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12    (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                              /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00849 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12    (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00850 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3          (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00851 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12    (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00852 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12   (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
00853 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12    (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00854 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
00855 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12   (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
00856 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2        (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
00857 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
00858 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2        (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
00859 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12   (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
00860 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
00861 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12   (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
00862 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO        (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
00863 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12    (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                            /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00864 #if defined(STM32F303xE) || defined(STM32F398xx)
00865 #define LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12  (LL_ADC_REG_TRIG_EXT_TIM1_CH3)                                                               /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO. Trigger edge set to rising edge (default setting). */
00866 #define LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12 (LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12)                                                         /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */
00867 #define LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12   (LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12)                                                         /*!< ADC group regular conversion trigger from external IP: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00868 #define LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12   (LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12)                                                        /*!< ADC group regular conversion trigger from external IP: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00869 #define LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12   (LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12)                                                         /*!< ADC group regular conversion trigger from external IP: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00870 #endif /* STM32F303xE || STM32F398xx */
00871
00872 /* ADC group regular external triggers for ADC instances: ADC3, ADC4 (for     */
00873 /* ADC instances ADCx available on the selected device)                       */
00874 /* Note: Literal without suffix "ADCxy" means that external trigger           */
00875 /*       is available on all ADC instances.                                   */
00876 /* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set   */
00877 /*       register SYSCFG_CFGR4. Refer to reference manual.                    */
00878 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34    (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                              /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00879 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34    (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00880 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3          (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00881 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34    (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00882 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34  (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
00883 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34  (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: external interrupt line 2. Trigger edge set to rising edge (default setting). */
00884 #define LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34    (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00885 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34  (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
00886 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2        (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
00887 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
00888 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2        (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
00889 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34  (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
00890 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
00891 #define LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34   (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
00892 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO        (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
00893 #define LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34    (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                            /*!< ADC group regular conversion trigger from external IP: TIM2 CCx. Trigger edge set to rising edge (default setting). */
00894 #if defined(STM32F303xE) || defined(STM32F398xx)
00895 #define LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC34  (LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34)                                                       /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO. Trigger edge set to rising edge (default setting). */
00896 #define LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34 (LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34)                                                         /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */
00897 #define LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34   (LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34)                                                         /*!< ADC group regular conversion trigger from external IP: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00898 #endif /* STM32F303xE || STM32F398xx */
00899
00900 #elif defined(STM32F303x8) || defined(STM32F328xx)
00901 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1          (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                              /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00902 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2          (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00903 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3          (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00904 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2          (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00905 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO         (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
00906 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4          (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00907 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
00908 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO         (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
00909 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
00910 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2        (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
00911 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
00912 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
00913 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
00914 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO        (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
00915 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4          (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                            /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00916
00917 #elif defined(STM32F334x8)
00918 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1          (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                              /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00919 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2          (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00920 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3          (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00921 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2          (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00922 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO         (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
00923 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
00924 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1        (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: HRTIM TRG1. Trigger edge set to rising edge (default setting). */
00925 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3        (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: HRTIM TRG3. Trigger edge set to rising edge (default setting). */
00926 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
00927 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2        (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
00928 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
00929 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
00930 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO        (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
00931 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4          (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                            /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00932
00933 #elif defined(STM32F302xC) || defined(STM32F302xE)
00934 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1          (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                              /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00935 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2          (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00936 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3          (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00937 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2          (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00938 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO         (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
00939 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4          (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00940 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
00941 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
00942 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2        (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
00943 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
00944 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
00945 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
00946 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO        (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
00947 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4          (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                            /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00948
00949 #elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00950 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1          (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                              /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00951 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2          (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00952 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3          (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00953 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
00954 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
00955 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2        (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
00956 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
00957 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO         (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
00958 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO        (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
00959 #endif
00960 /**
00961   * @}
00962   */
00963
00964 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
00965   * @{
00966   */
00967 #define LL_ADC_REG_TRIG_EXT_RISING         (                   ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to rising edge */
00968 #define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR_EXTEN_1                   )   /*!< ADC group regular conversion trigger polarity set to falling edge */
00969 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
00970 /**
00971   * @}
00972   */
00973
00974 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
00975 * @{
00976 */
00977 #define LL_ADC_REG_CONV_SINGLE             ((uint32_t)0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */
00978 #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR_CONT)         /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
00979 /**
00980   * @}
00981   */
00982
00983 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
00984   * @{
00985   */
00986 #define LL_ADC_REG_DMA_TRANSFER_NONE       ((uint32_t)0x00000000U)              /*!< ADC conversions are not transferred by DMA */
00987 #define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                  ADC_CFGR_DMAEN)   /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
00988 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)   /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
00989 /**
00990   * @}
00991   */
00992
00993 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
00994 * @{
00995 */
00996 #define LL_ADC_REG_OVR_DATA_PRESERVED      ((uint32_t)0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */
00997 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR_OVRMOD)      /*!< ADC group regular behavior in case of overrun: data overwritten */
00998 /**
00999   * @}
01000   */
01001
01002 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
01003   * @{
01004   */
01005 #define LL_ADC_REG_SEQ_SCAN_DISABLE        ((uint32_t)0x00000000U)                                     /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
01006 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
01007 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
01008 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
01009 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
01010 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
01011 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
01012 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
01013 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
01014 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
01015 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
01016 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
01017 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
01018 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
01019 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
01020 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
01021 /**
01022   * @}
01023   */
01024
01025 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
01026   * @{
01027   */
01028 #define LL_ADC_REG_SEQ_DISCONT_DISABLE     ((uint32_t)0x00000000U)                                                          /*!< ADC group regular sequencer discontinuous mode disable */
01029 #define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                               ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
01030 #define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                          ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
01031 #define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                     ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
01032 #define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                     ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
01033 #define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CFGR_DISCNUM_2                                           | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
01034 #define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CFGR_DISCNUM_2                      | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
01035 #define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
01036 #define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
01037 /**
01038   * @}
01039   */
01040
01041 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
01042   * @{
01043   */
01044 #define LL_ADC_REG_RANK_1                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */
01045 #define LL_ADC_REG_RANK_2                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */
01046 #define LL_ADC_REG_RANK_3                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */
01047 #define LL_ADC_REG_RANK_4                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */
01048 #define LL_ADC_REG_RANK_5                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */
01049 #define LL_ADC_REG_RANK_6                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */
01050 #define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */
01051 #define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */
01052 #define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */
01053 #define LL_ADC_REG_RANK_10                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
01054 #define LL_ADC_REG_RANK_11                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
01055 #define LL_ADC_REG_RANK_12                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
01056 #define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
01057 #define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
01058 #define LL_ADC_REG_RANK_15                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
01059 #define LL_ADC_REG_RANK_16                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
01060 /**
01061   * @}
01062   */
01063
01064 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source
01065   * @{
01066   */
01067 #define LL_ADC_INJ_TRIG_SOFTWARE              ((uint32_t)0x00000000U)                                                                        /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */
01068 #if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
01069 /* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for    */
01070 /* ADC instances ADCx available on the selected device)                       */
01071 /* Note: Literal without suffix "ADCxy" means that external trigger           */
01072 /*       is available on all ADC instances.                                   */
01073 /* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set   */
01074 /*       register SYSCFG_CFGR4. Refer to reference manual.                    */
01075 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO         (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
01076 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4          (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01077 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12   (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
01078 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12    (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01079 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12    (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01080 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12   (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
01081 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
01082 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01083 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2        (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
01084 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO         (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
01085 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2        (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
01086 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12    (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01087 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO         (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
01088 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12    (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01089 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12   (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
01090 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO        (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                             /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
01091 #if defined(STM32F303xE) || defined(STM32F398xx)
01092 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12  (LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12)                                                           /*!< ADC group injected conversion trigger from external IP: TIM20 TRG0. Trigger edge set to rising edge (default setting). */
01093 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12)                                                        /*!< ADC group injected conversion trigger from external IP: TIM20 TRG02. Trigger edge set to rising edge (default setting). */
01094 #define LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12   (LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12)                                                           /*!< ADC group injected conversion trigger from external IP: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01095 #endif /* STM32F303xE || STM32F398xx */
01096
01097 /* ADC group injected external triggers for ADC instances: ADC3, ADC4 (for    */
01098 /* ADC instances ADCx available on the selected device)                       */
01099 /* Note: Literal without suffix "ADCxy" means that external trigger           */
01100 /*       is available on all ADC instances.                                   */
01101 /* Note: External triggers JEXT2 and JEXT5 are the same (TIM4_CH3 event).     */
01102 /*       JEXT2 is the main trigger, JEXT5 is kept as spare trigger for        */
01103 /*       future devices.                                                      */
01104 /* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set   */
01105 /*       register SYSCFG_CFGR4. Refer to reference manual.                    */
01106 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO         (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
01107 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4          (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01108 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34    (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01109 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34    (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01110 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34   (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01111 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01112 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34  (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
01113 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2        (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
01114 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO         (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
01115 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2        (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
01116 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34    (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01117 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO         (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
01118 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34  (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
01119 #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34   (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM7 TRG0. Trigger edge set to rising edge (default setting). */
01120 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO        (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                             /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
01121 #if defined(STM32F303xE) || defined(STM32F398xx)
01122 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34   (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM20 TRG0. Trigger edge set to rising edge (default setting). */
01123 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34  (LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34)                                                           /*!< ADC group injected conversion trigger from external IP: TIM20 TRG02. Trigger edge set to rising edge (default setting). */
01124 #define LL_ADC_INJ_TRIG_EXT_TIM20_CH2         (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                                                               /*!< ADC group injected conversion trigger from external IP: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01125 #endif /* STM32F303xE || STM32F398xx */
01126
01127 #elif defined(STM32F303x8) || defined(STM32F328xx)
01128 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO         (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
01129 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4          (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01130 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO         (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
01131 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1          (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01132 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4          (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01133 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO         (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
01134 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
01135 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4          (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01136 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2        (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
01137 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO         (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
01138 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2        (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
01139 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3          (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01140 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO         (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
01141 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1          (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01142 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO         (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
01143 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO        (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                             /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
01144
01145 #elif defined(STM32F334x8)
01146 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO         (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
01147 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4          (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01148 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO         (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
01149 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1          (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01150 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4          (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01151 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
01152 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2        (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
01153 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2        (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: HRTIM TRG2. Trigger edge set to rising edge (default setting). */
01154 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4        (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: HRTIM TRG4. Trigger edge set to rising edge (default setting). */
01155 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3          (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01156 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO         (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
01157 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1          (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01158 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO         (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
01159 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO        (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                             /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
01160
01161 #elif defined(STM32F302xC) || defined(STM32F302xE)
01162 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO         (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
01163 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4          (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01164 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO         (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
01165 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1          (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01166 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4          (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01167 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO         (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
01168 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
01169 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2        (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
01170 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3          (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01171 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO         (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
01172 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1          (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01173 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO         (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
01174 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO        (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                             /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
01175
01176 #elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
01177 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO         (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
01178 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4          (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01179 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
01180 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2        (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
01181 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO         (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
01182 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO        (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                             /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
01183 #endif
01184 /**
01185   * @}
01186   */
01187
01188 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge
01189   * @{
01190   */
01191 #define LL_ADC_INJ_TRIG_EXT_RISING         (                    ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
01192 #define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1                    ) /*!< ADC group injected conversion trigger polarity set to falling edge */
01193 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
01194 /**
01195   * @}
01196   */
01197
01198 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode
01199 * @{
01200 */
01201 #define LL_ADC_INJ_TRIG_INDEPENDENT        ((uint32_t)0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
01202 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)       /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
01203 /**
01204   * @}
01205   */
01206
01207 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE  ADC group injected - Context queue mode
01208   * @{
01209   */
01210 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE ((uint32_t)0x00000000U)/* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
01211 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY   (ADC_CFGR_JQM)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
01212 /**
01213   * @}
01214   */
01215
01216 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length
01217   * @{
01218   */
01219 #define LL_ADC_INJ_SEQ_SCAN_DISABLE        ((uint32_t)0x00000000U)         /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
01220 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
01221 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
01222 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
01223 /**
01224   * @}
01225   */
01226
01227 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode
01228   * @{
01229   */
01230 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE     ((uint32_t)0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */
01231 #define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CFGR_JDISCEN)     /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
01232 /**
01233   * @}
01234   */
01235
01236 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
01237   * @{
01238   */
01239 #define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
01240 #define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
01241 #define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
01242 #define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
01243 /**
01244   * @}
01245   */
01246
01247 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
01248   * @{
01249   */
01250 #define LL_ADC_SAMPLINGTIME_1CYCLE_5       (0x00000000U)                                               /*!< Sampling time 1.5 ADC clock cycle */
01251 #define LL_ADC_SAMPLINGTIME_2CYCLES_5      (                                        ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
01252 #define LL_ADC_SAMPLINGTIME_4CYCLES_5      (                    ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 4.5 ADC clock cycles */
01253 #define LL_ADC_SAMPLINGTIME_7CYCLES_5      (                    ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 7.5 ADC clock cycles */
01254 #define LL_ADC_SAMPLINGTIME_19CYCLES_5     (ADC_SMPR2_SMP10_2                                        ) /*!< Sampling time 19.5 ADC clock cycles */
01255 #define LL_ADC_SAMPLINGTIME_61CYCLES_5     (ADC_SMPR2_SMP10_2                     | ADC_SMPR2_SMP10_0) /*!< Sampling time 61.5 ADC clock cycles */
01256 #define LL_ADC_SAMPLINGTIME_181CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 181.5 ADC clock cycles */
01257 #define LL_ADC_SAMPLINGTIME_601CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 601.5 ADC clock cycles */
01258 /**
01259   * @}
01260   */
01261
01262 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
01263   * @{
01264   */
01265 #define LL_ADC_SINGLE_ENDED                (                  ADC_CALFACT_CALFACT_S)         /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
01266 #define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)         /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
01267 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
01268 /**
01269   * @}
01270   */
01271
01272 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
01273   * @{
01274   */
01275 #define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
01276 #define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
01277 #define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
01278 /**
01279   * @}
01280   */
01281
01282 /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
01283   * @{
01284   */
01285 #define LL_ADC_AWD_DISABLE                 ((uint32_t)0x00000000U)                                                                             /*!< ADC analog watchdog monitoring disabled */
01286 #define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK                                    | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
01287 #define LL_ADC_AWD_ALL_CHANNELS_INJ        (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN                                     ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
01288 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
01289 #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
01290 #define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
01291 #define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
01292 #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
01293 #define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
01294 #define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
01295 #define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
01296 #define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
01297 #define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
01298 #define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
01299 #define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
01300 #define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
01301 #define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
01302 #define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
01303 #define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
01304 #define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
01305 #define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
01306 #define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
01307 #define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
01308 #define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
01309 #define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
01310 #define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
01311 #define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
01312 #define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
01313 #define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
01314 #define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
01315 #define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
01316 #define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
01317 #define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
01318 #define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
01319 #define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
01320 #define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
01321 #define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
01322 #define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
01323 #define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
01324 #define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
01325 #define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
01326 #define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
01327 #define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
01328 #define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
01329 #define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
01330 #define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
01331 #define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
01332 #define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
01333 #define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
01334 #define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
01335 #define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
01336 #define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
01337 #define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
01338 #define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
01339 #define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
01340 #define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
01341 #define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
01342 #define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
01343 #define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
01344 #define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
01345 #define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
01346 #define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
01347 #define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
01348 #define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
01349 #define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
01350 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
01351 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
01352 #define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
01353 #define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
01354 #define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
01355 #if defined(OPAMP1_CSR_OPAMP1EN)
01356 #define LL_ADC_AWD_CH_VOPAMP1_REG          ((LL_ADC_CHANNEL_VOPAMP1    & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
01357 #define LL_ADC_AWD_CH_VOPAMP1_INJ          ((LL_ADC_CHANNEL_VOPAMP1    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
01358 #define LL_ADC_AWD_CH_VOPAMP1_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP1    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
01359 #endif
01360 #if defined(OPAMP2_CSR_OPAMP2EN)
01361 #define LL_ADC_AWD_CH_VOPAMP2_REG          ((LL_ADC_CHANNEL_VOPAMP2    & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
01362 #define LL_ADC_AWD_CH_VOPAMP2_INJ          ((LL_ADC_CHANNEL_VOPAMP2    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
01363 #define LL_ADC_AWD_CH_VOPAMP2_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP2    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
01364 #endif
01365 #if defined(OPAMP3_CSR_OPAMP3EN)
01366 #define LL_ADC_AWD_CH_VOPAMP3_REG          ((LL_ADC_CHANNEL_VOPAMP3    & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
01367 #define LL_ADC_AWD_CH_VOPAMP3_INJ          ((LL_ADC_CHANNEL_VOPAMP3    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
01368 #define LL_ADC_AWD_CH_VOPAMP3_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP3    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
01369 #endif
01370 #if defined(OPAMP4_CSR_OPAMP4EN)
01371 #define LL_ADC_AWD_CH_VOPAMP4_REG          ((LL_ADC_CHANNEL_VOPAMP4    & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
01372 #define LL_ADC_AWD_CH_VOPAMP4_INJ          ((LL_ADC_CHANNEL_VOPAMP4    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
01373 #define LL_ADC_AWD_CH_VOPAMP4_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP4    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
01374 #endif
01375 /**
01376   * @}
01377   */
01378
01379 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
01380   * @{
01381   */
01382 #define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_TR1_HT1              ) /*!< ADC analog watchdog threshold high */
01383 #define LL_ADC_AWD_THRESHOLD_LOW           (              ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
01384 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
01385 /**
01386   * @}
01387   */
01388
01389 #if defined(ADC_MULTIMODE_SUPPORT)
01390 /** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode
01391   * @{
01392   */
01393 #define LL_ADC_MULTI_INDEPENDENT           ((uint32_t)0x00000000U)                                             /*!< ADC dual mode disabled (ADC independent mode) */
01394 #define LL_ADC_MULTI_DUAL_REG_SIMULT       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: group regular simultaneous */
01395 #define LL_ADC_MULTI_DUAL_REG_INTERL       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
01396 #define LL_ADC_MULTI_DUAL_INJ_SIMULT       (                 ADC_CCR_DUAL_2                  | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
01397 #define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_DUAL_3                                   | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
01398 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (                                                   ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
01399 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (                                  ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
01400 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (                                  ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
01401 /**
01402   * @}
01403   */
01404
01405 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER  Multimode - DMA transfer
01406   * @{
01407   */
01408 #define LL_ADC_MULTI_REG_DMA_EACH_ADC        ((uint32_t)0x00000000U)                            /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
01409 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (                 ADC_CCR_MDMA_1                 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */
01410 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B   (                 ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */
01411 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1                 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */
01412 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B   (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */
01413 /**
01414   * @}
01415   */
01416
01417 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
01418   * @{
01419   */
01420 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE   ((uint32_t)0x00000000U)                                                 /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
01421 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES  (                                                      ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
01422 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES  (                                    ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
01423 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES  (                                    ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
01424 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES  (                  ADC_CCR_DELAY_2                                    ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
01425 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (                  ADC_CCR_DELAY_2                   | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
01426 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
01427 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
01428 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
01429 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3                                     | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
01430 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
01431 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
01432 /**
01433   * @}
01434   */
01435
01436 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave
01437   * @{
01438   */
01439 #define LL_ADC_MULTI_MASTER                (                    ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
01440 #define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV                    ) /*!< In multimode, selection among several ADC instances: ADC slave */
01441 #define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
01442 /**
01443   * @}
01444   */
01445
01446 #endif /* ADC_MULTIMODE_SUPPORT */
01447
01448
01449 /** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
01450   * @note   Only ADC IP HW delays are defined in ADC LL driver driver,
01451   *         not timeout values.
01452   *         For details on delays values, refer to descriptions in source code
01453   *         above each literal definition.
01454   * @{
01455   */
01456
01457 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */
01458 /*       not timeout values.                                                  */
01459 /*       Timeout values for ADC operations are dependent to device clock      */
01460 /*       configuration (system clock versus ADC clock),                       */
01461 /*       and therefore must be defined in user application.                   */
01462 /*       Indications for estimation of ADC timeout delays, for this           */
01463 /*       STM32 serie:                                                         */
01464 /*       - ADC calibration time: maximum delay is 112/fADC.                   */
01465 /*         (refer to device datasheet, parameter "tCAL")                      */
01466 /*       - ADC enable time: maximum delay is 1 conversion cycle.              */
01467 /*         (refer to device datasheet, parameter "tSTAB")                     */
01468 /*       - ADC disable time: maximum delay should be a few ADC clock cycles   */
01469 /*       - ADC stop conversion time: maximum delay should be a few ADC clock  */
01470 /*         cycles                                                             */
01471 /*       - ADC conversion time: duration depending on ADC clock and ADC       */
01472 /*         configuration.                                                     */
01473 /*         (refer to device reference manual, section "Timing")               */
01474
01475 /* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */
01476 /* Delay set to maximum value (refer to device datasheet,                     */
01477 /* parameter "tADCVREG_STUP").                                                */
01478 /* Unit: us                                                                   */
01479 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ((uint32_t)  10U)  /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
01480
01481 /* Delay for internal voltage reference stabilization time.                   */
01482 /* Delay set to maximum value (refer to device datasheet,                     */
01483 /* parameter "tstart_vrefint").                                               */
01484 /* Unit: us                                                                   */
01485 #define LL_ADC_DELAY_VREFINT_STAB_US       ((uint32_t)  12U)  /*!< Delay for internal voltage reference stabilization time */
01486
01487 /* Delay for temperature sensor stabilization time.                           */
01488 /* Literal set to maximum value (refer to device datasheet,                   */
01489 /* parameter "tSTART").                                                       */
01490 /* Unit: us                                                                   */
01491 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US    ((uint32_t) 120U)  /*!< Delay for temperature sensor stabilization time */
01492
01493 /* Delay required between ADC end of calibration and ADC enable.              */
01494 /* Note: On this STM32 serie, a minimum number of ADC clock cycles            */
01495 /*       are required between ADC end of calibration and ADC enable.          */
01496 /*       Wait time can be computed in user application by waiting for the     */
01497 /*       equivalent number of CPU cycles, by taking into account              */
01498 /*       ratio of CPU clock versus ADC clock prescalers.                      */
01499 /* Unit: ADC clock cycles.                                                    */
01500 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 4U)  /*!< Delay required between ADC end of calibration and ADC enable */
01501
01502 /**
01503   * @}
01504   */
01505
01506 /**
01507   * @}
01508   */
01509
01510
01511 /* Exported macro ------------------------------------------------------------*/
01512 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
01513   * @{
01514   */
01515
01516 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
01517   * @{
01518   */
01519
01520 /**
01521   * @brief  Write a value in ADC register
01522   * @param  __INSTANCE__ ADC Instance
01523   * @param  __REG__ Register to be written
01524   * @param  __VALUE__ Value to be written in the register
01525   * @retval None
01526   */
01527 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
01528
01529 /**
01530   * @brief  Read a value in ADC register
01531   * @param  __INSTANCE__ ADC Instance
01532   * @param  __REG__ Register to be read
01533   * @retval Register value
01534   */
01535 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
01536 /**
01537   * @}
01538   */
01539
01540 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
01541   * @{
01542   */
01543
01544 /**
01545   * @brief  Helper macro to get ADC channel number in decimal format
01546   *         from literals LL_ADC_CHANNEL_x.
01547   * @note   Example:
01548   *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
01549   *           will return decimal number "4".
01550   * @note   The input can be a value from functions where a channel
01551   *         number is returned, either defined with number
01552   *         or with bitfield (only one bit must be set).
01553   * @param  __CHANNEL__ This parameter can be one of the following values:
01554   *         @arg @ref LL_ADC_CHANNEL_0
01555   *         @arg @ref LL_ADC_CHANNEL_1
01556   *         @arg @ref LL_ADC_CHANNEL_2
01557   *         @arg @ref LL_ADC_CHANNEL_3
01558   *         @arg @ref LL_ADC_CHANNEL_4
01559   *         @arg @ref LL_ADC_CHANNEL_5
01560   *         @arg @ref LL_ADC_CHANNEL_6
01561   *         @arg @ref LL_ADC_CHANNEL_7
01562   *         @arg @ref LL_ADC_CHANNEL_8
01563   *         @arg @ref LL_ADC_CHANNEL_9
01564   *         @arg @ref LL_ADC_CHANNEL_10
01565   *         @arg @ref LL_ADC_CHANNEL_11
01566   *         @arg @ref LL_ADC_CHANNEL_12
01567   *         @arg @ref LL_ADC_CHANNEL_13
01568   *         @arg @ref LL_ADC_CHANNEL_14
01569   *         @arg @ref LL_ADC_CHANNEL_15
01570   *         @arg @ref LL_ADC_CHANNEL_16
01571   *         @arg @ref LL_ADC_CHANNEL_17
01572   *         @arg @ref LL_ADC_CHANNEL_18
01573   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
01574   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01575   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
01576   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
01577   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
01578   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
01579   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
01580   *
01581   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
01582   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
01583   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
01584   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
01585   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
01586   *             only one ADC instance is allowed to be connected to VrefInt at the same time.
01587   * @retval Value between Min_Data=0 and Max_Data=18
01588   */
01589 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \
01590   ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U)                                  \
01591     ? (                                                                                    \
01592        ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
01593       )                                                                                    \
01594       :                                                                                    \
01595       (                                                                                    \
01596        POSITION_VAL((__CHANNEL__))                                                         \
01597       )                                                                                    \
01598   )
01599
01600 /**
01601   * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
01602   *         from number in decimal format.
01603   * @note   Example:
01604   *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
01605   *           will return a data equivalent to "LL_ADC_CHANNEL_4".
01606   * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
01607   * @retval Returned value can be one of the following values:
01608   *         @arg @ref LL_ADC_CHANNEL_0
01609   *         @arg @ref LL_ADC_CHANNEL_1
01610   *         @arg @ref LL_ADC_CHANNEL_2
01611   *         @arg @ref LL_ADC_CHANNEL_3
01612   *         @arg @ref LL_ADC_CHANNEL_4
01613   *         @arg @ref LL_ADC_CHANNEL_5
01614   *         @arg @ref LL_ADC_CHANNEL_6
01615   *         @arg @ref LL_ADC_CHANNEL_7
01616   *         @arg @ref LL_ADC_CHANNEL_8
01617   *         @arg @ref LL_ADC_CHANNEL_9
01618   *         @arg @ref LL_ADC_CHANNEL_10
01619   *         @arg @ref LL_ADC_CHANNEL_11
01620   *         @arg @ref LL_ADC_CHANNEL_12
01621   *         @arg @ref LL_ADC_CHANNEL_13
01622   *         @arg @ref LL_ADC_CHANNEL_14
01623   *         @arg @ref LL_ADC_CHANNEL_15
01624   *         @arg @ref LL_ADC_CHANNEL_16
01625   *         @arg @ref LL_ADC_CHANNEL_17
01626   *         @arg @ref LL_ADC_CHANNEL_18
01627   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
01628   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01629   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
01630   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
01631   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
01632   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
01633   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
01634   *
01635   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
01636   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
01637   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
01638   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
01639   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
01640   *             only one ADC instance is allowed to be connected to VrefInt at the same time.\n
01641   *         (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
01642   *                         comparison with internal channel parameter to be done
01643   *                         using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01644   */
01645 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                          \
01646   (((__DECIMAL_NB__) <= 9U)                                                                                     \
01647     ? (                                                                                                         \
01648        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |        \
01649        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                       |        \
01650        (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))         \
01651       )                                                                                                         \
01652       :                                                                                                         \
01653       (                                                                                                         \
01654        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                              | \
01655        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                              | \
01656        (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
01657       )                                                                                                         \
01658   )
01659
01660 /**
01661   * @brief  Helper macro to determine whether the selected channel
01662   *         corresponds to literal definitions of driver.
01663   * @note   The different literal definitions of ADC channels are:
01664   *         - ADC internal channel:
01665   *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
01666   *         - ADC external channel (channel connected to a GPIO pin):
01667   *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
01668   * @note   The channel parameter must be a value defined from literal
01669   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01670   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01671   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
01672   *         must not be a value from functions where a channel number is
01673   *         returned from ADC registers,
01674   *         because internal and external channels share the same channel
01675   *         number in ADC registers. The differentiation is made only with
01676   *         parameters definitions of driver.
01677   * @param  __CHANNEL__ This parameter can be one of the following values:
01678   *         @arg @ref LL_ADC_CHANNEL_0
01679   *         @arg @ref LL_ADC_CHANNEL_1
01680   *         @arg @ref LL_ADC_CHANNEL_2
01681   *         @arg @ref LL_ADC_CHANNEL_3
01682   *         @arg @ref LL_ADC_CHANNEL_4
01683   *         @arg @ref LL_ADC_CHANNEL_5
01684   *         @arg @ref LL_ADC_CHANNEL_6
01685   *         @arg @ref LL_ADC_CHANNEL_7
01686   *         @arg @ref LL_ADC_CHANNEL_8
01687   *         @arg @ref LL_ADC_CHANNEL_9
01688   *         @arg @ref LL_ADC_CHANNEL_10
01689   *         @arg @ref LL_ADC_CHANNEL_11
01690   *         @arg @ref LL_ADC_CHANNEL_12
01691   *         @arg @ref LL_ADC_CHANNEL_13
01692   *         @arg @ref LL_ADC_CHANNEL_14
01693   *         @arg @ref LL_ADC_CHANNEL_15
01694   *         @arg @ref LL_ADC_CHANNEL_16
01695   *         @arg @ref LL_ADC_CHANNEL_17
01696   *         @arg @ref LL_ADC_CHANNEL_18
01697   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
01698   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01699   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
01700   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
01701   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
01702   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
01703   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
01704   *
01705   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
01706   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
01707   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
01708   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
01709   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
01710   *             only one ADC instance is allowed to be connected to VrefInt at the same time.
01711   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
01712   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
01713   */
01714 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
01715   (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
01716
01717 /**
01718   * @brief  Helper macro to convert a channel defined from parameter
01719   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01720   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01721   *         to its equivalent parameter definition of a ADC external channel
01722   *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
01723   * @note   The channel parameter can be, additionally to a value
01724   *         defined from parameter definition of a ADC internal channel
01725   *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
01726   *         a value defined from parameter definition of
01727   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
01728   *         or a value from functions where a channel number is returned
01729   *         from ADC registers.
01730   * @param  __CHANNEL__ This parameter can be one of the following values:
01731   *         @arg @ref LL_ADC_CHANNEL_0
01732   *         @arg @ref LL_ADC_CHANNEL_1
01733   *         @arg @ref LL_ADC_CHANNEL_2
01734   *         @arg @ref LL_ADC_CHANNEL_3
01735   *         @arg @ref LL_ADC_CHANNEL_4
01736   *         @arg @ref LL_ADC_CHANNEL_5
01737   *         @arg @ref LL_ADC_CHANNEL_6
01738   *         @arg @ref LL_ADC_CHANNEL_7
01739   *         @arg @ref LL_ADC_CHANNEL_8
01740   *         @arg @ref LL_ADC_CHANNEL_9
01741   *         @arg @ref LL_ADC_CHANNEL_10
01742   *         @arg @ref LL_ADC_CHANNEL_11
01743   *         @arg @ref LL_ADC_CHANNEL_12
01744   *         @arg @ref LL_ADC_CHANNEL_13
01745   *         @arg @ref LL_ADC_CHANNEL_14
01746   *         @arg @ref LL_ADC_CHANNEL_15
01747   *         @arg @ref LL_ADC_CHANNEL_16
01748   *         @arg @ref LL_ADC_CHANNEL_17
01749   *         @arg @ref LL_ADC_CHANNEL_18
01750   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
01751   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01752   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
01753   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
01754   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
01755   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
01756   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
01757   *
01758   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
01759   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
01760   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
01761   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
01762   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
01763   *             only one ADC instance is allowed to be connected to VrefInt at the same time.
01764   * @retval Returned value can be one of the following values:
01765   *         @arg @ref LL_ADC_CHANNEL_0
01766   *         @arg @ref LL_ADC_CHANNEL_1
01767   *         @arg @ref LL_ADC_CHANNEL_2
01768   *         @arg @ref LL_ADC_CHANNEL_3
01769   *         @arg @ref LL_ADC_CHANNEL_4
01770   *         @arg @ref LL_ADC_CHANNEL_5
01771   *         @arg @ref LL_ADC_CHANNEL_6
01772   *         @arg @ref LL_ADC_CHANNEL_7
01773   *         @arg @ref LL_ADC_CHANNEL_8
01774   *         @arg @ref LL_ADC_CHANNEL_9
01775   *         @arg @ref LL_ADC_CHANNEL_10
01776   *         @arg @ref LL_ADC_CHANNEL_11
01777   *         @arg @ref LL_ADC_CHANNEL_12
01778   *         @arg @ref LL_ADC_CHANNEL_13
01779   *         @arg @ref LL_ADC_CHANNEL_14
01780   *         @arg @ref LL_ADC_CHANNEL_15
01781   *         @arg @ref LL_ADC_CHANNEL_16
01782   *         @arg @ref LL_ADC_CHANNEL_17
01783   *         @arg @ref LL_ADC_CHANNEL_18
01784   */
01785 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
01786   ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
01787
01788 /**
01789   * @brief  Helper macro to determine whether the internal channel
01790   *         selected is available on the ADC instance selected.
01791   * @note   The channel parameter must be a value defined from parameter
01792   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01793   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01794   *         must not be a value defined from parameter definition of
01795   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
01796   *         or a value from functions where a channel number is
01797   *         returned from ADC registers,
01798   *         because internal and external channels share the same channel
01799   *         number in ADC registers. The differentiation is made only with
01800   *         parameters definitions of driver.
01801   * @param  __ADC_INSTANCE__ ADC instance
01802   * @param  __CHANNEL__ This parameter can be one of the following values:
01803   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
01804   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01805   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
01806   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
01807   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
01808   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
01809   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
01810   *
01811   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
01812   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
01813   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
01814   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
01815   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
01816   *             only one ADC instance is allowed to be connected to VrefInt at the same time.
01817   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
01818   *         Value "1" if the internal channel selected is available on the ADC instance selected.
01819   */
01820 #if defined (ADC1) && defined (ADC2) && defined (ADC3) && defined (ADC4)
01821 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01822   (((__ADC_INSTANCE__) == ADC1)                                                \
01823     ? (                                                                        \
01824        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                         \
01825        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                         \
01826        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)       ||                         \
01827        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)                               \
01828       )                                                                        \
01829       :                                                                        \
01830       ((__ADC_INSTANCE__) == ADC2)                                             \
01831       ? (                                                                      \
01832          ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) ||                          \
01833          ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)                             \
01834         )                                                                      \
01835         :                                                                      \
01836         ((__ADC_INSTANCE__) == ADC3)                                           \
01837         ? (                                                                    \
01838            ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) ||                        \
01839            ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3)                           \
01840           )                                                                    \
01841           :                                                                    \
01842           ((__ADC_INSTANCE__) == ADC4)                                         \
01843           ? (                                                                  \
01844              ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) ||                      \
01845              ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4)                         \
01846             )                                                                  \
01847             :                                                                  \
01848             (0U)                                                               \
01849   )
01850 #elif defined (ADC1) && defined (ADC2)
01851 #if defined(OPAMP1_CSR_OPAMP1EN) && defined(OPAMP2_CSR_OPAMP2EN)
01852 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01853   (((__ADC_INSTANCE__) == ADC1)                                                \
01854     ? (                                                                        \
01855        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                         \
01856        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                         \
01857        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)       ||                         \
01858        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)                               \
01859       )                                                                        \
01860       :                                                                        \
01861       ((__ADC_INSTANCE__) == ADC2)                                             \
01862       ? (                                                                      \
01863          ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                       \
01864          ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)                             \
01865         )                                                                      \
01866         :                                                                      \
01867         (0U)                                                                   \
01868   )
01869 #elif defined(OPAMP2_CSR_OPAMP2EN)
01870 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01871   (((__ADC_INSTANCE__) == ADC1)                                                \
01872     ? (                                                                        \
01873        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                         \
01874        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                         \
01875        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                  \
01876       )                                                                        \
01877       :                                                                        \
01878       ((__ADC_INSTANCE__) == ADC2)                                             \
01879       ? (                                                                      \
01880          ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                       \
01881          ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)                             \
01882         )                                                                      \
01883         :                                                                      \
01884         (0U)                                                                   \
01885   )
01886 #else
01887 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01888   (((__ADC_INSTANCE__) == ADC1)                                                \
01889     ? (                                                                        \
01890        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                         \
01891        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                         \
01892        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)       ||                         \
01893        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)                               \
01894       )                                                                        \
01895       :                                                                        \
01896       ((__ADC_INSTANCE__) == ADC2)                                             \
01897       ? (                                                                      \
01898          ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                             \
01899         )                                                                      \
01900         :                                                                      \
01901         (0U)                                                                   \
01902   )
01903 #endif
01904 #elif defined (ADC1)
01905 #if defined(OPAMP1_CSR_OPAMP1EN)
01906 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01907   (                                                                            \
01908     ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \
01909     ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                            \
01910     ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)       ||                            \
01911     ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)                                  \
01912   )
01913 #else
01914 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01915   (                                                                            \
01916     ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \
01917     ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                            \
01918     ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                     \
01919   )
01920 #endif
01921 #endif
01922
01923 /**
01924   * @brief  Helper macro to define ADC analog watchdog parameter:
01925   *         define a single channel to monitor with analog watchdog
01926   *         from sequencer channel and groups definition.
01927   * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
01928   *         Example:
01929   *           LL_ADC_SetAnalogWDMonitChannels(
01930   *             ADC1, LL_ADC_AWD1,
01931   *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
01932   * @param  __CHANNEL__ This parameter can be one of the following values:
01933   *         @arg @ref LL_ADC_CHANNEL_0
01934   *         @arg @ref LL_ADC_CHANNEL_1
01935   *         @arg @ref LL_ADC_CHANNEL_2
01936   *         @arg @ref LL_ADC_CHANNEL_3
01937   *         @arg @ref LL_ADC_CHANNEL_4
01938   *         @arg @ref LL_ADC_CHANNEL_5
01939   *         @arg @ref LL_ADC_CHANNEL_6
01940   *         @arg @ref LL_ADC_CHANNEL_7
01941   *         @arg @ref LL_ADC_CHANNEL_8
01942   *         @arg @ref LL_ADC_CHANNEL_9
01943   *         @arg @ref LL_ADC_CHANNEL_10
01944   *         @arg @ref LL_ADC_CHANNEL_11
01945   *         @arg @ref LL_ADC_CHANNEL_12
01946   *         @arg @ref LL_ADC_CHANNEL_13
01947   *         @arg @ref LL_ADC_CHANNEL_14
01948   *         @arg @ref LL_ADC_CHANNEL_15
01949   *         @arg @ref LL_ADC_CHANNEL_16
01950   *         @arg @ref LL_ADC_CHANNEL_17
01951   *         @arg @ref LL_ADC_CHANNEL_18
01952   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
01953   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01954   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
01955   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
01956   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
01957   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
01958   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
01959   *
01960   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
01961   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
01962   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
01963   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
01964   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
01965   *             only one ADC instance is allowed to be connected to VrefInt at the same time.\n
01966   *         (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
01967   *                         comparison with internal channel parameter to be done
01968   *                         using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01969   * @param  __GROUP__ This parameter can be one of the following values:
01970   *         @arg @ref LL_ADC_GROUP_REGULAR
01971   *         @arg @ref LL_ADC_GROUP_INJECTED
01972   *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
01973   * @retval Returned value can be one of the following values:
01974   *         @arg @ref LL_ADC_AWD_DISABLE
01975   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
01976   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
01977   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
01978   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
01979   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
01980   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
01981   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
01982   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
01983   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
01984   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
01985   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
01986   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
01987   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
01988   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
01989   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
01990   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
01991   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
01992   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
01993   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
01994   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
01995   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
01996   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
01997   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
01998   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
01999   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
02000   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
02001   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
02002   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
02003   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
02004   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
02005   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
02006   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
02007   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
02008   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
02009   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
02010   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
02011   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
02012   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
02013   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
02014   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
02015   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
02016   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
02017   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
02018   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
02019   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
02020   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
02021   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
02022   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
02023   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
02024   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
02025   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
02026   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
02027   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
02028   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
02029   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
02030   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
02031   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
02032   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
02033   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
02034   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
02035   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(5)
02036   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(5)
02037   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (5)
02038   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(1)
02039   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(1)
02040   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (1)
02041   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(1)
02042   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(1)
02043   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (1)
02044   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG          (0)(1)
02045   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ          (0)(1)
02046   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ         (1)
02047   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG          (0)(2)
02048   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ          (0)(2)
02049   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ         (2)
02050   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG          (0)(3)
02051   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ          (0)(3)
02052   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ         (3)
02053   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG          (0)(4)
02054   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ          (0)(4)
02055   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ         (4)
02056   *
02057   *         (0) On STM32F3, parameter available only on analog watchdog number: AWD1.\n
02058   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
02059   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
02060   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
02061   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
02062   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
02063   *             only one ADC instance is allowed to be connected to VrefInt at the same time.
02064   */
02065 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \
02066   (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
02067     ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                        \
02068       :                                                                                                   \
02069       ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                              \
02070        ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                    \
02071          :                                                                                                \
02072          (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  \
02073   )
02074
02075 /**
02076   * @brief  Helper macro to set the value of ADC analog watchdog threshold high
02077   *         or low in function of ADC resolution, when ADC resolution is
02078   *         different of 12 bits.
02079   * @note   To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
02080   *         or @ref LL_ADC_SetAnalogWDThresholds().
02081   *         Example, with a ADC resolution of 8 bits, to set the value of
02082   *         analog watchdog threshold high (on 8 bits):
02083   *           LL_ADC_SetAnalogWDThresholds
02084   *            (< ADCx param >,
02085   *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
02086   *            );
02087   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
02088   *         @arg @ref LL_ADC_RESOLUTION_12B
02089   *         @arg @ref LL_ADC_RESOLUTION_10B
02090   *         @arg @ref LL_ADC_RESOLUTION_8B
02091   *         @arg @ref LL_ADC_RESOLUTION_6B
02092   * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
02093   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
02094   */
02095 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
02096   ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
02097
02098 /**
02099   * @brief  Helper macro to get the value of ADC analog watchdog threshold high
02100   *         or low in function of ADC resolution, when ADC resolution is
02101   *         different of 12 bits.
02102   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
02103   *         Example, with a ADC resolution of 8 bits, to get the value of
02104   *         analog watchdog threshold high (on 8 bits):
02105   *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
02106   *            (LL_ADC_RESOLUTION_8B,
02107   *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
02108   *            );
02109   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
02110   *         @arg @ref LL_ADC_RESOLUTION_12B
02111   *         @arg @ref LL_ADC_RESOLUTION_10B
02112   *         @arg @ref LL_ADC_RESOLUTION_8B
02113   *         @arg @ref LL_ADC_RESOLUTION_6B
02114   * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
02115   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
02116   */
02117 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
02118   ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
02119
02120 /**
02121   * @brief  Helper macro to get the ADC analog watchdog threshold high
02122   *         or low from raw value containing both thresholds concatenated.
02123   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
02124   *         Example, to get analog watchdog threshold high from the register raw value:
02125   *           __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
02126   * @param  __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
02127   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
02128   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
02129   * @param  __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
02130   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
02131   */
02132 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__)       \
02133   (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW)
02134
02135 /**
02136   * @brief  Helper macro to set the ADC calibration value with both single ended
02137   *         and differential modes calibration factors concatenated.
02138   * @note   To be used with function @ref LL_ADC_SetCalibrationFactor().
02139   *         Example, to set calibration factors single ended to 0x55
02140   *         and differential ended to 0x2A:
02141   *           LL_ADC_SetCalibrationFactor(
02142   *             ADC1,
02143   *             __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
02144   * @param  __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
02145   * @param  __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
02146   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
02147   */
02148 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__)        \
02149   (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__))
02150
02151 #if defined(ADC_MULTIMODE_SUPPORT)
02152 /**
02153   * @brief  Helper macro to get the ADC multimode conversion data of ADC master
02154   *         or ADC slave from raw value with both ADC conversion data concatenated.
02155   * @note   This macro is intended to be used when multimode transfer by DMA
02156   *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
02157   *         In this case the transferred data need to processed with this macro
02158   *         to separate the conversion data of ADC master and ADC slave.
02159   * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
02160   *         @arg @ref LL_ADC_MULTI_MASTER
02161   *         @arg @ref LL_ADC_MULTI_SLAVE
02162   * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
02163   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
02164   */
02165 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \
02166   (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
02167 #endif
02168
02169 /**
02170   * @brief  Helper macro to select the ADC common instance
02171   *         to which is belonging the selected ADC instance.
02172   * @note   ADC common register instance can be used for:
02173   *         - Set parameters common to several ADC instances
02174   *         - Multimode (for devices with several ADC instances)
02175   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
02176   * @param  __ADCx__ ADC instance
02177   * @retval ADC common register instance
02178   */
02179 #if defined(ADC3) && defined(ADC4)
02180 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
02181   ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2))                              \
02182     ? (                                                                        \
02183        (ADC12_COMMON)                                                          \
02184       )                                                                        \
02185       :                                                                        \
02186       (                                                                        \
02187        (ADC34_COMMON)                                                          \
02188       )                                                                        \
02189   )
02190 #elif defined(ADC1) && defined(ADC2)
02191 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
02192   (ADC12_COMMON)
02193 #else
02194 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
02195   (ADC1_COMMON)
02196 #endif
02197
02198 /**
02199   * @brief  Helper macro to check if all ADC instances sharing the same
02200   *         ADC common instance are disabled.
02201   * @note   This check is required by functions with setting conditioned to
02202   *         ADC state:
02203   *         All ADC instances of the ADC common group must be disabled.
02204   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
02205   * @note   On devices with only 1 ADC common instance, parameter of this macro
02206   *         is useless and can be ignored (parameter kept for compatibility
02207   *         with devices featuring several ADC common instances).
02208   * @param  __ADCXY_COMMON__ ADC common instance
02209   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02210   * @retval Value "0" if all ADC instances sharing the same ADC common instance
02211   *         are disabled.
02212   *         Value "1" if at least one ADC instance sharing the same ADC common instance
02213   *         is enabled.
02214   */
02215 #if defined(ADC3) && defined(ADC4)
02216 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
02217   (((__ADCXY_COMMON__) == ADC12_COMMON)                                        \
02218     ? (                                                                        \
02219        (LL_ADC_IsEnabled(ADC1) |                                               \
02220         LL_ADC_IsEnabled(ADC2)  )                                              \
02221       )                                                                        \
02222       :                                                                        \
02223       (                                                                        \
02224        (LL_ADC_IsEnabled(ADC3) |                                               \
02225         LL_ADC_IsEnabled(ADC4)  )                                              \
02226       )                                                                        \
02227   )
02228 #elif defined(ADC1) && defined(ADC2)
02229 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
02230   (LL_ADC_IsEnabled(ADC1) |                                                    \
02231    LL_ADC_IsEnabled(ADC2)  )
02232 #else
02233 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
02234   LL_ADC_IsEnabled(ADC1)
02235 #endif
02236
02237 /**
02238   * @brief  Helper macro to define the ADC conversion data full-scale digital
02239   *         value corresponding to the selected ADC resolution.
02240   * @note   ADC conversion data full-scale corresponds to voltage range
02241   *         determined by analog voltage references Vref+ and Vref-
02242   *         (refer to reference manual).
02243   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
02244   *         @arg @ref LL_ADC_RESOLUTION_12B
02245   *         @arg @ref LL_ADC_RESOLUTION_10B
02246   *         @arg @ref LL_ADC_RESOLUTION_8B
02247   *         @arg @ref LL_ADC_RESOLUTION_6B
02248   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
02249   */
02250 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
02251   (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))
02252
02253 /**
02254   * @brief  Helper macro to convert the ADC conversion data from
02255   *         a resolution to another resolution.
02256   * @param  __DATA__ ADC conversion data to be converted
02257   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
02258   *         This parameter can be one of the following values:
02259   *         @arg @ref LL_ADC_RESOLUTION_12B
02260   *         @arg @ref LL_ADC_RESOLUTION_10B
02261   *         @arg @ref LL_ADC_RESOLUTION_8B
02262   *         @arg @ref LL_ADC_RESOLUTION_6B
02263   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
02264   *         This parameter can be one of the following values:
02265   *         @arg @ref LL_ADC_RESOLUTION_12B
02266   *         @arg @ref LL_ADC_RESOLUTION_10B
02267   *         @arg @ref LL_ADC_RESOLUTION_8B
02268   *         @arg @ref LL_ADC_RESOLUTION_6B
02269   * @retval ADC conversion data to the requested resolution
02270   */
02271 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
02272                                          __ADC_RESOLUTION_CURRENT__,\
02273                                          __ADC_RESOLUTION_TARGET__)            \
02274   (((__DATA__)                                                                 \
02275     << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))    \
02276    >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))       \
02277   )
02278
02279 /**
02280   * @brief  Helper macro to calculate the voltage (unit: mVolt)
02281   *         corresponding to a ADC conversion data (unit: digital value).
02282   * @note   Analog reference voltage (Vref+) must be either known from
02283   *         user board environment or can be calculated using ADC measurement
02284   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
02285   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
02286   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
02287   *                       (unit: digital value).
02288   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
02289   *         @arg @ref LL_ADC_RESOLUTION_12B
02290   *         @arg @ref LL_ADC_RESOLUTION_10B
02291   *         @arg @ref LL_ADC_RESOLUTION_8B
02292   *         @arg @ref LL_ADC_RESOLUTION_6B
02293   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
02294   */
02295 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
02296                                       __ADC_DATA__,\
02297                                       __ADC_RESOLUTION__)                      \
02298   ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
02299    / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
02300   )
02301
02302 /**
02303   * @brief  Helper macro to calculate analog reference voltage (Vref+)
02304   *         (unit: mVolt) from ADC conversion data of internal voltage
02305   *         reference VrefInt.
02306   * @note   Computation is using VrefInt calibration value
02307   *         stored in system memory for each device during production.
02308   * @note   This voltage depends on user board environment: voltage level
02309   *         connected to pin Vref+.
02310   *         On devices with small package, the pin Vref+ is not present
02311   *         and internally bonded to pin Vdda.
02312   * @note   On this STM32 serie, calibration data of internal voltage reference
02313   *         VrefInt corresponds to a resolution of 12 bits,
02314   *         this is the recommended ADC resolution to convert voltage of
02315   *         internal voltage reference VrefInt.
02316   *         Otherwise, this macro performs the processing to scale
02317   *         ADC conversion data to 12 bits.
02318   * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
02319   *         of internal voltage reference VrefInt (unit: digital value).
02320   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
02321   *         @arg @ref LL_ADC_RESOLUTION_12B
02322   *         @arg @ref LL_ADC_RESOLUTION_10B
02323   *         @arg @ref LL_ADC_RESOLUTION_8B
02324   *         @arg @ref LL_ADC_RESOLUTION_6B
02325   * @retval Analog reference voltage (unit: mV)
02326   */
02327 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
02328                                          __ADC_RESOLUTION__)                   \
02329   (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
02330     / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                 \
02331                                        (__ADC_RESOLUTION__),                   \
02332                                        LL_ADC_RESOLUTION_12B)                  \
02333   )
02334
02335 /**
02336   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
02337   *         from ADC conversion data of internal temperature sensor.
02338   * @note   Computation is using temperature sensor calibration values
02339   *         stored in system memory for each device during production.
02340   * @note   Calculation formula:
02341   *           Temperature = ((TS_ADC_DATA - TS_CAL1)
02342   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
02343   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
02344   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
02345   *                Avg_Slope = (TS_CAL2 - TS_CAL1)
02346   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
02347   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
02348   *                            TEMP_DEGC_CAL1 (calibrated in factory)
02349   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
02350   *                            TEMP_DEGC_CAL2 (calibrated in factory)
02351   *         Caution: Calculation relevancy under reserve that calibration
02352   *                  parameters are correct (address and data).
02353   *                  To calculate temperature using temperature sensor
02354   *                  datasheet typical values (generic values less, therefore
02355   *                  less accurate than calibrated values),
02356   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
02357   * @note   As calculation input, the analog reference voltage (Vref+) must be
02358   *         defined as it impacts the ADC LSB equivalent voltage.
02359   * @note   Analog reference voltage (Vref+) must be either known from
02360   *         user board environment or can be calculated using ADC measurement
02361   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
02362   * @note   On this STM32 serie, calibration data of temperature sensor
02363   *         corresponds to a resolution of 12 bits,
02364   *         this is the recommended ADC resolution to convert voltage of
02365   *         temperature sensor.
02366   *         Otherwise, this macro performs the processing to scale
02367   *         ADC conversion data to 12 bits.
02368   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
02369   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
02370   *                                 temperature sensor (unit: digital value).
02371   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
02372   *                                 sensor voltage has been measured.
02373   *         This parameter can be one of the following values:
02374   *         @arg @ref LL_ADC_RESOLUTION_12B
02375   *         @arg @ref LL_ADC_RESOLUTION_10B
02376   *         @arg @ref LL_ADC_RESOLUTION_8B
02377   *         @arg @ref LL_ADC_RESOLUTION_6B
02378   * @retval Temperature (unit: degree Celsius)
02379   */
02380 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
02381                                   __TEMPSENSOR_ADC_DATA__,\
02382                                   __ADC_RESOLUTION__)                              \
02383   (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
02384                                                     (__ADC_RESOLUTION__),          \
02385                                                     LL_ADC_RESOLUTION_12B)         \
02386                    * (__VREFANALOG_VOLTAGE__))                                     \
02387                   / TEMPSENSOR_CAL_VREFANALOG)                                     \
02388         - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
02389      ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
02390     ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
02391    ) + TEMPSENSOR_CAL1_TEMP                                                        \
02392   )
02393
02394 /**
02395   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
02396   *         from ADC conversion data of internal temperature sensor.
02397   * @note   Computation is using temperature sensor typical values
02398   *         (refer to device datasheet).
02399   * @note   Calculation formula:
02400   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
02401   *                         / Avg_Slope + CALx_TEMP
02402   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
02403   *                                   (unit: digital value)
02404   *                Avg_Slope        = temperature sensor slope
02405   *                                   (unit: uV/Degree Celsius)
02406   *                TS_TYP_CALx_VOLT = temperature sensor digital value at
02407   *                                   temperature CALx_TEMP (unit: mV)
02408   *         Caution: Calculation relevancy under reserve the temperature sensor
02409   *                  of the current device has characteristics in line with
02410   *                  datasheet typical values.
02411   *                  If temperature sensor calibration values are available on
02412   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
02413   *                  temperature calculation will be more accurate using
02414   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
02415   * @note   As calculation input, the analog reference voltage (Vref+) must be
02416   *         defined as it impacts the ADC LSB equivalent voltage.
02417   * @note   Analog reference voltage (Vref+) must be either known from
02418   *         user board environment or can be calculated using ADC measurement
02419   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
02420   * @note   ADC measurement data must correspond to a resolution of 12bits
02421   *         (full scale digital value 4095). If not the case, the data must be
02422   *         preliminarily rescaled to an equivalent resolution of 12 bits.
02423   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
02424   *                                       On STM32F3, refer to device datasheet parameter "Avg_Slope".
02425   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
02426   *                                       On STM32F3, refer to device datasheet parameter "V25" (corresponding to TS_CAL1).
02427   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
02428   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
02429   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
02430   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
02431   *         This parameter can be one of the following values:
02432   *         @arg @ref LL_ADC_RESOLUTION_12B
02433   *         @arg @ref LL_ADC_RESOLUTION_10B
02434   *         @arg @ref LL_ADC_RESOLUTION_8B
02435   *         @arg @ref LL_ADC_RESOLUTION_6B
02436   * @retval Temperature (unit: degree Celsius)
02437   */
02438 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
02439                                              __TEMPSENSOR_TYP_CALX_V__,\
02440                                              __TEMPSENSOR_CALX_TEMP__,\
02441                                              __VREFANALOG_VOLTAGE__,\
02442                                              __TEMPSENSOR_ADC_DATA__,\
02443                                              __ADC_RESOLUTION__)               \
02444   ((( (                                                                        \
02445        (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
02446                  * 1000)                                                       \
02447        -                                                                       \
02448        (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
02449                   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
02450                  * 1000)                                                       \
02451       )                                                                        \
02452     ) / (__TEMPSENSOR_TYP_AVGSLOPE__)                                          \
02453    ) + (__TEMPSENSOR_CALX_TEMP__)                                              \
02454   )
02455
02456 /**
02457   * @}
02458   */
02459
02460 /**
02461   * @}
02462   */
02463
02464
02465 /* Exported functions --------------------------------------------------------*/
02466 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
02467   * @{
02468   */
02469
02470 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
02471   * @{
02472   */
02473 /* Note: LL ADC functions to set DMA transfer are located into sections of    */
02474 /*       configuration of ADC instance, groups and multimode (if available):  */
02475 /*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
02476
02477 /**
02478   * @brief  Function to help to configure DMA transfer from ADC: retrieve the
02479   *         ADC register address from ADC instance and a list of ADC registers
02480   *         intended to be used (most commonly) with DMA transfer.
02481   * @note   These ADC registers are data registers:
02482   *         when ADC conversion data is available in ADC data registers,
02483   *         ADC generates a DMA transfer request.
02484   * @note   This macro is intended to be used with LL DMA driver, refer to
02485   *         function "LL_DMA_ConfigAddresses()".
02486   *         Example:
02487   *           LL_DMA_ConfigAddresses(DMA1,
02488   *                                  LL_DMA_CHANNEL_1,
02489   *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
02490   *                                  (uint32_t)&< array or variable >,
02491   *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
02492   * @note   For devices with several ADC: in multimode, some devices
02493   *         use a different data register outside of ADC instance scope
02494   *         (common data register). This macro manages this register difference,
02495   *         only ADC instance has to be set as parameter.
02496   * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\n
02497   *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\n
02498   *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr
02499   * @param  ADCx ADC instance
02500   * @param  Register This parameter can be one of the following values:
02501   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
02502   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
02503   *
02504   *         (1) Available on devices with several ADC instances.
02505   * @retval ADC register address
02506   */
02507 #if defined(ADC_MULTIMODE_SUPPORT)
02508 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
02509 {
02510   register uint32_t data_reg_addr = 0U;
02511
02512   if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
02513   {
02514     /* Retrieve address of register DR */
02515     data_reg_addr = (uint32_t)&(ADCx->DR);
02516   }
02517   else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
02518   {
02519     /* Retrieve address of register CDR */
02520     data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
02521   }
02522
02523   return data_reg_addr;
02524 }
02525 #else
02526 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
02527 {
02528   /* Retrieve address of register DR */
02529   return (uint32_t)&(ADCx->DR);
02530 }
02531 #endif
02532
02533 /**
02534   * @}
02535   */
02536
02537 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
02538   * @{
02539   */
02540
02541 /**
02542   * @brief  Set parameter common to several ADC: Clock source and prescaler.
02543   * @note   On this STM32 serie, if ADC group injected is used, some
02544   *         clock ratio constraints between ADC clock and AHB clock
02545   *         must be respected.
02546   *         Refer to reference manual.
02547   * @note   On this STM32 serie, setting of this feature is conditioned to
02548   *         ADC state:
02549   *         All ADC instances of the ADC common group must be disabled.
02550   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
02551   *         ADC instance or by using helper macro helper macro
02552   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
02553   * @rmtoll CCR      CKMODE         LL_ADC_SetCommonClock\n
02554   *         CCR      PRESC          LL_ADC_SetCommonClock
02555   * @param  ADCxy_COMMON ADC common instance
02556   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02557   * @param  CommonClock This parameter can be one of the following values:
02558   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
02559   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
02560   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
02561   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
02562   * @retval None
02563   */
02564 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
02565 {
02566   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE, CommonClock);
02567 }
02568
02569 /**
02570   * @brief  Get parameter common to several ADC: Clock source and prescaler.
02571   * @rmtoll CCR      CKMODE         LL_ADC_GetCommonClock\n
02572   *         CCR      PRESC          LL_ADC_GetCommonClock
02573   * @param  ADCxy_COMMON ADC common instance
02574   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02575   * @retval Returned value can be one of the following values:
02576   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
02577   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
02578   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
02579   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
02580   */
02581 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
02582 {
02583   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE));
02584 }
02585
02586 /**
02587   * @brief  Set parameter common to several ADC: measurement path to internal
02588   *         channels (VrefInt, temperature sensor, ...).
02589   * @note   One or several values can be selected.
02590   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
02591   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
02592   * @note   Stabilization time of measurement path to internal channel:
02593   *         After enabling internal paths, before starting ADC conversion,
02594   *         a delay is required for internal voltage reference and
02595   *         temperature sensor stabilization time.
02596   *         Refer to device datasheet.
02597   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
02598   *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
02599   * @note   ADC internal channel sampling time constraint:
02600   *         For ADC conversion of internal channels,
02601   *         a sampling time minimum value is required.
02602   *         Refer to device datasheet.
02603   * @note   On this STM32 serie, setting of this feature is conditioned to
02604   *         ADC state:
02605   *         All ADC instances of the ADC common group must be disabled.
02606   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
02607   *         ADC instance or by using helper macro helper macro
02608   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
02609   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n
02610   *         CCR      TSEN           LL_ADC_SetCommonPathInternalCh\n
02611   *         CCR      VBATEN         LL_ADC_SetCommonPathInternalCh
02612   * @param  ADCxy_COMMON ADC common instance
02613   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02614   * @param  PathInternal This parameter can be a combination of the following values:
02615   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
02616   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
02617   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
02618   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
02619   * @retval None
02620   */
02621 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
02622 {
02623   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
02624 }
02625
02626 /**
02627   * @brief  Get parameter common to several ADC: measurement path to internal
02628   *         channels (VrefInt, temperature sensor, ...).
02629   * @note   One or several values can be selected.
02630   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
02631   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
02632   * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n
02633   *         CCR      TSEN           LL_ADC_GetCommonPathInternalCh\n
02634   *         CCR      VBATEN         LL_ADC_GetCommonPathInternalCh
02635   * @param  ADCxy_COMMON ADC common instance
02636   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02637   * @retval Returned value can be a combination of the following values:
02638   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
02639   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
02640   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
02641   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
02642   */
02643 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
02644 {
02645   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
02646 }
02647
02648 /**
02649   * @}
02650   */
02651
02652 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
02653   * @{
02654   */
02655
02656 /**
02657   * @brief  Set ADC calibration factor in the mode single-ended
02658   *         or differential (for devices with differential mode available).
02659   * @note   This function is intended to set calibration parameters
02660   *         without having to perform a new calibration using
02661   *         @ref LL_ADC_StartCalibration().
02662   * @note   For devices with differential mode available:
02663   *         Calibration of offset is specific to each of
02664   *         single-ended and differential modes
02665   *         (calibration factor must be specified for each of these
02666   *         differential modes, if used afterwards and if the application
02667   *         requires their calibration).
02668   * @note   In case of setting calibration factors of both modes single ended
02669   *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
02670   *         both calibration factors must be concatenated.
02671   *         To perform this processing, use helper macro
02672   *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
02673   * @note   On this STM32 serie, setting of this feature is conditioned to
02674   *         ADC state:
02675   *         ADC must be enabled, without calibration on going, without conversion
02676   *         on going on group regular.
02677   * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationFactor\n
02678   *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationFactor
02679   * @param  ADCx ADC instance
02680   * @param  SingleDiff This parameter can be one of the following values:
02681   *         @arg @ref LL_ADC_SINGLE_ENDED
02682   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
02683   *         @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
02684   * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
02685   * @retval None
02686   */
02687 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
02688 {
02689   MODIFY_REG(ADCx->CALFACT,
02690              SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
02691              CalibrationFactor << POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
02692 }
02693
02694 /**
02695   * @brief  Get ADC calibration factor in the mode single-ended
02696   *         or differential (for devices with differential mode available).
02697   * @note   Calibration factors are set by hardware after performing
02698   *         a calibration run using function @ref LL_ADC_StartCalibration().
02699   * @note   For devices with differential mode available:
02700   *         Calibration of offset is specific to each of
02701   *         single-ended and differential modes
02702   * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationFactor\n
02703   *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationFactor
02704   * @param  ADCx ADC instance
02705   * @param  SingleDiff This parameter can be one of the following values:
02706   *         @arg @ref LL_ADC_SINGLE_ENDED
02707   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
02708   * @retval Value between Min_Data=0x00 and Max_Data=0x7F
02709   */
02710 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
02711 {
02712   /* Retrieve bits with position in register depending on parameter           */
02713   /* "SingleDiff".                                                            */
02714   /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because      */
02715   /* containing other bits reserved for other purpose.                        */
02716   return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
02717 }
02718
02719 /**
02720   * @brief  Set ADC resolution.
02721   *         Refer to reference manual for alignments formats
02722   *         dependencies to ADC resolutions.
02723   * @note   On this STM32 serie, setting of this feature is conditioned to
02724   *         ADC state:
02725   *         ADC must be disabled or enabled without conversion on going
02726   *         on either groups regular or injected.
02727   * @rmtoll CFGR     RES            LL_ADC_SetResolution
02728   * @param  ADCx ADC instance
02729   * @param  Resolution This parameter can be one of the following values:
02730   *         @arg @ref LL_ADC_RESOLUTION_12B
02731   *         @arg @ref LL_ADC_RESOLUTION_10B
02732   *         @arg @ref LL_ADC_RESOLUTION_8B
02733   *         @arg @ref LL_ADC_RESOLUTION_6B
02734   * @retval None
02735   */
02736 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
02737 {
02738   MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
02739 }
02740
02741 /**
02742   * @brief  Get ADC resolution.
02743   *         Refer to reference manual for alignments formats
02744   *         dependencies to ADC resolutions.
02745   * @rmtoll CFGR     RES            LL_ADC_GetResolution
02746   * @param  ADCx ADC instance
02747   * @retval Returned value can be one of the following values:
02748   *         @arg @ref LL_ADC_RESOLUTION_12B
02749   *         @arg @ref LL_ADC_RESOLUTION_10B
02750   *         @arg @ref LL_ADC_RESOLUTION_8B
02751   *         @arg @ref LL_ADC_RESOLUTION_6B
02752   */
02753 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
02754 {
02755   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
02756 }
02757
02758 /**
02759   * @brief  Set ADC conversion data alignment.
02760   * @note   Refer to reference manual for alignments formats
02761   *         dependencies to ADC resolutions.
02762   * @note   On this STM32 serie, setting of this feature is conditioned to
02763   *         ADC state:
02764   *         ADC must be disabled or enabled without conversion on going
02765   *         on either groups regular or injected.
02766   * @rmtoll CFGR     ALIGN          LL_ADC_SetDataAlignment
02767   * @param  ADCx ADC instance
02768   * @param  DataAlignment This parameter can be one of the following values:
02769   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
02770   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
02771   * @retval None
02772   */
02773 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
02774 {
02775   MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
02776 }
02777
02778 /**
02779   * @brief  Get ADC conversion data alignment.
02780   * @note   Refer to reference manual for alignments formats
02781   *         dependencies to ADC resolutions.
02782   * @rmtoll CFGR     ALIGN          LL_ADC_GetDataAlignment
02783   * @param  ADCx ADC instance
02784   * @retval Returned value can be one of the following values:
02785   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
02786   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
02787   */
02788 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
02789 {
02790   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
02791 }
02792
02793 /**
02794   * @brief  Set ADC low power mode.
02795   * @note   Description of ADC low power modes:
02796   *         - ADC low power mode "auto wait": Dynamic low power mode,
02797   *           ADC conversions occurrences are limited to the minimum necessary
02798   *           in order to reduce power consumption.
02799   *           New ADC conversion starts only when the previous
02800   *           unitary conversion data (for ADC group regular)
02801   *           or previous sequence conversions data (for ADC group injected)
02802   *           has been retrieved by user software.
02803   *           In the meantime, ADC remains idle: does not performs any
02804   *           other conversion.
02805   *           This mode allows to automatically adapt the ADC conversions
02806   *           triggers to the speed of the software that reads the data.
02807   *           Moreover, this avoids risk of overrun for low frequency
02808   *           applications.
02809   *           How to use this low power mode:
02810   *           - Do not use with interruption or DMA since these modes
02811   *             have to clear immediately the EOC flag to free the
02812   *             IRQ vector sequencer.
02813   *           - Do use with polling: 1. Start conversion,
02814   *             2. Later on, when conversion data is needed: poll for end of
02815   *             conversion  to ensure that conversion is completed and
02816   *             retrieve ADC conversion data. This will trig another
02817   *             ADC conversion start.
02818   *         - ADC low power mode "auto power-off" (feature available on
02819   *           this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
02820   *           the ADC automatically powers-off after a conversion and
02821   *           automatically wakes up when a new conversion is triggered
02822   *           (with startup time between trigger and start of sampling).
02823   *           This feature can be combined with low power mode "auto wait".
02824   * @note   With ADC low power mode "auto wait", the ADC conversion data read
02825   *         is corresponding to previous ADC conversion start, independently
02826   *         of delay during which ADC was idle.
02827   *         Therefore, the ADC conversion data may be outdated: does not
02828   *         correspond to the current voltage level on the selected
02829   *         ADC channel.
02830   * @note   On this STM32 serie, setting of this feature is conditioned to
02831   *         ADC state:
02832   *         ADC must be disabled or enabled without conversion on going
02833   *         on either groups regular or injected.
02834   * @rmtoll CFGR     AUTDLY         LL_ADC_SetLowPowerMode
02835   * @param  ADCx ADC instance
02836   * @param  LowPowerMode This parameter can be one of the following values:
02837   *         @arg @ref LL_ADC_LP_MODE_NONE
02838   *         @arg @ref LL_ADC_LP_AUTOWAIT
02839   * @retval None
02840   */
02841 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
02842 {
02843   MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
02844 }
02845
02846 /**
02847   * @brief  Get ADC low power mode:
02848   * @note   Description of ADC low power modes:
02849   *         - ADC low power mode "auto wait": Dynamic low power mode,
02850   *           ADC conversions occurrences are limited to the minimum necessary
02851   *           in order to reduce power consumption.
02852   *           New ADC conversion starts only when the previous
02853   *           unitary conversion data (for ADC group regular)
02854   *           or previous sequence conversions data (for ADC group injected)
02855   *           has been retrieved by user software.
02856   *           In the meantime, ADC remains idle: does not performs any
02857   *           other conversion.
02858   *           This mode allows to automatically adapt the ADC conversions
02859   *           triggers to the speed of the software that reads the data.
02860   *           Moreover, this avoids risk of overrun for low frequency
02861   *           applications.
02862   *           How to use this low power mode:
02863   *           - Do not use with interruption or DMA since these modes
02864   *             have to clear immediately the EOC flag to free the
02865   *             IRQ vector sequencer.
02866   *           - Do use with polling: 1. Start conversion,
02867   *             2. Later on, when conversion data is needed: poll for end of
02868   *             conversion  to ensure that conversion is completed and
02869   *             retrieve ADC conversion data. This will trig another
02870   *             ADC conversion start.
02871   *         - ADC low power mode "auto power-off" (feature available on
02872   *           this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
02873   *           the ADC automatically powers-off after a conversion and
02874   *           automatically wakes up when a new conversion is triggered
02875   *           (with startup time between trigger and start of sampling).
02876   *           This feature can be combined with low power mode "auto wait".
02877   * @note   With ADC low power mode "auto wait", the ADC conversion data read
02878   *         is corresponding to previous ADC conversion start, independently
02879   *         of delay during which ADC was idle.
02880   *         Therefore, the ADC conversion data may be outdated: does not
02881   *         correspond to the current voltage level on the selected
02882   *         ADC channel.
02883   * @rmtoll CFGR     AUTDLY         LL_ADC_GetLowPowerMode
02884   * @param  ADCx ADC instance
02885   * @retval Returned value can be one of the following values:
02886   *         @arg @ref LL_ADC_LP_MODE_NONE
02887   *         @arg @ref LL_ADC_LP_AUTOWAIT
02888   */
02889 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
02890 {
02891   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
02892 }
02893
02894 /**
02895   * @brief  Set ADC selected offset number 1, 2, 3 or 4.
02896   * @note   This function set the 2 items of offset configuration:
02897   *         - ADC channel to which the offset programmed will be applied
02898   *           (independently of channel mapped on ADC group regular
02899   *           or group injected)
02900   *         - Offset level (offset to be subtracted from the raw
02901   *           converted data).
02902   * @note   Caution: Offset format is dependent to ADC resolution:
02903   *         offset has to be left-aligned on bit 11, the LSB (right bits)
02904   *         are set to 0.
02905   * @note   This function enables the offset, by default. It can be forced
02906   *         to disable state using function LL_ADC_SetOffsetState().
02907   * @note   If a channel is mapped on several offsets numbers, only the offset
02908   *         with the lowest value is considered for the subtraction.
02909   * @note   On this STM32 serie, setting of this feature is conditioned to
02910   *         ADC state:
02911   *         ADC must be disabled or enabled without conversion on going
02912   *         on either groups regular or injected.
02913   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_SetOffset\n
02914   *         OFR1     OFFSET1        LL_ADC_SetOffset\n
02915   *         OFR1     OFFSET1_EN     LL_ADC_SetOffset\n
02916   *         OFR2     OFFSET2_CH     LL_ADC_SetOffset\n
02917   *         OFR2     OFFSET2        LL_ADC_SetOffset\n
02918   *         OFR2     OFFSET2_EN     LL_ADC_SetOffset\n
02919   *         OFR3     OFFSET3_CH     LL_ADC_SetOffset\n
02920   *         OFR3     OFFSET3        LL_ADC_SetOffset\n
02921   *         OFR3     OFFSET3_EN     LL_ADC_SetOffset\n
02922   *         OFR4     OFFSET4_CH     LL_ADC_SetOffset\n
02923   *         OFR4     OFFSET4        LL_ADC_SetOffset\n
02924   *         OFR4     OFFSET4_EN     LL_ADC_SetOffset
02925   * @param  ADCx ADC instance
02926   * @param  Offsety This parameter can be one of the following values:
02927   *         @arg @ref LL_ADC_OFFSET_1
02928   *         @arg @ref LL_ADC_OFFSET_2
02929   *         @arg @ref LL_ADC_OFFSET_3
02930   *         @arg @ref LL_ADC_OFFSET_4
02931   * @param  Channel This parameter can be one of the following values:
02932   *         @arg @ref LL_ADC_CHANNEL_0
02933   *         @arg @ref LL_ADC_CHANNEL_1
02934   *         @arg @ref LL_ADC_CHANNEL_2
02935   *         @arg @ref LL_ADC_CHANNEL_3
02936   *         @arg @ref LL_ADC_CHANNEL_4
02937   *         @arg @ref LL_ADC_CHANNEL_5
02938   *         @arg @ref LL_ADC_CHANNEL_6
02939   *         @arg @ref LL_ADC_CHANNEL_7
02940   *         @arg @ref LL_ADC_CHANNEL_8
02941   *         @arg @ref LL_ADC_CHANNEL_9
02942   *         @arg @ref LL_ADC_CHANNEL_10
02943   *         @arg @ref LL_ADC_CHANNEL_11
02944   *         @arg @ref LL_ADC_CHANNEL_12
02945   *         @arg @ref LL_ADC_CHANNEL_13
02946   *         @arg @ref LL_ADC_CHANNEL_14
02947   *         @arg @ref LL_ADC_CHANNEL_15
02948   *         @arg @ref LL_ADC_CHANNEL_16
02949   *         @arg @ref LL_ADC_CHANNEL_17
02950   *         @arg @ref LL_ADC_CHANNEL_18
02951   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
02952   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
02953   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
02954   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
02955   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
02956   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
02957   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
02958   *
02959   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
02960   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
02961   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
02962   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
02963   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
02964   *             only one ADC instance is allowed to be connected to VrefInt at the same time.
02965   * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
02966   * @retval None
02967   */
02968 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
02969 {
02970   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
02971
02972   MODIFY_REG(*preg,
02973              ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
02974              ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
02975 }
02976
02977 /**
02978   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
02979   *         Channel to which the offset programmed will be applied
02980   *         (independently of channel mapped on ADC group regular
02981   *         or group injected)
02982   * @note   Usage of the returned channel number:
02983   *         - To reinject this channel into another function LL_ADC_xxx:
02984   *           the returned channel number is only partly formatted on definition
02985   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
02986   *           with parts of literals LL_ADC_CHANNEL_x or using
02987   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
02988   *           Then the selected literal LL_ADC_CHANNEL_x can be used
02989   *           as parameter for another function.
02990   *         - To get the channel number in decimal format:
02991   *           process the returned value with the helper macro
02992   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
02993   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_GetOffsetChannel\n
02994   *         OFR2     OFFSET2_CH     LL_ADC_GetOffsetChannel\n
02995   *         OFR3     OFFSET3_CH     LL_ADC_GetOffsetChannel\n
02996   *         OFR4     OFFSET4_CH     LL_ADC_GetOffsetChannel
02997   * @param  ADCx ADC instance
02998   * @param  Offsety This parameter can be one of the following values:
02999   *         @arg @ref LL_ADC_OFFSET_1
03000   *         @arg @ref LL_ADC_OFFSET_2
03001   *         @arg @ref LL_ADC_OFFSET_3
03002   *         @arg @ref LL_ADC_OFFSET_4
03003   * @retval Returned value can be one of the following values:
03004   *         @arg @ref LL_ADC_CHANNEL_0
03005   *         @arg @ref LL_ADC_CHANNEL_1
03006   *         @arg @ref LL_ADC_CHANNEL_2
03007   *         @arg @ref LL_ADC_CHANNEL_3
03008   *         @arg @ref LL_ADC_CHANNEL_4
03009   *         @arg @ref LL_ADC_CHANNEL_5
03010   *         @arg @ref LL_ADC_CHANNEL_6
03011   *         @arg @ref LL_ADC_CHANNEL_7
03012   *         @arg @ref LL_ADC_CHANNEL_8
03013   *         @arg @ref LL_ADC_CHANNEL_9
03014   *         @arg @ref LL_ADC_CHANNEL_10
03015   *         @arg @ref LL_ADC_CHANNEL_11
03016   *         @arg @ref LL_ADC_CHANNEL_12
03017   *         @arg @ref LL_ADC_CHANNEL_13
03018   *         @arg @ref LL_ADC_CHANNEL_14
03019   *         @arg @ref LL_ADC_CHANNEL_15
03020   *         @arg @ref LL_ADC_CHANNEL_16
03021   *         @arg @ref LL_ADC_CHANNEL_17
03022   *         @arg @ref LL_ADC_CHANNEL_18
03023   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
03024   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
03025   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
03026   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
03027   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
03028   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
03029   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
03030   *
03031   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
03032   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
03033   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
03034   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
03035   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
03036   *             only one ADC instance is allowed to be connected to VrefInt at the same time.\n
03037   *         (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
03038   *                         comparison with internal channel parameter to be done
03039   *                         using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
03040   */
03041 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
03042 {
03043   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
03044
03045   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
03046 }
03047
03048 /**
03049   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
03050   *         Offset level (offset to be subtracted from the raw
03051   *         converted data).
03052   * @note   Caution: Offset format is dependent to ADC resolution:
03053   *         offset has to be left-aligned on bit 11, the LSB (right bits)
03054   *         are set to 0.
03055   * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\n
03056   *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\n
03057   *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\n
03058   *         OFR4     OFFSET4        LL_ADC_GetOffsetLevel
03059   * @param  ADCx ADC instance
03060   * @param  Offsety This parameter can be one of the following values:
03061   *         @arg @ref LL_ADC_OFFSET_1
03062   *         @arg @ref LL_ADC_OFFSET_2
03063   *         @arg @ref LL_ADC_OFFSET_3
03064   *         @arg @ref LL_ADC_OFFSET_4
03065   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
03066   */
03067 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
03068 {
03069   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
03070
03071   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
03072 }
03073
03074 /**
03075   * @brief  Set for the ADC selected offset number 1, 2, 3 or 4:
03076   *         force offset state disable or enable
03077   *         without modifying offset channel or offset value.
03078   * @note   This function should be needed only in case of offset to be
03079   *         enabled-disabled dynamically, and should not be needed in other cases:
03080   *         function LL_ADC_SetOffset() automatically enables the offset.
03081   * @note   On this STM32 serie, setting of this feature is conditioned to
03082   *         ADC state:
03083   *         ADC must be disabled or enabled without conversion on going
03084   *         on either groups regular or injected.
03085   * @rmtoll OFR1     OFFSET1_EN     LL_ADC_SetOffsetState\n
03086   *         OFR2     OFFSET2_EN     LL_ADC_SetOffsetState\n
03087   *         OFR3     OFFSET3_EN     LL_ADC_SetOffsetState\n
03088   *         OFR4     OFFSET4_EN     LL_ADC_SetOffsetState
03089   * @param  ADCx ADC instance
03090   * @param  Offsety This parameter can be one of the following values:
03091   *         @arg @ref LL_ADC_OFFSET_1
03092   *         @arg @ref LL_ADC_OFFSET_2
03093   *         @arg @ref LL_ADC_OFFSET_3
03094   *         @arg @ref LL_ADC_OFFSET_4
03095   * @param  OffsetState This parameter can be one of the following values:
03096   *         @arg @ref LL_ADC_OFFSET_DISABLE
03097   *         @arg @ref LL_ADC_OFFSET_ENABLE
03098   * @retval None
03099   */
03100 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
03101 {
03102   register uint32_t *preg = (uint32_t *)((uint32_t)
03103                             ((uint32_t)(&ADCx->OFR1) + (Offsety*4U)));
03104
03105   MODIFY_REG(*preg,
03106              ADC_OFR1_OFFSET1_EN,
03107              OffsetState);
03108 }
03109
03110 /**
03111   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
03112   *         offset state disabled or enabled.
03113   * @rmtoll OFR1     OFFSET1_EN     LL_ADC_GetOffsetState\n
03114   *         OFR2     OFFSET2_EN     LL_ADC_GetOffsetState\n
03115   *         OFR3     OFFSET3_EN     LL_ADC_GetOffsetState\n
03116   *         OFR4     OFFSET4_EN     LL_ADC_GetOffsetState
03117   * @param  ADCx ADC instance
03118   * @param  Offsety This parameter can be one of the following values:
03119   *         @arg @ref LL_ADC_OFFSET_1
03120   *         @arg @ref LL_ADC_OFFSET_2
03121   *         @arg @ref LL_ADC_OFFSET_3
03122   *         @arg @ref LL_ADC_OFFSET_4
03123   * @retval Returned value can be one of the following values:
03124   *         @arg @ref LL_ADC_OFFSET_DISABLE
03125   *         @arg @ref LL_ADC_OFFSET_ENABLE
03126   */
03127 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
03128 {
03129   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
03130
03131   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
03132 }
03133
03134 /**
03135   * @}
03136   */
03137
03138 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
03139   * @{
03140   */
03141
03142 /**
03143   * @brief  Set ADC group regular conversion trigger source:
03144   *         internal (SW start) or from external IP (timer event,
03145   *         external interrupt line).
03146   * @note   On this STM32 serie, setting trigger source to external trigger
03147   *         also set trigger polarity to rising edge
03148   *         (default setting for compatibility with some ADC on other
03149   *         STM32 families having this setting set by HW default value).
03150   *         In case of need to modify trigger edge, use
03151   *         function @ref LL_ADC_REG_SetTriggerEdge().
03152   * @note   Availability of parameters of trigger sources from timer
03153   *         depends on timers availability on the selected device.
03154   * @note   On this STM32 serie, setting of this feature is conditioned to
03155   *         ADC state:
03156   *         ADC must be disabled or enabled without conversion on going
03157   *         on group regular.
03158   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_SetTriggerSource\n
03159   *         CFGR     EXTEN          LL_ADC_REG_SetTriggerSource
03160   * @param  ADCx ADC instance
03161   * @param  TriggerSource This parameter can be one of the following values:
03162   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
03163   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
03164   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
03165   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1                (3)(4)(5)(6)
03166   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12    (1)(2)            (7)
03167   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2                (3)(4)(5)(6)
03168   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12    (1)(2)            (7)
03169   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
03170   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO               (3)(4)(5)(6)
03171   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12   (1)(2)            (7)
03172   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34  (1)(2)               (8)
03173   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34    (1)(2)               (8)
03174   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12    (1)(2)            (7)
03175   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34    (1)(2)               (8)
03176   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO               (3)(4)(5)
03177   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12   (1)(2)            (7)
03178   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34  (1)(2)               (8)
03179   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34    (1)(2)               (8)
03180   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4                (3)(4)(5)
03181   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12    (1)(2)            (7)
03182   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO         (1)(2)(3)(5)
03183   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34    (1)(2)               (8)
03184   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4                (3)   (5)
03185   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12    (1)(2)            (7)
03186   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO               (3)(4)(5)(6)
03187   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12    (1)(2)            (7)
03188   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO               (3)
03189   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12   (1)(2)            (7)
03190   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2        (1)(2)
03191   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12   (1)(2)            (7)
03192   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34   (1)(2)               (8)
03193   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34  (1)(2)               (8)
03194   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2        (1)(2)
03195   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34    (1)(2)               (8)
03196   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO                    (5)
03197   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12  (1)               (7)
03198   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12 (1)               (7)
03199   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12   (1)               (7)
03200   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12   (1)               (7)
03201   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12   (1)               (7)
03202   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC3   (1)                  (8)
03203   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34 (1)                  (8)
03204   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34   (1)                  (8)
03205   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1                 (4)
03206   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3                 (4)
03207   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34  (1)(2)               (8)
03208   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11             (3)(4)(5)(6)
03209   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12 (1)(2)            (7)
03210
03211   *         (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
03212   *         (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
03213   *         (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
03214   *         (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
03215   *         (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
03216   *         (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
03217   *         (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
03218   *         (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
03219   * @retval None
03220   */
03221 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
03222 {
03223   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
03224 }
03225
03226 /**
03227   * @brief  Get ADC group regular conversion trigger source:
03228   *         internal (SW start) or from external IP (timer event,
03229   *         external interrupt line).
03230   * @note   To determine whether group regular trigger source is
03231   *         internal (SW start) or external, without detail
03232   *         of which peripheral is selected as external trigger,
03233   *         (equivalent to
03234   *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
03235   *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
03236   * @note   Availability of parameters of trigger sources from timer
03237   *         depends on timers availability on the selected device.
03238   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_GetTriggerSource\n
03239   *         CFGR     EXTEN          LL_ADC_REG_GetTriggerSource
03240   * @param  ADCx ADC instance
03241   * @retval Returned value can be one of the following values:
03242   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
03243   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
03244   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
03245   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1                (3)(4)(5)(6)
03246   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12    (1)(2)            (7)
03247   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2                (3)(4)(5)(6)
03248   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12    (1)(2)            (7)
03249   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
03250   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO               (3)(4)(5)(6)
03251   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12   (1)(2)            (7)
03252   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34  (1)(2)               (8)
03253   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34    (1)(2)               (8)
03254   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12    (1)(2)            (7)
03255   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34    (1)(2)               (8)
03256   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO               (3)(4)(5)
03257   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12   (1)(2)            (7)
03258   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34  (1)(2)               (8)
03259   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34    (1)(2)               (8)
03260   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4                (3)(4)(5)
03261   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12    (1)(2)            (7)
03262   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO         (1)(2)(3)(5)
03263   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34    (1)(2)               (8)
03264   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4                (3)   (5)
03265   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12    (1)(2)            (7)
03266   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO               (3)(4)(5)(6)
03267   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12    (1)(2)            (7)
03268   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO               (3)
03269   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12   (1)(2)            (7)
03270   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2        (1)(2)
03271   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12   (1)(2)            (7)
03272   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34   (1)(2)               (8)
03273   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34  (1)(2)               (8)
03274   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2        (1)(2)
03275   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34    (1)(2)               (8)
03276   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO                    (5)
03277   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12  (1)               (7)
03278   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12 (1)               (7)
03279   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12   (1)               (7)
03280   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12   (1)               (7)
03281   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12   (1)               (7)
03282   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC3   (1)                  (8)
03283   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34 (1)                  (8)
03284   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34   (1)                  (8)
03285   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1                 (4)
03286   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3                 (4)
03287   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34  (1)(2)               (8)
03288   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11             (3)(4)(5)(6)
03289   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12 (1)(2)            (7)
03290
03291   *         (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
03292   *         (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
03293   *         (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
03294   *         (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
03295   *         (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
03296   *         (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
03297   *         (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
03298   *         (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
03299   */
03300 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
03301 {
03302   register uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
03303
03304   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
03305   /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}.                            */
03306   register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
03307
03308   /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL         */
03309   /* to match with triggers literals definition.                              */
03310   return ((TriggerSource
03311            & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
03312           | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
03313          );
03314 }
03315
03316 /**
03317   * @brief  Get ADC group regular conversion trigger source internal (SW start)
03318             or external.
03319   * @note   In case of group regular trigger source set to external trigger,
03320   *         to determine which peripheral is selected as external trigger,
03321   *         use function @ref LL_ADC_REG_GetTriggerSource().
03322   * @rmtoll CFGR     EXTEN          LL_ADC_REG_IsTriggerSourceSWStart
03323   * @param  ADCx ADC instance
03324   * @retval Value "0" if trigger source external trigger
03325   *         Value "1" if trigger source SW start.
03326   */
03327 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
03328 {
03329   return (READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN));
03330 }
03331
03332 /**
03333   * @brief  Set ADC group regular conversion trigger polarity.
03334   * @note   Applicable only for trigger source set to external trigger.
03335   * @note   On this STM32 serie, setting of this feature is conditioned to
03336   *         ADC state:
03337   *         ADC must be disabled or enabled without conversion on going
03338   *         on group regular.
03339   * @rmtoll CFGR     EXTEN          LL_ADC_REG_SetTriggerEdge
03340   * @param  ADCx ADC instance
03341   * @param  ExternalTriggerEdge This parameter can be one of the following values:
03342   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
03343   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
03344   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
03345   * @retval None
03346   */
03347 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
03348 {
03349   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
03350 }
03351
03352 /**
03353   * @brief  Get ADC group regular conversion trigger polarity.
03354   * @note   Applicable only for trigger source set to external trigger.
03355   * @rmtoll CFGR     EXTEN          LL_ADC_REG_GetTriggerEdge
03356   * @param  ADCx ADC instance
03357   * @retval Returned value can be one of the following values:
03358   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
03359   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
03360   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
03361   */
03362 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
03363 {
03364   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
03365 }
03366
03367
03368 /**
03369   * @brief  Set ADC group regular sequencer length and scan direction.
03370   * @note   Description of ADC group regular sequencer features:
03371   *         - For devices with sequencer fully configurable
03372   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
03373   *           sequencer length and each rank affectation to a channel
03374   *           are configurable.
03375   *           This function performs configuration of:
03376   *           - Sequence length: Number of ranks in the scan sequence.
03377   *           - Sequence direction: Unless specified in parameters, sequencer
03378   *             scan direction is forward (from rank 1 to rank n).
03379   *           Sequencer ranks are selected using
03380   *           function "LL_ADC_REG_SetSequencerRanks()".
03381   *         - For devices with sequencer not fully configurable
03382   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
03383   *           sequencer length and each rank affectation to a channel
03384   *           are defined by channel number.
03385   *           This function performs configuration of:
03386   *           - Sequence length: Number of ranks in the scan sequence is
03387   *             defined by number of channels set in the sequence,
03388   *             rank of each channel is fixed by channel HW number.
03389   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
03390   *           - Sequence direction: Unless specified in parameters, sequencer
03391   *             scan direction is forward (from lowest channel number to
03392   *             highest channel number).
03393   *           Sequencer ranks are selected using
03394   *           function "LL_ADC_REG_SetSequencerChannels()".
03395   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
03396   *         ADC conversion on only 1 channel.
03397   * @note   On this STM32 serie, setting of this feature is conditioned to
03398   *         ADC state:
03399   *         ADC must be disabled or enabled without conversion on going
03400   *         on group regular.
03401   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
03402   * @param  ADCx ADC instance
03403   * @param  SequencerNbRanks This parameter can be one of the following values:
03404   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
03405   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
03406   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
03407   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
03408   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
03409   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
03410   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
03411   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
03412   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
03413   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
03414   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
03415   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
03416   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
03417   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
03418   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
03419   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
03420   * @retval None
03421   */
03422 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
03423 {
03424   MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
03425 }
03426
03427 /**
03428   * @brief  Get ADC group regular sequencer length and scan direction.
03429   * @note   Description of ADC group regular sequencer features:
03430   *         - For devices with sequencer fully configurable
03431   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
03432   *           sequencer length and each rank affectation to a channel
03433   *           are configurable.
03434   *           This function retrieves:
03435   *           - Sequence length: Number of ranks in the scan sequence.
03436   *           - Sequence direction: Unless specified in parameters, sequencer
03437   *             scan direction is forward (from rank 1 to rank n).
03438   *           Sequencer ranks are selected using
03439   *           function "LL_ADC_REG_SetSequencerRanks()".
03440   *         - For devices with sequencer not fully configurable
03441   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
03442   *           sequencer length and each rank affectation to a channel
03443   *           are defined by channel number.
03444   *           This function retrieves:
03445   *           - Sequence length: Number of ranks in the scan sequence is
03446   *             defined by number of channels set in the sequence,
03447   *             rank of each channel is fixed by channel HW number.
03448   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
03449   *           - Sequence direction: Unless specified in parameters, sequencer
03450   *             scan direction is forward (from lowest channel number to
03451   *             highest channel number).
03452   *           Sequencer ranks are selected using
03453   *           function "LL_ADC_REG_SetSequencerChannels()".
03454   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
03455   *         ADC conversion on only 1 channel.
03456   * @rmtoll SQR1     L              LL_ADC_REG_GetSequencerLength
03457   * @param  ADCx ADC instance
03458   * @retval Returned value can be one of the following values:
03459   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
03460   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
03461   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
03462   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
03463   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
03464   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
03465   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
03466   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
03467   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
03468   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
03469   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
03470   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
03471   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
03472   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
03473   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
03474   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
03475   */
03476 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
03477 {
03478   return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
03479 }
03480
03481 /**
03482   * @brief  Set ADC group regular sequencer discontinuous mode:
03483   *         sequence subdivided and scan conversions interrupted every selected
03484   *         number of ranks.
03485   * @note   It is not possible to enable both ADC group regular
03486   *         continuous mode and sequencer discontinuous mode.
03487   * @note   It is not possible to enable both ADC auto-injected mode
03488   *         and ADC group regular sequencer discontinuous mode.
03489   * @note   On this STM32 serie, setting of this feature is conditioned to
03490   *         ADC state:
03491   *         ADC must be disabled or enabled without conversion on going
03492   *         on group regular.
03493   * @rmtoll CFGR     DISCEN         LL_ADC_REG_SetSequencerDiscont\n
03494   *         CFGR     DISCNUM        LL_ADC_REG_SetSequencerDiscont
03495   * @param  ADCx ADC instance
03496   * @param  SeqDiscont This parameter can be one of the following values:
03497   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
03498   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
03499   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
03500   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
03501   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
03502   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
03503   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
03504   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
03505   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
03506   * @retval None
03507   */
03508 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
03509 {
03510   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
03511 }
03512
03513 /**
03514   * @brief  Get ADC group regular sequencer discontinuous mode:
03515   *         sequence subdivided and scan conversions interrupted every selected
03516   *         number of ranks.
03517   * @rmtoll CFGR     DISCEN         LL_ADC_REG_GetSequencerDiscont\n
03518   *         CFGR     DISCNUM        LL_ADC_REG_GetSequencerDiscont
03519   * @param  ADCx ADC instance
03520   * @retval Returned value can be one of the following values:
03521   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
03522   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
03523   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
03524   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
03525   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
03526   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
03527   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
03528   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
03529   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
03530   */
03531 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
03532 {
03533   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
03534 }
03535
03536 /**
03537   * @brief  Set ADC group regular sequence: channel on the selected
03538   *         scan sequence rank.
03539   * @note   This function performs configuration of:
03540   *         - Channels ordering into each rank of scan sequence:
03541   *           whatever channel can be placed into whatever rank.
03542   * @note   On this STM32 serie, ADC group regular sequencer is
03543   *         fully configurable: sequencer length and each rank
03544   *         affectation to a channel are configurable.
03545   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
03546   * @note   Depending on devices and packages, some channels may not be available.
03547   *         Refer to device datasheet for channels availability.
03548   * @note   On this STM32 serie, to measure internal channels (VrefInt,
03549   *         TempSensor, ...), measurement paths to internal channels must be
03550   *         enabled separately.
03551   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
03552   * @note   On this STM32 serie, setting of this feature is conditioned to
03553   *         ADC state:
03554   *         ADC must be disabled or enabled without conversion on going
03555   *         on group regular.
03556   * @rmtoll SQR1     SQ1            LL_ADC_REG_SetSequencerRanks\n
03557   *         SQR1     SQ2            LL_ADC_REG_SetSequencerRanks\n
03558   *         SQR1     SQ3            LL_ADC_REG_SetSequencerRanks\n
03559   *         SQR1     SQ4            LL_ADC_REG_SetSequencerRanks\n
03560   *         SQR2     SQ5            LL_ADC_REG_SetSequencerRanks\n
03561   *         SQR2     SQ6            LL_ADC_REG_SetSequencerRanks\n
03562   *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n
03563   *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n
03564   *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n
03565   *         SQR3     SQ10           LL_ADC_REG_SetSequencerRanks\n
03566   *         SQR3     SQ11           LL_ADC_REG_SetSequencerRanks\n
03567   *         SQR3     SQ12           LL_ADC_REG_SetSequencerRanks\n
03568   *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n
03569   *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n
03570   *         SQR4     SQ15           LL_ADC_REG_SetSequencerRanks\n
03571   *         SQR4     SQ16           LL_ADC_REG_SetSequencerRanks
03572   * @param  ADCx ADC instance
03573   * @param  Rank This parameter can be one of the following values:
03574   *         @arg @ref LL_ADC_REG_RANK_1
03575   *         @arg @ref LL_ADC_REG_RANK_2
03576   *         @arg @ref LL_ADC_REG_RANK_3
03577   *         @arg @ref LL_ADC_REG_RANK_4
03578   *         @arg @ref LL_ADC_REG_RANK_5
03579   *         @arg @ref LL_ADC_REG_RANK_6
03580   *         @arg @ref LL_ADC_REG_RANK_7
03581   *         @arg @ref LL_ADC_REG_RANK_8
03582   *         @arg @ref LL_ADC_REG_RANK_9
03583   *         @arg @ref LL_ADC_REG_RANK_10
03584   *         @arg @ref LL_ADC_REG_RANK_11
03585   *         @arg @ref LL_ADC_REG_RANK_12
03586   *         @arg @ref LL_ADC_REG_RANK_13
03587   *         @arg @ref LL_ADC_REG_RANK_14
03588   *         @arg @ref LL_ADC_REG_RANK_15
03589   *         @arg @ref LL_ADC_REG_RANK_16
03590   * @param  Channel This parameter can be one of the following values:
03591   *         @arg @ref LL_ADC_CHANNEL_0
03592   *         @arg @ref LL_ADC_CHANNEL_1
03593   *         @arg @ref LL_ADC_CHANNEL_2
03594   *         @arg @ref LL_ADC_CHANNEL_3
03595   *         @arg @ref LL_ADC_CHANNEL_4
03596   *         @arg @ref LL_ADC_CHANNEL_5
03597   *         @arg @ref LL_ADC_CHANNEL_6
03598   *         @arg @ref LL_ADC_CHANNEL_7
03599   *         @arg @ref LL_ADC_CHANNEL_8
03600   *         @arg @ref LL_ADC_CHANNEL_9
03601   *         @arg @ref LL_ADC_CHANNEL_10
03602   *         @arg @ref LL_ADC_CHANNEL_11
03603   *         @arg @ref LL_ADC_CHANNEL_12
03604   *         @arg @ref LL_ADC_CHANNEL_13
03605   *         @arg @ref LL_ADC_CHANNEL_14
03606   *         @arg @ref LL_ADC_CHANNEL_15
03607   *         @arg @ref LL_ADC_CHANNEL_16
03608   *         @arg @ref LL_ADC_CHANNEL_17
03609   *         @arg @ref LL_ADC_CHANNEL_18
03610   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
03611   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
03612   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
03613   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
03614   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
03615   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
03616   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
03617   *
03618   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
03619   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
03620   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
03621   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
03622   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
03623   *             only one ADC instance is allowed to be connected to VrefInt at the same time.
03624   * @retval None
03625   */
03626 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
03627 {
03628   /* Set bits with content of parameter "Channel" with bits position          */
03629   /* in register and register position depending on parameter "Rank".         */
03630   /* Parameters "Rank" and "Channel" are used with masks because containing   */
03631   /* other bits reserved for other purpose.                                   */
03632   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
03633
03634   MODIFY_REG(*preg,
03635              ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
03636              (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK)));
03637 }
03638
03639 /**
03640   * @brief  Get ADC group regular sequence: channel on the selected
03641   *         scan sequence rank.
03642   * @note   On this STM32 serie, ADC group regular sequencer is
03643   *         fully configurable: sequencer length and each rank
03644   *         affectation to a channel are configurable.
03645   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
03646   * @note   Depending on devices and packages, some channels may not be available.
03647   *         Refer to device datasheet for channels availability.
03648   * @note   Usage of the returned channel number:
03649   *         - To reinject this channel into another function LL_ADC_xxx:
03650   *           the returned channel number is only partly formatted on definition
03651   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
03652   *           with parts of literals LL_ADC_CHANNEL_x or using
03653   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
03654   *           Then the selected literal LL_ADC_CHANNEL_x can be used
03655   *           as parameter for another function.
03656   *         - To get the channel number in decimal format:
03657   *           process the returned value with the helper macro
03658   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
03659   * @rmtoll SQR1     SQ1            LL_ADC_REG_GetSequencerRanks\n
03660   *         SQR1     SQ2            LL_ADC_REG_GetSequencerRanks\n
03661   *         SQR1     SQ3            LL_ADC_REG_GetSequencerRanks\n
03662   *         SQR1     SQ4            LL_ADC_REG_GetSequencerRanks\n
03663   *         SQR2     SQ5            LL_ADC_REG_GetSequencerRanks\n
03664   *         SQR2     SQ6            LL_ADC_REG_GetSequencerRanks\n
03665   *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n
03666   *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n
03667   *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n
03668   *         SQR3     SQ10           LL_ADC_REG_GetSequencerRanks\n
03669   *         SQR3     SQ11           LL_ADC_REG_GetSequencerRanks\n
03670   *         SQR3     SQ12           LL_ADC_REG_GetSequencerRanks\n
03671   *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n
03672   *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n
03673   *         SQR4     SQ15           LL_ADC_REG_GetSequencerRanks\n
03674   *         SQR4     SQ16           LL_ADC_REG_GetSequencerRanks
03675   * @param  ADCx ADC instance
03676   * @param  Rank This parameter can be one of the following values:
03677   *         @arg @ref LL_ADC_REG_RANK_1
03678   *         @arg @ref LL_ADC_REG_RANK_2
03679   *         @arg @ref LL_ADC_REG_RANK_3
03680   *         @arg @ref LL_ADC_REG_RANK_4
03681   *         @arg @ref LL_ADC_REG_RANK_5
03682   *         @arg @ref LL_ADC_REG_RANK_6
03683   *         @arg @ref LL_ADC_REG_RANK_7
03684   *         @arg @ref LL_ADC_REG_RANK_8
03685   *         @arg @ref LL_ADC_REG_RANK_9
03686   *         @arg @ref LL_ADC_REG_RANK_10
03687   *         @arg @ref LL_ADC_REG_RANK_11
03688   *         @arg @ref LL_ADC_REG_RANK_12
03689   *         @arg @ref LL_ADC_REG_RANK_13
03690   *         @arg @ref LL_ADC_REG_RANK_14
03691   *         @arg @ref LL_ADC_REG_RANK_15
03692   *         @arg @ref LL_ADC_REG_RANK_16
03693   * @retval Returned value can be one of the following values:
03694   *         @arg @ref LL_ADC_CHANNEL_0
03695   *         @arg @ref LL_ADC_CHANNEL_1
03696   *         @arg @ref LL_ADC_CHANNEL_2
03697   *         @arg @ref LL_ADC_CHANNEL_3
03698   *         @arg @ref LL_ADC_CHANNEL_4
03699   *         @arg @ref LL_ADC_CHANNEL_5
03700   *         @arg @ref LL_ADC_CHANNEL_6
03701   *         @arg @ref LL_ADC_CHANNEL_7
03702   *         @arg @ref LL_ADC_CHANNEL_8
03703   *         @arg @ref LL_ADC_CHANNEL_9
03704   *         @arg @ref LL_ADC_CHANNEL_10
03705   *         @arg @ref LL_ADC_CHANNEL_11
03706   *         @arg @ref LL_ADC_CHANNEL_12
03707   *         @arg @ref LL_ADC_CHANNEL_13
03708   *         @arg @ref LL_ADC_CHANNEL_14
03709   *         @arg @ref LL_ADC_CHANNEL_15
03710   *         @arg @ref LL_ADC_CHANNEL_16
03711   *         @arg @ref LL_ADC_CHANNEL_17
03712   *         @arg @ref LL_ADC_CHANNEL_18
03713   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
03714   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
03715   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
03716   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
03717   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
03718   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
03719   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
03720   *
03721   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
03722   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
03723   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
03724   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
03725   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
03726   *             only one ADC instance is allowed to be connected to VrefInt at the same time.\n
03727   *         (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
03728   *                         comparison with internal channel parameter to be done
03729   *                         using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
03730   */
03731 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
03732 {
03733   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
03734
03735   return (uint32_t) (READ_BIT(*preg,
03736                               ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
03737                      << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK))
03738                     );
03739 }
03740
03741 /**
03742   * @brief  Set ADC continuous conversion mode on ADC group regular.
03743   * @note   Description of ADC continuous conversion mode:
03744   *         - single mode: one conversion per trigger
03745   *         - continuous mode: after the first trigger, following
03746   *           conversions launched successively automatically.
03747   * @note   It is not possible to enable both ADC group regular
03748   *         continuous mode and sequencer discontinuous mode.
03749   * @note   On this STM32 serie, setting of this feature is conditioned to
03750   *         ADC state:
03751   *         ADC must be disabled or enabled without conversion on going
03752   *         on group regular.
03753   * @rmtoll CFGR     CONT           LL_ADC_REG_SetContinuousMode
03754   * @param  ADCx ADC instance
03755   * @param  Continuous This parameter can be one of the following values:
03756   *         @arg @ref LL_ADC_REG_CONV_SINGLE
03757   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
03758   * @retval None
03759   */
03760 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
03761 {
03762   MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
03763 }
03764
03765 /**
03766   * @brief  Get ADC continuous conversion mode on ADC group regular.
03767   * @note   Description of ADC continuous conversion mode:
03768   *         - single mode: one conversion per trigger
03769   *         - continuous mode: after the first trigger, following
03770   *           conversions launched successively automatically.
03771   * @rmtoll CFGR     CONT           LL_ADC_REG_GetContinuousMode
03772   * @param  ADCx ADC instance
03773   * @retval Returned value can be one of the following values:
03774   *         @arg @ref LL_ADC_REG_CONV_SINGLE
03775   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
03776   */
03777 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
03778 {
03779   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
03780 }
03781
03782 /**
03783   * @brief  Set ADC group regular conversion data transfer: no transfer or
03784   *         transfer by DMA, and DMA requests mode.
03785   * @note   If transfer by DMA selected, specifies the DMA requests
03786   *         mode:
03787   *         - Limited mode (One shot mode): DMA transfer requests are stopped
03788   *           when number of DMA data transfers (number of
03789   *           ADC conversions) is reached.
03790   *           This ADC mode is intended to be used with DMA mode non-circular.
03791   *         - Unlimited mode: DMA transfer requests are unlimited,
03792   *           whatever number of DMA data transfers (number of
03793   *           ADC conversions).
03794   *           This ADC mode is intended to be used with DMA mode circular.
03795   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
03796   *         mode non-circular:
03797   *         when DMA transfers size will be reached, DMA will stop transfers of
03798   *         ADC conversions data ADC will raise an overrun error
03799   *        (overrun flag and interruption if enabled).
03800   * @note   For devices with several ADC instances: ADC multimode DMA
03801   *         settings are available using function @ref LL_ADC_SetMultiDMATransfer().
03802   * @note   To configure DMA source address (peripheral address),
03803   *         use function @ref LL_ADC_DMA_GetRegAddr().
03804   * @note   On this STM32 serie, setting of this feature is conditioned to
03805   *         ADC state:
03806   *         ADC must be disabled or enabled without conversion on going
03807   *         on either groups regular or injected.
03808   * @rmtoll CFGR     DMAEN          LL_ADC_REG_SetDMATransfer\n
03809   *         CFGR     DMACFG         LL_ADC_REG_SetDMATransfer
03810   * @param  ADCx ADC instance
03811   * @param  DMATransfer This parameter can be one of the following values:
03812   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
03813   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
03814   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
03815   * @retval None
03816   */
03817 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
03818 {
03819   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
03820 }
03821
03822 /**
03823   * @brief  Get ADC group regular conversion data transfer: no transfer or
03824   *         transfer by DMA, and DMA requests mode.
03825   * @note   If transfer by DMA selected, specifies the DMA requests
03826   *         mode:
03827   *         - Limited mode (One shot mode): DMA transfer requests are stopped
03828   *           when number of DMA data transfers (number of
03829   *           ADC conversions) is reached.
03830   *           This ADC mode is intended to be used with DMA mode non-circular.
03831   *         - Unlimited mode: DMA transfer requests are unlimited,
03832   *           whatever number of DMA data transfers (number of
03833   *           ADC conversions).
03834   *           This ADC mode is intended to be used with DMA mode circular.
03835   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
03836   *         mode non-circular:
03837   *         when DMA transfers size will be reached, DMA will stop transfers of
03838   *         ADC conversions data ADC will raise an overrun error
03839   *         (overrun flag and interruption if enabled).
03840   * @note   For devices with several ADC instances: ADC multimode DMA
03841   *         settings are available using function @ref LL_ADC_GetMultiDMATransfer().
03842   * @note   To configure DMA source address (peripheral address),
03843   *         use function @ref LL_ADC_DMA_GetRegAddr().
03844   * @rmtoll CFGR     DMAEN          LL_ADC_REG_GetDMATransfer\n
03845   *         CFGR     DMACFG         LL_ADC_REG_GetDMATransfer
03846   * @param  ADCx ADC instance
03847   * @retval Returned value can be one of the following values:
03848   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
03849   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
03850   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
03851   */
03852 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
03853 {
03854   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
03855 }
03856
03857 /**
03858   * @brief  Set ADC group regular behavior in case of overrun:
03859   *         data preserved or overwritten.
03860   * @note   Compatibility with devices without feature overrun:
03861   *         other devices without this feature have a behavior
03862   *         equivalent to data overwritten.
03863   *         The default setting of overrun is data preserved.
03864   *         Therefore, for compatibility with all devices, parameter
03865   *         overrun should be set to data overwritten.
03866   * @note   On this STM32 serie, setting of this feature is conditioned to
03867   *         ADC state:
03868   *         ADC must be disabled or enabled without conversion on going
03869   *         on group regular.
03870   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_SetOverrun
03871   * @param  ADCx ADC instance
03872   * @param  Overrun This parameter can be one of the following values:
03873   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
03874   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
03875   * @retval None
03876   */
03877 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
03878 {
03879   MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
03880 }
03881
03882 /**
03883   * @brief  Get ADC group regular behavior in case of overrun:
03884   *         data preserved or overwritten.
03885   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_GetOverrun
03886   * @param  ADCx ADC instance
03887   * @retval Returned value can be one of the following values:
03888   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
03889   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
03890   */
03891 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
03892 {
03893   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
03894 }
03895
03896 /**
03897   * @}
03898   */
03899
03900 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
03901   * @{
03902   */
03903
03904 /**
03905   * @brief  Set ADC group injected conversion trigger source:
03906   *         internal (SW start) or from external IP (timer event,
03907   *         external interrupt line).
03908   * @note   On this STM32 serie, setting trigger source to external trigger
03909   *         also set trigger polarity to rising edge
03910   *         (default setting for compatibility with some ADC on other
03911   *         STM32 families having this setting set by HW default value).
03912   *         In case of need to modify trigger edge, use
03913   *         function @ref LL_ADC_INJ_SetTriggerEdge().
03914   * @note   Caution to ADC group injected contexts queue: On this STM32 serie,
03915   *         using successively several times this function will appear has
03916   *         having no effect.
03917   *         This is due to ADC group injected contexts queue (this feature
03918   *         cannot be disabled on this STM32 serie).
03919   *         To set several features of ADC group injected, use
03920   *         function @ref LL_ADC_INJ_ConfigQueueContext().
03921   * @note   Availability of parameters of trigger sources from timer
03922   *         depends on timers availability on the selected device.
03923   * @note   On this STM32 serie, setting of this feature is conditioned to
03924   *         ADC state:
03925   *         ADC must not be disabled. Can be enabled with or without conversion
03926   *         on going on either groups regular or injected.
03927   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_SetTriggerSource\n
03928   *         JSQR     JEXTEN         LL_ADC_INJ_SetTriggerSource
03929   * @param  ADCx ADC instance
03930   * @param  TriggerSource This parameter can be one of the following values:
03931   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
03932   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
03933   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
03934   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34    (1)(2)               (8)
03935   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
03936   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO               (3)(4)(5)
03937   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12   (1)(2)            (7)
03938   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34  (1)(2)               (8)
03939   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1                (3)(4)(5)
03940   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12    (1)(2)            (7)
03941   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO         (1)(2)(3)(4)(5)
03942   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1                (3)(4)(5)
03943   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12    (1)(2)            (7)
03944   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3                (3)(4)(5)
03945   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12    (1)(2)            (7)
03946   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4                (3)(4)(5)
03947   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12    (1)(2)(3)(4)(5)   (7)
03948   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO               (3)   (5)
03949   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12   (1)(2)            (7)
03950   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34  (1)(2)               (8)
03951   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34    (1)(2)               (8)
03952   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34    (1)(2)               (8)
03953   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO               (3)(4)(5)
03954   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12   (1)(2)            (7)
03955   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34   (1)(2)               (8)
03956   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO         (1)(2)
03957   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2        (1)(2)
03958   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34    (1)(2)               (8)
03959   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12    (1)(2)            (7)
03960   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34   (1)(2)               (8)
03961   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
03962   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12  (1)               (7)
03963   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (1)               (7)
03964   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12   (1)               (7)
03965   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34   (1)                  (8)
03966   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34  (1)                  (8)
03967   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2_ADC34   (1)                  (8)
03968   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2                 (4)
03969   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4                 (4)
03970   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15             (3)(4)(5)(6)
03971   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (1)(2)            (7)
03972   *
03973   *         (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
03974   *         (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
03975   *         (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
03976   *         (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
03977   *         (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
03978   *         (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
03979   *         (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
03980   *         (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
03981   * @retval None
03982   */
03983 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
03984 {
03985   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
03986 }
03987
03988 /**
03989   * @brief  Get ADC group injected conversion trigger source:
03990   *         internal (SW start) or from external IP (timer event,
03991   *         external interrupt line).
03992   * @note   To determine whether group injected trigger source is
03993   *         internal (SW start) or external, without detail
03994   *         of which peripheral is selected as external trigger,
03995   *         (equivalent to
03996   *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
03997   *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
03998   * @note   Availability of parameters of trigger sources from timer
03999   *         depends on timers availability on the selected device.
04000   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_GetTriggerSource\n
04001   *         JSQR     JEXTEN         LL_ADC_INJ_GetTriggerSource
04002   * @param  ADCx ADC instance
04003   * @retval Returned value can be one of the following values:
04004   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
04005   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
04006   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
04007   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34    (1)(2)               (8)
04008   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
04009   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO               (3)(4)(5)
04010   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12   (1)(2)            (7)
04011   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34  (1)(2)               (8)
04012   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1                (3)(4)(5)
04013   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12    (1)(2)            (7)
04014   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO         (1)(2)(3)(4)(5)
04015   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1                (3)(4)(5)
04016   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12    (1)(2)            (7)
04017   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3                (3)(4)(5)
04018   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12    (1)(2)            (7)
04019   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4                (3)(4)(5)
04020   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12    (1)(2)(3)(4)(5)   (7)
04021   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO               (3)   (5)
04022   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12   (1)(2)            (7)
04023   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34  (1)(2)               (8)
04024   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34    (1)(2)               (8)
04025   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34    (1)(2)               (8)
04026   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO               (3)(4)(5)
04027   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12   (1)(2)            (7)
04028   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34   (1)(2)               (8)
04029   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO         (1)(2)
04030   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2        (1)(2)
04031   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34    (1)(2)               (8)
04032   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12    (1)(2)            (7)
04033   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34   (1)(2)               (8)
04034   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
04035   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12  (1)               (7)
04036   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (1)               (7)
04037   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12   (1)               (7)
04038   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34   (1)                  (8)
04039   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34  (1)                  (8)
04040   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2_ADC34   (1)                  (8)
04041   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2                 (4)
04042   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4                 (4)
04043   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15             (3)(4)(5)(6)
04044   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (1)(2)            (7)
04045   *
04046   *         (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
04047   *         (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
04048   *         (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
04049   *         (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
04050   *         (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
04051   *         (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
04052   *         (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
04053   *         (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
04054   */
04055 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
04056 {
04057   register uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
04058
04059   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
04060   /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */
04061   register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
04062
04063   /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */
04064   /* to match with triggers literals definition.                              */
04065   return ((TriggerSource
04066            & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
04067           | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
04068          );
04069 }
04070
04071 /**
04072   * @brief  Get ADC group injected conversion trigger source internal (SW start)
04073             or external
04074   * @note   In case of group injected trigger source set to external trigger,
04075   *         to determine which peripheral is selected as external trigger,
04076   *         use function @ref LL_ADC_INJ_GetTriggerSource.
04077   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart
04078   * @param  ADCx ADC instance
04079   * @retval Value "0" if trigger source external trigger
04080   *         Value "1" if trigger source SW start.
04081   */
04082 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
04083 {
04084   return (READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN));
04085 }
04086
04087 /**
04088   * @brief  Set ADC group injected conversion trigger polarity.
04089   *         Applicable only for trigger source set to external trigger.
04090   * @note   On this STM32 serie, setting of this feature is conditioned to
04091   *         ADC state:
04092   *         ADC must not be disabled. Can be enabled with or without conversion
04093   *         on going on either groups regular or injected.
04094   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_SetTriggerEdge
04095   * @param  ADCx ADC instance
04096   * @param  ExternalTriggerEdge This parameter can be one of the following values:
04097   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
04098   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
04099   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
04100   * @retval None
04101   */
04102 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
04103 {
04104   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
04105 }
04106
04107 /**
04108   * @brief  Get ADC group injected conversion trigger polarity.
04109   *         Applicable only for trigger source set to external trigger.
04110   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_GetTriggerEdge
04111   * @param  ADCx ADC instance
04112   * @retval Returned value can be one of the following values:
04113   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
04114   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
04115   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
04116   */
04117 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
04118 {
04119   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
04120 }
04121
04122 /**
04123   * @brief  Set ADC group injected sequencer length and scan direction.
04124   * @note   This function performs configuration of:
04125   *         - Sequence length: Number of ranks in the scan sequence.
04126   *         - Sequence direction: Unless specified in parameters, sequencer
04127   *           scan direction is forward (from rank 1 to rank n).
04128   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
04129   *         ADC conversion on only 1 channel.
04130   * @note   Caution to ADC group injected contexts queue: On this STM32 serie,
04131   *         using successively several times this function will appear has
04132   *         having no effect.
04133   *         This is due to ADC group injected contexts queue (this feature
04134   *         cannot be disabled on this STM32 serie).
04135   *         To set several features of ADC group injected, use
04136   *         function @ref LL_ADC_INJ_ConfigQueueContext().
04137   * @note   On this STM32 serie, setting of this feature is conditioned to
04138   *         ADC state:
04139   *         ADC must not be disabled. Can be enabled with or without conversion
04140   *         on going on either groups regular or injected.
04141   * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength
04142   * @param  ADCx ADC instance
04143   * @param  SequencerNbRanks This parameter can be one of the following values:
04144   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
04145   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
04146   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
04147   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
04148   * @retval None
04149   */
04150 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
04151 {
04152   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
04153 }
04154
04155 /**
04156   * @brief  Get ADC group injected sequencer length and scan direction.
04157   * @note   This function retrieves:
04158   *         - Sequence length: Number of ranks in the scan sequence.
04159   *         - Sequence direction: Unless specified in parameters, sequencer
04160   *           scan direction is forward (from rank 1 to rank n).
04161   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
04162   *         ADC conversion on only 1 channel.
04163   * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength
04164   * @param  ADCx ADC instance
04165   * @retval Returned value can be one of the following values:
04166   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
04167   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
04168   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
04169   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
04170   */
04171 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
04172 {
04173   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
04174 }
04175
04176 /**
04177   * @brief  Set ADC group injected sequencer discontinuous mode:
04178   *         sequence subdivided and scan conversions interrupted every selected
04179   *         number of ranks.
04180   * @note   It is not possible to enable both ADC group injected
04181   *         auto-injected mode and sequencer discontinuous mode.
04182   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_SetSequencerDiscont
04183   * @param  ADCx ADC instance
04184   * @param  SeqDiscont This parameter can be one of the following values:
04185   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
04186   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
04187   * @retval None
04188   */
04189 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
04190 {
04191   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
04192 }
04193
04194 /**
04195   * @brief  Get ADC group injected sequencer discontinuous mode:
04196   *         sequence subdivided and scan conversions interrupted every selected
04197   *         number of ranks.
04198   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_GetSequencerDiscont
04199   * @param  ADCx ADC instance
04200   * @retval Returned value can be one of the following values:
04201   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
04202   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
04203   */
04204 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
04205 {
04206   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
04207 }
04208
04209 /**
04210   * @brief  Set ADC group injected sequence: channel on the selected
04211   *         sequence rank.
04212   * @note   Depending on devices and packages, some channels may not be available.
04213   *         Refer to device datasheet for channels availability.
04214   * @note   On this STM32 serie, to measure internal channels (VrefInt,
04215   *         TempSensor, ...), measurement paths to internal channels must be
04216   *         enabled separately.
04217   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
04218   * @note   Caution to ADC group injected contexts queue: On this STM32 serie,
04219   *         using successively several times this function will appear has
04220   *         having no effect.
04221   *         This is due to ADC group injected contexts queue (this feature
04222   *         cannot be disabled on this STM32 serie).
04223   *         To set several features of ADC group injected, use
04224   *         function @ref LL_ADC_INJ_ConfigQueueContext().
04225   * @note   On this STM32 serie, setting of this feature is conditioned to
04226   *         ADC state:
04227   *         ADC must not be disabled. Can be enabled with or without conversion
04228   *         on going on either groups regular or injected.
04229   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
04230   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
04231   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
04232   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
04233   * @param  ADCx ADC instance
04234   * @param  Rank This parameter can be one of the following values:
04235   *         @arg @ref LL_ADC_INJ_RANK_1
04236   *         @arg @ref LL_ADC_INJ_RANK_2
04237   *         @arg @ref LL_ADC_INJ_RANK_3
04238   *         @arg @ref LL_ADC_INJ_RANK_4
04239   * @param  Channel This parameter can be one of the following values:
04240   *         @arg @ref LL_ADC_CHANNEL_0
04241   *         @arg @ref LL_ADC_CHANNEL_1
04242   *         @arg @ref LL_ADC_CHANNEL_2
04243   *         @arg @ref LL_ADC_CHANNEL_3
04244   *         @arg @ref LL_ADC_CHANNEL_4
04245   *         @arg @ref LL_ADC_CHANNEL_5
04246   *         @arg @ref LL_ADC_CHANNEL_6
04247   *         @arg @ref LL_ADC_CHANNEL_7
04248   *         @arg @ref LL_ADC_CHANNEL_8
04249   *         @arg @ref LL_ADC_CHANNEL_9
04250   *         @arg @ref LL_ADC_CHANNEL_10
04251   *         @arg @ref LL_ADC_CHANNEL_11
04252   *         @arg @ref LL_ADC_CHANNEL_12
04253   *         @arg @ref LL_ADC_CHANNEL_13
04254   *         @arg @ref LL_ADC_CHANNEL_14
04255   *         @arg @ref LL_ADC_CHANNEL_15
04256   *         @arg @ref LL_ADC_CHANNEL_16
04257   *         @arg @ref LL_ADC_CHANNEL_17
04258   *         @arg @ref LL_ADC_CHANNEL_18
04259   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
04260   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
04261   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
04262   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
04263   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
04264   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
04265   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
04266   *
04267   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
04268   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
04269   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
04270   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
04271   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
04272   *             only one ADC instance is allowed to be connected to VrefInt at the same time.
04273   * @retval None
04274   */
04275 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
04276 {
04277   /* Set bits with content of parameter "Channel" with bits position          */
04278   /* in register depending on parameter "Rank".                               */
04279   /* Parameters "Rank" and "Channel" are used with masks because containing   */
04280   /* other bits reserved for other purpose.                                   */
04281   MODIFY_REG(ADCx->JSQR,
04282              ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)),
04283              (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)));
04284 }
04285
04286 /**
04287   * @brief  Get ADC group injected sequence: channel on the selected
04288   *         sequence rank.
04289   * @note   Depending on devices and packages, some channels may not be available.
04290   *         Refer to device datasheet for channels availability.
04291   * @note   Usage of the returned channel number:
04292   *         - To reinject this channel into another function LL_ADC_xxx:
04293   *           the returned channel number is only partly formatted on definition
04294   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
04295   *           with parts of literals LL_ADC_CHANNEL_x or using
04296   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
04297   *           Then the selected literal LL_ADC_CHANNEL_x can be used
04298   *           as parameter for another function.
04299   *         - To get the channel number in decimal format:
04300   *           process the returned value with the helper macro
04301   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
04302   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_GetSequencerRanks\n
04303   *         JSQR     JSQ2           LL_ADC_INJ_GetSequencerRanks\n
04304   *         JSQR     JSQ3           LL_ADC_INJ_GetSequencerRanks\n
04305   *         JSQR     JSQ4           LL_ADC_INJ_GetSequencerRanks
04306   * @param  ADCx ADC instance
04307   * @param  Rank This parameter can be one of the following values:
04308   *         @arg @ref LL_ADC_INJ_RANK_1
04309   *         @arg @ref LL_ADC_INJ_RANK_2
04310   *         @arg @ref LL_ADC_INJ_RANK_3
04311   *         @arg @ref LL_ADC_INJ_RANK_4
04312   * @retval Returned value can be one of the following values:
04313   *         @arg @ref LL_ADC_CHANNEL_0
04314   *         @arg @ref LL_ADC_CHANNEL_1
04315   *         @arg @ref LL_ADC_CHANNEL_2
04316   *         @arg @ref LL_ADC_CHANNEL_3
04317   *         @arg @ref LL_ADC_CHANNEL_4
04318   *         @arg @ref LL_ADC_CHANNEL_5
04319   *         @arg @ref LL_ADC_CHANNEL_6
04320   *         @arg @ref LL_ADC_CHANNEL_7
04321   *         @arg @ref LL_ADC_CHANNEL_8
04322   *         @arg @ref LL_ADC_CHANNEL_9
04323   *         @arg @ref LL_ADC_CHANNEL_10
04324   *         @arg @ref LL_ADC_CHANNEL_11
04325   *         @arg @ref LL_ADC_CHANNEL_12
04326   *         @arg @ref LL_ADC_CHANNEL_13
04327   *         @arg @ref LL_ADC_CHANNEL_14
04328   *         @arg @ref LL_ADC_CHANNEL_15
04329   *         @arg @ref LL_ADC_CHANNEL_16
04330   *         @arg @ref LL_ADC_CHANNEL_17
04331   *         @arg @ref LL_ADC_CHANNEL_18
04332   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
04333   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
04334   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
04335   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
04336   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
04337   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
04338   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
04339   *
04340   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
04341   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
04342   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
04343   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
04344   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
04345   *             only one ADC instance is allowed to be connected to VrefInt at the same time.\n
04346   *         (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
04347   *                         comparison with internal channel parameter to be done
04348   *                         using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
04349   */
04350 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
04351 {
04352   return (uint32_t)(READ_BIT(ADCx->JSQR,
04353                              ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)))
04354                     << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
04355                    );
04356 }
04357
04358 /**
04359   * @brief  Set ADC group injected conversion trigger:
04360   *         independent or from ADC group regular.
04361   * @note   This mode can be used to extend number of data registers
04362   *         updated after one ADC conversion trigger and with data
04363   *         permanently kept (not erased by successive conversions of scan of
04364   *         ADC sequencer ranks), up to 5 data registers:
04365   *         1 data register on ADC group regular, 4 data registers
04366   *         on ADC group injected.
04367   * @note   If ADC group injected injected trigger source is set to an
04368   *         external trigger, this feature must be must be set to
04369   *         independent trigger.
04370   *         ADC group injected automatic trigger is compliant only with
04371   *         group injected trigger source set to SW start, without any
04372   *         further action on  ADC group injected conversion start or stop:
04373   *         in this case, ADC group injected is controlled only
04374   *         from ADC group regular.
04375   * @note   It is not possible to enable both ADC group injected
04376   *         auto-injected mode and sequencer discontinuous mode.
04377   * @note   On this STM32 serie, setting of this feature is conditioned to
04378   *         ADC state:
04379   *         ADC must be disabled or enabled without conversion on going
04380   *         on either groups regular or injected.
04381   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_SetTrigAuto
04382   * @param  ADCx ADC instance
04383   * @param  TrigAuto This parameter can be one of the following values:
04384   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
04385   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
04386   * @retval None
04387   */
04388 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
04389 {
04390   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
04391 }
04392
04393 /**
04394   * @brief  Get ADC group injected conversion trigger:
04395   *         independent or from ADC group regular.
04396   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_GetTrigAuto
04397   * @param  ADCx ADC instance
04398   * @retval Returned value can be one of the following values:
04399   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
04400   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
04401   */
04402 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
04403 {
04404   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
04405 }
04406
04407 /**
04408   * @brief  Set ADC group injected contexts queue mode.
04409   * @note   A context is a setting of group injected sequencer:
04410   *         - group injected trigger
04411   *         - sequencer length
04412   *         - sequencer ranks
04413   *         If contexts queue is disabled:
04414   *         - only 1 sequence can be configured
04415   *           and is active perpetually.
04416   *         If contexts queue is enabled:
04417   *         - up to 2 contexts can be queued
04418   *           and are checked in and out as a FIFO stack (first-in, first-out).
04419   *         - If a new context is set when queues is full, error is triggered
04420   *           by interruption "Injected Queue Overflow".
04421   *         - Two behaviors are possible when all contexts have been processed:
04422   *           the contexts queue can maintain the last context active perpetually
04423   *           or can be empty and injected group triggers are disabled.
04424   *         - Triggers can be only external (not internal SW start)
04425   *         - Caution: The sequence must be fully configured in one time
04426   *           (one write of register JSQR makes a check-in of a new context
04427   *           into the queue).
04428   *           Therefore functions to set separately injected trigger and
04429   *           sequencer channels cannot be used, register JSQR must be set
04430   *           using function @ref LL_ADC_INJ_ConfigQueueContext().
04431   * @note   This parameter can be modified only when no conversion is on going
04432   *         on either groups regular or injected.
04433   * @note   A modification of the context mode (bit JQDIS) causes the contexts
04434   *         queue to be flushed and the register JSQR is cleared.
04435   * @note   On this STM32 serie, setting of this feature is conditioned to
04436   *         ADC state:
04437   *         ADC must be disabled or enabled without conversion on going
04438   *         on either groups regular or injected.
04439   * @rmtoll CFGR     JQM            LL_ADC_INJ_SetQueueMode
04440   * @param  ADCx ADC instance
04441   * @param  QueueMode This parameter can be one of the following values:
04442   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
04443   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
04444   * @retval None
04445   */
04446 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
04447 {
04448   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM, QueueMode);
04449 }
04450
04451 /**
04452   * @brief  Get ADC group injected context queue mode.
04453   * @rmtoll CFGR     JQM            LL_ADC_INJ_GetQueueMode
04454   * @param  ADCx ADC instance
04455   * @retval Returned value can be one of the following values:
04456   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
04457   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
04458   */
04459 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
04460 {
04461   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM));
04462 }
04463
04464 /**
04465   * @brief  Set one context on ADC group injected that will be checked in
04466   *         contexts queue.
04467   * @note   A context is a setting of group injected sequencer:
04468   *         - group injected trigger
04469   *         - sequencer length
04470   *         - sequencer ranks
04471   *         This function is intended to be used when contexts queue is enabled,
04472   *         because the sequence must be fully configured in one time
04473   *         (functions to set separately injected trigger and sequencer channels
04474   *         cannot be used):
04475   *         Refer to function @ref LL_ADC_INJ_SetQueueMode().
04476   * @note   In the contexts queue, only the active context can be read.
04477   *         The parameters of this function can be read using functions:
04478   *         @arg @ref LL_ADC_INJ_GetTriggerSource()
04479   *         @arg @ref LL_ADC_INJ_GetTriggerEdge()
04480   *         @arg @ref LL_ADC_INJ_GetSequencerRanks()
04481   * @note   On this STM32 serie, to measure internal channels (VrefInt,
04482   *         TempSensor, ...), measurement paths to internal channels must be
04483   *         enabled separately.
04484   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
04485   * @note   On this STM32 serie, setting of this feature is conditioned to
04486   *         ADC state:
04487   *         ADC must not be disabled. Can be enabled with or without conversion
04488   *         on going on either groups regular or injected.
04489   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_ConfigQueueContext\n
04490   *         JSQR     JEXTEN         LL_ADC_INJ_ConfigQueueContext\n
04491   *         JSQR     JL             LL_ADC_INJ_ConfigQueueContext\n
04492   *         JSQR     JSQ1           LL_ADC_INJ_ConfigQueueContext\n
04493   *         JSQR     JSQ2           LL_ADC_INJ_ConfigQueueContext\n
04494   *         JSQR     JSQ3           LL_ADC_INJ_ConfigQueueContext\n
04495   *         JSQR     JSQ4           LL_ADC_INJ_ConfigQueueContext
04496   * @param  ADCx ADC instance
04497   * @param  TriggerSource This parameter can be one of the following values:
04498   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
04499   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
04500   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
04501   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34    (1)(2)               (8)
04502   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
04503   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO               (3)(4)(5)
04504   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12   (1)(2)            (7)
04505   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34  (1)(2)               (8)
04506   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1                (3)(4)(5)
04507   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12    (1)(2)            (7)
04508   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO         (1)(2)(3)(4)(5)
04509   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1                (3)(4)(5)
04510   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12    (1)(2)            (7)
04511   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3                (3)(4)(5)
04512   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12    (1)(2)            (7)
04513   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4                (3)(4)(5)
04514   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12    (1)(2)(3)(4)(5)   (7)
04515   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO               (3)   (5)
04516   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12   (1)(2)            (7)
04517   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34  (1)(2)               (8)
04518   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34    (1)(2)               (8)
04519   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34    (1)(2)               (8)
04520   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO               (3)(4)(5)
04521   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12   (1)(2)            (7)
04522   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34   (1)(2)               (8)
04523   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO         (1)(2)
04524   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2        (1)(2)
04525   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34    (1)(2)               (8)
04526   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12    (1)(2)            (7)
04527   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34   (1)(2)               (8)
04528   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
04529   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12  (1)               (7)
04530   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (1)               (7)
04531   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12   (1)               (7)
04532   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34   (1)                  (8)
04533   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34  (1)                  (8)
04534   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2_ADC34   (1)                  (8)
04535   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2                 (4)
04536   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4                 (4)
04537   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15             (3)(4)(5)(6)
04538   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (1)(2)            (7)
04539   *
04540   *         (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
04541   *         (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
04542   *         (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
04543   *         (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
04544   *         (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
04545   *         (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
04546   *         (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
04547   *         (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
04548   * @param  ExternalTriggerEdge This parameter can be one of the following values:
04549   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
04550   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
04551   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
04552   *
04553   *         Note: This parameter is discarded in case of SW start:
04554   *               parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
04555   * @param  SequencerNbRanks This parameter can be one of the following values:
04556   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
04557   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
04558   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
04559   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
04560   * @param  Rank1_Channel This parameter can be one of the following values:
04561   *         @arg @ref LL_ADC_CHANNEL_0
04562   *         @arg @ref LL_ADC_CHANNEL_1
04563   *         @arg @ref LL_ADC_CHANNEL_2
04564   *         @arg @ref LL_ADC_CHANNEL_3
04565   *         @arg @ref LL_ADC_CHANNEL_4
04566   *         @arg @ref LL_ADC_CHANNEL_5
04567   *         @arg @ref LL_ADC_CHANNEL_6
04568   *         @arg @ref LL_ADC_CHANNEL_7
04569   *         @arg @ref LL_ADC_CHANNEL_8
04570   *         @arg @ref LL_ADC_CHANNEL_9
04571   *         @arg @ref LL_ADC_CHANNEL_10
04572   *         @arg @ref LL_ADC_CHANNEL_11
04573   *         @arg @ref LL_ADC_CHANNEL_12
04574   *         @arg @ref LL_ADC_CHANNEL_13
04575   *         @arg @ref LL_ADC_CHANNEL_14
04576   *         @arg @ref LL_ADC_CHANNEL_15
04577   *         @arg @ref LL_ADC_CHANNEL_16
04578   *         @arg @ref LL_ADC_CHANNEL_17
04579   *         @arg @ref LL_ADC_CHANNEL_18
04580   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
04581   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
04582   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
04583   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
04584   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
04585   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
04586   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
04587   *
04588   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
04589   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
04590   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
04591   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
04592   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
04593   *             only one ADC instance is allowed to be connected to VrefInt at the same time.
04594   * @param  Rank2_Channel This parameter can be one of the following values:
04595   *         @arg @ref LL_ADC_CHANNEL_0
04596   *         @arg @ref LL_ADC_CHANNEL_1
04597   *         @arg @ref LL_ADC_CHANNEL_2
04598   *         @arg @ref LL_ADC_CHANNEL_3
04599   *         @arg @ref LL_ADC_CHANNEL_4
04600   *         @arg @ref LL_ADC_CHANNEL_5
04601   *         @arg @ref LL_ADC_CHANNEL_6
04602   *         @arg @ref LL_ADC_CHANNEL_7
04603   *         @arg @ref LL_ADC_CHANNEL_8
04604   *         @arg @ref LL_ADC_CHANNEL_9
04605   *         @arg @ref LL_ADC_CHANNEL_10
04606   *         @arg @ref LL_ADC_CHANNEL_11
04607   *         @arg @ref LL_ADC_CHANNEL_12
04608   *         @arg @ref LL_ADC_CHANNEL_13
04609   *         @arg @ref LL_ADC_CHANNEL_14
04610   *         @arg @ref LL_ADC_CHANNEL_15
04611   *         @arg @ref LL_ADC_CHANNEL_16
04612   *         @arg @ref LL_ADC_CHANNEL_17
04613   *         @arg @ref LL_ADC_CHANNEL_18
04614   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
04615   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
04616   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
04617   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
04618   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
04619   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
04620   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
04621   *
04622   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
04623   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
04624   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
04625   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
04626   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
04627   *             only one ADC instance is allowed to be connected to VrefInt at the same time.
04628   * @param  Rank3_Channel This parameter can be one of the following values:
04629   *         @arg @ref LL_ADC_CHANNEL_0
04630   *         @arg @ref LL_ADC_CHANNEL_1
04631   *         @arg @ref LL_ADC_CHANNEL_2
04632   *         @arg @ref LL_ADC_CHANNEL_3
04633   *         @arg @ref LL_ADC_CHANNEL_4
04634   *         @arg @ref LL_ADC_CHANNEL_5
04635   *         @arg @ref LL_ADC_CHANNEL_6
04636   *         @arg @ref LL_ADC_CHANNEL_7
04637   *         @arg @ref LL_ADC_CHANNEL_8
04638   *         @arg @ref LL_ADC_CHANNEL_9
04639   *         @arg @ref LL_ADC_CHANNEL_10
04640   *         @arg @ref LL_ADC_CHANNEL_11
04641   *         @arg @ref LL_ADC_CHANNEL_12
04642   *         @arg @ref LL_ADC_CHANNEL_13
04643   *         @arg @ref LL_ADC_CHANNEL_14
04644   *         @arg @ref LL_ADC_CHANNEL_15
04645   *         @arg @ref LL_ADC_CHANNEL_16
04646   *         @arg @ref LL_ADC_CHANNEL_17
04647   *         @arg @ref LL_ADC_CHANNEL_18
04648   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
04649   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
04650   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
04651   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
04652   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
04653   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
04654   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
04655   *
04656   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
04657   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
04658   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
04659   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
04660   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
04661   *             only one ADC instance is allowed to be connected to VrefInt at the same time.
04662   * @param  Rank4_Channel This parameter can be one of the following values:
04663   *         @arg @ref LL_ADC_CHANNEL_0
04664   *         @arg @ref LL_ADC_CHANNEL_1
04665   *         @arg @ref LL_ADC_CHANNEL_2
04666   *         @arg @ref LL_ADC_CHANNEL_3
04667   *         @arg @ref LL_ADC_CHANNEL_4
04668   *         @arg @ref LL_ADC_CHANNEL_5
04669   *         @arg @ref LL_ADC_CHANNEL_6
04670   *         @arg @ref LL_ADC_CHANNEL_7
04671   *         @arg @ref LL_ADC_CHANNEL_8
04672   *         @arg @ref LL_ADC_CHANNEL_9
04673   *         @arg @ref LL_ADC_CHANNEL_10
04674   *         @arg @ref LL_ADC_CHANNEL_11
04675   *         @arg @ref LL_ADC_CHANNEL_12
04676   *         @arg @ref LL_ADC_CHANNEL_13
04677   *         @arg @ref LL_ADC_CHANNEL_14
04678   *         @arg @ref LL_ADC_CHANNEL_15
04679   *         @arg @ref LL_ADC_CHANNEL_16
04680   *         @arg @ref LL_ADC_CHANNEL_17
04681   *         @arg @ref LL_ADC_CHANNEL_18
04682   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
04683   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
04684   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
04685   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
04686   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
04687   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
04688   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
04689   *
04690   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
04691   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
04692   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
04693   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
04694   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
04695   *             only one ADC instance is allowed to be connected to VrefInt at the same time.
04696   * @retval None
04697   */
04698 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
04699                                                    uint32_t TriggerSource,
04700                                                    uint32_t ExternalTriggerEdge,
04701                                                    uint32_t SequencerNbRanks,
04702                                                    uint32_t Rank1_Channel,
04703                                                    uint32_t Rank2_Channel,
04704                                                    uint32_t Rank3_Channel,
04705                                                    uint32_t Rank4_Channel)
04706 {
04707   /* Set bits with content of parameter "Rankx_Channel" with bits position    */
04708   /* in register depending on literal "LL_ADC_INJ_RANK_x".                    */
04709   /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks   */
04710   /* because containing other bits reserved for other purpose.                */
04711   /* If parameter "TriggerSource" is set to SW start, then parameter          */
04712   /* "ExternalTriggerEdge" is discarded.                                      */
04713   MODIFY_REG(ADCx->JSQR           ,
04714              ADC_JSQR_JEXTSEL |
04715              ADC_JSQR_JEXTEN  |
04716              ADC_JSQR_JSQ4    |
04717              ADC_JSQR_JSQ3    |
04718              ADC_JSQR_JSQ2    |
04719              ADC_JSQR_JSQ1    |
04720              ADC_JSQR_JL          ,
04721              TriggerSource       |
04722              (ExternalTriggerEdge * ((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE))) |
04723              ((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK))) |
04724              ((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK))) |
04725              ((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK))) |
04726              ((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK))) |
04727              SequencerNbRanks
04728             );
04729 }
04730
04731 /**
04732   * @}
04733   */
04734
04735 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
04736   * @{
04737   */
04738
04739 /**
04740   * @brief  Set sampling time of the selected ADC channel
04741   *         Unit: ADC clock cycles.
04742   * @note   On this device, sampling time is on channel scope: independently
04743   *         of channel mapped on ADC group regular or injected.
04744   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
04745   *         converted:
04746   *         sampling time constraints must be respected (sampling time can be
04747   *         adjusted in function of ADC clock frequency and sampling time
04748   *         setting).
04749   *         Refer to device datasheet for timings values (parameters TS_vrefint,
04750   *         TS_temp, ...).
04751   * @note   Conversion time is the addition of sampling time and processing time.
04752   *         On this STM32 serie, ADC processing time is:
04753   *         - 12.5 ADC clock cycles at ADC resolution 12 bits
04754   *         - 10.5 ADC clock cycles at ADC resolution 10 bits
04755   *         - 8.5 ADC clock cycles at ADC resolution 8 bits
04756   *         - 6.5 ADC clock cycles at ADC resolution 6 bits
04757   * @note   In case of ADC conversion of internal channel (VrefInt,
04758   *         temperature sensor, ...), a sampling time minimum value
04759   *         is required.
04760   *         Refer to device datasheet.
04761   * @note   On this STM32 serie, setting of this feature is conditioned to
04762   *         ADC state:
04763   *         ADC must be disabled or enabled without conversion on going
04764   *         on either groups regular or injected.
04765   * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\n
04766   *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\n
04767   *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\n
04768   *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\n
04769   *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\n
04770   *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\n
04771   *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\n
04772   *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\n
04773   *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\n
04774   *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\n
04775   *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n
04776   *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n
04777   *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n
04778   *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n
04779   *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n
04780   *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n
04781   *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n
04782   *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n
04783   *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime
04784   * @param  ADCx ADC instance
04785   * @param  Channel This parameter can be one of the following values:
04786   *         @arg @ref LL_ADC_CHANNEL_0
04787   *         @arg @ref LL_ADC_CHANNEL_1
04788   *         @arg @ref LL_ADC_CHANNEL_2
04789   *         @arg @ref LL_ADC_CHANNEL_3
04790   *         @arg @ref LL_ADC_CHANNEL_4
04791   *         @arg @ref LL_ADC_CHANNEL_5
04792   *         @arg @ref LL_ADC_CHANNEL_6
04793   *         @arg @ref LL_ADC_CHANNEL_7
04794   *         @arg @ref LL_ADC_CHANNEL_8
04795   *         @arg @ref LL_ADC_CHANNEL_9
04796   *         @arg @ref LL_ADC_CHANNEL_10
04797   *         @arg @ref LL_ADC_CHANNEL_11
04798   *         @arg @ref LL_ADC_CHANNEL_12
04799   *         @arg @ref LL_ADC_CHANNEL_13
04800   *         @arg @ref LL_ADC_CHANNEL_14
04801   *         @arg @ref LL_ADC_CHANNEL_15
04802   *         @arg @ref LL_ADC_CHANNEL_16
04803   *         @arg @ref LL_ADC_CHANNEL_17
04804   *         @arg @ref LL_ADC_CHANNEL_18
04805   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
04806   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
04807   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
04808   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
04809   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
04810   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
04811   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
04812   *
04813   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
04814   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
04815   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
04816   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
04817   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
04818   *             only one ADC instance is allowed to be connected to VrefInt at the same time.
04819   * @param  SamplingTime This parameter can be one of the following values:
04820   *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
04821   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
04822   *         @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES_5
04823   *         @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
04824   *         @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
04825   *         @arg @ref LL_ADC_SAMPLINGTIME_61CYCLES_5
04826   *         @arg @ref LL_ADC_SAMPLINGTIME_181CYCLES_5
04827   *         @arg @ref LL_ADC_SAMPLINGTIME_601CYCLES_5
04828   * @retval None
04829   */
04830 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
04831 {
04832   /* Set bits with content of parameter "SamplingTime" with bits position     */
04833   /* in register and register position depending on parameter "Channel".      */
04834   /* Parameter "Channel" is used with masks because containing                */
04835   /* other bits reserved for other purpose.                                   */
04836   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
04837
04838   MODIFY_REG(*preg,
04839              ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
04840              SamplingTime   << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
04841 }
04842
04843 /**
04844   * @brief  Get sampling time of the selected ADC channel
04845   *         Unit: ADC clock cycles.
04846   * @note   On this device, sampling time is on channel scope: independently
04847   *         of channel mapped on ADC group regular or injected.
04848   * @note   Conversion time is the addition of sampling time and processing time.
04849   *         On this STM32 serie, ADC processing time is:
04850   *         - 12.5 ADC clock cycles at ADC resolution 12 bits
04851   *         - 10.5 ADC clock cycles at ADC resolution 10 bits
04852   *         - 8.5 ADC clock cycles at ADC resolution 8 bits
04853   *         - 6.5 ADC clock cycles at ADC resolution 6 bits
04854   * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\n
04855   *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\n
04856   *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\n
04857   *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\n
04858   *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\n
04859   *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\n
04860   *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\n
04861   *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\n
04862   *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\n
04863   *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\n
04864   *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n
04865   *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n
04866   *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n
04867   *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n
04868   *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n
04869   *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n
04870   *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n
04871   *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n
04872   *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime
04873   * @param  ADCx ADC instance
04874   * @param  Channel This parameter can be one of the following values:
04875   *         @arg @ref LL_ADC_CHANNEL_0
04876   *         @arg @ref LL_ADC_CHANNEL_1
04877   *         @arg @ref LL_ADC_CHANNEL_2
04878   *         @arg @ref LL_ADC_CHANNEL_3
04879   *         @arg @ref LL_ADC_CHANNEL_4
04880   *         @arg @ref LL_ADC_CHANNEL_5
04881   *         @arg @ref LL_ADC_CHANNEL_6
04882   *         @arg @ref LL_ADC_CHANNEL_7
04883   *         @arg @ref LL_ADC_CHANNEL_8
04884   *         @arg @ref LL_ADC_CHANNEL_9
04885   *         @arg @ref LL_ADC_CHANNEL_10
04886   *         @arg @ref LL_ADC_CHANNEL_11
04887   *         @arg @ref LL_ADC_CHANNEL_12
04888   *         @arg @ref LL_ADC_CHANNEL_13
04889   *         @arg @ref LL_ADC_CHANNEL_14
04890   *         @arg @ref LL_ADC_CHANNEL_15
04891   *         @arg @ref LL_ADC_CHANNEL_16
04892   *         @arg @ref LL_ADC_CHANNEL_17
04893   *         @arg @ref LL_ADC_CHANNEL_18
04894   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (5)
04895   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
04896   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
04897   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1      (1)
04898   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2      (2)
04899   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3      (3)
04900   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4      (4)
04901   *
04902   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
04903   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
04904   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
04905   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
04906   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
04907   *             only one ADC instance is allowed to be connected to VrefInt at the same time.
04908   * @retval Returned value can be one of the following values:
04909   *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
04910   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
04911   *         @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES_5
04912   *         @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
04913   *         @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
04914   *         @arg @ref LL_ADC_SAMPLINGTIME_61CYCLES_5
04915   *         @arg @ref LL_ADC_SAMPLINGTIME_181CYCLES_5
04916   *         @arg @ref LL_ADC_SAMPLINGTIME_601CYCLES_5
04917   */
04918 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
04919 {
04920   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
04921
04922   return (uint32_t)(READ_BIT(*preg,
04923                              ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
04924                     >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
04925                    );
04926 }
04927
04928 /**
04929   * @brief  Set mode single-ended or differential input of the selected
04930   *         ADC channel.
04931   * @note   Channel ending is on channel scope: independently of channel mapped
04932   *         on ADC group regular or injected.
04933   *         In differential mode: Differential measurement is carried out
04934   *         between the selected channel 'i' (positive input) and
04935   *         channel 'i+1' (negative input). Only channel 'i' has to be
04936   *         configured, channel 'i+1' is configured automatically.
04937   * @note   Refer to Reference Manual to ensure the selected channel is
04938   *         available in differential mode.
04939   *         For example, internal channels (VrefInt, TempSensor, ...) are
04940   *         not available in differential mode.
04941   * @note   When configuring a channel 'i' in differential mode,
04942   *         the channel 'i+1' is not usable separately.
04943   * @note   On STM32F3, channels 16, 17, 18 of ADC1,
04944   *         channels 17, 18 of ADC2, ADC3, ADC4 (if available)
04945   *         are internally fixed to single-ended inputs configuration.
04946   * @note   For ADC channels configured in differential mode, both inputs
04947   *         should be biased at (Vref+)/2 +/-200mV.
04948   *         (Vref+ is the analog voltage reference)
04949   * @note   On this STM32 serie, setting of this feature is conditioned to
04950   *         ADC state:
04951   *         ADC must be ADC disabled.
04952   * @note   One or several values can be selected.
04953   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
04954   * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSamplingTime
04955   * @param  ADCx ADC instance
04956   * @param  Channel This parameter can be one of the following values:
04957   *         @arg @ref LL_ADC_CHANNEL_1
04958   *         @arg @ref LL_ADC_CHANNEL_2
04959   *         @arg @ref LL_ADC_CHANNEL_3
04960   *         @arg @ref LL_ADC_CHANNEL_4
04961   *         @arg @ref LL_ADC_CHANNEL_5
04962   *         @arg @ref LL_ADC_CHANNEL_6
04963   *         @arg @ref LL_ADC_CHANNEL_7
04964   *         @arg @ref LL_ADC_CHANNEL_8
04965   *         @arg @ref LL_ADC_CHANNEL_9
04966   *         @arg @ref LL_ADC_CHANNEL_10
04967   *         @arg @ref LL_ADC_CHANNEL_11
04968   *         @arg @ref LL_ADC_CHANNEL_12
04969   *         @arg @ref LL_ADC_CHANNEL_13
04970   *         @arg @ref LL_ADC_CHANNEL_14
04971   *         @arg @ref LL_ADC_CHANNEL_15
04972   *         @arg @ref LL_ADC_CHANNEL_16           (1)
04973   *
04974   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.
04975   * @param  SingleDiff This parameter can be a combination of the following values:
04976   *         @arg @ref LL_ADC_SINGLE_ENDED
04977   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
04978   * @retval None
04979   */
04980 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
04981 {
04982   /* Bits of channels in single or differential mode are set only for         */
04983   /* differential mode (for single mode, mask of bits allowed to be set is    */
04984   /* shifted out of range of bits of channels in single or differential mode. */
04985   MODIFY_REG(ADCx->DIFSEL,
04986              Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
04987              (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL << (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
04988 }
04989
04990 /**
04991   * @brief  Get mode single-ended or differential input of the selected
04992   *         ADC channel.
04993   * @note   When configuring a channel 'i' in differential mode,
04994   *         the channel 'i+1' is not usable separately.
04995   *         Therefore, to ensure a channel is configured in single-ended mode,
04996   *         the configuration of channel itself and the channel 'i-1' must be
04997   *         read back (to ensure that the selected channel channel has not been
04998   *         configured in differential mode by the previous channel).
04999   * @note   Refer to Reference Manual to ensure the selected channel is
05000   *         available in differential mode.
05001   *         For example, internal channels (VrefInt, TempSensor, ...) are
05002   *         not available in differential mode.
05003   * @note   When configuring a channel 'i' in differential mode,
05004   *         the channel 'i+1' is not usable separately.
05005   * @note   On STM32F3, channels 16, 17, 18 of ADC1,
05006   *         channels 17, 18 of ADC2, ADC3, ADC4 (if available)
05007   *         are internally fixed to single-ended inputs configuration.
05008   * @note   One or several values can be selected. In this case, the value
05009   *         returned is null if all channels are in single ended-mode.
05010   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
05011   * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSamplingTime
05012   * @param  ADCx ADC instance
05013   * @param  Channel This parameter can be a combination of the following values:
05014   *         @arg @ref LL_ADC_CHANNEL_0
05015   *         @arg @ref LL_ADC_CHANNEL_1
05016   *         @arg @ref LL_ADC_CHANNEL_2
05017   *         @arg @ref LL_ADC_CHANNEL_3
05018   *         @arg @ref LL_ADC_CHANNEL_4
05019   *         @arg @ref LL_ADC_CHANNEL_5
05020   *         @arg @ref LL_ADC_CHANNEL_6
05021   *         @arg @ref LL_ADC_CHANNEL_7
05022   *         @arg @ref LL_ADC_CHANNEL_8
05023   *         @arg @ref LL_ADC_CHANNEL_9
05024   *         @arg @ref LL_ADC_CHANNEL_10
05025   *         @arg @ref LL_ADC_CHANNEL_11
05026   *         @arg @ref LL_ADC_CHANNEL_12
05027   *         @arg @ref LL_ADC_CHANNEL_13
05028   *         @arg @ref LL_ADC_CHANNEL_14
05029   *         @arg @ref LL_ADC_CHANNEL_15
05030   *         @arg @ref LL_ADC_CHANNEL_16           (1)
05031   *
05032   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.
05033   * @retval 0: channel in single-ended mode, else: channel in differential mode
05034   */
05035 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
05036 {
05037   return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
05038 }
05039
05040 /**
05041   * @}
05042   */
05043
05044 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
05045   * @{
05046   */
05047
05048 /**
05049   * @brief  Set ADC analog watchdog monitored channels:
05050   *         a single channel, multiple channels or all channels,
05051   *         on ADC groups regular and-or injected.
05052   * @note   Once monitored channels are selected, analog watchdog
05053   *         is enabled.
05054   * @note   In case of need to define a single channel to monitor
05055   *         with analog watchdog from sequencer channel definition,
05056   *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
05057   * @note   On this STM32 serie, there are 2 kinds of analog watchdog
05058   *         instance:
05059   *         - AWD standard (instance AWD1):
05060   *           - channels monitored: can monitor 1 channel or all channels.
05061   *           - groups monitored: ADC groups regular and-or injected.
05062   *           - resolution: resolution is not limited (corresponds to
05063   *             ADC resolution configured).
05064   *         - AWD flexible (instances AWD2, AWD3):
05065   *           - channels monitored: flexible on channels monitored, selection is
05066   *             channel wise, from from 1 to all channels.
05067   *             Specificity of this analog watchdog: Multiple channels can
05068   *             be selected. For example:
05069   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
05070   *           - groups monitored: not selection possible (monitoring on both
05071   *             groups regular and injected).
05072   *             Channels selected are monitored on groups regular and injected:
05073   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
05074   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
05075   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
05076   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
05077   *             the 2 LSB are ignored.
05078   * @note   On this STM32 serie, setting of this feature is conditioned to
05079   *         ADC state:
05080   *         ADC must be disabled or enabled without conversion on going
05081   *         on either groups regular or injected.
05082   * @rmtoll CFGR     AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
05083   *         CFGR     AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
05084   *         CFGR     AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n
05085   *         CFGR     JAWD1EN        LL_ADC_SetAnalogWDMonitChannels\n
05086   *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n
05087   *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels
05088   * @param  ADCx ADC instance
05089   * @param  AWDy This parameter can be one of the following values:
05090   *         @arg @ref LL_ADC_AWD1
05091   *         @arg @ref LL_ADC_AWD2
05092   *         @arg @ref LL_ADC_AWD3
05093   * @param  AWDChannelGroup This parameter can be one of the following values:
05094   *         @arg @ref LL_ADC_AWD_DISABLE
05095   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
05096   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
05097   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
05098   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
05099   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
05100   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
05101   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
05102   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
05103   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
05104   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
05105   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
05106   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
05107   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
05108   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
05109   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
05110   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
05111   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
05112   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
05113   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
05114   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
05115   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
05116   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
05117   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
05118   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
05119   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
05120   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
05121   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
05122   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
05123   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
05124   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
05125   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
05126   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
05127   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
05128   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
05129   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
05130   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
05131   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
05132   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
05133   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
05134   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
05135   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
05136   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
05137   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
05138   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
05139   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
05140   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
05141   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
05142   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
05143   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
05144   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
05145   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
05146   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
05147   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
05148   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
05149   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
05150   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
05151   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
05152   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
05153   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
05154   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
05155   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(5)
05156   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(5)
05157   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (5)
05158   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(1)
05159   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(1)
05160   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (1)
05161   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(1)
05162   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(1)
05163   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (1)
05164   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG          (0)(1)
05165   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ          (0)(1)
05166   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ         (1)
05167   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG          (0)(2)
05168   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ          (0)(2)
05169   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ         (2)
05170   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG          (0)(3)
05171   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ          (0)(3)
05172   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ         (3)
05173   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG          (0)(4)
05174   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ          (0)(4)
05175   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ         (4)
05176   *
05177   *         (0) On STM32F3, parameter available only on analog watchdog number: AWD1.\n
05178   *         (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
05179   *         (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
05180   *         (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
05181   *         (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
05182   *         (5) On STM32F3, ADC channel available only on all ADC instances, but
05183   *             only one ADC instance is allowed to be connected to VrefInt at the same time.
05184   * @retval None
05185   */
05186 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
05187 {
05188   /* Set bits with content of parameter "AWDChannelGroup" with bits position  */
05189   /* in register and register position depending on parameter "AWDy".         */
05190   /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */
05191   /* containing other bits reserved for other purpose.                        */
05192   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
05193                                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
05194
05195   MODIFY_REG(*preg,
05196              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
05197              AWDChannelGroup & AWDy);
05198 }
05199
05200 /**
05201   * @brief  Get ADC analog watchdog monitored channel.
05202   * @note   Usage of the returned channel number:
05203   *         - To reinject this channel into another function LL_ADC_xxx:
05204   *           the returned channel number is only partly formatted on definition
05205   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
05206   *           with parts of literals LL_ADC_CHANNEL_x or using
05207   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
05208   *           Then the selected literal LL_ADC_CHANNEL_x can be used
05209   *           as parameter for another function.
05210   *         - To get the channel number in decimal format:
05211   *           process the returned value with the helper macro
05212   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
05213   *           Applicable only when the analog watchdog is set to monitor
05214   *           one channel.
05215   * @note   On this STM32 serie, there are 2 kinds of analog watchdog
05216   *         instance:
05217   *         - AWD standard (instance AWD1):
05218   *           - channels monitored: can monitor 1 channel or all channels.
05219   *           - groups monitored: ADC groups regular and-or injected.
05220   *           - resolution: resolution is not limited (corresponds to
05221   *             ADC resolution configured).
05222   *         - AWD flexible (instances AWD2, AWD3):
05223   *           - channels monitored: flexible on channels monitored, selection is
05224   *             channel wise, from from 1 to all channels.
05225   *             Specificity of this analog watchdog: Multiple channels can
05226   *             be selected. For example:
05227   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
05228   *           - groups monitored: not selection possible (monitoring on both
05229   *             groups regular and injected).
05230   *             Channels selected are monitored on groups regular and injected:
05231   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
05232   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
05233   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
05234   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
05235   *             the 2 LSB are ignored.
05236   * @note   On this STM32 serie, setting of this feature is conditioned to
05237   *         ADC state:
05238   *         ADC must be disabled or enabled without conversion on going
05239   *         on either groups regular or injected.
05240   * @rmtoll CFGR     AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
05241   *         CFGR     AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
05242   *         CFGR     AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n
05243   *         CFGR     JAWD1EN        LL_ADC_GetAnalogWDMonitChannels\n
05244   *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n
05245   *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels
05246   * @param  ADCx ADC instance
05247   * @param  AWDy This parameter can be one of the following values:
05248   *         @arg @ref LL_ADC_AWD1
05249   *         @arg @ref LL_ADC_AWD2 (1)
05250   *         @arg @ref LL_ADC_AWD3 (1)
05251   *
05252   *         (1) On this AWD number, monitored channel can be retrieved
05253   *             if only 1 channel is programmed (or none or all channels).
05254   *             This function cannot retrieve monitored channel if
05255   *             multiple channels are programmed simultaneously
05256   *             by bitfield.
05257   * @retval Returned value can be one of the following values:
05258   *         @arg @ref LL_ADC_AWD_DISABLE
05259   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
05260   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
05261   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
05262   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
05263   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
05264   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
05265   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
05266   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
05267   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
05268   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
05269   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
05270   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
05271   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
05272   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
05273   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
05274   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
05275   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
05276   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
05277   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
05278   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
05279   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
05280   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
05281   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
05282   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
05283   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
05284   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
05285   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
05286   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
05287   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
05288   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
05289   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
05290   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
05291   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
05292   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
05293   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
05294   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
05295   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
05296   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
05297   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
05298   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
05299   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
05300   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
05301   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
05302   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
05303   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
05304   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
05305   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
05306   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
05307   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
05308   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
05309   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
05310   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
05311   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
05312   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
05313   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
05314   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
05315   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
05316   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
05317   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
05318   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
05319   *
05320   *         (0) On STM32F3, parameter available only on analog watchdog number: AWD1.
05321   */
05322 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
05323 {
05324   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
05325                                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
05326
05327   /* Variable "AWDy" used to retrieve appropriate bitfield corresponding to   */
05328   /* ADC_AWD_CR1_CHANNEL_MASK or ADC_AWD_CR23_CHANNEL_MASK.                   */
05329   register uint32_t AWD123ChannelGroup = READ_BIT(*preg, (AWDy | ADC_AWD_CR_ALL_CHANNEL_MASK));
05330
05331   /* Set variable of AWD1 monitored channel according to AWD1 features        */
05332   /* and ADC channel definition:                                              */
05333   /* - channel ID with number                                                 */
05334   /* - channel ID with bitfield                                               */
05335   /* - AWD1 single or all channels                                            */
05336   /* - AWD1 enable or disable (also used to discard AWD1 bitfield in case of  */
05337   /*   AWD2 or AWD3 selected).                                                */
05338   register uint32_t AWD1ChannelSingle = ((AWD123ChannelGroup & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS);
05339
05340   register uint32_t AWD1ChannelGroup = ( (  AWD123ChannelGroup
05341                                           | ((ADC_CHANNEL_0_BITFIELD << ((AWD123ChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)) * AWD1ChannelSingle)
05342                                           | (ADC_CHANNEL_ID_BITFIELD_MASK * (~AWD1ChannelSingle & ((uint32_t)0x00000001U)))
05343                                          )
05344                                         * (((AWD123ChannelGroup & ADC_CFGR_JAWD1EN) >> ADC_CFGR_JAWD1EN_BITOFFSET_POS) | ((AWD123ChannelGroup & ADC_CFGR_AWD1EN) >> ADC_CFGR_AWD1EN_BITOFFSET_POS))
05345                                        );
05346
05347   /* Set variable of AWD2 and AWD3 monitored channel according to AWD2-3      */
05348   /* features and ADC channel definition:                                     */
05349   /* - channel ID with number                                                 */
05350   /* - channel ID with bitfield                                               */
05351   /* - AWD2-3 single or all channels (shift value 32 (0x1 shift 5) used to    */
05352   /*   shift AWD1 equivalent single-all channels out of register)             */
05353   /* - AWD2-3 enable or disable                                               */
05354   /* Note: Use modulo 3 to avoid a shift value too long. On AWD2 and AWD3,    */
05355   /*       channel can be read back if only 1 channel monitoring              */
05356   /*       is activated, therefore the channel monitoring value channel "3"   */
05357   /*       is not not supported by this function, there is no risk of         */
05358   /*       conflict.                                                          */
05359   register uint32_t AWD23Enabled = ((((uint32_t)0x00000001U) >> (AWD123ChannelGroup % 3U)) << 6U); /* Value "0" if AWD2-3 is enabled, value "32" if AWD2-3 is disabled */
05360
05361   register uint32_t AWD23ChannelGroup = (((  AWD123ChannelGroup
05362                                            | ((uint32_t)POSITION_VAL(AWD123ChannelGroup) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
05363                                            | ((ADC_CFGR_AWD1SGL) >> ((((uint32_t)0x00000001U) >> (ADC_AWD_CR23_CHANNEL_MASK - AWD123ChannelGroup)) << 5U))
05364                                            | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)
05365                                           ) >> AWD23Enabled
05366                                          ) >> (((AWDy & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS) << 5U));
05367
05368   return (AWD1ChannelGroup | AWD23ChannelGroup);
05369 }
05370
05371 /**
05372   * @brief  Set ADC analog watchdog thresholds value of both thresholds
05373   *         high and low.
05374   * @note   If value of only one threshold high or low must be set,
05375   *         use function @ref LL_ADC_SetAnalogWDThresholds().
05376   * @note   In case of ADC resolution different of 12 bits,
05377   *         analog watchdog thresholds data require a specific shift.
05378   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
05379   * @note   On this STM32 serie, there are 2 kinds of analog watchdog
05380   *         instance:
05381   *         - AWD standard (instance AWD1):
05382   *           - channels monitored: can monitor 1 channel or all channels.
05383   *           - groups monitored: ADC groups regular and-or injected.
05384   *           - resolution: resolution is not limited (corresponds to
05385   *             ADC resolution configured).
05386   *         - AWD flexible (instances AWD2, AWD3):
05387   *           - channels monitored: flexible on channels monitored, selection is
05388   *             channel wise, from from 1 to all channels.
05389   *             Specificity of this analog watchdog: Multiple channels can
05390   *             be selected. For example:
05391   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
05392   *           - groups monitored: not selection possible (monitoring on both
05393   *             groups regular and injected).
05394   *             Channels selected are monitored on groups regular and injected:
05395   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
05396   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
05397   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
05398   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
05399   *             the 2 LSB are ignored.
05400   * @note   On this STM32 serie, setting of this feature is conditioned to
05401   *         ADC state:
05402   *         ADC must be disabled or enabled without conversion on going
05403   *         on either groups regular or injected.
05404   * @rmtoll TR1      HT1            LL_ADC_ConfigAnalogWDThresholds\n
05405   *         TR2      HT2            LL_ADC_ConfigAnalogWDThresholds\n
05406   *         TR3      HT3            LL_ADC_ConfigAnalogWDThresholds\n
05407   *         TR1      LT1            LL_ADC_ConfigAnalogWDThresholds\n
05408   *         TR2      LT2            LL_ADC_ConfigAnalogWDThresholds\n
05409   *         TR3      LT3            LL_ADC_ConfigAnalogWDThresholds
05410   * @param  ADCx ADC instance
05411   * @param  AWDy This parameter can be one of the following values:
05412   *         @arg @ref LL_ADC_AWD1
05413   *         @arg @ref LL_ADC_AWD2
05414   *         @arg @ref LL_ADC_AWD3
05415   * @param  AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
05416   * @param  AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
05417   * @retval None
05418   */
05419 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
05420 {
05421   /* Set bits with content of parameter "AWDThresholdxxxValue" with bits      */
05422   /* position in register and register position depending on parameter        */
05423   /* "AWDy".                                                                  */
05424   /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
05425   /* containing other bits reserved for other purpose.                        */
05426   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
05427
05428   MODIFY_REG(*preg,
05429              ADC_TR1_HT1 | ADC_TR1_LT1,
05430              (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
05431 }
05432
05433 /**
05434   * @brief  Set ADC analog watchdog threshold value of threshold
05435   *         high or low.
05436   * @note   If values of both thresholds high or low must be set,
05437   *         use function @ref LL_ADC_ConfigAnalogWDThresholds().
05438   * @note   In case of ADC resolution different of 12 bits,
05439   *         analog watchdog thresholds data require a specific shift.
05440   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
05441   * @note   On this STM32 serie, there are 2 kinds of analog watchdog
05442   *         instance:
05443   *         - AWD standard (instance AWD1):
05444   *           - channels monitored: can monitor 1 channel or all channels.
05445   *           - groups monitored: ADC groups regular and-or injected.
05446   *           - resolution: resolution is not limited (corresponds to
05447   *             ADC resolution configured).
05448   *         - AWD flexible (instances AWD2, AWD3):
05449   *           - channels monitored: flexible on channels monitored, selection is
05450   *             channel wise, from from 1 to all channels.
05451   *             Specificity of this analog watchdog: Multiple channels can
05452   *             be selected. For example:
05453   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
05454   *           - groups monitored: not selection possible (monitoring on both
05455   *             groups regular and injected).
05456   *             Channels selected are monitored on groups regular and injected:
05457   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
05458   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
05459   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
05460   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
05461   *             the 2 LSB are ignored.
05462   * @note   On this STM32 serie, setting of this feature is conditioned to
05463   *         ADC state:
05464   *         ADC must be disabled or enabled without conversion on going
05465   *         on either groups regular or injected.
05466   * @rmtoll TR1      HT1            LL_ADC_SetAnalogWDThresholds\n
05467   *         TR2      HT2            LL_ADC_SetAnalogWDThresholds\n
05468   *         TR3      HT3            LL_ADC_SetAnalogWDThresholds\n
05469   *         TR1      LT1            LL_ADC_SetAnalogWDThresholds\n
05470   *         TR2      LT2            LL_ADC_SetAnalogWDThresholds\n
05471   *         TR3      LT3            LL_ADC_SetAnalogWDThresholds
05472   * @param  ADCx ADC instance
05473   * @param  AWDy This parameter can be one of the following values:
05474   *         @arg @ref LL_ADC_AWD1
05475   *         @arg @ref LL_ADC_AWD2
05476   *         @arg @ref LL_ADC_AWD3
05477   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
05478   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
05479   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
05480   * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
05481   * @retval None
05482   */
05483 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
05484 {
05485   /* Set bits with content of parameter "AWDThresholdValue" with bits         */
05486   /* position in register and register position depending on parameters       */
05487   /* "AWDThresholdsHighLow" and "AWDy".                                       */
05488   /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
05489   /* containing other bits reserved for other purpose.                        */
05490   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
05491
05492   MODIFY_REG(*preg,
05493              AWDThresholdsHighLow,
05494              AWDThresholdValue << POSITION_VAL(AWDThresholdsHighLow));
05495 }
05496
05497 /**
05498   * @brief  Get ADC analog watchdog threshold value of threshold high,
05499   *         threshold low or raw data with ADC thresholds high and low
05500   *         concatenated.
05501   * @note   If raw data with ADC thresholds high and low is retrieved,
05502   *         the data of each threshold high or low can be isolated
05503   *         using helper macro:
05504   *         @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
05505   * @note   In case of ADC resolution different of 12 bits,
05506   *         analog watchdog thresholds data require a specific shift.
05507   *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
05508   * @rmtoll TR1      HT1            LL_ADC_GetAnalogWDThresholds\n
05509   *         TR2      HT2            LL_ADC_GetAnalogWDThresholds\n
05510   *         TR3      HT3            LL_ADC_GetAnalogWDThresholds\n
05511   *         TR1      LT1            LL_ADC_GetAnalogWDThresholds\n
05512   *         TR2      LT2            LL_ADC_GetAnalogWDThresholds\n
05513   *         TR3      LT3            LL_ADC_GetAnalogWDThresholds
05514   * @param  ADCx ADC instance
05515   * @param  AWDy This parameter can be one of the following values:
05516   *         @arg @ref LL_ADC_AWD1
05517   *         @arg @ref LL_ADC_AWD2
05518   *         @arg @ref LL_ADC_AWD3
05519   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
05520   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
05521   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
05522   *         @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
05523   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
05524 */
05525 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
05526 {
05527   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
05528
05529   return (uint32_t)(READ_BIT(*preg,
05530                              (AWDThresholdsHighLow | ADC_TR1_LT1))
05531                     >> POSITION_VAL(AWDThresholdsHighLow)
05532                    );
05533 }
05534
05535 /**
05536   * @}
05537   */
05538
05539 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
05540   * @{
05541   */
05542
05543 #if defined(ADC_MULTIMODE_SUPPORT)
05544 /**
05545   * @brief  Set ADC multimode configuration to operate in independent mode
05546   *         or multimode (for devices with several ADC instances).
05547   * @note   If multimode configuration: the selected ADC instance is
05548   *         either master or slave depending on hardware.
05549   *         Refer to reference manual.
05550   * @note   On this STM32 serie, setting of this feature is conditioned to
05551   *         ADC state:
05552   *         All ADC instances of the ADC common group must be disabled.
05553   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
05554   *         ADC instance or by using helper macro
05555   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
05556   * @rmtoll CCR      DUAL           LL_ADC_SetMultimode
05557   * @param  ADCxy_COMMON ADC common instance
05558   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05559   * @param  Multimode This parameter can be one of the following values:
05560   *         @arg @ref LL_ADC_MULTI_INDEPENDENT
05561   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
05562   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
05563   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
05564   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
05565   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
05566   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
05567   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
05568   * @retval None
05569   */
05570 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
05571 {
05572   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
05573 }
05574
05575 /**
05576   * @brief  Get ADC multimode configuration to operate in independent mode
05577   *         or multimode (for devices with several ADC instances).
05578   * @note   If multimode configuration: the selected ADC instance is
05579   *         either master or slave depending on hardware.
05580   *         Refer to reference manual.
05581   * @rmtoll CCR      DUAL           LL_ADC_GetMultimode
05582   * @param  ADCxy_COMMON ADC common instance
05583   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05584   * @retval Returned value can be one of the following values:
05585   *         @arg @ref LL_ADC_MULTI_INDEPENDENT
05586   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
05587   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
05588   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
05589   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
05590   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
05591   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
05592   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
05593   */
05594 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
05595 {
05596   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
05597 }
05598
05599 /**
05600   * @brief  Set ADC multimode conversion data transfer: no transfer
05601   *         or transfer by DMA.
05602   * @note   If ADC multimode transfer by DMA is not selected:
05603   *         each ADC uses its own DMA channel, with its individual
05604   *         DMA transfer settings.
05605   *         If ADC multimode transfer by DMA is selected:
05606   *         One DMA channel is used for both ADC (DMA of ADC master)
05607   *         Specifies the DMA requests mode:
05608   *         - Limited mode (One shot mode): DMA transfer requests are stopped
05609   *           when number of DMA data transfers (number of
05610   *           ADC conversions) is reached.
05611   *           This ADC mode is intended to be used with DMA mode non-circular.
05612   *         - Unlimited mode: DMA transfer requests are unlimited,
05613   *           whatever number of DMA data transfers (number of
05614   *           ADC conversions).
05615   *           This ADC mode is intended to be used with DMA mode circular.
05616   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
05617   *         mode non-circular:
05618   *         when DMA transfers size will be reached, DMA will stop transfers of
05619   *         ADC conversions data ADC will raise an overrun error
05620   *         (overrun flag and interruption if enabled).
05621   * @note   How to retrieve multimode conversion data:
05622   *         Whatever multimode transfer by DMA setting: using function
05623   *         @ref LL_ADC_REG_ReadMultiConversionData32().
05624   *         If ADC multimode transfer by DMA is selected: conversion data
05625   *         is a raw data with ADC master and slave concatenated.
05626   *         A macro is available to get the conversion data of
05627   *         ADC master or ADC slave: see helper macro
05628   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
05629   * @note   On this STM32 serie, setting of this feature is conditioned to
05630   *         ADC state:
05631   *         All ADC instances of the ADC common group must be disabled
05632   *         or enabled without conversion on going on group regular.
05633   * @rmtoll CCR      MDMA           LL_ADC_SetMultiDMATransfer\n
05634   *         CCR      DMACFG         LL_ADC_SetMultiDMATransfer
05635   * @param  ADCxy_COMMON ADC common instance
05636   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05637   * @param  MultiDMATransfer This parameter can be one of the following values:
05638   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
05639   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
05640   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
05641   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
05642   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
05643   * @retval None
05644   */
05645 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
05646 {
05647   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
05648 }
05649
05650 /**
05651   * @brief  Get ADC multimode conversion data transfer: no transfer
05652   *         or transfer by DMA.
05653   * @note   If ADC multimode transfer by DMA is not selected:
05654   *         each ADC uses its own DMA channel, with its individual
05655   *         DMA transfer settings.
05656   *         If ADC multimode transfer by DMA is selected:
05657   *         One DMA channel is used for both ADC (DMA of ADC master)
05658   *         Specifies the DMA requests mode:
05659   *         - Limited mode (One shot mode): DMA transfer requests are stopped
05660   *           when number of DMA data transfers (number of
05661   *           ADC conversions) is reached.
05662   *           This ADC mode is intended to be used with DMA mode non-circular.
05663   *         - Unlimited mode: DMA transfer requests are unlimited,
05664   *           whatever number of DMA data transfers (number of
05665   *           ADC conversions).
05666   *           This ADC mode is intended to be used with DMA mode circular.
05667   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
05668   *         mode non-circular:
05669   *         when DMA transfers size will be reached, DMA will stop transfers of
05670   *         ADC conversions data ADC will raise an overrun error
05671   *         (overrun flag and interruption if enabled).
05672   * @note   How to retrieve multimode conversion data:
05673   *         Whatever multimode transfer by DMA setting: using function
05674   *         @ref LL_ADC_REG_ReadMultiConversionData32().
05675   *         If ADC multimode transfer by DMA is selected: conversion data
05676   *         is a raw data with ADC master and slave concatenated.
05677   *         A macro is available to get the conversion data of
05678   *         ADC master or ADC slave: see helper macro
05679   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
05680   * @rmtoll CCR      MDMA           LL_ADC_GetMultiDMATransfer\n
05681   *         CCR      DMACFG         LL_ADC_GetMultiDMATransfer
05682   * @param  ADCxy_COMMON ADC common instance
05683   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05684   * @retval Returned value can be one of the following values:
05685   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
05686   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
05687   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
05688   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
05689   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
05690   */
05691 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
05692 {
05693   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
05694 }
05695
05696 /**
05697   * @brief  Set ADC multimode delay between 2 sampling phases.
05698   * @note   The sampling delay range depends on ADC resolution:
05699   *         - ADC resolution 12 bits can have maximum delay of 12 cycles.
05700   *         - ADC resolution 10 bits can have maximum delay of 10 cycles.
05701   *         - ADC resolution  8 bits can have maximum delay of  8 cycles.
05702   *         - ADC resolution  6 bits can have maximum delay of  6 cycles.
05703   * @note   On this STM32 serie, setting of this feature is conditioned to
05704   *         ADC state:
05705   *         All ADC instances of the ADC common group must be disabled.
05706   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
05707   *         ADC instance or by using helper macro helper macro
05708   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
05709   * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay
05710   * @param  ADCxy_COMMON ADC common instance
05711   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05712   * @param  MultiTwoSamplingDelay This parameter can be one of the following values:
05713   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
05714   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
05715   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
05716   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
05717   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
05718   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
05719   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
05720   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
05721   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
05722   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
05723   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
05724   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
05725   *
05726   *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
05727   *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
05728   *         (3) Parameter available only if ADC resolution is 12 bits.
05729   * @retval None
05730   */
05731 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
05732 {
05733   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
05734 }
05735
05736 /**
05737   * @brief  Get ADC multimode delay between 2 sampling phases.
05738   * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay
05739   * @param  ADCxy_COMMON ADC common instance
05740   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05741   * @retval Returned value can be one of the following values:
05742   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
05743   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
05744   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
05745   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
05746   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
05747   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
05748   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
05749   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
05750   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
05751   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
05752   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
05753   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
05754   *
05755   *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
05756   *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
05757   *         (3) Parameter available only if ADC resolution is 12 bits.
05758   */
05759 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
05760 {
05761   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
05762 }
05763 #endif /* ADC_MULTIMODE_SUPPORT */
05764
05765 /**
05766   * @}
05767   */
05768 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
05769   * @{
05770   */
05771
05772 /**
05773   * @brief  Enable ADC instance internal voltage regulator.
05774   * @note   On this STM32 serie, after ADC internal voltage regulator enable,
05775   *         a delay for ADC internal voltage regulator stabilization
05776   *         is required before performing a ADC calibration or ADC enable.
05777   *         Refer to device datasheet, parameter tADCVREG_STUP.
05778   *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
05779   * @note   On this STM32 serie, setting of this feature is conditioned to
05780   *         ADC state:
05781   *         ADC must be ADC disabled.
05782   * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
05783   * @param  ADCx ADC instance
05784   * @retval None
05785   */
05786 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
05787 {
05788   /* 1. Set the intermediate state before moving the ADC voltage regulator    */
05789   /*    to state enable.                                                      */
05790   CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0));
05791   /* 2. Set the final state of ADC voltage regulator enable                   */
05792   /*    (ADVREGEN bits set to 0x01).                                          */
05793   /* Note: Write register with some additional bits forced to state reset     */
05794   /*       instead of modifying only the selected bit for this function,      */
05795   /*       to not interfere with bits with HW property "rs".                  */
05796   MODIFY_REG(ADCx->CR,
05797              ADC_CR_BITS_PROPERTY_RS,
05798              ADC_CR_ADVREGEN_0);
05799 }
05800
05801 /**
05802   * @brief  Disable ADC internal voltage regulator.
05803   * @note   On this STM32 serie, setting of this feature is conditioned to
05804   *         ADC state:
05805   *         ADC must be ADC disabled.
05806   * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator
05807   * @param  ADCx ADC instance
05808   * @retval None
05809   */
05810 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
05811 {
05812   CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
05813 }
05814
05815 /**
05816   * @brief  Get the selected ADC instance internal voltage regulator state.
05817   * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
05818   * @param  ADCx ADC instance
05819   * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
05820   */
05821 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
05822 {
05823   return (READ_BIT(ADCx->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0)) == (ADC_CR_ADVREGEN_0));
05824 }
05825
05826 /**
05827   * @brief  Enable the selected ADC instance.
05828   * @note   On this STM32 serie, after ADC enable, a delay for
05829   *         ADC internal analog stabilization is required before performing a
05830   *         ADC conversion start.
05831   *         Refer to device datasheet, parameter tSTAB.
05832   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
05833   *         is enabled and when conversion clock is active.
05834   *         (not only core clock: this ADC has a dual clock domain)
05835   * @note   On this STM32 serie, setting of this feature is conditioned to
05836   *         ADC state:
05837   *         ADC must be ADC disabled and ADC internal voltage regulator enabled.
05838   * @rmtoll CR       ADEN           LL_ADC_Enable
05839   * @param  ADCx ADC instance
05840   * @retval None
05841   */
05842 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
05843 {
05844   /* Note: Write register with some additional bits forced to state reset     */
05845   /*       instead of modifying only the selected bit for this function,      */
05846   /*       to not interfere with bits with HW property "rs".                  */
05847   MODIFY_REG(ADCx->CR,
05848              ADC_CR_BITS_PROPERTY_RS,
05849              ADC_CR_ADEN);
05850 }
05851
05852 /**
05853   * @brief  Disable the selected ADC instance.
05854   * @note   On this STM32 serie, setting of this feature is conditioned to
05855   *         ADC state:
05856   *         ADC must be not disabled. Must be enabled without conversion on going
05857   *         on either groups regular or injected.
05858   * @rmtoll CR       ADDIS          LL_ADC_Disable
05859   * @param  ADCx ADC instance
05860   * @retval None
05861   */
05862 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
05863 {
05864   /* Note: Write register with some additional bits forced to state reset     */
05865   /*       instead of modifying only the selected bit for this function,      */
05866   /*       to not interfere with bits with HW property "rs".                  */
05867   MODIFY_REG(ADCx->CR,
05868              ADC_CR_BITS_PROPERTY_RS,
05869              ADC_CR_ADDIS);
05870 }
05871
05872 /**
05873   * @brief  Get the selected ADC instance enable state.
05874   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
05875   *         is enabled and when conversion clock is active.
05876   *         (not only core clock: this ADC has a dual clock domain)
05877   * @rmtoll CR       ADEN           LL_ADC_IsEnabled
05878   * @param  ADCx ADC instance
05879   * @retval 0: ADC is disabled, 1: ADC is enabled.
05880   */
05881 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
05882 {
05883   return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
05884 }
05885
05886 /**
05887   * @brief  Get the selected ADC instance disable state.
05888   * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
05889   * @param  ADCx ADC instance
05890   * @retval 0: no ADC disable command on going.
05891   */
05892 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
05893 {
05894   return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
05895 }
05896
05897 /**
05898   * @brief  Start ADC calibration in the mode single-ended
05899   *         or differential (for devices with differential mode available).
05900   * @note   On this STM32 serie, a minimum number of ADC clock cycles
05901   *         are required between ADC end of calibration and ADC enable.
05902   *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
05903   * @note   For devices with differential mode available:
05904   *         Calibration of offset is specific to each of
05905   *         single-ended and differential modes
05906   *         (calibration run must be performed for each of these
05907   *         differential modes, if used afterwards and if the application
05908   *         requires their calibration).
05909   * @note   On this STM32 serie, setting of this feature is conditioned to
05910   *         ADC state:
05911   *         ADC must be ADC disabled.
05912   * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\n
05913   *         CR       ADCALDIF       LL_ADC_StartCalibration
05914   * @param  ADCx ADC instance
05915   * @param  SingleDiff This parameter can be one of the following values:
05916   *         @arg @ref LL_ADC_SINGLE_ENDED
05917   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
05918   * @retval None
05919   */
05920 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
05921 {
05922   /* Note: Write register with some additional bits forced to state reset     */
05923   /*       instead of modifying only the selected bit for this function,      */
05924   /*       to not interfere with bits with HW property "rs".                  */
05925   MODIFY_REG(ADCx->CR,
05926              ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
05927              ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
05928 }
05929
05930 /**
05931   * @brief  Get ADC calibration state.
05932   * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing
05933   * @param  ADCx ADC instance
05934   * @retval 0: calibration complete, 1: calibration in progress.
05935   */
05936 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
05937 {
05938   return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
05939 }
05940
05941 /**
05942   * @}
05943   */
05944
05945 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
05946   * @{
05947   */
05948
05949 /**
05950   * @brief  Start ADC group regular conversion.
05951   * @note   On this STM32 serie, this function is relevant for both
05952   *         internal trigger (SW start) and external trigger:
05953   *         - If ADC trigger has been set to software start, ADC conversion
05954   *           starts immediately.
05955   *         - If ADC trigger has been set to external trigger, ADC conversion
05956   *           will start at next trigger event (on the selected trigger edge)
05957   *           following the ADC start conversion command.
05958   * @note   On this STM32 serie, setting of this feature is conditioned to
05959   *         ADC state:
05960   *         ADC must be enabled without conversion on going on group regular,
05961   *         without conversion stop command on going on group regular,
05962   *         without ADC disable command on going.
05963   * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
05964   * @param  ADCx ADC instance
05965   * @retval None
05966   */
05967 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
05968 {
05969   /* Note: Write register with some additional bits forced to state reset     */
05970   /*       instead of modifying only the selected bit for this function,      */
05971   /*       to not interfere with bits with HW property "rs".                  */
05972   MODIFY_REG(ADCx->CR,
05973              ADC_CR_BITS_PROPERTY_RS,
05974              ADC_CR_ADSTART);
05975 }
05976
05977 /**
05978   * @brief  Stop ADC group regular conversion.
05979   * @note   On this STM32 serie, setting of this feature is conditioned to
05980   *         ADC state:
05981   *         ADC must be enabled with conversion on going on group regular,
05982   *         without ADC disable command on going.
05983   * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion
05984   * @param  ADCx ADC instance
05985   * @retval None
05986   */
05987 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
05988 {
05989   /* Note: Write register with some additional bits forced to state reset     */
05990   /*       instead of modifying only the selected bit for this function,      */
05991   /*       to not interfere with bits with HW property "rs".                  */
05992   MODIFY_REG(ADCx->CR,
05993              ADC_CR_BITS_PROPERTY_RS,
05994              ADC_CR_ADSTP);
05995 }
05996
05997 /**
05998   * @brief  Get ADC group regular conversion state.
05999   * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
06000   * @param  ADCx ADC instance
06001   * @retval 0: no conversion is on going on ADC group regular.
06002   */
06003 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
06004 {
06005   return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
06006 }
06007
06008 /**
06009   * @brief  Get ADC group regular command of conversion stop state
06010   * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing
06011   * @param  ADCx ADC instance
06012   * @retval 0: no command of conversion stop is on going on ADC group regular.
06013   */
06014 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
06015 {
06016   return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
06017 }
06018
06019 /**
06020   * @brief  Get ADC group regular conversion data, range fit for
06021   *         all ADC configurations: all ADC resolutions and
06022   *         all oversampling increased data width (for devices
06023   *         with feature oversampling).
06024   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32
06025   * @param  ADCx ADC instance
06026   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
06027   */
06028 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
06029 {
06030   return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
06031 }
06032
06033 /**
06034   * @brief  Get ADC group regular conversion data, range fit for
06035   *         ADC resolution 12 bits.
06036   * @note   For devices with feature oversampling: Oversampling
06037   *         can increase data width, function for extended range
06038   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
06039   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12
06040   * @param  ADCx ADC instance
06041   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
06042   */
06043 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
06044 {
06045   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
06046 }
06047
06048 /**
06049   * @brief  Get ADC group regular conversion data, range fit for
06050   *         ADC resolution 10 bits.
06051   * @note   For devices with feature oversampling: Oversampling
06052   *         can increase data width, function for extended range
06053   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
06054   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10
06055   * @param  ADCx ADC instance
06056   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
06057   */
06058 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
06059 {
06060   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
06061 }
06062
06063 /**
06064   * @brief  Get ADC group regular conversion data, range fit for
06065   *         ADC resolution 8 bits.
06066   * @note   For devices with feature oversampling: Oversampling
06067   *         can increase data width, function for extended range
06068   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
06069   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8
06070   * @param  ADCx ADC instance
06071   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
06072   */
06073 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
06074 {
06075   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
06076 }
06077
06078 /**
06079   * @brief  Get ADC group regular conversion data, range fit for
06080   *         ADC resolution 6 bits.
06081   * @note   For devices with feature oversampling: Oversampling
06082   *         can increase data width, function for extended range
06083   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
06084   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6
06085   * @param  ADCx ADC instance
06086   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
06087   */
06088 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
06089 {
06090   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
06091 }
06092
06093 #if defined(ADC_MULTIMODE_SUPPORT)
06094 /**
06095   * @brief  Get ADC multimode conversion data of ADC master, ADC slave
06096   *         or raw data with ADC master and slave concatenated.
06097   * @note   If raw data with ADC master and slave concatenated is retrieved,
06098   *         a macro is available to get the conversion data of
06099   *         ADC master or ADC slave: see helper macro
06100   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
06101   *         (however this macro is mainly intended for multimode
06102   *         transfer by DMA, because this function can do the same
06103   *         by getting multimode conversion data of ADC master or ADC slave
06104   *         separately).
06105   * @rmtoll CDR      RDATA_MST      LL_ADC_REG_ReadMultiConversionData32\n
06106   *         CDR      RDATA_SLV      LL_ADC_REG_ReadMultiConversionData32
06107   * @param  ADCxy_COMMON ADC common instance
06108   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06109   * @param  ConversionData This parameter can be one of the following values:
06110   *         @arg @ref LL_ADC_MULTI_MASTER
06111   *         @arg @ref LL_ADC_MULTI_SLAVE
06112   *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE
06113   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
06114   */
06115 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
06116 {
06117   return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
06118                              ConversionData)
06119                     >> POSITION_VAL(ConversionData)
06120                    );
06121 }
06122 #endif /* ADC_MULTIMODE_SUPPORT */
06123
06124 /**
06125   * @}
06126   */
06127
06128 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
06129   * @{
06130   */
06131
06132 /**
06133   * @brief  Start ADC group injected conversion.
06134   * @note   On this STM32 serie, this function is relevant for both
06135   *         internal trigger (SW start) and external trigger:
06136   *         - If ADC trigger has been set to software start, ADC conversion
06137   *           starts immediately.
06138   *         - If ADC trigger has been set to external trigger, ADC conversion
06139   *           will start at next trigger event (on the selected trigger edge)
06140   *           following the ADC start conversion command.
06141   * @note   On this STM32 serie, setting of this feature is conditioned to
06142   *         ADC state:
06143   *         ADC must be enabled without conversion on going on group injected,
06144   *         without conversion stop command on going on group injected,
06145   *         without ADC disable command on going.
06146   * @rmtoll CR       JADSTART       LL_ADC_INJ_StartConversion
06147   * @param  ADCx ADC instance
06148   * @retval None
06149   */
06150 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
06151 {
06152   /* Note: Write register with some additional bits forced to state reset     */
06153   /*       instead of modifying only the selected bit for this function,      */
06154   /*       to not interfere with bits with HW property "rs".                  */
06155   MODIFY_REG(ADCx->CR,
06156              ADC_CR_BITS_PROPERTY_RS,
06157              ADC_CR_JADSTART);
06158 }
06159
06160 /**
06161   * @brief  Stop ADC group injected conversion.
06162   * @note   On this STM32 serie, setting of this feature is conditioned to
06163   *         ADC state:
06164   *         ADC must be enabled with conversion on going on group injected,
06165   *         without ADC disable command on going.
06166   * @rmtoll CR       JADSTP         LL_ADC_INJ_StopConversion
06167   * @param  ADCx ADC instance
06168   * @retval None
06169   */
06170 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
06171 {
06172   /* Note: Write register with some additional bits forced to state reset     */
06173   /*       instead of modifying only the selected bit for this function,      */
06174   /*       to not interfere with bits with HW property "rs".                  */
06175   MODIFY_REG(ADCx->CR,
06176              ADC_CR_BITS_PROPERTY_RS,
06177              ADC_CR_JADSTP);
06178 }
06179
06180 /**
06181   * @brief  Get ADC group injected conversion state.
06182   * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing
06183   * @param  ADCx ADC instance
06184   * @retval 0: no conversion is on going on ADC group injected.
06185   */
06186 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
06187 {
06188   return (READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART));
06189 }
06190
06191 /**
06192   * @brief  Get ADC group injected command of conversion stop state
06193   * @rmtoll CR       JADSTP         LL_ADC_INJ_IsStopConversionOngoing
06194   * @param  ADCx ADC instance
06195   * @retval 0: no command of conversion stop is on going on ADC group injected.
06196   */
06197 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
06198 {
06199   return (READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP));
06200 }
06201
06202 /**
06203   * @brief  Get ADC group regular conversion data, range fit for
06204   *         all ADC configurations: all ADC resolutions and
06205   *         all oversampling increased data width (for devices
06206   *         with feature oversampling).
06207   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n
06208   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n
06209   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n
06210   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32
06211   * @param  ADCx ADC instance
06212   * @param  Rank This parameter can be one of the following values:
06213   *         @arg @ref LL_ADC_INJ_RANK_1
06214   *         @arg @ref LL_ADC_INJ_RANK_2
06215   *         @arg @ref LL_ADC_INJ_RANK_3
06216   *         @arg @ref LL_ADC_INJ_RANK_4
06217   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
06218   */
06219 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
06220 {
06221   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
06222
06223   return (uint32_t)(READ_BIT(*preg,
06224                              ADC_JDR1_JDATA)
06225                    );
06226 }
06227
06228 /**
06229   * @brief  Get ADC group injected conversion data, range fit for
06230   *         ADC resolution 12 bits.
06231   * @note   For devices with feature oversampling: Oversampling
06232   *         can increase data width, function for extended range
06233   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
06234   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n
06235   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n
06236   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n
06237   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12
06238   * @param  ADCx ADC instance
06239   * @param  Rank This parameter can be one of the following values:
06240   *         @arg @ref LL_ADC_INJ_RANK_1
06241   *         @arg @ref LL_ADC_INJ_RANK_2
06242   *         @arg @ref LL_ADC_INJ_RANK_3
06243   *         @arg @ref LL_ADC_INJ_RANK_4
06244   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
06245   */
06246 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
06247 {
06248   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
06249
06250   return (uint16_t)(READ_BIT(*preg,
06251                              ADC_JDR1_JDATA)
06252                    );
06253 }
06254
06255 /**
06256   * @brief  Get ADC group injected conversion data, range fit for
06257   *         ADC resolution 10 bits.
06258   * @note   For devices with feature oversampling: Oversampling
06259   *         can increase data width, function for extended range
06260   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
06261   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n
06262   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n
06263   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n
06264   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10
06265   * @param  ADCx ADC instance
06266   * @param  Rank This parameter can be one of the following values:
06267   *         @arg @ref LL_ADC_INJ_RANK_1
06268   *         @arg @ref LL_ADC_INJ_RANK_2
06269   *         @arg @ref LL_ADC_INJ_RANK_3
06270   *         @arg @ref LL_ADC_INJ_RANK_4
06271   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
06272   */
06273 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
06274 {
06275   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
06276
06277   return (uint16_t)(READ_BIT(*preg,
06278                              ADC_JDR1_JDATA)
06279                    );
06280 }
06281
06282 /**
06283   * @brief  Get ADC group injected conversion data, range fit for
06284   *         ADC resolution 8 bits.
06285   * @note   For devices with feature oversampling: Oversampling
06286   *         can increase data width, function for extended range
06287   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
06288   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n
06289   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n
06290   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n
06291   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8
06292   * @param  ADCx ADC instance
06293   * @param  Rank This parameter can be one of the following values:
06294   *         @arg @ref LL_ADC_INJ_RANK_1
06295   *         @arg @ref LL_ADC_INJ_RANK_2
06296   *         @arg @ref LL_ADC_INJ_RANK_3
06297   *         @arg @ref LL_ADC_INJ_RANK_4
06298   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
06299   */
06300 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
06301 {
06302   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
06303
06304   return (uint8_t)(READ_BIT(*preg,
06305                             ADC_JDR1_JDATA)
06306                   );
06307 }
06308
06309 /**
06310   * @brief  Get ADC group injected conversion data, range fit for
06311   *         ADC resolution 6 bits.
06312   * @note   For devices with feature oversampling: Oversampling
06313   *         can increase data width, function for extended range
06314   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
06315   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData6\n
06316   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData6\n
06317   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData6\n
06318   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData6
06319   * @param  ADCx ADC instance
06320   * @param  Rank This parameter can be one of the following values:
06321   *         @arg @ref LL_ADC_INJ_RANK_1
06322   *         @arg @ref LL_ADC_INJ_RANK_2
06323   *         @arg @ref LL_ADC_INJ_RANK_3
06324   *         @arg @ref LL_ADC_INJ_RANK_4
06325   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
06326   */
06327 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
06328 {
06329   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
06330
06331   return (uint8_t)(READ_BIT(*preg,
06332                             ADC_JDR1_JDATA)
06333                   );
06334 }
06335
06336 /**
06337   * @}
06338   */
06339
06340 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
06341   * @{
06342   */
06343
06344 /**
06345   * @brief  Get flag ADC ready.
06346   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
06347   *         is enabled and when conversion clock is active.
06348   *         (not only core clock: this ADC has a dual clock domain)
06349   * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY
06350   * @param  ADCx ADC instance
06351   * @retval State of bit (1 or 0).
06352   */
06353 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
06354 {
06355   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
06356 }
06357
06358 /**
06359   * @brief  Get flag ADC group regular end of unitary conversion.
06360   * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC
06361   * @param  ADCx ADC instance
06362   * @retval State of bit (1 or 0).
06363   */
06364 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
06365 {
06366   return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
06367 }
06368
06369 /**
06370   * @brief  Get flag ADC group regular end of sequence conversions.
06371   * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS
06372   * @param  ADCx ADC instance
06373   * @retval State of bit (1 or 0).
06374   */
06375 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
06376 {
06377   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
06378 }
06379
06380 /**
06381   * @brief  Get flag ADC group regular overrun.
06382   * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR
06383   * @param  ADCx ADC instance
06384   * @retval State of bit (1 or 0).
06385   */
06386 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
06387 {
06388   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
06389 }
06390
06391 /**
06392   * @brief  Get flag ADC group regular end of sampling phase.
06393   * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP
06394   * @param  ADCx ADC instance
06395   * @retval State of bit (1 or 0).
06396   */
06397 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
06398 {
06399   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP));
06400 }
06401
06402 /**
06403   * @brief  Get flag ADC group injected end of unitary conversion.
06404   * @rmtoll ISR      JEOC           LL_ADC_IsActiveFlag_JEOC
06405   * @param  ADCx ADC instance
06406   * @retval State of bit (1 or 0).
06407   */
06408 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
06409 {
06410   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC));
06411 }
06412
06413 /**
06414   * @brief  Get flag ADC group injected end of sequence conversions.
06415   * @rmtoll ISR      JEOS           LL_ADC_IsActiveFlag_JEOS
06416   * @param  ADCx ADC instance
06417   * @retval State of bit (1 or 0).
06418   */
06419 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
06420 {
06421   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
06422 }
06423
06424 /**
06425   * @brief  Get flag ADC group injected contexts queue overflow.
06426   * @rmtoll ISR      JQOVF          LL_ADC_IsActiveFlag_JQOVF
06427   * @param  ADCx ADC instance
06428   * @retval State of bit (1 or 0).
06429   */
06430 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
06431 {
06432   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF));
06433 }
06434
06435 /**
06436   * @brief  Get flag ADC analog watchdog 1 flag
06437   * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1
06438   * @param  ADCx ADC instance
06439   * @retval State of bit (1 or 0).
06440   */
06441 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
06442 {
06443   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
06444 }
06445
06446 /**
06447   * @brief  Get flag ADC analog watchdog 2.
06448   * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2
06449   * @param  ADCx ADC instance
06450   * @retval State of bit (1 or 0).
06451   */
06452 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
06453 {
06454   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2));
06455 }
06456
06457 /**
06458   * @brief  Get flag ADC analog watchdog 3.
06459   * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3
06460   * @param  ADCx ADC instance
06461   * @retval State of bit (1 or 0).
06462   */
06463 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
06464 {
06465   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3));
06466 }
06467
06468 /**
06469   * @brief  Clear flag ADC ready.
06470   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
06471   *         is enabled and when conversion clock is active.
06472   *         (not only core clock: this ADC has a dual clock domain)
06473   * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY
06474   * @param  ADCx ADC instance
06475   * @retval None
06476   */
06477 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
06478 {
06479   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
06480 }
06481
06482 /**
06483   * @brief  Clear flag ADC group regular end of unitary conversion.
06484   * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC
06485   * @param  ADCx ADC instance
06486   * @retval None
06487   */
06488 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
06489 {
06490   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
06491 }
06492
06493 /**
06494   * @brief  Clear flag ADC group regular end of sequence conversions.
06495   * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS
06496   * @param  ADCx ADC instance
06497   * @retval None
06498   */
06499 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
06500 {
06501   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
06502 }
06503
06504 /**
06505   * @brief  Clear flag ADC group regular overrun.
06506   * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR
06507   * @param  ADCx ADC instance
06508   * @retval None
06509   */
06510 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
06511 {
06512   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
06513 }
06514
06515 /**
06516   * @brief  Clear flag ADC group regular end of sampling phase.
06517   * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP
06518   * @param  ADCx ADC instance
06519   * @retval None
06520   */
06521 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
06522 {
06523   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
06524 }
06525
06526 /**
06527   * @brief  Clear flag ADC group injected end of unitary conversion.
06528   * @rmtoll ISR      JEOC           LL_ADC_ClearFlag_JEOC
06529   * @param  ADCx ADC instance
06530   * @retval None
06531   */
06532 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
06533 {
06534   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
06535 }
06536
06537 /**
06538   * @brief  Clear flag ADC group injected end of sequence conversions.
06539   * @rmtoll ISR      JEOS           LL_ADC_ClearFlag_JEOS
06540   * @param  ADCx ADC instance
06541   * @retval None
06542   */
06543 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
06544 {
06545   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
06546 }
06547
06548 /**
06549   * @brief  Clear flag ADC group injected contexts queue overflow.
06550   * @rmtoll ISR      JQOVF          LL_ADC_ClearFlag_JQOVF
06551   * @param  ADCx ADC instance
06552   * @retval None
06553   */
06554 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
06555 {
06556   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
06557 }
06558
06559 /**
06560   * @brief  Clear flag ADC analog watchdog 1.
06561   * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1
06562   * @param  ADCx ADC instance
06563   * @retval None
06564   */
06565 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
06566 {
06567   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
06568 }
06569
06570 /**
06571   * @brief  Clear flag ADC analog watchdog 2.
06572   * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2
06573   * @param  ADCx ADC instance
06574   * @retval None
06575   */
06576 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
06577 {
06578   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
06579 }
06580
06581 /**
06582   * @brief  Clear flag ADC analog watchdog 3.
06583   * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3
06584   * @param  ADCx ADC instance
06585   * @retval None
06586   */
06587 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
06588 {
06589   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
06590 }
06591
06592 #if defined(ADC_MULTIMODE_SUPPORT)
06593 /**
06594   * @brief  Get flag multimode ADC ready of the ADC master.
06595   * @rmtoll CSR      ADRDY_MST      LL_ADC_IsActiveFlag_MST_ADRDY
06596   * @param  ADCxy_COMMON ADC common instance
06597   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06598   * @retval State of bit (1 or 0).
06599   */
06600 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
06601 {
06602   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST));
06603 }
06604
06605 /**
06606   * @brief  Get flag multimode ADC ready of the ADC slave.
06607   * @rmtoll CSR      ADRDY_SLV      LL_ADC_IsActiveFlag_SLV_ADRDY
06608   * @param  ADCxy_COMMON ADC common instance
06609   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06610   * @retval State of bit (1 or 0).
06611   */
06612 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
06613 {
06614   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV));
06615 }
06616
06617 /**
06618   * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC master.
06619   * @rmtoll CSR      EOC_MST        LL_ADC_IsActiveFlag_MST_EOC
06620   * @param  ADCxy_COMMON ADC common instance
06621   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06622   * @retval State of bit (1 or 0).
06623   */
06624 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
06625 {
06626   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));
06627 }
06628
06629 /**
06630   * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
06631   * @rmtoll CSR      EOC_SLV        LL_ADC_IsActiveFlag_SLV_EOC
06632   * @param  ADCxy_COMMON ADC common instance
06633   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06634   * @retval State of bit (1 or 0).
06635   */
06636 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
06637 {
06638   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));
06639 }
06640
06641 /**
06642   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC master.
06643   * @rmtoll CSR      EOS_MST        LL_ADC_IsActiveFlag_MST_EOS
06644   * @param  ADCxy_COMMON ADC common instance
06645   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06646   * @retval State of bit (1 or 0).
06647   */
06648 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
06649 {
06650   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST));
06651 }
06652
06653 /**
06654   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
06655   * @rmtoll CSR      EOS_SLV        LL_ADC_IsActiveFlag_SLV_EOS
06656   * @param  ADCxy_COMMON ADC common instance
06657   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06658   * @retval State of bit (1 or 0).
06659   */
06660 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
06661 {
06662   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));
06663 }
06664
06665 /**
06666   * @brief  Get flag multimode ADC group regular overrun of the ADC master.
06667   * @rmtoll CSR      OVR_MST        LL_ADC_IsActiveFlag_MST_OVR
06668   * @param  ADCxy_COMMON ADC common instance
06669   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06670   * @retval State of bit (1 or 0).
06671   */
06672 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
06673 {
06674   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
06675 }
06676
06677 /**
06678   * @brief  Get flag multimode ADC group regular overrun of the ADC slave.
06679   * @rmtoll CSR      OVR_SLV        LL_ADC_IsActiveFlag_SLV_OVR
06680   * @param  ADCxy_COMMON ADC common instance
06681   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06682   * @retval State of bit (1 or 0).
06683   */
06684 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
06685 {
06686   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV));
06687 }
06688
06689 /**
06690   * @brief  Get flag multimode ADC group regular end of sampling of the ADC master.
06691   * @rmtoll CSR      EOSMP_MST      LL_ADC_IsActiveFlag_MST_EOSMP
06692   * @param  ADCxy_COMMON ADC common instance
06693   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06694   * @retval State of bit (1 or 0).
06695   */
06696 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
06697 {
06698   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST));
06699 }
06700
06701 /**
06702   * @brief  Get flag multimode ADC group regular end of sampling of the ADC slave.
06703   * @rmtoll CSR      EOSMP_SLV      LL_ADC_IsActiveFlag_SLV_EOSMP
06704   * @param  ADCxy_COMMON ADC common instance
06705   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06706   * @retval State of bit (1 or 0).
06707   */
06708 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
06709 {
06710   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV));
06711 }
06712
06713 /**
06714   * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC master.
06715   * @rmtoll CSR      JEOC_MST       LL_ADC_IsActiveFlag_MST_JEOC
06716   * @param  ADCxy_COMMON ADC common instance
06717   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06718   * @retval State of bit (1 or 0).
06719   */
06720 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
06721 {
06722   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST));
06723 }
06724
06725 /**
06726   * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
06727   * @rmtoll CSR      JEOC_SLV       LL_ADC_IsActiveFlag_SLV_JEOC
06728   * @param  ADCxy_COMMON ADC common instance
06729   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06730   * @retval State of bit (1 or 0).
06731   */
06732 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
06733 {
06734   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV));
06735 }
06736
06737 /**
06738   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.
06739   * @rmtoll CSR      JEOS_MST       LL_ADC_IsActiveFlag_MST_JEOS
06740   * @param  ADCxy_COMMON ADC common instance
06741   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06742   * @retval State of bit (1 or 0).
06743   */
06744 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
06745 {
06746   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST));
06747 }
06748
06749 /**
06750   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
06751   * @rmtoll CSR      JEOS_SLV       LL_ADC_IsActiveFlag_SLV_JEOS
06752   * @param  ADCxy_COMMON ADC common instance
06753   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06754   * @retval State of bit (1 or 0).
06755   */
06756 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
06757 {
06758   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));
06759 }
06760
06761 /**
06762   * @brief  Get flag multimode ADC group injected context queue overflow of the ADC master.
06763   * @rmtoll CSR      JQOVF_MST      LL_ADC_IsActiveFlag_MST_JQOVF
06764   * @param  ADCxy_COMMON ADC common instance
06765   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06766   * @retval State of bit (1 or 0).
06767   */
06768 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
06769 {
06770   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST));
06771 }
06772
06773 /**
06774   * @brief  Get flag multimode ADC group injected context queue overflow of the ADC slave.
06775   * @rmtoll CSR      JQOVF_SLV      LL_ADC_IsActiveFlag_SLV_JQOVF
06776   * @param  ADCxy_COMMON ADC common instance
06777   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06778   * @retval State of bit (1 or 0).
06779   */
06780 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
06781 {
06782   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV));
06783 }
06784
06785 /**
06786   * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.
06787   * @rmtoll CSR      AWD1_MST       LL_ADC_IsActiveFlag_MST_AWD1
06788   * @param  ADCxy_COMMON ADC common instance
06789   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06790   * @retval State of bit (1 or 0).
06791   */
06792 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
06793 {
06794   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
06795 }
06796
06797 /**
06798   * @brief  Get flag multimode analog watchdog 1 of the ADC slave.
06799   * @rmtoll CSR      AWD1_SLV       LL_ADC_IsActiveFlag_SLV_AWD1
06800   * @param  ADCxy_COMMON ADC common instance
06801   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06802   * @retval State of bit (1 or 0).
06803   */
06804 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
06805 {
06806   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV));
06807 }
06808
06809 /**
06810   * @brief  Get flag multimode ADC analog watchdog 2 of the ADC master.
06811   * @rmtoll CSR      AWD2_MST       LL_ADC_IsActiveFlag_MST_AWD2
06812   * @param  ADCxy_COMMON ADC common instance
06813   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06814   * @retval State of bit (1 or 0).
06815   */
06816 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
06817 {
06818   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST));
06819 }
06820
06821 /**
06822   * @brief  Get flag multimode ADC analog watchdog 2 of the ADC slave.
06823   * @rmtoll CSR      AWD2_SLV       LL_ADC_IsActiveFlag_SLV_AWD2
06824   * @param  ADCxy_COMMON ADC common instance
06825   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06826   * @retval State of bit (1 or 0).
06827   */
06828 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
06829 {
06830   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV));
06831 }
06832
06833 /**
06834   * @brief  Get flag multimode ADC analog watchdog 3 of the ADC master.
06835   * @rmtoll CSR      AWD3_MST       LL_ADC_IsActiveFlag_MST_AWD3
06836   * @param  ADCxy_COMMON ADC common instance
06837   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06838   * @retval State of bit (1 or 0).
06839   */
06840 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
06841 {
06842   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST));
06843 }
06844
06845 /**
06846   * @brief  Get flag multimode ADC analog watchdog 3 of the ADC slave.
06847   * @rmtoll CSR      AWD3_SLV       LL_ADC_IsActiveFlag_SLV_AWD3
06848   * @param  ADCxy_COMMON ADC common instance
06849   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06850   * @retval State of bit (1 or 0).
06851   */
06852 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
06853 {
06854   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV));
06855 }
06856 #endif /* ADC_MULTIMODE_SUPPORT */
06857
06858 /**
06859   * @}
06860   */
06861
06862 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
06863   * @{
06864   */
06865
06866 /**
06867   * @brief  Enable ADC ready.
06868   * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY
06869   * @param  ADCx ADC instance
06870   * @retval None
06871   */
06872 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
06873 {
06874   SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
06875 }
06876
06877 /**
06878   * @brief  Enable interruption ADC group regular end of unitary conversion.
06879   * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC
06880   * @param  ADCx ADC instance
06881   * @retval None
06882   */
06883 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
06884 {
06885   SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
06886 }
06887
06888 /**
06889   * @brief  Enable interruption ADC group regular end of sequence conversions.
06890   * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS
06891   * @param  ADCx ADC instance
06892   * @retval None
06893   */
06894 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
06895 {
06896   SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
06897 }
06898
06899 /**
06900   * @brief  Enable ADC group regular interruption overrun.
06901   * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR
06902   * @param  ADCx ADC instance
06903   * @retval None
06904   */
06905 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
06906 {
06907   SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
06908 }
06909
06910 /**
06911   * @brief  Enable interruption ADC group regular end of sampling.
06912   * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP
06913   * @param  ADCx ADC instance
06914   * @retval None
06915   */
06916 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
06917 {
06918   SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
06919 }
06920
06921 /**
06922   * @brief  Enable interruption ADC group injected end of unitary conversion.
06923   * @rmtoll IER      JEOCIE         LL_ADC_EnableIT_JEOC
06924   * @param  ADCx ADC instance
06925   * @retval None
06926   */
06927 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
06928 {
06929   SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
06930 }
06931
06932 /**
06933   * @brief  Enable interruption ADC group injected end of sequence conversions.
06934   * @rmtoll IER      JEOSIE         LL_ADC_EnableIT_JEOS
06935   * @param  ADCx ADC instance
06936   * @retval None
06937   */
06938 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
06939 {
06940   SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
06941 }
06942
06943 /**
06944   * @brief  Enable interruption ADC group injected context queue overflow.
06945   * @rmtoll IER      JQOVFIE        LL_ADC_EnableIT_JQOVF
06946   * @param  ADCx ADC instance
06947   * @retval None
06948   */
06949 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
06950 {
06951   SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
06952 }
06953
06954 /**
06955   * @brief  Enable interruption ADC analog watchdog 1.
06956   * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1
06957   * @param  ADCx ADC instance
06958   * @retval None
06959   */
06960 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
06961 {
06962   SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
06963 }
06964
06965 /**
06966   * @brief  Enable interruption ADC analog watchdog 2.
06967   * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2
06968   * @param  ADCx ADC instance
06969   * @retval None
06970   */
06971 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
06972 {
06973   SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
06974 }
06975
06976 /**
06977   * @brief  Enable interruption ADC analog watchdog 3.
06978   * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3
06979   * @param  ADCx ADC instance
06980   * @retval None
06981   */
06982 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
06983 {
06984   SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
06985 }
06986
06987 /**
06988   * @brief  Disable interruption ADC ready.
06989   * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY
06990   * @param  ADCx ADC instance
06991   * @retval None
06992   */
06993 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
06994 {
06995   CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
06996 }
06997
06998 /**
06999   * @brief  Disable interruption ADC group regular end of unitary conversion.
07000   * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC
07001   * @param  ADCx ADC instance
07002   * @retval None
07003   */
07004 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
07005 {
07006   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
07007 }
07008
07009 /**
07010   * @brief  Disable interruption ADC group regular end of sequence conversions.
07011   * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS
07012   * @param  ADCx ADC instance
07013   * @retval None
07014   */
07015 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
07016 {
07017   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
07018 }
07019
07020 /**
07021   * @brief  Disable interruption ADC group regular overrun.
07022   * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR
07023   * @param  ADCx ADC instance
07024   * @retval None
07025   */
07026 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
07027 {
07028   CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
07029 }
07030
07031 /**
07032   * @brief  Disable interruption ADC group regular end of sampling.
07033   * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP
07034   * @param  ADCx ADC instance
07035   * @retval None
07036   */
07037 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
07038 {
07039   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
07040 }
07041
07042 /**
07043   * @brief  Disable interruption ADC group regular end of unitary conversion.
07044   * @rmtoll IER      JEOCIE         LL_ADC_DisableIT_JEOC
07045   * @param  ADCx ADC instance
07046   * @retval None
07047   */
07048 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
07049 {
07050   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
07051 }
07052
07053 /**
07054   * @brief  Disable interruption ADC group injected end of sequence conversions.
07055   * @rmtoll IER      JEOSIE         LL_ADC_DisableIT_JEOS
07056   * @param  ADCx ADC instance
07057   * @retval None
07058   */
07059 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
07060 {
07061   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
07062 }
07063
07064 /**
07065   * @brief  Disable interruption ADC group injected context queue overflow.
07066   * @rmtoll IER      JQOVFIE        LL_ADC_DisableIT_JQOVF
07067   * @param  ADCx ADC instance
07068   * @retval None
07069   */
07070 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
07071 {
07072   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
07073 }
07074
07075 /**
07076   * @brief  Disable interruption ADC analog watchdog 1.
07077   * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1
07078   * @param  ADCx ADC instance
07079   * @retval None
07080   */
07081 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
07082 {
07083   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
07084 }
07085
07086 /**
07087   * @brief  Disable interruption ADC analog watchdog 2.
07088   * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2
07089   * @param  ADCx ADC instance
07090   * @retval None
07091   */
07092 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
07093 {
07094   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
07095 }
07096
07097 /**
07098   * @brief  Disable interruption ADC analog watchdog 3.
07099   * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3
07100   * @param  ADCx ADC instance
07101   * @retval None
07102   */
07103 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
07104 {
07105   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
07106 }
07107
07108 /**
07109   * @brief  Get state of interruption ADC ready
07110   *         (0: interrupt disabled, 1: interrupt enabled).
07111   * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY
07112   * @param  ADCx ADC instance
07113   * @retval State of bit (1 or 0).
07114   */
07115 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
07116 {
07117   return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY));
07118 }
07119
07120 /**
07121   * @brief  Get state of interruption ADC group regular end of unitary conversion
07122   *         (0: interrupt disabled, 1: interrupt enabled).
07123   * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC
07124   * @param  ADCx ADC instance
07125   * @retval State of bit (1 or 0).
07126   */
07127 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
07128 {
07129   return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC));
07130 }
07131
07132 /**
07133   * @brief  Get state of interruption ADC group regular end of sequence conversions
07134   *         (0: interrupt disabled, 1: interrupt enabled).
07135   * @rmtoll IER      EOSIE          LL_ADC_IsEnabledIT_EOS
07136   * @param  ADCx ADC instance
07137   * @retval State of bit (1 or 0).
07138   */
07139 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
07140 {
07141   return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
07142 }
07143
07144 /**
07145   * @brief  Get state of interruption ADC group regular overrun
07146   *         (0: interrupt disabled, 1: interrupt enabled).
07147   * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR
07148   * @param  ADCx ADC instance
07149   * @retval State of bit (1 or 0).
07150   */
07151 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
07152 {
07153   return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
07154 }
07155
07156 /**
07157   * @brief  Get state of interruption ADC group regular end of sampling
07158   *         (0: interrupt disabled, 1: interrupt enabled).
07159   * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP
07160   * @param  ADCx ADC instance
07161   * @retval State of bit (1 or 0).
07162   */
07163 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
07164 {
07165   return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP));
07166 }
07167
07168 /**
07169   * @brief  Get state of interruption ADC group injected end of unitary conversion
07170   *         (0: interrupt disabled, 1: interrupt enabled).
07171   * @rmtoll IER      JEOCIE         LL_ADC_IsEnabledIT_JEOC
07172   * @param  ADCx ADC instance
07173   * @retval State of bit (1 or 0).
07174   */
07175 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
07176 {
07177   return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC));
07178 }
07179
07180 /**
07181   * @brief  Get state of interruption ADC group injected end of sequence conversions
07182   *         (0: interrupt disabled, 1: interrupt enabled).
07183   * @rmtoll IER      JEOSIE         LL_ADC_IsEnabledIT_JEOS
07184   * @param  ADCx ADC instance
07185   * @retval State of bit (1 or 0).
07186   */
07187 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
07188 {
07189   return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
07190 }
07191
07192 /**
07193   * @brief  Get state of interruption ADC group injected context queue overflow interrupt state
07194   *         (0: interrupt disabled, 1: interrupt enabled).
07195   * @rmtoll IER      JQOVFIE        LL_ADC_IsEnabledIT_JQOVF
07196   * @param  ADCx ADC instance
07197   * @retval State of bit (1 or 0).
07198   */
07199 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
07200 {
07201   return (READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF));
07202 }
07203
07204 /**
07205   * @brief  Get state of interruption ADC analog watchdog 1
07206   *         (0: interrupt disabled, 1: interrupt enabled).
07207   * @rmtoll IER      AWD1IE         LL_ADC_IsEnabledIT_AWD1
07208   * @param  ADCx ADC instance
07209   * @retval State of bit (1 or 0).
07210   */
07211 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
07212 {
07213   return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
07214 }
07215
07216 /**
07217   * @brief  Get state of interruption Get ADC analog watchdog 2
07218   *         (0: interrupt disabled, 1: interrupt enabled).
07219   * @rmtoll IER      AWD2IE         LL_ADC_IsEnabledIT_AWD2
07220   * @param  ADCx ADC instance
07221   * @retval State of bit (1 or 0).
07222   */
07223 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
07224 {
07225   return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2));
07226 }
07227
07228 /**
07229   * @brief  Get state of interruption Get ADC analog watchdog 3
07230   *         (0: interrupt disabled, 1: interrupt enabled).
07231   * @rmtoll IER      AWD3IE         LL_ADC_IsEnabledIT_AWD3
07232   * @param  ADCx ADC instance
07233   * @retval State of bit (1 or 0).
07234   */
07235 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
07236 {
07237   return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3));
07238 }
07239
07240 /**
07241   * @}
07242   */
07243
07244 #if defined(USE_FULL_LL_DRIVER)
07245 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
07246   * @{
07247   */
07248
07249 /* Initialization of some features of ADC common parameters and multimode */
07250 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
07251 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
07252 void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
07253
07254 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
07255 /* (availability of ADC group injected depends on STM32 families) */
07256 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
07257
07258 /* Initialization of some features of ADC instance */
07259 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
07260 void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
07261
07262 /* Initialization of some features of ADC instance and ADC group regular */
07263 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
07264 void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
07265
07266 /* Initialization of some features of ADC instance and ADC group injected */
07267 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
07268 void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
07269
07270 /**
07271   * @}
07272   */
07273 #endif /* USE_FULL_LL_DRIVER */
07274
07275 /**
07276   * @}
07277   */
07278
07279 /**
07280   * @}
07281   */
07282
07283 #endif /* ADC1 || ADC2 || ADC3 || ADC4 */
07284
07285
07286 #endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
07287
07288 #if defined (ADC1_V2_5)
07289
07290 #if defined (ADC1)
07291
07292 /** @defgroup ADC_LL ADC
07293   * @{
07294   */
07295
07296 /* Private types -------------------------------------------------------------*/
07297 /* Private variables ---------------------------------------------------------*/
07298
07299 /* Private constants ---------------------------------------------------------*/
07300 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
07301   * @{
07302   */
07303
07304 /* Internal mask for ADC group regular sequencer:                             */
07305 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
07306 /* - sequencer register offset                                                */
07307 /* - sequencer rank bits position into the selected register                  */
07308
07309 /* Internal register offset for ADC group regular sequencer configuration */
07310 /* (offset placed into a spare area of literal definition) */
07311 #define ADC_SQR1_REGOFFSET                 ((uint32_t)0x00000000U)
07312 #define ADC_SQR2_REGOFFSET                 ((uint32_t)0x00000100U)
07313 #define ADC_SQR3_REGOFFSET                 ((uint32_t)0x00000200U)
07314 #define ADC_SQR4_REGOFFSET                 ((uint32_t)0x00000300U)
07315
07316 #define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
07317 #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
07318
07319 /* Definition of ADC group regular sequencer bits information to be inserted  */
07320 /* into ADC group regular sequencer ranks literals definition.                */
07321 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
07322 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
07323 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
07324 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
07325 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
07326 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
07327 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
07328 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
07329 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
07330 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
07331 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
07332 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
07333 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
07334 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
07335 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
07336 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
07337
07338
07339
07340 /* Internal mask for ADC group injected sequencer:                            */
07341 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */
07342 /* - data register offset                                                     */
07343 /* - offset register offset                                                   */
07344 /* - sequencer rank bits position into the selected register                  */
07345
07346 /* Internal register offset for ADC group injected data register */
07347 /* (offset placed into a spare area of literal definition) */
07348 #define ADC_JDR1_REGOFFSET                 ((uint32_t)0x00000000U)
07349 #define ADC_JDR2_REGOFFSET                 ((uint32_t)0x00000100U)
07350 #define ADC_JDR3_REGOFFSET                 ((uint32_t)0x00000200U)
07351 #define ADC_JDR4_REGOFFSET                 ((uint32_t)0x00000300U)
07352
07353 /* Internal register offset for ADC group injected offset configuration */
07354 /* (offset placed into a spare area of literal definition) */
07355 #define ADC_JOFR1_REGOFFSET                ((uint32_t)0x00000000U)
07356 #define ADC_JOFR2_REGOFFSET                ((uint32_t)0x00001000U)
07357 #define ADC_JOFR3_REGOFFSET                ((uint32_t)0x00002000U)
07358 #define ADC_JOFR4_REGOFFSET                ((uint32_t)0x00003000U)
07359
07360 #define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
07361 #define ADC_INJ_JOFRX_REGOFFSET_MASK       (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
07362 #define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
07363
07364 /* Definition of ADC group injected sequencer bits information to be inserted */
07365 /* into ADC group injected sequencer ranks literals definition.               */
07366 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
07367 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
07368 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
07369 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
07370
07371
07372
07373 /* Internal mask for ADC channel:                                             */
07374 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
07375 /* - channel identifier defined by number                                     */
07376 /* - channel differentiation between external channels (connected to          */
07377 /*   GPIO pins) and internal channels (connected to internal paths)           */
07378 /* - channel sampling time defined by SMPRx register offset                   */
07379 /*   and SMPx bits positions into SMPRx register                              */
07380 #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CR1_AWDCH)
07381 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t) 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
07382 #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
07383 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
07384 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
07385
07386 /* Channel differentiation between external and internal channels */
07387 #define ADC_CHANNEL_ID_INTERNAL_CH         ((uint32_t)0x80000000U) /* Marker of internal channel */
07388 #define ADC_CHANNEL_ID_INTERNAL_CH_2       ((uint32_t)0x40000000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
07389 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
07390
07391 /* Internal register offset for ADC channel sampling time configuration */
07392 /* (offset placed into a spare area of literal definition) */
07393 #define ADC_SMPR1_REGOFFSET                ((uint32_t)0x00000000U)
07394 #define ADC_SMPR2_REGOFFSET                ((uint32_t)0x02000000U)
07395 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
07396
07397 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK    ((uint32_t)0x01F00000U)
07398 #define ADC_CHANNEL_SMPx_BITOFFSET_POS     ((uint32_t)20U)           /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
07399
07400 /* Definition of channels ID number information to be inserted into           */
07401 /* channels literals definition.                                              */
07402 #define ADC_CHANNEL_0_NUMBER               ((uint32_t)0x00000000U)
07403 #define ADC_CHANNEL_1_NUMBER               (                                                                        ADC_CR1_AWDCH_0)
07404 #define ADC_CHANNEL_2_NUMBER               (                                                      ADC_CR1_AWDCH_1                  )
07405 #define ADC_CHANNEL_3_NUMBER               (                                                      ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
07406 #define ADC_CHANNEL_4_NUMBER               (                                    ADC_CR1_AWDCH_2                                    )
07407 #define ADC_CHANNEL_5_NUMBER               (                                    ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)
07408 #define ADC_CHANNEL_6_NUMBER               (                                    ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )
07409 #define ADC_CHANNEL_7_NUMBER               (                                    ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
07410 #define ADC_CHANNEL_8_NUMBER               (                  ADC_CR1_AWDCH_3                                                      )
07411 #define ADC_CHANNEL_9_NUMBER               (                  ADC_CR1_AWDCH_3                                     | ADC_CR1_AWDCH_0)
07412 #define ADC_CHANNEL_10_NUMBER              (                  ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1                  )
07413 #define ADC_CHANNEL_11_NUMBER              (                  ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
07414 #define ADC_CHANNEL_12_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                                    )
07415 #define ADC_CHANNEL_13_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)
07416 #define ADC_CHANNEL_14_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )
07417 #define ADC_CHANNEL_15_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
07418 #define ADC_CHANNEL_16_NUMBER              (ADC_CR1_AWDCH_4                                                                        )
07419 #define ADC_CHANNEL_17_NUMBER              (ADC_CR1_AWDCH_4                                                       | ADC_CR1_AWDCH_0)
07420
07421 /* Definition of channels sampling time information to be inserted into       */
07422 /* channels literals definition.                                              */
07423 #define ADC_CHANNEL_0_SMP                  (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
07424 #define ADC_CHANNEL_1_SMP                  (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
07425 #define ADC_CHANNEL_2_SMP                  (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
07426 #define ADC_CHANNEL_3_SMP                  (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
07427 #define ADC_CHANNEL_4_SMP                  (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
07428 #define ADC_CHANNEL_5_SMP                  (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
07429 #define ADC_CHANNEL_6_SMP                  (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
07430 #define ADC_CHANNEL_7_SMP                  (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
07431 #define ADC_CHANNEL_8_SMP                  (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
07432 #define ADC_CHANNEL_9_SMP                  (ADC_SMPR2_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
07433 #define ADC_CHANNEL_10_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
07434 #define ADC_CHANNEL_11_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
07435 #define ADC_CHANNEL_12_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
07436 #define ADC_CHANNEL_13_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
07437 #define ADC_CHANNEL_14_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
07438 #define ADC_CHANNEL_15_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
07439 #define ADC_CHANNEL_16_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
07440 #define ADC_CHANNEL_17_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
07441
07442
07443 /* Internal mask for ADC analog watchdog:                                     */
07444 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
07445 /* (concatenation of multiple bits used in different analog watchdogs,        */
07446 /* (feature of several watchdogs not available on all STM32 families)).       */
07447 /* - analog watchdog 1: monitored channel defined by number,                  */
07448 /*   selection of ADC group (ADC groups regular and-or injected).             */
07449
07450 /* Internal register offset for ADC analog watchdog channel configuration */
07451 #define ADC_AWD_CR1_REGOFFSET              ((uint32_t)0x00000000U)
07452
07453 #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET)
07454
07455 #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
07456 #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK)
07457
07458 /* Internal register offset for ADC analog watchdog threshold configuration */
07459 #define ADC_AWD_TR1_HIGH_REGOFFSET         ((uint32_t)0x00000000U)
07460 #define ADC_AWD_TR1_LOW_REGOFFSET          ((uint32_t)0x00000001U)
07461 #define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
07462
07463
07464 /* ADC registers bits positions */
07465 #define ADC_CR1_DUALMOD_BITOFFSET_POS      ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */
07466
07467
07468 /* ADC internal channels related definitions */
07469 /* Internal voltage reference VrefInt */
07470 #define VREFINT_CAL_ADDR                   ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
07471 #define VREFINT_CAL_VREF                   ((uint32_t) 3300U)                    /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
07472 /* Temperature sensor */
07473 #define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F37x, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
07474 #define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F37x, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
07475 #define TEMPSENSOR_CAL1_TEMP               (( int32_t)   30)                     /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
07476 #define TEMPSENSOR_CAL2_TEMP               (( int32_t)  110)                     /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
07477 #define TEMPSENSOR_CAL_VREFANALOG          ((uint32_t) 3300U)                    /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
07478
07479
07480 /**
07481   * @}
07482   */
07483
07484
07485 /* Private macros ------------------------------------------------------------*/
07486 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
07487   * @{
07488   */
07489
07490 /**
07491   * @brief  Driver macro reserved for internal use: isolate bits with the
07492   *         selected mask and shift them to the register LSB
07493   *         (shift mask on register position bit 0).
07494   * @param  __BITS__ Bits in register 32 bits
07495   * @param  __MASK__ Mask in register 32 bits
07496   * @retval Bits in register 32 bits
07497   */
07498 #define __ADC_MASK_SHIFT(__BITS__, __MASK__)                                   \
07499   (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
07500
07501 /**
07502   * @brief  Driver macro reserved for internal use: set a pointer to
07503   *         a register from a register basis from which an offset
07504   *         is applied.
07505   * @param  __REG__ Register basis from which the offset is applied.
07506   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
07507   * @retval Pointer to register address
07508   */
07509 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
07510  ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
07511
07512 /**
07513   * @}
07514   */
07515
07516
07517 /* Exported types ------------------------------------------------------------*/
07518 #if defined(USE_FULL_LL_DRIVER)
07519 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
07520   * @{
07521   */
07522
07523 /**
07524   * @brief  Structure definition of some features of ADC instance.
07525   * @note   These parameters have an impact on ADC scope: ADC instance.
07526   *         Affects both group regular and group injected (availability
07527   *         of ADC group injected depends on STM32 families).
07528   *         Refer to corresponding unitary functions into
07529   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
07530   * @note   The setting of these parameters by function @ref LL_ADC_Init()
07531   *         is conditioned to ADC state:
07532   *         ADC instance must be disabled.
07533   *         This condition is applied to all ADC features, for efficiency
07534   *         and compatibility over all STM32 families. However, the different
07535   *         features can be set under different ADC state conditions
07536   *         (setting possible with ADC enabled without conversion on going,
07537   *         ADC enabled with conversion on going, ...)
07538   *         Each feature can be updated afterwards with a unitary function
07539   *         and potentially with ADC in a different state than disabled,
07540   *         refer to description of each function for setting
07541   *         conditioned to ADC state.
07542   */
07543 typedef struct
07544 {
07545   uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.
07546                                              This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
07547
07548                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
07549
07550   uint32_t SequencersScanMode;          /*!< Set ADC scan selection.
07551                                              This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
07552
07553                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
07554
07555 } LL_ADC_InitTypeDef;
07556
07557 /**
07558   * @brief  Structure definition of some features of ADC group regular.
07559   * @note   These parameters have an impact on ADC scope: ADC group regular.
07560   *         Refer to corresponding unitary functions into
07561   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
07562   *         (functions with prefix "REG").
07563   * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
07564   *         is conditioned to ADC state:
07565   *         ADC instance must be disabled.
07566   *         This condition is applied to all ADC features, for efficiency
07567   *         and compatibility over all STM32 families. However, the different
07568   *         features can be set under different ADC state conditions
07569   *         (setting possible with ADC enabled without conversion on going,
07570   *         ADC enabled with conversion on going, ...)
07571   *         Each feature can be updated afterwards with a unitary function
07572   *         and potentially with ADC in a different state than disabled,
07573   *         refer to description of each function for setting
07574   *         conditioned to ADC state.
07575   */
07576 typedef struct
07577 {
07578   uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or external from timer or external interrupt.
07579                                              This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
07580                                              @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
07581                                                    (only trigger polarity available on this STM32 serie).
07582
07583                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
07584
07585   uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.
07586                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
07587                                              @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
07588
07589                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
07590
07591   uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
07592                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
07593                                              @note This parameter has an effect only if group regular sequencer is enabled
07594                                                    (scan length of 2 ranks or more).
07595
07596                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
07597
07598   uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
07599                                              This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
07600                                              Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
07601
07602                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
07603
07604   uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
07605                                              This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
07606
07607                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
07608
07609 } LL_ADC_REG_InitTypeDef;
07610
07611 /**
07612   * @brief  Structure definition of some features of ADC group injected.
07613   * @note   These parameters have an impact on ADC scope: ADC group injected.
07614   *         Refer to corresponding unitary functions into
07615   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
07616   *         (functions with prefix "INJ").
07617   * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()
07618   *         is conditioned to ADC state:
07619   *         ADC instance must be disabled.
07620   *         This condition is applied to all ADC features, for efficiency
07621   *         and compatibility over all STM32 families. However, the different
07622   *         features can be set under different ADC state conditions
07623   *         (setting possible with ADC enabled without conversion on going,
07624   *         ADC enabled with conversion on going, ...)
07625   *         Each feature can be updated afterwards with a unitary function
07626   *         and potentially with ADC in a different state than disabled,
07627   *         refer to description of each function for setting
07628   *         conditioned to ADC state.
07629   */
07630 typedef struct
07631 {
07632   uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or external from timer or external interrupt.
07633                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
07634                                              @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
07635                                                    (only trigger polarity available on this STM32 serie).
07636
07637                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
07638
07639   uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.
07640                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
07641                                              @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
07642
07643                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
07644
07645   uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
07646                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
07647                                              @note This parameter has an effect only if group injected sequencer is enabled
07648                                                    (scan length of 2 ranks or more).
07649
07650                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
07651
07652   uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
07653                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
07654                                              Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
07655
07656                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
07657
07658 } LL_ADC_INJ_InitTypeDef;
07659
07660 /**
07661   * @}
07662   */
07663 #endif /* USE_FULL_LL_DRIVER */
07664
07665 /* Exported constants --------------------------------------------------------*/
07666 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
07667   * @{
07668   */
07669
07670 /** @defgroup ADC_LL_EC_FLAG ADC flags
07671   * @brief    Flags defines which can be used with LL_ADC_ReadReg function
07672   * @{
07673   */
07674 #define LL_ADC_FLAG_STRT                   ADC_SR_STRT        /*!< ADC flag ADC group regular conversion start */
07675 #define LL_ADC_FLAG_EOS                    ADC_SR_EOC         /*!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
07676 #define LL_ADC_FLAG_JSTRT                  ADC_SR_JSTRT       /*!< ADC flag ADC group injected conversion start */
07677 #define LL_ADC_FLAG_JEOS                   ADC_SR_JEOC        /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
07678 #define LL_ADC_FLAG_AWD1                   ADC_SR_AWD         /*!< ADC flag ADC analog watchdog 1 */
07679 /**
07680   * @}
07681   */
07682
07683 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
07684   * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
07685   * @{
07686   */
07687 #define LL_ADC_IT_EOS                      ADC_CR1_EOCIE      /*!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
07688 #define LL_ADC_IT_JEOS                     ADC_CR1_JEOCIE     /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
07689 #define LL_ADC_IT_AWD1                     ADC_CR1_AWDIE      /*!< ADC interruption ADC analog watchdog 1 */
07690 /**
07691   * @}
07692   */
07693
07694 /** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
07695   * @{
07696   */
07697 /* List of ADC registers intended to be used (most commonly) with             */
07698 /* DMA transfer.                                                              */
07699 /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
07700 #define LL_ADC_DMA_REG_REGULAR_DATA          ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
07701 /**
07702   * @}
07703   */
07704
07705 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
07706   * @{
07707   */
07708 /* Note: Other measurement paths to internal channels may be available        */
07709 /*       (connections to other peripherals).                                  */
07710 /*       If they are not listed below, they do not require any specific       */
07711 /*       path enable. In this case, Access to measurement path is done        */
07712 /*       only by selecting the corresponding ADC internal channel.            */
07713 #define LL_ADC_PATH_INTERNAL_NONE          ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */
07714 #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CR2_TSVREFE)      /*!< ADC measurement path to internal channel VrefInt */
07715 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CR2_TSVREFE)      /*!< ADC measurement path to internal channel temperature sensor */
07716 /**
07717   * @}
07718   */
07719
07720 /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
07721   * @{
07722   */
07723 #define LL_ADC_RESOLUTION_12B              ((uint32_t)0x00000000U)             /*!< ADC resolution 12 bits */
07724 /**
07725   * @}
07726   */
07727
07728 /** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
07729   * @{
07730   */
07731 #define LL_ADC_DATA_ALIGN_RIGHT            ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
07732 #define LL_ADC_DATA_ALIGN_LEFT             (ADC_CR2_ALIGN)        /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
07733 /**
07734   * @}
07735   */
07736
07737 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
07738   * @{
07739   */
07740 #define LL_ADC_SEQ_SCAN_DISABLE            ((uint32_t)0x00000000U)  /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
07741 #define LL_ADC_SEQ_SCAN_ENABLE             ((uint32_t)ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
07742 /**
07743   * @}
07744   */
07745
07746 /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
07747   * @{
07748   */
07749 #define LL_ADC_GROUP_REGULAR               ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
07750 #define LL_ADC_GROUP_INJECTED              ((uint32_t)0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/
07751 #define LL_ADC_GROUP_REGULAR_INJECTED      ((uint32_t)0x00000003U) /*!< ADC both groups regular and injected */
07752 /**
07753   * @}
07754   */
07755
07756 /** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
07757   * @{
07758   */
07759 #define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
07760 #define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
07761 #define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
07762 #define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
07763 #define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
07764 #define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
07765 #define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
07766 #define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
07767 #define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
07768 #define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
07769 #define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
07770 #define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
07771 #define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
07772 #define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
07773 #define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
07774 #define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
07775 #define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
07776 #define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
07777 #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F37x, ADC channel available only on ADC instance: ADC1. */
07778 #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
07779 /**
07780   * @}
07781   */
07782
07783 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
07784   * @{
07785   */
07786 #define LL_ADC_REG_TRIG_SOFTWARE           (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger internal (SW start) */
07787 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)                    /*!< ADC group regular conversion trigger external from TIM2 CC2. Trigger edge set to rising edge (default setting). */
07788 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CR2_EXTSEL_2)                                       /*!< ADC group regular conversion trigger external from TIM3 TRGO. Trigger edge set to rising edge (default setting). */
07789 #define LL_ADC_REG_TRIG_EXT_TIM4_CH2       (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)                    /*!< ADC group regular conversion trigger external from TIM4 CC4. Trigger edge set to rising edge (default setting). */
07790 #define LL_ADC_REG_TRIG_EXT_TIM19_TRGO     ((uint32_t)0x00000000U)                                  /*!< ADC group regular conversion trigger external from TIM19 TRGO. Trigger edge set to rising edge (default setting). */
07791 #define LL_ADC_REG_TRIG_EXT_TIM19_CH3      (ADC_CR2_EXTSEL_0)                                       /*!< ADC group regular conversion trigger external from TIM19 CC3. Trigger edge set to rising edge (default setting). */
07792 #define LL_ADC_REG_TRIG_EXT_TIM19_CH4      (ADC_CR2_EXTSEL_1)                                       /*!< ADC group regular conversion trigger external from TIM19 CC4. Trigger edge set to rising edge (default setting). */
07793 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)                    /*!< ADC group regular conversion trigger external interrupt line 11. Trigger edge set to rising edge (default setting). */
07794 /**
07795   * @}
07796   */
07797
07798 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
07799   * @{
07800   */
07801 #define LL_ADC_REG_TRIG_EXT_RISING         ((uint32_t)0x00000000U)                 /*!< ADC group regular conversion trigger polarity set to rising edge */
07802 /**
07803   * @}
07804   */
07805
07806 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
07807 * @{
07808 */
07809 #define LL_ADC_REG_CONV_SINGLE             ((uint32_t)0x00000000U)/*!< ADC conversions are performed in single mode: one conversion per trigger */
07810 #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CR2_CONT)         /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
07811 /**
07812   * @}
07813   */
07814
07815 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer
07816   * @{
07817   */
07818 #define LL_ADC_REG_DMA_TRANSFER_NONE       ((uint32_t)0x00000000U)              /*!< ADC conversions are not transferred by DMA */
07819 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CR2_DMA)                        /*!< ADC conversions are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
07820 /**
07821   * @}
07822   */
07823
07824 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
07825   * @{
07826   */
07827 #define LL_ADC_REG_SEQ_SCAN_DISABLE        ((uint32_t)0x00000000U)                                     /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
07828 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
07829 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
07830 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
07831 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
07832 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
07833 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
07834 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
07835 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
07836 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
07837 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
07838 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
07839 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
07840 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
07841 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
07842 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
07843 /**
07844   * @}
07845   */
07846
07847 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
07848   * @{
07849   */
07850 #define LL_ADC_REG_SEQ_DISCONT_DISABLE     ((uint32_t)0x00000000U)                                                          /*!< ADC group regular sequencer discontinuous mode disable */
07851 #define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                            ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
07852 #define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                        ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
07853 #define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                    ADC_CR1_DISCNUM_1                     | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
07854 #define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                    ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
07855 #define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CR1_DISCNUM_2                                         | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
07856 #define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CR1_DISCNUM_2                     | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
07857 #define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1                     | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
07858 #define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
07859 /**
07860   * @}
07861   */
07862
07863 /** @defgroup ADC_LL_EC_REG_RANKS  ADC group regular - Sequencer ranks
07864   * @{
07865   */
07866 #define LL_ADC_REG_RANK_1                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */
07867 #define LL_ADC_REG_RANK_2                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */
07868 #define LL_ADC_REG_RANK_3                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */
07869 #define LL_ADC_REG_RANK_4                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */
07870 #define LL_ADC_REG_RANK_5                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */
07871 #define LL_ADC_REG_RANK_6                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */
07872 #define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */
07873 #define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */
07874 #define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */
07875 #define LL_ADC_REG_RANK_10                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
07876 #define LL_ADC_REG_RANK_11                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
07877 #define LL_ADC_REG_RANK_12                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
07878 #define LL_ADC_REG_RANK_13                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
07879 #define LL_ADC_REG_RANK_14                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
07880 #define LL_ADC_REG_RANK_15                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
07881 #define LL_ADC_REG_RANK_16                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
07882 /**
07883   * @}
07884   */
07885
07886 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source
07887   * @{
07888   */
07889 #define LL_ADC_INJ_TRIG_SOFTWARE           (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger internal (SW start) */
07890 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_CR2_JEXTSEL_1)                                         /*!< ADC group injected conversion trigger external from TIM2 TRGO. Trigger edge set to rising edge (default setting). */
07891 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)                     /*!< ADC group injected conversion trigger external from TIM2 CC1. Trigger edge set to rising edge (default setting). */
07892 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_CR2_JEXTSEL_2)                                         /*!< ADC group injected conversion trigger external from TIM3 CC4. Trigger edge set to rising edge (default setting). */
07893 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)                     /*!< ADC group injected conversion trigger external from TIM4 TRGO. Trigger edge set to rising edge (default setting). */
07894 #define LL_ADC_INJ_TRIG_EXT_TIM19_CH1      ((uint32_t)0x00000000U)                                     /*!< ADC group injected conversion trigger external from TIM19 CC1. Trigger edge set to rising edge (default setting). */
07895 #define LL_ADC_INJ_TRIG_EXT_TIM19_CH2      (ADC_CR2_JEXTSEL_0)                                         /*!< ADC group injected conversion trigger external from TIM19 CC2. Trigger edge set to rising edge (default setting). */
07896 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)                     /*!< ADC group injected conversion trigger external interrupt line 15. Trigger edge set to rising edge (default setting). */
07897 /**
07898   * @}
07899   */
07900
07901 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge
07902   * @{
07903   */
07904 #define LL_ADC_INJ_TRIG_EXT_RISING         ((uint32_t)0x00000000U)                 /*!< ADC group injected conversion trigger polarity set to rising edge */
07905 /**
07906   * @}
07907   */
07908
07909 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode
07910 * @{
07911 */
07912 #define LL_ADC_INJ_TRIG_INDEPENDENT        ((uint32_t)0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
07913 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CR1_JAUTO)        /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
07914 /**
07915   * @}
07916   */
07917
07918
07919 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length
07920   * @{
07921   */
07922 #define LL_ADC_INJ_SEQ_SCAN_DISABLE        ((uint32_t)0x00000000U)         /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
07923 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
07924 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
07925 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
07926 /**
07927   * @}
07928   */
07929
07930 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode
07931   * @{
07932   */
07933 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE     ((uint32_t)0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */
07934 #define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CR1_JDISCEN)      /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
07935 /**
07936   * @}
07937   */
07938
07939 /** @defgroup ADC_LL_EC_INJ_RANKS  ADC group injected - Sequencer ranks
07940   * @{
07941   */
07942 #define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
07943 #define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
07944 #define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
07945 #define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
07946 /**
07947   * @}
07948   */
07949
07950 /** @defgroup ADC_LL_EC_SAMPLINGTIME  Channel - Sampling time
07951   * @{
07952   */
07953 #define LL_ADC_SAMPLINGTIME_1CYCLE_5       ((uint32_t)0x00000000U)                                  /*!< Sampling time 1.5 ADC clock cycle */
07954 #define LL_ADC_SAMPLINGTIME_7CYCLES_5      (ADC_SMPR2_SMP0_0)                                       /*!< Sampling time 7.5 ADC clock cycles */
07955 #define LL_ADC_SAMPLINGTIME_13CYCLES_5     (ADC_SMPR2_SMP0_1)                                       /*!< Sampling time 13.5 ADC clock cycles */
07956 #define LL_ADC_SAMPLINGTIME_28CYCLES_5     (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)                    /*!< Sampling time 28.5 ADC clock cycles */
07957 #define LL_ADC_SAMPLINGTIME_41CYCLES_5     (ADC_SMPR2_SMP0_2)                                       /*!< Sampling time 41.5 ADC clock cycles */
07958 #define LL_ADC_SAMPLINGTIME_55CYCLES_5     (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)                    /*!< Sampling time 55.5 ADC clock cycles */
07959 #define LL_ADC_SAMPLINGTIME_71CYCLES_5     (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)                    /*!< Sampling time 71.5 ADC clock cycles */
07960 #define LL_ADC_SAMPLINGTIME_239CYCLES_5    (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 239.5 ADC clock cycles */
07961 /**
07962   * @}
07963   */
07964
07965 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
07966   * @{
07967   */
07968 #define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
07969 /**
07970   * @}
07971   */
07972
07973 /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
07974   * @{
07975   */
07976 #define LL_ADC_AWD_DISABLE                 ((uint32_t)0x00000000U)                                                                       /*!< ADC analog watchdog monitoring disabled */
07977 #define LL_ADC_AWD_ALL_CHANNELS_REG        (                                                             ADC_CR1_AWDEN                 ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
07978 #define LL_ADC_AWD_ALL_CHANNELS_INJ        (                                            ADC_CR1_JAWDEN                                 ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
07979 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (                                            ADC_CR1_JAWDEN | ADC_CR1_AWDEN                 ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
07980 #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
07981 #define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
07982 #define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
07983 #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
07984 #define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
07985 #define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
07986 #define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
07987 #define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
07988 #define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
07989 #define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
07990 #define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
07991 #define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
07992 #define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
07993 #define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
07994 #define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
07995 #define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
07996 #define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
07997 #define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
07998 #define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
07999 #define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
08000 #define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
08001 #define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
08002 #define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
08003 #define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
08004 #define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
08005 #define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
08006 #define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
08007 #define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
08008 #define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
08009 #define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
08010 #define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
08011 #define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
08012 #define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
08013 #define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
08014 #define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
08015 #define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
08016 #define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
08017 #define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
08018 #define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
08019 #define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
08020 #define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
08021 #define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
08022 #define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
08023 #define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
08024 #define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
08025 #define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
08026 #define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
08027 #define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
08028 #define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
08029 #define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
08030 #define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
08031 #define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
08032 #define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
08033 #define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
08034 #define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
08035 #define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
08036 #define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
08037 #define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
08038 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
08039 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
08040 /**
08041   * @}
08042   */
08043
08044 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
08045   * @{
08046   */
08047 #define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
08048 #define LL_ADC_AWD_THRESHOLD_LOW           (ADC_AWD_TR1_LOW_REGOFFSET)  /*!< ADC analog watchdog threshold low */
08049 /**
08050   * @}
08051   */
08052
08053
08054 /** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
08055   * @note   Only ADC IP HW delays are defined in ADC LL driver driver,
08056   *         not timeout values.
08057   *         For details on delays values, refer to descriptions in source code
08058   *         above each literal definition.
08059   * @{
08060   */
08061
08062 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */
08063 /*       not timeout values.                                                  */
08064 /*       Timeout values for ADC operations are dependent to device clock      */
08065 /*       configuration (system clock versus ADC clock),                       */
08066 /*       and therefore must be defined in user application.                   */
08067 /*       Indications for estimation of ADC timeout delays, for this           */
08068 /*       STM32 serie:                                                         */
08069 /*       - ADC enable time: maximum delay is 1us                              */
08070 /*         (refer to device datasheet, parameter "tSTAB")                     */
08071 /*       - ADC conversion time: duration depending on ADC clock and ADC       */
08072 /*         configuration.                                                     */
08073 /*         (refer to device reference manual, section "Timing")               */
08074
08075 /* Delay for temperature sensor stabilization time.                           */
08076 /* Literal set to maximum value (refer to device datasheet,                   */
08077 /* parameter "tSTART").                                                       */
08078 /* Unit: us                                                                   */
08079 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US    ((uint32_t)  10U)  /*!< Delay for internal voltage reference stabilization time */
08080
08081 /* Delay required between ADC disable and ADC calibration start.              */
08082 /* Note: On this STM32 serie, before starting a calibration,                  */
08083 /*       ADC must be disabled.                                                */
08084 /*       A minimum number of ADC clock cycles are required                    */
08085 /*       between ADC disable state and calibration start.                     */
08086 /*       Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.          */
08087 /*       Wait time can be computed in user application by waiting for the     */
08088 /*       equivalent number of CPU cycles, by taking into account              */
08089 /*       ratio of CPU clock versus ADC clock prescalers.                      */
08090 /* Unit: ADC clock cycles.                                                    */
08091 #define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES ((uint32_t) 2U)  /*!< Delay required between ADC disable and ADC calibration start */
08092
08093 /**
08094   * @}
08095   */
08096
08097 /**
08098   * @}
08099   */
08100
08101
08102 /* Exported macro ------------------------------------------------------------*/
08103 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
08104   * @{
08105   */
08106
08107 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
08108   * @{
08109   */
08110
08111 /**
08112   * @brief  Write a value in ADC register
08113   * @param  __INSTANCE__ ADC Instance
08114   * @param  __REG__ Register to be written
08115   * @param  __VALUE__ Value to be written in the register
08116   * @retval None
08117   */
08118 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
08119
08120 /**
08121   * @brief  Read a value in ADC register
08122   * @param  __INSTANCE__ ADC Instance
08123   * @param  __REG__ Register to be read
08124   * @retval Register value
08125   */
08126 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
08127 /**
08128   * @}
08129   */
08130
08131 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
08132   * @{
08133   */
08134
08135 /**
08136   * @brief  Helper macro to get ADC channel number in decimal format
08137   *         from literals LL_ADC_CHANNEL_x.
08138   * @note   Example:
08139   *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
08140   *           will return decimal number "4".
08141   * @note   The input can be a value from functions where a channel
08142   *         number is returned, either defined with number
08143   *         or with bitfield (only one bit must be set).
08144   * @param  __CHANNEL__ This parameter can be one of the following values:
08145   *         @arg @ref LL_ADC_CHANNEL_0
08146   *         @arg @ref LL_ADC_CHANNEL_1
08147   *         @arg @ref LL_ADC_CHANNEL_2
08148   *         @arg @ref LL_ADC_CHANNEL_3
08149   *         @arg @ref LL_ADC_CHANNEL_4
08150   *         @arg @ref LL_ADC_CHANNEL_5
08151   *         @arg @ref LL_ADC_CHANNEL_6
08152   *         @arg @ref LL_ADC_CHANNEL_7
08153   *         @arg @ref LL_ADC_CHANNEL_8
08154   *         @arg @ref LL_ADC_CHANNEL_9
08155   *         @arg @ref LL_ADC_CHANNEL_10
08156   *         @arg @ref LL_ADC_CHANNEL_11
08157   *         @arg @ref LL_ADC_CHANNEL_12
08158   *         @arg @ref LL_ADC_CHANNEL_13
08159   *         @arg @ref LL_ADC_CHANNEL_14
08160   *         @arg @ref LL_ADC_CHANNEL_15
08161   *         @arg @ref LL_ADC_CHANNEL_16
08162   *         @arg @ref LL_ADC_CHANNEL_17
08163   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
08164   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
08165   *
08166   *         (1) On STM32F37x, parameter available only on ADC instance: ADC1.
08167   * @retval Value between Min_Data=0 and Max_Data=18
08168   */
08169 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \
08170   (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
08171
08172 /**
08173   * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
08174   *         from number in decimal format.
08175   * @note   Example:
08176   *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
08177   *           will return a data equivalent to "LL_ADC_CHANNEL_4".
08178   * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
08179   * @retval Returned value can be one of the following values:
08180   *         @arg @ref LL_ADC_CHANNEL_0
08181   *         @arg @ref LL_ADC_CHANNEL_1
08182   *         @arg @ref LL_ADC_CHANNEL_2
08183   *         @arg @ref LL_ADC_CHANNEL_3
08184   *         @arg @ref LL_ADC_CHANNEL_4
08185   *         @arg @ref LL_ADC_CHANNEL_5
08186   *         @arg @ref LL_ADC_CHANNEL_6
08187   *         @arg @ref LL_ADC_CHANNEL_7
08188   *         @arg @ref LL_ADC_CHANNEL_8
08189   *         @arg @ref LL_ADC_CHANNEL_9
08190   *         @arg @ref LL_ADC_CHANNEL_10
08191   *         @arg @ref LL_ADC_CHANNEL_11
08192   *         @arg @ref LL_ADC_CHANNEL_12
08193   *         @arg @ref LL_ADC_CHANNEL_13
08194   *         @arg @ref LL_ADC_CHANNEL_14
08195   *         @arg @ref LL_ADC_CHANNEL_15
08196   *         @arg @ref LL_ADC_CHANNEL_16
08197   *         @arg @ref LL_ADC_CHANNEL_17
08198   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
08199   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
08200   *
08201   *         (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
08202   *         (1) For ADC channel read back from ADC register,
08203   *             comparison with internal channel parameter to be done
08204   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
08205   */
08206 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                          \
08207   (((__DECIMAL_NB__) <= 9U)                                                                                     \
08208     ? (                                                                                                         \
08209        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |        \
08210        (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))         \
08211       )                                                                                                         \
08212       :                                                                                                         \
08213       (                                                                                                         \
08214        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                              | \
08215        (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
08216       )                                                                                                         \
08217   )
08218
08219 /**
08220   * @brief  Helper macro to determine whether the selected channel
08221   *         corresponds to literal definitions of driver.
08222   * @note   The different literal definitions of ADC channels are:
08223   *         - ADC internal channel:
08224   *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
08225   *         - ADC external channel (channel connected to a GPIO pin):
08226   *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
08227   * @note   The channel parameter must be a value defined from literal
08228   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
08229   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
08230   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
08231   *         must not be a value from functions where a channel number is
08232   *         returned from ADC registers,
08233   *         because internal and external channels share the same channel
08234   *         number in ADC registers. The differentiation is made only with
08235   *         parameters definitions of driver.
08236   * @param  __CHANNEL__ This parameter can be one of the following values:
08237   *         @arg @ref LL_ADC_CHANNEL_0
08238   *         @arg @ref LL_ADC_CHANNEL_1
08239   *         @arg @ref LL_ADC_CHANNEL_2
08240   *         @arg @ref LL_ADC_CHANNEL_3
08241   *         @arg @ref LL_ADC_CHANNEL_4
08242   *         @arg @ref LL_ADC_CHANNEL_5
08243   *         @arg @ref LL_ADC_CHANNEL_6
08244   *         @arg @ref LL_ADC_CHANNEL_7
08245   *         @arg @ref LL_ADC_CHANNEL_8
08246   *         @arg @ref LL_ADC_CHANNEL_9
08247   *         @arg @ref LL_ADC_CHANNEL_10
08248   *         @arg @ref LL_ADC_CHANNEL_11
08249   *         @arg @ref LL_ADC_CHANNEL_12
08250   *         @arg @ref LL_ADC_CHANNEL_13
08251   *         @arg @ref LL_ADC_CHANNEL_14
08252   *         @arg @ref LL_ADC_CHANNEL_15
08253   *         @arg @ref LL_ADC_CHANNEL_16
08254   *         @arg @ref LL_ADC_CHANNEL_17
08255   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
08256   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
08257   *
08258   *         (1) On STM32F37x, parameter available only on ADC instance: ADC1.
08259   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin)
08260   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel
08261   */
08262 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
08263   (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
08264
08265 /**
08266   * @brief  Helper macro to convert a channel defined from parameter
08267   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
08268   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
08269   *         to its equivalent parameter definition of a ADC external channel
08270   *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
08271   * @note   The channel parameter can be, additionally to a value
08272   *         defined from parameter definition of a ADC internal channel
08273   *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
08274   *         a value defined from parameter definition of
08275   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
08276   *         or a value from functions where a channel number is returned
08277   *         from ADC registers.
08278   * @param  __CHANNEL__ This parameter can be one of the following values:
08279   *         @arg @ref LL_ADC_CHANNEL_0
08280   *         @arg @ref LL_ADC_CHANNEL_1
08281   *         @arg @ref LL_ADC_CHANNEL_2
08282   *         @arg @ref LL_ADC_CHANNEL_3
08283   *         @arg @ref LL_ADC_CHANNEL_4
08284   *         @arg @ref LL_ADC_CHANNEL_5
08285   *         @arg @ref LL_ADC_CHANNEL_6
08286   *         @arg @ref LL_ADC_CHANNEL_7
08287   *         @arg @ref LL_ADC_CHANNEL_8
08288   *         @arg @ref LL_ADC_CHANNEL_9
08289   *         @arg @ref LL_ADC_CHANNEL_10
08290   *         @arg @ref LL_ADC_CHANNEL_11
08291   *         @arg @ref LL_ADC_CHANNEL_12
08292   *         @arg @ref LL_ADC_CHANNEL_13
08293   *         @arg @ref LL_ADC_CHANNEL_14
08294   *         @arg @ref LL_ADC_CHANNEL_15
08295   *         @arg @ref LL_ADC_CHANNEL_16
08296   *         @arg @ref LL_ADC_CHANNEL_17
08297   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
08298   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
08299   *
08300   *         (1) On STM32F37x, parameter available only on ADC instance: ADC1.
08301   * @retval Returned value can be one of the following values:
08302   *         @arg @ref LL_ADC_CHANNEL_0
08303   *         @arg @ref LL_ADC_CHANNEL_1
08304   *         @arg @ref LL_ADC_CHANNEL_2
08305   *         @arg @ref LL_ADC_CHANNEL_3
08306   *         @arg @ref LL_ADC_CHANNEL_4
08307   *         @arg @ref LL_ADC_CHANNEL_5
08308   *         @arg @ref LL_ADC_CHANNEL_6
08309   *         @arg @ref LL_ADC_CHANNEL_7
08310   *         @arg @ref LL_ADC_CHANNEL_8
08311   *         @arg @ref LL_ADC_CHANNEL_9
08312   *         @arg @ref LL_ADC_CHANNEL_10
08313   *         @arg @ref LL_ADC_CHANNEL_11
08314   *         @arg @ref LL_ADC_CHANNEL_12
08315   *         @arg @ref LL_ADC_CHANNEL_13
08316   *         @arg @ref LL_ADC_CHANNEL_14
08317   *         @arg @ref LL_ADC_CHANNEL_15
08318   *         @arg @ref LL_ADC_CHANNEL_16
08319   *         @arg @ref LL_ADC_CHANNEL_17
08320   */
08321 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
08322   ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
08323
08324 /**
08325   * @brief  Helper macro to determine whether the internal channel
08326   *         selected is available on the ADC instance selected.
08327   * @note   The channel parameter must be a value defined from parameter
08328   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
08329   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
08330   *         must not be a value defined from parameter definition of
08331   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
08332   *         or a value from functions where a channel number is
08333   *         returned from ADC registers,
08334   *         because internal and external channels share the same channel
08335   *         number in ADC registers. The differentiation is made only with
08336   *         parameters definitions of driver.
08337   * @param  __ADC_INSTANCE__ ADC instance
08338   * @param  __CHANNEL__ This parameter can be one of the following values:
08339   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
08340   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
08341   *
08342   *         (1) On STM32F37x, parameter available only on ADC instance: ADC1.
08343   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
08344   *         Value "1" if the internal channel selected is available on the ADC instance selected.
08345   */
08346 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
08347   (((__ADC_INSTANCE__) == ADC1)                                                \
08348     ? (                                                                        \
08349        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                         \
08350        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)                            \
08351       )                                                                        \
08352       :                                                                        \
08353       (0U)                                                                     \
08354   )
08355
08356 /**
08357   * @brief  Helper macro to define ADC analog watchdog parameter:
08358   *         define a single channel to monitor with analog watchdog
08359   *         from sequencer channel and groups definition.
08360   * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
08361   *         Example:
08362   *           LL_ADC_SetAnalogWDMonitChannels(
08363   *             ADC1, LL_ADC_AWD1,
08364   *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
08365   * @param  __CHANNEL__ This parameter can be one of the following values:
08366   *         @arg @ref LL_ADC_CHANNEL_0
08367   *         @arg @ref LL_ADC_CHANNEL_1
08368   *         @arg @ref LL_ADC_CHANNEL_2
08369   *         @arg @ref LL_ADC_CHANNEL_3
08370   *         @arg @ref LL_ADC_CHANNEL_4
08371   *         @arg @ref LL_ADC_CHANNEL_5
08372   *         @arg @ref LL_ADC_CHANNEL_6
08373   *         @arg @ref LL_ADC_CHANNEL_7
08374   *         @arg @ref LL_ADC_CHANNEL_8
08375   *         @arg @ref LL_ADC_CHANNEL_9
08376   *         @arg @ref LL_ADC_CHANNEL_10
08377   *         @arg @ref LL_ADC_CHANNEL_11
08378   *         @arg @ref LL_ADC_CHANNEL_12
08379   *         @arg @ref LL_ADC_CHANNEL_13
08380   *         @arg @ref LL_ADC_CHANNEL_14
08381   *         @arg @ref LL_ADC_CHANNEL_15
08382   *         @arg @ref LL_ADC_CHANNEL_16
08383   *         @arg @ref LL_ADC_CHANNEL_17
08384   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
08385   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
08386   *
08387   *         (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
08388   *         (1) For ADC channel read back from ADC register,
08389   *             comparison with internal channel parameter to be done
08390   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
08391   * @param  __GROUP__ This parameter can be one of the following values:
08392   *         @arg @ref LL_ADC_GROUP_REGULAR
08393   *         @arg @ref LL_ADC_GROUP_INJECTED
08394   *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
08395   * @retval Returned value can be one of the following values:
08396   *         @arg @ref LL_ADC_AWD_DISABLE
08397   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
08398   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
08399   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
08400   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG
08401   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
08402   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
08403   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG
08404   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
08405   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
08406   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG
08407   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
08408   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
08409   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG
08410   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
08411   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
08412   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG
08413   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
08414   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
08415   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG
08416   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
08417   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
08418   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG
08419   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
08420   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
08421   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG
08422   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
08423   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
08424   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG
08425   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
08426   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
08427   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG
08428   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
08429   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
08430   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
08431   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
08432   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
08433   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
08434   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
08435   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
08436   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
08437   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
08438   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
08439   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
08440   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
08441   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
08442   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
08443   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
08444   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
08445   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
08446   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
08447   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
08448   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG
08449   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
08450   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
08451   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
08452   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
08453   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
08454   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (1)
08455   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (1)
08456   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ      (1)
08457   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (1)
08458   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (1)
08459   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   (1)
08460   *
08461   *         (1) On STM32F37x, parameter available only on ADC instance: ADC1.
08462   */
08463 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \
08464   (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
08465     ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)                            \
08466       :                                                                                                   \
08467       ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                              \
08468        ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)                        \
08469          :                                                                                                \
08470          (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)        \
08471   )
08472
08473 /**
08474   * @brief  Helper macro to set the value of ADC analog watchdog threshold high
08475   *         or low in function of ADC resolution, when ADC resolution is
08476   *         different of 12 bits.
08477   * @note   To be used with function @ref LL_ADC_SetAnalogWDThresholds().
08478   *         Example, with a ADC resolution of 8 bits, to set the value of
08479   *         analog watchdog threshold high (on 8 bits):
08480   *           LL_ADC_SetAnalogWDThresholds
08481   *            (< ADCx param >,
08482   *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
08483   *            );
08484   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
08485   *         @arg @ref LL_ADC_RESOLUTION_12B
08486   * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
08487   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
08488   */
08489 /* Note: On this STM32 serie, ADC is fixed to resolution 12 bits.             */
08490 /*       This macro has been kept anyway for compatibility with other         */
08491 /*       STM32 families featuring different ADC resolutions.                  */
08492 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
08493   ((__AWD_THRESHOLD__) << (0U))
08494
08495 /**
08496   * @brief  Helper macro to get the value of ADC analog watchdog threshold high
08497   *         or low in function of ADC resolution, when ADC resolution is
08498   *         different of 12 bits.
08499   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
08500   *         Example, with a ADC resolution of 8 bits, to get the value of
08501   *         analog watchdog threshold high (on 8 bits):
08502   *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
08503   *            (LL_ADC_RESOLUTION_8B,
08504   *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
08505   *            );
08506   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
08507   *         @arg @ref LL_ADC_RESOLUTION_12B
08508   * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
08509   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
08510   */
08511 /* Note: On this STM32 serie, ADC is fixed to resolution 12 bits.             */
08512 /*       This macro has been kept anyway for compatibility with other         */
08513 /*       STM32 families featuring different ADC resolutions.                  */
08514 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
08515   (__AWD_THRESHOLD_12_BITS__)
08516
08517 /**
08518   * @brief  Helper macro to select the ADC common instance
08519   *         to which is belonging the selected ADC instance.
08520   * @note   ADC common register instance can be used for:
08521   *         - Set parameters common to several ADC instances
08522   *         - Multimode (for devices with several ADC instances)
08523   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
08524   * @note   On STM32F37x, there is no common ADC instance.
08525   *         However, ADC instance ADC1 has a role of common ADC instance
08526   *         (equivalence with other STM32 families featuring several
08527   *         ADC instances).
08528   * @param  __ADCx__ ADC instance
08529   * @retval ADC common register instance
08530   */
08531 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
08532   (ADC1_COMMON)
08533
08534 /**
08535   * @brief  Helper macro to check if all ADC instances sharing the same
08536   *         ADC common instance are disabled.
08537   * @note   This check is required by functions with setting conditioned to
08538   *         ADC state:
08539   *         All ADC instances of the ADC common group must be disabled.
08540   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
08541   * @note   On devices with only 1 ADC common instance, parameter of this macro
08542   *         is useless and can be ignored (parameter kept for compatibility
08543   *         with devices featuring several ADC common instances).
08544   * @note   On STM32F37x, there is no common ADC instance.
08545   *         However, ADC instance ADC1 has a role of common ADC instance
08546   *         (equivalence with other STM32 families featuring several
08547   *         ADC instances).
08548   * @param  __ADCXY_COMMON__ ADC common instance
08549   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08550   * @retval Value "0" All ADC instances sharing the same ADC common instance
08551   *         are disabled.
08552   *         Value "1" At least one ADC instance sharing the same ADC common instance
08553   *         is enabled
08554   */
08555 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
08556   LL_ADC_IsEnabled(ADC1)
08557
08558 /**
08559   * @brief  Helper macro to define the ADC conversion data full-scale digital
08560   *         value corresponding to the selected ADC resolution.
08561   * @note   ADC conversion data full-scale corresponds to voltage range
08562   *         determined by analog voltage references Vref+ and Vref-
08563   *         (refer to reference manual).
08564   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
08565   *         @arg @ref LL_ADC_RESOLUTION_12B
08566   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
08567   */
08568 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
08569   ((uint32_t)0xFFFU)
08570
08571 /**
08572   * @brief  Helper macro to convert the ADC conversion data from
08573   *         a resolution to another resolution.
08574   * @note   On STM32F37x, the only ADC resolution available is 12 bits.
08575   *         This macro has been kept for compatibility purpose over other
08576   *         STM32 families.
08577   * @param  __DATA__ ADC conversion data to be converted
08578   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
08579   *         This parameter can be one of the following values:
08580   *         @arg @ref LL_ADC_RESOLUTION_12B
08581   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
08582   *         This parameter can be one of the following values:
08583   *         @arg @ref LL_ADC_RESOLUTION_12B
08584   * @retval ADC conversion data to the requested resolution
08585   */
08586 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
08587                                          __ADC_RESOLUTION_CURRENT__,\
08588                                          __ADC_RESOLUTION_TARGET__)            \
08589   (((__DATA__)                                                                 \
08590     << ((__ADC_RESOLUTION_CURRENT__) >> (0U)))                                 \
08591    >> ((__ADC_RESOLUTION_TARGET__) >> (0U))                                    \
08592   )
08593
08594 /**
08595   * @brief  Helper macro to calculate the voltage (unit: mVolt)
08596   *         corresponding to a ADC conversion data (unit: digital value).
08597   * @note   Analog reference voltage (Vref+) must be either known from
08598   *         user board environment or can be calculated using ADC measurement
08599   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
08600   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
08601   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
08602   *                       (unit: digital value).
08603   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
08604   *         @arg @ref LL_ADC_RESOLUTION_12B
08605   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
08606   */
08607 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
08608                                       __ADC_DATA__,\
08609                                       __ADC_RESOLUTION__)                      \
08610   ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
08611    / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
08612   )
08613
08614
08615 /**
08616   * @brief  Helper macro to calculate analog reference voltage (Vref+)
08617   *         (unit: mVolt) from ADC conversion data of internal voltage
08618   *         reference VrefInt.
08619   * @note   Computation is using VrefInt calibration value
08620   *         stored in system memory for each device during production.
08621   * @note   This voltage depends on user board environment: voltage level
08622   *         connected to pin Vref+.
08623   *         On devices with small package, the pin Vref+ is not present
08624   *         and internally bonded to pin Vdda.
08625   * @note   On this STM32 serie, calibration data of internal voltage reference
08626   *         VrefInt corresponds to a resolution of 12 bits,
08627   *         this is the recommended ADC resolution to convert voltage of
08628   *         internal voltage reference VrefInt.
08629   *         On STM32F37x, the only ADC resolution available is 12 bits.
08630   *         The parameter of ADC resolution is kept for compatibility purpose
08631   *         over other STM32 families.
08632   * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
08633   *         of internal voltage reference VrefInt (unit: digital value).
08634   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
08635   *         @arg @ref LL_ADC_RESOLUTION_12B
08636   * @retval Analog reference voltage (unit: mV)
08637   */
08638 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
08639                                          __ADC_RESOLUTION__)                   \
08640   (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
08641     / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                 \
08642                                        (__ADC_RESOLUTION__),                   \
08643                                        LL_ADC_RESOLUTION_12B)                  \
08644   )
08645
08646 /**
08647   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
08648   *         from ADC conversion data of internal temperature sensor.
08649   * @note   Computation is using temperature sensor calibration values
08650   *         stored in system memory for each device during production.
08651   * @note   Calculation formula:
08652   *           Temperature = ((TS_ADC_DATA - TS_CAL1)
08653   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
08654   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
08655   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
08656   *                Avg_Slope = (TS_CAL2 - TS_CAL1)
08657   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
08658   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
08659   *                            TEMP_DEGC_CAL1 (calibrated in factory)
08660   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
08661   *                            TEMP_DEGC_CAL2 (calibrated in factory)
08662   *         Caution: Calculation relevancy under reserve that calibration
08663   *                  parameters are correct (address and data).
08664   *                  To calculate temperature using temperature sensor
08665   *                  datasheet typical values (generic values less, therefore
08666   *                  less accurate than calibrated values),
08667   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
08668   * @note   As calculation input, the analog reference voltage (Vref+) must be
08669   *         defined as it impacts the ADC LSB equivalent voltage.
08670   * @note   Analog reference voltage (Vref+) must be either known from
08671   *         user board environment or can be calculated using ADC measurement
08672   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
08673   * @note   On this STM32 serie, calibration data of temperature sensor
08674   *         corresponds to a resolution of 12 bits,
08675   *         this is the recommended ADC resolution to convert voltage of
08676   *         temperature sensor.
08677   *         On STM32F37x, the only ADC resolution available is 12 bits.
08678   *         The parameter of ADC resolution is kept for compatibility purpose
08679   *         over other STM32 families.
08680   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
08681   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
08682   *                                 temperature sensor (unit: digital value).
08683   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
08684   *                                 sensor voltage has been measured.
08685   *         This parameter can be one of the following values:
08686   *         @arg @ref LL_ADC_RESOLUTION_12B
08687   * @retval Temperature (unit: degree Celsius)
08688   */
08689 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
08690                                   __TEMPSENSOR_ADC_DATA__,\
08691                                   __ADC_RESOLUTION__)                              \
08692   (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
08693                                                     (__ADC_RESOLUTION__),          \
08694                                                     LL_ADC_RESOLUTION_12B)         \
08695                    * (__VREFANALOG_VOLTAGE__))                                     \
08696                   / TEMPSENSOR_CAL_VREFANALOG)                                     \
08697         - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
08698      ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
08699     ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
08700    ) + TEMPSENSOR_CAL1_TEMP                                                        \
08701   )
08702
08703 /**
08704   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
08705   *         from ADC conversion data of internal temperature sensor.
08706   * @note   Computation is using temperature sensor typical values
08707   *         (refer to device datasheet).
08708   * @note   Calculation formula:
08709   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
08710   *                         / Avg_Slope + CALx_TEMP
08711   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
08712   *                                   (unit: digital value)
08713   *                Avg_Slope        = temperature sensor slope
08714   *                                   (unit: uV/Degree Celsius)
08715   *                TS_TYP_CALx_VOLT = temperature sensor digital value at
08716   *                                   temperature CALx_TEMP (unit: mV)
08717   *         Caution: Calculation relevancy under reserve the temperature sensor
08718   *                  of the current device has characteristics in line with
08719   *                  datasheet typical values.
08720   *                  If temperature sensor calibration values are available on
08721   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
08722   *                  temperature calculation will be more accurate using
08723   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
08724   * @note   As calculation input, the analog reference voltage (Vref+) must be
08725   *         defined as it impacts the ADC LSB equivalent voltage.
08726   * @note   Analog reference voltage (Vref+) must be either known from
08727   *         user board environment or can be calculated using ADC measurement
08728   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
08729   * @note   ADC measurement data must correspond to a resolution of 12bits
08730   *         (full scale digital value 4095). If not the case, the data must be
08731   *         preliminarily rescaled to an equivalent resolution of 12 bits.
08732   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
08733   *                                       On STM32F37x, refer to device datasheet parameter "Avg_Slope".
08734   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
08735   *                                       On STM32F37x, refer to device datasheet parameter "V25".
08736   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
08737   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
08738   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
08739   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
08740   *         This parameter can be one of the following values:
08741   *         @arg @ref LL_ADC_RESOLUTION_12B
08742   * @retval Temperature (unit: degree Celsius)
08743   */
08744 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
08745                                              __TEMPSENSOR_TYP_CALX_V__,\
08746                                              __TEMPSENSOR_CALX_TEMP__,\
08747                                              __VREFANALOG_VOLTAGE__,\
08748                                              __TEMPSENSOR_ADC_DATA__,\
08749                                              __ADC_RESOLUTION__)               \
08750   ((( (                                                                        \
08751        (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
08752                  * 1000)                                                       \
08753        -                                                                       \
08754        (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
08755                   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
08756                  * 1000)                                                       \
08757       )                                                                        \
08758     ) / (__TEMPSENSOR_TYP_AVGSLOPE__)                                          \
08759    ) + (__TEMPSENSOR_CALX_TEMP__)                                              \
08760   )
08761
08762 /**
08763   * @}
08764   */
08765
08766 /**
08767   * @}
08768   */
08769
08770
08771 /* Exported functions --------------------------------------------------------*/
08772 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
08773   * @{
08774   */
08775
08776 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
08777   * @{
08778   */
08779 /* Note: LL ADC functions to set DMA transfer are located into sections of    */
08780 /*       configuration of ADC instance, groups and multimode (if available):  */
08781 /*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
08782
08783 /**
08784   * @brief  Function to help to configure DMA transfer from ADC: retrieve the
08785   *         ADC register address from ADC instance and a list of ADC registers
08786   *         intended to be used (most commonly) with DMA transfer.
08787   * @note   These ADC registers are data registers:
08788   *         when ADC conversion data is available in ADC data registers,
08789   *         ADC generates a DMA transfer request.
08790   * @note   This macro is intended to be used with LL DMA driver, refer to
08791   *         function "LL_DMA_ConfigAddresses()".
08792   *         Example:
08793   *           LL_DMA_ConfigAddresses(DMA1,
08794   *                                  LL_DMA_CHANNEL_1,
08795   *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
08796   *                                  (uint32_t)&< array or variable >,
08797   *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
08798   * @note   For devices with several ADC: in multimode, some devices
08799   *         use a different data register outside of ADC instance scope
08800   *         (common data register). This macro manages this register difference,
08801   *         only ADC instance has to be set as parameter.
08802   * @rmtoll DR       DATA           LL_ADC_DMA_GetRegAddr
08803   * @param  ADCx ADC instance
08804   * @param  Register This parameter can be one of the following values:
08805   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
08806   * @retval ADC register address
08807   */
08808 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
08809 {
08810   /* Retrieve address of register DR */
08811   return (uint32_t)&(ADCx->DR);
08812 }
08813
08814 /**
08815   * @}
08816   */
08817
08818 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
08819   * @{
08820   */
08821
08822 /**
08823   * @brief  Set parameter common to several ADC: measurement path to internal
08824   *         channels (VrefInt, temperature sensor, ...).
08825   * @note   One or several values can be selected.
08826   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
08827   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
08828   * @note   Stabilization time of measurement path to internal channel:
08829   *         After enabling internal paths, before starting ADC conversion,
08830   *         a delay is required for internal voltage reference and
08831   *         temperature sensor stabilization time.
08832   *         Refer to device datasheet.
08833   *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
08834   * @note   ADC internal channel sampling time constraint:
08835   *         For ADC conversion of internal channels,
08836   *         a sampling time minimum value is required.
08837   *         Refer to device datasheet.
08838   * @rmtoll CR2      TSVREFE        LL_ADC_SetCommonPathInternalCh
08839   * @param  ADCxy_COMMON ADC common instance
08840   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08841   * @param  PathInternal This parameter can be a combination of the following values:
08842   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
08843   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
08844   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
08845   * @retval None
08846   */
08847 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
08848 {
08849   MODIFY_REG(ADCxy_COMMON->CR2, (ADC_CR2_TSVREFE), PathInternal);
08850 }
08851
08852 /**
08853   * @brief  Get parameter common to several ADC: measurement path to internal
08854   *         channels (VrefInt, temperature sensor, ...).
08855   * @note   One or several values can be selected.
08856   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
08857   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
08858   * @rmtoll CR2      TSVREFE        LL_ADC_GetCommonPathInternalCh
08859   * @param  ADCxy_COMMON ADC common instance
08860   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08861   * @retval Returned value can be a combination of the following values:
08862   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
08863   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
08864   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
08865   */
08866 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
08867 {
08868   return (uint32_t)(READ_BIT(ADCxy_COMMON->CR2, ADC_CR2_TSVREFE));
08869 }
08870
08871 /**
08872   * @}
08873   */
08874
08875 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
08876   * @{
08877   */
08878
08879 /**
08880   * @brief  Set ADC conversion data alignment.
08881   * @note   Refer to reference manual for alignments formats
08882   *         dependencies to ADC resolutions.
08883   * @rmtoll CR2      ALIGN          LL_ADC_SetDataAlignment
08884   * @param  ADCx ADC instance
08885   * @param  DataAlignment This parameter can be one of the following values:
08886   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
08887   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
08888   * @retval None
08889   */
08890 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
08891 {
08892   MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
08893 }
08894
08895 /**
08896   * @brief  Get ADC conversion data alignment.
08897   * @note   Refer to reference manual for alignments formats
08898   *         dependencies to ADC resolutions.
08899   * @rmtoll CR2      ALIGN          LL_ADC_SetDataAlignment
08900   * @param  ADCx ADC instance
08901   * @retval Returned value can be one of the following values:
08902   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
08903   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
08904   */
08905 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
08906 {
08907   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
08908 }
08909
08910 /**
08911   * @brief  Set ADC sequencers scan mode, for all ADC groups
08912   *         (group regular, group injected).
08913   * @note  According to sequencers scan mode :
08914   *         - If disabled: ADC conversion is performed in unitary conversion
08915   *           mode (one channel converted, that defined in rank 1).
08916   *           Configuration of sequencers of all ADC groups
08917   *           (sequencer scan length, ...) is discarded: equivalent to
08918   *           scan length of 1 rank.
08919   *         - If enabled: ADC conversions are performed in sequence conversions
08920   *           mode, according to configuration of sequencers of
08921   *           each ADC group (sequencer scan length, ...).
08922   *           Refer to function @ref LL_ADC_REG_SetSequencerLength()
08923   *           and to function @ref LL_ADC_INJ_SetSequencerLength().
08924   * @rmtoll CR1      SCAN           LL_ADC_SetSequencersScanMode
08925   * @param  ADCx ADC instance
08926   * @param  ScanMode This parameter can be one of the following values:
08927   *         @arg @ref LL_ADC_SEQ_SCAN_DISABLE
08928   *         @arg @ref LL_ADC_SEQ_SCAN_ENABLE
08929   * @retval None
08930   */
08931 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
08932 {
08933   MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
08934 }
08935
08936 /**
08937   * @brief  Get ADC sequencers scan mode, for all ADC groups
08938   *         (group regular, group injected).
08939   * @note  According to sequencers scan mode :
08940   *         - If disabled: ADC conversion is performed in unitary conversion
08941   *           mode (one channel converted, that defined in rank 1).
08942   *           Configuration of sequencers of all ADC groups
08943   *           (sequencer scan length, ...) is discarded: equivalent to
08944   *           scan length of 1 rank.
08945   *         - If enabled: ADC conversions are performed in sequence conversions
08946   *           mode, according to configuration of sequencers of
08947   *           each ADC group (sequencer scan length, ...).
08948   *           Refer to function @ref LL_ADC_REG_SetSequencerLength()
08949   *           and to function @ref LL_ADC_INJ_SetSequencerLength().
08950   * @rmtoll CR1      SCAN           LL_ADC_GetSequencersScanMode
08951   * @param  ADCx ADC instance
08952   * @retval Returned value can be one of the following values:
08953   *         @arg @ref LL_ADC_SEQ_SCAN_DISABLE
08954   *         @arg @ref LL_ADC_SEQ_SCAN_ENABLE
08955   */
08956 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
08957 {
08958   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
08959 }
08960
08961 /**
08962   * @}
08963   */
08964
08965 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
08966   * @{
08967   */
08968
08969 /**
08970   * @brief  Set ADC group regular conversion trigger source:
08971   *         internal (SW start) or external from timer or external interrupt.
08972   * @note   On this STM32 serie, external trigger is set with trigger polarity:
08973   *         rising edge (only trigger polarity available on this STM32 serie).
08974   * @note   Availability of parameters of trigger sources from timer
08975   *         depends on timers availability on the selected device.
08976   * @rmtoll CR2      EXTSEL         LL_ADC_REG_SetTriggerSource
08977   * @param  ADCx ADC instance
08978   * @param  TriggerSource This parameter can be one of the following values:
08979   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
08980   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
08981   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
08982   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH2
08983   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_TRGO
08984   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH3
08985   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH4
08986   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
08987   * @retval None
08988   */
08989 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
08990 {
08991 /* Note: On this STM32 serie, ADC group regular external trigger edge         */
08992 /*       is used to perform a ADC conversion start.                           */
08993 /*       This function does not set external trigger edge.                    */
08994 /*       This feature is set using function                                   */
08995 /*       @ref LL_ADC_REG_StartConversionExtTrig().                            */
08996   MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
08997 }
08998
08999 /**
09000   * @brief  Get ADC group regular conversion trigger source:
09001   *         internal (SW start) or external from timer or external interrupt.
09002   * @note   To determine whether group regular trigger source is
09003   *         internal (SW start) or external, without detail
09004   *         of which peripheral is selected as external trigger,
09005   *         (equivalent to
09006   *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
09007   *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
09008   * @note   Availability of parameters of trigger sources from timer
09009   *         depends on timers availability on the selected device.
09010   * @rmtoll CR2      EXTSEL         LL_ADC_REG_GetTriggerSource
09011   * @param  ADCx ADC instance
09012   * @retval Returned value can be one of the following values:
09013   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
09014   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
09015   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
09016   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH2
09017   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_TRGO
09018   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH3
09019   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH4
09020   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
09021   */
09022 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
09023 {
09024   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL));
09025 }
09026
09027 /**
09028   * @brief  Get ADC group regular conversion trigger source internal (SW start)
09029             or external.
09030   * @note   In case of group regular trigger source set to external trigger,
09031   *         to determine which peripheral is selected as external trigger,
09032   *         use function @ref LL_ADC_REG_GetTriggerSource().
09033   * @rmtoll CR2      EXTSEL         LL_ADC_REG_IsTriggerSourceSWStart
09034   * @param  ADCx ADC instance
09035   * @retval Value "0" trigger source external trigger
09036   *         Value "1" trigger source SW start.
09037   */
09038 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
09039 {
09040   return (READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL) == (LL_ADC_REG_TRIG_SOFTWARE));
09041 }
09042
09043
09044 /**
09045   * @brief  Set ADC group regular sequencer length and scan direction.
09046   * @note   Description of ADC group regular sequencer features:
09047   *         - For devices with sequencer fully configurable
09048   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
09049   *           sequencer length and each rank affectation to a channel
09050   *           are configurable.
09051   *           This function performs configuration of:
09052   *           - Sequence length: Number of ranks in the scan sequence.
09053   *           - Sequence direction: Unless specified in parameters, sequencer
09054   *             scan direction is forward (from rank 1 to rank n).
09055   *           Sequencer ranks are selected using
09056   *           function "LL_ADC_REG_SetSequencerRanks()".
09057   *         - For devices with sequencer not fully configurable
09058   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
09059   *           sequencer length and each rank affectation to a channel
09060   *           are defined by channel number.
09061   *           This function performs configuration of:
09062   *           - Sequence length: Number of ranks in the scan sequence is
09063   *             defined by number of channels set in the sequence,
09064   *             rank of each channel is fixed by channel HW number.
09065   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
09066   *           - Sequence direction: Unless specified in parameters, sequencer
09067   *             scan direction is forward (from lowest channel number to
09068   *             highest channel number).
09069   *           Sequencer ranks are selected using
09070   *           function "LL_ADC_REG_SetSequencerChannels()".
09071   * @note   On this STM32 serie, group regular sequencer configuration
09072   *         is conditioned to ADC instance sequencer mode.
09073   *         If ADC instance sequencer mode is disabled, sequencers of
09074   *         all groups (group regular, group injected) can be configured
09075   *         but their execution is disabled (limited to rank 1).
09076   *         Refer to function @ref LL_ADC_SetSequencersScanMode().
09077   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
09078   *         ADC conversion on only 1 channel.
09079   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
09080   * @param  ADCx ADC instance
09081   * @param  SequencerNbRanks This parameter can be one of the following values:
09082   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
09083   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
09084   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
09085   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
09086   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
09087   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
09088   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
09089   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
09090   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
09091   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
09092   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
09093   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
09094   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
09095   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
09096   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
09097   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
09098   * @retval None
09099   */
09100 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
09101 {
09102   MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
09103 }
09104
09105 /**
09106   * @brief  Get ADC group regular sequencer length and scan direction.
09107   * @note   Description of ADC group regular sequencer features:
09108   *         - For devices with sequencer fully configurable
09109   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
09110   *           sequencer length and each rank affectation to a channel
09111   *           are configurable.
09112   *           This function retrieves:
09113   *           - Sequence length: Number of ranks in the scan sequence.
09114   *           - Sequence direction: Unless specified in parameters, sequencer
09115   *             scan direction is forward (from rank 1 to rank n).
09116   *           Sequencer ranks are selected using
09117   *           function "LL_ADC_REG_SetSequencerRanks()".
09118   *         - For devices with sequencer not fully configurable
09119   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
09120   *           sequencer length and each rank affectation to a channel
09121   *           are defined by channel number.
09122   *           This function retrieves:
09123   *           - Sequence length: Number of ranks in the scan sequence is
09124   *             defined by number of channels set in the sequence,
09125   *             rank of each channel is fixed by channel HW number.
09126   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
09127   *           - Sequence direction: Unless specified in parameters, sequencer
09128   *             scan direction is forward (from lowest channel number to
09129   *             highest channel number).
09130   *           Sequencer ranks are selected using
09131   *           function "LL_ADC_REG_SetSequencerChannels()".
09132   * @note   On this STM32 serie, group regular sequencer configuration
09133   *         is conditioned to ADC instance sequencer mode.
09134   *         If ADC instance sequencer mode is disabled, sequencers of
09135   *         all groups (group regular, group injected) can be configured
09136   *         but their execution is disabled (limited to rank 1).
09137   *         Refer to function @ref LL_ADC_SetSequencersScanMode().
09138   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
09139   *         ADC conversion on only 1 channel.
09140   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
09141   * @param  ADCx ADC instance
09142   * @retval Returned value can be one of the following values:
09143   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
09144   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
09145   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
09146   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
09147   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
09148   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
09149   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
09150   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
09151   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
09152   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
09153   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
09154   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
09155   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
09156   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
09157   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
09158   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
09159   */
09160 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
09161 {
09162   return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
09163 }
09164
09165 /**
09166   * @brief  Set ADC group regular sequencer discontinuous mode:
09167   *         sequence subdivided and scan conversions interrupted every selected
09168   *         number of ranks.
09169   * @note   It is not possible to enable both ADC group regular
09170   *         continuous mode and sequencer discontinuous mode.
09171   * @note   It is not possible to enable both ADC auto-injected mode
09172   *         and ADC group regular sequencer discontinuous mode.
09173   * @rmtoll CR1      DISCEN         LL_ADC_REG_SetSequencerDiscont\n
09174   *         CR1      DISCNUM        LL_ADC_REG_SetSequencerDiscont
09175   * @param  ADCx ADC instance
09176   * @param  SeqDiscont This parameter can be one of the following values:
09177   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
09178   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
09179   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
09180   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
09181   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
09182   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
09183   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
09184   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
09185   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
09186   * @retval None
09187   */
09188 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
09189 {
09190   MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
09191 }
09192
09193 /**
09194   * @brief  Get ADC group regular sequencer discontinuous mode:
09195   *         sequence subdivided and scan conversions interrupted every selected
09196   *         number of ranks.
09197   * @rmtoll CR1      DISCEN         LL_ADC_REG_GetSequencerDiscont\n
09198   *         CR1      DISCNUM        LL_ADC_REG_GetSequencerDiscont
09199   * @param  ADCx ADC instance
09200   * @retval Returned value can be one of the following values:
09201   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
09202   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
09203   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
09204   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
09205   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
09206   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
09207   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
09208   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
09209   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
09210   */
09211 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
09212 {
09213   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
09214 }
09215
09216 /**
09217   * @brief  Set ADC group regular sequence: channel on the selected
09218   *         scan sequence rank.
09219   * @note   This function performs configuration of:
09220   *         - Channels ordering into each rank of scan sequence:
09221   *           whatever channel can be placed into whatever rank.
09222   * @note   On this STM32 serie, ADC group regular sequencer is
09223   *         fully configurable: sequencer length and each rank
09224   *         affectation to a channel are configurable.
09225   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
09226   * @note   Depending on devices and packages, some channels may not be available.
09227   *         Refer to device datasheet for channels availability.
09228   * @note   On this STM32 serie, to measure internal channels (VrefInt,
09229   *         TempSensor, ...), measurement paths to internal channels must be
09230   *         enabled separately.
09231   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
09232   * @rmtoll SQR3     SQ1            LL_ADC_REG_SetSequencerRanks\n
09233   *         SQR3     SQ2            LL_ADC_REG_SetSequencerRanks\n
09234   *         SQR3     SQ3            LL_ADC_REG_SetSequencerRanks\n
09235   *         SQR3     SQ4            LL_ADC_REG_SetSequencerRanks\n
09236   *         SQR3     SQ5            LL_ADC_REG_SetSequencerRanks\n
09237   *         SQR3     SQ6            LL_ADC_REG_SetSequencerRanks\n
09238   *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n
09239   *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n
09240   *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n
09241   *         SQR2     SQ10           LL_ADC_REG_SetSequencerRanks\n
09242   *         SQR2     SQ11           LL_ADC_REG_SetSequencerRanks\n
09243   *         SQR2     SQ12           LL_ADC_REG_SetSequencerRanks\n
09244   *         SQR1     SQ13           LL_ADC_REG_SetSequencerRanks\n
09245   *         SQR1     SQ14           LL_ADC_REG_SetSequencerRanks\n
09246   *         SQR1     SQ15           LL_ADC_REG_SetSequencerRanks\n
09247   *         SQR1     SQ16           LL_ADC_REG_SetSequencerRanks
09248   * @param  ADCx ADC instance
09249   * @param  Rank This parameter can be one of the following values:
09250   *         @arg @ref LL_ADC_REG_RANK_1
09251   *         @arg @ref LL_ADC_REG_RANK_2
09252   *         @arg @ref LL_ADC_REG_RANK_3
09253   *         @arg @ref LL_ADC_REG_RANK_4
09254   *         @arg @ref LL_ADC_REG_RANK_5
09255   *         @arg @ref LL_ADC_REG_RANK_6
09256   *         @arg @ref LL_ADC_REG_RANK_7
09257   *         @arg @ref LL_ADC_REG_RANK_8
09258   *         @arg @ref LL_ADC_REG_RANK_9
09259   *         @arg @ref LL_ADC_REG_RANK_10
09260   *         @arg @ref LL_ADC_REG_RANK_11
09261   *         @arg @ref LL_ADC_REG_RANK_12
09262   *         @arg @ref LL_ADC_REG_RANK_13
09263   *         @arg @ref LL_ADC_REG_RANK_14
09264   *         @arg @ref LL_ADC_REG_RANK_15
09265   *         @arg @ref LL_ADC_REG_RANK_16
09266   * @param  Channel This parameter can be one of the following values:
09267   *         @arg @ref LL_ADC_CHANNEL_0
09268   *         @arg @ref LL_ADC_CHANNEL_1
09269   *         @arg @ref LL_ADC_CHANNEL_2
09270   *         @arg @ref LL_ADC_CHANNEL_3
09271   *         @arg @ref LL_ADC_CHANNEL_4
09272   *         @arg @ref LL_ADC_CHANNEL_5
09273   *         @arg @ref LL_ADC_CHANNEL_6
09274   *         @arg @ref LL_ADC_CHANNEL_7
09275   *         @arg @ref LL_ADC_CHANNEL_8
09276   *         @arg @ref LL_ADC_CHANNEL_9
09277   *         @arg @ref LL_ADC_CHANNEL_10
09278   *         @arg @ref LL_ADC_CHANNEL_11
09279   *         @arg @ref LL_ADC_CHANNEL_12
09280   *         @arg @ref LL_ADC_CHANNEL_13
09281   *         @arg @ref LL_ADC_CHANNEL_14
09282   *         @arg @ref LL_ADC_CHANNEL_15
09283   *         @arg @ref LL_ADC_CHANNEL_16
09284   *         @arg @ref LL_ADC_CHANNEL_17
09285   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
09286   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
09287   *
09288   *         (1) On STM32F37x, parameter available only on ADC instance: ADC1.
09289   * @retval None
09290   */
09291 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
09292 {
09293   /* Set bits with content of parameter "Channel" with bits position          */
09294   /* in register and register position depending on parameter "Rank".         */
09295   /* Parameters "Rank" and "Channel" are used with masks because containing   */
09296   /* other bits reserved for other purpose.                                   */
09297   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
09298
09299   MODIFY_REG(*preg,
09300              ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
09301              (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
09302 }
09303
09304 /**
09305   * @brief  Get ADC group regular sequence: channel on the selected
09306   *         scan sequence rank.
09307   * @note   On this STM32 serie, ADC group regular sequencer is
09308   *         fully configurable: sequencer length and each rank
09309   *         affectation to a channel are configurable.
09310   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
09311   * @note   Depending on devices and packages, some channels may not be available.
09312   *         Refer to device datasheet for channels availability.
09313   * @note   Usage of the returned channel number:
09314   *         - To reinject this channel into another function LL_ADC_xxx:
09315   *           the returned channel number is only partly formatted on definition
09316   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
09317   *           with parts of literals LL_ADC_CHANNEL_x or using
09318   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
09319   *           Then the selected literal LL_ADC_CHANNEL_x can be used
09320   *           as parameter for another function.
09321   *         - To get the channel number in decimal format:
09322   *           process the returned value with the helper macro
09323   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
09324   * @rmtoll SQR3     SQ1            LL_ADC_REG_GetSequencerRanks\n
09325   *         SQR3     SQ2            LL_ADC_REG_GetSequencerRanks\n
09326   *         SQR3     SQ3            LL_ADC_REG_GetSequencerRanks\n
09327   *         SQR3     SQ4            LL_ADC_REG_GetSequencerRanks\n
09328   *         SQR3     SQ5            LL_ADC_REG_GetSequencerRanks\n
09329   *         SQR3     SQ6            LL_ADC_REG_GetSequencerRanks\n
09330   *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n
09331   *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n
09332   *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n
09333   *         SQR2     SQ10           LL_ADC_REG_GetSequencerRanks\n
09334   *         SQR2     SQ11           LL_ADC_REG_GetSequencerRanks\n
09335   *         SQR2     SQ12           LL_ADC_REG_GetSequencerRanks\n
09336   *         SQR1     SQ13           LL_ADC_REG_GetSequencerRanks\n
09337   *         SQR1     SQ14           LL_ADC_REG_GetSequencerRanks\n
09338   *         SQR1     SQ15           LL_ADC_REG_GetSequencerRanks\n
09339   *         SQR1     SQ16           LL_ADC_REG_GetSequencerRanks
09340   * @param  ADCx ADC instance
09341   * @param  Rank This parameter can be one of the following values:
09342   *         @arg @ref LL_ADC_REG_RANK_1
09343   *         @arg @ref LL_ADC_REG_RANK_2
09344   *         @arg @ref LL_ADC_REG_RANK_3
09345   *         @arg @ref LL_ADC_REG_RANK_4
09346   *         @arg @ref LL_ADC_REG_RANK_5
09347   *         @arg @ref LL_ADC_REG_RANK_6
09348   *         @arg @ref LL_ADC_REG_RANK_7
09349   *         @arg @ref LL_ADC_REG_RANK_8
09350   *         @arg @ref LL_ADC_REG_RANK_9
09351   *         @arg @ref LL_ADC_REG_RANK_10
09352   *         @arg @ref LL_ADC_REG_RANK_11
09353   *         @arg @ref LL_ADC_REG_RANK_12
09354   *         @arg @ref LL_ADC_REG_RANK_13
09355   *         @arg @ref LL_ADC_REG_RANK_14
09356   *         @arg @ref LL_ADC_REG_RANK_15
09357   *         @arg @ref LL_ADC_REG_RANK_16
09358   * @retval Returned value can be one of the following values:
09359   *         @arg @ref LL_ADC_CHANNEL_0
09360   *         @arg @ref LL_ADC_CHANNEL_1
09361   *         @arg @ref LL_ADC_CHANNEL_2
09362   *         @arg @ref LL_ADC_CHANNEL_3
09363   *         @arg @ref LL_ADC_CHANNEL_4
09364   *         @arg @ref LL_ADC_CHANNEL_5
09365   *         @arg @ref LL_ADC_CHANNEL_6
09366   *         @arg @ref LL_ADC_CHANNEL_7
09367   *         @arg @ref LL_ADC_CHANNEL_8
09368   *         @arg @ref LL_ADC_CHANNEL_9
09369   *         @arg @ref LL_ADC_CHANNEL_10
09370   *         @arg @ref LL_ADC_CHANNEL_11
09371   *         @arg @ref LL_ADC_CHANNEL_12
09372   *         @arg @ref LL_ADC_CHANNEL_13
09373   *         @arg @ref LL_ADC_CHANNEL_14
09374   *         @arg @ref LL_ADC_CHANNEL_15
09375   *         @arg @ref LL_ADC_CHANNEL_16
09376   *         @arg @ref LL_ADC_CHANNEL_17
09377   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
09378   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
09379   *
09380   *         (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
09381   *         (1) For ADC channel read back from ADC register,
09382   *             comparison with internal channel parameter to be done
09383   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
09384   */
09385 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
09386 {
09387   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
09388
09389   return (uint32_t) (READ_BIT(*preg,
09390                               ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
09391                      >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
09392                     );
09393 }
09394
09395 /**
09396   * @brief  Set ADC continuous conversion mode on ADC group regular.
09397   * @note   Description of ADC continuous conversion mode:
09398   *         - single mode: one conversion per trigger
09399   *         - continuous mode: after the first trigger, following
09400   *           conversions launched successively automatically.
09401   * @note   It is not possible to enable both ADC group regular
09402   *         continuous mode and sequencer discontinuous mode.
09403   * @rmtoll CR2      CONT           LL_ADC_REG_SetContinuousMode
09404   * @param  ADCx ADC instance
09405   * @param  Continuous This parameter can be one of the following values:
09406   *         @arg @ref LL_ADC_REG_CONV_SINGLE
09407   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
09408   * @retval None
09409   */
09410 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
09411 {
09412   MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
09413 }
09414
09415 /**
09416   * @brief  Get ADC continuous conversion mode on ADC group regular.
09417   * @note   Description of ADC continuous conversion mode:
09418   *         - single mode: one conversion per trigger
09419   *         - continuous mode: after the first trigger, following
09420   *           conversions launched successively automatically.
09421   * @rmtoll CR2      CONT           LL_ADC_REG_GetContinuousMode
09422   * @param  ADCx ADC instance
09423   * @retval Returned value can be one of the following values:
09424   *         @arg @ref LL_ADC_REG_CONV_SINGLE
09425   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
09426   */
09427 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
09428 {
09429   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
09430 }
09431
09432 /**
09433   * @brief  Set ADC group regular conversion data transfer: no transfer or
09434   *         transfer by DMA, and DMA requests mode.
09435   * @note   If transfer by DMA selected, specifies the DMA requests
09436   *         mode:
09437   *         - Limited mode (One shot mode): DMA transfer requests are stopped
09438   *           when number of DMA data transfers (number of
09439   *           ADC conversions) is reached.
09440   *           This ADC mode is intended to be used with DMA mode non-circular.
09441   *         - Unlimited mode: DMA transfer requests are unlimited,
09442   *           whatever number of DMA data transfers (number of
09443   *           ADC conversions).
09444   *           This ADC mode is intended to be used with DMA mode circular.
09445   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
09446   *         mode non-circular:
09447   *         when DMA transfers size will be reached, DMA will stop transfers of
09448   *         ADC conversions data ADC will raise an overrun error
09449   *        (overrun flag and interruption if enabled).
09450   * @note   To configure DMA source address (peripheral address),
09451   *         use function @ref LL_ADC_DMA_GetRegAddr().
09452   * @rmtoll CR2      DMA            LL_ADC_REG_SetDMATransfer
09453   * @param  ADCx ADC instance
09454   * @param  DMATransfer This parameter can be one of the following values:
09455   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
09456   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
09457   * @retval None
09458   */
09459 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
09460 {
09461   MODIFY_REG(ADCx->CR2, ADC_CR2_DMA, DMATransfer);
09462 }
09463
09464 /**
09465   * @brief  Get ADC group regular conversion data transfer: no transfer or
09466   *         transfer by DMA, and DMA requests mode.
09467   * @note   If transfer by DMA selected, specifies the DMA requests
09468   *         mode:
09469   *         - Limited mode (One shot mode): DMA transfer requests are stopped
09470   *           when number of DMA data transfers (number of
09471   *           ADC conversions) is reached.
09472   *           This ADC mode is intended to be used with DMA mode non-circular.
09473   *         - Unlimited mode: DMA transfer requests are unlimited,
09474   *           whatever number of DMA data transfers (number of
09475   *           ADC conversions).
09476   *           This ADC mode is intended to be used with DMA mode circular.
09477   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
09478   *         mode non-circular:
09479   *         when DMA transfers size will be reached, DMA will stop transfers of
09480   *         ADC conversions data ADC will raise an overrun error
09481   *         (overrun flag and interruption if enabled).
09482   * @note   To configure DMA source address (peripheral address),
09483   *         use function @ref LL_ADC_DMA_GetRegAddr().
09484   * @rmtoll CR2      DMA            LL_ADC_REG_GetDMATransfer
09485   * @param  ADCx ADC instance
09486   * @retval Returned value can be one of the following values:
09487   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
09488   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
09489   */
09490 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
09491 {
09492   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA));
09493 }
09494
09495 /**
09496   * @}
09497   */
09498
09499 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
09500   * @{
09501   */
09502
09503 /**
09504   * @brief  Set ADC group injected conversion trigger source:
09505   *         internal (SW start) or external from timer or external interrupt.
09506   * @note   On this STM32 serie, external trigger is set with trigger polarity:
09507   *         rising edge (only trigger polarity available on this STM32 serie).
09508   * @note   Availability of parameters of trigger sources from timer
09509   *         depends on timers availability on the selected device.
09510   * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_SetTriggerSource
09511   * @param  ADCx ADC instance
09512   * @param  TriggerSource This parameter can be one of the following values:
09513   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
09514   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
09515   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
09516   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
09517   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
09518   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH1
09519   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH2
09520   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
09521   * @retval None
09522   */
09523 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
09524 {
09525 /* Note: On this STM32 serie, ADC group injected external trigger edge        */
09526 /*       is used to perform a ADC conversion start.                           */
09527 /*       This function does not set external trigger edge.                    */
09528 /*       This feature is set using function                                   */
09529 /*       @ref LL_ADC_INJ_StartConversionExtTrig().                            */
09530   MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
09531 }
09532
09533 /**
09534   * @brief  Get ADC group injected conversion trigger source:
09535   *         internal (SW start) or external from timer or external interrupt.
09536   * @note   To determine whether group injected trigger source is
09537   *         internal (SW start) or external, without detail
09538   *         of which peripheral is selected as external trigger,
09539   *         (equivalent to
09540   *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
09541   *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
09542   * @note   Availability of parameters of trigger sources from timer
09543   *         depends on timers availability on the selected device.
09544   * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_GetTriggerSource
09545   * @param  ADCx ADC instance
09546   * @retval Returned value can be one of the following values:
09547   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
09548   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
09549   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
09550   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
09551   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
09552   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH1
09553   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH2
09554   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
09555   */
09556 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
09557 {
09558   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL));
09559 }
09560
09561 /**
09562   * @brief  Get ADC group injected conversion trigger source internal (SW start)
09563             or external
09564   * @note   In case of group injected trigger source set to external trigger,
09565   *         to determine which peripheral is selected as external trigger,
09566   *         use function @ref LL_ADC_INJ_GetTriggerSource.
09567   * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_IsTriggerSourceSWStart
09568   * @param  ADCx ADC instance
09569   * @retval Value "0" trigger source external trigger
09570   *         Value "1" trigger source SW start.
09571   */
09572 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
09573 {
09574   return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL) == LL_ADC_INJ_TRIG_SOFTWARE);
09575 }
09576
09577 /**
09578   * @brief  Set ADC group injected sequencer length and scan direction.
09579   * @note   This function performs configuration of:
09580   *         - Sequence length: Number of ranks in the scan sequence.
09581   *         - Sequence direction: Unless specified in parameters, sequencer
09582   *           scan direction is forward (from rank 1 to rank n).
09583   * @note   On this STM32 serie, group injected sequencer configuration
09584   *         is conditioned to ADC instance sequencer mode.
09585   *         If ADC instance sequencer mode is disabled, sequencers of
09586   *         all groups (group regular, group injected) can be configured
09587   *         but their execution is disabled (limited to rank 1).
09588   *         Refer to function @ref LL_ADC_SetSequencersScanMode().
09589   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
09590   *         ADC conversion on only 1 channel.
09591   * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength
09592   * @param  ADCx ADC instance
09593   * @param  SequencerNbRanks This parameter can be one of the following values:
09594   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
09595   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
09596   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
09597   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
09598   * @retval None
09599   */
09600 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
09601 {
09602   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
09603 }
09604
09605 /**
09606   * @brief  Get ADC group injected sequencer length and scan direction.
09607   * @note   This function retrieves:
09608   *         - Sequence length: Number of ranks in the scan sequence.
09609   *         - Sequence direction: Unless specified in parameters, sequencer
09610   *           scan direction is forward (from rank 1 to rank n).
09611   * @note   On this STM32 serie, group injected sequencer configuration
09612   *         is conditioned to ADC instance sequencer mode.
09613   *         If ADC instance sequencer mode is disabled, sequencers of
09614   *         all groups (group regular, group injected) can be configured
09615   *         but their execution is disabled (limited to rank 1).
09616   *         Refer to function @ref LL_ADC_SetSequencersScanMode().
09617   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
09618   *         ADC conversion on only 1 channel.
09619   * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength
09620   * @param  ADCx ADC instance
09621   * @retval Returned value can be one of the following values:
09622   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
09623   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
09624   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
09625   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
09626   */
09627 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
09628 {
09629   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
09630 }
09631
09632 /**
09633   * @brief  Set ADC group injected sequencer discontinuous mode:
09634   *         sequence subdivided and scan conversions interrupted every selected
09635   *         number of ranks.
09636   * @note   It is not possible to enable both ADC group injected
09637   *         auto-injected mode and sequencer discontinuous mode.
09638   * @rmtoll CR1      DISCEN         LL_ADC_INJ_SetSequencerDiscont
09639   * @param  ADCx ADC instance
09640   * @param  SeqDiscont This parameter can be one of the following values:
09641   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
09642   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
09643   * @retval None
09644   */
09645 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
09646 {
09647   MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
09648 }
09649
09650 /**
09651   * @brief  Get ADC group injected sequencer discontinuous mode:
09652   *         sequence subdivided and scan conversions interrupted every selected
09653   *         number of ranks.
09654   * @rmtoll CR1      DISCEN         LL_ADC_REG_GetSequencerDiscont
09655   * @param  ADCx ADC instance
09656   * @retval Returned value can be one of the following values:
09657   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
09658   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
09659   */
09660 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
09661 {
09662   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
09663 }
09664
09665 /**
09666   * @brief  Set ADC group injected sequence: channel on the selected
09667   *         sequence rank.
09668   * @note   Depending on devices and packages, some channels may not be available.
09669   *         Refer to device datasheet for channels availability.
09670   * @note   On this STM32 serie, to measure internal channels (VrefInt,
09671   *         TempSensor, ...), measurement paths to internal channels must be
09672   *         enabled separately.
09673   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
09674   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
09675   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
09676   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
09677   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
09678   * @param  ADCx ADC instance
09679   * @param  Rank This parameter can be one of the following values:
09680   *         @arg @ref LL_ADC_INJ_RANK_1
09681   *         @arg @ref LL_ADC_INJ_RANK_2
09682   *         @arg @ref LL_ADC_INJ_RANK_3
09683   *         @arg @ref LL_ADC_INJ_RANK_4
09684   * @param  Channel This parameter can be one of the following values:
09685   *         @arg @ref LL_ADC_CHANNEL_0
09686   *         @arg @ref LL_ADC_CHANNEL_1
09687   *         @arg @ref LL_ADC_CHANNEL_2
09688   *         @arg @ref LL_ADC_CHANNEL_3
09689   *         @arg @ref LL_ADC_CHANNEL_4
09690   *         @arg @ref LL_ADC_CHANNEL_5
09691   *         @arg @ref LL_ADC_CHANNEL_6
09692   *         @arg @ref LL_ADC_CHANNEL_7
09693   *         @arg @ref LL_ADC_CHANNEL_8
09694   *         @arg @ref LL_ADC_CHANNEL_9
09695   *         @arg @ref LL_ADC_CHANNEL_10
09696   *         @arg @ref LL_ADC_CHANNEL_11
09697   *         @arg @ref LL_ADC_CHANNEL_12
09698   *         @arg @ref LL_ADC_CHANNEL_13
09699   *         @arg @ref LL_ADC_CHANNEL_14
09700   *         @arg @ref LL_ADC_CHANNEL_15
09701   *         @arg @ref LL_ADC_CHANNEL_16
09702   *         @arg @ref LL_ADC_CHANNEL_17
09703   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
09704   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
09705   *
09706   *         (1) On STM32F37x, parameter available only on ADC instance: ADC1.
09707   * @retval None
09708   */
09709 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
09710 {
09711   /* Set bits with content of parameter "Channel" with bits position          */
09712   /* in register depending on parameter "Rank".                               */
09713   /* Parameters "Rank" and "Channel" are used with masks because containing   */
09714   /* other bits reserved for other purpose.                                   */
09715   MODIFY_REG(ADCx->JSQR,
09716              ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
09717              (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
09718 }
09719
09720 /**
09721   * @brief  Get ADC group injected sequence: channel on the selected
09722   *         sequence rank.
09723   * @note   Depending on devices and packages, some channels may not be available.
09724   *         Refer to device datasheet for channels availability.
09725   * @note   Usage of the returned channel number:
09726   *         - To reinject this channel into another function LL_ADC_xxx:
09727   *           the returned channel number is only partly formatted on definition
09728   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
09729   *           with parts of literals LL_ADC_CHANNEL_x or using
09730   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
09731   *           Then the selected literal LL_ADC_CHANNEL_x can be used
09732   *           as parameter for another function.
09733   *         - To get the channel number in decimal format:
09734   *           process the returned value with the helper macro
09735   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
09736   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
09737   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
09738   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
09739   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
09740   * @param  ADCx ADC instance
09741   * @param  Rank This parameter can be one of the following values:
09742   *         @arg @ref LL_ADC_INJ_RANK_1
09743   *         @arg @ref LL_ADC_INJ_RANK_2
09744   *         @arg @ref LL_ADC_INJ_RANK_3
09745   *         @arg @ref LL_ADC_INJ_RANK_4
09746   * @retval Returned value can be one of the following values:
09747   *         @arg @ref LL_ADC_CHANNEL_0
09748   *         @arg @ref LL_ADC_CHANNEL_1
09749   *         @arg @ref LL_ADC_CHANNEL_2
09750   *         @arg @ref LL_ADC_CHANNEL_3
09751   *         @arg @ref LL_ADC_CHANNEL_4
09752   *         @arg @ref LL_ADC_CHANNEL_5
09753   *         @arg @ref LL_ADC_CHANNEL_6
09754   *         @arg @ref LL_ADC_CHANNEL_7
09755   *         @arg @ref LL_ADC_CHANNEL_8
09756   *         @arg @ref LL_ADC_CHANNEL_9
09757   *         @arg @ref LL_ADC_CHANNEL_10
09758   *         @arg @ref LL_ADC_CHANNEL_11
09759   *         @arg @ref LL_ADC_CHANNEL_12
09760   *         @arg @ref LL_ADC_CHANNEL_13
09761   *         @arg @ref LL_ADC_CHANNEL_14
09762   *         @arg @ref LL_ADC_CHANNEL_15
09763   *         @arg @ref LL_ADC_CHANNEL_16
09764   *         @arg @ref LL_ADC_CHANNEL_17
09765   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
09766   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
09767   *
09768   *         (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
09769   *         (1) For ADC channel read back from ADC register,
09770   *             comparison with internal channel parameter to be done
09771   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
09772   */
09773 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
09774 {
09775   return (uint32_t)(READ_BIT(ADCx->JSQR,
09776                              ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
09777                     >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)
09778                    );
09779 }
09780
09781 /**
09782   * @brief  Set ADC group injected conversion trigger:
09783   *         independent or from ADC group regular.
09784   * @note   This mode can be used to extend number of data registers
09785   *         updated after one ADC conversion trigger and with data
09786   *         permanently kept (not erased by successive conversions of scan of
09787   *         ADC sequencer ranks), up to 5 data registers:
09788   *         1 data register on ADC group regular, 4 data registers
09789   *         on ADC group injected.
09790   * @note   If ADC group injected injected trigger source is set to an
09791   *         external trigger, this feature must be must be set to
09792   *         independent trigger.
09793   *         ADC group injected automatic trigger is compliant only with
09794   *         group injected trigger source set to SW start, without any
09795   *         further action on  ADC group injected conversion start or stop:
09796   *         in this case, ADC group injected is controlled only
09797   *         from ADC group regular.
09798   * @note   It is not possible to enable both ADC group injected
09799   *         auto-injected mode and sequencer discontinuous mode.
09800   * @rmtoll CR1      JAUTO          LL_ADC_INJ_SetTrigAuto
09801   * @param  ADCx ADC instance
09802   * @param  TrigAuto This parameter can be one of the following values:
09803   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
09804   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
09805   * @retval None
09806   */
09807 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
09808 {
09809   MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
09810 }
09811
09812 /**
09813   * @brief  Get ADC group injected conversion trigger:
09814   *         independent or from ADC group regular.
09815   * @rmtoll CR1      JAUTO          LL_ADC_INJ_GetTrigAuto
09816   * @param  ADCx ADC instance
09817   * @retval Returned value can be one of the following values:
09818   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
09819   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
09820   */
09821 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
09822 {
09823   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
09824 }
09825
09826 /**
09827   * @brief  Set ADC group injected offset.
09828   * @note   It sets:
09829   *         - ADC group injected rank to which the offset programmed
09830   *           will be applied
09831   *         - Offset level (offset to be subtracted from the raw
09832   *           converted data).
09833   *         Caution: Offset format is dependent to ADC resolution:
09834   *         offset has to be left-aligned on bit 11, the LSB (right bits)
09835   *         are set to 0.
09836   * @note   Offset cannot be enabled or disabled.
09837   *         To emulate offset disabled, set an offset value equal to 0.
09838   * @rmtoll JOFR1    JOFFSET1       LL_ADC_INJ_SetOffset\n
09839   *         JOFR2    JOFFSET2       LL_ADC_INJ_SetOffset\n
09840   *         JOFR3    JOFFSET3       LL_ADC_INJ_SetOffset\n
09841   *         JOFR4    JOFFSET4       LL_ADC_INJ_SetOffset
09842   * @param  ADCx ADC instance
09843   * @param  Rank This parameter can be one of the following values:
09844   *         @arg @ref LL_ADC_INJ_RANK_1
09845   *         @arg @ref LL_ADC_INJ_RANK_2
09846   *         @arg @ref LL_ADC_INJ_RANK_3
09847   *         @arg @ref LL_ADC_INJ_RANK_4
09848   * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
09849   * @retval None
09850   */
09851 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
09852 {
09853   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
09854
09855   MODIFY_REG(*preg,
09856              ADC_JOFR1_JOFFSET1,
09857              OffsetLevel);
09858 }
09859
09860 /**
09861   * @brief  Get ADC group injected offset.
09862   * @note   It gives offset level (offset to be subtracted from the raw converted data).
09863   *         Caution: Offset format is dependent to ADC resolution:
09864   *         offset has to be left-aligned on bit 11, the LSB (right bits)
09865   *         are set to 0.
09866   * @rmtoll JOFR1    JOFFSET1       LL_ADC_INJ_GetOffset\n
09867   *         JOFR2    JOFFSET2       LL_ADC_INJ_GetOffset\n
09868   *         JOFR3    JOFFSET3       LL_ADC_INJ_GetOffset\n
09869   *         JOFR4    JOFFSET4       LL_ADC_INJ_GetOffset
09870   * @param  ADCx ADC instance
09871   * @param  Rank This parameter can be one of the following values:
09872   *         @arg @ref LL_ADC_INJ_RANK_1
09873   *         @arg @ref LL_ADC_INJ_RANK_2
09874   *         @arg @ref LL_ADC_INJ_RANK_3
09875   *         @arg @ref LL_ADC_INJ_RANK_4
09876   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
09877   */
09878 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
09879 {
09880   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
09881
09882   return (uint32_t)(READ_BIT(*preg,
09883                              ADC_JOFR1_JOFFSET1)
09884                    );
09885 }
09886
09887 /**
09888   * @}
09889   */
09890
09891 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
09892   * @{
09893   */
09894
09895 /**
09896   * @brief  Set sampling time of the selected ADC channel
09897   *         Unit: ADC clock cycles.
09898   * @note   On this device, sampling time is on channel scope: independently
09899   *         of channel mapped on ADC group regular or injected.
09900   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
09901   *         converted:
09902   *         sampling time constraints must be respected (sampling time can be
09903   *         adjusted in function of ADC clock frequency and sampling time
09904   *         setting).
09905   *         Refer to device datasheet for timings values (parameters TS_vrefint,
09906   *         TS_temp, ...).
09907   * @note   Conversion time is the addition of sampling time and processing time.
09908   *         Refer to reference manual for ADC processing time of
09909   *         this STM32 serie.
09910   * @note   In case of ADC conversion of internal channel (VrefInt,
09911   *         temperature sensor, ...), a sampling time minimum value
09912   *         is required.
09913   *         Refer to device datasheet.
09914   * @rmtoll SMPR1    SMP17          LL_ADC_SetChannelSamplingTime\n
09915   *         SMPR1    SMP16          LL_ADC_SetChannelSamplingTime\n
09916   *         SMPR1    SMP15          LL_ADC_SetChannelSamplingTime\n
09917   *         SMPR1    SMP14          LL_ADC_SetChannelSamplingTime\n
09918   *         SMPR1    SMP13          LL_ADC_SetChannelSamplingTime\n
09919   *         SMPR1    SMP12          LL_ADC_SetChannelSamplingTime\n
09920   *         SMPR1    SMP11          LL_ADC_SetChannelSamplingTime\n
09921   *         SMPR1    SMP10          LL_ADC_SetChannelSamplingTime\n
09922   *         SMPR2    SMP9           LL_ADC_SetChannelSamplingTime\n
09923   *         SMPR2    SMP8           LL_ADC_SetChannelSamplingTime\n
09924   *         SMPR2    SMP7           LL_ADC_SetChannelSamplingTime\n
09925   *         SMPR2    SMP6           LL_ADC_SetChannelSamplingTime\n
09926   *         SMPR2    SMP5           LL_ADC_SetChannelSamplingTime\n
09927   *         SMPR2    SMP4           LL_ADC_SetChannelSamplingTime\n
09928   *         SMPR2    SMP3           LL_ADC_SetChannelSamplingTime\n
09929   *         SMPR2    SMP2           LL_ADC_SetChannelSamplingTime\n
09930   *         SMPR2    SMP1           LL_ADC_SetChannelSamplingTime\n
09931   *         SMPR2    SMP0           LL_ADC_SetChannelSamplingTime
09932   * @param  ADCx ADC instance
09933   * @param  Channel This parameter can be one of the following values:
09934   *         @arg @ref LL_ADC_CHANNEL_0
09935   *         @arg @ref LL_ADC_CHANNEL_1
09936   *         @arg @ref LL_ADC_CHANNEL_2
09937   *         @arg @ref LL_ADC_CHANNEL_3
09938   *         @arg @ref LL_ADC_CHANNEL_4
09939   *         @arg @ref LL_ADC_CHANNEL_5
09940   *         @arg @ref LL_ADC_CHANNEL_6
09941   *         @arg @ref LL_ADC_CHANNEL_7
09942   *         @arg @ref LL_ADC_CHANNEL_8
09943   *         @arg @ref LL_ADC_CHANNEL_9
09944   *         @arg @ref LL_ADC_CHANNEL_10
09945   *         @arg @ref LL_ADC_CHANNEL_11
09946   *         @arg @ref LL_ADC_CHANNEL_12
09947   *         @arg @ref LL_ADC_CHANNEL_13
09948   *         @arg @ref LL_ADC_CHANNEL_14
09949   *         @arg @ref LL_ADC_CHANNEL_15
09950   *         @arg @ref LL_ADC_CHANNEL_16
09951   *         @arg @ref LL_ADC_CHANNEL_17
09952   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
09953   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
09954   *
09955   *         (1) On STM32F37x, parameter available only on ADC instance: ADC1.
09956   * @param  SamplingTime This parameter can be one of the following values:
09957   *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
09958   *         @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
09959   *         @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
09960   *         @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
09961   *         @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
09962   *         @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
09963   *         @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
09964   *         @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
09965   * @retval None
09966   */
09967 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
09968 {
09969   /* Set bits with content of parameter "SamplingTime" with bits position     */
09970   /* in register and register position depending on parameter "Channel".      */
09971   /* Parameter "Channel" is used with masks because containing                */
09972   /* other bits reserved for other purpose.                                   */
09973   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
09974
09975   MODIFY_REG(*preg,
09976              ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
09977              SamplingTime   << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
09978 }
09979
09980 /**
09981   * @brief  Get sampling time of the selected ADC channel
09982   *         Unit: ADC clock cycles.
09983   * @note   On this device, sampling time is on channel scope: independently
09984   *         of channel mapped on ADC group regular or injected.
09985   * @note   Conversion time is the addition of sampling time and processing time.
09986   *         Refer to reference manual for ADC processing time of
09987   *         this STM32 serie.
09988   * @rmtoll SMPR1    SMP17          LL_ADC_GetChannelSamplingTime\n
09989   *         SMPR1    SMP16          LL_ADC_GetChannelSamplingTime\n
09990   *         SMPR1    SMP15          LL_ADC_GetChannelSamplingTime\n
09991   *         SMPR1    SMP14          LL_ADC_GetChannelSamplingTime\n
09992   *         SMPR1    SMP13          LL_ADC_GetChannelSamplingTime\n
09993   *         SMPR1    SMP12          LL_ADC_GetChannelSamplingTime\n
09994   *         SMPR1    SMP11          LL_ADC_GetChannelSamplingTime\n
09995   *         SMPR1    SMP10          LL_ADC_GetChannelSamplingTime\n
09996   *         SMPR2    SMP9           LL_ADC_GetChannelSamplingTime\n
09997   *         SMPR2    SMP8           LL_ADC_GetChannelSamplingTime\n
09998   *         SMPR2    SMP7           LL_ADC_GetChannelSamplingTime\n
09999   *         SMPR2    SMP6           LL_ADC_GetChannelSamplingTime\n
10000   *         SMPR2    SMP5           LL_ADC_GetChannelSamplingTime\n
10001   *         SMPR2    SMP4           LL_ADC_GetChannelSamplingTime\n
10002   *         SMPR2    SMP3           LL_ADC_GetChannelSamplingTime\n
10003   *         SMPR2    SMP2           LL_ADC_GetChannelSamplingTime\n
10004   *         SMPR2    SMP1           LL_ADC_GetChannelSamplingTime\n
10005   *         SMPR2    SMP0           LL_ADC_GetChannelSamplingTime
10006   * @param  ADCx ADC instance
10007   * @param  Channel This parameter can be one of the following values:
10008   *         @arg @ref LL_ADC_CHANNEL_0
10009   *         @arg @ref LL_ADC_CHANNEL_1
10010   *         @arg @ref LL_ADC_CHANNEL_2
10011   *         @arg @ref LL_ADC_CHANNEL_3
10012   *         @arg @ref LL_ADC_CHANNEL_4
10013   *         @arg @ref LL_ADC_CHANNEL_5
10014   *         @arg @ref LL_ADC_CHANNEL_6
10015   *         @arg @ref LL_ADC_CHANNEL_7
10016   *         @arg @ref LL_ADC_CHANNEL_8
10017   *         @arg @ref LL_ADC_CHANNEL_9
10018   *         @arg @ref LL_ADC_CHANNEL_10
10019   *         @arg @ref LL_ADC_CHANNEL_11
10020   *         @arg @ref LL_ADC_CHANNEL_12
10021   *         @arg @ref LL_ADC_CHANNEL_13
10022   *         @arg @ref LL_ADC_CHANNEL_14
10023   *         @arg @ref LL_ADC_CHANNEL_15
10024   *         @arg @ref LL_ADC_CHANNEL_16
10025   *         @arg @ref LL_ADC_CHANNEL_17
10026   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
10027   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
10028   *
10029   *         (1) On STM32F37x, parameter available only on ADC instance: ADC1.
10030   * @retval Returned value can be one of the following values:
10031   *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
10032   *         @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
10033   *         @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
10034   *         @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
10035   *         @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
10036   *         @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
10037   *         @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
10038   *         @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
10039   */
10040 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
10041 {
10042   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
10043
10044   return (uint32_t)(READ_BIT(*preg,
10045                              ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
10046                     >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
10047                    );
10048 }
10049
10050 /**
10051   * @}
10052   */
10053
10054 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
10055   * @{
10056   */
10057
10058 /**
10059   * @brief  Set ADC analog watchdog monitored channels:
10060   *         a single channel or all channels,
10061   *         on ADC groups regular and-or injected.
10062   * @note   Once monitored channels are selected, analog watchdog
10063   *         is enabled.
10064   * @note   In case of need to define a single channel to monitor
10065   *         with analog watchdog from sequencer channel definition,
10066   *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
10067   * @note   On this STM32 serie, there is only 1 kind of analog watchdog
10068   *         instance:
10069   *         - AWD standard (instance AWD1):
10070   *           - channels monitored: can monitor 1 channel or all channels.
10071   *           - groups monitored: ADC groups regular and-or injected.
10072   *           - resolution: resolution is not limited (corresponds to
10073   *             ADC resolution configured).
10074   * @rmtoll CR1      AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
10075   *         CR1      AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
10076   *         CR1      AWD1EN         LL_ADC_SetAnalogWDMonitChannels
10077   * @param  ADCx ADC instance
10078   * @param  AWDChannelGroup This parameter can be one of the following values:
10079   *         @arg @ref LL_ADC_AWD_DISABLE
10080   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
10081   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
10082   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
10083   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG
10084   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
10085   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
10086   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG
10087   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
10088   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
10089   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG
10090   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
10091   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
10092   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG
10093   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
10094   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
10095   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG
10096   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
10097   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
10098   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG
10099   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
10100   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
10101   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG
10102   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
10103   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
10104   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG
10105   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
10106   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
10107   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG
10108   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
10109   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
10110   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG
10111   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
10112   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
10113   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
10114   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
10115   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
10116   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
10117   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
10118   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
10119   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
10120   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
10121   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
10122   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
10123   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
10124   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
10125   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
10126   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
10127   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
10128   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
10129   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
10130   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
10131   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG
10132   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
10133   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
10134   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
10135   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
10136   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
10137   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (1)
10138   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (1)
10139   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ      (1)
10140   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (1)
10141   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (1)
10142   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   (1)
10143   *
10144   *         (1) On STM32F37x, parameter available only on ADC instance: ADC1.
10145   * @retval None
10146   */
10147 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
10148 {
10149   MODIFY_REG(ADCx->CR1,
10150              (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
10151              AWDChannelGroup);
10152 }
10153
10154 /**
10155   * @brief  Get ADC analog watchdog monitored channel.
10156   * @note   Usage of the returned channel number:
10157   *         - To reinject this channel into another function LL_ADC_xxx:
10158   *           the returned channel number is only partly formatted on definition
10159   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
10160   *           with parts of literals LL_ADC_CHANNEL_x or using
10161   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
10162   *           Then the selected literal LL_ADC_CHANNEL_x can be used
10163   *           as parameter for another function.
10164   *         - To get the channel number in decimal format:
10165   *           process the returned value with the helper macro
10166   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
10167   *           Applicable only when the analog watchdog is set to monitor
10168   *           one channel.
10169   * @note   On this STM32 serie, there is only 1 kind of analog watchdog
10170   *         instance:
10171   *         - AWD standard (instance AWD1):
10172   *           - channels monitored: can monitor 1 channel or all channels.
10173   *           - groups monitored: ADC groups regular and-or injected.
10174   *           - resolution: resolution is not limited (corresponds to
10175   *             ADC resolution configured).
10176   * @rmtoll CR1      AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
10177   *         CR1      AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
10178   *         CR1      AWD1EN         LL_ADC_GetAnalogWDMonitChannels
10179   * @param  ADCx ADC instance
10180   * @retval Returned value can be one of the following values:
10181   *         @arg @ref LL_ADC_AWD_DISABLE
10182   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
10183   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
10184   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
10185   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG
10186   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
10187   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
10188   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG
10189   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
10190   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
10191   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG
10192   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
10193   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
10194   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG
10195   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
10196   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
10197   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG
10198   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
10199   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
10200   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG
10201   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
10202   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
10203   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG
10204   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
10205   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
10206   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG
10207   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
10208   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
10209   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG
10210   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
10211   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
10212   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG
10213   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
10214   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
10215   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
10216   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
10217   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
10218   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
10219   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
10220   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
10221   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
10222   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
10223   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
10224   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
10225   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
10226   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
10227   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
10228   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
10229   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
10230   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
10231   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
10232   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
10233   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG
10234   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
10235   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
10236   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
10237   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
10238   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
10239   */
10240 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
10241 {
10242   return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
10243 }
10244
10245 /**
10246   * @brief  Set ADC analog watchdog threshold value of threshold
10247   *         high or low.
10248   * @note   On this STM32 serie, there is only 1 kind of analog watchdog
10249   *         instance:
10250   *         - AWD standard (instance AWD1):
10251   *           - channels monitored: can monitor 1 channel or all channels.
10252   *           - groups monitored: ADC groups regular and-or injected.
10253   *           - resolution: resolution is not limited (corresponds to
10254   *             ADC resolution configured).
10255   * @rmtoll HTR      HT             LL_ADC_SetAnalogWDThresholds\n
10256   *         LTR      LT             LL_ADC_SetAnalogWDThresholds
10257   * @param  ADCx ADC instance
10258   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
10259   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
10260   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
10261   * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
10262   * @retval None
10263   */
10264 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
10265 {
10266   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
10267
10268   MODIFY_REG(*preg,
10269              ADC_HTR_HT,
10270              AWDThresholdValue);
10271 }
10272
10273 /**
10274   * @brief  Get ADC analog watchdog threshold value of threshold high or
10275   *         threshold low.
10276   * @note   In case of ADC resolution different of 12 bits,
10277   *         analog watchdog thresholds data require a specific shift.
10278   *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
10279   * @rmtoll HTR      HT             LL_ADC_GetAnalogWDThresholds\n
10280   *         LTR      LT             LL_ADC_GetAnalogWDThresholds
10281   * @param  ADCx ADC instance
10282   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
10283   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
10284   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
10285   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
10286 */
10287 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
10288 {
10289   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
10290
10291   return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
10292 }
10293
10294 /**
10295   * @}
10296   */
10297
10298 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
10299   * @{
10300   */
10301
10302 /**
10303   * @brief  Enable the selected ADC instance.
10304   * @note   On this STM32 serie, after ADC enable, a delay for
10305   *         ADC internal analog stabilization is required before performing a
10306   *         ADC conversion start.
10307   *         Refer to device datasheet, parameter tSTAB.
10308   * @rmtoll CR2      ADON           LL_ADC_Enable
10309   * @param  ADCx ADC instance
10310   * @retval None
10311   */
10312 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
10313 {
10314   SET_BIT(ADCx->CR2, ADC_CR2_ADON);
10315 }
10316
10317 /**
10318   * @brief  Disable the selected ADC instance.
10319   * @rmtoll CR2      ADON           LL_ADC_Disable
10320   * @param  ADCx ADC instance
10321   * @retval None
10322   */
10323 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
10324 {
10325   CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
10326 }
10327
10328 /**
10329   * @brief  Get the selected ADC instance enable state.
10330   * @rmtoll CR2      ADON           LL_ADC_IsEnabled
10331   * @param  ADCx ADC instance
10332   * @retval 0: ADC is disabled, 1: ADC is enabled.
10333   */
10334 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
10335 {
10336   return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
10337 }
10338
10339 /**
10340   * @brief  Start ADC calibration in the mode single-ended
10341   *         or differential (for devices with differential mode available).
10342   * @note   On this STM32 serie, before starting a calibration,
10343   *         ADC must be disabled.
10344   *         A minimum number of ADC clock cycles are required
10345   *         between ADC disable state and calibration start.
10346   *         Refer to literal @ref LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES.
10347   * @note   On this STM32 serie, hardware prerequisite before starting a calibration:
10348             the ADC must have been in power-on state for at least
10349             two ADC clock cycles.
10350   * @rmtoll CR2      CAL            LL_ADC_StartCalibration
10351   * @param  ADCx ADC instance
10352   * @retval None
10353   */
10354 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
10355 {
10356   SET_BIT(ADCx->CR2, ADC_CR2_CAL);
10357 }
10358
10359 /**
10360   * @brief  Get ADC calibration state.
10361   * @rmtoll CR2      CAL            LL_ADC_IsCalibrationOnGoing
10362   * @param  ADCx ADC instance
10363   * @retval 0: calibration complete, 1: calibration in progress.
10364   */
10365 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
10366 {
10367   return (READ_BIT(ADCx->CR2, ADC_CR2_CAL) == (ADC_CR2_CAL));
10368 }
10369
10370 /**
10371   * @}
10372   */
10373
10374 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
10375   * @{
10376   */
10377
10378 /**
10379   * @brief  Start ADC group regular conversion.
10380   * @note   On this STM32 serie, this function is relevant for both
10381   *         internal trigger (SW start) and external trigger:
10382   *         - If ADC trigger has been set to software start, ADC conversion
10383   *           starts immediately.
10384   *         - If ADC trigger has been set to external trigger, ADC conversion
10385   *           will start at next trigger event (on the selected trigger edge)
10386   *           following the ADC start conversion command.
10387   * @rmtoll CR2      EXTTRIG        LL_ADC_REG_StartConversion
10388   * @param  ADCx ADC instance
10389   * @retval None
10390   */
10391 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
10392 {
10393   /* Note: Set bit ADC_CR2_SWSTART for case of trigger source set to          */
10394   /*       SW start. In case of external trigger selected, this bit           */
10395   /*       has no effect.                                                     */
10396   SET_BIT(ADCx->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
10397 }
10398
10399 /**
10400   * @brief  Stop ADC group regular conversion from external trigger.
10401   * @note   No more ADC conversion will start at next trigger event
10402   *         following the ADC stop conversion command.
10403   *         If a conversion is on-going, it will be completed.
10404   * @note   On this STM32 serie, there is no specific command
10405   *         to stop a conversion on-going or to stop ADC converting
10406   *         in continuous mode. These actions can be performed
10407   *         using function @ref LL_ADC_Disable().
10408   * @rmtoll CR2      EXTSEL         LL_ADC_REG_StopConversionExtTrig
10409   * @param  ADCx ADC instance
10410   * @retval None
10411   */
10412 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
10413 {
10414   SET_BIT(ADCx->CR2, ADC_CR2_EXTSEL);
10415 }
10416
10417 /**
10418   * @brief  Get ADC group regular conversion data, range fit for
10419   *         all ADC configurations: all ADC resolutions and
10420   *         all oversampling increased data width (for devices
10421   *         with feature oversampling).
10422   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32
10423   * @param  ADCx ADC instance
10424   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
10425   */
10426 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
10427 {
10428   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
10429 }
10430
10431 /**
10432   * @brief  Get ADC group regular conversion data, range fit for
10433   *         ADC resolution 12 bits.
10434   * @note   For devices with feature oversampling: Oversampling
10435   *         can increase data width, function for extended range
10436   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
10437   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12
10438   * @param  ADCx ADC instance
10439   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
10440   */
10441 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
10442 {
10443   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
10444 }
10445
10446 /**
10447   * @}
10448   */
10449
10450 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
10451   * @{
10452   */
10453
10454 /**
10455   * @brief  Start ADC group injected conversion.
10456   * @note   On this STM32 serie, this function is relevant for both
10457   *         internal trigger (SW start) and external trigger:
10458   *         - If ADC trigger has been set to software start, ADC conversion
10459   *           starts immediately.
10460   *         - If ADC trigger has been set to external trigger, ADC conversion
10461   *           will start at next trigger event (on the selected trigger edge)
10462   *           following the ADC start conversion command.
10463   * @rmtoll CR2      JEXTTRIG       LL_ADC_REG_StartConversion
10464   * @param  ADCx ADC instance
10465   * @retval None
10466   */
10467 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
10468 {
10469   /* Note: Set bit ADC_CR2_JSWSTART for case of trigger source set to         */
10470   /*       SW start. In case of external trigger selected, this bit           */
10471   /*       has no effect.                                                     */
10472   SET_BIT(ADCx->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
10473 }
10474
10475 /**
10476   * @brief  Stop ADC group injected conversion from external trigger.
10477   * @note   No more ADC conversion will start at next trigger event
10478   *         following the ADC stop conversion command.
10479   *         If a conversion is on-going, it will be completed.
10480   * @note   On this STM32 serie, there is no specific command
10481   *         to stop a conversion on-going or to stop ADC converting
10482   *         in continuous mode. These actions can be performed
10483   *         using function @ref LL_ADC_Disable().
10484   * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_StopConversionExtTrig
10485   * @param  ADCx ADC instance
10486   * @retval None
10487   */
10488 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
10489 {
10490   SET_BIT(ADCx->CR2, ADC_CR2_JEXTSEL);
10491 }
10492
10493 /**
10494   * @brief  Get ADC group regular conversion data, range fit for
10495   *         all ADC configurations: all ADC resolutions and
10496   *         all oversampling increased data width (for devices
10497   *         with feature oversampling).
10498   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n
10499   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n
10500   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n
10501   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32
10502   * @param  ADCx ADC instance
10503   * @param  Rank This parameter can be one of the following values:
10504   *         @arg @ref LL_ADC_INJ_RANK_1
10505   *         @arg @ref LL_ADC_INJ_RANK_2
10506   *         @arg @ref LL_ADC_INJ_RANK_3
10507   *         @arg @ref LL_ADC_INJ_RANK_4
10508   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
10509   */
10510 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
10511 {
10512   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
10513
10514   return (uint32_t)(READ_BIT(*preg,
10515                              ADC_JDR1_JDATA)
10516                    );
10517 }
10518
10519 /**
10520   * @brief  Get ADC group injected conversion data, range fit for
10521   *         ADC resolution 12 bits.
10522   * @note   For devices with feature oversampling: Oversampling
10523   *         can increase data width, function for extended range
10524   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
10525   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n
10526   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n
10527   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n
10528   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12
10529   * @param  ADCx ADC instance
10530   * @param  Rank This parameter can be one of the following values:
10531   *         @arg @ref LL_ADC_INJ_RANK_1
10532   *         @arg @ref LL_ADC_INJ_RANK_2
10533   *         @arg @ref LL_ADC_INJ_RANK_3
10534   *         @arg @ref LL_ADC_INJ_RANK_4
10535   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
10536   */
10537 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
10538 {
10539   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
10540
10541   return (uint16_t)(READ_BIT(*preg,
10542                              ADC_JDR1_JDATA)
10543                    );
10544 }
10545
10546 /**
10547   * @}
10548   */
10549
10550 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
10551   * @{
10552   */
10553
10554 /**
10555   * @brief  Get flag ADC group regular end of sequence conversions.
10556   * @rmtoll SR       EOC            LL_ADC_IsActiveFlag_EOS
10557   * @param  ADCx ADC instance
10558   * @retval State of bit (1 or 0).
10559   */
10560 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
10561 {
10562   /* Note: on this STM32 serie, there is no flag ADC group regular            */
10563   /*       end of unitary conversion.                                         */
10564   /*       Flag noted as "EOC" is corresponding to flag "EOS"                 */
10565   /*       in other STM32 families).                                          */
10566   return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
10567 }
10568
10569
10570 /**
10571   * @brief  Get flag ADC group injected end of sequence conversions.
10572   * @rmtoll SR       JEOC           LL_ADC_IsActiveFlag_JEOS
10573   * @param  ADCx ADC instance
10574   * @retval State of bit (1 or 0).
10575   */
10576 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
10577 {
10578   /* Note: on this STM32 serie, there is no flag ADC group injected           */
10579   /*       end of unitary conversion.                                         */
10580   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
10581   /*       in other STM32 families).                                          */
10582   return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
10583 }
10584
10585 /**
10586   * @brief  Get flag ADC analog watchdog 1 flag
10587   * @rmtoll SR       AWD            LL_ADC_IsActiveFlag_AWD1
10588   * @param  ADCx ADC instance
10589   * @retval State of bit (1 or 0).
10590   */
10591 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
10592 {
10593   return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
10594 }
10595
10596 /**
10597   * @brief  Clear flag ADC group regular end of sequence conversions.
10598   * @rmtoll SR       EOC            LL_ADC_ClearFlag_EOS
10599   * @param  ADCx ADC instance
10600   * @retval None
10601   */
10602 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
10603 {
10604   /* Note: on this STM32 serie, there is no flag ADC group regular            */
10605   /*       end of unitary conversion.                                         */
10606   /*       Flag noted as "EOC" is corresponding to flag "EOS"                 */
10607   /*       in other STM32 families).                                          */
10608   WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOS);
10609 }
10610
10611
10612 /**
10613   * @brief  Clear flag ADC group injected end of sequence conversions.
10614   * @rmtoll SR       JEOC           LL_ADC_ClearFlag_JEOS
10615   * @param  ADCx ADC instance
10616   * @retval None
10617   */
10618 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
10619 {
10620   /* Note: on this STM32 serie, there is no flag ADC group injected           */
10621   /*       end of unitary conversion.                                         */
10622   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
10623   /*       in other STM32 families).                                          */
10624   WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
10625 }
10626
10627 /**
10628   * @brief  Clear flag ADC analog watchdog 1.
10629   * @rmtoll SR       AWD            LL_ADC_ClearFlag_AWD1
10630   * @param  ADCx ADC instance
10631   * @retval None
10632   */
10633 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
10634 {
10635   WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
10636 }
10637
10638 /**
10639   * @}
10640   */
10641
10642 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
10643   * @{
10644   */
10645
10646 /**
10647   * @brief  Enable interruption ADC group regular end of sequence conversions.
10648   * @rmtoll CR1      EOCIE          LL_ADC_EnableIT_EOS
10649   * @param  ADCx ADC instance
10650   * @retval None
10651   */
10652 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
10653 {
10654   /* Note: on this STM32 serie, there is no flag ADC group regular            */
10655   /*       end of unitary conversion.                                         */
10656   /*       Flag noted as "EOC" is corresponding to flag "EOS"                 */
10657   /*       in other STM32 families).                                          */
10658   SET_BIT(ADCx->CR1, ADC_CR1_EOCIE);
10659 }
10660
10661
10662 /**
10663   * @brief  Enable interruption ADC group injected end of sequence conversions.
10664   * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS
10665   * @param  ADCx ADC instance
10666   * @retval None
10667   */
10668 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
10669 {
10670   /* Note: on this STM32 serie, there is no flag ADC group injected           */
10671   /*       end of unitary conversion.                                         */
10672   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
10673   /*       in other STM32 families).                                          */
10674   SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
10675 }
10676
10677 /**
10678   * @brief  Enable interruption ADC analog watchdog 1.
10679   * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1
10680   * @param  ADCx ADC instance
10681   * @retval None
10682   */
10683 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
10684 {
10685   SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
10686 }
10687
10688 /**
10689   * @brief  Disable interruption ADC group regular end of sequence conversions.
10690   * @rmtoll CR1      EOCIE          LL_ADC_DisableIT_EOS
10691   * @param  ADCx ADC instance
10692   * @retval None
10693   */
10694 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
10695 {
10696   /* Note: on this STM32 serie, there is no flag ADC group regular            */
10697   /*       end of unitary conversion.                                         */
10698   /*       Flag noted as "EOC" is corresponding to flag "EOS"                 */
10699   /*       in other STM32 families).                                          */
10700   CLEAR_BIT(ADCx->CR1, ADC_CR1_EOCIE);
10701 }
10702
10703
10704 /**
10705   * @brief  Disable interruption ADC group injected end of sequence conversions.
10706   * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS
10707   * @param  ADCx ADC instance
10708   * @retval None
10709   */
10710 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
10711 {
10712   /* Note: on this STM32 serie, there is no flag ADC group injected           */
10713   /*       end of unitary conversion.                                         */
10714   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
10715   /*       in other STM32 families).                                          */
10716   CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
10717 }
10718
10719 /**
10720   * @brief  Disable interruption ADC analog watchdog 1.
10721   * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1
10722   * @param  ADCx ADC instance
10723   * @retval None
10724   */
10725 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
10726 {
10727   CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
10728 }
10729
10730 /**
10731   * @brief  Get state of interruption ADC group regular end of sequence conversions
10732   *         (0: interrupt disabled, 1: interrupt enabled).
10733   * @rmtoll CR1      EOCIE          LL_ADC_IsEnabledIT_EOS
10734   * @param  ADCx ADC instance
10735   * @retval State of bit (1 or 0).
10736   */
10737 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
10738 {
10739   /* Note: on this STM32 serie, there is no flag ADC group regular            */
10740   /*       end of unitary conversion.                                         */
10741   /*       Flag noted as "EOC" is corresponding to flag "EOS"                 */
10742   /*       in other STM32 families).                                          */
10743   return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
10744 }
10745
10746
10747 /**
10748   * @brief  Get state of interruption ADC group injected end of sequence conversions
10749   *         (0: interrupt disabled, 1: interrupt enabled).
10750   * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS
10751   * @param  ADCx ADC instance
10752   * @retval State of bit (1 or 0).
10753   */
10754 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
10755 {
10756   /* Note: on this STM32 serie, there is no flag ADC group injected           */
10757   /*       end of unitary conversion.                                         */
10758   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
10759   /*       in other STM32 families).                                          */
10760   return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
10761 }
10762
10763 /**
10764   * @brief  Get state of interruption ADC analog watchdog 1
10765   *         (0: interrupt disabled, 1: interrupt enabled).
10766   * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1
10767   * @param  ADCx ADC instance
10768   * @retval State of bit (1 or 0).
10769   */
10770 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
10771 {
10772   return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
10773 }
10774
10775 /**
10776   * @}
10777   */
10778
10779 #if defined(USE_FULL_LL_DRIVER)
10780 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
10781   * @{
10782   */
10783
10784 /* Initialization of some features of ADC common parameters and multimode */
10785 /* Note: On STM32F37x ADC, there is no ADC common initialization              */
10786 /*       function.                                                            */
10787 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
10788
10789 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
10790 /* (availability of ADC group injected depends on STM32 families) */
10791 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
10792
10793 /* Initialization of some features of ADC instance */
10794 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
10795 void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
10796
10797 /* Initialization of some features of ADC instance and ADC group regular */
10798 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
10799 void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
10800
10801 /* Initialization of some features of ADC instance and ADC group injected */
10802 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
10803 void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
10804
10805 /**
10806   * @}
10807   */
10808 #endif /* USE_FULL_LL_DRIVER */
10809
10810 /**
10811   * @}
10812   */
10813
10814 /**
10815   * @}
10816   */
10817
10818 #endif /* ADC1 */
10819
10820
10821 #endif /* STM32F373xC || STM32F378xx */
10822
10823 /**
10824   * @}
10825   */
10826
10827 #ifdef __cplusplus
10828 }
10829 #endif
10830
10831 #endif /* __STM32F3xx_LL_ADC_H */
10832
10833 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_bus.h Source File

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stm32f3xx_ll_bus.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_bus.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of BUS LL module.
00006
00007   @verbatim
00008                       ##### RCC Limitations #####
00009   ==============================================================================
00010     [..]
00011       A delay between an RCC peripheral clock enable and the effective peripheral
00012       enabling should be taken into account in order to manage the peripheral read/write
00013       from/to registers.
00014       (+) This delay depends on the peripheral mapping.
00015         (++) AHB & APB peripherals, 1 dummy read is necessary
00016
00017     [..]
00018       Workarounds:
00019       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
00020           inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
00021
00022   @endverbatim
00023   ******************************************************************************
00024   * @attention
00025   *
00026   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00027   *
00028   * Redistribution and use in source and binary forms, with or without modification,
00029   * are permitted provided that the following conditions are met:
00030   *   1. Redistributions of source code must retain the above copyright notice,
00031   *      this list of conditions and the following disclaimer.
00032   *   2. Redistributions in binary form must reproduce the above copyright notice,
00033   *      this list of conditions and the following disclaimer in the documentation
00034   *      and/or other materials provided with the distribution.
00035   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00036   *      may be used to endorse or promote products derived from this software
00037   *      without specific prior written permission.
00038   *
00039   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00040   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00041   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00042   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00043   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00044   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00045   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00046   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00047   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00048   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00049   *
00050   ******************************************************************************
00051   */
00052
00053 /* Define to prevent recursive inclusion -------------------------------------*/
00054 #ifndef __STM32F3xx_LL_BUS_H
00055 #define __STM32F3xx_LL_BUS_H
00056
00057 #ifdef __cplusplus
00058 extern "C" {
00059 #endif
00060
00061 /* Includes ------------------------------------------------------------------*/
00062 #include "stm32f3xx.h"
00063
00064 /** @addtogroup STM32F3xx_LL_Driver
00065   * @{
00066   */
00067
00068 #if defined(RCC)
00069
00070 /** @defgroup BUS_LL BUS
00071   * @{
00072   */
00073
00074 /* Private types -------------------------------------------------------------*/
00075 /* Private variables ---------------------------------------------------------*/
00076
00077 /* Private constants ---------------------------------------------------------*/
00078
00079 /* Private macros ------------------------------------------------------------*/
00080
00081 /* Exported types ------------------------------------------------------------*/
00082 /* Exported constants --------------------------------------------------------*/
00083 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
00084   * @{
00085   */
00086
00087 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
00088   * @{
00089   */
00090 #define LL_AHB1_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
00091 #define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHBENR_DMA1EN
00092 #if defined(DMA2)
00093 #define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHBENR_DMA2EN
00094 #endif /*DMA2*/
00095 #define LL_AHB1_GRP1_PERIPH_SRAM           RCC_AHBENR_SRAMEN
00096 #define LL_AHB1_GRP1_PERIPH_FLASH          RCC_AHBENR_FLITFEN
00097 #if defined(FMC_Bank1)
00098 #define LL_AHB1_GRP1_PERIPH_FMC            RCC_AHBENR_FMCEN
00099 #endif /*FMC_Bank1*/
00100 #define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHBENR_CRCEN
00101 #if defined(GPIOH)
00102 #define LL_AHB1_GRP1_PERIPH_GPIOH          RCC_AHBENR_GPIOHEN
00103 #endif /*GPIOH*/
00104 #define LL_AHB1_GRP1_PERIPH_GPIOA          RCC_AHBENR_GPIOAEN
00105 #define LL_AHB1_GRP1_PERIPH_GPIOB          RCC_AHBENR_GPIOBEN
00106 #define LL_AHB1_GRP1_PERIPH_GPIOC          RCC_AHBENR_GPIOCEN
00107 #define LL_AHB1_GRP1_PERIPH_GPIOD          RCC_AHBENR_GPIODEN
00108 #if defined(GPIOE)
00109 #define LL_AHB1_GRP1_PERIPH_GPIOE          RCC_AHBENR_GPIOEEN
00110 #endif /*GPIOE*/
00111 #define LL_AHB1_GRP1_PERIPH_GPIOF          RCC_AHBENR_GPIOFEN
00112 #if defined(GPIOG)
00113 #define LL_AHB1_GRP1_PERIPH_GPIOG          RCC_AHBENR_GPIOGEN
00114 #endif /*GPIOH*/
00115 #define LL_AHB1_GRP1_PERIPH_TSC            RCC_AHBENR_TSCEN
00116 #if defined(RCC_AHBENR_ADC1EN)
00117 #define LL_AHB1_GRP1_PERIPH_ADC1           RCC_AHBENR_ADC1EN
00118 #endif /*RCC_AHBENR_ADC1EN*/
00119 #if defined(ADC1_2_COMMON)
00120 #define LL_AHB1_GRP1_PERIPH_ADC12          RCC_AHBENR_ADC12EN
00121 #endif /*ADC1_2_COMMON*/
00122 #if defined(ADC3_4_COMMON)
00123 #define LL_AHB1_GRP1_PERIPH_ADC34          RCC_AHBENR_ADC34EN
00124 #endif /*ADC3_4_COMMON*/
00125 /**
00126   * @}
00127   */
00128
00129 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
00130   * @{
00131   */
00132 #define LL_APB1_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
00133 #define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN
00134 #if defined(TIM3)
00135 #define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN
00136 #endif /*TIM3*/
00137 #if defined(TIM4)
00138 #define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR_TIM4EN
00139 #endif /*TIM4*/
00140 #if defined(TIM5)
00141 #define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR_TIM5EN
00142 #endif /*TIM5*/
00143 #define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN
00144 #if defined(TIM7)
00145 #define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN
00146 #endif /*TIM7*/
00147 #if defined(TIM12)
00148 #define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1ENR_TIM12EN
00149 #endif /*TIM12*/
00150 #if defined(TIM13)
00151 #define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1ENR_TIM13EN
00152 #endif /*TIM13*/
00153 #if defined(TIM14)
00154 #define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1ENR_TIM14EN
00155 #endif /*TIM14*/
00156 #if defined(TIM18)
00157 #define LL_APB1_GRP1_PERIPH_TIM18          RCC_APB1ENR_TIM18EN
00158 #endif /*TIM18*/
00159 #define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN
00160 #if defined(SPI2)
00161 #define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN
00162 #endif /*SPI2*/
00163 #if defined(SPI3)
00164 #define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR_SPI3EN
00165 #endif /*SPI3*/
00166 #define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN
00167 #define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR_USART3EN
00168 #if defined(UART4)
00169 #define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR_UART4EN
00170 #endif /*UART4*/
00171 #if defined(UART5)
00172 #define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR_UART5EN
00173 #endif /*UART5*/
00174 #define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN
00175 #if defined(I2C2)
00176 #define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN
00177 #endif /*I2C2*/
00178 #if defined(USB)
00179 #define LL_APB1_GRP1_PERIPH_USB            RCC_APB1ENR_USBEN
00180 #endif /*USB*/
00181 #if defined(CAN)
00182 #define LL_APB1_GRP1_PERIPH_CAN            RCC_APB1ENR_CANEN
00183 #endif /*CAN*/
00184 #if defined(DAC2)
00185 #define LL_APB1_GRP1_PERIPH_DAC2           RCC_APB1ENR_DAC2EN
00186 #endif /*DAC2*/
00187 #define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN
00188 #define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DAC1EN
00189 #if defined(CEC)
00190 #define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1ENR_CECEN
00191 #endif /*CEC*/
00192 #if defined(I2C3)
00193 #define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR_I2C3EN
00194 #endif /*I2C3*/
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
00200   * @{
00201   */
00202 #define LL_APB2_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
00203 #define LL_APB2_GRP1_PERIPH_SYSCFG         RCC_APB2ENR_SYSCFGEN
00204 #if defined(RCC_APB2ENR_ADC1EN)
00205 #define LL_APB2_GRP1_PERIPH_ADC1           RCC_APB2ENR_ADC1EN
00206 #endif /*RCC_APB2ENR_ADC1EN*/
00207 #if defined(TIM1)
00208 #define LL_APB2_GRP1_PERIPH_TIM1           RCC_APB2ENR_TIM1EN
00209 #endif /*TIM1*/
00210 #if defined(SPI1)
00211 #define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN
00212 #endif /*SPI1*/
00213 #if defined(TIM8)
00214 #define LL_APB2_GRP1_PERIPH_TIM8           RCC_APB2ENR_TIM8EN
00215 #endif /*TIM8*/
00216 #define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN
00217 #if defined(SPI4)
00218 #define LL_APB2_GRP1_PERIPH_SPI4           RCC_APB2ENR_SPI4EN
00219 #endif /*SPI4*/
00220 #define LL_APB2_GRP1_PERIPH_TIM15          RCC_APB2ENR_TIM15EN
00221 #define LL_APB2_GRP1_PERIPH_TIM16          RCC_APB2ENR_TIM16EN
00222 #define LL_APB2_GRP1_PERIPH_TIM17          RCC_APB2ENR_TIM17EN
00223 #if defined(TIM19)
00224 #define LL_APB2_GRP1_PERIPH_TIM19          RCC_APB2ENR_TIM19EN
00225 #endif /*TIM19*/
00226 #if defined(TIM20)
00227 #define LL_APB2_GRP1_PERIPH_TIM20          RCC_APB2ENR_TIM20EN
00228 #endif /*TIM20*/
00229 #if defined(HRTIM1)
00230 #define LL_APB2_GRP1_PERIPH_HRTIM1         RCC_APB2ENR_HRTIM1EN
00231 #endif /*HRTIM1*/
00232 #if defined(SDADC1)
00233 #define LL_APB2_GRP1_PERIPH_SDADC1         RCC_APB2ENR_SDADC1EN
00234 #endif /*SDADC1*/
00235 #if defined(SDADC2)
00236 #define LL_APB2_GRP1_PERIPH_SDADC2         RCC_APB2ENR_SDADC2EN
00237 #endif /*SDADC2*/
00238 #if defined(SDADC3)
00239 #define LL_APB2_GRP1_PERIPH_SDADC3         RCC_APB2ENR_SDADC3EN
00240 #endif /*SDADC3*/
00241 /**
00242   * @}
00243   */
00244
00245 /**
00246   * @}
00247   */
00248
00249 /* Exported macro ------------------------------------------------------------*/
00250
00251 /* Exported functions --------------------------------------------------------*/
00252 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
00253   * @{
00254   */
00255
00256 /** @defgroup BUS_LL_EF_AHB1 AHB1
00257   * @{
00258   */
00259
00260 /**
00261   * @brief  Enable AHB1 peripherals clock.
00262   * @rmtoll AHBENR       DMA1EN        LL_AHB1_GRP1_EnableClock\n
00263   *         AHBENR       DMA2EN        LL_AHB1_GRP1_EnableClock\n
00264   *         AHBENR       SRAMEN        LL_AHB1_GRP1_EnableClock\n
00265   *         AHBENR       FLITFEN       LL_AHB1_GRP1_EnableClock\n
00266   *         AHBENR       FMCEN         LL_AHB1_GRP1_EnableClock\n
00267   *         AHBENR       CRCEN         LL_AHB1_GRP1_EnableClock\n
00268   *         AHBENR       GPIOHEN       LL_AHB1_GRP1_EnableClock\n
00269   *         AHBENR       GPIOAEN       LL_AHB1_GRP1_EnableClock\n
00270   *         AHBENR       GPIOBEN       LL_AHB1_GRP1_EnableClock\n
00271   *         AHBENR       GPIOCEN       LL_AHB1_GRP1_EnableClock\n
00272   *         AHBENR       GPIODEN       LL_AHB1_GRP1_EnableClock\n
00273   *         AHBENR       GPIOEEN       LL_AHB1_GRP1_EnableClock\n
00274   *         AHBENR       GPIOFEN       LL_AHB1_GRP1_EnableClock\n
00275   *         AHBENR       GPIOGEN       LL_AHB1_GRP1_EnableClock\n
00276   *         AHBENR       TSCEN         LL_AHB1_GRP1_EnableClock\n
00277   *         AHBENR       ADC1EN        LL_AHB1_GRP1_EnableClock\n
00278   *         AHBENR       ADC12EN       LL_AHB1_GRP1_EnableClock\n
00279   *         AHBENR       ADC34EN       LL_AHB1_GRP1_EnableClock
00280   * @param  Periphs This parameter can be a combination of the following values:
00281   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00282   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
00283   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
00284   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00285   *         @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
00286   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00287   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
00288   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
00289   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
00290   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
00291   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
00292   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
00293   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
00294   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
00295   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00296   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
00297   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
00298   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
00299   *
00300   *         (*) value not defined in all devices.
00301   * @retval None
00302 */
00303 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
00304 {
00305   __IO uint32_t tmpreg;
00306   SET_BIT(RCC->AHBENR, Periphs);
00307   /* Delay after an RCC peripheral clock enabling */
00308   tmpreg = READ_BIT(RCC->AHBENR, Periphs);
00309   (void)tmpreg;
00310 }
00311
00312 /**
00313   * @brief  Check if AHB1 peripheral clock is enabled or not
00314   * @rmtoll AHBENR       DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n
00315   *         AHBENR       DMA2EN        LL_AHB1_GRP1_IsEnabledClock\n
00316   *         AHBENR       SRAMEN        LL_AHB1_GRP1_IsEnabledClock\n
00317   *         AHBENR       FLITFEN       LL_AHB1_GRP1_IsEnabledClock\n
00318   *         AHBENR       FMCEN         LL_AHB1_GRP1_IsEnabledClock\n
00319   *         AHBENR       CRCEN         LL_AHB1_GRP1_IsEnabledClock\n
00320   *         AHBENR       GPIOHEN       LL_AHB1_GRP1_IsEnabledClock\n
00321   *         AHBENR       GPIOAEN       LL_AHB1_GRP1_IsEnabledClock\n
00322   *         AHBENR       GPIOBEN       LL_AHB1_GRP1_IsEnabledClock\n
00323   *         AHBENR       GPIOCEN       LL_AHB1_GRP1_IsEnabledClock\n
00324   *         AHBENR       GPIODEN       LL_AHB1_GRP1_IsEnabledClock\n
00325   *         AHBENR       GPIOEEN       LL_AHB1_GRP1_IsEnabledClock\n
00326   *         AHBENR       GPIOFEN       LL_AHB1_GRP1_IsEnabledClock\n
00327   *         AHBENR       GPIOGEN       LL_AHB1_GRP1_IsEnabledClock\n
00328   *         AHBENR       TSCEN         LL_AHB1_GRP1_IsEnabledClock\n
00329   *         AHBENR       ADC1EN        LL_AHB1_GRP1_IsEnabledClock\n
00330   *         AHBENR       ADC12EN       LL_AHB1_GRP1_IsEnabledClock\n
00331   *         AHBENR       ADC34EN       LL_AHB1_GRP1_IsEnabledClock
00332   * @param  Periphs This parameter can be a combination of the following values:
00333   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00334   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
00335   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
00336   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00337   *         @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
00338   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00339   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
00340   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
00341   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
00342   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
00343   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
00344   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
00345   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
00346   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
00347   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00348   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
00349   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
00350   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
00351   *
00352   *         (*) value not defined in all devices.
00353   * @retval State of Periphs (1 or 0).
00354 */
00355 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
00356 {
00357   return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
00358 }
00359
00360 /**
00361   * @brief  Disable AHB1 peripherals clock.
00362   * @rmtoll AHBENR       DMA1EN        LL_AHB1_GRP1_DisableClock\n
00363   *         AHBENR       DMA2EN        LL_AHB1_GRP1_DisableClock\n
00364   *         AHBENR       SRAMEN        LL_AHB1_GRP1_DisableClock\n
00365   *         AHBENR       FLITFEN       LL_AHB1_GRP1_DisableClock\n
00366   *         AHBENR       FMCEN         LL_AHB1_GRP1_DisableClock\n
00367   *         AHBENR       CRCEN         LL_AHB1_GRP1_DisableClock\n
00368   *         AHBENR       GPIOHEN       LL_AHB1_GRP1_DisableClock\n
00369   *         AHBENR       GPIOAEN       LL_AHB1_GRP1_DisableClock\n
00370   *         AHBENR       GPIOBEN       LL_AHB1_GRP1_DisableClock\n
00371   *         AHBENR       GPIOCEN       LL_AHB1_GRP1_DisableClock\n
00372   *         AHBENR       GPIODEN       LL_AHB1_GRP1_DisableClock\n
00373   *         AHBENR       GPIOEEN       LL_AHB1_GRP1_DisableClock\n
00374   *         AHBENR       GPIOFEN       LL_AHB1_GRP1_DisableClock\n
00375   *         AHBENR       GPIOGEN       LL_AHB1_GRP1_DisableClock\n
00376   *         AHBENR       TSCEN         LL_AHB1_GRP1_DisableClock\n
00377   *         AHBENR       ADC1EN        LL_AHB1_GRP1_DisableClock\n
00378   *         AHBENR       ADC12EN       LL_AHB1_GRP1_DisableClock\n
00379   *         AHBENR       ADC34EN       LL_AHB1_GRP1_DisableClock
00380   * @param  Periphs This parameter can be a combination of the following values:
00381   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00382   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
00383   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
00384   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00385   *         @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
00386   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00387   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
00388   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
00389   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
00390   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
00391   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
00392   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
00393   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
00394   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
00395   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00396   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
00397   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
00398   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
00399   *
00400   *         (*) value not defined in all devices.
00401   * @retval None
00402 */
00403 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
00404 {
00405   CLEAR_BIT(RCC->AHBENR, Periphs);
00406 }
00407
00408 /**
00409   * @brief  Force AHB1 peripherals reset.
00410   * @rmtoll AHBRSTR      FMCRST        LL_AHB1_GRP1_ForceReset\n
00411   *         AHBRSTR      GPIOHRST      LL_AHB1_GRP1_ForceReset\n
00412   *         AHBRSTR      GPIOARST      LL_AHB1_GRP1_ForceReset\n
00413   *         AHBRSTR      GPIOBRST      LL_AHB1_GRP1_ForceReset\n
00414   *         AHBRSTR      GPIOCRST      LL_AHB1_GRP1_ForceReset\n
00415   *         AHBRSTR      GPIODRST      LL_AHB1_GRP1_ForceReset\n
00416   *         AHBRSTR      GPIOERST      LL_AHB1_GRP1_ForceReset\n
00417   *         AHBRSTR      GPIOFRST      LL_AHB1_GRP1_ForceReset\n
00418   *         AHBRSTR      GPIOGRST      LL_AHB1_GRP1_ForceReset\n
00419   *         AHBRSTR      TSCRST        LL_AHB1_GRP1_ForceReset\n
00420   *         AHBRSTR      ADC1RST       LL_AHB1_GRP1_ForceReset\n
00421   *         AHBRSTR      ADC12RST      LL_AHB1_GRP1_ForceReset\n
00422   *         AHBRSTR      ADC34RST      LL_AHB1_GRP1_ForceReset
00423   * @param  Periphs This parameter can be a combination of the following values:
00424   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
00425   *         @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
00426   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
00427   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
00428   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
00429   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
00430   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
00431   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
00432   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
00433   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
00434   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00435   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
00436   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
00437   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
00438   *
00439   *         (*) value not defined in all devices.
00440   * @retval None
00441 */
00442 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
00443 {
00444   SET_BIT(RCC->AHBRSTR, Periphs);
00445 }
00446
00447 /**
00448   * @brief  Release AHB1 peripherals reset.
00449   * @rmtoll AHBRSTR      FMCRST        LL_AHB1_GRP1_ReleaseReset\n
00450   *         AHBRSTR      GPIOHRST      LL_AHB1_GRP1_ReleaseReset\n
00451   *         AHBRSTR      GPIOARST      LL_AHB1_GRP1_ReleaseReset\n
00452   *         AHBRSTR      GPIOBRST      LL_AHB1_GRP1_ReleaseReset\n
00453   *         AHBRSTR      GPIOCRST      LL_AHB1_GRP1_ReleaseReset\n
00454   *         AHBRSTR      GPIODRST      LL_AHB1_GRP1_ReleaseReset\n
00455   *         AHBRSTR      GPIOERST      LL_AHB1_GRP1_ReleaseReset\n
00456   *         AHBRSTR      GPIOFRST      LL_AHB1_GRP1_ReleaseReset\n
00457   *         AHBRSTR      GPIOGRST      LL_AHB1_GRP1_ReleaseReset\n
00458   *         AHBRSTR      TSCRST        LL_AHB1_GRP1_ReleaseReset\n
00459   *         AHBRSTR      ADC1RST       LL_AHB1_GRP1_ReleaseReset\n
00460   *         AHBRSTR      ADC12RST      LL_AHB1_GRP1_ReleaseReset\n
00461   *         AHBRSTR      ADC34RST      LL_AHB1_GRP1_ReleaseReset
00462   * @param  Periphs This parameter can be a combination of the following values:
00463   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
00464   *         @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
00465   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
00466   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
00467   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
00468   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
00469   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
00470   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
00471   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
00472   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
00473   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00474   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
00475   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
00476   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
00477   *
00478   *         (*) value not defined in all devices.
00479   * @retval None
00480 */
00481 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
00482 {
00483   CLEAR_BIT(RCC->AHBRSTR, Periphs);
00484 }
00485
00486 /**
00487   * @}
00488   */
00489
00490 /** @defgroup BUS_LL_EF_APB1 APB1
00491   * @{
00492   */
00493
00494 /**
00495   * @brief  Enable APB1 peripherals clock.
00496   * @rmtoll APB1ENR      TIM2EN        LL_APB1_GRP1_EnableClock\n
00497   *         APB1ENR      TIM3EN        LL_APB1_GRP1_EnableClock\n
00498   *         APB1ENR      TIM4EN        LL_APB1_GRP1_EnableClock\n
00499   *         APB1ENR      TIM5EN        LL_APB1_GRP1_EnableClock\n
00500   *         APB1ENR      TIM6EN        LL_APB1_GRP1_EnableClock\n
00501   *         APB1ENR      TIM7EN        LL_APB1_GRP1_EnableClock\n
00502   *         APB1ENR      TIM12EN       LL_APB1_GRP1_EnableClock\n
00503   *         APB1ENR      TIM13EN       LL_APB1_GRP1_EnableClock\n
00504   *         APB1ENR      TIM14EN       LL_APB1_GRP1_EnableClock\n
00505   *         APB1ENR      TIM18EN       LL_APB1_GRP1_EnableClock\n
00506   *         APB1ENR      WWDGEN        LL_APB1_GRP1_EnableClock\n
00507   *         APB1ENR      SPI2EN        LL_APB1_GRP1_EnableClock\n
00508   *         APB1ENR      SPI3EN        LL_APB1_GRP1_EnableClock\n
00509   *         APB1ENR      USART2EN      LL_APB1_GRP1_EnableClock\n
00510   *         APB1ENR      USART3EN      LL_APB1_GRP1_EnableClock\n
00511   *         APB1ENR      UART4EN       LL_APB1_GRP1_EnableClock\n
00512   *         APB1ENR      UART5EN       LL_APB1_GRP1_EnableClock\n
00513   *         APB1ENR      I2C1EN        LL_APB1_GRP1_EnableClock\n
00514   *         APB1ENR      I2C2EN        LL_APB1_GRP1_EnableClock\n
00515   *         APB1ENR      USBEN         LL_APB1_GRP1_EnableClock\n
00516   *         APB1ENR      CANEN         LL_APB1_GRP1_EnableClock\n
00517   *         APB1ENR      DAC2EN        LL_APB1_GRP1_EnableClock\n
00518   *         APB1ENR      PWREN         LL_APB1_GRP1_EnableClock\n
00519   *         APB1ENR      DAC1EN        LL_APB1_GRP1_EnableClock\n
00520   *         APB1ENR      CECEN         LL_APB1_GRP1_EnableClock\n
00521   *         APB1ENR      I2C3EN        LL_APB1_GRP1_EnableClock
00522   * @param  Periphs This parameter can be a combination of the following values:
00523   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
00524   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
00525   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
00526   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
00527   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
00528   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
00529   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
00530   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
00531   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
00532   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
00533   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00534   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
00535   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
00536   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00537   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
00538   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
00539   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
00540   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00541   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
00542   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
00543   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
00544   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
00545   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00546   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
00547   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
00548   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
00549   *
00550   *         (*) value not defined in all devices.
00551   * @retval None
00552 */
00553 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
00554 {
00555   __IO uint32_t tmpreg;
00556   SET_BIT(RCC->APB1ENR, Periphs);
00557   /* Delay after an RCC peripheral clock enabling */
00558   tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
00559   (void)tmpreg;
00560 }
00561
00562 /**
00563   * @brief  Check if APB1 peripheral clock is enabled or not
00564   * @rmtoll APB1ENR      TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
00565   *         APB1ENR      TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
00566   *         APB1ENR      TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
00567   *         APB1ENR      TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
00568   *         APB1ENR      TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
00569   *         APB1ENR      TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
00570   *         APB1ENR      TIM12EN       LL_APB1_GRP1_IsEnabledClock\n
00571   *         APB1ENR      TIM13EN       LL_APB1_GRP1_IsEnabledClock\n
00572   *         APB1ENR      TIM14EN       LL_APB1_GRP1_IsEnabledClock\n
00573   *         APB1ENR      TIM18EN       LL_APB1_GRP1_IsEnabledClock\n
00574   *         APB1ENR      WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
00575   *         APB1ENR      SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
00576   *         APB1ENR      SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
00577   *         APB1ENR      USART2EN      LL_APB1_GRP1_IsEnabledClock\n
00578   *         APB1ENR      USART3EN      LL_APB1_GRP1_IsEnabledClock\n
00579   *         APB1ENR      UART4EN       LL_APB1_GRP1_IsEnabledClock\n
00580   *         APB1ENR      UART5EN       LL_APB1_GRP1_IsEnabledClock\n
00581   *         APB1ENR      I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
00582   *         APB1ENR      I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
00583   *         APB1ENR      USBEN         LL_APB1_GRP1_IsEnabledClock\n
00584   *         APB1ENR      CANEN         LL_APB1_GRP1_IsEnabledClock\n
00585   *         APB1ENR      DAC2EN        LL_APB1_GRP1_IsEnabledClock\n
00586   *         APB1ENR      PWREN         LL_APB1_GRP1_IsEnabledClock\n
00587   *         APB1ENR      DAC1EN        LL_APB1_GRP1_IsEnabledClock\n
00588   *         APB1ENR      CECEN         LL_APB1_GRP1_IsEnabledClock\n
00589   *         APB1ENR      I2C3EN        LL_APB1_GRP1_IsEnabledClock
00590   * @param  Periphs This parameter can be a combination of the following values:
00591   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
00592   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
00593   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
00594   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
00595   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
00596   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
00597   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
00598   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
00599   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
00600   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
00601   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00602   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
00603   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
00604   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00605   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
00606   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
00607   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
00608   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00609   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
00610   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
00611   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
00612   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
00613   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00614   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
00615   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
00616   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
00617   *
00618   *         (*) value not defined in all devices.
00619   * @retval State of Periphs (1 or 0).
00620 */
00621 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
00622 {
00623   return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
00624 }
00625
00626 /**
00627   * @brief  Disable APB1 peripherals clock.
00628   * @rmtoll APB1ENR      TIM2EN        LL_APB1_GRP1_DisableClock\n
00629   *         APB1ENR      TIM3EN        LL_APB1_GRP1_DisableClock\n
00630   *         APB1ENR      TIM4EN        LL_APB1_GRP1_DisableClock\n
00631   *         APB1ENR      TIM5EN        LL_APB1_GRP1_DisableClock\n
00632   *         APB1ENR      TIM6EN        LL_APB1_GRP1_DisableClock\n
00633   *         APB1ENR      TIM7EN        LL_APB1_GRP1_DisableClock\n
00634   *         APB1ENR      TIM12EN       LL_APB1_GRP1_DisableClock\n
00635   *         APB1ENR      TIM13EN       LL_APB1_GRP1_DisableClock\n
00636   *         APB1ENR      TIM14EN       LL_APB1_GRP1_DisableClock\n
00637   *         APB1ENR      TIM18EN       LL_APB1_GRP1_DisableClock\n
00638   *         APB1ENR      WWDGEN        LL_APB1_GRP1_DisableClock\n
00639   *         APB1ENR      SPI2EN        LL_APB1_GRP1_DisableClock\n
00640   *         APB1ENR      SPI3EN        LL_APB1_GRP1_DisableClock\n
00641   *         APB1ENR      USART2EN      LL_APB1_GRP1_DisableClock\n
00642   *         APB1ENR      USART3EN      LL_APB1_GRP1_DisableClock\n
00643   *         APB1ENR      UART4EN       LL_APB1_GRP1_DisableClock\n
00644   *         APB1ENR      UART5EN       LL_APB1_GRP1_DisableClock\n
00645   *         APB1ENR      I2C1EN        LL_APB1_GRP1_DisableClock\n
00646   *         APB1ENR      I2C2EN        LL_APB1_GRP1_DisableClock\n
00647   *         APB1ENR      USBEN         LL_APB1_GRP1_DisableClock\n
00648   *         APB1ENR      CANEN         LL_APB1_GRP1_DisableClock\n
00649   *         APB1ENR      DAC2EN        LL_APB1_GRP1_DisableClock\n
00650   *         APB1ENR      PWREN         LL_APB1_GRP1_DisableClock\n
00651   *         APB1ENR      DAC1EN        LL_APB1_GRP1_DisableClock\n
00652   *         APB1ENR      CECEN         LL_APB1_GRP1_DisableClock\n
00653   *         APB1ENR      I2C3EN        LL_APB1_GRP1_DisableClock
00654   * @param  Periphs This parameter can be a combination of the following values:
00655   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
00656   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
00657   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
00658   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
00659   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
00660   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
00661   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
00662   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
00663   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
00664   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
00665   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00666   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
00667   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
00668   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00669   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
00670   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
00671   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
00672   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00673   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
00674   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
00675   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
00676   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
00677   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00678   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
00679   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
00680   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
00681   *
00682   *         (*) value not defined in all devices.
00683   * @retval None
00684 */
00685 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
00686 {
00687   CLEAR_BIT(RCC->APB1ENR, Periphs);
00688 }
00689
00690 /**
00691   * @brief  Force APB1 peripherals reset.
00692   * @rmtoll APB1RSTR     TIM2RST       LL_APB1_GRP1_ForceReset\n
00693   *         APB1RSTR     TIM3RST       LL_APB1_GRP1_ForceReset\n
00694   *         APB1RSTR     TIM4RST       LL_APB1_GRP1_ForceReset\n
00695   *         APB1RSTR     TIM5RST       LL_APB1_GRP1_ForceReset\n
00696   *         APB1RSTR     TIM6RST       LL_APB1_GRP1_ForceReset\n
00697   *         APB1RSTR     TIM7RST       LL_APB1_GRP1_ForceReset\n
00698   *         APB1RSTR     TIM12RST      LL_APB1_GRP1_ForceReset\n
00699   *         APB1RSTR     TIM13RST      LL_APB1_GRP1_ForceReset\n
00700   *         APB1RSTR     TIM14RST      LL_APB1_GRP1_ForceReset\n
00701   *         APB1RSTR     TIM18RST      LL_APB1_GRP1_ForceReset\n
00702   *         APB1RSTR     WWDGRST       LL_APB1_GRP1_ForceReset\n
00703   *         APB1RSTR     SPI2RST       LL_APB1_GRP1_ForceReset\n
00704   *         APB1RSTR     SPI3RST       LL_APB1_GRP1_ForceReset\n
00705   *         APB1RSTR     USART2RST     LL_APB1_GRP1_ForceReset\n
00706   *         APB1RSTR     USART3RST     LL_APB1_GRP1_ForceReset\n
00707   *         APB1RSTR     UART4RST      LL_APB1_GRP1_ForceReset\n
00708   *         APB1RSTR     UART5RST      LL_APB1_GRP1_ForceReset\n
00709   *         APB1RSTR     I2C1RST       LL_APB1_GRP1_ForceReset\n
00710   *         APB1RSTR     I2C2RST       LL_APB1_GRP1_ForceReset\n
00711   *         APB1RSTR     USBRST        LL_APB1_GRP1_ForceReset\n
00712   *         APB1RSTR     CANRST        LL_APB1_GRP1_ForceReset\n
00713   *         APB1RSTR     DAC2RST       LL_APB1_GRP1_ForceReset\n
00714   *         APB1RSTR     PWRRST        LL_APB1_GRP1_ForceReset\n
00715   *         APB1RSTR     DAC1RST       LL_APB1_GRP1_ForceReset\n
00716   *         APB1RSTR     CECRST        LL_APB1_GRP1_ForceReset\n
00717   *         APB1RSTR     I2C3RST       LL_APB1_GRP1_ForceReset
00718   * @param  Periphs This parameter can be a combination of the following values:
00719   *         @arg @ref LL_APB1_GRP1_PERIPH_ALL
00720   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
00721   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
00722   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
00723   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
00724   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
00725   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
00726   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
00727   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
00728   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
00729   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
00730   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00731   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
00732   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
00733   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00734   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
00735   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
00736   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
00737   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00738   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
00739   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
00740   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
00741   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
00742   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00743   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
00744   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
00745   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
00746   *
00747   *         (*) value not defined in all devices.
00748   * @retval None
00749 */
00750 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
00751 {
00752   SET_BIT(RCC->APB1RSTR, Periphs);
00753 }
00754
00755 /**
00756   * @brief  Release APB1 peripherals reset.
00757   * @rmtoll APB1RSTR     TIM2RST       LL_APB1_GRP1_ReleaseReset\n
00758   *         APB1RSTR     TIM3RST       LL_APB1_GRP1_ReleaseReset\n
00759   *         APB1RSTR     TIM4RST       LL_APB1_GRP1_ReleaseReset\n
00760   *         APB1RSTR     TIM5RST       LL_APB1_GRP1_ReleaseReset\n
00761   *         APB1RSTR     TIM6RST       LL_APB1_GRP1_ReleaseReset\n
00762   *         APB1RSTR     TIM7RST       LL_APB1_GRP1_ReleaseReset\n
00763   *         APB1RSTR     TIM12RST      LL_APB1_GRP1_ReleaseReset\n
00764   *         APB1RSTR     TIM13RST      LL_APB1_GRP1_ReleaseReset\n
00765   *         APB1RSTR     TIM14RST      LL_APB1_GRP1_ReleaseReset\n
00766   *         APB1RSTR     TIM18RST      LL_APB1_GRP1_ReleaseReset\n
00767   *         APB1RSTR     WWDGRST       LL_APB1_GRP1_ReleaseReset\n
00768   *         APB1RSTR     SPI2RST       LL_APB1_GRP1_ReleaseReset\n
00769   *         APB1RSTR     SPI3RST       LL_APB1_GRP1_ReleaseReset\n
00770   *         APB1RSTR     USART2RST     LL_APB1_GRP1_ReleaseReset\n
00771   *         APB1RSTR     USART3RST     LL_APB1_GRP1_ReleaseReset\n
00772   *         APB1RSTR     UART4RST      LL_APB1_GRP1_ReleaseReset\n
00773   *         APB1RSTR     UART5RST      LL_APB1_GRP1_ReleaseReset\n
00774   *         APB1RSTR     I2C1RST       LL_APB1_GRP1_ReleaseReset\n
00775   *         APB1RSTR     I2C2RST       LL_APB1_GRP1_ReleaseReset\n
00776   *         APB1RSTR     USBRST        LL_APB1_GRP1_ReleaseReset\n
00777   *         APB1RSTR     CANRST        LL_APB1_GRP1_ReleaseReset\n
00778   *         APB1RSTR     DAC2RST       LL_APB1_GRP1_ReleaseReset\n
00779   *         APB1RSTR     PWRRST        LL_APB1_GRP1_ReleaseReset\n
00780   *         APB1RSTR     DAC1RST       LL_APB1_GRP1_ReleaseReset\n
00781   *         APB1RSTR     CECRST        LL_APB1_GRP1_ReleaseReset\n
00782   *         APB1RSTR     I2C3RST       LL_APB1_GRP1_ReleaseReset
00783   * @param  Periphs This parameter can be a combination of the following values:
00784   *         @arg @ref LL_APB1_GRP1_PERIPH_ALL
00785   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
00786   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
00787   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
00788   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
00789   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
00790   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
00791   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
00792   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
00793   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
00794   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
00795   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00796   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
00797   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
00798   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00799   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
00800   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
00801   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
00802   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00803   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
00804   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
00805   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
00806   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
00807   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00808   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
00809   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
00810   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
00811   *
00812   *         (*) value not defined in all devices.
00813   * @retval None
00814 */
00815 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
00816 {
00817   CLEAR_BIT(RCC->APB1RSTR, Periphs);
00818 }
00819
00820 /**
00821   * @}
00822   */
00823
00824 /** @defgroup BUS_LL_EF_APB2 APB2
00825   * @{
00826   */
00827
00828 /**
00829   * @brief  Enable APB2 peripherals clock.
00830   * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_EnableClock\n
00831   *         APB2ENR      ADC1EN        LL_APB2_GRP1_EnableClock\n
00832   *         APB2ENR      TIM1EN        LL_APB2_GRP1_EnableClock\n
00833   *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n
00834   *         APB2ENR      TIM8EN        LL_APB2_GRP1_EnableClock\n
00835   *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\n
00836   *         APB2ENR      SPI4EN        LL_APB2_GRP1_EnableClock\n
00837   *         APB2ENR      TIM15EN       LL_APB2_GRP1_EnableClock\n
00838   *         APB2ENR      TIM16EN       LL_APB2_GRP1_EnableClock\n
00839   *         APB2ENR      TIM17EN       LL_APB2_GRP1_EnableClock\n
00840   *         APB2ENR      TIM19EN       LL_APB2_GRP1_EnableClock\n
00841   *         APB2ENR      TIM20EN       LL_APB2_GRP1_EnableClock\n
00842   *         APB2ENR      HRTIM1EN      LL_APB2_GRP1_EnableClock\n
00843   *         APB2ENR      SDADC1EN      LL_APB2_GRP1_EnableClock\n
00844   *         APB2ENR      SDADC2EN      LL_APB2_GRP1_EnableClock\n
00845   *         APB2ENR      SDADC3EN      LL_APB2_GRP1_EnableClock
00846   * @param  Periphs This parameter can be a combination of the following values:
00847   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
00848   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
00849   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
00850   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
00851   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
00852   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
00853   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
00854   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
00855   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
00856   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
00857   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
00858   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
00859   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
00860   *         @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
00861   *         @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
00862   *         @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
00863   *
00864   *         (*) value not defined in all devices.
00865   * @retval None
00866 */
00867 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
00868 {
00869   __IO uint32_t tmpreg;
00870   SET_BIT(RCC->APB2ENR, Periphs);
00871   /* Delay after an RCC peripheral clock enabling */
00872   tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
00873   (void)tmpreg;
00874 }
00875
00876 /**
00877   * @brief  Check if APB2 peripheral clock is enabled or not
00878   * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n
00879   *         APB2ENR      ADC1EN        LL_APB2_GRP1_IsEnabledClock\n
00880   *         APB2ENR      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
00881   *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
00882   *         APB2ENR      TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
00883   *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n
00884   *         APB2ENR      SPI4EN        LL_APB2_GRP1_IsEnabledClock\n
00885   *         APB2ENR      TIM15EN       LL_APB2_GRP1_IsEnabledClock\n
00886   *         APB2ENR      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n
00887   *         APB2ENR      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n
00888   *         APB2ENR      TIM19EN       LL_APB2_GRP1_IsEnabledClock\n
00889   *         APB2ENR      TIM20EN       LL_APB2_GRP1_IsEnabledClock\n
00890   *         APB2ENR      HRTIM1EN      LL_APB2_GRP1_IsEnabledClock\n
00891   *         APB2ENR      SDADC1EN      LL_APB2_GRP1_IsEnabledClock\n
00892   *         APB2ENR      SDADC2EN      LL_APB2_GRP1_IsEnabledClock\n
00893   *         APB2ENR      SDADC3EN      LL_APB2_GRP1_IsEnabledClock
00894   * @param  Periphs This parameter can be a combination of the following values:
00895   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
00896   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
00897   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
00898   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
00899   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
00900   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
00901   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
00902   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
00903   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
00904   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
00905   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
00906   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
00907   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
00908   *         @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
00909   *         @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
00910   *         @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
00911   *
00912   *         (*) value not defined in all devices.
00913   * @retval State of Periphs (1 or 0).
00914 */
00915 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
00916 {
00917   return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
00918 }
00919
00920 /**
00921   * @brief  Disable APB2 peripherals clock.
00922   * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_DisableClock\n
00923   *         APB2ENR      ADC1EN        LL_APB2_GRP1_DisableClock\n
00924   *         APB2ENR      TIM1EN        LL_APB2_GRP1_DisableClock\n
00925   *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n
00926   *         APB2ENR      TIM8EN        LL_APB2_GRP1_DisableClock\n
00927   *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\n
00928   *         APB2ENR      SPI4EN        LL_APB2_GRP1_DisableClock\n
00929   *         APB2ENR      TIM15EN       LL_APB2_GRP1_DisableClock\n
00930   *         APB2ENR      TIM16EN       LL_APB2_GRP1_DisableClock\n
00931   *         APB2ENR      TIM17EN       LL_APB2_GRP1_DisableClock\n
00932   *         APB2ENR      TIM19EN       LL_APB2_GRP1_DisableClock\n
00933   *         APB2ENR      TIM20EN       LL_APB2_GRP1_DisableClock\n
00934   *         APB2ENR      HRTIM1EN      LL_APB2_GRP1_DisableClock\n
00935   *         APB2ENR      SDADC1EN      LL_APB2_GRP1_DisableClock\n
00936   *         APB2ENR      SDADC2EN      LL_APB2_GRP1_DisableClock\n
00937   *         APB2ENR      SDADC3EN      LL_APB2_GRP1_DisableClock
00938   * @param  Periphs This parameter can be a combination of the following values:
00939   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
00940   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
00941   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
00942   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
00943   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
00944   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
00945   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
00946   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
00947   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
00948   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
00949   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
00950   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
00951   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
00952   *         @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
00953   *         @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
00954   *         @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
00955   *
00956   *         (*) value not defined in all devices.
00957   * @retval None
00958 */
00959 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
00960 {
00961   CLEAR_BIT(RCC->APB2ENR, Periphs);
00962 }
00963
00964 /**
00965   * @brief  Force APB2 peripherals reset.
00966   * @rmtoll APB2RSTR     SYSCFGRST     LL_APB2_GRP1_ForceReset\n
00967   *         APB2RSTR     ADC1RST       LL_APB2_GRP1_ForceReset\n
00968   *         APB2RSTR     TIM1RST       LL_APB2_GRP1_ForceReset\n
00969   *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\n
00970   *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ForceReset\n
00971   *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset\n
00972   *         APB2RSTR     SPI4RST       LL_APB2_GRP1_ForceReset\n
00973   *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ForceReset\n
00974   *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ForceReset\n
00975   *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ForceReset\n
00976   *         APB2RSTR     TIM19RST      LL_APB2_GRP1_ForceReset\n
00977   *         APB2RSTR     TIM20RST      LL_APB2_GRP1_ForceReset\n
00978   *         APB2RSTR     HRTIM1RST     LL_APB2_GRP1_ForceReset\n
00979   *         APB2RSTR     SDADC1RST     LL_APB2_GRP1_ForceReset\n
00980   *         APB2RSTR     SDADC2RST     LL_APB2_GRP1_ForceReset\n
00981   *         APB2RSTR     SDADC3RST     LL_APB2_GRP1_ForceReset
00982   * @param  Periphs This parameter can be a combination of the following values:
00983   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
00984   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
00985   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
00986   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
00987   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
00988   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
00989   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
00990   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
00991   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
00992   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
00993   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
00994   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
00995   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
00996   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
00997   *         @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
00998   *         @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
00999   *         @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
01000   *
01001   *         (*) value not defined in all devices.
01002   * @retval None
01003 */
01004 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
01005 {
01006   SET_BIT(RCC->APB2RSTR, Periphs);
01007 }
01008
01009 /**
01010   * @brief  Release APB2 peripherals reset.
01011   * @rmtoll APB2RSTR     SYSCFGRST     LL_APB2_GRP1_ReleaseReset\n
01012   *         APB2RSTR     ADC1RST       LL_APB2_GRP1_ReleaseReset\n
01013   *         APB2RSTR     TIM1RST       LL_APB2_GRP1_ReleaseReset\n
01014   *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\n
01015   *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ReleaseReset\n
01016   *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset\n
01017   *         APB2RSTR     SPI4RST       LL_APB2_GRP1_ReleaseReset\n
01018   *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ReleaseReset\n
01019   *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ReleaseReset\n
01020   *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ReleaseReset\n
01021   *         APB2RSTR     TIM19RST      LL_APB2_GRP1_ReleaseReset\n
01022   *         APB2RSTR     TIM20RST      LL_APB2_GRP1_ReleaseReset\n
01023   *         APB2RSTR     HRTIM1RST     LL_APB2_GRP1_ReleaseReset\n
01024   *         APB2RSTR     SDADC1RST     LL_APB2_GRP1_ReleaseReset\n
01025   *         APB2RSTR     SDADC2RST     LL_APB2_GRP1_ReleaseReset\n
01026   *         APB2RSTR     SDADC3RST     LL_APB2_GRP1_ReleaseReset
01027   * @param  Periphs This parameter can be a combination of the following values:
01028   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
01029   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01030   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
01031   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
01032   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
01033   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
01034   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01035   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
01036   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
01037   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01038   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01039   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
01040   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
01041   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
01042   *         @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
01043   *         @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
01044   *         @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
01045   *
01046   *         (*) value not defined in all devices.
01047   * @retval None
01048 */
01049 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
01050 {
01051   CLEAR_BIT(RCC->APB2RSTR, Periphs);
01052 }
01053
01054 /**
01055   * @}
01056   */
01057
01058
01059 /**
01060   * @}
01061   */
01062
01063 /**
01064   * @}
01065   */
01066
01067 #endif /* defined(RCC) */
01068
01069 /**
01070   * @}
01071   */
01072
01073 #ifdef __cplusplus
01074 }
01075 #endif
01076
01077 #endif /* __STM32F3xx_LL_BUS_H */
01078
01079 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_comp.c Source File

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stm32f3xx_ll_comp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_comp.c
00004   * @author  MCD Application Team
00005   * @brief   COMP LL module driver
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 #if defined(USE_FULL_LL_DRIVER)
00036
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f3xx_ll_comp.h"
00039
00040 #ifdef  USE_FULL_ASSERT
00041   #include "stm32_assert.h"
00042 #else
00043   #define assert_param(expr) ((void)0U)
00044 #endif
00045
00046 /** @addtogroup STM32F3xx_LL_Driver
00047   * @{
00048   */
00049
00050 /* Note: Devices of STM32F3 serie embed 1 out of 2 different comparator IP.   */
00051 /*       - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x:  */
00052 /*         COMP IP from 3 to 7 instances and other specific features          */
00053 /*         (comparator output blanking, ...) (refer to reference manual).     */
00054 /*       - STM32F37x:                                                         */
00055 /*         COMP IP with 2 instances                                           */
00056 /*       This file contains the drivers of these COMP IP, located in 2 area    */
00057 /*       delimited by compilation switches.                                   */
00058
00059 #if defined(COMP_V1_3_0_0)
00060
00061 #if defined (COMP1) || defined (COMP2) || defined (COMP3) || defined (COMP4) || defined (COMP5) || defined (COMP6) || defined (COMP7)
00062
00063 /** @addtogroup COMP_LL COMP
00064   * @{
00065   */
00066
00067 /* Private types -------------------------------------------------------------*/
00068 /* Private variables ---------------------------------------------------------*/
00069 /* Private constants ---------------------------------------------------------*/
00070 /* Private macros ------------------------------------------------------------*/
00071
00072 /** @addtogroup COMP_LL_Private_Macros
00073   * @{
00074   */
00075
00076 /* Check of parameters for configuration of COMP hierarchical scope:          */
00077 /* COMP instance.                                                             */
00078
00079 #if defined(COMP_CSR_COMPxMODE)
00080 #define IS_LL_COMP_POWER_MODE(__POWER_MODE__)                                  \
00081   (   ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)                        \
00082    || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED)                      \
00083    || ((__POWER_MODE__) == LL_COMP_POWERMODE_LOWPOWER)                         \
00084    || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER)                    \
00085   )
00086 #else
00087 #define IS_LL_COMP_POWER_MODE(__POWER_MODE__)                                  \
00088   ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)
00089 #endif
00090
00091 /* Note: On this STM32 serie, comparator input plus parameters are            */
00092 /*       the same on all COMP instances.                                      */
00093 /*       However, comparator instance kept as macro parameter for             */
00094 /*       compatibility with other STM32 families.                             */
00095 #if defined(COMP_CSR_COMPxNONINSEL) && defined(LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1)
00096 /* Note: On devices where bit COMP_CSR_COMPxNONINSEL is available,            */
00097 /*       feature LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 is also available.         */
00098 #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
00099   (   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                             \
00100    || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                             \
00101    || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1)                  \
00102   )
00103 #elif defined(COMP_CSR_COMPxNONINSEL) && defined(LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2)
00104 /* Note: On devices where bit COMP_CSR_COMPxNONINSEL is available,            */
00105 /*       feature LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 is also available.         */
00106 #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
00107   (   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                             \
00108    || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                             \
00109    || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2)                  \
00110   )
00111 #elif defined(COMP_CSR_COMPxNONINSEL)
00112 #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
00113   (   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                             \
00114    || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                             \
00115   )
00116 #elif defined(LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2)
00117 /* Note: On devices where bit COMP_CSR_COMPxNONINSEL is available,            */
00118 /*       feature LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 is also available.         */
00119 #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
00120   (   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                             \
00121    || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2)                  \
00122   )
00123 #else
00124 /* Note: Device without comparator input plus configurable: corresponds to    */
00125 /*       setting "LL_COMP_INPUT_PLUS_IO1" or "LL_COMP_INPUT_PLUS_IO2"         */
00126 /*       compared to other STM32F3 devices, depending on comparator instance  */
00127 /*       (refer to reference manual).                                         */
00128 #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
00129   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)
00130 #endif
00131
00132 #if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
00133 #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
00134   (   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
00135    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
00136    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
00137    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
00138    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
00139    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                      \
00140    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
00141    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
00142    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3)                           \
00143    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4)                           \
00144   )
00145 #elif defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8)
00146 #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
00147   (   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
00148    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
00149    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
00150    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
00151    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
00152    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                      \
00153    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
00154    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
00155    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4)                           \
00156    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1)                      \
00157   )
00158 #elif defined(STM32F302xC) || defined(STM32F302xE)
00159 #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
00160   (   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
00161    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
00162    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
00163    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
00164    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
00165    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
00166    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
00167    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3)                           \
00168    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4)                           \
00169   )
00170 #else /* STM32F301x8 || STM32F318xx || STM32F302x8 */
00171 #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
00172   (   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
00173    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
00174    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
00175    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
00176    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
00177    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
00178    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
00179    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4)                           \
00180   )
00181 #endif
00182
00183 #if defined(COMP_CSR_COMPxHYST)
00184 #define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)                      \
00185   (   ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)                      \
00186    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW)                       \
00187    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM)                    \
00188    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH)                      \
00189   )
00190 #else
00191 #define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)                      \
00192   ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)
00193 #endif
00194
00195 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
00196 #define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__)   \
00197   ((    ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE)                        \
00198      || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN)                   \
00199      || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2)                  \
00200    )                                                                           \
00201     ? (                                                                        \
00202        (1U)                                                                    \
00203       )                                                                        \
00204       :                                                                        \
00205       (((__COMP_INSTANCE__) == COMP2)                                          \
00206         ? (                                                                    \
00207               ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP2)        \
00208            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP2)        \
00209            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP2)      \
00210            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP2)      \
00211           )                                                                    \
00212           :                                                                    \
00213           (((__COMP_INSTANCE__) == COMP4)                                      \
00214             ? (                                                                \
00215                   ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4)   \
00216                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4) \
00217               )                                                                \
00218               :                                                                \
00219               (                                                                \
00220                   ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6)    \
00221                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6)  \
00222                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6)   \
00223                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6) \
00224               )                                                                \
00225           )                                                                    \
00226       )                                                                        \
00227   )
00228 #elif defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8)
00229 #define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__)   \
00230   ((    ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE)                        \
00231      || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN)                   \
00232      || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2)                  \
00233    )                                                                           \
00234     ? (                                                                        \
00235        (1U)                                                                    \
00236       )                                                                        \
00237       :                                                                        \
00238       (((__COMP_INSTANCE__) == COMP2)                                          \
00239         ? (                                                                    \
00240               ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4)    \
00241            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP2)        \
00242            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP2)        \
00243            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP2)      \
00244            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP2)      \
00245            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP2)        \
00246           )                                                                    \
00247           :                                                                    \
00248           (((__COMP_INSTANCE__) == COMP4)                                      \
00249             ? (                                                                \
00250                   ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4)\
00251                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC3_COMP4)    \
00252                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4)   \
00253                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4) \
00254               )                                                                \
00255               :                                                                \
00256               (                                                                \
00257                   ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6)    \
00258                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6)  \
00259                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6)   \
00260                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6) \
00261               )                                                                \
00262           )                                                                    \
00263       )                                                                        \
00264   )
00265 #elif defined(STM32F302xC) || defined(STM32F302xE)
00266 #define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__)      \
00267   ((    ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE)                           \
00268      || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN)                      \
00269      || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2)                     \
00270    )                                                                              \
00271     ? (                                                                           \
00272        (1U)                                                                       \
00273       )                                                                           \
00274       :                                                                           \
00275       ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2))         \
00276         ? (                                                                       \
00277               ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4)     \
00278            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP1_2)         \
00279            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP1_2)         \
00280            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2)       \
00281            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2)       \
00282            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP1_2)         \
00283           )                                                                       \
00284           :                                                                       \
00285           (((__COMP_INSTANCE__) == COMP4)                                         \
00286             ? (                                                                   \
00287                   ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4) \
00288                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC3_COMP4)       \
00289                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC2_COMP4)       \
00290                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4)      \
00291                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4)    \
00292               )                                                                   \
00293               :                                                                   \
00294               (                                                                   \
00295                   ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4) \
00296                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6)       \
00297                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6)     \
00298                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC4_COMP6)       \
00299                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6)      \
00300                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6)    \
00301               )                                                                   \
00302           )                                                                       \
00303       )                                                                           \
00304   )
00305 #elif defined(STM32F303xC) || defined(STM32F358xx)
00306 #define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__)                     \
00307   ((    ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE)                                          \
00308      || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN)                                     \
00309      || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2)                                    \
00310      || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_TIM8_BKIN2)                               \
00311    )                                                                                             \
00312     ? (                                                                                          \
00313        (1U)                                                                                      \
00314       )                                                                                          \
00315       :                                                                                          \
00316       ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2))                        \
00317         ? (                                                                                      \
00318               ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7)                  \
00319            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3)                    \
00320            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5)                  \
00321            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP1_2)                        \
00322            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP1_2)                        \
00323            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP1_2)                        \
00324           )                                                                                      \
00325           :                                                                                      \
00326           (((__COMP_INSTANCE__) == COMP3)                                                        \
00327             ? (                                                                                  \
00328                   ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7)              \
00329                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3)                \
00330                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC2_COMP3)                      \
00331                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC1_COMP3)                      \
00332                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC1_COMP3)                     \
00333                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_BKIN)                          \
00334               )                                                                                  \
00335               :                                                                                  \
00336               (((__COMP_INSTANCE__) == COMP4)                                                    \
00337                 ? (                                                                              \
00338                       ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5)          \
00339                    || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC3_COMP4)                  \
00340                    || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC2_COMP4)                  \
00341                    || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4)                 \
00342                    || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4)               \
00343                   )                                                                              \
00344                   :                                                                              \
00345                   (((__COMP_INSTANCE__) == COMP5)                                                \
00346                     ? (                                                                          \
00347                           ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5)      \
00348                        || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7)      \
00349                        || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC1_COMP5)              \
00350                        || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC3_COMP5)              \
00351                        || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_IC1_COMP5)             \
00352                        || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_BKIN)                  \
00353                       )                                                                          \
00354                       :                                                                          \
00355                       (((__COMP_INSTANCE__) == COMP6)                                            \
00356                         ? (                                                                      \
00357                               ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7)  \
00358                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6)          \
00359                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6)        \
00360                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC4_COMP6)          \
00361                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6)         \
00362                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6)       \
00363                           )                                                                      \
00364                           :                                                                      \
00365                           (                                                                      \
00366                               ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7)  \
00367                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7)  \
00368                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC2_COMP7)          \
00369                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC3_COMP7)          \
00370                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_OCCLR_COMP7)       \
00371                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_BKIN)              \
00372                           )                                                                      \
00373                       )                                                                          \
00374                   )                                                                              \
00375               )                                                                                  \
00376           )                                                                                      \
00377       )                                                                                          \
00378   )
00379 #elif defined(STM32F303xE) || defined(STM32F398xx)
00380 #define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__)                     \
00381   ((    ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE)                                          \
00382      || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN)                                     \
00383      || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2)                                    \
00384      || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_TIM8_BKIN2)                               \
00385      || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM20_BKIN)                                    \
00386      || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM20_BKIN2)                                   \
00387      || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_TIM8_TIM20_BKIN2)                         \
00388    )                                                                                             \
00389     ? (                                                                                          \
00390        (1U)                                                                                      \
00391       )                                                                                          \
00392       :                                                                                          \
00393       ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2))                        \
00394         ? (                                                                                      \
00395               ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7)                  \
00396            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3)                    \
00397            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5)                  \
00398            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP1_2)                        \
00399            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP1_2)                        \
00400            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP1_2)                        \
00401            || (((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM20_OCCLR_COMP2)                      \
00402                && ((__COMP_INSTANCE__) == COMP2)                     )                           \
00403           )                                                                                      \
00404           :                                                                                      \
00405           (((__COMP_INSTANCE__) == COMP3)                                                        \
00406             ? (                                                                                  \
00407                   ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7)              \
00408                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3)                \
00409                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC2_COMP3)                      \
00410                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC1_COMP3)                      \
00411                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC1_COMP3)                     \
00412                || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_BKIN)                          \
00413               )                                                                                  \
00414               :                                                                                  \
00415               (((__COMP_INSTANCE__) == COMP4)                                                    \
00416                 ? (                                                                              \
00417                       ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5)          \
00418                    || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC3_COMP4)                  \
00419                    || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC2_COMP4)                  \
00420                    || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4)                 \
00421                    || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4)               \
00422                   )                                                                              \
00423                   :                                                                              \
00424                   (((__COMP_INSTANCE__) == COMP5)                                                \
00425                     ? (                                                                          \
00426                           ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5)      \
00427                        || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7)      \
00428                        || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC1_COMP5)              \
00429                        || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC3_COMP5)              \
00430                        || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_IC1_COMP5)             \
00431                        || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_BKIN)                  \
00432                       )                                                                          \
00433                       :                                                                          \
00434                       (((__COMP_INSTANCE__) == COMP6)                                            \
00435                         ? (                                                                      \
00436                               ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7)  \
00437                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6)          \
00438                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6)        \
00439                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC4_COMP6)          \
00440                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6)         \
00441                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6)       \
00442                           )                                                                      \
00443                           :                                                                      \
00444                           (                                                                      \
00445                               ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7)  \
00446                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7)  \
00447                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC2_COMP7)          \
00448                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC3_COMP7)          \
00449                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_OCCLR_COMP7)       \
00450                            || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_BKIN)              \
00451                           )                                                                      \
00452                       )                                                                          \
00453                   )                                                                              \
00454               )                                                                                  \
00455           )                                                                                      \
00456       )                                                                                          \
00457   )
00458 #endif
00459
00460 #define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)                               \
00461   (   ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED)                        \
00462    || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED)                           \
00463   )
00464
00465 #if defined(COMP_CSR_COMPxBLANKING)
00466 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
00467 #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__)       \
00468   (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)                                  \
00469     ? (                                                                                        \
00470        (1U)                                                                                    \
00471       )                                                                                        \
00472       :                                                                                        \
00473       (((__COMP_INSTANCE__) == COMP2)                                                          \
00474         ? (                                                                                    \
00475               ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2)             \
00476            || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2)             \
00477            || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2)             \
00478           )                                                                                    \
00479           :                                                                                    \
00480           (((__COMP_INSTANCE__) == COMP4)                                                      \
00481             ? (                                                                                \
00482                   ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4)         \
00483                || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4)        \
00484               )                                                                                \
00485               :                                                                                \
00486               (                                                                                \
00487                 (((__COMP_INSTANCE__) == COMP6)                                                \
00488                   ? (                                                                          \
00489                         ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6)   \
00490                      || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6)  \
00491                     )                                                                          \
00492                     :                                                                          \
00493                     (                                                                          \
00494                      (0U)                                                                      \
00495                     )                                                                          \
00496                 )                                                                              \
00497               )                                                                                \
00498           )                                                                                    \
00499       )                                                                                        \
00500   )
00501 #elif defined(STM32F302xE) || defined(STM32F302xC)
00502 #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__)       \
00503   (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)                                  \
00504     ? (                                                                                        \
00505        (1U)                                                                                    \
00506       )                                                                                        \
00507       :                                                                                        \
00508       ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2))                      \
00509         ? (                                                                                    \
00510               ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2)           \
00511            || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2)           \
00512            || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2)           \
00513           )                                                                                    \
00514           :                                                                                    \
00515           (((__COMP_INSTANCE__) == COMP4)                                                      \
00516             ? (                                                                                \
00517                   ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4)         \
00518                || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4)        \
00519               )                                                                                \
00520               :                                                                                \
00521               (                                                                                \
00522                 (((__COMP_INSTANCE__) == COMP6)                                                \
00523                   ? (                                                                          \
00524                         ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6)   \
00525                      || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6)  \
00526                     )                                                                          \
00527                     :                                                                          \
00528                     (                                                                          \
00529                      (0U)                                                                      \
00530                     )                                                                          \
00531                 )                                                                              \
00532               )                                                                                \
00533           )                                                                                    \
00534       )                                                                                        \
00535   )
00536 #elif defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
00537 #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__)                 \
00538   (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)                                            \
00539     ? (                                                                                                  \
00540        (1U)                                                                                              \
00541       )                                                                                                  \
00542       :                                                                                                  \
00543       ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2))                                \
00544         ? (                                                                                              \
00545               ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7)                   \
00546            || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2)                     \
00547            || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2)                     \
00548           )                                                                                              \
00549           :                                                                                              \
00550           (((__COMP_INSTANCE__) == COMP3)                                                                \
00551             ? (                                                                                          \
00552                ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6)                    \
00553               )                                                                                          \
00554               :                                                                                          \
00555               (((__COMP_INSTANCE__) == COMP4)                                                            \
00556                 ? (                                                                                      \
00557                       ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7)         \
00558                    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4)               \
00559                    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4)              \
00560                   )                                                                                      \
00561                   :                                                                                      \
00562                   (((__COMP_INSTANCE__) == COMP5)                                                        \
00563                     ? (                                                                                  \
00564                           ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7)     \
00565                       )                                                                                  \
00566                       :                                                                                  \
00567                       (((__COMP_INSTANCE__) == COMP6)                                                    \
00568                         ? (                                                                              \
00569                               ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7) \
00570                            || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6)     \
00571                            || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7)    \
00572                           )                                                                              \
00573                           :                                                                              \
00574                           (                                                                              \
00575                               ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7) \
00576                            || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7)   \
00577                            || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7)    \
00578                           )                                                                              \
00579                       )                                                                                  \
00580                   )                                                                                      \
00581               )                                                                                          \
00582           )                                                                                              \
00583       )                                                                                                  \
00584   )
00585 #endif
00586 #else
00587 #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
00588   ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)
00589 #endif
00590 /**
00591   * @}
00592   */
00593
00594
00595 /* Private function prototypes -----------------------------------------------*/
00596
00597 /* Exported functions --------------------------------------------------------*/
00598 /** @addtogroup COMP_LL_Exported_Functions
00599   * @{
00600   */
00601
00602 /** @addtogroup COMP_LL_EF_Init
00603   * @{
00604   */
00605
00606 /**
00607   * @brief  De-initialize registers of the selected COMP instance
00608   *         to their default reset values.
00609   * @note   If comparator is locked, de-initialization by software is
00610   *         not possible.
00611   *         The only way to unlock the comparator is a device hardware reset.
00612   * @param  COMPx COMP instance
00613   * @retval An ErrorStatus enumeration value:
00614   *          - SUCCESS: COMP registers are de-initialized
00615   *          - ERROR: COMP registers are not de-initialized
00616   */
00617 ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
00618 {
00619   ErrorStatus status = SUCCESS;
00620
00621   /* Check the parameters */
00622   assert_param(IS_COMP_ALL_INSTANCE(COMPx));
00623
00624   /* Note: Hardware constraint (refer to description of this function):       */
00625   /*       COMP instance must not be locked.                                  */
00626   if(LL_COMP_IsLocked(COMPx) == 0U)
00627   {
00628     LL_COMP_WriteReg(COMPx, CSR, 0x00000000U);
00629   }
00630   else
00631   {
00632     /* Comparator instance is locked: de-initialization by software is         */
00633     /* not possible.                                                           */
00634     /* The only way to unlock the comparator is a device hardware reset.       */
00635     status = ERROR;
00636   }
00637
00638   return status;
00639 }
00640
00641 /**
00642   * @brief  Initialize some features of COMP instance.
00643   * @note   This function configures features of the selected COMP instance.
00644   *         Some features are also available at scope COMP common instance
00645   *         (common to several COMP instances).
00646   *         Refer to functions having argument "COMPxy_COMMON" as parameter.
00647   * @param  COMPx COMP instance
00648   * @param  COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
00649   * @retval An ErrorStatus enumeration value:
00650   *          - SUCCESS: COMP registers are initialized
00651   *          - ERROR: COMP registers are not initialized
00652   */
00653 ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
00654 {
00655   ErrorStatus status = SUCCESS;
00656
00657   /* Check the parameters */
00658   assert_param(IS_COMP_ALL_INSTANCE(COMPx));
00659   assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
00660   assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
00661   assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
00662   assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
00663   assert_param(IS_LL_COMP_OUTPUT_SELECTION(COMPx, COMP_InitStruct->OutputSelection));
00664   assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
00665   assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMPx, COMP_InitStruct->OutputBlankingSource));
00666
00667   /* Note: Hardware constraint (refer to description of this function)        */
00668   /*       COMP instance must not be locked.                                  */
00669   if(LL_COMP_IsLocked(COMPx) == 0U)
00670   {
00671     /* Configuration of comparator instance :                                 */
00672     /*  - PowerMode                                                           */
00673     /*  - InputPlus                                                           */
00674     /*  - InputMinus                                                          */
00675     /*  - InputHysteresis                                                     */
00676     /*  - OutputSelection                                                     */
00677     /*  - OutputPolarity                                                      */
00678     /*  - OutputBlankingSource                                                */
00679     MODIFY_REG(COMPx->CSR,
00680                  ((uint32_t)0x00000000U)
00681 #if defined(COMP_CSR_COMPxMODE)
00682                | COMP_CSR_COMPxMODE
00683 #endif
00684 #if defined(COMP_CSR_COMPxNONINSEL)
00685                | COMP_CSR_COMPxNONINSEL
00686 #endif
00687                | COMP_CSR_COMPxINSEL
00688 #if defined(COMP_CSR_COMPxHYST)
00689                | COMP_CSR_COMPxHYST
00690 #endif
00691                | COMP_CSR_COMPxOUTSEL
00692                | COMP_CSR_COMPxPOL
00693                | COMP_CSR_COMPxBLANKING
00694               ,
00695                  ((uint32_t)0x00000000U)
00696 #if defined(COMP_CSR_COMPxMODE)
00697                | COMP_InitStruct->PowerMode
00698 #endif
00699 #if defined(COMP_CSR_COMPxNONINSEL)
00700                | COMP_InitStruct->InputPlus
00701 #endif
00702                | COMP_InitStruct->InputMinus
00703 #if defined(COMP_CSR_COMPxHYST)
00704                | COMP_InitStruct->InputHysteresis
00705 #endif
00706                | COMP_InitStruct->OutputSelection
00707                | COMP_InitStruct->OutputPolarity
00708                | COMP_InitStruct->OutputBlankingSource
00709               );
00710
00711   }
00712   else
00713   {
00714     /* Initialization error: COMP instance is locked.                         */
00715     status = ERROR;
00716   }
00717
00718   return status;
00719 }
00720
00721 /**
00722   * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
00723   * @param COMP_InitStruct pointer to a @ref LL_COMP_InitTypeDef structure
00724   *                         whose fields will be set to default values.
00725   * @retval None
00726   */
00727 void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
00728 {
00729   /* Set COMP_InitStruct fields to default values */
00730   /* Note: Comparator power mode "high speed" is the only mode                */
00731   /*       available on all STMF3 devices.                                    */
00732   COMP_InitStruct->PowerMode            = LL_COMP_POWERMODE_HIGHSPEED;
00733   COMP_InitStruct->InputPlus            = LL_COMP_INPUT_PLUS_IO1;
00734   COMP_InitStruct->InputMinus           = LL_COMP_INPUT_MINUS_VREFINT;
00735   COMP_InitStruct->InputHysteresis      = LL_COMP_HYSTERESIS_NONE;
00736   COMP_InitStruct->OutputSelection      = LL_COMP_OUTPUT_NONE;
00737   COMP_InitStruct->OutputPolarity       = LL_COMP_OUTPUTPOL_NONINVERTED;
00738   COMP_InitStruct->OutputBlankingSource = LL_COMP_BLANKINGSRC_NONE;
00739 }
00740
00741 /**
00742   * @}
00743   */
00744
00745 /**
00746   * @}
00747   */
00748
00749 /**
00750   * @}
00751   */
00752
00753 #endif /* COMP1 || COMP2 || COMP3 || COMP4 || COMP5 || COMP6 || COMP7 */
00754
00755
00756 #endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
00757
00758 #if defined (COMP_V1_1_0_0)
00759
00760 #if defined (COMP1) || defined (COMP2)
00761
00762 /** @addtogroup COMP_LL COMP
00763   * @{
00764   */
00765
00766 /* Private types -------------------------------------------------------------*/
00767 /* Private variables ---------------------------------------------------------*/
00768 /* Private constants ---------------------------------------------------------*/
00769 /* Private macros ------------------------------------------------------------*/
00770
00771 /** @addtogroup COMP_LL_Private_Macros
00772   * @{
00773   */
00774
00775 /* Check of parameters for configuration of COMP hierarchical scope:          */
00776 /* COMP instance.                                                             */
00777
00778 #define IS_LL_COMP_POWER_MODE(__POWER_MODE__)                                  \
00779   (   ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)                        \
00780    || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED)                      \
00781    || ((__POWER_MODE__) == LL_COMP_POWERMODE_LOWPOWER)                         \
00782    || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER)                    \
00783   )
00784
00785 /* Note: On this STM32 serie, comparator input plus parameters are            */
00786 /*       the different depending on COMP instances.                           */
00787 #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
00788   (((__COMP_INSTANCE__) == COMP1)                                              \
00789     ? (                                                                        \
00790           ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                         \
00791        || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1)                    \
00792       )                                                                        \
00793       :                                                                        \
00794       (                                                                        \
00795           ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                         \
00796       )                                                                        \
00797   )
00798
00799 /* Note: On this STM32 serie, comparator input minus parameters are           */
00800 /*       the same on all COMP instances.                                      */
00801 /*       However, comparator instance kept as macro parameter for             */
00802 /*       compatibility with other STM32 families.                             */
00803 #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
00804   (   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
00805    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
00806    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
00807    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
00808    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
00809    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                      \
00810    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
00811    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
00812    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3)                           \
00813    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4)                           \
00814    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1)                      \
00815   )
00816
00817 #define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)                      \
00818   (   ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)                      \
00819    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW)                       \
00820    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM)                    \
00821    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH)                      \
00822   )
00823
00824 /* Note: Output redirection is specific to COMP instances but is checked      */
00825 /*       with literals of instance COMP2 (no differentiation possible since   */
00826 /*       literals of COMP1 and COMP2 share the same values range).            */
00827 #define IS_LL_COMP_OUTPUT_SELECTION(__OUTPUT_SELECTION__)                      \
00828   (   ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE)                          \
00829    || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_BKIN)                    \
00830    || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC1)                      \
00831    || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_OCCLR)                    \
00832    || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4)                      \
00833    || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR)                    \
00834    || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP2)                \
00835    || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP2)              \
00836   )
00837
00838 #define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)                               \
00839   (   ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED)                        \
00840    || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED)                           \
00841   )
00842
00843 /**
00844   * @}
00845   */
00846
00847
00848 /* Private function prototypes -----------------------------------------------*/
00849
00850 /* Exported functions --------------------------------------------------------*/
00851 /** @addtogroup COMP_LL_Exported_Functions
00852   * @{
00853   */
00854
00855 /** @addtogroup COMP_LL_EF_Init
00856   * @{
00857   */
00858
00859 /**
00860   * @brief  De-initialize registers of the selected COMP instance
00861   *         to their default reset values.
00862   * @note   If comparator is locked, de-initialization by software is
00863   *         not possible.
00864   *         The only way to unlock the comparator is a device hardware reset.
00865   * @param  COMPx COMP instance
00866   * @retval An ErrorStatus enumeration value:
00867   *          - SUCCESS: COMP registers are de-initialized
00868   *          - ERROR: COMP registers are not de-initialized
00869   */
00870 ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
00871 {
00872   ErrorStatus status = SUCCESS;
00873
00874   /* Check the parameters */
00875   assert_param(IS_COMP_ALL_INSTANCE(COMPx));
00876
00877   /* Note: Hardware constraint (refer to description of this function):       */
00878   /*       COMP instance must not be locked.                                  */
00879   if(LL_COMP_IsLocked(COMPx) == 0U)
00880   {
00881     /* Note: Connection switch is applicable only to COMP instance COMP1,     */
00882     /*       therefore is COMP2 is selected the equivalent bit is             */
00883     /*       kept unmodified.                                                 */
00884     if(COMPx == COMP1)
00885     {
00886       CLEAR_BIT(COMP->CSR,
00887                 (  COMP_CSR_COMP1MODE
00888                  | COMP_CSR_COMP1INSEL
00889                  | COMP_CSR_COMP1SW1
00890                  | COMP_CSR_COMP1OUTSEL
00891                  | COMP_CSR_COMP1HYST
00892                  | COMP_CSR_COMP1POL
00893                  | COMP_CSR_COMP1EN
00894                 ) << __COMP_BITOFFSET_INSTANCE(COMPx)
00895                );
00896     }
00897     else
00898     {
00899       CLEAR_BIT(COMP->CSR,
00900                 (  COMP_CSR_COMP1MODE
00901                  | COMP_CSR_COMP1INSEL
00902                  | COMP_CSR_COMP1OUTSEL
00903                  | COMP_CSR_COMP1HYST
00904                  | COMP_CSR_COMP1POL
00905                  | COMP_CSR_COMP1EN
00906                 ) << __COMP_BITOFFSET_INSTANCE(COMPx)
00907                );
00908     }
00909
00910   }
00911   else
00912   {
00913     /* Comparator instance is locked: de-initialization by software is         */
00914     /* not possible.                                                           */
00915     /* The only way to unlock the comparator is a device hardware reset.       */
00916     status = ERROR;
00917   }
00918
00919   return status;
00920 }
00921
00922 /**
00923   * @brief  Initialize some features of COMP instance.
00924   * @note   This function configures features of the selected COMP instance.
00925   *         Some features are also available at scope COMP common instance
00926   *         (common to several COMP instances).
00927   *         Refer to functions having argument "COMPxy_COMMON" as parameter.
00928   * @param  COMPx COMP instance
00929   * @param  COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
00930   * @retval An ErrorStatus enumeration value:
00931   *          - SUCCESS: COMP registers are initialized
00932   *          - ERROR: COMP registers are not initialized
00933   */
00934 ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
00935 {
00936   ErrorStatus status = SUCCESS;
00937
00938   /* Check the parameters */
00939   assert_param(IS_COMP_ALL_INSTANCE(COMPx));
00940   assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
00941   assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
00942   assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
00943   assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
00944   assert_param(IS_LL_COMP_OUTPUT_SELECTION(COMP_InitStruct->OutputSelection));
00945   assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
00946
00947   /* Note: Hardware constraint (refer to description of this function)        */
00948   /*       COMP instance must not be locked.                                  */
00949   if(LL_COMP_IsLocked(COMPx) == 0U)
00950   {
00951     /* Configuration of comparator instance :                                 */
00952     /*  - PowerMode                                                           */
00953     /*  - InputPlus                                                           */
00954     /*  - InputMinus                                                          */
00955     /*  - InputHysteresis                                                     */
00956     /*  - OutputSelection                                                     */
00957     /*  - OutputPolarity                                                      */
00958     /* Note: Connection switch is applicable only to COMP instance COMP1,     */
00959     /*       therefore is COMP2 is selected the equivalent bit is             */
00960     /*       kept unmodified.                                                 */
00961     if(COMPx == COMP1)
00962     {
00963       MODIFY_REG(COMP->CSR,
00964                  (  COMP_CSR_COMP1MODE
00965                   | COMP_CSR_COMP1INSEL
00966                   | COMP_CSR_COMP1SW1
00967                   | COMP_CSR_COMP1OUTSEL
00968                   | COMP_CSR_COMP1HYST
00969                   | COMP_CSR_COMP1POL
00970                  ) << __COMP_BITOFFSET_INSTANCE(COMPx)
00971                 ,
00972                  (  COMP_InitStruct->PowerMode
00973                   | COMP_InitStruct->InputPlus
00974                   | COMP_InitStruct->InputMinus
00975                   | COMP_InitStruct->InputHysteresis
00976                   | COMP_InitStruct->OutputSelection
00977                   | COMP_InitStruct->OutputPolarity
00978                  ) << __COMP_BITOFFSET_INSTANCE(COMPx)
00979                 );
00980     }
00981     else
00982     {
00983       MODIFY_REG(COMP->CSR,
00984                  (  COMP_CSR_COMP1MODE
00985                   | COMP_CSR_COMP1INSEL
00986                   | COMP_CSR_COMP1OUTSEL
00987                   | COMP_CSR_COMP1HYST
00988                   | COMP_CSR_COMP1POL
00989                  ) << __COMP_BITOFFSET_INSTANCE(COMPx)
00990                 ,
00991                  (  COMP_InitStruct->PowerMode
00992                   | COMP_InitStruct->InputPlus
00993                   | COMP_InitStruct->InputMinus
00994                   | COMP_InitStruct->InputHysteresis
00995                   | COMP_InitStruct->OutputSelection
00996                   | COMP_InitStruct->OutputPolarity
00997                  ) << __COMP_BITOFFSET_INSTANCE(COMPx)
00998                 );
00999     }
01000
01001   }
01002   else
01003   {
01004     /* Initialization error: COMP instance is locked.                         */
01005     status = ERROR;
01006   }
01007
01008   return status;
01009 }
01010
01011 /**
01012   * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
01013   * @param COMP_InitStruct pointer to a @ref LL_COMP_InitTypeDef structure
01014   *                         whose fields will be set to default values.
01015   * @retval None
01016   */
01017 void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
01018 {
01019   /* Set COMP_InitStruct fields to default values */
01020   COMP_InitStruct->PowerMode            = LL_COMP_POWERMODE_ULTRALOWPOWER;
01021   COMP_InitStruct->InputPlus            = LL_COMP_INPUT_PLUS_IO1;
01022   COMP_InitStruct->InputMinus           = LL_COMP_INPUT_MINUS_VREFINT;
01023   COMP_InitStruct->InputHysteresis      = LL_COMP_HYSTERESIS_NONE;
01024   COMP_InitStruct->OutputSelection      = LL_COMP_OUTPUT_NONE;
01025   COMP_InitStruct->OutputPolarity       = LL_COMP_OUTPUTPOL_NONINVERTED;
01026 }
01027
01028 /**
01029   * @}
01030   */
01031
01032 /**
01033   * @}
01034   */
01035
01036 /**
01037   * @}
01038   */
01039
01040 #endif /* COMP1 || COMP2 */
01041
01042
01043 #endif /* STM32F373xC || STM32F378xx */
01044
01045 /**
01046   * @}
01047   */
01048
01049 #endif /* USE_FULL_LL_DRIVER */
01050
01051 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_comp.h Source File

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stm32f3xx_ll_comp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_comp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of COMP LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_COMP_H
00038 #define __STM32F3xx_LL_COMP_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 /* Note: Devices of STM32F3 serie embed 1 out of 2 different comparator IP.   */
00052 /*       - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x:  */
00053 /*         COMP IP from 3 to 7 instances and other specific features          */
00054 /*         (comparator output blanking, ...) (refer to reference manual).     */
00055 /*       - STM32F37x:                                                         */
00056 /*         COMP IP with 2 instances                                           */
00057 /*       This file contains the drivers of these COMP IP, located in 2 area    */
00058 /*       delimited by compilation switches.                                   */
00059
00060 #if defined(COMP_V1_3_0_0)
00061
00062 #if defined (COMP1) || defined (COMP2) || defined (COMP3) || defined (COMP4) || defined (COMP5) || defined (COMP6) || defined (COMP7)
00063
00064 /** @defgroup COMP_LL COMP
00065   * @{
00066   */
00067
00068 /* Private types -------------------------------------------------------------*/
00069 /* Private variables ---------------------------------------------------------*/
00070 /* Private constants ---------------------------------------------------------*/
00071 /** @defgroup COMP_LL_Private_Constants COMP Private Constants
00072   * @{
00073   */
00074
00075 /* COMP registers bits positions */
00076 #define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)30U) /* Value equivalent to POSITION_VAL(COMPxOUT) */
00077
00078 /**
00079   * @}
00080   */
00081
00082 /* Private macros ------------------------------------------------------------*/
00083 /* Exported types ------------------------------------------------------------*/
00084 #if defined(USE_FULL_LL_DRIVER)
00085 /** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
00086   * @{
00087   */
00088
00089 /**
00090   * @brief  Structure definition of some features of COMP instance.
00091   */
00092 typedef struct
00093 {
00094   uint32_t PowerMode;                   /*!< Set comparator operating mode to adjust power and speed.
00095                                              This parameter can be a value of @ref COMP_LL_EC_POWERMODE
00096
00097                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
00098
00099   uint32_t InputPlus;                   /*!< Set comparator input plus (non-inverting input).
00100                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
00101
00102                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
00103
00104   uint32_t InputMinus;                  /*!< Set comparator input minus (inverting input).
00105                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
00106
00107                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
00108
00109   uint32_t InputHysteresis;             /*!< Set comparator hysteresis mode of the input minus.
00110                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
00111
00112                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */
00113
00114   uint32_t OutputSelection;             /*!< Set comparator output selection.
00115                                              This parameter can be a value of @ref COMP_LL_EC_OUTPUT_SELECTION
00116
00117                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputSelection(). */
00118
00119   uint32_t OutputPolarity;              /*!< Set comparator output polarity.
00120                                              This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
00121
00122                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
00123
00124   uint32_t OutputBlankingSource;        /*!< Set comparator blanking source.
00125                                              This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
00126
00127                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */
00128
00129 } LL_COMP_InitTypeDef;
00130
00131 /**
00132   * @}
00133   */
00134 #endif /* USE_FULL_LL_DRIVER */
00135
00136 /* Exported constants --------------------------------------------------------*/
00137 /** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
00138   * @{
00139   */
00140
00141 /** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
00142   * @{
00143   */
00144 #define LL_COMP_WINDOWMODE_DISABLE                 ((uint32_t)0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */
00145 #if defined(COMP2_CSR_COMP2WNDWEN)
00146 #define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP2_CSR_COMP2WNDWEN) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
00147 #endif
00148 #if defined(COMP4_CSR_COMP4WNDWEN)
00149 #define LL_COMP_WINDOWMODE_COMP3_INPUT_PLUS_COMMON (COMP4_CSR_COMP4WNDWEN) /*!< Window mode enable: Comparators instances pair COMP3 and COMP4 have their input plus connected together. The common input is COMP3 input plus (COMP4 input plus is no more accessible). */
00150 #endif
00151 #if defined(COMP6_CSR_COMP6WNDWEN)
00152 #define LL_COMP_WINDOWMODE_COMP5_INPUT_PLUS_COMMON (COMP6_CSR_COMP6WNDWEN) /*!< Window mode enable: Comparators instances pair COMP5 and COMP6 have their input plus connected together. The common input is COMP5 input plus (COMP6 input plus is no more accessible). */
00153 #endif
00154 /**
00155   * @}
00156   */
00157
00158 /** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
00159   * @{
00160   */
00161 #define LL_COMP_POWERMODE_HIGHSPEED     ((uint32_t)0x00000000U)                       /*!< COMP power mode to high speed */
00162 #if defined(COMP_CSR_COMPxMODE)
00163 #define LL_COMP_POWERMODE_MEDIUMSPEED   (COMP_CSR_COMPxMODE_0)                        /*!< COMP power mode to medium speed */
00164 #define LL_COMP_POWERMODE_LOWPOWER      (COMP_CSR_COMPxMODE_1)                        /*!< COMP power mode to low power */
00165 #define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_COMPxMODE_1 | COMP_CSR_COMPxMODE_0) /*!< COMP power mode to ultra-low power */
00166 #endif
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
00172   * @{
00173   */
00174 #if !defined(COMP_CSR_COMPxNONINSEL)
00175 #define LL_COMP_INPUT_PLUS_IO1          ((uint32_t)0x00000000U)  /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, PA3 for COMP2 (except STM32F334xx: PA7), PB14 for COMP3, PB0 for COMP4, PD12 for COMP5, PD11 for COMP6, PA0  for COMP7) (COMP instance availability depends on the selected device) */
00176 #define LL_COMP_INPUT_PLUS_IO2          ((uint32_t)0x00000000U)  /*!< Comparator input plus connected to IO2: Same as IO1 */
00177 #else
00178 #define LL_COMP_INPUT_PLUS_IO1          ((uint32_t)0x00000000U)  /*!< Comparator input plus connected to IO1 (pin PA7 for COMP2, PB14 for COMP3, PB0 for COMP4, PD12 for COMP5, PD11 for COMP6, PA0  for COMP7) (COMP instance availability depends on the selected device) */
00179 #define LL_COMP_INPUT_PLUS_IO2          (COMP_CSR_COMPxNONINSEL) /*!< Comparator input plus connected to IO2 (pin PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5, PB11 for COMP6, PC1 for COMP7) (COMP instance availability depends on the selected device) */
00180 #endif
00181 #if defined(STM32F302xC) || defined(STM32F302xE) || defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F358xx) || defined(STM32F398xx)
00182 #define LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (COMP_CSR_COMPxSW1)    /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch (Note: this switch is solely intended to redirect signals onto high impedance input, such as COMP1 input plus (highly resistive switch)) (specific to COMP instance: COMP1) */
00183
00184 /* Note: Comparator input plus specific to COMP instances, defined with       */
00185 /*       generic naming not taking into account COMP instance constraints.    */
00186 /*       Refer to literal definitions above for COMP instance constraints.    */
00187 #define LL_COMP_INPUT_PLUS_DAC1_CH1     LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1      /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00188
00189 #elif defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F302x8)
00190 #define LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (COMP_CSR_COMPxSW1)    /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch (Note: this switch is solely intended to redirect signals onto high impedance input, such as COMP2 input plus (highly resistive switch)) (specific to COMP instance: COMP2) */
00191
00192 /* Note: Comparator input plus specific to COMP instances, defined with       */
00193 /*       generic naming not taking into account COMP instance constraints.    */
00194 /*       Refer to literal definitions above for COMP instance constraints.    */
00195 #define LL_COMP_INPUT_PLUS_DAC1_CH1     LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2      /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00196
00197 #endif
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
00203   * @{
00204   */
00205 #define LL_COMP_INPUT_MINUS_1_4VREFINT  ((uint32_t)0x00000000U)                                                /*!< Comparator input minus connected to 1/4 VrefInt  */
00206 #define LL_COMP_INPUT_MINUS_1_2VREFINT  (                                               COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt  */
00207 #define LL_COMP_INPUT_MINUS_3_4VREFINT  (                       COMP_CSR_COMPxINSEL_1                        ) /*!< Comparator input minus connected to 3/4 VrefInt  */
00208 #define LL_COMP_INPUT_MINUS_VREFINT     (                       COMP_CSR_COMPxINSEL_1 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to VrefInt */
00209 #define LL_COMP_INPUT_MINUS_DAC1_CH1    (COMP_CSR_COMPxINSEL_2                                               ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)  */
00210 #if defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F302x8) || defined(STM32F302xC) || defined(STM32F302xE)
00211 /* This device has no comparator input minus DAC1_CH2 */
00212 #else
00213 #define LL_COMP_INPUT_MINUS_DAC1_CH2    (COMP_CSR_COMPxINSEL_2                        | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)  */
00214 #endif
00215 #if defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F334x8)
00216 #define LL_COMP_INPUT_MINUS_IO1         (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_1                        ) /*!< Comparator input minus connected to IO1 (pin PA2 for COMP2) */
00217 #else
00218 #define LL_COMP_INPUT_MINUS_IO1         (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_1                        ) /*!< Comparator input minus connected to IO1 (pin PA0 for COMP1, pin PA2 for COMP2, PD15 for COMP3, PE8 for COMP4, PD13 for COMP5, PD10 for COMP6, PC0 for COMP7 (COMP instance availability depends on the selected device)) */
00219 #endif
00220 #define LL_COMP_INPUT_MINUS_IO2         (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_1 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to IO2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5, PB15 for COMP6 (COMP instance availability depends on the selected device)) */
00221 #if defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F334x8) || defined(STM32F302x8) || defined(STM32F303x8) || defined(STM32F328xx)
00222 /* This device has no comparator input minus IO3 */
00223 #else
00224 #define LL_COMP_INPUT_MINUS_IO3         (COMP_CSR_COMPxINSEL_2                         | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to IO3 (pin PA5 for COMP1/2/3/4/5/6/7 (COMP instance availability depends on the selected device)) */
00225 #endif
00226 #define LL_COMP_INPUT_MINUS_IO4         (COMP_CSR_COMPxINSEL_2                                                ) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1/2/3/4/5/6/7 (COMP instance availability depends on the selected device)) */
00227 #if defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8)
00228 #define LL_COMP_INPUT_MINUS_DAC2_CH1    (COMP_CSR_COMPxINSEL_3                                                ) /*!< Comparator input minus connected to DAC2 channel 1 (DAC2_OUT1)  */
00229 #else
00230 /* This device has no comparator input minus DAC2_CH1 */
00231 #endif
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
00237   * @{
00238   */
00239 #define LL_COMP_HYSTERESIS_NONE         ((uint32_t)0x00000000U)                       /*!< No hysteresis */
00240 #if defined(COMP_CSR_COMPxHYST)
00241 #define LL_COMP_HYSTERESIS_LOW          (                       COMP_CSR_COMPxHYST_0) /*!< Hysteresis level low (available only on devices: STM32F303xB/C, STM32F358xC) */
00242 #define LL_COMP_HYSTERESIS_MEDIUM       (COMP_CSR_COMPxHYST_1                       ) /*!< Hysteresis level medium (available only on devices: STM32F303xB/C, STM32F358xC) */
00243 #define LL_COMP_HYSTERESIS_HIGH         (COMP_CSR_COMPxHYST_1 | COMP_CSR_COMPxHYST_0) /*!< Hysteresis level high (available only on devices: STM32F303xB/C, STM32F358xC) */
00244 #endif
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup COMP_LL_EC_OUTPUT_SELECTION Comparator output - Output selection
00250   * @{
00251   */
00252 #define LL_COMP_OUTPUT_NONE             ((uint32_t)0x00000000)                                                      /*!< COMP output is not connected to other peripherals (except GPIO and EXTI that are always connected to COMP output) (specific to COMP instance: COMP2) */
00253 #if defined(COMP_CSR_COMPxOUT)
00254 /* Note: Output redirection common to all COMP instances, all STM32F3 serie   */
00255 /*       devices.                                                             */
00256 #define LL_COMP_OUTPUT_TIM1_BKIN        (COMP_CSR_COMPxOUTSEL_0)                                                    /*!< COMP output connected to TIM1 break input (BKIN) */
00257 #define LL_COMP_OUTPUT_TIM1_BKIN2       (COMP_CSR_COMPxOUTSEL_1)                                                    /*!< COMP output connected to TIM1 break input 2 (BKIN2) */
00258
00259 #if defined(STM32F301x8) || defined(STM32F318xx)
00260 /* Note: Output redirection specific to COMP instance: COMP2 */
00261 #define LL_COMP_OUTPUT_TIM1_IC1_COMP2    (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */
00262 #define LL_COMP_OUTPUT_TIM2_IC4_COMP2    (COMP_CSR_COMPxOUTSEL_3)                                                   /*!< COMP output connected to TIM1 input capture 4 (specific to COMP instance: COMP2) */
00263 #define LL_COMP_OUTPUT_TIM1_OCCLR_COMP2  (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */
00264 #define LL_COMP_OUTPUT_TIM2_OCCLR_COMP2  (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0)                          /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */
00265 /* Note: Output redirection specific to COMP instance: COMP4 */
00266 #define LL_COMP_OUTPUT_TIM15_IC2_COMP4   (COMP_CSR_COMPxOUTSEL_3)                                                   /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */
00267 #define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */
00268 /* Note: Output redirection specific to COMP instance: COMP6 */
00269 #define LL_COMP_OUTPUT_TIM2_IC2_COMP6    (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */
00270 #define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6  (COMP_CSR_COMPxOUTSEL_3)                                                   /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */
00271 #define LL_COMP_OUTPUT_TIM16_IC1_COMP6   (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */
00272 #define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0)                          /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */
00273
00274 /* Note: Output redirection specific to COMP instances, defined with          */
00275 /*       generic naming not taking into account COMP instance constraints.    */
00276 /*       Refer to literal definitions above for COMP instance constraints.    */
00277 /* Note: Some output redirections cannot have a generic naming,               */
00278 /*       due to literal value different depending on COMP instance.           */
00279 /*       (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 and                    */
00280 /*       LL_COMP_OUTPUT_TIM2_OCCLR_COMP6).                                    */
00281 #define LL_COMP_OUTPUT_TIM1_IC1          LL_COMP_OUTPUT_TIM1_IC1_COMP2         /*!< COMP output connected to TIM1 input capture 1.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00282 #define LL_COMP_OUTPUT_TIM1_OCCLR        LL_COMP_OUTPUT_TIM1_OCCLR_COMP2       /*!< COMP output connected to TIM1 OCREF clear.         Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00283 #define LL_COMP_OUTPUT_TIM2_IC2          LL_COMP_OUTPUT_TIM2_IC2_COMP6         /*!< COMP output connected to TIM2 input capture 2.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00284 #define LL_COMP_OUTPUT_TIM2_IC4          LL_COMP_OUTPUT_TIM2_IC4_COMP2         /*!< COMP output connected to TIM2 input capture 4.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00285 #define LL_COMP_OUTPUT_TIM15_IC2         LL_COMP_OUTPUT_TIM15_IC2_COMP4        /*!< COMP output connected to TIM15 input capture 1.    Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00286 #define LL_COMP_OUTPUT_TIM15_OCCLR       LL_COMP_OUTPUT_TIM15_OCCLR_COMP4      /*!< COMP output connected to TIM15 OCREF clear.        Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00287 #define LL_COMP_OUTPUT_TIM16_IC1         LL_COMP_OUTPUT_TIM16_IC1_COMP6        /*!< COMP output connected to TIM16 input capture 1.    Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00288 #define LL_COMP_OUTPUT_TIM16_OCCLR       LL_COMP_OUTPUT_TIM16_OCCLR_COMP6      /*!< COMP output connected to TIM16 OCREF clear.        Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00289 /* Note: Output redirection specific to COMP instances, defined with          */
00290 /*       partially generic naming grouping COMP instance constraints.         */
00291 /*       Refer to literal definitions above for COMP instance constraints.    */
00292 #define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3  LL_COMP_OUTPUT_TIM2_OCCLR_COMP2   /*!< COMP output connected to TIM2 OCREF clear.         Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00293
00294 #elif defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8)|| defined(STM32F302x8)
00295 /* Note: Output redirection specific to COMP instance: COMP2, COMP4 */
00296 #define LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP2, COMP4) */
00297 /* Note: Output redirection specific to COMP instance: COMP2 */
00298 #define LL_COMP_OUTPUT_TIM1_IC1_COMP2    (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */
00299 #define LL_COMP_OUTPUT_TIM2_IC4_COMP2    (COMP_CSR_COMPxOUTSEL_3)                                                   /*!< COMP output connected to TIM1 input capture 4 (specific to COMP instance: COMP2) */
00300 #define LL_COMP_OUTPUT_TIM1_OCCLR_COMP2  (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */
00301 #define LL_COMP_OUTPUT_TIM2_OCCLR_COMP2  (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0)                          /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */
00302 #define LL_COMP_OUTPUT_TIM3_IC1_COMP2    (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
00303 /* Note: Output redirection specific to COMP instance: COMP4 */
00304 #define LL_COMP_OUTPUT_TIM3_IC3_COMP4    (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */
00305 #define LL_COMP_OUTPUT_TIM15_IC2_COMP4   (COMP_CSR_COMPxOUTSEL_3)                                                   /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */
00306 #define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */
00307 /* Note: Output redirection specific to COMP instance: COMP6 */
00308 #define LL_COMP_OUTPUT_TIM2_IC2_COMP6    (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */
00309 #define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6  (COMP_CSR_COMPxOUTSEL_3)                                                   /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */
00310 #define LL_COMP_OUTPUT_TIM16_IC1_COMP6   (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */
00311 #define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0)                          /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */
00312
00313 /* Note: Output redirection specific to COMP instances, defined with          */
00314 /*       generic naming not taking into account COMP instance constraints.    */
00315 /*       Refer to literal definitions above for COMP instance constraints.    */
00316 /* Note: Some output redirections cannot have a generic naming,               */
00317 /*       due to literal value different depending on COMP instance.           */
00318 /*       (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 and                    */
00319 /*       LL_COMP_OUTPUT_TIM2_OCCLR_COMP6).                                    */
00320 #define LL_COMP_OUTPUT_TIM1_IC1          LL_COMP_OUTPUT_TIM1_IC1_COMP2         /*!< COMP output connected to TIM1 input capture 1.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00321 #define LL_COMP_OUTPUT_TIM1_OCCLR        LL_COMP_OUTPUT_TIM1_OCCLR_COMP2       /*!< COMP output connected to TIM1 OCREF clear.         Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00322 #define LL_COMP_OUTPUT_TIM2_IC2          LL_COMP_OUTPUT_TIM2_IC2_COMP6         /*!< COMP output connected to TIM2 input capture 2.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00323 #define LL_COMP_OUTPUT_TIM2_IC4          LL_COMP_OUTPUT_TIM2_IC4_COMP2         /*!< COMP output connected to TIM2 input capture 4.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00324 #define LL_COMP_OUTPUT_TIM3_IC1          LL_COMP_OUTPUT_TIM3_IC1_COMP2         /*!< COMP output connected to TIM3 input capture 1.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00325 #define LL_COMP_OUTPUT_TIM3_IC3          LL_COMP_OUTPUT_TIM3_IC3_COMP4         /*!< COMP output connected to TIM3 input capture 3.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00326 #define LL_COMP_OUTPUT_TIM3_OCCLR        LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4     /*!< COMP output connected to TIM3 OCREF clear.         Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00327 #define LL_COMP_OUTPUT_TIM15_IC2         LL_COMP_OUTPUT_TIM15_IC2_COMP4        /*!< COMP output connected to TIM15 input capture 1.    Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00328 #define LL_COMP_OUTPUT_TIM15_OCCLR       LL_COMP_OUTPUT_TIM15_OCCLR_COMP4      /*!< COMP output connected to TIM15 OCREF clear.        Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00329 #define LL_COMP_OUTPUT_TIM16_IC1         LL_COMP_OUTPUT_TIM16_IC1_COMP6        /*!< COMP output connected to TIM16 input capture 1.    Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00330 #define LL_COMP_OUTPUT_TIM16_OCCLR       LL_COMP_OUTPUT_TIM16_OCCLR_COMP6      /*!< COMP output connected to TIM16 OCREF clear.        Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00331 /* Note: Output redirection specific to COMP instances, defined with          */
00332 /*       partially generic naming grouping COMP instance constraints.         */
00333 /*       Refer to literal definitions above for COMP instance constraints.    */
00334 #define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3  LL_COMP_OUTPUT_TIM2_OCCLR_COMP2   /*!< COMP output connected to TIM2 OCREF clear.         Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00335
00336 #elif defined(STM32F302xC) || defined(STM32F302xE)
00337 /* Note: Output redirection specific to COMP instance: COMP1, COMP2, COMP4 */
00338 #define LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP2, COMP4) */
00339 /* Note: Output redirection specific to COMP instance: COMP1, COMP2 */
00340 #define LL_COMP_OUTPUT_TIM1_IC1_COMP1_2    (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */
00341 #define LL_COMP_OUTPUT_TIM2_IC4_COMP1_2    (COMP_CSR_COMPxOUTSEL_3)                                                   /*!< COMP output connected to TIM2 input capture 4 (specific to COMP instance: COMP2) */
00342 #define LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2  (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */
00343 #define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2  (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0)                          /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */
00344 #define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2    (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
00345 /* Note: Output redirection specific to COMP instance: COMP4 */
00346 #define LL_COMP_OUTPUT_TIM3_IC3_COMP4      (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */
00347 #define LL_COMP_OUTPUT_TIM4_IC2_COMP4      (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0)                          /*!< COMP output connected to TIM4 input capture 2 (specific to COMP instance: COMP4) */
00348 #define LL_COMP_OUTPUT_TIM15_IC2_COMP4     (COMP_CSR_COMPxOUTSEL_3)                                                   /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */
00349 #define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4   (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */
00350 /* Note: Output redirection specific to COMP instance: COMP6 */
00351 #define LL_COMP_OUTPUT_TIM2_IC2_COMP6      (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */
00352 #define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6    (COMP_CSR_COMPxOUTSEL_3)                                                   /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */
00353 #define LL_COMP_OUTPUT_TIM4_IC4_COMP6      (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 4 (specific to COMP instance: COMP6) */
00354 #define LL_COMP_OUTPUT_TIM16_IC1_COMP6     (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */
00355 #define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6   (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */
00356
00357 /* Note: Output redirection specific to COMP instances, defined with          */
00358 /*       generic naming not taking into account COMP instance constraints.    */
00359 /*       Refer to literal definitions above for COMP instance constraints.    */
00360 /* Note: Some output redirections cannot have a generic naming,               */
00361 /*       due to literal value different depending on COMP instance.           */
00362 /*       (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 and                  */
00363 /*       LL_COMP_OUTPUT_TIM2_OCCLR_COMP6).                                    */
00364 #define LL_COMP_OUTPUT_TIM1_IC1          LL_COMP_OUTPUT_TIM1_IC1_COMP1_2       /*!< COMP output connected to TIM1 input capture 1.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00365 #define LL_COMP_OUTPUT_TIM1_OCCLR        LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2     /*!< COMP output connected to TIM1 OCREF clear.         Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00366 #define LL_COMP_OUTPUT_TIM2_IC2          LL_COMP_OUTPUT_TIM2_IC2_COMP6         /*!< COMP output connected to TIM2 input capture 2.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00367 #define LL_COMP_OUTPUT_TIM2_IC4          LL_COMP_OUTPUT_TIM2_IC4_COMP1_2       /*!< COMP output connected to TIM2 input capture 4.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00368 #define LL_COMP_OUTPUT_TIM3_IC1          LL_COMP_OUTPUT_TIM3_IC1_COMP1_2       /*!< COMP output connected to TIM3 input capture 1.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00369 #define LL_COMP_OUTPUT_TIM3_IC3          LL_COMP_OUTPUT_TIM3_IC3_COMP4         /*!< COMP output connected to TIM3 input capture 3.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00370 #define LL_COMP_OUTPUT_TIM3_OCCLR        LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4   /*!< COMP output connected to TIM3 OCREF clear.         Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00371 #define LL_COMP_OUTPUT_TIM4_IC2          LL_COMP_OUTPUT_TIM4_IC2_COMP4         /*!< COMP output connected to TIM4 input capture 2.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00372 #define LL_COMP_OUTPUT_TIM4_IC4          LL_COMP_OUTPUT_TIM4_IC4_COMP6         /*!< COMP output connected to TIM4 input capture 4.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00373 #define LL_COMP_OUTPUT_TIM15_IC2         LL_COMP_OUTPUT_TIM15_IC2_COMP4        /*!< COMP output connected to TIM15 input capture 1.    Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00374 #define LL_COMP_OUTPUT_TIM15_OCCLR       LL_COMP_OUTPUT_TIM15_OCCLR_COMP4      /*!< COMP output connected to TIM15 OCREF clear.        Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00375 #define LL_COMP_OUTPUT_TIM16_IC1         LL_COMP_OUTPUT_TIM16_IC1_COMP6        /*!< COMP output connected to TIM16 input capture 1.    Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00376 #define LL_COMP_OUTPUT_TIM16_OCCLR       LL_COMP_OUTPUT_TIM16_OCCLR_COMP6      /*!< COMP output connected to TIM16 OCREF clear.        Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00377 /* Note: Output redirection specific to COMP instances, defined with          */
00378 /*       partially generic naming grouping COMP instance constraints.         */
00379 /*       Refer to literal definitions above for COMP instance constraints.    */
00380 #define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3  LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2   /*!< COMP output connected to TIM2 OCREF clear.         Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00381
00382 #elif defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
00383 /* Note: Output redirection common to all COMP instances */
00384 #define LL_COMP_OUTPUT_TIM8_BKIN         (COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0)                          /*!< COMP output connected to TIM8 break input (BKIN) */
00385 #define LL_COMP_OUTPUT_TIM8_BKIN2        (COMP_CSR_COMPxOUTSEL_2)                                                   /*!< COMP output connected to TIM8 break input 2 (BKIN2) */
00386 #define LL_COMP_OUTPUT_TIM1_TIM8_BKIN2   (COMP_CSR_COMPxOUTSEL_2| COMP_CSR_COMPxOUTSEL_0)                           /*!< COMP output connected to TIM1 break input 2 and TIM8 break input 2 (BKIN2) */
00387 #if defined(STM32F303xE) || defined(STM32F398xx)
00388 #define LL_COMP_OUTPUT_TIM20_BKIN        (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2)                          /*!< COMP output connected to TIM8 break input (BKIN) */
00389 #define LL_COMP_OUTPUT_TIM20_BKIN2       (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM8 break input 2 (BKIN2) */
00390 #define LL_COMP_OUTPUT_TIM1_TIM8_TIM20_BKIN2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2| COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 break input 2, TIM8 break input 2 and TIM20 break input 2 (BKIN2) */
00391 #endif
00392 /* Note: Output redirection specific to COMP instance: COMP1, COMP2, COMP3, COMP7 */
00393 #define LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP1, COMP2, COMP3, COMP7) */
00394 /* Note: Output redirection specific to COMP instance: COMP1, COMP2, COMP3 */
00395 #define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0)                          /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP1, COMP2, COMP3) */
00396 /* Note: Output redirection specific to COMP instance: COMP1, COMP2, COMP4, COMP5 */
00397 #define LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP1, COMP2, COMP4, COMP5) */
00398 /* Note: Output redirection specific to COMP instance: COMP4, COMP5, COMP6, COMP7 */
00399 #define LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM8 OCREF clear (specific to COMP instance: COMP4, COMP5, COMP6, COMP7) */
00400 /* Note: Output redirection specific to COMP instance: COMP1, COMP2 */
00401 #define LL_COMP_OUTPUT_TIM1_IC1_COMP1_2  (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */
00402 #define LL_COMP_OUTPUT_TIM2_IC4_COMP1_2  (COMP_CSR_COMPxOUTSEL_3)                                                   /*!< COMP output connected to TIM2 input capture 4 (specific to COMP instance: COMP2) */
00403 #define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2  (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
00404 #if defined(STM32F303xE) || defined(STM32F398xx)
00405 #define LL_COMP_OUTPUT_TIM20_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM20 OCREF clear (specific to COMP instance: COMP2) */
00406 #endif
00407 /* Note: Output redirection specific to COMP instance: COMP3 */
00408 #define LL_COMP_OUTPUT_TIM3_IC2_COMP3    (COMP_CSR_COMPxOUTSEL_3)                                                   /*!< COMP output connected to TIM3 input capture 2 (specific to COMP instance: COMP3) */
00409 #define LL_COMP_OUTPUT_TIM4_IC1_COMP3    (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 1 (specific to COMP instance: COMP3) */
00410 #define LL_COMP_OUTPUT_TIM15_IC1_COMP3   (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP3) */
00411 #define LL_COMP_OUTPUT_TIM15_BKIN_COMP3  (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM15 break input (BKIN) */
00412 /* Note: Output redirection specific to COMP instance: COMP4 */
00413 #define LL_COMP_OUTPUT_TIM3_IC3_COMP4    (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */
00414 #define LL_COMP_OUTPUT_TIM4_IC2_COMP4    (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0)                          /*!< COMP output connected to TIM4 input capture 2 (specific to COMP instance: COMP4) */
00415 #define LL_COMP_OUTPUT_TIM15_IC2_COMP4   (COMP_CSR_COMPxOUTSEL_3)                                                   /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */
00416 #define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */
00417 /* Note: Output redirection specific to COMP instance: COMP5 */
00418 #define LL_COMP_OUTPUT_TIM2_IC1_COMP5    (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM2 input capture 1 (specific to COMP instance: COMP5) */
00419 #define LL_COMP_OUTPUT_TIM4_IC3_COMP5    (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0)                          /*!< COMP output connected to TIM4 input capture 3 (specific to COMP instance: COMP5) */
00420 #define LL_COMP_OUTPUT_TIM17_IC1_COMP5   (COMP_CSR_COMPxOUTSEL_3)                                                   /*!< COMP output connected to TIM17 input capture 1 (specific to COMP instance: COMP5) */
00421 #define LL_COMP_OUTPUT_TIM16_BKIN_COMP5  (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM16 break input (BKIN) */
00422 /* Note: Output redirection specific to COMP instance: COMP6 */
00423 #define LL_COMP_OUTPUT_TIM2_IC2_COMP6    (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */
00424 #define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6  (COMP_CSR_COMPxOUTSEL_3)                                                   /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */
00425 #define LL_COMP_OUTPUT_TIM4_IC4_COMP6    (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 4 (specific to COMP instance: COMP6) */
00426 #define LL_COMP_OUTPUT_TIM16_IC1_COMP6   (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */
00427 #define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */
00428 /* Note: Output redirection specific to COMP instance: COMP7 */
00429 #define LL_COMP_OUTPUT_TIM1_IC2_COMP7    (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0)                          /*!< COMP output connected to TIM2 input capture 1 (specific to COMP instance: COMP7) */
00430 #define LL_COMP_OUTPUT_TIM2_IC3_COMP7    (COMP_CSR_COMPxOUTSEL_3)                                                   /*!< COMP output connected to TIM4 input capture 3 (specific to COMP instance: COMP7) */
00431 #define LL_COMP_OUTPUT_TIM17_OCCLR_COMP7 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1)                          /*!< COMP output connected to TIM17 OCREF clear (specific to COMP instance: COMP7) */
00432 #define LL_COMP_OUTPUT_TIM17_BKIN_COMP7  (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM17 break input (BKIN) */
00433
00434 /* Note: Output redirection specific to COMP instances, defined with          */
00435 /*       generic naming not taking into account COMP instance constraints.    */
00436 /*       Refer to literal definitions above for COMP instance constraints.    */
00437 /* Note: Some output redirections cannot have a generic naming,               */
00438 /*       due to literal value different depending on COMP instance.           */
00439 /*       (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 and                */
00440 /*       LL_COMP_OUTPUT_TIM2_OCCLR_COMP6).                                    */
00441 #define LL_COMP_OUTPUT_TIM1_IC1          LL_COMP_OUTPUT_TIM1_IC1_COMP1_2       /*!< COMP output connected to TIM1 input capture 1.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00442 #define LL_COMP_OUTPUT_TIM1_IC2          LL_COMP_OUTPUT_TIM1_IC2_COMP7         /*!< COMP output connected to TIM2 input capture 1.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00443 #define LL_COMP_OUTPUT_TIM1_OCCLR        LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7 /*!< COMP output connected to TIM1 OCREF clear.         Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00444 #define LL_COMP_OUTPUT_TIM2_IC1          LL_COMP_OUTPUT_TIM2_IC1_COMP5         /*!< COMP output connected to TIM2 input capture 1.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00445 #define LL_COMP_OUTPUT_TIM2_IC2          LL_COMP_OUTPUT_TIM2_IC2_COMP6         /*!< COMP output connected to TIM2 input capture 2.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00446 #define LL_COMP_OUTPUT_TIM2_IC3          LL_COMP_OUTPUT_TIM2_IC3_COMP7         /*!< COMP output connected to TIM4 input capture 3.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00447 #define LL_COMP_OUTPUT_TIM2_IC4          LL_COMP_OUTPUT_TIM2_IC4_COMP1_2       /*!< COMP output connected to TIM2 input capture 4.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00448 #define LL_COMP_OUTPUT_TIM3_IC1          LL_COMP_OUTPUT_TIM3_IC1_COMP1_2       /*!< COMP output connected to TIM3 input capture 1.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00449 #define LL_COMP_OUTPUT_TIM3_IC2          LL_COMP_OUTPUT_TIM3_IC2_COMP3         /*!< COMP output connected to TIM3 input capture 2.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00450 #define LL_COMP_OUTPUT_TIM3_IC3          LL_COMP_OUTPUT_TIM3_IC3_COMP4         /*!< COMP output connected to TIM3 input capture 3.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00451 #define LL_COMP_OUTPUT_TIM3_OCCLR        LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5 /*!< COMP output connected to TIM3 OCREF clear.         Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00452 #define LL_COMP_OUTPUT_TIM4_IC1          LL_COMP_OUTPUT_TIM4_IC1_COMP3         /*!< COMP output connected to TIM4 input capture 1.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00453 #define LL_COMP_OUTPUT_TIM4_IC2          LL_COMP_OUTPUT_TIM4_IC2_COMP4         /*!< COMP output connected to TIM4 input capture 2.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00454 #define LL_COMP_OUTPUT_TIM4_IC3          LL_COMP_OUTPUT_TIM4_IC3_COMP5         /*!< COMP output connected to TIM4 input capture 3.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00455 #define LL_COMP_OUTPUT_TIM4_IC4          LL_COMP_OUTPUT_TIM4_IC4_COMP6         /*!< COMP output connected to TIM4 input capture 4.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00456 #define LL_COMP_OUTPUT_TIM8_OCCLR        LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 /*!< COMP output connected to TIM8 OCREF clear.         Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00457 #define LL_COMP_OUTPUT_TIM15_IC1         LL_COMP_OUTPUT_TIM15_IC1_COMP3        /*!< COMP output connected to TIM15 input capture 1.    Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00458 #define LL_COMP_OUTPUT_TIM15_IC2         LL_COMP_OUTPUT_TIM15_IC2_COMP4        /*!< COMP output connected to TIM15 input capture 1.    Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00459 #define LL_COMP_OUTPUT_TIM15_BKIN        LL_COMP_OUTPUT_TIM15_BKIN_COMP3       /*!< COMP output connected to TIM15 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00460 #define LL_COMP_OUTPUT_TIM15_OCCLR       LL_COMP_OUTPUT_TIM15_OCCLR_COMP4      /*!< COMP output connected to TIM15 OCREF clear.        Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00461 #define LL_COMP_OUTPUT_TIM16_IC1         LL_COMP_OUTPUT_TIM16_IC1_COMP6        /*!< COMP output connected to TIM16 input capture 1.    Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00462 #define LL_COMP_OUTPUT_TIM16_BKIN        LL_COMP_OUTPUT_TIM16_BKIN_COMP5       /*!< COMP output connected to TIM16 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00463 #define LL_COMP_OUTPUT_TIM16_OCCLR       LL_COMP_OUTPUT_TIM16_OCCLR_COMP6      /*!< COMP output connected to TIM16 OCREF clear.        Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00464 #define LL_COMP_OUTPUT_TIM17_IC1         LL_COMP_OUTPUT_TIM17_IC1_COMP5        /*!< COMP output connected to TIM17 input capture 1.    Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00465 #define LL_COMP_OUTPUT_TIM17_BKIN        LL_COMP_OUTPUT_TIM17_BKIN_COMP7       /*!< COMP output connected to TIM17 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00466 #define LL_COMP_OUTPUT_TIM17_OCCLR       LL_COMP_OUTPUT_TIM17_OCCLR_COMP7      /*!< COMP output connected to TIM17 OCREF clear.        Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00467 #if defined(STM32F303xE) || defined(STM32F398xx)
00468 #define LL_COMP_OUTPUT_TIM20_OCCLR       LL_COMP_OUTPUT_TIM20_OCCLR_COMP2      /*!< COMP output connected to TIM20 OCREF clear.        Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00469 #endif
00470
00471 #endif
00472 #endif
00473 /**
00474   * @}
00475   */
00476
00477 /** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
00478   * @{
00479   */
00480 #define LL_COMP_OUTPUTPOL_NONINVERTED   ((uint32_t)0x00000000U) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
00481 #define LL_COMP_OUTPUTPOL_INVERTED      (COMP_CSR_COMPxPOL)     /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
00482 /**
00483   * @}
00484   */
00485
00486 /** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source
00487   * @{
00488   */
00489 #define LL_COMP_BLANKINGSRC_NONE        ((uint32_t)0x00000000U)                                   /*!<Comparator output without blanking */
00490 #if defined(COMP_CSR_COMPxBLANKING)
00491 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
00492 /* Note: Output blanking source specific to COMP instance: COMP2 */
00493 #define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2  (COMP_CSR_COMPxBLANKING_0)                            /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP2) */
00494 #define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2  (COMP_CSR_COMPxBLANKING_1)                            /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP2) */
00495 #define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2  (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP2) */
00496 /* Note: Output blanking source specific to COMP instance: COMP4 */
00497 #define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4  (COMP_CSR_COMPxBLANKING_0)                            /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4) */
00498 #define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 (COMP_CSR_COMPxBLANKING_0 | COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4) */
00499 /* Note: Output blanking source specific to COMP instance: COMP6 */
00500 #define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6  (COMP_CSR_COMPxBLANKING_0 | COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6) */
00501 #define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 (COMP_CSR_COMPxBLANKING_0)                            /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6) */
00502
00503 /* Note: Output blanking source specific to COMP instances, defined with      */
00504 /*       generic naming not taking into account COMP instance constraints.    */
00505 /*       Refer to literal definitions above for COMP instance constraints.    */
00506 #define LL_COMP_BLANKINGSRC_TIM1_OC5     LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2                        /*!< Comparator output blanking source TIM1 OC5.  Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00507 #define LL_COMP_BLANKINGSRC_TIM2_OC3     LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2                        /*!< Comparator output blanking source TIM2 OC3.  Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00508 #define LL_COMP_BLANKINGSRC_TIM2_OC4     LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6                        /*!< Comparator output blanking source TIM2 OC4.  Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00509 #define LL_COMP_BLANKINGSRC_TIM3_OC3     LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2                        /*!< Comparator output blanking source TIM3 OC3.  Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00510 #define LL_COMP_BLANKINGSRC_TIM3_OC4     LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4                        /*!< Comparator output blanking source TIM3 OC4.  Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00511 #define LL_COMP_BLANKINGSRC_TIM15_OC1    LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4                       /*!< Comparator output blanking source TIM15 OC1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00512 #define LL_COMP_BLANKINGSRC_TIM15_OC2    LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6                       /*!< Comparator output blanking source TIM15 OC2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00513
00514 #elif defined(STM32F302xE) || defined(STM32F302xC)
00515 /* Note: Output blanking source specific to COMP instance: COMP1, COMP2 */
00516 #define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2 (COMP_CSR_COMPxBLANKING_0)                            /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1, COMP2) */
00517 #define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 (COMP_CSR_COMPxBLANKING_1)                            /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1, COMP2) */
00518 #define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1, COMP2) */
00519 /* Note: Output blanking source specific to COMP instance: COMP4 */
00520 #define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4  (COMP_CSR_COMPxBLANKING_0)                             /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4) */
00521 #define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 (COMP_CSR_COMPxBLANKING_0 | COMP_CSR_COMPxBLANKING_1)  /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4) */
00522 /* Note: Output blanking source specific to COMP instance: COMP6 */
00523 #define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6  (COMP_CSR_COMPxBLANKING_0 | COMP_CSR_COMPxBLANKING_1)  /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6) */
00524 #define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 (COMP_CSR_COMPxBLANKING_0)                             /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6) */
00525
00526 /* Note: Output blanking source specific to COMP instances, defined with      */
00527 /*       generic naming not taking into account COMP instance constraints.    */
00528 /*       Refer to literal definitions above for COMP instance constraints.    */
00529 #define LL_COMP_BLANKINGSRC_TIM1_OC5     LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2                      /*!< Comparator output blanking source TIM1 OC5.  Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00530 #define LL_COMP_BLANKINGSRC_TIM2_OC3     LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2                      /*!< Comparator output blanking source TIM2 OC3.  Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00531 #define LL_COMP_BLANKINGSRC_TIM2_OC4     LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6                        /*!< Comparator output blanking source TIM2 OC4.  Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00532 #define LL_COMP_BLANKINGSRC_TIM3_OC3     LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2                      /*!< Comparator output blanking source TIM3 OC3.  Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00533 #define LL_COMP_BLANKINGSRC_TIM3_OC4     LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4                        /*!< Comparator output blanking source TIM3 OC4.  Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00534 #define LL_COMP_BLANKINGSRC_TIM15_OC1    LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4                       /*!< Comparator output blanking source TIM15 OC1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00535 #define LL_COMP_BLANKINGSRC_TIM15_OC2    LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6                       /*!< Comparator output blanking source TIM15 OC2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00536
00537 #elif defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
00538 /* Note: Output blanking source specific to COMP instance: COMP1, COMP2, COMP7 */
00539 #define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7 (COMP_CSR_COMPxBLANKING_0)                          /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1, COMP2, COMP7) */
00540 /* Note: Output blanking source specific to COMP instance: COMP1, COMP2 */
00541 #define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 (COMP_CSR_COMPxBLANKING_1)                            /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1, COMP2) */
00542 #define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1, COMP2) */
00543 /* Note: Output blanking source specific to COMP instance: COMP3, COMP6 */
00544 #define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6 (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP3, COMP6) */
00545 /* Note: Output blanking source specific to COMP instance: COMP4, COMP5, COMP6, COMP7 */
00546 #define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7 (COMP_CSR_COMPxBLANKING_1)                        /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP4, COMP5, COMP6, COMP7) */
00547 /* Note: Output blanling source specific to COMP instance: COMP6, COMP7 */
00548 #define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7 (COMP_CSR_COMPxBLANKING_2)                           /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6, COMP7) */
00549 /* Note: Output blanking source specific to COMP instance: COMP4 */
00550 #define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4   (COMP_CSR_COMPxBLANKING_0)                            /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4) */
00551 #define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4  (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4) */
00552
00553 /* Note: Output blanking source specific to COMP instances, defined with      */
00554 /*       generic naming not taking into account COMP instance constraints.    */
00555 /*       Refer to literal definitions above for COMP instance constraints.    */
00556 #define LL_COMP_BLANKINGSRC_TIM1_OC5     LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7                    /*!< Comparator output blanking source TIM1 OC5.  Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00557 #define LL_COMP_BLANKINGSRC_TIM2_OC3     LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2                      /*!< Comparator output blanking source TIM2 OC3.  Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00558 #define LL_COMP_BLANKINGSRC_TIM2_OC4     LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6                      /*!< Comparator output blanking source TIM2 OC4.  Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00559 #define LL_COMP_BLANKINGSRC_TIM3_OC3     LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2                      /*!< Comparator output blanking source TIM3 OC3.  Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00560 #define LL_COMP_BLANKINGSRC_TIM3_OC4     LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4                        /*!< Comparator output blanking source TIM3 OC4.  Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00561 #define LL_COMP_BLANKINGSRC_TIM8_OC5     LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7                  /*!< Comparator output blanking source TIM8 OC5.  Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00562 #define LL_COMP_BLANKINGSRC_TIM15_OC1    LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4                       /*!< Comparator output blanking source TIM15 OC1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00563 #define LL_COMP_BLANKINGSRC_TIM15_OC2    LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7                     /*!< Comparator output blanking source TIM15 OC2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
00564
00565 #endif
00566 #endif
00567 /**
00568   * @}
00569   */
00570
00571 /** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
00572   * @{
00573   */
00574 #define LL_COMP_OUTPUT_LEVEL_LOW        ((uint32_t)0x00000000U) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
00575 #define LL_COMP_OUTPUT_LEVEL_HIGH       ((uint32_t)0x00000001U) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
00576 /**
00577   * @}
00578   */
00579
00580 /** @defgroup COMP_LL_EC_HW_DELAYS  Definitions of COMP hardware constraints delays
00581   * @note   Only COMP IP HW delays are defined in COMP LL driver driver,
00582   *         not timeout values.
00583   *         For details on delays values, refer to descriptions in source code
00584   *         above each literal definition.
00585   * @{
00586   */
00587
00588 /* Delay for comparator startup time.                                         */
00589 /* Note: Delay required to reach propagation delay specification.             */
00590 /* Literal set to maximum value (refer to device datasheet,                   */
00591 /* parameter "tSTART").                                                       */
00592 /* Unit: us                                                                   */
00593 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
00594 #define LL_COMP_DELAY_STARTUP_US          ((uint32_t) 60U)  /*!< Delay for COMP startup time */
00595 #else
00596 #define LL_COMP_DELAY_STARTUP_US          ((uint32_t) 10U)  /*!< Delay for COMP startup time */
00597 #endif
00598
00599 /* Delay for comparator voltage scaler stabilization time.                    */
00600 /* Note: Voltage scaler is used when selecting comparator input               */
00601 /*       based on VrefInt: VrefInt or subdivision of VrefInt.                 */
00602 /* Literal set to maximum value (refer to device datasheet,                   */
00603 /* parameter "tS_SC").                                                        */
00604 /* Unit: us                                                                   */
00605 #define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)  /*!< Delay for COMP voltage scaler stabilization time */
00606
00607 /**
00608   * @}
00609   */
00610
00611 /**
00612   * @}
00613   */
00614
00615 /* Exported macro ------------------------------------------------------------*/
00616 /** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
00617   * @{
00618   */
00619 /** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
00620   * @{
00621   */
00622
00623 /**
00624   * @brief  Write a value in COMP register
00625   * @param  __INSTANCE__ comparator instance
00626   * @param  __REG__ Register to be written
00627   * @param  __VALUE__ Value to be written in the register
00628   * @retval None
00629   */
00630 #define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00631
00632 /**
00633   * @brief  Read a value in COMP register
00634   * @param  __INSTANCE__ comparator instance
00635   * @param  __REG__ Register to be read
00636   * @retval Register value
00637   */
00638 #define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00639 /**
00640   * @}
00641   */
00642
00643 /** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
00644   * @{
00645   */
00646
00647 /**
00648   * @brief  Helper macro to select the COMP common instance
00649   *         to which is belonging the selected COMP instance.
00650   * @note   COMP common register instance can be used to
00651   *         set parameters common to several COMP instances.
00652   *         Refer to functions having argument "COMPxy_COMMON" as parameter.
00653   * @param  __COMPx__ COMP instance
00654   * @retval COMP common instance or value "0" if there is no COMP common instance.
00655   */
00656 #if defined(COMP1) && defined(COMP2) && defined(COMP3) && defined(COMP4) && defined(COMP5) && defined(COMP6) && defined(COMP7)
00657 /* Note: On STM32F3 serie devices with 7 comparator instances,                */
00658 /*       COMP instance COMP7 has no other comparator instance to work         */
00659 /*       in pair with: window mode is not available for COMP7.                */
00660 #define __LL_COMP_COMMON_INSTANCE(__COMPx__)                                   \
00661   ((((__COMPx__) == COMP1) || ((__COMPx__) == COMP2))                          \
00662     ? (                                                                        \
00663        (COMP12_COMMON)                                                         \
00664       )                                                                        \
00665       :                                                                        \
00666       ((((__COMPx__) == COMP3) || ((__COMPx__) == COMP4))                      \
00667         ? (                                                                    \
00668            (COMP34_COMMON)                                                     \
00669           )                                                                    \
00670           :                                                                    \
00671           ((((__COMPx__) == COMP5) || ((__COMPx__) == COMP6))                  \
00672             ? (                                                                \
00673                (COMP56_COMMON)                                                 \
00674               )                                                                \
00675               :                                                                \
00676               (                                                                \
00677                ((uint32_t)0U)                                                  \
00678               )                                                                \
00679           )                                                                    \
00680       )                                                                        \
00681   )
00682 #elif defined(COMP1) && defined(COMP2) && defined(COMP4) && defined(COMP6)
00683 #define __LL_COMP_COMMON_INSTANCE(__COMPx__)                                   \
00684   ((((__COMPx__) == COMP1) || ((__COMPx__) == COMP2))                          \
00685     ? (                                                                        \
00686        (COMP12_COMMON)                                                         \
00687       )                                                                        \
00688       :                                                                        \
00689       (                                                                        \
00690        ((uint32_t)0U)                                                          \
00691       )                                                                        \
00692   )
00693 #elif defined(COMP2) && defined(COMP4) && defined(COMP6)
00694 /* Note: On STM32F3 serie devices with 3 comparator instances (COMP2, 4, 6)   */
00695 /*       COMP instances have no other comparator instance to work             */
00696 /*       in pair with: window mode is not available for all COMP instances.   */
00697 #define __LL_COMP_COMMON_INSTANCE(__COMPx__)                                   \
00698   ((uint32_t)0U)
00699 #endif
00700
00701 /**
00702   * @}
00703   */
00704
00705 /**
00706   * @}
00707   */
00708
00709 /* Exported functions --------------------------------------------------------*/
00710 /** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
00711   * @{
00712   */
00713
00714 /** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances
00715   * @{
00716   */
00717
00718 /**
00719   * @brief  Set window mode of a pair of comparators instances
00720   *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
00721   * @rmtoll CSR      COMPxWNDWEN    LL_COMP_SetCommonWindowMode
00722   * @param  COMPxy_COMMON Comparator common instance
00723   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
00724   * @param  WindowMode This parameter can be one of the following values:
00725   *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
00726   *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (1)
00727   *         @arg @ref LL_COMP_WINDOWMODE_COMP3_INPUT_PLUS_COMMON (2)
00728   *         @arg @ref LL_COMP_WINDOWMODE_COMP5_INPUT_PLUS_COMMON (2)
00729   *
00730   *         (1) Parameter available on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
00731   *         (2) Parameter available on devices: STM32F303xB/C, STM32F358xC
00732   * @retval None
00733   */
00734 __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
00735 {
00736 #if defined(COMP_CSR_COMPxWNDWEN)
00737   MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_COMPxWNDWEN, WindowMode);
00738 #else
00739   /* Device without pair of comparator working in window mode */
00740   /* No update of comparator register (corresponds to setting                 */
00741   /* "LL_COMP_WINDOWMODE_DISABLE").                                           */
00742 #endif
00743 }
00744
00745 /**
00746   * @brief  Get window mode of a pair of comparators instances
00747   *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
00748   * @rmtoll CSR      COMPxWNDWEN    LL_COMP_GetCommonWindowMode
00749   * @param  COMPxy_COMMON Comparator common instance
00750   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
00751   * @retval Returned value can be one of the following values:
00752   *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
00753   *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (1)
00754   *         @arg @ref LL_COMP_WINDOWMODE_COMP3_INPUT_PLUS_COMMON (2)
00755   *         @arg @ref LL_COMP_WINDOWMODE_COMP5_INPUT_PLUS_COMMON (2)
00756   *
00757   *         (1) Parameter available on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
00758   *         (2) Parameter available on devices: STM32F303xB/C, STM32F358xC
00759   */
00760 __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
00761 {
00762 #if defined(COMP_CSR_COMPxWNDWEN)
00763   return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_COMPxWNDWEN));
00764 #else
00765   /* Device without pair of comparator working in window mode */
00766   return (LL_COMP_WINDOWMODE_DISABLE);
00767 #endif
00768 }
00769
00770 /**
00771   * @}
00772   */
00773
00774 /** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
00775   * @{
00776   */
00777
00778 /**
00779   * @brief  Set comparator instance operating mode to adjust power and speed.
00780   * @rmtoll CSR      COMPxMODE      LL_COMP_SetPowerMode
00781   * @param  COMPx Comparator instance
00782   * @param  PowerMode This parameter can be one of the following values:
00783   *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED
00784   *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED   (1)
00785   *         @arg @ref LL_COMP_POWERMODE_LOWPOWER      (1)
00786   *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1)
00787   *
00788   *         (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
00789   * @retval None
00790   */
00791 __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
00792 {
00793 #if defined(COMP_CSR_COMPxMODE)
00794   MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxMODE, PowerMode);
00795 #else
00796   /* Device without comparator power mode configurable */
00797   /* No update of comparator register (corresponds to setting                 */
00798   /* "LL_COMP_POWERMODE_HIGHSPEED").                                          */
00799 #endif
00800 }
00801
00802 /**
00803   * @brief  Get comparator instance operating mode to adjust power and speed.
00804   * @rmtoll CSR      COMPxMODE      LL_COMP_GetPowerMode
00805   * @param  COMPx Comparator instance
00806   * @retval Returned value can be one of the following values:
00807   *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED
00808   *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED   (1)
00809   *         @arg @ref LL_COMP_POWERMODE_LOWPOWER      (1)
00810   *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1)
00811   *
00812   *         (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
00813   */
00814 __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
00815 {
00816 #if defined(COMP_CSR_COMPxMODE)
00817   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxMODE));
00818 #else
00819   /* Device without comparator power mode configurable */
00820   return (LL_COMP_POWERMODE_HIGHSPEED);
00821 #endif
00822 }
00823
00824 /**
00825   * @}
00826   */
00827
00828 /** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
00829   * @{
00830   */
00831
00832 /**
00833   * @brief  Set comparator inputs minus (inverting) and plus (non-inverting).
00834   * @note   In case of comparator input selected to be connected to IO:
00835   *         GPIO pins are specific to each comparator instance.
00836   *         Refer to description of parameters or to reference manual.
00837   * @note   On this STM32 serie, a voltage scaler is used
00838   *         when COMP input is based on VrefInt (VrefInt or subdivision
00839   *         of VrefInt):
00840   *         Voltage scaler requires a delay for voltage stabilization.
00841   *         Refer to device datasheet, parameter "tS_SC".
00842   * @rmtoll CSR      INMSEL         LL_COMP_ConfigInputs\n
00843   *         CSR      NONINSEL       LL_COMP_ConfigInputs
00844   * @param  COMPx Comparator instance
00845   * @param  InputMinus This parameter can be one of the following values:
00846   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
00847   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
00848   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
00849   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
00850   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
00851   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2   (3)
00852   *         @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1   (2)
00853   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
00854   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
00855   *         @arg @ref LL_COMP_INPUT_MINUS_IO3        (1)
00856   *         @arg @ref LL_COMP_INPUT_MINUS_IO4
00857   *         (1) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302x6/8, STM32F303x6/8, STM32F328xx, STM32F334xx.\n
00858   *         (2) Parameter available only on devices STM32F303x6/8, STM32F328x8, STM32F334xx.\n
00859   *         (3) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302xx.\n
00860   * @param  InputPlus This parameter can be one of the following values:
00861   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00862   *         @arg @ref LL_COMP_INPUT_PLUS_IO2            (1)
00863   *         @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (2)
00864   *         @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (3)
00865   *
00866   *         (1) Parameter available only on devices STM32F302xB/C, STM32F303xB/C, STM32F358xC.\n
00867   *         (2) Parameter available on devices: STM32F302xB/C, STM32F302xD/E, STM32F303xB/C/D/E, STM32F358xC, STM32F398xE.\n
00868   *         (3) Parameter available on devices: STM32F301x6/8, STM32F318xx, STM32F302x6/8.
00869   * @retval None
00870   */
00871 __STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
00872 {
00873 #if defined(COMP_CSR_COMPxNONINSEL) && defined(COMP_CSR_COMPxSW1)
00874   MODIFY_REG(COMPx->CSR,
00875              COMP_CSR_COMPxINSEL | COMP_CSR_COMPxNONINSEL | COMP_CSR_COMPxSW1,
00876              InputMinus | InputPlus);
00877 #elif defined(COMP_CSR_COMPxNONINSEL)
00878   MODIFY_REG(COMPx->CSR,
00879              COMP_CSR_COMPxINSEL | COMP_CSR_COMPxNONINSEL,
00880              InputMinus | InputPlus);
00881 #elif defined(COMP_CSR_COMPxSW1)
00882   MODIFY_REG(COMPx->CSR,
00883              COMP_CSR_COMPxINSEL | COMP_CSR_COMPxSW1,
00884              InputMinus | InputPlus);
00885 #else
00886   /* Device without comparator input plus configurable */
00887   /* No update of comparator register (corresponds to setting                 */
00888   /* "LL_COMP_INPUT_PLUS_IO1" or "LL_COMP_INPUT_PLUS_IO2" compared to         */
00889   /* other STM32F3 devices, depending on comparator instance                  */
00890   /* (refer to reference manual)).                                            */
00891   MODIFY_REG(COMPx->CSR,
00892              COMP_CSR_COMPxINSEL,
00893              InputMinus);
00894 #endif
00895 }
00896
00897 /**
00898   * @brief  Set comparator input plus (non-inverting).
00899   * @note   In case of comparator input selected to be connected to IO:
00900   *         GPIO pins are specific to each comparator instance.
00901   *         Refer to description of parameters or to reference manual.
00902   * @rmtoll CSR      NONINSEL       LL_COMP_SetInputPlus
00903   * @param  COMPx Comparator instance
00904   * @param  InputPlus This parameter can be one of the following values:
00905   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00906   *         @arg @ref LL_COMP_INPUT_PLUS_IO2            (1)
00907   *         @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (2)
00908   *         @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (3)
00909   *
00910   *         (1) Parameter available only on devices STM32F302xB/C, STM32F303xB/C, STM32F358xC.\n
00911   *         (2) Parameter available on devices: STM32F302xB/C, STM32F302xD/E, STM32F303xB/C/D/E, STM32F358xC, STM32F398xE.\n
00912   *         (3) Parameter available on devices: STM32F301x6/8, STM32F318xx, STM32F302x6/8.
00913   * @retval None
00914   */
00915 __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
00916 {
00917 #if defined(COMP_CSR_COMPxNONINSEL) && defined(COMP_CSR_COMPxSW1)
00918   MODIFY_REG(COMPx->CSR, (COMP_CSR_COMPxNONINSEL | COMP_CSR_COMPxSW1), InputPlus);
00919 #elif defined(COMP_CSR_COMPxNONINSEL)
00920   MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxNONINSEL, InputPlus);
00921 #elif defined(COMP_CSR_COMPxSW1)
00922   MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxSW1, InputPlus);
00923 #else
00924   /* Device without comparator input plus configurable */
00925   /* No update of comparator register (corresponds to setting                 */
00926   /* "LL_COMP_INPUT_PLUS_IO1" or "LL_COMP_INPUT_PLUS_IO2" compared to         */
00927   /* other STM32F3 devices, depending on comparator instance                  */
00928   /* (refer to reference manual)).                                            */
00929 #endif
00930 }
00931
00932 /**
00933   * @brief  Get comparator input plus (non-inverting).
00934   * @note   In case of comparator input selected to be connected to IO:
00935   *         GPIO pins are specific to each comparator instance.
00936   *         Refer to description of parameters or to reference manual.
00937   * @rmtoll CSR      NONINSEL       LL_COMP_GetInputPlus
00938   * @param  COMPx Comparator instance
00939   * @retval Returned value can be one of the following values:
00940   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00941   *         @arg @ref LL_COMP_INPUT_PLUS_IO2            (1)
00942   *         @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (2)
00943   *         @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (3)
00944   *
00945   *         (1) Parameter available only on devices STM32F302xB/C, STM32F303xB/C, STM32F358xC.\n
00946   *         (2) Parameter available on devices: STM32F302xB/C, STM32F302xD/E, STM32F303xB/C/D/E, STM32F358xC, STM32F398xE.\n
00947   *         (3) Parameter available on devices: STM32F301x6/8, STM32F318xx, STM32F302x6/8.
00948   */
00949 __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
00950 {
00951 #if defined(COMP_CSR_COMPxNONINSEL) && defined(COMP_CSR_COMPxSW1)
00952   return (uint32_t)(READ_BIT(COMPx->CSR, (COMP_CSR_COMPxNONINSEL | COMP_CSR_COMPxSW1)));
00953 #elif defined(COMP_CSR_COMPxNONINSEL)
00954   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxNONINSEL));
00955 #elif defined(COMP_CSR_COMPxSW1)
00956   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxSW1));
00957 #else
00958   /* Device without comparator input plus configurable */
00959   /* No update of comparator register (corresponds to setting                 */
00960   /* "LL_COMP_INPUT_PLUS_IO1" or "LL_COMP_INPUT_PLUS_IO2" compared to         */
00961   /* other STM32F3 devices, depending on comparator instance                  */
00962   /* (refer to reference manual)).                                            */
00963   return (LL_COMP_INPUT_PLUS_IO1);
00964 #endif
00965 }
00966
00967 /**
00968   * @brief  Set comparator input minus (inverting).
00969   * @note   In case of comparator input selected to be connected to IO:
00970   *         GPIO pins are specific to each comparator instance.
00971   *         Refer to description of parameters or to reference manual.
00972   * @note   On this STM32 serie, a voltage scaler is used
00973   *         when COMP input is based on VrefInt (VrefInt or subdivision
00974   *         of VrefInt):
00975   *         Voltage scaler requires a delay for voltage stabilization.
00976   *         Refer to device datasheet, parameter "tS_SC".
00977   * @rmtoll CSR      INMSEL         LL_COMP_SetInputMinus
00978   * @param  COMPx Comparator instance
00979   * @param  InputMinus This parameter can be one of the following values:
00980   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
00981   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
00982   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
00983   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
00984   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
00985   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2   (3)
00986   *         @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1   (2)
00987   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
00988   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
00989   *         @arg @ref LL_COMP_INPUT_MINUS_IO3        (1)
00990   *         @arg @ref LL_COMP_INPUT_MINUS_IO4
00991   *         (1) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302x6/8, STM32F303x6/8, STM32F328xx, STM32F334xx.\n
00992   *         (2) Parameter available only on devices STM32F303x6/8, STM32F328x8, STM32F334xx.\n
00993   *         (3) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302xx.\n
00994   * @retval None
00995   */
00996 __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
00997 {
00998   MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxINSEL, InputMinus);
00999 }
01000
01001 /**
01002   * @brief  Get comparator input minus (inverting).
01003   * @note   In case of comparator input selected to be connected to IO:
01004   *         GPIO pins are specific to each comparator instance.
01005   *         Refer to description of parameters or to reference manual.
01006   * @rmtoll CSR      INMSEL         LL_COMP_GetInputMinus
01007   * @param  COMPx Comparator instance
01008   * @retval Returned value can be one of the following values:
01009   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
01010   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
01011   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
01012   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
01013   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
01014   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2   (3)
01015   *         @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1   (2)
01016   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
01017   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
01018   *         @arg @ref LL_COMP_INPUT_MINUS_IO3        (1)
01019   *         @arg @ref LL_COMP_INPUT_MINUS_IO4
01020   *         (1) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302x6/8, STM32F303x6/8, STM32F328xx, STM32F334xx.\n
01021   *         (2) Parameter available only on devices STM32F303x6/8, STM32F328x8, STM32F334xx.\n
01022   *         (3) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302xx.\n
01023   */
01024 __STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
01025 {
01026   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxINSEL));
01027 }
01028
01029 /**
01030   * @brief  Set comparator instance hysteresis mode of the input minus (inverting input).
01031   * @rmtoll CSR      COMPxHYST      LL_COMP_SetInputHysteresis
01032   * @param  COMPx Comparator instance
01033   * @param  InputHysteresis This parameter can be one of the following values:
01034   *         @arg @ref LL_COMP_HYSTERESIS_NONE
01035   *         @arg @ref LL_COMP_HYSTERESIS_LOW         (1)
01036   *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM      (1)
01037   *         @arg @ref LL_COMP_HYSTERESIS_HIGH        (1)
01038   *
01039   *         (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
01040   * @retval None
01041   */
01042 __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
01043 {
01044 #if defined(COMP_CSR_COMPxHYST)
01045   MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxHYST, InputHysteresis);
01046 #else
01047   /* Device without comparator input hysteresis */
01048   /* No update of comparator register (corresponds to setting                 */
01049   /* "LL_COMP_HYSTERESIS_NONE").                                              */
01050 #endif
01051 }
01052
01053 /**
01054   * @brief  Get comparator instance hysteresis mode of the minus (inverting) input.
01055   * @rmtoll CSR      COMPxHYST      LL_COMP_GetInputHysteresis
01056   * @param  COMPx Comparator instance
01057   * @retval Returned value can be one of the following values:
01058   *         @arg @ref LL_COMP_HYSTERESIS_NONE
01059   *         @arg @ref LL_COMP_HYSTERESIS_LOW         (1)
01060   *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM      (1)
01061   *         @arg @ref LL_COMP_HYSTERESIS_HIGH        (1)
01062   *
01063   *         (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
01064   */
01065 __STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
01066 {
01067 #if defined(COMP_CSR_COMPxHYST)
01068   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxHYST));
01069 #else
01070   /* Device without comparator input hysteresis */
01071   return (LL_COMP_HYSTERESIS_NONE);
01072 #endif
01073 }
01074
01075 /**
01076   * @}
01077   */
01078
01079 /** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
01080   * @{
01081   */
01082
01083 /**
01084   * @brief  Set comparator output selection.
01085   * @note   Availability of parameters of output selection to timer
01086   *         depends on timers availability on the selected device.
01087   * @rmtoll CSR      COMPxOUTSEL    LL_COMP_SetOutputSelection
01088   * @param  COMPx Comparator instance
01089   * @param  OutputSelection This parameter can be one of the following values:
01090   *         @arg @ref LL_COMP_OUTPUT_NONE
01091   *         @arg @ref LL_COMP_OUTPUT_TIM1_BKIN
01092   *         @arg @ref LL_COMP_OUTPUT_TIM1_BKIN2
01093   *         @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_BKIN2
01094   *         @arg @ref LL_COMP_OUTPUT_TIM8_BKIN              (4)
01095   *         @arg @ref LL_COMP_OUTPUT_TIM8_BKIN2             (4)
01096   *         @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_BKIN2        (4)
01097   *         @arg @ref LL_COMP_OUTPUT_TIM20_BKIN             (5)
01098   *         @arg @ref LL_COMP_OUTPUT_TIM20_BKIN2            (5)
01099   *         @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_TIM20_BKIN2  (5)
01100   *         @arg @ref LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7 (4)
01101   *         @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3   (4)
01102   *         @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5 (4)
01103   *         @arg @ref LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 (4)
01104   *         @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4     (6)
01105   *         @arg @ref LL_COMP_OUTPUT_TIM1_IC1_COMP2         (2)
01106   *         @arg @ref LL_COMP_OUTPUT_TIM2_IC4_COMP2         (2)
01107   *         @arg @ref LL_COMP_OUTPUT_TIM3_IC1_COMP2         (1)
01108   *         @arg @ref LL_COMP_OUTPUT_TIM1_IC1_COMP1_2       (3)
01109   *         @arg @ref LL_COMP_OUTPUT_TIM2_IC4_COMP1_2       (3)
01110   *         @arg @ref LL_COMP_OUTPUT_TIM3_IC1_COMP1_2       (3)
01111   *         @arg @ref LL_COMP_OUTPUT_TIM20_OCCLR_COMP2      (5)
01112   *         @arg @ref LL_COMP_OUTPUT_TIM3_IC2_COMP3         (4)
01113   *         @arg @ref LL_COMP_OUTPUT_TIM4_IC1_COMP3         (4)
01114   *         @arg @ref LL_COMP_OUTPUT_TIM15_IC1_COMP3        (4)
01115   *         @arg @ref LL_COMP_OUTPUT_TIM15_BKIN
01116   *         @arg @ref LL_COMP_OUTPUT_TIM3_IC3_COMP4         (1)
01117   *         @arg @ref LL_COMP_OUTPUT_TIM4_IC2_COMP4
01118   *         @arg @ref LL_COMP_OUTPUT_TIM15_IC2_COMP4
01119   *         @arg @ref LL_COMP_OUTPUT_TIM15_OCCLR_COMP4
01120   *         @arg @ref LL_COMP_OUTPUT_TIM2_IC1_COMP5         (4)
01121   *         @arg @ref LL_COMP_OUTPUT_TIM4_IC3_COMP5         (4)
01122   *         @arg @ref LL_COMP_OUTPUT_TIM17_IC1_COMP5        (4)
01123   *         @arg @ref LL_COMP_OUTPUT_TIM16_BKIN
01124   *         @arg @ref LL_COMP_OUTPUT_TIM2_IC2_COMP6
01125   *         @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR_COMP6
01126   *         @arg @ref LL_COMP_OUTPUT_TIM4_IC4_COMP6
01127   *         @arg @ref LL_COMP_OUTPUT_TIM16_IC1_COMP6
01128   *         @arg @ref LL_COMP_OUTPUT_TIM16_OCCLR_COMP6
01129   *         @arg @ref LL_COMP_OUTPUT_TIM1_IC2_COMP7         (4)
01130   *         @arg @ref LL_COMP_OUTPUT_TIM2_IC3_COMP7         (4)
01131   *         @arg @ref LL_COMP_OUTPUT_TIM17_OCCLR_COMP7      (4)
01132   *         @arg @ref LL_COMP_OUTPUT_TIM17_BKIN             (4)
01133   *
01134   *         (1) Parameter available on devices: STM32F302x8, STM32F318xx, STM32F303x8, STM32F328xx, STM32F334x8, STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
01135   *         (2) Parameter available on devices: STM32F301x8, STM32F302x8, STM32F318xx, STM32F303x8, STM32F328xx, STM32F334x8.\n
01136   *         (3) Parameter available on devices: STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
01137   *         (4) Parameter available on devices: STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
01138   *         (5) Parameter available on devices: STM32F303xE, STM32F398xx.\n
01139   *         (6) Parameter available on devices: STM32F303x8, STM32F328xx, STM32F334x8.
01140   * @retval None
01141   */
01142 __STATIC_INLINE void LL_COMP_SetOutputSelection(COMP_TypeDef *COMPx, uint32_t OutputSelection)
01143 {
01144   MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxOUTSEL , OutputSelection);
01145 }
01146
01147 /**
01148   * @brief  Get comparator output selection.
01149   * @note   Availability of parameters of output selection to timer
01150   *         depends on timers availability on the selected device.
01151   * @rmtoll CSR      COMPxOUTSEL    LL_COMP_GetOutputSelection
01152   * @param  COMPx Comparator instance
01153   * @retval Returned value can be one of the following values:
01154   *         @arg @ref LL_COMP_OUTPUT_NONE
01155   *         @arg @ref LL_COMP_OUTPUT_TIM1_BKIN
01156   *         @arg @ref LL_COMP_OUTPUT_TIM1_BKIN2
01157   *         @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_BKIN2
01158   *         @arg @ref LL_COMP_OUTPUT_TIM8_BKIN              (4)
01159   *         @arg @ref LL_COMP_OUTPUT_TIM8_BKIN2             (4)
01160   *         @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_BKIN2        (4)
01161   *         @arg @ref LL_COMP_OUTPUT_TIM20_BKIN             (5)
01162   *         @arg @ref LL_COMP_OUTPUT_TIM20_BKIN2            (5)
01163   *         @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_TIM20_BKIN2  (5)
01164   *         @arg @ref LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7 (4)
01165   *         @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3   (4)
01166   *         @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5 (4)
01167   *         @arg @ref LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 (4)
01168   *         @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4     (6)
01169   *         @arg @ref LL_COMP_OUTPUT_TIM1_IC1_COMP2         (2)
01170   *         @arg @ref LL_COMP_OUTPUT_TIM2_IC4_COMP2         (2)
01171   *         @arg @ref LL_COMP_OUTPUT_TIM3_IC1_COMP2         (1)
01172   *         @arg @ref LL_COMP_OUTPUT_TIM1_IC1_COMP1_2       (3)
01173   *         @arg @ref LL_COMP_OUTPUT_TIM2_IC4_COMP1_2       (3)
01174   *         @arg @ref LL_COMP_OUTPUT_TIM3_IC1_COMP1_2       (3)
01175   *         @arg @ref LL_COMP_OUTPUT_TIM20_OCCLR_COMP2      (5)
01176   *         @arg @ref LL_COMP_OUTPUT_TIM3_IC2_COMP3         (4)
01177   *         @arg @ref LL_COMP_OUTPUT_TIM4_IC1_COMP3         (4)
01178   *         @arg @ref LL_COMP_OUTPUT_TIM15_IC1_COMP3        (4)
01179   *         @arg @ref LL_COMP_OUTPUT_TIM15_BKIN
01180   *         @arg @ref LL_COMP_OUTPUT_TIM3_IC3_COMP4         (1)
01181   *         @arg @ref LL_COMP_OUTPUT_TIM4_IC2_COMP4
01182   *         @arg @ref LL_COMP_OUTPUT_TIM15_IC2_COMP4
01183   *         @arg @ref LL_COMP_OUTPUT_TIM15_OCCLR_COMP4
01184   *         @arg @ref LL_COMP_OUTPUT_TIM2_IC1_COMP5         (4)
01185   *         @arg @ref LL_COMP_OUTPUT_TIM4_IC3_COMP5         (4)
01186   *         @arg @ref LL_COMP_OUTPUT_TIM17_IC1_COMP5        (4)
01187   *         @arg @ref LL_COMP_OUTPUT_TIM16_BKIN
01188   *         @arg @ref LL_COMP_OUTPUT_TIM2_IC2_COMP6
01189   *         @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR_COMP6
01190   *         @arg @ref LL_COMP_OUTPUT_TIM4_IC4_COMP6
01191   *         @arg @ref LL_COMP_OUTPUT_TIM16_IC1_COMP6
01192   *         @arg @ref LL_COMP_OUTPUT_TIM16_OCCLR_COMP6
01193   *         @arg @ref LL_COMP_OUTPUT_TIM1_IC2_COMP7         (4)
01194   *         @arg @ref LL_COMP_OUTPUT_TIM2_IC3_COMP7         (4)
01195   *         @arg @ref LL_COMP_OUTPUT_TIM17_OCCLR_COMP7      (4)
01196   *         @arg @ref LL_COMP_OUTPUT_TIM17_BKIN             (4)
01197   *
01198   *         (1) Parameter available on devices: STM32F302x8, STM32F318xx, STM32F303x8, STM32F328xx, STM32F334x8, STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
01199   *         (2) Parameter available on devices: STM32F301x8, STM32F302x8, STM32F318xx, STM32F303x8, STM32F328xx, STM32F334x8.\n
01200   *         (3) Parameter available on devices: STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
01201   *         (4) Parameter available on devices: STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
01202   *         (5) Parameter available on devices: STM32F303xE, STM32F398xx.\n
01203   *         (6) Parameter available on devices: STM32F303x8, STM32F328xx, STM32F334x8.
01204   */
01205 __STATIC_INLINE uint32_t LL_COMP_GetOutputSelection(COMP_TypeDef *COMPx)
01206 {
01207   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxOUTSEL));
01208 }
01209
01210 /**
01211   * @brief  Set comparator instance output polarity.
01212   * @rmtoll CSR      COMPxPOL       LL_COMP_SetOutputPolarity
01213   * @param  COMPx Comparator instance
01214   * @param  OutputPolarity This parameter can be one of the following values:
01215   *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
01216   *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
01217   * @retval None
01218   */
01219 __STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
01220 {
01221   MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxPOL, OutputPolarity);
01222 }
01223
01224 /**
01225   * @brief  Get comparator instance output polarity.
01226   * @rmtoll CSR      COMPxPOL       LL_COMP_GetOutputPolarity
01227   * @param  COMPx Comparator instance
01228   * @retval Returned value can be one of the following values:
01229   *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
01230   *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
01231   */
01232 __STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
01233 {
01234   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxPOL));
01235 }
01236
01237 /**
01238   * @brief  Set comparator instance blanking source.
01239   * @note   Blanking source may be specific to each comparator instance.
01240   *         Refer to description of parameters or to reference manual.
01241   * @note   Availability of parameters of blanking source from timer
01242   *         depends on timers availability on the selected device.
01243   * @rmtoll CSR      COMPxBLANKING  LL_COMP_SetOutputBlankingSource
01244   * @param  COMPx Comparator instance
01245   * @param  BlankingSource This parameter can be one of the following values:
01246   *         @arg @ref LL_COMP_BLANKINGSRC_NONE
01247   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2       (1)
01248   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2       (1)
01249   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2       (1)
01250   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2     (2)(3)
01251   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2     (2)(3)
01252   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2     (2)(3)
01253   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
01254   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
01255   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6       (2)
01256   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6      (1)(2)
01257   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7   (3)
01258   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6     (3)
01259   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7 (3)
01260   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7    (3)
01261   *
01262   *         (1) Parameter available on devices: STM32F301x8, STM32F302x8, STM32F318xx, STM32F303x8, STM32F334x8, STM32F328xx.\n
01263   *         (2) Parameter available on devices: STM32F302xE, STM32F302xC.\n
01264   *         (3) Parameter available on devices: STM32F303xE, STM32F398xx, STM32F303xC, STM32F358xx.
01265   * @retval None
01266   */
01267 __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32_t BlankingSource)
01268 {
01269   MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxBLANKING, BlankingSource);
01270 }
01271
01272 /**
01273   * @brief  Get comparator instance blanking source.
01274   * @note   Availability of parameters of blanking source from timer
01275   *         depends on timers availability on the selected device.
01276   * @note   Blanking source may be specific to each comparator instance.
01277   *         Refer to description of parameters or to reference manual.
01278   * @rmtoll CSR      COMPxBLANKING  LL_COMP_GetOutputBlankingSource
01279   * @param  COMPx Comparator instance
01280   * @retval Returned value can be one of the following values:
01281   *         @arg @ref LL_COMP_BLANKINGSRC_NONE
01282   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2       (1)
01283   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2       (1)
01284   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2       (1)
01285   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2     (2)(3)
01286   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2     (2)(3)
01287   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2     (2)(3)
01288   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
01289   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
01290   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6       (2)
01291   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6      (1)(2)
01292   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7   (3)
01293   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6     (3)
01294   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7 (3)
01295   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7    (3)
01296   *
01297   *         (1) Parameter available on devices: STM32F301x8, STM32F302x8, STM32F318xx, STM32F303x8, STM32F334x8, STM32F328xx.\n
01298   *         (2) Parameter available on devices: STM32F302xE, STM32F302xC.\n
01299   *         (3) Parameter available on devices: STM32F303xE, STM32F398xx, STM32F303xC, STM32F358xx.
01300   */
01301 __STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx)
01302 {
01303   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxBLANKING));
01304 }
01305
01306 /**
01307   * @}
01308   */
01309
01310 /** @defgroup COMP_LL_EF_Operation Operation on comparator instance
01311   * @{
01312   */
01313
01314 /**
01315   * @brief  Enable comparator instance.
01316   * @note   After enable from off state, comparator requires a delay
01317   *         to reach reach propagation delay specification.
01318   *         Refer to device datasheet, parameter "tSTART".
01319   * @rmtoll CSR      COMPxEN        LL_COMP_Enable
01320   * @param  COMPx Comparator instance
01321   * @retval None
01322   */
01323 __STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
01324 {
01325   SET_BIT(COMPx->CSR, COMP_CSR_COMPxEN);
01326 }
01327
01328 /**
01329   * @brief  Disable comparator instance.
01330   * @rmtoll CSR      COMPxEN        LL_COMP_Disable
01331   * @param  COMPx Comparator instance
01332   * @retval None
01333   */
01334 __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
01335 {
01336   CLEAR_BIT(COMPx->CSR, COMP_CSR_COMPxEN);
01337 }
01338
01339 /**
01340   * @brief  Get comparator enable state
01341   *         (0: COMP is disabled, 1: COMP is enabled)
01342   * @rmtoll CSR      COMPxEN        LL_COMP_IsEnabled
01343   * @param  COMPx Comparator instance
01344   * @retval State of bit (1 or 0).
01345   */
01346 __STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
01347 {
01348   return (READ_BIT(COMPx->CSR, COMP_CSR_COMPxEN) == (COMP_CSR_COMPxEN));
01349 }
01350
01351 /**
01352   * @brief  Lock comparator instance.
01353   * @note   Once locked, comparator configuration can be accessed in read-only.
01354   * @note   The only way to unlock the comparator is a device hardware reset.
01355   * @rmtoll CSR      COMPxLOCK      LL_COMP_Lock
01356   * @param  COMPx Comparator instance
01357   * @retval None
01358   */
01359 __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
01360 {
01361   SET_BIT(COMPx->CSR, COMP_CSR_COMPxLOCK);
01362 }
01363
01364 /**
01365   * @brief  Get comparator lock state
01366   *         (0: COMP is unlocked, 1: COMP is locked).
01367   * @note   Once locked, comparator configuration can be accessed in read-only.
01368   * @note   The only way to unlock the comparator is a device hardware reset.
01369   * @rmtoll CSR      COMPxLOCK      LL_COMP_IsLocked
01370   * @param  COMPx Comparator instance
01371   * @retval State of bit (1 or 0).
01372   */
01373 __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
01374 {
01375   return (READ_BIT(COMPx->CSR, COMP_CSR_COMPxLOCK) == (COMP_CSR_COMPxLOCK));
01376 }
01377
01378 /**
01379   * @brief  Read comparator instance output level.
01380   * @note   The comparator output level depends on the selected polarity
01381   *         (Refer to function @ref LL_COMP_SetOutputPolarity()).
01382   *         If the comparator polarity is not inverted:
01383   *          - Comparator output is low when the input plus
01384   *            is at a lower voltage than the input minus
01385   *          - Comparator output is high when the input plus
01386   *            is at a higher voltage than the input minus
01387   *         If the comparator polarity is inverted:
01388   *          - Comparator output is high when the input plus
01389   *            is at a lower voltage than the input minus
01390   *          - Comparator output is low when the input plus
01391   *            is at a higher voltage than the input minus
01392   * @rmtoll CSR      COMPxOUT       LL_COMP_ReadOutputLevel
01393   * @param  COMPx Comparator instance
01394   * @retval Returned value can be one of the following values:
01395   *         @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
01396   *         @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
01397   */
01398 __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
01399 {
01400   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxOUT)
01401                     >> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS);
01402 }
01403
01404 /**
01405   * @}
01406   */
01407
01408 #if defined(USE_FULL_LL_DRIVER)
01409 /** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
01410   * @{
01411   */
01412
01413 ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
01414 ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
01415 void        LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
01416
01417 /**
01418   * @}
01419   */
01420 #endif /* USE_FULL_LL_DRIVER */
01421
01422 /**
01423   * @}
01424   */
01425
01426 /**
01427   * @}
01428   */
01429
01430 #endif /* COMP1 || COMP2 || COMP3 || COMP4 || COMP5 || COMP6 || COMP7 */
01431
01432
01433 #endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
01434
01435 #if defined (COMP_V1_1_0_0)
01436
01437 #if defined (COMP1) || defined (COMP2)
01438
01439 /** @defgroup COMP_LL COMP
01440   * @{
01441   */
01442
01443 /* Private types -------------------------------------------------------------*/
01444 /* Private variables ---------------------------------------------------------*/
01445 /* Private constants ---------------------------------------------------------*/
01446 /** @defgroup COMP_LL_Private_Constants COMP Private Constants
01447   * @{
01448   */
01449
01450 /* Differentiation between COMP instances */
01451 /* Note: Value not corresponding to a register offset since both              */
01452 /*       COMP instances are sharing the same register) .                      */
01453 #define COMPX_BASE  COMP_BASE
01454 #define COMPX       (COMP1 - COMP2)
01455
01456 /* COMP registers bits positions */
01457 #define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(COMP_CSR_COMP1OUT) */
01458
01459 /**
01460   * @}
01461   */
01462
01463 /* Private macros ------------------------------------------------------------*/
01464 /** @defgroup COMP_LL_Private_Macros COMP Private Macros
01465   * @{
01466   */
01467
01468 /**
01469   * @brief  Driver macro reserved for internal use: if COMP instance selected
01470   *         is odd (COMP1, COMP3, ...), return value '1', else return '0'.
01471   * @param  __COMP_INSTANCE__ COMP instance
01472   * @retval If COMP instance is odd, value '1'. Else, value '0'.
01473 */
01474 #define __COMP_IS_INSTANCE_ODD(__COMP_INSTANCE__)                              \
01475   ((~(((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) >> 1U)) & 0x00000001)
01476
01477 /**
01478   * @brief  Driver macro reserved for internal use: if COMP instance selected
01479   *         is even (COMP2, COMP4, ...), return value '1', else return '0'.
01480   * @param  __COMP_INSTANCE__ COMP instance
01481   * @retval If COMP instance is even, value '1'. Else, value '0'.
01482 */
01483 #define __COMP_IS_INSTANCE_EVEN(__COMP_INSTANCE__)                             \
01484   (((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) >> 1U)
01485
01486 /**
01487   * @brief  Driver macro reserved for internal use: from COMP instance
01488   *         selected, set offset of bits into COMP register.
01489   * @note   Since both COMP instances are sharing the same register
01490   *         with 2 area of bits with an offset of 16 bits, this function
01491   *         returns value "0" if COMP1 is selected and "16" if COMP2 is
01492   *         selected.
01493   * @param  __COMP_INSTANCE__ COMP instance
01494   * @retval Bits offset in register 32 bits
01495 */
01496 #define __COMP_BITOFFSET_INSTANCE(__COMP_INSTANCE__)                           \
01497   (((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) << 3U)
01498
01499 /**
01500   * @}
01501   */
01502
01503 /* Exported types ------------------------------------------------------------*/
01504 #if defined(USE_FULL_LL_DRIVER)
01505 /** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
01506   * @{
01507   */
01508
01509 /**
01510   * @brief  Structure definition of some features of COMP instance.
01511   */
01512 typedef struct
01513 {
01514   uint32_t PowerMode;                   /*!< Set comparator operating mode to adjust power and speed.
01515                                              This parameter can be a value of @ref COMP_LL_EC_POWERMODE
01516
01517                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
01518
01519   uint32_t InputPlus;                   /*!< Set comparator input plus (non-inverting input).
01520                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
01521
01522                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
01523
01524   uint32_t InputMinus;                  /*!< Set comparator input minus (inverting input).
01525                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
01526
01527                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
01528
01529   uint32_t InputHysteresis;             /*!< Set comparator hysteresis mode of the input minus.
01530                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
01531
01532                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */
01533
01534   uint32_t OutputSelection;             /*!< Set comparator output selection.
01535                                              This parameter can be a value of @ref COMP_LL_EC_OUTPUT_SELECTION
01536
01537                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputSelection(). */
01538
01539   uint32_t OutputPolarity;              /*!< Set comparator output polarity.
01540                                              This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
01541
01542                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
01543
01544 } LL_COMP_InitTypeDef;
01545
01546 /**
01547   * @}
01548   */
01549 #endif /* USE_FULL_LL_DRIVER */
01550
01551 /* Exported constants --------------------------------------------------------*/
01552 /** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
01553   * @{
01554   */
01555
01556 /** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
01557   * @{
01558   */
01559 #define LL_COMP_WINDOWMODE_DISABLE                 ((uint32_t)0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */
01560 #define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WNDWEN)       /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
01561 /**
01562   * @}
01563   */
01564
01565 /** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
01566   * @{
01567   */
01568 #define LL_COMP_POWERMODE_HIGHSPEED     ((uint32_t)0x00000000U)                       /*!< COMP power mode to high speed */
01569 #define LL_COMP_POWERMODE_MEDIUMSPEED   (COMP_CSR_COMP1MODE_0)                        /*!< COMP power mode to medium speed */
01570 #define LL_COMP_POWERMODE_LOWPOWER      (COMP_CSR_COMP1MODE_1)                        /*!< COMP power mode to low power */
01571 #define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_COMP1MODE_1 | COMP_CSR_COMP1MODE_0) /*!< COMP power mode to ultra-low power */
01572 /**
01573   * @}
01574   */
01575
01576 /** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
01577   * @{
01578   */
01579 #define LL_COMP_INPUT_PLUS_IO1          ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA3 for COMP2) */
01580 #define LL_COMP_INPUT_PLUS_DAC1_CH1     (COMP_CSR_COMP1SW1)     /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch (Note: this switch is solely intended to redirect signals onto high impedance input, such as COMP1 input plus (highly resistive switch)) (specific to COMP instance: COMP1) */
01581 /**
01582   * @}
01583   */
01584
01585 /** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
01586   * @{
01587   */
01588 #define LL_COMP_INPUT_MINUS_1_4VREFINT  ((uint32_t)0x00000000U)                                                 /*!< Comparator input minus connected to 1/4 VrefInt  */
01589 #define LL_COMP_INPUT_MINUS_1_2VREFINT  (                                                COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt  */
01590 #define LL_COMP_INPUT_MINUS_3_4VREFINT  (                        COMP_CSR_COMP1INSEL_1                        ) /*!< Comparator input minus connected to 3/4 VrefInt  */
01591 #define LL_COMP_INPUT_MINUS_VREFINT     (                        COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to VrefInt */
01592 #define LL_COMP_INPUT_MINUS_DAC1_CH1    (COMP_CSR_COMP1INSEL_2                                                ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)  */
01593 #define LL_COMP_INPUT_MINUS_DAC1_CH2    (COMP_CSR_COMP1INSEL_2                         | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)  */
01594 #define LL_COMP_INPUT_MINUS_IO1         (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1                        ) /*!< Comparator input minus connected to IO1 (pin PA0 for COMP1, pin PA2 for COMP2) */
01595 #define LL_COMP_INPUT_MINUS_IO2         (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to IO2 (pin PA6 for COMP1 & COMP2) */
01596 #define LL_COMP_INPUT_MINUS_IO3         (COMP_CSR_COMP1INSEL_2 |                         COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to IO3 (pin PA5 for COMP1 & COMP2) */
01597 #define LL_COMP_INPUT_MINUS_IO4         (COMP_CSR_COMP1INSEL_2                                                ) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1 & COMP2) */
01598 #define LL_COMP_INPUT_MINUS_DAC2_CH1    (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to DAC2 channel 1 (DAC2_OUT1)  */
01599 /**
01600   * @}
01601   */
01602
01603 /** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
01604   * @{
01605   */
01606 #define LL_COMP_HYSTERESIS_NONE         ((uint32_t)0x00000000U)                       /*!< No hysteresis */
01607 #define LL_COMP_HYSTERESIS_LOW          (                       COMP_CSR_COMP1HYST_0) /*!< Hysteresis level low */
01608 #define LL_COMP_HYSTERESIS_MEDIUM       (COMP_CSR_COMP1HYST_1                       ) /*!< Hysteresis level medium */
01609 #define LL_COMP_HYSTERESIS_HIGH         (COMP_CSR_COMP1HYST_1 | COMP_CSR_COMP1HYST_0) /*!< Hysteresis level high */
01610 /**
01611   * @}
01612   */
01613
01614 /** @defgroup COMP_LL_EC_OUTPUT_SELECTION Comparator output - Output selection
01615   * @{
01616   */
01617 /* Note: Output redirection is common for COMP1 and COMP2 */
01618 #define LL_COMP_OUTPUT_NONE             ((uint32_t)0x00000000U)                                                    /*!< COMP output is not connected to other peripherals (except GPIO and EXTI that are always connected to COMP output) */
01619 #define LL_COMP_OUTPUT_TIM2_IC4         (COMP_CSR_COMP1OUTSEL_2)                                                   /*!< COMP output connected to TIM2 input capture 4 */
01620 #define LL_COMP_OUTPUT_TIM2_OCCLR       (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_0)                          /*!< COMP output connected to TIM2 OCREF clear */
01621
01622 /* Note: Output redirection specific to COMP instance: COMP1 */
01623 #define LL_COMP_OUTPUT_TIM15_BKIN_COMP1 (COMP_CSR_COMP1OUTSEL_0)                                                   /*!< COMP output connected to TIM15 break input (BKIN) (specific to COMP instance: COMP1) */
01624 #define LL_COMP_OUTPUT_TIM3_IC1_COMP1   (COMP_CSR_COMP1OUTSEL_1)                                                   /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP1) */
01625 #define LL_COMP_OUTPUT_TIM3_OCCLR_COMP1 (COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0)                          /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP1) */
01626 #define LL_COMP_OUTPUT_TIM5_IC4_COMP1   (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1)                          /*!< COMP output connected to TIM5 input capture 4 (specific to COMP instance: COMP1) */
01627 #define LL_COMP_OUTPUT_TIM5_OCCLR_COMP1 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM5 OCREF clear (specific to COMP instance: COMP1) */
01628
01629 /* Note: Output redirection specific to COMP instance: COMP2 */
01630 #define LL_COMP_OUTPUT_TIM16_BKIN_COMP2 (COMP_CSR_COMP1OUTSEL_0)                                                   /*!< COMP output connected to TIM16 break input (BKIN) (specific to COMP instance: COMP2) */
01631 #define LL_COMP_OUTPUT_TIM4_IC1_COMP2   (COMP_CSR_COMP1OUTSEL_1)                                                   /*!< COMP output connected to TIM4 input capture 1 (specific to COMP instance: COMP2) */
01632 #define LL_COMP_OUTPUT_TIM4_OCCLR_COMP2 (COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0)                          /*!< COMP output connected to TIM4 OCREF clear (specific to COMP instance: COMP2) */
01633 #define LL_COMP_OUTPUT_TIM3_IC1_COMP2   (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1)                          /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
01634 #define LL_COMP_OUTPUT_TIM3_OCCLR_COMP2 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP2) */
01635
01636 /* Note: Output redirection specific to COMP instances, defined with          */
01637 /*       generic naming not taking into account COMP instance constraints.    */
01638 /*       Refer to literal definitions above for COMP instance constraints.    */
01639 /* Note: Some output redirections cannot have a generic naming,               */
01640 /*       due to literal value different depending on COMP instance.           */
01641 /*       (For exemple: LL_COMP_OUTPUT_TIM3_IC1_COMP1 and                      */
01642 /*       LL_COMP_OUTPUT_TIM3_IC1_COMP2).                                      */
01643 #define LL_COMP_OUTPUT_TIM15_BKIN       LL_COMP_OUTPUT_TIM15_BKIN_COMP1       /*!< COMP output connected to TIM15 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
01644 #define LL_COMP_OUTPUT_TIM16_BKIN       LL_COMP_OUTPUT_TIM16_BKIN_COMP2       /*!< COMP output connected to TIM16 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
01645 #define LL_COMP_OUTPUT_TIM4_IC1         LL_COMP_OUTPUT_TIM4_IC1_COMP2         /*!< COMP output connected to TIM4 input capture 1.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
01646 #define LL_COMP_OUTPUT_TIM4_OCCLR       LL_COMP_OUTPUT_TIM4_OCCLR_COMP2       /*!< COMP output connected to TIM4 OCREF clear.         Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
01647 #define LL_COMP_OUTPUT_TIM5_IC4         LL_COMP_OUTPUT_TIM5_IC1_COMP1         /*!< COMP output connected to TIM5 input capture 4.     Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
01648 #define LL_COMP_OUTPUT_TIM5_OCCLR       LL_COMP_OUTPUT_TIM5_OCCLR_COMP1       /*!< COMP output connected to TIM5 OCREF clear.         Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
01649 /**
01650   * @}
01651   */
01652
01653 /** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
01654   * @{
01655   */
01656 #define LL_COMP_OUTPUTPOL_NONINVERTED   ((uint32_t)0x00000000U)  /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
01657 #define LL_COMP_OUTPUTPOL_INVERTED      (COMP_CSR_COMP1POL)      /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
01658 /**
01659   * @}
01660   */
01661
01662 /** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
01663   * @{
01664   */
01665 #define LL_COMP_OUTPUT_LEVEL_LOW        ((uint32_t)0x00000000U) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
01666 #define LL_COMP_OUTPUT_LEVEL_HIGH       ((uint32_t)0x00000001U) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
01667 /**
01668   * @}
01669   */
01670
01671 /** @defgroup COMP_LL_EC_HW_DELAYS  Definitions of COMP hardware constraints delays
01672   * @note   Only COMP IP HW delays are defined in COMP LL driver driver,
01673   *         not timeout values.
01674   *         For details on delays values, refer to descriptions in source code
01675   *         above each literal definition.
01676   * @{
01677   */
01678
01679 /* Delay for comparator startup time.                                         */
01680 /* Note: Delay required to reach propagation delay specification.             */
01681 /* Literal set to maximum value (refer to device datasheet,                   */
01682 /* parameter "tSTART").                                                       */
01683 /* Unit: us                                                                   */
01684 #define LL_COMP_DELAY_STARTUP_US          ((uint32_t) 60U)  /*!< Delay for COMP startup time */
01685
01686 /* Delay for comparator voltage scaler stabilization time                     */
01687 /* (voltage from VrefInt, delay based on VrefInt startup time).               */
01688 /* Literal set to maximum value (refer to device datasheet,                   */
01689 /* parameter "tS_SC").                                                        */
01690 /* Unit: us                                                                   */
01691 #define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)  /*!< Delay for COMP voltage scaler stabilization time */
01692
01693
01694 /**
01695   * @}
01696   */
01697
01698 /**
01699   * @}
01700   */
01701
01702 /* Exported macro ------------------------------------------------------------*/
01703 /** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
01704   * @{
01705   */
01706 /** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
01707   * @{
01708   */
01709
01710 /**
01711   * @brief  Write a value in COMP register
01712   * @param  __INSTANCE__ comparator instance
01713   * @param  __REG__ Register to be written
01714   * @param  __VALUE__ Value to be written in the register
01715   * @retval None
01716   */
01717 #define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
01718
01719 /**
01720   * @brief  Read a value in COMP register
01721   * @param  __INSTANCE__ comparator instance
01722   * @param  __REG__ Register to be read
01723   * @retval Register value
01724   */
01725 #define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
01726 /**
01727   * @}
01728   */
01729
01730 /** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
01731   * @{
01732   */
01733
01734 /**
01735   * @brief  Helper macro to select the COMP common instance
01736   *         to which is belonging the selected COMP instance.
01737   * @note   COMP common register instance can be used to
01738   *         set parameters common to several COMP instances.
01739   *         Refer to functions having argument "COMPxy_COMMON" as parameter.
01740   * @param  __COMPx__ COMP instance
01741   * @retval COMP common instance or value "0" if there is no COMP common instance.
01742   */
01743 #define __LL_COMP_COMMON_INSTANCE(__COMPx__)                                   \
01744   (COMP12_COMMON)
01745
01746 /**
01747   * @}
01748   */
01749
01750 /**
01751   * @}
01752   */
01753
01754 /* Exported functions --------------------------------------------------------*/
01755 /** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
01756   * @{
01757   */
01758
01759 /** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances
01760   * @{
01761   */
01762
01763 /**
01764   * @brief  Set window mode of a pair of comparators instances
01765   *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
01766   * @rmtoll CSR         WNDWEN          LL_COMP_SetCommonWindowMode
01767   * @param  COMPxy_COMMON Comparator common instance
01768   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
01769   * @param  WindowMode This parameter can be one of the following values:
01770   *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
01771   *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
01772   * @retval None
01773   */
01774 __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
01775 {
01776   MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_WNDWEN, WindowMode);
01777 }
01778
01779 /**
01780   * @brief  Get window mode of a pair of comparators instances
01781   *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
01782   * @rmtoll CSR         WNDWEN          LL_COMP_GetCommonWindowMode
01783   * @param  COMPxy_COMMON Comparator common instance
01784   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
01785   * @retval Returned value can be one of the following values:
01786   *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
01787   *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
01788   */
01789 __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
01790 {
01791   return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_WNDWEN));
01792 }
01793
01794 /**
01795   * @}
01796   */
01797
01798 /** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
01799   * @{
01800   */
01801
01802 /**
01803   * @brief  Set comparator instance operating mode to adjust power and speed.
01804   * @rmtoll CSR         COMP1MODE       LL_COMP_SetPowerMode\n
01805   *                     COMP2MODE       LL_COMP_SetPowerMode
01806   * @param  COMPx Comparator instance
01807   * @param  PowerMode This parameter can be one of the following values:
01808   *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED
01809   *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
01810   *         @arg @ref LL_COMP_POWERMODE_LOWPOWER
01811   *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
01812   * @retval None
01813   */
01814 __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
01815 {
01816   MODIFY_REG(COMP->CSR,
01817              COMP_CSR_COMP1MODE << __COMP_BITOFFSET_INSTANCE(COMPx),
01818              PowerMode          << __COMP_BITOFFSET_INSTANCE(COMPx) );
01819 }
01820
01821 /**
01822   * @brief  Get comparator instance operating mode to adjust power and speed.
01823   * @rmtoll CSR         COMP1MODE       LL_COMP_GetPowerMode\n
01824   *                     COMP2MODE       LL_COMP_GetPowerMode
01825   * @param  COMPx Comparator instance
01826   * @retval Returned value can be one of the following values:
01827   *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED
01828   *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
01829   *         @arg @ref LL_COMP_POWERMODE_LOWPOWER
01830   *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
01831   */
01832 __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
01833 {
01834   return (uint32_t)(READ_BIT(COMP->CSR,
01835                              COMP_CSR_COMP1MODE << __COMP_BITOFFSET_INSTANCE(COMPx))
01836                     >> __COMP_BITOFFSET_INSTANCE(COMPx)
01837                    );
01838 }
01839
01840 /**
01841   * @}
01842   */
01843
01844 /** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
01845   * @{
01846   */
01847
01848 /**
01849   * @brief  Set comparator inputs minus (inverting) and plus (non-inverting).
01850   * @note   In case of comparator input selected to be connected to IO:
01851   *         GPIO pins are specific to each comparator instance.
01852   *         Refer to description of parameters or to reference manual.
01853   * @rmtoll CSR         COMP1INSEL      LL_COMP_ConfigInputs\n
01854   *         CSR         COMP2INSEL      LL_COMP_ConfigInputs\n
01855   *         CSR         COMP1SW1        LL_COMP_ConfigInputs
01856   * @param  COMPx Comparator instance
01857   * @param  InputMinus This parameter can be one of the following values:
01858   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
01859   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
01860   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
01861   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
01862   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
01863   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
01864   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
01865   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
01866   *         @arg @ref LL_COMP_INPUT_MINUS_IO3
01867   *         @arg @ref LL_COMP_INPUT_MINUS_IO4
01868   *         @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1
01869   * @param  InputPlus This parameter can be one of the following values:
01870   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
01871   *         @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1)
01872   *
01873   *         (1) Parameter available only on COMP instance: COMP1.
01874   * @retval None
01875   */
01876 __STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
01877 {
01878   /* Note: Connection switch is applicable only to COMP instance COMP1,       */
01879   /*       therefore if COMP2 is selected the equivalent bit is               */
01880   /*       kept unmodified.                                                   */
01881   MODIFY_REG(COMP->CSR,
01882              (COMP_CSR_COMP1INSEL | (COMP_CSR_COMP1SW1 * __COMP_IS_INSTANCE_ODD(COMPx))) << __COMP_BITOFFSET_INSTANCE(COMPx),
01883              (InputMinus | InputPlus)                                        << __COMP_BITOFFSET_INSTANCE(COMPx) );
01884 }
01885
01886 /**
01887   * @brief  Set comparator input plus (non-inverting).
01888   * @note   In case of comparator input selected to be connected to IO:
01889   *         GPIO pins are specific to each comparator instance.
01890   *         Refer to description of parameters or to reference manual.
01891   * @rmtoll CSR         COMP1INSEL      LL_COMP_SetInputPlus\n
01892   *         CSR         COMP2INSEL      LL_COMP_SetInputPlus
01893   * @param  COMPx Comparator instance
01894   * @param  InputPlus This parameter can be one of the following values:
01895   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
01896   *         @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1)
01897   *
01898   *         (1) Parameter available only on COMP instance: COMP1.
01899   * @retval None
01900   */
01901 __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
01902 {
01903   /* Note: Connection switch is applicable only to COMP instance COMP1,       */
01904   /*       therefore if COMP2 is selected the equivalent bit is               */
01905   /*       kept unmodified.                                                   */
01906   MODIFY_REG(COMP->CSR,
01907              (COMP_CSR_COMP1SW1 * __COMP_IS_INSTANCE_ODD(COMPx)) << __COMP_BITOFFSET_INSTANCE(COMPx),
01908              InputPlus                                           << __COMP_BITOFFSET_INSTANCE(COMPx) );
01909 }
01910
01911 /**
01912   * @brief  Get comparator input plus (non-inverting).
01913   * @note   In case of comparator input selected to be connected to IO:
01914   *         GPIO pins are specific to each comparator instance.
01915   *         Refer to description of parameters or to reference manual.
01916   * @rmtoll CSR         COMP1INSEL      LL_COMP_GetInputPlus\n
01917   *         CSR         COMP2INSEL      LL_COMP_GetInputPlus
01918   * @param  COMPx Comparator instance
01919   * @retval Returned value can be one of the following values:
01920   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
01921   *         @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1)
01922   *
01923   *         (1) Parameter available only on COMP instance: COMP1.
01924   */
01925 __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
01926 {
01927   /* Note: Connection switch is applicable only to COMP instance COMP1,       */
01928   /*       therefore is COMP2 is selected the returned value will be null.    */
01929   return (uint32_t)(READ_BIT(COMP->CSR,
01930                              COMP_CSR_COMP1SW1 << __COMP_BITOFFSET_INSTANCE(COMPx))
01931                     >> __COMP_BITOFFSET_INSTANCE(COMPx)
01932                    );
01933 }
01934
01935 /**
01936   * @brief  Set comparator input minus (inverting).
01937   * @note   In case of comparator input selected to be connected to IO:
01938   *         GPIO pins are specific to each comparator instance.
01939   *         Refer to description of parameters or to reference manual.
01940   * @rmtoll CSR         COMP1SW1        LL_COMP_SetInputMinus
01941   * @param  COMPx Comparator instance
01942   * @param  InputMinus This parameter can be one of the following values:
01943   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
01944   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
01945   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
01946   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
01947   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
01948   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
01949   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
01950   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
01951   *         @arg @ref LL_COMP_INPUT_MINUS_IO3
01952   *         @arg @ref LL_COMP_INPUT_MINUS_IO4
01953   *         @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1
01954   * @retval None
01955   */
01956 __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
01957 {
01958   MODIFY_REG(COMP->CSR,
01959              COMP_CSR_COMP1INSEL << __COMP_BITOFFSET_INSTANCE(COMPx),
01960              InputMinus          << __COMP_BITOFFSET_INSTANCE(COMPx) );
01961 }
01962
01963 /**
01964   * @brief  Get comparator input minus (inverting).
01965   * @note   In case of comparator input selected to be connected to IO:
01966   *         GPIO pins are specific to each comparator instance.
01967   *         Refer to description of parameters or to reference manual.
01968   * @rmtoll CSR         COMP1SW1        LL_COMP_GetInputMinus
01969   * @param  COMPx Comparator instance
01970   * @retval Returned value can be one of the following values:
01971   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
01972   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
01973   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
01974   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
01975   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
01976   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
01977   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
01978   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
01979   *         @arg @ref LL_COMP_INPUT_MINUS_IO3
01980   *         @arg @ref LL_COMP_INPUT_MINUS_IO4
01981   *         @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1
01982   */
01983 __STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
01984 {
01985   return (uint32_t)(READ_BIT(COMP->CSR,
01986                              COMP_CSR_COMP1INSEL << __COMP_BITOFFSET_INSTANCE(COMPx))
01987                     >> __COMP_BITOFFSET_INSTANCE(COMPx)
01988                    );
01989 }
01990
01991 /**
01992   * @brief  Set comparator instance hysteresis mode of the input minus (inverting input).
01993   * @rmtoll CSR     COMP1HYST       LL_COMP_SetInputHysteresis\n
01994   *                 COMP2HYST       LL_COMP_SetInputHysteresis
01995   * @param  COMPx Comparator instance
01996   * @param  InputHysteresis This parameter can be one of the following values:
01997   *         @arg @ref LL_COMP_HYSTERESIS_NONE
01998   *         @arg @ref LL_COMP_HYSTERESIS_LOW
01999   *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM
02000   *         @arg @ref LL_COMP_HYSTERESIS_HIGH
02001   * @retval None
02002   */
02003 __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
02004 {
02005   MODIFY_REG(COMP->CSR,
02006              COMP_CSR_COMP1HYST << __COMP_BITOFFSET_INSTANCE(COMPx),
02007              InputHysteresis    << __COMP_BITOFFSET_INSTANCE(COMPx) );
02008 }
02009
02010 /**
02011   * @brief  Get comparator instance hysteresis mode of the minus (inverting) input.
02012   * @rmtoll CSR     COMP1HYST       LL_COMP_GetInputHysteresis\n
02013   *                 COMP2HYST       LL_COMP_GetInputHysteresis
02014   * @param  COMPx Comparator instance
02015   * @retval Returned value can be one of the following values:
02016   *         @arg @ref LL_COMP_HYSTERESIS_NONE
02017   *         @arg @ref LL_COMP_HYSTERESIS_LOW
02018   *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM
02019   *         @arg @ref LL_COMP_HYSTERESIS_HIGH
02020   */
02021 __STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
02022 {
02023   return (uint32_t)(READ_BIT(COMP->CSR,
02024                              COMP_CSR_COMP1HYST << __COMP_BITOFFSET_INSTANCE(COMPx))
02025                     >> __COMP_BITOFFSET_INSTANCE(COMPx)
02026                    );
02027
02028 }
02029
02030 /**
02031   * @}
02032   */
02033
02034 /** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
02035   * @{
02036   */
02037
02038 /**
02039   * @brief  Set comparator output selection.
02040   * @note   Availability of parameters of output selection to timer
02041   *         depends on timers availability on the selected device.
02042   * @rmtoll CSR     COMP1OUTSEL     LL_COMP_SetOutputSelection\n
02043   *                 COMP2OUTSEL     LL_COMP_SetOutputSelection
02044   * @param  COMPx Comparator instance
02045   * @param  OutputSelection This parameter can be one of the following values:
02046   *         @arg @ref LL_COMP_OUTPUT_NONE
02047   *         @arg @ref LL_COMP_OUTPUT_TIM16_BKIN     (1)
02048   *         @arg @ref LL_COMP_OUTPUT_TIM4_IC1       (1)
02049   *         @arg @ref LL_COMP_OUTPUT_TIM4_OCCLR     (1)
02050   *         @arg @ref LL_COMP_OUTPUT_TIM2_IC4       (1)
02051   *         @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR     (1)
02052   *         @arg @ref LL_COMP_OUTPUT_TIM3_IC1       (1)
02053   *         @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR     (1)
02054   *
02055   *         (1) Parameter availability depending on timer availability
02056   *             on the selected device.
02057   * @retval None
02058   */
02059 __STATIC_INLINE void LL_COMP_SetOutputSelection(COMP_TypeDef *COMPx, uint32_t OutputSelection)
02060 {
02061   MODIFY_REG(COMP->CSR,
02062              COMP_CSR_COMP1OUTSEL << __COMP_BITOFFSET_INSTANCE(COMPx),
02063              OutputSelection      << __COMP_BITOFFSET_INSTANCE(COMPx) );
02064 }
02065
02066 /**
02067   * @brief  Get comparator output selection.
02068   * @note   Availability of parameters of output selection to timer
02069   *         depends on timers availability on the selected device.
02070   * @rmtoll CSR     COMP1OUTSEL     LL_COMP_GetOutputSelection\n
02071   *                 COMP2OUTSEL     LL_COMP_GetOutputSelection
02072   * @param  COMPx Comparator instance
02073   * @retval Returned value can be one of the following values:
02074   *         @arg @ref LL_COMP_OUTPUT_NONE
02075   *         @arg @ref LL_COMP_OUTPUT_TIM16_BKIN     (1)
02076   *         @arg @ref LL_COMP_OUTPUT_TIM4_IC1       (1)
02077   *         @arg @ref LL_COMP_OUTPUT_TIM4_OCCLR     (1)
02078   *         @arg @ref LL_COMP_OUTPUT_TIM2_IC4       (1)
02079   *         @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR     (1)
02080   *         @arg @ref LL_COMP_OUTPUT_TIM3_IC1       (1)
02081   *         @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR     (1)
02082   *
02083   *         (1) Parameter availability depending on timer availability
02084   *             on the selected device.
02085   */
02086 __STATIC_INLINE uint32_t LL_COMP_GetOutputSelection(COMP_TypeDef *COMPx)
02087 {
02088   return (uint32_t)(READ_BIT(COMP->CSR,
02089                              COMP_CSR_COMP1OUTSEL << __COMP_BITOFFSET_INSTANCE(COMPx))
02090                     >> __COMP_BITOFFSET_INSTANCE(COMPx)
02091                    );
02092 }
02093
02094 /**
02095   * @brief  Set comparator instance output polarity.
02096   * @rmtoll CSR         COMP1POL        LL_COMP_SetOutputPolarity\n
02097   *                     COMP2POL        LL_COMP_SetOutputPolarity
02098   * @param  COMPx Comparator instance
02099   * @param  OutputPolarity This parameter can be one of the following values:
02100   *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
02101   *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
02102   * @retval None
02103   */
02104 __STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
02105 {
02106   MODIFY_REG(COMP->CSR,
02107              COMP_CSR_COMP1POL << __COMP_BITOFFSET_INSTANCE(COMPx),
02108              OutputPolarity    << __COMP_BITOFFSET_INSTANCE(COMPx) );
02109 }
02110
02111 /**
02112   * @brief  Get comparator instance output polarity.
02113   * @rmtoll CSR         COMP1POL        LL_COMP_GetOutputPolarity\n
02114   *                     COMP2POL        LL_COMP_GetOutputPolarity
02115   * @param  COMPx Comparator instance
02116   * @retval Returned value can be one of the following values:
02117   *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
02118   *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
02119   */
02120 __STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
02121 {
02122   return (uint32_t)(READ_BIT(COMP->CSR,
02123                              COMP_CSR_COMP1POL << __COMP_BITOFFSET_INSTANCE(COMPx))
02124                     >> __COMP_BITOFFSET_INSTANCE(COMPx)
02125                    );
02126 }
02127
02128 /**
02129   * @}
02130   */
02131
02132 /** @defgroup COMP_LL_EF_Operation Operation on comparator instance
02133   * @{
02134   */
02135
02136 /**
02137   * @brief  Enable comparator instance.
02138   * @note   After enable from off state, comparator requires a delay
02139   *         to reach reach propagation delay specification.
02140   *         Refer to device datasheet, parameter "tSTART".
02141   * @rmtoll CSR         COMP1EN         LL_COMP_Enable\n
02142   *                     COMP2EN         LL_COMP_Enable
02143   * @param  COMPx Comparator instance
02144   * @retval None
02145   */
02146 __STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
02147 {
02148   SET_BIT(COMP->CSR, COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx));
02149 }
02150
02151 /**
02152   * @brief  Disable comparator instance.
02153   * @rmtoll CSR         COMP1EN         LL_COMP_Disable\n
02154   *                     COMP2EN         LL_COMP_Disable
02155   * @param  COMPx Comparator instance
02156   * @retval None
02157   */
02158 __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
02159 {
02160   CLEAR_BIT(COMP->CSR, COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx));
02161 }
02162
02163 /**
02164   * @brief  Get comparator enable state
02165   *         (0: COMP is disabled, 1: COMP is enabled)
02166   * @rmtoll CSR         COMP1EN         LL_COMP_IsEnabled\n
02167   *                     COMP2EN         LL_COMP_IsEnabled
02168   * @param  COMPx Comparator instance
02169   * @retval State of bit (1 or 0).
02170   */
02171 __STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
02172 {
02173   return (READ_BIT(COMP->CSR, COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx)) == COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx));
02174 }
02175
02176 /**
02177   * @brief  Lock comparator instance.
02178   * @note   Once locked, comparator configuration can be accessed in read-only.
02179   * @note   The only way to unlock the comparator is a device hardware reset.
02180   * @rmtoll CSR         COMP1LOCK       LL_COMP_Lock\n
02181   *                     COMP2LOCK       LL_COMP_Lock
02182   * @param  COMPx Comparator instance
02183   * @retval None
02184   */
02185 __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
02186 {
02187   SET_BIT(COMP->CSR, COMP_CSR_COMP1LOCK << __COMP_BITOFFSET_INSTANCE(COMPx));
02188 }
02189
02190 /**
02191   * @brief  Get comparator lock state
02192   *         (0: COMP is unlocked, 1: COMP is locked).
02193   * @note   Once locked, comparator configuration can be accessed in read-only.
02194   * @note   The only way to unlock the comparator is a device hardware reset.
02195   * @rmtoll CSR         COMP1LOCK       LL_COMP_IsLocked\n
02196   *                     COMP2LOCK       LL_COMP_IsLocked
02197   * @param  COMPx Comparator instance
02198   * @retval State of bit (1 or 0).
02199   */
02200 __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
02201 {
02202   return (READ_BIT(COMP->CSR, COMP_CSR_COMP1LOCK << __COMP_BITOFFSET_INSTANCE(COMPx)) == COMP_CSR_COMP1LOCK << __COMP_BITOFFSET_INSTANCE(COMPx));
02203 }
02204
02205 /**
02206   * @brief  Read comparator instance output level.
02207   * @note   The comparator output level depends on the selected polarity
02208   *         (Refer to function @ref LL_COMP_SetOutputPolarity()).
02209   *         If the comparator polarity is not inverted:
02210   *          - Comparator output is low when the input plus
02211   *            is at a lower voltage than the input minus
02212   *          - Comparator output is high when the input plus
02213   *            is at a higher voltage than the input minus
02214   *         If the comparator polarity is inverted:
02215   *          - Comparator output is high when the input plus
02216   *            is at a lower voltage than the input minus
02217   *          - Comparator output is low when the input plus
02218   *            is at a higher voltage than the input minus
02219   * @rmtoll CSR         COMP1OUT        LL_COMP_ReadOutputLevel\n
02220   *                     COMP2OUT        LL_COMP_ReadOutputLevel
02221   * @param  COMPx Comparator instance
02222   * @retval Returned value can be one of the following values:
02223   *         @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
02224   *         @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
02225   */
02226 __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
02227 {
02228   return (uint32_t)(READ_BIT(COMP->CSR,
02229                              COMP_CSR_COMP1OUT << __COMP_BITOFFSET_INSTANCE(COMPx))
02230                     >> (__COMP_BITOFFSET_INSTANCE(COMPx) + LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS)
02231                    );
02232 }
02233
02234 /**
02235   * @}
02236   */
02237
02238 #if defined(USE_FULL_LL_DRIVER)
02239 /** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
02240   * @{
02241   */
02242
02243 ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
02244 ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
02245 void        LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
02246
02247 /**
02248   * @}
02249   */
02250 #endif /* USE_FULL_LL_DRIVER */
02251
02252 /**
02253   * @}
02254   */
02255
02256 /**
02257   * @}
02258   */
02259
02260 #endif /* COMP1 || COMP2 */
02261
02262
02263 #endif /* STM32F373xC || STM32F378xx */
02264
02265 /**
02266   * @}
02267   */
02268
02269 #ifdef __cplusplus
02270 }
02271 #endif
02272
02273 #endif /* __STM32F3xx_LL_COMP_H */
02274
02275 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_cortex.h Source File

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stm32f3xx_ll_cortex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_cortex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CORTEX LL module.
00006   @verbatim
00007   ==============================================================================
00008                      ##### How to use this driver #####
00009   ==============================================================================
00010     [..]
00011     The LL CORTEX driver contains a set of generic APIs that can be
00012     used by user:
00013       (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
00014           functions
00015       (+) Low power mode configuration (SCB register of Cortex-MCU)
00016       (+) MPU API to configure and enable regions
00017           (MPU services provided only on some devices)
00018       (+) API to access to MCU info (CPUID register)
00019       (+) API to enable fault handler (SHCSR accesses)
00020
00021   @endverbatim
00022   ******************************************************************************
00023   * @attention
00024   *
00025   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00026   *
00027   * Redistribution and use in source and binary forms, with or without modification,
00028   * are permitted provided that the following conditions are met:
00029   *   1. Redistributions of source code must retain the above copyright notice,
00030   *      this list of conditions and the following disclaimer.
00031   *   2. Redistributions in binary form must reproduce the above copyright notice,
00032   *      this list of conditions and the following disclaimer in the documentation
00033   *      and/or other materials provided with the distribution.
00034   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00035   *      may be used to endorse or promote products derived from this software
00036   *      without specific prior written permission.
00037   *
00038   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00039   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00040   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00041   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00042   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00043   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00044   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00045   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00046   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00047   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00048   *
00049   ******************************************************************************
00050   */
00051
00052 /* Define to prevent recursive inclusion -------------------------------------*/
00053 #ifndef __STM32F3xx_LL_CORTEX_H
00054 #define __STM32F3xx_LL_CORTEX_H
00055
00056 #ifdef __cplusplus
00057 extern "C" {
00058 #endif
00059
00060 /* Includes ------------------------------------------------------------------*/
00061 #include "stm32f3xx.h"
00062
00063 /** @addtogroup STM32F3xx_LL_Driver
00064   * @{
00065   */
00066
00067 /** @defgroup CORTEX_LL CORTEX
00068   * @{
00069   */
00070
00071 /* Private types -------------------------------------------------------------*/
00072 /* Private variables ---------------------------------------------------------*/
00073
00074 /* Private constants ---------------------------------------------------------*/
00075
00076 /* Private macros ------------------------------------------------------------*/
00077
00078 /* Exported types ------------------------------------------------------------*/
00079 /* Exported constants --------------------------------------------------------*/
00080 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
00081   * @{
00082   */
00083
00084 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
00085   * @{
00086   */
00087 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
00088 #define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
00089 /**
00090   * @}
00091   */
00092
00093 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
00094   * @{
00095   */
00096 #define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
00097 #define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
00098 #define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
00099 /**
00100   * @}
00101   */
00102
00103 #if __MPU_PRESENT
00104
00105 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
00106   * @{
00107   */
00108 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
00109 #define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
00110 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
00111 #define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
00112 /**
00113   * @}
00114   */
00115
00116 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
00117   * @{
00118   */
00119 #define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
00120 #define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
00121 #define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
00122 #define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
00123 #define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
00124 #define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
00125 #define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
00126 #define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
00132   * @{
00133   */
00134 #define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
00135 #define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
00136 #define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
00137 #define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
00138 #define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
00139 #define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
00140 #define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
00141 #define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
00142 #define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
00143 #define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
00144 #define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
00145 #define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
00146 #define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
00147 #define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
00148 #define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
00149 #define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
00150 #define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
00151 #define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
00152 #define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
00153 #define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
00154 #define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
00155 #define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
00156 #define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
00157 #define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
00158 #define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
00159 #define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
00160 #define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
00161 #define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
00167   * @{
00168   */
00169 #define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
00170 #define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
00171 #define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
00172 #define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
00173 #define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
00174 #define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
00175 /**
00176   * @}
00177   */
00178
00179 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
00180   * @{
00181   */
00182 #define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
00183 #define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
00184 #define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
00185 #define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
00191   * @{
00192   */
00193 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
00194 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
00200   * @{
00201   */
00202 #define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
00203 #define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
00209   * @{
00210   */
00211 #define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
00212 #define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
00218   * @{
00219   */
00220 #define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
00221 #define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
00222 /**
00223   * @}
00224   */
00225 #endif /* __MPU_PRESENT */
00226 /**
00227   * @}
00228   */
00229
00230 /* Exported macro ------------------------------------------------------------*/
00231
00232 /* Exported functions --------------------------------------------------------*/
00233 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
00234   * @{
00235   */
00236
00237 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
00238   * @{
00239   */
00240
00241 /**
00242   * @brief  This function checks if the Systick counter flag is active or not.
00243   * @note   It can be used in timeout function on application side.
00244   * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
00245   * @retval State of bit (1 or 0).
00246   */
00247 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
00248 {
00249   return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
00250 }
00251
00252 /**
00253   * @brief  Configures the SysTick clock source
00254   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
00255   * @param  Source This parameter can be one of the following values:
00256   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
00257   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
00258   * @retval None
00259   */
00260 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
00261 {
00262   if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
00263   {
00264     SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00265   }
00266   else
00267   {
00268     CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00269   }
00270 }
00271
00272 /**
00273   * @brief  Get the SysTick clock source
00274   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
00275   * @retval Returned value can be one of the following values:
00276   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
00277   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
00278   */
00279 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
00280 {
00281   return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00282 }
00283
00284 /**
00285   * @brief  Enable SysTick exception request
00286   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
00287   * @retval None
00288   */
00289 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
00290 {
00291   SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
00292 }
00293
00294 /**
00295   * @brief  Disable SysTick exception request
00296   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
00297   * @retval None
00298   */
00299 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
00300 {
00301   CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
00302 }
00303
00304 /**
00305   * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
00306   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
00307   * @retval State of bit (1 or 0).
00308   */
00309 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
00310 {
00311   return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
00312 }
00313
00314 /**
00315   * @}
00316   */
00317
00318 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
00319   * @{
00320   */
00321
00322 /**
00323   * @brief  Processor uses sleep as its low power mode
00324   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
00325   * @retval None
00326   */
00327 __STATIC_INLINE void LL_LPM_EnableSleep(void)
00328 {
00329   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00330   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00331 }
00332
00333 /**
00334   * @brief  Processor uses deep sleep as its low power mode
00335   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
00336   * @retval None
00337   */
00338 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
00339 {
00340   /* Set SLEEPDEEP bit of Cortex System Control Register */
00341   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00342 }
00343
00344 /**
00345   * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
00346   * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
00347   *         empty main application.
00348   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
00349   * @retval None
00350   */
00351 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
00352 {
00353   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00354   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00355 }
00356
00357 /**
00358   * @brief  Do not sleep when returning to Thread mode.
00359   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
00360   * @retval None
00361   */
00362 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
00363 {
00364   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00365   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00366 }
00367
00368 /**
00369   * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
00370   *         processor.
00371   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
00372   * @retval None
00373   */
00374 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
00375 {
00376   /* Set SEVEONPEND bit of Cortex System Control Register */
00377   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00378 }
00379
00380 /**
00381   * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
00382   *         excluded
00383   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
00384   * @retval None
00385   */
00386 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
00387 {
00388   /* Clear SEVEONPEND bit of Cortex System Control Register */
00389   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00390 }
00391
00392 /**
00393   * @}
00394   */
00395
00396 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
00397   * @{
00398   */
00399
00400 /**
00401   * @brief  Enable a fault in System handler control register (SHCSR)
00402   * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
00403   * @param  Fault This parameter can be a combination of the following values:
00404   *         @arg @ref LL_HANDLER_FAULT_USG
00405   *         @arg @ref LL_HANDLER_FAULT_BUS
00406   *         @arg @ref LL_HANDLER_FAULT_MEM
00407   * @retval None
00408   */
00409 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
00410 {
00411   /* Enable the system handler fault */
00412   SET_BIT(SCB->SHCSR, Fault);
00413 }
00414
00415 /**
00416   * @brief  Disable a fault in System handler control register (SHCSR)
00417   * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
00418   * @param  Fault This parameter can be a combination of the following values:
00419   *         @arg @ref LL_HANDLER_FAULT_USG
00420   *         @arg @ref LL_HANDLER_FAULT_BUS
00421   *         @arg @ref LL_HANDLER_FAULT_MEM
00422   * @retval None
00423   */
00424 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
00425 {
00426   /* Disable the system handler fault */
00427   CLEAR_BIT(SCB->SHCSR, Fault);
00428 }
00429
00430 /**
00431   * @}
00432   */
00433
00434 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
00435   * @{
00436   */
00437
00438 /**
00439   * @brief  Get Implementer code
00440   * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
00441   * @retval Value should be equal to 0x41 for ARM
00442   */
00443 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
00444 {
00445   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
00446 }
00447
00448 /**
00449   * @brief  Get Variant number (The r value in the rnpn product revision identifier)
00450   * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
00451   * @retval Value between 0 and 255 (0x0: revision 0)
00452   */
00453 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
00454 {
00455   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
00456 }
00457
00458 /**
00459   * @brief  Get Constant number
00460   * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
00461   * @retval Value should be equal to 0xF for Cortex-M4 devices
00462   */
00463 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
00464 {
00465   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
00466 }
00467
00468 /**
00469   * @brief  Get Part number
00470   * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
00471   * @retval Value should be equal to 0xC24 for Cortex-M4
00472   */
00473 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
00474 {
00475   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
00476 }
00477
00478 /**
00479   * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
00480   * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
00481   * @retval Value between 0 and 255 (0x1: patch 1)
00482   */
00483 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
00484 {
00485   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
00486 }
00487
00488 /**
00489   * @}
00490   */
00491
00492 #if __MPU_PRESENT
00493 /** @defgroup CORTEX_LL_EF_MPU MPU
00494   * @{
00495   */
00496
00497 /**
00498   * @brief  Enable MPU with input options
00499   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
00500   * @param  Options This parameter can be one of the following values:
00501   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
00502   *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
00503   *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
00504   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
00505   * @retval None
00506   */
00507 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
00508 {
00509   /* Enable the MPU*/
00510   WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
00511   /* Ensure MPU settings take effects */
00512   __DSB();
00513   /* Sequence instruction fetches using update settings */
00514   __ISB();
00515 }
00516
00517 /**
00518   * @brief  Disable MPU
00519   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
00520   * @retval None
00521   */
00522 __STATIC_INLINE void LL_MPU_Disable(void)
00523 {
00524   /* Make sure outstanding transfers are done */
00525   __DMB();
00526   /* Disable MPU*/
00527   WRITE_REG(MPU->CTRL, 0U);
00528 }
00529
00530 /**
00531   * @brief  Check if MPU is enabled or not
00532   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
00533   * @retval State of bit (1 or 0).
00534   */
00535 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
00536 {
00537   return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
00538 }
00539
00540 /**
00541   * @brief  Enable a MPU region
00542   * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
00543   * @param  Region This parameter can be one of the following values:
00544   *         @arg @ref LL_MPU_REGION_NUMBER0
00545   *         @arg @ref LL_MPU_REGION_NUMBER1
00546   *         @arg @ref LL_MPU_REGION_NUMBER2
00547   *         @arg @ref LL_MPU_REGION_NUMBER3
00548   *         @arg @ref LL_MPU_REGION_NUMBER4
00549   *         @arg @ref LL_MPU_REGION_NUMBER5
00550   *         @arg @ref LL_MPU_REGION_NUMBER6
00551   *         @arg @ref LL_MPU_REGION_NUMBER7
00552   * @retval None
00553   */
00554 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
00555 {
00556   /* Set Region number */
00557   WRITE_REG(MPU->RNR, Region);
00558   /* Enable the MPU region */
00559   SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
00560 }
00561
00562 /**
00563   * @brief  Configure and enable a region
00564   * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
00565   *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
00566   *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
00567   *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
00568   *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
00569   *         MPU_RASR     S             LL_MPU_ConfigRegion\n
00570   *         MPU_RASR     C             LL_MPU_ConfigRegion\n
00571   *         MPU_RASR     B             LL_MPU_ConfigRegion\n
00572   *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
00573   * @param  Region This parameter can be one of the following values:
00574   *         @arg @ref LL_MPU_REGION_NUMBER0
00575   *         @arg @ref LL_MPU_REGION_NUMBER1
00576   *         @arg @ref LL_MPU_REGION_NUMBER2
00577   *         @arg @ref LL_MPU_REGION_NUMBER3
00578   *         @arg @ref LL_MPU_REGION_NUMBER4
00579   *         @arg @ref LL_MPU_REGION_NUMBER5
00580   *         @arg @ref LL_MPU_REGION_NUMBER6
00581   *         @arg @ref LL_MPU_REGION_NUMBER7
00582   * @param  Address Value of region base address
00583   * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
00584   * @param  Attributes This parameter can be a combination of the following values:
00585   *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
00586   *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
00587   *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
00588   *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
00589   *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
00590   *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
00591   *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
00592   *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
00593   *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
00594   *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
00595   *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
00596   *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
00597   *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
00598   * @retval None
00599   */
00600 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
00601 {
00602   /* Set Region number */
00603   WRITE_REG(MPU->RNR, Region);
00604   /* Set base address */
00605   WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
00606   /* Configure MPU */
00607   WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
00608 }
00609
00610 /**
00611   * @brief  Disable a region
00612   * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
00613   *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
00614   * @param  Region This parameter can be one of the following values:
00615   *         @arg @ref LL_MPU_REGION_NUMBER0
00616   *         @arg @ref LL_MPU_REGION_NUMBER1
00617   *         @arg @ref LL_MPU_REGION_NUMBER2
00618   *         @arg @ref LL_MPU_REGION_NUMBER3
00619   *         @arg @ref LL_MPU_REGION_NUMBER4
00620   *         @arg @ref LL_MPU_REGION_NUMBER5
00621   *         @arg @ref LL_MPU_REGION_NUMBER6
00622   *         @arg @ref LL_MPU_REGION_NUMBER7
00623   * @retval None
00624   */
00625 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
00626 {
00627   /* Set Region number */
00628   WRITE_REG(MPU->RNR, Region);
00629   /* Disable the MPU region */
00630   CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
00631 }
00632
00633 /**
00634   * @}
00635   */
00636
00637 #endif /* __MPU_PRESENT */
00638 /**
00639   * @}
00640   */
00641
00642 /**
00643   * @}
00644   */
00645
00646 /**
00647   * @}
00648   */
00649
00650 #ifdef __cplusplus
00651 }
00652 #endif
00653
00654 #endif /* __STM32F3xx_LL_CORTEX_H */
00655
00656 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_crc.c Source File

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stm32f3xx_ll_crc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_crc.c
00004   * @author  MCD Application Team
00005   * @brief   CRC LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 #if defined(USE_FULL_LL_DRIVER)
00036
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f3xx_ll_crc.h"
00039
00040 #ifdef  USE_FULL_ASSERT
00041 #include "stm32_assert.h"
00042 #else
00043 #define assert_param(expr) ((void)0U)
00044 #endif
00045
00046 /** @addtogroup STM32F3xx_LL_Driver
00047   * @{
00048   */
00049
00050 #if defined (CRC)
00051
00052 /** @addtogroup CRC_LL
00053   * @{
00054   */
00055
00056 /* Private types -------------------------------------------------------------*/
00057 /* Private variables ---------------------------------------------------------*/
00058 /* Private constants ---------------------------------------------------------*/
00059 /* Private macros ------------------------------------------------------------*/
00060 /* Private function prototypes -----------------------------------------------*/
00061
00062 /* Exported functions --------------------------------------------------------*/
00063 /** @addtogroup CRC_LL_Exported_Functions
00064   * @{
00065   */
00066
00067 /** @addtogroup CRC_LL_EF_Init
00068   * @{
00069   */
00070
00071 /**
00072   * @brief  De-initialize CRC registers (Registers restored to their default values).
00073   * @param  CRCx CRC Instance
00074   * @retval An ErrorStatus enumeration value:
00075   *          - SUCCESS: CRC registers are de-initialized
00076   *          - ERROR: CRC registers are not de-initialized
00077   */
00078 ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
00079 {
00080   ErrorStatus status = SUCCESS;
00081
00082   /* Check the parameters */
00083   assert_param(IS_CRC_ALL_INSTANCE(CRCx));
00084
00085   if (CRCx == CRC)
00086   {
00087     /* Set programmable polynomial size in CR register to reset value (32 bits)*/
00088     LL_CRC_SetPolynomialSize(CRCx, LL_CRC_POLYLENGTH_32B);
00089
00090     /* Set programmable polynomial in POL register to reset value */
00091     LL_CRC_SetPolynomialCoef(CRCx, LL_CRC_DEFAULT_CRC32_POLY);
00092
00093     /* Set INIT register to reset value */
00094     LL_CRC_SetInitialData(CRCx, LL_CRC_DEFAULT_CRC_INITVALUE);
00095
00096     /* Set Reversibility options on I/O data values in CR register to reset value */
00097     LL_CRC_SetInputDataReverseMode(CRCx, LL_CRC_INDATA_REVERSE_NONE);
00098     LL_CRC_SetOutputDataReverseMode(CRCx, LL_CRC_OUTDATA_REVERSE_NONE);
00099
00100     /* Reset the CRC calculation unit */
00101     LL_CRC_ResetCRCCalculationUnit(CRCx);
00102
00103     /* Reset IDR register */
00104     LL_CRC_Write_IDR(CRCx, 0x00U);
00105   }
00106   else
00107   {
00108     status = ERROR;
00109   }
00110
00111   return (status);
00112 }
00113
00114 /**
00115   * @}
00116   */
00117
00118 /**
00119   * @}
00120   */
00121
00122 /**
00123   * @}
00124   */
00125
00126 #endif /* defined (CRC) */
00127
00128 /**
00129   * @}
00130   */
00131
00132 #endif /* USE_FULL_LL_DRIVER */
00133
00134 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00135
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_crc.h Source File

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stm32f3xx_ll_crc.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_crc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_CRC_H
00038 #define __STM32F3xx_LL_CRC_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined(CRC)
00052
00053 /** @defgroup CRC_LL CRC
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059 /* Private constants ---------------------------------------------------------*/
00060 /* Private macros ------------------------------------------------------------*/
00061
00062 /* Exported types ------------------------------------------------------------*/
00063 /* Exported constants --------------------------------------------------------*/
00064 /** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
00065   * @{
00066   */
00067
00068 /** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
00069   * @{
00070   */
00071 #define LL_CRC_POLYLENGTH_32B              0x00000000U                              /*!< 32 bits Polynomial size */
00072 #define LL_CRC_POLYLENGTH_16B              CRC_CR_POLYSIZE_0                        /*!< 16 bits Polynomial size */
00073 #define LL_CRC_POLYLENGTH_8B               CRC_CR_POLYSIZE_1                        /*!< 8 bits Polynomial size */
00074 #define LL_CRC_POLYLENGTH_7B               (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)  /*!< 7 bits Polynomial size */
00075 /**
00076   * @}
00077   */
00078
00079 /** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
00080   * @{
00081   */
00082 #define LL_CRC_INDATA_REVERSE_NONE         0x00000000U                              /*!< Input Data bit order not affected */
00083 #define LL_CRC_INDATA_REVERSE_BYTE         CRC_CR_REV_IN_0                          /*!< Input Data bit reversal done by byte */
00084 #define LL_CRC_INDATA_REVERSE_HALFWORD     CRC_CR_REV_IN_1                          /*!< Input Data bit reversal done by half-word */
00085 #define LL_CRC_INDATA_REVERSE_WORD         (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)      /*!< Input Data bit reversal done by word */
00086 /**
00087   * @}
00088   */
00089
00090 /** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
00091   * @{
00092   */
00093 #define LL_CRC_OUTDATA_REVERSE_NONE        0x00000000U                               /*!< Output Data bit order not affected */
00094 #define LL_CRC_OUTDATA_REVERSE_BIT         CRC_CR_REV_OUT                            /*!< Output Data bit reversal done by bit */
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup CRC_LL_EC_Default_Polynomial_Value    Default CRC generating polynomial value
00100   * @brief    Normal representation of this polynomial value is
00101   *           X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
00102   * @{
00103   */
00104 #define LL_CRC_DEFAULT_CRC32_POLY          0x04C11DB7U                               /*!< Default CRC generating polynomial value */
00105 /**
00106   * @}
00107   */
00108
00109 /** @defgroup CRC_LL_EC_Default_InitValue    Default CRC computation initialization value
00110   * @{
00111   */
00112 #define LL_CRC_DEFAULT_CRC_INITVALUE       0xFFFFFFFFU                               /*!< Default CRC computation initialization value */
00113 /**
00114   * @}
00115   */
00116
00117 /**
00118   * @}
00119   */
00120
00121 /* Exported macro ------------------------------------------------------------*/
00122 /** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
00123   * @{
00124   */
00125
00126 /** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
00127   * @{
00128   */
00129
00130 /**
00131   * @brief  Write a value in CRC register
00132   * @param  __INSTANCE__ CRC Instance
00133   * @param  __REG__ Register to be written
00134   * @param  __VALUE__ Value to be written in the register
00135   * @retval None
00136   */
00137 #define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00138
00139 /**
00140   * @brief  Read a value in CRC register
00141   * @param  __INSTANCE__ CRC Instance
00142   * @param  __REG__ Register to be read
00143   * @retval Register value
00144   */
00145 #define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00146 /**
00147   * @}
00148   */
00149
00150 /**
00151   * @}
00152   */
00153
00154
00155 /* Exported functions --------------------------------------------------------*/
00156 /** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
00157   * @{
00158   */
00159
00160 /** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
00161   * @{
00162   */
00163
00164 /**
00165   * @brief  Reset the CRC calculation unit.
00166   * @note   If Programmable Initial CRC value feature
00167   *         is available, also set the Data Register to the value stored in the
00168   *         CRC_INIT register, otherwise, reset Data Register to its default value.
00169   * @rmtoll CR           RESET         LL_CRC_ResetCRCCalculationUnit
00170   * @param  CRCx CRC Instance
00171   * @retval None
00172   */
00173 __STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
00174 {
00175   SET_BIT(CRCx->CR, CRC_CR_RESET);
00176 }
00177
00178 /**
00179   * @brief  Configure size of the polynomial.
00180   * @rmtoll CR           POLYSIZE      LL_CRC_SetPolynomialSize
00181   * @param  CRCx CRC Instance
00182   * @param  PolySize This parameter can be one of the following values:
00183   *         @arg @ref LL_CRC_POLYLENGTH_32B
00184   *         @arg @ref LL_CRC_POLYLENGTH_16B
00185   *         @arg @ref LL_CRC_POLYLENGTH_8B
00186   *         @arg @ref LL_CRC_POLYLENGTH_7B
00187   * @retval None
00188   */
00189 __STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
00190 {
00191   MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
00192 }
00193
00194 /**
00195   * @brief  Return size of the polynomial.
00196   * @rmtoll CR           POLYSIZE      LL_CRC_GetPolynomialSize
00197   * @param  CRCx CRC Instance
00198   * @retval Returned value can be one of the following values:
00199   *         @arg @ref LL_CRC_POLYLENGTH_32B
00200   *         @arg @ref LL_CRC_POLYLENGTH_16B
00201   *         @arg @ref LL_CRC_POLYLENGTH_8B
00202   *         @arg @ref LL_CRC_POLYLENGTH_7B
00203   */
00204 __STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
00205 {
00206   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
00207 }
00208
00209 /**
00210   * @brief  Configure the reversal of the bit order of the input data
00211   * @rmtoll CR           REV_IN        LL_CRC_SetInputDataReverseMode
00212   * @param  CRCx CRC Instance
00213   * @param  ReverseMode This parameter can be one of the following values:
00214   *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
00215   *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
00216   *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
00217   *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
00218   * @retval None
00219   */
00220 __STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
00221 {
00222   MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
00223 }
00224
00225 /**
00226   * @brief  Return type of reversal for input data bit order
00227   * @rmtoll CR           REV_IN        LL_CRC_GetInputDataReverseMode
00228   * @param  CRCx CRC Instance
00229   * @retval Returned value can be one of the following values:
00230   *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
00231   *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
00232   *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
00233   *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
00234   */
00235 __STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
00236 {
00237   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
00238 }
00239
00240 /**
00241   * @brief  Configure the reversal of the bit order of the Output data
00242   * @rmtoll CR           REV_OUT       LL_CRC_SetOutputDataReverseMode
00243   * @param  CRCx CRC Instance
00244   * @param  ReverseMode This parameter can be one of the following values:
00245   *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
00246   *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
00247   * @retval None
00248   */
00249 __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
00250 {
00251   MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
00252 }
00253
00254 /**
00255   * @brief  Configure the reversal of the bit order of the Output data
00256   * @rmtoll CR           REV_OUT       LL_CRC_GetOutputDataReverseMode
00257   * @param  CRCx CRC Instance
00258   * @retval Returned value can be one of the following values:
00259   *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
00260   *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
00261   */
00262 __STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
00263 {
00264   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
00265 }
00266
00267 /**
00268   * @brief  Initialize the Programmable initial CRC value.
00269   * @note   If the CRC size is less than 32 bits, the least significant bits
00270   *         are used to write the correct value
00271   * @note   LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
00272   * @rmtoll INIT         INIT          LL_CRC_SetInitialData
00273   * @param  CRCx CRC Instance
00274   * @param  InitCrc Value to be programmed in Programmable initial CRC value register
00275   * @retval None
00276   */
00277 __STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
00278 {
00279   WRITE_REG(CRCx->INIT, InitCrc);
00280 }
00281
00282 /**
00283   * @brief  Return current Initial CRC value.
00284   * @note   If the CRC size is less than 32 bits, the least significant bits
00285   *         are used to read the correct value
00286   * @rmtoll INIT         INIT          LL_CRC_GetInitialData
00287   * @param  CRCx CRC Instance
00288   * @retval Value programmed in Programmable initial CRC value register
00289   */
00290 __STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
00291 {
00292   return (uint32_t)(READ_REG(CRCx->INIT));
00293 }
00294
00295 /**
00296   * @brief  Initialize the Programmable polynomial value
00297   *         (coefficients of the polynomial to be used for CRC calculation).
00298   * @note   LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
00299   * @note   Please check Reference Manual and existing Errata Sheets,
00300   *         regarding possible limitations for Polynomial values usage.
00301   *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00302   * @rmtoll POL          POL           LL_CRC_SetPolynomialCoef
00303   * @param  CRCx CRC Instance
00304   * @param  PolynomCoef Value to be programmed in Programmable Polynomial value register
00305   * @retval None
00306   */
00307 __STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
00308 {
00309   WRITE_REG(CRCx->POL, PolynomCoef);
00310 }
00311
00312 /**
00313   * @brief  Return current Programmable polynomial value
00314   * @note   Please check Reference Manual and existing Errata Sheets,
00315   *         regarding possible limitations for Polynomial values usage.
00316   *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00317   * @rmtoll POL          POL           LL_CRC_GetPolynomialCoef
00318   * @param  CRCx CRC Instance
00319   * @retval Value programmed in Programmable Polynomial value register
00320   */
00321 __STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
00322 {
00323   return (uint32_t)(READ_REG(CRCx->POL));
00324 }
00325
00326 /**
00327   * @}
00328   */
00329
00330 /** @defgroup CRC_LL_EF_Data_Management Data_Management
00331   * @{
00332   */
00333
00334 /**
00335   * @brief  Write given 32-bit data to the CRC calculator
00336   * @rmtoll DR           DR            LL_CRC_FeedData32
00337   * @param  CRCx CRC Instance
00338   * @param  InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
00339   * @retval None
00340   */
00341 __STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
00342 {
00343   WRITE_REG(CRCx->DR, InData);
00344 }
00345
00346 /**
00347   * @brief  Write given 16-bit data to the CRC calculator
00348   * @rmtoll DR           DR            LL_CRC_FeedData16
00349   * @param  CRCx CRC Instance
00350   * @param  InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
00351   * @retval None
00352   */
00353 __STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
00354 {
00355   *(uint16_t __IO *)(&CRCx->DR) = (uint16_t) InData;
00356 }
00357
00358 /**
00359   * @brief  Write given 8-bit data to the CRC calculator
00360   * @rmtoll DR           DR            LL_CRC_FeedData8
00361   * @param  CRCx CRC Instance
00362   * @param  InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
00363   * @retval None
00364   */
00365 __STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
00366 {
00367   *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
00368 }
00369
00370 /**
00371   * @brief  Return current CRC calculation result. 32 bits value is returned.
00372   * @rmtoll DR           DR            LL_CRC_ReadData32
00373   * @param  CRCx CRC Instance
00374   * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
00375   */
00376 __STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
00377 {
00378   return (uint32_t)(READ_REG(CRCx->DR));
00379 }
00380
00381 /**
00382   * @brief  Return current CRC calculation result. 16 bits value is returned.
00383   * @note   This function is expected to be used in a 16 bits CRC polynomial size context.
00384   * @rmtoll DR           DR            LL_CRC_ReadData16
00385   * @param  CRCx CRC Instance
00386   * @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
00387   */
00388 __STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
00389 {
00390   return (uint16_t)READ_REG(CRCx->DR);
00391 }
00392
00393 /**
00394   * @brief  Return current CRC calculation result. 8 bits value is returned.
00395   * @note   This function is expected to be used in a 8 bits CRC polynomial size context.
00396   * @rmtoll DR           DR            LL_CRC_ReadData8
00397   * @param  CRCx CRC Instance
00398   * @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
00399   */
00400 __STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
00401 {
00402   return (uint8_t)READ_REG(CRCx->DR);
00403 }
00404
00405 /**
00406   * @brief  Return current CRC calculation result. 7 bits value is returned.
00407   * @note   This function is expected to be used in a 7 bits CRC polynomial size context.
00408   * @rmtoll DR           DR            LL_CRC_ReadData7
00409   * @param  CRCx CRC Instance
00410   * @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
00411   */
00412 __STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
00413 {
00414   return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
00415 }
00416
00417 /**
00418   * @brief  Return data stored in the Independent Data(IDR) register.
00419   * @note   This register can be used as a temporary storage location for one byte.
00420   * @rmtoll IDR          IDR           LL_CRC_Read_IDR
00421   * @param  CRCx CRC Instance
00422   * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
00423   */
00424 __STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
00425 {
00426   return (uint32_t)(READ_REG(CRCx->IDR));
00427 }
00428
00429 /**
00430   * @brief  Store data in the Independent Data(IDR) register.
00431   * @note   This register can be used as a temporary storage location for one byte.
00432   * @rmtoll IDR          IDR           LL_CRC_Write_IDR
00433   * @param  CRCx CRC Instance
00434   * @param  InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
00435   * @retval None
00436   */
00437 __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
00438 {
00439   *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
00440 }
00441 /**
00442   * @}
00443   */
00444
00445 #if defined(USE_FULL_LL_DRIVER)
00446 /** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
00447   * @{
00448   */
00449
00450 ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
00451
00452 /**
00453   * @}
00454   */
00455 #endif /* USE_FULL_LL_DRIVER */
00456
00457 /**
00458   * @}
00459   */
00460
00461 /**
00462   * @}
00463   */
00464
00465 #endif /* defined(CRC) */
00466
00467 /**
00468   * @}
00469   */
00470
00471 #ifdef __cplusplus
00472 }
00473 #endif
00474
00475 #endif /* __STM32F3xx_LL_CRC_H */
00476
00477 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_dac.c Source File

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stm32f3xx_ll_dac.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_dac.c
00004   * @author  MCD Application Team
00005   * @brief   DAC LL module driver
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 #if defined(USE_FULL_LL_DRIVER)
00036
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f3xx_ll_dac.h"
00039 #include "stm32f3xx_ll_bus.h"
00040
00041 #ifdef USE_FULL_ASSERT
00042   #include "stm32_assert.h"
00043 #else
00044   #define assert_param(expr) ((void)0U)
00045 #endif
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined (DAC1) || defined (DAC2)
00052
00053 /** @addtogroup DAC_LL DAC
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059 /* Private constants ---------------------------------------------------------*/
00060 /* Private macros ------------------------------------------------------------*/
00061
00062 /** @addtogroup DAC_LL_Private_Macros
00063   * @{
00064   */
00065
00066 #if defined(DAC_CHANNEL2_SUPPORT)
00067 #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)                           \
00068   (                                                                            \
00069       ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                  \
00070    || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)                                  \
00071   )
00072 #else
00073 #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)                           \
00074   (                                                                            \
00075    ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                     \
00076   )
00077 #endif /* DAC_CHANNEL2_SUPPORT */
00078
00079 #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
00080 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
00081   (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
00082    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
00083    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                      \
00084    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                      \
00085    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                     \
00086    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
00087    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
00088    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
00089   )
00090
00091 #elif defined(STM32F303x8) || defined(STM32F328xx)
00092 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
00093   (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
00094    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
00095    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                      \
00096    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                     \
00097    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
00098    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
00099    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
00100   )
00101
00102 #elif defined(STM32F302xE) || defined(STM32F302xC) || defined(STM32F302x8)
00103 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
00104   (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
00105    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
00106    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                      \
00107    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                      \
00108    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                     \
00109    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
00110    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
00111   )
00112
00113 #elif defined(STM32F301x8) || defined(STM32F318xx)
00114 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
00115   (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
00116    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
00117    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
00118    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                     \
00119    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
00120   )
00121
00122 #elif defined(STM32F373xC) || defined(STM32F378xx)
00123 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
00124   (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
00125    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
00126    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                      \
00127    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                      \
00128    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO)                      \
00129    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
00130    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
00131    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
00132   )
00133
00134 #elif defined(STM32F334x8)
00135 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
00136   (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
00137    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
00138    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                      \
00139    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
00140    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                     \
00141    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
00142    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIGGER_HRTIM1_DACTRG2)                  \
00143    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIGGER_HRTIM1_DACTRG3)                  \
00144    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
00145   )
00146 #endif
00147
00148 #define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)           \
00149   (   ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)     \
00150    || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)    \
00151    || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
00152   )
00153
00154 #define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__)      \
00155   (   ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0)     \
00156    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0)  \
00157    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0)  \
00158    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0)  \
00159    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0)  \
00160    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0)  \
00161    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0)  \
00162    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0)  \
00163    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0)  \
00164    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0)  \
00165    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
00166    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
00167    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1)       \
00168    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3)       \
00169    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7)       \
00170    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15)      \
00171    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31)      \
00172    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63)      \
00173    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127)     \
00174    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255)     \
00175    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511)     \
00176    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023)    \
00177    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047)    \
00178    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)    \
00179   )
00180
00181 #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)                             \
00182   (   ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                     \
00183    || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                    \
00184   )
00185
00186 /**
00187   * @}
00188   */
00189
00190
00191 /* Private function prototypes -----------------------------------------------*/
00192
00193 /* Exported functions --------------------------------------------------------*/
00194 /** @addtogroup DAC_LL_Exported_Functions
00195   * @{
00196   */
00197
00198 /** @addtogroup DAC_LL_EF_Init
00199   * @{
00200   */
00201
00202 /**
00203   * @brief  De-initialize registers of the selected DAC instance
00204   *         to their default reset values.
00205   * @param  DACx DAC instance
00206   * @retval An ErrorStatus enumeration value:
00207   *          - SUCCESS: DAC registers are de-initialized
00208   *          - ERROR: not applicable
00209   */
00210 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
00211 {
00212   /* Check the parameters */
00213   assert_param(IS_DAC_ALL_INSTANCE(DACx));
00214
00215   if(DACx == DAC1)
00216   {
00217     /* Force reset of DAC clock */
00218     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
00219
00220     /* Release reset of DAC clock */
00221     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
00222   }
00223 #if defined(DAC2)
00224   else
00225   {
00226     /* Force reset of DAC clock */
00227     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC2);
00228
00229     /* Release reset of DAC clock */
00230     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC2);
00231   }
00232 #endif
00233   return SUCCESS;
00234 }
00235
00236 /**
00237   * @brief  Initialize some features of DAC instance.
00238   * @note   The setting of these parameters by function @ref LL_DAC_Init()
00239   *         is conditioned to DAC state:
00240   *         DAC instance must be disabled.
00241   * @param  DACx DAC instance
00242   * @param  DAC_Channel This parameter can be one of the following values:
00243   *         @arg @ref LL_DAC_CHANNEL_1
00244   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00245   *
00246   *         (1) On this STM32 serie, parameter not available on all devices.
00247   *             Refer to device datasheet for channels availability.
00248   * @param  DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
00249   * @retval An ErrorStatus enumeration value:
00250   *          - SUCCESS: DAC registers are initialized
00251   *          - ERROR: DAC registers are not initialized
00252   */
00253 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
00254 {
00255   ErrorStatus status = SUCCESS;
00256
00257   /* Check the parameters */
00258   assert_param(IS_DAC_ALL_INSTANCE(DACx));
00259   assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
00260   assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
00261   assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
00262   assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
00263   if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
00264   {
00265     assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig));
00266   }
00267
00268   /* Note: Hardware constraint (refer to description of this function)        */
00269   /*       DAC instance must be disabled.                                     */
00270   if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
00271   {
00272     /* Configuration of DAC channel:                                          */
00273     /*  - TriggerSource                                                       */
00274     /*  - WaveAutoGeneration                                                  */
00275     /*  - OutputBuffer                                                        */
00276     if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
00277     {
00278       MODIFY_REG(DACx->CR,
00279                  (  DAC_CR_TSEL1
00280                   | DAC_CR_WAVE1
00281                   | DAC_CR_MAMP1
00282                   | DAC_CR_BOFF1
00283                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00284                 ,
00285                  (  DAC_InitStruct->TriggerSource
00286                   | DAC_InitStruct->WaveAutoGeneration
00287                   | DAC_InitStruct->WaveAutoGenerationConfig
00288                   | DAC_InitStruct->OutputBuffer
00289                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00290                 );
00291     }
00292     else
00293     {
00294       MODIFY_REG(DACx->CR,
00295                  (  DAC_CR_TSEL1
00296                   | DAC_CR_WAVE1
00297                   | DAC_CR_BOFF1
00298                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00299                 ,
00300                  (  DAC_InitStruct->TriggerSource
00301                   | LL_DAC_WAVE_AUTO_GENERATION_NONE
00302                   | DAC_InitStruct->OutputBuffer
00303                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00304                 );
00305     }
00306   }
00307   else
00308   {
00309     /* Initialization error: DAC instance is not disabled.                    */
00310     status = ERROR;
00311   }
00312   return status;
00313 }
00314
00315 /**
00316   * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
00317   * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
00318   *                       whose fields will be set to default values.
00319   * @retval None
00320   */
00321 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
00322 {
00323   /* Set DAC_InitStruct fields to default values */
00324   DAC_InitStruct->TriggerSource            = LL_DAC_TRIG_SOFTWARE;
00325   DAC_InitStruct->WaveAutoGeneration       = LL_DAC_WAVE_AUTO_GENERATION_NONE;
00326   /* Note: Parameter discarded if wave auto generation is disabled,           */
00327   /*       set anyway to its default value.                                   */
00328   DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
00329   DAC_InitStruct->OutputBuffer             = LL_DAC_OUTPUT_BUFFER_ENABLE;
00330 }
00331
00332 /**
00333   * @}
00334   */
00335
00336 /**
00337   * @}
00338   */
00339
00340 /**
00341   * @}
00342   */
00343
00344 #endif /* DAC1 || DAC2 */
00345
00346 /**
00347   * @}
00348   */
00349
00350 #endif /* USE_FULL_LL_DRIVER */
00351
00352 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_dac.h Source File

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stm32f3xx_ll_dac.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_dac.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DAC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_DAC_H
00038 #define __STM32F3xx_LL_DAC_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined (DAC1) || defined (DAC2)
00052
00053 /** @defgroup DAC_LL DAC
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059
00060 /* Private constants ---------------------------------------------------------*/
00061 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
00062   * @{
00063   */
00064
00065 /* Internal masks for DAC channels definition */
00066 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for:             */
00067 /* - channel bits position into register CR                                   */
00068 /* - channel bits position into register SWTRIG                               */
00069 /* - channel register offset of data holding register DHRx                    */
00070 /* - channel register offset of data output register DORx                     */
00071 #define DAC_CR_CH1_BITOFFSET           0U    /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
00072 #define DAC_CR_CH2_BITOFFSET           16U   /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
00073 #define DAC_CR_CHX_BITOFFSET_MASK      (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
00074
00075 #define DAC_SWTR_CH1                   (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
00076 #if defined(DAC_CHANNEL2_SUPPORT)
00077 #define DAC_SWTR_CH2                   (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
00078 #define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1 | DAC_SWTR_CH2)
00079 #else
00080 #define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1)
00081 #endif /* DAC_CHANNEL2_SUPPORT */
00082
00083 #define DAC_REG_DHR12R1_REGOFFSET      0x00000000U             /* Register DHR12Rx channel 1 taken as reference */
00084 #define DAC_REG_DHR12L1_REGOFFSET      0x00100000U             /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
00085 #define DAC_REG_DHR8R1_REGOFFSET       0x02000000U             /* Register offset of DHR8Rx  channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
00086 #if defined(DAC_CHANNEL2_SUPPORT)
00087 #define DAC_REG_DHR12R2_REGOFFSET      0x00030000U             /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
00088 #define DAC_REG_DHR12L2_REGOFFSET      0x00400000U             /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
00089 #define DAC_REG_DHR8R2_REGOFFSET       0x05000000U             /* Register offset of DHR8Rx  channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
00090 #endif /* DAC_CHANNEL2_SUPPORT */
00091 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
00092 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
00093 #define DAC_REG_DHR8RX_REGOFFSET_MASK  0x0F000000U
00094 #define DAC_REG_DHRX_REGOFFSET_MASK    (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
00095
00096 #define DAC_REG_DOR1_REGOFFSET         0x00000000U             /* Register DORx channel 1 taken as reference */
00097 #if defined(DAC_CHANNEL2_SUPPORT)
00098 #define DAC_REG_DOR2_REGOFFSET         0x10000000U             /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
00099 #define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
00100 #else
00101 #define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET)
00102 #endif /* DAC_CHANNEL2_SUPPORT */
00103
00104 /* DAC registers bits positions */
00105 #if defined(DAC_CHANNEL2_SUPPORT)
00106 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS                16U  /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
00107 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS                20U  /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
00108 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS                  8U  /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
00109 #endif /* DAC_CHANNEL2_SUPPORT */
00110
00111 /* Miscellaneous data */
00112 #define DAC_DIGITAL_SCALE_12BITS                        4095U  /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
00113
00114 /**
00115   * @}
00116   */
00117
00118
00119 /* Private macros ------------------------------------------------------------*/
00120 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
00121   * @{
00122   */
00123
00124 /**
00125   * @brief  Driver macro reserved for internal use: isolate bits with the
00126   *         selected mask and shift them to the register LSB
00127   *         (shift mask on register position bit 0).
00128   * @param  __BITS__ Bits in register 32 bits
00129   * @param  __MASK__ Mask in register 32 bits
00130   * @retval Bits in register 32 bits
00131 */
00132 #define __DAC_MASK_SHIFT(__BITS__, __MASK__)                                   \
00133   (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
00134
00135 /**
00136   * @brief  Driver macro reserved for internal use: set a pointer to
00137   *         a register from a register basis from which an offset
00138   *         is applied.
00139   * @param  __REG__ Register basis from which the offset is applied.
00140   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
00141   * @retval Pointer to register address
00142 */
00143 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
00144  ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
00145
00146 /**
00147   * @}
00148   */
00149
00150
00151 /* Exported types ------------------------------------------------------------*/
00152 #if defined(USE_FULL_LL_DRIVER)
00153 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
00154   * @{
00155   */
00156
00157 /**
00158   * @brief  Structure definition of some features of DAC instance.
00159   */
00160 typedef struct
00161 {
00162   uint32_t TriggerSource;               /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
00163                                              This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
00164
00165                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
00166
00167   uint32_t WaveAutoGeneration;          /*!< Set the waveform automatic generation mode for the selected DAC channel.
00168                                              This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
00169
00170                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
00171
00172   uint32_t WaveAutoGenerationConfig;    /*!< Set the waveform automatic generation mode for the selected DAC channel.
00173                                              If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
00174                                              If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
00175                                              @note If waveform automatic generation mode is disabled, this parameter is discarded.
00176
00177                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
00178
00179   uint32_t OutputBuffer;                /*!< Set the output buffer for the selected DAC channel.
00180                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
00181
00182                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
00183
00184 } LL_DAC_InitTypeDef;
00185
00186 /**
00187   * @}
00188   */
00189 #endif /* USE_FULL_LL_DRIVER */
00190
00191 /* Exported constants --------------------------------------------------------*/
00192 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
00193   * @{
00194   */
00195
00196 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
00197   * @brief    Flags defines which can be used with LL_DAC_ReadReg function
00198   * @{
00199   */
00200 /* DAC channel 1 flags */
00201 #define LL_DAC_FLAG_DMAUDR1                (DAC_SR_DMAUDR1)   /*!< DAC channel 1 flag DMA underrun */
00202
00203 #if defined(DAC_CHANNEL2_SUPPORT)
00204 /* DAC channel 2 flags */
00205 #define LL_DAC_FLAG_DMAUDR2                (DAC_SR_DMAUDR2)   /*!< DAC channel 2 flag DMA underrun */
00206 #endif /* DAC_CHANNEL2_SUPPORT */
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup DAC_LL_EC_IT DAC interruptions
00212   * @brief    IT defines which can be used with LL_DAC_ReadReg and  LL_DAC_WriteReg functions
00213   * @{
00214   */
00215 #define LL_DAC_IT_DMAUDRIE1                (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
00216 #if defined(DAC_CHANNEL2_SUPPORT)
00217 #define LL_DAC_IT_DMAUDRIE2                (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
00218 #endif /* DAC_CHANNEL2_SUPPORT */
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
00224   * @{
00225   */
00226 #define LL_DAC_CHANNEL_1                   (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
00227 #if defined(DAC_CHANNEL2_SUPPORT)
00228 #define LL_DAC_CHANNEL_2                   (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
00229 #endif /* DAC_CHANNEL2_SUPPORT */
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
00235   * @{
00236   */
00237 #define LL_DAC_TRIG_SOFTWARE               (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
00238 #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
00239 #define LL_DAC_TRIG_EXT_TIM6_TRGO          0x00000000U                                        /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
00240 #define LL_DAC_TRIG_EXT_TIM3_TRGO          (                                  DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */
00241 #define LL_DAC_TRIG_EXT_TIM7_TRGO          (                 DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
00242 #define LL_DAC_TRIG_EXT_TIM15_TRGO         (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
00243 #define LL_DAC_TRIG_EXT_TIM2_TRGO          (DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
00244 #define LL_DAC_TRIG_EXT_TIM4_TRGO          (DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
00245 #define LL_DAC_TRIG_EXT_TIM8_TRGO          (LL_DAC_TRIG_EXT_TIM3_TRGO)                        /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM8_TRGO for TIM8 selection. */
00246 #define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
00247
00248 #elif defined(STM32F303x8) || defined(STM32F328xx)
00249 #define LL_DAC_TRIG_EXT_TIM6_TRGO          0x00000000U                                        /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
00250 #define LL_DAC_TRIG_EXT_TIM3_TRGO          (                                  DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
00251 #define LL_DAC_TRIG_EXT_TIM7_TRGO          (                 DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
00252 #define LL_DAC_TRIG_EXT_TIM15_TRGO         (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
00253 #define LL_DAC_TRIG_EXT_TIM2_TRGO          (DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
00254 #define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
00255
00256 #elif defined(STM32F302xE) || defined(STM32F302xC) || defined(STM32F302x8)
00257 #define LL_DAC_TRIG_EXT_TIM6_TRGO          0x00000000U                                        /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
00258 #define LL_DAC_TRIG_EXT_TIM3_TRGO          (                                  DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
00259 #define LL_DAC_TRIG_EXT_TIM15_TRGO         (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
00260 #define LL_DAC_TRIG_EXT_TIM2_TRGO          (DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
00261 #define LL_DAC_TRIG_EXT_TIM4_TRGO          (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0                 ) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
00262 #define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
00263
00264 #elif defined(STM32F301x8) || defined(STM32F318xx)
00265 #define LL_DAC_TRIG_EXT_TIM6_TRGO          0x00000000U                                        /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
00266 #define LL_DAC_TRIG_EXT_TIM2_TRGO          (DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
00267 #define LL_DAC_TRIG_EXT_TIM15_TRGO         (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
00268 #define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
00269
00270 #elif defined(STM32F373xC) || defined(STM32F378xx)
00271 #define LL_DAC_TRIG_EXT_TIM6_TRGO          0x00000000U                                        /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
00272 #define LL_DAC_TRIG_EXT_TIM3_TRGO          (                                  DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
00273 #define LL_DAC_TRIG_EXT_TIM7_TRGO          (                 DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
00274 #define LL_DAC_TRIG_EXT_TIM5_TRGO          (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
00275 #define LL_DAC_TRIG_EXT_TIM2_TRGO          (DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
00276 #define LL_DAC_TRIG_EXT_TIM4_TRGO          (DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
00277 #define LL_DAC_TRIG_EXT_TIM18_TRGO         (LL_DAC_TRIG_EXT_TIM5_TRGO)                        /*!< DAC channel conversion trigger from external IP: TIM18 TRGO. */
00278 #define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
00279
00280 #elif defined(STM32F334x8)
00281 #define LL_DAC_TRIG_EXT_TIM6_TRGO          0x00000000U                                        /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
00282 #define LL_DAC_TRIG_EXT_TIM3_TRGO          (                                  DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */
00283 #define LL_DAC_TRIG_EXT_TIM7_TRGO          (                 DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
00284 #define LL_DAC_TRIG_EXT_TIM2_TRGO          (DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
00285 #define LL_DAC_TRIG_EXT_TIM15_TRGO         (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_TIM15_TRGO for TIM15 selection. */
00286 #define LL_DAC_TRIGGER_HRTIM1_DACTRG1      (LL_DAC_TRIG_EXT_TIM15_TRGO)                       /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG1. Available only on DAC instance: DAC1. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_HRTIM1_DAC1_TRIG1 for HRTIM1 TRIG1 selection. */
00287 #define LL_DAC_TRIGGER_HRTIM1_DACTRG2      (DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG2. Available only on DAC instance: DAC2. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG5_REMAP_HRTIM1_DAC1_TRIG2 for HRTIM1 TRIG2 selection. */
00288 #define LL_DAC_TRIGGER_HRTIM1_DACTRG3      (LL_DAC_TRIGGER_HRTIM1_DACTRG2)                    /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG3. */
00289 #define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
00290
00291 #endif
00292 /**
00293   * @}
00294   */
00295
00296 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
00297   * @{
00298   */
00299 #define LL_DAC_WAVE_AUTO_GENERATION_NONE     0x00000000U             /*!< DAC channel wave auto generation mode disabled. */
00300 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE    (DAC_CR_WAVE1_0)        /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
00301 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1)        /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
00307   * @{
00308   */
00309 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0      0x00000000U                                                         /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
00310 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0   (                                                   DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
00311 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0   (                                  DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
00312 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0   (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
00313 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0   (                 DAC_CR_MAMP1_2                                  ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
00314 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0   (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
00315 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
00316 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
00317 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0   (DAC_CR_MAMP1_3                                                   ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
00318 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0   (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
00319 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
00320 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
00326   * @{
00327   */
00328 #define LL_DAC_TRIANGLE_AMPLITUDE_1        0x00000000U                                                         /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
00329 #define LL_DAC_TRIANGLE_AMPLITUDE_3        (                                                   DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
00330 #define LL_DAC_TRIANGLE_AMPLITUDE_7        (                                  DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
00331 #define LL_DAC_TRIANGLE_AMPLITUDE_15       (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
00332 #define LL_DAC_TRIANGLE_AMPLITUDE_31       (                 DAC_CR_MAMP1_2                                  ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
00333 #define LL_DAC_TRIANGLE_AMPLITUDE_63       (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
00334 #define LL_DAC_TRIANGLE_AMPLITUDE_127      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
00335 #define LL_DAC_TRIANGLE_AMPLITUDE_255      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
00336 #define LL_DAC_TRIANGLE_AMPLITUDE_511      (DAC_CR_MAMP1_3                                                   ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
00337 #define LL_DAC_TRIANGLE_AMPLITUDE_1023     (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
00338 #define LL_DAC_TRIANGLE_AMPLITUDE_2047     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
00339 #define LL_DAC_TRIANGLE_AMPLITUDE_4095     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
00345   * @{
00346   */
00347 #define LL_DAC_OUTPUT_BUFFER_ENABLE        0x00000000U             /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
00348 #define LL_DAC_OUTPUT_BUFFER_DISABLE       (DAC_CR_BOFF1)          /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
00349
00350 #if defined(DAC_CR_OUTEN1) || defined(DAC_CR_OUTEN2)
00351 #define LL_DAC_OUTPUT_SWITCH_DISABLE       (LL_DAC_OUTPUT_BUFFER_ENABLE)  /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. Selection of switch disabled: DAC channel output not connected to GPIO. */
00352 #define LL_DAC_OUTPUT_SWITCH_ENABLE        (LL_DAC_OUTPUT_BUFFER_DISABLE) /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. */
00353 #endif
00354 /**
00355   * @}
00356   */
00357
00358
00359 /** @defgroup DAC_LL_EC_RESOLUTION  DAC channel output resolution
00360   * @{
00361   */
00362 #define LL_DAC_RESOLUTION_12B              0x00000000U             /*!< DAC channel resolution 12 bits */
00363 #define LL_DAC_RESOLUTION_8B               0x00000002U             /*!< DAC channel resolution 8 bits */
00364 /**
00365   * @}
00366   */
00367
00368 /** @defgroup DAC_LL_EC_REGISTERS  DAC registers compliant with specific purpose
00369   * @{
00370   */
00371 /* List of DAC registers intended to be used (most commonly) with             */
00372 /* DMA transfer.                                                              */
00373 /* Refer to function @ref LL_DAC_DMA_GetRegAddr().                            */
00374 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED  DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
00375 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED   DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
00376 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED   DAC_REG_DHR8RX_REGOFFSET_MASK  /*!< DAC channel data holding register 8 bits right aligned */
00377 /**
00378   * @}
00379   */
00380
00381 /** @defgroup DAC_LL_EC_HW_DELAYS  Definitions of DAC hardware constraints delays
00382   * @note   Only DAC IP HW delays are defined in DAC LL driver driver,
00383   *         not timeout values.
00384   *         For details on delays values, refer to descriptions in source code
00385   *         above each literal definition.
00386   * @{
00387   */
00388
00389 /* Delay for DAC channel voltage settling time from DAC channel startup       */
00390 /* (transition from disable to enable).                                       */
00391 /* Note: DAC channel startup time depends on board application environment:   */
00392 /*       impedance connected to DAC channel output.                           */
00393 /*       The delay below is specified under conditions:                       */
00394 /*        - voltage maximum transition (lowest to highest value)              */
00395 /*        - until voltage reaches final value +-1LSB                          */
00396 /*        - DAC channel output buffer enabled                                 */
00397 /*        - load impedance of 5kOhm (min), 50pF (max)                         */
00398 /* Literal set to maximum value (refer to device datasheet,                   */
00399 /* parameter "tWAKEUP").                                                      */
00400 /* Unit: us                                                                   */
00401 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US             15U  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
00402
00403 /* Delay for DAC channel voltage settling time.                               */
00404 /* Note: DAC channel startup time depends on board application environment:   */
00405 /*       impedance connected to DAC channel output.                           */
00406 /*       The delay below is specified under conditions:                       */
00407 /*        - voltage maximum transition (lowest to highest value)              */
00408 /*        - until voltage reaches final value +-1LSB                          */
00409 /*        - DAC channel output buffer enabled                                 */
00410 /*        - load impedance of 5kOhm min, 50pF max                             */
00411 /* Literal set to maximum value (refer to device datasheet,                   */
00412 /* parameter "tSETTLING").                                                    */
00413 /* Unit: us                                                                   */
00414 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US                    12U  /*!< Delay for DAC channel voltage settling time */
00415 /**
00416   * @}
00417   */
00418
00419 /**
00420   * @}
00421   */
00422
00423 /* Exported macro ------------------------------------------------------------*/
00424 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
00425   * @{
00426   */
00427
00428 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
00429   * @{
00430   */
00431
00432 /**
00433   * @brief  Write a value in DAC register
00434   * @param  __INSTANCE__ DAC Instance
00435   * @param  __REG__ Register to be written
00436   * @param  __VALUE__ Value to be written in the register
00437   * @retval None
00438   */
00439 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00440
00441 /**
00442   * @brief  Read a value in DAC register
00443   * @param  __INSTANCE__ DAC Instance
00444   * @param  __REG__ Register to be read
00445   * @retval Register value
00446   */
00447 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00448
00449 /**
00450   * @}
00451   */
00452
00453 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
00454   * @{
00455   */
00456
00457 /**
00458   * @brief  Helper macro to get DAC channel number in decimal format
00459   *         from literals LL_DAC_CHANNEL_x.
00460   *         Example:
00461   *            __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
00462   *            will return decimal number "1".
00463   * @note   The input can be a value from functions where a channel
00464   *         number is returned.
00465   * @param  __CHANNEL__ This parameter can be one of the following values:
00466   *         @arg @ref LL_DAC_CHANNEL_1
00467   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00468   *
00469   *         (1) On this STM32 serie, parameter not available on all devices.
00470   *             Refer to device datasheet for channels availability.
00471   * @retval 1...2 (value "2" depending on DAC channel 2 availability)
00472   */
00473 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                            \
00474   ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
00475
00476 /**
00477   * @brief  Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
00478   *         from number in decimal format.
00479   *         Example:
00480   *           __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
00481   *           will return a data equivalent to "LL_DAC_CHANNEL_1".
00482   * @note  If the input parameter does not correspond to a DAC channel,
00483   *        this macro returns value '0'.
00484   * @param  __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
00485   * @retval Returned value can be one of the following values:
00486   *         @arg @ref LL_DAC_CHANNEL_1
00487   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00488   *
00489   *         (1) On this STM32 serie, parameter not available on all devices.
00490   *             Refer to device datasheet for channels availability.
00491   */
00492 #if defined(DAC_CHANNEL2_SUPPORT)
00493 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \
00494   (((__DECIMAL_NB__) == 1U)                                                     \
00495     ? (                                                                        \
00496        LL_DAC_CHANNEL_1                                                        \
00497       )                                                                        \
00498       :                                                                        \
00499       (((__DECIMAL_NB__) == 2U)                                                 \
00500         ? (                                                                    \
00501            LL_DAC_CHANNEL_2                                                    \
00502           )                                                                    \
00503           :                                                                    \
00504           (                                                                    \
00505            0                                                                   \
00506           )                                                                    \
00507       )                                                                        \
00508   )
00509 #else
00510 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \
00511   (((__DECIMAL_NB__) == 1U)                                                     \
00512     ? (                                                                        \
00513        LL_DAC_CHANNEL_1                                                        \
00514       )                                                                        \
00515       :                                                                        \
00516       (                                                                        \
00517        0                                                                       \
00518       )                                                                        \
00519   )
00520 #endif  /* DAC_CHANNEL2_SUPPORT */
00521
00522 /**
00523   * @brief  Helper macro to define the DAC conversion data full-scale digital
00524   *         value corresponding to the selected DAC resolution.
00525   * @note   DAC conversion data full-scale corresponds to voltage range
00526   *         determined by analog voltage references Vref+ and Vref-
00527   *         (refer to reference manual).
00528   * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
00529   *         @arg @ref LL_DAC_RESOLUTION_12B
00530   *         @arg @ref LL_DAC_RESOLUTION_8B
00531   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
00532   */
00533 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                             \
00534   ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
00535
00536 /**
00537   * @brief  Helper macro to calculate the DAC conversion data (unit: digital
00538   *         value) corresponding to a voltage (unit: mVolt).
00539   * @note   This helper macro is intended to provide input data in voltage
00540   *         rather than digital value,
00541   *         to be used with LL DAC functions such as
00542   *         @ref LL_DAC_ConvertData12RightAligned().
00543   * @note   Analog reference voltage (Vref+) must be either known from
00544   *         user board environment or can be calculated using ADC measurement
00545   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
00546   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
00547   * @param  __DAC_VOLTAGE__ Voltage to be generated by DAC channel
00548   *                         (unit: mVolt).
00549   * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
00550   *         @arg @ref LL_DAC_RESOLUTION_12B
00551   *         @arg @ref LL_DAC_RESOLUTION_8B
00552   * @retval DAC conversion data (unit: digital value)
00553   */
00554 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
00555                                       __DAC_VOLTAGE__,\
00556                                       __DAC_RESOLUTION__)                      \
00557   ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)              \
00558    / (__VREFANALOG_VOLTAGE__)                                                  \
00559   )
00560
00561 /**
00562   * @}
00563   */
00564
00565 /**
00566   * @}
00567   */
00568
00569
00570 /* Exported functions --------------------------------------------------------*/
00571 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
00572   * @{
00573   */
00574 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
00575   * @{
00576   */
00577
00578 /**
00579   * @brief  Set the conversion trigger source for the selected DAC channel.
00580   * @note   For conversion trigger source to be effective, DAC trigger
00581   *         must be enabled using function @ref LL_DAC_EnableTrigger().
00582   * @note   To set conversion trigger source, DAC channel must be disabled.
00583   *         Otherwise, the setting is discarded.
00584   * @note   Availability of parameters of trigger sources from timer
00585   *         depends on timers availability on the selected device.
00586   * @rmtoll CR       TSEL1          LL_DAC_SetTriggerSource\n
00587   *         CR       TSEL2          LL_DAC_SetTriggerSource
00588   * @param  DACx DAC instance
00589   * @param  DAC_Channel This parameter can be one of the following values:
00590   *         @arg @ref LL_DAC_CHANNEL_1
00591   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00592   *
00593   *         (1) On this STM32 serie, parameter not available on all devices.
00594   *             Refer to device datasheet for channels availability.
00595   * @param  TriggerSource This parameter can be one of the following values:
00596   *         @arg @ref LL_DAC_TRIG_SOFTWARE
00597   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
00598   *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO        (1)
00599   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO        (1)
00600   *         @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO        (1)
00601   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
00602   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO        (1)
00603   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO        (1)
00604   *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO       (1)
00605   *         @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO       (1)
00606   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1   (1)
00607   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2   (1)(2)
00608   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3   (1)   (3)
00609   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
00610   *
00611   *         (1) On STM32F3, parameter not available on all devices
00612   *         (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n
00613   *         (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).
00614   * @retval None
00615   */
00616 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
00617 {
00618   MODIFY_REG(DACx->CR,
00619              DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00620              TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00621 }
00622
00623 /**
00624   * @brief  Get the conversion trigger source for the selected DAC channel.
00625   * @note   For conversion trigger source to be effective, DAC trigger
00626   *         must be enabled using function @ref LL_DAC_EnableTrigger().
00627   * @note   Availability of parameters of trigger sources from timer
00628   *         depends on timers availability on the selected device.
00629   * @rmtoll CR       TSEL1          LL_DAC_GetTriggerSource\n
00630   *         CR       TSEL2          LL_DAC_GetTriggerSource
00631   * @param  DACx DAC instance
00632   * @param  DAC_Channel This parameter can be one of the following values:
00633   *         @arg @ref LL_DAC_CHANNEL_1
00634   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00635   *
00636   *         (1) On this STM32 serie, parameter not available on all devices.
00637   *             Refer to device datasheet for channels availability.
00638   * @retval Returned value can be one of the following values:
00639   *         @arg @ref LL_DAC_TRIG_SOFTWARE
00640   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
00641   *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO        (1)
00642   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO        (1)
00643   *         @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO        (1)
00644   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
00645   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO        (1)
00646   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO        (1)
00647   *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO       (1)
00648   *         @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO       (1)
00649   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1   (1)
00650   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2   (1)(2)
00651   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3   (1)   (3)
00652   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
00653   *
00654   *         (1) On STM32F3, parameter not available on all devices
00655   *         (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n
00656   *         (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).
00657   */
00658 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00659 {
00660   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00661                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00662                    );
00663 }
00664
00665 /**
00666   * @brief  Set the waveform automatic generation mode
00667   *         for the selected DAC channel.
00668   * @rmtoll CR       WAVE1          LL_DAC_SetWaveAutoGeneration\n
00669   *         CR       WAVE2          LL_DAC_SetWaveAutoGeneration
00670   * @param  DACx DAC instance
00671   * @param  DAC_Channel This parameter can be one of the following values:
00672   *         @arg @ref LL_DAC_CHANNEL_1
00673   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00674   *
00675   *         (1) On this STM32 serie, parameter not available on all devices.
00676   *             Refer to device datasheet for channels availability.
00677   * @param  WaveAutoGeneration This parameter can be one of the following values:
00678   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
00679   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
00680   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
00681   * @retval None
00682   */
00683 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
00684 {
00685   MODIFY_REG(DACx->CR,
00686              DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00687              WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00688 }
00689
00690 /**
00691   * @brief  Get the waveform automatic generation mode
00692   *         for the selected DAC channel.
00693   * @rmtoll CR       WAVE1          LL_DAC_GetWaveAutoGeneration\n
00694   *         CR       WAVE2          LL_DAC_GetWaveAutoGeneration
00695   * @param  DACx DAC instance
00696   * @param  DAC_Channel This parameter can be one of the following values:
00697   *         @arg @ref LL_DAC_CHANNEL_1
00698   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00699   *
00700   *         (1) On this STM32 serie, parameter not available on all devices.
00701   *             Refer to device datasheet for channels availability.
00702   * @retval Returned value can be one of the following values:
00703   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
00704   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
00705   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
00706   */
00707 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00708 {
00709   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00710                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00711                    );
00712 }
00713
00714 /**
00715   * @brief  Set the noise waveform generation for the selected DAC channel:
00716   *         Noise mode and parameters LFSR (linear feedback shift register).
00717   * @note   For wave generation to be effective, DAC channel
00718   *         wave generation mode must be enabled using
00719   *         function @ref LL_DAC_SetWaveAutoGeneration().
00720   * @note   This setting can be set when the selected DAC channel is disabled
00721   *         (otherwise, the setting operation is ignored).
00722   * @rmtoll CR       MAMP1          LL_DAC_SetWaveNoiseLFSR\n
00723   *         CR       MAMP2          LL_DAC_SetWaveNoiseLFSR
00724   * @param  DACx DAC instance
00725   * @param  DAC_Channel This parameter can be one of the following values:
00726   *         @arg @ref LL_DAC_CHANNEL_1
00727   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00728   *
00729   *         (1) On this STM32 serie, parameter not available on all devices.
00730   *             Refer to device datasheet for channels availability.
00731   * @param  NoiseLFSRMask This parameter can be one of the following values:
00732   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
00733   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
00734   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
00735   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
00736   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
00737   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
00738   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
00739   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
00740   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
00741   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
00742   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
00743   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
00744   * @retval None
00745   */
00746 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
00747 {
00748   MODIFY_REG(DACx->CR,
00749              DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00750              NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00751 }
00752
00753 /**
00754   * @brief  Set the noise waveform generation for the selected DAC channel:
00755   *         Noise mode and parameters LFSR (linear feedback shift register).
00756   * @rmtoll CR       MAMP1          LL_DAC_GetWaveNoiseLFSR\n
00757   *         CR       MAMP2          LL_DAC_GetWaveNoiseLFSR
00758   * @param  DACx DAC instance
00759   * @param  DAC_Channel This parameter can be one of the following values:
00760   *         @arg @ref LL_DAC_CHANNEL_1
00761   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00762   *
00763   *         (1) On this STM32 serie, parameter not available on all devices.
00764   *             Refer to device datasheet for channels availability.
00765   * @retval Returned value can be one of the following values:
00766   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
00767   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
00768   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
00769   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
00770   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
00771   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
00772   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
00773   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
00774   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
00775   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
00776   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
00777   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
00778   */
00779 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00780 {
00781   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00782                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00783                    );
00784 }
00785
00786 /**
00787   * @brief  Set the triangle waveform generation for the selected DAC channel:
00788   *         triangle mode and amplitude.
00789   * @note   For wave generation to be effective, DAC channel
00790   *         wave generation mode must be enabled using
00791   *         function @ref LL_DAC_SetWaveAutoGeneration().
00792   * @note   This setting can be set when the selected DAC channel is disabled
00793   *         (otherwise, the setting operation is ignored).
00794   * @rmtoll CR       MAMP1          LL_DAC_SetWaveTriangleAmplitude\n
00795   *         CR       MAMP2          LL_DAC_SetWaveTriangleAmplitude
00796   * @param  DACx DAC instance
00797   * @param  DAC_Channel This parameter can be one of the following values:
00798   *         @arg @ref LL_DAC_CHANNEL_1
00799   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00800   *
00801   *         (1) On this STM32 serie, parameter not available on all devices.
00802   *             Refer to device datasheet for channels availability.
00803   * @param  TriangleAmplitude This parameter can be one of the following values:
00804   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
00805   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
00806   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
00807   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
00808   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
00809   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
00810   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
00811   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
00812   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
00813   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
00814   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
00815   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
00816   * @retval None
00817   */
00818 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
00819 {
00820   MODIFY_REG(DACx->CR,
00821              DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00822              TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00823 }
00824
00825 /**
00826   * @brief  Set the triangle waveform generation for the selected DAC channel:
00827   *         triangle mode and amplitude.
00828   * @rmtoll CR       MAMP1          LL_DAC_GetWaveTriangleAmplitude\n
00829   *         CR       MAMP2          LL_DAC_GetWaveTriangleAmplitude
00830   * @param  DACx DAC instance
00831   * @param  DAC_Channel This parameter can be one of the following values:
00832   *         @arg @ref LL_DAC_CHANNEL_1
00833   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00834   *
00835   *         (1) On this STM32 serie, parameter not available on all devices.
00836   *             Refer to device datasheet for channels availability.
00837   * @retval Returned value can be one of the following values:
00838   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
00839   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
00840   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
00841   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
00842   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
00843   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
00844   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
00845   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
00846   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
00847   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
00848   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
00849   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
00850   */
00851 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00852 {
00853   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00854                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00855                    );
00856 }
00857
00858 /**
00859   * @brief  Set the output buffer for the selected DAC channel.
00860   * @rmtoll CR       BOFF1          LL_DAC_SetOutputBuffer\n
00861   *         CR       BOFF2          LL_DAC_SetOutputBuffer
00862   * @param  DACx DAC instance
00863   * @param  DAC_Channel This parameter can be one of the following values:
00864   *         @arg @ref LL_DAC_CHANNEL_1
00865   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00866   *
00867   *         (1) On this STM32 serie, parameter not available on all devices.
00868   *             Refer to device datasheet for channels availability.
00869   * @param  OutputBuffer This parameter can be one of the following values:
00870   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
00871   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
00872   *         @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1)
00873   *         @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE  (1)
00874   *
00875   *         (1) Feature specific to STM32F303x6/8 and STM32F328:
00876   *             On DAC1 channel 2, output buffer is replaced by a switch
00877   *             to connect DAC channel output to pin PA5.
00878   *             On DAC2 channel 1, output buffer is replaced by a switch
00879   *             to connect DAC channel output to pin PA6.
00880   * @retval None
00881   */
00882 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
00883 {
00884   MODIFY_REG(DACx->CR,
00885              DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00886              OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00887 }
00888
00889 /**
00890   * @brief  Get the output buffer state for the selected DAC channel.
00891   * @rmtoll CR       BOFF1          LL_DAC_GetOutputBuffer\n
00892   *         CR       BOFF2          LL_DAC_GetOutputBuffer
00893   * @param  DACx DAC instance
00894   * @param  DAC_Channel This parameter can be one of the following values:
00895   *         @arg @ref LL_DAC_CHANNEL_1
00896   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00897   *
00898   *         (1) On this STM32 serie, parameter not available on all devices.
00899   *             Refer to device datasheet for channels availability.
00900   * @retval Returned value can be one of the following values:
00901   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
00902   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
00903   *         @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1)
00904   *         @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE  (1)
00905   *
00906   *         (1) Feature specific to STM32F303x6/8 and STM32F328:
00907   *             On DAC1 channel 2, output buffer is replaced by a switch
00908   *             to connect DAC channel output to pin PA5.
00909   *             On DAC2 channel 1, output buffer is replaced by a switch
00910   *             to connect DAC channel output to pin PA6.
00911   */
00912 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00913 {
00914   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00915                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00916                    );
00917 }
00918
00919 /**
00920   * @}
00921   */
00922
00923 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
00924   * @{
00925   */
00926
00927 /**
00928   * @brief  Enable DAC DMA transfer request of the selected channel.
00929   * @note   To configure DMA source address (peripheral address),
00930   *         use function @ref LL_DAC_DMA_GetRegAddr().
00931   * @rmtoll CR       DMAEN1         LL_DAC_EnableDMAReq\n
00932   *         CR       DMAEN2         LL_DAC_EnableDMAReq
00933   * @param  DACx DAC instance
00934   * @param  DAC_Channel This parameter can be one of the following values:
00935   *         @arg @ref LL_DAC_CHANNEL_1
00936   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00937   *
00938   *         (1) On this STM32 serie, parameter not available on all devices.
00939   *             Refer to device datasheet for channels availability.
00940   * @retval None
00941   */
00942 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00943 {
00944   SET_BIT(DACx->CR,
00945           DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00946 }
00947
00948 /**
00949   * @brief  Disable DAC DMA transfer request of the selected channel.
00950   * @note   To configure DMA source address (peripheral address),
00951   *         use function @ref LL_DAC_DMA_GetRegAddr().
00952   * @rmtoll CR       DMAEN1         LL_DAC_DisableDMAReq\n
00953   *         CR       DMAEN2         LL_DAC_DisableDMAReq
00954   * @param  DACx DAC instance
00955   * @param  DAC_Channel This parameter can be one of the following values:
00956   *         @arg @ref LL_DAC_CHANNEL_1
00957   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00958   *
00959   *         (1) On this STM32 serie, parameter not available on all devices.
00960   *             Refer to device datasheet for channels availability.
00961   * @retval None
00962   */
00963 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00964 {
00965   CLEAR_BIT(DACx->CR,
00966             DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00967 }
00968
00969 /**
00970   * @brief  Get DAC DMA transfer request state of the selected channel.
00971   *         (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
00972   * @rmtoll CR       DMAEN1         LL_DAC_IsDMAReqEnabled\n
00973   *         CR       DMAEN2         LL_DAC_IsDMAReqEnabled
00974   * @param  DACx DAC instance
00975   * @param  DAC_Channel This parameter can be one of the following values:
00976   *         @arg @ref LL_DAC_CHANNEL_1
00977   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00978   *
00979   *         (1) On this STM32 serie, parameter not available on all devices.
00980   *             Refer to device datasheet for channels availability.
00981   * @retval State of bit (1 or 0).
00982   */
00983 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00984 {
00985   return (READ_BIT(DACx->CR,
00986                    DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00987           == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
00988 }
00989
00990 /**
00991   * @brief  Function to help to configure DMA transfer to DAC: retrieve the
00992   *         DAC register address from DAC instance and a list of DAC registers
00993   *         intended to be used (most commonly) with DMA transfer.
00994   * @note   These DAC registers are data holding registers:
00995   *         when DAC conversion is requested, DAC generates a DMA transfer
00996   *         request to have data available in DAC data holding registers.
00997   * @note   This macro is intended to be used with LL DMA driver, refer to
00998   *         function "LL_DMA_ConfigAddresses()".
00999   *         Example:
01000   *           LL_DMA_ConfigAddresses(DMA1,
01001   *                                  LL_DMA_CHANNEL_1,
01002   *                                  (uint32_t)&< array or variable >,
01003   *                                  LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
01004   *                                  LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
01005   * @rmtoll DHR12R1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
01006   *         DHR12L1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
01007   *         DHR8R1   DACC1DHR       LL_DAC_DMA_GetRegAddr\n
01008   *         DHR12R2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
01009   *         DHR12L2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
01010   *         DHR8R2   DACC2DHR       LL_DAC_DMA_GetRegAddr
01011   * @param  DACx DAC instance
01012   * @param  DAC_Channel This parameter can be one of the following values:
01013   *         @arg @ref LL_DAC_CHANNEL_1
01014   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01015   *
01016   *         (1) On this STM32 serie, parameter not available on all devices.
01017   *             Refer to device datasheet for channels availability.
01018   * @param  Register This parameter can be one of the following values:
01019   *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
01020   *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
01021   *         @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
01022   * @retval DAC register address
01023   */
01024 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
01025 {
01026   /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on     */
01027   /* DAC channel selected.                                                    */
01028   return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
01029 }
01030 /**
01031   * @}
01032   */
01033
01034 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
01035   * @{
01036   */
01037
01038 /**
01039   * @brief  Enable DAC selected channel.
01040   * @rmtoll CR       EN1            LL_DAC_Enable\n
01041   *         CR       EN2            LL_DAC_Enable
01042   * @note   After enable from off state, DAC channel requires a delay
01043   *         for output voltage to reach accuracy +/- 1 LSB.
01044   *         Refer to device datasheet, parameter "tWAKEUP".
01045   * @param  DACx DAC instance
01046   * @param  DAC_Channel This parameter can be one of the following values:
01047   *         @arg @ref LL_DAC_CHANNEL_1
01048   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01049   *
01050   *         (1) On this STM32 serie, parameter not available on all devices.
01051   *             Refer to device datasheet for channels availability.
01052   * @retval None
01053   */
01054 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01055 {
01056   SET_BIT(DACx->CR,
01057           DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01058 }
01059
01060 /**
01061   * @brief  Disable DAC selected channel.
01062   * @rmtoll CR       EN1            LL_DAC_Disable\n
01063   *         CR       EN2            LL_DAC_Disable
01064   * @param  DACx DAC instance
01065   * @param  DAC_Channel This parameter can be one of the following values:
01066   *         @arg @ref LL_DAC_CHANNEL_1
01067   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01068   *
01069   *         (1) On this STM32 serie, parameter not available on all devices.
01070   *             Refer to device datasheet for channels availability.
01071   * @retval None
01072   */
01073 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01074 {
01075   CLEAR_BIT(DACx->CR,
01076             DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01077 }
01078
01079 /**
01080   * @brief  Get DAC enable state of the selected channel.
01081   *         (0: DAC channel is disabled, 1: DAC channel is enabled)
01082   * @rmtoll CR       EN1            LL_DAC_IsEnabled\n
01083   *         CR       EN2            LL_DAC_IsEnabled
01084   * @param  DACx DAC instance
01085   * @param  DAC_Channel This parameter can be one of the following values:
01086   *         @arg @ref LL_DAC_CHANNEL_1
01087   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01088   *
01089   *         (1) On this STM32 serie, parameter not available on all devices.
01090   *             Refer to device datasheet for channels availability.
01091   * @retval State of bit (1 or 0).
01092   */
01093 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01094 {
01095   return (READ_BIT(DACx->CR,
01096                    DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01097           == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
01098 }
01099
01100 /**
01101   * @brief  Enable DAC trigger of the selected channel.
01102   * @note   - If DAC trigger is disabled, DAC conversion is performed
01103   *           automatically once the data holding register is updated,
01104   *           using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
01105   *           @ref LL_DAC_ConvertData12RightAligned(), ...
01106   *         - If DAC trigger is enabled, DAC conversion is performed
01107   *           only when a hardware of software trigger event is occurring.
01108   *           Select trigger source using
01109   *           function @ref LL_DAC_SetTriggerSource().
01110   * @rmtoll CR       TEN1           LL_DAC_EnableTrigger\n
01111   *         CR       TEN2           LL_DAC_EnableTrigger
01112   * @param  DACx DAC instance
01113   * @param  DAC_Channel This parameter can be one of the following values:
01114   *         @arg @ref LL_DAC_CHANNEL_1
01115   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01116   *
01117   *         (1) On this STM32 serie, parameter not available on all devices.
01118   *             Refer to device datasheet for channels availability.
01119   * @retval None
01120   */
01121 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01122 {
01123   SET_BIT(DACx->CR,
01124           DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01125 }
01126
01127 /**
01128   * @brief  Disable DAC trigger of the selected channel.
01129   * @rmtoll CR       TEN1           LL_DAC_DisableTrigger\n
01130   *         CR       TEN2           LL_DAC_DisableTrigger
01131   * @param  DACx DAC instance
01132   * @param  DAC_Channel This parameter can be one of the following values:
01133   *         @arg @ref LL_DAC_CHANNEL_1
01134   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01135   *
01136   *         (1) On this STM32 serie, parameter not available on all devices.
01137   *             Refer to device datasheet for channels availability.
01138   * @retval None
01139   */
01140 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01141 {
01142   CLEAR_BIT(DACx->CR,
01143             DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01144 }
01145
01146 /**
01147   * @brief  Get DAC trigger state of the selected channel.
01148   *         (0: DAC trigger is disabled, 1: DAC trigger is enabled)
01149   * @rmtoll CR       TEN1           LL_DAC_IsTriggerEnabled\n
01150   *         CR       TEN2           LL_DAC_IsTriggerEnabled
01151   * @param  DACx DAC instance
01152   * @param  DAC_Channel This parameter can be one of the following values:
01153   *         @arg @ref LL_DAC_CHANNEL_1
01154   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01155   *
01156   *         (1) On this STM32 serie, parameter not available on all devices.
01157   *             Refer to device datasheet for channels availability.
01158   * @retval State of bit (1 or 0).
01159   */
01160 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01161 {
01162   return (READ_BIT(DACx->CR,
01163                    DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01164           == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
01165 }
01166
01167 /**
01168   * @brief  Trig DAC conversion by software for the selected DAC channel.
01169   * @note   Preliminarily, DAC trigger must be set to software trigger
01170   *         using function @ref LL_DAC_SetTriggerSource()
01171   *         with parameter "LL_DAC_TRIGGER_SOFTWARE".
01172   *         and DAC trigger must be enabled using
01173   *         function @ref LL_DAC_EnableTrigger().
01174   * @note   For devices featuring DAC with 2 channels: this function
01175   *         can perform a SW start of both DAC channels simultaneously.
01176   *         Two channels can be selected as parameter.
01177   *         Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
01178   * @rmtoll SWTRIGR  SWTRIG1        LL_DAC_TrigSWConversion\n
01179   *         SWTRIGR  SWTRIG2        LL_DAC_TrigSWConversion
01180   * @param  DACx DAC instance
01181   * @param  DAC_Channel  This parameter can a combination of the following values:
01182   *         @arg @ref LL_DAC_CHANNEL_1
01183   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01184   *
01185   *         (1) On this STM32 serie, parameter not available on all devices.
01186   *             Refer to device datasheet for channels availability.
01187   * @retval None
01188   */
01189 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01190 {
01191   SET_BIT(DACx->SWTRIGR,
01192           (DAC_Channel & DAC_SWTR_CHX_MASK));
01193 }
01194
01195 /**
01196   * @brief  Set the data to be loaded in the data holding register
01197   *         in format 12 bits left alignment (LSB aligned on bit 0),
01198   *         for the selected DAC channel.
01199   * @rmtoll DHR12R1  DACC1DHR       LL_DAC_ConvertData12RightAligned\n
01200   *         DHR12R2  DACC2DHR       LL_DAC_ConvertData12RightAligned
01201   * @param  DACx DAC instance
01202   * @param  DAC_Channel This parameter can be one of the following values:
01203   *         @arg @ref LL_DAC_CHANNEL_1
01204   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01205   *
01206   *         (1) On this STM32 serie, parameter not available on all devices.
01207   *             Refer to device datasheet for channels availability.
01208   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
01209   * @retval None
01210   */
01211 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01212 {
01213   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
01214
01215   MODIFY_REG(*preg,
01216              DAC_DHR12R1_DACC1DHR,
01217              Data);
01218 }
01219
01220 /**
01221   * @brief  Set the data to be loaded in the data holding register
01222   *         in format 12 bits left alignment (MSB aligned on bit 15),
01223   *         for the selected DAC channel.
01224   * @rmtoll DHR12L1  DACC1DHR       LL_DAC_ConvertData12LeftAligned\n
01225   *         DHR12L2  DACC2DHR       LL_DAC_ConvertData12LeftAligned
01226   * @param  DACx DAC instance
01227   * @param  DAC_Channel This parameter can be one of the following values:
01228   *         @arg @ref LL_DAC_CHANNEL_1
01229   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01230   *
01231   *         (1) On this STM32 serie, parameter not available on all devices.
01232   *             Refer to device datasheet for channels availability.
01233   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
01234   * @retval None
01235   */
01236 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01237 {
01238   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
01239
01240   MODIFY_REG(*preg,
01241              DAC_DHR12L1_DACC1DHR,
01242              Data);
01243 }
01244
01245 /**
01246   * @brief  Set the data to be loaded in the data holding register
01247   *         in format 8 bits left alignment (LSB aligned on bit 0),
01248   *         for the selected DAC channel.
01249   * @rmtoll DHR8R1   DACC1DHR       LL_DAC_ConvertData8RightAligned\n
01250   *         DHR8R2   DACC2DHR       LL_DAC_ConvertData8RightAligned
01251   * @param  DACx DAC instance
01252   * @param  DAC_Channel This parameter can be one of the following values:
01253   *         @arg @ref LL_DAC_CHANNEL_1
01254   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01255   *
01256   *         (1) On this STM32 serie, parameter not available on all devices.
01257   *             Refer to device datasheet for channels availability.
01258   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
01259   * @retval None
01260   */
01261 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01262 {
01263   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
01264
01265   MODIFY_REG(*preg,
01266              DAC_DHR8R1_DACC1DHR,
01267              Data);
01268 }
01269
01270 #if defined(DAC_CHANNEL2_SUPPORT)
01271 /**
01272   * @brief  Set the data to be loaded in the data holding register
01273   *         in format 12 bits left alignment (LSB aligned on bit 0),
01274   *         for both DAC channels.
01275   * @rmtoll DHR12RD  DACC1DHR       LL_DAC_ConvertDualData12RightAligned\n
01276   *         DHR12RD  DACC2DHR       LL_DAC_ConvertDualData12RightAligned
01277   * @param  DACx DAC instance
01278   * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
01279   * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
01280   * @retval None
01281   */
01282 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
01283 {
01284   MODIFY_REG(DACx->DHR12RD,
01285              (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
01286              ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
01287 }
01288
01289 /**
01290   * @brief  Set the data to be loaded in the data holding register
01291   *         in format 12 bits left alignment (MSB aligned on bit 15),
01292   *         for both DAC channels.
01293   * @rmtoll DHR12LD  DACC1DHR       LL_DAC_ConvertDualData12LeftAligned\n
01294   *         DHR12LD  DACC2DHR       LL_DAC_ConvertDualData12LeftAligned
01295   * @param  DACx DAC instance
01296   * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
01297   * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
01298   * @retval None
01299   */
01300 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
01301 {
01302   /* Note: Data of DAC channel 2 shift value subtracted of 4 because          */
01303   /*       data on 16 bits and DAC channel 2 bits field is on the 12 MSB,     */
01304   /*       the 4 LSB must be taken into account for the shift value.          */
01305   MODIFY_REG(DACx->DHR12LD,
01306              (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
01307              ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
01308 }
01309
01310 /**
01311   * @brief  Set the data to be loaded in the data holding register
01312   *         in format 8 bits left alignment (LSB aligned on bit 0),
01313   *         for both DAC channels.
01314   * @rmtoll DHR8RD  DACC1DHR       LL_DAC_ConvertDualData8RightAligned\n
01315   *         DHR8RD  DACC2DHR       LL_DAC_ConvertDualData8RightAligned
01316   * @param  DACx DAC instance
01317   * @param  DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
01318   * @param  DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
01319   * @retval None
01320   */
01321 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
01322 {
01323   MODIFY_REG(DACx->DHR8RD,
01324              (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
01325              ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
01326 }
01327
01328 #endif /* DAC_CHANNEL2_SUPPORT */
01329 /**
01330   * @brief  Retrieve output data currently generated for the selected DAC channel.
01331   * @note   Whatever alignment and resolution settings
01332   *         (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
01333   *         @ref LL_DAC_ConvertData12RightAligned(), ...),
01334   *         output data format is 12 bits right aligned (LSB aligned on bit 0).
01335   * @rmtoll DOR1     DACC1DOR       LL_DAC_RetrieveOutputData\n
01336   *         DOR2     DACC2DOR       LL_DAC_RetrieveOutputData
01337   * @param  DACx DAC instance
01338   * @param  DAC_Channel This parameter can be one of the following values:
01339   *         @arg @ref LL_DAC_CHANNEL_1
01340   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01341   *
01342   *         (1) On this STM32 serie, parameter not available on all devices.
01343   *             Refer to device datasheet for channels availability.
01344   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01345   */
01346 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01347 {
01348   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
01349
01350   return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
01351 }
01352
01353 /**
01354   * @}
01355   */
01356
01357 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
01358   * @{
01359   */
01360 /**
01361   * @brief  Get DAC underrun flag for DAC channel 1
01362   * @rmtoll SR       DMAUDR1        LL_DAC_IsActiveFlag_DMAUDR1
01363   * @param  DACx DAC instance
01364   * @retval State of bit (1 or 0).
01365   */
01366 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
01367 {
01368   return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
01369 }
01370
01371 #if defined(DAC_CHANNEL2_SUPPORT)
01372 /**
01373   * @brief  Get DAC underrun flag for DAC channel 2
01374   * @rmtoll SR       DMAUDR2        LL_DAC_IsActiveFlag_DMAUDR2
01375   * @param  DACx DAC instance
01376   * @retval State of bit (1 or 0).
01377   */
01378 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
01379 {
01380   return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
01381 }
01382 #endif /* DAC_CHANNEL2_SUPPORT */
01383
01384 /**
01385   * @brief  Clear DAC underrun flag for DAC channel 1
01386   * @rmtoll SR       DMAUDR1        LL_DAC_ClearFlag_DMAUDR1
01387   * @param  DACx DAC instance
01388   * @retval None
01389   */
01390 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
01391 {
01392   WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
01393 }
01394
01395 #if defined(DAC_CHANNEL2_SUPPORT)
01396 /**
01397   * @brief  Clear DAC underrun flag for DAC channel 2
01398   * @rmtoll SR       DMAUDR2        LL_DAC_ClearFlag_DMAUDR2
01399   * @param  DACx DAC instance
01400   * @retval None
01401   */
01402 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
01403 {
01404   WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
01405 }
01406 #endif /* DAC_CHANNEL2_SUPPORT */
01407
01408 /**
01409   * @}
01410   */
01411
01412 /** @defgroup DAC_LL_EF_IT_Management IT management
01413   * @{
01414   */
01415
01416 /**
01417   * @brief  Enable DMA underrun interrupt for DAC channel 1
01418   * @rmtoll CR       DMAUDRIE1      LL_DAC_EnableIT_DMAUDR1
01419   * @param  DACx DAC instance
01420   * @retval None
01421   */
01422 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
01423 {
01424   SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
01425 }
01426
01427 #if defined(DAC_CHANNEL2_SUPPORT)
01428 /**
01429   * @brief  Enable DMA underrun interrupt for DAC channel 2
01430   * @rmtoll CR       DMAUDRIE2      LL_DAC_EnableIT_DMAUDR2
01431   * @param  DACx DAC instance
01432   * @retval None
01433   */
01434 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
01435 {
01436   SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
01437 }
01438 #endif /* DAC_CHANNEL2_SUPPORT */
01439
01440 /**
01441   * @brief  Disable DMA underrun interrupt for DAC channel 1
01442   * @rmtoll CR       DMAUDRIE1      LL_DAC_DisableIT_DMAUDR1
01443   * @param  DACx DAC instance
01444   * @retval None
01445   */
01446 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
01447 {
01448   CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
01449 }
01450
01451 #if defined(DAC_CHANNEL2_SUPPORT)
01452 /**
01453   * @brief  Disable DMA underrun interrupt for DAC channel 2
01454   * @rmtoll CR       DMAUDRIE2      LL_DAC_DisableIT_DMAUDR2
01455   * @param  DACx DAC instance
01456   * @retval None
01457   */
01458 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
01459 {
01460   CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
01461 }
01462 #endif /* DAC_CHANNEL2_SUPPORT */
01463
01464 /**
01465   * @brief  Get DMA underrun interrupt for DAC channel 1
01466   * @rmtoll CR       DMAUDRIE1      LL_DAC_IsEnabledIT_DMAUDR1
01467   * @param  DACx DAC instance
01468   * @retval State of bit (1 or 0).
01469   */
01470 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
01471 {
01472   return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
01473 }
01474
01475 #if defined(DAC_CHANNEL2_SUPPORT)
01476 /**
01477   * @brief  Get DMA underrun interrupt for DAC channel 2
01478   * @rmtoll CR       DMAUDRIE2      LL_DAC_IsEnabledIT_DMAUDR2
01479   * @param  DACx DAC instance
01480   * @retval State of bit (1 or 0).
01481   */
01482 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
01483 {
01484   return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
01485 }
01486 #endif /* DAC_CHANNEL2_SUPPORT */
01487
01488 /**
01489   * @}
01490   */
01491
01492 #if defined(USE_FULL_LL_DRIVER)
01493 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
01494   * @{
01495   */
01496
01497 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
01498 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
01499 void        LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
01500
01501 /**
01502   * @}
01503   */
01504 #endif /* USE_FULL_LL_DRIVER */
01505
01506 /**
01507   * @}
01508   */
01509
01510 /**
01511   * @}
01512   */
01513
01514 #endif /* DAC1 || DAC2 */
01515
01516 /**
01517   * @}
01518   */
01519
01520 #ifdef __cplusplus
01521 }
01522 #endif
01523
01524 #endif /* __STM32F3xx_LL_DAC_H */
01525
01526 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_dma.c Source File

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stm32f3xx_ll_dma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_dma.c
00004   * @author  MCD Application Team
00005   * @brief   DMA LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 #if defined(USE_FULL_LL_DRIVER)
00036
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f3xx_ll_dma.h"
00039 #include "stm32f3xx_ll_bus.h"
00040 #ifdef  USE_FULL_ASSERT
00041 #include "stm32_assert.h"
00042 #else
00043 #define assert_param(expr) ((void)0U)
00044 #endif
00045
00046 /** @addtogroup STM32F3xx_LL_Driver
00047   * @{
00048   */
00049
00050 #if defined (DMA1) || defined (DMA2)
00051
00052 /** @defgroup DMA_LL DMA
00053   * @{
00054   */
00055
00056 /* Private types -------------------------------------------------------------*/
00057 /* Private variables ---------------------------------------------------------*/
00058 /* Private constants ---------------------------------------------------------*/
00059 /* Private macros ------------------------------------------------------------*/
00060 /** @addtogroup DMA_LL_Private_Macros
00061   * @{
00062   */
00063 #define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
00064                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
00065                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
00066
00067 #define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
00068                                                  ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
00069
00070 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
00071                                                  ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
00072
00073 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
00074                                                  ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
00075
00076 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
00077                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
00078                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
00079
00080 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
00081                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
00082                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
00083
00084 #define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
00085
00086
00087 #define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
00088                                                  ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
00089                                                  ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
00090                                                  ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
00091
00092 #if defined (DMA2)
00093 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
00094 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
00095                                                          (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00096                                                           ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00097                                                           ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00098                                                           ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00099                                                           ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00100                                                           ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00101                                                           ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
00102                                                          (((INSTANCE) == DMA2) && \
00103                                                          (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00104                                                           ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00105                                                           ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00106                                                           ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00107                                                           ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00108                                                           ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00109                                                           ((CHANNEL) == LL_DMA_CHANNEL_7))))
00110 #else
00111 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
00112                                                          (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00113                                                           ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00114                                                           ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00115                                                           ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00116                                                           ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00117                                                           ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00118                                                           ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
00119                                                          (((INSTANCE) == DMA2) && \
00120                                                          (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00121                                                           ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00122                                                           ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00123                                                           ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00124                                                           ((CHANNEL) == LL_DMA_CHANNEL_5))))
00125 #endif
00126 #else
00127 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
00128                                                             (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
00129                                                             ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00130                                                             ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00131                                                             ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00132                                                             ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00133                                                             ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00134                                                             ((CHANNEL) == LL_DMA_CHANNEL_7))))
00135 #endif
00136 /**
00137   * @}
00138   */
00139
00140 /* Private function prototypes -----------------------------------------------*/
00141
00142 /* Exported functions --------------------------------------------------------*/
00143 /** @addtogroup DMA_LL_Exported_Functions
00144   * @{
00145   */
00146
00147 /** @addtogroup DMA_LL_EF_Init
00148   * @{
00149   */
00150
00151 /**
00152   * @brief  De-initialize the DMA registers to their default reset values.
00153   * @param  DMAx DMAx Instance
00154   * @param  Channel This parameter can be one of the following values:
00155   *         @arg @ref LL_DMA_CHANNEL_1
00156   *         @arg @ref LL_DMA_CHANNEL_2
00157   *         @arg @ref LL_DMA_CHANNEL_3
00158   *         @arg @ref LL_DMA_CHANNEL_4
00159   *         @arg @ref LL_DMA_CHANNEL_5
00160   *         @arg @ref LL_DMA_CHANNEL_6
00161   *         @arg @ref LL_DMA_CHANNEL_7
00162   * @retval An ErrorStatus enumeration value:
00163   *          - SUCCESS: DMA registers are de-initialized
00164   *          - ERROR: DMA registers are not de-initialized
00165   */
00166 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
00167 {
00168   DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
00169   ErrorStatus status = SUCCESS;
00170
00171   /* Check the DMA Instance DMAx and Channel parameters*/
00172   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
00173
00174     tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
00175
00176     /* Disable the selected DMAx_Channely */
00177     CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
00178
00179     /* Reset DMAx_Channely control register */
00180     LL_DMA_WriteReg(tmp, CCR, 0U);
00181
00182     /* Reset DMAx_Channely remaining bytes register */
00183     LL_DMA_WriteReg(tmp, CNDTR, 0U);
00184
00185     /* Reset DMAx_Channely peripheral address register */
00186     LL_DMA_WriteReg(tmp, CPAR, 0U);
00187
00188     /* Reset DMAx_Channely memory address register */
00189     LL_DMA_WriteReg(tmp, CMAR, 0U);
00190
00191
00192     if (Channel == LL_DMA_CHANNEL_1)
00193     {
00194       /* Reset interrupt pending bits for DMAx Channel1 */
00195       LL_DMA_ClearFlag_GI1(DMAx);
00196     }
00197     else if (Channel == LL_DMA_CHANNEL_2)
00198     {
00199       /* Reset interrupt pending bits for DMAx Channel2 */
00200       LL_DMA_ClearFlag_GI2(DMAx);
00201     }
00202     else if (Channel == LL_DMA_CHANNEL_3)
00203     {
00204       /* Reset interrupt pending bits for DMAx Channel3 */
00205       LL_DMA_ClearFlag_GI3(DMAx);
00206     }
00207     else if (Channel == LL_DMA_CHANNEL_4)
00208     {
00209       /* Reset interrupt pending bits for DMAx Channel4 */
00210       LL_DMA_ClearFlag_GI4(DMAx);
00211     }
00212     else if (Channel == LL_DMA_CHANNEL_5)
00213     {
00214       /* Reset interrupt pending bits for DMAx Channel5 */
00215       LL_DMA_ClearFlag_GI5(DMAx);
00216     }
00217
00218     else if (Channel == LL_DMA_CHANNEL_6)
00219     {
00220       /* Reset interrupt pending bits for DMAx Channel6 */
00221       LL_DMA_ClearFlag_GI6(DMAx);
00222     }
00223     else if (Channel == LL_DMA_CHANNEL_7)
00224     {
00225       /* Reset interrupt pending bits for DMAx Channel7 */
00226       LL_DMA_ClearFlag_GI7(DMAx);
00227     }
00228     else
00229     {
00230       status = ERROR;
00231     }
00232
00233   return status;
00234 }
00235
00236 /**
00237   * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
00238   * @note   To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
00239   *         @arg @ref __LL_DMA_GET_INSTANCE
00240   *         @arg @ref __LL_DMA_GET_CHANNEL
00241   * @param  DMAx DMAx Instance
00242   * @param  Channel This parameter can be one of the following values:
00243   *         @arg @ref LL_DMA_CHANNEL_1
00244   *         @arg @ref LL_DMA_CHANNEL_2
00245   *         @arg @ref LL_DMA_CHANNEL_3
00246   *         @arg @ref LL_DMA_CHANNEL_4
00247   *         @arg @ref LL_DMA_CHANNEL_5
00248   *         @arg @ref LL_DMA_CHANNEL_6
00249   *         @arg @ref LL_DMA_CHANNEL_7
00250   * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
00251   * @retval An ErrorStatus enumeration value:
00252   *          - SUCCESS: DMA registers are initialized
00253   *          - ERROR: Not applicable
00254   */
00255 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
00256 {
00257   /* Check the DMA Instance DMAx and Channel parameters*/
00258   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
00259
00260   /* Check the DMA parameters from DMA_InitStruct */
00261   assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
00262   assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
00263   assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
00264   assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
00265   assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
00266   assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
00267   assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
00268   assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
00269
00270   /*---------------------------- DMAx CCR Configuration ------------------------
00271    * Configure DMAx_Channely: data transfer direction, data transfer mode,
00272    *                          peripheral and memory increment mode,
00273    *                          data size alignment and  priority level with parameters :
00274    * - Direction:      DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
00275    * - Mode:           DMA_CCR_CIRC bit
00276    * - PeriphOrM2MSrcIncMode:  DMA_CCR_PINC bit
00277    * - MemoryOrM2MDstIncMode:  DMA_CCR_MINC bit
00278    * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
00279    * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
00280    * - Priority:               DMA_CCR_PL[1:0] bits
00281    */
00282   LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction              | \
00283                         DMA_InitStruct->Mode                   | \
00284                         DMA_InitStruct->PeriphOrM2MSrcIncMode  | \
00285                         DMA_InitStruct->MemoryOrM2MDstIncMode  | \
00286                         DMA_InitStruct->PeriphOrM2MSrcDataSize | \
00287                         DMA_InitStruct->MemoryOrM2MDstDataSize | \
00288                         DMA_InitStruct->Priority);
00289
00290   /*-------------------------- DMAx CMAR Configuration -------------------------
00291    * Configure the memory or destination base address with parameter :
00292    * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
00293    */
00294   LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
00295
00296   /*-------------------------- DMAx CPAR Configuration -------------------------
00297    * Configure the peripheral or source base address with parameter :
00298    * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
00299    */
00300   LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
00301
00302   /*--------------------------- DMAx CNDTR Configuration -----------------------
00303    * Configure the peripheral base address with parameter :
00304    * - NbData: DMA_CNDTR_NDT[15:0] bits
00305    */
00306   LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
00307
00308
00309   return SUCCESS;
00310 }
00311
00312 /**
00313   * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
00314   * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
00315   * @retval None
00316   */
00317 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
00318 {
00319   /* Set DMA_InitStruct fields to default values */
00320   DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
00321   DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
00322   DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
00323   DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
00324   DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
00325   DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
00326   DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
00327   DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
00328   DMA_InitStruct->NbData                 = 0x00000000U;
00329   DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
00330 }
00331
00332 /**
00333   * @}
00334   */
00335
00336 /**
00337   * @}
00338   */
00339
00340 /**
00341   * @}
00342   */
00343
00344 #endif /* DMA1 || DMA2 */
00345
00346 /**
00347   * @}
00348   */
00349
00350 #endif /* USE_FULL_LL_DRIVER */
00351
00352 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_dma.h Source File

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stm32f3xx_ll_dma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_dma.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_DMA_H
00038 #define __STM32F3xx_LL_DMA_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined (DMA1) || defined (DMA2)
00052
00053 /** @defgroup DMA_LL DMA
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
00060   * @{
00061   */
00062 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
00063 static const uint8_t CHANNEL_OFFSET_TAB[] =
00064 {
00065   (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
00066   (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
00067   (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
00068   (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
00069   (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
00070   (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
00071   (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
00072 };
00073 /**
00074   * @}
00075   */
00076
00077 /* Private constants ---------------------------------------------------------*/
00078 /* Private macros ------------------------------------------------------------*/
00079 #if defined(USE_FULL_LL_DRIVER)
00080 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
00081   * @{
00082   */
00083 /**
00084   * @}
00085   */
00086 #endif /*USE_FULL_LL_DRIVER*/
00087
00088 /* Exported types ------------------------------------------------------------*/
00089 #if defined(USE_FULL_LL_DRIVER)
00090 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
00091   * @{
00092   */
00093 typedef struct
00094 {
00095   uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
00096                                         or as Source base address in case of memory to memory transfer direction.
00097
00098                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
00099
00100   uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
00101                                         or as Destination base address in case of memory to memory transfer direction.
00102
00103                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
00104
00105   uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
00106                                         from memory to memory or from peripheral to memory.
00107                                         This parameter can be a value of @ref DMA_LL_EC_DIRECTION
00108
00109                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
00110
00111   uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
00112                                         This parameter can be a value of @ref DMA_LL_EC_MODE
00113                                         @note: The circular buffer mode cannot be used if the memory to memory
00114                                                data transfer direction is configured on the selected Channel
00115
00116                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
00117
00118   uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
00119                                         is incremented or not.
00120                                         This parameter can be a value of @ref DMA_LL_EC_PERIPH
00121
00122                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
00123
00124   uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
00125                                         is incremented or not.
00126                                         This parameter can be a value of @ref DMA_LL_EC_MEMORY
00127
00128                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
00129
00130   uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
00131                                         in case of memory to memory transfer direction.
00132                                         This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
00133
00134                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
00135
00136   uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
00137                                         in case of memory to memory transfer direction.
00138                                         This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
00139
00140                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
00141
00142   uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
00143                                         The data unit is equal to the source buffer configuration set in PeripheralSize
00144                                         or MemorySize parameters depending in the transfer direction.
00145                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
00146
00147                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
00148
00149   uint32_t Priority;               /*!< Specifies the channel priority level.
00150                                         This parameter can be a value of @ref DMA_LL_EC_PRIORITY
00151
00152                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
00153
00154 } LL_DMA_InitTypeDef;
00155 /**
00156   * @}
00157   */
00158 #endif /*USE_FULL_LL_DRIVER*/
00159
00160 /* Exported constants --------------------------------------------------------*/
00161 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
00162   * @{
00163   */
00164 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
00165   * @brief    Flags defines which can be used with LL_DMA_WriteReg function
00166   * @{
00167   */
00168 #define LL_DMA_IFCR_CGIF1                 DMA_IFCR_CGIF1        /*!< Channel 1 global flag            */
00169 #define LL_DMA_IFCR_CTCIF1                DMA_IFCR_CTCIF1       /*!< Channel 1 transfer complete flag */
00170 #define LL_DMA_IFCR_CHTIF1                DMA_IFCR_CHTIF1       /*!< Channel 1 half transfer flag     */
00171 #define LL_DMA_IFCR_CTEIF1                DMA_IFCR_CTEIF1       /*!< Channel 1 transfer error flag    */
00172 #define LL_DMA_IFCR_CGIF2                 DMA_IFCR_CGIF2        /*!< Channel 2 global flag            */
00173 #define LL_DMA_IFCR_CTCIF2                DMA_IFCR_CTCIF2       /*!< Channel 2 transfer complete flag */
00174 #define LL_DMA_IFCR_CHTIF2                DMA_IFCR_CHTIF2       /*!< Channel 2 half transfer flag     */
00175 #define LL_DMA_IFCR_CTEIF2                DMA_IFCR_CTEIF2       /*!< Channel 2 transfer error flag    */
00176 #define LL_DMA_IFCR_CGIF3                 DMA_IFCR_CGIF3        /*!< Channel 3 global flag            */
00177 #define LL_DMA_IFCR_CTCIF3                DMA_IFCR_CTCIF3       /*!< Channel 3 transfer complete flag */
00178 #define LL_DMA_IFCR_CHTIF3                DMA_IFCR_CHTIF3       /*!< Channel 3 half transfer flag     */
00179 #define LL_DMA_IFCR_CTEIF3                DMA_IFCR_CTEIF3       /*!< Channel 3 transfer error flag    */
00180 #define LL_DMA_IFCR_CGIF4                 DMA_IFCR_CGIF4        /*!< Channel 4 global flag            */
00181 #define LL_DMA_IFCR_CTCIF4                DMA_IFCR_CTCIF4       /*!< Channel 4 transfer complete flag */
00182 #define LL_DMA_IFCR_CHTIF4                DMA_IFCR_CHTIF4       /*!< Channel 4 half transfer flag     */
00183 #define LL_DMA_IFCR_CTEIF4                DMA_IFCR_CTEIF4       /*!< Channel 4 transfer error flag    */
00184 #define LL_DMA_IFCR_CGIF5                 DMA_IFCR_CGIF5        /*!< Channel 5 global flag            */
00185 #define LL_DMA_IFCR_CTCIF5                DMA_IFCR_CTCIF5       /*!< Channel 5 transfer complete flag */
00186 #define LL_DMA_IFCR_CHTIF5                DMA_IFCR_CHTIF5       /*!< Channel 5 half transfer flag     */
00187 #define LL_DMA_IFCR_CTEIF5                DMA_IFCR_CTEIF5       /*!< Channel 5 transfer error flag    */
00188 #define LL_DMA_IFCR_CGIF6                 DMA_IFCR_CGIF6        /*!< Channel 6 global flag            */
00189 #define LL_DMA_IFCR_CTCIF6                DMA_IFCR_CTCIF6       /*!< Channel 6 transfer complete flag */
00190 #define LL_DMA_IFCR_CHTIF6                DMA_IFCR_CHTIF6       /*!< Channel 6 half transfer flag     */
00191 #define LL_DMA_IFCR_CTEIF6                DMA_IFCR_CTEIF6       /*!< Channel 6 transfer error flag    */
00192 #define LL_DMA_IFCR_CGIF7                 DMA_IFCR_CGIF7        /*!< Channel 7 global flag            */
00193 #define LL_DMA_IFCR_CTCIF7                DMA_IFCR_CTCIF7       /*!< Channel 7 transfer complete flag */
00194 #define LL_DMA_IFCR_CHTIF7                DMA_IFCR_CHTIF7       /*!< Channel 7 half transfer flag     */
00195 #define LL_DMA_IFCR_CTEIF7                DMA_IFCR_CTEIF7       /*!< Channel 7 transfer error flag    */
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
00201   * @brief    Flags defines which can be used with LL_DMA_ReadReg function
00202   * @{
00203   */
00204 #define LL_DMA_ISR_GIF1                   DMA_ISR_GIF1          /*!< Channel 1 global flag            */
00205 #define LL_DMA_ISR_TCIF1                  DMA_ISR_TCIF1         /*!< Channel 1 transfer complete flag */
00206 #define LL_DMA_ISR_HTIF1                  DMA_ISR_HTIF1         /*!< Channel 1 half transfer flag     */
00207 #define LL_DMA_ISR_TEIF1                  DMA_ISR_TEIF1         /*!< Channel 1 transfer error flag    */
00208 #define LL_DMA_ISR_GIF2                   DMA_ISR_GIF2          /*!< Channel 2 global flag            */
00209 #define LL_DMA_ISR_TCIF2                  DMA_ISR_TCIF2         /*!< Channel 2 transfer complete flag */
00210 #define LL_DMA_ISR_HTIF2                  DMA_ISR_HTIF2         /*!< Channel 2 half transfer flag     */
00211 #define LL_DMA_ISR_TEIF2                  DMA_ISR_TEIF2         /*!< Channel 2 transfer error flag    */
00212 #define LL_DMA_ISR_GIF3                   DMA_ISR_GIF3          /*!< Channel 3 global flag            */
00213 #define LL_DMA_ISR_TCIF3                  DMA_ISR_TCIF3         /*!< Channel 3 transfer complete flag */
00214 #define LL_DMA_ISR_HTIF3                  DMA_ISR_HTIF3         /*!< Channel 3 half transfer flag     */
00215 #define LL_DMA_ISR_TEIF3                  DMA_ISR_TEIF3         /*!< Channel 3 transfer error flag    */
00216 #define LL_DMA_ISR_GIF4                   DMA_ISR_GIF4          /*!< Channel 4 global flag            */
00217 #define LL_DMA_ISR_TCIF4                  DMA_ISR_TCIF4         /*!< Channel 4 transfer complete flag */
00218 #define LL_DMA_ISR_HTIF4                  DMA_ISR_HTIF4         /*!< Channel 4 half transfer flag     */
00219 #define LL_DMA_ISR_TEIF4                  DMA_ISR_TEIF4         /*!< Channel 4 transfer error flag    */
00220 #define LL_DMA_ISR_GIF5                   DMA_ISR_GIF5          /*!< Channel 5 global flag            */
00221 #define LL_DMA_ISR_TCIF5                  DMA_ISR_TCIF5         /*!< Channel 5 transfer complete flag */
00222 #define LL_DMA_ISR_HTIF5                  DMA_ISR_HTIF5         /*!< Channel 5 half transfer flag     */
00223 #define LL_DMA_ISR_TEIF5                  DMA_ISR_TEIF5         /*!< Channel 5 transfer error flag    */
00224 #define LL_DMA_ISR_GIF6                   DMA_ISR_GIF6          /*!< Channel 6 global flag            */
00225 #define LL_DMA_ISR_TCIF6                  DMA_ISR_TCIF6         /*!< Channel 6 transfer complete flag */
00226 #define LL_DMA_ISR_HTIF6                  DMA_ISR_HTIF6         /*!< Channel 6 half transfer flag     */
00227 #define LL_DMA_ISR_TEIF6                  DMA_ISR_TEIF6         /*!< Channel 6 transfer error flag    */
00228 #define LL_DMA_ISR_GIF7                   DMA_ISR_GIF7          /*!< Channel 7 global flag            */
00229 #define LL_DMA_ISR_TCIF7                  DMA_ISR_TCIF7         /*!< Channel 7 transfer complete flag */
00230 #define LL_DMA_ISR_HTIF7                  DMA_ISR_HTIF7         /*!< Channel 7 half transfer flag     */
00231 #define LL_DMA_ISR_TEIF7                  DMA_ISR_TEIF7         /*!< Channel 7 transfer error flag    */
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup DMA_LL_EC_IT IT Defines
00237   * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMA_WriteReg functions
00238   * @{
00239   */
00240 #define LL_DMA_CCR_TCIE                   DMA_CCR_TCIE          /*!< Transfer complete interrupt */
00241 #define LL_DMA_CCR_HTIE                   DMA_CCR_HTIE          /*!< Half Transfer interrupt     */
00242 #define LL_DMA_CCR_TEIE                   DMA_CCR_TEIE          /*!< Transfer error interrupt    */
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
00248   * @{
00249   */
00250 #define LL_DMA_CHANNEL_1                  0x00000001U /*!< DMA Channel 1 */
00251 #define LL_DMA_CHANNEL_2                  0x00000002U /*!< DMA Channel 2 */
00252 #define LL_DMA_CHANNEL_3                  0x00000003U /*!< DMA Channel 3 */
00253 #define LL_DMA_CHANNEL_4                  0x00000004U /*!< DMA Channel 4 */
00254 #define LL_DMA_CHANNEL_5                  0x00000005U /*!< DMA Channel 5 */
00255 #define LL_DMA_CHANNEL_6                  0x00000006U /*!< DMA Channel 6 */
00256 #define LL_DMA_CHANNEL_7                  0x00000007U /*!< DMA Channel 7 */
00257 #if defined(USE_FULL_LL_DRIVER)
00258 #define LL_DMA_CHANNEL_ALL                0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
00259 #endif /*USE_FULL_LL_DRIVER*/
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
00265   * @{
00266   */
00267 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U             /*!< Peripheral to memory direction */
00268 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR             /*!< Memory to peripheral direction */
00269 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM         /*!< Memory to memory direction     */
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup DMA_LL_EC_MODE Transfer mode
00275   * @{
00276   */
00277 #define LL_DMA_MODE_NORMAL                0x00000000U             /*!< Normal Mode                  */
00278 #define LL_DMA_MODE_CIRCULAR              DMA_CCR_CIRC            /*!< Circular Mode                */
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
00284   * @{
00285   */
00286 #define LL_DMA_PERIPH_INCREMENT           DMA_CCR_PINC            /*!< Peripheral increment mode Enable */
00287 #define LL_DMA_PERIPH_NOINCREMENT         0x00000000U             /*!< Peripheral increment mode Disable */
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
00293   * @{
00294   */
00295 #define LL_DMA_MEMORY_INCREMENT           DMA_CCR_MINC            /*!< Memory increment mode Enable  */
00296 #define LL_DMA_MEMORY_NOINCREMENT         0x00000000U             /*!< Memory increment mode Disable */
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
00302   * @{
00303   */
00304 #define LL_DMA_PDATAALIGN_BYTE            0x00000000U             /*!< Peripheral data alignment : Byte     */
00305 #define LL_DMA_PDATAALIGN_HALFWORD        DMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */
00306 #define LL_DMA_PDATAALIGN_WORD            DMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
00312   * @{
00313   */
00314 #define LL_DMA_MDATAALIGN_BYTE            0x00000000U             /*!< Memory data alignment : Byte     */
00315 #define LL_DMA_MDATAALIGN_HALFWORD        DMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord */
00316 #define LL_DMA_MDATAALIGN_WORD            DMA_CCR_MSIZE_1         /*!< Memory data alignment : Word     */
00317 /**
00318   * @}
00319   */
00320
00321 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
00322   * @{
00323   */
00324 #define LL_DMA_PRIORITY_LOW               0x00000000U             /*!< Priority level : Low       */
00325 #define LL_DMA_PRIORITY_MEDIUM            DMA_CCR_PL_0            /*!< Priority level : Medium    */
00326 #define LL_DMA_PRIORITY_HIGH              DMA_CCR_PL_1            /*!< Priority level : High      */
00327 #define LL_DMA_PRIORITY_VERYHIGH          DMA_CCR_PL              /*!< Priority level : Very_High */
00328 /**
00329   * @}
00330   */
00331
00332
00333 /**
00334   * @}
00335   */
00336
00337 /* Exported macro ------------------------------------------------------------*/
00338 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
00339   * @{
00340   */
00341
00342 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
00343   * @{
00344   */
00345 /**
00346   * @brief  Write a value in DMA register
00347   * @param  __INSTANCE__ DMA Instance
00348   * @param  __REG__ Register to be written
00349   * @param  __VALUE__ Value to be written in the register
00350   * @retval None
00351   */
00352 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00353
00354 /**
00355   * @brief  Read a value in DMA register
00356   * @param  __INSTANCE__ DMA Instance
00357   * @param  __REG__ Register to be read
00358   * @retval Register value
00359   */
00360 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00361 /**
00362   * @}
00363   */
00364
00365 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
00366   * @{
00367   */
00368 /**
00369   * @brief  Convert DMAx_Channely into DMAx
00370   * @param  __CHANNEL_INSTANCE__ DMAx_Channely
00371   * @retval DMAx
00372   */
00373 #if defined(DMA2)
00374 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)   \
00375 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ?  DMA2 : DMA1)
00376 #else
00377 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)  (DMA1)
00378 #endif
00379
00380 /**
00381   * @brief  Convert DMAx_Channely into LL_DMA_CHANNEL_y
00382   * @param  __CHANNEL_INSTANCE__ DMAx_Channely
00383   * @retval LL_DMA_CHANNEL_y
00384   */
00385 #if defined (DMA2)
00386 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
00387 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
00388 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
00389  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
00390  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
00391  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
00392  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
00393  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
00394  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
00395  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
00396  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
00397  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
00398  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
00399  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
00400  LL_DMA_CHANNEL_7)
00401 #else
00402 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
00403 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
00404  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
00405  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
00406  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
00407  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
00408  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
00409  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
00410  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
00411  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
00412  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
00413  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
00414  LL_DMA_CHANNEL_7)
00415 #endif
00416 #else
00417 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
00418 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
00419  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
00420  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
00421  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
00422  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
00423  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
00424  LL_DMA_CHANNEL_7)
00425 #endif
00426
00427 /**
00428   * @brief  Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
00429   * @param  __DMA_INSTANCE__ DMAx
00430   * @param  __CHANNEL__ LL_DMA_CHANNEL_y
00431   * @retval DMAx_Channely
00432   */
00433 #if defined (DMA2)
00434 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
00435 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
00436 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
00437  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
00438  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
00439  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
00440  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
00441  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
00442  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
00443  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
00444  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
00445  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
00446  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
00447  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
00448  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
00449  DMA2_Channel7)
00450 #else
00451 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
00452 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
00453  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
00454  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
00455  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
00456  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
00457  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
00458  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
00459  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
00460  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
00461  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
00462  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
00463  DMA1_Channel7)
00464 #endif
00465 #else
00466 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
00467 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
00468  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
00469  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
00470  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
00471  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
00472  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
00473  DMA1_Channel7)
00474 #endif
00475
00476 /**
00477   * @}
00478   */
00479
00480 /**
00481   * @}
00482   */
00483
00484 /* Exported functions --------------------------------------------------------*/
00485 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
00486  * @{
00487  */
00488
00489 /** @defgroup DMA_LL_EF_Configuration Configuration
00490   * @{
00491   */
00492 /**
00493   * @brief  Enable DMA channel.
00494   * @rmtoll CCR          EN            LL_DMA_EnableChannel
00495   * @param  DMAx DMAx Instance
00496   * @param  Channel This parameter can be one of the following values:
00497   *         @arg @ref LL_DMA_CHANNEL_1
00498   *         @arg @ref LL_DMA_CHANNEL_2
00499   *         @arg @ref LL_DMA_CHANNEL_3
00500   *         @arg @ref LL_DMA_CHANNEL_4
00501   *         @arg @ref LL_DMA_CHANNEL_5
00502   *         @arg @ref LL_DMA_CHANNEL_6
00503   *         @arg @ref LL_DMA_CHANNEL_7
00504   * @retval None
00505   */
00506 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00507 {
00508   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
00509 }
00510
00511 /**
00512   * @brief  Disable DMA channel.
00513   * @rmtoll CCR          EN            LL_DMA_DisableChannel
00514   * @param  DMAx DMAx Instance
00515   * @param  Channel This parameter can be one of the following values:
00516   *         @arg @ref LL_DMA_CHANNEL_1
00517   *         @arg @ref LL_DMA_CHANNEL_2
00518   *         @arg @ref LL_DMA_CHANNEL_3
00519   *         @arg @ref LL_DMA_CHANNEL_4
00520   *         @arg @ref LL_DMA_CHANNEL_5
00521   *         @arg @ref LL_DMA_CHANNEL_6
00522   *         @arg @ref LL_DMA_CHANNEL_7
00523   * @retval None
00524   */
00525 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00526 {
00527   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
00528 }
00529
00530 /**
00531   * @brief  Check if DMA channel is enabled or disabled.
00532   * @rmtoll CCR          EN            LL_DMA_IsEnabledChannel
00533   * @param  DMAx DMAx Instance
00534   * @param  Channel This parameter can be one of the following values:
00535   *         @arg @ref LL_DMA_CHANNEL_1
00536   *         @arg @ref LL_DMA_CHANNEL_2
00537   *         @arg @ref LL_DMA_CHANNEL_3
00538   *         @arg @ref LL_DMA_CHANNEL_4
00539   *         @arg @ref LL_DMA_CHANNEL_5
00540   *         @arg @ref LL_DMA_CHANNEL_6
00541   *         @arg @ref LL_DMA_CHANNEL_7
00542   * @retval State of bit (1 or 0).
00543   */
00544 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00545 {
00546   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00547                    DMA_CCR_EN) == (DMA_CCR_EN));
00548 }
00549
00550 /**
00551   * @brief  Configure all parameters link to DMA transfer.
00552   * @rmtoll CCR          DIR           LL_DMA_ConfigTransfer\n
00553   *         CCR          MEM2MEM       LL_DMA_ConfigTransfer\n
00554   *         CCR          CIRC          LL_DMA_ConfigTransfer\n
00555   *         CCR          PINC          LL_DMA_ConfigTransfer\n
00556   *         CCR          MINC          LL_DMA_ConfigTransfer\n
00557   *         CCR          PSIZE         LL_DMA_ConfigTransfer\n
00558   *         CCR          MSIZE         LL_DMA_ConfigTransfer\n
00559   *         CCR          PL            LL_DMA_ConfigTransfer
00560   * @param  DMAx DMAx Instance
00561   * @param  Channel This parameter can be one of the following values:
00562   *         @arg @ref LL_DMA_CHANNEL_1
00563   *         @arg @ref LL_DMA_CHANNEL_2
00564   *         @arg @ref LL_DMA_CHANNEL_3
00565   *         @arg @ref LL_DMA_CHANNEL_4
00566   *         @arg @ref LL_DMA_CHANNEL_5
00567   *         @arg @ref LL_DMA_CHANNEL_6
00568   *         @arg @ref LL_DMA_CHANNEL_7
00569   * @param  Configuration This parameter must be a combination of all the following values:
00570   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00571   *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
00572   *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
00573   *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
00574   *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
00575   *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
00576   *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
00577   * @retval None
00578   */
00579 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
00580 {
00581   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00582              DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
00583              Configuration);
00584 }
00585
00586 /**
00587   * @brief  Set Data transfer direction (read from peripheral or from memory).
00588   * @rmtoll CCR          DIR           LL_DMA_SetDataTransferDirection\n
00589   *         CCR          MEM2MEM       LL_DMA_SetDataTransferDirection
00590   * @param  DMAx DMAx Instance
00591   * @param  Channel This parameter can be one of the following values:
00592   *         @arg @ref LL_DMA_CHANNEL_1
00593   *         @arg @ref LL_DMA_CHANNEL_2
00594   *         @arg @ref LL_DMA_CHANNEL_3
00595   *         @arg @ref LL_DMA_CHANNEL_4
00596   *         @arg @ref LL_DMA_CHANNEL_5
00597   *         @arg @ref LL_DMA_CHANNEL_6
00598   *         @arg @ref LL_DMA_CHANNEL_7
00599   * @param  Direction This parameter can be one of the following values:
00600   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00601   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00602   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00603   * @retval None
00604   */
00605 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
00606 {
00607   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00608              DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
00609 }
00610
00611 /**
00612   * @brief  Get Data transfer direction (read from peripheral or from memory).
00613   * @rmtoll CCR          DIR           LL_DMA_GetDataTransferDirection\n
00614   *         CCR          MEM2MEM       LL_DMA_GetDataTransferDirection
00615   * @param  DMAx DMAx Instance
00616   * @param  Channel This parameter can be one of the following values:
00617   *         @arg @ref LL_DMA_CHANNEL_1
00618   *         @arg @ref LL_DMA_CHANNEL_2
00619   *         @arg @ref LL_DMA_CHANNEL_3
00620   *         @arg @ref LL_DMA_CHANNEL_4
00621   *         @arg @ref LL_DMA_CHANNEL_5
00622   *         @arg @ref LL_DMA_CHANNEL_6
00623   *         @arg @ref LL_DMA_CHANNEL_7
00624   * @retval Returned value can be one of the following values:
00625   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00626   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00627   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00628   */
00629 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
00630 {
00631   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00632                    DMA_CCR_DIR | DMA_CCR_MEM2MEM));
00633 }
00634
00635 /**
00636   * @brief  Set DMA mode circular or normal.
00637   * @note The circular buffer mode cannot be used if the memory-to-memory
00638   * data transfer is configured on the selected Channel.
00639   * @rmtoll CCR          CIRC          LL_DMA_SetMode
00640   * @param  DMAx DMAx Instance
00641   * @param  Channel This parameter can be one of the following values:
00642   *         @arg @ref LL_DMA_CHANNEL_1
00643   *         @arg @ref LL_DMA_CHANNEL_2
00644   *         @arg @ref LL_DMA_CHANNEL_3
00645   *         @arg @ref LL_DMA_CHANNEL_4
00646   *         @arg @ref LL_DMA_CHANNEL_5
00647   *         @arg @ref LL_DMA_CHANNEL_6
00648   *         @arg @ref LL_DMA_CHANNEL_7
00649   * @param  Mode This parameter can be one of the following values:
00650   *         @arg @ref LL_DMA_MODE_NORMAL
00651   *         @arg @ref LL_DMA_MODE_CIRCULAR
00652   * @retval None
00653   */
00654 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
00655 {
00656   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
00657              Mode);
00658 }
00659
00660 /**
00661   * @brief  Get DMA mode circular or normal.
00662   * @rmtoll CCR          CIRC          LL_DMA_GetMode
00663   * @param  DMAx DMAx Instance
00664   * @param  Channel This parameter can be one of the following values:
00665   *         @arg @ref LL_DMA_CHANNEL_1
00666   *         @arg @ref LL_DMA_CHANNEL_2
00667   *         @arg @ref LL_DMA_CHANNEL_3
00668   *         @arg @ref LL_DMA_CHANNEL_4
00669   *         @arg @ref LL_DMA_CHANNEL_5
00670   *         @arg @ref LL_DMA_CHANNEL_6
00671   *         @arg @ref LL_DMA_CHANNEL_7
00672   * @retval Returned value can be one of the following values:
00673   *         @arg @ref LL_DMA_MODE_NORMAL
00674   *         @arg @ref LL_DMA_MODE_CIRCULAR
00675   */
00676 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
00677 {
00678   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00679                    DMA_CCR_CIRC));
00680 }
00681
00682 /**
00683   * @brief  Set Peripheral increment mode.
00684   * @rmtoll CCR          PINC          LL_DMA_SetPeriphIncMode
00685   * @param  DMAx DMAx Instance
00686   * @param  Channel This parameter can be one of the following values:
00687   *         @arg @ref LL_DMA_CHANNEL_1
00688   *         @arg @ref LL_DMA_CHANNEL_2
00689   *         @arg @ref LL_DMA_CHANNEL_3
00690   *         @arg @ref LL_DMA_CHANNEL_4
00691   *         @arg @ref LL_DMA_CHANNEL_5
00692   *         @arg @ref LL_DMA_CHANNEL_6
00693   *         @arg @ref LL_DMA_CHANNEL_7
00694   * @param  PeriphOrM2MSrcIncMode This parameter can be one of the following values:
00695   *         @arg @ref LL_DMA_PERIPH_INCREMENT
00696   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
00697   * @retval None
00698   */
00699 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
00700 {
00701   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
00702              PeriphOrM2MSrcIncMode);
00703 }
00704
00705 /**
00706   * @brief  Get Peripheral increment mode.
00707   * @rmtoll CCR          PINC          LL_DMA_GetPeriphIncMode
00708   * @param  DMAx DMAx Instance
00709   * @param  Channel This parameter can be one of the following values:
00710   *         @arg @ref LL_DMA_CHANNEL_1
00711   *         @arg @ref LL_DMA_CHANNEL_2
00712   *         @arg @ref LL_DMA_CHANNEL_3
00713   *         @arg @ref LL_DMA_CHANNEL_4
00714   *         @arg @ref LL_DMA_CHANNEL_5
00715   *         @arg @ref LL_DMA_CHANNEL_6
00716   *         @arg @ref LL_DMA_CHANNEL_7
00717   * @retval Returned value can be one of the following values:
00718   *         @arg @ref LL_DMA_PERIPH_INCREMENT
00719   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
00720   */
00721 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
00722 {
00723   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00724                    DMA_CCR_PINC));
00725 }
00726
00727 /**
00728   * @brief  Set Memory increment mode.
00729   * @rmtoll CCR          MINC          LL_DMA_SetMemoryIncMode
00730   * @param  DMAx DMAx Instance
00731   * @param  Channel This parameter can be one of the following values:
00732   *         @arg @ref LL_DMA_CHANNEL_1
00733   *         @arg @ref LL_DMA_CHANNEL_2
00734   *         @arg @ref LL_DMA_CHANNEL_3
00735   *         @arg @ref LL_DMA_CHANNEL_4
00736   *         @arg @ref LL_DMA_CHANNEL_5
00737   *         @arg @ref LL_DMA_CHANNEL_6
00738   *         @arg @ref LL_DMA_CHANNEL_7
00739   * @param  MemoryOrM2MDstIncMode This parameter can be one of the following values:
00740   *         @arg @ref LL_DMA_MEMORY_INCREMENT
00741   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
00742   * @retval None
00743   */
00744 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
00745 {
00746   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
00747              MemoryOrM2MDstIncMode);
00748 }
00749
00750 /**
00751   * @brief  Get Memory increment mode.
00752   * @rmtoll CCR          MINC          LL_DMA_GetMemoryIncMode
00753   * @param  DMAx DMAx Instance
00754   * @param  Channel This parameter can be one of the following values:
00755   *         @arg @ref LL_DMA_CHANNEL_1
00756   *         @arg @ref LL_DMA_CHANNEL_2
00757   *         @arg @ref LL_DMA_CHANNEL_3
00758   *         @arg @ref LL_DMA_CHANNEL_4
00759   *         @arg @ref LL_DMA_CHANNEL_5
00760   *         @arg @ref LL_DMA_CHANNEL_6
00761   *         @arg @ref LL_DMA_CHANNEL_7
00762   * @retval Returned value can be one of the following values:
00763   *         @arg @ref LL_DMA_MEMORY_INCREMENT
00764   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
00765   */
00766 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
00767 {
00768   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00769                    DMA_CCR_MINC));
00770 }
00771
00772 /**
00773   * @brief  Set Peripheral size.
00774   * @rmtoll CCR          PSIZE         LL_DMA_SetPeriphSize
00775   * @param  DMAx DMAx Instance
00776   * @param  Channel This parameter can be one of the following values:
00777   *         @arg @ref LL_DMA_CHANNEL_1
00778   *         @arg @ref LL_DMA_CHANNEL_2
00779   *         @arg @ref LL_DMA_CHANNEL_3
00780   *         @arg @ref LL_DMA_CHANNEL_4
00781   *         @arg @ref LL_DMA_CHANNEL_5
00782   *         @arg @ref LL_DMA_CHANNEL_6
00783   *         @arg @ref LL_DMA_CHANNEL_7
00784   * @param  PeriphOrM2MSrcDataSize This parameter can be one of the following values:
00785   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
00786   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
00787   *         @arg @ref LL_DMA_PDATAALIGN_WORD
00788   * @retval None
00789   */
00790 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
00791 {
00792   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
00793              PeriphOrM2MSrcDataSize);
00794 }
00795
00796 /**
00797   * @brief  Get Peripheral size.
00798   * @rmtoll CCR          PSIZE         LL_DMA_GetPeriphSize
00799   * @param  DMAx DMAx Instance
00800   * @param  Channel This parameter can be one of the following values:
00801   *         @arg @ref LL_DMA_CHANNEL_1
00802   *         @arg @ref LL_DMA_CHANNEL_2
00803   *         @arg @ref LL_DMA_CHANNEL_3
00804   *         @arg @ref LL_DMA_CHANNEL_4
00805   *         @arg @ref LL_DMA_CHANNEL_5
00806   *         @arg @ref LL_DMA_CHANNEL_6
00807   *         @arg @ref LL_DMA_CHANNEL_7
00808   * @retval Returned value can be one of the following values:
00809   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
00810   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
00811   *         @arg @ref LL_DMA_PDATAALIGN_WORD
00812   */
00813 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
00814 {
00815   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00816                    DMA_CCR_PSIZE));
00817 }
00818
00819 /**
00820   * @brief  Set Memory size.
00821   * @rmtoll CCR          MSIZE         LL_DMA_SetMemorySize
00822   * @param  DMAx DMAx Instance
00823   * @param  Channel This parameter can be one of the following values:
00824   *         @arg @ref LL_DMA_CHANNEL_1
00825   *         @arg @ref LL_DMA_CHANNEL_2
00826   *         @arg @ref LL_DMA_CHANNEL_3
00827   *         @arg @ref LL_DMA_CHANNEL_4
00828   *         @arg @ref LL_DMA_CHANNEL_5
00829   *         @arg @ref LL_DMA_CHANNEL_6
00830   *         @arg @ref LL_DMA_CHANNEL_7
00831   * @param  MemoryOrM2MDstDataSize This parameter can be one of the following values:
00832   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
00833   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
00834   *         @arg @ref LL_DMA_MDATAALIGN_WORD
00835   * @retval None
00836   */
00837 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
00838 {
00839   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
00840              MemoryOrM2MDstDataSize);
00841 }
00842
00843 /**
00844   * @brief  Get Memory size.
00845   * @rmtoll CCR          MSIZE         LL_DMA_GetMemorySize
00846   * @param  DMAx DMAx Instance
00847   * @param  Channel This parameter can be one of the following values:
00848   *         @arg @ref LL_DMA_CHANNEL_1
00849   *         @arg @ref LL_DMA_CHANNEL_2
00850   *         @arg @ref LL_DMA_CHANNEL_3
00851   *         @arg @ref LL_DMA_CHANNEL_4
00852   *         @arg @ref LL_DMA_CHANNEL_5
00853   *         @arg @ref LL_DMA_CHANNEL_6
00854   *         @arg @ref LL_DMA_CHANNEL_7
00855   * @retval Returned value can be one of the following values:
00856   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
00857   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
00858   *         @arg @ref LL_DMA_MDATAALIGN_WORD
00859   */
00860 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
00861 {
00862   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00863                    DMA_CCR_MSIZE));
00864 }
00865
00866 /**
00867   * @brief  Set Channel priority level.
00868   * @rmtoll CCR          PL            LL_DMA_SetChannelPriorityLevel
00869   * @param  DMAx DMAx Instance
00870   * @param  Channel This parameter can be one of the following values:
00871   *         @arg @ref LL_DMA_CHANNEL_1
00872   *         @arg @ref LL_DMA_CHANNEL_2
00873   *         @arg @ref LL_DMA_CHANNEL_3
00874   *         @arg @ref LL_DMA_CHANNEL_4
00875   *         @arg @ref LL_DMA_CHANNEL_5
00876   *         @arg @ref LL_DMA_CHANNEL_6
00877   *         @arg @ref LL_DMA_CHANNEL_7
00878   * @param  Priority This parameter can be one of the following values:
00879   *         @arg @ref LL_DMA_PRIORITY_LOW
00880   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
00881   *         @arg @ref LL_DMA_PRIORITY_HIGH
00882   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
00883   * @retval None
00884   */
00885 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
00886 {
00887   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
00888              Priority);
00889 }
00890
00891 /**
00892   * @brief  Get Channel priority level.
00893   * @rmtoll CCR          PL            LL_DMA_GetChannelPriorityLevel
00894   * @param  DMAx DMAx Instance
00895   * @param  Channel This parameter can be one of the following values:
00896   *         @arg @ref LL_DMA_CHANNEL_1
00897   *         @arg @ref LL_DMA_CHANNEL_2
00898   *         @arg @ref LL_DMA_CHANNEL_3
00899   *         @arg @ref LL_DMA_CHANNEL_4
00900   *         @arg @ref LL_DMA_CHANNEL_5
00901   *         @arg @ref LL_DMA_CHANNEL_6
00902   *         @arg @ref LL_DMA_CHANNEL_7
00903   * @retval Returned value can be one of the following values:
00904   *         @arg @ref LL_DMA_PRIORITY_LOW
00905   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
00906   *         @arg @ref LL_DMA_PRIORITY_HIGH
00907   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
00908   */
00909 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
00910 {
00911   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00912                    DMA_CCR_PL));
00913 }
00914
00915 /**
00916   * @brief  Set Number of data to transfer.
00917   * @note   This action has no effect if
00918   *         channel is enabled.
00919   * @rmtoll CNDTR        NDT           LL_DMA_SetDataLength
00920   * @param  DMAx DMAx Instance
00921   * @param  Channel This parameter can be one of the following values:
00922   *         @arg @ref LL_DMA_CHANNEL_1
00923   *         @arg @ref LL_DMA_CHANNEL_2
00924   *         @arg @ref LL_DMA_CHANNEL_3
00925   *         @arg @ref LL_DMA_CHANNEL_4
00926   *         @arg @ref LL_DMA_CHANNEL_5
00927   *         @arg @ref LL_DMA_CHANNEL_6
00928   *         @arg @ref LL_DMA_CHANNEL_7
00929   * @param  NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
00930   * @retval None
00931   */
00932 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
00933 {
00934   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
00935              DMA_CNDTR_NDT, NbData);
00936 }
00937
00938 /**
00939   * @brief  Get Number of data to transfer.
00940   * @note   Once the channel is enabled, the return value indicate the
00941   *         remaining bytes to be transmitted.
00942   * @rmtoll CNDTR        NDT           LL_DMA_GetDataLength
00943   * @param  DMAx DMAx Instance
00944   * @param  Channel This parameter can be one of the following values:
00945   *         @arg @ref LL_DMA_CHANNEL_1
00946   *         @arg @ref LL_DMA_CHANNEL_2
00947   *         @arg @ref LL_DMA_CHANNEL_3
00948   *         @arg @ref LL_DMA_CHANNEL_4
00949   *         @arg @ref LL_DMA_CHANNEL_5
00950   *         @arg @ref LL_DMA_CHANNEL_6
00951   *         @arg @ref LL_DMA_CHANNEL_7
00952   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
00953   */
00954 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
00955 {
00956   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
00957                    DMA_CNDTR_NDT));
00958 }
00959
00960 /**
00961   * @brief  Configure the Source and Destination addresses.
00962   * @note   This API must not be called when the DMA channel is enabled.
00963   * @note   Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
00964   * @rmtoll CPAR         PA            LL_DMA_ConfigAddresses\n
00965   *         CMAR         MA            LL_DMA_ConfigAddresses
00966   * @param  DMAx DMAx Instance
00967   * @param  Channel This parameter can be one of the following values:
00968   *         @arg @ref LL_DMA_CHANNEL_1
00969   *         @arg @ref LL_DMA_CHANNEL_2
00970   *         @arg @ref LL_DMA_CHANNEL_3
00971   *         @arg @ref LL_DMA_CHANNEL_4
00972   *         @arg @ref LL_DMA_CHANNEL_5
00973   *         @arg @ref LL_DMA_CHANNEL_6
00974   *         @arg @ref LL_DMA_CHANNEL_7
00975   * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
00976   * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
00977   * @param  Direction This parameter can be one of the following values:
00978   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00979   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00980   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00981   * @retval None
00982   */
00983 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
00984                                             uint32_t DstAddress, uint32_t Direction)
00985 {
00986   /* Direction Memory to Periph */
00987   if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
00988   {
00989     WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
00990     WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
00991   }
00992   /* Direction Periph to Memory and Memory to Memory */
00993   else
00994   {
00995     WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
00996     WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
00997   }
00998 }
00999
01000 /**
01001   * @brief  Set the Memory address.
01002   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01003   * @note   This API must not be called when the DMA channel is enabled.
01004   * @rmtoll CMAR         MA            LL_DMA_SetMemoryAddress
01005   * @param  DMAx DMAx Instance
01006   * @param  Channel This parameter can be one of the following values:
01007   *         @arg @ref LL_DMA_CHANNEL_1
01008   *         @arg @ref LL_DMA_CHANNEL_2
01009   *         @arg @ref LL_DMA_CHANNEL_3
01010   *         @arg @ref LL_DMA_CHANNEL_4
01011   *         @arg @ref LL_DMA_CHANNEL_5
01012   *         @arg @ref LL_DMA_CHANNEL_6
01013   *         @arg @ref LL_DMA_CHANNEL_7
01014   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01015   * @retval None
01016   */
01017 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
01018 {
01019   WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
01020 }
01021
01022 /**
01023   * @brief  Set the Peripheral address.
01024   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01025   * @note   This API must not be called when the DMA channel is enabled.
01026   * @rmtoll CPAR         PA            LL_DMA_SetPeriphAddress
01027   * @param  DMAx DMAx Instance
01028   * @param  Channel This parameter can be one of the following values:
01029   *         @arg @ref LL_DMA_CHANNEL_1
01030   *         @arg @ref LL_DMA_CHANNEL_2
01031   *         @arg @ref LL_DMA_CHANNEL_3
01032   *         @arg @ref LL_DMA_CHANNEL_4
01033   *         @arg @ref LL_DMA_CHANNEL_5
01034   *         @arg @ref LL_DMA_CHANNEL_6
01035   *         @arg @ref LL_DMA_CHANNEL_7
01036   * @param  PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01037   * @retval None
01038   */
01039 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
01040 {
01041   WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
01042 }
01043
01044 /**
01045   * @brief  Get Memory address.
01046   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01047   * @rmtoll CMAR         MA            LL_DMA_GetMemoryAddress
01048   * @param  DMAx DMAx Instance
01049   * @param  Channel This parameter can be one of the following values:
01050   *         @arg @ref LL_DMA_CHANNEL_1
01051   *         @arg @ref LL_DMA_CHANNEL_2
01052   *         @arg @ref LL_DMA_CHANNEL_3
01053   *         @arg @ref LL_DMA_CHANNEL_4
01054   *         @arg @ref LL_DMA_CHANNEL_5
01055   *         @arg @ref LL_DMA_CHANNEL_6
01056   *         @arg @ref LL_DMA_CHANNEL_7
01057   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01058   */
01059 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01060 {
01061   return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
01062 }
01063
01064 /**
01065   * @brief  Get Peripheral address.
01066   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01067   * @rmtoll CPAR         PA            LL_DMA_GetPeriphAddress
01068   * @param  DMAx DMAx Instance
01069   * @param  Channel This parameter can be one of the following values:
01070   *         @arg @ref LL_DMA_CHANNEL_1
01071   *         @arg @ref LL_DMA_CHANNEL_2
01072   *         @arg @ref LL_DMA_CHANNEL_3
01073   *         @arg @ref LL_DMA_CHANNEL_4
01074   *         @arg @ref LL_DMA_CHANNEL_5
01075   *         @arg @ref LL_DMA_CHANNEL_6
01076   *         @arg @ref LL_DMA_CHANNEL_7
01077   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01078   */
01079 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01080 {
01081   return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
01082 }
01083
01084 /**
01085   * @brief  Set the Memory to Memory Source address.
01086   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01087   * @note   This API must not be called when the DMA channel is enabled.
01088   * @rmtoll CPAR         PA            LL_DMA_SetM2MSrcAddress
01089   * @param  DMAx DMAx Instance
01090   * @param  Channel This parameter can be one of the following values:
01091   *         @arg @ref LL_DMA_CHANNEL_1
01092   *         @arg @ref LL_DMA_CHANNEL_2
01093   *         @arg @ref LL_DMA_CHANNEL_3
01094   *         @arg @ref LL_DMA_CHANNEL_4
01095   *         @arg @ref LL_DMA_CHANNEL_5
01096   *         @arg @ref LL_DMA_CHANNEL_6
01097   *         @arg @ref LL_DMA_CHANNEL_7
01098   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01099   * @retval None
01100   */
01101 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
01102 {
01103   WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
01104 }
01105
01106 /**
01107   * @brief  Set the Memory to Memory Destination address.
01108   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01109   * @note   This API must not be called when the DMA channel is enabled.
01110   * @rmtoll CMAR         MA            LL_DMA_SetM2MDstAddress
01111   * @param  DMAx DMAx Instance
01112   * @param  Channel This parameter can be one of the following values:
01113   *         @arg @ref LL_DMA_CHANNEL_1
01114   *         @arg @ref LL_DMA_CHANNEL_2
01115   *         @arg @ref LL_DMA_CHANNEL_3
01116   *         @arg @ref LL_DMA_CHANNEL_4
01117   *         @arg @ref LL_DMA_CHANNEL_5
01118   *         @arg @ref LL_DMA_CHANNEL_6
01119   *         @arg @ref LL_DMA_CHANNEL_7
01120   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01121   * @retval None
01122   */
01123 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
01124 {
01125   WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
01126 }
01127
01128 /**
01129   * @brief  Get the Memory to Memory Source address.
01130   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01131   * @rmtoll CPAR         PA            LL_DMA_GetM2MSrcAddress
01132   * @param  DMAx DMAx Instance
01133   * @param  Channel This parameter can be one of the following values:
01134   *         @arg @ref LL_DMA_CHANNEL_1
01135   *         @arg @ref LL_DMA_CHANNEL_2
01136   *         @arg @ref LL_DMA_CHANNEL_3
01137   *         @arg @ref LL_DMA_CHANNEL_4
01138   *         @arg @ref LL_DMA_CHANNEL_5
01139   *         @arg @ref LL_DMA_CHANNEL_6
01140   *         @arg @ref LL_DMA_CHANNEL_7
01141   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01142   */
01143 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01144 {
01145   return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
01146 }
01147
01148 /**
01149   * @brief  Get the Memory to Memory Destination address.
01150   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01151   * @rmtoll CMAR         MA            LL_DMA_GetM2MDstAddress
01152   * @param  DMAx DMAx Instance
01153   * @param  Channel This parameter can be one of the following values:
01154   *         @arg @ref LL_DMA_CHANNEL_1
01155   *         @arg @ref LL_DMA_CHANNEL_2
01156   *         @arg @ref LL_DMA_CHANNEL_3
01157   *         @arg @ref LL_DMA_CHANNEL_4
01158   *         @arg @ref LL_DMA_CHANNEL_5
01159   *         @arg @ref LL_DMA_CHANNEL_6
01160   *         @arg @ref LL_DMA_CHANNEL_7
01161   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01162   */
01163 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01164 {
01165   return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
01166 }
01167
01168
01169 /**
01170   * @}
01171   */
01172
01173 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
01174   * @{
01175   */
01176
01177 /**
01178   * @brief  Get Channel 1 global interrupt flag.
01179   * @rmtoll ISR          GIF1          LL_DMA_IsActiveFlag_GI1
01180   * @param  DMAx DMAx Instance
01181   * @retval State of bit (1 or 0).
01182   */
01183 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
01184 {
01185   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
01186 }
01187
01188 /**
01189   * @brief  Get Channel 2 global interrupt flag.
01190   * @rmtoll ISR          GIF2          LL_DMA_IsActiveFlag_GI2
01191   * @param  DMAx DMAx Instance
01192   * @retval State of bit (1 or 0).
01193   */
01194 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
01195 {
01196   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
01197 }
01198
01199 /**
01200   * @brief  Get Channel 3 global interrupt flag.
01201   * @rmtoll ISR          GIF3          LL_DMA_IsActiveFlag_GI3
01202   * @param  DMAx DMAx Instance
01203   * @retval State of bit (1 or 0).
01204   */
01205 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
01206 {
01207   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
01208 }
01209
01210 /**
01211   * @brief  Get Channel 4 global interrupt flag.
01212   * @rmtoll ISR          GIF4          LL_DMA_IsActiveFlag_GI4
01213   * @param  DMAx DMAx Instance
01214   * @retval State of bit (1 or 0).
01215   */
01216 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
01217 {
01218   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
01219 }
01220
01221 /**
01222   * @brief  Get Channel 5 global interrupt flag.
01223   * @rmtoll ISR          GIF5          LL_DMA_IsActiveFlag_GI5
01224   * @param  DMAx DMAx Instance
01225   * @retval State of bit (1 or 0).
01226   */
01227 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
01228 {
01229   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
01230 }
01231
01232 /**
01233   * @brief  Get Channel 6 global interrupt flag.
01234   * @rmtoll ISR          GIF6          LL_DMA_IsActiveFlag_GI6
01235   * @param  DMAx DMAx Instance
01236   * @retval State of bit (1 or 0).
01237   */
01238 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
01239 {
01240   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
01241 }
01242
01243 /**
01244   * @brief  Get Channel 7 global interrupt flag.
01245   * @rmtoll ISR          GIF7          LL_DMA_IsActiveFlag_GI7
01246   * @param  DMAx DMAx Instance
01247   * @retval State of bit (1 or 0).
01248   */
01249 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
01250 {
01251   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
01252 }
01253
01254 /**
01255   * @brief  Get Channel 1 transfer complete flag.
01256   * @rmtoll ISR          TCIF1         LL_DMA_IsActiveFlag_TC1
01257   * @param  DMAx DMAx Instance
01258   * @retval State of bit (1 or 0).
01259   */
01260 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
01261 {
01262   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
01263 }
01264
01265 /**
01266   * @brief  Get Channel 2 transfer complete flag.
01267   * @rmtoll ISR          TCIF2         LL_DMA_IsActiveFlag_TC2
01268   * @param  DMAx DMAx Instance
01269   * @retval State of bit (1 or 0).
01270   */
01271 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
01272 {
01273   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
01274 }
01275
01276 /**
01277   * @brief  Get Channel 3 transfer complete flag.
01278   * @rmtoll ISR          TCIF3         LL_DMA_IsActiveFlag_TC3
01279   * @param  DMAx DMAx Instance
01280   * @retval State of bit (1 or 0).
01281   */
01282 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
01283 {
01284   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
01285 }
01286
01287 /**
01288   * @brief  Get Channel 4 transfer complete flag.
01289   * @rmtoll ISR          TCIF4         LL_DMA_IsActiveFlag_TC4
01290   * @param  DMAx DMAx Instance
01291   * @retval State of bit (1 or 0).
01292   */
01293 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
01294 {
01295   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
01296 }
01297
01298 /**
01299   * @brief  Get Channel 5 transfer complete flag.
01300   * @rmtoll ISR          TCIF5         LL_DMA_IsActiveFlag_TC5
01301   * @param  DMAx DMAx Instance
01302   * @retval State of bit (1 or 0).
01303   */
01304 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
01305 {
01306   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
01307 }
01308
01309 /**
01310   * @brief  Get Channel 6 transfer complete flag.
01311   * @rmtoll ISR          TCIF6         LL_DMA_IsActiveFlag_TC6
01312   * @param  DMAx DMAx Instance
01313   * @retval State of bit (1 or 0).
01314   */
01315 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
01316 {
01317   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
01318 }
01319
01320 /**
01321   * @brief  Get Channel 7 transfer complete flag.
01322   * @rmtoll ISR          TCIF7         LL_DMA_IsActiveFlag_TC7
01323   * @param  DMAx DMAx Instance
01324   * @retval State of bit (1 or 0).
01325   */
01326 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
01327 {
01328   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
01329 }
01330
01331 /**
01332   * @brief  Get Channel 1 half transfer flag.
01333   * @rmtoll ISR          HTIF1         LL_DMA_IsActiveFlag_HT1
01334   * @param  DMAx DMAx Instance
01335   * @retval State of bit (1 or 0).
01336   */
01337 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
01338 {
01339   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
01340 }
01341
01342 /**
01343   * @brief  Get Channel 2 half transfer flag.
01344   * @rmtoll ISR          HTIF2         LL_DMA_IsActiveFlag_HT2
01345   * @param  DMAx DMAx Instance
01346   * @retval State of bit (1 or 0).
01347   */
01348 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
01349 {
01350   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
01351 }
01352
01353 /**
01354   * @brief  Get Channel 3 half transfer flag.
01355   * @rmtoll ISR          HTIF3         LL_DMA_IsActiveFlag_HT3
01356   * @param  DMAx DMAx Instance
01357   * @retval State of bit (1 or 0).
01358   */
01359 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
01360 {
01361   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
01362 }
01363
01364 /**
01365   * @brief  Get Channel 4 half transfer flag.
01366   * @rmtoll ISR          HTIF4         LL_DMA_IsActiveFlag_HT4
01367   * @param  DMAx DMAx Instance
01368   * @retval State of bit (1 or 0).
01369   */
01370 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
01371 {
01372   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
01373 }
01374
01375 /**
01376   * @brief  Get Channel 5 half transfer flag.
01377   * @rmtoll ISR          HTIF5         LL_DMA_IsActiveFlag_HT5
01378   * @param  DMAx DMAx Instance
01379   * @retval State of bit (1 or 0).
01380   */
01381 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
01382 {
01383   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
01384 }
01385
01386 /**
01387   * @brief  Get Channel 6 half transfer flag.
01388   * @rmtoll ISR          HTIF6         LL_DMA_IsActiveFlag_HT6
01389   * @param  DMAx DMAx Instance
01390   * @retval State of bit (1 or 0).
01391   */
01392 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
01393 {
01394   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
01395 }
01396
01397 /**
01398   * @brief  Get Channel 7 half transfer flag.
01399   * @rmtoll ISR          HTIF7         LL_DMA_IsActiveFlag_HT7
01400   * @param  DMAx DMAx Instance
01401   * @retval State of bit (1 or 0).
01402   */
01403 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
01404 {
01405   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
01406 }
01407
01408 /**
01409   * @brief  Get Channel 1 transfer error flag.
01410   * @rmtoll ISR          TEIF1         LL_DMA_IsActiveFlag_TE1
01411   * @param  DMAx DMAx Instance
01412   * @retval State of bit (1 or 0).
01413   */
01414 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
01415 {
01416   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
01417 }
01418
01419 /**
01420   * @brief  Get Channel 2 transfer error flag.
01421   * @rmtoll ISR          TEIF2         LL_DMA_IsActiveFlag_TE2
01422   * @param  DMAx DMAx Instance
01423   * @retval State of bit (1 or 0).
01424   */
01425 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
01426 {
01427   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
01428 }
01429
01430 /**
01431   * @brief  Get Channel 3 transfer error flag.
01432   * @rmtoll ISR          TEIF3         LL_DMA_IsActiveFlag_TE3
01433   * @param  DMAx DMAx Instance
01434   * @retval State of bit (1 or 0).
01435   */
01436 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
01437 {
01438   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
01439 }
01440
01441 /**
01442   * @brief  Get Channel 4 transfer error flag.
01443   * @rmtoll ISR          TEIF4         LL_DMA_IsActiveFlag_TE4
01444   * @param  DMAx DMAx Instance
01445   * @retval State of bit (1 or 0).
01446   */
01447 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
01448 {
01449   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
01450 }
01451
01452 /**
01453   * @brief  Get Channel 5 transfer error flag.
01454   * @rmtoll ISR          TEIF5         LL_DMA_IsActiveFlag_TE5
01455   * @param  DMAx DMAx Instance
01456   * @retval State of bit (1 or 0).
01457   */
01458 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
01459 {
01460   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
01461 }
01462
01463 /**
01464   * @brief  Get Channel 6 transfer error flag.
01465   * @rmtoll ISR          TEIF6         LL_DMA_IsActiveFlag_TE6
01466   * @param  DMAx DMAx Instance
01467   * @retval State of bit (1 or 0).
01468   */
01469 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
01470 {
01471   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
01472 }
01473
01474 /**
01475   * @brief  Get Channel 7 transfer error flag.
01476   * @rmtoll ISR          TEIF7         LL_DMA_IsActiveFlag_TE7
01477   * @param  DMAx DMAx Instance
01478   * @retval State of bit (1 or 0).
01479   */
01480 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
01481 {
01482   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
01483 }
01484
01485 /**
01486   * @brief  Clear Channel 1 global interrupt flag.
01487   * @rmtoll IFCR         CGIF1         LL_DMA_ClearFlag_GI1
01488   * @param  DMAx DMAx Instance
01489   * @retval None
01490   */
01491 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
01492 {
01493   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
01494 }
01495
01496 /**
01497   * @brief  Clear Channel 2 global interrupt flag.
01498   * @rmtoll IFCR         CGIF2         LL_DMA_ClearFlag_GI2
01499   * @param  DMAx DMAx Instance
01500   * @retval None
01501   */
01502 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
01503 {
01504   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
01505 }
01506
01507 /**
01508   * @brief  Clear Channel 3 global interrupt flag.
01509   * @rmtoll IFCR         CGIF3         LL_DMA_ClearFlag_GI3
01510   * @param  DMAx DMAx Instance
01511   * @retval None
01512   */
01513 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
01514 {
01515   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
01516 }
01517
01518 /**
01519   * @brief  Clear Channel 4 global interrupt flag.
01520   * @rmtoll IFCR         CGIF4         LL_DMA_ClearFlag_GI4
01521   * @param  DMAx DMAx Instance
01522   * @retval None
01523   */
01524 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
01525 {
01526   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
01527 }
01528
01529 /**
01530   * @brief  Clear Channel 5 global interrupt flag.
01531   * @rmtoll IFCR         CGIF5         LL_DMA_ClearFlag_GI5
01532   * @param  DMAx DMAx Instance
01533   * @retval None
01534   */
01535 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
01536 {
01537   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
01538 }
01539
01540 /**
01541   * @brief  Clear Channel 6 global interrupt flag.
01542   * @rmtoll IFCR         CGIF6         LL_DMA_ClearFlag_GI6
01543   * @param  DMAx DMAx Instance
01544   * @retval None
01545   */
01546 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
01547 {
01548   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
01549 }
01550
01551 /**
01552   * @brief  Clear Channel 7 global interrupt flag.
01553   * @rmtoll IFCR         CGIF7         LL_DMA_ClearFlag_GI7
01554   * @param  DMAx DMAx Instance
01555   * @retval None
01556   */
01557 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
01558 {
01559   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
01560 }
01561
01562 /**
01563   * @brief  Clear Channel 1  transfer complete flag.
01564   * @rmtoll IFCR         CTCIF1        LL_DMA_ClearFlag_TC1
01565   * @param  DMAx DMAx Instance
01566   * @retval None
01567   */
01568 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
01569 {
01570   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
01571 }
01572
01573 /**
01574   * @brief  Clear Channel 2  transfer complete flag.
01575   * @rmtoll IFCR         CTCIF2        LL_DMA_ClearFlag_TC2
01576   * @param  DMAx DMAx Instance
01577   * @retval None
01578   */
01579 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
01580 {
01581   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
01582 }
01583
01584 /**
01585   * @brief  Clear Channel 3  transfer complete flag.
01586   * @rmtoll IFCR         CTCIF3        LL_DMA_ClearFlag_TC3
01587   * @param  DMAx DMAx Instance
01588   * @retval None
01589   */
01590 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
01591 {
01592   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
01593 }
01594
01595 /**
01596   * @brief  Clear Channel 4  transfer complete flag.
01597   * @rmtoll IFCR         CTCIF4        LL_DMA_ClearFlag_TC4
01598   * @param  DMAx DMAx Instance
01599   * @retval None
01600   */
01601 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
01602 {
01603   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
01604 }
01605
01606 /**
01607   * @brief  Clear Channel 5  transfer complete flag.
01608   * @rmtoll IFCR         CTCIF5        LL_DMA_ClearFlag_TC5
01609   * @param  DMAx DMAx Instance
01610   * @retval None
01611   */
01612 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
01613 {
01614   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
01615 }
01616
01617 /**
01618   * @brief  Clear Channel 6  transfer complete flag.
01619   * @rmtoll IFCR         CTCIF6        LL_DMA_ClearFlag_TC6
01620   * @param  DMAx DMAx Instance
01621   * @retval None
01622   */
01623 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
01624 {
01625   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
01626 }
01627
01628 /**
01629   * @brief  Clear Channel 7  transfer complete flag.
01630   * @rmtoll IFCR         CTCIF7        LL_DMA_ClearFlag_TC7
01631   * @param  DMAx DMAx Instance
01632   * @retval None
01633   */
01634 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
01635 {
01636   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
01637 }
01638
01639 /**
01640   * @brief  Clear Channel 1  half transfer flag.
01641   * @rmtoll IFCR         CHTIF1        LL_DMA_ClearFlag_HT1
01642   * @param  DMAx DMAx Instance
01643   * @retval None
01644   */
01645 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
01646 {
01647   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
01648 }
01649
01650 /**
01651   * @brief  Clear Channel 2  half transfer flag.
01652   * @rmtoll IFCR         CHTIF2        LL_DMA_ClearFlag_HT2
01653   * @param  DMAx DMAx Instance
01654   * @retval None
01655   */
01656 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
01657 {
01658   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
01659 }
01660
01661 /**
01662   * @brief  Clear Channel 3  half transfer flag.
01663   * @rmtoll IFCR         CHTIF3        LL_DMA_ClearFlag_HT3
01664   * @param  DMAx DMAx Instance
01665   * @retval None
01666   */
01667 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
01668 {
01669   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
01670 }
01671
01672 /**
01673   * @brief  Clear Channel 4  half transfer flag.
01674   * @rmtoll IFCR         CHTIF4        LL_DMA_ClearFlag_HT4
01675   * @param  DMAx DMAx Instance
01676   * @retval None
01677   */
01678 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
01679 {
01680   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
01681 }
01682
01683 /**
01684   * @brief  Clear Channel 5  half transfer flag.
01685   * @rmtoll IFCR         CHTIF5        LL_DMA_ClearFlag_HT5
01686   * @param  DMAx DMAx Instance
01687   * @retval None
01688   */
01689 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
01690 {
01691   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
01692 }
01693
01694 /**
01695   * @brief  Clear Channel 6  half transfer flag.
01696   * @rmtoll IFCR         CHTIF6        LL_DMA_ClearFlag_HT6
01697   * @param  DMAx DMAx Instance
01698   * @retval None
01699   */
01700 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
01701 {
01702   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
01703 }
01704
01705 /**
01706   * @brief  Clear Channel 7  half transfer flag.
01707   * @rmtoll IFCR         CHTIF7        LL_DMA_ClearFlag_HT7
01708   * @param  DMAx DMAx Instance
01709   * @retval None
01710   */
01711 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
01712 {
01713   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
01714 }
01715
01716 /**
01717   * @brief  Clear Channel 1 transfer error flag.
01718   * @rmtoll IFCR         CTEIF1        LL_DMA_ClearFlag_TE1
01719   * @param  DMAx DMAx Instance
01720   * @retval None
01721   */
01722 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
01723 {
01724   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
01725 }
01726
01727 /**
01728   * @brief  Clear Channel 2 transfer error flag.
01729   * @rmtoll IFCR         CTEIF2        LL_DMA_ClearFlag_TE2
01730   * @param  DMAx DMAx Instance
01731   * @retval None
01732   */
01733 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
01734 {
01735   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
01736 }
01737
01738 /**
01739   * @brief  Clear Channel 3 transfer error flag.
01740   * @rmtoll IFCR         CTEIF3        LL_DMA_ClearFlag_TE3
01741   * @param  DMAx DMAx Instance
01742   * @retval None
01743   */
01744 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
01745 {
01746   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
01747 }
01748
01749 /**
01750   * @brief  Clear Channel 4 transfer error flag.
01751   * @rmtoll IFCR         CTEIF4        LL_DMA_ClearFlag_TE4
01752   * @param  DMAx DMAx Instance
01753   * @retval None
01754   */
01755 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
01756 {
01757   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
01758 }
01759
01760 /**
01761   * @brief  Clear Channel 5 transfer error flag.
01762   * @rmtoll IFCR         CTEIF5        LL_DMA_ClearFlag_TE5
01763   * @param  DMAx DMAx Instance
01764   * @retval None
01765   */
01766 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
01767 {
01768   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
01769 }
01770
01771 /**
01772   * @brief  Clear Channel 6 transfer error flag.
01773   * @rmtoll IFCR         CTEIF6        LL_DMA_ClearFlag_TE6
01774   * @param  DMAx DMAx Instance
01775   * @retval None
01776   */
01777 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
01778 {
01779   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
01780 }
01781
01782 /**
01783   * @brief  Clear Channel 7 transfer error flag.
01784   * @rmtoll IFCR         CTEIF7        LL_DMA_ClearFlag_TE7
01785   * @param  DMAx DMAx Instance
01786   * @retval None
01787   */
01788 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
01789 {
01790   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
01791 }
01792
01793 /**
01794   * @}
01795   */
01796
01797 /** @defgroup DMA_LL_EF_IT_Management IT_Management
01798   * @{
01799   */
01800 /**
01801   * @brief  Enable Transfer complete interrupt.
01802   * @rmtoll CCR          TCIE          LL_DMA_EnableIT_TC
01803   * @param  DMAx DMAx Instance
01804   * @param  Channel This parameter can be one of the following values:
01805   *         @arg @ref LL_DMA_CHANNEL_1
01806   *         @arg @ref LL_DMA_CHANNEL_2
01807   *         @arg @ref LL_DMA_CHANNEL_3
01808   *         @arg @ref LL_DMA_CHANNEL_4
01809   *         @arg @ref LL_DMA_CHANNEL_5
01810   *         @arg @ref LL_DMA_CHANNEL_6
01811   *         @arg @ref LL_DMA_CHANNEL_7
01812   * @retval None
01813   */
01814 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
01815 {
01816   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
01817 }
01818
01819 /**
01820   * @brief  Enable Half transfer interrupt.
01821   * @rmtoll CCR          HTIE          LL_DMA_EnableIT_HT
01822   * @param  DMAx DMAx Instance
01823   * @param  Channel This parameter can be one of the following values:
01824   *         @arg @ref LL_DMA_CHANNEL_1
01825   *         @arg @ref LL_DMA_CHANNEL_2
01826   *         @arg @ref LL_DMA_CHANNEL_3
01827   *         @arg @ref LL_DMA_CHANNEL_4
01828   *         @arg @ref LL_DMA_CHANNEL_5
01829   *         @arg @ref LL_DMA_CHANNEL_6
01830   *         @arg @ref LL_DMA_CHANNEL_7
01831   * @retval None
01832   */
01833 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
01834 {
01835   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
01836 }
01837
01838 /**
01839   * @brief  Enable Transfer error interrupt.
01840   * @rmtoll CCR          TEIE          LL_DMA_EnableIT_TE
01841   * @param  DMAx DMAx Instance
01842   * @param  Channel This parameter can be one of the following values:
01843   *         @arg @ref LL_DMA_CHANNEL_1
01844   *         @arg @ref LL_DMA_CHANNEL_2
01845   *         @arg @ref LL_DMA_CHANNEL_3
01846   *         @arg @ref LL_DMA_CHANNEL_4
01847   *         @arg @ref LL_DMA_CHANNEL_5
01848   *         @arg @ref LL_DMA_CHANNEL_6
01849   *         @arg @ref LL_DMA_CHANNEL_7
01850   * @retval None
01851   */
01852 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
01853 {
01854   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
01855 }
01856
01857 /**
01858   * @brief  Disable Transfer complete interrupt.
01859   * @rmtoll CCR          TCIE          LL_DMA_DisableIT_TC
01860   * @param  DMAx DMAx Instance
01861   * @param  Channel This parameter can be one of the following values:
01862   *         @arg @ref LL_DMA_CHANNEL_1
01863   *         @arg @ref LL_DMA_CHANNEL_2
01864   *         @arg @ref LL_DMA_CHANNEL_3
01865   *         @arg @ref LL_DMA_CHANNEL_4
01866   *         @arg @ref LL_DMA_CHANNEL_5
01867   *         @arg @ref LL_DMA_CHANNEL_6
01868   *         @arg @ref LL_DMA_CHANNEL_7
01869   * @retval None
01870   */
01871 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
01872 {
01873   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
01874 }
01875
01876 /**
01877   * @brief  Disable Half transfer interrupt.
01878   * @rmtoll CCR          HTIE          LL_DMA_DisableIT_HT
01879   * @param  DMAx DMAx Instance
01880   * @param  Channel This parameter can be one of the following values:
01881   *         @arg @ref LL_DMA_CHANNEL_1
01882   *         @arg @ref LL_DMA_CHANNEL_2
01883   *         @arg @ref LL_DMA_CHANNEL_3
01884   *         @arg @ref LL_DMA_CHANNEL_4
01885   *         @arg @ref LL_DMA_CHANNEL_5
01886   *         @arg @ref LL_DMA_CHANNEL_6
01887   *         @arg @ref LL_DMA_CHANNEL_7
01888   * @retval None
01889   */
01890 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
01891 {
01892   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
01893 }
01894
01895 /**
01896   * @brief  Disable Transfer error interrupt.
01897   * @rmtoll CCR          TEIE          LL_DMA_DisableIT_TE
01898   * @param  DMAx DMAx Instance
01899   * @param  Channel This parameter can be one of the following values:
01900   *         @arg @ref LL_DMA_CHANNEL_1
01901   *         @arg @ref LL_DMA_CHANNEL_2
01902   *         @arg @ref LL_DMA_CHANNEL_3
01903   *         @arg @ref LL_DMA_CHANNEL_4
01904   *         @arg @ref LL_DMA_CHANNEL_5
01905   *         @arg @ref LL_DMA_CHANNEL_6
01906   *         @arg @ref LL_DMA_CHANNEL_7
01907   * @retval None
01908   */
01909 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
01910 {
01911   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
01912 }
01913
01914 /**
01915   * @brief  Check if Transfer complete Interrupt is enabled.
01916   * @rmtoll CCR          TCIE          LL_DMA_IsEnabledIT_TC
01917   * @param  DMAx DMAx Instance
01918   * @param  Channel This parameter can be one of the following values:
01919   *         @arg @ref LL_DMA_CHANNEL_1
01920   *         @arg @ref LL_DMA_CHANNEL_2
01921   *         @arg @ref LL_DMA_CHANNEL_3
01922   *         @arg @ref LL_DMA_CHANNEL_4
01923   *         @arg @ref LL_DMA_CHANNEL_5
01924   *         @arg @ref LL_DMA_CHANNEL_6
01925   *         @arg @ref LL_DMA_CHANNEL_7
01926   * @retval State of bit (1 or 0).
01927   */
01928 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
01929 {
01930   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
01931                    DMA_CCR_TCIE) == (DMA_CCR_TCIE));
01932 }
01933
01934 /**
01935   * @brief  Check if Half transfer Interrupt is enabled.
01936   * @rmtoll CCR          HTIE          LL_DMA_IsEnabledIT_HT
01937   * @param  DMAx DMAx Instance
01938   * @param  Channel This parameter can be one of the following values:
01939   *         @arg @ref LL_DMA_CHANNEL_1
01940   *         @arg @ref LL_DMA_CHANNEL_2
01941   *         @arg @ref LL_DMA_CHANNEL_3
01942   *         @arg @ref LL_DMA_CHANNEL_4
01943   *         @arg @ref LL_DMA_CHANNEL_5
01944   *         @arg @ref LL_DMA_CHANNEL_6
01945   *         @arg @ref LL_DMA_CHANNEL_7
01946   * @retval State of bit (1 or 0).
01947   */
01948 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
01949 {
01950   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
01951                    DMA_CCR_HTIE) == (DMA_CCR_HTIE));
01952 }
01953
01954 /**
01955   * @brief  Check if Transfer error Interrupt is enabled.
01956   * @rmtoll CCR          TEIE          LL_DMA_IsEnabledIT_TE
01957   * @param  DMAx DMAx Instance
01958   * @param  Channel This parameter can be one of the following values:
01959   *         @arg @ref LL_DMA_CHANNEL_1
01960   *         @arg @ref LL_DMA_CHANNEL_2
01961   *         @arg @ref LL_DMA_CHANNEL_3
01962   *         @arg @ref LL_DMA_CHANNEL_4
01963   *         @arg @ref LL_DMA_CHANNEL_5
01964   *         @arg @ref LL_DMA_CHANNEL_6
01965   *         @arg @ref LL_DMA_CHANNEL_7
01966   * @retval State of bit (1 or 0).
01967   */
01968 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
01969 {
01970   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
01971                    DMA_CCR_TEIE) == (DMA_CCR_TEIE));
01972 }
01973
01974 /**
01975   * @}
01976   */
01977
01978 #if defined(USE_FULL_LL_DRIVER)
01979 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
01980   * @{
01981   */
01982
01983 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
01984 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
01985 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
01986
01987 /**
01988   * @}
01989   */
01990 #endif /* USE_FULL_LL_DRIVER */
01991
01992 /**
01993   * @}
01994   */
01995
01996 /**
01997   * @}
01998   */
01999
02000 #endif /* DMA1 || DMA2 */
02001
02002 /**
02003   * @}
02004   */
02005
02006 #ifdef __cplusplus
02007 }
02008 #endif
02009
02010 #endif /* __STM32F3xx_LL_DMA_H */
02011
02012 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_exti.c Source File

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stm32f3xx_ll_exti.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_exti.c
00004   * @author  MCD Application Team
00005   * @brief   EXTI LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 #if defined(USE_FULL_LL_DRIVER)
00036
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f3xx_ll_exti.h"
00039 #ifdef  USE_FULL_ASSERT
00040 #include "stm32_assert.h"
00041 #else
00042 #define assert_param(expr) ((void)0U)
00043 #endif
00044
00045 /** @addtogroup STM32F3xx_LL_Driver
00046   * @{
00047   */
00048
00049 #if defined (EXTI)
00050
00051 /** @defgroup EXTI_LL EXTI
00052   * @{
00053   */
00054
00055 /* Private types -------------------------------------------------------------*/
00056 /* Private variables ---------------------------------------------------------*/
00057 /* Private constants ---------------------------------------------------------*/
00058 /* Private macros ------------------------------------------------------------*/
00059 /** @addtogroup EXTI_LL_Private_Macros
00060   * @{
00061   */
00062
00063 #define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
00064 #if defined(EXTI_32_63_SUPPORT)
00065 #define IS_LL_EXTI_LINE_32_63(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
00066 #endif
00067
00068 #define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
00069                                                    || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
00070                                                    || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
00071
00072
00073 #define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
00074                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
00075                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
00076                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
00077
00078 /**
00079   * @}
00080   */
00081
00082 /* Private function prototypes -----------------------------------------------*/
00083
00084 /* Exported functions --------------------------------------------------------*/
00085 /** @addtogroup EXTI_LL_Exported_Functions
00086   * @{
00087   */
00088
00089 /** @addtogroup EXTI_LL_EF_Init
00090   * @{
00091   */
00092
00093 /**
00094   * @brief  De-initialize the EXTI registers to their default reset values.
00095   * @retval An ErrorStatus enumeration value:
00096   *          - SUCCESS: EXTI registers are de-initialized
00097   *          - ERROR: not applicable
00098   */
00099 uint32_t LL_EXTI_DeInit(void)
00100 {
00101   /* Interrupt mask register set to default reset values */
00102   LL_EXTI_WriteReg(IMR,   0x1F800000U);
00103   /* Event mask register set to default reset values */
00104   LL_EXTI_WriteReg(EMR,   0x00000000U);
00105   /* Rising Trigger selection register set to default reset values */
00106   LL_EXTI_WriteReg(RTSR,  0x00000000U);
00107   /* Falling Trigger selection register set to default reset values */
00108   LL_EXTI_WriteReg(FTSR,  0x00000000U);
00109   /* Software interrupt event register set to default reset values */
00110   LL_EXTI_WriteReg(SWIER, 0x00000000U);
00111   /* Pending register clear */
00112   LL_EXTI_WriteReg(PR,    0x007FFFFFU);
00113
00114 #if defined(EXTI_32_63_SUPPORT)
00115   /* Interrupt mask register 2 set to default reset values */
00116 #if defined(STM32F334x8)
00117   LL_EXTI_WriteReg(IMR2,        0xFFFFFFFEU);
00118 #else
00119   LL_EXTI_WriteReg(IMR2,        0xFFFFFFFCU);
00120 #endif
00121   /* Event mask register 2 set to default reset values */
00122   LL_EXTI_WriteReg(EMR2,        0x00000000U);
00123   /* Rising Trigger selection register 2 set to default reset values */
00124   LL_EXTI_WriteReg(RTSR2,       0x00000000U);
00125   /* Falling Trigger selection register 2 set to default reset values */
00126   LL_EXTI_WriteReg(FTSR2,       0x00000000U);
00127   /* Software interrupt event register 2 set to default reset values */
00128   LL_EXTI_WriteReg(SWIER2,      0x00000000U);
00129   /* Pending register 2 clear */
00130   LL_EXTI_WriteReg(PR2,         0x00000003U);
00131
00132 #endif
00133   return SUCCESS;
00134 }
00135
00136 /**
00137   * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
00138   * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
00139   * @retval An ErrorStatus enumeration value:
00140   *          - SUCCESS: EXTI registers are initialized
00141   *          - ERROR: not applicable
00142   */
00143 uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
00144 {
00145   ErrorStatus status = SUCCESS;
00146   /* Check the parameters */
00147   assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
00148 #if defined(EXTI_32_63_SUPPORT)
00149   assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
00150 #endif
00151   assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
00152   assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
00153
00154   /* ENABLE LineCommand */
00155   if (EXTI_InitStruct->LineCommand != DISABLE)
00156   {
00157     assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
00158
00159     /* Configure EXTI Lines in range from 0 to 31 */
00160     if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
00161     {
00162       switch (EXTI_InitStruct->Mode)
00163       {
00164         case LL_EXTI_MODE_IT:
00165           /* First Disable Event on provided Lines */
00166           LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
00167           /* Then Enable IT on provided Lines */
00168           LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
00169           break;
00170         case LL_EXTI_MODE_EVENT:
00171           /* First Disable IT on provided Lines */
00172           LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
00173           /* Then Enable Event on provided Lines */
00174           LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
00175           break;
00176         case LL_EXTI_MODE_IT_EVENT:
00177           /* Directly Enable IT & Event on provided Lines */
00178           LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
00179           LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
00180           break;
00181         default:
00182           status = ERROR;
00183           break;
00184       }
00185       if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
00186       {
00187         switch (EXTI_InitStruct->Trigger)
00188         {
00189           case LL_EXTI_TRIGGER_RISING:
00190             /* First Disable Falling Trigger on provided Lines */
00191             LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00192             /* Then Enable Rising Trigger on provided Lines */
00193             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00194             break;
00195           case LL_EXTI_TRIGGER_FALLING:
00196             /* First Disable Rising Trigger on provided Lines */
00197             LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00198             /* Then Enable Falling Trigger on provided Lines */
00199             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00200             break;
00201           case LL_EXTI_TRIGGER_RISING_FALLING:
00202             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00203             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00204             break;
00205           default:
00206             status = ERROR;
00207             break;
00208         }
00209       }
00210     }
00211 #if defined(EXTI_32_63_SUPPORT)
00212     /* Configure EXTI Lines in range from 32 to 63 */
00213     if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
00214     {
00215       switch (EXTI_InitStruct->Mode)
00216       {
00217         case LL_EXTI_MODE_IT:
00218           /* First Disable Event on provided Lines */
00219           LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
00220           /* Then Enable IT on provided Lines */
00221           LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
00222           break;
00223         case LL_EXTI_MODE_EVENT:
00224           /* First Disable IT on provided Lines */
00225           LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
00226           /* Then Enable Event on provided Lines */
00227           LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
00228           break;
00229         case LL_EXTI_MODE_IT_EVENT:
00230           /* Directly Enable IT & Event on provided Lines */
00231           LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
00232           LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
00233           break;
00234         default:
00235           status = ERROR;
00236           break;
00237       }
00238       if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
00239       {
00240         switch (EXTI_InitStruct->Trigger)
00241         {
00242           case LL_EXTI_TRIGGER_RISING:
00243             /* First Disable Falling Trigger on provided Lines */
00244             LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
00245             /* Then Enable IT on provided Lines */
00246             LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
00247             break;
00248           case LL_EXTI_TRIGGER_FALLING:
00249             /* First Disable Rising Trigger on provided Lines */
00250             LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
00251             /* Then Enable Falling Trigger on provided Lines */
00252             LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
00253             break;
00254           case LL_EXTI_TRIGGER_RISING_FALLING:
00255             LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
00256             LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
00257             break;
00258           default:
00259             status = ERROR;
00260             break;
00261         }
00262       }
00263     }
00264 #endif
00265   }
00266   /* DISABLE LineCommand */
00267   else
00268   {
00269     /* De-configure EXTI Lines in range from 0 to 31 */
00270     LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
00271     LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
00272 #if defined(EXTI_32_63_SUPPORT)
00273     /* De-configure EXTI Lines in range from 32 to 63 */
00274     LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
00275     LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
00276 #endif
00277   }
00278   return status;
00279 }
00280
00281 /**
00282   * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
00283   * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
00284   * @retval None
00285   */
00286 void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
00287 {
00288   EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
00289 #if defined(EXTI_32_63_SUPPORT)
00290   EXTI_InitStruct->Line_32_63     = LL_EXTI_LINE_NONE;
00291 #endif
00292   EXTI_InitStruct->LineCommand    = DISABLE;
00293   EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
00294   EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
00295 }
00296
00297 /**
00298   * @}
00299   */
00300
00301 /**
00302   * @}
00303   */
00304
00305 /**
00306   * @}
00307   */
00308
00309 #endif /* defined (EXTI) */
00310
00311 /**
00312   * @}
00313   */
00314
00315 #endif /* USE_FULL_LL_DRIVER */
00316
00317 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_exti.h Source File

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stm32f3xx_ll_exti.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_exti.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of EXTI LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_EXTI_H
00038 #define __STM32F3xx_LL_EXTI_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined (EXTI)
00052
00053 /** @defgroup EXTI_LL EXTI
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059 /* Private constants ---------------------------------------------------------*/
00060 /* Private Macros ------------------------------------------------------------*/
00061 #if defined(USE_FULL_LL_DRIVER)
00062 /** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
00063   * @{
00064   */
00065 /**
00066   * @}
00067   */
00068 #endif /*USE_FULL_LL_DRIVER*/
00069 /* Exported types ------------------------------------------------------------*/
00070 #if defined(USE_FULL_LL_DRIVER)
00071 /** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
00072   * @{
00073   */
00074 typedef struct
00075 {
00076
00077   uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
00078                                      This parameter can be any combination of @ref EXTI_LL_EC_LINE */
00079 #if defined(EXTI_32_63_SUPPORT)
00080
00081   uint32_t Line_32_63;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
00082                                      This parameter can be any combination of @ref EXTI_LL_EC_LINE */
00083 #endif
00084
00085   FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
00086                                      This parameter can be set either to ENABLE or DISABLE */
00087
00088   uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
00089                                      This parameter can be a value of @ref EXTI_LL_EC_MODE. */
00090
00091   uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
00092                                      This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
00093 } LL_EXTI_InitTypeDef;
00094
00095 /**
00096   * @}
00097   */
00098 #endif /*USE_FULL_LL_DRIVER*/
00099
00100 /* Exported constants --------------------------------------------------------*/
00101 /** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
00102   * @{
00103   */
00104
00105 /** @defgroup EXTI_LL_EC_LINE LINE
00106   * @{
00107   */
00108 #define LL_EXTI_LINE_0                 EXTI_IMR_IM0           /*!< Extended line 0 */
00109 #define LL_EXTI_LINE_1                 EXTI_IMR_IM1           /*!< Extended line 1 */
00110 #define LL_EXTI_LINE_2                 EXTI_IMR_IM2           /*!< Extended line 2 */
00111 #define LL_EXTI_LINE_3                 EXTI_IMR_IM3           /*!< Extended line 3 */
00112 #define LL_EXTI_LINE_4                 EXTI_IMR_IM4           /*!< Extended line 4 */
00113 #define LL_EXTI_LINE_5                 EXTI_IMR_IM5           /*!< Extended line 5 */
00114 #define LL_EXTI_LINE_6                 EXTI_IMR_IM6           /*!< Extended line 6 */
00115 #define LL_EXTI_LINE_7                 EXTI_IMR_IM7           /*!< Extended line 7 */
00116 #define LL_EXTI_LINE_8                 EXTI_IMR_IM8           /*!< Extended line 8 */
00117 #define LL_EXTI_LINE_9                 EXTI_IMR_IM9           /*!< Extended line 9 */
00118 #define LL_EXTI_LINE_10                EXTI_IMR_IM10          /*!< Extended line 10 */
00119 #define LL_EXTI_LINE_11                EXTI_IMR_IM11          /*!< Extended line 11 */
00120 #define LL_EXTI_LINE_12                EXTI_IMR_IM12          /*!< Extended line 12 */
00121 #define LL_EXTI_LINE_13                EXTI_IMR_IM13          /*!< Extended line 13 */
00122 #define LL_EXTI_LINE_14                EXTI_IMR_IM14          /*!< Extended line 14 */
00123 #define LL_EXTI_LINE_15                EXTI_IMR_IM15          /*!< Extended line 15 */
00124 #if defined(EXTI_IMR_IM16)
00125 #define LL_EXTI_LINE_16                EXTI_IMR_IM16          /*!< Extended line 16 */
00126 #endif
00127 #define LL_EXTI_LINE_17                EXTI_IMR_IM17          /*!< Extended line 17 */
00128 #if defined(EXTI_IMR_IM18)
00129 #define LL_EXTI_LINE_18                EXTI_IMR_IM18          /*!< Extended line 18 */
00130 #endif
00131 #define LL_EXTI_LINE_19                EXTI_IMR_IM19          /*!< Extended line 19 */
00132 #if defined(EXTI_IMR_IM20)
00133 #define LL_EXTI_LINE_20                EXTI_IMR_IM20          /*!< Extended line 20 */
00134 #endif
00135 #if defined(EXTI_IMR_IM21)
00136 #define LL_EXTI_LINE_21                EXTI_IMR_IM21          /*!< Extended line 21 */
00137 #endif
00138 #if defined(EXTI_IMR_IM22)
00139 #define LL_EXTI_LINE_22                EXTI_IMR_IM22          /*!< Extended line 22 */
00140 #endif
00141 #define LL_EXTI_LINE_23                EXTI_IMR_IM23          /*!< Extended line 23 */
00142 #if defined(EXTI_IMR_IM24)
00143 #define LL_EXTI_LINE_24                EXTI_IMR_IM24          /*!< Extended line 24 */
00144 #endif
00145 #if defined(EXTI_IMR_IM25)
00146 #define LL_EXTI_LINE_25                EXTI_IMR_IM25          /*!< Extended line 25 */
00147 #endif
00148 #if defined(EXTI_IMR_IM26)
00149 #define LL_EXTI_LINE_26                EXTI_IMR_IM26          /*!< Extended line 26 */
00150 #endif
00151 #if defined(EXTI_IMR_IM27)
00152 #define LL_EXTI_LINE_27                EXTI_IMR_IM27          /*!< Extended line 27 */
00153 #endif
00154 #if defined(EXTI_IMR_IM28)
00155 #define LL_EXTI_LINE_28                EXTI_IMR_IM28          /*!< Extended line 28 */
00156 #endif
00157 #if defined(EXTI_IMR_IM29)
00158 #define LL_EXTI_LINE_29                EXTI_IMR_IM29          /*!< Extended line 29 */
00159 #endif
00160 #if defined(EXTI_IMR_IM30)
00161 #define LL_EXTI_LINE_30                EXTI_IMR_IM30          /*!< Extended line 30 */
00162 #endif
00163 #if defined(EXTI_IMR_IM31)
00164 #define LL_EXTI_LINE_31                EXTI_IMR_IM31          /*!< Extended line 31 */
00165 #endif
00166 #define LL_EXTI_LINE_ALL_0_31          EXTI_IMR_IM            /*!< All Extended line not reserved*/
00167
00168 #if defined(EXTI_32_63_SUPPORT)
00169 #define LL_EXTI_LINE_32                EXTI_IMR2_IM32          /*!< Extended line 32 */
00170 #if defined(EXTI_IMR2_IM33)
00171 #define LL_EXTI_LINE_33                EXTI_IMR2_IM33          /*!< Extended line 33 */
00172 #endif
00173 #if defined(EXTI_IMR2_IM34)
00174 #define LL_EXTI_LINE_34                EXTI_IMR2_IM34          /*!< Extended line 34 */
00175 #endif
00176 #if defined(EXTI_IMR2_IM35)
00177 #define LL_EXTI_LINE_35                EXTI_IMR2_IM35          /*!< Extended line 35 */
00178 #endif
00179 #if defined(EXTI_IMR2_IM36)
00180 #define LL_EXTI_LINE_36                EXTI_IMR2_IM36          /*!< Extended line 36 */
00181 #endif
00182 #if defined(EXTI_IMR2_IM37)
00183 #define LL_EXTI_LINE_37                EXTI_IMR2_IM37          /*!< Extended line 37 */
00184 #endif
00185 #if defined(EXTI_IMR2_IM38)
00186 #define LL_EXTI_LINE_38                EXTI_IMR2_IM38          /*!< Extended line 38 */
00187 #endif
00188 #if defined(EXTI_IMR2_IM39)
00189 #define LL_EXTI_LINE_39                EXTI_IMR2_IM39          /*!< Extended line 39 */
00190 #endif
00191 #if defined(EXTI_IMR2_IM40)
00192 #define LL_EXTI_LINE_40                EXTI_IMR2_IM40          /*!< Extended line 40 */
00193 #endif
00194 #define LL_EXTI_LINE_ALL_32_63         EXTI_IMR2_IM            /*!< All Extended line not reserved*/
00195
00196 #endif
00197
00198 #define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */
00199
00200 #if defined(USE_FULL_LL_DRIVER)
00201 #define LL_EXTI_LINE_NONE              (0x00000000U)  /*!< None Extended line */
00202 #endif /*USE_FULL_LL_DRIVER*/
00203
00204 /**
00205   * @}
00206   */
00207 #if defined(USE_FULL_LL_DRIVER)
00208
00209 /** @defgroup EXTI_LL_EC_MODE Mode
00210   * @{
00211   */
00212 #define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */
00213 #define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */
00214 #define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
00220   * @{
00221   */
00222 #define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
00223 #define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
00224 #define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
00225 #define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
00226
00227 /**
00228   * @}
00229   */
00230
00231
00232 #endif /*USE_FULL_LL_DRIVER*/
00233
00234
00235 /**
00236   * @}
00237   */
00238
00239 /* Exported macro ------------------------------------------------------------*/
00240 /** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
00241   * @{
00242   */
00243
00244 /** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
00245   * @{
00246   */
00247
00248 /**
00249   * @brief  Write a value in EXTI register
00250   * @param  __REG__ Register to be written
00251   * @param  __VALUE__ Value to be written in the register
00252   * @retval None
00253   */
00254 #define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
00255
00256 /**
00257   * @brief  Read a value in EXTI register
00258   * @param  __REG__ Register to be read
00259   * @retval Register value
00260   */
00261 #define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
00262 /**
00263   * @}
00264   */
00265
00266
00267 /**
00268   * @}
00269   */
00270
00271
00272
00273 /* Exported functions --------------------------------------------------------*/
00274 /** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
00275  * @{
00276  */
00277 /** @defgroup EXTI_LL_EF_IT_Management IT_Management
00278   * @{
00279   */
00280
00281 /**
00282   * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
00283   * @note The reset value for the direct or internal lines (see RM)
00284   *       is set to 1 in order to enable the interrupt by default.
00285   *       Bits are set automatically at Power on.
00286   * @rmtoll IMR         IMx           LL_EXTI_EnableIT_0_31
00287   * @param  ExtiLine This parameter can be one of the following values:
00288   *         @arg @ref LL_EXTI_LINE_0
00289   *         @arg @ref LL_EXTI_LINE_1
00290   *         @arg @ref LL_EXTI_LINE_2
00291   *         @arg @ref LL_EXTI_LINE_3
00292   *         @arg @ref LL_EXTI_LINE_4
00293   *         @arg @ref LL_EXTI_LINE_5
00294   *         @arg @ref LL_EXTI_LINE_6
00295   *         @arg @ref LL_EXTI_LINE_7
00296   *         @arg @ref LL_EXTI_LINE_8
00297   *         @arg @ref LL_EXTI_LINE_9
00298   *         @arg @ref LL_EXTI_LINE_10
00299   *         @arg @ref LL_EXTI_LINE_11
00300   *         @arg @ref LL_EXTI_LINE_12
00301   *         @arg @ref LL_EXTI_LINE_13
00302   *         @arg @ref LL_EXTI_LINE_14
00303   *         @arg @ref LL_EXTI_LINE_15
00304   *         @arg @ref LL_EXTI_LINE_16
00305   *         @arg @ref LL_EXTI_LINE_17
00306   *         @arg @ref LL_EXTI_LINE_18
00307   *         @arg @ref LL_EXTI_LINE_19
00308   *         @arg @ref LL_EXTI_LINE_20
00309   *         @arg @ref LL_EXTI_LINE_21
00310   *         @arg @ref LL_EXTI_LINE_22
00311   *         @arg @ref LL_EXTI_LINE_23
00312   *         @arg @ref LL_EXTI_LINE_24
00313   *         @arg @ref LL_EXTI_LINE_25
00314   *         @arg @ref LL_EXTI_LINE_26
00315   *         @arg @ref LL_EXTI_LINE_27
00316   *         @arg @ref LL_EXTI_LINE_28
00317   *         @arg @ref LL_EXTI_LINE_29
00318   *         @arg @ref LL_EXTI_LINE_30
00319   *         @arg @ref LL_EXTI_LINE_31
00320   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00321   * @note   Please check each device line mapping for EXTI Line availability
00322   * @retval None
00323   */
00324 __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
00325 {
00326   SET_BIT(EXTI->IMR, ExtiLine);
00327 }
00328 #if defined(EXTI_32_63_SUPPORT)
00329 /**
00330   * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63
00331   * @note The reset value for the direct lines (lines from 32 to 34, line
00332   *       39) is set to 1 in order to enable the interrupt by default.
00333   *       Bits are set automatically at Power on.
00334   * @rmtoll IMR2         IMx           LL_EXTI_EnableIT_32_63
00335   * @param  ExtiLine This parameter can be one of the following values:
00336   *         @arg @ref LL_EXTI_LINE_32
00337   *         @arg @ref LL_EXTI_LINE_33
00338   *         @arg @ref LL_EXTI_LINE_34
00339   *         @arg @ref LL_EXTI_LINE_35
00340   *         @arg @ref LL_EXTI_LINE_36
00341   *         @arg @ref LL_EXTI_LINE_37
00342   *         @arg @ref LL_EXTI_LINE_38
00343   *         @arg @ref LL_EXTI_LINE_39
00344   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00345   * @retval None
00346   */
00347 __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
00348 {
00349   SET_BIT(EXTI->IMR2, ExtiLine);
00350 }
00351 #endif
00352
00353 /**
00354   * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
00355   * @note The reset value for the direct or internal lines (see RM)
00356   *       is set to 1 in order to enable the interrupt by default.
00357   *       Bits are set automatically at Power on.
00358   * @rmtoll IMR         IMx           LL_EXTI_DisableIT_0_31
00359   * @param  ExtiLine This parameter can be one of the following values:
00360   *         @arg @ref LL_EXTI_LINE_0
00361   *         @arg @ref LL_EXTI_LINE_1
00362   *         @arg @ref LL_EXTI_LINE_2
00363   *         @arg @ref LL_EXTI_LINE_3
00364   *         @arg @ref LL_EXTI_LINE_4
00365   *         @arg @ref LL_EXTI_LINE_5
00366   *         @arg @ref LL_EXTI_LINE_6
00367   *         @arg @ref LL_EXTI_LINE_7
00368   *         @arg @ref LL_EXTI_LINE_8
00369   *         @arg @ref LL_EXTI_LINE_9
00370   *         @arg @ref LL_EXTI_LINE_10
00371   *         @arg @ref LL_EXTI_LINE_11
00372   *         @arg @ref LL_EXTI_LINE_12
00373   *         @arg @ref LL_EXTI_LINE_13
00374   *         @arg @ref LL_EXTI_LINE_14
00375   *         @arg @ref LL_EXTI_LINE_15
00376   *         @arg @ref LL_EXTI_LINE_16
00377   *         @arg @ref LL_EXTI_LINE_17
00378   *         @arg @ref LL_EXTI_LINE_18
00379   *         @arg @ref LL_EXTI_LINE_19
00380   *         @arg @ref LL_EXTI_LINE_20
00381   *         @arg @ref LL_EXTI_LINE_21
00382   *         @arg @ref LL_EXTI_LINE_22
00383   *         @arg @ref LL_EXTI_LINE_23
00384   *         @arg @ref LL_EXTI_LINE_24
00385   *         @arg @ref LL_EXTI_LINE_25
00386   *         @arg @ref LL_EXTI_LINE_26
00387   *         @arg @ref LL_EXTI_LINE_27
00388   *         @arg @ref LL_EXTI_LINE_28
00389   *         @arg @ref LL_EXTI_LINE_29
00390   *         @arg @ref LL_EXTI_LINE_30
00391   *         @arg @ref LL_EXTI_LINE_31
00392   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00393   * @note   Please check each device line mapping for EXTI Line availability
00394   * @retval None
00395   */
00396 __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
00397 {
00398   CLEAR_BIT(EXTI->IMR, ExtiLine);
00399 }
00400
00401 #if defined(EXTI_32_63_SUPPORT)
00402 /**
00403   * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63
00404   * @note The reset value for the direct lines (lines from 32 to 34, line
00405   *       39) is set to 1 in order to enable the interrupt by default.
00406   *       Bits are set automatically at Power on.
00407   * @rmtoll IMR2         IMx           LL_EXTI_DisableIT_32_63
00408   * @param  ExtiLine This parameter can be one of the following values:
00409   *         @arg @ref LL_EXTI_LINE_32
00410   *         @arg @ref LL_EXTI_LINE_33
00411   *         @arg @ref LL_EXTI_LINE_34
00412   *         @arg @ref LL_EXTI_LINE_35
00413   *         @arg @ref LL_EXTI_LINE_36
00414   *         @arg @ref LL_EXTI_LINE_37
00415   *         @arg @ref LL_EXTI_LINE_38
00416   *         @arg @ref LL_EXTI_LINE_39
00417   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00418   * @retval None
00419   */
00420 __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
00421 {
00422   CLEAR_BIT(EXTI->IMR2, ExtiLine);
00423 }
00424 #endif
00425
00426 /**
00427   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
00428   * @note The reset value for the direct or internal lines (see RM)
00429   *       is set to 1 in order to enable the interrupt by default.
00430   *       Bits are set automatically at Power on.
00431   * @rmtoll IMR         IMx           LL_EXTI_IsEnabledIT_0_31
00432   * @param  ExtiLine This parameter can be one of the following values:
00433   *         @arg @ref LL_EXTI_LINE_0
00434   *         @arg @ref LL_EXTI_LINE_1
00435   *         @arg @ref LL_EXTI_LINE_2
00436   *         @arg @ref LL_EXTI_LINE_3
00437   *         @arg @ref LL_EXTI_LINE_4
00438   *         @arg @ref LL_EXTI_LINE_5
00439   *         @arg @ref LL_EXTI_LINE_6
00440   *         @arg @ref LL_EXTI_LINE_7
00441   *         @arg @ref LL_EXTI_LINE_8
00442   *         @arg @ref LL_EXTI_LINE_9
00443   *         @arg @ref LL_EXTI_LINE_10
00444   *         @arg @ref LL_EXTI_LINE_11
00445   *         @arg @ref LL_EXTI_LINE_12
00446   *         @arg @ref LL_EXTI_LINE_13
00447   *         @arg @ref LL_EXTI_LINE_14
00448   *         @arg @ref LL_EXTI_LINE_15
00449   *         @arg @ref LL_EXTI_LINE_16
00450   *         @arg @ref LL_EXTI_LINE_17
00451   *         @arg @ref LL_EXTI_LINE_18
00452   *         @arg @ref LL_EXTI_LINE_19
00453   *         @arg @ref LL_EXTI_LINE_20
00454   *         @arg @ref LL_EXTI_LINE_21
00455   *         @arg @ref LL_EXTI_LINE_22
00456   *         @arg @ref LL_EXTI_LINE_23
00457   *         @arg @ref LL_EXTI_LINE_24
00458   *         @arg @ref LL_EXTI_LINE_25
00459   *         @arg @ref LL_EXTI_LINE_26
00460   *         @arg @ref LL_EXTI_LINE_27
00461   *         @arg @ref LL_EXTI_LINE_28
00462   *         @arg @ref LL_EXTI_LINE_29
00463   *         @arg @ref LL_EXTI_LINE_30
00464   *         @arg @ref LL_EXTI_LINE_31
00465   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00466   * @note   Please check each device line mapping for EXTI Line availability
00467   * @retval State of bit (1 or 0).
00468   */
00469 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
00470 {
00471   return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
00472 }
00473
00474 #if defined(EXTI_32_63_SUPPORT)
00475 /**
00476   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
00477   * @note The reset value for the direct lines (lines from 32 to 34, line
00478   *       39) is set to 1 in order to enable the interrupt by default.
00479   *       Bits are set automatically at Power on.
00480   * @rmtoll IMR2         IMx           LL_EXTI_IsEnabledIT_32_63
00481   * @param  ExtiLine This parameter can be one of the following values:
00482   *         @arg @ref LL_EXTI_LINE_32
00483   *         @arg @ref LL_EXTI_LINE_33
00484   *         @arg @ref LL_EXTI_LINE_34
00485   *         @arg @ref LL_EXTI_LINE_35
00486   *         @arg @ref LL_EXTI_LINE_36
00487   *         @arg @ref LL_EXTI_LINE_37
00488   *         @arg @ref LL_EXTI_LINE_38
00489   *         @arg @ref LL_EXTI_LINE_39
00490   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00491   * @retval State of bit (1 or 0).
00492   */
00493 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
00494 {
00495   return (READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine));
00496 }
00497 #endif
00498
00499 /**
00500   * @}
00501   */
00502
00503 /** @defgroup EXTI_LL_EF_Event_Management Event_Management
00504   * @{
00505   */
00506
00507 /**
00508   * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
00509   * @rmtoll EMR         EMx           LL_EXTI_EnableEvent_0_31
00510   * @param  ExtiLine This parameter can be one of the following values:
00511   *         @arg @ref LL_EXTI_LINE_0
00512   *         @arg @ref LL_EXTI_LINE_1
00513   *         @arg @ref LL_EXTI_LINE_2
00514   *         @arg @ref LL_EXTI_LINE_3
00515   *         @arg @ref LL_EXTI_LINE_4
00516   *         @arg @ref LL_EXTI_LINE_5
00517   *         @arg @ref LL_EXTI_LINE_6
00518   *         @arg @ref LL_EXTI_LINE_7
00519   *         @arg @ref LL_EXTI_LINE_8
00520   *         @arg @ref LL_EXTI_LINE_9
00521   *         @arg @ref LL_EXTI_LINE_10
00522   *         @arg @ref LL_EXTI_LINE_11
00523   *         @arg @ref LL_EXTI_LINE_12
00524   *         @arg @ref LL_EXTI_LINE_13
00525   *         @arg @ref LL_EXTI_LINE_14
00526   *         @arg @ref LL_EXTI_LINE_15
00527   *         @arg @ref LL_EXTI_LINE_16
00528   *         @arg @ref LL_EXTI_LINE_17
00529   *         @arg @ref LL_EXTI_LINE_18
00530   *         @arg @ref LL_EXTI_LINE_19
00531   *         @arg @ref LL_EXTI_LINE_20
00532   *         @arg @ref LL_EXTI_LINE_21
00533   *         @arg @ref LL_EXTI_LINE_22
00534   *         @arg @ref LL_EXTI_LINE_23
00535   *         @arg @ref LL_EXTI_LINE_24
00536   *         @arg @ref LL_EXTI_LINE_25
00537   *         @arg @ref LL_EXTI_LINE_26
00538   *         @arg @ref LL_EXTI_LINE_27
00539   *         @arg @ref LL_EXTI_LINE_28
00540   *         @arg @ref LL_EXTI_LINE_29
00541   *         @arg @ref LL_EXTI_LINE_30
00542   *         @arg @ref LL_EXTI_LINE_31
00543   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00544   * @note   Please check each device line mapping for EXTI Line availability
00545   * @retval None
00546   */
00547 __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
00548 {
00549   SET_BIT(EXTI->EMR, ExtiLine);
00550
00551 }
00552
00553 #if defined(EXTI_32_63_SUPPORT)
00554 /**
00555   * @brief  Enable ExtiLine Event request for Lines in range 32 to 63
00556   * @rmtoll EMR2         EMx           LL_EXTI_EnableEvent_32_63
00557   * @param  ExtiLine This parameter can be a combination of the following values:
00558   *         @arg @ref LL_EXTI_LINE_32
00559   *         @arg @ref LL_EXTI_LINE_33
00560   *         @arg @ref LL_EXTI_LINE_34
00561   *         @arg @ref LL_EXTI_LINE_35
00562   *         @arg @ref LL_EXTI_LINE_36
00563   *         @arg @ref LL_EXTI_LINE_37
00564   *         @arg @ref LL_EXTI_LINE_38
00565   *         @arg @ref LL_EXTI_LINE_39
00566   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00567   * @retval None
00568   */
00569 __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
00570 {
00571   SET_BIT(EXTI->EMR2, ExtiLine);
00572 }
00573 #endif
00574
00575 /**
00576   * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
00577   * @rmtoll EMR         EMx           LL_EXTI_DisableEvent_0_31
00578   * @param  ExtiLine This parameter can be one of the following values:
00579   *         @arg @ref LL_EXTI_LINE_0
00580   *         @arg @ref LL_EXTI_LINE_1
00581   *         @arg @ref LL_EXTI_LINE_2
00582   *         @arg @ref LL_EXTI_LINE_3
00583   *         @arg @ref LL_EXTI_LINE_4
00584   *         @arg @ref LL_EXTI_LINE_5
00585   *         @arg @ref LL_EXTI_LINE_6
00586   *         @arg @ref LL_EXTI_LINE_7
00587   *         @arg @ref LL_EXTI_LINE_8
00588   *         @arg @ref LL_EXTI_LINE_9
00589   *         @arg @ref LL_EXTI_LINE_10
00590   *         @arg @ref LL_EXTI_LINE_11
00591   *         @arg @ref LL_EXTI_LINE_12
00592   *         @arg @ref LL_EXTI_LINE_13
00593   *         @arg @ref LL_EXTI_LINE_14
00594   *         @arg @ref LL_EXTI_LINE_15
00595   *         @arg @ref LL_EXTI_LINE_16
00596   *         @arg @ref LL_EXTI_LINE_17
00597   *         @arg @ref LL_EXTI_LINE_18
00598   *         @arg @ref LL_EXTI_LINE_19
00599   *         @arg @ref LL_EXTI_LINE_20
00600   *         @arg @ref LL_EXTI_LINE_21
00601   *         @arg @ref LL_EXTI_LINE_22
00602   *         @arg @ref LL_EXTI_LINE_23
00603   *         @arg @ref LL_EXTI_LINE_24
00604   *         @arg @ref LL_EXTI_LINE_25
00605   *         @arg @ref LL_EXTI_LINE_26
00606   *         @arg @ref LL_EXTI_LINE_27
00607   *         @arg @ref LL_EXTI_LINE_28
00608   *         @arg @ref LL_EXTI_LINE_29
00609   *         @arg @ref LL_EXTI_LINE_30
00610   *         @arg @ref LL_EXTI_LINE_31
00611   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00612   * @note   Please check each device line mapping for EXTI Line availability
00613   * @retval None
00614   */
00615 __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
00616 {
00617   CLEAR_BIT(EXTI->EMR, ExtiLine);
00618 }
00619
00620 #if defined(EXTI_32_63_SUPPORT)
00621 /**
00622   * @brief  Disable ExtiLine Event request for Lines in range 32 to 63
00623   * @rmtoll EMR2         EMx           LL_EXTI_DisableEvent_32_63
00624   * @param  ExtiLine This parameter can be a combination of the following values:
00625   *         @arg @ref LL_EXTI_LINE_32
00626   *         @arg @ref LL_EXTI_LINE_33
00627   *         @arg @ref LL_EXTI_LINE_34
00628   *         @arg @ref LL_EXTI_LINE_35
00629   *         @arg @ref LL_EXTI_LINE_36
00630   *         @arg @ref LL_EXTI_LINE_37
00631   *         @arg @ref LL_EXTI_LINE_38
00632   *         @arg @ref LL_EXTI_LINE_39
00633   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00634   * @retval None
00635   */
00636 __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
00637 {
00638   CLEAR_BIT(EXTI->EMR2, ExtiLine);
00639 }
00640 #endif
00641
00642 /**
00643   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
00644   * @rmtoll EMR         EMx           LL_EXTI_IsEnabledEvent_0_31
00645   * @param  ExtiLine This parameter can be one of the following values:
00646   *         @arg @ref LL_EXTI_LINE_0
00647   *         @arg @ref LL_EXTI_LINE_1
00648   *         @arg @ref LL_EXTI_LINE_2
00649   *         @arg @ref LL_EXTI_LINE_3
00650   *         @arg @ref LL_EXTI_LINE_4
00651   *         @arg @ref LL_EXTI_LINE_5
00652   *         @arg @ref LL_EXTI_LINE_6
00653   *         @arg @ref LL_EXTI_LINE_7
00654   *         @arg @ref LL_EXTI_LINE_8
00655   *         @arg @ref LL_EXTI_LINE_9
00656   *         @arg @ref LL_EXTI_LINE_10
00657   *         @arg @ref LL_EXTI_LINE_11
00658   *         @arg @ref LL_EXTI_LINE_12
00659   *         @arg @ref LL_EXTI_LINE_13
00660   *         @arg @ref LL_EXTI_LINE_14
00661   *         @arg @ref LL_EXTI_LINE_15
00662   *         @arg @ref LL_EXTI_LINE_16
00663   *         @arg @ref LL_EXTI_LINE_17
00664   *         @arg @ref LL_EXTI_LINE_18
00665   *         @arg @ref LL_EXTI_LINE_19
00666   *         @arg @ref LL_EXTI_LINE_20
00667   *         @arg @ref LL_EXTI_LINE_21
00668   *         @arg @ref LL_EXTI_LINE_22
00669   *         @arg @ref LL_EXTI_LINE_23
00670   *         @arg @ref LL_EXTI_LINE_24
00671   *         @arg @ref LL_EXTI_LINE_25
00672   *         @arg @ref LL_EXTI_LINE_26
00673   *         @arg @ref LL_EXTI_LINE_27
00674   *         @arg @ref LL_EXTI_LINE_28
00675   *         @arg @ref LL_EXTI_LINE_29
00676   *         @arg @ref LL_EXTI_LINE_30
00677   *         @arg @ref LL_EXTI_LINE_31
00678   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00679   * @note   Please check each device line mapping for EXTI Line availability
00680   * @retval State of bit (1 or 0).
00681   */
00682 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
00683 {
00684   return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
00685
00686 }
00687
00688 #if defined(EXTI_32_63_SUPPORT)
00689 /**
00690   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
00691   * @rmtoll EMR2         EMx           LL_EXTI_IsEnabledEvent_32_63
00692   * @param  ExtiLine This parameter can be a combination of the following values:
00693   *         @arg @ref LL_EXTI_LINE_32
00694   *         @arg @ref LL_EXTI_LINE_33
00695   *         @arg @ref LL_EXTI_LINE_34
00696   *         @arg @ref LL_EXTI_LINE_35
00697   *         @arg @ref LL_EXTI_LINE_36
00698   *         @arg @ref LL_EXTI_LINE_37
00699   *         @arg @ref LL_EXTI_LINE_38
00700   *         @arg @ref LL_EXTI_LINE_39
00701   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00702   * @retval State of bit (1 or 0).
00703   */
00704 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
00705 {
00706   return (READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine));
00707 }
00708 #endif
00709
00710 /**
00711   * @}
00712   */
00713
00714 /** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
00715   * @{
00716   */
00717
00718 /**
00719   * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
00720   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00721   *       generated on these lines. If a rising edge on a configurable interrupt
00722   *       line occurs during a write operation in the EXTI_RTSR register, the
00723   *       pending bit is not set.
00724   *       Rising and falling edge triggers can be set for
00725   *       the same interrupt line. In this case, both generate a trigger
00726   *       condition.
00727   * @rmtoll RTSR        RTx           LL_EXTI_EnableRisingTrig_0_31
00728   * @param  ExtiLine This parameter can be a combination of the following values:
00729   *         @arg @ref LL_EXTI_LINE_0
00730   *         @arg @ref LL_EXTI_LINE_1
00731   *         @arg @ref LL_EXTI_LINE_2
00732   *         @arg @ref LL_EXTI_LINE_3
00733   *         @arg @ref LL_EXTI_LINE_4
00734   *         @arg @ref LL_EXTI_LINE_5
00735   *         @arg @ref LL_EXTI_LINE_6
00736   *         @arg @ref LL_EXTI_LINE_7
00737   *         @arg @ref LL_EXTI_LINE_8
00738   *         @arg @ref LL_EXTI_LINE_9
00739   *         @arg @ref LL_EXTI_LINE_10
00740   *         @arg @ref LL_EXTI_LINE_11
00741   *         @arg @ref LL_EXTI_LINE_12
00742   *         @arg @ref LL_EXTI_LINE_13
00743   *         @arg @ref LL_EXTI_LINE_14
00744   *         @arg @ref LL_EXTI_LINE_15
00745   *         @arg @ref LL_EXTI_LINE_16
00746   *         @arg @ref LL_EXTI_LINE_18
00747   *         @arg @ref LL_EXTI_LINE_19
00748   *         @arg @ref LL_EXTI_LINE_20
00749   *         @arg @ref LL_EXTI_LINE_21
00750   *         @arg @ref LL_EXTI_LINE_22
00751   *         @arg @ref LL_EXTI_LINE_29
00752   *         @arg @ref LL_EXTI_LINE_30
00753   *         @arg @ref LL_EXTI_LINE_31
00754   * @note   Please check each device line mapping for EXTI Line availability
00755   * @retval None
00756   */
00757 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
00758 {
00759   SET_BIT(EXTI->RTSR, ExtiLine);
00760
00761 }
00762
00763 #if defined(EXTI_32_63_SUPPORT)
00764 /**
00765   * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
00766   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00767   *       generated on these lines. If a rising edge on a configurable interrupt
00768   *       line occurs during a write operation in the EXTI_RTSR register, the
00769   *       pending bit is not set.Rising and falling edge triggers can be set for
00770   *       the same interrupt line. In this case, both generate a trigger
00771   *       condition.
00772   * @rmtoll RTSR2        RTx           LL_EXTI_EnableRisingTrig_32_63
00773   * @param  ExtiLine This parameter can be a combination of the following values:
00774   *         @arg @ref LL_EXTI_LINE_35
00775   *         @arg @ref LL_EXTI_LINE_36
00776   *         @arg @ref LL_EXTI_LINE_37
00777   *         @arg @ref LL_EXTI_LINE_38
00778   * @retval None
00779   */
00780 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
00781 {
00782   SET_BIT(EXTI->RTSR2, ExtiLine);
00783 }
00784 #endif
00785
00786 /**
00787   * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
00788   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00789   *       generated on these lines. If a rising edge on a configurable interrupt
00790   *       line occurs during a write operation in the EXTI_RTSR register, the
00791   *       pending bit is not set.
00792   *       Rising and falling edge triggers can be set for
00793   *       the same interrupt line. In this case, both generate a trigger
00794   *       condition.
00795   * @rmtoll RTSR        RTx           LL_EXTI_DisableRisingTrig_0_31
00796   * @param  ExtiLine This parameter can be a combination of the following values:
00797   *         @arg @ref LL_EXTI_LINE_0
00798   *         @arg @ref LL_EXTI_LINE_1
00799   *         @arg @ref LL_EXTI_LINE_2
00800   *         @arg @ref LL_EXTI_LINE_3
00801   *         @arg @ref LL_EXTI_LINE_4
00802   *         @arg @ref LL_EXTI_LINE_5
00803   *         @arg @ref LL_EXTI_LINE_6
00804   *         @arg @ref LL_EXTI_LINE_7
00805   *         @arg @ref LL_EXTI_LINE_8
00806   *         @arg @ref LL_EXTI_LINE_9
00807   *         @arg @ref LL_EXTI_LINE_10
00808   *         @arg @ref LL_EXTI_LINE_11
00809   *         @arg @ref LL_EXTI_LINE_12
00810   *         @arg @ref LL_EXTI_LINE_13
00811   *         @arg @ref LL_EXTI_LINE_14
00812   *         @arg @ref LL_EXTI_LINE_15
00813   *         @arg @ref LL_EXTI_LINE_16
00814   *         @arg @ref LL_EXTI_LINE_18
00815   *         @arg @ref LL_EXTI_LINE_19
00816   *         @arg @ref LL_EXTI_LINE_20
00817   *         @arg @ref LL_EXTI_LINE_21
00818   *         @arg @ref LL_EXTI_LINE_22
00819   *         @arg @ref LL_EXTI_LINE_29
00820   *         @arg @ref LL_EXTI_LINE_30
00821   *         @arg @ref LL_EXTI_LINE_31
00822   * @note   Please check each device line mapping for EXTI Line availability
00823   * @retval None
00824   */
00825 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
00826 {
00827   CLEAR_BIT(EXTI->RTSR, ExtiLine);
00828
00829 }
00830
00831 #if defined(EXTI_32_63_SUPPORT)
00832 /**
00833   * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
00834   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00835   *       generated on these lines. If a rising edge on a configurable interrupt
00836   *       line occurs during a write operation in the EXTI_RTSR register, the
00837   *       pending bit is not set.
00838   *       Rising and falling edge triggers can be set for
00839   *       the same interrupt line. In this case, both generate a trigger
00840   *       condition.
00841   * @rmtoll RTSR2        RTx           LL_EXTI_DisableRisingTrig_32_63
00842   * @param  ExtiLine This parameter can be a combination of the following values:
00843   *         @arg @ref LL_EXTI_LINE_35
00844   *         @arg @ref LL_EXTI_LINE_36
00845   *         @arg @ref LL_EXTI_LINE_37
00846   *         @arg @ref LL_EXTI_LINE_38
00847   * @retval None
00848   */
00849 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
00850 {
00851   CLEAR_BIT(EXTI->RTSR2, ExtiLine);
00852 }
00853 #endif
00854
00855 /**
00856   * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
00857   * @rmtoll RTSR        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
00858   * @param  ExtiLine This parameter can be a combination of the following values:
00859   *         @arg @ref LL_EXTI_LINE_0
00860   *         @arg @ref LL_EXTI_LINE_1
00861   *         @arg @ref LL_EXTI_LINE_2
00862   *         @arg @ref LL_EXTI_LINE_3
00863   *         @arg @ref LL_EXTI_LINE_4
00864   *         @arg @ref LL_EXTI_LINE_5
00865   *         @arg @ref LL_EXTI_LINE_6
00866   *         @arg @ref LL_EXTI_LINE_7
00867   *         @arg @ref LL_EXTI_LINE_8
00868   *         @arg @ref LL_EXTI_LINE_9
00869   *         @arg @ref LL_EXTI_LINE_10
00870   *         @arg @ref LL_EXTI_LINE_11
00871   *         @arg @ref LL_EXTI_LINE_12
00872   *         @arg @ref LL_EXTI_LINE_13
00873   *         @arg @ref LL_EXTI_LINE_14
00874   *         @arg @ref LL_EXTI_LINE_15
00875   *         @arg @ref LL_EXTI_LINE_16
00876   *         @arg @ref LL_EXTI_LINE_18
00877   *         @arg @ref LL_EXTI_LINE_19
00878   *         @arg @ref LL_EXTI_LINE_20
00879   *         @arg @ref LL_EXTI_LINE_21
00880   *         @arg @ref LL_EXTI_LINE_22
00881   *         @arg @ref LL_EXTI_LINE_29
00882   *         @arg @ref LL_EXTI_LINE_30
00883   *         @arg @ref LL_EXTI_LINE_31
00884   * @note   Please check each device line mapping for EXTI Line availability
00885   * @retval State of bit (1 or 0).
00886   */
00887 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
00888 {
00889   return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
00890 }
00891
00892 #if defined(EXTI_32_63_SUPPORT)
00893 /**
00894   * @brief  Check if rising edge trigger is enabled for Lines in range 32 to 63
00895   * @rmtoll RTSR2        RTx           LL_EXTI_IsEnabledRisingTrig_32_63
00896   * @param  ExtiLine This parameter can be a combination of the following values:
00897   *         @arg @ref LL_EXTI_LINE_35
00898   *         @arg @ref LL_EXTI_LINE_36
00899   *         @arg @ref LL_EXTI_LINE_37
00900   *         @arg @ref LL_EXTI_LINE_38
00901   * @retval State of bit (1 or 0).
00902   */
00903 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
00904 {
00905   return (READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine));
00906 }
00907 #endif
00908
00909 /**
00910   * @}
00911   */
00912
00913 /** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
00914   * @{
00915   */
00916
00917 /**
00918   * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
00919   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00920   *       generated on these lines. If a falling edge on a configurable interrupt
00921   *       line occurs during a write operation in the EXTI_FTSR register, the
00922   *       pending bit is not set.
00923   *       Rising and falling edge triggers can be set for
00924   *       the same interrupt line. In this case, both generate a trigger
00925   *       condition.
00926   * @rmtoll FTSR        FTx           LL_EXTI_EnableFallingTrig_0_31
00927   * @param  ExtiLine This parameter can be a combination of the following values:
00928   *         @arg @ref LL_EXTI_LINE_0
00929   *         @arg @ref LL_EXTI_LINE_1
00930   *         @arg @ref LL_EXTI_LINE_2
00931   *         @arg @ref LL_EXTI_LINE_3
00932   *         @arg @ref LL_EXTI_LINE_4
00933   *         @arg @ref LL_EXTI_LINE_5
00934   *         @arg @ref LL_EXTI_LINE_6
00935   *         @arg @ref LL_EXTI_LINE_7
00936   *         @arg @ref LL_EXTI_LINE_8
00937   *         @arg @ref LL_EXTI_LINE_9
00938   *         @arg @ref LL_EXTI_LINE_10
00939   *         @arg @ref LL_EXTI_LINE_11
00940   *         @arg @ref LL_EXTI_LINE_12
00941   *         @arg @ref LL_EXTI_LINE_13
00942   *         @arg @ref LL_EXTI_LINE_14
00943   *         @arg @ref LL_EXTI_LINE_15
00944   *         @arg @ref LL_EXTI_LINE_16
00945   *         @arg @ref LL_EXTI_LINE_18
00946   *         @arg @ref LL_EXTI_LINE_19
00947   *         @arg @ref LL_EXTI_LINE_20
00948   *         @arg @ref LL_EXTI_LINE_21
00949   *         @arg @ref LL_EXTI_LINE_22
00950   *         @arg @ref LL_EXTI_LINE_29
00951   *         @arg @ref LL_EXTI_LINE_30
00952   *         @arg @ref LL_EXTI_LINE_31
00953   * @note   Please check each device line mapping for EXTI Line availability
00954   * @retval None
00955   */
00956 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
00957 {
00958   SET_BIT(EXTI->FTSR, ExtiLine);
00959 }
00960
00961 #if defined(EXTI_32_63_SUPPORT)
00962 /**
00963   * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
00964   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00965   *       generated on these lines. If a Falling edge on a configurable interrupt
00966   *       line occurs during a write operation in the EXTI_FTSR register, the
00967   *       pending bit is not set.
00968   *       Rising and falling edge triggers can be set for
00969   *       the same interrupt line. In this case, both generate a trigger
00970   *       condition.
00971   * @rmtoll FTSR2        FTx           LL_EXTI_EnableFallingTrig_32_63
00972   * @param  ExtiLine This parameter can be a combination of the following values:
00973   *         @arg @ref LL_EXTI_LINE_35
00974   *         @arg @ref LL_EXTI_LINE_36
00975   *         @arg @ref LL_EXTI_LINE_37
00976   *         @arg @ref LL_EXTI_LINE_38
00977   * @retval None
00978   */
00979 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
00980 {
00981   SET_BIT(EXTI->FTSR2, ExtiLine);
00982 }
00983 #endif
00984
00985 /**
00986   * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
00987   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00988   *       generated on these lines. If a Falling edge on a configurable interrupt
00989   *       line occurs during a write operation in the EXTI_FTSR register, the
00990   *       pending bit is not set.
00991   *       Rising and falling edge triggers can be set for the same interrupt line.
00992   *       In this case, both generate a trigger condition.
00993   * @rmtoll FTSR        FTx           LL_EXTI_DisableFallingTrig_0_31
00994   * @param  ExtiLine This parameter can be a combination of the following values:
00995   *         @arg @ref LL_EXTI_LINE_0
00996   *         @arg @ref LL_EXTI_LINE_1
00997   *         @arg @ref LL_EXTI_LINE_2
00998   *         @arg @ref LL_EXTI_LINE_3
00999   *         @arg @ref LL_EXTI_LINE_4
01000   *         @arg @ref LL_EXTI_LINE_5
01001   *         @arg @ref LL_EXTI_LINE_6
01002   *         @arg @ref LL_EXTI_LINE_7
01003   *         @arg @ref LL_EXTI_LINE_8
01004   *         @arg @ref LL_EXTI_LINE_9
01005   *         @arg @ref LL_EXTI_LINE_10
01006   *         @arg @ref LL_EXTI_LINE_11
01007   *         @arg @ref LL_EXTI_LINE_12
01008   *         @arg @ref LL_EXTI_LINE_13
01009   *         @arg @ref LL_EXTI_LINE_14
01010   *         @arg @ref LL_EXTI_LINE_15
01011   *         @arg @ref LL_EXTI_LINE_16
01012   *         @arg @ref LL_EXTI_LINE_18
01013   *         @arg @ref LL_EXTI_LINE_19
01014   *         @arg @ref LL_EXTI_LINE_20
01015   *         @arg @ref LL_EXTI_LINE_21
01016   *         @arg @ref LL_EXTI_LINE_22
01017   *         @arg @ref LL_EXTI_LINE_29
01018   *         @arg @ref LL_EXTI_LINE_30
01019   *         @arg @ref LL_EXTI_LINE_31
01020   * @note   Please check each device line mapping for EXTI Line availability
01021   * @retval None
01022   */
01023 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
01024 {
01025   CLEAR_BIT(EXTI->FTSR, ExtiLine);
01026 }
01027
01028 #if defined(EXTI_32_63_SUPPORT)
01029 /**
01030   * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
01031   * @note The configurable wakeup lines are edge-triggered. No glitch must be
01032   *       generated on these lines. If a Falling edge on a configurable interrupt
01033   *       line occurs during a write operation in the EXTI_FTSR register, the
01034   *       pending bit is not set.
01035   *       Rising and falling edge triggers can be set for the same interrupt line.
01036   *       In this case, both generate a trigger condition.
01037   * @rmtoll FTSR2        FTx           LL_EXTI_DisableFallingTrig_32_63
01038   * @param  ExtiLine This parameter can be a combination of the following values:
01039   *         @arg @ref LL_EXTI_LINE_35
01040   *         @arg @ref LL_EXTI_LINE_36
01041   *         @arg @ref LL_EXTI_LINE_37
01042   *         @arg @ref LL_EXTI_LINE_38
01043   * @retval None
01044   */
01045 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
01046 {
01047   CLEAR_BIT(EXTI->FTSR2, ExtiLine);
01048 }
01049 #endif
01050
01051 /**
01052   * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
01053   * @rmtoll FTSR        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
01054   * @param  ExtiLine This parameter can be a combination of the following values:
01055   *         @arg @ref LL_EXTI_LINE_0
01056   *         @arg @ref LL_EXTI_LINE_1
01057   *         @arg @ref LL_EXTI_LINE_2
01058   *         @arg @ref LL_EXTI_LINE_3
01059   *         @arg @ref LL_EXTI_LINE_4
01060   *         @arg @ref LL_EXTI_LINE_5
01061   *         @arg @ref LL_EXTI_LINE_6
01062   *         @arg @ref LL_EXTI_LINE_7
01063   *         @arg @ref LL_EXTI_LINE_8
01064   *         @arg @ref LL_EXTI_LINE_9
01065   *         @arg @ref LL_EXTI_LINE_10
01066   *         @arg @ref LL_EXTI_LINE_11
01067   *         @arg @ref LL_EXTI_LINE_12
01068   *         @arg @ref LL_EXTI_LINE_13
01069   *         @arg @ref LL_EXTI_LINE_14
01070   *         @arg @ref LL_EXTI_LINE_15
01071   *         @arg @ref LL_EXTI_LINE_16
01072   *         @arg @ref LL_EXTI_LINE_18
01073   *         @arg @ref LL_EXTI_LINE_19
01074   *         @arg @ref LL_EXTI_LINE_20
01075   *         @arg @ref LL_EXTI_LINE_21
01076   *         @arg @ref LL_EXTI_LINE_22
01077   *         @arg @ref LL_EXTI_LINE_29
01078   *         @arg @ref LL_EXTI_LINE_30
01079   *         @arg @ref LL_EXTI_LINE_31
01080   * @note   Please check each device line mapping for EXTI Line availability
01081   * @retval State of bit (1 or 0).
01082   */
01083 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
01084 {
01085   return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
01086 }
01087
01088 #if defined(EXTI_32_63_SUPPORT)
01089 /**
01090   * @brief  Check if falling edge trigger is enabled for Lines in range 32 to 63
01091   * @rmtoll FTSR2        FTx           LL_EXTI_IsEnabledFallingTrig_32_63
01092   * @param  ExtiLine This parameter can be a combination of the following values:
01093   *         @arg @ref LL_EXTI_LINE_35
01094   *         @arg @ref LL_EXTI_LINE_36
01095   *         @arg @ref LL_EXTI_LINE_37
01096   *         @arg @ref LL_EXTI_LINE_38
01097   * @retval State of bit (1 or 0).
01098   */
01099 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
01100 {
01101   return (READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine));
01102 }
01103 #endif
01104
01105 /**
01106   * @}
01107   */
01108
01109 /** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
01110   * @{
01111   */
01112
01113 /**
01114   * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
01115   * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
01116   *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
01117   *       resulting in an interrupt request generation.
01118   *       This bit is cleared by clearing the corresponding bit in the EXTI_PR
01119   *       register (by writing a 1 into the bit)
01120   * @rmtoll SWIER       SWIx          LL_EXTI_GenerateSWI_0_31
01121   * @param  ExtiLine This parameter can be a combination of the following values:
01122   *         @arg @ref LL_EXTI_LINE_0
01123   *         @arg @ref LL_EXTI_LINE_1
01124   *         @arg @ref LL_EXTI_LINE_2
01125   *         @arg @ref LL_EXTI_LINE_3
01126   *         @arg @ref LL_EXTI_LINE_4
01127   *         @arg @ref LL_EXTI_LINE_5
01128   *         @arg @ref LL_EXTI_LINE_6
01129   *         @arg @ref LL_EXTI_LINE_7
01130   *         @arg @ref LL_EXTI_LINE_8
01131   *         @arg @ref LL_EXTI_LINE_9
01132   *         @arg @ref LL_EXTI_LINE_10
01133   *         @arg @ref LL_EXTI_LINE_11
01134   *         @arg @ref LL_EXTI_LINE_12
01135   *         @arg @ref LL_EXTI_LINE_13
01136   *         @arg @ref LL_EXTI_LINE_14
01137   *         @arg @ref LL_EXTI_LINE_15
01138   *         @arg @ref LL_EXTI_LINE_16
01139   *         @arg @ref LL_EXTI_LINE_18
01140   *         @arg @ref LL_EXTI_LINE_19
01141   *         @arg @ref LL_EXTI_LINE_20
01142   *         @arg @ref LL_EXTI_LINE_21
01143   *         @arg @ref LL_EXTI_LINE_22
01144   *         @arg @ref LL_EXTI_LINE_29
01145   *         @arg @ref LL_EXTI_LINE_30
01146   *         @arg @ref LL_EXTI_LINE_31
01147   * @note   Please check each device line mapping for EXTI Line availability
01148   * @retval None
01149   */
01150 __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
01151 {
01152   SET_BIT(EXTI->SWIER, ExtiLine);
01153 }
01154
01155 #if defined(EXTI_32_63_SUPPORT)
01156 /**
01157   * @brief  Generate a software Interrupt Event for Lines in range 32 to 63
01158   * @note If the interrupt is enabled on this line inthe EXTI_IMR2, writing a 1 to
01159   *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
01160   *       resulting in an interrupt request generation.
01161   *       This bit is cleared by clearing the corresponding bit in the EXTI_PR2
01162   *       register (by writing a 1 into the bit)
01163   * @rmtoll SWIER2       SWIx          LL_EXTI_GenerateSWI_32_63
01164   * @param  ExtiLine This parameter can be a combination of the following values:
01165   *         @arg @ref LL_EXTI_LINE_35
01166   *         @arg @ref LL_EXTI_LINE_36
01167   *         @arg @ref LL_EXTI_LINE_37
01168   *         @arg @ref LL_EXTI_LINE_38
01169   * @retval None
01170   */
01171 __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
01172 {
01173   SET_BIT(EXTI->SWIER2, ExtiLine);
01174 }
01175 #endif
01176
01177 /**
01178   * @}
01179   */
01180
01181 /** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
01182   * @{
01183   */
01184
01185 /**
01186   * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
01187   * @note This bit is set when the selected edge event arrives on the interrupt
01188   *       line. This bit is cleared by writing a 1 to the bit.
01189   * @rmtoll PR          PIFx           LL_EXTI_IsActiveFlag_0_31
01190   * @param  ExtiLine This parameter can be a combination of the following values:
01191   *         @arg @ref LL_EXTI_LINE_0
01192   *         @arg @ref LL_EXTI_LINE_1
01193   *         @arg @ref LL_EXTI_LINE_2
01194   *         @arg @ref LL_EXTI_LINE_3
01195   *         @arg @ref LL_EXTI_LINE_4
01196   *         @arg @ref LL_EXTI_LINE_5
01197   *         @arg @ref LL_EXTI_LINE_6
01198   *         @arg @ref LL_EXTI_LINE_7
01199   *         @arg @ref LL_EXTI_LINE_8
01200   *         @arg @ref LL_EXTI_LINE_9
01201   *         @arg @ref LL_EXTI_LINE_10
01202   *         @arg @ref LL_EXTI_LINE_11
01203   *         @arg @ref LL_EXTI_LINE_12
01204   *         @arg @ref LL_EXTI_LINE_13
01205   *         @arg @ref LL_EXTI_LINE_14
01206   *         @arg @ref LL_EXTI_LINE_15
01207   *         @arg @ref LL_EXTI_LINE_16
01208   *         @arg @ref LL_EXTI_LINE_18
01209   *         @arg @ref LL_EXTI_LINE_19
01210   *         @arg @ref LL_EXTI_LINE_20
01211   *         @arg @ref LL_EXTI_LINE_21
01212   *         @arg @ref LL_EXTI_LINE_22
01213   *         @arg @ref LL_EXTI_LINE_29
01214   *         @arg @ref LL_EXTI_LINE_30
01215   *         @arg @ref LL_EXTI_LINE_31
01216   * @note   Please check each device line mapping for EXTI Line availability
01217   * @retval State of bit (1 or 0).
01218   */
01219 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
01220 {
01221   return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
01222 }
01223
01224 #if defined(EXTI_32_63_SUPPORT)
01225 /**
01226   * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63
01227   * @note This bit is set when the selected edge event arrives on the interrupt
01228   *       line. This bit is cleared by writing a 1 to the bit.
01229   * @rmtoll PR2          PIFx           LL_EXTI_IsActiveFlag_32_63
01230   * @param  ExtiLine This parameter can be a combination of the following values:
01231   *         @arg @ref LL_EXTI_LINE_35
01232   *         @arg @ref LL_EXTI_LINE_36
01233   *         @arg @ref LL_EXTI_LINE_37
01234   *         @arg @ref LL_EXTI_LINE_38
01235   * @retval State of bit (1 or 0).
01236   */
01237 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
01238 {
01239   return (READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine));
01240 }
01241 #endif
01242
01243 /**
01244   * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
01245   * @note This bit is set when the selected edge event arrives on the interrupt
01246   *       line. This bit is cleared by writing a 1 to the bit.
01247   * @rmtoll PR          PIFx           LL_EXTI_ReadFlag_0_31
01248   * @param  ExtiLine This parameter can be a combination of the following values:
01249   *         @arg @ref LL_EXTI_LINE_0
01250   *         @arg @ref LL_EXTI_LINE_1
01251   *         @arg @ref LL_EXTI_LINE_2
01252   *         @arg @ref LL_EXTI_LINE_3
01253   *         @arg @ref LL_EXTI_LINE_4
01254   *         @arg @ref LL_EXTI_LINE_5
01255   *         @arg @ref LL_EXTI_LINE_6
01256   *         @arg @ref LL_EXTI_LINE_7
01257   *         @arg @ref LL_EXTI_LINE_8
01258   *         @arg @ref LL_EXTI_LINE_9
01259   *         @arg @ref LL_EXTI_LINE_10
01260   *         @arg @ref LL_EXTI_LINE_11
01261   *         @arg @ref LL_EXTI_LINE_12
01262   *         @arg @ref LL_EXTI_LINE_13
01263   *         @arg @ref LL_EXTI_LINE_14
01264   *         @arg @ref LL_EXTI_LINE_15
01265   *         @arg @ref LL_EXTI_LINE_16
01266   *         @arg @ref LL_EXTI_LINE_18
01267   *         @arg @ref LL_EXTI_LINE_19
01268   *         @arg @ref LL_EXTI_LINE_20
01269   *         @arg @ref LL_EXTI_LINE_21
01270   *         @arg @ref LL_EXTI_LINE_22
01271   *         @arg @ref LL_EXTI_LINE_29
01272   *         @arg @ref LL_EXTI_LINE_30
01273   *         @arg @ref LL_EXTI_LINE_31
01274   * @note   Please check each device line mapping for EXTI Line availability
01275   * @retval @note This bit is set when the selected edge event arrives on the interrupt
01276   */
01277 __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
01278 {
01279   return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
01280 }
01281
01282 #if defined(EXTI_32_63_SUPPORT)
01283
01284 /**
01285   * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63
01286   * @note This bit is set when the selected edge event arrives on the interrupt
01287   *       line. This bit is cleared by writing a 1 to the bit.
01288   * @rmtoll PR2          PIFx           LL_EXTI_ReadFlag_32_63
01289   * @param  ExtiLine This parameter can be a combination of the following values:
01290   *         @arg @ref LL_EXTI_LINE_35
01291   *         @arg @ref LL_EXTI_LINE_36
01292   *         @arg @ref LL_EXTI_LINE_37
01293   *         @arg @ref LL_EXTI_LINE_38
01294   * @retval @note This bit is set when the selected edge event arrives on the interrupt
01295   */
01296 __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
01297 {
01298   return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
01299 }
01300 #endif
01301
01302 /**
01303   * @brief  Clear ExtLine Flags  for Lines in range 0 to 31
01304   * @note This bit is set when the selected edge event arrives on the interrupt
01305   *       line. This bit is cleared by writing a 1 to the bit.
01306   * @rmtoll PR          PIFx           LL_EXTI_ClearFlag_0_31
01307   * @param  ExtiLine This parameter can be a combination of the following values:
01308   *         @arg @ref LL_EXTI_LINE_0
01309   *         @arg @ref LL_EXTI_LINE_1
01310   *         @arg @ref LL_EXTI_LINE_2
01311   *         @arg @ref LL_EXTI_LINE_3
01312   *         @arg @ref LL_EXTI_LINE_4
01313   *         @arg @ref LL_EXTI_LINE_5
01314   *         @arg @ref LL_EXTI_LINE_6
01315   *         @arg @ref LL_EXTI_LINE_7
01316   *         @arg @ref LL_EXTI_LINE_8
01317   *         @arg @ref LL_EXTI_LINE_9
01318   *         @arg @ref LL_EXTI_LINE_10
01319   *         @arg @ref LL_EXTI_LINE_11
01320   *         @arg @ref LL_EXTI_LINE_12
01321   *         @arg @ref LL_EXTI_LINE_13
01322   *         @arg @ref LL_EXTI_LINE_14
01323   *         @arg @ref LL_EXTI_LINE_15
01324   *         @arg @ref LL_EXTI_LINE_16
01325   *         @arg @ref LL_EXTI_LINE_18
01326   *         @arg @ref LL_EXTI_LINE_19
01327   *         @arg @ref LL_EXTI_LINE_20
01328   *         @arg @ref LL_EXTI_LINE_21
01329   *         @arg @ref LL_EXTI_LINE_22
01330   *         @arg @ref LL_EXTI_LINE_29
01331   *         @arg @ref LL_EXTI_LINE_30
01332   *         @arg @ref LL_EXTI_LINE_31
01333   * @note   Please check each device line mapping for EXTI Line availability
01334   * @retval None
01335   */
01336 __STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
01337 {
01338   WRITE_REG(EXTI->PR, ExtiLine);
01339 }
01340
01341 #if defined(EXTI_32_63_SUPPORT)
01342 /**
01343   * @brief  Clear ExtLine Flags for  Lines in range 32 to 63
01344   * @note This bit is set when the selected edge event arrives on the interrupt
01345   *       line. This bit is cleared by writing a 1 to the bit.
01346   * @rmtoll PR2          PIFx           LL_EXTI_ClearFlag_32_63
01347   * @param  ExtiLine This parameter can be a combination of the following values:
01348   *         @arg @ref LL_EXTI_LINE_35
01349   *         @arg @ref LL_EXTI_LINE_36
01350   *         @arg @ref LL_EXTI_LINE_37
01351   *         @arg @ref LL_EXTI_LINE_38
01352   * @retval None
01353   */
01354 __STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
01355 {
01356   WRITE_REG(EXTI->PR2, ExtiLine);
01357 }
01358 #endif
01359
01360 /**
01361   * @}
01362   */
01363
01364 #if defined(USE_FULL_LL_DRIVER)
01365 /** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
01366   * @{
01367   */
01368
01369 uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
01370 uint32_t LL_EXTI_DeInit(void);
01371 void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
01372
01373
01374 /**
01375   * @}
01376   */
01377 #endif /* USE_FULL_LL_DRIVER */
01378
01379 /**
01380   * @}
01381   */
01382
01383 /**
01384   * @}
01385   */
01386
01387 #endif /* EXTI */
01388
01389 /**
01390   * @}
01391   */
01392
01393 #ifdef __cplusplus
01394 }
01395 #endif
01396
01397 #endif /* __STM32F3xx_LL_EXTI_H */
01398
01399 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_gpio.c Source File

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stm32f3xx_ll_gpio.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_gpio.c
00004   * @author  MCD Application Team
00005   * @brief   GPIO LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 #if defined(USE_FULL_LL_DRIVER)
00036
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f3xx_ll_gpio.h"
00039 #include "stm32f3xx_ll_bus.h"
00040 #ifdef  USE_FULL_ASSERT
00041 #include "stm32_assert.h"
00042 #else
00043 #define assert_param(expr) ((void)0U)
00044 #endif
00045
00046 /** @addtogroup STM32F3xx_LL_Driver
00047   * @{
00048   */
00049
00050 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH)
00051
00052 /** @addtogroup GPIO_LL
00053   * @{
00054   */
00055
00056 /* Private types -------------------------------------------------------------*/
00057 /* Private variables ---------------------------------------------------------*/
00058 /* Private constants ---------------------------------------------------------*/
00059 /* Private macros ------------------------------------------------------------*/
00060 /** @addtogroup GPIO_LL_Private_Macros
00061   * @{
00062   */
00063 #define IS_LL_GPIO_PIN(__VALUE__)          (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
00064
00065 #define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
00066                                             ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
00067                                             ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
00068                                             ((__VALUE__) == LL_GPIO_MODE_ANALOG))
00069
00070 #define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
00071                                             ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
00072
00073 #define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
00074                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
00075                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH))
00076
00077 #define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
00078                                             ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
00079                                             ((__VALUE__) == LL_GPIO_PULL_DOWN))
00080
00081 #define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
00082                                             ((__VALUE__) == LL_GPIO_AF_1  )   ||\
00083                                             ((__VALUE__) == LL_GPIO_AF_2  )   ||\
00084                                             ((__VALUE__) == LL_GPIO_AF_3  )   ||\
00085                                             ((__VALUE__) == LL_GPIO_AF_4  )   ||\
00086                                             ((__VALUE__) == LL_GPIO_AF_5  )   ||\
00087                                             ((__VALUE__) == LL_GPIO_AF_6  )   ||\
00088                                             ((__VALUE__) == LL_GPIO_AF_7  )   ||\
00089                                             ((__VALUE__) == LL_GPIO_AF_8  )   ||\
00090                                             ((__VALUE__) == LL_GPIO_AF_9  )   ||\
00091                                             ((__VALUE__) == LL_GPIO_AF_10 )   ||\
00092                                             ((__VALUE__) == LL_GPIO_AF_11 )   ||\
00093                                             ((__VALUE__) == LL_GPIO_AF_12 )   ||\
00094                                             ((__VALUE__) == LL_GPIO_AF_13 )   ||\
00095                                             ((__VALUE__) == LL_GPIO_AF_14 )   ||\
00096                                             ((__VALUE__) == LL_GPIO_AF_15 ))
00097 /**
00098   * @}
00099   */
00100
00101 /* Private function prototypes -----------------------------------------------*/
00102
00103 /* Exported functions --------------------------------------------------------*/
00104 /** @addtogroup GPIO_LL_Exported_Functions
00105   * @{
00106   */
00107
00108 /** @addtogroup GPIO_LL_EF_Init
00109   * @{
00110   */
00111
00112 /**
00113   * @brief  De-initialize GPIO registers (Registers restored to their default values).
00114   * @param  GPIOx GPIO Port
00115   * @retval An ErrorStatus enumeration value:
00116   *          - SUCCESS: GPIO registers are de-initialized
00117   *          - ERROR:   Wrong GPIO Port
00118   */
00119 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
00120 {
00121   ErrorStatus status = SUCCESS;
00122
00123   /* Check the parameters */
00124   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00125
00126   /* Force and Release reset on clock of GPIOx Port */
00127   if (GPIOx == GPIOA)
00128   {
00129     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA);
00130     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA);
00131   }
00132   else if (GPIOx == GPIOB)
00133   {
00134     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB);
00135     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB);
00136   }
00137   else if (GPIOx == GPIOC)
00138   {
00139     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC);
00140     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC);
00141   }
00142 #if defined(GPIOD)
00143   else if (GPIOx == GPIOD)
00144   {
00145     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD);
00146     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD);
00147   }
00148 #endif /* GPIOD */
00149 #if defined(GPIOE)
00150   else if (GPIOx == GPIOE)
00151   {
00152     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE);
00153     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE);
00154   }
00155 #endif /* GPIOE */
00156 #if defined(GPIOF)
00157   else if (GPIOx == GPIOF)
00158   {
00159     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF);
00160     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF);
00161   }
00162 #endif /* GPIOF */
00163 #if defined(GPIOG)
00164   else if (GPIOx == GPIOG)
00165   {
00166     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOG);
00167     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG);
00168   }
00169 #endif /* GPIOG */
00170 #if defined(GPIOH)
00171   else if (GPIOx == GPIOH)
00172   {
00173     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOH);
00174     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH);
00175   }
00176 #endif /* GPIOH */
00177   else
00178   {
00179     status = ERROR;
00180   }
00181
00182   return (status);
00183 }
00184
00185 /**
00186   * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
00187   * @param  GPIOx GPIO Port
00188   * @param  GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
00189   *         that contains the configuration information for the specified GPIO peripheral.
00190   * @retval An ErrorStatus enumeration value:
00191   *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
00192   *          - ERROR:   Not applicable
00193   */
00194 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
00195 {
00196   uint32_t pinpos     = 0x00000000U;
00197   uint32_t currentpin = 0x00000000U;
00198
00199   /* Check the parameters */
00200   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00201   assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
00202   assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
00203   assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
00204
00205   /* ------------------------- Configure the port pins ---------------- */
00206   /* Initialize  pinpos on first pin set */
00207   pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
00208
00209   /* Configure the port pins */
00210   while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
00211   {
00212     /* Get current io position */
00213     currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
00214
00215     if (currentpin)
00216     {
00217       /* Pin Mode configuration */
00218       LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
00219
00220       if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
00221       {
00222         /* Check Speed mode parameters */
00223         assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
00224
00225         /* Speed mode configuration */
00226         LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
00227       }
00228
00229       /* Pull-up Pull down resistor configuration*/
00230       LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
00231
00232       if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
00233       {
00234         /* Check Alternate parameter */
00235         assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
00236
00237         /* Speed mode configuration */
00238         if (POSITION_VAL(currentpin) < 0x00000008U)
00239         {
00240           LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
00241         }
00242         else
00243         {
00244           LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
00245         }
00246       }
00247     }
00248     pinpos++;
00249   }
00250
00251   if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
00252   {
00253     /* Check Output mode parameters */
00254     assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
00255
00256     /* Output mode configuration*/
00257     LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
00258
00259   }
00260   return (SUCCESS);
00261 }
00262
00263 /**
00264   * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
00265   * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
00266   *                          whose fields will be set to default values.
00267   * @retval None
00268   */
00269
00270 void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
00271 {
00272   /* Reset GPIO init structure parameters values */
00273   GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
00274   GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;
00275   GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;
00276   GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
00277   GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;
00278   GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;
00279 }
00280
00281 /**
00282   * @}
00283   */
00284
00285 /**
00286   * @}
00287   */
00288
00289 /**
00290   * @}
00291   */
00292
00293 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) */
00294
00295 /**
00296   * @}
00297   */
00298
00299 #endif /* USE_FULL_LL_DRIVER */
00300
00301 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_gpio.h Source File

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stm32f3xx_ll_gpio.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_gpio.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of GPIO LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_GPIO_H
00038 #define __STM32F3xx_LL_GPIO_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH)
00052
00053 /** @defgroup GPIO_LL GPIO
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059 /* Private constants ---------------------------------------------------------*/
00060 /* Private macros ------------------------------------------------------------*/
00061 #if defined(USE_FULL_LL_DRIVER)
00062 /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
00063   * @{
00064   */
00065
00066 /**
00067   * @}
00068   */
00069 #endif /*USE_FULL_LL_DRIVER*/
00070
00071 /* Exported types ------------------------------------------------------------*/
00072 #if defined(USE_FULL_LL_DRIVER)
00073 /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
00074   * @{
00075   */
00076
00077 /**
00078   * @brief LL GPIO Init Structure definition
00079   */
00080 typedef struct
00081 {
00082   uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
00083                               This parameter can be any value of @ref GPIO_LL_EC_PIN */
00084
00085   uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
00086                               This parameter can be a value of @ref GPIO_LL_EC_MODE.
00087
00088                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
00089
00090   uint32_t Speed;        /*!< Specifies the speed for the selected pins.
00091                               This parameter can be a value of @ref GPIO_LL_EC_SPEED.
00092
00093                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
00094
00095   uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
00096                               This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
00097
00098                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
00099
00100   uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
00101                               This parameter can be a value of @ref GPIO_LL_EC_PULL.
00102
00103                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
00104
00105   uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
00106                               This parameter can be a value of @ref GPIO_LL_EC_AF.
00107
00108                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
00109 } LL_GPIO_InitTypeDef;
00110
00111 /**
00112   * @}
00113   */
00114 #endif /* USE_FULL_LL_DRIVER */
00115
00116 /* Exported constants --------------------------------------------------------*/
00117 /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
00118   * @{
00119   */
00120
00121 /** @defgroup GPIO_LL_EC_PIN PIN
00122   * @{
00123   */
00124 #define LL_GPIO_PIN_0                      GPIO_BSRR_BS_0 /*!< Select pin 0 */
00125 #define LL_GPIO_PIN_1                      GPIO_BSRR_BS_1 /*!< Select pin 1 */
00126 #define LL_GPIO_PIN_2                      GPIO_BSRR_BS_2 /*!< Select pin 2 */
00127 #define LL_GPIO_PIN_3                      GPIO_BSRR_BS_3 /*!< Select pin 3 */
00128 #define LL_GPIO_PIN_4                      GPIO_BSRR_BS_4 /*!< Select pin 4 */
00129 #define LL_GPIO_PIN_5                      GPIO_BSRR_BS_5 /*!< Select pin 5 */
00130 #define LL_GPIO_PIN_6                      GPIO_BSRR_BS_6 /*!< Select pin 6 */
00131 #define LL_GPIO_PIN_7                      GPIO_BSRR_BS_7 /*!< Select pin 7 */
00132 #define LL_GPIO_PIN_8                      GPIO_BSRR_BS_8 /*!< Select pin 8 */
00133 #define LL_GPIO_PIN_9                      GPIO_BSRR_BS_9 /*!< Select pin 9 */
00134 #define LL_GPIO_PIN_10                     GPIO_BSRR_BS_10 /*!< Select pin 10 */
00135 #define LL_GPIO_PIN_11                     GPIO_BSRR_BS_11 /*!< Select pin 11 */
00136 #define LL_GPIO_PIN_12                     GPIO_BSRR_BS_12 /*!< Select pin 12 */
00137 #define LL_GPIO_PIN_13                     GPIO_BSRR_BS_13 /*!< Select pin 13 */
00138 #define LL_GPIO_PIN_14                     GPIO_BSRR_BS_14 /*!< Select pin 14 */
00139 #define LL_GPIO_PIN_15                     GPIO_BSRR_BS_15 /*!< Select pin 15 */
00140 #define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1  | GPIO_BSRR_BS_2  | \
00141                                            GPIO_BSRR_BS_3  | GPIO_BSRR_BS_4  | GPIO_BSRR_BS_5  | \
00142                                            GPIO_BSRR_BS_6  | GPIO_BSRR_BS_7  | GPIO_BSRR_BS_8  | \
00143                                            GPIO_BSRR_BS_9  | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
00144                                            GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
00145                                            GPIO_BSRR_BS_15) /*!< Select all pins */
00146 /**
00147   * @}
00148   */
00149
00150 /** @defgroup GPIO_LL_EC_MODE Mode
00151   * @{
00152   */
00153 #define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
00154 #define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODER0_0  /*!< Select output mode */
00155 #define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODER0_1  /*!< Select alternate function mode */
00156 #define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODER0    /*!< Select analog mode */
00157 /**
00158   * @}
00159   */
00160
00161 /** @defgroup GPIO_LL_EC_OUTPUT Output Type
00162   * @{
00163   */
00164 #define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
00165 #define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup GPIO_LL_EC_SPEED Output Speed
00171   * @{
00172   */
00173 #define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
00174 #define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
00175 #define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDER_OSPEEDR0   /*!< Select I/O high output speed   */
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
00181   * @{
00182   */
00183 #define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
00184 #define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
00185 #define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup GPIO_LL_EC_AF Alternate Function
00191   * @{
00192   */
00193 #define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
00194 #define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
00195 #define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
00196 #define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
00197 #define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
00198 #define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
00199 #define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
00200 #define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
00201 #define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
00202 #define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
00203 #define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
00204 #define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
00205 #define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
00206 #define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
00207 #define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
00208 #define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
00209 /**
00210   * @}
00211   */
00212
00213 /**
00214   * @}
00215   */
00216
00217 /* Exported macro ------------------------------------------------------------*/
00218 /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
00219   * @{
00220   */
00221
00222 /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
00223   * @{
00224   */
00225
00226 /**
00227   * @brief  Write a value in GPIO register
00228   * @param  __INSTANCE__ GPIO Instance
00229   * @param  __REG__ Register to be written
00230   * @param  __VALUE__ Value to be written in the register
00231   * @retval None
00232   */
00233 #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00234
00235 /**
00236   * @brief  Read a value in GPIO register
00237   * @param  __INSTANCE__ GPIO Instance
00238   * @param  __REG__ Register to be read
00239   * @retval Register value
00240   */
00241 #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00242 /**
00243   * @}
00244   */
00245
00246 /**
00247   * @}
00248   */
00249
00250 /* Exported functions --------------------------------------------------------*/
00251 /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
00252   * @{
00253   */
00254
00255 /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
00256   * @{
00257   */
00258
00259 /**
00260   * @brief  Configure gpio mode for a dedicated pin on dedicated port.
00261   * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
00262   * @note   Warning: only one pin can be passed as parameter.
00263   * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
00264   * @param  GPIOx GPIO Port
00265   * @param  Pin This parameter can be one of the following values:
00266   *         @arg @ref LL_GPIO_PIN_0
00267   *         @arg @ref LL_GPIO_PIN_1
00268   *         @arg @ref LL_GPIO_PIN_2
00269   *         @arg @ref LL_GPIO_PIN_3
00270   *         @arg @ref LL_GPIO_PIN_4
00271   *         @arg @ref LL_GPIO_PIN_5
00272   *         @arg @ref LL_GPIO_PIN_6
00273   *         @arg @ref LL_GPIO_PIN_7
00274   *         @arg @ref LL_GPIO_PIN_8
00275   *         @arg @ref LL_GPIO_PIN_9
00276   *         @arg @ref LL_GPIO_PIN_10
00277   *         @arg @ref LL_GPIO_PIN_11
00278   *         @arg @ref LL_GPIO_PIN_12
00279   *         @arg @ref LL_GPIO_PIN_13
00280   *         @arg @ref LL_GPIO_PIN_14
00281   *         @arg @ref LL_GPIO_PIN_15
00282   * @param  Mode This parameter can be one of the following values:
00283   *         @arg @ref LL_GPIO_MODE_INPUT
00284   *         @arg @ref LL_GPIO_MODE_OUTPUT
00285   *         @arg @ref LL_GPIO_MODE_ALTERNATE
00286   *         @arg @ref LL_GPIO_MODE_ANALOG
00287   * @retval None
00288   */
00289 __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
00290 {
00291   MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
00292 }
00293
00294 /**
00295   * @brief  Return gpio mode for a dedicated pin on dedicated port.
00296   * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
00297   * @note   Warning: only one pin can be passed as parameter.
00298   * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
00299   * @param  GPIOx GPIO Port
00300   * @param  Pin This parameter can be one of the following values:
00301   *         @arg @ref LL_GPIO_PIN_0
00302   *         @arg @ref LL_GPIO_PIN_1
00303   *         @arg @ref LL_GPIO_PIN_2
00304   *         @arg @ref LL_GPIO_PIN_3
00305   *         @arg @ref LL_GPIO_PIN_4
00306   *         @arg @ref LL_GPIO_PIN_5
00307   *         @arg @ref LL_GPIO_PIN_6
00308   *         @arg @ref LL_GPIO_PIN_7
00309   *         @arg @ref LL_GPIO_PIN_8
00310   *         @arg @ref LL_GPIO_PIN_9
00311   *         @arg @ref LL_GPIO_PIN_10
00312   *         @arg @ref LL_GPIO_PIN_11
00313   *         @arg @ref LL_GPIO_PIN_12
00314   *         @arg @ref LL_GPIO_PIN_13
00315   *         @arg @ref LL_GPIO_PIN_14
00316   *         @arg @ref LL_GPIO_PIN_15
00317   * @retval Returned value can be one of the following values:
00318   *         @arg @ref LL_GPIO_MODE_INPUT
00319   *         @arg @ref LL_GPIO_MODE_OUTPUT
00320   *         @arg @ref LL_GPIO_MODE_ALTERNATE
00321   *         @arg @ref LL_GPIO_MODE_ANALOG
00322   */
00323 __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
00324 {
00325   return (uint32_t)(READ_BIT(GPIOx->MODER,
00326                              (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
00327 }
00328
00329 /**
00330   * @brief  Configure gpio output type for several pins on dedicated port.
00331   * @note   Output type as to be set when gpio pin is in output or
00332   *         alternate modes. Possible type are Push-pull or Open-drain.
00333   * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
00334   * @param  GPIOx GPIO Port
00335   * @param  PinMask This parameter can be a combination of the following values:
00336   *         @arg @ref LL_GPIO_PIN_0
00337   *         @arg @ref LL_GPIO_PIN_1
00338   *         @arg @ref LL_GPIO_PIN_2
00339   *         @arg @ref LL_GPIO_PIN_3
00340   *         @arg @ref LL_GPIO_PIN_4
00341   *         @arg @ref LL_GPIO_PIN_5
00342   *         @arg @ref LL_GPIO_PIN_6
00343   *         @arg @ref LL_GPIO_PIN_7
00344   *         @arg @ref LL_GPIO_PIN_8
00345   *         @arg @ref LL_GPIO_PIN_9
00346   *         @arg @ref LL_GPIO_PIN_10
00347   *         @arg @ref LL_GPIO_PIN_11
00348   *         @arg @ref LL_GPIO_PIN_12
00349   *         @arg @ref LL_GPIO_PIN_13
00350   *         @arg @ref LL_GPIO_PIN_14
00351   *         @arg @ref LL_GPIO_PIN_15
00352   *         @arg @ref LL_GPIO_PIN_ALL
00353   * @param  OutputType This parameter can be one of the following values:
00354   *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
00355   *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
00356   * @retval None
00357   */
00358 __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
00359 {
00360   MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
00361 }
00362
00363 /**
00364   * @brief  Return gpio output type for several pins on dedicated port.
00365   * @note   Output type as to be set when gpio pin is in output or
00366   *         alternate modes. Possible type are Push-pull or Open-drain.
00367   * @note   Warning: only one pin can be passed as parameter.
00368   * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
00369   * @param  GPIOx GPIO Port
00370   * @param  Pin This parameter can be one of the following values:
00371   *         @arg @ref LL_GPIO_PIN_0
00372   *         @arg @ref LL_GPIO_PIN_1
00373   *         @arg @ref LL_GPIO_PIN_2
00374   *         @arg @ref LL_GPIO_PIN_3
00375   *         @arg @ref LL_GPIO_PIN_4
00376   *         @arg @ref LL_GPIO_PIN_5
00377   *         @arg @ref LL_GPIO_PIN_6
00378   *         @arg @ref LL_GPIO_PIN_7
00379   *         @arg @ref LL_GPIO_PIN_8
00380   *         @arg @ref LL_GPIO_PIN_9
00381   *         @arg @ref LL_GPIO_PIN_10
00382   *         @arg @ref LL_GPIO_PIN_11
00383   *         @arg @ref LL_GPIO_PIN_12
00384   *         @arg @ref LL_GPIO_PIN_13
00385   *         @arg @ref LL_GPIO_PIN_14
00386   *         @arg @ref LL_GPIO_PIN_15
00387   *         @arg @ref LL_GPIO_PIN_ALL
00388   * @retval Returned value can be one of the following values:
00389   *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
00390   *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
00391   */
00392 __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
00393 {
00394   return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
00395 }
00396
00397 /**
00398   * @brief  Configure gpio speed for a dedicated pin on dedicated port.
00399   * @note   I/O speed can be Low, Medium, Fast or High speed.
00400   * @note   Warning: only one pin can be passed as parameter.
00401   * @note   Refer to datasheet for frequency specifications and the power
00402   *         supply and load conditions for each speed.
00403   * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
00404   * @param  GPIOx GPIO Port
00405   * @param  Pin This parameter can be one of the following values:
00406   *         @arg @ref LL_GPIO_PIN_0
00407   *         @arg @ref LL_GPIO_PIN_1
00408   *         @arg @ref LL_GPIO_PIN_2
00409   *         @arg @ref LL_GPIO_PIN_3
00410   *         @arg @ref LL_GPIO_PIN_4
00411   *         @arg @ref LL_GPIO_PIN_5
00412   *         @arg @ref LL_GPIO_PIN_6
00413   *         @arg @ref LL_GPIO_PIN_7
00414   *         @arg @ref LL_GPIO_PIN_8
00415   *         @arg @ref LL_GPIO_PIN_9
00416   *         @arg @ref LL_GPIO_PIN_10
00417   *         @arg @ref LL_GPIO_PIN_11
00418   *         @arg @ref LL_GPIO_PIN_12
00419   *         @arg @ref LL_GPIO_PIN_13
00420   *         @arg @ref LL_GPIO_PIN_14
00421   *         @arg @ref LL_GPIO_PIN_15
00422   * @param  Speed This parameter can be one of the following values:
00423   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
00424   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
00425   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
00426   * @retval None
00427   */
00428 __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
00429 {
00430   MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
00431              (Speed << (POSITION_VAL(Pin) * 2U)));
00432 }
00433
00434 /**
00435   * @brief  Return gpio speed for a dedicated pin on dedicated port.
00436   * @note   I/O speed can be Low, Medium, Fast or High speed.
00437   * @note   Warning: only one pin can be passed as parameter.
00438   * @note   Refer to datasheet for frequency specifications and the power
00439   *         supply and load conditions for each speed.
00440   * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
00441   * @param  GPIOx GPIO Port
00442   * @param  Pin This parameter can be one of the following values:
00443   *         @arg @ref LL_GPIO_PIN_0
00444   *         @arg @ref LL_GPIO_PIN_1
00445   *         @arg @ref LL_GPIO_PIN_2
00446   *         @arg @ref LL_GPIO_PIN_3
00447   *         @arg @ref LL_GPIO_PIN_4
00448   *         @arg @ref LL_GPIO_PIN_5
00449   *         @arg @ref LL_GPIO_PIN_6
00450   *         @arg @ref LL_GPIO_PIN_7
00451   *         @arg @ref LL_GPIO_PIN_8
00452   *         @arg @ref LL_GPIO_PIN_9
00453   *         @arg @ref LL_GPIO_PIN_10
00454   *         @arg @ref LL_GPIO_PIN_11
00455   *         @arg @ref LL_GPIO_PIN_12
00456   *         @arg @ref LL_GPIO_PIN_13
00457   *         @arg @ref LL_GPIO_PIN_14
00458   *         @arg @ref LL_GPIO_PIN_15
00459   * @retval Returned value can be one of the following values:
00460   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
00461   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
00462   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
00463   */
00464 __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
00465 {
00466   return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
00467                              (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
00468 }
00469
00470 /**
00471   * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
00472   * @note   Warning: only one pin can be passed as parameter.
00473   * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
00474   * @param  GPIOx GPIO Port
00475   * @param  Pin This parameter can be one of the following values:
00476   *         @arg @ref LL_GPIO_PIN_0
00477   *         @arg @ref LL_GPIO_PIN_1
00478   *         @arg @ref LL_GPIO_PIN_2
00479   *         @arg @ref LL_GPIO_PIN_3
00480   *         @arg @ref LL_GPIO_PIN_4
00481   *         @arg @ref LL_GPIO_PIN_5
00482   *         @arg @ref LL_GPIO_PIN_6
00483   *         @arg @ref LL_GPIO_PIN_7
00484   *         @arg @ref LL_GPIO_PIN_8
00485   *         @arg @ref LL_GPIO_PIN_9
00486   *         @arg @ref LL_GPIO_PIN_10
00487   *         @arg @ref LL_GPIO_PIN_11
00488   *         @arg @ref LL_GPIO_PIN_12
00489   *         @arg @ref LL_GPIO_PIN_13
00490   *         @arg @ref LL_GPIO_PIN_14
00491   *         @arg @ref LL_GPIO_PIN_15
00492   * @param  Pull This parameter can be one of the following values:
00493   *         @arg @ref LL_GPIO_PULL_NO
00494   *         @arg @ref LL_GPIO_PULL_UP
00495   *         @arg @ref LL_GPIO_PULL_DOWN
00496   * @retval None
00497   */
00498 __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
00499 {
00500   MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
00501 }
00502
00503 /**
00504   * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
00505   * @note   Warning: only one pin can be passed as parameter.
00506   * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
00507   * @param  GPIOx GPIO Port
00508   * @param  Pin This parameter can be one of the following values:
00509   *         @arg @ref LL_GPIO_PIN_0
00510   *         @arg @ref LL_GPIO_PIN_1
00511   *         @arg @ref LL_GPIO_PIN_2
00512   *         @arg @ref LL_GPIO_PIN_3
00513   *         @arg @ref LL_GPIO_PIN_4
00514   *         @arg @ref LL_GPIO_PIN_5
00515   *         @arg @ref LL_GPIO_PIN_6
00516   *         @arg @ref LL_GPIO_PIN_7
00517   *         @arg @ref LL_GPIO_PIN_8
00518   *         @arg @ref LL_GPIO_PIN_9
00519   *         @arg @ref LL_GPIO_PIN_10
00520   *         @arg @ref LL_GPIO_PIN_11
00521   *         @arg @ref LL_GPIO_PIN_12
00522   *         @arg @ref LL_GPIO_PIN_13
00523   *         @arg @ref LL_GPIO_PIN_14
00524   *         @arg @ref LL_GPIO_PIN_15
00525   * @retval Returned value can be one of the following values:
00526   *         @arg @ref LL_GPIO_PULL_NO
00527   *         @arg @ref LL_GPIO_PULL_UP
00528   *         @arg @ref LL_GPIO_PULL_DOWN
00529   */
00530 __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
00531 {
00532   return (uint32_t)(READ_BIT(GPIOx->PUPDR,
00533                              (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
00534 }
00535
00536 /**
00537   * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
00538   * @note   Possible values are from AF0 to AF15 depending on target.
00539   * @note   Warning: only one pin can be passed as parameter.
00540   * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
00541   * @param  GPIOx GPIO Port
00542   * @param  Pin This parameter can be one of the following values:
00543   *         @arg @ref LL_GPIO_PIN_0
00544   *         @arg @ref LL_GPIO_PIN_1
00545   *         @arg @ref LL_GPIO_PIN_2
00546   *         @arg @ref LL_GPIO_PIN_3
00547   *         @arg @ref LL_GPIO_PIN_4
00548   *         @arg @ref LL_GPIO_PIN_5
00549   *         @arg @ref LL_GPIO_PIN_6
00550   *         @arg @ref LL_GPIO_PIN_7
00551   * @param  Alternate This parameter can be one of the following values:
00552   *         @arg @ref LL_GPIO_AF_0
00553   *         @arg @ref LL_GPIO_AF_1
00554   *         @arg @ref LL_GPIO_AF_2
00555   *         @arg @ref LL_GPIO_AF_3
00556   *         @arg @ref LL_GPIO_AF_4
00557   *         @arg @ref LL_GPIO_AF_5
00558   *         @arg @ref LL_GPIO_AF_6
00559   *         @arg @ref LL_GPIO_AF_7
00560   *         @arg @ref LL_GPIO_AF_8
00561   *         @arg @ref LL_GPIO_AF_9
00562   *         @arg @ref LL_GPIO_AF_10
00563   *         @arg @ref LL_GPIO_AF_11
00564   *         @arg @ref LL_GPIO_AF_12
00565   *         @arg @ref LL_GPIO_AF_13
00566   *         @arg @ref LL_GPIO_AF_14
00567   *         @arg @ref LL_GPIO_AF_15
00568   * @retval None
00569   */
00570 __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
00571 {
00572   MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U)),
00573              (Alternate << (POSITION_VAL(Pin) * 4U)));
00574 }
00575
00576 /**
00577   * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
00578   * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
00579   * @param  GPIOx GPIO Port
00580   * @param  Pin This parameter can be one of the following values:
00581   *         @arg @ref LL_GPIO_PIN_0
00582   *         @arg @ref LL_GPIO_PIN_1
00583   *         @arg @ref LL_GPIO_PIN_2
00584   *         @arg @ref LL_GPIO_PIN_3
00585   *         @arg @ref LL_GPIO_PIN_4
00586   *         @arg @ref LL_GPIO_PIN_5
00587   *         @arg @ref LL_GPIO_PIN_6
00588   *         @arg @ref LL_GPIO_PIN_7
00589   * @retval Returned value can be one of the following values:
00590   *         @arg @ref LL_GPIO_AF_0
00591   *         @arg @ref LL_GPIO_AF_1
00592   *         @arg @ref LL_GPIO_AF_2
00593   *         @arg @ref LL_GPIO_AF_3
00594   *         @arg @ref LL_GPIO_AF_4
00595   *         @arg @ref LL_GPIO_AF_5
00596   *         @arg @ref LL_GPIO_AF_6
00597   *         @arg @ref LL_GPIO_AF_7
00598   *         @arg @ref LL_GPIO_AF_8
00599   *         @arg @ref LL_GPIO_AF_9
00600   *         @arg @ref LL_GPIO_AF_10
00601   *         @arg @ref LL_GPIO_AF_11
00602   *         @arg @ref LL_GPIO_AF_12
00603   *         @arg @ref LL_GPIO_AF_13
00604   *         @arg @ref LL_GPIO_AF_14
00605   *         @arg @ref LL_GPIO_AF_15
00606   */
00607 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
00608 {
00609   return (uint32_t)(READ_BIT(GPIOx->AFR[0],
00610                              (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
00611 }
00612
00613 /**
00614   * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
00615   * @note   Possible values are from AF0 to AF15 depending on target.
00616   * @note   Warning: only one pin can be passed as parameter.
00617   * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
00618   * @param  GPIOx GPIO Port
00619   * @param  Pin This parameter can be one of the following values:
00620   *         @arg @ref LL_GPIO_PIN_8
00621   *         @arg @ref LL_GPIO_PIN_9
00622   *         @arg @ref LL_GPIO_PIN_10
00623   *         @arg @ref LL_GPIO_PIN_11
00624   *         @arg @ref LL_GPIO_PIN_12
00625   *         @arg @ref LL_GPIO_PIN_13
00626   *         @arg @ref LL_GPIO_PIN_14
00627   *         @arg @ref LL_GPIO_PIN_15
00628   * @param  Alternate This parameter can be one of the following values:
00629   *         @arg @ref LL_GPIO_AF_0
00630   *         @arg @ref LL_GPIO_AF_1
00631   *         @arg @ref LL_GPIO_AF_2
00632   *         @arg @ref LL_GPIO_AF_3
00633   *         @arg @ref LL_GPIO_AF_4
00634   *         @arg @ref LL_GPIO_AF_5
00635   *         @arg @ref LL_GPIO_AF_6
00636   *         @arg @ref LL_GPIO_AF_7
00637   *         @arg @ref LL_GPIO_AF_8
00638   *         @arg @ref LL_GPIO_AF_9
00639   *         @arg @ref LL_GPIO_AF_10
00640   *         @arg @ref LL_GPIO_AF_11
00641   *         @arg @ref LL_GPIO_AF_12
00642   *         @arg @ref LL_GPIO_AF_13
00643   *         @arg @ref LL_GPIO_AF_14
00644   *         @arg @ref LL_GPIO_AF_15
00645   * @retval None
00646   */
00647 __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
00648 {
00649   MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U)),
00650              (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
00651 }
00652
00653 /**
00654   * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
00655   * @note   Possible values are from AF0 to AF15 depending on target.
00656   * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
00657   * @param  GPIOx GPIO Port
00658   * @param  Pin This parameter can be one of the following values:
00659   *         @arg @ref LL_GPIO_PIN_8
00660   *         @arg @ref LL_GPIO_PIN_9
00661   *         @arg @ref LL_GPIO_PIN_10
00662   *         @arg @ref LL_GPIO_PIN_11
00663   *         @arg @ref LL_GPIO_PIN_12
00664   *         @arg @ref LL_GPIO_PIN_13
00665   *         @arg @ref LL_GPIO_PIN_14
00666   *         @arg @ref LL_GPIO_PIN_15
00667   * @retval Returned value can be one of the following values:
00668   *         @arg @ref LL_GPIO_AF_0
00669   *         @arg @ref LL_GPIO_AF_1
00670   *         @arg @ref LL_GPIO_AF_2
00671   *         @arg @ref LL_GPIO_AF_3
00672   *         @arg @ref LL_GPIO_AF_4
00673   *         @arg @ref LL_GPIO_AF_5
00674   *         @arg @ref LL_GPIO_AF_6
00675   *         @arg @ref LL_GPIO_AF_7
00676   *         @arg @ref LL_GPIO_AF_8
00677   *         @arg @ref LL_GPIO_AF_9
00678   *         @arg @ref LL_GPIO_AF_10
00679   *         @arg @ref LL_GPIO_AF_11
00680   *         @arg @ref LL_GPIO_AF_12
00681   *         @arg @ref LL_GPIO_AF_13
00682   *         @arg @ref LL_GPIO_AF_14
00683   *         @arg @ref LL_GPIO_AF_15
00684   */
00685 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
00686 {
00687   return (uint32_t)(READ_BIT(GPIOx->AFR[1],
00688                              (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
00689 }
00690
00691
00692 /**
00693   * @brief  Lock configuration of several pins for a dedicated port.
00694   * @note   When the lock sequence has been applied on a port bit, the
00695   *         value of this port bit can no longer be modified until the
00696   *         next reset.
00697   * @note   Each lock bit freezes a specific configuration register
00698   *         (control and alternate function registers).
00699   * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
00700   * @param  GPIOx GPIO Port
00701   * @param  PinMask This parameter can be a combination of the following values:
00702   *         @arg @ref LL_GPIO_PIN_0
00703   *         @arg @ref LL_GPIO_PIN_1
00704   *         @arg @ref LL_GPIO_PIN_2
00705   *         @arg @ref LL_GPIO_PIN_3
00706   *         @arg @ref LL_GPIO_PIN_4
00707   *         @arg @ref LL_GPIO_PIN_5
00708   *         @arg @ref LL_GPIO_PIN_6
00709   *         @arg @ref LL_GPIO_PIN_7
00710   *         @arg @ref LL_GPIO_PIN_8
00711   *         @arg @ref LL_GPIO_PIN_9
00712   *         @arg @ref LL_GPIO_PIN_10
00713   *         @arg @ref LL_GPIO_PIN_11
00714   *         @arg @ref LL_GPIO_PIN_12
00715   *         @arg @ref LL_GPIO_PIN_13
00716   *         @arg @ref LL_GPIO_PIN_14
00717   *         @arg @ref LL_GPIO_PIN_15
00718   *         @arg @ref LL_GPIO_PIN_ALL
00719   * @retval None
00720   */
00721 __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00722 {
00723   __IO uint32_t temp;
00724   WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
00725   WRITE_REG(GPIOx->LCKR, PinMask);
00726   WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
00727   temp = READ_REG(GPIOx->LCKR);
00728   (void) temp;
00729 }
00730
00731 /**
00732   * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
00733   * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
00734   * @param  GPIOx GPIO Port
00735   * @param  PinMask This parameter can be a combination of the following values:
00736   *         @arg @ref LL_GPIO_PIN_0
00737   *         @arg @ref LL_GPIO_PIN_1
00738   *         @arg @ref LL_GPIO_PIN_2
00739   *         @arg @ref LL_GPIO_PIN_3
00740   *         @arg @ref LL_GPIO_PIN_4
00741   *         @arg @ref LL_GPIO_PIN_5
00742   *         @arg @ref LL_GPIO_PIN_6
00743   *         @arg @ref LL_GPIO_PIN_7
00744   *         @arg @ref LL_GPIO_PIN_8
00745   *         @arg @ref LL_GPIO_PIN_9
00746   *         @arg @ref LL_GPIO_PIN_10
00747   *         @arg @ref LL_GPIO_PIN_11
00748   *         @arg @ref LL_GPIO_PIN_12
00749   *         @arg @ref LL_GPIO_PIN_13
00750   *         @arg @ref LL_GPIO_PIN_14
00751   *         @arg @ref LL_GPIO_PIN_15
00752   *         @arg @ref LL_GPIO_PIN_ALL
00753   * @retval State of bit (1 or 0).
00754   */
00755 __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00756 {
00757   return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
00758 }
00759
00760 /**
00761   * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
00762   * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
00763   * @param  GPIOx GPIO Port
00764   * @retval State of bit (1 or 0).
00765   */
00766 __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
00767 {
00768   return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
00769 }
00770
00771 /**
00772   * @}
00773   */
00774
00775 /** @defgroup GPIO_LL_EF_Data_Access Data Access
00776   * @{
00777   */
00778
00779 /**
00780   * @brief  Return full input data register value for a dedicated port.
00781   * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
00782   * @param  GPIOx GPIO Port
00783   * @retval Input data register value of port
00784   */
00785 __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
00786 {
00787   return (uint32_t)(READ_REG(GPIOx->IDR));
00788 }
00789
00790 /**
00791   * @brief  Return if input data level for several pins of dedicated port is high or low.
00792   * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
00793   * @param  GPIOx GPIO Port
00794   * @param  PinMask This parameter can be a combination of the following values:
00795   *         @arg @ref LL_GPIO_PIN_0
00796   *         @arg @ref LL_GPIO_PIN_1
00797   *         @arg @ref LL_GPIO_PIN_2
00798   *         @arg @ref LL_GPIO_PIN_3
00799   *         @arg @ref LL_GPIO_PIN_4
00800   *         @arg @ref LL_GPIO_PIN_5
00801   *         @arg @ref LL_GPIO_PIN_6
00802   *         @arg @ref LL_GPIO_PIN_7
00803   *         @arg @ref LL_GPIO_PIN_8
00804   *         @arg @ref LL_GPIO_PIN_9
00805   *         @arg @ref LL_GPIO_PIN_10
00806   *         @arg @ref LL_GPIO_PIN_11
00807   *         @arg @ref LL_GPIO_PIN_12
00808   *         @arg @ref LL_GPIO_PIN_13
00809   *         @arg @ref LL_GPIO_PIN_14
00810   *         @arg @ref LL_GPIO_PIN_15
00811   *         @arg @ref LL_GPIO_PIN_ALL
00812   * @retval State of bit (1 or 0).
00813   */
00814 __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00815 {
00816   return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
00817 }
00818
00819 /**
00820   * @brief  Write output data register for the port.
00821   * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
00822   * @param  GPIOx GPIO Port
00823   * @param  PortValue Level value for each pin of the port
00824   * @retval None
00825   */
00826 __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
00827 {
00828   WRITE_REG(GPIOx->ODR, PortValue);
00829 }
00830
00831 /**
00832   * @brief  Return full output data register value for a dedicated port.
00833   * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
00834   * @param  GPIOx GPIO Port
00835   * @retval Output data register value of port
00836   */
00837 __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
00838 {
00839   return (uint32_t)(READ_REG(GPIOx->ODR));
00840 }
00841
00842 /**
00843   * @brief  Return if input data level for several pins of dedicated port is high or low.
00844   * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
00845   * @param  GPIOx GPIO Port
00846   * @param  PinMask This parameter can be a combination of the following values:
00847   *         @arg @ref LL_GPIO_PIN_0
00848   *         @arg @ref LL_GPIO_PIN_1
00849   *         @arg @ref LL_GPIO_PIN_2
00850   *         @arg @ref LL_GPIO_PIN_3
00851   *         @arg @ref LL_GPIO_PIN_4
00852   *         @arg @ref LL_GPIO_PIN_5
00853   *         @arg @ref LL_GPIO_PIN_6
00854   *         @arg @ref LL_GPIO_PIN_7
00855   *         @arg @ref LL_GPIO_PIN_8
00856   *         @arg @ref LL_GPIO_PIN_9
00857   *         @arg @ref LL_GPIO_PIN_10
00858   *         @arg @ref LL_GPIO_PIN_11
00859   *         @arg @ref LL_GPIO_PIN_12
00860   *         @arg @ref LL_GPIO_PIN_13
00861   *         @arg @ref LL_GPIO_PIN_14
00862   *         @arg @ref LL_GPIO_PIN_15
00863   *         @arg @ref LL_GPIO_PIN_ALL
00864   * @retval State of bit (1 or 0).
00865   */
00866 __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00867 {
00868   return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
00869 }
00870
00871 /**
00872   * @brief  Set several pins to high level on dedicated gpio port.
00873   * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
00874   * @param  GPIOx GPIO Port
00875   * @param  PinMask This parameter can be a combination of the following values:
00876   *         @arg @ref LL_GPIO_PIN_0
00877   *         @arg @ref LL_GPIO_PIN_1
00878   *         @arg @ref LL_GPIO_PIN_2
00879   *         @arg @ref LL_GPIO_PIN_3
00880   *         @arg @ref LL_GPIO_PIN_4
00881   *         @arg @ref LL_GPIO_PIN_5
00882   *         @arg @ref LL_GPIO_PIN_6
00883   *         @arg @ref LL_GPIO_PIN_7
00884   *         @arg @ref LL_GPIO_PIN_8
00885   *         @arg @ref LL_GPIO_PIN_9
00886   *         @arg @ref LL_GPIO_PIN_10
00887   *         @arg @ref LL_GPIO_PIN_11
00888   *         @arg @ref LL_GPIO_PIN_12
00889   *         @arg @ref LL_GPIO_PIN_13
00890   *         @arg @ref LL_GPIO_PIN_14
00891   *         @arg @ref LL_GPIO_PIN_15
00892   *         @arg @ref LL_GPIO_PIN_ALL
00893   * @retval None
00894   */
00895 __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00896 {
00897   WRITE_REG(GPIOx->BSRR, PinMask);
00898 }
00899
00900 /**
00901   * @brief  Set several pins to low level on dedicated gpio port.
00902   * @rmtoll BRR          BRy           LL_GPIO_ResetOutputPin
00903   * @param  GPIOx GPIO Port
00904   * @param  PinMask This parameter can be a combination of the following values:
00905   *         @arg @ref LL_GPIO_PIN_0
00906   *         @arg @ref LL_GPIO_PIN_1
00907   *         @arg @ref LL_GPIO_PIN_2
00908   *         @arg @ref LL_GPIO_PIN_3
00909   *         @arg @ref LL_GPIO_PIN_4
00910   *         @arg @ref LL_GPIO_PIN_5
00911   *         @arg @ref LL_GPIO_PIN_6
00912   *         @arg @ref LL_GPIO_PIN_7
00913   *         @arg @ref LL_GPIO_PIN_8
00914   *         @arg @ref LL_GPIO_PIN_9
00915   *         @arg @ref LL_GPIO_PIN_10
00916   *         @arg @ref LL_GPIO_PIN_11
00917   *         @arg @ref LL_GPIO_PIN_12
00918   *         @arg @ref LL_GPIO_PIN_13
00919   *         @arg @ref LL_GPIO_PIN_14
00920   *         @arg @ref LL_GPIO_PIN_15
00921   *         @arg @ref LL_GPIO_PIN_ALL
00922   * @retval None
00923   */
00924 __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00925 {
00926   WRITE_REG(GPIOx->BRR, PinMask);
00927 }
00928
00929 /**
00930   * @brief  Toggle data value for several pin of dedicated port.
00931   * @rmtoll ODR          ODy           LL_GPIO_TogglePin
00932   * @param  GPIOx GPIO Port
00933   * @param  PinMask This parameter can be a combination of the following values:
00934   *         @arg @ref LL_GPIO_PIN_0
00935   *         @arg @ref LL_GPIO_PIN_1
00936   *         @arg @ref LL_GPIO_PIN_2
00937   *         @arg @ref LL_GPIO_PIN_3
00938   *         @arg @ref LL_GPIO_PIN_4
00939   *         @arg @ref LL_GPIO_PIN_5
00940   *         @arg @ref LL_GPIO_PIN_6
00941   *         @arg @ref LL_GPIO_PIN_7
00942   *         @arg @ref LL_GPIO_PIN_8
00943   *         @arg @ref LL_GPIO_PIN_9
00944   *         @arg @ref LL_GPIO_PIN_10
00945   *         @arg @ref LL_GPIO_PIN_11
00946   *         @arg @ref LL_GPIO_PIN_12
00947   *         @arg @ref LL_GPIO_PIN_13
00948   *         @arg @ref LL_GPIO_PIN_14
00949   *         @arg @ref LL_GPIO_PIN_15
00950   *         @arg @ref LL_GPIO_PIN_ALL
00951   * @retval None
00952   */
00953 __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00954 {
00955   WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
00956 }
00957
00958 /**
00959   * @}
00960   */
00961
00962 #if defined(USE_FULL_LL_DRIVER)
00963 /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
00964   * @{
00965   */
00966
00967 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
00968 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
00969 void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
00970
00971 /**
00972   * @}
00973   */
00974 #endif /* USE_FULL_LL_DRIVER */
00975
00976 /**
00977   * @}
00978   */
00979
00980 /**
00981   * @}
00982   */
00983
00984 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) */
00985 /**
00986   * @}
00987   */
00988
00989 #ifdef __cplusplus
00990 }
00991 #endif
00992
00993 #endif /* __STM32F3xx_LL_GPIO_H */
00994
00995 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_hrtim.c Source File

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stm32f3xx_ll_hrtim.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_hrtim.c
00004   * @author  MCD Application Team
00005   * @brief   HRTIM LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 #if defined(USE_FULL_LL_DRIVER)
00036
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f3xx_ll_hrtim.h"
00039 #include "stm32f3xx_ll_bus.h"
00040
00041 #ifdef  USE_FULL_ASSERT
00042 #include "stm32_assert.h"
00043 #else
00044 #define assert_param(expr) ((void)0U)
00045 #endif
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined (HRTIM1)
00052
00053 /** @addtogroup HRTIM_LL
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059 /* Private constants ---------------------------------------------------------*/
00060 /* Private macros ------------------------------------------------------------*/
00061 /* Private function prototypes -----------------------------------------------*/
00062 /* Exported functions --------------------------------------------------------*/
00063 /** @addtogroup HRTIM_LL_Exported_Functions
00064   * @{
00065   */
00066 /**
00067   * @brief  Set HRTIM instance registers to their reset values.
00068   * @param  HRTIMx High Resolution Timer instance
00069   * @retval ErrorStatus enumeration value:
00070   *          - SUCCESS: HRTIMx registers are de-initialized
00071   *          - ERROR: invalid HRTIMx instance
00072   */
00073 ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx)
00074 {
00075   ErrorStatus result = SUCCESS;
00076
00077   /* Check the parameters */
00078   assert_param(IS_HRTIM_ALL_INSTANCE(HRTIMx));
00079
00080   LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_HRTIM1);
00081   LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_HRTIM1);
00082
00083   return result;
00084 }
00085 /**
00086   * @}
00087   */
00088
00089 /**
00090   * @}
00091   */
00092
00093 #endif /* HRTIM1 */
00094
00095 /**
00096   * @}
00097   */
00098
00099 #endif /* USE_FULL_LL_DRIVER */
00100
00101 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_hrtim.h Source File

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stm32f3xx_ll_hrtim.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_hrtim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of HRTIM LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_HRTIM_H
00038 #define __STM32F3xx_LL_HRTIM_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined (HRTIM1)
00052
00053 /** @defgroup HRTIM_LL HRTIM
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059 /** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables
00060   * @{
00061   */
00062 static const uint16_t REG_OFFSET_TAB_TIMER[] =
00063 {
00064   0x00U,   /* 0: MASTER  */
00065   0x80U,   /* 1: TIMER A */
00066   0x100U,  /* 2: TIMER B  */
00067   0x180U,  /* 3: TIMER C */
00068   0x200U,  /* 4: TIMER D  */
00069   0x280U,  /* 5: TIMER E */
00070 };
00071
00072 static const uint8_t REG_OFFSET_TAB_ADCxR[] =
00073 {
00074   0x00U,   /* 0: HRTIM_ADC1R */
00075   0x04U,   /* 1: HRTIM_ADC2R */
00076   0x08U,   /* 2: HRTIM_ADC3R */
00077   0x0CU,   /* 3: HRTIM_ADC4R */
00078 };
00079
00080 static const uint16_t REG_OFFSET_TAB_SETxR[] =
00081 {
00082   0x00U,   /* 0: TA1  */
00083   0x08U,   /* 1: TA2 */
00084   0x80U,   /* 2: TB1  */
00085   0x88U,   /* 3: TB2 */
00086   0x100U,  /* 4: TC1  */
00087   0x108U,  /* 5: TC2 */
00088   0x180U,  /* 6: TD1  */
00089   0x188U,  /* 7: TD2 */
00090   0x200U,  /* 8: TE1  */
00091   0x208U   /* 9: TE2 */
00092 };
00093
00094 static const uint16_t REG_OFFSET_TAB_OUTxR[] =
00095 {
00096   0x00U,   /* 0: TA1  */
00097   0x00U,   /* 1: TA2 */
00098   0x80U,   /* 2: TB1  */
00099   0x80U,   /* 3: TB2 */
00100   0x100U,  /* 4: TC1  */
00101   0x100U,  /* 5: TC2 */
00102   0x180U,  /* 6: TD1  */
00103   0x180U,  /* 7: TD2 */
00104   0x200U,  /* 8: TE1  */
00105   0x200U   /* 9: TE2 */
00106 };
00107
00108
00109 static const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] =
00110 {
00111   0x04U,   /* 0: LL_HRTIM_OUT_LEVEL_INACTIVE  */
00112   0x00U    /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE  */
00113 };
00114
00115 static const uint8_t REG_OFFSET_TAB_EECR[] =
00116 {
00117   0x00U, /* LL_HRTIM_EVENT_1 */
00118   0x00U, /* LL_HRTIM_EVENT_2 */
00119   0x00U, /* LL_HRTIM_EVENT_3 */
00120   0x00U, /* LL_HRTIM_EVENT_4 */
00121   0x00U, /* LL_HRTIM_EVENT_5 */
00122   0x04U, /* LL_HRTIM_EVENT_6 */
00123   0x04U, /* LL_HRTIM_EVENT_7 */
00124   0x04U, /* LL_HRTIM_EVENT_8 */
00125   0x04U, /* LL_HRTIM_EVENT_9 */
00126   0x04U  /* LL_HRTIM_EVENT_10 */
00127 };
00128
00129 static const uint8_t REG_OFFSET_TAB_FLTINR[] =
00130 {
00131   0x00U, /* LL_HRTIM_FAULT_1 */
00132   0x00U, /* LL_HRTIM_FAULT_2 */
00133   0x00U, /* LL_HRTIM_FAULT_3 */
00134   0x00U, /* LL_HRTIM_FAULT_4 */
00135   0x04U  /* LL_HRTIM_FAULT_5 */
00136 };
00137
00138 static const uint32_t REG_MASK_TAB_UPDATETRIG[] =
00139 {
00140   0x20000000U,  /* 0: MASTER  */
00141   0x01FE0000U,  /* 1: TIMER A */
00142   0x01FE0000U,  /* 2: TIMER B */
00143   0x01FE0000U,  /* 3: TIMER C */
00144   0x01FE0000U,  /* 4: TIMER D */
00145   0x01FE0000U,  /* 5: TIMER E */
00146 };
00147
00148 static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] =
00149 {
00150   12U, /* 0: MASTER  */
00151   0U,  /* 1: TIMER A */
00152   0U,  /* 2: TIMER B  */
00153   0U,  /* 3: TIMER C */
00154   0U,  /* 4: TIMER D  */
00155   0U,  /* 5: TIMER E */
00156 };
00157
00158 static const uint8_t REG_SHIFT_TAB_EExSRC[] =
00159 {
00160   0U,  /* LL_HRTIM_EVENT_1 */
00161   6U,  /* LL_HRTIM_EVENT_2 */
00162   12U, /* LL_HRTIM_EVENT_3 */
00163   18U, /* LL_HRTIM_EVENT_4 */
00164   24U, /* LL_HRTIM_EVENT_5 */
00165   0U,  /* LL_HRTIM_EVENT_6 */
00166   6U,  /* LL_HRTIM_EVENT_7 */
00167   12U, /* LL_HRTIM_EVENT_8 */
00168   18U, /* LL_HRTIM_EVENT_9 */
00169   24U  /* LL_HRTIM_EVENT_10 */
00170 };
00171
00172 static const uint32_t REG_MASK_TAB_UPDATEGATING[] =
00173 {
00174   HRTIM_MCR_BRSTDMA,   /* 0: MASTER  */
00175   HRTIM_TIMCR_UPDGAT,  /* 1: TIMER A */
00176   HRTIM_TIMCR_UPDGAT,  /* 2: TIMER B  */
00177   HRTIM_TIMCR_UPDGAT,  /* 3: TIMER C */
00178   HRTIM_TIMCR_UPDGAT,  /* 4: TIMER D  */
00179   HRTIM_TIMCR_UPDGAT,  /* 5: TIMER E */
00180 };
00181
00182 static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] =
00183 {
00184   2U, /* 0: MASTER  */
00185   0U, /* 1: TIMER A */
00186   0U, /* 2: TIMER B  */
00187   0U, /* 3: TIMER C */
00188   0U, /* 4: TIMER D  */
00189   0U, /* 5: TIMER E */
00190 };
00191
00192 static const uint8_t REG_SHIFT_TAB_OUTxR[] =
00193 {
00194   0U,  /* 0: TA1  */
00195   16U, /* 1: TA2 */
00196   0U,  /* 2: TB1  */
00197   16U, /* 3: TB2 */
00198   0U,  /* 4: TC1  */
00199   16U, /* 5: TC2 */
00200   0U,  /* 6: TD1  */
00201   16U, /* 7: TD2 */
00202   0U,  /* 8: TE1  */
00203   16U  /* 9: TE2 */
00204 };
00205
00206 static const uint8_t REG_SHIFT_TAB_OxSTAT[] =
00207 {
00208   0U,  /* 0: TA1  */
00209   1U,  /* 1: TA2 */
00210   0U,  /* 2: TB1  */
00211   1U,  /* 3: TB2 */
00212   0U,  /* 4: TC1  */
00213   1U,  /* 5: TC2 */
00214   0U,  /* 6: TD1  */
00215   1U,  /* 7: TD2 */
00216   0U,  /* 8: TE1  */
00217   1U   /* 9: TE2 */
00218 };
00219
00220 static const uint8_t REG_SHIFT_TAB_FLTxE[] =
00221 {
00222   0U,  /* LL_HRTIM_FAULT_1 */
00223   8U,  /* LL_HRTIM_FAULT_2 */
00224   16U, /* LL_HRTIM_FAULT_3 */
00225   24U, /* LL_HRTIM_FAULT_4 */
00226   0U   /* LL_HRTIM_FAULT_5 */
00227 };
00228
00229 /**
00230   * @}
00231   */
00232
00233
00234 /* Private constants ---------------------------------------------------------*/
00235 /** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants
00236   * @{
00237   */
00238 #define HRTIM_CR1_UDIS_MASK   ((uint32_t)(HRTIM_CR1_MUDIS  |\
00239                                           HRTIM_CR1_TAUDIS |\
00240                                           HRTIM_CR1_TBUDIS |\
00241                                           HRTIM_CR1_TCUDIS |\
00242                                           HRTIM_CR1_TDUDIS |\
00243                                           HRTIM_CR1_TEUDIS))
00244
00245 #define HRTIM_CR2_SWUPD_MASK   ((uint32_t)(HRTIM_CR2_MSWU  |\
00246                                           HRTIM_CR2_TASWU |\
00247                                           HRTIM_CR2_TBSWU |\
00248                                           HRTIM_CR2_TCSWU |\
00249                                           HRTIM_CR2_TDSWU |\
00250                                           HRTIM_CR2_TESWU))
00251
00252 #define HRTIM_CR2_SWRST_MASK   ((uint32_t)(HRTIM_CR2_MRST  |\
00253                                           HRTIM_CR2_TARST |\
00254                                           HRTIM_CR2_TBRST |\
00255                                           HRTIM_CR2_TCRST |\
00256                                           HRTIM_CR2_TDRST |\
00257                                           HRTIM_CR2_TERST))
00258
00259 #define HRTIM_OENR_OEN_MASK   ((uint32_t)(HRTIM_OENR_TA1OEN |\
00260                                           HRTIM_OENR_TA2OEN |\
00261                                           HRTIM_OENR_TB1OEN |\
00262                                           HRTIM_OENR_TB2OEN |\
00263                                           HRTIM_OENR_TC1OEN |\
00264                                           HRTIM_OENR_TC2OEN |\
00265                                           HRTIM_OENR_TD1OEN |\
00266                                           HRTIM_OENR_TD2OEN |\
00267                                           HRTIM_OENR_TE1OEN |\
00268                                           HRTIM_OENR_TE2OEN))
00269
00270 #define HRTIM_OENR_ODIS_MASK  ((uint32_t)(HRTIM_ODISR_TA1ODIS  |\
00271                                           HRTIM_ODISR_TA2ODIS  |\
00272                                           HRTIM_ODISR_TB1ODIS  |\
00273                                           HRTIM_ODISR_TB2ODIS  |\
00274                                           HRTIM_ODISR_TC1ODIS  |\
00275                                           HRTIM_ODISR_TC2ODIS  |\
00276                                           HRTIM_ODISR_TD1ODIS  |\
00277                                           HRTIM_ODISR_TD2ODIS  |\
00278                                           HRTIM_ODISR_TE1ODIS  |\
00279                                           HRTIM_ODISR_TE2ODIS))
00280
00281 #define HRTIM_OUT_CONFIG_MASK  ((uint32_t)(HRTIM_OUTR_POL1   |\
00282                                            HRTIM_OUTR_IDLM1  |\
00283                                            HRTIM_OUTR_IDLES1 |\
00284                                            HRTIM_OUTR_FAULT1 |\
00285                                            HRTIM_OUTR_CHP1   |\
00286                                            HRTIM_OUTR_DIDL1))
00287
00288 #define HRTIM_EE_CONFIG_MASK   ((uint32_t)(HRTIM_EECR1_EE1SRC |\
00289                                            HRTIM_EECR1_EE1POL |\
00290                                            HRTIM_EECR1_EE1SNS |\
00291                                            HRTIM_EECR1_EE1FAST))
00292
00293 #define HRTIM_FLT_CONFIG_MASK   ((uint32_t)(HRTIM_FLTINR1_FLT1P |\
00294                                             HRTIM_FLTINR1_FLT1SRC))
00295
00296 #define HRTIM_BM_CONFIG_MASK   ((uint32_t)( HRTIM_BMCR_BMPRSC |\
00297                                             HRTIM_BMCR_BMCLK  |\
00298                                             HRTIM_BMCR_BMOM))
00299
00300 /**
00301   * @}
00302   */
00303
00304
00305 /* Private macros ------------------------------------------------------------*/
00306 /* Exported types ------------------------------------------------------------*/
00307 #if defined(USE_FULL_LL_DRIVER)
00308 /** @defgroup HRTIM_LL_ES_INIT HRTIM Exported Init structure
00309   * @{
00310   */
00311 /* TO BE COMPLETED */
00312 /**
00313   * @}
00314   */
00315 #endif /* USE_FULL_LL_DRIVER */
00316
00317 /* Exported constants --------------------------------------------------------*/
00318 /** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
00319   * @{
00320   */
00321
00322 /** @defgroup HRTIM_EC_GET_FLAG Get Flags Defines
00323   * @brief    Flags defines which can be used with LL_HRTIM_ReadReg function
00324   * @{
00325   */
00326 #define LL_HRTIM_ISR_FLT1                  HRTIM_ISR_FLT1
00327 #define LL_HRTIM_ISR_FLT2                  HRTIM_ISR_FLT2
00328 #define LL_HRTIM_ISR_FLT3                  HRTIM_ISR_FLT3
00329 #define LL_HRTIM_ISR_FLT4                  HRTIM_ISR_FLT4
00330 #define LL_HRTIM_ISR_FLT5                  HRTIM_ISR_FLT5
00331 #define LL_HRTIM_ISR_SYSFLT                HRTIM_ISR_SYSFLT
00332 #define LL_HRTIM_ISR_DLLRDY                HRTIM_ISR_DLLRDY
00333 #define LL_HRTIM_ISR_BMPER                 HRTIM_ISR_BMPER
00334
00335 #define LL_HRTIM_MISR_MCMP1                HRTIM_MISR_MCMP1
00336 #define LL_HRTIM_MISR_MCMP2                HRTIM_MISR_MCMP2
00337 #define LL_HRTIM_MISR_MCMP3                HRTIM_MISR_MCMP3
00338 #define LL_HRTIM_MISR_MCMP4                HRTIM_MISR_MCMP4
00339 #define LL_HRTIM_MISR_MREP                 HRTIM_MISR_MREP
00340 #define LL_HRTIM_MISR_SYNC                 HRTIM_MISR_SYNC
00341 #define LL_HRTIM_MISR_MUPD                 HRTIM_MISR_MUPD
00342
00343 #define LL_HRTIM_TIMISR_CMP1               HRTIM_TIMISR_CMP1
00344 #define LL_HRTIM_TIMISR_CMP2               HRTIM_TIMISR_CMP2
00345 #define LL_HRTIM_TIMISR_CMP3               HRTIM_TIMISR_CMP3
00346 #define LL_HRTIM_TIMISR_CMP4               HRTIM_TIMISR_CMP4
00347 #define LL_HRTIM_TIMISR_REP                HRTIM_TIMISR_REP
00348 #define LL_HRTIM_TIMISR_UPD                HRTIM_TIMISR_UPD
00349 #define LL_HRTIM_TIMISR_CPT1               HRTIM_TIMISR_CPT1
00350 #define LL_HRTIM_TIMISR_CPT2               HRTIM_TIMISR_CPT2
00351 #define LL_HRTIM_TIMISR_SET1               HRTIM_TIMISR_SET1
00352 #define LL_HRTIM_TIMISR_RST1               HRTIM_TIMISR_RST1
00353 #define LL_HRTIM_TIMISR_SET2               HRTIM_TIMISR_SET2
00354 #define LL_HRTIM_TIMISR_RST2               HRTIM_TIMISR_RST2
00355 #define LL_HRTIM_TIMISR_RST                HRTIM_TIMISR_RST
00356 #define LL_HRTIM_TIMISR_DLYPRT             HRTIM_TIMISR_DLYPRT
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup HRTIM_EC_IT IT Defines
00362   * @brief    IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions
00363   * @{
00364   */
00365 #define LL_HRTIM_IER_FLT1IE                HRTIM_IER_FLT1IE
00366 #define LL_HRTIM_IER_FLT2IE                HRTIM_IER_FLT2IE
00367 #define LL_HRTIM_IER_FLT3IE                HRTIM_IER_FLT3IE
00368 #define LL_HRTIM_IER_FLT4IE                HRTIM_IER_FLT4IE
00369 #define LL_HRTIM_IER_FLT5IE                HRTIM_IER_FLT5IE
00370 #define LL_HRTIM_IER_SYSFLTIE              HRTIM_IER_SYSFLTIE
00371 #define LL_HRTIM_IER_DLLRDYIE              HRTIM_IER_DLLRDYIE
00372 #define LL_HRTIM_IER_BMPERIE               HRTIM_IER_BMPERIE
00373
00374 #define LL_HRTIM_MDIER_MCMP1IE             HRTIM_MDIER_MCMP1IE
00375 #define LL_HRTIM_MDIER_MCMP2IE             HRTIM_MDIER_MCMP2IE
00376 #define LL_HRTIM_MDIER_MCMP3IE             HRTIM_MDIER_MCMP3IE
00377 #define LL_HRTIM_MDIER_MCMP4IE             HRTIM_MDIER_MCMP4IE
00378 #define LL_HRTIM_MDIER_MREPIE              HRTIM_MDIER_MREPIE
00379 #define LL_HRTIM_MDIER_SYNCIE              HRTIM_MDIER_SYNCIE
00380 #define LL_HRTIM_MDIER_MUPDIE              HRTIM_MDIER_MUPDIE
00381
00382
00383 #define LL_HRTIM_TIMDIER_CMP1IE            HRTIM_TIMDIER_CMP1IE
00384 #define LL_HRTIM_TIMDIER_CMP2IE            HRTIM_TIMDIER_CMP2IE
00385 #define LL_HRTIM_TIMDIER_CMP3IE            HRTIM_TIMDIER_CMP3IE
00386 #define LL_HRTIM_TIMDIER_CMP4IE            HRTIM_TIMDIER_CMP4IE
00387 #define LL_HRTIM_TIMDIER_REPIE             HRTIM_TIMDIER_REPIE
00388 #define LL_HRTIM_TIMDIER_UPDIE             HRTIM_TIMDIER_UPDIE
00389 #define LL_HRTIM_TIMDIER_CPT1IE            HRTIM_TIMDIER_CPT1IE
00390 #define LL_HRTIM_TIMDIER_CPT2IE            HRTIM_TIMDIER_CPT2IE
00391 #define LL_HRTIM_TIMDIER_SET1IE            HRTIM_TIMDIER_SET1IE
00392 #define LL_HRTIM_TIMDIER_RST1IE            HRTIM_TIMDIER_RST1IE
00393 #define LL_HRTIM_TIMDIER_SET2IE            HRTIM_TIMDIER_SET2IE
00394 #define LL_HRTIM_TIMDIER_RST2IE            HRTIM_TIMDIER_RST2IE
00395 #define LL_HRTIM_TIMDIER_RSTIE             HRTIM_TIMDIER_RSTIE
00396 #define LL_HRTIM_TIMDIER_DLYPRTIE          HRTIM_TIMDIER_DLYPRTIE
00397 /**
00398   * @}
00399   */
00400
00401 /** @defgroup HRTIM_EC_SYNCIN_SRC  SYNCHRONIZATION INPUT SOURCE
00402   * @{
00403   * @brief Constants defining defining the synchronization input source.
00404   */
00405 #define LL_HRTIM_SYNCIN_SRC_NONE            ((uint32_t)0x00000000U)                      /*!< HRTIM is not synchronized and runs in standalone mode */
00406 #define LL_HRTIM_SYNCIN_SRC_TIM_EVENT       (HRTIM_MCR_SYNC_IN_1)                        /*!< The HRTIM is synchronized with the on-chip timer */
00407 #define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT  (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0)  /*!< A positive pulse on SYNCIN input triggers the HRTIM */
00408 /**
00409   * @}
00410   */
00411
00412 /** @defgroup HRTIM_EC_SYNCOUT_SRC  SYNCHRONIZATION OUTPUT SOURCE
00413   * @{
00414   * @brief Constants defining the source and event to be sent on the synchronization output.
00415   */
00416 #define LL_HRTIM_SYNCOUT_SRC_MASTER_START  ((uint32_t)0x00000000U)                        /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
00417 #define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1   (HRTIM_MCR_SYNC_SRC_0)                         /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
00418 #define LL_HRTIM_SYNCOUT_SRC_TIMA_START    (HRTIM_MCR_SYNC_SRC_1)                         /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
00419 #define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1     (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)  /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
00420 /**
00421   * @}
00422   */
00423
00424 /** @defgroup HRTIM_EC_SYNCOUT_POLARITY  SYNCHRONIZATION OUTPUT POLARITY
00425   * @{
00426   * @brief Constants defining the routing and conditioning of the synchronization output event.
00427   */
00428 #define LL_HRTIM_SYNCOUT_DISABLED     ((uint32_t)0x00000000U)                         /*!< Synchronization output event is disabled */
00429 #define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1)                        /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
00430 #define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
00431 /**
00432   * @}
00433   */
00434
00435 /** @defgroup HRTIM_EC_TIMER  TIMER ID
00436   * @{
00437   * @brief Constants identifying a timing unit.
00438   */
00439 #define LL_HRTIM_TIMER_MASTER              HRTIM_MCR_MCEN   /*!< Master timer identifier */
00440 #define LL_HRTIM_TIMER_A                   HRTIM_MCR_TACEN  /*!< Timer A identifier */
00441 #define LL_HRTIM_TIMER_B                   HRTIM_MCR_TBCEN  /*!< Timer B identifier */
00442 #define LL_HRTIM_TIMER_C                   HRTIM_MCR_TCCEN  /*!< Timer C identifier */
00443 #define LL_HRTIM_TIMER_D                   HRTIM_MCR_TDCEN  /*!< Timer D identifier */
00444 #define LL_HRTIM_TIMER_E                   HRTIM_MCR_TECEN  /*!< Timer E identifier */
00445 /**
00446   * @}
00447   */
00448
00449 /** @defgroup HRTIM_EC_OUTPUT  OUTPUT ID
00450   * @{
00451   * @brief Constants identifying an HRTIM output.
00452   */
00453 #define LL_HRTIM_OUTPUT_TA1                HRTIM_OENR_TA1OEN  /*!< Timer A - Output 1 identifier */
00454 #define LL_HRTIM_OUTPUT_TA2                HRTIM_OENR_TA2OEN  /*!< Timer A - Output 2 identifier */
00455 #define LL_HRTIM_OUTPUT_TB1                HRTIM_OENR_TB1OEN  /*!< Timer B - Output 1 identifier */
00456 #define LL_HRTIM_OUTPUT_TB2                HRTIM_OENR_TB2OEN  /*!< Timer B - Output 2 identifier */
00457 #define LL_HRTIM_OUTPUT_TC1                HRTIM_OENR_TC1OEN  /*!< Timer C - Output 1 identifier */
00458 #define LL_HRTIM_OUTPUT_TC2                HRTIM_OENR_TC2OEN  /*!< Timer C - Output 2 identifier */
00459 #define LL_HRTIM_OUTPUT_TD1                HRTIM_OENR_TD1OEN  /*!< Timer D - Output 1 identifier */
00460 #define LL_HRTIM_OUTPUT_TD2                HRTIM_OENR_TD2OEN  /*!< Timer D - Output 2 identifier */
00461 #define LL_HRTIM_OUTPUT_TE1                HRTIM_OENR_TE1OEN  /*!< Timer E - Output 1 identifier */
00462 #define LL_HRTIM_OUTPUT_TE2                HRTIM_OENR_TE2OEN  /*!< Timer E - Output 2 identifier */
00463 /**
00464   * @}
00465   */
00466
00467 /** @defgroup HRTIM_EC_COMPAREUNIT  COMPARE UNIT ID
00468   * @{
00469   * @brief Constants identifying a compare unit.
00470   */
00471 #define LL_HRTIM_COMPAREUNIT_2             HRTIM_TIMCR_DELCMP2  /*!< Compare unit 2 identifier */
00472 #define LL_HRTIM_COMPAREUNIT_4             HRTIM_TIMCR_DELCMP4  /*!< Compare unit 4 identifier */
00473 /**
00474   * @}
00475   */
00476
00477 /** @defgroup HRTIM_EC_CAPTUREUNIT  CAPTURE UNIT ID
00478   * @{
00479   * @brief Constants identifying a capture unit.
00480   */
00481 #define LL_HRTIM_CAPTUREUNIT_1             0  /*!< Capture unit 1 identifier */
00482 #define LL_HRTIM_CAPTUREUNIT_2             1  /*!< Capture unit 2 identifier */
00483 /**
00484   * @}
00485   */
00486
00487 /** @defgroup HRTIM_EC_FAULT  FAULT ID
00488   * @{
00489   * @brief Constants identifying a fault channel.
00490   */
00491 #define LL_HRTIM_FAULT_1      HRTIM_FLTR_FLT1EN     /*!< Fault channel 1 identifier */
00492 #define LL_HRTIM_FAULT_2      HRTIM_FLTR_FLT2EN     /*!< Fault channel 2 identifier */
00493 #define LL_HRTIM_FAULT_3      HRTIM_FLTR_FLT3EN     /*!< Fault channel 3 identifier */
00494 #define LL_HRTIM_FAULT_4      HRTIM_FLTR_FLT4EN     /*!< Fault channel 4 identifier */
00495 #define LL_HRTIM_FAULT_5      HRTIM_FLTR_FLT5EN     /*!< Fault channel 5 identifier */
00496 /**
00497   * @}
00498   */
00499
00500 /** @defgroup HRTIM_EC_EVENT  EXTERNAL EVENT ID
00501   * @{
00502   * @brief Constants identifying an external event channel.
00503   */
00504 #define LL_HRTIM_EVENT_1        ((uint32_t)0x00000001U)     /*!< External event channel 1 identifier */
00505 #define LL_HRTIM_EVENT_2        ((uint32_t)0x00000002U)     /*!< External event channel 2 identifier */
00506 #define LL_HRTIM_EVENT_3        ((uint32_t)0x00000004U)     /*!< External event channel 3 identifier */
00507 #define LL_HRTIM_EVENT_4        ((uint32_t)0x00000008U)     /*!< External event channel 4 identifier */
00508 #define LL_HRTIM_EVENT_5        ((uint32_t)0x00000010U)     /*!< External event channel 5 identifier */
00509 #define LL_HRTIM_EVENT_6        ((uint32_t)0x00000020U)     /*!< External event channel 6 identifier */
00510 #define LL_HRTIM_EVENT_7        ((uint32_t)0x00000040U)     /*!< External event channel 7 identifier */
00511 #define LL_HRTIM_EVENT_8        ((uint32_t)0x00000080U)     /*!< External event channel 8 identifier */
00512 #define LL_HRTIM_EVENT_9        ((uint32_t)0x00000100U)     /*!< External event channel 9 identifier */
00513 #define LL_HRTIM_EVENT_10       ((uint32_t)0x00000200U)     /*!< External event channel 10 identifier */
00514 /**
00515   * @}
00516   */
00517
00518 /** @defgroup HRTIM_EC_OUTPUTSTATE  OUTPUT STATE
00519   * @{
00520   * @brief Constants defining the state of an HRTIM output.
00521   */
00522 #define LL_HRTIM_OUTPUTSTATE_IDLE          ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */
00523 #define LL_HRTIM_OUTPUTSTATE_RUN           ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */
00524 #define LL_HRTIM_OUTPUTSTATE_FAULT         ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */
00525 /**
00526   * @}
00527   */
00528
00529 /** @defgroup HRTIM_EC_ADCTRIG  ADC TRIGGER
00530   * @{
00531   * @brief Constants identifying an ADC trigger.
00532   */
00533 #define LL_HRTIM_ADCTRIG_1              ((uint32_t)0x00000000U) /*!< ADC trigger 1 identifier */
00534 #define LL_HRTIM_ADCTRIG_2              ((uint32_t)0x00000001U)  /*!< ADC trigger 2 identifier */
00535 #define LL_HRTIM_ADCTRIG_3              ((uint32_t)0x00000002U)  /*!< ADC trigger 3 identifier */
00536 #define LL_HRTIM_ADCTRIG_4              ((uint32_t)0x00000003U)  /*!< ADC trigger 4 identifier */
00537 /**
00538   * @}
00539   */
00540
00541 /** @defgroup HRTIM_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE
00542   * @{
00543   * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).
00544   */
00545 #define LL_HRTIM_ADCTRIG_UPDATE_MASTER  ((uint32_t)0x00000000U)                       /*!< HRTIM_ADCxR register update is triggered by the Master timer */
00546 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0)                        /*!< HRTIM_ADCxR register update is triggered by the Timer A */
00547 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1)                        /*!< HRTIM_ADCxR register update is triggered by the Timer B */
00548 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer C */
00549 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2)                        /*!< HRTIM_ADCxR register update is triggered by the Timer D */
00550 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer E */
00551 /**
00552   * @}
00553   */
00554
00555 /** @defgroup HRTIM_EC_ADCTRIG_SRC13  ADC TRIGGER 1/3 SOURCE
00556   * @{
00557   * @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.
00558   */
00559 #define LL_HRTIM_ADCTRIG_SRC13_NONE           ((uint32_t)0x00000000U)  /*!< No ADC trigger event */
00560 #define LL_HRTIM_ADCTRIG_SRC13_MCMP1          HRTIM_ADC1R_AD1MC1       /*!< ADC Trigger on master compare 1 */
00561 #define LL_HRTIM_ADCTRIG_SRC13_MCMP2          HRTIM_ADC1R_AD1MC2       /*!< ADC Trigger on master compare 2 */
00562 #define LL_HRTIM_ADCTRIG_SRC13_MCMP3          HRTIM_ADC1R_AD1MC3       /*!< ADC Trigger on master compare 3 */
00563 #define LL_HRTIM_ADCTRIG_SRC13_MCMP4          HRTIM_ADC1R_AD1MC4       /*!< ADC Trigger on master compare 4 */
00564 #define LL_HRTIM_ADCTRIG_SRC13_MPER           HRTIM_ADC1R_AD1MPER      /*!< ADC Trigger on master period */
00565 #define LL_HRTIM_ADCTRIG_SRC13_EEV1           HRTIM_ADC1R_AD1EEV1      /*!< ADC Trigger on external event 1 */
00566 #define LL_HRTIM_ADCTRIG_SRC13_EEV2           HRTIM_ADC1R_AD1EEV2      /*!< ADC Trigger on external event 2 */
00567 #define LL_HRTIM_ADCTRIG_SRC13_EEV3           HRTIM_ADC1R_AD1EEV3      /*!< ADC Trigger on external event 3 */
00568 #define LL_HRTIM_ADCTRIG_SRC13_EEV4           HRTIM_ADC1R_AD1EEV4      /*!< ADC Trigger on external event 4 */
00569 #define LL_HRTIM_ADCTRIG_SRC13_EEV5           HRTIM_ADC1R_AD1EEV5      /*!< ADC Trigger on external event 5 */
00570 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP2       HRTIM_ADC1R_AD1TAC2      /*!< ADC Trigger on Timer A compare 2 */
00571 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3       HRTIM_ADC1R_AD1TAC3      /*!< ADC Trigger on Timer A compare 3 */
00572 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4       HRTIM_ADC1R_AD1TAC4      /*!< ADC Trigger on Timer A compare 4 */
00573 #define LL_HRTIM_ADCTRIG_SRC13_TIMAPER        HRTIM_ADC1R_AD1TAPER     /*!< ADC Trigger on Timer A period */
00574 #define LL_HRTIM_ADCTRIG_SRC13_TIMARST        HRTIM_ADC1R_AD1TARST     /*!< ADC Trigger on Timer A reset */
00575 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2       HRTIM_ADC1R_AD1TBC2      /*!< ADC Trigger on Timer B compare 2 */
00576 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3       HRTIM_ADC1R_AD1TBC3      /*!< ADC Trigger on Timer B compare 3 */
00577 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4       HRTIM_ADC1R_AD1TBC4      /*!< ADC Trigger on Timer B compare 4 */
00578 #define LL_HRTIM_ADCTRIG_SRC13_TIMBPER        HRTIM_ADC1R_AD1TBPER     /*!< ADC Trigger on Timer B period */
00579 #define LL_HRTIM_ADCTRIG_SRC13_TIMBRST        HRTIM_ADC1R_AD1TBRST     /*!< ADC Trigger on Timer B reset */
00580 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2       HRTIM_ADC1R_AD1TCC2      /*!< ADC Trigger on Timer C compare 2 */
00581 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3       HRTIM_ADC1R_AD1TCC3      /*!< ADC Trigger on Timer C compare 3 */
00582 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4       HRTIM_ADC1R_AD1TCC4      /*!< ADC Trigger on Timer C compare 4 */
00583 #define LL_HRTIM_ADCTRIG_SRC13_TIMCPER        HRTIM_ADC1R_AD1TCPER     /*!< ADC Trigger on Timer C period */
00584 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2       HRTIM_ADC1R_AD1TDC2      /*!< ADC Trigger on Timer D compare 2 */
00585 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3       HRTIM_ADC1R_AD1TDC3      /*!< ADC Trigger on Timer D compare 3 */
00586 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4       HRTIM_ADC1R_AD1TDC4      /*!< ADC Trigger on Timer D compare 4 */
00587 #define LL_HRTIM_ADCTRIG_SRC13_TIMDPER        HRTIM_ADC1R_AD1TDPER     /*!< ADC Trigger on Timer D period */
00588 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP2       HRTIM_ADC1R_AD1TEC2      /*!< ADC Trigger on Timer E compare 2 */
00589 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3       HRTIM_ADC1R_AD1TEC3      /*!< ADC Trigger on Timer E compare 3 */
00590 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4       HRTIM_ADC1R_AD1TEC4      /*!< ADC Trigger on Timer E compare 4 */
00591 #define LL_HRTIM_ADCTRIG_SRC13_TIMEPER        HRTIM_ADC1R_AD1TEPER     /*!< ADC Trigger on Timer E period */
00592 /**
00593   * @}
00594   */
00595
00596 /** @defgroup HRTIM_EC_ADCTRIG_SRC24  ADC TRIGGER 2/4 SOURCE
00597   * @{
00598   * @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.
00599   */
00600 #define LL_HRTIM_ADCTRIG_SRC24_NONE           ((uint32_t)0x00000000U)/*!< No ADC trigger event */
00601 #define LL_HRTIM_ADCTRIG_SRC24_MCMP1          HRTIM_ADC2R_AD2MC1     /*!< ADC Trigger on master compare 1 */
00602 #define LL_HRTIM_ADCTRIG_SRC24_MCMP2          HRTIM_ADC2R_AD2MC2     /*!< ADC Trigger on master compare 2 */
00603 #define LL_HRTIM_ADCTRIG_SRC24_MCMP3          HRTIM_ADC2R_AD2MC3     /*!< ADC Trigger on master compare 3 */
00604 #define LL_HRTIM_ADCTRIG_SRC24_MCMP4          HRTIM_ADC2R_AD2MC4     /*!< ADC Trigger on master compare 4 */
00605 #define LL_HRTIM_ADCTRIG_SRC24_MPER           HRTIM_ADC2R_AD2MPER    /*!< ADC Trigger on master period */
00606 #define LL_HRTIM_ADCTRIG_SRC24_EEV6           HRTIM_ADC2R_AD2EEV6    /*!< ADC Trigger on external event 6 */
00607 #define LL_HRTIM_ADCTRIG_SRC24_EEV7           HRTIM_ADC2R_AD2EEV7    /*!< ADC Trigger on external event 7 */
00608 #define LL_HRTIM_ADCTRIG_SRC24_EEV8           HRTIM_ADC2R_AD2EEV8    /*!< ADC Trigger on external event 8 */
00609 #define LL_HRTIM_ADCTRIG_SRC24_EEV9           HRTIM_ADC2R_AD2EEV9    /*!< ADC Trigger on external event 9 */
00610 #define LL_HRTIM_ADCTRIG_SRC24_EEV10          HRTIM_ADC2R_AD2EEV10   /*!< ADC Trigger on external event 10 */
00611 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2       HRTIM_ADC2R_AD2TAC2    /*!< ADC Trigger on Timer A compare 2 */
00612 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP3       HRTIM_ADC2R_AD2TAC3    /*!< ADC Trigger on Timer A compare 3 */
00613 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4       HRTIM_ADC2R_AD2TAC4    /*!< ADC Trigger on Timer A compare 4 */
00614 #define LL_HRTIM_ADCTRIG_SRC24_TIMAPER        HRTIM_ADC2R_AD2TAPER   /*!< ADC Trigger on Timer A period */
00615 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2       HRTIM_ADC2R_AD2TBC2    /*!< ADC Trigger on Timer B compare 2 */
00616 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3       HRTIM_ADC2R_AD2TBC3    /*!< ADC Trigger on Timer B compare 3 */
00617 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4       HRTIM_ADC2R_AD2TBC4    /*!< ADC Trigger on Timer B compare 4 */
00618 #define LL_HRTIM_ADCTRIG_SRC24_TIMBPER        HRTIM_ADC2R_AD2TBPER   /*!< ADC Trigger on Timer B period */
00619 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2       HRTIM_ADC2R_AD2TCC2    /*!< ADC Trigger on Timer C compare 2 */
00620 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3       HRTIM_ADC2R_AD2TCC3    /*!< ADC Trigger on Timer C compare 3 */
00621 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4       HRTIM_ADC2R_AD2TCC4    /*!< ADC Trigger on Timer C compare 4 */
00622 #define LL_HRTIM_ADCTRIG_SRC24_TIMCPER        HRTIM_ADC2R_AD2TCPER   /*!< ADC Trigger on Timer C period */
00623 #define LL_HRTIM_ADCTRIG_SRC24_TIMCRST        HRTIM_ADC2R_AD2TCRST   /*!< ADC Trigger on Timer C reset */
00624 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2       HRTIM_ADC2R_AD2TDC2    /*!< ADC Trigger on Timer D compare 2 */
00625 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3       HRTIM_ADC2R_AD2TDC3    /*!< ADC Trigger on Timer D compare 3 */
00626 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4       HRTIM_ADC2R_AD2TDC4    /*!< ADC Trigger on Timer D compare 4 */
00627 #define LL_HRTIM_ADCTRIG_SRC24_TIMDPER        HRTIM_ADC2R_AD2TDPER   /*!< ADC Trigger on Timer D period */
00628 #define LL_HRTIM_ADCTRIG_SRC24_TIMDRST        HRTIM_ADC2R_AD2TDRST   /*!< ADC Trigger on Timer D reset */
00629 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2       HRTIM_ADC2R_AD2TEC2    /*!< ADC Trigger on Timer E compare 2 */
00630 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3       HRTIM_ADC2R_AD2TEC3    /*!< ADC Trigger on Timer E compare 3 */
00631 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4       HRTIM_ADC2R_AD2TEC4    /*!< ADC Trigger on Timer E compare 4 */
00632 #define LL_HRTIM_ADCTRIG_SRC24_TIMERST        HRTIM_ADC2R_AD2TERST   /*!< ADC Trigger on Timer E reset */
00633 /**
00634   * @}
00635   */
00636
00637 /** @defgroup HRTIM_EC_DLLCALIBRATION_MODE  DLL CALIBRATION MODE
00638   * @{
00639   * @brief Constants defining the DLL calibration mode.
00640   */
00641 #define LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT   ((uint32_t)0x00000000U)/*!<Calibration is perfomed only once */
00642 #define LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS   HRTIM_DLLCR_CALEN      /*!<Calibration is performed periodically */
00643 /**
00644   * @}
00645   */
00646
00647 /** @defgroup HRTIM_EC_CALIBRATIONRATE  DLL CALIBRATION RATE
00648   * @{
00649   * @brief Constants defining the DLL calibration periods (in micro seconds).
00650   */
00651 #define LL_HRTIM_DLLCALIBRATION_RATE_7300      ((uint32_t)0x00000000U)                        /*!< Periodic DLL calibration: T = 1048576 * tHRTIM (7.3 ms) */
00652 #define LL_HRTIM_DLLCALIBRATION_RATE_910       (HRTIM_DLLCR_CALRTE_0)                         /*!< Periodic DLL calibration: T = 131072 * tHRTIM (910 ms) */
00653 #define LL_HRTIM_DLLCALIBRATION_RATE_114       (HRTIM_DLLCR_CALRTE_1)                         /*!< Periodic DLL calibration: T = 16384 * tHRTIM (114 ms) */
00654 #define LL_HRTIM_DLLCALIBRATION_RATE_14        (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)  /*!< Periodic DLL calibration: T = 2048 * tHRTIM (14 ms) */
00655 /**
00656   * @}
00657   */
00658
00659 /** @defgroup HRTIM_EC_PRESCALERRATIO  PRESCALER RATIO
00660   * @{
00661   * @brief Constants defining timer high-resolution clock prescaler ratio.
00662   */
00663 #define LL_HRTIM_PRESCALERRATIO_MUL32      ((uint32_t)0x00000000U) /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)      */
00664 #define LL_HRTIM_PRESCALERRATIO_MUL16      ((uint32_t)0x00000001U)  /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)      */
00665 #define LL_HRTIM_PRESCALERRATIO_MUL8       ((uint32_t)0x00000002U)  /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)      */
00666 #define LL_HRTIM_PRESCALERRATIO_MUL4       ((uint32_t)0x00000003U)  /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)      */
00667 #define LL_HRTIM_PRESCALERRATIO_MUL2       ((uint32_t)0x00000004U)  /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)      */
00668 #define LL_HRTIM_PRESCALERRATIO_DIV1       ((uint32_t)0x00000005U)  /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)      */
00669 #define LL_HRTIM_PRESCALERRATIO_DIV2       ((uint32_t)0x00000006U)  /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)      */
00670 #define LL_HRTIM_PRESCALERRATIO_DIV4       ((uint32_t)0x00000007U)  /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)      */
00671 /**
00672   * @}
00673   */
00674
00675 /** @defgroup HRTIM_EC_MODE  COUNTER MODE
00676   * @{
00677   * @brief Constants defining timer counter operating mode.
00678   */
00679 #define LL_HRTIM_MODE_CONTINUOUS           ((uint32_t)0x00000008U)  /*!< The timer operates in continuous (free-running) mode */
00680 #define LL_HRTIM_MODE_SINGLESHOT           ((uint32_t)0x00000000U) /*!< The timer operates in non retriggerable single-shot mode */
00681 #define LL_HRTIM_MODE_RETRIGGERABLE        ((uint32_t)0x00000010U)  /*!< The timer operates in retriggerable single-shot mode */
00682 /**
00683   * @}
00684   */
00685
00686 /** @defgroup HRTIM_EC_DACTRIG  DAC TRIGGER
00687   * @{
00688   * @brief Constants defining on which output the DAC synchronization event is sent.
00689   */
00690 #define LL_HRTIM_DACTRIG_NONE           ((uint32_t)0x00000000U)                     /*!< No DAC synchronization event generated */
00691 #define LL_HRTIM_DACTRIG_DACTRIGOUT_1   (HRTIM_MCR_DACSYNC_0)                       /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
00692 #define LL_HRTIM_DACTRIG_DACTRIGOUT_2   (HRTIM_MCR_DACSYNC_1)                       /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
00693 #define LL_HRTIM_DACTRIG_DACTRIGOUT_3   (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */
00694 /**
00695   * @}
00696   */
00697
00698 /** @defgroup HRTIM_EC_UPDATETRIG  UPDATE TRIGGER
00699   * @{
00700   * @brief Constants defining whether the registers update is done synchronously with any other timer or master update.
00701   */
00702 #define LL_HRTIM_UPDATETRIG_NONE        ((uint32_t)0x00000000U)/*!< Register update is disabled */
00703 #define LL_HRTIM_UPDATETRIG_MASTER      HRTIM_TIMCR_MSTU       /*!< Register update is triggered by the master timer update */
00704 #define LL_HRTIM_UPDATETRIG_TIMER_A     HRTIM_TIMCR_TAU        /*!< Register update is triggered by the timer A update */
00705 #define LL_HRTIM_UPDATETRIG_TIMER_B     HRTIM_TIMCR_TBU        /*!< Register update is triggered by the timer B update */
00706 #define LL_HRTIM_UPDATETRIG_TIMER_C     HRTIM_TIMCR_TCU        /*!< Register update is triggered by the timer C update*/
00707 #define LL_HRTIM_UPDATETRIG_TIMER_D     HRTIM_TIMCR_TDU        /*!< Register update is triggered by the timer D update */
00708 #define LL_HRTIM_UPDATETRIG_TIMER_E     HRTIM_TIMCR_TEU        /*!< Register update is triggered by the timer E update */
00709 #define LL_HRTIM_UPDATETRIG_REPETITION  HRTIM_TIMCR_TREPU      /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/
00710 #define LL_HRTIM_UPDATETRIG_RESET       HRTIM_TIMCR_TRSTU      /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */
00711 /**
00712   * @}
00713   */
00714
00715 /** @defgroup HRTIM_EC_UPDATEGATING  UPDATE GATING
00716   * @{
00717   * @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.
00718   */
00719 #define LL_HRTIM_UPDATEGATING_INDEPENDENT     ((uint32_t)0x00000000U)                                               /*!< Update done independently from the DMA burst transfer completion */
00720 #define LL_HRTIM_UPDATEGATING_DMABURST        (HRTIM_TIMCR_UPDGAT_0)                                                /*!< Update done when the DMA burst transfer is completed */
00721 #define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1)                                                /*!< Update done on timer roll-over following a DMA burst transfer completion*/
00722 #define LL_HRTIM_UPDATEGATING_UPDEN1          (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
00723 #define LL_HRTIM_UPDATEGATING_UPDEN2          (HRTIM_TIMCR_UPDGAT_2)                                                /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
00724 #define LL_HRTIM_UPDATEGATING_UPDEN3          (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
00725 #define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1)                         /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 1 */
00726 #define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)  /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
00727 #define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE   (HRTIM_TIMCR_UPDGAT_3)                                                /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
00728 /**
00729   * @}
00730   */
00731
00732 /** @defgroup HRTIM_EC_COMPAREMODE  COMPARE MODE
00733   * @{
00734   * @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode.
00735   */
00736 #define LL_HRTIM_COMPAREMODE_REGULAR          ((uint32_t)0x00000000U)                         /*!< standard compare mode */
00737 #define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT  (HRTIM_TIMCR_DELCMP2_0)                         /*!< Compare event generated only if a capture has occurred */
00738 #define LL_HRTIM_COMPAREMODE_DELAY_CMP1       (HRTIM_TIMCR_DELCMP2_1)                         /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
00739 #define LL_HRTIM_COMPAREMODE_DELAY_CMP3       (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
00740 /**
00741   * @}
00742   */
00743
00744 /** @defgroup HRTIM_EC_RESETTRIG  RESET TRIGGER
00745   * @{
00746   * @brief Constants defining the events that can be selected to trigger the reset of the timer counter.
00747   */
00748 #define LL_HRTIM_RESETTRIG_NONE        ((uint32_t)0x00000000U)/*!< No counter reset trigger */
00749 #define LL_HRTIM_RESETTRIG_UPDATE      HRTIM_RSTR_UPDATE      /*!< The timer counter is reset upon update event */
00750 #define LL_HRTIM_RESETTRIG_CMP2        HRTIM_RSTR_CMP2        /*!< The timer counter is reset upon Timer Compare 2 event */
00751 #define LL_HRTIM_RESETTRIG_CMP4        HRTIM_RSTR_CMP4        /*!< The timer counter is reset upon Timer Compare 4 event */
00752 #define LL_HRTIM_RESETTRIG_MASTER_PER  HRTIM_RSTR_MSTPER      /*!< The timer counter is reset upon master timer period event */
00753 #define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1     /*!< The timer counter is reset upon master timer Compare 1 event */
00754 #define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2     /*!< The timer counter is reset upon master timer Compare 2 event */
00755 #define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3     /*!< The timer counter is reset upon master timer Compare 3 event */
00756 #define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4     /*!< The timer counter is reset upon master timer Compare 4 event */
00757 #define LL_HRTIM_RESETTRIG_EEV_1       HRTIM_RSTR_EXTEVNT1    /*!< The timer counter is reset upon external event 1 */
00758 #define LL_HRTIM_RESETTRIG_EEV_2       HRTIM_RSTR_EXTEVNT2    /*!< The timer counter is reset upon external event 2 */
00759 #define LL_HRTIM_RESETTRIG_EEV_3       HRTIM_RSTR_EXTEVNT3    /*!< The timer counter is reset upon external event 3 */
00760 #define LL_HRTIM_RESETTRIG_EEV_4       HRTIM_RSTR_EXTEVNT4    /*!< The timer counter is reset upon external event 4 */
00761 #define LL_HRTIM_RESETTRIG_EEV_5       HRTIM_RSTR_EXTEVNT5    /*!< The timer counter is reset upon external event 5 */
00762 #define LL_HRTIM_RESETTRIG_EEV_6       HRTIM_RSTR_EXTEVNT6    /*!< The timer counter is reset upon external event 6 */
00763 #define LL_HRTIM_RESETTRIG_EEV_7       HRTIM_RSTR_EXTEVNT7    /*!< The timer counter is reset upon external event 7 */
00764 #define LL_HRTIM_RESETTRIG_EEV_8       HRTIM_RSTR_EXTEVNT8    /*!< The timer counter is reset upon external event 8 */
00765 #define LL_HRTIM_RESETTRIG_EEV_9       HRTIM_RSTR_EXTEVNT9    /*!< The timer counter is reset upon external event 9 */
00766 #define LL_HRTIM_RESETTRIG_EEV_10      HRTIM_RSTR_EXTEVNT10   /*!< The timer counter is reset upon external event 10 */
00767 #define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
00768 #define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
00769 #define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4    /*!< The timer counter is reset upon other timer Compare 4 event */
00770 #define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
00771 #define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
00772 #define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4    /*!< The timer counter is reset upon other timer Compare 4 event */
00773 #define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
00774 #define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
00775 #define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4    /*!< The timer counter is reset upon other timer Compare 4 event */
00776 #define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
00777 #define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
00778 #define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4    /*!< The timer counter is reset upon other timer Compare 4 event */
00779 /**
00780   * @}
00781   */
00782
00783 /** @defgroup HRTIM_EC_CAPTURETRIG  CAPTURE TRIGGER
00784   * @{
00785   * @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter.
00786   */
00787 #define LL_HRTIM_CAPTURETRIG_NONE         ((uint32_t)0x00000000U)/*!< Capture trigger is disabled */
00788 #define LL_HRTIM_CAPTURETRIG_UPDATE       HRTIM_CPT1CR_UPDCPT    /*!< The update event triggers the Capture */
00789 #define LL_HRTIM_CAPTURETRIG_EEV_1        HRTIM_CPT1CR_EXEV1CPT  /*!< The External event 1 triggers the Capture */
00790 #define LL_HRTIM_CAPTURETRIG_EEV_2        HRTIM_CPT1CR_EXEV2CPT  /*!< The External event 2 triggers the Capture */
00791 #define LL_HRTIM_CAPTURETRIG_EEV_3        HRTIM_CPT1CR_EXEV3CPT  /*!< The External event 3 triggers the Capture */
00792 #define LL_HRTIM_CAPTURETRIG_EEV_4        HRTIM_CPT1CR_EXEV4CPT  /*!< The External event 4 triggers the Capture */
00793 #define LL_HRTIM_CAPTURETRIG_EEV_5        HRTIM_CPT1CR_EXEV5CPT  /*!< The External event 5 triggers the Capture */
00794 #define LL_HRTIM_CAPTURETRIG_EEV_6        HRTIM_CPT1CR_EXEV6CPT  /*!< The External event 6 triggers the Capture */
00795 #define LL_HRTIM_CAPTURETRIG_EEV_7        HRTIM_CPT1CR_EXEV7CPT  /*!< The External event 7 triggers the Capture */
00796 #define LL_HRTIM_CAPTURETRIG_EEV_8        HRTIM_CPT1CR_EXEV8CPT  /*!< The External event 8 triggers the Capture */
00797 #define LL_HRTIM_CAPTURETRIG_EEV_9        HRTIM_CPT1CR_EXEV9CPT  /*!< The External event 9 triggers the Capture */
00798 #define LL_HRTIM_CAPTURETRIG_EEV_10       HRTIM_CPT1CR_EXEV10CPT /*!< The External event 10 triggers the Capture */
00799 #define LL_HRTIM_CAPTURETRIG_TA1_SET      HRTIM_CPT1CR_TA1SET    /*!< Capture is triggered by TA1 output inactive to active transition */
00800 #define LL_HRTIM_CAPTURETRIG_TA1_RESET    HRTIM_CPT1CR_TA1RST    /*!< Capture is triggered by TA1 output active to inactive transition */
00801 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP1    HRTIM_CPT1CR_TIMACMP1  /*!< Timer A Compare 1 triggers Capture */
00802 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP2    HRTIM_CPT1CR_TIMACMP2  /*!< Timer A Compare 2 triggers Capture */
00803 #define LL_HRTIM_CAPTURETRIG_TB1_SET      HRTIM_CPT1CR_TB1SET    /*!< Capture is triggered by TB1 output inactive to active transition */
00804 #define LL_HRTIM_CAPTURETRIG_TB1_RESET    HRTIM_CPT1CR_TB1RST    /*!< Capture is triggered by TB1 output active to inactive transition */
00805 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP1    HRTIM_CPT1CR_TIMBCMP1  /*!< Timer B Compare 1 triggers Capture */
00806 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP2    HRTIM_CPT1CR_TIMBCMP2  /*!< Timer B Compare 2 triggers Capture */
00807 #define LL_HRTIM_CAPTURETRIG_TC1_SET      HRTIM_CPT1CR_TC1SET    /*!< Capture is triggered by TC1 output inactive to active transition */
00808 #define LL_HRTIM_CAPTURETRIG_TC1_RESET    HRTIM_CPT1CR_TC1RST    /*!< Capture is triggered by TC1 output active to inactive transition */
00809 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP1    HRTIM_CPT1CR_TIMCCMP1  /*!< Timer C Compare 1 triggers Capture */
00810 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP2    HRTIM_CPT1CR_TIMCCMP2  /*!< Timer C Compare 2 triggers Capture */
00811 #define LL_HRTIM_CAPTURETRIG_TD1_SET      HRTIM_CPT1CR_TD1SET    /*!< Capture is triggered by TD1 output inactive to active transition */
00812 #define LL_HRTIM_CAPTURETRIG_TD1_RESET    HRTIM_CPT1CR_TD1RST    /*!< Capture is triggered by TD1 output active to inactive transition */
00813 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP1    HRTIM_CPT1CR_TIMDCMP1  /*!< Timer D Compare 1 triggers Capture */
00814 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP2    HRTIM_CPT1CR_TIMDCMP2  /*!< Timer D Compare 2 triggers Capture */
00815 #define LL_HRTIM_CAPTURETRIG_TE1_SET      HRTIM_CPT1CR_TE1SET    /*!< Capture is triggered by TE1 output inactive to active transition */
00816 #define LL_HRTIM_CAPTURETRIG_TE1_RESET    HRTIM_CPT1CR_TE1RST    /*!< Capture is triggered by TE1 output active to inactive transition */
00817 #define LL_HRTIM_CAPTURETRIG_TIME_CMP1    HRTIM_CPT1CR_TIMECMP1  /*!< Timer E Compare 1 triggers Capture */
00818 #define LL_HRTIM_CAPTURETRIG_TIME_CMP2    HRTIM_CPT1CR_TIMECMP2  /*!< Timer E Compare 2 triggers Capture */
00819 /**
00820   * @}
00821   */
00822
00823 /** @defgroup HRTIM_EC_DLYPRT  DELAYED PROTECTION (DLYPRT) MODE
00824   * @{
00825   * @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied).
00826   */
00827 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6  ((uint32_t)0x00000000U)                                            /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */
00828 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6  (HRTIM_OUTR_DLYPRT_0)                                             /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */
00829 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6  (HRTIM_OUTR_DLYPRT_1)                                             /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */
00830 #define LL_HRTIM_DLYPRT_BALANCED_EEV6   (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0)                       /*!< Timers A, B, C: Balanced Idle on external Event 6 */
00831 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7  (HRTIM_OUTR_DLYPRT_2)                                             /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */
00832 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0)                       /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */
00833 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1)                       /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */
00834 #define LL_HRTIM_DLYPRT_BALANCED_EEV7   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */
00835
00836 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8  ((uint32_t)0x00000000U)                                             /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */
00837 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8  (HRTIM_OUTR_DLYPRT_0)                                               /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */
00838 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8  (HRTIM_OUTR_DLYPRT_1)                                               /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */
00839 #define LL_HRTIM_DLYPRT_BALANCED_EEV8   (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0)                         /*!< Timers D, E: Balanced Idle on external Event 8 */
00840 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9  (HRTIM_OUTR_DLYPRT_2)                                               /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */
00841 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0)                         /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */
00842 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1)                         /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */
00843 #define LL_HRTIM_DLYPRT_BALANCED_EEV9   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0)   /*!< Timers D, E: Balanced Idle on external Event 9 */
00844 /**
00845   * @}
00846   */
00847
00848 /** @defgroup HRTIM_EC_BURSTMODE  BURST MODE
00849   * @{
00850   * @brief Constants defining how the timer behaves during a burst mode operation.
00851   */
00852 #define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
00853 #define LL_HRTIM_BURSTMODE_RESETCOUNTER  (HRTIM_BMCR_MTBM)  /*!< Timer counter clock is stopped and the counter is reset */
00854 /**
00855   * @}
00856   */
00857
00858 /** @defgroup HRTIM_EC_BURSTDMA  BURST DMA
00859   * @{
00860   * @brief Constants defining the registers that can be written during a burst DMA operation.
00861   */
00862 #define LL_HRTIM_BURSTDMA_NONE  ((uint32_t)0x00000000U)     /*!< No register is updated by Burst DMA accesses */
00863
00864 #define LL_HRTIM_BURSTDMA_MCR    (HRTIM_BDMUPR_MCR)          /*!< MCR  register is updated by Burst DMA accesses */
00865 #define LL_HRTIM_BURSTDMA_MICR   (HRTIM_BDMUPR_MICR)         /*!< MICR register is updated by Burst DMA accesses */
00866 #define LL_HRTIM_BURSTDMA_MDIER  (HRTIM_BDMUPR_MDIER)        /*!< MDIER register is updated by Burst DMA accesses */
00867 #define LL_HRTIM_BURSTDMA_MCNT   (HRTIM_BDMUPR_MCNT)         /*!< MCNTR register is updated by Burst DMA accesses */
00868 #define LL_HRTIM_BURSTDMA_MPER   (HRTIM_BDMUPR_MPER)         /*!< MPER register is updated by Burst DMA accesses */
00869 #define LL_HRTIM_BURSTDMA_MREP   (HRTIM_BDMUPR_MREP)         /*!< MREPR register is updated by Burst DMA accesses */
00870 #define LL_HRTIM_BURSTDMA_MCMP1  (HRTIM_BDMUPR_MCMP1)        /*!< MCMP1R register is updated by Burst DMA accesses */
00871 #define LL_HRTIM_BURSTDMA_MCMP2  (HRTIM_BDMUPR_MCMP2)        /*!< MCMP2R register is updated by Burst DMA accesses */
00872 #define LL_HRTIM_BURSTDMA_MCMP3  (HRTIM_BDMUPR_MCMP3)        /*!< MCMP3R register is updated by Burst DMA accesses */
00873 #define LL_HRTIM_BURSTDMA_MCMP4  (HRTIM_BDMUPR_MCMP4)        /*!< MCMP4R register is updated by Burst DMA accesses */
00874
00875 #define LL_HRTIM_BURSTDMA_TIMMCR   (HRTIM_BDTUPR_TIMCR)      /*!< TIMxCR register is updated by Burst DMA accesses */
00876 #define LL_HRTIM_BURSTDMA_TIMICR   (HRTIM_BDTUPR_TIMICR)     /*!< TIMxICR register is updated by Burst DMA accesses */
00877 #define LL_HRTIM_BURSTDMA_TIMDIER  (HRTIM_BDTUPR_TIMDIER)    /*!< TIMxDIER register is updated by Burst DMA accesses */
00878 #define LL_HRTIM_BURSTDMA_TIMCNT   (HRTIM_BDTUPR_TIMCNT)     /*!< CNTxCR register is updated by Burst DMA accesses */
00879 #define LL_HRTIM_BURSTDMA_TIMPER   (HRTIM_BDTUPR_TIMPER)     /*!< PERxR register is updated by Burst DMA accesses */
00880 #define LL_HRTIM_BURSTDMA_TIMREP   (HRTIM_BDTUPR_TIMREP)     /*!< REPxR register is updated by Burst DMA accesses */
00881 #define LL_HRTIM_BURSTDMA_TIMCMP1  (HRTIM_BDTUPR_TIMCMP1)    /*!< CMP1xR register is updated by Burst DMA accesses */
00882 #define LL_HRTIM_BURSTDMA_TIMCMP2  (HRTIM_BDTUPR_TIMCMP2)    /*!< CMP2xR register is updated by Burst DMA accesses */
00883 #define LL_HRTIM_BURSTDMA_TIMCMP3  (HRTIM_BDTUPR_TIMCMP3)    /*!< CMP3xR register is updated by Burst DMA accesses */
00884 #define LL_HRTIM_BURSTDMA_TIMCMP4  (HRTIM_BDTUPR_TIMCMP4)    /*!< CMP4xR register is updated by Burst DMA accesses */
00885 #define LL_HRTIM_BURSTDMA_TIMDTR   (HRTIM_BDTUPR_TIMDTR)     /*!< DTxR register is updated by Burst DMA accesses */
00886 #define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R)   /*!< SET1R register is updated by Burst DMA accesses */
00887 #define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R)   /*!< RST1R register is updated by Burst DMA accesses */
00888 #define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R)   /*!< SET2R register is updated by Burst DMA accesses */
00889 #define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R)   /*!< RST1R register is updated by Burst DMA accesses */
00890 #define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1)   /*!< EEFxR1 register is updated by Burst DMA accesses */
00891 #define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2)   /*!< EEFxR2 register is updated by Burst DMA accesses */
00892 #define LL_HRTIM_BURSTDMA_TIMRSTR  (HRTIM_BDTUPR_TIMRSTR)    /*!< RSTxR register is updated by Burst DMA accesses */
00893 #define LL_HRTIM_BURSTDMA_TIMCHPR  (HRTIM_BDTUPR_TIMCHPR)    /*!< CHPxR register is updated by Burst DMA accesses */
00894 #define LL_HRTIM_BURSTDMA_TIMOUTR  (HRTIM_BDTUPR_TIMOUTR)    /*!< OUTxR register is updated by Burst DMA accesses */
00895 #define LL_HRTIM_BURSTDMA_TIMFLTR  (HRTIM_BDTUPR_TIMFLTR)    /*!< FLTxR register is updated by Burst DMA accesses */
00896 /**
00897   * @}
00898   */
00899
00900 /** @defgroup HRTIM_EC_CPPSTAT  CURRENT PUSH-PULL STATUS
00901   * @{
00902   * @brief Constants defining on which output the signal is currently applied in push-pull mode.
00903   */
00904 #define LL_HRTIM_CPPSTAT_OUTPUT1   ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */
00905 #define LL_HRTIM_CPPSTAT_OUTPUT2   (HRTIM_TIMISR_CPPSTAT)  /*!< Signal applied on output 2 and output 1 forced inactive */
00906 /**
00907   * @}
00908   */
00909
00910 /** @defgroup HRTIM_EC_IPPSTAT  IDLE PUSH-PULL STATUS
00911   * @{
00912   * @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.
00913   */
00914 #define LL_HRTIM_IPPSTAT_OUTPUT1   ((uint32_t) 0x00000000U)    /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
00915 #define LL_HRTIM_IPPSTAT_OUTPUT2   (HRTIM_TIMISR_IPPSTAT)     /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
00916 /**
00917   * @}
00918   */
00919
00920 /** @defgroup HRTIM_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER
00921   * @{
00922   * @brief Constants defining the event filtering applied to external events by a timer.
00923   */
00924 #define LL_HRTIM_EEFLTR_NONE             ((uint32_t)0x00000000U)
00925 #define LL_HRTIM_EEFLTR_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 1 */
00926 #define LL_HRTIM_EEFLTR_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 2 */
00927 #define LL_HRTIM_EEFLTR_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from counter reset/roll-over to Compare 3 */
00928 #define LL_HRTIM_EEFLTR_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 4 */
00929 #define LL_HRTIM_EEFLTR_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR1 source */
00930 #define LL_HRTIM_EEFLTR_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR2 source */
00931 #define LL_HRTIM_EEFLTR_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Blanking from another timing unit: TIMFLTR3 source */
00932 #define LL_HRTIM_EEFLTR_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)                                                                                                                           /*!< Blanking from another timing unit: TIMFLTR4 source */
00933 #define LL_HRTIM_EEFLTR_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR5 source */
00934 #define LL_HRTIM_EEFLTR_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR6 source */
00935 #define LL_HRTIM_EEFLTR_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Blanking from another timing unit: TIMFLTR7 source */
00936 #define LL_HRTIM_EEFLTR_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR8 source */
00937 #define LL_HRTIM_EEFLTR_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Windowing from counter reset/roll-over to Compare 2 */
00938 #define LL_HRTIM_EEFLTR_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                                                                           /*!< Windowing from counter reset/roll-over to Compare 3 */
00939 #define LL_HRTIM_EEFLTR_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)  /*!< Windowing from another timing unit: TIMWIN source */
00940 /**
00941   * @}
00942   */
00943
00944 /** @defgroup HRTIM_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS
00945   * @{
00946   * @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.
00947   */
00948 #define LL_HRTIM_EELATCH_DISABLED    ((uint32_t)0x00000000U) /*!< Event is ignored if it happens during a blank, or passed through during a window */
00949 #define LL_HRTIM_EELATCH_ENABLED     HRTIM_EEFR1_EE1LTCH     /*!< Event is latched and delayed till the end of the blanking or windowing period */
00950 /**
00951   * @}
00952   */
00953
00954 /** @defgroup HRTIM_EC_DT_PRESCALER DEADTIME PRESCALER
00955   * @{
00956   * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG).
00957   */
00958 #define LL_HRTIM_DT_PRESCALER_MUL8    ((uint32_t)0x00000000U)                                         /*!< fDTG = fHRTIM * 8 */
00959 #define LL_HRTIM_DT_PRESCALER_MUL4    (HRTIM_DTR_DTPRSC_0)                                            /*!< fDTG = fHRTIM * 4 */
00960 #define LL_HRTIM_DT_PRESCALER_MUL2    (HRTIM_DTR_DTPRSC_1)                                            /*!< fDTG = fHRTIM * 2 */
00961 #define LL_HRTIM_DT_PRESCALER_DIV1    (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM */
00962 #define LL_HRTIM_DT_PRESCALER_DIV2    (HRTIM_DTR_DTPRSC_2)                                            /*!< fDTG = fHRTIM / 2 */
00963 #define LL_HRTIM_DT_PRESCALER_DIV4    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM / 4 */
00964 #define LL_HRTIM_DT_PRESCALER_DIV8    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1)                       /*!< fDTG = fHRTIM / 8 */
00965 #define LL_HRTIM_DT_PRESCALER_DIV16   (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)  /*!< fDTG = fHRTIM / 16 */
00966 /**
00967   * @}
00968   */
00969
00970 /** @defgroup HRTIM_EC_DT_RISING_SIGN DEADTIME RISING SIGN
00971   * @{
00972   * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.
00973   */
00974 #define LL_HRTIM_DT_RISING_POSITIVE    ((uint32_t)0x00000000U) /*!< Positive deadtime on rising edge */
00975 #define LL_HRTIM_DT_RISING_NEGATIVE    (HRTIM_DTR_SDTR)        /*!< Negative deadtime on rising edge */
00976 /**
00977   * @}
00978   */
00979
00980 /** @defgroup HRTIM_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN
00981   * @{
00982   * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.
00983   */
00984 #define LL_HRTIM_DT_FALLING_POSITIVE    ((uint32_t)0x00000000U) /*!< Positive deadtime on falling edge */
00985 #define LL_HRTIM_DT_FALLING_NEGATIVE    (HRTIM_DTR_SDTF)        /*!< Negative deadtime on falling edge */
00986 /**
00987   * @}
00988   */
00989
00990 /** @defgroup HRTIM_EC_CHP_PRESCALER CHOPPER MODE PRESCALER
00991   * @{
00992   * @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ).
00993   */
00994 #define LL_HRTIM_CHP_PRESCALER_DIV16  ((uint32_t)0x00000000U)                                                                     /*!< fCHPFRQ = fHRTIM / 16  */
00995 #define LL_HRTIM_CHP_PRESCALER_DIV32  (HRTIM_CHPR_CARFRQ_0)                                                                    /*!< fCHPFRQ = fHRTIM / 32  */
00996 #define LL_HRTIM_CHP_PRESCALER_DIV48  (HRTIM_CHPR_CARFRQ_1)                                                                    /*!< fCHPFRQ = fHRTIM / 48  */
00997 #define LL_HRTIM_CHP_PRESCALER_DIV64  (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 64  */
00998 #define LL_HRTIM_CHP_PRESCALER_DIV80  (HRTIM_CHPR_CARFRQ_2)                                                                    /*!< fCHPFRQ = fHRTIM / 80  */
00999 #define LL_HRTIM_CHP_PRESCALER_DIV96  (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 96  */
01000 #define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 112  */
01001 #define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 128  */
01002 #define LL_HRTIM_CHP_PRESCALER_DIV144 (HRTIM_CHPR_CARFRQ_3)                                                                    /*!< fCHPFRQ = fHRTIM / 144  */
01003 #define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 160  */
01004 #define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 176  */
01005 #define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 192  */
01006 #define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2)                                              /*!< fCHPFRQ = fHRTIM / 208  */
01007 #define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 224  */
01008 #define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                        /*!< fCHPFRQ = fHRTIM / 240  */
01009 #define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)  /*!< fCHPFRQ = fHRTIM / 256  */
01010 /**
01011  * @}
01012  */
01013
01014 /** @defgroup HRTIM_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE
01015   * @{
01016   * @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8).
01017   */
01018 #define LL_HRTIM_CHP_DUTYCYCLE_0    ((uint32_t)0x00000000U)                                              /*!< Only 1st pulse is present */
01019 #define LL_HRTIM_CHP_DUTYCYCLE_125  (HRTIM_CHPR_CARDTY_0)                                             /*!< Duty cycle of the carrier signal is 12.5 % */
01020 #define LL_HRTIM_CHP_DUTYCYCLE_250  (HRTIM_CHPR_CARDTY_1)                                             /*!< Duty cycle of the carrier signal is 25 % */
01021 #define LL_HRTIM_CHP_DUTYCYCLE_375  (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 37.5 % */
01022 #define LL_HRTIM_CHP_DUTYCYCLE_500  (HRTIM_CHPR_CARDTY_2)                                             /*!< Duty cycle of the carrier signal is 50 % */
01023 #define LL_HRTIM_CHP_DUTYCYCLE_625  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 62.5 % */
01024 #define LL_HRTIM_CHP_DUTYCYCLE_750  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1)                       /*!< Duty cycle of the carrier signal is 75 % */
01025 #define LL_HRTIM_CHP_DUTYCYCLE_875  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */
01026 /**
01027   * @}
01028   */
01029
01030 /** @defgroup HRTIM_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH
01031   * @{
01032   * @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier.
01033   */
01034 #define LL_HRTIM_CHP_PULSEWIDTH_16   ((uint32_t)0x00000000U)                                                                 /*!< tSTPW = tHRTIM x 16  */
01035 #define LL_HRTIM_CHP_PULSEWIDTH_32   (HRTIM_CHPR_STRPW_0)                                                                 /*!< tSTPW = tHRTIM x 32  */
01036 #define LL_HRTIM_CHP_PULSEWIDTH_48   (HRTIM_CHPR_STRPW_1)                                                                 /*!< tSTPW = tHRTIM x 48  */
01037 #define LL_HRTIM_CHP_PULSEWIDTH_64   (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 64  */
01038 #define LL_HRTIM_CHP_PULSEWIDTH_80   (HRTIM_CHPR_STRPW_2)                                                                 /*!< tSTPW = tHRTIM x 80  */
01039 #define LL_HRTIM_CHP_PULSEWIDTH_96   (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 96  */
01040 #define LL_HRTIM_CHP_PULSEWIDTH_112  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 112  */
01041 #define LL_HRTIM_CHP_PULSEWIDTH_128  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 128  */
01042 #define LL_HRTIM_CHP_PULSEWIDTH_144  (HRTIM_CHPR_STRPW_3)                                                                 /*!< tSTPW = tHRTIM x 144  */
01043 #define LL_HRTIM_CHP_PULSEWIDTH_160  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 160  */
01044 #define LL_HRTIM_CHP_PULSEWIDTH_176  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 176  */
01045 #define LL_HRTIM_CHP_PULSEWIDTH_192  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 192  */
01046 #define LL_HRTIM_CHP_PULSEWIDTH_208  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2)                                            /*!< tSTPW = tHRTIM x 208  */
01047 #define LL_HRTIM_CHP_PULSEWIDTH_224  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 224  */
01048 #define LL_HRTIM_CHP_PULSEWIDTH_240  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                       /*!< tSTPW = tHRTIM x 240  */
01049 #define LL_HRTIM_CHP_PULSEWIDTH_256  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)  /*!< tSTPW = tHRTIM x 256  */
01050 /**
01051   * @}
01052   */
01053
01054 /** @defgroup HRTIM_EC_CROSSBAR_INPUT CROSSBAR INPUT
01055   * @{
01056   * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
01057   */
01058 #define LL_HRTIM_CROSSBAR_NONE       ((uint32_t)0x00000000U) /*!< Reset the output set crossbar */
01059 #define LL_HRTIM_CROSSBAR_RESYNC     (HRTIM_SET1R_RESYNC)    /*!< Timer reset event coming solely from software or SYNC input forces an output level transision */
01060 #define LL_HRTIM_CROSSBAR_TIMPER     (HRTIM_SET1R_PER)       /*!< Timer period event forces an output level transision */
01061 #define LL_HRTIM_CROSSBAR_TIMCMP1    (HRTIM_SET1R_CMP1)      /*!< Timer compare 1 event forces an output level transision */
01062 #define LL_HRTIM_CROSSBAR_TIMCMP2    (HRTIM_SET1R_CMP2)      /*!< Timer compare 2 event forces an output level transision */
01063 #define LL_HRTIM_CROSSBAR_TIMCMP3    (HRTIM_SET1R_CMP3)      /*!< Timer compare 3 event forces an output level transision */
01064 #define LL_HRTIM_CROSSBAR_TIMCMP4    (HRTIM_SET1R_CMP4)      /*!< Timer compare 4 event forces an output level transision */
01065 #define LL_HRTIM_CROSSBAR_MASTERPER  (HRTIM_SET1R_MSTPER)    /*!< The master timer period event forces an output level transision */
01066 #define LL_HRTIM_CROSSBAR_MASTERCMP1 (HRTIM_SET1R_MSTCMP1)   /*!< Master Timer compare 1 event forces an output level transision */
01067 #define LL_HRTIM_CROSSBAR_MASTERCMP2 (HRTIM_SET1R_MSTCMP2)   /*!< Master Timer compare 2 event forces an output level transision */
01068 #define LL_HRTIM_CROSSBAR_MASTERCMP3 (HRTIM_SET1R_MSTCMP3)   /*!< Master Timer compare 3 event forces an output level transision */
01069 #define LL_HRTIM_CROSSBAR_MASTERCMP4 (HRTIM_SET1R_MSTCMP4)   /*!< Master Timer compare 4 event forces an output level transision */
01070 #define LL_HRTIM_CROSSBAR_TIMEV_1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces an output level transision */
01071 #define LL_HRTIM_CROSSBAR_TIMEV_2    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces an output level transision */
01072 #define LL_HRTIM_CROSSBAR_TIMEV_3    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces an output level transision */
01073 #define LL_HRTIM_CROSSBAR_TIMEV_4    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces an output level transision */
01074 #define LL_HRTIM_CROSSBAR_TIMEV_5    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces an output level transision */
01075 #define LL_HRTIM_CROSSBAR_TIMEV_6    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces an output level transision */
01076 #define LL_HRTIM_CROSSBAR_TIMEV_7    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces an output level transision */
01077 #define LL_HRTIM_CROSSBAR_TIMEV_8    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces an output level transision */
01078 #define LL_HRTIM_CROSSBAR_TIMEV_9    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces an output level transision */
01079 #define LL_HRTIM_CROSSBAR_EEV_1      (HRTIM_SET1R_EXTVNT1)   /*!< External event 1 forces an output level transision */
01080 #define LL_HRTIM_CROSSBAR_EEV_2      (HRTIM_SET1R_EXTVNT2)   /*!< External event 2 forces an output level transision */
01081 #define LL_HRTIM_CROSSBAR_EEV_3      (HRTIM_SET1R_EXTVNT3)   /*!< External event 3 forces an output level transision */
01082 #define LL_HRTIM_CROSSBAR_EEV_4      (HRTIM_SET1R_EXTVNT4)   /*!< External event 4 forces an output level transision */
01083 #define LL_HRTIM_CROSSBAR_EEV_5      (HRTIM_SET1R_EXTVNT5)   /*!< External event 5 forces an output level transision */
01084 #define LL_HRTIM_CROSSBAR_EEV_6      (HRTIM_SET1R_EXTVNT6)   /*!< External event 6 forces an output level transision */
01085 #define LL_HRTIM_CROSSBAR_EEV_7      (HRTIM_SET1R_EXTVNT7)   /*!< External event 7 forces an output level transision */
01086 #define LL_HRTIM_CROSSBAR_EEV_8      (HRTIM_SET1R_EXTVNT8)   /*!< External event 8 forces an output level transision */
01087 #define LL_HRTIM_CROSSBAR_EEV_9      (HRTIM_SET1R_EXTVNT9)   /*!< External event 9 forces an output level transision */
01088 #define LL_HRTIM_CROSSBAR_EEV_10     (HRTIM_SET1R_EXTVNT10)  /*!< External event 10 forces an output level transision */
01089 #define LL_HRTIM_CROSSBAR_UPDATE     (HRTIM_SET1R_UPDATE)    /*!< Timer register update event forces an output level transision */
01090 /**
01091   * @}
01092   */
01093
01094 /** @defgroup HRTIM_EC_OUT_POLARITY OUPUT_POLARITY
01095   * @{
01096   * @brief Constants defining the polarity of a timer output.
01097   */
01098 #define LL_HRTIM_OUT_POSITIVE_POLARITY    ((uint32_t)0x00000000U) /*!< Output is acitve HIGH */
01099 #define LL_HRTIM_OUT_NEGATIVE_POLARITY     (HRTIM_OUTR_POL1)       /*!< Output is active LOW */
01100 /**
01101   * @}
01102   */
01103
01104 /** @defgroup HRTIM_EC_OUT_IDLEMODE OUTPUT IDLE MODE
01105   * @{
01106   * @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.
01107   */
01108 #define LL_HRTIM_OUT_NO_IDLE             ((uint32_t)0x00000000U)/*!< The output is not affected by the burst mode operation */
01109 #define LL_HRTIM_OUT_IDLE_WHEN_BURST     (HRTIM_OUTR_IDLM1)     /*!< The output is in idle state when requested by the burst mode controller */
01110 /**
01111  * @}
01112  */
01113
01114 /** @defgroup HRTIM_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL
01115   * @{
01116   * @brief Constants defining the output level when output is in IDLE state
01117   */
01118 #define LL_HRTIM_OUT_IDLELEVEL_INACTIVE   ((uint32_t)0x00000000U)/*!< Output at inactive level when in IDLE state */
01119 #define LL_HRTIM_OUT_IDLELEVEL_ACTIVE     (HRTIM_OUTR_IDLES1)   /*!< Output at active level when in IDLE state */
01120 /**
01121   * @}
01122   */
01123
01124 /** @defgroup HRTIM_EC_OUT_FAULTSTATE OUTPUT FAULT STATE
01125  * @{
01126  * @brief Constants defining the output level when output is in FAULT state.
01127  */
01128 #define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION ((uint32_t)0x00000000U)                      /*!< The output is not affected by the fault input */
01129 #define LL_HRTIM_OUT_FAULTSTATE_ACTIVE    (HRTIM_OUTR_FAULT1_0)                        /*!< Output at active level when in FAULT state */
01130 #define LL_HRTIM_OUT_FAULTSTATE_INACTIVE  (HRTIM_OUTR_FAULT1_1)                        /*!< Output at inactive level when in FAULT state */
01131 #define LL_HRTIM_OUT_FAULTSTATE_HIGHZ     (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0)  /*!< Output is tri-stated when in FAULT state */
01132 /**
01133   * @}
01134   */
01135
01136 /** @defgroup HRTIM_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE
01137   * @{
01138   * @brief Constants defining whether or not chopper mode is enabled for a timer output.
01139   */
01140 #define LL_HRTIM_OUT_CHOPPERMODE_DISABLED   ((uint32_t)0x00000000U) /*!< Output signal is not altered  */
01141 #define LL_HRTIM_OUT_CHOPPERMODE_ENABLED    (HRTIM_OUTR_CHP1)       /*!< Output signal is chopped by a carrier signal  */
01142 /**
01143   * @}
01144   */
01145
01146 /** @defgroup HRTIM_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE
01147   * @{
01148   * @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state
01149 during a programmable period before the output takes its idle state.
01150   */
01151 #define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR   ((uint32_t)0x00000000U)/*!< The programmed Idle state is applied immediately to the Output */
01152 #define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED   (HRTIM_OUTR_DIDL1)     /*!< Deadtime is inserted on output before entering the idle mode */
01153 /**
01154   * @}
01155   */
01156 /** @defgroup HRTIM_EC_OUT_LEVEL OUTPUT LEVEL
01157   * @{
01158   * @brief Constants defining the level of a timer output.
01159   */
01160 #define LL_HRTIM_OUT_LEVEL_INACTIVE   ((uint32_t)0x00000000U)/*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */
01161 #define LL_HRTIM_OUT_LEVEL_ACTIVE     ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */
01162 /**
01163   * @}
01164   */
01165
01166 /** @defgroup HRTIM_EC_EE_SRC EXTERNAL EVENT SOURCE
01167   * @{
01168   * @brief Constants defining available sources associated to external events.
01169   */
01170 #define LL_HRTIM_EE_SRC_1         ((uint32_t)0x00000000U)                        /*!< External event source 1 (EExSrc1)*/
01171 #define LL_HRTIM_EE_SRC_2         (HRTIM_EECR1_EE1SRC_0)                         /*!< External event source 2 (EExSrc2) */
01172 #define LL_HRTIM_EE_SRC_3         (HRTIM_EECR1_EE1SRC_1)                         /*!< External event source 3 (EExSrc3) */
01173 #define LL_HRTIM_EE_SRC_4         (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)  /*!< External event source 4 (EExSrc4) */
01174 /**
01175   * @}
01176   */
01177 /** @defgroup HRTIM_EC_EE_POLARITY EXTERNAL EVENT POLARITY
01178   * @{
01179   * @brief Constants defining the polarity of an external event.
01180   */
01181 #define LL_HRTIM_EE_POLARITY_HIGH    ((uint32_t)0x00000000U) /*!< External event is active high */
01182 #define LL_HRTIM_EE_POLARITY_LOW     (HRTIM_EECR1_EE1POL)    /*!< External event is active low */
01183 /**
01184   * @}
01185   */
01186
01187 /** @defgroup HRTIM_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY
01188   * @{
01189   * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.
01190   */
01191 #define LL_HRTIM_EE_SENSITIVITY_LEVEL          ((uint32_t)0x00000000U)                        /*!< External event is active on level */
01192 #define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE     (HRTIM_EECR1_EE1SNS_0)                         /*!< External event is active on Rising edge */
01193 #define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE    (HRTIM_EECR1_EE1SNS_1)                         /*!< External event is active on Falling edge */
01194 #define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES      (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0)  /*!< External event is active on Rising and Falling edges */
01195 /**
01196   * @}
01197   */
01198
01199 /** @defgroup HRTIM_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE
01200   * @{
01201   * @brief Constants defining whether or not an external event is programmed in fast mode.
01202   */
01203 #define LL_HRTIM_EE_FASTMODE_DISABLE         ((uint32_t)0x00000000U)  /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
01204 #define LL_HRTIM_EE_FASTMODE_ENABLE          (HRTIM_EECR1_EE1FAST)    /*!< External Event is acting asynchronously on outputs (low latency mode) */
01205 /**
01206   * @}
01207   */
01208
01209 /** @defgroup HRTIM_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER
01210   * @{
01211   * @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied.
01212   */
01213 #define LL_HRTIM_EE_FILTER_NONE      ((uint32_t)0x00000000U)                                                               /*!< Filter disabled */
01214 #define LL_HRTIM_EE_FILTER_1         (HRTIM_EECR3_EE6F_0)                                                                  /*!< fSAMPLING = fHRTIM, N=2 */
01215 #define LL_HRTIM_EE_FILTER_2         (HRTIM_EECR3_EE6F_1)                                                                  /*!< fSAMPLING = fHRTIM, N=4 */
01216 #define LL_HRTIM_EE_FILTER_3         (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING = fHRTIM, N=8 */
01217 #define LL_HRTIM_EE_FILTER_4         (HRTIM_EECR3_EE6F_2)                                                                  /*!< fSAMPLING = fEEVS/2, N=6 */
01218 #define LL_HRTIM_EE_FILTER_5         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING = fEEVS/2, N=8 */
01219 #define LL_HRTIM_EE_FILTER_6         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING = fEEVS/4, N=6 */
01220 #define LL_HRTIM_EE_FILTER_7         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING = fEEVS/4, N=8 */
01221 #define LL_HRTIM_EE_FILTER_8         (HRTIM_EECR3_EE6F_3)                                                                  /*!< fSAMPLING = fEEVS/8, N=6 */
01222 #define LL_HRTIM_EE_FILTER_9         (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING = fEEVS/8, N=8 */
01223 #define LL_HRTIM_EE_FILTER_10        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING = fEEVS/16, N=5 */
01224 #define LL_HRTIM_EE_FILTER_11        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING = fEEVS/16, N=6 */
01225 #define LL_HRTIM_EE_FILTER_12        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2)                                             /*!< fSAMPLING = fEEVS/16, N=8 */
01226 #define LL_HRTIM_EE_FILTER_13        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_0)                       /*!< fSAMPLING = fEEVS/32, N=5 */
01227 #define LL_HRTIM_EE_FILTER_14        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1)                       /*!< fSAMPLING = fEEVS/32, N=6 */
01228 #define LL_HRTIM_EE_FILTER_15        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)  /*!< fSAMPLING = fEEVS/32, N=8 */
01229 /**
01230   * @}
01231   */
01232
01233 /** @defgroup HRTIM_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER
01234   * @{
01235   * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.
01236   */
01237 #define LL_HRTIM_EE_PRESCALER_DIV1    ((uint32_t)0x00000000U)                     /*!< fEEVS = fHRTIM */
01238 #define LL_HRTIM_EE_PRESCALER_DIV2    (HRTIM_EECR3_EEVSD_0)                       /*!< fEEVS = fHRTIM / 2 */
01239 #define LL_HRTIM_EE_PRESCALER_DIV4    (HRTIM_EECR3_EEVSD_1)                       /*!< fEEVS = fHRTIM / 4 */
01240 #define LL_HRTIM_EE_PRESCALER_DIV8    (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */
01241 /**
01242   * @}
01243   */
01244
01245 /** @defgroup HRTIM_EC_FLT_SRC FAULT SOURCE
01246   * @{
01247   * @brief Constants defining whether a faults is be triggered by any external or internal fault source.
01248   */
01249 #define LL_HRTIM_FLT_SRC_DIGITALINPUT      ((uint32_t)0x00000000U)    /*!< Fault input is FLT input pin */
01250 #define LL_HRTIM_FLT_SRC_INTERNAL          (HRTIM_FLTINR1_FLT1SRC)    /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
01251 /**
01252   * @}
01253   */
01254
01255 /** @defgroup HRTIM_EC_FLT_POLARITY FAULT POLARITY
01256   * @{
01257   * @brief Constants defining the polarity of a fault event.
01258   */
01259 #define LL_HRTIM_FLT_POLARITY_LOW     ((uint32_t)0x00000000U)  /*!< Fault input is active low */
01260 #define LL_HRTIM_FLT_POLARITY_HIGH    (HRTIM_FLTINR1_FLT1P)    /*!< Fault input is active high */
01261 /**
01262   * @}
01263   */
01264
01265 /** @defgroup HRTIM_EC_FLT_FILTER FAULT DIGITAL FILTER
01266   * @{
01267   * @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied.
01268   */
01269 #define LL_HRTIM_FLT_FILTER_NONE      ((uint32_t)0x00000000U)                                                                          /*!< Filter disabled */
01270 #define LL_HRTIM_FLT_FILTER_1         (HRTIM_FLTINR1_FLT1F_0)                                                                          /*!< fSAMPLING= fHRTIM, N=2 */
01271 #define LL_HRTIM_FLT_FILTER_2         (HRTIM_FLTINR1_FLT1F_1)                                                                          /*!< fSAMPLING= fHRTIM, N=4 */
01272 #define LL_HRTIM_FLT_FILTER_3         (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fHRTIM, N=8 */
01273 #define LL_HRTIM_FLT_FILTER_4         (HRTIM_FLTINR1_FLT1F_2)                                                                          /*!< fSAMPLING= fFLTS/2, N=6 */
01274 #define LL_HRTIM_FLT_FILTER_5         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/2, N=8 */
01275 #define LL_HRTIM_FLT_FILTER_6         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/4, N=6 */
01276 #define LL_HRTIM_FLT_FILTER_7         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/4, N=8 */
01277 #define LL_HRTIM_FLT_FILTER_8         (HRTIM_FLTINR1_FLT1F_3)                                                                          /*!< fSAMPLING= fFLTS/8, N=6 */
01278 #define LL_HRTIM_FLT_FILTER_9         (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/8, N=8 */
01279 #define LL_HRTIM_FLT_FILTER_10        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/16, N=5 */
01280 #define LL_HRTIM_FLT_FILTER_11        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/16, N=6 */
01281 #define LL_HRTIM_FLT_FILTER_12        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2)                                                  /*!< fSAMPLING= fFLTS/16, N=8 */
01282 #define LL_HRTIM_FLT_FILTER_13        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/32, N=5 */
01283 #define LL_HRTIM_FLT_FILTER_14        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                          /*!< fSAMPLING= fFLTS/32, N=6 */
01284 #define LL_HRTIM_FLT_FILTER_15        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)  /*!< fSAMPLING= fFLTS/32, N=8 */
01285 /**
01286   * @}
01287   */
01288
01289 /** @defgroup HRTIM_EC_FLT_PRESCALER BURST FAULT PRESCALER
01290   * @{
01291   * @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used  by the digital filters.
01292   */
01293 #define LL_HRTIM_FLT_PRESCALER_DIV1    ((uint32_t)0x00000000U)                         /*!< fFLTS = fHRTIM */
01294 #define LL_HRTIM_FLT_PRESCALER_DIV2    (HRTIM_FLTINR2_FLTSD_0)                         /*!< fFLTS = fHRTIM / 2 */
01295 #define LL_HRTIM_FLT_PRESCALER_DIV4    (HRTIM_FLTINR2_FLTSD_1)                         /*!< fFLTS = fHRTIM / 4 */
01296 #define LL_HRTIM_FLT_PRESCALER_DIV8    (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */
01297 /**
01298   * @}
01299   */
01300
01301 /** @defgroup HRTIM_EC_BM_MODE BURST MODE OPERATING MODE
01302   * @{
01303   * @brief Constants defining if the burst mode is entered once or if it is continuously operating.
01304   */
01305 #define LL_HRTIM_BM_MODE_SINGLESHOT ((uint32_t)0x00000000U) /*!< Burst mode operates in single shot mode */
01306 #define LL_HRTIM_BM_MODE_CONTINOUS   (HRTIM_BMCR_BMOM)      /*!< Burst mode operates in continuous mode */
01307 /**
01308   * @}
01309   */
01310
01311 /** @defgroup HRTIM_EC_BM_CLKSRC BURST MODE CLOCK SOURCE
01312   * @{
01313   * @brief Constants defining the clock source for the burst mode counter.
01314   */
01315 #define LL_HRTIM_BM_CLKSRC_MASTER     ((uint32_t)0x00000000U)                                         /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
01316 #define LL_HRTIM_BM_CLKSRC_TIMER_A    (HRTIM_BMCR_BMCLK_0)                                            /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
01317 #define LL_HRTIM_BM_CLKSRC_TIMER_B    (HRTIM_BMCR_BMCLK_1)                                            /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
01318 #define LL_HRTIM_BM_CLKSRC_TIMER_C    (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
01319 #define LL_HRTIM_BM_CLKSRC_TIMER_D    (HRTIM_BMCR_BMCLK_2)                                            /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
01320 #define LL_HRTIM_BM_CLKSRC_TIMER_E    (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
01321 #define LL_HRTIM_BM_CLKSRC_TIM16_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1)                       /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
01322 #define LL_HRTIM_BM_CLKSRC_TIM17_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)  /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
01323 #define LL_HRTIM_BM_CLKSRC_TIM7_TRGO  (HRTIM_BMCR_BMCLK_3)                                            /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
01324 #define LL_HRTIM_BM_CLKSRC_FHRTIM     (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1)                       /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
01325 /**
01326   * @}
01327   */
01328
01329 /** @defgroup HRTIM_EC_BM_PRESCALER BURST MODE PRESCALER
01330   * @{
01331   * @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST).
01332   */
01333 #define LL_HRTIM_BM_PRESCALER_DIV1     ((uint32_t)0x00000000U)                                                                 /*!< fBRST = fHRTIM */
01334 #define LL_HRTIM_BM_PRESCALER_DIV2     (HRTIM_BMCR_BMPRSC_0)                                                                   /*!< fBRST = fHRTIM/2 */
01335 #define LL_HRTIM_BM_PRESCALER_DIV4     (HRTIM_BMCR_BMPRSC_1)                                                                   /*!< fBRST = fHRTIM/4 */
01336 #define LL_HRTIM_BM_PRESCALER_DIV8     (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/8 */
01337 #define LL_HRTIM_BM_PRESCALER_DIV16    (HRTIM_BMCR_BMPRSC_2)                                                                   /*!< fBRST = fHRTIM/16 */
01338 #define LL_HRTIM_BM_PRESCALER_DIV32    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/32 */
01339 #define LL_HRTIM_BM_PRESCALER_DIV64    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/64 */
01340 #define LL_HRTIM_BM_PRESCALER_DIV128   (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/128 */
01341 #define LL_HRTIM_BM_PRESCALER_DIV256   (HRTIM_BMCR_BMPRSC_3)                                                                   /*!< fBRST = fHRTIM/256 */
01342 #define LL_HRTIM_BM_PRESCALER_DIV512   (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/512 */
01343 #define LL_HRTIM_BM_PRESCALER_DIV1024  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/1024 */
01344 #define LL_HRTIM_BM_PRESCALER_DIV2048  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/2048*/
01345 #define LL_HRTIM_BM_PRESCALER_DIV4096  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2)                                             /*!< fBRST = fHRTIM/4096 */
01346 #define LL_HRTIM_BM_PRESCALER_DIV8192  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/8192 */
01347 #define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                       /*!< fBRST = fHRTIM/16384 */
01348 #define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
01349 /**
01350   * @}
01351   */
01352
01353 /** @defgroup HRTIM_EC_BM_TRIG HRTIM BURST MODE TRIGGER
01354   * @{
01355   * @brief Constants defining the events that can be used to trig the burst mode operation.
01356   */
01357 #define LL_HRTIM_BM_TRIG_NONE               (uint32_t)0x00000000    /*!<  No trigger */
01358 #define LL_HRTIM_BM_TRIG_MASTER_RESET       (HRTIM_BMTRGR_MSTRST)   /*!<  Master timer reset event is starting the burst mode operation */
01359 #define LL_HRTIM_BM_TRIG_MASTER_REPETITION  (HRTIM_BMTRGR_MSTREP)   /*!<  Master timer repetition event is starting the burst mode operation */
01360 #define LL_HRTIM_BM_TRIG_MASTER_CMP1        (HRTIM_BMTRGR_MSTCMP1)  /*!<  Master timer compare 1 event is starting the burst mode operation */
01361 #define LL_HRTIM_BM_TRIG_MASTER_CMP2        (HRTIM_BMTRGR_MSTCMP2)  /*!<  Master timer compare 2 event is starting the burst mode operation */
01362 #define LL_HRTIM_BM_TRIG_MASTER_CMP3        (HRTIM_BMTRGR_MSTCMP3)  /*!<  Master timer compare 3 event is starting the burst mode operation */
01363 #define LL_HRTIM_BM_TRIG_MASTER_CMP4        (HRTIM_BMTRGR_MSTCMP4)  /*!<  Master timer compare 4 event is starting the burst mode operation */
01364 #define LL_HRTIM_BM_TRIG_TIMA_RESET         (HRTIM_BMTRGR_TARST)    /*!< Timer A reset event is starting the burst mode operation */
01365 #define LL_HRTIM_BM_TRIG_TIMA_REPETITION    (HRTIM_BMTRGR_TAREP)    /*!< Timer A repetition event is starting the burst mode operation */
01366 #define LL_HRTIM_BM_TRIG_TIMA_CMP1          (HRTIM_BMTRGR_TACMP1)   /*!< Timer A compare 1 event is starting the burst mode operation */
01367 #define LL_HRTIM_BM_TRIG_TIMA_CMP2          (HRTIM_BMTRGR_TACMP2)   /*!< Timer A compare 2 event is starting the burst mode operation */
01368 #define LL_HRTIM_BM_TRIG_TIMB_RESET         (HRTIM_BMTRGR_TBRST)    /*!< Timer B reset event is starting the burst mode operation */
01369 #define LL_HRTIM_BM_TRIG_TIMB_REPETITION    (HRTIM_BMTRGR_TBREP)    /*!< Timer B repetition event is starting the burst mode operation */
01370 #define LL_HRTIM_BM_TRIG_TIMB_CMP1          (HRTIM_BMTRGR_TBCMP1)   /*!< Timer B compare 1 event is starting the burst mode operation */
01371 #define LL_HRTIM_BM_TRIG_TIMB_CMP2          (HRTIM_BMTRGR_TBCMP2)   /*!< Timer B compare 2 event is starting the burst mode operation */
01372 #define LL_HRTIM_BM_TRIG_TIMC_RESET         (HRTIM_BMTRGR_TCRST)    /*!< Timer C resetevent is starting the burst mode operation  */
01373 #define LL_HRTIM_BM_TRIG_TIMC_REPETITION    (HRTIM_BMTRGR_TCREP)    /*!< Timer C repetition event is starting the burst mode operation */
01374 #define LL_HRTIM_BM_TRIG_TIMC_CMP1          (HRTIM_BMTRGR_TCCMP1)   /*!< Timer C compare 1 event is starting the burst mode operation */
01375 #define LL_HRTIM_BM_TRIG_TIMC_CMP2          (HRTIM_BMTRGR_TCCMP2)   /*!< Timer C compare 2 event is starting the burst mode operation */
01376 #define LL_HRTIM_BM_TRIG_TIMD_RESET         (HRTIM_BMTRGR_TDRST)    /*!< Timer D reset event is starting the burst mode operation */
01377 #define LL_HRTIM_BM_TRIG_TIMD_REPETITION    (HRTIM_BMTRGR_TDREP)    /*!< Timer D repetition event is starting the burst mode operation */
01378 #define LL_HRTIM_BM_TRIG_TIMD_CMP1          (HRTIM_BMTRGR_TDCMP1)   /*!< Timer D compare 1 event is starting the burst mode operation */
01379 #define LL_HRTIM_BM_TRIG_TIMD_CMP2          (HRTIM_BMTRGR_TDCMP2)   /*!< Timer D compare 2 event is starting the burst mode operation */
01380 #define LL_HRTIM_BM_TRIG_TIME_RESET         (HRTIM_BMTRGR_TERST)    /*!< Timer E reset event is starting the burst mode operation */
01381 #define LL_HRTIM_BM_TRIG_TIME_REPETITION    (HRTIM_BMTRGR_TEREP)    /*!< Timer E repetition event is starting the burst mode operation */
01382 #define LL_HRTIM_BM_TRIG_TIME_CMP1          (HRTIM_BMTRGR_TECMP1)   /*!< Timer E compare 1 event is starting the burst mode operation */
01383 #define LL_HRTIM_BM_TRIG_TIME_CMP2          (HRTIM_BMTRGR_TECMP2)   /*!< Timer E compare 2 event is starting the burst mode operation */
01384 #define LL_HRTIM_BM_TRIG_TIMA_EVENT7        (HRTIM_BMTRGR_TAEEV7)   /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst
01385 mode operation  */
01386 #define LL_HRTIM_BM_TRIG_TIMD_EVENT8        (HRTIM_BMTRGR_TDEEV8)   /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst
01387 mode operation  */
01388 #define LL_HRTIM_BM_TRIG_EVENT_7            (HRTIM_BMTRGR_EEV7)     /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */
01389 #define LL_HRTIM_BM_TRIG_EVENT_8            (HRTIM_BMTRGR_EEV8)     /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */
01390 #define LL_HRTIM_BM_TRIG_EVENT_ONCHIP       (HRTIM_BMTRGR_OCHPEV)   /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode
01391 operation */
01392 /**
01393   * @}
01394   */
01395
01396 /** @defgroup HRTIM_EC_BM_STATUS HRTIM BURST MODE STATUS
01397   * @{
01398   * @brief Constants defining the operating state of the burst mode controller.
01399   */
01400 #define LL_HRTIM_BM_STATUS_NORMAL        ((uint32_t) 0x00000000U) /*!< Normal operation */
01401 #define LL_HRTIM_BM_STATUS_BURST_ONGOING (HRTIM_BMCR_BMSTAT)     /*!< Burst operation on-going */
01402 /**
01403   * @}
01404   */
01405
01406 /**
01407   * @}
01408   */
01409
01410 /* Exported macro ------------------------------------------------------------*/
01411 /** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros
01412   * @{
01413   */
01414
01415 /** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros
01416   * @{
01417   */
01418
01419 /**
01420   * @brief  Write a value in HRTIM register
01421   * @param  __INSTANCE__ HRTIM Instance
01422   * @param  __REG__ Register to be written
01423   * @param  __VALUE__ Value to be written in the register
01424   * @retval None
01425   */
01426 #define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
01427
01428 /**
01429   * @brief  Read a value in HRTIM register
01430   * @param  __INSTANCE__ HRTIM Instance
01431   * @param  __REG__ Register to be read
01432   * @retval Register value
01433   */
01434 #define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
01435 /**
01436   * @}
01437   */
01438
01439 /** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros
01440   * @{
01441   */
01442 /**
01443   * @brief  HELPER macro returning the output state from output enable/disable status
01444   * @param  __OUTPUT_STATUS_EN__ output enable status
01445   * @param  __OUTPUT_STATUS_DIS__ output Disable status
01446   * @retval Returned value can be one of the following values:
01447   *         @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE
01448   *         @arg @ref LL_HRTIM_OUTPUTSTATE_RUN
01449   *         @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT
01450 */
01451 #define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\
01452   (((__OUTPUT_STATUS_EN__) == 1) ?  LL_HRTIM_OUTPUTSTATE_RUN :\
01453    ((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT)
01454 /**
01455   * @}
01456   */
01457
01458
01459 /**
01460   * @}
01461   */
01462
01463 /* Exported functions --------------------------------------------------------*/
01464 /** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions
01465   * @{
01466   */
01467 /** @defgroup HRTIM_EF_HRTIM_Control HRTIM_Control
01468   * @{
01469   */
01470
01471 /**
01472   * @brief  Select the HRTIM synchronization input source.
01473   * @note This function must not be called when  the concerned timer(s) is (are) enabled .
01474   * @rmtoll MCR          SYNCIN        LL_HRTIM_SetSyncInSrc
01475   * @param  HRTIMx High Resolution Timer instance
01476   * @param  SyncInSrc This parameter can be one of the following values:
01477   *         @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
01478   *         @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
01479   *         @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
01480   * @retval None
01481   */
01482 __STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncInSrc)
01483 {
01484   MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN, SyncInSrc);
01485 }
01486
01487 /**
01488   * @brief  Get actual HRTIM synchronization input source.
01489   * @rmtoll MCR          SYNCIN        LL_HRTIM_SetSyncInSrc
01490   * @param  HRTIMx High Resolution Timer instance
01491   * @retval SyncInSrc Returned value can be one of the following values:
01492   *         @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
01493   *         @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
01494   *         @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
01495   */
01496 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(HRTIM_TypeDef *HRTIMx)
01497 {
01498   return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN));
01499 }
01500
01501 /**
01502   * @brief  Configure the HRTIM synchronization output.
01503   * @rmtoll MCR          SYNCSRC      LL_HRTIM_ConfigSyncOut\n
01504   *         MCR          SYNCOUT      LL_HRTIM_ConfigSyncOut
01505   * @param  HRTIMx High Resolution Timer instance
01506   * @param  Config This parameter can be one of the following values:
01507   *         @arg @ref LL_HRTIM_SYNCOUT_DISABLED
01508   *         @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
01509   *         @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
01510   * @param  Src This parameter can be one of the following values:
01511   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
01512   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
01513   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
01514   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
01515   * @retval None
01516   */
01517 __STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src)
01518 {
01519   MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src));
01520 }
01521
01522 /**
01523   * @brief  Set the routing and conditioning of the synchronization output event.
01524   * @rmtoll MCR          SYNCOUT      LL_HRTIM_SetSyncOutConfig
01525   * @note This function can be called only when the master timer is enabled.
01526   * @param  HRTIMx High Resolution Timer instance
01527   * @param  SyncOutConfig This parameter can be one of the following values:
01528   *         @arg @ref LL_HRTIM_SYNCOUT_DISABLED
01529   *         @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
01530   *         @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
01531   * @retval None
01532   */
01533 __STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutConfig)
01534 {
01535   MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT, SyncOutConfig);
01536 }
01537
01538 /**
01539   * @brief  Get actual routing and conditioning of the synchronization output event.
01540   * @rmtoll MCR          SYNCOUT      LL_HRTIM_GetSyncOutConfig
01541   * @param  HRTIMx High Resolution Timer instance
01542   * @retval SyncOutConfig Returned value can be one of the following values:
01543   *         @arg @ref LL_HRTIM_SYNCOUT_DISABLED
01544   *         @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
01545   *         @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
01546   */
01547 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(HRTIM_TypeDef *HRTIMx)
01548 {
01549   return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT));
01550 }
01551
01552 /**
01553   * @brief  Set the source and event to be sent on the HRTIM synchronization output.
01554   * @rmtoll MCR          SYNCSRC      LL_HRTIM_SetSyncOutSrc
01555   * @param  HRTIMx High Resolution Timer instance
01556   * @param  SyncOutSrc This parameter can be one of the following values:
01557   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
01558   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
01559   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
01560   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
01561   * @retval None
01562   */
01563 __STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutSrc)
01564 {
01565   MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC, SyncOutSrc);
01566 }
01567
01568 /**
01569   * @brief  Get actual  source and event sent on the HRTIM synchronization output.
01570   * @rmtoll MCR          SYNCSRC      LL_HRTIM_GetSyncOutSrc
01571   * @param  HRTIMx High Resolution Timer instance
01572   * @retval SyncOutSrc Returned value can be one of the following values:
01573   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
01574   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
01575   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
01576   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
01577   */
01578 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(HRTIM_TypeDef *HRTIMx)
01579 {
01580   return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC));
01581 }
01582
01583 /**
01584   * @brief  Disable (temporarily) update event generation.
01585   * @rmtoll CR1          MUDIS         LL_HRTIM_SuspendUpdate\n
01586   *         CR1          TAUDIS        LL_HRTIM_SuspendUpdate\n
01587   *         CR1          TBUDIS        LL_HRTIM_SuspendUpdate\n
01588   *         CR1          TCUDIS        LL_HRTIM_SuspendUpdate\n
01589   *         CR1          TDUDIS        LL_HRTIM_SuspendUpdate\n
01590   *         CR1          TEUDIS        LL_HRTIM_SuspendUpdate
01591   * @note Allow to temporarily disable the transfer from preload to active
01592   *      registers, whatever the selected update event. This allows to modify
01593   *      several registers in multiple timers.
01594   * @param  HRTIMx High Resolution Timer instance
01595   * @param  Timers This parameter can be a combination of the following values:
01596   *         @arg @ref LL_HRTIM_TIMER_MASTER
01597   *         @arg @ref LL_HRTIM_TIMER_A
01598   *         @arg @ref LL_HRTIM_TIMER_B
01599   *         @arg @ref LL_HRTIM_TIMER_C
01600   *         @arg @ref LL_HRTIM_TIMER_D
01601   *         @arg @ref LL_HRTIM_TIMER_E
01602   * @retval None
01603   */
01604 __STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
01605 {
01606   SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
01607 }
01608
01609 /**
01610   * @brief  Enable update event generation.
01611   * @rmtoll CR1          MUDIS         LL_HRTIM_ResumeUpdate\n
01612   *         CR1          TAUDIS        LL_HRTIM_ResumeUpdate\n
01613   *         CR1          TBUDIS        LL_HRTIM_ResumeUpdate\n
01614   *         CR1          TCUDIS        LL_HRTIM_ResumeUpdate\n
01615   *         CR1          TDUDIS        LL_HRTIM_ResumeUpdate\n
01616   *         CR1          TEUDIS        LL_HRTIM_ResumeUpdate
01617   * @note The regular update event takes place.
01618   * @param  HRTIMx High Resolution Timer instance
01619   * @param  Timers This parameter can be a combination of the following values:
01620   *         @arg @ref LL_HRTIM_TIMER_MASTER
01621   *         @arg @ref LL_HRTIM_TIMER_A
01622   *         @arg @ref LL_HRTIM_TIMER_B
01623   *         @arg @ref LL_HRTIM_TIMER_C
01624   *         @arg @ref LL_HRTIM_TIMER_D
01625   *         @arg @ref LL_HRTIM_TIMER_E
01626   * @retval None
01627   */
01628 __STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
01629 {
01630   CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
01631 }
01632
01633 /**
01634   * @brief  Force an immediate transfer from the preload to the active register .
01635   * @rmtoll CR2          MSWU          LL_HRTIM_ForceUpdate\n
01636   *         CR2          TASWU         LL_HRTIM_ForceUpdate\n
01637   *         CR2          TBSWU         LL_HRTIM_ForceUpdate\n
01638   *         CR2          TCSWU         LL_HRTIM_ForceUpdate\n
01639   *         CR2          TDSWU         LL_HRTIM_ForceUpdate\n
01640   *         CR2          TESWU         LL_HRTIM_ForceUpdate
01641   * @note Any pending update request is cancelled.
01642   * @param  HRTIMx High Resolution Timer instance
01643   * @param  Timers This parameter can be a combination of the following values:
01644   *         @arg @ref LL_HRTIM_TIMER_MASTER
01645   *         @arg @ref LL_HRTIM_TIMER_A
01646   *         @arg @ref LL_HRTIM_TIMER_B
01647   *         @arg @ref LL_HRTIM_TIMER_C
01648   *         @arg @ref LL_HRTIM_TIMER_D
01649   *         @arg @ref LL_HRTIM_TIMER_E
01650   * @retval None
01651   */
01652 __STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
01653 {
01654   SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK));
01655 }
01656
01657 /**
01658   * @brief  Reset the HRTIM timer(s) counter.
01659   * @rmtoll CR2          MRST          LL_HRTIM_CounterReset\n
01660   *         CR2          TARST         LL_HRTIM_CounterReset\n
01661   *         CR2          TBRST         LL_HRTIM_CounterReset\n
01662   *         CR2          TCRST         LL_HRTIM_CounterReset\n
01663   *         CR2          TDRST         LL_HRTIM_CounterReset\n
01664   *         CR2          TERST         LL_HRTIM_CounterReset
01665   * @param  HRTIMx High Resolution Timer instance
01666   * @param  Timers This parameter can be a combination of the following values:
01667   *         @arg @ref LL_HRTIM_TIMER_MASTER
01668   *         @arg @ref LL_HRTIM_TIMER_A
01669   *         @arg @ref LL_HRTIM_TIMER_B
01670   *         @arg @ref LL_HRTIM_TIMER_C
01671   *         @arg @ref LL_HRTIM_TIMER_D
01672   *         @arg @ref LL_HRTIM_TIMER_E
01673   * @retval None
01674   */
01675 __STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
01676 {
01677   SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK));
01678 }
01679
01680 /**
01681   * @brief  Enable the HRTIM timer(s) output(s) .
01682   * @rmtoll OENR         TA1OEN        LL_HRTIM_EnableOutput\n
01683   *         OENR         TA2OEN        LL_HRTIM_EnableOutput\n
01684   *         OENR         TB1OEN        LL_HRTIM_EnableOutput\n
01685   *         OENR         TB2OEN        LL_HRTIM_EnableOutput\n
01686   *         OENR         TC1OEN        LL_HRTIM_EnableOutput\n
01687   *         OENR         TC2OEN        LL_HRTIM_EnableOutput\n
01688   *         OENR         TD1OEN        LL_HRTIM_EnableOutput\n
01689   *         OENR         TD2OEN        LL_HRTIM_EnableOutput\n
01690   *         OENR         TE1OEN        LL_HRTIM_EnableOutput\n
01691   *         OENR         TE2OEN        LL_HRTIM_EnableOutput
01692   * @param  HRTIMx High Resolution Timer instance
01693   * @param  Outputs This parameter can be a combination of the following values:
01694   *         @arg @ref LL_HRTIM_OUTPUT_TA1
01695   *         @arg @ref LL_HRTIM_OUTPUT_TA2
01696   *         @arg @ref LL_HRTIM_OUTPUT_TB1
01697   *         @arg @ref LL_HRTIM_OUTPUT_TB2
01698   *         @arg @ref LL_HRTIM_OUTPUT_TC1
01699   *         @arg @ref LL_HRTIM_OUTPUT_TC2
01700   *         @arg @ref LL_HRTIM_OUTPUT_TD1
01701   *         @arg @ref LL_HRTIM_OUTPUT_TD2
01702   *         @arg @ref LL_HRTIM_OUTPUT_TE1
01703   *         @arg @ref LL_HRTIM_OUTPUT_TE2
01704   * @retval None
01705   */
01706 __STATIC_INLINE void LL_HRTIM_EnableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
01707 {
01708   SET_BIT(HRTIMx->sCommonRegs.OENR, (Outputs & HRTIM_OENR_OEN_MASK));
01709 }
01710
01711 /**
01712   * @brief  Disable the HRTIM timer(s) output(s) .
01713   * @rmtoll OENR         TA1OEN        LL_HRTIM_DisableOutput\n
01714   *         OENR         TA2OEN        LL_HRTIM_DisableOutput\n
01715   *         OENR         TB1OEN        LL_HRTIM_DisableOutput\n
01716   *         OENR         TB2OEN        LL_HRTIM_DisableOutput\n
01717   *         OENR         TC1OEN        LL_HRTIM_DisableOutput\n
01718   *         OENR         TC2OEN        LL_HRTIM_DisableOutput\n
01719   *         OENR         TD1OEN        LL_HRTIM_DisableOutput\n
01720   *         OENR         TD2OEN        LL_HRTIM_DisableOutput\n
01721   *         OENR         TE1OEN        LL_HRTIM_DisableOutput\n
01722   *         OENR         TE2OEN        LL_HRTIM_DisableOutput
01723   * @param  HRTIMx High Resolution Timer instance
01724   * @param  Outputs This parameter can be a combination of the following values:
01725   *         @arg @ref LL_HRTIM_OUTPUT_TA1
01726   *         @arg @ref LL_HRTIM_OUTPUT_TA2
01727   *         @arg @ref LL_HRTIM_OUTPUT_TB1
01728   *         @arg @ref LL_HRTIM_OUTPUT_TB2
01729   *         @arg @ref LL_HRTIM_OUTPUT_TC1
01730   *         @arg @ref LL_HRTIM_OUTPUT_TC2
01731   *         @arg @ref LL_HRTIM_OUTPUT_TD1
01732   *         @arg @ref LL_HRTIM_OUTPUT_TD2
01733   *         @arg @ref LL_HRTIM_OUTPUT_TE1
01734   *         @arg @ref LL_HRTIM_OUTPUT_TE2
01735   * @retval None
01736   */
01737 __STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
01738 {
01739   SET_BIT(HRTIMx->sCommonRegs.ODISR, (Outputs & HRTIM_OENR_ODIS_MASK));
01740 }
01741
01742 /**
01743   * @brief  Indicates whether the HRTIM timer output is enabled.
01744   * @rmtoll OENR         TA1OEN        LL_HRTIM_IsEnabledOutput\n
01745   *         OENR         TA2OEN        LL_HRTIM_IsEnabledOutput\n
01746   *         OENR         TB1OEN        LL_HRTIM_IsEnabledOutput\n
01747   *         OENR         TB2OEN        LL_HRTIM_IsEnabledOutput\n
01748   *         OENR         TC1OEN        LL_HRTIM_IsEnabledOutput\n
01749   *         OENR         TC2OEN        LL_HRTIM_IsEnabledOutput\n
01750   *         OENR         TD1OEN        LL_HRTIM_IsEnabledOutput\n
01751   *         OENR         TD2OEN        LL_HRTIM_IsEnabledOutput\n
01752   *         OENR         TE1OEN        LL_HRTIM_IsEnabledOutput\n
01753   *         OENR         TE2OEN        LL_HRTIM_IsEnabledOutput
01754   * @param  HRTIMx High Resolution Timer instance
01755   * @param  Output This parameter can be one of the following values:
01756   *         @arg @ref LL_HRTIM_OUTPUT_TA1
01757   *         @arg @ref LL_HRTIM_OUTPUT_TA2
01758   *         @arg @ref LL_HRTIM_OUTPUT_TB1
01759   *         @arg @ref LL_HRTIM_OUTPUT_TB2
01760   *         @arg @ref LL_HRTIM_OUTPUT_TC1
01761   *         @arg @ref LL_HRTIM_OUTPUT_TC2
01762   *         @arg @ref LL_HRTIM_OUTPUT_TD1
01763   *         @arg @ref LL_HRTIM_OUTPUT_TD2
01764   *         @arg @ref LL_HRTIM_OUTPUT_TE1
01765   *         @arg @ref LL_HRTIM_OUTPUT_TE2
01766   * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).
01767   */
01768 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
01769 {
01770   return (READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output);
01771 }
01772
01773 /**
01774   * @brief  Indicates whether the HRTIM timer output is disabled.
01775   * @rmtoll ODISR        TA1ODIS        LL_HRTIM_IsDisabledOutput\n
01776   *         ODISR        TA2ODIS        LL_HRTIM_IsDisabledOutput\n
01777   *         ODISR        TB1ODIS        LL_HRTIM_IsDisabledOutput\n
01778   *         ODISR        TB2ODIS        LL_HRTIM_IsDisabledOutput\n
01779   *         ODISR        TC1ODIS        LL_HRTIM_IsDisabledOutput\n
01780   *         ODISR        TC2ODIS        LL_HRTIM_IsDisabledOutput\n
01781   *         ODISR        TD1ODIS        LL_HRTIM_IsDisabledOutput\n
01782   *         ODISR        TD2ODIS        LL_HRTIM_IsDisabledOutput\n
01783   *         ODISR        TE1ODIS        LL_HRTIM_IsDisabledOutput\n
01784   *         ODISR        TE2ODIS        LL_HRTIM_IsDisabledOutput
01785   * @param  HRTIMx High Resolution Timer instance
01786   * @param  Output This parameter can be one of the following values:
01787   *         @arg @ref LL_HRTIM_OUTPUT_TA1
01788   *         @arg @ref LL_HRTIM_OUTPUT_TA2
01789   *         @arg @ref LL_HRTIM_OUTPUT_TB1
01790   *         @arg @ref LL_HRTIM_OUTPUT_TB2
01791   *         @arg @ref LL_HRTIM_OUTPUT_TC1
01792   *         @arg @ref LL_HRTIM_OUTPUT_TC2
01793   *         @arg @ref LL_HRTIM_OUTPUT_TD1
01794   *         @arg @ref LL_HRTIM_OUTPUT_TD2
01795   *         @arg @ref LL_HRTIM_OUTPUT_TE1
01796   *         @arg @ref LL_HRTIM_OUTPUT_TE2
01797   * @retval State of TxyODS bit in HRTIM_ODSR register (1 or 0).
01798   */
01799 __STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
01800 {
01801   return (READ_BIT(HRTIMx->sCommonRegs.ODISR, Output) == Output);
01802 }
01803
01804 /**
01805   * @brief  Configure an ADC trigger.
01806   * @rmtoll CR1          ADC1USRC        LL_HRTIM_ConfigADCTrig\n
01807   *         CR1          ADC2USRC        LL_HRTIM_ConfigADCTrig\n
01808   *         CR1          ADC3USRC        LL_HRTIM_ConfigADCTrig\n
01809   *         CR1          ADC4USRC        LL_HRTIM_ConfigADCTrig\n
01810   *         ADC1R        ADC1MC4         LL_HRTIM_ConfigADCTrig\n
01811   *         ADC1R        ADC1MPER        LL_HRTIM_ConfigADCTrig\n
01812   *         ADC1R        ADC1EEV1        LL_HRTIM_ConfigADCTrig\n
01813   *         ADC1R        ADC1EEV2        LL_HRTIM_ConfigADCTrig\n
01814   *         ADC1R        ADC1EEV3        LL_HRTIM_ConfigADCTrig\n
01815   *         ADC1R        ADC1EEV4        LL_HRTIM_ConfigADCTrig\n
01816   *         ADC1R        ADC1EEV5        LL_HRTIM_ConfigADCTrig\n
01817   *         ADC1R        ADC1TAC2        LL_HRTIM_ConfigADCTrig\n
01818   *         ADC1R        ADC1TAC3        LL_HRTIM_ConfigADCTrig\n
01819   *         ADC1R        ADC1TAC4        LL_HRTIM_ConfigADCTrig\n
01820   *         ADC1R        ADC1TAPER       LL_HRTIM_ConfigADCTrig\n
01821   *         ADC1R        ADC1TARST       LL_HRTIM_ConfigADCTrig\n
01822   *         ADC1R        ADC1TBC2        LL_HRTIM_ConfigADCTrig\n
01823   *         ADC1R        ADC1TBC3        LL_HRTIM_ConfigADCTrig\n
01824   *         ADC1R        ADC1TBC4        LL_HRTIM_ConfigADCTrig\n
01825   *         ADC1R        ADC1TBPER       LL_HRTIM_ConfigADCTrig\n
01826   *         ADC1R        ADC1TBRST       LL_HRTIM_ConfigADCTrig\n
01827   *         ADC1R        ADC1TCC2        LL_HRTIM_ConfigADCTrig\n
01828   *         ADC1R        ADC1TCC3        LL_HRTIM_ConfigADCTrig\n
01829   *         ADC1R        ADC1TCC4        LL_HRTIM_ConfigADCTrig\n
01830   *         ADC1R        ADC1TCPER       LL_HRTIM_ConfigADCTrig\n
01831   *         ADC1R        ADC1TDC2        LL_HRTIM_ConfigADCTrig\n
01832   *         ADC1R        ADC1TDC3        LL_HRTIM_ConfigADCTrig\n
01833   *         ADC1R        ADC1TDC4        LL_HRTIM_ConfigADCTrig\n
01834   *         ADC1R        ADC1TDPER       LL_HRTIM_ConfigADCTrig\n
01835   *         ADC1R        ADC1TEC2        LL_HRTIM_ConfigADCTrig\n
01836   *         ADC1R        ADC1TEC3        LL_HRTIM_ConfigADCTrig\n
01837   *         ADC1R        ADC1TEC4        LL_HRTIM_ConfigADCTrig\n
01838   *         ADC1R        ADC1TEPER       LL_HRTIM_ConfigADCTrig\n
01839   *         ADC2R        ADC2MC1         LL_HRTIM_ConfigADCTrig\n
01840   *         ADC2R        ADC2MC2         LL_HRTIM_ConfigADCTrig\n
01841   *         ADC2R        ADC2MC3         LL_HRTIM_ConfigADCTrig\n
01842   *         ADC2R        ADC2MC4         LL_HRTIM_ConfigADCTrig\n
01843   *         ADC2R        ADC2MPER        LL_HRTIM_ConfigADCTrig\n
01844   *         ADC2R        ADC2EEV6        LL_HRTIM_ConfigADCTrig\n
01845   *         ADC2R        ADC2EEV7        LL_HRTIM_ConfigADCTrig\n
01846   *         ADC2R        ADC2EEV8        LL_HRTIM_ConfigADCTrig\n
01847   *         ADC2R        ADC2EEV9        LL_HRTIM_ConfigADCTrig\n
01848   *         ADC2R        ADC2EEV10       LL_HRTIM_ConfigADCTrig\n
01849   *         ADC2R        ADC2TAC2        LL_HRTIM_ConfigADCTrig\n
01850   *         ADC2R        ADC2TAC3        LL_HRTIM_ConfigADCTrig\n
01851   *         ADC2R        ADC2TAC4        LL_HRTIM_ConfigADCTrig\n
01852   *         ADC2R        ADC2TAPER       LL_HRTIM_ConfigADCTrig\n
01853   *         ADC2R        ADC2TBC2        LL_HRTIM_ConfigADCTrig\n
01854   *         ADC2R        ADC2TBC3        LL_HRTIM_ConfigADCTrig\n
01855   *         ADC2R        ADC2TBC4        LL_HRTIM_ConfigADCTrig\n
01856   *         ADC2R        ADC2TBPER       LL_HRTIM_ConfigADCTrig\n
01857   *         ADC2R        ADC2TCC2        LL_HRTIM_ConfigADCTrig\n
01858   *         ADC2R        ADC2TCC3        LL_HRTIM_ConfigADCTrig\n
01859   *         ADC2R        ADC2TCC4        LL_HRTIM_ConfigADCTrig\n
01860   *         ADC2R        ADC2TCPER       LL_HRTIM_ConfigADCTrig\n
01861   *         ADC2R        ADC2TCRST       LL_HRTIM_ConfigADCTrig\n
01862   *         ADC2R        ADC2TDC2        LL_HRTIM_ConfigADCTrig\n
01863   *         ADC2R        ADC2TDC3        LL_HRTIM_ConfigADCTrig\n
01864   *         ADC2R        ADC2TDC4        LL_HRTIM_ConfigADCTrig\n
01865   *         ADC2R        ADC2TDPER       LL_HRTIM_ConfigADCTrig\n
01866   *         ADC2R        ADC2TDRST       LL_HRTIM_ConfigADCTrig\n
01867   *         ADC2R        ADC2TEC2        LL_HRTIM_ConfigADCTrig\n
01868   *         ADC2R        ADC2TEC3        LL_HRTIM_ConfigADCTrig\n
01869   *         ADC2R        ADC2TEC4        LL_HRTIM_ConfigADCTrig\n
01870   *         ADC2R        ADC2TERST       LL_HRTIM_ConfigADCTrig\n
01871   *         ADC3R        ADC3MC1         LL_HRTIM_ConfigADCTrig\n
01872   *         ADC3R        ADC3MC2         LL_HRTIM_ConfigADCTrig\n
01873   *         ADC3R        ADC3MC3         LL_HRTIM_ConfigADCTrig\n
01874   *         ADC3R        ADC3MC4         LL_HRTIM_ConfigADCTrig\n
01875   *         ADC3R        ADC3MPER        LL_HRTIM_ConfigADCTrig\n
01876   *         ADC3R        ADC3EEV1        LL_HRTIM_ConfigADCTrig\n
01877   *         ADC3R        ADC3EEV2        LL_HRTIM_ConfigADCTrig\n
01878   *         ADC3R        ADC3EEV3        LL_HRTIM_ConfigADCTrig\n
01879   *         ADC3R        ADC3EEV4        LL_HRTIM_ConfigADCTrig\n
01880   *         ADC3R        ADC3EEV5        LL_HRTIM_ConfigADCTrig\n
01881   *         ADC3R        ADC3TAC2        LL_HRTIM_ConfigADCTrig\n
01882   *         ADC3R        ADC3TAC3        LL_HRTIM_ConfigADCTrig\n
01883   *         ADC3R        ADC3TAC4        LL_HRTIM_ConfigADCTrig\n
01884   *         ADC3R        ADC3TAPER       LL_HRTIM_ConfigADCTrig\n
01885   *         ADC3R        ADC3TARST       LL_HRTIM_ConfigADCTrig\n
01886   *         ADC3R        ADC3TBC2        LL_HRTIM_ConfigADCTrig\n
01887   *         ADC3R        ADC3TBC3        LL_HRTIM_ConfigADCTrig\n
01888   *         ADC3R        ADC3TBC4        LL_HRTIM_ConfigADCTrig\n
01889   *         ADC3R        ADC3TBPER       LL_HRTIM_ConfigADCTrig\n
01890   *         ADC3R        ADC3TBRST       LL_HRTIM_ConfigADCTrig\n
01891   *         ADC3R        ADC3TCC2        LL_HRTIM_ConfigADCTrig\n
01892   *         ADC3R        ADC3TCC3        LL_HRTIM_ConfigADCTrig\n
01893   *         ADC3R        ADC3TCC4        LL_HRTIM_ConfigADCTrig\n
01894   *         ADC3R        ADC3TCPER       LL_HRTIM_ConfigADCTrig\n
01895   *         ADC3R        ADC3TDC2        LL_HRTIM_ConfigADCTrig\n
01896   *         ADC3R        ADC3TDC3        LL_HRTIM_ConfigADCTrig\n
01897   *         ADC3R        ADC3TDC4        LL_HRTIM_ConfigADCTrig\n
01898   *         ADC3R        ADC3TDPER       LL_HRTIM_ConfigADCTrig\n
01899   *         ADC3R        ADC3TEC2        LL_HRTIM_ConfigADCTrig\n
01900   *         ADC3R        ADC3TEC3        LL_HRTIM_ConfigADCTrig\n
01901   *         ADC3R        ADC3TEC4        LL_HRTIM_ConfigADCTrig\n
01902   *         ADC3R        ADC3TEPER       LL_HRTIM_ConfigADCTrig\n
01903   *         ADC4R        ADC4MC1         LL_HRTIM_ConfigADCTrig\n
01904   *         ADC4R        ADC4MC2         LL_HRTIM_ConfigADCTrig\n
01905   *         ADC4R        ADC4MC3         LL_HRTIM_ConfigADCTrig\n
01906   *         ADC4R        ADC4MC4         LL_HRTIM_ConfigADCTrig\n
01907   *         ADC4R        ADC4MPER        LL_HRTIM_ConfigADCTrig\n
01908   *         ADC4R        ADC4EEV6        LL_HRTIM_ConfigADCTrig\n
01909   *         ADC4R        ADC4EEV7        LL_HRTIM_ConfigADCTrig\n
01910   *         ADC4R        ADC4EEV8        LL_HRTIM_ConfigADCTrig\n
01911   *         ADC4R        ADC4EEV9        LL_HRTIM_ConfigADCTrig\n
01912   *         ADC4R        ADC4EEV10       LL_HRTIM_ConfigADCTrig\n
01913   *         ADC4R        ADC4TAC2        LL_HRTIM_ConfigADCTrig\n
01914   *         ADC4R        ADC4TAC3        LL_HRTIM_ConfigADCTrig\n
01915   *         ADC4R        ADC4TAC4        LL_HRTIM_ConfigADCTrig\n
01916   *         ADC4R        ADC4TAPER       LL_HRTIM_ConfigADCTrig\n
01917   *         ADC4R        ADC4TBC2        LL_HRTIM_ConfigADCTrig\n
01918   *         ADC4R        ADC4TBC3        LL_HRTIM_ConfigADCTrig\n
01919   *         ADC4R        ADC4TBC4        LL_HRTIM_ConfigADCTrig\n
01920   *         ADC4R        ADC4TBPER       LL_HRTIM_ConfigADCTrig\n
01921   *         ADC4R        ADC4TCC2        LL_HRTIM_ConfigADCTrig\n
01922   *         ADC4R        ADC4TCC3        LL_HRTIM_ConfigADCTrig\n
01923   *         ADC4R        ADC4TCC4        LL_HRTIM_ConfigADCTrig\n
01924   *         ADC4R        ADC4TCPER       LL_HRTIM_ConfigADCTrig\n
01925   *         ADC4R        ADC4TCRST       LL_HRTIM_ConfigADCTrig\n
01926   *         ADC4R        ADC4TDC2        LL_HRTIM_ConfigADCTrig\n
01927   *         ADC4R        ADC4TDC3        LL_HRTIM_ConfigADCTrig\n
01928   *         ADC4R        ADC4TDC4        LL_HRTIM_ConfigADCTrig\n
01929   *         ADC4R        ADC4TDPER       LL_HRTIM_ConfigADCTrig\n
01930   *         ADC4R        ADC4TDRST       LL_HRTIM_ConfigADCTrig\n
01931   *         ADC4R        ADC4TEC2        LL_HRTIM_ConfigADCTrig\n
01932   *         ADC4R        ADC4TEC3        LL_HRTIM_ConfigADCTrig\n
01933   *         ADC4R        ADC4TEC4        LL_HRTIM_ConfigADCTrig\n
01934   *         ADC4R        ADC4TERST       LL_HRTIM_ConfigADCTrig
01935   * @param  HRTIMx High Resolution Timer instance
01936   * @param  ADCTrig This parameter can be one of the following values:
01937   *         @arg @ref LL_HRTIM_ADCTRIG_1
01938   *         @arg @ref LL_HRTIM_ADCTRIG_2
01939   *         @arg @ref LL_HRTIM_ADCTRIG_3
01940   *         @arg @ref LL_HRTIM_ADCTRIG_4
01941   * @param  Update This parameter can be one of the following values:
01942   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
01943   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
01944   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
01945   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
01946   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
01947   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
01948   * @param  Src This parameter can be a combination of the following values:
01949   *
01950   *         For ADC trigger 1 and ADC trigger 3:
01951   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
01952   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
01953   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
01954   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
01955   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
01956   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
01957   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
01958   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
01959   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
01960   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
01961   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
01962   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
01963   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
01964   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
01965   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
01966   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
01967   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
01968   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
01969   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
01970   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
01971   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
01972   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
01973   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
01974   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
01975   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
01976   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
01977   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
01978   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
01979   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
01980   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
01981   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
01982   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
01983   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
01984   *
01985   *         For ADC trigger 2 and ADC trigger 4:
01986   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
01987   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
01988   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
01989   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
01990   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
01991   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
01992   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
01993   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
01994   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
01995   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
01996   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
01997   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
01998   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
01999   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
02000   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
02001   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
02002   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
02003   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
02004   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
02005   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
02006   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
02007   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
02008   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
02009   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
02010   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
02011   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
02012   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
02013   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
02014   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
02015   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
02016   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
02017   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
02018   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
02019   * @retval None
02020   */
02021 __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)
02022 {
02023   register uint32_t shift = 3 * ADCTrig;
02024   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
02025                                                     REG_OFFSET_TAB_ADCxR[ADCTrig]));
02026   MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));
02027   WRITE_REG(*pReg, Src);
02028 }
02029
02030 /**
02031   * @brief  Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register.
02032   * @rmtoll CR1          ADC1USRC         LL_HRTIM_SetADCTrigUpdate\n
02033   *         CR1          ADC2USRC         LL_HRTIM_SetADCTrigUpdate\n
02034   *         CR1          ADC3USRC         LL_HRTIM_SetADCTrigUpdate\n
02035   *         CR1          ADC4USRC         LL_HRTIM_SetADCTrigUpdate
02036   * @note When the preload is disabled in the source timer, the HRTIM_ADCxR
02037   *       registers are not preloaded either: a write access will result in an
02038   *       immediate update of the trigger source.
02039   * @param  HRTIMx High Resolution Timer instance
02040   * @param  ADCTrig This parameter can be one of the following values:
02041   *         @arg @ref LL_HRTIM_ADCTRIG_1
02042   *         @arg @ref LL_HRTIM_ADCTRIG_2
02043   *         @arg @ref LL_HRTIM_ADCTRIG_3
02044   *         @arg @ref LL_HRTIM_ADCTRIG_4
02045   * @param  Update This parameter can be one of the following values:
02046   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
02047   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
02048   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
02049   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
02050   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
02051   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
02052   * @retval None
02053   */
02054 __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)
02055 {
02056   register uint32_t shift = 3 * ADCTrig;
02057   MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));
02058 }
02059
02060 /**
02061   * @brief  Get the source timer triggering the update of the HRTIM_ADCxR register.
02062   * @rmtoll CR1          ADC1USRC        LL_HRTIM_GetADCTrigUpdate\n
02063   *         CR1          ADC2USRC        LL_HRTIM_GetADCTrigUpdate\n
02064   *         CR1          ADC3USRC        LL_HRTIM_GetADCTrigUpdate\n
02065   *         CR1          ADC4USRC        LL_HRTIM_GetADCTrigUpdate
02066   * @param  HRTIMx High Resolution Timer instance
02067   * @param  ADCTrig This parameter can be one of the following values:
02068   *         @arg @ref LL_HRTIM_ADCTRIG_1
02069   *         @arg @ref LL_HRTIM_ADCTRIG_2
02070   *         @arg @ref LL_HRTIM_ADCTRIG_3
02071   *         @arg @ref LL_HRTIM_ADCTRIG_4
02072   * @retval Update Returned value can be one of the following values:
02073   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
02074   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
02075   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
02076   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
02077   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
02078   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
02079   */
02080 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
02081 {
02082   register uint32_t shift = 3 * ADCTrig;
02083   return (READ_BIT(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift)) >> shift);
02084 }
02085
02086 /**
02087   * @brief  Specify which events (timer events and/or external events) are used as triggers for ADC conversion.
02088   * @rmtoll ADC1R        ADC1MC4         LL_HRTIM_SetADCTrigSrc\n
02089   *         ADC1R        ADC1MPER        LL_HRTIM_SetADCTrigSrc\n
02090   *         ADC1R        ADC1EEV1        LL_HRTIM_SetADCTrigSrc\n
02091   *         ADC1R        ADC1EEV2        LL_HRTIM_SetADCTrigSrc\n
02092   *         ADC1R        ADC1EEV3        LL_HRTIM_SetADCTrigSrc\n
02093   *         ADC1R        ADC1EEV4        LL_HRTIM_SetADCTrigSrc\n
02094   *         ADC1R        ADC1EEV5        LL_HRTIM_SetADCTrigSrc\n
02095   *         ADC1R        ADC1TAC2        LL_HRTIM_SetADCTrigSrc\n
02096   *         ADC1R        ADC1TAC3        LL_HRTIM_SetADCTrigSrc\n
02097   *         ADC1R        ADC1TAC4        LL_HRTIM_SetADCTrigSrc\n
02098   *         ADC1R        ADC1TAPER       LL_HRTIM_SetADCTrigSrc\n
02099   *         ADC1R        ADC1TARST       LL_HRTIM_SetADCTrigSrc\n
02100   *         ADC1R        ADC1TBC2        LL_HRTIM_SetADCTrigSrc\n
02101   *         ADC1R        ADC1TBC3        LL_HRTIM_SetADCTrigSrc\n
02102   *         ADC1R        ADC1TBC4        LL_HRTIM_SetADCTrigSrc\n
02103   *         ADC1R        ADC1TBPER       LL_HRTIM_SetADCTrigSrc\n
02104   *         ADC1R        ADC1TBRST       LL_HRTIM_SetADCTrigSrc\n
02105   *         ADC1R        ADC1TCC2        LL_HRTIM_SetADCTrigSrc\n
02106   *         ADC1R        ADC1TCC3        LL_HRTIM_SetADCTrigSrc\n
02107   *         ADC1R        ADC1TCC4        LL_HRTIM_SetADCTrigSrc\n
02108   *         ADC1R        ADC1TCPER       LL_HRTIM_SetADCTrigSrc\n
02109   *         ADC1R        ADC1TDC2        LL_HRTIM_SetADCTrigSrc\n
02110   *         ADC1R        ADC1TDC3        LL_HRTIM_SetADCTrigSrc\n
02111   *         ADC1R        ADC1TDC4        LL_HRTIM_SetADCTrigSrc\n
02112   *         ADC1R        ADC1TDPER       LL_HRTIM_SetADCTrigSrc\n
02113   *         ADC1R        ADC1TEC2        LL_HRTIM_SetADCTrigSrc\n
02114   *         ADC1R        ADC1TEC3        LL_HRTIM_SetADCTrigSrc\n
02115   *         ADC1R        ADC1TEC4        LL_HRTIM_SetADCTrigSrc\n
02116   *         ADC1R        ADC1TEPER       LL_HRTIM_SetADCTrigSrc\n
02117   *         ADC2R        ADC2MC1         LL_HRTIM_SetADCTrigSrc\n
02118   *         ADC2R        ADC2MC2         LL_HRTIM_SetADCTrigSrc\n
02119   *         ADC2R        ADC2MC3         LL_HRTIM_SetADCTrigSrc\n
02120   *         ADC2R        ADC2MC4         LL_HRTIM_SetADCTrigSrc\n
02121   *         ADC2R        ADC2MPER        LL_HRTIM_SetADCTrigSrc\n
02122   *         ADC2R        ADC2EEV6        LL_HRTIM_SetADCTrigSrc\n
02123   *         ADC2R        ADC2EEV7        LL_HRTIM_SetADCTrigSrc\n
02124   *         ADC2R        ADC2EEV8        LL_HRTIM_SetADCTrigSrc\n
02125   *         ADC2R        ADC2EEV9        LL_HRTIM_SetADCTrigSrc\n
02126   *         ADC2R        ADC2EEV10       LL_HRTIM_SetADCTrigSrc\n
02127   *         ADC2R        ADC2TAC2        LL_HRTIM_SetADCTrigSrc\n
02128   *         ADC2R        ADC2TAC3        LL_HRTIM_SetADCTrigSrc\n
02129   *         ADC2R        ADC2TAC4        LL_HRTIM_SetADCTrigSrc\n
02130   *         ADC2R        ADC2TAPER       LL_HRTIM_SetADCTrigSrc\n
02131   *         ADC2R        ADC2TBC2        LL_HRTIM_SetADCTrigSrc\n
02132   *         ADC2R        ADC2TBC3        LL_HRTIM_SetADCTrigSrc\n
02133   *         ADC2R        ADC2TBC4        LL_HRTIM_SetADCTrigSrc\n
02134   *         ADC2R        ADC2TBPER       LL_HRTIM_SetADCTrigSrc\n
02135   *         ADC2R        ADC2TCC2        LL_HRTIM_SetADCTrigSrc\n
02136   *         ADC2R        ADC2TCC3        LL_HRTIM_SetADCTrigSrc\n
02137   *         ADC2R        ADC2TCC4        LL_HRTIM_SetADCTrigSrc\n
02138   *         ADC2R        ADC2TCPER       LL_HRTIM_SetADCTrigSrc\n
02139   *         ADC2R        ADC2TCRST       LL_HRTIM_SetADCTrigSrc\n
02140   *         ADC2R        ADC2TDC2        LL_HRTIM_SetADCTrigSrc\n
02141   *         ADC2R        ADC2TDC3        LL_HRTIM_SetADCTrigSrc\n
02142   *         ADC2R        ADC2TDC4        LL_HRTIM_SetADCTrigSrc\n
02143   *         ADC2R        ADC2TDPER       LL_HRTIM_SetADCTrigSrc\n
02144   *         ADC2R        ADC2TDRST       LL_HRTIM_SetADCTrigSrc\n
02145   *         ADC2R        ADC2TEC2        LL_HRTIM_SetADCTrigSrc\n
02146   *         ADC2R        ADC2TEC3        LL_HRTIM_SetADCTrigSrc\n
02147   *         ADC2R        ADC2TEC4        LL_HRTIM_SetADCTrigSrc\n
02148   *         ADC2R        ADC2TERST       LL_HRTIM_SetADCTrigSrc\n
02149   *         ADC3R        ADC3MC1         LL_HRTIM_SetADCTrigSrc\n
02150   *         ADC3R        ADC3MC2         LL_HRTIM_SetADCTrigSrc\n
02151   *         ADC3R        ADC3MC3         LL_HRTIM_SetADCTrigSrc\n
02152   *         ADC3R        ADC3MC4         LL_HRTIM_SetADCTrigSrc\n
02153   *         ADC3R        ADC3MPER        LL_HRTIM_SetADCTrigSrc\n
02154   *         ADC3R        ADC3EEV1        LL_HRTIM_SetADCTrigSrc\n
02155   *         ADC3R        ADC3EEV2        LL_HRTIM_SetADCTrigSrc\n
02156   *         ADC3R        ADC3EEV3        LL_HRTIM_SetADCTrigSrc\n
02157   *         ADC3R        ADC3EEV4        LL_HRTIM_SetADCTrigSrc\n
02158   *         ADC3R        ADC3EEV5        LL_HRTIM_SetADCTrigSrc\n
02159   *         ADC3R        ADC3TAC2        LL_HRTIM_SetADCTrigSrc\n
02160   *         ADC3R        ADC3TAC3        LL_HRTIM_SetADCTrigSrc\n
02161   *         ADC3R        ADC3TAC4        LL_HRTIM_SetADCTrigSrc\n
02162   *         ADC3R        ADC3TAPER       LL_HRTIM_SetADCTrigSrc\n
02163   *         ADC3R        ADC3TARST       LL_HRTIM_SetADCTrigSrc\n
02164   *         ADC3R        ADC3TBC2        LL_HRTIM_SetADCTrigSrc\n
02165   *         ADC3R        ADC3TBC3        LL_HRTIM_SetADCTrigSrc\n
02166   *         ADC3R        ADC3TBC4        LL_HRTIM_SetADCTrigSrc\n
02167   *         ADC3R        ADC3TBPER       LL_HRTIM_SetADCTrigSrc\n
02168   *         ADC3R        ADC3TBRST       LL_HRTIM_SetADCTrigSrc\n
02169   *         ADC3R        ADC3TCC2        LL_HRTIM_SetADCTrigSrc\n
02170   *         ADC3R        ADC3TCC3        LL_HRTIM_SetADCTrigSrc\n
02171   *         ADC3R        ADC3TCC4        LL_HRTIM_SetADCTrigSrc\n
02172   *         ADC3R        ADC3TCPER       LL_HRTIM_SetADCTrigSrc\n
02173   *         ADC3R        ADC3TDC2        LL_HRTIM_SetADCTrigSrc\n
02174   *         ADC3R        ADC3TDC3        LL_HRTIM_SetADCTrigSrc\n
02175   *         ADC3R        ADC3TDC4        LL_HRTIM_SetADCTrigSrc\n
02176   *         ADC3R        ADC3TDPER       LL_HRTIM_SetADCTrigSrc\n
02177   *         ADC3R        ADC3TEC2        LL_HRTIM_SetADCTrigSrc\n
02178   *         ADC3R        ADC3TEC3        LL_HRTIM_SetADCTrigSrc\n
02179   *         ADC3R        ADC3TEC4        LL_HRTIM_SetADCTrigSrc\n
02180   *         ADC3R        ADC3TEPER       LL_HRTIM_SetADCTrigSrc\n
02181   *         ADC4R        ADC4MC1         LL_HRTIM_SetADCTrigSrc\n
02182   *         ADC4R        ADC4MC2         LL_HRTIM_SetADCTrigSrc\n
02183   *         ADC4R        ADC4MC3         LL_HRTIM_SetADCTrigSrc\n
02184   *         ADC4R        ADC4MC4         LL_HRTIM_SetADCTrigSrc\n
02185   *         ADC4R        ADC4MPER        LL_HRTIM_SetADCTrigSrc\n
02186   *         ADC4R        ADC4EEV6        LL_HRTIM_SetADCTrigSrc\n
02187   *         ADC4R        ADC4EEV7        LL_HRTIM_SetADCTrigSrc\n
02188   *         ADC4R        ADC4EEV8        LL_HRTIM_SetADCTrigSrc\n
02189   *         ADC4R        ADC4EEV9        LL_HRTIM_SetADCTrigSrc\n
02190   *         ADC4R        ADC4EEV10       LL_HRTIM_SetADCTrigSrc\n
02191   *         ADC4R        ADC4TAC2        LL_HRTIM_SetADCTrigSrc\n
02192   *         ADC4R        ADC4TAC3        LL_HRTIM_SetADCTrigSrc\n
02193   *         ADC4R        ADC4TAC4        LL_HRTIM_SetADCTrigSrc\n
02194   *         ADC4R        ADC4TAPER       LL_HRTIM_SetADCTrigSrc\n
02195   *         ADC4R        ADC4TBC2        LL_HRTIM_SetADCTrigSrc\n
02196   *         ADC4R        ADC4TBC3        LL_HRTIM_SetADCTrigSrc\n
02197   *         ADC4R        ADC4TBC4        LL_HRTIM_SetADCTrigSrc\n
02198   *         ADC4R        ADC4TBPER       LL_HRTIM_SetADCTrigSrc\n
02199   *         ADC4R        ADC4TCC2        LL_HRTIM_SetADCTrigSrc\n
02200   *         ADC4R        ADC4TCC3        LL_HRTIM_SetADCTrigSrc\n
02201   *         ADC4R        ADC4TCC4        LL_HRTIM_SetADCTrigSrc\n
02202   *         ADC4R        ADC4TCPER       LL_HRTIM_SetADCTrigSrc\n
02203   *         ADC4R        ADC4TCRST       LL_HRTIM_SetADCTrigSrc\n
02204   *         ADC4R        ADC4TDC2        LL_HRTIM_SetADCTrigSrc\n
02205   *         ADC4R        ADC4TDC3        LL_HRTIM_SetADCTrigSrc\n
02206   *         ADC4R        ADC4TDC4        LL_HRTIM_SetADCTrigSrc\n
02207   *         ADC4R        ADC4TDPER       LL_HRTIM_SetADCTrigSrc\n
02208   *         ADC4R        ADC4TDRST       LL_HRTIM_SetADCTrigSrc\n
02209   *         ADC4R        ADC4TEC2        LL_HRTIM_SetADCTrigSrc\n
02210   *         ADC4R        ADC4TEC3        LL_HRTIM_SetADCTrigSrc\n
02211   *         ADC4R        ADC4TEC4        LL_HRTIM_SetADCTrigSrc\n
02212   *         ADC4R        ADC4TERST       LL_HRTIM_SetADCTrigSrc
02213   * @param  HRTIMx High Resolution Timer instance
02214   * @param  ADCTrig This parameter can be one of the following values:
02215   *         @arg @ref LL_HRTIM_ADCTRIG_1
02216   *         @arg @ref LL_HRTIM_ADCTRIG_2
02217   *         @arg @ref LL_HRTIM_ADCTRIG_3
02218   *         @arg @ref LL_HRTIM_ADCTRIG_4
02219   * @param  Src This parameter can be a combination of the following values:
02220   *
02221   *         For ADC trigger 1 and ADC trigger 3:
02222   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
02223   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
02224   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
02225   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
02226   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
02227   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
02228   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
02229   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
02230   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
02231   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
02232   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
02233   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
02234   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
02235   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
02236   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
02237   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
02238   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
02239   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
02240   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
02241   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
02242   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
02243   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
02244   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
02245   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
02246   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
02247   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
02248   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
02249   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
02250   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
02251   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
02252   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
02253   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
02254   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
02255   *
02256   *         For ADC trigger 2 and ADC trigger 4:
02257   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
02258   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
02259   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
02260   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
02261   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
02262   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
02263   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
02264   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
02265   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
02266   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
02267   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
02268   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
02269   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
02270   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
02271   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
02272   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
02273   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
02274   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
02275   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
02276   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
02277   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
02278   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
02279   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
02280   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
02281   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
02282   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
02283   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
02284   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
02285   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
02286   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
02287   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
02288   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
02289   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
02290 * @retval None
02291   */
02292 __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src)
02293 {
02294   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
02295                                                     REG_OFFSET_TAB_ADCxR[ADCTrig]));
02296   WRITE_REG(*pReg, Src);
02297 }
02298
02299 /**
02300   * @brief  Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion.
02301   * @rmtoll ADC1R        ADC1MC4         LL_HRTIM_GetADCTrigSrc\n
02302   *         ADC1R        ADC1MPER        LL_HRTIM_GetADCTrigSrc\n
02303   *         ADC1R        ADC1EEV1        LL_HRTIM_GetADCTrigSrc\n
02304   *         ADC1R        ADC1EEV2        LL_HRTIM_GetADCTrigSrc\n
02305   *         ADC1R        ADC1EEV3        LL_HRTIM_GetADCTrigSrc\n
02306   *         ADC1R        ADC1EEV4        LL_HRTIM_GetADCTrigSrc\n
02307   *         ADC1R        ADC1EEV5        LL_HRTIM_GetADCTrigSrc\n
02308   *         ADC1R        ADC1TAC2        LL_HRTIM_GetADCTrigSrc\n
02309   *         ADC1R        ADC1TAC3        LL_HRTIM_GetADCTrigSrc\n
02310   *         ADC1R        ADC1TAC4        LL_HRTIM_GetADCTrigSrc\n
02311   *         ADC1R        ADC1TAPER       LL_HRTIM_GetADCTrigSrc\n
02312   *         ADC1R        ADC1TARST       LL_HRTIM_GetADCTrigSrc\n
02313   *         ADC1R        ADC1TBC2        LL_HRTIM_GetADCTrigSrc\n
02314   *         ADC1R        ADC1TBC3        LL_HRTIM_GetADCTrigSrc\n
02315   *         ADC1R        ADC1TBC4        LL_HRTIM_GetADCTrigSrc\n
02316   *         ADC1R        ADC1TBPER       LL_HRTIM_GetADCTrigSrc\n
02317   *         ADC1R        ADC1TBRST       LL_HRTIM_GetADCTrigSrc\n
02318   *         ADC1R        ADC1TCC2        LL_HRTIM_GetADCTrigSrc\n
02319   *         ADC1R        ADC1TCC3        LL_HRTIM_GetADCTrigSrc\n
02320   *         ADC1R        ADC1TCC4        LL_HRTIM_GetADCTrigSrc\n
02321   *         ADC1R        ADC1TCPER       LL_HRTIM_GetADCTrigSrc\n
02322   *         ADC1R        ADC1TDC2        LL_HRTIM_GetADCTrigSrc\n
02323   *         ADC1R        ADC1TDC3        LL_HRTIM_GetADCTrigSrc\n
02324   *         ADC1R        ADC1TDC4        LL_HRTIM_GetADCTrigSrc\n
02325   *         ADC1R        ADC1TDPER       LL_HRTIM_GetADCTrigSrc\n
02326   *         ADC1R        ADC1TEC2        LL_HRTIM_GetADCTrigSrc\n
02327   *         ADC1R        ADC1TEC3        LL_HRTIM_GetADCTrigSrc\n
02328   *         ADC1R        ADC1TEC4        LL_HRTIM_GetADCTrigSrc\n
02329   *         ADC1R        ADC1TEPER       LL_HRTIM_GetADCTrigSrc\n
02330   *         ADC2R        ADC2MC1         LL_HRTIM_GetADCTrigSrc\n
02331   *         ADC2R        ADC2MC2         LL_HRTIM_GetADCTrigSrc\n
02332   *         ADC2R        ADC2MC3         LL_HRTIM_GetADCTrigSrc\n
02333   *         ADC2R        ADC2MC4         LL_HRTIM_GetADCTrigSrc\n
02334   *         ADC2R        ADC2MPER        LL_HRTIM_GetADCTrigSrc\n
02335   *         ADC2R        ADC2EEV6        LL_HRTIM_GetADCTrigSrc\n
02336   *         ADC2R        ADC2EEV7        LL_HRTIM_GetADCTrigSrc\n
02337   *         ADC2R        ADC2EEV8        LL_HRTIM_GetADCTrigSrc\n
02338   *         ADC2R        ADC2EEV9        LL_HRTIM_GetADCTrigSrc\n
02339   *         ADC2R        ADC2EEV10       LL_HRTIM_GetADCTrigSrc\n
02340   *         ADC2R        ADC2TAC2        LL_HRTIM_GetADCTrigSrc\n
02341   *         ADC2R        ADC2TAC3        LL_HRTIM_GetADCTrigSrc\n
02342   *         ADC2R        ADC2TAC4        LL_HRTIM_GetADCTrigSrc\n
02343   *         ADC2R        ADC2TAPER       LL_HRTIM_GetADCTrigSrc\n
02344   *         ADC2R        ADC2TBC2        LL_HRTIM_GetADCTrigSrc\n
02345   *         ADC2R        ADC2TBC3        LL_HRTIM_GetADCTrigSrc\n
02346   *         ADC2R        ADC2TBC4        LL_HRTIM_GetADCTrigSrc\n
02347   *         ADC2R        ADC2TBPER       LL_HRTIM_GetADCTrigSrc\n
02348   *         ADC2R        ADC2TCC2        LL_HRTIM_GetADCTrigSrc\n
02349   *         ADC2R        ADC2TCC3        LL_HRTIM_GetADCTrigSrc\n
02350   *         ADC2R        ADC2TCC4        LL_HRTIM_GetADCTrigSrc\n
02351   *         ADC2R        ADC2TCPER       LL_HRTIM_GetADCTrigSrc\n
02352   *         ADC2R        ADC2TCRST       LL_HRTIM_GetADCTrigSrc\n
02353   *         ADC2R        ADC2TDC2        LL_HRTIM_GetADCTrigSrc\n
02354   *         ADC2R        ADC2TDC3        LL_HRTIM_GetADCTrigSrc\n
02355   *         ADC2R        ADC2TDC4        LL_HRTIM_GetADCTrigSrc\n
02356   *         ADC2R        ADC2TDPER       LL_HRTIM_GetADCTrigSrc\n
02357   *         ADC2R        ADC2TDRST       LL_HRTIM_GetADCTrigSrc\n
02358   *         ADC2R        ADC2TEC2        LL_HRTIM_GetADCTrigSrc\n
02359   *         ADC2R        ADC2TEC3        LL_HRTIM_GetADCTrigSrc\n
02360   *         ADC2R        ADC2TEC4        LL_HRTIM_GetADCTrigSrc\n
02361   *         ADC2R        ADC2TERST       LL_HRTIM_GetADCTrigSrc\n
02362   *         ADC3R        ADC3MC1         LL_HRTIM_GetADCTrigSrc\n
02363   *         ADC3R        ADC3MC2         LL_HRTIM_GetADCTrigSrc\n
02364   *         ADC3R        ADC3MC3         LL_HRTIM_GetADCTrigSrc\n
02365   *         ADC3R        ADC3MC4         LL_HRTIM_GetADCTrigSrc\n
02366   *         ADC3R        ADC3MPER        LL_HRTIM_GetADCTrigSrc\n
02367   *         ADC3R        ADC3EEV1        LL_HRTIM_GetADCTrigSrc\n
02368   *         ADC3R        ADC3EEV2        LL_HRTIM_GetADCTrigSrc\n
02369   *         ADC3R        ADC3EEV3        LL_HRTIM_GetADCTrigSrc\n
02370   *         ADC3R        ADC3EEV4        LL_HRTIM_GetADCTrigSrc\n
02371   *         ADC3R        ADC3EEV5        LL_HRTIM_GetADCTrigSrc\n
02372   *         ADC3R        ADC3TAC2        LL_HRTIM_GetADCTrigSrc\n
02373   *         ADC3R        ADC3TAC3        LL_HRTIM_GetADCTrigSrc\n
02374   *         ADC3R        ADC3TAC4        LL_HRTIM_GetADCTrigSrc\n
02375   *         ADC3R        ADC3TAPER       LL_HRTIM_GetADCTrigSrc\n
02376   *         ADC3R        ADC3TARST       LL_HRTIM_GetADCTrigSrc\n
02377   *         ADC3R        ADC3TBC2        LL_HRTIM_GetADCTrigSrc\n
02378   *         ADC3R        ADC3TBC3        LL_HRTIM_GetADCTrigSrc\n
02379   *         ADC3R        ADC3TBC4        LL_HRTIM_GetADCTrigSrc\n
02380   *         ADC3R        ADC3TBPER       LL_HRTIM_GetADCTrigSrc\n
02381   *         ADC3R        ADC3TBRST       LL_HRTIM_GetADCTrigSrc\n
02382   *         ADC3R        ADC3TCC2        LL_HRTIM_GetADCTrigSrc\n
02383   *         ADC3R        ADC3TCC3        LL_HRTIM_GetADCTrigSrc\n
02384   *         ADC3R        ADC3TCC4        LL_HRTIM_GetADCTrigSrc\n
02385   *         ADC3R        ADC3TCPER       LL_HRTIM_GetADCTrigSrc\n
02386   *         ADC3R        ADC3TDC2        LL_HRTIM_GetADCTrigSrc\n
02387   *         ADC3R        ADC3TDC3        LL_HRTIM_GetADCTrigSrc\n
02388   *         ADC3R        ADC3TDC4        LL_HRTIM_GetADCTrigSrc\n
02389   *         ADC3R        ADC3TDPER       LL_HRTIM_GetADCTrigSrc\n
02390   *         ADC3R        ADC3TEC2        LL_HRTIM_GetADCTrigSrc\n
02391   *         ADC3R        ADC3TEC3        LL_HRTIM_GetADCTrigSrc\n
02392   *         ADC3R        ADC3TEC4        LL_HRTIM_GetADCTrigSrc\n
02393   *         ADC3R        ADC3TEPER       LL_HRTIM_GetADCTrigSrc\n
02394   *         ADC4R        ADC4MC1         LL_HRTIM_GetADCTrigSrc\n
02395   *         ADC4R        ADC4MC2         LL_HRTIM_GetADCTrigSrc\n
02396   *         ADC4R        ADC4MC3         LL_HRTIM_GetADCTrigSrc\n
02397   *         ADC4R        ADC4MC4         LL_HRTIM_GetADCTrigSrc\n
02398   *         ADC4R        ADC4MPER        LL_HRTIM_GetADCTrigSrc\n
02399   *         ADC4R        ADC4EEV6        LL_HRTIM_GetADCTrigSrc\n
02400   *         ADC4R        ADC4EEV7        LL_HRTIM_GetADCTrigSrc\n
02401   *         ADC4R        ADC4EEV8        LL_HRTIM_GetADCTrigSrc\n
02402   *         ADC4R        ADC4EEV9        LL_HRTIM_GetADCTrigSrc\n
02403   *         ADC4R        ADC4EEV10       LL_HRTIM_GetADCTrigSrc\n
02404   *         ADC4R        ADC4TAC2        LL_HRTIM_GetADCTrigSrc\n
02405   *         ADC4R        ADC4TAC3        LL_HRTIM_GetADCTrigSrc\n
02406   *         ADC4R        ADC4TAC4        LL_HRTIM_GetADCTrigSrc\n
02407   *         ADC4R        ADC4TAPER       LL_HRTIM_GetADCTrigSrc\n
02408   *         ADC4R        ADC4TBC2        LL_HRTIM_GetADCTrigSrc\n
02409   *         ADC4R        ADC4TBC3        LL_HRTIM_GetADCTrigSrc\n
02410   *         ADC4R        ADC4TBC4        LL_HRTIM_GetADCTrigSrc\n
02411   *         ADC4R        ADC4TBPER       LL_HRTIM_GetADCTrigSrc\n
02412   *         ADC4R        ADC4TCC2        LL_HRTIM_GetADCTrigSrc\n
02413   *         ADC4R        ADC4TCC3        LL_HRTIM_GetADCTrigSrc\n
02414   *         ADC4R        ADC4TCC4        LL_HRTIM_GetADCTrigSrc\n
02415   *         ADC4R        ADC4TCPER       LL_HRTIM_GetADCTrigSrc\n
02416   *         ADC4R        ADC4TCRST       LL_HRTIM_GetADCTrigSrc\n
02417   *         ADC4R        ADC4TDC2        LL_HRTIM_GetADCTrigSrc\n
02418   *         ADC4R        ADC4TDC3        LL_HRTIM_GetADCTrigSrc\n
02419   *         ADC4R        ADC4TDC4        LL_HRTIM_GetADCTrigSrc\n
02420   *         ADC4R        ADC4TDPER       LL_HRTIM_GetADCTrigSrc\n
02421   *         ADC4R        ADC4TDRST       LL_HRTIM_GetADCTrigSrc\n
02422   *         ADC4R        ADC4TEC2        LL_HRTIM_GetADCTrigSrc\n
02423   *         ADC4R        ADC4TEC3        LL_HRTIM_GetADCTrigSrc\n
02424   *         ADC4R        ADC4TEC4        LL_HRTIM_GetADCTrigSrc\n
02425   *         ADC4R        ADC4TERST       LL_HRTIM_GetADCTrigSrc
02426   * @param  HRTIMx High Resolution Timer instance
02427   * @param  ADCTrig This parameter can be one of the following values:
02428   *         @arg @ref LL_HRTIM_ADCTRIG_1
02429   *         @arg @ref LL_HRTIM_ADCTRIG_2
02430   *         @arg @ref LL_HRTIM_ADCTRIG_3
02431   *         @arg @ref LL_HRTIM_ADCTRIG_4
02432   * @retval Src This parameter can be a combination of the following values:
02433   *
02434   *         For ADC trigger 1 and ADC trigger 3:
02435   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
02436   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
02437   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
02438   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
02439   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
02440   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
02441   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
02442   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
02443   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
02444   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
02445   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
02446   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
02447   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
02448   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
02449   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
02450   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
02451   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
02452   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
02453   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
02454   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
02455   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
02456   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
02457   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
02458   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
02459   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
02460   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
02461   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
02462   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
02463   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
02464   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
02465   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
02466   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
02467   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
02468   *
02469   *         For ADC trigger 2 and ADC trigger 4:
02470   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
02471   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
02472   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
02473   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
02474   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
02475   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
02476   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
02477   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
02478   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
02479   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
02480   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
02481   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
02482   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
02483   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
02484   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
02485   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
02486   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
02487   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
02488   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
02489   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
02490   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
02491   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
02492   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
02493   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
02494   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
02495   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
02496   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
02497   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
02498   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
02499   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
02500   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
02501   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
02502   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
02503   */
02504 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
02505 {
02506   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
02507                                                     REG_OFFSET_TAB_ADCxR[ADCTrig]));
02508   return (*pReg);
02509 }
02510
02511 /**
02512   * @brief  Configure the DLL calibration mode.
02513   * @rmtoll DLLCR        CALEN         LL_HRTIM_ConfigDLLCalibration\n
02514   *         DLLCR        CALRTE        LL_HRTIM_ConfigDLLCalibration
02515   * @param  HRTIMx High Resolution Timer instance
02516   * @param  Mode This parameter can be one of the following values:
02517   *         @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT
02518   *         @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS
02519    * @param  Period This parameter can be one of the following values:
02520   *         @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_7300
02521   *         @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_910
02522   *         @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_114
02523   *         @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_14
02524  * @retval None
02525   */
02526 __STATIC_INLINE void LL_HRTIM_ConfigDLLCalibration(HRTIM_TypeDef *HRTIMx, uint32_t Mode, uint32_t Period)
02527 {
02528   MODIFY_REG(HRTIMx->sCommonRegs.DLLCR, (HRTIM_DLLCR_CALEN | HRTIM_DLLCR_CALRTE), (Mode | Period));
02529 }
02530
02531 /**
02532   * @brief  Launch DLL calibration
02533   * @rmtoll DLLCR        CAL           LL_HRTIM_StartDLLCalibration
02534   * @param  HRTIMx High Resolution Timer instance
02535   * @retval None
02536   */
02537 __STATIC_INLINE void LL_HRTIM_StartDLLCalibration(HRTIM_TypeDef *HRTIMx)
02538 {
02539   SET_BIT(HRTIMx->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
02540 }
02541
02542 /**
02543   * @}
02544   */
02545
02546 /** @defgroup HRTIM_EF_HRTIM_Timer_Control HRTIM_Timer_Control
02547   * @{
02548   */
02549
02550 /**
02551   * @brief  Enable timer(s) counter.
02552   * @rmtoll MDIER        TECEN         LL_HRTIM_TIM_CounterEnable\n
02553   *         MDIER        TDCEN         LL_HRTIM_TIM_CounterEnable\n
02554   *         MDIER        TCCEN         LL_HRTIM_TIM_CounterEnable\n
02555   *         MDIER        TBCEN         LL_HRTIM_TIM_CounterEnable\n
02556   *         MDIER        TACEN         LL_HRTIM_TIM_CounterEnable\n
02557   *         MDIER        MCEN          LL_HRTIM_TIM_CounterEnable
02558   * @param  HRTIMx High Resolution Timer instance
02559   * @param  Timers This parameter can be a combination of the following values:
02560   *         @arg @ref LL_HRTIM_TIMER_MASTER
02561   *         @arg @ref LL_HRTIM_TIMER_A
02562   *         @arg @ref LL_HRTIM_TIMER_B
02563   *         @arg @ref LL_HRTIM_TIMER_C
02564   *         @arg @ref LL_HRTIM_TIMER_D
02565   *         @arg @ref LL_HRTIM_TIMER_E
02566   * @retval None
02567   */
02568 __STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
02569 {
02570   SET_BIT(HRTIMx->sMasterRegs.MCR, Timers);
02571 }
02572
02573 /**
02574   * @brief  Disable timer(s) counter.
02575   * @rmtoll MDIER        TECEN         LL_HRTIM_TIM_CounterDisable\n
02576   *         MDIER        TDCEN         LL_HRTIM_TIM_CounterDisable\n
02577   *         MDIER        TCCEN         LL_HRTIM_TIM_CounterDisable\n
02578   *         MDIER        TBCEN         LL_HRTIM_TIM_CounterDisable\n
02579   *         MDIER        TACEN         LL_HRTIM_TIM_CounterDisable\n
02580   *         MDIER        MCEN          LL_HRTIM_TIM_CounterDisable
02581   * @param  HRTIMx High Resolution Timer instance
02582   * @param  Timers This parameter can be a combination of the following values:
02583   *         @arg @ref LL_HRTIM_TIMER_MASTER
02584   *         @arg @ref LL_HRTIM_TIMER_A
02585   *         @arg @ref LL_HRTIM_TIMER_B
02586   *         @arg @ref LL_HRTIM_TIMER_C
02587   *         @arg @ref LL_HRTIM_TIMER_D
02588   *         @arg @ref LL_HRTIM_TIMER_E
02589   * @retval None
02590   */
02591 __STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
02592 {
02593   CLEAR_BIT(HRTIMx->sMasterRegs.MCR, Timers);
02594 }
02595
02596 /**
02597   * @brief  Indicate whether the timer counter is enabled.
02598   * @rmtoll MDIER        TECEN         LL_HRTIM_TIM_IsCounterEnabled\n
02599   *         MDIER        TDCEN         LL_HRTIM_TIM_IsCounterEnabled\n
02600   *         MDIER        TCCEN         LL_HRTIM_TIM_IsCounterEnabled\n
02601   *         MDIER        TBCEN         LL_HRTIM_TIM_IsCounterEnabled\n
02602   *         MDIER        TACEN         LL_HRTIM_TIM_IsCounterEnabled\n
02603   *         MDIER        MCEN          LL_HRTIM_TIM_IsCounterEnabled
02604   * @param  HRTIMx High Resolution Timer instance
02605   * @param  Timer This parameter can be one of the following values:
02606   *         @arg @ref LL_HRTIM_TIMER_MASTER
02607   *         @arg @ref LL_HRTIM_TIMER_A
02608   *         @arg @ref LL_HRTIM_TIMER_B
02609   *         @arg @ref LL_HRTIM_TIMER_C
02610   *         @arg @ref LL_HRTIM_TIMER_D
02611   *         @arg @ref LL_HRTIM_TIMER_E
02612   * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0).
02613   */
02614 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02615 {
02616   return (READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer));
02617 }
02618
02619 /**
02620   * @brief  Set the timer clock prescaler ratio.
02621   * @rmtoll MCR        CKPSC         LL_HRTIM_TIM_SetPrescaler\n
02622   *         TIMxCR     CKPSC         LL_HRTIM_TIM_SetPrescaler
02623   * @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0].
02624   * @note The prescaling ratio cannot be modified once the timer counter is enabled.
02625   * @param  HRTIMx High Resolution Timer instance
02626   * @param  Timer This parameter can be one of the following values:
02627   *         @arg @ref LL_HRTIM_TIMER_MASTER
02628   *         @arg @ref LL_HRTIM_TIMER_A
02629   *         @arg @ref LL_HRTIM_TIMER_B
02630   *         @arg @ref LL_HRTIM_TIMER_C
02631   *         @arg @ref LL_HRTIM_TIMER_D
02632   *         @arg @ref LL_HRTIM_TIMER_E
02633   * @param  Prescaler This parameter can be one of the following values:
02634   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
02635   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
02636   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
02637   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
02638   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
02639   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
02640   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
02641   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
02642   * @retval None
02643   */
02644 __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
02645 {
02646   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02647   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02648   MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler);
02649 }
02650
02651 /**
02652   * @brief  Get the timer clock prescaler ratio
02653   * @rmtoll MCR        CKPSC         LL_HRTIM_TIM_GetPrescaler\n
02654   *         TIMxCR     CKPSC         LL_HRTIM_TIM_GetPrescaler
02655   * @param  HRTIMx High Resolution Timer instance
02656   * @param  Timer This parameter can be one of the following values:
02657   *         @arg @ref LL_HRTIM_TIMER_MASTER
02658   *         @arg @ref LL_HRTIM_TIMER_A
02659   *         @arg @ref LL_HRTIM_TIMER_B
02660   *         @arg @ref LL_HRTIM_TIMER_C
02661   *         @arg @ref LL_HRTIM_TIMER_D
02662   *         @arg @ref LL_HRTIM_TIMER_E
02663   * @retval Prescaler Returned value can be one of the following values:
02664   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
02665   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
02666   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
02667   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
02668   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
02669   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
02670   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
02671   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
02672   */
02673 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02674 {
02675   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02676   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02677   return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC));
02678 }
02679
02680 /**
02681   * @brief  Set the counter operating mode mode (single-shot, continuous or re-triggerable).
02682   * @rmtoll MCR        CONT         LL_HRTIM_TIM_SetCounterMode\n
02683   *         MCR        RETRIG       LL_HRTIM_TIM_SetCounterMode\n
02684   *         TIMxCR     CONT         LL_HRTIM_TIM_SetCounterMode\n
02685   *         TIMxCR     RETRIG       LL_HRTIM_TIM_SetCounterMode
02686   * @param  HRTIMx High Resolution Timer instance
02687   * @param  Timer This parameter can be one of the following values:
02688   *         @arg @ref LL_HRTIM_TIMER_MASTER
02689   *         @arg @ref LL_HRTIM_TIMER_A
02690   *         @arg @ref LL_HRTIM_TIMER_B
02691   *         @arg @ref LL_HRTIM_TIMER_C
02692   *         @arg @ref LL_HRTIM_TIMER_D
02693   *         @arg @ref LL_HRTIM_TIMER_E
02694   * @param  Mode This parameter can be one of the following values:
02695   *         @arg @ref LL_HRTIM_MODE_CONTINUOUS
02696   *         @arg @ref LL_HRTIM_MODE_SINGLESHOT
02697   *         @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
02698   * @retval None
02699   */
02700 __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
02701 {
02702   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02703   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02704   MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode);
02705 }
02706
02707 /**
02708   * @brief  Get the counter operating mode mode
02709   * @rmtoll MCR        CONT         LL_HRTIM_TIM_GetCounterMode\n
02710   *         MCR        RETRIG       LL_HRTIM_TIM_GetCounterMode\n
02711   *         TIMxCR     CONT         LL_HRTIM_TIM_GetCounterMode\n
02712   *         TIMxCR     RETRIG       LL_HRTIM_TIM_GetCounterMode
02713   * @param  HRTIMx High Resolution Timer instance
02714   * @param  Timer This parameter can be one of the following values:
02715   *         @arg @ref LL_HRTIM_TIMER_MASTER
02716   *         @arg @ref LL_HRTIM_TIMER_A
02717   *         @arg @ref LL_HRTIM_TIMER_B
02718   *         @arg @ref LL_HRTIM_TIMER_C
02719   *         @arg @ref LL_HRTIM_TIMER_D
02720   *         @arg @ref LL_HRTIM_TIMER_E
02721   * @retval Mode Returned value can be one of the following values:
02722   *         @arg @ref LL_HRTIM_MODE_CONTINUOUS
02723   *         @arg @ref LL_HRTIM_MODE_SINGLESHOT
02724   *         @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
02725   */
02726 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02727 {
02728   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02729   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02730   return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT)));
02731 }
02732
02733 /**
02734   * @brief  Enable the half duty-cycle mode.
02735   * @rmtoll MCR        HALF         LL_HRTIM_TIM_EnableHalfMode\n
02736   *         TIMxCR     HALF         LL_HRTIM_TIM_EnableHalfMode
02737   * @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR)
02738   *       active register is automatically updated with HRTIM_MPER/2
02739   *       (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
02740   * @param  HRTIMx High Resolution Timer instance
02741   * @param  Timer This parameter can be one of the following values:
02742   *         @arg @ref LL_HRTIM_TIMER_MASTER
02743   *         @arg @ref LL_HRTIM_TIMER_A
02744   *         @arg @ref LL_HRTIM_TIMER_B
02745   *         @arg @ref LL_HRTIM_TIMER_C
02746   *         @arg @ref LL_HRTIM_TIMER_D
02747   *         @arg @ref LL_HRTIM_TIMER_E
02748   * @retval None
02749   */
02750 __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02751 {
02752   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02753   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02754   SET_BIT(*pReg, HRTIM_MCR_HALF);
02755 }
02756
02757 /**
02758   * @brief  Disable the half duty-cycle mode.
02759   * @rmtoll MCR        HALF         LL_HRTIM_TIM_DisableHalfMode\n
02760   *         TIMxCR     HALF         LL_HRTIM_TIM_DisableHalfMode
02761   * @param  HRTIMx High Resolution Timer instance
02762   * @param  Timer This parameter can be one of the following values:
02763   *         @arg @ref LL_HRTIM_TIMER_MASTER
02764   *         @arg @ref LL_HRTIM_TIMER_A
02765   *         @arg @ref LL_HRTIM_TIMER_B
02766   *         @arg @ref LL_HRTIM_TIMER_C
02767   *         @arg @ref LL_HRTIM_TIMER_D
02768   *         @arg @ref LL_HRTIM_TIMER_E
02769   * @retval None
02770   */
02771 __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02772 {
02773   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02774   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02775   CLEAR_BIT(*pReg, HRTIM_MCR_HALF);
02776 }
02777
02778 /**
02779   * @brief  Indicate whether half duty-cycle mode is enabled for a given timer.
02780   * @rmtoll MCR        HALF         LL_HRTIM_TIM_IsEnabledHalfMode\n
02781   *         TIMxCR     HALF         LL_HRTIM_TIM_IsEnabledHalfMode
02782   * @param  HRTIMx High Resolution Timer instance
02783   * @param  Timer This parameter can be one of the following values:
02784   *         @arg @ref LL_HRTIM_TIMER_MASTER
02785   *         @arg @ref LL_HRTIM_TIMER_A
02786   *         @arg @ref LL_HRTIM_TIMER_B
02787   *         @arg @ref LL_HRTIM_TIMER_C
02788   *         @arg @ref LL_HRTIM_TIMER_D
02789   *         @arg @ref LL_HRTIM_TIMER_E
02790   * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
02791   */
02792 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02793 {
02794   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02795   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02796   return (READ_BIT(*pReg, HRTIM_MCR_HALF) == HRTIM_MCR_HALF);
02797 }
02798
02799 /**
02800   * @brief  Enable the timer start when receiving a synchronization input event.
02801   * @rmtoll MCR        SYNCSTRTM        LL_HRTIM_TIM_EnableStartOnSync\n
02802   *         TIMxCR     SYNSTRTA         LL_HRTIM_TIM_EnableStartOnSync
02803   * @param  HRTIMx High Resolution Timer instance
02804   * @param  Timer This parameter can be one of the following values:
02805   *         @arg @ref LL_HRTIM_TIMER_MASTER
02806   *         @arg @ref LL_HRTIM_TIMER_A
02807   *         @arg @ref LL_HRTIM_TIMER_B
02808   *         @arg @ref LL_HRTIM_TIMER_C
02809   *         @arg @ref LL_HRTIM_TIMER_D
02810   *         @arg @ref LL_HRTIM_TIMER_E
02811   * @retval None
02812   */
02813 __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02814 {
02815   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02816   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02817   SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
02818 }
02819
02820 /**
02821   * @brief  Disable the timer start when receiving a synchronization input event.
02822   * @rmtoll MCR        SYNCSTRTM        LL_HRTIM_TIM_DisableStartOnSync\n
02823   *         TIMxCR     SYNSTRTA         LL_HRTIM_TIM_DisableStartOnSync
02824   * @param  HRTIMx High Resolution Timer instance
02825   * @param  Timer This parameter can be one of the following values:
02826   *         @arg @ref LL_HRTIM_TIMER_MASTER
02827   *         @arg @ref LL_HRTIM_TIMER_A
02828   *         @arg @ref LL_HRTIM_TIMER_B
02829   *         @arg @ref LL_HRTIM_TIMER_C
02830   *         @arg @ref LL_HRTIM_TIMER_D
02831   *         @arg @ref LL_HRTIM_TIMER_E
02832   * @retval None
02833   */
02834 __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02835 {
02836   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02837   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02838   CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
02839 }
02840
02841 /**
02842   * @brief  Indicate whether the timer start when receiving a synchronization input event.
02843   * @rmtoll MCR        SYNCSTRTM        LL_HRTIM_TIM_IsEnabledStartOnSync\n
02844   *         TIMxCR     SYNSTRTA         LL_HRTIM_TIM_IsEnabledStartOnSync
02845   * @param  HRTIMx High Resolution Timer instance
02846   * @param  Timer This parameter can be one of the following values:
02847   *         @arg @ref LL_HRTIM_TIMER_MASTER
02848   *         @arg @ref LL_HRTIM_TIMER_A
02849   *         @arg @ref LL_HRTIM_TIMER_B
02850   *         @arg @ref LL_HRTIM_TIMER_C
02851   *         @arg @ref LL_HRTIM_TIMER_D
02852   *         @arg @ref LL_HRTIM_TIMER_E
02853   * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
02854   */
02855 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02856 {
02857   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02858   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02859   return (READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == HRTIM_MCR_SYNCSTRTM);
02860 }
02861
02862 /**
02863   * @brief  Enable the timer reset when receiving a synchronization input event.
02864   * @rmtoll MCR        SYNCRSTM        LL_HRTIM_TIM_EnableResetOnSync\n
02865   *         TIMxCR     SYNCRSTA        LL_HRTIM_TIM_EnableResetOnSync
02866   * @param  HRTIMx High Resolution Timer instance
02867   * @param  Timer This parameter can be one of the following values:
02868   *         @arg @ref LL_HRTIM_TIMER_MASTER
02869   *         @arg @ref LL_HRTIM_TIMER_A
02870   *         @arg @ref LL_HRTIM_TIMER_B
02871   *         @arg @ref LL_HRTIM_TIMER_C
02872   *         @arg @ref LL_HRTIM_TIMER_D
02873   *         @arg @ref LL_HRTIM_TIMER_E
02874   * @retval None
02875   */
02876 __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02877 {
02878   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02879   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02880   SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
02881 }
02882
02883 /**
02884   * @brief  Disable the timer reset when receiving a synchronization input event.
02885   * @rmtoll MCR        SYNCRSTM        LL_HRTIM_TIM_DisableResetOnSync\n
02886   *         TIMxCR     SYNCRSTA        LL_HRTIM_TIM_DisableResetOnSync
02887   * @param  HRTIMx High Resolution Timer instance
02888   * @param  Timer This parameter can be one of the following values:
02889   *         @arg @ref LL_HRTIM_TIMER_MASTER
02890   *         @arg @ref LL_HRTIM_TIMER_A
02891   *         @arg @ref LL_HRTIM_TIMER_B
02892   *         @arg @ref LL_HRTIM_TIMER_C
02893   *         @arg @ref LL_HRTIM_TIMER_D
02894   *         @arg @ref LL_HRTIM_TIMER_E
02895   * @retval None
02896   */
02897 __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02898 {
02899   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02900   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02901   CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
02902 }
02903
02904 /**
02905   * @brief  Indicate whether the timer reset when receiving a synchronization input event.
02906   * @rmtoll MCR        SYNCRSTM        LL_HRTIM_TIM_IsEnabledResetOnSync\n
02907   *         TIMxCR     SYNCRSTA        LL_HRTIM_TIM_IsEnabledResetOnSync
02908   * @param  HRTIMx High Resolution Timer instance
02909   * @param  Timer This parameter can be one of the following values:
02910   *         @arg @ref LL_HRTIM_TIMER_MASTER
02911   *         @arg @ref LL_HRTIM_TIMER_A
02912   *         @arg @ref LL_HRTIM_TIMER_B
02913   *         @arg @ref LL_HRTIM_TIMER_C
02914   *         @arg @ref LL_HRTIM_TIMER_D
02915   *         @arg @ref LL_HRTIM_TIMER_E
02916   * @retval None
02917   */
02918 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02919 {
02920   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02921   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02922   return (READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == HRTIM_MCR_SYNCRSTM);
02923 }
02924
02925 /**
02926   * @brief  Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
02927   * @rmtoll MCR        DACSYNC        LL_HRTIM_TIM_SetDACTrig\n
02928   *         TIMxCR     DACSYNC        LL_HRTIM_TIM_SetDACTrig
02929   * @param  HRTIMx High Resolution Timer instance
02930   * @param  Timer This parameter can be one of the following values:
02931   *         @arg @ref LL_HRTIM_TIMER_MASTER
02932   *         @arg @ref LL_HRTIM_TIMER_A
02933   *         @arg @ref LL_HRTIM_TIMER_B
02934   *         @arg @ref LL_HRTIM_TIMER_C
02935   *         @arg @ref LL_HRTIM_TIMER_D
02936   *         @arg @ref LL_HRTIM_TIMER_E
02937   * @param  DACTrig This parameter can be one of the following values:
02938   *         @arg @ref LL_HRTIM_DACTRIG_NONE
02939   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
02940   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
02941   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
02942   * @retval None
02943   */
02944 __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig)
02945 {
02946   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02947   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02948   MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig);
02949 }
02950
02951 /**
02952   * @brief  Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
02953   * @rmtoll MCR        DACSYNC        LL_HRTIM_TIM_GetDACTrig\n
02954   *         TIMxCR     DACSYNC        LL_HRTIM_TIM_GetDACTrig
02955   * @param  HRTIMx High Resolution Timer instance
02956   * @param  Timer This parameter can be one of the following values:
02957   *         @arg @ref LL_HRTIM_TIMER_MASTER
02958   *         @arg @ref LL_HRTIM_TIMER_A
02959   *         @arg @ref LL_HRTIM_TIMER_B
02960   *         @arg @ref LL_HRTIM_TIMER_C
02961   *         @arg @ref LL_HRTIM_TIMER_D
02962   *         @arg @ref LL_HRTIM_TIMER_E
02963   * @retval DACTrig Returned value can be one of the following values:
02964   *         @arg @ref LL_HRTIM_DACTRIG_NONE
02965   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
02966   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
02967   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
02968   */
02969 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02970 {
02971   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02972   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02973   return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC));
02974 }
02975
02976 /**
02977   * @brief  Enable the timer registers preload mechanism.
02978   * @rmtoll MCR        PREEN        LL_HRTIM_TIM_EnablePreload\n
02979   *         TIMxCR     PREEN        LL_HRTIM_TIM_EnablePreload
02980   * @note When the preload mode is enabled, accessed registers are shadow registers.
02981   *       Their content is transferred into the active register after an update request,
02982   *       either software or synchronized with an event.
02983   * @param  HRTIMx High Resolution Timer instance
02984   * @param  Timer This parameter can be one of the following values:
02985   *         @arg @ref LL_HRTIM_TIMER_MASTER
02986   *         @arg @ref LL_HRTIM_TIMER_A
02987   *         @arg @ref LL_HRTIM_TIMER_B
02988   *         @arg @ref LL_HRTIM_TIMER_C
02989   *         @arg @ref LL_HRTIM_TIMER_D
02990   *         @arg @ref LL_HRTIM_TIMER_E
02991   * @retval None
02992   */
02993 __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02994 {
02995   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02996   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02997   SET_BIT(*pReg, HRTIM_MCR_PREEN);
02998 }
02999
03000 /**
03001   * @brief  Disable the timer registers preload mechanism.
03002   * @rmtoll MCR        PREEN        LL_HRTIM_TIM_DisablePreload\n
03003   *         TIMxCR     PREEN        LL_HRTIM_TIM_DisablePreload
03004   * @param  HRTIMx High Resolution Timer instance
03005   * @param  Timer This parameter can be one of the following values:
03006   *         @arg @ref LL_HRTIM_TIMER_MASTER
03007   *         @arg @ref LL_HRTIM_TIMER_A
03008   *         @arg @ref LL_HRTIM_TIMER_B
03009   *         @arg @ref LL_HRTIM_TIMER_C
03010   *         @arg @ref LL_HRTIM_TIMER_D
03011   *         @arg @ref LL_HRTIM_TIMER_E
03012   * @retval None
03013   */
03014 __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03015 {
03016   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03017   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
03018   CLEAR_BIT(*pReg, HRTIM_MCR_PREEN);
03019 }
03020
03021 /**
03022   * @brief  Indicate whether the timer registers preload mechanism is enabled.
03023   * @rmtoll MCR        PREEN        LL_HRTIM_TIM_IsEnabledPreload\n
03024   *         TIMxCR     PREEN        LL_HRTIM_TIM_IsEnabledPreload
03025   * @param  HRTIMx High Resolution Timer instance
03026   * @param  Timer This parameter can be one of the following values:
03027   *         @arg @ref LL_HRTIM_TIMER_MASTER
03028   *         @arg @ref LL_HRTIM_TIMER_A
03029   *         @arg @ref LL_HRTIM_TIMER_B
03030   *         @arg @ref LL_HRTIM_TIMER_C
03031   *         @arg @ref LL_HRTIM_TIMER_D
03032   *         @arg @ref LL_HRTIM_TIMER_E
03033   * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
03034   */
03035 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03036 {
03037   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03038   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
03039   return (READ_BIT(*pReg, HRTIM_MCR_PREEN) == HRTIM_MCR_PREEN);
03040 }
03041
03042 /**
03043   * @brief  Set the timer register update trigger.
03044   * @rmtoll MCR           MREPU      LL_HRTIM_TIM_SetUpdateTrig\n
03045   *         TIMxCR        TAU        LL_HRTIM_TIM_SetUpdateTrig\n
03046   *         TIMxCR        TBU        LL_HRTIM_TIM_SetUpdateTrig\n
03047   *         TIMxCR        TCU        LL_HRTIM_TIM_SetUpdateTrig\n
03048   *         TIMxCR        TDU        LL_HRTIM_TIM_SetUpdateTrig\n
03049   *         TIMxCR        TEU        LL_HRTIM_TIM_SetUpdateTrig\n
03050   *         TIMxCR        MSTU       LL_HRTIM_TIM_SetUpdateTrig
03051   * @param  HRTIMx High Resolution Timer instance
03052   * @param  Timer This parameter can be one of the following values:
03053   *         @arg @ref LL_HRTIM_TIMER_MASTER
03054   *         @arg @ref LL_HRTIM_TIMER_A
03055   *         @arg @ref LL_HRTIM_TIMER_B
03056   *         @arg @ref LL_HRTIM_TIMER_C
03057   *         @arg @ref LL_HRTIM_TIMER_D
03058   *         @arg @ref LL_HRTIM_TIMER_E
03059   * @param  UpdateTrig This parameter can be one of the following values:
03060   *
03061   *         For the master timer this parameter can be one of the following values:
03062   *         @arg @ref LL_HRTIM_UPDATETRIG_NONE
03063   *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
03064   *
03065   *         For timer A..E this parameter can be:
03066   *         @arg @ref LL_HRTIM_UPDATETRIG_NONE
03067   *         or a combination of the following values:
03068   *         @arg @ref LL_HRTIM_UPDATETRIG_MASTER
03069   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
03070   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
03071   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
03072   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
03073   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
03074   *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
03075   *         @arg @ref LL_HRTIM_UPDATETRIG_RESET
03076   * @retval None
03077   */
03078 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig)
03079 {
03080   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03081   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
03082   MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]);
03083 }
03084
03085 /**
03086   * @brief  Set the timer register update trigger.
03087   * @rmtoll MCR           MREPU      LL_HRTIM_TIM_GetUpdateTrig\n
03088   *         TIMxCR        TBU        LL_HRTIM_TIM_GetUpdateTrig\n
03089   *         TIMxCR        TCU        LL_HRTIM_TIM_GetUpdateTrig\n
03090   *         TIMxCR        TDU        LL_HRTIM_TIM_GetUpdateTrig\n
03091   *         TIMxCR        TEU        LL_HRTIM_TIM_GetUpdateTrig\n
03092   *         TIMxCR        MSTU       LL_HRTIM_TIM_GetUpdateTrig
03093  * @param  HRTIMx High Resolution Timer instance
03094   * @param  Timer This parameter can be one of the following values:
03095   *         @arg @ref LL_HRTIM_TIMER_MASTER
03096   *         @arg @ref LL_HRTIM_TIMER_A
03097   *         @arg @ref LL_HRTIM_TIMER_B
03098   *         @arg @ref LL_HRTIM_TIMER_C
03099   *         @arg @ref LL_HRTIM_TIMER_D
03100   *         @arg @ref LL_HRTIM_TIMER_E
03101   * @retval UpdateTrig Returned value can be one of the following values:
03102   *
03103   *         For the master timer this parameter can be one of the following values:
03104   *         @arg @ref LL_HRTIM_UPDATETRIG_NONE
03105   *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
03106   *
03107   *         For timer A..E this parameter can be:
03108   *         @arg @ref LL_HRTIM_UPDATETRIG_NONE
03109   *         or a combination of the following values:
03110   *         @arg @ref LL_HRTIM_UPDATETRIG_MASTER
03111   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
03112   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
03113   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
03114   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
03115   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
03116   *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
03117   *         @arg @ref LL_HRTIM_UPDATETRIG_RESET
03118   */
03119 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03120 {
03121   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03122   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
03123   return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >>  REG_SHIFT_TAB_UPDATETRIG[iTimer]);
03124 }
03125
03126 /**
03127   * @brief  Set  the timer registers update condition (how the registers update occurs relatively to the burst DMA  transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])).
03128   * @rmtoll MCR           BRSTDMA      LL_HRTIM_TIM_SetUpdateGating\n
03129   *         TIMxCR        UPDGAT       LL_HRTIM_TIM_SetUpdateGating
03130   * @param  HRTIMx High Resolution Timer instance
03131   * @param  Timer This parameter can be one of the following values:
03132   *         @arg @ref LL_HRTIM_TIMER_MASTER
03133   *         @arg @ref LL_HRTIM_TIMER_A
03134   *         @arg @ref LL_HRTIM_TIMER_B
03135   *         @arg @ref LL_HRTIM_TIMER_C
03136   *         @arg @ref LL_HRTIM_TIMER_D
03137   *         @arg @ref LL_HRTIM_TIMER_E
03138   * @param  UpdateGating This parameter can be one of the following values:
03139   *
03140   *         For the master timer this parameter can be one of the following values:
03141   *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
03142   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
03143   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
03144   *
03145   *         For the timer A..E this parameter can be one of the following values:
03146   *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
03147   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
03148   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
03149   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
03150   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
03151   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
03152   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
03153   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
03154   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
03155   * @retval None
03156   */
03157 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating)
03158 {
03159   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03160   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
03161   MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer]));
03162 }
03163
03164 /**
03165   * @brief  Get  the timer registers update condition.
03166   * @rmtoll MCR           BRSTDMA      LL_HRTIM_TIM_GetUpdateGating\n
03167   *         TIMxCR        UPDGAT       LL_HRTIM_TIM_GetUpdateGating
03168   * @param  HRTIMx High Resolution Timer instance
03169   * @param  Timer This parameter can be one of the following values:
03170   *         @arg @ref LL_HRTIM_TIMER_MASTER
03171   *         @arg @ref LL_HRTIM_TIMER_A
03172   *         @arg @ref LL_HRTIM_TIMER_B
03173   *         @arg @ref LL_HRTIM_TIMER_C
03174   *         @arg @ref LL_HRTIM_TIMER_D
03175   *         @arg @ref LL_HRTIM_TIMER_E
03176   * @retval UpdateGating Returned value can be one of the following values:
03177   *
03178   *         For the master timer this parameter can be one of the following values:
03179   *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
03180   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
03181   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
03182   *
03183   *         For the timer A..E this parameter can be one of the following values:
03184   *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
03185   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
03186   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
03187   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
03188   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
03189   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
03190   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
03191   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
03192   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
03193   */
03194 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03195 {
03196   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03197   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
03198   return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >>  REG_SHIFT_TAB_UPDATEGATING[iTimer]);
03199 }
03200
03201 /**
03202   * @brief  Enable the push-pull mode.
03203   * @rmtoll TIMxCR        PSHPLL       LL_HRTIM_TIM_EnablePushPullMode
03204   * @param  HRTIMx High Resolution Timer instance
03205   * @param  Timer This parameter can be one of the following values:
03206   *         @arg @ref LL_HRTIM_TIMER_A
03207   *         @arg @ref LL_HRTIM_TIMER_B
03208   *         @arg @ref LL_HRTIM_TIMER_C
03209   *         @arg @ref LL_HRTIM_TIMER_D
03210   *         @arg @ref LL_HRTIM_TIMER_E
03211   * @retval None
03212   */
03213 __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03214 {
03215   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03216   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
03217                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03218   SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
03219 }
03220
03221 /**
03222   * @brief  Disable the push-pull mode.
03223   * @rmtoll TIMxCR        PSHPLL       LL_HRTIM_TIM_DisablePushPullMode
03224   * @param  HRTIMx High Resolution Timer instance
03225   * @param  Timer This parameter can be one of the following values:
03226   *         @arg @ref LL_HRTIM_TIMER_A
03227   *         @arg @ref LL_HRTIM_TIMER_B
03228   *         @arg @ref LL_HRTIM_TIMER_C
03229   *         @arg @ref LL_HRTIM_TIMER_D
03230   *         @arg @ref LL_HRTIM_TIMER_E
03231   * @retval None
03232   */
03233 __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03234 {
03235   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03236   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
03237                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03238   CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
03239 }
03240
03241 /**
03242   * @brief  Indicate whether the push-pull mode is enabled.
03243   * @rmtoll TIMxCR        PSHPLL       LL_HRTIM_TIM_IsEnabledPushPullMode\n
03244   * @param  HRTIMx High Resolution Timer instance
03245   * @param  Timer This parameter can be one of the following values:
03246   *         @arg @ref LL_HRTIM_TIMER_A
03247   *         @arg @ref LL_HRTIM_TIMER_B
03248   *         @arg @ref LL_HRTIM_TIMER_C
03249   *         @arg @ref LL_HRTIM_TIMER_D
03250   *         @arg @ref LL_HRTIM_TIMER_E
03251   * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0).
03252   */
03253 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03254 {
03255   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03256   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
03257                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03258   return (READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == HRTIM_TIMCR_PSHPLL);
03259 }
03260
03261 /**
03262   * @brief  Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode).
03263   * @rmtoll TIMxCR        DELCMP2       LL_HRTIM_TIM_SetCompareMode\n
03264   *         TIMxCR        DELCMP4       LL_HRTIM_TIM_SetCompareMode
03265   * @note In auto-delayed mode  the compare match occurs independently from the timer counter value.
03266   * @param  HRTIMx High Resolution Timer instance
03267   * @param  Timer This parameter can be one of the following values:
03268   *         @arg @ref LL_HRTIM_TIMER_A
03269   *         @arg @ref LL_HRTIM_TIMER_B
03270   *         @arg @ref LL_HRTIM_TIMER_C
03271   *         @arg @ref LL_HRTIM_TIMER_D
03272   *         @arg @ref LL_HRTIM_TIMER_E
03273   * @param  CompareUnit This parameter can be one of the following values:
03274   *         @arg @ref LL_HRTIM_COMPAREUNIT_2
03275   *         @arg @ref LL_HRTIM_COMPAREUNIT_4
03276   * @param  Mode This parameter can be one of the following values:
03277   *         @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
03278   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
03279   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
03280   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
03281   * @retval None
03282   */
03283 __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit,
03284                                                  uint32_t Mode)
03285 {
03286   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03287   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
03288                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03289   register uint32_t shift = POSITION_VAL(CompareUnit) - POSITION_VAL(LL_HRTIM_COMPAREUNIT_2);
03290   MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift));
03291 }
03292
03293 /**
03294   * @brief  Get the functioning mode of the compare unit.
03295   * @rmtoll TIMxCR        DELCMP2       LL_HRTIM_TIM_GetCompareMode\n
03296   *         TIMxCR        DELCMP4       LL_HRTIM_TIM_GetCompareMode
03297   * @param  HRTIMx High Resolution Timer instance
03298   * @param  Timer This parameter can be one of the following values:
03299   *         @arg @ref LL_HRTIM_TIMER_A
03300   *         @arg @ref LL_HRTIM_TIMER_B
03301   *         @arg @ref LL_HRTIM_TIMER_C
03302   *         @arg @ref LL_HRTIM_TIMER_D
03303   *         @arg @ref LL_HRTIM_TIMER_E
03304   * @param  CompareUnit This parameter can be one of the following values:
03305   *         @arg @ref LL_HRTIM_COMPAREUNIT_2
03306   *         @arg @ref LL_HRTIM_COMPAREUNIT_4
03307   * @retval Mode Returned value can be one of the following values:
03308   *         @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
03309   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
03310   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
03311   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
03312   */
03313 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
03314 {
03315   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03316   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
03317                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03318   register uint32_t shift = POSITION_VAL(CompareUnit) - POSITION_VAL(LL_HRTIM_COMPAREUNIT_2);
03319   return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >>  shift);
03320 }
03321
03322 /**
03323   * @brief  Set the timer counter value.
03324   * @rmtoll MCNTR        MCNT       LL_HRTIM_TIM_SetCounter\n
03325   *         CNTxR        CNTx       LL_HRTIM_TIM_SetCounter
03326   * @note  This function can only be called when the timer is stopped.
03327   * @note  For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least
03328   *        significant bits of the counter are not significant. They cannot be
03329   *        written and return 0 when read.
03330   * @note The timer behavior is not guaranteed if the counter value is set above
03331   *       the period.
03332   * @param  HRTIMx High Resolution Timer instance
03333   * @param  Timer This parameter can be one of the following values:
03334   *         @arg @ref LL_HRTIM_TIMER_MASTER
03335   *         @arg @ref LL_HRTIM_TIMER_A
03336   *         @arg @ref LL_HRTIM_TIMER_B
03337   *         @arg @ref LL_HRTIM_TIMER_C
03338   *         @arg @ref LL_HRTIM_TIMER_D
03339   *         @arg @ref LL_HRTIM_TIMER_E
03340   * @param  Counter Value between 0 and 0xFFFF
03341   * @retval None
03342   */
03343 __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter)
03344 {
03345   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03346   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
03347                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03348   MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter);
03349 }
03350
03351 /**
03352   * @brief  Get actual timer counter value.
03353   * @rmtoll MCNTR        MCNT       LL_HRTIM_TIM_GetCounter\n
03354   *         CNTxR        CNTx       LL_HRTIM_TIM_GetCounter
03355   * @param  HRTIMx High Resolution Timer instance
03356   * @param  Timer This parameter can be one of the following values:
03357   *         @arg @ref LL_HRTIM_TIMER_MASTER
03358   *         @arg @ref LL_HRTIM_TIMER_A
03359   *         @arg @ref LL_HRTIM_TIMER_B
03360   *         @arg @ref LL_HRTIM_TIMER_C
03361   *         @arg @ref LL_HRTIM_TIMER_D
03362   *         @arg @ref LL_HRTIM_TIMER_E
03363   * @retval Counter Value between 0 and 0xFFFF
03364   */
03365 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03366 {
03367   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03368   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
03369                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03370   return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR));
03371 }
03372
03373 /**
03374   * @brief  Set the timer period value.
03375   * @rmtoll MPER        MPER       LL_HRTIM_TIM_SetPeriod\n
03376   *         PERxR       PERx       LL_HRTIM_TIM_SetPeriod
03377   * @param  HRTIMx High Resolution Timer instance
03378   * @param  Timer This parameter can be one of the following values:
03379   *         @arg @ref LL_HRTIM_TIMER_MASTER
03380   *         @arg @ref LL_HRTIM_TIMER_A
03381   *         @arg @ref LL_HRTIM_TIMER_B
03382   *         @arg @ref LL_HRTIM_TIMER_C
03383   *         @arg @ref LL_HRTIM_TIMER_D
03384   *         @arg @ref LL_HRTIM_TIMER_E
03385   * @param  Period Value between 0 and 0xFFFF
03386   * @retval None
03387   */
03388 __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period)
03389 {
03390   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03391   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
03392                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03393   MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period);
03394 }
03395
03396 /**
03397   * @brief  Get actual timer period value.
03398   * @rmtoll MPER        MPER       LL_HRTIM_TIM_GetPeriod\n
03399   *         PERxR       PERx       LL_HRTIM_TIM_GetPeriod
03400   * @param  HRTIMx High Resolution Timer instance
03401   * @param  Timer This parameter can be one of the following values:
03402   *         @arg @ref LL_HRTIM_TIMER_MASTER
03403   *         @arg @ref LL_HRTIM_TIMER_A
03404   *         @arg @ref LL_HRTIM_TIMER_B
03405   *         @arg @ref LL_HRTIM_TIMER_C
03406   *         @arg @ref LL_HRTIM_TIMER_D
03407   *         @arg @ref LL_HRTIM_TIMER_E
03408   * @retval Period Value between 0 and 0xFFFF
03409   */
03410 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03411 {
03412   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03413   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
03414                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03415   return (READ_BIT(*pReg, HRTIM_MPER_MPER));
03416 }
03417
03418 /**
03419   * @brief  Set the timer repetition period value.
03420   * @rmtoll MREP        MREP       LL_HRTIM_TIM_SetRepetition\n
03421   *         REPxR       REPx       LL_HRTIM_TIM_SetRepetition
03422   * @param  HRTIMx High Resolution Timer instance
03423   * @param  Timer This parameter can be one of the following values:
03424   *         @arg @ref LL_HRTIM_TIMER_MASTER
03425   *         @arg @ref LL_HRTIM_TIMER_A
03426   *         @arg @ref LL_HRTIM_TIMER_B
03427   *         @arg @ref LL_HRTIM_TIMER_C
03428   *         @arg @ref LL_HRTIM_TIMER_D
03429   *         @arg @ref LL_HRTIM_TIMER_E
03430   * @param  Repetition Value between 0 and 0xFF
03431   * @retval None
03432   */
03433 __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition)
03434 {
03435   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03436   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
03437                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03438   MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition);
03439 }
03440
03441 /**
03442   * @brief  Get actual timer repetition period value.
03443   * @rmtoll MREP        MREP       LL_HRTIM_TIM_GetRepetition\n
03444   *         REPxR       REPx       LL_HRTIM_TIM_GetRepetition
03445   * @param  HRTIMx High Resolution Timer instance
03446   * @param  Timer This parameter can be one of the following values:
03447   *         @arg @ref LL_HRTIM_TIMER_MASTER
03448   *         @arg @ref LL_HRTIM_TIMER_A
03449   *         @arg @ref LL_HRTIM_TIMER_B
03450   *         @arg @ref LL_HRTIM_TIMER_C
03451   *         @arg @ref LL_HRTIM_TIMER_D
03452   *         @arg @ref LL_HRTIM_TIMER_E
03453   * @retval Repetition Value between 0 and 0xFF
03454   */
03455 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03456 {
03457   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03458   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
03459                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03460   return (READ_BIT(*pReg, HRTIM_MREP_MREP));
03461 }
03462
03463 /**
03464   * @brief  Set the compare value of the compare unit 1.
03465   * @rmtoll MCMP1R      MCMP1       LL_HRTIM_TIM_SetCompare1\n
03466   *         CMP1xR      CMP1x       LL_HRTIM_TIM_SetCompare1
03467   * @param  HRTIMx High Resolution Timer instance
03468   * @param  Timer This parameter can be one of the following values:
03469   *         @arg @ref LL_HRTIM_TIMER_MASTER
03470   *         @arg @ref LL_HRTIM_TIMER_A
03471   *         @arg @ref LL_HRTIM_TIMER_B
03472   *         @arg @ref LL_HRTIM_TIMER_C
03473   *         @arg @ref LL_HRTIM_TIMER_D
03474   *         @arg @ref LL_HRTIM_TIMER_E
03475   * @param  CompareValue Compare value must be above or equal to 3
03476   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
03477   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
03478   * @retval None
03479   */
03480 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
03481 {
03482   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03483   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
03484                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03485   MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue);
03486 }
03487
03488 /**
03489   * @brief  Get actual compare value of the compare unit 1.
03490   * @rmtoll MCMP1R      MCMP1       LL_HRTIM_TIM_GetCompare1\n
03491   *         CMP1xR      CMP1x       LL_HRTIM_TIM_GetCompare1
03492   * @param  HRTIMx High Resolution Timer instance
03493   * @param  Timer This parameter can be one of the following values:
03494   *         @arg @ref LL_HRTIM_TIMER_MASTER
03495   *         @arg @ref LL_HRTIM_TIMER_A
03496   *         @arg @ref LL_HRTIM_TIMER_B
03497   *         @arg @ref LL_HRTIM_TIMER_C
03498   *         @arg @ref LL_HRTIM_TIMER_D
03499   *         @arg @ref LL_HRTIM_TIMER_E
03500   * @retval CompareValue Compare value must be above or equal to 3
03501   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
03502   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
03503   */
03504 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03505 {
03506   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03507   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
03508                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03509   return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R));
03510 }
03511
03512 /**
03513   * @brief  Set the compare value of the compare unit 2.
03514   * @rmtoll MCMP2R      MCMP2       LL_HRTIM_TIM_SetCompare2\n
03515   *         CMP2xR      CMP2x       LL_HRTIM_TIM_SetCompare2
03516   * @param  HRTIMx High Resolution Timer instance
03517   * @param  Timer This parameter can be one of the following values:
03518   *         @arg @ref LL_HRTIM_TIMER_MASTER
03519   *         @arg @ref LL_HRTIM_TIMER_A
03520   *         @arg @ref LL_HRTIM_TIMER_B
03521   *         @arg @ref LL_HRTIM_TIMER_C
03522   *         @arg @ref LL_HRTIM_TIMER_D
03523   *         @arg @ref LL_HRTIM_TIMER_E
03524   * @param  CompareValue Compare value must be above or equal to 3
03525   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
03526   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
03527   * @retval None
03528   */
03529 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
03530 {
03531   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03532   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
03533                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03534   MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue);
03535 }
03536
03537 /**
03538   * @brief  Get actual compare value of the compare unit 2.
03539   * @rmtoll MCMP2R      MCMP2       LL_HRTIM_TIM_GetCompare2\n
03540   *         CMP2xR      CMP2x       LL_HRTIM_TIM_GetCompare2\n
03541   * @param  HRTIMx High Resolution Timer instance
03542   * @param  Timer This parameter can be one of the following values:
03543   *         @arg @ref LL_HRTIM_TIMER_MASTER
03544   *         @arg @ref LL_HRTIM_TIMER_A
03545   *         @arg @ref LL_HRTIM_TIMER_B
03546   *         @arg @ref LL_HRTIM_TIMER_C
03547   *         @arg @ref LL_HRTIM_TIMER_D
03548   *         @arg @ref LL_HRTIM_TIMER_E
03549   * @retval CompareValue Compare value must be above or equal to 3
03550   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
03551   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
03552   */
03553 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03554 {
03555   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03556   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
03557                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03558   return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R));
03559 }
03560
03561 /**
03562   * @brief  Set the compare value of the compare unit 3.
03563   * @rmtoll MCMP3R      MCMP3       LL_HRTIM_TIM_SetCompare3\n
03564   *         CMP3xR      CMP3x       LL_HRTIM_TIM_SetCompare3
03565   * @param  HRTIMx High Resolution Timer instance
03566   * @param  Timer This parameter can be one of the following values:
03567   *         @arg @ref LL_HRTIM_TIMER_MASTER
03568   *         @arg @ref LL_HRTIM_TIMER_A
03569   *         @arg @ref LL_HRTIM_TIMER_B
03570   *         @arg @ref LL_HRTIM_TIMER_C
03571   *         @arg @ref LL_HRTIM_TIMER_D
03572   *         @arg @ref LL_HRTIM_TIMER_E
03573   * @param  CompareValue Compare value must be above or equal to 3
03574   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
03575   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
03576   * @retval None
03577   */
03578 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
03579 {
03580   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03581   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
03582                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03583   MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue);
03584 }
03585
03586 /**
03587   * @brief  Get actual compare value of the compare unit 3.
03588   * @rmtoll MCMP3R      MCMP3       LL_HRTIM_TIM_GetCompare3\n
03589   *         CMP3xR      CMP3x       LL_HRTIM_TIM_GetCompare3
03590   * @param  HRTIMx High Resolution Timer instance
03591   * @param  Timer This parameter can be one of the following values:
03592   *         @arg @ref LL_HRTIM_TIMER_MASTER
03593   *         @arg @ref LL_HRTIM_TIMER_A
03594   *         @arg @ref LL_HRTIM_TIMER_B
03595   *         @arg @ref LL_HRTIM_TIMER_C
03596   *         @arg @ref LL_HRTIM_TIMER_D
03597   *         @arg @ref LL_HRTIM_TIMER_E
03598   * @retval CompareValue Compare value must be above or equal to 3
03599   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
03600   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
03601   */
03602 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03603 {
03604   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03605   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
03606                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03607   return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R));
03608 }
03609
03610 /**
03611   * @brief  Set the compare value of the compare unit 4.
03612   * @rmtoll MCMP4R      MCMP4       LL_HRTIM_TIM_SetCompare4\n
03613   *         CMP4xR      CMP4x       LL_HRTIM_TIM_SetCompare4
03614   * @param  HRTIMx High Resolution Timer instance
03615   * @param  Timer This parameter can be one of the following values:
03616   *         @arg @ref LL_HRTIM_TIMER_MASTER
03617   *         @arg @ref LL_HRTIM_TIMER_A
03618   *         @arg @ref LL_HRTIM_TIMER_B
03619   *         @arg @ref LL_HRTIM_TIMER_C
03620   *         @arg @ref LL_HRTIM_TIMER_D
03621   *         @arg @ref LL_HRTIM_TIMER_E
03622   * @param  CompareValue Compare value must be above or equal to 3
03623   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
03624   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
03625   * @retval None
03626   */
03627 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
03628 {
03629   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03630   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
03631                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03632   MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue);
03633 }
03634
03635 /**
03636   * @brief  Get actual compare value of the compare unit 4.
03637   * @rmtoll MCMP4R      MCMP4       LL_HRTIM_TIM_GetCompare4\n
03638   *         CMP4xR      CMP4x       LL_HRTIM_TIM_GetCompare4
03639   * @param  HRTIMx High Resolution Timer instance
03640   * @param  Timer This parameter can be one of the following values:
03641   *         @arg @ref LL_HRTIM_TIMER_MASTER
03642   *         @arg @ref LL_HRTIM_TIMER_A
03643   *         @arg @ref LL_HRTIM_TIMER_B
03644   *         @arg @ref LL_HRTIM_TIMER_C
03645   *         @arg @ref LL_HRTIM_TIMER_D
03646   *         @arg @ref LL_HRTIM_TIMER_E
03647   * @retval CompareValue Compare value must be above or equal to 3
03648   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
03649   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
03650   */
03651 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03652 {
03653   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03654   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
03655                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03656   return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R));
03657 }
03658
03659 /**
03660   * @brief  Set the reset trigger of a timer counter.
03661   * @rmtoll RSTxR      UPDT           LL_HRTIM_TIM_SetResetTrig\n
03662   *         RSTxR      CMP2           LL_HRTIM_TIM_SetResetTrig\n
03663   *         RSTxR      CMP4           LL_HRTIM_TIM_SetResetTrig\n
03664   *         RSTxR      MSTPER         LL_HRTIM_TIM_SetResetTrig\n
03665   *         RSTxR      MSTCMP1        LL_HRTIM_TIM_SetResetTrig\n
03666   *         RSTxR      MSTCMP2        LL_HRTIM_TIM_SetResetTrig\n
03667   *         RSTxR      MSTCMP3        LL_HRTIM_TIM_SetResetTrig\n
03668   *         RSTxR      MSTCMP4        LL_HRTIM_TIM_SetResetTrig\n
03669   *         RSTxR      EXTEVNT1       LL_HRTIM_TIM_SetResetTrig\n
03670   *         RSTxR      EXTEVNT2       LL_HRTIM_TIM_SetResetTrig\n
03671   *         RSTxR      EXTEVNT3       LL_HRTIM_TIM_SetResetTrig\n
03672   *         RSTxR      EXTEVNT4       LL_HRTIM_TIM_SetResetTrig\n
03673   *         RSTxR      EXTEVNT5       LL_HRTIM_TIM_SetResetTrig\n
03674   *         RSTxR      EXTEVNT6       LL_HRTIM_TIM_SetResetTrig\n
03675   *         RSTxR      EXTEVNT7       LL_HRTIM_TIM_SetResetTrig\n
03676   *         RSTxR      EXTEVNT8       LL_HRTIM_TIM_SetResetTrig\n
03677   *         RSTxR      EXTEVNT9       LL_HRTIM_TIM_SetResetTrig\n
03678   *         RSTxR      EXTEVNT10      LL_HRTIM_TIM_SetResetTrig\n
03679   *         RSTxR      TIMBCMP1       LL_HRTIM_TIM_SetResetTrig\n
03680   *         RSTxR      TIMBCMP2       LL_HRTIM_TIM_SetResetTrig\n
03681   *         RSTxR      TIMBCMP4       LL_HRTIM_TIM_SetResetTrig\n
03682   *         RSTxR      TIMCCMP1       LL_HRTIM_TIM_SetResetTrig\n
03683   *         RSTxR      TIMCCMP2       LL_HRTIM_TIM_SetResetTrig\n
03684   *         RSTxR      TIMCCMP4       LL_HRTIM_TIM_SetResetTrig\n
03685   *         RSTxR      TIMDCMP1       LL_HRTIM_TIM_SetResetTrig\n
03686   *         RSTxR      TIMDCMP2       LL_HRTIM_TIM_SetResetTrig\n
03687   *         RSTxR      TIMDCMP4       LL_HRTIM_TIM_SetResetTrig\n
03688   *         RSTxR      TIMECMP1       LL_HRTIM_TIM_SetResetTrig\n
03689   *         RSTxR      TIMECMP2       LL_HRTIM_TIM_SetResetTrig\n
03690   *         RSTxR      TIMECMP4       LL_HRTIM_TIM_SetResetTrig
03691   * @note The reset of the timer counter can be triggered by up to 30 events
03692   *       that can be selected among the following sources:
03693   *         @arg The timing unit: Compare 2, Compare 4 and Update (3 events).
03694   *         @arg The master timer: Reset and Compare 1..4 (5 events).
03695   *         @arg The external events EXTEVNT1..10 (10 events).
03696   *         @arg All other timing units (e.g. Timer B..E for timer A): Compare 1, 2 and 4 (12 events).
03697   * @param  HRTIMx High Resolution Timer instance
03698   * @param  Timer This parameter can be one of the following values:
03699   *         @arg @ref LL_HRTIM_TIMER_A
03700   *         @arg @ref LL_HRTIM_TIMER_B
03701   *         @arg @ref LL_HRTIM_TIMER_C
03702   *         @arg @ref LL_HRTIM_TIMER_D
03703   *         @arg @ref LL_HRTIM_TIMER_E
03704   * @param  ResetTrig This parameter can be a combination of the following values:
03705   *         @arg @ref LL_HRTIM_RESETTRIG_NONE
03706   *         @arg @ref LL_HRTIM_RESETTRIG_UPDATE
03707   *         @arg @ref LL_HRTIM_RESETTRIG_CMP2
03708   *         @arg @ref LL_HRTIM_RESETTRIG_CMP4
03709   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
03710   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
03711   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
03712   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
03713   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
03714   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_1
03715   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_2
03716   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_3
03717   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_4
03718   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_5
03719   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_6
03720   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_7
03721   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_8
03722   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_9
03723   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_10
03724   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
03725   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
03726   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
03727   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
03728   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
03729   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
03730   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
03731   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
03732   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
03733   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
03734   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
03735   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
03736   * @retval None
03737   */
03738 __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig)
03739 {
03740   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03741   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
03742                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03743   WRITE_REG(*pReg, ResetTrig);
03744 }
03745
03746 /**
03747   * @brief  Get actual reset trigger of a timer counter.
03748   * @rmtoll RSTxR      UPDT           LL_HRTIM_TIM_GetResetTrig\n
03749   *         RSTxR      CMP2           LL_HRTIM_TIM_GetResetTrig\n
03750   *         RSTxR      CMP4           LL_HRTIM_TIM_GetResetTrig\n
03751   *         RSTxR      MSTPER         LL_HRTIM_TIM_GetResetTrig\n
03752   *         RSTxR      MSTCMP1        LL_HRTIM_TIM_GetResetTrig\n
03753   *         RSTxR      MSTCMP2        LL_HRTIM_TIM_GetResetTrig\n
03754   *         RSTxR      MSTCMP3        LL_HRTIM_TIM_GetResetTrig\n
03755   *         RSTxR      MSTCMP4        LL_HRTIM_TIM_GetResetTrig\n
03756   *         RSTxR      EXTEVNT1       LL_HRTIM_TIM_GetResetTrig\n
03757   *         RSTxR      EXTEVNT2       LL_HRTIM_TIM_GetResetTrig\n
03758   *         RSTxR      EXTEVNT3       LL_HRTIM_TIM_GetResetTrig\n
03759   *         RSTxR      EXTEVNT4       LL_HRTIM_TIM_GetResetTrig\n
03760   *         RSTxR      EXTEVNT5       LL_HRTIM_TIM_GetResetTrig\n
03761   *         RSTxR      EXTEVNT6       LL_HRTIM_TIM_GetResetTrig\n
03762   *         RSTxR      EXTEVNT7       LL_HRTIM_TIM_GetResetTrig\n
03763   *         RSTxR      EXTEVNT8       LL_HRTIM_TIM_GetResetTrig\n
03764   *         RSTxR      EXTEVNT9       LL_HRTIM_TIM_GetResetTrig\n
03765   *         RSTxR      EXTEVNT10      LL_HRTIM_TIM_GetResetTrig\n
03766   *         RSTxR      TIMBCMP1       LL_HRTIM_TIM_GetResetTrig\n
03767   *         RSTxR      TIMBCMP2       LL_HRTIM_TIM_GetResetTrig\n
03768   *         RSTxR      TIMBCMP4       LL_HRTIM_TIM_GetResetTrig\n
03769   *         RSTxR      TIMCCMP1       LL_HRTIM_TIM_GetResetTrig\n
03770   *         RSTxR      TIMCCMP2       LL_HRTIM_TIM_GetResetTrig\n
03771   *         RSTxR      TIMCCMP4       LL_HRTIM_TIM_GetResetTrig\n
03772   *         RSTxR      TIMDCMP1       LL_HRTIM_TIM_GetResetTrig\n
03773   *         RSTxR      TIMDCMP2       LL_HRTIM_TIM_GetResetTrig\n
03774   *         RSTxR      TIMDCMP4       LL_HRTIM_TIM_GetResetTrig\n
03775   *         RSTxR      TIMECMP1       LL_HRTIM_TIM_GetResetTrig\n
03776   *         RSTxR      TIMECMP2       LL_HRTIM_TIM_GetResetTrig\n
03777   *         RSTxR      TIMECMP4       LL_HRTIM_TIM_GetResetTrig
03778   * @param  HRTIMx High Resolution Timer instance
03779   * @param  Timer This parameter can be one of the following values:
03780   *         @arg @ref LL_HRTIM_TIMER_A
03781   *         @arg @ref LL_HRTIM_TIMER_B
03782   *         @arg @ref LL_HRTIM_TIMER_C
03783   *         @arg @ref LL_HRTIM_TIMER_D
03784   *         @arg @ref LL_HRTIM_TIMER_E
03785   * @retval ResetTrig Returned value can be one of the following values:
03786   *         @arg @ref LL_HRTIM_RESETTRIG_NONE
03787   *         @arg @ref LL_HRTIM_RESETTRIG_UPDATE
03788   *         @arg @ref LL_HRTIM_RESETTRIG_CMP2
03789   *         @arg @ref LL_HRTIM_RESETTRIG_CMP4
03790   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
03791   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
03792   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
03793   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
03794   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
03795   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_1
03796   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_2
03797   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_3
03798   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_4
03799   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_5
03800   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_6
03801   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_7
03802   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_8
03803   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_9
03804   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_10
03805   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
03806   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
03807   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
03808   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
03809   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
03810   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
03811   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
03812   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
03813   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
03814   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
03815   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
03816   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
03817   */
03818 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03819 {
03820   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03821   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
03822                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03823   return (READ_REG(*pReg));
03824 }
03825
03826 /**
03827   * @brief  Get captured value for capture unit 1.
03828   * @rmtoll CPT1xR      CPT1x           LL_HRTIM_TIM_GetCapture1
03829   * @param  HRTIMx High Resolution Timer instance
03830   * @param  Timer This parameter can be one of the following values:
03831   *         @arg @ref LL_HRTIM_TIMER_A
03832   *         @arg @ref LL_HRTIM_TIMER_B
03833   *         @arg @ref LL_HRTIM_TIMER_C
03834   *         @arg @ref LL_HRTIM_TIMER_D
03835   *         @arg @ref LL_HRTIM_TIMER_E
03836   * @retval Captured value
03837   */
03838 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03839 {
03840   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03841   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
03842                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03843   return (READ_REG(*pReg));
03844 }
03845
03846 /**
03847   * @brief  Get captured value for capture unit 2.
03848   * @rmtoll CPT2xR      CPT2x           LL_HRTIM_TIM_GetCapture2
03849   * @param  HRTIMx High Resolution Timer instance
03850   * @param  Timer This parameter can be one of the following values:
03851   *         @arg @ref LL_HRTIM_TIMER_A
03852   *         @arg @ref LL_HRTIM_TIMER_B
03853   *         @arg @ref LL_HRTIM_TIMER_C
03854   *         @arg @ref LL_HRTIM_TIMER_D
03855   *         @arg @ref LL_HRTIM_TIMER_E
03856   * @retval Captured value
03857   */
03858 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03859 {
03860   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03861   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
03862                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03863   return (READ_REG(*pReg));
03864 }
03865
03866 /**
03867   * @brief  Set the trigger of a capture unit for a given timer.
03868   * @rmtoll CPT1xCR      SWCPT            LL_HRTIM_TIM_SetCaptureTrig\n
03869   *         CPT1xCR      UPDCPT           LL_HRTIM_TIM_SetCaptureTrig\n
03870   *         CPT1xCR      EXEV1CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03871   *         CPT1xCR      EXEV2CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03872   *         CPT1xCR      EXEV3CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03873   *         CPT1xCR      EXEV4CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03874   *         CPT1xCR      EXEV5CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03875   *         CPT1xCR      EXEV6CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03876   *         CPT1xCR      EXEV7CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03877   *         CPT1xCR      EXEV8CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03878   *         CPT1xCR      EXEV9CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03879   *         CPT1xCR      EXEV10CPT        LL_HRTIM_TIM_SetCaptureTrig\n
03880   *         CPT1xCR      TA1SET           LL_HRTIM_TIM_SetCaptureTrig\n
03881   *         CPT1xCR      TA1RST           LL_HRTIM_TIM_SetCaptureTrig\n
03882   *         CPT1xCR      TACMP1           LL_HRTIM_TIM_SetCaptureTrig\n
03883   *         CPT1xCR      TACMP2           LL_HRTIM_TIM_SetCaptureTrig\n
03884   *         CPT1xCR      TB1SET           LL_HRTIM_TIM_SetCaptureTrig\n
03885   *         CPT1xCR      TB1RST           LL_HRTIM_TIM_SetCaptureTrig\n
03886   *         CPT1xCR      TBCMP1           LL_HRTIM_TIM_SetCaptureTrig\n
03887   *         CPT1xCR      TBCMP2           LL_HRTIM_TIM_SetCaptureTrig\n
03888   *         CPT1xCR      TC1SET           LL_HRTIM_TIM_SetCaptureTrig\n
03889   *         CPT1xCR      TC1RST           LL_HRTIM_TIM_SetCaptureTrig\n
03890   *         CPT1xCR      TCCMP1           LL_HRTIM_TIM_SetCaptureTrig\n
03891   *         CPT1xCR      TCCMP2           LL_HRTIM_TIM_SetCaptureTrig\n
03892   *         CPT1xCR      TD1SET           LL_HRTIM_TIM_SetCaptureTrig\n
03893   *         CPT1xCR      TD1RST           LL_HRTIM_TIM_SetCaptureTrig\n
03894   *         CPT1xCR      TDCMP1           LL_HRTIM_TIM_SetCaptureTrig\n
03895   *         CPT1xCR      TDCMP2           LL_HRTIM_TIM_SetCaptureTrig\n
03896   *         CPT1xCR      TE1SET           LL_HRTIM_TIM_SetCaptureTrig\n
03897   *         CPT1xCR      TE1RST           LL_HRTIM_TIM_SetCaptureTrig\n
03898   *         CPT1xCR      TECMP1           LL_HRTIM_TIM_SetCaptureTrig\n
03899   *         CPT1xCR      TECMP2           LL_HRTIM_TIM_SetCaptureTrig
03900   * @param  HRTIMx High Resolution Timer instance
03901   * @param  Timer This parameter can be one of the following values:
03902   *         @arg @ref LL_HRTIM_TIMER_A
03903   *         @arg @ref LL_HRTIM_TIMER_B
03904   *         @arg @ref LL_HRTIM_TIMER_C
03905   *         @arg @ref LL_HRTIM_TIMER_D
03906   *         @arg @ref LL_HRTIM_TIMER_E
03907   * @param  CaptureUnit This parameter can be one of the following values:
03908   *         @arg @ref LL_HRTIM_CAPTUREUNIT_1
03909   *         @arg @ref LL_HRTIM_CAPTUREUNIT_2
03910   * @param  CaptureTrig This parameter can be a combination of the following values:
03911   *         @arg @ref LL_HRTIM_CAPTURETRIG_NONE
03912   *         @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
03913   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
03914   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
03915   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
03916   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
03917   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
03918   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
03919   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
03920   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
03921   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
03922   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
03923   *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
03924   *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
03925   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
03926   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
03927   *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
03928   *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
03929   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
03930   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
03931   *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
03932   *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
03933   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
03934   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
03935   *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
03936   *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
03937   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
03938   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
03939   *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
03940   *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
03941   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
03942   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
03943   * @retval None
03944   */
03945 __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit,
03946                                                  uint32_t CaptureTrig)
03947 {
03948   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03949   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xCR) +
03950                                                     REG_OFFSET_TAB_TIMER[iTimer] + CaptureUnit * 4));
03951   WRITE_REG(*pReg, CaptureTrig);
03952 }
03953
03954 /**
03955   * @brief  Get actual trigger of a capture unit for a given timer.
03956   * @rmtoll CPT1xCR      SWCPT            LL_HRTIM_TIM_GetCaptureTrig\n
03957   *         CPT1xCR      UPDCPT           LL_HRTIM_TIM_GetCaptureTrig\n
03958   *         CPT1xCR      EXEV1CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03959   *         CPT1xCR      EXEV2CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03960   *         CPT1xCR      EXEV3CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03961   *         CPT1xCR      EXEV4CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03962   *         CPT1xCR      EXEV5CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03963   *         CPT1xCR      EXEV6CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03964   *         CPT1xCR      EXEV7CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03965   *         CPT1xCR      EXEV8CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03966   *         CPT1xCR      EXEV9CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03967   *         CPT1xCR      EXEV10CPT        LL_HRTIM_TIM_GetCaptureTrig\n
03968   *         CPT1xCR      TA1SET           LL_HRTIM_TIM_GetCaptureTrig\n
03969   *         CPT1xCR      TA1RST           LL_HRTIM_TIM_GetCaptureTrig\n
03970   *         CPT1xCR      TACMP1           LL_HRTIM_TIM_GetCaptureTrig\n
03971   *         CPT1xCR      TACMP2           LL_HRTIM_TIM_GetCaptureTrig\n
03972   *         CPT1xCR      TB1SET           LL_HRTIM_TIM_GetCaptureTrig\n
03973   *         CPT1xCR      TB1RST           LL_HRTIM_TIM_GetCaptureTrig\n
03974   *         CPT1xCR      TBCMP1           LL_HRTIM_TIM_GetCaptureTrig\n
03975   *         CPT1xCR      TBCMP2           LL_HRTIM_TIM_GetCaptureTrig\n
03976   *         CPT1xCR      TC1SET           LL_HRTIM_TIM_GetCaptureTrig\n
03977   *         CPT1xCR      TC1RST           LL_HRTIM_TIM_GetCaptureTrig\n
03978   *         CPT1xCR      TCCMP1           LL_HRTIM_TIM_GetCaptureTrig\n
03979   *         CPT1xCR      TCCMP2           LL_HRTIM_TIM_GetCaptureTrig\n
03980   *         CPT1xCR      TD1SET           LL_HRTIM_TIM_GetCaptureTrig\n
03981   *         CPT1xCR      TD1RST           LL_HRTIM_TIM_GetCaptureTrig\n
03982   *         CPT1xCR      TDCMP1           LL_HRTIM_TIM_GetCaptureTrig\n
03983   *         CPT1xCR      TDCMP2           LL_HRTIM_TIM_GetCaptureTrig\n
03984   *         CPT1xCR      TE1SET           LL_HRTIM_TIM_GetCaptureTrig\n
03985   *         CPT1xCR      TE1RST           LL_HRTIM_TIM_GetCaptureTrig\n
03986   *         CPT1xCR      TECMP1           LL_HRTIM_TIM_GetCaptureTrig\n
03987   *         CPT1xCR      TECMP2           LL_HRTIM_TIM_GetCaptureTrig
03988   * @param  HRTIMx High Resolution Timer instance
03989   * @param  Timer This parameter can be one of the following values:
03990   *         @arg @ref LL_HRTIM_TIMER_A
03991   *         @arg @ref LL_HRTIM_TIMER_B
03992   *         @arg @ref LL_HRTIM_TIMER_C
03993   *         @arg @ref LL_HRTIM_TIMER_D
03994   *         @arg @ref LL_HRTIM_TIMER_E
03995   * @param  CaptureUnit This parameter can be one of the following values:
03996   *         @arg @ref LL_HRTIM_CAPTUREUNIT_1
03997   *         @arg @ref LL_HRTIM_CAPTUREUNIT_2
03998   * @retval CaptureTrig This parameter can be a combination of the following values:
03999   *         @arg @ref LL_HRTIM_CAPTURETRIG_NONE
04000   *         @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
04001   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
04002   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
04003   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
04004   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
04005   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
04006   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
04007   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
04008   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
04009   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
04010   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
04011   *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
04012   *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
04013   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
04014   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
04015   *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
04016   *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
04017   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
04018   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
04019   *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
04020   *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
04021   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
04022   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
04023   *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
04024   *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
04025   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
04026   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
04027   *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
04028   *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
04029   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
04030   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
04031   */
04032 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
04033 {
04034   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04035   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xCR) +
04036                                                     REG_OFFSET_TAB_TIMER[iTimer] + CaptureUnit * 4));
04037   return (READ_REG(*pReg));
04038 }
04039
04040 /**
04041   * @brief  Enable deadtime insertion for a given timer.
04042   * @rmtoll OUTxR      DTEN           LL_HRTIM_TIM_EnableDeadTime
04043   * @param  HRTIMx High Resolution Timer instance
04044   * @param  Timer This parameter can be one of the following values:
04045   *         @arg @ref LL_HRTIM_TIMER_A
04046   *         @arg @ref LL_HRTIM_TIMER_B
04047   *         @arg @ref LL_HRTIM_TIMER_C
04048   *         @arg @ref LL_HRTIM_TIMER_D
04049   *         @arg @ref LL_HRTIM_TIMER_E
04050   * @retval None
04051   */
04052 __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04053 {
04054   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04055   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
04056                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04057   SET_BIT(*pReg, HRTIM_OUTR_DTEN);
04058 }
04059
04060 /**
04061   * @brief  Disable deadtime insertion for a given timer.
04062   * @rmtoll OUTxR      DTEN           LL_HRTIM_TIM_DisableDeadTime
04063   * @param  HRTIMx High Resolution Timer instance
04064   * @param  Timer This parameter can be one of the following values:
04065   *         @arg @ref LL_HRTIM_TIMER_A
04066   *         @arg @ref LL_HRTIM_TIMER_B
04067   *         @arg @ref LL_HRTIM_TIMER_C
04068   *         @arg @ref LL_HRTIM_TIMER_D
04069   *         @arg @ref LL_HRTIM_TIMER_E
04070   * @retval None
04071   */
04072 __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04073 {
04074   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04075   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
04076                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04077   CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN);
04078 }
04079
04080 /**
04081   * @brief  Indicate whether deadtime insertion is enabled for a given timer.
04082   * @rmtoll OUTxR      DTEN           LL_HRTIM_TIM_IsEnabledDeadTime
04083   * @param  HRTIMx High Resolution Timer instance
04084   * @param  Timer This parameter can be one of the following values:
04085   *         @arg @ref LL_HRTIM_TIMER_A
04086   *         @arg @ref LL_HRTIM_TIMER_B
04087   *         @arg @ref LL_HRTIM_TIMER_C
04088   *         @arg @ref LL_HRTIM_TIMER_D
04089   *         @arg @ref LL_HRTIM_TIMER_E
04090   * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0).
04091   */
04092 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04093 {
04094   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04095   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
04096                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04097   return (READ_BIT(*pReg, HRTIM_OUTR_DTEN) == HRTIM_OUTR_DTEN);
04098 }
04099
04100 /**
04101   * @brief  Set the delayed protection (DLYPRT) mode.
04102   * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_SetDLYPRTMode\n
04103   *         OUTxR      DLYPRT         LL_HRTIM_TIM_SetDLYPRTMode
04104   * @note   This function must be called prior enabling the delayed protection
04105   * @note   Balanced Idle mode is only available in push-pull mode
04106   * @param  HRTIMx High Resolution Timer instance
04107   * @param  Timer This parameter can be one of the following values:
04108   *         @arg @ref LL_HRTIM_TIMER_A
04109   *         @arg @ref LL_HRTIM_TIMER_B
04110   *         @arg @ref LL_HRTIM_TIMER_C
04111   *         @arg @ref LL_HRTIM_TIMER_D
04112   *         @arg @ref LL_HRTIM_TIMER_E
04113   * @param  DLYPRTMode Delayed protection (DLYPRT) mode
04114   *
04115   *         For timers A, B and C this parameter can be one of the following vallues:
04116   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
04117   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
04118   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
04119   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
04120   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
04121   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
04122   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
04123   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
04124   *
04125   *         For timers D and E this parameter can be one of the following vallues:
04126   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
04127   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
04128   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
04129   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
04130   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
04131   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
04132   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
04133   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
04134   * @retval None
04135   */
04136 __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode)
04137 {
04138   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04139   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
04140                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04141   MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode);
04142 }
04143
04144 /**
04145   * @brief  Get the delayed protection (DLYPRT) mode.
04146   * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_GetDLYPRTMode\n
04147   *         OUTxR      DLYPRT         LL_HRTIM_TIM_GetDLYPRTMode
04148   * @param  HRTIMx High Resolution Timer instance
04149   * @param  Timer This parameter can be one of the following values:
04150   *         @arg @ref LL_HRTIM_TIMER_A
04151   *         @arg @ref LL_HRTIM_TIMER_B
04152   *         @arg @ref LL_HRTIM_TIMER_C
04153   *         @arg @ref LL_HRTIM_TIMER_D
04154   *         @arg @ref LL_HRTIM_TIMER_E
04155   * @retval DLYPRTMode Delayed protection (DLYPRT) mode
04156   *
04157   *         For timers A, B and C this parameter can be one of the following vallues:
04158   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
04159   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
04160   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
04161   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
04162   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
04163   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
04164   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
04165   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
04166   *
04167   *         For timers D and E this parameter can be one of the following vallues:
04168   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
04169   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
04170   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
04171   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
04172   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
04173   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
04174   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
04175   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
04176   */
04177 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04178 {
04179   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04180   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
04181                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04182   return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT));
04183 }
04184
04185 /**
04186   * @brief  Enable delayed protection (DLYPRT) for a given timer.
04187   * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_EnableDLYPRT
04188   * @note   This function must not be called once the concerned timer is enabled
04189   * @param  HRTIMx High Resolution Timer instance
04190   * @param  Timer This parameter can be one of the following values:
04191   *         @arg @ref LL_HRTIM_TIMER_A
04192   *         @arg @ref LL_HRTIM_TIMER_B
04193   *         @arg @ref LL_HRTIM_TIMER_C
04194   *         @arg @ref LL_HRTIM_TIMER_D
04195   *         @arg @ref LL_HRTIM_TIMER_E
04196   * @retval None
04197   */
04198 __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04199 {
04200   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04201   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
04202                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04203   SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
04204 }
04205
04206 /**
04207   * @brief  Disable delayed protection (DLYPRT) for a given timer.
04208   * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_DisableDLYPRT
04209   * @note   This function must not be called once the concerned timer is enabled
04210   * @param  HRTIMx High Resolution Timer instance
04211   * @param  Timer This parameter can be one of the following values:
04212   *         @arg @ref LL_HRTIM_TIMER_A
04213   *         @arg @ref LL_HRTIM_TIMER_B
04214   *         @arg @ref LL_HRTIM_TIMER_C
04215   *         @arg @ref LL_HRTIM_TIMER_D
04216   *         @arg @ref LL_HRTIM_TIMER_E
04217   * @retval None
04218   */
04219 __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04220 {
04221   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04222   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
04223                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04224   CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
04225 }
04226
04227 /**
04228   * @brief  Indicate whether delayed protection (DLYPRT) is enabled for a given timer.
04229   * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_IsEnabledDLYPRT
04230   * @param  HRTIMx High Resolution Timer instance
04231   * @param  Timer This parameter can be one of the following values:
04232   *         @arg @ref LL_HRTIM_TIMER_A
04233   *         @arg @ref LL_HRTIM_TIMER_B
04234   *         @arg @ref LL_HRTIM_TIMER_C
04235   *         @arg @ref LL_HRTIM_TIMER_D
04236   *         @arg @ref LL_HRTIM_TIMER_E
04237   * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
04238   */
04239 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04240 {
04241   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04242   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
04243                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04244   return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == HRTIM_OUTR_DLYPRTEN);
04245 }
04246
04247 /**
04248   * @brief  Enable the fault channel(s) for a given timer.
04249   * @rmtoll FLTxR      FLT1EN       LL_HRTIM_TIM_EnableFault\n
04250   *         FLTxR      FLT2EN       LL_HRTIM_TIM_EnableFault\n
04251   *         FLTxR      FLT3EN       LL_HRTIM_TIM_EnableFault\n
04252   *         FLTxR      FLT4EN       LL_HRTIM_TIM_EnableFault\n
04253   *         FLTxR      FLT5EN       LL_HRTIM_TIM_EnableFault
04254   * @param  HRTIMx High Resolution Timer instance
04255   * @param  Timer This parameter can be one of the following values:
04256   *         @arg @ref LL_HRTIM_TIMER_A
04257   *         @arg @ref LL_HRTIM_TIMER_B
04258   *         @arg @ref LL_HRTIM_TIMER_C
04259   *         @arg @ref LL_HRTIM_TIMER_D
04260   *         @arg @ref LL_HRTIM_TIMER_E
04261   * @param  Faults This parameter can be a combination of the following values:
04262   *         @arg @ref LL_HRTIM_FAULT_1
04263   *         @arg @ref LL_HRTIM_FAULT_2
04264   *         @arg @ref LL_HRTIM_FAULT_3
04265   *         @arg @ref LL_HRTIM_FAULT_4
04266   *         @arg @ref LL_HRTIM_FAULT_5
04267   * @retval None
04268   */
04269 __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
04270 {
04271   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04272   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
04273                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04274   SET_BIT(*pReg, Faults);
04275 }
04276
04277 /**
04278   * @brief  Disable the fault channel(s) for a given timer.
04279   * @rmtoll FLTxR      FLT1EN       LL_HRTIM_TIM_DisableFault\n
04280   *         FLTxR      FLT2EN       LL_HRTIM_TIM_DisableFault\n
04281   *         FLTxR      FLT3EN       LL_HRTIM_TIM_DisableFault\n
04282   *         FLTxR      FLT4EN       LL_HRTIM_TIM_DisableFault\n
04283   *         FLTxR      FLT5EN       LL_HRTIM_TIM_DisableFault
04284   * @param  HRTIMx High Resolution Timer instance
04285   * @param  Timer This parameter can be one of the following values:
04286   *         @arg @ref LL_HRTIM_TIMER_A
04287   *         @arg @ref LL_HRTIM_TIMER_B
04288   *         @arg @ref LL_HRTIM_TIMER_C
04289   *         @arg @ref LL_HRTIM_TIMER_D
04290   *         @arg @ref LL_HRTIM_TIMER_E
04291   * @param  Faults This parameter can be a combination of the following values:
04292   *         @arg @ref LL_HRTIM_FAULT_1
04293   *         @arg @ref LL_HRTIM_FAULT_2
04294   *         @arg @ref LL_HRTIM_FAULT_3
04295   *         @arg @ref LL_HRTIM_FAULT_4
04296   *         @arg @ref LL_HRTIM_FAULT_5
04297   * @retval None
04298   */
04299 __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
04300 {
04301   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04302   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
04303                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04304   CLEAR_BIT(*pReg, Faults);
04305 }
04306
04307 /**
04308   * @brief  Indicate whether the fault channel is enabled for a given timer.
04309   * @rmtoll FLTxR      FLT1EN       LL_HRTIM_TIM_IsEnabledFault\n
04310   *         FLTxR      FLT2EN       LL_HRTIM_TIM_IsEnabledFault\n
04311   *         FLTxR      FLT3EN       LL_HRTIM_TIM_IsEnabledFault\n
04312   *         FLTxR      FLT4EN       LL_HRTIM_TIM_IsEnabledFault\n
04313   *         FLTxR      FLT5EN       LL_HRTIM_TIM_IsEnabledFault
04314   * @param  HRTIMx High Resolution Timer instance
04315   * @param  Timer This parameter can be one of the following values:
04316   *         @arg @ref LL_HRTIM_TIMER_A
04317   *         @arg @ref LL_HRTIM_TIMER_B
04318   *         @arg @ref LL_HRTIM_TIMER_C
04319   *         @arg @ref LL_HRTIM_TIMER_D
04320   *         @arg @ref LL_HRTIM_TIMER_E
04321   * @param  Fault This parameter can be one of the following values:
04322   *         @arg @ref LL_HRTIM_FAULT_1
04323   *         @arg @ref LL_HRTIM_FAULT_2
04324   *         @arg @ref LL_HRTIM_FAULT_3
04325   *         @arg @ref LL_HRTIM_FAULT_4
04326   *         @arg @ref LL_HRTIM_FAULT_5
04327   * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0).
04328   */
04329 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
04330 {
04331   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04332   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
04333                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04334   return (READ_BIT(*pReg, Fault) == (Fault));
04335 }
04336
04337 /**
04338   * @brief  Lock the fault conditioning set-up for a given timer.
04339   * @rmtoll FLTxR      FLTLCK       LL_HRTIM_TIM_LockFault
04340   * @note Timer fault-related set-up is frozen until the next HRTIM or system reset
04341   * @param  HRTIMx High Resolution Timer instance
04342   * @param  Timer This parameter can be one of the following values:
04343   *         @arg @ref LL_HRTIM_TIMER_A
04344   *         @arg @ref LL_HRTIM_TIMER_B
04345   *         @arg @ref LL_HRTIM_TIMER_C
04346   *         @arg @ref LL_HRTIM_TIMER_D
04347   *         @arg @ref LL_HRTIM_TIMER_E
04348   * @retval None
04349   */
04350 __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04351 {
04352   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04353   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
04354                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04355   SET_BIT(*pReg, HRTIM_FLTR_FLTLCK);
04356 }
04357
04358 /**
04359   * @brief  Define how the timer behaves during a burst mode operation.
04360   * @rmtoll BMCR      MTBM       LL_HRTIM_TIM_SetBurstModeOption\n
04361   *         BMCR      TABM       LL_HRTIM_TIM_SetBurstModeOption\n
04362   *         BMCR      TBBM       LL_HRTIM_TIM_SetBurstModeOption\n
04363   *         BMCR      TCBM       LL_HRTIM_TIM_SetBurstModeOption\n
04364   *         BMCR      TDBM       LL_HRTIM_TIM_SetBurstModeOption\n
04365   *         BMCR      TEBM       LL_HRTIM_TIM_SetBurstModeOption
04366   * @note This function must not be called when the burst mode is enabled
04367   * @param  HRTIMx High Resolution Timer instance
04368   * @param  Timer This parameter can be one of the following values:
04369   *         @arg @ref LL_HRTIM_TIMER_MASTER
04370   *         @arg @ref LL_HRTIM_TIMER_A
04371   *         @arg @ref LL_HRTIM_TIMER_B
04372   *         @arg @ref LL_HRTIM_TIMER_C
04373   *         @arg @ref LL_HRTIM_TIMER_D
04374   *         @arg @ref LL_HRTIM_TIMER_E
04375   * @param  BurtsModeOption This parameter can be one of the following values:
04376   *         @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
04377   *         @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
04378   * @retval None
04379   */
04380 __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption)
04381 {
04382   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04383   MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer);
04384 }
04385
04386 /**
04387   * @brief  Retrieve how the timer behaves during a burst mode operation.
04388   * @rmtoll BMCR      MCR        LL_HRTIM_TIM_GetBurstModeOption\n
04389   *         BMCR      TABM       LL_HRTIM_TIM_GetBurstModeOption\n
04390   *         BMCR      TBBM       LL_HRTIM_TIM_GetBurstModeOption\n
04391   *         BMCR      TCBM       LL_HRTIM_TIM_GetBurstModeOption\n
04392   *         BMCR      TDBM       LL_HRTIM_TIM_GetBurstModeOption\n
04393   *         BMCR      TEBM       LL_HRTIM_TIM_GetBurstModeOption
04394   * @param  HRTIMx High Resolution Timer instance
04395   * @param  Timer This parameter can be one of the following values:
04396   *         @arg @ref LL_HRTIM_TIMER_MASTER
04397   *         @arg @ref LL_HRTIM_TIMER_A
04398   *         @arg @ref LL_HRTIM_TIMER_B
04399   *         @arg @ref LL_HRTIM_TIMER_C
04400   *         @arg @ref LL_HRTIM_TIMER_D
04401   *         @arg @ref LL_HRTIM_TIMER_E
04402   * @retval BurtsMode This parameter can be one of the following values:
04403   *         @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
04404   *         @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
04405   */
04406 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04407 {
04408   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04409   return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer);
04410 }
04411
04412 /**
04413   * @brief  Program which registers are to be written by Burst DMA transfers.
04414   * @rmtoll BDMUPDR      MTBM        LL_HRTIM_TIM_ConfigBurstDMA\n
04415   *         BDMUPDR      MICR        LL_HRTIM_TIM_ConfigBurstDMA\n
04416   *         BDMUPDR      MDIER       LL_HRTIM_TIM_ConfigBurstDMA\n
04417   *         BDMUPDR      MCNT        LL_HRTIM_TIM_ConfigBurstDMA\n
04418   *         BDMUPDR      MPER        LL_HRTIM_TIM_ConfigBurstDMA\n
04419   *         BDMUPDR      MREP        LL_HRTIM_TIM_ConfigBurstDMA\n
04420   *         BDMUPDR      MCMP1       LL_HRTIM_TIM_ConfigBurstDMA\n
04421   *         BDMUPDR      MCMP2       LL_HRTIM_TIM_ConfigBurstDMA\n
04422   *         BDMUPDR      MCMP3       LL_HRTIM_TIM_ConfigBurstDMA\n
04423   *         BDMUPDR      MCMP4       LL_HRTIM_TIM_ConfigBurstDMA\n
04424   *         BDTxUPDR     TIMxCR      LL_HRTIM_TIM_ConfigBurstDMA\n
04425   *         BDTxUPDR     TIMxICR     LL_HRTIM_TIM_ConfigBurstDMA\n
04426   *         BDTxUPDR     TIMxDIER    LL_HRTIM_TIM_ConfigBurstDMA\n
04427   *         BDTxUPDR     TIMxCNT     LL_HRTIM_TIM_ConfigBurstDMA\n
04428   *         BDTxUPDR     TIMxPER     LL_HRTIM_TIM_ConfigBurstDMA\n
04429   *         BDTxUPDR     TIMxREP     LL_HRTIM_TIM_ConfigBurstDMA\n
04430   *         BDTxUPDR     TIMxCMP1    LL_HRTIM_TIM_ConfigBurstDMA\n
04431   *         BDTxUPDR     TIMxCMP2    LL_HRTIM_TIM_ConfigBurstDMA\n
04432   *         BDTxUPDR     TIMxCMP3    LL_HRTIM_TIM_ConfigBurstDMA\n
04433   *         BDTxUPDR     TIMxCMP4    LL_HRTIM_TIM_ConfigBurstDMA\n
04434   *         BDTxUPDR     TIMxDTR     LL_HRTIM_TIM_ConfigBurstDMA\n
04435   *         BDTxUPDR     TIMxSET1R   LL_HRTIM_TIM_ConfigBurstDMA\n
04436   *         BDTxUPDR     TIMxRST1R   LL_HRTIM_TIM_ConfigBurstDMA\n
04437   *         BDTxUPDR     TIMxSET2R   LL_HRTIM_TIM_ConfigBurstDMA\n
04438   *         BDTxUPDR     TIMxRST2R   LL_HRTIM_TIM_ConfigBurstDMA\n
04439   *         BDTxUPDR     TIAEEFR1    LL_HRTIM_TIM_ConfigBurstDMA\n
04440   *         BDTxUPDR     TIMxEEFR2   LL_HRTIM_TIM_ConfigBurstDMA\n
04441   *         BDTxUPDR     TIMxRSTR    LL_HRTIM_TIM_ConfigBurstDMA\n
04442   *         BDTxUPDR     TIMxOUTR    LL_HRTIM_TIM_ConfigBurstDMA\n
04443   *         BDTxUPDR     TIMxLTCH    LL_HRTIM_TIM_ConfigBurstDMA
04444   * @param  HRTIMx High Resolution Timer instance
04445   * @param  Timer This parameter can be one of the following values:
04446   *         @arg @ref LL_HRTIM_TIMER_MASTER
04447   *         @arg @ref LL_HRTIM_TIMER_A
04448   *         @arg @ref LL_HRTIM_TIMER_B
04449   *         @arg @ref LL_HRTIM_TIMER_C
04450   *         @arg @ref LL_HRTIM_TIMER_D
04451   *         @arg @ref LL_HRTIM_TIMER_E
04452   * @param  Registers Registers to be updated by the DMA request
04453   *
04454   *         For Master timer this parameter can be can be a combination of the following values:
04455   *         @arg @ref LL_HRTIM_BURSTDMA_NONE
04456   *         @arg @ref LL_HRTIM_BURSTDMA_MCR
04457   *         @arg @ref LL_HRTIM_BURSTDMA_MICR
04458   *         @arg @ref LL_HRTIM_BURSTDMA_MDIER
04459   *         @arg @ref LL_HRTIM_BURSTDMA_MCNT
04460   *         @arg @ref LL_HRTIM_BURSTDMA_MPER
04461   *         @arg @ref LL_HRTIM_BURSTDMA_MREP
04462   *         @arg @ref LL_HRTIM_BURSTDMA_MCMP1
04463   *         @arg @ref LL_HRTIM_BURSTDMA_MCMP2
04464   *         @arg @ref LL_HRTIM_BURSTDMA_MCMP3
04465   *         @arg @ref LL_HRTIM_BURSTDMA_MCMP4
04466   *
04467   *         For Timers A..E this parameter can be can be a combination of the following values:
04468   *         @arg @ref LL_HRTIM_BURSTDMA_NONE
04469   *         @arg @ref LL_HRTIM_BURSTDMA_TIMMCR
04470   *         @arg @ref LL_HRTIM_BURSTDMA_TIMICR
04471   *         @arg @ref LL_HRTIM_BURSTDMA_TIMDIER
04472   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCNT
04473   *         @arg @ref LL_HRTIM_BURSTDMA_TIMPER
04474   *         @arg @ref LL_HRTIM_BURSTDMA_TIMREP
04475   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1
04476   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2
04477   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3
04478   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4
04479   *         @arg @ref LL_HRTIM_BURSTDMA_TIMDTR
04480   *         @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R
04481   *         @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R
04482   *         @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R
04483   *         @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R
04484   *         @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1
04485   *         @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2
04486   *         @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR
04487   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR
04488   *         @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR
04489   *         @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR
04490   * @retval None
04491   */
04492 __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers)
04493 {
04494   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04495   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + 4 * iTimer));
04496   WRITE_REG(*pReg, Registers);
04497 }
04498
04499 /**
04500   * @brief  Indicate on which output the signal is currently applied.
04501   * @rmtoll TIMxISR      CPPSTAT        LL_HRTIM_TIM_GetCurrentPushPullStatus
04502   * @note Only significant when the timer operates in push-pull mode.
04503   * @param  HRTIMx High Resolution Timer instance
04504   * @param  Timer This parameter can be one of the following values:
04505   *         @arg @ref LL_HRTIM_TIMER_A
04506   *         @arg @ref LL_HRTIM_TIMER_B
04507   *         @arg @ref LL_HRTIM_TIMER_C
04508   *         @arg @ref LL_HRTIM_TIMER_D
04509   *         @arg @ref LL_HRTIM_TIMER_E
04510   * @retval CPPSTAT This parameter can be one of the following values:
04511   *         @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1
04512   *         @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2
04513   */
04514 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04515 {
04516   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04517   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
04518                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04519   return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT));
04520 }
04521
04522 /**
04523   * @brief  Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.
04524   * @rmtoll TIMxISR      IPPSTAT        LL_HRTIM_TIM_GetIdlePushPullStatus
04525   * @param  HRTIMx High Resolution Timer instance
04526   * @param  Timer This parameter can be one of the following values:
04527   *         @arg @ref LL_HRTIM_TIMER_A
04528   *         @arg @ref LL_HRTIM_TIMER_B
04529   *         @arg @ref LL_HRTIM_TIMER_C
04530   *         @arg @ref LL_HRTIM_TIMER_D
04531   *         @arg @ref LL_HRTIM_TIMER_E
04532   * @retval IPPSTAT This parameter can be one of the following values:
04533   *         @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1
04534   *         @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2
04535   */
04536 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04537 {
04538   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04539   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
04540                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04541   return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT));
04542 }
04543
04544 /**
04545   * @brief  Set the event filter for a given timer.
04546   * @rmtoll EEFxR1      EE1LTCH        LL_HRTIM_TIM_SetEventFilter\n
04547   *         EEFxR1      EE2LTCH        LL_HRTIM_TIM_SetEventFilter\n
04548   *         EEFxR1      EE3LTCH        LL_HRTIM_TIM_SetEventFilter\n
04549   *         EEFxR1      EE4LTCH        LL_HRTIM_TIM_SetEventFilter\n
04550   *         EEFxR1      EE5LTCH        LL_HRTIM_TIM_SetEventFilter\n
04551   *         EEFxR2      EE6LTCH        LL_HRTIM_TIM_SetEventFilter\n
04552   *         EEFxR2      EE7LTCH        LL_HRTIM_TIM_SetEventFilter\n
04553   *         EEFxR2      EE8LTCH        LL_HRTIM_TIM_SetEventFilter\n
04554   *         EEFxR2      EE9LTCH        LL_HRTIM_TIM_SetEventFilter\n
04555   *         EEFxR2      EE10LTCH       LL_HRTIM_TIM_SetEventFilter
04556   * @note This function must not be called when the timer counter is enabled.
04557   * @param  HRTIMx High Resolution Timer instance
04558   * @param  Timer This parameter can be one of the following values:
04559   *         @arg @ref LL_HRTIM_TIMER_A
04560   *         @arg @ref LL_HRTIM_TIMER_B
04561   *         @arg @ref LL_HRTIM_TIMER_C
04562   *         @arg @ref LL_HRTIM_TIMER_D
04563   *         @arg @ref LL_HRTIM_TIMER_E
04564   * @param  Event This parameter can be one of the following values:
04565   *         @arg @ref LL_HRTIM_EVENT_1
04566   *         @arg @ref LL_HRTIM_EVENT_2
04567   *         @arg @ref LL_HRTIM_EVENT_3
04568   *         @arg @ref LL_HRTIM_EVENT_4
04569   *         @arg @ref LL_HRTIM_EVENT_5
04570   *         @arg @ref LL_HRTIM_EVENT_6
04571   *         @arg @ref LL_HRTIM_EVENT_7
04572   *         @arg @ref LL_HRTIM_EVENT_8
04573   *         @arg @ref LL_HRTIM_EVENT_9
04574   *         @arg @ref LL_HRTIM_EVENT_10
04575   * @param  Filter This parameter can be one of the following values:
04576   *         @arg @ref LL_HRTIM_EEFLTR_NONE
04577   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
04578   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
04579   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
04580   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
04581   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1
04582   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2
04583   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3
04584   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4
04585   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5
04586   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6
04587   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7
04588   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8
04589   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
04590   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
04591   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
04592   * @retval None
04593   */
04594 __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter)
04595 {
04596   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
04597   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
04598   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
04599                                                     REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
04600   MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
04601 }
04602
04603 /**
04604   * @brief  Get actual event filter settings for a given timer.
04605   * @rmtoll EEFxR1      EE1FLTR        LL_HRTIM_TIM_GetEventFilter\n
04606   *         EEFxR1      EE2FLTR        LL_HRTIM_TIM_GetEventFilter\n
04607   *         EEFxR1      EE3FLTR        LL_HRTIM_TIM_GetEventFilter\n
04608   *         EEFxR1      EE4FLTR        LL_HRTIM_TIM_GetEventFilter\n
04609   *         EEFxR1      EE5FLTR        LL_HRTIM_TIM_GetEventFilter\n
04610   *         EEFxR2      EE6FLTR        LL_HRTIM_TIM_GetEventFilter\n
04611   *         EEFxR2      EE7FLTR        LL_HRTIM_TIM_GetEventFilter\n
04612   *         EEFxR2      EE8FLTR        LL_HRTIM_TIM_GetEventFilter\n
04613   *         EEFxR2      EE9FLTR        LL_HRTIM_TIM_GetEventFilter\n
04614   *         EEFxR2      EE10FLTR       LL_HRTIM_TIM_GetEventFilter
04615   * @param  HRTIMx High Resolution Timer instance
04616   * @param  Timer This parameter can be one of the following values:
04617   *         @arg @ref LL_HRTIM_TIMER_A
04618   *         @arg @ref LL_HRTIM_TIMER_B
04619   *         @arg @ref LL_HRTIM_TIMER_C
04620   *         @arg @ref LL_HRTIM_TIMER_D
04621   *         @arg @ref LL_HRTIM_TIMER_E
04622   * @param  Event This parameter can be one of the following values:
04623   *         @arg @ref LL_HRTIM_EVENT_1
04624   *         @arg @ref LL_HRTIM_EVENT_2
04625   *         @arg @ref LL_HRTIM_EVENT_3
04626   *         @arg @ref LL_HRTIM_EVENT_4
04627   *         @arg @ref LL_HRTIM_EVENT_5
04628   *         @arg @ref LL_HRTIM_EVENT_6
04629   *         @arg @ref LL_HRTIM_EVENT_7
04630   *         @arg @ref LL_HRTIM_EVENT_8
04631   *         @arg @ref LL_HRTIM_EVENT_9
04632   *         @arg @ref LL_HRTIM_EVENT_10
04633   * @retval Filter This parameter can be one of the following values:
04634   *         @arg @ref LL_HRTIM_EEFLTR_NONE
04635   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
04636   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
04637   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
04638   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
04639   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1
04640   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2
04641   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3
04642   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4
04643   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5
04644   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6
04645   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7
04646   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8
04647   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
04648   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
04649   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
04650   */
04651 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
04652 {
04653   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
04654   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
04655   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
04656                                                     REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
04657   return (READ_BIT(*pReg, HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
04658 }
04659
04660 /**
04661   * @brief  Enable or disable event latch mechanism for a given timer.
04662   * @rmtoll EEFxR1      EE1LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04663   *         EEFxR1      EE2LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04664   *         EEFxR1      EE3LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04665   *         EEFxR1      EE4LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04666   *         EEFxR1      EE5LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04667   *         EEFxR2      EE6LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04668   *         EEFxR2      EE7LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04669   *         EEFxR2      EE8LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04670   *         EEFxR2      EE9LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04671   *         EEFxR2      EE10LTCH       LL_HRTIM_TIM_SetEventLatchStatus
04672   * @note This function must not be called when the timer counter is enabled.
04673   * @param  HRTIMx High Resolution Timer instance
04674   * @param  Timer This parameter can be one of the following values:
04675   *         @arg @ref LL_HRTIM_TIMER_A
04676   *         @arg @ref LL_HRTIM_TIMER_B
04677   *         @arg @ref LL_HRTIM_TIMER_C
04678   *         @arg @ref LL_HRTIM_TIMER_D
04679   *         @arg @ref LL_HRTIM_TIMER_E
04680   * @param  Event This parameter can be one of the following values:
04681   *         @arg @ref LL_HRTIM_EVENT_1
04682   *         @arg @ref LL_HRTIM_EVENT_2
04683   *         @arg @ref LL_HRTIM_EVENT_3
04684   *         @arg @ref LL_HRTIM_EVENT_4
04685   *         @arg @ref LL_HRTIM_EVENT_5
04686   *         @arg @ref LL_HRTIM_EVENT_6
04687   *         @arg @ref LL_HRTIM_EVENT_7
04688   *         @arg @ref LL_HRTIM_EVENT_8
04689   *         @arg @ref LL_HRTIM_EVENT_9
04690   *         @arg @ref LL_HRTIM_EVENT_10
04691   * @param  LatchStatus This parameter can be one of the following values:
04692   *         @arg @ref LL_HRTIM_EELATCH_DISABLED
04693   *         @arg @ref LL_HRTIM_EELATCH_ENABLED
04694   * @retval None
04695   */
04696 __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event,
04697                                                       uint32_t LatchStatus)
04698 {
04699   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
04700   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
04701   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
04702                                                     REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
04703   MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent]));
04704 }
04705
04706 /**
04707   * @brief  Get actual event latch status for a given timer.
04708   * @rmtoll EEFxR1      EE1LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04709   *         EEFxR1      EE2LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04710   *         EEFxR1      EE3LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04711   *         EEFxR1      EE4LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04712   *         EEFxR1      EE5LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04713   *         EEFxR2      EE6LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04714   *         EEFxR2      EE7LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04715   *         EEFxR2      EE8LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04716   *         EEFxR2      EE9LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04717   *         EEFxR2      EE10LTCH       LL_HRTIM_TIM_GetEventLatchStatus
04718   * @param  HRTIMx High Resolution Timer instance
04719   * @param  Timer This parameter can be one of the following values:
04720   *         @arg @ref LL_HRTIM_TIMER_A
04721   *         @arg @ref LL_HRTIM_TIMER_B
04722   *         @arg @ref LL_HRTIM_TIMER_C
04723   *         @arg @ref LL_HRTIM_TIMER_D
04724   *         @arg @ref LL_HRTIM_TIMER_E
04725   * @param  Event This parameter can be one of the following values:
04726   *         @arg @ref LL_HRTIM_EVENT_1
04727   *         @arg @ref LL_HRTIM_EVENT_2
04728   *         @arg @ref LL_HRTIM_EVENT_3
04729   *         @arg @ref LL_HRTIM_EVENT_4
04730   *         @arg @ref LL_HRTIM_EVENT_5
04731   *         @arg @ref LL_HRTIM_EVENT_6
04732   *         @arg @ref LL_HRTIM_EVENT_7
04733   *         @arg @ref LL_HRTIM_EVENT_8
04734   *         @arg @ref LL_HRTIM_EVENT_9
04735   *         @arg @ref LL_HRTIM_EVENT_10
04736   * @retval LatchStatus This parameter can be one of the following values:
04737   *         @arg @ref LL_HRTIM_EELATCH_DISABLED
04738   *         @arg @ref LL_HRTIM_EELATCH_ENABLED
04739   */
04740 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
04741 {
04742   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
04743   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
04744   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
04745                                                     REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
04746   return (READ_BIT(*pReg, HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
04747 }
04748
04749 /**
04750   * @}
04751   */
04752
04753 /** @defgroup HRTIM_EF_Dead_Time_Configuration Dead_Time_Configuration
04754   * @{
04755   */
04756
04757 /**
04758   * @brief  Configure the dead time insertion feature for a given timer.
04759   * @rmtoll DTxR      DTPRSC     LL_HRTIM_DT_Config\n
04760   *         DTxR      SDTF       LL_HRTIM_DT_Config\n
04761   *         DTxR      SDRT       LL_HRTIM_DT_Config
04762   * @param  HRTIMx High Resolution Timer instance
04763   * @param  Timer This parameter can be one of the following values:
04764   *         @arg @ref LL_HRTIM_TIMER_A
04765   *         @arg @ref LL_HRTIM_TIMER_B
04766   *         @arg @ref LL_HRTIM_TIMER_C
04767   *         @arg @ref LL_HRTIM_TIMER_D
04768   *         @arg @ref LL_HRTIM_TIMER_E
04769   * @param  Configuration This parameter must be a combination of all the following values:
04770   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16
04771   *         @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE
04772   *         @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE
04773   * @retval None
04774   */
04775 __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
04776 {
04777   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04778   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04779                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04780   MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration);
04781 }
04782
04783 /**
04784   * @brief  Set the deadtime prescaler value.
04785   * @rmtoll DTxR      DTPRSC     LL_HRTIM_DT_SetPrescaler
04786   * @param  HRTIMx High Resolution Timer instance
04787   * @param  Timer This parameter can be one of the following values:
04788   *         @arg @ref LL_HRTIM_TIMER_A
04789   *         @arg @ref LL_HRTIM_TIMER_B
04790   *         @arg @ref LL_HRTIM_TIMER_C
04791   *         @arg @ref LL_HRTIM_TIMER_D
04792   *         @arg @ref LL_HRTIM_TIMER_E
04793   * @param  Prescaler This parameter can be one of the following values:
04794   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
04795   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
04796   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
04797   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
04798   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
04799   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
04800   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
04801   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
04802   * @retval None
04803   */
04804 __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
04805 {
04806   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04807   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04808                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04809   MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler);
04810 }
04811
04812 /**
04813   * @brief  Get actual deadtime prescaler value.
04814   * @rmtoll DTxR      DTPRSC     LL_HRTIM_DT_GetPrescaler
04815   * @param  HRTIMx High Resolution Timer instance
04816   * @param  Timer This parameter can be one of the following values:
04817   *         @arg @ref LL_HRTIM_TIMER_A
04818   *         @arg @ref LL_HRTIM_TIMER_B
04819   *         @arg @ref LL_HRTIM_TIMER_C
04820   *         @arg @ref LL_HRTIM_TIMER_D
04821   *         @arg @ref LL_HRTIM_TIMER_E
04822   * @retval Prescaler This parameter can be one of the following values:
04823   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
04824   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
04825   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
04826   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
04827   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
04828   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
04829   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
04830   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
04831   */
04832 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04833 {
04834   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04835   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04836                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04837   return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC));
04838 }
04839
04840 /**
04841   * @brief  Set the deadtime rising value.
04842   * @rmtoll DTxR      DTR       LL_HRTIM_DT_SetRisingValue
04843   * @param  HRTIMx High Resolution Timer instance
04844   * @param  Timer This parameter can be one of the following values:
04845   *         @arg @ref LL_HRTIM_TIMER_A
04846   *         @arg @ref LL_HRTIM_TIMER_B
04847   *         @arg @ref LL_HRTIM_TIMER_C
04848   *         @arg @ref LL_HRTIM_TIMER_D
04849   *         @arg @ref LL_HRTIM_TIMER_E
04850   * @param  RisingValue Value between 0 and 0x1FF
04851   * @retval None
04852   */
04853 __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue)
04854 {
04855   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04856   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04857                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04858   MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue);
04859 }
04860
04861 /**
04862   * @brief  Get actual deadtime rising value.
04863   * @rmtoll DTxR      DTR       LL_HRTIM_DT_GetRisingValue
04864   * @param  HRTIMx High Resolution Timer instance
04865   * @param  Timer This parameter can be one of the following values:
04866   *         @arg @ref LL_HRTIM_TIMER_A
04867   *         @arg @ref LL_HRTIM_TIMER_B
04868   *         @arg @ref LL_HRTIM_TIMER_C
04869   *         @arg @ref LL_HRTIM_TIMER_D
04870   *         @arg @ref LL_HRTIM_TIMER_E
04871  * @retval RisingValue Value between 0 and 0x1FF
04872   */
04873 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04874 {
04875   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04876   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04877                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04878   return (READ_BIT(*pReg, HRTIM_DTR_DTR));
04879 }
04880
04881 /**
04882   * @brief  Set the deadtime sign on rising edge.
04883   * @rmtoll DTxR      SDTR       LL_HRTIM_DT_SetRisingSign
04884   * @param  HRTIMx High Resolution Timer instance
04885   * @param  Timer This parameter can be one of the following values:
04886   *         @arg @ref LL_HRTIM_TIMER_A
04887   *         @arg @ref LL_HRTIM_TIMER_B
04888   *         @arg @ref LL_HRTIM_TIMER_C
04889   *         @arg @ref LL_HRTIM_TIMER_D
04890   *         @arg @ref LL_HRTIM_TIMER_E
04891   * @param  RisingSign This parameter can be one of the following values:
04892   *         @arg @ref LL_HRTIM_DT_RISING_POSITIVE
04893   *         @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
04894   * @retval None
04895   */
04896 __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign)
04897 {
04898   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04899   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04900                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04901   MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign);
04902 }
04903
04904 /**
04905   * @brief  Get actual deadtime sign on rising edge.
04906   * @rmtoll DTxR      SDTR       LL_HRTIM_DT_GetRisingSign
04907   * @param  HRTIMx High Resolution Timer instance
04908   * @param  Timer This parameter can be one of the following values:
04909   *         @arg @ref LL_HRTIM_TIMER_A
04910   *         @arg @ref LL_HRTIM_TIMER_B
04911   *         @arg @ref LL_HRTIM_TIMER_C
04912   *         @arg @ref LL_HRTIM_TIMER_D
04913   *         @arg @ref LL_HRTIM_TIMER_E
04914   * @retval RisingSign This parameter can be one of the following values:
04915   *         @arg @ref LL_HRTIM_DT_RISING_POSITIVE
04916   *         @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
04917   */
04918 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04919 {
04920   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04921   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04922                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04923   return (READ_BIT(*pReg, HRTIM_DTR_SDTR));
04924 }
04925
04926 /**
04927   * @brief  Set the deadime falling value.
04928   * @rmtoll DTxR      DTF       LL_HRTIM_DT_SetFallingValue
04929   * @param  HRTIMx High Resolution Timer instance
04930   * @param  Timer This parameter can be one of the following values:
04931   *         @arg @ref LL_HRTIM_TIMER_A
04932   *         @arg @ref LL_HRTIM_TIMER_B
04933   *         @arg @ref LL_HRTIM_TIMER_C
04934   *         @arg @ref LL_HRTIM_TIMER_D
04935   *         @arg @ref LL_HRTIM_TIMER_E
04936   * @param  FallingValue Value between 0 and 0x1FF
04937   * @retval None
04938   */
04939 __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue)
04940 {
04941   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04942   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04943                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04944   MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos);
04945 }
04946
04947 /**
04948   * @brief  Get actual deadtime falling value
04949   * @rmtoll DTxR      DTF       LL_HRTIM_DT_GetFallingValue
04950   * @param  HRTIMx High Resolution Timer instance
04951   * @param  Timer This parameter can be one of the following values:
04952   *         @arg @ref LL_HRTIM_TIMER_A
04953   *         @arg @ref LL_HRTIM_TIMER_B
04954   *         @arg @ref LL_HRTIM_TIMER_C
04955   *         @arg @ref LL_HRTIM_TIMER_D
04956   *         @arg @ref LL_HRTIM_TIMER_E
04957  * @retval FallingValue Value between 0 and 0x1FF
04958   */
04959 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04960 {
04961   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04962   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04963                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04964   return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos);
04965 }
04966
04967 /**
04968   * @brief  Set the deadtime sign on falling edge.
04969   * @rmtoll DTxR      SDTF       LL_HRTIM_DT_SetFallingSign
04970   * @param  HRTIMx High Resolution Timer instance
04971   * @param  Timer This parameter can be one of the following values:
04972   *         @arg @ref LL_HRTIM_TIMER_A
04973   *         @arg @ref LL_HRTIM_TIMER_B
04974   *         @arg @ref LL_HRTIM_TIMER_C
04975   *         @arg @ref LL_HRTIM_TIMER_D
04976   *         @arg @ref LL_HRTIM_TIMER_E
04977   * @param  FallingSign This parameter can be one of the following values:
04978   *         @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
04979   *         @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
04980   * @retval None
04981   */
04982 __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign)
04983 {
04984   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04985   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04986                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04987   MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign);
04988 }
04989
04990 /**
04991   * @brief  Get actual deadtime sign on falling edge.
04992   * @rmtoll DTxR      SDTF       LL_HRTIM_DT_GetFallingSign
04993   * @param  HRTIMx High Resolution Timer instance
04994   * @param  Timer This parameter can be one of the following values:
04995   *         @arg @ref LL_HRTIM_TIMER_A
04996   *         @arg @ref LL_HRTIM_TIMER_B
04997   *         @arg @ref LL_HRTIM_TIMER_C
04998   *         @arg @ref LL_HRTIM_TIMER_D
04999   *         @arg @ref LL_HRTIM_TIMER_E
05000   * @retval FallingSign This parameter can be one of the following values:
05001   *         @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
05002   *         @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
05003   */
05004 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05005 {
05006   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05007   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
05008                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05009   return (READ_BIT(*pReg, HRTIM_DTR_SDTF));
05010 }
05011
05012 /**
05013   * @brief  Lock the deadtime value and sign on rising edge.
05014   * @rmtoll DTxR      DTRLK       LL_HRTIM_DT_LockRising
05015   * @param  HRTIMx High Resolution Timer instance
05016   * @param  Timer This parameter can be one of the following values:
05017   *         @arg @ref LL_HRTIM_TIMER_A
05018   *         @arg @ref LL_HRTIM_TIMER_B
05019   *         @arg @ref LL_HRTIM_TIMER_C
05020   *         @arg @ref LL_HRTIM_TIMER_D
05021   *         @arg @ref LL_HRTIM_TIMER_E
05022   * @retval None
05023   */
05024 __STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05025 {
05026   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05027   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
05028                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05029   SET_BIT(*pReg, HRTIM_DTR_DTRLK);
05030 }
05031
05032 /**
05033   * @brief  Lock the deadtime sign on rising edge.
05034   * @rmtoll DTxR      DTRSLK       LL_HRTIM_DT_LockRisingSign
05035   * @param  HRTIMx High Resolution Timer instance
05036   * @param  Timer This parameter can be one of the following values:
05037   *         @arg @ref LL_HRTIM_TIMER_A
05038   *         @arg @ref LL_HRTIM_TIMER_B
05039   *         @arg @ref LL_HRTIM_TIMER_C
05040   *         @arg @ref LL_HRTIM_TIMER_D
05041   *         @arg @ref LL_HRTIM_TIMER_E
05042   * @retval None
05043   */
05044 __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05045 {
05046   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05047   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
05048                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05049   SET_BIT(*pReg, HRTIM_DTR_DTRSLK);
05050 }
05051
05052 /**
05053   * @brief  Lock the deadtime value and sign on falling edge.
05054   * @rmtoll DTxR      DTFLK       LL_HRTIM_DT_LockFalling
05055   * @param  HRTIMx High Resolution Timer instance
05056   * @param  Timer This parameter can be one of the following values:
05057   *         @arg @ref LL_HRTIM_TIMER_A
05058   *         @arg @ref LL_HRTIM_TIMER_B
05059   *         @arg @ref LL_HRTIM_TIMER_C
05060   *         @arg @ref LL_HRTIM_TIMER_D
05061   *         @arg @ref LL_HRTIM_TIMER_E
05062   * @retval None
05063   */
05064 __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05065 {
05066   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05067   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
05068                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05069   SET_BIT(*pReg, HRTIM_DTR_DTFLK);
05070 }
05071
05072 /**
05073   * @brief  Lock the deadtime sign on falling edge.
05074   * @rmtoll DTxR      DTFSLK       LL_HRTIM_DT_LockFallingSign
05075   * @param  HRTIMx High Resolution Timer instance
05076   * @param  Timer This parameter can be one of the following values:
05077   *         @arg @ref LL_HRTIM_TIMER_A
05078   *         @arg @ref LL_HRTIM_TIMER_B
05079   *         @arg @ref LL_HRTIM_TIMER_C
05080   *         @arg @ref LL_HRTIM_TIMER_D
05081   *         @arg @ref LL_HRTIM_TIMER_E
05082   * @retval None
05083   */
05084 __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05085 {
05086   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05087   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
05088                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05089   SET_BIT(*pReg, HRTIM_DTR_DTFSLK);
05090 }
05091
05092 /**
05093   * @}
05094   */
05095
05096 /** @defgroup HRTIM_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration
05097   * @{
05098   */
05099
05100 /**
05101   * @brief  Configure the chopper stage for a given timer.
05102   * @rmtoll CHPxR      CARFRQ       LL_HRTIM_CHP_Config\n
05103   *         CHPxR      CARDTY       LL_HRTIM_CHP_Config\n
05104   *         CHPxR      STRTPW       LL_HRTIM_CHP_Config
05105   * @note This function must not be called if the chopper mode is already
05106   *       enabled for one of the timer outputs.
05107   * @param  HRTIMx High Resolution Timer instance
05108   * @param  Timer This parameter can be one of the following values:
05109   *         @arg @ref LL_HRTIM_TIMER_A
05110   *         @arg @ref LL_HRTIM_TIMER_B
05111   *         @arg @ref LL_HRTIM_TIMER_C
05112   *         @arg @ref LL_HRTIM_TIMER_D
05113   *         @arg @ref LL_HRTIM_TIMER_E
05114   * @param  Configuration This parameter must be a combination of all the following values:
05115   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256
05116   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875
05117   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256
05118   * @retval None
05119   */
05120 __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
05121 {
05122   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05123   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
05124                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05125   MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration);
05126 }
05127
05128 /**
05129   * @brief  Set prescaler determining the carrier frequency to be added on top
05130   *         of the timer output signals when chopper mode is enabled.
05131   * @rmtoll CHPxR      CARFRQ       LL_HRTIM_CHP_SetPrescaler
05132   * @note This function must not be called if the chopper mode is already
05133   *       enabled for one of the timer outputs.
05134   * @param  HRTIMx High Resolution Timer instance
05135   * @param  Timer This parameter can be one of the following values:
05136   *         @arg @ref LL_HRTIM_TIMER_A
05137   *         @arg @ref LL_HRTIM_TIMER_B
05138   *         @arg @ref LL_HRTIM_TIMER_C
05139   *         @arg @ref LL_HRTIM_TIMER_D
05140   *         @arg @ref LL_HRTIM_TIMER_E
05141   * @param  Prescaler This parameter can be one of the following values:
05142   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
05143   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
05144   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
05145   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
05146   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
05147   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
05148   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
05149   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
05150   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
05151   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
05152   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
05153   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
05154   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
05155   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
05156   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
05157   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
05158   * @retval None
05159   */
05160 __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
05161 {
05162   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05163   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
05164                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05165   MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler);
05166 }
05167
05168 /**
05169   * @brief  Get actual chopper stage prescaler value.
05170   * @rmtoll CHPxR      CARFRQ       LL_HRTIM_CHP_GetPrescaler
05171   * @param  HRTIMx High Resolution Timer instance
05172   * @param  Timer This parameter can be one of the following values:
05173   *         @arg @ref LL_HRTIM_TIMER_A
05174   *         @arg @ref LL_HRTIM_TIMER_B
05175   *         @arg @ref LL_HRTIM_TIMER_C
05176   *         @arg @ref LL_HRTIM_TIMER_D
05177   *         @arg @ref LL_HRTIM_TIMER_E
05178   * @retval Prescaler This parameter can be one of the following values:
05179   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
05180   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
05181   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
05182   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
05183   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
05184   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
05185   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
05186   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
05187   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
05188   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
05189   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
05190   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
05191   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
05192   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
05193   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
05194   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
05195   */
05196 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05197 {
05198   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05199   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
05200                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05201   return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ));
05202 }
05203
05204 /**
05205   * @brief  Set the chopper duty cycle.
05206   * @rmtoll CHPxR      CARDTY       LL_HRTIM_CHP_SetDutyCycle
05207   * @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
05208   * @note This function must not be called if the chopper mode is already
05209   *       enabled for one of the timer outputs.
05210   * @param  HRTIMx High Resolution Timer instance
05211   * @param  Timer This parameter can be one of the following values:
05212   *         @arg @ref LL_HRTIM_TIMER_A
05213   *         @arg @ref LL_HRTIM_TIMER_B
05214   *         @arg @ref LL_HRTIM_TIMER_C
05215   *         @arg @ref LL_HRTIM_TIMER_D
05216   *         @arg @ref LL_HRTIM_TIMER_E
05217   * @param  DutyCycle This parameter can be one of the following values:
05218   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
05219   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
05220   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
05221   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
05222   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
05223   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
05224   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
05225   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
05226   * @retval None
05227   */
05228 __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle)
05229 {
05230   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05231   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
05232                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05233   MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle);
05234 }
05235
05236 /**
05237   * @brief  Get actual chopper duty cycle.
05238   * @rmtoll CHPxR      CARDTY       LL_HRTIM_CHP_GetDutyCycle
05239   * @param  HRTIMx High Resolution Timer instance
05240   * @param  Timer This parameter can be one of the following values:
05241   *         @arg @ref LL_HRTIM_TIMER_A
05242   *         @arg @ref LL_HRTIM_TIMER_B
05243   *         @arg @ref LL_HRTIM_TIMER_C
05244   *         @arg @ref LL_HRTIM_TIMER_D
05245   *         @arg @ref LL_HRTIM_TIMER_E
05246   * @retval DutyCycle This parameter can be one of the following values:
05247   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
05248   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
05249   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
05250   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
05251   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
05252   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
05253   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
05254   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
05255   */
05256 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05257 {
05258   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05259   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
05260                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05261   return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY));
05262 }
05263
05264 /**
05265   * @brief  Set the start pulse width.
05266   * @rmtoll CHPxR      STRPW       LL_HRTIM_CHP_SetPulseWidth
05267   * @note This function must not be called if the chopper mode is already
05268   *       enabled for one of the timer outputs.
05269   * @param  HRTIMx High Resolution Timer instance
05270   * @param  Timer This parameter can be one of the following values:
05271   *         @arg @ref LL_HRTIM_TIMER_A
05272   *         @arg @ref LL_HRTIM_TIMER_B
05273   *         @arg @ref LL_HRTIM_TIMER_C
05274   *         @arg @ref LL_HRTIM_TIMER_D
05275   *         @arg @ref LL_HRTIM_TIMER_E
05276   * @param  PulseWidth This parameter can be one of the following values:
05277   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
05278   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
05279   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
05280   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
05281   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
05282   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
05283   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
05284   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
05285   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
05286   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
05287   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
05288   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
05289   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
05290   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
05291   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
05292   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
05293   * @retval None
05294   */
05295 __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth)
05296 {
05297   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05298   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
05299                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05300   MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth);
05301 }
05302
05303 /**
05304   * @brief  Get actual start pulse width.
05305   * @rmtoll CHPxR      STRPW       LL_HRTIM_CHP_GetPulseWidth
05306   * @param  HRTIMx High Resolution Timer instance
05307   * @param  Timer This parameter can be one of the following values:
05308   *         @arg @ref LL_HRTIM_TIMER_A
05309   *         @arg @ref LL_HRTIM_TIMER_B
05310   *         @arg @ref LL_HRTIM_TIMER_C
05311   *         @arg @ref LL_HRTIM_TIMER_D
05312   *         @arg @ref LL_HRTIM_TIMER_E
05313   * @retval PulseWidth This parameter can be one of the following values:
05314   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
05315   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
05316   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
05317   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
05318   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
05319   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
05320   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
05321   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
05322   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
05323   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
05324   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
05325   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
05326   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
05327   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
05328   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
05329   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
05330   */
05331 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05332 {
05333   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05334   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
05335                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05336   return (READ_BIT(*pReg, HRTIM_CHPR_STRPW));
05337 }
05338
05339 /**
05340   * @}
05341   */
05342
05343 /** @defgroup HRTIM_EF_Output_Management Output_Management
05344   * @{
05345   */
05346
05347 /**
05348   * @brief  Set the timer output set source.
05349   * @rmtoll SETx1R      SST          LL_HRTIM_OUT_SetOutputSetSrc\n
05350   *         SETx1R      RESYNC       LL_HRTIM_OUT_SetOutputSetSrc\n
05351   *         SETx1R      PER          LL_HRTIM_OUT_SetOutputSetSrc\n
05352   *         SETx1R      CMP1         LL_HRTIM_OUT_SetOutputSetSrc\n
05353   *         SETx1R      CMP2         LL_HRTIM_OUT_SetOutputSetSrc\n
05354   *         SETx1R      CMP3         LL_HRTIM_OUT_SetOutputSetSrc\n
05355   *         SETx1R      CMP4         LL_HRTIM_OUT_SetOutputSetSrc\n
05356   *         SETx1R      MSTPER       LL_HRTIM_OUT_SetOutputSetSrc\n
05357   *         SETx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputSetSrc\n
05358   *         SETx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputSetSrc\n
05359   *         SETx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputSetSrc\n
05360   *         SETx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputSetSrc\n
05361   *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputSetSrc\n
05362   *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputSetSrc\n
05363   *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputSetSrc\n
05364   *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputSetSrc\n
05365   *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputSetSrc\n
05366   *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputSetSrc\n
05367   *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputSetSrc\n
05368   *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputSetSrc\n
05369   *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputSetSrc\n
05370   *         SETx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputSetSrc\n
05371   *         SETx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputSetSrc\n
05372   *         SETx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputSetSrc\n
05373   *         SETx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputSetSrc\n
05374   *         SETx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputSetSrc\n
05375   *         SETx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputSetSrc\n
05376   *         SETx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputSetSrc\n
05377   *         SETx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputSetSrc\n
05378   *         SETx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputSetSrc\n
05379   *         SETx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputSetSrc\n
05380   *         SETx1R      UPDATE       LL_HRTIM_OUT_SetOutputSetSrc\n
05381   *         SETx1R      SST          LL_HRTIM_OUT_SetOutputSetSrc\n
05382   *         SETx1R      RESYNC       LL_HRTIM_OUT_SetOutputSetSrc\n
05383   *         SETx1R      PER          LL_HRTIM_OUT_SetOutputSetSrc\n
05384   *         SETx1R      CMP1         LL_HRTIM_OUT_SetOutputSetSrc\n
05385   *         SETx1R      CMP2         LL_HRTIM_OUT_SetOutputSetSrc\n
05386   *         SETx1R      CMP3         LL_HRTIM_OUT_SetOutputSetSrc\n
05387   *         SETx1R      CMP4         LL_HRTIM_OUT_SetOutputSetSrc\n
05388   *         SETx1R      MSTPER       LL_HRTIM_OUT_SetOutputSetSrc\n
05389   *         SETx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputSetSrc\n
05390   *         SETx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputSetSrc\n
05391   *         SETx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputSetSrc\n
05392   *         SETx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputSetSrc\n
05393   *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputSetSrc\n
05394   *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputSetSrc\n
05395   *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputSetSrc\n
05396   *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputSetSrc\n
05397   *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputSetSrc\n
05398   *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputSetSrc\n
05399   *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputSetSrc\n
05400   *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputSetSrc\n
05401   *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputSetSrc\n
05402   *         SETx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputSetSrc\n
05403   *         SETx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputSetSrc\n
05404   *         SETx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputSetSrc\n
05405   *         SETx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputSetSrc\n
05406   *         SETx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputSetSrc\n
05407   *         SETx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputSetSrc\n
05408   *         SETx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputSetSrc\n
05409   *         SETx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputSetSrc\n
05410   *         SETx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputSetSrc\n
05411   *         SETx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputSetSrc\n
05412   *         SETx1R      UPDATE       LL_HRTIM_OUT_SetOutputSetSrc
05413   * @param  HRTIMx High Resolution Timer instance
05414   * @param  Output This parameter can be one of the following values:
05415   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05416   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05417   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05418   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05419   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05420   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05421   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05422   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05423   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05424   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05425   * @param SetSrc This parameter can be a combination of the following values:
05426   *         @arg @ref LL_HRTIM_CROSSBAR_NONE
05427   *         @arg @ref LL_HRTIM_CROSSBAR_RESYNC
05428   *         @arg @ref LL_HRTIM_CROSSBAR_TIMPER
05429   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
05430   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
05431   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
05432   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
05433   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
05434   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
05435   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
05436   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
05437   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
05438   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
05439   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
05440   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
05441   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
05442   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
05443   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
05444   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
05445   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
05446   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
05447   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_1
05448   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_2
05449   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_3
05450   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_4
05451   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_5
05452   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_6
05453   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_7
05454   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_8
05455   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_9
05456   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_10
05457   *         @arg @ref LL_HRTIM_CROSSBAR_UPDATE
05458   * @retval None
05459   */
05460 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
05461 {
05462   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05463   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
05464                                                     REG_OFFSET_TAB_SETxR[iOutput]));
05465   WRITE_REG(*pReg, SetSrc);
05466 }
05467
05468 /**
05469   * @brief  Get the timer output set source.
05470   * @rmtoll SETx1R      SST          LL_HRTIM_OUT_GetOutputSetSrc\n
05471   *         SETx1R      RESYNC       LL_HRTIM_OUT_GetOutputSetSrc\n
05472   *         SETx1R      PER          LL_HRTIM_OUT_GetOutputSetSrc\n
05473   *         SETx1R      CMP1         LL_HRTIM_OUT_GetOutputSetSrc\n
05474   *         SETx1R      CMP2         LL_HRTIM_OUT_GetOutputSetSrc\n
05475   *         SETx1R      CMP3         LL_HRTIM_OUT_GetOutputSetSrc\n
05476   *         SETx1R      CMP4         LL_HRTIM_OUT_GetOutputSetSrc\n
05477   *         SETx1R      MSTPER       LL_HRTIM_OUT_GetOutputSetSrc\n
05478   *         SETx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputSetSrc\n
05479   *         SETx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputSetSrc\n
05480   *         SETx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputSetSrc\n
05481   *         SETx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputSetSrc\n
05482   *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputSetSrc\n
05483   *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputSetSrc\n
05484   *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputSetSrc\n
05485   *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputSetSrc\n
05486   *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputSetSrc\n
05487   *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputSetSrc\n
05488   *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputSetSrc\n
05489   *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputSetSrc\n
05490   *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputSetSrc\n
05491   *         SETx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputSetSrc\n
05492   *         SETx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputSetSrc\n
05493   *         SETx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputSetSrc\n
05494   *         SETx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputSetSrc\n
05495   *         SETx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputSetSrc\n
05496   *         SETx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputSetSrc\n
05497   *         SETx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputSetSrc\n
05498   *         SETx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputSetSrc\n
05499   *         SETx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputSetSrc\n
05500   *         SETx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputSetSrc\n
05501   *         SETx1R      UPDATE       LL_HRTIM_OUT_GetOutputSetSrc\n
05502   *         SETx1R      SST          LL_HRTIM_OUT_GetOutputSetSrc\n
05503   *         SETx1R      RESYNC       LL_HRTIM_OUT_GetOutputSetSrc\n
05504   *         SETx1R      PER          LL_HRTIM_OUT_GetOutputSetSrc\n
05505   *         SETx1R      CMP1         LL_HRTIM_OUT_GetOutputSetSrc\n
05506   *         SETx1R      CMP2         LL_HRTIM_OUT_GetOutputSetSrc\n
05507   *         SETx1R      CMP3         LL_HRTIM_OUT_GetOutputSetSrc\n
05508   *         SETx1R      CMP4         LL_HRTIM_OUT_GetOutputSetSrc\n
05509   *         SETx1R      MSTPER       LL_HRTIM_OUT_GetOutputSetSrc\n
05510   *         SETx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputSetSrc\n
05511   *         SETx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputSetSrc\n
05512   *         SETx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputSetSrc\n
05513   *         SETx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputSetSrc\n
05514   *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputSetSrc\n
05515   *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputSetSrc\n
05516   *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputSetSrc\n
05517   *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputSetSrc\n
05518   *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputSetSrc\n
05519   *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputSetSrc\n
05520   *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputSetSrc\n
05521   *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputSetSrc\n
05522   *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputSetSrc\n
05523   *         SETx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputSetSrc\n
05524   *         SETx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputSetSrc\n
05525   *         SETx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputSetSrc\n
05526   *         SETx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputSetSrc\n
05527   *         SETx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputSetSrc\n
05528   *         SETx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputSetSrc\n
05529   *         SETx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputSetSrc\n
05530   *         SETx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputSetSrc\n
05531   *         SETx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputSetSrc\n
05532   *         SETx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputSetSrc\n
05533   *         SETx1R      UPDATE       LL_HRTIM_OUT_GetOutputSetSrc
05534   * @param  HRTIMx High Resolution Timer instance
05535   * @param  Output This parameter can be one of the following values:
05536   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05537   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05538   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05539   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05540   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05541   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05542   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05543   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05544   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05545   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05546   * @retval SetSrc This parameter can be a combination of the following values:
05547   *         @arg @ref LL_HRTIM_CROSSBAR_NONE
05548   *         @arg @ref LL_HRTIM_CROSSBAR_RESYNC
05549   *         @arg @ref LL_HRTIM_CROSSBAR_TIMPER
05550   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
05551   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
05552   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
05553   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
05554   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
05555   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
05556   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
05557   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
05558   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
05559   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
05560   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
05561   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
05562   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
05563   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
05564   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
05565   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
05566   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
05567   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
05568   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_1
05569   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_2
05570   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_3
05571   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_4
05572   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_5
05573   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_6
05574   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_7
05575   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_8
05576   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_9
05577   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_10
05578   *         @arg @ref LL_HRTIM_CROSSBAR_UPDATE
05579   */
05580 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
05581 {
05582   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05583   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
05584                                                     REG_OFFSET_TAB_SETxR[iOutput]));
05585   return (uint32_t) READ_REG(*pReg);
05586 }
05587
05588 /**
05589   * @brief  Set the timer output reset source.
05590   * @rmtoll RSTx1R      RST          LL_HRTIM_OUT_SetOutputResetSrc\n
05591   *         RSTx1R      RESYNC       LL_HRTIM_OUT_SetOutputResetSrc\n
05592   *         RSTx1R      PER          LL_HRTIM_OUT_SetOutputResetSrc\n
05593   *         RSTx1R      CMP1         LL_HRTIM_OUT_SetOutputResetSrc\n
05594   *         RSTx1R      CMP2         LL_HRTIM_OUT_SetOutputResetSrc\n
05595   *         RSTx1R      CMP3         LL_HRTIM_OUT_SetOutputResetSrc\n
05596   *         RSTx1R      CMP4         LL_HRTIM_OUT_SetOutputResetSrc\n
05597   *         RSTx1R      MSTPER       LL_HRTIM_OUT_SetOutputResetSrc\n
05598   *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputResetSrc\n
05599   *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputResetSrc\n
05600   *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputResetSrc\n
05601   *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputResetSrc\n
05602   *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputResetSrc\n
05603   *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputResetSrc\n
05604   *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputResetSrc\n
05605   *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputResetSrc\n
05606   *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputResetSrc\n
05607   *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputResetSrc\n
05608   *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputResetSrc\n
05609   *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputResetSrc\n
05610   *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputResetSrc\n
05611   *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputResetSrc\n
05612   *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputResetSrc\n
05613   *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputResetSrc\n
05614   *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputResetSrc\n
05615   *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputResetSrc\n
05616   *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputResetSrc\n
05617   *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputResetSrc\n
05618   *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputResetSrc\n
05619   *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputResetSrc\n
05620   *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputResetSrc\n
05621   *         RSTx1R      UPDATE       LL_HRTIM_OUT_SetOutputResetSrc\n
05622   *         RSTx1R      RST          LL_HRTIM_OUT_SetOutputResetSrc\n
05623   *         RSTx1R      RESYNC       LL_HRTIM_OUT_SetOutputResetSrc\n
05624   *         RSTx1R      PER          LL_HRTIM_OUT_SetOutputResetSrc\n
05625   *         RSTx1R      CMP1         LL_HRTIM_OUT_SetOutputResetSrc\n
05626   *         RSTx1R      CMP2         LL_HRTIM_OUT_SetOutputResetSrc\n
05627   *         RSTx1R      CMP3         LL_HRTIM_OUT_SetOutputResetSrc\n
05628   *         RSTx1R      CMP4         LL_HRTIM_OUT_SetOutputResetSrc\n
05629   *         RSTx1R      MSTPER       LL_HRTIM_OUT_SetOutputResetSrc\n
05630   *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputResetSrc\n
05631   *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputResetSrc\n
05632   *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputResetSrc\n
05633   *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputResetSrc\n
05634   *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputResetSrc\n
05635   *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputResetSrc\n
05636   *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputResetSrc\n
05637   *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputResetSrc\n
05638   *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputResetSrc\n
05639   *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputResetSrc\n
05640   *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputResetSrc\n
05641   *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputResetSrc\n
05642   *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputResetSrc\n
05643   *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputResetSrc\n
05644   *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputResetSrc\n
05645   *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputResetSrc\n
05646   *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputResetSrc\n
05647   *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputResetSrc\n
05648   *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputResetSrc\n
05649   *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputResetSrc\n
05650   *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputResetSrc\n
05651   *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputResetSrc\n
05652   *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputResetSrc\n
05653   *         RSTx1R      UPDATE       LL_HRTIM_OUT_SetOutputResetSrc
05654   * @param  HRTIMx High Resolution Timer instance
05655   * @param  Output This parameter can be one of the following values:
05656   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05657   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05658   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05659   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05660   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05661   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05662   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05663   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05664   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05665   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05666   * @param ResetSrc This parameter can be a combination of the following values:
05667   *         @arg @ref LL_HRTIM_CROSSBAR_NONE
05668   *         @arg @ref LL_HRTIM_CROSSBAR_RESYNC
05669   *         @arg @ref LL_HRTIM_CROSSBAR_TIMPER
05670   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
05671   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
05672   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
05673   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
05674   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
05675   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
05676   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
05677   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
05678   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
05679   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
05680   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
05681   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
05682   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
05683   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
05684   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
05685   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
05686   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
05687   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
05688   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_1
05689   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_2
05690   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_3
05691   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_4
05692   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_5
05693   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_6
05694   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_7
05695   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_8
05696   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_9
05697   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_10
05698   *         @arg @ref LL_HRTIM_CROSSBAR_UPDATE
05699   * @retval None
05700   */
05701 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)
05702 {
05703   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05704   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
05705                                                     REG_OFFSET_TAB_SETxR[iOutput]));
05706   WRITE_REG(*pReg, ResetSrc);
05707 }
05708
05709 /**
05710   * @brief  Get the timer output set source.
05711   * @rmtoll RSTx1R      RST          LL_HRTIM_OUT_GetOutputResetSrc\n
05712   *         RSTx1R      RESYNC       LL_HRTIM_OUT_GetOutputResetSrc\n
05713   *         RSTx1R      PER          LL_HRTIM_OUT_GetOutputResetSrc\n
05714   *         RSTx1R      CMP1         LL_HRTIM_OUT_GetOutputResetSrc\n
05715   *         RSTx1R      CMP2         LL_HRTIM_OUT_GetOutputResetSrc\n
05716   *         RSTx1R      CMP3         LL_HRTIM_OUT_GetOutputResetSrc\n
05717   *         RSTx1R      CMP4         LL_HRTIM_OUT_GetOutputResetSrc\n
05718   *         RSTx1R      MSTPER       LL_HRTIM_OUT_GetOutputResetSrc\n
05719   *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputResetSrc\n
05720   *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputResetSrc\n
05721   *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputResetSrc\n
05722   *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputResetSrc\n
05723   *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputResetSrc\n
05724   *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputResetSrc\n
05725   *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputResetSrc\n
05726   *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputResetSrc\n
05727   *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputResetSrc\n
05728   *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputResetSrc\n
05729   *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputResetSrc\n
05730   *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputResetSrc\n
05731   *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputResetSrc\n
05732   *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputResetSrc\n
05733   *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputResetSrc\n
05734   *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputResetSrc\n
05735   *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputResetSrc\n
05736   *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputResetSrc\n
05737   *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputResetSrc\n
05738   *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputResetSrc\n
05739   *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputResetSrc\n
05740   *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputResetSrc\n
05741   *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputResetSrc\n
05742   *         RSTx1R      UPDATE       LL_HRTIM_OUT_GetOutputResetSrc\n
05743   *         RSTx1R      RST          LL_HRTIM_OUT_GetOutputResetSrc\n
05744   *         RSTx1R      RESYNC       LL_HRTIM_OUT_GetOutputResetSrc\n
05745   *         RSTx1R      PER          LL_HRTIM_OUT_GetOutputResetSrc\n
05746   *         RSTx1R      CMP1         LL_HRTIM_OUT_GetOutputResetSrc\n
05747   *         RSTx1R      CMP2         LL_HRTIM_OUT_GetOutputResetSrc\n
05748   *         RSTx1R      CMP3         LL_HRTIM_OUT_GetOutputResetSrc\n
05749   *         RSTx1R      CMP4         LL_HRTIM_OUT_GetOutputResetSrc\n
05750   *         RSTx1R      MSTPER       LL_HRTIM_OUT_GetOutputResetSrc\n
05751   *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputResetSrc\n
05752   *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputResetSrc\n
05753   *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputResetSrc\n
05754   *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputResetSrc\n
05755   *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputResetSrc\n
05756   *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputResetSrc\n
05757   *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputResetSrc\n
05758   *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputResetSrc\n
05759   *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputResetSrc\n
05760   *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputResetSrc\n
05761   *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputResetSrc\n
05762   *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputResetSrc\n
05763   *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputResetSrc\n
05764   *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputResetSrc\n
05765   *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputResetSrc\n
05766   *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputResetSrc\n
05767   *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputResetSrc\n
05768   *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputResetSrc\n
05769   *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputResetSrc\n
05770   *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputResetSrc\n
05771   *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputResetSrc\n
05772   *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputResetSrc\n
05773   *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputResetSrc\n
05774   *         RSTx1R      UPDATE       LL_HRTIM_OUT_GetOutputResetSrc
05775   * @param  HRTIMx High Resolution Timer instance
05776   * @param  Output This parameter can be one of the following values:
05777   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05778   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05779   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05780   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05781   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05782   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05783   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05784   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05785   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05786   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05787   * @retval ResetSrc This parameter can be a combination of the following values:
05788   *         @arg @ref LL_HRTIM_CROSSBAR_NONE
05789   *         @arg @ref LL_HRTIM_CROSSBAR_RESYNC
05790   *         @arg @ref LL_HRTIM_CROSSBAR_TIMPER
05791   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
05792   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
05793   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
05794   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
05795   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
05796   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
05797   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
05798   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
05799   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
05800   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
05801   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
05802   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
05803   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
05804   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
05805   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
05806   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
05807   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
05808   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
05809   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_1
05810   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_2
05811   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_3
05812   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_4
05813   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_5
05814   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_6
05815   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_7
05816   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_8
05817   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_9
05818   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_10
05819   *         @arg @ref LL_HRTIM_CROSSBAR_UPDATE
05820   */
05821 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
05822 {
05823   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05824   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
05825                                                     REG_OFFSET_TAB_SETxR[iOutput]));
05826   return (uint32_t) READ_REG(*pReg);
05827 }
05828
05829 /**
05830   * @brief  Configure a timer output.
05831   * @rmtoll OUTxR      POL1          LL_HRTIM_OUT_Config\n
05832   *         OUTxR      IDLEM1        LL_HRTIM_OUT_Config\n
05833   *         OUTxR      IDLES1        LL_HRTIM_OUT_Config\n
05834   *         OUTxR      FAULT1        LL_HRTIM_OUT_Config\n
05835   *         OUTxR      CHP1          LL_HRTIM_OUT_Config\n
05836   *         OUTxR      DIDL1         LL_HRTIM_OUT_Config\n
05837   *         OUTxR      POL2          LL_HRTIM_OUT_Config\n
05838   *         OUTxR      IDLEM2        LL_HRTIM_OUT_Config\n
05839   *         OUTxR      IDLES2        LL_HRTIM_OUT_Config\n
05840   *         OUTxR      FAULT2        LL_HRTIM_OUT_Config\n
05841   *         OUTxR      CHP2          LL_HRTIM_OUT_Config\n
05842   *         OUTxR      DIDL2         LL_HRTIM_OUT_Config
05843   * @param  HRTIMx High Resolution Timer instance
05844   * @param  Output This parameter can be one of the following values:
05845   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05846   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05847   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05848   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05849   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05850   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05851   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05852   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05853   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05854   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05855   * @param  Configuration This parameter must be a combination of all the following values:
05856   *         @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
05857   *         @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
05858   *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
05859   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
05860   *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
05861   *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
05862   * @retval None
05863   */
05864 __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration)
05865 {
05866   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05867   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05868                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
05869   MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]),
05870              (Configuration << REG_SHIFT_TAB_OUTxR[iOutput]));
05871 }
05872
05873 /**
05874   * @brief  Set the polarity of a timer output.
05875   * @rmtoll OUTxR      POL1          LL_HRTIM_OUT_SetPolarity\n
05876   *         OUTxR      POL2          LL_HRTIM_OUT_SetPolarity
05877   * @param  HRTIMx High Resolution Timer instance
05878   * @param  Output This parameter can be one of the following values:
05879   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05880   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05881   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05882   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05883   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05884   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05885   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05886   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05887   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05888   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05889   * @param  Polarity This parameter can be one of the following values:
05890   *         @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
05891   *         @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
05892   * @retval None
05893   */
05894 __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity)
05895 {
05896   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05897   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05898                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
05899   MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput]));
05900 }
05901
05902 /**
05903   * @brief  Get actual polarity of the timer output.
05904   * @rmtoll OUTxR      POL1          LL_HRTIM_OUT_GetPolarity\n
05905   *         OUTxR      POL2          LL_HRTIM_OUT_GetPolarity
05906   * @param  HRTIMx High Resolution Timer instance
05907   * @param  Output This parameter can be one of the following values:
05908   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05909   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05910   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05911   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05912   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05913   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05914   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05915   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05916   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05917   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05918   * @retval Polarity This parameter can be one of the following values:
05919   *         @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
05920   *         @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
05921   */
05922 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output)
05923 {
05924   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05925   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05926                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
05927   return (READ_BIT(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
05928 }
05929
05930 /**
05931   * @brief  Set the output IDLE mode.
05932   * @rmtoll OUTxR      IDLEM1          LL_HRTIM_OUT_SetIdleMode\n
05933   *         OUTxR      IDLEM2          LL_HRTIM_OUT_SetIdleMode
05934   * @note This function must not be called when the burst mode is active
05935   * @param  HRTIMx High Resolution Timer instance
05936   * @param  Output This parameter can be one of the following values:
05937   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05938   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05939   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05940   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05941   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05942   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05943   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05944   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05945   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05946   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05947   * @param  IdleMode This parameter can be one of the following values:
05948   *         @arg @ref LL_HRTIM_OUT_NO_IDLE
05949   *         @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
05950   * @retval None
05951   */
05952 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode)
05953 {
05954   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05955   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05956                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
05957   MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleMode << REG_SHIFT_TAB_OUTxR[iOutput]));
05958 }
05959
05960 /**
05961   * @brief  Get actual output IDLE mode.
05962   * @rmtoll OUTxR      IDLEM1          LL_HRTIM_OUT_GetIdleMode\n
05963   *         OUTxR      IDLEM2          LL_HRTIM_OUT_GetIdleMode
05964   * @param  HRTIMx High Resolution Timer instance
05965   * @param  Output This parameter can be one of the following values:
05966   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05967   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05968   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05969   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05970   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05971   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05972   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05973   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05974   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05975   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05976   * @retval IdleMode This parameter can be one of the following values:
05977   *         @arg @ref LL_HRTIM_OUT_NO_IDLE
05978   *         @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
05979   */
05980 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
05981 {
05982   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05983   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05984                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
05985   return (READ_BIT(*pReg, (HRTIM_OUTR_IDLM1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
05986 }
05987
05988 /**
05989   * @brief  Set the output IDLE level.
05990   * @rmtoll OUTxR      IDLES1          LL_HRTIM_OUT_SetIdleLevel\n
05991   *         OUTxR      IDLES2          LL_HRTIM_OUT_SetIdleLevel
05992   * @note This function must be called prior enabling the timer.
05993   * @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE.
05994   * @param  HRTIMx High Resolution Timer instance
05995   * @param  Output This parameter can be one of the following values:
05996   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05997   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05998   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05999   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06000   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06001   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06002   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06003   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06004   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06005   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06006   * @param  IdleLevel This parameter can be one of the following values:
06007   *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
06008   *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
06009   * @retval None
06010   */
06011 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel)
06012 {
06013   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06014   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
06015                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
06016   MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput]));
06017 }
06018
06019 /**
06020   * @brief  Get actual output IDLE level.
06021   * @rmtoll OUTxR      IDLES1          LL_HRTIM_OUT_GetIdleLevel\n
06022   *         OUTxR      IDLES2          LL_HRTIM_OUT_GetIdleLevel
06023   * @param  HRTIMx High Resolution Timer instance
06024   * @param  Output This parameter can be one of the following values:
06025   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06026   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06027   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06028   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06029   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06030   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06031   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06032   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06033   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06034   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06035   * @retval IdleLevel This parameter can be one of the following values:
06036   *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
06037   *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
06038   */
06039 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
06040 {
06041   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06042   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
06043                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
06044   return (READ_BIT(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
06045 }
06046
06047 /**
06048   * @brief  Set the output FAULT state.
06049   * @rmtoll OUTxR      FAULT1          LL_HRTIM_OUT_SetFaultState\n
06050   *         OUTxR      FAULT2          LL_HRTIM_OUT_SetFaultState
06051   * @note This function must not called when the timer is enabled and a fault
06052   *       channel is enabled at timer level.
06053   * @param  HRTIMx High Resolution Timer instance
06054   * @param  Output This parameter can be one of the following values:
06055   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06056   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06057   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06058   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06059   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06060   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06061   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06062   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06063   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06064   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06065   * @param  FaultState This parameter can be one of the following values:
06066   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
06067   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
06068   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
06069   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
06070   * @retval None
06071   */
06072 __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState)
06073 {
06074   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06075   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
06076                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
06077   MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput]));
06078 }
06079
06080 /**
06081   * @brief  Get actual FAULT state.
06082   * @rmtoll OUTxR      FAULT1          LL_HRTIM_OUT_GetFaultState\n
06083   *         OUTxR      FAULT2          LL_HRTIM_OUT_GetFaultState
06084   * @param  HRTIMx High Resolution Timer instance
06085   * @param  Output This parameter can be one of the following values:
06086   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06087   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06088   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06089   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06090   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06091   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06092   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06093   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06094   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06095   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06096   * @retval FaultState This parameter can be one of the following values:
06097   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
06098   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
06099   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
06100   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
06101   */
06102 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output)
06103 {
06104   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06105   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
06106                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
06107   return (READ_BIT(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
06108 }
06109
06110 /**
06111   * @brief  Set the output chopper mode.
06112   * @rmtoll OUTxR      CHP1          LL_HRTIM_OUT_SetChopperMode\n
06113   *         OUTxR      CHP2          LL_HRTIM_OUT_SetChopperMode
06114   * @note This function must not called when the timer is enabled.
06115   * @param  HRTIMx High Resolution Timer instance
06116   * @param  Output This parameter can be one of the following values:
06117   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06118   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06119   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06120   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06121   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06122   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06123   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06124   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06125   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06126   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06127   * @param  ChopperMode This parameter can be one of the following values:
06128   *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
06129   *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
06130   * @retval None
06131   */
06132 __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode)
06133 {
06134   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06135   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
06136                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
06137   MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput]));
06138 }
06139
06140 /**
06141   * @brief  Get actual output chopper mode
06142   * @rmtoll OUTxR      CHP1          LL_HRTIM_OUT_GetChopperMode\n
06143   *         OUTxR      CHP2          LL_HRTIM_OUT_GetChopperMode
06144   * @param  HRTIMx High Resolution Timer instance
06145   * @param  Output This parameter can be one of the following values:
06146   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06147   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06148   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06149   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06150   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06151   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06152   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06153   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06154   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06155   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06156   * @retval ChopperMode This parameter can be one of the following values:
06157   *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
06158   *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
06159   */
06160 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
06161 {
06162   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06163   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
06164                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
06165   return (READ_BIT(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
06166 }
06167
06168 /**
06169   * @brief  Set the output burst mode entry mode.
06170   * @rmtoll OUTxR      DIDL1          LL_HRTIM_OUT_SetBMEntryMode\n
06171   *         OUTxR      DIDL2          LL_HRTIM_OUT_SetBMEntryMode
06172   * @note This function must not called when the timer is enabled.
06173   * @param  HRTIMx High Resolution Timer instance
06174   * @param  Output This parameter can be one of the following values:
06175   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06176   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06177   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06178   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06179   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06180   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06181   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06182   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06183   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06184   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06185   * @param  BMEntryMode This parameter can be one of the following values:
06186   *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
06187   *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
06188   * @retval None
06189   */
06190 __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode)
06191 {
06192   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06193   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
06194                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
06195   MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput]));
06196 }
06197
06198 /**
06199   * @brief  Get actual output burst mode entry mode.
06200   * @rmtoll OUTxR      DIDL1          LL_HRTIM_OUT_GetBMEntryMode\n
06201   *         OUTxR      DIDL2          LL_HRTIM_OUT_GetBMEntryMode
06202   * @param  HRTIMx High Resolution Timer instance
06203   * @param  Output This parameter can be one of the following values:
06204   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06205   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06206   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06207   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06208   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06209   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06210   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06211   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06212   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06213   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06214   * @retval BMEntryMode This parameter can be one of the following values:
06215   *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
06216   *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
06217   */
06218 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
06219 {
06220   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06221   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
06222                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
06223   return (READ_BIT(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
06224 }
06225
06226 /**
06227   * @brief  Get the level (active or inactive) of the designated output when the
06228   *         delayed protection was triggered.
06229   * @rmtoll TIMxISR      O1SRSR          LL_HRTIM_OUT_GetDLYPRTOutStatus\n
06230   *         TIMxISR      O2SRSR          LL_HRTIM_OUT_GetDLYPRTOutStatus
06231   * @param  HRTIMx High Resolution Timer instance
06232   * @param  Output This parameter can be one of the following values:
06233   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06234   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06235   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06236   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06237   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06238   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06239   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06240   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06241   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06242   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06243   * @retval OutputLevel This parameter can be one of the following values:
06244   *         @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
06245   *         @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
06246   */
06247 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output)
06248 {
06249   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06250   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
06251                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
06252   return ((READ_BIT(*pReg, (HRTIM_TIMISR_O1STAT << REG_SHIFT_TAB_OxSTAT[iOutput])) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
06253           HRTIM_TIMISR_O1STAT_Pos);
06254 }
06255
06256 /**
06257   * @brief  Force the timer output to its active or inactive level.
06258   * @rmtoll SETx1R      SST          LL_HRTIM_OUT_ForceLevel\n
06259   *         RSTx1R      SRT          LL_HRTIM_OUT_ForceLevel\n
06260   *         SETx2R      SST          LL_HRTIM_OUT_ForceLevel\n
06261   *         RSTx2R      SRT          LL_HRTIM_OUT_ForceLevel
06262   * @param  HRTIMx High Resolution Timer instance
06263   * @param  Output This parameter can be one of the following values:
06264   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06265   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06266   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06267   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06268   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06269   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06270   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06271   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06272   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06273   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06274   * @param  OutputLevel This parameter can be one of the following values:
06275   *         @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
06276   *         @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
06277   * @retval None
06278   */
06279 __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel)
06280 {
06281   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06282   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
06283                                                     REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel]));
06284   SET_BIT(*pReg, HRTIM_SET1R_SST);
06285 }
06286
06287 /**
06288   * @brief  Get actual output level, before the output stage (chopper, polarity).
06289   * @rmtoll TIMxISR     O1CPY          LL_HRTIM_OUT_GetLevel\n
06290   *         TIMxISR     O2CPY          LL_HRTIM_OUT_GetLevel
06291   * @param  HRTIMx High Resolution Timer instance
06292   * @param  Output This parameter can be one of the following values:
06293   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06294   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06295   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06296   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06297   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06298   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06299   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06300   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06301   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06302   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06303   * @retval OutputLevel This parameter can be one of the following values:
06304   *         @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
06305   *         @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
06306   */
06307 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
06308 {
06309   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06310   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
06311                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
06312   return ((READ_BIT(*pReg, (HRTIM_TIMISR_O1CPY << REG_SHIFT_TAB_OxSTAT[iOutput])) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
06313           HRTIM_TIMISR_O1CPY_Pos);
06314 }
06315
06316 /**
06317   * @}
06318   */
06319
06320 /** @defgroup HRTIM_EF_External_Event_management External_Event_management
06321   * @{
06322   */
06323
06324 /**
06325   * @brief  Configure external event conditioning.
06326   * @rmtoll EECR1     EE1SRC          LL_HRTIM_EE_Config\n
06327   *         EECR1     EE1POL          LL_HRTIM_EE_Config\n
06328   *         EECR1     EE1SNS          LL_HRTIM_EE_Config\n
06329   *         EECR1     EE1FAST         LL_HRTIM_EE_Config\n
06330   *         EECR1     EE2SRC          LL_HRTIM_EE_Config\n
06331   *         EECR1     EE2POL          LL_HRTIM_EE_Config\n
06332   *         EECR1     EE2SNS          LL_HRTIM_EE_Config\n
06333   *         EECR1     EE2FAST         LL_HRTIM_EE_Config\n
06334   *         EECR1     EE3SRC          LL_HRTIM_EE_Config\n
06335   *         EECR1     EE3POL          LL_HRTIM_EE_Config\n
06336   *         EECR1     EE3SNS          LL_HRTIM_EE_Config\n
06337   *         EECR1     EE3FAST         LL_HRTIM_EE_Config\n
06338   *         EECR1     EE4SRC          LL_HRTIM_EE_Config\n
06339   *         EECR1     EE4POL          LL_HRTIM_EE_Config\n
06340   *         EECR1     EE4SNS          LL_HRTIM_EE_Config\n
06341   *         EECR1     EE4FAST         LL_HRTIM_EE_Config\n
06342   *         EECR1     EE5SRC          LL_HRTIM_EE_Config\n
06343   *         EECR1     EE5POL          LL_HRTIM_EE_Config\n
06344   *         EECR1     EE5SNS          LL_HRTIM_EE_Config\n
06345   *         EECR1     EE5FAST         LL_HRTIM_EE_Config\n
06346   *         EECR2     EE6SRC          LL_HRTIM_EE_Config\n
06347   *         EECR2     EE6POL          LL_HRTIM_EE_Config\n
06348   *         EECR2     EE6SNS          LL_HRTIM_EE_Config\n
06349   *         EECR2     EE6FAST         LL_HRTIM_EE_Config\n
06350   *         EECR2     EE7SRC          LL_HRTIM_EE_Config\n
06351   *         EECR2     EE7POL          LL_HRTIM_EE_Config\n
06352   *         EECR2     EE7SNS          LL_HRTIM_EE_Config\n
06353   *         EECR2     EE7FAST         LL_HRTIM_EE_Config\n
06354   *         EECR2     EE8SRC          LL_HRTIM_EE_Config\n
06355   *         EECR2     EE8POL          LL_HRTIM_EE_Config\n
06356   *         EECR2     EE8SNS          LL_HRTIM_EE_Config\n
06357   *         EECR2     EE8FAST         LL_HRTIM_EE_Config\n
06358   *         EECR2     EE9SRC          LL_HRTIM_EE_Config\n
06359   *         EECR2     EE9POL          LL_HRTIM_EE_Config\n
06360   *         EECR2     EE9SNS          LL_HRTIM_EE_Config\n
06361   *         EECR2     EE9FAST         LL_HRTIM_EE_Config\n
06362   *         EECR2     EE10SRC         LL_HRTIM_EE_Config\n
06363   *         EECR2     EE10POL         LL_HRTIM_EE_Config\n
06364   *         EECR2     EE10SNS         LL_HRTIM_EE_Config\n
06365   *         EECR2     EE10FAST        LL_HRTIM_EE_Config
06366   * @note This function must not be called when the timer counter is enabled.
06367   * @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel.
06368   * @note Fast mode is available only for LL_HRTIM_EVENT_1..5.
06369   * @param  HRTIMx High Resolution Timer instance
06370   * @param  Event This parameter can be one of the following values:
06371   *         @arg @ref LL_HRTIM_EVENT_1
06372   *         @arg @ref LL_HRTIM_EVENT_2
06373   *         @arg @ref LL_HRTIM_EVENT_3
06374   *         @arg @ref LL_HRTIM_EVENT_4
06375   *         @arg @ref LL_HRTIM_EVENT_5
06376   *         @arg @ref LL_HRTIM_EVENT_6
06377   *         @arg @ref LL_HRTIM_EVENT_7
06378   *         @arg @ref LL_HRTIM_EVENT_8
06379   *         @arg @ref LL_HRTIM_EVENT_9
06380   *         @arg @ref LL_HRTIM_EVENT_10
06381   * @param  Configuration This parameter must be a combination of all the following values:
06382   *         @arg @ref LL_HRTIM_EE_SRC_1 or @ref LL_HRTIM_EE_SRC_2 or @ref LL_HRTIM_EE_SRC_3 or @ref LL_HRTIM_EE_SRC_4
06383   *         @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW
06384   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
06385   *         @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE
06386   * @retval None
06387   */
06388 __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration)
06389 {
06390   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06391   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06392                                                     REG_OFFSET_TAB_EECR[iEvent]));
06393   MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]),
06394              (Configuration << REG_SHIFT_TAB_EExSRC[iEvent]));
06395 }
06396
06397 /**
06398   * @brief  Set the external event source.
06399   * @rmtoll EECR1     EE1SRC          LL_HRTIM_EE_SetSrc\n
06400   *         EECR1     EE2SRC          LL_HRTIM_EE_SetSrc\n
06401   *         EECR1     EE3SRC          LL_HRTIM_EE_SetSrc\n
06402   *         EECR1     EE4SRC          LL_HRTIM_EE_SetSrc\n
06403   *         EECR1     EE5SRC          LL_HRTIM_EE_SetSrc\n
06404   *         EECR2     EE6SRC          LL_HRTIM_EE_SetSrc\n
06405   *         EECR2     EE7SRC          LL_HRTIM_EE_SetSrc\n
06406   *         EECR2     EE8SRC          LL_HRTIM_EE_SetSrc\n
06407   *         EECR2     EE9SRC          LL_HRTIM_EE_SetSrc\n
06408   *         EECR2     EE10SRC         LL_HRTIM_EE_SetSrc
06409   * @param  HRTIMx High Resolution Timer instance
06410   * @param  Event This parameter can be one of the following values:
06411   *         @arg @ref LL_HRTIM_EVENT_1
06412   *         @arg @ref LL_HRTIM_EVENT_2
06413   *         @arg @ref LL_HRTIM_EVENT_3
06414   *         @arg @ref LL_HRTIM_EVENT_4
06415   *         @arg @ref LL_HRTIM_EVENT_5
06416   *         @arg @ref LL_HRTIM_EVENT_6
06417   *         @arg @ref LL_HRTIM_EVENT_7
06418   *         @arg @ref LL_HRTIM_EVENT_8
06419   *         @arg @ref LL_HRTIM_EVENT_9
06420   *         @arg @ref LL_HRTIM_EVENT_10
06421   * @param  Src This parameter can be one of the following values:
06422   *         @arg @ref LL_HRTIM_EE_SRC_1
06423   *         @arg @ref LL_HRTIM_EE_SRC_2
06424   *         @arg @ref LL_HRTIM_EE_SRC_3
06425   *         @arg @ref LL_HRTIM_EE_SRC_4
06426   * @retval None
06427   */
06428 __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src)
06429 {
06430   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06431   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06432                                                     REG_OFFSET_TAB_EECR[iEvent]));
06433   MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent]));
06434 }
06435
06436 /**
06437   * @brief  Get actual external event source.
06438   * @rmtoll EECR1     EE1SRC          LL_HRTIM_EE_GetSrc\n
06439   *         EECR1     EE2SRC          LL_HRTIM_EE_GetSrc\n
06440   *         EECR1     EE3SRC          LL_HRTIM_EE_GetSrc\n
06441   *         EECR1     EE4SRC          LL_HRTIM_EE_GetSrc\n
06442   *         EECR1     EE5SRC          LL_HRTIM_EE_GetSrc\n
06443   *         EECR2     EE6SRC          LL_HRTIM_EE_GetSrc\n
06444   *         EECR2     EE7SRC          LL_HRTIM_EE_GetSrc\n
06445   *         EECR2     EE8SRC          LL_HRTIM_EE_GetSrc\n
06446   *         EECR2     EE9SRC          LL_HRTIM_EE_GetSrc\n
06447   *         EECR2     EE10SRC         LL_HRTIM_EE_GetSrc
06448   * @param  HRTIMx High Resolution Timer instance
06449   * @param  Event This parameter can be one of the following values:
06450   *         @arg @ref LL_HRTIM_EVENT_1
06451   *         @arg @ref LL_HRTIM_EVENT_2
06452   *         @arg @ref LL_HRTIM_EVENT_3
06453   *         @arg @ref LL_HRTIM_EVENT_4
06454   *         @arg @ref LL_HRTIM_EVENT_5
06455   *         @arg @ref LL_HRTIM_EVENT_6
06456   *         @arg @ref LL_HRTIM_EVENT_7
06457   *         @arg @ref LL_HRTIM_EVENT_8
06458   *         @arg @ref LL_HRTIM_EVENT_9
06459   *         @arg @ref LL_HRTIM_EVENT_10
06460   * @retval EventSrc This parameter can be one of the following values:
06461   *         @arg @ref LL_HRTIM_EE_SRC_1
06462   *         @arg @ref LL_HRTIM_EE_SRC_2
06463   *         @arg @ref LL_HRTIM_EE_SRC_3
06464   *         @arg @ref LL_HRTIM_EE_SRC_4
06465   */
06466 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event)
06467 {
06468   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06469   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06470                                                     REG_OFFSET_TAB_EECR[iEvent]));
06471   return (READ_BIT(*pReg, HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
06472 }
06473
06474 /**
06475   * @brief  Set the polarity of an external event.
06476   * @rmtoll EECR1     EE1POL          LL_HRTIM_EE_SetPolarity\n
06477   *         EECR1     EE2POL          LL_HRTIM_EE_SetPolarity\n
06478   *         EECR1     EE3POL          LL_HRTIM_EE_SetPolarity\n
06479   *         EECR1     EE4POL          LL_HRTIM_EE_SetPolarity\n
06480   *         EECR1     EE5POL          LL_HRTIM_EE_SetPolarity\n
06481   *         EECR2     EE6POL          LL_HRTIM_EE_SetPolarity\n
06482   *         EECR2     EE7POL          LL_HRTIM_EE_SetPolarity\n
06483   *         EECR2     EE8POL          LL_HRTIM_EE_SetPolarity\n
06484   *         EECR2     EE9POL          LL_HRTIM_EE_SetPolarity\n
06485   *         EECR2     EE10POL         LL_HRTIM_EE_SetPolarity
06486   * @note This function must not be called when the timer counter is enabled.
06487   * @note Event polarity is only significant when event detection is level-sensitive.
06488   * @param  HRTIMx High Resolution Timer instance
06489   * @param  Event This parameter can be one of the following values:
06490   *         @arg @ref LL_HRTIM_EVENT_1
06491   *         @arg @ref LL_HRTIM_EVENT_2
06492   *         @arg @ref LL_HRTIM_EVENT_3
06493   *         @arg @ref LL_HRTIM_EVENT_4
06494   *         @arg @ref LL_HRTIM_EVENT_5
06495   *         @arg @ref LL_HRTIM_EVENT_6
06496   *         @arg @ref LL_HRTIM_EVENT_7
06497   *         @arg @ref LL_HRTIM_EVENT_8
06498   *         @arg @ref LL_HRTIM_EVENT_9
06499   *         @arg @ref LL_HRTIM_EVENT_10
06500   * @param  Polarity This parameter can be one of the following values:
06501   *         @arg @ref LL_HRTIM_EE_POLARITY_HIGH
06502   *         @arg @ref LL_HRTIM_EE_POLARITY_LOW
06503   * @retval None
06504   */
06505 __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity)
06506 {
06507   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06508   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06509                                                     REG_OFFSET_TAB_EECR[iEvent]));
06510   MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent]));
06511 }
06512
06513 /**
06514   * @brief  Get actual polarity setting of an external event.
06515   * @rmtoll EECR1     EE1POL          LL_HRTIM_EE_GetPolarity\n
06516   *         EECR1     EE2POL          LL_HRTIM_EE_GetPolarity\n
06517   *         EECR1     EE3POL          LL_HRTIM_EE_GetPolarity\n
06518   *         EECR1     EE4POL          LL_HRTIM_EE_GetPolarity\n
06519   *         EECR1     EE5POL          LL_HRTIM_EE_GetPolarity\n
06520   *         EECR2     EE6POL          LL_HRTIM_EE_GetPolarity\n
06521   *         EECR2     EE7POL          LL_HRTIM_EE_GetPolarity\n
06522   *         EECR2     EE8POL          LL_HRTIM_EE_GetPolarity\n
06523   *         EECR2     EE9POL          LL_HRTIM_EE_GetPolarity\n
06524   *         EECR2     EE10POL         LL_HRTIM_EE_GetPolarity
06525   * @param  HRTIMx High Resolution Timer instance
06526   * @param  Event This parameter can be one of the following values:
06527   *         @arg @ref LL_HRTIM_EVENT_1
06528   *         @arg @ref LL_HRTIM_EVENT_2
06529   *         @arg @ref LL_HRTIM_EVENT_3
06530   *         @arg @ref LL_HRTIM_EVENT_4
06531   *         @arg @ref LL_HRTIM_EVENT_5
06532   *         @arg @ref LL_HRTIM_EVENT_6
06533   *         @arg @ref LL_HRTIM_EVENT_7
06534   *         @arg @ref LL_HRTIM_EVENT_8
06535   *         @arg @ref LL_HRTIM_EVENT_9
06536   *         @arg @ref LL_HRTIM_EVENT_10
06537   * @retval Polarity This parameter can be one of the following values:
06538   *         @arg @ref LL_HRTIM_EE_POLARITY_HIGH
06539   *         @arg @ref LL_HRTIM_EE_POLARITY_LOW
06540   */
06541 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
06542 {
06543   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06544   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06545                                                     REG_OFFSET_TAB_EECR[iEvent]));
06546   return (READ_BIT(*pReg, HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
06547 }
06548
06549 /**
06550   * @brief  Set the sensitivity of an external event.
06551   * @rmtoll EECR1     EE1SNS          LL_HRTIM_EE_SetSensitivity\n
06552   *         EECR1     EE2SNS          LL_HRTIM_EE_SetSensitivity\n
06553   *         EECR1     EE3SNS          LL_HRTIM_EE_SetSensitivity\n
06554   *         EECR1     EE4SNS          LL_HRTIM_EE_SetSensitivity\n
06555   *         EECR1     EE5SNS          LL_HRTIM_EE_SetSensitivity\n
06556   *         EECR2     EE6SNS          LL_HRTIM_EE_SetSensitivity\n
06557   *         EECR2     EE7SNS          LL_HRTIM_EE_SetSensitivity\n
06558   *         EECR2     EE8SNS          LL_HRTIM_EE_SetSensitivity\n
06559   *         EECR2     EE9SNS          LL_HRTIM_EE_SetSensitivity\n
06560   *         EECR2     EE10SNS         LL_HRTIM_EE_SetSensitivity
06561   * @param  HRTIMx High Resolution Timer instance
06562   * @param  Event This parameter can be one of the following values:
06563   *         @arg @ref LL_HRTIM_EVENT_1
06564   *         @arg @ref LL_HRTIM_EVENT_2
06565   *         @arg @ref LL_HRTIM_EVENT_3
06566   *         @arg @ref LL_HRTIM_EVENT_4
06567   *         @arg @ref LL_HRTIM_EVENT_5
06568   *         @arg @ref LL_HRTIM_EVENT_6
06569   *         @arg @ref LL_HRTIM_EVENT_7
06570   *         @arg @ref LL_HRTIM_EVENT_8
06571   *         @arg @ref LL_HRTIM_EVENT_9
06572   *         @arg @ref LL_HRTIM_EVENT_10
06573   * @param  Sensitivity This parameter can be one of the following values:
06574   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
06575   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
06576   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
06577   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
06578   * @retval None
06579   */
06580
06581 __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity)
06582 {
06583   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06584   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06585                                                     REG_OFFSET_TAB_EECR[iEvent]));
06586   MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent]));
06587 }
06588
06589 /**
06590   * @brief  Get actual sensitivity setting of an external event.
06591   * @rmtoll EECR1     EE1SNS          LL_HRTIM_EE_GetSensitivity\n
06592   *         EECR1     EE2SNS          LL_HRTIM_EE_GetSensitivity\n
06593   *         EECR1     EE3SNS          LL_HRTIM_EE_GetSensitivity\n
06594   *         EECR1     EE4SNS          LL_HRTIM_EE_GetSensitivity\n
06595   *         EECR1     EE5SNS          LL_HRTIM_EE_GetSensitivity\n
06596   *         EECR2     EE6SNS          LL_HRTIM_EE_GetSensitivity\n
06597   *         EECR2     EE7SNS          LL_HRTIM_EE_GetSensitivity\n
06598   *         EECR2     EE8SNS          LL_HRTIM_EE_GetSensitivity\n
06599   *         EECR2     EE9SNS          LL_HRTIM_EE_GetSensitivity\n
06600   *         EECR2     EE10SNS         LL_HRTIM_EE_GetSensitivity
06601   * @param  HRTIMx High Resolution Timer instance
06602   * @param  Event This parameter can be one of the following values:
06603   *         @arg @ref LL_HRTIM_EVENT_1
06604   *         @arg @ref LL_HRTIM_EVENT_2
06605   *         @arg @ref LL_HRTIM_EVENT_3
06606   *         @arg @ref LL_HRTIM_EVENT_4
06607   *         @arg @ref LL_HRTIM_EVENT_5
06608   *         @arg @ref LL_HRTIM_EVENT_6
06609   *         @arg @ref LL_HRTIM_EVENT_7
06610   *         @arg @ref LL_HRTIM_EVENT_8
06611   *         @arg @ref LL_HRTIM_EVENT_9
06612   *         @arg @ref LL_HRTIM_EVENT_10
06613   * @retval Polarity This parameter can be one of the following values:
06614   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
06615   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
06616   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
06617   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
06618   */
06619 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
06620 {
06621   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06622   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06623                                                     REG_OFFSET_TAB_EECR[iEvent]));
06624   return (READ_BIT(*pReg, HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
06625 }
06626
06627 /**
06628   * @brief  Set the fast mode of an external event.
06629   * @rmtoll EECR1     EE1FAST         LL_HRTIM_EE_SetFastMode\n
06630   *         EECR1     EE2FAST         LL_HRTIM_EE_SetFastMode\n
06631   *         EECR1     EE3FAST         LL_HRTIM_EE_SetFastMode\n
06632   *         EECR1     EE4FAST         LL_HRTIM_EE_SetFastMode\n
06633   *         EECR1     EE5FAST         LL_HRTIM_EE_SetFastMode\n
06634   *         EECR2     EE6FAST         LL_HRTIM_EE_SetFastMode\n
06635   *         EECR2     EE7FAST         LL_HRTIM_EE_SetFastMode\n
06636   *         EECR2     EE8FAST         LL_HRTIM_EE_SetFastMode\n
06637   *         EECR2     EE9FAST         LL_HRTIM_EE_SetFastMode\n
06638   *         EECR2     EE10FAST        LL_HRTIM_EE_SetFastMode
06639   * @note This function must not be called when the timer counter is enabled.
06640   * @param  HRTIMx High Resolution Timer instance
06641   * @param  Event This parameter can be one of the following values:
06642   *         @arg @ref LL_HRTIM_EVENT_1
06643   *         @arg @ref LL_HRTIM_EVENT_2
06644   *         @arg @ref LL_HRTIM_EVENT_3
06645   *         @arg @ref LL_HRTIM_EVENT_4
06646   *         @arg @ref LL_HRTIM_EVENT_5
06647   * @param  FastMode This parameter can be one of the following values:
06648   *         @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
06649   *         @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
06650   * @retval None
06651   */
06652 __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode)
06653 {
06654   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06655   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06656                                                     REG_OFFSET_TAB_EECR[iEvent]));
06657   MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent]));
06658 }
06659
06660 /**
06661   * @brief  Get actual fast mode setting of an external event.
06662   * @rmtoll EECR1     EE1FAST         LL_HRTIM_EE_GetFastMode\n
06663   *         EECR1     EE2FAST         LL_HRTIM_EE_GetFastMode\n
06664   *         EECR1     EE3FAST         LL_HRTIM_EE_GetFastMode\n
06665   *         EECR1     EE4FAST         LL_HRTIM_EE_GetFastMode\n
06666   *         EECR1     EE5FAST         LL_HRTIM_EE_GetFastMode\n
06667   *         EECR2     EE6FAST         LL_HRTIM_EE_GetFastMode\n
06668   *         EECR2     EE7FAST         LL_HRTIM_EE_GetFastMode\n
06669   *         EECR2     EE8FAST         LL_HRTIM_EE_GetFastMode\n
06670   *         EECR2     EE9FAST         LL_HRTIM_EE_GetFastMode\n
06671   *         EECR2     EE10FAST        LL_HRTIM_EE_GetFastMode
06672   * @param  HRTIMx High Resolution Timer instance
06673   * @param  Event This parameter can be one of the following values:
06674   *         @arg @ref LL_HRTIM_EVENT_1
06675   *         @arg @ref LL_HRTIM_EVENT_2
06676   *         @arg @ref LL_HRTIM_EVENT_3
06677   *         @arg @ref LL_HRTIM_EVENT_4
06678   *         @arg @ref LL_HRTIM_EVENT_5
06679   * @retval FastMode This parameter can be one of the following values:
06680   *         @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
06681   *         @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
06682   */
06683 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event)
06684 {
06685   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06686   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06687                                                     REG_OFFSET_TAB_EECR[iEvent]));
06688   return (READ_BIT(*pReg, HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
06689 }
06690
06691 /**
06692   * @brief  Set the digital noise filter of a external event.
06693   * @rmtoll EECR3     EE6F         LL_HRTIM_EE_SetFilter\n
06694   *         EECR3     EE7F         LL_HRTIM_EE_SetFilter\n
06695   *         EECR3     EE8F         LL_HRTIM_EE_SetFilter\n
06696   *         EECR3     EE9F         LL_HRTIM_EE_SetFilter\n
06697   *         EECR3     EE10F        LL_HRTIM_EE_SetFilter
06698   * @param  HRTIMx High Resolution Timer instance
06699   * @param  Event This parameter can be one of the following values:
06700   *         @arg @ref LL_HRTIM_EVENT_6
06701   *         @arg @ref LL_HRTIM_EVENT_7
06702   *         @arg @ref LL_HRTIM_EVENT_8
06703   *         @arg @ref LL_HRTIM_EVENT_9
06704   *         @arg @ref LL_HRTIM_EVENT_10
06705   * @param  Filter This parameter can be one of the following values:
06706   *         @arg @ref LL_HRTIM_EE_FILTER_NONE
06707   *         @arg @ref LL_HRTIM_EE_FILTER_1
06708   *         @arg @ref LL_HRTIM_EE_FILTER_2
06709   *         @arg @ref LL_HRTIM_EE_FILTER_3
06710   *         @arg @ref LL_HRTIM_EE_FILTER_4
06711   *         @arg @ref LL_HRTIM_EE_FILTER_5
06712   *         @arg @ref LL_HRTIM_EE_FILTER_6
06713   *         @arg @ref LL_HRTIM_EE_FILTER_7
06714   *         @arg @ref LL_HRTIM_EE_FILTER_8
06715   *         @arg @ref LL_HRTIM_EE_FILTER_9
06716   *         @arg @ref LL_HRTIM_EE_FILTER_10
06717   *         @arg @ref LL_HRTIM_EE_FILTER_11
06718   *         @arg @ref LL_HRTIM_EE_FILTER_12
06719   *         @arg @ref LL_HRTIM_EE_FILTER_13
06720   *         @arg @ref LL_HRTIM_EE_FILTER_14
06721   *         @arg @ref LL_HRTIM_EE_FILTER_15
06722   * @retval None
06723   */
06724 __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter)
06725 {
06726   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06727   MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]),
06728              (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
06729 }
06730
06731 /**
06732   * @brief  Get actual digital noise filter setting of a external event.
06733   * @rmtoll EECR3     EE6F         LL_HRTIM_EE_GetFilter\n
06734   *         EECR3     EE7F         LL_HRTIM_EE_GetFilter\n
06735   *         EECR3     EE8F         LL_HRTIM_EE_GetFilter\n
06736   *         EECR3     EE9F         LL_HRTIM_EE_GetFilter\n
06737   *         EECR3     EE10F        LL_HRTIM_EE_GetFilter
06738   * @param  HRTIMx High Resolution Timer instance
06739   * @param  Event This parameter can be one of the following values:
06740   *         @arg @ref LL_HRTIM_EVENT_6
06741   *         @arg @ref LL_HRTIM_EVENT_7
06742   *         @arg @ref LL_HRTIM_EVENT_8
06743   *         @arg @ref LL_HRTIM_EVENT_9
06744   *         @arg @ref LL_HRTIM_EVENT_10
06745   * @retval Filter This parameter can be one of the following values:
06746   *         @arg @ref LL_HRTIM_EE_FILTER_NONE
06747   *         @arg @ref LL_HRTIM_EE_FILTER_1
06748   *         @arg @ref LL_HRTIM_EE_FILTER_2
06749   *         @arg @ref LL_HRTIM_EE_FILTER_3
06750   *         @arg @ref LL_HRTIM_EE_FILTER_4
06751   *         @arg @ref LL_HRTIM_EE_FILTER_5
06752   *         @arg @ref LL_HRTIM_EE_FILTER_6
06753   *         @arg @ref LL_HRTIM_EE_FILTER_7
06754   *         @arg @ref LL_HRTIM_EE_FILTER_8
06755   *         @arg @ref LL_HRTIM_EE_FILTER_9
06756   *         @arg @ref LL_HRTIM_EE_FILTER_10
06757   *         @arg @ref LL_HRTIM_EE_FILTER_11
06758   *         @arg @ref LL_HRTIM_EE_FILTER_12
06759   *         @arg @ref LL_HRTIM_EE_FILTER_13
06760   *         @arg @ref LL_HRTIM_EE_FILTER_14
06761   *         @arg @ref LL_HRTIM_EE_FILTER_15
06762   */
06763 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event)
06764 {
06765   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6));
06766   return (READ_BIT(HRTIMx->sCommonRegs.EECR3,
06767                    (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent])) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
06768 }
06769
06770 /**
06771   * @brief  Set the external event prescaler.
06772   * @rmtoll EECR3     EEVSD        LL_HRTIM_EE_SetPrescaler
06773   * @param  HRTIMx High Resolution Timer instance
06774   * @param  Prescaler This parameter can be one of the following values:
06775   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
06776   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
06777   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
06778   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
06779   * @retval None
06780   */
06781
06782 __STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
06783 {
06784   MODIFY_REG(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, Prescaler);
06785 }
06786
06787 /**
06788   * @brief  Get actual external event prescaler setting.
06789   * @rmtoll EECR3     EEVSD        LL_HRTIM_EE_GetPrescaler
06790   * @param  HRTIMx High Resolution Timer instance
06791   * @retval Prescaler This parameter can be one of the following values:
06792   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
06793   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
06794   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
06795   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
06796   */
06797
06798 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef *HRTIMx)
06799 {
06800   return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD));
06801 }
06802
06803 /**
06804   * @}
06805   */
06806
06807 /** @defgroup HRTIM_EF_Fault_management Fault_management
06808   * @{
06809   */
06810
06811 /**
06812   * @brief  Configure fault signal conditioning.
06813   * @rmtoll FLTINR1     FLT1P        LL_HRTIM_FLT_Config\n
06814   *         FLTINR1     FLT1SRC      LL_HRTIM_FLT_Config\n
06815   *         FLTINR1     FLT2P        LL_HRTIM_FLT_Config\n
06816   *         FLTINR1     FLT2SRC      LL_HRTIM_FLT_Config\n
06817   *         FLTINR1     FLT3P        LL_HRTIM_FLT_Config\n
06818   *         FLTINR1     FLT3SRC      LL_HRTIM_FLT_Config\n
06819   *         FLTINR1     FLT4P        LL_HRTIM_FLT_Config\n
06820   *         FLTINR1     FLT4SRC      LL_HRTIM_FLT_Config\n
06821   *         FLTINR2     FLT5P        LL_HRTIM_FLT_Config\n
06822   *         FLTINR2     FLT5SRC      LL_HRTIM_FLT_Config
06823   * @note This function must not be called when the fault channel is enabled.
06824   * @param  HRTIMx High Resolution Timer instance
06825   * @param  Fault This parameter can be one of the following values:
06826   *         @arg @ref LL_HRTIM_FAULT_1
06827   *         @arg @ref LL_HRTIM_FAULT_2
06828   *         @arg @ref LL_HRTIM_FAULT_3
06829   *         @arg @ref LL_HRTIM_FAULT_4
06830   *         @arg @ref LL_HRTIM_FAULT_5
06831   * @param  Configuration This parameter must be a combination of all the following values:
06832   *         @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT or @ref LL_HRTIM_FLT_SRC_INTERNAL
06833   *         @arg @ref LL_HRTIM_FLT_POLARITY_LOW or @ref LL_HRTIM_FLT_POLARITY_HIGH
06834   * @retval None
06835   */
06836 __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration)
06837 {
06838   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
06839   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
06840                                                     REG_OFFSET_TAB_FLTINR[iFault]));
06841   MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]),
06842              (Configuration << REG_SHIFT_TAB_FLTxE[iFault]));
06843 }
06844
06845 /**
06846   * @brief  Set the source of a fault signal.
06847   * @rmtoll FLTINR1     FLT1SRC      LL_HRTIM_FLT_SetSrc\n
06848   *         FLTINR1     FLT2SRC      LL_HRTIM_FLT_SetSrc\n
06849   *         FLTINR1     FLT3SRC      LL_HRTIM_FLT_SetSrc\n
06850   *         FLTINR1     FLT4SRC      LL_HRTIM_FLT_SetSrc\n
06851   *         FLTINR2     FLT5SRC      LL_HRTIM_FLT_SetSrc
06852   * @note This function must not be called when the fault channel is enabled.
06853   * @param  HRTIMx High Resolution Timer instance
06854   * @param  Fault This parameter can be one of the following values:
06855   *         @arg @ref LL_HRTIM_FAULT_1
06856   *         @arg @ref LL_HRTIM_FAULT_2
06857   *         @arg @ref LL_HRTIM_FAULT_3
06858   *         @arg @ref LL_HRTIM_FAULT_4
06859   *         @arg @ref LL_HRTIM_FAULT_5
06860   * @param  Src This parameter can be one of the following values:
06861   *         @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
06862   *         @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
06863   * @retval None
06864   */
06865 __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src)
06866 {
06867   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
06868   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
06869                                                     REG_OFFSET_TAB_FLTINR[iFault]));
06870   MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault]));
06871 }
06872
06873 /**
06874   * @brief  Get actual source of a fault signal.
06875   * @rmtoll FLTINR1     FLT1SRC      LL_HRTIM_FLT_GetSrc\n
06876   *         FLTINR1     FLT2SRC      LL_HRTIM_FLT_GetSrc\n
06877   *         FLTINR1     FLT3SRC      LL_HRTIM_FLT_GetSrc\n
06878   *         FLTINR1     FLT4SRC      LL_HRTIM_FLT_GetSrc\n
06879   *         FLTINR2     FLT5SRC      LL_HRTIM_FLT_GetSrc
06880   * @param  HRTIMx High Resolution Timer instance
06881   * @param  Fault This parameter can be one of the following values:
06882   *         @arg @ref LL_HRTIM_FAULT_1
06883   *         @arg @ref LL_HRTIM_FAULT_2
06884   *         @arg @ref LL_HRTIM_FAULT_3
06885   *         @arg @ref LL_HRTIM_FAULT_4
06886   *         @arg @ref LL_HRTIM_FAULT_5
06887   * @retval Src This parameter can be one of the following values:
06888   *         @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
06889   *         @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
06890   */
06891 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
06892 {
06893   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
06894   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
06895                                                     REG_OFFSET_TAB_FLTINR[iFault]));
06896   return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >>  REG_SHIFT_TAB_FLTxE[iFault]);
06897 }
06898
06899 /**
06900   * @brief  Set the polarity of a fault signal.
06901   * @rmtoll FLTINR1     FLT1P        LL_HRTIM_FLT_SetPolarity\n
06902   *         FLTINR1     FLT2P        LL_HRTIM_FLT_SetPolarity\n
06903   *         FLTINR1     FLT3P        LL_HRTIM_FLT_SetPolarity\n
06904   *         FLTINR1     FLT4P        LL_HRTIM_FLT_SetPolarity\n
06905   *         FLTINR2     FLT5P        LL_HRTIM_FLT_SetPolarity
06906   * @note This function must not be called when the fault channel is enabled.
06907   * @param  HRTIMx High Resolution Timer instance
06908   * @param  Fault This parameter can be one of the following values:
06909   *         @arg @ref LL_HRTIM_FAULT_1
06910   *         @arg @ref LL_HRTIM_FAULT_2
06911   *         @arg @ref LL_HRTIM_FAULT_3
06912   *         @arg @ref LL_HRTIM_FAULT_4
06913   *         @arg @ref LL_HRTIM_FAULT_5
06914   * @param  Polarity This parameter can be one of the following values:
06915   *         @arg @ref LL_HRTIM_FLT_POLARITY_LOW
06916   *         @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
06917   * @retval None
06918   */
06919 __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity)
06920 {
06921   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
06922   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
06923                                                     REG_OFFSET_TAB_FLTINR[iFault]));
06924   MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault]));
06925 }
06926
06927 /**
06928   * @brief  Get actual polarity of a fault signal.
06929   * @rmtoll FLTINR1     FLT1P        LL_HRTIM_FLT_GetPolarity\n
06930   *         FLTINR1     FLT2P        LL_HRTIM_FLT_GetPolarity\n
06931   *         FLTINR1     FLT3P        LL_HRTIM_FLT_GetPolarity\n
06932   *         FLTINR1     FLT4P        LL_HRTIM_FLT_GetPolarity\n
06933   *         FLTINR2     FLT5P        LL_HRTIM_FLT_GetPolarity
06934   * @param  HRTIMx High Resolution Timer instance
06935   * @param  Fault This parameter can be one of the following values:
06936   *         @arg @ref LL_HRTIM_FAULT_1
06937   *         @arg @ref LL_HRTIM_FAULT_2
06938   *         @arg @ref LL_HRTIM_FAULT_3
06939   *         @arg @ref LL_HRTIM_FAULT_4
06940   *         @arg @ref LL_HRTIM_FAULT_5
06941   * @retval Polarity This parameter can be one of the following values:
06942   *         @arg @ref LL_HRTIM_FLT_POLARITY_LOW
06943   *         @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
06944   */
06945 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
06946 {
06947   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
06948   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
06949                                                     REG_OFFSET_TAB_FLTINR[iFault]));
06950   return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >>  REG_SHIFT_TAB_FLTxE[iFault]);
06951 }
06952
06953 /**
06954   * @brief  Set the digital noise filter of a fault signal.
06955   * @rmtoll FLTINR1     FLT1F      LL_HRTIM_FLT_SetFilter\n
06956   *         FLTINR1     FLT2F      LL_HRTIM_FLT_SetFilter\n
06957   *         FLTINR1     FLT3F      LL_HRTIM_FLT_SetFilter\n
06958   *         FLTINR1     FLT4F      LL_HRTIM_FLT_SetFilter\n
06959   *         FLTINR2     FLT5F      LL_HRTIM_FLT_SetFilter
06960   * @note This function must not be called when the fault channel is enabled.
06961   * @param  HRTIMx High Resolution Timer instance
06962   * @param  Fault This parameter can be one of the following values:
06963   *         @arg @ref LL_HRTIM_FAULT_1
06964   *         @arg @ref LL_HRTIM_FAULT_2
06965   *         @arg @ref LL_HRTIM_FAULT_3
06966   *         @arg @ref LL_HRTIM_FAULT_4
06967   *         @arg @ref LL_HRTIM_FAULT_5
06968   * @param  Filter This parameter can be one of the following values:
06969   *         @arg @ref LL_HRTIM_FLT_FILTER_NONE
06970   *         @arg @ref LL_HRTIM_FLT_FILTER_1
06971   *         @arg @ref LL_HRTIM_FLT_FILTER_2
06972   *         @arg @ref LL_HRTIM_FLT_FILTER_3
06973   *         @arg @ref LL_HRTIM_FLT_FILTER_4
06974   *         @arg @ref LL_HRTIM_FLT_FILTER_5
06975   *         @arg @ref LL_HRTIM_FLT_FILTER_6
06976   *         @arg @ref LL_HRTIM_FLT_FILTER_7
06977   *         @arg @ref LL_HRTIM_FLT_FILTER_8
06978   *         @arg @ref LL_HRTIM_FLT_FILTER_9
06979   *         @arg @ref LL_HRTIM_FLT_FILTER_10
06980   *         @arg @ref LL_HRTIM_FLT_FILTER_11
06981   *         @arg @ref LL_HRTIM_FLT_FILTER_12
06982   *         @arg @ref LL_HRTIM_FLT_FILTER_13
06983   *         @arg @ref LL_HRTIM_FLT_FILTER_14
06984   *         @arg @ref LL_HRTIM_FLT_FILTER_15
06985   * @retval None
06986   */
06987 __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter)
06988 {
06989   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
06990   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
06991                                                     REG_OFFSET_TAB_FLTINR[iFault]));
06992   MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault]));
06993 }
06994
06995 /**
06996   * @brief  Get actual digital noise filter setting of a fault signal.
06997   * @rmtoll FLTINR1     FLT1F      LL_HRTIM_FLT_GetFilter\n
06998   *         FLTINR1     FLT2F      LL_HRTIM_FLT_GetFilter\n
06999   *         FLTINR1     FLT3F      LL_HRTIM_FLT_GetFilter\n
07000   *         FLTINR1     FLT4F      LL_HRTIM_FLT_GetFilter\n
07001   *         FLTINR2     FLT5F      LL_HRTIM_FLT_GetFilter
07002   * @param  HRTIMx High Resolution Timer instance
07003   * @param  Fault This parameter can be one of the following values:
07004   *         @arg @ref LL_HRTIM_FAULT_1
07005   *         @arg @ref LL_HRTIM_FAULT_2
07006   *         @arg @ref LL_HRTIM_FAULT_3
07007   *         @arg @ref LL_HRTIM_FAULT_4
07008   *         @arg @ref LL_HRTIM_FAULT_5
07009   * @retval Filter This parameter can be one of the following values:
07010   *         @arg @ref LL_HRTIM_FLT_FILTER_NONE
07011   *         @arg @ref LL_HRTIM_FLT_FILTER_1
07012   *         @arg @ref LL_HRTIM_FLT_FILTER_2
07013   *         @arg @ref LL_HRTIM_FLT_FILTER_3
07014   *         @arg @ref LL_HRTIM_FLT_FILTER_4
07015   *         @arg @ref LL_HRTIM_FLT_FILTER_5
07016   *         @arg @ref LL_HRTIM_FLT_FILTER_6
07017   *         @arg @ref LL_HRTIM_FLT_FILTER_7
07018   *         @arg @ref LL_HRTIM_FLT_FILTER_8
07019   *         @arg @ref LL_HRTIM_FLT_FILTER_9
07020   *         @arg @ref LL_HRTIM_FLT_FILTER_10
07021   *         @arg @ref LL_HRTIM_FLT_FILTER_11
07022   *         @arg @ref LL_HRTIM_FLT_FILTER_12
07023   *         @arg @ref LL_HRTIM_FLT_FILTER_13
07024   *         @arg @ref LL_HRTIM_FLT_FILTER_14
07025   *         @arg @ref LL_HRTIM_FLT_FILTER_15
07026   */
07027 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
07028 {
07029   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
07030   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
07031                                                     REG_OFFSET_TAB_FLTINR[iFault]));
07032   return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >>  REG_SHIFT_TAB_FLTxE[iFault]);
07033 }
07034
07035 /**
07036   * @brief  Set the fault circuitry prescaler.
07037   * @rmtoll FLTINR2     FLTSD      LL_HRTIM_FLT_SetPrescaler
07038   * @param  HRTIMx High Resolution Timer instance
07039   * @param  Prescaler This parameter can be one of the following values:
07040   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
07041   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
07042   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
07043   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
07044   * @retval None
07045   */
07046 __STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
07047 {
07048   MODIFY_REG(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, Prescaler);
07049 }
07050
07051 /**
07052   * @brief  Get actual fault circuitry prescaler setting.
07053   * @rmtoll FLTINR2     FLTSD      LL_HRTIM_FLT_GetPrescaler
07054   * @param  HRTIMx High Resolution Timer instance
07055   * @retval Prescaler This parameter can be one of the following values:
07056   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
07057   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
07058   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
07059   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
07060   */
07061 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef *HRTIMx)
07062 {
07063   return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD));
07064
07065 }
07066
07067 /**
07068   * @brief  Lock the fault signal conditioning settings.
07069   * @rmtoll FLTINR1     FLT1LCK      LL_HRTIM_FLT_Lock\n
07070   *         FLTINR1     FLT2LCK      LL_HRTIM_FLT_Lock\n
07071   *         FLTINR1     FLT3LCK      LL_HRTIM_FLT_Lock\n
07072   *         FLTINR1     FLT4LCK      LL_HRTIM_FLT_Lock\n
07073   *         FLTINR2     FLT5LCK      LL_HRTIM_FLT_Lock
07074   * @param  HRTIMx High Resolution Timer instance
07075   * @param  Fault This parameter can be one of the following values:
07076   *         @arg @ref LL_HRTIM_FAULT_1
07077   *         @arg @ref LL_HRTIM_FAULT_2
07078   *         @arg @ref LL_HRTIM_FAULT_3
07079   *         @arg @ref LL_HRTIM_FAULT_4
07080   *         @arg @ref LL_HRTIM_FAULT_5
07081   * @retval None
07082   */
07083 __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
07084 {
07085   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
07086   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
07087                                                     REG_OFFSET_TAB_FLTINR[iFault]));
07088   SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault]));
07089 }
07090
07091 /**
07092   * @brief  Enable the fault circuitry for the designated fault input.
07093   * @rmtoll FLTINR1     FLT1E      LL_HRTIM_FLT_Enable\n
07094   *         FLTINR1     FLT2E      LL_HRTIM_FLT_Enable\n
07095   *         FLTINR1     FLT3E      LL_HRTIM_FLT_Enable\n
07096   *         FLTINR1     FLT4E      LL_HRTIM_FLT_Enable\n
07097   *         FLTINR2     FLT5E      LL_HRTIM_FLT_Enable
07098   * @param  HRTIMx High Resolution Timer instance
07099   * @param  Fault This parameter can be one of the following values:
07100   *         @arg @ref LL_HRTIM_FAULT_1
07101   *         @arg @ref LL_HRTIM_FAULT_2
07102   *         @arg @ref LL_HRTIM_FAULT_3
07103   *         @arg @ref LL_HRTIM_FAULT_4
07104   *         @arg @ref LL_HRTIM_FAULT_5
07105   * @retval None
07106   */
07107 __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
07108 {
07109   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
07110   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
07111                                                     REG_OFFSET_TAB_FLTINR[iFault]));
07112   SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
07113 }
07114
07115 /**
07116   * @brief  Disable the fault circuitry for for the designated fault input.
07117   * @rmtoll FLTINR1     FLT1E      LL_HRTIM_FLT_Disable\n
07118   *         FLTINR1     FLT2E      LL_HRTIM_FLT_Disable\n
07119   *         FLTINR1     FLT3E      LL_HRTIM_FLT_Disable\n
07120   *         FLTINR1     FLT4E      LL_HRTIM_FLT_Disable\n
07121   *         FLTINR2     FLT5E      LL_HRTIM_FLT_Disable
07122   * @param  HRTIMx High Resolution Timer instance
07123   * @param  Fault This parameter can be one of the following values:
07124   *         @arg @ref LL_HRTIM_FAULT_1
07125   *         @arg @ref LL_HRTIM_FAULT_2
07126   *         @arg @ref LL_HRTIM_FAULT_3
07127   *         @arg @ref LL_HRTIM_FAULT_4
07128   *         @arg @ref LL_HRTIM_FAULT_5
07129   * @retval None
07130   */
07131 __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
07132 {
07133   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
07134   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
07135                                                     REG_OFFSET_TAB_FLTINR[iFault]));
07136   CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
07137 }
07138
07139 /**
07140   * @brief  Indicate whether the fault circuitry is enabled for a given fault input.
07141   * @rmtoll FLTINR1     FLT1E      LL_HRTIM_FLT_IsEnabled\n
07142   *         FLTINR1     FLT2E      LL_HRTIM_FLT_IsEnabled\n
07143   *         FLTINR1     FLT3E      LL_HRTIM_FLT_IsEnabled\n
07144   *         FLTINR1     FLT4E      LL_HRTIM_FLT_IsEnabled\n
07145   *         FLTINR2     FLT5E      LL_HRTIM_FLT_IsEnabled
07146   * @param  HRTIMx High Resolution Timer instance  * @param  HRTIMx High Resolution Timer instance
07147   * @param  Fault This parameter can be one of the following values:
07148   *         @arg @ref LL_HRTIM_FAULT_1
07149   *         @arg @ref LL_HRTIM_FAULT_2
07150   *         @arg @ref LL_HRTIM_FAULT_3
07151   *         @arg @ref LL_HRTIM_FAULT_4
07152   *         @arg @ref LL_HRTIM_FAULT_5
07153   * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0).
07154   */
07155 __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
07156 {
07157   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
07158   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
07159                                                     REG_OFFSET_TAB_FLTINR[iFault]));
07160   return ((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==
07161           (HRTIM_IER_FLT1));
07162 }
07163
07164 /**
07165   * @}
07166   */
07167
07168 /** @defgroup HRTIM_EF_Burst_Mode_management Burst_Mode_management
07169   * @{
07170   */
07171
07172 /**
07173   * @brief  Configure the burst mode controller.
07174   * @rmtoll BMCR     BMOM        LL_HRTIM_BM_Config\n
07175   *         BMCR     BMCLK       LL_HRTIM_BM_Config\n
07176   *         BMCR     BMPRSC      LL_HRTIM_BM_Config
07177   * @param  HRTIMx High Resolution Timer instance
07178   * @param  Configuration This parameter must be a combination of all the following values:
07179   *         @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS
07180   *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM
07181   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768
07182   * @retval None
07183   */
07184 __STATIC_INLINE void LL_HRTIM_BM_Config(HRTIM_TypeDef *HRTIMx, uint32_t Configuration)
07185 {
07186   MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BM_CONFIG_MASK, Configuration);
07187 }
07188
07189 /**
07190   * @brief  Set the burst mode controller operating mode.
07191   * @rmtoll BMCR     BMOM        LL_HRTIM_BM_SetMode
07192   * @param  HRTIMx High Resolution Timer instance
07193   * @param  Mode This parameter can be one of the following values:
07194   *         @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
07195   *         @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
07196   * @retval None
07197   */
07198 __STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode)
07199 {
07200   MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM, Mode);
07201 }
07202
07203 /**
07204   * @brief  Get actual burst mode controller operating mode.
07205   * @rmtoll BMCR     BMOM        LL_HRTIM_BM_GetMode
07206   * @param  HRTIMx High Resolution Timer instance
07207   * @retval Mode This parameter can be one of the following values:
07208   *         @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
07209   *         @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
07210   */
07211 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(HRTIM_TypeDef *HRTIMx)
07212 {
07213   return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM);
07214 }
07215
07216 /**
07217   * @brief  Set the burst mode controller clock source.
07218   * @rmtoll BMCR     BMCLK       LL_HRTIM_BM_SetClockSrc
07219   * @param  HRTIMx High Resolution Timer instance
07220   * @param  ClockSrc This parameter can be one of the following values:
07221   *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
07222   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
07223   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
07224   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
07225   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
07226   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
07227   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
07228   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
07229   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
07230   *         @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
07231   * @retval None
07232   */
07233 __STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t ClockSrc)
07234 {
07235   MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK, ClockSrc);
07236 }
07237
07238 /**
07239   * @brief  Get actual burst mode controller clock source.
07240   * @rmtoll BMCR     BMCLK       LL_HRTIM_BM_GetClockSrc
07241   * @param  HRTIMx High Resolution Timer instance
07242   * @retval ClockSrc This parameter can be one of the following values:
07243   *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
07244   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
07245   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
07246   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
07247   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
07248   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
07249   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
07250   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
07251   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
07252   *         @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
07253   */
07254 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(HRTIM_TypeDef *HRTIMx)
07255 {
07256   return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK);
07257 }
07258
07259 /**
07260   * @brief  Set the burst mode controller prescaler.
07261   * @rmtoll BMCR     BMPRSC      LL_HRTIM_BM_SetPrescaler
07262   * @param  HRTIMx High Resolution Timer instance
07263   * @param  Prescaler This parameter can be one of the following values:
07264   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
07265   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
07266   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
07267   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
07268   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
07269   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
07270   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
07271   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
07272   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
07273   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
07274   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
07275   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
07276   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
07277   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
07278   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
07279   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
07280   * @retval None
07281   */
07282 __STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
07283 {
07284   MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC, Prescaler);
07285 }
07286
07287 /**
07288   * @brief  Get actual burst mode controller prescaler setting.
07289   * @rmtoll BMCR     BMPRSC      LL_HRTIM_BM_GetPrescaler
07290   * @param  HRTIMx High Resolution Timer instance
07291   * @retval Prescaler This parameter can be one of the following values:
07292   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
07293   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
07294   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
07295   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
07296   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
07297   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
07298   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
07299   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
07300   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
07301   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
07302   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
07303   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
07304   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
07305   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
07306   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
07307   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
07308   */
07309 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(HRTIM_TypeDef *HRTIMx)
07310 {
07311   return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC);
07312 }
07313
07314 /**
07315   * @brief  Enable burst mode compare and period registers preload.
07316   * @rmtoll BMCR     BMPREN      LL_HRTIM_BM_EnablePreload
07317   * @param  HRTIMx High Resolution Timer instance
07318   * @retval None
07319   */
07320 __STATIC_INLINE void LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef *HRTIMx)
07321 {
07322   SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
07323 }
07324
07325 /**
07326   * @brief  Disable burst mode compare and period registers preload.
07327   * @rmtoll BMCR     BMPREN      LL_HRTIM_BM_DisablePreload
07328   * @param  HRTIMx High Resolution Timer instance
07329   * @retval None
07330   */
07331 __STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx)
07332 {
07333   CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
07334 }
07335
07336 /**
07337   * @brief  Indicate whether burst mode compare and period registers are preloaded.
07338   * @rmtoll BMCR     BMPREN      LL_HRTIM_BM_IsEnabledPreload
07339   * @param  HRTIMx High Resolution Timer instance
07340   * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0).
07341   */
07342 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx)
07343 {
07344   return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN) == HRTIM_BMCR_BMPREN);
07345 }
07346
07347 /**
07348   * @brief  Set the burst mode controller trigger
07349   * @rmtoll BMTRGR     SW           LL_HRTIM_BM_SetTrig\n
07350   *         BMTRGR     MSTRST       LL_HRTIM_BM_SetTrig\n
07351   *         BMTRGR     MSTREP       LL_HRTIM_BM_SetTrig\n
07352   *         BMTRGR     MSTCMP1      LL_HRTIM_BM_SetTrig\n
07353   *         BMTRGR     MSTCMP2      LL_HRTIM_BM_SetTrig\n
07354   *         BMTRGR     MSTCMP3      LL_HRTIM_BM_SetTrig\n
07355   *         BMTRGR     MSTCMP4      LL_HRTIM_BM_SetTrig\n
07356   *         BMTRGR     TARST        LL_HRTIM_BM_SetTrig\n
07357   *         BMTRGR     TAREP        LL_HRTIM_BM_SetTrig\n
07358   *         BMTRGR     TACMP1       LL_HRTIM_BM_SetTrig\n
07359   *         BMTRGR     TACMP2       LL_HRTIM_BM_SetTrig\n
07360   *         BMTRGR     TBRST        LL_HRTIM_BM_SetTrig\n
07361   *         BMTRGR     TBREP        LL_HRTIM_BM_SetTrig\n
07362   *         BMTRGR     TBCMP1       LL_HRTIM_BM_SetTrig\n
07363   *         BMTRGR     TBCMP2       LL_HRTIM_BM_SetTrig\n
07364   *         BMTRGR     TCRST        LL_HRTIM_BM_SetTrig\n
07365   *         BMTRGR     TCREP        LL_HRTIM_BM_SetTrig\n
07366   *         BMTRGR     TCCMP1       LL_HRTIM_BM_SetTrig\n
07367   *         BMTRGR     TCCMP2       LL_HRTIM_BM_SetTrig\n
07368   *         BMTRGR     TDRST        LL_HRTIM_BM_SetTrig\n
07369   *         BMTRGR     TDREP        LL_HRTIM_BM_SetTrig\n
07370   *         BMTRGR     TDCMP1       LL_HRTIM_BM_SetTrig\n
07371   *         BMTRGR     TDCMP2       LL_HRTIM_BM_SetTrig\n
07372   *         BMTRGR     TERST        LL_HRTIM_BM_SetTrig\n
07373   *         BMTRGR     TEREP        LL_HRTIM_BM_SetTrig\n
07374   *         BMTRGR     TECMP1       LL_HRTIM_BM_SetTrig\n
07375   *         BMTRGR     TECMP2       LL_HRTIM_BM_SetTrig\n
07376   *         BMTRGR     TAEEV7       LL_HRTIM_BM_SetTrig\n
07377   *         BMTRGR     TAEEV8       LL_HRTIM_BM_SetTrig\n
07378   *         BMTRGR     EEV7         LL_HRTIM_BM_SetTrig\n
07379   *         BMTRGR     EEV8         LL_HRTIM_BM_SetTrig\n
07380   *         BMTRGR     OCHIPEV      LL_HRTIM_BM_SetTrig
07381   * @param  HRTIMx High Resolution Timer instance
07382   * @param  Trig This parameter can be a combination of the following values:
07383   *         @arg @ref LL_HRTIM_BM_TRIG_NONE
07384   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
07385   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
07386   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
07387   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
07388   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
07389   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
07390   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
07391   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
07392   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
07393   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
07394   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
07395   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
07396   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
07397   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
07398   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
07399   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
07400   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
07401   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2
07402   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
07403   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
07404   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1
07405   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
07406   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET
07407   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
07408   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
07409   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
07410   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
07411   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
07412   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
07413   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
07414   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
07415     * @retval None
07416   */
07417 __STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig)
07418 {
07419   WRITE_REG(HRTIMx->sCommonRegs.BMTRGR, Trig);
07420 }
07421
07422 /**
07423   * @brief  Get actual burst mode controller trigger.
07424   * @rmtoll BMTRGR     SW           LL_HRTIM_BM_GetTrig\n
07425   *         BMTRGR     MSTRST       LL_HRTIM_BM_GetTrig\n
07426   *         BMTRGR     MSTREP       LL_HRTIM_BM_GetTrig\n
07427   *         BMTRGR     MSTCMP1      LL_HRTIM_BM_GetTrig\n
07428   *         BMTRGR     MSTCMP2      LL_HRTIM_BM_GetTrig\n
07429   *         BMTRGR     MSTCMP3      LL_HRTIM_BM_GetTrig\n
07430   *         BMTRGR     MSTCMP4      LL_HRTIM_BM_GetTrig\n
07431   *         BMTRGR     TARST        LL_HRTIM_BM_GetTrig\n
07432   *         BMTRGR     TAREP        LL_HRTIM_BM_GetTrig\n
07433   *         BMTRGR     TACMP1       LL_HRTIM_BM_GetTrig\n
07434   *         BMTRGR     TACMP2       LL_HRTIM_BM_GetTrig\n
07435   *         BMTRGR     TBRST        LL_HRTIM_BM_GetTrig\n
07436   *         BMTRGR     TBREP        LL_HRTIM_BM_GetTrig\n
07437   *         BMTRGR     TBCMP1       LL_HRTIM_BM_GetTrig\n
07438   *         BMTRGR     TBCMP2       LL_HRTIM_BM_GetTrig\n
07439   *         BMTRGR     TCRST        LL_HRTIM_BM_GetTrig\n
07440   *         BMTRGR     TCREP        LL_HRTIM_BM_GetTrig\n
07441   *         BMTRGR     TCCMP1       LL_HRTIM_BM_GetTrig\n
07442   *         BMTRGR     TCCMP2       LL_HRTIM_BM_GetTrig\n
07443   *         BMTRGR     TDRST        LL_HRTIM_BM_GetTrig\n
07444   *         BMTRGR     TDREP        LL_HRTIM_BM_GetTrig\n
07445   *         BMTRGR     TDCMP1       LL_HRTIM_BM_GetTrig\n
07446   *         BMTRGR     TDCMP2       LL_HRTIM_BM_GetTrig\n
07447   *         BMTRGR     TERST        LL_HRTIM_BM_GetTrig\n
07448   *         BMTRGR     TEREP        LL_HRTIM_BM_GetTrig\n
07449   *         BMTRGR     TECMP1       LL_HRTIM_BM_GetTrig\n
07450   *         BMTRGR     TECMP2       LL_HRTIM_BM_GetTrig\n
07451   *         BMTRGR     TAEEV7       LL_HRTIM_BM_GetTrig\n
07452   *         BMTRGR     TAEEV8       LL_HRTIM_BM_GetTrig\n
07453   *         BMTRGR     EEV7         LL_HRTIM_BM_GetTrig\n
07454   *         BMTRGR     EEV8         LL_HRTIM_BM_GetTrig\n
07455   *         BMTRGR     OCHIPEV      LL_HRTIM_BM_GetTrig
07456   * @param  HRTIMx High Resolution Timer instance
07457   * @retval Trig This parameter can be a combination of the following values:
07458   *         @arg @ref LL_HRTIM_BM_TRIG_NONE
07459   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
07460   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
07461   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
07462   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
07463   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
07464   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
07465   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
07466   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
07467   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
07468   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
07469   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
07470   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
07471   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
07472   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
07473   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
07474   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
07475   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
07476   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2
07477   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
07478   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
07479   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1
07480   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
07481   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET
07482   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
07483   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
07484   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
07485   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
07486   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
07487   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
07488   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
07489   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
07490   */
07491 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(HRTIM_TypeDef *HRTIMx)
07492 {
07493   return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR);
07494 }
07495
07496 /**
07497   * @brief  Set the burst mode controller compare value.
07498   * @rmtoll BMCMPR     BMCMP      LL_HRTIM_BM_SetCompare
07499   * @param  HRTIMx High Resolution Timer instance
07500   * @param  CompareValue Compare value must be above or equal to 3
07501   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
07502   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
07503   * @retval None
07504   */
07505 __STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareValue)
07506 {
07507   WRITE_REG(HRTIMx->sCommonRegs.BMCMPR, CompareValue);
07508 }
07509
07510 /**
07511   * @brief  Get actual burst mode controller compare value.
07512   * @rmtoll BMCMPR     BMCMP      LL_HRTIM_BM_GetCompare
07513   * @param  HRTIMx High Resolution Timer instance
07514   * @retval CompareValue Compare value must be above or equal to 3
07515   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
07516   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
07517   */
07518 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(HRTIM_TypeDef *HRTIMx)
07519 {
07520   return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR);
07521 }
07522
07523 /**
07524   * @brief  Set the burst mode controller period.
07525   * @rmtoll BMPER     BMPER      LL_HRTIM_BM_SetPeriod
07526   * @param  HRTIMx High Resolution Timer instance
07527   * @param  Period The period value must be above or equal to 3 periods of the fHRTIM clock,
07528   *         that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
07529   *         The maximum value is 0x0000 FFDF.
07530   * @retval None
07531   */
07532 __STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Period)
07533 {
07534   WRITE_REG(HRTIMx->sCommonRegs.BMPER, Period);
07535 }
07536
07537 /**
07538   * @brief  Get actual burst mode controller period.
07539   * @rmtoll BMPER     BMPER      LL_HRTIM_BM_GetPeriod
07540   * @param  HRTIMx High Resolution Timer instance
07541   * @retval The period value must be above or equal to 3 periods of the fHRTIM clock,
07542   *         that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
07543   *         The maximum value is 0x0000 FFDF.
07544   */
07545 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(HRTIM_TypeDef *HRTIMx)
07546 {
07547   return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER);
07548 }
07549
07550 /**
07551   * @brief  Enable the burst mode controller
07552   * @rmtoll BMCR     BME      LL_HRTIM_BM_Enable
07553   * @param  HRTIMx High Resolution Timer instance
07554   * @retval None
07555   */
07556 __STATIC_INLINE void LL_HRTIM_BM_Enable(HRTIM_TypeDef *HRTIMx)
07557 {
07558   SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
07559 }
07560
07561 /**
07562   * @brief  Disable the burst mode controller
07563   * @rmtoll BMCR     BME      LL_HRTIM_BM_Disable
07564   * @param  HRTIMx High Resolution Timer instance
07565   * @retval None
07566   */
07567 __STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx)
07568 {
07569   CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
07570 }
07571
07572 /**
07573   * @brief  Indicate whether the burst mode controller is enabled.
07574   * @rmtoll BMCR     BME      LL_HRTIM_BM_IsEnabled
07575   * @param  HRTIMx High Resolution Timer instance
07576   * @retval State of BME bit in HRTIM_BMCR register (1 or 0).
07577   */
07578 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(HRTIM_TypeDef *HRTIMx)
07579 {
07580   return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == HRTIM_BMCR_BME);
07581 }
07582
07583 /**
07584   * @brief  Trigger the burst operation (software trigger)
07585   * @rmtoll BMTRGR     SW           LL_HRTIM_BM_Start
07586   * @param  HRTIMx High Resolution Timer instance
07587   * @retval None
07588   */
07589 __STATIC_INLINE void LL_HRTIM_BM_Start(HRTIM_TypeDef *HRTIMx)
07590 {
07591   SET_BIT(HRTIMx->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
07592 }
07593
07594 /**
07595   * @brief  Stop the burst mode operation.
07596   * @rmtoll BMCR     BMSTAT           LL_HRTIM_BM_Stop
07597   * @note Causes a burst mode early termination.
07598   * @param  HRTIMx High Resolution Timer instance
07599   * @retval None
07600   */
07601 __STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx)
07602 {
07603   CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT);
07604 }
07605
07606 /**
07607   * @brief  Get actual burst mode status
07608   * @rmtoll BMCR     BMSTAT           LL_HRTIM_BM_GetStatus
07609   * @param  HRTIMx High Resolution Timer instance
07610   * @retval Status This parameter can be one of the following values:
07611   *         @arg @ref LL_HRTIM_BM_STATUS_NORMAL
07612   *         @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING
07613   */
07614 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(HRTIM_TypeDef *HRTIMx)
07615 {
07616   return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT));
07617 }
07618
07619 /**
07620   * @}
07621   */
07622
07623 /** @defgroup HRTIM_EF_FLAG_Management FLAG_Management
07624   * @{
07625   */
07626
07627 /**
07628   * @brief  Clear the Fault 1 interrupt flag.
07629   * @rmtoll ICR     FLT1C           LL_HRTIM_ClearFlag_FLT1
07630   * @param  HRTIMx High Resolution Timer instance
07631   * @retval None
07632   */
07633 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx)
07634 {
07635   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT1C);
07636 }
07637
07638 /**
07639   * @brief  Indicate whether Fault 1 interrupt occurred.
07640   * @rmtoll ICR     FLT1           LL_HRTIM_IsActiveFlag_FLT1
07641   * @param  HRTIMx High Resolution Timer instance
07642   * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0).
07643   */
07644 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(HRTIM_TypeDef *HRTIMx)
07645 {
07646   return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1));
07647 }
07648
07649 /**
07650   * @brief  Clear the Fault 2 interrupt flag.
07651   * @rmtoll ICR     FLT2C           LL_HRTIM_ClearFlag_FLT2
07652   * @param  HRTIMx High Resolution Timer instance
07653   * @retval None
07654   */
07655 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx)
07656 {
07657   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT2C);
07658 }
07659
07660 /**
07661   * @brief  Indicate whether Fault 2 interrupt occurred.
07662   * @rmtoll ICR     FLT2           LL_HRTIM_IsActiveFlag_FLT2
07663   * @param  HRTIMx High Resolution Timer instance
07664   * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0).
07665   */
07666 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(HRTIM_TypeDef *HRTIMx)
07667 {
07668   return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2));
07669 }
07670
07671 /**
07672   * @brief  Clear the Fault 3 interrupt flag.
07673   * @rmtoll ICR     FLT3C           LL_HRTIM_ClearFlag_FLT3
07674   * @param  HRTIMx High Resolution Timer instance
07675   * @retval None
07676   */
07677 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx)
07678 {
07679   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT3C);
07680 }
07681
07682 /**
07683   * @brief  Indicate whether Fault 3 interrupt occurred.
07684   * @rmtoll ICR     FLT3           LL_HRTIM_IsActiveFlag_FLT3
07685   * @param  HRTIMx High Resolution Timer instance
07686   * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0).
07687   */
07688 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(HRTIM_TypeDef *HRTIMx)
07689 {
07690   return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3));
07691 }
07692
07693 /**
07694   * @brief  Clear the Fault 4 interrupt flag.
07695   * @rmtoll ICR     FLT4C           LL_HRTIM_ClearFlag_FLT4
07696   * @param  HRTIMx High Resolution Timer instance
07697   * @retval None
07698   */
07699 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx)
07700 {
07701   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT4C);
07702 }
07703
07704 /**
07705   * @brief  Indicate whether Fault 4 interrupt occurred.
07706   * @rmtoll ICR     FLT4           LL_HRTIM_IsActiveFlag_FLT4
07707   * @param  HRTIMx High Resolution Timer instance
07708   * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0).
07709   */
07710 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(HRTIM_TypeDef *HRTIMx)
07711 {
07712   return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4));
07713 }
07714
07715 /**
07716   * @brief  Clear the Fault 5 interrupt flag.
07717   * @rmtoll ICR     FLT5C           LL_HRTIM_ClearFlag_FLT5
07718   * @param  HRTIMx High Resolution Timer instance
07719   * @retval None
07720   */
07721 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx)
07722 {
07723   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT5C);
07724 }
07725
07726 /**
07727   * @brief  Indicate whether Fault 5 interrupt occurred.
07728   * @rmtoll ICR     FLT5           LL_HRTIM_IsActiveFlag_FLT5
07729   * @param  HRTIMx High Resolution Timer instance
07730   * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0).
07731   */
07732 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(HRTIM_TypeDef *HRTIMx)
07733 {
07734   return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5));
07735 }
07736
07737 /**
07738   * @brief  Clear the System Fault interrupt flag.
07739   * @rmtoll ICR     SYSFLTC           LL_HRTIM_ClearFlag_SYSFLT
07740   * @param  HRTIMx High Resolution Timer instance
07741   * @retval None
07742   */
07743 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
07744 {
07745   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_SYSFLTC);
07746 }
07747
07748 /**
07749   * @brief  Indicate whether System Fault interrupt occurred.
07750   * @rmtoll ISR     SYSFLT           LL_HRTIM_IsActiveFlag_SYSFLT
07751   * @param  HRTIMx High Resolution Timer instance
07752   * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0).
07753   */
07754 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
07755 {
07756   return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT));
07757 }
07758
07759 /**
07760   * @brief  Clear the DLL ready interrupt flag.
07761   * @rmtoll ICR     DLLRDYC           LL_HRTIM_ClearFlag_DLLRDY
07762   * @param  HRTIMx High Resolution Timer instance
07763   * @retval None
07764   */
07765 __STATIC_INLINE void LL_HRTIM_ClearFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
07766 {
07767   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_DLLRDYC);
07768 }
07769
07770 /**
07771   * @brief  Indicate whether DLL ready  interrupt occurred.
07772   * @rmtoll ISR     DLLRDY           LL_HRTIM_IsActiveFlag_DLLRDY
07773   * @param  HRTIMx High Resolution Timer instance
07774   * @retval State of DLLRDY bit in HRTIM_ISR register (1 or 0).
07775   */
07776 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
07777 {
07778   return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_DLLRDY) == (HRTIM_ISR_DLLRDY));
07779 }
07780
07781 /**
07782   * @brief  Clear the Burst Mode period interrupt flag.
07783   * @rmtoll ICR     BMPERC           LL_HRTIM_ClearFlag_BMPER
07784   * @param  HRTIMx High Resolution Timer instance
07785   * @retval None
07786   */
07787 __STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx)
07788 {
07789   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_BMPERC);
07790 }
07791
07792 /**
07793   * @brief  Indicate whether Burst Mode period interrupt occurred.
07794   * @rmtoll ISR     BMPER           LL_HRTIM_IsActiveFlag_BMPER
07795   * @param  HRTIMx High Resolution Timer instance
07796   * @retval State of BMPER bit in HRTIM_ISR register (1 or 0).
07797   */
07798 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(HRTIM_TypeDef *HRTIMx)
07799 {
07800   return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER));
07801 }
07802
07803 /**
07804   * @brief  Clear the Synchronization Input interrupt flag.
07805   * @rmtoll MICR     SYNCC           LL_HRTIM_ClearFlag_SYNC
07806   * @param  HRTIMx High Resolution Timer instance
07807   * @retval None
07808   */
07809 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx)
07810 {
07811   SET_BIT(HRTIMx->sMasterRegs.MICR, HRTIM_MICR_SYNC);
07812 }
07813
07814 /**
07815   * @brief  Indicate whether the Synchronization Input interrupt occurred.
07816   * @rmtoll MISR     SYNC           LL_HRTIM_IsActiveFlag_SYNC
07817   * @param  HRTIMx High Resolution Timer instance
07818   * @retval State of SYNC bit in HRTIM_MISR register  (1 or 0).
07819   */
07820 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx)
07821 {
07822   return (READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC));
07823 }
07824
07825 /**
07826   * @brief  Clear the update interrupt flag for a given timer (including the master timer) .
07827   * @rmtoll MICR        MUPDC          LL_HRTIM_ClearFlag_UPDATE\n
07828   *         TIMxICR     UPDC           LL_HRTIM_ClearFlag_UPDATE
07829   * @param  HRTIMx High Resolution Timer instance
07830   * @param  Timer This parameter can be one of the following values:
07831   *         @arg @ref LL_HRTIM_TIMER_MASTER
07832   *         @arg @ref LL_HRTIM_TIMER_A
07833   *         @arg @ref LL_HRTIM_TIMER_B
07834   *         @arg @ref LL_HRTIM_TIMER_C
07835   *         @arg @ref LL_HRTIM_TIMER_D
07836   *         @arg @ref LL_HRTIM_TIMER_E
07837   * @retval None
07838   */
07839 __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07840 {
07841   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07842   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
07843                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07844   SET_BIT(*pReg, HRTIM_MICR_MUPD);
07845 }
07846
07847 /**
07848   * @brief  Indicate whether the update interrupt has occurred for a given timer (including the master timer) .
07849   * @rmtoll MISR        MUPD          LL_HRTIM_IsActiveFlag_UPDATE\n
07850   *         TIMxISR     UPD           LL_HRTIM_IsActiveFlag_UPDATE
07851   * @param  HRTIMx High Resolution Timer instance
07852   * @param  Timer This parameter can be one of the following values:
07853   *         @arg @ref LL_HRTIM_TIMER_MASTER
07854   *         @arg @ref LL_HRTIM_TIMER_A
07855   *         @arg @ref LL_HRTIM_TIMER_B
07856   *         @arg @ref LL_HRTIM_TIMER_C
07857   *         @arg @ref LL_HRTIM_TIMER_D
07858   *         @arg @ref LL_HRTIM_TIMER_E
07859   * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
07860   */
07861 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07862 {
07863   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07864   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
07865                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07866   return (READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD));
07867 }
07868
07869 /**
07870   * @brief  Clear the repetition interrupt flag for a given timer (including the master timer) .
07871   * @rmtoll MICR        MREPC          LL_HRTIM_ClearFlag_REP\n
07872   *         TIMxICR     REPC           LL_HRTIM_ClearFlag_REP
07873   * @param  HRTIMx High Resolution Timer instance
07874   * @param  Timer This parameter can be one of the following values:
07875   *         @arg @ref LL_HRTIM_TIMER_MASTER
07876   *         @arg @ref LL_HRTIM_TIMER_A
07877   *         @arg @ref LL_HRTIM_TIMER_B
07878   *         @arg @ref LL_HRTIM_TIMER_C
07879   *         @arg @ref LL_HRTIM_TIMER_D
07880   *         @arg @ref LL_HRTIM_TIMER_E
07881   * @retval None
07882   */
07883 __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07884 {
07885   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07886   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
07887                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07888   SET_BIT(*pReg, HRTIM_MICR_MREP);
07889
07890 }
07891
07892 /**
07893   * @brief  Indicate whether the repetition  interrupt has occurred for a given timer (including the master timer) .
07894   * @rmtoll MISR        MREP          LL_HRTIM_IsActiveFlag_REP\n
07895   *         TIMxISR     REP           LL_HRTIM_IsActiveFlag_REP
07896   * @param  HRTIMx High Resolution Timer instance
07897   * @param  Timer This parameter can be one of the following values:
07898   *         @arg @ref LL_HRTIM_TIMER_MASTER
07899   *         @arg @ref LL_HRTIM_TIMER_A
07900   *         @arg @ref LL_HRTIM_TIMER_B
07901   *         @arg @ref LL_HRTIM_TIMER_C
07902   *         @arg @ref LL_HRTIM_TIMER_D
07903   *         @arg @ref LL_HRTIM_TIMER_E
07904   * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
07905   */
07906 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07907 {
07908   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07909   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
07910                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07911   return (READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP));
07912 }
07913
07914 /**
07915   * @brief  Clear the compare 1 match interrupt for a given timer (including the master timer).
07916   * @rmtoll MICR        MCMP1C          LL_HRTIM_ClearFlag_CMP1\n
07917   *         TIMxICR     CMP1C           LL_HRTIM_ClearFlag_CMP1
07918   * @param  HRTIMx High Resolution Timer instance
07919   * @param  Timer This parameter can be one of the following values:
07920   *         @arg @ref LL_HRTIM_TIMER_MASTER
07921   *         @arg @ref LL_HRTIM_TIMER_A
07922   *         @arg @ref LL_HRTIM_TIMER_B
07923   *         @arg @ref LL_HRTIM_TIMER_C
07924   *         @arg @ref LL_HRTIM_TIMER_D
07925   *         @arg @ref LL_HRTIM_TIMER_E
07926   * @retval None
07927   */
07928 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07929 {
07930   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07931   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
07932                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07933   SET_BIT(*pReg, HRTIM_MICR_MCMP1);
07934 }
07935
07936 /**
07937   * @brief  Indicate whether the compare match 1  interrupt has occurred for a given timer (including the master timer) .
07938   * @rmtoll MISR        MCMP1          LL_HRTIM_IsActiveFlag_CMP1\n
07939   *         TIMxISR     CMP1           LL_HRTIM_IsActiveFlag_CMP1
07940   * @param  HRTIMx High Resolution Timer instance
07941   * @param  Timer This parameter can be one of the following values:
07942   *         @arg @ref LL_HRTIM_TIMER_MASTER
07943   *         @arg @ref LL_HRTIM_TIMER_A
07944   *         @arg @ref LL_HRTIM_TIMER_B
07945   *         @arg @ref LL_HRTIM_TIMER_C
07946   *         @arg @ref LL_HRTIM_TIMER_D
07947   *         @arg @ref LL_HRTIM_TIMER_E
07948   * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
07949   */
07950 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07951 {
07952   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07953   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
07954                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07955   return (READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1));
07956 }
07957
07958 /**
07959   * @brief  Clear the compare 2 match interrupt for a given timer (including the master timer).
07960   * @rmtoll MICR        MCMP2C          LL_HRTIM_ClearFlag_CMP2\n
07961   *         TIMxICR     CMP2C           LL_HRTIM_ClearFlag_CMP2
07962   * @param  HRTIMx High Resolution Timer instance
07963   * @param  Timer This parameter can be one of the following values:
07964   *         @arg @ref LL_HRTIM_TIMER_MASTER
07965   *         @arg @ref LL_HRTIM_TIMER_A
07966   *         @arg @ref LL_HRTIM_TIMER_B
07967   *         @arg @ref LL_HRTIM_TIMER_C
07968   *         @arg @ref LL_HRTIM_TIMER_D
07969   *         @arg @ref LL_HRTIM_TIMER_E
07970   * @retval None
07971   */
07972 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07973 {
07974   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07975   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
07976                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07977   SET_BIT(*pReg, HRTIM_MICR_MCMP2);
07978 }
07979
07980 /**
07981   * @brief  Indicate whether the compare match 2  interrupt has occurred for a given timer (including the master timer) .
07982   * @rmtoll MISR        MCMP2          LL_HRTIM_IsActiveFlag_CMP2\n
07983   *         TIMxISR     CMP2           LL_HRTIM_IsActiveFlag_CMP2
07984   * @param  HRTIMx High Resolution Timer instance
07985   * @param  Timer This parameter can be one of the following values:
07986   *         @arg @ref LL_HRTIM_TIMER_MASTER
07987   *         @arg @ref LL_HRTIM_TIMER_A
07988   *         @arg @ref LL_HRTIM_TIMER_B
07989   *         @arg @ref LL_HRTIM_TIMER_C
07990   *         @arg @ref LL_HRTIM_TIMER_D
07991   *         @arg @ref LL_HRTIM_TIMER_E
07992   * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
07993   */
07994 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07995 {
07996   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07997   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
07998                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07999   return (READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2));
08000 }
08001
08002 /**
08003   * @brief  Clear the compare 3 match interrupt for a given timer (including the master timer).
08004   * @rmtoll MICR        MCMP3C          LL_HRTIM_ClearFlag_CMP3\n
08005   *         TIMxICR     CMP3C           LL_HRTIM_ClearFlag_CMP3
08006   * @param  HRTIMx High Resolution Timer instance
08007   * @param  Timer This parameter can be one of the following values:
08008   *         @arg @ref LL_HRTIM_TIMER_MASTER
08009   *         @arg @ref LL_HRTIM_TIMER_A
08010   *         @arg @ref LL_HRTIM_TIMER_B
08011   *         @arg @ref LL_HRTIM_TIMER_C
08012   *         @arg @ref LL_HRTIM_TIMER_D
08013   *         @arg @ref LL_HRTIM_TIMER_E
08014   * @retval None
08015   */
08016 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08017 {
08018   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08019   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08020                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08021   SET_BIT(*pReg, HRTIM_MICR_MCMP3);
08022 }
08023
08024 /**
08025   * @brief  Indicate whether the compare match 3  interrupt has occurred for a given timer (including the master timer) .
08026   * @rmtoll MISR        MCMP3          LL_HRTIM_IsActiveFlag_CMP3\n
08027   *         TIMxISR     CMP3           LL_HRTIM_IsActiveFlag_CMP3
08028   * @param  HRTIMx High Resolution Timer instance
08029   * @param  Timer This parameter can be one of the following values:
08030   *         @arg @ref LL_HRTIM_TIMER_MASTER
08031   *         @arg @ref LL_HRTIM_TIMER_A
08032   *         @arg @ref LL_HRTIM_TIMER_B
08033   *         @arg @ref LL_HRTIM_TIMER_C
08034   *         @arg @ref LL_HRTIM_TIMER_D
08035   *         @arg @ref LL_HRTIM_TIMER_E
08036   * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
08037   */
08038 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08039 {
08040   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08041   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08042                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08043   return (READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3));
08044 }
08045
08046 /**
08047   * @brief  Clear the compare 4 match interrupt for a given timer (including the master timer).
08048   * @rmtoll MICR        MCMP4C          LL_HRTIM_ClearFlag_CMP4\n
08049   *         TIMxICR     CMP4C           LL_HRTIM_ClearFlag_CMP4
08050   * @param  HRTIMx High Resolution Timer instance
08051   * @param  Timer This parameter can be one of the following values:
08052   *         @arg @ref LL_HRTIM_TIMER_MASTER
08053   *         @arg @ref LL_HRTIM_TIMER_A
08054   *         @arg @ref LL_HRTIM_TIMER_B
08055   *         @arg @ref LL_HRTIM_TIMER_C
08056   *         @arg @ref LL_HRTIM_TIMER_D
08057   *         @arg @ref LL_HRTIM_TIMER_E
08058   * @retval None
08059   */
08060 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08061 {
08062   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08063   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08064                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08065   SET_BIT(*pReg, HRTIM_MICR_MCMP4);
08066 }
08067
08068 /**
08069   * @brief  Indicate whether the compare match 4  interrupt has occurred for a given timer (including the master timer) .
08070   * @rmtoll MISR        MCMP4          LL_HRTIM_IsActiveFlag_CMP4\n
08071   *         TIMxISR     CMP4           LL_HRTIM_IsActiveFlag_CMP4
08072   * @param  HRTIMx High Resolution Timer instance
08073   * @param  Timer This parameter can be one of the following values:
08074   *         @arg @ref LL_HRTIM_TIMER_MASTER
08075   *         @arg @ref LL_HRTIM_TIMER_A
08076   *         @arg @ref LL_HRTIM_TIMER_B
08077   *         @arg @ref LL_HRTIM_TIMER_C
08078   *         @arg @ref LL_HRTIM_TIMER_D
08079   *         @arg @ref LL_HRTIM_TIMER_E
08080   * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
08081   */
08082 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08083 {
08084   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08085   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08086                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08087   return (READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4));
08088 }
08089
08090 /**
08091   * @brief  Clear the capture 1 interrupt flag for a given timer.
08092   * @rmtoll TIMxICR     CPT1C           LL_HRTIM_ClearFlag_CPT1
08093   * @param  HRTIMx High Resolution Timer instance
08094   * @param  Timer This parameter can be one of the following values:
08095   *         @arg @ref LL_HRTIM_TIMER_A
08096   *         @arg @ref LL_HRTIM_TIMER_B
08097   *         @arg @ref LL_HRTIM_TIMER_C
08098   *         @arg @ref LL_HRTIM_TIMER_D
08099   *         @arg @ref LL_HRTIM_TIMER_E
08100   * @retval None
08101   */
08102 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08103 {
08104   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08105   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08106                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08107   SET_BIT(*pReg, HRTIM_TIMICR_CPT1C);
08108 }
08109
08110 /**
08111   * @brief  Indicate whether the capture 1 interrupt occurred for a given timer.
08112   * @rmtoll TIMxISR     CPT1           LL_HRTIM_IsActiveFlag_CPT1
08113   * @param  HRTIMx High Resolution Timer instance
08114   * @param  Timer This parameter can be one of the following values:
08115   *         @arg @ref LL_HRTIM_TIMER_A
08116   *         @arg @ref LL_HRTIM_TIMER_B
08117   *         @arg @ref LL_HRTIM_TIMER_C
08118   *         @arg @ref LL_HRTIM_TIMER_D
08119   *         @arg @ref LL_HRTIM_TIMER_E
08120   * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0).
08121   */
08122 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08123 {
08124   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08125   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08126                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08127   return (READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1));
08128 }
08129
08130 /**
08131   * @brief  Clear the capture 2 interrupt flag for a given timer.
08132   * @rmtoll TIMxICR     CPT2C           LL_HRTIM_ClearFlag_CPT2
08133   * @param  HRTIMx High Resolution Timer instance
08134   * @param  Timer This parameter can be one of the following values:
08135   *         @arg @ref LL_HRTIM_TIMER_A
08136   *         @arg @ref LL_HRTIM_TIMER_B
08137   *         @arg @ref LL_HRTIM_TIMER_C
08138   *         @arg @ref LL_HRTIM_TIMER_D
08139   *         @arg @ref LL_HRTIM_TIMER_E
08140   * @retval None
08141   */
08142 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08143 {
08144   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08145   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08146                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08147   SET_BIT(*pReg, HRTIM_TIMICR_CPT2C);
08148 }
08149
08150 /**
08151   * @brief  Indicate whether the capture 2 interrupt occurred for a given timer.
08152   * @rmtoll TIMxISR     CPT2           LL_HRTIM_IsActiveFlag_CPT2
08153   * @param  HRTIMx High Resolution Timer instance
08154   * @param  Timer This parameter can be one of the following values:
08155   *         @arg @ref LL_HRTIM_TIMER_A
08156   *         @arg @ref LL_HRTIM_TIMER_B
08157   *         @arg @ref LL_HRTIM_TIMER_C
08158   *         @arg @ref LL_HRTIM_TIMER_D
08159   *         @arg @ref LL_HRTIM_TIMER_E
08160   * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0).
08161   */
08162 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08163 {
08164   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08165   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08166                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08167   return (READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2));
08168 }
08169
08170 /**
08171   * @brief  Clear the output 1 set interrupt flag for a given timer.
08172   * @rmtoll TIMxICR     SET1C           LL_HRTIM_ClearFlag_SET1
08173   * @param  HRTIMx High Resolution Timer instance
08174   * @param  Timer This parameter can be one of the following values:
08175   *         @arg @ref LL_HRTIM_TIMER_A
08176   *         @arg @ref LL_HRTIM_TIMER_B
08177   *         @arg @ref LL_HRTIM_TIMER_C
08178   *         @arg @ref LL_HRTIM_TIMER_D
08179   *         @arg @ref LL_HRTIM_TIMER_E
08180   * @retval None
08181   */
08182 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08183 {
08184   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08185   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08186                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08187   SET_BIT(*pReg, HRTIM_TIMICR_SET1C);
08188 }
08189
08190 /**
08191   * @brief  Indicate whether the output 1 set interrupt occurred for a given timer.
08192   * @rmtoll TIMxISR     SET1           LL_HRTIM_IsActiveFlag_SET1
08193   * @param  HRTIMx High Resolution Timer instance
08194   * @param  Timer This parameter can be one of the following values:
08195   *         @arg @ref LL_HRTIM_TIMER_A
08196   *         @arg @ref LL_HRTIM_TIMER_B
08197   *         @arg @ref LL_HRTIM_TIMER_C
08198   *         @arg @ref LL_HRTIM_TIMER_D
08199   *         @arg @ref LL_HRTIM_TIMER_E
08200   * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0).
08201   */
08202 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08203 {
08204   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08205   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08206                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08207   return (READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1));
08208 }
08209
08210 /**
08211   * @brief  Clear the output 1 reset interrupt flag for a given timer.
08212   * @rmtoll TIMxICR     RST1C           LL_HRTIM_ClearFlag_RST1
08213   * @param  HRTIMx High Resolution Timer instance
08214   * @param  Timer This parameter can be one of the following values:
08215   *         @arg @ref LL_HRTIM_TIMER_A
08216   *         @arg @ref LL_HRTIM_TIMER_B
08217   *         @arg @ref LL_HRTIM_TIMER_C
08218   *         @arg @ref LL_HRTIM_TIMER_D
08219   *         @arg @ref LL_HRTIM_TIMER_E
08220   * @retval None
08221   */
08222 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08223 {
08224   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08225   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08226                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08227   SET_BIT(*pReg, HRTIM_TIMICR_RST1C);
08228 }
08229
08230 /**
08231   * @brief  Indicate whether the output 1 reset interrupt occurred for a given timer.
08232   * @rmtoll TIMxISR     RST1           LL_HRTIM_IsActiveFlag_RST1
08233   * @param  HRTIMx High Resolution Timer instance
08234   * @param  Timer This parameter can be one of the following values:
08235   *         @arg @ref LL_HRTIM_TIMER_A
08236   *         @arg @ref LL_HRTIM_TIMER_B
08237   *         @arg @ref LL_HRTIM_TIMER_C
08238   *         @arg @ref LL_HRTIM_TIMER_D
08239   *         @arg @ref LL_HRTIM_TIMER_E
08240   * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0).
08241   */
08242 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08243 {
08244   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08245   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08246                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08247   return (READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1));
08248 }
08249
08250 /**
08251   * @brief  Clear the output 2 set interrupt flag for a given timer.
08252   * @rmtoll TIMxICR     SET2C           LL_HRTIM_ClearFlag_SET2
08253   * @param  HRTIMx High Resolution Timer instance
08254   * @param  Timer This parameter can be one of the following values:
08255   *         @arg @ref LL_HRTIM_TIMER_A
08256   *         @arg @ref LL_HRTIM_TIMER_B
08257   *         @arg @ref LL_HRTIM_TIMER_C
08258   *         @arg @ref LL_HRTIM_TIMER_D
08259   *         @arg @ref LL_HRTIM_TIMER_E
08260   * @retval None
08261   */
08262 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08263 {
08264   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08265   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08266                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08267   SET_BIT(*pReg, HRTIM_TIMICR_SET2C);
08268 }
08269
08270 /**
08271   * @brief  Indicate whether the output 2 set interrupt occurred for a given timer.
08272   * @rmtoll TIMxISR     SET2           LL_HRTIM_IsActiveFlag_SET2
08273   * @param  HRTIMx High Resolution Timer instance
08274   * @param  Timer This parameter can be one of the following values:
08275   *         @arg @ref LL_HRTIM_TIMER_A
08276   *         @arg @ref LL_HRTIM_TIMER_B
08277   *         @arg @ref LL_HRTIM_TIMER_C
08278   *         @arg @ref LL_HRTIM_TIMER_D
08279   *         @arg @ref LL_HRTIM_TIMER_E
08280   * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0).
08281   */
08282 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08283 {
08284   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08285   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08286                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08287   return (READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2));
08288 }
08289
08290 /**
08291   * @brief  Clear the output 2reset interrupt flag for a given timer.
08292   * @rmtoll TIMxICR     RST2C           LL_HRTIM_ClearFlag_RST2
08293   * @param  HRTIMx High Resolution Timer instance
08294   * @param  Timer This parameter can be one of the following values:
08295   *         @arg @ref LL_HRTIM_TIMER_A
08296   *         @arg @ref LL_HRTIM_TIMER_B
08297   *         @arg @ref LL_HRTIM_TIMER_C
08298   *         @arg @ref LL_HRTIM_TIMER_D
08299   *         @arg @ref LL_HRTIM_TIMER_E
08300   * @retval None
08301   */
08302 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08303 {
08304   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08305   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08306                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08307   SET_BIT(*pReg, HRTIM_TIMICR_RST2C);
08308 }
08309
08310 /**
08311   * @brief  Indicate whether the output 2 reset interrupt occurred for a given timer.
08312   * @rmtoll TIMxISR     RST2           LL_HRTIM_IsActiveFlag_RST2
08313   * @param  HRTIMx High Resolution Timer instance
08314   * @param  Timer This parameter can be one of the following values:
08315   *         @arg @ref LL_HRTIM_TIMER_A
08316   *         @arg @ref LL_HRTIM_TIMER_B
08317   *         @arg @ref LL_HRTIM_TIMER_C
08318   *         @arg @ref LL_HRTIM_TIMER_D
08319   *         @arg @ref LL_HRTIM_TIMER_E
08320   * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0).
08321   */
08322 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08323 {
08324   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08325   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08326                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08327   return (READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2));
08328 }
08329
08330 /**
08331   * @brief  Clear the reset and/or roll-over interrupt flag for a given timer.
08332   * @rmtoll TIMxICR     RSTC           LL_HRTIM_ClearFlag_RST
08333   * @param  HRTIMx High Resolution Timer instance
08334   * @param  Timer This parameter can be one of the following values:
08335   *         @arg @ref LL_HRTIM_TIMER_A
08336   *         @arg @ref LL_HRTIM_TIMER_B
08337   *         @arg @ref LL_HRTIM_TIMER_C
08338   *         @arg @ref LL_HRTIM_TIMER_D
08339   *         @arg @ref LL_HRTIM_TIMER_E
08340   * @retval None
08341   */
08342 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08343 {
08344   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08345   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08346                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08347   SET_BIT(*pReg, HRTIM_TIMICR_RSTC);
08348 }
08349
08350 /**
08351   * @brief  Indicate whether the  reset and/or roll-over interrupt occurred for a given timer.
08352   * @rmtoll TIMxISR     RST           LL_HRTIM_IsActiveFlag_RST
08353   * @param  HRTIMx High Resolution Timer instance
08354   * @param  Timer This parameter can be one of the following values:
08355   *         @arg @ref LL_HRTIM_TIMER_A
08356   *         @arg @ref LL_HRTIM_TIMER_B
08357   *         @arg @ref LL_HRTIM_TIMER_C
08358   *         @arg @ref LL_HRTIM_TIMER_D
08359   *         @arg @ref LL_HRTIM_TIMER_E
08360   * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0).
08361   */
08362 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08363 {
08364   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08365   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08366                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08367   return (READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST));
08368 }
08369
08370 /**
08371   * @brief  Clear the delayed protection interrupt flag for a given timer.
08372   * @rmtoll TIMxICR     DLYPRTC           LL_HRTIM_ClearFlag_DLYPRT
08373   * @param  HRTIMx High Resolution Timer instance
08374   * @param  Timer This parameter can be one of the following values:
08375   *         @arg @ref LL_HRTIM_TIMER_A
08376   *         @arg @ref LL_HRTIM_TIMER_B
08377   *         @arg @ref LL_HRTIM_TIMER_C
08378   *         @arg @ref LL_HRTIM_TIMER_D
08379   *         @arg @ref LL_HRTIM_TIMER_E
08380   * @retval None
08381   */
08382 __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08383 {
08384   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08385   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08386                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08387   SET_BIT(*pReg, HRTIM_TIMICR_DLYPRT1C);
08388 }
08389
08390 /**
08391   * @brief  Indicate whether the  delayed protection interrupt occurred for a given timer.
08392   * @rmtoll TIMxISR     DLYPRT           LL_HRTIM_IsActiveFlag_DLYPRT
08393   * @param  HRTIMx High Resolution Timer instance
08394   * @param  Timer This parameter can be one of the following values:
08395   *         @arg @ref LL_HRTIM_TIMER_A
08396   *         @arg @ref LL_HRTIM_TIMER_B
08397   *         @arg @ref LL_HRTIM_TIMER_C
08398   *         @arg @ref LL_HRTIM_TIMER_D
08399   *         @arg @ref LL_HRTIM_TIMER_E
08400   * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0).
08401   */
08402 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08403 {
08404   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08405   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08406                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08407   return (READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT));
08408 }
08409
08410 /**
08411   * @}
08412   */
08413
08414 /** @defgroup HRTIM_EF_IT_Management IT_Management
08415   * @{
08416   */
08417
08418 /**
08419   * @brief  Enable the fault 1 interrupt.
08420   * @rmtoll IER     FLT1IE           LL_HRTIM_EnableIT_FLT1
08421   * @param  HRTIMx High Resolution Timer instance
08422   * @retval None
08423   */
08424 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef *HRTIMx)
08425 {
08426   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
08427 }
08428
08429 /**
08430   * @brief  Disable the fault 1 interrupt.
08431   * @rmtoll IER     FLT1IE           LL_HRTIM_DisableIT_FLT1
08432   * @param  HRTIMx High Resolution Timer instance
08433   * @retval None
08434   */
08435 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx)
08436 {
08437   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
08438 }
08439
08440 /**
08441   * @brief  Indicate whether the fault 1 interrupt is enabled.
08442   * @rmtoll IER     FLT1IE           LL_HRTIM_IsEnabledIT_FLT1
08443   * @param  HRTIMx High Resolution Timer instance
08444   * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0).
08445   */
08446 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(HRTIM_TypeDef *HRTIMx)
08447 {
08448   return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1));
08449 }
08450
08451 /**
08452   * @brief  Enable the fault 2 interrupt.
08453   * @rmtoll IER     FLT2IE           LL_HRTIM_EnableIT_FLT2
08454   * @param  HRTIMx High Resolution Timer instance
08455   * @retval None
08456   */
08457 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef *HRTIMx)
08458 {
08459   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
08460 }
08461
08462 /**
08463   * @brief  Disable the fault 2 interrupt.
08464   * @rmtoll IER     FLT2IE           LL_HRTIM_DisableIT_FLT2
08465   * @param  HRTIMx High Resolution Timer instance
08466   * @retval None
08467   */
08468 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx)
08469 {
08470   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
08471 }
08472
08473 /**
08474   * @brief  Indicate whether the fault 2 interrupt is enabled.
08475   * @rmtoll IER     FLT2IE           LL_HRTIM_IsEnabledIT_FLT2
08476   * @param  HRTIMx High Resolution Timer instance
08477   * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0).
08478   */
08479 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(HRTIM_TypeDef *HRTIMx)
08480 {
08481   return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2));
08482 }
08483
08484 /**
08485   * @brief  Enable the fault 3 interrupt.
08486   * @rmtoll IER     FLT3IE           LL_HRTIM_EnableIT_FLT3
08487   * @param  HRTIMx High Resolution Timer instance
08488   * @retval None
08489   */
08490 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef *HRTIMx)
08491 {
08492   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
08493 }
08494
08495 /**
08496   * @brief  Disable the fault 3 interrupt.
08497   * @rmtoll IER     FLT3IE           LL_HRTIM_DisableIT_FLT3
08498   * @param  HRTIMx High Resolution Timer instance
08499   * @retval None
08500   */
08501 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx)
08502 {
08503   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
08504 }
08505
08506 /**
08507   * @brief  Indicate whether the fault 3 interrupt is enabled.
08508   * @rmtoll IER     FLT3IE           LL_HRTIM_IsEnabledIT_FLT3
08509   * @param  HRTIMx High Resolution Timer instance
08510   * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0).
08511   */
08512 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(HRTIM_TypeDef *HRTIMx)
08513 {
08514   return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3));
08515 }
08516
08517 /**
08518   * @brief  Enable the fault 4 interrupt.
08519   * @rmtoll IER     FLT4IE           LL_HRTIM_EnableIT_FLT4
08520   * @param  HRTIMx High Resolution Timer instance
08521   * @retval None
08522   */
08523 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef *HRTIMx)
08524 {
08525   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
08526 }
08527
08528 /**
08529   * @brief  Disable the fault 4 interrupt.
08530   * @rmtoll IER     FLT4IE           LL_HRTIM_DisableIT_FLT4
08531   * @param  HRTIMx High Resolution Timer instance
08532   * @retval None
08533   */
08534 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx)
08535 {
08536   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
08537 }
08538
08539 /**
08540   * @brief  Indicate whether the fault 4 interrupt is enabled.
08541   * @rmtoll IER     FLT4IE           LL_HRTIM_IsEnabledIT_FLT4
08542   * @param  HRTIMx High Resolution Timer instance
08543   * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0).
08544   */
08545 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(HRTIM_TypeDef *HRTIMx)
08546 {
08547   return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4));
08548 }
08549
08550 /**
08551   * @brief  Enable the fault 5 interrupt.
08552   * @rmtoll IER     FLT5IE           LL_HRTIM_EnableIT_FLT5
08553   * @param  HRTIMx High Resolution Timer instance
08554   * @retval None
08555   */
08556 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef *HRTIMx)
08557 {
08558   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
08559 }
08560
08561 /**
08562   * @brief  Disable the fault 5 interrupt.
08563   * @rmtoll IER     FLT5IE           LL_HRTIM_DisableIT_FLT5
08564   * @param  HRTIMx High Resolution Timer instance
08565   * @retval None
08566   */
08567 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx)
08568 {
08569   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
08570 }
08571
08572 /**
08573   * @brief  Indicate whether the fault 5 interrupt is enabled.
08574   * @rmtoll IER     FLT5IE           LL_HRTIM_IsEnabledIT_FLT5
08575   * @param  HRTIMx High Resolution Timer instance
08576   * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0).
08577   */
08578 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(HRTIM_TypeDef *HRTIMx)
08579 {
08580   return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5));
08581 }
08582
08583 /**
08584   * @brief  Enable the system fault interrupt.
08585   * @rmtoll IER     SYSFLTIE           LL_HRTIM_EnableIT_SYSFLT
08586   * @param  HRTIMx High Resolution Timer instance
08587   * @retval None
08588   */
08589 __STATIC_INLINE void LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
08590 {
08591   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
08592 }
08593
08594 /**
08595   * @brief  Disable the system fault interrupt.
08596   * @rmtoll IER     SYSFLTIE           LL_HRTIM_DisableIT_SYSFLT
08597   * @param  HRTIMx High Resolution Timer instance
08598   * @retval None
08599   */
08600 __STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
08601 {
08602   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
08603 }
08604
08605 /**
08606   * @brief  Indicate whether the system fault interrupt is enabled.
08607   * @rmtoll IER     SYSFLTIE           LL_HRTIM_IsEnabledIT_SYSFLT
08608   * @param  HRTIMx High Resolution Timer instance
08609   * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0).
08610   */
08611 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
08612 {
08613   return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT));
08614 }
08615
08616 /**
08617   * @brief  Enable the DLL ready interrupt.
08618   * @rmtoll IER     DLLRDYIE           LL_HRTIM_EnableIT_DLLRDY
08619   * @param  HRTIMx High Resolution Timer instance
08620   * @retval None
08621   */
08622 __STATIC_INLINE void LL_HRTIM_EnableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
08623 {
08624   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
08625 }
08626
08627 /**
08628   * @brief  Disable the DLL ready interrupt.
08629   * @rmtoll IER     DLLRDYIE           LL_HRTIM_DisableIT_DLLRDY
08630   * @param  HRTIMx High Resolution Timer instance
08631   * @retval None
08632   */
08633 __STATIC_INLINE void LL_HRTIM_DisableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
08634 {
08635   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
08636 }
08637
08638 /**
08639   * @brief  Indicate whether the DLL ready interrupt is enabled.
08640   * @rmtoll IER     DLLRDYIE           LL_HRTIM_IsEnabledIT_DLLRDY
08641   * @param  HRTIMx High Resolution Timer instance
08642   * @retval State of DLLRDYIE bit in HRTIM_IER register (1 or 0).
08643   */
08644 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
08645 {
08646   return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY) == (HRTIM_IER_DLLRDY));
08647 }
08648
08649 /**
08650   * @brief  Enable the burst mode period interrupt.
08651   * @rmtoll IER     BMPERIE           LL_HRTIM_EnableIT_BMPER
08652   * @param  HRTIMx High Resolution Timer instance
08653   * @retval None
08654   */
08655 __STATIC_INLINE void LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef *HRTIMx)
08656 {
08657   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
08658 }
08659
08660 /**
08661   * @brief  Disable the burst mode period interrupt.
08662   * @rmtoll IER     BMPERIE           LL_HRTIM_DisableIT_BMPER
08663   * @param  HRTIMx High Resolution Timer instance
08664   * @retval None
08665   */
08666 __STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx)
08667 {
08668   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
08669 }
08670
08671 /**
08672   * @brief  Indicate whether the burst mode period interrupt is enabled.
08673   * @rmtoll IER     BMPERIE           LL_HRTIM_IsEnabledIT_BMPER
08674   * @param  HRTIMx High Resolution Timer instance
08675   * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0).
08676   */
08677 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(HRTIM_TypeDef *HRTIMx)
08678 {
08679   return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER));
08680 }
08681
08682 /**
08683   * @brief  Enable the synchronization input interrupt.
08684   * @rmtoll MDIER     SYNCIE           LL_HRTIM_EnableIT_SYNC
08685   * @param  HRTIMx High Resolution Timer instance
08686   * @retval None
08687   */
08688 __STATIC_INLINE void LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef *HRTIMx)
08689 {
08690   SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
08691 }
08692
08693 /**
08694   * @brief  Disable the synchronization input interrupt.
08695   * @rmtoll MDIER     SYNCIE           LL_HRTIM_DisableIT_SYNC
08696   * @param  HRTIMx High Resolution Timer instance
08697   * @retval None
08698   */
08699 __STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx)
08700 {
08701   CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
08702 }
08703
08704 /**
08705   * @brief  Indicate whether the synchronization input interrupt is enabled.
08706   * @rmtoll MDIER     SYNCIE           LL_HRTIM_IsEnabledIT_SYNC
08707   * @param  HRTIMx High Resolution Timer instance
08708   * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0).
08709   */
08710 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx)
08711 {
08712   return (READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE));
08713 }
08714
08715 /**
08716   * @brief  Enable the update interrupt for a given timer.
08717   * @rmtoll MDIER        MUPDIE           LL_HRTIM_EnableIT_UPDATE\n
08718   *         TIMxDIER     UPDIE            LL_HRTIM_EnableIT_UPDATE
08719   * @param  HRTIMx High Resolution Timer instance
08720   * @param  Timer This parameter can be one of the following values:
08721   *         @arg @ref LL_HRTIM_TIMER_MASTER
08722   *         @arg @ref LL_HRTIM_TIMER_A
08723   *         @arg @ref LL_HRTIM_TIMER_B
08724   *         @arg @ref LL_HRTIM_TIMER_C
08725   *         @arg @ref LL_HRTIM_TIMER_D
08726   *         @arg @ref LL_HRTIM_TIMER_E
08727   * @retval None
08728   */
08729 __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08730 {
08731   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08732   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08733                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08734   SET_BIT(*pReg, HRTIM_MDIER_MUPDIE);
08735 }
08736
08737 /**
08738   * @brief  Disable the update interrupt for a given timer.
08739   * @rmtoll MDIER        MUPDIE           LL_HRTIM_DisableIT_UPDATE\n
08740   *         TIMxDIER     UPDIE            LL_HRTIM_DisableIT_UPDATE
08741   * @param  HRTIMx High Resolution Timer instance
08742   * @param  Timer This parameter can be one of the following values:
08743   *         @arg @ref LL_HRTIM_TIMER_MASTER
08744   *         @arg @ref LL_HRTIM_TIMER_A
08745   *         @arg @ref LL_HRTIM_TIMER_B
08746   *         @arg @ref LL_HRTIM_TIMER_C
08747   *         @arg @ref LL_HRTIM_TIMER_D
08748   *         @arg @ref LL_HRTIM_TIMER_E
08749   * @retval None
08750   */
08751 __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08752 {
08753   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08754   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08755                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08756   CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE);
08757 }
08758
08759 /**
08760   * @brief  Indicate whether the update interrupt is enabled for a given timer.
08761   * @rmtoll MDIER        MUPDIE           LL_HRTIM_IsEnabledIT_UPDATE\n
08762   *         TIMxDIER     UPDIE            LL_HRTIM_IsEnabledIT_UPDATE
08763   * @param  HRTIMx High Resolution Timer instance
08764   * @param  Timer This parameter can be one of the following values:
08765   *         @arg @ref LL_HRTIM_TIMER_MASTER
08766   *         @arg @ref LL_HRTIM_TIMER_A
08767   *         @arg @ref LL_HRTIM_TIMER_B
08768   *         @arg @ref LL_HRTIM_TIMER_C
08769   *         @arg @ref LL_HRTIM_TIMER_D
08770   *         @arg @ref LL_HRTIM_TIMER_E
08771   * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
08772   */
08773 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08774 {
08775   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08776   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08777                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08778   return (READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE));
08779 }
08780
08781 /**
08782   * @brief  Enable the repetition interrupt for a given timer.
08783   * @rmtoll MDIER        MREPIE           LL_HRTIM_EnableIT_REP\n
08784   *         TIMxDIER     REPIE            LL_HRTIM_EnableIT_REP
08785   * @param  HRTIMx High Resolution Timer instance
08786   * @param  Timer This parameter can be one of the following values:
08787   *         @arg @ref LL_HRTIM_TIMER_MASTER
08788   *         @arg @ref LL_HRTIM_TIMER_A
08789   *         @arg @ref LL_HRTIM_TIMER_B
08790   *         @arg @ref LL_HRTIM_TIMER_C
08791   *         @arg @ref LL_HRTIM_TIMER_D
08792   *         @arg @ref LL_HRTIM_TIMER_E
08793   * @retval None
08794   */
08795 __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08796 {
08797   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08798   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08799                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08800   SET_BIT(*pReg, HRTIM_MDIER_MREPIE);
08801 }
08802
08803 /**
08804   * @brief  Disable the repetition interrupt for a given timer.
08805   * @rmtoll MDIER        MREPIE           LL_HRTIM_DisableIT_REP\n
08806   *         TIMxDIER     REPIE            LL_HRTIM_DisableIT_REP
08807   * @param  HRTIMx High Resolution Timer instance
08808   * @param  Timer This parameter can be one of the following values:
08809   *         @arg @ref LL_HRTIM_TIMER_MASTER
08810   *         @arg @ref LL_HRTIM_TIMER_A
08811   *         @arg @ref LL_HRTIM_TIMER_B
08812   *         @arg @ref LL_HRTIM_TIMER_C
08813   *         @arg @ref LL_HRTIM_TIMER_D
08814   *         @arg @ref LL_HRTIM_TIMER_E
08815   * @retval None
08816   */
08817 __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08818 {
08819   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08820   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08821                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08822   CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE);
08823 }
08824
08825 /**
08826   * @brief  Indicate whether the repetition interrupt is enabled for a given timer.
08827   * @rmtoll MDIER        MREPIE           LL_HRTIM_IsEnabledIT_REP\n
08828   *         TIMxDIER     REPIE            LL_HRTIM_IsEnabledIT_REP
08829   * @param  HRTIMx High Resolution Timer instance
08830   * @param  Timer This parameter can be one of the following values:
08831   *         @arg @ref LL_HRTIM_TIMER_MASTER
08832   *         @arg @ref LL_HRTIM_TIMER_A
08833   *         @arg @ref LL_HRTIM_TIMER_B
08834   *         @arg @ref LL_HRTIM_TIMER_C
08835   *         @arg @ref LL_HRTIM_TIMER_D
08836   *         @arg @ref LL_HRTIM_TIMER_E
08837   * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
08838   */
08839 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08840 {
08841   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08842   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08843                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08844   return (READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE));
08845 }
08846
08847 /**
08848   * @brief  Enable the compare 1 interrupt for a given timer.
08849   * @rmtoll MDIER        MCMP1IE           LL_HRTIM_EnableIT_CMP1\n
08850   *         TIMxDIER     CMP1IE            LL_HRTIM_EnableIT_CMP1
08851   * @param  HRTIMx High Resolution Timer instance
08852   * @param  Timer This parameter can be one of the following values:
08853   *         @arg @ref LL_HRTIM_TIMER_MASTER
08854   *         @arg @ref LL_HRTIM_TIMER_A
08855   *         @arg @ref LL_HRTIM_TIMER_B
08856   *         @arg @ref LL_HRTIM_TIMER_C
08857   *         @arg @ref LL_HRTIM_TIMER_D
08858   *         @arg @ref LL_HRTIM_TIMER_E
08859   * @retval None
08860   */
08861 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08862 {
08863   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08864   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08865                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08866   SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
08867 }
08868
08869 /**
08870   * @brief  Disable the compare 1 interrupt for a given timer.
08871   * @rmtoll MDIER        MCMP1IE           LL_HRTIM_DisableIT_CMP1\n
08872   *         TIMxDIER     CMP1IE            LL_HRTIM_DisableIT_CMP1
08873   * @param  HRTIMx High Resolution Timer instance
08874   * @param  Timer This parameter can be one of the following values:
08875   *         @arg @ref LL_HRTIM_TIMER_MASTER
08876   *         @arg @ref LL_HRTIM_TIMER_A
08877   *         @arg @ref LL_HRTIM_TIMER_B
08878   *         @arg @ref LL_HRTIM_TIMER_C
08879   *         @arg @ref LL_HRTIM_TIMER_D
08880   *         @arg @ref LL_HRTIM_TIMER_E
08881   * @retval None
08882   */
08883 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08884 {
08885   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08886   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08887                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08888   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
08889 }
08890
08891 /**
08892   * @brief  Indicate whether the compare 1 interrupt is enabled for a given timer.
08893   * @rmtoll MDIER        MCMP1IE           LL_HRTIM_IsEnabledIT_CMP1\n
08894   *         TIMxDIER     CMP1IE            LL_HRTIM_IsEnabledIT_CMP1
08895   * @param  HRTIMx High Resolution Timer instance
08896   * @param  Timer This parameter can be one of the following values:
08897   *         @arg @ref LL_HRTIM_TIMER_MASTER
08898   *         @arg @ref LL_HRTIM_TIMER_A
08899   *         @arg @ref LL_HRTIM_TIMER_B
08900   *         @arg @ref LL_HRTIM_TIMER_C
08901   *         @arg @ref LL_HRTIM_TIMER_D
08902   *         @arg @ref LL_HRTIM_TIMER_E
08903   * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
08904   */
08905 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08906 {
08907   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08908   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08909                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08910   return (READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE));
08911 }
08912
08913 /**
08914   * @brief  Enable the compare 2 interrupt for a given timer.
08915   * @rmtoll MDIER        MCMP2IE           LL_HRTIM_EnableIT_CMP2\n
08916   *         TIMxDIER     CMP2IE            LL_HRTIM_EnableIT_CMP2
08917   * @param  HRTIMx High Resolution Timer instance
08918   * @param  Timer This parameter can be one of the following values:
08919   *         @arg @ref LL_HRTIM_TIMER_MASTER
08920   *         @arg @ref LL_HRTIM_TIMER_A
08921   *         @arg @ref LL_HRTIM_TIMER_B
08922   *         @arg @ref LL_HRTIM_TIMER_C
08923   *         @arg @ref LL_HRTIM_TIMER_D
08924   *         @arg @ref LL_HRTIM_TIMER_E
08925   * @retval None
08926   */
08927 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08928 {
08929   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08930   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08931                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08932   SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
08933 }
08934
08935 /**
08936   * @brief  Disable the compare 2 interrupt for a given timer.
08937   * @rmtoll MDIER        MCMP2IE           LL_HRTIM_DisableIT_CMP2\n
08938   *         TIMxDIER     CMP2IE            LL_HRTIM_DisableIT_CMP2
08939   * @param  HRTIMx High Resolution Timer instance
08940   * @param  Timer This parameter can be one of the following values:
08941   *         @arg @ref LL_HRTIM_TIMER_MASTER
08942   *         @arg @ref LL_HRTIM_TIMER_A
08943   *         @arg @ref LL_HRTIM_TIMER_B
08944   *         @arg @ref LL_HRTIM_TIMER_C
08945   *         @arg @ref LL_HRTIM_TIMER_D
08946   *         @arg @ref LL_HRTIM_TIMER_E
08947   * @retval None
08948   */
08949 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08950 {
08951   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08952   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08953                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08954   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
08955 }
08956
08957 /**
08958   * @brief  Indicate whether the compare 2 interrupt is enabled for a given timer.
08959   * @rmtoll MDIER        MCMP2IE           LL_HRTIM_IsEnabledIT_CMP2\n
08960   *         TIMxDIER     CMP2IE            LL_HRTIM_IsEnabledIT_CMP2
08961   * @param  HRTIMx High Resolution Timer instance
08962   * @param  Timer This parameter can be one of the following values:
08963   *         @arg @ref LL_HRTIM_TIMER_MASTER
08964   *         @arg @ref LL_HRTIM_TIMER_A
08965   *         @arg @ref LL_HRTIM_TIMER_B
08966   *         @arg @ref LL_HRTIM_TIMER_C
08967   *         @arg @ref LL_HRTIM_TIMER_D
08968   *         @arg @ref LL_HRTIM_TIMER_E
08969   * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
08970   */
08971 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08972 {
08973   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08974   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08975                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08976   return (READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE));
08977 }
08978
08979 /**
08980   * @brief  Enable the compare 3 interrupt for a given timer.
08981   * @rmtoll MDIER        MCMP3IE           LL_HRTIM_EnableIT_CMP3\n
08982   *         TIMxDIER     CMP3IE            LL_HRTIM_EnableIT_CMP3
08983   * @param  HRTIMx High Resolution Timer instance
08984   * @param  Timer This parameter can be one of the following values:
08985   *         @arg @ref LL_HRTIM_TIMER_MASTER
08986   *         @arg @ref LL_HRTIM_TIMER_A
08987   *         @arg @ref LL_HRTIM_TIMER_B
08988   *         @arg @ref LL_HRTIM_TIMER_C
08989   *         @arg @ref LL_HRTIM_TIMER_D
08990   *         @arg @ref LL_HRTIM_TIMER_E
08991   * @retval None
08992   */
08993 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08994 {
08995   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08996   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08997                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08998   SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
08999 }
09000
09001 /**
09002   * @brief  Disable the compare 3 interrupt for a given timer.
09003   * @rmtoll MDIER        MCMP3IE           LL_HRTIM_DisableIT_CMP3\n
09004   *         TIMxDIER     CMP3IE            LL_HRTIM_DisableIT_CMP3
09005   * @param  HRTIMx High Resolution Timer instance
09006   * @param  Timer This parameter can be one of the following values:
09007   *         @arg @ref LL_HRTIM_TIMER_MASTER
09008   *         @arg @ref LL_HRTIM_TIMER_A
09009   *         @arg @ref LL_HRTIM_TIMER_B
09010   *         @arg @ref LL_HRTIM_TIMER_C
09011   *         @arg @ref LL_HRTIM_TIMER_D
09012   *         @arg @ref LL_HRTIM_TIMER_E
09013   * @retval None
09014   */
09015 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09016 {
09017   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09018   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09019                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09020   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
09021 }
09022
09023 /**
09024   * @brief  Indicate whether the compare 3 interrupt is enabled for a given timer.
09025   * @rmtoll MDIER        MCMP3IE           LL_HRTIM_IsEnabledIT_CMP3\n
09026   *         TIMxDIER     CMP3IE            LL_HRTIM_IsEnabledIT_CMP3
09027   * @param  HRTIMx High Resolution Timer instance
09028   * @param  Timer This parameter can be one of the following values:
09029   *         @arg @ref LL_HRTIM_TIMER_MASTER
09030   *         @arg @ref LL_HRTIM_TIMER_A
09031   *         @arg @ref LL_HRTIM_TIMER_B
09032   *         @arg @ref LL_HRTIM_TIMER_C
09033   *         @arg @ref LL_HRTIM_TIMER_D
09034   *         @arg @ref LL_HRTIM_TIMER_E
09035   * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
09036   */
09037 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09038 {
09039   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09040   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09041                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09042   return (READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE));
09043 }
09044
09045 /**
09046   * @brief  Enable the compare 4 interrupt for a given timer.
09047   * @rmtoll MDIER        MCMP4IE           LL_HRTIM_EnableIT_CMP4\n
09048   *         TIMxDIER     CMP4IE            LL_HRTIM_EnableIT_CMP4
09049   * @param  HRTIMx High Resolution Timer instance
09050   * @param  Timer This parameter can be one of the following values:
09051   *         @arg @ref LL_HRTIM_TIMER_MASTER
09052   *         @arg @ref LL_HRTIM_TIMER_A
09053   *         @arg @ref LL_HRTIM_TIMER_B
09054   *         @arg @ref LL_HRTIM_TIMER_C
09055   *         @arg @ref LL_HRTIM_TIMER_D
09056   *         @arg @ref LL_HRTIM_TIMER_E
09057   * @retval None
09058   */
09059 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09060 {
09061   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09062   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09063                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09064   SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
09065 }
09066
09067 /**
09068   * @brief  Disable the compare 4 interrupt for a given timer.
09069   * @rmtoll MDIER        MCMP4IE           LL_HRTIM_DisableIT_CMP4\n
09070   *         TIMxDIER     CMP4IE            LL_HRTIM_DisableIT_CMP4
09071   * @param  HRTIMx High Resolution Timer instance
09072   * @param  Timer This parameter can be one of the following values:
09073   *         @arg @ref LL_HRTIM_TIMER_MASTER
09074   *         @arg @ref LL_HRTIM_TIMER_A
09075   *         @arg @ref LL_HRTIM_TIMER_B
09076   *         @arg @ref LL_HRTIM_TIMER_C
09077   *         @arg @ref LL_HRTIM_TIMER_D
09078   *         @arg @ref LL_HRTIM_TIMER_E
09079   * @retval None
09080   */
09081 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09082 {
09083   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09084   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09085                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09086   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
09087 }
09088
09089 /**
09090   * @brief  Indicate whether the compare 4 interrupt is enabled for a given timer.
09091   * @rmtoll MDIER        MCMP4IE           LL_HRTIM_IsEnabledIT_CMP4\n
09092   *         TIMxDIER     CMP4IE            LL_HRTIM_IsEnabledIT_CMP4
09093   * @param  HRTIMx High Resolution Timer instance
09094   * @param  Timer This parameter can be one of the following values:
09095   *         @arg @ref LL_HRTIM_TIMER_MASTER
09096   *         @arg @ref LL_HRTIM_TIMER_A
09097   *         @arg @ref LL_HRTIM_TIMER_B
09098   *         @arg @ref LL_HRTIM_TIMER_C
09099   *         @arg @ref LL_HRTIM_TIMER_D
09100   *         @arg @ref LL_HRTIM_TIMER_E
09101   * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
09102   */
09103 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09104 {
09105   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09106   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09107                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09108   return (READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE));
09109 }
09110
09111 /**
09112   * @brief  Enable the capture 1 interrupt for a given timer.
09113   * @rmtoll TIMxDIER     CPT1IE            LL_HRTIM_EnableIT_CPT1
09114   * @param  HRTIMx High Resolution Timer instance
09115   * @param  Timer This parameter can be one of the following values:
09116   *         @arg @ref LL_HRTIM_TIMER_A
09117   *         @arg @ref LL_HRTIM_TIMER_B
09118   *         @arg @ref LL_HRTIM_TIMER_C
09119   *         @arg @ref LL_HRTIM_TIMER_D
09120   *         @arg @ref LL_HRTIM_TIMER_E
09121   * @retval None
09122   */
09123 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09124 {
09125   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09126   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09127                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09128   SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
09129 }
09130
09131 /**
09132   * @brief  Enable the capture 1 interrupt for a given timer.
09133   * @rmtoll TIMxDIER     CPT1IE            LL_HRTIM_DisableIT_CPT1
09134   * @param  HRTIMx High Resolution Timer instance
09135   * @param  Timer This parameter can be one of the following values:
09136   *         @arg @ref LL_HRTIM_TIMER_A
09137   *         @arg @ref LL_HRTIM_TIMER_B
09138   *         @arg @ref LL_HRTIM_TIMER_C
09139   *         @arg @ref LL_HRTIM_TIMER_D
09140   *         @arg @ref LL_HRTIM_TIMER_E
09141   * @retval None
09142   */
09143 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09144 {
09145   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09146   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09147                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09148   CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
09149 }
09150
09151 /**
09152   * @brief  Indicate whether the capture 1 interrupt is enabled for a given timer.
09153   * @rmtoll TIMxDIER     CPT1IE            LL_HRTIM_IsEnabledIT_CPT1
09154   * @param  HRTIMx High Resolution Timer instance
09155   * @param  Timer This parameter can be one of the following values:
09156   *         @arg @ref LL_HRTIM_TIMER_A
09157   *         @arg @ref LL_HRTIM_TIMER_B
09158   *         @arg @ref LL_HRTIM_TIMER_C
09159   *         @arg @ref LL_HRTIM_TIMER_D
09160   *         @arg @ref LL_HRTIM_TIMER_E
09161   * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0).
09162   */
09163 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09164 {
09165   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09166   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09167                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09168   return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE));
09169 }
09170
09171 /**
09172   * @brief  Enable the capture 2 interrupt for a given timer.
09173   * @rmtoll TIMxDIER     CPT2IE            LL_HRTIM_EnableIT_CPT2
09174   * @param  HRTIMx High Resolution Timer instance
09175   * @param  Timer This parameter can be one of the following values:
09176   *         @arg @ref LL_HRTIM_TIMER_A
09177   *         @arg @ref LL_HRTIM_TIMER_B
09178   *         @arg @ref LL_HRTIM_TIMER_C
09179   *         @arg @ref LL_HRTIM_TIMER_D
09180   *         @arg @ref LL_HRTIM_TIMER_E
09181   * @retval None
09182   */
09183 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09184 {
09185   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09186   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09187                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09188   SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
09189 }
09190
09191 /**
09192   * @brief  Enable the capture 2 interrupt for a given timer.
09193   * @rmtoll TIMxDIER     CPT2IE            LL_HRTIM_DisableIT_CPT2
09194   * @param  HRTIMx High Resolution Timer instance
09195   * @param  Timer This parameter can be one of the following values:
09196   *         @arg @ref LL_HRTIM_TIMER_A
09197   *         @arg @ref LL_HRTIM_TIMER_B
09198   *         @arg @ref LL_HRTIM_TIMER_C
09199   *         @arg @ref LL_HRTIM_TIMER_D
09200   *         @arg @ref LL_HRTIM_TIMER_E
09201   * @retval None
09202   */
09203 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09204 {
09205   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09206   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09207                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09208   CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
09209 }
09210
09211 /**
09212   * @brief  Indicate whether the capture 2 interrupt is enabled for a given timer.
09213   * @rmtoll TIMxDIER     CPT2IE            LL_HRTIM_IsEnabledIT_CPT2
09214   * @param  HRTIMx High Resolution Timer instance
09215   * @param  Timer This parameter can be one of the following values:
09216   *         @arg @ref LL_HRTIM_TIMER_A
09217   *         @arg @ref LL_HRTIM_TIMER_B
09218   *         @arg @ref LL_HRTIM_TIMER_C
09219   *         @arg @ref LL_HRTIM_TIMER_D
09220   *         @arg @ref LL_HRTIM_TIMER_E
09221   * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0).
09222   */
09223 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09224 {
09225   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09226   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09227                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09228   return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE));
09229 }
09230
09231 /**
09232   * @brief  Enable the output 1 set interrupt for a given timer.
09233   * @rmtoll TIMxDIER     SET1IE            LL_HRTIM_EnableIT_SET1
09234   * @param  HRTIMx High Resolution Timer instance
09235   * @param  Timer This parameter can be one of the following values:
09236   *         @arg @ref LL_HRTIM_TIMER_A
09237   *         @arg @ref LL_HRTIM_TIMER_B
09238   *         @arg @ref LL_HRTIM_TIMER_C
09239   *         @arg @ref LL_HRTIM_TIMER_D
09240   *         @arg @ref LL_HRTIM_TIMER_E
09241   * @retval None
09242   */
09243 __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09244 {
09245   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09246   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09247                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09248   SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
09249 }
09250
09251 /**
09252   * @brief  Disable the output 1 set interrupt for a given timer.
09253   * @rmtoll TIMxDIER     SET1IE            LL_HRTIM_DisableIT_SET1
09254   * @param  HRTIMx High Resolution Timer instance
09255   * @param  Timer This parameter can be one of the following values:
09256   *         @arg @ref LL_HRTIM_TIMER_A
09257   *         @arg @ref LL_HRTIM_TIMER_B
09258   *         @arg @ref LL_HRTIM_TIMER_C
09259   *         @arg @ref LL_HRTIM_TIMER_D
09260   *         @arg @ref LL_HRTIM_TIMER_E
09261   * @retval None
09262   */
09263 __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09264 {
09265   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09266   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09267                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09268   CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
09269 }
09270
09271 /**
09272   * @brief  Indicate whether the output 1 set interrupt is enabled for a given timer.
09273   * @rmtoll TIMxDIER     SET1IE            LL_HRTIM_IsEnabledIT_SET1
09274   * @param  HRTIMx High Resolution Timer instance
09275   * @param  Timer This parameter can be one of the following values:
09276   *         @arg @ref LL_HRTIM_TIMER_A
09277   *         @arg @ref LL_HRTIM_TIMER_B
09278   *         @arg @ref LL_HRTIM_TIMER_C
09279   *         @arg @ref LL_HRTIM_TIMER_D
09280   *         @arg @ref LL_HRTIM_TIMER_E
09281   * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0).
09282   */
09283 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09284 {
09285   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09286   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09287                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09288   return (READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE));
09289 }
09290
09291 /**
09292   * @brief  Enable the output 1 reset interrupt for a given timer.
09293   * @rmtoll TIMxDIER     RST1IE            LL_HRTIM_EnableIT_RST1
09294   * @param  HRTIMx High Resolution Timer instance
09295   * @param  Timer This parameter can be one of the following values:
09296   *         @arg @ref LL_HRTIM_TIMER_A
09297   *         @arg @ref LL_HRTIM_TIMER_B
09298   *         @arg @ref LL_HRTIM_TIMER_C
09299   *         @arg @ref LL_HRTIM_TIMER_D
09300   *         @arg @ref LL_HRTIM_TIMER_E
09301   * @retval None
09302   */
09303 __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09304 {
09305   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09306   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09307                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09308   SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
09309 }
09310
09311 /**
09312   * @brief  Disable the output 1 reset interrupt for a given timer.
09313   * @rmtoll TIMxDIER     RST1IE            LL_HRTIM_DisableIT_RST1
09314   * @param  HRTIMx High Resolution Timer instance
09315   * @param  Timer This parameter can be one of the following values:
09316   *         @arg @ref LL_HRTIM_TIMER_A
09317   *         @arg @ref LL_HRTIM_TIMER_B
09318   *         @arg @ref LL_HRTIM_TIMER_C
09319   *         @arg @ref LL_HRTIM_TIMER_D
09320   *         @arg @ref LL_HRTIM_TIMER_E
09321   * @retval None
09322   */
09323 __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09324 {
09325   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09326   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09327                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09328   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
09329 }
09330
09331 /**
09332   * @brief  Indicate whether the output 1 reset interrupt is enabled for a given timer.
09333   * @rmtoll TIMxDIER     RST1IE            LL_HRTIM_IsEnabledIT_RST1
09334   * @param  HRTIMx High Resolution Timer instance
09335   * @param  Timer This parameter can be one of the following values:
09336   *         @arg @ref LL_HRTIM_TIMER_A
09337   *         @arg @ref LL_HRTIM_TIMER_B
09338   *         @arg @ref LL_HRTIM_TIMER_C
09339   *         @arg @ref LL_HRTIM_TIMER_D
09340   *         @arg @ref LL_HRTIM_TIMER_E
09341   * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0).
09342   */
09343 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09344 {
09345   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09346   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09347                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09348   return (READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE));
09349 }
09350
09351 /**
09352   * @brief  Enable the output 2 set interrupt for a given timer.
09353   * @rmtoll TIMxDIER     SET2IE            LL_HRTIM_EnableIT_SET2
09354   * @param  HRTIMx High Resolution Timer instance
09355   * @param  Timer This parameter can be one of the following values:
09356   *         @arg @ref LL_HRTIM_TIMER_A
09357   *         @arg @ref LL_HRTIM_TIMER_B
09358   *         @arg @ref LL_HRTIM_TIMER_C
09359   *         @arg @ref LL_HRTIM_TIMER_D
09360   *         @arg @ref LL_HRTIM_TIMER_E
09361   * @retval None
09362   */
09363 __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09364 {
09365   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09366   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09367                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09368   SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
09369 }
09370
09371 /**
09372   * @brief  Disable the output 2 set interrupt for a given timer.
09373   * @rmtoll TIMxDIER     SET2IE            LL_HRTIM_DisableIT_SET2
09374   * @param  HRTIMx High Resolution Timer instance
09375   * @param  Timer This parameter can be one of the following values:
09376   *         @arg @ref LL_HRTIM_TIMER_A
09377   *         @arg @ref LL_HRTIM_TIMER_B
09378   *         @arg @ref LL_HRTIM_TIMER_C
09379   *         @arg @ref LL_HRTIM_TIMER_D
09380   *         @arg @ref LL_HRTIM_TIMER_E
09381   * @retval None
09382   */
09383 __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09384 {
09385   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09386   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09387                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09388   CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
09389 }
09390
09391 /**
09392   * @brief  Indicate whether the output 2 set interrupt is enabled for a given timer.
09393   * @rmtoll TIMxDIER     SET2IE            LL_HRTIM_IsEnabledIT_SET2
09394   * @param  HRTIMx High Resolution Timer instance
09395   * @param  Timer This parameter can be one of the following values:
09396   *         @arg @ref LL_HRTIM_TIMER_A
09397   *         @arg @ref LL_HRTIM_TIMER_B
09398   *         @arg @ref LL_HRTIM_TIMER_C
09399   *         @arg @ref LL_HRTIM_TIMER_D
09400   *         @arg @ref LL_HRTIM_TIMER_E
09401   * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0).
09402   */
09403 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09404 {
09405   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09406   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09407                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09408   return (READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE));
09409 }
09410
09411 /**
09412   * @brief  Enable the output 2 reset interrupt for a given timer.
09413   * @rmtoll TIMxDIER     RST2IE            LL_HRTIM_EnableIT_RST2
09414   * @param  HRTIMx High Resolution Timer instance
09415   * @param  Timer This parameter can be one of the following values:
09416   *         @arg @ref LL_HRTIM_TIMER_A
09417   *         @arg @ref LL_HRTIM_TIMER_B
09418   *         @arg @ref LL_HRTIM_TIMER_C
09419   *         @arg @ref LL_HRTIM_TIMER_D
09420   *         @arg @ref LL_HRTIM_TIMER_E
09421   * @retval None
09422   */
09423 __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09424 {
09425   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09426   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09427                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09428   SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
09429 }
09430
09431 /**
09432   * @brief  Disable the output 2 reset interrupt for a given timer.
09433   * @rmtoll TIMxDIER     RST2IE            LL_HRTIM_DisableIT_RST2
09434   * @param  HRTIMx High Resolution Timer instance
09435   * @param  Timer This parameter can be one of the following values:
09436   *         @arg @ref LL_HRTIM_TIMER_A
09437   *         @arg @ref LL_HRTIM_TIMER_B
09438   *         @arg @ref LL_HRTIM_TIMER_C
09439   *         @arg @ref LL_HRTIM_TIMER_D
09440   *         @arg @ref LL_HRTIM_TIMER_E
09441   * @retval None
09442   */
09443 __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09444 {
09445   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09446   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09447                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09448   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
09449 }
09450
09451 /**
09452   * @brief  Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer.
09453   * @rmtoll TIMxDIER     RST2IE            LL_HRTIM_DisableIT_RST2
09454   * @param  HRTIMx High Resolution Timer instance
09455   * @param  Timer This parameter can be one of the following values:
09456   *         @arg @ref LL_HRTIM_TIMER_A
09457   *         @arg @ref LL_HRTIM_TIMER_B
09458   *         @arg @ref LL_HRTIM_TIMER_C
09459   *         @arg @ref LL_HRTIM_TIMER_D
09460   *         @arg @ref LL_HRTIM_TIMER_E
09461   * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0).
09462   */
09463 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09464 {
09465   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09466   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09467                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09468   return (READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE));
09469 }
09470
09471 /**
09472   * @brief  Enable the reset/roll-over interrupt for a given timer.
09473   * @rmtoll TIMxDIER     RSTIE            LL_HRTIM_EnableIT_RST
09474   * @param  HRTIMx High Resolution Timer instance
09475   * @param  Timer This parameter can be one of the following values:
09476   *         @arg @ref LL_HRTIM_TIMER_A
09477   *         @arg @ref LL_HRTIM_TIMER_B
09478   *         @arg @ref LL_HRTIM_TIMER_C
09479   *         @arg @ref LL_HRTIM_TIMER_D
09480   *         @arg @ref LL_HRTIM_TIMER_E
09481   * @retval None
09482   */
09483 __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09484 {
09485   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09486   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09487                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09488   SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
09489 }
09490
09491 /**
09492   * @brief  Disable the reset/roll-over interrupt for a given timer.
09493   * @rmtoll TIMxDIER     RSTIE            LL_HRTIM_DisableIT_RST
09494   * @param  HRTIMx High Resolution Timer instance
09495   * @param  Timer This parameter can be one of the following values:
09496   *         @arg @ref LL_HRTIM_TIMER_A
09497   *         @arg @ref LL_HRTIM_TIMER_B
09498   *         @arg @ref LL_HRTIM_TIMER_C
09499   *         @arg @ref LL_HRTIM_TIMER_D
09500   *         @arg @ref LL_HRTIM_TIMER_E
09501   * @retval None
09502   */
09503 __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09504 {
09505   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09506   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09507                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09508   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
09509 }
09510
09511 /**
09512   * @brief  Indicate whether the reset/roll-over interrupt is enabled for a given timer.
09513   * @rmtoll TIMxDIER     RSTIE            LL_HRTIM_IsEnabledIT_RST
09514   * @param  HRTIMx High Resolution Timer instance
09515   * @param  Timer This parameter can be one of the following values:
09516   *         @arg @ref LL_HRTIM_TIMER_A
09517   *         @arg @ref LL_HRTIM_TIMER_B
09518   *         @arg @ref LL_HRTIM_TIMER_C
09519   *         @arg @ref LL_HRTIM_TIMER_D
09520   *         @arg @ref LL_HRTIM_TIMER_E
09521   * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0).
09522   */
09523 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09524 {
09525   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09526   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09527                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09528   return (READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE));
09529 }
09530
09531 /**
09532   * @brief  Enable the delayed protection interrupt for a given timer.
09533   * @rmtoll TIMxDIER     DLYPRTIE            LL_HRTIM_EnableIT_DLYPRT
09534   * @param  HRTIMx High Resolution Timer instance
09535   * @param  Timer This parameter can be one of the following values:
09536   *         @arg @ref LL_HRTIM_TIMER_A
09537   *         @arg @ref LL_HRTIM_TIMER_B
09538   *         @arg @ref LL_HRTIM_TIMER_C
09539   *         @arg @ref LL_HRTIM_TIMER_D
09540   *         @arg @ref LL_HRTIM_TIMER_E
09541   * @retval None
09542   */
09543 __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09544 {
09545   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09546   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09547                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09548   SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
09549 }
09550
09551 /**
09552   * @brief  Disable the delayed protection interrupt for a given timer.
09553   * @rmtoll TIMxDIER     DLYPRTIE            LL_HRTIM_DisableIT_DLYPRT
09554   * @param  HRTIMx High Resolution Timer instance
09555   * @param  Timer This parameter can be one of the following values:
09556   *         @arg @ref LL_HRTIM_TIMER_A
09557   *         @arg @ref LL_HRTIM_TIMER_B
09558   *         @arg @ref LL_HRTIM_TIMER_C
09559   *         @arg @ref LL_HRTIM_TIMER_D
09560   *         @arg @ref LL_HRTIM_TIMER_E
09561   * @retval None
09562   */
09563 __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09564 {
09565   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09566   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09567                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09568   CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
09569 }
09570
09571 /**
09572   * @brief  Indicate whether the delayed protection interrupt is enabled for a given timer.
09573   * @rmtoll TIMxDIER     DLYPRTIE            LL_HRTIM_IsEnabledIT_DLYPRT
09574   * @param  HRTIMx High Resolution Timer instance
09575   * @param  Timer This parameter can be one of the following values:
09576   *         @arg @ref LL_HRTIM_TIMER_A
09577   *         @arg @ref LL_HRTIM_TIMER_B
09578   *         @arg @ref LL_HRTIM_TIMER_C
09579   *         @arg @ref LL_HRTIM_TIMER_D
09580   *         @arg @ref LL_HRTIM_TIMER_E
09581   * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0).
09582   */
09583 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09584 {
09585   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09586   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09587                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09588   return (READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE));
09589 }
09590
09591 /**
09592   * @}
09593   */
09594
09595 /** @defgroup HRTIM_EF_DMA_Management DMA_Management
09596   * @{
09597   */
09598
09599 /**
09600   * @brief  Enable the synchronization input DMA request.
09601   * @rmtoll MDIER     SYNCDE            LL_HRTIM_EnableDMAReq_SYNC
09602   * @param  HRTIMx High Resolution Timer instance
09603   * @retval None
09604   */
09605 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
09606 {
09607   SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
09608 }
09609
09610 /**
09611   * @brief  Disable the synchronization input DMA request
09612   * @rmtoll MDIER     SYNCDE            LL_HRTIM_DisableDMAReq_SYNC
09613   * @param  HRTIMx High Resolution Timer instance
09614   * @retval None
09615   */
09616 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
09617 {
09618   CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
09619 }
09620
09621 /**
09622   * @brief  Indicate whether the synchronization input DMA request is enabled.
09623   * @rmtoll MDIER     SYNCDE            LL_HRTIM_IsEnabledDMAReq_SYNC
09624   * @param  HRTIMx High Resolution Timer instance
09625   * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0).
09626   */
09627 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
09628 {
09629   return (READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE));
09630 }
09631
09632 /**
09633   * @brief  Enable the update DMA request for a given timer.
09634   * @rmtoll MDIER        MUPDDE            LL_HRTIM_EnableDMAReq_UPDATE\n
09635   *         TIMxDIER     UPDDE             LL_HRTIM_EnableDMAReq_UPDATE
09636   * @param  HRTIMx High Resolution Timer instance
09637   * @param  Timer This parameter can be one of the following values:
09638   *         @arg @ref LL_HRTIM_TIMER_MASTER
09639   *         @arg @ref LL_HRTIM_TIMER_A
09640   *         @arg @ref LL_HRTIM_TIMER_B
09641   *         @arg @ref LL_HRTIM_TIMER_C
09642   *         @arg @ref LL_HRTIM_TIMER_D
09643   *         @arg @ref LL_HRTIM_TIMER_E
09644   * @retval None
09645   */
09646 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09647 {
09648   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09649   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09650                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09651   SET_BIT(*pReg, HRTIM_MDIER_MUPDDE);
09652 }
09653
09654 /**
09655   * @brief  Disable the update DMA request for a given timer.
09656   * @rmtoll MDIER        MUPDDE            LL_HRTIM_DisableDMAReq_UPDATE\n
09657   *         TIMxDIER     UPDDE             LL_HRTIM_DisableDMAReq_UPDATE
09658   * @param  HRTIMx High Resolution Timer instance
09659   * @param  Timer This parameter can be one of the following values:
09660   *         @arg @ref LL_HRTIM_TIMER_MASTER
09661   *         @arg @ref LL_HRTIM_TIMER_A
09662   *         @arg @ref LL_HRTIM_TIMER_B
09663   *         @arg @ref LL_HRTIM_TIMER_C
09664   *         @arg @ref LL_HRTIM_TIMER_D
09665   *         @arg @ref LL_HRTIM_TIMER_E
09666   * @retval None
09667   */
09668 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09669 {
09670   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09671   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09672                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09673   CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE);
09674 }
09675
09676 /**
09677   * @brief  Indicate whether the update DMA request is enabled for a given timer.
09678   * @rmtoll MDIER        MUPDDE            LL_HRTIM_IsEnabledDMAReq_UPDATE\n
09679   *         TIMxDIER     UPDDE             LL_HRTIM_IsEnabledDMAReq_UPDATE
09680   * @param  HRTIMx High Resolution Timer instance
09681   * @param  Timer This parameter can be one of the following values:
09682   *         @arg @ref LL_HRTIM_TIMER_MASTER
09683   *         @arg @ref LL_HRTIM_TIMER_A
09684   *         @arg @ref LL_HRTIM_TIMER_B
09685   *         @arg @ref LL_HRTIM_TIMER_C
09686   *         @arg @ref LL_HRTIM_TIMER_D
09687   *         @arg @ref LL_HRTIM_TIMER_E
09688   * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
09689   */
09690 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09691 {
09692   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09693   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09694                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09695   return (READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE));
09696 }
09697
09698 /**
09699   * @brief  Enable the repetition DMA request for a given timer.
09700   * @rmtoll MDIER        MREPDE            LL_HRTIM_EnableDMAReq_REP\n
09701   *         TIMxDIER     REPDE             LL_HRTIM_EnableDMAReq_REP
09702   * @param  HRTIMx High Resolution Timer instance
09703   * @param  Timer This parameter can be one of the following values:
09704   *         @arg @ref LL_HRTIM_TIMER_MASTER
09705   *         @arg @ref LL_HRTIM_TIMER_A
09706   *         @arg @ref LL_HRTIM_TIMER_B
09707   *         @arg @ref LL_HRTIM_TIMER_C
09708   *         @arg @ref LL_HRTIM_TIMER_D
09709   *         @arg @ref LL_HRTIM_TIMER_E
09710   * @retval None
09711   */
09712 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09713 {
09714   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09715   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09716                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09717   SET_BIT(*pReg, HRTIM_MDIER_MREPDE);
09718 }
09719
09720 /**
09721   * @brief  Disable the repetition DMA request for a given timer.
09722   * @rmtoll MDIER        MREPDE            LL_HRTIM_DisableDMAReq_REP\n
09723   *         TIMxDIER     REPDE             LL_HRTIM_DisableDMAReq_REP
09724   * @param  HRTIMx High Resolution Timer instance
09725   * @param  Timer This parameter can be one of the following values:
09726   *         @arg @ref LL_HRTIM_TIMER_MASTER
09727   *         @arg @ref LL_HRTIM_TIMER_A
09728   *         @arg @ref LL_HRTIM_TIMER_B
09729   *         @arg @ref LL_HRTIM_TIMER_C
09730   *         @arg @ref LL_HRTIM_TIMER_D
09731   *         @arg @ref LL_HRTIM_TIMER_E
09732   * @retval None
09733   */
09734 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09735 {
09736   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09737   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09738                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09739   CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE);
09740 }
09741
09742 /**
09743   * @brief  Indicate whether the repetition DMA request is enabled for a given timer.
09744   * @rmtoll MDIER        MREPDE            LL_HRTIM_IsEnabledDMAReq_REP\n
09745   *         TIMxDIER     REPDE             LL_HRTIM_IsEnabledDMAReq_REP
09746   * @param  HRTIMx High Resolution Timer instance
09747   * @param  Timer This parameter can be one of the following values:
09748   *         @arg @ref LL_HRTIM_TIMER_MASTER
09749   *         @arg @ref LL_HRTIM_TIMER_A
09750   *         @arg @ref LL_HRTIM_TIMER_B
09751   *         @arg @ref LL_HRTIM_TIMER_C
09752   *         @arg @ref LL_HRTIM_TIMER_D
09753   *         @arg @ref LL_HRTIM_TIMER_E
09754   * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
09755   */
09756 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09757 {
09758   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09759   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09760                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09761   return (READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE));
09762 }
09763
09764 /**
09765   * @brief  Enable the compare 1 DMA request for a given timer.
09766   * @rmtoll MDIER        MCMP1DE            LL_HRTIM_EnableDMAReq_CMP1\n
09767   *         TIMxDIER     CMP1DE             LL_HRTIM_EnableDMAReq_CMP1
09768   * @param  HRTIMx High Resolution Timer instance
09769   * @param  Timer This parameter can be one of the following values:
09770   *         @arg @ref LL_HRTIM_TIMER_MASTER
09771   *         @arg @ref LL_HRTIM_TIMER_A
09772   *         @arg @ref LL_HRTIM_TIMER_B
09773   *         @arg @ref LL_HRTIM_TIMER_C
09774   *         @arg @ref LL_HRTIM_TIMER_D
09775   *         @arg @ref LL_HRTIM_TIMER_E
09776   * @retval None
09777   */
09778 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09779 {
09780   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09781   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09782                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09783   SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
09784 }
09785
09786 /**
09787   * @brief  Disable the compare 1 DMA request for a given timer.
09788   * @rmtoll MDIER        MCMP1DE            LL_HRTIM_DisableDMAReq_CMP1\n
09789   *         TIMxDIER     CMP1DE             LL_HRTIM_DisableDMAReq_CMP1
09790   * @param  HRTIMx High Resolution Timer instance
09791   * @param  Timer This parameter can be one of the following values:
09792   *         @arg @ref LL_HRTIM_TIMER_MASTER
09793   *         @arg @ref LL_HRTIM_TIMER_A
09794   *         @arg @ref LL_HRTIM_TIMER_B
09795   *         @arg @ref LL_HRTIM_TIMER_C
09796   *         @arg @ref LL_HRTIM_TIMER_D
09797   *         @arg @ref LL_HRTIM_TIMER_E
09798   * @retval None
09799   */
09800 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09801 {
09802   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09803   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09804                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09805   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
09806 }
09807
09808 /**
09809   * @brief  Indicate whether the compare 1 DMA request is enabled for a given timer.
09810   * @rmtoll MDIER        MCMP1DE            LL_HRTIM_IsEnabledDMAReq_CMP1\n
09811   *         TIMxDIER     CMP1DE             LL_HRTIM_IsEnabledDMAReq_CMP1
09812   * @param  HRTIMx High Resolution Timer instance
09813   * @param  Timer This parameter can be one of the following values:
09814   *         @arg @ref LL_HRTIM_TIMER_MASTER
09815   *         @arg @ref LL_HRTIM_TIMER_A
09816   *         @arg @ref LL_HRTIM_TIMER_B
09817   *         @arg @ref LL_HRTIM_TIMER_C
09818   *         @arg @ref LL_HRTIM_TIMER_D
09819   *         @arg @ref LL_HRTIM_TIMER_E
09820   * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
09821   */
09822 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09823 {
09824   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09825   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09826                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09827   return (READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE));
09828 }
09829
09830 /**
09831   * @brief  Enable the compare 2 DMA request for a given timer.
09832   * @rmtoll MDIER        MCMP2DE            LL_HRTIM_EnableDMAReq_CMP2\n
09833   *         TIMxDIER     CMP2DE             LL_HRTIM_EnableDMAReq_CMP2
09834   * @param  HRTIMx High Resolution Timer instance
09835   * @param  Timer This parameter can be one of the following values:
09836   *         @arg @ref LL_HRTIM_TIMER_MASTER
09837   *         @arg @ref LL_HRTIM_TIMER_A
09838   *         @arg @ref LL_HRTIM_TIMER_B
09839   *         @arg @ref LL_HRTIM_TIMER_C
09840   *         @arg @ref LL_HRTIM_TIMER_D
09841   *         @arg @ref LL_HRTIM_TIMER_E
09842   * @retval None
09843   */
09844 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09845 {
09846   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09847   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09848                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09849   SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
09850 }
09851
09852 /**
09853   * @brief  Disable the compare 2 DMA request for a given timer.
09854   * @rmtoll MDIER        MCMP2DE            LL_HRTIM_DisableDMAReq_CMP2\n
09855   *         TIMxDIER     CMP2DE             LL_HRTIM_DisableDMAReq_CMP2
09856   * @param  HRTIMx High Resolution Timer instance
09857   * @param  Timer This parameter can be one of the following values:
09858   *         @arg @ref LL_HRTIM_TIMER_MASTER
09859   *         @arg @ref LL_HRTIM_TIMER_A
09860   *         @arg @ref LL_HRTIM_TIMER_B
09861   *         @arg @ref LL_HRTIM_TIMER_C
09862   *         @arg @ref LL_HRTIM_TIMER_D
09863   *         @arg @ref LL_HRTIM_TIMER_E
09864   * @retval None
09865   */
09866 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09867 {
09868   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09869   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09870                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09871   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
09872 }
09873
09874 /**
09875   * @brief  Indicate whether the compare 2 DMA request is enabled for a given timer.
09876   * @rmtoll MDIER        MCMP2DE            LL_HRTIM_IsEnabledDMAReq_CMP2\n
09877   *         TIMxDIER     CMP2DE             LL_HRTIM_IsEnabledDMAReq_CMP2
09878   * @param  HRTIMx High Resolution Timer instance
09879   * @param  Timer This parameter can be one of the following values:
09880   *         @arg @ref LL_HRTIM_TIMER_MASTER
09881   *         @arg @ref LL_HRTIM_TIMER_A
09882   *         @arg @ref LL_HRTIM_TIMER_B
09883   *         @arg @ref LL_HRTIM_TIMER_C
09884   *         @arg @ref LL_HRTIM_TIMER_D
09885   *         @arg @ref LL_HRTIM_TIMER_E
09886   * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
09887   */
09888 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09889 {
09890   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09891   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09892                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09893   return (READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE));
09894 }
09895
09896 /**
09897   * @brief  Enable the compare 3 DMA request for a given timer.
09898   * @rmtoll MDIER        MCMP3DE            LL_HRTIM_EnableDMAReq_CMP3\n
09899   *         TIMxDIER     CMP3DE             LL_HRTIM_EnableDMAReq_CMP3
09900   * @param  HRTIMx High Resolution Timer instance
09901   * @param  Timer This parameter can be one of the following values:
09902   *         @arg @ref LL_HRTIM_TIMER_MASTER
09903   *         @arg @ref LL_HRTIM_TIMER_A
09904   *         @arg @ref LL_HRTIM_TIMER_B
09905   *         @arg @ref LL_HRTIM_TIMER_C
09906   *         @arg @ref LL_HRTIM_TIMER_D
09907   *         @arg @ref LL_HRTIM_TIMER_E
09908   * @retval None
09909   */
09910 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09911 {
09912   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09913   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09914                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09915   SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
09916 }
09917
09918 /**
09919   * @brief  Disable the compare 3 DMA request for a given timer.
09920   * @rmtoll MDIER        MCMP3DE            LL_HRTIM_DisableDMAReq_CMP3\n
09921   *         TIMxDIER     CMP3DE             LL_HRTIM_DisableDMAReq_CMP3
09922   * @param  HRTIMx High Resolution Timer instance
09923   * @param  Timer This parameter can be one of the following values:
09924   *         @arg @ref LL_HRTIM_TIMER_MASTER
09925   *         @arg @ref LL_HRTIM_TIMER_A
09926   *         @arg @ref LL_HRTIM_TIMER_B
09927   *         @arg @ref LL_HRTIM_TIMER_C
09928   *         @arg @ref LL_HRTIM_TIMER_D
09929   *         @arg @ref LL_HRTIM_TIMER_E
09930   * @retval None
09931   */
09932 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09933 {
09934   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09935   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09936                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09937   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
09938 }
09939
09940 /**
09941   * @brief  Indicate whether the compare 3 DMA request is enabled for a given timer.
09942   * @rmtoll MDIER        MCMP3DE            LL_HRTIM_IsEnabledDMAReq_CMP3\n
09943   *         TIMxDIER     CMP3DE             LL_HRTIM_IsEnabledDMAReq_CMP3
09944   * @param  HRTIMx High Resolution Timer instance
09945   * @param  Timer This parameter can be one of the following values:
09946   *         @arg @ref LL_HRTIM_TIMER_MASTER
09947   *         @arg @ref LL_HRTIM_TIMER_A
09948   *         @arg @ref LL_HRTIM_TIMER_B
09949   *         @arg @ref LL_HRTIM_TIMER_C
09950   *         @arg @ref LL_HRTIM_TIMER_D
09951   *         @arg @ref LL_HRTIM_TIMER_E
09952   * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
09953   */
09954 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09955 {
09956   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09957   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09958                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09959   return (READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE));
09960 }
09961
09962 /**
09963   * @brief  Enable the compare 4 DMA request for a given timer.
09964   * @rmtoll MDIER        MCMP4DE            LL_HRTIM_EnableDMAReq_CMP4\n
09965   *         TIMxDIER     CMP4DE             LL_HRTIM_EnableDMAReq_CMP4
09966   * @param  HRTIMx High Resolution Timer instance
09967   * @param  Timer This parameter can be one of the following values:
09968   *         @arg @ref LL_HRTIM_TIMER_MASTER
09969   *         @arg @ref LL_HRTIM_TIMER_A
09970   *         @arg @ref LL_HRTIM_TIMER_B
09971   *         @arg @ref LL_HRTIM_TIMER_C
09972   *         @arg @ref LL_HRTIM_TIMER_D
09973   *         @arg @ref LL_HRTIM_TIMER_E
09974   * @retval None
09975   */
09976 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09977 {
09978   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09979   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09980                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09981   SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
09982 }
09983
09984 /**
09985   * @brief  Disable the compare 4 DMA request for a given timer.
09986   * @rmtoll MDIER        MCMP4DE            LL_HRTIM_DisableDMAReq_CMP4\n
09987   *         TIMxDIER     CMP4DE             LL_HRTIM_DisableDMAReq_CMP4
09988   * @param  HRTIMx High Resolution Timer instance
09989   * @param  Timer This parameter can be one of the following values:
09990   *         @arg @ref LL_HRTIM_TIMER_MASTER
09991   *         @arg @ref LL_HRTIM_TIMER_A
09992   *         @arg @ref LL_HRTIM_TIMER_B
09993   *         @arg @ref LL_HRTIM_TIMER_C
09994   *         @arg @ref LL_HRTIM_TIMER_D
09995   *         @arg @ref LL_HRTIM_TIMER_E
09996   * @retval None
09997   */
09998 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09999 {
10000   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10001   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10002                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10003   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
10004 }
10005
10006 /**
10007   * @brief  Indicate whether the compare 4 DMA request is enabled for a given timer.
10008   * @rmtoll MDIER        MCMP4DE            LL_HRTIM_IsEnabledDMAReq_CMP4\n
10009   *         TIMxDIER     CMP4DE             LL_HRTIM_IsEnabledDMAReq_CMP4
10010   * @param  HRTIMx High Resolution Timer instance
10011   * @param  Timer This parameter can be one of the following values:
10012   *         @arg @ref LL_HRTIM_TIMER_MASTER
10013   *         @arg @ref LL_HRTIM_TIMER_A
10014   *         @arg @ref LL_HRTIM_TIMER_B
10015   *         @arg @ref LL_HRTIM_TIMER_C
10016   *         @arg @ref LL_HRTIM_TIMER_D
10017   *         @arg @ref LL_HRTIM_TIMER_E
10018   * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
10019   */
10020 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10021 {
10022   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10023   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10024                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10025   return (READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE));
10026 }
10027
10028 /**
10029   * @brief  Enable the capture 1 DMA request for a given timer.
10030   * @rmtoll TIMxDIER     CPT1DE             LL_HRTIM_EnableDMAReq_CPT1
10031   * @param  HRTIMx High Resolution Timer instance
10032   * @param  Timer This parameter can be one of the following values:
10033   *         @arg @ref LL_HRTIM_TIMER_A
10034   *         @arg @ref LL_HRTIM_TIMER_B
10035   *         @arg @ref LL_HRTIM_TIMER_C
10036   *         @arg @ref LL_HRTIM_TIMER_D
10037   *         @arg @ref LL_HRTIM_TIMER_E
10038   * @retval None
10039   */
10040 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10041 {
10042   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10043   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10044                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10045   SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
10046 }
10047
10048 /**
10049   * @brief  Disable the capture 1 DMA request for a given timer.
10050   * @rmtoll TIMxDIER     CPT1DE             LL_HRTIM_DisableDMAReq_CPT1
10051   * @param  HRTIMx High Resolution Timer instance
10052   * @param  Timer This parameter can be one of the following values:
10053   *         @arg @ref LL_HRTIM_TIMER_A
10054   *         @arg @ref LL_HRTIM_TIMER_B
10055   *         @arg @ref LL_HRTIM_TIMER_C
10056   *         @arg @ref LL_HRTIM_TIMER_D
10057   *         @arg @ref LL_HRTIM_TIMER_E
10058   * @retval None
10059   */
10060 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10061 {
10062   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10063   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10064                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10065   CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
10066 }
10067
10068 /**
10069   * @brief  Indicate whether the capture 1 DMA request is enabled for a given timer.
10070   * @rmtoll TIMxDIER     CPT1DE             LL_HRTIM_IsEnabledDMAReq_CPT1
10071   * @param  HRTIMx High Resolution Timer instance
10072   * @param  Timer This parameter can be one of the following values:
10073   *         @arg @ref LL_HRTIM_TIMER_A
10074   *         @arg @ref LL_HRTIM_TIMER_B
10075   *         @arg @ref LL_HRTIM_TIMER_C
10076   *         @arg @ref LL_HRTIM_TIMER_D
10077   *         @arg @ref LL_HRTIM_TIMER_E
10078   * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0).
10079   */
10080 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10081 {
10082   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10083   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10084                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10085   return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE));
10086 }
10087
10088 /**
10089   * @brief  Enable the capture 2 DMA request for a given timer.
10090   * @rmtoll TIMxDIER     CPT2DE             LL_HRTIM_EnableDMAReq_CPT2
10091   * @param  HRTIMx High Resolution Timer instance
10092   * @param  Timer This parameter can be one of the following values:
10093   *         @arg @ref LL_HRTIM_TIMER_A
10094   *         @arg @ref LL_HRTIM_TIMER_B
10095   *         @arg @ref LL_HRTIM_TIMER_C
10096   *         @arg @ref LL_HRTIM_TIMER_D
10097   *         @arg @ref LL_HRTIM_TIMER_E
10098   * @retval None
10099   */
10100 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10101 {
10102   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10103   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10104                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10105   SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
10106 }
10107
10108 /**
10109   * @brief  Disable the capture 2 DMA request for a given timer.
10110   * @rmtoll TIMxDIER     CPT2DE             LL_HRTIM_DisableDMAReq_CPT2
10111   * @param  HRTIMx High Resolution Timer instance
10112   * @param  Timer This parameter can be one of the following values:
10113   *         @arg @ref LL_HRTIM_TIMER_A
10114   *         @arg @ref LL_HRTIM_TIMER_B
10115   *         @arg @ref LL_HRTIM_TIMER_C
10116   *         @arg @ref LL_HRTIM_TIMER_D
10117   *         @arg @ref LL_HRTIM_TIMER_E
10118   * @retval None
10119   */
10120 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10121 {
10122   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10123   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10124                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10125   CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
10126 }
10127
10128 /**
10129   * @brief  Indicate whether the capture 2 DMA request is enabled for a given timer.
10130   * @rmtoll TIMxDIER     CPT2DE             LL_HRTIM_IsEnabledDMAReq_CPT2
10131   * @param  HRTIMx High Resolution Timer instance
10132   * @param  Timer This parameter can be one of the following values:
10133   *         @arg @ref LL_HRTIM_TIMER_A
10134   *         @arg @ref LL_HRTIM_TIMER_B
10135   *         @arg @ref LL_HRTIM_TIMER_C
10136   *         @arg @ref LL_HRTIM_TIMER_D
10137   *         @arg @ref LL_HRTIM_TIMER_E
10138   * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0).
10139   */
10140 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10141 {
10142   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10143   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10144                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10145   return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE));
10146 }
10147
10148 /**
10149   * @brief  Enable the output 1 set  DMA request for a given timer.
10150   * @rmtoll TIMxDIER     SET1DE             LL_HRTIM_EnableDMAReq_SET1
10151   * @param  HRTIMx High Resolution Timer instance
10152   * @param  Timer This parameter can be one of the following values:
10153   *         @arg @ref LL_HRTIM_TIMER_A
10154   *         @arg @ref LL_HRTIM_TIMER_B
10155   *         @arg @ref LL_HRTIM_TIMER_C
10156   *         @arg @ref LL_HRTIM_TIMER_D
10157   *         @arg @ref LL_HRTIM_TIMER_E
10158   * @retval None
10159   */
10160 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10161 {
10162   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10163   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10164                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10165   SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
10166 }
10167
10168 /**
10169   * @brief  Disable the output 1 set  DMA request for a given timer.
10170   * @rmtoll TIMxDIER     SET1DE             LL_HRTIM_DisableDMAReq_SET1
10171   * @param  HRTIMx High Resolution Timer instance
10172   * @param  Timer This parameter can be one of the following values:
10173   *         @arg @ref LL_HRTIM_TIMER_A
10174   *         @arg @ref LL_HRTIM_TIMER_B
10175   *         @arg @ref LL_HRTIM_TIMER_C
10176   *         @arg @ref LL_HRTIM_TIMER_D
10177   *         @arg @ref LL_HRTIM_TIMER_E
10178   * @retval None
10179   */
10180 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10181 {
10182   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10183   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10184                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10185   CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
10186 }
10187
10188 /**
10189   * @brief  Indicate whether the output 1 set  DMA request is enabled for a given timer.
10190   * @rmtoll TIMxDIER     SET1DE             LL_HRTIM_IsEnabledDMAReq_SET1
10191   * @param  HRTIMx High Resolution Timer instance
10192   * @param  Timer This parameter can be one of the following values:
10193   *         @arg @ref LL_HRTIM_TIMER_A
10194   *         @arg @ref LL_HRTIM_TIMER_B
10195   *         @arg @ref LL_HRTIM_TIMER_C
10196   *         @arg @ref LL_HRTIM_TIMER_D
10197   *         @arg @ref LL_HRTIM_TIMER_E
10198   * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0).
10199   */
10200 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10201 {
10202   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10203   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10204                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10205   return (READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE));
10206 }
10207
10208 /**
10209   * @brief  Enable the output 1 reset  DMA request for a given timer.
10210   * @rmtoll TIMxDIER     RST1DE             LL_HRTIM_EnableDMAReq_RST1
10211   * @param  HRTIMx High Resolution Timer instance
10212   * @param  Timer This parameter can be one of the following values:
10213   *         @arg @ref LL_HRTIM_TIMER_A
10214   *         @arg @ref LL_HRTIM_TIMER_B
10215   *         @arg @ref LL_HRTIM_TIMER_C
10216   *         @arg @ref LL_HRTIM_TIMER_D
10217   *         @arg @ref LL_HRTIM_TIMER_E
10218   * @retval None
10219   */
10220 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10221 {
10222   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10223   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10224                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10225   SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
10226 }
10227
10228 /**
10229   * @brief  Disable the output 1 reset  DMA request for a given timer.
10230   * @rmtoll TIMxDIER     RST1DE             LL_HRTIM_DisableDMAReq_RST1
10231   * @param  HRTIMx High Resolution Timer instance
10232   * @param  Timer This parameter can be one of the following values:
10233   *         @arg @ref LL_HRTIM_TIMER_A
10234   *         @arg @ref LL_HRTIM_TIMER_B
10235   *         @arg @ref LL_HRTIM_TIMER_C
10236   *         @arg @ref LL_HRTIM_TIMER_D
10237   *         @arg @ref LL_HRTIM_TIMER_E
10238   * @retval None
10239   */
10240 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10241 {
10242   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10243   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10244                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10245   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
10246 }
10247
10248 /**
10249   * @brief  Indicate whether the output 1 reset interrupt is enabled for a given timer.
10250   * @rmtoll TIMxDIER     RST1DE             LL_HRTIM_IsEnabledDMAReq_RST1
10251   * @param  HRTIMx High Resolution Timer instance
10252   * @param  Timer This parameter can be one of the following values:
10253   *         @arg @ref LL_HRTIM_TIMER_A
10254   *         @arg @ref LL_HRTIM_TIMER_B
10255   *         @arg @ref LL_HRTIM_TIMER_C
10256   *         @arg @ref LL_HRTIM_TIMER_D
10257   *         @arg @ref LL_HRTIM_TIMER_E
10258   * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0).
10259   */
10260 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10261 {
10262   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10263   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10264                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10265   return (READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE));
10266 }
10267
10268 /**
10269   * @brief  Enable the output 2 set  DMA request for a given timer.
10270   * @rmtoll TIMxDIER     SET2DE             LL_HRTIM_EnableDMAReq_SET2
10271   * @param  HRTIMx High Resolution Timer instance
10272   * @param  Timer This parameter can be one of the following values:
10273   *         @arg @ref LL_HRTIM_TIMER_A
10274   *         @arg @ref LL_HRTIM_TIMER_B
10275   *         @arg @ref LL_HRTIM_TIMER_C
10276   *         @arg @ref LL_HRTIM_TIMER_D
10277   *         @arg @ref LL_HRTIM_TIMER_E
10278   * @retval None
10279   */
10280 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10281 {
10282   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10283   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10284                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10285   SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
10286 }
10287
10288 /**
10289   * @brief  Disable the output 2 set  DMA request for a given timer.
10290   * @rmtoll TIMxDIER     SET2DE             LL_HRTIM_DisableDMAReq_SET2
10291   * @param  HRTIMx High Resolution Timer instance
10292   * @param  Timer This parameter can be one of the following values:
10293   *         @arg @ref LL_HRTIM_TIMER_A
10294   *         @arg @ref LL_HRTIM_TIMER_B
10295   *         @arg @ref LL_HRTIM_TIMER_C
10296   *         @arg @ref LL_HRTIM_TIMER_D
10297   *         @arg @ref LL_HRTIM_TIMER_E
10298   * @retval None
10299   */
10300 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10301 {
10302   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10303   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10304                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10305   CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
10306 }
10307
10308 /**
10309   * @brief  Indicate whether the output 2 set  DMA request is enabled for a given timer.
10310   * @rmtoll TIMxDIER     SET2DE             LL_HRTIM_IsEnabledDMAReq_SET2
10311   * @param  HRTIMx High Resolution Timer instance
10312   * @param  Timer This parameter can be one of the following values:
10313   *         @arg @ref LL_HRTIM_TIMER_A
10314   *         @arg @ref LL_HRTIM_TIMER_B
10315   *         @arg @ref LL_HRTIM_TIMER_C
10316   *         @arg @ref LL_HRTIM_TIMER_D
10317   *         @arg @ref LL_HRTIM_TIMER_E
10318   * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0).
10319   */
10320 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10321 {
10322   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10323   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10324                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10325   return (READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE));
10326 }
10327
10328 /**
10329   * @brief  Enable the output 2 reset  DMA request for a given timer.
10330   * @rmtoll TIMxDIER     RST2DE             LL_HRTIM_EnableDMAReq_RST2
10331   * @param  HRTIMx High Resolution Timer instance
10332   * @param  Timer This parameter can be one of the following values:
10333   *         @arg @ref LL_HRTIM_TIMER_A
10334   *         @arg @ref LL_HRTIM_TIMER_B
10335   *         @arg @ref LL_HRTIM_TIMER_C
10336   *         @arg @ref LL_HRTIM_TIMER_D
10337   *         @arg @ref LL_HRTIM_TIMER_E
10338   * @retval None
10339   */
10340 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10341 {
10342   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10343   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10344                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10345   SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
10346 }
10347
10348 /**
10349   * @brief  Disable the output 2 reset  DMA request for a given timer.
10350   * @rmtoll TIMxDIER     RST2DE             LL_HRTIM_DisableDMAReq_RST2
10351   * @param  HRTIMx High Resolution Timer instance
10352   * @param  Timer This parameter can be one of the following values:
10353   *         @arg @ref LL_HRTIM_TIMER_A
10354   *         @arg @ref LL_HRTIM_TIMER_B
10355   *         @arg @ref LL_HRTIM_TIMER_C
10356   *         @arg @ref LL_HRTIM_TIMER_D
10357   *         @arg @ref LL_HRTIM_TIMER_E
10358   * @retval None
10359   */
10360 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10361 {
10362   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10363   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10364                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10365   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
10366 }
10367
10368 /**
10369   * @brief  Indicate whether the output 2 reset  DMA request is enabled for a given timer.
10370   * @rmtoll TIMxDIER     RST2DE             LL_HRTIM_IsEnabledDMAReq_RST2
10371   * @param  HRTIMx High Resolution Timer instance
10372   * @param  Timer This parameter can be one of the following values:
10373   *         @arg @ref LL_HRTIM_TIMER_A
10374   *         @arg @ref LL_HRTIM_TIMER_B
10375   *         @arg @ref LL_HRTIM_TIMER_C
10376   *         @arg @ref LL_HRTIM_TIMER_D
10377   *         @arg @ref LL_HRTIM_TIMER_E
10378   * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0).
10379   */
10380 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10381 {
10382   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10383   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10384                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10385   return (READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE));
10386 }
10387
10388 /**
10389   * @brief  Enable the reset/roll-over DMA request for a given timer.
10390   * @rmtoll TIMxDIER     RSTDE             LL_HRTIM_EnableDMAReq_RST
10391   * @param  HRTIMx High Resolution Timer instance
10392   * @param  Timer This parameter can be one of the following values:
10393   *         @arg @ref LL_HRTIM_TIMER_A
10394   *         @arg @ref LL_HRTIM_TIMER_B
10395   *         @arg @ref LL_HRTIM_TIMER_C
10396   *         @arg @ref LL_HRTIM_TIMER_D
10397   *         @arg @ref LL_HRTIM_TIMER_E
10398   * @retval None
10399   */
10400 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10401 {
10402   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10403   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10404                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10405   SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
10406 }
10407
10408 /**
10409   * @brief  Disable the reset/roll-over DMA request for a given timer.
10410   * @rmtoll TIMxDIER     RSTDE             LL_HRTIM_DisableDMAReq_RST
10411   * @param  HRTIMx High Resolution Timer instance
10412   * @param  Timer This parameter can be one of the following values:
10413   *         @arg @ref LL_HRTIM_TIMER_A
10414   *         @arg @ref LL_HRTIM_TIMER_B
10415   *         @arg @ref LL_HRTIM_TIMER_C
10416   *         @arg @ref LL_HRTIM_TIMER_D
10417   *         @arg @ref LL_HRTIM_TIMER_E
10418   * @retval None
10419   */
10420 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10421 {
10422   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10423   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10424                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10425   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
10426 }
10427
10428 /**
10429   * @brief  Indicate whether the reset/roll-over DMA request is enabled for a given timer.
10430   * @rmtoll TIMxDIER     RSTDE             LL_HRTIM_IsEnabledDMAReq_RST
10431   * @param  HRTIMx High Resolution Timer instance
10432   * @param  Timer This parameter can be one of the following values:
10433   *         @arg @ref LL_HRTIM_TIMER_A
10434   *         @arg @ref LL_HRTIM_TIMER_B
10435   *         @arg @ref LL_HRTIM_TIMER_C
10436   *         @arg @ref LL_HRTIM_TIMER_D
10437   *         @arg @ref LL_HRTIM_TIMER_E
10438   * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0).
10439   */
10440 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10441 {
10442   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10443   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10444                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10445   return (READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE));
10446 }
10447
10448 /**
10449   * @brief  Enable the delayed protection DMA request for a given timer.
10450   * @rmtoll TIMxDIER     DLYPRTDE             LL_HRTIM_EnableDMAReq_DLYPRT
10451   * @param  HRTIMx High Resolution Timer instance
10452   * @param  Timer This parameter can be one of the following values:
10453   *         @arg @ref LL_HRTIM_TIMER_A
10454   *         @arg @ref LL_HRTIM_TIMER_B
10455   *         @arg @ref LL_HRTIM_TIMER_C
10456   *         @arg @ref LL_HRTIM_TIMER_D
10457   *         @arg @ref LL_HRTIM_TIMER_E
10458   * @retval None
10459   */
10460 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10461 {
10462   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10463   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10464                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10465   SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
10466 }
10467
10468 /**
10469   * @brief  Disable the delayed protection DMA request for a given timer.
10470   * @rmtoll TIMxDIER     DLYPRTDE             LL_HRTIM_DisableDMAReq_DLYPRT
10471   * @param  HRTIMx High Resolution Timer instance
10472   * @param  Timer This parameter can be one of the following values:
10473   *         @arg @ref LL_HRTIM_TIMER_A
10474   *         @arg @ref LL_HRTIM_TIMER_B
10475   *         @arg @ref LL_HRTIM_TIMER_C
10476   *         @arg @ref LL_HRTIM_TIMER_D
10477   *         @arg @ref LL_HRTIM_TIMER_E
10478   * @retval None
10479   */
10480 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10481 {
10482   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10483   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10484                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10485   CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
10486 }
10487
10488 /**
10489   * @brief  Indicate whether the delayed protection DMA request is enabled for a given timer.
10490   * @rmtoll TIMxDIER     DLYPRTDE             LL_HRTIM_IsEnabledDMAReq_DLYPRT
10491   * @param  HRTIMx High Resolution Timer instance
10492   * @param  Timer This parameter can be one of the following values:
10493   *         @arg @ref LL_HRTIM_TIMER_A
10494   *         @arg @ref LL_HRTIM_TIMER_B
10495   *         @arg @ref LL_HRTIM_TIMER_C
10496   *         @arg @ref LL_HRTIM_TIMER_D
10497   *         @arg @ref LL_HRTIM_TIMER_E
10498   * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0).
10499   */
10500 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10501 {
10502   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10503   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10504                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10505   return (READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE));
10506 }
10507
10508 /**
10509   * @}
10510   */
10511
10512 #if defined(USE_FULL_LL_DRIVER)
10513 /** @defgroup HRTIM_LL_EF_Init Initialisation and deinitialisation functions
10514   * @{
10515   */
10516 ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);
10517 /**
10518   * @}
10519   */
10520 #endif /* USE_FULL_LL_DRIVER */
10521
10522 /**
10523   * @}
10524   */
10525
10526 /**
10527   * @}
10528   */
10529
10530 #endif /* HRTIM1 */
10531
10532 /**
10533   * @}
10534   */
10535
10536 #ifdef __cplusplus
10537 }
10538 #endif
10539
10540 #endif /* __STM32F3xx_LL_HRTIM_H */
10541
10542 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_i2c.c Source File

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stm32f3xx_ll_i2c.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_i2c.c
00004   * @author  MCD Application Team
00005   * @brief   I2C LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 #if defined(USE_FULL_LL_DRIVER)
00036
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f3xx_ll_i2c.h"
00039 #include "stm32f3xx_ll_bus.h"
00040 #ifdef  USE_FULL_ASSERT
00041 #include "stm32_assert.h"
00042 #else
00043 #define assert_param(expr) ((void)0U)
00044 #endif
00045
00046 /** @addtogroup STM32F3xx_LL_Driver
00047   * @{
00048   */
00049
00050 #if defined (I2C1) || defined (I2C2) || defined (I2C3)
00051
00052 /** @defgroup I2C_LL I2C
00053   * @{
00054   */
00055
00056 /* Private types -------------------------------------------------------------*/
00057 /* Private variables ---------------------------------------------------------*/
00058 /* Private constants ---------------------------------------------------------*/
00059 /* Private macros ------------------------------------------------------------*/
00060 /** @addtogroup I2C_LL_Private_Macros
00061   * @{
00062   */
00063
00064 #define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)    (((__VALUE__) == LL_I2C_MODE_I2C)          || \
00065                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
00066                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
00067                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
00068
00069 #define IS_LL_I2C_ANALOG_FILTER(__VALUE__)      (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
00070                                                  ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
00071
00072 #define IS_LL_I2C_DIGITAL_FILTER(__VALUE__)     ((__VALUE__) <= 0x0000000FU)
00073
00074 #define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= 0x000003FFU)
00075
00076 #define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)   (((__VALUE__) == LL_I2C_ACK) || \
00077                                                  ((__VALUE__) == LL_I2C_NACK))
00078
00079 #define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)       (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
00080                                                  ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
00081 /**
00082   * @}
00083   */
00084
00085 /* Private function prototypes -----------------------------------------------*/
00086
00087 /* Exported functions --------------------------------------------------------*/
00088 /** @addtogroup I2C_LL_Exported_Functions
00089   * @{
00090   */
00091
00092 /** @addtogroup I2C_LL_EF_Init
00093   * @{
00094   */
00095
00096 /**
00097   * @brief  De-initialize the I2C registers to their default reset values.
00098   * @param  I2Cx I2C Instance.
00099   * @retval An ErrorStatus enumeration value:
00100   *          - SUCCESS: I2C registers are de-initialized
00101   *          - ERROR: I2C registers are not de-initialized
00102   */
00103 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
00104 {
00105   ErrorStatus status = SUCCESS;
00106
00107   /* Check the I2C Instance I2Cx */
00108   assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
00109
00110   if (I2Cx == I2C1)
00111   {
00112     /* Force reset of I2C clock */
00113     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
00114
00115     /* Release reset of I2C clock */
00116     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
00117   }
00118 #if defined(I2C2)
00119   else if (I2Cx == I2C2)
00120   {
00121     /* Force reset of I2C clock */
00122     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
00123
00124     /* Release reset of I2C clock */
00125     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
00126
00127   }
00128 #endif
00129 #if defined(I2C3)
00130   else if (I2Cx == I2C3)
00131   {
00132     /* Force reset of I2C clock */
00133     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
00134
00135     /* Release reset of I2C clock */
00136     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
00137   }
00138 #endif
00139   else
00140   {
00141     status = ERROR;
00142   }
00143
00144   return status;
00145 }
00146
00147 /**
00148   * @brief  Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
00149   * @param  I2Cx I2C Instance.
00150   * @param  I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
00151   * @retval An ErrorStatus enumeration value:
00152   *          - SUCCESS: I2C registers are initialized
00153   *          - ERROR: Not applicable
00154   */
00155 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
00156 {
00157   /* Check the I2C Instance I2Cx */
00158   assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
00159
00160   /* Check the I2C parameters from I2C_InitStruct */
00161   assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
00162   assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
00163   assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
00164   assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
00165   assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
00166   assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
00167
00168   /* Disable the selected I2Cx Peripheral */
00169   LL_I2C_Disable(I2Cx);
00170
00171   /*---------------------------- I2Cx CR1 Configuration ------------------------
00172    * Configure the analog and digital noise filters with parameters :
00173    * - AnalogFilter: I2C_CR1_ANFOFF bit
00174    * - DigitalFilter: I2C_CR1_DNF[3:0] bits
00175    */
00176   LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
00177
00178   /*---------------------------- I2Cx TIMINGR Configuration --------------------
00179    * Configure the SDA setup, hold time and the SCL high, low period with parameter :
00180    * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
00181    *           I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
00182    */
00183   LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
00184
00185   /* Enable the selected I2Cx Peripheral */
00186   LL_I2C_Enable(I2Cx);
00187
00188   /*---------------------------- I2Cx OAR1 Configuration -----------------------
00189    * Disable, Configure and Enable I2Cx device own address 1 with parameters :
00190    * - OwnAddress1:  I2C_OAR1_OA1[9:0] bits
00191    * - OwnAddrSize:  I2C_OAR1_OA1MODE bit
00192    */
00193   LL_I2C_DisableOwnAddress1(I2Cx);
00194   LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
00195
00196   /* OwnAdress1 == 0 is reserved for General Call address */
00197   if (I2C_InitStruct->OwnAddress1 != 0U)
00198   {
00199     LL_I2C_EnableOwnAddress1(I2Cx);
00200   }
00201
00202   /*---------------------------- I2Cx MODE Configuration -----------------------
00203   * Configure I2Cx peripheral mode with parameter :
00204    * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
00205    */
00206   LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
00207
00208   /*---------------------------- I2Cx CR2 Configuration ------------------------
00209    * Configure the ACKnowledge or Non ACKnowledge condition
00210    * after the address receive match code or next received byte with parameter :
00211    * - TypeAcknowledge: I2C_CR2_NACK bit
00212    */
00213   LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
00214
00215   return SUCCESS;
00216 }
00217
00218 /**
00219   * @brief  Set each @ref LL_I2C_InitTypeDef field to default value.
00220   * @param  I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
00221   * @retval None
00222   */
00223 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
00224 {
00225   /* Set I2C_InitStruct fields to default values */
00226   I2C_InitStruct->PeripheralMode  = LL_I2C_MODE_I2C;
00227   I2C_InitStruct->Timing          = 0U;
00228   I2C_InitStruct->AnalogFilter    = LL_I2C_ANALOGFILTER_ENABLE;
00229   I2C_InitStruct->DigitalFilter   = 0U;
00230   I2C_InitStruct->OwnAddress1     = 0U;
00231   I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
00232   I2C_InitStruct->OwnAddrSize     = LL_I2C_OWNADDRESS1_7BIT;
00233 }
00234
00235 /**
00236   * @}
00237   */
00238
00239 /**
00240   * @}
00241   */
00242
00243 /**
00244   * @}
00245   */
00246
00247 #endif /* I2C1 || I2C2 || I2C3 */
00248
00249 /**
00250   * @}
00251   */
00252
00253 #endif /* USE_FULL_LL_DRIVER */
00254
00255 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_i2c.h Source File

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stm32f3xx_ll_i2c.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_i2c.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2C LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_I2C_H
00038 #define __STM32F3xx_LL_I2C_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined (I2C1) || defined (I2C2) || defined (I2C3)
00052
00053 /** @defgroup I2C_LL I2C
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059
00060 /* Private constants ---------------------------------------------------------*/
00061 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
00062   * @{
00063   */
00064 /**
00065   * @}
00066   */
00067
00068 /* Private macros ------------------------------------------------------------*/
00069 #if defined(USE_FULL_LL_DRIVER)
00070 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
00071   * @{
00072   */
00073 /**
00074   * @}
00075   */
00076 #endif /*USE_FULL_LL_DRIVER*/
00077
00078 /* Exported types ------------------------------------------------------------*/
00079 #if defined(USE_FULL_LL_DRIVER)
00080 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
00081   * @{
00082   */
00083 typedef struct
00084 {
00085   uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
00086                                      This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
00087
00088                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
00089
00090   uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
00091                                      This parameter must be set by referring to the STM32CubeMX Tool and
00092                                      the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
00093
00094                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
00095
00096   uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
00097                                      This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
00098
00099                                      This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
00100
00101   uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
00102                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
00103
00104                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
00105
00106   uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
00107                                      This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
00108
00109                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
00110
00111   uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
00112                                      This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
00113
00114                                      This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
00115
00116   uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
00117                                      This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
00118
00119                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
00120 } LL_I2C_InitTypeDef;
00121 /**
00122   * @}
00123   */
00124 #endif /*USE_FULL_LL_DRIVER*/
00125
00126 /* Exported constants --------------------------------------------------------*/
00127 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
00128   * @{
00129   */
00130
00131 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
00132   * @brief    Flags defines which can be used with LL_I2C_WriteReg function
00133   * @{
00134   */
00135 #define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */
00136 #define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
00137 #define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */
00138 #define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */
00139 #define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
00140 #define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
00141 #define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */
00142 #define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
00143 #define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */
00144 /**
00145   * @}
00146   */
00147
00148 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
00149   * @brief    Flags defines which can be used with LL_I2C_ReadReg function
00150   * @{
00151   */
00152 #define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */
00153 #define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */
00154 #define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */
00155 #define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */
00156 #define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
00157 #define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */
00158 #define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */
00159 #define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */
00160 #define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */
00161 #define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */
00162 #define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
00163 #define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
00164 #define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
00165 #define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
00166 #define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup I2C_LL_EC_IT IT Defines
00172   * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
00173   * @{
00174   */
00175 #define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */
00176 #define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */
00177 #define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
00178 #define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
00179 #define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
00180 #define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
00181 #define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */
00182 /**
00183   * @}
00184   */
00185
00186 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
00187   * @{
00188   */
00189 #define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                                    */
00190 #define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge                              */
00191 #define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode (Default address not acknowledge) */
00192 #define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge                    */
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
00198   * @{
00199   */
00200 #define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */
00201 #define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
00202 /**
00203   * @}
00204   */
00205
00206 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
00207   * @{
00208   */
00209 #define LL_I2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */
00210 #define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
00211 /**
00212   * @}
00213   */
00214
00215 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
00216   * @{
00217   */
00218 #define LL_I2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */
00219 #define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
00220 /**
00221   * @}
00222   */
00223
00224 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
00225   * @{
00226   */
00227 #define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                                */
00228 #define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared.                */
00229 #define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared.                */
00230 #define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared.                */
00231 #define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared.                */
00232 #define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared.                */
00233 #define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.                  */
00234 #define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done. All Address2 are acknowledged.*/
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
00240   * @{
00241   */
00242 #define LL_I2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */
00243 #define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
00249   * @{
00250   */
00251 #define LL_I2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */
00252 #define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
00258   * @{
00259   */
00260 #define LL_I2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */
00261 #define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
00267   * @{
00268   */
00269 #define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD                                      /*!< Enable I2C Reload mode.                                   */
00270 #define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND                                     /*!< Enable I2C Automatic end mode with no HW PEC comparison.  */
00271 #define LL_I2C_MODE_SOFTEND                 0x00000000U                                         /*!< Enable I2C Software end mode with no HW PEC comparison.   */
00272 #define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD                                  /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
00273 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND                                 /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
00274 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND                                 /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
00275 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
00276 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
00282   * @{
00283   */
00284 #define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U                                                  /*!< Don't Generate Stop and Start condition.                */
00285 #define LL_I2C_GENERATE_STOP                I2C_CR2_STOP                                                 /*!< Generate Stop condition (Size should be set to 0).      */
00286 #define LL_I2C_GENERATE_START_READ          (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Start for read request.                        */
00287 #define LL_I2C_GENERATE_START_WRITE         I2C_CR2_START                                                /*!< Generate Start for write request.                       */
00288 #define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Restart for read request, slave 7Bit address.  */
00289 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE  I2C_CR2_START                                                /*!< Generate Restart for write request, slave 7Bit address. */
00290 #define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
00291 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START                                                /*!< Generate Restart for write request, slave 10Bit address.*/
00292 /**
00293   * @}
00294   */
00295
00296 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
00297   * @{
00298   */
00299 #define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master, slave enters receiver mode.  */
00300 #define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master, slave enters transmitter mode.*/
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
00306   * @{
00307   */
00308 #define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for transmission */
00309 #define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for reception */
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
00315   * @{
00316   */
00317 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect SCL low level timeout.              */
00318 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
00324   * @{
00325   */
00326 #define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                                   /*!< TimeoutA enable bit                                */
00327 #define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                                     /*!< TimeoutB (extended clock) enable bit               */
00328 #define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
00329 /**
00330   * @}
00331   */
00332
00333 /**
00334   * @}
00335   */
00336
00337 /* Exported macro ------------------------------------------------------------*/
00338 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
00339   * @{
00340   */
00341
00342 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
00343   * @{
00344   */
00345
00346 /**
00347   * @brief  Write a value in I2C register
00348   * @param  __INSTANCE__ I2C Instance
00349   * @param  __REG__ Register to be written
00350   * @param  __VALUE__ Value to be written in the register
00351   * @retval None
00352   */
00353 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00354
00355 /**
00356   * @brief  Read a value in I2C register
00357   * @param  __INSTANCE__ I2C Instance
00358   * @param  __REG__ Register to be read
00359   * @retval Register value
00360   */
00361 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
00367   * @{
00368   */
00369 /**
00370   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
00371   * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.
00372   * @param  __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
00373   * @param  __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
00374   * @param  __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
00375   * @param  __CLOCK_LOW_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
00376   * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
00377   */
00378 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)   \
00379         ((((uint32_t)(__PRESCALER__)         << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
00380          (((uint32_t)(__DATA_SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
00381          (((uint32_t)(__DATA_HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
00382          (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
00383          (((uint32_t)(__CLOCK_LOW_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
00384 /**
00385   * @}
00386   */
00387
00388 /**
00389   * @}
00390   */
00391
00392 /* Exported functions --------------------------------------------------------*/
00393 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
00394   * @{
00395   */
00396
00397 /** @defgroup I2C_LL_EF_Configuration Configuration
00398   * @{
00399   */
00400
00401 /**
00402   * @brief  Enable I2C peripheral (PE = 1).
00403   * @rmtoll CR1          PE            LL_I2C_Enable
00404   * @param  I2Cx I2C Instance.
00405   * @retval None
00406   */
00407 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
00408 {
00409   SET_BIT(I2Cx->CR1, I2C_CR1_PE);
00410 }
00411
00412 /**
00413   * @brief  Disable I2C peripheral (PE = 0).
00414   * @note   When PE = 0, the I2C SCL and SDA lines are released.
00415   *         Internal state machines and status bits are put back to their reset value.
00416   *         When cleared, PE must be kept low for at least 3 APB clock cycles.
00417   * @rmtoll CR1          PE            LL_I2C_Disable
00418   * @param  I2Cx I2C Instance.
00419   * @retval None
00420   */
00421 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
00422 {
00423   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
00424 }
00425
00426 /**
00427   * @brief  Check if the I2C peripheral is enabled or disabled.
00428   * @rmtoll CR1          PE            LL_I2C_IsEnabled
00429   * @param  I2Cx I2C Instance.
00430   * @retval State of bit (1 or 0).
00431   */
00432 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
00433 {
00434   return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
00435 }
00436
00437 /**
00438   * @brief  Configure Noise Filters (Analog and Digital).
00439   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
00440   *         The filters can only be programmed when the I2C is disabled (PE = 0).
00441   * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n
00442   *         CR1          DNF           LL_I2C_ConfigFilters
00443   * @param  I2Cx I2C Instance.
00444   * @param  AnalogFilter This parameter can be one of the following values:
00445   *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
00446   *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
00447   * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
00448   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
00449   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
00450   * @retval None
00451   */
00452 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
00453 {
00454   MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
00455 }
00456
00457 /**
00458   * @brief  Configure Digital Noise Filter.
00459   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
00460   *         This filter can only be programmed when the I2C is disabled (PE = 0).
00461   * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
00462   * @param  I2Cx I2C Instance.
00463   * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
00464   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
00465   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
00466   * @retval None
00467   */
00468 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
00469 {
00470   MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
00471 }
00472
00473 /**
00474   * @brief  Get the current Digital Noise Filter configuration.
00475   * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter
00476   * @param  I2Cx I2C Instance.
00477   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00478   */
00479 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
00480 {
00481   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
00482 }
00483
00484 /**
00485   * @brief  Enable Analog Noise Filter.
00486   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
00487   * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter
00488   * @param  I2Cx I2C Instance.
00489   * @retval None
00490   */
00491 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
00492 {
00493   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
00494 }
00495
00496 /**
00497   * @brief  Disable Analog Noise Filter.
00498   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
00499   * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter
00500   * @param  I2Cx I2C Instance.
00501   * @retval None
00502   */
00503 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
00504 {
00505   SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
00506 }
00507
00508 /**
00509   * @brief  Check if Analog Noise Filter is enabled or disabled.
00510   * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter
00511   * @param  I2Cx I2C Instance.
00512   * @retval State of bit (1 or 0).
00513   */
00514 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
00515 {
00516   return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
00517 }
00518
00519 /**
00520   * @brief  Enable DMA transmission requests.
00521   * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX
00522   * @param  I2Cx I2C Instance.
00523   * @retval None
00524   */
00525 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
00526 {
00527   SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
00528 }
00529
00530 /**
00531   * @brief  Disable DMA transmission requests.
00532   * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX
00533   * @param  I2Cx I2C Instance.
00534   * @retval None
00535   */
00536 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
00537 {
00538   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
00539 }
00540
00541 /**
00542   * @brief  Check if DMA transmission requests are enabled or disabled.
00543   * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX
00544   * @param  I2Cx I2C Instance.
00545   * @retval State of bit (1 or 0).
00546   */
00547 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
00548 {
00549   return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
00550 }
00551
00552 /**
00553   * @brief  Enable DMA reception requests.
00554   * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX
00555   * @param  I2Cx I2C Instance.
00556   * @retval None
00557   */
00558 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
00559 {
00560   SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
00561 }
00562
00563 /**
00564   * @brief  Disable DMA reception requests.
00565   * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX
00566   * @param  I2Cx I2C Instance.
00567   * @retval None
00568   */
00569 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
00570 {
00571   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
00572 }
00573
00574 /**
00575   * @brief  Check if DMA reception requests are enabled or disabled.
00576   * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX
00577   * @param  I2Cx I2C Instance.
00578   * @retval State of bit (1 or 0).
00579   */
00580 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
00581 {
00582   return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
00583 }
00584
00585 /**
00586   * @brief  Get the data register address used for DMA transfer
00587   * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n
00588   *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr
00589   * @param  I2Cx I2C Instance
00590   * @param  Direction This parameter can be one of the following values:
00591   *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
00592   *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
00593   * @retval Address of data register
00594   */
00595 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
00596 {
00597   register uint32_t data_reg_addr = 0U;
00598
00599   if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
00600   {
00601     /* return address of TXDR register */
00602     data_reg_addr = (uint32_t) & (I2Cx->TXDR);
00603   }
00604   else
00605   {
00606     /* return address of RXDR register */
00607     data_reg_addr = (uint32_t) & (I2Cx->RXDR);
00608   }
00609
00610   return data_reg_addr;
00611 }
00612
00613 /**
00614   * @brief  Enable Clock stretching.
00615   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00616   * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
00617   * @param  I2Cx I2C Instance.
00618   * @retval None
00619   */
00620 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
00621 {
00622   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
00623 }
00624
00625 /**
00626   * @brief  Disable Clock stretching.
00627   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00628   * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
00629   * @param  I2Cx I2C Instance.
00630   * @retval None
00631   */
00632 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
00633 {
00634   SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
00635 }
00636
00637 /**
00638   * @brief  Check if Clock stretching is enabled or disabled.
00639   * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
00640   * @param  I2Cx I2C Instance.
00641   * @retval State of bit (1 or 0).
00642   */
00643 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
00644 {
00645   return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
00646 }
00647
00648 /**
00649   * @brief  Enable hardware byte control in slave mode.
00650   * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl
00651   * @param  I2Cx I2C Instance.
00652   * @retval None
00653   */
00654 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
00655 {
00656   SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
00657 }
00658
00659 /**
00660   * @brief  Disable hardware byte control in slave mode.
00661   * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl
00662   * @param  I2Cx I2C Instance.
00663   * @retval None
00664   */
00665 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
00666 {
00667   CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
00668 }
00669
00670 /**
00671   * @brief  Check if hardware byte control in slave mode is enabled or disabled.
00672   * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl
00673   * @param  I2Cx I2C Instance.
00674   * @retval State of bit (1 or 0).
00675   */
00676 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
00677 {
00678   return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
00679 }
00680
00681 /**
00682   * @brief  Enable Wakeup from STOP.
00683   * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00684   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00685   * @note   This bit can only be programmed when Digital Filter is disabled.
00686   * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
00687   * @param  I2Cx I2C Instance.
00688   * @retval None
00689   */
00690 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
00691 {
00692   SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
00693 }
00694
00695 /**
00696   * @brief  Disable Wakeup from STOP.
00697   * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00698   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00699   * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
00700   * @param  I2Cx I2C Instance.
00701   * @retval None
00702   */
00703 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
00704 {
00705   CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
00706 }
00707
00708 /**
00709   * @brief  Check if Wakeup from STOP is enabled or disabled.
00710   * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00711   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00712   * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
00713   * @param  I2Cx I2C Instance.
00714   * @retval State of bit (1 or 0).
00715   */
00716 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
00717 {
00718   return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN));
00719 }
00720
00721 /**
00722   * @brief  Enable General Call.
00723   * @note   When enabled the Address 0x00 is ACKed.
00724   * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall
00725   * @param  I2Cx I2C Instance.
00726   * @retval None
00727   */
00728 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
00729 {
00730   SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
00731 }
00732
00733 /**
00734   * @brief  Disable General Call.
00735   * @note   When disabled the Address 0x00 is NACKed.
00736   * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall
00737   * @param  I2Cx I2C Instance.
00738   * @retval None
00739   */
00740 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
00741 {
00742   CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
00743 }
00744
00745 /**
00746   * @brief  Check if General Call is enabled or disabled.
00747   * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall
00748   * @param  I2Cx I2C Instance.
00749   * @retval State of bit (1 or 0).
00750   */
00751 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
00752 {
00753   return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
00754 }
00755
00756 /**
00757   * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
00758   * @note   Changing this bit is not allowed, when the START bit is set.
00759   * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode
00760   * @param  I2Cx I2C Instance.
00761   * @param  AddressingMode This parameter can be one of the following values:
00762   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
00763   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
00764   * @retval None
00765   */
00766 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
00767 {
00768   MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
00769 }
00770
00771 /**
00772   * @brief  Get the Master addressing mode.
00773   * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode
00774   * @param  I2Cx I2C Instance.
00775   * @retval Returned value can be one of the following values:
00776   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
00777   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
00778   */
00779 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
00780 {
00781   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
00782 }
00783
00784 /**
00785   * @brief  Set the Own Address1.
00786   * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n
00787   *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1
00788   * @param  I2Cx I2C Instance.
00789   * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
00790   * @param  OwnAddrSize This parameter can be one of the following values:
00791   *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
00792   *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
00793   * @retval None
00794   */
00795 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
00796 {
00797   MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
00798 }
00799
00800 /**
00801   * @brief  Enable acknowledge on Own Address1 match address.
00802   * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1
00803   * @param  I2Cx I2C Instance.
00804   * @retval None
00805   */
00806 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
00807 {
00808   SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
00809 }
00810
00811 /**
00812   * @brief  Disable acknowledge on Own Address1 match address.
00813   * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1
00814   * @param  I2Cx I2C Instance.
00815   * @retval None
00816   */
00817 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
00818 {
00819   CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
00820 }
00821
00822 /**
00823   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
00824   * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1
00825   * @param  I2Cx I2C Instance.
00826   * @retval State of bit (1 or 0).
00827   */
00828 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
00829 {
00830   return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
00831 }
00832
00833 /**
00834   * @brief  Set the 7bits Own Address2.
00835   * @note   This action has no effect if own address2 is enabled.
00836   * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n
00837   *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2
00838   * @param  I2Cx I2C Instance.
00839   * @param  OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
00840   * @param  OwnAddrMask This parameter can be one of the following values:
00841   *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK
00842   *         @arg @ref LL_I2C_OWNADDRESS2_MASK01
00843   *         @arg @ref LL_I2C_OWNADDRESS2_MASK02
00844   *         @arg @ref LL_I2C_OWNADDRESS2_MASK03
00845   *         @arg @ref LL_I2C_OWNADDRESS2_MASK04
00846   *         @arg @ref LL_I2C_OWNADDRESS2_MASK05
00847   *         @arg @ref LL_I2C_OWNADDRESS2_MASK06
00848   *         @arg @ref LL_I2C_OWNADDRESS2_MASK07
00849   * @retval None
00850   */
00851 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
00852 {
00853   MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
00854 }
00855
00856 /**
00857   * @brief  Enable acknowledge on Own Address2 match address.
00858   * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2
00859   * @param  I2Cx I2C Instance.
00860   * @retval None
00861   */
00862 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
00863 {
00864   SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
00865 }
00866
00867 /**
00868   * @brief  Disable  acknowledge on Own Address2 match address.
00869   * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2
00870   * @param  I2Cx I2C Instance.
00871   * @retval None
00872   */
00873 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
00874 {
00875   CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
00876 }
00877
00878 /**
00879   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
00880   * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2
00881   * @param  I2Cx I2C Instance.
00882   * @retval State of bit (1 or 0).
00883   */
00884 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
00885 {
00886   return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
00887 }
00888
00889 /**
00890   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
00891   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00892   * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming
00893   * @param  I2Cx I2C Instance.
00894   * @param  Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
00895   * @note   This parameter is computed with the STM32CubeMX Tool.
00896   * @retval None
00897   */
00898 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
00899 {
00900   WRITE_REG(I2Cx->TIMINGR, Timing);
00901 }
00902
00903 /**
00904   * @brief  Get the Timing Prescaler setting.
00905   * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler
00906   * @param  I2Cx I2C Instance.
00907   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00908   */
00909 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
00910 {
00911   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
00912 }
00913
00914 /**
00915   * @brief  Get the SCL low period setting.
00916   * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod
00917   * @param  I2Cx I2C Instance.
00918   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
00919   */
00920 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
00921 {
00922   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
00923 }
00924
00925 /**
00926   * @brief  Get the SCL high period setting.
00927   * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod
00928   * @param  I2Cx I2C Instance.
00929   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
00930   */
00931 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
00932 {
00933   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
00934 }
00935
00936 /**
00937   * @brief  Get the SDA hold time.
00938   * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime
00939   * @param  I2Cx I2C Instance.
00940   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00941   */
00942 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
00943 {
00944   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
00945 }
00946
00947 /**
00948   * @brief  Get the SDA setup time.
00949   * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime
00950   * @param  I2Cx I2C Instance.
00951   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00952   */
00953 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
00954 {
00955   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
00956 }
00957
00958 /**
00959   * @brief  Configure peripheral mode.
00960   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00961   *         SMBus feature is supported by the I2Cx Instance.
00962   * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
00963   *         CR1          SMBDEN        LL_I2C_SetMode
00964   * @param  I2Cx I2C Instance.
00965   * @param  PeripheralMode This parameter can be one of the following values:
00966   *         @arg @ref LL_I2C_MODE_I2C
00967   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
00968   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
00969   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
00970   * @retval None
00971   */
00972 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
00973 {
00974   MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
00975 }
00976
00977 /**
00978   * @brief  Get peripheral mode.
00979   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00980   *         SMBus feature is supported by the I2Cx Instance.
00981   * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
00982   *         CR1          SMBDEN        LL_I2C_GetMode
00983   * @param  I2Cx I2C Instance.
00984   * @retval Returned value can be one of the following values:
00985   *         @arg @ref LL_I2C_MODE_I2C
00986   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
00987   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
00988   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
00989   */
00990 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
00991 {
00992   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
00993 }
00994
00995 /**
00996   * @brief  Enable SMBus alert (Host or Device mode)
00997   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00998   *         SMBus feature is supported by the I2Cx Instance.
00999   * @note   SMBus Device mode:
01000   *         - SMBus Alert pin is drived low and
01001   *           Alert Response Address Header acknowledge is enabled.
01002   *         SMBus Host mode:
01003   *         - SMBus Alert pin management is supported.
01004   * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert
01005   * @param  I2Cx I2C Instance.
01006   * @retval None
01007   */
01008 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
01009 {
01010   SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
01011 }
01012
01013 /**
01014   * @brief  Disable SMBus alert (Host or Device mode)
01015   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01016   *         SMBus feature is supported by the I2Cx Instance.
01017   * @note   SMBus Device mode:
01018   *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
01019   *           Alert Response Address Header acknowledge is disabled.
01020   *         SMBus Host mode:
01021   *         - SMBus Alert pin management is not supported.
01022   * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert
01023   * @param  I2Cx I2C Instance.
01024   * @retval None
01025   */
01026 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
01027 {
01028   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
01029 }
01030
01031 /**
01032   * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
01033   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01034   *         SMBus feature is supported by the I2Cx Instance.
01035   * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
01036   * @param  I2Cx I2C Instance.
01037   * @retval State of bit (1 or 0).
01038   */
01039 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
01040 {
01041   return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
01042 }
01043
01044 /**
01045   * @brief  Enable SMBus Packet Error Calculation (PEC).
01046   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01047   *         SMBus feature is supported by the I2Cx Instance.
01048   * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
01049   * @param  I2Cx I2C Instance.
01050   * @retval None
01051   */
01052 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
01053 {
01054   SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
01055 }
01056
01057 /**
01058   * @brief  Disable SMBus Packet Error Calculation (PEC).
01059   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01060   *         SMBus feature is supported by the I2Cx Instance.
01061   * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
01062   * @param  I2Cx I2C Instance.
01063   * @retval None
01064   */
01065 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
01066 {
01067   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
01068 }
01069
01070 /**
01071   * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
01072   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01073   *         SMBus feature is supported by the I2Cx Instance.
01074   * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
01075   * @param  I2Cx I2C Instance.
01076   * @retval State of bit (1 or 0).
01077   */
01078 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
01079 {
01080   return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
01081 }
01082
01083 /**
01084   * @brief  Configure the SMBus Clock Timeout.
01085   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01086   *         SMBus feature is supported by the I2Cx Instance.
01087   * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
01088   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
01089   *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n
01090   *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout
01091   * @param  I2Cx I2C Instance.
01092   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01093   * @param  TimeoutAMode This parameter can be one of the following values:
01094   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01095   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01096   * @param  TimeoutB
01097   * @retval None
01098   */
01099 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
01100                                                uint32_t TimeoutB)
01101 {
01102   MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
01103              TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
01104 }
01105
01106 /**
01107   * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
01108   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01109   *         SMBus feature is supported by the I2Cx Instance.
01110   * @note   These bits can only be programmed when TimeoutA is disabled.
01111   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
01112   * @param  I2Cx I2C Instance.
01113   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01114   * @retval None
01115   */
01116 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
01117 {
01118   WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
01119 }
01120
01121 /**
01122   * @brief  Get the SMBus Clock TimeoutA setting.
01123   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01124   *         SMBus feature is supported by the I2Cx Instance.
01125   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
01126   * @param  I2Cx I2C Instance.
01127   * @retval Value between Min_Data=0 and Max_Data=0xFFF
01128   */
01129 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
01130 {
01131   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
01132 }
01133
01134 /**
01135   * @brief  Set the SMBus Clock TimeoutA mode.
01136   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01137   *         SMBus feature is supported by the I2Cx Instance.
01138   * @note   This bit can only be programmed when TimeoutA is disabled.
01139   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
01140   * @param  I2Cx I2C Instance.
01141   * @param  TimeoutAMode This parameter can be one of the following values:
01142   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01143   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01144   * @retval None
01145   */
01146 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
01147 {
01148   WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
01149 }
01150
01151 /**
01152   * @brief  Get the SMBus Clock TimeoutA mode.
01153   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01154   *         SMBus feature is supported by the I2Cx Instance.
01155   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
01156   * @param  I2Cx I2C Instance.
01157   * @retval Returned value can be one of the following values:
01158   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01159   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01160   */
01161 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
01162 {
01163   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
01164 }
01165
01166 /**
01167   * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
01168   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01169   *         SMBus feature is supported by the I2Cx Instance.
01170   * @note   These bits can only be programmed when TimeoutB is disabled.
01171   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
01172   * @param  I2Cx I2C Instance.
01173   * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01174   * @retval None
01175   */
01176 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
01177 {
01178   WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
01179 }
01180
01181 /**
01182   * @brief  Get the SMBus Extented Cumulative Clock TimeoutB setting.
01183   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01184   *         SMBus feature is supported by the I2Cx Instance.
01185   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
01186   * @param  I2Cx I2C Instance.
01187   * @retval Value between Min_Data=0 and Max_Data=0xFFF
01188   */
01189 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
01190 {
01191   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
01192 }
01193
01194 /**
01195   * @brief  Enable the SMBus Clock Timeout.
01196   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01197   *         SMBus feature is supported by the I2Cx Instance.
01198   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
01199   *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
01200   * @param  I2Cx I2C Instance.
01201   * @param  ClockTimeout This parameter can be one of the following values:
01202   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01203   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01204   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01205   * @retval None
01206   */
01207 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01208 {
01209   SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
01210 }
01211
01212 /**
01213   * @brief  Disable the SMBus Clock Timeout.
01214   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01215   *         SMBus feature is supported by the I2Cx Instance.
01216   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
01217   *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
01218   * @param  I2Cx I2C Instance.
01219   * @param  ClockTimeout This parameter can be one of the following values:
01220   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01221   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01222   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01223   * @retval None
01224   */
01225 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01226 {
01227   CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
01228 }
01229
01230 /**
01231   * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
01232   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01233   *         SMBus feature is supported by the I2Cx Instance.
01234   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
01235   *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
01236   * @param  I2Cx I2C Instance.
01237   * @param  ClockTimeout This parameter can be one of the following values:
01238   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01239   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01240   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01241   * @retval State of bit (1 or 0).
01242   */
01243 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01244 {
01245   return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
01246 }
01247
01248 /**
01249   * @}
01250   */
01251
01252 /** @defgroup I2C_LL_EF_IT_Management IT_Management
01253   * @{
01254   */
01255
01256 /**
01257   * @brief  Enable TXIS interrupt.
01258   * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX
01259   * @param  I2Cx I2C Instance.
01260   * @retval None
01261   */
01262 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
01263 {
01264   SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
01265 }
01266
01267 /**
01268   * @brief  Disable TXIS interrupt.
01269   * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX
01270   * @param  I2Cx I2C Instance.
01271   * @retval None
01272   */
01273 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
01274 {
01275   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
01276 }
01277
01278 /**
01279   * @brief  Check if the TXIS Interrupt is enabled or disabled.
01280   * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX
01281   * @param  I2Cx I2C Instance.
01282   * @retval State of bit (1 or 0).
01283   */
01284 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
01285 {
01286   return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
01287 }
01288
01289 /**
01290   * @brief  Enable RXNE interrupt.
01291   * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX
01292   * @param  I2Cx I2C Instance.
01293   * @retval None
01294   */
01295 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
01296 {
01297   SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
01298 }
01299
01300 /**
01301   * @brief  Disable RXNE interrupt.
01302   * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX
01303   * @param  I2Cx I2C Instance.
01304   * @retval None
01305   */
01306 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
01307 {
01308   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
01309 }
01310
01311 /**
01312   * @brief  Check if the RXNE Interrupt is enabled or disabled.
01313   * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX
01314   * @param  I2Cx I2C Instance.
01315   * @retval State of bit (1 or 0).
01316   */
01317 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
01318 {
01319   return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
01320 }
01321
01322 /**
01323   * @brief  Enable Address match interrupt (slave mode only).
01324   * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR
01325   * @param  I2Cx I2C Instance.
01326   * @retval None
01327   */
01328 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
01329 {
01330   SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
01331 }
01332
01333 /**
01334   * @brief  Disable Address match interrupt (slave mode only).
01335   * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR
01336   * @param  I2Cx I2C Instance.
01337   * @retval None
01338   */
01339 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
01340 {
01341   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
01342 }
01343
01344 /**
01345   * @brief  Check if Address match interrupt is enabled or disabled.
01346   * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR
01347   * @param  I2Cx I2C Instance.
01348   * @retval State of bit (1 or 0).
01349   */
01350 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
01351 {
01352   return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
01353 }
01354
01355 /**
01356   * @brief  Enable Not acknowledge received interrupt.
01357   * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK
01358   * @param  I2Cx I2C Instance.
01359   * @retval None
01360   */
01361 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
01362 {
01363   SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
01364 }
01365
01366 /**
01367   * @brief  Disable Not acknowledge received interrupt.
01368   * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK
01369   * @param  I2Cx I2C Instance.
01370   * @retval None
01371   */
01372 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
01373 {
01374   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
01375 }
01376
01377 /**
01378   * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
01379   * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK
01380   * @param  I2Cx I2C Instance.
01381   * @retval State of bit (1 or 0).
01382   */
01383 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
01384 {
01385   return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
01386 }
01387
01388 /**
01389   * @brief  Enable STOP detection interrupt.
01390   * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP
01391   * @param  I2Cx I2C Instance.
01392   * @retval None
01393   */
01394 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
01395 {
01396   SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
01397 }
01398
01399 /**
01400   * @brief  Disable STOP detection interrupt.
01401   * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP
01402   * @param  I2Cx I2C Instance.
01403   * @retval None
01404   */
01405 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
01406 {
01407   CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
01408 }
01409
01410 /**
01411   * @brief  Check if STOP detection interrupt is enabled or disabled.
01412   * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP
01413   * @param  I2Cx I2C Instance.
01414   * @retval State of bit (1 or 0).
01415   */
01416 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
01417 {
01418   return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
01419 }
01420
01421 /**
01422   * @brief  Enable Transfer Complete interrupt.
01423   * @note   Any of these events will generate interrupt :
01424   *         Transfer Complete (TC)
01425   *         Transfer Complete Reload (TCR)
01426   * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC
01427   * @param  I2Cx I2C Instance.
01428   * @retval None
01429   */
01430 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
01431 {
01432   SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
01433 }
01434
01435 /**
01436   * @brief  Disable Transfer Complete interrupt.
01437   * @note   Any of these events will generate interrupt :
01438   *         Transfer Complete (TC)
01439   *         Transfer Complete Reload (TCR)
01440   * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC
01441   * @param  I2Cx I2C Instance.
01442   * @retval None
01443   */
01444 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
01445 {
01446   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
01447 }
01448
01449 /**
01450   * @brief  Check if Transfer Complete interrupt is enabled or disabled.
01451   * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC
01452   * @param  I2Cx I2C Instance.
01453   * @retval State of bit (1 or 0).
01454   */
01455 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
01456 {
01457   return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
01458 }
01459
01460 /**
01461   * @brief  Enable Error interrupts.
01462   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01463   *         SMBus feature is supported by the I2Cx Instance.
01464   * @note   Any of these errors will generate interrupt :
01465   *         Arbitration Loss (ARLO)
01466   *         Bus Error detection (BERR)
01467   *         Overrun/Underrun (OVR)
01468   *         SMBus Timeout detection (TIMEOUT)
01469   *         SMBus PEC error detection (PECERR)
01470   *         SMBus Alert pin event detection (ALERT)
01471   * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR
01472   * @param  I2Cx I2C Instance.
01473   * @retval None
01474   */
01475 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
01476 {
01477   SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
01478 }
01479
01480 /**
01481   * @brief  Disable Error interrupts.
01482   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01483   *         SMBus feature is supported by the I2Cx Instance.
01484   * @note   Any of these errors will generate interrupt :
01485   *         Arbitration Loss (ARLO)
01486   *         Bus Error detection (BERR)
01487   *         Overrun/Underrun (OVR)
01488   *         SMBus Timeout detection (TIMEOUT)
01489   *         SMBus PEC error detection (PECERR)
01490   *         SMBus Alert pin event detection (ALERT)
01491   * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR
01492   * @param  I2Cx I2C Instance.
01493   * @retval None
01494   */
01495 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
01496 {
01497   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
01498 }
01499
01500 /**
01501   * @brief  Check if Error interrupts are enabled or disabled.
01502   * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR
01503   * @param  I2Cx I2C Instance.
01504   * @retval State of bit (1 or 0).
01505   */
01506 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
01507 {
01508   return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
01509 }
01510
01511 /**
01512   * @}
01513   */
01514
01515 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
01516   * @{
01517   */
01518
01519 /**
01520   * @brief  Indicate the status of Transmit data register empty flag.
01521   * @note   RESET: When next data is written in Transmit data register.
01522   *         SET: When Transmit data register is empty.
01523   * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE
01524   * @param  I2Cx I2C Instance.
01525   * @retval State of bit (1 or 0).
01526   */
01527 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
01528 {
01529   return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
01530 }
01531
01532 /**
01533   * @brief  Indicate the status of Transmit interrupt flag.
01534   * @note   RESET: When next data is written in Transmit data register.
01535   *         SET: When Transmit data register is empty.
01536   * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS
01537   * @param  I2Cx I2C Instance.
01538   * @retval State of bit (1 or 0).
01539   */
01540 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
01541 {
01542   return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
01543 }
01544
01545 /**
01546   * @brief  Indicate the status of Receive data register not empty flag.
01547   * @note   RESET: When Receive data register is read.
01548   *         SET: When the received data is copied in Receive data register.
01549   * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE
01550   * @param  I2Cx I2C Instance.
01551   * @retval State of bit (1 or 0).
01552   */
01553 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
01554 {
01555   return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
01556 }
01557
01558 /**
01559   * @brief  Indicate the status of Address matched flag (slave mode).
01560   * @note   RESET: Clear default value.
01561   *         SET: When the received slave address matched with one of the enabled slave address.
01562   * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR
01563   * @param  I2Cx I2C Instance.
01564   * @retval State of bit (1 or 0).
01565   */
01566 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
01567 {
01568   return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
01569 }
01570
01571 /**
01572   * @brief  Indicate the status of Not Acknowledge received flag.
01573   * @note   RESET: Clear default value.
01574   *         SET: When a NACK is received after a byte transmission.
01575   * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK
01576   * @param  I2Cx I2C Instance.
01577   * @retval State of bit (1 or 0).
01578   */
01579 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
01580 {
01581   return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
01582 }
01583
01584 /**
01585   * @brief  Indicate the status of Stop detection flag.
01586   * @note   RESET: Clear default value.
01587   *         SET: When a Stop condition is detected.
01588   * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP
01589   * @param  I2Cx I2C Instance.
01590   * @retval State of bit (1 or 0).
01591   */
01592 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
01593 {
01594   return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
01595 }
01596
01597 /**
01598   * @brief  Indicate the status of Transfer complete flag (master mode).
01599   * @note   RESET: Clear default value.
01600   *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
01601   * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC
01602   * @param  I2Cx I2C Instance.
01603   * @retval State of bit (1 or 0).
01604   */
01605 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
01606 {
01607   return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
01608 }
01609
01610 /**
01611   * @brief  Indicate the status of Transfer complete flag (master mode).
01612   * @note   RESET: Clear default value.
01613   *         SET: When RELOAD=1 and NBYTES date have been transferred.
01614   * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR
01615   * @param  I2Cx I2C Instance.
01616   * @retval State of bit (1 or 0).
01617   */
01618 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
01619 {
01620   return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
01621 }
01622
01623 /**
01624   * @brief  Indicate the status of Bus error flag.
01625   * @note   RESET: Clear default value.
01626   *         SET: When a misplaced Start or Stop condition is detected.
01627   * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR
01628   * @param  I2Cx I2C Instance.
01629   * @retval State of bit (1 or 0).
01630   */
01631 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
01632 {
01633   return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
01634 }
01635
01636 /**
01637   * @brief  Indicate the status of Arbitration lost flag.
01638   * @note   RESET: Clear default value.
01639   *         SET: When arbitration lost.
01640   * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO
01641   * @param  I2Cx I2C Instance.
01642   * @retval State of bit (1 or 0).
01643   */
01644 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
01645 {
01646   return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
01647 }
01648
01649 /**
01650   * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
01651   * @note   RESET: Clear default value.
01652   *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
01653   * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR
01654   * @param  I2Cx I2C Instance.
01655   * @retval State of bit (1 or 0).
01656   */
01657 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
01658 {
01659   return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
01660 }
01661
01662 /**
01663   * @brief  Indicate the status of SMBus PEC error flag in reception.
01664   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01665   *         SMBus feature is supported by the I2Cx Instance.
01666   * @note   RESET: Clear default value.
01667   *         SET: When the received PEC does not match with the PEC register content.
01668   * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
01669   * @param  I2Cx I2C Instance.
01670   * @retval State of bit (1 or 0).
01671   */
01672 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
01673 {
01674   return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
01675 }
01676
01677 /**
01678   * @brief  Indicate the status of SMBus Timeout detection flag.
01679   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01680   *         SMBus feature is supported by the I2Cx Instance.
01681   * @note   RESET: Clear default value.
01682   *         SET: When a timeout or extended clock timeout occurs.
01683   * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
01684   * @param  I2Cx I2C Instance.
01685   * @retval State of bit (1 or 0).
01686   */
01687 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
01688 {
01689   return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
01690 }
01691
01692 /**
01693   * @brief  Indicate the status of SMBus alert flag.
01694   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01695   *         SMBus feature is supported by the I2Cx Instance.
01696   * @note   RESET: Clear default value.
01697   *         SET: When SMBus host configuration, SMBus alert enabled and
01698   *              a falling edge event occurs on SMBA pin.
01699   * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT
01700   * @param  I2Cx I2C Instance.
01701   * @retval State of bit (1 or 0).
01702   */
01703 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
01704 {
01705   return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
01706 }
01707
01708 /**
01709   * @brief  Indicate the status of Bus Busy flag.
01710   * @note   RESET: Clear default value.
01711   *         SET: When a Start condition is detected.
01712   * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY
01713   * @param  I2Cx I2C Instance.
01714   * @retval State of bit (1 or 0).
01715   */
01716 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
01717 {
01718   return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
01719 }
01720
01721 /**
01722   * @brief  Clear Address Matched flag.
01723   * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR
01724   * @param  I2Cx I2C Instance.
01725   * @retval None
01726   */
01727 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
01728 {
01729   SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
01730 }
01731
01732 /**
01733   * @brief  Clear Not Acknowledge flag.
01734   * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK
01735   * @param  I2Cx I2C Instance.
01736   * @retval None
01737   */
01738 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
01739 {
01740   SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
01741 }
01742
01743 /**
01744   * @brief  Clear Stop detection flag.
01745   * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP
01746   * @param  I2Cx I2C Instance.
01747   * @retval None
01748   */
01749 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
01750 {
01751   SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
01752 }
01753
01754 /**
01755   * @brief  Clear Transmit data register empty flag (TXE).
01756   * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
01757   * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE
01758   * @param  I2Cx I2C Instance.
01759   * @retval None
01760   */
01761 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
01762 {
01763   WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
01764 }
01765
01766 /**
01767   * @brief  Clear Bus error flag.
01768   * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR
01769   * @param  I2Cx I2C Instance.
01770   * @retval None
01771   */
01772 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
01773 {
01774   SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
01775 }
01776
01777 /**
01778   * @brief  Clear Arbitration lost flag.
01779   * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO
01780   * @param  I2Cx I2C Instance.
01781   * @retval None
01782   */
01783 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
01784 {
01785   SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
01786 }
01787
01788 /**
01789   * @brief  Clear Overrun/Underrun flag.
01790   * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR
01791   * @param  I2Cx I2C Instance.
01792   * @retval None
01793   */
01794 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
01795 {
01796   SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
01797 }
01798
01799 /**
01800   * @brief  Clear SMBus PEC error flag.
01801   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01802   *         SMBus feature is supported by the I2Cx Instance.
01803   * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
01804   * @param  I2Cx I2C Instance.
01805   * @retval None
01806   */
01807 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
01808 {
01809   SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
01810 }
01811
01812 /**
01813   * @brief  Clear SMBus Timeout detection flag.
01814   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01815   *         SMBus feature is supported by the I2Cx Instance.
01816   * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
01817   * @param  I2Cx I2C Instance.
01818   * @retval None
01819   */
01820 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
01821 {
01822   SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
01823 }
01824
01825 /**
01826   * @brief  Clear SMBus Alert flag.
01827   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01828   *         SMBus feature is supported by the I2Cx Instance.
01829   * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
01830   * @param  I2Cx I2C Instance.
01831   * @retval None
01832   */
01833 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
01834 {
01835   SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
01836 }
01837
01838 /**
01839   * @}
01840   */
01841
01842 /** @defgroup I2C_LL_EF_Data_Management Data_Management
01843   * @{
01844   */
01845
01846 /**
01847   * @brief  Enable automatic STOP condition generation (master mode).
01848   * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
01849   *         This bit has no effect in slave mode or when RELOAD bit is set.
01850   * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode
01851   * @param  I2Cx I2C Instance.
01852   * @retval None
01853   */
01854 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
01855 {
01856   SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
01857 }
01858
01859 /**
01860   * @brief  Disable automatic STOP condition generation (master mode).
01861   * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
01862   * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode
01863   * @param  I2Cx I2C Instance.
01864   * @retval None
01865   */
01866 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
01867 {
01868   CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
01869 }
01870
01871 /**
01872   * @brief  Check if automatic STOP condition is enabled or disabled.
01873   * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode
01874   * @param  I2Cx I2C Instance.
01875   * @retval State of bit (1 or 0).
01876   */
01877 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
01878 {
01879   return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
01880 }
01881
01882 /**
01883   * @brief  Enable reload mode (master mode).
01884   * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
01885   * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode
01886   * @param  I2Cx I2C Instance.
01887   * @retval None
01888   */
01889 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
01890 {
01891   SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
01892 }
01893
01894 /**
01895   * @brief  Disable reload mode (master mode).
01896   * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
01897   * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode
01898   * @param  I2Cx I2C Instance.
01899   * @retval None
01900   */
01901 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
01902 {
01903   CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
01904 }
01905
01906 /**
01907   * @brief  Check if reload mode is enabled or disabled.
01908   * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode
01909   * @param  I2Cx I2C Instance.
01910   * @retval State of bit (1 or 0).
01911   */
01912 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
01913 {
01914   return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
01915 }
01916
01917 /**
01918   * @brief  Configure the number of bytes for transfer.
01919   * @note   Changing these bits when START bit is set is not allowed.
01920   * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize
01921   * @param  I2Cx I2C Instance.
01922   * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
01923   * @retval None
01924   */
01925 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
01926 {
01927   MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
01928 }
01929
01930 /**
01931   * @brief  Get the number of bytes configured for transfer.
01932   * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize
01933   * @param  I2Cx I2C Instance.
01934   * @retval Value between Min_Data=0x0 and Max_Data=0xFF
01935   */
01936 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
01937 {
01938   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
01939 }
01940
01941 /**
01942   * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
01943   * @note   Usage in Slave mode only.
01944   * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
01945   * @param  I2Cx I2C Instance.
01946   * @param  TypeAcknowledge This parameter can be one of the following values:
01947   *         @arg @ref LL_I2C_ACK
01948   *         @arg @ref LL_I2C_NACK
01949   * @retval None
01950   */
01951 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
01952 {
01953   MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
01954 }
01955
01956 /**
01957   * @brief  Generate a START or RESTART condition
01958   * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
01959   *         This action has no effect when RELOAD is set.
01960   * @rmtoll CR2          START           LL_I2C_GenerateStartCondition
01961   * @param  I2Cx I2C Instance.
01962   * @retval None
01963   */
01964 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
01965 {
01966   SET_BIT(I2Cx->CR2, I2C_CR2_START);
01967 }
01968
01969 /**
01970   * @brief  Generate a STOP condition after the current byte transfer (master mode).
01971   * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition
01972   * @param  I2Cx I2C Instance.
01973   * @retval None
01974   */
01975 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
01976 {
01977   SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
01978 }
01979
01980 /**
01981   * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
01982   * @note   The master sends the complete 10bit slave address read sequence :
01983   *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
01984   * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
01985   * @param  I2Cx I2C Instance.
01986   * @retval None
01987   */
01988 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
01989 {
01990   CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
01991 }
01992
01993 /**
01994   * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
01995   * @note   The master only sends the first 7 bits of 10bit address in Read direction.
01996   * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead
01997   * @param  I2Cx I2C Instance.
01998   * @retval None
01999   */
02000 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
02001 {
02002   SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
02003 }
02004
02005 /**
02006   * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
02007   * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead
02008   * @param  I2Cx I2C Instance.
02009   * @retval State of bit (1 or 0).
02010   */
02011 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
02012 {
02013   return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
02014 }
02015
02016 /**
02017   * @brief  Configure the transfer direction (master mode).
02018   * @note   Changing these bits when START bit is set is not allowed.
02019   * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest
02020   * @param  I2Cx I2C Instance.
02021   * @param  TransferRequest This parameter can be one of the following values:
02022   *         @arg @ref LL_I2C_REQUEST_WRITE
02023   *         @arg @ref LL_I2C_REQUEST_READ
02024   * @retval None
02025   */
02026 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
02027 {
02028   MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
02029 }
02030
02031 /**
02032   * @brief  Get the transfer direction requested (master mode).
02033   * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest
02034   * @param  I2Cx I2C Instance.
02035   * @retval Returned value can be one of the following values:
02036   *         @arg @ref LL_I2C_REQUEST_WRITE
02037   *         @arg @ref LL_I2C_REQUEST_READ
02038   */
02039 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
02040 {
02041   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
02042 }
02043
02044 /**
02045   * @brief  Configure the slave address for transfer (master mode).
02046   * @note   Changing these bits when START bit is set is not allowed.
02047   * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr
02048   * @param  I2Cx I2C Instance.
02049   * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
02050   * @retval None
02051   */
02052 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
02053 {
02054   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
02055 }
02056
02057 /**
02058   * @brief  Get the slave address programmed for transfer.
02059   * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr
02060   * @param  I2Cx I2C Instance.
02061   * @retval Value between Min_Data=0x0 and Max_Data=0x3F
02062   */
02063 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
02064 {
02065   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
02066 }
02067
02068 /**
02069   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
02070   * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n
02071   *         CR2          ADD10         LL_I2C_HandleTransfer\n
02072   *         CR2          RD_WRN        LL_I2C_HandleTransfer\n
02073   *         CR2          START         LL_I2C_HandleTransfer\n
02074   *         CR2          STOP          LL_I2C_HandleTransfer\n
02075   *         CR2          RELOAD        LL_I2C_HandleTransfer\n
02076   *         CR2          NBYTES        LL_I2C_HandleTransfer\n
02077   *         CR2          AUTOEND       LL_I2C_HandleTransfer\n
02078   *         CR2          HEAD10R       LL_I2C_HandleTransfer
02079   * @param  I2Cx I2C Instance.
02080   * @param  SlaveAddr Specifies the slave address to be programmed.
02081   * @param  SlaveAddrSize This parameter can be one of the following values:
02082   *         @arg @ref LL_I2C_ADDRSLAVE_7BIT
02083   *         @arg @ref LL_I2C_ADDRSLAVE_10BIT
02084   * @param  TransferSize Specifies the number of bytes to be programmed.
02085   *                       This parameter must be a value between Min_Data=0 and Max_Data=255.
02086   * @param  EndMode This parameter can be one of the following values:
02087   *         @arg @ref LL_I2C_MODE_RELOAD
02088   *         @arg @ref LL_I2C_MODE_AUTOEND
02089   *         @arg @ref LL_I2C_MODE_SOFTEND
02090   *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD
02091   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
02092   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
02093   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
02094   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
02095   * @param  Request This parameter can be one of the following values:
02096   *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
02097   *         @arg @ref LL_I2C_GENERATE_STOP
02098   *         @arg @ref LL_I2C_GENERATE_START_READ
02099   *         @arg @ref LL_I2C_GENERATE_START_WRITE
02100   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
02101   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
02102   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
02103   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
02104   * @retval None
02105   */
02106 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
02107                                            uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
02108 {
02109   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
02110              I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
02111              SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request);
02112 }
02113
02114 /**
02115   * @brief  Indicate the value of transfer direction (slave mode).
02116   * @note   RESET: Write transfer, Slave enters in receiver mode.
02117   *         SET: Read transfer, Slave enters in transmitter mode.
02118   * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection
02119   * @param  I2Cx I2C Instance.
02120   * @retval Returned value can be one of the following values:
02121   *         @arg @ref LL_I2C_DIRECTION_WRITE
02122   *         @arg @ref LL_I2C_DIRECTION_READ
02123   */
02124 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
02125 {
02126   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
02127 }
02128
02129 /**
02130   * @brief  Return the slave matched address.
02131   * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode
02132   * @param  I2Cx I2C Instance.
02133   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
02134   */
02135 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
02136 {
02137   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
02138 }
02139
02140 /**
02141   * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
02142   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02143   *         SMBus feature is supported by the I2Cx Instance.
02144   * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
02145   *         This bit has no effect when RELOAD bit is set.
02146   *         This bit has no effect in device mode when SBC bit is not set.
02147   * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
02148   * @param  I2Cx I2C Instance.
02149   * @retval None
02150   */
02151 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
02152 {
02153   SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
02154 }
02155
02156 /**
02157   * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.
02158   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02159   *         SMBus feature is supported by the I2Cx Instance.
02160   * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
02161   * @param  I2Cx I2C Instance.
02162   * @retval State of bit (1 or 0).
02163   */
02164 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
02165 {
02166   return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
02167 }
02168
02169 /**
02170   * @brief  Get the SMBus Packet Error byte calculated.
02171   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02172   *         SMBus feature is supported by the I2Cx Instance.
02173   * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
02174   * @param  I2Cx I2C Instance.
02175   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
02176 */
02177 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
02178 {
02179   return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
02180 }
02181
02182 /**
02183   * @brief  Read Receive Data register.
02184   * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8
02185   * @param  I2Cx I2C Instance.
02186   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
02187   */
02188 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
02189 {
02190   return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
02191 }
02192
02193 /**
02194   * @brief  Write in Transmit Data Register .
02195   * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8
02196   * @param  I2Cx I2C Instance.
02197   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
02198   * @retval None
02199   */
02200 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
02201 {
02202   WRITE_REG(I2Cx->TXDR, Data);
02203 }
02204
02205 /**
02206   * @}
02207   */
02208
02209 #if defined(USE_FULL_LL_DRIVER)
02210 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
02211   * @{
02212   */
02213
02214 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
02215 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
02216 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
02217
02218
02219 /**
02220   * @}
02221   */
02222 #endif /* USE_FULL_LL_DRIVER */
02223
02224 /**
02225   * @}
02226   */
02227
02228 /**
02229   * @}
02230   */
02231
02232 #endif /* I2C1 || I2C2 || I2C3 */
02233
02234 /**
02235   * @}
02236   */
02237
02238 #ifdef __cplusplus
02239 }
02240 #endif
02241
02242 #endif /* __STM32F3xx_LL_I2C_H */
02243
02244 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_iwdg.h Source File

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stm32f3xx_ll_iwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_iwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IWDG LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_IWDG_H
00038 #define __STM32F3xx_LL_IWDG_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined(IWDG)
00052
00053 /** @defgroup IWDG_LL IWDG
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059
00060 /* Private constants ---------------------------------------------------------*/
00061 /** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
00062   * @{
00063   */
00064
00065 #define LL_IWDG_KEY_RELOAD                 0x0000AAAAU               /*!< IWDG Reload Counter Enable   */
00066 #define LL_IWDG_KEY_ENABLE                 0x0000CCCCU               /*!< IWDG Peripheral Enable       */
00067 #define LL_IWDG_KEY_WR_ACCESS_ENABLE       0x00005555U               /*!< IWDG KR Write Access Enable  */
00068 #define LL_IWDG_KEY_WR_ACCESS_DISABLE      0x00000000U               /*!< IWDG KR Write Access Disable */
00069
00070 /**
00071   * @}
00072   */
00073
00074 /* Private macros ------------------------------------------------------------*/
00075
00076 /* Exported types ------------------------------------------------------------*/
00077 /* Exported constants --------------------------------------------------------*/
00078 /** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
00079   * @{
00080   */
00081
00082 /** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
00083   * @brief    Flags defines which can be used with LL_IWDG_ReadReg function
00084   * @{
00085   */
00086 #define LL_IWDG_SR_PVU                     IWDG_SR_PVU                           /*!< Watchdog prescaler value update */
00087 #define LL_IWDG_SR_RVU                     IWDG_SR_RVU                           /*!< Watchdog counter reload value update */
00088 #define LL_IWDG_SR_WVU                     IWDG_SR_WVU                           /*!< Watchdog counter window value update */
00089
00090 /**
00091   * @}
00092   */
00093
00094 /** @defgroup IWDG_LL_EC_PRESCALER  Prescaler Divider
00095   * @{
00096   */
00097 #define LL_IWDG_PRESCALER_4                0x00000000U                           /*!< Divider by 4   */
00098 #define LL_IWDG_PRESCALER_8                (IWDG_PR_PR_0)                        /*!< Divider by 8   */
00099 #define LL_IWDG_PRESCALER_16               (IWDG_PR_PR_1)                        /*!< Divider by 16  */
00100 #define LL_IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)         /*!< Divider by 32  */
00101 #define LL_IWDG_PRESCALER_64               (IWDG_PR_PR_2)                        /*!< Divider by 64  */
00102 #define LL_IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)         /*!< Divider by 128 */
00103 #define LL_IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)         /*!< Divider by 256 */
00104 /**
00105   * @}
00106   */
00107
00108 /**
00109   * @}
00110   */
00111
00112 /* Exported macro ------------------------------------------------------------*/
00113 /** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
00114   * @{
00115   */
00116
00117 /** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
00118   * @{
00119   */
00120
00121 /**
00122   * @brief  Write a value in IWDG register
00123   * @param  __INSTANCE__ IWDG Instance
00124   * @param  __REG__ Register to be written
00125   * @param  __VALUE__ Value to be written in the register
00126   * @retval None
00127   */
00128 #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00129
00130 /**
00131   * @brief  Read a value in IWDG register
00132   * @param  __INSTANCE__ IWDG Instance
00133   * @param  __REG__ Register to be read
00134   * @retval Register value
00135   */
00136 #define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00137 /**
00138   * @}
00139   */
00140
00141 /**
00142   * @}
00143   */
00144
00145
00146 /* Exported functions --------------------------------------------------------*/
00147 /** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
00148   * @{
00149   */
00150 /** @defgroup IWDG_LL_EF_Configuration Configuration
00151   * @{
00152   */
00153
00154 /**
00155   * @brief  Start the Independent Watchdog
00156   * @note   Except if the hardware watchdog option is selected
00157   * @rmtoll KR           KEY           LL_IWDG_Enable
00158   * @param  IWDGx IWDG Instance
00159   * @retval None
00160   */
00161 __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
00162 {
00163   WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
00164 }
00165
00166 /**
00167   * @brief  Reloads IWDG counter with value defined in the reload register
00168   * @rmtoll KR           KEY           LL_IWDG_ReloadCounter
00169   * @param  IWDGx IWDG Instance
00170   * @retval None
00171   */
00172 __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
00173 {
00174   WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
00175 }
00176
00177 /**
00178   * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
00179   * @rmtoll KR           KEY           LL_IWDG_EnableWriteAccess
00180   * @param  IWDGx IWDG Instance
00181   * @retval None
00182   */
00183 __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
00184 {
00185   WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
00186 }
00187
00188 /**
00189   * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
00190   * @rmtoll KR           KEY           LL_IWDG_DisableWriteAccess
00191   * @param  IWDGx IWDG Instance
00192   * @retval None
00193   */
00194 __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
00195 {
00196   WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
00197 }
00198
00199 /**
00200   * @brief  Select the prescaler of the IWDG
00201   * @rmtoll PR           PR            LL_IWDG_SetPrescaler
00202   * @param  IWDGx IWDG Instance
00203   * @param  Prescaler This parameter can be one of the following values:
00204   *         @arg @ref LL_IWDG_PRESCALER_4
00205   *         @arg @ref LL_IWDG_PRESCALER_8
00206   *         @arg @ref LL_IWDG_PRESCALER_16
00207   *         @arg @ref LL_IWDG_PRESCALER_32
00208   *         @arg @ref LL_IWDG_PRESCALER_64
00209   *         @arg @ref LL_IWDG_PRESCALER_128
00210   *         @arg @ref LL_IWDG_PRESCALER_256
00211   * @retval None
00212   */
00213 __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
00214 {
00215   WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
00216 }
00217
00218 /**
00219   * @brief  Get the selected prescaler of the IWDG
00220   * @rmtoll PR           PR            LL_IWDG_GetPrescaler
00221   * @param  IWDGx IWDG Instance
00222   * @retval Returned value can be one of the following values:
00223   *         @arg @ref LL_IWDG_PRESCALER_4
00224   *         @arg @ref LL_IWDG_PRESCALER_8
00225   *         @arg @ref LL_IWDG_PRESCALER_16
00226   *         @arg @ref LL_IWDG_PRESCALER_32
00227   *         @arg @ref LL_IWDG_PRESCALER_64
00228   *         @arg @ref LL_IWDG_PRESCALER_128
00229   *         @arg @ref LL_IWDG_PRESCALER_256
00230   */
00231 __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
00232 {
00233   return (uint32_t)(READ_REG(IWDGx->PR));
00234 }
00235
00236 /**
00237   * @brief  Specify the IWDG down-counter reload value
00238   * @rmtoll RLR          RL            LL_IWDG_SetReloadCounter
00239   * @param  IWDGx IWDG Instance
00240   * @param  Counter Value between Min_Data=0 and Max_Data=0x0FFF
00241   * @retval None
00242   */
00243 __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
00244 {
00245   WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
00246 }
00247
00248 /**
00249   * @brief  Get the specified IWDG down-counter reload value
00250   * @rmtoll RLR          RL            LL_IWDG_GetReloadCounter
00251   * @param  IWDGx IWDG Instance
00252   * @retval Value between Min_Data=0 and Max_Data=0x0FFF
00253   */
00254 __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
00255 {
00256   return (uint32_t)(READ_REG(IWDGx->RLR));
00257 }
00258
00259 /**
00260   * @brief  Specify high limit of the window value to be compared to the down-counter.
00261   * @rmtoll WINR         WIN           LL_IWDG_SetWindow
00262   * @param  IWDGx IWDG Instance
00263   * @param  Window Value between Min_Data=0 and Max_Data=0x0FFF
00264   * @retval None
00265   */
00266 __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
00267 {
00268   WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
00269 }
00270
00271 /**
00272   * @brief  Get the high limit of the window value specified.
00273   * @rmtoll WINR         WIN           LL_IWDG_GetWindow
00274   * @param  IWDGx IWDG Instance
00275   * @retval Value between Min_Data=0 and Max_Data=0x0FFF
00276   */
00277 __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
00278 {
00279   return (uint32_t)(READ_REG(IWDGx->WINR));
00280 }
00281
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
00287   * @{
00288   */
00289
00290 /**
00291   * @brief  Check if flag Prescaler Value Update is set or not
00292   * @rmtoll SR           PVU           LL_IWDG_IsActiveFlag_PVU
00293   * @param  IWDGx IWDG Instance
00294   * @retval State of bit (1 or 0).
00295   */
00296 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
00297 {
00298   return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
00299 }
00300
00301 /**
00302   * @brief  Check if flag Reload Value Update is set or not
00303   * @rmtoll SR           RVU           LL_IWDG_IsActiveFlag_RVU
00304   * @param  IWDGx IWDG Instance
00305   * @retval State of bit (1 or 0).
00306   */
00307 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
00308 {
00309   return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
00310 }
00311
00312 /**
00313   * @brief  Check if flag Window Value Update is set or not
00314   * @rmtoll SR           WVU           LL_IWDG_IsActiveFlag_WVU
00315   * @param  IWDGx IWDG Instance
00316   * @retval State of bit (1 or 0).
00317   */
00318 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
00319 {
00320   return (READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU));
00321 }
00322
00323 /**
00324   * @brief  Check if all flags Prescaler, Reload & Window Value Update are reset or not
00325   * @rmtoll SR           PVU           LL_IWDG_IsReady\n
00326   *         SR           WVU           LL_IWDG_IsReady\n
00327   *         SR           RVU           LL_IWDG_IsReady
00328   * @param  IWDGx IWDG Instance
00329   * @retval State of bits (1 or 0).
00330   */
00331 __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
00332 {
00333   return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U);
00334 }
00335
00336 /**
00337   * @}
00338   */
00339
00340
00341 /**
00342   * @}
00343   */
00344
00345 /**
00346   * @}
00347   */
00348
00349 #endif /* IWDG) */
00350
00351 /**
00352   * @}
00353   */
00354
00355 #ifdef __cplusplus
00356 }
00357 #endif
00358
00359 #endif /* __STM32F3xx_LL_IWDG_H */
00360
00361 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_opamp.c Source File

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stm32f3xx_ll_opamp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_opamp.c
00004   * @author  MCD Application Team
00005   * @brief   OPAMP LL module driver
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 #if defined(USE_FULL_LL_DRIVER)
00036
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f3xx_ll_opamp.h"
00039
00040 #ifdef  USE_FULL_ASSERT
00041   #include "stm32_assert.h"
00042 #else
00043   #define assert_param(expr) ((void)0U)
00044 #endif
00045
00046 /** @addtogroup STM32F3xx_LL_Driver
00047   * @{
00048   */
00049
00050 #if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4)
00051
00052 /** @addtogroup OPAMP_LL OPAMP
00053   * @{
00054   */
00055
00056 /* Private types -------------------------------------------------------------*/
00057 /* Private variables ---------------------------------------------------------*/
00058 /* Private constants ---------------------------------------------------------*/
00059 /* Private macros ------------------------------------------------------------*/
00060
00061 /** @addtogroup OPAMP_LL_Private_Macros
00062   * @{
00063   */
00064
00065 /* Check of parameters for configuration of OPAMP hierarchical scope:         */
00066 /* OPAMP instance.                                                            */
00067
00068 #define IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__)                       \
00069   (   ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_STANDALONE)                      \
00070    || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_FOLLOWER)                        \
00071    || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA)                             \
00072   )
00073
00074 /* Note: Comparator non-inverting inputs parameters are the same on all       */
00075 /*       OPAMP instances.                                                     */
00076 /*       However, comparator instance kept as macro parameter for             */
00077 /*       compatibility with other STM32 families.                             */
00078 #define IS_LL_OPAMP_INPUT_NONINVERTING(__OPAMPX__, __INPUT_NONINVERTING__)     \
00079   (   ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0)               \
00080    || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO1)               \
00081    || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO2)               \
00082    || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO3)               \
00083   )
00084
00085 /* Note: Comparator non-inverting inputs parameters are the same on all       */
00086 /*       OPAMP instances.                                                     */
00087 /*       However, comparator instance kept as macro parameter for             */
00088 /*       compatibility with other STM32 families.                             */
00089 #define IS_LL_OPAMP_INPUT_INVERTING(__OPAMPX__, __INPUT_INVERTING__)           \
00090   (   ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO0)                     \
00091    || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO1)                     \
00092    || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_CONNECT_NO)              \
00093   )
00094
00095 /**
00096   * @}
00097   */
00098
00099
00100 /* Private function prototypes -----------------------------------------------*/
00101
00102 /* Exported functions --------------------------------------------------------*/
00103 /** @addtogroup OPAMP_LL_Exported_Functions
00104   * @{
00105   */
00106
00107 /** @addtogroup OPAMP_LL_EF_Init
00108   * @{
00109   */
00110
00111 /**
00112   * @brief  De-initialize registers of the selected OPAMP instance
00113   *         to their default reset values.
00114   * @note   If comparator is locked, de-initialization by software is
00115   *         not possible.
00116   *         The only way to unlock the comparator is a device hardware reset.
00117   * @param  OPAMPx OPAMP instance
00118   * @retval An ErrorStatus enumeration value:
00119   *          - SUCCESS: OPAMP registers are de-initialized
00120   *          - ERROR: OPAMP registers are not de-initialized
00121   */
00122 ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef* OPAMPx)
00123 {
00124   ErrorStatus status = SUCCESS;
00125
00126   /* Check the parameters */
00127   assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
00128
00129   /* Note: Hardware constraint (refer to description of this function):       */
00130   /*       OPAMP instance must not be locked.                                 */
00131   if(LL_OPAMP_IsLocked(OPAMPx) == 0U)
00132   {
00133   LL_OPAMP_WriteReg(OPAMPx, CSR, 0x00000000U);
00134   }
00135   else
00136   {
00137     /* OPAMP instance is locked: de-initialization by software is              */
00138     /* not possible.                                                           */
00139     /* The only way to unlock the OPAMP is a device hardware reset.            */
00140     status = ERROR;
00141   }
00142
00143   return status;
00144 }
00145
00146 /**
00147   * @brief  Initialize some features of OPAMP instance.
00148   * @note   This function reset bit of calibration mode to ensure
00149   *         to be in functional mode, in order to have OPAMP parameters
00150   *         (inputs selection, ...) set with the corresponding OPAMP mode
00151   *         to be effective.
00152   * @param  OPAMPx OPAMP instance
00153   * @param  OPAMP_InitStruct Pointer to a @ref LL_OPAMP_InitTypeDef structure
00154   * @retval An ErrorStatus enumeration value:
00155   *          - SUCCESS: OPAMP registers are initialized
00156   *          - ERROR: OPAMP registers are not initialized
00157   */
00158 ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
00159 {
00160   ErrorStatus status = SUCCESS;
00161
00162   /* Check the parameters */
00163   assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
00164   assert_param(IS_LL_OPAMP_FUNCTIONAL_MODE(OPAMP_InitStruct->FunctionalMode));
00165   assert_param(IS_LL_OPAMP_INPUT_NONINVERTING(OPAMPx, OPAMP_InitStruct->InputNonInverting));
00166
00167   /* Note: OPAMP inverting input can be used with OPAMP in mode standalone    */
00168   /*       or PGA with external capacitors for filtering circuit.             */
00169   /*       Otherwise (OPAMP in mode follower), OPAMP inverting input is       */
00170   /*       not used (not connected to GPIO pin).                              */
00171   if(OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
00172   {
00173     assert_param(IS_LL_OPAMP_INPUT_INVERTING(OPAMPx, OPAMP_InitStruct->InputInverting));
00174   }
00175
00176   /* Note: Hardware constraint (refer to description of this function):       */
00177   /*       OPAMP instance must not be locked.                                 */
00178   if(LL_OPAMP_IsLocked(OPAMPx) == 0U)
00179   {
00180     /* Configuration of OPAMP instance :                                      */
00181     /*  - Functional mode                                                     */
00182     /*  - Input non-inverting                                                 */
00183     /*  - Input inverting                                                     */
00184     /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode.    */
00185     if(OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
00186     {
00187       MODIFY_REG(OPAMPx->CSR,
00188                    OPAMP_CSR_CALON
00189                  | OPAMP_CSR_VMSEL
00190                  | OPAMP_CSR_VPSEL
00191                 ,
00192                    OPAMP_InitStruct->FunctionalMode
00193                  | OPAMP_InitStruct->InputNonInverting
00194                  | OPAMP_InitStruct->InputInverting
00195                 );
00196     }
00197     else
00198     {
00199       MODIFY_REG(OPAMPx->CSR,
00200                    OPAMP_CSR_CALON
00201                  | OPAMP_CSR_VMSEL
00202                  | OPAMP_CSR_VPSEL
00203                 ,
00204                    LL_OPAMP_MODE_FOLLOWER
00205                  | OPAMP_InitStruct->InputNonInverting
00206                 );
00207     }
00208   }
00209   else
00210   {
00211     /* Initialization error: OPAMP instance is locked.                        */
00212     status = ERROR;
00213   }
00214
00215   return status;
00216 }
00217
00218 /**
00219   * @brief Set each @ref LL_OPAMP_InitTypeDef field to default value.
00220   * @param OPAMP_InitStruct pointer to a @ref LL_OPAMP_InitTypeDef structure
00221   *                         whose fields will be set to default values.
00222   * @retval None
00223   */
00224 void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
00225 {
00226   /* Set OPAMP_InitStruct fields to default values */
00227   OPAMP_InitStruct->FunctionalMode    = LL_OPAMP_MODE_FOLLOWER;
00228   OPAMP_InitStruct->InputNonInverting = LL_OPAMP_INPUT_NONINVERT_IO0;
00229   /* Note: Parameter discarded if OPAMP in functional mode follower,          */
00230   /*       set anyway to its default value.                                   */
00231   OPAMP_InitStruct->InputInverting    = LL_OPAMP_INPUT_INVERT_CONNECT_NO;
00232 }
00233
00234 /**
00235   * @}
00236   */
00237
00238 /**
00239   * @}
00240   */
00241
00242 /**
00243   * @}
00244   */
00245
00246 #endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 */
00247
00248 /**
00249   * @}
00250   */
00251
00252 #endif /* USE_FULL_LL_DRIVER */
00253
00254 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_opamp.h Source File

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  • Globals
  • Firmware
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  • STM32F3xx_HAL_Driver
  • Inc
stm32f3xx_ll_opamp.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_opamp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of OPAMP LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_OPAMP_H
00038 #define __STM32F3xx_LL_OPAMP_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4)
00052
00053 /** @defgroup OPAMP_LL OPAMP
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059
00060 /* Private constants ---------------------------------------------------------*/
00061 /** @defgroup OPAMP_LL_Private_Constants OPAMP Private Constants
00062   * @{
00063   */
00064
00065 /* Internal mask for OPAMP trimming of transistors differential pair NMOS     */
00066 /* or PMOS.                                                                   */
00067 /* To select into literal LL_OPAMP_TRIMMING_x the relevant bits for:          */
00068 /* - OPAMP trimming selection of transistors differential pair                */
00069 /* - OPAMP trimming values of transistors differential pair                   */
00070 #define OPAMP_TRIMMING_SELECT_MASK          (OPAMP_CSR_CALSEL)
00071 #define OPAMP_TRIMMING_VALUE_MASK           (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP)
00072
00073 /**
00074   * @}
00075   */
00076
00077
00078 /* Private macros ------------------------------------------------------------*/
00079 /** @defgroup OPAMP_LL_Private_Macros OPAMP Private Macros
00080   * @{
00081   */
00082
00083 /**
00084   * @brief  Driver macro reserved for internal use: set a pointer to
00085   *         a register from a register basis from which an offset
00086   *         is applied.
00087   * @param  __REG__ Register basis from which the offset is applied.
00088   * @param  __REG_OFFSET__ Offset to be applied (unit: number of registers).
00089   * @retval Register address
00090 */
00091 #define __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__)                        \
00092  ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2U))))
00093
00094
00095
00096
00097 /**
00098   * @}
00099   */
00100
00101
00102 /* Exported types ------------------------------------------------------------*/
00103 #if defined(USE_FULL_LL_DRIVER)
00104 /** @defgroup OPAMP_LL_ES_INIT OPAMP Exported Init structure
00105   * @{
00106   */
00107
00108 /**
00109   * @brief  Structure definition of some features of OPAMP instance.
00110   */
00111 typedef struct
00112 {
00113   uint32_t FunctionalMode;              /*!< Set OPAMP functional mode by setting internal connections: OPAMP operation in standalone, follower, ...
00114                                              This parameter can be a value of @ref OPAMP_LL_EC_FUNCTIONAL_MODE
00115                                              @note If OPAMP is configured in mode PGA, the gain can be configured using function @ref LL_OPAMP_SetPGAGain().
00116
00117                                              This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetFunctionalMode(). */
00118
00119   uint32_t InputNonInverting;           /*!< Set OPAMP input non-inverting connection.
00120                                              This parameter can be a value of @ref OPAMP_LL_EC_INPUT_NONINVERTING
00121
00122                                              This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputNonInverting(). */
00123
00124   uint32_t InputInverting;              /*!< Set OPAMP inverting input connection.
00125                                              This parameter can be a value of @ref OPAMP_LL_EC_INPUT_INVERTING
00126                                              @note OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin), this parameter is discarded.
00127
00128                                              This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputInverting(). */
00129
00130 } LL_OPAMP_InitTypeDef;
00131
00132 /**
00133   * @}
00134   */
00135 #endif /* USE_FULL_LL_DRIVER */
00136
00137 /* Exported constants --------------------------------------------------------*/
00138 /** @defgroup OPAMP_LL_Exported_Constants OPAMP Exported Constants
00139   * @{
00140   */
00141
00142 /** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional.
00143   * @{
00144   */
00145 #define LL_OPAMP_MODE_FUNCTIONAL        ((uint32_t)0x00000000U)                     /*!< OPAMP functional mode */
00146 #define LL_OPAMP_MODE_CALIBRATION       (OPAMP_CSR_CALON)                           /*!< OPAMP calibration mode */
00147 /**
00148   * @}
00149   */
00150
00151 /** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode
00152   * @{
00153   */
00154 #define LL_OPAMP_MODE_STANDALONE        ((uint32_t)0x00000000U)                     /*!< OPAMP functional mode, OPAMP operation in standalone */
00155 #define LL_OPAMP_MODE_FOLLOWER          (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)     /*!< OPAMP functional mode, OPAMP operation in follower */
00156 #define LL_OPAMP_MODE_PGA               (OPAMP_CSR_VMSEL_1)                         /*!< OPAMP functional mode, OPAMP operation in PGA */
00157 #define LL_OPAMP_MODE_PGA_EXT_FILT_IO0  (OPAMP_CSR_PGGAIN_3                      | OPAMP_CSR_VMSEL_1) /*!< OPAMP functional mode, OPAMP operation in PGA with external filtering on OPAMP input IO0. */
00158 #define LL_OPAMP_MODE_PGA_EXT_FILT_IO1  (OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL_1) /*!< OPAMP functional mode, OPAMP operation in PGA with external filtering on OPAMP input IO1. */
00159 /**
00160   * @}
00161   */
00162
00163 /** @defgroup OPAMP_LL_EC_MODE_PGA_GAIN OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
00164   * @{
00165   */
00166 #define LL_OPAMP_PGA_GAIN_2             ((uint32_t)0x00000000U)                    /*!< OPAMP PGA gain 2 */
00167 #define LL_OPAMP_PGA_GAIN_4             (OPAMP_CSR_PGGAIN_0)                       /*!< OPAMP PGA gain 4 */
00168 #define LL_OPAMP_PGA_GAIN_8             (OPAMP_CSR_PGGAIN_1)                       /*!< OPAMP PGA gain 8 */
00169 #define LL_OPAMP_PGA_GAIN_16            (OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0 ) /*!< OPAMP PGA gain 16 */
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting
00175   * @{
00176   */
00177 #define LL_OPAMP_INPUT_NONINVERT_IO0      (OPAMP_CSR_VPSEL)       /*!< OPAMP non inverting input connected to GPIO pin (pin PA1 for OPAMP1, pin PA7  for OPAMP2, pin PB0  for OPAMP3, pin PB13 for OPAMP4) */
00178 #define LL_OPAMP_INPUT_NONINVERT_IO1      ((uint32_t)0x00000000)  /*!< OPAMP non inverting input connected to GPIO pin (pin PA7 for OPAMP1, pin PD14 for OPAMP2, pin PB13 for OPAMP3, pin PD11 for OPAMP4) */
00179 #define LL_OPAMP_INPUT_NONINVERT_IO2      (OPAMP_CSR_VPSEL_1)     /*!< OPAMP non inverting input connected to GPIO pin (pin PA3 for OPAMP1, pin PB0  for OPAMP2, pin PA1  for OPAMP3, pin PB11 for OPAMP4) */
00180 #define LL_OPAMP_INPUT_NONINVERT_IO3      (OPAMP_CSR_VPSEL_0)     /*!< OPAMP non inverting input connected to GPIO pin (pin PA5 for OPAMP1, pin PB14 for OPAMP2, pin PA5  for OPAMP3, pin PA4  for OPAMP4) */
00181 #define LL_OPAMP_INPUT_NONINV_DAC1_CH1    (LL_OPAMP_INPUT_NONINVERT_IO3) /*!< OPAMP non inverting input connected to DAC1 channel1 output (specific to OPAMP instances: OPAMP4) */
00182 #define LL_OPAMP_INPUT_NONINV_DAC1_CH2    (LL_OPAMP_INPUT_NONINVERT_IO3) /*!< OPAMP non inverting input connected to DAC1 channel2 output (specific to OPAMP instances: OPAMP1, OPAMP3) */
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup OPAMP_LL_EC_INPUT_INVERTING OPAMP input inverting
00188   * @{
00189   */
00190 #define LL_OPAMP_INPUT_INVERT_IO0        ((uint32_t)0x00000000U) /*!< OPAMP inverting input connected to GPIO pin (pin PC5 for OPAMP1, pin PC5 for OPAMP2, pin PB10  for OPAMP3, pin PB10 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
00191 #define LL_OPAMP_INPUT_INVERT_IO1        (OPAMP_CSR_VMSEL_0)     /*!< OPAMP inverting input connected to GPIO pin (pin PA3 for OPAMP1, pin PA5 for OPAMP2, pin PB2   for OPAMP3, pin PD8  for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
00192 #define LL_OPAMP_INPUT_INVERT_CONNECT_NO (OPAMP_CSR_VMSEL_1)     /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA without external capacitors for filtering). Note: On this STM32 serie, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA. */
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING_SECONDARY OPAMP input non-inverting secondary
00198   * @{
00199   */
00200 #define LL_OPAMP_INPUT_NONINVERT_IO0_SEC   (LL_OPAMP_INPUT_NONINVERT_IO0   << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA1 for OPAMP1, pin PA7  for OPAMP2, pin PB0  for OPAMP3, pin PB13 for OPAMP4) */
00201 #define LL_OPAMP_INPUT_NONINVERT_IO1_SEC   (LL_OPAMP_INPUT_NONINVERT_IO1   << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA7 for OPAMP1, pin PD14 for OPAMP2, pin PB13 for OPAMP3, pin PD11 for OPAMP4) */
00202 #define LL_OPAMP_INPUT_NONINVERT_IO2_SEC   (LL_OPAMP_INPUT_NONINVERT_IO2   << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA3 for OPAMP1, pin PB0  for OPAMP2, pin PA1  for OPAMP3, pin PB11 for OPAMP4) */
00203 #define LL_OPAMP_INPUT_NONINVERT_IO3_SEC   (LL_OPAMP_INPUT_NONINVERT_IO3   << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA5 for OPAMP1, pin PD14 for OPAMP2, pin PA5  for OPAMP3, pin PA4  for OPAMP4) */
00204 #define LL_OPAMP_INPUT_NONINV_DAC1_CH1_SEC (LL_OPAMP_INPUT_NONINV_DAC1_CH1 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to DAC1 channel1 output (specific to OPAMP instances: OPAMP4) */
00205 #define LL_OPAMP_INPUT_NONINV_DAC1_CH2_SEC (LL_OPAMP_INPUT_NONINV_DAC1_CH2 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to DAC1 channel2 output (specific to OPAMP instances: OPAMP1, OPAMP3) */
00206
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup OPAMP_LL_EC_INPUT_INVERTING_SECONDARY OPAMP input inverting secondary
00212   * @{
00213   */
00214 #define LL_OPAMP_INPUT_INVERT_IO0_SEC    (LL_OPAMP_INPUT_INVERT_IO0 << (OPAMP_CSR_VMSSEL_Pos - OPAMP_CSR_VMSEL_Pos)) /*!< OPAMP inverting input secondary connected to GPIO pin (pin PC5 for OPAMP1, pin PC5 for OPAMP2, pin PB10  for OPAMP3, pin PB10 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
00215 #define LL_OPAMP_INPUT_INVERT_IO1_SEC    (LL_OPAMP_INPUT_INVERT_IO1 << (OPAMP_CSR_VMSSEL_Pos - OPAMP_CSR_VMSEL_Pos)) /*!< OPAMP inverting input secondary connected to GPIO pin (pin PA3 for OPAMP1, pin PA5 for OPAMP2, pin PB2   for OPAMP3, pin PD8  for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
00216 /**
00217   * @}
00218   */
00219
00220 /** @defgroup OPAMP_LL_EC_INPUT_MUX_MODE OPAMP inputs multiplexer mode
00221   * @{
00222   */
00223 #define LL_OPAMP_INPUT_MUX_DISABLE       ((uint32_t)0x00000000U)  /*!< OPAMP inputs multiplexer mode dosabled. */
00224 #define LL_OPAMP_INPUT_MUX_TIM1_CH6    (OPAMP_CSR_TCMEN)        /*!< OPAMP inputs multiplexer mode enabled, controlled by TIM1 CC6. */
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup OPAMP_LL_EC_VREF_OUTPUT OPAMP internal reference voltage path state to output
00230   * @{
00231   */
00232 #define LL_OPAMP_VREF_OUTPUT_DISABLE    ((uint32_t)0x00000000U)  /*!< OPAMP internal reference voltage path to output is disabled. */
00233 #define LL_OPAMP_VREF_OUTPUT_ENABLE     (OPAMP_CSR_TSTREF)       /*!< OPAMP internal reference voltage path to output is enabled. */
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode
00239   * @{
00240   */
00241 #define LL_OPAMP_TRIMMING_FACTORY       ((uint32_t)0x00000000U) /*!< OPAMP trimming factors set to factory values */
00242 #define LL_OPAMP_TRIMMING_USER          (OPAMP_CSR_USERTRIM)    /*!< OPAMP trimming factors set to user values */
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup OPAMP_LL_EC_TRIMMING_TRANSISTORS_DIFF_PAIR OPAMP trimming of transistors differential pair NMOS or PMOS
00248   * @{
00249   */
00250 #define LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA  (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 | OPAMP_CSR_CALSEL_0) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
00251 #define LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA  (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1                     ) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.5*Vdda). */
00252 #define LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA  (OPAMP_CSR_TRIMOFFSETP                      | OPAMP_CSR_CALSEL_0) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
00253 #define LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA (OPAMP_CSR_TRIMOFFSETP                                          ) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.33*Vdda). */
00254 #define LL_OPAMP_TRIMMING_NMOS          (LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
00255 #define LL_OPAMP_TRIMMING_PMOS          (LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup OPAMP_LL_EC_HW_DELAYS  Definitions of OPAMP hardware constraints delays
00261   * @note   Only OPAMP IP HW delays are defined in OPAMP LL driver driver,
00262   *         not timeout values.
00263   *         For details on delays values, refer to descriptions in source code
00264   *         above each literal definition.
00265   * @{
00266   */
00267
00268 /* Delay for OPAMP startup time (transition from state disable to enable).    */
00269 /* Note: OPAMP startup time depends on board application environment:         */
00270 /*       impedance connected to OPAMP output.                                 */
00271 /*       The delay below is specified under conditions:                       */
00272 /*        - OPAMP in functional mode follower                                 */
00273 /*        - load impedance of 4kOhm (min), 50pF (max)                         */
00274 /* Literal set to maximum value (refer to device datasheet,                   */
00275 /* parameter "tWAKEUP").                                                      */
00276 /* Unit: us                                                                   */
00277 #define LL_OPAMP_DELAY_STARTUP_US         ((uint32_t)  5U)  /*!< Delay for OPAMP startup time */
00278
00279 /**
00280   * @}
00281   */
00282
00283 /**
00284   * @}
00285   */
00286
00287 /* Exported macro ------------------------------------------------------------*/
00288 /** @defgroup OPAMP_LL_Exported_Macros OPAMP Exported Macros
00289   * @{
00290   */
00291 /** @defgroup OPAMP_LL_EM_WRITE_READ Common write and read registers macro
00292   * @{
00293   */
00294 /**
00295   * @brief  Write a value in OPAMP register
00296   * @param  __INSTANCE__ OPAMP Instance
00297   * @param  __REG__ Register to be written
00298   * @param  __VALUE__ Value to be written in the register
00299   * @retval None
00300   */
00301 #define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00302
00303 /**
00304   * @brief  Read a value in OPAMP register
00305   * @param  __INSTANCE__ OPAMP Instance
00306   * @param  __REG__ Register to be read
00307   * @retval Register value
00308   */
00309 #define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00310 /**
00311   * @}
00312   */
00313
00314 /**
00315   * @}
00316   */
00317
00318 /* Exported functions --------------------------------------------------------*/
00319 /** @defgroup OPAMP_LL_Exported_Functions OPAMP Exported Functions
00320   * @{
00321   */
00322
00323 /** @defgroup OPAMP_LL_EF_CONFIGURATION_OPAMP_INSTANCE Configuration of OPAMP hierarchical scope: OPAMP instance
00324   * @{
00325   */
00326
00327 /**
00328   * @brief  Set OPAMP mode calibration or functional.
00329   * @note   OPAMP mode corresponds to functional or calibration mode:
00330   *          - functional mode: OPAMP operation in standalone, follower, ...
00331   *            Set functional mode using function
00332   *            @ref LL_OPAMP_SetFunctionalMode().
00333   *          - calibration mode: offset calibration of the selected
00334   *            transistors differential pair NMOS or PMOS.
00335   * @rmtoll CSR      CALON          LL_OPAMP_SetMode
00336   * @param  OPAMPx OPAMP instance
00337   * @param  Mode This parameter can be one of the following values:
00338   *         @arg @ref LL_OPAMP_MODE_FUNCTIONAL
00339   *         @arg @ref LL_OPAMP_MODE_CALIBRATION
00340   * @retval None
00341   */
00342 __STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode)
00343 {
00344   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALON, Mode);
00345 }
00346
00347 /**
00348   * @brief  Get OPAMP mode calibration or functional.
00349   * @note   OPAMP mode corresponds to functional or calibration mode:
00350   *          - functional mode: OPAMP operation in standalone, follower, ...
00351   *            Set functional mode using function
00352   *            @ref LL_OPAMP_SetFunctionalMode().
00353   *          - calibration mode: offset calibration of the selected
00354   *            transistors differential pair NMOS or PMOS.
00355   * @rmtoll CSR      CALON          LL_OPAMP_GetMode
00356   * @param  OPAMPx OPAMP instance
00357   * @retval Returned value can be one of the following values:
00358   *         @arg @ref LL_OPAMP_MODE_FUNCTIONAL
00359   *         @arg @ref LL_OPAMP_MODE_CALIBRATION
00360   */
00361 __STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx)
00362 {
00363   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON));
00364 }
00365
00366 /**
00367   * @brief  Set OPAMP functional mode by setting internal connections.
00368   *         OPAMP operation in standalone, follower, ...
00369   * @note   This function reset bit of calibration mode to ensure
00370   *         to be in functional mode, in order to have OPAMP parameters
00371   *         (inputs selection, ...) set with the corresponding OPAMP mode
00372   *         to be effective.
00373   * @rmtoll CSR      VMSEL          LL_OPAMP_SetFunctionalMode
00374   * @param  OPAMPx OPAMP instance
00375   * @param  FunctionalMode This parameter can be one of the following values:
00376   *         @arg @ref LL_OPAMP_MODE_STANDALONE
00377   *         @arg @ref LL_OPAMP_MODE_FOLLOWER
00378   *         @arg @ref LL_OPAMP_MODE_PGA
00379   *         @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO0
00380   *         @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO1
00381   * @retval None
00382   */
00383 __STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
00384 {
00385   /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode */
00386   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL | OPAMP_CSR_CALON, FunctionalMode);
00387 }
00388
00389 /**
00390   * @brief  Get OPAMP functional mode from setting of internal connections.
00391   *         OPAMP operation in standalone, follower, ...
00392   * @rmtoll CSR      VMSEL          LL_OPAMP_GetFunctionalMode
00393   * @param  OPAMPx OPAMP instance
00394   * @retval Returned value can be one of the following values:
00395   *         @arg @ref LL_OPAMP_MODE_STANDALONE
00396   *         @arg @ref LL_OPAMP_MODE_FOLLOWER
00397   *         @arg @ref LL_OPAMP_MODE_PGA
00398   *         @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO0
00399   *         @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO1
00400   */
00401 __STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx)
00402 {
00403   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL));
00404 }
00405
00406 /**
00407   * @brief  Set OPAMP PGA gain.
00408   * @note   Preliminarily, OPAMP must be set in mode PGA
00409   *         using function @ref LL_OPAMP_SetFunctionalMode().
00410   * @rmtoll CSR      PGGAIN         LL_OPAMP_SetPGAGain
00411   * @param  OPAMPx OPAMP instance
00412   * @param  PGAGain This parameter can be one of the following values:
00413   *         @arg @ref LL_OPAMP_PGA_GAIN_2
00414   *         @arg @ref LL_OPAMP_PGA_GAIN_4
00415   *         @arg @ref LL_OPAMP_PGA_GAIN_8
00416   *         @arg @ref LL_OPAMP_PGA_GAIN_16
00417   * @retval None
00418   */
00419 __STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
00420 {
00421   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0, PGAGain);
00422 }
00423
00424 /**
00425   * @brief  Get OPAMP PGA gain.
00426   * @note   Preliminarily, OPAMP must be set in mode PGA
00427   *         using function @ref LL_OPAMP_SetFunctionalMode().
00428   * @rmtoll CSR      PGGAIN         LL_OPAMP_GetPGAGain
00429   * @param  OPAMPx OPAMP instance
00430   * @retval Returned value can be one of the following values:
00431   *         @arg @ref LL_OPAMP_PGA_GAIN_2
00432   *         @arg @ref LL_OPAMP_PGA_GAIN_4
00433   *         @arg @ref LL_OPAMP_PGA_GAIN_8
00434   *         @arg @ref LL_OPAMP_PGA_GAIN_16
00435   */
00436 __STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx)
00437 {
00438   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0));
00439 }
00440
00441 /**
00442   * @}
00443   */
00444
00445 /** @defgroup OPAMP_LL_EF_CONFIGURATION_INPUTS Configuration of OPAMP inputs
00446   * @{
00447   */
00448
00449 /**
00450   * @brief  Set OPAMP non-inverting input connection.
00451   * @rmtoll CSR      VPSEL          LL_OPAMP_SetInputNonInverting
00452   * @param  OPAMPx OPAMP instance
00453   * @param  InputNonInverting This parameter can be one of the following values:
00454   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
00455   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1
00456   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2
00457   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3
00458   *         @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 (1)
00459   *         @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2 (2)
00460   *
00461   *         (1) Parameter specific to OPAMP instances: OPAMP4.\n
00462   *         (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
00463   * @retval None
00464   */
00465 __STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
00466 {
00467   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VPSEL, InputNonInverting);
00468 }
00469
00470 /**
00471   * @brief  Get OPAMP non-inverting input connection.
00472   * @rmtoll CSR      VPSEL          LL_OPAMP_GetInputNonInverting
00473   * @param  OPAMPx OPAMP instance
00474   * @retval Returned value can be one of the following values:
00475   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
00476   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1
00477   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2
00478   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3
00479   *         @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 (1)
00480   *         @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2 (2)
00481   *
00482   *         (1) Parameter specific to OPAMP instances: OPAMP4.\n
00483   *         (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
00484   */
00485 __STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx)
00486 {
00487   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSEL));
00488 }
00489
00490 /**
00491   * @brief  Set OPAMP inverting input connection.
00492   * @note   OPAMP inverting input is used with OPAMP in mode standalone
00493   *         or PGA with external capacitors for filtering circuit.
00494   *         Otherwise (OPAMP in mode follower), OPAMP inverting input
00495   *         is not used (not connected to GPIO pin).
00496   * @rmtoll CSR      VMSEL          LL_OPAMP_SetInputInverting
00497   * @param  OPAMPx OPAMP instance
00498   * @param  InputInverting This parameter can be one of the following values:
00499   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0
00500   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1
00501   *         @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
00502   * @retval None
00503   */
00504 __STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
00505 {
00506   /* Manage cases of OPAMP inverting input not connected (0x10 and 0x11)      */
00507   /* to not modify OPAMP mode follower or PGA.                                */
00508   /* Bit OPAMP_CSR_VMSEL_1 is set by OPAMP mode (follower, PGA). */
00509   MODIFY_REG(OPAMPx->CSR, (~(InputInverting >> 1)) & OPAMP_CSR_VMSEL_0, InputInverting);
00510 }
00511
00512 /**
00513   * @brief  Get OPAMP inverting input connection.
00514   * @rmtoll CSR      VMSEL          LL_OPAMP_GetInputInverting
00515   * @param  OPAMPx OPAMP instance
00516   * @retval Returned value can be one of the following values:
00517   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0
00518   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1
00519   *         @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
00520   */
00521 __STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx)
00522 {
00523   register uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL);
00524
00525   /* Manage cases 0x10 and 0x11 to return the same value: OPAMP inverting     */
00526   /* input not connected.                                                     */
00527   return (input_inverting & ~((input_inverting >> 1) & OPAMP_CSR_VMSEL_0));
00528 }
00529
00530 /**
00531   * @brief  Set OPAMP non-inverting input secondary connection.
00532   * @rmtoll CSR      VPSSEL         LL_OPAMP_SetInputNonInvertingSecondary
00533   * @param  OPAMPx OPAMP instance
00534   * @param  InputNonInverting This parameter can be one of the following values:
00535   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0_SEC
00536   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1_SEC
00537   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2_SEC
00538   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3_SEC
00539   *         @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1_SEC (1)
00540   *         @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2_SEC (2)
00541   *
00542   *         (1) Parameter specific to OPAMP instances: OPAMP4.\n
00543   *         (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
00544   * @retval None
00545   */
00546 __STATIC_INLINE void LL_OPAMP_SetInputNonInvertingSecondary(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
00547 {
00548   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VPSSEL, InputNonInverting);
00549 }
00550
00551 /**
00552   * @brief  Get OPAMP non-inverting input secondary connection.
00553   * @rmtoll CSR      VPSSEL         LL_OPAMP_GetInputNonInvertingSecondary
00554   * @param  OPAMPx OPAMP instance
00555   * @retval Returned value can be one of the following values:
00556   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0_SEC
00557   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1_SEC
00558   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2_SEC
00559   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3_SEC
00560   *         @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1_SEC (1)
00561   *         @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2_SEC (2)
00562   *
00563   *         (1) Parameter specific to OPAMP instances: OPAMP4.\n
00564   *         (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
00565   */
00566 __STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInvertingSecondary(OPAMP_TypeDef *OPAMPx)
00567 {
00568   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSSEL));
00569 }
00570
00571 /**
00572   * @brief  Set OPAMP inverting input secondary connection.
00573   * @note   OPAMP inverting input is used with OPAMP in mode standalone
00574   *         or PGA with external capacitors for filtering circuit.
00575   *         Otherwise (OPAMP in mode follower), OPAMP inverting input
00576   *         is not used (not connected to GPIO pin).
00577   * @rmtoll CSR      VMSSEL         LL_OPAMP_SetInputInvertingSecondary
00578   * @param  OPAMPx OPAMP instance
00579   * @param  InputInverting This parameter can be one of the following values:
00580   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0_SEC
00581   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1_SEC
00582   * @retval None
00583   */
00584 __STATIC_INLINE void LL_OPAMP_SetInputInvertingSecondary (OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
00585 {
00586   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VMSSEL, InputInverting);
00587 }
00588
00589 /**
00590   * @brief  Get OPAMP inverting input secondary connection.
00591   * @rmtoll CSR      VMSSEL         LL_OPAMP_GetInputInvertingSecondary
00592   * @param  OPAMPx OPAMP instance
00593   * @retval Returned value can be one of the following values:
00594   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0_SEC
00595   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1_SEC
00596   */
00597 __STATIC_INLINE uint32_t LL_OPAMP_GetInputInvertingSecondary(OPAMP_TypeDef *OPAMPx)
00598 {
00599   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSSEL));
00600 }
00601
00602 /**
00603   * @brief  Set OPAMP inputs multiplexer mode.
00604   * @rmtoll CSR      TCMEN          LL_OPAMP_SetInputsMuxMode
00605   * @param  OPAMPx OPAMP instance
00606   * @param  InputsMuxMode This parameter can be one of the following values:
00607   *         @arg @ref LL_OPAMP_INPUT_MUX_DISABLE
00608   *         @arg @ref LL_OPAMP_INPUT_MUX_TIM1_CH6
00609   * @retval None
00610   */
00611 __STATIC_INLINE void LL_OPAMP_SetInputsMuxMode(OPAMP_TypeDef *OPAMPx, uint32_t InputsMuxMode)
00612 {
00613   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_TCMEN, InputsMuxMode);
00614 }
00615
00616 /**
00617   * @brief  Get OPAMP inputs multiplexer mode.
00618   * @rmtoll CSR      TCMEN          LL_OPAMP_GetInputsMuxMode
00619   * @param  OPAMPx OPAMP instance
00620   * @retval Returned value can be one of the following values:
00621   *         @arg @ref LL_OPAMP_INPUT_MUX_DISABLE
00622   *         @arg @ref LL_OPAMP_INPUT_MUX_TIM1_CH6
00623   */
00624 __STATIC_INLINE uint32_t LL_OPAMP_GetInputsMuxMode(OPAMP_TypeDef *OPAMPx)
00625 {
00626   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_TCMEN));
00627 }
00628
00629 /**
00630   * @}
00631   */
00632
00633 /** @defgroup OPAMP_LL_EF_OPAMP_TRIMMING Configuration and operation of OPAMP trimming
00634   * @{
00635   */
00636
00637 /**
00638   * @brief  Set OPAMP trimming mode.
00639   * @rmtoll CSR      USERTRIM       LL_OPAMP_SetTrimmingMode
00640   * @param  OPAMPx OPAMP instance
00641   * @param  TrimmingMode This parameter can be one of the following values:
00642   *         @arg @ref LL_OPAMP_TRIMMING_FACTORY
00643   *         @arg @ref LL_OPAMP_TRIMMING_USER
00644   * @retval None
00645   */
00646 __STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
00647 {
00648   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_USERTRIM, TrimmingMode);
00649 }
00650
00651 /**
00652   * @brief  Get OPAMP trimming mode.
00653   * @rmtoll CSR      USERTRIM       LL_OPAMP_GetTrimmingMode
00654   * @param  OPAMPx OPAMP instance
00655   * @retval Returned value can be one of the following values:
00656   *         @arg @ref LL_OPAMP_TRIMMING_FACTORY
00657   *         @arg @ref LL_OPAMP_TRIMMING_USER
00658   */
00659 __STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx)
00660 {
00661   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM));
00662 }
00663
00664 /**
00665   * @brief  Set OPAMP offset to calibrate the selected transistors
00666   *         differential pair NMOS or PMOS.
00667   * @note   Preliminarily, OPAMP must be set in mode calibration
00668   *         using function @ref LL_OPAMP_SetMode().
00669   * @rmtoll CSR      CALSEL         LL_OPAMP_SetCalibrationSelection
00670   * @param  OPAMPx OPAMP instance
00671   * @param  TransistorsDiffPair This parameter can be one of the following values:
00672   *         @arg @ref LL_OPAMP_TRIMMING_NMOS            (1)
00673   *         @arg @ref LL_OPAMP_TRIMMING_PMOS            (1)
00674   *         @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
00675   *         @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
00676   *
00677   *         (1) Default parameters to be used for calibration
00678   *             using two trimming steps (one with each transistors differential
00679   *             pair NMOS and PMOS)
00680   * @retval None
00681   */
00682 __STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
00683 {
00684   /* Parameter used with mask "OPAMP_TRIMMING_SELECT_MASK" because            */
00685   /* containing other bits reserved for other purpose.                        */
00686   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALSEL, (TransistorsDiffPair & OPAMP_TRIMMING_SELECT_MASK));
00687 }
00688
00689 /**
00690   * @brief  Get OPAMP offset to calibrate the selected transistors
00691   *         differential pair NMOS or PMOS.
00692   * @note   Preliminarily, OPAMP must be set in mode calibration
00693   *         using function @ref LL_OPAMP_SetMode().
00694   * @rmtoll CSR      CALSEL         LL_OPAMP_GetCalibrationSelection
00695   * @param  OPAMPx OPAMP instance
00696   * @retval Returned value can be one of the following values:
00697   *         @arg @ref LL_OPAMP_TRIMMING_NMOS            (1)
00698   *         @arg @ref LL_OPAMP_TRIMMING_PMOS            (1)
00699   *         @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
00700   *         @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
00701   *
00702   *         (1) Default parameters to be used for calibration
00703   *             using two trimming steps (one with each transistors differential
00704   *             pair NMOS and PMOS)
00705   */
00706 __STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)
00707 {
00708   register uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
00709
00710   return (CalibrationSelection |
00711           ((OPAMP_CSR_TRIMOFFSETN) << (POSITION_VAL(OPAMP_CSR_TRIMOFFSETP) * (CalibrationSelection && OPAMP_CSR_CALSEL))));
00712 }
00713
00714 /**
00715   * @brief  Set OPAMP calibration internal reference voltage to output.
00716   * @rmtoll CSR      TSTREF         LL_OPAMP_SetCalibrationVrefOutput
00717   * @param  OPAMPx OPAMP instance
00718   * @param  CalibrationVrefOutput This parameter can be one of the following values:
00719   *         @arg @ref LL_OPAMP_VREF_OUTPUT_DISABLE
00720   *         @arg @ref LL_OPAMP_VREF_OUTPUT_ENABLE
00721   * @retval None
00722   */
00723 __STATIC_INLINE void LL_OPAMP_SetCalibrationVrefOutput(OPAMP_TypeDef *OPAMPx, uint32_t CalibrationVrefOutput)
00724 {
00725   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_TSTREF, CalibrationVrefOutput);
00726 }
00727
00728 /**
00729   * @brief  Get OPAMP calibration internal reference voltage to output.
00730   * @rmtoll CSR      TSTREF         LL_OPAMP_GetCalibrationVrefOutput
00731   * @param  OPAMPx OPAMP instance
00732   * @retval Returned value can be one of the following values:
00733   *         @arg @ref LL_OPAMP_VREF_OUTPUT_DISABLE
00734   *         @arg @ref LL_OPAMP_VREF_OUTPUT_ENABLE
00735   */
00736 __STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationVrefOutput(OPAMP_TypeDef *OPAMPx)
00737 {
00738   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_TSTREF));
00739 }
00740
00741 /**
00742   * @brief  Get OPAMP calibration result of toggling output.
00743   * @note   This functions returns:
00744   *         0 if OPAMP calibration output is reset
00745   *         1 if OPAMP calibration output is set
00746   * @rmtoll CSR      OUTCAL         LL_OPAMP_IsCalibrationOutputSet
00747   * @param  OPAMPx OPAMP instance
00748   * @retval State of bit (1 or 0).
00749   */
00750 __STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx)
00751 {
00752   return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OUTCAL) == OPAMP_CSR_OUTCAL);
00753 }
00754
00755 /**
00756   * @brief  Set OPAMP trimming factor for the selected transistors
00757   *         differential pair NMOS or PMOS, corresponding to the selected
00758   *         power mode.
00759   * @rmtoll CSR      TRIMOFFSETN    LL_OPAMP_SetTrimmingValue\n
00760   *         CSR      TRIMOFFSETP    LL_OPAMP_SetTrimmingValue
00761   * @param  OPAMPx OPAMP instance
00762   * @param  TransistorsDiffPair This parameter can be one of the following values:
00763   *         @arg @ref LL_OPAMP_TRIMMING_NMOS
00764   *         @arg @ref LL_OPAMP_TRIMMING_PMOS
00765   * @param  TrimmingValue 0x00...0x1F
00766   * @retval None
00767   */
00768 __STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
00769 {
00770   MODIFY_REG(OPAMPx->CSR,
00771              (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK),
00772              TrimmingValue << (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK)));
00773 }
00774
00775 /**
00776   * @brief  Get OPAMP trimming factor for the selected transistors
00777   *         differential pair NMOS or PMOS, corresponding to the selected
00778   *         power mode.
00779   * @rmtoll CSR      TRIMOFFSETN    LL_OPAMP_GetTrimmingValue\n
00780   *         CSR      TRIMOFFSETP    LL_OPAMP_GetTrimmingValue
00781   * @param  OPAMPx OPAMP instance
00782   * @param  TransistorsDiffPair This parameter can be one of the following values:
00783   *         @arg @ref LL_OPAMP_TRIMMING_NMOS
00784   *         @arg @ref LL_OPAMP_TRIMMING_PMOS
00785   * @retval 0x0...0x1F
00786   */
00787 __STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t TransistorsDiffPair)
00788 {
00789   return (uint32_t)(READ_BIT(OPAMPx->CSR, (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))
00790                     >> (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))
00791                    );
00792 }
00793
00794 /**
00795   * @}
00796   */
00797
00798 /** @defgroup OPAMP_LL_EF_OPERATION Operation on OPAMP instance
00799   * @{
00800   */
00801 /**
00802   * @brief  Enable OPAMP instance.
00803   * @note   After enable from off state, OPAMP requires a delay
00804   *         to fullfill wake up time specification.
00805   *         Refer to device datasheet, parameter "tWAKEUP".
00806   * @rmtoll CSR      OPAMPXEN       LL_OPAMP_Enable
00807   * @param  OPAMPx OPAMP instance
00808   * @retval None
00809   */
00810 __STATIC_INLINE void LL_OPAMP_Enable(OPAMP_TypeDef *OPAMPx)
00811 {
00812   SET_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
00813 }
00814
00815 /**
00816   * @brief  Disable OPAMP instance.
00817   * @rmtoll CSR      OPAMPXEN       LL_OPAMP_Disable
00818   * @param  OPAMPx OPAMP instance
00819   * @retval None
00820   */
00821 __STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx)
00822 {
00823   CLEAR_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
00824 }
00825
00826 /**
00827   * @brief  Get OPAMP instance enable state
00828   *         (0: OPAMP is disabled, 1: OPAMP is enabled)
00829   * @rmtoll CSR      OPAMPXEN       LL_OPAMP_IsEnabled
00830   * @param  OPAMPx OPAMP instance
00831   * @retval State of bit (1 or 0).
00832   */
00833 __STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx)
00834 {
00835   return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN));
00836 }
00837
00838 /**
00839   * @brief  Lock OPAMP instance.
00840   * @note   Once locked, OPAMP configuration can be accessed in read-only.
00841   * @note   The only way to unlock the OPAMP is a device hardware reset.
00842   * @rmtoll CSR      LOCK           LL_OPAMP_Lock
00843   * @param  OPAMPx OPAMP instance
00844   * @retval None
00845   */
00846 __STATIC_INLINE void LL_OPAMP_Lock(OPAMP_TypeDef *OPAMPx)
00847 {
00848   SET_BIT(OPAMPx->CSR, OPAMP_CSR_LOCK);
00849 }
00850
00851 /**
00852   * @brief  Get OPAMP lock state
00853   *         (0: OPAMP is unlocked, 1: OPAMP is locked).
00854   * @note   Once locked, OPAMP configuration can be accessed in read-only.
00855   * @note   The only way to unlock the OPAMP is a device hardware reset.
00856   * @rmtoll CSR      LOCK           LL_OPAMP_IsLocked
00857   * @param  OPAMPx OPAMP instance
00858   * @retval State of bit (1 or 0).
00859   */
00860 __STATIC_INLINE uint32_t LL_OPAMP_IsLocked(OPAMP_TypeDef *OPAMPx)
00861 {
00862   return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_LOCK) == (OPAMP_CSR_LOCK));
00863 }
00864
00865 /**
00866   * @}
00867   */
00868
00869 #if defined(USE_FULL_LL_DRIVER)
00870 /** @defgroup OPAMP_LL_EF_Init Initialization and de-initialization functions
00871   * @{
00872   */
00873
00874 ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx);
00875 ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
00876 void        LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
00877
00878 /**
00879   * @}
00880   */
00881 #endif /* USE_FULL_LL_DRIVER */
00882
00883 /**
00884   * @}
00885   */
00886
00887 /**
00888   * @}
00889   */
00890
00891 #endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 */
00892
00893 /**
00894   * @}
00895   */
00896
00897 #ifdef __cplusplus
00898 }
00899 #endif
00900
00901 #endif /* __STM32F3xx_LL_OPAMP_H */
00902
00903 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_pwr.c Source File

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stm32f3xx_ll_pwr.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_pwr.c
00004   * @author  MCD Application Team
00005   * @brief   PWR LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 #if defined(USE_FULL_LL_DRIVER)
00036
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f3xx_ll_pwr.h"
00039 #include "stm32f3xx_ll_bus.h"
00040
00041 /** @addtogroup STM32F3xx_LL_Driver
00042   * @{
00043   */
00044
00045 #if defined(PWR)
00046
00047 /** @defgroup PWR_LL PWR
00048   * @{
00049   */
00050
00051 /* Private types -------------------------------------------------------------*/
00052 /* Private variables ---------------------------------------------------------*/
00053 /* Private constants ---------------------------------------------------------*/
00054 /* Private macros ------------------------------------------------------------*/
00055 /* Private function prototypes -----------------------------------------------*/
00056
00057 /* Exported functions --------------------------------------------------------*/
00058 /** @addtogroup PWR_LL_Exported_Functions
00059   * @{
00060   */
00061
00062 /** @addtogroup PWR_LL_EF_Init
00063   * @{
00064   */
00065
00066 /**
00067   * @brief  De-initialize the PWR registers to their default reset values.
00068   * @retval An ErrorStatus enumeration value:
00069   *          - SUCCESS: PWR registers are de-initialized
00070   *          - ERROR: not applicable
00071   */
00072 ErrorStatus LL_PWR_DeInit(void)
00073 {
00074   /* Force reset of PWR clock */
00075   LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
00076
00077   /* Release reset of PWR clock */
00078   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
00079
00080   return SUCCESS;
00081 }
00082
00083 /**
00084   * @}
00085   */
00086
00087 /**
00088   * @}
00089   */
00090
00091 /**
00092   * @}
00093   */
00094 #endif /* defined(PWR) */
00095 /**
00096   * @}
00097   */
00098
00099 #endif /* USE_FULL_LL_DRIVER */
00100
00101 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_pwr.h Source File

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stm32f3xx_ll_pwr.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_pwr.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PWR LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_PWR_H
00038 #define __STM32F3xx_LL_PWR_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined(PWR)
00052
00053 /** @defgroup PWR_LL PWR
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059 /* Private constants ---------------------------------------------------------*/
00060 /* Private macros ------------------------------------------------------------*/
00061 /* Exported types ------------------------------------------------------------*/
00062 /* Exported constants --------------------------------------------------------*/
00063 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
00064   * @{
00065   */
00066
00067 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
00068   * @brief    Flags defines which can be used with LL_PWR_WriteReg function
00069   * @{
00070   */
00071 #define LL_PWR_CR_CSBF                     PWR_CR_CSBF            /*!< Clear standby flag */
00072 #define LL_PWR_CR_CWUF                     PWR_CR_CWUF            /*!< Clear wakeup flag */
00073 /**
00074   * @}
00075   */
00076
00077 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
00078   * @brief    Flags defines which can be used with LL_PWR_ReadReg function
00079   * @{
00080   */
00081 #define LL_PWR_CSR_WUF                     PWR_CSR_WUF            /*!< Wakeup flag */
00082 #define LL_PWR_CSR_SBF                     PWR_CSR_SBF            /*!< Standby flag */
00083 #if defined(PWR_PVD_SUPPORT)
00084 #define LL_PWR_CSR_PVDO                    PWR_CSR_PVDO           /*!< Power voltage detector output flag */
00085 #endif /* PWR_PVD_SUPPORT */
00086 #if defined(PWR_CSR_VREFINTRDYF)
00087 #define LL_PWR_CSR_VREFINTRDYF             PWR_CSR_VREFINTRDYF    /*!< VREFINT ready flag */
00088 #endif /* PWR_CSR_VREFINTRDYF */
00089 #define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP1          /*!< Enable WKUP pin 1 */
00090 #define LL_PWR_CSR_EWUP2                   PWR_CSR_EWUP2          /*!< Enable WKUP pin 2 */
00091 #if defined(PWR_CSR_EWUP3)
00092 #define LL_PWR_CSR_EWUP3                   PWR_CSR_EWUP3          /*!< Enable WKUP pin 3 */
00093 #endif /* PWR_CSR_EWUP3 */
00094 /**
00095   * @}
00096   */
00097
00098
00099 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
00100   * @{
00101   */
00102 #define LL_PWR_MODE_STOP_MAINREGU             0x00000000U                    /*!< Enter Stop mode when the CPU enters deepsleep */
00103 #define LL_PWR_MODE_STOP_LPREGU               (PWR_CR_LPDS)                  /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
00104 #define LL_PWR_MODE_STANDBY                   (PWR_CR_PDDS)                  /*!< Enter Standby mode when the CPU enters deepsleep */
00105 /**
00106   * @}
00107   */
00108
00109 #if defined(PWR_CR_LPDS)
00110 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
00111  * @{
00112  */
00113 #define LL_PWR_REGU_DSMODE_MAIN        0x00000000U           /*!< Voltage Regulator in main mode during deepsleep mode */
00114 #define LL_PWR_REGU_DSMODE_LOW_POWER   (PWR_CR_LPDS)         /*!< Voltage Regulator in low-power mode during deepsleep mode */
00115 /**
00116   * @}
00117   */
00118 #endif /* PWR_CR_LPDS */
00119
00120 #if defined(PWR_PVD_SUPPORT)
00121 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
00122   * @{
00123   */
00124 #define LL_PWR_PVDLEVEL_0                  (PWR_CR_PLS_LEV0)      /*!< Voltage threshold detected by PVD 2.2 V */
00125 #define LL_PWR_PVDLEVEL_1                  (PWR_CR_PLS_LEV1)      /*!< Voltage threshold detected by PVD 2.3 V */
00126 #define LL_PWR_PVDLEVEL_2                  (PWR_CR_PLS_LEV2)      /*!< Voltage threshold detected by PVD 2.4 V */
00127 #define LL_PWR_PVDLEVEL_3                  (PWR_CR_PLS_LEV3)      /*!< Voltage threshold detected by PVD 2.5 V */
00128 #define LL_PWR_PVDLEVEL_4                  (PWR_CR_PLS_LEV4)      /*!< Voltage threshold detected by PVD 2.6 V */
00129 #define LL_PWR_PVDLEVEL_5                  (PWR_CR_PLS_LEV5)      /*!< Voltage threshold detected by PVD 2.7 V */
00130 #define LL_PWR_PVDLEVEL_6                  (PWR_CR_PLS_LEV6)      /*!< Voltage threshold detected by PVD 2.8 V */
00131 #define LL_PWR_PVDLEVEL_7                  (PWR_CR_PLS_LEV7)      /*!< Voltage threshold detected by PVD 2.9 V */
00132 /**
00133   * @}
00134   */
00135 #endif /* PWR_PVD_SUPPORT */
00136 /** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
00137   * @{
00138   */
00139 #define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP1)        /*!< WKUP pin 1 : PA0 */
00140 #define LL_PWR_WAKEUP_PIN2                 (PWR_CSR_EWUP2)        /*!< WKUP pin 2 : PC13 */
00141 #if defined(PWR_CSR_EWUP3)
00142 #define LL_PWR_WAKEUP_PIN3                 (PWR_CSR_EWUP3)        /*!< WKUP pin 3 : PE6 or PA2 according to device */
00143 #endif /* PWR_CSR_EWUP3 */
00144 /**
00145   * @}
00146   */
00147
00148 /** @defgroup PWR_LL_EC_SDADC_ANALOG_X SDADC Analogx
00149   * @{
00150   */
00151 #if defined(SDADC1)
00152 #define LL_PWR_SDADC_ANALOG1              (PWR_CR_ENSD1)   /*!< Enable SDADC1 */
00153 #endif /* SDADC1 */
00154 #if defined(SDADC2)
00155 #define LL_PWR_SDADC_ANALOG2              (PWR_CR_ENSD2)   /*!< Enable SDADC2 */
00156 #endif /* SDADC2 */
00157 #if defined(SDADC3)
00158 #define LL_PWR_SDADC_ANALOG3              (PWR_CR_ENSD3)   /*!< Enable SDADC3 */
00159 #endif /* SDADC3 */
00160 /**
00161   * @}
00162   */
00163 /**
00164   * @}
00165   */
00166
00167
00168 /* Exported macro ------------------------------------------------------------*/
00169 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
00170   * @{
00171   */
00172
00173 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
00174   * @{
00175   */
00176
00177 /**
00178   * @brief  Write a value in PWR register
00179   * @param  __REG__ Register to be written
00180   * @param  __VALUE__ Value to be written in the register
00181   * @retval None
00182   */
00183 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
00184
00185 /**
00186   * @brief  Read a value in PWR register
00187   * @param  __REG__ Register to be read
00188   * @retval Register value
00189   */
00190 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
00191 /**
00192   * @}
00193   */
00194
00195 /**
00196   * @}
00197   */
00198
00199 /* Exported functions --------------------------------------------------------*/
00200 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
00201   * @{
00202   */
00203
00204 /** @defgroup PWR_LL_EF_Configuration Configuration
00205   * @{
00206   */
00207 /**
00208   * @brief  Enables the SDADC peripheral functionality
00209   * @rmtoll CR   ENSD1       LL_PWR_EnableSDADC\n
00210   *         CR   ENSD2       LL_PWR_EnableSDADC\n
00211   *         CR   ENSD3       LL_PWR_EnableSDADC
00212   * @param  Analogx This parameter can be a combination of the following values:
00213   *         @arg @ref LL_PWR_SDADC_ANALOG1
00214   *         @arg @ref LL_PWR_SDADC_ANALOG2
00215   *         @arg @ref LL_PWR_SDADC_ANALOG3
00216   * @retval None
00217   */
00218 __STATIC_INLINE void LL_PWR_EnableSDADC(uint32_t Analogx)
00219 {
00220   SET_BIT(PWR->CR, Analogx);
00221 }
00222
00223 /**
00224   * @brief  Disables the SDADC peripheral functionality
00225   * @rmtoll CR   ENSD1       LL_PWR_EnableSDADC\n
00226   *         CR   ENSD2       LL_PWR_EnableSDADC\n
00227   *         CR   ENSD3       LL_PWR_EnableSDADC
00228   * @param  Analogx This parameter can be a combination of the following values:
00229   *         @arg @ref LL_PWR_SDADC_ANALOG1
00230   *         @arg @ref LL_PWR_SDADC_ANALOG2
00231   *         @arg @ref LL_PWR_SDADC_ANALOG3
00232   * @retval None
00233   */
00234 __STATIC_INLINE void LL_PWR_DisableSDADC(uint32_t Analogx)
00235 {
00236   CLEAR_BIT(PWR->CR, Analogx);
00237 }
00238
00239 /**
00240   * @brief  Check if SDADCx has been enabled or not
00241   * @rmtoll CR   ENSD1       LL_PWR_IsEnabledSDADC\n
00242   *         CR   ENSD2       LL_PWR_IsEnabledSDADC\n
00243   *         CR   ENSD3       LL_PWR_IsEnabledSDADC
00244   * @param  Analogx This parameter can be a combination of the following values:
00245   *         @arg @ref LL_PWR_SDADC_ANALOG1
00246   *         @arg @ref LL_PWR_SDADC_ANALOG2
00247   *         @arg @ref LL_PWR_SDADC_ANALOG3
00248   * @retval None
00249   */
00250 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSDADC(uint32_t Analogx)
00251 {
00252   return (READ_BIT(PWR->CR, Analogx) == (Analogx));
00253 }
00254
00255 /**
00256   * @brief  Enable access to the backup domain
00257   * @rmtoll CR    DBP       LL_PWR_EnableBkUpAccess
00258   * @retval None
00259   */
00260 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
00261 {
00262   SET_BIT(PWR->CR, PWR_CR_DBP);
00263 }
00264
00265 /**
00266   * @brief  Disable access to the backup domain
00267   * @rmtoll CR    DBP       LL_PWR_DisableBkUpAccess
00268   * @retval None
00269   */
00270 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
00271 {
00272   CLEAR_BIT(PWR->CR, PWR_CR_DBP);
00273 }
00274
00275 /**
00276   * @brief  Check if the backup domain is enabled
00277   * @rmtoll CR    DBP       LL_PWR_IsEnabledBkUpAccess
00278   * @retval State of bit (1 or 0).
00279   */
00280 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
00281 {
00282   return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
00283 }
00284
00285 #if defined(PWR_CR_LPDS)
00286 /**
00287   * @brief  Set voltage Regulator mode during deep sleep mode
00288   * @rmtoll CR    LPDS         LL_PWR_SetRegulModeDS
00289   * @param  RegulMode This parameter can be one of the following values:
00290   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
00291   *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
00292   * @retval None
00293   */
00294 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
00295 {
00296   MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
00297 }
00298
00299 /**
00300   * @brief  Get voltage Regulator mode during deep sleep mode
00301   * @rmtoll CR    LPDS         LL_PWR_GetRegulModeDS
00302   * @retval Returned value can be one of the following values:
00303   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
00304   *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
00305   */
00306 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
00307 {
00308   return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
00309 }
00310 #endif /* PWR_CR_LPDS */
00311
00312 /**
00313   * @brief  Set Power Down mode when CPU enters deepsleep
00314   * @rmtoll CR    PDDS         LL_PWR_SetPowerMode\n
00315   * @rmtoll CR    LPDS         LL_PWR_SetPowerMode
00316   * @param  PDMode This parameter can be one of the following values:
00317   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
00318   *         @arg @ref LL_PWR_MODE_STOP_LPREGU
00319   *         @arg @ref LL_PWR_MODE_STANDBY
00320   * @retval None
00321   */
00322 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
00323 {
00324   MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
00325 }
00326
00327 /**
00328   * @brief  Get Power Down mode when CPU enters deepsleep
00329   * @rmtoll CR    PDDS         LL_PWR_GetPowerMode\n
00330   * @rmtoll CR    LPDS         LL_PWR_GetPowerMode
00331   * @retval Returned value can be one of the following values:
00332   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
00333   *         @arg @ref LL_PWR_MODE_STOP_LPREGU
00334   *         @arg @ref LL_PWR_MODE_STANDBY
00335   */
00336 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
00337 {
00338   return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
00339 }
00340
00341 #if defined(PWR_PVD_SUPPORT)
00342 /**
00343   * @brief  Configure the voltage threshold detected by the Power Voltage Detector
00344   * @rmtoll CR    PLS       LL_PWR_SetPVDLevel
00345   * @param  PVDLevel This parameter can be one of the following values:
00346   *         @arg @ref LL_PWR_PVDLEVEL_0
00347   *         @arg @ref LL_PWR_PVDLEVEL_1
00348   *         @arg @ref LL_PWR_PVDLEVEL_2
00349   *         @arg @ref LL_PWR_PVDLEVEL_3
00350   *         @arg @ref LL_PWR_PVDLEVEL_4
00351   *         @arg @ref LL_PWR_PVDLEVEL_5
00352   *         @arg @ref LL_PWR_PVDLEVEL_6
00353   *         @arg @ref LL_PWR_PVDLEVEL_7
00354   * @retval None
00355   */
00356 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
00357 {
00358   MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
00359 }
00360
00361 /**
00362   * @brief  Get the voltage threshold detection
00363   * @rmtoll CR    PLS       LL_PWR_GetPVDLevel
00364   * @retval Returned value can be one of the following values:
00365   *         @arg @ref LL_PWR_PVDLEVEL_0
00366   *         @arg @ref LL_PWR_PVDLEVEL_1
00367   *         @arg @ref LL_PWR_PVDLEVEL_2
00368   *         @arg @ref LL_PWR_PVDLEVEL_3
00369   *         @arg @ref LL_PWR_PVDLEVEL_4
00370   *         @arg @ref LL_PWR_PVDLEVEL_5
00371   *         @arg @ref LL_PWR_PVDLEVEL_6
00372   *         @arg @ref LL_PWR_PVDLEVEL_7
00373   */
00374 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
00375 {
00376   return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
00377 }
00378
00379 /**
00380   * @brief  Enable Power Voltage Detector
00381   * @rmtoll CR    PVDE       LL_PWR_EnablePVD
00382   * @retval None
00383   */
00384 __STATIC_INLINE void LL_PWR_EnablePVD(void)
00385 {
00386   SET_BIT(PWR->CR, PWR_CR_PVDE);
00387 }
00388
00389 /**
00390   * @brief  Disable Power Voltage Detector
00391   * @rmtoll CR    PVDE       LL_PWR_DisablePVD
00392   * @retval None
00393   */
00394 __STATIC_INLINE void LL_PWR_DisablePVD(void)
00395 {
00396   CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
00397 }
00398
00399 /**
00400   * @brief  Check if Power Voltage Detector is enabled
00401   * @rmtoll CR    PVDE       LL_PWR_IsEnabledPVD
00402   * @retval State of bit (1 or 0).
00403   */
00404 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
00405 {
00406   return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
00407 }
00408 #endif /* PWR_PVD_SUPPORT */
00409
00410 /**
00411   * @brief  Enable the WakeUp PINx functionality
00412   * @rmtoll CSR   EWUP1       LL_PWR_EnableWakeUpPin\n
00413   * @rmtoll CSR   EWUP2       LL_PWR_EnableWakeUpPin\n
00414   * @rmtoll CSR   EWUP3       LL_PWR_EnableWakeUpPin
00415   * @param  WakeUpPin This parameter can be one of the following values:
00416   *         @arg @ref LL_PWR_WAKEUP_PIN1
00417   *         @arg @ref LL_PWR_WAKEUP_PIN2
00418   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
00419   *
00420   *         (*) not available on all devices
00421   * @retval None
00422   */
00423 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
00424 {
00425   SET_BIT(PWR->CSR, WakeUpPin);
00426 }
00427
00428 /**
00429   * @brief  Disable the WakeUp PINx functionality
00430   * @rmtoll CSR   EWUP1       LL_PWR_DisableWakeUpPin\n
00431   * @rmtoll CSR   EWUP2       LL_PWR_DisableWakeUpPin\n
00432   * @rmtoll CSR   EWUP3       LL_PWR_DisableWakeUpPin
00433   * @param  WakeUpPin This parameter can be one of the following values:
00434   *         @arg @ref LL_PWR_WAKEUP_PIN1
00435   *         @arg @ref LL_PWR_WAKEUP_PIN2
00436   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
00437   *
00438   *         (*) not available on all devices
00439   * @retval None
00440   */
00441 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
00442 {
00443   CLEAR_BIT(PWR->CSR, WakeUpPin);
00444 }
00445
00446 /**
00447   * @brief  Check if the WakeUp PINx functionality is enabled
00448   * @rmtoll CSR   EWUP1       LL_PWR_IsEnabledWakeUpPin\n
00449   * @rmtoll CSR   EWUP2       LL_PWR_IsEnabledWakeUpPin\n
00450   * @rmtoll CSR   EWUP3       LL_PWR_IsEnabledWakeUpPin
00451   * @param  WakeUpPin This parameter can be one of the following values:
00452   *         @arg @ref LL_PWR_WAKEUP_PIN1
00453   *         @arg @ref LL_PWR_WAKEUP_PIN2
00454   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
00455   *
00456   *         (*) not available on all devices
00457   * @retval State of bit (1 or 0).
00458   */
00459 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
00460 {
00461   return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
00462 }
00463
00464
00465 /**
00466   * @}
00467   */
00468
00469 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
00470   * @{
00471   */
00472
00473 /**
00474   * @brief  Get Wake-up Flag
00475   * @rmtoll CSR   WUF       LL_PWR_IsActiveFlag_WU
00476   * @retval State of bit (1 or 0).
00477   */
00478 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
00479 {
00480   return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
00481 }
00482
00483 /**
00484   * @brief  Get Standby Flag
00485   * @rmtoll CSR   SBF       LL_PWR_IsActiveFlag_SB
00486   * @retval State of bit (1 or 0).
00487   */
00488 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
00489 {
00490   return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
00491 }
00492
00493 #if defined(PWR_PVD_SUPPORT)
00494 /**
00495   * @brief  Indicate whether VDD voltage is below the selected PVD threshold
00496   * @rmtoll CSR   PVDO       LL_PWR_IsActiveFlag_PVDO
00497   * @retval State of bit (1 or 0).
00498   */
00499 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
00500 {
00501   return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
00502 }
00503 #endif /* PWR_PVD_SUPPORT */
00504
00505 #if defined(PWR_CSR_VREFINTRDYF)
00506 /**
00507   * @brief  Get Internal Reference VrefInt Flag
00508   * @rmtoll CSR   VREFINTRDYF       LL_PWR_IsActiveFlag_VREFINTRDY
00509   * @retval State of bit (1 or 0).
00510   */
00511 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
00512 {
00513   return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
00514 }
00515 #endif /* PWR_CSR_VREFINTRDYF */
00516 /**
00517   * @brief  Clear Standby Flag
00518   * @rmtoll CR   CSBF       LL_PWR_ClearFlag_SB
00519   * @retval None
00520   */
00521 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
00522 {
00523   SET_BIT(PWR->CR, PWR_CR_CSBF);
00524 }
00525
00526 /**
00527   * @brief  Clear Wake-up Flags
00528   * @rmtoll CR   CWUF       LL_PWR_ClearFlag_WU
00529   * @retval None
00530   */
00531 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
00532 {
00533   SET_BIT(PWR->CR, PWR_CR_CWUF);
00534 }
00535
00536 /**
00537   * @}
00538   */
00539
00540 #if defined(USE_FULL_LL_DRIVER)
00541 /** @defgroup PWR_LL_EF_Init De-initialization function
00542   * @{
00543   */
00544 ErrorStatus LL_PWR_DeInit(void);
00545 /**
00546   * @}
00547   */
00548 #endif /* USE_FULL_LL_DRIVER */
00549
00550 /**
00551   * @}
00552   */
00553
00554 /**
00555   * @}
00556   */
00557
00558 #endif /* defined(PWR) */
00559
00560 /**
00561   * @}
00562   */
00563
00564 #ifdef __cplusplus
00565 }
00566 #endif
00567
00568 #endif /* __STM32F3xx_LL_PWR_H */
00569
00570 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32F373xC HAL User Manual: stm32f3xx_ll_rcc.c Source File

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stm32f3xx_ll_rcc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_rcc.c
00004   * @author  MCD Application Team
00005   * @brief   RCC LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 #if defined(USE_FULL_LL_DRIVER)
00036
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f3xx_ll_rcc.h"
00039 #ifdef  USE_FULL_ASSERT
00040   #include "stm32_assert.h"
00041 #else
00042   #define assert_param(expr) ((void)0U)
00043 #endif /* USE_FULL_ASSERT */
00044 /** @addtogroup STM32F3xx_LL_Driver
00045   * @{
00046   */
00047
00048 #if defined(RCC)
00049
00050 /** @defgroup RCC_LL RCC
00051   * @{
00052   */
00053
00054 /* Private types -------------------------------------------------------------*/
00055 /* Private variables ---------------------------------------------------------*/
00056 /** @addtogroup RCC_LL_Private_Variables
00057   * @{
00058   */
00059 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
00060 const uint16_t aADCPrescTable[16]       = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U, 256U, 256U, 256U, 256U};
00061 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
00062 #if defined(RCC_CFGR_SDPRE)
00063 const uint8_t aSDADCPrescTable[16]       = {2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U};
00064 #endif /* RCC_CFGR_SDPRE */
00065 /**
00066   * @}
00067   */
00068
00069
00070 /* Private constants ---------------------------------------------------------*/
00071 /* Private macros ------------------------------------------------------------*/
00072 /** @addtogroup RCC_LL_Private_Macros
00073   * @{
00074   */
00075 #if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW)
00076 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
00077                                             || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
00078                                             || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
00079 #elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW)
00080 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
00081                                             || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
00082 #elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW)
00083 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
00084                                             || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
00085 #else
00086 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE))
00087 #endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
00088
00089 #if defined(UART4) && defined(UART5)
00090 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
00091                                              || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
00092 #elif defined(UART4)
00093 #define IS_LL_RCC_UART_INSTANCE(__VALUE__)     ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
00094 #elif defined(UART5)
00095 #define IS_LL_RCC_UART_INSTANCE(__VALUE__)     ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)
00096 #endif /* UART4 && UART5*/
00097
00098 #if defined(RCC_CFGR3_I2C2SW) && defined(RCC_CFGR3_I2C3SW)
00099 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
00100                                             || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
00101                                             || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
00102
00103 #elif defined(RCC_CFGR3_I2C2SW) && !defined(RCC_CFGR3_I2C3SW)
00104 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
00105                                             || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE))
00106
00107 #elif defined(RCC_CFGR3_I2C3SW) && !defined(RCC_CFGR3_I2C2SW)
00108 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
00109                                             || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
00110
00111 #else
00112 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)     ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
00113 #endif /* RCC_CFGR3_I2C2SW && RCC_CFGR3_I2C3SW */
00114
00115 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__)     ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
00116
00117 #if defined(USB)
00118 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
00119 #endif /* USB */
00120
00121 #if defined(RCC_CFGR_ADCPRE)
00122 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
00123 #else
00124 #if defined(RCC_CFGR2_ADC1PRES)
00125 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_ADC1_CLKSOURCE))
00126 #elif  defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34)
00127 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE) \
00128                                             || ((__VALUE__) == LL_RCC_ADC34_CLKSOURCE))
00129 #else /* RCC_CFGR2_ADCPRE12 */
00130 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE))
00131 #endif /* RCC_CFGR2_ADC1PRES */
00132 #endif /* RCC_CFGR_ADCPRE */
00133
00134 #if defined(RCC_CFGR_SDPRE)
00135 #define IS_LL_RCC_SDADC_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_SDADC_CLKSOURCE))
00136 #endif /* RCC_CFGR_SDPRE */
00137
00138 #if defined(CEC)
00139 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
00140 #endif /* CEC */
00141
00142 #if defined(RCC_CFGR3_TIMSW)
00143 #if defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
00144  && defined(RCC_CFGR3_TIM17SW) && defined(RCC_CFGR3_TIM20SW) && defined(RCC_CFGR3_TIM2SW) \
00145  && defined(RCC_CFGR3_TIM34SW)
00146
00147 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE)  \
00148                                             || ((__VALUE__) == LL_RCC_TIM2_CLKSOURCE)  \
00149                                             || ((__VALUE__) == LL_RCC_TIM8_CLKSOURCE)  \
00150                                             || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
00151                                             || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
00152                                             || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE) \
00153                                             || ((__VALUE__) == LL_RCC_TIM20_CLKSOURCE) \
00154                                             || ((__VALUE__) == LL_RCC_TIM34_CLKSOURCE))
00155
00156 #elif !defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
00157  && defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && defined(RCC_CFGR3_TIM2SW) \
00158  && defined(RCC_CFGR3_TIM34SW)
00159
00160 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE)  \
00161                                             || ((__VALUE__) == LL_RCC_TIM2_CLKSOURCE)  \
00162                                             || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
00163                                             || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
00164                                             || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE) \
00165                                             || ((__VALUE__) == LL_RCC_TIM34_CLKSOURCE))
00166
00167 #elif defined(RCC_CFGR3_TIM8SW) && !defined(RCC_CFGR3_TIM15SW) && !defined(RCC_CFGR3_TIM16SW) \
00168  && !defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
00169  && !defined(RCC_CFGR3_TIM34SW)
00170
00171 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE)  \
00172                                             || ((__VALUE__) == LL_RCC_TIM8_CLKSOURCE))
00173
00174 #elif !defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
00175  && defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
00176  && !defined(RCC_CFGR3_TIM34SW)
00177
00178 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE)  \
00179                                             || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
00180                                             || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
00181                                             || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE))
00182
00183 #elif !defined(RCC_CFGR3_TIM8SW) && !defined(RCC_CFGR3_TIM15SW) && !defined(RCC_CFGR3_TIM16SW) \
00184  && !defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
00185  && !defined(RCC_CFGR3_TIM34SW)
00186
00187 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE))
00188
00189 #else
00190 #error "Miss macro"
00191 #endif /* RCC_CFGR3_TIMxSW */
00192 #endif /* RCC_CFGR3_TIMSW */
00193
00194 #if defined(HRTIM1)
00195 #define IS_LL_RCC_HRTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_HRTIM1_CLKSOURCE))
00196 #endif /* HRTIM1 */
00197
00198 /**
00199   * @}
00200   */
00201
00202 /* Private function prototypes -----------------------------------------------*/
00203 /** @defgroup RCC_LL_Private_Functions RCC Private functions
00204   * @{
00205   */
00206 uint32_t RCC_GetSystemClockFreq(void);
00207 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
00208 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
00209 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
00210 uint32_t RCC_PLL_GetFreqDomain_SYS(void);
00211 /**
00212   * @}
00213   */
00214
00215
00216 /* Exported functions --------------------------------------------------------*/
00217 /** @addtogroup RCC_LL_Exported_Functions
00218   * @{
00219   */
00220
00221 /** @addtogroup RCC_LL_EF_Init
00222   * @{
00223   */
00224
00225 /**
00226   * @brief  Reset the RCC clock configuration to the default reset state.
00227   * @note   The default reset state of the clock configuration is given below:
00228   *         - HSI ON and used as system clock source
00229   *         - HSE and PLL OFF
00230   *         - AHB, APB1 and APB2 prescaler set to 1.
00231   *         - CSS, MCO OFF
00232   *         - All interrupts disabled
00233   * @note   This function doesn't modify the configuration of the
00234   *         - Peripheral clocks
00235   *         - LSI, LSE and RTC clocks
00236   * @retval An ErrorStatus enumeration value:
00237   *          - SUCCESS: RCC registers are de-initialized
00238   *          - ERROR: not applicable
00239   */
00240 ErrorStatus LL_RCC_DeInit(void)
00241 {
00242   uint32_t vl_mask = 0U;
00243
00244   /* Set HSION bit */
00245   LL_RCC_HSI_Enable();
00246
00247   /* Set HSITRIM bits to the reset value*/
00248   LL_RCC_HSI_SetCalibTrimming(0x10U);
00249
00250   /* Reset SW, HPRE, PPRE and MCOSEL bits */
00251   vl_mask = 0xFFFFFFFFU;
00252   CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL));
00253   LL_RCC_WriteReg(CFGR, vl_mask);
00254
00255   /* Reset HSEON, CSSON, PLLON bits */
00256   vl_mask = 0xFFFFFFFFU;
00257   CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON));
00258   LL_RCC_WriteReg(CR, vl_mask);
00259
00260   /* Reset HSEBYP bit */
00261   LL_RCC_HSE_DisableBypass();
00262
00263   /* Reset CFGR register */
00264   LL_RCC_WriteReg(CFGR, 0x00000000U);
00265
00266   /* Reset CFGR2 register */
00267   LL_RCC_WriteReg(CFGR2, 0x00000000U);
00268
00269   /* Reset CFGR3 register */
00270   LL_RCC_WriteReg(CFGR3, 0x00000000U);
00271
00272   /* Clear pending flags */
00273   vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_CSSC);
00274   SET_BIT(RCC->CIR, vl_mask);
00275
00276   /* Disable all interrupts */
00277   LL_RCC_WriteReg(CIR, 0x00000000U);
00278
00279   return SUCCESS;
00280 }
00281
00282 /**
00283   * @}
00284   */
00285
00286 /** @addtogroup RCC_LL_EF_Get_Freq
00287   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
00288   *         and different peripheral clocks available on the device.
00289   * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
00290   * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
00291   * @note   If SYSCLK source is PLL, function returns values based on
00292   *         HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
00293   * @note   (**) HSI_VALUE is a defined constant but the real value may vary
00294   *              depending on the variations in voltage and temperature.
00295   * @note   (***) HSE_VALUE is a defined constant, user has to ensure that
00296   *               HSE_VALUE is same as the real frequency of the crystal used.
00297   *               Otherwise, this function may have wrong result.
00298   * @note   The result of this function could be incorrect when using fractional
00299   *         value for HSE crystal.
00300   * @note   This function can be used by the user application to compute the
00301   *         baud-rate for the communication peripherals or configure other parameters.
00302   * @{
00303   */
00304
00305 /**
00306   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
00307   * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
00308   *         must be called to update structure fields. Otherwise, any
00309   *         configuration based on this function will be incorrect.
00310   * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
00311   * @retval None
00312   */
00313 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
00314 {
00315   /* Get SYSCLK frequency */
00316   RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
00317
00318   /* HCLK clock frequency */
00319   RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
00320
00321   /* PCLK1 clock frequency */
00322   RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
00323
00324   /* PCLK2 clock frequency */
00325   RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
00326 }
00327
00328 /**
00329   * @brief  Return USARTx clock frequency
00330   * @param  USARTxSource This parameter can be one of the following values:
00331   *         @arg @ref LL_RCC_USART1_CLKSOURCE
00332   *         @arg @ref LL_RCC_USART2_CLKSOURCE (*)
00333   *         @arg @ref LL_RCC_USART3_CLKSOURCE (*)
00334   *
00335   *         (*) value not defined in all devices.
00336   * @retval USART clock frequency (in Hz)
00337   *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
00338   */
00339 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
00340 {
00341   uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00342
00343   /* Check parameter */
00344   assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
00345 #if defined(RCC_CFGR3_USART1SW)
00346   if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
00347   {
00348     /* USART1CLK clock frequency */
00349     switch (LL_RCC_GetUSARTClockSource(USARTxSource))
00350     {
00351       case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
00352         usart_frequency = RCC_GetSystemClockFreq();
00353         break;
00354
00355       case LL_RCC_USART1_CLKSOURCE_HSI:    /* USART1 Clock is HSI Osc. */
00356         if (LL_RCC_HSI_IsReady())
00357         {
00358           usart_frequency = HSI_VALUE;
00359         }
00360         break;
00361
00362       case LL_RCC_USART1_CLKSOURCE_LSE:    /* USART1 Clock is LSE Osc. */
00363         if (LL_RCC_LSE_IsReady())
00364         {
00365           usart_frequency = LSE_VALUE;
00366         }
00367         break;
00368
00369 #if defined(RCC_CFGR3_USART1SW_PCLK1)
00370       case LL_RCC_USART1_CLKSOURCE_PCLK1:  /* USART1 Clock is PCLK1 */
00371       default:
00372         usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00373 #else
00374       case LL_RCC_USART1_CLKSOURCE_PCLK2:  /* USART1 Clock is PCLK2 */
00375       default:
00376         usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00377 #endif /* RCC_CFGR3_USART1SW_PCLK1 */
00378         break;
00379     }
00380   }
00381 #endif /* RCC_CFGR3_USART1SW  */
00382
00383 #if defined(RCC_CFGR3_USART2SW)
00384   if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
00385   {
00386     /* USART2CLK clock frequency */
00387     switch (LL_RCC_GetUSARTClockSource(USARTxSource))
00388     {
00389       case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
00390         usart_frequency = RCC_GetSystemClockFreq();
00391         break;
00392
00393       case LL_RCC_USART2_CLKSOURCE_HSI:    /* USART2 Clock is HSI Osc. */
00394         if (LL_RCC_HSI_IsReady())
00395         {
00396           usart_frequency = HSI_VALUE;
00397         }
00398         break;
00399
00400       case LL_RCC_USART2_CLKSOURCE_LSE:    /* USART2 Clock is LSE Osc. */
00401         if (LL_RCC_LSE_IsReady())
00402         {
00403           usart_frequency = LSE_VALUE;
00404         }
00405         break;
00406
00407       case LL_RCC_USART2_CLKSOURCE_PCLK1:  /* USART2 Clock is PCLK1 */
00408       default:
00409         usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00410         break;
00411     }
00412   }
00413 #endif /* RCC_CFGR3_USART2SW */
00414
00415 #if defined(RCC_CFGR3_USART3SW)
00416   if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
00417   {
00418     /* USART3CLK clock frequency */
00419     switch (LL_RCC_GetUSARTClockSource(USARTxSource))
00420     {
00421       case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
00422         usart_frequency = RCC_GetSystemClockFreq();
00423         break;
00424
00425       case LL_RCC_USART3_CLKSOURCE_HSI:    /* USART3 Clock is HSI Osc. */
00426         if (LL_RCC_HSI_IsReady())
00427         {
00428           usart_frequency = HSI_VALUE;
00429         }
00430         break;
00431
00432       case LL_RCC_USART3_CLKSOURCE_LSE:    /* USART3 Clock is LSE Osc. */
00433         if (LL_RCC_LSE_IsReady())
00434         {
00435           usart_frequency = LSE_VALUE;
00436         }
00437         break;
00438
00439       case LL_RCC_USART3_CLKSOURCE_PCLK1:  /* USART3 Clock is PCLK1 */
00440       default:
00441         usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00442         break;
00443     }
00444   }
00445
00446 #endif /* RCC_CFGR3_USART3SW */
00447   return usart_frequency;
00448 }
00449
00450 #if defined(UART4) || defined(UART5)
00451 /**
00452   * @brief  Return UARTx clock frequency
00453   * @param  UARTxSource This parameter can be one of the following values:
00454   *         @arg @ref LL_RCC_UART4_CLKSOURCE
00455   *         @arg @ref LL_RCC_UART5_CLKSOURCE
00456   * @retval UART clock frequency (in Hz)
00457   *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
00458   */
00459 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
00460 {
00461   uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00462
00463   /* Check parameter */
00464   assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
00465
00466 #if defined(UART4)
00467   if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
00468   {
00469     /* UART4CLK clock frequency */
00470     switch (LL_RCC_GetUARTClockSource(UARTxSource))
00471     {
00472       case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
00473         uart_frequency = RCC_GetSystemClockFreq();
00474         break;
00475
00476       case LL_RCC_UART4_CLKSOURCE_HSI:    /* UART4 Clock is HSI Osc. */
00477         if (LL_RCC_HSI_IsReady())
00478         {
00479           uart_frequency = HSI_VALUE;
00480         }
00481         break;
00482
00483       case LL_RCC_UART4_CLKSOURCE_LSE:    /* UART4 Clock is LSE Osc. */
00484         if (LL_RCC_LSE_IsReady())
00485         {
00486           uart_frequency = LSE_VALUE;
00487         }
00488         break;
00489
00490       case LL_RCC_UART4_CLKSOURCE_PCLK1:  /* UART4 Clock is PCLK1 */
00491       default:
00492         uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00493         break;
00494     }
00495   }
00496 #endif /* UART4 */
00497
00498 #if defined(UART5)
00499   if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
00500   {
00501     /* UART5CLK clock frequency */
00502     switch (LL_RCC_GetUARTClockSource(UARTxSource))
00503     {
00504       case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
00505         uart_frequency = RCC_GetSystemClockFreq();
00506         break;
00507
00508       case LL_RCC_UART5_CLKSOURCE_HSI:    /* UART5 Clock is HSI Osc. */
00509         if (LL_RCC_HSI_IsReady())
00510         {
00511           uart_frequency = HSI_VALUE;
00512         }
00513         break;
00514
00515       case LL_RCC_UART5_CLKSOURCE_LSE:    /* UART5 Clock is LSE Osc. */
00516         if (LL_RCC_LSE_IsReady())
00517         {
00518           uart_frequency = LSE_VALUE;
00519         }
00520         break;
00521
00522       case LL_RCC_UART5_CLKSOURCE_PCLK1:  /* UART5 Clock is PCLK1 */
00523       default:
00524         uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00525         break;
00526     }
00527   }
00528 #endif /* UART5 */
00529
00530   return uart_frequency;
00531 }
00532 #endif /* UART4 || UART5 */
00533
00534 /**
00535   * @brief  Return I2Cx clock frequency
00536   * @param  I2CxSource This parameter can be one of the following values:
00537   *         @arg @ref LL_RCC_I2C1_CLKSOURCE
00538   *         @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
00539   *         @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
00540   *
00541   *         (*) value not defined in all devices
00542   * @retval I2C clock frequency (in Hz)
00543   *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
00544   */
00545 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
00546 {
00547   uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00548
00549   /* Check parameter */
00550   assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
00551
00552   /* I2C1 CLK clock frequency */
00553   if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
00554   {
00555     switch (LL_RCC_GetI2CClockSource(I2CxSource))
00556     {
00557       case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
00558         i2c_frequency = RCC_GetSystemClockFreq();
00559         break;
00560
00561       case LL_RCC_I2C1_CLKSOURCE_HSI:    /* I2C1 Clock is HSI Osc. */
00562       default:
00563         if (LL_RCC_HSI_IsReady())
00564         {
00565           i2c_frequency = HSI_VALUE;
00566         }
00567         break;
00568     }
00569   }
00570
00571 #if defined(RCC_CFGR3_I2C2SW)
00572   /* I2C2 CLK clock frequency */
00573   if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
00574   {
00575     switch (LL_RCC_GetI2CClockSource(I2CxSource))
00576     {
00577       case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
00578         i2c_frequency = RCC_GetSystemClockFreq();
00579         break;
00580
00581       case LL_RCC_I2C2_CLKSOURCE_HSI:    /* I2C2 Clock is HSI Osc. */
00582       default:
00583         if (LL_RCC_HSI_IsReady())
00584         {
00585           i2c_frequency = HSI_VALUE;
00586         }
00587         break;
00588     }
00589   }
00590 #endif /*RCC_CFGR3_I2C2SW*/
00591
00592 #if defined(RCC_CFGR3_I2C3SW)
00593   /* I2C3 CLK clock frequency */
00594   if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
00595   {
00596     switch (LL_RCC_GetI2CClockSource(I2CxSource))
00597     {
00598       case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
00599         i2c_frequency = RCC_GetSystemClockFreq();
00600         break;
00601
00602       case LL_RCC_I2C3_CLKSOURCE_HSI:    /* I2C3 Clock is HSI Osc. */
00603       default:
00604         if (LL_RCC_HSI_IsReady())
00605         {
00606           i2c_frequency = HSI_VALUE;
00607         }
00608         break;
00609     }
00610   }
00611 #endif /*RCC_CFGR3_I2C3SW*/
00612
00613   return i2c_frequency;
00614 }
00615
00616 #if  defined(RCC_CFGR_I2SSRC)
00617 /**
00618   * @brief  Return I2Sx clock frequency
00619   * @param  I2SxSource This parameter can be one of the following values:
00620   *         @arg @ref LL_RCC_I2S_CLKSOURCE
00621   * @retval I2S clock frequency (in Hz)
00622   *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used */
00623 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
00624 {
00625   uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00626
00627   /* Check parameter */
00628   assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
00629
00630   /* I2S1CLK clock frequency */
00631   switch (LL_RCC_GetI2SClockSource(I2SxSource))
00632   {
00633     case LL_RCC_I2S_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */
00634       i2s_frequency = RCC_GetSystemClockFreq();
00635       break;
00636
00637     case LL_RCC_I2S_CLKSOURCE_PIN:    /*!< External clock selected as I2S clock source */
00638     default:
00639       i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00640       break;
00641   }
00642
00643   return i2s_frequency;
00644 }
00645 #endif /* RCC_CFGR_I2SSRC */
00646 #if defined(USB)
00647 /**
00648   * @brief  Return USBx clock frequency
00649   * @param  USBxSource This parameter can be one of the following values:
00650   *         @arg @ref LL_RCC_USB_CLKSOURCE
00651   * @retval USB clock frequency (in Hz)
00652   *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
00653   *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
00654   */
00655 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
00656 {
00657   uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00658
00659   /* Check parameter */
00660   assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
00661
00662   /* USBCLK clock frequency */
00663   switch (LL_RCC_GetUSBClockSource(USBxSource))
00664   {
00665     case LL_RCC_USB_CLKSOURCE_PLL:        /* PLL clock used as USB clock source */
00666       if (LL_RCC_PLL_IsReady())
00667       {
00668         usb_frequency = RCC_PLL_GetFreqDomain_SYS();
00669       }
00670       break;
00671
00672     case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5:        /* PLL clock used as USB clock source */
00673     default:
00674       if (LL_RCC_PLL_IsReady())
00675       {
00676         usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
00677       }
00678       break;
00679   }
00680
00681   return usb_frequency;
00682 }
00683 #endif /* USB */
00684
00685 #if defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
00686 /**
00687   * @brief  Return ADCx clock frequency
00688   * @param  ADCxSource This parameter can be one of the following values:
00689   *         @arg @ref LL_RCC_ADC_CLKSOURCE   (*)
00690   *         @arg @ref LL_RCC_ADC1_CLKSOURCE  (*)
00691   *         @arg @ref LL_RCC_ADC12_CLKSOURCE (*)
00692   *         @arg @ref LL_RCC_ADC34_CLKSOURCE (*)
00693   *
00694   *         (*) value not defined in all devices
00695   * @retval ADC clock frequency (in Hz)
00696   */
00697 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
00698 {
00699   uint32_t adc_prescaler = 0U;
00700   uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00701
00702   /* Check parameter */
00703   assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
00704
00705   /* Get ADC prescaler */
00706   adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
00707
00708 #if defined(RCC_CFGR_ADCPRE)
00709   /* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
00710   adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
00711                   / (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
00712 #else
00713   if ((adc_prescaler & 0x0000FFFFU) == ((uint32_t)0x00000000U))
00714   {
00715     /* ADC frequency = HCLK frequency */
00716     adc_frequency = RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq());
00717   }
00718   else
00719   {
00720     /* ADC frequency = PCLK2 frequency / ADC prescaler (from 1 to 256) */
00721     adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
00722                     / (aADCPrescTable[((adc_prescaler & 0x0000FFFFU) >> POSITION_VAL(ADCxSource)) & 0xFU]);
00723   }
00724 #endif /* RCC_CFGR_ADCPRE */
00725
00726   return adc_frequency;
00727 }
00728 #endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
00729
00730 #if defined(RCC_CFGR_SDPRE)
00731 /**
00732   * @brief  Return SDADCx clock frequency
00733   * @param  SDADCxSource This parameter can be one of the following values:
00734   *         @arg @ref LL_RCC_SDADC_CLKSOURCE
00735   * @retval SDADC clock frequency (in Hz)
00736   */
00737 uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource)
00738 {
00739   uint32_t sdadc_prescaler = 0U;
00740   uint32_t sdadc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00741
00742   /* Check parameter */
00743   assert_param(IS_LL_RCC_SDADC_CLKSOURCE(SDADCxSource));
00744
00745   /* Get SDADC prescaler */
00746   sdadc_prescaler = LL_RCC_GetSDADCClockSource(SDADCxSource);
00747
00748   /* SDADC frequency = SYSTEM frequency / SDADC prescaler (from 2 to 48) */
00749   sdadc_frequency = RCC_GetSystemClockFreq()
00750                     / (aSDADCPrescTable[(sdadc_prescaler >> POSITION_VAL(SDADCxSource)) & 0xFU]);
00751
00752   return sdadc_frequency;
00753 }
00754 #endif /*RCC_CFGR_SDPRE */
00755
00756 #if defined(CEC)
00757 /**
00758   * @brief  Return CECx clock frequency
00759   * @param  CECxSource This parameter can be one of the following values:
00760   *         @arg @ref LL_RCC_CEC_CLKSOURCE
00761   * @retval CEC clock frequency (in Hz)
00762   *        @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready
00763   */
00764 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
00765 {
00766   uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00767
00768   /* Check parameter */
00769   assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
00770
00771   /* CECCLK clock frequency */
00772   switch (LL_RCC_GetCECClockSource(CECxSource))
00773   {
00774     case LL_RCC_CEC_CLKSOURCE_HSI_DIV244:   /* HSI / 244 clock used as CEC clock source */
00775       if (LL_RCC_HSI_IsReady())
00776       {
00777         cec_frequency = HSI_VALUE / 244U;
00778       }
00779       break;
00780
00781     case LL_RCC_CEC_CLKSOURCE_LSE:          /* LSE clock used as CEC clock source */
00782     default:
00783       if (LL_RCC_LSE_IsReady())
00784       {
00785         cec_frequency = LSE_VALUE;
00786       }
00787       break;
00788   }
00789
00790   return cec_frequency;
00791 }
00792 #endif /* CEC */
00793
00794 #if defined(RCC_CFGR3_TIMSW)
00795 /**
00796   * @brief  Return TIMx clock frequency
00797   * @param  TIMxSource This parameter can be one of the following values:
00798   *         @arg @ref LL_RCC_TIM1_CLKSOURCE
00799   *         @arg @ref LL_RCC_TIM8_CLKSOURCE (*)
00800   *         @arg @ref LL_RCC_TIM15_CLKSOURCE (*)
00801   *         @arg @ref LL_RCC_TIM16_CLKSOURCE (*)
00802   *         @arg @ref LL_RCC_TIM17_CLKSOURCE (*)
00803   *         @arg @ref LL_RCC_TIM20_CLKSOURCE (*)
00804   *         @arg @ref LL_RCC_TIM2_CLKSOURCE (*)
00805   *         @arg @ref LL_RCC_TIM34_CLKSOURCE (*)
00806   *
00807   *         (*) value not defined in all devices
00808   * @retval TIM clock frequency (in Hz)
00809   */
00810 uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource)
00811 {
00812   uint32_t tim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00813
00814   /* Check parameter */
00815   assert_param(IS_LL_RCC_TIM_CLKSOURCE(TIMxSource));
00816
00817   if (TIMxSource == LL_RCC_TIM1_CLKSOURCE)
00818   {
00819     /* TIM1CLK clock frequency */
00820     if (LL_RCC_GetTIMClockSource(LL_RCC_TIM1_CLKSOURCE) == LL_RCC_TIM1_CLKSOURCE_PCLK2)
00821     {
00822       /* PCLK2 used as TIM1 clock source */
00823       tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00824     }
00825     else /* LL_RCC_TIM1_CLKSOURCE_PLL */
00826     {
00827       /* PLL clock used as TIM1 clock source */
00828       tim_frequency = RCC_PLL_GetFreqDomain_SYS();
00829     }
00830   }
00831
00832 #if defined(RCC_CFGR3_TIM8SW)
00833   if (TIMxSource == LL_RCC_TIM8_CLKSOURCE)
00834   {
00835     /* TIM8CLK clock frequency */
00836     if (LL_RCC_GetTIMClockSource(LL_RCC_TIM8_CLKSOURCE) == LL_RCC_TIM8_CLKSOURCE_PCLK2)
00837     {
00838       /* PCLK2 used as TIM8 clock source */
00839       tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00840     }
00841     else /* LL_RCC_TIM8_CLKSOURCE_PLL */
00842     {
00843       /* PLL clock used as TIM8 clock source */
00844       tim_frequency = RCC_PLL_GetFreqDomain_SYS();
00845     }
00846   }
00847 #endif /*RCC_CFGR3_TIM8SW*/
00848
00849 #if defined(RCC_CFGR3_TIM15SW)
00850   if (TIMxSource == LL_RCC_TIM15_CLKSOURCE)
00851   {
00852     /* TIM15CLK clock frequency */
00853     if (LL_RCC_GetTIMClockSource(LL_RCC_TIM15_CLKSOURCE) == LL_RCC_TIM15_CLKSOURCE_PCLK2)
00854     {
00855       /* PCLK2 used as TIM15 clock source */
00856       tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00857     }
00858     else /* LL_RCC_TIM15_CLKSOURCE_PLL */
00859     {
00860       /* PLL clock used as TIM15 clock source */
00861       tim_frequency = RCC_PLL_GetFreqDomain_SYS();
00862     }
00863   }
00864 #endif /*RCC_CFGR3_TIM15SW*/
00865
00866 #if defined(RCC_CFGR3_TIM16SW)
00867   if (TIMxSource == LL_RCC_TIM16_CLKSOURCE)
00868   {
00869     /* TIM16CLK clock frequency */
00870     if (LL_RCC_GetTIMClockSource(LL_RCC_TIM16_CLKSOURCE) == LL_RCC_TIM16_CLKSOURCE_PCLK2)
00871     {
00872       /* PCLK2 used as TIM16 clock source */
00873       tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00874     }
00875     else /* LL_RCC_TIM16_CLKSOURCE_PLL */
00876     {
00877       /* PLL clock used as TIM16 clock source */
00878       tim_frequency = RCC_PLL_GetFreqDomain_SYS();
00879     }
00880   }
00881 #endif /*RCC_CFGR3_TIM16SW*/
00882
00883 #if defined(RCC_CFGR3_TIM17SW)
00884   if (TIMxSource == LL_RCC_TIM17_CLKSOURCE)
00885   {
00886     /* TIM17CLK clock frequency */
00887     if (LL_RCC_GetTIMClockSource(LL_RCC_TIM17_CLKSOURCE) == LL_RCC_TIM17_CLKSOURCE_PCLK2)
00888     {
00889       /* PCLK2 used as TIM17 clock source */
00890       tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00891     }
00892     else /* LL_RCC_TIM17_CLKSOURCE_PLL */
00893     {
00894       /* PLL clock used as TIM17 clock source */
00895       tim_frequency = RCC_PLL_GetFreqDomain_SYS();
00896     }
00897   }
00898 #endif /*RCC_CFGR3_TIM17SW*/
00899
00900 #if defined(RCC_CFGR3_TIM20SW)
00901   if (TIMxSource == LL_RCC_TIM20_CLKSOURCE)
00902   {
00903     /* TIM20CLK clock frequency */
00904     if (LL_RCC_GetTIMClockSource(LL_RCC_TIM20_CLKSOURCE) == LL_RCC_TIM20_CLKSOURCE_PCLK2)
00905     {
00906       /* PCLK2 used as TIM20 clock source */
00907       tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00908     }
00909     else /* LL_RCC_TIM20_CLKSOURCE_PLL */
00910     {
00911       /* PLL clock used as TIM20 clock source */
00912       tim_frequency = RCC_PLL_GetFreqDomain_SYS();
00913     }
00914   }
00915 #endif /*RCC_CFGR3_TIM20SW*/
00916
00917 #if defined(RCC_CFGR3_TIM2SW)
00918   if (TIMxSource == LL_RCC_TIM2_CLKSOURCE)
00919   {
00920     /* TIM2CLK clock frequency */
00921     if (LL_RCC_GetTIMClockSource(LL_RCC_TIM2_CLKSOURCE) == LL_RCC_TIM2_CLKSOURCE_PCLK1)
00922     {
00923       /* PCLK1 used as TIM2 clock source */
00924       tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00925     }
00926     else /* LL_RCC_TIM2_CLKSOURCE_PLL */
00927     {
00928       /* PLL clock used as TIM2 clock source */
00929       tim_frequency = RCC_PLL_GetFreqDomain_SYS();
00930     }
00931   }
00932 #endif /*RCC_CFGR3_TIM2SW*/
00933
00934 #if defined(RCC_CFGR3_TIM34SW)
00935   if (TIMxSource == LL_RCC_TIM34_CLKSOURCE)
00936   {
00937     /* TIM3/4 CLK clock frequency */
00938     if (LL_RCC_GetTIMClockSource(LL_RCC_TIM34_CLKSOURCE) == LL_RCC_TIM34_CLKSOURCE_PCLK1)
00939     {
00940       /* PCLK1 used as TIM3/4 clock source */
00941       tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00942     }
00943     else /* LL_RCC_TIM34_CLKSOURCE_PLL */
00944     {
00945       /* PLL clock used as TIM3/4 clock source */
00946       tim_frequency = RCC_PLL_GetFreqDomain_SYS();
00947     }
00948   }
00949 #endif /*RCC_CFGR3_TIM34SW*/
00950
00951   return tim_frequency;
00952 }
00953 #endif /*RCC_CFGR3_TIMSW*/
00954
00955 #if defined(HRTIM1)
00956 /**
00957   * @brief  Return HRTIMx clock frequency
00958   * @param  HRTIMxSource This parameter can be one of the following values:
00959   *         @arg @ref LL_RCC_HRTIM1_CLKSOURCE
00960   * @retval HRTIM clock frequency (in Hz)
00961   */
00962 uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource)
00963 {
00964   uint32_t hrtim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00965
00966   /* Check parameter */
00967   assert_param(IS_LL_RCC_HRTIM_CLKSOURCE(HRTIMxSource));
00968
00969   /* HRTIM1CLK clock frequency */
00970   if (LL_RCC_GetTIMClockSource(LL_RCC_HRTIM1_CLKSOURCE) == LL_RCC_HRTIM1_CLKSOURCE_PCLK2)
00971   {
00972     /* PCLK2 used as HRTIM1 clock source */
00973     hrtim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00974   }
00975   else /* LL_RCC_HRTIM1_CLKSOURCE_PLL */
00976   {
00977     /* PLL clock used as HRTIM1 clock source */
00978     hrtim_frequency = RCC_PLL_GetFreqDomain_SYS();
00979   }
00980
00981   return hrtim_frequency;
00982 }
00983 #endif /* HRTIM1 */
00984
00985 /**
00986   * @}
00987   */
00988
00989 /**
00990   * @}
00991   */
00992
00993 /** @addtogroup RCC_LL_Private_Functions
00994   * @{
00995   */
00996
00997 /**
00998   * @brief  Return SYSTEM clock frequency
00999   * @retval SYSTEM clock frequency (in Hz)
01000   */
01001 uint32_t RCC_GetSystemClockFreq(void)
01002 {
01003   uint32_t frequency = 0U;
01004
01005   /* Get SYSCLK source -------------------------------------------------------*/
01006   switch (LL_RCC_GetSysClkSource())
01007   {
01008     case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */
01009       frequency = HSI_VALUE;
01010       break;
01011
01012     case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
01013       frequency = HSE_VALUE;
01014       break;
01015
01016     case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */
01017       frequency = RCC_PLL_GetFreqDomain_SYS();
01018       break;
01019
01020     default:
01021       frequency = HSI_VALUE;
01022       break;
01023   }
01024
01025   return frequency;
01026 }
01027
01028 /**
01029   * @brief  Return HCLK clock frequency
01030   * @param  SYSCLK_Frequency SYSCLK clock frequency
01031   * @retval HCLK clock frequency (in Hz)
01032   */
01033 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
01034 {
01035   /* HCLK clock frequency */
01036   return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
01037 }
01038
01039 /**
01040   * @brief  Return PCLK1 clock frequency
01041   * @param  HCLK_Frequency HCLK clock frequency
01042   * @retval PCLK1 clock frequency (in Hz)
01043   */
01044 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
01045 {
01046   /* PCLK1 clock frequency */
01047   return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
01048 }
01049
01050 /**
01051   * @brief  Return PCLK2 clock frequency
01052   * @param  HCLK_Frequency HCLK clock frequency
01053   * @retval PCLK2 clock frequency (in Hz)
01054   */
01055 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
01056 {
01057   /* PCLK2 clock frequency */
01058   return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
01059 }
01060
01061 /**
01062   * @brief  Return PLL clock frequency used for system domain
01063   * @retval PLL clock frequency (in Hz)
01064   */
01065 uint32_t RCC_PLL_GetFreqDomain_SYS(void)
01066 {
01067   uint32_t pllinputfreq = 0U, pllsource = 0U;
01068
01069   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
01070
01071   /* Get PLL source */
01072   pllsource = LL_RCC_PLL_GetMainSource();
01073
01074   switch (pllsource)
01075   {
01076 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
01077     case LL_RCC_PLLSOURCE_HSI:       /* HSI used as PLL clock source */
01078       pllinputfreq = HSI_VALUE;
01079 #else
01080     case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
01081       pllinputfreq = HSI_VALUE / 2U;
01082 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
01083       break;
01084
01085     case LL_RCC_PLLSOURCE_HSE:       /* HSE used as PLL clock source */
01086       pllinputfreq = HSE_VALUE;
01087       break;
01088
01089     default:
01090 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
01091       pllinputfreq = HSI_VALUE;
01092 #else
01093       pllinputfreq = HSI_VALUE / 2U;
01094 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
01095       break;
01096   }
01097 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
01098   return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv());
01099 #else
01100   return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator());
01101 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
01102 }
01103 /**
01104   * @}
01105   */
01106
01107 /**
01108   * @}
01109   */
01110
01111 #endif /* defined(RCC) */
01112
01113 /**
01114   * @}
01115   */
01116
01117 #endif /* USE_FULL_LL_DRIVER */
01118
01119 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_rcc.h Source File

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stm32f3xx_ll_rcc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_rcc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RCC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_RCC_H
00038 #define __STM32F3xx_LL_RCC_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined(RCC)
00052
00053 /** @defgroup RCC_LL RCC
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059 /* Private constants ---------------------------------------------------------*/
00060 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
00061   * @{
00062   */
00063 /* Defines used for the bit position in the register and perform offsets*/
00064 #define RCC_POSITION_HPRE       (uint32_t)POSITION_VAL(RCC_CFGR_HPRE)     /*!< field position in register RCC_CFGR */
00065 #define RCC_POSITION_PPRE1      (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1)    /*!< field position in register RCC_CFGR */
00066 #define RCC_POSITION_PPRE2      (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2)    /*!< field position in register RCC_CFGR */
00067 #define RCC_POSITION_HSICAL     (uint32_t)POSITION_VAL(RCC_CR_HSICAL)     /*!< field position in register RCC_CR */
00068 #define RCC_POSITION_HSITRIM    (uint32_t)POSITION_VAL(RCC_CR_HSITRIM)    /*!< field position in register RCC_CR */
00069 #define RCC_POSITION_PLLMUL     (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL)   /*!< field position in register RCC_CFGR */
00070 #define RCC_POSITION_USART1SW   (uint32_t)0U                              /*!< field position in register RCC_CFGR3 */
00071 #define RCC_POSITION_USART2SW   (uint32_t)16U                             /*!< field position in register RCC_CFGR3 */
00072 #define RCC_POSITION_USART3SW   (uint32_t)18U                             /*!< field position in register RCC_CFGR3 */
00073 #define RCC_POSITION_TIM1SW     (uint32_t)8U                              /*!< field position in register RCC_CFGR3 */
00074 #define RCC_POSITION_TIM8SW     (uint32_t)9U                              /*!< field position in register RCC_CFGR3 */
00075 #define RCC_POSITION_TIM15SW    (uint32_t)10U                             /*!< field position in register RCC_CFGR3 */
00076 #define RCC_POSITION_TIM16SW    (uint32_t)11U                             /*!< field position in register RCC_CFGR3 */
00077 #define RCC_POSITION_TIM17SW    (uint32_t)13U                             /*!< field position in register RCC_CFGR3 */
00078 #define RCC_POSITION_TIM20SW    (uint32_t)15U                             /*!< field position in register RCC_CFGR3 */
00079 #define RCC_POSITION_TIM2SW     (uint32_t)24U                             /*!< field position in register RCC_CFGR3 */
00080 #define RCC_POSITION_TIM34SW    (uint32_t)25U                             /*!< field position in register RCC_CFGR3 */
00081
00082 /**
00083   * @}
00084   */
00085
00086 /* Private macros ------------------------------------------------------------*/
00087 #if defined(USE_FULL_LL_DRIVER)
00088 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
00089   * @{
00090   */
00091 /**
00092   * @}
00093   */
00094 #endif /*USE_FULL_LL_DRIVER*/
00095 /* Exported types ------------------------------------------------------------*/
00096 #if defined(USE_FULL_LL_DRIVER)
00097 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
00098   * @{
00099   */
00100
00101 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
00102   * @{
00103   */
00104
00105 /**
00106   * @brief  RCC Clocks Frequency Structure
00107   */
00108 typedef struct
00109 {
00110   uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
00111   uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
00112   uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
00113   uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */
00114 } LL_RCC_ClocksTypeDef;
00115
00116 /**
00117   * @}
00118   */
00119
00120 /**
00121   * @}
00122   */
00123 #endif /* USE_FULL_LL_DRIVER */
00124
00125 /* Exported constants --------------------------------------------------------*/
00126 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
00127   * @{
00128   */
00129
00130 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
00131   * @brief    Defines used to adapt values of different oscillators
00132   * @note     These values could be modified in the user environment according to
00133   *           HW set-up.
00134   * @{
00135   */
00136 #if !defined  (HSE_VALUE)
00137 #define HSE_VALUE    8000000U  /*!< Value of the HSE oscillator in Hz */
00138 #endif /* HSE_VALUE */
00139
00140 #if !defined  (HSI_VALUE)
00141 #define HSI_VALUE    8000000U  /*!< Value of the HSI oscillator in Hz */
00142 #endif /* HSI_VALUE */
00143
00144 #if !defined  (LSE_VALUE)
00145 #define LSE_VALUE    32768U    /*!< Value of the LSE oscillator in Hz */
00146 #endif /* LSE_VALUE */
00147
00148 #if !defined  (LSI_VALUE)
00149 #define LSI_VALUE    32000U    /*!< Value of the LSI oscillator in Hz */
00150 #endif /* LSI_VALUE */
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
00156   * @brief    Flags defines which can be used with LL_RCC_WriteReg function
00157   * @{
00158   */
00159 #define LL_RCC_CIR_LSIRDYC                RCC_CIR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
00160 #define LL_RCC_CIR_LSERDYC                RCC_CIR_LSERDYC     /*!< LSE Ready Interrupt Clear */
00161 #define LL_RCC_CIR_HSIRDYC                RCC_CIR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
00162 #define LL_RCC_CIR_HSERDYC                RCC_CIR_HSERDYC     /*!< HSE Ready Interrupt Clear */
00163 #define LL_RCC_CIR_PLLRDYC                RCC_CIR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
00164 #define LL_RCC_CIR_CSSC                   RCC_CIR_CSSC        /*!< Clock Security System Interrupt Clear */
00165 /**
00166   * @}
00167   */
00168
00169 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
00170   * @brief    Flags defines which can be used with LL_RCC_ReadReg function
00171   * @{
00172   */
00173 #define LL_RCC_CIR_LSIRDYF                RCC_CIR_LSIRDYF     /*!< LSI Ready Interrupt flag */
00174 #define LL_RCC_CIR_LSERDYF                RCC_CIR_LSERDYF     /*!< LSE Ready Interrupt flag */
00175 #define LL_RCC_CIR_HSIRDYF                RCC_CIR_HSIRDYF     /*!< HSI Ready Interrupt flag */
00176 #define LL_RCC_CIR_HSERDYF                RCC_CIR_HSERDYF     /*!< HSE Ready Interrupt flag */
00177 #define LL_RCC_CFGR_MCOF                  RCC_CFGR_MCOF     /*!< MCO flag */
00178 #define LL_RCC_CIR_PLLRDYF                RCC_CIR_PLLRDYF     /*!< PLL Ready Interrupt flag */
00179 #define LL_RCC_CIR_CSSF                   RCC_CIR_CSSF       /*!< Clock Security System Interrupt flag */
00180 #define LL_RCC_CSR_OBLRSTF                RCC_CSR_OBLRSTF         /*!< OBL reset flag */
00181 #define LL_RCC_CSR_PINRSTF                RCC_CSR_PINRSTF         /*!< PIN reset flag */
00182 #define LL_RCC_CSR_PORRSTF                RCC_CSR_PORRSTF         /*!< POR/PDR reset flag */
00183 #define LL_RCC_CSR_SFTRSTF                RCC_CSR_SFTRSTF         /*!< Software Reset flag */
00184 #define LL_RCC_CSR_IWDGRSTF               RCC_CSR_IWDGRSTF        /*!< Independent Watchdog reset flag */
00185 #define LL_RCC_CSR_WWDGRSTF               RCC_CSR_WWDGRSTF        /*!< Window watchdog reset flag */
00186 #define LL_RCC_CSR_LPWRRSTF               RCC_CSR_LPWRRSTF        /*!< Low-Power reset flag */
00187 #if defined(RCC_CSR_V18PWRRSTF)
00188 #define LL_RCC_CSR_V18PWRRSTF             RCC_CSR_V18PWRRSTF      /*!< Reset flag of the 1.8 V domain. */
00189 #endif /* RCC_CSR_V18PWRRSTF */
00190 /**
00191   * @}
00192   */
00193
00194 /** @defgroup RCC_LL_EC_IT IT Defines
00195   * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
00196   * @{
00197   */
00198 #define LL_RCC_CIR_LSIRDYIE               RCC_CIR_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
00199 #define LL_RCC_CIR_LSERDYIE               RCC_CIR_LSERDYIE      /*!< LSE Ready Interrupt Enable */
00200 #define LL_RCC_CIR_HSIRDYIE               RCC_CIR_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
00201 #define LL_RCC_CIR_HSERDYIE               RCC_CIR_HSERDYIE      /*!< HSE Ready Interrupt Enable */
00202 #define LL_RCC_CIR_PLLRDYIE               RCC_CIR_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
00208   * @{
00209   */
00210 #define LL_RCC_LSEDRIVE_LOW                ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */
00211 #define LL_RCC_LSEDRIVE_MEDIUMLOW          RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
00212 #define LL_RCC_LSEDRIVE_MEDIUMHIGH         RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
00213 #define LL_RCC_LSEDRIVE_HIGH               RCC_BDCR_LSEDRV   /*!< Xtal mode higher driving capability */
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
00219   * @{
00220   */
00221 #define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
00222 #define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
00223 #define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
00229   * @{
00230   */
00231 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
00232 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
00233 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
00239   * @{
00240   */
00241 #define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
00242 #define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
00243 #define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
00244 #define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
00245 #define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
00246 #define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
00247 #define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
00248 #define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
00249 #define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
00255   * @{
00256   */
00257 #define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
00258 #define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
00259 #define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
00260 #define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
00261 #define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
00267   * @{
00268   */
00269 #define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
00270 #define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
00271 #define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
00272 #define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
00273 #define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
00274 /**
00275   * @}
00276   */
00277
00278 /** @defgroup RCC_LL_EC_MCO1SOURCE  MCO1 SOURCE selection
00279   * @{
00280   */
00281 #define LL_RCC_MCO1SOURCE_NOCLOCK          RCC_CFGR_MCOSEL_NOCLOCK      /*!< MCO output disabled, no clock on MCO */
00282 #define LL_RCC_MCO1SOURCE_SYSCLK           RCC_CFGR_MCOSEL_SYSCLK       /*!< SYSCLK selection as MCO source */
00283 #define LL_RCC_MCO1SOURCE_HSI              RCC_CFGR_MCOSEL_HSI          /*!< HSI selection as MCO source */
00284 #define LL_RCC_MCO1SOURCE_HSE              RCC_CFGR_MCOSEL_HSE          /*!< HSE selection as MCO source */
00285 #define LL_RCC_MCO1SOURCE_LSI              RCC_CFGR_MCOSEL_LSI          /*!< LSI selection as MCO source */
00286 #define LL_RCC_MCO1SOURCE_LSE              RCC_CFGR_MCOSEL_LSE          /*!< LSE selection as MCO source */
00287 #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2     RCC_CFGR_MCOSEL_PLL_DIV2     /*!< PLL clock divided by 2*/
00288 #if defined(RCC_CFGR_PLLNODIV)
00289 #define LL_RCC_MCO1SOURCE_PLLCLK           (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/
00290 #endif /* RCC_CFGR_PLLNODIV */
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup RCC_LL_EC_MCO1_DIV  MCO1 prescaler
00296   * @{
00297   */
00298 #define LL_RCC_MCO1_DIV_1                  ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */
00299 #if defined(RCC_CFGR_MCOPRE)
00300 #define LL_RCC_MCO1_DIV_2                  RCC_CFGR_MCOPRE_DIV2   /*!< MCO Clock divided by 2 */
00301 #define LL_RCC_MCO1_DIV_4                  RCC_CFGR_MCOPRE_DIV4   /*!< MCO Clock divided by 4 */
00302 #define LL_RCC_MCO1_DIV_8                  RCC_CFGR_MCOPRE_DIV8   /*!< MCO Clock divided by 8 */
00303 #define LL_RCC_MCO1_DIV_16                 RCC_CFGR_MCOPRE_DIV16  /*!< MCO Clock divided by 16 */
00304 #define LL_RCC_MCO1_DIV_32                 RCC_CFGR_MCOPRE_DIV32  /*!< MCO Clock divided by 32 */
00305 #define LL_RCC_MCO1_DIV_64                 RCC_CFGR_MCOPRE_DIV64  /*!< MCO Clock divided by 64 */
00306 #define LL_RCC_MCO1_DIV_128                RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */
00307 #endif /* RCC_CFGR_MCOPRE */
00308 /**
00309   * @}
00310   */
00311
00312 #if defined(USE_FULL_LL_DRIVER)
00313 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
00314   * @{
00315   */
00316 #define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U      /*!< No clock enabled for the peripheral            */
00317 #define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU      /*!< Frequency cannot be provided as external clock */
00318 /**
00319   * @}
00320   */
00321 #endif /* USE_FULL_LL_DRIVER */
00322
00323 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
00324   * @{
00325   */
00326 #if defined(RCC_CFGR3_USART1SW_PCLK1)
00327 #define LL_RCC_USART1_CLKSOURCE_PCLK1    (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK1)  /*!< PCLK1 clock used as USART1 clock source */
00328 #else
00329 #define LL_RCC_USART1_CLKSOURCE_PCLK2    (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK2)  /*!< PCLK2 clock used as USART1 clock source */
00330 #endif /*RCC_CFGR3_USART1SW_PCLK1*/
00331 #define LL_RCC_USART1_CLKSOURCE_SYSCLK   (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */
00332 #define LL_RCC_USART1_CLKSOURCE_LSE      (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_LSE)    /*!< LSE oscillator clock used as USART1 clock source */
00333 #define LL_RCC_USART1_CLKSOURCE_HSI      (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_HSI)    /*!< HSI oscillator clock used as USART1 clock source */
00334 #if defined(RCC_CFGR3_USART2SW)
00335 #define LL_RCC_USART2_CLKSOURCE_PCLK1    (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_PCLK)   /*!< PCLK1 clock used as USART2 clock source */
00336 #define LL_RCC_USART2_CLKSOURCE_SYSCLK   (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */
00337 #define LL_RCC_USART2_CLKSOURCE_LSE      (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_LSE)    /*!< LSE oscillator clock used as USART2 clock source */
00338 #define LL_RCC_USART2_CLKSOURCE_HSI      (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_HSI)    /*!< HSI oscillator clock used as USART2 clock source */
00339 #endif /* RCC_CFGR3_USART2SW */
00340 #if defined(RCC_CFGR3_USART3SW)
00341 #define LL_RCC_USART3_CLKSOURCE_PCLK1    (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_PCLK)   /*!< PCLK1 clock used as USART3 clock source */
00342 #define LL_RCC_USART3_CLKSOURCE_SYSCLK   (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */
00343 #define LL_RCC_USART3_CLKSOURCE_LSE      (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_LSE)    /*!< LSE oscillator clock used as USART3 clock source */
00344 #define LL_RCC_USART3_CLKSOURCE_HSI      (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_HSI)    /*!< HSI oscillator clock used as USART3 clock source */
00345 #endif /* RCC_CFGR3_USART3SW */
00346 /**
00347   * @}
00348   */
00349
00350 #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
00351 /** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection
00352   * @{
00353   */
00354 #define LL_RCC_UART4_CLKSOURCE_PCLK1     (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_PCLK)   /*!< PCLK1 clock used as UART4 clock source */
00355 #define LL_RCC_UART4_CLKSOURCE_SYSCLK    (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_SYSCLK) /*!< System clock selected as UART4 clock source */
00356 #define LL_RCC_UART4_CLKSOURCE_LSE       (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_LSE)    /*!< LSE oscillator clock used as UART4 clock source */
00357 #define LL_RCC_UART4_CLKSOURCE_HSI       (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_HSI)    /*!< HSI oscillator clock used as UART4 clock source */
00358 #define LL_RCC_UART5_CLKSOURCE_PCLK1     (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_PCLK)   /*!< PCLK1 clock used as UART5 clock source */
00359 #define LL_RCC_UART5_CLKSOURCE_SYSCLK    (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_SYSCLK) /*!< System clock selected as UART5 clock source */
00360 #define LL_RCC_UART5_CLKSOURCE_LSE       (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_LSE)    /*!< LSE oscillator clock used as UART5 clock source */
00361 #define LL_RCC_UART5_CLKSOURCE_HSI       (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_HSI)    /*!< HSI oscillator clock used as UART5 clock source */
00362 /**
00363   * @}
00364   */
00365
00366 #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
00367
00368 /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
00369   * @{
00370   */
00371 #define LL_RCC_I2C1_CLKSOURCE_HSI        (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_HSI)    /*!< HSI oscillator clock used as I2C1 clock source */
00372 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK     (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_SYSCLK) /*!< System clock selected as I2C1 clock source */
00373 #if defined(RCC_CFGR3_I2C2SW)
00374 #define LL_RCC_I2C2_CLKSOURCE_HSI        (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_HSI)    /*!< HSI oscillator clock used as I2C2 clock source */
00375 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK     (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_SYSCLK) /*!< System clock selected as I2C2 clock source */
00376 #endif /*RCC_CFGR3_I2C2SW*/
00377 #if defined(RCC_CFGR3_I2C3SW)
00378 #define LL_RCC_I2C3_CLKSOURCE_HSI        (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_HSI)    /*!< HSI oscillator clock used as I2C3 clock source */
00379 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK     (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_SYSCLK) /*!< System clock selected as I2C3 clock source */
00380 #endif /*RCC_CFGR3_I2C3SW*/
00381 /**
00382   * @}
00383   */
00384
00385 #if defined(RCC_CFGR_I2SSRC)
00386 /** @defgroup RCC_LL_EC_I2S_CLKSOURCE Peripheral I2S clock source selection
00387   * @{
00388   */
00389 #define LL_RCC_I2S_CLKSOURCE_SYSCLK      RCC_CFGR_I2SSRC_SYSCLK /*!< System clock selected as I2S clock source */
00390 #define LL_RCC_I2S_CLKSOURCE_PIN         RCC_CFGR_I2SSRC_EXT    /*!< External clock selected as I2S clock source */
00391 /**
00392   * @}
00393   */
00394
00395 #endif /* RCC_CFGR_I2SSRC */
00396
00397 #if defined(RCC_CFGR3_TIMSW)
00398 /** @defgroup RCC_LL_EC_TIM1_CLKSOURCE Peripheral TIM clock source selection
00399   * @{
00400   */
00401 #define LL_RCC_TIM1_CLKSOURCE_PCLK2      (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PCLK2)   /*!< PCLK2 used as TIM1 clock source */
00402 #define LL_RCC_TIM1_CLKSOURCE_PLL        (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PLL)     /*!< PLL clock used as TIM1 clock source */
00403 #if defined(RCC_CFGR3_TIM8SW)
00404 #define LL_RCC_TIM8_CLKSOURCE_PCLK2      (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PCLK2)   /*!< PCLK2 used as TIM8 clock source */
00405 #define LL_RCC_TIM8_CLKSOURCE_PLL        (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PLL)     /*!< PLL clock used as TIM8 clock source */
00406 #endif /*RCC_CFGR3_TIM8SW*/
00407 #if defined(RCC_CFGR3_TIM15SW)
00408 #define LL_RCC_TIM15_CLKSOURCE_PCLK2     (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PCLK2) /*!< PCLK2 used as TIM15 clock source */
00409 #define LL_RCC_TIM15_CLKSOURCE_PLL       (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PLL)   /*!< PLL clock used as TIM15 clock source */
00410 #endif /*RCC_CFGR3_TIM15SW*/
00411 #if defined(RCC_CFGR3_TIM16SW)
00412 #define LL_RCC_TIM16_CLKSOURCE_PCLK2     (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PCLK2) /*!< PCLK2 used as TIM16 clock source */
00413 #define LL_RCC_TIM16_CLKSOURCE_PLL       (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PLL)   /*!< PLL clock used as TIM16 clock source */
00414 #endif /*RCC_CFGR3_TIM16SW*/
00415 #if defined(RCC_CFGR3_TIM17SW)
00416 #define LL_RCC_TIM17_CLKSOURCE_PCLK2     (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PCLK2) /*!< PCLK2 used as TIM17 clock source */
00417 #define LL_RCC_TIM17_CLKSOURCE_PLL       (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PLL)   /*!< PLL clock used as TIM17 clock source */
00418 #endif /*RCC_CFGR3_TIM17SW*/
00419 #if defined(RCC_CFGR3_TIM20SW)
00420 #define LL_RCC_TIM20_CLKSOURCE_PCLK2     (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PCLK2) /*!< PCLK2 used as TIM20 clock source */
00421 #define LL_RCC_TIM20_CLKSOURCE_PLL       (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PLL)   /*!< PLL clock used as TIM20 clock source */
00422 #endif /*RCC_CFGR3_TIM20SW*/
00423 #if defined(RCC_CFGR3_TIM2SW)
00424 #define LL_RCC_TIM2_CLKSOURCE_PCLK1      (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PCLK1)   /*!< PCLK1 used as TIM2 clock source */
00425 #define LL_RCC_TIM2_CLKSOURCE_PLL        (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PLL)     /*!< PLL clock used as TIM2 clock source */
00426 #endif /*RCC_CFGR3_TIM2SW*/
00427 #if defined(RCC_CFGR3_TIM34SW)
00428 #define LL_RCC_TIM34_CLKSOURCE_PCLK1     (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PCLK1) /*!< PCLK1 used as TIM3/4 clock source */
00429 #define LL_RCC_TIM34_CLKSOURCE_PLL       (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PLL)   /*!< PLL clock used as TIM3/4 clock source */
00430 #endif /*RCC_CFGR3_TIM34SW*/
00431 /**
00432   * @}
00433   */
00434
00435 #endif /* RCC_CFGR3_TIMSW */
00436
00437 #if defined(HRTIM1)
00438 /** @defgroup RCC_LL_EC_HRTIM1_CLKSOURCE Peripheral HRTIM1 clock source selection
00439   * @{
00440   */
00441 #define LL_RCC_HRTIM1_CLKSOURCE_PCLK2    RCC_CFGR3_HRTIM1SW_PCLK2 /*!< PCLK2 used as  HRTIM1 clock source */
00442 #define LL_RCC_HRTIM1_CLKSOURCE_PLL      RCC_CFGR3_HRTIM1SW_PLL   /*!< PLL clock used as  HRTIM1 clock source */
00443 /**
00444   * @}
00445   */
00446
00447 #endif /* HRTIM1 */
00448
00449 #if defined(CEC)
00450 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
00451   * @{
00452   */
00453 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV244  RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
00454 #define LL_RCC_CEC_CLKSOURCE_LSE         RCC_CFGR3_CECSW_LSE        /*!< LSE clock selected as HDMI CEC entry clock source */
00455 /**
00456   * @}
00457   */
00458
00459 #endif /* CEC */
00460
00461 #if defined(USB)
00462 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
00463   * @{
00464   */
00465 #define LL_RCC_USB_CLKSOURCE_PLL         RCC_CFGR_USBPRE_DIV1    /*!< USB prescaler is PLL clock divided by 1 */
00466 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 RCC_CFGR_USBPRE_DIV1_5  /*!< USB prescaler is PLL clock divided by 1.5 */
00467 /**
00468   * @}
00469   */
00470
00471 #endif /* USB */
00472
00473 #if defined(RCC_CFGR_ADCPRE)
00474 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
00475   * @{
00476   */
00477 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2    RCC_CFGR_ADCPRE_DIV2      /*!< ADC prescaler PCLK divided by 2 */
00478 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4    RCC_CFGR_ADCPRE_DIV4      /*!< ADC prescaler PCLK divided by 4 */
00479 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6    RCC_CFGR_ADCPRE_DIV6      /*!< ADC prescaler PCLK divided by 6 */
00480 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8    RCC_CFGR_ADCPRE_DIV8      /*!< ADC prescaler PCLK divided by 8 */
00481 /**
00482   * @}
00483   */
00484
00485 #elif defined(RCC_CFGR2_ADC1PRES)
00486 /** @defgroup RCC_LL_EC_ADC1_CLKSOURCE Peripheral ADC clock source selection
00487   * @{
00488   */
00489 #define LL_RCC_ADC1_CLKSRC_HCLK          RCC_CFGR2_ADC1PRES_NO     /*!< ADC1 clock disabled, ADC1 can use AHB clock */
00490 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_1     RCC_CFGR2_ADC1PRES_DIV1   /*!< ADC1 PLL clock divided by 1 */
00491 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_2     RCC_CFGR2_ADC1PRES_DIV2   /*!< ADC1 PLL clock divided by 2 */
00492 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_4     RCC_CFGR2_ADC1PRES_DIV4   /*!< ADC1 PLL clock divided by 4 */
00493 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_6     RCC_CFGR2_ADC1PRES_DIV6   /*!< ADC1 PLL clock divided by 6 */
00494 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_8     RCC_CFGR2_ADC1PRES_DIV8   /*!< ADC1 PLL clock divided by 8 */
00495 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_10    RCC_CFGR2_ADC1PRES_DIV10  /*!< ADC1 PLL clock divided by 10 */
00496 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_12    RCC_CFGR2_ADC1PRES_DIV12  /*!< ADC1 PLL clock divided by 12 */
00497 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_16    RCC_CFGR2_ADC1PRES_DIV16  /*!< ADC1 PLL clock divided by 16 */
00498 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_32    RCC_CFGR2_ADC1PRES_DIV32  /*!< ADC1 PLL clock divided by 32 */
00499 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_64    RCC_CFGR2_ADC1PRES_DIV64  /*!< ADC1 PLL clock divided by 64 */
00500 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_128   RCC_CFGR2_ADC1PRES_DIV128 /*!< ADC1 PLL clock divided by 128 */
00501 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_256   RCC_CFGR2_ADC1PRES_DIV256 /*!< ADC1 PLL clock divided by 256 */
00502 /**
00503   * @}
00504   */
00505
00506 #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
00507 #if defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34)
00508 /** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC12 clock source selection
00509   * @{
00510   */
00511 #define LL_RCC_ADC12_CLKSRC_HCLK         (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_NO)     /*!< ADC12 clock disabled, ADC12 can use AHB clock */
00512 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_1    (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV1)   /*!< ADC12 PLL clock divided by 1 */
00513 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_2    (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV2)   /*!< ADC12 PLL clock divided by 2 */
00514 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_4    (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV4)   /*!< ADC12 PLL clock divided by 4 */
00515 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_6    (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV6)   /*!< ADC12 PLL clock divided by 6 */
00516 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_8    (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV8)   /*!< ADC12 PLL clock divided by 8 */
00517 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_10   (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV10)  /*!< ADC12 PLL clock divided by 10 */
00518 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_12   (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV12)  /*!< ADC12 PLL clock divided by 12 */
00519 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_16   (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV16)  /*!< ADC12 PLL clock divided by 16 */
00520 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_32   (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV32)  /*!< ADC12 PLL clock divided by 32 */
00521 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_64   (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV64)  /*!< ADC12 PLL clock divided by 64 */
00522 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_128  (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV128) /*!< ADC12 PLL clock divided by 128 */
00523 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_256  (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV256) /*!< ADC12 PLL clock divided by 256 */
00524 /**
00525   * @}
00526   */
00527
00528 /** @defgroup RCC_LL_EC_ADC34_CLKSOURCE Peripheral ADC34 clock source selection
00529   * @{
00530   */
00531 #define LL_RCC_ADC34_CLKSRC_HCLK         (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_NO)     /*!< ADC34 clock disabled, ADC34 can use AHB clock */
00532 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_1    (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV1)   /*!< ADC34 PLL clock divided by 1 */
00533 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_2    (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV2)   /*!< ADC34 PLL clock divided by 2 */
00534 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_4    (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV4)   /*!< ADC34 PLL clock divided by 4 */
00535 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_6    (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV6)   /*!< ADC34 PLL clock divided by 6 */
00536 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_8    (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV8)   /*!< ADC34 PLL clock divided by 8 */
00537 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_10   (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV10)  /*!< ADC34 PLL clock divided by 10 */
00538 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_12   (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV12)  /*!< ADC34 PLL clock divided by 12 */
00539 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_16   (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV16)  /*!< ADC34 PLL clock divided by 16 */
00540 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_32   (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV32)  /*!< ADC34 PLL clock divided by 32 */
00541 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_64   (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV64)  /*!< ADC34 PLL clock divided by 64 */
00542 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_128  (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV128) /*!< ADC34 PLL clock divided by 128 */
00543 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_256  (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV256) /*!< ADC34 PLL clock divided by 256 */
00544 /**
00545   * @}
00546   */
00547
00548 #else
00549 /** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC clock source selection
00550   * @{
00551   */
00552 #define LL_RCC_ADC12_CLKSRC_HCLK         RCC_CFGR2_ADCPRE12_NO     /*!< ADC12 clock disabled, ADC12 can use AHB clock */
00553 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_1    RCC_CFGR2_ADCPRE12_DIV1   /*!< ADC12 PLL clock divided by 1 */
00554 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_2    RCC_CFGR2_ADCPRE12_DIV2   /*!< ADC12 PLL clock divided by 2 */
00555 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_4    RCC_CFGR2_ADCPRE12_DIV4   /*!< ADC12 PLL clock divided by 4 */
00556 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_6    RCC_CFGR2_ADCPRE12_DIV6   /*!< ADC12 PLL clock divided by 6 */
00557 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_8    RCC_CFGR2_ADCPRE12_DIV8   /*!< ADC12 PLL clock divided by 8 */
00558 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_10   RCC_CFGR2_ADCPRE12_DIV10  /*!< ADC12 PLL clock divided by 10 */
00559 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_12   RCC_CFGR2_ADCPRE12_DIV12  /*!< ADC12 PLL clock divided by 12 */
00560 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_16   RCC_CFGR2_ADCPRE12_DIV16  /*!< ADC12 PLL clock divided by 16 */
00561 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_32   RCC_CFGR2_ADCPRE12_DIV32  /*!< ADC12 PLL clock divided by 32 */
00562 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_64   RCC_CFGR2_ADCPRE12_DIV64  /*!< ADC12 PLL clock divided by 64 */
00563 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_128  RCC_CFGR2_ADCPRE12_DIV128 /*!< ADC12 PLL clock divided by 128 */
00564 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_256  RCC_CFGR2_ADCPRE12_DIV256 /*!< ADC12 PLL clock divided by 256 */
00565 /**
00566   * @}
00567   */
00568
00569 #endif /* RCC_CFGR2_ADCPRE12 && RCC_CFGR2_ADCPRE34 */
00570
00571 #endif /* RCC_CFGR_ADCPRE */
00572
00573 #if defined(RCC_CFGR_SDPRE)
00574 /** @defgroup RCC_LL_EC_SDADC_CLKSOURCE_SYSCLK Peripheral SDADC clock source selection
00575   * @{
00576   */
00577 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_1    RCC_CFGR_SDPRE_DIV1   /*!< SDADC CLK not divided */
00578 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_2    RCC_CFGR_SDPRE_DIV2   /*!< SDADC CLK divided by 2 */
00579 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_4    RCC_CFGR_SDPRE_DIV4   /*!< SDADC CLK divided by 4 */
00580 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_6    RCC_CFGR_SDPRE_DIV6   /*!< SDADC CLK divided by 6 */
00581 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_8    RCC_CFGR_SDPRE_DIV8   /*!< SDADC CLK divided by 8 */
00582 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_10   RCC_CFGR_SDPRE_DIV10  /*!< SDADC CLK divided by 10 */
00583 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_12   RCC_CFGR_SDPRE_DIV12  /*!< SDADC CLK divided by 12 */
00584 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_14   RCC_CFGR_SDPRE_DIV14  /*!< SDADC CLK divided by 14 */
00585 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_16   RCC_CFGR_SDPRE_DIV16  /*!< SDADC CLK divided by 16 */
00586 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_20   RCC_CFGR_SDPRE_DIV20  /*!< SDADC CLK divided by 20 */
00587 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_24   RCC_CFGR_SDPRE_DIV24  /*!< SDADC CLK divided by 24 */
00588 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_28   RCC_CFGR_SDPRE_DIV28  /*!< SDADC CLK divided by 28 */
00589 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_32   RCC_CFGR_SDPRE_DIV32  /*!< SDADC CLK divided by 32 */
00590 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_36   RCC_CFGR_SDPRE_DIV36  /*!< SDADC CLK divided by 36 */
00591 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_40   RCC_CFGR_SDPRE_DIV40  /*!< SDADC CLK divided by 40 */
00592 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_44   RCC_CFGR_SDPRE_DIV44  /*!< SDADC CLK divided by 44 */
00593 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_48   RCC_CFGR_SDPRE_DIV48  /*!< SDADC CLK divided by 48 */
00594 /**
00595   * @}
00596   */
00597
00598 #endif /* RCC_CFGR_SDPRE */
00599
00600 /** @defgroup RCC_LL_EC_USART Peripheral USART get clock source
00601   * @{
00602   */
00603 #define LL_RCC_USART1_CLKSOURCE          RCC_POSITION_USART1SW /*!< USART1 Clock source selection */
00604 #if defined(RCC_CFGR3_USART2SW)
00605 #define LL_RCC_USART2_CLKSOURCE          RCC_POSITION_USART2SW /*!< USART2 Clock source selection */
00606 #endif /* RCC_CFGR3_USART2SW */
00607 #if defined(RCC_CFGR3_USART3SW)
00608 #define LL_RCC_USART3_CLKSOURCE          RCC_POSITION_USART3SW /*!< USART3 Clock source selection */
00609 #endif /* RCC_CFGR3_USART3SW */
00610 /**
00611   * @}
00612   */
00613
00614 #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
00615 /** @defgroup RCC_LL_EC_UART Peripheral UART get clock source
00616   * @{
00617   */
00618 #define LL_RCC_UART4_CLKSOURCE           RCC_CFGR3_UART4SW /*!< UART4 Clock source selection */
00619 #define LL_RCC_UART5_CLKSOURCE           RCC_CFGR3_UART5SW /*!< UART5 Clock source selection */
00620 /**
00621   * @}
00622   */
00623
00624 #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
00625
00626 /** @defgroup RCC_LL_EC_I2C Peripheral I2C get clock source
00627   * @{
00628   */
00629 #define LL_RCC_I2C1_CLKSOURCE            RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */
00630 #if defined(RCC_CFGR3_I2C2SW)
00631 #define LL_RCC_I2C2_CLKSOURCE            RCC_CFGR3_I2C2SW /*!< I2C2 Clock source selection */
00632 #endif /*RCC_CFGR3_I2C2SW*/
00633 #if defined(RCC_CFGR3_I2C3SW)
00634 #define LL_RCC_I2C3_CLKSOURCE            RCC_CFGR3_I2C3SW /*!< I2C3 Clock source selection */
00635 #endif /*RCC_CFGR3_I2C3SW*/
00636 /**
00637   * @}
00638   */
00639
00640 #if defined(RCC_CFGR_I2SSRC)
00641 /** @defgroup RCC_LL_EC_I2S Peripheral I2S get clock source
00642   * @{
00643   */
00644 #define LL_RCC_I2S_CLKSOURCE             RCC_CFGR_I2SSRC       /*!< I2S Clock source selection */
00645 /**
00646   * @}
00647   */
00648
00649 #endif /* RCC_CFGR_I2SSRC */
00650
00651 #if defined(RCC_CFGR3_TIMSW)
00652 /** @defgroup RCC_LL_EC_TIM TIMx Peripheral TIM get clock source
00653   * @{
00654   */
00655 #define LL_RCC_TIM1_CLKSOURCE            (RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW)  /*!< TIM1 Clock source selection */
00656 #if defined(RCC_CFGR3_TIM2SW)
00657 #define LL_RCC_TIM2_CLKSOURCE            (RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW)  /*!< TIM2 Clock source selection */
00658 #endif /*RCC_CFGR3_TIM2SW*/
00659 #if defined(RCC_CFGR3_TIM8SW)
00660 #define LL_RCC_TIM8_CLKSOURCE            (RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW)  /*!< TIM8 Clock source selection */
00661 #endif /*RCC_CFGR3_TIM8SW*/
00662 #if defined(RCC_CFGR3_TIM15SW)
00663 #define LL_RCC_TIM15_CLKSOURCE           (RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) /*!< TIM15 Clock source selection */
00664 #endif /*RCC_CFGR3_TIM15SW*/
00665 #if defined(RCC_CFGR3_TIM16SW)
00666 #define LL_RCC_TIM16_CLKSOURCE           (RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) /*!< TIM16 Clock source selection */
00667 #endif /*RCC_CFGR3_TIM16SW*/
00668 #if defined(RCC_CFGR3_TIM17SW)
00669 #define LL_RCC_TIM17_CLKSOURCE           (RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) /*!< TIM17 Clock source selection */
00670 #endif /*RCC_CFGR3_TIM17SW*/
00671 #if defined(RCC_CFGR3_TIM20SW)
00672 #define LL_RCC_TIM20_CLKSOURCE           (RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) /*!< TIM20 Clock source selection */
00673 #endif /*RCC_CFGR3_TIM20SW*/
00674 #if defined(RCC_CFGR3_TIM34SW)
00675 #define LL_RCC_TIM34_CLKSOURCE           (RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) /*!< TIM3/4 Clock source selection */
00676 #endif /*RCC_CFGR3_TIM34SW*/
00677 /**
00678   * @}
00679   */
00680
00681 #endif /* RCC_CFGR3_TIMSW */
00682
00683 #if defined(HRTIM1)
00684 /** @defgroup RCC_LL_EC_HRTIM1 Peripheral HRTIM1 get clock source
00685   * @{
00686   */
00687 #define LL_RCC_HRTIM1_CLKSOURCE          RCC_CFGR3_HRTIM1SW /*!< HRTIM1 Clock source selection */
00688 /**
00689   * @}
00690   */
00691
00692 #endif /* HRTIM1 */
00693
00694 #if defined(CEC)
00695 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
00696   * @{
00697   */
00698 #define LL_RCC_CEC_CLKSOURCE             RCC_CFGR3_CECSW /*!< CEC Clock source selection */
00699 /**
00700   * @}
00701   */
00702
00703 #endif /* CEC */
00704
00705 #if defined(USB)
00706 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
00707   * @{
00708   */
00709 #define LL_RCC_USB_CLKSOURCE             RCC_CFGR_USBPRE /*!< USB Clock source selection */
00710 /**
00711   * @}
00712   */
00713
00714 #endif /* USB */
00715
00716 #if defined(RCC_CFGR_ADCPRE)
00717 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
00718   * @{
00719   */
00720 #define LL_RCC_ADC_CLKSOURCE             RCC_CFGR_ADCPRE /*!< ADC Clock source selection */
00721 /**
00722   * @}
00723   */
00724
00725 #endif /* RCC_CFGR_ADCPRE */
00726
00727 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
00728 /** @defgroup RCC_LL_EC_ADCXX Peripheral ADC get clock source
00729   * @{
00730   */
00731 #if defined(RCC_CFGR2_ADC1PRES)
00732 #define LL_RCC_ADC1_CLKSOURCE            RCC_CFGR2_ADC1PRES /*!< ADC1 Clock source selection */
00733 #else
00734 #define LL_RCC_ADC12_CLKSOURCE           RCC_CFGR2_ADCPRE12 /*!< ADC12 Clock source selection */
00735 #if defined(RCC_CFGR2_ADCPRE34)
00736 #define LL_RCC_ADC34_CLKSOURCE           RCC_CFGR2_ADCPRE34 /*!< ADC34 Clock source selection */
00737 #endif /*RCC_CFGR2_ADCPRE34*/
00738 #endif /*RCC_CFGR2_ADC1PRES*/
00739 /**
00740   * @}
00741   */
00742
00743 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
00744
00745 #if defined(RCC_CFGR_SDPRE)
00746 /** @defgroup RCC_LL_EC_SDADC Peripheral SDADC get clock source
00747   * @{
00748   */
00749 #define LL_RCC_SDADC_CLKSOURCE           RCC_CFGR_SDPRE  /*!< SDADC Clock source selection */
00750 /**
00751   * @}
00752   */
00753
00754 #endif /* RCC_CFGR_SDPRE */
00755
00756
00757 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
00758   * @{
00759   */
00760 #define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */
00761 #define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
00762 #define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
00763 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by 32 used as RTC clock */
00764 /**
00765   * @}
00766   */
00767
00768 /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
00769   * @{
00770   */
00771 #define LL_RCC_PLL_MUL_2                   RCC_CFGR_PLLMUL2  /*!< PLL input clock*2 */
00772 #define LL_RCC_PLL_MUL_3                   RCC_CFGR_PLLMUL3  /*!< PLL input clock*3 */
00773 #define LL_RCC_PLL_MUL_4                   RCC_CFGR_PLLMUL4  /*!< PLL input clock*4 */
00774 #define LL_RCC_PLL_MUL_5                   RCC_CFGR_PLLMUL5  /*!< PLL input clock*5 */
00775 #define LL_RCC_PLL_MUL_6                   RCC_CFGR_PLLMUL6  /*!< PLL input clock*6 */
00776 #define LL_RCC_PLL_MUL_7                   RCC_CFGR_PLLMUL7  /*!< PLL input clock*7 */
00777 #define LL_RCC_PLL_MUL_8                   RCC_CFGR_PLLMUL8  /*!< PLL input clock*8 */
00778 #define LL_RCC_PLL_MUL_9                   RCC_CFGR_PLLMUL9  /*!< PLL input clock*9 */
00779 #define LL_RCC_PLL_MUL_10                  RCC_CFGR_PLLMUL10  /*!< PLL input clock*10 */
00780 #define LL_RCC_PLL_MUL_11                  RCC_CFGR_PLLMUL11  /*!< PLL input clock*11 */
00781 #define LL_RCC_PLL_MUL_12                  RCC_CFGR_PLLMUL12  /*!< PLL input clock*12 */
00782 #define LL_RCC_PLL_MUL_13                  RCC_CFGR_PLLMUL13  /*!< PLL input clock*13 */
00783 #define LL_RCC_PLL_MUL_14                  RCC_CFGR_PLLMUL14  /*!< PLL input clock*14 */
00784 #define LL_RCC_PLL_MUL_15                  RCC_CFGR_PLLMUL15  /*!< PLL input clock*15 */
00785 #define LL_RCC_PLL_MUL_16                  RCC_CFGR_PLLMUL16  /*!< PLL input clock*16 */
00786 /**
00787   * @}
00788   */
00789
00790 /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
00791   * @{
00792   */
00793 #define LL_RCC_PLLSOURCE_HSE               RCC_CFGR_PLLSRC_HSE_PREDIV                    /*!< HSE/PREDIV clock selected as PLL entry clock source */
00794 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
00795 #define LL_RCC_PLLSOURCE_HSI               RCC_CFGR_PLLSRC_HSI_PREDIV                    /*!< HSI/PREDIV clock selected as PLL entry clock source */
00796 #else
00797 #define LL_RCC_PLLSOURCE_HSI_DIV_2         RCC_CFGR_PLLSRC_HSI_DIV2                      /*!< HSI clock divided by 2 selected as PLL entry clock source */
00798 #define LL_RCC_PLLSOURCE_HSE_DIV_1         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1)    /*!< HSE clock selected as PLL entry clock source */
00799 #define LL_RCC_PLLSOURCE_HSE_DIV_2         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2)    /*!< HSE/2 clock selected as PLL entry clock source */
00800 #define LL_RCC_PLLSOURCE_HSE_DIV_3         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3)    /*!< HSE/3 clock selected as PLL entry clock source */
00801 #define LL_RCC_PLLSOURCE_HSE_DIV_4         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4)    /*!< HSE/4 clock selected as PLL entry clock source */
00802 #define LL_RCC_PLLSOURCE_HSE_DIV_5         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5)    /*!< HSE/5 clock selected as PLL entry clock source */
00803 #define LL_RCC_PLLSOURCE_HSE_DIV_6         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6)    /*!< HSE/6 clock selected as PLL entry clock source */
00804 #define LL_RCC_PLLSOURCE_HSE_DIV_7         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7)    /*!< HSE/7 clock selected as PLL entry clock source */
00805 #define LL_RCC_PLLSOURCE_HSE_DIV_8         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8)    /*!< HSE/8 clock selected as PLL entry clock source */
00806 #define LL_RCC_PLLSOURCE_HSE_DIV_9         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9)    /*!< HSE/9 clock selected as PLL entry clock source */
00807 #define LL_RCC_PLLSOURCE_HSE_DIV_10        (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10)   /*!< HSE/10 clock selected as PLL entry clock source */
00808 #define LL_RCC_PLLSOURCE_HSE_DIV_11        (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11)   /*!< HSE/11 clock selected as PLL entry clock source */
00809 #define LL_RCC_PLLSOURCE_HSE_DIV_12        (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12)   /*!< HSE/12 clock selected as PLL entry clock source */
00810 #define LL_RCC_PLLSOURCE_HSE_DIV_13        (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13)   /*!< HSE/13 clock selected as PLL entry clock source */
00811 #define LL_RCC_PLLSOURCE_HSE_DIV_14        (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14)   /*!< HSE/14 clock selected as PLL entry clock source */
00812 #define LL_RCC_PLLSOURCE_HSE_DIV_15        (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15)   /*!< HSE/15 clock selected as PLL entry clock source */
00813 #define LL_RCC_PLLSOURCE_HSE_DIV_16        (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16)   /*!< HSE/16 clock selected as PLL entry clock source */
00814 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
00815 /**
00816   * @}
00817   */
00818
00819 /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
00820   * @{
00821   */
00822 #define LL_RCC_PREDIV_DIV_1                RCC_CFGR2_PREDIV_DIV1   /*!< PREDIV input clock not divided */
00823 #define LL_RCC_PREDIV_DIV_2                RCC_CFGR2_PREDIV_DIV2   /*!< PREDIV input clock divided by 2 */
00824 #define LL_RCC_PREDIV_DIV_3                RCC_CFGR2_PREDIV_DIV3   /*!< PREDIV input clock divided by 3 */
00825 #define LL_RCC_PREDIV_DIV_4                RCC_CFGR2_PREDIV_DIV4   /*!< PREDIV input clock divided by 4 */
00826 #define LL_RCC_PREDIV_DIV_5                RCC_CFGR2_PREDIV_DIV5   /*!< PREDIV input clock divided by 5 */
00827 #define LL_RCC_PREDIV_DIV_6                RCC_CFGR2_PREDIV_DIV6   /*!< PREDIV input clock divided by 6 */
00828 #define LL_RCC_PREDIV_DIV_7                RCC_CFGR2_PREDIV_DIV7   /*!< PREDIV input clock divided by 7 */
00829 #define LL_RCC_PREDIV_DIV_8                RCC_CFGR2_PREDIV_DIV8   /*!< PREDIV input clock divided by 8 */
00830 #define LL_RCC_PREDIV_DIV_9                RCC_CFGR2_PREDIV_DIV9   /*!< PREDIV input clock divided by 9 */
00831 #define LL_RCC_PREDIV_DIV_10               RCC_CFGR2_PREDIV_DIV10  /*!< PREDIV input clock divided by 10 */
00832 #define LL_RCC_PREDIV_DIV_11               RCC_CFGR2_PREDIV_DIV11  /*!< PREDIV input clock divided by 11 */
00833 #define LL_RCC_PREDIV_DIV_12               RCC_CFGR2_PREDIV_DIV12  /*!< PREDIV input clock divided by 12 */
00834 #define LL_RCC_PREDIV_DIV_13               RCC_CFGR2_PREDIV_DIV13  /*!< PREDIV input clock divided by 13 */
00835 #define LL_RCC_PREDIV_DIV_14               RCC_CFGR2_PREDIV_DIV14  /*!< PREDIV input clock divided by 14 */
00836 #define LL_RCC_PREDIV_DIV_15               RCC_CFGR2_PREDIV_DIV15  /*!< PREDIV input clock divided by 15 */
00837 #define LL_RCC_PREDIV_DIV_16               RCC_CFGR2_PREDIV_DIV16  /*!< PREDIV input clock divided by 16 */
00838 /**
00839   * @}
00840   */
00841
00842 /**
00843   * @}
00844   */
00845
00846 /* Exported macro ------------------------------------------------------------*/
00847 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
00848   * @{
00849   */
00850
00851 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
00852   * @{
00853   */
00854
00855 /**
00856   * @brief  Write a value in RCC register
00857   * @param  __REG__ Register to be written
00858   * @param  __VALUE__ Value to be written in the register
00859   * @retval None
00860   */
00861 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
00862
00863 /**
00864   * @brief  Read a value in RCC register
00865   * @param  __REG__ Register to be read
00866   * @retval Register value
00867   */
00868 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
00869 /**
00870   * @}
00871   */
00872
00873 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
00874   * @{
00875   */
00876
00877 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
00878 /**
00879   * @brief  Helper macro to calculate the PLLCLK frequency
00880   * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator()
00881   *             , @ref LL_RCC_PLL_GetPrediv());
00882   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
00883   * @param  __PLLMUL__ This parameter can be one of the following values:
00884   *         @arg @ref LL_RCC_PLL_MUL_2
00885   *         @arg @ref LL_RCC_PLL_MUL_3
00886   *         @arg @ref LL_RCC_PLL_MUL_4
00887   *         @arg @ref LL_RCC_PLL_MUL_5
00888   *         @arg @ref LL_RCC_PLL_MUL_6
00889   *         @arg @ref LL_RCC_PLL_MUL_7
00890   *         @arg @ref LL_RCC_PLL_MUL_8
00891   *         @arg @ref LL_RCC_PLL_MUL_9
00892   *         @arg @ref LL_RCC_PLL_MUL_10
00893   *         @arg @ref LL_RCC_PLL_MUL_11
00894   *         @arg @ref LL_RCC_PLL_MUL_12
00895   *         @arg @ref LL_RCC_PLL_MUL_13
00896   *         @arg @ref LL_RCC_PLL_MUL_14
00897   *         @arg @ref LL_RCC_PLL_MUL_15
00898   *         @arg @ref LL_RCC_PLL_MUL_16
00899   * @param  __PLLPREDIV__ This parameter can be one of the following values:
00900   *         @arg @ref LL_RCC_PREDIV_DIV_1
00901   *         @arg @ref LL_RCC_PREDIV_DIV_2
00902   *         @arg @ref LL_RCC_PREDIV_DIV_3
00903   *         @arg @ref LL_RCC_PREDIV_DIV_4
00904   *         @arg @ref LL_RCC_PREDIV_DIV_5
00905   *         @arg @ref LL_RCC_PREDIV_DIV_6
00906   *         @arg @ref LL_RCC_PREDIV_DIV_7
00907   *         @arg @ref LL_RCC_PREDIV_DIV_8
00908   *         @arg @ref LL_RCC_PREDIV_DIV_9
00909   *         @arg @ref LL_RCC_PREDIV_DIV_10
00910   *         @arg @ref LL_RCC_PREDIV_DIV_11
00911   *         @arg @ref LL_RCC_PREDIV_DIV_12
00912   *         @arg @ref LL_RCC_PREDIV_DIV_13
00913   *         @arg @ref LL_RCC_PREDIV_DIV_14
00914   *         @arg @ref LL_RCC_PREDIV_DIV_15
00915   *         @arg @ref LL_RCC_PREDIV_DIV_16
00916   * @retval PLL clock frequency (in Hz)
00917   */
00918 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \
00919           (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
00920
00921 #else
00922 /**
00923   * @brief  Helper macro to calculate the PLLCLK frequency
00924   * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
00925   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2)
00926   * @param  __PLLMUL__ This parameter can be one of the following values:
00927   *         @arg @ref LL_RCC_PLL_MUL_2
00928   *         @arg @ref LL_RCC_PLL_MUL_3
00929   *         @arg @ref LL_RCC_PLL_MUL_4
00930   *         @arg @ref LL_RCC_PLL_MUL_5
00931   *         @arg @ref LL_RCC_PLL_MUL_6
00932   *         @arg @ref LL_RCC_PLL_MUL_7
00933   *         @arg @ref LL_RCC_PLL_MUL_8
00934   *         @arg @ref LL_RCC_PLL_MUL_9
00935   *         @arg @ref LL_RCC_PLL_MUL_10
00936   *         @arg @ref LL_RCC_PLL_MUL_11
00937   *         @arg @ref LL_RCC_PLL_MUL_12
00938   *         @arg @ref LL_RCC_PLL_MUL_13
00939   *         @arg @ref LL_RCC_PLL_MUL_14
00940   *         @arg @ref LL_RCC_PLL_MUL_15
00941   *         @arg @ref LL_RCC_PLL_MUL_16
00942   * @retval PLL clock frequency (in Hz)
00943   */
00944 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
00945           ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
00946 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
00947 /**
00948   * @brief  Helper macro to calculate the HCLK frequency
00949   * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
00950   *        ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
00951   * @param  __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
00952   * @param  __AHBPRESCALER__ This parameter can be one of the following values:
00953   *         @arg @ref LL_RCC_SYSCLK_DIV_1
00954   *         @arg @ref LL_RCC_SYSCLK_DIV_2
00955   *         @arg @ref LL_RCC_SYSCLK_DIV_4
00956   *         @arg @ref LL_RCC_SYSCLK_DIV_8
00957   *         @arg @ref LL_RCC_SYSCLK_DIV_16
00958   *         @arg @ref LL_RCC_SYSCLK_DIV_64
00959   *         @arg @ref LL_RCC_SYSCLK_DIV_128
00960   *         @arg @ref LL_RCC_SYSCLK_DIV_256
00961   *         @arg @ref LL_RCC_SYSCLK_DIV_512
00962   * @retval HCLK clock frequency (in Hz)
00963   */
00964 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])
00965
00966 /**
00967   * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
00968   * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
00969   *        ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
00970   * @param  __HCLKFREQ__ HCLK frequency
00971   * @param  __APB1PRESCALER__: This parameter can be one of the following values:
00972   *         @arg @ref LL_RCC_APB1_DIV_1
00973   *         @arg @ref LL_RCC_APB1_DIV_2
00974   *         @arg @ref LL_RCC_APB1_DIV_4
00975   *         @arg @ref LL_RCC_APB1_DIV_8
00976   *         @arg @ref LL_RCC_APB1_DIV_16
00977   * @retval PCLK1 clock frequency (in Hz)
00978   */
00979 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos])
00980
00981 /**
00982   * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
00983   * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
00984   *        ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
00985   * @param  __HCLKFREQ__ HCLK frequency
00986   * @param  __APB2PRESCALER__: This parameter can be one of the following values:
00987   *         @arg @ref LL_RCC_APB2_DIV_1
00988   *         @arg @ref LL_RCC_APB2_DIV_2
00989   *         @arg @ref LL_RCC_APB2_DIV_4
00990   *         @arg @ref LL_RCC_APB2_DIV_8
00991   *         @arg @ref LL_RCC_APB2_DIV_16
00992   * @retval PCLK2 clock frequency (in Hz)
00993   */
00994 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos])
00995
00996 /**
00997   * @}
00998   */
00999
01000 /**
01001   * @}
01002   */
01003
01004 /* Exported functions --------------------------------------------------------*/
01005 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
01006   * @{
01007   */
01008
01009 /** @defgroup RCC_LL_EF_HSE HSE
01010   * @{
01011   */
01012
01013 /**
01014   * @brief  Enable the Clock Security System.
01015   * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
01016   * @retval None
01017   */
01018 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
01019 {
01020   SET_BIT(RCC->CR, RCC_CR_CSSON);
01021 }
01022
01023 /**
01024   * @brief  Disable the Clock Security System.
01025   * @note Cannot be disabled in HSE is ready (only by hardware)
01026   * @rmtoll CR           CSSON         LL_RCC_HSE_DisableCSS
01027   * @retval None
01028   */
01029 __STATIC_INLINE void LL_RCC_HSE_DisableCSS(void)
01030 {
01031   CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
01032 }
01033
01034 /**
01035   * @brief  Enable HSE external oscillator (HSE Bypass)
01036   * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
01037   * @retval None
01038   */
01039 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
01040 {
01041   SET_BIT(RCC->CR, RCC_CR_HSEBYP);
01042 }
01043
01044 /**
01045   * @brief  Disable HSE external oscillator (HSE Bypass)
01046   * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
01047   * @retval None
01048   */
01049 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
01050 {
01051   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
01052 }
01053
01054 /**
01055   * @brief  Enable HSE crystal oscillator (HSE ON)
01056   * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
01057   * @retval None
01058   */
01059 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
01060 {
01061   SET_BIT(RCC->CR, RCC_CR_HSEON);
01062 }
01063
01064 /**
01065   * @brief  Disable HSE crystal oscillator (HSE ON)
01066   * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
01067   * @retval None
01068   */
01069 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
01070 {
01071   CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
01072 }
01073
01074 /**
01075   * @brief  Check if HSE oscillator Ready
01076   * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
01077   * @retval State of bit (1 or 0).
01078   */
01079 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
01080 {
01081   return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
01082 }
01083
01084 /**
01085   * @}
01086   */
01087
01088 /** @defgroup RCC_LL_EF_HSI HSI
01089   * @{
01090   */
01091
01092 /**
01093   * @brief  Enable HSI oscillator
01094   * @rmtoll CR           HSION         LL_RCC_HSI_Enable
01095   * @retval None
01096   */
01097 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
01098 {
01099   SET_BIT(RCC->CR, RCC_CR_HSION);
01100 }
01101
01102 /**
01103   * @brief  Disable HSI oscillator
01104   * @rmtoll CR           HSION         LL_RCC_HSI_Disable
01105   * @retval None
01106   */
01107 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
01108 {
01109   CLEAR_BIT(RCC->CR, RCC_CR_HSION);
01110 }
01111
01112 /**
01113   * @brief  Check if HSI clock is ready
01114   * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
01115   * @retval State of bit (1 or 0).
01116   */
01117 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
01118 {
01119   return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
01120 }
01121
01122 /**
01123   * @brief  Get HSI Calibration value
01124   * @note When HSITRIM is written, HSICAL is updated with the sum of
01125   *       HSITRIM and the factory trim value
01126   * @rmtoll CR        HSICAL        LL_RCC_HSI_GetCalibration
01127   * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
01128   */
01129 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
01130 {
01131   return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
01132 }
01133
01134 /**
01135   * @brief  Set HSI Calibration trimming
01136   * @note user-programmable trimming value that is added to the HSICAL
01137   * @note Default value is 16, which, when added to the HSICAL value,
01138   *       should trim the HSI to 16 MHz +/- 1 %
01139   * @rmtoll CR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
01140   * @param  Value between Min_Data = 0x00 and Max_Data = 0x1F
01141   * @retval None
01142   */
01143 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
01144 {
01145   MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
01146 }
01147
01148 /**
01149   * @brief  Get HSI Calibration trimming
01150   * @rmtoll CR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
01151   * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
01152   */
01153 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
01154 {
01155   return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
01156 }
01157
01158 /**
01159   * @}
01160   */
01161
01162 /** @defgroup RCC_LL_EF_LSE LSE
01163   * @{
01164   */
01165
01166 /**
01167   * @brief  Enable  Low Speed External (LSE) crystal.
01168   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
01169   * @retval None
01170   */
01171 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
01172 {
01173   SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
01174 }
01175
01176 /**
01177   * @brief  Disable  Low Speed External (LSE) crystal.
01178   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
01179   * @retval None
01180   */
01181 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
01182 {
01183   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
01184 }
01185
01186 /**
01187   * @brief  Enable external clock source (LSE bypass).
01188   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
01189   * @retval None
01190   */
01191 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
01192 {
01193   SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
01194 }
01195
01196 /**
01197   * @brief  Disable external clock source (LSE bypass).
01198   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
01199   * @retval None
01200   */
01201 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
01202 {
01203   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
01204 }
01205
01206 /**
01207   * @brief  Set LSE oscillator drive capability
01208   * @note The oscillator is in Xtal mode when it is not in bypass mode.
01209   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
01210   * @param  LSEDrive This parameter can be one of the following values:
01211   *         @arg @ref LL_RCC_LSEDRIVE_LOW
01212   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
01213   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
01214   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
01215   * @retval None
01216   */
01217 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
01218 {
01219   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
01220 }
01221
01222 /**
01223   * @brief  Get LSE oscillator drive capability
01224   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
01225   * @retval Returned value can be one of the following values:
01226   *         @arg @ref LL_RCC_LSEDRIVE_LOW
01227   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
01228   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
01229   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
01230   */
01231 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
01232 {
01233   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
01234 }
01235
01236 /**
01237   * @brief  Check if LSE oscillator Ready
01238   * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
01239   * @retval State of bit (1 or 0).
01240   */
01241 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
01242 {
01243   return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
01244 }
01245
01246 /**
01247   * @}
01248   */
01249
01250 /** @defgroup RCC_LL_EF_LSI LSI
01251   * @{
01252   */
01253
01254 /**
01255   * @brief  Enable LSI Oscillator
01256   * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
01257   * @retval None
01258   */
01259 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
01260 {
01261   SET_BIT(RCC->CSR, RCC_CSR_LSION);
01262 }
01263
01264 /**
01265   * @brief  Disable LSI Oscillator
01266   * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
01267   * @retval None
01268   */
01269 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
01270 {
01271   CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
01272 }
01273
01274 /**
01275   * @brief  Check if LSI is Ready
01276   * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
01277   * @retval State of bit (1 or 0).
01278   */
01279 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
01280 {
01281   return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
01282 }
01283
01284 /**
01285   * @}
01286   */
01287
01288 /** @defgroup RCC_LL_EF_System System
01289   * @{
01290   */
01291
01292 /**
01293   * @brief  Configure the system clock source
01294   * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
01295   * @param  Source This parameter can be one of the following values:
01296   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
01297   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
01298   *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
01299   * @retval None
01300   */
01301 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
01302 {
01303   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
01304 }
01305
01306 /**
01307   * @brief  Get the system clock source
01308   * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
01309   * @retval Returned value can be one of the following values:
01310   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
01311   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
01312   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
01313   */
01314 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
01315 {
01316   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
01317 }
01318
01319 /**
01320   * @brief  Set AHB prescaler
01321   * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
01322   * @param  Prescaler This parameter can be one of the following values:
01323   *         @arg @ref LL_RCC_SYSCLK_DIV_1
01324   *         @arg @ref LL_RCC_SYSCLK_DIV_2
01325   *         @arg @ref LL_RCC_SYSCLK_DIV_4
01326   *         @arg @ref LL_RCC_SYSCLK_DIV_8
01327   *         @arg @ref LL_RCC_SYSCLK_DIV_16
01328   *         @arg @ref LL_RCC_SYSCLK_DIV_64
01329   *         @arg @ref LL_RCC_SYSCLK_DIV_128
01330   *         @arg @ref LL_RCC_SYSCLK_DIV_256
01331   *         @arg @ref LL_RCC_SYSCLK_DIV_512
01332   * @retval None
01333   */
01334 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
01335 {
01336   MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
01337 }
01338
01339 /**
01340   * @brief  Set APB1 prescaler
01341   * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
01342   * @param  Prescaler This parameter can be one of the following values:
01343   *         @arg @ref LL_RCC_APB1_DIV_1
01344   *         @arg @ref LL_RCC_APB1_DIV_2
01345   *         @arg @ref LL_RCC_APB1_DIV_4
01346   *         @arg @ref LL_RCC_APB1_DIV_8
01347   *         @arg @ref LL_RCC_APB1_DIV_16
01348   * @retval None
01349   */
01350 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
01351 {
01352   MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
01353 }
01354
01355 /**
01356   * @brief  Set APB2 prescaler
01357   * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
01358   * @param  Prescaler This parameter can be one of the following values:
01359   *         @arg @ref LL_RCC_APB2_DIV_1
01360   *         @arg @ref LL_RCC_APB2_DIV_2
01361   *         @arg @ref LL_RCC_APB2_DIV_4
01362   *         @arg @ref LL_RCC_APB2_DIV_8
01363   *         @arg @ref LL_RCC_APB2_DIV_16
01364   * @retval None
01365   */
01366 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
01367 {
01368   MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
01369 }
01370
01371 /**
01372   * @brief  Get AHB prescaler
01373   * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
01374   * @retval Returned value can be one of the following values:
01375   *         @arg @ref LL_RCC_SYSCLK_DIV_1
01376   *         @arg @ref LL_RCC_SYSCLK_DIV_2
01377   *         @arg @ref LL_RCC_SYSCLK_DIV_4
01378   *         @arg @ref LL_RCC_SYSCLK_DIV_8
01379   *         @arg @ref LL_RCC_SYSCLK_DIV_16
01380   *         @arg @ref LL_RCC_SYSCLK_DIV_64
01381   *         @arg @ref LL_RCC_SYSCLK_DIV_128
01382   *         @arg @ref LL_RCC_SYSCLK_DIV_256
01383   *         @arg @ref LL_RCC_SYSCLK_DIV_512
01384   */
01385 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
01386 {
01387   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
01388 }
01389
01390 /**
01391   * @brief  Get APB1 prescaler
01392   * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
01393   * @retval Returned value can be one of the following values:
01394   *         @arg @ref LL_RCC_APB1_DIV_1
01395   *         @arg @ref LL_RCC_APB1_DIV_2
01396   *         @arg @ref LL_RCC_APB1_DIV_4
01397   *         @arg @ref LL_RCC_APB1_DIV_8
01398   *         @arg @ref LL_RCC_APB1_DIV_16
01399   */
01400 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
01401 {
01402   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
01403 }
01404
01405 /**
01406   * @brief  Get APB2 prescaler
01407   * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
01408   * @retval Returned value can be one of the following values:
01409   *         @arg @ref LL_RCC_APB2_DIV_1
01410   *         @arg @ref LL_RCC_APB2_DIV_2
01411   *         @arg @ref LL_RCC_APB2_DIV_4
01412   *         @arg @ref LL_RCC_APB2_DIV_8
01413   *         @arg @ref LL_RCC_APB2_DIV_16
01414   */
01415 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
01416 {
01417   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
01418 }
01419
01420 /**
01421   * @}
01422   */
01423
01424 /** @defgroup RCC_LL_EF_MCO MCO
01425   * @{
01426   */
01427
01428 /**
01429   * @brief  Configure MCOx
01430   * @rmtoll CFGR         MCO           LL_RCC_ConfigMCO\n
01431   *         CFGR         MCOPRE        LL_RCC_ConfigMCO\n
01432   *         CFGR         PLLNODIV      LL_RCC_ConfigMCO
01433   * @param  MCOxSource This parameter can be one of the following values:
01434   *         @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
01435   *         @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
01436   *         @arg @ref LL_RCC_MCO1SOURCE_HSI
01437   *         @arg @ref LL_RCC_MCO1SOURCE_HSE
01438   *         @arg @ref LL_RCC_MCO1SOURCE_LSI
01439   *         @arg @ref LL_RCC_MCO1SOURCE_LSE
01440   *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*)
01441   *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
01442   *
01443   *         (*) value not defined in all devices
01444   * @param  MCOxPrescaler This parameter can be one of the following values:
01445   *         @arg @ref LL_RCC_MCO1_DIV_1
01446   *         @arg @ref LL_RCC_MCO1_DIV_2 (*)
01447   *         @arg @ref LL_RCC_MCO1_DIV_4 (*)
01448   *         @arg @ref LL_RCC_MCO1_DIV_8 (*)
01449   *         @arg @ref LL_RCC_MCO1_DIV_16 (*)
01450   *         @arg @ref LL_RCC_MCO1_DIV_32 (*)
01451   *         @arg @ref LL_RCC_MCO1_DIV_64 (*)
01452   *         @arg @ref LL_RCC_MCO1_DIV_128 (*)
01453   *
01454   *         (*) value not defined in all devices
01455   * @retval None
01456   */
01457 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
01458 {
01459 #if defined(RCC_CFGR_MCOPRE)
01460 #if defined(RCC_CFGR_PLLNODIV)
01461   MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler);
01462 #else
01463   MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
01464 #endif /* RCC_CFGR_PLLNODIV */
01465 #else
01466   MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
01467 #endif /* RCC_CFGR_MCOPRE */
01468 }
01469
01470 /**
01471   * @}
01472   */
01473
01474 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
01475   * @{
01476   */
01477
01478 /**
01479   * @brief  Configure USARTx clock source
01480   * @rmtoll CFGR3        USART1SW      LL_RCC_SetUSARTClockSource\n
01481   *         CFGR3        USART2SW      LL_RCC_SetUSARTClockSource\n
01482   *         CFGR3        USART3SW      LL_RCC_SetUSARTClockSource
01483   * @param  USARTxSource This parameter can be one of the following values:
01484   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*)
01485   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
01486   *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
01487   *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
01488   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
01489   *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
01490   *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
01491   *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
01492   *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
01493   *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
01494   *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
01495   *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
01496   *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
01497   *
01498   *         (*) value not defined in all devices.
01499   * @retval None
01500   */
01501 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
01502 {
01503   MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource  & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU));
01504 }
01505
01506 #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
01507 /**
01508   * @brief  Configure UARTx clock source
01509   * @rmtoll CFGR3        UART4SW       LL_RCC_SetUARTClockSource\n
01510   *         CFGR3        UART5SW       LL_RCC_SetUARTClockSource
01511   * @param  UARTxSource This parameter can be one of the following values:
01512   *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
01513   *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
01514   *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
01515   *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
01516   *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
01517   *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
01518   *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
01519   *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
01520   * @retval None
01521   */
01522 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
01523 {
01524   MODIFY_REG(RCC->CFGR3, ((UARTxSource  & 0x0000FFFFU) << 8U), (UARTxSource & (RCC_CFGR3_UART4SW | RCC_CFGR3_UART5SW)));
01525 }
01526 #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
01527
01528 /**
01529   * @brief  Configure I2Cx clock source
01530   * @rmtoll CFGR3        I2C1SW        LL_RCC_SetI2CClockSource\n
01531   *         CFGR3        I2C2SW        LL_RCC_SetI2CClockSource\n
01532   *         CFGR3        I2C3SW        LL_RCC_SetI2CClockSource
01533   * @param  I2CxSource This parameter can be one of the following values:
01534   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
01535   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
01536   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
01537   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
01538   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
01539   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
01540   *
01541   *         (*) value not defined in all devices.
01542   * @retval None
01543   */
01544 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
01545 {
01546   MODIFY_REG(RCC->CFGR3, ((I2CxSource  & 0xFF000000U) >> 24U), (I2CxSource & 0x00FFFFFFU));
01547 }
01548
01549 #if defined(RCC_CFGR_I2SSRC)
01550 /**
01551   * @brief  Configure I2Sx clock source
01552   * @rmtoll CFGR         I2SSRC        LL_RCC_SetI2SClockSource
01553   * @param  I2SxSource This parameter can be one of the following values:
01554   *         @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
01555   *         @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
01556   * @retval None
01557   */
01558 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
01559 {
01560   MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, I2SxSource);
01561 }
01562 #endif /* RCC_CFGR_I2SSRC */
01563
01564 #if defined(RCC_CFGR3_TIMSW)
01565 /**
01566   * @brief  Configure TIMx clock source
01567   * @rmtoll CFGR3        TIM1SW        LL_RCC_SetTIMClockSource\n
01568   *         CFGR3        TIM8SW        LL_RCC_SetTIMClockSource\n
01569   *         CFGR3        TIM15SW       LL_RCC_SetTIMClockSource\n
01570   *         CFGR3        TIM16SW       LL_RCC_SetTIMClockSource\n
01571   *         CFGR3        TIM17SW       LL_RCC_SetTIMClockSource\n
01572   *         CFGR3        TIM20SW       LL_RCC_SetTIMClockSource\n
01573   *         CFGR3        TIM2SW        LL_RCC_SetTIMClockSource\n
01574   *         CFGR3        TIM34SW       LL_RCC_SetTIMClockSource
01575   * @param  TIMxSource This parameter can be one of the following values:
01576   *         @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2
01577   *         @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
01578   *         @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*)
01579   *         @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*)
01580   *         @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*)
01581   *         @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*)
01582   *         @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*)
01583   *         @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*)
01584   *         @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*)
01585   *         @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*)
01586   *         @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*)
01587   *         @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*)
01588   *         @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*)
01589   *         @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*)
01590   *         @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*)
01591   *         @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*)
01592   *
01593   *         (*) value not defined in all devices.
01594   * @retval None
01595   */
01596 __STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource)
01597 {
01598   MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_TIM1SW << (TIMxSource >> 27U)), (TIMxSource & 0x03FFFFFFU));
01599 }
01600 #endif /* RCC_CFGR3_TIMSW */
01601
01602 #if defined(HRTIM1)
01603 /**
01604   * @brief  Configure HRTIMx clock source
01605   * @rmtoll CFGR3        HRTIMSW       LL_RCC_SetHRTIMClockSource
01606   * @param  HRTIMxSource This parameter can be one of the following values:
01607   *         @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2
01608   *         @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL
01609   * @retval None
01610   */
01611 __STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t HRTIMxSource)
01612 {
01613   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIMSW, HRTIMxSource);
01614 }
01615 #endif /* HRTIM1 */
01616
01617 #if defined(CEC)
01618 /**
01619   * @brief  Configure CEC clock source
01620   * @rmtoll CFGR3        CECSW         LL_RCC_SetCECClockSource
01621   * @param  CECxSource This parameter can be one of the following values:
01622   *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
01623   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
01624   * @retval None
01625   */
01626 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource)
01627 {
01628   MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource);
01629 }
01630 #endif /* CEC */
01631
01632 #if defined(USB)
01633 /**
01634   * @brief  Configure USB clock source
01635   * @rmtoll CFGR         USBPRE        LL_RCC_SetUSBClockSource
01636   * @param  USBxSource This parameter can be one of the following values:
01637   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
01638   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5
01639   * @retval None
01640   */
01641 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
01642 {
01643   MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
01644 }
01645 #endif /* USB */
01646
01647 #if defined(RCC_CFGR_ADCPRE)
01648 /**
01649   * @brief  Configure ADC clock source
01650   * @rmtoll CFGR         ADCPRE        LL_RCC_SetADCClockSource
01651   * @param  ADCxSource This parameter can be one of the following values:
01652   *         @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
01653   *         @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
01654   *         @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
01655   *         @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
01656   * @retval None
01657   */
01658 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
01659 {
01660   MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
01661 }
01662
01663 #elif defined(RCC_CFGR2_ADC1PRES)
01664 /**
01665   * @brief  Configure ADC clock source
01666   * @rmtoll CFGR2        ADC1PRES      LL_RCC_SetADCClockSource
01667   * @param  ADCxSource This parameter can be one of the following values:
01668   *         @arg @ref LL_RCC_ADC1_CLKSRC_HCLK
01669   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1
01670   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2
01671   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4
01672   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6
01673   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8
01674   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10
01675   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12
01676   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16
01677   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32
01678   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64
01679   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128
01680   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256
01681   * @retval None
01682   */
01683 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
01684 {
01685   MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, ADCxSource);
01686 }
01687
01688 #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
01689 /**
01690   * @brief  Configure ADC clock source
01691   * @rmtoll CFGR2        ADCPRE12      LL_RCC_SetADCClockSource\n
01692   *         CFGR2        ADCPRE34      LL_RCC_SetADCClockSource
01693   * @param  ADCxSource This parameter can be one of the following values:
01694   *         @arg @ref LL_RCC_ADC12_CLKSRC_HCLK
01695   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1
01696   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2
01697   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4
01698   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6
01699   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8
01700   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10
01701   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12
01702   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16
01703   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32
01704   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64
01705   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128
01706   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256
01707   *         @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*)
01708   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*)
01709   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*)
01710   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*)
01711   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*)
01712   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*)
01713   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*)
01714   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*)
01715   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*)
01716   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*)
01717   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*)
01718   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*)
01719   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*)
01720   *
01721   *         (*) value not defined in all devices.
01722   * @retval None
01723   */
01724 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
01725 {
01726 #if defined(RCC_CFGR2_ADCPRE34)
01727   MODIFY_REG(RCC->CFGR2, (ADCxSource >> 16U), (ADCxSource & 0x0000FFFFU));
01728 #else
01729   MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, ADCxSource);
01730 #endif /* RCC_CFGR2_ADCPRE34 */
01731 }
01732 #endif /* RCC_CFGR_ADCPRE */
01733
01734 #if defined(RCC_CFGR_SDPRE)
01735 /**
01736   * @brief  Configure SDADCx clock source
01737   * @rmtoll CFGR         SDPRE      LL_RCC_SetSDADCClockSource
01738   * @param  SDADCxSource This parameter can be one of the following values:
01739   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1
01740   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2
01741   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4
01742   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6
01743   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8
01744   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10
01745   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12
01746   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14
01747   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16
01748   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20
01749   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24
01750   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28
01751   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32
01752   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36
01753   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40
01754   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44
01755   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48
01756   * @retval None
01757   */
01758 __STATIC_INLINE void LL_RCC_SetSDADCClockSource(uint32_t SDADCxSource)
01759 {
01760   MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, SDADCxSource);
01761 }
01762 #endif /* RCC_CFGR_SDPRE */
01763
01764 /**
01765   * @brief  Get USARTx clock source
01766   * @rmtoll CFGR3        USART1SW      LL_RCC_GetUSARTClockSource\n
01767   *         CFGR3        USART2SW      LL_RCC_GetUSARTClockSource\n
01768   *         CFGR3        USART3SW      LL_RCC_GetUSARTClockSource
01769   * @param  USARTx This parameter can be one of the following values:
01770   *         @arg @ref LL_RCC_USART1_CLKSOURCE
01771   *         @arg @ref LL_RCC_USART2_CLKSOURCE (*)
01772   *         @arg @ref LL_RCC_USART3_CLKSOURCE (*)
01773   *
01774   *         (*) value not defined in all devices.
01775   * @retval Returned value can be one of the following values:
01776   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*)
01777   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
01778   *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
01779   *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
01780   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
01781   *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
01782   *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
01783   *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
01784   *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
01785   *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
01786   *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
01787   *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
01788   *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
01789   *
01790   *         (*) value not defined in all devices.
01791   */
01792 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
01793 {
01794   return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U));
01795 }
01796
01797 #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
01798 /**
01799   * @brief  Get UARTx clock source
01800   * @rmtoll CFGR3        UART4SW       LL_RCC_GetUARTClockSource\n
01801   *         CFGR3        UART5SW       LL_RCC_GetUARTClockSource
01802   * @param  UARTx This parameter can be one of the following values:
01803   *         @arg @ref LL_RCC_UART4_CLKSOURCE
01804   *         @arg @ref LL_RCC_UART5_CLKSOURCE
01805   * @retval Returned value can be one of the following values:
01806   *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
01807   *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
01808   *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
01809   *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
01810   *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
01811   *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
01812   *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
01813   *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
01814   */
01815 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
01816 {
01817   return (uint32_t)(READ_BIT(RCC->CFGR3, UARTx) | (UARTx >> 8U));
01818 }
01819 #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
01820
01821 /**
01822   * @brief  Get I2Cx clock source
01823   * @rmtoll CFGR3        I2C1SW        LL_RCC_GetI2CClockSource\n
01824   *         CFGR3        I2C2SW        LL_RCC_GetI2CClockSource\n
01825   *         CFGR3        I2C3SW        LL_RCC_GetI2CClockSource
01826   * @param  I2Cx This parameter can be one of the following values:
01827   *         @arg @ref LL_RCC_I2C1_CLKSOURCE
01828   *         @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
01829   *         @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
01830   *
01831   *         (*) value not defined in all devices.
01832   * @retval Returned value can be one of the following values:
01833   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
01834   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
01835   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
01836   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
01837   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
01838   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
01839   *
01840   *         (*) value not defined in all devices.
01841   */
01842 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
01843 {
01844   return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx) | (I2Cx << 24U));
01845 }
01846
01847 #if defined(RCC_CFGR_I2SSRC)
01848 /**
01849   * @brief  Get I2Sx clock source
01850   * @rmtoll CFGR         I2SSRC        LL_RCC_GetI2SClockSource
01851   * @param  I2Sx This parameter can be one of the following values:
01852   *         @arg @ref LL_RCC_I2S_CLKSOURCE
01853   * @retval Returned value can be one of the following values:
01854   *         @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
01855   *         @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
01856   */
01857 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
01858 {
01859   return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
01860 }
01861 #endif /* RCC_CFGR_I2SSRC */
01862
01863 #if defined(RCC_CFGR3_TIMSW)
01864 /**
01865   * @brief  Get TIMx clock source
01866   * @rmtoll CFGR3        TIM1SW        LL_RCC_GetTIMClockSource\n
01867   *         CFGR3        TIM8SW        LL_RCC_GetTIMClockSource\n
01868   *         CFGR3        TIM15SW       LL_RCC_GetTIMClockSource\n
01869   *         CFGR3        TIM16SW       LL_RCC_GetTIMClockSource\n
01870   *         CFGR3        TIM17SW       LL_RCC_GetTIMClockSource\n
01871   *         CFGR3        TIM20SW       LL_RCC_GetTIMClockSource\n
01872   *         CFGR3        TIM2SW        LL_RCC_GetTIMClockSource\n
01873   *         CFGR3        TIM34SW       LL_RCC_GetTIMClockSource
01874   * @param  TIMx This parameter can be one of the following values:
01875   *         @arg @ref LL_RCC_TIM1_CLKSOURCE
01876   *         @arg @ref LL_RCC_TIM2_CLKSOURCE (*)
01877   *         @arg @ref LL_RCC_TIM8_CLKSOURCE (*)
01878   *         @arg @ref LL_RCC_TIM15_CLKSOURCE (*)
01879   *         @arg @ref LL_RCC_TIM16_CLKSOURCE (*)
01880   *         @arg @ref LL_RCC_TIM17_CLKSOURCE (*)
01881   *         @arg @ref LL_RCC_TIM20_CLKSOURCE (*)
01882   *         @arg @ref LL_RCC_TIM34_CLKSOURCE (*)
01883   *
01884   *         (*) value not defined in all devices.
01885   * @retval Returned value can be one of the following values:
01886   *         @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2
01887   *         @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
01888   *         @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*)
01889   *         @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*)
01890   *         @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*)
01891   *         @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*)
01892   *         @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*)
01893   *         @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*)
01894   *         @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*)
01895   *         @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*)
01896   *         @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*)
01897   *         @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*)
01898   *         @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*)
01899   *         @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*)
01900   *         @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*)
01901   *         @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*)
01902   *
01903   *         (*) value not defined in all devices.
01904   */
01905 __STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx)
01906 {
01907   return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_TIM1SW << TIMx)) | (TIMx << 27U));
01908 }
01909 #endif /* RCC_CFGR3_TIMSW */
01910
01911 #if defined(HRTIM1)
01912 /**
01913   * @brief  Get HRTIMx clock source
01914   * @rmtoll CFGR3        HRTIMSW       LL_RCC_GetHRTIMClockSource
01915   * @param  HRTIMx This parameter can be one of the following values:
01916   *         @arg @ref LL_RCC_HRTIM1_CLKSOURCE
01917   * @retval Returned value can be one of the following values:
01918   *         @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2
01919   *         @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL
01920   */
01921 __STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(uint32_t HRTIMx)
01922 {
01923   return (uint32_t)(READ_BIT(RCC->CFGR3, HRTIMx));
01924 }
01925 #endif /* HRTIM1 */
01926
01927 #if defined(CEC)
01928 /**
01929   * @brief  Get CEC clock source
01930   * @rmtoll CFGR3        CECSW         LL_RCC_GetCECClockSource
01931   * @param  CECx This parameter can be one of the following values:
01932   *         @arg @ref LL_RCC_CEC_CLKSOURCE
01933   * @retval Returned value can be one of the following values:
01934   *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
01935   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
01936   */
01937 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
01938 {
01939   return (uint32_t)(READ_BIT(RCC->CFGR3, CECx));
01940 }
01941 #endif /* CEC */
01942
01943 #if defined(USB)
01944 /**
01945   * @brief  Get USBx clock source
01946   * @rmtoll CFGR         USBPRE        LL_RCC_GetUSBClockSource
01947   * @param  USBx This parameter can be one of the following values:
01948   *         @arg @ref LL_RCC_USB_CLKSOURCE
01949   * @retval Returned value can be one of the following values:
01950   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
01951   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5
01952   */
01953 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
01954 {
01955   return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
01956 }
01957 #endif /* USB */
01958
01959 #if defined(RCC_CFGR_ADCPRE)
01960 /**
01961   * @brief  Get ADCx clock source
01962   * @rmtoll CFGR         ADCPRE        LL_RCC_GetADCClockSource
01963   * @param  ADCx This parameter can be one of the following values:
01964   *         @arg @ref LL_RCC_ADC_CLKSOURCE
01965   * @retval Returned value can be one of the following values:
01966   *         @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
01967   *         @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
01968   *         @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
01969   *         @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
01970   */
01971 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
01972 {
01973   return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
01974 }
01975
01976 #elif defined(RCC_CFGR2_ADC1PRES)
01977 /**
01978   * @brief  Get ADCx clock source
01979   * @rmtoll CFGR2        ADC1PRES      LL_RCC_GetADCClockSource
01980   * @param  ADCx This parameter can be one of the following values:
01981   *         @arg @ref LL_RCC_ADC1_CLKSOURCE
01982   * @retval Returned value can be one of the following values:
01983   *         @arg @ref LL_RCC_ADC1_CLKSRC_HCLK
01984   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1
01985   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2
01986   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4
01987   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6
01988   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8
01989   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10
01990   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12
01991   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16
01992   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32
01993   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64
01994   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128
01995   *         @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256
01996   */
01997 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
01998 {
01999   return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx));
02000 }
02001
02002 #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
02003 /**
02004   * @brief  Get ADCx clock source
02005   * @rmtoll CFGR2        ADCPRE12      LL_RCC_GetADCClockSource\n
02006   *         CFGR2        ADCPRE34      LL_RCC_GetADCClockSource
02007   * @param  ADCx This parameter can be one of the following values:
02008   *         @arg @ref LL_RCC_ADC12_CLKSOURCE
02009   *         @arg @ref LL_RCC_ADC34_CLKSOURCE (*)
02010   *
02011   *         (*) value not defined in all devices.
02012   * @retval Returned value can be one of the following values:
02013   *         @arg @ref LL_RCC_ADC12_CLKSRC_HCLK
02014   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1
02015   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2
02016   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4
02017   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6
02018   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8
02019   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10
02020   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12
02021   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16
02022   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32
02023   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64
02024   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128
02025   *         @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256
02026   *         @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*)
02027   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*)
02028   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*)
02029   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*)
02030   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*)
02031   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*)
02032   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*)
02033   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*)
02034   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*)
02035   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*)
02036   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*)
02037   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*)
02038   *         @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*)
02039   *
02040   *         (*) value not defined in all devices.
02041   */
02042 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
02043 {
02044 #if defined(RCC_CFGR2_ADCPRE34)
02045   return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx) | (ADCx << 16U));
02046 #else
02047   return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx));
02048 #endif /*RCC_CFGR2_ADCPRE34*/
02049 }
02050 #endif /* RCC_CFGR_ADCPRE */
02051
02052 #if defined(RCC_CFGR_SDPRE)
02053 /**
02054   * @brief  Get SDADCx clock source
02055   * @rmtoll CFGR         SDPRE      LL_RCC_GetSDADCClockSource
02056   * @param  SDADCx This parameter can be one of the following values:
02057   *         @arg @ref LL_RCC_SDADC_CLKSOURCE
02058   * @retval Returned value can be one of the following values:
02059   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1
02060   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2
02061   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4
02062   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6
02063   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8
02064   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10
02065   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12
02066   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14
02067   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16
02068   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20
02069   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24
02070   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28
02071   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32
02072   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36
02073   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40
02074   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44
02075   *         @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48
02076   */
02077 __STATIC_INLINE uint32_t LL_RCC_GetSDADCClockSource(uint32_t SDADCx)
02078 {
02079   return (uint32_t)(READ_BIT(RCC->CFGR, SDADCx));
02080 }
02081 #endif /* RCC_CFGR_SDPRE */
02082
02083 /**
02084   * @}
02085   */
02086
02087 /** @defgroup RCC_LL_EF_RTC RTC
02088   * @{
02089   */
02090
02091 /**
02092   * @brief  Set RTC Clock Source
02093   * @note Once the RTC clock source has been selected, it cannot be changed any more unless
02094   *       the Backup domain is reset. The BDRST bit can be used to reset them.
02095   * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
02096   * @param  Source This parameter can be one of the following values:
02097   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
02098   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
02099   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
02100   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
02101   * @retval None
02102   */
02103 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
02104 {
02105   MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
02106 }
02107
02108 /**
02109   * @brief  Get RTC Clock Source
02110   * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
02111   * @retval Returned value can be one of the following values:
02112   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
02113   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
02114   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
02115   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
02116   */
02117 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
02118 {
02119   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
02120 }
02121
02122 /**
02123   * @brief  Enable RTC
02124   * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
02125   * @retval None
02126   */
02127 __STATIC_INLINE void LL_RCC_EnableRTC(void)
02128 {
02129   SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
02130 }
02131
02132 /**
02133   * @brief  Disable RTC
02134   * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
02135   * @retval None
02136   */
02137 __STATIC_INLINE void LL_RCC_DisableRTC(void)
02138 {
02139   CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
02140 }
02141
02142 /**
02143   * @brief  Check if RTC has been enabled or not
02144   * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
02145   * @retval State of bit (1 or 0).
02146   */
02147 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
02148 {
02149   return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
02150 }
02151
02152 /**
02153   * @brief  Force the Backup domain reset
02154   * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset
02155   * @retval None
02156   */
02157 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
02158 {
02159   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
02160 }
02161
02162 /**
02163   * @brief  Release the Backup domain reset
02164   * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset
02165   * @retval None
02166   */
02167 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
02168 {
02169   CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
02170 }
02171
02172 /**
02173   * @}
02174   */
02175
02176 /** @defgroup RCC_LL_EF_PLL PLL
02177   * @{
02178   */
02179
02180 /**
02181   * @brief  Enable PLL
02182   * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
02183   * @retval None
02184   */
02185 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
02186 {
02187   SET_BIT(RCC->CR, RCC_CR_PLLON);
02188 }
02189
02190 /**
02191   * @brief  Disable PLL
02192   * @note Cannot be disabled if the PLL clock is used as the system clock
02193   * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
02194   * @retval None
02195   */
02196 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
02197 {
02198   CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
02199 }
02200
02201 /**
02202   * @brief  Check if PLL Ready
02203   * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
02204   * @retval State of bit (1 or 0).
02205   */
02206 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
02207 {
02208   return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
02209 }
02210
02211 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
02212 /**
02213   * @brief  Configure PLL used for SYSCLK Domain
02214   * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
02215   *         CFGR         PLLMUL        LL_RCC_PLL_ConfigDomain_SYS\n
02216   *         CFGR2        PREDIV        LL_RCC_PLL_ConfigDomain_SYS
02217   * @param  Source This parameter can be one of the following values:
02218   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02219   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02220   * @param  PLLMul This parameter can be one of the following values:
02221   *         @arg @ref LL_RCC_PLL_MUL_2
02222   *         @arg @ref LL_RCC_PLL_MUL_3
02223   *         @arg @ref LL_RCC_PLL_MUL_4
02224   *         @arg @ref LL_RCC_PLL_MUL_5
02225   *         @arg @ref LL_RCC_PLL_MUL_6
02226   *         @arg @ref LL_RCC_PLL_MUL_7
02227   *         @arg @ref LL_RCC_PLL_MUL_8
02228   *         @arg @ref LL_RCC_PLL_MUL_9
02229   *         @arg @ref LL_RCC_PLL_MUL_10
02230   *         @arg @ref LL_RCC_PLL_MUL_11
02231   *         @arg @ref LL_RCC_PLL_MUL_12
02232   *         @arg @ref LL_RCC_PLL_MUL_13
02233   *         @arg @ref LL_RCC_PLL_MUL_14
02234   *         @arg @ref LL_RCC_PLL_MUL_15
02235   *         @arg @ref LL_RCC_PLL_MUL_16
02236   * @param  PLLDiv This parameter can be one of the following values:
02237   *         @arg @ref LL_RCC_PREDIV_DIV_1
02238   *         @arg @ref LL_RCC_PREDIV_DIV_2
02239   *         @arg @ref LL_RCC_PREDIV_DIV_3
02240   *         @arg @ref LL_RCC_PREDIV_DIV_4
02241   *         @arg @ref LL_RCC_PREDIV_DIV_5
02242   *         @arg @ref LL_RCC_PREDIV_DIV_6
02243   *         @arg @ref LL_RCC_PREDIV_DIV_7
02244   *         @arg @ref LL_RCC_PREDIV_DIV_8
02245   *         @arg @ref LL_RCC_PREDIV_DIV_9
02246   *         @arg @ref LL_RCC_PREDIV_DIV_10
02247   *         @arg @ref LL_RCC_PREDIV_DIV_11
02248   *         @arg @ref LL_RCC_PREDIV_DIV_12
02249   *         @arg @ref LL_RCC_PREDIV_DIV_13
02250   *         @arg @ref LL_RCC_PREDIV_DIV_14
02251   *         @arg @ref LL_RCC_PREDIV_DIV_15
02252   *         @arg @ref LL_RCC_PREDIV_DIV_16
02253   * @retval None
02254   */
02255 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
02256 {
02257   MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul);
02258   MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv);
02259 }
02260
02261 #else
02262
02263 /**
02264   * @brief  Configure PLL used for SYSCLK Domain
02265   * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
02266   *         CFGR         PLLMUL        LL_RCC_PLL_ConfigDomain_SYS\n
02267   *         CFGR2        PREDIV        LL_RCC_PLL_ConfigDomain_SYS
02268   * @param  Source This parameter can be one of the following values:
02269   *         @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
02270   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
02271   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2
02272   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3
02273   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4
02274   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5
02275   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6
02276   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7
02277   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8
02278   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9
02279   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10
02280   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11
02281   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12
02282   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13
02283   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14
02284   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15
02285   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16
02286   * @param  PLLMul This parameter can be one of the following values:
02287   *         @arg @ref LL_RCC_PLL_MUL_2
02288   *         @arg @ref LL_RCC_PLL_MUL_3
02289   *         @arg @ref LL_RCC_PLL_MUL_4
02290   *         @arg @ref LL_RCC_PLL_MUL_5
02291   *         @arg @ref LL_RCC_PLL_MUL_6
02292   *         @arg @ref LL_RCC_PLL_MUL_7
02293   *         @arg @ref LL_RCC_PLL_MUL_8
02294   *         @arg @ref LL_RCC_PLL_MUL_9
02295   *         @arg @ref LL_RCC_PLL_MUL_10
02296   *         @arg @ref LL_RCC_PLL_MUL_11
02297   *         @arg @ref LL_RCC_PLL_MUL_12
02298   *         @arg @ref LL_RCC_PLL_MUL_13
02299   *         @arg @ref LL_RCC_PLL_MUL_14
02300   *         @arg @ref LL_RCC_PLL_MUL_15
02301   *         @arg @ref LL_RCC_PLL_MUL_16
02302   * @retval None
02303   */
02304 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
02305 {
02306   MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul);
02307   MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV));
02308 }
02309 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
02310
02311 /**
02312   * @brief  Get the oscillator used as PLL clock source.
02313   * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_GetMainSource
02314   * @retval Returned value can be one of the following values:
02315   *         @arg @ref LL_RCC_PLLSOURCE_HSI (*)
02316   *         @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*)
02317   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02318   *
02319   *         (*) value not defined in all devices
02320   */
02321 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
02322 {
02323   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
02324 }
02325
02326 /**
02327   * @brief  Get PLL multiplication Factor
02328   * @rmtoll CFGR         PLLMUL        LL_RCC_PLL_GetMultiplicator
02329   * @retval Returned value can be one of the following values:
02330   *         @arg @ref LL_RCC_PLL_MUL_2
02331   *         @arg @ref LL_RCC_PLL_MUL_3
02332   *         @arg @ref LL_RCC_PLL_MUL_4
02333   *         @arg @ref LL_RCC_PLL_MUL_5
02334   *         @arg @ref LL_RCC_PLL_MUL_6
02335   *         @arg @ref LL_RCC_PLL_MUL_7
02336   *         @arg @ref LL_RCC_PLL_MUL_8
02337   *         @arg @ref LL_RCC_PLL_MUL_9
02338   *         @arg @ref LL_RCC_PLL_MUL_10
02339   *         @arg @ref LL_RCC_PLL_MUL_11
02340   *         @arg @ref LL_RCC_PLL_MUL_12
02341   *         @arg @ref LL_RCC_PLL_MUL_13
02342   *         @arg @ref LL_RCC_PLL_MUL_14
02343   *         @arg @ref LL_RCC_PLL_MUL_15
02344   *         @arg @ref LL_RCC_PLL_MUL_16
02345   */
02346 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
02347 {
02348   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
02349 }
02350
02351 /**
02352   * @brief  Get PREDIV division factor for the main PLL
02353   * @note They can be written only when the PLL is disabled
02354   * @rmtoll CFGR2        PREDIV        LL_RCC_PLL_GetPrediv
02355   * @retval Returned value can be one of the following values:
02356   *         @arg @ref LL_RCC_PREDIV_DIV_1
02357   *         @arg @ref LL_RCC_PREDIV_DIV_2
02358   *         @arg @ref LL_RCC_PREDIV_DIV_3
02359   *         @arg @ref LL_RCC_PREDIV_DIV_4
02360   *         @arg @ref LL_RCC_PREDIV_DIV_5
02361   *         @arg @ref LL_RCC_PREDIV_DIV_6
02362   *         @arg @ref LL_RCC_PREDIV_DIV_7
02363   *         @arg @ref LL_RCC_PREDIV_DIV_8
02364   *         @arg @ref LL_RCC_PREDIV_DIV_9
02365   *         @arg @ref LL_RCC_PREDIV_DIV_10
02366   *         @arg @ref LL_RCC_PREDIV_DIV_11
02367   *         @arg @ref LL_RCC_PREDIV_DIV_12
02368   *         @arg @ref LL_RCC_PREDIV_DIV_13
02369   *         @arg @ref LL_RCC_PREDIV_DIV_14
02370   *         @arg @ref LL_RCC_PREDIV_DIV_15
02371   *         @arg @ref LL_RCC_PREDIV_DIV_16
02372   */
02373 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
02374 {
02375   return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV));
02376 }
02377
02378 /**
02379   * @}
02380   */
02381
02382 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
02383   * @{
02384   */
02385
02386 /**
02387   * @brief  Clear LSI ready interrupt flag
02388   * @rmtoll CIR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
02389   * @retval None
02390   */
02391 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
02392 {
02393   SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
02394 }
02395
02396 /**
02397   * @brief  Clear LSE ready interrupt flag
02398   * @rmtoll CIR         LSERDYC       LL_RCC_ClearFlag_LSERDY
02399   * @retval None
02400   */
02401 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
02402 {
02403   SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
02404 }
02405
02406 /**
02407   * @brief  Clear HSI ready interrupt flag
02408   * @rmtoll CIR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
02409   * @retval None
02410   */
02411 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
02412 {
02413   SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
02414 }
02415
02416 /**
02417   * @brief  Clear HSE ready interrupt flag
02418   * @rmtoll CIR         HSERDYC       LL_RCC_ClearFlag_HSERDY
02419   * @retval None
02420   */
02421 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
02422 {
02423   SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
02424 }
02425
02426 /**
02427   * @brief  Clear PLL ready interrupt flag
02428   * @rmtoll CIR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
02429   * @retval None
02430   */
02431 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
02432 {
02433   SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
02434 }
02435
02436 /**
02437   * @brief  Clear Clock security system interrupt flag
02438   * @rmtoll CIR         CSSC          LL_RCC_ClearFlag_HSECSS
02439   * @retval None
02440   */
02441 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
02442 {
02443   SET_BIT(RCC->CIR, RCC_CIR_CSSC);
02444 }
02445
02446 /**
02447   * @brief  Check if LSI ready interrupt occurred or not
02448   * @rmtoll CIR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
02449   * @retval State of bit (1 or 0).
02450   */
02451 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
02452 {
02453   return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
02454 }
02455
02456 /**
02457   * @brief  Check if LSE ready interrupt occurred or not
02458   * @rmtoll CIR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
02459   * @retval State of bit (1 or 0).
02460   */
02461 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
02462 {
02463   return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
02464 }
02465
02466 /**
02467   * @brief  Check if HSI ready interrupt occurred or not
02468   * @rmtoll CIR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
02469   * @retval State of bit (1 or 0).
02470   */
02471 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
02472 {
02473   return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
02474 }
02475
02476 /**
02477   * @brief  Check if HSE ready interrupt occurred or not
02478   * @rmtoll CIR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
02479   * @retval State of bit (1 or 0).
02480   */
02481 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
02482 {
02483   return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
02484 }
02485
02486 #if defined(RCC_CFGR_MCOF)
02487 /**
02488   * @brief  Check if switch to new MCO source is effective or not
02489   * @rmtoll CFGR         MCOF          LL_RCC_IsActiveFlag_MCO1
02490   * @retval State of bit (1 or 0).
02491   */
02492 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MCO1(void)
02493 {
02494   return (READ_BIT(RCC->CFGR, RCC_CFGR_MCOF) == (RCC_CFGR_MCOF));
02495 }
02496 #endif /* RCC_CFGR_MCOF */
02497
02498 /**
02499   * @brief  Check if PLL ready interrupt occurred or not
02500   * @rmtoll CIR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
02501   * @retval State of bit (1 or 0).
02502   */
02503 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
02504 {
02505   return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
02506 }
02507
02508 /**
02509   * @brief  Check if Clock security system interrupt occurred or not
02510   * @rmtoll CIR         CSSF          LL_RCC_IsActiveFlag_HSECSS
02511   * @retval State of bit (1 or 0).
02512   */
02513 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
02514 {
02515   return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
02516 }
02517
02518 /**
02519   * @brief  Check if RCC flag Independent Watchdog reset is set or not.
02520   * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
02521   * @retval State of bit (1 or 0).
02522   */
02523 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
02524 {
02525   return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
02526 }
02527
02528 /**
02529   * @brief  Check if RCC flag Low Power reset is set or not.
02530   * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
02531   * @retval State of bit (1 or 0).
02532   */
02533 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
02534 {
02535   return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
02536 }
02537
02538 /**
02539   * @brief  Check if RCC flag is set or not.
02540   * @rmtoll CSR          OBLRSTF       LL_RCC_IsActiveFlag_OBLRST
02541   * @retval State of bit (1 or 0).
02542   */
02543 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
02544 {
02545   return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
02546 }
02547
02548 /**
02549   * @brief  Check if RCC flag Pin reset is set or not.
02550   * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
02551   * @retval State of bit (1 or 0).
02552   */
02553 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
02554 {
02555   return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
02556 }
02557
02558 /**
02559   * @brief  Check if RCC flag POR/PDR reset is set or not.
02560   * @rmtoll CSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
02561   * @retval State of bit (1 or 0).
02562   */
02563 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
02564 {
02565   return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
02566 }
02567
02568 /**
02569   * @brief  Check if RCC flag Software reset is set or not.
02570   * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
02571   * @retval State of bit (1 or 0).
02572   */
02573 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
02574 {
02575   return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
02576 }
02577
02578 /**
02579   * @brief  Check if RCC flag Window Watchdog reset is set or not.
02580   * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
02581   * @retval State of bit (1 or 0).
02582   */
02583 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
02584 {
02585   return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
02586 }
02587
02588 #if defined(RCC_CSR_V18PWRRSTF)
02589 /**
02590   * @brief  Check if RCC Reset flag of the 1.8 V domain is set or not.
02591   * @rmtoll CSR          V18PWRRSTF    LL_RCC_IsActiveFlag_V18PWRRST
02592   * @retval State of bit (1 or 0).
02593   */
02594 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void)
02595 {
02596   return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF));
02597 }
02598 #endif /* RCC_CSR_V18PWRRSTF */
02599
02600 /**
02601   * @brief  Set RMVF bit to clear the reset flags.
02602   * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
02603   * @retval None
02604   */
02605 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
02606 {
02607   SET_BIT(RCC->CSR, RCC_CSR_RMVF);
02608 }
02609
02610 /**
02611   * @}
02612   */
02613
02614 /** @defgroup RCC_LL_EF_IT_Management IT Management
02615   * @{
02616   */
02617
02618 /**
02619   * @brief  Enable LSI ready interrupt
02620   * @rmtoll CIR         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
02621   * @retval None
02622   */
02623 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
02624 {
02625   SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
02626 }
02627
02628 /**
02629   * @brief  Enable LSE ready interrupt
02630   * @rmtoll CIR         LSERDYIE      LL_RCC_EnableIT_LSERDY
02631   * @retval None
02632   */
02633 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
02634 {
02635   SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
02636 }
02637
02638 /**
02639   * @brief  Enable HSI ready interrupt
02640   * @rmtoll CIR         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
02641   * @retval None
02642   */
02643 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
02644 {
02645   SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
02646 }
02647
02648 /**
02649   * @brief  Enable HSE ready interrupt
02650   * @rmtoll CIR         HSERDYIE      LL_RCC_EnableIT_HSERDY
02651   * @retval None
02652   */
02653 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
02654 {
02655   SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
02656 }
02657
02658 /**
02659   * @brief  Enable PLL ready interrupt
02660   * @rmtoll CIR         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
02661   * @retval None
02662   */
02663 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
02664 {
02665   SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
02666 }
02667
02668 /**
02669   * @brief  Disable LSI ready interrupt
02670   * @rmtoll CIR         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
02671   * @retval None
02672   */
02673 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
02674 {
02675   CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
02676 }
02677
02678 /**
02679   * @brief  Disable LSE ready interrupt
02680   * @rmtoll CIR         LSERDYIE      LL_RCC_DisableIT_LSERDY
02681   * @retval None
02682   */
02683 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
02684 {
02685   CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
02686 }
02687
02688 /**
02689   * @brief  Disable HSI ready interrupt
02690   * @rmtoll CIR         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
02691   * @retval None
02692   */
02693 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
02694 {
02695   CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
02696 }
02697
02698 /**
02699   * @brief  Disable HSE ready interrupt
02700   * @rmtoll CIR         HSERDYIE      LL_RCC_DisableIT_HSERDY
02701   * @retval None
02702   */
02703 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
02704 {
02705   CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
02706 }
02707
02708 /**
02709   * @brief  Disable PLL ready interrupt
02710   * @rmtoll CIR         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
02711   * @retval None
02712   */
02713 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
02714 {
02715   CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
02716 }
02717
02718 /**
02719   * @brief  Checks if LSI ready interrupt source is enabled or disabled.
02720   * @rmtoll CIR         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
02721   * @retval State of bit (1 or 0).
02722   */
02723 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
02724 {
02725   return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
02726 }
02727
02728 /**
02729   * @brief  Checks if LSE ready interrupt source is enabled or disabled.
02730   * @rmtoll CIR         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
02731   * @retval State of bit (1 or 0).
02732   */
02733 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
02734 {
02735   return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
02736 }
02737
02738 /**
02739   * @brief  Checks if HSI ready interrupt source is enabled or disabled.
02740   * @rmtoll CIR         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
02741   * @retval State of bit (1 or 0).
02742   */
02743 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
02744 {
02745   return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
02746 }
02747
02748 /**
02749   * @brief  Checks if HSE ready interrupt source is enabled or disabled.
02750   * @rmtoll CIR         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
02751   * @retval State of bit (1 or 0).
02752   */
02753 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
02754 {
02755   return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
02756 }
02757
02758 /**
02759   * @brief  Checks if PLL ready interrupt source is enabled or disabled.
02760   * @rmtoll CIR         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
02761   * @retval State of bit (1 or 0).
02762   */
02763 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
02764 {
02765   return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
02766 }
02767
02768 /**
02769   * @}
02770   */
02771
02772 #if defined(USE_FULL_LL_DRIVER)
02773 /** @defgroup RCC_LL_EF_Init De-initialization function
02774   * @{
02775   */
02776 ErrorStatus LL_RCC_DeInit(void);
02777 /**
02778   * @}
02779   */
02780
02781 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
02782   * @{
02783   */
02784 void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
02785 uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
02786 #if defined(UART4) || defined(UART5)
02787 uint32_t    LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
02788 #endif /* UART4 || UART5 */
02789 uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
02790 #if defined(RCC_CFGR_I2SSRC)
02791 uint32_t    LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
02792 #endif /* RCC_CFGR_I2SSRC */
02793 #if defined(USB_OTG_FS) || defined(USB)
02794 uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
02795 #endif /* USB_OTG_FS || USB */
02796 #if (defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34))
02797 uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
02798 #endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
02799 #if defined(RCC_CFGR_SDPRE)
02800 uint32_t    LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource);
02801 #endif /*RCC_CFGR_SDPRE */
02802 #if defined(CEC)
02803 uint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);
02804 #endif /* CEC */
02805 #if defined(RCC_CFGR3_TIMSW)
02806 uint32_t    LL_RCC_GetTIMClockFreq(uint32_t TIMxSource);
02807 #endif /*RCC_CFGR3_TIMSW*/
02808 uint32_t    LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource);
02809 /**
02810   * @}
02811   */
02812 #endif /* USE_FULL_LL_DRIVER */
02813
02814 /**
02815   * @}
02816   */
02817
02818 /**
02819   * @}
02820   */
02821
02822 #endif /* RCC */
02823
02824 /**
02825   * @}
02826   */
02827
02828 #ifdef __cplusplus
02829 }
02830 #endif
02831
02832 #endif /* __STM32F3xx_LL_RCC_H */
02833
02834 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_rtc.c Source File

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stm32f3xx_ll_rtc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_rtc.c
00004   * @author  MCD Application Team
00005   * @brief   RTC LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 #if defined(USE_FULL_LL_DRIVER)
00036
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f3xx_ll_rtc.h"
00039 #include "stm32f3xx_ll_cortex.h"
00040 #ifdef  USE_FULL_ASSERT
00041 #include "stm32_assert.h"
00042 #else
00043 #define assert_param(expr) ((void)0U)
00044 #endif
00045
00046 /** @addtogroup STM32F3xx_LL_Driver
00047   * @{
00048   */
00049
00050 #if defined(RTC)
00051
00052 /** @addtogroup RTC_LL
00053   * @{
00054   */
00055
00056 /* Private types -------------------------------------------------------------*/
00057 /* Private variables ---------------------------------------------------------*/
00058 /* Private constants ---------------------------------------------------------*/
00059 /** @addtogroup RTC_LL_Private_Constants
00060   * @{
00061   */
00062 /* Default values used for prescaler */
00063 #define RTC_ASYNCH_PRESC_DEFAULT     0x0000007FU
00064 #define RTC_SYNCH_PRESC_DEFAULT      0x000000FFU
00065
00066 /* Values used for timeout */
00067 #define RTC_INITMODE_TIMEOUT         1000U /* 1s when tick set to 1ms */
00068 #define RTC_SYNCHRO_TIMEOUT          1000U /* 1s when tick set to 1ms */
00069 /**
00070   * @}
00071   */
00072
00073 /* Private macros ------------------------------------------------------------*/
00074 /** @addtogroup RTC_LL_Private_Macros
00075   * @{
00076   */
00077
00078 #define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
00079                                       || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
00080
00081 #define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__)   ((__VALUE__) <= 0x7FU)
00082
00083 #define IS_LL_RTC_SYNCH_PREDIV(__VALUE__)    ((__VALUE__) <= 0x7FFFU)
00084
00085 #define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
00086                                   || ((__VALUE__) == LL_RTC_FORMAT_BCD))
00087
00088 #define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
00089                                        || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
00090
00091 #define IS_LL_RTC_HOUR12(__HOUR__)            (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
00092 #define IS_LL_RTC_HOUR24(__HOUR__)            ((__HOUR__) <= 23U)
00093 #define IS_LL_RTC_MINUTES(__MINUTES__)        ((__MINUTES__) <= 59U)
00094 #define IS_LL_RTC_SECONDS(__SECONDS__)        ((__SECONDS__) <= 59U)
00095
00096 #define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
00097                                    || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
00098                                    || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
00099                                    || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
00100                                    || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
00101                                    || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
00102                                    || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
00103
00104 #define IS_LL_RTC_DAY(__DAY__)    (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
00105
00106 #define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
00107                                  || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
00108                                  || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
00109                                  || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
00110                                  || ((__VALUE__) == LL_RTC_MONTH_MAY) \
00111                                  || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
00112                                  || ((__VALUE__) == LL_RTC_MONTH_JULY) \
00113                                  || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
00114                                  || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
00115                                  || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
00116                                  || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
00117                                  || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))
00118
00119 #define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
00120
00121 #define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
00122                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
00123                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
00124                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
00125                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
00126                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
00127
00128 #define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
00129                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
00130                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
00131                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
00132                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
00133                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
00134
00135
00136 #define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
00137                                                   ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
00138
00139 #define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
00140                                                   ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
00141
00142
00143 /**
00144   * @}
00145   */
00146 /* Private function prototypes -----------------------------------------------*/
00147 /* Exported functions --------------------------------------------------------*/
00148 /** @addtogroup RTC_LL_Exported_Functions
00149   * @{
00150   */
00151
00152 /** @addtogroup RTC_LL_EF_Init
00153   * @{
00154   */
00155
00156 /**
00157   * @brief  De-Initializes the RTC registers to their default reset values.
00158   * @note   This function doesn't reset the RTC Clock source and RTC Backup Data
00159   *         registers.
00160   * @param  RTCx RTC Instance
00161   * @retval An ErrorStatus enumeration value:
00162   *          - SUCCESS: RTC registers are de-initialized
00163   *          - ERROR: RTC registers are not de-initialized
00164   */
00165 ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
00166 {
00167   ErrorStatus status = ERROR;
00168
00169   /* Check the parameter */
00170   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00171
00172   /* Disable the write protection for RTC registers */
00173   LL_RTC_DisableWriteProtection(RTCx);
00174
00175   /* Set Initialization mode */
00176   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00177   {
00178     /* Reset TR, DR and CR registers */
00179     LL_RTC_WriteReg(RTCx, TR,       0x00000000U);
00180 #if defined(RTC_WAKEUP_SUPPORT)
00181     LL_RTC_WriteReg(RTCx, WUTR,     RTC_WUTR_WUT);
00182 #endif /* RTC_WAKEUP_SUPPORT */
00183     LL_RTC_WriteReg(RTCx, DR  ,     (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
00184     /* Reset All CR bits except CR[2:0] */
00185 #if defined(RTC_WAKEUP_SUPPORT)
00186     LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL));
00187 #else
00188     LL_RTC_WriteReg(RTCx, CR, 0x00000000U);
00189 #endif /* RTC_WAKEUP_SUPPORT */
00190     LL_RTC_WriteReg(RTCx, PRER,     (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
00191     LL_RTC_WriteReg(RTCx, ALRMAR,   0x00000000U);
00192     LL_RTC_WriteReg(RTCx, ALRMBR,   0x00000000U);
00193     LL_RTC_WriteReg(RTCx, SHIFTR,   0x00000000U);
00194     LL_RTC_WriteReg(RTCx, CALR,     0x00000000U);
00195     LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U);
00196     LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U);
00197
00198     /* Reset ISR register and exit initialization mode */
00199     LL_RTC_WriteReg(RTCx, ISR,      0x00000000U);
00200
00201     /* Reset Tamper and alternate functions configuration register */
00202     LL_RTC_WriteReg(RTCx, TAFCR, 0x00000000U);
00203
00204     /* Wait till the RTC RSF flag is set */
00205     status = LL_RTC_WaitForSynchro(RTCx);
00206   }
00207
00208   /* Enable the write protection for RTC registers */
00209   LL_RTC_EnableWriteProtection(RTCx);
00210
00211   return status;
00212 }
00213
00214 /**
00215   * @brief  Initializes the RTC registers according to the specified parameters
00216   *         in RTC_InitStruct.
00217   * @param  RTCx RTC Instance
00218   * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
00219   *         the configuration information for the RTC peripheral.
00220   * @note   The RTC Prescaler register is write protected and can be written in
00221   *         initialization mode only.
00222   * @retval An ErrorStatus enumeration value:
00223   *          - SUCCESS: RTC registers are initialized
00224   *          - ERROR: RTC registers are not initialized
00225   */
00226 ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
00227 {
00228   ErrorStatus status = ERROR;
00229
00230   /* Check the parameters */
00231   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00232   assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
00233   assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
00234   assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
00235
00236   /* Disable the write protection for RTC registers */
00237   LL_RTC_DisableWriteProtection(RTCx);
00238
00239   /* Set Initialization mode */
00240   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00241   {
00242     /* Set Hour Format */
00243     LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
00244
00245     /* Configure Synchronous and Asynchronous prescaler factor */
00246     LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
00247     LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
00248
00249     /* Exit Initialization mode */
00250     LL_RTC_DisableInitMode(RTCx);
00251
00252     status = SUCCESS;
00253   }
00254   /* Enable the write protection for RTC registers */
00255   LL_RTC_EnableWriteProtection(RTCx);
00256
00257   return status;
00258 }
00259
00260 /**
00261   * @brief  Set each @ref LL_RTC_InitTypeDef field to default value.
00262   * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
00263   * @retval None
00264   */
00265 void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
00266 {
00267   /* Set RTC_InitStruct fields to default values */
00268   RTC_InitStruct->HourFormat      = LL_RTC_HOURFORMAT_24HOUR;
00269   RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
00270   RTC_InitStruct->SynchPrescaler  = RTC_SYNCH_PRESC_DEFAULT;
00271 }
00272
00273 /**
00274   * @brief  Set the RTC current time.
00275   * @param  RTCx RTC Instance
00276   * @param  RTC_Format This parameter can be one of the following values:
00277   *         @arg @ref LL_RTC_FORMAT_BIN
00278   *         @arg @ref LL_RTC_FORMAT_BCD
00279   * @param  RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
00280   *                        the time configuration information for the RTC.
00281   * @retval An ErrorStatus enumeration value:
00282   *          - SUCCESS: RTC Time register is configured
00283   *          - ERROR: RTC Time register is not configured
00284   */
00285 ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
00286 {
00287   ErrorStatus status = ERROR;
00288
00289   /* Check the parameters */
00290   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00291   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00292
00293   if (RTC_Format == LL_RTC_FORMAT_BIN)
00294   {
00295     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00296     {
00297       assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
00298       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
00299     }
00300     else
00301     {
00302       RTC_TimeStruct->TimeFormat = 0x00U;
00303       assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
00304     }
00305     assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
00306     assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
00307   }
00308   else
00309   {
00310     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00311     {
00312       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
00313       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
00314     }
00315     else
00316     {
00317       RTC_TimeStruct->TimeFormat = 0x00U;
00318       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
00319     }
00320     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
00321     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
00322   }
00323
00324   /* Disable the write protection for RTC registers */
00325   LL_RTC_DisableWriteProtection(RTCx);
00326
00327   /* Set Initialization mode */
00328   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00329   {
00330     /* Check the input parameters format */
00331     if (RTC_Format != LL_RTC_FORMAT_BIN)
00332     {
00333       LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
00334                          RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
00335     }
00336     else
00337     {
00338       LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
00339                          __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
00340                          __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
00341     }
00342
00343     /* Exit Initialization mode */
00344     LL_RTC_DisableInitMode(RTC);
00345
00346     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00347     if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
00348     {
00349       status = LL_RTC_WaitForSynchro(RTCx);
00350     }
00351     else
00352     {
00353       status = SUCCESS;
00354     }
00355   }
00356   /* Enable the write protection for RTC registers */
00357   LL_RTC_EnableWriteProtection(RTCx);
00358
00359   return status;
00360 }
00361
00362 /**
00363   * @brief  Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
00364   * @param  RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
00365   * @retval None
00366   */
00367 void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
00368 {
00369   /* Time = 00h:00min:00sec */
00370   RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
00371   RTC_TimeStruct->Hours      = 0U;
00372   RTC_TimeStruct->Minutes    = 0U;
00373   RTC_TimeStruct->Seconds    = 0U;
00374 }
00375
00376 /**
00377   * @brief  Set the RTC current date.
00378   * @param  RTCx RTC Instance
00379   * @param  RTC_Format This parameter can be one of the following values:
00380   *         @arg @ref LL_RTC_FORMAT_BIN
00381   *         @arg @ref LL_RTC_FORMAT_BCD
00382   * @param  RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains
00383   *                         the date configuration information for the RTC.
00384   * @retval An ErrorStatus enumeration value:
00385   *          - SUCCESS: RTC Day register is configured
00386   *          - ERROR: RTC Day register is not configured
00387   */
00388 ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
00389 {
00390   ErrorStatus status = ERROR;
00391
00392   /* Check the parameters */
00393   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00394   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00395
00396   if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
00397   {
00398     RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU;
00399   }
00400   if (RTC_Format == LL_RTC_FORMAT_BIN)
00401   {
00402     assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
00403     assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
00404     assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
00405   }
00406   else
00407   {
00408     assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
00409     assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
00410     assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
00411   }
00412   assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
00413
00414   /* Disable the write protection for RTC registers */
00415   LL_RTC_DisableWriteProtection(RTCx);
00416
00417   /* Set Initialization mode */
00418   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00419   {
00420     /* Check the input parameters format */
00421     if (RTC_Format != LL_RTC_FORMAT_BIN)
00422     {
00423       LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
00424     }
00425     else
00426     {
00427       LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
00428                          __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
00429     }
00430
00431     /* Exit Initialization mode */
00432     LL_RTC_DisableInitMode(RTC);
00433
00434     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00435     if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
00436     {
00437       status = LL_RTC_WaitForSynchro(RTCx);
00438     }
00439     else
00440     {
00441       status = SUCCESS;
00442     }
00443   }
00444   /* Enable the write protection for RTC registers */
00445   LL_RTC_EnableWriteProtection(RTCx);
00446
00447   return status;
00448 }
00449
00450 /**
00451   * @brief  Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
00452   * @param  RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
00453   * @retval None
00454   */
00455 void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
00456 {
00457   /* Monday, January 01 xx00 */
00458   RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
00459   RTC_DateStruct->Day     = 1U;
00460   RTC_DateStruct->Month   = LL_RTC_MONTH_JANUARY;
00461   RTC_DateStruct->Year    = 0U;
00462 }
00463
00464 /**
00465   * @brief  Set the RTC Alarm A.
00466   * @note   The Alarm register can only be written when the corresponding Alarm
00467   *         is disabled (Use @ref LL_RTC_ALMA_Disable function).
00468   * @param  RTCx RTC Instance
00469   * @param  RTC_Format This parameter can be one of the following values:
00470   *         @arg @ref LL_RTC_FORMAT_BIN
00471   *         @arg @ref LL_RTC_FORMAT_BCD
00472   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
00473   *                         contains the alarm configuration parameters.
00474   * @retval An ErrorStatus enumeration value:
00475   *          - SUCCESS: ALARMA registers are configured
00476   *          - ERROR: ALARMA registers are not configured
00477   */
00478 ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00479 {
00480   /* Check the parameters */
00481   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00482   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00483   assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
00484   assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
00485
00486   if (RTC_Format == LL_RTC_FORMAT_BIN)
00487   {
00488     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00489     {
00490       assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
00491       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00492     }
00493     else
00494     {
00495       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00496       assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
00497     }
00498     assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
00499     assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
00500
00501     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00502     {
00503       assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
00504     }
00505     else
00506     {
00507       assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
00508     }
00509   }
00510   else
00511   {
00512     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00513     {
00514       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00515       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00516     }
00517     else
00518     {
00519       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00520       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00521     }
00522
00523     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
00524     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
00525
00526     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00527     {
00528       assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00529     }
00530     else
00531     {
00532       assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00533     }
00534   }
00535
00536   /* Disable the write protection for RTC registers */
00537   LL_RTC_DisableWriteProtection(RTCx);
00538
00539   /* Select weekday selection */
00540   if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00541   {
00542     /* Set the date for ALARM */
00543     LL_RTC_ALMA_DisableWeekday(RTCx);
00544     if (RTC_Format != LL_RTC_FORMAT_BIN)
00545     {
00546       LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00547     }
00548     else
00549     {
00550       LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
00551     }
00552   }
00553   else
00554   {
00555     /* Set the week day for ALARM */
00556     LL_RTC_ALMA_EnableWeekday(RTCx);
00557     LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00558   }
00559
00560   /* Configure the Alarm register */
00561   if (RTC_Format != LL_RTC_FORMAT_BIN)
00562   {
00563     LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
00564                            RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
00565   }
00566   else
00567   {
00568     LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
00569                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
00570                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
00571                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
00572   }
00573   /* Set ALARM mask */
00574   LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
00575
00576   /* Enable the write protection for RTC registers */
00577   LL_RTC_EnableWriteProtection(RTCx);
00578
00579   return SUCCESS;
00580 }
00581
00582 /**
00583   * @brief  Set the RTC Alarm B.
00584   * @note   The Alarm register can only be written when the corresponding Alarm
00585   *         is disabled (@ref LL_RTC_ALMB_Disable function).
00586   * @param  RTCx RTC Instance
00587   * @param  RTC_Format This parameter can be one of the following values:
00588   *         @arg @ref LL_RTC_FORMAT_BIN
00589   *         @arg @ref LL_RTC_FORMAT_BCD
00590   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
00591   *                         contains the alarm configuration parameters.
00592   * @retval An ErrorStatus enumeration value:
00593   *          - SUCCESS: ALARMB registers are configured
00594   *          - ERROR: ALARMB registers are not configured
00595   */
00596 ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00597 {
00598   /* Check the parameters */
00599   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00600   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00601   assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
00602   assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
00603
00604   if (RTC_Format == LL_RTC_FORMAT_BIN)
00605   {
00606     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00607     {
00608       assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
00609       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00610     }
00611     else
00612     {
00613       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00614       assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
00615     }
00616     assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
00617     assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
00618
00619     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00620     {
00621       assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
00622     }
00623     else
00624     {
00625       assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
00626     }
00627   }
00628   else
00629   {
00630     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00631     {
00632       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00633       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00634     }
00635     else
00636     {
00637       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00638       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00639     }
00640
00641     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
00642     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
00643
00644     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00645     {
00646       assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00647     }
00648     else
00649     {
00650       assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00651     }
00652   }
00653
00654   /* Disable the write protection for RTC registers */
00655   LL_RTC_DisableWriteProtection(RTCx);
00656
00657   /* Select weekday selection */
00658   if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00659   {
00660     /* Set the date for ALARM */
00661     LL_RTC_ALMB_DisableWeekday(RTCx);
00662     if (RTC_Format != LL_RTC_FORMAT_BIN)
00663     {
00664       LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00665     }
00666     else
00667     {
00668       LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
00669     }
00670   }
00671   else
00672   {
00673     /* Set the week day for ALARM */
00674     LL_RTC_ALMB_EnableWeekday(RTCx);
00675     LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00676   }
00677
00678   /* Configure the Alarm register */
00679   if (RTC_Format != LL_RTC_FORMAT_BIN)
00680   {
00681     LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
00682                            RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
00683   }
00684   else
00685   {
00686     LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
00687                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
00688                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
00689                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
00690   }
00691   /* Set ALARM mask */
00692   LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
00693
00694   /* Enable the write protection for RTC registers */
00695   LL_RTC_EnableWriteProtection(RTCx);
00696
00697   return SUCCESS;
00698 }
00699
00700 /**
00701   * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
00702   *         Day = 1st day of the month/Mask = all fields are masked).
00703   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
00704   * @retval None
00705   */
00706 void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00707 {
00708   /* Alarm Time Settings : Time = 00h:00mn:00sec */
00709   RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
00710   RTC_AlarmStruct->AlarmTime.Hours      = 0U;
00711   RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
00712   RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
00713
00714   /* Alarm Day Settings : Day = 1st day of the month */
00715   RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
00716   RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
00717
00718   /* Alarm Masks Settings : Mask =  all fields are not masked */
00719   RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMA_MASK_NONE;
00720 }
00721
00722 /**
00723   * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
00724   *         Day = 1st day of the month/Mask = all fields are masked).
00725   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
00726   * @retval None
00727   */
00728 void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00729 {
00730   /* Alarm Time Settings : Time = 00h:00mn:00sec */
00731   RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
00732   RTC_AlarmStruct->AlarmTime.Hours      = 0U;
00733   RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
00734   RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
00735
00736   /* Alarm Day Settings : Day = 1st day of the month */
00737   RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
00738   RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
00739
00740   /* Alarm Masks Settings : Mask =  all fields are not masked */
00741   RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMB_MASK_NONE;
00742 }
00743
00744 /**
00745   * @brief  Enters the RTC Initialization mode.
00746   * @note   The RTC Initialization mode is write protected, use the
00747   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00748   * @param  RTCx RTC Instance
00749   * @retval An ErrorStatus enumeration value:
00750   *          - SUCCESS: RTC is in Init mode
00751   *          - ERROR: RTC is not in Init mode
00752   */
00753 ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
00754 {
00755   __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
00756   ErrorStatus status = SUCCESS;
00757   uint32_t tmp = 0U;
00758
00759   /* Check the parameter */
00760   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00761
00762   /* Check if the Initialization mode is set */
00763   if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
00764   {
00765     /* Set the Initialization mode */
00766     LL_RTC_EnableInitMode(RTCx);
00767
00768     /* Wait till RTC is in INIT state and if Time out is reached exit */
00769     tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
00770     while ((timeout != 0U) && (tmp != 1U))
00771     {
00772       if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00773       {
00774         timeout --;
00775       }
00776       tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
00777       if (timeout == 0U)
00778       {
00779         status = ERROR;
00780       }
00781     }
00782   }
00783   return status;
00784 }
00785
00786 /**
00787   * @brief  Exit the RTC Initialization mode.
00788   * @note   When the initialization sequence is complete, the calendar restarts
00789   *         counting after 4 RTCCLK cycles.
00790   * @note   The RTC Initialization mode is write protected, use the
00791   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00792   * @param  RTCx RTC Instance
00793   * @retval An ErrorStatus enumeration value:
00794   *          - SUCCESS: RTC exited from in Init mode
00795   *          - ERROR: Not applicable
00796   */
00797 ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
00798 {
00799   /* Check the parameter */
00800   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00801
00802   /* Disable initialization mode */
00803   LL_RTC_DisableInitMode(RTCx);
00804
00805   return SUCCESS;
00806 }
00807
00808 /**
00809   * @brief  Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
00810   *         synchronized with RTC APB clock.
00811   * @note   The RTC Resynchronization mode is write protected, use the
00812   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00813   * @note   To read the calendar through the shadow registers after Calendar
00814   *         initialization, calendar update or after wakeup from low power modes
00815   *         the software must first clear the RSF flag.
00816   *         The software must then wait until it is set again before reading
00817   *         the calendar, which means that the calendar registers have been
00818   *         correctly copied into the RTC_TR and RTC_DR shadow registers.
00819   * @param  RTCx RTC Instance
00820   * @retval An ErrorStatus enumeration value:
00821   *          - SUCCESS: RTC registers are synchronised
00822   *          - ERROR: RTC registers are not synchronised
00823   */
00824 ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
00825 {
00826   __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
00827   ErrorStatus status = SUCCESS;
00828   uint32_t tmp = 0U;
00829
00830   /* Check the parameter */
00831   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00832
00833   /* Clear RSF flag */
00834   LL_RTC_ClearFlag_RS(RTCx);
00835
00836   /* Wait the registers to be synchronised */
00837   tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00838   while ((timeout != 0U) && (tmp != 0U))
00839   {
00840     if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00841     {
00842       timeout--;
00843     }
00844     tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00845     if (timeout == 0U)
00846     {
00847       status = ERROR;
00848     }
00849   }
00850
00851   if (status != ERROR)
00852   {
00853     timeout = RTC_SYNCHRO_TIMEOUT;
00854     tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00855     while ((timeout != 0U) && (tmp != 1U))
00856     {
00857       if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00858       {
00859         timeout--;
00860       }
00861       tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00862       if (timeout == 0U)
00863       {
00864         status = ERROR;
00865       }
00866     }
00867   }
00868
00869   return (status);
00870 }
00871
00872 /**
00873   * @}
00874   */
00875
00876 /**
00877   * @}
00878   */
00879
00880 /**
00881   * @}
00882   */
00883
00884 #endif /* defined(RTC) */
00885
00886 /**
00887   * @}
00888   */
00889
00890 #endif /* USE_FULL_LL_DRIVER */
00891
00892 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_rtc.h Source File

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stm32f3xx_ll_rtc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_rtc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RTC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_RTC_H
00038 #define __STM32F3xx_LL_RTC_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined(RTC)
00052
00053 /** @defgroup RTC_LL RTC
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059 /* Private constants ---------------------------------------------------------*/
00060 /** @defgroup RTC_LL_Private_Constants RTC Private Constants
00061   * @{
00062   */
00063 /* Masks Definition */
00064 #define RTC_INIT_MASK                 0xFFFFFFFFU
00065 #define RTC_RSF_MASK                  0xFFFFFF5FU
00066
00067 /* Write protection defines */
00068 #define RTC_WRITE_PROTECTION_DISABLE  ((uint8_t)0xFFU)
00069 #define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
00070 #define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
00071
00072 /* Defines used to combine date & time */
00073 #define RTC_OFFSET_WEEKDAY            24U
00074 #define RTC_OFFSET_DAY                16U
00075 #define RTC_OFFSET_MONTH              8U
00076 #define RTC_OFFSET_HOUR               16U
00077 #define RTC_OFFSET_MINUTE             8U
00078
00079 /**
00080   * @}
00081   */
00082
00083 /* Private macros ------------------------------------------------------------*/
00084 #if defined(USE_FULL_LL_DRIVER)
00085 /** @defgroup RTC_LL_Private_Macros RTC Private Macros
00086   * @{
00087   */
00088 /**
00089   * @}
00090   */
00091 #endif /*USE_FULL_LL_DRIVER*/
00092
00093 /* Exported types ------------------------------------------------------------*/
00094 #if defined(USE_FULL_LL_DRIVER)
00095 /** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
00096   * @{
00097   */
00098
00099 /**
00100   * @brief  RTC Init structures definition
00101   */
00102 typedef struct
00103 {
00104   uint32_t HourFormat;   /*!< Specifies the RTC Hours Format.
00105                               This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
00106
00107                               This feature can be modified afterwards using unitary function
00108                               @ref LL_RTC_SetHourFormat(). */
00109
00110   uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
00111                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
00112
00113                               This feature can be modified afterwards using unitary function
00114                               @ref LL_RTC_SetAsynchPrescaler(). */
00115
00116   uint32_t SynchPrescaler;  /*!< Specifies the RTC Synchronous Predivider value.
00117                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
00118
00119                               This feature can be modified afterwards using unitary function
00120                               @ref LL_RTC_SetSynchPrescaler(). */
00121 } LL_RTC_InitTypeDef;
00122
00123 /**
00124   * @brief  RTC Time structure definition
00125   */
00126 typedef struct
00127 {
00128   uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
00129                             This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
00130
00131                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */
00132
00133   uint8_t Hours;       /*!< Specifies the RTC Time Hours.
00134                             This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected.
00135                             This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
00136
00137                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */
00138
00139   uint8_t Minutes;     /*!< Specifies the RTC Time Minutes.
00140                             This parameter must be a number between Min_Data = 0 and Max_Data = 59
00141
00142                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */
00143
00144   uint8_t Seconds;     /*!< Specifies the RTC Time Seconds.
00145                             This parameter must be a number between Min_Data = 0 and Max_Data = 59
00146
00147                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */
00148 } LL_RTC_TimeTypeDef;
00149
00150 /**
00151   * @brief  RTC Date structure definition
00152   */
00153 typedef struct
00154 {
00155   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
00156                          This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
00157
00158                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */
00159
00160   uint8_t Month;    /*!< Specifies the RTC Date Month.
00161                          This parameter can be a value of @ref RTC_LL_EC_MONTH
00162
00163                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */
00164
00165   uint8_t Day;      /*!< Specifies the RTC Date Day.
00166                          This parameter must be a number between Min_Data = 1 and Max_Data = 31
00167
00168                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */
00169
00170   uint8_t Year;     /*!< Specifies the RTC Date Year.
00171                          This parameter must be a number between Min_Data = 0 and Max_Data = 99
00172
00173                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */
00174 } LL_RTC_DateTypeDef;
00175
00176 /**
00177   * @brief  RTC Alarm structure definition
00178   */
00179 typedef struct
00180 {
00181   LL_RTC_TimeTypeDef AlarmTime;  /*!< Specifies the RTC Alarm Time members. */
00182
00183   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
00184                                       This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
00185
00186                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A
00187                                       or @ref LL_RTC_ALMB_SetMask() for ALARM B
00188                                  */
00189
00190   uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on day or WeekDay.
00191                                       This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
00192
00193                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
00194                                       for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B
00195                                  */
00196
00197   uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Day/WeekDay.
00198                                       If AlarmDateWeekDaySel set to day, this parameter  must be a number between Min_Data = 1 and Max_Data = 31.
00199
00200                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()
00201                                       for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
00202
00203                                       If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.
00204
00205                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()
00206                                       for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
00207                                  */
00208 } LL_RTC_AlarmTypeDef;
00209
00210 /**
00211   * @}
00212   */
00213 #endif /* USE_FULL_LL_DRIVER */
00214
00215 /* Exported constants --------------------------------------------------------*/
00216 /** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
00217   * @{
00218   */
00219
00220 #if defined(USE_FULL_LL_DRIVER)
00221 /** @defgroup RTC_LL_EC_FORMAT FORMAT
00222   * @{
00223   */
00224 #define LL_RTC_FORMAT_BIN                  0x000000000U /*!< Binary data format */
00225 #define LL_RTC_FORMAT_BCD                  0x000000001U /*!< BCD data format */
00226 /**
00227   * @}
00228   */
00229
00230 /** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
00231   * @{
00232   */
00233 #define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm A Date is selected */
00234 #define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL        /*!< Alarm A WeekDay is selected */
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
00240   * @{
00241   */
00242 #define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm B Date is selected */
00243 #define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL        /*!< Alarm B WeekDay is selected */
00244 /**
00245   * @}
00246   */
00247
00248 #endif /* USE_FULL_LL_DRIVER */
00249
00250 /** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
00251   * @brief    Flags defines which can be used with LL_RTC_ReadReg function
00252   * @{
00253   */
00254 #define LL_RTC_ISR_RECALPF                 RTC_ISR_RECALPF
00255 #define LL_RTC_ISR_TAMP3F                  RTC_ISR_TAMP3F
00256 #define LL_RTC_ISR_TAMP2F                  RTC_ISR_TAMP2F
00257 #define LL_RTC_ISR_TAMP1F                  RTC_ISR_TAMP1F
00258 #define LL_RTC_ISR_TSOVF                   RTC_ISR_TSOVF
00259 #define LL_RTC_ISR_TSF                     RTC_ISR_TSF
00260 #define LL_RTC_ISR_WUTF                    RTC_ISR_WUTF
00261 #define LL_RTC_ISR_ALRBF                   RTC_ISR_ALRBF
00262 #define LL_RTC_ISR_ALRAF                   RTC_ISR_ALRAF
00263 #define LL_RTC_ISR_INITF                   RTC_ISR_INITF
00264 #define LL_RTC_ISR_RSF                     RTC_ISR_RSF
00265 #define LL_RTC_ISR_INITS                   RTC_ISR_INITS
00266 #define LL_RTC_ISR_SHPF                    RTC_ISR_SHPF
00267 #define LL_RTC_ISR_WUTWF                   RTC_ISR_WUTWF
00268 #define LL_RTC_ISR_ALRBWF                  RTC_ISR_ALRBWF
00269 #define LL_RTC_ISR_ALRAWF                  RTC_ISR_ALRAWF
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup RTC_LL_EC_IT IT Defines
00275   * @brief    IT defines which can be used with LL_RTC_ReadReg and  LL_RTC_WriteReg functions
00276   * @{
00277   */
00278 #define LL_RTC_CR_TSIE                     RTC_CR_TSIE
00279 #define LL_RTC_CR_WUTIE                    RTC_CR_WUTIE
00280 #define LL_RTC_CR_ALRBIE                   RTC_CR_ALRBIE
00281 #define LL_RTC_CR_ALRAIE                   RTC_CR_ALRAIE
00282 #define LL_RTC_TAFCR_TAMPIE               RTC_TAFCR_TAMPIE
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup RTC_LL_EC_WEEKDAY  WEEK DAY
00288   * @{
00289   */
00290 #define LL_RTC_WEEKDAY_MONDAY              ((uint8_t)0x01U) /*!< Monday    */
00291 #define LL_RTC_WEEKDAY_TUESDAY             ((uint8_t)0x02U) /*!< Tuesday   */
00292 #define LL_RTC_WEEKDAY_WEDNESDAY           ((uint8_t)0x03U) /*!< Wednesday */
00293 #define LL_RTC_WEEKDAY_THURSDAY            ((uint8_t)0x04U) /*!< Thrusday  */
00294 #define LL_RTC_WEEKDAY_FRIDAY              ((uint8_t)0x05U) /*!< Friday    */
00295 #define LL_RTC_WEEKDAY_SATURDAY            ((uint8_t)0x06U) /*!< Saturday  */
00296 #define LL_RTC_WEEKDAY_SUNDAY              ((uint8_t)0x07U) /*!< Sunday    */
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup RTC_LL_EC_MONTH  MONTH
00302   * @{
00303   */
00304 #define LL_RTC_MONTH_JANUARY               ((uint8_t)0x01U)  /*!< January   */
00305 #define LL_RTC_MONTH_FEBRUARY              ((uint8_t)0x02U)  /*!< February  */
00306 #define LL_RTC_MONTH_MARCH                 ((uint8_t)0x03U)  /*!< March     */
00307 #define LL_RTC_MONTH_APRIL                 ((uint8_t)0x04U)  /*!< April     */
00308 #define LL_RTC_MONTH_MAY                   ((uint8_t)0x05U)  /*!< May       */
00309 #define LL_RTC_MONTH_JUNE                  ((uint8_t)0x06U)  /*!< June      */
00310 #define LL_RTC_MONTH_JULY                  ((uint8_t)0x07U)  /*!< July      */
00311 #define LL_RTC_MONTH_AUGUST                ((uint8_t)0x08U)  /*!< August    */
00312 #define LL_RTC_MONTH_SEPTEMBER             ((uint8_t)0x09U)  /*!< September */
00313 #define LL_RTC_MONTH_OCTOBER               ((uint8_t)0x10U)  /*!< October   */
00314 #define LL_RTC_MONTH_NOVEMBER              ((uint8_t)0x11U)  /*!< November  */
00315 #define LL_RTC_MONTH_DECEMBER              ((uint8_t)0x12U)  /*!< December  */
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup RTC_LL_EC_HOURFORMAT  HOUR FORMAT
00321   * @{
00322   */
00323 #define LL_RTC_HOURFORMAT_24HOUR           0x00000000U           /*!< 24 hour/day format */
00324 #define LL_RTC_HOURFORMAT_AMPM             RTC_CR_FMT            /*!< AM/PM hour format */
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup RTC_LL_EC_ALARMOUT  ALARM OUTPUT
00330   * @{
00331   */
00332 #define LL_RTC_ALARMOUT_DISABLE            0x00000000U             /*!< Output disabled */
00333 #define LL_RTC_ALARMOUT_ALMA               RTC_CR_OSEL_0           /*!< Alarm A output enabled */
00334 #define LL_RTC_ALARMOUT_ALMB               RTC_CR_OSEL_1           /*!< Alarm B output enabled */
00335 #define LL_RTC_ALARMOUT_WAKEUP             RTC_CR_OSEL             /*!< Wakeup output enabled */
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE  ALARM OUTPUT TYPE
00341   * @{
00342   */
00343 #define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  0x00000000U                          /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
00344 #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   RTC_TAFCR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup RTC_LL_EC_PIN PIN
00350   * @{
00351   */
00352 #define LL_RTC_PIN_PC13                    RTC_TAFCR_PC13MODE    /*!< PC13 is forced to push-pull output if all RTC alternate functions are disabled */
00353 #define LL_RTC_PIN_PC14                    RTC_TAFCR_PC14MODE    /*!< PC14 is forced to push-pull output if LSE is disabled */
00354 #define LL_RTC_PIN_PC15                    RTC_TAFCR_PC15MODE    /*!< PC15 is forced to push-pull output if LSE is disabled */
00355 /**
00356   * @}
00357   */
00358
00359 /** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN  OUTPUT POLARITY PIN
00360   * @{
00361   */
00362 #define LL_RTC_OUTPUTPOLARITY_PIN_HIGH     0x00000000U           /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
00363 #define LL_RTC_OUTPUTPOLARITY_PIN_LOW      RTC_CR_POL            /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
00364 /**
00365   * @}
00366   */
00367
00368 /** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
00369   * @{
00370   */
00371 #define LL_RTC_TIME_FORMAT_AM_OR_24        0x00000000U           /*!< AM or 24-hour format */
00372 #define LL_RTC_TIME_FORMAT_PM              RTC_TR_PM             /*!< PM */
00373 /**
00374   * @}
00375   */
00376
00377 /** @defgroup RTC_LL_EC_SHIFT_SECOND  SHIFT SECOND
00378   * @{
00379   */
00380 #define LL_RTC_SHIFT_SECOND_DELAY          0x00000000U           /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
00381 #define LL_RTC_SHIFT_SECOND_ADVANCE        RTC_SHIFTR_ADD1S      /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
00382 /**
00383   * @}
00384   */
00385
00386 /** @defgroup RTC_LL_EC_ALMA_MASK  ALARMA MASK
00387   * @{
00388   */
00389 #define LL_RTC_ALMA_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm A*/
00390 #define LL_RTC_ALMA_MASK_DATEWEEKDAY       RTC_ALRMAR_MSK4         /*!< Date/day do not care in Alarm A comparison */
00391 #define LL_RTC_ALMA_MASK_HOURS             RTC_ALRMAR_MSK3         /*!< Hours do not care in Alarm A comparison */
00392 #define LL_RTC_ALMA_MASK_MINUTES           RTC_ALRMAR_MSK2         /*!< Minutes do not care in Alarm A comparison */
00393 #define LL_RTC_ALMA_MASK_SECONDS           RTC_ALRMAR_MSK1         /*!< Seconds do not care in Alarm A comparison */
00394 #define LL_RTC_ALMA_MASK_ALL               (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
00395 /**
00396   * @}
00397   */
00398
00399 /** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT  ALARMA TIME FORMAT
00400   * @{
00401   */
00402 #define LL_RTC_ALMA_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
00403 #define LL_RTC_ALMA_TIME_FORMAT_PM         RTC_ALRMAR_PM         /*!< PM */
00404 /**
00405   * @}
00406   */
00407
00408 /** @defgroup RTC_LL_EC_ALMB_MASK  ALARMB MASK
00409   * @{
00410   */
00411 #define LL_RTC_ALMB_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm B*/
00412 #define LL_RTC_ALMB_MASK_DATEWEEKDAY       RTC_ALRMBR_MSK4         /*!< Date/day do not care in Alarm B comparison */
00413 #define LL_RTC_ALMB_MASK_HOURS             RTC_ALRMBR_MSK3         /*!< Hours do not care in Alarm B comparison */
00414 #define LL_RTC_ALMB_MASK_MINUTES           RTC_ALRMBR_MSK2         /*!< Minutes do not care in Alarm B comparison */
00415 #define LL_RTC_ALMB_MASK_SECONDS           RTC_ALRMBR_MSK1         /*!< Seconds do not care in Alarm B comparison */
00416 #define LL_RTC_ALMB_MASK_ALL               (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
00417 /**
00418   * @}
00419   */
00420
00421 /** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT  ALARMB TIME FORMAT
00422   * @{
00423   */
00424 #define LL_RTC_ALMB_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
00425 #define LL_RTC_ALMB_TIME_FORMAT_PM         RTC_ALRMBR_PM         /*!< PM */
00426 /**
00427   * @}
00428   */
00429
00430 /** @defgroup RTC_LL_EC_TIMESTAMP_EDGE  TIMESTAMP EDGE
00431   * @{
00432   */
00433 #define LL_RTC_TIMESTAMP_EDGE_RISING       0x00000000U           /*!< RTC_TS input rising edge generates a time-stamp event */
00434 #define LL_RTC_TIMESTAMP_EDGE_FALLING      RTC_CR_TSEDGE         /*!< RTC_TS input falling edge generates a time-stamp even */
00435 /**
00436   * @}
00437   */
00438
00439 /** @defgroup RTC_LL_EC_TS_TIME_FORMAT  TIMESTAMP TIME FORMAT
00440   * @{
00441   */
00442 #define LL_RTC_TS_TIME_FORMAT_AM           0x00000000U           /*!< AM or 24-hour format */
00443 #define LL_RTC_TS_TIME_FORMAT_PM           RTC_TSTR_PM           /*!< PM */
00444 /**
00445   * @}
00446   */
00447
00448 /** @defgroup RTC_LL_EC_TAMPER  TAMPER
00449   * @{
00450   */
00451 #if defined(RTC_TAMPER1_SUPPORT)
00452 #define LL_RTC_TAMPER_1                    RTC_TAFCR_TAMP1E /*!< RTC_TAMP1 input detection */
00453 #endif /* RTC_TAMPER1_SUPPORT */
00454 #if defined(RTC_TAMPER2_SUPPORT)
00455 #define LL_RTC_TAMPER_2                    RTC_TAFCR_TAMP2E /*!< RTC_TAMP2 input detection */
00456 #endif /* RTC_TAMPER2_SUPPORT */
00457 #if defined(RTC_TAMPER3_SUPPORT)
00458 #define LL_RTC_TAMPER_3                    RTC_TAFCR_TAMP3E /*!< RTC_TAMP3 input detection */
00459 #endif /* RTC_TAMPER3_SUPPORT */
00460 /**
00461   * @}
00462   */
00463
00464 /** @defgroup RTC_LL_EC_TAMPER_MASK  TAMPER MASK
00465   * @{
00466   */
00467 #if defined(RTC_TAMPER1_SUPPORT)
00468 #define LL_RTC_TAMPER_MASK_TAMPER1         RTC_TAFCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
00469 #endif /* RTC_TAMPER1_SUPPORT */
00470 #if defined(RTC_TAMPER2_SUPPORT)
00471 #define LL_RTC_TAMPER_MASK_TAMPER2         RTC_TAFCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
00472 #endif /* RTC_TAMPER2_SUPPORT */
00473 #if defined(RTC_TAMPER3_SUPPORT)
00474 #define LL_RTC_TAMPER_MASK_TAMPER3         RTC_TAFCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */
00475 #endif /* RTC_TAMPER3_SUPPORT */
00476 /**
00477   * @}
00478   */
00479
00480 /** @defgroup RTC_LL_EC_TAMPER_NOERASE  TAMPER NO ERASE
00481   * @{
00482   */
00483 #if defined(RTC_TAMPER1_SUPPORT)
00484 #define LL_RTC_TAMPER_NOERASE_TAMPER1      RTC_TAFCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
00485 #endif /* RTC_TAMPER1_SUPPORT */
00486 #if defined(RTC_TAMPER2_SUPPORT)
00487 #define LL_RTC_TAMPER_NOERASE_TAMPER2      RTC_TAFCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
00488 #endif /* RTC_TAMPER2_SUPPORT */
00489 #if defined(RTC_TAMPER3_SUPPORT)
00490 #define LL_RTC_TAMPER_NOERASE_TAMPER3      RTC_TAFCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
00491 #endif /* RTC_TAMPER3_SUPPORT */
00492 /**
00493   * @}
00494   */
00495
00496 #if defined(RTC_TAFCR_TAMPPRCH)
00497 /** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION
00498   * @{
00499   */
00500 #define LL_RTC_TAMPER_DURATION_1RTCCLK     0x00000000U                             /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */
00501 #define LL_RTC_TAMPER_DURATION_2RTCCLK     RTC_TAFCR_TAMPPRCH_0  /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
00502 #define LL_RTC_TAMPER_DURATION_4RTCCLK     RTC_TAFCR_TAMPPRCH_1  /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
00503 #define LL_RTC_TAMPER_DURATION_8RTCCLK     RTC_TAFCR_TAMPPRCH    /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
00504 /**
00505   * @}
00506   */
00507 #endif /* RTC_TAFCR_TAMPPRCH */
00508
00509 #if defined(RTC_TAFCR_TAMPFLT)
00510 /** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER
00511   * @{
00512   */
00513 #define LL_RTC_TAMPER_FILTER_DISABLE       0x00000000U                              /*!< Tamper filter is disabled */
00514 #define LL_RTC_TAMPER_FILTER_2SAMPLE       RTC_TAFCR_TAMPFLT_0    /*!< Tamper is activated after 2 consecutive samples at the active level */
00515 #define LL_RTC_TAMPER_FILTER_4SAMPLE       RTC_TAFCR_TAMPFLT_1    /*!< Tamper is activated after 4 consecutive samples at the active level */
00516 #define LL_RTC_TAMPER_FILTER_8SAMPLE       RTC_TAFCR_TAMPFLT      /*!< Tamper is activated after 8 consecutive samples at the active level. */
00517 /**
00518   * @}
00519   */
00520 #endif /* RTC_TAFCR_TAMPFLT */
00521
00522 #if defined(RTC_TAFCR_TAMPFREQ)
00523 /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER
00524   * @{
00525   */
00526 #define LL_RTC_TAMPER_SAMPLFREQDIV_32768   0x00000000U                                                      /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
00527 #define LL_RTC_TAMPER_SAMPLFREQDIV_16384   RTC_TAFCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 16384 */
00528 #define LL_RTC_TAMPER_SAMPLFREQDIV_8192    RTC_TAFCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 8192 */
00529 #define LL_RTC_TAMPER_SAMPLFREQDIV_4096    (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 4096 */
00530 #define LL_RTC_TAMPER_SAMPLFREQDIV_2048    RTC_TAFCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 2048 */
00531 #define LL_RTC_TAMPER_SAMPLFREQDIV_1024    (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 1024 */
00532 #define LL_RTC_TAMPER_SAMPLFREQDIV_512     (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 512 */
00533 #define LL_RTC_TAMPER_SAMPLFREQDIV_256     RTC_TAFCR_TAMPFREQ                             /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 256 */
00534 /**
00535   * @}
00536   */
00537 #endif /* RTC_TAFCR_TAMPFREQ */
00538
00539 /** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL  TAMPER ACTIVE LEVEL
00540   * @{
00541   */
00542 #if defined(RTC_TAMPER1_SUPPORT)
00543 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1    RTC_TAFCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
00544 #endif /* RTC_TAMPER1_SUPPORT */
00545 #if defined(RTC_TAMPER2_SUPPORT)
00546 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2    RTC_TAFCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
00547 #endif /* RTC_TAMPER2_SUPPORT */
00548 #if defined(RTC_TAMPER3_SUPPORT)
00549 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3    RTC_TAFCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
00550 #endif /* RTC_TAMPER3_SUPPORT */
00551 /**
00552   * @}
00553   */
00554
00555 /** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV  WAKEUP CLOCK DIV
00556   * @{
00557   */
00558 #define LL_RTC_WAKEUPCLOCK_DIV_16          0x00000000U                           /*!< RTC/16 clock is selected */
00559 #define LL_RTC_WAKEUPCLOCK_DIV_8           (RTC_CR_WUCKSEL_0)                    /*!< RTC/8 clock is selected */
00560 #define LL_RTC_WAKEUPCLOCK_DIV_4           (RTC_CR_WUCKSEL_1)                    /*!< RTC/4 clock is selected */
00561 #define LL_RTC_WAKEUPCLOCK_DIV_2           (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
00562 #define LL_RTC_WAKEUPCLOCK_CKSPRE          (RTC_CR_WUCKSEL_2)                    /*!< ck_spre (usually 1 Hz) clock is selected */
00563 #define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT      (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
00564 /**
00565   * @}
00566   */
00567
00568 #if defined(RTC_BACKUP_SUPPORT)
00569 /** @defgroup RTC_LL_EC_BKP  BACKUP
00570   * @{
00571   */
00572 #define LL_RTC_BKP_DR0                     0x00000000U
00573 #define LL_RTC_BKP_DR1                     0x00000001U
00574 #define LL_RTC_BKP_DR2                     0x00000002U
00575 #define LL_RTC_BKP_DR3                     0x00000003U
00576 #define LL_RTC_BKP_DR4                     0x00000004U
00577 #if RTC_BKP_NUMBER > 5
00578 #define LL_RTC_BKP_DR5                     0x00000005U
00579 #define LL_RTC_BKP_DR6                     0x00000006U
00580 #define LL_RTC_BKP_DR7                     0x00000007U
00581 #define LL_RTC_BKP_DR8                     0x00000008U
00582 #define LL_RTC_BKP_DR9                     0x00000009U
00583 #define LL_RTC_BKP_DR10                    0x0000000AU
00584 #define LL_RTC_BKP_DR11                    0x0000000BU
00585 #define LL_RTC_BKP_DR12                    0x0000000CU
00586 #define LL_RTC_BKP_DR13                    0x0000000DU
00587 #define LL_RTC_BKP_DR14                    0x0000000EU
00588 #define LL_RTC_BKP_DR15                    0x0000000FU
00589 #endif /* RTC_BKP_NUMBER > 5 */
00590
00591 #if RTC_BKP_NUMBER > 16
00592 #define LL_RTC_BKP_DR16                    0x00000010U
00593 #define LL_RTC_BKP_DR17                    0x00000011U
00594 #define LL_RTC_BKP_DR18                    0x00000012U
00595 #define LL_RTC_BKP_DR19                    0x00000013U
00596 #endif /* RTC_BKP_NUMBER > 16 */
00597
00598 #if RTC_BKP_NUMBER > 20
00599 #define LL_RTC_BKP_DR20                    0x00000014U
00600 #define LL_RTC_BKP_DR21                    0x00000015U
00601 #define LL_RTC_BKP_DR22                    0x00000016U
00602 #define LL_RTC_BKP_DR23                    0x00000017U
00603 #define LL_RTC_BKP_DR24                    0x00000018U
00604 #define LL_RTC_BKP_DR25                    0x00000019U
00605 #define LL_RTC_BKP_DR26                    0x0000001AU
00606 #define LL_RTC_BKP_DR27                    0x0000001BU
00607 #define LL_RTC_BKP_DR28                    0x0000001CU
00608 #define LL_RTC_BKP_DR29                    0x0000001DU
00609 #define LL_RTC_BKP_DR30                    0x0000001EU
00610 #define LL_RTC_BKP_DR31                    0x0000001FU
00611 #endif /* RTC_BKP_NUMBER > 20 */
00612 /**
00613   * @}
00614   */
00615 #endif /* RTC_BACKUP_SUPPORT */
00616
00617 /** @defgroup RTC_LL_EC_CALIB_OUTPUT  Calibration output
00618   * @{
00619   */
00620 #define LL_RTC_CALIB_OUTPUT_NONE           0x00000000U                 /*!< Calibration output disabled */
00621 #define LL_RTC_CALIB_OUTPUT_1HZ            (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */
00622 #define LL_RTC_CALIB_OUTPUT_512HZ          (RTC_CR_COE)                /*!< Calibration output is 512 Hz */
00623 /**
00624   * @}
00625   */
00626
00627 /** @defgroup RTC_LL_EC_CALIB_INSERTPULSE  Calibration pulse insertion
00628   * @{
00629   */
00630 #define LL_RTC_CALIB_INSERTPULSE_NONE      0x00000000U           /*!< No RTCCLK pulses are added */
00631 #define LL_RTC_CALIB_INSERTPULSE_SET       RTC_CALR_CALP         /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
00632 /**
00633   * @}
00634   */
00635
00636 /** @defgroup RTC_LL_EC_CALIB_PERIOD  Calibration period
00637   * @{
00638   */
00639 #define LL_RTC_CALIB_PERIOD_32SEC          0x00000000U           /*!< Use a 32-second calibration cycle period */
00640 #define LL_RTC_CALIB_PERIOD_16SEC          RTC_CALR_CALW16       /*!< Use a 16-second calibration cycle period */
00641 #define LL_RTC_CALIB_PERIOD_8SEC           RTC_CALR_CALW8        /*!< Use a 8-second calibration cycle period */
00642 /**
00643   * @}
00644   */
00645
00646 /**
00647   * @}
00648   */
00649
00650 /* Exported macro ------------------------------------------------------------*/
00651 /** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
00652   * @{
00653   */
00654
00655 /** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
00656   * @{
00657   */
00658
00659 /**
00660   * @brief  Write a value in RTC register
00661   * @param  __INSTANCE__ RTC Instance
00662   * @param  __REG__ Register to be written
00663   * @param  __VALUE__ Value to be written in the register
00664   * @retval None
00665   */
00666 #define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00667
00668 /**
00669   * @brief  Read a value in RTC register
00670   * @param  __INSTANCE__ RTC Instance
00671   * @param  __REG__ Register to be read
00672   * @retval Register value
00673   */
00674 #define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00675 /**
00676   * @}
00677   */
00678
00679 /** @defgroup RTC_LL_EM_Convert Convert helper Macros
00680   * @{
00681   */
00682
00683 /**
00684   * @brief  Helper macro to convert a value from 2 digit decimal format to BCD format
00685   * @param  __VALUE__ Byte to be converted
00686   * @retval Converted byte
00687   */
00688 #define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
00689
00690 /**
00691   * @brief  Helper macro to convert a value from BCD format to 2 digit decimal format
00692   * @param  __VALUE__ BCD value to be converted
00693   * @retval Converted byte
00694   */
00695 #define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))
00696
00697 /**
00698   * @}
00699   */
00700
00701 /** @defgroup RTC_LL_EM_Date Date helper Macros
00702   * @{
00703   */
00704
00705 /**
00706   * @brief  Helper macro to retrieve weekday.
00707   * @param  __RTC_DATE__ Date returned by @ref  LL_RTC_DATE_Get function.
00708   * @retval Returned value can be one of the following values:
00709   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
00710   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
00711   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
00712   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
00713   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
00714   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
00715   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
00716   */
00717 #define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
00718
00719 /**
00720   * @brief  Helper macro to retrieve Year in BCD format
00721   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00722   * @retval Year in BCD format (0x00 . . . 0x99)
00723   */
00724 #define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
00725
00726 /**
00727   * @brief  Helper macro to retrieve Month in BCD format
00728   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00729   * @retval Returned value can be one of the following values:
00730   *         @arg @ref LL_RTC_MONTH_JANUARY
00731   *         @arg @ref LL_RTC_MONTH_FEBRUARY
00732   *         @arg @ref LL_RTC_MONTH_MARCH
00733   *         @arg @ref LL_RTC_MONTH_APRIL
00734   *         @arg @ref LL_RTC_MONTH_MAY
00735   *         @arg @ref LL_RTC_MONTH_JUNE
00736   *         @arg @ref LL_RTC_MONTH_JULY
00737   *         @arg @ref LL_RTC_MONTH_AUGUST
00738   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
00739   *         @arg @ref LL_RTC_MONTH_OCTOBER
00740   *         @arg @ref LL_RTC_MONTH_NOVEMBER
00741   *         @arg @ref LL_RTC_MONTH_DECEMBER
00742   */
00743 #define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
00744
00745 /**
00746   * @brief  Helper macro to retrieve Day in BCD format
00747   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00748   * @retval Day in BCD format (0x01 . . . 0x31)
00749   */
00750 #define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
00751
00752 /**
00753   * @}
00754   */
00755
00756 /** @defgroup RTC_LL_EM_Time Time helper Macros
00757   * @{
00758   */
00759
00760 /**
00761   * @brief  Helper macro to retrieve hour in BCD format
00762   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00763   * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
00764   */
00765 #define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
00766
00767 /**
00768   * @brief  Helper macro to retrieve minute in BCD format
00769   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00770   * @retval Minutes in BCD format (0x00. . .0x59)
00771   */
00772 #define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
00773
00774 /**
00775   * @brief  Helper macro to retrieve second in BCD format
00776   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00777   * @retval Seconds in  format (0x00. . .0x59)
00778   */
00779 #define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
00780
00781 /**
00782   * @}
00783   */
00784
00785 /**
00786   * @}
00787   */
00788
00789 /* Exported functions --------------------------------------------------------*/
00790 /** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
00791   * @{
00792   */
00793
00794 /** @defgroup RTC_LL_EF_Configuration Configuration
00795   * @{
00796   */
00797
00798 /**
00799   * @brief  Set Hours format (24 hour/day or AM/PM hour format)
00800   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00801   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
00802   * @rmtoll CR           FMT           LL_RTC_SetHourFormat
00803   * @param  RTCx RTC Instance
00804   * @param  HourFormat This parameter can be one of the following values:
00805   *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
00806   *         @arg @ref LL_RTC_HOURFORMAT_AMPM
00807   * @retval None
00808   */
00809 __STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
00810 {
00811   MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
00812 }
00813
00814 /**
00815   * @brief  Get Hours format (24 hour/day or AM/PM hour format)
00816   * @rmtoll CR           FMT           LL_RTC_GetHourFormat
00817   * @param  RTCx RTC Instance
00818   * @retval Returned value can be one of the following values:
00819   *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
00820   *         @arg @ref LL_RTC_HOURFORMAT_AMPM
00821   */
00822 __STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
00823 {
00824   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
00825 }
00826
00827 /**
00828   * @brief  Select the flag to be routed to RTC_ALARM output
00829   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00830   * @rmtoll CR           OSEL          LL_RTC_SetAlarmOutEvent
00831   * @param  RTCx RTC Instance
00832   * @param  AlarmOutput This parameter can be one of the following values:
00833   *         @arg @ref LL_RTC_ALARMOUT_DISABLE
00834   *         @arg @ref LL_RTC_ALARMOUT_ALMA
00835   *         @arg @ref LL_RTC_ALARMOUT_ALMB
00836   *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
00837   * @retval None
00838   */
00839 __STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
00840 {
00841   MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
00842 }
00843
00844 /**
00845   * @brief  Get the flag to be routed to RTC_ALARM output
00846   * @rmtoll CR           OSEL          LL_RTC_GetAlarmOutEvent
00847   * @param  RTCx RTC Instance
00848   * @retval Returned value can be one of the following values:
00849   *         @arg @ref LL_RTC_ALARMOUT_DISABLE
00850   *         @arg @ref LL_RTC_ALARMOUT_ALMA
00851   *         @arg @ref LL_RTC_ALARMOUT_ALMB
00852   *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
00853   */
00854 __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
00855 {
00856   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
00857 }
00858
00859 /**
00860   * @brief  Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
00861   * @note   Used only when RTC_ALARM is mapped on PC13
00862   * @note   If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the
00863   *         PC13 output data
00864   * @rmtoll TAFCR        ALARMOUTTYPE  LL_RTC_SetAlarmOutputType
00865   * @param  RTCx RTC Instance
00866   * @param  Output This parameter can be one of the following values:
00867   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
00868   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
00869   * @retval None
00870   */
00871 __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
00872 {
00873   MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_ALARMOUTTYPE, Output);
00874 }
00875
00876 /**
00877   * @brief  Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
00878   * @note   used only when RTC_ALARM is mapped on PC13
00879   * @note   If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the
00880   *         PC13 output data
00881   * @rmtoll TAFCR        ALARMOUTTYPE  LL_RTC_GetAlarmOutputType
00882   * @param  RTCx RTC Instance
00883   * @retval Returned value can be one of the following values:
00884   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
00885   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
00886   */
00887 __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
00888 {
00889   return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_ALARMOUTTYPE));
00890 }
00891
00892 /**
00893   * @brief  Enable push-pull output on PC13, PC14 and/or PC15
00894   * @note   PC13 forced to push-pull output if all RTC alternate functions are disabled
00895   * @note   PC14 and PC15 forced to push-pull output if LSE is disabled
00896   * @rmtoll TAFCR        PC13MODE  LL_RTC_EnablePushPullMode\n
00897   * @rmtoll TAFCR        PC14MODE  LL_RTC_EnablePushPullMode\n
00898   * @rmtoll TAFCR        PC15MODE  LL_RTC_EnablePushPullMode
00899   * @param  RTCx RTC Instance
00900   * @param  PinMask This parameter can be a combination of the following values:
00901   *         @arg @ref LL_RTC_PIN_PC13
00902   *         @arg @ref LL_RTC_PIN_PC14
00903   *         @arg @ref LL_RTC_PIN_PC15
00904   * @retval None
00905   */
00906 __STATIC_INLINE void LL_RTC_EnablePushPullMode(RTC_TypeDef *RTCx, uint32_t PinMask)
00907 {
00908   SET_BIT(RTCx->TAFCR, PinMask);
00909 }
00910
00911 /**
00912   * @brief  Disable push-pull output on PC13, PC14 and/or PC15
00913   * @note   PC13, PC14 and/or PC15 are controlled by the GPIO configuration registers.
00914   *         Consequently PC13, PC14 and/or PC15 are floating in Standby mode.
00915   * @rmtoll TAFCR        PC13MODE      LL_RTC_DisablePushPullMode\n
00916   *         TAFCR        PC14MODE      LL_RTC_DisablePushPullMode\n
00917   *         TAFCR        PC15MODE      LL_RTC_DisablePushPullMode
00918   * @param  RTCx RTC Instance
00919   * @param  PinMask This parameter can be a combination of the following values:
00920   *         @arg @ref LL_RTC_PIN_PC13
00921   *         @arg @ref LL_RTC_PIN_PC14
00922   *         @arg @ref LL_RTC_PIN_PC15
00923   * @retval None
00924   */
00925 __STATIC_INLINE void LL_RTC_DisablePushPullMode(RTC_TypeDef* RTCx, uint32_t PinMask)
00926 {
00927   CLEAR_BIT(RTCx->TAFCR, PinMask);
00928 }
00929
00930 /**
00931   * @brief  Set PC14 and/or PC15 to high level.
00932   * @note   Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode)
00933   * @rmtoll TAFCR        PC14VALUE     LL_RTC_SetOutputPin\n
00934   *         TAFCR        PC15VALUE     LL_RTC_SetOutputPin
00935   * @param  RTCx RTC Instance
00936   * @param  PinMask This parameter can be a combination of the following values:
00937   *         @arg @ref LL_RTC_PIN_PC14
00938   *         @arg @ref LL_RTC_PIN_PC15
00939   * @retval None
00940   */
00941 __STATIC_INLINE void LL_RTC_SetOutputPin(RTC_TypeDef* RTCx, uint32_t PinMask)
00942 {
00943   SET_BIT(RTCx->TAFCR, (PinMask >> 1));
00944 }
00945
00946 /**
00947   * @brief  Set PC14 and/or PC15 to low level.
00948   * @note   Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode)
00949   * @rmtoll TAFCR        PC14VALUE     LL_RTC_ResetOutputPin\n
00950   *         TAFCR        PC15VALUE     LL_RTC_ResetOutputPin
00951   * @param  RTCx RTC Instance
00952   * @param  PinMask This parameter can be a combination of the following values:
00953   *         @arg @ref LL_RTC_PIN_PC14
00954   *         @arg @ref LL_RTC_PIN_PC15
00955   * @retval None
00956   */
00957 __STATIC_INLINE void LL_RTC_ResetOutputPin(RTC_TypeDef* RTCx, uint32_t PinMask)
00958 {
00959   CLEAR_BIT(RTCx->TAFCR, (PinMask >> 1));
00960 }
00961
00962 /**
00963   * @brief  Enable initialization mode
00964   * @note   Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
00965   *         and prescaler register (RTC_PRER).
00966   *         Counters are stopped and start counting from the new value when INIT is reset.
00967   * @rmtoll ISR          INIT          LL_RTC_EnableInitMode
00968   * @param  RTCx RTC Instance
00969   * @retval None
00970   */
00971 __STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
00972 {
00973   /* Set the Initialization mode */
00974   WRITE_REG(RTCx->ISR, RTC_INIT_MASK);
00975 }
00976
00977 /**
00978   * @brief  Disable initialization mode (Free running mode)
00979   * @rmtoll ISR          INIT          LL_RTC_DisableInitMode
00980   * @param  RTCx RTC Instance
00981   * @retval None
00982   */
00983 __STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
00984 {
00985   /* Exit Initialization mode */
00986   WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT);
00987 }
00988
00989 /**
00990   * @brief  Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
00991   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00992   * @rmtoll CR           POL           LL_RTC_SetOutputPolarity
00993   * @param  RTCx RTC Instance
00994   * @param  Polarity This parameter can be one of the following values:
00995   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
00996   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
00997   * @retval None
00998   */
00999 __STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
01000 {
01001   MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
01002 }
01003
01004 /**
01005   * @brief  Get Output polarity
01006   * @rmtoll CR           POL           LL_RTC_GetOutputPolarity
01007   * @param  RTCx RTC Instance
01008   * @retval Returned value can be one of the following values:
01009   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
01010   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
01011   */
01012 __STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
01013 {
01014   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
01015 }
01016
01017 /**
01018   * @brief  Enable Bypass the shadow registers
01019   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01020   * @rmtoll CR           BYPSHAD       LL_RTC_EnableShadowRegBypass
01021   * @param  RTCx RTC Instance
01022   * @retval None
01023   */
01024 __STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
01025 {
01026   SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
01027 }
01028
01029 /**
01030   * @brief  Disable Bypass the shadow registers
01031   * @rmtoll CR           BYPSHAD       LL_RTC_DisableShadowRegBypass
01032   * @param  RTCx RTC Instance
01033   * @retval None
01034   */
01035 __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
01036 {
01037   CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
01038 }
01039
01040 /**
01041   * @brief  Check if Shadow registers bypass is enabled or not.
01042   * @rmtoll CR           BYPSHAD       LL_RTC_IsShadowRegBypassEnabled
01043   * @param  RTCx RTC Instance
01044   * @retval State of bit (1 or 0).
01045   */
01046 __STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
01047 {
01048   return (READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD));
01049 }
01050
01051 /**
01052   * @brief  Enable RTC_REFIN reference clock detection (50 or 60 Hz)
01053   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01054   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01055   * @rmtoll CR           REFCKON       LL_RTC_EnableRefClock
01056   * @param  RTCx RTC Instance
01057   * @retval None
01058   */
01059 __STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
01060 {
01061   SET_BIT(RTCx->CR, RTC_CR_REFCKON);
01062 }
01063
01064 /**
01065   * @brief  Disable RTC_REFIN reference clock detection (50 or 60 Hz)
01066   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01067   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01068   * @rmtoll CR           REFCKON       LL_RTC_DisableRefClock
01069   * @param  RTCx RTC Instance
01070   * @retval None
01071   */
01072 __STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
01073 {
01074   CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
01075 }
01076
01077 /**
01078   * @brief  Set Asynchronous prescaler factor
01079   * @rmtoll PRER         PREDIV_A      LL_RTC_SetAsynchPrescaler
01080   * @param  RTCx RTC Instance
01081   * @param  AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
01082   * @retval None
01083   */
01084 __STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
01085 {
01086   MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
01087 }
01088
01089 /**
01090   * @brief  Set Synchronous prescaler factor
01091   * @rmtoll PRER         PREDIV_S      LL_RTC_SetSynchPrescaler
01092   * @param  RTCx RTC Instance
01093   * @param  SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
01094   * @retval None
01095   */
01096 __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
01097 {
01098   MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
01099 }
01100
01101 /**
01102   * @brief  Get Asynchronous prescaler factor
01103   * @rmtoll PRER         PREDIV_A      LL_RTC_GetAsynchPrescaler
01104   * @param  RTCx RTC Instance
01105   * @retval Value between Min_Data = 0 and Max_Data = 0x7F
01106   */
01107 __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
01108 {
01109   return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
01110 }
01111
01112 /**
01113   * @brief  Get Synchronous prescaler factor
01114   * @rmtoll PRER         PREDIV_S      LL_RTC_GetSynchPrescaler
01115   * @param  RTCx RTC Instance
01116   * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
01117   */
01118 __STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
01119 {
01120   return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
01121 }
01122
01123 /**
01124   * @brief  Enable the write protection for RTC registers.
01125   * @rmtoll WPR          KEY           LL_RTC_EnableWriteProtection
01126   * @param  RTCx RTC Instance
01127   * @retval None
01128   */
01129 __STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
01130 {
01131   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
01132 }
01133
01134 /**
01135   * @brief  Disable the write protection for RTC registers.
01136   * @rmtoll WPR          KEY           LL_RTC_DisableWriteProtection
01137   * @param  RTCx RTC Instance
01138   * @retval None
01139   */
01140 __STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
01141 {
01142   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
01143   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
01144 }
01145
01146 /**
01147   * @}
01148   */
01149
01150 /** @defgroup RTC_LL_EF_Time Time
01151   * @{
01152   */
01153
01154 /**
01155   * @brief  Set time format (AM/24-hour or PM notation)
01156   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01157   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01158   * @rmtoll TR           PM            LL_RTC_TIME_SetFormat
01159   * @param  RTCx RTC Instance
01160   * @param  TimeFormat This parameter can be one of the following values:
01161   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01162   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01163   * @retval None
01164   */
01165 __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
01166 {
01167   MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
01168 }
01169
01170 /**
01171   * @brief  Get time format (AM or PM notation)
01172   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01173   *       before reading this bit
01174   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01175   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01176   * @rmtoll TR           PM            LL_RTC_TIME_GetFormat
01177   * @param  RTCx RTC Instance
01178   * @retval Returned value can be one of the following values:
01179   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01180   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01181   */
01182 __STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
01183 {
01184   return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
01185 }
01186
01187 /**
01188   * @brief  Set Hours in BCD format
01189   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01190   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01191   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
01192   * @rmtoll TR           HT            LL_RTC_TIME_SetHour\n
01193   *         TR           HU            LL_RTC_TIME_SetHour
01194   * @param  RTCx RTC Instance
01195   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01196   * @retval None
01197   */
01198 __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
01199 {
01200   MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
01201              (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
01202 }
01203
01204 /**
01205   * @brief  Get Hours in BCD format
01206   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01207   *       before reading this bit
01208   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01209   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01210   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
01211   *       Binary format
01212   * @rmtoll TR           HT            LL_RTC_TIME_GetHour\n
01213   *         TR           HU            LL_RTC_TIME_GetHour
01214   * @param  RTCx RTC Instance
01215   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01216   */
01217 __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
01218 {
01219   register uint32_t temp = 0U;
01220
01221   temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU));
01222   return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos));
01223 }
01224
01225 /**
01226   * @brief  Set Minutes in BCD format
01227   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01228   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01229   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
01230   * @rmtoll TR           MNT           LL_RTC_TIME_SetMinute\n
01231   *         TR           MNU           LL_RTC_TIME_SetMinute
01232   * @param  RTCx RTC Instance
01233   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01234   * @retval None
01235   */
01236 __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
01237 {
01238   MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
01239              (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
01240 }
01241
01242 /**
01243   * @brief  Get Minutes in BCD format
01244   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01245   *       before reading this bit
01246   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01247   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01248   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
01249   *       to Binary format
01250   * @rmtoll TR           MNT           LL_RTC_TIME_GetMinute\n
01251   *         TR           MNU           LL_RTC_TIME_GetMinute
01252   * @param  RTCx RTC Instance
01253   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01254   */
01255 __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
01256 {
01257   register uint32_t temp = 0U;
01258
01259   temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU));
01260   return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos));
01261 }
01262
01263 /**
01264   * @brief  Set Seconds in BCD format
01265   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01266   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01267   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
01268   * @rmtoll TR           ST            LL_RTC_TIME_SetSecond\n
01269   *         TR           SU            LL_RTC_TIME_SetSecond
01270   * @param  RTCx RTC Instance
01271   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01272   * @retval None
01273   */
01274 __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
01275 {
01276   MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
01277              (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
01278 }
01279
01280 /**
01281   * @brief  Get Seconds in BCD format
01282   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01283   *       before reading this bit
01284   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01285   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01286   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
01287   *       to Binary format
01288   * @rmtoll TR           ST            LL_RTC_TIME_GetSecond\n
01289   *         TR           SU            LL_RTC_TIME_GetSecond
01290   * @param  RTCx RTC Instance
01291   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01292   */
01293 __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
01294 {
01295   register uint32_t temp = 0U;
01296
01297   temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU));
01298   return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos));
01299 }
01300
01301 /**
01302   * @brief  Set time (hour, minute and second) in BCD format
01303   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01304   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01305   * @note TimeFormat and Hours should follow the same format
01306   * @rmtoll TR           PM            LL_RTC_TIME_Config\n
01307   *         TR           HT            LL_RTC_TIME_Config\n
01308   *         TR           HU            LL_RTC_TIME_Config\n
01309   *         TR           MNT           LL_RTC_TIME_Config\n
01310   *         TR           MNU           LL_RTC_TIME_Config\n
01311   *         TR           ST            LL_RTC_TIME_Config\n
01312   *         TR           SU            LL_RTC_TIME_Config
01313   * @param  RTCx RTC Instance
01314   * @param  Format12_24 This parameter can be one of the following values:
01315   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01316   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01317   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01318   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01319   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01320   * @retval None
01321   */
01322 __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
01323 {
01324   register uint32_t temp = 0U;
01325
01326   temp = Format12_24                                                                                    | \
01327          (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))     | \
01328          (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
01329          (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
01330   MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
01331 }
01332
01333 /**
01334   * @brief  Get time (hour, minute and second) in BCD format
01335   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01336   *       before reading this bit
01337   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01338   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01339   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
01340   *       are available to get independently each parameter.
01341   * @rmtoll TR           HT            LL_RTC_TIME_Get\n
01342   *         TR           HU            LL_RTC_TIME_Get\n
01343   *         TR           MNT           LL_RTC_TIME_Get\n
01344   *         TR           MNU           LL_RTC_TIME_Get\n
01345   *         TR           ST            LL_RTC_TIME_Get\n
01346   *         TR           SU            LL_RTC_TIME_Get
01347   * @param  RTCx RTC Instance
01348   * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
01349   */
01350 __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
01351 {
01352   register uint32_t temp = 0U;
01353
01354   temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
01355   return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) |  \
01356                     (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
01357                     ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
01358 }
01359
01360 /**
01361   * @brief  Memorize whether the daylight saving time change has been performed
01362   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01363   * @rmtoll CR           BKP           LL_RTC_TIME_EnableDayLightStore
01364   * @param  RTCx RTC Instance
01365   * @retval None
01366   */
01367 __STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
01368 {
01369   SET_BIT(RTCx->CR, RTC_CR_BKP);
01370 }
01371
01372 /**
01373   * @brief  Disable memorization whether the daylight saving time change has been performed.
01374   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01375   * @rmtoll CR           BKP           LL_RTC_TIME_DisableDayLightStore
01376   * @param  RTCx RTC Instance
01377   * @retval None
01378   */
01379 __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
01380 {
01381   CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
01382 }
01383
01384 /**
01385   * @brief  Check if RTC Day Light Saving stored operation has been enabled or not
01386   * @rmtoll CR           BKP           LL_RTC_TIME_IsDayLightStoreEnabled
01387   * @param  RTCx RTC Instance
01388   * @retval State of bit (1 or 0).
01389   */
01390 __STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
01391 {
01392   return (READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP));
01393 }
01394
01395 /**
01396   * @brief  Subtract 1 hour (winter time change)
01397   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01398   * @rmtoll CR           SUB1H         LL_RTC_TIME_DecHour
01399   * @param  RTCx RTC Instance
01400   * @retval None
01401   */
01402 __STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
01403 {
01404   SET_BIT(RTCx->CR, RTC_CR_SUB1H);
01405 }
01406
01407 /**
01408   * @brief  Add 1 hour (summer time change)
01409   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01410   * @rmtoll CR           ADD1H         LL_RTC_TIME_IncHour
01411   * @param  RTCx RTC Instance
01412   * @retval None
01413   */
01414 __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
01415 {
01416   SET_BIT(RTCx->CR, RTC_CR_ADD1H);
01417 }
01418
01419 /**
01420   * @brief  Get Sub second value in the synchronous prescaler counter.
01421   * @note  You can use both SubSeconds value and SecondFraction (PREDIV_S through
01422   *        LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
01423   *        SubSeconds value in second fraction ratio with time unit following
01424   *        generic formula:
01425   *          ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
01426   *        This conversion can be performed only if no shift operation is pending
01427   *        (ie. SHFP=0) when PREDIV_S >= SS.
01428   * @rmtoll SSR          SS            LL_RTC_TIME_GetSubSecond
01429   * @param  RTCx RTC Instance
01430   * @retval Sub second value (number between 0 and 65535)
01431   */
01432 __STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
01433 {
01434   return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
01435 }
01436
01437 /**
01438   * @brief  Synchronize to a remote clock with a high degree of precision.
01439   * @note   This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
01440   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01441   * @note   When REFCKON is set, firmware must not write to Shift control register.
01442   * @rmtoll SHIFTR       ADD1S         LL_RTC_TIME_Synchronize\n
01443   *         SHIFTR       SUBFS         LL_RTC_TIME_Synchronize
01444   * @param  RTCx RTC Instance
01445   * @param  ShiftSecond This parameter can be one of the following values:
01446   *         @arg @ref LL_RTC_SHIFT_SECOND_DELAY
01447   *         @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
01448   * @param  Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
01449   * @retval None
01450   */
01451 __STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
01452 {
01453   WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);
01454 }
01455
01456 /**
01457   * @}
01458   */
01459
01460 /** @defgroup RTC_LL_EF_Date Date
01461   * @{
01462   */
01463
01464 /**
01465   * @brief  Set Year in BCD format
01466   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
01467   * @rmtoll DR           YT            LL_RTC_DATE_SetYear\n
01468   *         DR           YU            LL_RTC_DATE_SetYear
01469   * @param  RTCx RTC Instance
01470   * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
01471   * @retval None
01472   */
01473 __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
01474 {
01475   MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
01476              (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
01477 }
01478
01479 /**
01480   * @brief  Get Year in BCD format
01481   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01482   *       before reading this bit
01483   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
01484   * @rmtoll DR           YT            LL_RTC_DATE_GetYear\n
01485   *         DR           YU            LL_RTC_DATE_GetYear
01486   * @param  RTCx RTC Instance
01487   * @retval Value between Min_Data=0x00 and Max_Data=0x99
01488   */
01489 __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
01490 {
01491   register uint32_t temp = 0U;
01492
01493   temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU));
01494   return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos));
01495 }
01496
01497 /**
01498   * @brief  Set Week day
01499   * @rmtoll DR           WDU           LL_RTC_DATE_SetWeekDay
01500   * @param  RTCx RTC Instance
01501   * @param  WeekDay This parameter can be one of the following values:
01502   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01503   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01504   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01505   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01506   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01507   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01508   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01509   * @retval None
01510   */
01511 __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
01512 {
01513   MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
01514 }
01515
01516 /**
01517   * @brief  Get Week day
01518   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01519   *       before reading this bit
01520   * @rmtoll DR           WDU           LL_RTC_DATE_GetWeekDay
01521   * @param  RTCx RTC Instance
01522   * @retval Returned value can be one of the following values:
01523   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01524   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01525   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01526   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01527   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01528   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01529   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01530   */
01531 __STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
01532 {
01533   return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
01534 }
01535
01536 /**
01537   * @brief  Set Month in BCD format
01538   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
01539   * @rmtoll DR           MT            LL_RTC_DATE_SetMonth\n
01540   *         DR           MU            LL_RTC_DATE_SetMonth
01541   * @param  RTCx RTC Instance
01542   * @param  Month This parameter can be one of the following values:
01543   *         @arg @ref LL_RTC_MONTH_JANUARY
01544   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01545   *         @arg @ref LL_RTC_MONTH_MARCH
01546   *         @arg @ref LL_RTC_MONTH_APRIL
01547   *         @arg @ref LL_RTC_MONTH_MAY
01548   *         @arg @ref LL_RTC_MONTH_JUNE
01549   *         @arg @ref LL_RTC_MONTH_JULY
01550   *         @arg @ref LL_RTC_MONTH_AUGUST
01551   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01552   *         @arg @ref LL_RTC_MONTH_OCTOBER
01553   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01554   *         @arg @ref LL_RTC_MONTH_DECEMBER
01555   * @retval None
01556   */
01557 __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
01558 {
01559   MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
01560              (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
01561 }
01562
01563 /**
01564   * @brief  Get Month in BCD format
01565   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01566   *       before reading this bit
01567   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
01568   * @rmtoll DR           MT            LL_RTC_DATE_GetMonth\n
01569   *         DR           MU            LL_RTC_DATE_GetMonth
01570   * @param  RTCx RTC Instance
01571   * @retval Returned value can be one of the following values:
01572   *         @arg @ref LL_RTC_MONTH_JANUARY
01573   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01574   *         @arg @ref LL_RTC_MONTH_MARCH
01575   *         @arg @ref LL_RTC_MONTH_APRIL
01576   *         @arg @ref LL_RTC_MONTH_MAY
01577   *         @arg @ref LL_RTC_MONTH_JUNE
01578   *         @arg @ref LL_RTC_MONTH_JULY
01579   *         @arg @ref LL_RTC_MONTH_AUGUST
01580   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01581   *         @arg @ref LL_RTC_MONTH_OCTOBER
01582   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01583   *         @arg @ref LL_RTC_MONTH_DECEMBER
01584   */
01585 __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
01586 {
01587   register uint32_t temp = 0U;
01588
01589   temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU));
01590   return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos));
01591 }
01592
01593 /**
01594   * @brief  Set Day in BCD format
01595   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
01596   * @rmtoll DR           DT            LL_RTC_DATE_SetDay\n
01597   *         DR           DU            LL_RTC_DATE_SetDay
01598   * @param  RTCx RTC Instance
01599   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
01600   * @retval None
01601   */
01602 __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
01603 {
01604   MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
01605              (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
01606 }
01607
01608 /**
01609   * @brief  Get Day in BCD format
01610   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01611   *       before reading this bit
01612   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
01613   * @rmtoll DR           DT            LL_RTC_DATE_GetDay\n
01614   *         DR           DU            LL_RTC_DATE_GetDay
01615   * @param  RTCx RTC Instance
01616   * @retval Value between Min_Data=0x01 and Max_Data=0x31
01617   */
01618 __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
01619 {
01620   register uint32_t temp = 0U;
01621
01622   temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU));
01623   return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos));
01624 }
01625
01626 /**
01627   * @brief  Set date (WeekDay, Day, Month and Year) in BCD format
01628   * @rmtoll DR           WDU           LL_RTC_DATE_Config\n
01629   *         DR           MT            LL_RTC_DATE_Config\n
01630   *         DR           MU            LL_RTC_DATE_Config\n
01631   *         DR           DT            LL_RTC_DATE_Config\n
01632   *         DR           DU            LL_RTC_DATE_Config\n
01633   *         DR           YT            LL_RTC_DATE_Config\n
01634   *         DR           YU            LL_RTC_DATE_Config
01635   * @param  RTCx RTC Instance
01636   * @param  WeekDay This parameter can be one of the following values:
01637   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01638   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01639   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01640   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01641   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01642   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01643   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01644   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
01645   * @param  Month This parameter can be one of the following values:
01646   *         @arg @ref LL_RTC_MONTH_JANUARY
01647   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01648   *         @arg @ref LL_RTC_MONTH_MARCH
01649   *         @arg @ref LL_RTC_MONTH_APRIL
01650   *         @arg @ref LL_RTC_MONTH_MAY
01651   *         @arg @ref LL_RTC_MONTH_JUNE
01652   *         @arg @ref LL_RTC_MONTH_JULY
01653   *         @arg @ref LL_RTC_MONTH_AUGUST
01654   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01655   *         @arg @ref LL_RTC_MONTH_OCTOBER
01656   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01657   *         @arg @ref LL_RTC_MONTH_DECEMBER
01658   * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
01659   * @retval None
01660   */
01661 __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
01662 {
01663   register uint32_t temp = 0U;
01664
01665   temp = (WeekDay << RTC_DR_WDU_Pos)                                                        | \
01666          (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))   | \
01667          (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
01668          (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
01669
01670   MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
01671 }
01672
01673 /**
01674   * @brief  Get date (WeekDay, Day, Month and Year) in BCD format
01675   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01676   *       before reading this bit
01677   * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
01678   * and __LL_RTC_GET_DAY are available to get independently each parameter.
01679   * @rmtoll DR           WDU           LL_RTC_DATE_Get\n
01680   *         DR           MT            LL_RTC_DATE_Get\n
01681   *         DR           MU            LL_RTC_DATE_Get\n
01682   *         DR           DT            LL_RTC_DATE_Get\n
01683   *         DR           DU            LL_RTC_DATE_Get\n
01684   *         DR           YT            LL_RTC_DATE_Get\n
01685   *         DR           YU            LL_RTC_DATE_Get
01686   * @param  RTCx RTC Instance
01687   * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
01688   */
01689 __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
01690 {
01691   register uint32_t temp = 0U;
01692
01693   temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
01694   return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
01695                     (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
01696                     (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
01697                     ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
01698 }
01699
01700 /**
01701   * @}
01702   */
01703
01704 /** @defgroup RTC_LL_EF_ALARMA ALARMA
01705   * @{
01706   */
01707
01708 /**
01709   * @brief  Enable Alarm A
01710   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01711   * @rmtoll CR           ALRAE         LL_RTC_ALMA_Enable
01712   * @param  RTCx RTC Instance
01713   * @retval None
01714   */
01715 __STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
01716 {
01717   SET_BIT(RTCx->CR, RTC_CR_ALRAE);
01718 }
01719
01720 /**
01721   * @brief  Disable Alarm A
01722   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01723   * @rmtoll CR           ALRAE         LL_RTC_ALMA_Disable
01724   * @param  RTCx RTC Instance
01725   * @retval None
01726   */
01727 __STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
01728 {
01729   CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
01730 }
01731
01732 /**
01733   * @brief  Specify the Alarm A masks.
01734   * @rmtoll ALRMAR       MSK4          LL_RTC_ALMA_SetMask\n
01735   *         ALRMAR       MSK3          LL_RTC_ALMA_SetMask\n
01736   *         ALRMAR       MSK2          LL_RTC_ALMA_SetMask\n
01737   *         ALRMAR       MSK1          LL_RTC_ALMA_SetMask
01738   * @param  RTCx RTC Instance
01739   * @param  Mask This parameter can be a combination of the following values:
01740   *         @arg @ref LL_RTC_ALMA_MASK_NONE
01741   *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
01742   *         @arg @ref LL_RTC_ALMA_MASK_HOURS
01743   *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
01744   *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
01745   *         @arg @ref LL_RTC_ALMA_MASK_ALL
01746   * @retval None
01747   */
01748 __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
01749 {
01750   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
01751 }
01752
01753 /**
01754   * @brief  Get the Alarm A masks.
01755   * @rmtoll ALRMAR       MSK4          LL_RTC_ALMA_GetMask\n
01756   *         ALRMAR       MSK3          LL_RTC_ALMA_GetMask\n
01757   *         ALRMAR       MSK2          LL_RTC_ALMA_GetMask\n
01758   *         ALRMAR       MSK1          LL_RTC_ALMA_GetMask
01759   * @param  RTCx RTC Instance
01760   * @retval Returned value can be can be a combination of the following values:
01761   *         @arg @ref LL_RTC_ALMA_MASK_NONE
01762   *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
01763   *         @arg @ref LL_RTC_ALMA_MASK_HOURS
01764   *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
01765   *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
01766   *         @arg @ref LL_RTC_ALMA_MASK_ALL
01767   */
01768 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
01769 {
01770   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
01771 }
01772
01773 /**
01774   * @brief  Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
01775   * @rmtoll ALRMAR       WDSEL         LL_RTC_ALMA_EnableWeekday
01776   * @param  RTCx RTC Instance
01777   * @retval None
01778   */
01779 __STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
01780 {
01781   SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
01782 }
01783
01784 /**
01785   * @brief  Disable AlarmA Week day selection (DU[3:0] represents the date )
01786   * @rmtoll ALRMAR       WDSEL         LL_RTC_ALMA_DisableWeekday
01787   * @param  RTCx RTC Instance
01788   * @retval None
01789   */
01790 __STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
01791 {
01792   CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
01793 }
01794
01795 /**
01796   * @brief  Set ALARM A Day in BCD format
01797   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
01798   * @rmtoll ALRMAR       DT            LL_RTC_ALMA_SetDay\n
01799   *         ALRMAR       DU            LL_RTC_ALMA_SetDay
01800   * @param  RTCx RTC Instance
01801   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
01802   * @retval None
01803   */
01804 __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
01805 {
01806   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
01807              (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
01808 }
01809
01810 /**
01811   * @brief  Get ALARM A Day in BCD format
01812   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
01813   * @rmtoll ALRMAR       DT            LL_RTC_ALMA_GetDay\n
01814   *         ALRMAR       DU            LL_RTC_ALMA_GetDay
01815   * @param  RTCx RTC Instance
01816   * @retval Value between Min_Data=0x01 and Max_Data=0x31
01817   */
01818 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
01819 {
01820   register uint32_t temp = 0U;
01821
01822   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU));
01823   return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos));
01824 }
01825
01826 /**
01827   * @brief  Set ALARM A Weekday
01828   * @rmtoll ALRMAR       DU            LL_RTC_ALMA_SetWeekDay
01829   * @param  RTCx RTC Instance
01830   * @param  WeekDay This parameter can be one of the following values:
01831   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01832   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01833   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01834   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01835   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01836   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01837   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01838   * @retval None
01839   */
01840 __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
01841 {
01842   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
01843 }
01844
01845 /**
01846   * @brief  Get ALARM A Weekday
01847   * @rmtoll ALRMAR       DU            LL_RTC_ALMA_GetWeekDay
01848   * @param  RTCx RTC Instance
01849   * @retval Returned value can be one of the following values:
01850   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01851   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01852   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01853   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01854   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01855   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01856   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01857   */
01858 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
01859 {
01860   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
01861 }
01862
01863 /**
01864   * @brief  Set Alarm A time format (AM/24-hour or PM notation)
01865   * @rmtoll ALRMAR       PM            LL_RTC_ALMA_SetTimeFormat
01866   * @param  RTCx RTC Instance
01867   * @param  TimeFormat This parameter can be one of the following values:
01868   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
01869   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
01870   * @retval None
01871   */
01872 __STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
01873 {
01874   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
01875 }
01876
01877 /**
01878   * @brief  Get Alarm A time format (AM or PM notation)
01879   * @rmtoll ALRMAR       PM            LL_RTC_ALMA_GetTimeFormat
01880   * @param  RTCx RTC Instance
01881   * @retval Returned value can be one of the following values:
01882   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
01883   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
01884   */
01885 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
01886 {
01887   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
01888 }
01889
01890 /**
01891   * @brief  Set ALARM A Hours in BCD format
01892   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
01893   * @rmtoll ALRMAR       HT            LL_RTC_ALMA_SetHour\n
01894   *         ALRMAR       HU            LL_RTC_ALMA_SetHour
01895   * @param  RTCx RTC Instance
01896   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01897   * @retval None
01898   */
01899 __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
01900 {
01901   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
01902              (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
01903 }
01904
01905 /**
01906   * @brief  Get ALARM A Hours in BCD format
01907   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
01908   * @rmtoll ALRMAR       HT            LL_RTC_ALMA_GetHour\n
01909   *         ALRMAR       HU            LL_RTC_ALMA_GetHour
01910   * @param  RTCx RTC Instance
01911   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01912   */
01913 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
01914 {
01915   register uint32_t temp = 0U;
01916
01917   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU));
01918   return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos));
01919 }
01920
01921 /**
01922   * @brief  Set ALARM A Minutes in BCD format
01923   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
01924   * @rmtoll ALRMAR       MNT           LL_RTC_ALMA_SetMinute\n
01925   *         ALRMAR       MNU           LL_RTC_ALMA_SetMinute
01926   * @param  RTCx RTC Instance
01927   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01928   * @retval None
01929   */
01930 __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
01931 {
01932   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
01933              (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
01934 }
01935
01936 /**
01937   * @brief  Get ALARM A Minutes in BCD format
01938   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
01939   * @rmtoll ALRMAR       MNT           LL_RTC_ALMA_GetMinute\n
01940   *         ALRMAR       MNU           LL_RTC_ALMA_GetMinute
01941   * @param  RTCx RTC Instance
01942   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01943   */
01944 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
01945 {
01946   register uint32_t temp = 0U;
01947
01948   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU));
01949   return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos));
01950 }
01951
01952 /**
01953   * @brief  Set ALARM A Seconds in BCD format
01954   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
01955   * @rmtoll ALRMAR       ST            LL_RTC_ALMA_SetSecond\n
01956   *         ALRMAR       SU            LL_RTC_ALMA_SetSecond
01957   * @param  RTCx RTC Instance
01958   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01959   * @retval None
01960   */
01961 __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
01962 {
01963   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
01964              (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
01965 }
01966
01967 /**
01968   * @brief  Get ALARM A Seconds in BCD format
01969   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
01970   * @rmtoll ALRMAR       ST            LL_RTC_ALMA_GetSecond\n
01971   *         ALRMAR       SU            LL_RTC_ALMA_GetSecond
01972   * @param  RTCx RTC Instance
01973   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01974   */
01975 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
01976 {
01977   register uint32_t temp = 0U;
01978
01979   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
01980   return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos));
01981 }
01982
01983 /**
01984   * @brief  Set Alarm A Time (hour, minute and second) in BCD format
01985   * @rmtoll ALRMAR       PM            LL_RTC_ALMA_ConfigTime\n
01986   *         ALRMAR       HT            LL_RTC_ALMA_ConfigTime\n
01987   *         ALRMAR       HU            LL_RTC_ALMA_ConfigTime\n
01988   *         ALRMAR       MNT           LL_RTC_ALMA_ConfigTime\n
01989   *         ALRMAR       MNU           LL_RTC_ALMA_ConfigTime\n
01990   *         ALRMAR       ST            LL_RTC_ALMA_ConfigTime\n
01991   *         ALRMAR       SU            LL_RTC_ALMA_ConfigTime
01992   * @param  RTCx RTC Instance
01993   * @param  Format12_24 This parameter can be one of the following values:
01994   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
01995   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
01996   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01997   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01998   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01999   * @retval None
02000   */
02001 __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
02002 {
02003   register uint32_t temp = 0U;
02004
02005   temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))    | \
02006          (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
02007          (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
02008
02009   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
02010 }
02011
02012 /**
02013   * @brief  Get Alarm B Time (hour, minute and second) in BCD format
02014   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
02015   * are available to get independently each parameter.
02016   * @rmtoll ALRMAR       HT            LL_RTC_ALMA_GetTime\n
02017   *         ALRMAR       HU            LL_RTC_ALMA_GetTime\n
02018   *         ALRMAR       MNT           LL_RTC_ALMA_GetTime\n
02019   *         ALRMAR       MNU           LL_RTC_ALMA_GetTime\n
02020   *         ALRMAR       ST            LL_RTC_ALMA_GetTime\n
02021   *         ALRMAR       SU            LL_RTC_ALMA_GetTime
02022   * @param  RTCx RTC Instance
02023   * @retval Combination of hours, minutes and seconds.
02024   */
02025 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
02026 {
02027   return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
02028 }
02029
02030 /**
02031   * @brief  Set Alarm A Mask the most-significant bits starting at this bit
02032   * @note This register can be written only when ALRAE is reset in RTC_CR register,
02033   *       or in initialization mode.
02034   * @rmtoll ALRMASSR     MASKSS        LL_RTC_ALMA_SetSubSecondMask
02035   * @param  RTCx RTC Instance
02036   * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
02037   * @retval None
02038   */
02039 __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
02040 {
02041   MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
02042 }
02043
02044 /**
02045   * @brief  Get Alarm A Mask the most-significant bits starting at this bit
02046   * @rmtoll ALRMASSR     MASKSS        LL_RTC_ALMA_GetSubSecondMask
02047   * @param  RTCx RTC Instance
02048   * @retval Value between Min_Data=0x00 and Max_Data=0xF
02049   */
02050 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
02051 {
02052   return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
02053 }
02054
02055 /**
02056   * @brief  Set Alarm A Sub seconds value
02057   * @rmtoll ALRMASSR     SS            LL_RTC_ALMA_SetSubSecond
02058   * @param  RTCx RTC Instance
02059   * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
02060   * @retval None
02061   */
02062 __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
02063 {
02064   MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
02065 }
02066
02067 /**
02068   * @brief  Get Alarm A Sub seconds value
02069   * @rmtoll ALRMASSR     SS            LL_RTC_ALMA_GetSubSecond
02070   * @param  RTCx RTC Instance
02071   * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
02072   */
02073 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
02074 {
02075   return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
02076 }
02077
02078 /**
02079   * @}
02080   */
02081
02082 /** @defgroup RTC_LL_EF_ALARMB ALARMB
02083   * @{
02084   */
02085
02086 /**
02087   * @brief  Enable Alarm B
02088   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02089   * @rmtoll CR           ALRBE         LL_RTC_ALMB_Enable
02090   * @param  RTCx RTC Instance
02091   * @retval None
02092   */
02093 __STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
02094 {
02095   SET_BIT(RTCx->CR, RTC_CR_ALRBE);
02096 }
02097
02098 /**
02099   * @brief  Disable Alarm B
02100   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02101   * @rmtoll CR           ALRBE         LL_RTC_ALMB_Disable
02102   * @param  RTCx RTC Instance
02103   * @retval None
02104   */
02105 __STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
02106 {
02107   CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
02108 }
02109
02110 /**
02111   * @brief  Specify the Alarm B masks.
02112   * @rmtoll ALRMBR       MSK4          LL_RTC_ALMB_SetMask\n
02113   *         ALRMBR       MSK3          LL_RTC_ALMB_SetMask\n
02114   *         ALRMBR       MSK2          LL_RTC_ALMB_SetMask\n
02115   *         ALRMBR       MSK1          LL_RTC_ALMB_SetMask
02116   * @param  RTCx RTC Instance
02117   * @param  Mask This parameter can be a combination of the following values:
02118   *         @arg @ref LL_RTC_ALMB_MASK_NONE
02119   *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
02120   *         @arg @ref LL_RTC_ALMB_MASK_HOURS
02121   *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
02122   *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
02123   *         @arg @ref LL_RTC_ALMB_MASK_ALL
02124   * @retval None
02125   */
02126 __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
02127 {
02128   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
02129 }
02130
02131 /**
02132   * @brief  Get the Alarm B masks.
02133   * @rmtoll ALRMBR       MSK4          LL_RTC_ALMB_GetMask\n
02134   *         ALRMBR       MSK3          LL_RTC_ALMB_GetMask\n
02135   *         ALRMBR       MSK2          LL_RTC_ALMB_GetMask\n
02136   *         ALRMBR       MSK1          LL_RTC_ALMB_GetMask
02137   * @param  RTCx RTC Instance
02138   * @retval Returned value can be can be a combination of the following values:
02139   *         @arg @ref LL_RTC_ALMB_MASK_NONE
02140   *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
02141   *         @arg @ref LL_RTC_ALMB_MASK_HOURS
02142   *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
02143   *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
02144   *         @arg @ref LL_RTC_ALMB_MASK_ALL
02145   */
02146 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
02147 {
02148   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
02149 }
02150
02151 /**
02152   * @brief  Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
02153   * @rmtoll ALRMBR       WDSEL         LL_RTC_ALMB_EnableWeekday
02154   * @param  RTCx RTC Instance
02155   * @retval None
02156   */
02157 __STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
02158 {
02159   SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
02160 }
02161
02162 /**
02163   * @brief  Disable AlarmB Week day selection (DU[3:0] represents the date )
02164   * @rmtoll ALRMBR       WDSEL         LL_RTC_ALMB_DisableWeekday
02165   * @param  RTCx RTC Instance
02166   * @retval None
02167   */
02168 __STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
02169 {
02170   CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
02171 }
02172
02173 /**
02174   * @brief  Set ALARM B Day in BCD format
02175   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
02176   * @rmtoll ALRMBR       DT            LL_RTC_ALMB_SetDay\n
02177   *         ALRMBR       DU            LL_RTC_ALMB_SetDay
02178   * @param  RTCx RTC Instance
02179   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
02180   * @retval None
02181   */
02182 __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
02183 {
02184   MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
02185              (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
02186 }
02187
02188 /**
02189   * @brief  Get ALARM B Day in BCD format
02190   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
02191   * @rmtoll ALRMBR       DT            LL_RTC_ALMB_GetDay\n
02192   *         ALRMBR       DU            LL_RTC_ALMB_GetDay
02193   * @param  RTCx RTC Instance
02194   * @retval Value between Min_Data=0x01 and Max_Data=0x31
02195   */
02196 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
02197 {
02198   register uint32_t temp = 0U;
02199
02200   temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU));
02201   return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_ALRMBR_DT_Pos) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos));
02202 }
02203
02204 /**
02205   * @brief  Set ALARM B Weekday
02206   * @rmtoll ALRMBR       DU            LL_RTC_ALMB_SetWeekDay
02207   * @param  RTCx RTC Instance
02208   * @param  WeekDay This parameter can be one of the following values:
02209   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02210   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02211   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02212   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02213   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02214   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02215   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02216   * @retval None
02217   */
02218 __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
02219 {
02220   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
02221 }
02222
02223 /**
02224   * @brief  Get ALARM B Weekday
02225   * @rmtoll ALRMBR       DU            LL_RTC_ALMB_GetWeekDay
02226   * @param  RTCx RTC Instance
02227   * @retval Returned value can be one of the following values:
02228   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02229   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02230   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02231   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02232   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02233   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02234   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02235   */
02236 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
02237 {
02238   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
02239 }
02240
02241 /**
02242   * @brief  Set ALARM B time format (AM/24-hour or PM notation)
02243   * @rmtoll ALRMBR       PM            LL_RTC_ALMB_SetTimeFormat
02244   * @param  RTCx RTC Instance
02245   * @param  TimeFormat This parameter can be one of the following values:
02246   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02247   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02248   * @retval None
02249   */
02250 __STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
02251 {
02252   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
02253 }
02254
02255 /**
02256   * @brief  Get ALARM B time format (AM or PM notation)
02257   * @rmtoll ALRMBR       PM            LL_RTC_ALMB_GetTimeFormat
02258   * @param  RTCx RTC Instance
02259   * @retval Returned value can be one of the following values:
02260   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02261   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02262   */
02263 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
02264 {
02265   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
02266 }
02267
02268 /**
02269   * @brief  Set ALARM B Hours in BCD format
02270   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
02271   * @rmtoll ALRMBR       HT            LL_RTC_ALMB_SetHour\n
02272   *         ALRMBR       HU            LL_RTC_ALMB_SetHour
02273   * @param  RTCx RTC Instance
02274   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02275   * @retval None
02276   */
02277 __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
02278 {
02279   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
02280              (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
02281 }
02282
02283 /**
02284   * @brief  Get ALARM B Hours in BCD format
02285   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
02286   * @rmtoll ALRMBR       HT            LL_RTC_ALMB_GetHour\n
02287   *         ALRMBR       HU            LL_RTC_ALMB_GetHour
02288   * @param  RTCx RTC Instance
02289   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02290   */
02291 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
02292 {
02293   register uint32_t temp = 0U;
02294
02295   temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU));
02296   return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_ALRMBR_HT_Pos) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_ALRMBR_HU_Pos));
02297 }
02298
02299 /**
02300   * @brief  Set ALARM B Minutes in BCD format
02301   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
02302   * @rmtoll ALRMBR       MNT           LL_RTC_ALMB_SetMinute\n
02303   *         ALRMBR       MNU           LL_RTC_ALMB_SetMinute
02304   * @param  RTCx RTC Instance
02305   * @param  Minutes between Min_Data=0x00 and Max_Data=0x59
02306   * @retval None
02307   */
02308 __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
02309 {
02310   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
02311              (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
02312 }
02313
02314 /**
02315   * @brief  Get ALARM B Minutes in BCD format
02316   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
02317   * @rmtoll ALRMBR       MNT           LL_RTC_ALMB_GetMinute\n
02318   *         ALRMBR       MNU           LL_RTC_ALMB_GetMinute
02319   * @param  RTCx RTC Instance
02320   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02321   */
02322 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
02323 {
02324   register uint32_t temp = 0U;
02325
02326   temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU));
02327   return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_ALRMBR_MNT_Pos) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_ALRMBR_MNU_Pos));
02328 }
02329
02330 /**
02331   * @brief  Set ALARM B Seconds in BCD format
02332   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
02333   * @rmtoll ALRMBR       ST            LL_RTC_ALMB_SetSecond\n
02334   *         ALRMBR       SU            LL_RTC_ALMB_SetSecond
02335   * @param  RTCx RTC Instance
02336   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
02337   * @retval None
02338   */
02339 __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
02340 {
02341   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
02342              (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
02343 }
02344
02345 /**
02346   * @brief  Get ALARM B Seconds in BCD format
02347   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
02348   * @rmtoll ALRMBR       ST            LL_RTC_ALMB_GetSecond\n
02349   *         ALRMBR       SU            LL_RTC_ALMB_GetSecond
02350   * @param  RTCx RTC Instance
02351   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02352   */
02353 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
02354 {
02355   register uint32_t temp = 0U;
02356
02357   temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU));
02358   return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_ALRMBR_ST_Pos) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_ALRMBR_SU_Pos));
02359 }
02360
02361 /**
02362   * @brief  Set Alarm B Time (hour, minute and second) in BCD format
02363   * @rmtoll ALRMBR       PM            LL_RTC_ALMB_ConfigTime\n
02364   *         ALRMBR       HT            LL_RTC_ALMB_ConfigTime\n
02365   *         ALRMBR       HU            LL_RTC_ALMB_ConfigTime\n
02366   *         ALRMBR       MNT           LL_RTC_ALMB_ConfigTime\n
02367   *         ALRMBR       MNU           LL_RTC_ALMB_ConfigTime\n
02368   *         ALRMBR       ST            LL_RTC_ALMB_ConfigTime\n
02369   *         ALRMBR       SU            LL_RTC_ALMB_ConfigTime
02370   * @param  RTCx RTC Instance
02371   * @param  Format12_24 This parameter can be one of the following values:
02372   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02373   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02374   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02375   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
02376   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
02377   * @retval None
02378   */
02379 __STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
02380 {
02381   register uint32_t temp = 0U;
02382
02383   temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))    | \
02384          (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
02385          (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
02386
02387   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM| RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
02388 }
02389
02390 /**
02391   * @brief  Get Alarm B Time (hour, minute and second) in BCD format
02392   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
02393   * are available to get independently each parameter.
02394   * @rmtoll ALRMBR       HT            LL_RTC_ALMB_GetTime\n
02395   *         ALRMBR       HU            LL_RTC_ALMB_GetTime\n
02396   *         ALRMBR       MNT           LL_RTC_ALMB_GetTime\n
02397   *         ALRMBR       MNU           LL_RTC_ALMB_GetTime\n
02398   *         ALRMBR       ST            LL_RTC_ALMB_GetTime\n
02399   *         ALRMBR       SU            LL_RTC_ALMB_GetTime
02400   * @param  RTCx RTC Instance
02401   * @retval Combination of hours, minutes and seconds.
02402   */
02403 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
02404 {
02405   return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
02406 }
02407
02408 /**
02409   * @brief  Set Alarm B Mask the most-significant bits starting at this bit
02410   * @note This register can be written only when ALRBE is reset in RTC_CR register,
02411   *       or in initialization mode.
02412   * @rmtoll ALRMBSSR     MASKSS        LL_RTC_ALMB_SetSubSecondMask
02413   * @param  RTCx RTC Instance
02414   * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
02415   * @retval None
02416   */
02417 __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
02418 {
02419   MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
02420 }
02421
02422 /**
02423   * @brief  Get Alarm B Mask the most-significant bits starting at this bit
02424   * @rmtoll ALRMBSSR     MASKSS        LL_RTC_ALMB_GetSubSecondMask
02425   * @param  RTCx RTC Instance
02426   * @retval Value between Min_Data=0x00 and Max_Data=0xF
02427   */
02428 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
02429 {
02430   return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS)  >> RTC_ALRMBSSR_MASKSS_Pos);
02431 }
02432
02433 /**
02434   * @brief  Set Alarm B Sub seconds value
02435   * @rmtoll ALRMBSSR     SS            LL_RTC_ALMB_SetSubSecond
02436   * @param  RTCx RTC Instance
02437   * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
02438   * @retval None
02439   */
02440 __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
02441 {
02442   MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
02443 }
02444
02445 /**
02446   * @brief  Get Alarm B Sub seconds value
02447   * @rmtoll ALRMBSSR     SS            LL_RTC_ALMB_GetSubSecond
02448   * @param  RTCx RTC Instance
02449   * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
02450   */
02451 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
02452 {
02453   return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
02454 }
02455
02456 /**
02457   * @}
02458   */
02459
02460 /** @defgroup RTC_LL_EF_Timestamp Timestamp
02461   * @{
02462   */
02463
02464 /**
02465   * @brief  Enable Timestamp
02466   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02467   * @rmtoll CR           TSE           LL_RTC_TS_Enable
02468   * @param  RTCx RTC Instance
02469   * @retval None
02470   */
02471 __STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
02472 {
02473   SET_BIT(RTCx->CR, RTC_CR_TSE);
02474 }
02475
02476 /**
02477   * @brief  Disable Timestamp
02478   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02479   * @rmtoll CR           TSE           LL_RTC_TS_Disable
02480   * @param  RTCx RTC Instance
02481   * @retval None
02482   */
02483 __STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
02484 {
02485   CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
02486 }
02487
02488 /**
02489   * @brief  Set Time-stamp event active edge
02490   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02491   * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
02492   * @rmtoll CR           TSEDGE        LL_RTC_TS_SetActiveEdge
02493   * @param  RTCx RTC Instance
02494   * @param  Edge This parameter can be one of the following values:
02495   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
02496   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
02497   * @retval None
02498   */
02499 __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
02500 {
02501   MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
02502 }
02503
02504 /**
02505   * @brief  Get Time-stamp event active edge
02506   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02507   * @rmtoll CR           TSEDGE        LL_RTC_TS_GetActiveEdge
02508   * @param  RTCx RTC Instance
02509   * @retval Returned value can be one of the following values:
02510   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
02511   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
02512   */
02513 __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
02514 {
02515   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
02516 }
02517
02518 /**
02519   * @brief  Get Timestamp AM/PM notation (AM or 24-hour format)
02520   * @rmtoll TSTR         PM            LL_RTC_TS_GetTimeFormat
02521   * @param  RTCx RTC Instance
02522   * @retval Returned value can be one of the following values:
02523   *         @arg @ref LL_RTC_TS_TIME_FORMAT_AM
02524   *         @arg @ref LL_RTC_TS_TIME_FORMAT_PM
02525   */
02526 __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
02527 {
02528   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
02529 }
02530
02531 /**
02532   * @brief  Get Timestamp Hours in BCD format
02533   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
02534   * @rmtoll TSTR         HT            LL_RTC_TS_GetHour\n
02535   *         TSTR         HU            LL_RTC_TS_GetHour
02536   * @param  RTCx RTC Instance
02537   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02538   */
02539 __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
02540 {
02541   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
02542 }
02543
02544 /**
02545   * @brief  Get Timestamp Minutes in BCD format
02546   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
02547   * @rmtoll TSTR         MNT           LL_RTC_TS_GetMinute\n
02548   *         TSTR         MNU           LL_RTC_TS_GetMinute
02549   * @param  RTCx RTC Instance
02550   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02551   */
02552 __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
02553 {
02554   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
02555 }
02556
02557 /**
02558   * @brief  Get Timestamp Seconds in BCD format
02559   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
02560   * @rmtoll TSTR         ST            LL_RTC_TS_GetSecond\n
02561   *         TSTR         SU            LL_RTC_TS_GetSecond
02562   * @param  RTCx RTC Instance
02563   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02564   */
02565 __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
02566 {
02567   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
02568 }
02569
02570 /**
02571   * @brief  Get Timestamp time (hour, minute and second) in BCD format
02572   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
02573   * are available to get independently each parameter.
02574   * @rmtoll TSTR         HT            LL_RTC_TS_GetTime\n
02575   *         TSTR         HU            LL_RTC_TS_GetTime\n
02576   *         TSTR         MNT           LL_RTC_TS_GetTime\n
02577   *         TSTR         MNU           LL_RTC_TS_GetTime\n
02578   *         TSTR         ST            LL_RTC_TS_GetTime\n
02579   *         TSTR         SU            LL_RTC_TS_GetTime
02580   * @param  RTCx RTC Instance
02581   * @retval Combination of hours, minutes and seconds.
02582   */
02583 __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
02584 {
02585   return (uint32_t)(READ_BIT(RTCx->TSTR,
02586                              RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
02587 }
02588
02589 /**
02590   * @brief  Get Timestamp Week day
02591   * @rmtoll TSDR         WDU           LL_RTC_TS_GetWeekDay
02592   * @param  RTCx RTC Instance
02593   * @retval Returned value can be one of the following values:
02594   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02595   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02596   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02597   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02598   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02599   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02600   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02601   */
02602 __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
02603 {
02604   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
02605 }
02606
02607 /**
02608   * @brief  Get Timestamp Month in BCD format
02609   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
02610   * @rmtoll TSDR         MT            LL_RTC_TS_GetMonth\n
02611   *         TSDR         MU            LL_RTC_TS_GetMonth
02612   * @param  RTCx RTC Instance
02613   * @retval Returned value can be one of the following values:
02614   *         @arg @ref LL_RTC_MONTH_JANUARY
02615   *         @arg @ref LL_RTC_MONTH_FEBRUARY
02616   *         @arg @ref LL_RTC_MONTH_MARCH
02617   *         @arg @ref LL_RTC_MONTH_APRIL
02618   *         @arg @ref LL_RTC_MONTH_MAY
02619   *         @arg @ref LL_RTC_MONTH_JUNE
02620   *         @arg @ref LL_RTC_MONTH_JULY
02621   *         @arg @ref LL_RTC_MONTH_AUGUST
02622   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
02623   *         @arg @ref LL_RTC_MONTH_OCTOBER
02624   *         @arg @ref LL_RTC_MONTH_NOVEMBER
02625   *         @arg @ref LL_RTC_MONTH_DECEMBER
02626   */
02627 __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
02628 {
02629   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
02630 }
02631
02632 /**
02633   * @brief  Get Timestamp Day in BCD format
02634   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
02635   * @rmtoll TSDR         DT            LL_RTC_TS_GetDay\n
02636   *         TSDR         DU            LL_RTC_TS_GetDay
02637   * @param  RTCx RTC Instance
02638   * @retval Value between Min_Data=0x01 and Max_Data=0x31
02639   */
02640 __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
02641 {
02642   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
02643 }
02644
02645 /**
02646   * @brief  Get Timestamp date (WeekDay, Day and Month) in BCD format
02647   * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
02648   * and __LL_RTC_GET_DAY are available to get independently each parameter.
02649   * @rmtoll TSDR         WDU           LL_RTC_TS_GetDate\n
02650   *         TSDR         MT            LL_RTC_TS_GetDate\n
02651   *         TSDR         MU            LL_RTC_TS_GetDate\n
02652   *         TSDR         DT            LL_RTC_TS_GetDate\n
02653   *         TSDR         DU            LL_RTC_TS_GetDate
02654   * @param  RTCx RTC Instance
02655   * @retval Combination of Weekday, Day and Month
02656   */
02657 __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
02658 {
02659   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
02660 }
02661
02662 /**
02663   * @brief  Get time-stamp sub second value
02664   * @rmtoll TSSSR        SS            LL_RTC_TS_GetSubSecond
02665   * @param  RTCx RTC Instance
02666   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
02667   */
02668 __STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
02669 {
02670   return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
02671 }
02672
02673 #if defined(RTC_TAFCR_TAMPTS)
02674 /**
02675   * @brief  Activate timestamp on tamper detection event
02676   * @rmtoll TAFCR       TAMPTS        LL_RTC_TS_EnableOnTamper
02677   * @param  RTCx RTC Instance
02678   * @retval None
02679   */
02680 __STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
02681 {
02682   SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPTS);
02683 }
02684
02685 /**
02686   * @brief  Disable timestamp on tamper detection event
02687   * @rmtoll TAFCR       TAMPTS        LL_RTC_TS_DisableOnTamper
02688   * @param  RTCx RTC Instance
02689   * @retval None
02690   */
02691 __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
02692 {
02693   CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPTS);
02694 }
02695 #endif /* RTC_TAFCR_TAMPTS */
02696
02697 /**
02698   * @}
02699   */
02700
02701 /** @defgroup RTC_LL_EF_Tamper Tamper
02702   * @{
02703   */
02704
02705 /**
02706   * @brief  Enable RTC_TAMPx input detection
02707   * @rmtoll TAFCR       TAMP1E        LL_RTC_TAMPER_Enable\n
02708   *         TAFCR       TAMP2E        LL_RTC_TAMPER_Enable\n
02709   *         TAFCR       TAMP3E        LL_RTC_TAMPER_Enable
02710   * @param  RTCx RTC Instance
02711   * @param  Tamper This parameter can be a combination of the following values:
02712   *         @arg @ref LL_RTC_TAMPER_1
02713   *         @arg @ref LL_RTC_TAMPER_2
02714   *         @arg @ref LL_RTC_TAMPER_3 (*)
02715   *
02716   *         (*) value not defined in all devices.
02717   * @retval None
02718   */
02719 __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
02720 {
02721   SET_BIT(RTCx->TAFCR, Tamper);
02722 }
02723
02724 /**
02725   * @brief  Clear RTC_TAMPx input detection
02726   * @rmtoll TAFCR       TAMP1E        LL_RTC_TAMPER_Disable\n
02727   *         TAFCR       TAMP2E        LL_RTC_TAMPER_Disable\n
02728   *         TAFCR       TAMP3E        LL_RTC_TAMPER_Disable
02729   * @param  RTCx RTC Instance
02730   * @param  Tamper This parameter can be a combination of the following values:
02731   *         @arg @ref LL_RTC_TAMPER_1
02732   *         @arg @ref LL_RTC_TAMPER_2
02733   *         @arg @ref LL_RTC_TAMPER_3 (*)
02734   *
02735   *         (*) value not defined in all devices.
02736   * @retval None
02737   */
02738 __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
02739 {
02740   CLEAR_BIT(RTCx->TAFCR, Tamper);
02741 }
02742
02743 #if defined(RTC_TAFCR_TAMPPUDIS)
02744 /**
02745   * @brief  Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
02746   * @rmtoll TAFCR       TAMPPUDIS     LL_RTC_TAMPER_DisablePullUp
02747   * @param  RTCx RTC Instance
02748   * @retval None
02749   */
02750 __STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
02751 {
02752   SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS);
02753 }
02754
02755 /**
02756   * @brief  Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
02757   * @rmtoll TAFCR       TAMPPUDIS     LL_RTC_TAMPER_EnablePullUp
02758   * @param  RTCx RTC Instance
02759   * @retval None
02760   */
02761 __STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
02762 {
02763   CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS);
02764 }
02765 #endif /* RTC_TAFCR_TAMPPUDIS */
02766
02767 #if defined(RTC_TAFCR_TAMPPRCH)
02768 /**
02769   * @brief  Set RTC_TAMPx precharge duration
02770   * @rmtoll TAFCR       TAMPPRCH      LL_RTC_TAMPER_SetPrecharge
02771   * @param  RTCx RTC Instance
02772   * @param  Duration This parameter can be one of the following values:
02773   *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
02774   *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
02775   *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
02776   *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
02777   * @retval None
02778   */
02779 __STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
02780 {
02781   MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH, Duration);
02782 }
02783
02784 /**
02785   * @brief  Get RTC_TAMPx precharge duration
02786   * @rmtoll TAFCR       TAMPPRCH      LL_RTC_TAMPER_GetPrecharge
02787   * @param  RTCx RTC Instance
02788   * @retval Returned value can be one of the following values:
02789   *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
02790   *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
02791   *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
02792   *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
02793   */
02794 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
02795 {
02796   return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH));
02797 }
02798 #endif /* RTC_TAFCR_TAMPPRCH */
02799
02800 #if defined(RTC_TAFCR_TAMPFLT)
02801 /**
02802   * @brief  Set RTC_TAMPx filter count
02803   * @rmtoll TAFCR       TAMPFLT       LL_RTC_TAMPER_SetFilterCount
02804   * @param  RTCx RTC Instance
02805   * @param  FilterCount This parameter can be one of the following values:
02806   *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
02807   *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
02808   *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
02809   *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
02810   * @retval None
02811   */
02812 __STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
02813 {
02814   MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPFLT, FilterCount);
02815 }
02816
02817 /**
02818   * @brief  Get RTC_TAMPx filter count
02819   * @rmtoll TAFCR       TAMPFLT       LL_RTC_TAMPER_GetFilterCount
02820   * @param  RTCx RTC Instance
02821   * @retval Returned value can be one of the following values:
02822   *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
02823   *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
02824   *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
02825   *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
02826   */
02827 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
02828 {
02829   return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFLT));
02830 }
02831 #endif /* RTC_TAFCR_TAMPFLT */
02832
02833 #if defined(RTC_TAFCR_TAMPFREQ)
02834 /**
02835   * @brief  Set Tamper sampling frequency
02836   * @rmtoll TAFCR       TAMPFREQ      LL_RTC_TAMPER_SetSamplingFreq
02837   * @param  RTCx RTC Instance
02838   * @param  SamplingFreq This parameter can be one of the following values:
02839   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
02840   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
02841   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
02842   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
02843   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
02844   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
02845   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
02846   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
02847   * @retval None
02848   */
02849 __STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
02850 {
02851   MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ, SamplingFreq);
02852 }
02853
02854 /**
02855   * @brief  Get Tamper sampling frequency
02856   * @rmtoll TAFCR       TAMPFREQ      LL_RTC_TAMPER_GetSamplingFreq
02857   * @param  RTCx RTC Instance
02858   * @retval Returned value can be one of the following values:
02859   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
02860   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
02861   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
02862   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
02863   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
02864   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
02865   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
02866   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
02867   */
02868 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
02869 {
02870   return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ));
02871 }
02872 #endif /* RTC_TAFCR_TAMPFREQ */
02873
02874 /**
02875   * @brief  Enable Active level for Tamper input
02876   * @rmtoll TAFCR       TAMP1TRG      LL_RTC_TAMPER_EnableActiveLevel\n
02877   *         TAFCR       TAMP2TRG      LL_RTC_TAMPER_EnableActiveLevel\n
02878   *         TAFCR       TAMP3TRG      LL_RTC_TAMPER_EnableActiveLevel
02879   * @param  RTCx RTC Instance
02880   * @param  Tamper This parameter can be a combination of the following values:
02881   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
02882   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
02883   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
02884   *
02885   *         (*) value not defined in all devices.
02886   * @retval None
02887   */
02888 __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
02889 {
02890   SET_BIT(RTCx->TAFCR, Tamper);
02891 }
02892
02893 /**
02894   * @brief  Disable Active level for Tamper input
02895   * @rmtoll TAFCR       TAMP1TRG      LL_RTC_TAMPER_DisableActiveLevel\n
02896   *         TAFCR       TAMP2TRG      LL_RTC_TAMPER_DisableActiveLevel\n
02897   *         TAFCR       TAMP3TRG      LL_RTC_TAMPER_DisableActiveLevel
02898   * @param  RTCx RTC Instance
02899   * @param  Tamper This parameter can be a combination of the following values:
02900   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
02901   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
02902   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
02903   *
02904   *         (*) value not defined in all devices.
02905   * @retval None
02906   */
02907 __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
02908 {
02909   CLEAR_BIT(RTCx->TAFCR, Tamper);
02910 }
02911
02912 /**
02913   * @}
02914   */
02915
02916 #if defined(RTC_WAKEUP_SUPPORT)
02917 /** @defgroup RTC_LL_EF_Wakeup Wakeup
02918   * @{
02919   */
02920
02921 /**
02922   * @brief  Enable Wakeup timer
02923   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02924   * @rmtoll CR           WUTE          LL_RTC_WAKEUP_Enable
02925   * @param  RTCx RTC Instance
02926   * @retval None
02927   */
02928 __STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
02929 {
02930   SET_BIT(RTCx->CR, RTC_CR_WUTE);
02931 }
02932
02933 /**
02934   * @brief  Disable Wakeup timer
02935   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02936   * @rmtoll CR           WUTE          LL_RTC_WAKEUP_Disable
02937   * @param  RTCx RTC Instance
02938   * @retval None
02939   */
02940 __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
02941 {
02942   CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
02943 }
02944
02945 /**
02946   * @brief  Check if Wakeup timer is enabled or not
02947   * @rmtoll CR           WUTE          LL_RTC_WAKEUP_IsEnabled
02948   * @param  RTCx RTC Instance
02949   * @retval State of bit (1 or 0).
02950   */
02951 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
02952 {
02953   return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE));
02954 }
02955
02956 /**
02957   * @brief  Select Wakeup clock
02958   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02959   * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
02960   * @rmtoll CR           WUCKSEL       LL_RTC_WAKEUP_SetClock
02961   * @param  RTCx RTC Instance
02962   * @param  WakeupClock This parameter can be one of the following values:
02963   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
02964   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
02965   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
02966   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
02967   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
02968   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
02969   * @retval None
02970   */
02971 __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
02972 {
02973   MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
02974 }
02975
02976 /**
02977   * @brief  Get Wakeup clock
02978   * @rmtoll CR           WUCKSEL       LL_RTC_WAKEUP_GetClock
02979   * @param  RTCx RTC Instance
02980   * @retval Returned value can be one of the following values:
02981   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
02982   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
02983   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
02984   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
02985   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
02986   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
02987   */
02988 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
02989 {
02990   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
02991 }
02992
02993 /**
02994   * @brief  Set Wakeup auto-reload value
02995   * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR
02996   * @rmtoll WUTR         WUT           LL_RTC_WAKEUP_SetAutoReload
02997   * @param  RTCx RTC Instance
02998   * @param  Value Value between Min_Data=0x00 and Max_Data=0xFFFF
02999   * @retval None
03000   */
03001 __STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
03002 {
03003   MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
03004 }
03005
03006 /**
03007   * @brief  Get Wakeup auto-reload value
03008   * @rmtoll WUTR         WUT           LL_RTC_WAKEUP_GetAutoReload
03009   * @param  RTCx RTC Instance
03010   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
03011   */
03012 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
03013 {
03014   return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
03015 }
03016
03017 /**
03018   * @}
03019   */
03020 #endif /* RTC_WAKEUP_SUPPORT */
03021
03022 #if defined(RTC_BACKUP_SUPPORT)
03023 /** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
03024   * @{
03025   */
03026
03027 /**
03028   * @brief  Writes a data in a specified RTC Backup data register.
03029   * @rmtoll BKPxR        BKP           LL_RTC_BAK_SetRegister
03030   * @param  RTCx RTC Instance
03031   * @param  BackupRegister This parameter can be one of the following values:
03032   *         @arg @ref LL_RTC_BKP_DR0
03033   *         @arg @ref LL_RTC_BKP_DR1
03034   *         @arg @ref LL_RTC_BKP_DR2
03035   *         @arg @ref LL_RTC_BKP_DR3
03036   *         @arg @ref LL_RTC_BKP_DR4
03037   *         @arg @ref LL_RTC_BKP_DR5 (*)
03038   *         @arg @ref LL_RTC_BKP_DR6 (*)
03039   *         @arg @ref LL_RTC_BKP_DR7 (*)
03040   *         @arg @ref LL_RTC_BKP_DR8 (*)
03041   *         @arg @ref LL_RTC_BKP_DR9 (*)
03042   *         @arg @ref LL_RTC_BKP_DR10 (*)
03043   *         @arg @ref LL_RTC_BKP_DR11 (*)
03044   *         @arg @ref LL_RTC_BKP_DR12 (*)
03045   *         @arg @ref LL_RTC_BKP_DR13 (*)
03046   *         @arg @ref LL_RTC_BKP_DR14 (*)
03047   *         @arg @ref LL_RTC_BKP_DR15 (*)
03048   *         @arg @ref LL_RTC_BKP_DR16 (*)
03049   *         @arg @ref LL_RTC_BKP_DR17 (*)
03050   *         @arg @ref LL_RTC_BKP_DR18 (*)
03051   *         @arg @ref LL_RTC_BKP_DR19 (*)
03052   *         @arg @ref LL_RTC_BKP_DR20 (*)
03053   *         @arg @ref LL_RTC_BKP_DR21 (*)
03054   *         @arg @ref LL_RTC_BKP_DR22 (*)
03055   *         @arg @ref LL_RTC_BKP_DR23 (*)
03056   *         @arg @ref LL_RTC_BKP_DR24 (*)
03057   *         @arg @ref LL_RTC_BKP_DR25 (*)
03058   *         @arg @ref LL_RTC_BKP_DR26 (*)
03059   *         @arg @ref LL_RTC_BKP_DR27 (*)
03060   *         @arg @ref LL_RTC_BKP_DR28 (*)
03061   *         @arg @ref LL_RTC_BKP_DR29 (*)
03062   *         @arg @ref LL_RTC_BKP_DR30 (*)
03063   *         @arg @ref LL_RTC_BKP_DR31 (*)
03064   *
03065   *         (*) value not defined in all devices.
03066   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
03067   * @retval None
03068   */
03069 __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
03070 {
03071   register uint32_t tmp = 0U;
03072
03073   tmp = (uint32_t)(&(RTCx->BKP0R));
03074   tmp += (BackupRegister * 4U);
03075
03076   /* Write the specified register */
03077   *(__IO uint32_t *)tmp = (uint32_t)Data;
03078 }
03079
03080 /**
03081   * @brief  Reads data from the specified RTC Backup data Register.
03082   * @rmtoll BKPxR        BKP           LL_RTC_BAK_GetRegister
03083   * @param  RTCx RTC Instance
03084   * @param  BackupRegister This parameter can be one of the following values:
03085   *         @arg @ref LL_RTC_BKP_DR0
03086   *         @arg @ref LL_RTC_BKP_DR1
03087   *         @arg @ref LL_RTC_BKP_DR2
03088   *         @arg @ref LL_RTC_BKP_DR3
03089   *         @arg @ref LL_RTC_BKP_DR4
03090   *         @arg @ref LL_RTC_BKP_DR5 (*)
03091   *         @arg @ref LL_RTC_BKP_DR6 (*)
03092   *         @arg @ref LL_RTC_BKP_DR7 (*)
03093   *         @arg @ref LL_RTC_BKP_DR8 (*)
03094   *         @arg @ref LL_RTC_BKP_DR9 (*)
03095   *         @arg @ref LL_RTC_BKP_DR10 (*)
03096   *         @arg @ref LL_RTC_BKP_DR11 (*)
03097   *         @arg @ref LL_RTC_BKP_DR12 (*)
03098   *         @arg @ref LL_RTC_BKP_DR13 (*)
03099   *         @arg @ref LL_RTC_BKP_DR14 (*)
03100   *         @arg @ref LL_RTC_BKP_DR15 (*)
03101   *         @arg @ref LL_RTC_BKP_DR16 (*)
03102   *         @arg @ref LL_RTC_BKP_DR17 (*)
03103   *         @arg @ref LL_RTC_BKP_DR18 (*)
03104   *         @arg @ref LL_RTC_BKP_DR19 (*)
03105   *         @arg @ref LL_RTC_BKP_DR20 (*)
03106   *         @arg @ref LL_RTC_BKP_DR21 (*)
03107   *         @arg @ref LL_RTC_BKP_DR22 (*)
03108   *         @arg @ref LL_RTC_BKP_DR23 (*)
03109   *         @arg @ref LL_RTC_BKP_DR24 (*)
03110   *         @arg @ref LL_RTC_BKP_DR25 (*)
03111   *         @arg @ref LL_RTC_BKP_DR26 (*)
03112   *         @arg @ref LL_RTC_BKP_DR27 (*)
03113   *         @arg @ref LL_RTC_BKP_DR28 (*)
03114   *         @arg @ref LL_RTC_BKP_DR29 (*)
03115   *         @arg @ref LL_RTC_BKP_DR30 (*)
03116   *         @arg @ref LL_RTC_BKP_DR31 (*)
03117   *
03118   *         (*) value not defined in all devices.
03119   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
03120   */
03121 __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
03122 {
03123   register uint32_t tmp = 0U;
03124
03125   tmp = (uint32_t)(&(RTCx->BKP0R));
03126   tmp += (BackupRegister * 4U);
03127
03128   /* Read the specified register */
03129   return (*(__IO uint32_t *)tmp);
03130 }
03131
03132 /**
03133   * @}
03134   */
03135 #endif /* RTC_BACKUP_SUPPORT */
03136
03137 /** @defgroup RTC_LL_EF_Calibration Calibration
03138   * @{
03139   */
03140
03141 /**
03142   * @brief  Set Calibration output frequency (1 Hz or 512 Hz)
03143   * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03144   * @rmtoll CR           COE           LL_RTC_CAL_SetOutputFreq\n
03145   *         CR           COSEL         LL_RTC_CAL_SetOutputFreq
03146   * @param  RTCx RTC Instance
03147   * @param  Frequency This parameter can be one of the following values:
03148   *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
03149   *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
03150   *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
03151   * @retval None
03152   */
03153 __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
03154 {
03155   MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
03156 }
03157
03158 /**
03159   * @brief  Get Calibration output frequency (1 Hz or 512 Hz)
03160   * @rmtoll CR           COE           LL_RTC_CAL_GetOutputFreq\n
03161   *         CR           COSEL         LL_RTC_CAL_GetOutputFreq
03162   * @param  RTCx RTC Instance
03163   * @retval Returned value can be one of the following values:
03164   *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
03165   *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
03166   *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
03167   */
03168 __STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
03169 {
03170   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
03171 }
03172
03173 /**
03174   * @brief  Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
03175   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03176   * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
03177   * @rmtoll CALR         CALP          LL_RTC_CAL_SetPulse
03178   * @param  RTCx RTC Instance
03179   * @param  Pulse This parameter can be one of the following values:
03180   *         @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
03181   *         @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
03182   * @retval None
03183   */
03184 __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
03185 {
03186   MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
03187 }
03188
03189 /**
03190   * @brief  Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
03191   * @rmtoll CALR         CALP          LL_RTC_CAL_IsPulseInserted
03192   * @param  RTCx RTC Instance
03193   * @retval State of bit (1 or 0).
03194   */
03195 __STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
03196 {
03197   return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP));
03198 }
03199
03200 /**
03201   * @brief  Set the calibration cycle period
03202   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03203   * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR
03204   * @rmtoll CALR         CALW8         LL_RTC_CAL_SetPeriod\n
03205   *         CALR         CALW16        LL_RTC_CAL_SetPeriod
03206   * @param  RTCx RTC Instance
03207   * @param  Period This parameter can be one of the following values:
03208   *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
03209   *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
03210   *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
03211   * @retval None
03212   */
03213 __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
03214 {
03215   MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
03216 }
03217
03218 /**
03219   * @brief  Get the calibration cycle period
03220   * @rmtoll CALR         CALW8         LL_RTC_CAL_GetPeriod\n
03221   *         CALR         CALW16        LL_RTC_CAL_GetPeriod
03222   * @param  RTCx RTC Instance
03223   * @retval Returned value can be one of the following values:
03224   *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
03225   *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
03226   *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
03227   */
03228 __STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
03229 {
03230   return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
03231 }
03232
03233 /**
03234   * @brief  Set Calibration minus
03235   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03236   * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR
03237   * @rmtoll CALR         CALM          LL_RTC_CAL_SetMinus
03238   * @param  RTCx RTC Instance
03239   * @param  CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
03240   * @retval None
03241   */
03242 __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
03243 {
03244   MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
03245 }
03246
03247 /**
03248   * @brief  Get Calibration minus
03249   * @rmtoll CALR         CALM          LL_RTC_CAL_GetMinus
03250   * @param  RTCx RTC Instance
03251   * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
03252   */
03253 __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
03254 {
03255   return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
03256 }
03257
03258 /**
03259   * @}
03260   */
03261
03262 /** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
03263   * @{
03264   */
03265
03266 /**
03267   * @brief  Get Recalibration pending Flag
03268   * @rmtoll ISR          RECALPF       LL_RTC_IsActiveFlag_RECALP
03269   * @param  RTCx RTC Instance
03270   * @retval State of bit (1 or 0).
03271   */
03272 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
03273 {
03274   return (READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF));
03275 }
03276
03277 #if defined(RTC_TAMPER3_SUPPORT)
03278 /**
03279   * @brief  Get RTC_TAMP3 detection flag
03280   * @rmtoll ISR          TAMP3F        LL_RTC_IsActiveFlag_TAMP3
03281   * @param  RTCx RTC Instance
03282   * @retval State of bit (1 or 0).
03283   */
03284 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
03285 {
03286   return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F));
03287 }
03288 #endif /* RTC_TAMPER3_SUPPORT */
03289
03290 #if defined(RTC_TAMPER2_SUPPORT)
03291 /**
03292   * @brief  Get RTC_TAMP2 detection flag
03293   * @rmtoll ISR          TAMP2F        LL_RTC_IsActiveFlag_TAMP2
03294   * @param  RTCx RTC Instance
03295   * @retval State of bit (1 or 0).
03296   */
03297 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
03298 {
03299   return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F));
03300 }
03301 #endif /* RTC_TAMPER2_SUPPORT */
03302
03303 #if defined(RTC_TAMPER1_SUPPORT)
03304 /**
03305   * @brief  Get RTC_TAMP1 detection flag
03306   * @rmtoll ISR          TAMP1F        LL_RTC_IsActiveFlag_TAMP1
03307   * @param  RTCx RTC Instance
03308   * @retval State of bit (1 or 0).
03309   */
03310 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
03311 {
03312   return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F));
03313 }
03314 #endif /* RTC_TAMPER1_SUPPORT */
03315
03316 /**
03317   * @brief  Get Time-stamp overflow flag
03318   * @rmtoll ISR          TSOVF         LL_RTC_IsActiveFlag_TSOV
03319   * @param  RTCx RTC Instance
03320   * @retval State of bit (1 or 0).
03321   */
03322 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
03323 {
03324   return (READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF));
03325 }
03326
03327 /**
03328   * @brief  Get Time-stamp flag
03329   * @rmtoll ISR          TSF           LL_RTC_IsActiveFlag_TS
03330   * @param  RTCx RTC Instance
03331   * @retval State of bit (1 or 0).
03332   */
03333 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
03334 {
03335   return (READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF));
03336 }
03337
03338 #if defined(RTC_WAKEUP_SUPPORT)
03339 /**
03340   * @brief  Get Wakeup timer flag
03341   * @rmtoll ISR          WUTF          LL_RTC_IsActiveFlag_WUT
03342   * @param  RTCx RTC Instance
03343   * @retval State of bit (1 or 0).
03344   */
03345 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
03346 {
03347   return (READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF));
03348 }
03349 #endif /* RTC_WAKEUP_SUPPORT */
03350
03351 /**
03352   * @brief  Get Alarm B flag
03353   * @rmtoll ISR          ALRBF         LL_RTC_IsActiveFlag_ALRB
03354   * @param  RTCx RTC Instance
03355   * @retval State of bit (1 or 0).
03356   */
03357 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
03358 {
03359   return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF));
03360 }
03361
03362 /**
03363   * @brief  Get Alarm A flag
03364   * @rmtoll ISR          ALRAF         LL_RTC_IsActiveFlag_ALRA
03365   * @param  RTCx RTC Instance
03366   * @retval State of bit (1 or 0).
03367   */
03368 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
03369 {
03370   return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF));
03371 }
03372
03373 #if defined(RTC_TAMPER3_SUPPORT)
03374 /**
03375   * @brief  Clear RTC_TAMP3 detection flag
03376   * @rmtoll ISR          TAMP3F        LL_RTC_ClearFlag_TAMP3
03377   * @param  RTCx RTC Instance
03378   * @retval None
03379   */
03380 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
03381 {
03382   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03383 }
03384 #endif /* RTC_TAMPER3_SUPPORT */
03385
03386 #if defined(RTC_TAMPER2_SUPPORT)
03387 /**
03388   * @brief  Clear RTC_TAMP2 detection flag
03389   * @rmtoll ISR          TAMP2F        LL_RTC_ClearFlag_TAMP2
03390   * @param  RTCx RTC Instance
03391   * @retval None
03392   */
03393 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
03394 {
03395   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03396 }
03397 #endif /* RTC_TAMPER2_SUPPORT */
03398
03399 #if defined(RTC_TAMPER1_SUPPORT)
03400 /**
03401   * @brief  Clear RTC_TAMP1 detection flag
03402   * @rmtoll ISR          TAMP1F        LL_RTC_ClearFlag_TAMP1
03403   * @param  RTCx RTC Instance
03404   * @retval None
03405   */
03406 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
03407 {
03408   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03409 }
03410 #endif /* RTC_TAMPER1_SUPPORT */
03411
03412 /**
03413   * @brief  Clear Time-stamp overflow flag
03414   * @rmtoll ISR          TSOVF         LL_RTC_ClearFlag_TSOV
03415   * @param  RTCx RTC Instance
03416   * @retval None
03417   */
03418 __STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
03419 {
03420   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03421 }
03422
03423 /**
03424   * @brief  Clear Time-stamp flag
03425   * @rmtoll ISR          TSF           LL_RTC_ClearFlag_TS
03426   * @param  RTCx RTC Instance
03427   * @retval None
03428   */
03429 __STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
03430 {
03431   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03432 }
03433
03434 #if defined(RTC_WAKEUP_SUPPORT)
03435 /**
03436   * @brief  Clear Wakeup timer flag
03437   * @rmtoll ISR          WUTF          LL_RTC_ClearFlag_WUT
03438   * @param  RTCx RTC Instance
03439   * @retval None
03440   */
03441 __STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
03442 {
03443   WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03444 }
03445 #endif /* RTC_WAKEUP_SUPPORT */
03446
03447 /**
03448   * @brief  Clear Alarm B flag
03449   * @rmtoll ISR          ALRBF         LL_RTC_ClearFlag_ALRB
03450   * @param  RTCx RTC Instance
03451   * @retval None
03452   */
03453 __STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
03454 {
03455   WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03456 }
03457
03458 /**
03459   * @brief  Clear Alarm A flag
03460   * @rmtoll ISR          ALRAF         LL_RTC_ClearFlag_ALRA
03461   * @param  RTCx RTC Instance
03462   * @retval None
03463   */
03464 __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
03465 {
03466   WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03467 }
03468
03469 /**
03470   * @brief  Get Initialization flag
03471   * @rmtoll ISR          INITF         LL_RTC_IsActiveFlag_INIT
03472   * @param  RTCx RTC Instance
03473   * @retval State of bit (1 or 0).
03474   */
03475 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
03476 {
03477   return (READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF));
03478 }
03479
03480 /**
03481   * @brief  Get Registers synchronization flag
03482   * @rmtoll ISR          RSF           LL_RTC_IsActiveFlag_RS
03483   * @param  RTCx RTC Instance
03484   * @retval State of bit (1 or 0).
03485   */
03486 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
03487 {
03488   return (READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF));
03489 }
03490
03491 /**
03492   * @brief  Clear Registers synchronization flag
03493   * @rmtoll ISR          RSF           LL_RTC_ClearFlag_RS
03494   * @param  RTCx RTC Instance
03495   * @retval None
03496   */
03497 __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
03498 {
03499   WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03500 }
03501
03502 /**
03503   * @brief  Get Initialization status flag
03504   * @rmtoll ISR          INITS         LL_RTC_IsActiveFlag_INITS
03505   * @param  RTCx RTC Instance
03506   * @retval State of bit (1 or 0).
03507   */
03508 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
03509 {
03510   return (READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS));
03511 }
03512
03513 /**
03514   * @brief  Get Shift operation pending flag
03515   * @rmtoll ISR          SHPF          LL_RTC_IsActiveFlag_SHP
03516   * @param  RTCx RTC Instance
03517   * @retval State of bit (1 or 0).
03518   */
03519 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
03520 {
03521   return (READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF));
03522 }
03523
03524 #if defined(RTC_WAKEUP_SUPPORT)
03525 /**
03526   * @brief  Get Wakeup timer write flag
03527   * @rmtoll ISR          WUTWF         LL_RTC_IsActiveFlag_WUTW
03528   * @param  RTCx RTC Instance
03529   * @retval State of bit (1 or 0).
03530   */
03531 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
03532 {
03533   return (READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF));
03534 }
03535 #endif /* RTC_WAKEUP_SUPPORT */
03536
03537 /**
03538   * @brief  Get Alarm B write flag
03539   * @rmtoll ISR          ALRBWF        LL_RTC_IsActiveFlag_ALRBW
03540   * @param  RTCx RTC Instance
03541   * @retval State of bit (1 or 0).
03542   */
03543 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
03544 {
03545   return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF));
03546 }
03547
03548 /**
03549   * @brief  Get Alarm A write flag
03550   * @rmtoll ISR          ALRAWF        LL_RTC_IsActiveFlag_ALRAW
03551   * @param  RTCx RTC Instance
03552   * @retval State of bit (1 or 0).
03553   */
03554 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
03555 {
03556   return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF));
03557 }
03558
03559 /**
03560   * @}
03561   */
03562
03563 /** @defgroup RTC_LL_EF_IT_Management IT_Management
03564   * @{
03565   */
03566
03567 /**
03568   * @brief  Enable Time-stamp interrupt
03569   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03570   * @rmtoll CR           TSIE          LL_RTC_EnableIT_TS
03571   * @param  RTCx RTC Instance
03572   * @retval None
03573   */
03574 __STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
03575 {
03576   SET_BIT(RTCx->CR, RTC_CR_TSIE);
03577 }
03578
03579 /**
03580   * @brief  Disable Time-stamp interrupt
03581   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03582   * @rmtoll CR           TSIE          LL_RTC_DisableIT_TS
03583   * @param  RTCx RTC Instance
03584   * @retval None
03585   */
03586 __STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
03587 {
03588   CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
03589 }
03590
03591 #if defined(RTC_WAKEUP_SUPPORT)
03592 /**
03593   * @brief  Enable Wakeup timer interrupt
03594   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03595   * @rmtoll CR           WUTIE         LL_RTC_EnableIT_WUT
03596   * @param  RTCx RTC Instance
03597   * @retval None
03598   */
03599 __STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
03600 {
03601   SET_BIT(RTCx->CR, RTC_CR_WUTIE);
03602 }
03603
03604 /**
03605   * @brief  Disable Wakeup timer interrupt
03606   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03607   * @rmtoll CR           WUTIE         LL_RTC_DisableIT_WUT
03608   * @param  RTCx RTC Instance
03609   * @retval None
03610   */
03611 __STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
03612 {
03613   CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
03614 }
03615 #endif /* RTC_WAKEUP_SUPPORT */
03616
03617 /**
03618   * @brief  Enable Alarm B interrupt
03619   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03620   * @rmtoll CR           ALRBIE        LL_RTC_EnableIT_ALRB
03621   * @param  RTCx RTC Instance
03622   * @retval None
03623   */
03624 __STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
03625 {
03626   SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
03627 }
03628
03629 /**
03630   * @brief  Disable Alarm B interrupt
03631   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03632   * @rmtoll CR           ALRBIE        LL_RTC_DisableIT_ALRB
03633   * @param  RTCx RTC Instance
03634   * @retval None
03635   */
03636 __STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
03637 {
03638   CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
03639 }
03640
03641 /**
03642   * @brief  Enable Alarm A interrupt
03643   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03644   * @rmtoll CR           ALRAIE        LL_RTC_EnableIT_ALRA
03645   * @param  RTCx RTC Instance
03646   * @retval None
03647   */
03648 __STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
03649 {
03650   SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
03651 }
03652
03653 /**
03654   * @brief  Disable Alarm A interrupt
03655   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03656   * @rmtoll CR           ALRAIE        LL_RTC_DisableIT_ALRA
03657   * @param  RTCx RTC Instance
03658   * @retval None
03659   */
03660 __STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
03661 {
03662   CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
03663 }
03664
03665 /**
03666   * @brief  Enable all Tamper Interrupt
03667   * @rmtoll TAFCR       TAMPIE        LL_RTC_EnableIT_TAMP
03668   * @param  RTCx RTC Instance
03669   * @retval None
03670   */
03671 __STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx)
03672 {
03673   SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPIE);
03674 }
03675
03676 /**
03677   * @brief  Disable all Tamper Interrupt
03678   * @rmtoll TAFCR       TAMPIE        LL_RTC_DisableIT_TAMP
03679   * @param  RTCx RTC Instance
03680   * @retval None
03681   */
03682 __STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx)
03683 {
03684   CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPIE);
03685 }
03686
03687 /**
03688   * @brief  Check if  Time-stamp interrupt is enabled or not
03689   * @rmtoll CR           TSIE          LL_RTC_IsEnabledIT_TS
03690   * @param  RTCx RTC Instance
03691   * @retval State of bit (1 or 0).
03692   */
03693 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
03694 {
03695   return (READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE));
03696 }
03697
03698 #if defined(RTC_WAKEUP_SUPPORT)
03699 /**
03700   * @brief  Check if  Wakeup timer interrupt is enabled or not
03701   * @rmtoll CR           WUTIE         LL_RTC_IsEnabledIT_WUT
03702   * @param  RTCx RTC Instance
03703   * @retval State of bit (1 or 0).
03704   */
03705 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
03706 {
03707   return (READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE));
03708 }
03709 #endif /* RTC_WAKEUP_SUPPORT */
03710
03711 /**
03712   * @brief  Check if  Alarm B interrupt is enabled or not
03713   * @rmtoll CR           ALRBIE        LL_RTC_IsEnabledIT_ALRB
03714   * @param  RTCx RTC Instance
03715   * @retval State of bit (1 or 0).
03716   */
03717 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
03718 {
03719   return (READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE));
03720 }
03721
03722 /**
03723   * @brief  Check if  Alarm A interrupt is enabled or not
03724   * @rmtoll CR           ALRAIE        LL_RTC_IsEnabledIT_ALRA
03725   * @param  RTCx RTC Instance
03726   * @retval State of bit (1 or 0).
03727   */
03728 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
03729 {
03730   return (READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE));
03731 }
03732
03733 /**
03734   * @brief  Check if all the TAMPER interrupts are enabled or not
03735   * @rmtoll TAFCR       TAMPIE        LL_RTC_IsEnabledIT_TAMP
03736   * @param  RTCx RTC Instance
03737   * @retval State of bit (1 or 0).
03738   */
03739 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
03740 {
03741   return (READ_BIT(RTCx->TAFCR,
03742                    RTC_TAFCR_TAMPIE) == (RTC_TAFCR_TAMPIE));
03743 }
03744
03745 /**
03746   * @}
03747   */
03748
03749 #if defined(USE_FULL_LL_DRIVER)
03750 /** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
03751   * @{
03752   */
03753
03754 ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
03755 ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
03756 void        LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
03757 ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
03758 void        LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
03759 ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
03760 void        LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
03761 ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
03762 ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
03763 void        LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
03764 void        LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
03765 ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
03766 ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
03767 ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
03768
03769 /**
03770   * @}
03771   */
03772 #endif /* USE_FULL_LL_DRIVER */
03773
03774 /**
03775   * @}
03776   */
03777
03778 /**
03779   * @}
03780   */
03781
03782 #endif /* defined(RTC) */
03783
03784 /**
03785   * @}
03786   */
03787
03788 #ifdef __cplusplus
03789 }
03790 #endif
03791
03792 #endif /* __STM32F3xx_LL_RTC_H */
03793
03794 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_spi.c Source File

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stm32f3xx_ll_spi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_spi.c
00004   * @author  MCD Application Team
00005   * @brief   SPI LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 #if defined(USE_FULL_LL_DRIVER)
00036
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f3xx_ll_spi.h"
00039 #include "stm32f3xx_ll_bus.h"
00040 #include "stm32f3xx_ll_rcc.h"
00041
00042 #ifdef  USE_FULL_ASSERT
00043 #include "stm32_assert.h"
00044 #else
00045 #define assert_param(expr) ((void)0U)
00046 #endif
00047
00048 /** @addtogroup STM32F3xx_LL_Driver
00049   * @{
00050   */
00051
00052 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4)
00053
00054 /** @addtogroup SPI_LL
00055   * @{
00056   */
00057
00058 /* Private types -------------------------------------------------------------*/
00059 /* Private variables ---------------------------------------------------------*/
00060
00061 /* Private constants ---------------------------------------------------------*/
00062 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
00063   * @{
00064   */
00065 /* SPI registers Masks */
00066 #define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
00067                                             SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
00068                                             SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
00069                                             SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
00070                                             SPI_CR1_BIDIMODE)
00071 /**
00072   * @}
00073   */
00074
00075 /* Private macros ------------------------------------------------------------*/
00076 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
00077   * @{
00078   */
00079 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)    \
00080                                               || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
00081                                               || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
00082                                               || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
00083
00084 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
00085                                 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
00086
00087 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)  \
00088                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
00089                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
00090                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
00091                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
00092                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
00093                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
00094                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
00095                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
00096                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
00097                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
00098                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
00099                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
00100
00101 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
00102                                     || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
00103
00104 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
00105                                  || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
00106
00107 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
00108                                || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
00109                                || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
00110
00111 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)   \
00112                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
00113                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
00114                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
00115                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
00116                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
00117                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
00118                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
00119
00120 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
00121                                     || ((__VALUE__) == LL_SPI_MSB_FIRST))
00122
00123 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
00124                                           || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
00125
00126 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
00127
00128 /**
00129   * @}
00130   */
00131
00132 /* Private function prototypes -----------------------------------------------*/
00133
00134 /* Exported functions --------------------------------------------------------*/
00135 /** @addtogroup SPI_LL_Exported_Functions
00136   * @{
00137   */
00138
00139 /** @addtogroup SPI_LL_EF_Init
00140   * @{
00141   */
00142
00143 /**
00144   * @brief  De-initialize the SPI registers to their default reset values.
00145   * @param  SPIx SPI Instance
00146   * @retval An ErrorStatus enumeration value:
00147   *          - SUCCESS: SPI registers are de-initialized
00148   *          - ERROR: SPI registers are not de-initialized
00149   */
00150 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
00151 {
00152   ErrorStatus status = ERROR;
00153
00154   /* Check the parameters */
00155   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
00156
00157 #if defined(SPI1)
00158   if (SPIx == SPI1)
00159   {
00160     /* Force reset of SPI clock */
00161     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
00162
00163     /* Release reset of SPI clock */
00164     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
00165
00166     status = SUCCESS;
00167   }
00168 #endif /* SPI1 */
00169 #if defined(SPI2)
00170   if (SPIx == SPI2)
00171   {
00172     /* Force reset of SPI clock */
00173     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
00174
00175     /* Release reset of SPI clock */
00176     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
00177
00178     status = SUCCESS;
00179   }
00180 #endif /* SPI2 */
00181 #if defined(SPI3)
00182   if (SPIx == SPI3)
00183   {
00184     /* Force reset of SPI clock */
00185     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
00186
00187     /* Release reset of SPI clock */
00188     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
00189
00190     status = SUCCESS;
00191   }
00192 #endif /* SPI3 */
00193 #if defined(SPI4)
00194   if (SPIx == SPI4)
00195   {
00196     /* Force reset of SPI clock */
00197     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
00198
00199     /* Release reset of SPI clock */
00200     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
00201
00202     status = SUCCESS;
00203   }
00204 #endif /* SPI4 */
00205
00206   return status;
00207 }
00208
00209 /**
00210   * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
00211   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
00212   *         SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00213   * @param  SPIx SPI Instance
00214   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
00215   * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
00216   */
00217 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
00218 {
00219   ErrorStatus status = ERROR;
00220
00221   /* Check the SPI Instance SPIx*/
00222   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
00223
00224   /* Check the SPI parameters from SPI_InitStruct*/
00225   assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
00226   assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
00227   assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
00228   assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
00229   assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
00230   assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
00231   assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
00232   assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
00233   assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
00234
00235   if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
00236   {
00237     /*---------------------------- SPIx CR1 Configuration ------------------------
00238      * Configure SPIx CR1 with parameters:
00239      * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
00240      * - Master/Slave Mode:  SPI_CR1_MSTR bit
00241      * - ClockPolarity:      SPI_CR1_CPOL bit
00242      * - ClockPhase:         SPI_CR1_CPHA bit
00243      * - NSS management:     SPI_CR1_SSM bit
00244      * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
00245      * - BitOrder:           SPI_CR1_LSBFIRST bit
00246      * - CRCCalculation:     SPI_CR1_CRCEN bit
00247      */
00248     MODIFY_REG(SPIx->CR1,
00249                SPI_CR1_CLEAR_MASK,
00250                SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
00251                SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
00252                SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
00253                SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
00254
00255     /*---------------------------- SPIx CR2 Configuration ------------------------
00256      * Configure SPIx CR2 with parameters:
00257      * - DataWidth:          DS[3:0] bits
00258      * - NSS management:     SSOE bit
00259      */
00260     MODIFY_REG(SPIx->CR2,
00261                SPI_CR2_DS | SPI_CR2_SSOE,
00262                SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
00263
00264     /*---------------------------- SPIx CRCPR Configuration ----------------------
00265      * Configure SPIx CRCPR with parameters:
00266      * - CRCPoly:            CRCPOLY[15:0] bits
00267      */
00268     if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
00269     {
00270       assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
00271       LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
00272     }
00273     status = SUCCESS;
00274   }
00275
00276 #if defined (SPI_I2S_SUPPORT)
00277   /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
00278   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
00279 #endif /* SPI_I2S_SUPPORT */
00280   return status;
00281 }
00282
00283 /**
00284   * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
00285   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
00286   * whose fields will be set to default values.
00287   * @retval None
00288   */
00289 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
00290 {
00291   /* Set SPI_InitStruct fields to default values */
00292   SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
00293   SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
00294   SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
00295   SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
00296   SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
00297   SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
00298   SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
00299   SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
00300   SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
00301   SPI_InitStruct->CRCPoly           = 7U;
00302 }
00303
00304 /**
00305   * @}
00306   */
00307
00308 /**
00309   * @}
00310   */
00311
00312 /**
00313   * @}
00314   */
00315
00316 #if defined(SPI_I2S_SUPPORT)
00317 /** @addtogroup I2S_LL
00318   * @{
00319   */
00320
00321 /* Private types -------------------------------------------------------------*/
00322 /* Private variables ---------------------------------------------------------*/
00323 /* Private constants ---------------------------------------------------------*/
00324 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
00325   * @{
00326   */
00327 /* I2S registers Masks */
00328 #define I2S_I2SCFGR_CLEAR_MASK             (SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
00329                                             SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
00330                                             SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )
00331
00332 #define I2S_I2SPR_CLEAR_MASK               0x0002U
00333 /**
00334   * @}
00335   */
00336 /* Private macros ------------------------------------------------------------*/
00337 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
00338   * @{
00339   */
00340
00341 #define IS_LL_I2S_DATAFORMAT(__VALUE__)  (((__VALUE__) == LL_I2S_DATAFORMAT_16B)          \
00342                                        || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
00343                                        || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
00344                                        || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
00345
00346 #define IS_LL_I2S_CPOL(__VALUE__)        (((__VALUE__) == LL_I2S_POLARITY_LOW)  \
00347                                        || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
00348
00349 #define IS_LL_I2S_STANDARD(__VALUE__)    (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)   \
00350                                        || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
00351                                        || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
00352                                        || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
00353                                        || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
00354
00355 #define IS_LL_I2S_MODE(__VALUE__)        (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)  \
00356                                        || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
00357                                        || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
00358                                        || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
00359
00360 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
00361                                        || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
00362
00363 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)    \
00364                                        && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
00365                                        || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
00366
00367 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)  ((__VALUE__) >= 0x2U)
00368
00369 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
00370                                            || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
00371 /**
00372   * @}
00373   */
00374
00375 /* Private function prototypes -----------------------------------------------*/
00376
00377 /* Exported functions --------------------------------------------------------*/
00378 /** @addtogroup I2S_LL_Exported_Functions
00379   * @{
00380   */
00381
00382 /** @addtogroup I2S_LL_EF_Init
00383   * @{
00384   */
00385
00386 /**
00387   * @brief  De-initialize the SPI/I2S registers to their default reset values.
00388   * @param  SPIx SPI Instance
00389   * @retval An ErrorStatus enumeration value:
00390   *          - SUCCESS: SPI registers are de-initialized
00391   *          - ERROR: SPI registers are not de-initialized
00392   */
00393 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
00394 {
00395   return LL_SPI_DeInit(SPIx);
00396 }
00397
00398 /**
00399   * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
00400   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
00401   *         SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00402   * @param  SPIx SPI Instance
00403   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
00404   * @retval An ErrorStatus enumeration value:
00405   *          - SUCCESS: SPI registers are Initialized
00406   *          - ERROR: SPI registers are not Initialized
00407   */
00408 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
00409 {
00410   uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
00411   uint32_t tmp = 0U;
00412   LL_RCC_ClocksTypeDef rcc_clocks;
00413   uint32_t sourceclock = 0U;
00414   ErrorStatus status = ERROR;
00415
00416   /* Check the I2S parameters */
00417   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
00418   assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
00419   assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
00420   assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
00421   assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
00422   assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
00423   assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
00424
00425   if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
00426   {
00427     /*---------------------------- SPIx I2SCFGR Configuration --------------------
00428      * Configure SPIx I2SCFGR with parameters:
00429      * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
00430      * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
00431      * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
00432      * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
00433      */
00434
00435     /* Write to SPIx I2SCFGR */
00436     MODIFY_REG(SPIx->I2SCFGR,
00437                I2S_I2SCFGR_CLEAR_MASK,
00438                I2S_InitStruct->Mode | I2S_InitStruct->Standard |
00439                I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
00440                SPI_I2SCFGR_I2SMOD);
00441
00442     /*---------------------------- SPIx I2SPR Configuration ----------------------
00443      * Configure SPIx I2SPR with parameters:
00444      * - MCLKOutput:    SPI_I2SPR_MCKOE bit
00445      * - AudioFreq:     SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
00446      */
00447
00448     /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
00449      * else, default values are used:  i2sodd = 0U, i2sdiv = 2U.
00450      */
00451     if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
00452     {
00453       /* Check the frame length (For the Prescaler computing)
00454        * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
00455        */
00456       if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
00457       {
00458         /* Packet length is 32 bits */
00459         packetlength = 2U;
00460       }
00461
00462       /* I2S Clock source is System clock: Get System Clock frequency */
00463       LL_RCC_GetSystemClocksFreq(&rcc_clocks);
00464
00465       /* Get the source clock value: based on System Clock value */
00466       sourceclock = rcc_clocks.SYSCLK_Frequency;
00467
00468       /* Compute the Real divider depending on the MCLK output state with a floating point */
00469       if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
00470       {
00471         /* MCLK output is enabled */
00472         tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
00473       }
00474       else
00475       {
00476         /* MCLK output is disabled */
00477         tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
00478       }
00479
00480       /* Remove the floating point */
00481       tmp = tmp / 10U;
00482
00483       /* Check the parity of the divider */
00484       i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
00485
00486       /* Compute the i2sdiv prescaler */
00487       i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
00488
00489       /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
00490       i2sodd = (uint16_t)(i2sodd << 8U);
00491     }
00492
00493     /* Test if the divider is 1 or 0 or greater than 0xFF */
00494     if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
00495     {
00496       /* Set the default values */
00497       i2sdiv = 2U;
00498       i2sodd = 0U;
00499     }
00500
00501     /* Write to SPIx I2SPR register the computed value */
00502     WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
00503
00504     status = SUCCESS;
00505   }
00506   return status;
00507 }
00508
00509 /**
00510   * @brief  Set each @ref LL_I2S_InitTypeDef field to default value.
00511   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
00512   *         whose fields will be set to default values.
00513   * @retval None
00514   */
00515 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
00516 {
00517   /*--------------- Reset I2S init structure parameters values -----------------*/
00518   I2S_InitStruct->Mode              = LL_I2S_MODE_SLAVE_TX;
00519   I2S_InitStruct->Standard          = LL_I2S_STANDARD_PHILIPS;
00520   I2S_InitStruct->DataFormat        = LL_I2S_DATAFORMAT_16B;
00521   I2S_InitStruct->MCLKOutput        = LL_I2S_MCLK_OUTPUT_DISABLE;
00522   I2S_InitStruct->AudioFreq         = LL_I2S_AUDIOFREQ_DEFAULT;
00523   I2S_InitStruct->ClockPolarity     = LL_I2S_POLARITY_LOW;
00524 }
00525
00526 /**
00527   * @brief  Set linear and parity prescaler.
00528   * @note   To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
00529   *         Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
00530   * @param  SPIx SPI Instance
00531   * @param  PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
00532   * @param  PrescalerParity This parameter can be one of the following values:
00533   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
00534   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
00535   * @retval None
00536   */
00537 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
00538 {
00539   /* Check the I2S parameters */
00540   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
00541   assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
00542   assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
00543
00544   /* Write to SPIx I2SPR */
00545   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
00546 }
00547
00548 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
00549 /**
00550   * @brief  Configures the full duplex mode for the I2Sx peripheral using its extension
00551   *         I2Sxext according to the specified parameters in the I2S_InitStruct.
00552   * @note   The structure pointed by I2S_InitStruct parameter should be the same
00553   *         used for the master I2S peripheral. In this case, if the master is
00554   *         configured as transmitter, the slave will be receiver and vice versa.
00555   *         Or you can force a different mode by modifying the field I2S_Mode to the
00556   *         value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration.
00557   * @param  I2Sxext SPI Instance
00558   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
00559   * @retval An ErrorStatus enumeration value:
00560   *          - SUCCESS: I2Sxext registers are Initialized
00561   *          - ERROR: I2Sxext registers are not Initialized
00562   */
00563 ErrorStatus  LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct)
00564 {
00565   uint16_t mode = 0U;
00566   ErrorStatus status = ERROR;
00567
00568   /* Check the I2S parameters */
00569   assert_param(IS_I2S_EXT_ALL_INSTANCE(I2Sxext));
00570   assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
00571   assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
00572   assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
00573   assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
00574
00575   if (LL_I2S_IsEnabled(I2Sxext) == 0x00000000U)
00576   {
00577     /*---------------------------- SPIx I2SCFGR Configuration --------------------
00578      * Configure SPIx I2SCFGR with parameters:
00579      * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
00580      * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
00581      * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
00582      * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
00583      */
00584
00585     /* Reset I2SPR registers */
00586     WRITE_REG(I2Sxext->I2SPR, I2S_I2SPR_CLEAR_MASK);
00587
00588     /* Get the mode to be configured for the extended I2S */
00589     if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_TX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_TX))
00590     {
00591       mode = LL_I2S_MODE_SLAVE_RX;
00592     }
00593     else
00594     {
00595       if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_RX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_RX))
00596       {
00597         mode = LL_I2S_MODE_SLAVE_TX;
00598       }
00599     }
00600
00601     /* Write to SPIx I2SCFGR */
00602     MODIFY_REG(I2Sxext->I2SCFGR,
00603                I2S_I2SCFGR_CLEAR_MASK,
00604                I2S_InitStruct->Standard |
00605                I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
00606                SPI_I2SCFGR_I2SMOD | mode);
00607
00608     status = SUCCESS;
00609   }
00610   return status;
00611 }
00612 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
00613
00614 /**
00615   * @}
00616   */
00617
00618 /**
00619   * @}
00620   */
00621
00622 /**
00623   * @}
00624   */
00625 #endif /* SPI_I2S_SUPPORT */
00626
00627 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) */
00628
00629 /**
00630   * @}
00631   */
00632
00633 #endif /* USE_FULL_LL_DRIVER */
00634
00635 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_spi.h Source File

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stm32f3xx_ll_spi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_spi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SPI LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_SPI_H
00038 #define __STM32F3xx_LL_SPI_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4)
00052
00053 /** @defgroup SPI_LL SPI
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059 /* Private macros ------------------------------------------------------------*/
00060
00061 /* Exported types ------------------------------------------------------------*/
00062 #if defined(USE_FULL_LL_DRIVER)
00063 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
00064   * @{
00065   */
00066
00067 /**
00068   * @brief  SPI Init structures definition
00069   */
00070 typedef struct
00071 {
00072   uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
00073                                          This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
00074
00075                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
00076
00077   uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
00078                                          This parameter can be a value of @ref SPI_LL_EC_MODE.
00079
00080                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
00081
00082   uint32_t DataWidth;               /*!< Specifies the SPI data width.
00083                                          This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
00084
00085                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
00086
00087   uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
00088                                          This parameter can be a value of @ref SPI_LL_EC_POLARITY.
00089
00090                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
00091
00092   uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
00093                                          This parameter can be a value of @ref SPI_LL_EC_PHASE.
00094
00095                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
00096
00097   uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
00098                                          This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
00099
00100                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
00101
00102   uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
00103                                          This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
00104                                          @note The communication clock is derived from the master clock. The slave clock does not need to be set.
00105
00106                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
00107
00108   uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
00109                                          This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
00110
00111                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
00112
00113   uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
00114                                          This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
00115
00116                                          This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
00117
00118   uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
00119                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
00120
00121                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
00122
00123 } LL_SPI_InitTypeDef;
00124
00125 /**
00126   * @}
00127   */
00128 #endif /* USE_FULL_LL_DRIVER */
00129
00130 /* Exported constants --------------------------------------------------------*/
00131 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
00132   * @{
00133   */
00134
00135 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
00136   * @brief    Flags defines which can be used with LL_SPI_ReadReg function
00137   * @{
00138   */
00139 #define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
00140 #define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
00141 #define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
00142 #define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
00143 #define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
00144 #define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
00145 #define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format error flag  */
00146 /**
00147   * @}
00148   */
00149
00150 /** @defgroup SPI_LL_EC_IT IT Defines
00151   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
00152   * @{
00153   */
00154 #define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty interrupt enable */
00155 #define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt enable     */
00156 #define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable               */
00157 /**
00158   * @}
00159   */
00160
00161 /** @defgroup SPI_LL_EC_MODE Operation Mode
00162   * @{
00163   */
00164 #define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
00165 #define LL_SPI_MODE_SLAVE                  0x00000000U                     /*!< Slave configuration   */
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
00171   * @{
00172   */
00173 #define LL_SPI_PROTOCOL_MOTOROLA           0x00000000U               /*!< Motorola mode. Used as default value */
00174 #define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                              */
00175 /**
00176   * @}
00177   */
00178
00179 /** @defgroup SPI_LL_EC_PHASE Clock Phase
00180   * @{
00181   */
00182 #define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is the first data capture edge  */
00183 #define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
00189   * @{
00190   */
00191 #define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
00192 #define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
00198   * @{
00199   */
00200 #define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< BaudRate control equal to fPCLK/2   */
00201 #define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
00202 #define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
00203 #define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
00204 #define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< BaudRate control equal to fPCLK/32  */
00205 #define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/64  */
00206 #define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< BaudRate control equal to fPCLK/128 */
00207 #define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< BaudRate control equal to fPCLK/256 */
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
00213   * @{
00214   */
00215 #define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
00216 #define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/received with the MSB first */
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
00222   * @{
00223   */
00224 #define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
00225 #define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
00226 #define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
00227 #define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
00233   * @{
00234   */
00235 #define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
00236 #define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in Input. Only used in Master mode                */
00237 #define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
00238 /**
00239   * @}
00240   */
00241
00242 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
00243   * @{
00244   */
00245 #define LL_SPI_DATAWIDTH_4BIT              (SPI_CR2_DS_0 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  4 bits */
00246 #define LL_SPI_DATAWIDTH_5BIT              (SPI_CR2_DS_2)                                              /*!< Data length for SPI transfer:  5 bits */
00247 #define LL_SPI_DATAWIDTH_6BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer:  6 bits */
00248 #define LL_SPI_DATAWIDTH_7BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  7 bits */
00249 #define LL_SPI_DATAWIDTH_8BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer:  8 bits */
00250 #define LL_SPI_DATAWIDTH_9BIT              (SPI_CR2_DS_3)                                              /*!< Data length for SPI transfer:  9 bits */
00251 #define LL_SPI_DATAWIDTH_10BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer: 10 bits */
00252 #define LL_SPI_DATAWIDTH_11BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer: 11 bits */
00253 #define LL_SPI_DATAWIDTH_12BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 12 bits */
00254 #define LL_SPI_DATAWIDTH_13BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2)                               /*!< Data length for SPI transfer: 13 bits */
00255 #define LL_SPI_DATAWIDTH_14BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 14 bits */
00256 #define LL_SPI_DATAWIDTH_15BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)                /*!< Data length for SPI transfer: 15 bits */
00257 #define LL_SPI_DATAWIDTH_16BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
00258 /**
00259   * @}
00260   */
00261 #if defined(USE_FULL_LL_DRIVER)
00262
00263 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
00264   * @{
00265   */
00266 #define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U               /*!< CRC calculation disabled */
00267 #define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)           /*!< CRC calculation enabled  */
00268 /**
00269   * @}
00270   */
00271 #endif /* USE_FULL_LL_DRIVER */
00272
00273 /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
00274   * @{
00275   */
00276 #define LL_SPI_CRC_8BIT                    0x00000000U               /*!<  8-bit CRC length */
00277 #define LL_SPI_CRC_16BIT                   (SPI_CR1_CRCL)            /*!< 16-bit CRC length */
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
00283   * @{
00284   */
00285 #define LL_SPI_RX_FIFO_TH_HALF             0x00000000U               /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */
00286 #define LL_SPI_RX_FIFO_TH_QUARTER          (SPI_CR2_FRXTH)           /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit)  */
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
00292   * @{
00293   */
00294 #define LL_SPI_RX_FIFO_EMPTY               0x00000000U                       /*!< FIFO reception empty */
00295 #define LL_SPI_RX_FIFO_QUARTER_FULL        (SPI_SR_FRLVL_0)                  /*!< FIFO reception 1/4   */
00296 #define LL_SPI_RX_FIFO_HALF_FULL           (SPI_SR_FRLVL_1)                  /*!< FIFO reception 1/2   */
00297 #define LL_SPI_RX_FIFO_FULL                (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full  */
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
00303   * @{
00304   */
00305 #define LL_SPI_TX_FIFO_EMPTY               0x00000000U                       /*!< FIFO transmission empty */
00306 #define LL_SPI_TX_FIFO_QUARTER_FULL        (SPI_SR_FTLVL_0)                  /*!< FIFO transmission 1/4   */
00307 #define LL_SPI_TX_FIFO_HALF_FULL           (SPI_SR_FTLVL_1)                  /*!< FIFO transmission 1/2   */
00308 #define LL_SPI_TX_FIFO_FULL                (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full  */
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
00314   * @{
00315   */
00316 #define LL_SPI_DMA_PARITY_EVEN             0x00000000U   /*!< Select DMA parity Even */
00317 #define LL_SPI_DMA_PARITY_ODD              0x00000001U   /*!< Select DMA parity Odd  */
00318
00319 /**
00320   * @}
00321   */
00322
00323 /**
00324   * @}
00325   */
00326
00327 /* Exported macro ------------------------------------------------------------*/
00328 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
00329   * @{
00330   */
00331
00332 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
00333   * @{
00334   */
00335
00336 /**
00337   * @brief  Write a value in SPI register
00338   * @param  __INSTANCE__ SPI Instance
00339   * @param  __REG__ Register to be written
00340   * @param  __VALUE__ Value to be written in the register
00341   * @retval None
00342   */
00343 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00344
00345 /**
00346   * @brief  Read a value in SPI register
00347   * @param  __INSTANCE__ SPI Instance
00348   * @param  __REG__ Register to be read
00349   * @retval Register value
00350   */
00351 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00352 /**
00353   * @}
00354   */
00355
00356 /**
00357   * @}
00358   */
00359
00360 /* Exported functions --------------------------------------------------------*/
00361 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
00362   * @{
00363   */
00364
00365 /** @defgroup SPI_LL_EF_Configuration Configuration
00366   * @{
00367   */
00368
00369 /**
00370   * @brief  Enable SPI peripheral
00371   * @rmtoll CR1          SPE           LL_SPI_Enable
00372   * @param  SPIx SPI Instance
00373   * @retval None
00374   */
00375 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
00376 {
00377   SET_BIT(SPIx->CR1, SPI_CR1_SPE);
00378 }
00379
00380 /**
00381   * @brief  Disable SPI peripheral
00382   * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
00383   * @rmtoll CR1          SPE           LL_SPI_Disable
00384   * @param  SPIx SPI Instance
00385   * @retval None
00386   */
00387 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
00388 {
00389   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
00390 }
00391
00392 /**
00393   * @brief  Check if SPI peripheral is enabled
00394   * @rmtoll CR1          SPE           LL_SPI_IsEnabled
00395   * @param  SPIx SPI Instance
00396   * @retval State of bit (1 or 0).
00397   */
00398 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
00399 {
00400   return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
00401 }
00402
00403 /**
00404   * @brief  Set SPI operation mode to Master or Slave
00405   * @note   This bit should not be changed when communication is ongoing.
00406   * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
00407   *         CR1          SSI           LL_SPI_SetMode
00408   * @param  SPIx SPI Instance
00409   * @param  Mode This parameter can be one of the following values:
00410   *         @arg @ref LL_SPI_MODE_MASTER
00411   *         @arg @ref LL_SPI_MODE_SLAVE
00412   * @retval None
00413   */
00414 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
00415 {
00416   MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
00417 }
00418
00419 /**
00420   * @brief  Get SPI operation mode (Master or Slave)
00421   * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
00422   *         CR1          SSI           LL_SPI_GetMode
00423   * @param  SPIx SPI Instance
00424   * @retval Returned value can be one of the following values:
00425   *         @arg @ref LL_SPI_MODE_MASTER
00426   *         @arg @ref LL_SPI_MODE_SLAVE
00427   */
00428 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
00429 {
00430   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
00431 }
00432
00433 /**
00434   * @brief  Set serial protocol used
00435   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00436   * @rmtoll CR2          FRF           LL_SPI_SetStandard
00437   * @param  SPIx SPI Instance
00438   * @param  Standard This parameter can be one of the following values:
00439   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
00440   *         @arg @ref LL_SPI_PROTOCOL_TI
00441   * @retval None
00442   */
00443 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
00444 {
00445   MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
00446 }
00447
00448 /**
00449   * @brief  Get serial protocol used
00450   * @rmtoll CR2          FRF           LL_SPI_GetStandard
00451   * @param  SPIx SPI Instance
00452   * @retval Returned value can be one of the following values:
00453   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
00454   *         @arg @ref LL_SPI_PROTOCOL_TI
00455   */
00456 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
00457 {
00458   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
00459 }
00460
00461 /**
00462   * @brief  Set clock phase
00463   * @note   This bit should not be changed when communication is ongoing.
00464   *         This bit is not used in SPI TI mode.
00465   * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
00466   * @param  SPIx SPI Instance
00467   * @param  ClockPhase This parameter can be one of the following values:
00468   *         @arg @ref LL_SPI_PHASE_1EDGE
00469   *         @arg @ref LL_SPI_PHASE_2EDGE
00470   * @retval None
00471   */
00472 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
00473 {
00474   MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
00475 }
00476
00477 /**
00478   * @brief  Get clock phase
00479   * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
00480   * @param  SPIx SPI Instance
00481   * @retval Returned value can be one of the following values:
00482   *         @arg @ref LL_SPI_PHASE_1EDGE
00483   *         @arg @ref LL_SPI_PHASE_2EDGE
00484   */
00485 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
00486 {
00487   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
00488 }
00489
00490 /**
00491   * @brief  Set clock polarity
00492   * @note   This bit should not be changed when communication is ongoing.
00493   *         This bit is not used in SPI TI mode.
00494   * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
00495   * @param  SPIx SPI Instance
00496   * @param  ClockPolarity This parameter can be one of the following values:
00497   *         @arg @ref LL_SPI_POLARITY_LOW
00498   *         @arg @ref LL_SPI_POLARITY_HIGH
00499   * @retval None
00500   */
00501 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
00502 {
00503   MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
00504 }
00505
00506 /**
00507   * @brief  Get clock polarity
00508   * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
00509   * @param  SPIx SPI Instance
00510   * @retval Returned value can be one of the following values:
00511   *         @arg @ref LL_SPI_POLARITY_LOW
00512   *         @arg @ref LL_SPI_POLARITY_HIGH
00513   */
00514 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
00515 {
00516   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
00517 }
00518
00519 /**
00520   * @brief  Set baud rate prescaler
00521   * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
00522   * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
00523   * @param  SPIx SPI Instance
00524   * @param  BaudRate This parameter can be one of the following values:
00525   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
00526   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
00527   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
00528   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
00529   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
00530   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
00531   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
00532   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
00533   * @retval None
00534   */
00535 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
00536 {
00537   MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
00538 }
00539
00540 /**
00541   * @brief  Get baud rate prescaler
00542   * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
00543   * @param  SPIx SPI Instance
00544   * @retval Returned value can be one of the following values:
00545   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
00546   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
00547   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
00548   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
00549   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
00550   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
00551   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
00552   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
00553   */
00554 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
00555 {
00556   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
00557 }
00558
00559 /**
00560   * @brief  Set transfer bit order
00561   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00562   * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
00563   * @param  SPIx SPI Instance
00564   * @param  BitOrder This parameter can be one of the following values:
00565   *         @arg @ref LL_SPI_LSB_FIRST
00566   *         @arg @ref LL_SPI_MSB_FIRST
00567   * @retval None
00568   */
00569 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
00570 {
00571   MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
00572 }
00573
00574 /**
00575   * @brief  Get transfer bit order
00576   * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
00577   * @param  SPIx SPI Instance
00578   * @retval Returned value can be one of the following values:
00579   *         @arg @ref LL_SPI_LSB_FIRST
00580   *         @arg @ref LL_SPI_MSB_FIRST
00581   */
00582 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
00583 {
00584   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
00585 }
00586
00587 /**
00588   * @brief  Set transfer direction mode
00589   * @note   For Half-Duplex mode, Rx Direction is set by default.
00590   *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
00591   * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
00592   *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
00593   *         CR1          BIDIOE        LL_SPI_SetTransferDirection
00594   * @param  SPIx SPI Instance
00595   * @param  TransferDirection This parameter can be one of the following values:
00596   *         @arg @ref LL_SPI_FULL_DUPLEX
00597   *         @arg @ref LL_SPI_SIMPLEX_RX
00598   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
00599   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
00600   * @retval None
00601   */
00602 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
00603 {
00604   MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
00605 }
00606
00607 /**
00608   * @brief  Get transfer direction mode
00609   * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
00610   *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
00611   *         CR1          BIDIOE        LL_SPI_GetTransferDirection
00612   * @param  SPIx SPI Instance
00613   * @retval Returned value can be one of the following values:
00614   *         @arg @ref LL_SPI_FULL_DUPLEX
00615   *         @arg @ref LL_SPI_SIMPLEX_RX
00616   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
00617   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
00618   */
00619 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
00620 {
00621   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
00622 }
00623
00624 /**
00625   * @brief  Set frame data width
00626   * @rmtoll CR2          DS            LL_SPI_SetDataWidth
00627   * @param  SPIx SPI Instance
00628   * @param  DataWidth This parameter can be one of the following values:
00629   *         @arg @ref LL_SPI_DATAWIDTH_4BIT
00630   *         @arg @ref LL_SPI_DATAWIDTH_5BIT
00631   *         @arg @ref LL_SPI_DATAWIDTH_6BIT
00632   *         @arg @ref LL_SPI_DATAWIDTH_7BIT
00633   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
00634   *         @arg @ref LL_SPI_DATAWIDTH_9BIT
00635   *         @arg @ref LL_SPI_DATAWIDTH_10BIT
00636   *         @arg @ref LL_SPI_DATAWIDTH_11BIT
00637   *         @arg @ref LL_SPI_DATAWIDTH_12BIT
00638   *         @arg @ref LL_SPI_DATAWIDTH_13BIT
00639   *         @arg @ref LL_SPI_DATAWIDTH_14BIT
00640   *         @arg @ref LL_SPI_DATAWIDTH_15BIT
00641   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
00642   * @retval None
00643   */
00644 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
00645 {
00646   MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
00647 }
00648
00649 /**
00650   * @brief  Get frame data width
00651   * @rmtoll CR2          DS            LL_SPI_GetDataWidth
00652   * @param  SPIx SPI Instance
00653   * @retval Returned value can be one of the following values:
00654   *         @arg @ref LL_SPI_DATAWIDTH_4BIT
00655   *         @arg @ref LL_SPI_DATAWIDTH_5BIT
00656   *         @arg @ref LL_SPI_DATAWIDTH_6BIT
00657   *         @arg @ref LL_SPI_DATAWIDTH_7BIT
00658   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
00659   *         @arg @ref LL_SPI_DATAWIDTH_9BIT
00660   *         @arg @ref LL_SPI_DATAWIDTH_10BIT
00661   *         @arg @ref LL_SPI_DATAWIDTH_11BIT
00662   *         @arg @ref LL_SPI_DATAWIDTH_12BIT
00663   *         @arg @ref LL_SPI_DATAWIDTH_13BIT
00664   *         @arg @ref LL_SPI_DATAWIDTH_14BIT
00665   *         @arg @ref LL_SPI_DATAWIDTH_15BIT
00666   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
00667   */
00668 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
00669 {
00670   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
00671 }
00672
00673 /**
00674   * @brief  Set threshold of RXFIFO that triggers an RXNE event
00675   * @rmtoll CR2          FRXTH         LL_SPI_SetRxFIFOThreshold
00676   * @param  SPIx SPI Instance
00677   * @param  Threshold This parameter can be one of the following values:
00678   *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
00679   *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
00680   * @retval None
00681   */
00682 __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
00683 {
00684   MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
00685 }
00686
00687 /**
00688   * @brief  Get threshold of RXFIFO that triggers an RXNE event
00689   * @rmtoll CR2          FRXTH         LL_SPI_GetRxFIFOThreshold
00690   * @param  SPIx SPI Instance
00691   * @retval Returned value can be one of the following values:
00692   *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
00693   *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
00694   */
00695 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
00696 {
00697   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
00698 }
00699
00700 /**
00701   * @}
00702   */
00703
00704 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
00705   * @{
00706   */
00707
00708 /**
00709   * @brief  Enable CRC
00710   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00711   * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
00712   * @param  SPIx SPI Instance
00713   * @retval None
00714   */
00715 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
00716 {
00717   SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
00718 }
00719
00720 /**
00721   * @brief  Disable CRC
00722   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00723   * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
00724   * @param  SPIx SPI Instance
00725   * @retval None
00726   */
00727 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
00728 {
00729   CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
00730 }
00731
00732 /**
00733   * @brief  Check if CRC is enabled
00734   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00735   * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
00736   * @param  SPIx SPI Instance
00737   * @retval State of bit (1 or 0).
00738   */
00739 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
00740 {
00741   return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
00742 }
00743
00744 /**
00745   * @brief  Set CRC Length
00746   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00747   * @rmtoll CR1          CRCL          LL_SPI_SetCRCWidth
00748   * @param  SPIx SPI Instance
00749   * @param  CRCLength This parameter can be one of the following values:
00750   *         @arg @ref LL_SPI_CRC_8BIT
00751   *         @arg @ref LL_SPI_CRC_16BIT
00752   * @retval None
00753   */
00754 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
00755 {
00756   MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
00757 }
00758
00759 /**
00760   * @brief  Get CRC Length
00761   * @rmtoll CR1          CRCL          LL_SPI_GetCRCWidth
00762   * @param  SPIx SPI Instance
00763   * @retval Returned value can be one of the following values:
00764   *         @arg @ref LL_SPI_CRC_8BIT
00765   *         @arg @ref LL_SPI_CRC_16BIT
00766   */
00767 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
00768 {
00769   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
00770 }
00771
00772 /**
00773   * @brief  Set CRCNext to transfer CRC on the line
00774   * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
00775   * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
00776   * @param  SPIx SPI Instance
00777   * @retval None
00778   */
00779 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
00780 {
00781   SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
00782 }
00783
00784 /**
00785   * @brief  Set polynomial for CRC calculation
00786   * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
00787   * @param  SPIx SPI Instance
00788   * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00789   * @retval None
00790   */
00791 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
00792 {
00793   WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
00794 }
00795
00796 /**
00797   * @brief  Get polynomial for CRC calculation
00798   * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
00799   * @param  SPIx SPI Instance
00800   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00801   */
00802 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
00803 {
00804   return (uint32_t)(READ_REG(SPIx->CRCPR));
00805 }
00806
00807 /**
00808   * @brief  Get Rx CRC
00809   * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
00810   * @param  SPIx SPI Instance
00811   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00812   */
00813 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
00814 {
00815   return (uint32_t)(READ_REG(SPIx->RXCRCR));
00816 }
00817
00818 /**
00819   * @brief  Get Tx CRC
00820   * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
00821   * @param  SPIx SPI Instance
00822   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00823   */
00824 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
00825 {
00826   return (uint32_t)(READ_REG(SPIx->TXCRCR));
00827 }
00828
00829 /**
00830   * @}
00831   */
00832
00833 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
00834   * @{
00835   */
00836
00837 /**
00838   * @brief  Set NSS mode
00839   * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
00840   * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
00841   * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
00842   * @param  SPIx SPI Instance
00843   * @param  NSS This parameter can be one of the following values:
00844   *         @arg @ref LL_SPI_NSS_SOFT
00845   *         @arg @ref LL_SPI_NSS_HARD_INPUT
00846   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
00847   * @retval None
00848   */
00849 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
00850 {
00851   MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
00852   MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
00853 }
00854
00855 /**
00856   * @brief  Get NSS mode
00857   * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
00858   * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
00859   * @param  SPIx SPI Instance
00860   * @retval Returned value can be one of the following values:
00861   *         @arg @ref LL_SPI_NSS_SOFT
00862   *         @arg @ref LL_SPI_NSS_HARD_INPUT
00863   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
00864   */
00865 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
00866 {
00867   register uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
00868   register uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
00869   return (Ssm | Ssoe);
00870 }
00871
00872 /**
00873   * @brief  Enable NSS pulse management
00874   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00875   * @rmtoll CR2          NSSP          LL_SPI_EnableNSSPulseMgt
00876   * @param  SPIx SPI Instance
00877   * @retval None
00878   */
00879 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
00880 {
00881   SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
00882 }
00883
00884 /**
00885   * @brief  Disable NSS pulse management
00886   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00887   * @rmtoll CR2          NSSP          LL_SPI_DisableNSSPulseMgt
00888   * @param  SPIx SPI Instance
00889   * @retval None
00890   */
00891 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
00892 {
00893   CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
00894 }
00895
00896 /**
00897   * @brief  Check if NSS pulse is enabled
00898   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00899   * @rmtoll CR2          NSSP          LL_SPI_IsEnabledNSSPulse
00900   * @param  SPIx SPI Instance
00901   * @retval State of bit (1 or 0).
00902   */
00903 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
00904 {
00905   return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
00906 }
00907
00908 /**
00909   * @}
00910   */
00911
00912 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
00913   * @{
00914   */
00915
00916 /**
00917   * @brief  Check if Rx buffer is not empty
00918   * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
00919   * @param  SPIx SPI Instance
00920   * @retval State of bit (1 or 0).
00921   */
00922 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
00923 {
00924   return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
00925 }
00926
00927 /**
00928   * @brief  Check if Tx buffer is empty
00929   * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
00930   * @param  SPIx SPI Instance
00931   * @retval State of bit (1 or 0).
00932   */
00933 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
00934 {
00935   return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
00936 }
00937
00938 /**
00939   * @brief  Get CRC error flag
00940   * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
00941   * @param  SPIx SPI Instance
00942   * @retval State of bit (1 or 0).
00943   */
00944 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
00945 {
00946   return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
00947 }
00948
00949 /**
00950   * @brief  Get mode fault error flag
00951   * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
00952   * @param  SPIx SPI Instance
00953   * @retval State of bit (1 or 0).
00954   */
00955 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
00956 {
00957   return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
00958 }
00959
00960 /**
00961   * @brief  Get overrun error flag
00962   * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
00963   * @param  SPIx SPI Instance
00964   * @retval State of bit (1 or 0).
00965   */
00966 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
00967 {
00968   return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
00969 }
00970
00971 /**
00972   * @brief  Get busy flag
00973   * @note   The BSY flag is cleared under any one of the following conditions:
00974   * -When the SPI is correctly disabled
00975   * -When a fault is detected in Master mode (MODF bit set to 1)
00976   * -In Master mode, when it finishes a data transmission and no new data is ready to be
00977   * sent
00978   * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
00979   * each data transfer.
00980   * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
00981   * @param  SPIx SPI Instance
00982   * @retval State of bit (1 or 0).
00983   */
00984 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
00985 {
00986   return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
00987 }
00988
00989 /**
00990   * @brief  Get frame format error flag
00991   * @rmtoll SR           FRE           LL_SPI_IsActiveFlag_FRE
00992   * @param  SPIx SPI Instance
00993   * @retval State of bit (1 or 0).
00994   */
00995 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
00996 {
00997   return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
00998 }
00999
01000 /**
01001   * @brief  Get FIFO reception Level
01002   * @rmtoll SR           FRLVL         LL_SPI_GetRxFIFOLevel
01003   * @param  SPIx SPI Instance
01004   * @retval Returned value can be one of the following values:
01005   *         @arg @ref LL_SPI_RX_FIFO_EMPTY
01006   *         @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
01007   *         @arg @ref LL_SPI_RX_FIFO_HALF_FULL
01008   *         @arg @ref LL_SPI_RX_FIFO_FULL
01009   */
01010 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
01011 {
01012   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
01013 }
01014
01015 /**
01016   * @brief  Get FIFO Transmission Level
01017   * @rmtoll SR           FTLVL         LL_SPI_GetTxFIFOLevel
01018   * @param  SPIx SPI Instance
01019   * @retval Returned value can be one of the following values:
01020   *         @arg @ref LL_SPI_TX_FIFO_EMPTY
01021   *         @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
01022   *         @arg @ref LL_SPI_TX_FIFO_HALF_FULL
01023   *         @arg @ref LL_SPI_TX_FIFO_FULL
01024   */
01025 __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
01026 {
01027   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
01028 }
01029
01030 /**
01031   * @brief  Clear CRC error flag
01032   * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
01033   * @param  SPIx SPI Instance
01034   * @retval None
01035   */
01036 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
01037 {
01038   CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
01039 }
01040
01041 /**
01042   * @brief  Clear mode fault error flag
01043   * @note   Clearing this flag is done by a read access to the SPIx_SR
01044   *         register followed by a write access to the SPIx_CR1 register
01045   * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
01046   * @param  SPIx SPI Instance
01047   * @retval None
01048   */
01049 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
01050 {
01051   __IO uint32_t tmpreg;
01052   tmpreg = SPIx->SR;
01053   (void) tmpreg;
01054   tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
01055   (void) tmpreg;
01056 }
01057
01058 /**
01059   * @brief  Clear overrun error flag
01060   * @note   Clearing this flag is done by a read access to the SPIx_DR
01061   *         register followed by a read access to the SPIx_SR register
01062   * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
01063   * @param  SPIx SPI Instance
01064   * @retval None
01065   */
01066 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
01067 {
01068   __IO uint32_t tmpreg;
01069   tmpreg = SPIx->DR;
01070   (void) tmpreg;
01071   tmpreg = SPIx->SR;
01072   (void) tmpreg;
01073 }
01074
01075 /**
01076   * @brief  Clear frame format error flag
01077   * @note   Clearing this flag is done by reading SPIx_SR register
01078   * @rmtoll SR           FRE           LL_SPI_ClearFlag_FRE
01079   * @param  SPIx SPI Instance
01080   * @retval None
01081   */
01082 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
01083 {
01084   __IO uint32_t tmpreg;
01085   tmpreg = SPIx->SR;
01086   (void) tmpreg;
01087 }
01088
01089 /**
01090   * @}
01091   */
01092
01093 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
01094   * @{
01095   */
01096
01097 /**
01098   * @brief  Enable error interrupt
01099   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
01100   * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
01101   * @param  SPIx SPI Instance
01102   * @retval None
01103   */
01104 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
01105 {
01106   SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
01107 }
01108
01109 /**
01110   * @brief  Enable Rx buffer not empty interrupt
01111   * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
01112   * @param  SPIx SPI Instance
01113   * @retval None
01114   */
01115 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
01116 {
01117   SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
01118 }
01119
01120 /**
01121   * @brief  Enable Tx buffer empty interrupt
01122   * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
01123   * @param  SPIx SPI Instance
01124   * @retval None
01125   */
01126 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
01127 {
01128   SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
01129 }
01130
01131 /**
01132   * @brief  Disable error interrupt
01133   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
01134   * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
01135   * @param  SPIx SPI Instance
01136   * @retval None
01137   */
01138 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
01139 {
01140   CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
01141 }
01142
01143 /**
01144   * @brief  Disable Rx buffer not empty interrupt
01145   * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
01146   * @param  SPIx SPI Instance
01147   * @retval None
01148   */
01149 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
01150 {
01151   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
01152 }
01153
01154 /**
01155   * @brief  Disable Tx buffer empty interrupt
01156   * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
01157   * @param  SPIx SPI Instance
01158   * @retval None
01159   */
01160 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
01161 {
01162   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
01163 }
01164
01165 /**
01166   * @brief  Check if error interrupt is enabled
01167   * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
01168   * @param  SPIx SPI Instance
01169   * @retval State of bit (1 or 0).
01170   */
01171 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
01172 {
01173   return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
01174 }
01175
01176 /**
01177   * @brief  Check if Rx buffer not empty interrupt is enabled
01178   * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
01179   * @param  SPIx SPI Instance
01180   * @retval State of bit (1 or 0).
01181   */
01182 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
01183 {
01184   return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
01185 }
01186
01187 /**
01188   * @brief  Check if Tx buffer empty interrupt
01189   * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
01190   * @param  SPIx SPI Instance
01191   * @retval State of bit (1 or 0).
01192   */
01193 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
01194 {
01195   return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
01196 }
01197
01198 /**
01199   * @}
01200   */
01201
01202 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
01203   * @{
01204   */
01205
01206 /**
01207   * @brief  Enable DMA Rx
01208   * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
01209   * @param  SPIx SPI Instance
01210   * @retval None
01211   */
01212 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
01213 {
01214   SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
01215 }
01216
01217 /**
01218   * @brief  Disable DMA Rx
01219   * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
01220   * @param  SPIx SPI Instance
01221   * @retval None
01222   */
01223 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
01224 {
01225   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
01226 }
01227
01228 /**
01229   * @brief  Check if DMA Rx is enabled
01230   * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
01231   * @param  SPIx SPI Instance
01232   * @retval State of bit (1 or 0).
01233   */
01234 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
01235 {
01236   return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
01237 }
01238
01239 /**
01240   * @brief  Enable DMA Tx
01241   * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
01242   * @param  SPIx SPI Instance
01243   * @retval None
01244   */
01245 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
01246 {
01247   SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
01248 }
01249
01250 /**
01251   * @brief  Disable DMA Tx
01252   * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
01253   * @param  SPIx SPI Instance
01254   * @retval None
01255   */
01256 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
01257 {
01258   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
01259 }
01260
01261 /**
01262   * @brief  Check if DMA Tx is enabled
01263   * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
01264   * @param  SPIx SPI Instance
01265   * @retval State of bit (1 or 0).
01266   */
01267 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
01268 {
01269   return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
01270 }
01271
01272 /**
01273   * @brief  Set parity of  Last DMA reception
01274   * @rmtoll CR2          LDMARX        LL_SPI_SetDMAParity_RX
01275   * @param  SPIx SPI Instance
01276   * @param  Parity This parameter can be one of the following values:
01277   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01278   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01279   * @retval None
01280   */
01281 __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
01282 {
01283   MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
01284 }
01285
01286 /**
01287   * @brief  Get parity configuration for  Last DMA reception
01288   * @rmtoll CR2          LDMARX        LL_SPI_GetDMAParity_RX
01289   * @param  SPIx SPI Instance
01290   * @retval Returned value can be one of the following values:
01291   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01292   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01293   */
01294 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
01295 {
01296   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
01297 }
01298
01299 /**
01300   * @brief  Set parity of  Last DMA transmission
01301   * @rmtoll CR2          LDMATX        LL_SPI_SetDMAParity_TX
01302   * @param  SPIx SPI Instance
01303   * @param  Parity This parameter can be one of the following values:
01304   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01305   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01306   * @retval None
01307   */
01308 __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
01309 {
01310   MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
01311 }
01312
01313 /**
01314   * @brief  Get parity configuration for Last DMA transmission
01315   * @rmtoll CR2          LDMATX        LL_SPI_GetDMAParity_TX
01316   * @param  SPIx SPI Instance
01317   * @retval Returned value can be one of the following values:
01318   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01319   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01320   */
01321 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
01322 {
01323   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
01324 }
01325
01326 /**
01327   * @brief  Get the data register address used for DMA transfer
01328   * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
01329   * @param  SPIx SPI Instance
01330   * @retval Address of data register
01331   */
01332 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
01333 {
01334   return (uint32_t) & (SPIx->DR);
01335 }
01336
01337 /**
01338   * @}
01339   */
01340
01341 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
01342   * @{
01343   */
01344
01345 /**
01346   * @brief  Read 8-Bits in the data register
01347   * @rmtoll DR           DR            LL_SPI_ReceiveData8
01348   * @param  SPIx SPI Instance
01349   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
01350   */
01351 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
01352 {
01353   return (uint8_t)(READ_REG(SPIx->DR));
01354 }
01355
01356 /**
01357   * @brief  Read 16-Bits in the data register
01358   * @rmtoll DR           DR            LL_SPI_ReceiveData16
01359   * @param  SPIx SPI Instance
01360   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
01361   */
01362 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
01363 {
01364   return (uint16_t)(READ_REG(SPIx->DR));
01365 }
01366
01367 /**
01368   * @brief  Write 8-Bits in the data register
01369   * @rmtoll DR           DR            LL_SPI_TransmitData8
01370   * @param  SPIx SPI Instance
01371   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
01372   * @retval None
01373   */
01374 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
01375 {
01376   *((__IO uint8_t *)&SPIx->DR) = TxData;
01377 }
01378
01379 /**
01380   * @brief  Write 16-Bits in the data register
01381   * @rmtoll DR           DR            LL_SPI_TransmitData16
01382   * @param  SPIx SPI Instance
01383   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
01384   * @retval None
01385   */
01386 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
01387 {
01388   *((__IO uint16_t *)&SPIx->DR) = TxData;
01389 }
01390
01391 /**
01392   * @}
01393   */
01394 #if defined(USE_FULL_LL_DRIVER)
01395 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
01396   * @{
01397   */
01398
01399 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
01400 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
01401 void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
01402
01403 /**
01404   * @}
01405   */
01406 #endif /* USE_FULL_LL_DRIVER */
01407 /**
01408   * @}
01409   */
01410
01411 /**
01412   * @}
01413   */
01414
01415 #if defined(SPI_I2S_SUPPORT)
01416 /** @defgroup I2S_LL I2S
01417   * @{
01418   */
01419
01420 /* Private variables ---------------------------------------------------------*/
01421 /* Private constants ---------------------------------------------------------*/
01422 /* Private macros ------------------------------------------------------------*/
01423
01424 /* Exported types ------------------------------------------------------------*/
01425 #if defined(USE_FULL_LL_DRIVER)
01426 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
01427   * @{
01428   */
01429
01430 /**
01431   * @brief  I2S Init structure definition
01432   */
01433
01434 typedef struct
01435 {
01436   uint32_t Mode;                    /*!< Specifies the I2S operating mode.
01437                                          This parameter can be a value of @ref I2S_LL_EC_MODE
01438
01439                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
01440
01441   uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.
01442                                          This parameter can be a value of @ref I2S_LL_EC_STANDARD
01443
01444                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
01445
01446
01447   uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.
01448                                          This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
01449
01450                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
01451
01452
01453   uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.
01454                                          This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
01455
01456                                          This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
01457
01458
01459   uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication.
01460                                          This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
01461
01462                                          Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
01463                                          and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
01464
01465
01466   uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.
01467                                          This parameter can be a value of @ref I2S_LL_EC_POLARITY
01468
01469                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
01470
01471 } LL_I2S_InitTypeDef;
01472
01473 /**
01474   * @}
01475   */
01476 #endif /*USE_FULL_LL_DRIVER*/
01477
01478 /* Exported constants --------------------------------------------------------*/
01479 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
01480   * @{
01481   */
01482
01483 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
01484   * @brief    Flags defines which can be used with LL_I2S_ReadReg function
01485   * @{
01486   */
01487 #define LL_I2S_SR_RXNE                     LL_SPI_SR_RXNE            /*!< Rx buffer not empty flag         */
01488 #define LL_I2S_SR_TXE                      LL_SPI_SR_TXE             /*!< Tx buffer empty flag             */
01489 #define LL_I2S_SR_BSY                      LL_SPI_SR_BSY             /*!< Busy flag                        */
01490 #define LL_I2S_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
01491 #define LL_I2S_SR_OVR                      LL_SPI_SR_OVR             /*!< Overrun flag                     */
01492 #define LL_I2S_SR_FRE                      LL_SPI_SR_FRE             /*!< TI mode frame format error flag  */
01493 /**
01494   * @}
01495   */
01496
01497 /** @defgroup SPI_LL_EC_IT IT Defines
01498   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
01499   * @{
01500   */
01501 #define LL_I2S_CR2_RXNEIE                  LL_SPI_CR2_RXNEIE         /*!< Rx buffer not empty interrupt enable */
01502 #define LL_I2S_CR2_TXEIE                   LL_SPI_CR2_TXEIE          /*!< Tx buffer empty interrupt enable     */
01503 #define LL_I2S_CR2_ERRIE                   LL_SPI_CR2_ERRIE          /*!< Error interrupt enable               */
01504 /**
01505   * @}
01506   */
01507
01508 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
01509   * @{
01510   */
01511 #define LL_I2S_DATAFORMAT_16B              0x00000000U                                   /*!< Data length 16 bits, Channel lenght 16bit */
01512 #define LL_I2S_DATAFORMAT_16B_EXTENDED     (SPI_I2SCFGR_CHLEN)                           /*!< Data length 16 bits, Channel lenght 32bit */
01513 #define LL_I2S_DATAFORMAT_24B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)    /*!< Data length 24 bits, Channel lenght 32bit */
01514 #define LL_I2S_DATAFORMAT_32B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)    /*!< Data length 16 bits, Channel lenght 32bit */
01515 /**
01516   * @}
01517   */
01518
01519 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
01520   * @{
01521   */
01522 #define LL_I2S_POLARITY_LOW                0x00000000U               /*!< Clock steady state is low level  */
01523 #define LL_I2S_POLARITY_HIGH               (SPI_I2SCFGR_CKPOL)       /*!< Clock steady state is high level */
01524 /**
01525   * @}
01526   */
01527
01528 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
01529   * @{
01530   */
01531 #define LL_I2S_STANDARD_PHILIPS            0x00000000U                                                         /*!< I2S standard philips                      */
01532 #define LL_I2S_STANDARD_MSB                (SPI_I2SCFGR_I2SSTD_0)                                              /*!< MSB justified standard (left justified)   */
01533 #define LL_I2S_STANDARD_LSB                (SPI_I2SCFGR_I2SSTD_1)                                              /*!< LSB justified standard (right justified)  */
01534 #define LL_I2S_STANDARD_PCM_SHORT          (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)                       /*!< PCM standard, short frame synchronization */
01535 #define LL_I2S_STANDARD_PCM_LONG           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization  */
01536 /**
01537   * @}
01538   */
01539
01540 /** @defgroup I2S_LL_EC_MODE Operation Mode
01541   * @{
01542   */
01543 #define LL_I2S_MODE_SLAVE_TX               0x00000000U                                   /*!< Slave Tx configuration  */
01544 #define LL_I2S_MODE_SLAVE_RX               (SPI_I2SCFGR_I2SCFG_0)                        /*!< Slave Rx configuration  */
01545 #define LL_I2S_MODE_MASTER_TX              (SPI_I2SCFGR_I2SCFG_1)                        /*!< Master Tx configuration */
01546 #define LL_I2S_MODE_MASTER_RX              (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
01547 /**
01548   * @}
01549   */
01550
01551 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
01552   * @{
01553   */
01554 #define LL_I2S_PRESCALER_PARITY_EVEN       0x00000000U               /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
01555 #define LL_I2S_PRESCALER_PARITY_ODD        (SPI_I2SPR_ODD >> 8U)     /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
01556 /**
01557   * @}
01558   */
01559
01560 #if defined(USE_FULL_LL_DRIVER)
01561
01562 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
01563   * @{
01564   */
01565 #define LL_I2S_MCLK_OUTPUT_DISABLE         0x00000000U               /*!< Master clock output is disabled */
01566 #define LL_I2S_MCLK_OUTPUT_ENABLE          (SPI_I2SPR_MCKOE)         /*!< Master clock output is enabled  */
01567 /**
01568   * @}
01569   */
01570
01571 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
01572   * @{
01573   */
01574
01575 #define LL_I2S_AUDIOFREQ_192K              192000U       /*!< Audio Frequency configuration 192000 Hz       */
01576 #define LL_I2S_AUDIOFREQ_96K               96000U        /*!< Audio Frequency configuration  96000 Hz       */
01577 #define LL_I2S_AUDIOFREQ_48K               48000U        /*!< Audio Frequency configuration  48000 Hz       */
01578 #define LL_I2S_AUDIOFREQ_44K               44100U        /*!< Audio Frequency configuration  44100 Hz       */
01579 #define LL_I2S_AUDIOFREQ_32K               32000U        /*!< Audio Frequency configuration  32000 Hz       */
01580 #define LL_I2S_AUDIOFREQ_22K               22050U        /*!< Audio Frequency configuration  22050 Hz       */
01581 #define LL_I2S_AUDIOFREQ_16K               16000U        /*!< Audio Frequency configuration  16000 Hz       */
01582 #define LL_I2S_AUDIOFREQ_11K               11025U        /*!< Audio Frequency configuration  11025 Hz       */
01583 #define LL_I2S_AUDIOFREQ_8K                8000U         /*!< Audio Frequency configuration   8000 Hz       */
01584 #define LL_I2S_AUDIOFREQ_DEFAULT           2U            /*!< Audio Freq not specified. Register I2SDIV = 2 */
01585 /**
01586   * @}
01587   */
01588 #endif /* USE_FULL_LL_DRIVER */
01589
01590 /**
01591   * @}
01592   */
01593
01594 /* Exported macro ------------------------------------------------------------*/
01595 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
01596   * @{
01597   */
01598
01599 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
01600   * @{
01601   */
01602
01603 /**
01604   * @brief  Write a value in I2S register
01605   * @param  __INSTANCE__ I2S Instance
01606   * @param  __REG__ Register to be written
01607   * @param  __VALUE__ Value to be written in the register
01608   * @retval None
01609   */
01610 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
01611
01612 /**
01613   * @brief  Read a value in I2S register
01614   * @param  __INSTANCE__ I2S Instance
01615   * @param  __REG__ Register to be read
01616   * @retval Register value
01617   */
01618 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
01619 /**
01620   * @}
01621   */
01622
01623 /**
01624   * @}
01625   */
01626
01627
01628 /* Exported functions --------------------------------------------------------*/
01629
01630 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
01631   * @{
01632   */
01633
01634 /** @defgroup I2S_LL_EF_Configuration Configuration
01635   * @{
01636   */
01637
01638 /**
01639   * @brief  Select I2S mode and Enable I2S peripheral
01640   * @rmtoll I2SCFGR      I2SMOD        LL_I2S_Enable\n
01641   *         I2SCFGR      I2SE          LL_I2S_Enable
01642   * @param  SPIx SPI Instance
01643   * @retval None
01644   */
01645 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
01646 {
01647   SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
01648 }
01649
01650 /**
01651   * @brief  Disable I2S peripheral
01652   * @rmtoll I2SCFGR      I2SE          LL_I2S_Disable
01653   * @param  SPIx SPI Instance
01654   * @retval None
01655   */
01656 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
01657 {
01658   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
01659 }
01660
01661 /**
01662   * @brief  Check if I2S peripheral is enabled
01663   * @rmtoll I2SCFGR      I2SE          LL_I2S_IsEnabled
01664   * @param  SPIx SPI Instance
01665   * @retval State of bit (1 or 0).
01666   */
01667 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
01668 {
01669   return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
01670 }
01671
01672 /**
01673   * @brief  Set I2S data frame length
01674   * @rmtoll I2SCFGR      DATLEN        LL_I2S_SetDataFormat\n
01675   *         I2SCFGR      CHLEN         LL_I2S_SetDataFormat
01676   * @param  SPIx SPI Instance
01677   * @param  DataFormat This parameter can be one of the following values:
01678   *         @arg @ref LL_I2S_DATAFORMAT_16B
01679   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
01680   *         @arg @ref LL_I2S_DATAFORMAT_24B
01681   *         @arg @ref LL_I2S_DATAFORMAT_32B
01682   * @retval None
01683   */
01684 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
01685 {
01686   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
01687 }
01688
01689 /**
01690   * @brief  Get I2S data frame length
01691   * @rmtoll I2SCFGR      DATLEN        LL_I2S_GetDataFormat\n
01692   *         I2SCFGR      CHLEN         LL_I2S_GetDataFormat
01693   * @param  SPIx SPI Instance
01694   * @retval Returned value can be one of the following values:
01695   *         @arg @ref LL_I2S_DATAFORMAT_16B
01696   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
01697   *         @arg @ref LL_I2S_DATAFORMAT_24B
01698   *         @arg @ref LL_I2S_DATAFORMAT_32B
01699   */
01700 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
01701 {
01702   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
01703 }
01704
01705 /**
01706   * @brief  Set I2S clock polarity
01707   * @rmtoll I2SCFGR      CKPOL         LL_I2S_SetClockPolarity
01708   * @param  SPIx SPI Instance
01709   * @param  ClockPolarity This parameter can be one of the following values:
01710   *         @arg @ref LL_I2S_POLARITY_LOW
01711   *         @arg @ref LL_I2S_POLARITY_HIGH
01712   * @retval None
01713   */
01714 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
01715 {
01716   SET_BIT(SPIx->I2SCFGR, ClockPolarity);
01717 }
01718
01719 /**
01720   * @brief  Get I2S clock polarity
01721   * @rmtoll I2SCFGR      CKPOL         LL_I2S_GetClockPolarity
01722   * @param  SPIx SPI Instance
01723   * @retval Returned value can be one of the following values:
01724   *         @arg @ref LL_I2S_POLARITY_LOW
01725   *         @arg @ref LL_I2S_POLARITY_HIGH
01726   */
01727 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
01728 {
01729   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
01730 }
01731
01732 /**
01733   * @brief  Set I2S standard protocol
01734   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_SetStandard\n
01735   *         I2SCFGR      PCMSYNC       LL_I2S_SetStandard
01736   * @param  SPIx SPI Instance
01737   * @param  Standard This parameter can be one of the following values:
01738   *         @arg @ref LL_I2S_STANDARD_PHILIPS
01739   *         @arg @ref LL_I2S_STANDARD_MSB
01740   *         @arg @ref LL_I2S_STANDARD_LSB
01741   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
01742   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
01743   * @retval None
01744   */
01745 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
01746 {
01747   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
01748 }
01749
01750 /**
01751   * @brief  Get I2S standard protocol
01752   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_GetStandard\n
01753   *         I2SCFGR      PCMSYNC       LL_I2S_GetStandard
01754   * @param  SPIx SPI Instance
01755   * @retval Returned value can be one of the following values:
01756   *         @arg @ref LL_I2S_STANDARD_PHILIPS
01757   *         @arg @ref LL_I2S_STANDARD_MSB
01758   *         @arg @ref LL_I2S_STANDARD_LSB
01759   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
01760   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
01761   */
01762 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
01763 {
01764   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
01765 }
01766
01767 /**
01768   * @brief  Set I2S transfer mode
01769   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_SetTransferMode
01770   * @param  SPIx SPI Instance
01771   * @param  Mode This parameter can be one of the following values:
01772   *         @arg @ref LL_I2S_MODE_SLAVE_TX
01773   *         @arg @ref LL_I2S_MODE_SLAVE_RX
01774   *         @arg @ref LL_I2S_MODE_MASTER_TX
01775   *         @arg @ref LL_I2S_MODE_MASTER_RX
01776   * @retval None
01777   */
01778 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
01779 {
01780   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
01781 }
01782
01783 /**
01784   * @brief  Get I2S transfer mode
01785   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_GetTransferMode
01786   * @param  SPIx SPI Instance
01787   * @retval Returned value can be one of the following values:
01788   *         @arg @ref LL_I2S_MODE_SLAVE_TX
01789   *         @arg @ref LL_I2S_MODE_SLAVE_RX
01790   *         @arg @ref LL_I2S_MODE_MASTER_TX
01791   *         @arg @ref LL_I2S_MODE_MASTER_RX
01792   */
01793 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
01794 {
01795   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
01796 }
01797
01798 /**
01799   * @brief  Set I2S linear prescaler
01800   * @rmtoll I2SPR        I2SDIV        LL_I2S_SetPrescalerLinear
01801   * @param  SPIx SPI Instance
01802   * @param  PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
01803   * @retval None
01804   */
01805 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
01806 {
01807   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
01808 }
01809
01810 /**
01811   * @brief  Get I2S linear prescaler
01812   * @rmtoll I2SPR        I2SDIV        LL_I2S_GetPrescalerLinear
01813   * @param  SPIx SPI Instance
01814   * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
01815   */
01816 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
01817 {
01818   return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
01819 }
01820
01821 /**
01822   * @brief  Set I2S parity prescaler
01823   * @rmtoll I2SPR        ODD           LL_I2S_SetPrescalerParity
01824   * @param  SPIx SPI Instance
01825   * @param  PrescalerParity This parameter can be one of the following values:
01826   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
01827   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
01828   * @retval None
01829   */
01830 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
01831 {
01832   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
01833 }
01834
01835 /**
01836   * @brief  Get I2S parity prescaler
01837   * @rmtoll I2SPR        ODD           LL_I2S_GetPrescalerParity
01838   * @param  SPIx SPI Instance
01839   * @retval Returned value can be one of the following values:
01840   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
01841   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
01842   */
01843 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
01844 {
01845   return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
01846 }
01847
01848 /**
01849   * @brief  Enable the master clock ouput (Pin MCK)
01850   * @rmtoll I2SPR        MCKOE         LL_I2S_EnableMasterClock
01851   * @param  SPIx SPI Instance
01852   * @retval None
01853   */
01854 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
01855 {
01856   SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
01857 }
01858
01859 /**
01860   * @brief  Disable the master clock ouput (Pin MCK)
01861   * @rmtoll I2SPR        MCKOE         LL_I2S_DisableMasterClock
01862   * @param  SPIx SPI Instance
01863   * @retval None
01864   */
01865 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
01866 {
01867   CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
01868 }
01869
01870 /**
01871   * @brief  Check if the master clock ouput (Pin MCK) is enabled
01872   * @rmtoll I2SPR        MCKOE         LL_I2S_IsEnabledMasterClock
01873   * @param  SPIx SPI Instance
01874   * @retval State of bit (1 or 0).
01875   */
01876 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
01877 {
01878   return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
01879 }
01880
01881 /**
01882   * @}
01883   */
01884
01885 /** @defgroup I2S_LL_EF_FLAG FLAG Management
01886   * @{
01887   */
01888
01889 /**
01890   * @brief  Check if Rx buffer is not empty
01891   * @rmtoll SR           RXNE          LL_I2S_IsActiveFlag_RXNE
01892   * @param  SPIx SPI Instance
01893   * @retval State of bit (1 or 0).
01894   */
01895 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
01896 {
01897   return LL_SPI_IsActiveFlag_RXNE(SPIx);
01898 }
01899
01900 /**
01901   * @brief  Check if Tx buffer is empty
01902   * @rmtoll SR           TXE           LL_I2S_IsActiveFlag_TXE
01903   * @param  SPIx SPI Instance
01904   * @retval State of bit (1 or 0).
01905   */
01906 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
01907 {
01908   return LL_SPI_IsActiveFlag_TXE(SPIx);
01909 }
01910
01911 /**
01912   * @brief  Get busy flag
01913   * @rmtoll SR           BSY           LL_I2S_IsActiveFlag_BSY
01914   * @param  SPIx SPI Instance
01915   * @retval State of bit (1 or 0).
01916   */
01917 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
01918 {
01919   return LL_SPI_IsActiveFlag_BSY(SPIx);
01920 }
01921
01922 /**
01923   * @brief  Get overrun error flag
01924   * @rmtoll SR           OVR           LL_I2S_IsActiveFlag_OVR
01925   * @param  SPIx SPI Instance
01926   * @retval State of bit (1 or 0).
01927   */
01928 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
01929 {
01930   return LL_SPI_IsActiveFlag_OVR(SPIx);
01931 }
01932
01933 /**
01934   * @brief  Get underrun error flag
01935   * @rmtoll SR           UDR           LL_I2S_IsActiveFlag_UDR
01936   * @param  SPIx SPI Instance
01937   * @retval State of bit (1 or 0).
01938   */
01939 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
01940 {
01941   return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
01942 }
01943
01944 /**
01945   * @brief  Get frame format error flag
01946   * @rmtoll SR           FRE           LL_I2S_IsActiveFlag_FRE
01947   * @param  SPIx SPI Instance
01948   * @retval State of bit (1 or 0).
01949   */
01950 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
01951 {
01952   return LL_SPI_IsActiveFlag_FRE(SPIx);
01953 }
01954
01955 /**
01956   * @brief  Get channel side flag.
01957   * @note   0: Channel Left has to be transmitted or has been received\n
01958   *         1: Channel Right has to be transmitted or has been received\n
01959   *         It has no significance in PCM mode.
01960   * @rmtoll SR           CHSIDE        LL_I2S_IsActiveFlag_CHSIDE
01961   * @param  SPIx SPI Instance
01962   * @retval State of bit (1 or 0).
01963   */
01964 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
01965 {
01966   return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
01967 }
01968
01969 /**
01970   * @brief  Clear overrun error flag
01971   * @rmtoll SR           OVR           LL_I2S_ClearFlag_OVR
01972   * @param  SPIx SPI Instance
01973   * @retval None
01974   */
01975 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
01976 {
01977   LL_SPI_ClearFlag_OVR(SPIx);
01978 }
01979
01980 /**
01981   * @brief  Clear underrun error flag
01982   * @rmtoll SR           UDR           LL_I2S_ClearFlag_UDR
01983   * @param  SPIx SPI Instance
01984   * @retval None
01985   */
01986 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
01987 {
01988   __IO uint32_t tmpreg;
01989   tmpreg = SPIx->SR;
01990   (void)tmpreg;
01991 }
01992
01993 /**
01994   * @brief  Clear frame format error flag
01995   * @rmtoll SR           FRE           LL_I2S_ClearFlag_FRE
01996   * @param  SPIx SPI Instance
01997   * @retval None
01998   */
01999 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
02000 {
02001   LL_SPI_ClearFlag_FRE(SPIx);
02002 }
02003
02004 /**
02005   * @}
02006   */
02007
02008 /** @defgroup I2S_LL_EF_IT Interrupt Management
02009   * @{
02010   */
02011
02012 /**
02013   * @brief  Enable error IT
02014   * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
02015   * @rmtoll CR2          ERRIE         LL_I2S_EnableIT_ERR
02016   * @param  SPIx SPI Instance
02017   * @retval None
02018   */
02019 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
02020 {
02021   LL_SPI_EnableIT_ERR(SPIx);
02022 }
02023
02024 /**
02025   * @brief  Enable Rx buffer not empty IT
02026   * @rmtoll CR2          RXNEIE        LL_I2S_EnableIT_RXNE
02027   * @param  SPIx SPI Instance
02028   * @retval None
02029   */
02030 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
02031 {
02032   LL_SPI_EnableIT_RXNE(SPIx);
02033 }
02034
02035 /**
02036   * @brief  Enable Tx buffer empty IT
02037   * @rmtoll CR2          TXEIE         LL_I2S_EnableIT_TXE
02038   * @param  SPIx SPI Instance
02039   * @retval None
02040   */
02041 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
02042 {
02043   LL_SPI_EnableIT_TXE(SPIx);
02044 }
02045
02046 /**
02047   * @brief  Disable error IT
02048   * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
02049   * @rmtoll CR2          ERRIE         LL_I2S_DisableIT_ERR
02050   * @param  SPIx SPI Instance
02051   * @retval None
02052   */
02053 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
02054 {
02055   LL_SPI_DisableIT_ERR(SPIx);
02056 }
02057
02058 /**
02059   * @brief  Disable Rx buffer not empty IT
02060   * @rmtoll CR2          RXNEIE        LL_I2S_DisableIT_RXNE
02061   * @param  SPIx SPI Instance
02062   * @retval None
02063   */
02064 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
02065 {
02066   LL_SPI_DisableIT_RXNE(SPIx);
02067 }
02068
02069 /**
02070   * @brief  Disable Tx buffer empty IT
02071   * @rmtoll CR2          TXEIE         LL_I2S_DisableIT_TXE
02072   * @param  SPIx SPI Instance
02073   * @retval None
02074   */
02075 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
02076 {
02077   LL_SPI_DisableIT_TXE(SPIx);
02078 }
02079
02080 /**
02081   * @brief  Check if ERR IT is enabled
02082   * @rmtoll CR2          ERRIE         LL_I2S_IsEnabledIT_ERR
02083   * @param  SPIx SPI Instance
02084   * @retval State of bit (1 or 0).
02085   */
02086 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
02087 {
02088   return LL_SPI_IsEnabledIT_ERR(SPIx);
02089 }
02090
02091 /**
02092   * @brief  Check if RXNE IT is enabled
02093   * @rmtoll CR2          RXNEIE        LL_I2S_IsEnabledIT_RXNE
02094   * @param  SPIx SPI Instance
02095   * @retval State of bit (1 or 0).
02096   */
02097 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
02098 {
02099   return LL_SPI_IsEnabledIT_RXNE(SPIx);
02100 }
02101
02102 /**
02103   * @brief  Check if TXE IT is enabled
02104   * @rmtoll CR2          TXEIE         LL_I2S_IsEnabledIT_TXE
02105   * @param  SPIx SPI Instance
02106   * @retval State of bit (1 or 0).
02107   */
02108 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
02109 {
02110   return LL_SPI_IsEnabledIT_TXE(SPIx);
02111 }
02112
02113 /**
02114   * @}
02115   */
02116
02117 /** @defgroup I2S_LL_EF_DMA DMA Management
02118   * @{
02119   */
02120
02121 /**
02122   * @brief  Enable DMA Rx
02123   * @rmtoll CR2          RXDMAEN       LL_I2S_EnableDMAReq_RX
02124   * @param  SPIx SPI Instance
02125   * @retval None
02126   */
02127 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
02128 {
02129   LL_SPI_EnableDMAReq_RX(SPIx);
02130 }
02131
02132 /**
02133   * @brief  Disable DMA Rx
02134   * @rmtoll CR2          RXDMAEN       LL_I2S_DisableDMAReq_RX
02135   * @param  SPIx SPI Instance
02136   * @retval None
02137   */
02138 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
02139 {
02140   LL_SPI_DisableDMAReq_RX(SPIx);
02141 }
02142
02143 /**
02144   * @brief  Check if DMA Rx is enabled
02145   * @rmtoll CR2          RXDMAEN       LL_I2S_IsEnabledDMAReq_RX
02146   * @param  SPIx SPI Instance
02147   * @retval State of bit (1 or 0).
02148   */
02149 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
02150 {
02151   return LL_SPI_IsEnabledDMAReq_RX(SPIx);
02152 }
02153
02154 /**
02155   * @brief  Enable DMA Tx
02156   * @rmtoll CR2          TXDMAEN       LL_I2S_EnableDMAReq_TX
02157   * @param  SPIx SPI Instance
02158   * @retval None
02159   */
02160 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
02161 {
02162   LL_SPI_EnableDMAReq_TX(SPIx);
02163 }
02164
02165 /**
02166   * @brief  Disable DMA Tx
02167   * @rmtoll CR2          TXDMAEN       LL_I2S_DisableDMAReq_TX
02168   * @param  SPIx SPI Instance
02169   * @retval None
02170   */
02171 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
02172 {
02173   LL_SPI_DisableDMAReq_TX(SPIx);
02174 }
02175
02176 /**
02177   * @brief  Check if DMA Tx is enabled
02178   * @rmtoll CR2          TXDMAEN       LL_I2S_IsEnabledDMAReq_TX
02179   * @param  SPIx SPI Instance
02180   * @retval State of bit (1 or 0).
02181   */
02182 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
02183 {
02184   return LL_SPI_IsEnabledDMAReq_TX(SPIx);
02185 }
02186
02187 /**
02188   * @}
02189   */
02190
02191 /** @defgroup I2S_LL_EF_DATA DATA Management
02192   * @{
02193   */
02194
02195 /**
02196   * @brief  Read 16-Bits in data register
02197   * @rmtoll DR           DR            LL_I2S_ReceiveData16
02198   * @param  SPIx SPI Instance
02199   * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
02200   */
02201 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
02202 {
02203   return LL_SPI_ReceiveData16(SPIx);
02204 }
02205
02206 /**
02207   * @brief  Write 16-Bits in data register
02208   * @rmtoll DR           DR            LL_I2S_TransmitData16
02209   * @param  SPIx SPI Instance
02210   * @param  TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
02211   * @retval None
02212   */
02213 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
02214 {
02215   LL_SPI_TransmitData16(SPIx, TxData);
02216 }
02217
02218 /**
02219   * @}
02220   */
02221
02222 #if defined(USE_FULL_LL_DRIVER)
02223 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
02224   * @{
02225   */
02226
02227 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
02228 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
02229 void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
02230 void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
02231 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
02232 ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct);
02233 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
02234
02235 /**
02236   * @}
02237   */
02238 #endif /* USE_FULL_LL_DRIVER */
02239
02240 /**
02241   * @}
02242   */
02243
02244 /**
02245   * @}
02246   */
02247 #endif /* SPI_I2S_SUPPORT */
02248
02249 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) */
02250
02251 /**
02252   * @}
02253   */
02254
02255 #ifdef __cplusplus
02256 }
02257 #endif
02258
02259 #endif /* __STM32F3xx_LL_SPI_H */
02260
02261 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_system.h Source File

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stm32f3xx_ll_system.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_system.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SYSTEM LL module.
00006   @verbatim
00007   ==============================================================================
00008                      ##### How to use this driver #####
00009   ==============================================================================
00010     [..]
00011     The LL SYSTEM driver contains a set of generic APIs that can be
00012     used by user:
00013       (+) Some of the FLASH features need to be handled in the SYSTEM file.
00014       (+) Access to DBGCMU registers
00015       (+) Access to SYSCFG registers
00016
00017   @endverbatim
00018   ******************************************************************************
00019   * @attention
00020   *
00021   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00022   *
00023   * Redistribution and use in source and binary forms, with or without modification,
00024   * are permitted provided that the following conditions are met:
00025   *   1. Redistributions of source code must retain the above copyright notice,
00026   *      this list of conditions and the following disclaimer.
00027   *   2. Redistributions in binary form must reproduce the above copyright notice,
00028   *      this list of conditions and the following disclaimer in the documentation
00029   *      and/or other materials provided with the distribution.
00030   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00031   *      may be used to endorse or promote products derived from this software
00032   *      without specific prior written permission.
00033   *
00034   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00035   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00036   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00037   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00038   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00039   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00040   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00041   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00042   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00043   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00044   *
00045   ******************************************************************************
00046   */
00047
00048 /* Define to prevent recursive inclusion -------------------------------------*/
00049 #ifndef __STM32F3xx_LL_SYSTEM_H
00050 #define __STM32F3xx_LL_SYSTEM_H
00051
00052 #ifdef __cplusplus
00053 extern "C" {
00054 #endif
00055
00056 /* Includes ------------------------------------------------------------------*/
00057 #include "stm32f3xx.h"
00058
00059 /** @addtogroup STM32F3xx_LL_Driver
00060   * @{
00061   */
00062
00063 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
00064
00065 /** @defgroup SYSTEM_LL SYSTEM
00066   * @{
00067   */
00068
00069 /* Private types -------------------------------------------------------------*/
00070 /* Private variables ---------------------------------------------------------*/
00071
00072 /* Private constants ---------------------------------------------------------*/
00073 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
00074   * @{
00075   */
00076
00077 /* Offset used to access to SYSCFG_CFGR1 and SYSCFG_CFGR3 registers */
00078 #define SYSCFG_OFFSET_CFGR1    0x00000000U
00079 #define SYSCFG_OFFSET_CFGR3    0x00000050U
00080
00081 /* Mask used for TIM breaks functions */
00082 #if defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
00083 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)
00084 #elif defined(SYSCFG_CFGR2_PVD_LOCK) && !defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
00085 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK)
00086 #elif !defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
00087 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK)
00088 #else
00089 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK)
00090 #endif /* SYSCFG_CFGR2_PVD_LOCK && SYSCFG_CFGR2_SRAM_PARITY_LOCK */
00091
00092 /**
00093   * @}
00094   */
00095
00096 /* Private macros ------------------------------------------------------------*/
00097
00098 /* Exported types ------------------------------------------------------------*/
00099 /* Exported constants --------------------------------------------------------*/
00100 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
00101   * @{
00102   */
00103
00104 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
00105   * @{
00106   */
00107 #define LL_SYSCFG_REMAP_FLASH              (uint32_t)0x00000000                                /* Main Flash memory mapped at 0x00000000 */
00108 #define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_CFGR1_MEM_MODE_0                             /* System Flash memory mapped at 0x00000000 */
00109 #define LL_SYSCFG_REMAP_SRAM               (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /* Embedded SRAM mapped at 0x00000000 */
00110 #if defined(FMC_BANK1)
00111 #define LL_SYSCFG_REMAP_FMC                SYSCFG_CFGR1_MEM_MODE_2                             /*<! FMC Bank (Only the first two banks) */
00112 #endif /* FMC_BANK1 */
00113 /**
00114   * @}
00115   */
00116
00117 #if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
00118 /** @defgroup SYSTEM_LL_EC_SPI1_DMA_RMP_RX SYSCFG SPI1 RX/TX DMA1 request REMAP
00119   * @{
00120   */
00121 #define LL_SYSCFG_SPI1RX_RMP_DMA1_CH2    (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U)          /*!< SPI1_RX mapped on DMA1 CH2 */
00122 #define LL_SYSCFG_SPI1RX_RMP_DMA1_CH4    (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0) /*!< SPI1_RX mapped on DMA1 CH4 */
00123 #define LL_SYSCFG_SPI1RX_RMP_DMA1_CH6    (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1) /*!< SPI1_RX mapped on DMA1 CH6 */
00124 #define LL_SYSCFG_SPI1TX_RMP_DMA1_CH3    (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U)          /*!< SPI1_TX mapped on DMA1 CH3 */
00125 #define LL_SYSCFG_SPI1TX_RMP_DMA1_CH5    (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0) /*!< SPI1_TX mapped on DMA1 CH5 */
00126 #define LL_SYSCFG_SPI1TX_RMP_DMA1_CH7    (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1) /*!< SPI1_TX mapped on DMA1 CH7 */
00127 /**
00128   * @}
00129   */
00130 #endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
00131
00132 #if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
00133 /** @defgroup SYSTEM_LL_EC_I2C1_DMA_RMP_RX SYSCFG I2C1 RX/TX DMA1 request REMAP
00134   * @{
00135   */
00136 #define LL_SYSCFG_I2C1RX_RMP_DMA1_CH7    (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U)          /*!< I2C1_RX mapped on DMA1 CH7 */
00137 #define LL_SYSCFG_I2C1RX_RMP_DMA1_CH3    (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0) /*!< I2C1_RX mapped on DMA1 CH3 */
00138 #define LL_SYSCFG_I2C1RX_RMP_DMA1_CH5    (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1) /*!< I2C1_RX mapped on DMA1 CH5 */
00139 #define LL_SYSCFG_I2C1TX_RMP_DMA1_CH6    (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U)          /*!< I2C1_TX mapped on DMA1 CH6 */
00140 #define LL_SYSCFG_I2C1TX_RMP_DMA1_CH2    (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0) /*!< I2C1_TX mapped on DMA1 CH2 */
00141 #define LL_SYSCFG_I2C1TX_RMP_DMA1_CH4    (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1) /*!< I2C1_TX mapped on DMA1 CH4 */
00142 /**
00143   * @}
00144   */
00145
00146 #endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
00147
00148 #if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
00149 /** @defgroup SYSTEM_LL_EC_ADC24_DMA_REMAP SYSCFG ADC DMA request REMAP
00150   * @{
00151   */
00152 #if defined (SYSCFG_CFGR1_ADC24_DMA_RMP)
00153 #define LL_SYSCFG_ADC24_RMP_DMA2_CH12    (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | (uint32_t)0x00000000U)        /*!< ADC24 DMA requests mapped on DMA2 channels 1 and 2 */
00154 #define LL_SYSCFG_ADC24_RMP_DMA2_CH34    (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | SYSCFG_CFGR1_ADC24_DMA_RMP)   /*!< ADC24 DMA requests mapped on DMA2 channels 3 and 4 */
00155 #endif /*SYSCFG_CFGR1_ADC24_DMA_RMP*/
00156 #if defined (SYSCFG_CFGR3_ADC2_DMA_RMP)
00157 #define LL_SYSCFG_ADC2_RMP_DMA1_CH2      (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | (uint32_t)0x00000000U)       /*!< ADC2 mapped on DMA1 channel 2 */
00158 #define LL_SYSCFG_ADC2_RMP_DMA1_CH4      (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_0) /*!< ADC2 mapped on DMA1 channel 4 */
00159 #define LL_SYSCFG_ADC2_RMP_DMA2          (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | (uint32_t)0x00000000U)       /*!< ADC2 mapped on DMA2 */
00160 #define LL_SYSCFG_ADC2_RMP_DMA1          (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_1) /*!< ADC2 mapped on DMA1 */
00161 #endif /*SYSCFG_CFGR3_ADC2_DMA_RMP*/
00162 /**
00163   * @}
00164   */
00165
00166 #endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
00167
00168 /** @defgroup SYSTEM_LL_EC_DAC1_DMA2_REMAP SYSCFG DAC1/2 DMA1/2 request REMAP
00169   * @{
00170   */
00171 #define LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3     ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)              /*!< DAC_CH1 DMA requests mapped on DMA2 channel 3 */
00172 #define LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3     ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP)   /*!< DAC_CH1 DMA requests mapped on DMA1 channel 3 */
00173 #if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
00174 #define LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4    ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U)              /*!< DAC1_OUT2 DMA requests mapped on DMA2 channel 4 */
00175 #define LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4    ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)   /*!< DAC1_OUT2 DMA requests mapped on DMA1 channel 4 */
00176 #endif /*SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP*/
00177 #if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
00178 #define LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5    ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)             /*!< DAC2_OUT1 DMA requests mapped on DMA2 channel 5 */
00179 #define LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5    ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) /*!< DAC2_OUT1 DMA requests mapped on DMA1 channel 5 */
00180 #endif /*SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP*/
00181 #if defined(SYSCFG_CFGR1_DAC2Ch1_DMA_RMP)
00182 #define LL_SYSCFG_DAC2_CH1_RMP_NO           ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)                  /*!< No remap */
00183 #define LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5     ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_DAC2Ch1_DMA_RMP)           /*!< DAC2_CH1 DMA requests mapped on DMA1 channel 5 */
00184 #endif /*SYSCFG_CFGR1_DAC2Ch1_DMA_RMP*/
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup SYSTEM_LL_EC_TIM16_DMA1_REMAP SYSCFG TIM DMA request REMAP
00190   * @{
00191   */
00192 #define LL_SYSCFG_TIM16_RMP_DMA1_CH3        ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | (uint32_t)0x00000000U)                     /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 3 */
00193 #define LL_SYSCFG_TIM16_RMP_DMA1_CH6        ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP)                /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6 */
00194 #define LL_SYSCFG_TIM17_RMP_DMA1_CH1        ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | (uint32_t)0x00000000U)                     /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 1 */
00195 #define LL_SYSCFG_TIM17_RMP_DMA1_CH7        ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP)                /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7 */
00196 #define LL_SYSCFG_TIM6_RMP_DMA2_CH3         ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)               /*!< TIM6 DMA requests mapped on DMA2 channel 3 */
00197 #define LL_SYSCFG_TIM6_RMP_DMA1_CH3         ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP)    /*!< TIM6 DMA requests mapped on DMA1 channel 3 */
00198 #if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
00199 #define LL_SYSCFG_TIM7_RMP_DMA2_CH4         ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U)               /*!< TIM7 DMA requests mapped on DMA2 channel 4 */
00200 #define LL_SYSCFG_TIM7_RMP_DMA1_CH4         ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)    /*!< TIM7 DMA requests mapped on DMA1 channel 4 */
00201 #endif /*SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP*/
00202 #if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
00203 #define LL_SYSCFG_TIM18_RMP_DMA2_CH5        ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)              /*!< TIM18 DMA requests mapped on DMA2 channel 5 */
00204 #define LL_SYSCFG_TIM18_RMP_DMA1_CH5        ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)  /*!< TIM18 DMA requests mapped on DMA1 channel 5 */
00205 #endif /*SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP*/
00206 /**
00207   * @}
00208   */
00209
00210 #if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
00211 /** @defgroup SYSTEM_LL_EC_TIM1_ITR3_RMP_TIM4 SYSCFG TIM REMAP
00212   * @{
00213   */
00214 #if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP)
00215 #define LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO      ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | (uint32_t)0x00000000U)              /*!< TIM1_ITR3 = TIM4_TRGO */
00216 #define LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC       ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | SYSCFG_CFGR1_TIM1_ITR3_RMP)         /*!< TIM1_ITR3 = TIM17_OC */
00217 #endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP */
00218 #if defined(SYSCFG_CFGR1_ENCODER_MODE)
00219 #define LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION ((SYSCFG_CFGR1_ENCODER_MODE << 8U) | (uint32_t)0x00000000U)               /*!< No redirection */
00220 #define LL_SYSCFG_TIM15_ENCODEMODE_TIM2          ((SYSCFG_CFGR1_ENCODER_MODE_0 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_0)       /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
00221 #if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM3)
00222 #define LL_SYSCFG_TIM15_ENCODEMODE_TIM3          ((SYSCFG_CFGR1_ENCODER_MODE_TIM3 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM3) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
00223 #endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM3 */
00224 #if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM4)
00225 #define LL_SYSCFG_TIM15_ENCODEMODE_TIM4          ((SYSCFG_CFGR1_ENCODER_MODE_TIM4 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM4) /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
00226 #endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM4 */
00227 #endif /* SYSCFG_CFGR1_ENCODER_MODE */
00228 /**
00229   * @}
00230   */
00231
00232 #endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */
00233
00234 #if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
00235 /** @defgroup SYSTEM_LL_EC_ADC12_EXT2_RMP_TIM1 SYSCFG ADC Trigger REMAP
00236   * @{
00237   */
00238 #define LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3      ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | (uint32_t)0x00000000U)           /*!< Input trigger of ADC12 regular channel EXT2:Trigger source is TIM1_CC3 */
00239 #define LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO    ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT2_RMP)     /*!< Input trigger of ADC12 regular channel EXT2:Trigger source is TIM20_TRGO */
00240 #define LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2      ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | (uint32_t)0x00000000U)           /*!< Input trigger of ADC12 regular channel EXT3:Trigger source is TIM2_CC2 */
00241 #define LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2   ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT3_RMP)     /*!< Input trigger of ADC12 regular channel EXT3:Trigger source is TIM20_TRGO2 */
00242 #define LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4      ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | (uint32_t)0x00000000U)           /*!< Input trigger of ADC12 regular channel EXT5:Trigger source is TIM4_CC4 */
00243 #define LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1     ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT5_RMP)     /*!< Input trigger of ADC12 regular channel EXT5:Trigger source is TIM20_CC1 */
00244 #define LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO    ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | (uint32_t)0x00000000U)          /*!< Input trigger of ADC12 regular channel EXT13:Trigger source is TIM6_TRGO */
00245 #define LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2    ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT13_RMP)   /*!< Input trigger of ADC12 regular channel EXT13:Trigger source is TIM20_CC2 */
00246 #define LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4     ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | (uint32_t)0x00000000U)          /*!< Input trigger of ADC12 regular channel EXT15:Trigger source is TIM3_CC4 */
00247 #define LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3    ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT15_RMP)   /*!< Input trigger of ADC12 regular channel EXT15:Trigger source is TIM20_CC3 */
00248 #define LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1     ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | (uint32_t)0x00000000U)          /*!< Input trigger of ADC12 regular channel JEXT3:Trigger source is TIM2_CC1 */
00249 #define LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO   ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT3_RMP)   /*!< Input trigger of ADC12 regular channel JEXT3:Trigger source is TIM20_TRGO */
00250 #define LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | (uint32_t)0x00000000U)          /*!< Input trigger of ADC12 regular channel JEXT6:Trigger source is EXTI_LINE_15 */
00251 #define LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2  ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT6_RMP)   /*!< Input trigger of ADC12 regular channel JEXT6:Trigger source is TIM20_TRGO2 */
00252 #define LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1    ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | (uint32_t)0x00000000U)         /*!< Input trigger of ADC12 regular channel JEXT13:Trigger source is TIM3_CC1 */
00253 #define LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4   ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT13_RMP) /*!< Input trigger of ADC12 regular channel JEXT13:Trigger source is TIM20_CC4 */
00254 #define LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2   ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | (uint32_t)0x00000000U)           /*!< Input trigger of ADC34 regular channel EXT5:Trigger source is EXTI_LINE_2 */
00255 #define LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO    ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT5_RMP)     /*!< Input trigger of ADC34 regular channel EXT5:Trigger source is TIM20_TRGO */
00256 #define LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1      ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | (uint32_t)0x00000000U)           /*!< Input trigger of ADC34 regular channel EXT6:Trigger source is TIM4_CC1 */
00257 #define LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2   ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT6_RMP)     /*!< Input trigger of ADC34 regular channel EXT6:Trigger source is TIM20_TRGO2 */
00258 #define LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1     ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | (uint32_t)0x00000000U)          /*!< Input trigger of ADC34 regular channel EXT15:Trigger source is  TIM2_CC1 */
00259 #define LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1    ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT15_RMP)   /*!< Input trigger of ADC34 regular channel EXT15:Trigger source is TIM20_CC1 */
00260 #define LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3     ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | (uint32_t)0x00000000U)          /*!< Input trigger of ADC34 regular channel JEXT5:Trigger source is TIM4_CC3 */
00261 #define LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO   ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT5_RMP)   /*!< Input trigger of ADC34 regular channel JEXT5:Trigger source is TIM20_TRGO */
00262 #define LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3    ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | (uint32_t)0x00000000U)         /*!< Input trigger of ADC34 regular channel JEXT11:Trigger source is TIM1_CC3 */
00263 #define LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT11_RMP) /*!< Input trigger of ADC34 regular channel JEXT11:Trigger source is TIM20_TRGO2 */
00264 #define LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO   ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | (uint32_t)0x00000000U)         /*!< Input trigger of ADC34 regular channel JEXT14:Trigger source is TIM7_TRGO */
00265 #define LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2   ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT14_RMP) /*!< Input trigger of ADC34 regular channel JEXT14:Trigger source is TIM20_CC2 */
00266 /**
00267   * @}
00268   */
00269
00270 #endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
00271
00272 #if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
00273 /** @defgroup SYSTEM_LL_EC_DAC1_TRIG1_REMAP SYSCFG DAC1 Trigger REMAP
00274   * @{
00275   */
00276 #if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP)
00277 #define LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO         (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | (uint32_t)0x00000000U)       /*!< No remap: DAC trigger TRIG1 is TIM8_TRGO */
00278 #define LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO         (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | SYSCFG_CFGR1_DAC1_TRIG1_RMP) /*!< DAC trigger is TIM3_TRGO */
00279 #endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP */
00280 #if defined(SYSCFG_CFGR3_DAC1_TRG3_RMP)
00281 #define LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO        (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | (uint32_t)0x00000000U)        /*!< DAC trigger is TIM15_TRGO */
00282 #define LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG3_RMP)   /*!< DAC trigger is HRTIM1_DAC1_TRIG1 */
00283 #endif /* SYSCFG_CFGR3_DAC1_TRG3_RMP */
00284 #if defined(SYSCFG_CFGR3_DAC1_TRG5_RMP)
00285 #define LL_SYSCFG_DAC1_TRIG5_RMP_NO                (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | (uint32_t)0x00000000U)        /*!<  No remap  */
00286 #define LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG5_RMP)   /*!< DAC trigger is HRTIM1_DAC1_TRIG2 */
00287 #endif /* SYSCFG_CFGR3_DAC1_TRG5_RMP */
00288 /**
00289   * @}
00290   */
00291
00292 #endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */
00293
00294 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
00295   * @{
00296   */
00297 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6     SYSCFG_CFGR1_I2C_PB6_FMP  /*!< I2C PB6 Fast mode plus */
00298 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7     SYSCFG_CFGR1_I2C_PB7_FMP  /*!< I2C PB7 Fast mode plus */
00299 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8     SYSCFG_CFGR1_I2C_PB8_FMP  /*!< I2C PB8 Fast mode plus */
00300 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9     SYSCFG_CFGR1_I2C_PB9_FMP  /*!< I2C PB9 Fast mode plus */
00301 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1    SYSCFG_CFGR1_I2C1_FMP     /*!< I2C1 Fast mode plus    */
00302 #if defined(SYSCFG_CFGR1_I2C2_FMP)
00303 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2    SYSCFG_CFGR1_I2C2_FMP     /*!< I2C2 Fast mode plus    */
00304 #endif /*SYSCFG_CFGR1_I2C2_FMP*/
00305 #if defined(SYSCFG_CFGR1_I2C3_FMP)
00306 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3    SYSCFG_CFGR1_I2C3_FMP     /*!< I2C3 Fast mode plus    */
00307 #endif /*SYSCFG_CFGR1_I2C3_FMP*/
00308 /**
00309   * @}
00310   */
00311
00312 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
00313   * @{
00314   */
00315 #define LL_SYSCFG_EXTI_PORTA               (uint32_t)0U /*!< EXTI PORT A  */
00316 #define LL_SYSCFG_EXTI_PORTB               (uint32_t)1U /*!< EXTI PORT B  */
00317 #define LL_SYSCFG_EXTI_PORTC               (uint32_t)2U /*!< EXTI PORT C  */
00318 #define LL_SYSCFG_EXTI_PORTD               (uint32_t)3U /*!< EXTI PORT D  */
00319 #if defined(GPIOE)
00320 #define LL_SYSCFG_EXTI_PORTE               (uint32_t)4U /*!< EXTI PORT E  */
00321 #endif /* GPIOE */
00322 #define LL_SYSCFG_EXTI_PORTF               (uint32_t)5U /*!< EXTI PORT F  */
00323 #if defined(GPIOG)
00324 #define LL_SYSCFG_EXTI_PORTG               (uint32_t)6U /*!< EXTI PORT G  */
00325 #endif /* GPIOG */
00326 #if defined(GPIOH)
00327 #define LL_SYSCFG_EXTI_PORTH               (uint32_t)7U /*!< EXTI PORT H  */
00328 #endif /* GPIOH */
00329 /**
00330   * @}
00331   */
00332
00333 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
00334   * @{
00335   */
00336 #define LL_SYSCFG_EXTI_LINE0               (uint32_t)(0x000FU << 16U | 0U)  /* EXTI_POSITION_0  | EXTICR[0] */
00337 #define LL_SYSCFG_EXTI_LINE1               (uint32_t)(0x00F0U << 16U | 0U)  /* EXTI_POSITION_4  | EXTICR[0] */
00338 #define LL_SYSCFG_EXTI_LINE2               (uint32_t)(0x0F00U << 16U | 0U)  /* EXTI_POSITION_8  | EXTICR[0] */
00339 #define LL_SYSCFG_EXTI_LINE3               (uint32_t)(0xF000U << 16U | 0U)  /* EXTI_POSITION_12 | EXTICR[0] */
00340 #define LL_SYSCFG_EXTI_LINE4               (uint32_t)(0x000FU << 16U | 1U)  /* EXTI_POSITION_0  | EXTICR[1] */
00341 #define LL_SYSCFG_EXTI_LINE5               (uint32_t)(0x00F0U << 16U | 1U)  /* EXTI_POSITION_4  | EXTICR[1] */
00342 #define LL_SYSCFG_EXTI_LINE6               (uint32_t)(0x0F00U << 16U | 1U)  /* EXTI_POSITION_8  | EXTICR[1] */
00343 #define LL_SYSCFG_EXTI_LINE7               (uint32_t)(0xF000U << 16U | 1U)  /* EXTI_POSITION_12 | EXTICR[1] */
00344 #define LL_SYSCFG_EXTI_LINE8               (uint32_t)(0x000FU << 16U | 2U)  /* EXTI_POSITION_0  | EXTICR[2] */
00345 #define LL_SYSCFG_EXTI_LINE9               (uint32_t)(0x00F0U << 16U | 2U)  /* EXTI_POSITION_4  | EXTICR[2] */
00346 #define LL_SYSCFG_EXTI_LINE10              (uint32_t)(0x0F00U << 16U | 2U)  /* EXTI_POSITION_8  | EXTICR[2] */
00347 #define LL_SYSCFG_EXTI_LINE11              (uint32_t)(0xF000U << 16U | 2U)  /* EXTI_POSITION_12 | EXTICR[2] */
00348 #define LL_SYSCFG_EXTI_LINE12              (uint32_t)(0x000FU << 16U | 3U)  /* EXTI_POSITION_0  | EXTICR[3] */
00349 #define LL_SYSCFG_EXTI_LINE13              (uint32_t)(0x00F0U << 16U | 3U)  /* EXTI_POSITION_4  | EXTICR[3] */
00350 #define LL_SYSCFG_EXTI_LINE14              (uint32_t)(0x0F00U << 16U | 3U)  /* EXTI_POSITION_8  | EXTICR[3] */
00351 #define LL_SYSCFG_EXTI_LINE15              (uint32_t)(0xF000U << 16U | 3U)  /* EXTI_POSITION_12 | EXTICR[3] */
00352 /**
00353   * @}
00354   */
00355
00356 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
00357   * @{
00358   */
00359 #if defined(SYSCFG_CFGR2_PVD_LOCK)
00360 #define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVD_LOCK           /*!< Enables and locks the PVD connection with TIMx Break Input and also the PVDE and PLS bits of the Power Control Interface */
00361 #endif /*SYSCFG_CFGR2_PVD_LOCK*/
00362 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
00363 #define LL_SYSCFG_TIMBREAK_SRAM_PARITY     SYSCFG_CFGR2_SRAM_PARITY_LOCK   /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
00364 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
00365 #define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_LOCKUP_LOCK        /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMx */
00366 /**
00367   * @}
00368   */
00369
00370 #if defined(SYSCFG_RCR_PAGE0)
00371 /** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCM SRAM WRP
00372   * @{
00373   */
00374 #define LL_SYSCFG_CCMSRAMWRP_PAGE0         SYSCFG_RCR_PAGE0  /*!< ICODE SRAM Write protection page 0  */
00375 #define LL_SYSCFG_CCMSRAMWRP_PAGE1         SYSCFG_RCR_PAGE1  /*!< ICODE SRAM Write protection page 1  */
00376 #define LL_SYSCFG_CCMSRAMWRP_PAGE2         SYSCFG_RCR_PAGE2  /*!< ICODE SRAM Write protection page 2  */
00377 #define LL_SYSCFG_CCMSRAMWRP_PAGE3         SYSCFG_RCR_PAGE3  /*!< ICODE SRAM Write protection page 3  */
00378 #if defined(SYSCFG_RCR_PAGE4)
00379 #define LL_SYSCFG_CCMSRAMWRP_PAGE4         SYSCFG_RCR_PAGE4  /*!< ICODE SRAM Write protection page 4  */
00380 #define LL_SYSCFG_CCMSRAMWRP_PAGE5         SYSCFG_RCR_PAGE5  /*!< ICODE SRAM Write protection page 5  */
00381 #define LL_SYSCFG_CCMSRAMWRP_PAGE6         SYSCFG_RCR_PAGE6  /*!< ICODE SRAM Write protection page 6  */
00382 #define LL_SYSCFG_CCMSRAMWRP_PAGE7         SYSCFG_RCR_PAGE7  /*!< ICODE SRAM Write protection page 7  */
00383 #endif
00384 #if defined(SYSCFG_RCR_PAGE8)
00385 #define LL_SYSCFG_CCMSRAMWRP_PAGE8         SYSCFG_RCR_PAGE8  /*!< ICODE SRAM Write protection page 8  */
00386 #define LL_SYSCFG_CCMSRAMWRP_PAGE9         SYSCFG_RCR_PAGE9  /*!< ICODE SRAM Write protection page 9  */
00387 #define LL_SYSCFG_CCMSRAMWRP_PAGE10        SYSCFG_RCR_PAGE10 /*!< ICODE SRAM Write protection page 10 */
00388 #define LL_SYSCFG_CCMSRAMWRP_PAGE11        SYSCFG_RCR_PAGE11 /*!< ICODE SRAM Write protection page 11 */
00389 #define LL_SYSCFG_CCMSRAMWRP_PAGE12        SYSCFG_RCR_PAGE12 /*!< ICODE SRAM Write protection page 12 */
00390 #define LL_SYSCFG_CCMSRAMWRP_PAGE13        SYSCFG_RCR_PAGE13 /*!< ICODE SRAM Write protection page 13 */
00391 #define LL_SYSCFG_CCMSRAMWRP_PAGE14        SYSCFG_RCR_PAGE14 /*!< ICODE SRAM Write protection page 14 */
00392 #define LL_SYSCFG_CCMSRAMWRP_PAGE15        SYSCFG_RCR_PAGE15 /*!< ICODE SRAM Write protection page 15 */
00393 #endif
00394 /**
00395   * @}
00396   */
00397
00398 #endif /* SYSCFG_RCR_PAGE0 */
00399
00400 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
00401   * @{
00402   */
00403 #define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
00404 #define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
00405 #define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
00406 #define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
00407 #define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
00408 /**
00409   * @}
00410   */
00411
00412 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
00413   * @{
00414   */
00415 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1_FZ_DBG_TIM2_STOP          /*!< TIM2 counter stopped when core is halted */
00416 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
00417 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1_FZ_DBG_TIM3_STOP          /*!< TIM3 counter stopped when core is halted */
00418 #endif /*DBGMCU_APB1_FZ_DBG_TIM3_STOP*/
00419 #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
00420 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1_FZ_DBG_TIM4_STOP          /*!< TIM4 counter stopped when core is halted */
00421 #endif /*DBGMCU_APB1_FZ_DBG_TIM4_STOP*/
00422 #if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
00423 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1_FZ_DBG_TIM5_STOP          /*!< TIM5 counter stopped when core is halted */
00424 #endif /*DBGMCU_APB1_FZ_DBG_TIM5_STOP*/
00425 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1_FZ_DBG_TIM6_STOP          /*!< TIM6 counter stopped when core is halted */
00426 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
00427 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1_FZ_DBG_TIM7_STOP          /*!< TIM7 counter stopped when core is halted */
00428 #endif /*DBGMCU_APB1_FZ_DBG_TIM7_STOP*/
00429 #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
00430 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_APB1_FZ_DBG_TIM12_STOP         /*!< TIM12 counter stopped when core is halted */
00431 #endif /*DBGMCU_APB1_FZ_DBG_TIM12_STOP*/
00432 #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
00433 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_APB1_FZ_DBG_TIM13_STOP         /*!< TIM13 counter stopped when core is halted */
00434 #endif /*DBGMCU_APB1_FZ_DBG_TIM13_STOP*/
00435 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
00436 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_APB1_FZ_DBG_TIM14_STOP         /*!< TIM14 counter stopped when core is halted */
00437 #endif /*DBGMCU_APB1_FZ_DBG_TIM14_STOP*/
00438 #if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
00439 #define LL_DBGMCU_APB1_GRP1_TIM18_STOP     DBGMCU_APB1_FZ_DBG_TIM18_STOP         /*!< TIM18 counter stopped when core is halted */
00440 #endif /*DBGMCU_APB1_FZ_DBG_TIM18_STOP*/
00441 #define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1_FZ_DBG_RTC_STOP           /*!< RTC counter stopped when core is halted */
00442 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1_FZ_DBG_WWDG_STOP          /*!< Debug Window Watchdog stopped when Core is halted */
00443 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1_FZ_DBG_IWDG_STOP          /*!< Debug Independent Watchdog stopped when Core is halted */
00444 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
00445 #if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
00446 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
00447 #endif /*DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT*/
00448 #if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
00449 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
00450 #endif /*DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT*/
00451 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
00452 #define LL_DBGMCU_APB1_GRP1_CAN_STOP       DBGMCU_APB1_FZ_DBG_CAN_STOP            /*!< CAN debug stopped when Core is halted  */
00453 #endif /*DBGMCU_APB1_FZ_DBG_CAN_STOP*/
00454 /**
00455   * @}
00456   */
00457
00458 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
00459   * @{
00460   */
00461 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
00462 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2_FZ_DBG_TIM1_STOP   /*!< TIM1 counter stopped when core is halted */
00463 #endif /*DBGMCU_APB2_FZ_DBG_TIM1_STOP*/
00464 #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
00465 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2_FZ_DBG_TIM8_STOP   /*!< TIM8 counter stopped when core is halted */
00466 #endif /*DBGMCU_APB2_FZ_DBG_TIM8_STOP*/
00467 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_APB2_FZ_DBG_TIM15_STOP  /*!< TIM15 counter stopped when core is halted */
00468 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_APB2_FZ_DBG_TIM16_STOP  /*!< TIM16 counter stopped when core is halted */
00469 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_APB2_FZ_DBG_TIM17_STOP  /*!< TIM17 counter stopped when core is halted */
00470 #if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
00471 #define LL_DBGMCU_APB2_GRP1_TIM19_STOP     DBGMCU_APB2_FZ_DBG_TIM19_STOP  /*!< TIM19 counter stopped when core is halted */
00472 #endif /*DBGMCU_APB2_FZ_DBG_TIM19_STOP*/
00473 #if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
00474 #define LL_DBGMCU_APB2_GRP1_TIM20_STOP     DBGMCU_APB2_FZ_DBG_TIM20_STOP  /*!< TIM20 counter stopped when core is halted */
00475 #endif /*DBGMCU_APB2_FZ_DBG_TIM20_STOP*/
00476 #if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
00477 #define LL_DBGMCU_APB2_GRP1_HRTIM1_STOP    DBGMCU_APB2_FZ_DBG_HRTIM1_STOP /*!< HRTIM1 counter stopped when core is halted */
00478 #endif /*DBGMCU_APB2_FZ_DBG_HRTIM1_STOP*/
00479 /**
00480   * @}
00481   */
00482
00483 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
00484   * @{
00485   */
00486 #define LL_FLASH_LATENCY_0                 0x00000000U             /*!< FLASH Zero Latency cycle */
00487 #define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_0     /*!< FLASH One Latency cycle */
00488 #define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_1     /*!< FLASH Two Latency cycles */
00489 /**
00490   * @}
00491   */
00492
00493 /**
00494   * @}
00495   */
00496
00497 /* Exported macro ------------------------------------------------------------*/
00498
00499 /* Exported functions --------------------------------------------------------*/
00500 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
00501   * @{
00502   */
00503
00504 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
00505   * @{
00506   */
00507
00508 /**
00509   * @brief  Set memory mapping at address 0x00000000
00510   * @rmtoll SYSCFG_CFGR1 MEM_MODE      LL_SYSCFG_SetRemapMemory
00511   * @param  Memory This parameter can be one of the following values:
00512   *         @arg @ref LL_SYSCFG_REMAP_FLASH
00513   *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
00514   *         @arg @ref LL_SYSCFG_REMAP_SRAM
00515   *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
00516   *
00517   *         (*) value not defined in all devices.
00518   * @retval None
00519   */
00520 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
00521 {
00522   MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
00523 }
00524
00525 /**
00526   * @brief  Get memory mapping at address 0x00000000
00527   * @rmtoll SYSCFG_CFGR1 MEM_MODE      LL_SYSCFG_GetRemapMemory
00528   * @retval Returned value can be one of the following values:
00529   *         @arg @ref LL_SYSCFG_REMAP_FLASH
00530   *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
00531   *         @arg @ref LL_SYSCFG_REMAP_SRAM
00532   *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
00533   *
00534   *         (*) value not defined in all devices.
00535   */
00536 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
00537 {
00538   return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
00539 }
00540
00541 #if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
00542 /**
00543   * @brief  Set DMA request remapping bits for SPI
00544   * @rmtoll SYSCFG_CFGR3 SPI1_RX_DMA_RMP  LL_SYSCFG_SetRemapDMA_SPI\n
00545   *         SYSCFG_CFGR3 SPI1_TX_DMA_RMP  LL_SYSCFG_SetRemapDMA_SPI
00546   * @param  Remap This parameter can be one of the following values:
00547   *         @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH2
00548   *         @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH4
00549   *         @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH6
00550   *         @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH3
00551   *         @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH5
00552   *         @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH7
00553   * @retval None
00554   */
00555 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)
00556 {
00557   MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
00558 }
00559 #endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
00560
00561 #if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
00562 /**
00563   * @brief  Set DMA request remapping bits for I2C
00564   * @rmtoll SYSCFG_CFGR3 I2C1_RX_DMA_RMP  LL_SYSCFG_SetRemapDMA_I2C\n
00565   *         SYSCFG_CFGR3 I2C1_TX_DMA_RMP  LL_SYSCFG_SetRemapDMA_I2C
00566   * @param  Remap This parameter can be one of the following values:
00567   *         @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH7
00568   *         @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH3
00569   *         @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH5
00570   *         @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH6
00571   *         @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH2
00572   *         @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH4
00573   * @retval None
00574   */
00575 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)
00576 {
00577   MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
00578 }
00579 #endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
00580
00581 #if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
00582 /**
00583   * @brief  Set DMA request remapping bits for ADC
00584   * @rmtoll SYSCFG_CFGR1 ADC24_DMA_RMP  LL_SYSCFG_SetRemapDMA_ADC\n
00585   *         SYSCFG_CFGR3 ADC2_DMA_RMP   LL_SYSCFG_SetRemapDMA_ADC
00586   * @param  Remap This parameter can be one of the following values:
00587   *         @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH12 (*)
00588   *         @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH34 (*)
00589   *         @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH2 (*)
00590   *         @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH4 (*)
00591   *         @arg @ref LL_SYSCFG_ADC2_RMP_DMA2 (*)
00592   *         @arg @ref LL_SYSCFG_ADC2_RMP_DMA1 (*)
00593   *
00594   *         (*) value not defined in all devices.
00595   * @retval None
00596   */
00597 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)
00598 {
00599   __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
00600   MODIFY_REG(*reg, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FFFFU));
00601 }
00602 #endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
00603
00604 /**
00605   * @brief  Set DMA request remapping bits for DAC
00606   * @rmtoll SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP  LL_SYSCFG_SetRemapDMA_DAC\n
00607   *         SYSCFG_CFGR1 DAC2Ch1_DMA_RMP      LL_SYSCFG_SetRemapDMA_DAC
00608   * @param  Remap This parameter can be one of the following values:
00609   *         @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3
00610   *         @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3
00611   *         @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 (*)
00612   *         @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 (*)
00613   *         @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 (*)
00614   *         @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 (*)
00615   *         @arg @ref LL_SYSCFG_DAC2_CH1_RMP_NO (*)
00616   *         @arg @ref LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 (*)
00617   *
00618   *         (*) value not defined in all devices.
00619   * @retval None
00620   */
00621 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_DAC(uint32_t Remap)
00622 {
00623   MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
00624 }
00625
00626 /**
00627   * @brief  Set DMA request remapping bits for TIM
00628   * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP        LL_SYSCFG_SetRemapDMA_TIM\n
00629   *         SYSCFG_CFGR1 TIM17_DMA_RMP        LL_SYSCFG_SetRemapDMA_TIM\n
00630   *         SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP  LL_SYSCFG_SetRemapDMA_TIM\n
00631   *         SYSCFG_CFGR1 TIM7DAC1Ch2_DMA_RMP  LL_SYSCFG_SetRemapDMA_TIM\n
00632   *         SYSCFG_CFGR1 TIM18DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
00633   * @param  Remap This parameter can be a combination of the following values:
00634   *         @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 or @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6
00635   *         @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 or @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7
00636   *         @arg @ref LL_SYSCFG_TIM6_RMP_DMA2_CH3 or @ref LL_SYSCFG_TIM6_RMP_DMA1_CH3
00637   *         @arg @ref LL_SYSCFG_TIM7_RMP_DMA2_CH4 or @ref LL_SYSCFG_TIM7_RMP_DMA1_CH4 (*)
00638   *         @arg @ref LL_SYSCFG_TIM18_RMP_DMA2_CH5 or @ref LL_SYSCFG_TIM18_RMP_DMA1_CH5 (*)
00639   *
00640   *         (*) value not defined in all devices.
00641   * @retval None
00642   */
00643 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)
00644 {
00645   MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
00646 }
00647
00648 #if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
00649 /**
00650   * @brief  Set Timer input remap
00651   * @rmtoll SYSCFG_CFGR1 TIM1_ITR3_RMP  LL_SYSCFG_SetRemapInput_TIM\n
00652   *         SYSCFG_CFGR1 ENCODER_MODE   LL_SYSCFG_SetRemapInput_TIM
00653   * @param  Remap This parameter can be one of the following values:
00654   *         @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO (*)
00655   *         @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC (*)
00656   *         @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION (*)
00657   *         @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM2 (*)
00658   *         @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM3 (*)
00659   *         @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM4 (*)
00660   *
00661   *         (*) value not defined in all devices.
00662   * @retval None
00663   */
00664 __STATIC_INLINE void LL_SYSCFG_SetRemapInput_TIM(uint32_t Remap)
00665 {
00666    MODIFY_REG(SYSCFG->CFGR1, (Remap & 0xFF00FF00U) >> 8U, (Remap & 0x00FF00FFU));
00667 }
00668 #endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */
00669
00670 #if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
00671 /**
00672   * @brief  Set ADC Trigger remap
00673   * @rmtoll SYSCFG_CFGR4 ADC12_EXT2_RMP    LL_SYSCFG_SetRemapTrigger_ADC\n
00674   *         SYSCFG_CFGR4 ADC12_EXT3_RMP    LL_SYSCFG_SetRemapTrigger_ADC\n
00675   *         SYSCFG_CFGR4 ADC12_EXT5_RMP    LL_SYSCFG_SetRemapTrigger_ADC\n
00676   *         SYSCFG_CFGR4 ADC12_EXT13_RMP   LL_SYSCFG_SetRemapTrigger_ADC\n
00677   *         SYSCFG_CFGR4 ADC12_EXT15_RMP   LL_SYSCFG_SetRemapTrigger_ADC\n
00678   *         SYSCFG_CFGR4 ADC12_JEXT3_RMP   LL_SYSCFG_SetRemapTrigger_ADC\n
00679   *         SYSCFG_CFGR4 ADC12_JEXT6_RMP   LL_SYSCFG_SetRemapTrigger_ADC\n
00680   *         SYSCFG_CFGR4 ADC12_JEXT13_RMP  LL_SYSCFG_SetRemapTrigger_ADC\n
00681   *         SYSCFG_CFGR4 ADC34_EXT5_RMP    LL_SYSCFG_SetRemapTrigger_ADC\n
00682   *         SYSCFG_CFGR4 ADC34_EXT6_RMP    LL_SYSCFG_SetRemapTrigger_ADC\n
00683   *         SYSCFG_CFGR4 ADC34_EXT15_RMP   LL_SYSCFG_SetRemapTrigger_ADC\n
00684   *         SYSCFG_CFGR4 ADC34_JEXT5_RMP   LL_SYSCFG_SetRemapTrigger_ADC\n
00685   *         SYSCFG_CFGR4 ADC34_JEXT11_RMP  LL_SYSCFG_SetRemapTrigger_ADC\n
00686   *         SYSCFG_CFGR4 ADC34_JEXT14_RMP  LL_SYSCFG_SetRemapTrigger_ADC
00687   * @param  Remap This parameter can be one of the following values:
00688   *         @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3
00689   *         @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO
00690   *         @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2
00691   *         @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2
00692   *         @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4
00693   *         @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1
00694   *         @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO
00695   *         @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2
00696   *         @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4
00697   *         @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3
00698   *         @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1
00699   *         @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO
00700   *         @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15
00701   *         @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2
00702   *         @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1
00703   *         @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4
00704   *         @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2
00705   *         @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO
00706   *         @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1
00707   *         @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2
00708   *         @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1
00709   *         @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1
00710   *         @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3
00711   *         @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO
00712   *         @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3
00713   *         @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2
00714   *         @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO
00715   *         @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2
00716   * @retval None
00717   */
00718 __STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_ADC(uint32_t Remap)
00719 {
00720   MODIFY_REG(SYSCFG->CFGR4, (Remap & 0xFFFF0000U) >> 16U, (Remap & 0x0000FFFFU));
00721 }
00722 #endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
00723
00724 #if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
00725 /**
00726   * @brief  Set DAC Trigger remap
00727   * @rmtoll SYSCFG_CFGR1 DAC1_TRIG1_RMP  LL_SYSCFG_SetRemapTrigger_DAC\n
00728   *         SYSCFG_CFGR3 DAC1_TRG3_RMP   LL_SYSCFG_SetRemapTrigger_DAC\n
00729   *         SYSCFG_CFGR3 DAC1_TRG5_RMP   LL_SYSCFG_SetRemapTrigger_DAC
00730   * @param  Remap This parameter can be one of the following values:
00731   *         @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (*)
00732   *         @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (*)
00733   *         @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (*)
00734   *         @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (*)
00735   *         @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_NO (*)
00736   *         @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (*)
00737   *         (*) value not defined in all devices.
00738   * @retval None
00739   */
00740 __STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_DAC(uint32_t Remap)
00741 {
00742   __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
00743   MODIFY_REG(*reg, (Remap & 0x00F00F00U) >> 4U, (Remap & 0x000F00F0U));
00744 }
00745 #endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */
00746
00747 #if defined(SYSCFG_CFGR1_USB_IT_RMP)
00748 /**
00749   * @brief  Enable USB interrupt remap
00750   * @note  Remap the USB interrupts (USB_HP, USB_LP and USB_WKUP) on interrupt lines 74, 75 and 76
00751   * respectively
00752   * @rmtoll SYSCFG_CFGR1 USB_IT_RMP    LL_SYSCFG_EnableRemapIT_USB
00753   * @retval None
00754   */
00755 __STATIC_INLINE void LL_SYSCFG_EnableRemapIT_USB(void)
00756 {
00757   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
00758 }
00759
00760 /**
00761   * @brief  Disable USB interrupt remap
00762   * @rmtoll SYSCFG_CFGR1 USB_IT_RMP    LL_SYSCFG_DisableRemapIT_USB
00763   * @retval None
00764   */
00765 __STATIC_INLINE void LL_SYSCFG_DisableRemapIT_USB(void)
00766 {
00767   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
00768 }
00769 #endif /* SYSCFG_CFGR1_USB_IT_RMP */
00770
00771 #if defined(SYSCFG_CFGR1_VBAT)
00772 /**
00773   * @brief  Enable VBAT monitoring (to enable the power switch to deliver VBAT voltage on ADC channel 18 input)
00774   * @rmtoll SYSCFG_CFGR1 VBAT          LL_SYSCFG_EnableVBATMonitoring
00775   * @retval None
00776   */
00777 __STATIC_INLINE void LL_SYSCFG_EnableVBATMonitoring(void)
00778 {
00779   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
00780 }
00781
00782 /**
00783   * @brief  Disable VBAT monitoring
00784   * @rmtoll SYSCFG_CFGR1 VBAT          LL_SYSCFG_DisableVBATMonitoring
00785   * @retval None
00786   */
00787 __STATIC_INLINE void LL_SYSCFG_DisableVBATMonitoring(void)
00788 {
00789   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
00790 }
00791 #endif /* SYSCFG_CFGR1_VBAT */
00792
00793 /**
00794   * @brief  Enable the I2C fast mode plus driving capability.
00795   * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP   LL_SYSCFG_EnableFastModePlus\n
00796   *         SYSCFG_CFGR1 I2C_PB7_FMP   LL_SYSCFG_EnableFastModePlus\n
00797   *         SYSCFG_CFGR1 I2C_PB8_FMP   LL_SYSCFG_EnableFastModePlus\n
00798   *         SYSCFG_CFGR1 I2C_PB9_FMP   LL_SYSCFG_EnableFastModePlus\n
00799   *         SYSCFG_CFGR1 I2C1_FMP      LL_SYSCFG_EnableFastModePlus\n
00800   *         SYSCFG_CFGR1 I2C2_FMP      LL_SYSCFG_EnableFastModePlus\n
00801   *         SYSCFG_CFGR1 I2C3_FMP      LL_SYSCFG_EnableFastModePlus
00802   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
00803   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
00804   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
00805   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
00806   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
00807   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
00808   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
00809   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
00810   *
00811   *         (*) value not defined in all devices.
00812   * @retval None
00813   */
00814 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
00815 {
00816   SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
00817 }
00818
00819 /**
00820   * @brief  Disable the I2C fast mode plus driving capability.
00821   * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP   LL_SYSCFG_DisableFastModePlus\n
00822   *         SYSCFG_CFGR1 I2C_PB7_FMP   LL_SYSCFG_DisableFastModePlus\n
00823   *         SYSCFG_CFGR1 I2C_PB8_FMP   LL_SYSCFG_DisableFastModePlus\n
00824   *         SYSCFG_CFGR1 I2C_PB9_FMP   LL_SYSCFG_DisableFastModePlus\n
00825   *         SYSCFG_CFGR1 I2C1_FMP      LL_SYSCFG_DisableFastModePlus\n
00826   *         SYSCFG_CFGR1 I2C2_FMP      LL_SYSCFG_DisableFastModePlus\n
00827   *         SYSCFG_CFGR1 I2C3_FMP      LL_SYSCFG_DisableFastModePlus
00828   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
00829   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
00830   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
00831   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
00832   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
00833   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
00834   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
00835   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
00836   *
00837   *         (*) value not defined in all devices.
00838   * @retval None
00839   */
00840 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
00841 {
00842   CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
00843 }
00844
00845 /**
00846   * @brief  Enable Floating Point Unit Invalid operation Interrupt
00847   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_EnableIT_FPU_IOC
00848   * @retval None
00849   */
00850 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
00851 {
00852   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
00853 }
00854
00855 /**
00856   * @brief  Enable Floating Point Unit Divide-by-zero Interrupt
00857   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_EnableIT_FPU_DZC
00858   * @retval None
00859   */
00860 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
00861 {
00862   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
00863 }
00864
00865 /**
00866   * @brief  Enable Floating Point Unit Underflow Interrupt
00867   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_EnableIT_FPU_UFC
00868   * @retval None
00869   */
00870 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
00871 {
00872   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
00873 }
00874
00875 /**
00876   * @brief  Enable Floating Point Unit Overflow Interrupt
00877   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_EnableIT_FPU_OFC
00878   * @retval None
00879   */
00880 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
00881 {
00882   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
00883 }
00884
00885 /**
00886   * @brief  Enable Floating Point Unit Input denormal Interrupt
00887   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_EnableIT_FPU_IDC
00888   * @retval None
00889   */
00890 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
00891 {
00892   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
00893 }
00894
00895 /**
00896   * @brief  Enable Floating Point Unit Inexact Interrupt
00897   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_EnableIT_FPU_IXC
00898   * @retval None
00899   */
00900 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
00901 {
00902   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
00903 }
00904
00905 /**
00906   * @brief  Disable Floating Point Unit Invalid operation Interrupt
00907   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_DisableIT_FPU_IOC
00908   * @retval None
00909   */
00910 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
00911 {
00912   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
00913 }
00914
00915 /**
00916   * @brief  Disable Floating Point Unit Divide-by-zero Interrupt
00917   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_DisableIT_FPU_DZC
00918   * @retval None
00919   */
00920 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
00921 {
00922   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
00923 }
00924
00925 /**
00926   * @brief  Disable Floating Point Unit Underflow Interrupt
00927   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_DisableIT_FPU_UFC
00928   * @retval None
00929   */
00930 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
00931 {
00932   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
00933 }
00934
00935 /**
00936   * @brief  Disable Floating Point Unit Overflow Interrupt
00937   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_DisableIT_FPU_OFC
00938   * @retval None
00939   */
00940 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
00941 {
00942   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
00943 }
00944
00945 /**
00946   * @brief  Disable Floating Point Unit Input denormal Interrupt
00947   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_DisableIT_FPU_IDC
00948   * @retval None
00949   */
00950 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
00951 {
00952   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
00953 }
00954
00955 /**
00956   * @brief  Disable Floating Point Unit Inexact Interrupt
00957   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_DisableIT_FPU_IXC
00958   * @retval None
00959   */
00960 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
00961 {
00962   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
00963 }
00964
00965 /**
00966   * @brief  Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
00967   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_IsEnabledIT_FPU_IOC
00968   * @retval State of bit (1 or 0).
00969   */
00970 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
00971 {
00972   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
00973 }
00974
00975 /**
00976   * @brief  Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
00977   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_IsEnabledIT_FPU_DZC
00978   * @retval State of bit (1 or 0).
00979   */
00980 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
00981 {
00982   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
00983 }
00984
00985 /**
00986   * @brief  Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
00987   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_IsEnabledIT_FPU_UFC
00988   * @retval State of bit (1 or 0).
00989   */
00990 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
00991 {
00992   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
00993 }
00994
00995 /**
00996   * @brief  Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
00997   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_IsEnabledIT_FPU_OFC
00998   * @retval State of bit (1 or 0).
00999   */
01000 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
01001 {
01002   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
01003 }
01004
01005 /**
01006   * @brief  Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
01007   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_IsEnabledIT_FPU_IDC
01008   * @retval State of bit (1 or 0).
01009   */
01010 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
01011 {
01012   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
01013 }
01014
01015 /**
01016   * @brief  Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
01017   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_IsEnabledIT_FPU_IXC
01018   * @retval State of bit (1 or 0).
01019   */
01020 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
01021 {
01022   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
01023 }
01024
01025 /**
01026   * @brief  Configure source input for the EXTI external interrupt.
01027   * @rmtoll SYSCFG_EXTICR1 EXTI0         LL_SYSCFG_SetEXTISource\n
01028   *         SYSCFG_EXTICR1 EXTI1         LL_SYSCFG_SetEXTISource\n
01029   *         SYSCFG_EXTICR1 EXTI2         LL_SYSCFG_SetEXTISource\n
01030   *         SYSCFG_EXTICR1 EXTI3         LL_SYSCFG_SetEXTISource\n
01031   *         SYSCFG_EXTICR1 EXTI4         LL_SYSCFG_SetEXTISource\n
01032   *         SYSCFG_EXTICR1 EXTI5         LL_SYSCFG_SetEXTISource\n
01033   *         SYSCFG_EXTICR1 EXTI6         LL_SYSCFG_SetEXTISource\n
01034   *         SYSCFG_EXTICR1 EXTI7         LL_SYSCFG_SetEXTISource\n
01035   *         SYSCFG_EXTICR1 EXTI8         LL_SYSCFG_SetEXTISource\n
01036   *         SYSCFG_EXTICR1 EXTI9         LL_SYSCFG_SetEXTISource\n
01037   *         SYSCFG_EXTICR1 EXTI10        LL_SYSCFG_SetEXTISource\n
01038   *         SYSCFG_EXTICR1 EXTI11        LL_SYSCFG_SetEXTISource\n
01039   *         SYSCFG_EXTICR1 EXTI12        LL_SYSCFG_SetEXTISource\n
01040   *         SYSCFG_EXTICR1 EXTI13        LL_SYSCFG_SetEXTISource\n
01041   *         SYSCFG_EXTICR1 EXTI14        LL_SYSCFG_SetEXTISource\n
01042   *         SYSCFG_EXTICR1 EXTI15        LL_SYSCFG_SetEXTISource\n
01043   *         SYSCFG_EXTICR2 EXTI0         LL_SYSCFG_SetEXTISource\n
01044   *         SYSCFG_EXTICR2 EXTI1         LL_SYSCFG_SetEXTISource\n
01045   *         SYSCFG_EXTICR2 EXTI2         LL_SYSCFG_SetEXTISource\n
01046   *         SYSCFG_EXTICR2 EXTI3         LL_SYSCFG_SetEXTISource\n
01047   *         SYSCFG_EXTICR2 EXTI4         LL_SYSCFG_SetEXTISource\n
01048   *         SYSCFG_EXTICR2 EXTI5         LL_SYSCFG_SetEXTISource\n
01049   *         SYSCFG_EXTICR2 EXTI6         LL_SYSCFG_SetEXTISource\n
01050   *         SYSCFG_EXTICR2 EXTI7         LL_SYSCFG_SetEXTISource\n
01051   *         SYSCFG_EXTICR2 EXTI8         LL_SYSCFG_SetEXTISource\n
01052   *         SYSCFG_EXTICR2 EXTI9         LL_SYSCFG_SetEXTISource\n
01053   *         SYSCFG_EXTICR2 EXTI10        LL_SYSCFG_SetEXTISource\n
01054   *         SYSCFG_EXTICR2 EXTI11        LL_SYSCFG_SetEXTISource\n
01055   *         SYSCFG_EXTICR2 EXTI12        LL_SYSCFG_SetEXTISource\n
01056   *         SYSCFG_EXTICR2 EXTI13        LL_SYSCFG_SetEXTISource\n
01057   *         SYSCFG_EXTICR2 EXTI14        LL_SYSCFG_SetEXTISource\n
01058   *         SYSCFG_EXTICR2 EXTI15        LL_SYSCFG_SetEXTISource\n
01059   *         SYSCFG_EXTICR3 EXTI0         LL_SYSCFG_SetEXTISource\n
01060   *         SYSCFG_EXTICR3 EXTI1         LL_SYSCFG_SetEXTISource\n
01061   *         SYSCFG_EXTICR3 EXTI2         LL_SYSCFG_SetEXTISource\n
01062   *         SYSCFG_EXTICR3 EXTI3         LL_SYSCFG_SetEXTISource\n
01063   *         SYSCFG_EXTICR3 EXTI4         LL_SYSCFG_SetEXTISource\n
01064   *         SYSCFG_EXTICR3 EXTI5         LL_SYSCFG_SetEXTISource\n
01065   *         SYSCFG_EXTICR3 EXTI6         LL_SYSCFG_SetEXTISource\n
01066   *         SYSCFG_EXTICR3 EXTI7         LL_SYSCFG_SetEXTISource\n
01067   *         SYSCFG_EXTICR3 EXTI8         LL_SYSCFG_SetEXTISource\n
01068   *         SYSCFG_EXTICR3 EXTI9         LL_SYSCFG_SetEXTISource\n
01069   *         SYSCFG_EXTICR3 EXTI10        LL_SYSCFG_SetEXTISource\n
01070   *         SYSCFG_EXTICR3 EXTI11        LL_SYSCFG_SetEXTISource\n
01071   *         SYSCFG_EXTICR3 EXTI12        LL_SYSCFG_SetEXTISource\n
01072   *         SYSCFG_EXTICR3 EXTI13        LL_SYSCFG_SetEXTISource\n
01073   *         SYSCFG_EXTICR3 EXTI14        LL_SYSCFG_SetEXTISource\n
01074   *         SYSCFG_EXTICR3 EXTI15        LL_SYSCFG_SetEXTISource\n
01075   *         SYSCFG_EXTICR4 EXTI0         LL_SYSCFG_SetEXTISource\n
01076   *         SYSCFG_EXTICR4 EXTI1         LL_SYSCFG_SetEXTISource\n
01077   *         SYSCFG_EXTICR4 EXTI2         LL_SYSCFG_SetEXTISource\n
01078   *         SYSCFG_EXTICR4 EXTI3         LL_SYSCFG_SetEXTISource\n
01079   *         SYSCFG_EXTICR4 EXTI4         LL_SYSCFG_SetEXTISource\n
01080   *         SYSCFG_EXTICR4 EXTI5         LL_SYSCFG_SetEXTISource\n
01081   *         SYSCFG_EXTICR4 EXTI6         LL_SYSCFG_SetEXTISource\n
01082   *         SYSCFG_EXTICR4 EXTI7         LL_SYSCFG_SetEXTISource\n
01083   *         SYSCFG_EXTICR4 EXTI8         LL_SYSCFG_SetEXTISource\n
01084   *         SYSCFG_EXTICR4 EXTI9         LL_SYSCFG_SetEXTISource\n
01085   *         SYSCFG_EXTICR4 EXTI10        LL_SYSCFG_SetEXTISource\n
01086   *         SYSCFG_EXTICR4 EXTI11        LL_SYSCFG_SetEXTISource\n
01087   *         SYSCFG_EXTICR4 EXTI12        LL_SYSCFG_SetEXTISource\n
01088   *         SYSCFG_EXTICR4 EXTI13        LL_SYSCFG_SetEXTISource\n
01089   *         SYSCFG_EXTICR4 EXTI14        LL_SYSCFG_SetEXTISource\n
01090   *         SYSCFG_EXTICR4 EXTI15        LL_SYSCFG_SetEXTISource
01091   * @param  Port This parameter can be one of the following values:
01092   *         @arg @ref LL_SYSCFG_EXTI_PORTA
01093   *         @arg @ref LL_SYSCFG_EXTI_PORTB
01094   *         @arg @ref LL_SYSCFG_EXTI_PORTC
01095   *         @arg @ref LL_SYSCFG_EXTI_PORTD
01096   *         @arg @ref LL_SYSCFG_EXTI_PORTE (*)
01097   *         @arg @ref LL_SYSCFG_EXTI_PORTF
01098   *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
01099   *         @arg @ref LL_SYSCFG_EXTI_PORTH (*)
01100   *
01101   *         (*) value not defined in all devices.
01102   * @param  Line This parameter can be one of the following values:
01103   *         @arg @ref LL_SYSCFG_EXTI_LINE0
01104   *         @arg @ref LL_SYSCFG_EXTI_LINE1
01105   *         @arg @ref LL_SYSCFG_EXTI_LINE2
01106   *         @arg @ref LL_SYSCFG_EXTI_LINE3
01107   *         @arg @ref LL_SYSCFG_EXTI_LINE4
01108   *         @arg @ref LL_SYSCFG_EXTI_LINE5
01109   *         @arg @ref LL_SYSCFG_EXTI_LINE6
01110   *         @arg @ref LL_SYSCFG_EXTI_LINE7
01111   *         @arg @ref LL_SYSCFG_EXTI_LINE8
01112   *         @arg @ref LL_SYSCFG_EXTI_LINE9
01113   *         @arg @ref LL_SYSCFG_EXTI_LINE10
01114   *         @arg @ref LL_SYSCFG_EXTI_LINE11
01115   *         @arg @ref LL_SYSCFG_EXTI_LINE12
01116   *         @arg @ref LL_SYSCFG_EXTI_LINE13
01117   *         @arg @ref LL_SYSCFG_EXTI_LINE14
01118   *         @arg @ref LL_SYSCFG_EXTI_LINE15
01119   * @retval None
01120   */
01121 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
01122 {
01123   MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
01124 }
01125
01126 /**
01127   * @brief  Get the configured defined for specific EXTI Line
01128   * @rmtoll SYSCFG_EXTICR1 EXTI0         LL_SYSCFG_GetEXTISource\n
01129   *         SYSCFG_EXTICR1 EXTI1         LL_SYSCFG_GetEXTISource\n
01130   *         SYSCFG_EXTICR1 EXTI2         LL_SYSCFG_GetEXTISource\n
01131   *         SYSCFG_EXTICR1 EXTI3         LL_SYSCFG_GetEXTISource\n
01132   *         SYSCFG_EXTICR1 EXTI4         LL_SYSCFG_GetEXTISource\n
01133   *         SYSCFG_EXTICR1 EXTI5         LL_SYSCFG_GetEXTISource\n
01134   *         SYSCFG_EXTICR1 EXTI6         LL_SYSCFG_GetEXTISource\n
01135   *         SYSCFG_EXTICR1 EXTI7         LL_SYSCFG_GetEXTISource\n
01136   *         SYSCFG_EXTICR1 EXTI8         LL_SYSCFG_GetEXTISource\n
01137   *         SYSCFG_EXTICR1 EXTI9         LL_SYSCFG_GetEXTISource\n
01138   *         SYSCFG_EXTICR1 EXTI10        LL_SYSCFG_GetEXTISource\n
01139   *         SYSCFG_EXTICR1 EXTI11        LL_SYSCFG_GetEXTISource\n
01140   *         SYSCFG_EXTICR1 EXTI12        LL_SYSCFG_GetEXTISource\n
01141   *         SYSCFG_EXTICR1 EXTI13        LL_SYSCFG_GetEXTISource\n
01142   *         SYSCFG_EXTICR1 EXTI14        LL_SYSCFG_GetEXTISource\n
01143   *         SYSCFG_EXTICR1 EXTI15        LL_SYSCFG_GetEXTISource\n
01144   *         SYSCFG_EXTICR2 EXTI0         LL_SYSCFG_GetEXTISource\n
01145   *         SYSCFG_EXTICR2 EXTI1         LL_SYSCFG_GetEXTISource\n
01146   *         SYSCFG_EXTICR2 EXTI2         LL_SYSCFG_GetEXTISource\n
01147   *         SYSCFG_EXTICR2 EXTI3         LL_SYSCFG_GetEXTISource\n
01148   *         SYSCFG_EXTICR2 EXTI4         LL_SYSCFG_GetEXTISource\n
01149   *         SYSCFG_EXTICR2 EXTI5         LL_SYSCFG_GetEXTISource\n
01150   *         SYSCFG_EXTICR2 EXTI6         LL_SYSCFG_GetEXTISource\n
01151   *         SYSCFG_EXTICR2 EXTI7         LL_SYSCFG_GetEXTISource\n
01152   *         SYSCFG_EXTICR2 EXTI8         LL_SYSCFG_GetEXTISource\n
01153   *         SYSCFG_EXTICR2 EXTI9         LL_SYSCFG_GetEXTISource\n
01154   *         SYSCFG_EXTICR2 EXTI10        LL_SYSCFG_GetEXTISource\n
01155   *         SYSCFG_EXTICR2 EXTI11        LL_SYSCFG_GetEXTISource\n
01156   *         SYSCFG_EXTICR2 EXTI12        LL_SYSCFG_GetEXTISource\n
01157   *         SYSCFG_EXTICR2 EXTI13        LL_SYSCFG_GetEXTISource\n
01158   *         SYSCFG_EXTICR2 EXTI14        LL_SYSCFG_GetEXTISource\n
01159   *         SYSCFG_EXTICR2 EXTI15        LL_SYSCFG_GetEXTISource\n
01160   *         SYSCFG_EXTICR3 EXTI0         LL_SYSCFG_GetEXTISource\n
01161   *         SYSCFG_EXTICR3 EXTI1         LL_SYSCFG_GetEXTISource\n
01162   *         SYSCFG_EXTICR3 EXTI2         LL_SYSCFG_GetEXTISource\n
01163   *         SYSCFG_EXTICR3 EXTI3         LL_SYSCFG_GetEXTISource\n
01164   *         SYSCFG_EXTICR3 EXTI4         LL_SYSCFG_GetEXTISource\n
01165   *         SYSCFG_EXTICR3 EXTI5         LL_SYSCFG_GetEXTISource\n
01166   *         SYSCFG_EXTICR3 EXTI6         LL_SYSCFG_GetEXTISource\n
01167   *         SYSCFG_EXTICR3 EXTI7         LL_SYSCFG_GetEXTISource\n
01168   *         SYSCFG_EXTICR3 EXTI8         LL_SYSCFG_GetEXTISource\n
01169   *         SYSCFG_EXTICR3 EXTI9         LL_SYSCFG_GetEXTISource\n
01170   *         SYSCFG_EXTICR3 EXTI10        LL_SYSCFG_GetEXTISource\n
01171   *         SYSCFG_EXTICR3 EXTI11        LL_SYSCFG_GetEXTISource\n
01172   *         SYSCFG_EXTICR3 EXTI12        LL_SYSCFG_GetEXTISource\n
01173   *         SYSCFG_EXTICR3 EXTI13        LL_SYSCFG_GetEXTISource\n
01174   *         SYSCFG_EXTICR3 EXTI14        LL_SYSCFG_GetEXTISource\n
01175   *         SYSCFG_EXTICR3 EXTI15        LL_SYSCFG_GetEXTISource\n
01176   *         SYSCFG_EXTICR4 EXTI0         LL_SYSCFG_GetEXTISource\n
01177   *         SYSCFG_EXTICR4 EXTI1         LL_SYSCFG_GetEXTISource\n
01178   *         SYSCFG_EXTICR4 EXTI2         LL_SYSCFG_GetEXTISource\n
01179   *         SYSCFG_EXTICR4 EXTI3         LL_SYSCFG_GetEXTISource\n
01180   *         SYSCFG_EXTICR4 EXTI4         LL_SYSCFG_GetEXTISource\n
01181   *         SYSCFG_EXTICR4 EXTI5         LL_SYSCFG_GetEXTISource\n
01182   *         SYSCFG_EXTICR4 EXTI6         LL_SYSCFG_GetEXTISource\n
01183   *         SYSCFG_EXTICR4 EXTI7         LL_SYSCFG_GetEXTISource\n
01184   *         SYSCFG_EXTICR4 EXTI8         LL_SYSCFG_GetEXTISource\n
01185   *         SYSCFG_EXTICR4 EXTI9         LL_SYSCFG_GetEXTISource\n
01186   *         SYSCFG_EXTICR4 EXTI10        LL_SYSCFG_GetEXTISource\n
01187   *         SYSCFG_EXTICR4 EXTI11        LL_SYSCFG_GetEXTISource\n
01188   *         SYSCFG_EXTICR4 EXTI12        LL_SYSCFG_GetEXTISource\n
01189   *         SYSCFG_EXTICR4 EXTI13        LL_SYSCFG_GetEXTISource\n
01190   *         SYSCFG_EXTICR4 EXTI14        LL_SYSCFG_GetEXTISource\n
01191   *         SYSCFG_EXTICR4 EXTI15        LL_SYSCFG_GetEXTISource
01192   * @param  Line This parameter can be one of the following values:
01193   *         @arg @ref LL_SYSCFG_EXTI_LINE0
01194   *         @arg @ref LL_SYSCFG_EXTI_LINE1
01195   *         @arg @ref LL_SYSCFG_EXTI_LINE2
01196   *         @arg @ref LL_SYSCFG_EXTI_LINE3
01197   *         @arg @ref LL_SYSCFG_EXTI_LINE4
01198   *         @arg @ref LL_SYSCFG_EXTI_LINE5
01199   *         @arg @ref LL_SYSCFG_EXTI_LINE6
01200   *         @arg @ref LL_SYSCFG_EXTI_LINE7
01201   *         @arg @ref LL_SYSCFG_EXTI_LINE8
01202   *         @arg @ref LL_SYSCFG_EXTI_LINE9
01203   *         @arg @ref LL_SYSCFG_EXTI_LINE10
01204   *         @arg @ref LL_SYSCFG_EXTI_LINE11
01205   *         @arg @ref LL_SYSCFG_EXTI_LINE12
01206   *         @arg @ref LL_SYSCFG_EXTI_LINE13
01207   *         @arg @ref LL_SYSCFG_EXTI_LINE14
01208   *         @arg @ref LL_SYSCFG_EXTI_LINE15
01209   * @retval Returned value can be one of the following values:
01210   *         @arg @ref LL_SYSCFG_EXTI_PORTA
01211   *         @arg @ref LL_SYSCFG_EXTI_PORTB
01212   *         @arg @ref LL_SYSCFG_EXTI_PORTC
01213   *         @arg @ref LL_SYSCFG_EXTI_PORTD
01214   *         @arg @ref LL_SYSCFG_EXTI_PORTE (*)
01215   *         @arg @ref LL_SYSCFG_EXTI_PORTF
01216   *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
01217   *         @arg @ref LL_SYSCFG_EXTI_PORTH (*)
01218   *
01219   *         (*) value not defined in all devices.
01220   */
01221 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
01222 {
01223   return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
01224 }
01225
01226 /**
01227   * @brief  Set connections to TIMx Break inputs
01228   * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK       LL_SYSCFG_SetTIMBreakInputs\n
01229   *         SYSCFG_CFGR2 SRAM_PARITY_LOCK  LL_SYSCFG_SetTIMBreakInputs\n
01230   *         SYSCFG_CFGR2 PVD_LOCK          LL_SYSCFG_SetTIMBreakInputs
01231   * @param  Break This parameter can be a combination of the following values:
01232   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
01233   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
01234   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
01235   *
01236   *         (*) value not defined in all devices.
01237   * @retval None
01238   */
01239 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
01240 {
01241   MODIFY_REG(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK, Break);
01242 }
01243
01244 /**
01245   * @brief  Get connections to TIMx Break inputs
01246   * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK       LL_SYSCFG_GetTIMBreakInputs\n
01247   *         SYSCFG_CFGR2 SRAM_PARITY_LOCK  LL_SYSCFG_GetTIMBreakInputs\n
01248   *         SYSCFG_CFGR2 PVD_LOCK          LL_SYSCFG_GetTIMBreakInputs
01249   * @retval Returned value can be can be a combination of the following values:
01250   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
01251   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
01252   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
01253   *
01254   *         (*) value not defined in all devices.
01255   */
01256 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
01257 {
01258   return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK));
01259 }
01260
01261 #if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
01262 /**
01263   * @brief  Disable RAM Parity Check Disable
01264   * @rmtoll SYSCFG_CFGR2 BYP_ADDR_PAR  LL_SYSCFG_DisableSRAMParityCheck
01265   * @retval None
01266   */
01267 __STATIC_INLINE void LL_SYSCFG_DisableSRAMParityCheck(void)
01268 {
01269   SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_BYP_ADDR_PAR);
01270 }
01271 #endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
01272
01273 #if defined(SYSCFG_CFGR2_SRAM_PE)
01274 /**
01275   * @brief  Check if SRAM parity error detected
01276   * @rmtoll SYSCFG_CFGR2 SRAM_PE       LL_SYSCFG_IsActiveFlag_SP
01277   * @retval State of bit (1 or 0).
01278   */
01279 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
01280 {
01281   return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE) == (SYSCFG_CFGR2_SRAM_PE));
01282 }
01283
01284 /**
01285   * @brief  Clear SRAM parity error flag
01286   * @rmtoll SYSCFG_CFGR2 SRAM_PE       LL_SYSCFG_ClearFlag_SP
01287   * @retval None
01288   */
01289 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
01290 {
01291   SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE);
01292 }
01293 #endif /* SYSCFG_CFGR2_SRAM_PE */
01294
01295 #if defined(SYSCFG_RCR_PAGE0)
01296 /**
01297   * @brief  Enable CCM SRAM page write protection
01298   * @note   Write protection is cleared only by a system reset
01299   * @rmtoll SYSCFG_RCR   PAGE0         LL_SYSCFG_EnableCCM_SRAMPageWRP\n
01300   *         SYSCFG_RCR   PAGE1         LL_SYSCFG_EnableCCM_SRAMPageWRP\n
01301   *         SYSCFG_RCR   PAGE2         LL_SYSCFG_EnableCCM_SRAMPageWRP\n
01302   *         SYSCFG_RCR   PAGE3         LL_SYSCFG_EnableCCM_SRAMPageWRP\n
01303   *         SYSCFG_RCR   PAGE4         LL_SYSCFG_EnableCCM_SRAMPageWRP\n
01304   *         SYSCFG_RCR   PAGE5         LL_SYSCFG_EnableCCM_SRAMPageWRP\n
01305   *         SYSCFG_RCR   PAGE6         LL_SYSCFG_EnableCCM_SRAMPageWRP\n
01306   *         SYSCFG_RCR   PAGE7         LL_SYSCFG_EnableCCM_SRAMPageWRP\n
01307   *         SYSCFG_RCR   PAGE8         LL_SYSCFG_EnableCCM_SRAMPageWRP\n
01308   *         SYSCFG_RCR   PAGE9         LL_SYSCFG_EnableCCM_SRAMPageWRP\n
01309   *         SYSCFG_RCR   PAGE10        LL_SYSCFG_EnableCCM_SRAMPageWRP\n
01310   *         SYSCFG_RCR   PAGE11        LL_SYSCFG_EnableCCM_SRAMPageWRP\n
01311   *         SYSCFG_RCR   PAGE12        LL_SYSCFG_EnableCCM_SRAMPageWRP\n
01312   *         SYSCFG_RCR   PAGE13        LL_SYSCFG_EnableCCM_SRAMPageWRP\n
01313   *         SYSCFG_RCR   PAGE14        LL_SYSCFG_EnableCCM_SRAMPageWRP\n
01314   *         SYSCFG_RCR   PAGE15        LL_SYSCFG_EnableCCM_SRAMPageWRP
01315   * @param  PageWRP This parameter can be a combination of the following values:
01316   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0
01317   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1
01318   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2
01319   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3
01320   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4 (*)
01321   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5 (*)
01322   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6 (*)
01323   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7 (*)
01324   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8 (*)
01325   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9 (*)
01326   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*)
01327   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*)
01328   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*)
01329   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*)
01330   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*)
01331   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*)
01332   *
01333   *         (*) value not defined in all devices.
01334   * @retval None
01335   */
01336 __STATIC_INLINE void LL_SYSCFG_EnableCCM_SRAMPageWRP(uint32_t PageWRP)
01337 {
01338   SET_BIT(SYSCFG->RCR, PageWRP);
01339 }
01340 #endif /* SYSCFG_RCR_PAGE0 */
01341
01342 /**
01343   * @}
01344   */
01345
01346 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
01347   * @{
01348   */
01349
01350 /**
01351   * @brief  Return the device identifier
01352   * @note For STM32F303xC, STM32F358xx and STM32F302xC devices, the device ID is 0x422
01353   * @note For STM32F373xx and STM32F378xx devices, the device ID is 0x432
01354   * @note For STM32F303x8, STM32F334xx and STM32F328xx devices, the device ID is 0x438.
01355   * @note For STM32F302x8, STM32F301x8 and STM32F318xx devices, the device ID is 0x439
01356   * @note For STM32F303xE, STM32F398xx and STM32F302xE devices, the device ID is 0x446
01357   * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
01358   * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
01359   */
01360 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
01361 {
01362   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
01363 }
01364
01365 /**
01366   * @brief  Return the device revision identifier
01367   * @note This field indicates the revision of the device.
01368   * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
01369   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
01370   */
01371 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
01372 {
01373   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
01374 }
01375
01376 /**
01377   * @brief  Enable the Debug Module during SLEEP mode
01378   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
01379   * @retval None
01380   */
01381 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
01382 {
01383   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
01384 }
01385
01386 /**
01387   * @brief  Disable the Debug Module during SLEEP mode
01388   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
01389   * @retval None
01390   */
01391 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
01392 {
01393   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
01394 }
01395
01396 /**
01397   * @brief  Enable the Debug Module during STOP mode
01398   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
01399   * @retval None
01400   */
01401 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
01402 {
01403   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
01404 }
01405
01406 /**
01407   * @brief  Disable the Debug Module during STOP mode
01408   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
01409   * @retval None
01410   */
01411 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
01412 {
01413   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
01414 }
01415
01416 /**
01417   * @brief  Enable the Debug Module during STANDBY mode
01418   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
01419   * @retval None
01420   */
01421 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
01422 {
01423   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
01424 }
01425
01426 /**
01427   * @brief  Disable the Debug Module during STANDBY mode
01428   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
01429   * @retval None
01430   */
01431 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
01432 {
01433   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
01434 }
01435
01436 /**
01437   * @brief  Set Trace pin assignment control
01438   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
01439   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
01440   * @param  PinAssignment This parameter can be one of the following values:
01441   *         @arg @ref LL_DBGMCU_TRACE_NONE
01442   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
01443   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
01444   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
01445   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
01446   * @retval None
01447   */
01448 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
01449 {
01450   MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
01451 }
01452
01453 /**
01454   * @brief  Get Trace pin assignment control
01455   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
01456   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
01457   * @retval Returned value can be one of the following values:
01458   *         @arg @ref LL_DBGMCU_TRACE_NONE
01459   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
01460   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
01461   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
01462   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
01463   */
01464 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
01465 {
01466   return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
01467 }
01468
01469 /**
01470   * @brief  Freeze APB1 peripherals (group1 peripherals)
01471   * @rmtoll APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01472   *         APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01473   *         APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01474   *         APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01475   *         APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01476   *         APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01477   *         APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01478   *         APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01479   *         APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01480   *         APB1_FZ      DBG_TIM18_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01481   *         APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01482   *         APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01483   *         APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01484   *         APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01485   *         APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01486   *         APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01487   *         APB1_FZ      DBG_CAN_STOP  LL_DBGMCU_APB1_GRP1_FreezePeriph
01488   * @param  Periphs This parameter can be a combination of the following values:
01489   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
01490   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
01491   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
01492   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
01493   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
01494   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
01495   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
01496   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
01497   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
01498   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
01499   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
01500   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
01501   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
01502   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
01503   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
01504   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
01505   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
01506   *
01507   *         (*) value not defined in all devices.
01508   * @retval None
01509   */
01510 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
01511 {
01512   SET_BIT(DBGMCU->APB1FZ, Periphs);
01513 }
01514
01515 /**
01516   * @brief  Unfreeze APB1 peripherals (group1 peripherals)
01517   * @rmtoll APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01518   *         APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01519   *         APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01520   *         APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01521   *         APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01522   *         APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01523   *         APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01524   *         APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01525   *         APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01526   *         APB1_FZ      DBG_TIM18_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01527   *         APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01528   *         APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01529   *         APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01530   *         APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01531   *         APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01532   *         APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01533   *         APB1_FZ      DBG_CAN_STOP  LL_DBGMCU_APB1_GRP1_UnFreezePeriph
01534   * @param  Periphs This parameter can be a combination of the following values:
01535   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
01536   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
01537   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
01538   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
01539   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
01540   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
01541   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
01542   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
01543   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
01544   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
01545   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
01546   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
01547   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
01548   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
01549   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
01550   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
01551   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
01552   *
01553   *         (*) value not defined in all devices.
01554   * @retval None
01555   */
01556 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
01557 {
01558   CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
01559 }
01560
01561 /**
01562   * @brief  Freeze APB2 peripherals
01563   * @rmtoll APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
01564   *         APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
01565   *         APB2_FZ      DBG_TIM15_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
01566   *         APB2_FZ      DBG_TIM16_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
01567   *         APB2_FZ      DBG_TIM17_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
01568   *         APB2_FZ      DBG_TIM19_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
01569   *         APB2_FZ      DBG_TIM20_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
01570   *         APB2_FZ      DBG_HRTIM1_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph
01571   * @param  Periphs This parameter can be a combination of the following values:
01572   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
01573   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
01574   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
01575   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
01576   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
01577   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
01578   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
01579   *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
01580   *
01581   *         (*) value not defined in all devices.
01582   * @retval None
01583   */
01584 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
01585 {
01586   SET_BIT(DBGMCU->APB2FZ, Periphs);
01587 }
01588
01589 /**
01590   * @brief  Unfreeze APB2 peripherals
01591   * @rmtoll APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
01592   *         APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
01593   *         APB2_FZ      DBG_TIM15_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
01594   *         APB2_FZ      DBG_TIM16_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
01595   *         APB2_FZ      DBG_TIM17_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
01596   *         APB2_FZ      DBG_TIM19_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
01597   *         APB2_FZ      DBG_TIM20_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
01598   *         APB2_FZ      DBG_HRTIM1_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph
01599   * @param  Periphs This parameter can be a combination of the following values:
01600   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
01601   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
01602   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
01603   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
01604   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
01605   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
01606   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
01607   *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
01608   *
01609   *         (*) value not defined in all devices.
01610   * @retval None
01611   */
01612 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
01613 {
01614   CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
01615 }
01616
01617 /**
01618   * @}
01619   */
01620
01621 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
01622   * @{
01623   */
01624
01625 /**
01626   * @brief  Set FLASH Latency
01627   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
01628   * @param  Latency This parameter can be one of the following values:
01629   *         @arg @ref LL_FLASH_LATENCY_0
01630   *         @arg @ref LL_FLASH_LATENCY_1
01631   *         @arg @ref LL_FLASH_LATENCY_2
01632   * @retval None
01633   */
01634 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
01635 {
01636   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
01637 }
01638
01639 /**
01640   * @brief  Get FLASH Latency
01641   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
01642   * @retval Returned value can be one of the following values:
01643   *         @arg @ref LL_FLASH_LATENCY_0
01644   *         @arg @ref LL_FLASH_LATENCY_1
01645   *         @arg @ref LL_FLASH_LATENCY_2
01646   */
01647 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
01648 {
01649   return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
01650 }
01651
01652 /**
01653   * @brief  Enable Prefetch
01654   * @rmtoll FLASH_ACR    PRFTBE         LL_FLASH_EnablePrefetch
01655   * @retval None
01656   */
01657 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
01658 {
01659   SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
01660 }
01661
01662 /**
01663   * @brief  Disable Prefetch
01664   * @rmtoll FLASH_ACR    PRFTBE         LL_FLASH_DisablePrefetch
01665   * @retval None
01666   */
01667 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
01668 {
01669   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
01670 }
01671
01672 /**
01673   * @brief  Check if Prefetch buffer is enabled
01674   * @rmtoll FLASH_ACR    PRFTBS        LL_FLASH_IsPrefetchEnabled
01675   * @retval State of bit (1 or 0).
01676   */
01677 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
01678 {
01679   return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
01680 }
01681
01682 #if defined(FLASH_ACR_HLFCYA)
01683 /**
01684   * @brief  Enable Flash Half Cycle Access
01685   * @rmtoll FLASH_ACR    HLFCYA        LL_FLASH_EnableHalfCycleAccess
01686   * @retval None
01687   */
01688 __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
01689 {
01690   SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
01691 }
01692
01693 /**
01694   * @brief  Disable Flash Half Cycle Access
01695   * @rmtoll FLASH_ACR    HLFCYA        LL_FLASH_DisableHalfCycleAccess
01696   * @retval None
01697   */
01698 __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
01699 {
01700   CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
01701 }
01702
01703 /**
01704   * @brief  Check if  Flash Half Cycle Access is enabled or not
01705   * @rmtoll FLASH_ACR    HLFCYA        LL_FLASH_IsHalfCycleAccessEnabled
01706   * @retval State of bit (1 or 0).
01707   */
01708 __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
01709 {
01710   return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
01711 }
01712 #endif /* FLASH_ACR_HLFCYA */
01713
01714
01715
01716 /**
01717   * @}
01718   */
01719
01720 /**
01721   * @}
01722   */
01723
01724 /**
01725   * @}
01726   */
01727
01728 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
01729
01730 /**
01731   * @}
01732   */
01733
01734 #ifdef __cplusplus
01735 }
01736 #endif
01737
01738 #endif /* __STM32F3xx_LL_SYSTEM_H */
01739
01740 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_tim.c Source File

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stm32f3xx_ll_tim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_tim.c
00004   * @author  MCD Application Team
00005   * @brief   TIM LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 #if defined(USE_FULL_LL_DRIVER)
00036
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f3xx_ll_tim.h"
00039 #include "stm32f3xx_ll_bus.h"
00040
00041 #ifdef  USE_FULL_ASSERT
00042 #include "stm32_assert.h"
00043 #else
00044 #define assert_param(expr) ((void)0U)
00045 #endif
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20)
00052
00053 /** @addtogroup TIM_LL
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059 /* Private constants ---------------------------------------------------------*/
00060 /* Private macros ------------------------------------------------------------*/
00061 /** @addtogroup TIM_LL_Private_Macros
00062   * @{
00063   */
00064 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
00065                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
00066                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
00067                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
00068                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
00069
00070 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
00071                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
00072                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
00073
00074 #if defined(TIM_CCMR1_OC1M_3)
00075 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
00076                                   || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
00077                                   || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
00078                                   || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
00079                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
00080                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
00081                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
00082                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
00083                                   || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
00084                                   || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
00085                                   || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
00086                                   || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
00087                                   || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
00088                                   || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
00089 #else
00090 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
00091                                   || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
00092                                   || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
00093                                   || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
00094                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
00095                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
00096                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
00097                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
00098 #endif
00099
00100 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
00101                                    || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
00102
00103 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
00104                                       || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
00105
00106 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
00107                                        || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
00108
00109 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
00110                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
00111                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
00112
00113 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
00114                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
00115                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
00116                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
00117
00118 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
00119                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
00120                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
00121                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
00122                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
00123                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
00124                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
00125                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
00126                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
00127                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
00128                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
00129                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
00130                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
00131                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
00132                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
00133                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
00134
00135 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
00136                                        || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
00137                                        || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
00138
00139 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
00140                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
00141                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
00142
00143 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
00144                                                || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
00145
00146 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
00147                                      || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
00148
00149 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
00150                                       || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
00151
00152 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
00153                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
00154                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
00155                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
00156
00157 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
00158                                        || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
00159
00160 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
00161                                           || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
00162 #if defined(TIM_BDTR_BKF)
00163
00164 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
00165                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
00166                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
00167                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
00168                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
00169                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
00170                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
00171                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
00172                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
00173                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
00174                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
00175                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
00176                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
00177                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
00178                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
00179                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
00180 #endif /* TIM_BDTR_BKF */
00181 #if defined(TIM_BDTR_BK2E)
00182
00183 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
00184                                         || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
00185
00186 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
00187                                            || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
00188
00189 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
00190                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
00191                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
00192                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
00193                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
00194                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
00195                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
00196                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
00197                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
00198                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
00199                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
00200                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
00201                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
00202                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
00203                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
00204                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
00205 #endif /* TIM_BDTR_BK2E */
00206
00207 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
00208                                                   || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
00209 /**
00210   * @}
00211   */
00212
00213
00214 /* Private function prototypes -----------------------------------------------*/
00215 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
00216   * @{
00217   */
00218 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00219 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00220 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00221 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00222 #if defined(TIM_CCER_CC5E)
00223 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00224 #endif /* TIM_CCER_CC5E */
00225 #if defined(TIM_CCER_CC6E)
00226 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00227 #endif /* TIM_CCER_CC6E */
00228 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00229 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00230 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00231 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00232 /**
00233   * @}
00234   */
00235
00236 /* Exported functions --------------------------------------------------------*/
00237 /** @addtogroup TIM_LL_Exported_Functions
00238   * @{
00239   */
00240
00241 /** @addtogroup TIM_LL_EF_Init
00242   * @{
00243   */
00244
00245 /**
00246   * @brief  Set TIMx registers to their reset values.
00247   * @param  TIMx Timer instance
00248   * @retval An ErrorStatus enumeration value:
00249   *          - SUCCESS: TIMx registers are de-initialized
00250   *          - ERROR: invalid TIMx instance
00251   */
00252 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
00253 {
00254   ErrorStatus result = SUCCESS;
00255
00256   /* Check the parameters */
00257   assert_param(IS_TIM_INSTANCE(TIMx));
00258
00259
00260   if (TIMx == TIM2)
00261   {
00262     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
00263     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
00264   }
00265
00266 #if defined(TIM1)
00267   else if (TIMx == TIM1)
00268   {
00269     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
00270     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
00271   }
00272 #endif
00273 #if defined(TIM3)
00274   else if (TIMx == TIM3)
00275   {
00276     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
00277     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
00278   }
00279 #endif
00280 #if defined(TIM4)
00281   else if (TIMx == TIM4)
00282   {
00283     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
00284     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
00285   }
00286 #endif
00287 #if defined(TIM5)
00288   else if (TIMx == TIM5)
00289   {
00290     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
00291     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
00292   }
00293 #endif
00294 #if defined(TIM6)
00295   else if (TIMx == TIM6)
00296   {
00297     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
00298     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
00299   }
00300 #endif
00301 #if defined(TIM7)
00302   else if (TIMx == TIM7)
00303   {
00304     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
00305     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
00306   }
00307 #endif
00308 #if defined(TIM8)
00309   else if (TIMx == TIM8)
00310   {
00311     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
00312     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
00313   }
00314 #endif
00315 #if defined(TIM12)
00316   else if (TIMx == TIM12)
00317   {
00318     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
00319     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
00320   }
00321 #endif
00322 #if defined(TIM13)
00323   else if (TIMx == TIM13)
00324   {
00325     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
00326     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
00327   }
00328 #endif
00329 #if defined(TIM14)
00330   else if (TIMx == TIM14)
00331   {
00332     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
00333     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
00334   }
00335 #endif
00336 #if defined(TIM15)
00337   else if (TIMx == TIM15)
00338   {
00339     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
00340     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
00341   }
00342 #endif
00343 #if defined(TIM16)
00344   else if (TIMx == TIM16)
00345   {
00346     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
00347     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
00348   }
00349 #endif
00350 #if defined(TIM17)
00351   else if (TIMx == TIM17)
00352   {
00353     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
00354     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
00355   }
00356 #endif
00357 #if defined(TIM18)
00358   else if (TIMx == TIM18)
00359   {
00360     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM18);
00361     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM18);
00362   }
00363 #endif
00364 #if defined(TIM19)
00365   else if (TIMx == TIM19)
00366   {
00367     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM19);
00368     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM19);
00369   }
00370 #endif
00371 #if defined(TIM20)
00372   else if (TIMx == TIM20)
00373   {
00374     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM20);
00375     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM20);
00376   }
00377 #endif
00378   else
00379   {
00380     result = ERROR;
00381   }
00382
00383
00384   return result;
00385 }
00386
00387 /**
00388   * @brief  Set the fields of the time base unit configuration data structure
00389   *         to their default values.
00390   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
00391   * @retval None
00392   */
00393 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
00394 {
00395   /* Set the default configuration */
00396   TIM_InitStruct->Prescaler         = (uint16_t)0x0000U;
00397   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
00398   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
00399   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
00400   TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
00401 }
00402
00403 /**
00404   * @brief  Configure the TIMx time base unit.
00405   * @param  TIMx Timer Instance
00406   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
00407   * @retval An ErrorStatus enumeration value:
00408   *          - SUCCESS: TIMx registers are de-initialized
00409   *          - ERROR: not applicable
00410   */
00411 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
00412 {
00413   uint32_t tmpcr1 = 0U;
00414
00415   /* Check the parameters */
00416   assert_param(IS_TIM_INSTANCE(TIMx));
00417   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
00418   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
00419
00420   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
00421
00422   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
00423   {
00424     /* Select the Counter Mode */
00425     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
00426   }
00427
00428   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
00429   {
00430     /* Set the clock division */
00431     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
00432   }
00433
00434   /* Write to TIMx CR1 */
00435   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
00436
00437   /* Set the Autoreload value */
00438   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
00439
00440   /* Set the Prescaler value */
00441   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
00442
00443   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
00444   {
00445     /* Set the Repetition Counter value */
00446     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
00447   }
00448
00449   /* Generate an update event to reload the Prescaler
00450      and the repetition counter value (if applicable) immediately */
00451   LL_TIM_GenerateEvent_UPDATE(TIMx);
00452
00453   return SUCCESS;
00454 }
00455
00456 /**
00457   * @brief  Set the fields of the TIMx output channel configuration data
00458   *         structure to their default values.
00459   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
00460   * @retval None
00461   */
00462 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
00463 {
00464   /* Set the default configuration */
00465   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
00466   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
00467   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
00468   TIM_OC_InitStruct->CompareValue = 0x00000000U;
00469   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
00470   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
00471   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
00472   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
00473 }
00474
00475 /**
00476   * @brief  Configure the TIMx output channel.
00477   * @param  TIMx Timer Instance
00478   * @param  Channel This parameter can be one of the following values:
00479   *         @arg @ref LL_TIM_CHANNEL_CH1
00480   *         @arg @ref LL_TIM_CHANNEL_CH2
00481   *         @arg @ref LL_TIM_CHANNEL_CH3
00482   *         @arg @ref LL_TIM_CHANNEL_CH4
00483   *         @arg @ref LL_TIM_CHANNEL_CH5
00484   *         @arg @ref LL_TIM_CHANNEL_CH6
00485   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
00486   * @note   OC5 and OC6 are not available for all F3 devices
00487   * @retval An ErrorStatus enumeration value:
00488   *          - SUCCESS: TIMx output channel is initialized
00489   *          - ERROR: TIMx output channel is not initialized
00490   */
00491 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
00492 {
00493   ErrorStatus result = ERROR;
00494
00495   switch (Channel)
00496   {
00497     case LL_TIM_CHANNEL_CH1:
00498       result = OC1Config(TIMx, TIM_OC_InitStruct);
00499       break;
00500     case LL_TIM_CHANNEL_CH2:
00501       result = OC2Config(TIMx, TIM_OC_InitStruct);
00502       break;
00503     case LL_TIM_CHANNEL_CH3:
00504       result = OC3Config(TIMx, TIM_OC_InitStruct);
00505       break;
00506     case LL_TIM_CHANNEL_CH4:
00507       result = OC4Config(TIMx, TIM_OC_InitStruct);
00508       break;
00509 #if defined(TIM_CCER_CC5E)
00510     case LL_TIM_CHANNEL_CH5:
00511       result = OC5Config(TIMx, TIM_OC_InitStruct);
00512       break;
00513     case LL_TIM_CHANNEL_CH6:
00514       result = OC6Config(TIMx, TIM_OC_InitStruct);
00515       break;
00516 #endif /* TIM_CCER_CC5E */
00517     default:
00518       break;
00519   }
00520
00521   return result;
00522 }
00523
00524 /**
00525   * @brief  Set the fields of the TIMx input channel configuration data
00526   *         structure to their default values.
00527   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
00528   * @retval None
00529   */
00530 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
00531 {
00532   /* Set the default configuration */
00533   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
00534   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00535   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
00536   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
00537 }
00538
00539 /**
00540   * @brief  Configure the TIMx input channel.
00541   * @param  TIMx Timer Instance
00542   * @param  Channel This parameter can be one of the following values:
00543   *         @arg @ref LL_TIM_CHANNEL_CH1
00544   *         @arg @ref LL_TIM_CHANNEL_CH2
00545   *         @arg @ref LL_TIM_CHANNEL_CH3
00546   *         @arg @ref LL_TIM_CHANNEL_CH4
00547   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
00548   * @retval An ErrorStatus enumeration value:
00549   *          - SUCCESS: TIMx output channel is initialized
00550   *          - ERROR: TIMx output channel is not initialized
00551   */
00552 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
00553 {
00554   ErrorStatus result = ERROR;
00555
00556   switch (Channel)
00557   {
00558     case LL_TIM_CHANNEL_CH1:
00559       result = IC1Config(TIMx, TIM_IC_InitStruct);
00560       break;
00561     case LL_TIM_CHANNEL_CH2:
00562       result = IC2Config(TIMx, TIM_IC_InitStruct);
00563       break;
00564     case LL_TIM_CHANNEL_CH3:
00565       result = IC3Config(TIMx, TIM_IC_InitStruct);
00566       break;
00567     case LL_TIM_CHANNEL_CH4:
00568       result = IC4Config(TIMx, TIM_IC_InitStruct);
00569       break;
00570     default:
00571       break;
00572   }
00573
00574   return result;
00575 }
00576
00577 /**
00578   * @brief  Fills each TIM_EncoderInitStruct field with its default value
00579   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
00580   * @retval None
00581   */
00582 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
00583 {
00584   /* Set the default configuration */
00585   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
00586   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
00587   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00588   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
00589   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
00590   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
00591   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00592   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
00593   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
00594 }
00595
00596 /**
00597   * @brief  Configure the encoder interface of the timer instance.
00598   * @param  TIMx Timer Instance
00599   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
00600   * @retval An ErrorStatus enumeration value:
00601   *          - SUCCESS: TIMx registers are de-initialized
00602   *          - ERROR: not applicable
00603   */
00604 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
00605 {
00606   uint32_t tmpccmr1 = 0U;
00607   uint32_t tmpccer = 0U;
00608
00609   /* Check the parameters */
00610   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
00611   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
00612   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
00613   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
00614   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
00615   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
00616   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
00617   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
00618   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
00619   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
00620
00621   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
00622   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
00623
00624   /* Get the TIMx CCMR1 register value */
00625   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00626
00627   /* Get the TIMx CCER register value */
00628   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00629
00630   /* Configure TI1 */
00631   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
00632   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
00633   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
00634   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
00635
00636   /* Configure TI2 */
00637   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
00638   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
00639   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
00640   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
00641
00642   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
00643   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
00644   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
00645   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
00646   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
00647
00648   /* Set encoder mode */
00649   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
00650
00651   /* Write to TIMx CCMR1 */
00652   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00653
00654   /* Write to TIMx CCER */
00655   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00656
00657   return SUCCESS;
00658 }
00659
00660 #if defined TIM_CR2_MMS2
00661 /**
00662   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
00663   *         structure to their default values.
00664   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
00665   * @retval None
00666   */
00667 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
00668 {
00669   /* Set the default configuration */
00670   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
00671   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
00672   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
00673   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
00674 }
00675
00676 /**
00677   * @brief  Configure the Hall sensor interface of the timer instance.
00678   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
00679   *       to the TI1 input channel
00680   * @note TIMx slave mode controller is configured in reset mode.
00681           Selected internal trigger is TI1F_ED.
00682   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
00683   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
00684   *       between 2 changes on the inputs. It gives information about motor speed.
00685   * @note Channel 2 is configured in output PWM 2 mode.
00686   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
00687   * @note OC2REF is selected as trigger output on TRGO.
00688   * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
00689   *       when TIMx operates in Hall sensor interface mode.
00690   * @param  TIMx Timer Instance
00691   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
00692   * @retval An ErrorStatus enumeration value:
00693   *          - SUCCESS: TIMx registers are de-initialized
00694   *          - ERROR: not applicable
00695   */
00696 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
00697 {
00698   uint32_t tmpcr2 = 0U;
00699   uint32_t tmpccmr1 = 0U;
00700   uint32_t tmpccer = 0U;
00701   uint32_t tmpsmcr = 0U;
00702
00703   /* Check the parameters */
00704   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
00705   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
00706   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
00707   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
00708
00709   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
00710   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
00711
00712   /* Get the TIMx CR2 register value */
00713   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00714
00715   /* Get the TIMx CCMR1 register value */
00716   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00717
00718   /* Get the TIMx CCER register value */
00719   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00720
00721   /* Get the TIMx SMCR register value */
00722   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
00723
00724   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
00725   tmpcr2 |= TIM_CR2_TI1S;
00726
00727   /* OC2REF signal is used as trigger output (TRGO) */
00728   tmpcr2 |= LL_TIM_TRGO_OC2REF;
00729
00730   /* Configure the slave mode controller */
00731   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
00732   tmpsmcr |= LL_TIM_TS_TI1F_ED;
00733   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
00734
00735   /* Configure input channel 1 */
00736   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
00737   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
00738   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
00739   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
00740
00741   /* Configure input channel 2 */
00742   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
00743   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
00744
00745   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
00746   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
00747   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
00748   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
00749
00750   /* Write to TIMx CR2 */
00751   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00752
00753   /* Write to TIMx SMCR */
00754   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
00755
00756   /* Write to TIMx CCMR1 */
00757   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00758
00759   /* Write to TIMx CCER */
00760   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00761
00762   /* Write to TIMx CCR2 */
00763   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
00764
00765   return SUCCESS;
00766 }
00767 #endif /* TIM_CR2_MMS2 */
00768
00769 /**
00770   * @brief  Set the fields of the Break and Dead Time configuration data structure
00771   *         to their default values.
00772   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
00773   * @retval None
00774   */
00775 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
00776 {
00777   /* Set the default configuration */
00778   TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
00779   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
00780   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
00781   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00U;
00782   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
00783   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
00784 #if defined(TIM_BDTR_BKF)
00785   TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
00786 #endif /* TIM_BDTR_BKF */
00787 #if defined(TIM_BDTR_BK2E)
00788   TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
00789   TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
00790   TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
00791 #endif /* TIM_BDTR_BK2E */
00792   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
00793 }
00794
00795 /**
00796   * @brief  Configure the Break and Dead Time feature of the timer instance.
00797   * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
00798   *  and DTG[7:0] can be write-locked depending on the LOCK configuration, it
00799   *  can be necessary to configure all of them during the first write access to
00800   *  the TIMx_BDTR register.
00801   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
00802   *       a timer instance provides a break input.
00803   * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
00804   *       a timer instance provides a second break input.
00805   * @param  TIMx Timer Instance
00806   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
00807   * @retval An ErrorStatus enumeration value:
00808   *          - SUCCESS: Break and Dead Time is initialized
00809   *          - ERROR: not applicable
00810   */
00811 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
00812 {
00813   uint32_t tmpbdtr = 0;
00814
00815   /* Check the parameters */
00816   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
00817   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
00818   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
00819   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
00820   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
00821   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
00822   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
00823
00824   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
00825   the OSSI State, the dead time value and the Automatic Output Enable Bit */
00826
00827   /* Set the BDTR bits */
00828   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
00829   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
00830   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
00831   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
00832   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
00833   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
00834   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
00835   MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
00836 #if defined(TIM_BDTR_BKF)
00837   if (IS_TIM_ADVANCED_INSTANCE(TIMx))
00838   {
00839     assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
00840     MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
00841   }
00842 #endif /* TIM_BDTR_BKF */
00843 #if defined(TIM_BDTR_BK2E)
00844
00845   if (IS_TIM_BKIN2_INSTANCE(TIMx))
00846   {
00847     assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
00848     assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
00849     assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
00850
00851     /* Set the BREAK2 input related BDTR bit-fields */
00852     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
00853     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
00854     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
00855   }
00856 #endif /* TIM_BDTR_BK2E */
00857
00858   /* Set TIMx_BDTR */
00859   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
00860
00861   return SUCCESS;
00862 }
00863 /**
00864   * @}
00865   */
00866
00867 /**
00868   * @}
00869   */
00870
00871 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
00872  *  @brief   Private functions
00873   * @{
00874   */
00875 /**
00876   * @brief  Configure the TIMx output channel 1.
00877   * @param  TIMx Timer Instance
00878   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
00879   * @retval An ErrorStatus enumeration value:
00880   *          - SUCCESS: TIMx registers are de-initialized
00881   *          - ERROR: not applicable
00882   */
00883 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00884 {
00885   uint32_t tmpccmr1 = 0U;
00886   uint32_t tmpccer = 0U;
00887   uint32_t tmpcr2 = 0U;
00888
00889   /* Check the parameters */
00890   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
00891   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00892   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00893   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00894   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00895   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00896
00897   /* Disable the Channel 1: Reset the CC1E Bit */
00898   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
00899
00900   /* Get the TIMx CCER register value */
00901   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00902
00903   /* Get the TIMx CR2 register value */
00904   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00905
00906   /* Get the TIMx CCMR1 register value */
00907   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00908
00909   /* Reset Capture/Compare selection Bits */
00910   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
00911
00912   /* Set the Output Compare Mode */
00913   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
00914
00915   /* Set the Output Compare Polarity */
00916   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
00917
00918   /* Set the Output State */
00919   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
00920
00921   if (IS_TIM_BREAK_INSTANCE(TIMx))
00922   {
00923     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00924     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00925
00926     /* Set the complementary output Polarity */
00927     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
00928
00929     /* Set the complementary output State */
00930     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
00931
00932     /* Set the Output Idle state */
00933     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
00934
00935     /* Set the complementary output Idle state */
00936     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
00937   }
00938
00939   /* Write to TIMx CR2 */
00940   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00941
00942   /* Write to TIMx CCMR1 */
00943   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00944
00945   /* Set the Capture Compare Register value */
00946   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
00947
00948   /* Write to TIMx CCER */
00949   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00950
00951   return SUCCESS;
00952 }
00953
00954 /**
00955   * @brief  Configure the TIMx output channel 2.
00956   * @param  TIMx Timer Instance
00957   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
00958   * @retval An ErrorStatus enumeration value:
00959   *          - SUCCESS: TIMx registers are de-initialized
00960   *          - ERROR: not applicable
00961   */
00962 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00963 {
00964   uint32_t tmpccmr1 = 0U;
00965   uint32_t tmpccer = 0U;
00966   uint32_t tmpcr2 = 0U;
00967
00968   /* Check the parameters */
00969   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
00970   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00971   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00972   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00973   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00974   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00975
00976   /* Disable the Channel 2: Reset the CC2E Bit */
00977   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
00978
00979   /* Get the TIMx CCER register value */
00980   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
00981
00982   /* Get the TIMx CR2 register value */
00983   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00984
00985   /* Get the TIMx CCMR1 register value */
00986   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00987
00988   /* Reset Capture/Compare selection Bits */
00989   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
00990
00991   /* Select the Output Compare Mode */
00992   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
00993
00994   /* Set the Output Compare Polarity */
00995   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
00996
00997   /* Set the Output State */
00998   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
00999
01000   if (IS_TIM_BREAK_INSTANCE(TIMx))
01001   {
01002     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01003     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01004
01005     /* Set the complementary output Polarity */
01006     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
01007
01008     /* Set the complementary output State */
01009     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
01010
01011     /* Set the Output Idle state */
01012     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
01013
01014 #if defined(STM32F373xC) || defined(STM32F378xx)
01015 #else
01016     /* Set the complementary output Idle state */
01017     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
01018 #endif
01019   }
01020
01021   /* Write to TIMx CR2 */
01022   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
01023
01024   /* Write to TIMx CCMR1 */
01025   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
01026
01027   /* Set the Capture Compare Register value */
01028   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
01029
01030   /* Write to TIMx CCER */
01031   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01032
01033   return SUCCESS;
01034 }
01035
01036 /**
01037   * @brief  Configure the TIMx output channel 3.
01038   * @param  TIMx Timer Instance
01039   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
01040   * @retval An ErrorStatus enumeration value:
01041   *          - SUCCESS: TIMx registers are de-initialized
01042   *          - ERROR: not applicable
01043   */
01044 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
01045 {
01046   uint32_t tmpccmr2 = 0U;
01047   uint32_t tmpccer = 0U;
01048   uint32_t tmpcr2 = 0U;
01049
01050   /* Check the parameters */
01051   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
01052   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
01053   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
01054   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
01055   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01056   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01057
01058   /* Disable the Channel 3: Reset the CC3E Bit */
01059   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
01060
01061   /* Get the TIMx CCER register value */
01062   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
01063
01064   /* Get the TIMx CR2 register value */
01065   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
01066
01067   /* Get the TIMx CCMR2 register value */
01068   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
01069
01070   /* Reset Capture/Compare selection Bits */
01071   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
01072
01073   /* Select the Output Compare Mode */
01074   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
01075
01076   /* Set the Output Compare Polarity */
01077   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
01078
01079   /* Set the Output State */
01080   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
01081
01082   if (IS_TIM_BREAK_INSTANCE(TIMx))
01083   {
01084     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01085     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01086
01087     /* Set the complementary output Polarity */
01088     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
01089
01090     /* Set the complementary output State */
01091     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
01092
01093 #if defined(STM32F373xC) || defined(STM32F378xx)
01094 #else
01095     /* Set the Output Idle state */
01096     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
01097
01098     /* Set the complementary output Idle state */
01099     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
01100 #endif
01101   }
01102
01103   /* Write to TIMx CR2 */
01104   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
01105
01106   /* Write to TIMx CCMR2 */
01107   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
01108
01109   /* Set the Capture Compare Register value */
01110   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
01111
01112   /* Write to TIMx CCER */
01113   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01114
01115   return SUCCESS;
01116 }
01117
01118 /**
01119   * @brief  Configure the TIMx output channel 4.
01120   * @param  TIMx Timer Instance
01121   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
01122   * @retval An ErrorStatus enumeration value:
01123   *          - SUCCESS: TIMx registers are de-initialized
01124   *          - ERROR: not applicable
01125   */
01126 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
01127 {
01128   uint32_t tmpccmr2 = 0U;
01129   uint32_t tmpccer = 0U;
01130   uint32_t tmpcr2 = 0U;
01131
01132   /* Check the parameters */
01133   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
01134   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
01135   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
01136   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
01137   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01138   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01139
01140   /* Disable the Channel 4: Reset the CC4E Bit */
01141   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
01142
01143   /* Get the TIMx CCER register value */
01144   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
01145
01146   /* Get the TIMx CR2 register value */
01147   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
01148
01149   /* Get the TIMx CCMR2 register value */
01150   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
01151
01152   /* Reset Capture/Compare selection Bits */
01153   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
01154
01155   /* Select the Output Compare Mode */
01156   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
01157
01158   /* Set the Output Compare Polarity */
01159   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
01160
01161   /* Set the Output State */
01162   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
01163
01164   if (IS_TIM_BREAK_INSTANCE(TIMx))
01165   {
01166     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01167     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01168
01169 #if defined(STM32F373xC) || defined(STM32F378xx)
01170 #else
01171     /* Set the Output Idle state */
01172     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
01173 #endif
01174   }
01175
01176   /* Write to TIMx CR2 */
01177   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
01178
01179   /* Write to TIMx CCMR2 */
01180   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
01181
01182   /* Set the Capture Compare Register value */
01183   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
01184
01185   /* Write to TIMx CCER */
01186   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01187
01188   return SUCCESS;
01189 }
01190
01191 #if defined(TIM_CCER_CC5E)
01192 /**
01193   * @brief  Configure the TIMx output channel 5.
01194   * @param  TIMx Timer Instance
01195   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
01196   * @note   OC5 is not available for all F3 devices
01197   * @retval An ErrorStatus enumeration value:
01198   *          - SUCCESS: TIMx registers are de-initialized
01199   *          - ERROR: not applicable
01200   */
01201 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
01202 {
01203   uint32_t tmpccmr3 = 0U;
01204   uint32_t tmpccer = 0U;
01205
01206   /* Check the parameters */
01207   assert_param(IS_TIM_CC5_INSTANCE(TIMx));
01208   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
01209   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
01210   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
01211   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01212   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01213
01214   /* Disable the Channel 5: Reset the CC5E Bit */
01215   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
01216
01217   /* Get the TIMx CCER register value */
01218   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
01219
01220   /* Get the TIMx CCMR3 register value */
01221   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
01222
01223   /* Select the Output Compare Mode */
01224   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
01225
01226   /* Set the Output Compare Polarity */
01227   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
01228
01229   /* Set the Output State */
01230   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
01231
01232   if (IS_TIM_BREAK_INSTANCE(TIMx))
01233   {
01234     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01235     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01236
01237     /* Set the Output Idle state */
01238     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
01239
01240   }
01241
01242   /* Write to TIMx CCMR3 */
01243   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
01244
01245   /* Set the Capture Compare Register value */
01246   LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
01247
01248   /* Write to TIMx CCER */
01249   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01250
01251   return SUCCESS;
01252 }
01253
01254 /**
01255   * @brief  Configure the TIMx output channel 6.
01256   * @param  TIMx Timer Instance
01257   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
01258   * @note   OC6 is not available for all F3 devices
01259   * @retval An ErrorStatus enumeration value:
01260   *          - SUCCESS: TIMx registers are de-initialized
01261   *          - ERROR: not applicable
01262   */
01263 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
01264 {
01265   uint32_t tmpccmr3 = 0U;
01266   uint32_t tmpccer = 0U;
01267
01268   /* Check the parameters */
01269   assert_param(IS_TIM_CC6_INSTANCE(TIMx));
01270   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
01271   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
01272   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
01273   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01274   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01275
01276   /* Disable the Channel 5: Reset the CC6E Bit */
01277   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
01278
01279   /* Get the TIMx CCER register value */
01280   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
01281
01282   /* Get the TIMx CCMR3 register value */
01283   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
01284
01285   /* Select the Output Compare Mode */
01286   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
01287
01288   /* Set the Output Compare Polarity */
01289   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
01290
01291   /* Set the Output State */
01292   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
01293
01294   if (IS_TIM_BREAK_INSTANCE(TIMx))
01295   {
01296     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01297     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01298
01299     /* Set the Output Idle state */
01300     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
01301   }
01302
01303   /* Write to TIMx CCMR3 */
01304   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
01305
01306   /* Set the Capture Compare Register value */
01307   LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
01308
01309   /* Write to TIMx CCER */
01310   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01311
01312   return SUCCESS;
01313 }
01314 #endif /* TIM_CCER_CC5E */
01315
01316 /**
01317   * @brief  Configure the TIMx input channel 1.
01318   * @param  TIMx Timer Instance
01319   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
01320   * @retval An ErrorStatus enumeration value:
01321   *          - SUCCESS: TIMx registers are de-initialized
01322   *          - ERROR: not applicable
01323   */
01324 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01325 {
01326   /* Check the parameters */
01327   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
01328   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01329   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01330   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01331   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01332
01333   /* Disable the Channel 1: Reset the CC1E Bit */
01334   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
01335
01336   /* Select the Input and set the filter and the prescaler value */
01337   MODIFY_REG(TIMx->CCMR1,
01338              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
01339              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
01340
01341   /* Select the Polarity and set the CC1E Bit */
01342   MODIFY_REG(TIMx->CCER,
01343              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
01344              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
01345
01346   return SUCCESS;
01347 }
01348
01349 /**
01350   * @brief  Configure the TIMx input channel 2.
01351   * @param  TIMx Timer Instance
01352   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
01353   * @retval An ErrorStatus enumeration value:
01354   *          - SUCCESS: TIMx registers are de-initialized
01355   *          - ERROR: not applicable
01356   */
01357 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01358 {
01359   /* Check the parameters */
01360   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
01361   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01362   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01363   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01364   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01365
01366   /* Disable the Channel 2: Reset the CC2E Bit */
01367   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
01368
01369   /* Select the Input and set the filter and the prescaler value */
01370   MODIFY_REG(TIMx->CCMR1,
01371              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
01372              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
01373
01374   /* Select the Polarity and set the CC2E Bit */
01375   MODIFY_REG(TIMx->CCER,
01376              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
01377              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
01378
01379   return SUCCESS;
01380 }
01381
01382 /**
01383   * @brief  Configure the TIMx input channel 3.
01384   * @param  TIMx Timer Instance
01385   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
01386   * @retval An ErrorStatus enumeration value:
01387   *          - SUCCESS: TIMx registers are de-initialized
01388   *          - ERROR: not applicable
01389   */
01390 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01391 {
01392   /* Check the parameters */
01393   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
01394   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01395   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01396   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01397   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01398
01399   /* Disable the Channel 3: Reset the CC3E Bit */
01400   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
01401
01402   /* Select the Input and set the filter and the prescaler value */
01403   MODIFY_REG(TIMx->CCMR2,
01404              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
01405              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
01406
01407   /* Select the Polarity and set the CC3E Bit */
01408   MODIFY_REG(TIMx->CCER,
01409              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
01410              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
01411
01412   return SUCCESS;
01413 }
01414
01415 /**
01416   * @brief  Configure the TIMx input channel 4.
01417   * @param  TIMx Timer Instance
01418   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
01419   * @retval An ErrorStatus enumeration value:
01420   *          - SUCCESS: TIMx registers are de-initialized
01421   *          - ERROR: not applicable
01422   */
01423 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01424 {
01425   /* Check the parameters */
01426   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
01427   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01428   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01429   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01430   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01431
01432   /* Disable the Channel 4: Reset the CC4E Bit */
01433   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
01434
01435   /* Select the Input and set the filter and the prescaler value */
01436   MODIFY_REG(TIMx->CCMR2,
01437              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
01438              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
01439
01440   /* Select the Polarity and set the CC2E Bit */
01441   MODIFY_REG(TIMx->CCER,
01442              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
01443              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
01444
01445   return SUCCESS;
01446 }
01447
01448
01449 /**
01450   * @}
01451   */
01452
01453 /**
01454   * @}
01455   */
01456
01457 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 || TIM19 || TIM20 */
01458
01459 /**
01460   * @}
01461   */
01462
01463 #endif /* USE_FULL_LL_DRIVER */
01464
01465 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_tim.h Source File

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stm32f3xx_ll_tim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_tim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TIM LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_TIM_H
00038 #define __STM32F3xx_LL_TIM_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20)
00052
00053 /** @defgroup TIM_LL TIM
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
00060   * @{
00061   */
00062 static const uint8_t OFFSET_TAB_CCMRx[] =
00063 {
00064   0x00U,   /* 0: TIMx_CH1  */
00065   0x00U,   /* 1: TIMx_CH1N */
00066   0x00U,   /* 2: TIMx_CH2  */
00067   0x00U,   /* 3: TIMx_CH2N */
00068   0x04U,   /* 4: TIMx_CH3  */
00069   0x04U,   /* 5: TIMx_CH3N */
00070   0x04U,   /* 6: TIMx_CH4  */
00071   0x3CU,   /* 7: TIMx_CH5  */
00072   0x3CU    /* 8: TIMx_CH6  */
00073 };
00074
00075 static const uint8_t SHIFT_TAB_OCxx[] =
00076 {
00077   0U,            /* 0: OC1M, OC1FE, OC1PE */
00078   0U,            /* 1: - NA */
00079   8U,            /* 2: OC2M, OC2FE, OC2PE */
00080   0U,            /* 3: - NA */
00081   0U,            /* 4: OC3M, OC3FE, OC3PE */
00082   0U,            /* 5: - NA */
00083   8U,            /* 6: OC4M, OC4FE, OC4PE */
00084   0U,            /* 7: OC5M, OC5FE, OC5PE */
00085   8U             /* 8: OC6M, OC6FE, OC6PE */
00086 };
00087
00088 static const uint8_t SHIFT_TAB_ICxx[] =
00089 {
00090   0U,            /* 0: CC1S, IC1PSC, IC1F */
00091   0U,            /* 1: - NA */
00092   8U,            /* 2: CC2S, IC2PSC, IC2F */
00093   0U,            /* 3: - NA */
00094   0U,            /* 4: CC3S, IC3PSC, IC3F */
00095   0U,            /* 5: - NA */
00096   8U,            /* 6: CC4S, IC4PSC, IC4F */
00097   0U,            /* 7: - NA */
00098   0U             /* 8: - NA */
00099 };
00100
00101 static const uint8_t SHIFT_TAB_CCxP[] =
00102 {
00103   0U,            /* 0: CC1P */
00104   2U,            /* 1: CC1NP */
00105   4U,            /* 2: CC2P */
00106   6U,            /* 3: CC2NP */
00107   8U,            /* 4: CC3P */
00108   10U,           /* 5: CC3NP */
00109   12U,           /* 6: CC4P */
00110   16U,           /* 7: CC5P */
00111   20U            /* 8: CC6P */
00112 };
00113
00114 static const uint8_t SHIFT_TAB_OISx[] =
00115 {
00116   0U,            /* 0: OIS1 */
00117   1U,            /* 1: OIS1N */
00118   2U,            /* 2: OIS2 */
00119   3U,            /* 3: OIS2N */
00120   4U,            /* 4: OIS3 */
00121   5U,            /* 5: OIS3N */
00122   6U,            /* 6: OIS4 */
00123   8U,            /* 7: OIS5 */
00124   10U            /* 8: OIS6 */
00125 };
00126 /**
00127   * @}
00128   */
00129
00130
00131 /* Private constants ---------------------------------------------------------*/
00132 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
00133   * @{
00134   */
00135
00136
00137 #define TIMx_OR_RMP_SHIFT 16U
00138 #define TIMx_OR_RMP_MASK  0x0000FFFFU
00139 #if defined(TIM1)
00140 #define TIM1_OR_RMP_MASK   (TIM1_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
00141 #endif /* TIM1 */
00142 #if defined (TIM8)
00143 #define TIM8_OR_RMP_MASK   (TIM8_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
00144 #endif /* TIM8 */
00145 #if defined(TIM14)
00146 #define TIM14_OR_RMP_MASK  (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
00147 #endif /* TIM14 */
00148 #if defined(TIM16)
00149 #define TIM16_OR_RMP_MASK  (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
00150 #endif /* TIM16 */
00151 #if defined(TIM20)
00152 #define TIM20_OR_RMP_MASK  (TIM20_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
00153 #endif /* TIM20 */
00154
00155 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
00156 #define DT_DELAY_1 ((uint8_t)0x7FU)
00157 #define DT_DELAY_2 ((uint8_t)0x3FU)
00158 #define DT_DELAY_3 ((uint8_t)0x1FU)
00159 #define DT_DELAY_4 ((uint8_t)0x1FU)
00160
00161 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
00162 #define DT_RANGE_1 ((uint8_t)0x00U)
00163 #define DT_RANGE_2 ((uint8_t)0x80U)
00164 #define DT_RANGE_3 ((uint8_t)0xC0U)
00165 #define DT_RANGE_4 ((uint8_t)0xE0U)
00166
00167
00168 /**
00169   * @}
00170   */
00171
00172 /* Private macros ------------------------------------------------------------*/
00173 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
00174   * @{
00175   */
00176 /** @brief  Convert channel id into channel index.
00177   * @param  __CHANNEL__ This parameter can be one of the following values:
00178   *         @arg @ref LL_TIM_CHANNEL_CH1
00179   *         @arg @ref LL_TIM_CHANNEL_CH1N
00180   *         @arg @ref LL_TIM_CHANNEL_CH2
00181   *         @arg @ref LL_TIM_CHANNEL_CH2N
00182   *         @arg @ref LL_TIM_CHANNEL_CH3
00183   *         @arg @ref LL_TIM_CHANNEL_CH3N
00184   *         @arg @ref LL_TIM_CHANNEL_CH4
00185   *         @arg @ref LL_TIM_CHANNEL_CH5
00186   *         @arg @ref LL_TIM_CHANNEL_CH6
00187   * @note   CH5 and CH6 channels are not available for all F3 devices
00188   * @retval none
00189   */
00190 #if defined(TIM_CCR5_CCR5)
00191 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
00192 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
00193 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
00194 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
00195 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
00196 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
00197 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
00198 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
00199 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
00200 #else
00201 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
00202 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
00203 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
00204 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
00205 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
00206 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
00207 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
00208 #endif
00209
00210 /** @brief  Calculate the deadtime sampling period(in ps).
00211   * @param  __TIMCLK__ timer input clock frequency (in Hz).
00212   * @param  __CKD__ This parameter can be one of the following values:
00213   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
00214   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
00215   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
00216   * @retval none
00217   */
00218 #define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
00219     (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
00220      ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
00221      ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
00222 /**
00223   * @}
00224   */
00225
00226
00227 /* Exported types ------------------------------------------------------------*/
00228 #if defined(USE_FULL_LL_DRIVER)
00229 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
00230   * @{
00231   */
00232
00233 /**
00234   * @brief  TIM Time Base configuration structure definition.
00235   */
00236 typedef struct
00237 {
00238   uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00239                                    This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00240
00241                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
00242
00243   uint32_t CounterMode;       /*!< Specifies the counter mode.
00244                                    This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
00245
00246                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
00247
00248   uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
00249                                    Auto-Reload Register at the next update event.
00250                                    This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00251                                    Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
00252
00253                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
00254
00255   uint32_t ClockDivision;     /*!< Specifies the clock division.
00256                                    This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
00257
00258                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
00259
00260   uint8_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00261                                    reaches zero, an update event is generated and counting restarts
00262                                    from the RCR value (N).
00263                                    This means in PWM mode that (N+1) corresponds to:
00264                                       - the number of PWM periods in edge-aligned mode
00265                                       - the number of half PWM period in center-aligned mode
00266                                    This parameter must be a number between 0x00 and 0xFF.
00267
00268                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
00269 } LL_TIM_InitTypeDef;
00270
00271 /**
00272   * @brief  TIM Output Compare configuration structure definition.
00273   */
00274 typedef struct
00275 {
00276   uint32_t OCMode;        /*!< Specifies the output mode.
00277                                This parameter can be a value of @ref TIM_LL_EC_OCMODE.
00278
00279                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
00280
00281   uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
00282                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
00283
00284                                This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
00285
00286   uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
00287                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
00288
00289                                This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
00290
00291   uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
00292                                This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00293
00294                                This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
00295
00296   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00297                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
00298
00299                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
00300
00301   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00302                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
00303
00304                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
00305
00306
00307   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00308                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
00309
00310                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
00311
00312   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00313                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
00314
00315                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
00316 } LL_TIM_OC_InitTypeDef;
00317
00318 /**
00319   * @brief  TIM Input Capture configuration structure definition.
00320   */
00321
00322 typedef struct
00323 {
00324
00325   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00326                                This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00327
00328                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00329
00330   uint32_t ICActiveInput; /*!< Specifies the input.
00331                                This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00332
00333                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00334
00335   uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
00336                                This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00337
00338                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00339
00340   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00341                                This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00342
00343                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00344 } LL_TIM_IC_InitTypeDef;
00345
00346
00347 /**
00348   * @brief  TIM Encoder interface configuration structure definition.
00349   */
00350 typedef struct
00351 {
00352   uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
00353                                  This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
00354
00355                                  This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
00356
00357   uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
00358                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00359
00360                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00361
00362   uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
00363                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00364
00365                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00366
00367   uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
00368                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00369
00370                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00371
00372   uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
00373                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00374
00375                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00376
00377   uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
00378                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00379
00380                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00381
00382   uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
00383                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00384
00385                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00386
00387   uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
00388                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00389
00390                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00391
00392   uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
00393                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00394
00395                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00396
00397 } LL_TIM_ENCODER_InitTypeDef;
00398
00399 /**
00400   * @brief  TIM Hall sensor interface configuration structure definition.
00401   */
00402 typedef struct
00403 {
00404
00405   uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
00406                                     This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00407
00408                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00409
00410   uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
00411                                     Prescaler must be set to get a maximum counter period longer than the
00412                                     time interval between 2 consecutive changes on the Hall inputs.
00413                                     This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00414
00415                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00416
00417   uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
00418                                     This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00419
00420                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00421
00422   uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
00423                                     A positive pulse (TRGO event) is generated with a programmable delay every time
00424                                     a change occurs on the Hall inputs.
00425                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
00426
00427                                     This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
00428 } LL_TIM_HALLSENSOR_InitTypeDef;
00429
00430 /**
00431   * @brief  BDTR (Break and Dead Time) structure definition
00432   */
00433 typedef struct
00434 {
00435   uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
00436                                       This parameter can be a value of @ref TIM_LL_EC_OSSR
00437
00438                                       This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
00439
00440                                       @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
00441
00442   uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
00443                                       This parameter can be a value of @ref TIM_LL_EC_OSSI
00444
00445                                       This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
00446
00447                                       @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
00448
00449   uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
00450                                       This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
00451
00452                                       @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
00453                                             has been written, their content is frozen until the next reset.*/
00454
00455   uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
00456                                       switching-on of the outputs.
00457                                       This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00458
00459                                       This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
00460
00461                                       @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
00462
00463   uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
00464                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
00465
00466                                       This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
00467
00468                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00469
00470   uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
00471                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
00472
00473                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
00474
00475                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00476
00477 #if defined(TIM_BDTR_BKF)
00478   uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
00479                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
00480
00481                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
00482
00483                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00484
00485 #endif /* TIM_BDTR_BKF */
00486 #if defined(TIM_BDTR_BK2E)
00487   uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
00488                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
00489
00490                                       This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
00491
00492                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00493
00494   uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
00495                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
00496
00497                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
00498
00499                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00500
00501   uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
00502                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
00503
00504                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
00505
00506                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00507
00508 #endif /* TIM_BDTR_BK2E */
00509   uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
00510                                       This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
00511
00512                                       This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
00513
00514                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00515 } LL_TIM_BDTR_InitTypeDef;
00516
00517 /**
00518   * @}
00519   */
00520 #endif /* USE_FULL_LL_DRIVER */
00521
00522 /* Exported constants --------------------------------------------------------*/
00523 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
00524   * @{
00525   */
00526
00527 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
00528   * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
00529   * @{
00530   */
00531 #define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
00532 #define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
00533 #define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
00534 #define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
00535 #define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
00536 #if defined(TIM_CCMR1_OC1M_3)
00537 #define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */
00538 #define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */
00539 #endif /* TIM_CCMR1_OC1M_3 */
00540 #define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
00541 #define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
00542 #define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
00543 #define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */
00544 #define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
00545 #define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
00546 #define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
00547 #define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
00548 /**
00549   * @}
00550   */
00551
00552 #if defined(USE_FULL_LL_DRIVER)
00553 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
00554   * @{
00555   */
00556 #define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
00557 #define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
00558 /**
00559   * @}
00560   */
00561 #if defined(TIM_BDTR_BK2E)
00562
00563 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
00564   * @{
00565   */
00566 #define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
00567 #define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
00568 /**
00569   * @}
00570   */
00571 #endif /* TIM_BDTR_BK2E */
00572
00573 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
00574   * @{
00575   */
00576 #define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
00577 #define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
00578 /**
00579   * @}
00580   */
00581 #endif /* USE_FULL_LL_DRIVER */
00582
00583 /** @defgroup TIM_LL_EC_IT IT Defines
00584   * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
00585   * @{
00586   */
00587 #define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
00588 #define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
00589 #define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
00590 #define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
00591 #define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
00592 #define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
00593 #define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
00594 #define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
00595 /**
00596   * @}
00597   */
00598
00599 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
00600   * @{
00601   */
00602 #define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
00603 #define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
00604 /**
00605   * @}
00606   */
00607
00608 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
00609   * @{
00610   */
00611 #define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter is not stopped at update event */
00612 #define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter stops counting at the next update event */
00613 /**
00614   * @}
00615   */
00616
00617 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
00618   * @{
00619   */
00620 #define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
00621 #define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
00622 #define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
00623 #define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
00624 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
00625 /**
00626   * @}
00627   */
00628
00629 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
00630   * @{
00631   */
00632 #define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
00633 #define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
00634 #define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
00635 /**
00636   * @}
00637   */
00638
00639 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
00640   * @{
00641   */
00642 #define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
00643 #define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
00644 /**
00645   * @}
00646   */
00647
00648 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
00649   * @{
00650   */
00651 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
00652 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
00653 /**
00654   * @}
00655   */
00656
00657 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
00658   * @{
00659   */
00660 #define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
00661 #define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
00662 /**
00663   * @}
00664   */
00665
00666 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
00667   * @{
00668   */
00669 #define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
00670 #define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
00671 #define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
00672 #define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
00673 /**
00674   * @}
00675   */
00676
00677 /** @defgroup TIM_LL_EC_CHANNEL Channel
00678   * @{
00679   */
00680 #if defined(TIM_CCMR1_OC1M_3)
00681 #define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
00682 #define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
00683 #define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
00684 #define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
00685 #define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
00686 #define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
00687 #define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
00688 #define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
00689 #define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
00690 #else
00691 #define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
00692 #define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
00693 #define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
00694 #define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
00695 #define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
00696 #define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
00697 #define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
00698 #endif
00699 /**
00700   * @}
00701   */
00702
00703 #if defined(USE_FULL_LL_DRIVER)
00704 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
00705   * @{
00706   */
00707 #define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
00708 #define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
00709 /**
00710   * @}
00711   */
00712 #endif /* USE_FULL_LL_DRIVER */
00713
00714 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
00715   * @{
00716   */
00717 #define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
00718 #define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
00719 #define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
00720 #define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
00721 #define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                       /*!<OCyREF is forced low*/
00722 #define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
00723 #define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
00724 #define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
00725 #if defined(TIM_CCMR1_OC1M_3)
00726 #define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/
00727 #define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/
00728 #endif
00729 #if defined(TIM_CCMR1_OC1M_3)
00730 #define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/
00731 #define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
00732 #endif
00733 #if defined(TIM_CCMR1_OC1M_3)
00734 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
00735 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
00736 #endif
00737 /**
00738   * @}
00739   */
00740
00741 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
00742   * @{
00743   */
00744 #define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
00745 #define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
00746 /**
00747   * @}
00748   */
00749
00750 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
00751   * @{
00752   */
00753 #define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
00754 #define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
00755 /**
00756   * @}
00757   */
00758
00759 #if defined(TIM_CCR5_CCR5)
00760 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
00761   * @{
00762   */
00763 #define LL_TIM_GROUPCH5_NONE                   0x00000000U           /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
00764 #define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
00765 #define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
00766 #define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
00767 /**
00768   * @}
00769   */
00770 #endif /* TIM_CCR5_CCR5 */
00771
00772 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
00773   * @{
00774   */
00775 #define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
00776 #define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
00777 #define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
00778 /**
00779   * @}
00780   */
00781
00782 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
00783   * @{
00784   */
00785 #define LL_TIM_ICPSC_DIV1                      0x00000000U                              /*!< No prescaler, capture is done each time an edge is detected on the capture input */
00786 #define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
00787 #define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
00788 #define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
00789 /**
00790   * @}
00791   */
00792
00793 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
00794   * @{
00795   */
00796 #define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
00797 #define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
00798 #define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
00799 #define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
00800 #define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
00801 #define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
00802 #define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
00803 #define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
00804 #define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
00805 #define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
00806 #define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
00807 #define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
00808 #define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
00809 #define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
00810 #define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
00811 #define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
00812 /**
00813   * @}
00814   */
00815
00816 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
00817   * @{
00818   */
00819 #define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
00820 #define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
00821 #define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
00822 /**
00823   * @}
00824   */
00825
00826 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
00827   * @{
00828   */
00829 #define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
00830 #define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected inpu t*/
00831 #define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
00832 /**
00833   * @}
00834   */
00835
00836 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
00837   * @{
00838   */
00839 #define LL_TIM_ENCODERMODE_X2_TI1              TIM_SMCR_SMS_0                    /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
00840 #define LL_TIM_ENCODERMODE_X2_TI2              TIM_SMCR_SMS_1                    /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
00841 #define LL_TIM_ENCODERMODE_X4_TI12             (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges                                                                                                                                                                   depending on the level of the other input l */
00842 /**
00843   * @}
00844   */
00845
00846 /** @defgroup TIM_LL_EC_TRGO Trigger Output
00847   * @{
00848   */
00849 #define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
00850 #define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
00851 #define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
00852 #define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
00853 #define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
00854 #define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
00855 #define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
00856 #define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
00857 /**
00858   * @}
00859   */
00860
00861 #if   defined(TIM_CR2_MMS2)
00862 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
00863   * @{
00864   */
00865 #define LL_TIM_TRGO2_RESET                     0x00000000U                                                         /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
00866 #define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
00867 #define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */
00868 #define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */
00869 #define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */
00870 #define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */
00871 #define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */
00872 #define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */
00873 #define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */
00874 #define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */
00875 #define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */
00876 #define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */
00877 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
00878 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
00879 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
00880 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
00881 /**
00882   * @}
00883   */
00884 #endif /* TIM_CR2_MMS2 */
00885
00886 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
00887   * @{
00888   */
00889 #define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
00890 #define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
00891 #define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
00892 #define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
00893 #if  defined (TIM_SMCR_SMS_3)
00894 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */
00895 #endif /* TIM_SMCR_SMS_3 */
00896 /**
00897   * @}
00898   */
00899
00900 /** @defgroup TIM_LL_EC_TS Trigger Selection
00901   * @{
00902   */
00903 #define LL_TIM_TS_ITR0                         0x00000000U                                      /*!< Internal Trigger 0 (ITR0) is used as trigger input */
00904 #define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                    /*!< Internal Trigger 1 (ITR1) is used as trigger input */
00905 #define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                    /*!< Internal Trigger 2 (ITR2) is used as trigger input */
00906 #define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                  /*!< Internal Trigger 3 (ITR3) is used as trigger input */
00907 #define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                    /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
00908 #define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                  /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
00909 #define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                  /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
00910 #define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)  /*!< Filtered external Trigger (ETRF) is used as trigger input */
00911 /**
00912   * @}
00913   */
00914
00915 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
00916   * @{
00917   */
00918 #define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
00919 #define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
00920 /**
00921   * @}
00922   */
00923
00924 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
00925   * @{
00926   */
00927 #define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
00928 #define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
00929 #define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
00930 #define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
00931 /**
00932   * @}
00933   */
00934
00935 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
00936   * @{
00937   */
00938 #define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
00939 #define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
00940 #define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
00941 #define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
00942 #define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
00943 #define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
00944 #define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
00945 #define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
00946 #define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
00947 #define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
00948 #define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
00949 #define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
00950 #define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
00951 #define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
00952 #define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
00953 #define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
00954 /**
00955   * @}
00956   */
00957
00958
00959 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
00960   * @{
00961   */
00962 #define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
00963 #define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
00964 /**
00965   * @}
00966   */
00967
00968 #if defined(TIM_BDTR_BKF)
00969 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
00970   * @{
00971   */
00972 #define LL_TIM_BREAK_FILTER_FDIV1              0x00000000U   /*!< No filter, BRK acts asynchronously */
00973 #define LL_TIM_BREAK_FILTER_FDIV1_N2           0x00010000U   /*!< fSAMPLING=fCK_INT, N=2 */
00974 #define LL_TIM_BREAK_FILTER_FDIV1_N4           0x00020000U   /*!< fSAMPLING=fCK_INT, N=4 */
00975 #define LL_TIM_BREAK_FILTER_FDIV1_N8           0x00030000U   /*!< fSAMPLING=fCK_INT, N=8 */
00976 #define LL_TIM_BREAK_FILTER_FDIV2_N6           0x00040000U   /*!< fSAMPLING=fDTS/2, N=6 */
00977 #define LL_TIM_BREAK_FILTER_FDIV2_N8           0x00050000U   /*!< fSAMPLING=fDTS/2, N=8 */
00978 #define LL_TIM_BREAK_FILTER_FDIV4_N6           0x00060000U   /*!< fSAMPLING=fDTS/4, N=6 */
00979 #define LL_TIM_BREAK_FILTER_FDIV4_N8           0x00070000U   /*!< fSAMPLING=fDTS/4, N=8 */
00980 #define LL_TIM_BREAK_FILTER_FDIV8_N6           0x00080000U   /*!< fSAMPLING=fDTS/8, N=6 */
00981 #define LL_TIM_BREAK_FILTER_FDIV8_N8           0x00090000U   /*!< fSAMPLING=fDTS/8, N=8 */
00982 #define LL_TIM_BREAK_FILTER_FDIV16_N5          0x000A0000U   /*!< fSAMPLING=fDTS/16, N=5 */
00983 #define LL_TIM_BREAK_FILTER_FDIV16_N6          0x000B0000U   /*!< fSAMPLING=fDTS/16, N=6 */
00984 #define LL_TIM_BREAK_FILTER_FDIV16_N8          0x000C0000U   /*!< fSAMPLING=fDTS/16, N=8 */
00985 #define LL_TIM_BREAK_FILTER_FDIV32_N5          0x000D0000U   /*!< fSAMPLING=fDTS/32, N=5 */
00986 #define LL_TIM_BREAK_FILTER_FDIV32_N6          0x000E0000U   /*!< fSAMPLING=fDTS/32, N=6 */
00987 #define LL_TIM_BREAK_FILTER_FDIV32_N8          0x000F0000U   /*!< fSAMPLING=fDTS/32, N=8 */
00988 /**
00989   * @}
00990   */
00991 #endif /* TIM_BDTR_BKF */
00992
00993 #if defined(TIM_BDTR_BK2P)
00994 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
00995   * @{
00996   */
00997 #define LL_TIM_BREAK2_POLARITY_LOW             0x00000000U             /*!< Break input BRK2 is active low */
00998 #define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           /*!< Break input BRK2 is active high */
00999 /**
01000   * @}
01001   */
01002 #endif /* TIM_BDTR_BK2P */
01003
01004 #if defined(TIM_BDTR_BK2F)
01005 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
01006   * @{
01007   */
01008 #define LL_TIM_BREAK2_FILTER_FDIV1             0x00000000U   /*!< No filter, BRK acts asynchronously */
01009 #define LL_TIM_BREAK2_FILTER_FDIV1_N2          0x00100000U   /*!< fSAMPLING=fCK_INT, N=2 */
01010 #define LL_TIM_BREAK2_FILTER_FDIV1_N4          0x00200000U   /*!< fSAMPLING=fCK_INT, N=4 */
01011 #define LL_TIM_BREAK2_FILTER_FDIV1_N8          0x00300000U   /*!< fSAMPLING=fCK_INT, N=8 */
01012 #define LL_TIM_BREAK2_FILTER_FDIV2_N6          0x00400000U   /*!< fSAMPLING=fDTS/2, N=6 */
01013 #define LL_TIM_BREAK2_FILTER_FDIV2_N8          0x00500000U   /*!< fSAMPLING=fDTS/2, N=8 */
01014 #define LL_TIM_BREAK2_FILTER_FDIV4_N6          0x00600000U   /*!< fSAMPLING=fDTS/4, N=6 */
01015 #define LL_TIM_BREAK2_FILTER_FDIV4_N8          0x00700000U   /*!< fSAMPLING=fDTS/4, N=8 */
01016 #define LL_TIM_BREAK2_FILTER_FDIV8_N6          0x00800000U   /*!< fSAMPLING=fDTS/8, N=6 */
01017 #define LL_TIM_BREAK2_FILTER_FDIV8_N8          0x00900000U   /*!< fSAMPLING=fDTS/8, N=8 */
01018 #define LL_TIM_BREAK2_FILTER_FDIV16_N5         0x00A00000U   /*!< fSAMPLING=fDTS/16, N=5 */
01019 #define LL_TIM_BREAK2_FILTER_FDIV16_N6         0x00B00000U   /*!< fSAMPLING=fDTS/16, N=6 */
01020 #define LL_TIM_BREAK2_FILTER_FDIV16_N8         0x00C00000U   /*!< fSAMPLING=fDTS/16, N=8 */
01021 #define LL_TIM_BREAK2_FILTER_FDIV32_N5         0x00D00000U   /*!< fSAMPLING=fDTS/32, N=5 */
01022 #define LL_TIM_BREAK2_FILTER_FDIV32_N6         0x00E00000U   /*!< fSAMPLING=fDTS/32, N=6 */
01023 #define LL_TIM_BREAK2_FILTER_FDIV32_N8         0x00F00000U   /*!< fSAMPLING=fDTS/32, N=8 */
01024 /**
01025   * @}
01026   */
01027 #endif /* TIM_BDTR_BK2F */
01028
01029 /** @defgroup TIM_LL_EC_OSSI OSSI
01030   * @{
01031   */
01032 #define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
01033 #define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
01034 /**
01035   * @}
01036   */
01037
01038 /** @defgroup TIM_LL_EC_OSSR OSSR
01039   * @{
01040   */
01041 #define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
01042 #define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
01043 /**
01044   * @}
01045   */
01046
01047
01048 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
01049   * @{
01050   */
01051 #define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
01052 #define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
01053 #define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
01054 #define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
01055 #define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
01056 #define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
01057 #define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
01058 #define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
01059 #define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
01060 #define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
01061 #define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
01062 #define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
01063 #define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
01064 #define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
01065 #define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
01066 #define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
01067 #define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
01068 #define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
01069 #define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
01070 #if defined(TIM_CCR6_CCR6)
01071 #define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
01072 #define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)                                  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
01073 #endif /* TIM_CCR6_CCR6 */
01074 #define LL_TIM_DMABURST_BASEADDR_OR            (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_OR register is the DMA base address for DMA burst */
01075 /**
01076   * @}
01077   */
01078
01079 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
01080   * @{
01081   */
01082 #define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
01083 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
01084 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
01085 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
01086 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
01087 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
01088 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
01089 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
01090 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
01091 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
01092 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
01093 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
01094 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
01095 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
01096 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
01097 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
01098 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
01099 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
01100 /**
01101   * @}
01102   */
01103
01104 #if defined(TIM1)
01105 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP  TIM1 External Trigger ADC1 Remap
01106   * @{
01107   */
01108 #define LL_TIM_TIM1_ETR_ADC1_RMP_NC   TIM1_OR_RMP_MASK                                            /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */
01109 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR_ETR_RMP_0 | TIM1_OR_RMP_MASK)                      /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */
01110 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR_ETR_RMP_1 | TIM1_OR_RMP_MASK)                      /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */
01111 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR_ETR_RMP_0 | TIM1_OR_ETR_RMP_1| TIM1_OR_RMP_MASK)   /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */
01112 /**
01113   * @}
01114   */
01115 #if defined(ADC4)
01116 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC4_RMP  TIM1 External Trigger ADC4 Remap
01117   * @{
01118   */
01119 #define LL_TIM_TIM1_ETR_ADC4_RMP_NC   TIM1_OR_RMP_MASK                                             /*!< TIM1_ETR is not connected to ADC4 analog watchdog  x*/
01120 #define LL_TIM_TIM1_ETR_ADC4_RMP_AWD1 (TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK)                       /*!< TIM1_ETR is connected to ADC4 analog watchdog 1 */
01121 #define LL_TIM_TIM1_ETR_ADC4_RMP_AWD2 (TIM1_OR_ETR_RMP_3 | TIM1_OR_RMP_MASK)                       /*!< TIM1_ETR is connected to ADC4 analog watchdog 2 */
01122 #define LL_TIM_TIM1_ETR_ADC4_RMP_AWD3 (TIM1_OR_ETR_RMP_3 | TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK)   /*!< TIM1_ETR is connected to ADC4 analog watchdog 3 */
01123 /**
01124   * @}
01125   */
01126 #else
01127 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC2_RMP  TIM1 External Trigger ADC3 Remap
01128   * @{
01129   */
01130 #define LL_TIM_TIM1_ETR_ADC2_RMP_NC   TIM1_OR_RMP_MASK                                             /*!< TIM1_ETR is not connected to ADC2 analog watchdog  x*/
01131 #define LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK)                       /*!< TIM1_ETR is connected to ADC2 analog watchdog 1 */
01132 #define LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (TIM1_OR_ETR_RMP_3 | TIM1_OR_RMP_MASK)                       /*!< TIM1_ETR is connected to ADC2 analog watchdog 2 */
01133 #define LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (TIM1_OR_ETR_RMP_3 | TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK)   /*!< TIM1_ETR is connected to ADC2 analog watchdog 3 */
01134 /**
01135   * @}
01136   */
01137 #endif /* ADC4 */
01138 #endif /* TIM1 */
01139 #if defined(TIM8)
01140 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP  TIM8 External Trigger ADC2 Remap
01141   * @{
01142   */
01143 #define LL_TIM_TIM8_ETR_ADC2_RMP_NC   TIM8_OR_RMP_MASK                                             /*!< TIM8_ETR is not connected to ADC2 analog watchdog x */
01144 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR_ETR_RMP_0 | TIM8_OR_RMP_MASK)                       /*!< TIM8_ETR is connected to ADC2 analog watchdog */
01145 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR_ETR_RMP_1 | TIM8_OR_RMP_MASK)                       /*!< TIM8_ETR is connected to ADC2 analog watchdog 2 */
01146 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR_ETR_RMP_0 | TIM8_OR_ETR_RMP_1 | TIM8_OR_RMP_MASK)   /*!< TIM8_ETR is connected to ADC2 analog watchdog 3 */
01147 /**
01148   * @}
01149   */
01150
01151 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP  TIM8 External Trigger ADC3 Remap
01152   * @{
01153   */
01154 #define LL_TIM_TIM8_ETR_ADC3_RMP_NC   TIM8_OR_RMP_MASK                                             /*!< TIM8_ETR is not connected to ADC3 analog watchdog x */
01155 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR_ETR_RMP_2 | TIM8_OR_RMP_MASK)                       /*!< TIM8_ETR is connected to ADC3 analog watchdog 1 */
01156 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR_ETR_RMP_3 | TIM8_OR_RMP_MASK)                       /*!< TIM8_ETR is connected to ADC3 analog watchdog 2 */
01157 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR_ETR_RMP_2 | TIM8_OR_ETR_RMP_3 | TIM8_OR_RMP_MASK)   /*!< TIM8_ETR is connected to ADC3 analog watchdog 3 */
01158 /**
01159   * @}
01160   */
01161 #endif /* TIM8 */
01162 #if defined(TIM16)
01163 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 External Input Ch1 Remap
01164   * @{
01165   */
01166 #define LL_TIM_TIM16_TI1_RMP_GPIO    0x00000000U                                                   /*!< TIM16 input capture 1 is connected to GPIO */
01167 #define LL_TIM_TIM16_TI1_RMP_RTC     (TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK)                      /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */
01168 #define LL_TIM_TIM16_TI1_RMP_HSE_32  (TIM16_OR_TI1_RMP_1 | TIM16_OR_RMP_MASK)                      /*!< TIM16 input capture 1 is connected to HSE/32 clock */
01169 #define LL_TIM_TIM16_TI1_RMP_MCO     (TIM16_OR_TI1_RMP_1 | TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to MCO */
01170 /**
01171   * @}
01172   */
01173 #endif /* TIM16 */
01174 #if defined(TIM20)
01175 /** @defgroup TIM_LL_EC_TIM20_ETR_ADC3_RMP  TIM20 External Trigger ADC3 Remap
01176   * @{
01177   */
01178 #define LL_TIM_TIM20_ETR_ADC3_RMP_NC   TIM20_OR_RMP_MASK                                               /*!< TIM20_ETR is not connected to ADC3 analog watchdog x */
01179 #define LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (TIM20_OR_ETR_RMP_0 | TIM20_OR_RMP_MASK)                        /*!< TIM20_ETR is connected to ADC3 analog watchdog */
01180 #define LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (TIM20_OR_ETR_RMP_1 | TIM20_OR_RMP_MASK)                        /*!< TIM20_ETR is connected to ADC3 analog watchdog 2 */
01181 #define LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (TIM20_OR_ETR_RMP_0 | TIM20_OR_ETR_RMP_1 | TIM20_OR_RMP_MASK)   /*!< TIM20_ETR is connected to ADC3 analog watchdog 3 */
01182 /**
01183   * @}
01184   */
01185
01186 /** @defgroup TIM_LL_EC_TIM20_ETR_ADC4_RMP  TIM20 External Trigger ADC4 Remap
01187   * @{
01188   */
01189 #define LL_TIM_TIM20_ETR_ADC4_RMP_NC   TIM20_OR_RMP_MASK                                               /*!< TIM20_ETR is not connected to ADC4 analog watchdog x */
01190 #define LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (TIM20_OR_ETR_RMP_2 | TIM20_OR_RMP_MASK)                        /*!< TIM20_ETR is connected to ADC4 analog watchdog 1 */
01191 #define LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (TIM20_OR_ETR_RMP_3 | TIM20_OR_RMP_MASK)                        /*!< TIM20_ETR is connected to ADC4 analog watchdog 2 */
01192 #define LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (TIM20_OR_ETR_RMP_2 | TIM20_OR_ETR_RMP_3 | TIM20_OR_RMP_MASK)   /*!< TIM20_ETR is connected to ADC4 analog watchdog 3 */
01193 /**
01194   * @}
01195   */
01196 #endif /* TIM20 */
01197 #if defined(TIM14)
01198 /** @defgroup TIM_LL_EC_TIM14_TI1_RMP  TIM14 Timer Input1 Remap
01199   * @{
01200   */
01201 #define LL_TIM_TIM14_TI1_RMP_GPIO    TIM14_OR_RMP_MASK                                               /*!< TIM14_TI1 is connected to GPIO */
01202 #define LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 | TIM14_OR_RMP_MASK)                        /*!< TIM14_TI1 is connected to RTC Clock */
01203 #define LL_TIM_TIM14_TI1_RMP_HSE     (TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK)                        /*!< TIM14_TI1 is connected to HSE/32 */
01204 #define LL_TIM_TIM14_TI1_RMP_MCO     (TIM14_OR_TI1_RMP_0 | TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK)   /*!< TIM14_TI1 is connected to MCO */
01205 /**
01206   * @}
01207   */
01208 #endif /* TIM14 */
01209
01210 #if defined(TIM_SMCR_OCCS)
01211 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
01212   * @{
01213   */
01214 #define LL_TIM_OCREF_CLR_INT_OCREF_CLR     0x00000000U         /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
01215 #define LL_TIM_OCREF_CLR_INT_ETR           TIM_SMCR_OCCS       /*!< OCREF_CLR_INT is connected to ETRF */
01216 /**
01217   * @}
01218   */
01219 #endif /* TIM_SMCR_OCCS*/
01220
01221 /**
01222   * @}
01223   */
01224
01225 /* Exported macro ------------------------------------------------------------*/
01226 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
01227   * @{
01228   */
01229
01230 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
01231   * @{
01232   */
01233 /**
01234   * @brief  Write a value in TIM register.
01235   * @param  __INSTANCE__ TIM Instance
01236   * @param  __REG__ Register to be written
01237   * @param  __VALUE__ Value to be written in the register
01238   * @retval None
01239   */
01240 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
01241
01242 /**
01243   * @brief  Read a value in TIM register.
01244   * @param  __INSTANCE__ TIM Instance
01245   * @param  __REG__ Register to be read
01246   * @retval Register value
01247   */
01248 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
01249 /**
01250   * @}
01251   */
01252
01253 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
01254   * @{
01255   */
01256 /**
01257   * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
01258   * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
01259   * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
01260   *        to TIMx_CNT register bit 31)
01261   * @param  __CNT__ Counter value
01262   * @retval UIF status bit
01263   */
01264 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
01265    (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
01266
01267 /**
01268   * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
01269   * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
01270   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01271   * @param  __CKD__ This parameter can be one of the following values:
01272   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01273   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01274   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01275   * @param  __DT__ deadtime duration (in ns)
01276   * @retval DTG[0:7]
01277   */
01278 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
01279     ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))           ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :                                               \
01280       (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
01281       (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
01282       (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
01283        0U)
01284
01285 /**
01286   * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
01287   * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
01288   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01289   * @param  __CNTCLK__ counter clock frequency (in Hz)
01290   * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
01291   */
01292 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
01293    ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
01294
01295 /**
01296   * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
01297   * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
01298   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01299   * @param  __PSC__ prescaler
01300   * @param  __FREQ__ output signal frequency (in Hz)
01301   * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
01302   */
01303 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
01304      (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
01305
01306 /**
01307   * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
01308   * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
01309   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01310   * @param  __PSC__ prescaler
01311   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01312   * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
01313   */
01314 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
01315 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
01316           / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
01317
01318 /**
01319   * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
01320   * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
01321   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01322   * @param  __PSC__ prescaler
01323   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01324   * @param  __PULSE__ pulse duration (in us)
01325   * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
01326   */
01327 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
01328  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
01329            + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
01330
01331 /**
01332   * @brief  HELPER macro retrieving the ratio of the input capture prescaler
01333   * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
01334   * @param  __ICPSC__ This parameter can be one of the following values:
01335   *         @arg @ref LL_TIM_ICPSC_DIV1
01336   *         @arg @ref LL_TIM_ICPSC_DIV2
01337   *         @arg @ref LL_TIM_ICPSC_DIV4
01338   *         @arg @ref LL_TIM_ICPSC_DIV8
01339   * @retval Input capture prescaler ratio (1, 2, 4 or 8)
01340   */
01341 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
01342    ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
01343
01344
01345 /**
01346   * @}
01347   */
01348
01349
01350 /**
01351   * @}
01352   */
01353
01354 /* Exported functions --------------------------------------------------------*/
01355 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
01356   * @{
01357   */
01358
01359 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
01360   * @{
01361   */
01362 /**
01363   * @brief  Enable timer counter.
01364   * @rmtoll CR1          CEN           LL_TIM_EnableCounter
01365   * @param  TIMx Timer instance
01366   * @retval None
01367   */
01368 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
01369 {
01370   SET_BIT(TIMx->CR1, TIM_CR1_CEN);
01371 }
01372
01373 /**
01374   * @brief  Disable timer counter.
01375   * @rmtoll CR1          CEN           LL_TIM_DisableCounter
01376   * @param  TIMx Timer instance
01377   * @retval None
01378   */
01379 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
01380 {
01381   CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
01382 }
01383
01384 /**
01385   * @brief  Indicates whether the timer counter is enabled.
01386   * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
01387   * @param  TIMx Timer instance
01388   * @retval State of bit (1 or 0).
01389   */
01390 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
01391 {
01392   return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
01393 }
01394
01395 /**
01396   * @brief  Enable update event generation.
01397   * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
01398   * @param  TIMx Timer instance
01399   * @retval None
01400   */
01401 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
01402 {
01403   CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
01404 }
01405
01406 /**
01407   * @brief  Disable update event generation.
01408   * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
01409   * @param  TIMx Timer instance
01410   * @retval None
01411   */
01412 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
01413 {
01414   SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
01415 }
01416
01417 /**
01418   * @brief  Indicates whether update event generation is enabled.
01419   * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
01420   * @param  TIMx Timer instance
01421   * @retval State of bit (1 or 0).
01422   */
01423 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
01424 {
01425   return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
01426 }
01427
01428 /**
01429   * @brief  Set update event source
01430   * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
01431   *       generate an update interrupt or DMA request if enabled:
01432   *        - Counter overflow/underflow
01433   *        - Setting the UG bit
01434   *        - Update generation through the slave mode controller
01435   * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
01436   *       overflow/underflow generates an update interrupt or DMA request if enabled.
01437   * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
01438   * @param  TIMx Timer instance
01439   * @param  UpdateSource This parameter can be one of the following values:
01440   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
01441   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
01442   * @retval None
01443   */
01444 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
01445 {
01446   MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
01447 }
01448
01449 /**
01450   * @brief  Get actual event update source
01451   * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
01452   * @param  TIMx Timer instance
01453   * @retval Returned value can be one of the following values:
01454   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
01455   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
01456   */
01457 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
01458 {
01459   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
01460 }
01461
01462 /**
01463   * @brief  Set one pulse mode (one shot v.s. repetitive).
01464   * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
01465   * @param  TIMx Timer instance
01466   * @param  OnePulseMode This parameter can be one of the following values:
01467   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
01468   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
01469   * @retval None
01470   */
01471 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
01472 {
01473   MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
01474 }
01475
01476 /**
01477   * @brief  Get actual one pulse mode.
01478   * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
01479   * @param  TIMx Timer instance
01480   * @retval Returned value can be one of the following values:
01481   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
01482   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
01483   */
01484 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
01485 {
01486   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
01487 }
01488
01489 /**
01490   * @brief  Set the timer counter counting mode.
01491   * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
01492   *       check whether or not the counter mode selection feature is supported
01493   *       by a timer instance.
01494   * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
01495   *         CR1          CMS           LL_TIM_SetCounterMode
01496   * @param  TIMx Timer instance
01497   * @param  CounterMode This parameter can be one of the following values:
01498   *         @arg @ref LL_TIM_COUNTERMODE_UP
01499   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
01500   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
01501   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
01502   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
01503   * @retval None
01504   */
01505 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
01506 {
01507   MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
01508 }
01509
01510 /**
01511   * @brief  Get actual counter mode.
01512   * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
01513   *       check whether or not the counter mode selection feature is supported
01514   *       by a timer instance.
01515   * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
01516   *         CR1          CMS           LL_TIM_GetCounterMode
01517   * @param  TIMx Timer instance
01518   * @retval Returned value can be one of the following values:
01519   *         @arg @ref LL_TIM_COUNTERMODE_UP
01520   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
01521   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
01522   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
01523   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
01524   */
01525 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
01526 {
01527   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
01528 }
01529
01530 /**
01531   * @brief  Enable auto-reload (ARR) preload.
01532   * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
01533   * @param  TIMx Timer instance
01534   * @retval None
01535   */
01536 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
01537 {
01538   SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
01539 }
01540
01541 /**
01542   * @brief  Disable auto-reload (ARR) preload.
01543   * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
01544   * @param  TIMx Timer instance
01545   * @retval None
01546   */
01547 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
01548 {
01549   CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
01550 }
01551
01552 /**
01553   * @brief  Indicates whether auto-reload (ARR) preload is enabled.
01554   * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
01555   * @param  TIMx Timer instance
01556   * @retval State of bit (1 or 0).
01557   */
01558 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
01559 {
01560   return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
01561 }
01562
01563 /**
01564   * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
01565   * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
01566   *       whether or not the clock division feature is supported by the timer
01567   *       instance.
01568   * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
01569   * @param  TIMx Timer instance
01570   * @param  ClockDivision This parameter can be one of the following values:
01571   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01572   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01573   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01574   * @retval None
01575   */
01576 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
01577 {
01578   MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
01579 }
01580
01581 /**
01582   * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
01583   * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
01584   *       whether or not the clock division feature is supported by the timer
01585   *       instance.
01586   * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
01587   * @param  TIMx Timer instance
01588   * @retval Returned value can be one of the following values:
01589   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01590   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01591   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01592   */
01593 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
01594 {
01595   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
01596 }
01597
01598 /**
01599   * @brief  Set the counter value.
01600   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01601   *       whether or not a timer instance supports a 32 bits counter.
01602   * @rmtoll CNT          CNT           LL_TIM_SetCounter
01603   * @param  TIMx Timer instance
01604   * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
01605   * @retval None
01606   */
01607 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
01608 {
01609   WRITE_REG(TIMx->CNT, Counter);
01610 }
01611
01612 /**
01613   * @brief  Get the counter value.
01614   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01615   *       whether or not a timer instance supports a 32 bits counter.
01616   * @rmtoll CNT          CNT           LL_TIM_GetCounter
01617   * @param  TIMx Timer instance
01618   * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
01619   */
01620 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
01621 {
01622   return (uint32_t)(READ_REG(TIMx->CNT));
01623 }
01624
01625 /**
01626   * @brief  Get the current direction of the counter
01627   * @rmtoll CR1          DIR           LL_TIM_GetDirection
01628   * @param  TIMx Timer instance
01629   * @retval Returned value can be one of the following values:
01630   *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
01631   *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
01632   */
01633 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
01634 {
01635   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
01636 }
01637
01638 /**
01639   * @brief  Set the prescaler value.
01640   * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
01641   * @note The prescaler can be changed on the fly as this control register is buffered. The new
01642   *       prescaler ratio is taken into account at the next update event.
01643   * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
01644   * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
01645   * @param  TIMx Timer instance
01646   * @param  Prescaler between Min_Data=0 and Max_Data=65535
01647   * @retval None
01648   */
01649 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
01650 {
01651   WRITE_REG(TIMx->PSC, Prescaler);
01652 }
01653
01654 /**
01655   * @brief  Get the prescaler value.
01656   * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
01657   * @param  TIMx Timer instance
01658   * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
01659   */
01660 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
01661 {
01662   return (uint32_t)(READ_REG(TIMx->PSC));
01663 }
01664
01665 /**
01666   * @brief  Set the auto-reload value.
01667   * @note The counter is blocked while the auto-reload value is null.
01668   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01669   *       whether or not a timer instance supports a 32 bits counter.
01670   * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
01671   * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
01672   * @param  TIMx Timer instance
01673   * @param  AutoReload between Min_Data=0 and Max_Data=65535
01674   * @retval None
01675   */
01676 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
01677 {
01678   WRITE_REG(TIMx->ARR, AutoReload);
01679 }
01680
01681 /**
01682   * @brief  Get the auto-reload value.
01683   * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
01684   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01685   *       whether or not a timer instance supports a 32 bits counter.
01686   * @param  TIMx Timer instance
01687   * @retval Auto-reload value
01688   */
01689 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
01690 {
01691   return (uint32_t)(READ_REG(TIMx->ARR));
01692 }
01693
01694 /**
01695   * @brief  Set the repetition counter value.
01696   * @note For advanced timer instances RepetitionCounter can be up to 65535 except for STM32F373xC and STM32F378xx devices.
01697   * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
01698   *       whether or not a timer instance supports a repetition counter.
01699   * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
01700   * @param  TIMx Timer instance
01701   * @param  RepetitionCounter between Min_Data=0 and Max_Data=255
01702   * @retval None
01703   */
01704 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
01705 {
01706   WRITE_REG(TIMx->RCR, RepetitionCounter);
01707 }
01708
01709 /**
01710   * @brief  Get the repetition counter value.
01711   * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
01712   *       whether or not a timer instance supports a repetition counter.
01713   * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
01714   * @param  TIMx Timer instance
01715   * @retval Repetition counter value
01716   */
01717 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
01718 {
01719   return (uint32_t)(READ_REG(TIMx->RCR));
01720 }
01721
01722 #if defined(TIM_CR1_UIFREMAP)
01723 /**
01724   * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
01725   * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
01726   * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
01727   * @param  TIMx Timer instance
01728   * @retval None
01729   */
01730 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
01731 {
01732   SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
01733 }
01734
01735 /**
01736   * @brief  Disable update interrupt flag (UIF) remapping.
01737   * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
01738   * @param  TIMx Timer instance
01739   * @retval None
01740   */
01741 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
01742 {
01743   CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
01744 }
01745
01746 #endif /* TIM_CR1_UIFREMAP */
01747 /**
01748   * @}
01749   */
01750
01751 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
01752   * @{
01753   */
01754 /**
01755   * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
01756   * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
01757   *       they are updated only when a commutation event (COM) occurs.
01758   * @note Only on channels that have a complementary output.
01759   * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01760   *       whether or not a timer instance is able to generate a commutation event.
01761   * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
01762   * @param  TIMx Timer instance
01763   * @retval None
01764   */
01765 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
01766 {
01767   SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
01768 }
01769
01770 /**
01771   * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
01772   * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01773   *       whether or not a timer instance is able to generate a commutation event.
01774   * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
01775   * @param  TIMx Timer instance
01776   * @retval None
01777   */
01778 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
01779 {
01780   CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
01781 }
01782
01783 /**
01784   * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
01785   * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01786   *       whether or not a timer instance is able to generate a commutation event.
01787   * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
01788   * @param  TIMx Timer instance
01789   * @param  CCUpdateSource This parameter can be one of the following values:
01790   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
01791   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
01792   * @retval None
01793   */
01794 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
01795 {
01796   MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
01797 }
01798
01799 /**
01800   * @brief  Set the trigger of the capture/compare DMA request.
01801   * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
01802   * @param  TIMx Timer instance
01803   * @param  DMAReqTrigger This parameter can be one of the following values:
01804   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
01805   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
01806   * @retval None
01807   */
01808 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
01809 {
01810   MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
01811 }
01812
01813 /**
01814   * @brief  Get actual trigger of the capture/compare DMA request.
01815   * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
01816   * @param  TIMx Timer instance
01817   * @retval Returned value can be one of the following values:
01818   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
01819   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
01820   */
01821 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
01822 {
01823   return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
01824 }
01825
01826 /**
01827   * @brief  Set the lock level to freeze the
01828   *         configuration of several capture/compare parameters.
01829   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
01830   *       the lock mechanism is supported by a timer instance.
01831   * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
01832   * @param  TIMx Timer instance
01833   * @param  LockLevel This parameter can be one of the following values:
01834   *         @arg @ref LL_TIM_LOCKLEVEL_OFF
01835   *         @arg @ref LL_TIM_LOCKLEVEL_1
01836   *         @arg @ref LL_TIM_LOCKLEVEL_2
01837   *         @arg @ref LL_TIM_LOCKLEVEL_3
01838   * @retval None
01839   */
01840 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
01841 {
01842   MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
01843 }
01844
01845 /**
01846   * @brief  Enable capture/compare channels.
01847   * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
01848   *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
01849   *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
01850   *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
01851   *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
01852   *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
01853   *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
01854   *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
01855   *         CCER         CC6E          LL_TIM_CC_EnableChannel
01856   * @param  TIMx Timer instance
01857   * @param  Channels This parameter can be a combination of the following values:
01858   *         @arg @ref LL_TIM_CHANNEL_CH1
01859   *         @arg @ref LL_TIM_CHANNEL_CH1N
01860   *         @arg @ref LL_TIM_CHANNEL_CH2
01861   *         @arg @ref LL_TIM_CHANNEL_CH2N
01862   *         @arg @ref LL_TIM_CHANNEL_CH3
01863   *         @arg @ref LL_TIM_CHANNEL_CH3N
01864   *         @arg @ref LL_TIM_CHANNEL_CH4
01865   *         @arg @ref LL_TIM_CHANNEL_CH5
01866   *         @arg @ref LL_TIM_CHANNEL_CH6
01867   * @note   CH5 and CH6 channels are not available for all F3 devices
01868   * @retval None
01869   */
01870 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
01871 {
01872   SET_BIT(TIMx->CCER, Channels);
01873 }
01874
01875 /**
01876   * @brief  Disable capture/compare channels.
01877   * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
01878   *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
01879   *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
01880   *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
01881   *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
01882   *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
01883   *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
01884   *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
01885   *         CCER         CC6E          LL_TIM_CC_DisableChannel
01886   * @param  TIMx Timer instance
01887   * @param  Channels This parameter can be a combination of the following values:
01888   *         @arg @ref LL_TIM_CHANNEL_CH1
01889   *         @arg @ref LL_TIM_CHANNEL_CH1N
01890   *         @arg @ref LL_TIM_CHANNEL_CH2
01891   *         @arg @ref LL_TIM_CHANNEL_CH2N
01892   *         @arg @ref LL_TIM_CHANNEL_CH3
01893   *         @arg @ref LL_TIM_CHANNEL_CH3N
01894   *         @arg @ref LL_TIM_CHANNEL_CH4
01895   *         @arg @ref LL_TIM_CHANNEL_CH5
01896   *         @arg @ref LL_TIM_CHANNEL_CH6
01897   * @note   CH5 and CH6 channels are not available for all F3 devices
01898   * @retval None
01899   */
01900 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
01901 {
01902   CLEAR_BIT(TIMx->CCER, Channels);
01903 }
01904
01905 /**
01906   * @brief  Indicate whether channel(s) is(are) enabled.
01907   * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
01908   *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
01909   *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
01910   *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
01911   *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
01912   *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
01913   *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
01914   *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
01915   *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
01916   * @param  TIMx Timer instance
01917   * @param  Channels This parameter can be a combination of the following values:
01918   *         @arg @ref LL_TIM_CHANNEL_CH1
01919   *         @arg @ref LL_TIM_CHANNEL_CH1N
01920   *         @arg @ref LL_TIM_CHANNEL_CH2
01921   *         @arg @ref LL_TIM_CHANNEL_CH2N
01922   *         @arg @ref LL_TIM_CHANNEL_CH3
01923   *         @arg @ref LL_TIM_CHANNEL_CH3N
01924   *         @arg @ref LL_TIM_CHANNEL_CH4
01925   *         @arg @ref LL_TIM_CHANNEL_CH5
01926   *         @arg @ref LL_TIM_CHANNEL_CH6
01927   * @note   CH5 and CH6 channels are not available for all F3 devices
01928   * @retval State of bit (1 or 0).
01929   */
01930 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
01931 {
01932   return (READ_BIT(TIMx->CCER, Channels) == (Channels));
01933 }
01934
01935 /**
01936   * @}
01937   */
01938
01939 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
01940   * @{
01941   */
01942 /**
01943   * @brief  Configure an output channel.
01944   * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
01945   *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
01946   *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
01947   *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
01948   * @if STM32F334x8
01949   *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
01950   *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
01951   * @elseif STM32F303xC
01952   *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
01953   *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
01954   * @elseif STM32F302x8
01955   *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
01956   *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
01957   * @endif
01958   *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
01959   *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
01960   *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
01961   *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
01962   *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
01963   *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
01964   *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
01965   *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
01966   *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
01967   *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
01968   *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
01969   *         CR2          OIS6          LL_TIM_OC_ConfigOutput
01970   * @param  TIMx Timer instance
01971   * @param  Channel This parameter can be one of the following values:
01972   *         @arg @ref LL_TIM_CHANNEL_CH1
01973   *         @arg @ref LL_TIM_CHANNEL_CH2
01974   *         @arg @ref LL_TIM_CHANNEL_CH3
01975   *         @arg @ref LL_TIM_CHANNEL_CH4
01976   *         @arg @ref LL_TIM_CHANNEL_CH5
01977   *         @arg @ref LL_TIM_CHANNEL_CH6
01978   * @param  Configuration This parameter must be a combination of all the following values:
01979   *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
01980   *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
01981   * @note   CH3 CH4 CH5 and CH6 channels are not available for all F3 devices
01982   * @retval None
01983   */
01984 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
01985 {
01986   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01987   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
01988   CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
01989   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
01990              (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
01991   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
01992              (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
01993 }
01994
01995 /**
01996   * @brief  Define the behavior of the output reference signal OCxREF from which
01997   *         OCx and OCxN (when relevant) are derived.
01998   * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
01999   *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
02000   *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
02001   *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
02002   * @if STM32F334x8
02003   *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
02004   *         CCMR3        OC6M          LL_TIM_OC_SetMode
02005   * @elseif STM32F303xC
02006   *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
02007   *         CCMR3        OC6M          LL_TIM_OC_SetMode
02008   * @elseif STM32F302x8
02009   *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
02010   *         CCMR3        OC6M          LL_TIM_OC_SetMode
02011   * @endif
02012   * @param  TIMx Timer instance
02013   * @param  Channel This parameter can be one of the following values:
02014   *         @arg @ref LL_TIM_CHANNEL_CH1
02015   *         @arg @ref LL_TIM_CHANNEL_CH2
02016   *         @arg @ref LL_TIM_CHANNEL_CH3
02017   *         @arg @ref LL_TIM_CHANNEL_CH4
02018   *         @arg @ref LL_TIM_CHANNEL_CH5
02019   *         @arg @ref LL_TIM_CHANNEL_CH6
02020   * @param  Mode This parameter can be one of the following values:
02021   *         @arg @ref LL_TIM_OCMODE_FROZEN
02022   *         @arg @ref LL_TIM_OCMODE_ACTIVE
02023   *         @arg @ref LL_TIM_OCMODE_INACTIVE
02024   *         @arg @ref LL_TIM_OCMODE_TOGGLE
02025   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
02026   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
02027   *         @arg @ref LL_TIM_OCMODE_PWM1
02028   *         @arg @ref LL_TIM_OCMODE_PWM2
02029   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
02030   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
02031   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
02032   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
02033   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
02034   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
02035   * @note  The following OC modes are not available on all F3 devices :
02036   *        -  LL_TIM_OCMODE_RETRIG_OPM1
02037   *        -  LL_TIM_OCMODE_RETRIG_OPM2
02038   *        -  LL_TIM_OCMODE_COMBINED_PWM1
02039   *        -  LL_TIM_OCMODE_COMBINED_PWM2
02040   *        -  LL_TIM_OCMODE_ASSYMETRIC_PWM1
02041   *        -  LL_TIM_OCMODE_ASSYMETRIC_PWM2
02042   * @note  CH5 and CH6 channels are not available for all F3 devices
02043   * @retval None
02044   */
02045 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
02046 {
02047   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02048   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02049   MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]),  Mode << SHIFT_TAB_OCxx[iChannel]);
02050 }
02051
02052 /**
02053   * @brief  Get the output compare mode of an output channel.
02054   * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
02055   *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
02056   *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
02057   *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
02058   * @if STM32F334x8
02059   *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
02060   *         CCMR3        OC6M          LL_TIM_OC_GetMode
02061   * @elseif STM32F303xC
02062   *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
02063   *         CCMR3        OC6M          LL_TIM_OC_GetMode
02064   * @elseif STM32F302x8
02065   *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
02066   *         CCMR3        OC6M          LL_TIM_OC_GetMode
02067   * @endif
02068   * @param  TIMx Timer instance
02069   * @param  Channel This parameter can be one of the following values:
02070   *         @arg @ref LL_TIM_CHANNEL_CH1
02071   *         @arg @ref LL_TIM_CHANNEL_CH2
02072   *         @arg @ref LL_TIM_CHANNEL_CH3
02073   *         @arg @ref LL_TIM_CHANNEL_CH4
02074   *         @arg @ref LL_TIM_CHANNEL_CH5
02075   *         @arg @ref LL_TIM_CHANNEL_CH6
02076   * @note  The following OC modes are not available on all F3 devices :
02077   *        -  LL_TIM_OCMODE_RETRIG_OPM1
02078   *        -  LL_TIM_OCMODE_RETRIG_OPM2
02079   *        -  LL_TIM_OCMODE_COMBINED_PWM1
02080   *        -  LL_TIM_OCMODE_COMBINED_PWM2
02081   *        -  LL_TIM_OCMODE_ASSYMETRIC_PWM1
02082   *        -  LL_TIM_OCMODE_ASSYMETRIC_PWM2
02083   * @note  CH5 and CH6 channels are not available for all F3 devices
02084   * @retval Returned value can be one of the following values:
02085   *         @arg @ref LL_TIM_OCMODE_FROZEN
02086   *         @arg @ref LL_TIM_OCMODE_ACTIVE
02087   *         @arg @ref LL_TIM_OCMODE_INACTIVE
02088   *         @arg @ref LL_TIM_OCMODE_TOGGLE
02089   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
02090   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
02091   *         @arg @ref LL_TIM_OCMODE_PWM1
02092   *         @arg @ref LL_TIM_OCMODE_PWM2
02093   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
02094   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
02095   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
02096   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
02097   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
02098   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
02099   */
02100 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
02101 {
02102   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02103   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02104   return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
02105 }
02106
02107 /**
02108   * @brief  Set the polarity of an output channel.
02109   * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
02110   *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
02111   *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
02112   *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
02113   *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
02114   *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
02115   *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
02116   *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
02117   *         CCER         CC6P          LL_TIM_OC_SetPolarity
02118   * @param  TIMx Timer instance
02119   * @param  Channel This parameter can be one of the following values:
02120   *         @arg @ref LL_TIM_CHANNEL_CH1
02121   *         @arg @ref LL_TIM_CHANNEL_CH1N
02122   *         @arg @ref LL_TIM_CHANNEL_CH2
02123   *         @arg @ref LL_TIM_CHANNEL_CH2N
02124   *         @arg @ref LL_TIM_CHANNEL_CH3
02125   *         @arg @ref LL_TIM_CHANNEL_CH3N
02126   *         @arg @ref LL_TIM_CHANNEL_CH4
02127   *         @arg @ref LL_TIM_CHANNEL_CH5
02128   *         @arg @ref LL_TIM_CHANNEL_CH6
02129   * @param  Polarity This parameter can be one of the following values:
02130   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
02131   *         @arg @ref LL_TIM_OCPOLARITY_LOW
02132   * @note   CH5 and CH6 channels are not available for all F3 devices
02133   * @retval None
02134   */
02135 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
02136 {
02137   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02138   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
02139 }
02140
02141 /**
02142   * @brief  Get the polarity of an output channel.
02143   * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
02144   *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
02145   *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
02146   *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
02147   *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
02148   *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
02149   *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
02150   *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
02151   *         CCER         CC6P          LL_TIM_OC_GetPolarity
02152   * @param  TIMx Timer instance
02153   * @param  Channel This parameter can be one of the following values:
02154   *         @arg @ref LL_TIM_CHANNEL_CH1
02155   *         @arg @ref LL_TIM_CHANNEL_CH1N
02156   *         @arg @ref LL_TIM_CHANNEL_CH2
02157   *         @arg @ref LL_TIM_CHANNEL_CH2N
02158   *         @arg @ref LL_TIM_CHANNEL_CH3
02159   *         @arg @ref LL_TIM_CHANNEL_CH3N
02160   *         @arg @ref LL_TIM_CHANNEL_CH4
02161   *         @arg @ref LL_TIM_CHANNEL_CH5
02162   *         @arg @ref LL_TIM_CHANNEL_CH6
02163   * @note   CH5 and CH6 channels are not available for all F3 devices
02164   * @retval Returned value can be one of the following values:
02165   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
02166   *         @arg @ref LL_TIM_OCPOLARITY_LOW
02167   */
02168 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
02169 {
02170   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02171   return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
02172 }
02173
02174 /**
02175   * @brief  Set the IDLE state of an output channel
02176   * @note This function is significant only for the timer instances
02177   *       supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
02178   *       can be used to check whether or not a timer instance provides
02179   *       a break input.
02180   * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
02181   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
02182   *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
02183   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
02184   *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
02185   *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
02186   *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
02187   *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
02188   *         CR2         OIS6          LL_TIM_OC_SetIdleState
02189   * @param  TIMx Timer instance
02190   * @param  Channel This parameter can be one of the following values:
02191   *         @arg @ref LL_TIM_CHANNEL_CH1
02192   *         @arg @ref LL_TIM_CHANNEL_CH1N
02193   *         @arg @ref LL_TIM_CHANNEL_CH2
02194   *         @arg @ref LL_TIM_CHANNEL_CH2N
02195   *         @arg @ref LL_TIM_CHANNEL_CH3
02196   *         @arg @ref LL_TIM_CHANNEL_CH3N
02197   *         @arg @ref LL_TIM_CHANNEL_CH4
02198   *         @arg @ref LL_TIM_CHANNEL_CH5
02199   *         @arg @ref LL_TIM_CHANNEL_CH6
02200   * @param  IdleState This parameter can be one of the following values:
02201   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
02202   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
02203   * @note   CH5 and CH6 channels are not available for all F3 devices
02204   * @retval None
02205   */
02206 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
02207 {
02208   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02209   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
02210 }
02211
02212 /**
02213   * @brief  Get the IDLE state of an output channel
02214   * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
02215   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
02216   *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
02217   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
02218   *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
02219   *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
02220   *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
02221   *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
02222   *         CR2         OIS6          LL_TIM_OC_GetIdleState
02223   * @param  TIMx Timer instance
02224   * @param  Channel This parameter can be one of the following values:
02225   *         @arg @ref LL_TIM_CHANNEL_CH1
02226   *         @arg @ref LL_TIM_CHANNEL_CH1N
02227   *         @arg @ref LL_TIM_CHANNEL_CH2
02228   *         @arg @ref LL_TIM_CHANNEL_CH2N
02229   *         @arg @ref LL_TIM_CHANNEL_CH3
02230   *         @arg @ref LL_TIM_CHANNEL_CH3N
02231   *         @arg @ref LL_TIM_CHANNEL_CH4
02232   *         @arg @ref LL_TIM_CHANNEL_CH5
02233   *         @arg @ref LL_TIM_CHANNEL_CH6
02234   * @note   CH5 and CH6 channels are not available for all F3 devices
02235   * @retval Returned value can be one of the following values:
02236   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
02237   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
02238   */
02239 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
02240 {
02241   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02242   return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
02243 }
02244
02245 /**
02246   * @brief  Enable fast mode for the output channel.
02247   * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
02248   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
02249   *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
02250   *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
02251   *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
02252   * @if STM32F334x8
02253   *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
02254   *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
02255   * @elseif STM32F303xC
02256   *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
02257   *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
02258   * @elseif STM32F302x8
02259   *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
02260   *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
02261   * @endif
02262   * @param  TIMx Timer instance
02263   * @param  Channel This parameter can be one of the following values:
02264   *         @arg @ref LL_TIM_CHANNEL_CH1
02265   *         @arg @ref LL_TIM_CHANNEL_CH2
02266   *         @arg @ref LL_TIM_CHANNEL_CH3
02267   *         @arg @ref LL_TIM_CHANNEL_CH4
02268   *         @arg @ref LL_TIM_CHANNEL_CH5
02269   *         @arg @ref LL_TIM_CHANNEL_CH6
02270   * @note   OC5FE and OC6FE are not available for all F3 devices
02271   * @note   CH5 and CH6 channels are not available for all F3 devices
02272   * @retval None
02273   */
02274 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
02275 {
02276   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02277   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02278   SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
02279
02280 }
02281
02282 /**
02283   * @brief  Disable fast mode for the output channel.
02284   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
02285   *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
02286   *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
02287   *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
02288   * @if STM32F334x8
02289   *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
02290   *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
02291   * @elseif STM32F303xC
02292   *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
02293   *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
02294   * @elseif STM32F302x8
02295   *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
02296   *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
02297   * @endif
02298   * @param  TIMx Timer instance
02299   * @param  Channel This parameter can be one of the following values:
02300   *         @arg @ref LL_TIM_CHANNEL_CH1
02301   *         @arg @ref LL_TIM_CHANNEL_CH2
02302   *         @arg @ref LL_TIM_CHANNEL_CH3
02303   *         @arg @ref LL_TIM_CHANNEL_CH4
02304   *         @arg @ref LL_TIM_CHANNEL_CH5
02305   *         @arg @ref LL_TIM_CHANNEL_CH6
02306   * @note   OC5FE and OC6FE are not available for all F3 devices
02307   * @note   CH5 and CH6 channels are not available for all F3 devices
02308   * @retval None
02309   */
02310 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
02311 {
02312   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02313   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02314   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
02315
02316 }
02317
02318 /**
02319   * @brief  Indicates whether fast mode is enabled for the output channel.
02320   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
02321   *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
02322   *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
02323   *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
02324   * @if STM32F334x8
02325   *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
02326   *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
02327   * @elseif STM32F303xC
02328   *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
02329   *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
02330   * @elseif STM32F302x8
02331   *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
02332   *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
02333   * @endif
02334   * @param  TIMx Timer instance
02335   * @param  Channel This parameter can be one of the following values:
02336   *         @arg @ref LL_TIM_CHANNEL_CH1
02337   *         @arg @ref LL_TIM_CHANNEL_CH2
02338   *         @arg @ref LL_TIM_CHANNEL_CH3
02339   *         @arg @ref LL_TIM_CHANNEL_CH4
02340   *         @arg @ref LL_TIM_CHANNEL_CH5
02341   *         @arg @ref LL_TIM_CHANNEL_CH6
02342   * @note   OC5FE and OC6FE are not available for all F3 devices
02343   * @note   CH5 and CH6 channels are not available for all F3 devices
02344   * @retval State of bit (1 or 0).
02345   */
02346 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
02347 {
02348   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02349   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02350   register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
02351   return (READ_BIT(*pReg, bitfield) == bitfield);
02352 }
02353
02354 /**
02355   * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
02356   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
02357   *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
02358   *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
02359   *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
02360   * @if STM32F334x8
02361   *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
02362   *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
02363   * @elseif STM32F303xC
02364   *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
02365   *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
02366   * @elseif STM32F302x8
02367   *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
02368   *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
02369   * @endif
02370   * @param  TIMx Timer instance
02371   * @param  Channel This parameter can be one of the following values:
02372   *         @arg @ref LL_TIM_CHANNEL_CH1
02373   *         @arg @ref LL_TIM_CHANNEL_CH2
02374   *         @arg @ref LL_TIM_CHANNEL_CH3
02375   *         @arg @ref LL_TIM_CHANNEL_CH4
02376   *         @arg @ref LL_TIM_CHANNEL_CH5
02377   *         @arg @ref LL_TIM_CHANNEL_CH6
02378   * @note   OC5PE and OC6PE are not available for all F3 devices
02379   * @note   CH5 and CH6 channels are not available for all F3 devices
02380   * @retval None
02381   */
02382 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
02383 {
02384   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02385   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02386   SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
02387 }
02388
02389 /**
02390   * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
02391   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
02392   *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
02393   *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
02394   *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
02395   * @if STM32F334x8
02396   *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
02397   *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
02398   * @elseif STM32F303xC
02399   *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
02400   *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
02401   * @elseif STM32F302x8
02402   *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
02403   *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
02404   * @endif
02405   * @param  TIMx Timer instance
02406   * @param  Channel This parameter can be one of the following values:
02407   *         @arg @ref LL_TIM_CHANNEL_CH1
02408   *         @arg @ref LL_TIM_CHANNEL_CH2
02409   *         @arg @ref LL_TIM_CHANNEL_CH3
02410   *         @arg @ref LL_TIM_CHANNEL_CH4
02411   *         @arg @ref LL_TIM_CHANNEL_CH5
02412   *         @arg @ref LL_TIM_CHANNEL_CH6
02413   * @note   OC5PE and OC6PE are not available for all F3 devices
02414   * @note   CH5 and CH6 channels are not available for all F3 devices
02415   * @retval None
02416   */
02417 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
02418 {
02419   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02420   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02421   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
02422 }
02423
02424 /**
02425   * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
02426   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
02427   *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
02428   *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
02429   *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
02430   * @if   STM32F334x8
02431   *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
02432   *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
02433   * @elseif STM32F303xC
02434   *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
02435   *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
02436   * @elseif STM32F302x8
02437   *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
02438   *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
02439   * @endif
02440   * @param  TIMx Timer instance
02441   * @param  Channel This parameter can be one of the following values:
02442   *         @arg @ref LL_TIM_CHANNEL_CH1
02443   *         @arg @ref LL_TIM_CHANNEL_CH2
02444   *         @arg @ref LL_TIM_CHANNEL_CH3
02445   *         @arg @ref LL_TIM_CHANNEL_CH4
02446   *         @arg @ref LL_TIM_CHANNEL_CH5
02447   *         @arg @ref LL_TIM_CHANNEL_CH6
02448   * @note   OC5PE and OC6PE are not available for all F3 devices
02449   * @note   CH5 and CH6 channels are not available for all F3 devices
02450   * @retval State of bit (1 or 0).
02451   */
02452 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
02453 {
02454   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02455   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02456   register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
02457   return (READ_BIT(*pReg, bitfield) == bitfield);
02458 }
02459
02460 /**
02461   * @brief  Enable clearing the output channel on an external event.
02462   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
02463   * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02464   *       or not a timer instance can clear the OCxREF signal on an external event.
02465   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
02466   *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
02467   *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
02468   *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
02469   * @if STM32F334x8
02470   *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
02471   *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
02472   * @elseif STM32F303xC
02473   *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
02474   *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
02475   * @elseif STM32F302x8
02476   *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
02477   *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
02478   * @endif
02479   * @param  TIMx Timer instance
02480   * @param  Channel This parameter can be one of the following values:
02481   *         @arg @ref LL_TIM_CHANNEL_CH1
02482   *         @arg @ref LL_TIM_CHANNEL_CH2
02483   *         @arg @ref LL_TIM_CHANNEL_CH3
02484   *         @arg @ref LL_TIM_CHANNEL_CH4
02485   *         @arg @ref LL_TIM_CHANNEL_CH5
02486   *         @arg @ref LL_TIM_CHANNEL_CH6
02487   * @note   OC5CE and OC6CE are not available for all F3 devices
02488   * @note   CH5 and CH6 channels are not available for all F3 devices
02489   * @retval None
02490   */
02491 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
02492 {
02493   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02494   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02495   SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
02496 }
02497
02498 /**
02499   * @brief  Disable clearing the output channel on an external event.
02500   * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02501   *       or not a timer instance can clear the OCxREF signal on an external event.
02502   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
02503   *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
02504   *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
02505   *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
02506   * @if STM32F334x8
02507   *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
02508   *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
02509   * @elseif STM32F303xC
02510   *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
02511   *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
02512   * @elseif STM32F302x8
02513   *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
02514   *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
02515   * @endif
02516   * @param  TIMx Timer instance
02517   * @param  Channel This parameter can be one of the following values:
02518   *         @arg @ref LL_TIM_CHANNEL_CH1
02519   *         @arg @ref LL_TIM_CHANNEL_CH2
02520   *         @arg @ref LL_TIM_CHANNEL_CH3
02521   *         @arg @ref LL_TIM_CHANNEL_CH4
02522   *         @arg @ref LL_TIM_CHANNEL_CH5
02523   *         @arg @ref LL_TIM_CHANNEL_CH6
02524   * @note   OC5CE and OC6CE are not available for all F3 devices
02525   * @note   CH5 and CH6 channels are not available for all F3 devices
02526   * @retval None
02527   */
02528 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
02529 {
02530   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02531   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02532   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
02533 }
02534
02535 /**
02536   * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
02537   * @note This function enables clearing the output channel on an external event.
02538   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
02539   * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02540   *       or not a timer instance can clear the OCxREF signal on an external event.
02541   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
02542   *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
02543   *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
02544   *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
02545   * @if STM32F334x8
02546   *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
02547   *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
02548   * @elseif STM32F303xC
02549   *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
02550   *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
02551   * @elseif STM32F302x8
02552   *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
02553   *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
02554   * @endif
02555   * @param  TIMx Timer instance
02556   * @param  Channel This parameter can be one of the following values:
02557   *         @arg @ref LL_TIM_CHANNEL_CH1
02558   *         @arg @ref LL_TIM_CHANNEL_CH2
02559   *         @arg @ref LL_TIM_CHANNEL_CH3
02560   *         @arg @ref LL_TIM_CHANNEL_CH4
02561   *         @arg @ref LL_TIM_CHANNEL_CH5
02562   *         @arg @ref LL_TIM_CHANNEL_CH6
02563   * @note   OC5CE and OC6CE are not available for all F3 devices
02564   * @note   CH5 and CH6 channels are not available for all F3 devices
02565   * @retval State of bit (1 or 0).
02566   */
02567 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
02568 {
02569   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02570   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02571   register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
02572   return (READ_BIT(*pReg, bitfield) == bitfield);
02573 }
02574
02575 /**
02576   * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
02577   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02578   *       dead-time insertion feature is supported by a timer instance.
02579   * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
02580   * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
02581   * @param  TIMx Timer instance
02582   * @param  DeadTime between Min_Data=0 and Max_Data=255
02583   * @retval None
02584   */
02585 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
02586 {
02587   MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
02588 }
02589
02590 /**
02591   * @brief  Set compare value for output channel 1 (TIMx_CCR1).
02592   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02593   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02594   *       whether or not a timer instance supports a 32 bits counter.
02595   * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02596   *       output channel 1 is supported by a timer instance.
02597   * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
02598   * @param  TIMx Timer instance
02599   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02600   * @retval None
02601   */
02602 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
02603 {
02604   WRITE_REG(TIMx->CCR1, CompareValue);
02605 }
02606
02607 /**
02608   * @brief  Set compare value for output channel 2 (TIMx_CCR2).
02609   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02610   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02611   *       whether or not a timer instance supports a 32 bits counter.
02612   * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02613   *       output channel 2 is supported by a timer instance.
02614   * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
02615   * @param  TIMx Timer instance
02616   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02617   * @retval None
02618   */
02619 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
02620 {
02621   WRITE_REG(TIMx->CCR2, CompareValue);
02622 }
02623
02624 /**
02625   * @brief  Set compare value for output channel 3 (TIMx_CCR3).
02626   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02627   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02628   *       whether or not a timer instance supports a 32 bits counter.
02629   * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02630   *       output channel is supported by a timer instance.
02631   * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
02632   * @param  TIMx Timer instance
02633   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02634   * @retval None
02635   */
02636 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
02637 {
02638   WRITE_REG(TIMx->CCR3, CompareValue);
02639 }
02640
02641 /**
02642   * @brief  Set compare value for output channel 4 (TIMx_CCR4).
02643   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02644   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02645   *       whether or not a timer instance supports a 32 bits counter.
02646   * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02647   *       output channel 4 is supported by a timer instance.
02648   * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
02649   * @param  TIMx Timer instance
02650   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02651   * @retval None
02652   */
02653 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
02654 {
02655   WRITE_REG(TIMx->CCR4, CompareValue);
02656 }
02657
02658 #if defined(TIM_CCR5_CCR5)
02659 /**
02660   * @brief  Set compare value for output channel 5 (TIMx_CCR5).
02661   * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
02662   *       output channel 5 is supported by a timer instance.
02663   * @if STM32F334x8
02664   * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
02665   * @elseif STM32F303xC
02666   * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
02667   * @elseif STM32F302x8
02668   * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
02669   * @endif
02670   * @param  TIMx Timer instance
02671   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02672   * @note   CH5 channel is not available for all F3 devices
02673   * @retval None
02674   */
02675 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
02676 {
02677   WRITE_REG(TIMx->CCR5, CompareValue);
02678 }
02679
02680 #endif /* TIM_CCR5_CCR5 */
02681 #if defined(TIM_CCR6_CCR6)
02682 /**
02683   * @brief  Set compare value for output channel 6 (TIMx_CCR6).
02684   * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
02685   *       output channel 6 is supported by a timer instance.
02686   * @if STM32F344x8
02687   * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
02688   * @elseif STM32F303xC
02689   *         CCR6         CCR6          LL_TIM_OC_SetCompareCH6
02690   * @elseif STM32F302x8
02691   *         CCR6         CCR6          LL_TIM_OC_SetCompareCH6
02692   * @endif
02693   * @param  TIMx Timer instance
02694   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02695   * @note   CH6 channel is not available for all F3 devices
02696   * @retval None
02697   */
02698 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
02699 {
02700   WRITE_REG(TIMx->CCR6, CompareValue);
02701 }
02702
02703 #endif /* TIM_CCR6_CCR6 */
02704 /**
02705   * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
02706   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02707   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02708   *       whether or not a timer instance supports a 32 bits counter.
02709   * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02710   *       output channel 1 is supported by a timer instance.
02711   * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
02712   * @param  TIMx Timer instance
02713   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02714   */
02715 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
02716 {
02717   return (uint32_t)(READ_REG(TIMx->CCR1));
02718 }
02719
02720 /**
02721   * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
02722   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02723   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02724   *       whether or not a timer instance supports a 32 bits counter.
02725   * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02726   *       output channel 2 is supported by a timer instance.
02727   * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
02728   * @param  TIMx Timer instance
02729   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02730   */
02731 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
02732 {
02733   return (uint32_t)(READ_REG(TIMx->CCR2));
02734 }
02735
02736 /**
02737   * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
02738   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02739   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02740   *       whether or not a timer instance supports a 32 bits counter.
02741   * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02742   *       output channel 3 is supported by a timer instance.
02743   * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
02744   * @param  TIMx Timer instance
02745   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02746   */
02747 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
02748 {
02749   return (uint32_t)(READ_REG(TIMx->CCR3));
02750 }
02751
02752 /**
02753   * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
02754   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02755   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02756   *       whether or not a timer instance supports a 32 bits counter.
02757   * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02758   *       output channel 4 is supported by a timer instance.
02759   * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
02760   * @param  TIMx Timer instance
02761   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02762   */
02763 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
02764 {
02765   return (uint32_t)(READ_REG(TIMx->CCR4));
02766 }
02767
02768 #if defined(TIM_CCR5_CCR5)
02769 /**
02770   * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
02771   * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
02772   *       output channel 5 is supported by a timer instance.
02773   * @if STM32F334x8
02774   * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
02775   * @elseif STM32F303xC
02776   *         CCR5         CCR5          LL_TIM_OC_GetCompareCH5
02777   * @elseif STM32F302x8
02778   *         CCR5         CCR5          LL_TIM_OC_GetCompareCH5
02779   * @endif
02780   * @param  TIMx Timer instance
02781   * @note   CH5 channel is not available for all F3 devices
02782   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02783   */
02784 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
02785 {
02786   return (uint32_t)(READ_REG(TIMx->CCR5));
02787 }
02788
02789 #endif /* TIM_CCR5_CCR5 */
02790 #if defined(TIM_CCR6_CCR6)
02791 /**
02792   * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
02793   * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
02794   *       output channel 6 is supported by a timer instance.
02795   * @if STM32F334x8
02796   * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
02797   * @elseif STM32F303xC
02798   *         CCR6         CCR6          LL_TIM_OC_GetCompareCH6
02799   * @elseif STM32F302x8
02800   *         CCR6         CCR6          LL_TIM_OC_GetCompareCH6
02801   * @endif
02802   * @param  TIMx Timer instance
02803   * @note   CH6 channel is not available for all F3 devices
02804   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02805   */
02806 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
02807 {
02808   return (uint32_t)(READ_REG(TIMx->CCR6));
02809 }
02810
02811 #endif /* TIM_CCR6_CCR6 */
02812 #if defined(TIM_CCR5_CCR5)
02813 /**
02814   * @brief  Select on which reference signal the OC5REF is combined to.
02815   * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
02816   *       whether or not a timer instance supports the combined 3-phase PWM mode.
02817   * @if STM32F334x8
02818   * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
02819   *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
02820   *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
02821   * @elseif STM32F303xC
02822   *         CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
02823   *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
02824   *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
02825   * @elseif STM32F302x8
02826   *         CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
02827   *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
02828   *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
02829   * @endif
02830   * @param  TIMx Timer instance
02831   * @param  GroupCH5 This parameter can be one of the following values:
02832   *         @arg @ref LL_TIM_GROUPCH5_NONE
02833   *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
02834   *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
02835   *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
02836   * @note   CH5 channel is not available for all F3 devices
02837   * @retval None
02838   */
02839 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
02840 {
02841   MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
02842 }
02843
02844 #endif /* TIM_CCR5_CCR5 */
02845 /**
02846   * @}
02847   */
02848
02849 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
02850   * @{
02851   */
02852 /**
02853   * @brief  Configure input channel.
02854   * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
02855   *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
02856   *         CCMR1        IC1F          LL_TIM_IC_Config\n
02857   *         CCMR1        CC2S          LL_TIM_IC_Config\n
02858   *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
02859   *         CCMR1        IC2F          LL_TIM_IC_Config\n
02860   *         CCMR2        CC3S          LL_TIM_IC_Config\n
02861   *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
02862   *         CCMR2        IC3F          LL_TIM_IC_Config\n
02863   *         CCMR2        CC4S          LL_TIM_IC_Config\n
02864   *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
02865   *         CCMR2        IC4F          LL_TIM_IC_Config\n
02866   *         CCER         CC1P          LL_TIM_IC_Config\n
02867   *         CCER         CC1NP         LL_TIM_IC_Config\n
02868   *         CCER         CC2P          LL_TIM_IC_Config\n
02869   *         CCER         CC2NP         LL_TIM_IC_Config\n
02870   *         CCER         CC3P          LL_TIM_IC_Config\n
02871   *         CCER         CC3NP         LL_TIM_IC_Config\n
02872   *         CCER         CC4P          LL_TIM_IC_Config\n
02873   *         CCER         CC4NP         LL_TIM_IC_Config
02874   * @param  TIMx Timer instance
02875   * @param  Channel This parameter can be one of the following values:
02876   *         @arg @ref LL_TIM_CHANNEL_CH1
02877   *         @arg @ref LL_TIM_CHANNEL_CH2
02878   *         @arg @ref LL_TIM_CHANNEL_CH3
02879   *         @arg @ref LL_TIM_CHANNEL_CH4
02880   * @param  Configuration This parameter must be a combination of all the following values:
02881   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
02882   *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
02883   *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
02884   *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
02885   * @retval None
02886   */
02887 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
02888 {
02889   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02890   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02891   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
02892              ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))  << SHIFT_TAB_ICxx[iChannel]);
02893   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
02894              (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
02895 }
02896
02897 /**
02898   * @brief  Set the active input.
02899   * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
02900   *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
02901   *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
02902   *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
02903   * @param  TIMx Timer instance
02904   * @param  Channel This parameter can be one of the following values:
02905   *         @arg @ref LL_TIM_CHANNEL_CH1
02906   *         @arg @ref LL_TIM_CHANNEL_CH2
02907   *         @arg @ref LL_TIM_CHANNEL_CH3
02908   *         @arg @ref LL_TIM_CHANNEL_CH4
02909   * @param  ICActiveInput This parameter can be one of the following values:
02910   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
02911   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
02912   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
02913   * @retval None
02914   */
02915 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
02916 {
02917   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02918   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02919   MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02920 }
02921
02922 /**
02923   * @brief  Get the current active input.
02924   * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
02925   *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
02926   *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
02927   *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
02928   * @param  TIMx Timer instance
02929   * @param  Channel This parameter can be one of the following values:
02930   *         @arg @ref LL_TIM_CHANNEL_CH1
02931   *         @arg @ref LL_TIM_CHANNEL_CH2
02932   *         @arg @ref LL_TIM_CHANNEL_CH3
02933   *         @arg @ref LL_TIM_CHANNEL_CH4
02934   * @retval Returned value can be one of the following values:
02935   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
02936   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
02937   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
02938   */
02939 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
02940 {
02941   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02942   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02943   return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
02944 }
02945
02946 /**
02947   * @brief  Set the prescaler of input channel.
02948   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
02949   *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
02950   *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
02951   *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
02952   * @param  TIMx Timer instance
02953   * @param  Channel This parameter can be one of the following values:
02954   *         @arg @ref LL_TIM_CHANNEL_CH1
02955   *         @arg @ref LL_TIM_CHANNEL_CH2
02956   *         @arg @ref LL_TIM_CHANNEL_CH3
02957   *         @arg @ref LL_TIM_CHANNEL_CH4
02958   * @param  ICPrescaler This parameter can be one of the following values:
02959   *         @arg @ref LL_TIM_ICPSC_DIV1
02960   *         @arg @ref LL_TIM_ICPSC_DIV2
02961   *         @arg @ref LL_TIM_ICPSC_DIV4
02962   *         @arg @ref LL_TIM_ICPSC_DIV8
02963   * @retval None
02964   */
02965 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
02966 {
02967   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02968   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02969   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02970 }
02971
02972 /**
02973   * @brief  Get the current prescaler value acting on an  input channel.
02974   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
02975   *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
02976   *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
02977   *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
02978   * @param  TIMx Timer instance
02979   * @param  Channel This parameter can be one of the following values:
02980   *         @arg @ref LL_TIM_CHANNEL_CH1
02981   *         @arg @ref LL_TIM_CHANNEL_CH2
02982   *         @arg @ref LL_TIM_CHANNEL_CH3
02983   *         @arg @ref LL_TIM_CHANNEL_CH4
02984   * @retval Returned value can be one of the following values:
02985   *         @arg @ref LL_TIM_ICPSC_DIV1
02986   *         @arg @ref LL_TIM_ICPSC_DIV2
02987   *         @arg @ref LL_TIM_ICPSC_DIV4
02988   *         @arg @ref LL_TIM_ICPSC_DIV8
02989   */
02990 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
02991 {
02992   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02993   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02994   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
02995 }
02996
02997 /**
02998   * @brief  Set the input filter duration.
02999   * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
03000   *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
03001   *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
03002   *         CCMR2        IC4F          LL_TIM_IC_SetFilter
03003   * @param  TIMx Timer instance
03004   * @param  Channel This parameter can be one of the following values:
03005   *         @arg @ref LL_TIM_CHANNEL_CH1
03006   *         @arg @ref LL_TIM_CHANNEL_CH2
03007   *         @arg @ref LL_TIM_CHANNEL_CH3
03008   *         @arg @ref LL_TIM_CHANNEL_CH4
03009   * @param  ICFilter This parameter can be one of the following values:
03010   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
03011   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
03012   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
03013   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
03014   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
03015   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
03016   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
03017   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
03018   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
03019   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
03020   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
03021   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
03022   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
03023   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
03024   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
03025   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
03026   * @retval None
03027   */
03028 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
03029 {
03030   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03031   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03032   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
03033 }
03034
03035 /**
03036   * @brief  Get the input filter duration.
03037   * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
03038   *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
03039   *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
03040   *         CCMR2        IC4F          LL_TIM_IC_GetFilter
03041   * @param  TIMx Timer instance
03042   * @param  Channel This parameter can be one of the following values:
03043   *         @arg @ref LL_TIM_CHANNEL_CH1
03044   *         @arg @ref LL_TIM_CHANNEL_CH2
03045   *         @arg @ref LL_TIM_CHANNEL_CH3
03046   *         @arg @ref LL_TIM_CHANNEL_CH4
03047   * @retval Returned value can be one of the following values:
03048   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
03049   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
03050   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
03051   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
03052   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
03053   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
03054   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
03055   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
03056   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
03057   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
03058   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
03059   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
03060   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
03061   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
03062   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
03063   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
03064   */
03065 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
03066 {
03067   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03068   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03069   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
03070 }
03071
03072 /**
03073   * @brief  Set the input channel polarity.
03074   * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
03075   *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
03076   *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
03077   *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
03078   *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
03079   *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
03080   *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
03081   *         CCER         CC4NP         LL_TIM_IC_SetPolarity
03082   * @param  TIMx Timer instance
03083   * @param  Channel This parameter can be one of the following values:
03084   *         @arg @ref LL_TIM_CHANNEL_CH1
03085   *         @arg @ref LL_TIM_CHANNEL_CH2
03086   *         @arg @ref LL_TIM_CHANNEL_CH3
03087   *         @arg @ref LL_TIM_CHANNEL_CH4
03088   * @param  ICPolarity This parameter can be one of the following values:
03089   *         @arg @ref LL_TIM_IC_POLARITY_RISING
03090   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
03091   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
03092   * @retval None
03093   */
03094 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
03095 {
03096   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03097   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
03098              ICPolarity << SHIFT_TAB_CCxP[iChannel]);
03099 }
03100
03101 /**
03102   * @brief  Get the current input channel polarity.
03103   * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
03104   *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
03105   *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
03106   *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
03107   *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
03108   *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
03109   *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
03110   *         CCER         CC4NP         LL_TIM_IC_GetPolarity
03111   * @param  TIMx Timer instance
03112   * @param  Channel This parameter can be one of the following values:
03113   *         @arg @ref LL_TIM_CHANNEL_CH1
03114   *         @arg @ref LL_TIM_CHANNEL_CH2
03115   *         @arg @ref LL_TIM_CHANNEL_CH3
03116   *         @arg @ref LL_TIM_CHANNEL_CH4
03117   * @retval Returned value can be one of the following values:
03118   *         @arg @ref LL_TIM_IC_POLARITY_RISING
03119   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
03120   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
03121   */
03122 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
03123 {
03124   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03125   return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
03126           SHIFT_TAB_CCxP[iChannel]);
03127 }
03128
03129 /**
03130   * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
03131   * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
03132   *       a timer instance provides an XOR input.
03133   * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
03134   * @param  TIMx Timer instance
03135   * @retval None
03136   */
03137 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
03138 {
03139   SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
03140 }
03141
03142 /**
03143   * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
03144   * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
03145   *       a timer instance provides an XOR input.
03146   * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
03147   * @param  TIMx Timer instance
03148   * @retval None
03149   */
03150 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
03151 {
03152   CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
03153 }
03154
03155 /**
03156   * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
03157   * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
03158   * a timer instance provides an XOR input.
03159   * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
03160   * @param  TIMx Timer instance
03161   * @retval State of bit (1 or 0).
03162   */
03163 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
03164 {
03165   return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
03166 }
03167
03168 /**
03169   * @brief  Get captured value for input channel 1.
03170   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
03171   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03172   *       whether or not a timer instance supports a 32 bits counter.
03173   * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
03174   *       input channel 1 is supported by a timer instance.
03175   * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
03176   * @param  TIMx Timer instance
03177   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03178   */
03179 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
03180 {
03181   return (uint32_t)(READ_REG(TIMx->CCR1));
03182 }
03183
03184 /**
03185   * @brief  Get captured value for input channel 2.
03186   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
03187   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03188   *       whether or not a timer instance supports a 32 bits counter.
03189   * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
03190   *       input channel 2 is supported by a timer instance.
03191   * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
03192   * @param  TIMx Timer instance
03193   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03194   */
03195 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
03196 {
03197   return (uint32_t)(READ_REG(TIMx->CCR2));
03198 }
03199
03200 /**
03201   * @brief  Get captured value for input channel 3.
03202   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
03203   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03204   *       whether or not a timer instance supports a 32 bits counter.
03205   * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
03206   *       input channel 3 is supported by a timer instance.
03207   * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
03208   * @param  TIMx Timer instance
03209   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03210   */
03211 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
03212 {
03213   return (uint32_t)(READ_REG(TIMx->CCR3));
03214 }
03215
03216 /**
03217   * @brief  Get captured value for input channel 4.
03218   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
03219   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03220   *       whether or not a timer instance supports a 32 bits counter.
03221   * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
03222   *       input channel 4 is supported by a timer instance.
03223   * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
03224   * @param  TIMx Timer instance
03225   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03226   */
03227 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
03228 {
03229   return (uint32_t)(READ_REG(TIMx->CCR4));
03230 }
03231
03232 /**
03233   * @}
03234   */
03235
03236 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
03237   * @{
03238   */
03239 /**
03240   * @brief  Enable external clock mode 2.
03241   * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
03242   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03243   *       whether or not a timer instance supports external clock mode2.
03244   * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
03245   * @param  TIMx Timer instance
03246   * @retval None
03247   */
03248 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
03249 {
03250   SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
03251 }
03252
03253 /**
03254   * @brief  Disable external clock mode 2.
03255   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03256   *       whether or not a timer instance supports external clock mode2.
03257   * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
03258   * @param  TIMx Timer instance
03259   * @retval None
03260   */
03261 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
03262 {
03263   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
03264 }
03265
03266 /**
03267   * @brief  Indicate whether external clock mode 2 is enabled.
03268   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03269   *       whether or not a timer instance supports external clock mode2.
03270   * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
03271   * @param  TIMx Timer instance
03272   * @retval State of bit (1 or 0).
03273   */
03274 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
03275 {
03276   return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
03277 }
03278
03279 /**
03280   * @brief  Set the clock source of the counter clock.
03281   * @note when selected clock source is external clock mode 1, the timer input
03282   *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
03283   *       function. This timer input must be configured by calling
03284   *       the @ref LL_TIM_IC_Config() function.
03285   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
03286   *       whether or not a timer instance supports external clock mode1.
03287   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03288   *       whether or not a timer instance supports external clock mode2.
03289   * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
03290   *         SMCR         ECE           LL_TIM_SetClockSource
03291   * @param  TIMx Timer instance
03292   * @param  ClockSource This parameter can be one of the following values:
03293   *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
03294   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
03295   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
03296   * @retval None
03297   */
03298 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
03299 {
03300   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
03301 }
03302
03303 /**
03304   * @brief  Set the encoder interface mode.
03305   * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
03306   *       whether or not a timer instance supports the encoder mode.
03307   * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
03308   * @param  TIMx Timer instance
03309   * @param  EncoderMode This parameter can be one of the following values:
03310   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
03311   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
03312   *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
03313   * @retval None
03314   */
03315 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
03316 {
03317   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
03318 }
03319
03320 /**
03321   * @}
03322   */
03323
03324 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
03325   * @{
03326   */
03327 /**
03328   * @brief  Set the trigger output (TRGO) used for timer synchronization .
03329   * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
03330   *       whether or not a timer instance can operate as a master timer.
03331   * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
03332   * @param  TIMx Timer instance
03333   * @param  TimerSynchronization This parameter can be one of the following values:
03334   *         @arg @ref LL_TIM_TRGO_RESET
03335   *         @arg @ref LL_TIM_TRGO_ENABLE
03336   *         @arg @ref LL_TIM_TRGO_UPDATE
03337   *         @arg @ref LL_TIM_TRGO_CC1IF
03338   *         @arg @ref LL_TIM_TRGO_OC1REF
03339   *         @arg @ref LL_TIM_TRGO_OC2REF
03340   *         @arg @ref LL_TIM_TRGO_OC3REF
03341   *         @arg @ref LL_TIM_TRGO_OC4REF
03342   * @retval None
03343   */
03344 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
03345 {
03346   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
03347 }
03348
03349 #if   defined(TIM_CR2_MMS2)
03350 /**
03351   * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
03352   * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
03353   *       whether or not a timer instance can be used for ADC synchronization.
03354   * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
03355   * @param  TIMx Timer Instance
03356   * @param  ADCSynchronization This parameter can be one of the following values:
03357   *         @arg @ref LL_TIM_TRGO2_RESET
03358   *         @arg @ref LL_TIM_TRGO2_ENABLE
03359   *         @arg @ref LL_TIM_TRGO2_UPDATE
03360   *         @arg @ref LL_TIM_TRGO2_CC1F
03361   *         @arg @ref LL_TIM_TRGO2_OC1
03362   *         @arg @ref LL_TIM_TRGO2_OC2
03363   *         @arg @ref LL_TIM_TRGO2_OC3
03364   *         @arg @ref LL_TIM_TRGO2_OC4
03365   *         @arg @ref LL_TIM_TRGO2_OC5
03366   *         @arg @ref LL_TIM_TRGO2_OC6
03367   *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
03368   *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
03369   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
03370   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
03371   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
03372   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
03373   * @note   OC5 and OC6 are not available for all F3 devices
03374   * @retval None
03375   */
03376 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
03377 {
03378   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
03379 }
03380
03381 #endif /* TIM_CR2_MMS2 */
03382 /**
03383   * @brief  Set the synchronization mode of a slave timer.
03384   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03385   *       a timer instance can operate as a slave timer.
03386   * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
03387   * @param  TIMx Timer instance
03388   * @param  SlaveMode This parameter can be one of the following values:
03389   *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
03390   *         @arg @ref LL_TIM_SLAVEMODE_RESET
03391   *         @arg @ref LL_TIM_SLAVEMODE_GATED
03392   *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
03393   *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
03394   * @retval None
03395   */
03396 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
03397 {
03398   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
03399 }
03400
03401 /**
03402   * @brief  Set the selects the trigger input to be used to synchronize the counter.
03403   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03404   *       a timer instance can operate as a slave timer.
03405   * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
03406   * @param  TIMx Timer instance
03407   * @param  TriggerInput This parameter can be one of the following values:
03408   *         @arg @ref LL_TIM_TS_ITR0
03409   *         @arg @ref LL_TIM_TS_ITR1
03410   *         @arg @ref LL_TIM_TS_ITR2
03411   *         @arg @ref LL_TIM_TS_ITR3
03412   *         @arg @ref LL_TIM_TS_TI1F_ED
03413   *         @arg @ref LL_TIM_TS_TI1FP1
03414   *         @arg @ref LL_TIM_TS_TI2FP2
03415   *         @arg @ref LL_TIM_TS_ETRF
03416   * @retval None
03417   */
03418 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
03419 {
03420   MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
03421 }
03422
03423 /**
03424   * @brief  Enable the Master/Slave mode.
03425   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03426   *       a timer instance can operate as a slave timer.
03427   * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
03428   * @param  TIMx Timer instance
03429   * @retval None
03430   */
03431 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
03432 {
03433   SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
03434 }
03435
03436 /**
03437   * @brief  Disable the Master/Slave mode.
03438   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03439   *       a timer instance can operate as a slave timer.
03440   * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
03441   * @param  TIMx Timer instance
03442   * @retval None
03443   */
03444 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
03445 {
03446   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
03447 }
03448
03449 /**
03450   * @brief Indicates whether the Master/Slave mode is enabled.
03451   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03452   * a timer instance can operate as a slave timer.
03453   * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
03454   * @param  TIMx Timer instance
03455   * @retval State of bit (1 or 0).
03456   */
03457 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
03458 {
03459   return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
03460 }
03461
03462 /**
03463   * @brief  Configure the external trigger (ETR) input.
03464   * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
03465   *       a timer instance provides an external trigger input.
03466   * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
03467   *         SMCR         ETPS          LL_TIM_ConfigETR\n
03468   *         SMCR         ETF           LL_TIM_ConfigETR
03469   * @param  TIMx Timer instance
03470   * @param  ETRPolarity This parameter can be one of the following values:
03471   *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
03472   *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
03473   * @param  ETRPrescaler This parameter can be one of the following values:
03474   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
03475   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
03476   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
03477   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
03478   * @param  ETRFilter This parameter can be one of the following values:
03479   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
03480   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
03481   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
03482   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
03483   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
03484   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
03485   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
03486   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
03487   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
03488   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
03489   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
03490   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
03491   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
03492   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
03493   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
03494   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
03495   * @retval None
03496   */
03497 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
03498                                       uint32_t ETRFilter)
03499 {
03500   MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
03501 }
03502
03503 /**
03504   * @}
03505   */
03506
03507 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
03508   * @{
03509   */
03510 /**
03511   * @brief  Enable the break function.
03512   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03513   *       a timer instance provides a break input.
03514   * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
03515   * @param  TIMx Timer instance
03516   * @retval None
03517   */
03518 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
03519 {
03520   __IO uint32_t tmpreg;
03521
03522   SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
03523
03524   /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
03525   tmpreg = READ_REG(TIMx->BDTR);
03526   (void)(tmpreg);
03527 }
03528
03529 /**
03530   * @brief  Disable the break function.
03531   * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
03532   * @param  TIMx Timer instance
03533   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03534   *       a timer instance provides a break input.
03535   * @retval None
03536   */
03537 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
03538 {
03539   __IO uint32_t tmpreg;
03540
03541   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
03542
03543   /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
03544   tmpreg = READ_REG(TIMx->BDTR);
03545   (void)(tmpreg);
03546 }
03547
03548 #if defined(TIM_BDTR_BKF)
03549 /**
03550   * @brief  Configure the break input.
03551   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03552   *       a timer instance provides a break input.
03553   * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
03554   *         BDTR         BKF           LL_TIM_ConfigBRK
03555   * @param  TIMx Timer instance
03556   * @param  BreakPolarity This parameter can be one of the following values:
03557   *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
03558   *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
03559   * @param  BreakFilter This parameter can be one of the following values:
03560   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
03561   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
03562   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
03563   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
03564   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
03565   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
03566   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
03567   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
03568   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
03569   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
03570   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
03571   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
03572   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
03573   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
03574   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
03575   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
03576   * @retval None
03577   */
03578 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
03579 {
03580   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
03581 }
03582
03583 #else
03584 /**
03585   * @brief  Configure the break input.
03586   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03587   *       a timer instance provides a break input.
03588   * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK
03589   * @param  TIMx Timer instance
03590   * @param  BreakPolarity This parameter can be one of the following values:
03591   *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
03592   *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
03593   * @retval None
03594   */
03595 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
03596 {
03597   __IO uint32_t tmpreg;
03598
03599   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
03600
03601   /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
03602   tmpreg = READ_REG(TIMx->BDTR);
03603   (void)(tmpreg);
03604 }
03605
03606 #endif /* TIM_BDTR_BKF */
03607 #if defined(TIM_BDTR_BK2E)
03608 /**
03609   * @brief  Enable the break 2 function.
03610   * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03611   *       a timer instance provides a second break input.
03612   * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
03613   * @param  TIMx Timer instance
03614   * @retval None
03615   */
03616 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
03617 {
03618   SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
03619 }
03620
03621 /**
03622   * @brief  Disable the break  2 function.
03623   * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03624   *       a timer instance provides a second break input.
03625   * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
03626   * @param  TIMx Timer instance
03627   * @retval None
03628   */
03629 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
03630 {
03631   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
03632 }
03633
03634 /**
03635   * @brief  Configure the break 2 input.
03636   * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03637   *       a timer instance provides a second break input.
03638   * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
03639   *         BDTR         BK2F          LL_TIM_ConfigBRK2
03640   * @param  TIMx Timer instance
03641   * @param  Break2Polarity This parameter can be one of the following values:
03642   *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
03643   *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
03644   * @param  Break2Filter This parameter can be one of the following values:
03645   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
03646   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
03647   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
03648   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
03649   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
03650   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
03651   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
03652   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
03653   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
03654   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
03655   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
03656   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
03657   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
03658   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
03659   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
03660   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
03661   * @retval None
03662   */
03663 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
03664 {
03665   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
03666 }
03667
03668 #endif /* TIM_BDTR_BK2E */
03669 /**
03670   * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
03671   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03672   *       a timer instance provides a break input.
03673   * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
03674   *         BDTR         OSSR          LL_TIM_SetOffStates
03675   * @param  TIMx Timer instance
03676   * @param  OffStateIdle This parameter can be one of the following values:
03677   *         @arg @ref LL_TIM_OSSI_DISABLE
03678   *         @arg @ref LL_TIM_OSSI_ENABLE
03679   * @param  OffStateRun This parameter can be one of the following values:
03680   *         @arg @ref LL_TIM_OSSR_DISABLE
03681   *         @arg @ref LL_TIM_OSSR_ENABLE
03682   * @retval None
03683   */
03684 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
03685 {
03686   MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
03687 }
03688
03689 /**
03690   * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
03691   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03692   *       a timer instance provides a break input.
03693   * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
03694   * @param  TIMx Timer instance
03695   * @retval None
03696   */
03697 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
03698 {
03699   SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
03700 }
03701
03702 /**
03703   * @brief  Disable automatic output (MOE can be set only by software).
03704   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03705   *       a timer instance provides a break input.
03706   * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
03707   * @param  TIMx Timer instance
03708   * @retval None
03709   */
03710 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
03711 {
03712   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
03713 }
03714
03715 /**
03716   * @brief  Indicate whether automatic output is enabled.
03717   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03718   *       a timer instance provides a break input.
03719   * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
03720   * @param  TIMx Timer instance
03721   * @retval State of bit (1 or 0).
03722   */
03723 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
03724 {
03725   return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
03726 }
03727
03728 /**
03729   * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
03730   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
03731   *       software and is reset in case of break or break2 event
03732   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03733   *       a timer instance provides a break input.
03734   * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
03735   * @param  TIMx Timer instance
03736   * @retval None
03737   */
03738 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
03739 {
03740   SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
03741 }
03742
03743 /**
03744   * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
03745   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
03746   *       software and is reset in case of break or break2 event.
03747   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03748   *       a timer instance provides a break input.
03749   * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
03750   * @param  TIMx Timer instance
03751   * @retval None
03752   */
03753 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
03754 {
03755   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
03756 }
03757
03758 /**
03759   * @brief  Indicates whether outputs are enabled.
03760   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03761   *       a timer instance provides a break input.
03762   * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
03763   * @param  TIMx Timer instance
03764   * @retval State of bit (1 or 0).
03765   */
03766 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
03767 {
03768   return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
03769 }
03770
03771 /**
03772   * @}
03773   */
03774
03775 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
03776   * @{
03777   */
03778 /**
03779   * @brief  Configures the timer DMA burst feature.
03780   * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
03781   *       not a timer instance supports the DMA burst mode.
03782   * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
03783   *         DCR          DBA           LL_TIM_ConfigDMABurst
03784   * @param  TIMx Timer instance
03785   * @param  DMABurstBaseAddress This parameter can be one of the following values:
03786   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
03787   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
03788   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
03789   *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
03790   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
03791   *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
03792   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
03793   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
03794   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
03795   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
03796   *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
03797   *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
03798   *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
03799   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
03800   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
03801   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
03802   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
03803   *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
03804   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 (*)
03805   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5  (*)
03806   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6  (*)
03807   *         (*) value not defined in all devices
03808   *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR
03809   * @param  DMABurstLength This parameter can be one of the following values:
03810   *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
03811   *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
03812   *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
03813   *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
03814   *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
03815   *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
03816   *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
03817   *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
03818   *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
03819   *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
03820   *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
03821   *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
03822   *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
03823   *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
03824   *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
03825   *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
03826   *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
03827   *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
03828   * @retval None
03829   */
03830 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
03831 {
03832   MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
03833 }
03834
03835 /**
03836   * @}
03837   */
03838
03839 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
03840   * @{
03841   */
03842 /**
03843   * @brief  Remap TIM inputs (input channel, internal/external triggers).
03844   * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
03845   *       a some timer inputs can be remapped.
03846   * @if STM32F334x8
03847   * @rmtoll TIM1_OR     ETR_RMP      LL_TIM_SetRemap\n
03848   *         TIM16_OR    TI1_RMP      LL_TIM_SetRemap\n
03849   * @elseif STM32F302x8
03850   * @rmtoll TIM1_OR     ETR_RMP      LL_TIM_SetRemap\n
03851   *         TIM16_OR    TI1_RMP      LL_TIM_SetRemap\n
03852   * @elseif STM32F303xC
03853   * @rmtoll TIM1_OR     ETR_RMP      LL_TIM_SetRemap\n
03854   *         TIM8_OR     ETR_RMP      LL_TIM_SetRemap\n
03855   *         TIM20_OR    ETR_RMP      LL_TIM_SetRemap\n
03856   * @elseif STM32F373xC
03857   * @rmtoll  TIM14_OR    TI1_RMP      LL_TIM_SetRemap
03858   * @endif
03859   * @param  TIMx Timer instance
03860   * @param  Remap Remap params depends on the TIMx. Description available only
03861   *         in CHM version of the User Manual (not in .pdf).
03862   *         Otherwise see Reference Manual description of OR registers.
03863   *
03864   *         Below description summarizes "Timer Instance" and "Remap" param combinations:
03865   *
03866   *         TIM1: any combination of ETR_RMP where      (**)
03867   *
03868   *            . . ETR_RMP can be one of the following values
03869   *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
03870   *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1   (*)
03871   *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2   (*)
03872   *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3   (*)
03873   *            @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_NC     (*)
03874   *            @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD1   (*)
03875   *            @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD2   (*)
03876   *            @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD3   (*)
03877   *            @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC     (*)
03878   *            @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1   (*)
03879   *            @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2   (*)
03880   *            @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3   (*)
03881   *
03882   *         TIM8: any combination of ETR_RMP where       (**)
03883   *
03884   *            . . ETR_RMP can be one of the following values
03885   *            @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC      (*)
03886   *            @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1    (*)
03887   *            @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2    (*)
03888   *            @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3    (*)
03889   *            @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC      (*)
03890   *            @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1    (*)
03891   *            @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2    (*)
03892   *            @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3    (*)
03893   *
03894   *         TIM14: any combination of TI1_RMP where       (**)
03895   *
03896   *            . . TI1_RMP can be one of the following values
03897   *            @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO       (*)
03898   *            @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK    (*)
03899   *            @arg @ref LL_TIM_TIM14_TI1_RMP_HSE        (*)
03900   *            @arg @ref LL_TIM_TIM14_TI1_RMP_MCO        (*)
03901   *
03902   *         TIM16: any combination of TI1_RMP where       (**)
03903   *
03904   *            . . TI1_RMP can be one of the following values
03905   *            @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO       (*)
03906   *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSI        (*)
03907   *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSE        (*)
03908   *            @arg @ref LL_TIM_TIM16_TI1_RMP_RTC        (*)
03909   *
03910   *         TIM20: any combination of ETR_RMP where       (**)
03911   *
03912   *            . . ETR_RMP can be one of the following values
03913   *            @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_NC      (*)
03914   *            @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD1    (*)
03915   *            @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD2    (*)
03916   *            @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD3    (*)
03917   *            @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_NC      (*)
03918   *            @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD1    (*)
03919   *            @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD2    (*)
03920   *            @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD3    (*)
03921   *
03922   *         (*)  Value not defined in all devices. \n
03923   *         (**) Register not available in all devices.
03924   * @retval None
03925   */
03926 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
03927 {
03928   MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
03929 }
03930
03931 /**
03932   * @}
03933   */
03934
03935 #if defined(TIM_SMCR_OCCS)
03936 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
03937   * @{
03938   */
03939 /**
03940   * @brief  Set the OCREF clear input source
03941   * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
03942   * @note This function can only be used in Output compare and PWM modes.
03943   * @rmtoll SMCR          OCCS                LL_TIM_SetOCRefClearInputSource
03944   * @param  TIMx Timer instance
03945   * @param  OCRefClearInputSource This parameter can be one of the following values:
03946   *         @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
03947   *         @arg @ref LL_TIM_OCREF_CLR_INT_ETR
03948   * @retval None
03949   */
03950 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
03951 {
03952   MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
03953 }
03954 /**
03955   * @}
03956   */
03957 #endif /* TIM_SMCR_OCCS */
03958
03959 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
03960   * @{
03961   */
03962 /**
03963   * @brief  Clear the update interrupt flag (UIF).
03964   * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
03965   * @param  TIMx Timer instance
03966   * @retval None
03967   */
03968 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
03969 {
03970   WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
03971 }
03972
03973 /**
03974   * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
03975   * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
03976   * @param  TIMx Timer instance
03977   * @retval State of bit (1 or 0).
03978   */
03979 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
03980 {
03981   return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
03982 }
03983
03984 /**
03985   * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
03986   * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
03987   * @param  TIMx Timer instance
03988   * @retval None
03989   */
03990 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
03991 {
03992   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
03993 }
03994
03995 /**
03996   * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
03997   * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
03998   * @param  TIMx Timer instance
03999   * @retval State of bit (1 or 0).
04000   */
04001 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
04002 {
04003   return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
04004 }
04005
04006 /**
04007   * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
04008   * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
04009   * @param  TIMx Timer instance
04010   * @retval None
04011   */
04012 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
04013 {
04014   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
04015 }
04016
04017 /**
04018   * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
04019   * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
04020   * @param  TIMx Timer instance
04021   * @retval State of bit (1 or 0).
04022   */
04023 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
04024 {
04025   return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
04026 }
04027
04028 /**
04029   * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
04030   * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
04031   * @param  TIMx Timer instance
04032   * @retval None
04033   */
04034 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
04035 {
04036   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
04037 }
04038
04039 /**
04040   * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
04041   * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
04042   * @param  TIMx Timer instance
04043   * @retval State of bit (1 or 0).
04044   */
04045 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
04046 {
04047   return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
04048 }
04049
04050 /**
04051   * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
04052   * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
04053   * @param  TIMx Timer instance
04054   * @retval None
04055   */
04056 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
04057 {
04058   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
04059 }
04060
04061 /**
04062   * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
04063   * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
04064   * @param  TIMx Timer instance
04065   * @retval State of bit (1 or 0).
04066   */
04067 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
04068 {
04069   return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
04070 }
04071
04072 #if   defined (TIM_SR_CC5IF)
04073 /**
04074   * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
04075   * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
04076   * @param  TIMx Timer instance
04077   * @retval None
04078   */
04079 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
04080 {
04081   WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
04082 }
04083
04084 /**
04085   * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
04086   * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
04087   * @param  TIMx Timer instance
04088   * @retval State of bit (1 or 0).
04089   */
04090 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
04091 {
04092   return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF));
04093 }
04094
04095 #endif /* TIM_SR_CC5IF */
04096 #if   defined (TIM_SR_CC6IF)
04097 /**
04098   * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
04099   * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
04100   * @param  TIMx Timer instance
04101   * @retval None
04102   */
04103 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
04104 {
04105   WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
04106 }
04107
04108 /**
04109   * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
04110   * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
04111   * @param  TIMx Timer instance
04112   * @retval State of bit (1 or 0).
04113   */
04114 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
04115 {
04116   return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF));
04117 }
04118
04119 #endif /* TIM_SR_CC6IF */
04120 /**
04121   * @brief  Clear the commutation interrupt flag (COMIF).
04122   * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
04123   * @param  TIMx Timer instance
04124   * @retval None
04125   */
04126 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
04127 {
04128   WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
04129 }
04130
04131 /**
04132   * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
04133   * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
04134   * @param  TIMx Timer instance
04135   * @retval State of bit (1 or 0).
04136   */
04137 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
04138 {
04139   return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
04140 }
04141
04142 /**
04143   * @brief  Clear the trigger interrupt flag (TIF).
04144   * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
04145   * @param  TIMx Timer instance
04146   * @retval None
04147   */
04148 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
04149 {
04150   WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
04151 }
04152
04153 /**
04154   * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
04155   * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
04156   * @param  TIMx Timer instance
04157   * @retval State of bit (1 or 0).
04158   */
04159 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
04160 {
04161   return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
04162 }
04163
04164 /**
04165   * @brief  Clear the break interrupt flag (BIF).
04166   * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
04167   * @param  TIMx Timer instance
04168   * @retval None
04169   */
04170 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
04171 {
04172   WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
04173 }
04174
04175 /**
04176   * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
04177   * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
04178   * @param  TIMx Timer instance
04179   * @retval State of bit (1 or 0).
04180   */
04181 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
04182 {
04183   return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
04184 }
04185
04186 #if defined(TIM_SR_B2IF)
04187 /**
04188   * @brief  Clear the break 2 interrupt flag (B2IF).
04189   * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
04190   * @param  TIMx Timer instance
04191   * @retval None
04192   */
04193 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
04194 {
04195   WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
04196 }
04197
04198 /**
04199   * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
04200   * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
04201   * @param  TIMx Timer instance
04202   * @retval State of bit (1 or 0).
04203   */
04204 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
04205 {
04206   return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF));
04207 }
04208
04209 #endif /* TIM_SR_B2IF */
04210 /**
04211   * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
04212   * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
04213   * @param  TIMx Timer instance
04214   * @retval None
04215   */
04216 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
04217 {
04218   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
04219 }
04220
04221 /**
04222   * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
04223   * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
04224   * @param  TIMx Timer instance
04225   * @retval State of bit (1 or 0).
04226   */
04227 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
04228 {
04229   return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
04230 }
04231
04232 /**
04233   * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
04234   * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
04235   * @param  TIMx Timer instance
04236   * @retval None
04237   */
04238 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
04239 {
04240   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
04241 }
04242
04243 /**
04244   * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
04245   * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
04246   * @param  TIMx Timer instance
04247   * @retval State of bit (1 or 0).
04248   */
04249 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
04250 {
04251   return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
04252 }
04253
04254 /**
04255   * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
04256   * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
04257   * @param  TIMx Timer instance
04258   * @retval None
04259   */
04260 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
04261 {
04262   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
04263 }
04264
04265 /**
04266   * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
04267   * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
04268   * @param  TIMx Timer instance
04269   * @retval State of bit (1 or 0).
04270   */
04271 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
04272 {
04273   return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
04274 }
04275
04276 /**
04277   * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
04278   * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
04279   * @param  TIMx Timer instance
04280   * @retval None
04281   */
04282 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
04283 {
04284   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
04285 }
04286
04287 /**
04288   * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
04289   * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
04290   * @param  TIMx Timer instance
04291   * @retval State of bit (1 or 0).
04292   */
04293 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
04294 {
04295   return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
04296 }
04297
04298 /**
04299   * @}
04300   */
04301
04302 /** @defgroup TIM_LL_EF_IT_Management IT-Management
04303   * @{
04304   */
04305 /**
04306   * @brief  Enable update interrupt (UIE).
04307   * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
04308   * @param  TIMx Timer instance
04309   * @retval None
04310   */
04311 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
04312 {
04313   SET_BIT(TIMx->DIER, TIM_DIER_UIE);
04314 }
04315
04316 /**
04317   * @brief  Disable update interrupt (UIE).
04318   * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
04319   * @param  TIMx Timer instance
04320   * @retval None
04321   */
04322 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
04323 {
04324   CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
04325 }
04326
04327 /**
04328   * @brief  Indicates whether the update interrupt (UIE) is enabled.
04329   * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
04330   * @param  TIMx Timer instance
04331   * @retval State of bit (1 or 0).
04332   */
04333 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
04334 {
04335   return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
04336 }
04337
04338 /**
04339   * @brief  Enable capture/compare 1 interrupt (CC1IE).
04340   * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
04341   * @param  TIMx Timer instance
04342   * @retval None
04343   */
04344 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
04345 {
04346   SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
04347 }
04348
04349 /**
04350   * @brief  Disable capture/compare 1  interrupt (CC1IE).
04351   * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
04352   * @param  TIMx Timer instance
04353   * @retval None
04354   */
04355 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
04356 {
04357   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
04358 }
04359
04360 /**
04361   * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
04362   * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
04363   * @param  TIMx Timer instance
04364   * @retval State of bit (1 or 0).
04365   */
04366 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
04367 {
04368   return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
04369 }
04370
04371 /**
04372   * @brief  Enable capture/compare 2 interrupt (CC2IE).
04373   * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
04374   * @param  TIMx Timer instance
04375   * @retval None
04376   */
04377 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
04378 {
04379   SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
04380 }
04381
04382 /**
04383   * @brief  Disable capture/compare 2  interrupt (CC2IE).
04384   * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
04385   * @param  TIMx Timer instance
04386   * @retval None
04387   */
04388 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
04389 {
04390   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
04391 }
04392
04393 /**
04394   * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
04395   * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
04396   * @param  TIMx Timer instance
04397   * @retval State of bit (1 or 0).
04398   */
04399 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
04400 {
04401   return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
04402 }
04403
04404 /**
04405   * @brief  Enable capture/compare 3 interrupt (CC3IE).
04406   * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
04407   * @param  TIMx Timer instance
04408   * @retval None
04409   */
04410 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
04411 {
04412   SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
04413 }
04414
04415 /**
04416   * @brief  Disable capture/compare 3  interrupt (CC3IE).
04417   * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
04418   * @param  TIMx Timer instance
04419   * @retval None
04420   */
04421 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
04422 {
04423   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
04424 }
04425
04426 /**
04427   * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
04428   * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
04429   * @param  TIMx Timer instance
04430   * @retval State of bit (1 or 0).
04431   */
04432 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
04433 {
04434   return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
04435 }
04436
04437 /**
04438   * @brief  Enable capture/compare 4 interrupt (CC4IE).
04439   * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
04440   * @param  TIMx Timer instance
04441   * @retval None
04442   */
04443 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
04444 {
04445   SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
04446 }
04447
04448 /**
04449   * @brief  Disable capture/compare 4  interrupt (CC4IE).
04450   * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
04451   * @param  TIMx Timer instance
04452   * @retval None
04453   */
04454 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
04455 {
04456   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
04457 }
04458
04459 /**
04460   * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
04461   * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
04462   * @param  TIMx Timer instance
04463   * @retval State of bit (1 or 0).
04464   */
04465 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
04466 {
04467   return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
04468 }
04469
04470 /**
04471   * @brief  Enable commutation interrupt (COMIE).
04472   * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
04473   * @param  TIMx Timer instance
04474   * @retval None
04475   */
04476 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
04477 {
04478   SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
04479 }
04480
04481 /**
04482   * @brief  Disable commutation interrupt (COMIE).
04483   * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
04484   * @param  TIMx Timer instance
04485   * @retval None
04486   */
04487 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
04488 {
04489   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
04490 }
04491
04492 /**
04493   * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
04494   * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
04495   * @param  TIMx Timer instance
04496   * @retval State of bit (1 or 0).
04497   */
04498 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
04499 {
04500   return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
04501 }
04502
04503 /**
04504   * @brief  Enable trigger interrupt (TIE).
04505   * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
04506   * @param  TIMx Timer instance
04507   * @retval None
04508   */
04509 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
04510 {
04511   SET_BIT(TIMx->DIER, TIM_DIER_TIE);
04512 }
04513
04514 /**
04515   * @brief  Disable trigger interrupt (TIE).
04516   * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
04517   * @param  TIMx Timer instance
04518   * @retval None
04519   */
04520 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
04521 {
04522   CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
04523 }
04524
04525 /**
04526   * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
04527   * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
04528   * @param  TIMx Timer instance
04529   * @retval State of bit (1 or 0).
04530   */
04531 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
04532 {
04533   return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
04534 }
04535
04536 /**
04537   * @brief  Enable break interrupt (BIE).
04538   * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
04539   * @param  TIMx Timer instance
04540   * @retval None
04541   */
04542 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
04543 {
04544   SET_BIT(TIMx->DIER, TIM_DIER_BIE);
04545 }
04546
04547 /**
04548   * @brief  Disable break interrupt (BIE).
04549   * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
04550   * @param  TIMx Timer instance
04551   * @retval None
04552   */
04553 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
04554 {
04555   CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
04556 }
04557
04558 /**
04559   * @brief  Indicates whether the break interrupt (BIE) is enabled.
04560   * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
04561   * @param  TIMx Timer instance
04562   * @retval State of bit (1 or 0).
04563   */
04564 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
04565 {
04566   return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
04567 }
04568
04569 /**
04570   * @}
04571   */
04572
04573 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
04574   * @{
04575   */
04576 /**
04577   * @brief  Enable update DMA request (UDE).
04578   * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
04579   * @param  TIMx Timer instance
04580   * @retval None
04581   */
04582 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
04583 {
04584   SET_BIT(TIMx->DIER, TIM_DIER_UDE);
04585 }
04586
04587 /**
04588   * @brief  Disable update DMA request (UDE).
04589   * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
04590   * @param  TIMx Timer instance
04591   * @retval None
04592   */
04593 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
04594 {
04595   CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
04596 }
04597
04598 /**
04599   * @brief  Indicates whether the update DMA request  (UDE) is enabled.
04600   * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
04601   * @param  TIMx Timer instance
04602   * @retval State of bit (1 or 0).
04603   */
04604 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
04605 {
04606   return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
04607 }
04608
04609 /**
04610   * @brief  Enable capture/compare 1 DMA request (CC1DE).
04611   * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
04612   * @param  TIMx Timer instance
04613   * @retval None
04614   */
04615 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
04616 {
04617   SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
04618 }
04619
04620 /**
04621   * @brief  Disable capture/compare 1  DMA request (CC1DE).
04622   * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
04623   * @param  TIMx Timer instance
04624   * @retval None
04625   */
04626 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
04627 {
04628   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
04629 }
04630
04631 /**
04632   * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
04633   * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
04634   * @param  TIMx Timer instance
04635   * @retval State of bit (1 or 0).
04636   */
04637 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
04638 {
04639   return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
04640 }
04641
04642 /**
04643   * @brief  Enable capture/compare 2 DMA request (CC2DE).
04644   * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
04645   * @param  TIMx Timer instance
04646   * @retval None
04647   */
04648 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
04649 {
04650   SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
04651 }
04652
04653 /**
04654   * @brief  Disable capture/compare 2  DMA request (CC2DE).
04655   * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
04656   * @param  TIMx Timer instance
04657   * @retval None
04658   */
04659 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
04660 {
04661   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
04662 }
04663
04664 /**
04665   * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
04666   * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
04667   * @param  TIMx Timer instance
04668   * @retval State of bit (1 or 0).
04669   */
04670 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
04671 {
04672   return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
04673 }
04674
04675 /**
04676   * @brief  Enable capture/compare 3 DMA request (CC3DE).
04677   * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
04678   * @param  TIMx Timer instance
04679   * @retval None
04680   */
04681 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
04682 {
04683   SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
04684 }
04685
04686 /**
04687   * @brief  Disable capture/compare 3  DMA request (CC3DE).
04688   * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
04689   * @param  TIMx Timer instance
04690   * @retval None
04691   */
04692 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
04693 {
04694   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
04695 }
04696
04697 /**
04698   * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
04699   * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
04700   * @param  TIMx Timer instance
04701   * @retval State of bit (1 or 0).
04702   */
04703 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
04704 {
04705   return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
04706 }
04707
04708 /**
04709   * @brief  Enable capture/compare 4 DMA request (CC4DE).
04710   * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
04711   * @param  TIMx Timer instance
04712   * @retval None
04713   */
04714 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
04715 {
04716   SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
04717 }
04718
04719 /**
04720   * @brief  Disable capture/compare 4  DMA request (CC4DE).
04721   * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
04722   * @param  TIMx Timer instance
04723   * @retval None
04724   */
04725 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
04726 {
04727   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
04728 }
04729
04730 /**
04731   * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
04732   * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
04733   * @param  TIMx Timer instance
04734   * @retval State of bit (1 or 0).
04735   */
04736 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
04737 {
04738   return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
04739 }
04740
04741 /**
04742   * @brief  Enable commutation DMA request (COMDE).
04743   * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
04744   * @param  TIMx Timer instance
04745   * @retval None
04746   */
04747 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
04748 {
04749   SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
04750 }
04751
04752 /**
04753   * @brief  Disable commutation DMA request (COMDE).
04754   * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
04755   * @param  TIMx Timer instance
04756   * @retval None
04757   */
04758 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
04759 {
04760   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
04761 }
04762
04763 /**
04764   * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
04765   * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
04766   * @param  TIMx Timer instance
04767   * @retval State of bit (1 or 0).
04768   */
04769 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
04770 {
04771   return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
04772 }
04773
04774 /**
04775   * @brief  Enable trigger interrupt (TDE).
04776   * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
04777   * @param  TIMx Timer instance
04778   * @retval None
04779   */
04780 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
04781 {
04782   SET_BIT(TIMx->DIER, TIM_DIER_TDE);
04783 }
04784
04785 /**
04786   * @brief  Disable trigger interrupt (TDE).
04787   * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
04788   * @param  TIMx Timer instance
04789   * @retval None
04790   */
04791 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
04792 {
04793   CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
04794 }
04795
04796 /**
04797   * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
04798   * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
04799   * @param  TIMx Timer instance
04800   * @retval State of bit (1 or 0).
04801   */
04802 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
04803 {
04804   return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
04805 }
04806
04807 /**
04808   * @}
04809   */
04810
04811 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
04812   * @{
04813   */
04814 /**
04815   * @brief  Generate an update event.
04816   * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
04817   * @param  TIMx Timer instance
04818   * @retval None
04819   */
04820 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
04821 {
04822   SET_BIT(TIMx->EGR, TIM_EGR_UG);
04823 }
04824
04825 /**
04826   * @brief  Generate Capture/Compare 1 event.
04827   * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
04828   * @param  TIMx Timer instance
04829   * @retval None
04830   */
04831 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
04832 {
04833   SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
04834 }
04835
04836 /**
04837   * @brief  Generate Capture/Compare 2 event.
04838   * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
04839   * @param  TIMx Timer instance
04840   * @retval None
04841   */
04842 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
04843 {
04844   SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
04845 }
04846
04847 /**
04848   * @brief  Generate Capture/Compare 3 event.
04849   * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
04850   * @param  TIMx Timer instance
04851   * @retval None
04852   */
04853 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
04854 {
04855   SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
04856 }
04857
04858 /**
04859   * @brief  Generate Capture/Compare 4 event.
04860   * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
04861   * @param  TIMx Timer instance
04862   * @retval None
04863   */
04864 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
04865 {
04866   SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
04867 }
04868
04869 /**
04870   * @brief  Generate commutation event.
04871   * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
04872   * @param  TIMx Timer instance
04873   * @retval None
04874   */
04875 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
04876 {
04877   SET_BIT(TIMx->EGR, TIM_EGR_COMG);
04878 }
04879
04880 /**
04881   * @brief  Generate trigger event.
04882   * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
04883   * @param  TIMx Timer instance
04884   * @retval None
04885   */
04886 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
04887 {
04888   SET_BIT(TIMx->EGR, TIM_EGR_TG);
04889 }
04890
04891 /**
04892   * @brief  Generate break event.
04893   * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
04894   * @param  TIMx Timer instance
04895   * @retval None
04896   */
04897 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
04898 {
04899   SET_BIT(TIMx->EGR, TIM_EGR_BG);
04900 }
04901
04902 #if defined(TIM_EGR_B2G)
04903 /**
04904   * @brief  Generate break 2 event.
04905   * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
04906   * @param  TIMx Timer instance
04907   * @retval None
04908   */
04909 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
04910 {
04911   SET_BIT(TIMx->EGR, TIM_EGR_B2G);
04912 }
04913
04914 #endif /* TIM_EGR_B2G */
04915 /**
04916   * @}
04917   */
04918
04919 #if defined(USE_FULL_LL_DRIVER)
04920 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
04921   * @{
04922   */
04923
04924 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
04925 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
04926 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
04927 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
04928 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
04929 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
04930 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
04931 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
04932 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
04933 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
04934 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
04935 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
04936 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
04937 /**
04938   * @}
04939   */
04940 #endif /* USE_FULL_LL_DRIVER */
04941
04942 /**
04943   * @}
04944   */
04945
04946 /**
04947   * @}
04948   */
04949
04950 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 || TIM19 || TIM20 */
04951
04952 /**
04953   * @}
04954   */
04955
04956 #ifdef __cplusplus
04957 }
04958 #endif
04959
04960 #endif /* __STM32F3xx_LL_TIM_H */
04961 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_usart.c Source File

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stm32f3xx_ll_usart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_usart.c
00004   * @author  MCD Application Team
00005   * @brief   USART LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 #if defined(USE_FULL_LL_DRIVER)
00036
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f3xx_ll_usart.h"
00039 #include "stm32f3xx_ll_rcc.h"
00040 #include "stm32f3xx_ll_bus.h"
00041 #ifdef  USE_FULL_ASSERT
00042 #include "stm32_assert.h"
00043 #else
00044 #define assert_param(expr) ((void)0U)
00045 #endif
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
00052
00053 /** @addtogroup USART_LL
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059 /* Private constants ---------------------------------------------------------*/
00060 /** @addtogroup USART_LL_Private_Constants
00061   * @{
00062   */
00063
00064 /**
00065   * @}
00066   */
00067
00068
00069 /* Private macros ------------------------------------------------------------*/
00070 /** @addtogroup USART_LL_Private_Macros
00071   * @{
00072   */
00073
00074 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
00075  *              divided by the smallest oversampling used on the USART (i.e. 8)    */
00076 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 9000000U)
00077
00078 /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
00079 #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
00080
00081 /* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
00082 #define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
00083
00084 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
00085                                        || ((__VALUE__) == LL_USART_DIRECTION_RX) \
00086                                        || ((__VALUE__) == LL_USART_DIRECTION_TX) \
00087                                        || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
00088
00089 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
00090                                     || ((__VALUE__) == LL_USART_PARITY_EVEN) \
00091                                     || ((__VALUE__) == LL_USART_PARITY_ODD))
00092
00093 #if defined(USART_7BITS_SUPPORT)
00094 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
00095                                        || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
00096                                        || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
00097 #else
00098 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
00099                                        || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
00100 #endif
00101
00102 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
00103                                           || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
00104
00105 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
00106                                               || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
00107
00108 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
00109                                         || ((__VALUE__) == LL_USART_PHASE_2EDGE))
00110
00111 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
00112                                            || ((__VALUE__) == LL_USART_POLARITY_HIGH))
00113
00114 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
00115                                          || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
00116
00117 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
00118                                       || ((__VALUE__) == LL_USART_STOPBITS_1) \
00119                                       || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
00120                                       || ((__VALUE__) == LL_USART_STOPBITS_2))
00121
00122 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
00123                                        || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
00124                                        || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
00125                                        || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
00126
00127 /**
00128   * @}
00129   */
00130
00131 /* Private function prototypes -----------------------------------------------*/
00132
00133 /* Exported functions --------------------------------------------------------*/
00134 /** @addtogroup USART_LL_Exported_Functions
00135   * @{
00136   */
00137
00138 /** @addtogroup USART_LL_EF_Init
00139   * @{
00140   */
00141
00142 /**
00143   * @brief  De-initialize USART registers (Registers restored to their default values).
00144   * @param  USARTx USART Instance
00145   * @retval An ErrorStatus enumeration value:
00146   *          - SUCCESS: USART registers are de-initialized
00147   *          - ERROR: USART registers are not de-initialized
00148   */
00149 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
00150 {
00151   ErrorStatus status = SUCCESS;
00152
00153   /* Check the parameters */
00154   assert_param(IS_UART_INSTANCE(USARTx));
00155
00156   if (USARTx == USART1)
00157   {
00158     /* Force reset of USART clock */
00159     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
00160
00161     /* Release reset of USART clock */
00162     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
00163   }
00164   else if (USARTx == USART2)
00165   {
00166     /* Force reset of USART clock */
00167     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
00168
00169     /* Release reset of USART clock */
00170     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
00171   }
00172   else if (USARTx == USART3)
00173   {
00174     /* Force reset of USART clock */
00175     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
00176
00177     /* Release reset of USART clock */
00178     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
00179   }
00180 #if defined(UART4)
00181   else if (USARTx == UART4)
00182   {
00183     /* Force reset of UART clock */
00184     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
00185
00186     /* Release reset of UART clock */
00187     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
00188   }
00189 #endif /* UART4 */
00190 #if defined(UART5)
00191   else if (USARTx == UART5)
00192   {
00193     /* Force reset of UART clock */
00194     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
00195
00196     /* Release reset of UART clock */
00197     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
00198   }
00199 #endif /* UART5 */
00200   else
00201   {
00202     status = ERROR;
00203   }
00204
00205   return (status);
00206 }
00207
00208 /**
00209   * @brief  Initialize USART registers according to the specified
00210   *         parameters in USART_InitStruct.
00211   * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
00212   *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00213   * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
00214   * @param  USARTx USART Instance
00215   * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure
00216   *         that contains the configuration information for the specified USART peripheral.
00217   * @retval An ErrorStatus enumeration value:
00218   *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
00219   *          - ERROR: Problem occurred during USART Registers initialization
00220   */
00221 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
00222 {
00223   ErrorStatus status = ERROR;
00224   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
00225 #if defined(STM32F303x8)||defined(STM32F334x8)||defined(STM32F328xx)||defined(STM32F301x8)||defined(STM32F302x8)||defined(STM32F318xx)
00226   LL_RCC_ClocksTypeDef RCC_Clocks;
00227 #endif
00228
00229   /* Check the parameters */
00230   assert_param(IS_UART_INSTANCE(USARTx));
00231   assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
00232   assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
00233   assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
00234   assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
00235   assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
00236   assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
00237   assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
00238
00239   /* USART needs to be in disabled state, in order to be able to configure some bits in
00240      CRx registers */
00241   if (LL_USART_IsEnabled(USARTx) == 0U)
00242   {
00243     /*---------------------------- USART CR1 Configuration ---------------------
00244      * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
00245      * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
00246      * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
00247      * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
00248      * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
00249      */
00250     MODIFY_REG(USARTx->CR1,
00251                (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
00252                 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
00253                (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
00254                 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
00255
00256     /*---------------------------- USART CR2 Configuration ---------------------
00257      * Configure USARTx CR2 (Stop bits) with parameters:
00258      * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
00259      * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
00260      */
00261     LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
00262
00263     /*---------------------------- USART CR3 Configuration ---------------------
00264      * Configure USARTx CR3 (Hardware Flow Control) with parameters:
00265      * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
00266      */
00267     LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
00268
00269     /*---------------------------- USART BRR Configuration ---------------------
00270      * Retrieve Clock frequency used for USART Peripheral
00271      */
00272     if (USARTx == USART1)
00273     {
00274       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
00275     }
00276     else if (USARTx == USART2)
00277     {
00278 #if defined (RCC_CFGR3_USART2SW)
00279       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
00280 #else
00281       /* USART2 clock is PCLK */
00282       LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
00283       periphclk = RCC_Clocks.PCLK1_Frequency;
00284 #endif
00285     }
00286     else if (USARTx == USART3)
00287     {
00288 #if defined (RCC_CFGR3_USART3SW)
00289       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
00290 #else
00291       /* USART3 clock is PCLK */
00292       LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
00293       periphclk = RCC_Clocks.PCLK1_Frequency;
00294 #endif
00295     }
00296 #if defined(UART4)
00297     else if (USARTx == UART4)
00298     {
00299       periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
00300     }
00301 #endif /* UART4 */
00302 #if defined(UART5)
00303     else if (USARTx == UART5)
00304     {
00305       periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);
00306     }
00307 #endif /* UART5 */
00308     else
00309     {
00310       /* Nothing to do, as error code is already assigned to ERROR value */
00311     }
00312
00313     /* Configure the USART Baud Rate :
00314        - valid baud rate value (different from 0) is required
00315        - Peripheral clock as returned by RCC service, should be valid (different from 0).
00316     */
00317     if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
00318         && (USART_InitStruct->BaudRate != 0U))
00319     {
00320       status = SUCCESS;
00321       LL_USART_SetBaudRate(USARTx,
00322                            periphclk,
00323                            USART_InitStruct->OverSampling,
00324                            USART_InitStruct->BaudRate);
00325
00326       /* Check BRR is greater than or equal to 16d */
00327       assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
00328
00329       /* Check BRR is greater than or equal to 16d */
00330       assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
00331     }
00332   }
00333   /* Endif (=> USART not in Disabled state => return ERROR) */
00334
00335   return (status);
00336 }
00337
00338 /**
00339   * @brief Set each @ref LL_USART_InitTypeDef field to default value.
00340   * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
00341   *                          whose fields will be set to default values.
00342   * @retval None
00343   */
00344
00345 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
00346 {
00347   /* Set USART_InitStruct fields to default values */
00348   USART_InitStruct->BaudRate            = 9600U;
00349   USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
00350   USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
00351   USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
00352   USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
00353   USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
00354   USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
00355 }
00356
00357 /**
00358   * @brief  Initialize USART Clock related settings according to the
00359   *         specified parameters in the USART_ClockInitStruct.
00360   * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
00361   *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00362   * @param  USARTx USART Instance
00363   * @param  USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
00364   *         that contains the Clock configuration information for the specified USART peripheral.
00365   * @retval An ErrorStatus enumeration value:
00366   *          - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
00367   *          - ERROR: Problem occurred during USART Registers initialization
00368   */
00369 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
00370 {
00371   ErrorStatus status = SUCCESS;
00372
00373   /* Check USART Instance and Clock signal output parameters */
00374   assert_param(IS_UART_INSTANCE(USARTx));
00375   assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
00376
00377   /* USART needs to be in disabled state, in order to be able to configure some bits in
00378      CRx registers */
00379   if (LL_USART_IsEnabled(USARTx) == 0U)
00380   {
00381     /*---------------------------- USART CR2 Configuration -----------------------*/
00382     /* If Clock signal has to be output */
00383     if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
00384     {
00385       /* Deactivate Clock signal delivery :
00386        * - Disable Clock Output:        USART_CR2_CLKEN cleared
00387        */
00388       LL_USART_DisableSCLKOutput(USARTx);
00389     }
00390     else
00391     {
00392       /* Ensure USART instance is USART capable */
00393       assert_param(IS_USART_INSTANCE(USARTx));
00394
00395       /* Check clock related parameters */
00396       assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
00397       assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
00398       assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
00399
00400       /*---------------------------- USART CR2 Configuration -----------------------
00401        * Configure USARTx CR2 (Clock signal related bits) with parameters:
00402        * - Enable Clock Output:         USART_CR2_CLKEN set
00403        * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
00404        * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
00405        * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
00406        */
00407       MODIFY_REG(USARTx->CR2,
00408                  USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
00409                  USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
00410                  USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
00411     }
00412   }
00413   /* Else (USART not in Disabled state => return ERROR */
00414   else
00415   {
00416     status = ERROR;
00417   }
00418
00419   return (status);
00420 }
00421
00422 /**
00423   * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
00424   * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
00425   *                               whose fields will be set to default values.
00426   * @retval None
00427   */
00428 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
00429 {
00430   /* Set LL_USART_ClockInitStruct fields with default values */
00431   USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
00432   USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00433   USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00434   USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00435 }
00436
00437 /**
00438   * @}
00439   */
00440
00441 /**
00442   * @}
00443   */
00444
00445 /**
00446   * @}
00447   */
00448
00449 #endif /* USART1 || USART2|| USART3 || UART4 || UART5 */
00450
00451 /**
00452   * @}
00453   */
00454
00455 #endif /* USE_FULL_LL_DRIVER */
00456
00457 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00458
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_usart.h Source File

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stm32f3xx_ll_usart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_usart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of USART LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_USART_H
00038 #define __STM32F3xx_LL_USART_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
00052
00053 /** @defgroup USART_LL USART
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059
00060 /* Private constants ---------------------------------------------------------*/
00061 /** @defgroup USART_LL_Private_Constants USART Private Constants
00062   * @{
00063   */
00064 /**
00065   * @}
00066   */
00067
00068 /* Private macros ------------------------------------------------------------*/
00069 #if defined(USE_FULL_LL_DRIVER)
00070 /** @defgroup USART_LL_Private_Macros USART Private Macros
00071   * @{
00072   */
00073 /**
00074   * @}
00075   */
00076 #endif /*USE_FULL_LL_DRIVER*/
00077
00078 /* Exported types ------------------------------------------------------------*/
00079 #if defined(USE_FULL_LL_DRIVER)
00080 /** @defgroup USART_LL_ES_INIT USART Exported Init structures
00081   * @{
00082   */
00083
00084 /**
00085   * @brief LL USART Init Structure definition
00086   */
00087 typedef struct
00088 {
00089   uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
00090
00091                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
00092
00093   uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
00094                                            This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
00095
00096                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
00097
00098   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00099                                            This parameter can be a value of @ref USART_LL_EC_STOPBITS.
00100
00101                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
00102
00103   uint32_t Parity;                    /*!< Specifies the parity mode.
00104                                            This parameter can be a value of @ref USART_LL_EC_PARITY.
00105
00106                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
00107
00108   uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
00109                                            This parameter can be a value of @ref USART_LL_EC_DIRECTION.
00110
00111                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
00112
00113   uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
00114                                            This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
00115
00116                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
00117
00118   uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
00119                                            This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
00120
00121                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
00122
00123 } LL_USART_InitTypeDef;
00124
00125 /**
00126   * @brief LL USART Clock Init Structure definition
00127   */
00128 typedef struct
00129 {
00130   uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
00131                                            This parameter can be a value of @ref USART_LL_EC_CLOCK.
00132
00133                                            USART HW configuration can be modified afterwards using unitary functions
00134                                            @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
00135                                            For more details, refer to description of this function. */
00136
00137   uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
00138                                            This parameter can be a value of @ref USART_LL_EC_POLARITY.
00139
00140                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
00141                                            For more details, refer to description of this function. */
00142
00143   uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
00144                                            This parameter can be a value of @ref USART_LL_EC_PHASE.
00145
00146                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
00147                                            For more details, refer to description of this function. */
00148
00149   uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
00150                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00151                                            This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
00152
00153                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
00154                                            For more details, refer to description of this function. */
00155
00156 } LL_USART_ClockInitTypeDef;
00157
00158 /**
00159   * @}
00160   */
00161 #endif /* USE_FULL_LL_DRIVER */
00162
00163 /* Exported constants --------------------------------------------------------*/
00164 /** @defgroup USART_LL_Exported_Constants USART Exported Constants
00165   * @{
00166   */
00167
00168 /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
00169   * @brief    Flags defines which can be used with LL_USART_WriteReg function
00170   * @{
00171   */
00172 #define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error flag */
00173 #define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error flag */
00174 #define LL_USART_ICR_NCF                        USART_ICR_NCF                 /*!< Noise detected flag */
00175 #define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error flag */
00176 #define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected flag */
00177 #define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete flag */
00178 #define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection flag */
00179 #define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS flag */
00180 #define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout flag */
00181 #define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block flag */
00182 #define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match flag */
00183 #define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
00189   * @brief    Flags defines which can be used with LL_USART_ReadReg function
00190   * @{
00191   */
00192 #define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
00193 #define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
00194 #define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
00195 #define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
00196 #define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
00197 #define LL_USART_ISR_RXNE                       USART_ISR_RXNE                /*!< Read data register not empty flag */
00198 #define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
00199 #define LL_USART_ISR_TXE                        USART_ISR_TXE                 /*!< Transmit data register empty flag */
00200 #define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
00201 #define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
00202 #define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
00203 #define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
00204 #define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
00205 #define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
00206 #define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
00207 #define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
00208 #define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
00209 #define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
00210 #define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
00211 #define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
00212 #define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
00213 #define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup USART_LL_EC_IT IT Defines
00219   * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
00220   * @{
00221   */
00222 #define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
00223 #define LL_USART_CR1_RXNEIE                     USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */
00224 #define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
00225 #define LL_USART_CR1_TXEIE                      USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */
00226 #define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
00227 #define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
00228 #define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
00229 #define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
00230 #define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
00231 #define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
00232 #define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
00233 #define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup USART_LL_EC_DIRECTION Communication Direction
00239   * @{
00240   */
00241 #define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
00242 #define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
00243 #define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
00244 #define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup USART_LL_EC_PARITY Parity Control
00250   * @{
00251   */
00252 #define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
00253 #define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
00254 #define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup USART_LL_EC_WAKEUP Wakeup
00260   * @{
00261   */
00262 #define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
00263 #define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup USART_LL_EC_DATAWIDTH Datawidth
00269   * @{
00270   */
00271 #if defined(USART_7BITS_SUPPORT)
00272 #define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
00273 #define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
00274 #define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
00275 #else
00276 #define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
00277 #define LL_USART_DATAWIDTH_9B                   USART_CR1_M             /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
00278 #endif
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
00284   * @{
00285   */
00286 #define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
00287 #define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
00288 /**
00289   * @}
00290   */
00291
00292 #if defined(USE_FULL_LL_DRIVER)
00293 /** @defgroup USART_LL_EC_CLOCK Clock Signal
00294   * @{
00295   */
00296
00297 #define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
00298 #define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
00299 /**
00300   * @}
00301   */
00302 #endif /*USE_FULL_LL_DRIVER*/
00303
00304 /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
00305   * @{
00306   */
00307 #define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
00308 #define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup USART_LL_EC_PHASE Clock Phase
00314   * @{
00315   */
00316 #define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
00317 #define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup USART_LL_EC_POLARITY Clock Polarity
00323   * @{
00324   */
00325 #define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
00326 #define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
00327 /**
00328   * @}
00329   */
00330
00331 /** @defgroup USART_LL_EC_STOPBITS Stop Bits
00332   * @{
00333   */
00334 #define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
00335 #define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
00336 #define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
00337 #define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
00338 /**
00339   * @}
00340   */
00341
00342 /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
00343   * @{
00344   */
00345 #define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
00346 #define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
00347 /**
00348   * @}
00349   */
00350
00351 /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
00352   * @{
00353   */
00354 #define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
00355 #define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
00361   * @{
00362   */
00363 #define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
00364 #define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
00365 /**
00366   * @}
00367   */
00368
00369 /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
00370   * @{
00371   */
00372 #define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
00373 #define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
00374 /**
00375   * @}
00376   */
00377
00378 /** @defgroup USART_LL_EC_BITORDER Bit Order
00379   * @{
00380   */
00381 #define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
00382 #define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
00383 /**
00384   * @}
00385   */
00386
00387 /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
00388   * @{
00389   */
00390 #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
00391 #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
00392 #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
00393 #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
00394 /**
00395   * @}
00396   */
00397
00398 /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
00399   * @{
00400   */
00401 #define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
00402 #define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
00403 /**
00404   * @}
00405   */
00406
00407 /** @defgroup USART_LL_EC_HWCONTROL Hardware Control
00408   * @{
00409   */
00410 #define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
00411 #define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
00412 #define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
00413 #define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
00414 /**
00415   * @}
00416   */
00417
00418 /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
00419   * @{
00420   */
00421 #define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
00422 #define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
00423 #define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
00424 /**
00425   * @}
00426   */
00427
00428 /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
00429   * @{
00430   */
00431 #define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
00432 #define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
00433 /**
00434   * @}
00435   */
00436
00437 /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
00438   * @{
00439   */
00440 #define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
00441 #define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
00442 /**
00443   * @}
00444   */
00445
00446 /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
00447   * @{
00448   */
00449 #define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
00450 #define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
00451 /**
00452   * @}
00453   */
00454
00455 /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
00456   * @{
00457   */
00458 #define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
00459 #define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
00460 /**
00461   * @}
00462   */
00463
00464 /**
00465   * @}
00466   */
00467
00468 /* Exported macro ------------------------------------------------------------*/
00469 /** @defgroup USART_LL_Exported_Macros USART Exported Macros
00470   * @{
00471   */
00472
00473 /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
00474   * @{
00475   */
00476
00477 /**
00478   * @brief  Write a value in USART register
00479   * @param  __INSTANCE__ USART Instance
00480   * @param  __REG__ Register to be written
00481   * @param  __VALUE__ Value to be written in the register
00482   * @retval None
00483   */
00484 #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00485
00486 /**
00487   * @brief  Read a value in USART register
00488   * @param  __INSTANCE__ USART Instance
00489   * @param  __REG__ Register to be read
00490   * @retval Register value
00491   */
00492 #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00493 /**
00494   * @}
00495   */
00496
00497 /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
00498   * @{
00499   */
00500
00501 /**
00502   * @brief  Compute USARTDIV value according to Peripheral Clock and
00503   *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
00504   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
00505   * @param  __BAUDRATE__ Baud rate value to achieve
00506   * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
00507   */
00508 #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
00509
00510 /**
00511   * @brief  Compute USARTDIV value according to Peripheral Clock and
00512   *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
00513   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
00514   * @param  __BAUDRATE__ Baud rate value to achieve
00515   * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
00516   */
00517 #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
00518
00519 /**
00520   * @}
00521   */
00522
00523 /**
00524   * @}
00525   */
00526
00527 /* Exported functions --------------------------------------------------------*/
00528
00529 /** @defgroup USART_LL_Exported_Functions USART Exported Functions
00530   * @{
00531   */
00532
00533 /** @defgroup USART_LL_EF_Configuration Configuration functions
00534   * @{
00535   */
00536
00537 /**
00538   * @brief  USART Enable
00539   * @rmtoll CR1          UE            LL_USART_Enable
00540   * @param  USARTx USART Instance
00541   * @retval None
00542   */
00543 __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
00544 {
00545   SET_BIT(USARTx->CR1, USART_CR1_UE);
00546 }
00547
00548 /**
00549   * @brief  USART Disable (all USART prescalers and outputs are disabled)
00550   * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
00551   *         and current operations are discarded. The configuration of the USART is kept, but all the status
00552   *         flags, in the USARTx_ISR are set to their default values.
00553   * @rmtoll CR1          UE            LL_USART_Disable
00554   * @param  USARTx USART Instance
00555   * @retval None
00556   */
00557 __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
00558 {
00559   CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
00560 }
00561
00562 /**
00563   * @brief  Indicate if USART is enabled
00564   * @rmtoll CR1          UE            LL_USART_IsEnabled
00565   * @param  USARTx USART Instance
00566   * @retval State of bit (1 or 0).
00567   */
00568 __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
00569 {
00570   return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
00571 }
00572
00573 /**
00574   * @brief  USART enabled in STOP Mode.
00575   * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
00576   *         USART clock selection is HSI or LSE in RCC.
00577   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00578   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00579   * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
00580   * @param  USARTx USART Instance
00581   * @retval None
00582   */
00583 __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
00584 {
00585   SET_BIT(USARTx->CR1, USART_CR1_UESM);
00586 }
00587
00588 /**
00589   * @brief  USART disabled in STOP Mode.
00590   * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
00591   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00592   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00593   * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
00594   * @param  USARTx USART Instance
00595   * @retval None
00596   */
00597 __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
00598 {
00599   CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
00600 }
00601
00602 /**
00603   * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
00604   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00605   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00606   * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
00607   * @param  USARTx USART Instance
00608   * @retval State of bit (1 or 0).
00609   */
00610 __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
00611 {
00612   return (READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
00613 }
00614
00615 /**
00616   * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
00617   * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
00618   * @param  USARTx USART Instance
00619   * @retval None
00620   */
00621 __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
00622 {
00623   SET_BIT(USARTx->CR1, USART_CR1_RE);
00624 }
00625
00626 /**
00627   * @brief  Receiver Disable
00628   * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
00629   * @param  USARTx USART Instance
00630   * @retval None
00631   */
00632 __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
00633 {
00634   CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
00635 }
00636
00637 /**
00638   * @brief  Transmitter Enable
00639   * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
00640   * @param  USARTx USART Instance
00641   * @retval None
00642   */
00643 __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
00644 {
00645   SET_BIT(USARTx->CR1, USART_CR1_TE);
00646 }
00647
00648 /**
00649   * @brief  Transmitter Disable
00650   * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
00651   * @param  USARTx USART Instance
00652   * @retval None
00653   */
00654 __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
00655 {
00656   CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
00657 }
00658
00659 /**
00660   * @brief  Configure simultaneously enabled/disabled states
00661   *         of Transmitter and Receiver
00662   * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
00663   *         CR1          TE            LL_USART_SetTransferDirection
00664   * @param  USARTx USART Instance
00665   * @param  TransferDirection This parameter can be one of the following values:
00666   *         @arg @ref LL_USART_DIRECTION_NONE
00667   *         @arg @ref LL_USART_DIRECTION_RX
00668   *         @arg @ref LL_USART_DIRECTION_TX
00669   *         @arg @ref LL_USART_DIRECTION_TX_RX
00670   * @retval None
00671   */
00672 __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
00673 {
00674   MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
00675 }
00676
00677 /**
00678   * @brief  Return enabled/disabled states of Transmitter and Receiver
00679   * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
00680   *         CR1          TE            LL_USART_GetTransferDirection
00681   * @param  USARTx USART Instance
00682   * @retval Returned value can be one of the following values:
00683   *         @arg @ref LL_USART_DIRECTION_NONE
00684   *         @arg @ref LL_USART_DIRECTION_RX
00685   *         @arg @ref LL_USART_DIRECTION_TX
00686   *         @arg @ref LL_USART_DIRECTION_TX_RX
00687   */
00688 __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
00689 {
00690   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
00691 }
00692
00693 /**
00694   * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
00695   * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
00696   *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
00697   *         (9th or 8th bit depending on data width) and parity is checked on the received data.
00698   * @rmtoll CR1          PS            LL_USART_SetParity\n
00699   *         CR1          PCE           LL_USART_SetParity
00700   * @param  USARTx USART Instance
00701   * @param  Parity This parameter can be one of the following values:
00702   *         @arg @ref LL_USART_PARITY_NONE
00703   *         @arg @ref LL_USART_PARITY_EVEN
00704   *         @arg @ref LL_USART_PARITY_ODD
00705   * @retval None
00706   */
00707 __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
00708 {
00709   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
00710 }
00711
00712 /**
00713   * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
00714   * @rmtoll CR1          PS            LL_USART_GetParity\n
00715   *         CR1          PCE           LL_USART_GetParity
00716   * @param  USARTx USART Instance
00717   * @retval Returned value can be one of the following values:
00718   *         @arg @ref LL_USART_PARITY_NONE
00719   *         @arg @ref LL_USART_PARITY_EVEN
00720   *         @arg @ref LL_USART_PARITY_ODD
00721   */
00722 __STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
00723 {
00724   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
00725 }
00726
00727 /**
00728   * @brief  Set Receiver Wake Up method from Mute mode.
00729   * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
00730   * @param  USARTx USART Instance
00731   * @param  Method This parameter can be one of the following values:
00732   *         @arg @ref LL_USART_WAKEUP_IDLELINE
00733   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
00734   * @retval None
00735   */
00736 __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
00737 {
00738   MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
00739 }
00740
00741 /**
00742   * @brief  Return Receiver Wake Up method from Mute mode
00743   * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
00744   * @param  USARTx USART Instance
00745   * @retval Returned value can be one of the following values:
00746   *         @arg @ref LL_USART_WAKEUP_IDLELINE
00747   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
00748   */
00749 __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
00750 {
00751   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
00752 }
00753
00754 /**
00755   * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
00756   * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
00757   *         CR1          M1            LL_USART_SetDataWidth
00758   * @param  USARTx USART Instance
00759   * @param  DataWidth This parameter can be one of the following values:
00760   *         @arg @ref LL_USART_DATAWIDTH_7B (*)
00761   *         @arg @ref LL_USART_DATAWIDTH_8B
00762   *         @arg @ref LL_USART_DATAWIDTH_9B
00763   *
00764   *         (*) Values not available on all devices
00765   * @retval None
00766   */
00767 __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
00768 {
00769   MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
00770 }
00771
00772 /**
00773   * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
00774   * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
00775   *         CR1          M1            LL_USART_GetDataWidth
00776   * @param  USARTx USART Instance
00777   * @retval Returned value can be one of the following values:
00778   *         @arg @ref LL_USART_DATAWIDTH_7B (*)
00779   *         @arg @ref LL_USART_DATAWIDTH_8B
00780   *         @arg @ref LL_USART_DATAWIDTH_9B
00781   *
00782   *         (*) Values not available on all devices
00783   */
00784 __STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
00785 {
00786   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
00787 }
00788
00789 /**
00790   * @brief  Allow switch between Mute Mode and Active mode
00791   * @rmtoll CR1          MME           LL_USART_EnableMuteMode
00792   * @param  USARTx USART Instance
00793   * @retval None
00794   */
00795 __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
00796 {
00797   SET_BIT(USARTx->CR1, USART_CR1_MME);
00798 }
00799
00800 /**
00801   * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
00802   * @rmtoll CR1          MME           LL_USART_DisableMuteMode
00803   * @param  USARTx USART Instance
00804   * @retval None
00805   */
00806 __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
00807 {
00808   CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
00809 }
00810
00811 /**
00812   * @brief  Indicate if switch between Mute Mode and Active mode is allowed
00813   * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
00814   * @param  USARTx USART Instance
00815   * @retval State of bit (1 or 0).
00816   */
00817 __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
00818 {
00819   return (READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));
00820 }
00821
00822 /**
00823   * @brief  Set Oversampling to 8-bit or 16-bit mode
00824   * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
00825   * @param  USARTx USART Instance
00826   * @param  OverSampling This parameter can be one of the following values:
00827   *         @arg @ref LL_USART_OVERSAMPLING_16
00828   *         @arg @ref LL_USART_OVERSAMPLING_8
00829   * @retval None
00830   */
00831 __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
00832 {
00833   MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
00834 }
00835
00836 /**
00837   * @brief  Return Oversampling mode
00838   * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
00839   * @param  USARTx USART Instance
00840   * @retval Returned value can be one of the following values:
00841   *         @arg @ref LL_USART_OVERSAMPLING_16
00842   *         @arg @ref LL_USART_OVERSAMPLING_8
00843   */
00844 __STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
00845 {
00846   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
00847 }
00848
00849 /**
00850   * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
00851   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00852   *         Synchronous mode is supported by the USARTx instance.
00853   * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
00854   * @param  USARTx USART Instance
00855   * @param  LastBitClockPulse This parameter can be one of the following values:
00856   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
00857   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
00858   * @retval None
00859   */
00860 __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
00861 {
00862   MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
00863 }
00864
00865 /**
00866   * @brief  Retrieve Clock pulse of the last data bit output configuration
00867   *         (Last bit Clock pulse output to the SCLK pin or not)
00868   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00869   *         Synchronous mode is supported by the USARTx instance.
00870   * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
00871   * @param  USARTx USART Instance
00872   * @retval Returned value can be one of the following values:
00873   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
00874   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
00875   */
00876 __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
00877 {
00878   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
00879 }
00880
00881 /**
00882   * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
00883   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00884   *         Synchronous mode is supported by the USARTx instance.
00885   * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
00886   * @param  USARTx USART Instance
00887   * @param  ClockPhase This parameter can be one of the following values:
00888   *         @arg @ref LL_USART_PHASE_1EDGE
00889   *         @arg @ref LL_USART_PHASE_2EDGE
00890   * @retval None
00891   */
00892 __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
00893 {
00894   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
00895 }
00896
00897 /**
00898   * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
00899   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00900   *         Synchronous mode is supported by the USARTx instance.
00901   * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
00902   * @param  USARTx USART Instance
00903   * @retval Returned value can be one of the following values:
00904   *         @arg @ref LL_USART_PHASE_1EDGE
00905   *         @arg @ref LL_USART_PHASE_2EDGE
00906   */
00907 __STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
00908 {
00909   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
00910 }
00911
00912 /**
00913   * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
00914   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00915   *         Synchronous mode is supported by the USARTx instance.
00916   * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
00917   * @param  USARTx USART Instance
00918   * @param  ClockPolarity This parameter can be one of the following values:
00919   *         @arg @ref LL_USART_POLARITY_LOW
00920   *         @arg @ref LL_USART_POLARITY_HIGH
00921   * @retval None
00922   */
00923 __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
00924 {
00925   MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
00926 }
00927
00928 /**
00929   * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
00930   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00931   *         Synchronous mode is supported by the USARTx instance.
00932   * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
00933   * @param  USARTx USART Instance
00934   * @retval Returned value can be one of the following values:
00935   *         @arg @ref LL_USART_POLARITY_LOW
00936   *         @arg @ref LL_USART_POLARITY_HIGH
00937   */
00938 __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
00939 {
00940   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
00941 }
00942
00943 /**
00944   * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
00945   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00946   *         Synchronous mode is supported by the USARTx instance.
00947   * @note   Call of this function is equivalent to following function call sequence :
00948   *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
00949   *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
00950   *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
00951   * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
00952   *         CR2          CPOL          LL_USART_ConfigClock\n
00953   *         CR2          LBCL          LL_USART_ConfigClock
00954   * @param  USARTx USART Instance
00955   * @param  Phase This parameter can be one of the following values:
00956   *         @arg @ref LL_USART_PHASE_1EDGE
00957   *         @arg @ref LL_USART_PHASE_2EDGE
00958   * @param  Polarity This parameter can be one of the following values:
00959   *         @arg @ref LL_USART_POLARITY_LOW
00960   *         @arg @ref LL_USART_POLARITY_HIGH
00961   * @param  LBCPOutput This parameter can be one of the following values:
00962   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
00963   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
00964   * @retval None
00965   */
00966 __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
00967 {
00968   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
00969 }
00970
00971 /**
00972   * @brief  Enable Clock output on SCLK pin
00973   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00974   *         Synchronous mode is supported by the USARTx instance.
00975   * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
00976   * @param  USARTx USART Instance
00977   * @retval None
00978   */
00979 __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
00980 {
00981   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
00982 }
00983
00984 /**
00985   * @brief  Disable Clock output on SCLK pin
00986   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00987   *         Synchronous mode is supported by the USARTx instance.
00988   * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
00989   * @param  USARTx USART Instance
00990   * @retval None
00991   */
00992 __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
00993 {
00994   CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
00995 }
00996
00997 /**
00998   * @brief  Indicate if Clock output on SCLK pin is enabled
00999   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01000   *         Synchronous mode is supported by the USARTx instance.
01001   * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
01002   * @param  USARTx USART Instance
01003   * @retval State of bit (1 or 0).
01004   */
01005 __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
01006 {
01007   return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
01008 }
01009
01010 /**
01011   * @brief  Set the length of the stop bits
01012   * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
01013   * @param  USARTx USART Instance
01014   * @param  StopBits This parameter can be one of the following values:
01015   *         @arg @ref LL_USART_STOPBITS_0_5
01016   *         @arg @ref LL_USART_STOPBITS_1
01017   *         @arg @ref LL_USART_STOPBITS_1_5
01018   *         @arg @ref LL_USART_STOPBITS_2
01019   * @retval None
01020   */
01021 __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
01022 {
01023   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
01024 }
01025
01026 /**
01027   * @brief  Retrieve the length of the stop bits
01028   * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
01029   * @param  USARTx USART Instance
01030   * @retval Returned value can be one of the following values:
01031   *         @arg @ref LL_USART_STOPBITS_0_5
01032   *         @arg @ref LL_USART_STOPBITS_1
01033   *         @arg @ref LL_USART_STOPBITS_1_5
01034   *         @arg @ref LL_USART_STOPBITS_2
01035   */
01036 __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
01037 {
01038   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
01039 }
01040
01041 /**
01042   * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
01043   * @note   Call of this function is equivalent to following function call sequence :
01044   *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
01045   *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
01046   *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
01047   * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
01048   *         CR1          PCE           LL_USART_ConfigCharacter\n
01049   *         CR1          M0            LL_USART_ConfigCharacter\n
01050   *         CR1          M1            LL_USART_ConfigCharacter\n
01051   *         CR2          STOP          LL_USART_ConfigCharacter
01052   * @param  USARTx USART Instance
01053   * @param  DataWidth This parameter can be one of the following values:
01054   *         @arg @ref LL_USART_DATAWIDTH_7B (*)
01055   *         @arg @ref LL_USART_DATAWIDTH_8B
01056   *         @arg @ref LL_USART_DATAWIDTH_9B
01057   * @param  Parity This parameter can be one of the following values:
01058   *         @arg @ref LL_USART_PARITY_NONE
01059   *         @arg @ref LL_USART_PARITY_EVEN
01060   *         @arg @ref LL_USART_PARITY_ODD
01061   * @param  StopBits This parameter can be one of the following values:
01062   *         @arg @ref LL_USART_STOPBITS_0_5
01063   *         @arg @ref LL_USART_STOPBITS_1
01064   *         @arg @ref LL_USART_STOPBITS_1_5
01065   *         @arg @ref LL_USART_STOPBITS_2
01066   *
01067   *         (*) Values not available on all devices
01068   * @retval None
01069   */
01070 __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
01071                                               uint32_t StopBits)
01072 {
01073   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
01074   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
01075 }
01076
01077 /**
01078   * @brief  Configure TX/RX pins swapping setting.
01079   * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
01080   * @param  USARTx USART Instance
01081   * @param  SwapConfig This parameter can be one of the following values:
01082   *         @arg @ref LL_USART_TXRX_STANDARD
01083   *         @arg @ref LL_USART_TXRX_SWAPPED
01084   * @retval None
01085   */
01086 __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
01087 {
01088   MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
01089 }
01090
01091 /**
01092   * @brief  Retrieve TX/RX pins swapping configuration.
01093   * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
01094   * @param  USARTx USART Instance
01095   * @retval Returned value can be one of the following values:
01096   *         @arg @ref LL_USART_TXRX_STANDARD
01097   *         @arg @ref LL_USART_TXRX_SWAPPED
01098   */
01099 __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
01100 {
01101   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
01102 }
01103
01104 /**
01105   * @brief  Configure RX pin active level logic
01106   * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
01107   * @param  USARTx USART Instance
01108   * @param  PinInvMethod This parameter can be one of the following values:
01109   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
01110   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
01111   * @retval None
01112   */
01113 __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
01114 {
01115   MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
01116 }
01117
01118 /**
01119   * @brief  Retrieve RX pin active level logic configuration
01120   * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
01121   * @param  USARTx USART Instance
01122   * @retval Returned value can be one of the following values:
01123   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
01124   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
01125   */
01126 __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
01127 {
01128   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
01129 }
01130
01131 /**
01132   * @brief  Configure TX pin active level logic
01133   * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
01134   * @param  USARTx USART Instance
01135   * @param  PinInvMethod This parameter can be one of the following values:
01136   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
01137   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
01138   * @retval None
01139   */
01140 __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
01141 {
01142   MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
01143 }
01144
01145 /**
01146   * @brief  Retrieve TX pin active level logic configuration
01147   * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
01148   * @param  USARTx USART Instance
01149   * @retval Returned value can be one of the following values:
01150   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
01151   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
01152   */
01153 __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
01154 {
01155   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
01156 }
01157
01158 /**
01159   * @brief  Configure Binary data logic.
01160   * @note   Allow to define how Logical data from the data register are send/received :
01161   *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
01162   * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
01163   * @param  USARTx USART Instance
01164   * @param  DataLogic This parameter can be one of the following values:
01165   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
01166   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
01167   * @retval None
01168   */
01169 __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
01170 {
01171   MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
01172 }
01173
01174 /**
01175   * @brief  Retrieve Binary data configuration
01176   * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
01177   * @param  USARTx USART Instance
01178   * @retval Returned value can be one of the following values:
01179   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
01180   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
01181   */
01182 __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
01183 {
01184   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
01185 }
01186
01187 /**
01188   * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
01189   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01190   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01191   * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
01192   * @param  USARTx USART Instance
01193   * @param  BitOrder This parameter can be one of the following values:
01194   *         @arg @ref LL_USART_BITORDER_LSBFIRST
01195   *         @arg @ref LL_USART_BITORDER_MSBFIRST
01196   * @retval None
01197   */
01198 __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
01199 {
01200   MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
01201 }
01202
01203 /**
01204   * @brief  Return transfer bit order (either Less or Most Significant Bit First)
01205   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01206   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01207   * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
01208   * @param  USARTx USART Instance
01209   * @retval Returned value can be one of the following values:
01210   *         @arg @ref LL_USART_BITORDER_LSBFIRST
01211   *         @arg @ref LL_USART_BITORDER_MSBFIRST
01212   */
01213 __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
01214 {
01215   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
01216 }
01217
01218 /**
01219   * @brief  Enable Auto Baud-Rate Detection
01220   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01221   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01222   * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
01223   * @param  USARTx USART Instance
01224   * @retval None
01225   */
01226 __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
01227 {
01228   SET_BIT(USARTx->CR2, USART_CR2_ABREN);
01229 }
01230
01231 /**
01232   * @brief  Disable Auto Baud-Rate Detection
01233   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01234   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01235   * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
01236   * @param  USARTx USART Instance
01237   * @retval None
01238   */
01239 __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
01240 {
01241   CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
01242 }
01243
01244 /**
01245   * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
01246   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01247   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01248   * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
01249   * @param  USARTx USART Instance
01250   * @retval State of bit (1 or 0).
01251   */
01252 __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
01253 {
01254   return (READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN));
01255 }
01256
01257 /**
01258   * @brief  Set Auto Baud-Rate mode bits
01259   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01260   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01261   * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
01262   * @param  USARTx USART Instance
01263   * @param  AutoBaudRateMode This parameter can be one of the following values:
01264   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
01265   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
01266   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
01267   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
01268   * @retval None
01269   */
01270 __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
01271 {
01272   MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
01273 }
01274
01275 /**
01276   * @brief  Return Auto Baud-Rate mode
01277   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01278   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01279   * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
01280   * @param  USARTx USART Instance
01281   * @retval Returned value can be one of the following values:
01282   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
01283   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
01284   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
01285   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
01286   */
01287 __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
01288 {
01289   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
01290 }
01291
01292 /**
01293   * @brief  Enable Receiver Timeout
01294   * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
01295   * @param  USARTx USART Instance
01296   * @retval None
01297   */
01298 __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
01299 {
01300   SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
01301 }
01302
01303 /**
01304   * @brief  Disable Receiver Timeout
01305   * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
01306   * @param  USARTx USART Instance
01307   * @retval None
01308   */
01309 __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
01310 {
01311   CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
01312 }
01313
01314 /**
01315   * @brief  Indicate if Receiver Timeout feature is enabled
01316   * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
01317   * @param  USARTx USART Instance
01318   * @retval State of bit (1 or 0).
01319   */
01320 __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
01321 {
01322   return (READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN));
01323 }
01324
01325 /**
01326   * @brief  Set Address of the USART node.
01327   * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
01328   *         for wake up with address mark detection.
01329   * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
01330   *         (b7-b4 should be set to 0)
01331   *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
01332   *         (This is used in multiprocessor communication during Mute mode or Stop mode,
01333   *         for wake up with 7-bit address mark detection.
01334   *         The MSB of the character sent by the transmitter should be equal to 1.
01335   *         It may also be used for character detection during normal reception,
01336   *         Mute mode inactive (for example, end of block detection in ModBus protocol).
01337   *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
01338   *         value and CMF flag is set on match)
01339   * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
01340   *         CR2          ADDM7         LL_USART_ConfigNodeAddress
01341   * @param  USARTx USART Instance
01342   * @param  AddressLen This parameter can be one of the following values:
01343   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
01344   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
01345   * @param  NodeAddress 4 or 7 bit Address of the USART node.
01346   * @retval None
01347   */
01348 __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
01349 {
01350   MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
01351              (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
01352 }
01353
01354 /**
01355   * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
01356   * @note   If 4-bit Address Detection is selected in ADDM7,
01357   *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
01358   *         If 7-bit Address Detection is selected in ADDM7,
01359   *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
01360   * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
01361   * @param  USARTx USART Instance
01362   * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
01363   */
01364 __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
01365 {
01366   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
01367 }
01368
01369 /**
01370   * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
01371   * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
01372   * @param  USARTx USART Instance
01373   * @retval Returned value can be one of the following values:
01374   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
01375   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
01376   */
01377 __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
01378 {
01379   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
01380 }
01381
01382 /**
01383   * @brief  Enable RTS HW Flow Control
01384   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01385   *         Hardware Flow control feature is supported by the USARTx instance.
01386   * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
01387   * @param  USARTx USART Instance
01388   * @retval None
01389   */
01390 __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
01391 {
01392   SET_BIT(USARTx->CR3, USART_CR3_RTSE);
01393 }
01394
01395 /**
01396   * @brief  Disable RTS HW Flow Control
01397   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01398   *         Hardware Flow control feature is supported by the USARTx instance.
01399   * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
01400   * @param  USARTx USART Instance
01401   * @retval None
01402   */
01403 __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
01404 {
01405   CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
01406 }
01407
01408 /**
01409   * @brief  Enable CTS HW Flow Control
01410   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01411   *         Hardware Flow control feature is supported by the USARTx instance.
01412   * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
01413   * @param  USARTx USART Instance
01414   * @retval None
01415   */
01416 __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
01417 {
01418   SET_BIT(USARTx->CR3, USART_CR3_CTSE);
01419 }
01420
01421 /**
01422   * @brief  Disable CTS HW Flow Control
01423   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01424   *         Hardware Flow control feature is supported by the USARTx instance.
01425   * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
01426   * @param  USARTx USART Instance
01427   * @retval None
01428   */
01429 __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
01430 {
01431   CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
01432 }
01433
01434 /**
01435   * @brief  Configure HW Flow Control mode (both CTS and RTS)
01436   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01437   *         Hardware Flow control feature is supported by the USARTx instance.
01438   * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
01439   *         CR3          CTSE          LL_USART_SetHWFlowCtrl
01440   * @param  USARTx USART Instance
01441   * @param  HardwareFlowControl This parameter can be one of the following values:
01442   *         @arg @ref LL_USART_HWCONTROL_NONE
01443   *         @arg @ref LL_USART_HWCONTROL_RTS
01444   *         @arg @ref LL_USART_HWCONTROL_CTS
01445   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
01446   * @retval None
01447   */
01448 __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
01449 {
01450   MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
01451 }
01452
01453 /**
01454   * @brief  Return HW Flow Control configuration (both CTS and RTS)
01455   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01456   *         Hardware Flow control feature is supported by the USARTx instance.
01457   * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
01458   *         CR3          CTSE          LL_USART_GetHWFlowCtrl
01459   * @param  USARTx USART Instance
01460   * @retval Returned value can be one of the following values:
01461   *         @arg @ref LL_USART_HWCONTROL_NONE
01462   *         @arg @ref LL_USART_HWCONTROL_RTS
01463   *         @arg @ref LL_USART_HWCONTROL_CTS
01464   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
01465   */
01466 __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
01467 {
01468   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
01469 }
01470
01471 /**
01472   * @brief  Enable One bit sampling method
01473   * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
01474   * @param  USARTx USART Instance
01475   * @retval None
01476   */
01477 __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
01478 {
01479   SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
01480 }
01481
01482 /**
01483   * @brief  Disable One bit sampling method
01484   * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
01485   * @param  USARTx USART Instance
01486   * @retval None
01487   */
01488 __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
01489 {
01490   CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
01491 }
01492
01493 /**
01494   * @brief  Indicate if One bit sampling method is enabled
01495   * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
01496   * @param  USARTx USART Instance
01497   * @retval State of bit (1 or 0).
01498   */
01499 __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
01500 {
01501   return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
01502 }
01503
01504 /**
01505   * @brief  Enable Overrun detection
01506   * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
01507   * @param  USARTx USART Instance
01508   * @retval None
01509   */
01510 __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
01511 {
01512   CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
01513 }
01514
01515 /**
01516   * @brief  Disable Overrun detection
01517   * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
01518   * @param  USARTx USART Instance
01519   * @retval None
01520   */
01521 __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
01522 {
01523   SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
01524 }
01525
01526 /**
01527   * @brief  Indicate if Overrun detection is enabled
01528   * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
01529   * @param  USARTx USART Instance
01530   * @retval State of bit (1 or 0).
01531   */
01532 __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
01533 {
01534   return (READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);
01535 }
01536
01537 /**
01538   * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01539   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
01540   *         Wake-up from Stop mode feature is supported by the USARTx instance.
01541   * @rmtoll CR3          WUS           LL_USART_SetWKUPType
01542   * @param  USARTx USART Instance
01543   * @param  Type This parameter can be one of the following values:
01544   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
01545   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
01546   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
01547   * @retval None
01548   */
01549 __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
01550 {
01551   MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
01552 }
01553
01554 /**
01555   * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01556   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
01557   *         Wake-up from Stop mode feature is supported by the USARTx instance.
01558   * @rmtoll CR3          WUS           LL_USART_GetWKUPType
01559   * @param  USARTx USART Instance
01560   * @retval Returned value can be one of the following values:
01561   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
01562   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
01563   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
01564   */
01565 __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
01566 {
01567   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
01568 }
01569
01570 /**
01571   * @brief  Configure USART BRR register for achieving expected Baud Rate value.
01572   * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
01573   *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
01574   * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
01575   *         (Baud rate value != 0)
01576   * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
01577   * @rmtoll BRR          BRR           LL_USART_SetBaudRate
01578   * @param  USARTx USART Instance
01579   * @param  PeriphClk Peripheral Clock
01580   * @param  OverSampling This parameter can be one of the following values:
01581   *         @arg @ref LL_USART_OVERSAMPLING_16
01582   *         @arg @ref LL_USART_OVERSAMPLING_8
01583   * @param  BaudRate Baud Rate
01584   * @retval None
01585   */
01586 __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
01587                                           uint32_t BaudRate)
01588 {
01589   register uint32_t usartdiv = 0x0U;
01590   register uint32_t brrtemp = 0x0U;
01591
01592   if (OverSampling == LL_USART_OVERSAMPLING_8)
01593   {
01594     usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
01595     brrtemp = usartdiv & 0xFFF0U;
01596     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
01597     USARTx->BRR = brrtemp;
01598   }
01599   else
01600   {
01601     USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
01602   }
01603 }
01604
01605 /**
01606   * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
01607   *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
01608   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
01609   * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
01610   * @rmtoll BRR          BRR           LL_USART_GetBaudRate
01611   * @param  USARTx USART Instance
01612   * @param  PeriphClk Peripheral Clock
01613   * @param  OverSampling This parameter can be one of the following values:
01614   *         @arg @ref LL_USART_OVERSAMPLING_16
01615   *         @arg @ref LL_USART_OVERSAMPLING_8
01616   * @retval Baud Rate
01617   */
01618 __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
01619 {
01620   register uint32_t usartdiv = 0x0U;
01621   register uint32_t brrresult = 0x0U;
01622
01623   usartdiv = USARTx->BRR;
01624
01625   if (OverSampling == LL_USART_OVERSAMPLING_8)
01626   {
01627     if ((usartdiv & 0xFFF7U) != 0U)
01628     {
01629       usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
01630       brrresult = (PeriphClk * 2U) / usartdiv;
01631     }
01632   }
01633   else
01634   {
01635     if ((usartdiv & 0xFFFFU) != 0U)
01636     {
01637       brrresult = PeriphClk / usartdiv;
01638     }
01639   }
01640   return (brrresult);
01641 }
01642
01643 /**
01644   * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
01645   * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
01646   * @param  USARTx USART Instance
01647   * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
01648   * @retval None
01649   */
01650 __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
01651 {
01652   MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
01653 }
01654
01655 /**
01656   * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
01657   * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
01658   * @param  USARTx USART Instance
01659   * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
01660   */
01661 __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
01662 {
01663   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
01664 }
01665
01666 /**
01667   * @brief  Set Block Length value in reception
01668   * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
01669   * @param  USARTx USART Instance
01670   * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
01671   * @retval None
01672   */
01673 __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
01674 {
01675   MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
01676 }
01677
01678 /**
01679   * @brief  Get Block Length value in reception
01680   * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
01681   * @param  USARTx USART Instance
01682   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
01683   */
01684 __STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
01685 {
01686   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
01687 }
01688
01689 /**
01690   * @}
01691   */
01692
01693 /** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
01694   * @{
01695   */
01696
01697 /**
01698   * @brief  Enable IrDA mode
01699   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01700   *         IrDA feature is supported by the USARTx instance.
01701   * @rmtoll CR3          IREN          LL_USART_EnableIrda
01702   * @param  USARTx USART Instance
01703   * @retval None
01704   */
01705 __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
01706 {
01707   SET_BIT(USARTx->CR3, USART_CR3_IREN);
01708 }
01709
01710 /**
01711   * @brief  Disable IrDA mode
01712   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01713   *         IrDA feature is supported by the USARTx instance.
01714   * @rmtoll CR3          IREN          LL_USART_DisableIrda
01715   * @param  USARTx USART Instance
01716   * @retval None
01717   */
01718 __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
01719 {
01720   CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
01721 }
01722
01723 /**
01724   * @brief  Indicate if IrDA mode is enabled
01725   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01726   *         IrDA feature is supported by the USARTx instance.
01727   * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
01728   * @param  USARTx USART Instance
01729   * @retval State of bit (1 or 0).
01730   */
01731 __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
01732 {
01733   return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
01734 }
01735
01736 /**
01737   * @brief  Configure IrDA Power Mode (Normal or Low Power)
01738   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01739   *         IrDA feature is supported by the USARTx instance.
01740   * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
01741   * @param  USARTx USART Instance
01742   * @param  PowerMode This parameter can be one of the following values:
01743   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
01744   *         @arg @ref LL_USART_IRDA_POWER_LOW
01745   * @retval None
01746   */
01747 __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
01748 {
01749   MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
01750 }
01751
01752 /**
01753   * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
01754   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01755   *         IrDA feature is supported by the USARTx instance.
01756   * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
01757   * @param  USARTx USART Instance
01758   * @retval Returned value can be one of the following values:
01759   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
01760   *         @arg @ref LL_USART_PHASE_2EDGE
01761   */
01762 __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
01763 {
01764   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
01765 }
01766
01767 /**
01768   * @brief  Set Irda prescaler value, used for dividing the USART clock source
01769   *         to achieve the Irda Low Power frequency (8 bits value)
01770   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01771   *         IrDA feature is supported by the USARTx instance.
01772   * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
01773   * @param  USARTx USART Instance
01774   * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
01775   * @retval None
01776   */
01777 __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
01778 {
01779   MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
01780 }
01781
01782 /**
01783   * @brief  Return Irda prescaler value, used for dividing the USART clock source
01784   *         to achieve the Irda Low Power frequency (8 bits value)
01785   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01786   *         IrDA feature is supported by the USARTx instance.
01787   * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
01788   * @param  USARTx USART Instance
01789   * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
01790   */
01791 __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
01792 {
01793   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
01794 }
01795
01796 /**
01797   * @}
01798   */
01799
01800 /** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
01801   * @{
01802   */
01803
01804 /**
01805   * @brief  Enable Smartcard NACK transmission
01806   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01807   *         Smartcard feature is supported by the USARTx instance.
01808   * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
01809   * @param  USARTx USART Instance
01810   * @retval None
01811   */
01812 __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
01813 {
01814   SET_BIT(USARTx->CR3, USART_CR3_NACK);
01815 }
01816
01817 /**
01818   * @brief  Disable Smartcard NACK transmission
01819   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01820   *         Smartcard feature is supported by the USARTx instance.
01821   * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
01822   * @param  USARTx USART Instance
01823   * @retval None
01824   */
01825 __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
01826 {
01827   CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
01828 }
01829
01830 /**
01831   * @brief  Indicate if Smartcard NACK transmission is enabled
01832   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01833   *         Smartcard feature is supported by the USARTx instance.
01834   * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
01835   * @param  USARTx USART Instance
01836   * @retval State of bit (1 or 0).
01837   */
01838 __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
01839 {
01840   return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
01841 }
01842
01843 /**
01844   * @brief  Enable Smartcard mode
01845   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01846   *         Smartcard feature is supported by the USARTx instance.
01847   * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
01848   * @param  USARTx USART Instance
01849   * @retval None
01850   */
01851 __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
01852 {
01853   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
01854 }
01855
01856 /**
01857   * @brief  Disable Smartcard mode
01858   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01859   *         Smartcard feature is supported by the USARTx instance.
01860   * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
01861   * @param  USARTx USART Instance
01862   * @retval None
01863   */
01864 __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
01865 {
01866   CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
01867 }
01868
01869 /**
01870   * @brief  Indicate if Smartcard mode is enabled
01871   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01872   *         Smartcard feature is supported by the USARTx instance.
01873   * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
01874   * @param  USARTx USART Instance
01875   * @retval State of bit (1 or 0).
01876   */
01877 __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
01878 {
01879   return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
01880 }
01881
01882 /**
01883   * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
01884   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01885   *         Smartcard feature is supported by the USARTx instance.
01886   * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
01887   *         In transmission mode, it specifies the number of automatic retransmission retries, before
01888   *         generating a transmission error (FE bit set).
01889   *         In reception mode, it specifies the number or erroneous reception trials, before generating a
01890   *         reception error (RXNE and PE bits set)
01891   * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
01892   * @param  USARTx USART Instance
01893   * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
01894   * @retval None
01895   */
01896 __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
01897 {
01898   MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
01899 }
01900
01901 /**
01902   * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
01903   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01904   *         Smartcard feature is supported by the USARTx instance.
01905   * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
01906   * @param  USARTx USART Instance
01907   * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
01908   */
01909 __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
01910 {
01911   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
01912 }
01913
01914 /**
01915   * @brief  Set Smartcard prescaler value, used for dividing the USART clock
01916   *         source to provide the SMARTCARD Clock (5 bits value)
01917   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01918   *         Smartcard feature is supported by the USARTx instance.
01919   * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
01920   * @param  USARTx USART Instance
01921   * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
01922   * @retval None
01923   */
01924 __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
01925 {
01926   MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
01927 }
01928
01929 /**
01930   * @brief  Return Smartcard prescaler value, used for dividing the USART clock
01931   *         source to provide the SMARTCARD Clock (5 bits value)
01932   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01933   *         Smartcard feature is supported by the USARTx instance.
01934   * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
01935   * @param  USARTx USART Instance
01936   * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
01937   */
01938 __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
01939 {
01940   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
01941 }
01942
01943 /**
01944   * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
01945   *         (GT[7:0] bits : Guard time value)
01946   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01947   *         Smartcard feature is supported by the USARTx instance.
01948   * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
01949   * @param  USARTx USART Instance
01950   * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
01951   * @retval None
01952   */
01953 __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
01954 {
01955   MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos);
01956 }
01957
01958 /**
01959   * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
01960   *         (GT[7:0] bits : Guard time value)
01961   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01962   *         Smartcard feature is supported by the USARTx instance.
01963   * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
01964   * @param  USARTx USART Instance
01965   * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
01966   */
01967 __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
01968 {
01969   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
01970 }
01971
01972 /**
01973   * @}
01974   */
01975
01976 /** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
01977   * @{
01978   */
01979
01980 /**
01981   * @brief  Enable Single Wire Half-Duplex mode
01982   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
01983   *         Half-Duplex mode is supported by the USARTx instance.
01984   * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
01985   * @param  USARTx USART Instance
01986   * @retval None
01987   */
01988 __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
01989 {
01990   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
01991 }
01992
01993 /**
01994   * @brief  Disable Single Wire Half-Duplex mode
01995   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
01996   *         Half-Duplex mode is supported by the USARTx instance.
01997   * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
01998   * @param  USARTx USART Instance
01999   * @retval None
02000   */
02001 __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
02002 {
02003   CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
02004 }
02005
02006 /**
02007   * @brief  Indicate if Single Wire Half-Duplex mode is enabled
02008   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02009   *         Half-Duplex mode is supported by the USARTx instance.
02010   * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
02011   * @param  USARTx USART Instance
02012   * @retval State of bit (1 or 0).
02013   */
02014 __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
02015 {
02016   return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
02017 }
02018
02019 /**
02020   * @}
02021   */
02022
02023 /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
02024   * @{
02025   */
02026
02027 /**
02028   * @brief  Set LIN Break Detection Length
02029   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02030   *         LIN feature is supported by the USARTx instance.
02031   * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
02032   * @param  USARTx USART Instance
02033   * @param  LINBDLength This parameter can be one of the following values:
02034   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
02035   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
02036   * @retval None
02037   */
02038 __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
02039 {
02040   MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
02041 }
02042
02043 /**
02044   * @brief  Return LIN Break Detection Length
02045   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02046   *         LIN feature is supported by the USARTx instance.
02047   * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
02048   * @param  USARTx USART Instance
02049   * @retval Returned value can be one of the following values:
02050   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
02051   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
02052   */
02053 __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
02054 {
02055   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
02056 }
02057
02058 /**
02059   * @brief  Enable LIN mode
02060   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02061   *         LIN feature is supported by the USARTx instance.
02062   * @rmtoll CR2          LINEN         LL_USART_EnableLIN
02063   * @param  USARTx USART Instance
02064   * @retval None
02065   */
02066 __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
02067 {
02068   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
02069 }
02070
02071 /**
02072   * @brief  Disable LIN mode
02073   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02074   *         LIN feature is supported by the USARTx instance.
02075   * @rmtoll CR2          LINEN         LL_USART_DisableLIN
02076   * @param  USARTx USART Instance
02077   * @retval None
02078   */
02079 __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
02080 {
02081   CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
02082 }
02083
02084 /**
02085   * @brief  Indicate if LIN mode is enabled
02086   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02087   *         LIN feature is supported by the USARTx instance.
02088   * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
02089   * @param  USARTx USART Instance
02090   * @retval State of bit (1 or 0).
02091   */
02092 __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
02093 {
02094   return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
02095 }
02096
02097 /**
02098   * @}
02099   */
02100
02101 /** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
02102   * @{
02103   */
02104
02105 /**
02106   * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
02107   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02108   *         Driver Enable feature is supported by the USARTx instance.
02109   * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
02110   * @param  USARTx USART Instance
02111   * @param  Time Value between Min_Data=0 and Max_Data=31
02112   * @retval None
02113   */
02114 __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
02115 {
02116   MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
02117 }
02118
02119 /**
02120   * @brief  Return DEDT (Driver Enable De-Assertion Time)
02121   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02122   *         Driver Enable feature is supported by the USARTx instance.
02123   * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
02124   * @param  USARTx USART Instance
02125   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
02126   */
02127 __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
02128 {
02129   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
02130 }
02131
02132 /**
02133   * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
02134   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02135   *         Driver Enable feature is supported by the USARTx instance.
02136   * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
02137   * @param  USARTx USART Instance
02138   * @param  Time Value between Min_Data=0 and Max_Data=31
02139   * @retval None
02140   */
02141 __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
02142 {
02143   MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
02144 }
02145
02146 /**
02147   * @brief  Return DEAT (Driver Enable Assertion Time)
02148   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02149   *         Driver Enable feature is supported by the USARTx instance.
02150   * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
02151   * @param  USARTx USART Instance
02152   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
02153   */
02154 __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
02155 {
02156   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
02157 }
02158
02159 /**
02160   * @brief  Enable Driver Enable (DE) Mode
02161   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02162   *         Driver Enable feature is supported by the USARTx instance.
02163   * @rmtoll CR3          DEM           LL_USART_EnableDEMode
02164   * @param  USARTx USART Instance
02165   * @retval None
02166   */
02167 __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
02168 {
02169   SET_BIT(USARTx->CR3, USART_CR3_DEM);
02170 }
02171
02172 /**
02173   * @brief  Disable Driver Enable (DE) Mode
02174   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02175   *         Driver Enable feature is supported by the USARTx instance.
02176   * @rmtoll CR3          DEM           LL_USART_DisableDEMode
02177   * @param  USARTx USART Instance
02178   * @retval None
02179   */
02180 __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
02181 {
02182   CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
02183 }
02184
02185 /**
02186   * @brief  Indicate if Driver Enable (DE) Mode is enabled
02187   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02188   *         Driver Enable feature is supported by the USARTx instance.
02189   * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
02190   * @param  USARTx USART Instance
02191   * @retval State of bit (1 or 0).
02192   */
02193 __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
02194 {
02195   return (READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));
02196 }
02197
02198 /**
02199   * @brief  Select Driver Enable Polarity
02200   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02201   *         Driver Enable feature is supported by the USARTx instance.
02202   * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
02203   * @param  USARTx USART Instance
02204   * @param  Polarity This parameter can be one of the following values:
02205   *         @arg @ref LL_USART_DE_POLARITY_HIGH
02206   *         @arg @ref LL_USART_DE_POLARITY_LOW
02207   * @retval None
02208   */
02209 __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
02210 {
02211   MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
02212 }
02213
02214 /**
02215   * @brief  Return Driver Enable Polarity
02216   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02217   *         Driver Enable feature is supported by the USARTx instance.
02218   * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
02219   * @param  USARTx USART Instance
02220   * @retval Returned value can be one of the following values:
02221   *         @arg @ref LL_USART_DE_POLARITY_HIGH
02222   *         @arg @ref LL_USART_DE_POLARITY_LOW
02223   */
02224 __STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
02225 {
02226   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
02227 }
02228
02229 /**
02230   * @}
02231   */
02232
02233 /** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
02234   * @{
02235   */
02236
02237 /**
02238   * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
02239   * @note   In UART mode, the following bits must be kept cleared:
02240   *           - LINEN bit in the USART_CR2 register,
02241   *           - CLKEN bit in the USART_CR2 register,
02242   *           - SCEN bit in the USART_CR3 register,
02243   *           - IREN bit in the USART_CR3 register,
02244   *           - HDSEL bit in the USART_CR3 register.
02245   * @note   Call of this function is equivalent to following function call sequence :
02246   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02247   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02248   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02249   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02250   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02251   * @note   Other remaining configurations items related to Asynchronous Mode
02252   *         (as Baud Rate, Word length, Parity, ...) should be set using
02253   *         dedicated functions
02254   * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
02255   *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
02256   *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
02257   *         CR3          IREN          LL_USART_ConfigAsyncMode\n
02258   *         CR3          HDSEL         LL_USART_ConfigAsyncMode
02259   * @param  USARTx USART Instance
02260   * @retval None
02261   */
02262 __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
02263 {
02264   /* In Asynchronous mode, the following bits must be kept cleared:
02265   - LINEN, CLKEN bits in the USART_CR2 register,
02266   - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
02267   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02268   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
02269 }
02270
02271 /**
02272   * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
02273   * @note   In Synchronous mode, the following bits must be kept cleared:
02274   *           - LINEN bit in the USART_CR2 register,
02275   *           - SCEN bit in the USART_CR3 register,
02276   *           - IREN bit in the USART_CR3 register,
02277   *           - HDSEL bit in the USART_CR3 register.
02278   *         This function also sets the USART in Synchronous mode.
02279   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
02280   *         Synchronous mode is supported by the USARTx instance.
02281   * @note   Call of this function is equivalent to following function call sequence :
02282   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02283   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02284   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02285   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02286   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
02287   * @note   Other remaining configurations items related to Synchronous Mode
02288   *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
02289   *         dedicated functions
02290   * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
02291   *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
02292   *         CR3          SCEN          LL_USART_ConfigSyncMode\n
02293   *         CR3          IREN          LL_USART_ConfigSyncMode\n
02294   *         CR3          HDSEL         LL_USART_ConfigSyncMode
02295   * @param  USARTx USART Instance
02296   * @retval None
02297   */
02298 __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
02299 {
02300   /* In Synchronous mode, the following bits must be kept cleared:
02301   - LINEN bit in the USART_CR2 register,
02302   - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
02303   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
02304   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
02305   /* set the UART/USART in Synchronous mode */
02306   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
02307 }
02308
02309 /**
02310   * @brief  Perform basic configuration of USART for enabling use in LIN Mode
02311   * @note   In LIN mode, the following bits must be kept cleared:
02312   *           - STOP and CLKEN bits in the USART_CR2 register,
02313   *           - SCEN bit in the USART_CR3 register,
02314   *           - IREN bit in the USART_CR3 register,
02315   *           - HDSEL bit in the USART_CR3 register.
02316   *         This function also set the UART/USART in LIN mode.
02317   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02318   *         LIN feature is supported by the USARTx instance.
02319   * @note   Call of this function is equivalent to following function call sequence :
02320   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02321   *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02322   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02323   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02324   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02325   *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
02326   * @note   Other remaining configurations items related to LIN Mode
02327   *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
02328   *         dedicated functions
02329   * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
02330   *         CR2          STOP          LL_USART_ConfigLINMode\n
02331   *         CR2          LINEN         LL_USART_ConfigLINMode\n
02332   *         CR3          IREN          LL_USART_ConfigLINMode\n
02333   *         CR3          SCEN          LL_USART_ConfigLINMode\n
02334   *         CR3          HDSEL         LL_USART_ConfigLINMode
02335   * @param  USARTx USART Instance
02336   * @retval None
02337   */
02338 __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
02339 {
02340   /* In LIN mode, the following bits must be kept cleared:
02341   - STOP and CLKEN bits in the USART_CR2 register,
02342   - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
02343   CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
02344   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
02345   /* Set the UART/USART in LIN mode */
02346   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
02347 }
02348
02349 /**
02350   * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
02351   * @note   In Half Duplex mode, the following bits must be kept cleared:
02352   *           - LINEN bit in the USART_CR2 register,
02353   *           - CLKEN bit in the USART_CR2 register,
02354   *           - SCEN bit in the USART_CR3 register,
02355   *           - IREN bit in the USART_CR3 register,
02356   *         This function also sets the UART/USART in Half Duplex mode.
02357   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02358   *         Half-Duplex mode is supported by the USARTx instance.
02359   * @note   Call of this function is equivalent to following function call sequence :
02360   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02361   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02362   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02363   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02364   *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
02365   * @note   Other remaining configurations items related to Half Duplex Mode
02366   *         (as Baud Rate, Word length, Parity, ...) should be set using
02367   *         dedicated functions
02368   * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
02369   *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
02370   *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
02371   *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
02372   *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
02373   * @param  USARTx USART Instance
02374   * @retval None
02375   */
02376 __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
02377 {
02378   /* In Half Duplex mode, the following bits must be kept cleared:
02379   - LINEN and CLKEN bits in the USART_CR2 register,
02380   - SCEN and IREN bits in the USART_CR3 register.*/
02381   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02382   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
02383   /* set the UART/USART in Half Duplex mode */
02384   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
02385 }
02386
02387 /**
02388   * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
02389   * @note   In Smartcard mode, the following bits must be kept cleared:
02390   *           - LINEN bit in the USART_CR2 register,
02391   *           - IREN bit in the USART_CR3 register,
02392   *           - HDSEL bit in the USART_CR3 register.
02393   *         This function also configures Stop bits to 1.5 bits and
02394   *         sets the USART in Smartcard mode (SCEN bit).
02395   *         Clock Output is also enabled (CLKEN).
02396   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02397   *         Smartcard feature is supported by the USARTx instance.
02398   * @note   Call of this function is equivalent to following function call sequence :
02399   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02400   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02401   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02402   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02403   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
02404   *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
02405   * @note   Other remaining configurations items related to Smartcard Mode
02406   *         (as Baud Rate, Word length, Parity, ...) should be set using
02407   *         dedicated functions
02408   * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
02409   *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
02410   *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
02411   *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
02412   *         CR3          SCEN          LL_USART_ConfigSmartcardMode
02413   * @param  USARTx USART Instance
02414   * @retval None
02415   */
02416 __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
02417 {
02418   /* In Smartcard mode, the following bits must be kept cleared:
02419   - LINEN bit in the USART_CR2 register,
02420   - IREN and HDSEL bits in the USART_CR3 register.*/
02421   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
02422   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
02423   /* Configure Stop bits to 1.5 bits */
02424   /* Synchronous mode is activated by default */
02425   SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
02426   /* set the UART/USART in Smartcard mode */
02427   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
02428 }
02429
02430 /**
02431   * @brief  Perform basic configuration of USART for enabling use in Irda Mode
02432   * @note   In IRDA mode, the following bits must be kept cleared:
02433   *           - LINEN bit in the USART_CR2 register,
02434   *           - STOP and CLKEN bits in the USART_CR2 register,
02435   *           - SCEN bit in the USART_CR3 register,
02436   *           - HDSEL bit in the USART_CR3 register.
02437   *         This function also sets the UART/USART in IRDA mode (IREN bit).
02438   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02439   *         IrDA feature is supported by the USARTx instance.
02440   * @note   Call of this function is equivalent to following function call sequence :
02441   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02442   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02443   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02444   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02445   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02446   *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
02447   * @note   Other remaining configurations items related to Irda Mode
02448   *         (as Baud Rate, Word length, Power mode, ...) should be set using
02449   *         dedicated functions
02450   * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
02451   *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
02452   *         CR2          STOP          LL_USART_ConfigIrdaMode\n
02453   *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
02454   *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
02455   *         CR3          IREN          LL_USART_ConfigIrdaMode
02456   * @param  USARTx USART Instance
02457   * @retval None
02458   */
02459 __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
02460 {
02461   /* In IRDA mode, the following bits must be kept cleared:
02462   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
02463   - SCEN and HDSEL bits in the USART_CR3 register.*/
02464   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
02465   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
02466   /* set the UART/USART in IRDA mode */
02467   SET_BIT(USARTx->CR3, USART_CR3_IREN);
02468 }
02469
02470 /**
02471   * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
02472   *         (several USARTs connected in a network, one of the USARTs can be the master,
02473   *         its TX output connected to the RX inputs of the other slaves USARTs).
02474   * @note   In MultiProcessor mode, the following bits must be kept cleared:
02475   *           - LINEN bit in the USART_CR2 register,
02476   *           - CLKEN bit in the USART_CR2 register,
02477   *           - SCEN bit in the USART_CR3 register,
02478   *           - IREN bit in the USART_CR3 register,
02479   *           - HDSEL bit in the USART_CR3 register.
02480   * @note   Call of this function is equivalent to following function call sequence :
02481   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02482   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02483   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02484   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02485   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02486   * @note   Other remaining configurations items related to Multi processor Mode
02487   *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
02488   *         dedicated functions
02489   * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
02490   *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
02491   *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
02492   *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
02493   *         CR3          IREN          LL_USART_ConfigMultiProcessMode
02494   * @param  USARTx USART Instance
02495   * @retval None
02496   */
02497 __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
02498 {
02499   /* In Multi Processor mode, the following bits must be kept cleared:
02500   - LINEN and CLKEN bits in the USART_CR2 register,
02501   - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
02502   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02503   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
02504 }
02505
02506 /**
02507   * @}
02508   */
02509
02510 /** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
02511   * @{
02512   */
02513
02514 /**
02515   * @brief  Check if the USART Parity Error Flag is set or not
02516   * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
02517   * @param  USARTx USART Instance
02518   * @retval State of bit (1 or 0).
02519   */
02520 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
02521 {
02522   return (READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));
02523 }
02524
02525 /**
02526   * @brief  Check if the USART Framing Error Flag is set or not
02527   * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
02528   * @param  USARTx USART Instance
02529   * @retval State of bit (1 or 0).
02530   */
02531 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
02532 {
02533   return (READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));
02534 }
02535
02536 /**
02537   * @brief  Check if the USART Noise error detected Flag is set or not
02538   * @rmtoll ISR          NF            LL_USART_IsActiveFlag_NE
02539   * @param  USARTx USART Instance
02540   * @retval State of bit (1 or 0).
02541   */
02542 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
02543 {
02544   return (READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));
02545 }
02546
02547 /**
02548   * @brief  Check if the USART OverRun Error Flag is set or not
02549   * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
02550   * @param  USARTx USART Instance
02551   * @retval State of bit (1 or 0).
02552   */
02553 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
02554 {
02555   return (READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));
02556 }
02557
02558 /**
02559   * @brief  Check if the USART IDLE line detected Flag is set or not
02560   * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
02561   * @param  USARTx USART Instance
02562   * @retval State of bit (1 or 0).
02563   */
02564 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
02565 {
02566   return (READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));
02567 }
02568
02569 /**
02570   * @brief  Check if the USART Read Data Register Not Empty Flag is set or not
02571   * @rmtoll ISR          RXNE          LL_USART_IsActiveFlag_RXNE
02572   * @param  USARTx USART Instance
02573   * @retval State of bit (1 or 0).
02574   */
02575 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
02576 {
02577   return (READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));
02578 }
02579
02580 /**
02581   * @brief  Check if the USART Transmission Complete Flag is set or not
02582   * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
02583   * @param  USARTx USART Instance
02584   * @retval State of bit (1 or 0).
02585   */
02586 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
02587 {
02588   return (READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));
02589 }
02590
02591 /**
02592   * @brief  Check if the USART Transmit Data Register Empty Flag is set or not
02593   * @rmtoll ISR          TXE           LL_USART_IsActiveFlag_TXE
02594   * @param  USARTx USART Instance
02595   * @retval State of bit (1 or 0).
02596   */
02597 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
02598 {
02599   return (READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));
02600 }
02601
02602 /**
02603   * @brief  Check if the USART LIN Break Detection Flag is set or not
02604   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02605   *         LIN feature is supported by the USARTx instance.
02606   * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
02607   * @param  USARTx USART Instance
02608   * @retval State of bit (1 or 0).
02609   */
02610 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
02611 {
02612   return (READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF));
02613 }
02614
02615 /**
02616   * @brief  Check if the USART CTS interrupt Flag is set or not
02617   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
02618   *         Hardware Flow control feature is supported by the USARTx instance.
02619   * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
02620   * @param  USARTx USART Instance
02621   * @retval State of bit (1 or 0).
02622   */
02623 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
02624 {
02625   return (READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));
02626 }
02627
02628 /**
02629   * @brief  Check if the USART CTS Flag is set or not
02630   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
02631   *         Hardware Flow control feature is supported by the USARTx instance.
02632   * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
02633   * @param  USARTx USART Instance
02634   * @retval State of bit (1 or 0).
02635   */
02636 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
02637 {
02638   return (READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));
02639 }
02640
02641 /**
02642   * @brief  Check if the USART Receiver Time Out Flag is set or not
02643   * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
02644   * @param  USARTx USART Instance
02645   * @retval State of bit (1 or 0).
02646   */
02647 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
02648 {
02649   return (READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF));
02650 }
02651
02652 /**
02653   * @brief  Check if the USART End Of Block Flag is set or not
02654   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02655   *         Smartcard feature is supported by the USARTx instance.
02656   * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
02657   * @param  USARTx USART Instance
02658   * @retval State of bit (1 or 0).
02659   */
02660 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
02661 {
02662   return (READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF));
02663 }
02664
02665 /**
02666   * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
02667   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
02668   *         Auto Baud Rate detection feature is supported by the USARTx instance.
02669   * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
02670   * @param  USARTx USART Instance
02671   * @retval State of bit (1 or 0).
02672   */
02673 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
02674 {
02675   return (READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE));
02676 }
02677
02678 /**
02679   * @brief  Check if the USART Auto-Baud Rate Flag is set or not
02680   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
02681   *         Auto Baud Rate detection feature is supported by the USARTx instance.
02682   * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
02683   * @param  USARTx USART Instance
02684   * @retval State of bit (1 or 0).
02685   */
02686 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
02687 {
02688   return (READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF));
02689 }
02690
02691 /**
02692   * @brief  Check if the USART Busy Flag is set or not
02693   * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
02694   * @param  USARTx USART Instance
02695   * @retval State of bit (1 or 0).
02696   */
02697 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
02698 {
02699   return (READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));
02700 }
02701
02702 /**
02703   * @brief  Check if the USART Character Match Flag is set or not
02704   * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
02705   * @param  USARTx USART Instance
02706   * @retval State of bit (1 or 0).
02707   */
02708 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
02709 {
02710   return (READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));
02711 }
02712
02713 /**
02714   * @brief  Check if the USART Send Break Flag is set or not
02715   * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
02716   * @param  USARTx USART Instance
02717   * @retval State of bit (1 or 0).
02718   */
02719 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
02720 {
02721   return (READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));
02722 }
02723
02724 /**
02725   * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
02726   * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
02727   * @param  USARTx USART Instance
02728   * @retval State of bit (1 or 0).
02729   */
02730 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
02731 {
02732   return (READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));
02733 }
02734
02735 /**
02736   * @brief  Check if the USART Wake Up from stop mode Flag is set or not
02737   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
02738   *         Wake-up from Stop mode feature is supported by the USARTx instance.
02739   * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
02740   * @param  USARTx USART Instance
02741   * @retval State of bit (1 or 0).
02742   */
02743 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
02744 {
02745   return (READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));
02746 }
02747
02748 /**
02749   * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
02750   * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
02751   * @param  USARTx USART Instance
02752   * @retval State of bit (1 or 0).
02753   */
02754 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
02755 {
02756   return (READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));
02757 }
02758
02759 /**
02760   * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
02761   * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
02762   * @param  USARTx USART Instance
02763   * @retval State of bit (1 or 0).
02764   */
02765 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
02766 {
02767   return (READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));
02768 }
02769
02770
02771 /**
02772   * @brief  Clear Parity Error Flag
02773   * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
02774   * @param  USARTx USART Instance
02775   * @retval None
02776   */
02777 __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
02778 {
02779   WRITE_REG(USARTx->ICR, USART_ICR_PECF);
02780 }
02781
02782 /**
02783   * @brief  Clear Framing Error Flag
02784   * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
02785   * @param  USARTx USART Instance
02786   * @retval None
02787   */
02788 __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
02789 {
02790   WRITE_REG(USARTx->ICR, USART_ICR_FECF);
02791 }
02792
02793 /**
02794   * @brief  Clear Noise detected Flag
02795   * @rmtoll ICR          NCF           LL_USART_ClearFlag_NE
02796   * @param  USARTx USART Instance
02797   * @retval None
02798   */
02799 __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
02800 {
02801   WRITE_REG(USARTx->ICR, USART_ICR_NCF);
02802 }
02803
02804 /**
02805   * @brief  Clear OverRun Error Flag
02806   * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
02807   * @param  USARTx USART Instance
02808   * @retval None
02809   */
02810 __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
02811 {
02812   WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
02813 }
02814
02815 /**
02816   * @brief  Clear IDLE line detected Flag
02817   * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
02818   * @param  USARTx USART Instance
02819   * @retval None
02820   */
02821 __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
02822 {
02823   WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
02824 }
02825
02826 /**
02827   * @brief  Clear Transmission Complete Flag
02828   * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
02829   * @param  USARTx USART Instance
02830   * @retval None
02831   */
02832 __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
02833 {
02834   WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
02835 }
02836
02837
02838 /**
02839   * @brief  Clear LIN Break Detection Flag
02840   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02841   *         LIN feature is supported by the USARTx instance.
02842   * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
02843   * @param  USARTx USART Instance
02844   * @retval None
02845   */
02846 __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
02847 {
02848   WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
02849 }
02850
02851 /**
02852   * @brief  Clear CTS Interrupt Flag
02853   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
02854   *         Hardware Flow control feature is supported by the USARTx instance.
02855   * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
02856   * @param  USARTx USART Instance
02857   * @retval None
02858   */
02859 __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
02860 {
02861   WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
02862 }
02863
02864 /**
02865   * @brief  Clear Receiver Time Out Flag
02866   * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
02867   * @param  USARTx USART Instance
02868   * @retval None
02869   */
02870 __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
02871 {
02872   WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
02873 }
02874
02875 /**
02876   * @brief  Clear End Of Block Flag
02877   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02878   *         Smartcard feature is supported by the USARTx instance.
02879   * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
02880   * @param  USARTx USART Instance
02881   * @retval None
02882   */
02883 __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
02884 {
02885   WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
02886 }
02887
02888 /**
02889   * @brief  Clear Character Match Flag
02890   * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
02891   * @param  USARTx USART Instance
02892   * @retval None
02893   */
02894 __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
02895 {
02896   WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
02897 }
02898
02899 /**
02900   * @brief  Clear Wake Up from stop mode Flag
02901   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
02902   *         Wake-up from Stop mode feature is supported by the USARTx instance.
02903   * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
02904   * @param  USARTx USART Instance
02905   * @retval None
02906   */
02907 __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
02908 {
02909   WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
02910 }
02911
02912 /**
02913   * @}
02914   */
02915
02916 /** @defgroup USART_LL_EF_IT_Management IT_Management
02917   * @{
02918   */
02919
02920 /**
02921   * @brief  Enable IDLE Interrupt
02922   * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
02923   * @param  USARTx USART Instance
02924   * @retval None
02925   */
02926 __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
02927 {
02928   SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
02929 }
02930
02931 /**
02932   * @brief  Enable RX Not Empty Interrupt
02933   * @rmtoll CR1          RXNEIE        LL_USART_EnableIT_RXNE
02934   * @param  USARTx USART Instance
02935   * @retval None
02936   */
02937 __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
02938 {
02939   SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
02940 }
02941
02942 /**
02943   * @brief  Enable Transmission Complete Interrupt
02944   * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
02945   * @param  USARTx USART Instance
02946   * @retval None
02947   */
02948 __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
02949 {
02950   SET_BIT(USARTx->CR1, USART_CR1_TCIE);
02951 }
02952
02953 /**
02954   * @brief  Enable TX Empty Interrupt
02955   * @rmtoll CR1          TXEIE         LL_USART_EnableIT_TXE
02956   * @param  USARTx USART Instance
02957   * @retval None
02958   */
02959 __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
02960 {
02961   SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
02962 }
02963
02964 /**
02965   * @brief  Enable Parity Error Interrupt
02966   * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
02967   * @param  USARTx USART Instance
02968   * @retval None
02969   */
02970 __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
02971 {
02972   SET_BIT(USARTx->CR1, USART_CR1_PEIE);
02973 }
02974
02975 /**
02976   * @brief  Enable Character Match Interrupt
02977   * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
02978   * @param  USARTx USART Instance
02979   * @retval None
02980   */
02981 __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
02982 {
02983   SET_BIT(USARTx->CR1, USART_CR1_CMIE);
02984 }
02985
02986 /**
02987   * @brief  Enable Receiver Timeout Interrupt
02988   * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
02989   * @param  USARTx USART Instance
02990   * @retval None
02991   */
02992 __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
02993 {
02994   SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
02995 }
02996
02997 /**
02998   * @brief  Enable End Of Block Interrupt
02999   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03000   *         Smartcard feature is supported by the USARTx instance.
03001   * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
03002   * @param  USARTx USART Instance
03003   * @retval None
03004   */
03005 __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
03006 {
03007   SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
03008 }
03009
03010 /**
03011   * @brief  Enable LIN Break Detection Interrupt
03012   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03013   *         LIN feature is supported by the USARTx instance.
03014   * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
03015   * @param  USARTx USART Instance
03016   * @retval None
03017   */
03018 __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
03019 {
03020   SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
03021 }
03022
03023 /**
03024   * @brief  Enable Error Interrupt
03025   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
03026   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
03027   *           0: Interrupt is inhibited
03028   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
03029   * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
03030   * @param  USARTx USART Instance
03031   * @retval None
03032   */
03033 __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
03034 {
03035   SET_BIT(USARTx->CR3, USART_CR3_EIE);
03036 }
03037
03038 /**
03039   * @brief  Enable CTS Interrupt
03040   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03041   *         Hardware Flow control feature is supported by the USARTx instance.
03042   * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
03043   * @param  USARTx USART Instance
03044   * @retval None
03045   */
03046 __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
03047 {
03048   SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
03049 }
03050
03051 /**
03052   * @brief  Enable Wake Up from Stop Mode Interrupt
03053   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03054   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03055   * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
03056   * @param  USARTx USART Instance
03057   * @retval None
03058   */
03059 __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
03060 {
03061   SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
03062 }
03063
03064
03065 /**
03066   * @brief  Disable IDLE Interrupt
03067   * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
03068   * @param  USARTx USART Instance
03069   * @retval None
03070   */
03071 __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
03072 {
03073   CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
03074 }
03075
03076 /**
03077   * @brief  Disable RX Not Empty Interrupt
03078   * @rmtoll CR1          RXNEIE        LL_USART_DisableIT_RXNE
03079   * @param  USARTx USART Instance
03080   * @retval None
03081   */
03082 __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
03083 {
03084   CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
03085 }
03086
03087 /**
03088   * @brief  Disable Transmission Complete Interrupt
03089   * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
03090   * @param  USARTx USART Instance
03091   * @retval None
03092   */
03093 __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
03094 {
03095   CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
03096 }
03097
03098 /**
03099   * @brief  Disable TX Empty Interrupt
03100   * @rmtoll CR1          TXEIE         LL_USART_DisableIT_TXE
03101   * @param  USARTx USART Instance
03102   * @retval None
03103   */
03104 __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
03105 {
03106   CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
03107 }
03108
03109 /**
03110   * @brief  Disable Parity Error Interrupt
03111   * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
03112   * @param  USARTx USART Instance
03113   * @retval None
03114   */
03115 __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
03116 {
03117   CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
03118 }
03119
03120 /**
03121   * @brief  Disable Character Match Interrupt
03122   * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
03123   * @param  USARTx USART Instance
03124   * @retval None
03125   */
03126 __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
03127 {
03128   CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
03129 }
03130
03131 /**
03132   * @brief  Disable Receiver Timeout Interrupt
03133   * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
03134   * @param  USARTx USART Instance
03135   * @retval None
03136   */
03137 __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
03138 {
03139   CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
03140 }
03141
03142 /**
03143   * @brief  Disable End Of Block Interrupt
03144   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03145   *         Smartcard feature is supported by the USARTx instance.
03146   * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
03147   * @param  USARTx USART Instance
03148   * @retval None
03149   */
03150 __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
03151 {
03152   CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
03153 }
03154
03155 /**
03156   * @brief  Disable LIN Break Detection Interrupt
03157   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03158   *         LIN feature is supported by the USARTx instance.
03159   * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
03160   * @param  USARTx USART Instance
03161   * @retval None
03162   */
03163 __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
03164 {
03165   CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
03166 }
03167
03168 /**
03169   * @brief  Disable Error Interrupt
03170   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
03171   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
03172   *           0: Interrupt is inhibited
03173   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
03174   * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
03175   * @param  USARTx USART Instance
03176   * @retval None
03177   */
03178 __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
03179 {
03180   CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
03181 }
03182
03183 /**
03184   * @brief  Disable CTS Interrupt
03185   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03186   *         Hardware Flow control feature is supported by the USARTx instance.
03187   * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
03188   * @param  USARTx USART Instance
03189   * @retval None
03190   */
03191 __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
03192 {
03193   CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
03194 }
03195
03196 /**
03197   * @brief  Disable Wake Up from Stop Mode Interrupt
03198   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03199   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03200   * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
03201   * @param  USARTx USART Instance
03202   * @retval None
03203   */
03204 __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
03205 {
03206   CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
03207 }
03208
03209
03210 /**
03211   * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
03212   * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
03213   * @param  USARTx USART Instance
03214   * @retval State of bit (1 or 0).
03215   */
03216 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
03217 {
03218   return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
03219 }
03220
03221 /**
03222   * @brief  Check if the USART RX Not Empty Interrupt is enabled or disabled.
03223   * @rmtoll CR1          RXNEIE        LL_USART_IsEnabledIT_RXNE
03224   * @param  USARTx USART Instance
03225   * @retval State of bit (1 or 0).
03226   */
03227 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
03228 {
03229   return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
03230 }
03231
03232 /**
03233   * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
03234   * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
03235   * @param  USARTx USART Instance
03236   * @retval State of bit (1 or 0).
03237   */
03238 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
03239 {
03240   return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
03241 }
03242
03243 /**
03244   * @brief  Check if the USART TX Empty Interrupt is enabled or disabled.
03245   * @rmtoll CR1          TXEIE         LL_USART_IsEnabledIT_TXE
03246   * @param  USARTx USART Instance
03247   * @retval State of bit (1 or 0).
03248   */
03249 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
03250 {
03251   return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
03252 }
03253
03254 /**
03255   * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
03256   * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
03257   * @param  USARTx USART Instance
03258   * @retval State of bit (1 or 0).
03259   */
03260 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
03261 {
03262   return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
03263 }
03264
03265 /**
03266   * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
03267   * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
03268   * @param  USARTx USART Instance
03269   * @retval State of bit (1 or 0).
03270   */
03271 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
03272 {
03273   return (READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
03274 }
03275
03276 /**
03277   * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
03278   * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
03279   * @param  USARTx USART Instance
03280   * @retval State of bit (1 or 0).
03281   */
03282 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
03283 {
03284   return (READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE));
03285 }
03286
03287 /**
03288   * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
03289   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03290   *         Smartcard feature is supported by the USARTx instance.
03291   * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
03292   * @param  USARTx USART Instance
03293   * @retval State of bit (1 or 0).
03294   */
03295 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
03296 {
03297   return (READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE));
03298 }
03299
03300 /**
03301   * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
03302   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03303   *         LIN feature is supported by the USARTx instance.
03304   * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
03305   * @param  USARTx USART Instance
03306   * @retval State of bit (1 or 0).
03307   */
03308 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
03309 {
03310   return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
03311 }
03312
03313 /**
03314   * @brief  Check if the USART Error Interrupt is enabled or disabled.
03315   * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
03316   * @param  USARTx USART Instance
03317   * @retval State of bit (1 or 0).
03318   */
03319 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
03320 {
03321   return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
03322 }
03323
03324 /**
03325   * @brief  Check if the USART CTS Interrupt is enabled or disabled.
03326   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03327   *         Hardware Flow control feature is supported by the USARTx instance.
03328   * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
03329   * @param  USARTx USART Instance
03330   * @retval State of bit (1 or 0).
03331   */
03332 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
03333 {
03334   return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
03335 }
03336
03337 /**
03338   * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
03339   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03340   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03341   * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
03342   * @param  USARTx USART Instance
03343   * @retval State of bit (1 or 0).
03344   */
03345 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
03346 {
03347   return (READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));
03348 }
03349
03350
03351 /**
03352   * @}
03353   */
03354
03355 /** @defgroup USART_LL_EF_DMA_Management DMA_Management
03356   * @{
03357   */
03358
03359 /**
03360   * @brief  Enable DMA Mode for reception
03361   * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
03362   * @param  USARTx USART Instance
03363   * @retval None
03364   */
03365 __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
03366 {
03367   SET_BIT(USARTx->CR3, USART_CR3_DMAR);
03368 }
03369
03370 /**
03371   * @brief  Disable DMA Mode for reception
03372   * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
03373   * @param  USARTx USART Instance
03374   * @retval None
03375   */
03376 __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
03377 {
03378   CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
03379 }
03380
03381 /**
03382   * @brief  Check if DMA Mode is enabled for reception
03383   * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
03384   * @param  USARTx USART Instance
03385   * @retval State of bit (1 or 0).
03386   */
03387 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
03388 {
03389   return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
03390 }
03391
03392 /**
03393   * @brief  Enable DMA Mode for transmission
03394   * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
03395   * @param  USARTx USART Instance
03396   * @retval None
03397   */
03398 __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
03399 {
03400   SET_BIT(USARTx->CR3, USART_CR3_DMAT);
03401 }
03402
03403 /**
03404   * @brief  Disable DMA Mode for transmission
03405   * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
03406   * @param  USARTx USART Instance
03407   * @retval None
03408   */
03409 __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
03410 {
03411   CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
03412 }
03413
03414 /**
03415   * @brief  Check if DMA Mode is enabled for transmission
03416   * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
03417   * @param  USARTx USART Instance
03418   * @retval State of bit (1 or 0).
03419   */
03420 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
03421 {
03422   return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
03423 }
03424
03425 /**
03426   * @brief  Enable DMA Disabling on Reception Error
03427   * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
03428   * @param  USARTx USART Instance
03429   * @retval None
03430   */
03431 __STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
03432 {
03433   SET_BIT(USARTx->CR3, USART_CR3_DDRE);
03434 }
03435
03436 /**
03437   * @brief  Disable DMA Disabling on Reception Error
03438   * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
03439   * @param  USARTx USART Instance
03440   * @retval None
03441   */
03442 __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
03443 {
03444   CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
03445 }
03446
03447 /**
03448   * @brief  Indicate if DMA Disabling on Reception Error is disabled
03449   * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
03450   * @param  USARTx USART Instance
03451   * @retval State of bit (1 or 0).
03452   */
03453 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
03454 {
03455   return (READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));
03456 }
03457
03458 /**
03459   * @brief  Get the data register address used for DMA transfer
03460   * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
03461   * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
03462   * @param  USARTx USART Instance
03463   * @param  Direction This parameter can be one of the following values:
03464   *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
03465   *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
03466   * @retval Address of data register
03467   */
03468 __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
03469 {
03470   register uint32_t data_reg_addr = 0U;
03471
03472   if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
03473   {
03474     /* return address of TDR register */
03475     data_reg_addr = (uint32_t) &(USARTx->TDR);
03476   }
03477   else
03478   {
03479     /* return address of RDR register */
03480     data_reg_addr = (uint32_t) &(USARTx->RDR);
03481   }
03482
03483   return data_reg_addr;
03484 }
03485
03486 /**
03487   * @}
03488   */
03489
03490 /** @defgroup USART_LL_EF_Data_Management Data_Management
03491   * @{
03492   */
03493
03494 /**
03495   * @brief  Read Receiver Data register (Receive Data value, 8 bits)
03496   * @rmtoll RDR          RDR           LL_USART_ReceiveData8
03497   * @param  USARTx USART Instance
03498   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
03499   */
03500 __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
03501 {
03502   return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
03503 }
03504
03505 /**
03506   * @brief  Read Receiver Data register (Receive Data value, 9 bits)
03507   * @rmtoll RDR          RDR           LL_USART_ReceiveData9
03508   * @param  USARTx USART Instance
03509   * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
03510   */
03511 __STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
03512 {
03513   return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
03514 }
03515
03516 /**
03517   * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
03518   * @rmtoll TDR          TDR           LL_USART_TransmitData8
03519   * @param  USARTx USART Instance
03520   * @param  Value between Min_Data=0x00 and Max_Data=0xFF
03521   * @retval None
03522   */
03523 __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
03524 {
03525   USARTx->TDR = Value;
03526 }
03527
03528 /**
03529   * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
03530   * @rmtoll TDR          TDR           LL_USART_TransmitData9
03531   * @param  USARTx USART Instance
03532   * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
03533   * @retval None
03534   */
03535 __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
03536 {
03537   USARTx->TDR = Value & 0x1FFU;
03538 }
03539
03540 /**
03541   * @}
03542   */
03543
03544 /** @defgroup USART_LL_EF_Execution Execution
03545   * @{
03546   */
03547
03548 /**
03549   * @brief  Request an Automatic Baud Rate measurement on next received data frame
03550   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
03551   *         Auto Baud Rate detection feature is supported by the USARTx instance.
03552   * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
03553   * @param  USARTx USART Instance
03554   * @retval None
03555   */
03556 __STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
03557 {
03558   SET_BIT(USARTx->RQR, USART_RQR_ABRRQ);
03559 }
03560
03561 /**
03562   * @brief  Request Break sending
03563   * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
03564   * @param  USARTx USART Instance
03565   * @retval None
03566   */
03567 __STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
03568 {
03569   SET_BIT(USARTx->RQR, USART_RQR_SBKRQ);
03570 }
03571
03572 /**
03573   * @brief  Put USART in mute mode and set the RWU flag
03574   * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
03575   * @param  USARTx USART Instance
03576   * @retval None
03577   */
03578 __STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
03579 {
03580   SET_BIT(USARTx->RQR, USART_RQR_MMRQ);
03581 }
03582
03583 /**
03584   * @brief  Request a Receive Data flush
03585   * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
03586   * @param  USARTx USART Instance
03587   * @retval None
03588   */
03589 __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
03590 {
03591   SET_BIT(USARTx->RQR, USART_RQR_RXFRQ);
03592 }
03593
03594 /**
03595   * @brief  Request a Transmit data flush
03596   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03597   *         Smartcard feature is supported by the USARTx instance.
03598   * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
03599   * @param  USARTx USART Instance
03600   * @retval None
03601   */
03602 __STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
03603 {
03604   SET_BIT(USARTx->RQR, USART_RQR_TXFRQ);
03605 }
03606
03607 /**
03608   * @}
03609   */
03610
03611 #if defined(USE_FULL_LL_DRIVER)
03612 /** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
03613   * @{
03614   */
03615 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
03616 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
03617 void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
03618 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
03619 void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
03620 /**
03621   * @}
03622   */
03623 #endif /* USE_FULL_LL_DRIVER */
03624
03625 /**
03626   * @}
03627   */
03628
03629 /**
03630   * @}
03631   */
03632
03633 #endif /* USART1 || USART2|| USART3 || UART4 || UART5 */
03634
03635 /**
03636   * @}
03637   */
03638
03639 #ifdef __cplusplus
03640 }
03641 #endif
03642
03643 #endif /* __STM32F3xx_LL_USART_H */
03644
03645 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_utils.c Source File

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stm32f3xx_ll_utils.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_utils.c
00004   * @author  MCD Application Team
00005   * @brief   UTILS LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 /* Includes ------------------------------------------------------------------*/
00036 #include "stm32f3xx_ll_rcc.h"
00037 #include "stm32f3xx_ll_utils.h"
00038 #include "stm32f3xx_ll_system.h"
00039 #include "stm32f3xx_ll_pwr.h"
00040 #ifdef  USE_FULL_ASSERT
00041 #include "stm32_assert.h"
00042 #else
00043 #define assert_param(expr) ((void)0U)
00044 #endif
00045
00046 /** @addtogroup STM32F3xx_LL_Driver
00047   * @{
00048   */
00049
00050 /** @addtogroup UTILS_LL
00051   * @{
00052   */
00053
00054 /* Private types -------------------------------------------------------------*/
00055 /* Private variables ---------------------------------------------------------*/
00056 /* Private constants ---------------------------------------------------------*/
00057 /** @addtogroup UTILS_LL_Private_Constants
00058   * @{
00059   */
00060
00061 /* Defines used for PLL range */
00062 #define UTILS_PLL_OUTPUT_MAX        72000000U    /*!< Frequency max for PLL output, in Hz  */
00063
00064 /* Defines used for HSE range */
00065 #define UTILS_HSE_FREQUENCY_MIN      4000000U       /*!< Frequency min for HSE frequency, in Hz   */
00066 #define UTILS_HSE_FREQUENCY_MAX     32000000U       /*!< Frequency max for HSE frequency, in Hz   */
00067
00068 /* Defines used for FLASH latency according to SYSCLK Frequency */
00069 #define UTILS_LATENCY1_FREQ         24000000U        /*!< SYSCLK frequency to set FLASH latency 1 */
00070 #define UTILS_LATENCY2_FREQ         48000000U        /*!< SYSCLK frequency to set FLASH latency 2 */
00071 /**
00072   * @}
00073   */
00074 /* Private macros ------------------------------------------------------------*/
00075 /** @addtogroup UTILS_LL_Private_Macros
00076   * @{
00077   */
00078 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
00079                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
00080                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
00081                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
00082                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
00083                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
00084                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
00085                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
00086                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
00087
00088 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
00089                                       || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
00090                                       || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
00091                                       || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
00092                                       || ((__VALUE__) == LL_RCC_APB1_DIV_16))
00093
00094 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
00095                                       || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
00096                                       || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
00097                                       || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
00098                                       || ((__VALUE__) == LL_RCC_APB2_DIV_16))
00099
00100 #define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
00101                                           || ((__VALUE__) == LL_RCC_PLL_MUL_3) \
00102                                           || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
00103                                           || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
00104                                           || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
00105                                           || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
00106                                           || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
00107                                           || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
00108                                           || ((__VALUE__) == LL_RCC_PLL_MUL_10) \
00109                                           || ((__VALUE__) == LL_RCC_PLL_MUL_11) \
00110                                           || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
00111                                           || ((__VALUE__) == LL_RCC_PLL_MUL_13) \
00112                                           || ((__VALUE__) == LL_RCC_PLL_MUL_14) \
00113                                           || ((__VALUE__) == LL_RCC_PLL_MUL_15) \
00114                                           || ((__VALUE__) == LL_RCC_PLL_MUL_16))
00115
00116 #define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_2)   || \
00117                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_3)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_4)   || \
00118                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_5)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_6)   || \
00119                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_7)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_8)   || \
00120                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_9)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_10)  || \
00121                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12)  || \
00122                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14)  || \
00123                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
00124
00125 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
00126
00127
00128 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
00129                                         || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
00130
00131 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
00132 /**
00133   * @}
00134   */
00135 /* Private function prototypes -----------------------------------------------*/
00136 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
00137   * @{
00138   */
00139 static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
00140                                                LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
00141 #if defined(FLASH_ACR_LATENCY)
00142 static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
00143 #endif /* FLASH_ACR_LATENCY */
00144 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00145 static ErrorStatus UTILS_PLL_IsBusy(void);
00146 /**
00147   * @}
00148   */
00149
00150 /* Exported functions --------------------------------------------------------*/
00151 /** @addtogroup UTILS_LL_Exported_Functions
00152   * @{
00153   */
00154
00155 /** @addtogroup UTILS_LL_EF_DELAY
00156   * @{
00157   */
00158
00159 /**
00160   * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
00161   * @note   When a RTOS is used, it is recommended to avoid changing the Systick
00162   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00163   * @param  HCLKFrequency HCLK frequency in Hz
00164   * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
00165   * @retval None
00166   */
00167 void LL_Init1msTick(uint32_t HCLKFrequency)
00168 {
00169   /* Use frequency provided in argument */
00170   LL_InitTick(HCLKFrequency, 1000U);
00171 }
00172
00173 /**
00174   * @brief  This function provides accurate delay (in milliseconds) based
00175   *         on SysTick counter flag
00176   * @note   When a RTOS is used, it is recommended to avoid using blocking delay
00177   *         and use rather osDelay service.
00178   * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
00179   *         will configure Systick to 1ms
00180   * @param  Delay specifies the delay time length, in milliseconds.
00181   * @retval None
00182   */
00183 void LL_mDelay(uint32_t Delay)
00184 {
00185   __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
00186   /* Add this code to indicate that local variable is not used */
00187   ((void)tmp);
00188
00189   /* Add a period to guaranty minimum wait */
00190   if (Delay < LL_MAX_DELAY)
00191   {
00192     Delay++;
00193   }
00194
00195   while (Delay)
00196   {
00197     if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
00198     {
00199       Delay--;
00200     }
00201   }
00202 }
00203
00204 /**
00205   * @}
00206   */
00207
00208 /** @addtogroup UTILS_EF_SYSTEM
00209   *  @brief    System Configuration functions
00210   *
00211   @verbatim
00212  ===============================================================================
00213            ##### System Configuration functions #####
00214  ===============================================================================
00215     [..]
00216          System, AHB and APB buses clocks configuration
00217
00218          (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72000000 Hz.
00219   @endverbatim
00220   @internal
00221              Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
00222              (++) +-----------------------------------------------+
00223              (++) | Latency       | SYSCLK clock frequency (MHz)  |
00224              (++) |---------------|-------------------------------|
00225              (++) |0WS(1CPU cycle)|       0 < SYSCLK <= 24        |
00226              (++) |---------------|-------------------------------|
00227              (++) |1WS(2CPU cycle)|      24 < SYSCLK <= 48        |
00228              (++) |---------------|-------------------------------|
00229              (++) |2WS(3CPU cycle)|      48 < SYSCLK <= 72        |
00230              (++) +-----------------------------------------------+
00231   @endinternal
00232   * @{
00233   */
00234
00235 /**
00236   * @brief  This function sets directly SystemCoreClock CMSIS variable.
00237   * @note   Variable can be calculated also through SystemCoreClockUpdate function.
00238   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
00239   * @retval None
00240   */
00241 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
00242 {
00243   /* HCLK clock frequency */
00244   SystemCoreClock = HCLKFrequency;
00245 }
00246
00247 /**
00248   * @brief  This function configures system clock with HSI as clock source of the PLL
00249   * @note   The application need to ensure that PLL is disabled.
00250   * @note   Function is based on the following formula:
00251   *         - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
00252   *         - PREDIV: Set to 2 for few devices
00253   *         - PLLMUL: The application software must set correctly the PLL multiplication factor to
00254   *                   not exceed 72MHz
00255   * @note   FLASH latency can be modified through this function.
00256   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00257   *                             the configuration information for the PLL.
00258   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00259   *                             the configuration information for the BUS prescalers.
00260   * @retval An ErrorStatus enumeration value:
00261   *          - SUCCESS: Max frequency configuration done
00262   *          - ERROR: Max frequency configuration not done
00263   */
00264 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00265                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00266 {
00267   ErrorStatus status = SUCCESS;
00268   uint32_t pllfreq = 0U;
00269
00270   /* Check if one of the PLL is enabled */
00271   if (UTILS_PLL_IsBusy() == SUCCESS)
00272   {
00273 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
00274     /* Check PREDIV value */
00275     assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
00276 #else
00277     /* Force PREDIV value to 2 */
00278     UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
00279 #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
00280     /* Calculate the new PLL output frequency */
00281     pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
00282
00283     /* Enable HSI if not enabled */
00284     if (LL_RCC_HSI_IsReady() != 1U)
00285     {
00286       LL_RCC_HSI_Enable();
00287       while (LL_RCC_HSI_IsReady() != 1U)
00288       {
00289         /* Wait for HSI ready */
00290       }
00291     }
00292
00293     /* Configure PLL */
00294 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
00295     LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
00296 #else
00297     LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
00298 #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
00299
00300     /* Enable PLL and switch system clock to PLL */
00301     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
00302   }
00303   else
00304   {
00305     /* Current PLL configuration cannot be modified */
00306     status = ERROR;
00307   }
00308
00309   return status;
00310 }
00311
00312 /**
00313   * @brief  This function configures system clock with HSE as clock source of the PLL
00314   * @note   The application need to ensure that PLL is disabled.
00315   * @note   Function is based on the following formula:
00316   *         - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
00317   *         - PREDIV: Set to 2 for few devices
00318   *         - PLLMUL: The application software must set correctly the PLL multiplication factor to
00319   *                   not exceed @ref UTILS_PLL_OUTPUT_MAX
00320   * @note   FLASH latency can be modified through this function.
00321   * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 32000000
00322   * @param  HSEBypass This parameter can be one of the following values:
00323   *         @arg @ref LL_UTILS_HSEBYPASS_ON
00324   *         @arg @ref LL_UTILS_HSEBYPASS_OFF
00325   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00326   *                             the configuration information for the PLL.
00327   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00328   *                             the configuration information for the BUS prescalers.
00329   * @retval An ErrorStatus enumeration value:
00330   *          - SUCCESS: Max frequency configuration done
00331   *          - ERROR: Max frequency configuration not done
00332   */
00333 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
00334                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00335 {
00336   ErrorStatus status = SUCCESS;
00337   uint32_t pllfreq = 0U;
00338
00339   /* Check the parameters */
00340   assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
00341   assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
00342
00343   /* Check if one of the PLL is enabled */
00344   if (UTILS_PLL_IsBusy() == SUCCESS)
00345   {
00346     /* Check PREDIV value */
00347 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
00348     assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
00349 #else
00350     assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
00351 #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
00352
00353     /* Calculate the new PLL output frequency */
00354     pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
00355
00356     /* Enable HSE if not enabled */
00357     if (LL_RCC_HSE_IsReady() != 1U)
00358     {
00359       /* Check if need to enable HSE bypass feature or not */
00360       if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
00361       {
00362         LL_RCC_HSE_EnableBypass();
00363       }
00364       else
00365       {
00366         LL_RCC_HSE_DisableBypass();
00367       }
00368
00369       /* Enable HSE */
00370       LL_RCC_HSE_Enable();
00371       while (LL_RCC_HSE_IsReady() != 1U)
00372       {
00373         /* Wait for HSE ready */
00374       }
00375     }
00376
00377       /* Configure PLL */
00378 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
00379       LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
00380 #else
00381     LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
00382 #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
00383
00384     /* Enable PLL and switch system clock to PLL */
00385     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
00386   }
00387   else
00388   {
00389     /* Current PLL configuration cannot be modified */
00390     status = ERROR;
00391   }
00392
00393   return status;
00394 }
00395
00396 /**
00397   * @}
00398   */
00399
00400 /**
00401   * @}
00402   */
00403
00404 /** @addtogroup UTILS_LL_Private_Functions
00405   * @{
00406   */
00407 /**
00408   * @brief  Update number of Flash wait states in line with new frequency and current
00409             voltage range.
00410   * @param  Frequency  SYSCLK frequency
00411   * @retval An ErrorStatus enumeration value:
00412   *          - SUCCESS: Latency has been modified
00413   *          - ERROR: Latency cannot be modified
00414   */
00415 #if defined(FLASH_ACR_LATENCY)
00416 static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
00417 {
00418   ErrorStatus status = SUCCESS;
00419
00420   uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */
00421
00422   /* Frequency cannot be equal to 0 */
00423   if (Frequency == 0U)
00424   {
00425     status = ERROR;
00426   }
00427   else
00428   {
00429     if (Frequency > UTILS_LATENCY2_FREQ)
00430     {
00431       /* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
00432       latency = LL_FLASH_LATENCY_2;
00433     }
00434     else
00435     {
00436       if (Frequency > UTILS_LATENCY1_FREQ)
00437       {
00438         /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
00439         latency = LL_FLASH_LATENCY_1;
00440       }
00441       /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
00442     }
00443
00444     LL_FLASH_SetLatency(latency);
00445
00446     /* Check that the new number of wait states is taken into account to access the Flash
00447        memory by reading the FLASH_ACR register */
00448     if (LL_FLASH_GetLatency() != latency)
00449     {
00450       status = ERROR;
00451     }
00452   }
00453   return status;
00454 }
00455 #endif /* FLASH_ACR_LATENCY */
00456
00457 /**
00458   * @brief  Function to check that PLL can be modified
00459   * @param  PLL_InputFrequency  PLL input frequency (in Hz)
00460   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00461   *                             the configuration information for the PLL.
00462   * @retval PLL output frequency (in Hz)
00463   */
00464 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
00465 {
00466   uint32_t pllfreq = 0U;
00467
00468   /* Check the parameters */
00469   assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
00470
00471   /* Check different PLL parameters according to RM                          */
00472   /* The application software must set correctly the PLL multiplication factor to
00473      not exceed @ref UTILS_PLL_OUTPUT_MAX */
00474 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
00475   pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
00476 #else
00477   pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
00478 #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
00479   assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
00480
00481   return pllfreq;
00482 }
00483
00484 /**
00485   * @brief  Function to check that PLL can be modified
00486   * @retval An ErrorStatus enumeration value:
00487   *          - SUCCESS: PLL modification can be done
00488   *          - ERROR: PLL is busy
00489   */
00490 static ErrorStatus UTILS_PLL_IsBusy(void)
00491 {
00492   ErrorStatus status = SUCCESS;
00493
00494   /* Check if PLL is busy*/
00495   if (LL_RCC_PLL_IsReady() != 0U)
00496   {
00497     /* PLL configuration cannot be modified */
00498     status = ERROR;
00499   }
00500
00501   return status;
00502 }
00503
00504 /**
00505   * @brief  Function to enable PLL and switch system clock to PLL
00506   * @param  SYSCLK_Frequency SYSCLK frequency
00507   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00508   *                             the configuration information for the BUS prescalers.
00509   * @retval An ErrorStatus enumeration value:
00510   *          - SUCCESS: No problem to switch system to PLL
00511   *          - ERROR: Problem to switch system to PLL
00512   */
00513 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00514 {
00515   ErrorStatus status = SUCCESS;
00516   uint32_t sysclk_frequency_current = 0U;
00517
00518   assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
00519   assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
00520   assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
00521
00522   /* Calculate current SYSCLK frequency */
00523   sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSITION_HPRE]);
00524
00525   /* Increasing the number of wait states because of higher CPU frequency */
00526   if (sysclk_frequency_current < SYSCLK_Frequency)
00527   {
00528     /* Set FLASH latency to highest latency */
00529     status = UTILS_SetFlashLatency(SYSCLK_Frequency);
00530   }
00531
00532   /* Update system clock configuration */
00533   if (status == SUCCESS)
00534   {
00535     /* Enable PLL */
00536     LL_RCC_PLL_Enable();
00537     while (LL_RCC_PLL_IsReady() != 1U)
00538     {
00539       /* Wait for PLL ready */
00540     }
00541
00542     /* Sysclk activation on the main PLL */
00543     LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
00544     LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
00545     while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
00546     {
00547       /* Wait for system clock switch to PLL */
00548     }
00549
00550     /* Set APB1 & APB2 prescaler*/
00551     LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
00552     LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
00553   }
00554
00555   /* Decreasing the number of wait states because of lower CPU frequency */
00556   if (sysclk_frequency_current > SYSCLK_Frequency)
00557   {
00558     /* Set FLASH latency to lowest latency */
00559     status = UTILS_SetFlashLatency(SYSCLK_Frequency);
00560   }
00561
00562   /* Update SystemCoreClock variable */
00563   if (status == SUCCESS)
00564   {
00565     LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
00566   }
00567
00568   return status;
00569 }
00570
00571 /**
00572   * @}
00573   */
00574
00575 /**
00576   * @}
00577   */
00578
00579 /**
00580   * @}
00581   */
00582
00583 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_utils.h Source File

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stm32f3xx_ll_utils.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_utils.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UTILS LL module.
00006   @verbatim
00007   ==============================================================================
00008                      ##### How to use this driver #####
00009   ==============================================================================
00010     [..]
00011     The LL UTILS driver contains a set of generic APIs that can be
00012     used by user:
00013       (+) Device electronic signature
00014       (+) Timing functions
00015       (+) PLL configuration functions
00016
00017   @endverbatim
00018   ******************************************************************************
00019   * @attention
00020   *
00021   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00022   *
00023   * Redistribution and use in source and binary forms, with or without modification,
00024   * are permitted provided that the following conditions are met:
00025   *   1. Redistributions of source code must retain the above copyright notice,
00026   *      this list of conditions and the following disclaimer.
00027   *   2. Redistributions in binary form must reproduce the above copyright notice,
00028   *      this list of conditions and the following disclaimer in the documentation
00029   *      and/or other materials provided with the distribution.
00030   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00031   *      may be used to endorse or promote products derived from this software
00032   *      without specific prior written permission.
00033   *
00034   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00035   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00036   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00037   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00038   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00039   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00040   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00041   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00042   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00043   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00044   *
00045   ******************************************************************************
00046   */
00047
00048 /* Define to prevent recursive inclusion -------------------------------------*/
00049 #ifndef __STM32F3xx_LL_UTILS_H
00050 #define __STM32F3xx_LL_UTILS_H
00051
00052 #ifdef __cplusplus
00053 extern "C" {
00054 #endif
00055
00056 /* Includes ------------------------------------------------------------------*/
00057 #include "stm32f3xx.h"
00058
00059 /** @addtogroup STM32F3xx_LL_Driver
00060   * @{
00061   */
00062
00063 /** @defgroup UTILS_LL UTILS
00064   * @{
00065   */
00066
00067 /* Private types -------------------------------------------------------------*/
00068 /* Private variables ---------------------------------------------------------*/
00069
00070 /* Private constants ---------------------------------------------------------*/
00071 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
00072   * @{
00073   */
00074
00075 /* Max delay can be used in LL_mDelay */
00076 #define LL_MAX_DELAY                  0xFFFFFFFFU
00077
00078 /**
00079  * @brief Unique device ID register base address
00080  */
00081 #define UID_BASE_ADDRESS              UID_BASE
00082
00083 /**
00084  * @brief Flash size data register base address
00085  */
00086 #define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
00087
00088 /**
00089  * @brief Package data register base address
00090  */
00091 #define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
00092
00093 /**
00094   * @}
00095   */
00096
00097 /* Private macros ------------------------------------------------------------*/
00098 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
00099   * @{
00100   */
00101 /**
00102   * @}
00103   */
00104 /* Exported types ------------------------------------------------------------*/
00105 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
00106   * @{
00107   */
00108 /**
00109   * @brief  UTILS PLL structure definition
00110   */
00111 typedef struct
00112 {
00113   uint32_t PLLMul;   /*!< Multiplication factor for PLL VCO input clock.
00114                           This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
00115
00116                           This feature can be modified afterwards using unitary function
00117                           @ref LL_RCC_PLL_ConfigDomain_SYS(). */
00118
00119 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
00120   uint32_t PLLDiv;   /*!< Division factor for PLL VCO output clock.
00121                           This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
00122
00123                           This feature can be modified afterwards using unitary function
00124                           @ref LL_RCC_PLL_ConfigDomain_SYS(). */
00125 #else
00126   uint32_t Prediv;   /*!< Division factor for HSE used as PLL clock source.
00127                           This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
00128
00129                           This feature can be modified afterwards using unitary function
00130                           @ref LL_RCC_PLL_ConfigDomain_SYS(). */
00131 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
00132 } LL_UTILS_PLLInitTypeDef;
00133
00134 /**
00135   * @brief  UTILS System, AHB and APB buses clock configuration structure definition
00136   */
00137 typedef struct
00138 {
00139   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
00140                                        This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
00141
00142                                        This feature can be modified afterwards using unitary function
00143                                        @ref LL_RCC_SetAHBPrescaler(). */
00144
00145   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00146                                        This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
00147
00148                                        This feature can be modified afterwards using unitary function
00149                                        @ref LL_RCC_SetAPB1Prescaler(). */
00150
00151   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
00152                                        This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
00153
00154                                        This feature can be modified afterwards using unitary function
00155                                        @ref LL_RCC_SetAPB2Prescaler(). */
00156
00157 } LL_UTILS_ClkInitTypeDef;
00158
00159 /**
00160   * @}
00161   */
00162
00163 /* Exported constants --------------------------------------------------------*/
00164 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
00165   * @{
00166   */
00167
00168 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
00169   * @{
00170   */
00171 #define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
00172 #define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
00173 /**
00174   * @}
00175   */
00176
00177 /**
00178   * @}
00179   */
00180
00181 /* Exported macro ------------------------------------------------------------*/
00182
00183 /* Exported functions --------------------------------------------------------*/
00184 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
00185   * @{
00186   */
00187
00188 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
00189   * @{
00190   */
00191
00192 /**
00193   * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
00194   * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
00195   */
00196 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
00197 {
00198   return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
00199 }
00200
00201 /**
00202   * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
00203   * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
00204   */
00205 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
00206 {
00207   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
00208 }
00209
00210 /**
00211   * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
00212   * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
00213   */
00214 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
00215 {
00216   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
00217 }
00218
00219 /**
00220   * @brief  Get Flash memory size
00221   * @note   This bitfield indicates the size of the device Flash memory expressed in
00222   *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
00223   * @retval FLASH_SIZE[15:0]: Flash memory size
00224   */
00225 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
00226 {
00227   return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
00228 }
00229
00230
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup UTILS_LL_EF_DELAY DELAY
00236   * @{
00237   */
00238
00239 /**
00240   * @brief  This function configures the Cortex-M SysTick source of the time base.
00241   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
00242   * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
00243   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00244   * @param  Ticks Number of ticks
00245   * @retval None
00246   */
00247 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
00248 {
00249   /* Configure the SysTick to have interrupt in 1ms time base */
00250   SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
00251   SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
00252   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
00253                    SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
00254 }
00255
00256 void        LL_Init1msTick(uint32_t HCLKFrequency);
00257 void        LL_mDelay(uint32_t Delay);
00258
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup UTILS_EF_SYSTEM SYSTEM
00264   * @{
00265   */
00266
00267 void        LL_SetSystemCoreClock(uint32_t HCLKFrequency);
00268 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00269                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00270 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
00271                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00272
00273 /**
00274   * @}
00275   */
00276
00277 /**
00278   * @}
00279   */
00280
00281 /**
00282   * @}
00283   */
00284
00285 /**
00286   * @}
00287   */
00288
00289 #ifdef __cplusplus
00290 }
00291 #endif
00292
00293 #endif /* __STM32F3xx_LL_UTILS_H */
00294
00295 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jun 13 2017 08:20:10 for STM32F373xC HAL User Manual by doxygen 1.7.6.1


STM32F373xC HAL User Manual: stm32f3xx_ll_wwdg.h Source File

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stm32f3xx_ll_wwdg.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f3xx_ll_wwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of WWDG LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F3xx_LL_WWDG_H
00038 #define __STM32F3xx_LL_WWDG_H
00039
00040 #ifdef __cplusplus
00041 extern "C" {
00042 #endif
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f3xx.h"
00046
00047 /** @addtogroup STM32F3xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined (WWDG)
00052
00053 /** @defgroup WWDG_LL WWDG
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059
00060 /* Private constants ---------------------------------------------------------*/
00061
00062 /* Private macros ------------------------------------------------------------*/
00063
00064 /* Exported types ------------------------------------------------------------*/
00065 /* Exported constants --------------------------------------------------------*/
00066 /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
00067   * @{
00068   */
00069
00070
00071 /** @defgroup WWDG_LL_EC_IT IT Defines
00072   * @brief    IT defines which can be used with LL_WWDG_ReadReg and  LL_WWDG_WriteReg functions
00073   * @{
00074   */
00075 #define LL_WWDG_CFR_EWI                    WWDG_CFR_EWI
00076 /**
00077   * @}
00078   */
00079
00080 /** @defgroup WWDG_LL_EC_PRESCALER  PRESCALER
00081 * @{
00082 */
00083 #define LL_WWDG_PRESCALER_1                0x00000000U                                             /*!< WWDG counter clock = (PCLK1/4096)/1 */
00084 #define LL_WWDG_PRESCALER_2                WWDG_CFR_WDGTB_0                                        /*!< WWDG counter clock = (PCLK1/4096)/2 */
00085 #define LL_WWDG_PRESCALER_4                WWDG_CFR_WDGTB_1                                        /*!< WWDG counter clock = (PCLK1/4096)/4 */
00086 #define LL_WWDG_PRESCALER_8                (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)                   /*!< WWDG counter clock = (PCLK1/4096)/8 */
00087 /**
00088   * @}
00089   */
00090
00091 /**
00092   * @}
00093   */
00094
00095 /* Exported macro ------------------------------------------------------------*/
00096 /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
00097   * @{
00098   */
00099 /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
00100   * @{
00101   */
00102 /**
00103   * @brief  Write a value in WWDG register
00104   * @param  __INSTANCE__ WWDG Instance
00105   * @param  __REG__ Register to be written
00106   * @param  __VALUE__ Value to be written in the register
00107   * @retval None
00108   */
00109 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00110
00111 /**
00112   * @brief  Read a value in WWDG register
00113   * @param  __INSTANCE__ WWDG Instance
00114   * @param  __REG__ Register to be read
00115   * @retval Register value
00116   */
00117 #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00118 /**
00119   * @}
00120   */
00121
00122
00123 /**
00124   * @}
00125   */
00126
00127 /* Exported functions --------------------------------------------------------*/
00128 /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
00129   * @{
00130   */
00131
00132 /** @defgroup WWDG_LL_EF_Configuration Configuration
00133   * @{
00134   */
00135 /**
00136   * @brief  Enable Window Watchdog. The watchdog is always disabled after a reset.
00137   * @note   It is enabled by setting the WDGA bit in the WWDG_CR register,
00138   *         then it cannot be disabled again except by a reset.
00139   *         This bit is set by software and only cleared by hardware after a reset.
00140   *         When WDGA = 1, the watchdog can generate a reset.
00141   * @rmtoll CR           WDGA          LL_WWDG_Enable
00142   * @param  WWDGx WWDG Instance
00143   * @retval None
00144   */
00145 __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
00146 {
00147   SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
00148 }
00149
00150 /**
00151   * @brief  Checks if Window Watchdog is enabled
00152   * @rmtoll CR           WDGA          LL_WWDG_IsEnabled
00153   * @param  WWDGx WWDG Instance
00154   * @retval State of bit (1 or 0).
00155   */
00156 __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
00157 {
00158   return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
00159 }
00160
00161 /**
00162   * @brief  Set the Watchdog counter value to provided value (7-bits T[6:0])
00163   * @note   When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
00164   *         This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
00165   *         A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
00166   *         Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
00167   * @rmtoll CR           T             LL_WWDG_SetCounter
00168   * @param  WWDGx WWDG Instance
00169   * @param  Counter 0..0x7F (7 bit counter value)
00170   * @retval None
00171   */
00172 __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
00173 {
00174   MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
00175 }
00176
00177 /**
00178   * @brief  Return current Watchdog Counter Value (7 bits counter value)
00179   * @rmtoll CR           T             LL_WWDG_GetCounter
00180   * @param  WWDGx WWDG Instance
00181   * @retval 7 bit Watchdog Counter value
00182   */
00183 __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
00184 {
00185   return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
00186 }
00187
00188 /**
00189   * @brief  Set the time base of the prescaler (WDGTB).
00190   * @note   Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
00191   *         is decremented every (4096 x 2expWDGTB) PCLK cycles
00192   * @rmtoll CFR          WDGTB         LL_WWDG_SetPrescaler
00193   * @param  WWDGx WWDG Instance
00194   * @param  Prescaler This parameter can be one of the following values:
00195   *         @arg @ref LL_WWDG_PRESCALER_1
00196   *         @arg @ref LL_WWDG_PRESCALER_2
00197   *         @arg @ref LL_WWDG_PRESCALER_4
00198   *         @arg @ref LL_WWDG_PRESCALER_8
00199   * @retval None
00200   */
00201 __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
00202 {
00203   MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
00204 }
00205
00206 /**
00207   * @brief  Return current Watchdog Prescaler Value
00208   * @rmtoll CFR          WDGTB         LL_WWDG_GetPrescaler
00209   * @param  WWDGx WWDG Instance
00210   * @retval Returned value can be one of the following values:
00211   *         @arg @ref LL_WWDG_PRESCALER_1
00212   *         @arg @ref LL_WWDG_PRESCALER_2
00213   *         @arg @ref LL_WWDG_PRESCALER_4
00214   *         @arg @ref LL_WWDG_PRESCALER_8
00215   */
00216 __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
00217 {
00218   return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
00219 }
00220
00221 /**
00222   * @brief  Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
00223   * @note   This window value defines when write in the WWDG_CR register
00224   *         to program Watchdog counter is allowed.
00225   *         Watchdog counter value update must occur only when the counter value
00226   *         is lower than the Watchdog window register value.
00227   *         Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
00228   *         (in the control register) is refreshed before the downcounter has reached
00229   *         the watchdog window register value.
00230   *         Physically is possible to set the Window lower then 0x40 but it is not recommended.
00231   *         To generate an immediate reset, it is possible to set the Counter lower than 0x40.
00232   * @rmtoll CFR          W             LL_WWDG_SetWindow
00233   * @param  WWDGx WWDG Instance
00234   * @param  Window 0x00..0x7F (7 bit Window value)
00235   * @retval None
00236   */
00237 __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
00238 {
00239   MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
00240 }
00241
00242 /**
00243   * @brief  Return current Watchdog Window Value (7 bits value)
00244   * @rmtoll CFR          W             LL_WWDG_GetWindow
00245   * @param  WWDGx WWDG Instance
00246   * @retval 7 bit Watchdog Window value
00247   */
00248 __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
00249 {
00250   return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
00251 }
00252
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
00258   * @{
00259   */
00260 /**
00261   * @brief  Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
00262   * @note   This bit is set by hardware when the counter has reached the value 0x40.
00263   *         It must be cleared by software by writing 0.
00264   *         A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
00265   * @rmtoll SR           EWIF          LL_WWDG_IsActiveFlag_EWKUP
00266   * @param  WWDGx WWDG Instance
00267   * @retval State of bit (1 or 0).
00268   */
00269 __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
00270 {
00271   return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
00272 }
00273
00274 /**
00275   * @brief  Clear WWDG Early Wakeup Interrupt Flag (EWIF)
00276   * @rmtoll SR           EWIF          LL_WWDG_ClearFlag_EWKUP
00277   * @param  WWDGx WWDG Instance
00278   * @retval None
00279   */
00280 __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
00281 {
00282   WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
00283 }
00284
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup WWDG_LL_EF_IT_Management IT_Management
00290   * @{
00291   */
00292 /**
00293   * @brief  Enable the Early Wakeup Interrupt.
00294   * @note   When set, an interrupt occurs whenever the counter reaches value 0x40.
00295   *         This interrupt is only cleared by hardware after a reset
00296   * @rmtoll CFR          EWI           LL_WWDG_EnableIT_EWKUP
00297   * @param  WWDGx WWDG Instance
00298   * @retval None
00299   */
00300 __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
00301 {
00302   SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
00303 }
00304
00305 /**
00306   * @brief  Check if Early Wakeup Interrupt is enabled
00307   * @rmtoll CFR          EWI           LL_WWDG_IsEnabledIT_EWKUP
00308   * @param  WWDGx WWDG Instance
00309   * @retval State of bit (1 or 0).
00310   */
00311 __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
00312 {
00313   return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
00314 }
00315
00316 /**
00317   * @}
00318   */
00319
00320 /**
00321   * @}
00322   */
00323
00324 /**
00325   * @}
00326   */
00327
00328 #endif /* WWDG */
00329
00330 /**
00331   * @}
00332   */
00333
00334 #ifdef __cplusplus
00335 }
00336 #endif
00337
00338 #endif /* __STM32F3xx_LL_WWDG_H */
00339
00340 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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